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1da177e4 LT |
1 | /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*- |
2 | */ | |
0d6aa60b | 3 | /* |
bc54fd1a | 4 | * |
1da177e4 LT |
5 | * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. |
6 | * All Rights Reserved. | |
bc54fd1a DA |
7 | * |
8 | * Permission is hereby granted, free of charge, to any person obtaining a | |
9 | * copy of this software and associated documentation files (the | |
10 | * "Software"), to deal in the Software without restriction, including | |
11 | * without limitation the rights to use, copy, modify, merge, publish, | |
12 | * distribute, sub license, and/or sell copies of the Software, and to | |
13 | * permit persons to whom the Software is furnished to do so, subject to | |
14 | * the following conditions: | |
15 | * | |
16 | * The above copyright notice and this permission notice (including the | |
17 | * next paragraph) shall be included in all copies or substantial portions | |
18 | * of the Software. | |
19 | * | |
20 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS | |
21 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
22 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. | |
23 | * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR | |
24 | * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, | |
25 | * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE | |
26 | * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. | |
27 | * | |
0d6aa60b | 28 | */ |
1da177e4 LT |
29 | |
30 | #ifndef _I915_DRV_H_ | |
31 | #define _I915_DRV_H_ | |
32 | ||
585fb111 | 33 | #include "i915_reg.h" |
79e53945 | 34 | #include "intel_bios.h" |
0839ccb8 | 35 | #include <linux/io-mapping.h> |
585fb111 | 36 | |
1da177e4 LT |
37 | /* General customization: |
38 | */ | |
39 | ||
40 | #define DRIVER_AUTHOR "Tungsten Graphics, Inc." | |
41 | ||
42 | #define DRIVER_NAME "i915" | |
43 | #define DRIVER_DESC "Intel Graphics" | |
673a394b | 44 | #define DRIVER_DATE "20080730" |
1da177e4 | 45 | |
317c35d1 JB |
46 | enum pipe { |
47 | PIPE_A = 0, | |
48 | PIPE_B, | |
49 | }; | |
50 | ||
80824003 JB |
51 | enum plane { |
52 | PLANE_A = 0, | |
53 | PLANE_B, | |
54 | }; | |
55 | ||
52440211 KP |
56 | #define I915_NUM_PIPE 2 |
57 | ||
1da177e4 LT |
58 | /* Interface history: |
59 | * | |
60 | * 1.1: Original. | |
0d6aa60b DA |
61 | * 1.2: Add Power Management |
62 | * 1.3: Add vblank support | |
de227f5f | 63 | * 1.4: Fix cmdbuffer path, add heap destroy |
702880f2 | 64 | * 1.5: Add vblank pipe configuration |
2228ed67 MD |
65 | * 1.6: - New ioctl for scheduling buffer swaps on vertical blank |
66 | * - Support vertical blank on secondary display pipe | |
1da177e4 LT |
67 | */ |
68 | #define DRIVER_MAJOR 1 | |
2228ed67 | 69 | #define DRIVER_MINOR 6 |
1da177e4 LT |
70 | #define DRIVER_PATCHLEVEL 0 |
71 | ||
673a394b EA |
72 | #define WATCH_COHERENCY 0 |
73 | #define WATCH_BUF 0 | |
74 | #define WATCH_EXEC 0 | |
75 | #define WATCH_LRU 0 | |
76 | #define WATCH_RELOC 0 | |
77 | #define WATCH_INACTIVE 0 | |
78 | #define WATCH_PWRITE 0 | |
79 | ||
71acb5eb DA |
80 | #define I915_GEM_PHYS_CURSOR_0 1 |
81 | #define I915_GEM_PHYS_CURSOR_1 2 | |
82 | #define I915_GEM_PHYS_OVERLAY_REGS 3 | |
83 | #define I915_MAX_PHYS_OBJECT (I915_GEM_PHYS_OVERLAY_REGS) | |
84 | ||
85 | struct drm_i915_gem_phys_object { | |
86 | int id; | |
87 | struct page **page_list; | |
88 | drm_dma_handle_t *handle; | |
89 | struct drm_gem_object *cur_obj; | |
90 | }; | |
91 | ||
1da177e4 | 92 | typedef struct _drm_i915_ring_buffer { |
1da177e4 LT |
93 | unsigned long Size; |
94 | u8 *virtual_start; | |
95 | int head; | |
96 | int tail; | |
97 | int space; | |
98 | drm_local_map_t map; | |
673a394b | 99 | struct drm_gem_object *ring_obj; |
1da177e4 LT |
100 | } drm_i915_ring_buffer_t; |
101 | ||
102 | struct mem_block { | |
103 | struct mem_block *next; | |
104 | struct mem_block *prev; | |
105 | int start; | |
106 | int size; | |
6c340eac | 107 | struct drm_file *file_priv; /* NULL: free, -1: heap, other: real files */ |
1da177e4 LT |
108 | }; |
109 | ||
0a3e67a4 JB |
110 | struct opregion_header; |
111 | struct opregion_acpi; | |
112 | struct opregion_swsci; | |
113 | struct opregion_asle; | |
114 | ||
8ee1c3db MG |
115 | struct intel_opregion { |
116 | struct opregion_header *header; | |
117 | struct opregion_acpi *acpi; | |
118 | struct opregion_swsci *swsci; | |
119 | struct opregion_asle *asle; | |
120 | int enabled; | |
121 | }; | |
122 | ||
7c1c2871 DA |
123 | struct drm_i915_master_private { |
124 | drm_local_map_t *sarea; | |
125 | struct _drm_i915_sarea *sarea_priv; | |
126 | }; | |
de151cf6 JB |
127 | #define I915_FENCE_REG_NONE -1 |
128 | ||
129 | struct drm_i915_fence_reg { | |
130 | struct drm_gem_object *obj; | |
131 | }; | |
7c1c2871 | 132 | |
9b9d172d | 133 | struct sdvo_device_mapping { |
134 | u8 dvo_port; | |
135 | u8 slave_addr; | |
136 | u8 dvo_wiring; | |
137 | u8 initialized; | |
138 | }; | |
139 | ||
63eeaf38 JB |
140 | struct drm_i915_error_state { |
141 | u32 eir; | |
142 | u32 pgtbl_er; | |
143 | u32 pipeastat; | |
144 | u32 pipebstat; | |
145 | u32 ipeir; | |
146 | u32 ipehr; | |
147 | u32 instdone; | |
148 | u32 acthd; | |
149 | u32 instpm; | |
150 | u32 instps; | |
151 | u32 instdone1; | |
152 | u32 seqno; | |
153 | struct timeval time; | |
154 | }; | |
155 | ||
e70236a8 JB |
156 | struct drm_i915_display_funcs { |
157 | void (*dpms)(struct drm_crtc *crtc, int mode); | |
158 | bool (*fbc_enabled)(struct drm_crtc *crtc); | |
159 | void (*enable_fbc)(struct drm_crtc *crtc, unsigned long interval); | |
160 | void (*disable_fbc)(struct drm_device *dev); | |
161 | int (*get_display_clock_speed)(struct drm_device *dev); | |
162 | int (*get_fifo_size)(struct drm_device *dev, int plane); | |
163 | void (*update_wm)(struct drm_device *dev, int planea_clock, | |
164 | int planeb_clock, int sr_hdisplay, int pixel_size); | |
165 | /* clock updates for mode set */ | |
166 | /* cursor updates */ | |
167 | /* render clock increase/decrease */ | |
168 | /* display clock increase/decrease */ | |
169 | /* pll clock increase/decrease */ | |
170 | /* clock gating init */ | |
171 | }; | |
172 | ||
02e792fb DV |
173 | struct intel_overlay; |
174 | ||
cfdf1fa2 KH |
175 | struct intel_device_info { |
176 | u8 is_mobile : 1; | |
177 | u8 is_i8xx : 1; | |
178 | u8 is_i915g : 1; | |
179 | u8 is_i9xx : 1; | |
180 | u8 is_i945gm : 1; | |
181 | u8 is_i965g : 1; | |
182 | u8 is_i965gm : 1; | |
183 | u8 is_g33 : 1; | |
184 | u8 need_gfx_hws : 1; | |
185 | u8 is_g4x : 1; | |
186 | u8 is_pineview : 1; | |
187 | u8 is_ironlake : 1; | |
188 | u8 has_fbc : 1; | |
189 | u8 has_rc6 : 1; | |
190 | u8 has_pipe_cxsr : 1; | |
191 | u8 has_hotplug : 1; | |
b295d1b6 | 192 | u8 cursor_needs_physical : 1; |
cfdf1fa2 KH |
193 | }; |
194 | ||
b5e50c3f JB |
195 | enum no_fbc_reason { |
196 | FBC_STOLEN_TOO_SMALL, /* not enough space to hold compressed buffers */ | |
197 | FBC_UNSUPPORTED_MODE, /* interlace or doublescanned mode */ | |
198 | FBC_MODE_TOO_LARGE, /* mode too large for compression */ | |
199 | FBC_BAD_PLANE, /* fbc not supported on plane */ | |
200 | FBC_NOT_TILED, /* buffer not tiled */ | |
201 | }; | |
202 | ||
1da177e4 | 203 | typedef struct drm_i915_private { |
673a394b EA |
204 | struct drm_device *dev; |
205 | ||
cfdf1fa2 KH |
206 | const struct intel_device_info *info; |
207 | ||
ac5c4e76 DA |
208 | int has_gem; |
209 | ||
3043c60c | 210 | void __iomem *regs; |
1da177e4 | 211 | |
ec2a4c3f | 212 | struct pci_dev *bridge_dev; |
1da177e4 LT |
213 | drm_i915_ring_buffer_t ring; |
214 | ||
9c8da5eb | 215 | drm_dma_handle_t *status_page_dmah; |
1da177e4 | 216 | void *hw_status_page; |
1da177e4 | 217 | dma_addr_t dma_status_page; |
0a3e67a4 | 218 | uint32_t counter; |
dc7a9319 WZ |
219 | unsigned int status_gfx_addr; |
220 | drm_local_map_t hws_map; | |
673a394b | 221 | struct drm_gem_object *hws_obj; |
97f5ab66 | 222 | struct drm_gem_object *pwrctx; |
1da177e4 | 223 | |
d7658989 JB |
224 | struct resource mch_res; |
225 | ||
a6b54f3f | 226 | unsigned int cpp; |
1da177e4 LT |
227 | int back_offset; |
228 | int front_offset; | |
229 | int current_page; | |
230 | int page_flipping; | |
1da177e4 LT |
231 | |
232 | wait_queue_head_t irq_queue; | |
233 | atomic_t irq_received; | |
ed4cb414 EA |
234 | /** Protects user_irq_refcount and irq_mask_reg */ |
235 | spinlock_t user_irq_lock; | |
236 | /** Refcount for i915_user_irq_get() versus i915_user_irq_put(). */ | |
237 | int user_irq_refcount; | |
9d34e5db | 238 | u32 trace_irq_seqno; |
ed4cb414 EA |
239 | /** Cached value of IMR to avoid reads in updating the bitfield */ |
240 | u32 irq_mask_reg; | |
7c463586 | 241 | u32 pipestat[2]; |
f2b115e6 | 242 | /** splitted irq regs for graphics and display engine on Ironlake, |
036a4a7d ZW |
243 | irq_mask_reg is still used for display irq. */ |
244 | u32 gt_irq_mask_reg; | |
245 | u32 gt_irq_enable_reg; | |
246 | u32 de_irq_enable_reg; | |
c650156a ZW |
247 | u32 pch_irq_mask_reg; |
248 | u32 pch_irq_enable_reg; | |
1da177e4 | 249 | |
5ca58282 JB |
250 | u32 hotplug_supported_mask; |
251 | struct work_struct hotplug_work; | |
252 | ||
1da177e4 LT |
253 | int tex_lru_log_granularity; |
254 | int allow_batchbuffer; | |
255 | struct mem_block *agp_heap; | |
0d6aa60b | 256 | unsigned int sr01, adpa, ppcr, dvob, dvoc, lvds; |
702880f2 | 257 | int vblank_pipe; |
a6b54f3f | 258 | |
f65d9421 BG |
259 | /* For hangcheck timer */ |
260 | #define DRM_I915_HANGCHECK_PERIOD 75 /* in jiffies */ | |
261 | struct timer_list hangcheck_timer; | |
262 | int hangcheck_count; | |
263 | uint32_t last_acthd; | |
264 | ||
79e53945 JB |
265 | struct drm_mm vram; |
266 | ||
80824003 JB |
267 | unsigned long cfb_size; |
268 | unsigned long cfb_pitch; | |
269 | int cfb_fence; | |
270 | int cfb_plane; | |
271 | ||
79e53945 JB |
272 | int irq_enabled; |
273 | ||
8ee1c3db MG |
274 | struct intel_opregion opregion; |
275 | ||
02e792fb DV |
276 | /* overlay */ |
277 | struct intel_overlay *overlay; | |
278 | ||
79e53945 JB |
279 | /* LVDS info */ |
280 | int backlight_duty_cycle; /* restore backlight to this value */ | |
281 | bool panel_wants_dither; | |
282 | struct drm_display_mode *panel_fixed_mode; | |
88631706 ML |
283 | struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */ |
284 | struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */ | |
79e53945 JB |
285 | |
286 | /* Feature bits from the VBIOS */ | |
95281e35 HE |
287 | unsigned int int_tv_support:1; |
288 | unsigned int lvds_dither:1; | |
289 | unsigned int lvds_vbt:1; | |
290 | unsigned int int_crt_support:1; | |
43565a06 | 291 | unsigned int lvds_use_ssc:1; |
32f9d658 | 292 | unsigned int edp_support:1; |
43565a06 | 293 | int lvds_ssc_freq; |
500a8cc4 | 294 | int edp_bpp; |
79e53945 | 295 | |
c1c7af60 JB |
296 | struct notifier_block lid_notifier; |
297 | ||
29874f44 | 298 | int crt_ddc_bus; /* 0 = unknown, else GPIO to use for CRT DDC */ |
de151cf6 JB |
299 | struct drm_i915_fence_reg fence_regs[16]; /* assume 965 */ |
300 | int fence_reg_start; /* 4 if userland hasn't ioctl'd us yet */ | |
301 | int num_fence_regs; /* 8 on pre-965, 16 otherwise */ | |
302 | ||
7662c8bd SL |
303 | unsigned int fsb_freq, mem_freq; |
304 | ||
63eeaf38 JB |
305 | spinlock_t error_lock; |
306 | struct drm_i915_error_state *first_error; | |
8a905236 | 307 | struct work_struct error_work; |
9c9fe1f8 | 308 | struct workqueue_struct *wq; |
63eeaf38 | 309 | |
e70236a8 JB |
310 | /* Display functions */ |
311 | struct drm_i915_display_funcs display; | |
312 | ||
ba8bbcf6 | 313 | /* Register state */ |
c9354c85 | 314 | bool modeset_on_lid; |
ba8bbcf6 JB |
315 | u8 saveLBB; |
316 | u32 saveDSPACNTR; | |
317 | u32 saveDSPBCNTR; | |
e948e994 | 318 | u32 saveDSPARB; |
461cba2d | 319 | u32 saveHWS; |
ba8bbcf6 JB |
320 | u32 savePIPEACONF; |
321 | u32 savePIPEBCONF; | |
322 | u32 savePIPEASRC; | |
323 | u32 savePIPEBSRC; | |
324 | u32 saveFPA0; | |
325 | u32 saveFPA1; | |
326 | u32 saveDPLL_A; | |
327 | u32 saveDPLL_A_MD; | |
328 | u32 saveHTOTAL_A; | |
329 | u32 saveHBLANK_A; | |
330 | u32 saveHSYNC_A; | |
331 | u32 saveVTOTAL_A; | |
332 | u32 saveVBLANK_A; | |
333 | u32 saveVSYNC_A; | |
334 | u32 saveBCLRPAT_A; | |
5586c8bc | 335 | u32 saveTRANSACONF; |
42048781 ZW |
336 | u32 saveTRANS_HTOTAL_A; |
337 | u32 saveTRANS_HBLANK_A; | |
338 | u32 saveTRANS_HSYNC_A; | |
339 | u32 saveTRANS_VTOTAL_A; | |
340 | u32 saveTRANS_VBLANK_A; | |
341 | u32 saveTRANS_VSYNC_A; | |
0da3ea12 | 342 | u32 savePIPEASTAT; |
ba8bbcf6 JB |
343 | u32 saveDSPASTRIDE; |
344 | u32 saveDSPASIZE; | |
345 | u32 saveDSPAPOS; | |
585fb111 | 346 | u32 saveDSPAADDR; |
ba8bbcf6 JB |
347 | u32 saveDSPASURF; |
348 | u32 saveDSPATILEOFF; | |
349 | u32 savePFIT_PGM_RATIOS; | |
0eb96d6e | 350 | u32 saveBLC_HIST_CTL; |
ba8bbcf6 JB |
351 | u32 saveBLC_PWM_CTL; |
352 | u32 saveBLC_PWM_CTL2; | |
42048781 ZW |
353 | u32 saveBLC_CPU_PWM_CTL; |
354 | u32 saveBLC_CPU_PWM_CTL2; | |
ba8bbcf6 JB |
355 | u32 saveFPB0; |
356 | u32 saveFPB1; | |
357 | u32 saveDPLL_B; | |
358 | u32 saveDPLL_B_MD; | |
359 | u32 saveHTOTAL_B; | |
360 | u32 saveHBLANK_B; | |
361 | u32 saveHSYNC_B; | |
362 | u32 saveVTOTAL_B; | |
363 | u32 saveVBLANK_B; | |
364 | u32 saveVSYNC_B; | |
365 | u32 saveBCLRPAT_B; | |
5586c8bc | 366 | u32 saveTRANSBCONF; |
42048781 ZW |
367 | u32 saveTRANS_HTOTAL_B; |
368 | u32 saveTRANS_HBLANK_B; | |
369 | u32 saveTRANS_HSYNC_B; | |
370 | u32 saveTRANS_VTOTAL_B; | |
371 | u32 saveTRANS_VBLANK_B; | |
372 | u32 saveTRANS_VSYNC_B; | |
0da3ea12 | 373 | u32 savePIPEBSTAT; |
ba8bbcf6 JB |
374 | u32 saveDSPBSTRIDE; |
375 | u32 saveDSPBSIZE; | |
376 | u32 saveDSPBPOS; | |
585fb111 | 377 | u32 saveDSPBADDR; |
ba8bbcf6 JB |
378 | u32 saveDSPBSURF; |
379 | u32 saveDSPBTILEOFF; | |
585fb111 JB |
380 | u32 saveVGA0; |
381 | u32 saveVGA1; | |
382 | u32 saveVGA_PD; | |
ba8bbcf6 JB |
383 | u32 saveVGACNTRL; |
384 | u32 saveADPA; | |
385 | u32 saveLVDS; | |
585fb111 JB |
386 | u32 savePP_ON_DELAYS; |
387 | u32 savePP_OFF_DELAYS; | |
ba8bbcf6 JB |
388 | u32 saveDVOA; |
389 | u32 saveDVOB; | |
390 | u32 saveDVOC; | |
391 | u32 savePP_ON; | |
392 | u32 savePP_OFF; | |
393 | u32 savePP_CONTROL; | |
585fb111 | 394 | u32 savePP_DIVISOR; |
ba8bbcf6 JB |
395 | u32 savePFIT_CONTROL; |
396 | u32 save_palette_a[256]; | |
397 | u32 save_palette_b[256]; | |
06027f91 | 398 | u32 saveDPFC_CB_BASE; |
ba8bbcf6 JB |
399 | u32 saveFBC_CFB_BASE; |
400 | u32 saveFBC_LL_BASE; | |
401 | u32 saveFBC_CONTROL; | |
402 | u32 saveFBC_CONTROL2; | |
0da3ea12 JB |
403 | u32 saveIER; |
404 | u32 saveIIR; | |
405 | u32 saveIMR; | |
42048781 ZW |
406 | u32 saveDEIER; |
407 | u32 saveDEIMR; | |
408 | u32 saveGTIER; | |
409 | u32 saveGTIMR; | |
410 | u32 saveFDI_RXA_IMR; | |
411 | u32 saveFDI_RXB_IMR; | |
1f84e550 | 412 | u32 saveCACHE_MODE_0; |
1f84e550 | 413 | u32 saveMI_ARB_STATE; |
ba8bbcf6 JB |
414 | u32 saveSWF0[16]; |
415 | u32 saveSWF1[16]; | |
416 | u32 saveSWF2[3]; | |
417 | u8 saveMSR; | |
418 | u8 saveSR[8]; | |
123f794f | 419 | u8 saveGR[25]; |
ba8bbcf6 | 420 | u8 saveAR_INDEX; |
a59e122a | 421 | u8 saveAR[21]; |
ba8bbcf6 | 422 | u8 saveDACMASK; |
a59e122a | 423 | u8 saveCR[37]; |
79f11c19 | 424 | uint64_t saveFENCE[16]; |
1fd1c624 EA |
425 | u32 saveCURACNTR; |
426 | u32 saveCURAPOS; | |
427 | u32 saveCURABASE; | |
428 | u32 saveCURBCNTR; | |
429 | u32 saveCURBPOS; | |
430 | u32 saveCURBBASE; | |
431 | u32 saveCURSIZE; | |
a4fc5ed6 KP |
432 | u32 saveDP_B; |
433 | u32 saveDP_C; | |
434 | u32 saveDP_D; | |
435 | u32 savePIPEA_GMCH_DATA_M; | |
436 | u32 savePIPEB_GMCH_DATA_M; | |
437 | u32 savePIPEA_GMCH_DATA_N; | |
438 | u32 savePIPEB_GMCH_DATA_N; | |
439 | u32 savePIPEA_DP_LINK_M; | |
440 | u32 savePIPEB_DP_LINK_M; | |
441 | u32 savePIPEA_DP_LINK_N; | |
442 | u32 savePIPEB_DP_LINK_N; | |
42048781 ZW |
443 | u32 saveFDI_RXA_CTL; |
444 | u32 saveFDI_TXA_CTL; | |
445 | u32 saveFDI_RXB_CTL; | |
446 | u32 saveFDI_TXB_CTL; | |
447 | u32 savePFA_CTL_1; | |
448 | u32 savePFB_CTL_1; | |
449 | u32 savePFA_WIN_SZ; | |
450 | u32 savePFB_WIN_SZ; | |
451 | u32 savePFA_WIN_POS; | |
452 | u32 savePFB_WIN_POS; | |
5586c8bc ZW |
453 | u32 savePCH_DREF_CONTROL; |
454 | u32 saveDISP_ARB_CTL; | |
455 | u32 savePIPEA_DATA_M1; | |
456 | u32 savePIPEA_DATA_N1; | |
457 | u32 savePIPEA_LINK_M1; | |
458 | u32 savePIPEA_LINK_N1; | |
459 | u32 savePIPEB_DATA_M1; | |
460 | u32 savePIPEB_DATA_N1; | |
461 | u32 savePIPEB_LINK_M1; | |
462 | u32 savePIPEB_LINK_N1; | |
b5b72e89 | 463 | u32 saveMCHBAR_RENDER_STANDBY; |
673a394b EA |
464 | |
465 | struct { | |
466 | struct drm_mm gtt_space; | |
467 | ||
0839ccb8 | 468 | struct io_mapping *gtt_mapping; |
ab657db1 | 469 | int gtt_mtrr; |
0839ccb8 | 470 | |
31169714 CW |
471 | /** |
472 | * Membership on list of all loaded devices, used to evict | |
473 | * inactive buffers under memory pressure. | |
474 | * | |
475 | * Modifications should only be done whilst holding the | |
476 | * shrink_list_lock spinlock. | |
477 | */ | |
478 | struct list_head shrink_list; | |
479 | ||
673a394b EA |
480 | /** |
481 | * List of objects currently involved in rendering from the | |
482 | * ringbuffer. | |
483 | * | |
ce44b0ea EA |
484 | * Includes buffers having the contents of their GPU caches |
485 | * flushed, not necessarily primitives. last_rendering_seqno | |
486 | * represents when the rendering involved will be completed. | |
487 | * | |
673a394b EA |
488 | * A reference is held on the buffer while on this list. |
489 | */ | |
5e118f41 | 490 | spinlock_t active_list_lock; |
673a394b EA |
491 | struct list_head active_list; |
492 | ||
493 | /** | |
494 | * List of objects which are not in the ringbuffer but which | |
495 | * still have a write_domain which needs to be flushed before | |
496 | * unbinding. | |
497 | * | |
ce44b0ea EA |
498 | * last_rendering_seqno is 0 while an object is in this list. |
499 | * | |
673a394b EA |
500 | * A reference is held on the buffer while on this list. |
501 | */ | |
502 | struct list_head flushing_list; | |
503 | ||
99fcb766 DV |
504 | /** |
505 | * List of objects currently pending a GPU write flush. | |
506 | * | |
507 | * All elements on this list will belong to either the | |
508 | * active_list or flushing_list, last_rendering_seqno can | |
509 | * be used to differentiate between the two elements. | |
510 | */ | |
511 | struct list_head gpu_write_list; | |
512 | ||
673a394b EA |
513 | /** |
514 | * LRU list of objects which are not in the ringbuffer and | |
515 | * are ready to unbind, but are still in the GTT. | |
516 | * | |
ce44b0ea EA |
517 | * last_rendering_seqno is 0 while an object is in this list. |
518 | * | |
673a394b EA |
519 | * A reference is not held on the buffer while on this list, |
520 | * as merely being GTT-bound shouldn't prevent its being | |
521 | * freed, and we'll pull it off the list in the free path. | |
522 | */ | |
523 | struct list_head inactive_list; | |
524 | ||
a09ba7fa EA |
525 | /** LRU list of objects with fence regs on them. */ |
526 | struct list_head fence_list; | |
527 | ||
673a394b EA |
528 | /** |
529 | * List of breadcrumbs associated with GPU requests currently | |
530 | * outstanding. | |
531 | */ | |
532 | struct list_head request_list; | |
533 | ||
534 | /** | |
535 | * We leave the user IRQ off as much as possible, | |
536 | * but this means that requests will finish and never | |
537 | * be retired once the system goes idle. Set a timer to | |
538 | * fire periodically while the ring is running. When it | |
539 | * fires, go retire requests. | |
540 | */ | |
541 | struct delayed_work retire_work; | |
542 | ||
543 | uint32_t next_gem_seqno; | |
544 | ||
545 | /** | |
546 | * Waiting sequence number, if any | |
547 | */ | |
548 | uint32_t waiting_gem_seqno; | |
549 | ||
550 | /** | |
551 | * Last seq seen at irq time | |
552 | */ | |
553 | uint32_t irq_gem_seqno; | |
554 | ||
555 | /** | |
556 | * Flag if the X Server, and thus DRM, is not currently in | |
557 | * control of the device. | |
558 | * | |
559 | * This is set between LeaveVT and EnterVT. It needs to be | |
560 | * replaced with a semaphore. It also needs to be | |
561 | * transitioned away from for kernel modesetting. | |
562 | */ | |
563 | int suspended; | |
564 | ||
565 | /** | |
566 | * Flag if the hardware appears to be wedged. | |
567 | * | |
568 | * This is set when attempts to idle the device timeout. | |
569 | * It prevents command submission from occuring and makes | |
570 | * every pending request fail | |
571 | */ | |
ba1234d1 | 572 | atomic_t wedged; |
673a394b EA |
573 | |
574 | /** Bit 6 swizzling required for X tiling */ | |
575 | uint32_t bit_6_swizzle_x; | |
576 | /** Bit 6 swizzling required for Y tiling */ | |
577 | uint32_t bit_6_swizzle_y; | |
71acb5eb DA |
578 | |
579 | /* storage for physical objects */ | |
580 | struct drm_i915_gem_phys_object *phys_objs[I915_MAX_PHYS_OBJECT]; | |
673a394b | 581 | } mm; |
9b9d172d | 582 | struct sdvo_device_mapping sdvo_mappings[2]; |
a3e17eb8 ZY |
583 | /* indicate whether the LVDS_BORDER should be enabled or not */ |
584 | unsigned int lvds_border_bits; | |
652c393a | 585 | |
6b95a207 KH |
586 | struct drm_crtc *plane_to_crtc_mapping[2]; |
587 | struct drm_crtc *pipe_to_crtc_mapping[2]; | |
588 | wait_queue_head_t pending_flip_queue; | |
589 | ||
652c393a JB |
590 | /* Reclocking support */ |
591 | bool render_reclock_avail; | |
592 | bool lvds_downclock_avail; | |
18f9ed12 ZY |
593 | /* indicates the reduced downclock for LVDS*/ |
594 | int lvds_downclock; | |
652c393a JB |
595 | struct work_struct idle_work; |
596 | struct timer_list idle_timer; | |
597 | bool busy; | |
598 | u16 orig_clock; | |
6363ee6f ZY |
599 | int child_dev_num; |
600 | struct child_device_config *child_dev; | |
a2565377 | 601 | struct drm_connector *int_lvds_connector; |
f97108d1 | 602 | |
c4804411 | 603 | bool mchbar_need_disable; |
f97108d1 JB |
604 | |
605 | u8 cur_delay; | |
606 | u8 min_delay; | |
607 | u8 max_delay; | |
b5e50c3f JB |
608 | |
609 | enum no_fbc_reason no_fbc_reason; | |
1da177e4 LT |
610 | } drm_i915_private_t; |
611 | ||
673a394b EA |
612 | /** driver private structure attached to each drm_gem_object */ |
613 | struct drm_i915_gem_object { | |
614 | struct drm_gem_object *obj; | |
615 | ||
616 | /** Current space allocated to this object in the GTT, if any. */ | |
617 | struct drm_mm_node *gtt_space; | |
618 | ||
619 | /** This object's place on the active/flushing/inactive lists */ | |
620 | struct list_head list; | |
99fcb766 DV |
621 | /** This object's place on GPU write list */ |
622 | struct list_head gpu_write_list; | |
673a394b | 623 | |
a09ba7fa EA |
624 | /** This object's place on the fenced object LRU */ |
625 | struct list_head fence_list; | |
626 | ||
673a394b EA |
627 | /** |
628 | * This is set if the object is on the active or flushing lists | |
629 | * (has pending rendering), and is not set if it's on inactive (ready | |
630 | * to be unbound). | |
631 | */ | |
632 | int active; | |
633 | ||
634 | /** | |
635 | * This is set if the object has been written to since last bound | |
636 | * to the GTT | |
637 | */ | |
638 | int dirty; | |
639 | ||
640 | /** AGP memory structure for our GTT binding. */ | |
641 | DRM_AGP_MEM *agp_mem; | |
642 | ||
856fa198 EA |
643 | struct page **pages; |
644 | int pages_refcount; | |
673a394b EA |
645 | |
646 | /** | |
647 | * Current offset of the object in GTT space. | |
648 | * | |
649 | * This is the same as gtt_space->start | |
650 | */ | |
651 | uint32_t gtt_offset; | |
e67b8ce1 | 652 | |
de151cf6 JB |
653 | /** |
654 | * Fake offset for use by mmap(2) | |
655 | */ | |
656 | uint64_t mmap_offset; | |
657 | ||
658 | /** | |
659 | * Fence register bits (if any) for this object. Will be set | |
660 | * as needed when mapped into the GTT. | |
661 | * Protected by dev->struct_mutex. | |
662 | */ | |
663 | int fence_reg; | |
673a394b | 664 | |
673a394b EA |
665 | /** How many users have pinned this object in GTT space */ |
666 | int pin_count; | |
667 | ||
668 | /** Breadcrumb of last rendering to the buffer. */ | |
669 | uint32_t last_rendering_seqno; | |
670 | ||
671 | /** Current tiling mode for the object. */ | |
672 | uint32_t tiling_mode; | |
de151cf6 | 673 | uint32_t stride; |
673a394b | 674 | |
280b713b EA |
675 | /** Record of address bit 17 of each page at last unbind. */ |
676 | long *bit_17; | |
677 | ||
ba1eb1d8 KP |
678 | /** AGP mapping type (AGP_USER_MEMORY or AGP_USER_CACHED_MEMORY */ |
679 | uint32_t agp_type; | |
680 | ||
673a394b | 681 | /** |
e47c68e9 EA |
682 | * If present, while GEM_DOMAIN_CPU is in the read domain this array |
683 | * flags which individual pages are valid. | |
673a394b EA |
684 | */ |
685 | uint8_t *page_cpu_valid; | |
79e53945 JB |
686 | |
687 | /** User space pin count and filp owning the pin */ | |
688 | uint32_t user_pin_count; | |
689 | struct drm_file *pin_filp; | |
71acb5eb DA |
690 | |
691 | /** for phy allocated objects */ | |
692 | struct drm_i915_gem_phys_object *phys_obj; | |
b70d11da KH |
693 | |
694 | /** | |
695 | * Used for checking the object doesn't appear more than once | |
696 | * in an execbuffer object list. | |
697 | */ | |
698 | int in_execbuffer; | |
3ef94daa CW |
699 | |
700 | /** | |
701 | * Advice: are the backing pages purgeable? | |
702 | */ | |
703 | int madv; | |
6b95a207 KH |
704 | |
705 | /** | |
706 | * Number of crtcs where this object is currently the fb, but | |
707 | * will be page flipped away on the next vblank. When it | |
708 | * reaches 0, dev_priv->pending_flip_queue will be woken up. | |
709 | */ | |
710 | atomic_t pending_flip; | |
673a394b EA |
711 | }; |
712 | ||
713 | /** | |
714 | * Request queue structure. | |
715 | * | |
716 | * The request queue allows us to note sequence numbers that have been emitted | |
717 | * and may be associated with active buffers to be retired. | |
718 | * | |
719 | * By keeping this list, we can avoid having to do questionable | |
720 | * sequence-number comparisons on buffer last_rendering_seqnos, and associate | |
721 | * an emission time with seqnos for tracking how far ahead of the GPU we are. | |
722 | */ | |
723 | struct drm_i915_gem_request { | |
724 | /** GEM sequence number associated with this request. */ | |
725 | uint32_t seqno; | |
726 | ||
727 | /** Time at which this request was emitted, in jiffies. */ | |
728 | unsigned long emitted_jiffies; | |
729 | ||
b962442e | 730 | /** global list entry for this request */ |
673a394b | 731 | struct list_head list; |
b962442e EA |
732 | |
733 | /** file_priv list entry for this request */ | |
734 | struct list_head client_list; | |
673a394b EA |
735 | }; |
736 | ||
737 | struct drm_i915_file_private { | |
738 | struct { | |
b962442e | 739 | struct list_head request_list; |
673a394b EA |
740 | } mm; |
741 | }; | |
742 | ||
79e53945 JB |
743 | enum intel_chip_family { |
744 | CHIP_I8XX = 0x01, | |
745 | CHIP_I9XX = 0x02, | |
746 | CHIP_I915 = 0x04, | |
747 | CHIP_I965 = 0x08, | |
748 | }; | |
749 | ||
c153f45f | 750 | extern struct drm_ioctl_desc i915_ioctls[]; |
b3a83639 | 751 | extern int i915_max_ioctl; |
79e53945 | 752 | extern unsigned int i915_fbpercrtc; |
652c393a | 753 | extern unsigned int i915_powersave; |
33814341 | 754 | extern unsigned int i915_lvds_downclock; |
b3a83639 | 755 | |
1341d655 BG |
756 | extern void i915_save_display(struct drm_device *dev); |
757 | extern void i915_restore_display(struct drm_device *dev); | |
7c1c2871 DA |
758 | extern int i915_master_create(struct drm_device *dev, struct drm_master *master); |
759 | extern void i915_master_destroy(struct drm_device *dev, struct drm_master *master); | |
760 | ||
1da177e4 | 761 | /* i915_dma.c */ |
84b1fd10 | 762 | extern void i915_kernel_lost_context(struct drm_device * dev); |
22eae947 | 763 | extern int i915_driver_load(struct drm_device *, unsigned long flags); |
ba8bbcf6 | 764 | extern int i915_driver_unload(struct drm_device *); |
673a394b | 765 | extern int i915_driver_open(struct drm_device *dev, struct drm_file *file_priv); |
84b1fd10 | 766 | extern void i915_driver_lastclose(struct drm_device * dev); |
6c340eac EA |
767 | extern void i915_driver_preclose(struct drm_device *dev, |
768 | struct drm_file *file_priv); | |
673a394b EA |
769 | extern void i915_driver_postclose(struct drm_device *dev, |
770 | struct drm_file *file_priv); | |
84b1fd10 | 771 | extern int i915_driver_device_is_agp(struct drm_device * dev); |
0d6aa60b DA |
772 | extern long i915_compat_ioctl(struct file *filp, unsigned int cmd, |
773 | unsigned long arg); | |
673a394b | 774 | extern int i915_emit_box(struct drm_device *dev, |
201361a5 | 775 | struct drm_clip_rect *boxes, |
673a394b | 776 | int i, int DR1, int DR4); |
11ed50ec | 777 | extern int i965_reset(struct drm_device *dev, u8 flags); |
af6061af | 778 | |
1da177e4 | 779 | /* i915_irq.c */ |
f65d9421 | 780 | void i915_hangcheck_elapsed(unsigned long data); |
c153f45f EA |
781 | extern int i915_irq_emit(struct drm_device *dev, void *data, |
782 | struct drm_file *file_priv); | |
783 | extern int i915_irq_wait(struct drm_device *dev, void *data, | |
784 | struct drm_file *file_priv); | |
673a394b | 785 | void i915_user_irq_get(struct drm_device *dev); |
9d34e5db | 786 | void i915_trace_irq_get(struct drm_device *dev, u32 seqno); |
673a394b | 787 | void i915_user_irq_put(struct drm_device *dev); |
79e53945 | 788 | extern void i915_enable_interrupt (struct drm_device *dev); |
1da177e4 LT |
789 | |
790 | extern irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS); | |
84b1fd10 | 791 | extern void i915_driver_irq_preinstall(struct drm_device * dev); |
0a3e67a4 | 792 | extern int i915_driver_irq_postinstall(struct drm_device *dev); |
84b1fd10 | 793 | extern void i915_driver_irq_uninstall(struct drm_device * dev); |
c153f45f EA |
794 | extern int i915_vblank_pipe_set(struct drm_device *dev, void *data, |
795 | struct drm_file *file_priv); | |
796 | extern int i915_vblank_pipe_get(struct drm_device *dev, void *data, | |
797 | struct drm_file *file_priv); | |
0a3e67a4 JB |
798 | extern int i915_enable_vblank(struct drm_device *dev, int crtc); |
799 | extern void i915_disable_vblank(struct drm_device *dev, int crtc); | |
800 | extern u32 i915_get_vblank_counter(struct drm_device *dev, int crtc); | |
9880b7a5 | 801 | extern u32 gm45_get_vblank_counter(struct drm_device *dev, int crtc); |
c153f45f EA |
802 | extern int i915_vblank_swap(struct drm_device *dev, void *data, |
803 | struct drm_file *file_priv); | |
8ee1c3db | 804 | extern void i915_enable_irq(drm_i915_private_t *dev_priv, u32 mask); |
1da177e4 | 805 | |
7c463586 KP |
806 | void |
807 | i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask); | |
808 | ||
809 | void | |
810 | i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask); | |
811 | ||
01c66889 ZY |
812 | void intel_enable_asle (struct drm_device *dev); |
813 | ||
7c463586 | 814 | |
1da177e4 | 815 | /* i915_mem.c */ |
c153f45f EA |
816 | extern int i915_mem_alloc(struct drm_device *dev, void *data, |
817 | struct drm_file *file_priv); | |
818 | extern int i915_mem_free(struct drm_device *dev, void *data, | |
819 | struct drm_file *file_priv); | |
820 | extern int i915_mem_init_heap(struct drm_device *dev, void *data, | |
821 | struct drm_file *file_priv); | |
822 | extern int i915_mem_destroy_heap(struct drm_device *dev, void *data, | |
823 | struct drm_file *file_priv); | |
1da177e4 | 824 | extern void i915_mem_takedown(struct mem_block **heap); |
84b1fd10 | 825 | extern void i915_mem_release(struct drm_device * dev, |
6c340eac | 826 | struct drm_file *file_priv, struct mem_block *heap); |
673a394b EA |
827 | /* i915_gem.c */ |
828 | int i915_gem_init_ioctl(struct drm_device *dev, void *data, | |
829 | struct drm_file *file_priv); | |
830 | int i915_gem_create_ioctl(struct drm_device *dev, void *data, | |
831 | struct drm_file *file_priv); | |
832 | int i915_gem_pread_ioctl(struct drm_device *dev, void *data, | |
833 | struct drm_file *file_priv); | |
834 | int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data, | |
835 | struct drm_file *file_priv); | |
836 | int i915_gem_mmap_ioctl(struct drm_device *dev, void *data, | |
837 | struct drm_file *file_priv); | |
de151cf6 JB |
838 | int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data, |
839 | struct drm_file *file_priv); | |
673a394b EA |
840 | int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data, |
841 | struct drm_file *file_priv); | |
842 | int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data, | |
843 | struct drm_file *file_priv); | |
844 | int i915_gem_execbuffer(struct drm_device *dev, void *data, | |
845 | struct drm_file *file_priv); | |
76446cac JB |
846 | int i915_gem_execbuffer2(struct drm_device *dev, void *data, |
847 | struct drm_file *file_priv); | |
673a394b EA |
848 | int i915_gem_pin_ioctl(struct drm_device *dev, void *data, |
849 | struct drm_file *file_priv); | |
850 | int i915_gem_unpin_ioctl(struct drm_device *dev, void *data, | |
851 | struct drm_file *file_priv); | |
852 | int i915_gem_busy_ioctl(struct drm_device *dev, void *data, | |
853 | struct drm_file *file_priv); | |
854 | int i915_gem_throttle_ioctl(struct drm_device *dev, void *data, | |
855 | struct drm_file *file_priv); | |
3ef94daa CW |
856 | int i915_gem_madvise_ioctl(struct drm_device *dev, void *data, |
857 | struct drm_file *file_priv); | |
673a394b EA |
858 | int i915_gem_entervt_ioctl(struct drm_device *dev, void *data, |
859 | struct drm_file *file_priv); | |
860 | int i915_gem_leavevt_ioctl(struct drm_device *dev, void *data, | |
861 | struct drm_file *file_priv); | |
862 | int i915_gem_set_tiling(struct drm_device *dev, void *data, | |
863 | struct drm_file *file_priv); | |
864 | int i915_gem_get_tiling(struct drm_device *dev, void *data, | |
865 | struct drm_file *file_priv); | |
5a125c3c EA |
866 | int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data, |
867 | struct drm_file *file_priv); | |
673a394b | 868 | void i915_gem_load(struct drm_device *dev); |
673a394b EA |
869 | int i915_gem_init_object(struct drm_gem_object *obj); |
870 | void i915_gem_free_object(struct drm_gem_object *obj); | |
871 | int i915_gem_object_pin(struct drm_gem_object *obj, uint32_t alignment); | |
872 | void i915_gem_object_unpin(struct drm_gem_object *obj); | |
0f973f27 | 873 | int i915_gem_object_unbind(struct drm_gem_object *obj); |
d05ca301 | 874 | void i915_gem_release_mmap(struct drm_gem_object *obj); |
673a394b EA |
875 | void i915_gem_lastclose(struct drm_device *dev); |
876 | uint32_t i915_get_gem_seqno(struct drm_device *dev); | |
22be1724 | 877 | bool i915_seqno_passed(uint32_t seq1, uint32_t seq2); |
8c4b8c3f | 878 | int i915_gem_object_get_fence_reg(struct drm_gem_object *obj); |
52dc7d32 | 879 | int i915_gem_object_put_fence_reg(struct drm_gem_object *obj); |
673a394b EA |
880 | void i915_gem_retire_requests(struct drm_device *dev); |
881 | void i915_gem_retire_work_handler(struct work_struct *work); | |
882 | void i915_gem_clflush_object(struct drm_gem_object *obj); | |
79e53945 JB |
883 | int i915_gem_object_set_domain(struct drm_gem_object *obj, |
884 | uint32_t read_domains, | |
885 | uint32_t write_domain); | |
886 | int i915_gem_init_ringbuffer(struct drm_device *dev); | |
887 | void i915_gem_cleanup_ringbuffer(struct drm_device *dev); | |
888 | int i915_gem_do_init(struct drm_device *dev, unsigned long start, | |
889 | unsigned long end); | |
5669fcac | 890 | int i915_gem_idle(struct drm_device *dev); |
5a5a0c64 DV |
891 | uint32_t i915_add_request(struct drm_device *dev, struct drm_file *file_priv, |
892 | uint32_t flush_domains); | |
893 | int i915_do_wait_request(struct drm_device *dev, uint32_t seqno, int interruptible); | |
de151cf6 | 894 | int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf); |
79e53945 JB |
895 | int i915_gem_object_set_to_gtt_domain(struct drm_gem_object *obj, |
896 | int write); | |
b9241ea3 | 897 | int i915_gem_object_set_to_display_plane(struct drm_gem_object *obj); |
71acb5eb DA |
898 | int i915_gem_attach_phys_object(struct drm_device *dev, |
899 | struct drm_gem_object *obj, int id); | |
900 | void i915_gem_detach_phys_object(struct drm_device *dev, | |
901 | struct drm_gem_object *obj); | |
902 | void i915_gem_free_all_phys_object(struct drm_device *dev); | |
4bdadb97 | 903 | int i915_gem_object_get_pages(struct drm_gem_object *obj, gfp_t gfpmask); |
6911a9b8 | 904 | void i915_gem_object_put_pages(struct drm_gem_object *obj); |
1fd1c624 | 905 | void i915_gem_release(struct drm_device * dev, struct drm_file *file_priv); |
6b95a207 | 906 | void i915_gem_object_flush_write_domain(struct drm_gem_object *obj); |
673a394b | 907 | |
31169714 CW |
908 | void i915_gem_shrinker_init(void); |
909 | void i915_gem_shrinker_exit(void); | |
910 | ||
673a394b EA |
911 | /* i915_gem_tiling.c */ |
912 | void i915_gem_detect_bit_6_swizzle(struct drm_device *dev); | |
280b713b EA |
913 | void i915_gem_object_do_bit_17_swizzle(struct drm_gem_object *obj); |
914 | void i915_gem_object_save_bit_17_swizzle(struct drm_gem_object *obj); | |
76446cac JB |
915 | bool i915_tiling_ok(struct drm_device *dev, int stride, int size, |
916 | int tiling_mode); | |
917 | bool i915_obj_fenceable(struct drm_device *dev, struct drm_gem_object *obj); | |
673a394b EA |
918 | |
919 | /* i915_gem_debug.c */ | |
920 | void i915_gem_dump_object(struct drm_gem_object *obj, int len, | |
921 | const char *where, uint32_t mark); | |
922 | #if WATCH_INACTIVE | |
923 | void i915_verify_inactive(struct drm_device *dev, char *file, int line); | |
924 | #else | |
925 | #define i915_verify_inactive(dev, file, line) | |
926 | #endif | |
927 | void i915_gem_object_check_coherency(struct drm_gem_object *obj, int handle); | |
928 | void i915_gem_dump_object(struct drm_gem_object *obj, int len, | |
929 | const char *where, uint32_t mark); | |
930 | void i915_dump_lru(struct drm_device *dev, const char *where); | |
1da177e4 | 931 | |
2017263e | 932 | /* i915_debugfs.c */ |
27c202ad BG |
933 | int i915_debugfs_init(struct drm_minor *minor); |
934 | void i915_debugfs_cleanup(struct drm_minor *minor); | |
2017263e | 935 | |
317c35d1 JB |
936 | /* i915_suspend.c */ |
937 | extern int i915_save_state(struct drm_device *dev); | |
938 | extern int i915_restore_state(struct drm_device *dev); | |
0a3e67a4 JB |
939 | |
940 | /* i915_suspend.c */ | |
941 | extern int i915_save_state(struct drm_device *dev); | |
942 | extern int i915_restore_state(struct drm_device *dev); | |
317c35d1 | 943 | |
65e082c9 | 944 | #ifdef CONFIG_ACPI |
8ee1c3db | 945 | /* i915_opregion.c */ |
74a365b3 | 946 | extern int intel_opregion_init(struct drm_device *dev, int resume); |
3b1c1c11 | 947 | extern void intel_opregion_free(struct drm_device *dev, int suspend); |
8ee1c3db | 948 | extern void opregion_asle_intr(struct drm_device *dev); |
01c66889 | 949 | extern void ironlake_opregion_gse_intr(struct drm_device *dev); |
8ee1c3db | 950 | extern void opregion_enable_asle(struct drm_device *dev); |
65e082c9 | 951 | #else |
03ae61dd | 952 | static inline int intel_opregion_init(struct drm_device *dev, int resume) { return 0; } |
3b1c1c11 | 953 | static inline void intel_opregion_free(struct drm_device *dev, int suspend) { return; } |
65e082c9 | 954 | static inline void opregion_asle_intr(struct drm_device *dev) { return; } |
01c66889 | 955 | static inline void ironlake_opregion_gse_intr(struct drm_device *dev) { return; } |
65e082c9 LB |
956 | static inline void opregion_enable_asle(struct drm_device *dev) { return; } |
957 | #endif | |
8ee1c3db | 958 | |
79e53945 JB |
959 | /* modesetting */ |
960 | extern void intel_modeset_init(struct drm_device *dev); | |
961 | extern void intel_modeset_cleanup(struct drm_device *dev); | |
28d52043 | 962 | extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state); |
80824003 | 963 | extern void i8xx_disable_fbc(struct drm_device *dev); |
74dff282 | 964 | extern void g4x_disable_fbc(struct drm_device *dev); |
79e53945 | 965 | |
546b0974 EA |
966 | /** |
967 | * Lock test for when it's just for synchronization of ring access. | |
968 | * | |
969 | * In that case, we don't need to do it when GEM is initialized as nobody else | |
970 | * has access to the ring. | |
971 | */ | |
972 | #define RING_LOCK_TEST_WITH_RETURN(dev, file_priv) do { \ | |
973 | if (((drm_i915_private_t *)dev->dev_private)->ring.ring_obj == NULL) \ | |
974 | LOCK_TEST_WITH_RETURN(dev, file_priv); \ | |
975 | } while (0) | |
976 | ||
3043c60c EA |
977 | #define I915_READ(reg) readl(dev_priv->regs + (reg)) |
978 | #define I915_WRITE(reg, val) writel(val, dev_priv->regs + (reg)) | |
979 | #define I915_READ16(reg) readw(dev_priv->regs + (reg)) | |
980 | #define I915_WRITE16(reg, val) writel(val, dev_priv->regs + (reg)) | |
981 | #define I915_READ8(reg) readb(dev_priv->regs + (reg)) | |
982 | #define I915_WRITE8(reg, val) writeb(val, dev_priv->regs + (reg)) | |
de151cf6 | 983 | #define I915_WRITE64(reg, val) writeq(val, dev_priv->regs + (reg)) |
049ef7e4 | 984 | #define I915_READ64(reg) readq(dev_priv->regs + (reg)) |
7d57382e | 985 | #define POSTING_READ(reg) (void)I915_READ(reg) |
1da177e4 LT |
986 | |
987 | #define I915_VERBOSE 0 | |
988 | ||
0ef82af7 CW |
989 | #define RING_LOCALS volatile unsigned int *ring_virt__; |
990 | ||
991 | #define BEGIN_LP_RING(n) do { \ | |
992 | int bytes__ = 4*(n); \ | |
993 | if (I915_VERBOSE) DRM_DEBUG("BEGIN_LP_RING(%d)\n", (n)); \ | |
994 | /* a wrap must occur between instructions so pad beforehand */ \ | |
995 | if (unlikely (dev_priv->ring.tail + bytes__ > dev_priv->ring.Size)) \ | |
996 | i915_wrap_ring(dev); \ | |
997 | if (unlikely (dev_priv->ring.space < bytes__)) \ | |
998 | i915_wait_ring(dev, bytes__, __func__); \ | |
999 | ring_virt__ = (unsigned int *) \ | |
1000 | (dev_priv->ring.virtual_start + dev_priv->ring.tail); \ | |
1001 | dev_priv->ring.tail += bytes__; \ | |
1002 | dev_priv->ring.tail &= dev_priv->ring.Size - 1; \ | |
1003 | dev_priv->ring.space -= bytes__; \ | |
1da177e4 LT |
1004 | } while (0) |
1005 | ||
0ef82af7 | 1006 | #define OUT_RING(n) do { \ |
1da177e4 | 1007 | if (I915_VERBOSE) DRM_DEBUG(" OUT_RING %x\n", (int)(n)); \ |
0ef82af7 | 1008 | *ring_virt__++ = (n); \ |
1da177e4 LT |
1009 | } while (0) |
1010 | ||
1011 | #define ADVANCE_LP_RING() do { \ | |
0ef82af7 CW |
1012 | if (I915_VERBOSE) \ |
1013 | DRM_DEBUG("ADVANCE_LP_RING %x\n", dev_priv->ring.tail); \ | |
1014 | I915_WRITE(PRB0_TAIL, dev_priv->ring.tail); \ | |
1da177e4 LT |
1015 | } while(0) |
1016 | ||
ba8bbcf6 | 1017 | /** |
585fb111 JB |
1018 | * Reads a dword out of the status page, which is written to from the command |
1019 | * queue by automatic updates, MI_REPORT_HEAD, MI_STORE_DATA_INDEX, or | |
1020 | * MI_STORE_DATA_IMM. | |
ba8bbcf6 | 1021 | * |
585fb111 | 1022 | * The following dwords have a reserved meaning: |
0cdad7e8 KP |
1023 | * 0x00: ISR copy, updated when an ISR bit not set in the HWSTAM changes. |
1024 | * 0x04: ring 0 head pointer | |
1025 | * 0x05: ring 1 head pointer (915-class) | |
1026 | * 0x06: ring 2 head pointer (915-class) | |
1027 | * 0x10-0x1b: Context status DWords (GM45) | |
1028 | * 0x1f: Last written status offset. (GM45) | |
ba8bbcf6 | 1029 | * |
0cdad7e8 | 1030 | * The area from dword 0x20 to 0x3ff is available for driver usage. |
ba8bbcf6 | 1031 | */ |
585fb111 | 1032 | #define READ_HWSP(dev_priv, reg) (((volatile u32*)(dev_priv->hw_status_page))[reg]) |
0baf823a | 1033 | #define READ_BREADCRUMB(dev_priv) READ_HWSP(dev_priv, I915_BREADCRUMB_INDEX) |
0cdad7e8 | 1034 | #define I915_GEM_HWS_INDEX 0x20 |
0baf823a | 1035 | #define I915_BREADCRUMB_INDEX 0x21 |
ba8bbcf6 | 1036 | |
0ef82af7 | 1037 | extern int i915_wrap_ring(struct drm_device * dev); |
585fb111 | 1038 | extern int i915_wait_ring(struct drm_device * dev, int n, const char *caller); |
ba8bbcf6 | 1039 | |
cfdf1fa2 KH |
1040 | #define INTEL_INFO(dev) (((struct drm_i915_private *) (dev)->dev_private)->info) |
1041 | ||
1042 | #define IS_I830(dev) ((dev)->pci_device == 0x3577) | |
1043 | #define IS_845G(dev) ((dev)->pci_device == 0x2562) | |
1044 | #define IS_I85X(dev) ((dev)->pci_device == 0x3582) | |
1045 | #define IS_I865G(dev) ((dev)->pci_device == 0x2572) | |
1046 | #define IS_I8XX(dev) (INTEL_INFO(dev)->is_i8xx) | |
1047 | #define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g) | |
1048 | #define IS_I915GM(dev) ((dev)->pci_device == 0x2592) | |
1049 | #define IS_I945G(dev) ((dev)->pci_device == 0x2772) | |
1050 | #define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm) | |
1051 | #define IS_I965G(dev) (INTEL_INFO(dev)->is_i965g) | |
1052 | #define IS_I965GM(dev) (INTEL_INFO(dev)->is_i965gm) | |
1053 | #define IS_GM45(dev) ((dev)->pci_device == 0x2A42) | |
1054 | #define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x) | |
1055 | #define IS_PINEVIEW_G(dev) ((dev)->pci_device == 0xa001) | |
1056 | #define IS_PINEVIEW_M(dev) ((dev)->pci_device == 0xa011) | |
1057 | #define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview) | |
1058 | #define IS_G33(dev) (INTEL_INFO(dev)->is_g33) | |
f2b115e6 AJ |
1059 | #define IS_IRONLAKE_D(dev) ((dev)->pci_device == 0x0042) |
1060 | #define IS_IRONLAKE_M(dev) ((dev)->pci_device == 0x0046) | |
cfdf1fa2 KH |
1061 | #define IS_IRONLAKE(dev) (INTEL_INFO(dev)->is_ironlake) |
1062 | #define IS_I9XX(dev) (INTEL_INFO(dev)->is_i9xx) | |
1063 | #define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile) | |
ba8bbcf6 | 1064 | |
cfdf1fa2 | 1065 | #define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws) |
ba8bbcf6 | 1066 | |
0f973f27 JB |
1067 | /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte |
1068 | * rows, which changed the alignment requirements and fence programming. | |
1069 | */ | |
1070 | #define HAS_128_BYTE_Y_TILING(dev) (IS_I9XX(dev) && !(IS_I915G(dev) || \ | |
1071 | IS_I915GM(dev))) | |
f2b115e6 AJ |
1072 | #define SUPPORTS_DIGITAL_OUTPUTS(dev) (IS_I9XX(dev) && !IS_PINEVIEW(dev)) |
1073 | #define SUPPORTS_INTEGRATED_HDMI(dev) (IS_G4X(dev) || IS_IRONLAKE(dev)) | |
1074 | #define SUPPORTS_INTEGRATED_DP(dev) (IS_G4X(dev) || IS_IRONLAKE(dev)) | |
1075 | #define SUPPORTS_EDP(dev) (IS_IRONLAKE_M(dev)) | |
103a196f | 1076 | #define SUPPORTS_TV(dev) (IS_I9XX(dev) && IS_MOBILE(dev) && \ |
f2b115e6 | 1077 | !IS_IRONLAKE(dev) && !IS_PINEVIEW(dev)) |
cfdf1fa2 | 1078 | #define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug) |
7662c8bd | 1079 | /* dsparb controlled by hw only */ |
f2b115e6 | 1080 | #define DSPARB_HWCONTROL(dev) (IS_G4X(dev) || IS_IRONLAKE(dev)) |
b39d50e5 | 1081 | |
f2b115e6 | 1082 | #define HAS_FW_BLC(dev) (IS_I9XX(dev) || IS_G4X(dev) || IS_IRONLAKE(dev)) |
cfdf1fa2 KH |
1083 | #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr) |
1084 | #define I915_HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc) | |
1085 | #define I915_HAS_RC6(dev) (INTEL_INFO(dev)->has_rc6) | |
652c393a | 1086 | |
ba8bbcf6 | 1087 | #define PRIMARY_RINGBUFFER_SIZE (128*1024) |
0d6aa60b | 1088 | |
1da177e4 | 1089 | #endif |