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1da177e4 LT |
1 | /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*- |
2 | */ | |
0d6aa60b | 3 | /* |
bc54fd1a | 4 | * |
1da177e4 LT |
5 | * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. |
6 | * All Rights Reserved. | |
bc54fd1a DA |
7 | * |
8 | * Permission is hereby granted, free of charge, to any person obtaining a | |
9 | * copy of this software and associated documentation files (the | |
10 | * "Software"), to deal in the Software without restriction, including | |
11 | * without limitation the rights to use, copy, modify, merge, publish, | |
12 | * distribute, sub license, and/or sell copies of the Software, and to | |
13 | * permit persons to whom the Software is furnished to do so, subject to | |
14 | * the following conditions: | |
15 | * | |
16 | * The above copyright notice and this permission notice (including the | |
17 | * next paragraph) shall be included in all copies or substantial portions | |
18 | * of the Software. | |
19 | * | |
20 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS | |
21 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
22 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. | |
23 | * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR | |
24 | * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, | |
25 | * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE | |
26 | * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. | |
27 | * | |
0d6aa60b | 28 | */ |
1da177e4 LT |
29 | |
30 | #ifndef _I915_DRV_H_ | |
31 | #define _I915_DRV_H_ | |
32 | ||
e9b73c67 | 33 | #include <uapi/drm/i915_drm.h> |
93b81f51 | 34 | #include <uapi/drm/drm_fourcc.h> |
e9b73c67 | 35 | |
0839ccb8 | 36 | #include <linux/io-mapping.h> |
f899fc64 | 37 | #include <linux/i2c.h> |
c167a6fc | 38 | #include <linux/i2c-algo-bit.h> |
aaa6fd2a | 39 | #include <linux/backlight.h> |
4ff4b44c | 40 | #include <linux/hash.h> |
2911a35b | 41 | #include <linux/intel-iommu.h> |
742cbee8 | 42 | #include <linux/kref.h> |
b46a33e2 | 43 | #include <linux/perf_event.h> |
9ee32fea | 44 | #include <linux/pm_qos.h> |
d07f0e59 | 45 | #include <linux/reservation.h> |
e73bdd20 CW |
46 | #include <linux/shmem_fs.h> |
47 | ||
48 | #include <drm/drmP.h> | |
49 | #include <drm/intel-gtt.h> | |
50 | #include <drm/drm_legacy.h> /* for struct drm_dma_handle */ | |
51 | #include <drm/drm_gem.h> | |
3b96a0b1 | 52 | #include <drm/drm_auth.h> |
f9a87bd7 | 53 | #include <drm/drm_cache.h> |
e73bdd20 CW |
54 | |
55 | #include "i915_params.h" | |
56 | #include "i915_reg.h" | |
40b326ee | 57 | #include "i915_utils.h" |
e73bdd20 CW |
58 | |
59 | #include "intel_bios.h" | |
b978520d | 60 | #include "intel_device_info.h" |
3846a9b1 | 61 | #include "intel_display.h" |
ac7f11c6 | 62 | #include "intel_dpll_mgr.h" |
e73bdd20 | 63 | #include "intel_lrc.h" |
3846a9b1 | 64 | #include "intel_opregion.h" |
e73bdd20 | 65 | #include "intel_ringbuffer.h" |
3846a9b1 | 66 | #include "intel_uncore.h" |
6b0478fb | 67 | #include "intel_wopcm.h" |
3846a9b1 | 68 | #include "intel_uc.h" |
e73bdd20 | 69 | |
d501b1d2 | 70 | #include "i915_gem.h" |
6095868a | 71 | #include "i915_gem_context.h" |
b42fe9ca JL |
72 | #include "i915_gem_fence_reg.h" |
73 | #include "i915_gem_object.h" | |
e73bdd20 | 74 | #include "i915_gem_gtt.h" |
d897a111 | 75 | #include "i915_gpu_error.h" |
e61e0f51 | 76 | #include "i915_request.h" |
b7268c5e | 77 | #include "i915_scheduler.h" |
a89d1f92 | 78 | #include "i915_timeline.h" |
b42fe9ca JL |
79 | #include "i915_vma.h" |
80 | ||
0ad35fed ZW |
81 | #include "intel_gvt.h" |
82 | ||
1da177e4 LT |
83 | /* General customization: |
84 | */ | |
85 | ||
1da177e4 LT |
86 | #define DRIVER_NAME "i915" |
87 | #define DRIVER_DESC "Intel Graphics" | |
01f83786 JN |
88 | #define DRIVER_DATE "20180514" |
89 | #define DRIVER_TIMESTAMP 1526300884 | |
1da177e4 | 90 | |
e2c719b7 RC |
91 | /* Use I915_STATE_WARN(x) and I915_STATE_WARN_ON() (rather than WARN() and |
92 | * WARN_ON()) for hw state sanity checks to check for unexpected conditions | |
93 | * which may not necessarily be a user visible problem. This will either | |
94 | * WARN() or DRM_ERROR() depending on the verbose_checks moduleparam, to | |
95 | * enable distros and users to tailor their preferred amount of i915 abrt | |
96 | * spam. | |
97 | */ | |
98 | #define I915_STATE_WARN(condition, format...) ({ \ | |
99 | int __ret_warn_on = !!(condition); \ | |
32753cb8 | 100 | if (unlikely(__ret_warn_on)) \ |
4f044a88 | 101 | if (!WARN(i915_modparams.verbose_state_checks, format)) \ |
e2c719b7 | 102 | DRM_ERROR(format); \ |
e2c719b7 RC |
103 | unlikely(__ret_warn_on); \ |
104 | }) | |
105 | ||
152b2262 JL |
106 | #define I915_STATE_WARN_ON(x) \ |
107 | I915_STATE_WARN((x), "%s", "WARN_ON(" __stringify(x) ")") | |
c883ef1b | 108 | |
fae919f0 | 109 | #if IS_ENABLED(CONFIG_DRM_I915_DEBUG) |
4fec15d1 ID |
110 | bool __i915_inject_load_failure(const char *func, int line); |
111 | #define i915_inject_load_failure() \ | |
112 | __i915_inject_load_failure(__func__, __LINE__) | |
fae919f0 MW |
113 | #else |
114 | #define i915_inject_load_failure() false | |
115 | #endif | |
4fec15d1 | 116 | |
b95320bd MK |
117 | typedef struct { |
118 | uint32_t val; | |
119 | } uint_fixed_16_16_t; | |
120 | ||
121 | #define FP_16_16_MAX ({ \ | |
122 | uint_fixed_16_16_t fp; \ | |
123 | fp.val = UINT_MAX; \ | |
124 | fp; \ | |
125 | }) | |
126 | ||
d555cb58 KM |
127 | static inline bool is_fixed16_zero(uint_fixed_16_16_t val) |
128 | { | |
129 | if (val.val == 0) | |
130 | return true; | |
131 | return false; | |
132 | } | |
133 | ||
eac2cb81 | 134 | static inline uint_fixed_16_16_t u32_to_fixed16(uint32_t val) |
b95320bd MK |
135 | { |
136 | uint_fixed_16_16_t fp; | |
137 | ||
0b4d7cbf | 138 | WARN_ON(val > U16_MAX); |
b95320bd MK |
139 | |
140 | fp.val = val << 16; | |
141 | return fp; | |
142 | } | |
143 | ||
eac2cb81 | 144 | static inline uint32_t fixed16_to_u32_round_up(uint_fixed_16_16_t fp) |
b95320bd MK |
145 | { |
146 | return DIV_ROUND_UP(fp.val, 1 << 16); | |
147 | } | |
148 | ||
eac2cb81 | 149 | static inline uint32_t fixed16_to_u32(uint_fixed_16_16_t fp) |
b95320bd MK |
150 | { |
151 | return fp.val >> 16; | |
152 | } | |
153 | ||
eac2cb81 | 154 | static inline uint_fixed_16_16_t min_fixed16(uint_fixed_16_16_t min1, |
b95320bd MK |
155 | uint_fixed_16_16_t min2) |
156 | { | |
157 | uint_fixed_16_16_t min; | |
158 | ||
159 | min.val = min(min1.val, min2.val); | |
160 | return min; | |
161 | } | |
162 | ||
eac2cb81 | 163 | static inline uint_fixed_16_16_t max_fixed16(uint_fixed_16_16_t max1, |
b95320bd MK |
164 | uint_fixed_16_16_t max2) |
165 | { | |
166 | uint_fixed_16_16_t max; | |
167 | ||
168 | max.val = max(max1.val, max2.val); | |
169 | return max; | |
170 | } | |
171 | ||
07ab976d KM |
172 | static inline uint_fixed_16_16_t clamp_u64_to_fixed16(uint64_t val) |
173 | { | |
174 | uint_fixed_16_16_t fp; | |
0b4d7cbf KM |
175 | WARN_ON(val > U32_MAX); |
176 | fp.val = (uint32_t) val; | |
07ab976d KM |
177 | return fp; |
178 | } | |
179 | ||
a9d055de KM |
180 | static inline uint32_t div_round_up_fixed16(uint_fixed_16_16_t val, |
181 | uint_fixed_16_16_t d) | |
182 | { | |
183 | return DIV_ROUND_UP(val.val, d.val); | |
184 | } | |
185 | ||
186 | static inline uint32_t mul_round_up_u32_fixed16(uint32_t val, | |
187 | uint_fixed_16_16_t mul) | |
188 | { | |
189 | uint64_t intermediate_val; | |
a9d055de KM |
190 | |
191 | intermediate_val = (uint64_t) val * mul.val; | |
192 | intermediate_val = DIV_ROUND_UP_ULL(intermediate_val, 1 << 16); | |
0b4d7cbf KM |
193 | WARN_ON(intermediate_val > U32_MAX); |
194 | return (uint32_t) intermediate_val; | |
a9d055de KM |
195 | } |
196 | ||
197 | static inline uint_fixed_16_16_t mul_fixed16(uint_fixed_16_16_t val, | |
198 | uint_fixed_16_16_t mul) | |
199 | { | |
200 | uint64_t intermediate_val; | |
a9d055de KM |
201 | |
202 | intermediate_val = (uint64_t) val.val * mul.val; | |
203 | intermediate_val = intermediate_val >> 16; | |
07ab976d | 204 | return clamp_u64_to_fixed16(intermediate_val); |
a9d055de KM |
205 | } |
206 | ||
eac2cb81 | 207 | static inline uint_fixed_16_16_t div_fixed16(uint32_t val, uint32_t d) |
b95320bd | 208 | { |
b95320bd MK |
209 | uint64_t interm_val; |
210 | ||
211 | interm_val = (uint64_t)val << 16; | |
212 | interm_val = DIV_ROUND_UP_ULL(interm_val, d); | |
07ab976d | 213 | return clamp_u64_to_fixed16(interm_val); |
b95320bd MK |
214 | } |
215 | ||
a9d055de KM |
216 | static inline uint32_t div_round_up_u32_fixed16(uint32_t val, |
217 | uint_fixed_16_16_t d) | |
218 | { | |
219 | uint64_t interm_val; | |
220 | ||
221 | interm_val = (uint64_t)val << 16; | |
222 | interm_val = DIV_ROUND_UP_ULL(interm_val, d.val); | |
0b4d7cbf KM |
223 | WARN_ON(interm_val > U32_MAX); |
224 | return (uint32_t) interm_val; | |
a9d055de KM |
225 | } |
226 | ||
eac2cb81 | 227 | static inline uint_fixed_16_16_t mul_u32_fixed16(uint32_t val, |
b95320bd MK |
228 | uint_fixed_16_16_t mul) |
229 | { | |
230 | uint64_t intermediate_val; | |
b95320bd MK |
231 | |
232 | intermediate_val = (uint64_t) val * mul.val; | |
07ab976d | 233 | return clamp_u64_to_fixed16(intermediate_val); |
b95320bd MK |
234 | } |
235 | ||
6ea593c0 KM |
236 | static inline uint_fixed_16_16_t add_fixed16(uint_fixed_16_16_t add1, |
237 | uint_fixed_16_16_t add2) | |
238 | { | |
239 | uint64_t interm_sum; | |
240 | ||
241 | interm_sum = (uint64_t) add1.val + add2.val; | |
242 | return clamp_u64_to_fixed16(interm_sum); | |
243 | } | |
244 | ||
245 | static inline uint_fixed_16_16_t add_fixed16_u32(uint_fixed_16_16_t add1, | |
246 | uint32_t add2) | |
247 | { | |
248 | uint64_t interm_sum; | |
249 | uint_fixed_16_16_t interm_add2 = u32_to_fixed16(add2); | |
250 | ||
251 | interm_sum = (uint64_t) add1.val + interm_add2.val; | |
252 | return clamp_u64_to_fixed16(interm_sum); | |
253 | } | |
254 | ||
1d843f9d EE |
255 | enum hpd_pin { |
256 | HPD_NONE = 0, | |
1d843f9d EE |
257 | HPD_TV = HPD_NONE, /* TV is known to be unreliable */ |
258 | HPD_CRT, | |
259 | HPD_SDVO_B, | |
260 | HPD_SDVO_C, | |
cc24fcdc | 261 | HPD_PORT_A, |
1d843f9d EE |
262 | HPD_PORT_B, |
263 | HPD_PORT_C, | |
264 | HPD_PORT_D, | |
26951caf | 265 | HPD_PORT_E, |
96ae4831 | 266 | HPD_PORT_F, |
1d843f9d EE |
267 | HPD_NUM_PINS |
268 | }; | |
269 | ||
c91711f9 JN |
270 | #define for_each_hpd_pin(__pin) \ |
271 | for ((__pin) = (HPD_NONE + 1); (__pin) < HPD_NUM_PINS; (__pin)++) | |
272 | ||
317eaa95 L |
273 | #define HPD_STORM_DEFAULT_THRESHOLD 5 |
274 | ||
5fcece80 JN |
275 | struct i915_hotplug { |
276 | struct work_struct hotplug_work; | |
277 | ||
278 | struct { | |
279 | unsigned long last_jiffies; | |
280 | int count; | |
281 | enum { | |
282 | HPD_ENABLED = 0, | |
283 | HPD_DISABLED = 1, | |
284 | HPD_MARK_DISABLED = 2 | |
285 | } state; | |
286 | } stats[HPD_NUM_PINS]; | |
287 | u32 event_bits; | |
288 | struct delayed_work reenable_work; | |
289 | ||
290 | struct intel_digital_port *irq_port[I915_MAX_PORTS]; | |
291 | u32 long_port_mask; | |
292 | u32 short_port_mask; | |
293 | struct work_struct dig_port_work; | |
294 | ||
19625e85 L |
295 | struct work_struct poll_init_work; |
296 | bool poll_enabled; | |
297 | ||
317eaa95 L |
298 | unsigned int hpd_storm_threshold; |
299 | ||
5fcece80 JN |
300 | /* |
301 | * if we get a HPD irq from DP and a HPD irq from non-DP | |
302 | * the non-DP HPD could block the workqueue on a mode config | |
303 | * mutex getting, that userspace may have taken. However | |
304 | * userspace is waiting on the DP workqueue to run which is | |
305 | * blocked behind the non-DP one. | |
306 | */ | |
307 | struct workqueue_struct *dp_wq; | |
308 | }; | |
309 | ||
2a2d5482 CW |
310 | #define I915_GEM_GPU_DOMAINS \ |
311 | (I915_GEM_DOMAIN_RENDER | \ | |
312 | I915_GEM_DOMAIN_SAMPLER | \ | |
313 | I915_GEM_DOMAIN_COMMAND | \ | |
314 | I915_GEM_DOMAIN_INSTRUCTION | \ | |
315 | I915_GEM_DOMAIN_VERTEX) | |
62fdfeaf | 316 | |
e7b903d2 | 317 | struct drm_i915_private; |
ad46cb53 | 318 | struct i915_mm_struct; |
5cc9ed4b | 319 | struct i915_mmu_object; |
e7b903d2 | 320 | |
a6f766f3 CW |
321 | struct drm_i915_file_private { |
322 | struct drm_i915_private *dev_priv; | |
323 | struct drm_file *file; | |
324 | ||
325 | struct { | |
326 | spinlock_t lock; | |
327 | struct list_head request_list; | |
d0bc54f2 CW |
328 | /* 20ms is a fairly arbitrary limit (greater than the average frame time) |
329 | * chosen to prevent the CPU getting more than a frame ahead of the GPU | |
330 | * (when using lax throttling for the frontbuffer). We also use it to | |
331 | * offer free GPU waitboosts for severely congested workloads. | |
332 | */ | |
333 | #define DRM_I915_THROTTLE_JIFFIES msecs_to_jiffies(20) | |
a6f766f3 CW |
334 | } mm; |
335 | struct idr context_idr; | |
336 | ||
2e1b8730 | 337 | struct intel_rps_client { |
7b92c1bd | 338 | atomic_t boosts; |
562d9bae | 339 | } rps_client; |
a6f766f3 | 340 | |
c80ff16e | 341 | unsigned int bsd_engine; |
b083a087 MK |
342 | |
343 | /* Client can have a maximum of 3 contexts banned before | |
344 | * it is denied of creating new contexts. As one context | |
345 | * ban needs 4 consecutive hangs, and more if there is | |
346 | * progress in between, this is a last resort stop gap measure | |
347 | * to limit the badly behaving clients access to gpu. | |
348 | */ | |
349 | #define I915_MAX_CLIENT_CONTEXT_BANS 3 | |
77b25a97 | 350 | atomic_t context_bans; |
a6f766f3 CW |
351 | }; |
352 | ||
1da177e4 LT |
353 | /* Interface history: |
354 | * | |
355 | * 1.1: Original. | |
0d6aa60b DA |
356 | * 1.2: Add Power Management |
357 | * 1.3: Add vblank support | |
de227f5f | 358 | * 1.4: Fix cmdbuffer path, add heap destroy |
702880f2 | 359 | * 1.5: Add vblank pipe configuration |
2228ed67 MD |
360 | * 1.6: - New ioctl for scheduling buffer swaps on vertical blank |
361 | * - Support vertical blank on secondary display pipe | |
1da177e4 LT |
362 | */ |
363 | #define DRIVER_MAJOR 1 | |
2228ed67 | 364 | #define DRIVER_MINOR 6 |
1da177e4 LT |
365 | #define DRIVER_PATCHLEVEL 0 |
366 | ||
6ef3d427 CW |
367 | struct intel_overlay; |
368 | struct intel_overlay_error_state; | |
369 | ||
9b9d172d | 370 | struct sdvo_device_mapping { |
e957d772 | 371 | u8 initialized; |
9b9d172d | 372 | u8 dvo_port; |
373 | u8 slave_addr; | |
374 | u8 dvo_wiring; | |
e957d772 | 375 | u8 i2c_pin; |
b1083333 | 376 | u8 ddc_pin; |
9b9d172d | 377 | }; |
378 | ||
7bd688cd | 379 | struct intel_connector; |
820d2d77 | 380 | struct intel_encoder; |
ccf010fb | 381 | struct intel_atomic_state; |
5cec258b | 382 | struct intel_crtc_state; |
5724dbd1 | 383 | struct intel_initial_plane_config; |
0e8ffe1b | 384 | struct intel_crtc; |
ee9300bb DV |
385 | struct intel_limit; |
386 | struct dpll; | |
49cd97a3 | 387 | struct intel_cdclk_state; |
b8cecdf5 | 388 | |
e70236a8 | 389 | struct drm_i915_display_funcs { |
49cd97a3 VS |
390 | void (*get_cdclk)(struct drm_i915_private *dev_priv, |
391 | struct intel_cdclk_state *cdclk_state); | |
b0587e4d VS |
392 | void (*set_cdclk)(struct drm_i915_private *dev_priv, |
393 | const struct intel_cdclk_state *cdclk_state); | |
bdaf8439 VS |
394 | int (*get_fifo_size)(struct drm_i915_private *dev_priv, |
395 | enum i9xx_plane_id i9xx_plane); | |
e3bddded | 396 | int (*compute_pipe_wm)(struct intel_crtc_state *cstate); |
ed4a6a7c MR |
397 | int (*compute_intermediate_wm)(struct drm_device *dev, |
398 | struct intel_crtc *intel_crtc, | |
399 | struct intel_crtc_state *newstate); | |
ccf010fb ML |
400 | void (*initial_watermarks)(struct intel_atomic_state *state, |
401 | struct intel_crtc_state *cstate); | |
402 | void (*atomic_update_watermarks)(struct intel_atomic_state *state, | |
403 | struct intel_crtc_state *cstate); | |
404 | void (*optimize_watermarks)(struct intel_atomic_state *state, | |
405 | struct intel_crtc_state *cstate); | |
98d39494 | 406 | int (*compute_global_watermarks)(struct drm_atomic_state *state); |
432081bc | 407 | void (*update_wm)(struct intel_crtc *crtc); |
27c329ed | 408 | int (*modeset_calc_cdclk)(struct drm_atomic_state *state); |
0e8ffe1b DV |
409 | /* Returns the active state of the crtc, and if the crtc is active, |
410 | * fills out the pipe-config with the hw state. */ | |
411 | bool (*get_pipe_config)(struct intel_crtc *, | |
5cec258b | 412 | struct intel_crtc_state *); |
5724dbd1 DL |
413 | void (*get_initial_plane_config)(struct intel_crtc *, |
414 | struct intel_initial_plane_config *); | |
190f68c5 ACO |
415 | int (*crtc_compute_clock)(struct intel_crtc *crtc, |
416 | struct intel_crtc_state *crtc_state); | |
4a806558 ML |
417 | void (*crtc_enable)(struct intel_crtc_state *pipe_config, |
418 | struct drm_atomic_state *old_state); | |
419 | void (*crtc_disable)(struct intel_crtc_state *old_crtc_state, | |
420 | struct drm_atomic_state *old_state); | |
b44d5c0c | 421 | void (*update_crtcs)(struct drm_atomic_state *state); |
8ec47de2 VS |
422 | void (*audio_codec_enable)(struct intel_encoder *encoder, |
423 | const struct intel_crtc_state *crtc_state, | |
424 | const struct drm_connector_state *conn_state); | |
425 | void (*audio_codec_disable)(struct intel_encoder *encoder, | |
426 | const struct intel_crtc_state *old_crtc_state, | |
427 | const struct drm_connector_state *old_conn_state); | |
dc4a1094 ACO |
428 | void (*fdi_link_train)(struct intel_crtc *crtc, |
429 | const struct intel_crtc_state *crtc_state); | |
46f16e63 | 430 | void (*init_clock_gating)(struct drm_i915_private *dev_priv); |
91d14251 | 431 | void (*hpd_irq_setup)(struct drm_i915_private *dev_priv); |
e70236a8 JB |
432 | /* clock updates for mode set */ |
433 | /* cursor updates */ | |
434 | /* render clock increase/decrease */ | |
435 | /* display clock increase/decrease */ | |
436 | /* pll clock increase/decrease */ | |
8563b1e8 | 437 | |
b95c5321 ML |
438 | void (*load_csc_matrix)(struct drm_crtc_state *crtc_state); |
439 | void (*load_luts)(struct drm_crtc_state *crtc_state); | |
e70236a8 JB |
440 | }; |
441 | ||
b6e7d894 DL |
442 | #define CSR_VERSION(major, minor) ((major) << 16 | (minor)) |
443 | #define CSR_VERSION_MAJOR(version) ((version) >> 16) | |
444 | #define CSR_VERSION_MINOR(version) ((version) & 0xffff) | |
445 | ||
eb805623 | 446 | struct intel_csr { |
8144ac59 | 447 | struct work_struct work; |
eb805623 | 448 | const char *fw_path; |
a7f749f9 | 449 | uint32_t *dmc_payload; |
eb805623 | 450 | uint32_t dmc_fw_size; |
b6e7d894 | 451 | uint32_t version; |
eb805623 | 452 | uint32_t mmio_count; |
f0f59a00 | 453 | i915_reg_t mmioaddr[8]; |
eb805623 | 454 | uint32_t mmiodata[8]; |
832dba88 | 455 | uint32_t dc_state; |
a37baf3b | 456 | uint32_t allowed_dc_mask; |
eb805623 DV |
457 | }; |
458 | ||
7faf1ab2 DV |
459 | enum i915_cache_level { |
460 | I915_CACHE_NONE = 0, | |
350ec881 CW |
461 | I915_CACHE_LLC, /* also used for snoopable memory on non-LLC */ |
462 | I915_CACHE_L3_LLC, /* gen7+, L3 sits between the domain specifc | |
463 | caches, eg sampler/render caches, and the | |
464 | large Last-Level-Cache. LLC is coherent with | |
465 | the CPU, but L3 is only visible to the GPU. */ | |
651d794f | 466 | I915_CACHE_WT, /* hsw:gt3e WriteThrough for scanouts */ |
7faf1ab2 DV |
467 | }; |
468 | ||
85fd4f58 CW |
469 | #define I915_COLOR_UNEVICTABLE (-1) /* a non-vma sharing the address space */ |
470 | ||
a4001f1b PZ |
471 | enum fb_op_origin { |
472 | ORIGIN_GTT, | |
473 | ORIGIN_CPU, | |
474 | ORIGIN_CS, | |
475 | ORIGIN_FLIP, | |
74b4ea1e | 476 | ORIGIN_DIRTYFB, |
a4001f1b PZ |
477 | }; |
478 | ||
ab34a7e8 | 479 | struct intel_fbc { |
25ad93fd PZ |
480 | /* This is always the inner lock when overlapping with struct_mutex and |
481 | * it's the outer lock when overlapping with stolen_lock. */ | |
482 | struct mutex lock; | |
5e59f717 | 483 | unsigned threshold; |
dbef0f15 PZ |
484 | unsigned int possible_framebuffer_bits; |
485 | unsigned int busy_bits; | |
010cf73d | 486 | unsigned int visible_pipes_mask; |
e35fef21 | 487 | struct intel_crtc *crtc; |
5c3fe8b0 | 488 | |
c4213885 | 489 | struct drm_mm_node compressed_fb; |
5c3fe8b0 BW |
490 | struct drm_mm_node *compressed_llb; |
491 | ||
da46f936 RV |
492 | bool false_color; |
493 | ||
d029bcad | 494 | bool enabled; |
0e631adc | 495 | bool active; |
9adccc60 | 496 | |
61a585d6 PZ |
497 | bool underrun_detected; |
498 | struct work_struct underrun_work; | |
499 | ||
525a4f93 PZ |
500 | /* |
501 | * Due to the atomic rules we can't access some structures without the | |
502 | * appropriate locking, so we cache information here in order to avoid | |
503 | * these problems. | |
504 | */ | |
aaf78d27 | 505 | struct intel_fbc_state_cache { |
be1e3415 | 506 | struct i915_vma *vma; |
1c9b6b13 | 507 | unsigned long flags; |
be1e3415 | 508 | |
aaf78d27 PZ |
509 | struct { |
510 | unsigned int mode_flags; | |
511 | uint32_t hsw_bdw_pixel_rate; | |
512 | } crtc; | |
513 | ||
514 | struct { | |
515 | unsigned int rotation; | |
516 | int src_w; | |
517 | int src_h; | |
518 | bool visible; | |
bf0a5d4b JPH |
519 | /* |
520 | * Display surface base address adjustement for | |
521 | * pageflips. Note that on gen4+ this only adjusts up | |
522 | * to a tile, offsets within a tile are handled in | |
523 | * the hw itself (with the TILEOFF register). | |
524 | */ | |
525 | int adjusted_x; | |
526 | int adjusted_y; | |
31d1d3c8 JPH |
527 | |
528 | int y; | |
aaf78d27 PZ |
529 | } plane; |
530 | ||
531 | struct { | |
801c8fe8 | 532 | const struct drm_format_info *format; |
aaf78d27 | 533 | unsigned int stride; |
aaf78d27 PZ |
534 | } fb; |
535 | } state_cache; | |
536 | ||
525a4f93 PZ |
537 | /* |
538 | * This structure contains everything that's relevant to program the | |
539 | * hardware registers. When we want to figure out if we need to disable | |
540 | * and re-enable FBC for a new configuration we just check if there's | |
541 | * something different in the struct. The genx_fbc_activate functions | |
542 | * are supposed to read from it in order to program the registers. | |
543 | */ | |
b183b3f1 | 544 | struct intel_fbc_reg_params { |
be1e3415 | 545 | struct i915_vma *vma; |
1c9b6b13 | 546 | unsigned long flags; |
be1e3415 | 547 | |
b183b3f1 PZ |
548 | struct { |
549 | enum pipe pipe; | |
ed15030d | 550 | enum i9xx_plane_id i9xx_plane; |
b183b3f1 PZ |
551 | unsigned int fence_y_offset; |
552 | } crtc; | |
553 | ||
554 | struct { | |
801c8fe8 | 555 | const struct drm_format_info *format; |
b183b3f1 | 556 | unsigned int stride; |
b183b3f1 PZ |
557 | } fb; |
558 | ||
559 | int cfb_size; | |
5654a162 | 560 | unsigned int gen9_wa_cfb_stride; |
b183b3f1 PZ |
561 | } params; |
562 | ||
5c3fe8b0 | 563 | struct intel_fbc_work { |
128d7356 | 564 | bool scheduled; |
1b29b7ca | 565 | u64 scheduled_vblank; |
128d7356 | 566 | struct work_struct work; |
128d7356 | 567 | } work; |
5c3fe8b0 | 568 | |
bf6189c6 | 569 | const char *no_fbc_reason; |
b5e50c3f JB |
570 | }; |
571 | ||
fe88d122 | 572 | /* |
96178eeb VK |
573 | * HIGH_RR is the highest eDP panel refresh rate read from EDID |
574 | * LOW_RR is the lowest eDP panel refresh rate found from EDID | |
575 | * parsing for same resolution. | |
576 | */ | |
577 | enum drrs_refresh_rate_type { | |
578 | DRRS_HIGH_RR, | |
579 | DRRS_LOW_RR, | |
580 | DRRS_MAX_RR, /* RR count */ | |
581 | }; | |
582 | ||
583 | enum drrs_support_type { | |
584 | DRRS_NOT_SUPPORTED = 0, | |
585 | STATIC_DRRS_SUPPORT = 1, | |
586 | SEAMLESS_DRRS_SUPPORT = 2 | |
439d7ac0 PB |
587 | }; |
588 | ||
2807cf69 | 589 | struct intel_dp; |
96178eeb VK |
590 | struct i915_drrs { |
591 | struct mutex mutex; | |
592 | struct delayed_work work; | |
593 | struct intel_dp *dp; | |
594 | unsigned busy_frontbuffer_bits; | |
595 | enum drrs_refresh_rate_type refresh_rate_type; | |
596 | enum drrs_support_type type; | |
597 | }; | |
598 | ||
a031d709 | 599 | struct i915_psr { |
f0355c4a | 600 | struct mutex lock; |
a031d709 | 601 | bool sink_support; |
2807cf69 | 602 | struct intel_dp *enabled; |
7c8f8a70 RV |
603 | bool active; |
604 | struct delayed_work work; | |
9ca15301 | 605 | unsigned busy_frontbuffer_bits; |
95f28d2e | 606 | bool sink_psr2_support; |
60e5ffe3 | 607 | bool link_standby; |
97da2ef4 | 608 | bool colorimetry_support; |
340c93c0 | 609 | bool alpm; |
5baf63cc | 610 | bool has_hw_tracking; |
95f28d2e | 611 | bool psr2_enabled; |
26e5378d | 612 | u8 sink_sync_latency; |
54fd3149 | 613 | bool debug; |
3f983e54 DP |
614 | ktime_t last_entry_attempt; |
615 | ktime_t last_exit; | |
424644c2 | 616 | |
d0d5e0d7 RV |
617 | void (*enable_source)(struct intel_dp *, |
618 | const struct intel_crtc_state *); | |
424644c2 RV |
619 | void (*disable_source)(struct intel_dp *, |
620 | const struct intel_crtc_state *); | |
49ad316f | 621 | void (*enable_sink)(struct intel_dp *); |
e3702ac9 | 622 | void (*activate)(struct intel_dp *); |
2a5db87f | 623 | void (*setup_vsc)(struct intel_dp *, const struct intel_crtc_state *); |
3f51e471 | 624 | }; |
5c3fe8b0 | 625 | |
3bad0781 | 626 | enum intel_pch { |
f0350830 | 627 | PCH_NONE = 0, /* No PCH present */ |
3bad0781 | 628 | PCH_IBX, /* Ibexpeak PCH */ |
243dec58 VS |
629 | PCH_CPT, /* Cougarpoint/Pantherpoint PCH */ |
630 | PCH_LPT, /* Lynxpoint/Wildcatpoint PCH */ | |
e7e7ea20 | 631 | PCH_SPT, /* Sunrisepoint PCH */ |
23247d71 RV |
632 | PCH_KBP, /* Kaby Lake PCH */ |
633 | PCH_CNP, /* Cannon Lake PCH */ | |
0b58436f | 634 | PCH_ICP, /* Ice Lake PCH */ |
40c7ead9 | 635 | PCH_NOP, |
3bad0781 ZW |
636 | }; |
637 | ||
988d6ee8 PZ |
638 | enum intel_sbi_destination { |
639 | SBI_ICLK, | |
640 | SBI_MPHY, | |
641 | }; | |
642 | ||
435793df | 643 | #define QUIRK_LVDS_SSC_DISABLE (1<<1) |
4dca20ef | 644 | #define QUIRK_INVERT_BRIGHTNESS (1<<2) |
9c72cc6f | 645 | #define QUIRK_BACKLIGHT_PRESENT (1<<3) |
656bfa3a | 646 | #define QUIRK_PIN_SWIZZLED_PAGES (1<<5) |
c99a259b | 647 | #define QUIRK_INCREASE_T12_DELAY (1<<6) |
b690e96c | 648 | |
8be48d92 | 649 | struct intel_fbdev; |
1630fe75 | 650 | struct intel_fbc_work; |
38651674 | 651 | |
c2b9152f DV |
652 | struct intel_gmbus { |
653 | struct i2c_adapter adapter; | |
3e4d44e0 | 654 | #define GMBUS_FORCE_BIT_RETRY (1U << 31) |
f2ce9faf | 655 | u32 force_bit; |
c2b9152f | 656 | u32 reg0; |
f0f59a00 | 657 | i915_reg_t gpio_reg; |
c167a6fc | 658 | struct i2c_algo_bit_data bit_algo; |
c2b9152f DV |
659 | struct drm_i915_private *dev_priv; |
660 | }; | |
661 | ||
f4c956ad | 662 | struct i915_suspend_saved_registers { |
e948e994 | 663 | u32 saveDSPARB; |
ba8bbcf6 | 664 | u32 saveFBC_CONTROL; |
1f84e550 | 665 | u32 saveCACHE_MODE_0; |
1f84e550 | 666 | u32 saveMI_ARB_STATE; |
ba8bbcf6 JB |
667 | u32 saveSWF0[16]; |
668 | u32 saveSWF1[16]; | |
85fa792b | 669 | u32 saveSWF3[3]; |
4b9de737 | 670 | uint64_t saveFENCE[I915_MAX_NUM_FENCES]; |
cda2bb78 | 671 | u32 savePCH_PORT_HOTPLUG; |
9f49c376 | 672 | u16 saveGCDGMBUS; |
f4c956ad | 673 | }; |
c85aa885 | 674 | |
ddeea5b0 ID |
675 | struct vlv_s0ix_state { |
676 | /* GAM */ | |
677 | u32 wr_watermark; | |
678 | u32 gfx_prio_ctrl; | |
679 | u32 arb_mode; | |
680 | u32 gfx_pend_tlb0; | |
681 | u32 gfx_pend_tlb1; | |
682 | u32 lra_limits[GEN7_LRA_LIMITS_REG_NUM]; | |
683 | u32 media_max_req_count; | |
684 | u32 gfx_max_req_count; | |
685 | u32 render_hwsp; | |
686 | u32 ecochk; | |
687 | u32 bsd_hwsp; | |
688 | u32 blt_hwsp; | |
689 | u32 tlb_rd_addr; | |
690 | ||
691 | /* MBC */ | |
692 | u32 g3dctl; | |
693 | u32 gsckgctl; | |
694 | u32 mbctl; | |
695 | ||
696 | /* GCP */ | |
697 | u32 ucgctl1; | |
698 | u32 ucgctl3; | |
699 | u32 rcgctl1; | |
700 | u32 rcgctl2; | |
701 | u32 rstctl; | |
702 | u32 misccpctl; | |
703 | ||
704 | /* GPM */ | |
705 | u32 gfxpause; | |
706 | u32 rpdeuhwtc; | |
707 | u32 rpdeuc; | |
708 | u32 ecobus; | |
709 | u32 pwrdwnupctl; | |
710 | u32 rp_down_timeout; | |
711 | u32 rp_deucsw; | |
712 | u32 rcubmabdtmr; | |
713 | u32 rcedata; | |
714 | u32 spare2gh; | |
715 | ||
716 | /* Display 1 CZ domain */ | |
717 | u32 gt_imr; | |
718 | u32 gt_ier; | |
719 | u32 pm_imr; | |
720 | u32 pm_ier; | |
721 | u32 gt_scratch[GEN7_GT_SCRATCH_REG_NUM]; | |
722 | ||
723 | /* GT SA CZ domain */ | |
724 | u32 tilectl; | |
725 | u32 gt_fifoctl; | |
726 | u32 gtlc_wake_ctrl; | |
727 | u32 gtlc_survive; | |
728 | u32 pmwgicz; | |
729 | ||
730 | /* Display 2 CZ domain */ | |
731 | u32 gu_ctl0; | |
732 | u32 gu_ctl1; | |
9c25210f | 733 | u32 pcbr; |
ddeea5b0 ID |
734 | u32 clock_gate_dis2; |
735 | }; | |
736 | ||
bf225f20 | 737 | struct intel_rps_ei { |
679cb6c1 | 738 | ktime_t ktime; |
bf225f20 CW |
739 | u32 render_c0; |
740 | u32 media_c0; | |
31685c25 D |
741 | }; |
742 | ||
562d9bae | 743 | struct intel_rps { |
d4d70aa5 ID |
744 | /* |
745 | * work, interrupts_enabled and pm_iir are protected by | |
746 | * dev_priv->irq_lock | |
747 | */ | |
c85aa885 | 748 | struct work_struct work; |
d4d70aa5 | 749 | bool interrupts_enabled; |
c85aa885 | 750 | u32 pm_iir; |
59cdb63d | 751 | |
b20e3cfe | 752 | /* PM interrupt bits that should never be masked */ |
5dd04556 | 753 | u32 pm_intrmsk_mbz; |
1800ad25 | 754 | |
b39fb297 BW |
755 | /* Frequencies are stored in potentially platform dependent multiples. |
756 | * In other words, *_freq needs to be multiplied by X to be interesting. | |
757 | * Soft limits are those which are used for the dynamic reclocking done | |
758 | * by the driver (raise frequencies under heavy loads, and lower for | |
759 | * lighter loads). Hard limits are those imposed by the hardware. | |
760 | * | |
761 | * A distinction is made for overclocking, which is never enabled by | |
762 | * default, and is considered to be above the hard limit if it's | |
763 | * possible at all. | |
764 | */ | |
765 | u8 cur_freq; /* Current frequency (cached, may not == HW) */ | |
766 | u8 min_freq_softlimit; /* Minimum frequency permitted by the driver */ | |
767 | u8 max_freq_softlimit; /* Max frequency permitted by the driver */ | |
768 | u8 max_freq; /* Maximum frequency, RP0 if not overclocking */ | |
769 | u8 min_freq; /* AKA RPn. Minimum frequency */ | |
29ecd78d | 770 | u8 boost_freq; /* Frequency to request when wait boosting */ |
aed242ff | 771 | u8 idle_freq; /* Frequency to request when we are idle */ |
b39fb297 BW |
772 | u8 efficient_freq; /* AKA RPe. Pre-determined balanced frequency */ |
773 | u8 rp1_freq; /* "less than" RP0 power/freqency */ | |
774 | u8 rp0_freq; /* Non-overclocked max frequency. */ | |
c30fec65 | 775 | u16 gpll_ref_freq; /* vlv/chv GPLL reference frequency */ |
1a01ab3b | 776 | |
8fb55197 CW |
777 | u8 up_threshold; /* Current %busy required to uplock */ |
778 | u8 down_threshold; /* Current %busy required to downclock */ | |
779 | ||
dd75fdc8 CW |
780 | int last_adj; |
781 | enum { LOW_POWER, BETWEEN, HIGH_POWER } power; | |
782 | ||
c0951f0c | 783 | bool enabled; |
7b92c1bd CW |
784 | atomic_t num_waiters; |
785 | atomic_t boosts; | |
4fc688ce | 786 | |
bf225f20 | 787 | /* manual wa residency calculations */ |
e0e8c7cb | 788 | struct intel_rps_ei ei; |
c85aa885 DV |
789 | }; |
790 | ||
37d933fc SAK |
791 | struct intel_rc6 { |
792 | bool enabled; | |
817cc079 TU |
793 | u64 prev_hw_residency[4]; |
794 | u64 cur_residency[4]; | |
37d933fc SAK |
795 | }; |
796 | ||
797 | struct intel_llc_pstate { | |
798 | bool enabled; | |
799 | }; | |
800 | ||
562d9bae SAK |
801 | struct intel_gen6_power_mgmt { |
802 | struct intel_rps rps; | |
37d933fc SAK |
803 | struct intel_rc6 rc6; |
804 | struct intel_llc_pstate llc_pstate; | |
562d9bae SAK |
805 | }; |
806 | ||
1a240d4d DV |
807 | /* defined intel_pm.c */ |
808 | extern spinlock_t mchdev_lock; | |
809 | ||
c85aa885 DV |
810 | struct intel_ilk_power_mgmt { |
811 | u8 cur_delay; | |
812 | u8 min_delay; | |
813 | u8 max_delay; | |
814 | u8 fmax; | |
815 | u8 fstart; | |
816 | ||
817 | u64 last_count1; | |
818 | unsigned long last_time1; | |
819 | unsigned long chipset_power; | |
820 | u64 last_count2; | |
5ed0bdf2 | 821 | u64 last_time2; |
c85aa885 DV |
822 | unsigned long gfx_power; |
823 | u8 corr; | |
824 | ||
825 | int c_m; | |
826 | int r_t; | |
827 | }; | |
828 | ||
c6cb582e ID |
829 | struct drm_i915_private; |
830 | struct i915_power_well; | |
831 | ||
832 | struct i915_power_well_ops { | |
833 | /* | |
834 | * Synchronize the well's hw state to match the current sw state, for | |
835 | * example enable/disable it based on the current refcount. Called | |
836 | * during driver init and resume time, possibly after first calling | |
837 | * the enable/disable handlers. | |
838 | */ | |
839 | void (*sync_hw)(struct drm_i915_private *dev_priv, | |
840 | struct i915_power_well *power_well); | |
841 | /* | |
842 | * Enable the well and resources that depend on it (for example | |
843 | * interrupts located on the well). Called after the 0->1 refcount | |
844 | * transition. | |
845 | */ | |
846 | void (*enable)(struct drm_i915_private *dev_priv, | |
847 | struct i915_power_well *power_well); | |
848 | /* | |
849 | * Disable the well and resources that depend on it. Called after | |
850 | * the 1->0 refcount transition. | |
851 | */ | |
852 | void (*disable)(struct drm_i915_private *dev_priv, | |
853 | struct i915_power_well *power_well); | |
854 | /* Returns the hw enabled state. */ | |
855 | bool (*is_enabled)(struct drm_i915_private *dev_priv, | |
856 | struct i915_power_well *power_well); | |
857 | }; | |
858 | ||
a38911a3 WX |
859 | /* Power well structure for haswell */ |
860 | struct i915_power_well { | |
c1ca727f | 861 | const char *name; |
6f3ef5dd | 862 | bool always_on; |
a38911a3 WX |
863 | /* power well enable/disable usage count */ |
864 | int count; | |
bfafe93a ID |
865 | /* cached hw enabled state */ |
866 | bool hw_enabled; | |
d8fc70b7 | 867 | u64 domains; |
01c3faa7 | 868 | /* unique identifier for this power well */ |
438b8dc4 | 869 | enum i915_power_well_id id; |
362624c9 ACO |
870 | /* |
871 | * Arbitraty data associated with this power well. Platform and power | |
872 | * well specific. | |
873 | */ | |
b5565a2e ID |
874 | union { |
875 | struct { | |
876 | enum dpio_phy phy; | |
877 | } bxt; | |
001bd2cb ID |
878 | struct { |
879 | /* Mask of pipes whose IRQ logic is backed by the pw */ | |
880 | u8 irq_pipe_mask; | |
881 | /* The pw is backing the VGA functionality */ | |
882 | bool has_vga:1; | |
b2891eb2 | 883 | bool has_fuses:1; |
001bd2cb | 884 | } hsw; |
b5565a2e | 885 | }; |
c6cb582e | 886 | const struct i915_power_well_ops *ops; |
a38911a3 WX |
887 | }; |
888 | ||
83c00f55 | 889 | struct i915_power_domains { |
baa70707 ID |
890 | /* |
891 | * Power wells needed for initialization at driver init and suspend | |
892 | * time are on. They are kept on until after the first modeset. | |
893 | */ | |
894 | bool init_power_on; | |
0d116a29 | 895 | bool initializing; |
c1ca727f | 896 | int power_well_count; |
baa70707 | 897 | |
83c00f55 | 898 | struct mutex lock; |
1da51581 | 899 | int domain_use_count[POWER_DOMAIN_NUM]; |
c1ca727f | 900 | struct i915_power_well *power_wells; |
83c00f55 ID |
901 | }; |
902 | ||
35a85ac6 | 903 | #define MAX_L3_SLICES 2 |
a4da4fa4 | 904 | struct intel_l3_parity { |
35a85ac6 | 905 | u32 *remap_info[MAX_L3_SLICES]; |
a4da4fa4 | 906 | struct work_struct error_work; |
35a85ac6 | 907 | int which_slice; |
a4da4fa4 DV |
908 | }; |
909 | ||
4b5aed62 | 910 | struct i915_gem_mm { |
4b5aed62 DV |
911 | /** Memory allocator for GTT stolen memory */ |
912 | struct drm_mm stolen; | |
92e97d2f PZ |
913 | /** Protects the usage of the GTT stolen memory allocator. This is |
914 | * always the inner lock when overlapping with struct_mutex. */ | |
915 | struct mutex stolen_lock; | |
916 | ||
f2123818 CW |
917 | /* Protects bound_list/unbound_list and #drm_i915_gem_object.mm.link */ |
918 | spinlock_t obj_lock; | |
919 | ||
4b5aed62 DV |
920 | /** List of all objects in gtt_space. Used to restore gtt |
921 | * mappings on resume */ | |
922 | struct list_head bound_list; | |
923 | /** | |
924 | * List of objects which are not bound to the GTT (thus | |
fbbd37b3 CW |
925 | * are idle and not used by the GPU). These objects may or may |
926 | * not actually have any pages attached. | |
4b5aed62 DV |
927 | */ |
928 | struct list_head unbound_list; | |
929 | ||
275f039d CW |
930 | /** List of all objects in gtt_space, currently mmaped by userspace. |
931 | * All objects within this list must also be on bound_list. | |
932 | */ | |
933 | struct list_head userfault_list; | |
934 | ||
fbbd37b3 CW |
935 | /** |
936 | * List of objects which are pending destruction. | |
937 | */ | |
938 | struct llist_head free_list; | |
939 | struct work_struct free_work; | |
87701b4b | 940 | spinlock_t free_lock; |
c9c70471 CW |
941 | /** |
942 | * Count of objects pending destructions. Used to skip needlessly | |
943 | * waiting on an RCU barrier if no objects are waiting to be freed. | |
944 | */ | |
945 | atomic_t free_count; | |
fbbd37b3 | 946 | |
66df1014 CW |
947 | /** |
948 | * Small stash of WC pages | |
949 | */ | |
950 | struct pagevec wc_stash; | |
951 | ||
465c403c MA |
952 | /** |
953 | * tmpfs instance used for shmem backed objects | |
954 | */ | |
955 | struct vfsmount *gemfs; | |
956 | ||
4b5aed62 DV |
957 | /** PPGTT used for aliasing the PPGTT with the GTT */ |
958 | struct i915_hw_ppgtt *aliasing_ppgtt; | |
959 | ||
2cfcd32a | 960 | struct notifier_block oom_notifier; |
e87666b5 | 961 | struct notifier_block vmap_notifier; |
ceabbba5 | 962 | struct shrinker shrinker; |
4b5aed62 | 963 | |
4b5aed62 DV |
964 | /** LRU list of objects with fence regs on them. */ |
965 | struct list_head fence_list; | |
966 | ||
8a2421bd CW |
967 | /** |
968 | * Workqueue to fault in userptr pages, flushed by the execbuf | |
969 | * when required but otherwise left to userspace to try again | |
970 | * on EAGAIN. | |
971 | */ | |
972 | struct workqueue_struct *userptr_wq; | |
973 | ||
94312828 CW |
974 | u64 unordered_timeline; |
975 | ||
bdf1e7e3 | 976 | /* the indicator for dispatch video commands on two BSD rings */ |
6f633402 | 977 | atomic_t bsd_engine_dispatch_index; |
bdf1e7e3 | 978 | |
4b5aed62 DV |
979 | /** Bit 6 swizzling required for X tiling */ |
980 | uint32_t bit_6_swizzle_x; | |
981 | /** Bit 6 swizzling required for Y tiling */ | |
982 | uint32_t bit_6_swizzle_y; | |
983 | ||
4b5aed62 | 984 | /* accounting, useful for userland debugging */ |
c20e8355 | 985 | spinlock_t object_stat_lock; |
3ef7f228 | 986 | u64 object_memory; |
4b5aed62 DV |
987 | u32 object_count; |
988 | }; | |
989 | ||
ee42c00e CW |
990 | #define I915_IDLE_ENGINES_TIMEOUT (200) /* in ms */ |
991 | ||
b52992c0 CW |
992 | #define I915_RESET_TIMEOUT (10 * HZ) /* 10s */ |
993 | #define I915_FENCE_TIMEOUT (10 * HZ) /* 10s */ | |
994 | ||
3fe3b030 MK |
995 | #define I915_ENGINE_DEAD_TIMEOUT (4 * HZ) /* Seqno, head and subunits dead */ |
996 | #define I915_SEQNO_DEAD_TIMEOUT (12 * HZ) /* Seqno dead with active head */ | |
997 | ||
b8efb17b ZR |
998 | enum modeset_restore { |
999 | MODESET_ON_LID_OPEN, | |
1000 | MODESET_DONE, | |
1001 | MODESET_SUSPENDED, | |
1002 | }; | |
1003 | ||
500ea70d RV |
1004 | #define DP_AUX_A 0x40 |
1005 | #define DP_AUX_B 0x10 | |
1006 | #define DP_AUX_C 0x20 | |
1007 | #define DP_AUX_D 0x30 | |
a324fcac | 1008 | #define DP_AUX_F 0x60 |
500ea70d | 1009 | |
11c1b657 XZ |
1010 | #define DDC_PIN_B 0x05 |
1011 | #define DDC_PIN_C 0x04 | |
1012 | #define DDC_PIN_D 0x06 | |
1013 | ||
6acab15a | 1014 | struct ddi_vbt_port_info { |
d6038611 VS |
1015 | int max_tmds_clock; |
1016 | ||
ce4dd49e DL |
1017 | /* |
1018 | * This is an index in the HDMI/DVI DDI buffer translation table. | |
1019 | * The special value HDMI_LEVEL_SHIFT_UNKNOWN means the VBT didn't | |
1020 | * populate this field. | |
1021 | */ | |
1022 | #define HDMI_LEVEL_SHIFT_UNKNOWN 0xff | |
6acab15a | 1023 | uint8_t hdmi_level_shift; |
311a2094 PZ |
1024 | |
1025 | uint8_t supports_dvi:1; | |
1026 | uint8_t supports_hdmi:1; | |
1027 | uint8_t supports_dp:1; | |
a98d9c1d | 1028 | uint8_t supports_edp:1; |
500ea70d RV |
1029 | |
1030 | uint8_t alternate_aux_channel; | |
11c1b657 | 1031 | uint8_t alternate_ddc_pin; |
75067dde AK |
1032 | |
1033 | uint8_t dp_boost_level; | |
1034 | uint8_t hdmi_boost_level; | |
99b91bda | 1035 | int dp_max_link_rate; /* 0 for not limited by VBT */ |
6acab15a PZ |
1036 | }; |
1037 | ||
bfd7ebda RV |
1038 | enum psr_lines_to_wait { |
1039 | PSR_0_LINES_TO_WAIT = 0, | |
1040 | PSR_1_LINE_TO_WAIT, | |
1041 | PSR_4_LINES_TO_WAIT, | |
1042 | PSR_8_LINES_TO_WAIT | |
83a7280e PB |
1043 | }; |
1044 | ||
41aa3448 RV |
1045 | struct intel_vbt_data { |
1046 | struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */ | |
1047 | struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */ | |
1048 | ||
1049 | /* Feature bits */ | |
1050 | unsigned int int_tv_support:1; | |
1051 | unsigned int lvds_dither:1; | |
1052 | unsigned int lvds_vbt:1; | |
1053 | unsigned int int_crt_support:1; | |
1054 | unsigned int lvds_use_ssc:1; | |
1055 | unsigned int display_clock_mode:1; | |
1056 | unsigned int fdi_rx_polarity_inverted:1; | |
3e845c7a | 1057 | unsigned int panel_type:4; |
41aa3448 RV |
1058 | int lvds_ssc_freq; |
1059 | unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */ | |
1060 | ||
83a7280e PB |
1061 | enum drrs_support_type drrs_type; |
1062 | ||
6aa23e65 JN |
1063 | struct { |
1064 | int rate; | |
1065 | int lanes; | |
1066 | int preemphasis; | |
1067 | int vswing; | |
06411f08 | 1068 | bool low_vswing; |
6aa23e65 JN |
1069 | bool initialized; |
1070 | bool support; | |
1071 | int bpp; | |
1072 | struct edp_power_seq pps; | |
1073 | } edp; | |
41aa3448 | 1074 | |
bfd7ebda | 1075 | struct { |
2bdd045e | 1076 | bool enable; |
bfd7ebda RV |
1077 | bool full_link; |
1078 | bool require_aux_wakeup; | |
1079 | int idle_frames; | |
1080 | enum psr_lines_to_wait lines_to_wait; | |
1081 | int tp1_wakeup_time; | |
1082 | int tp2_tp3_wakeup_time; | |
1083 | } psr; | |
1084 | ||
f00076d2 JN |
1085 | struct { |
1086 | u16 pwm_freq_hz; | |
39fbc9c8 | 1087 | bool present; |
f00076d2 | 1088 | bool active_low_pwm; |
1de6068e | 1089 | u8 min_brightness; /* min_brightness/255 of max */ |
add03379 | 1090 | u8 controller; /* brightness controller number */ |
9a41e17d | 1091 | enum intel_backlight_type type; |
f00076d2 JN |
1092 | } backlight; |
1093 | ||
d17c5443 SK |
1094 | /* MIPI DSI */ |
1095 | struct { | |
1096 | u16 panel_id; | |
d3b542fc SK |
1097 | struct mipi_config *config; |
1098 | struct mipi_pps_data *pps; | |
46e58320 MC |
1099 | u16 bl_ports; |
1100 | u16 cabc_ports; | |
d3b542fc SK |
1101 | u8 seq_version; |
1102 | u32 size; | |
1103 | u8 *data; | |
8d3ed2f3 | 1104 | const u8 *sequence[MIPI_SEQ_MAX]; |
fb38e7ad | 1105 | u8 *deassert_seq; /* Used by fixup_mipi_sequences() */ |
d17c5443 SK |
1106 | } dsi; |
1107 | ||
41aa3448 RV |
1108 | int crt_ddc_pin; |
1109 | ||
1110 | int child_dev_num; | |
cc998589 | 1111 | struct child_device_config *child_dev; |
6acab15a PZ |
1112 | |
1113 | struct ddi_vbt_port_info ddi_port_info[I915_MAX_PORTS]; | |
9d6c875d | 1114 | struct sdvo_device_mapping sdvo_mappings[2]; |
41aa3448 RV |
1115 | }; |
1116 | ||
77c122bc VS |
1117 | enum intel_ddb_partitioning { |
1118 | INTEL_DDB_PART_1_2, | |
1119 | INTEL_DDB_PART_5_6, /* IVB+ */ | |
1120 | }; | |
1121 | ||
1fd527cc VS |
1122 | struct intel_wm_level { |
1123 | bool enable; | |
1124 | uint32_t pri_val; | |
1125 | uint32_t spr_val; | |
1126 | uint32_t cur_val; | |
1127 | uint32_t fbc_val; | |
1128 | }; | |
1129 | ||
820c1980 | 1130 | struct ilk_wm_values { |
609cedef VS |
1131 | uint32_t wm_pipe[3]; |
1132 | uint32_t wm_lp[3]; | |
1133 | uint32_t wm_lp_spr[3]; | |
1134 | uint32_t wm_linetime[3]; | |
1135 | bool enable_fbc_wm; | |
1136 | enum intel_ddb_partitioning partitioning; | |
1137 | }; | |
1138 | ||
114d7dc0 | 1139 | struct g4x_pipe_wm { |
1b31389c | 1140 | uint16_t plane[I915_MAX_PLANES]; |
04548cba | 1141 | uint16_t fbc; |
262cd2e1 | 1142 | }; |
ae80152d | 1143 | |
114d7dc0 | 1144 | struct g4x_sr_wm { |
262cd2e1 | 1145 | uint16_t plane; |
1b31389c | 1146 | uint16_t cursor; |
04548cba | 1147 | uint16_t fbc; |
1b31389c VS |
1148 | }; |
1149 | ||
1150 | struct vlv_wm_ddl_values { | |
1151 | uint8_t plane[I915_MAX_PLANES]; | |
262cd2e1 | 1152 | }; |
ae80152d | 1153 | |
262cd2e1 | 1154 | struct vlv_wm_values { |
114d7dc0 VS |
1155 | struct g4x_pipe_wm pipe[3]; |
1156 | struct g4x_sr_wm sr; | |
1b31389c | 1157 | struct vlv_wm_ddl_values ddl[3]; |
6eb1a681 VS |
1158 | uint8_t level; |
1159 | bool cxsr; | |
0018fda1 VS |
1160 | }; |
1161 | ||
04548cba VS |
1162 | struct g4x_wm_values { |
1163 | struct g4x_pipe_wm pipe[2]; | |
1164 | struct g4x_sr_wm sr; | |
1165 | struct g4x_sr_wm hpll; | |
1166 | bool cxsr; | |
1167 | bool hpll_en; | |
1168 | bool fbc_en; | |
1169 | }; | |
1170 | ||
c193924e | 1171 | struct skl_ddb_entry { |
16160e3d | 1172 | uint16_t start, end; /* in number of blocks, 'end' is exclusive */ |
c193924e DL |
1173 | }; |
1174 | ||
1175 | static inline uint16_t skl_ddb_entry_size(const struct skl_ddb_entry *entry) | |
1176 | { | |
16160e3d | 1177 | return entry->end - entry->start; |
c193924e DL |
1178 | } |
1179 | ||
08db6652 DL |
1180 | static inline bool skl_ddb_entry_equal(const struct skl_ddb_entry *e1, |
1181 | const struct skl_ddb_entry *e2) | |
1182 | { | |
1183 | if (e1->start == e2->start && e1->end == e2->end) | |
1184 | return true; | |
1185 | ||
1186 | return false; | |
1187 | } | |
1188 | ||
c193924e | 1189 | struct skl_ddb_allocation { |
b879d58f MK |
1190 | /* packed/y */ |
1191 | struct skl_ddb_entry plane[I915_MAX_PIPES][I915_MAX_PLANES]; | |
1192 | struct skl_ddb_entry uv_plane[I915_MAX_PIPES][I915_MAX_PLANES]; | |
74bd8004 | 1193 | u8 enabled_slices; /* GEN11 has configurable 2 slices */ |
c193924e DL |
1194 | }; |
1195 | ||
60f8e873 | 1196 | struct skl_ddb_values { |
2b4b9f35 | 1197 | unsigned dirty_pipes; |
c193924e | 1198 | struct skl_ddb_allocation ddb; |
2ac96d2a PB |
1199 | }; |
1200 | ||
1201 | struct skl_wm_level { | |
a62163e9 L |
1202 | bool plane_en; |
1203 | uint16_t plane_res_b; | |
1204 | uint8_t plane_res_l; | |
2ac96d2a PB |
1205 | }; |
1206 | ||
7e452fdb KM |
1207 | /* Stores plane specific WM parameters */ |
1208 | struct skl_wm_params { | |
1209 | bool x_tiled, y_tiled; | |
1210 | bool rc_surface; | |
942aa2d0 | 1211 | bool is_planar; |
7e452fdb KM |
1212 | uint32_t width; |
1213 | uint8_t cpp; | |
1214 | uint32_t plane_pixel_rate; | |
1215 | uint32_t y_min_scanlines; | |
1216 | uint32_t plane_bytes_per_line; | |
1217 | uint_fixed_16_16_t plane_blocks_per_line; | |
1218 | uint_fixed_16_16_t y_tile_minimum; | |
1219 | uint32_t linetime_us; | |
df8ee190 | 1220 | uint32_t dbuf_block_size; |
7e452fdb KM |
1221 | }; |
1222 | ||
c67a470b | 1223 | /* |
765dab67 PZ |
1224 | * This struct helps tracking the state needed for runtime PM, which puts the |
1225 | * device in PCI D3 state. Notice that when this happens, nothing on the | |
1226 | * graphics device works, even register access, so we don't get interrupts nor | |
1227 | * anything else. | |
c67a470b | 1228 | * |
765dab67 PZ |
1229 | * Every piece of our code that needs to actually touch the hardware needs to |
1230 | * either call intel_runtime_pm_get or call intel_display_power_get with the | |
1231 | * appropriate power domain. | |
a8a8bd54 | 1232 | * |
765dab67 PZ |
1233 | * Our driver uses the autosuspend delay feature, which means we'll only really |
1234 | * suspend if we stay with zero refcount for a certain amount of time. The | |
f458ebbc | 1235 | * default value is currently very conservative (see intel_runtime_pm_enable), but |
765dab67 | 1236 | * it can be changed with the standard runtime PM files from sysfs. |
c67a470b PZ |
1237 | * |
1238 | * The irqs_disabled variable becomes true exactly after we disable the IRQs and | |
1239 | * goes back to false exactly before we reenable the IRQs. We use this variable | |
1240 | * to check if someone is trying to enable/disable IRQs while they're supposed | |
1241 | * to be disabled. This shouldn't happen and we'll print some error messages in | |
730488b2 | 1242 | * case it happens. |
c67a470b | 1243 | * |
765dab67 | 1244 | * For more, read the Documentation/power/runtime_pm.txt. |
c67a470b | 1245 | */ |
5d584b2e | 1246 | struct i915_runtime_pm { |
1f814dac | 1247 | atomic_t wakeref_count; |
5d584b2e | 1248 | bool suspended; |
2aeb7d3a | 1249 | bool irqs_enabled; |
c67a470b PZ |
1250 | }; |
1251 | ||
926321d5 DV |
1252 | enum intel_pipe_crc_source { |
1253 | INTEL_PIPE_CRC_SOURCE_NONE, | |
1254 | INTEL_PIPE_CRC_SOURCE_PLANE1, | |
1255 | INTEL_PIPE_CRC_SOURCE_PLANE2, | |
1256 | INTEL_PIPE_CRC_SOURCE_PF, | |
5b3a856b | 1257 | INTEL_PIPE_CRC_SOURCE_PIPE, |
3d099a05 DV |
1258 | /* TV/DP on pre-gen5/vlv can't use the pipe source. */ |
1259 | INTEL_PIPE_CRC_SOURCE_TV, | |
1260 | INTEL_PIPE_CRC_SOURCE_DP_B, | |
1261 | INTEL_PIPE_CRC_SOURCE_DP_C, | |
1262 | INTEL_PIPE_CRC_SOURCE_DP_D, | |
46a19188 | 1263 | INTEL_PIPE_CRC_SOURCE_AUTO, |
926321d5 DV |
1264 | INTEL_PIPE_CRC_SOURCE_MAX, |
1265 | }; | |
1266 | ||
8bf1e9f1 | 1267 | struct intel_pipe_crc_entry { |
ac2300d4 | 1268 | uint32_t frame; |
8bf1e9f1 SH |
1269 | uint32_t crc[5]; |
1270 | }; | |
1271 | ||
b2c88f5b | 1272 | #define INTEL_PIPE_CRC_ENTRIES_NR 128 |
8bf1e9f1 | 1273 | struct intel_pipe_crc { |
d538bbdf DL |
1274 | spinlock_t lock; |
1275 | bool opened; /* exclusive access to the result file */ | |
e5f75aca | 1276 | struct intel_pipe_crc_entry *entries; |
926321d5 | 1277 | enum intel_pipe_crc_source source; |
d538bbdf | 1278 | int head, tail; |
07144428 | 1279 | wait_queue_head_t wq; |
8c6b709d | 1280 | int skipped; |
8bf1e9f1 SH |
1281 | }; |
1282 | ||
f99d7069 | 1283 | struct i915_frontbuffer_tracking { |
b5add959 | 1284 | spinlock_t lock; |
f99d7069 DV |
1285 | |
1286 | /* | |
1287 | * Tracking bits for delayed frontbuffer flushing du to gpu activity or | |
1288 | * scheduled flips. | |
1289 | */ | |
1290 | unsigned busy_bits; | |
1291 | unsigned flip_bits; | |
1292 | }; | |
1293 | ||
7225342a | 1294 | struct i915_wa_reg { |
f0f59a00 | 1295 | i915_reg_t addr; |
7225342a MK |
1296 | u32 value; |
1297 | /* bitmask representing WA bits */ | |
1298 | u32 mask; | |
1299 | }; | |
1300 | ||
d6242aeb | 1301 | #define I915_MAX_WA_REGS 16 |
7225342a MK |
1302 | |
1303 | struct i915_workarounds { | |
1304 | struct i915_wa_reg reg[I915_MAX_WA_REGS]; | |
1305 | u32 count; | |
1306 | }; | |
1307 | ||
cf9d2890 YZ |
1308 | struct i915_virtual_gpu { |
1309 | bool active; | |
8a4ab66f | 1310 | u32 caps; |
cf9d2890 YZ |
1311 | }; |
1312 | ||
aa363136 MR |
1313 | /* used in computing the new watermarks state */ |
1314 | struct intel_wm_config { | |
1315 | unsigned int num_pipes_active; | |
1316 | bool sprites_enabled; | |
1317 | bool sprites_scaled; | |
1318 | }; | |
1319 | ||
d7965152 RB |
1320 | struct i915_oa_format { |
1321 | u32 format; | |
1322 | int size; | |
1323 | }; | |
1324 | ||
8a3003dd RB |
1325 | struct i915_oa_reg { |
1326 | i915_reg_t addr; | |
1327 | u32 value; | |
1328 | }; | |
1329 | ||
701f8231 LL |
1330 | struct i915_oa_config { |
1331 | char uuid[UUID_STRING_LEN + 1]; | |
1332 | int id; | |
1333 | ||
1334 | const struct i915_oa_reg *mux_regs; | |
1335 | u32 mux_regs_len; | |
1336 | const struct i915_oa_reg *b_counter_regs; | |
1337 | u32 b_counter_regs_len; | |
1338 | const struct i915_oa_reg *flex_regs; | |
1339 | u32 flex_regs_len; | |
1340 | ||
1341 | struct attribute_group sysfs_metric; | |
1342 | struct attribute *attrs[2]; | |
1343 | struct device_attribute sysfs_metric_id; | |
f89823c2 LL |
1344 | |
1345 | atomic_t ref_count; | |
701f8231 LL |
1346 | }; |
1347 | ||
eec688e1 RB |
1348 | struct i915_perf_stream; |
1349 | ||
16d98b31 RB |
1350 | /** |
1351 | * struct i915_perf_stream_ops - the OPs to support a specific stream type | |
1352 | */ | |
eec688e1 | 1353 | struct i915_perf_stream_ops { |
16d98b31 RB |
1354 | /** |
1355 | * @enable: Enables the collection of HW samples, either in response to | |
1356 | * `I915_PERF_IOCTL_ENABLE` or implicitly called when stream is opened | |
1357 | * without `I915_PERF_FLAG_DISABLED`. | |
eec688e1 RB |
1358 | */ |
1359 | void (*enable)(struct i915_perf_stream *stream); | |
1360 | ||
16d98b31 RB |
1361 | /** |
1362 | * @disable: Disables the collection of HW samples, either in response | |
1363 | * to `I915_PERF_IOCTL_DISABLE` or implicitly called before destroying | |
1364 | * the stream. | |
eec688e1 RB |
1365 | */ |
1366 | void (*disable)(struct i915_perf_stream *stream); | |
1367 | ||
16d98b31 RB |
1368 | /** |
1369 | * @poll_wait: Call poll_wait, passing a wait queue that will be woken | |
eec688e1 RB |
1370 | * once there is something ready to read() for the stream |
1371 | */ | |
1372 | void (*poll_wait)(struct i915_perf_stream *stream, | |
1373 | struct file *file, | |
1374 | poll_table *wait); | |
1375 | ||
16d98b31 RB |
1376 | /** |
1377 | * @wait_unlocked: For handling a blocking read, wait until there is | |
1378 | * something to ready to read() for the stream. E.g. wait on the same | |
d7965152 | 1379 | * wait queue that would be passed to poll_wait(). |
eec688e1 RB |
1380 | */ |
1381 | int (*wait_unlocked)(struct i915_perf_stream *stream); | |
1382 | ||
16d98b31 RB |
1383 | /** |
1384 | * @read: Copy buffered metrics as records to userspace | |
1385 | * **buf**: the userspace, destination buffer | |
1386 | * **count**: the number of bytes to copy, requested by userspace | |
1387 | * **offset**: zero at the start of the read, updated as the read | |
1388 | * proceeds, it represents how many bytes have been copied so far and | |
1389 | * the buffer offset for copying the next record. | |
eec688e1 | 1390 | * |
16d98b31 RB |
1391 | * Copy as many buffered i915 perf samples and records for this stream |
1392 | * to userspace as will fit in the given buffer. | |
eec688e1 | 1393 | * |
16d98b31 RB |
1394 | * Only write complete records; returning -%ENOSPC if there isn't room |
1395 | * for a complete record. | |
eec688e1 | 1396 | * |
16d98b31 RB |
1397 | * Return any error condition that results in a short read such as |
1398 | * -%ENOSPC or -%EFAULT, even though these may be squashed before | |
1399 | * returning to userspace. | |
eec688e1 RB |
1400 | */ |
1401 | int (*read)(struct i915_perf_stream *stream, | |
1402 | char __user *buf, | |
1403 | size_t count, | |
1404 | size_t *offset); | |
1405 | ||
16d98b31 RB |
1406 | /** |
1407 | * @destroy: Cleanup any stream specific resources. | |
eec688e1 RB |
1408 | * |
1409 | * The stream will always be disabled before this is called. | |
1410 | */ | |
1411 | void (*destroy)(struct i915_perf_stream *stream); | |
1412 | }; | |
1413 | ||
16d98b31 RB |
1414 | /** |
1415 | * struct i915_perf_stream - state for a single open stream FD | |
1416 | */ | |
eec688e1 | 1417 | struct i915_perf_stream { |
16d98b31 RB |
1418 | /** |
1419 | * @dev_priv: i915 drm device | |
1420 | */ | |
eec688e1 RB |
1421 | struct drm_i915_private *dev_priv; |
1422 | ||
16d98b31 RB |
1423 | /** |
1424 | * @link: Links the stream into ``&drm_i915_private->streams`` | |
1425 | */ | |
eec688e1 RB |
1426 | struct list_head link; |
1427 | ||
16d98b31 RB |
1428 | /** |
1429 | * @sample_flags: Flags representing the `DRM_I915_PERF_PROP_SAMPLE_*` | |
1430 | * properties given when opening a stream, representing the contents | |
1431 | * of a single sample as read() by userspace. | |
1432 | */ | |
eec688e1 | 1433 | u32 sample_flags; |
16d98b31 RB |
1434 | |
1435 | /** | |
1436 | * @sample_size: Considering the configured contents of a sample | |
1437 | * combined with the required header size, this is the total size | |
1438 | * of a single sample record. | |
1439 | */ | |
d7965152 | 1440 | int sample_size; |
eec688e1 | 1441 | |
16d98b31 RB |
1442 | /** |
1443 | * @ctx: %NULL if measuring system-wide across all contexts or a | |
1444 | * specific context that is being monitored. | |
1445 | */ | |
eec688e1 | 1446 | struct i915_gem_context *ctx; |
16d98b31 RB |
1447 | |
1448 | /** | |
1449 | * @enabled: Whether the stream is currently enabled, considering | |
1450 | * whether the stream was opened in a disabled state and based | |
1451 | * on `I915_PERF_IOCTL_ENABLE` and `I915_PERF_IOCTL_DISABLE` calls. | |
1452 | */ | |
eec688e1 RB |
1453 | bool enabled; |
1454 | ||
16d98b31 RB |
1455 | /** |
1456 | * @ops: The callbacks providing the implementation of this specific | |
1457 | * type of configured stream. | |
1458 | */ | |
d7965152 | 1459 | const struct i915_perf_stream_ops *ops; |
701f8231 LL |
1460 | |
1461 | /** | |
1462 | * @oa_config: The OA configuration used by the stream. | |
1463 | */ | |
1464 | struct i915_oa_config *oa_config; | |
d7965152 RB |
1465 | }; |
1466 | ||
16d98b31 RB |
1467 | /** |
1468 | * struct i915_oa_ops - Gen specific implementation of an OA unit stream | |
1469 | */ | |
d7965152 | 1470 | struct i915_oa_ops { |
f89823c2 LL |
1471 | /** |
1472 | * @is_valid_b_counter_reg: Validates register's address for | |
1473 | * programming boolean counters for a particular platform. | |
1474 | */ | |
1475 | bool (*is_valid_b_counter_reg)(struct drm_i915_private *dev_priv, | |
1476 | u32 addr); | |
1477 | ||
1478 | /** | |
1479 | * @is_valid_mux_reg: Validates register's address for programming mux | |
1480 | * for a particular platform. | |
1481 | */ | |
1482 | bool (*is_valid_mux_reg)(struct drm_i915_private *dev_priv, u32 addr); | |
1483 | ||
1484 | /** | |
1485 | * @is_valid_flex_reg: Validates register's address for programming | |
1486 | * flex EU filtering for a particular platform. | |
1487 | */ | |
1488 | bool (*is_valid_flex_reg)(struct drm_i915_private *dev_priv, u32 addr); | |
1489 | ||
16d98b31 RB |
1490 | /** |
1491 | * @init_oa_buffer: Resets the head and tail pointers of the | |
1492 | * circular buffer for periodic OA reports. | |
1493 | * | |
1494 | * Called when first opening a stream for OA metrics, but also may be | |
1495 | * called in response to an OA buffer overflow or other error | |
1496 | * condition. | |
1497 | * | |
1498 | * Note it may be necessary to clear the full OA buffer here as part of | |
1499 | * maintaining the invariable that new reports must be written to | |
1500 | * zeroed memory for us to be able to reliable detect if an expected | |
1501 | * report has not yet landed in memory. (At least on Haswell the OA | |
1502 | * buffer tail pointer is not synchronized with reports being visible | |
1503 | * to the CPU) | |
1504 | */ | |
d7965152 | 1505 | void (*init_oa_buffer)(struct drm_i915_private *dev_priv); |
16d98b31 | 1506 | |
19f81df2 RB |
1507 | /** |
1508 | * @enable_metric_set: Selects and applies any MUX configuration to set | |
1509 | * up the Boolean and Custom (B/C) counters that are part of the | |
1510 | * counter reports being sampled. May apply system constraints such as | |
16d98b31 RB |
1511 | * disabling EU clock gating as required. |
1512 | */ | |
701f8231 LL |
1513 | int (*enable_metric_set)(struct drm_i915_private *dev_priv, |
1514 | const struct i915_oa_config *oa_config); | |
16d98b31 RB |
1515 | |
1516 | /** | |
1517 | * @disable_metric_set: Remove system constraints associated with using | |
1518 | * the OA unit. | |
1519 | */ | |
d7965152 | 1520 | void (*disable_metric_set)(struct drm_i915_private *dev_priv); |
16d98b31 RB |
1521 | |
1522 | /** | |
1523 | * @oa_enable: Enable periodic sampling | |
1524 | */ | |
d7965152 | 1525 | void (*oa_enable)(struct drm_i915_private *dev_priv); |
16d98b31 RB |
1526 | |
1527 | /** | |
1528 | * @oa_disable: Disable periodic sampling | |
1529 | */ | |
d7965152 | 1530 | void (*oa_disable)(struct drm_i915_private *dev_priv); |
16d98b31 RB |
1531 | |
1532 | /** | |
1533 | * @read: Copy data from the circular OA buffer into a given userspace | |
1534 | * buffer. | |
1535 | */ | |
d7965152 RB |
1536 | int (*read)(struct i915_perf_stream *stream, |
1537 | char __user *buf, | |
1538 | size_t count, | |
1539 | size_t *offset); | |
16d98b31 RB |
1540 | |
1541 | /** | |
19f81df2 | 1542 | * @oa_hw_tail_read: read the OA tail pointer register |
16d98b31 | 1543 | * |
19f81df2 RB |
1544 | * In particular this enables us to share all the fiddly code for |
1545 | * handling the OA unit tail pointer race that affects multiple | |
1546 | * generations. | |
16d98b31 | 1547 | */ |
19f81df2 | 1548 | u32 (*oa_hw_tail_read)(struct drm_i915_private *dev_priv); |
eec688e1 RB |
1549 | }; |
1550 | ||
49cd97a3 | 1551 | struct intel_cdclk_state { |
b6c51c3e | 1552 | unsigned int cdclk, vco, ref, bypass; |
64600bd5 | 1553 | u8 voltage_level; |
49cd97a3 VS |
1554 | }; |
1555 | ||
77fec556 | 1556 | struct drm_i915_private { |
8f460e2c CW |
1557 | struct drm_device drm; |
1558 | ||
efab6d8d | 1559 | struct kmem_cache *objects; |
e20d2ab7 | 1560 | struct kmem_cache *vmas; |
d1b48c1e | 1561 | struct kmem_cache *luts; |
efab6d8d | 1562 | struct kmem_cache *requests; |
52e54209 | 1563 | struct kmem_cache *dependencies; |
c5cf9a91 | 1564 | struct kmem_cache *priorities; |
f4c956ad | 1565 | |
5c969aa7 | 1566 | const struct intel_device_info info; |
3fed1808 | 1567 | struct intel_driver_caps caps; |
f4c956ad | 1568 | |
77894226 MA |
1569 | /** |
1570 | * Data Stolen Memory - aka "i915 stolen memory" gives us the start and | |
1571 | * end of stolen which we can optionally use to create GEM objects | |
b1ace601 | 1572 | * backed by stolen memory. Note that stolen_usable_size tells us |
77894226 MA |
1573 | * exactly how much of this we are actually allowed to use, given that |
1574 | * some portion of it is in fact reserved for use by hardware functions. | |
1575 | */ | |
1576 | struct resource dsm; | |
17a05345 MA |
1577 | /** |
1578 | * Reseved portion of Data Stolen Memory | |
1579 | */ | |
1580 | struct resource dsm_reserved; | |
77894226 | 1581 | |
b1ace601 MA |
1582 | /* |
1583 | * Stolen memory is segmented in hardware with different portions | |
1584 | * offlimits to certain functions. | |
1585 | * | |
1586 | * The drm_mm is initialised to the total accessible range, as found | |
1587 | * from the PCI config. On Broadwell+, this is further restricted to | |
1588 | * avoid the first page! The upper end of stolen memory is reserved for | |
1589 | * hardware functions and similarly removed from the accessible range. | |
1590 | */ | |
b7128ef1 | 1591 | resource_size_t stolen_usable_size; /* Total size minus reserved ranges */ |
b1ace601 | 1592 | |
f4c956ad DV |
1593 | void __iomem *regs; |
1594 | ||
907b28c5 | 1595 | struct intel_uncore uncore; |
f4c956ad | 1596 | |
cf9d2890 YZ |
1597 | struct i915_virtual_gpu vgpu; |
1598 | ||
feddf6e8 | 1599 | struct intel_gvt *gvt; |
0ad35fed | 1600 | |
6b0478fb JL |
1601 | struct intel_wopcm wopcm; |
1602 | ||
bd132858 | 1603 | struct intel_huc huc; |
33a732f4 AD |
1604 | struct intel_guc guc; |
1605 | ||
eb805623 DV |
1606 | struct intel_csr csr; |
1607 | ||
5ea6e5e3 | 1608 | struct intel_gmbus gmbus[GMBUS_NUM_PINS]; |
28c70f16 | 1609 | |
f4c956ad DV |
1610 | /** gmbus_mutex protects against concurrent usage of the single hw gmbus |
1611 | * controller on different i2c buses. */ | |
1612 | struct mutex gmbus_mutex; | |
1613 | ||
1614 | /** | |
1615 | * Base address of the gmbus and gpio block. | |
1616 | */ | |
1617 | uint32_t gpio_mmio_base; | |
1618 | ||
b6fdd0f2 SS |
1619 | /* MMIO base address for MIPI regs */ |
1620 | uint32_t mipi_mmio_base; | |
1621 | ||
443a389f VS |
1622 | uint32_t psr_mmio_base; |
1623 | ||
44cb734c ID |
1624 | uint32_t pps_mmio_base; |
1625 | ||
28c70f16 DV |
1626 | wait_queue_head_t gmbus_wait_queue; |
1627 | ||
f4c956ad | 1628 | struct pci_dev *bridge_dev; |
3b3f1650 | 1629 | struct intel_engine_cs *engine[I915_NUM_ENGINES]; |
e7af3116 CW |
1630 | /* Context used internally to idle the GPU and setup initial state */ |
1631 | struct i915_gem_context *kernel_context; | |
1632 | /* Context only to be used for injecting preemption commands */ | |
1633 | struct i915_gem_context *preempt_context; | |
b46a33e2 TU |
1634 | struct intel_engine_cs *engine_class[MAX_ENGINE_CLASS + 1] |
1635 | [MAX_ENGINE_INSTANCE + 1]; | |
f4c956ad | 1636 | |
ba8286fa | 1637 | struct drm_dma_handle *status_page_dmah; |
f4c956ad DV |
1638 | struct resource mch_res; |
1639 | ||
f4c956ad DV |
1640 | /* protects the irq masks */ |
1641 | spinlock_t irq_lock; | |
1642 | ||
f8b79e58 ID |
1643 | bool display_irqs_enabled; |
1644 | ||
9ee32fea DV |
1645 | /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */ |
1646 | struct pm_qos_request pm_qos; | |
1647 | ||
a580516d VS |
1648 | /* Sideband mailbox protection */ |
1649 | struct mutex sb_lock; | |
f4c956ad DV |
1650 | |
1651 | /** Cached value of IMR to avoid reads in updating the bitfield */ | |
abd58f01 BW |
1652 | union { |
1653 | u32 irq_mask; | |
1654 | u32 de_irq_mask[I915_MAX_PIPES]; | |
1655 | }; | |
f4c956ad | 1656 | u32 gt_irq_mask; |
f4e9af4f AG |
1657 | u32 pm_imr; |
1658 | u32 pm_ier; | |
a6706b45 | 1659 | u32 pm_rps_events; |
26705e20 | 1660 | u32 pm_guc_events; |
91d181dd | 1661 | u32 pipestat_irq_mask[I915_MAX_PIPES]; |
f4c956ad | 1662 | |
5fcece80 | 1663 | struct i915_hotplug hotplug; |
ab34a7e8 | 1664 | struct intel_fbc fbc; |
439d7ac0 | 1665 | struct i915_drrs drrs; |
f4c956ad | 1666 | struct intel_opregion opregion; |
41aa3448 | 1667 | struct intel_vbt_data vbt; |
f4c956ad | 1668 | |
d9ceb816 JB |
1669 | bool preserve_bios_swizzle; |
1670 | ||
f4c956ad DV |
1671 | /* overlay */ |
1672 | struct intel_overlay *overlay; | |
f4c956ad | 1673 | |
58c68779 | 1674 | /* backlight registers and fields in struct intel_panel */ |
07f11d49 | 1675 | struct mutex backlight_lock; |
31ad8ec6 | 1676 | |
f4c956ad | 1677 | /* LVDS info */ |
f4c956ad DV |
1678 | bool no_aux_handshake; |
1679 | ||
e39b999a VS |
1680 | /* protects panel power sequencer state */ |
1681 | struct mutex pps_mutex; | |
1682 | ||
f4c956ad | 1683 | struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; /* assume 965 */ |
f4c956ad DV |
1684 | int num_fence_regs; /* 8 on pre-965, 16 otherwise */ |
1685 | ||
1686 | unsigned int fsb_freq, mem_freq, is_ddr3; | |
b2045352 | 1687 | unsigned int skl_preferred_vco_freq; |
49cd97a3 | 1688 | unsigned int max_cdclk_freq; |
8d96561a | 1689 | |
adafdc6f | 1690 | unsigned int max_dotclk_freq; |
e7dc33f3 | 1691 | unsigned int rawclk_freq; |
6bcda4f0 | 1692 | unsigned int hpll_freq; |
58ecd9d5 | 1693 | unsigned int fdi_pll_freq; |
bfa7df01 | 1694 | unsigned int czclk_freq; |
f4c956ad | 1695 | |
63911d72 | 1696 | struct { |
bb0f4aab VS |
1697 | /* |
1698 | * The current logical cdclk state. | |
1699 | * See intel_atomic_state.cdclk.logical | |
1700 | * | |
1701 | * For reading holding any crtc lock is sufficient, | |
1702 | * for writing must hold all of them. | |
1703 | */ | |
1704 | struct intel_cdclk_state logical; | |
1705 | /* | |
1706 | * The current actual cdclk state. | |
1707 | * See intel_atomic_state.cdclk.actual | |
1708 | */ | |
1709 | struct intel_cdclk_state actual; | |
1710 | /* The current hardware cdclk state */ | |
49cd97a3 VS |
1711 | struct intel_cdclk_state hw; |
1712 | } cdclk; | |
63911d72 | 1713 | |
645416f5 DV |
1714 | /** |
1715 | * wq - Driver workqueue for GEM. | |
1716 | * | |
1717 | * NOTE: Work items scheduled here are not allowed to grab any modeset | |
1718 | * locks, for otherwise the flushing done in the pageflip code will | |
1719 | * result in deadlocks. | |
1720 | */ | |
f4c956ad DV |
1721 | struct workqueue_struct *wq; |
1722 | ||
757fffcf VS |
1723 | /* ordered wq for modesets */ |
1724 | struct workqueue_struct *modeset_wq; | |
1725 | ||
f4c956ad DV |
1726 | /* Display functions */ |
1727 | struct drm_i915_display_funcs display; | |
1728 | ||
1729 | /* PCH chipset type */ | |
1730 | enum intel_pch pch_type; | |
17a303ec | 1731 | unsigned short pch_id; |
f4c956ad DV |
1732 | |
1733 | unsigned long quirks; | |
1734 | ||
b8efb17b ZR |
1735 | enum modeset_restore modeset_restore; |
1736 | struct mutex modeset_restore_lock; | |
e2c8b870 | 1737 | struct drm_atomic_state *modeset_restore_state; |
73974893 | 1738 | struct drm_modeset_acquire_ctx reset_ctx; |
673a394b | 1739 | |
a7bbbd63 | 1740 | struct list_head vm_list; /* Global list of all address spaces */ |
62106b4f | 1741 | struct i915_ggtt ggtt; /* VM representing the global address space */ |
5d4545ae | 1742 | |
4b5aed62 | 1743 | struct i915_gem_mm mm; |
ad46cb53 CW |
1744 | DECLARE_HASHTABLE(mm_structs, 7); |
1745 | struct mutex mm_lock; | |
8781342d | 1746 | |
4395890a ZW |
1747 | struct intel_ppat ppat; |
1748 | ||
8781342d DV |
1749 | /* Kernel Modesetting */ |
1750 | ||
e2af48c6 VS |
1751 | struct intel_crtc *plane_to_crtc_mapping[I915_MAX_PIPES]; |
1752 | struct intel_crtc *pipe_to_crtc_mapping[I915_MAX_PIPES]; | |
6b95a207 | 1753 | |
c4597872 DV |
1754 | #ifdef CONFIG_DEBUG_FS |
1755 | struct intel_pipe_crc pipe_crc[I915_MAX_PIPES]; | |
1756 | #endif | |
1757 | ||
565602d7 | 1758 | /* dpll and cdclk state is protected by connection_mutex */ |
e72f9fbf DV |
1759 | int num_shared_dpll; |
1760 | struct intel_shared_dpll shared_dplls[I915_NUM_PLLS]; | |
f9476a6c | 1761 | const struct intel_dpll_mgr *dpll_mgr; |
565602d7 | 1762 | |
fbf6d879 ML |
1763 | /* |
1764 | * dpll_lock serializes intel_{prepare,enable,disable}_shared_dpll. | |
1765 | * Must be global rather than per dpll, because on some platforms | |
1766 | * plls share registers. | |
1767 | */ | |
1768 | struct mutex dpll_lock; | |
1769 | ||
565602d7 | 1770 | unsigned int active_crtcs; |
d305e061 VS |
1771 | /* minimum acceptable cdclk for each pipe */ |
1772 | int min_cdclk[I915_MAX_PIPES]; | |
53e9bf5e VS |
1773 | /* minimum acceptable voltage level for each pipe */ |
1774 | u8 min_voltage_level[I915_MAX_PIPES]; | |
565602d7 | 1775 | |
e4607fcf | 1776 | int dpio_phy_iosf_port[I915_NUM_PHYS_VLV]; |
ee7b9f93 | 1777 | |
7225342a | 1778 | struct i915_workarounds workarounds; |
888b5995 | 1779 | |
f99d7069 DV |
1780 | struct i915_frontbuffer_tracking fb_tracking; |
1781 | ||
eb955eee CW |
1782 | struct intel_atomic_helper { |
1783 | struct llist_head free_list; | |
1784 | struct work_struct free_work; | |
1785 | } atomic_helper; | |
1786 | ||
652c393a | 1787 | u16 orig_clock; |
f97108d1 | 1788 | |
c4804411 | 1789 | bool mchbar_need_disable; |
f97108d1 | 1790 | |
a4da4fa4 DV |
1791 | struct intel_l3_parity l3_parity; |
1792 | ||
59124506 | 1793 | /* Cannot be determined by PCIID. You must always read a register. */ |
3accaf7e | 1794 | u32 edram_cap; |
59124506 | 1795 | |
9f817501 SAK |
1796 | /* |
1797 | * Protects RPS/RC6 register access and PCU communication. | |
1798 | * Must be taken after struct_mutex if nested. Note that | |
1799 | * this lock may be held for long periods of time when | |
1800 | * talking to hw - so only take it when talking to hw! | |
1801 | */ | |
1802 | struct mutex pcu_lock; | |
1803 | ||
562d9bae SAK |
1804 | /* gen6+ GT PM state */ |
1805 | struct intel_gen6_power_mgmt gt_pm; | |
c6a828d3 | 1806 | |
20e4d407 DV |
1807 | /* ilk-only ips/rps state. Everything in here is protected by the global |
1808 | * mchdev_lock in intel_pm.c */ | |
c85aa885 | 1809 | struct intel_ilk_power_mgmt ips; |
b5e50c3f | 1810 | |
83c00f55 | 1811 | struct i915_power_domains power_domains; |
a38911a3 | 1812 | |
a031d709 | 1813 | struct i915_psr psr; |
3f51e471 | 1814 | |
99584db3 | 1815 | struct i915_gpu_error gpu_error; |
ae681d96 | 1816 | |
c9cddffc JB |
1817 | struct drm_i915_gem_object *vlv_pctx; |
1818 | ||
8be48d92 DA |
1819 | /* list of fbdev register on this device */ |
1820 | struct intel_fbdev *fbdev; | |
82e3b8c1 | 1821 | struct work_struct fbdev_suspend_work; |
e953fd7b CW |
1822 | |
1823 | struct drm_property *broadcast_rgb_property; | |
3f43c48d | 1824 | struct drm_property *force_audio_property; |
e3689190 | 1825 | |
58fddc28 | 1826 | /* hda/i915 audio component */ |
51e1d83c | 1827 | struct i915_audio_component *audio_component; |
58fddc28 | 1828 | bool audio_component_registered; |
4a21ef7d LY |
1829 | /** |
1830 | * av_mutex - mutex for audio/video sync | |
1831 | * | |
1832 | */ | |
1833 | struct mutex av_mutex; | |
58fddc28 | 1834 | |
829a0af2 CW |
1835 | struct { |
1836 | struct list_head list; | |
5f09a9c8 CW |
1837 | struct llist_head free_list; |
1838 | struct work_struct free_work; | |
829a0af2 CW |
1839 | |
1840 | /* The hw wants to have a stable context identifier for the | |
1841 | * lifetime of the context (for OA, PASID, faults, etc). | |
1842 | * This is limited in execlists to 21 bits. | |
1843 | */ | |
1844 | struct ida hw_ida; | |
1845 | #define MAX_CONTEXT_HW_ID (1<<21) /* exclusive */ | |
ac52da6a | 1846 | #define GEN11_MAX_CONTEXT_HW_ID (1<<11) /* exclusive */ |
829a0af2 | 1847 | } contexts; |
f4c956ad | 1848 | |
3e68320e | 1849 | u32 fdi_rx_config; |
68d18ad7 | 1850 | |
c231775c | 1851 | /* Shadow for DISPLAY_PHY_CONTROL which can't be safely read */ |
70722468 | 1852 | u32 chv_phy_control; |
c231775c VS |
1853 | /* |
1854 | * Shadows for CHV DPLL_MD regs to keep the state | |
1855 | * checker somewhat working in the presence hardware | |
1856 | * crappiness (can't read out DPLL_MD for pipes B & C). | |
1857 | */ | |
1858 | u32 chv_dpll_md[I915_MAX_PIPES]; | |
adc7f04b | 1859 | u32 bxt_phy_grc; |
70722468 | 1860 | |
842f1c8b | 1861 | u32 suspend_count; |
0f90603c | 1862 | bool power_domains_suspended; |
f4c956ad | 1863 | struct i915_suspend_saved_registers regfile; |
ddeea5b0 | 1864 | struct vlv_s0ix_state vlv_s0ix_state; |
231f42a4 | 1865 | |
656d1b89 | 1866 | enum { |
16dcdc4e PZ |
1867 | I915_SAGV_UNKNOWN = 0, |
1868 | I915_SAGV_DISABLED, | |
1869 | I915_SAGV_ENABLED, | |
1870 | I915_SAGV_NOT_CONTROLLED | |
1871 | } sagv_status; | |
656d1b89 | 1872 | |
53615a5e VS |
1873 | struct { |
1874 | /* | |
1875 | * Raw watermark latency values: | |
1876 | * in 0.1us units for WM0, | |
1877 | * in 0.5us units for WM1+. | |
1878 | */ | |
1879 | /* primary */ | |
1880 | uint16_t pri_latency[5]; | |
1881 | /* sprite */ | |
1882 | uint16_t spr_latency[5]; | |
1883 | /* cursor */ | |
1884 | uint16_t cur_latency[5]; | |
2af30a5c PB |
1885 | /* |
1886 | * Raw watermark memory latency values | |
1887 | * for SKL for all 8 levels | |
1888 | * in 1us units. | |
1889 | */ | |
1890 | uint16_t skl_latency[8]; | |
609cedef VS |
1891 | |
1892 | /* current hardware state */ | |
2d41c0b5 PB |
1893 | union { |
1894 | struct ilk_wm_values hw; | |
60f8e873 | 1895 | struct skl_ddb_values skl_hw; |
0018fda1 | 1896 | struct vlv_wm_values vlv; |
04548cba | 1897 | struct g4x_wm_values g4x; |
2d41c0b5 | 1898 | }; |
58590c14 VS |
1899 | |
1900 | uint8_t max_level; | |
ed4a6a7c MR |
1901 | |
1902 | /* | |
1903 | * Should be held around atomic WM register writing; also | |
1904 | * protects * intel_crtc->wm.active and | |
1905 | * cstate->wm.need_postvbl_update. | |
1906 | */ | |
1907 | struct mutex wm_mutex; | |
279e99d7 MR |
1908 | |
1909 | /* | |
1910 | * Set during HW readout of watermarks/DDB. Some platforms | |
1911 | * need to know when we're still using BIOS-provided values | |
1912 | * (which we don't fully trust). | |
1913 | */ | |
1914 | bool distrust_bios_wm; | |
53615a5e VS |
1915 | } wm; |
1916 | ||
ad1443f0 | 1917 | struct i915_runtime_pm runtime_pm; |
8a187455 | 1918 | |
eec688e1 RB |
1919 | struct { |
1920 | bool initialized; | |
d7965152 | 1921 | |
442b8c06 | 1922 | struct kobject *metrics_kobj; |
ccdf6341 | 1923 | struct ctl_table_header *sysctl_header; |
442b8c06 | 1924 | |
f89823c2 LL |
1925 | /* |
1926 | * Lock associated with adding/modifying/removing OA configs | |
1927 | * in dev_priv->perf.metrics_idr. | |
1928 | */ | |
1929 | struct mutex metrics_lock; | |
1930 | ||
1931 | /* | |
1932 | * List of dynamic configurations, you need to hold | |
1933 | * dev_priv->perf.metrics_lock to access it. | |
1934 | */ | |
1935 | struct idr metrics_idr; | |
1936 | ||
1937 | /* | |
1938 | * Lock associated with anything below within this structure | |
1939 | * except exclusive_stream. | |
1940 | */ | |
eec688e1 RB |
1941 | struct mutex lock; |
1942 | struct list_head streams; | |
8a3003dd RB |
1943 | |
1944 | struct { | |
f89823c2 LL |
1945 | /* |
1946 | * The stream currently using the OA unit. If accessed | |
1947 | * outside a syscall associated to its file | |
1948 | * descriptor, you need to hold | |
1949 | * dev_priv->drm.struct_mutex. | |
1950 | */ | |
d7965152 RB |
1951 | struct i915_perf_stream *exclusive_stream; |
1952 | ||
1fc44d9b | 1953 | struct intel_context *pinned_ctx; |
d7965152 | 1954 | u32 specific_ctx_id; |
d7965152 RB |
1955 | |
1956 | struct hrtimer poll_check_timer; | |
1957 | wait_queue_head_t poll_wq; | |
1958 | bool pollin; | |
1959 | ||
712122ea RB |
1960 | /** |
1961 | * For rate limiting any notifications of spurious | |
1962 | * invalid OA reports | |
1963 | */ | |
1964 | struct ratelimit_state spurious_report_rs; | |
1965 | ||
d7965152 RB |
1966 | bool periodic; |
1967 | int period_exponent; | |
d7965152 | 1968 | |
701f8231 | 1969 | struct i915_oa_config test_config; |
d7965152 RB |
1970 | |
1971 | struct { | |
1972 | struct i915_vma *vma; | |
1973 | u8 *vaddr; | |
19f81df2 | 1974 | u32 last_ctx_id; |
d7965152 RB |
1975 | int format; |
1976 | int format_size; | |
f279020a | 1977 | |
0dd860cf RB |
1978 | /** |
1979 | * Locks reads and writes to all head/tail state | |
1980 | * | |
1981 | * Consider: the head and tail pointer state | |
1982 | * needs to be read consistently from a hrtimer | |
1983 | * callback (atomic context) and read() fop | |
1984 | * (user context) with tail pointer updates | |
1985 | * happening in atomic context and head updates | |
1986 | * in user context and the (unlikely) | |
1987 | * possibility of read() errors needing to | |
1988 | * reset all head/tail state. | |
1989 | * | |
1990 | * Note: Contention or performance aren't | |
1991 | * currently a significant concern here | |
1992 | * considering the relatively low frequency of | |
1993 | * hrtimer callbacks (5ms period) and that | |
1994 | * reads typically only happen in response to a | |
1995 | * hrtimer event and likely complete before the | |
1996 | * next callback. | |
1997 | * | |
1998 | * Note: This lock is not held *while* reading | |
1999 | * and copying data to userspace so the value | |
2000 | * of head observed in htrimer callbacks won't | |
2001 | * represent any partial consumption of data. | |
2002 | */ | |
2003 | spinlock_t ptr_lock; | |
2004 | ||
2005 | /** | |
2006 | * One 'aging' tail pointer and one 'aged' | |
2007 | * tail pointer ready to used for reading. | |
2008 | * | |
2009 | * Initial values of 0xffffffff are invalid | |
2010 | * and imply that an update is required | |
2011 | * (and should be ignored by an attempted | |
2012 | * read) | |
2013 | */ | |
2014 | struct { | |
2015 | u32 offset; | |
2016 | } tails[2]; | |
2017 | ||
2018 | /** | |
2019 | * Index for the aged tail ready to read() | |
2020 | * data up to. | |
2021 | */ | |
2022 | unsigned int aged_tail_idx; | |
2023 | ||
2024 | /** | |
2025 | * A monotonic timestamp for when the current | |
2026 | * aging tail pointer was read; used to | |
2027 | * determine when it is old enough to trust. | |
2028 | */ | |
2029 | u64 aging_timestamp; | |
2030 | ||
f279020a RB |
2031 | /** |
2032 | * Although we can always read back the head | |
2033 | * pointer register, we prefer to avoid | |
2034 | * trusting the HW state, just to avoid any | |
2035 | * risk that some hardware condition could | |
2036 | * somehow bump the head pointer unpredictably | |
2037 | * and cause us to forward the wrong OA buffer | |
2038 | * data to userspace. | |
2039 | */ | |
2040 | u32 head; | |
d7965152 RB |
2041 | } oa_buffer; |
2042 | ||
2043 | u32 gen7_latched_oastatus1; | |
19f81df2 RB |
2044 | u32 ctx_oactxctrl_offset; |
2045 | u32 ctx_flexeu0_offset; | |
2046 | ||
2047 | /** | |
2048 | * The RPT_ID/reason field for Gen8+ includes a bit | |
2049 | * to determine if the CTX ID in the report is valid | |
2050 | * but the specific bit differs between Gen 8 and 9 | |
2051 | */ | |
2052 | u32 gen8_valid_ctx_bit; | |
d7965152 RB |
2053 | |
2054 | struct i915_oa_ops ops; | |
2055 | const struct i915_oa_format *oa_formats; | |
8a3003dd | 2056 | } oa; |
eec688e1 RB |
2057 | } perf; |
2058 | ||
a83014d3 OM |
2059 | /* Abstract the submission mechanism (legacy ringbuffer or execlists) away */ |
2060 | struct { | |
821ed7df | 2061 | void (*resume)(struct drm_i915_private *); |
117897f4 | 2062 | void (*cleanup_engine)(struct intel_engine_cs *engine); |
67d97da3 | 2063 | |
b887d615 | 2064 | struct list_head timelines; |
643b450a CW |
2065 | |
2066 | struct list_head active_rings; | |
3365e226 | 2067 | struct list_head closed_vma; |
28176ef4 | 2068 | u32 active_requests; |
52d7f16e | 2069 | u32 request_serial; |
73cb9701 | 2070 | |
67d97da3 CW |
2071 | /** |
2072 | * Is the GPU currently considered idle, or busy executing | |
2073 | * userspace requests? Whilst idle, we allow runtime power | |
2074 | * management to power down the hardware and display clocks. | |
2075 | * In order to reduce the effect on performance, there | |
2076 | * is a slight delay before we do so. | |
2077 | */ | |
67d97da3 CW |
2078 | bool awake; |
2079 | ||
6f56103d CW |
2080 | /** |
2081 | * The number of times we have woken up. | |
2082 | */ | |
2083 | unsigned int epoch; | |
2084 | #define I915_EPOCH_INVALID 0 | |
2085 | ||
67d97da3 CW |
2086 | /** |
2087 | * We leave the user IRQ off as much as possible, | |
2088 | * but this means that requests will finish and never | |
2089 | * be retired once the system goes idle. Set a timer to | |
2090 | * fire periodically while the ring is running. When it | |
2091 | * fires, go retire requests. | |
2092 | */ | |
2093 | struct delayed_work retire_work; | |
2094 | ||
2095 | /** | |
2096 | * When we detect an idle GPU, we want to turn on | |
2097 | * powersaving features. So once we see that there | |
2098 | * are no more requests outstanding and no more | |
2099 | * arrive within a small period of time, we fire | |
2100 | * off the idle_work. | |
2101 | */ | |
2102 | struct delayed_work idle_work; | |
de867c20 CW |
2103 | |
2104 | ktime_t last_init_time; | |
a83014d3 OM |
2105 | } gt; |
2106 | ||
3be60de9 VS |
2107 | /* perform PHY state sanity checks? */ |
2108 | bool chv_phy_assert[2]; | |
2109 | ||
a3a8986c MK |
2110 | bool ipc_enabled; |
2111 | ||
f9318941 PD |
2112 | /* Used to save the pipe-to-encoder mapping for audio */ |
2113 | struct intel_encoder *av_enc_map[I915_MAX_PIPES]; | |
0bdf5a05 | 2114 | |
eef57324 JA |
2115 | /* necessary resource sharing with HDMI LPE audio driver. */ |
2116 | struct { | |
2117 | struct platform_device *platdev; | |
2118 | int irq; | |
2119 | } lpe_audio; | |
2120 | ||
b46a33e2 TU |
2121 | struct i915_pmu pmu; |
2122 | ||
bdf1e7e3 DV |
2123 | /* |
2124 | * NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch | |
2125 | * will be rejected. Instead look for a better place. | |
2126 | */ | |
77fec556 | 2127 | }; |
1da177e4 | 2128 | |
2c1792a1 CW |
2129 | static inline struct drm_i915_private *to_i915(const struct drm_device *dev) |
2130 | { | |
091387c1 | 2131 | return container_of(dev, struct drm_i915_private, drm); |
2c1792a1 CW |
2132 | } |
2133 | ||
c49d13ee | 2134 | static inline struct drm_i915_private *kdev_to_i915(struct device *kdev) |
888d0d42 | 2135 | { |
c49d13ee | 2136 | return to_i915(dev_get_drvdata(kdev)); |
888d0d42 ID |
2137 | } |
2138 | ||
6b0478fb JL |
2139 | static inline struct drm_i915_private *wopcm_to_i915(struct intel_wopcm *wopcm) |
2140 | { | |
2141 | return container_of(wopcm, struct drm_i915_private, wopcm); | |
2142 | } | |
2143 | ||
33a732f4 AD |
2144 | static inline struct drm_i915_private *guc_to_i915(struct intel_guc *guc) |
2145 | { | |
2146 | return container_of(guc, struct drm_i915_private, guc); | |
2147 | } | |
2148 | ||
50beba55 AH |
2149 | static inline struct drm_i915_private *huc_to_i915(struct intel_huc *huc) |
2150 | { | |
2151 | return container_of(huc, struct drm_i915_private, huc); | |
2152 | } | |
2153 | ||
b4ac5afc | 2154 | /* Simple iterator over all initialised engines */ |
3b3f1650 AG |
2155 | #define for_each_engine(engine__, dev_priv__, id__) \ |
2156 | for ((id__) = 0; \ | |
2157 | (id__) < I915_NUM_ENGINES; \ | |
2158 | (id__)++) \ | |
2159 | for_each_if ((engine__) = (dev_priv__)->engine[(id__)]) | |
c3232b18 DG |
2160 | |
2161 | /* Iterator over subset of engines selected by mask */ | |
bafb0fce | 2162 | #define for_each_engine_masked(engine__, dev_priv__, mask__, tmp__) \ |
19d3cf00 TU |
2163 | for ((tmp__) = (mask__) & INTEL_INFO(dev_priv__)->ring_mask; \ |
2164 | (tmp__) ? \ | |
2165 | ((engine__) = (dev_priv__)->engine[__mask_next_bit(tmp__)]), 1 : \ | |
2166 | 0;) | |
ee4b6faf | 2167 | |
b1d7e4b4 WF |
2168 | enum hdmi_force_audio { |
2169 | HDMI_AUDIO_OFF_DVI = -2, /* no aux data for HDMI-DVI converter */ | |
2170 | HDMI_AUDIO_OFF, /* force turn off HDMI audio */ | |
2171 | HDMI_AUDIO_AUTO, /* trust EDID */ | |
2172 | HDMI_AUDIO_ON, /* force turn on HDMI audio */ | |
2173 | }; | |
2174 | ||
190d6cd5 | 2175 | #define I915_GTT_OFFSET_NONE ((u32)-1) |
ed2f3452 | 2176 | |
a071fa00 DV |
2177 | /* |
2178 | * Frontbuffer tracking bits. Set in obj->frontbuffer_bits while a gem bo is | |
d1b9d039 | 2179 | * considered to be the frontbuffer for the given plane interface-wise. This |
a071fa00 DV |
2180 | * doesn't mean that the hw necessarily already scans it out, but that any |
2181 | * rendering (by the cpu or gpu) will land in the frontbuffer eventually. | |
2182 | * | |
2183 | * We have one bit per pipe and per scanout plane type. | |
2184 | */ | |
d1b9d039 | 2185 | #define INTEL_FRONTBUFFER_BITS_PER_PIPE 8 |
aa81e2c3 VS |
2186 | #define INTEL_FRONTBUFFER(pipe, plane_id) ({ \ |
2187 | BUILD_BUG_ON(INTEL_FRONTBUFFER_BITS_PER_PIPE * I915_MAX_PIPES > 32); \ | |
2188 | BUILD_BUG_ON(I915_MAX_PLANES > INTEL_FRONTBUFFER_BITS_PER_PIPE); \ | |
2189 | BIT((plane_id) + INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)); \ | |
2190 | }) | |
a071fa00 | 2191 | #define INTEL_FRONTBUFFER_OVERLAY(pipe) \ |
aa81e2c3 | 2192 | BIT(INTEL_FRONTBUFFER_BITS_PER_PIPE - 1 + INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)) |
cc36513c | 2193 | #define INTEL_FRONTBUFFER_ALL_MASK(pipe) \ |
aa81e2c3 VS |
2194 | GENMASK(INTEL_FRONTBUFFER_BITS_PER_PIPE * ((pipe) + 1) - 1, \ |
2195 | INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)) | |
a071fa00 | 2196 | |
85d1225e DG |
2197 | /* |
2198 | * Optimised SGL iterator for GEM objects | |
2199 | */ | |
2200 | static __always_inline struct sgt_iter { | |
2201 | struct scatterlist *sgp; | |
2202 | union { | |
2203 | unsigned long pfn; | |
2204 | dma_addr_t dma; | |
2205 | }; | |
2206 | unsigned int curr; | |
2207 | unsigned int max; | |
2208 | } __sgt_iter(struct scatterlist *sgl, bool dma) { | |
2209 | struct sgt_iter s = { .sgp = sgl }; | |
2210 | ||
2211 | if (s.sgp) { | |
2212 | s.max = s.curr = s.sgp->offset; | |
2213 | s.max += s.sgp->length; | |
2214 | if (dma) | |
2215 | s.dma = sg_dma_address(s.sgp); | |
2216 | else | |
2217 | s.pfn = page_to_pfn(sg_page(s.sgp)); | |
2218 | } | |
2219 | ||
2220 | return s; | |
2221 | } | |
2222 | ||
96d77634 CW |
2223 | static inline struct scatterlist *____sg_next(struct scatterlist *sg) |
2224 | { | |
2225 | ++sg; | |
2226 | if (unlikely(sg_is_chain(sg))) | |
2227 | sg = sg_chain_ptr(sg); | |
2228 | return sg; | |
2229 | } | |
2230 | ||
63d15326 DG |
2231 | /** |
2232 | * __sg_next - return the next scatterlist entry in a list | |
2233 | * @sg: The current sg entry | |
2234 | * | |
2235 | * Description: | |
2236 | * If the entry is the last, return NULL; otherwise, step to the next | |
2237 | * element in the array (@sg@+1). If that's a chain pointer, follow it; | |
2238 | * otherwise just return the pointer to the current element. | |
2239 | **/ | |
2240 | static inline struct scatterlist *__sg_next(struct scatterlist *sg) | |
2241 | { | |
2242 | #ifdef CONFIG_DEBUG_SG | |
2243 | BUG_ON(sg->sg_magic != SG_MAGIC); | |
2244 | #endif | |
96d77634 | 2245 | return sg_is_last(sg) ? NULL : ____sg_next(sg); |
63d15326 DG |
2246 | } |
2247 | ||
85d1225e DG |
2248 | /** |
2249 | * for_each_sgt_dma - iterate over the DMA addresses of the given sg_table | |
2250 | * @__dmap: DMA address (output) | |
2251 | * @__iter: 'struct sgt_iter' (iterator state, internal) | |
2252 | * @__sgt: sg_table to iterate over (input) | |
2253 | */ | |
2254 | #define for_each_sgt_dma(__dmap, __iter, __sgt) \ | |
2255 | for ((__iter) = __sgt_iter((__sgt)->sgl, true); \ | |
2256 | ((__dmap) = (__iter).dma + (__iter).curr); \ | |
e60b36f7 CW |
2257 | (((__iter).curr += PAGE_SIZE) >= (__iter).max) ? \ |
2258 | (__iter) = __sgt_iter(__sg_next((__iter).sgp), true), 0 : 0) | |
85d1225e DG |
2259 | |
2260 | /** | |
2261 | * for_each_sgt_page - iterate over the pages of the given sg_table | |
2262 | * @__pp: page pointer (output) | |
2263 | * @__iter: 'struct sgt_iter' (iterator state, internal) | |
2264 | * @__sgt: sg_table to iterate over (input) | |
2265 | */ | |
2266 | #define for_each_sgt_page(__pp, __iter, __sgt) \ | |
2267 | for ((__iter) = __sgt_iter((__sgt)->sgl, false); \ | |
2268 | ((__pp) = (__iter).pfn == 0 ? NULL : \ | |
2269 | pfn_to_page((__iter).pfn + ((__iter).curr >> PAGE_SHIFT))); \ | |
e60b36f7 CW |
2270 | (((__iter).curr += PAGE_SIZE) >= (__iter).max) ? \ |
2271 | (__iter) = __sgt_iter(__sg_next((__iter).sgp), false), 0 : 0) | |
a071fa00 | 2272 | |
a5c08166 MA |
2273 | static inline unsigned int i915_sg_page_sizes(struct scatterlist *sg) |
2274 | { | |
2275 | unsigned int page_sizes; | |
2276 | ||
2277 | page_sizes = 0; | |
2278 | while (sg) { | |
2279 | GEM_BUG_ON(sg->offset); | |
2280 | GEM_BUG_ON(!IS_ALIGNED(sg->length, PAGE_SIZE)); | |
2281 | page_sizes |= sg->length; | |
2282 | sg = __sg_next(sg); | |
2283 | } | |
2284 | ||
2285 | return page_sizes; | |
2286 | } | |
2287 | ||
5602452e TU |
2288 | static inline unsigned int i915_sg_segment_size(void) |
2289 | { | |
2290 | unsigned int size = swiotlb_max_segment(); | |
2291 | ||
2292 | if (size == 0) | |
2293 | return SCATTERLIST_MAX_SEGMENT; | |
2294 | ||
2295 | size = rounddown(size, PAGE_SIZE); | |
2296 | /* swiotlb_max_segment_size can return 1 byte when it means one page. */ | |
2297 | if (size < PAGE_SIZE) | |
2298 | size = PAGE_SIZE; | |
2299 | ||
2300 | return size; | |
2301 | } | |
2302 | ||
5ca43ef0 TU |
2303 | static inline const struct intel_device_info * |
2304 | intel_info(const struct drm_i915_private *dev_priv) | |
2305 | { | |
2306 | return &dev_priv->info; | |
2307 | } | |
2308 | ||
2309 | #define INTEL_INFO(dev_priv) intel_info((dev_priv)) | |
50a0bc90 | 2310 | |
55b8f2a7 | 2311 | #define INTEL_GEN(dev_priv) ((dev_priv)->info.gen) |
50a0bc90 | 2312 | #define INTEL_DEVID(dev_priv) ((dev_priv)->info.device_id) |
cae5852d | 2313 | |
e87a005d | 2314 | #define REVID_FOREVER 0xff |
4805fe82 | 2315 | #define INTEL_REVID(dev_priv) ((dev_priv)->drm.pdev->revision) |
ac657f64 TU |
2316 | |
2317 | #define GEN_FOREVER (0) | |
fe52e597 JL |
2318 | |
2319 | #define INTEL_GEN_MASK(s, e) ( \ | |
2320 | BUILD_BUG_ON_ZERO(!__builtin_constant_p(s)) + \ | |
2321 | BUILD_BUG_ON_ZERO(!__builtin_constant_p(e)) + \ | |
2322 | GENMASK((e) != GEN_FOREVER ? (e) - 1 : BITS_PER_LONG - 1, \ | |
2323 | (s) != GEN_FOREVER ? (s) - 1 : 0) \ | |
2324 | ) | |
2325 | ||
ac657f64 TU |
2326 | /* |
2327 | * Returns true if Gen is in inclusive range [Start, End]. | |
2328 | * | |
2329 | * Use GEN_FOREVER for unbound start and or end. | |
2330 | */ | |
fe52e597 JL |
2331 | #define IS_GEN(dev_priv, s, e) \ |
2332 | (!!((dev_priv)->info.gen_mask & INTEL_GEN_MASK((s), (e)))) | |
ac657f64 | 2333 | |
e87a005d JN |
2334 | /* |
2335 | * Return true if revision is in range [since,until] inclusive. | |
2336 | * | |
2337 | * Use 0 for open-ended since, and REVID_FOREVER for open-ended until. | |
2338 | */ | |
2339 | #define IS_REVID(p, since, until) \ | |
2340 | (INTEL_REVID(p) >= (since) && INTEL_REVID(p) <= (until)) | |
2341 | ||
ae7617f0 | 2342 | #define IS_PLATFORM(dev_priv, p) ((dev_priv)->info.platform_mask & BIT(p)) |
5a127a8c TU |
2343 | |
2344 | #define IS_I830(dev_priv) IS_PLATFORM(dev_priv, INTEL_I830) | |
2345 | #define IS_I845G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I845G) | |
2346 | #define IS_I85X(dev_priv) IS_PLATFORM(dev_priv, INTEL_I85X) | |
2347 | #define IS_I865G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I865G) | |
2348 | #define IS_I915G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I915G) | |
2349 | #define IS_I915GM(dev_priv) IS_PLATFORM(dev_priv, INTEL_I915GM) | |
2350 | #define IS_I945G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I945G) | |
2351 | #define IS_I945GM(dev_priv) IS_PLATFORM(dev_priv, INTEL_I945GM) | |
2352 | #define IS_I965G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I965G) | |
2353 | #define IS_I965GM(dev_priv) IS_PLATFORM(dev_priv, INTEL_I965GM) | |
2354 | #define IS_G45(dev_priv) IS_PLATFORM(dev_priv, INTEL_G45) | |
2355 | #define IS_GM45(dev_priv) IS_PLATFORM(dev_priv, INTEL_GM45) | |
f69c11ae | 2356 | #define IS_G4X(dev_priv) (IS_G45(dev_priv) || IS_GM45(dev_priv)) |
50a0bc90 TU |
2357 | #define IS_PINEVIEW_G(dev_priv) (INTEL_DEVID(dev_priv) == 0xa001) |
2358 | #define IS_PINEVIEW_M(dev_priv) (INTEL_DEVID(dev_priv) == 0xa011) | |
5a127a8c TU |
2359 | #define IS_PINEVIEW(dev_priv) IS_PLATFORM(dev_priv, INTEL_PINEVIEW) |
2360 | #define IS_G33(dev_priv) IS_PLATFORM(dev_priv, INTEL_G33) | |
50a0bc90 | 2361 | #define IS_IRONLAKE_M(dev_priv) (INTEL_DEVID(dev_priv) == 0x0046) |
5a127a8c | 2362 | #define IS_IVYBRIDGE(dev_priv) IS_PLATFORM(dev_priv, INTEL_IVYBRIDGE) |
18b53818 LL |
2363 | #define IS_IVB_GT1(dev_priv) (IS_IVYBRIDGE(dev_priv) && \ |
2364 | (dev_priv)->info.gt == 1) | |
5a127a8c TU |
2365 | #define IS_VALLEYVIEW(dev_priv) IS_PLATFORM(dev_priv, INTEL_VALLEYVIEW) |
2366 | #define IS_CHERRYVIEW(dev_priv) IS_PLATFORM(dev_priv, INTEL_CHERRYVIEW) | |
2367 | #define IS_HASWELL(dev_priv) IS_PLATFORM(dev_priv, INTEL_HASWELL) | |
2368 | #define IS_BROADWELL(dev_priv) IS_PLATFORM(dev_priv, INTEL_BROADWELL) | |
2369 | #define IS_SKYLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_SKYLAKE) | |
2370 | #define IS_BROXTON(dev_priv) IS_PLATFORM(dev_priv, INTEL_BROXTON) | |
2371 | #define IS_KABYLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_KABYLAKE) | |
2372 | #define IS_GEMINILAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_GEMINILAKE) | |
2373 | #define IS_COFFEELAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_COFFEELAKE) | |
2374 | #define IS_CANNONLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_CANNONLAKE) | |
41231001 | 2375 | #define IS_ICELAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_ICELAKE) |
646d5772 | 2376 | #define IS_MOBILE(dev_priv) ((dev_priv)->info.is_mobile) |
50a0bc90 TU |
2377 | #define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \ |
2378 | (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0C00) | |
2379 | #define IS_BDW_ULT(dev_priv) (IS_BROADWELL(dev_priv) && \ | |
2380 | ((INTEL_DEVID(dev_priv) & 0xf) == 0x6 || \ | |
2381 | (INTEL_DEVID(dev_priv) & 0xf) == 0xb || \ | |
2382 | (INTEL_DEVID(dev_priv) & 0xf) == 0xe)) | |
ebb72aad | 2383 | /* ULX machines are also considered ULT. */ |
50a0bc90 TU |
2384 | #define IS_BDW_ULX(dev_priv) (IS_BROADWELL(dev_priv) && \ |
2385 | (INTEL_DEVID(dev_priv) & 0xf) == 0xe) | |
2386 | #define IS_BDW_GT3(dev_priv) (IS_BROADWELL(dev_priv) && \ | |
18b53818 | 2387 | (dev_priv)->info.gt == 3) |
50a0bc90 TU |
2388 | #define IS_HSW_ULT(dev_priv) (IS_HASWELL(dev_priv) && \ |
2389 | (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0A00) | |
2390 | #define IS_HSW_GT3(dev_priv) (IS_HASWELL(dev_priv) && \ | |
18b53818 | 2391 | (dev_priv)->info.gt == 3) |
9bbfd20a | 2392 | /* ULX machines are also considered ULT. */ |
50a0bc90 TU |
2393 | #define IS_HSW_ULX(dev_priv) (INTEL_DEVID(dev_priv) == 0x0A0E || \ |
2394 | INTEL_DEVID(dev_priv) == 0x0A1E) | |
2395 | #define IS_SKL_ULT(dev_priv) (INTEL_DEVID(dev_priv) == 0x1906 || \ | |
2396 | INTEL_DEVID(dev_priv) == 0x1913 || \ | |
2397 | INTEL_DEVID(dev_priv) == 0x1916 || \ | |
2398 | INTEL_DEVID(dev_priv) == 0x1921 || \ | |
2399 | INTEL_DEVID(dev_priv) == 0x1926) | |
2400 | #define IS_SKL_ULX(dev_priv) (INTEL_DEVID(dev_priv) == 0x190E || \ | |
2401 | INTEL_DEVID(dev_priv) == 0x1915 || \ | |
2402 | INTEL_DEVID(dev_priv) == 0x191E) | |
2403 | #define IS_KBL_ULT(dev_priv) (INTEL_DEVID(dev_priv) == 0x5906 || \ | |
2404 | INTEL_DEVID(dev_priv) == 0x5913 || \ | |
2405 | INTEL_DEVID(dev_priv) == 0x5916 || \ | |
2406 | INTEL_DEVID(dev_priv) == 0x5921 || \ | |
2407 | INTEL_DEVID(dev_priv) == 0x5926) | |
2408 | #define IS_KBL_ULX(dev_priv) (INTEL_DEVID(dev_priv) == 0x590E || \ | |
2409 | INTEL_DEVID(dev_priv) == 0x5915 || \ | |
2410 | INTEL_DEVID(dev_priv) == 0x591E) | |
19f81df2 | 2411 | #define IS_SKL_GT2(dev_priv) (IS_SKYLAKE(dev_priv) && \ |
18b53818 | 2412 | (dev_priv)->info.gt == 2) |
50a0bc90 | 2413 | #define IS_SKL_GT3(dev_priv) (IS_SKYLAKE(dev_priv) && \ |
18b53818 | 2414 | (dev_priv)->info.gt == 3) |
50a0bc90 | 2415 | #define IS_SKL_GT4(dev_priv) (IS_SKYLAKE(dev_priv) && \ |
18b53818 | 2416 | (dev_priv)->info.gt == 4) |
3891589e | 2417 | #define IS_KBL_GT2(dev_priv) (IS_KABYLAKE(dev_priv) && \ |
18b53818 | 2418 | (dev_priv)->info.gt == 2) |
3891589e | 2419 | #define IS_KBL_GT3(dev_priv) (IS_KABYLAKE(dev_priv) && \ |
18b53818 | 2420 | (dev_priv)->info.gt == 3) |
da411a48 RV |
2421 | #define IS_CFL_ULT(dev_priv) (IS_COFFEELAKE(dev_priv) && \ |
2422 | (INTEL_DEVID(dev_priv) & 0x00F0) == 0x00A0) | |
22ea4f35 LL |
2423 | #define IS_CFL_GT2(dev_priv) (IS_COFFEELAKE(dev_priv) && \ |
2424 | (dev_priv)->info.gt == 2) | |
4407eaa9 LL |
2425 | #define IS_CFL_GT3(dev_priv) (IS_COFFEELAKE(dev_priv) && \ |
2426 | (dev_priv)->info.gt == 3) | |
3f43031b RV |
2427 | #define IS_CNL_WITH_PORT_F(dev_priv) (IS_CANNONLAKE(dev_priv) && \ |
2428 | (INTEL_DEVID(dev_priv) & 0x0004) == 0x0004) | |
7a58bad0 | 2429 | |
c007fb4a | 2430 | #define IS_ALPHA_SUPPORT(intel_info) ((intel_info)->is_alpha_support) |
cae5852d | 2431 | |
ef712bb4 JN |
2432 | #define SKL_REVID_A0 0x0 |
2433 | #define SKL_REVID_B0 0x1 | |
2434 | #define SKL_REVID_C0 0x2 | |
2435 | #define SKL_REVID_D0 0x3 | |
2436 | #define SKL_REVID_E0 0x4 | |
2437 | #define SKL_REVID_F0 0x5 | |
4ba9c1f7 MK |
2438 | #define SKL_REVID_G0 0x6 |
2439 | #define SKL_REVID_H0 0x7 | |
ef712bb4 | 2440 | |
e87a005d JN |
2441 | #define IS_SKL_REVID(p, since, until) (IS_SKYLAKE(p) && IS_REVID(p, since, until)) |
2442 | ||
ef712bb4 | 2443 | #define BXT_REVID_A0 0x0 |
fffda3f4 | 2444 | #define BXT_REVID_A1 0x1 |
ef712bb4 | 2445 | #define BXT_REVID_B0 0x3 |
a3f79ca6 | 2446 | #define BXT_REVID_B_LAST 0x8 |
ef712bb4 | 2447 | #define BXT_REVID_C0 0x9 |
6c74c87f | 2448 | |
e2d214ae TU |
2449 | #define IS_BXT_REVID(dev_priv, since, until) \ |
2450 | (IS_BROXTON(dev_priv) && IS_REVID(dev_priv, since, until)) | |
e87a005d | 2451 | |
c033a37c MK |
2452 | #define KBL_REVID_A0 0x0 |
2453 | #define KBL_REVID_B0 0x1 | |
fe905819 MK |
2454 | #define KBL_REVID_C0 0x2 |
2455 | #define KBL_REVID_D0 0x3 | |
2456 | #define KBL_REVID_E0 0x4 | |
c033a37c | 2457 | |
0853723b TU |
2458 | #define IS_KBL_REVID(dev_priv, since, until) \ |
2459 | (IS_KABYLAKE(dev_priv) && IS_REVID(dev_priv, since, until)) | |
c033a37c | 2460 | |
f4f4b59b ACO |
2461 | #define GLK_REVID_A0 0x0 |
2462 | #define GLK_REVID_A1 0x1 | |
2463 | ||
2464 | #define IS_GLK_REVID(dev_priv, since, until) \ | |
2465 | (IS_GEMINILAKE(dev_priv) && IS_REVID(dev_priv, since, until)) | |
2466 | ||
3c2e0fd9 PZ |
2467 | #define CNL_REVID_A0 0x0 |
2468 | #define CNL_REVID_B0 0x1 | |
e4ffc83d | 2469 | #define CNL_REVID_C0 0x2 |
3c2e0fd9 PZ |
2470 | |
2471 | #define IS_CNL_REVID(p, since, until) \ | |
2472 | (IS_CANNONLAKE(p) && IS_REVID(p, since, until)) | |
2473 | ||
cc38cae7 OM |
2474 | #define ICL_REVID_A0 0x0 |
2475 | #define ICL_REVID_A2 0x1 | |
2476 | #define ICL_REVID_B0 0x3 | |
2477 | #define ICL_REVID_B2 0x4 | |
2478 | #define ICL_REVID_C0 0x5 | |
2479 | ||
2480 | #define IS_ICL_REVID(p, since, until) \ | |
2481 | (IS_ICELAKE(p) && IS_REVID(p, since, until)) | |
2482 | ||
85436696 JB |
2483 | /* |
2484 | * The genX designation typically refers to the render engine, so render | |
2485 | * capability related checks should use IS_GEN, while display and other checks | |
2486 | * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular | |
2487 | * chips, etc.). | |
2488 | */ | |
5db94019 TU |
2489 | #define IS_GEN2(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(1))) |
2490 | #define IS_GEN3(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(2))) | |
2491 | #define IS_GEN4(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(3))) | |
2492 | #define IS_GEN5(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(4))) | |
2493 | #define IS_GEN6(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(5))) | |
2494 | #define IS_GEN7(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(6))) | |
2495 | #define IS_GEN8(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(7))) | |
2496 | #define IS_GEN9(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(8))) | |
413f3c19 | 2497 | #define IS_GEN10(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(9))) |
41231001 | 2498 | #define IS_GEN11(dev_priv) (!!((dev_priv)->info.gen_mask & BIT(10))) |
cae5852d | 2499 | |
8727dc09 | 2500 | #define IS_LP(dev_priv) (INTEL_INFO(dev_priv)->is_lp) |
b976dc53 RV |
2501 | #define IS_GEN9_LP(dev_priv) (IS_GEN9(dev_priv) && IS_LP(dev_priv)) |
2502 | #define IS_GEN9_BC(dev_priv) (IS_GEN9(dev_priv) && !IS_LP(dev_priv)) | |
3e4274f8 | 2503 | |
a19d6ff2 TU |
2504 | #define ENGINE_MASK(id) BIT(id) |
2505 | #define RENDER_RING ENGINE_MASK(RCS) | |
2506 | #define BSD_RING ENGINE_MASK(VCS) | |
2507 | #define BLT_RING ENGINE_MASK(BCS) | |
2508 | #define VEBOX_RING ENGINE_MASK(VECS) | |
2509 | #define BSD2_RING ENGINE_MASK(VCS2) | |
022d3093 TU |
2510 | #define BSD3_RING ENGINE_MASK(VCS3) |
2511 | #define BSD4_RING ENGINE_MASK(VCS4) | |
2512 | #define VEBOX2_RING ENGINE_MASK(VECS2) | |
a19d6ff2 TU |
2513 | #define ALL_ENGINES (~0) |
2514 | ||
2515 | #define HAS_ENGINE(dev_priv, id) \ | |
0031fb96 | 2516 | (!!((dev_priv)->info.ring_mask & ENGINE_MASK(id))) |
a19d6ff2 TU |
2517 | |
2518 | #define HAS_BSD(dev_priv) HAS_ENGINE(dev_priv, VCS) | |
2519 | #define HAS_BSD2(dev_priv) HAS_ENGINE(dev_priv, VCS2) | |
2520 | #define HAS_BLT(dev_priv) HAS_ENGINE(dev_priv, BCS) | |
2521 | #define HAS_VEBOX(dev_priv) HAS_ENGINE(dev_priv, VECS) | |
2522 | ||
93c6e966 CW |
2523 | #define HAS_LEGACY_SEMAPHORES(dev_priv) IS_GEN7(dev_priv) |
2524 | ||
0031fb96 TU |
2525 | #define HAS_LLC(dev_priv) ((dev_priv)->info.has_llc) |
2526 | #define HAS_SNOOP(dev_priv) ((dev_priv)->info.has_snoop) | |
2527 | #define HAS_EDRAM(dev_priv) (!!((dev_priv)->edram_cap & EDRAM_ENABLED)) | |
8652744b TU |
2528 | #define HAS_WT(dev_priv) ((IS_HASWELL(dev_priv) || \ |
2529 | IS_BROADWELL(dev_priv)) && HAS_EDRAM(dev_priv)) | |
cae5852d | 2530 | |
0031fb96 | 2531 | #define HWS_NEEDS_PHYSICAL(dev_priv) ((dev_priv)->info.hws_needs_physical) |
1d2a314c | 2532 | |
0031fb96 TU |
2533 | #define HAS_LOGICAL_RING_CONTEXTS(dev_priv) \ |
2534 | ((dev_priv)->info.has_logical_ring_contexts) | |
05f0addd TD |
2535 | #define HAS_LOGICAL_RING_ELSQ(dev_priv) \ |
2536 | ((dev_priv)->info.has_logical_ring_elsq) | |
a4598d17 MW |
2537 | #define HAS_LOGICAL_RING_PREEMPTION(dev_priv) \ |
2538 | ((dev_priv)->info.has_logical_ring_preemption) | |
fb5c551a CW |
2539 | |
2540 | #define HAS_EXECLISTS(dev_priv) HAS_LOGICAL_RING_CONTEXTS(dev_priv) | |
2541 | ||
4f044a88 MW |
2542 | #define USES_PPGTT(dev_priv) (i915_modparams.enable_ppgtt) |
2543 | #define USES_FULL_PPGTT(dev_priv) (i915_modparams.enable_ppgtt >= 2) | |
2544 | #define USES_FULL_48BIT_PPGTT(dev_priv) (i915_modparams.enable_ppgtt == 3) | |
a5c08166 MA |
2545 | #define HAS_PAGE_SIZES(dev_priv, sizes) ({ \ |
2546 | GEM_BUG_ON((sizes) == 0); \ | |
2547 | ((sizes) & ~(dev_priv)->info.page_sizes) == 0; \ | |
2548 | }) | |
0031fb96 TU |
2549 | |
2550 | #define HAS_OVERLAY(dev_priv) ((dev_priv)->info.has_overlay) | |
2551 | #define OVERLAY_NEEDS_PHYSICAL(dev_priv) \ | |
2552 | ((dev_priv)->info.overlay_needs_physical) | |
cae5852d | 2553 | |
b45305fc | 2554 | /* Early gen2 have a totally busted CS tlb and require pinned batches. */ |
2a307c2e | 2555 | #define HAS_BROKEN_CS_TLB(dev_priv) (IS_I830(dev_priv) || IS_I845G(dev_priv)) |
06e668ac | 2556 | |
d66047e4 | 2557 | /* WaRsDisableCoarsePowerGating:skl,cnl */ |
61251512 | 2558 | #define NEEDS_WaRsDisableCoarsePowerGating(dev_priv) \ |
d66047e4 RV |
2559 | (IS_CANNONLAKE(dev_priv) || \ |
2560 | IS_SKL_GT3(dev_priv) || IS_SKL_GT4(dev_priv)) | |
185c66e5 | 2561 | |
4e6b788c DV |
2562 | /* |
2563 | * dp aux and gmbus irq on gen4 seems to be able to generate legacy interrupts | |
2564 | * even when in MSI mode. This results in spurious interrupt warnings if the | |
2565 | * legacy irq no. is shared with another device. The kernel then disables that | |
2566 | * interrupt source and so prevents the other device from working properly. | |
309bd8ed VS |
2567 | * |
2568 | * Since we don't enable MSI anymore on gen4, we can always use GMBUS/AUX | |
2569 | * interrupts. | |
4e6b788c | 2570 | */ |
309bd8ed VS |
2571 | #define HAS_AUX_IRQ(dev_priv) true |
2572 | #define HAS_GMBUS_IRQ(dev_priv) (INTEL_GEN(dev_priv) >= 4) | |
b45305fc | 2573 | |
cae5852d ZN |
2574 | /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte |
2575 | * rows, which changed the alignment requirements and fence programming. | |
2576 | */ | |
50a0bc90 TU |
2577 | #define HAS_128_BYTE_Y_TILING(dev_priv) (!IS_GEN2(dev_priv) && \ |
2578 | !(IS_I915G(dev_priv) || \ | |
2579 | IS_I915GM(dev_priv))) | |
56b857a5 TU |
2580 | #define SUPPORTS_TV(dev_priv) ((dev_priv)->info.supports_tv) |
2581 | #define I915_HAS_HOTPLUG(dev_priv) ((dev_priv)->info.has_hotplug) | |
cae5852d | 2582 | |
56b857a5 | 2583 | #define HAS_FW_BLC(dev_priv) (INTEL_GEN(dev_priv) > 2) |
56b857a5 | 2584 | #define HAS_FBC(dev_priv) ((dev_priv)->info.has_fbc) |
c56b89f1 | 2585 | #define HAS_CUR_FBC(dev_priv) (!HAS_GMCH_DISPLAY(dev_priv) && INTEL_GEN(dev_priv) >= 7) |
cae5852d | 2586 | |
50a0bc90 | 2587 | #define HAS_IPS(dev_priv) (IS_HSW_ULT(dev_priv) || IS_BROADWELL(dev_priv)) |
f5adf94e | 2588 | |
56b857a5 | 2589 | #define HAS_DP_MST(dev_priv) ((dev_priv)->info.has_dp_mst) |
0c9b3715 | 2590 | |
56b857a5 TU |
2591 | #define HAS_DDI(dev_priv) ((dev_priv)->info.has_ddi) |
2592 | #define HAS_FPGA_DBG_UNCLAIMED(dev_priv) ((dev_priv)->info.has_fpga_dbg) | |
2593 | #define HAS_PSR(dev_priv) ((dev_priv)->info.has_psr) | |
fb6db0f5 | 2594 | |
56b857a5 TU |
2595 | #define HAS_RC6(dev_priv) ((dev_priv)->info.has_rc6) |
2596 | #define HAS_RC6p(dev_priv) ((dev_priv)->info.has_rc6p) | |
fb6db0f5 | 2597 | #define HAS_RC6pp(dev_priv) (false) /* HW was never validated */ |
affa9354 | 2598 | |
56b857a5 | 2599 | #define HAS_CSR(dev_priv) ((dev_priv)->info.has_csr) |
eb805623 | 2600 | |
6772ffe0 | 2601 | #define HAS_RUNTIME_PM(dev_priv) ((dev_priv)->info.has_runtime_pm) |
dfc5148f JL |
2602 | #define HAS_64BIT_RELOC(dev_priv) ((dev_priv)->info.has_64bit_reloc) |
2603 | ||
e57f1c02 MK |
2604 | #define HAS_IPC(dev_priv) ((dev_priv)->info.has_ipc) |
2605 | ||
1a3d1898 DG |
2606 | /* |
2607 | * For now, anything with a GuC requires uCode loading, and then supports | |
2608 | * command submission once loaded. But these are logically independent | |
2609 | * properties, so we have separate macros to test them. | |
2610 | */ | |
4805fe82 | 2611 | #define HAS_GUC(dev_priv) ((dev_priv)->info.has_guc) |
f8a58d63 | 2612 | #define HAS_GUC_CT(dev_priv) ((dev_priv)->info.has_guc_ct) |
4805fe82 TU |
2613 | #define HAS_GUC_UCODE(dev_priv) (HAS_GUC(dev_priv)) |
2614 | #define HAS_GUC_SCHED(dev_priv) (HAS_GUC(dev_priv)) | |
2fe2d4e3 MW |
2615 | |
2616 | /* For now, anything with a GuC has also HuC */ | |
2617 | #define HAS_HUC(dev_priv) (HAS_GUC(dev_priv)) | |
bd132858 | 2618 | #define HAS_HUC_UCODE(dev_priv) (HAS_GUC(dev_priv)) |
33a732f4 | 2619 | |
93ffbe8e | 2620 | /* Having a GuC is not the same as using a GuC */ |
121981fa MW |
2621 | #define USES_GUC(dev_priv) intel_uc_is_using_guc() |
2622 | #define USES_GUC_SUBMISSION(dev_priv) intel_uc_is_using_guc_submission() | |
2623 | #define USES_HUC(dev_priv) intel_uc_is_using_huc() | |
93ffbe8e | 2624 | |
4805fe82 | 2625 | #define HAS_RESOURCE_STREAMER(dev_priv) ((dev_priv)->info.has_resource_streamer) |
a9ed33ca | 2626 | |
4805fe82 | 2627 | #define HAS_POOLED_EU(dev_priv) ((dev_priv)->info.has_pooled_eu) |
33e141ed | 2628 | |
c5e855d0 | 2629 | #define INTEL_PCH_DEVICE_ID_MASK 0xff80 |
17a303ec PZ |
2630 | #define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00 |
2631 | #define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00 | |
2632 | #define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00 | |
2633 | #define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00 | |
2634 | #define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE 0x9c00 | |
c5e855d0 VS |
2635 | #define INTEL_PCH_WPT_DEVICE_ID_TYPE 0x8c80 |
2636 | #define INTEL_PCH_WPT_LP_DEVICE_ID_TYPE 0x9c80 | |
e7e7ea20 S |
2637 | #define INTEL_PCH_SPT_DEVICE_ID_TYPE 0xA100 |
2638 | #define INTEL_PCH_SPT_LP_DEVICE_ID_TYPE 0x9D00 | |
c5e855d0 | 2639 | #define INTEL_PCH_KBP_DEVICE_ID_TYPE 0xA280 |
7b22b8c4 | 2640 | #define INTEL_PCH_CNP_DEVICE_ID_TYPE 0xA300 |
ec7e0bb3 | 2641 | #define INTEL_PCH_CNP_LP_DEVICE_ID_TYPE 0x9D80 |
5c8ea018 | 2642 | #define INTEL_PCH_ICP_DEVICE_ID_TYPE 0x3480 |
30c964a6 | 2643 | #define INTEL_PCH_P2X_DEVICE_ID_TYPE 0x7100 |
1844a66b | 2644 | #define INTEL_PCH_P3X_DEVICE_ID_TYPE 0x7000 |
39bfcd52 | 2645 | #define INTEL_PCH_QEMU_DEVICE_ID_TYPE 0x2900 /* qemu q35 has 2918 */ |
17a303ec | 2646 | |
6e266956 | 2647 | #define INTEL_PCH_TYPE(dev_priv) ((dev_priv)->pch_type) |
81717504 | 2648 | #define INTEL_PCH_ID(dev_priv) ((dev_priv)->pch_id) |
0b58436f | 2649 | #define HAS_PCH_ICP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_ICP) |
7b22b8c4 | 2650 | #define HAS_PCH_CNP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_CNP) |
ec7e0bb3 | 2651 | #define HAS_PCH_CNP_LP(dev_priv) \ |
81717504 | 2652 | (INTEL_PCH_ID(dev_priv) == INTEL_PCH_CNP_LP_DEVICE_ID_TYPE) |
6e266956 TU |
2653 | #define HAS_PCH_KBP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_KBP) |
2654 | #define HAS_PCH_SPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_SPT) | |
2655 | #define HAS_PCH_LPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_LPT) | |
4f8036a2 | 2656 | #define HAS_PCH_LPT_LP(dev_priv) \ |
81717504 JN |
2657 | (INTEL_PCH_ID(dev_priv) == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE || \ |
2658 | INTEL_PCH_ID(dev_priv) == INTEL_PCH_WPT_LP_DEVICE_ID_TYPE) | |
4f8036a2 | 2659 | #define HAS_PCH_LPT_H(dev_priv) \ |
81717504 JN |
2660 | (INTEL_PCH_ID(dev_priv) == INTEL_PCH_LPT_DEVICE_ID_TYPE || \ |
2661 | INTEL_PCH_ID(dev_priv) == INTEL_PCH_WPT_DEVICE_ID_TYPE) | |
6e266956 TU |
2662 | #define HAS_PCH_CPT(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_CPT) |
2663 | #define HAS_PCH_IBX(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_IBX) | |
2664 | #define HAS_PCH_NOP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_NOP) | |
2665 | #define HAS_PCH_SPLIT(dev_priv) (INTEL_PCH_TYPE(dev_priv) != PCH_NONE) | |
cae5852d | 2666 | |
49cff963 | 2667 | #define HAS_GMCH_DISPLAY(dev_priv) ((dev_priv)->info.has_gmch_display) |
5fafe292 | 2668 | |
ff15947e | 2669 | #define HAS_LSPCON(dev_priv) (INTEL_GEN(dev_priv) >= 9) |
6389dd83 | 2670 | |
040d2baa | 2671 | /* DPF == dynamic parity feature */ |
3c9192bc | 2672 | #define HAS_L3_DPF(dev_priv) ((dev_priv)->info.has_l3_dpf) |
50a0bc90 TU |
2673 | #define NUM_L3_SLICES(dev_priv) (IS_HSW_GT3(dev_priv) ? \ |
2674 | 2 : HAS_L3_DPF(dev_priv)) | |
e1ef7cc2 | 2675 | |
c8735b0c | 2676 | #define GT_FREQUENCY_MULTIPLIER 50 |
de43ae9d | 2677 | #define GEN9_FREQ_SCALER 3 |
c8735b0c | 2678 | |
05394f39 CW |
2679 | #include "i915_trace.h" |
2680 | ||
80debff8 | 2681 | static inline bool intel_vtd_active(void) |
48f112fe CW |
2682 | { |
2683 | #ifdef CONFIG_INTEL_IOMMU | |
80debff8 | 2684 | if (intel_iommu_gfx_mapped) |
48f112fe CW |
2685 | return true; |
2686 | #endif | |
2687 | return false; | |
2688 | } | |
2689 | ||
80debff8 CW |
2690 | static inline bool intel_scanout_needs_vtd_wa(struct drm_i915_private *dev_priv) |
2691 | { | |
2692 | return INTEL_GEN(dev_priv) >= 6 && intel_vtd_active(); | |
2693 | } | |
2694 | ||
0ef34ad6 JB |
2695 | static inline bool |
2696 | intel_ggtt_update_needs_vtd_wa(struct drm_i915_private *dev_priv) | |
2697 | { | |
80debff8 | 2698 | return IS_BROXTON(dev_priv) && intel_vtd_active(); |
0ef34ad6 JB |
2699 | } |
2700 | ||
c033666a | 2701 | int intel_sanitize_enable_ppgtt(struct drm_i915_private *dev_priv, |
351c3b53 | 2702 | int enable_ppgtt); |
0e4ca100 | 2703 | |
0673ad47 | 2704 | /* i915_drv.c */ |
d15d7538 ID |
2705 | void __printf(3, 4) |
2706 | __i915_printk(struct drm_i915_private *dev_priv, const char *level, | |
2707 | const char *fmt, ...); | |
2708 | ||
2709 | #define i915_report_error(dev_priv, fmt, ...) \ | |
2710 | __i915_printk(dev_priv, KERN_ERR, fmt, ##__VA_ARGS__) | |
2711 | ||
c43b5634 | 2712 | #ifdef CONFIG_COMPAT |
0d6aa60b DA |
2713 | extern long i915_compat_ioctl(struct file *filp, unsigned int cmd, |
2714 | unsigned long arg); | |
55edf41b JN |
2715 | #else |
2716 | #define i915_compat_ioctl NULL | |
c43b5634 | 2717 | #endif |
efab0698 JN |
2718 | extern const struct dev_pm_ops i915_pm_ops; |
2719 | ||
2720 | extern int i915_driver_load(struct pci_dev *pdev, | |
2721 | const struct pci_device_id *ent); | |
2722 | extern void i915_driver_unload(struct drm_device *dev); | |
dc97997a CW |
2723 | extern int intel_gpu_reset(struct drm_i915_private *dev_priv, u32 engine_mask); |
2724 | extern bool intel_has_gpu_reset(struct drm_i915_private *dev_priv); | |
535275d3 | 2725 | |
d0667e9c CW |
2726 | extern void i915_reset(struct drm_i915_private *i915, |
2727 | unsigned int stalled_mask, | |
2728 | const char *reason); | |
2729 | extern int i915_reset_engine(struct intel_engine_cs *engine, | |
2730 | const char *reason); | |
535275d3 | 2731 | |
142bc7d9 | 2732 | extern bool intel_has_reset_engine(struct drm_i915_private *dev_priv); |
cb20a3c0 | 2733 | extern int intel_reset_guc(struct drm_i915_private *dev_priv); |
6acbea89 MT |
2734 | extern int intel_guc_reset_engine(struct intel_guc *guc, |
2735 | struct intel_engine_cs *engine); | |
fc0768ce | 2736 | extern void intel_engine_init_hangcheck(struct intel_engine_cs *engine); |
3ac168a7 | 2737 | extern void intel_hangcheck_init(struct drm_i915_private *dev_priv); |
7648fa99 JB |
2738 | extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv); |
2739 | extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv); | |
2740 | extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv); | |
2741 | extern void i915_update_gfx_val(struct drm_i915_private *dev_priv); | |
650ad970 | 2742 | int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool on); |
7648fa99 | 2743 | |
63ffbcda | 2744 | int intel_engines_init_mmio(struct drm_i915_private *dev_priv); |
bb8f0f5a CW |
2745 | int intel_engines_init(struct drm_i915_private *dev_priv); |
2746 | ||
77913b39 | 2747 | /* intel_hotplug.c */ |
91d14251 TU |
2748 | void intel_hpd_irq_handler(struct drm_i915_private *dev_priv, |
2749 | u32 pin_mask, u32 long_mask); | |
77913b39 JN |
2750 | void intel_hpd_init(struct drm_i915_private *dev_priv); |
2751 | void intel_hpd_init_work(struct drm_i915_private *dev_priv); | |
2752 | void intel_hpd_cancel_work(struct drm_i915_private *dev_priv); | |
cf53902f RV |
2753 | enum port intel_hpd_pin_to_port(struct drm_i915_private *dev_priv, |
2754 | enum hpd_pin pin); | |
2755 | enum hpd_pin intel_hpd_pin_default(struct drm_i915_private *dev_priv, | |
2756 | enum port port); | |
b236d7c8 L |
2757 | bool intel_hpd_disable(struct drm_i915_private *dev_priv, enum hpd_pin pin); |
2758 | void intel_hpd_enable(struct drm_i915_private *dev_priv, enum hpd_pin pin); | |
77913b39 | 2759 | |
1da177e4 | 2760 | /* i915_irq.c */ |
26a02b8f CW |
2761 | static inline void i915_queue_hangcheck(struct drm_i915_private *dev_priv) |
2762 | { | |
2763 | unsigned long delay; | |
2764 | ||
4f044a88 | 2765 | if (unlikely(!i915_modparams.enable_hangcheck)) |
26a02b8f CW |
2766 | return; |
2767 | ||
2768 | /* Don't continually defer the hangcheck so that it is always run at | |
2769 | * least once after work has been scheduled on any ring. Otherwise, | |
2770 | * we will ignore a hung ring if a second ring is kept busy. | |
2771 | */ | |
2772 | ||
2773 | delay = round_jiffies_up_relative(DRM_I915_HANGCHECK_JIFFIES); | |
2774 | queue_delayed_work(system_long_wq, | |
2775 | &dev_priv->gpu_error.hangcheck_work, delay); | |
2776 | } | |
2777 | ||
ce800754 | 2778 | __printf(4, 5) |
c033666a CW |
2779 | void i915_handle_error(struct drm_i915_private *dev_priv, |
2780 | u32 engine_mask, | |
ce800754 | 2781 | unsigned long flags, |
58174462 | 2782 | const char *fmt, ...); |
ce800754 | 2783 | #define I915_ERROR_CAPTURE BIT(0) |
1da177e4 | 2784 | |
b963291c | 2785 | extern void intel_irq_init(struct drm_i915_private *dev_priv); |
cefcff8f | 2786 | extern void intel_irq_fini(struct drm_i915_private *dev_priv); |
2aeb7d3a DV |
2787 | int intel_irq_install(struct drm_i915_private *dev_priv); |
2788 | void intel_irq_uninstall(struct drm_i915_private *dev_priv); | |
907b28c5 | 2789 | |
0ad35fed ZW |
2790 | static inline bool intel_gvt_active(struct drm_i915_private *dev_priv) |
2791 | { | |
feddf6e8 | 2792 | return dev_priv->gvt; |
0ad35fed ZW |
2793 | } |
2794 | ||
c033666a | 2795 | static inline bool intel_vgpu_active(struct drm_i915_private *dev_priv) |
cf9d2890 | 2796 | { |
c033666a | 2797 | return dev_priv->vgpu.active; |
cf9d2890 | 2798 | } |
b1f14ad0 | 2799 | |
6b12ca56 VS |
2800 | u32 i915_pipestat_enable_mask(struct drm_i915_private *dev_priv, |
2801 | enum pipe pipe); | |
7c463586 | 2802 | void |
50227e1c | 2803 | i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe, |
755e9019 | 2804 | u32 status_mask); |
7c463586 KP |
2805 | |
2806 | void | |
50227e1c | 2807 | i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe, |
755e9019 | 2808 | u32 status_mask); |
7c463586 | 2809 | |
f8b79e58 ID |
2810 | void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv); |
2811 | void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv); | |
0706f17c EE |
2812 | void i915_hotplug_interrupt_update(struct drm_i915_private *dev_priv, |
2813 | uint32_t mask, | |
2814 | uint32_t bits); | |
fbdedaea VS |
2815 | void ilk_update_display_irq(struct drm_i915_private *dev_priv, |
2816 | uint32_t interrupt_mask, | |
2817 | uint32_t enabled_irq_mask); | |
2818 | static inline void | |
2819 | ilk_enable_display_irq(struct drm_i915_private *dev_priv, uint32_t bits) | |
2820 | { | |
2821 | ilk_update_display_irq(dev_priv, bits, bits); | |
2822 | } | |
2823 | static inline void | |
2824 | ilk_disable_display_irq(struct drm_i915_private *dev_priv, uint32_t bits) | |
2825 | { | |
2826 | ilk_update_display_irq(dev_priv, bits, 0); | |
2827 | } | |
013d3752 VS |
2828 | void bdw_update_pipe_irq(struct drm_i915_private *dev_priv, |
2829 | enum pipe pipe, | |
2830 | uint32_t interrupt_mask, | |
2831 | uint32_t enabled_irq_mask); | |
2832 | static inline void bdw_enable_pipe_irq(struct drm_i915_private *dev_priv, | |
2833 | enum pipe pipe, uint32_t bits) | |
2834 | { | |
2835 | bdw_update_pipe_irq(dev_priv, pipe, bits, bits); | |
2836 | } | |
2837 | static inline void bdw_disable_pipe_irq(struct drm_i915_private *dev_priv, | |
2838 | enum pipe pipe, uint32_t bits) | |
2839 | { | |
2840 | bdw_update_pipe_irq(dev_priv, pipe, bits, 0); | |
2841 | } | |
47339cd9 DV |
2842 | void ibx_display_interrupt_update(struct drm_i915_private *dev_priv, |
2843 | uint32_t interrupt_mask, | |
2844 | uint32_t enabled_irq_mask); | |
14443261 VS |
2845 | static inline void |
2846 | ibx_enable_display_interrupt(struct drm_i915_private *dev_priv, uint32_t bits) | |
2847 | { | |
2848 | ibx_display_interrupt_update(dev_priv, bits, bits); | |
2849 | } | |
2850 | static inline void | |
2851 | ibx_disable_display_interrupt(struct drm_i915_private *dev_priv, uint32_t bits) | |
2852 | { | |
2853 | ibx_display_interrupt_update(dev_priv, bits, 0); | |
2854 | } | |
2855 | ||
673a394b | 2856 | /* i915_gem.c */ |
673a394b EA |
2857 | int i915_gem_create_ioctl(struct drm_device *dev, void *data, |
2858 | struct drm_file *file_priv); | |
2859 | int i915_gem_pread_ioctl(struct drm_device *dev, void *data, | |
2860 | struct drm_file *file_priv); | |
2861 | int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data, | |
2862 | struct drm_file *file_priv); | |
2863 | int i915_gem_mmap_ioctl(struct drm_device *dev, void *data, | |
2864 | struct drm_file *file_priv); | |
de151cf6 JB |
2865 | int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data, |
2866 | struct drm_file *file_priv); | |
673a394b EA |
2867 | int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data, |
2868 | struct drm_file *file_priv); | |
2869 | int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data, | |
2870 | struct drm_file *file_priv); | |
6a20fe7b VS |
2871 | int i915_gem_execbuffer_ioctl(struct drm_device *dev, void *data, |
2872 | struct drm_file *file_priv); | |
2873 | int i915_gem_execbuffer2_ioctl(struct drm_device *dev, void *data, | |
2874 | struct drm_file *file_priv); | |
673a394b EA |
2875 | int i915_gem_busy_ioctl(struct drm_device *dev, void *data, |
2876 | struct drm_file *file_priv); | |
199adf40 BW |
2877 | int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data, |
2878 | struct drm_file *file); | |
2879 | int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data, | |
2880 | struct drm_file *file); | |
673a394b EA |
2881 | int i915_gem_throttle_ioctl(struct drm_device *dev, void *data, |
2882 | struct drm_file *file_priv); | |
3ef94daa CW |
2883 | int i915_gem_madvise_ioctl(struct drm_device *dev, void *data, |
2884 | struct drm_file *file_priv); | |
111dbcab CW |
2885 | int i915_gem_set_tiling_ioctl(struct drm_device *dev, void *data, |
2886 | struct drm_file *file_priv); | |
2887 | int i915_gem_get_tiling_ioctl(struct drm_device *dev, void *data, | |
2888 | struct drm_file *file_priv); | |
8a2421bd CW |
2889 | int i915_gem_init_userptr(struct drm_i915_private *dev_priv); |
2890 | void i915_gem_cleanup_userptr(struct drm_i915_private *dev_priv); | |
5cc9ed4b CW |
2891 | int i915_gem_userptr_ioctl(struct drm_device *dev, void *data, |
2892 | struct drm_file *file); | |
5a125c3c EA |
2893 | int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data, |
2894 | struct drm_file *file_priv); | |
23ba4fd0 BW |
2895 | int i915_gem_wait_ioctl(struct drm_device *dev, void *data, |
2896 | struct drm_file *file_priv); | |
24145517 | 2897 | void i915_gem_sanitize(struct drm_i915_private *i915); |
a0de908d MW |
2898 | int i915_gem_init_early(struct drm_i915_private *dev_priv); |
2899 | void i915_gem_cleanup_early(struct drm_i915_private *dev_priv); | |
40ae4e16 | 2900 | void i915_gem_load_init_fences(struct drm_i915_private *dev_priv); |
6a800eab | 2901 | int i915_gem_freeze(struct drm_i915_private *dev_priv); |
461fb99c CW |
2902 | int i915_gem_freeze_late(struct drm_i915_private *dev_priv); |
2903 | ||
187685cb | 2904 | void *i915_gem_object_alloc(struct drm_i915_private *dev_priv); |
42dcedd4 | 2905 | void i915_gem_object_free(struct drm_i915_gem_object *obj); |
37e680a1 CW |
2906 | void i915_gem_object_init(struct drm_i915_gem_object *obj, |
2907 | const struct drm_i915_gem_object_ops *ops); | |
12d79d78 TU |
2908 | struct drm_i915_gem_object * |
2909 | i915_gem_object_create(struct drm_i915_private *dev_priv, u64 size); | |
2910 | struct drm_i915_gem_object * | |
2911 | i915_gem_object_create_from_data(struct drm_i915_private *dev_priv, | |
2912 | const void *data, size_t size); | |
b1f788c6 | 2913 | void i915_gem_close_object(struct drm_gem_object *gem, struct drm_file *file); |
673a394b | 2914 | void i915_gem_free_object(struct drm_gem_object *obj); |
42dcedd4 | 2915 | |
bdeb9785 CW |
2916 | static inline void i915_gem_drain_freed_objects(struct drm_i915_private *i915) |
2917 | { | |
c9c70471 CW |
2918 | if (!atomic_read(&i915->mm.free_count)) |
2919 | return; | |
2920 | ||
bdeb9785 CW |
2921 | /* A single pass should suffice to release all the freed objects (along |
2922 | * most call paths) , but be a little more paranoid in that freeing | |
2923 | * the objects does take a little amount of time, during which the rcu | |
2924 | * callbacks could have added new objects into the freed list, and | |
2925 | * armed the work again. | |
2926 | */ | |
2927 | do { | |
2928 | rcu_barrier(); | |
2929 | } while (flush_work(&i915->mm.free_work)); | |
2930 | } | |
2931 | ||
3b19f16a CW |
2932 | static inline void i915_gem_drain_workqueue(struct drm_i915_private *i915) |
2933 | { | |
2934 | /* | |
2935 | * Similar to objects above (see i915_gem_drain_freed-objects), in | |
2936 | * general we have workers that are armed by RCU and then rearm | |
2937 | * themselves in their callbacks. To be paranoid, we need to | |
2938 | * drain the workqueue a second time after waiting for the RCU | |
2939 | * grace period so that we catch work queued via RCU from the first | |
2940 | * pass. As neither drain_workqueue() nor flush_workqueue() report | |
2941 | * a result, we make an assumption that we only don't require more | |
2942 | * than 2 passes to catch all recursive RCU delayed work. | |
2943 | * | |
2944 | */ | |
2945 | int pass = 2; | |
2946 | do { | |
2947 | rcu_barrier(); | |
2948 | drain_workqueue(i915->wq); | |
2949 | } while (--pass); | |
2950 | } | |
2951 | ||
058d88c4 | 2952 | struct i915_vma * __must_check |
ec7adb6e JL |
2953 | i915_gem_object_ggtt_pin(struct drm_i915_gem_object *obj, |
2954 | const struct i915_ggtt_view *view, | |
91b2db6f | 2955 | u64 size, |
2ffffd0f CW |
2956 | u64 alignment, |
2957 | u64 flags); | |
fe14d5f4 | 2958 | |
aa653a68 | 2959 | int i915_gem_object_unbind(struct drm_i915_gem_object *obj); |
05394f39 | 2960 | void i915_gem_release_mmap(struct drm_i915_gem_object *obj); |
f787a5f5 | 2961 | |
7c108fd8 CW |
2962 | void i915_gem_runtime_suspend(struct drm_i915_private *dev_priv); |
2963 | ||
a4f5ea64 | 2964 | static inline int __sg_page_count(const struct scatterlist *sg) |
9da3da66 | 2965 | { |
ee286370 CW |
2966 | return sg->length >> PAGE_SHIFT; |
2967 | } | |
67d5a50c | 2968 | |
96d77634 CW |
2969 | struct scatterlist * |
2970 | i915_gem_object_get_sg(struct drm_i915_gem_object *obj, | |
2971 | unsigned int n, unsigned int *offset); | |
341be1cd | 2972 | |
96d77634 CW |
2973 | struct page * |
2974 | i915_gem_object_get_page(struct drm_i915_gem_object *obj, | |
2975 | unsigned int n); | |
67d5a50c | 2976 | |
96d77634 CW |
2977 | struct page * |
2978 | i915_gem_object_get_dirty_page(struct drm_i915_gem_object *obj, | |
2979 | unsigned int n); | |
67d5a50c | 2980 | |
96d77634 CW |
2981 | dma_addr_t |
2982 | i915_gem_object_get_dma_address(struct drm_i915_gem_object *obj, | |
2983 | unsigned long n); | |
ee286370 | 2984 | |
03ac84f1 | 2985 | void __i915_gem_object_set_pages(struct drm_i915_gem_object *obj, |
a5c08166 | 2986 | struct sg_table *pages, |
84e8978e | 2987 | unsigned int sg_page_sizes); |
a4f5ea64 CW |
2988 | int __i915_gem_object_get_pages(struct drm_i915_gem_object *obj); |
2989 | ||
2990 | static inline int __must_check | |
2991 | i915_gem_object_pin_pages(struct drm_i915_gem_object *obj) | |
2992 | { | |
1233e2db | 2993 | might_lock(&obj->mm.lock); |
a4f5ea64 | 2994 | |
1233e2db | 2995 | if (atomic_inc_not_zero(&obj->mm.pages_pin_count)) |
a4f5ea64 CW |
2996 | return 0; |
2997 | ||
2998 | return __i915_gem_object_get_pages(obj); | |
2999 | } | |
3000 | ||
f1fa4f44 CW |
3001 | static inline bool |
3002 | i915_gem_object_has_pages(struct drm_i915_gem_object *obj) | |
3003 | { | |
3004 | return !IS_ERR_OR_NULL(READ_ONCE(obj->mm.pages)); | |
3005 | } | |
3006 | ||
a4f5ea64 CW |
3007 | static inline void |
3008 | __i915_gem_object_pin_pages(struct drm_i915_gem_object *obj) | |
a5570178 | 3009 | { |
f1fa4f44 | 3010 | GEM_BUG_ON(!i915_gem_object_has_pages(obj)); |
a4f5ea64 | 3011 | |
1233e2db | 3012 | atomic_inc(&obj->mm.pages_pin_count); |
a4f5ea64 CW |
3013 | } |
3014 | ||
3015 | static inline bool | |
3016 | i915_gem_object_has_pinned_pages(struct drm_i915_gem_object *obj) | |
3017 | { | |
1233e2db | 3018 | return atomic_read(&obj->mm.pages_pin_count); |
a4f5ea64 CW |
3019 | } |
3020 | ||
3021 | static inline void | |
3022 | __i915_gem_object_unpin_pages(struct drm_i915_gem_object *obj) | |
3023 | { | |
f1fa4f44 | 3024 | GEM_BUG_ON(!i915_gem_object_has_pages(obj)); |
a4f5ea64 | 3025 | GEM_BUG_ON(!i915_gem_object_has_pinned_pages(obj)); |
a4f5ea64 | 3026 | |
1233e2db | 3027 | atomic_dec(&obj->mm.pages_pin_count); |
a5570178 | 3028 | } |
0a798eb9 | 3029 | |
1233e2db CW |
3030 | static inline void |
3031 | i915_gem_object_unpin_pages(struct drm_i915_gem_object *obj) | |
a5570178 | 3032 | { |
a4f5ea64 | 3033 | __i915_gem_object_unpin_pages(obj); |
a5570178 CW |
3034 | } |
3035 | ||
548625ee CW |
3036 | enum i915_mm_subclass { /* lockdep subclass for obj->mm.lock */ |
3037 | I915_MM_NORMAL = 0, | |
3038 | I915_MM_SHRINKER | |
3039 | }; | |
3040 | ||
3041 | void __i915_gem_object_put_pages(struct drm_i915_gem_object *obj, | |
3042 | enum i915_mm_subclass subclass); | |
03ac84f1 | 3043 | void __i915_gem_object_invalidate(struct drm_i915_gem_object *obj); |
a4f5ea64 | 3044 | |
d31d7cb1 CW |
3045 | enum i915_map_type { |
3046 | I915_MAP_WB = 0, | |
3047 | I915_MAP_WC, | |
a575c676 CW |
3048 | #define I915_MAP_OVERRIDE BIT(31) |
3049 | I915_MAP_FORCE_WB = I915_MAP_WB | I915_MAP_OVERRIDE, | |
3050 | I915_MAP_FORCE_WC = I915_MAP_WC | I915_MAP_OVERRIDE, | |
d31d7cb1 CW |
3051 | }; |
3052 | ||
0a798eb9 CW |
3053 | /** |
3054 | * i915_gem_object_pin_map - return a contiguous mapping of the entire object | |
a73c7a44 CW |
3055 | * @obj: the object to map into kernel address space |
3056 | * @type: the type of mapping, used to select pgprot_t | |
0a798eb9 CW |
3057 | * |
3058 | * Calls i915_gem_object_pin_pages() to prevent reaping of the object's | |
3059 | * pages and then returns a contiguous mapping of the backing storage into | |
d31d7cb1 CW |
3060 | * the kernel address space. Based on the @type of mapping, the PTE will be |
3061 | * set to either WriteBack or WriteCombine (via pgprot_t). | |
0a798eb9 | 3062 | * |
1233e2db CW |
3063 | * The caller is responsible for calling i915_gem_object_unpin_map() when the |
3064 | * mapping is no longer required. | |
0a798eb9 | 3065 | * |
8305216f DG |
3066 | * Returns the pointer through which to access the mapped object, or an |
3067 | * ERR_PTR() on error. | |
0a798eb9 | 3068 | */ |
d31d7cb1 CW |
3069 | void *__must_check i915_gem_object_pin_map(struct drm_i915_gem_object *obj, |
3070 | enum i915_map_type type); | |
0a798eb9 CW |
3071 | |
3072 | /** | |
3073 | * i915_gem_object_unpin_map - releases an earlier mapping | |
a73c7a44 | 3074 | * @obj: the object to unmap |
0a798eb9 CW |
3075 | * |
3076 | * After pinning the object and mapping its pages, once you are finished | |
3077 | * with your access, call i915_gem_object_unpin_map() to release the pin | |
3078 | * upon the mapping. Once the pin count reaches zero, that mapping may be | |
3079 | * removed. | |
0a798eb9 CW |
3080 | */ |
3081 | static inline void i915_gem_object_unpin_map(struct drm_i915_gem_object *obj) | |
3082 | { | |
0a798eb9 CW |
3083 | i915_gem_object_unpin_pages(obj); |
3084 | } | |
3085 | ||
43394c7d CW |
3086 | int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj, |
3087 | unsigned int *needs_clflush); | |
3088 | int i915_gem_obj_prepare_shmem_write(struct drm_i915_gem_object *obj, | |
3089 | unsigned int *needs_clflush); | |
7f5f95d8 CW |
3090 | #define CLFLUSH_BEFORE BIT(0) |
3091 | #define CLFLUSH_AFTER BIT(1) | |
3092 | #define CLFLUSH_FLAGS (CLFLUSH_BEFORE | CLFLUSH_AFTER) | |
43394c7d CW |
3093 | |
3094 | static inline void | |
3095 | i915_gem_obj_finish_shmem_access(struct drm_i915_gem_object *obj) | |
3096 | { | |
3097 | i915_gem_object_unpin_pages(obj); | |
3098 | } | |
3099 | ||
54cf91dc | 3100 | int __must_check i915_mutex_lock_interruptible(struct drm_device *dev); |
e2d05a8b | 3101 | void i915_vma_move_to_active(struct i915_vma *vma, |
e61e0f51 | 3102 | struct i915_request *rq, |
5cf3d280 | 3103 | unsigned int flags); |
ff72145b DA |
3104 | int i915_gem_dumb_create(struct drm_file *file_priv, |
3105 | struct drm_device *dev, | |
3106 | struct drm_mode_create_dumb *args); | |
da6b51d0 DA |
3107 | int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev, |
3108 | uint32_t handle, uint64_t *offset); | |
4cc69075 | 3109 | int i915_gem_mmap_gtt_version(void); |
85d1225e DG |
3110 | |
3111 | void i915_gem_track_fb(struct drm_i915_gem_object *old, | |
3112 | struct drm_i915_gem_object *new, | |
3113 | unsigned frontbuffer_bits); | |
3114 | ||
73cb9701 | 3115 | int __must_check i915_gem_set_global_seqno(struct drm_device *dev, u32 seqno); |
1690e1eb | 3116 | |
e61e0f51 | 3117 | struct i915_request * |
0bc40be8 | 3118 | i915_gem_find_active_request(struct intel_engine_cs *engine); |
8d9fc7fd | 3119 | |
8c185eca CW |
3120 | static inline bool i915_reset_backoff(struct i915_gpu_error *error) |
3121 | { | |
3122 | return unlikely(test_bit(I915_RESET_BACKOFF, &error->flags)); | |
3123 | } | |
3124 | ||
3125 | static inline bool i915_reset_handoff(struct i915_gpu_error *error) | |
1f83fee0 | 3126 | { |
8c185eca | 3127 | return unlikely(test_bit(I915_RESET_HANDOFF, &error->flags)); |
c19ae989 CW |
3128 | } |
3129 | ||
8af29b0c | 3130 | static inline bool i915_terminally_wedged(struct i915_gpu_error *error) |
c19ae989 | 3131 | { |
8af29b0c | 3132 | return unlikely(test_bit(I915_WEDGED, &error->flags)); |
1f83fee0 DV |
3133 | } |
3134 | ||
8c185eca | 3135 | static inline bool i915_reset_backoff_or_wedged(struct i915_gpu_error *error) |
1f83fee0 | 3136 | { |
8c185eca | 3137 | return i915_reset_backoff(error) | i915_terminally_wedged(error); |
2ac0f450 MK |
3138 | } |
3139 | ||
3140 | static inline u32 i915_reset_count(struct i915_gpu_error *error) | |
3141 | { | |
8af29b0c | 3142 | return READ_ONCE(error->reset_count); |
1f83fee0 | 3143 | } |
a71d8d94 | 3144 | |
702c8f8e MT |
3145 | static inline u32 i915_reset_engine_count(struct i915_gpu_error *error, |
3146 | struct intel_engine_cs *engine) | |
3147 | { | |
3148 | return READ_ONCE(error->reset_engine_count[engine->id]); | |
3149 | } | |
3150 | ||
e61e0f51 | 3151 | struct i915_request * |
a1ef70e1 | 3152 | i915_gem_reset_prepare_engine(struct intel_engine_cs *engine); |
0e178aef | 3153 | int i915_gem_reset_prepare(struct drm_i915_private *dev_priv); |
d0667e9c CW |
3154 | void i915_gem_reset(struct drm_i915_private *dev_priv, |
3155 | unsigned int stalled_mask); | |
a1ef70e1 | 3156 | void i915_gem_reset_finish_engine(struct intel_engine_cs *engine); |
b1ed35d9 | 3157 | void i915_gem_reset_finish(struct drm_i915_private *dev_priv); |
821ed7df | 3158 | void i915_gem_set_wedged(struct drm_i915_private *dev_priv); |
2e8f9d32 | 3159 | bool i915_gem_unset_wedged(struct drm_i915_private *dev_priv); |
a1ef70e1 | 3160 | void i915_gem_reset_engine(struct intel_engine_cs *engine, |
bba0869b CW |
3161 | struct i915_request *request, |
3162 | bool stalled); | |
57822dc6 | 3163 | |
24145517 | 3164 | void i915_gem_init_mmio(struct drm_i915_private *i915); |
bf9e8429 TU |
3165 | int __must_check i915_gem_init(struct drm_i915_private *dev_priv); |
3166 | int __must_check i915_gem_init_hw(struct drm_i915_private *dev_priv); | |
c6be607a | 3167 | void i915_gem_init_swizzling(struct drm_i915_private *dev_priv); |
cb15d9f8 | 3168 | void i915_gem_cleanup_engines(struct drm_i915_private *dev_priv); |
496b575e CW |
3169 | int i915_gem_wait_for_idle(struct drm_i915_private *dev_priv, |
3170 | unsigned int flags); | |
bf9e8429 TU |
3171 | int __must_check i915_gem_suspend(struct drm_i915_private *dev_priv); |
3172 | void i915_gem_resume(struct drm_i915_private *dev_priv); | |
11bac800 | 3173 | int i915_gem_fault(struct vm_fault *vmf); |
e95433c7 CW |
3174 | int i915_gem_object_wait(struct drm_i915_gem_object *obj, |
3175 | unsigned int flags, | |
3176 | long timeout, | |
3177 | struct intel_rps_client *rps); | |
6b5e90f5 CW |
3178 | int i915_gem_object_wait_priority(struct drm_i915_gem_object *obj, |
3179 | unsigned int flags, | |
b7268c5e | 3180 | const struct i915_sched_attr *attr); |
6b5e90f5 CW |
3181 | #define I915_PRIORITY_DISPLAY I915_PRIORITY_MAX |
3182 | ||
2e2f351d | 3183 | int __must_check |
e22d8e3c CW |
3184 | i915_gem_object_set_to_wc_domain(struct drm_i915_gem_object *obj, bool write); |
3185 | int __must_check | |
3186 | i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write); | |
2021746e | 3187 | int __must_check |
dabdfe02 | 3188 | i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write); |
058d88c4 | 3189 | struct i915_vma * __must_check |
2da3b9b9 CW |
3190 | i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj, |
3191 | u32 alignment, | |
5935485f CW |
3192 | const struct i915_ggtt_view *view, |
3193 | unsigned int flags); | |
058d88c4 | 3194 | void i915_gem_object_unpin_from_display_plane(struct i915_vma *vma); |
00731155 | 3195 | int i915_gem_object_attach_phys(struct drm_i915_gem_object *obj, |
6eeefaf3 | 3196 | int align); |
829a0af2 | 3197 | int i915_gem_open(struct drm_i915_private *i915, struct drm_file *file); |
05394f39 | 3198 | void i915_gem_release(struct drm_device *dev, struct drm_file *file); |
673a394b | 3199 | |
e4ffd173 CW |
3200 | int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj, |
3201 | enum i915_cache_level cache_level); | |
3202 | ||
1286ff73 DV |
3203 | struct drm_gem_object *i915_gem_prime_import(struct drm_device *dev, |
3204 | struct dma_buf *dma_buf); | |
3205 | ||
3206 | struct dma_buf *i915_gem_prime_export(struct drm_device *dev, | |
3207 | struct drm_gem_object *gem_obj, int flags); | |
3208 | ||
841cd773 DV |
3209 | static inline struct i915_hw_ppgtt * |
3210 | i915_vm_to_ppgtt(struct i915_address_space *vm) | |
3211 | { | |
841cd773 DV |
3212 | return container_of(vm, struct i915_hw_ppgtt, base); |
3213 | } | |
3214 | ||
b42fe9ca | 3215 | /* i915_gem_fence_reg.c */ |
969b0950 CD |
3216 | struct drm_i915_fence_reg * |
3217 | i915_reserve_fence(struct drm_i915_private *dev_priv); | |
3218 | void i915_unreserve_fence(struct drm_i915_fence_reg *fence); | |
49ef5294 | 3219 | |
b1ed35d9 | 3220 | void i915_gem_revoke_fences(struct drm_i915_private *dev_priv); |
4362f4f6 | 3221 | void i915_gem_restore_fences(struct drm_i915_private *dev_priv); |
41a36b73 | 3222 | |
4362f4f6 | 3223 | void i915_gem_detect_bit_6_swizzle(struct drm_i915_private *dev_priv); |
03ac84f1 CW |
3224 | void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj, |
3225 | struct sg_table *pages); | |
3226 | void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj, | |
3227 | struct sg_table *pages); | |
7f96ecaf | 3228 | |
1acfc104 CW |
3229 | static inline struct i915_gem_context * |
3230 | __i915_gem_context_lookup_rcu(struct drm_i915_file_private *file_priv, u32 id) | |
3231 | { | |
3232 | return idr_find(&file_priv->context_idr, id); | |
3233 | } | |
3234 | ||
ca585b5d CW |
3235 | static inline struct i915_gem_context * |
3236 | i915_gem_context_lookup(struct drm_i915_file_private *file_priv, u32 id) | |
3237 | { | |
3238 | struct i915_gem_context *ctx; | |
3239 | ||
1acfc104 CW |
3240 | rcu_read_lock(); |
3241 | ctx = __i915_gem_context_lookup_rcu(file_priv, id); | |
3242 | if (ctx && !kref_get_unless_zero(&ctx->ref)) | |
3243 | ctx = NULL; | |
3244 | rcu_read_unlock(); | |
ca585b5d CW |
3245 | |
3246 | return ctx; | |
3247 | } | |
3248 | ||
eec688e1 RB |
3249 | int i915_perf_open_ioctl(struct drm_device *dev, void *data, |
3250 | struct drm_file *file); | |
f89823c2 LL |
3251 | int i915_perf_add_config_ioctl(struct drm_device *dev, void *data, |
3252 | struct drm_file *file); | |
3253 | int i915_perf_remove_config_ioctl(struct drm_device *dev, void *data, | |
3254 | struct drm_file *file); | |
19f81df2 RB |
3255 | void i915_oa_init_reg_state(struct intel_engine_cs *engine, |
3256 | struct i915_gem_context *ctx, | |
3257 | uint32_t *reg_state); | |
eec688e1 | 3258 | |
679845ed | 3259 | /* i915_gem_evict.c */ |
e522ac23 | 3260 | int __must_check i915_gem_evict_something(struct i915_address_space *vm, |
2ffffd0f | 3261 | u64 min_size, u64 alignment, |
679845ed | 3262 | unsigned cache_level, |
2ffffd0f | 3263 | u64 start, u64 end, |
1ec9e26d | 3264 | unsigned flags); |
625d988a CW |
3265 | int __must_check i915_gem_evict_for_node(struct i915_address_space *vm, |
3266 | struct drm_mm_node *node, | |
3267 | unsigned int flags); | |
2889caa9 | 3268 | int i915_gem_evict_vm(struct i915_address_space *vm); |
1d2a314c | 3269 | |
7125397b CW |
3270 | void i915_gem_flush_ggtt_writes(struct drm_i915_private *dev_priv); |
3271 | ||
0260c420 | 3272 | /* belongs in i915_gem_gtt.h */ |
c033666a | 3273 | static inline void i915_gem_chipset_flush(struct drm_i915_private *dev_priv) |
e76e9aeb | 3274 | { |
600f4368 | 3275 | wmb(); |
c033666a | 3276 | if (INTEL_GEN(dev_priv) < 6) |
e76e9aeb BW |
3277 | intel_gtt_chipset_flush(); |
3278 | } | |
246cbfb5 | 3279 | |
9797fbfb | 3280 | /* i915_gem_stolen.c */ |
d713fd49 PZ |
3281 | int i915_gem_stolen_insert_node(struct drm_i915_private *dev_priv, |
3282 | struct drm_mm_node *node, u64 size, | |
3283 | unsigned alignment); | |
a9da512b PZ |
3284 | int i915_gem_stolen_insert_node_in_range(struct drm_i915_private *dev_priv, |
3285 | struct drm_mm_node *node, u64 size, | |
3286 | unsigned alignment, u64 start, | |
3287 | u64 end); | |
d713fd49 PZ |
3288 | void i915_gem_stolen_remove_node(struct drm_i915_private *dev_priv, |
3289 | struct drm_mm_node *node); | |
7ace3d30 | 3290 | int i915_gem_init_stolen(struct drm_i915_private *dev_priv); |
9797fbfb | 3291 | void i915_gem_cleanup_stolen(struct drm_device *dev); |
0104fdbb | 3292 | struct drm_i915_gem_object * |
b7128ef1 MA |
3293 | i915_gem_object_create_stolen(struct drm_i915_private *dev_priv, |
3294 | resource_size_t size); | |
866d12b4 | 3295 | struct drm_i915_gem_object * |
187685cb | 3296 | i915_gem_object_create_stolen_for_preallocated(struct drm_i915_private *dev_priv, |
b7128ef1 MA |
3297 | resource_size_t stolen_offset, |
3298 | resource_size_t gtt_offset, | |
3299 | resource_size_t size); | |
9797fbfb | 3300 | |
920cf419 CW |
3301 | /* i915_gem_internal.c */ |
3302 | struct drm_i915_gem_object * | |
3303 | i915_gem_object_create_internal(struct drm_i915_private *dev_priv, | |
fcd46e53 | 3304 | phys_addr_t size); |
920cf419 | 3305 | |
be6a0376 | 3306 | /* i915_gem_shrinker.c */ |
56fa4bf2 | 3307 | unsigned long i915_gem_shrink(struct drm_i915_private *i915, |
14387540 | 3308 | unsigned long target, |
912d572d | 3309 | unsigned long *nr_scanned, |
be6a0376 DV |
3310 | unsigned flags); |
3311 | #define I915_SHRINK_PURGEABLE 0x1 | |
3312 | #define I915_SHRINK_UNBOUND 0x2 | |
3313 | #define I915_SHRINK_BOUND 0x4 | |
5763ff04 | 3314 | #define I915_SHRINK_ACTIVE 0x8 |
eae2c43b | 3315 | #define I915_SHRINK_VMAPS 0x10 |
56fa4bf2 CW |
3316 | unsigned long i915_gem_shrink_all(struct drm_i915_private *i915); |
3317 | void i915_gem_shrinker_register(struct drm_i915_private *i915); | |
3318 | void i915_gem_shrinker_unregister(struct drm_i915_private *i915); | |
be6a0376 DV |
3319 | |
3320 | ||
673a394b | 3321 | /* i915_gem_tiling.c */ |
2c1792a1 | 3322 | static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj) |
e9b73c67 | 3323 | { |
091387c1 | 3324 | struct drm_i915_private *dev_priv = to_i915(obj->base.dev); |
e9b73c67 CW |
3325 | |
3326 | return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 && | |
3e510a8e | 3327 | i915_gem_object_is_tiled(obj); |
e9b73c67 CW |
3328 | } |
3329 | ||
91d4e0aa CW |
3330 | u32 i915_gem_fence_size(struct drm_i915_private *dev_priv, u32 size, |
3331 | unsigned int tiling, unsigned int stride); | |
3332 | u32 i915_gem_fence_alignment(struct drm_i915_private *dev_priv, u32 size, | |
3333 | unsigned int tiling, unsigned int stride); | |
3334 | ||
2017263e | 3335 | /* i915_debugfs.c */ |
f8c168fa | 3336 | #ifdef CONFIG_DEBUG_FS |
1dac891c | 3337 | int i915_debugfs_register(struct drm_i915_private *dev_priv); |
249e87de | 3338 | int i915_debugfs_connector_add(struct drm_connector *connector); |
36cdd013 | 3339 | void intel_display_crc_init(struct drm_i915_private *dev_priv); |
07144428 | 3340 | #else |
8d35acba | 3341 | static inline int i915_debugfs_register(struct drm_i915_private *dev_priv) {return 0;} |
101057fa DV |
3342 | static inline int i915_debugfs_connector_add(struct drm_connector *connector) |
3343 | { return 0; } | |
ce5e2ac1 | 3344 | static inline void intel_display_crc_init(struct drm_i915_private *dev_priv) {} |
07144428 | 3345 | #endif |
84734a04 | 3346 | |
0a4cd7c8 | 3347 | const char *i915_cache_level_str(struct drm_i915_private *i915, int type); |
2017263e | 3348 | |
351e3db2 | 3349 | /* i915_cmd_parser.c */ |
1ca3712c | 3350 | int i915_cmd_parser_get_version(struct drm_i915_private *dev_priv); |
7756e454 | 3351 | void intel_engine_init_cmd_parser(struct intel_engine_cs *engine); |
33a051a5 | 3352 | void intel_engine_cleanup_cmd_parser(struct intel_engine_cs *engine); |
33a051a5 CW |
3353 | int intel_engine_cmd_parser(struct intel_engine_cs *engine, |
3354 | struct drm_i915_gem_object *batch_obj, | |
3355 | struct drm_i915_gem_object *shadow_batch_obj, | |
3356 | u32 batch_start_offset, | |
3357 | u32 batch_len, | |
3358 | bool is_master); | |
351e3db2 | 3359 | |
eec688e1 RB |
3360 | /* i915_perf.c */ |
3361 | extern void i915_perf_init(struct drm_i915_private *dev_priv); | |
3362 | extern void i915_perf_fini(struct drm_i915_private *dev_priv); | |
442b8c06 RB |
3363 | extern void i915_perf_register(struct drm_i915_private *dev_priv); |
3364 | extern void i915_perf_unregister(struct drm_i915_private *dev_priv); | |
eec688e1 | 3365 | |
317c35d1 | 3366 | /* i915_suspend.c */ |
af6dc742 TU |
3367 | extern int i915_save_state(struct drm_i915_private *dev_priv); |
3368 | extern int i915_restore_state(struct drm_i915_private *dev_priv); | |
0a3e67a4 | 3369 | |
0136db58 | 3370 | /* i915_sysfs.c */ |
694c2828 DW |
3371 | void i915_setup_sysfs(struct drm_i915_private *dev_priv); |
3372 | void i915_teardown_sysfs(struct drm_i915_private *dev_priv); | |
0136db58 | 3373 | |
eef57324 JA |
3374 | /* intel_lpe_audio.c */ |
3375 | int intel_lpe_audio_init(struct drm_i915_private *dev_priv); | |
3376 | void intel_lpe_audio_teardown(struct drm_i915_private *dev_priv); | |
3377 | void intel_lpe_audio_irq_handler(struct drm_i915_private *dev_priv); | |
46d196ec | 3378 | void intel_lpe_audio_notify(struct drm_i915_private *dev_priv, |
20be551e VS |
3379 | enum pipe pipe, enum port port, |
3380 | const void *eld, int ls_clock, bool dp_output); | |
eef57324 | 3381 | |
f899fc64 | 3382 | /* intel_i2c.c */ |
40196446 TU |
3383 | extern int intel_setup_gmbus(struct drm_i915_private *dev_priv); |
3384 | extern void intel_teardown_gmbus(struct drm_i915_private *dev_priv); | |
88ac7939 JN |
3385 | extern bool intel_gmbus_is_valid_pin(struct drm_i915_private *dev_priv, |
3386 | unsigned int pin); | |
07e17a75 | 3387 | extern int intel_gmbus_output_aksv(struct i2c_adapter *adapter); |
3bd7d909 | 3388 | |
0184df46 JN |
3389 | extern struct i2c_adapter * |
3390 | intel_gmbus_get_adapter(struct drm_i915_private *dev_priv, unsigned int pin); | |
e957d772 CW |
3391 | extern void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed); |
3392 | extern void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit); | |
8f375e10 | 3393 | static inline bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter) |
b8232e90 CW |
3394 | { |
3395 | return container_of(adapter, struct intel_gmbus, adapter)->force_bit; | |
3396 | } | |
af6dc742 | 3397 | extern void intel_i2c_reset(struct drm_i915_private *dev_priv); |
f899fc64 | 3398 | |
8b8e1a89 | 3399 | /* intel_bios.c */ |
66578857 | 3400 | void intel_bios_init(struct drm_i915_private *dev_priv); |
785f076b | 3401 | void intel_bios_cleanup(struct drm_i915_private *dev_priv); |
f0067a31 | 3402 | bool intel_bios_is_valid_vbt(const void *buf, size_t size); |
3bdd14d5 | 3403 | bool intel_bios_is_tv_present(struct drm_i915_private *dev_priv); |
5a69d13d | 3404 | bool intel_bios_is_lvds_present(struct drm_i915_private *dev_priv, u8 *i2c_pin); |
22f35042 | 3405 | bool intel_bios_is_port_present(struct drm_i915_private *dev_priv, enum port port); |
951d9efe | 3406 | bool intel_bios_is_port_edp(struct drm_i915_private *dev_priv, enum port port); |
d6199256 | 3407 | bool intel_bios_is_port_dp_dual_mode(struct drm_i915_private *dev_priv, enum port port); |
7137aec1 | 3408 | bool intel_bios_is_dsi_present(struct drm_i915_private *dev_priv, enum port *port); |
d252bf68 SS |
3409 | bool intel_bios_is_port_hpd_inverted(struct drm_i915_private *dev_priv, |
3410 | enum port port); | |
6389dd83 SS |
3411 | bool intel_bios_is_lspcon_present(struct drm_i915_private *dev_priv, |
3412 | enum port port); | |
3413 | ||
723bfd70 JB |
3414 | /* intel_acpi.c */ |
3415 | #ifdef CONFIG_ACPI | |
3416 | extern void intel_register_dsm_handler(void); | |
3417 | extern void intel_unregister_dsm_handler(void); | |
3418 | #else | |
3419 | static inline void intel_register_dsm_handler(void) { return; } | |
3420 | static inline void intel_unregister_dsm_handler(void) { return; } | |
3421 | #endif /* CONFIG_ACPI */ | |
3422 | ||
94b4f3ba CW |
3423 | /* intel_device_info.c */ |
3424 | static inline struct intel_device_info * | |
3425 | mkwrite_device_info(struct drm_i915_private *dev_priv) | |
3426 | { | |
3427 | return (struct intel_device_info *)&dev_priv->info; | |
3428 | } | |
3429 | ||
79e53945 | 3430 | /* modesetting */ |
f817586c | 3431 | extern void intel_modeset_init_hw(struct drm_device *dev); |
b079bd17 | 3432 | extern int intel_modeset_init(struct drm_device *dev); |
79e53945 | 3433 | extern void intel_modeset_cleanup(struct drm_device *dev); |
1ebaa0b9 | 3434 | extern int intel_connector_register(struct drm_connector *); |
c191eca1 | 3435 | extern void intel_connector_unregister(struct drm_connector *); |
6315b5d3 TU |
3436 | extern int intel_modeset_vga_set_state(struct drm_i915_private *dev_priv, |
3437 | bool state); | |
043e9bda | 3438 | extern void intel_display_resume(struct drm_device *dev); |
29b74b7f TU |
3439 | extern void i915_redisable_vga(struct drm_i915_private *dev_priv); |
3440 | extern void i915_redisable_vga_power_on(struct drm_i915_private *dev_priv); | |
91d14251 | 3441 | extern bool ironlake_set_drps(struct drm_i915_private *dev_priv, u8 val); |
c39055b0 | 3442 | extern void intel_init_pch_refclk(struct drm_i915_private *dev_priv); |
9fcee2f7 | 3443 | extern int intel_set_rps(struct drm_i915_private *dev_priv, u8 val); |
11a85d6a | 3444 | extern bool intel_set_memory_cxsr(struct drm_i915_private *dev_priv, |
5209b1f4 | 3445 | bool enable); |
3bad0781 | 3446 | |
c0c7babc BW |
3447 | int i915_reg_read_ioctl(struct drm_device *dev, void *data, |
3448 | struct drm_file *file); | |
575155a9 | 3449 | |
6ef3d427 | 3450 | /* overlay */ |
c033666a CW |
3451 | extern struct intel_overlay_error_state * |
3452 | intel_overlay_capture_error_state(struct drm_i915_private *dev_priv); | |
edc3d884 MK |
3453 | extern void intel_overlay_print_error_state(struct drm_i915_error_state_buf *e, |
3454 | struct intel_overlay_error_state *error); | |
c4a1d9e4 | 3455 | |
c033666a CW |
3456 | extern struct intel_display_error_state * |
3457 | intel_display_capture_error_state(struct drm_i915_private *dev_priv); | |
edc3d884 | 3458 | extern void intel_display_print_error_state(struct drm_i915_error_state_buf *e, |
c4a1d9e4 | 3459 | struct intel_display_error_state *error); |
6ef3d427 | 3460 | |
151a49d0 | 3461 | int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val); |
e76019a8 | 3462 | int sandybridge_pcode_write_timeout(struct drm_i915_private *dev_priv, u32 mbox, |
006bb4cc ID |
3463 | u32 val, int fast_timeout_us, |
3464 | int slow_timeout_ms); | |
e76019a8 | 3465 | #define sandybridge_pcode_write(dev_priv, mbox, val) \ |
006bb4cc | 3466 | sandybridge_pcode_write_timeout(dev_priv, mbox, val, 500, 0) |
e76019a8 | 3467 | |
a0b8a1fe ID |
3468 | int skl_pcode_request(struct drm_i915_private *dev_priv, u32 mbox, u32 request, |
3469 | u32 reply_mask, u32 reply, int timeout_base_ms); | |
59de0813 JN |
3470 | |
3471 | /* intel_sideband.c */ | |
707b6e3d | 3472 | u32 vlv_punit_read(struct drm_i915_private *dev_priv, u32 addr); |
9fcee2f7 | 3473 | int vlv_punit_write(struct drm_i915_private *dev_priv, u32 addr, u32 val); |
64936258 | 3474 | u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr); |
dfb19ed2 D |
3475 | u32 vlv_iosf_sb_read(struct drm_i915_private *dev_priv, u8 port, u32 reg); |
3476 | void vlv_iosf_sb_write(struct drm_i915_private *dev_priv, u8 port, u32 reg, u32 val); | |
e9f882a3 JN |
3477 | u32 vlv_cck_read(struct drm_i915_private *dev_priv, u32 reg); |
3478 | void vlv_cck_write(struct drm_i915_private *dev_priv, u32 reg, u32 val); | |
3479 | u32 vlv_ccu_read(struct drm_i915_private *dev_priv, u32 reg); | |
3480 | void vlv_ccu_write(struct drm_i915_private *dev_priv, u32 reg, u32 val); | |
f3419158 JB |
3481 | u32 vlv_bunit_read(struct drm_i915_private *dev_priv, u32 reg); |
3482 | void vlv_bunit_write(struct drm_i915_private *dev_priv, u32 reg, u32 val); | |
5e69f97f CML |
3483 | u32 vlv_dpio_read(struct drm_i915_private *dev_priv, enum pipe pipe, int reg); |
3484 | void vlv_dpio_write(struct drm_i915_private *dev_priv, enum pipe pipe, int reg, u32 val); | |
59de0813 JN |
3485 | u32 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg, |
3486 | enum intel_sbi_destination destination); | |
3487 | void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value, | |
3488 | enum intel_sbi_destination destination); | |
e9fe51c6 SK |
3489 | u32 vlv_flisdsi_read(struct drm_i915_private *dev_priv, u32 reg); |
3490 | void vlv_flisdsi_write(struct drm_i915_private *dev_priv, u32 reg, u32 val); | |
0a073b84 | 3491 | |
b7fa22d8 | 3492 | /* intel_dpio_phy.c */ |
0a116ce8 | 3493 | void bxt_port_to_phy_channel(struct drm_i915_private *dev_priv, enum port port, |
ed37892e | 3494 | enum dpio_phy *phy, enum dpio_channel *ch); |
b6e08203 ACO |
3495 | void bxt_ddi_phy_set_signal_level(struct drm_i915_private *dev_priv, |
3496 | enum port port, u32 margin, u32 scale, | |
3497 | u32 enable, u32 deemphasis); | |
47a6bc61 ACO |
3498 | void bxt_ddi_phy_init(struct drm_i915_private *dev_priv, enum dpio_phy phy); |
3499 | void bxt_ddi_phy_uninit(struct drm_i915_private *dev_priv, enum dpio_phy phy); | |
3500 | bool bxt_ddi_phy_is_enabled(struct drm_i915_private *dev_priv, | |
3501 | enum dpio_phy phy); | |
3502 | bool bxt_ddi_phy_verify_state(struct drm_i915_private *dev_priv, | |
3503 | enum dpio_phy phy); | |
5161d058 | 3504 | uint8_t bxt_ddi_phy_calc_lane_lat_optim_mask(uint8_t lane_count); |
47a6bc61 ACO |
3505 | void bxt_ddi_phy_set_lane_optim_mask(struct intel_encoder *encoder, |
3506 | uint8_t lane_lat_optim_mask); | |
3507 | uint8_t bxt_ddi_phy_get_lane_lat_optim_mask(struct intel_encoder *encoder); | |
3508 | ||
b7fa22d8 ACO |
3509 | void chv_set_phy_signal_level(struct intel_encoder *encoder, |
3510 | u32 deemph_reg_value, u32 margin_reg_value, | |
3511 | bool uniq_trans_scale); | |
844b2f9a | 3512 | void chv_data_lane_soft_reset(struct intel_encoder *encoder, |
2e1029c6 | 3513 | const struct intel_crtc_state *crtc_state, |
844b2f9a | 3514 | bool reset); |
2e1029c6 VS |
3515 | void chv_phy_pre_pll_enable(struct intel_encoder *encoder, |
3516 | const struct intel_crtc_state *crtc_state); | |
3517 | void chv_phy_pre_encoder_enable(struct intel_encoder *encoder, | |
3518 | const struct intel_crtc_state *crtc_state); | |
e7d2a717 | 3519 | void chv_phy_release_cl2_override(struct intel_encoder *encoder); |
2e1029c6 VS |
3520 | void chv_phy_post_pll_disable(struct intel_encoder *encoder, |
3521 | const struct intel_crtc_state *old_crtc_state); | |
b7fa22d8 | 3522 | |
53d98725 ACO |
3523 | void vlv_set_phy_signal_level(struct intel_encoder *encoder, |
3524 | u32 demph_reg_value, u32 preemph_reg_value, | |
3525 | u32 uniqtranscale_reg_value, u32 tx3_demph); | |
2e1029c6 VS |
3526 | void vlv_phy_pre_pll_enable(struct intel_encoder *encoder, |
3527 | const struct intel_crtc_state *crtc_state); | |
3528 | void vlv_phy_pre_encoder_enable(struct intel_encoder *encoder, | |
3529 | const struct intel_crtc_state *crtc_state); | |
3530 | void vlv_phy_reset_lanes(struct intel_encoder *encoder, | |
3531 | const struct intel_crtc_state *old_crtc_state); | |
53d98725 | 3532 | |
616bc820 VS |
3533 | int intel_gpu_freq(struct drm_i915_private *dev_priv, int val); |
3534 | int intel_freq_opcode(struct drm_i915_private *dev_priv, int val); | |
36cc8b96 | 3535 | u64 intel_rc6_residency_ns(struct drm_i915_private *dev_priv, |
c5a0ad11 | 3536 | const i915_reg_t reg); |
c8d9a590 | 3537 | |
c84b2705 TU |
3538 | u32 intel_get_cagf(struct drm_i915_private *dev_priv, u32 rpstat1); |
3539 | ||
36cc8b96 TU |
3540 | static inline u64 intel_rc6_residency_us(struct drm_i915_private *dev_priv, |
3541 | const i915_reg_t reg) | |
3542 | { | |
3543 | return DIV_ROUND_UP_ULL(intel_rc6_residency_ns(dev_priv, reg), 1000); | |
3544 | } | |
3545 | ||
0b274481 BW |
3546 | #define I915_READ8(reg) dev_priv->uncore.funcs.mmio_readb(dev_priv, (reg), true) |
3547 | #define I915_WRITE8(reg, val) dev_priv->uncore.funcs.mmio_writeb(dev_priv, (reg), (val), true) | |
3548 | ||
3549 | #define I915_READ16(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), true) | |
3550 | #define I915_WRITE16(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), true) | |
3551 | #define I915_READ16_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), false) | |
3552 | #define I915_WRITE16_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), false) | |
3553 | ||
3554 | #define I915_READ(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), true) | |
3555 | #define I915_WRITE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), true) | |
3556 | #define I915_READ_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), false) | |
3557 | #define I915_WRITE_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), false) | |
3558 | ||
698b3135 CW |
3559 | /* Be very careful with read/write 64-bit values. On 32-bit machines, they |
3560 | * will be implemented using 2 32-bit writes in an arbitrary order with | |
3561 | * an arbitrary delay between them. This can cause the hardware to | |
3562 | * act upon the intermediate value, possibly leading to corruption and | |
b18c1bb4 CW |
3563 | * machine death. For this reason we do not support I915_WRITE64, or |
3564 | * dev_priv->uncore.funcs.mmio_writeq. | |
3565 | * | |
3566 | * When reading a 64-bit value as two 32-bit values, the delay may cause | |
3567 | * the two reads to mismatch, e.g. a timestamp overflowing. Also note that | |
3568 | * occasionally a 64-bit register does not actualy support a full readq | |
3569 | * and must be read using two 32-bit reads. | |
3570 | * | |
3571 | * You have been warned. | |
698b3135 | 3572 | */ |
0b274481 | 3573 | #define I915_READ64(reg) dev_priv->uncore.funcs.mmio_readq(dev_priv, (reg), true) |
cae5852d | 3574 | |
50877445 | 3575 | #define I915_READ64_2x32(lower_reg, upper_reg) ({ \ |
acd29f7b CW |
3576 | u32 upper, lower, old_upper, loop = 0; \ |
3577 | upper = I915_READ(upper_reg); \ | |
ee0a227b | 3578 | do { \ |
acd29f7b | 3579 | old_upper = upper; \ |
ee0a227b | 3580 | lower = I915_READ(lower_reg); \ |
acd29f7b CW |
3581 | upper = I915_READ(upper_reg); \ |
3582 | } while (upper != old_upper && loop++ < 2); \ | |
ee0a227b | 3583 | (u64)upper << 32 | lower; }) |
50877445 | 3584 | |
cae5852d ZN |
3585 | #define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg) |
3586 | #define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg) | |
3587 | ||
75aa3f63 | 3588 | #define __raw_read(x, s) \ |
6e3955a5 | 3589 | static inline uint##x##_t __raw_i915_read##x(const struct drm_i915_private *dev_priv, \ |
f0f59a00 | 3590 | i915_reg_t reg) \ |
75aa3f63 | 3591 | { \ |
f0f59a00 | 3592 | return read##s(dev_priv->regs + i915_mmio_reg_offset(reg)); \ |
75aa3f63 VS |
3593 | } |
3594 | ||
3595 | #define __raw_write(x, s) \ | |
6e3955a5 | 3596 | static inline void __raw_i915_write##x(const struct drm_i915_private *dev_priv, \ |
f0f59a00 | 3597 | i915_reg_t reg, uint##x##_t val) \ |
75aa3f63 | 3598 | { \ |
f0f59a00 | 3599 | write##s(val, dev_priv->regs + i915_mmio_reg_offset(reg)); \ |
75aa3f63 VS |
3600 | } |
3601 | __raw_read(8, b) | |
3602 | __raw_read(16, w) | |
3603 | __raw_read(32, l) | |
3604 | __raw_read(64, q) | |
3605 | ||
3606 | __raw_write(8, b) | |
3607 | __raw_write(16, w) | |
3608 | __raw_write(32, l) | |
3609 | __raw_write(64, q) | |
3610 | ||
3611 | #undef __raw_read | |
3612 | #undef __raw_write | |
3613 | ||
a6111f7b | 3614 | /* These are untraced mmio-accessors that are only valid to be used inside |
aafee2eb | 3615 | * critical sections, such as inside IRQ handlers, where forcewake is explicitly |
a6111f7b | 3616 | * controlled. |
aafee2eb | 3617 | * |
a6111f7b | 3618 | * Think twice, and think again, before using these. |
aafee2eb AH |
3619 | * |
3620 | * As an example, these accessors can possibly be used between: | |
3621 | * | |
3622 | * spin_lock_irq(&dev_priv->uncore.lock); | |
3623 | * intel_uncore_forcewake_get__locked(); | |
3624 | * | |
3625 | * and | |
3626 | * | |
3627 | * intel_uncore_forcewake_put__locked(); | |
3628 | * spin_unlock_irq(&dev_priv->uncore.lock); | |
3629 | * | |
3630 | * | |
3631 | * Note: some registers may not need forcewake held, so | |
3632 | * intel_uncore_forcewake_{get,put} can be omitted, see | |
3633 | * intel_uncore_forcewake_for_reg(). | |
3634 | * | |
3635 | * Certain architectures will die if the same cacheline is concurrently accessed | |
3636 | * by different clients (e.g. on Ivybridge). Access to registers should | |
3637 | * therefore generally be serialised, by either the dev_priv->uncore.lock or | |
3638 | * a more localised lock guarding all access to that bank of registers. | |
a6111f7b | 3639 | */ |
75aa3f63 VS |
3640 | #define I915_READ_FW(reg__) __raw_i915_read32(dev_priv, (reg__)) |
3641 | #define I915_WRITE_FW(reg__, val__) __raw_i915_write32(dev_priv, (reg__), (val__)) | |
76f8421f | 3642 | #define I915_WRITE64_FW(reg__, val__) __raw_i915_write64(dev_priv, (reg__), (val__)) |
a6111f7b CW |
3643 | #define POSTING_READ_FW(reg__) (void)I915_READ_FW(reg__) |
3644 | ||
55bc60db VS |
3645 | /* "Broadcast RGB" property */ |
3646 | #define INTEL_BROADCAST_RGB_AUTO 0 | |
3647 | #define INTEL_BROADCAST_RGB_FULL 1 | |
3648 | #define INTEL_BROADCAST_RGB_LIMITED 2 | |
ba4f01a3 | 3649 | |
920a14b2 | 3650 | static inline i915_reg_t i915_vgacntrl_reg(struct drm_i915_private *dev_priv) |
766aa1c4 | 3651 | { |
920a14b2 | 3652 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) |
766aa1c4 | 3653 | return VLV_VGACNTRL; |
920a14b2 | 3654 | else if (INTEL_GEN(dev_priv) >= 5) |
92e23b99 | 3655 | return CPU_VGACNTRL; |
766aa1c4 VS |
3656 | else |
3657 | return VGACNTRL; | |
3658 | } | |
3659 | ||
df97729f ID |
3660 | static inline unsigned long msecs_to_jiffies_timeout(const unsigned int m) |
3661 | { | |
3662 | unsigned long j = msecs_to_jiffies(m); | |
3663 | ||
3664 | return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1); | |
3665 | } | |
3666 | ||
7bd0e226 DV |
3667 | static inline unsigned long nsecs_to_jiffies_timeout(const u64 n) |
3668 | { | |
b8050148 CW |
3669 | /* nsecs_to_jiffies64() does not guard against overflow */ |
3670 | if (NSEC_PER_SEC % HZ && | |
3671 | div_u64(n, NSEC_PER_SEC) >= MAX_JIFFY_OFFSET / HZ) | |
3672 | return MAX_JIFFY_OFFSET; | |
3673 | ||
7bd0e226 DV |
3674 | return min_t(u64, MAX_JIFFY_OFFSET, nsecs_to_jiffies64(n) + 1); |
3675 | } | |
3676 | ||
df97729f ID |
3677 | static inline unsigned long |
3678 | timespec_to_jiffies_timeout(const struct timespec *value) | |
3679 | { | |
3680 | unsigned long j = timespec_to_jiffies(value); | |
3681 | ||
3682 | return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1); | |
3683 | } | |
3684 | ||
dce56b3c PZ |
3685 | /* |
3686 | * If you need to wait X milliseconds between events A and B, but event B | |
3687 | * doesn't happen exactly after event A, you record the timestamp (jiffies) of | |
3688 | * when event A happened, then just before event B you call this function and | |
3689 | * pass the timestamp as the first argument, and X as the second argument. | |
3690 | */ | |
3691 | static inline void | |
3692 | wait_remaining_ms_from_jiffies(unsigned long timestamp_jiffies, int to_wait_ms) | |
3693 | { | |
ec5e0cfb | 3694 | unsigned long target_jiffies, tmp_jiffies, remaining_jiffies; |
dce56b3c PZ |
3695 | |
3696 | /* | |
3697 | * Don't re-read the value of "jiffies" every time since it may change | |
3698 | * behind our back and break the math. | |
3699 | */ | |
3700 | tmp_jiffies = jiffies; | |
3701 | target_jiffies = timestamp_jiffies + | |
3702 | msecs_to_jiffies_timeout(to_wait_ms); | |
3703 | ||
3704 | if (time_after(target_jiffies, tmp_jiffies)) { | |
ec5e0cfb ID |
3705 | remaining_jiffies = target_jiffies - tmp_jiffies; |
3706 | while (remaining_jiffies) | |
3707 | remaining_jiffies = | |
3708 | schedule_timeout_uninterruptible(remaining_jiffies); | |
dce56b3c PZ |
3709 | } |
3710 | } | |
221fe799 CW |
3711 | |
3712 | static inline bool | |
e61e0f51 | 3713 | __i915_request_irq_complete(const struct i915_request *rq) |
688e6c72 | 3714 | { |
e61e0f51 | 3715 | struct intel_engine_cs *engine = rq->engine; |
754c9fd5 | 3716 | u32 seqno; |
f69a02c9 | 3717 | |
309663ab CW |
3718 | /* Note that the engine may have wrapped around the seqno, and |
3719 | * so our request->global_seqno will be ahead of the hardware, | |
3720 | * even though it completed the request before wrapping. We catch | |
3721 | * this by kicking all the waiters before resetting the seqno | |
3722 | * in hardware, and also signal the fence. | |
3723 | */ | |
e61e0f51 | 3724 | if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &rq->fence.flags)) |
309663ab CW |
3725 | return true; |
3726 | ||
754c9fd5 CW |
3727 | /* The request was dequeued before we were awoken. We check after |
3728 | * inspecting the hw to confirm that this was the same request | |
3729 | * that generated the HWS update. The memory barriers within | |
3730 | * the request execution are sufficient to ensure that a check | |
3731 | * after reading the value from hw matches this request. | |
3732 | */ | |
e61e0f51 | 3733 | seqno = i915_request_global_seqno(rq); |
754c9fd5 CW |
3734 | if (!seqno) |
3735 | return false; | |
3736 | ||
7ec2c73b CW |
3737 | /* Before we do the heavier coherent read of the seqno, |
3738 | * check the value (hopefully) in the CPU cacheline. | |
3739 | */ | |
e61e0f51 | 3740 | if (__i915_request_completed(rq, seqno)) |
7ec2c73b CW |
3741 | return true; |
3742 | ||
688e6c72 CW |
3743 | /* Ensure our read of the seqno is coherent so that we |
3744 | * do not "miss an interrupt" (i.e. if this is the last | |
3745 | * request and the seqno write from the GPU is not visible | |
3746 | * by the time the interrupt fires, we will see that the | |
3747 | * request is incomplete and go back to sleep awaiting | |
3748 | * another interrupt that will never come.) | |
3749 | * | |
3750 | * Strictly, we only need to do this once after an interrupt, | |
3751 | * but it is easier and safer to do it every time the waiter | |
3752 | * is woken. | |
3753 | */ | |
3d5564e9 | 3754 | if (engine->irq_seqno_barrier && |
538b257d | 3755 | test_and_clear_bit(ENGINE_IRQ_BREADCRUMB, &engine->irq_posted)) { |
56299fb7 | 3756 | struct intel_breadcrumbs *b = &engine->breadcrumbs; |
99fe4a5f | 3757 | |
3d5564e9 CW |
3758 | /* The ordering of irq_posted versus applying the barrier |
3759 | * is crucial. The clearing of the current irq_posted must | |
3760 | * be visible before we perform the barrier operation, | |
3761 | * such that if a subsequent interrupt arrives, irq_posted | |
3762 | * is reasserted and our task rewoken (which causes us to | |
3763 | * do another __i915_request_irq_complete() immediately | |
3764 | * and reapply the barrier). Conversely, if the clear | |
3765 | * occurs after the barrier, then an interrupt that arrived | |
3766 | * whilst we waited on the barrier would not trigger a | |
3767 | * barrier on the next pass, and the read may not see the | |
3768 | * seqno update. | |
3769 | */ | |
f69a02c9 | 3770 | engine->irq_seqno_barrier(engine); |
99fe4a5f CW |
3771 | |
3772 | /* If we consume the irq, but we are no longer the bottom-half, | |
3773 | * the real bottom-half may not have serialised their own | |
3774 | * seqno check with the irq-barrier (i.e. may have inspected | |
3775 | * the seqno before we believe it coherent since they see | |
3776 | * irq_posted == false but we are still running). | |
3777 | */ | |
2c33b541 | 3778 | spin_lock_irq(&b->irq_lock); |
61d3dc70 | 3779 | if (b->irq_wait && b->irq_wait->tsk != current) |
99fe4a5f CW |
3780 | /* Note that if the bottom-half is changed as we |
3781 | * are sending the wake-up, the new bottom-half will | |
3782 | * be woken by whomever made the change. We only have | |
3783 | * to worry about when we steal the irq-posted for | |
3784 | * ourself. | |
3785 | */ | |
61d3dc70 | 3786 | wake_up_process(b->irq_wait->tsk); |
2c33b541 | 3787 | spin_unlock_irq(&b->irq_lock); |
99fe4a5f | 3788 | |
e61e0f51 | 3789 | if (__i915_request_completed(rq, seqno)) |
7ec2c73b CW |
3790 | return true; |
3791 | } | |
688e6c72 | 3792 | |
688e6c72 CW |
3793 | return false; |
3794 | } | |
3795 | ||
0b1de5d5 CW |
3796 | void i915_memcpy_init_early(struct drm_i915_private *dev_priv); |
3797 | bool i915_memcpy_from_wc(void *dst, const void *src, unsigned long len); | |
3798 | ||
c4d3ae68 CW |
3799 | /* The movntdqa instructions used for memcpy-from-wc require 16-byte alignment, |
3800 | * as well as SSE4.1 support. i915_memcpy_from_wc() will report if it cannot | |
3801 | * perform the operation. To check beforehand, pass in the parameters to | |
3802 | * to i915_can_memcpy_from_wc() - since we only care about the low 4 bits, | |
3803 | * you only need to pass in the minor offsets, page-aligned pointers are | |
3804 | * always valid. | |
3805 | * | |
3806 | * For just checking for SSE4.1, in the foreknowledge that the future use | |
3807 | * will be correctly aligned, just use i915_has_memcpy_from_wc(). | |
3808 | */ | |
3809 | #define i915_can_memcpy_from_wc(dst, src, len) \ | |
3810 | i915_memcpy_from_wc((void *)((unsigned long)(dst) | (unsigned long)(src) | (len)), NULL, 0) | |
3811 | ||
3812 | #define i915_has_memcpy_from_wc() \ | |
3813 | i915_memcpy_from_wc(NULL, NULL, 0) | |
3814 | ||
c58305af CW |
3815 | /* i915_mm.c */ |
3816 | int remap_io_mapping(struct vm_area_struct *vma, | |
3817 | unsigned long addr, unsigned long pfn, unsigned long size, | |
3818 | struct io_mapping *iomap); | |
3819 | ||
767a983a CW |
3820 | static inline int intel_hws_csb_write_index(struct drm_i915_private *i915) |
3821 | { | |
3822 | if (INTEL_GEN(i915) >= 10) | |
3823 | return CNL_HWS_CSB_WRITE_INDEX; | |
3824 | else | |
3825 | return I915_HWS_CSB_WRITE_INDEX; | |
3826 | } | |
3827 | ||
1da177e4 | 3828 | #endif |