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1da177e4 LT |
1 | /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*- |
2 | */ | |
0d6aa60b | 3 | /* |
bc54fd1a | 4 | * |
1da177e4 LT |
5 | * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. |
6 | * All Rights Reserved. | |
bc54fd1a DA |
7 | * |
8 | * Permission is hereby granted, free of charge, to any person obtaining a | |
9 | * copy of this software and associated documentation files (the | |
10 | * "Software"), to deal in the Software without restriction, including | |
11 | * without limitation the rights to use, copy, modify, merge, publish, | |
12 | * distribute, sub license, and/or sell copies of the Software, and to | |
13 | * permit persons to whom the Software is furnished to do so, subject to | |
14 | * the following conditions: | |
15 | * | |
16 | * The above copyright notice and this permission notice (including the | |
17 | * next paragraph) shall be included in all copies or substantial portions | |
18 | * of the Software. | |
19 | * | |
20 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS | |
21 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
22 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. | |
23 | * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR | |
24 | * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, | |
25 | * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE | |
26 | * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. | |
27 | * | |
0d6aa60b | 28 | */ |
1da177e4 LT |
29 | |
30 | #ifndef _I915_DRV_H_ | |
31 | #define _I915_DRV_H_ | |
32 | ||
585fb111 | 33 | #include "i915_reg.h" |
79e53945 | 34 | #include "intel_bios.h" |
8187a2b7 | 35 | #include "intel_ringbuffer.h" |
0839ccb8 | 36 | #include <linux/io-mapping.h> |
f899fc64 | 37 | #include <linux/i2c.h> |
0ade6386 | 38 | #include <drm/intel-gtt.h> |
585fb111 | 39 | |
1da177e4 LT |
40 | /* General customization: |
41 | */ | |
42 | ||
43 | #define DRIVER_AUTHOR "Tungsten Graphics, Inc." | |
44 | ||
45 | #define DRIVER_NAME "i915" | |
46 | #define DRIVER_DESC "Intel Graphics" | |
673a394b | 47 | #define DRIVER_DATE "20080730" |
1da177e4 | 48 | |
317c35d1 JB |
49 | enum pipe { |
50 | PIPE_A = 0, | |
51 | PIPE_B, | |
9db4a9c7 JB |
52 | PIPE_C, |
53 | I915_MAX_PIPES | |
317c35d1 | 54 | }; |
9db4a9c7 | 55 | #define pipe_name(p) ((p) + 'A') |
317c35d1 | 56 | |
80824003 JB |
57 | enum plane { |
58 | PLANE_A = 0, | |
59 | PLANE_B, | |
9db4a9c7 | 60 | PLANE_C, |
80824003 | 61 | }; |
9db4a9c7 | 62 | #define plane_name(p) ((p) + 'A') |
52440211 | 63 | |
62fdfeaf EA |
64 | #define I915_GEM_GPU_DOMAINS (~(I915_GEM_DOMAIN_CPU | I915_GEM_DOMAIN_GTT)) |
65 | ||
9db4a9c7 JB |
66 | #define for_each_pipe(p) for ((p) = 0; (p) < dev_priv->num_pipe; (p)++) |
67 | ||
1da177e4 LT |
68 | /* Interface history: |
69 | * | |
70 | * 1.1: Original. | |
0d6aa60b DA |
71 | * 1.2: Add Power Management |
72 | * 1.3: Add vblank support | |
de227f5f | 73 | * 1.4: Fix cmdbuffer path, add heap destroy |
702880f2 | 74 | * 1.5: Add vblank pipe configuration |
2228ed67 MD |
75 | * 1.6: - New ioctl for scheduling buffer swaps on vertical blank |
76 | * - Support vertical blank on secondary display pipe | |
1da177e4 LT |
77 | */ |
78 | #define DRIVER_MAJOR 1 | |
2228ed67 | 79 | #define DRIVER_MINOR 6 |
1da177e4 LT |
80 | #define DRIVER_PATCHLEVEL 0 |
81 | ||
673a394b | 82 | #define WATCH_COHERENCY 0 |
23bc5982 | 83 | #define WATCH_LISTS 0 |
673a394b | 84 | |
71acb5eb DA |
85 | #define I915_GEM_PHYS_CURSOR_0 1 |
86 | #define I915_GEM_PHYS_CURSOR_1 2 | |
87 | #define I915_GEM_PHYS_OVERLAY_REGS 3 | |
88 | #define I915_MAX_PHYS_OBJECT (I915_GEM_PHYS_OVERLAY_REGS) | |
89 | ||
90 | struct drm_i915_gem_phys_object { | |
91 | int id; | |
92 | struct page **page_list; | |
93 | drm_dma_handle_t *handle; | |
05394f39 | 94 | struct drm_i915_gem_object *cur_obj; |
71acb5eb DA |
95 | }; |
96 | ||
1da177e4 LT |
97 | struct mem_block { |
98 | struct mem_block *next; | |
99 | struct mem_block *prev; | |
100 | int start; | |
101 | int size; | |
6c340eac | 102 | struct drm_file *file_priv; /* NULL: free, -1: heap, other: real files */ |
1da177e4 LT |
103 | }; |
104 | ||
0a3e67a4 JB |
105 | struct opregion_header; |
106 | struct opregion_acpi; | |
107 | struct opregion_swsci; | |
108 | struct opregion_asle; | |
109 | ||
8ee1c3db MG |
110 | struct intel_opregion { |
111 | struct opregion_header *header; | |
112 | struct opregion_acpi *acpi; | |
113 | struct opregion_swsci *swsci; | |
114 | struct opregion_asle *asle; | |
44834a67 | 115 | void *vbt; |
01fe9dbd | 116 | u32 __iomem *lid_state; |
8ee1c3db | 117 | }; |
44834a67 | 118 | #define OPREGION_SIZE (8*1024) |
8ee1c3db | 119 | |
6ef3d427 CW |
120 | struct intel_overlay; |
121 | struct intel_overlay_error_state; | |
122 | ||
7c1c2871 DA |
123 | struct drm_i915_master_private { |
124 | drm_local_map_t *sarea; | |
125 | struct _drm_i915_sarea *sarea_priv; | |
126 | }; | |
de151cf6 JB |
127 | #define I915_FENCE_REG_NONE -1 |
128 | ||
129 | struct drm_i915_fence_reg { | |
007cc8ac | 130 | struct list_head lru_list; |
caea7476 | 131 | struct drm_i915_gem_object *obj; |
d9e86c0e | 132 | uint32_t setup_seqno; |
de151cf6 | 133 | }; |
7c1c2871 | 134 | |
9b9d172d | 135 | struct sdvo_device_mapping { |
e957d772 | 136 | u8 initialized; |
9b9d172d | 137 | u8 dvo_port; |
138 | u8 slave_addr; | |
139 | u8 dvo_wiring; | |
e957d772 CW |
140 | u8 i2c_pin; |
141 | u8 i2c_speed; | |
b1083333 | 142 | u8 ddc_pin; |
9b9d172d | 143 | }; |
144 | ||
c4a1d9e4 CW |
145 | struct intel_display_error_state; |
146 | ||
63eeaf38 JB |
147 | struct drm_i915_error_state { |
148 | u32 eir; | |
149 | u32 pgtbl_er; | |
9db4a9c7 | 150 | u32 pipestat[I915_MAX_PIPES]; |
63eeaf38 JB |
151 | u32 ipeir; |
152 | u32 ipehr; | |
153 | u32 instdone; | |
154 | u32 acthd; | |
1d8f38f4 CW |
155 | u32 error; /* gen6+ */ |
156 | u32 bcs_acthd; /* gen6+ blt engine */ | |
157 | u32 bcs_ipehr; | |
158 | u32 bcs_ipeir; | |
159 | u32 bcs_instdone; | |
160 | u32 bcs_seqno; | |
add354dd CW |
161 | u32 vcs_acthd; /* gen6+ bsd engine */ |
162 | u32 vcs_ipehr; | |
163 | u32 vcs_ipeir; | |
164 | u32 vcs_instdone; | |
165 | u32 vcs_seqno; | |
63eeaf38 JB |
166 | u32 instpm; |
167 | u32 instps; | |
168 | u32 instdone1; | |
169 | u32 seqno; | |
9df30794 | 170 | u64 bbaddr; |
748ebc60 | 171 | u64 fence[16]; |
63eeaf38 | 172 | struct timeval time; |
9df30794 CW |
173 | struct drm_i915_error_object { |
174 | int page_count; | |
175 | u32 gtt_offset; | |
176 | u32 *pages[0]; | |
e2f973d5 | 177 | } *ringbuffer[I915_NUM_RINGS], *batchbuffer[I915_NUM_RINGS]; |
9df30794 | 178 | struct drm_i915_error_buffer { |
a779e5ab | 179 | u32 size; |
9df30794 CW |
180 | u32 name; |
181 | u32 seqno; | |
182 | u32 gtt_offset; | |
183 | u32 read_domains; | |
184 | u32 write_domain; | |
a779e5ab | 185 | s32 fence_reg:5; |
9df30794 CW |
186 | s32 pinned:2; |
187 | u32 tiling:2; | |
188 | u32 dirty:1; | |
189 | u32 purgeable:1; | |
e5c65260 | 190 | u32 ring:4; |
a779e5ab | 191 | u32 agp_type:1; |
c724e8a9 CW |
192 | } *active_bo, *pinned_bo; |
193 | u32 active_bo_count, pinned_bo_count; | |
6ef3d427 | 194 | struct intel_overlay_error_state *overlay; |
c4a1d9e4 | 195 | struct intel_display_error_state *display; |
63eeaf38 JB |
196 | }; |
197 | ||
e70236a8 JB |
198 | struct drm_i915_display_funcs { |
199 | void (*dpms)(struct drm_crtc *crtc, int mode); | |
ee5382ae | 200 | bool (*fbc_enabled)(struct drm_device *dev); |
e70236a8 JB |
201 | void (*enable_fbc)(struct drm_crtc *crtc, unsigned long interval); |
202 | void (*disable_fbc)(struct drm_device *dev); | |
203 | int (*get_display_clock_speed)(struct drm_device *dev); | |
204 | int (*get_fifo_size)(struct drm_device *dev, int plane); | |
d210246a | 205 | void (*update_wm)(struct drm_device *dev); |
e70236a8 JB |
206 | /* clock updates for mode set */ |
207 | /* cursor updates */ | |
208 | /* render clock increase/decrease */ | |
209 | /* display clock increase/decrease */ | |
210 | /* pll clock increase/decrease */ | |
211 | /* clock gating init */ | |
212 | }; | |
213 | ||
cfdf1fa2 | 214 | struct intel_device_info { |
c96c3a8c | 215 | u8 gen; |
cfdf1fa2 | 216 | u8 is_mobile : 1; |
5ce8ba7c | 217 | u8 is_i85x : 1; |
cfdf1fa2 | 218 | u8 is_i915g : 1; |
cfdf1fa2 | 219 | u8 is_i945gm : 1; |
cfdf1fa2 KH |
220 | u8 is_g33 : 1; |
221 | u8 need_gfx_hws : 1; | |
222 | u8 is_g4x : 1; | |
223 | u8 is_pineview : 1; | |
534843da CW |
224 | u8 is_broadwater : 1; |
225 | u8 is_crestline : 1; | |
cfdf1fa2 | 226 | u8 has_fbc : 1; |
cfdf1fa2 KH |
227 | u8 has_pipe_cxsr : 1; |
228 | u8 has_hotplug : 1; | |
b295d1b6 | 229 | u8 cursor_needs_physical : 1; |
31578148 CW |
230 | u8 has_overlay : 1; |
231 | u8 overlay_needs_physical : 1; | |
a6c45cf0 | 232 | u8 supports_tv : 1; |
92f49d9c | 233 | u8 has_bsd_ring : 1; |
549f7365 | 234 | u8 has_blt_ring : 1; |
cfdf1fa2 KH |
235 | }; |
236 | ||
b5e50c3f | 237 | enum no_fbc_reason { |
bed4a673 | 238 | FBC_NO_OUTPUT, /* no outputs enabled to compress */ |
b5e50c3f JB |
239 | FBC_STOLEN_TOO_SMALL, /* not enough space to hold compressed buffers */ |
240 | FBC_UNSUPPORTED_MODE, /* interlace or doublescanned mode */ | |
241 | FBC_MODE_TOO_LARGE, /* mode too large for compression */ | |
242 | FBC_BAD_PLANE, /* fbc not supported on plane */ | |
243 | FBC_NOT_TILED, /* buffer not tiled */ | |
9c928d16 | 244 | FBC_MULTIPLE_PIPES, /* more than one pipe active */ |
b5e50c3f JB |
245 | }; |
246 | ||
3bad0781 ZW |
247 | enum intel_pch { |
248 | PCH_IBX, /* Ibexpeak PCH */ | |
249 | PCH_CPT, /* Cougarpoint PCH */ | |
250 | }; | |
251 | ||
b690e96c JB |
252 | #define QUIRK_PIPEA_FORCE (1<<0) |
253 | ||
8be48d92 | 254 | struct intel_fbdev; |
38651674 | 255 | |
1da177e4 | 256 | typedef struct drm_i915_private { |
673a394b EA |
257 | struct drm_device *dev; |
258 | ||
cfdf1fa2 KH |
259 | const struct intel_device_info *info; |
260 | ||
ac5c4e76 | 261 | int has_gem; |
72bfa19c | 262 | int relative_constants_mode; |
ac5c4e76 | 263 | |
3043c60c | 264 | void __iomem *regs; |
1da177e4 | 265 | |
f899fc64 CW |
266 | struct intel_gmbus { |
267 | struct i2c_adapter adapter; | |
e957d772 CW |
268 | struct i2c_adapter *force_bit; |
269 | u32 reg0; | |
f899fc64 CW |
270 | } *gmbus; |
271 | ||
ec2a4c3f | 272 | struct pci_dev *bridge_dev; |
1ec14ad3 | 273 | struct intel_ring_buffer ring[I915_NUM_RINGS]; |
6f392d54 | 274 | uint32_t next_seqno; |
1da177e4 | 275 | |
9c8da5eb | 276 | drm_dma_handle_t *status_page_dmah; |
0a3e67a4 | 277 | uint32_t counter; |
dc7a9319 | 278 | drm_local_map_t hws_map; |
05394f39 CW |
279 | struct drm_i915_gem_object *pwrctx; |
280 | struct drm_i915_gem_object *renderctx; | |
1da177e4 | 281 | |
d7658989 JB |
282 | struct resource mch_res; |
283 | ||
a6b54f3f | 284 | unsigned int cpp; |
1da177e4 LT |
285 | int back_offset; |
286 | int front_offset; | |
287 | int current_page; | |
288 | int page_flipping; | |
1da177e4 | 289 | |
1da177e4 | 290 | atomic_t irq_received; |
1ec14ad3 CW |
291 | |
292 | /* protects the irq masks */ | |
293 | spinlock_t irq_lock; | |
ed4cb414 | 294 | /** Cached value of IMR to avoid reads in updating the bitfield */ |
7c463586 | 295 | u32 pipestat[2]; |
1ec14ad3 CW |
296 | u32 irq_mask; |
297 | u32 gt_irq_mask; | |
298 | u32 pch_irq_mask; | |
1da177e4 | 299 | |
5ca58282 JB |
300 | u32 hotplug_supported_mask; |
301 | struct work_struct hotplug_work; | |
302 | ||
1da177e4 LT |
303 | int tex_lru_log_granularity; |
304 | int allow_batchbuffer; | |
305 | struct mem_block *agp_heap; | |
0d6aa60b | 306 | unsigned int sr01, adpa, ppcr, dvob, dvoc, lvds; |
702880f2 | 307 | int vblank_pipe; |
a3524f1b | 308 | int num_pipe; |
a6b54f3f | 309 | |
f65d9421 | 310 | /* For hangcheck timer */ |
576ae4b8 | 311 | #define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */ |
f65d9421 BG |
312 | struct timer_list hangcheck_timer; |
313 | int hangcheck_count; | |
314 | uint32_t last_acthd; | |
cbb465e7 CW |
315 | uint32_t last_instdone; |
316 | uint32_t last_instdone1; | |
f65d9421 | 317 | |
80824003 JB |
318 | unsigned long cfb_size; |
319 | unsigned long cfb_pitch; | |
bed4a673 | 320 | unsigned long cfb_offset; |
80824003 JB |
321 | int cfb_fence; |
322 | int cfb_plane; | |
bed4a673 | 323 | int cfb_y; |
80824003 | 324 | |
8ee1c3db MG |
325 | struct intel_opregion opregion; |
326 | ||
02e792fb DV |
327 | /* overlay */ |
328 | struct intel_overlay *overlay; | |
329 | ||
79e53945 | 330 | /* LVDS info */ |
a9573556 | 331 | int backlight_level; /* restore backlight to this value */ |
47356eb6 | 332 | bool backlight_enabled; |
79e53945 | 333 | struct drm_display_mode *panel_fixed_mode; |
88631706 ML |
334 | struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */ |
335 | struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */ | |
79e53945 JB |
336 | |
337 | /* Feature bits from the VBIOS */ | |
95281e35 HE |
338 | unsigned int int_tv_support:1; |
339 | unsigned int lvds_dither:1; | |
340 | unsigned int lvds_vbt:1; | |
341 | unsigned int int_crt_support:1; | |
43565a06 KH |
342 | unsigned int lvds_use_ssc:1; |
343 | int lvds_ssc_freq; | |
5ceb0f9b | 344 | struct { |
9f0e7ff4 JB |
345 | int rate; |
346 | int lanes; | |
347 | int preemphasis; | |
348 | int vswing; | |
349 | ||
350 | bool initialized; | |
351 | bool support; | |
352 | int bpp; | |
353 | struct edp_power_seq pps; | |
5ceb0f9b | 354 | } edp; |
89667383 | 355 | bool no_aux_handshake; |
79e53945 | 356 | |
c1c7af60 JB |
357 | struct notifier_block lid_notifier; |
358 | ||
f899fc64 | 359 | int crt_ddc_pin; |
de151cf6 JB |
360 | struct drm_i915_fence_reg fence_regs[16]; /* assume 965 */ |
361 | int fence_reg_start; /* 4 if userland hasn't ioctl'd us yet */ | |
362 | int num_fence_regs; /* 8 on pre-965, 16 otherwise */ | |
363 | ||
95534263 | 364 | unsigned int fsb_freq, mem_freq, is_ddr3; |
7662c8bd | 365 | |
63eeaf38 JB |
366 | spinlock_t error_lock; |
367 | struct drm_i915_error_state *first_error; | |
8a905236 | 368 | struct work_struct error_work; |
30dbf0c0 | 369 | struct completion error_completion; |
9c9fe1f8 | 370 | struct workqueue_struct *wq; |
63eeaf38 | 371 | |
e70236a8 JB |
372 | /* Display functions */ |
373 | struct drm_i915_display_funcs display; | |
374 | ||
3bad0781 ZW |
375 | /* PCH chipset type */ |
376 | enum intel_pch pch_type; | |
377 | ||
b690e96c JB |
378 | unsigned long quirks; |
379 | ||
ba8bbcf6 | 380 | /* Register state */ |
c9354c85 | 381 | bool modeset_on_lid; |
ba8bbcf6 JB |
382 | u8 saveLBB; |
383 | u32 saveDSPACNTR; | |
384 | u32 saveDSPBCNTR; | |
e948e994 | 385 | u32 saveDSPARB; |
968b503e | 386 | u32 saveHWS; |
ba8bbcf6 JB |
387 | u32 savePIPEACONF; |
388 | u32 savePIPEBCONF; | |
389 | u32 savePIPEASRC; | |
390 | u32 savePIPEBSRC; | |
391 | u32 saveFPA0; | |
392 | u32 saveFPA1; | |
393 | u32 saveDPLL_A; | |
394 | u32 saveDPLL_A_MD; | |
395 | u32 saveHTOTAL_A; | |
396 | u32 saveHBLANK_A; | |
397 | u32 saveHSYNC_A; | |
398 | u32 saveVTOTAL_A; | |
399 | u32 saveVBLANK_A; | |
400 | u32 saveVSYNC_A; | |
401 | u32 saveBCLRPAT_A; | |
5586c8bc | 402 | u32 saveTRANSACONF; |
42048781 ZW |
403 | u32 saveTRANS_HTOTAL_A; |
404 | u32 saveTRANS_HBLANK_A; | |
405 | u32 saveTRANS_HSYNC_A; | |
406 | u32 saveTRANS_VTOTAL_A; | |
407 | u32 saveTRANS_VBLANK_A; | |
408 | u32 saveTRANS_VSYNC_A; | |
0da3ea12 | 409 | u32 savePIPEASTAT; |
ba8bbcf6 JB |
410 | u32 saveDSPASTRIDE; |
411 | u32 saveDSPASIZE; | |
412 | u32 saveDSPAPOS; | |
585fb111 | 413 | u32 saveDSPAADDR; |
ba8bbcf6 JB |
414 | u32 saveDSPASURF; |
415 | u32 saveDSPATILEOFF; | |
416 | u32 savePFIT_PGM_RATIOS; | |
0eb96d6e | 417 | u32 saveBLC_HIST_CTL; |
ba8bbcf6 JB |
418 | u32 saveBLC_PWM_CTL; |
419 | u32 saveBLC_PWM_CTL2; | |
42048781 ZW |
420 | u32 saveBLC_CPU_PWM_CTL; |
421 | u32 saveBLC_CPU_PWM_CTL2; | |
ba8bbcf6 JB |
422 | u32 saveFPB0; |
423 | u32 saveFPB1; | |
424 | u32 saveDPLL_B; | |
425 | u32 saveDPLL_B_MD; | |
426 | u32 saveHTOTAL_B; | |
427 | u32 saveHBLANK_B; | |
428 | u32 saveHSYNC_B; | |
429 | u32 saveVTOTAL_B; | |
430 | u32 saveVBLANK_B; | |
431 | u32 saveVSYNC_B; | |
432 | u32 saveBCLRPAT_B; | |
5586c8bc | 433 | u32 saveTRANSBCONF; |
42048781 ZW |
434 | u32 saveTRANS_HTOTAL_B; |
435 | u32 saveTRANS_HBLANK_B; | |
436 | u32 saveTRANS_HSYNC_B; | |
437 | u32 saveTRANS_VTOTAL_B; | |
438 | u32 saveTRANS_VBLANK_B; | |
439 | u32 saveTRANS_VSYNC_B; | |
0da3ea12 | 440 | u32 savePIPEBSTAT; |
ba8bbcf6 JB |
441 | u32 saveDSPBSTRIDE; |
442 | u32 saveDSPBSIZE; | |
443 | u32 saveDSPBPOS; | |
585fb111 | 444 | u32 saveDSPBADDR; |
ba8bbcf6 JB |
445 | u32 saveDSPBSURF; |
446 | u32 saveDSPBTILEOFF; | |
585fb111 JB |
447 | u32 saveVGA0; |
448 | u32 saveVGA1; | |
449 | u32 saveVGA_PD; | |
ba8bbcf6 JB |
450 | u32 saveVGACNTRL; |
451 | u32 saveADPA; | |
452 | u32 saveLVDS; | |
585fb111 JB |
453 | u32 savePP_ON_DELAYS; |
454 | u32 savePP_OFF_DELAYS; | |
ba8bbcf6 JB |
455 | u32 saveDVOA; |
456 | u32 saveDVOB; | |
457 | u32 saveDVOC; | |
458 | u32 savePP_ON; | |
459 | u32 savePP_OFF; | |
460 | u32 savePP_CONTROL; | |
585fb111 | 461 | u32 savePP_DIVISOR; |
ba8bbcf6 JB |
462 | u32 savePFIT_CONTROL; |
463 | u32 save_palette_a[256]; | |
464 | u32 save_palette_b[256]; | |
06027f91 | 465 | u32 saveDPFC_CB_BASE; |
ba8bbcf6 JB |
466 | u32 saveFBC_CFB_BASE; |
467 | u32 saveFBC_LL_BASE; | |
468 | u32 saveFBC_CONTROL; | |
469 | u32 saveFBC_CONTROL2; | |
0da3ea12 JB |
470 | u32 saveIER; |
471 | u32 saveIIR; | |
472 | u32 saveIMR; | |
42048781 ZW |
473 | u32 saveDEIER; |
474 | u32 saveDEIMR; | |
475 | u32 saveGTIER; | |
476 | u32 saveGTIMR; | |
477 | u32 saveFDI_RXA_IMR; | |
478 | u32 saveFDI_RXB_IMR; | |
1f84e550 | 479 | u32 saveCACHE_MODE_0; |
1f84e550 | 480 | u32 saveMI_ARB_STATE; |
ba8bbcf6 JB |
481 | u32 saveSWF0[16]; |
482 | u32 saveSWF1[16]; | |
483 | u32 saveSWF2[3]; | |
484 | u8 saveMSR; | |
485 | u8 saveSR[8]; | |
123f794f | 486 | u8 saveGR[25]; |
ba8bbcf6 | 487 | u8 saveAR_INDEX; |
a59e122a | 488 | u8 saveAR[21]; |
ba8bbcf6 | 489 | u8 saveDACMASK; |
a59e122a | 490 | u8 saveCR[37]; |
79f11c19 | 491 | uint64_t saveFENCE[16]; |
1fd1c624 EA |
492 | u32 saveCURACNTR; |
493 | u32 saveCURAPOS; | |
494 | u32 saveCURABASE; | |
495 | u32 saveCURBCNTR; | |
496 | u32 saveCURBPOS; | |
497 | u32 saveCURBBASE; | |
498 | u32 saveCURSIZE; | |
a4fc5ed6 KP |
499 | u32 saveDP_B; |
500 | u32 saveDP_C; | |
501 | u32 saveDP_D; | |
502 | u32 savePIPEA_GMCH_DATA_M; | |
503 | u32 savePIPEB_GMCH_DATA_M; | |
504 | u32 savePIPEA_GMCH_DATA_N; | |
505 | u32 savePIPEB_GMCH_DATA_N; | |
506 | u32 savePIPEA_DP_LINK_M; | |
507 | u32 savePIPEB_DP_LINK_M; | |
508 | u32 savePIPEA_DP_LINK_N; | |
509 | u32 savePIPEB_DP_LINK_N; | |
42048781 ZW |
510 | u32 saveFDI_RXA_CTL; |
511 | u32 saveFDI_TXA_CTL; | |
512 | u32 saveFDI_RXB_CTL; | |
513 | u32 saveFDI_TXB_CTL; | |
514 | u32 savePFA_CTL_1; | |
515 | u32 savePFB_CTL_1; | |
516 | u32 savePFA_WIN_SZ; | |
517 | u32 savePFB_WIN_SZ; | |
518 | u32 savePFA_WIN_POS; | |
519 | u32 savePFB_WIN_POS; | |
5586c8bc ZW |
520 | u32 savePCH_DREF_CONTROL; |
521 | u32 saveDISP_ARB_CTL; | |
522 | u32 savePIPEA_DATA_M1; | |
523 | u32 savePIPEA_DATA_N1; | |
524 | u32 savePIPEA_LINK_M1; | |
525 | u32 savePIPEA_LINK_N1; | |
526 | u32 savePIPEB_DATA_M1; | |
527 | u32 savePIPEB_DATA_N1; | |
528 | u32 savePIPEB_LINK_M1; | |
529 | u32 savePIPEB_LINK_N1; | |
b5b72e89 | 530 | u32 saveMCHBAR_RENDER_STANDBY; |
673a394b EA |
531 | |
532 | struct { | |
19966754 | 533 | /** Bridge to intel-gtt-ko */ |
c64f7ba5 | 534 | const struct intel_gtt *gtt; |
19966754 | 535 | /** Memory allocator for GTT stolen memory */ |
fe669bf8 | 536 | struct drm_mm stolen; |
19966754 | 537 | /** Memory allocator for GTT */ |
673a394b | 538 | struct drm_mm gtt_space; |
93a37f20 DV |
539 | /** List of all objects in gtt_space. Used to restore gtt |
540 | * mappings on resume */ | |
541 | struct list_head gtt_list; | |
bee4a186 CW |
542 | |
543 | /** Usable portion of the GTT for GEM */ | |
544 | unsigned long gtt_start; | |
a6e0aa42 | 545 | unsigned long gtt_mappable_end; |
bee4a186 | 546 | unsigned long gtt_end; |
673a394b | 547 | |
0839ccb8 | 548 | struct io_mapping *gtt_mapping; |
ab657db1 | 549 | int gtt_mtrr; |
0839ccb8 | 550 | |
17250b71 | 551 | struct shrinker inactive_shrinker; |
31169714 | 552 | |
69dc4987 CW |
553 | /** |
554 | * List of objects currently involved in rendering. | |
555 | * | |
556 | * Includes buffers having the contents of their GPU caches | |
557 | * flushed, not necessarily primitives. last_rendering_seqno | |
558 | * represents when the rendering involved will be completed. | |
559 | * | |
560 | * A reference is held on the buffer while on this list. | |
561 | */ | |
562 | struct list_head active_list; | |
563 | ||
673a394b EA |
564 | /** |
565 | * List of objects which are not in the ringbuffer but which | |
566 | * still have a write_domain which needs to be flushed before | |
567 | * unbinding. | |
568 | * | |
ce44b0ea EA |
569 | * last_rendering_seqno is 0 while an object is in this list. |
570 | * | |
673a394b EA |
571 | * A reference is held on the buffer while on this list. |
572 | */ | |
573 | struct list_head flushing_list; | |
574 | ||
575 | /** | |
576 | * LRU list of objects which are not in the ringbuffer and | |
577 | * are ready to unbind, but are still in the GTT. | |
578 | * | |
ce44b0ea EA |
579 | * last_rendering_seqno is 0 while an object is in this list. |
580 | * | |
673a394b EA |
581 | * A reference is not held on the buffer while on this list, |
582 | * as merely being GTT-bound shouldn't prevent its being | |
583 | * freed, and we'll pull it off the list in the free path. | |
584 | */ | |
585 | struct list_head inactive_list; | |
586 | ||
f13d3f73 CW |
587 | /** |
588 | * LRU list of objects which are not in the ringbuffer but | |
589 | * are still pinned in the GTT. | |
590 | */ | |
591 | struct list_head pinned_list; | |
592 | ||
a09ba7fa EA |
593 | /** LRU list of objects with fence regs on them. */ |
594 | struct list_head fence_list; | |
595 | ||
be72615b CW |
596 | /** |
597 | * List of objects currently pending being freed. | |
598 | * | |
599 | * These objects are no longer in use, but due to a signal | |
600 | * we were prevented from freeing them at the appointed time. | |
601 | */ | |
602 | struct list_head deferred_free_list; | |
603 | ||
673a394b EA |
604 | /** |
605 | * We leave the user IRQ off as much as possible, | |
606 | * but this means that requests will finish and never | |
607 | * be retired once the system goes idle. Set a timer to | |
608 | * fire periodically while the ring is running. When it | |
609 | * fires, go retire requests. | |
610 | */ | |
611 | struct delayed_work retire_work; | |
612 | ||
ce453d81 CW |
613 | /** |
614 | * Are we in a non-interruptible section of code like | |
615 | * modesetting? | |
616 | */ | |
617 | bool interruptible; | |
618 | ||
673a394b EA |
619 | /** |
620 | * Flag if the X Server, and thus DRM, is not currently in | |
621 | * control of the device. | |
622 | * | |
623 | * This is set between LeaveVT and EnterVT. It needs to be | |
624 | * replaced with a semaphore. It also needs to be | |
625 | * transitioned away from for kernel modesetting. | |
626 | */ | |
627 | int suspended; | |
628 | ||
629 | /** | |
630 | * Flag if the hardware appears to be wedged. | |
631 | * | |
632 | * This is set when attempts to idle the device timeout. | |
25985edc | 633 | * It prevents command submission from occurring and makes |
673a394b EA |
634 | * every pending request fail |
635 | */ | |
ba1234d1 | 636 | atomic_t wedged; |
673a394b EA |
637 | |
638 | /** Bit 6 swizzling required for X tiling */ | |
639 | uint32_t bit_6_swizzle_x; | |
640 | /** Bit 6 swizzling required for Y tiling */ | |
641 | uint32_t bit_6_swizzle_y; | |
71acb5eb DA |
642 | |
643 | /* storage for physical objects */ | |
644 | struct drm_i915_gem_phys_object *phys_objs[I915_MAX_PHYS_OBJECT]; | |
9220434a | 645 | |
73aa808f | 646 | /* accounting, useful for userland debugging */ |
73aa808f | 647 | size_t gtt_total; |
6299f992 CW |
648 | size_t mappable_gtt_total; |
649 | size_t object_memory; | |
73aa808f | 650 | u32 object_count; |
673a394b | 651 | } mm; |
9b9d172d | 652 | struct sdvo_device_mapping sdvo_mappings[2]; |
a3e17eb8 ZY |
653 | /* indicate whether the LVDS_BORDER should be enabled or not */ |
654 | unsigned int lvds_border_bits; | |
1d8e1c75 CW |
655 | /* Panel fitter placement and size for Ironlake+ */ |
656 | u32 pch_pf_pos, pch_pf_size; | |
5d613501 | 657 | int panel_t3, panel_t12; |
652c393a | 658 | |
6b95a207 KH |
659 | struct drm_crtc *plane_to_crtc_mapping[2]; |
660 | struct drm_crtc *pipe_to_crtc_mapping[2]; | |
661 | wait_queue_head_t pending_flip_queue; | |
1afe3e9d | 662 | bool flip_pending_is_done; |
6b95a207 | 663 | |
652c393a JB |
664 | /* Reclocking support */ |
665 | bool render_reclock_avail; | |
666 | bool lvds_downclock_avail; | |
18f9ed12 ZY |
667 | /* indicates the reduced downclock for LVDS*/ |
668 | int lvds_downclock; | |
652c393a JB |
669 | struct work_struct idle_work; |
670 | struct timer_list idle_timer; | |
671 | bool busy; | |
672 | u16 orig_clock; | |
6363ee6f ZY |
673 | int child_dev_num; |
674 | struct child_device_config *child_dev; | |
a2565377 | 675 | struct drm_connector *int_lvds_connector; |
f97108d1 | 676 | |
c4804411 | 677 | bool mchbar_need_disable; |
f97108d1 JB |
678 | |
679 | u8 cur_delay; | |
680 | u8 min_delay; | |
681 | u8 max_delay; | |
7648fa99 JB |
682 | u8 fmax; |
683 | u8 fstart; | |
684 | ||
05394f39 CW |
685 | u64 last_count1; |
686 | unsigned long last_time1; | |
687 | u64 last_count2; | |
688 | struct timespec last_time2; | |
689 | unsigned long gfx_power; | |
690 | int c_m; | |
691 | int r_t; | |
692 | u8 corr; | |
7648fa99 | 693 | spinlock_t *mchdev_lock; |
b5e50c3f JB |
694 | |
695 | enum no_fbc_reason no_fbc_reason; | |
38651674 | 696 | |
20bf377e JB |
697 | struct drm_mm_node *compressed_fb; |
698 | struct drm_mm_node *compressed_llb; | |
34dc4d44 | 699 | |
ae681d96 CW |
700 | unsigned long last_gpu_reset; |
701 | ||
8be48d92 DA |
702 | /* list of fbdev register on this device */ |
703 | struct intel_fbdev *fbdev; | |
e953fd7b CW |
704 | |
705 | struct drm_property *broadcast_rgb_property; | |
1da177e4 LT |
706 | } drm_i915_private_t; |
707 | ||
673a394b | 708 | struct drm_i915_gem_object { |
c397b908 | 709 | struct drm_gem_object base; |
673a394b EA |
710 | |
711 | /** Current space allocated to this object in the GTT, if any. */ | |
712 | struct drm_mm_node *gtt_space; | |
93a37f20 | 713 | struct list_head gtt_list; |
673a394b EA |
714 | |
715 | /** This object's place on the active/flushing/inactive lists */ | |
69dc4987 CW |
716 | struct list_head ring_list; |
717 | struct list_head mm_list; | |
99fcb766 DV |
718 | /** This object's place on GPU write list */ |
719 | struct list_head gpu_write_list; | |
432e58ed CW |
720 | /** This object's place in the batchbuffer or on the eviction list */ |
721 | struct list_head exec_list; | |
673a394b EA |
722 | |
723 | /** | |
724 | * This is set if the object is on the active or flushing lists | |
725 | * (has pending rendering), and is not set if it's on inactive (ready | |
726 | * to be unbound). | |
727 | */ | |
778c3544 | 728 | unsigned int active : 1; |
673a394b EA |
729 | |
730 | /** | |
731 | * This is set if the object has been written to since last bound | |
732 | * to the GTT | |
733 | */ | |
778c3544 DV |
734 | unsigned int dirty : 1; |
735 | ||
87ca9c8a CW |
736 | /** |
737 | * This is set if the object has been written to since the last | |
738 | * GPU flush. | |
739 | */ | |
740 | unsigned int pending_gpu_write : 1; | |
741 | ||
778c3544 DV |
742 | /** |
743 | * Fence register bits (if any) for this object. Will be set | |
744 | * as needed when mapped into the GTT. | |
745 | * Protected by dev->struct_mutex. | |
746 | * | |
747 | * Size: 4 bits for 16 fences + sign (for FENCE_REG_NONE) | |
748 | */ | |
11824e8c | 749 | signed int fence_reg : 5; |
778c3544 | 750 | |
778c3544 DV |
751 | /** |
752 | * Advice: are the backing pages purgeable? | |
753 | */ | |
754 | unsigned int madv : 2; | |
755 | ||
778c3544 DV |
756 | /** |
757 | * Current tiling mode for the object. | |
758 | */ | |
759 | unsigned int tiling_mode : 2; | |
d9e86c0e | 760 | unsigned int tiling_changed : 1; |
778c3544 DV |
761 | |
762 | /** How many users have pinned this object in GTT space. The following | |
763 | * users can each hold at most one reference: pwrite/pread, pin_ioctl | |
764 | * (via user_pin_count), execbuffer (objects are not allowed multiple | |
765 | * times for the same batchbuffer), and the framebuffer code. When | |
766 | * switching/pageflipping, the framebuffer code has at most two buffers | |
767 | * pinned per crtc. | |
768 | * | |
769 | * In the worst case this is 1 + 1 + 1 + 2*2 = 7. That would fit into 3 | |
770 | * bits with absolutely no headroom. So use 4 bits. */ | |
11824e8c | 771 | unsigned int pin_count : 4; |
778c3544 | 772 | #define DRM_I915_GEM_OBJECT_MAX_PIN_COUNT 0xf |
673a394b | 773 | |
75e9e915 DV |
774 | /** |
775 | * Is the object at the current location in the gtt mappable and | |
776 | * fenceable? Used to avoid costly recalculations. | |
777 | */ | |
778 | unsigned int map_and_fenceable : 1; | |
779 | ||
fb7d516a DV |
780 | /** |
781 | * Whether the current gtt mapping needs to be mappable (and isn't just | |
782 | * mappable by accident). Track pin and fault separate for a more | |
783 | * accurate mappable working set. | |
784 | */ | |
785 | unsigned int fault_mappable : 1; | |
786 | unsigned int pin_mappable : 1; | |
787 | ||
caea7476 CW |
788 | /* |
789 | * Is the GPU currently using a fence to access this buffer, | |
790 | */ | |
791 | unsigned int pending_fenced_gpu_access:1; | |
792 | unsigned int fenced_gpu_access:1; | |
793 | ||
856fa198 | 794 | struct page **pages; |
673a394b | 795 | |
185cbcb3 DV |
796 | /** |
797 | * DMAR support | |
798 | */ | |
799 | struct scatterlist *sg_list; | |
800 | int num_sg; | |
801 | ||
67731b87 CW |
802 | /** |
803 | * Used for performing relocations during execbuffer insertion. | |
804 | */ | |
805 | struct hlist_node exec_node; | |
806 | unsigned long exec_handle; | |
6fe4f140 | 807 | struct drm_i915_gem_exec_object2 *exec_entry; |
67731b87 | 808 | |
673a394b EA |
809 | /** |
810 | * Current offset of the object in GTT space. | |
811 | * | |
812 | * This is the same as gtt_space->start | |
813 | */ | |
814 | uint32_t gtt_offset; | |
e67b8ce1 | 815 | |
673a394b EA |
816 | /** Breadcrumb of last rendering to the buffer. */ |
817 | uint32_t last_rendering_seqno; | |
caea7476 CW |
818 | struct intel_ring_buffer *ring; |
819 | ||
820 | /** Breadcrumb of last fenced GPU access to the buffer. */ | |
821 | uint32_t last_fenced_seqno; | |
822 | struct intel_ring_buffer *last_fenced_ring; | |
673a394b | 823 | |
778c3544 | 824 | /** Current tiling stride for the object, if it's tiled. */ |
de151cf6 | 825 | uint32_t stride; |
673a394b | 826 | |
280b713b | 827 | /** Record of address bit 17 of each page at last unbind. */ |
d312ec25 | 828 | unsigned long *bit_17; |
280b713b | 829 | |
ba1eb1d8 KP |
830 | /** AGP mapping type (AGP_USER_MEMORY or AGP_USER_CACHED_MEMORY */ |
831 | uint32_t agp_type; | |
832 | ||
673a394b | 833 | /** |
e47c68e9 EA |
834 | * If present, while GEM_DOMAIN_CPU is in the read domain this array |
835 | * flags which individual pages are valid. | |
673a394b EA |
836 | */ |
837 | uint8_t *page_cpu_valid; | |
79e53945 JB |
838 | |
839 | /** User space pin count and filp owning the pin */ | |
840 | uint32_t user_pin_count; | |
841 | struct drm_file *pin_filp; | |
71acb5eb DA |
842 | |
843 | /** for phy allocated objects */ | |
844 | struct drm_i915_gem_phys_object *phys_obj; | |
b70d11da | 845 | |
6b95a207 KH |
846 | /** |
847 | * Number of crtcs where this object is currently the fb, but | |
848 | * will be page flipped away on the next vblank. When it | |
849 | * reaches 0, dev_priv->pending_flip_queue will be woken up. | |
850 | */ | |
851 | atomic_t pending_flip; | |
673a394b EA |
852 | }; |
853 | ||
62b8b215 | 854 | #define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base) |
23010e43 | 855 | |
673a394b EA |
856 | /** |
857 | * Request queue structure. | |
858 | * | |
859 | * The request queue allows us to note sequence numbers that have been emitted | |
860 | * and may be associated with active buffers to be retired. | |
861 | * | |
862 | * By keeping this list, we can avoid having to do questionable | |
863 | * sequence-number comparisons on buffer last_rendering_seqnos, and associate | |
864 | * an emission time with seqnos for tracking how far ahead of the GPU we are. | |
865 | */ | |
866 | struct drm_i915_gem_request { | |
852835f3 ZN |
867 | /** On Which ring this request was generated */ |
868 | struct intel_ring_buffer *ring; | |
869 | ||
673a394b EA |
870 | /** GEM sequence number associated with this request. */ |
871 | uint32_t seqno; | |
872 | ||
873 | /** Time at which this request was emitted, in jiffies. */ | |
874 | unsigned long emitted_jiffies; | |
875 | ||
b962442e | 876 | /** global list entry for this request */ |
673a394b | 877 | struct list_head list; |
b962442e | 878 | |
f787a5f5 | 879 | struct drm_i915_file_private *file_priv; |
b962442e EA |
880 | /** file_priv list entry for this request */ |
881 | struct list_head client_list; | |
673a394b EA |
882 | }; |
883 | ||
884 | struct drm_i915_file_private { | |
885 | struct { | |
1c25595f | 886 | struct spinlock lock; |
b962442e | 887 | struct list_head request_list; |
673a394b EA |
888 | } mm; |
889 | }; | |
890 | ||
79e53945 JB |
891 | enum intel_chip_family { |
892 | CHIP_I8XX = 0x01, | |
893 | CHIP_I9XX = 0x02, | |
894 | CHIP_I915 = 0x04, | |
895 | CHIP_I965 = 0x08, | |
896 | }; | |
897 | ||
cae5852d ZN |
898 | #define INTEL_INFO(dev) (((struct drm_i915_private *) (dev)->dev_private)->info) |
899 | ||
900 | #define IS_I830(dev) ((dev)->pci_device == 0x3577) | |
901 | #define IS_845G(dev) ((dev)->pci_device == 0x2562) | |
902 | #define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x) | |
903 | #define IS_I865G(dev) ((dev)->pci_device == 0x2572) | |
904 | #define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g) | |
905 | #define IS_I915GM(dev) ((dev)->pci_device == 0x2592) | |
906 | #define IS_I945G(dev) ((dev)->pci_device == 0x2772) | |
907 | #define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm) | |
908 | #define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater) | |
909 | #define IS_CRESTLINE(dev) (INTEL_INFO(dev)->is_crestline) | |
910 | #define IS_GM45(dev) ((dev)->pci_device == 0x2A42) | |
911 | #define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x) | |
912 | #define IS_PINEVIEW_G(dev) ((dev)->pci_device == 0xa001) | |
913 | #define IS_PINEVIEW_M(dev) ((dev)->pci_device == 0xa011) | |
914 | #define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview) | |
915 | #define IS_G33(dev) (INTEL_INFO(dev)->is_g33) | |
916 | #define IS_IRONLAKE_D(dev) ((dev)->pci_device == 0x0042) | |
917 | #define IS_IRONLAKE_M(dev) ((dev)->pci_device == 0x0046) | |
918 | #define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile) | |
919 | ||
920 | #define IS_GEN2(dev) (INTEL_INFO(dev)->gen == 2) | |
921 | #define IS_GEN3(dev) (INTEL_INFO(dev)->gen == 3) | |
922 | #define IS_GEN4(dev) (INTEL_INFO(dev)->gen == 4) | |
923 | #define IS_GEN5(dev) (INTEL_INFO(dev)->gen == 5) | |
924 | #define IS_GEN6(dev) (INTEL_INFO(dev)->gen == 6) | |
925 | ||
926 | #define HAS_BSD(dev) (INTEL_INFO(dev)->has_bsd_ring) | |
927 | #define HAS_BLT(dev) (INTEL_INFO(dev)->has_blt_ring) | |
928 | #define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws) | |
929 | ||
05394f39 | 930 | #define HAS_OVERLAY(dev) (INTEL_INFO(dev)->has_overlay) |
cae5852d ZN |
931 | #define OVERLAY_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->overlay_needs_physical) |
932 | ||
933 | /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte | |
934 | * rows, which changed the alignment requirements and fence programming. | |
935 | */ | |
936 | #define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \ | |
937 | IS_I915GM(dev))) | |
938 | #define SUPPORTS_DIGITAL_OUTPUTS(dev) (!IS_GEN2(dev) && !IS_PINEVIEW(dev)) | |
939 | #define SUPPORTS_INTEGRATED_HDMI(dev) (IS_G4X(dev) || IS_GEN5(dev)) | |
940 | #define SUPPORTS_INTEGRATED_DP(dev) (IS_G4X(dev) || IS_GEN5(dev)) | |
941 | #define SUPPORTS_EDP(dev) (IS_IRONLAKE_M(dev)) | |
942 | #define SUPPORTS_TV(dev) (INTEL_INFO(dev)->supports_tv) | |
943 | #define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug) | |
944 | /* dsparb controlled by hw only */ | |
945 | #define DSPARB_HWCONTROL(dev) (IS_G4X(dev) || IS_IRONLAKE(dev)) | |
946 | ||
947 | #define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2) | |
948 | #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr) | |
949 | #define I915_HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc) | |
cae5852d ZN |
950 | |
951 | #define HAS_PCH_SPLIT(dev) (IS_GEN5(dev) || IS_GEN6(dev)) | |
952 | #define HAS_PIPE_CONTROL(dev) (IS_GEN5(dev) || IS_GEN6(dev)) | |
953 | ||
954 | #define INTEL_PCH_TYPE(dev) (((struct drm_i915_private *)(dev)->dev_private)->pch_type) | |
955 | #define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT) | |
956 | #define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX) | |
957 | ||
05394f39 CW |
958 | #include "i915_trace.h" |
959 | ||
c153f45f | 960 | extern struct drm_ioctl_desc i915_ioctls[]; |
b3a83639 | 961 | extern int i915_max_ioctl; |
79e53945 | 962 | extern unsigned int i915_fbpercrtc; |
fca87409 | 963 | extern int i915_panel_ignore_lid; |
652c393a | 964 | extern unsigned int i915_powersave; |
a1656b90 | 965 | extern unsigned int i915_semaphores; |
33814341 | 966 | extern unsigned int i915_lvds_downclock; |
a7615030 | 967 | extern unsigned int i915_panel_use_ssc; |
5a1e5b6c | 968 | extern int i915_vbt_sdvo_panel_type; |
ac668088 | 969 | extern unsigned int i915_enable_rc6; |
b3a83639 | 970 | |
6a9ee8af DA |
971 | extern int i915_suspend(struct drm_device *dev, pm_message_t state); |
972 | extern int i915_resume(struct drm_device *dev); | |
1341d655 BG |
973 | extern void i915_save_display(struct drm_device *dev); |
974 | extern void i915_restore_display(struct drm_device *dev); | |
7c1c2871 DA |
975 | extern int i915_master_create(struct drm_device *dev, struct drm_master *master); |
976 | extern void i915_master_destroy(struct drm_device *dev, struct drm_master *master); | |
977 | ||
1da177e4 | 978 | /* i915_dma.c */ |
84b1fd10 | 979 | extern void i915_kernel_lost_context(struct drm_device * dev); |
22eae947 | 980 | extern int i915_driver_load(struct drm_device *, unsigned long flags); |
ba8bbcf6 | 981 | extern int i915_driver_unload(struct drm_device *); |
673a394b | 982 | extern int i915_driver_open(struct drm_device *dev, struct drm_file *file_priv); |
84b1fd10 | 983 | extern void i915_driver_lastclose(struct drm_device * dev); |
6c340eac EA |
984 | extern void i915_driver_preclose(struct drm_device *dev, |
985 | struct drm_file *file_priv); | |
673a394b EA |
986 | extern void i915_driver_postclose(struct drm_device *dev, |
987 | struct drm_file *file_priv); | |
84b1fd10 | 988 | extern int i915_driver_device_is_agp(struct drm_device * dev); |
0d6aa60b DA |
989 | extern long i915_compat_ioctl(struct file *filp, unsigned int cmd, |
990 | unsigned long arg); | |
673a394b | 991 | extern int i915_emit_box(struct drm_device *dev, |
c4e7a414 CW |
992 | struct drm_clip_rect *box, |
993 | int DR1, int DR4); | |
f803aa55 | 994 | extern int i915_reset(struct drm_device *dev, u8 flags); |
7648fa99 JB |
995 | extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv); |
996 | extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv); | |
997 | extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv); | |
998 | extern void i915_update_gfx_val(struct drm_i915_private *dev_priv); | |
999 | ||
af6061af | 1000 | |
1da177e4 | 1001 | /* i915_irq.c */ |
f65d9421 | 1002 | void i915_hangcheck_elapsed(unsigned long data); |
527f9e90 | 1003 | void i915_handle_error(struct drm_device *dev, bool wedged); |
c153f45f EA |
1004 | extern int i915_irq_emit(struct drm_device *dev, void *data, |
1005 | struct drm_file *file_priv); | |
1006 | extern int i915_irq_wait(struct drm_device *dev, void *data, | |
1007 | struct drm_file *file_priv); | |
1da177e4 LT |
1008 | |
1009 | extern irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS); | |
84b1fd10 | 1010 | extern void i915_driver_irq_preinstall(struct drm_device * dev); |
0a3e67a4 | 1011 | extern int i915_driver_irq_postinstall(struct drm_device *dev); |
84b1fd10 | 1012 | extern void i915_driver_irq_uninstall(struct drm_device * dev); |
c153f45f EA |
1013 | extern int i915_vblank_pipe_set(struct drm_device *dev, void *data, |
1014 | struct drm_file *file_priv); | |
1015 | extern int i915_vblank_pipe_get(struct drm_device *dev, void *data, | |
1016 | struct drm_file *file_priv); | |
0a3e67a4 JB |
1017 | extern int i915_enable_vblank(struct drm_device *dev, int crtc); |
1018 | extern void i915_disable_vblank(struct drm_device *dev, int crtc); | |
1019 | extern u32 i915_get_vblank_counter(struct drm_device *dev, int crtc); | |
9880b7a5 | 1020 | extern u32 gm45_get_vblank_counter(struct drm_device *dev, int crtc); |
c153f45f EA |
1021 | extern int i915_vblank_swap(struct drm_device *dev, void *data, |
1022 | struct drm_file *file_priv); | |
1da177e4 | 1023 | |
7c463586 KP |
1024 | void |
1025 | i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask); | |
1026 | ||
1027 | void | |
1028 | i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask); | |
1029 | ||
01c66889 | 1030 | void intel_enable_asle (struct drm_device *dev); |
0af7e4df MK |
1031 | int i915_get_vblank_timestamp(struct drm_device *dev, int crtc, |
1032 | int *max_error, | |
1033 | struct timeval *vblank_time, | |
1034 | unsigned flags); | |
1035 | ||
1036 | int i915_get_crtc_scanoutpos(struct drm_device *dev, int pipe, | |
1037 | int *vpos, int *hpos); | |
01c66889 | 1038 | |
3bd3c932 CW |
1039 | #ifdef CONFIG_DEBUG_FS |
1040 | extern void i915_destroy_error_state(struct drm_device *dev); | |
1041 | #else | |
1042 | #define i915_destroy_error_state(x) | |
1043 | #endif | |
1044 | ||
7c463586 | 1045 | |
1da177e4 | 1046 | /* i915_mem.c */ |
c153f45f EA |
1047 | extern int i915_mem_alloc(struct drm_device *dev, void *data, |
1048 | struct drm_file *file_priv); | |
1049 | extern int i915_mem_free(struct drm_device *dev, void *data, | |
1050 | struct drm_file *file_priv); | |
1051 | extern int i915_mem_init_heap(struct drm_device *dev, void *data, | |
1052 | struct drm_file *file_priv); | |
1053 | extern int i915_mem_destroy_heap(struct drm_device *dev, void *data, | |
1054 | struct drm_file *file_priv); | |
1da177e4 | 1055 | extern void i915_mem_takedown(struct mem_block **heap); |
84b1fd10 | 1056 | extern void i915_mem_release(struct drm_device * dev, |
6c340eac | 1057 | struct drm_file *file_priv, struct mem_block *heap); |
673a394b EA |
1058 | /* i915_gem.c */ |
1059 | int i915_gem_init_ioctl(struct drm_device *dev, void *data, | |
1060 | struct drm_file *file_priv); | |
1061 | int i915_gem_create_ioctl(struct drm_device *dev, void *data, | |
1062 | struct drm_file *file_priv); | |
1063 | int i915_gem_pread_ioctl(struct drm_device *dev, void *data, | |
1064 | struct drm_file *file_priv); | |
1065 | int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data, | |
1066 | struct drm_file *file_priv); | |
1067 | int i915_gem_mmap_ioctl(struct drm_device *dev, void *data, | |
1068 | struct drm_file *file_priv); | |
de151cf6 JB |
1069 | int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data, |
1070 | struct drm_file *file_priv); | |
673a394b EA |
1071 | int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data, |
1072 | struct drm_file *file_priv); | |
1073 | int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data, | |
1074 | struct drm_file *file_priv); | |
1075 | int i915_gem_execbuffer(struct drm_device *dev, void *data, | |
1076 | struct drm_file *file_priv); | |
76446cac JB |
1077 | int i915_gem_execbuffer2(struct drm_device *dev, void *data, |
1078 | struct drm_file *file_priv); | |
673a394b EA |
1079 | int i915_gem_pin_ioctl(struct drm_device *dev, void *data, |
1080 | struct drm_file *file_priv); | |
1081 | int i915_gem_unpin_ioctl(struct drm_device *dev, void *data, | |
1082 | struct drm_file *file_priv); | |
1083 | int i915_gem_busy_ioctl(struct drm_device *dev, void *data, | |
1084 | struct drm_file *file_priv); | |
1085 | int i915_gem_throttle_ioctl(struct drm_device *dev, void *data, | |
1086 | struct drm_file *file_priv); | |
3ef94daa CW |
1087 | int i915_gem_madvise_ioctl(struct drm_device *dev, void *data, |
1088 | struct drm_file *file_priv); | |
673a394b EA |
1089 | int i915_gem_entervt_ioctl(struct drm_device *dev, void *data, |
1090 | struct drm_file *file_priv); | |
1091 | int i915_gem_leavevt_ioctl(struct drm_device *dev, void *data, | |
1092 | struct drm_file *file_priv); | |
1093 | int i915_gem_set_tiling(struct drm_device *dev, void *data, | |
1094 | struct drm_file *file_priv); | |
1095 | int i915_gem_get_tiling(struct drm_device *dev, void *data, | |
1096 | struct drm_file *file_priv); | |
5a125c3c EA |
1097 | int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data, |
1098 | struct drm_file *file_priv); | |
673a394b | 1099 | void i915_gem_load(struct drm_device *dev); |
673a394b | 1100 | int i915_gem_init_object(struct drm_gem_object *obj); |
db53a302 | 1101 | int __must_check i915_gem_flush_ring(struct intel_ring_buffer *ring, |
88241785 CW |
1102 | uint32_t invalidate_domains, |
1103 | uint32_t flush_domains); | |
05394f39 CW |
1104 | struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev, |
1105 | size_t size); | |
673a394b | 1106 | void i915_gem_free_object(struct drm_gem_object *obj); |
2021746e CW |
1107 | int __must_check i915_gem_object_pin(struct drm_i915_gem_object *obj, |
1108 | uint32_t alignment, | |
1109 | bool map_and_fenceable); | |
05394f39 | 1110 | void i915_gem_object_unpin(struct drm_i915_gem_object *obj); |
2021746e | 1111 | int __must_check i915_gem_object_unbind(struct drm_i915_gem_object *obj); |
05394f39 | 1112 | void i915_gem_release_mmap(struct drm_i915_gem_object *obj); |
673a394b | 1113 | void i915_gem_lastclose(struct drm_device *dev); |
f787a5f5 | 1114 | |
54cf91dc | 1115 | int __must_check i915_mutex_lock_interruptible(struct drm_device *dev); |
ce453d81 | 1116 | int __must_check i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj); |
54cf91dc | 1117 | void i915_gem_object_move_to_active(struct drm_i915_gem_object *obj, |
1ec14ad3 CW |
1118 | struct intel_ring_buffer *ring, |
1119 | u32 seqno); | |
54cf91dc | 1120 | |
ff72145b DA |
1121 | int i915_gem_dumb_create(struct drm_file *file_priv, |
1122 | struct drm_device *dev, | |
1123 | struct drm_mode_create_dumb *args); | |
1124 | int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev, | |
1125 | uint32_t handle, uint64_t *offset); | |
1126 | int i915_gem_dumb_destroy(struct drm_file *file_priv, struct drm_device *dev, | |
1127 | uint32_t handle); | |
f787a5f5 CW |
1128 | /** |
1129 | * Returns true if seq1 is later than seq2. | |
1130 | */ | |
1131 | static inline bool | |
1132 | i915_seqno_passed(uint32_t seq1, uint32_t seq2) | |
1133 | { | |
1134 | return (int32_t)(seq1 - seq2) >= 0; | |
1135 | } | |
1136 | ||
54cf91dc | 1137 | static inline u32 |
db53a302 | 1138 | i915_gem_next_request_seqno(struct intel_ring_buffer *ring) |
54cf91dc | 1139 | { |
db53a302 | 1140 | drm_i915_private_t *dev_priv = ring->dev->dev_private; |
54cf91dc CW |
1141 | return ring->outstanding_lazy_request = dev_priv->next_seqno; |
1142 | } | |
1143 | ||
d9e86c0e | 1144 | int __must_check i915_gem_object_get_fence(struct drm_i915_gem_object *obj, |
ce453d81 | 1145 | struct intel_ring_buffer *pipelined); |
d9e86c0e | 1146 | int __must_check i915_gem_object_put_fence(struct drm_i915_gem_object *obj); |
2021746e | 1147 | |
b09a1fec | 1148 | void i915_gem_retire_requests(struct drm_device *dev); |
069efc1d | 1149 | void i915_gem_reset(struct drm_device *dev); |
05394f39 | 1150 | void i915_gem_clflush_object(struct drm_i915_gem_object *obj); |
2021746e CW |
1151 | int __must_check i915_gem_object_set_domain(struct drm_i915_gem_object *obj, |
1152 | uint32_t read_domains, | |
1153 | uint32_t write_domain); | |
ce453d81 | 1154 | int __must_check i915_gem_object_flush_gpu(struct drm_i915_gem_object *obj); |
2021746e | 1155 | int __must_check i915_gem_init_ringbuffer(struct drm_device *dev); |
79e53945 | 1156 | void i915_gem_cleanup_ringbuffer(struct drm_device *dev); |
2021746e CW |
1157 | void i915_gem_do_init(struct drm_device *dev, |
1158 | unsigned long start, | |
1159 | unsigned long mappable_end, | |
1160 | unsigned long end); | |
1161 | int __must_check i915_gpu_idle(struct drm_device *dev); | |
1162 | int __must_check i915_gem_idle(struct drm_device *dev); | |
db53a302 CW |
1163 | int __must_check i915_add_request(struct intel_ring_buffer *ring, |
1164 | struct drm_file *file, | |
1165 | struct drm_i915_gem_request *request); | |
1166 | int __must_check i915_wait_request(struct intel_ring_buffer *ring, | |
ce453d81 | 1167 | uint32_t seqno); |
de151cf6 | 1168 | int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf); |
2021746e CW |
1169 | int __must_check |
1170 | i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, | |
1171 | bool write); | |
1172 | int __must_check | |
1173 | i915_gem_object_set_to_display_plane(struct drm_i915_gem_object *obj, | |
1174 | struct intel_ring_buffer *pipelined); | |
71acb5eb | 1175 | int i915_gem_attach_phys_object(struct drm_device *dev, |
05394f39 | 1176 | struct drm_i915_gem_object *obj, |
6eeefaf3 CW |
1177 | int id, |
1178 | int align); | |
71acb5eb | 1179 | void i915_gem_detach_phys_object(struct drm_device *dev, |
05394f39 | 1180 | struct drm_i915_gem_object *obj); |
71acb5eb | 1181 | void i915_gem_free_all_phys_object(struct drm_device *dev); |
05394f39 | 1182 | void i915_gem_release(struct drm_device *dev, struct drm_file *file); |
673a394b | 1183 | |
467cffba CW |
1184 | uint32_t |
1185 | i915_gem_get_unfenced_gtt_alignment(struct drm_i915_gem_object *obj); | |
1186 | ||
76aaf220 DV |
1187 | /* i915_gem_gtt.c */ |
1188 | void i915_gem_restore_gtt_mappings(struct drm_device *dev); | |
2021746e | 1189 | int __must_check i915_gem_gtt_bind_object(struct drm_i915_gem_object *obj); |
05394f39 | 1190 | void i915_gem_gtt_unbind_object(struct drm_i915_gem_object *obj); |
76aaf220 | 1191 | |
b47eb4a2 | 1192 | /* i915_gem_evict.c */ |
2021746e CW |
1193 | int __must_check i915_gem_evict_something(struct drm_device *dev, int min_size, |
1194 | unsigned alignment, bool mappable); | |
1195 | int __must_check i915_gem_evict_everything(struct drm_device *dev, | |
1196 | bool purgeable_only); | |
1197 | int __must_check i915_gem_evict_inactive(struct drm_device *dev, | |
1198 | bool purgeable_only); | |
b47eb4a2 | 1199 | |
673a394b EA |
1200 | /* i915_gem_tiling.c */ |
1201 | void i915_gem_detect_bit_6_swizzle(struct drm_device *dev); | |
05394f39 CW |
1202 | void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj); |
1203 | void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj); | |
673a394b EA |
1204 | |
1205 | /* i915_gem_debug.c */ | |
05394f39 | 1206 | void i915_gem_dump_object(struct drm_i915_gem_object *obj, int len, |
673a394b | 1207 | const char *where, uint32_t mark); |
23bc5982 CW |
1208 | #if WATCH_LISTS |
1209 | int i915_verify_lists(struct drm_device *dev); | |
673a394b | 1210 | #else |
23bc5982 | 1211 | #define i915_verify_lists(dev) 0 |
673a394b | 1212 | #endif |
05394f39 CW |
1213 | void i915_gem_object_check_coherency(struct drm_i915_gem_object *obj, |
1214 | int handle); | |
1215 | void i915_gem_dump_object(struct drm_i915_gem_object *obj, int len, | |
673a394b | 1216 | const char *where, uint32_t mark); |
1da177e4 | 1217 | |
2017263e | 1218 | /* i915_debugfs.c */ |
27c202ad BG |
1219 | int i915_debugfs_init(struct drm_minor *minor); |
1220 | void i915_debugfs_cleanup(struct drm_minor *minor); | |
2017263e | 1221 | |
317c35d1 JB |
1222 | /* i915_suspend.c */ |
1223 | extern int i915_save_state(struct drm_device *dev); | |
1224 | extern int i915_restore_state(struct drm_device *dev); | |
0a3e67a4 JB |
1225 | |
1226 | /* i915_suspend.c */ | |
1227 | extern int i915_save_state(struct drm_device *dev); | |
1228 | extern int i915_restore_state(struct drm_device *dev); | |
317c35d1 | 1229 | |
f899fc64 CW |
1230 | /* intel_i2c.c */ |
1231 | extern int intel_setup_gmbus(struct drm_device *dev); | |
1232 | extern void intel_teardown_gmbus(struct drm_device *dev); | |
e957d772 CW |
1233 | extern void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed); |
1234 | extern void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit); | |
b8232e90 CW |
1235 | extern inline bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter) |
1236 | { | |
1237 | return container_of(adapter, struct intel_gmbus, adapter)->force_bit; | |
1238 | } | |
f899fc64 CW |
1239 | extern void intel_i2c_reset(struct drm_device *dev); |
1240 | ||
3b617967 | 1241 | /* intel_opregion.c */ |
44834a67 CW |
1242 | extern int intel_opregion_setup(struct drm_device *dev); |
1243 | #ifdef CONFIG_ACPI | |
1244 | extern void intel_opregion_init(struct drm_device *dev); | |
1245 | extern void intel_opregion_fini(struct drm_device *dev); | |
3b617967 CW |
1246 | extern void intel_opregion_asle_intr(struct drm_device *dev); |
1247 | extern void intel_opregion_gse_intr(struct drm_device *dev); | |
1248 | extern void intel_opregion_enable_asle(struct drm_device *dev); | |
65e082c9 | 1249 | #else |
44834a67 CW |
1250 | static inline void intel_opregion_init(struct drm_device *dev) { return; } |
1251 | static inline void intel_opregion_fini(struct drm_device *dev) { return; } | |
3b617967 CW |
1252 | static inline void intel_opregion_asle_intr(struct drm_device *dev) { return; } |
1253 | static inline void intel_opregion_gse_intr(struct drm_device *dev) { return; } | |
1254 | static inline void intel_opregion_enable_asle(struct drm_device *dev) { return; } | |
65e082c9 | 1255 | #endif |
8ee1c3db | 1256 | |
723bfd70 JB |
1257 | /* intel_acpi.c */ |
1258 | #ifdef CONFIG_ACPI | |
1259 | extern void intel_register_dsm_handler(void); | |
1260 | extern void intel_unregister_dsm_handler(void); | |
1261 | #else | |
1262 | static inline void intel_register_dsm_handler(void) { return; } | |
1263 | static inline void intel_unregister_dsm_handler(void) { return; } | |
1264 | #endif /* CONFIG_ACPI */ | |
1265 | ||
79e53945 JB |
1266 | /* modesetting */ |
1267 | extern void intel_modeset_init(struct drm_device *dev); | |
1268 | extern void intel_modeset_cleanup(struct drm_device *dev); | |
28d52043 | 1269 | extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state); |
80824003 | 1270 | extern void i8xx_disable_fbc(struct drm_device *dev); |
74dff282 | 1271 | extern void g4x_disable_fbc(struct drm_device *dev); |
b52eb4dc | 1272 | extern void ironlake_disable_fbc(struct drm_device *dev); |
ee5382ae AJ |
1273 | extern void intel_disable_fbc(struct drm_device *dev); |
1274 | extern void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval); | |
1275 | extern bool intel_fbc_enabled(struct drm_device *dev); | |
7648fa99 | 1276 | extern bool ironlake_set_drps(struct drm_device *dev, u8 val); |
d5bb081b | 1277 | extern void ironlake_enable_rc6(struct drm_device *dev); |
3b8d8d91 | 1278 | extern void gen6_set_rps(struct drm_device *dev, u8 val); |
3bad0781 | 1279 | extern void intel_detect_pch (struct drm_device *dev); |
e3421a18 | 1280 | extern int intel_trans_dp_port_sel (struct drm_crtc *crtc); |
3bad0781 | 1281 | |
6ef3d427 | 1282 | /* overlay */ |
3bd3c932 | 1283 | #ifdef CONFIG_DEBUG_FS |
6ef3d427 CW |
1284 | extern struct intel_overlay_error_state *intel_overlay_capture_error_state(struct drm_device *dev); |
1285 | extern void intel_overlay_print_error_state(struct seq_file *m, struct intel_overlay_error_state *error); | |
c4a1d9e4 CW |
1286 | |
1287 | extern struct intel_display_error_state *intel_display_capture_error_state(struct drm_device *dev); | |
1288 | extern void intel_display_print_error_state(struct seq_file *m, | |
1289 | struct drm_device *dev, | |
1290 | struct intel_display_error_state *error); | |
3bd3c932 | 1291 | #endif |
6ef3d427 | 1292 | |
1ec14ad3 CW |
1293 | #define LP_RING(d) (&((struct drm_i915_private *)(d))->ring[RCS]) |
1294 | ||
1295 | #define BEGIN_LP_RING(n) \ | |
1296 | intel_ring_begin(LP_RING(dev_priv), (n)) | |
1297 | ||
1298 | #define OUT_RING(x) \ | |
1299 | intel_ring_emit(LP_RING(dev_priv), x) | |
1300 | ||
1301 | #define ADVANCE_LP_RING() \ | |
1302 | intel_ring_advance(LP_RING(dev_priv)) | |
1303 | ||
546b0974 EA |
1304 | /** |
1305 | * Lock test for when it's just for synchronization of ring access. | |
1306 | * | |
1307 | * In that case, we don't need to do it when GEM is initialized as nobody else | |
1308 | * has access to the ring. | |
1309 | */ | |
05394f39 | 1310 | #define RING_LOCK_TEST_WITH_RETURN(dev, file) do { \ |
1ec14ad3 | 1311 | if (LP_RING(dev->dev_private)->obj == NULL) \ |
05394f39 | 1312 | LOCK_TEST_WITH_RETURN(dev, file); \ |
546b0974 EA |
1313 | } while (0) |
1314 | ||
cae5852d | 1315 | |
5f75377d KP |
1316 | #define __i915_read(x, y) \ |
1317 | static inline u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg) { \ | |
1318 | u##x val = read##y(dev_priv->regs + reg); \ | |
db53a302 | 1319 | trace_i915_reg_rw(false, reg, val, sizeof(val)); \ |
5f75377d KP |
1320 | return val; \ |
1321 | } | |
1322 | __i915_read(8, b) | |
1323 | __i915_read(16, w) | |
1324 | __i915_read(32, l) | |
1325 | __i915_read(64, q) | |
1326 | #undef __i915_read | |
1327 | ||
1328 | #define __i915_write(x, y) \ | |
1329 | static inline void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val) { \ | |
db53a302 | 1330 | trace_i915_reg_rw(true, reg, val, sizeof(val)); \ |
5f75377d KP |
1331 | write##y(val, dev_priv->regs + reg); \ |
1332 | } | |
1333 | __i915_write(8, b) | |
1334 | __i915_write(16, w) | |
1335 | __i915_write(32, l) | |
1336 | __i915_write(64, q) | |
1337 | #undef __i915_write | |
1338 | ||
1339 | #define I915_READ8(reg) i915_read8(dev_priv, (reg)) | |
1340 | #define I915_WRITE8(reg, val) i915_write8(dev_priv, (reg), (val)) | |
1341 | ||
1342 | #define I915_READ16(reg) i915_read16(dev_priv, (reg)) | |
1343 | #define I915_WRITE16(reg, val) i915_write16(dev_priv, (reg), (val)) | |
1344 | #define I915_READ16_NOTRACE(reg) readw(dev_priv->regs + (reg)) | |
1345 | #define I915_WRITE16_NOTRACE(reg, val) writew(val, dev_priv->regs + (reg)) | |
1346 | ||
1347 | #define I915_READ(reg) i915_read32(dev_priv, (reg)) | |
1348 | #define I915_WRITE(reg, val) i915_write32(dev_priv, (reg), (val)) | |
cae5852d ZN |
1349 | #define I915_READ_NOTRACE(reg) readl(dev_priv->regs + (reg)) |
1350 | #define I915_WRITE_NOTRACE(reg, val) writel(val, dev_priv->regs + (reg)) | |
5f75377d KP |
1351 | |
1352 | #define I915_WRITE64(reg, val) i915_write64(dev_priv, (reg), (val)) | |
1353 | #define I915_READ64(reg) i915_read64(dev_priv, (reg)) | |
cae5852d ZN |
1354 | |
1355 | #define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg) | |
1356 | #define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg) | |
1357 | ||
ba4f01a3 | 1358 | |
cae5852d ZN |
1359 | /* On SNB platform, before reading ring registers forcewake bit |
1360 | * must be set to prevent GT core from power down and stale values being | |
1361 | * returned. | |
1362 | */ | |
91355834 CW |
1363 | void __gen6_gt_force_wake_get(struct drm_i915_private *dev_priv); |
1364 | void __gen6_gt_force_wake_put(struct drm_i915_private *dev_priv); | |
1365 | void __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv); | |
1366 | ||
1367 | static inline u32 i915_gt_read(struct drm_i915_private *dev_priv, u32 reg) | |
cae5852d | 1368 | { |
eb43f4af CW |
1369 | u32 val; |
1370 | ||
1371 | if (dev_priv->info->gen >= 6) { | |
91355834 | 1372 | __gen6_gt_force_wake_get(dev_priv); |
eb43f4af | 1373 | val = I915_READ(reg); |
91355834 | 1374 | __gen6_gt_force_wake_put(dev_priv); |
eb43f4af CW |
1375 | } else |
1376 | val = I915_READ(reg); | |
1377 | ||
1378 | return val; | |
cae5852d ZN |
1379 | } |
1380 | ||
91355834 CW |
1381 | static inline void i915_gt_write(struct drm_i915_private *dev_priv, |
1382 | u32 reg, u32 val) | |
ba4f01a3 | 1383 | { |
91355834 CW |
1384 | if (dev_priv->info->gen >= 6) |
1385 | __gen6_gt_wait_for_fifo(dev_priv); | |
1386 | I915_WRITE(reg, val); | |
ba4f01a3 | 1387 | } |
1da177e4 | 1388 | #endif |