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1da177e4 LT |
1 | /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*- |
2 | */ | |
0d6aa60b | 3 | /* |
bc54fd1a | 4 | * |
1da177e4 LT |
5 | * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. |
6 | * All Rights Reserved. | |
bc54fd1a DA |
7 | * |
8 | * Permission is hereby granted, free of charge, to any person obtaining a | |
9 | * copy of this software and associated documentation files (the | |
10 | * "Software"), to deal in the Software without restriction, including | |
11 | * without limitation the rights to use, copy, modify, merge, publish, | |
12 | * distribute, sub license, and/or sell copies of the Software, and to | |
13 | * permit persons to whom the Software is furnished to do so, subject to | |
14 | * the following conditions: | |
15 | * | |
16 | * The above copyright notice and this permission notice (including the | |
17 | * next paragraph) shall be included in all copies or substantial portions | |
18 | * of the Software. | |
19 | * | |
20 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS | |
21 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
22 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. | |
23 | * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR | |
24 | * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, | |
25 | * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE | |
26 | * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. | |
27 | * | |
0d6aa60b | 28 | */ |
1da177e4 LT |
29 | |
30 | #ifndef _I915_DRV_H_ | |
31 | #define _I915_DRV_H_ | |
32 | ||
585fb111 | 33 | #include "i915_reg.h" |
79e53945 | 34 | #include "intel_bios.h" |
8187a2b7 | 35 | #include "intel_ringbuffer.h" |
0839ccb8 | 36 | #include <linux/io-mapping.h> |
f899fc64 | 37 | #include <linux/i2c.h> |
0ade6386 | 38 | #include <drm/intel-gtt.h> |
585fb111 | 39 | |
1da177e4 LT |
40 | /* General customization: |
41 | */ | |
42 | ||
43 | #define DRIVER_AUTHOR "Tungsten Graphics, Inc." | |
44 | ||
45 | #define DRIVER_NAME "i915" | |
46 | #define DRIVER_DESC "Intel Graphics" | |
673a394b | 47 | #define DRIVER_DATE "20080730" |
1da177e4 | 48 | |
317c35d1 JB |
49 | enum pipe { |
50 | PIPE_A = 0, | |
51 | PIPE_B, | |
9db4a9c7 JB |
52 | PIPE_C, |
53 | I915_MAX_PIPES | |
317c35d1 | 54 | }; |
9db4a9c7 | 55 | #define pipe_name(p) ((p) + 'A') |
317c35d1 | 56 | |
80824003 JB |
57 | enum plane { |
58 | PLANE_A = 0, | |
59 | PLANE_B, | |
9db4a9c7 | 60 | PLANE_C, |
80824003 | 61 | }; |
9db4a9c7 | 62 | #define plane_name(p) ((p) + 'A') |
52440211 | 63 | |
62fdfeaf EA |
64 | #define I915_GEM_GPU_DOMAINS (~(I915_GEM_DOMAIN_CPU | I915_GEM_DOMAIN_GTT)) |
65 | ||
9db4a9c7 JB |
66 | #define for_each_pipe(p) for ((p) = 0; (p) < dev_priv->num_pipe; (p)++) |
67 | ||
1da177e4 LT |
68 | /* Interface history: |
69 | * | |
70 | * 1.1: Original. | |
0d6aa60b DA |
71 | * 1.2: Add Power Management |
72 | * 1.3: Add vblank support | |
de227f5f | 73 | * 1.4: Fix cmdbuffer path, add heap destroy |
702880f2 | 74 | * 1.5: Add vblank pipe configuration |
2228ed67 MD |
75 | * 1.6: - New ioctl for scheduling buffer swaps on vertical blank |
76 | * - Support vertical blank on secondary display pipe | |
1da177e4 LT |
77 | */ |
78 | #define DRIVER_MAJOR 1 | |
2228ed67 | 79 | #define DRIVER_MINOR 6 |
1da177e4 LT |
80 | #define DRIVER_PATCHLEVEL 0 |
81 | ||
673a394b | 82 | #define WATCH_COHERENCY 0 |
23bc5982 | 83 | #define WATCH_LISTS 0 |
673a394b | 84 | |
71acb5eb DA |
85 | #define I915_GEM_PHYS_CURSOR_0 1 |
86 | #define I915_GEM_PHYS_CURSOR_1 2 | |
87 | #define I915_GEM_PHYS_OVERLAY_REGS 3 | |
88 | #define I915_MAX_PHYS_OBJECT (I915_GEM_PHYS_OVERLAY_REGS) | |
89 | ||
90 | struct drm_i915_gem_phys_object { | |
91 | int id; | |
92 | struct page **page_list; | |
93 | drm_dma_handle_t *handle; | |
05394f39 | 94 | struct drm_i915_gem_object *cur_obj; |
71acb5eb DA |
95 | }; |
96 | ||
1da177e4 LT |
97 | struct mem_block { |
98 | struct mem_block *next; | |
99 | struct mem_block *prev; | |
100 | int start; | |
101 | int size; | |
6c340eac | 102 | struct drm_file *file_priv; /* NULL: free, -1: heap, other: real files */ |
1da177e4 LT |
103 | }; |
104 | ||
0a3e67a4 JB |
105 | struct opregion_header; |
106 | struct opregion_acpi; | |
107 | struct opregion_swsci; | |
108 | struct opregion_asle; | |
109 | ||
8ee1c3db MG |
110 | struct intel_opregion { |
111 | struct opregion_header *header; | |
112 | struct opregion_acpi *acpi; | |
113 | struct opregion_swsci *swsci; | |
114 | struct opregion_asle *asle; | |
44834a67 | 115 | void *vbt; |
01fe9dbd | 116 | u32 __iomem *lid_state; |
8ee1c3db | 117 | }; |
44834a67 | 118 | #define OPREGION_SIZE (8*1024) |
8ee1c3db | 119 | |
6ef3d427 CW |
120 | struct intel_overlay; |
121 | struct intel_overlay_error_state; | |
122 | ||
7c1c2871 DA |
123 | struct drm_i915_master_private { |
124 | drm_local_map_t *sarea; | |
125 | struct _drm_i915_sarea *sarea_priv; | |
126 | }; | |
de151cf6 JB |
127 | #define I915_FENCE_REG_NONE -1 |
128 | ||
129 | struct drm_i915_fence_reg { | |
007cc8ac | 130 | struct list_head lru_list; |
caea7476 | 131 | struct drm_i915_gem_object *obj; |
d9e86c0e | 132 | uint32_t setup_seqno; |
de151cf6 | 133 | }; |
7c1c2871 | 134 | |
9b9d172d | 135 | struct sdvo_device_mapping { |
e957d772 | 136 | u8 initialized; |
9b9d172d | 137 | u8 dvo_port; |
138 | u8 slave_addr; | |
139 | u8 dvo_wiring; | |
e957d772 CW |
140 | u8 i2c_pin; |
141 | u8 i2c_speed; | |
b1083333 | 142 | u8 ddc_pin; |
9b9d172d | 143 | }; |
144 | ||
c4a1d9e4 CW |
145 | struct intel_display_error_state; |
146 | ||
63eeaf38 JB |
147 | struct drm_i915_error_state { |
148 | u32 eir; | |
149 | u32 pgtbl_er; | |
9db4a9c7 | 150 | u32 pipestat[I915_MAX_PIPES]; |
63eeaf38 JB |
151 | u32 ipeir; |
152 | u32 ipehr; | |
153 | u32 instdone; | |
154 | u32 acthd; | |
1d8f38f4 CW |
155 | u32 error; /* gen6+ */ |
156 | u32 bcs_acthd; /* gen6+ blt engine */ | |
157 | u32 bcs_ipehr; | |
158 | u32 bcs_ipeir; | |
159 | u32 bcs_instdone; | |
160 | u32 bcs_seqno; | |
add354dd CW |
161 | u32 vcs_acthd; /* gen6+ bsd engine */ |
162 | u32 vcs_ipehr; | |
163 | u32 vcs_ipeir; | |
164 | u32 vcs_instdone; | |
165 | u32 vcs_seqno; | |
63eeaf38 JB |
166 | u32 instpm; |
167 | u32 instps; | |
168 | u32 instdone1; | |
169 | u32 seqno; | |
9df30794 | 170 | u64 bbaddr; |
748ebc60 | 171 | u64 fence[16]; |
63eeaf38 | 172 | struct timeval time; |
9df30794 CW |
173 | struct drm_i915_error_object { |
174 | int page_count; | |
175 | u32 gtt_offset; | |
176 | u32 *pages[0]; | |
e2f973d5 | 177 | } *ringbuffer[I915_NUM_RINGS], *batchbuffer[I915_NUM_RINGS]; |
9df30794 | 178 | struct drm_i915_error_buffer { |
a779e5ab | 179 | u32 size; |
9df30794 CW |
180 | u32 name; |
181 | u32 seqno; | |
182 | u32 gtt_offset; | |
183 | u32 read_domains; | |
184 | u32 write_domain; | |
a779e5ab | 185 | s32 fence_reg:5; |
9df30794 CW |
186 | s32 pinned:2; |
187 | u32 tiling:2; | |
188 | u32 dirty:1; | |
189 | u32 purgeable:1; | |
e5c65260 | 190 | u32 ring:4; |
93dfb40c | 191 | u32 cache_level:2; |
c724e8a9 CW |
192 | } *active_bo, *pinned_bo; |
193 | u32 active_bo_count, pinned_bo_count; | |
6ef3d427 | 194 | struct intel_overlay_error_state *overlay; |
c4a1d9e4 | 195 | struct intel_display_error_state *display; |
63eeaf38 JB |
196 | }; |
197 | ||
e70236a8 JB |
198 | struct drm_i915_display_funcs { |
199 | void (*dpms)(struct drm_crtc *crtc, int mode); | |
ee5382ae | 200 | bool (*fbc_enabled)(struct drm_device *dev); |
e70236a8 JB |
201 | void (*enable_fbc)(struct drm_crtc *crtc, unsigned long interval); |
202 | void (*disable_fbc)(struct drm_device *dev); | |
203 | int (*get_display_clock_speed)(struct drm_device *dev); | |
204 | int (*get_fifo_size)(struct drm_device *dev, int plane); | |
d210246a | 205 | void (*update_wm)(struct drm_device *dev); |
f564048e EA |
206 | int (*crtc_mode_set)(struct drm_crtc *crtc, |
207 | struct drm_display_mode *mode, | |
208 | struct drm_display_mode *adjusted_mode, | |
209 | int x, int y, | |
210 | struct drm_framebuffer *old_fb); | |
674cf967 | 211 | void (*fdi_link_train)(struct drm_crtc *crtc); |
6067aaea | 212 | void (*init_clock_gating)(struct drm_device *dev); |
645c62a5 | 213 | void (*init_pch_clock_gating)(struct drm_device *dev); |
8c9f3aaf JB |
214 | int (*queue_flip)(struct drm_device *dev, struct drm_crtc *crtc, |
215 | struct drm_framebuffer *fb, | |
216 | struct drm_i915_gem_object *obj); | |
17638cd6 JB |
217 | int (*update_plane)(struct drm_crtc *crtc, struct drm_framebuffer *fb, |
218 | int x, int y); | |
e70236a8 JB |
219 | /* clock updates for mode set */ |
220 | /* cursor updates */ | |
221 | /* render clock increase/decrease */ | |
222 | /* display clock increase/decrease */ | |
223 | /* pll clock increase/decrease */ | |
e70236a8 JB |
224 | }; |
225 | ||
cfdf1fa2 | 226 | struct intel_device_info { |
c96c3a8c | 227 | u8 gen; |
cfdf1fa2 | 228 | u8 is_mobile : 1; |
5ce8ba7c | 229 | u8 is_i85x : 1; |
cfdf1fa2 | 230 | u8 is_i915g : 1; |
cfdf1fa2 | 231 | u8 is_i945gm : 1; |
cfdf1fa2 KH |
232 | u8 is_g33 : 1; |
233 | u8 need_gfx_hws : 1; | |
234 | u8 is_g4x : 1; | |
235 | u8 is_pineview : 1; | |
534843da CW |
236 | u8 is_broadwater : 1; |
237 | u8 is_crestline : 1; | |
4b65177b | 238 | u8 is_ivybridge : 1; |
cfdf1fa2 | 239 | u8 has_fbc : 1; |
cfdf1fa2 KH |
240 | u8 has_pipe_cxsr : 1; |
241 | u8 has_hotplug : 1; | |
b295d1b6 | 242 | u8 cursor_needs_physical : 1; |
31578148 CW |
243 | u8 has_overlay : 1; |
244 | u8 overlay_needs_physical : 1; | |
a6c45cf0 | 245 | u8 supports_tv : 1; |
92f49d9c | 246 | u8 has_bsd_ring : 1; |
549f7365 | 247 | u8 has_blt_ring : 1; |
cfdf1fa2 KH |
248 | }; |
249 | ||
b5e50c3f | 250 | enum no_fbc_reason { |
bed4a673 | 251 | FBC_NO_OUTPUT, /* no outputs enabled to compress */ |
b5e50c3f JB |
252 | FBC_STOLEN_TOO_SMALL, /* not enough space to hold compressed buffers */ |
253 | FBC_UNSUPPORTED_MODE, /* interlace or doublescanned mode */ | |
254 | FBC_MODE_TOO_LARGE, /* mode too large for compression */ | |
255 | FBC_BAD_PLANE, /* fbc not supported on plane */ | |
256 | FBC_NOT_TILED, /* buffer not tiled */ | |
9c928d16 | 257 | FBC_MULTIPLE_PIPES, /* more than one pipe active */ |
c1a9f047 | 258 | FBC_MODULE_PARAM, |
b5e50c3f JB |
259 | }; |
260 | ||
3bad0781 ZW |
261 | enum intel_pch { |
262 | PCH_IBX, /* Ibexpeak PCH */ | |
263 | PCH_CPT, /* Cougarpoint PCH */ | |
264 | }; | |
265 | ||
b690e96c JB |
266 | #define QUIRK_PIPEA_FORCE (1<<0) |
267 | ||
8be48d92 | 268 | struct intel_fbdev; |
38651674 | 269 | |
1da177e4 | 270 | typedef struct drm_i915_private { |
673a394b EA |
271 | struct drm_device *dev; |
272 | ||
cfdf1fa2 KH |
273 | const struct intel_device_info *info; |
274 | ||
ac5c4e76 | 275 | int has_gem; |
72bfa19c | 276 | int relative_constants_mode; |
ac5c4e76 | 277 | |
3043c60c | 278 | void __iomem *regs; |
1da177e4 | 279 | |
f899fc64 CW |
280 | struct intel_gmbus { |
281 | struct i2c_adapter adapter; | |
e957d772 CW |
282 | struct i2c_adapter *force_bit; |
283 | u32 reg0; | |
f899fc64 CW |
284 | } *gmbus; |
285 | ||
ec2a4c3f | 286 | struct pci_dev *bridge_dev; |
1ec14ad3 | 287 | struct intel_ring_buffer ring[I915_NUM_RINGS]; |
6f392d54 | 288 | uint32_t next_seqno; |
1da177e4 | 289 | |
9c8da5eb | 290 | drm_dma_handle_t *status_page_dmah; |
0a3e67a4 | 291 | uint32_t counter; |
dc7a9319 | 292 | drm_local_map_t hws_map; |
05394f39 CW |
293 | struct drm_i915_gem_object *pwrctx; |
294 | struct drm_i915_gem_object *renderctx; | |
1da177e4 | 295 | |
d7658989 JB |
296 | struct resource mch_res; |
297 | ||
a6b54f3f | 298 | unsigned int cpp; |
1da177e4 LT |
299 | int back_offset; |
300 | int front_offset; | |
301 | int current_page; | |
302 | int page_flipping; | |
1da177e4 | 303 | |
1da177e4 | 304 | atomic_t irq_received; |
1ec14ad3 CW |
305 | |
306 | /* protects the irq masks */ | |
307 | spinlock_t irq_lock; | |
ed4cb414 | 308 | /** Cached value of IMR to avoid reads in updating the bitfield */ |
7c463586 | 309 | u32 pipestat[2]; |
1ec14ad3 CW |
310 | u32 irq_mask; |
311 | u32 gt_irq_mask; | |
312 | u32 pch_irq_mask; | |
1da177e4 | 313 | |
5ca58282 JB |
314 | u32 hotplug_supported_mask; |
315 | struct work_struct hotplug_work; | |
316 | ||
1da177e4 LT |
317 | int tex_lru_log_granularity; |
318 | int allow_batchbuffer; | |
319 | struct mem_block *agp_heap; | |
0d6aa60b | 320 | unsigned int sr01, adpa, ppcr, dvob, dvoc, lvds; |
702880f2 | 321 | int vblank_pipe; |
a3524f1b | 322 | int num_pipe; |
a6b54f3f | 323 | |
f65d9421 | 324 | /* For hangcheck timer */ |
576ae4b8 | 325 | #define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */ |
f65d9421 BG |
326 | struct timer_list hangcheck_timer; |
327 | int hangcheck_count; | |
328 | uint32_t last_acthd; | |
cbb465e7 CW |
329 | uint32_t last_instdone; |
330 | uint32_t last_instdone1; | |
f65d9421 | 331 | |
80824003 JB |
332 | unsigned long cfb_size; |
333 | unsigned long cfb_pitch; | |
bed4a673 | 334 | unsigned long cfb_offset; |
80824003 JB |
335 | int cfb_fence; |
336 | int cfb_plane; | |
bed4a673 | 337 | int cfb_y; |
80824003 | 338 | |
8ee1c3db MG |
339 | struct intel_opregion opregion; |
340 | ||
02e792fb DV |
341 | /* overlay */ |
342 | struct intel_overlay *overlay; | |
343 | ||
79e53945 | 344 | /* LVDS info */ |
a9573556 | 345 | int backlight_level; /* restore backlight to this value */ |
47356eb6 | 346 | bool backlight_enabled; |
79e53945 | 347 | struct drm_display_mode *panel_fixed_mode; |
88631706 ML |
348 | struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */ |
349 | struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */ | |
79e53945 JB |
350 | |
351 | /* Feature bits from the VBIOS */ | |
95281e35 HE |
352 | unsigned int int_tv_support:1; |
353 | unsigned int lvds_dither:1; | |
354 | unsigned int lvds_vbt:1; | |
355 | unsigned int int_crt_support:1; | |
43565a06 KH |
356 | unsigned int lvds_use_ssc:1; |
357 | int lvds_ssc_freq; | |
5ceb0f9b | 358 | struct { |
9f0e7ff4 JB |
359 | int rate; |
360 | int lanes; | |
361 | int preemphasis; | |
362 | int vswing; | |
363 | ||
364 | bool initialized; | |
365 | bool support; | |
366 | int bpp; | |
367 | struct edp_power_seq pps; | |
5ceb0f9b | 368 | } edp; |
89667383 | 369 | bool no_aux_handshake; |
79e53945 | 370 | |
c1c7af60 JB |
371 | struct notifier_block lid_notifier; |
372 | ||
f899fc64 | 373 | int crt_ddc_pin; |
de151cf6 JB |
374 | struct drm_i915_fence_reg fence_regs[16]; /* assume 965 */ |
375 | int fence_reg_start; /* 4 if userland hasn't ioctl'd us yet */ | |
376 | int num_fence_regs; /* 8 on pre-965, 16 otherwise */ | |
377 | ||
95534263 | 378 | unsigned int fsb_freq, mem_freq, is_ddr3; |
7662c8bd | 379 | |
63eeaf38 JB |
380 | spinlock_t error_lock; |
381 | struct drm_i915_error_state *first_error; | |
8a905236 | 382 | struct work_struct error_work; |
30dbf0c0 | 383 | struct completion error_completion; |
9c9fe1f8 | 384 | struct workqueue_struct *wq; |
63eeaf38 | 385 | |
e70236a8 JB |
386 | /* Display functions */ |
387 | struct drm_i915_display_funcs display; | |
388 | ||
3bad0781 ZW |
389 | /* PCH chipset type */ |
390 | enum intel_pch pch_type; | |
391 | ||
b690e96c JB |
392 | unsigned long quirks; |
393 | ||
ba8bbcf6 | 394 | /* Register state */ |
c9354c85 | 395 | bool modeset_on_lid; |
ba8bbcf6 JB |
396 | u8 saveLBB; |
397 | u32 saveDSPACNTR; | |
398 | u32 saveDSPBCNTR; | |
e948e994 | 399 | u32 saveDSPARB; |
968b503e | 400 | u32 saveHWS; |
ba8bbcf6 JB |
401 | u32 savePIPEACONF; |
402 | u32 savePIPEBCONF; | |
403 | u32 savePIPEASRC; | |
404 | u32 savePIPEBSRC; | |
405 | u32 saveFPA0; | |
406 | u32 saveFPA1; | |
407 | u32 saveDPLL_A; | |
408 | u32 saveDPLL_A_MD; | |
409 | u32 saveHTOTAL_A; | |
410 | u32 saveHBLANK_A; | |
411 | u32 saveHSYNC_A; | |
412 | u32 saveVTOTAL_A; | |
413 | u32 saveVBLANK_A; | |
414 | u32 saveVSYNC_A; | |
415 | u32 saveBCLRPAT_A; | |
5586c8bc | 416 | u32 saveTRANSACONF; |
42048781 ZW |
417 | u32 saveTRANS_HTOTAL_A; |
418 | u32 saveTRANS_HBLANK_A; | |
419 | u32 saveTRANS_HSYNC_A; | |
420 | u32 saveTRANS_VTOTAL_A; | |
421 | u32 saveTRANS_VBLANK_A; | |
422 | u32 saveTRANS_VSYNC_A; | |
0da3ea12 | 423 | u32 savePIPEASTAT; |
ba8bbcf6 JB |
424 | u32 saveDSPASTRIDE; |
425 | u32 saveDSPASIZE; | |
426 | u32 saveDSPAPOS; | |
585fb111 | 427 | u32 saveDSPAADDR; |
ba8bbcf6 JB |
428 | u32 saveDSPASURF; |
429 | u32 saveDSPATILEOFF; | |
430 | u32 savePFIT_PGM_RATIOS; | |
0eb96d6e | 431 | u32 saveBLC_HIST_CTL; |
ba8bbcf6 JB |
432 | u32 saveBLC_PWM_CTL; |
433 | u32 saveBLC_PWM_CTL2; | |
42048781 ZW |
434 | u32 saveBLC_CPU_PWM_CTL; |
435 | u32 saveBLC_CPU_PWM_CTL2; | |
ba8bbcf6 JB |
436 | u32 saveFPB0; |
437 | u32 saveFPB1; | |
438 | u32 saveDPLL_B; | |
439 | u32 saveDPLL_B_MD; | |
440 | u32 saveHTOTAL_B; | |
441 | u32 saveHBLANK_B; | |
442 | u32 saveHSYNC_B; | |
443 | u32 saveVTOTAL_B; | |
444 | u32 saveVBLANK_B; | |
445 | u32 saveVSYNC_B; | |
446 | u32 saveBCLRPAT_B; | |
5586c8bc | 447 | u32 saveTRANSBCONF; |
42048781 ZW |
448 | u32 saveTRANS_HTOTAL_B; |
449 | u32 saveTRANS_HBLANK_B; | |
450 | u32 saveTRANS_HSYNC_B; | |
451 | u32 saveTRANS_VTOTAL_B; | |
452 | u32 saveTRANS_VBLANK_B; | |
453 | u32 saveTRANS_VSYNC_B; | |
0da3ea12 | 454 | u32 savePIPEBSTAT; |
ba8bbcf6 JB |
455 | u32 saveDSPBSTRIDE; |
456 | u32 saveDSPBSIZE; | |
457 | u32 saveDSPBPOS; | |
585fb111 | 458 | u32 saveDSPBADDR; |
ba8bbcf6 JB |
459 | u32 saveDSPBSURF; |
460 | u32 saveDSPBTILEOFF; | |
585fb111 JB |
461 | u32 saveVGA0; |
462 | u32 saveVGA1; | |
463 | u32 saveVGA_PD; | |
ba8bbcf6 JB |
464 | u32 saveVGACNTRL; |
465 | u32 saveADPA; | |
466 | u32 saveLVDS; | |
585fb111 JB |
467 | u32 savePP_ON_DELAYS; |
468 | u32 savePP_OFF_DELAYS; | |
ba8bbcf6 JB |
469 | u32 saveDVOA; |
470 | u32 saveDVOB; | |
471 | u32 saveDVOC; | |
472 | u32 savePP_ON; | |
473 | u32 savePP_OFF; | |
474 | u32 savePP_CONTROL; | |
585fb111 | 475 | u32 savePP_DIVISOR; |
ba8bbcf6 JB |
476 | u32 savePFIT_CONTROL; |
477 | u32 save_palette_a[256]; | |
478 | u32 save_palette_b[256]; | |
06027f91 | 479 | u32 saveDPFC_CB_BASE; |
ba8bbcf6 JB |
480 | u32 saveFBC_CFB_BASE; |
481 | u32 saveFBC_LL_BASE; | |
482 | u32 saveFBC_CONTROL; | |
483 | u32 saveFBC_CONTROL2; | |
0da3ea12 JB |
484 | u32 saveIER; |
485 | u32 saveIIR; | |
486 | u32 saveIMR; | |
42048781 ZW |
487 | u32 saveDEIER; |
488 | u32 saveDEIMR; | |
489 | u32 saveGTIER; | |
490 | u32 saveGTIMR; | |
491 | u32 saveFDI_RXA_IMR; | |
492 | u32 saveFDI_RXB_IMR; | |
1f84e550 | 493 | u32 saveCACHE_MODE_0; |
1f84e550 | 494 | u32 saveMI_ARB_STATE; |
ba8bbcf6 JB |
495 | u32 saveSWF0[16]; |
496 | u32 saveSWF1[16]; | |
497 | u32 saveSWF2[3]; | |
498 | u8 saveMSR; | |
499 | u8 saveSR[8]; | |
123f794f | 500 | u8 saveGR[25]; |
ba8bbcf6 | 501 | u8 saveAR_INDEX; |
a59e122a | 502 | u8 saveAR[21]; |
ba8bbcf6 | 503 | u8 saveDACMASK; |
a59e122a | 504 | u8 saveCR[37]; |
79f11c19 | 505 | uint64_t saveFENCE[16]; |
1fd1c624 EA |
506 | u32 saveCURACNTR; |
507 | u32 saveCURAPOS; | |
508 | u32 saveCURABASE; | |
509 | u32 saveCURBCNTR; | |
510 | u32 saveCURBPOS; | |
511 | u32 saveCURBBASE; | |
512 | u32 saveCURSIZE; | |
a4fc5ed6 KP |
513 | u32 saveDP_B; |
514 | u32 saveDP_C; | |
515 | u32 saveDP_D; | |
516 | u32 savePIPEA_GMCH_DATA_M; | |
517 | u32 savePIPEB_GMCH_DATA_M; | |
518 | u32 savePIPEA_GMCH_DATA_N; | |
519 | u32 savePIPEB_GMCH_DATA_N; | |
520 | u32 savePIPEA_DP_LINK_M; | |
521 | u32 savePIPEB_DP_LINK_M; | |
522 | u32 savePIPEA_DP_LINK_N; | |
523 | u32 savePIPEB_DP_LINK_N; | |
42048781 ZW |
524 | u32 saveFDI_RXA_CTL; |
525 | u32 saveFDI_TXA_CTL; | |
526 | u32 saveFDI_RXB_CTL; | |
527 | u32 saveFDI_TXB_CTL; | |
528 | u32 savePFA_CTL_1; | |
529 | u32 savePFB_CTL_1; | |
530 | u32 savePFA_WIN_SZ; | |
531 | u32 savePFB_WIN_SZ; | |
532 | u32 savePFA_WIN_POS; | |
533 | u32 savePFB_WIN_POS; | |
5586c8bc ZW |
534 | u32 savePCH_DREF_CONTROL; |
535 | u32 saveDISP_ARB_CTL; | |
536 | u32 savePIPEA_DATA_M1; | |
537 | u32 savePIPEA_DATA_N1; | |
538 | u32 savePIPEA_LINK_M1; | |
539 | u32 savePIPEA_LINK_N1; | |
540 | u32 savePIPEB_DATA_M1; | |
541 | u32 savePIPEB_DATA_N1; | |
542 | u32 savePIPEB_LINK_M1; | |
543 | u32 savePIPEB_LINK_N1; | |
b5b72e89 | 544 | u32 saveMCHBAR_RENDER_STANDBY; |
673a394b EA |
545 | |
546 | struct { | |
19966754 | 547 | /** Bridge to intel-gtt-ko */ |
c64f7ba5 | 548 | const struct intel_gtt *gtt; |
19966754 | 549 | /** Memory allocator for GTT stolen memory */ |
fe669bf8 | 550 | struct drm_mm stolen; |
19966754 | 551 | /** Memory allocator for GTT */ |
673a394b | 552 | struct drm_mm gtt_space; |
93a37f20 DV |
553 | /** List of all objects in gtt_space. Used to restore gtt |
554 | * mappings on resume */ | |
555 | struct list_head gtt_list; | |
bee4a186 CW |
556 | |
557 | /** Usable portion of the GTT for GEM */ | |
558 | unsigned long gtt_start; | |
a6e0aa42 | 559 | unsigned long gtt_mappable_end; |
bee4a186 | 560 | unsigned long gtt_end; |
673a394b | 561 | |
0839ccb8 | 562 | struct io_mapping *gtt_mapping; |
ab657db1 | 563 | int gtt_mtrr; |
0839ccb8 | 564 | |
17250b71 | 565 | struct shrinker inactive_shrinker; |
31169714 | 566 | |
69dc4987 CW |
567 | /** |
568 | * List of objects currently involved in rendering. | |
569 | * | |
570 | * Includes buffers having the contents of their GPU caches | |
571 | * flushed, not necessarily primitives. last_rendering_seqno | |
572 | * represents when the rendering involved will be completed. | |
573 | * | |
574 | * A reference is held on the buffer while on this list. | |
575 | */ | |
576 | struct list_head active_list; | |
577 | ||
673a394b EA |
578 | /** |
579 | * List of objects which are not in the ringbuffer but which | |
580 | * still have a write_domain which needs to be flushed before | |
581 | * unbinding. | |
582 | * | |
ce44b0ea EA |
583 | * last_rendering_seqno is 0 while an object is in this list. |
584 | * | |
673a394b EA |
585 | * A reference is held on the buffer while on this list. |
586 | */ | |
587 | struct list_head flushing_list; | |
588 | ||
589 | /** | |
590 | * LRU list of objects which are not in the ringbuffer and | |
591 | * are ready to unbind, but are still in the GTT. | |
592 | * | |
ce44b0ea EA |
593 | * last_rendering_seqno is 0 while an object is in this list. |
594 | * | |
673a394b EA |
595 | * A reference is not held on the buffer while on this list, |
596 | * as merely being GTT-bound shouldn't prevent its being | |
597 | * freed, and we'll pull it off the list in the free path. | |
598 | */ | |
599 | struct list_head inactive_list; | |
600 | ||
f13d3f73 CW |
601 | /** |
602 | * LRU list of objects which are not in the ringbuffer but | |
603 | * are still pinned in the GTT. | |
604 | */ | |
605 | struct list_head pinned_list; | |
606 | ||
a09ba7fa EA |
607 | /** LRU list of objects with fence regs on them. */ |
608 | struct list_head fence_list; | |
609 | ||
be72615b CW |
610 | /** |
611 | * List of objects currently pending being freed. | |
612 | * | |
613 | * These objects are no longer in use, but due to a signal | |
614 | * we were prevented from freeing them at the appointed time. | |
615 | */ | |
616 | struct list_head deferred_free_list; | |
617 | ||
673a394b EA |
618 | /** |
619 | * We leave the user IRQ off as much as possible, | |
620 | * but this means that requests will finish and never | |
621 | * be retired once the system goes idle. Set a timer to | |
622 | * fire periodically while the ring is running. When it | |
623 | * fires, go retire requests. | |
624 | */ | |
625 | struct delayed_work retire_work; | |
626 | ||
ce453d81 CW |
627 | /** |
628 | * Are we in a non-interruptible section of code like | |
629 | * modesetting? | |
630 | */ | |
631 | bool interruptible; | |
632 | ||
673a394b EA |
633 | /** |
634 | * Flag if the X Server, and thus DRM, is not currently in | |
635 | * control of the device. | |
636 | * | |
637 | * This is set between LeaveVT and EnterVT. It needs to be | |
638 | * replaced with a semaphore. It also needs to be | |
639 | * transitioned away from for kernel modesetting. | |
640 | */ | |
641 | int suspended; | |
642 | ||
643 | /** | |
644 | * Flag if the hardware appears to be wedged. | |
645 | * | |
646 | * This is set when attempts to idle the device timeout. | |
25985edc | 647 | * It prevents command submission from occurring and makes |
673a394b EA |
648 | * every pending request fail |
649 | */ | |
ba1234d1 | 650 | atomic_t wedged; |
673a394b EA |
651 | |
652 | /** Bit 6 swizzling required for X tiling */ | |
653 | uint32_t bit_6_swizzle_x; | |
654 | /** Bit 6 swizzling required for Y tiling */ | |
655 | uint32_t bit_6_swizzle_y; | |
71acb5eb DA |
656 | |
657 | /* storage for physical objects */ | |
658 | struct drm_i915_gem_phys_object *phys_objs[I915_MAX_PHYS_OBJECT]; | |
9220434a | 659 | |
73aa808f | 660 | /* accounting, useful for userland debugging */ |
73aa808f | 661 | size_t gtt_total; |
6299f992 CW |
662 | size_t mappable_gtt_total; |
663 | size_t object_memory; | |
73aa808f | 664 | u32 object_count; |
673a394b | 665 | } mm; |
9b9d172d | 666 | struct sdvo_device_mapping sdvo_mappings[2]; |
a3e17eb8 ZY |
667 | /* indicate whether the LVDS_BORDER should be enabled or not */ |
668 | unsigned int lvds_border_bits; | |
1d8e1c75 CW |
669 | /* Panel fitter placement and size for Ironlake+ */ |
670 | u32 pch_pf_pos, pch_pf_size; | |
5d613501 | 671 | int panel_t3, panel_t12; |
652c393a | 672 | |
6b95a207 KH |
673 | struct drm_crtc *plane_to_crtc_mapping[2]; |
674 | struct drm_crtc *pipe_to_crtc_mapping[2]; | |
675 | wait_queue_head_t pending_flip_queue; | |
1afe3e9d | 676 | bool flip_pending_is_done; |
6b95a207 | 677 | |
652c393a JB |
678 | /* Reclocking support */ |
679 | bool render_reclock_avail; | |
680 | bool lvds_downclock_avail; | |
18f9ed12 ZY |
681 | /* indicates the reduced downclock for LVDS*/ |
682 | int lvds_downclock; | |
652c393a JB |
683 | struct work_struct idle_work; |
684 | struct timer_list idle_timer; | |
685 | bool busy; | |
686 | u16 orig_clock; | |
6363ee6f ZY |
687 | int child_dev_num; |
688 | struct child_device_config *child_dev; | |
a2565377 | 689 | struct drm_connector *int_lvds_connector; |
f97108d1 | 690 | |
c4804411 | 691 | bool mchbar_need_disable; |
f97108d1 | 692 | |
4912d041 BW |
693 | struct work_struct rps_work; |
694 | spinlock_t rps_lock; | |
695 | u32 pm_iir; | |
696 | ||
f97108d1 JB |
697 | u8 cur_delay; |
698 | u8 min_delay; | |
699 | u8 max_delay; | |
7648fa99 JB |
700 | u8 fmax; |
701 | u8 fstart; | |
702 | ||
05394f39 CW |
703 | u64 last_count1; |
704 | unsigned long last_time1; | |
705 | u64 last_count2; | |
706 | struct timespec last_time2; | |
707 | unsigned long gfx_power; | |
708 | int c_m; | |
709 | int r_t; | |
710 | u8 corr; | |
7648fa99 | 711 | spinlock_t *mchdev_lock; |
b5e50c3f JB |
712 | |
713 | enum no_fbc_reason no_fbc_reason; | |
38651674 | 714 | |
20bf377e JB |
715 | struct drm_mm_node *compressed_fb; |
716 | struct drm_mm_node *compressed_llb; | |
34dc4d44 | 717 | |
ae681d96 CW |
718 | unsigned long last_gpu_reset; |
719 | ||
8be48d92 DA |
720 | /* list of fbdev register on this device */ |
721 | struct intel_fbdev *fbdev; | |
e953fd7b CW |
722 | |
723 | struct drm_property *broadcast_rgb_property; | |
3f43c48d | 724 | struct drm_property *force_audio_property; |
fcca7926 BW |
725 | |
726 | atomic_t forcewake_count; | |
1da177e4 LT |
727 | } drm_i915_private_t; |
728 | ||
93dfb40c CW |
729 | enum i915_cache_level { |
730 | I915_CACHE_NONE, | |
731 | I915_CACHE_LLC, | |
732 | I915_CACHE_LLC_MLC, /* gen6+ */ | |
733 | }; | |
734 | ||
673a394b | 735 | struct drm_i915_gem_object { |
c397b908 | 736 | struct drm_gem_object base; |
673a394b EA |
737 | |
738 | /** Current space allocated to this object in the GTT, if any. */ | |
739 | struct drm_mm_node *gtt_space; | |
93a37f20 | 740 | struct list_head gtt_list; |
673a394b EA |
741 | |
742 | /** This object's place on the active/flushing/inactive lists */ | |
69dc4987 CW |
743 | struct list_head ring_list; |
744 | struct list_head mm_list; | |
99fcb766 DV |
745 | /** This object's place on GPU write list */ |
746 | struct list_head gpu_write_list; | |
432e58ed CW |
747 | /** This object's place in the batchbuffer or on the eviction list */ |
748 | struct list_head exec_list; | |
673a394b EA |
749 | |
750 | /** | |
751 | * This is set if the object is on the active or flushing lists | |
752 | * (has pending rendering), and is not set if it's on inactive (ready | |
753 | * to be unbound). | |
754 | */ | |
778c3544 | 755 | unsigned int active : 1; |
673a394b EA |
756 | |
757 | /** | |
758 | * This is set if the object has been written to since last bound | |
759 | * to the GTT | |
760 | */ | |
778c3544 DV |
761 | unsigned int dirty : 1; |
762 | ||
87ca9c8a CW |
763 | /** |
764 | * This is set if the object has been written to since the last | |
765 | * GPU flush. | |
766 | */ | |
767 | unsigned int pending_gpu_write : 1; | |
768 | ||
778c3544 DV |
769 | /** |
770 | * Fence register bits (if any) for this object. Will be set | |
771 | * as needed when mapped into the GTT. | |
772 | * Protected by dev->struct_mutex. | |
773 | * | |
774 | * Size: 4 bits for 16 fences + sign (for FENCE_REG_NONE) | |
775 | */ | |
11824e8c | 776 | signed int fence_reg : 5; |
778c3544 | 777 | |
778c3544 DV |
778 | /** |
779 | * Advice: are the backing pages purgeable? | |
780 | */ | |
781 | unsigned int madv : 2; | |
782 | ||
778c3544 DV |
783 | /** |
784 | * Current tiling mode for the object. | |
785 | */ | |
786 | unsigned int tiling_mode : 2; | |
d9e86c0e | 787 | unsigned int tiling_changed : 1; |
778c3544 DV |
788 | |
789 | /** How many users have pinned this object in GTT space. The following | |
790 | * users can each hold at most one reference: pwrite/pread, pin_ioctl | |
791 | * (via user_pin_count), execbuffer (objects are not allowed multiple | |
792 | * times for the same batchbuffer), and the framebuffer code. When | |
793 | * switching/pageflipping, the framebuffer code has at most two buffers | |
794 | * pinned per crtc. | |
795 | * | |
796 | * In the worst case this is 1 + 1 + 1 + 2*2 = 7. That would fit into 3 | |
797 | * bits with absolutely no headroom. So use 4 bits. */ | |
11824e8c | 798 | unsigned int pin_count : 4; |
778c3544 | 799 | #define DRM_I915_GEM_OBJECT_MAX_PIN_COUNT 0xf |
673a394b | 800 | |
75e9e915 DV |
801 | /** |
802 | * Is the object at the current location in the gtt mappable and | |
803 | * fenceable? Used to avoid costly recalculations. | |
804 | */ | |
805 | unsigned int map_and_fenceable : 1; | |
806 | ||
fb7d516a DV |
807 | /** |
808 | * Whether the current gtt mapping needs to be mappable (and isn't just | |
809 | * mappable by accident). Track pin and fault separate for a more | |
810 | * accurate mappable working set. | |
811 | */ | |
812 | unsigned int fault_mappable : 1; | |
813 | unsigned int pin_mappable : 1; | |
814 | ||
caea7476 CW |
815 | /* |
816 | * Is the GPU currently using a fence to access this buffer, | |
817 | */ | |
818 | unsigned int pending_fenced_gpu_access:1; | |
819 | unsigned int fenced_gpu_access:1; | |
820 | ||
93dfb40c CW |
821 | unsigned int cache_level:2; |
822 | ||
856fa198 | 823 | struct page **pages; |
673a394b | 824 | |
185cbcb3 DV |
825 | /** |
826 | * DMAR support | |
827 | */ | |
828 | struct scatterlist *sg_list; | |
829 | int num_sg; | |
830 | ||
67731b87 CW |
831 | /** |
832 | * Used for performing relocations during execbuffer insertion. | |
833 | */ | |
834 | struct hlist_node exec_node; | |
835 | unsigned long exec_handle; | |
6fe4f140 | 836 | struct drm_i915_gem_exec_object2 *exec_entry; |
67731b87 | 837 | |
673a394b EA |
838 | /** |
839 | * Current offset of the object in GTT space. | |
840 | * | |
841 | * This is the same as gtt_space->start | |
842 | */ | |
843 | uint32_t gtt_offset; | |
e67b8ce1 | 844 | |
673a394b EA |
845 | /** Breadcrumb of last rendering to the buffer. */ |
846 | uint32_t last_rendering_seqno; | |
caea7476 CW |
847 | struct intel_ring_buffer *ring; |
848 | ||
849 | /** Breadcrumb of last fenced GPU access to the buffer. */ | |
850 | uint32_t last_fenced_seqno; | |
851 | struct intel_ring_buffer *last_fenced_ring; | |
673a394b | 852 | |
778c3544 | 853 | /** Current tiling stride for the object, if it's tiled. */ |
de151cf6 | 854 | uint32_t stride; |
673a394b | 855 | |
280b713b | 856 | /** Record of address bit 17 of each page at last unbind. */ |
d312ec25 | 857 | unsigned long *bit_17; |
280b713b | 858 | |
ba1eb1d8 | 859 | |
673a394b | 860 | /** |
e47c68e9 EA |
861 | * If present, while GEM_DOMAIN_CPU is in the read domain this array |
862 | * flags which individual pages are valid. | |
673a394b EA |
863 | */ |
864 | uint8_t *page_cpu_valid; | |
79e53945 JB |
865 | |
866 | /** User space pin count and filp owning the pin */ | |
867 | uint32_t user_pin_count; | |
868 | struct drm_file *pin_filp; | |
71acb5eb DA |
869 | |
870 | /** for phy allocated objects */ | |
871 | struct drm_i915_gem_phys_object *phys_obj; | |
b70d11da | 872 | |
6b95a207 KH |
873 | /** |
874 | * Number of crtcs where this object is currently the fb, but | |
875 | * will be page flipped away on the next vblank. When it | |
876 | * reaches 0, dev_priv->pending_flip_queue will be woken up. | |
877 | */ | |
878 | atomic_t pending_flip; | |
673a394b EA |
879 | }; |
880 | ||
62b8b215 | 881 | #define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base) |
23010e43 | 882 | |
673a394b EA |
883 | /** |
884 | * Request queue structure. | |
885 | * | |
886 | * The request queue allows us to note sequence numbers that have been emitted | |
887 | * and may be associated with active buffers to be retired. | |
888 | * | |
889 | * By keeping this list, we can avoid having to do questionable | |
890 | * sequence-number comparisons on buffer last_rendering_seqnos, and associate | |
891 | * an emission time with seqnos for tracking how far ahead of the GPU we are. | |
892 | */ | |
893 | struct drm_i915_gem_request { | |
852835f3 ZN |
894 | /** On Which ring this request was generated */ |
895 | struct intel_ring_buffer *ring; | |
896 | ||
673a394b EA |
897 | /** GEM sequence number associated with this request. */ |
898 | uint32_t seqno; | |
899 | ||
900 | /** Time at which this request was emitted, in jiffies. */ | |
901 | unsigned long emitted_jiffies; | |
902 | ||
b962442e | 903 | /** global list entry for this request */ |
673a394b | 904 | struct list_head list; |
b962442e | 905 | |
f787a5f5 | 906 | struct drm_i915_file_private *file_priv; |
b962442e EA |
907 | /** file_priv list entry for this request */ |
908 | struct list_head client_list; | |
673a394b EA |
909 | }; |
910 | ||
911 | struct drm_i915_file_private { | |
912 | struct { | |
1c25595f | 913 | struct spinlock lock; |
b962442e | 914 | struct list_head request_list; |
673a394b EA |
915 | } mm; |
916 | }; | |
917 | ||
cae5852d ZN |
918 | #define INTEL_INFO(dev) (((struct drm_i915_private *) (dev)->dev_private)->info) |
919 | ||
920 | #define IS_I830(dev) ((dev)->pci_device == 0x3577) | |
921 | #define IS_845G(dev) ((dev)->pci_device == 0x2562) | |
922 | #define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x) | |
923 | #define IS_I865G(dev) ((dev)->pci_device == 0x2572) | |
924 | #define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g) | |
925 | #define IS_I915GM(dev) ((dev)->pci_device == 0x2592) | |
926 | #define IS_I945G(dev) ((dev)->pci_device == 0x2772) | |
927 | #define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm) | |
928 | #define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater) | |
929 | #define IS_CRESTLINE(dev) (INTEL_INFO(dev)->is_crestline) | |
930 | #define IS_GM45(dev) ((dev)->pci_device == 0x2A42) | |
931 | #define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x) | |
932 | #define IS_PINEVIEW_G(dev) ((dev)->pci_device == 0xa001) | |
933 | #define IS_PINEVIEW_M(dev) ((dev)->pci_device == 0xa011) | |
934 | #define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview) | |
935 | #define IS_G33(dev) (INTEL_INFO(dev)->is_g33) | |
936 | #define IS_IRONLAKE_D(dev) ((dev)->pci_device == 0x0042) | |
937 | #define IS_IRONLAKE_M(dev) ((dev)->pci_device == 0x0046) | |
4b65177b | 938 | #define IS_IVYBRIDGE(dev) (INTEL_INFO(dev)->is_ivybridge) |
cae5852d ZN |
939 | #define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile) |
940 | ||
85436696 JB |
941 | /* |
942 | * The genX designation typically refers to the render engine, so render | |
943 | * capability related checks should use IS_GEN, while display and other checks | |
944 | * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular | |
945 | * chips, etc.). | |
946 | */ | |
cae5852d ZN |
947 | #define IS_GEN2(dev) (INTEL_INFO(dev)->gen == 2) |
948 | #define IS_GEN3(dev) (INTEL_INFO(dev)->gen == 3) | |
949 | #define IS_GEN4(dev) (INTEL_INFO(dev)->gen == 4) | |
950 | #define IS_GEN5(dev) (INTEL_INFO(dev)->gen == 5) | |
951 | #define IS_GEN6(dev) (INTEL_INFO(dev)->gen == 6) | |
85436696 | 952 | #define IS_GEN7(dev) (INTEL_INFO(dev)->gen == 7) |
cae5852d ZN |
953 | |
954 | #define HAS_BSD(dev) (INTEL_INFO(dev)->has_bsd_ring) | |
955 | #define HAS_BLT(dev) (INTEL_INFO(dev)->has_blt_ring) | |
956 | #define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws) | |
957 | ||
05394f39 | 958 | #define HAS_OVERLAY(dev) (INTEL_INFO(dev)->has_overlay) |
cae5852d ZN |
959 | #define OVERLAY_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->overlay_needs_physical) |
960 | ||
961 | /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte | |
962 | * rows, which changed the alignment requirements and fence programming. | |
963 | */ | |
964 | #define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \ | |
965 | IS_I915GM(dev))) | |
966 | #define SUPPORTS_DIGITAL_OUTPUTS(dev) (!IS_GEN2(dev) && !IS_PINEVIEW(dev)) | |
967 | #define SUPPORTS_INTEGRATED_HDMI(dev) (IS_G4X(dev) || IS_GEN5(dev)) | |
968 | #define SUPPORTS_INTEGRATED_DP(dev) (IS_G4X(dev) || IS_GEN5(dev)) | |
969 | #define SUPPORTS_EDP(dev) (IS_IRONLAKE_M(dev)) | |
970 | #define SUPPORTS_TV(dev) (INTEL_INFO(dev)->supports_tv) | |
971 | #define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug) | |
972 | /* dsparb controlled by hw only */ | |
973 | #define DSPARB_HWCONTROL(dev) (IS_G4X(dev) || IS_IRONLAKE(dev)) | |
974 | ||
975 | #define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2) | |
976 | #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr) | |
977 | #define I915_HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc) | |
cae5852d | 978 | |
eceae481 JB |
979 | #define HAS_PCH_SPLIT(dev) (IS_GEN5(dev) || IS_GEN6(dev) || IS_IVYBRIDGE(dev)) |
980 | #define HAS_PIPE_CONTROL(dev) (INTEL_INFO(dev)->gen >= 5) | |
cae5852d ZN |
981 | |
982 | #define INTEL_PCH_TYPE(dev) (((struct drm_i915_private *)(dev)->dev_private)->pch_type) | |
983 | #define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT) | |
984 | #define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX) | |
985 | ||
05394f39 CW |
986 | #include "i915_trace.h" |
987 | ||
c153f45f | 988 | extern struct drm_ioctl_desc i915_ioctls[]; |
b3a83639 | 989 | extern int i915_max_ioctl; |
79e53945 | 990 | extern unsigned int i915_fbpercrtc; |
fca87409 | 991 | extern int i915_panel_ignore_lid; |
652c393a | 992 | extern unsigned int i915_powersave; |
a1656b90 | 993 | extern unsigned int i915_semaphores; |
33814341 | 994 | extern unsigned int i915_lvds_downclock; |
a7615030 | 995 | extern unsigned int i915_panel_use_ssc; |
5a1e5b6c | 996 | extern int i915_vbt_sdvo_panel_type; |
ac668088 | 997 | extern unsigned int i915_enable_rc6; |
c1a9f047 | 998 | extern unsigned int i915_enable_fbc; |
3e0dc6b0 | 999 | extern bool i915_enable_hangcheck; |
b3a83639 | 1000 | |
6a9ee8af DA |
1001 | extern int i915_suspend(struct drm_device *dev, pm_message_t state); |
1002 | extern int i915_resume(struct drm_device *dev); | |
7c1c2871 DA |
1003 | extern int i915_master_create(struct drm_device *dev, struct drm_master *master); |
1004 | extern void i915_master_destroy(struct drm_device *dev, struct drm_master *master); | |
1005 | ||
1da177e4 | 1006 | /* i915_dma.c */ |
84b1fd10 | 1007 | extern void i915_kernel_lost_context(struct drm_device * dev); |
22eae947 | 1008 | extern int i915_driver_load(struct drm_device *, unsigned long flags); |
ba8bbcf6 | 1009 | extern int i915_driver_unload(struct drm_device *); |
673a394b | 1010 | extern int i915_driver_open(struct drm_device *dev, struct drm_file *file_priv); |
84b1fd10 | 1011 | extern void i915_driver_lastclose(struct drm_device * dev); |
6c340eac EA |
1012 | extern void i915_driver_preclose(struct drm_device *dev, |
1013 | struct drm_file *file_priv); | |
673a394b EA |
1014 | extern void i915_driver_postclose(struct drm_device *dev, |
1015 | struct drm_file *file_priv); | |
84b1fd10 | 1016 | extern int i915_driver_device_is_agp(struct drm_device * dev); |
0d6aa60b DA |
1017 | extern long i915_compat_ioctl(struct file *filp, unsigned int cmd, |
1018 | unsigned long arg); | |
673a394b | 1019 | extern int i915_emit_box(struct drm_device *dev, |
c4e7a414 CW |
1020 | struct drm_clip_rect *box, |
1021 | int DR1, int DR4); | |
f803aa55 | 1022 | extern int i915_reset(struct drm_device *dev, u8 flags); |
7648fa99 JB |
1023 | extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv); |
1024 | extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv); | |
1025 | extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv); | |
1026 | extern void i915_update_gfx_val(struct drm_i915_private *dev_priv); | |
1027 | ||
af6061af | 1028 | |
1da177e4 | 1029 | /* i915_irq.c */ |
f65d9421 | 1030 | void i915_hangcheck_elapsed(unsigned long data); |
527f9e90 | 1031 | void i915_handle_error(struct drm_device *dev, bool wedged); |
c153f45f EA |
1032 | extern int i915_irq_emit(struct drm_device *dev, void *data, |
1033 | struct drm_file *file_priv); | |
1034 | extern int i915_irq_wait(struct drm_device *dev, void *data, | |
1035 | struct drm_file *file_priv); | |
1da177e4 | 1036 | |
f71d4af4 | 1037 | extern void intel_irq_init(struct drm_device *dev); |
b1f14ad0 | 1038 | |
c153f45f EA |
1039 | extern int i915_vblank_pipe_set(struct drm_device *dev, void *data, |
1040 | struct drm_file *file_priv); | |
1041 | extern int i915_vblank_pipe_get(struct drm_device *dev, void *data, | |
1042 | struct drm_file *file_priv); | |
1043 | extern int i915_vblank_swap(struct drm_device *dev, void *data, | |
1044 | struct drm_file *file_priv); | |
1da177e4 | 1045 | |
7c463586 KP |
1046 | void |
1047 | i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask); | |
1048 | ||
1049 | void | |
1050 | i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask); | |
1051 | ||
01c66889 ZY |
1052 | void intel_enable_asle (struct drm_device *dev); |
1053 | ||
3bd3c932 CW |
1054 | #ifdef CONFIG_DEBUG_FS |
1055 | extern void i915_destroy_error_state(struct drm_device *dev); | |
1056 | #else | |
1057 | #define i915_destroy_error_state(x) | |
1058 | #endif | |
1059 | ||
7c463586 | 1060 | |
1da177e4 | 1061 | /* i915_mem.c */ |
c153f45f EA |
1062 | extern int i915_mem_alloc(struct drm_device *dev, void *data, |
1063 | struct drm_file *file_priv); | |
1064 | extern int i915_mem_free(struct drm_device *dev, void *data, | |
1065 | struct drm_file *file_priv); | |
1066 | extern int i915_mem_init_heap(struct drm_device *dev, void *data, | |
1067 | struct drm_file *file_priv); | |
1068 | extern int i915_mem_destroy_heap(struct drm_device *dev, void *data, | |
1069 | struct drm_file *file_priv); | |
1da177e4 | 1070 | extern void i915_mem_takedown(struct mem_block **heap); |
84b1fd10 | 1071 | extern void i915_mem_release(struct drm_device * dev, |
6c340eac | 1072 | struct drm_file *file_priv, struct mem_block *heap); |
673a394b EA |
1073 | /* i915_gem.c */ |
1074 | int i915_gem_init_ioctl(struct drm_device *dev, void *data, | |
1075 | struct drm_file *file_priv); | |
1076 | int i915_gem_create_ioctl(struct drm_device *dev, void *data, | |
1077 | struct drm_file *file_priv); | |
1078 | int i915_gem_pread_ioctl(struct drm_device *dev, void *data, | |
1079 | struct drm_file *file_priv); | |
1080 | int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data, | |
1081 | struct drm_file *file_priv); | |
1082 | int i915_gem_mmap_ioctl(struct drm_device *dev, void *data, | |
1083 | struct drm_file *file_priv); | |
de151cf6 JB |
1084 | int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data, |
1085 | struct drm_file *file_priv); | |
673a394b EA |
1086 | int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data, |
1087 | struct drm_file *file_priv); | |
1088 | int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data, | |
1089 | struct drm_file *file_priv); | |
1090 | int i915_gem_execbuffer(struct drm_device *dev, void *data, | |
1091 | struct drm_file *file_priv); | |
76446cac JB |
1092 | int i915_gem_execbuffer2(struct drm_device *dev, void *data, |
1093 | struct drm_file *file_priv); | |
673a394b EA |
1094 | int i915_gem_pin_ioctl(struct drm_device *dev, void *data, |
1095 | struct drm_file *file_priv); | |
1096 | int i915_gem_unpin_ioctl(struct drm_device *dev, void *data, | |
1097 | struct drm_file *file_priv); | |
1098 | int i915_gem_busy_ioctl(struct drm_device *dev, void *data, | |
1099 | struct drm_file *file_priv); | |
1100 | int i915_gem_throttle_ioctl(struct drm_device *dev, void *data, | |
1101 | struct drm_file *file_priv); | |
3ef94daa CW |
1102 | int i915_gem_madvise_ioctl(struct drm_device *dev, void *data, |
1103 | struct drm_file *file_priv); | |
673a394b EA |
1104 | int i915_gem_entervt_ioctl(struct drm_device *dev, void *data, |
1105 | struct drm_file *file_priv); | |
1106 | int i915_gem_leavevt_ioctl(struct drm_device *dev, void *data, | |
1107 | struct drm_file *file_priv); | |
1108 | int i915_gem_set_tiling(struct drm_device *dev, void *data, | |
1109 | struct drm_file *file_priv); | |
1110 | int i915_gem_get_tiling(struct drm_device *dev, void *data, | |
1111 | struct drm_file *file_priv); | |
5a125c3c EA |
1112 | int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data, |
1113 | struct drm_file *file_priv); | |
673a394b | 1114 | void i915_gem_load(struct drm_device *dev); |
673a394b | 1115 | int i915_gem_init_object(struct drm_gem_object *obj); |
db53a302 | 1116 | int __must_check i915_gem_flush_ring(struct intel_ring_buffer *ring, |
88241785 CW |
1117 | uint32_t invalidate_domains, |
1118 | uint32_t flush_domains); | |
05394f39 CW |
1119 | struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev, |
1120 | size_t size); | |
673a394b | 1121 | void i915_gem_free_object(struct drm_gem_object *obj); |
2021746e CW |
1122 | int __must_check i915_gem_object_pin(struct drm_i915_gem_object *obj, |
1123 | uint32_t alignment, | |
1124 | bool map_and_fenceable); | |
05394f39 | 1125 | void i915_gem_object_unpin(struct drm_i915_gem_object *obj); |
2021746e | 1126 | int __must_check i915_gem_object_unbind(struct drm_i915_gem_object *obj); |
05394f39 | 1127 | void i915_gem_release_mmap(struct drm_i915_gem_object *obj); |
673a394b | 1128 | void i915_gem_lastclose(struct drm_device *dev); |
f787a5f5 | 1129 | |
54cf91dc | 1130 | int __must_check i915_mutex_lock_interruptible(struct drm_device *dev); |
ce453d81 | 1131 | int __must_check i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj); |
54cf91dc | 1132 | void i915_gem_object_move_to_active(struct drm_i915_gem_object *obj, |
1ec14ad3 CW |
1133 | struct intel_ring_buffer *ring, |
1134 | u32 seqno); | |
54cf91dc | 1135 | |
ff72145b DA |
1136 | int i915_gem_dumb_create(struct drm_file *file_priv, |
1137 | struct drm_device *dev, | |
1138 | struct drm_mode_create_dumb *args); | |
1139 | int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev, | |
1140 | uint32_t handle, uint64_t *offset); | |
1141 | int i915_gem_dumb_destroy(struct drm_file *file_priv, struct drm_device *dev, | |
1142 | uint32_t handle); | |
f787a5f5 CW |
1143 | /** |
1144 | * Returns true if seq1 is later than seq2. | |
1145 | */ | |
1146 | static inline bool | |
1147 | i915_seqno_passed(uint32_t seq1, uint32_t seq2) | |
1148 | { | |
1149 | return (int32_t)(seq1 - seq2) >= 0; | |
1150 | } | |
1151 | ||
54cf91dc | 1152 | static inline u32 |
db53a302 | 1153 | i915_gem_next_request_seqno(struct intel_ring_buffer *ring) |
54cf91dc | 1154 | { |
db53a302 | 1155 | drm_i915_private_t *dev_priv = ring->dev->dev_private; |
54cf91dc CW |
1156 | return ring->outstanding_lazy_request = dev_priv->next_seqno; |
1157 | } | |
1158 | ||
d9e86c0e | 1159 | int __must_check i915_gem_object_get_fence(struct drm_i915_gem_object *obj, |
ce453d81 | 1160 | struct intel_ring_buffer *pipelined); |
d9e86c0e | 1161 | int __must_check i915_gem_object_put_fence(struct drm_i915_gem_object *obj); |
2021746e | 1162 | |
b09a1fec | 1163 | void i915_gem_retire_requests(struct drm_device *dev); |
069efc1d | 1164 | void i915_gem_reset(struct drm_device *dev); |
05394f39 | 1165 | void i915_gem_clflush_object(struct drm_i915_gem_object *obj); |
2021746e CW |
1166 | int __must_check i915_gem_object_set_domain(struct drm_i915_gem_object *obj, |
1167 | uint32_t read_domains, | |
1168 | uint32_t write_domain); | |
a8198eea | 1169 | int __must_check i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj); |
2021746e | 1170 | int __must_check i915_gem_init_ringbuffer(struct drm_device *dev); |
79e53945 | 1171 | void i915_gem_cleanup_ringbuffer(struct drm_device *dev); |
2021746e CW |
1172 | void i915_gem_do_init(struct drm_device *dev, |
1173 | unsigned long start, | |
1174 | unsigned long mappable_end, | |
1175 | unsigned long end); | |
1176 | int __must_check i915_gpu_idle(struct drm_device *dev); | |
1177 | int __must_check i915_gem_idle(struct drm_device *dev); | |
db53a302 CW |
1178 | int __must_check i915_add_request(struct intel_ring_buffer *ring, |
1179 | struct drm_file *file, | |
1180 | struct drm_i915_gem_request *request); | |
1181 | int __must_check i915_wait_request(struct intel_ring_buffer *ring, | |
ce453d81 | 1182 | uint32_t seqno); |
de151cf6 | 1183 | int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf); |
2021746e CW |
1184 | int __must_check |
1185 | i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, | |
1186 | bool write); | |
1187 | int __must_check | |
2da3b9b9 CW |
1188 | i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj, |
1189 | u32 alignment, | |
2021746e | 1190 | struct intel_ring_buffer *pipelined); |
71acb5eb | 1191 | int i915_gem_attach_phys_object(struct drm_device *dev, |
05394f39 | 1192 | struct drm_i915_gem_object *obj, |
6eeefaf3 CW |
1193 | int id, |
1194 | int align); | |
71acb5eb | 1195 | void i915_gem_detach_phys_object(struct drm_device *dev, |
05394f39 | 1196 | struct drm_i915_gem_object *obj); |
71acb5eb | 1197 | void i915_gem_free_all_phys_object(struct drm_device *dev); |
05394f39 | 1198 | void i915_gem_release(struct drm_device *dev, struct drm_file *file); |
673a394b | 1199 | |
467cffba CW |
1200 | uint32_t |
1201 | i915_gem_get_unfenced_gtt_alignment(struct drm_i915_gem_object *obj); | |
1202 | ||
e4ffd173 CW |
1203 | int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj, |
1204 | enum i915_cache_level cache_level); | |
1205 | ||
76aaf220 DV |
1206 | /* i915_gem_gtt.c */ |
1207 | void i915_gem_restore_gtt_mappings(struct drm_device *dev); | |
2021746e | 1208 | int __must_check i915_gem_gtt_bind_object(struct drm_i915_gem_object *obj); |
e4ffd173 CW |
1209 | void i915_gem_gtt_rebind_object(struct drm_i915_gem_object *obj, |
1210 | enum i915_cache_level cache_level); | |
05394f39 | 1211 | void i915_gem_gtt_unbind_object(struct drm_i915_gem_object *obj); |
76aaf220 | 1212 | |
b47eb4a2 | 1213 | /* i915_gem_evict.c */ |
2021746e CW |
1214 | int __must_check i915_gem_evict_something(struct drm_device *dev, int min_size, |
1215 | unsigned alignment, bool mappable); | |
1216 | int __must_check i915_gem_evict_everything(struct drm_device *dev, | |
1217 | bool purgeable_only); | |
1218 | int __must_check i915_gem_evict_inactive(struct drm_device *dev, | |
1219 | bool purgeable_only); | |
b47eb4a2 | 1220 | |
673a394b EA |
1221 | /* i915_gem_tiling.c */ |
1222 | void i915_gem_detect_bit_6_swizzle(struct drm_device *dev); | |
05394f39 CW |
1223 | void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj); |
1224 | void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj); | |
673a394b EA |
1225 | |
1226 | /* i915_gem_debug.c */ | |
05394f39 | 1227 | void i915_gem_dump_object(struct drm_i915_gem_object *obj, int len, |
673a394b | 1228 | const char *where, uint32_t mark); |
23bc5982 CW |
1229 | #if WATCH_LISTS |
1230 | int i915_verify_lists(struct drm_device *dev); | |
673a394b | 1231 | #else |
23bc5982 | 1232 | #define i915_verify_lists(dev) 0 |
673a394b | 1233 | #endif |
05394f39 CW |
1234 | void i915_gem_object_check_coherency(struct drm_i915_gem_object *obj, |
1235 | int handle); | |
1236 | void i915_gem_dump_object(struct drm_i915_gem_object *obj, int len, | |
673a394b | 1237 | const char *where, uint32_t mark); |
1da177e4 | 1238 | |
2017263e | 1239 | /* i915_debugfs.c */ |
27c202ad BG |
1240 | int i915_debugfs_init(struct drm_minor *minor); |
1241 | void i915_debugfs_cleanup(struct drm_minor *minor); | |
2017263e | 1242 | |
317c35d1 JB |
1243 | /* i915_suspend.c */ |
1244 | extern int i915_save_state(struct drm_device *dev); | |
1245 | extern int i915_restore_state(struct drm_device *dev); | |
0a3e67a4 JB |
1246 | |
1247 | /* i915_suspend.c */ | |
1248 | extern int i915_save_state(struct drm_device *dev); | |
1249 | extern int i915_restore_state(struct drm_device *dev); | |
317c35d1 | 1250 | |
f899fc64 CW |
1251 | /* intel_i2c.c */ |
1252 | extern int intel_setup_gmbus(struct drm_device *dev); | |
1253 | extern void intel_teardown_gmbus(struct drm_device *dev); | |
e957d772 CW |
1254 | extern void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed); |
1255 | extern void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit); | |
b8232e90 CW |
1256 | extern inline bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter) |
1257 | { | |
1258 | return container_of(adapter, struct intel_gmbus, adapter)->force_bit; | |
1259 | } | |
f899fc64 CW |
1260 | extern void intel_i2c_reset(struct drm_device *dev); |
1261 | ||
3b617967 | 1262 | /* intel_opregion.c */ |
44834a67 CW |
1263 | extern int intel_opregion_setup(struct drm_device *dev); |
1264 | #ifdef CONFIG_ACPI | |
1265 | extern void intel_opregion_init(struct drm_device *dev); | |
1266 | extern void intel_opregion_fini(struct drm_device *dev); | |
3b617967 CW |
1267 | extern void intel_opregion_asle_intr(struct drm_device *dev); |
1268 | extern void intel_opregion_gse_intr(struct drm_device *dev); | |
1269 | extern void intel_opregion_enable_asle(struct drm_device *dev); | |
65e082c9 | 1270 | #else |
44834a67 CW |
1271 | static inline void intel_opregion_init(struct drm_device *dev) { return; } |
1272 | static inline void intel_opregion_fini(struct drm_device *dev) { return; } | |
3b617967 CW |
1273 | static inline void intel_opregion_asle_intr(struct drm_device *dev) { return; } |
1274 | static inline void intel_opregion_gse_intr(struct drm_device *dev) { return; } | |
1275 | static inline void intel_opregion_enable_asle(struct drm_device *dev) { return; } | |
65e082c9 | 1276 | #endif |
8ee1c3db | 1277 | |
723bfd70 JB |
1278 | /* intel_acpi.c */ |
1279 | #ifdef CONFIG_ACPI | |
1280 | extern void intel_register_dsm_handler(void); | |
1281 | extern void intel_unregister_dsm_handler(void); | |
1282 | #else | |
1283 | static inline void intel_register_dsm_handler(void) { return; } | |
1284 | static inline void intel_unregister_dsm_handler(void) { return; } | |
1285 | #endif /* CONFIG_ACPI */ | |
1286 | ||
79e53945 JB |
1287 | /* modesetting */ |
1288 | extern void intel_modeset_init(struct drm_device *dev); | |
2c7111db | 1289 | extern void intel_modeset_gem_init(struct drm_device *dev); |
79e53945 | 1290 | extern void intel_modeset_cleanup(struct drm_device *dev); |
28d52043 | 1291 | extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state); |
ee5382ae | 1292 | extern bool intel_fbc_enabled(struct drm_device *dev); |
43a9539f | 1293 | extern void intel_disable_fbc(struct drm_device *dev); |
7648fa99 | 1294 | extern bool ironlake_set_drps(struct drm_device *dev, u8 val); |
d5bb081b | 1295 | extern void ironlake_enable_rc6(struct drm_device *dev); |
3b8d8d91 | 1296 | extern void gen6_set_rps(struct drm_device *dev, u8 val); |
3bad0781 | 1297 | extern void intel_detect_pch (struct drm_device *dev); |
e3421a18 | 1298 | extern int intel_trans_dp_port_sel (struct drm_crtc *crtc); |
3bad0781 | 1299 | |
6ef3d427 | 1300 | /* overlay */ |
3bd3c932 | 1301 | #ifdef CONFIG_DEBUG_FS |
6ef3d427 CW |
1302 | extern struct intel_overlay_error_state *intel_overlay_capture_error_state(struct drm_device *dev); |
1303 | extern void intel_overlay_print_error_state(struct seq_file *m, struct intel_overlay_error_state *error); | |
c4a1d9e4 CW |
1304 | |
1305 | extern struct intel_display_error_state *intel_display_capture_error_state(struct drm_device *dev); | |
1306 | extern void intel_display_print_error_state(struct seq_file *m, | |
1307 | struct drm_device *dev, | |
1308 | struct intel_display_error_state *error); | |
3bd3c932 | 1309 | #endif |
6ef3d427 | 1310 | |
1ec14ad3 CW |
1311 | #define LP_RING(d) (&((struct drm_i915_private *)(d))->ring[RCS]) |
1312 | ||
1313 | #define BEGIN_LP_RING(n) \ | |
1314 | intel_ring_begin(LP_RING(dev_priv), (n)) | |
1315 | ||
1316 | #define OUT_RING(x) \ | |
1317 | intel_ring_emit(LP_RING(dev_priv), x) | |
1318 | ||
1319 | #define ADVANCE_LP_RING() \ | |
1320 | intel_ring_advance(LP_RING(dev_priv)) | |
1321 | ||
546b0974 EA |
1322 | /** |
1323 | * Lock test for when it's just for synchronization of ring access. | |
1324 | * | |
1325 | * In that case, we don't need to do it when GEM is initialized as nobody else | |
1326 | * has access to the ring. | |
1327 | */ | |
05394f39 | 1328 | #define RING_LOCK_TEST_WITH_RETURN(dev, file) do { \ |
1ec14ad3 | 1329 | if (LP_RING(dev->dev_private)->obj == NULL) \ |
05394f39 | 1330 | LOCK_TEST_WITH_RETURN(dev, file); \ |
546b0974 EA |
1331 | } while (0) |
1332 | ||
b7287d80 BW |
1333 | /* On SNB platform, before reading ring registers forcewake bit |
1334 | * must be set to prevent GT core from power down and stale values being | |
1335 | * returned. | |
1336 | */ | |
fcca7926 BW |
1337 | void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv); |
1338 | void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv); | |
b7287d80 BW |
1339 | void __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv); |
1340 | ||
1341 | /* We give fast paths for the really cool registers */ | |
1342 | #define NEEDS_FORCE_WAKE(dev_priv, reg) \ | |
1343 | (((dev_priv)->info->gen >= 6) && \ | |
1344 | ((reg) < 0x40000) && \ | |
1345 | ((reg) != FORCEWAKE)) | |
cae5852d | 1346 | |
5f75377d KP |
1347 | #define __i915_read(x, y) \ |
1348 | static inline u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg) { \ | |
b7287d80 BW |
1349 | u##x val = 0; \ |
1350 | if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \ | |
fcca7926 | 1351 | gen6_gt_force_wake_get(dev_priv); \ |
b7287d80 | 1352 | val = read##y(dev_priv->regs + reg); \ |
fcca7926 | 1353 | gen6_gt_force_wake_put(dev_priv); \ |
b7287d80 BW |
1354 | } else { \ |
1355 | val = read##y(dev_priv->regs + reg); \ | |
1356 | } \ | |
db53a302 | 1357 | trace_i915_reg_rw(false, reg, val, sizeof(val)); \ |
5f75377d KP |
1358 | return val; \ |
1359 | } | |
fcca7926 | 1360 | |
5f75377d KP |
1361 | __i915_read(8, b) |
1362 | __i915_read(16, w) | |
1363 | __i915_read(32, l) | |
1364 | __i915_read(64, q) | |
1365 | #undef __i915_read | |
1366 | ||
1367 | #define __i915_write(x, y) \ | |
1368 | static inline void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val) { \ | |
db53a302 | 1369 | trace_i915_reg_rw(true, reg, val, sizeof(val)); \ |
b7287d80 BW |
1370 | if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \ |
1371 | __gen6_gt_wait_for_fifo(dev_priv); \ | |
1372 | } \ | |
5f75377d KP |
1373 | write##y(val, dev_priv->regs + reg); \ |
1374 | } | |
1375 | __i915_write(8, b) | |
1376 | __i915_write(16, w) | |
1377 | __i915_write(32, l) | |
1378 | __i915_write(64, q) | |
1379 | #undef __i915_write | |
1380 | ||
1381 | #define I915_READ8(reg) i915_read8(dev_priv, (reg)) | |
1382 | #define I915_WRITE8(reg, val) i915_write8(dev_priv, (reg), (val)) | |
1383 | ||
1384 | #define I915_READ16(reg) i915_read16(dev_priv, (reg)) | |
1385 | #define I915_WRITE16(reg, val) i915_write16(dev_priv, (reg), (val)) | |
1386 | #define I915_READ16_NOTRACE(reg) readw(dev_priv->regs + (reg)) | |
1387 | #define I915_WRITE16_NOTRACE(reg, val) writew(val, dev_priv->regs + (reg)) | |
1388 | ||
1389 | #define I915_READ(reg) i915_read32(dev_priv, (reg)) | |
1390 | #define I915_WRITE(reg, val) i915_write32(dev_priv, (reg), (val)) | |
cae5852d ZN |
1391 | #define I915_READ_NOTRACE(reg) readl(dev_priv->regs + (reg)) |
1392 | #define I915_WRITE_NOTRACE(reg, val) writel(val, dev_priv->regs + (reg)) | |
5f75377d KP |
1393 | |
1394 | #define I915_WRITE64(reg, val) i915_write64(dev_priv, (reg), (val)) | |
1395 | #define I915_READ64(reg) i915_read64(dev_priv, (reg)) | |
cae5852d ZN |
1396 | |
1397 | #define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg) | |
1398 | #define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg) | |
1399 | ||
ba4f01a3 | 1400 | |
1da177e4 | 1401 | #endif |