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1da177e4 LT |
1 | /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*- |
2 | */ | |
0d6aa60b | 3 | /* |
bc54fd1a | 4 | * |
1da177e4 LT |
5 | * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. |
6 | * All Rights Reserved. | |
bc54fd1a DA |
7 | * |
8 | * Permission is hereby granted, free of charge, to any person obtaining a | |
9 | * copy of this software and associated documentation files (the | |
10 | * "Software"), to deal in the Software without restriction, including | |
11 | * without limitation the rights to use, copy, modify, merge, publish, | |
12 | * distribute, sub license, and/or sell copies of the Software, and to | |
13 | * permit persons to whom the Software is furnished to do so, subject to | |
14 | * the following conditions: | |
15 | * | |
16 | * The above copyright notice and this permission notice (including the | |
17 | * next paragraph) shall be included in all copies or substantial portions | |
18 | * of the Software. | |
19 | * | |
20 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS | |
21 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
22 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. | |
23 | * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR | |
24 | * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, | |
25 | * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE | |
26 | * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. | |
27 | * | |
0d6aa60b | 28 | */ |
1da177e4 LT |
29 | |
30 | #ifndef _I915_DRV_H_ | |
31 | #define _I915_DRV_H_ | |
32 | ||
e9b73c67 | 33 | #include <uapi/drm/i915_drm.h> |
93b81f51 | 34 | #include <uapi/drm/drm_fourcc.h> |
e9b73c67 | 35 | |
585fb111 | 36 | #include "i915_reg.h" |
79e53945 | 37 | #include "intel_bios.h" |
8187a2b7 | 38 | #include "intel_ringbuffer.h" |
b20385f1 | 39 | #include "intel_lrc.h" |
0260c420 | 40 | #include "i915_gem_gtt.h" |
564ddb2f | 41 | #include "i915_gem_render_state.h" |
0839ccb8 | 42 | #include <linux/io-mapping.h> |
f899fc64 | 43 | #include <linux/i2c.h> |
c167a6fc | 44 | #include <linux/i2c-algo-bit.h> |
0ade6386 | 45 | #include <drm/intel-gtt.h> |
ba8286fa | 46 | #include <drm/drm_legacy.h> /* for struct drm_dma_handle */ |
d9fc9413 | 47 | #include <drm/drm_gem.h> |
aaa6fd2a | 48 | #include <linux/backlight.h> |
5cc9ed4b | 49 | #include <linux/hashtable.h> |
2911a35b | 50 | #include <linux/intel-iommu.h> |
742cbee8 | 51 | #include <linux/kref.h> |
9ee32fea | 52 | #include <linux/pm_qos.h> |
33a732f4 | 53 | #include "intel_guc.h" |
585fb111 | 54 | |
1da177e4 LT |
55 | /* General customization: |
56 | */ | |
57 | ||
1da177e4 LT |
58 | #define DRIVER_NAME "i915" |
59 | #define DRIVER_DESC "Intel Graphics" | |
80bea189 | 60 | #define DRIVER_DATE "20151010" |
1da177e4 | 61 | |
c883ef1b | 62 | #undef WARN_ON |
5f77eeb0 DV |
63 | /* Many gcc seem to no see through this and fall over :( */ |
64 | #if 0 | |
65 | #define WARN_ON(x) ({ \ | |
66 | bool __i915_warn_cond = (x); \ | |
67 | if (__builtin_constant_p(__i915_warn_cond)) \ | |
68 | BUILD_BUG_ON(__i915_warn_cond); \ | |
69 | WARN(__i915_warn_cond, "WARN_ON(" #x ")"); }) | |
70 | #else | |
4eee4920 | 71 | #define WARN_ON(x) WARN((x), "WARN_ON(%s)", #x ) |
5f77eeb0 DV |
72 | #endif |
73 | ||
cd9bfacb | 74 | #undef WARN_ON_ONCE |
4eee4920 | 75 | #define WARN_ON_ONCE(x) WARN_ONCE((x), "WARN_ON_ONCE(%s)", #x ) |
cd9bfacb | 76 | |
5f77eeb0 DV |
77 | #define MISSING_CASE(x) WARN(1, "Missing switch case (%lu) in %s\n", \ |
78 | (long) (x), __func__); | |
c883ef1b | 79 | |
e2c719b7 RC |
80 | /* Use I915_STATE_WARN(x) and I915_STATE_WARN_ON() (rather than WARN() and |
81 | * WARN_ON()) for hw state sanity checks to check for unexpected conditions | |
82 | * which may not necessarily be a user visible problem. This will either | |
83 | * WARN() or DRM_ERROR() depending on the verbose_checks moduleparam, to | |
84 | * enable distros and users to tailor their preferred amount of i915 abrt | |
85 | * spam. | |
86 | */ | |
87 | #define I915_STATE_WARN(condition, format...) ({ \ | |
88 | int __ret_warn_on = !!(condition); \ | |
89 | if (unlikely(__ret_warn_on)) { \ | |
90 | if (i915.verbose_state_checks) \ | |
2f3408c7 | 91 | WARN(1, format); \ |
e2c719b7 RC |
92 | else \ |
93 | DRM_ERROR(format); \ | |
94 | } \ | |
95 | unlikely(__ret_warn_on); \ | |
96 | }) | |
97 | ||
98 | #define I915_STATE_WARN_ON(condition) ({ \ | |
99 | int __ret_warn_on = !!(condition); \ | |
100 | if (unlikely(__ret_warn_on)) { \ | |
101 | if (i915.verbose_state_checks) \ | |
2f3408c7 | 102 | WARN(1, "WARN_ON(" #condition ")\n"); \ |
e2c719b7 RC |
103 | else \ |
104 | DRM_ERROR("WARN_ON(" #condition ")\n"); \ | |
105 | } \ | |
106 | unlikely(__ret_warn_on); \ | |
107 | }) | |
c883ef1b | 108 | |
42a8ca4c JN |
109 | static inline const char *yesno(bool v) |
110 | { | |
111 | return v ? "yes" : "no"; | |
112 | } | |
113 | ||
317c35d1 | 114 | enum pipe { |
752aa88a | 115 | INVALID_PIPE = -1, |
317c35d1 JB |
116 | PIPE_A = 0, |
117 | PIPE_B, | |
9db4a9c7 | 118 | PIPE_C, |
a57c774a AK |
119 | _PIPE_EDP, |
120 | I915_MAX_PIPES = _PIPE_EDP | |
317c35d1 | 121 | }; |
9db4a9c7 | 122 | #define pipe_name(p) ((p) + 'A') |
317c35d1 | 123 | |
a5c961d1 PZ |
124 | enum transcoder { |
125 | TRANSCODER_A = 0, | |
126 | TRANSCODER_B, | |
127 | TRANSCODER_C, | |
a57c774a AK |
128 | TRANSCODER_EDP, |
129 | I915_MAX_TRANSCODERS | |
a5c961d1 PZ |
130 | }; |
131 | #define transcoder_name(t) ((t) + 'A') | |
132 | ||
84139d1e | 133 | /* |
31409e97 MR |
134 | * I915_MAX_PLANES in the enum below is the maximum (across all platforms) |
135 | * number of planes per CRTC. Not all platforms really have this many planes, | |
136 | * which means some arrays of size I915_MAX_PLANES may have unused entries | |
137 | * between the topmost sprite plane and the cursor plane. | |
84139d1e | 138 | */ |
80824003 JB |
139 | enum plane { |
140 | PLANE_A = 0, | |
141 | PLANE_B, | |
9db4a9c7 | 142 | PLANE_C, |
31409e97 MR |
143 | PLANE_CURSOR, |
144 | I915_MAX_PLANES, | |
80824003 | 145 | }; |
9db4a9c7 | 146 | #define plane_name(p) ((p) + 'A') |
52440211 | 147 | |
d615a166 | 148 | #define sprite_name(p, s) ((p) * INTEL_INFO(dev)->num_sprites[(p)] + (s) + 'A') |
06da8da2 | 149 | |
2b139522 ED |
150 | enum port { |
151 | PORT_A = 0, | |
152 | PORT_B, | |
153 | PORT_C, | |
154 | PORT_D, | |
155 | PORT_E, | |
156 | I915_MAX_PORTS | |
157 | }; | |
158 | #define port_name(p) ((p) + 'A') | |
159 | ||
a09caddd | 160 | #define I915_NUM_PHYS_VLV 2 |
e4607fcf CML |
161 | |
162 | enum dpio_channel { | |
163 | DPIO_CH0, | |
164 | DPIO_CH1 | |
165 | }; | |
166 | ||
167 | enum dpio_phy { | |
168 | DPIO_PHY0, | |
169 | DPIO_PHY1 | |
170 | }; | |
171 | ||
b97186f0 PZ |
172 | enum intel_display_power_domain { |
173 | POWER_DOMAIN_PIPE_A, | |
174 | POWER_DOMAIN_PIPE_B, | |
175 | POWER_DOMAIN_PIPE_C, | |
176 | POWER_DOMAIN_PIPE_A_PANEL_FITTER, | |
177 | POWER_DOMAIN_PIPE_B_PANEL_FITTER, | |
178 | POWER_DOMAIN_PIPE_C_PANEL_FITTER, | |
179 | POWER_DOMAIN_TRANSCODER_A, | |
180 | POWER_DOMAIN_TRANSCODER_B, | |
181 | POWER_DOMAIN_TRANSCODER_C, | |
f52e353e | 182 | POWER_DOMAIN_TRANSCODER_EDP, |
319be8ae ID |
183 | POWER_DOMAIN_PORT_DDI_A_2_LANES, |
184 | POWER_DOMAIN_PORT_DDI_A_4_LANES, | |
185 | POWER_DOMAIN_PORT_DDI_B_2_LANES, | |
186 | POWER_DOMAIN_PORT_DDI_B_4_LANES, | |
187 | POWER_DOMAIN_PORT_DDI_C_2_LANES, | |
188 | POWER_DOMAIN_PORT_DDI_C_4_LANES, | |
189 | POWER_DOMAIN_PORT_DDI_D_2_LANES, | |
190 | POWER_DOMAIN_PORT_DDI_D_4_LANES, | |
d8e19f99 | 191 | POWER_DOMAIN_PORT_DDI_E_2_LANES, |
319be8ae ID |
192 | POWER_DOMAIN_PORT_DSI, |
193 | POWER_DOMAIN_PORT_CRT, | |
194 | POWER_DOMAIN_PORT_OTHER, | |
cdf8dd7f | 195 | POWER_DOMAIN_VGA, |
fbeeaa23 | 196 | POWER_DOMAIN_AUDIO, |
bd2bb1b9 | 197 | POWER_DOMAIN_PLLS, |
1407121a S |
198 | POWER_DOMAIN_AUX_A, |
199 | POWER_DOMAIN_AUX_B, | |
200 | POWER_DOMAIN_AUX_C, | |
201 | POWER_DOMAIN_AUX_D, | |
baa70707 | 202 | POWER_DOMAIN_INIT, |
bddc7645 ID |
203 | |
204 | POWER_DOMAIN_NUM, | |
b97186f0 PZ |
205 | }; |
206 | ||
207 | #define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A) | |
208 | #define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \ | |
209 | ((pipe) + POWER_DOMAIN_PIPE_A_PANEL_FITTER) | |
f52e353e ID |
210 | #define POWER_DOMAIN_TRANSCODER(tran) \ |
211 | ((tran) == TRANSCODER_EDP ? POWER_DOMAIN_TRANSCODER_EDP : \ | |
212 | (tran) + POWER_DOMAIN_TRANSCODER_A) | |
b97186f0 | 213 | |
1d843f9d EE |
214 | enum hpd_pin { |
215 | HPD_NONE = 0, | |
1d843f9d EE |
216 | HPD_TV = HPD_NONE, /* TV is known to be unreliable */ |
217 | HPD_CRT, | |
218 | HPD_SDVO_B, | |
219 | HPD_SDVO_C, | |
cc24fcdc | 220 | HPD_PORT_A, |
1d843f9d EE |
221 | HPD_PORT_B, |
222 | HPD_PORT_C, | |
223 | HPD_PORT_D, | |
26951caf | 224 | HPD_PORT_E, |
1d843f9d EE |
225 | HPD_NUM_PINS |
226 | }; | |
227 | ||
c91711f9 JN |
228 | #define for_each_hpd_pin(__pin) \ |
229 | for ((__pin) = (HPD_NONE + 1); (__pin) < HPD_NUM_PINS; (__pin)++) | |
230 | ||
5fcece80 JN |
231 | struct i915_hotplug { |
232 | struct work_struct hotplug_work; | |
233 | ||
234 | struct { | |
235 | unsigned long last_jiffies; | |
236 | int count; | |
237 | enum { | |
238 | HPD_ENABLED = 0, | |
239 | HPD_DISABLED = 1, | |
240 | HPD_MARK_DISABLED = 2 | |
241 | } state; | |
242 | } stats[HPD_NUM_PINS]; | |
243 | u32 event_bits; | |
244 | struct delayed_work reenable_work; | |
245 | ||
246 | struct intel_digital_port *irq_port[I915_MAX_PORTS]; | |
247 | u32 long_port_mask; | |
248 | u32 short_port_mask; | |
249 | struct work_struct dig_port_work; | |
250 | ||
251 | /* | |
252 | * if we get a HPD irq from DP and a HPD irq from non-DP | |
253 | * the non-DP HPD could block the workqueue on a mode config | |
254 | * mutex getting, that userspace may have taken. However | |
255 | * userspace is waiting on the DP workqueue to run which is | |
256 | * blocked behind the non-DP one. | |
257 | */ | |
258 | struct workqueue_struct *dp_wq; | |
259 | }; | |
260 | ||
2a2d5482 CW |
261 | #define I915_GEM_GPU_DOMAINS \ |
262 | (I915_GEM_DOMAIN_RENDER | \ | |
263 | I915_GEM_DOMAIN_SAMPLER | \ | |
264 | I915_GEM_DOMAIN_COMMAND | \ | |
265 | I915_GEM_DOMAIN_INSTRUCTION | \ | |
266 | I915_GEM_DOMAIN_VERTEX) | |
62fdfeaf | 267 | |
055e393f DL |
268 | #define for_each_pipe(__dev_priv, __p) \ |
269 | for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++) | |
dd740780 DL |
270 | #define for_each_plane(__dev_priv, __pipe, __p) \ |
271 | for ((__p) = 0; \ | |
272 | (__p) < INTEL_INFO(__dev_priv)->num_sprites[(__pipe)] + 1; \ | |
273 | (__p)++) | |
3bdcfc0c DL |
274 | #define for_each_sprite(__dev_priv, __p, __s) \ |
275 | for ((__s) = 0; \ | |
276 | (__s) < INTEL_INFO(__dev_priv)->num_sprites[(__p)]; \ | |
277 | (__s)++) | |
9db4a9c7 | 278 | |
d79b814d DL |
279 | #define for_each_crtc(dev, crtc) \ |
280 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) | |
281 | ||
27321ae8 ML |
282 | #define for_each_intel_plane(dev, intel_plane) \ |
283 | list_for_each_entry(intel_plane, \ | |
284 | &dev->mode_config.plane_list, \ | |
285 | base.head) | |
286 | ||
262cd2e1 VS |
287 | #define for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) \ |
288 | list_for_each_entry(intel_plane, \ | |
289 | &(dev)->mode_config.plane_list, \ | |
290 | base.head) \ | |
291 | if ((intel_plane)->pipe == (intel_crtc)->pipe) | |
292 | ||
d063ae48 DL |
293 | #define for_each_intel_crtc(dev, intel_crtc) \ |
294 | list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, base.head) | |
295 | ||
b2784e15 DL |
296 | #define for_each_intel_encoder(dev, intel_encoder) \ |
297 | list_for_each_entry(intel_encoder, \ | |
298 | &(dev)->mode_config.encoder_list, \ | |
299 | base.head) | |
300 | ||
3a3371ff ACO |
301 | #define for_each_intel_connector(dev, intel_connector) \ |
302 | list_for_each_entry(intel_connector, \ | |
303 | &dev->mode_config.connector_list, \ | |
304 | base.head) | |
305 | ||
6c2b7c12 DV |
306 | #define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \ |
307 | list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \ | |
308 | if ((intel_encoder)->base.crtc == (__crtc)) | |
309 | ||
53f5e3ca JB |
310 | #define for_each_connector_on_encoder(dev, __encoder, intel_connector) \ |
311 | list_for_each_entry((intel_connector), &(dev)->mode_config.connector_list, base.head) \ | |
312 | if ((intel_connector)->base.encoder == (__encoder)) | |
313 | ||
b04c5bd6 BF |
314 | #define for_each_power_domain(domain, mask) \ |
315 | for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \ | |
316 | if ((1 << (domain)) & (mask)) | |
317 | ||
e7b903d2 | 318 | struct drm_i915_private; |
ad46cb53 | 319 | struct i915_mm_struct; |
5cc9ed4b | 320 | struct i915_mmu_object; |
e7b903d2 | 321 | |
a6f766f3 CW |
322 | struct drm_i915_file_private { |
323 | struct drm_i915_private *dev_priv; | |
324 | struct drm_file *file; | |
325 | ||
326 | struct { | |
327 | spinlock_t lock; | |
328 | struct list_head request_list; | |
d0bc54f2 CW |
329 | /* 20ms is a fairly arbitrary limit (greater than the average frame time) |
330 | * chosen to prevent the CPU getting more than a frame ahead of the GPU | |
331 | * (when using lax throttling for the frontbuffer). We also use it to | |
332 | * offer free GPU waitboosts for severely congested workloads. | |
333 | */ | |
334 | #define DRM_I915_THROTTLE_JIFFIES msecs_to_jiffies(20) | |
a6f766f3 CW |
335 | } mm; |
336 | struct idr context_idr; | |
337 | ||
2e1b8730 CW |
338 | struct intel_rps_client { |
339 | struct list_head link; | |
340 | unsigned boosts; | |
341 | } rps; | |
a6f766f3 | 342 | |
2e1b8730 | 343 | struct intel_engine_cs *bsd_ring; |
a6f766f3 CW |
344 | }; |
345 | ||
46edb027 DV |
346 | enum intel_dpll_id { |
347 | DPLL_ID_PRIVATE = -1, /* non-shared dpll in use */ | |
348 | /* real shared dpll ids must be >= 0 */ | |
9cd86933 DV |
349 | DPLL_ID_PCH_PLL_A = 0, |
350 | DPLL_ID_PCH_PLL_B = 1, | |
429d47d5 | 351 | /* hsw/bdw */ |
9cd86933 DV |
352 | DPLL_ID_WRPLL1 = 0, |
353 | DPLL_ID_WRPLL2 = 1, | |
00490c22 ML |
354 | DPLL_ID_SPLL = 2, |
355 | ||
429d47d5 S |
356 | /* skl */ |
357 | DPLL_ID_SKL_DPLL1 = 0, | |
358 | DPLL_ID_SKL_DPLL2 = 1, | |
359 | DPLL_ID_SKL_DPLL3 = 2, | |
46edb027 | 360 | }; |
429d47d5 | 361 | #define I915_NUM_PLLS 3 |
46edb027 | 362 | |
5358901f | 363 | struct intel_dpll_hw_state { |
dcfc3552 | 364 | /* i9xx, pch plls */ |
66e985c0 | 365 | uint32_t dpll; |
8bcc2795 | 366 | uint32_t dpll_md; |
66e985c0 DV |
367 | uint32_t fp0; |
368 | uint32_t fp1; | |
dcfc3552 DL |
369 | |
370 | /* hsw, bdw */ | |
d452c5b6 | 371 | uint32_t wrpll; |
00490c22 | 372 | uint32_t spll; |
d1a2dc78 S |
373 | |
374 | /* skl */ | |
375 | /* | |
376 | * DPLL_CTRL1 has 6 bits for each each this DPLL. We store those in | |
71cd8423 | 377 | * lower part of ctrl1 and they get shifted into position when writing |
d1a2dc78 S |
378 | * the register. This allows us to easily compare the state to share |
379 | * the DPLL. | |
380 | */ | |
381 | uint32_t ctrl1; | |
382 | /* HDMI only, 0 when used for DP */ | |
383 | uint32_t cfgcr1, cfgcr2; | |
dfb82408 S |
384 | |
385 | /* bxt */ | |
05712c15 ID |
386 | uint32_t ebb0, ebb4, pll0, pll1, pll2, pll3, pll6, pll8, pll9, pll10, |
387 | pcsdw12; | |
5358901f DV |
388 | }; |
389 | ||
3e369b76 | 390 | struct intel_shared_dpll_config { |
1e6f2ddc | 391 | unsigned crtc_mask; /* mask of CRTCs sharing this PLL */ |
3e369b76 ACO |
392 | struct intel_dpll_hw_state hw_state; |
393 | }; | |
394 | ||
395 | struct intel_shared_dpll { | |
396 | struct intel_shared_dpll_config config; | |
8bd31e67 | 397 | |
ee7b9f93 JB |
398 | int active; /* count of number of active CRTCs (i.e. DPMS on) */ |
399 | bool on; /* is the PLL actually active? Disabled during modeset */ | |
46edb027 DV |
400 | const char *name; |
401 | /* should match the index in the dev_priv->shared_dplls array */ | |
402 | enum intel_dpll_id id; | |
96f6128c DV |
403 | /* The mode_set hook is optional and should be used together with the |
404 | * intel_prepare_shared_dpll function. */ | |
15bdd4cf DV |
405 | void (*mode_set)(struct drm_i915_private *dev_priv, |
406 | struct intel_shared_dpll *pll); | |
e7b903d2 DV |
407 | void (*enable)(struct drm_i915_private *dev_priv, |
408 | struct intel_shared_dpll *pll); | |
409 | void (*disable)(struct drm_i915_private *dev_priv, | |
410 | struct intel_shared_dpll *pll); | |
5358901f DV |
411 | bool (*get_hw_state)(struct drm_i915_private *dev_priv, |
412 | struct intel_shared_dpll *pll, | |
413 | struct intel_dpll_hw_state *hw_state); | |
ee7b9f93 | 414 | }; |
ee7b9f93 | 415 | |
429d47d5 S |
416 | #define SKL_DPLL0 0 |
417 | #define SKL_DPLL1 1 | |
418 | #define SKL_DPLL2 2 | |
419 | #define SKL_DPLL3 3 | |
420 | ||
e69d0bc1 DV |
421 | /* Used by dp and fdi links */ |
422 | struct intel_link_m_n { | |
423 | uint32_t tu; | |
424 | uint32_t gmch_m; | |
425 | uint32_t gmch_n; | |
426 | uint32_t link_m; | |
427 | uint32_t link_n; | |
428 | }; | |
429 | ||
430 | void intel_link_compute_m_n(int bpp, int nlanes, | |
431 | int pixel_clock, int link_clock, | |
432 | struct intel_link_m_n *m_n); | |
433 | ||
1da177e4 LT |
434 | /* Interface history: |
435 | * | |
436 | * 1.1: Original. | |
0d6aa60b DA |
437 | * 1.2: Add Power Management |
438 | * 1.3: Add vblank support | |
de227f5f | 439 | * 1.4: Fix cmdbuffer path, add heap destroy |
702880f2 | 440 | * 1.5: Add vblank pipe configuration |
2228ed67 MD |
441 | * 1.6: - New ioctl for scheduling buffer swaps on vertical blank |
442 | * - Support vertical blank on secondary display pipe | |
1da177e4 LT |
443 | */ |
444 | #define DRIVER_MAJOR 1 | |
2228ed67 | 445 | #define DRIVER_MINOR 6 |
1da177e4 LT |
446 | #define DRIVER_PATCHLEVEL 0 |
447 | ||
23bc5982 | 448 | #define WATCH_LISTS 0 |
673a394b | 449 | |
0a3e67a4 JB |
450 | struct opregion_header; |
451 | struct opregion_acpi; | |
452 | struct opregion_swsci; | |
453 | struct opregion_asle; | |
454 | ||
8ee1c3db | 455 | struct intel_opregion { |
115719fc WD |
456 | struct opregion_header *header; |
457 | struct opregion_acpi *acpi; | |
458 | struct opregion_swsci *swsci; | |
ebde53c7 JN |
459 | u32 swsci_gbda_sub_functions; |
460 | u32 swsci_sbcb_sub_functions; | |
115719fc WD |
461 | struct opregion_asle *asle; |
462 | void *vbt; | |
463 | u32 *lid_state; | |
91a60f20 | 464 | struct work_struct asle_work; |
8ee1c3db | 465 | }; |
44834a67 | 466 | #define OPREGION_SIZE (8*1024) |
8ee1c3db | 467 | |
6ef3d427 CW |
468 | struct intel_overlay; |
469 | struct intel_overlay_error_state; | |
470 | ||
de151cf6 | 471 | #define I915_FENCE_REG_NONE -1 |
42b5aeab VS |
472 | #define I915_MAX_NUM_FENCES 32 |
473 | /* 32 fences + sign bit for FENCE_REG_NONE */ | |
474 | #define I915_MAX_NUM_FENCE_BITS 6 | |
de151cf6 JB |
475 | |
476 | struct drm_i915_fence_reg { | |
007cc8ac | 477 | struct list_head lru_list; |
caea7476 | 478 | struct drm_i915_gem_object *obj; |
1690e1eb | 479 | int pin_count; |
de151cf6 | 480 | }; |
7c1c2871 | 481 | |
9b9d172d | 482 | struct sdvo_device_mapping { |
e957d772 | 483 | u8 initialized; |
9b9d172d | 484 | u8 dvo_port; |
485 | u8 slave_addr; | |
486 | u8 dvo_wiring; | |
e957d772 | 487 | u8 i2c_pin; |
b1083333 | 488 | u8 ddc_pin; |
9b9d172d | 489 | }; |
490 | ||
c4a1d9e4 CW |
491 | struct intel_display_error_state; |
492 | ||
63eeaf38 | 493 | struct drm_i915_error_state { |
742cbee8 | 494 | struct kref ref; |
585b0288 BW |
495 | struct timeval time; |
496 | ||
cb383002 | 497 | char error_msg[128]; |
eb5be9d0 | 498 | int iommu; |
48b031e3 | 499 | u32 reset_count; |
62d5d69b | 500 | u32 suspend_count; |
cb383002 | 501 | |
585b0288 | 502 | /* Generic register state */ |
63eeaf38 JB |
503 | u32 eir; |
504 | u32 pgtbl_er; | |
be998e2e | 505 | u32 ier; |
885ea5a8 | 506 | u32 gtier[4]; |
b9a3906b | 507 | u32 ccid; |
0f3b6849 CW |
508 | u32 derrmr; |
509 | u32 forcewake; | |
585b0288 BW |
510 | u32 error; /* gen6+ */ |
511 | u32 err_int; /* gen7 */ | |
6c826f34 MK |
512 | u32 fault_data0; /* gen8, gen9 */ |
513 | u32 fault_data1; /* gen8, gen9 */ | |
585b0288 | 514 | u32 done_reg; |
91ec5d11 BW |
515 | u32 gac_eco; |
516 | u32 gam_ecochk; | |
517 | u32 gab_ctl; | |
518 | u32 gfx_mode; | |
585b0288 | 519 | u32 extra_instdone[I915_NUM_INSTDONE_REG]; |
585b0288 BW |
520 | u64 fence[I915_MAX_NUM_FENCES]; |
521 | struct intel_overlay_error_state *overlay; | |
522 | struct intel_display_error_state *display; | |
0ca36d78 | 523 | struct drm_i915_error_object *semaphore_obj; |
585b0288 | 524 | |
52d39a21 | 525 | struct drm_i915_error_ring { |
372fbb8e | 526 | bool valid; |
362b8af7 BW |
527 | /* Software tracked state */ |
528 | bool waiting; | |
529 | int hangcheck_score; | |
530 | enum intel_ring_hangcheck_action hangcheck_action; | |
531 | int num_requests; | |
532 | ||
533 | /* our own tracking of ring head and tail */ | |
534 | u32 cpu_ring_head; | |
535 | u32 cpu_ring_tail; | |
536 | ||
537 | u32 semaphore_seqno[I915_NUM_RINGS - 1]; | |
538 | ||
539 | /* Register state */ | |
94f8cf10 | 540 | u32 start; |
362b8af7 BW |
541 | u32 tail; |
542 | u32 head; | |
543 | u32 ctl; | |
544 | u32 hws; | |
545 | u32 ipeir; | |
546 | u32 ipehr; | |
547 | u32 instdone; | |
362b8af7 BW |
548 | u32 bbstate; |
549 | u32 instpm; | |
550 | u32 instps; | |
551 | u32 seqno; | |
552 | u64 bbaddr; | |
50877445 | 553 | u64 acthd; |
362b8af7 | 554 | u32 fault_reg; |
13ffadd1 | 555 | u64 faddr; |
362b8af7 BW |
556 | u32 rc_psmi; /* sleep state */ |
557 | u32 semaphore_mboxes[I915_NUM_RINGS - 1]; | |
558 | ||
52d39a21 CW |
559 | struct drm_i915_error_object { |
560 | int page_count; | |
e1f12325 | 561 | u64 gtt_offset; |
52d39a21 | 562 | u32 *pages[0]; |
ab0e7ff9 | 563 | } *ringbuffer, *batchbuffer, *wa_batchbuffer, *ctx, *hws_page; |
362b8af7 | 564 | |
52d39a21 CW |
565 | struct drm_i915_error_request { |
566 | long jiffies; | |
567 | u32 seqno; | |
ee4f42b1 | 568 | u32 tail; |
52d39a21 | 569 | } *requests; |
6c7a01ec BW |
570 | |
571 | struct { | |
572 | u32 gfx_mode; | |
573 | union { | |
574 | u64 pdp[4]; | |
575 | u32 pp_dir_base; | |
576 | }; | |
577 | } vm_info; | |
ab0e7ff9 CW |
578 | |
579 | pid_t pid; | |
580 | char comm[TASK_COMM_LEN]; | |
52d39a21 | 581 | } ring[I915_NUM_RINGS]; |
3a448734 | 582 | |
9df30794 | 583 | struct drm_i915_error_buffer { |
a779e5ab | 584 | u32 size; |
9df30794 | 585 | u32 name; |
b4716185 | 586 | u32 rseqno[I915_NUM_RINGS], wseqno; |
e1f12325 | 587 | u64 gtt_offset; |
9df30794 CW |
588 | u32 read_domains; |
589 | u32 write_domain; | |
4b9de737 | 590 | s32 fence_reg:I915_MAX_NUM_FENCE_BITS; |
9df30794 CW |
591 | s32 pinned:2; |
592 | u32 tiling:2; | |
593 | u32 dirty:1; | |
594 | u32 purgeable:1; | |
5cc9ed4b | 595 | u32 userptr:1; |
5d1333fc | 596 | s32 ring:4; |
f56383cb | 597 | u32 cache_level:3; |
95f5301d | 598 | } **active_bo, **pinned_bo; |
6c7a01ec | 599 | |
95f5301d | 600 | u32 *active_bo_count, *pinned_bo_count; |
3a448734 | 601 | u32 vm_count; |
63eeaf38 JB |
602 | }; |
603 | ||
7bd688cd | 604 | struct intel_connector; |
820d2d77 | 605 | struct intel_encoder; |
5cec258b | 606 | struct intel_crtc_state; |
5724dbd1 | 607 | struct intel_initial_plane_config; |
0e8ffe1b | 608 | struct intel_crtc; |
ee9300bb DV |
609 | struct intel_limit; |
610 | struct dpll; | |
b8cecdf5 | 611 | |
e70236a8 | 612 | struct drm_i915_display_funcs { |
e70236a8 JB |
613 | int (*get_display_clock_speed)(struct drm_device *dev); |
614 | int (*get_fifo_size)(struct drm_device *dev, int plane); | |
ee9300bb DV |
615 | /** |
616 | * find_dpll() - Find the best values for the PLL | |
617 | * @limit: limits for the PLL | |
618 | * @crtc: current CRTC | |
619 | * @target: target frequency in kHz | |
620 | * @refclk: reference clock frequency in kHz | |
621 | * @match_clock: if provided, @best_clock P divider must | |
622 | * match the P divider from @match_clock | |
623 | * used for LVDS downclocking | |
624 | * @best_clock: best PLL values found | |
625 | * | |
626 | * Returns true on success, false on failure. | |
627 | */ | |
628 | bool (*find_dpll)(const struct intel_limit *limit, | |
a93e255f | 629 | struct intel_crtc_state *crtc_state, |
ee9300bb DV |
630 | int target, int refclk, |
631 | struct dpll *match_clock, | |
632 | struct dpll *best_clock); | |
46ba614c | 633 | void (*update_wm)(struct drm_crtc *crtc); |
2791a16c PZ |
634 | void (*update_sprite_wm)(struct drm_plane *plane, |
635 | struct drm_crtc *crtc, | |
636 | uint32_t sprite_width, uint32_t sprite_height, | |
637 | int pixel_size, bool enable, bool scaled); | |
27c329ed ML |
638 | int (*modeset_calc_cdclk)(struct drm_atomic_state *state); |
639 | void (*modeset_commit_cdclk)(struct drm_atomic_state *state); | |
0e8ffe1b DV |
640 | /* Returns the active state of the crtc, and if the crtc is active, |
641 | * fills out the pipe-config with the hw state. */ | |
642 | bool (*get_pipe_config)(struct intel_crtc *, | |
5cec258b | 643 | struct intel_crtc_state *); |
5724dbd1 DL |
644 | void (*get_initial_plane_config)(struct intel_crtc *, |
645 | struct intel_initial_plane_config *); | |
190f68c5 ACO |
646 | int (*crtc_compute_clock)(struct intel_crtc *crtc, |
647 | struct intel_crtc_state *crtc_state); | |
76e5a89c DV |
648 | void (*crtc_enable)(struct drm_crtc *crtc); |
649 | void (*crtc_disable)(struct drm_crtc *crtc); | |
69bfe1a9 JN |
650 | void (*audio_codec_enable)(struct drm_connector *connector, |
651 | struct intel_encoder *encoder, | |
5e7234c9 | 652 | const struct drm_display_mode *adjusted_mode); |
69bfe1a9 | 653 | void (*audio_codec_disable)(struct intel_encoder *encoder); |
674cf967 | 654 | void (*fdi_link_train)(struct drm_crtc *crtc); |
6067aaea | 655 | void (*init_clock_gating)(struct drm_device *dev); |
8c9f3aaf JB |
656 | int (*queue_flip)(struct drm_device *dev, struct drm_crtc *crtc, |
657 | struct drm_framebuffer *fb, | |
ed8d1975 | 658 | struct drm_i915_gem_object *obj, |
6258fbe2 | 659 | struct drm_i915_gem_request *req, |
ed8d1975 | 660 | uint32_t flags); |
29b9bde6 DV |
661 | void (*update_primary_plane)(struct drm_crtc *crtc, |
662 | struct drm_framebuffer *fb, | |
663 | int x, int y); | |
20afbda2 | 664 | void (*hpd_irq_setup)(struct drm_device *dev); |
e70236a8 JB |
665 | /* clock updates for mode set */ |
666 | /* cursor updates */ | |
667 | /* render clock increase/decrease */ | |
668 | /* display clock increase/decrease */ | |
669 | /* pll clock increase/decrease */ | |
e70236a8 JB |
670 | }; |
671 | ||
48c1026a MK |
672 | enum forcewake_domain_id { |
673 | FW_DOMAIN_ID_RENDER = 0, | |
674 | FW_DOMAIN_ID_BLITTER, | |
675 | FW_DOMAIN_ID_MEDIA, | |
676 | ||
677 | FW_DOMAIN_ID_COUNT | |
678 | }; | |
679 | ||
680 | enum forcewake_domains { | |
681 | FORCEWAKE_RENDER = (1 << FW_DOMAIN_ID_RENDER), | |
682 | FORCEWAKE_BLITTER = (1 << FW_DOMAIN_ID_BLITTER), | |
683 | FORCEWAKE_MEDIA = (1 << FW_DOMAIN_ID_MEDIA), | |
684 | FORCEWAKE_ALL = (FORCEWAKE_RENDER | | |
685 | FORCEWAKE_BLITTER | | |
686 | FORCEWAKE_MEDIA) | |
687 | }; | |
688 | ||
907b28c5 | 689 | struct intel_uncore_funcs { |
c8d9a590 | 690 | void (*force_wake_get)(struct drm_i915_private *dev_priv, |
48c1026a | 691 | enum forcewake_domains domains); |
c8d9a590 | 692 | void (*force_wake_put)(struct drm_i915_private *dev_priv, |
48c1026a | 693 | enum forcewake_domains domains); |
0b274481 BW |
694 | |
695 | uint8_t (*mmio_readb)(struct drm_i915_private *dev_priv, off_t offset, bool trace); | |
696 | uint16_t (*mmio_readw)(struct drm_i915_private *dev_priv, off_t offset, bool trace); | |
697 | uint32_t (*mmio_readl)(struct drm_i915_private *dev_priv, off_t offset, bool trace); | |
698 | uint64_t (*mmio_readq)(struct drm_i915_private *dev_priv, off_t offset, bool trace); | |
699 | ||
700 | void (*mmio_writeb)(struct drm_i915_private *dev_priv, off_t offset, | |
701 | uint8_t val, bool trace); | |
702 | void (*mmio_writew)(struct drm_i915_private *dev_priv, off_t offset, | |
703 | uint16_t val, bool trace); | |
704 | void (*mmio_writel)(struct drm_i915_private *dev_priv, off_t offset, | |
705 | uint32_t val, bool trace); | |
706 | void (*mmio_writeq)(struct drm_i915_private *dev_priv, off_t offset, | |
707 | uint64_t val, bool trace); | |
990bbdad CW |
708 | }; |
709 | ||
907b28c5 CW |
710 | struct intel_uncore { |
711 | spinlock_t lock; /** lock is also taken in irq contexts. */ | |
712 | ||
713 | struct intel_uncore_funcs funcs; | |
714 | ||
715 | unsigned fifo_count; | |
48c1026a | 716 | enum forcewake_domains fw_domains; |
b2cff0db CW |
717 | |
718 | struct intel_uncore_forcewake_domain { | |
719 | struct drm_i915_private *i915; | |
48c1026a | 720 | enum forcewake_domain_id id; |
b2cff0db CW |
721 | unsigned wake_count; |
722 | struct timer_list timer; | |
05a2fb15 MK |
723 | u32 reg_set; |
724 | u32 val_set; | |
725 | u32 val_clear; | |
726 | u32 reg_ack; | |
727 | u32 reg_post; | |
728 | u32 val_reset; | |
b2cff0db | 729 | } fw_domain[FW_DOMAIN_ID_COUNT]; |
b2cff0db CW |
730 | }; |
731 | ||
732 | /* Iterate over initialised fw domains */ | |
733 | #define for_each_fw_domain_mask(domain__, mask__, dev_priv__, i__) \ | |
734 | for ((i__) = 0, (domain__) = &(dev_priv__)->uncore.fw_domain[0]; \ | |
735 | (i__) < FW_DOMAIN_ID_COUNT; \ | |
736 | (i__)++, (domain__) = &(dev_priv__)->uncore.fw_domain[i__]) \ | |
737 | if (((mask__) & (dev_priv__)->uncore.fw_domains) & (1 << (i__))) | |
738 | ||
739 | #define for_each_fw_domain(domain__, dev_priv__, i__) \ | |
740 | for_each_fw_domain_mask(domain__, FORCEWAKE_ALL, dev_priv__, i__) | |
907b28c5 | 741 | |
dc174300 SS |
742 | enum csr_state { |
743 | FW_UNINITIALIZED = 0, | |
744 | FW_LOADED, | |
745 | FW_FAILED | |
746 | }; | |
747 | ||
eb805623 DV |
748 | struct intel_csr { |
749 | const char *fw_path; | |
a7f749f9 | 750 | uint32_t *dmc_payload; |
eb805623 DV |
751 | uint32_t dmc_fw_size; |
752 | uint32_t mmio_count; | |
753 | uint32_t mmioaddr[8]; | |
754 | uint32_t mmiodata[8]; | |
dc174300 | 755 | enum csr_state state; |
eb805623 DV |
756 | }; |
757 | ||
79fc46df DL |
758 | #define DEV_INFO_FOR_EACH_FLAG(func, sep) \ |
759 | func(is_mobile) sep \ | |
760 | func(is_i85x) sep \ | |
761 | func(is_i915g) sep \ | |
762 | func(is_i945gm) sep \ | |
763 | func(is_g33) sep \ | |
764 | func(need_gfx_hws) sep \ | |
765 | func(is_g4x) sep \ | |
766 | func(is_pineview) sep \ | |
767 | func(is_broadwater) sep \ | |
768 | func(is_crestline) sep \ | |
769 | func(is_ivybridge) sep \ | |
770 | func(is_valleyview) sep \ | |
771 | func(is_haswell) sep \ | |
7201c0b3 | 772 | func(is_skylake) sep \ |
b833d685 | 773 | func(is_preliminary) sep \ |
79fc46df DL |
774 | func(has_fbc) sep \ |
775 | func(has_pipe_cxsr) sep \ | |
776 | func(has_hotplug) sep \ | |
777 | func(cursor_needs_physical) sep \ | |
778 | func(has_overlay) sep \ | |
779 | func(overlay_needs_physical) sep \ | |
780 | func(supports_tv) sep \ | |
dd93be58 | 781 | func(has_llc) sep \ |
30568c45 DL |
782 | func(has_ddi) sep \ |
783 | func(has_fpga_dbg) | |
c96ea64e | 784 | |
a587f779 DL |
785 | #define DEFINE_FLAG(name) u8 name:1 |
786 | #define SEP_SEMICOLON ; | |
c96ea64e | 787 | |
cfdf1fa2 | 788 | struct intel_device_info { |
10fce67a | 789 | u32 display_mmio_offset; |
87f1f465 | 790 | u16 device_id; |
7eb552ae | 791 | u8 num_pipes:3; |
d615a166 | 792 | u8 num_sprites[I915_MAX_PIPES]; |
c96c3a8c | 793 | u8 gen; |
73ae478c | 794 | u8 ring_mask; /* Rings supported by the HW */ |
a587f779 | 795 | DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG, SEP_SEMICOLON); |
a57c774a AK |
796 | /* Register offsets for the various display pipes and transcoders */ |
797 | int pipe_offsets[I915_MAX_TRANSCODERS]; | |
798 | int trans_offsets[I915_MAX_TRANSCODERS]; | |
a57c774a | 799 | int palette_offsets[I915_MAX_PIPES]; |
5efb3e28 | 800 | int cursor_offsets[I915_MAX_PIPES]; |
3873218f JM |
801 | |
802 | /* Slice/subslice/EU info */ | |
803 | u8 slice_total; | |
804 | u8 subslice_total; | |
805 | u8 subslice_per_slice; | |
806 | u8 eu_total; | |
807 | u8 eu_per_subslice; | |
b7668791 DL |
808 | /* For each slice, which subslice(s) has(have) 7 EUs (bitfield)? */ |
809 | u8 subslice_7eu[3]; | |
3873218f JM |
810 | u8 has_slice_pg:1; |
811 | u8 has_subslice_pg:1; | |
812 | u8 has_eu_pg:1; | |
cfdf1fa2 KH |
813 | }; |
814 | ||
a587f779 DL |
815 | #undef DEFINE_FLAG |
816 | #undef SEP_SEMICOLON | |
817 | ||
7faf1ab2 DV |
818 | enum i915_cache_level { |
819 | I915_CACHE_NONE = 0, | |
350ec881 CW |
820 | I915_CACHE_LLC, /* also used for snoopable memory on non-LLC */ |
821 | I915_CACHE_L3_LLC, /* gen7+, L3 sits between the domain specifc | |
822 | caches, eg sampler/render caches, and the | |
823 | large Last-Level-Cache. LLC is coherent with | |
824 | the CPU, but L3 is only visible to the GPU. */ | |
651d794f | 825 | I915_CACHE_WT, /* hsw:gt3e WriteThrough for scanouts */ |
7faf1ab2 DV |
826 | }; |
827 | ||
e59ec13d MK |
828 | struct i915_ctx_hang_stats { |
829 | /* This context had batch pending when hang was declared */ | |
830 | unsigned batch_pending; | |
831 | ||
832 | /* This context had batch active when hang was declared */ | |
833 | unsigned batch_active; | |
be62acb4 MK |
834 | |
835 | /* Time when this context was last blamed for a GPU reset */ | |
836 | unsigned long guilty_ts; | |
837 | ||
676fa572 CW |
838 | /* If the contexts causes a second GPU hang within this time, |
839 | * it is permanently banned from submitting any more work. | |
840 | */ | |
841 | unsigned long ban_period_seconds; | |
842 | ||
be62acb4 MK |
843 | /* This context is banned to submit more work */ |
844 | bool banned; | |
e59ec13d | 845 | }; |
40521054 BW |
846 | |
847 | /* This must match up with the value previously used for execbuf2.rsvd1. */ | |
821d66dd | 848 | #define DEFAULT_CONTEXT_HANDLE 0 |
b1b38278 DW |
849 | |
850 | #define CONTEXT_NO_ZEROMAP (1<<0) | |
31b7a88d OM |
851 | /** |
852 | * struct intel_context - as the name implies, represents a context. | |
853 | * @ref: reference count. | |
854 | * @user_handle: userspace tracking identity for this context. | |
855 | * @remap_slice: l3 row remapping information. | |
b1b38278 DW |
856 | * @flags: context specific flags: |
857 | * CONTEXT_NO_ZEROMAP: do not allow mapping things to page 0. | |
31b7a88d OM |
858 | * @file_priv: filp associated with this context (NULL for global default |
859 | * context). | |
860 | * @hang_stats: information about the role of this context in possible GPU | |
861 | * hangs. | |
7df113e4 | 862 | * @ppgtt: virtual memory space used by this context. |
31b7a88d OM |
863 | * @legacy_hw_ctx: render context backing object and whether it is correctly |
864 | * initialized (legacy ring submission mechanism only). | |
865 | * @link: link in the global list of contexts. | |
866 | * | |
867 | * Contexts are memory images used by the hardware to store copies of their | |
868 | * internal state. | |
869 | */ | |
273497e5 | 870 | struct intel_context { |
dce3271b | 871 | struct kref ref; |
821d66dd | 872 | int user_handle; |
3ccfd19d | 873 | uint8_t remap_slice; |
9ea4feec | 874 | struct drm_i915_private *i915; |
b1b38278 | 875 | int flags; |
40521054 | 876 | struct drm_i915_file_private *file_priv; |
e59ec13d | 877 | struct i915_ctx_hang_stats hang_stats; |
ae6c4806 | 878 | struct i915_hw_ppgtt *ppgtt; |
a33afea5 | 879 | |
c9e003af | 880 | /* Legacy ring buffer submission */ |
ea0c76f8 OM |
881 | struct { |
882 | struct drm_i915_gem_object *rcs_state; | |
883 | bool initialized; | |
884 | } legacy_hw_ctx; | |
885 | ||
c9e003af OM |
886 | /* Execlists */ |
887 | struct { | |
888 | struct drm_i915_gem_object *state; | |
84c2377f | 889 | struct intel_ringbuffer *ringbuf; |
a7cbedec | 890 | int pin_count; |
c9e003af OM |
891 | } engine[I915_NUM_RINGS]; |
892 | ||
a33afea5 | 893 | struct list_head link; |
40521054 BW |
894 | }; |
895 | ||
a4001f1b PZ |
896 | enum fb_op_origin { |
897 | ORIGIN_GTT, | |
898 | ORIGIN_CPU, | |
899 | ORIGIN_CS, | |
900 | ORIGIN_FLIP, | |
74b4ea1e | 901 | ORIGIN_DIRTYFB, |
a4001f1b PZ |
902 | }; |
903 | ||
5c3fe8b0 | 904 | struct i915_fbc { |
25ad93fd PZ |
905 | /* This is always the inner lock when overlapping with struct_mutex and |
906 | * it's the outer lock when overlapping with stolen_lock. */ | |
907 | struct mutex lock; | |
60ee5cd2 | 908 | unsigned long uncompressed_size; |
5e59f717 | 909 | unsigned threshold; |
5c3fe8b0 | 910 | unsigned int fb_id; |
dbef0f15 PZ |
911 | unsigned int possible_framebuffer_bits; |
912 | unsigned int busy_bits; | |
e35fef21 | 913 | struct intel_crtc *crtc; |
5c3fe8b0 BW |
914 | int y; |
915 | ||
c4213885 | 916 | struct drm_mm_node compressed_fb; |
5c3fe8b0 BW |
917 | struct drm_mm_node *compressed_llb; |
918 | ||
da46f936 RV |
919 | bool false_color; |
920 | ||
9adccc60 PZ |
921 | /* Tracks whether the HW is actually enabled, not whether the feature is |
922 | * possible. */ | |
923 | bool enabled; | |
924 | ||
5c3fe8b0 BW |
925 | struct intel_fbc_work { |
926 | struct delayed_work work; | |
220285f2 | 927 | struct intel_crtc *crtc; |
5c3fe8b0 | 928 | struct drm_framebuffer *fb; |
5c3fe8b0 BW |
929 | } *fbc_work; |
930 | ||
29ebf90f CW |
931 | enum no_fbc_reason { |
932 | FBC_OK, /* FBC is enabled */ | |
933 | FBC_UNSUPPORTED, /* FBC is not supported by this chipset */ | |
5c3fe8b0 BW |
934 | FBC_NO_OUTPUT, /* no outputs enabled to compress */ |
935 | FBC_STOLEN_TOO_SMALL, /* not enough space for buffers */ | |
936 | FBC_UNSUPPORTED_MODE, /* interlace or doublescanned mode */ | |
937 | FBC_MODE_TOO_LARGE, /* mode too large for compression */ | |
938 | FBC_BAD_PLANE, /* fbc not supported on plane */ | |
939 | FBC_NOT_TILED, /* buffer not tiled */ | |
940 | FBC_MULTIPLE_PIPES, /* more than one pipe active */ | |
941 | FBC_MODULE_PARAM, | |
942 | FBC_CHIP_DEFAULT, /* disabled by default on this chip */ | |
87f5ff01 | 943 | FBC_ROTATION, /* rotation is not supported */ |
89351085 | 944 | FBC_IN_DBG_MASTER, /* kernel debugger is active */ |
adf70c65 | 945 | FBC_BAD_STRIDE, /* stride is not supported */ |
7b24c9a6 | 946 | FBC_PIXEL_RATE, /* pixel rate is too big */ |
b9e831dc | 947 | FBC_PIXEL_FORMAT /* pixel format is invalid */ |
5c3fe8b0 | 948 | } no_fbc_reason; |
ff2a3117 | 949 | |
7733b49b | 950 | bool (*fbc_enabled)(struct drm_i915_private *dev_priv); |
220285f2 | 951 | void (*enable_fbc)(struct intel_crtc *crtc); |
7733b49b | 952 | void (*disable_fbc)(struct drm_i915_private *dev_priv); |
b5e50c3f JB |
953 | }; |
954 | ||
96178eeb VK |
955 | /** |
956 | * HIGH_RR is the highest eDP panel refresh rate read from EDID | |
957 | * LOW_RR is the lowest eDP panel refresh rate found from EDID | |
958 | * parsing for same resolution. | |
959 | */ | |
960 | enum drrs_refresh_rate_type { | |
961 | DRRS_HIGH_RR, | |
962 | DRRS_LOW_RR, | |
963 | DRRS_MAX_RR, /* RR count */ | |
964 | }; | |
965 | ||
966 | enum drrs_support_type { | |
967 | DRRS_NOT_SUPPORTED = 0, | |
968 | STATIC_DRRS_SUPPORT = 1, | |
969 | SEAMLESS_DRRS_SUPPORT = 2 | |
439d7ac0 PB |
970 | }; |
971 | ||
2807cf69 | 972 | struct intel_dp; |
96178eeb VK |
973 | struct i915_drrs { |
974 | struct mutex mutex; | |
975 | struct delayed_work work; | |
976 | struct intel_dp *dp; | |
977 | unsigned busy_frontbuffer_bits; | |
978 | enum drrs_refresh_rate_type refresh_rate_type; | |
979 | enum drrs_support_type type; | |
980 | }; | |
981 | ||
a031d709 | 982 | struct i915_psr { |
f0355c4a | 983 | struct mutex lock; |
a031d709 RV |
984 | bool sink_support; |
985 | bool source_ok; | |
2807cf69 | 986 | struct intel_dp *enabled; |
7c8f8a70 RV |
987 | bool active; |
988 | struct delayed_work work; | |
9ca15301 | 989 | unsigned busy_frontbuffer_bits; |
474d1ec4 SJ |
990 | bool psr2_support; |
991 | bool aux_frame_sync; | |
3f51e471 | 992 | }; |
5c3fe8b0 | 993 | |
3bad0781 | 994 | enum intel_pch { |
f0350830 | 995 | PCH_NONE = 0, /* No PCH present */ |
3bad0781 ZW |
996 | PCH_IBX, /* Ibexpeak PCH */ |
997 | PCH_CPT, /* Cougarpoint PCH */ | |
eb877ebf | 998 | PCH_LPT, /* Lynxpoint PCH */ |
e7e7ea20 | 999 | PCH_SPT, /* Sunrisepoint PCH */ |
40c7ead9 | 1000 | PCH_NOP, |
3bad0781 ZW |
1001 | }; |
1002 | ||
988d6ee8 PZ |
1003 | enum intel_sbi_destination { |
1004 | SBI_ICLK, | |
1005 | SBI_MPHY, | |
1006 | }; | |
1007 | ||
b690e96c | 1008 | #define QUIRK_PIPEA_FORCE (1<<0) |
435793df | 1009 | #define QUIRK_LVDS_SSC_DISABLE (1<<1) |
4dca20ef | 1010 | #define QUIRK_INVERT_BRIGHTNESS (1<<2) |
9c72cc6f | 1011 | #define QUIRK_BACKLIGHT_PRESENT (1<<3) |
b6b5d049 | 1012 | #define QUIRK_PIPEB_FORCE (1<<4) |
656bfa3a | 1013 | #define QUIRK_PIN_SWIZZLED_PAGES (1<<5) |
b690e96c | 1014 | |
8be48d92 | 1015 | struct intel_fbdev; |
1630fe75 | 1016 | struct intel_fbc_work; |
38651674 | 1017 | |
c2b9152f DV |
1018 | struct intel_gmbus { |
1019 | struct i2c_adapter adapter; | |
f2ce9faf | 1020 | u32 force_bit; |
c2b9152f | 1021 | u32 reg0; |
36c785f0 | 1022 | u32 gpio_reg; |
c167a6fc | 1023 | struct i2c_algo_bit_data bit_algo; |
c2b9152f DV |
1024 | struct drm_i915_private *dev_priv; |
1025 | }; | |
1026 | ||
f4c956ad | 1027 | struct i915_suspend_saved_registers { |
e948e994 | 1028 | u32 saveDSPARB; |
ba8bbcf6 | 1029 | u32 saveLVDS; |
585fb111 JB |
1030 | u32 savePP_ON_DELAYS; |
1031 | u32 savePP_OFF_DELAYS; | |
ba8bbcf6 JB |
1032 | u32 savePP_ON; |
1033 | u32 savePP_OFF; | |
1034 | u32 savePP_CONTROL; | |
585fb111 | 1035 | u32 savePP_DIVISOR; |
ba8bbcf6 | 1036 | u32 saveFBC_CONTROL; |
1f84e550 | 1037 | u32 saveCACHE_MODE_0; |
1f84e550 | 1038 | u32 saveMI_ARB_STATE; |
ba8bbcf6 JB |
1039 | u32 saveSWF0[16]; |
1040 | u32 saveSWF1[16]; | |
85fa792b | 1041 | u32 saveSWF3[3]; |
4b9de737 | 1042 | uint64_t saveFENCE[I915_MAX_NUM_FENCES]; |
cda2bb78 | 1043 | u32 savePCH_PORT_HOTPLUG; |
9f49c376 | 1044 | u16 saveGCDGMBUS; |
f4c956ad | 1045 | }; |
c85aa885 | 1046 | |
ddeea5b0 ID |
1047 | struct vlv_s0ix_state { |
1048 | /* GAM */ | |
1049 | u32 wr_watermark; | |
1050 | u32 gfx_prio_ctrl; | |
1051 | u32 arb_mode; | |
1052 | u32 gfx_pend_tlb0; | |
1053 | u32 gfx_pend_tlb1; | |
1054 | u32 lra_limits[GEN7_LRA_LIMITS_REG_NUM]; | |
1055 | u32 media_max_req_count; | |
1056 | u32 gfx_max_req_count; | |
1057 | u32 render_hwsp; | |
1058 | u32 ecochk; | |
1059 | u32 bsd_hwsp; | |
1060 | u32 blt_hwsp; | |
1061 | u32 tlb_rd_addr; | |
1062 | ||
1063 | /* MBC */ | |
1064 | u32 g3dctl; | |
1065 | u32 gsckgctl; | |
1066 | u32 mbctl; | |
1067 | ||
1068 | /* GCP */ | |
1069 | u32 ucgctl1; | |
1070 | u32 ucgctl3; | |
1071 | u32 rcgctl1; | |
1072 | u32 rcgctl2; | |
1073 | u32 rstctl; | |
1074 | u32 misccpctl; | |
1075 | ||
1076 | /* GPM */ | |
1077 | u32 gfxpause; | |
1078 | u32 rpdeuhwtc; | |
1079 | u32 rpdeuc; | |
1080 | u32 ecobus; | |
1081 | u32 pwrdwnupctl; | |
1082 | u32 rp_down_timeout; | |
1083 | u32 rp_deucsw; | |
1084 | u32 rcubmabdtmr; | |
1085 | u32 rcedata; | |
1086 | u32 spare2gh; | |
1087 | ||
1088 | /* Display 1 CZ domain */ | |
1089 | u32 gt_imr; | |
1090 | u32 gt_ier; | |
1091 | u32 pm_imr; | |
1092 | u32 pm_ier; | |
1093 | u32 gt_scratch[GEN7_GT_SCRATCH_REG_NUM]; | |
1094 | ||
1095 | /* GT SA CZ domain */ | |
1096 | u32 tilectl; | |
1097 | u32 gt_fifoctl; | |
1098 | u32 gtlc_wake_ctrl; | |
1099 | u32 gtlc_survive; | |
1100 | u32 pmwgicz; | |
1101 | ||
1102 | /* Display 2 CZ domain */ | |
1103 | u32 gu_ctl0; | |
1104 | u32 gu_ctl1; | |
9c25210f | 1105 | u32 pcbr; |
ddeea5b0 ID |
1106 | u32 clock_gate_dis2; |
1107 | }; | |
1108 | ||
bf225f20 CW |
1109 | struct intel_rps_ei { |
1110 | u32 cz_clock; | |
1111 | u32 render_c0; | |
1112 | u32 media_c0; | |
31685c25 D |
1113 | }; |
1114 | ||
c85aa885 | 1115 | struct intel_gen6_power_mgmt { |
d4d70aa5 ID |
1116 | /* |
1117 | * work, interrupts_enabled and pm_iir are protected by | |
1118 | * dev_priv->irq_lock | |
1119 | */ | |
c85aa885 | 1120 | struct work_struct work; |
d4d70aa5 | 1121 | bool interrupts_enabled; |
c85aa885 | 1122 | u32 pm_iir; |
59cdb63d | 1123 | |
b39fb297 BW |
1124 | /* Frequencies are stored in potentially platform dependent multiples. |
1125 | * In other words, *_freq needs to be multiplied by X to be interesting. | |
1126 | * Soft limits are those which are used for the dynamic reclocking done | |
1127 | * by the driver (raise frequencies under heavy loads, and lower for | |
1128 | * lighter loads). Hard limits are those imposed by the hardware. | |
1129 | * | |
1130 | * A distinction is made for overclocking, which is never enabled by | |
1131 | * default, and is considered to be above the hard limit if it's | |
1132 | * possible at all. | |
1133 | */ | |
1134 | u8 cur_freq; /* Current frequency (cached, may not == HW) */ | |
1135 | u8 min_freq_softlimit; /* Minimum frequency permitted by the driver */ | |
1136 | u8 max_freq_softlimit; /* Max frequency permitted by the driver */ | |
1137 | u8 max_freq; /* Maximum frequency, RP0 if not overclocking */ | |
1138 | u8 min_freq; /* AKA RPn. Minimum frequency */ | |
aed242ff | 1139 | u8 idle_freq; /* Frequency to request when we are idle */ |
b39fb297 BW |
1140 | u8 efficient_freq; /* AKA RPe. Pre-determined balanced frequency */ |
1141 | u8 rp1_freq; /* "less than" RP0 power/freqency */ | |
1142 | u8 rp0_freq; /* Non-overclocked max frequency. */ | |
1a01ab3b | 1143 | |
8fb55197 CW |
1144 | u8 up_threshold; /* Current %busy required to uplock */ |
1145 | u8 down_threshold; /* Current %busy required to downclock */ | |
1146 | ||
dd75fdc8 CW |
1147 | int last_adj; |
1148 | enum { LOW_POWER, BETWEEN, HIGH_POWER } power; | |
1149 | ||
8d3afd7d CW |
1150 | spinlock_t client_lock; |
1151 | struct list_head clients; | |
1152 | bool client_boost; | |
1153 | ||
c0951f0c | 1154 | bool enabled; |
1a01ab3b | 1155 | struct delayed_work delayed_resume_work; |
1854d5ca | 1156 | unsigned boosts; |
4fc688ce | 1157 | |
2e1b8730 | 1158 | struct intel_rps_client semaphores, mmioflips; |
a6f766f3 | 1159 | |
bf225f20 CW |
1160 | /* manual wa residency calculations */ |
1161 | struct intel_rps_ei up_ei, down_ei; | |
1162 | ||
4fc688ce JB |
1163 | /* |
1164 | * Protects RPS/RC6 register access and PCU communication. | |
8d3afd7d CW |
1165 | * Must be taken after struct_mutex if nested. Note that |
1166 | * this lock may be held for long periods of time when | |
1167 | * talking to hw - so only take it when talking to hw! | |
4fc688ce JB |
1168 | */ |
1169 | struct mutex hw_lock; | |
c85aa885 DV |
1170 | }; |
1171 | ||
1a240d4d DV |
1172 | /* defined intel_pm.c */ |
1173 | extern spinlock_t mchdev_lock; | |
1174 | ||
c85aa885 DV |
1175 | struct intel_ilk_power_mgmt { |
1176 | u8 cur_delay; | |
1177 | u8 min_delay; | |
1178 | u8 max_delay; | |
1179 | u8 fmax; | |
1180 | u8 fstart; | |
1181 | ||
1182 | u64 last_count1; | |
1183 | unsigned long last_time1; | |
1184 | unsigned long chipset_power; | |
1185 | u64 last_count2; | |
5ed0bdf2 | 1186 | u64 last_time2; |
c85aa885 DV |
1187 | unsigned long gfx_power; |
1188 | u8 corr; | |
1189 | ||
1190 | int c_m; | |
1191 | int r_t; | |
1192 | }; | |
1193 | ||
c6cb582e ID |
1194 | struct drm_i915_private; |
1195 | struct i915_power_well; | |
1196 | ||
1197 | struct i915_power_well_ops { | |
1198 | /* | |
1199 | * Synchronize the well's hw state to match the current sw state, for | |
1200 | * example enable/disable it based on the current refcount. Called | |
1201 | * during driver init and resume time, possibly after first calling | |
1202 | * the enable/disable handlers. | |
1203 | */ | |
1204 | void (*sync_hw)(struct drm_i915_private *dev_priv, | |
1205 | struct i915_power_well *power_well); | |
1206 | /* | |
1207 | * Enable the well and resources that depend on it (for example | |
1208 | * interrupts located on the well). Called after the 0->1 refcount | |
1209 | * transition. | |
1210 | */ | |
1211 | void (*enable)(struct drm_i915_private *dev_priv, | |
1212 | struct i915_power_well *power_well); | |
1213 | /* | |
1214 | * Disable the well and resources that depend on it. Called after | |
1215 | * the 1->0 refcount transition. | |
1216 | */ | |
1217 | void (*disable)(struct drm_i915_private *dev_priv, | |
1218 | struct i915_power_well *power_well); | |
1219 | /* Returns the hw enabled state. */ | |
1220 | bool (*is_enabled)(struct drm_i915_private *dev_priv, | |
1221 | struct i915_power_well *power_well); | |
1222 | }; | |
1223 | ||
a38911a3 WX |
1224 | /* Power well structure for haswell */ |
1225 | struct i915_power_well { | |
c1ca727f | 1226 | const char *name; |
6f3ef5dd | 1227 | bool always_on; |
a38911a3 WX |
1228 | /* power well enable/disable usage count */ |
1229 | int count; | |
bfafe93a ID |
1230 | /* cached hw enabled state */ |
1231 | bool hw_enabled; | |
c1ca727f | 1232 | unsigned long domains; |
77961eb9 | 1233 | unsigned long data; |
c6cb582e | 1234 | const struct i915_power_well_ops *ops; |
a38911a3 WX |
1235 | }; |
1236 | ||
83c00f55 | 1237 | struct i915_power_domains { |
baa70707 ID |
1238 | /* |
1239 | * Power wells needed for initialization at driver init and suspend | |
1240 | * time are on. They are kept on until after the first modeset. | |
1241 | */ | |
1242 | bool init_power_on; | |
0d116a29 | 1243 | bool initializing; |
c1ca727f | 1244 | int power_well_count; |
baa70707 | 1245 | |
83c00f55 | 1246 | struct mutex lock; |
1da51581 | 1247 | int domain_use_count[POWER_DOMAIN_NUM]; |
c1ca727f | 1248 | struct i915_power_well *power_wells; |
83c00f55 ID |
1249 | }; |
1250 | ||
35a85ac6 | 1251 | #define MAX_L3_SLICES 2 |
a4da4fa4 | 1252 | struct intel_l3_parity { |
35a85ac6 | 1253 | u32 *remap_info[MAX_L3_SLICES]; |
a4da4fa4 | 1254 | struct work_struct error_work; |
35a85ac6 | 1255 | int which_slice; |
a4da4fa4 DV |
1256 | }; |
1257 | ||
4b5aed62 | 1258 | struct i915_gem_mm { |
4b5aed62 DV |
1259 | /** Memory allocator for GTT stolen memory */ |
1260 | struct drm_mm stolen; | |
92e97d2f PZ |
1261 | /** Protects the usage of the GTT stolen memory allocator. This is |
1262 | * always the inner lock when overlapping with struct_mutex. */ | |
1263 | struct mutex stolen_lock; | |
1264 | ||
4b5aed62 DV |
1265 | /** List of all objects in gtt_space. Used to restore gtt |
1266 | * mappings on resume */ | |
1267 | struct list_head bound_list; | |
1268 | /** | |
1269 | * List of objects which are not bound to the GTT (thus | |
1270 | * are idle and not used by the GPU) but still have | |
1271 | * (presumably uncached) pages still attached. | |
1272 | */ | |
1273 | struct list_head unbound_list; | |
1274 | ||
1275 | /** Usable portion of the GTT for GEM */ | |
1276 | unsigned long stolen_base; /* limited to low memory (32-bit) */ | |
1277 | ||
4b5aed62 DV |
1278 | /** PPGTT used for aliasing the PPGTT with the GTT */ |
1279 | struct i915_hw_ppgtt *aliasing_ppgtt; | |
1280 | ||
2cfcd32a | 1281 | struct notifier_block oom_notifier; |
ceabbba5 | 1282 | struct shrinker shrinker; |
4b5aed62 DV |
1283 | bool shrinker_no_lock_stealing; |
1284 | ||
4b5aed62 DV |
1285 | /** LRU list of objects with fence regs on them. */ |
1286 | struct list_head fence_list; | |
1287 | ||
1288 | /** | |
1289 | * We leave the user IRQ off as much as possible, | |
1290 | * but this means that requests will finish and never | |
1291 | * be retired once the system goes idle. Set a timer to | |
1292 | * fire periodically while the ring is running. When it | |
1293 | * fires, go retire requests. | |
1294 | */ | |
1295 | struct delayed_work retire_work; | |
1296 | ||
b29c19b6 CW |
1297 | /** |
1298 | * When we detect an idle GPU, we want to turn on | |
1299 | * powersaving features. So once we see that there | |
1300 | * are no more requests outstanding and no more | |
1301 | * arrive within a small period of time, we fire | |
1302 | * off the idle_work. | |
1303 | */ | |
1304 | struct delayed_work idle_work; | |
1305 | ||
4b5aed62 DV |
1306 | /** |
1307 | * Are we in a non-interruptible section of code like | |
1308 | * modesetting? | |
1309 | */ | |
1310 | bool interruptible; | |
1311 | ||
f62a0076 CW |
1312 | /** |
1313 | * Is the GPU currently considered idle, or busy executing userspace | |
1314 | * requests? Whilst idle, we attempt to power down the hardware and | |
1315 | * display clocks. In order to reduce the effect on performance, there | |
1316 | * is a slight delay before we do so. | |
1317 | */ | |
1318 | bool busy; | |
1319 | ||
bdf1e7e3 DV |
1320 | /* the indicator for dispatch video commands on two BSD rings */ |
1321 | int bsd_ring_dispatch_index; | |
1322 | ||
4b5aed62 DV |
1323 | /** Bit 6 swizzling required for X tiling */ |
1324 | uint32_t bit_6_swizzle_x; | |
1325 | /** Bit 6 swizzling required for Y tiling */ | |
1326 | uint32_t bit_6_swizzle_y; | |
1327 | ||
4b5aed62 | 1328 | /* accounting, useful for userland debugging */ |
c20e8355 | 1329 | spinlock_t object_stat_lock; |
4b5aed62 DV |
1330 | size_t object_memory; |
1331 | u32 object_count; | |
1332 | }; | |
1333 | ||
edc3d884 | 1334 | struct drm_i915_error_state_buf { |
0a4cd7c8 | 1335 | struct drm_i915_private *i915; |
edc3d884 MK |
1336 | unsigned bytes; |
1337 | unsigned size; | |
1338 | int err; | |
1339 | u8 *buf; | |
1340 | loff_t start; | |
1341 | loff_t pos; | |
1342 | }; | |
1343 | ||
fc16b48b MK |
1344 | struct i915_error_state_file_priv { |
1345 | struct drm_device *dev; | |
1346 | struct drm_i915_error_state *error; | |
1347 | }; | |
1348 | ||
99584db3 DV |
1349 | struct i915_gpu_error { |
1350 | /* For hangcheck timer */ | |
1351 | #define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */ | |
1352 | #define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD) | |
be62acb4 MK |
1353 | /* Hang gpu twice in this window and your context gets banned */ |
1354 | #define DRM_I915_CTX_BAN_PERIOD DIV_ROUND_UP(8*DRM_I915_HANGCHECK_PERIOD, 1000) | |
1355 | ||
737b1506 CW |
1356 | struct workqueue_struct *hangcheck_wq; |
1357 | struct delayed_work hangcheck_work; | |
99584db3 DV |
1358 | |
1359 | /* For reset and error_state handling. */ | |
1360 | spinlock_t lock; | |
1361 | /* Protected by the above dev->gpu_error.lock. */ | |
1362 | struct drm_i915_error_state *first_error; | |
094f9a54 CW |
1363 | |
1364 | unsigned long missed_irq_rings; | |
1365 | ||
1f83fee0 | 1366 | /** |
2ac0f450 | 1367 | * State variable controlling the reset flow and count |
1f83fee0 | 1368 | * |
2ac0f450 MK |
1369 | * This is a counter which gets incremented when reset is triggered, |
1370 | * and again when reset has been handled. So odd values (lowest bit set) | |
1371 | * means that reset is in progress and even values that | |
1372 | * (reset_counter >> 1):th reset was successfully completed. | |
1373 | * | |
1374 | * If reset is not completed succesfully, the I915_WEDGE bit is | |
1375 | * set meaning that hardware is terminally sour and there is no | |
1376 | * recovery. All waiters on the reset_queue will be woken when | |
1377 | * that happens. | |
1378 | * | |
1379 | * This counter is used by the wait_seqno code to notice that reset | |
1380 | * event happened and it needs to restart the entire ioctl (since most | |
1381 | * likely the seqno it waited for won't ever signal anytime soon). | |
f69061be DV |
1382 | * |
1383 | * This is important for lock-free wait paths, where no contended lock | |
1384 | * naturally enforces the correct ordering between the bail-out of the | |
1385 | * waiter and the gpu reset work code. | |
1f83fee0 DV |
1386 | */ |
1387 | atomic_t reset_counter; | |
1388 | ||
1f83fee0 | 1389 | #define I915_RESET_IN_PROGRESS_FLAG 1 |
2ac0f450 | 1390 | #define I915_WEDGED (1 << 31) |
1f83fee0 DV |
1391 | |
1392 | /** | |
1393 | * Waitqueue to signal when the reset has completed. Used by clients | |
1394 | * that wait for dev_priv->mm.wedged to settle. | |
1395 | */ | |
1396 | wait_queue_head_t reset_queue; | |
33196ded | 1397 | |
88b4aa87 MK |
1398 | /* Userspace knobs for gpu hang simulation; |
1399 | * combines both a ring mask, and extra flags | |
1400 | */ | |
1401 | u32 stop_rings; | |
1402 | #define I915_STOP_RING_ALLOW_BAN (1 << 31) | |
1403 | #define I915_STOP_RING_ALLOW_WARN (1 << 30) | |
094f9a54 CW |
1404 | |
1405 | /* For missed irq/seqno simulation. */ | |
1406 | unsigned int test_irq_rings; | |
6689c167 MA |
1407 | |
1408 | /* Used to prevent gem_check_wedged returning -EAGAIN during gpu reset */ | |
1409 | bool reload_in_reset; | |
99584db3 DV |
1410 | }; |
1411 | ||
b8efb17b ZR |
1412 | enum modeset_restore { |
1413 | MODESET_ON_LID_OPEN, | |
1414 | MODESET_DONE, | |
1415 | MODESET_SUSPENDED, | |
1416 | }; | |
1417 | ||
500ea70d RV |
1418 | #define DP_AUX_A 0x40 |
1419 | #define DP_AUX_B 0x10 | |
1420 | #define DP_AUX_C 0x20 | |
1421 | #define DP_AUX_D 0x30 | |
1422 | ||
11c1b657 XZ |
1423 | #define DDC_PIN_B 0x05 |
1424 | #define DDC_PIN_C 0x04 | |
1425 | #define DDC_PIN_D 0x06 | |
1426 | ||
6acab15a | 1427 | struct ddi_vbt_port_info { |
ce4dd49e DL |
1428 | /* |
1429 | * This is an index in the HDMI/DVI DDI buffer translation table. | |
1430 | * The special value HDMI_LEVEL_SHIFT_UNKNOWN means the VBT didn't | |
1431 | * populate this field. | |
1432 | */ | |
1433 | #define HDMI_LEVEL_SHIFT_UNKNOWN 0xff | |
6acab15a | 1434 | uint8_t hdmi_level_shift; |
311a2094 PZ |
1435 | |
1436 | uint8_t supports_dvi:1; | |
1437 | uint8_t supports_hdmi:1; | |
1438 | uint8_t supports_dp:1; | |
500ea70d RV |
1439 | |
1440 | uint8_t alternate_aux_channel; | |
11c1b657 | 1441 | uint8_t alternate_ddc_pin; |
75067dde AK |
1442 | |
1443 | uint8_t dp_boost_level; | |
1444 | uint8_t hdmi_boost_level; | |
6acab15a PZ |
1445 | }; |
1446 | ||
bfd7ebda RV |
1447 | enum psr_lines_to_wait { |
1448 | PSR_0_LINES_TO_WAIT = 0, | |
1449 | PSR_1_LINE_TO_WAIT, | |
1450 | PSR_4_LINES_TO_WAIT, | |
1451 | PSR_8_LINES_TO_WAIT | |
83a7280e PB |
1452 | }; |
1453 | ||
41aa3448 RV |
1454 | struct intel_vbt_data { |
1455 | struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */ | |
1456 | struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */ | |
1457 | ||
1458 | /* Feature bits */ | |
1459 | unsigned int int_tv_support:1; | |
1460 | unsigned int lvds_dither:1; | |
1461 | unsigned int lvds_vbt:1; | |
1462 | unsigned int int_crt_support:1; | |
1463 | unsigned int lvds_use_ssc:1; | |
1464 | unsigned int display_clock_mode:1; | |
1465 | unsigned int fdi_rx_polarity_inverted:1; | |
3e6bd011 | 1466 | unsigned int has_mipi:1; |
41aa3448 RV |
1467 | int lvds_ssc_freq; |
1468 | unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */ | |
1469 | ||
83a7280e PB |
1470 | enum drrs_support_type drrs_type; |
1471 | ||
41aa3448 RV |
1472 | /* eDP */ |
1473 | int edp_rate; | |
1474 | int edp_lanes; | |
1475 | int edp_preemphasis; | |
1476 | int edp_vswing; | |
1477 | bool edp_initialized; | |
1478 | bool edp_support; | |
1479 | int edp_bpp; | |
1480 | struct edp_power_seq edp_pps; | |
1481 | ||
bfd7ebda RV |
1482 | struct { |
1483 | bool full_link; | |
1484 | bool require_aux_wakeup; | |
1485 | int idle_frames; | |
1486 | enum psr_lines_to_wait lines_to_wait; | |
1487 | int tp1_wakeup_time; | |
1488 | int tp2_tp3_wakeup_time; | |
1489 | } psr; | |
1490 | ||
f00076d2 JN |
1491 | struct { |
1492 | u16 pwm_freq_hz; | |
39fbc9c8 | 1493 | bool present; |
f00076d2 | 1494 | bool active_low_pwm; |
1de6068e | 1495 | u8 min_brightness; /* min_brightness/255 of max */ |
f00076d2 JN |
1496 | } backlight; |
1497 | ||
d17c5443 SK |
1498 | /* MIPI DSI */ |
1499 | struct { | |
3e6bd011 | 1500 | u16 port; |
d17c5443 | 1501 | u16 panel_id; |
d3b542fc SK |
1502 | struct mipi_config *config; |
1503 | struct mipi_pps_data *pps; | |
1504 | u8 seq_version; | |
1505 | u32 size; | |
1506 | u8 *data; | |
1507 | u8 *sequence[MIPI_SEQ_MAX]; | |
d17c5443 SK |
1508 | } dsi; |
1509 | ||
41aa3448 RV |
1510 | int crt_ddc_pin; |
1511 | ||
1512 | int child_dev_num; | |
768f69c9 | 1513 | union child_device_config *child_dev; |
6acab15a PZ |
1514 | |
1515 | struct ddi_vbt_port_info ddi_port_info[I915_MAX_PORTS]; | |
41aa3448 RV |
1516 | }; |
1517 | ||
77c122bc VS |
1518 | enum intel_ddb_partitioning { |
1519 | INTEL_DDB_PART_1_2, | |
1520 | INTEL_DDB_PART_5_6, /* IVB+ */ | |
1521 | }; | |
1522 | ||
1fd527cc VS |
1523 | struct intel_wm_level { |
1524 | bool enable; | |
1525 | uint32_t pri_val; | |
1526 | uint32_t spr_val; | |
1527 | uint32_t cur_val; | |
1528 | uint32_t fbc_val; | |
1529 | }; | |
1530 | ||
820c1980 | 1531 | struct ilk_wm_values { |
609cedef VS |
1532 | uint32_t wm_pipe[3]; |
1533 | uint32_t wm_lp[3]; | |
1534 | uint32_t wm_lp_spr[3]; | |
1535 | uint32_t wm_linetime[3]; | |
1536 | bool enable_fbc_wm; | |
1537 | enum intel_ddb_partitioning partitioning; | |
1538 | }; | |
1539 | ||
262cd2e1 VS |
1540 | struct vlv_pipe_wm { |
1541 | uint16_t primary; | |
1542 | uint16_t sprite[2]; | |
1543 | uint8_t cursor; | |
1544 | }; | |
ae80152d | 1545 | |
262cd2e1 VS |
1546 | struct vlv_sr_wm { |
1547 | uint16_t plane; | |
1548 | uint8_t cursor; | |
1549 | }; | |
ae80152d | 1550 | |
262cd2e1 VS |
1551 | struct vlv_wm_values { |
1552 | struct vlv_pipe_wm pipe[3]; | |
1553 | struct vlv_sr_wm sr; | |
0018fda1 VS |
1554 | struct { |
1555 | uint8_t cursor; | |
1556 | uint8_t sprite[2]; | |
1557 | uint8_t primary; | |
1558 | } ddl[3]; | |
6eb1a681 VS |
1559 | uint8_t level; |
1560 | bool cxsr; | |
0018fda1 VS |
1561 | }; |
1562 | ||
c193924e | 1563 | struct skl_ddb_entry { |
16160e3d | 1564 | uint16_t start, end; /* in number of blocks, 'end' is exclusive */ |
c193924e DL |
1565 | }; |
1566 | ||
1567 | static inline uint16_t skl_ddb_entry_size(const struct skl_ddb_entry *entry) | |
1568 | { | |
16160e3d | 1569 | return entry->end - entry->start; |
c193924e DL |
1570 | } |
1571 | ||
08db6652 DL |
1572 | static inline bool skl_ddb_entry_equal(const struct skl_ddb_entry *e1, |
1573 | const struct skl_ddb_entry *e2) | |
1574 | { | |
1575 | if (e1->start == e2->start && e1->end == e2->end) | |
1576 | return true; | |
1577 | ||
1578 | return false; | |
1579 | } | |
1580 | ||
c193924e | 1581 | struct skl_ddb_allocation { |
34bb56af | 1582 | struct skl_ddb_entry pipe[I915_MAX_PIPES]; |
2cd601c6 | 1583 | struct skl_ddb_entry plane[I915_MAX_PIPES][I915_MAX_PLANES]; /* packed/uv */ |
4969d33e | 1584 | struct skl_ddb_entry y_plane[I915_MAX_PIPES][I915_MAX_PLANES]; |
c193924e DL |
1585 | }; |
1586 | ||
2ac96d2a PB |
1587 | struct skl_wm_values { |
1588 | bool dirty[I915_MAX_PIPES]; | |
c193924e | 1589 | struct skl_ddb_allocation ddb; |
2ac96d2a PB |
1590 | uint32_t wm_linetime[I915_MAX_PIPES]; |
1591 | uint32_t plane[I915_MAX_PIPES][I915_MAX_PLANES][8]; | |
2ac96d2a | 1592 | uint32_t plane_trans[I915_MAX_PIPES][I915_MAX_PLANES]; |
2ac96d2a PB |
1593 | }; |
1594 | ||
1595 | struct skl_wm_level { | |
1596 | bool plane_en[I915_MAX_PLANES]; | |
1597 | uint16_t plane_res_b[I915_MAX_PLANES]; | |
1598 | uint8_t plane_res_l[I915_MAX_PLANES]; | |
2ac96d2a PB |
1599 | }; |
1600 | ||
c67a470b | 1601 | /* |
765dab67 PZ |
1602 | * This struct helps tracking the state needed for runtime PM, which puts the |
1603 | * device in PCI D3 state. Notice that when this happens, nothing on the | |
1604 | * graphics device works, even register access, so we don't get interrupts nor | |
1605 | * anything else. | |
c67a470b | 1606 | * |
765dab67 PZ |
1607 | * Every piece of our code that needs to actually touch the hardware needs to |
1608 | * either call intel_runtime_pm_get or call intel_display_power_get with the | |
1609 | * appropriate power domain. | |
a8a8bd54 | 1610 | * |
765dab67 PZ |
1611 | * Our driver uses the autosuspend delay feature, which means we'll only really |
1612 | * suspend if we stay with zero refcount for a certain amount of time. The | |
f458ebbc | 1613 | * default value is currently very conservative (see intel_runtime_pm_enable), but |
765dab67 | 1614 | * it can be changed with the standard runtime PM files from sysfs. |
c67a470b PZ |
1615 | * |
1616 | * The irqs_disabled variable becomes true exactly after we disable the IRQs and | |
1617 | * goes back to false exactly before we reenable the IRQs. We use this variable | |
1618 | * to check if someone is trying to enable/disable IRQs while they're supposed | |
1619 | * to be disabled. This shouldn't happen and we'll print some error messages in | |
730488b2 | 1620 | * case it happens. |
c67a470b | 1621 | * |
765dab67 | 1622 | * For more, read the Documentation/power/runtime_pm.txt. |
c67a470b | 1623 | */ |
5d584b2e PZ |
1624 | struct i915_runtime_pm { |
1625 | bool suspended; | |
2aeb7d3a | 1626 | bool irqs_enabled; |
c67a470b PZ |
1627 | }; |
1628 | ||
926321d5 DV |
1629 | enum intel_pipe_crc_source { |
1630 | INTEL_PIPE_CRC_SOURCE_NONE, | |
1631 | INTEL_PIPE_CRC_SOURCE_PLANE1, | |
1632 | INTEL_PIPE_CRC_SOURCE_PLANE2, | |
1633 | INTEL_PIPE_CRC_SOURCE_PF, | |
5b3a856b | 1634 | INTEL_PIPE_CRC_SOURCE_PIPE, |
3d099a05 DV |
1635 | /* TV/DP on pre-gen5/vlv can't use the pipe source. */ |
1636 | INTEL_PIPE_CRC_SOURCE_TV, | |
1637 | INTEL_PIPE_CRC_SOURCE_DP_B, | |
1638 | INTEL_PIPE_CRC_SOURCE_DP_C, | |
1639 | INTEL_PIPE_CRC_SOURCE_DP_D, | |
46a19188 | 1640 | INTEL_PIPE_CRC_SOURCE_AUTO, |
926321d5 DV |
1641 | INTEL_PIPE_CRC_SOURCE_MAX, |
1642 | }; | |
1643 | ||
8bf1e9f1 | 1644 | struct intel_pipe_crc_entry { |
ac2300d4 | 1645 | uint32_t frame; |
8bf1e9f1 SH |
1646 | uint32_t crc[5]; |
1647 | }; | |
1648 | ||
b2c88f5b | 1649 | #define INTEL_PIPE_CRC_ENTRIES_NR 128 |
8bf1e9f1 | 1650 | struct intel_pipe_crc { |
d538bbdf DL |
1651 | spinlock_t lock; |
1652 | bool opened; /* exclusive access to the result file */ | |
e5f75aca | 1653 | struct intel_pipe_crc_entry *entries; |
926321d5 | 1654 | enum intel_pipe_crc_source source; |
d538bbdf | 1655 | int head, tail; |
07144428 | 1656 | wait_queue_head_t wq; |
8bf1e9f1 SH |
1657 | }; |
1658 | ||
f99d7069 DV |
1659 | struct i915_frontbuffer_tracking { |
1660 | struct mutex lock; | |
1661 | ||
1662 | /* | |
1663 | * Tracking bits for delayed frontbuffer flushing du to gpu activity or | |
1664 | * scheduled flips. | |
1665 | */ | |
1666 | unsigned busy_bits; | |
1667 | unsigned flip_bits; | |
1668 | }; | |
1669 | ||
7225342a MK |
1670 | struct i915_wa_reg { |
1671 | u32 addr; | |
1672 | u32 value; | |
1673 | /* bitmask representing WA bits */ | |
1674 | u32 mask; | |
1675 | }; | |
1676 | ||
1677 | #define I915_MAX_WA_REGS 16 | |
1678 | ||
1679 | struct i915_workarounds { | |
1680 | struct i915_wa_reg reg[I915_MAX_WA_REGS]; | |
1681 | u32 count; | |
1682 | }; | |
1683 | ||
cf9d2890 YZ |
1684 | struct i915_virtual_gpu { |
1685 | bool active; | |
1686 | }; | |
1687 | ||
5f19e2bf JH |
1688 | struct i915_execbuffer_params { |
1689 | struct drm_device *dev; | |
1690 | struct drm_file *file; | |
1691 | uint32_t dispatch_flags; | |
1692 | uint32_t args_batch_start_offset; | |
af98714e | 1693 | uint64_t batch_obj_vm_offset; |
5f19e2bf JH |
1694 | struct intel_engine_cs *ring; |
1695 | struct drm_i915_gem_object *batch_obj; | |
1696 | struct intel_context *ctx; | |
6a6ae79a | 1697 | struct drm_i915_gem_request *request; |
5f19e2bf JH |
1698 | }; |
1699 | ||
77fec556 | 1700 | struct drm_i915_private { |
f4c956ad | 1701 | struct drm_device *dev; |
efab6d8d | 1702 | struct kmem_cache *objects; |
e20d2ab7 | 1703 | struct kmem_cache *vmas; |
efab6d8d | 1704 | struct kmem_cache *requests; |
f4c956ad | 1705 | |
5c969aa7 | 1706 | const struct intel_device_info info; |
f4c956ad DV |
1707 | |
1708 | int relative_constants_mode; | |
1709 | ||
1710 | void __iomem *regs; | |
1711 | ||
907b28c5 | 1712 | struct intel_uncore uncore; |
f4c956ad | 1713 | |
cf9d2890 YZ |
1714 | struct i915_virtual_gpu vgpu; |
1715 | ||
33a732f4 AD |
1716 | struct intel_guc guc; |
1717 | ||
eb805623 DV |
1718 | struct intel_csr csr; |
1719 | ||
1720 | /* Display CSR-related protection */ | |
1721 | struct mutex csr_lock; | |
1722 | ||
5ea6e5e3 | 1723 | struct intel_gmbus gmbus[GMBUS_NUM_PINS]; |
28c70f16 | 1724 | |
f4c956ad DV |
1725 | /** gmbus_mutex protects against concurrent usage of the single hw gmbus |
1726 | * controller on different i2c buses. */ | |
1727 | struct mutex gmbus_mutex; | |
1728 | ||
1729 | /** | |
1730 | * Base address of the gmbus and gpio block. | |
1731 | */ | |
1732 | uint32_t gpio_mmio_base; | |
1733 | ||
b6fdd0f2 SS |
1734 | /* MMIO base address for MIPI regs */ |
1735 | uint32_t mipi_mmio_base; | |
1736 | ||
28c70f16 DV |
1737 | wait_queue_head_t gmbus_wait_queue; |
1738 | ||
f4c956ad | 1739 | struct pci_dev *bridge_dev; |
a4872ba6 | 1740 | struct intel_engine_cs ring[I915_NUM_RINGS]; |
3e78998a | 1741 | struct drm_i915_gem_object *semaphore_obj; |
f72b3435 | 1742 | uint32_t last_seqno, next_seqno; |
f4c956ad | 1743 | |
ba8286fa | 1744 | struct drm_dma_handle *status_page_dmah; |
f4c956ad DV |
1745 | struct resource mch_res; |
1746 | ||
f4c956ad DV |
1747 | /* protects the irq masks */ |
1748 | spinlock_t irq_lock; | |
1749 | ||
84c33a64 SG |
1750 | /* protects the mmio flip data */ |
1751 | spinlock_t mmio_flip_lock; | |
1752 | ||
f8b79e58 ID |
1753 | bool display_irqs_enabled; |
1754 | ||
9ee32fea DV |
1755 | /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */ |
1756 | struct pm_qos_request pm_qos; | |
1757 | ||
a580516d VS |
1758 | /* Sideband mailbox protection */ |
1759 | struct mutex sb_lock; | |
f4c956ad DV |
1760 | |
1761 | /** Cached value of IMR to avoid reads in updating the bitfield */ | |
abd58f01 BW |
1762 | union { |
1763 | u32 irq_mask; | |
1764 | u32 de_irq_mask[I915_MAX_PIPES]; | |
1765 | }; | |
f4c956ad | 1766 | u32 gt_irq_mask; |
605cd25b | 1767 | u32 pm_irq_mask; |
a6706b45 | 1768 | u32 pm_rps_events; |
91d181dd | 1769 | u32 pipestat_irq_mask[I915_MAX_PIPES]; |
f4c956ad | 1770 | |
5fcece80 | 1771 | struct i915_hotplug hotplug; |
5c3fe8b0 | 1772 | struct i915_fbc fbc; |
439d7ac0 | 1773 | struct i915_drrs drrs; |
f4c956ad | 1774 | struct intel_opregion opregion; |
41aa3448 | 1775 | struct intel_vbt_data vbt; |
f4c956ad | 1776 | |
d9ceb816 JB |
1777 | bool preserve_bios_swizzle; |
1778 | ||
f4c956ad DV |
1779 | /* overlay */ |
1780 | struct intel_overlay *overlay; | |
f4c956ad | 1781 | |
58c68779 | 1782 | /* backlight registers and fields in struct intel_panel */ |
07f11d49 | 1783 | struct mutex backlight_lock; |
31ad8ec6 | 1784 | |
f4c956ad | 1785 | /* LVDS info */ |
f4c956ad DV |
1786 | bool no_aux_handshake; |
1787 | ||
e39b999a VS |
1788 | /* protects panel power sequencer state */ |
1789 | struct mutex pps_mutex; | |
1790 | ||
f4c956ad | 1791 | struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; /* assume 965 */ |
f4c956ad DV |
1792 | int num_fence_regs; /* 8 on pre-965, 16 otherwise */ |
1793 | ||
1794 | unsigned int fsb_freq, mem_freq, is_ddr3; | |
5d96d8af | 1795 | unsigned int skl_boot_cdclk; |
44913155 | 1796 | unsigned int cdclk_freq, max_cdclk_freq; |
adafdc6f | 1797 | unsigned int max_dotclk_freq; |
6bcda4f0 | 1798 | unsigned int hpll_freq; |
bfa7df01 | 1799 | unsigned int czclk_freq; |
f4c956ad | 1800 | |
645416f5 DV |
1801 | /** |
1802 | * wq - Driver workqueue for GEM. | |
1803 | * | |
1804 | * NOTE: Work items scheduled here are not allowed to grab any modeset | |
1805 | * locks, for otherwise the flushing done in the pageflip code will | |
1806 | * result in deadlocks. | |
1807 | */ | |
f4c956ad DV |
1808 | struct workqueue_struct *wq; |
1809 | ||
1810 | /* Display functions */ | |
1811 | struct drm_i915_display_funcs display; | |
1812 | ||
1813 | /* PCH chipset type */ | |
1814 | enum intel_pch pch_type; | |
17a303ec | 1815 | unsigned short pch_id; |
f4c956ad DV |
1816 | |
1817 | unsigned long quirks; | |
1818 | ||
b8efb17b ZR |
1819 | enum modeset_restore modeset_restore; |
1820 | struct mutex modeset_restore_lock; | |
673a394b | 1821 | |
a7bbbd63 | 1822 | struct list_head vm_list; /* Global list of all address spaces */ |
0260c420 | 1823 | struct i915_gtt gtt; /* VM representing the global address space */ |
5d4545ae | 1824 | |
4b5aed62 | 1825 | struct i915_gem_mm mm; |
ad46cb53 CW |
1826 | DECLARE_HASHTABLE(mm_structs, 7); |
1827 | struct mutex mm_lock; | |
8781342d | 1828 | |
8781342d DV |
1829 | /* Kernel Modesetting */ |
1830 | ||
9b9d172d | 1831 | struct sdvo_device_mapping sdvo_mappings[2]; |
652c393a | 1832 | |
76c4ac04 DL |
1833 | struct drm_crtc *plane_to_crtc_mapping[I915_MAX_PIPES]; |
1834 | struct drm_crtc *pipe_to_crtc_mapping[I915_MAX_PIPES]; | |
6b95a207 KH |
1835 | wait_queue_head_t pending_flip_queue; |
1836 | ||
c4597872 DV |
1837 | #ifdef CONFIG_DEBUG_FS |
1838 | struct intel_pipe_crc pipe_crc[I915_MAX_PIPES]; | |
1839 | #endif | |
1840 | ||
e72f9fbf DV |
1841 | int num_shared_dpll; |
1842 | struct intel_shared_dpll shared_dplls[I915_NUM_PLLS]; | |
e4607fcf | 1843 | int dpio_phy_iosf_port[I915_NUM_PHYS_VLV]; |
ee7b9f93 | 1844 | |
7225342a | 1845 | struct i915_workarounds workarounds; |
888b5995 | 1846 | |
652c393a JB |
1847 | /* Reclocking support */ |
1848 | bool render_reclock_avail; | |
f99d7069 DV |
1849 | |
1850 | struct i915_frontbuffer_tracking fb_tracking; | |
1851 | ||
652c393a | 1852 | u16 orig_clock; |
f97108d1 | 1853 | |
c4804411 | 1854 | bool mchbar_need_disable; |
f97108d1 | 1855 | |
a4da4fa4 DV |
1856 | struct intel_l3_parity l3_parity; |
1857 | ||
59124506 BW |
1858 | /* Cannot be determined by PCIID. You must always read a register. */ |
1859 | size_t ellc_size; | |
1860 | ||
c6a828d3 | 1861 | /* gen6+ rps state */ |
c85aa885 | 1862 | struct intel_gen6_power_mgmt rps; |
c6a828d3 | 1863 | |
20e4d407 DV |
1864 | /* ilk-only ips/rps state. Everything in here is protected by the global |
1865 | * mchdev_lock in intel_pm.c */ | |
c85aa885 | 1866 | struct intel_ilk_power_mgmt ips; |
b5e50c3f | 1867 | |
83c00f55 | 1868 | struct i915_power_domains power_domains; |
a38911a3 | 1869 | |
a031d709 | 1870 | struct i915_psr psr; |
3f51e471 | 1871 | |
99584db3 | 1872 | struct i915_gpu_error gpu_error; |
ae681d96 | 1873 | |
c9cddffc JB |
1874 | struct drm_i915_gem_object *vlv_pctx; |
1875 | ||
0695726e | 1876 | #ifdef CONFIG_DRM_FBDEV_EMULATION |
8be48d92 DA |
1877 | /* list of fbdev register on this device */ |
1878 | struct intel_fbdev *fbdev; | |
82e3b8c1 | 1879 | struct work_struct fbdev_suspend_work; |
4520f53a | 1880 | #endif |
e953fd7b CW |
1881 | |
1882 | struct drm_property *broadcast_rgb_property; | |
3f43c48d | 1883 | struct drm_property *force_audio_property; |
e3689190 | 1884 | |
58fddc28 | 1885 | /* hda/i915 audio component */ |
51e1d83c | 1886 | struct i915_audio_component *audio_component; |
58fddc28 | 1887 | bool audio_component_registered; |
4a21ef7d LY |
1888 | /** |
1889 | * av_mutex - mutex for audio/video sync | |
1890 | * | |
1891 | */ | |
1892 | struct mutex av_mutex; | |
58fddc28 | 1893 | |
254f965c | 1894 | uint32_t hw_context_size; |
a33afea5 | 1895 | struct list_head context_list; |
f4c956ad | 1896 | |
3e68320e | 1897 | u32 fdi_rx_config; |
68d18ad7 | 1898 | |
70722468 VS |
1899 | u32 chv_phy_control; |
1900 | ||
842f1c8b | 1901 | u32 suspend_count; |
f4c956ad | 1902 | struct i915_suspend_saved_registers regfile; |
ddeea5b0 | 1903 | struct vlv_s0ix_state vlv_s0ix_state; |
231f42a4 | 1904 | |
53615a5e VS |
1905 | struct { |
1906 | /* | |
1907 | * Raw watermark latency values: | |
1908 | * in 0.1us units for WM0, | |
1909 | * in 0.5us units for WM1+. | |
1910 | */ | |
1911 | /* primary */ | |
1912 | uint16_t pri_latency[5]; | |
1913 | /* sprite */ | |
1914 | uint16_t spr_latency[5]; | |
1915 | /* cursor */ | |
1916 | uint16_t cur_latency[5]; | |
2af30a5c PB |
1917 | /* |
1918 | * Raw watermark memory latency values | |
1919 | * for SKL for all 8 levels | |
1920 | * in 1us units. | |
1921 | */ | |
1922 | uint16_t skl_latency[8]; | |
609cedef | 1923 | |
2d41c0b5 PB |
1924 | /* |
1925 | * The skl_wm_values structure is a bit too big for stack | |
1926 | * allocation, so we keep the staging struct where we store | |
1927 | * intermediate results here instead. | |
1928 | */ | |
1929 | struct skl_wm_values skl_results; | |
1930 | ||
609cedef | 1931 | /* current hardware state */ |
2d41c0b5 PB |
1932 | union { |
1933 | struct ilk_wm_values hw; | |
1934 | struct skl_wm_values skl_hw; | |
0018fda1 | 1935 | struct vlv_wm_values vlv; |
2d41c0b5 | 1936 | }; |
58590c14 VS |
1937 | |
1938 | uint8_t max_level; | |
53615a5e VS |
1939 | } wm; |
1940 | ||
8a187455 PZ |
1941 | struct i915_runtime_pm pm; |
1942 | ||
a83014d3 OM |
1943 | /* Abstract the submission mechanism (legacy ringbuffer or execlists) away */ |
1944 | struct { | |
5f19e2bf | 1945 | int (*execbuf_submit)(struct i915_execbuffer_params *params, |
f3dc74c0 | 1946 | struct drm_i915_gem_execbuffer2 *args, |
5f19e2bf | 1947 | struct list_head *vmas); |
a83014d3 OM |
1948 | int (*init_rings)(struct drm_device *dev); |
1949 | void (*cleanup_ring)(struct intel_engine_cs *ring); | |
1950 | void (*stop_ring)(struct intel_engine_cs *ring); | |
1951 | } gt; | |
1952 | ||
9e458034 SJ |
1953 | bool edp_low_vswing; |
1954 | ||
3be60de9 VS |
1955 | /* perform PHY state sanity checks? */ |
1956 | bool chv_phy_assert[2]; | |
1957 | ||
bdf1e7e3 DV |
1958 | /* |
1959 | * NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch | |
1960 | * will be rejected. Instead look for a better place. | |
1961 | */ | |
77fec556 | 1962 | }; |
1da177e4 | 1963 | |
2c1792a1 CW |
1964 | static inline struct drm_i915_private *to_i915(const struct drm_device *dev) |
1965 | { | |
1966 | return dev->dev_private; | |
1967 | } | |
1968 | ||
888d0d42 ID |
1969 | static inline struct drm_i915_private *dev_to_i915(struct device *dev) |
1970 | { | |
1971 | return to_i915(dev_get_drvdata(dev)); | |
1972 | } | |
1973 | ||
33a732f4 AD |
1974 | static inline struct drm_i915_private *guc_to_i915(struct intel_guc *guc) |
1975 | { | |
1976 | return container_of(guc, struct drm_i915_private, guc); | |
1977 | } | |
1978 | ||
b4519513 CW |
1979 | /* Iterate over initialised rings */ |
1980 | #define for_each_ring(ring__, dev_priv__, i__) \ | |
1981 | for ((i__) = 0; (i__) < I915_NUM_RINGS; (i__)++) \ | |
1982 | if (((ring__) = &(dev_priv__)->ring[(i__)]), intel_ring_initialized((ring__))) | |
1983 | ||
b1d7e4b4 WF |
1984 | enum hdmi_force_audio { |
1985 | HDMI_AUDIO_OFF_DVI = -2, /* no aux data for HDMI-DVI converter */ | |
1986 | HDMI_AUDIO_OFF, /* force turn off HDMI audio */ | |
1987 | HDMI_AUDIO_AUTO, /* trust EDID */ | |
1988 | HDMI_AUDIO_ON, /* force turn on HDMI audio */ | |
1989 | }; | |
1990 | ||
190d6cd5 | 1991 | #define I915_GTT_OFFSET_NONE ((u32)-1) |
ed2f3452 | 1992 | |
37e680a1 CW |
1993 | struct drm_i915_gem_object_ops { |
1994 | /* Interface between the GEM object and its backing storage. | |
1995 | * get_pages() is called once prior to the use of the associated set | |
1996 | * of pages before to binding them into the GTT, and put_pages() is | |
1997 | * called after we no longer need them. As we expect there to be | |
1998 | * associated cost with migrating pages between the backing storage | |
1999 | * and making them available for the GPU (e.g. clflush), we may hold | |
2000 | * onto the pages after they are no longer referenced by the GPU | |
2001 | * in case they may be used again shortly (for example migrating the | |
2002 | * pages to a different memory domain within the GTT). put_pages() | |
2003 | * will therefore most likely be called when the object itself is | |
2004 | * being released or under memory pressure (where we attempt to | |
2005 | * reap pages for the shrinker). | |
2006 | */ | |
2007 | int (*get_pages)(struct drm_i915_gem_object *); | |
2008 | void (*put_pages)(struct drm_i915_gem_object *); | |
5cc9ed4b CW |
2009 | int (*dmabuf_export)(struct drm_i915_gem_object *); |
2010 | void (*release)(struct drm_i915_gem_object *); | |
37e680a1 CW |
2011 | }; |
2012 | ||
a071fa00 DV |
2013 | /* |
2014 | * Frontbuffer tracking bits. Set in obj->frontbuffer_bits while a gem bo is | |
d1b9d039 | 2015 | * considered to be the frontbuffer for the given plane interface-wise. This |
a071fa00 DV |
2016 | * doesn't mean that the hw necessarily already scans it out, but that any |
2017 | * rendering (by the cpu or gpu) will land in the frontbuffer eventually. | |
2018 | * | |
2019 | * We have one bit per pipe and per scanout plane type. | |
2020 | */ | |
d1b9d039 SAK |
2021 | #define INTEL_MAX_SPRITE_BITS_PER_PIPE 5 |
2022 | #define INTEL_FRONTBUFFER_BITS_PER_PIPE 8 | |
a071fa00 DV |
2023 | #define INTEL_FRONTBUFFER_BITS \ |
2024 | (INTEL_FRONTBUFFER_BITS_PER_PIPE * I915_MAX_PIPES) | |
2025 | #define INTEL_FRONTBUFFER_PRIMARY(pipe) \ | |
2026 | (1 << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))) | |
2027 | #define INTEL_FRONTBUFFER_CURSOR(pipe) \ | |
d1b9d039 SAK |
2028 | (1 << (1 + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))) |
2029 | #define INTEL_FRONTBUFFER_SPRITE(pipe, plane) \ | |
2030 | (1 << (2 + plane + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))) | |
a071fa00 | 2031 | #define INTEL_FRONTBUFFER_OVERLAY(pipe) \ |
d1b9d039 | 2032 | (1 << (2 + INTEL_MAX_SPRITE_BITS_PER_PIPE + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))) |
cc36513c | 2033 | #define INTEL_FRONTBUFFER_ALL_MASK(pipe) \ |
d1b9d039 | 2034 | (0xff << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))) |
a071fa00 | 2035 | |
673a394b | 2036 | struct drm_i915_gem_object { |
c397b908 | 2037 | struct drm_gem_object base; |
673a394b | 2038 | |
37e680a1 CW |
2039 | const struct drm_i915_gem_object_ops *ops; |
2040 | ||
2f633156 BW |
2041 | /** List of VMAs backed by this object */ |
2042 | struct list_head vma_list; | |
2043 | ||
c1ad11fc CW |
2044 | /** Stolen memory for this object, instead of being backed by shmem. */ |
2045 | struct drm_mm_node *stolen; | |
35c20a60 | 2046 | struct list_head global_list; |
673a394b | 2047 | |
b4716185 | 2048 | struct list_head ring_list[I915_NUM_RINGS]; |
b25cb2f8 BW |
2049 | /** Used in execbuf to temporarily hold a ref */ |
2050 | struct list_head obj_exec_link; | |
673a394b | 2051 | |
8d9d5744 | 2052 | struct list_head batch_pool_link; |
493018dc | 2053 | |
673a394b | 2054 | /** |
65ce3027 CW |
2055 | * This is set if the object is on the active lists (has pending |
2056 | * rendering and so a non-zero seqno), and is not set if it i s on | |
2057 | * inactive (ready to be unbound) list. | |
673a394b | 2058 | */ |
b4716185 | 2059 | unsigned int active:I915_NUM_RINGS; |
673a394b EA |
2060 | |
2061 | /** | |
2062 | * This is set if the object has been written to since last bound | |
2063 | * to the GTT | |
2064 | */ | |
0206e353 | 2065 | unsigned int dirty:1; |
778c3544 DV |
2066 | |
2067 | /** | |
2068 | * Fence register bits (if any) for this object. Will be set | |
2069 | * as needed when mapped into the GTT. | |
2070 | * Protected by dev->struct_mutex. | |
778c3544 | 2071 | */ |
4b9de737 | 2072 | signed int fence_reg:I915_MAX_NUM_FENCE_BITS; |
778c3544 | 2073 | |
778c3544 DV |
2074 | /** |
2075 | * Advice: are the backing pages purgeable? | |
2076 | */ | |
0206e353 | 2077 | unsigned int madv:2; |
778c3544 | 2078 | |
778c3544 DV |
2079 | /** |
2080 | * Current tiling mode for the object. | |
2081 | */ | |
0206e353 | 2082 | unsigned int tiling_mode:2; |
5d82e3e6 CW |
2083 | /** |
2084 | * Whether the tiling parameters for the currently associated fence | |
2085 | * register have changed. Note that for the purposes of tracking | |
2086 | * tiling changes we also treat the unfenced register, the register | |
2087 | * slot that the object occupies whilst it executes a fenced | |
2088 | * command (such as BLT on gen2/3), as a "fence". | |
2089 | */ | |
2090 | unsigned int fence_dirty:1; | |
778c3544 | 2091 | |
75e9e915 DV |
2092 | /** |
2093 | * Is the object at the current location in the gtt mappable and | |
2094 | * fenceable? Used to avoid costly recalculations. | |
2095 | */ | |
0206e353 | 2096 | unsigned int map_and_fenceable:1; |
75e9e915 | 2097 | |
fb7d516a DV |
2098 | /** |
2099 | * Whether the current gtt mapping needs to be mappable (and isn't just | |
2100 | * mappable by accident). Track pin and fault separate for a more | |
2101 | * accurate mappable working set. | |
2102 | */ | |
0206e353 | 2103 | unsigned int fault_mappable:1; |
fb7d516a | 2104 | |
24f3a8cf AG |
2105 | /* |
2106 | * Is the object to be mapped as read-only to the GPU | |
2107 | * Only honoured if hardware has relevant pte bit | |
2108 | */ | |
2109 | unsigned long gt_ro:1; | |
651d794f | 2110 | unsigned int cache_level:3; |
0f71979a | 2111 | unsigned int cache_dirty:1; |
93dfb40c | 2112 | |
a071fa00 DV |
2113 | unsigned int frontbuffer_bits:INTEL_FRONTBUFFER_BITS; |
2114 | ||
8a0c39b1 TU |
2115 | unsigned int pin_display; |
2116 | ||
9da3da66 | 2117 | struct sg_table *pages; |
a5570178 | 2118 | int pages_pin_count; |
ee286370 CW |
2119 | struct get_page { |
2120 | struct scatterlist *sg; | |
2121 | int last; | |
2122 | } get_page; | |
673a394b | 2123 | |
1286ff73 | 2124 | /* prime dma-buf support */ |
9a70cc2a DA |
2125 | void *dma_buf_vmapping; |
2126 | int vmapping_count; | |
2127 | ||
b4716185 CW |
2128 | /** Breadcrumb of last rendering to the buffer. |
2129 | * There can only be one writer, but we allow for multiple readers. | |
2130 | * If there is a writer that necessarily implies that all other | |
2131 | * read requests are complete - but we may only be lazily clearing | |
2132 | * the read requests. A read request is naturally the most recent | |
2133 | * request on a ring, so we may have two different write and read | |
2134 | * requests on one ring where the write request is older than the | |
2135 | * read request. This allows for the CPU to read from an active | |
2136 | * buffer by only waiting for the write to complete. | |
2137 | * */ | |
2138 | struct drm_i915_gem_request *last_read_req[I915_NUM_RINGS]; | |
97b2a6a1 | 2139 | struct drm_i915_gem_request *last_write_req; |
caea7476 | 2140 | /** Breadcrumb of last fenced GPU access to the buffer. */ |
97b2a6a1 | 2141 | struct drm_i915_gem_request *last_fenced_req; |
673a394b | 2142 | |
778c3544 | 2143 | /** Current tiling stride for the object, if it's tiled. */ |
de151cf6 | 2144 | uint32_t stride; |
673a394b | 2145 | |
80075d49 DV |
2146 | /** References from framebuffers, locks out tiling changes. */ |
2147 | unsigned long framebuffer_references; | |
2148 | ||
280b713b | 2149 | /** Record of address bit 17 of each page at last unbind. */ |
d312ec25 | 2150 | unsigned long *bit_17; |
280b713b | 2151 | |
5cc9ed4b | 2152 | union { |
6a2c4232 CW |
2153 | /** for phy allocated objects */ |
2154 | struct drm_dma_handle *phys_handle; | |
2155 | ||
5cc9ed4b CW |
2156 | struct i915_gem_userptr { |
2157 | uintptr_t ptr; | |
2158 | unsigned read_only :1; | |
2159 | unsigned workers :4; | |
2160 | #define I915_GEM_USERPTR_MAX_WORKERS 15 | |
2161 | ||
ad46cb53 CW |
2162 | struct i915_mm_struct *mm; |
2163 | struct i915_mmu_object *mmu_object; | |
5cc9ed4b CW |
2164 | struct work_struct *work; |
2165 | } userptr; | |
2166 | }; | |
2167 | }; | |
62b8b215 | 2168 | #define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base) |
23010e43 | 2169 | |
a071fa00 DV |
2170 | void i915_gem_track_fb(struct drm_i915_gem_object *old, |
2171 | struct drm_i915_gem_object *new, | |
2172 | unsigned frontbuffer_bits); | |
2173 | ||
673a394b EA |
2174 | /** |
2175 | * Request queue structure. | |
2176 | * | |
2177 | * The request queue allows us to note sequence numbers that have been emitted | |
2178 | * and may be associated with active buffers to be retired. | |
2179 | * | |
97b2a6a1 JH |
2180 | * By keeping this list, we can avoid having to do questionable sequence |
2181 | * number comparisons on buffer last_read|write_seqno. It also allows an | |
2182 | * emission time to be associated with the request for tracking how far ahead | |
2183 | * of the GPU the submission is. | |
b3a38998 NH |
2184 | * |
2185 | * The requests are reference counted, so upon creation they should have an | |
2186 | * initial reference taken using kref_init | |
673a394b EA |
2187 | */ |
2188 | struct drm_i915_gem_request { | |
abfe262a JH |
2189 | struct kref ref; |
2190 | ||
852835f3 | 2191 | /** On Which ring this request was generated */ |
efab6d8d | 2192 | struct drm_i915_private *i915; |
a4872ba6 | 2193 | struct intel_engine_cs *ring; |
852835f3 | 2194 | |
673a394b EA |
2195 | /** GEM sequence number associated with this request. */ |
2196 | uint32_t seqno; | |
2197 | ||
7d736f4f MK |
2198 | /** Position in the ringbuffer of the start of the request */ |
2199 | u32 head; | |
2200 | ||
72f95afa NH |
2201 | /** |
2202 | * Position in the ringbuffer of the start of the postfix. | |
2203 | * This is required to calculate the maximum available ringbuffer | |
2204 | * space without overwriting the postfix. | |
2205 | */ | |
2206 | u32 postfix; | |
2207 | ||
2208 | /** Position in the ringbuffer of the end of the whole request */ | |
a71d8d94 CW |
2209 | u32 tail; |
2210 | ||
b3a38998 | 2211 | /** |
a8c6ecb3 | 2212 | * Context and ring buffer related to this request |
b3a38998 NH |
2213 | * Contexts are refcounted, so when this request is associated with a |
2214 | * context, we must increment the context's refcount, to guarantee that | |
2215 | * it persists while any request is linked to it. Requests themselves | |
2216 | * are also refcounted, so the request will only be freed when the last | |
2217 | * reference to it is dismissed, and the code in | |
2218 | * i915_gem_request_free() will then decrement the refcount on the | |
2219 | * context. | |
2220 | */ | |
273497e5 | 2221 | struct intel_context *ctx; |
98e1bd4a | 2222 | struct intel_ringbuffer *ringbuf; |
0e50e96b | 2223 | |
dc4be607 JH |
2224 | /** Batch buffer related to this request if any (used for |
2225 | error state dump only) */ | |
7d736f4f MK |
2226 | struct drm_i915_gem_object *batch_obj; |
2227 | ||
673a394b EA |
2228 | /** Time at which this request was emitted, in jiffies. */ |
2229 | unsigned long emitted_jiffies; | |
2230 | ||
b962442e | 2231 | /** global list entry for this request */ |
673a394b | 2232 | struct list_head list; |
b962442e | 2233 | |
f787a5f5 | 2234 | struct drm_i915_file_private *file_priv; |
b962442e EA |
2235 | /** file_priv list entry for this request */ |
2236 | struct list_head client_list; | |
67e2937b | 2237 | |
071c92de MK |
2238 | /** process identifier submitting this request */ |
2239 | struct pid *pid; | |
2240 | ||
6d3d8274 NH |
2241 | /** |
2242 | * The ELSP only accepts two elements at a time, so we queue | |
2243 | * context/tail pairs on a given queue (ring->execlist_queue) until the | |
2244 | * hardware is available. The queue serves a double purpose: we also use | |
2245 | * it to keep track of the up to 2 contexts currently in the hardware | |
2246 | * (usually one in execution and the other queued up by the GPU): We | |
2247 | * only remove elements from the head of the queue when the hardware | |
2248 | * informs us that an element has been completed. | |
2249 | * | |
2250 | * All accesses to the queue are mediated by a spinlock | |
2251 | * (ring->execlist_lock). | |
2252 | */ | |
2253 | ||
2254 | /** Execlist link in the submission queue.*/ | |
2255 | struct list_head execlist_link; | |
2256 | ||
2257 | /** Execlists no. of times this request has been sent to the ELSP */ | |
2258 | int elsp_submitted; | |
2259 | ||
673a394b EA |
2260 | }; |
2261 | ||
6689cb2b | 2262 | int i915_gem_request_alloc(struct intel_engine_cs *ring, |
217e46b5 JH |
2263 | struct intel_context *ctx, |
2264 | struct drm_i915_gem_request **req_out); | |
29b1b415 | 2265 | void i915_gem_request_cancel(struct drm_i915_gem_request *req); |
abfe262a | 2266 | void i915_gem_request_free(struct kref *req_ref); |
fcfa423c JH |
2267 | int i915_gem_request_add_to_client(struct drm_i915_gem_request *req, |
2268 | struct drm_file *file); | |
abfe262a | 2269 | |
b793a00a JH |
2270 | static inline uint32_t |
2271 | i915_gem_request_get_seqno(struct drm_i915_gem_request *req) | |
2272 | { | |
2273 | return req ? req->seqno : 0; | |
2274 | } | |
2275 | ||
2276 | static inline struct intel_engine_cs * | |
2277 | i915_gem_request_get_ring(struct drm_i915_gem_request *req) | |
2278 | { | |
2279 | return req ? req->ring : NULL; | |
2280 | } | |
2281 | ||
b2cfe0ab | 2282 | static inline struct drm_i915_gem_request * |
abfe262a JH |
2283 | i915_gem_request_reference(struct drm_i915_gem_request *req) |
2284 | { | |
b2cfe0ab CW |
2285 | if (req) |
2286 | kref_get(&req->ref); | |
2287 | return req; | |
abfe262a JH |
2288 | } |
2289 | ||
2290 | static inline void | |
2291 | i915_gem_request_unreference(struct drm_i915_gem_request *req) | |
2292 | { | |
f245860e | 2293 | WARN_ON(!mutex_is_locked(&req->ring->dev->struct_mutex)); |
abfe262a JH |
2294 | kref_put(&req->ref, i915_gem_request_free); |
2295 | } | |
2296 | ||
41037f9f CW |
2297 | static inline void |
2298 | i915_gem_request_unreference__unlocked(struct drm_i915_gem_request *req) | |
2299 | { | |
b833bb61 ML |
2300 | struct drm_device *dev; |
2301 | ||
2302 | if (!req) | |
2303 | return; | |
41037f9f | 2304 | |
b833bb61 ML |
2305 | dev = req->ring->dev; |
2306 | if (kref_put_mutex(&req->ref, i915_gem_request_free, &dev->struct_mutex)) | |
41037f9f | 2307 | mutex_unlock(&dev->struct_mutex); |
41037f9f CW |
2308 | } |
2309 | ||
abfe262a JH |
2310 | static inline void i915_gem_request_assign(struct drm_i915_gem_request **pdst, |
2311 | struct drm_i915_gem_request *src) | |
2312 | { | |
2313 | if (src) | |
2314 | i915_gem_request_reference(src); | |
2315 | ||
2316 | if (*pdst) | |
2317 | i915_gem_request_unreference(*pdst); | |
2318 | ||
2319 | *pdst = src; | |
2320 | } | |
2321 | ||
1b5a433a JH |
2322 | /* |
2323 | * XXX: i915_gem_request_completed should be here but currently needs the | |
2324 | * definition of i915_seqno_passed() which is below. It will be moved in | |
2325 | * a later patch when the call to i915_seqno_passed() is obsoleted... | |
2326 | */ | |
2327 | ||
351e3db2 BV |
2328 | /* |
2329 | * A command that requires special handling by the command parser. | |
2330 | */ | |
2331 | struct drm_i915_cmd_descriptor { | |
2332 | /* | |
2333 | * Flags describing how the command parser processes the command. | |
2334 | * | |
2335 | * CMD_DESC_FIXED: The command has a fixed length if this is set, | |
2336 | * a length mask if not set | |
2337 | * CMD_DESC_SKIP: The command is allowed but does not follow the | |
2338 | * standard length encoding for the opcode range in | |
2339 | * which it falls | |
2340 | * CMD_DESC_REJECT: The command is never allowed | |
2341 | * CMD_DESC_REGISTER: The command should be checked against the | |
2342 | * register whitelist for the appropriate ring | |
2343 | * CMD_DESC_MASTER: The command is allowed if the submitting process | |
2344 | * is the DRM master | |
2345 | */ | |
2346 | u32 flags; | |
2347 | #define CMD_DESC_FIXED (1<<0) | |
2348 | #define CMD_DESC_SKIP (1<<1) | |
2349 | #define CMD_DESC_REJECT (1<<2) | |
2350 | #define CMD_DESC_REGISTER (1<<3) | |
2351 | #define CMD_DESC_BITMASK (1<<4) | |
2352 | #define CMD_DESC_MASTER (1<<5) | |
2353 | ||
2354 | /* | |
2355 | * The command's unique identification bits and the bitmask to get them. | |
2356 | * This isn't strictly the opcode field as defined in the spec and may | |
2357 | * also include type, subtype, and/or subop fields. | |
2358 | */ | |
2359 | struct { | |
2360 | u32 value; | |
2361 | u32 mask; | |
2362 | } cmd; | |
2363 | ||
2364 | /* | |
2365 | * The command's length. The command is either fixed length (i.e. does | |
2366 | * not include a length field) or has a length field mask. The flag | |
2367 | * CMD_DESC_FIXED indicates a fixed length. Otherwise, the command has | |
2368 | * a length mask. All command entries in a command table must include | |
2369 | * length information. | |
2370 | */ | |
2371 | union { | |
2372 | u32 fixed; | |
2373 | u32 mask; | |
2374 | } length; | |
2375 | ||
2376 | /* | |
2377 | * Describes where to find a register address in the command to check | |
2378 | * against the ring's register whitelist. Only valid if flags has the | |
2379 | * CMD_DESC_REGISTER bit set. | |
6a65c5b9 FJ |
2380 | * |
2381 | * A non-zero step value implies that the command may access multiple | |
2382 | * registers in sequence (e.g. LRI), in that case step gives the | |
2383 | * distance in dwords between individual offset fields. | |
351e3db2 BV |
2384 | */ |
2385 | struct { | |
2386 | u32 offset; | |
2387 | u32 mask; | |
6a65c5b9 | 2388 | u32 step; |
351e3db2 BV |
2389 | } reg; |
2390 | ||
2391 | #define MAX_CMD_DESC_BITMASKS 3 | |
2392 | /* | |
2393 | * Describes command checks where a particular dword is masked and | |
2394 | * compared against an expected value. If the command does not match | |
2395 | * the expected value, the parser rejects it. Only valid if flags has | |
2396 | * the CMD_DESC_BITMASK bit set. Only entries where mask is non-zero | |
2397 | * are valid. | |
d4d48035 BV |
2398 | * |
2399 | * If the check specifies a non-zero condition_mask then the parser | |
2400 | * only performs the check when the bits specified by condition_mask | |
2401 | * are non-zero. | |
351e3db2 BV |
2402 | */ |
2403 | struct { | |
2404 | u32 offset; | |
2405 | u32 mask; | |
2406 | u32 expected; | |
d4d48035 BV |
2407 | u32 condition_offset; |
2408 | u32 condition_mask; | |
351e3db2 BV |
2409 | } bits[MAX_CMD_DESC_BITMASKS]; |
2410 | }; | |
2411 | ||
2412 | /* | |
2413 | * A table of commands requiring special handling by the command parser. | |
2414 | * | |
2415 | * Each ring has an array of tables. Each table consists of an array of command | |
2416 | * descriptors, which must be sorted with command opcodes in ascending order. | |
2417 | */ | |
2418 | struct drm_i915_cmd_table { | |
2419 | const struct drm_i915_cmd_descriptor *table; | |
2420 | int count; | |
2421 | }; | |
2422 | ||
dbbe9127 | 2423 | /* Note that the (struct drm_i915_private *) cast is just to shut up gcc. */ |
7312e2dd CW |
2424 | #define __I915__(p) ({ \ |
2425 | struct drm_i915_private *__p; \ | |
2426 | if (__builtin_types_compatible_p(typeof(*p), struct drm_i915_private)) \ | |
2427 | __p = (struct drm_i915_private *)p; \ | |
2428 | else if (__builtin_types_compatible_p(typeof(*p), struct drm_device)) \ | |
2429 | __p = to_i915((struct drm_device *)p); \ | |
2430 | else \ | |
2431 | BUILD_BUG(); \ | |
2432 | __p; \ | |
2433 | }) | |
dbbe9127 | 2434 | #define INTEL_INFO(p) (&__I915__(p)->info) |
87f1f465 | 2435 | #define INTEL_DEVID(p) (INTEL_INFO(p)->device_id) |
e90a21d4 | 2436 | #define INTEL_REVID(p) (__I915__(p)->dev->pdev->revision) |
cae5852d | 2437 | |
87f1f465 CW |
2438 | #define IS_I830(dev) (INTEL_DEVID(dev) == 0x3577) |
2439 | #define IS_845G(dev) (INTEL_DEVID(dev) == 0x2562) | |
cae5852d | 2440 | #define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x) |
87f1f465 | 2441 | #define IS_I865G(dev) (INTEL_DEVID(dev) == 0x2572) |
cae5852d | 2442 | #define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g) |
87f1f465 CW |
2443 | #define IS_I915GM(dev) (INTEL_DEVID(dev) == 0x2592) |
2444 | #define IS_I945G(dev) (INTEL_DEVID(dev) == 0x2772) | |
cae5852d ZN |
2445 | #define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm) |
2446 | #define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater) | |
2447 | #define IS_CRESTLINE(dev) (INTEL_INFO(dev)->is_crestline) | |
87f1f465 | 2448 | #define IS_GM45(dev) (INTEL_DEVID(dev) == 0x2A42) |
cae5852d | 2449 | #define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x) |
87f1f465 CW |
2450 | #define IS_PINEVIEW_G(dev) (INTEL_DEVID(dev) == 0xa001) |
2451 | #define IS_PINEVIEW_M(dev) (INTEL_DEVID(dev) == 0xa011) | |
cae5852d ZN |
2452 | #define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview) |
2453 | #define IS_G33(dev) (INTEL_INFO(dev)->is_g33) | |
87f1f465 | 2454 | #define IS_IRONLAKE_M(dev) (INTEL_DEVID(dev) == 0x0046) |
4b65177b | 2455 | #define IS_IVYBRIDGE(dev) (INTEL_INFO(dev)->is_ivybridge) |
87f1f465 CW |
2456 | #define IS_IVB_GT1(dev) (INTEL_DEVID(dev) == 0x0156 || \ |
2457 | INTEL_DEVID(dev) == 0x0152 || \ | |
2458 | INTEL_DEVID(dev) == 0x015a) | |
70a3eb7a | 2459 | #define IS_VALLEYVIEW(dev) (INTEL_INFO(dev)->is_valleyview) |
6df4027b | 2460 | #define IS_CHERRYVIEW(dev) (INTEL_INFO(dev)->is_valleyview && IS_GEN8(dev)) |
4cae9ae0 | 2461 | #define IS_HASWELL(dev) (INTEL_INFO(dev)->is_haswell) |
8179f1f0 | 2462 | #define IS_BROADWELL(dev) (!INTEL_INFO(dev)->is_valleyview && IS_GEN8(dev)) |
7201c0b3 | 2463 | #define IS_SKYLAKE(dev) (INTEL_INFO(dev)->is_skylake) |
1feed885 | 2464 | #define IS_BROXTON(dev) (!INTEL_INFO(dev)->is_skylake && IS_GEN9(dev)) |
cae5852d | 2465 | #define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile) |
ed1c9e2c | 2466 | #define IS_HSW_EARLY_SDV(dev) (IS_HASWELL(dev) && \ |
87f1f465 | 2467 | (INTEL_DEVID(dev) & 0xFF00) == 0x0C00) |
5dd8c4c3 | 2468 | #define IS_BDW_ULT(dev) (IS_BROADWELL(dev) && \ |
6b96d705 | 2469 | ((INTEL_DEVID(dev) & 0xf) == 0x6 || \ |
0dc6f20b | 2470 | (INTEL_DEVID(dev) & 0xf) == 0xb || \ |
87f1f465 | 2471 | (INTEL_DEVID(dev) & 0xf) == 0xe)) |
ebb72aad VS |
2472 | /* ULX machines are also considered ULT. */ |
2473 | #define IS_BDW_ULX(dev) (IS_BROADWELL(dev) && \ | |
2474 | (INTEL_DEVID(dev) & 0xf) == 0xe) | |
a0fcbd95 RV |
2475 | #define IS_BDW_GT3(dev) (IS_BROADWELL(dev) && \ |
2476 | (INTEL_DEVID(dev) & 0x00F0) == 0x0020) | |
5dd8c4c3 | 2477 | #define IS_HSW_ULT(dev) (IS_HASWELL(dev) && \ |
87f1f465 | 2478 | (INTEL_DEVID(dev) & 0xFF00) == 0x0A00) |
9435373e | 2479 | #define IS_HSW_GT3(dev) (IS_HASWELL(dev) && \ |
87f1f465 | 2480 | (INTEL_DEVID(dev) & 0x00F0) == 0x0020) |
9bbfd20a | 2481 | /* ULX machines are also considered ULT. */ |
87f1f465 CW |
2482 | #define IS_HSW_ULX(dev) (INTEL_DEVID(dev) == 0x0A0E || \ |
2483 | INTEL_DEVID(dev) == 0x0A1E) | |
f8896f5d DW |
2484 | #define IS_SKL_ULT(dev) (INTEL_DEVID(dev) == 0x1906 || \ |
2485 | INTEL_DEVID(dev) == 0x1913 || \ | |
2486 | INTEL_DEVID(dev) == 0x1916 || \ | |
2487 | INTEL_DEVID(dev) == 0x1921 || \ | |
2488 | INTEL_DEVID(dev) == 0x1926) | |
2489 | #define IS_SKL_ULX(dev) (INTEL_DEVID(dev) == 0x190E || \ | |
2490 | INTEL_DEVID(dev) == 0x1915 || \ | |
2491 | INTEL_DEVID(dev) == 0x191E) | |
7a58bad0 SAK |
2492 | #define IS_SKL_GT3(dev) (IS_SKYLAKE(dev) && \ |
2493 | (INTEL_DEVID(dev) & 0x00F0) == 0x0020) | |
2494 | #define IS_SKL_GT4(dev) (IS_SKYLAKE(dev) && \ | |
2495 | (INTEL_DEVID(dev) & 0x00F0) == 0x0030) | |
2496 | ||
b833d685 | 2497 | #define IS_PRELIMINARY_HW(intel_info) ((intel_info)->is_preliminary) |
cae5852d | 2498 | |
e90a21d4 HN |
2499 | #define SKL_REVID_A0 (0x0) |
2500 | #define SKL_REVID_B0 (0x1) | |
2501 | #define SKL_REVID_C0 (0x2) | |
2502 | #define SKL_REVID_D0 (0x3) | |
8bc0ccf6 | 2503 | #define SKL_REVID_E0 (0x4) |
b88baa2a | 2504 | #define SKL_REVID_F0 (0x5) |
e90a21d4 | 2505 | |
6c74c87f NH |
2506 | #define BXT_REVID_A0 (0x0) |
2507 | #define BXT_REVID_B0 (0x3) | |
5ca4163a | 2508 | #define BXT_REVID_C0 (0x9) |
6c74c87f | 2509 | |
85436696 JB |
2510 | /* |
2511 | * The genX designation typically refers to the render engine, so render | |
2512 | * capability related checks should use IS_GEN, while display and other checks | |
2513 | * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular | |
2514 | * chips, etc.). | |
2515 | */ | |
cae5852d ZN |
2516 | #define IS_GEN2(dev) (INTEL_INFO(dev)->gen == 2) |
2517 | #define IS_GEN3(dev) (INTEL_INFO(dev)->gen == 3) | |
2518 | #define IS_GEN4(dev) (INTEL_INFO(dev)->gen == 4) | |
2519 | #define IS_GEN5(dev) (INTEL_INFO(dev)->gen == 5) | |
2520 | #define IS_GEN6(dev) (INTEL_INFO(dev)->gen == 6) | |
85436696 | 2521 | #define IS_GEN7(dev) (INTEL_INFO(dev)->gen == 7) |
d2980845 | 2522 | #define IS_GEN8(dev) (INTEL_INFO(dev)->gen == 8) |
b71252dc | 2523 | #define IS_GEN9(dev) (INTEL_INFO(dev)->gen == 9) |
cae5852d | 2524 | |
73ae478c BW |
2525 | #define RENDER_RING (1<<RCS) |
2526 | #define BSD_RING (1<<VCS) | |
2527 | #define BLT_RING (1<<BCS) | |
2528 | #define VEBOX_RING (1<<VECS) | |
845f74a7 | 2529 | #define BSD2_RING (1<<VCS2) |
63c42e56 | 2530 | #define HAS_BSD(dev) (INTEL_INFO(dev)->ring_mask & BSD_RING) |
845f74a7 | 2531 | #define HAS_BSD2(dev) (INTEL_INFO(dev)->ring_mask & BSD2_RING) |
63c42e56 BW |
2532 | #define HAS_BLT(dev) (INTEL_INFO(dev)->ring_mask & BLT_RING) |
2533 | #define HAS_VEBOX(dev) (INTEL_INFO(dev)->ring_mask & VEBOX_RING) | |
2534 | #define HAS_LLC(dev) (INTEL_INFO(dev)->has_llc) | |
2535 | #define HAS_WT(dev) ((IS_HASWELL(dev) || IS_BROADWELL(dev)) && \ | |
f2fbc690 | 2536 | __I915__(dev)->ellc_size) |
cae5852d ZN |
2537 | #define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws) |
2538 | ||
254f965c | 2539 | #define HAS_HW_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 6) |
d7f621e5 | 2540 | #define HAS_LOGICAL_RING_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 8) |
692ef70c | 2541 | #define USES_PPGTT(dev) (i915.enable_ppgtt) |
81ba8aef MT |
2542 | #define USES_FULL_PPGTT(dev) (i915.enable_ppgtt >= 2) |
2543 | #define USES_FULL_48BIT_PPGTT(dev) (i915.enable_ppgtt == 3) | |
1d2a314c | 2544 | |
05394f39 | 2545 | #define HAS_OVERLAY(dev) (INTEL_INFO(dev)->has_overlay) |
cae5852d ZN |
2546 | #define OVERLAY_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->overlay_needs_physical) |
2547 | ||
b45305fc DV |
2548 | /* Early gen2 have a totally busted CS tlb and require pinned batches. */ |
2549 | #define HAS_BROKEN_CS_TLB(dev) (IS_I830(dev) || IS_845G(dev)) | |
4e6b788c DV |
2550 | /* |
2551 | * dp aux and gmbus irq on gen4 seems to be able to generate legacy interrupts | |
2552 | * even when in MSI mode. This results in spurious interrupt warnings if the | |
2553 | * legacy irq no. is shared with another device. The kernel then disables that | |
2554 | * interrupt source and so prevents the other device from working properly. | |
2555 | */ | |
2556 | #define HAS_AUX_IRQ(dev) (INTEL_INFO(dev)->gen >= 5) | |
2557 | #define HAS_GMBUS_IRQ(dev) (INTEL_INFO(dev)->gen >= 5) | |
b45305fc | 2558 | |
cae5852d ZN |
2559 | /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte |
2560 | * rows, which changed the alignment requirements and fence programming. | |
2561 | */ | |
2562 | #define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \ | |
2563 | IS_I915GM(dev))) | |
cae5852d ZN |
2564 | #define SUPPORTS_TV(dev) (INTEL_INFO(dev)->supports_tv) |
2565 | #define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug) | |
cae5852d ZN |
2566 | |
2567 | #define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2) | |
2568 | #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr) | |
3a77c4c4 | 2569 | #define HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc) |
cae5852d | 2570 | |
dbf7786e | 2571 | #define HAS_IPS(dev) (IS_HSW_ULT(dev) || IS_BROADWELL(dev)) |
f5adf94e | 2572 | |
0c9b3715 JN |
2573 | #define HAS_DP_MST(dev) (IS_HASWELL(dev) || IS_BROADWELL(dev) || \ |
2574 | INTEL_INFO(dev)->gen >= 9) | |
2575 | ||
dd93be58 | 2576 | #define HAS_DDI(dev) (INTEL_INFO(dev)->has_ddi) |
30568c45 | 2577 | #define HAS_FPGA_DBG_UNCLAIMED(dev) (INTEL_INFO(dev)->has_fpga_dbg) |
b32c6f48 | 2578 | #define HAS_PSR(dev) (IS_HASWELL(dev) || IS_BROADWELL(dev) || \ |
e3d99845 SJ |
2579 | IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev) || \ |
2580 | IS_SKYLAKE(dev)) | |
6157d3c8 | 2581 | #define HAS_RUNTIME_PM(dev) (IS_GEN6(dev) || IS_HASWELL(dev) || \ |
00776511 SS |
2582 | IS_BROADWELL(dev) || IS_VALLEYVIEW(dev) || \ |
2583 | IS_SKYLAKE(dev)) | |
58abf1da RV |
2584 | #define HAS_RC6(dev) (INTEL_INFO(dev)->gen >= 6) |
2585 | #define HAS_RC6p(dev) (INTEL_INFO(dev)->gen == 6 || IS_IVYBRIDGE(dev)) | |
affa9354 | 2586 | |
7b403ffb | 2587 | #define HAS_CSR(dev) (IS_GEN9(dev)) |
eb805623 | 2588 | |
33a732f4 AD |
2589 | #define HAS_GUC_UCODE(dev) (IS_GEN9(dev)) |
2590 | #define HAS_GUC_SCHED(dev) (IS_GEN9(dev)) | |
2591 | ||
a9ed33ca AJ |
2592 | #define HAS_RESOURCE_STREAMER(dev) (IS_HASWELL(dev) || \ |
2593 | INTEL_INFO(dev)->gen >= 8) | |
2594 | ||
97d3308a | 2595 | #define HAS_CORE_RING_FREQ(dev) (INTEL_INFO(dev)->gen >= 6 && \ |
430b7ad5 | 2596 | !IS_VALLEYVIEW(dev) && !IS_BROXTON(dev)) |
97d3308a | 2597 | |
17a303ec PZ |
2598 | #define INTEL_PCH_DEVICE_ID_MASK 0xff00 |
2599 | #define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00 | |
2600 | #define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00 | |
2601 | #define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00 | |
2602 | #define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00 | |
2603 | #define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE 0x9c00 | |
e7e7ea20 S |
2604 | #define INTEL_PCH_SPT_DEVICE_ID_TYPE 0xA100 |
2605 | #define INTEL_PCH_SPT_LP_DEVICE_ID_TYPE 0x9D00 | |
30c964a6 | 2606 | #define INTEL_PCH_P2X_DEVICE_ID_TYPE 0x7100 |
17a303ec | 2607 | |
f2fbc690 | 2608 | #define INTEL_PCH_TYPE(dev) (__I915__(dev)->pch_type) |
e7e7ea20 | 2609 | #define HAS_PCH_SPT(dev) (INTEL_PCH_TYPE(dev) == PCH_SPT) |
eb877ebf | 2610 | #define HAS_PCH_LPT(dev) (INTEL_PCH_TYPE(dev) == PCH_LPT) |
c2699524 | 2611 | #define HAS_PCH_LPT_LP(dev) (__I915__(dev)->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) |
cae5852d ZN |
2612 | #define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT) |
2613 | #define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX) | |
40c7ead9 | 2614 | #define HAS_PCH_NOP(dev) (INTEL_PCH_TYPE(dev) == PCH_NOP) |
45e6e3a1 | 2615 | #define HAS_PCH_SPLIT(dev) (INTEL_PCH_TYPE(dev) != PCH_NONE) |
cae5852d | 2616 | |
5fafe292 SJ |
2617 | #define HAS_GMCH_DISPLAY(dev) (INTEL_INFO(dev)->gen < 5 || IS_VALLEYVIEW(dev)) |
2618 | ||
040d2baa BW |
2619 | /* DPF == dynamic parity feature */ |
2620 | #define HAS_L3_DPF(dev) (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) | |
2621 | #define NUM_L3_SLICES(dev) (IS_HSW_GT3(dev) ? 2 : HAS_L3_DPF(dev)) | |
e1ef7cc2 | 2622 | |
c8735b0c | 2623 | #define GT_FREQUENCY_MULTIPLIER 50 |
de43ae9d | 2624 | #define GEN9_FREQ_SCALER 3 |
c8735b0c | 2625 | |
05394f39 CW |
2626 | #include "i915_trace.h" |
2627 | ||
baa70943 | 2628 | extern const struct drm_ioctl_desc i915_ioctls[]; |
b3a83639 DA |
2629 | extern int i915_max_ioctl; |
2630 | ||
1751fcf9 ML |
2631 | extern int i915_suspend_switcheroo(struct drm_device *dev, pm_message_t state); |
2632 | extern int i915_resume_switcheroo(struct drm_device *dev); | |
7c1c2871 | 2633 | |
d330a953 JN |
2634 | /* i915_params.c */ |
2635 | struct i915_params { | |
2636 | int modeset; | |
2637 | int panel_ignore_lid; | |
d330a953 | 2638 | int semaphores; |
d330a953 JN |
2639 | int lvds_channel_mode; |
2640 | int panel_use_ssc; | |
2641 | int vbt_sdvo_panel_type; | |
2642 | int enable_rc6; | |
2643 | int enable_fbc; | |
d330a953 | 2644 | int enable_ppgtt; |
127f1003 | 2645 | int enable_execlists; |
d330a953 JN |
2646 | int enable_psr; |
2647 | unsigned int preliminary_hw_support; | |
2648 | int disable_power_well; | |
2649 | int enable_ips; | |
e5aa6541 | 2650 | int invert_brightness; |
351e3db2 | 2651 | int enable_cmd_parser; |
e5aa6541 DL |
2652 | /* leave bools at the end to not create holes */ |
2653 | bool enable_hangcheck; | |
73831236 | 2654 | bool fastboot; |
d330a953 | 2655 | bool prefault_disable; |
5bedeb2d | 2656 | bool load_detect_test; |
d330a953 | 2657 | bool reset; |
a0bae57f | 2658 | bool disable_display; |
7a10dfa6 | 2659 | bool disable_vtd_wa; |
63dc0449 AD |
2660 | bool enable_guc_submission; |
2661 | int guc_log_level; | |
84c33a64 | 2662 | int use_mmio_flip; |
48572edd | 2663 | int mmio_debug; |
e2c719b7 | 2664 | bool verbose_state_checks; |
c5b852f3 | 2665 | bool nuclear_pageflip; |
9e458034 | 2666 | int edp_vswing; |
d330a953 JN |
2667 | }; |
2668 | extern struct i915_params i915 __read_mostly; | |
2669 | ||
1da177e4 | 2670 | /* i915_dma.c */ |
22eae947 | 2671 | extern int i915_driver_load(struct drm_device *, unsigned long flags); |
ba8bbcf6 | 2672 | extern int i915_driver_unload(struct drm_device *); |
2885f6ac | 2673 | extern int i915_driver_open(struct drm_device *dev, struct drm_file *file); |
84b1fd10 | 2674 | extern void i915_driver_lastclose(struct drm_device * dev); |
6c340eac | 2675 | extern void i915_driver_preclose(struct drm_device *dev, |
2885f6ac | 2676 | struct drm_file *file); |
673a394b | 2677 | extern void i915_driver_postclose(struct drm_device *dev, |
2885f6ac | 2678 | struct drm_file *file); |
c43b5634 | 2679 | #ifdef CONFIG_COMPAT |
0d6aa60b DA |
2680 | extern long i915_compat_ioctl(struct file *filp, unsigned int cmd, |
2681 | unsigned long arg); | |
c43b5634 | 2682 | #endif |
8e96d9c4 | 2683 | extern int intel_gpu_reset(struct drm_device *dev); |
49e4d842 | 2684 | extern bool intel_has_gpu_reset(struct drm_device *dev); |
d4b8bb2a | 2685 | extern int i915_reset(struct drm_device *dev); |
7648fa99 JB |
2686 | extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv); |
2687 | extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv); | |
2688 | extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv); | |
2689 | extern void i915_update_gfx_val(struct drm_i915_private *dev_priv); | |
650ad970 | 2690 | int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool on); |
eb805623 | 2691 | void i915_firmware_load_error_print(const char *fw_path, int err); |
7648fa99 | 2692 | |
77913b39 JN |
2693 | /* intel_hotplug.c */ |
2694 | void intel_hpd_irq_handler(struct drm_device *dev, u32 pin_mask, u32 long_mask); | |
2695 | void intel_hpd_init(struct drm_i915_private *dev_priv); | |
2696 | void intel_hpd_init_work(struct drm_i915_private *dev_priv); | |
2697 | void intel_hpd_cancel_work(struct drm_i915_private *dev_priv); | |
cc24fcdc | 2698 | bool intel_hpd_pin_to_port(enum hpd_pin pin, enum port *port); |
77913b39 | 2699 | |
1da177e4 | 2700 | /* i915_irq.c */ |
10cd45b6 | 2701 | void i915_queue_hangcheck(struct drm_device *dev); |
58174462 MK |
2702 | __printf(3, 4) |
2703 | void i915_handle_error(struct drm_device *dev, bool wedged, | |
2704 | const char *fmt, ...); | |
1da177e4 | 2705 | |
b963291c | 2706 | extern void intel_irq_init(struct drm_i915_private *dev_priv); |
2aeb7d3a DV |
2707 | int intel_irq_install(struct drm_i915_private *dev_priv); |
2708 | void intel_irq_uninstall(struct drm_i915_private *dev_priv); | |
907b28c5 CW |
2709 | |
2710 | extern void intel_uncore_sanitize(struct drm_device *dev); | |
10018603 ID |
2711 | extern void intel_uncore_early_sanitize(struct drm_device *dev, |
2712 | bool restore_forcewake); | |
907b28c5 | 2713 | extern void intel_uncore_init(struct drm_device *dev); |
907b28c5 | 2714 | extern void intel_uncore_check_errors(struct drm_device *dev); |
aec347ab | 2715 | extern void intel_uncore_fini(struct drm_device *dev); |
156c7ca0 | 2716 | extern void intel_uncore_forcewake_reset(struct drm_device *dev, bool restore); |
48c1026a | 2717 | const char *intel_uncore_forcewake_domain_to_str(const enum forcewake_domain_id id); |
59bad947 | 2718 | void intel_uncore_forcewake_get(struct drm_i915_private *dev_priv, |
48c1026a | 2719 | enum forcewake_domains domains); |
59bad947 | 2720 | void intel_uncore_forcewake_put(struct drm_i915_private *dev_priv, |
48c1026a | 2721 | enum forcewake_domains domains); |
a6111f7b CW |
2722 | /* Like above but the caller must manage the uncore.lock itself. |
2723 | * Must be used with I915_READ_FW and friends. | |
2724 | */ | |
2725 | void intel_uncore_forcewake_get__locked(struct drm_i915_private *dev_priv, | |
2726 | enum forcewake_domains domains); | |
2727 | void intel_uncore_forcewake_put__locked(struct drm_i915_private *dev_priv, | |
2728 | enum forcewake_domains domains); | |
59bad947 | 2729 | void assert_forcewakes_inactive(struct drm_i915_private *dev_priv); |
cf9d2890 YZ |
2730 | static inline bool intel_vgpu_active(struct drm_device *dev) |
2731 | { | |
2732 | return to_i915(dev)->vgpu.active; | |
2733 | } | |
b1f14ad0 | 2734 | |
7c463586 | 2735 | void |
50227e1c | 2736 | i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe, |
755e9019 | 2737 | u32 status_mask); |
7c463586 KP |
2738 | |
2739 | void | |
50227e1c | 2740 | i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe, |
755e9019 | 2741 | u32 status_mask); |
7c463586 | 2742 | |
f8b79e58 ID |
2743 | void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv); |
2744 | void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv); | |
0706f17c EE |
2745 | void i915_hotplug_interrupt_update(struct drm_i915_private *dev_priv, |
2746 | uint32_t mask, | |
2747 | uint32_t bits); | |
47339cd9 DV |
2748 | void |
2749 | ironlake_enable_display_irq(struct drm_i915_private *dev_priv, u32 mask); | |
2750 | void | |
2751 | ironlake_disable_display_irq(struct drm_i915_private *dev_priv, u32 mask); | |
2752 | void ibx_display_interrupt_update(struct drm_i915_private *dev_priv, | |
2753 | uint32_t interrupt_mask, | |
2754 | uint32_t enabled_irq_mask); | |
2755 | #define ibx_enable_display_interrupt(dev_priv, bits) \ | |
2756 | ibx_display_interrupt_update((dev_priv), (bits), (bits)) | |
2757 | #define ibx_disable_display_interrupt(dev_priv, bits) \ | |
2758 | ibx_display_interrupt_update((dev_priv), (bits), 0) | |
f8b79e58 | 2759 | |
673a394b | 2760 | /* i915_gem.c */ |
673a394b EA |
2761 | int i915_gem_create_ioctl(struct drm_device *dev, void *data, |
2762 | struct drm_file *file_priv); | |
2763 | int i915_gem_pread_ioctl(struct drm_device *dev, void *data, | |
2764 | struct drm_file *file_priv); | |
2765 | int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data, | |
2766 | struct drm_file *file_priv); | |
2767 | int i915_gem_mmap_ioctl(struct drm_device *dev, void *data, | |
2768 | struct drm_file *file_priv); | |
de151cf6 JB |
2769 | int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data, |
2770 | struct drm_file *file_priv); | |
673a394b EA |
2771 | int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data, |
2772 | struct drm_file *file_priv); | |
2773 | int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data, | |
2774 | struct drm_file *file_priv); | |
ba8b7ccb | 2775 | void i915_gem_execbuffer_move_to_active(struct list_head *vmas, |
8a8edb59 | 2776 | struct drm_i915_gem_request *req); |
adeca76d | 2777 | void i915_gem_execbuffer_retire_commands(struct i915_execbuffer_params *params); |
5f19e2bf | 2778 | int i915_gem_ringbuffer_submission(struct i915_execbuffer_params *params, |
a83014d3 | 2779 | struct drm_i915_gem_execbuffer2 *args, |
5f19e2bf | 2780 | struct list_head *vmas); |
673a394b EA |
2781 | int i915_gem_execbuffer(struct drm_device *dev, void *data, |
2782 | struct drm_file *file_priv); | |
76446cac JB |
2783 | int i915_gem_execbuffer2(struct drm_device *dev, void *data, |
2784 | struct drm_file *file_priv); | |
673a394b EA |
2785 | int i915_gem_busy_ioctl(struct drm_device *dev, void *data, |
2786 | struct drm_file *file_priv); | |
199adf40 BW |
2787 | int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data, |
2788 | struct drm_file *file); | |
2789 | int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data, | |
2790 | struct drm_file *file); | |
673a394b EA |
2791 | int i915_gem_throttle_ioctl(struct drm_device *dev, void *data, |
2792 | struct drm_file *file_priv); | |
3ef94daa CW |
2793 | int i915_gem_madvise_ioctl(struct drm_device *dev, void *data, |
2794 | struct drm_file *file_priv); | |
673a394b EA |
2795 | int i915_gem_set_tiling(struct drm_device *dev, void *data, |
2796 | struct drm_file *file_priv); | |
2797 | int i915_gem_get_tiling(struct drm_device *dev, void *data, | |
2798 | struct drm_file *file_priv); | |
5cc9ed4b CW |
2799 | int i915_gem_init_userptr(struct drm_device *dev); |
2800 | int i915_gem_userptr_ioctl(struct drm_device *dev, void *data, | |
2801 | struct drm_file *file); | |
5a125c3c EA |
2802 | int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data, |
2803 | struct drm_file *file_priv); | |
23ba4fd0 BW |
2804 | int i915_gem_wait_ioctl(struct drm_device *dev, void *data, |
2805 | struct drm_file *file_priv); | |
673a394b | 2806 | void i915_gem_load(struct drm_device *dev); |
42dcedd4 CW |
2807 | void *i915_gem_object_alloc(struct drm_device *dev); |
2808 | void i915_gem_object_free(struct drm_i915_gem_object *obj); | |
37e680a1 CW |
2809 | void i915_gem_object_init(struct drm_i915_gem_object *obj, |
2810 | const struct drm_i915_gem_object_ops *ops); | |
05394f39 CW |
2811 | struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev, |
2812 | size_t size); | |
ea70299d DG |
2813 | struct drm_i915_gem_object *i915_gem_object_create_from_data( |
2814 | struct drm_device *dev, const void *data, size_t size); | |
673a394b | 2815 | void i915_gem_free_object(struct drm_gem_object *obj); |
2f633156 | 2816 | void i915_gem_vma_destroy(struct i915_vma *vma); |
42dcedd4 | 2817 | |
0875546c DV |
2818 | /* Flags used by pin/bind&friends. */ |
2819 | #define PIN_MAPPABLE (1<<0) | |
2820 | #define PIN_NONBLOCK (1<<1) | |
2821 | #define PIN_GLOBAL (1<<2) | |
2822 | #define PIN_OFFSET_BIAS (1<<3) | |
2823 | #define PIN_USER (1<<4) | |
2824 | #define PIN_UPDATE (1<<5) | |
101b506a MT |
2825 | #define PIN_ZONE_4G (1<<6) |
2826 | #define PIN_HIGH (1<<7) | |
d23db88c | 2827 | #define PIN_OFFSET_MASK (~4095) |
ec7adb6e JL |
2828 | int __must_check |
2829 | i915_gem_object_pin(struct drm_i915_gem_object *obj, | |
2830 | struct i915_address_space *vm, | |
2831 | uint32_t alignment, | |
2832 | uint64_t flags); | |
2833 | int __must_check | |
2834 | i915_gem_object_ggtt_pin(struct drm_i915_gem_object *obj, | |
2835 | const struct i915_ggtt_view *view, | |
2836 | uint32_t alignment, | |
2837 | uint64_t flags); | |
fe14d5f4 TU |
2838 | |
2839 | int i915_vma_bind(struct i915_vma *vma, enum i915_cache_level cache_level, | |
2840 | u32 flags); | |
07fe0b12 | 2841 | int __must_check i915_vma_unbind(struct i915_vma *vma); |
e9f24d5f TU |
2842 | /* |
2843 | * BEWARE: Do not use the function below unless you can _absolutely_ | |
2844 | * _guarantee_ VMA in question is _not in use_ anywhere. | |
2845 | */ | |
2846 | int __must_check __i915_vma_unbind_no_wait(struct i915_vma *vma); | |
dd624afd | 2847 | int i915_gem_object_put_pages(struct drm_i915_gem_object *obj); |
48018a57 | 2848 | void i915_gem_release_all_mmaps(struct drm_i915_private *dev_priv); |
05394f39 | 2849 | void i915_gem_release_mmap(struct drm_i915_gem_object *obj); |
f787a5f5 | 2850 | |
4c914c0c BV |
2851 | int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj, |
2852 | int *needs_clflush); | |
2853 | ||
37e680a1 | 2854 | int __must_check i915_gem_object_get_pages(struct drm_i915_gem_object *obj); |
ee286370 CW |
2855 | |
2856 | static inline int __sg_page_count(struct scatterlist *sg) | |
9da3da66 | 2857 | { |
ee286370 CW |
2858 | return sg->length >> PAGE_SHIFT; |
2859 | } | |
67d5a50c | 2860 | |
ee286370 CW |
2861 | static inline struct page * |
2862 | i915_gem_object_get_page(struct drm_i915_gem_object *obj, int n) | |
9da3da66 | 2863 | { |
ee286370 CW |
2864 | if (WARN_ON(n >= obj->base.size >> PAGE_SHIFT)) |
2865 | return NULL; | |
67d5a50c | 2866 | |
ee286370 CW |
2867 | if (n < obj->get_page.last) { |
2868 | obj->get_page.sg = obj->pages->sgl; | |
2869 | obj->get_page.last = 0; | |
2870 | } | |
67d5a50c | 2871 | |
ee286370 CW |
2872 | while (obj->get_page.last + __sg_page_count(obj->get_page.sg) <= n) { |
2873 | obj->get_page.last += __sg_page_count(obj->get_page.sg++); | |
2874 | if (unlikely(sg_is_chain(obj->get_page.sg))) | |
2875 | obj->get_page.sg = sg_chain_ptr(obj->get_page.sg); | |
2876 | } | |
67d5a50c | 2877 | |
ee286370 | 2878 | return nth_page(sg_page(obj->get_page.sg), n - obj->get_page.last); |
9da3da66 | 2879 | } |
ee286370 | 2880 | |
a5570178 CW |
2881 | static inline void i915_gem_object_pin_pages(struct drm_i915_gem_object *obj) |
2882 | { | |
2883 | BUG_ON(obj->pages == NULL); | |
2884 | obj->pages_pin_count++; | |
2885 | } | |
2886 | static inline void i915_gem_object_unpin_pages(struct drm_i915_gem_object *obj) | |
2887 | { | |
2888 | BUG_ON(obj->pages_pin_count == 0); | |
2889 | obj->pages_pin_count--; | |
2890 | } | |
2891 | ||
54cf91dc | 2892 | int __must_check i915_mutex_lock_interruptible(struct drm_device *dev); |
2911a35b | 2893 | int i915_gem_object_sync(struct drm_i915_gem_object *obj, |
91af127f JH |
2894 | struct intel_engine_cs *to, |
2895 | struct drm_i915_gem_request **to_req); | |
e2d05a8b | 2896 | void i915_vma_move_to_active(struct i915_vma *vma, |
b2af0376 | 2897 | struct drm_i915_gem_request *req); |
ff72145b DA |
2898 | int i915_gem_dumb_create(struct drm_file *file_priv, |
2899 | struct drm_device *dev, | |
2900 | struct drm_mode_create_dumb *args); | |
da6b51d0 DA |
2901 | int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev, |
2902 | uint32_t handle, uint64_t *offset); | |
f787a5f5 CW |
2903 | /** |
2904 | * Returns true if seq1 is later than seq2. | |
2905 | */ | |
2906 | static inline bool | |
2907 | i915_seqno_passed(uint32_t seq1, uint32_t seq2) | |
2908 | { | |
2909 | return (int32_t)(seq1 - seq2) >= 0; | |
2910 | } | |
2911 | ||
1b5a433a JH |
2912 | static inline bool i915_gem_request_completed(struct drm_i915_gem_request *req, |
2913 | bool lazy_coherency) | |
2914 | { | |
2915 | u32 seqno; | |
2916 | ||
2917 | BUG_ON(req == NULL); | |
2918 | ||
2919 | seqno = req->ring->get_seqno(req->ring, lazy_coherency); | |
2920 | ||
2921 | return i915_seqno_passed(seqno, req->seqno); | |
2922 | } | |
2923 | ||
fca26bb4 MK |
2924 | int __must_check i915_gem_get_seqno(struct drm_device *dev, u32 *seqno); |
2925 | int __must_check i915_gem_set_seqno(struct drm_device *dev, u32 seqno); | |
1690e1eb | 2926 | |
8d9fc7fd | 2927 | struct drm_i915_gem_request * |
a4872ba6 | 2928 | i915_gem_find_active_request(struct intel_engine_cs *ring); |
8d9fc7fd | 2929 | |
b29c19b6 | 2930 | bool i915_gem_retire_requests(struct drm_device *dev); |
a4872ba6 | 2931 | void i915_gem_retire_requests_ring(struct intel_engine_cs *ring); |
33196ded | 2932 | int __must_check i915_gem_check_wedge(struct i915_gpu_error *error, |
d6b2c790 | 2933 | bool interruptible); |
84c33a64 | 2934 | |
1f83fee0 DV |
2935 | static inline bool i915_reset_in_progress(struct i915_gpu_error *error) |
2936 | { | |
2937 | return unlikely(atomic_read(&error->reset_counter) | |
2ac0f450 | 2938 | & (I915_RESET_IN_PROGRESS_FLAG | I915_WEDGED)); |
1f83fee0 DV |
2939 | } |
2940 | ||
2941 | static inline bool i915_terminally_wedged(struct i915_gpu_error *error) | |
2942 | { | |
2ac0f450 MK |
2943 | return atomic_read(&error->reset_counter) & I915_WEDGED; |
2944 | } | |
2945 | ||
2946 | static inline u32 i915_reset_count(struct i915_gpu_error *error) | |
2947 | { | |
2948 | return ((atomic_read(&error->reset_counter) & ~I915_WEDGED) + 1) / 2; | |
1f83fee0 | 2949 | } |
a71d8d94 | 2950 | |
88b4aa87 MK |
2951 | static inline bool i915_stop_ring_allow_ban(struct drm_i915_private *dev_priv) |
2952 | { | |
2953 | return dev_priv->gpu_error.stop_rings == 0 || | |
2954 | dev_priv->gpu_error.stop_rings & I915_STOP_RING_ALLOW_BAN; | |
2955 | } | |
2956 | ||
2957 | static inline bool i915_stop_ring_allow_warn(struct drm_i915_private *dev_priv) | |
2958 | { | |
2959 | return dev_priv->gpu_error.stop_rings == 0 || | |
2960 | dev_priv->gpu_error.stop_rings & I915_STOP_RING_ALLOW_WARN; | |
2961 | } | |
2962 | ||
069efc1d | 2963 | void i915_gem_reset(struct drm_device *dev); |
000433b6 | 2964 | bool i915_gem_clflush_object(struct drm_i915_gem_object *obj, bool force); |
1070a42b | 2965 | int __must_check i915_gem_init(struct drm_device *dev); |
a83014d3 | 2966 | int i915_gem_init_rings(struct drm_device *dev); |
f691e2f4 | 2967 | int __must_check i915_gem_init_hw(struct drm_device *dev); |
6909a666 | 2968 | int i915_gem_l3_remap(struct drm_i915_gem_request *req, int slice); |
f691e2f4 | 2969 | void i915_gem_init_swizzling(struct drm_device *dev); |
79e53945 | 2970 | void i915_gem_cleanup_ringbuffer(struct drm_device *dev); |
b2da9fe5 | 2971 | int __must_check i915_gpu_idle(struct drm_device *dev); |
45c5f202 | 2972 | int __must_check i915_gem_suspend(struct drm_device *dev); |
75289874 | 2973 | void __i915_add_request(struct drm_i915_gem_request *req, |
5b4a60c2 JH |
2974 | struct drm_i915_gem_object *batch_obj, |
2975 | bool flush_caches); | |
75289874 | 2976 | #define i915_add_request(req) \ |
fcfa423c | 2977 | __i915_add_request(req, NULL, true) |
75289874 | 2978 | #define i915_add_request_no_flush(req) \ |
fcfa423c | 2979 | __i915_add_request(req, NULL, false) |
9c654818 | 2980 | int __i915_wait_request(struct drm_i915_gem_request *req, |
16e9a21f ACO |
2981 | unsigned reset_counter, |
2982 | bool interruptible, | |
2983 | s64 *timeout, | |
2e1b8730 | 2984 | struct intel_rps_client *rps); |
a4b3a571 | 2985 | int __must_check i915_wait_request(struct drm_i915_gem_request *req); |
de151cf6 | 2986 | int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf); |
2021746e | 2987 | int __must_check |
2e2f351d CW |
2988 | i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj, |
2989 | bool readonly); | |
2990 | int __must_check | |
2021746e CW |
2991 | i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, |
2992 | bool write); | |
2993 | int __must_check | |
dabdfe02 CW |
2994 | i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write); |
2995 | int __must_check | |
2da3b9b9 CW |
2996 | i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj, |
2997 | u32 alignment, | |
e6617330 | 2998 | struct intel_engine_cs *pipelined, |
91af127f | 2999 | struct drm_i915_gem_request **pipelined_request, |
e6617330 TU |
3000 | const struct i915_ggtt_view *view); |
3001 | void i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object *obj, | |
3002 | const struct i915_ggtt_view *view); | |
00731155 | 3003 | int i915_gem_object_attach_phys(struct drm_i915_gem_object *obj, |
6eeefaf3 | 3004 | int align); |
b29c19b6 | 3005 | int i915_gem_open(struct drm_device *dev, struct drm_file *file); |
05394f39 | 3006 | void i915_gem_release(struct drm_device *dev, struct drm_file *file); |
673a394b | 3007 | |
0fa87796 ID |
3008 | uint32_t |
3009 | i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode); | |
467cffba | 3010 | uint32_t |
d865110c ID |
3011 | i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size, |
3012 | int tiling_mode, bool fenced); | |
467cffba | 3013 | |
e4ffd173 CW |
3014 | int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj, |
3015 | enum i915_cache_level cache_level); | |
3016 | ||
1286ff73 DV |
3017 | struct drm_gem_object *i915_gem_prime_import(struct drm_device *dev, |
3018 | struct dma_buf *dma_buf); | |
3019 | ||
3020 | struct dma_buf *i915_gem_prime_export(struct drm_device *dev, | |
3021 | struct drm_gem_object *gem_obj, int flags); | |
3022 | ||
088e0df4 MT |
3023 | u64 i915_gem_obj_ggtt_offset_view(struct drm_i915_gem_object *o, |
3024 | const struct i915_ggtt_view *view); | |
3025 | u64 i915_gem_obj_offset(struct drm_i915_gem_object *o, | |
3026 | struct i915_address_space *vm); | |
3027 | static inline u64 | |
ec7adb6e | 3028 | i915_gem_obj_ggtt_offset(struct drm_i915_gem_object *o) |
fe14d5f4 | 3029 | { |
9abc4648 | 3030 | return i915_gem_obj_ggtt_offset_view(o, &i915_ggtt_view_normal); |
fe14d5f4 | 3031 | } |
ec7adb6e | 3032 | |
a70a3148 | 3033 | bool i915_gem_obj_bound_any(struct drm_i915_gem_object *o); |
ec7adb6e | 3034 | bool i915_gem_obj_ggtt_bound_view(struct drm_i915_gem_object *o, |
9abc4648 | 3035 | const struct i915_ggtt_view *view); |
a70a3148 | 3036 | bool i915_gem_obj_bound(struct drm_i915_gem_object *o, |
ec7adb6e | 3037 | struct i915_address_space *vm); |
fe14d5f4 | 3038 | |
a70a3148 BW |
3039 | unsigned long i915_gem_obj_size(struct drm_i915_gem_object *o, |
3040 | struct i915_address_space *vm); | |
fe14d5f4 | 3041 | struct i915_vma * |
ec7adb6e JL |
3042 | i915_gem_obj_to_vma(struct drm_i915_gem_object *obj, |
3043 | struct i915_address_space *vm); | |
3044 | struct i915_vma * | |
3045 | i915_gem_obj_to_ggtt_view(struct drm_i915_gem_object *obj, | |
3046 | const struct i915_ggtt_view *view); | |
fe14d5f4 | 3047 | |
accfef2e BW |
3048 | struct i915_vma * |
3049 | i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object *obj, | |
ec7adb6e JL |
3050 | struct i915_address_space *vm); |
3051 | struct i915_vma * | |
3052 | i915_gem_obj_lookup_or_create_ggtt_vma(struct drm_i915_gem_object *obj, | |
3053 | const struct i915_ggtt_view *view); | |
5c2abbea | 3054 | |
ec7adb6e JL |
3055 | static inline struct i915_vma * |
3056 | i915_gem_obj_to_ggtt(struct drm_i915_gem_object *obj) | |
3057 | { | |
3058 | return i915_gem_obj_to_ggtt_view(obj, &i915_ggtt_view_normal); | |
d7f46fc4 | 3059 | } |
ec7adb6e | 3060 | bool i915_gem_obj_is_pinned(struct drm_i915_gem_object *obj); |
5c2abbea | 3061 | |
a70a3148 | 3062 | /* Some GGTT VM helpers */ |
5dc383b0 | 3063 | #define i915_obj_to_ggtt(obj) \ |
a70a3148 BW |
3064 | (&((struct drm_i915_private *)(obj)->base.dev->dev_private)->gtt.base) |
3065 | static inline bool i915_is_ggtt(struct i915_address_space *vm) | |
3066 | { | |
3067 | struct i915_address_space *ggtt = | |
3068 | &((struct drm_i915_private *)(vm)->dev->dev_private)->gtt.base; | |
3069 | return vm == ggtt; | |
3070 | } | |
3071 | ||
841cd773 DV |
3072 | static inline struct i915_hw_ppgtt * |
3073 | i915_vm_to_ppgtt(struct i915_address_space *vm) | |
3074 | { | |
3075 | WARN_ON(i915_is_ggtt(vm)); | |
3076 | ||
3077 | return container_of(vm, struct i915_hw_ppgtt, base); | |
3078 | } | |
3079 | ||
3080 | ||
a70a3148 BW |
3081 | static inline bool i915_gem_obj_ggtt_bound(struct drm_i915_gem_object *obj) |
3082 | { | |
9abc4648 | 3083 | return i915_gem_obj_ggtt_bound_view(obj, &i915_ggtt_view_normal); |
a70a3148 BW |
3084 | } |
3085 | ||
3086 | static inline unsigned long | |
3087 | i915_gem_obj_ggtt_size(struct drm_i915_gem_object *obj) | |
3088 | { | |
5dc383b0 | 3089 | return i915_gem_obj_size(obj, i915_obj_to_ggtt(obj)); |
a70a3148 | 3090 | } |
c37e2204 BW |
3091 | |
3092 | static inline int __must_check | |
3093 | i915_gem_obj_ggtt_pin(struct drm_i915_gem_object *obj, | |
3094 | uint32_t alignment, | |
1ec9e26d | 3095 | unsigned flags) |
c37e2204 | 3096 | { |
5dc383b0 DV |
3097 | return i915_gem_object_pin(obj, i915_obj_to_ggtt(obj), |
3098 | alignment, flags | PIN_GLOBAL); | |
c37e2204 | 3099 | } |
a70a3148 | 3100 | |
b287110e DV |
3101 | static inline int |
3102 | i915_gem_object_ggtt_unbind(struct drm_i915_gem_object *obj) | |
3103 | { | |
3104 | return i915_vma_unbind(i915_gem_obj_to_ggtt(obj)); | |
3105 | } | |
3106 | ||
e6617330 TU |
3107 | void i915_gem_object_ggtt_unpin_view(struct drm_i915_gem_object *obj, |
3108 | const struct i915_ggtt_view *view); | |
3109 | static inline void | |
3110 | i915_gem_object_ggtt_unpin(struct drm_i915_gem_object *obj) | |
3111 | { | |
3112 | i915_gem_object_ggtt_unpin_view(obj, &i915_ggtt_view_normal); | |
3113 | } | |
b287110e | 3114 | |
41a36b73 DV |
3115 | /* i915_gem_fence.c */ |
3116 | int __must_check i915_gem_object_get_fence(struct drm_i915_gem_object *obj); | |
3117 | int __must_check i915_gem_object_put_fence(struct drm_i915_gem_object *obj); | |
3118 | ||
3119 | bool i915_gem_object_pin_fence(struct drm_i915_gem_object *obj); | |
3120 | void i915_gem_object_unpin_fence(struct drm_i915_gem_object *obj); | |
3121 | ||
3122 | void i915_gem_restore_fences(struct drm_device *dev); | |
3123 | ||
7f96ecaf DV |
3124 | void i915_gem_detect_bit_6_swizzle(struct drm_device *dev); |
3125 | void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj); | |
3126 | void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj); | |
3127 | ||
254f965c | 3128 | /* i915_gem_context.c */ |
8245be31 | 3129 | int __must_check i915_gem_context_init(struct drm_device *dev); |
254f965c | 3130 | void i915_gem_context_fini(struct drm_device *dev); |
acce9ffa | 3131 | void i915_gem_context_reset(struct drm_device *dev); |
e422b888 | 3132 | int i915_gem_context_open(struct drm_device *dev, struct drm_file *file); |
b3dd6b96 | 3133 | int i915_gem_context_enable(struct drm_i915_gem_request *req); |
254f965c | 3134 | void i915_gem_context_close(struct drm_device *dev, struct drm_file *file); |
ba01cc93 | 3135 | int i915_switch_context(struct drm_i915_gem_request *req); |
273497e5 | 3136 | struct intel_context * |
41bde553 | 3137 | i915_gem_context_get(struct drm_i915_file_private *file_priv, u32 id); |
dce3271b | 3138 | void i915_gem_context_free(struct kref *ctx_ref); |
8c857917 OM |
3139 | struct drm_i915_gem_object * |
3140 | i915_gem_alloc_context_obj(struct drm_device *dev, size_t size); | |
273497e5 | 3141 | static inline void i915_gem_context_reference(struct intel_context *ctx) |
dce3271b | 3142 | { |
691e6415 | 3143 | kref_get(&ctx->ref); |
dce3271b MK |
3144 | } |
3145 | ||
273497e5 | 3146 | static inline void i915_gem_context_unreference(struct intel_context *ctx) |
dce3271b | 3147 | { |
691e6415 | 3148 | kref_put(&ctx->ref, i915_gem_context_free); |
dce3271b MK |
3149 | } |
3150 | ||
273497e5 | 3151 | static inline bool i915_gem_context_is_default(const struct intel_context *c) |
3fac8978 | 3152 | { |
821d66dd | 3153 | return c->user_handle == DEFAULT_CONTEXT_HANDLE; |
3fac8978 MK |
3154 | } |
3155 | ||
84624813 BW |
3156 | int i915_gem_context_create_ioctl(struct drm_device *dev, void *data, |
3157 | struct drm_file *file); | |
3158 | int i915_gem_context_destroy_ioctl(struct drm_device *dev, void *data, | |
3159 | struct drm_file *file); | |
c9dc0f35 CW |
3160 | int i915_gem_context_getparam_ioctl(struct drm_device *dev, void *data, |
3161 | struct drm_file *file_priv); | |
3162 | int i915_gem_context_setparam_ioctl(struct drm_device *dev, void *data, | |
3163 | struct drm_file *file_priv); | |
1286ff73 | 3164 | |
679845ed BW |
3165 | /* i915_gem_evict.c */ |
3166 | int __must_check i915_gem_evict_something(struct drm_device *dev, | |
3167 | struct i915_address_space *vm, | |
3168 | int min_size, | |
3169 | unsigned alignment, | |
3170 | unsigned cache_level, | |
d23db88c CW |
3171 | unsigned long start, |
3172 | unsigned long end, | |
1ec9e26d | 3173 | unsigned flags); |
679845ed | 3174 | int i915_gem_evict_vm(struct i915_address_space *vm, bool do_idle); |
1d2a314c | 3175 | |
0260c420 | 3176 | /* belongs in i915_gem_gtt.h */ |
d09105c6 | 3177 | static inline void i915_gem_chipset_flush(struct drm_device *dev) |
e76e9aeb BW |
3178 | { |
3179 | if (INTEL_INFO(dev)->gen < 6) | |
3180 | intel_gtt_chipset_flush(); | |
3181 | } | |
246cbfb5 | 3182 | |
9797fbfb | 3183 | /* i915_gem_stolen.c */ |
d713fd49 PZ |
3184 | int i915_gem_stolen_insert_node(struct drm_i915_private *dev_priv, |
3185 | struct drm_mm_node *node, u64 size, | |
3186 | unsigned alignment); | |
a9da512b PZ |
3187 | int i915_gem_stolen_insert_node_in_range(struct drm_i915_private *dev_priv, |
3188 | struct drm_mm_node *node, u64 size, | |
3189 | unsigned alignment, u64 start, | |
3190 | u64 end); | |
d713fd49 PZ |
3191 | void i915_gem_stolen_remove_node(struct drm_i915_private *dev_priv, |
3192 | struct drm_mm_node *node); | |
9797fbfb CW |
3193 | int i915_gem_init_stolen(struct drm_device *dev); |
3194 | void i915_gem_cleanup_stolen(struct drm_device *dev); | |
0104fdbb CW |
3195 | struct drm_i915_gem_object * |
3196 | i915_gem_object_create_stolen(struct drm_device *dev, u32 size); | |
866d12b4 CW |
3197 | struct drm_i915_gem_object * |
3198 | i915_gem_object_create_stolen_for_preallocated(struct drm_device *dev, | |
3199 | u32 stolen_offset, | |
3200 | u32 gtt_offset, | |
3201 | u32 size); | |
9797fbfb | 3202 | |
be6a0376 DV |
3203 | /* i915_gem_shrinker.c */ |
3204 | unsigned long i915_gem_shrink(struct drm_i915_private *dev_priv, | |
14387540 | 3205 | unsigned long target, |
be6a0376 DV |
3206 | unsigned flags); |
3207 | #define I915_SHRINK_PURGEABLE 0x1 | |
3208 | #define I915_SHRINK_UNBOUND 0x2 | |
3209 | #define I915_SHRINK_BOUND 0x4 | |
5763ff04 | 3210 | #define I915_SHRINK_ACTIVE 0x8 |
be6a0376 DV |
3211 | unsigned long i915_gem_shrink_all(struct drm_i915_private *dev_priv); |
3212 | void i915_gem_shrinker_init(struct drm_i915_private *dev_priv); | |
3213 | ||
3214 | ||
673a394b | 3215 | /* i915_gem_tiling.c */ |
2c1792a1 | 3216 | static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj) |
e9b73c67 | 3217 | { |
50227e1c | 3218 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
e9b73c67 CW |
3219 | |
3220 | return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 && | |
3221 | obj->tiling_mode != I915_TILING_NONE; | |
3222 | } | |
3223 | ||
673a394b | 3224 | /* i915_gem_debug.c */ |
23bc5982 CW |
3225 | #if WATCH_LISTS |
3226 | int i915_verify_lists(struct drm_device *dev); | |
673a394b | 3227 | #else |
23bc5982 | 3228 | #define i915_verify_lists(dev) 0 |
673a394b | 3229 | #endif |
1da177e4 | 3230 | |
2017263e | 3231 | /* i915_debugfs.c */ |
27c202ad BG |
3232 | int i915_debugfs_init(struct drm_minor *minor); |
3233 | void i915_debugfs_cleanup(struct drm_minor *minor); | |
f8c168fa | 3234 | #ifdef CONFIG_DEBUG_FS |
249e87de | 3235 | int i915_debugfs_connector_add(struct drm_connector *connector); |
07144428 DL |
3236 | void intel_display_crc_init(struct drm_device *dev); |
3237 | #else | |
101057fa DV |
3238 | static inline int i915_debugfs_connector_add(struct drm_connector *connector) |
3239 | { return 0; } | |
f8c168fa | 3240 | static inline void intel_display_crc_init(struct drm_device *dev) {} |
07144428 | 3241 | #endif |
84734a04 MK |
3242 | |
3243 | /* i915_gpu_error.c */ | |
edc3d884 MK |
3244 | __printf(2, 3) |
3245 | void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...); | |
fc16b48b MK |
3246 | int i915_error_state_to_str(struct drm_i915_error_state_buf *estr, |
3247 | const struct i915_error_state_file_priv *error); | |
4dc955f7 | 3248 | int i915_error_state_buf_init(struct drm_i915_error_state_buf *eb, |
0a4cd7c8 | 3249 | struct drm_i915_private *i915, |
4dc955f7 MK |
3250 | size_t count, loff_t pos); |
3251 | static inline void i915_error_state_buf_release( | |
3252 | struct drm_i915_error_state_buf *eb) | |
3253 | { | |
3254 | kfree(eb->buf); | |
3255 | } | |
58174462 MK |
3256 | void i915_capture_error_state(struct drm_device *dev, bool wedge, |
3257 | const char *error_msg); | |
84734a04 MK |
3258 | void i915_error_state_get(struct drm_device *dev, |
3259 | struct i915_error_state_file_priv *error_priv); | |
3260 | void i915_error_state_put(struct i915_error_state_file_priv *error_priv); | |
3261 | void i915_destroy_error_state(struct drm_device *dev); | |
3262 | ||
3263 | void i915_get_extra_instdone(struct drm_device *dev, uint32_t *instdone); | |
0a4cd7c8 | 3264 | const char *i915_cache_level_str(struct drm_i915_private *i915, int type); |
2017263e | 3265 | |
351e3db2 | 3266 | /* i915_cmd_parser.c */ |
d728c8ef | 3267 | int i915_cmd_parser_get_version(void); |
a4872ba6 OM |
3268 | int i915_cmd_parser_init_ring(struct intel_engine_cs *ring); |
3269 | void i915_cmd_parser_fini_ring(struct intel_engine_cs *ring); | |
3270 | bool i915_needs_cmd_parser(struct intel_engine_cs *ring); | |
3271 | int i915_parse_cmds(struct intel_engine_cs *ring, | |
351e3db2 | 3272 | struct drm_i915_gem_object *batch_obj, |
78a42377 | 3273 | struct drm_i915_gem_object *shadow_batch_obj, |
351e3db2 | 3274 | u32 batch_start_offset, |
b9ffd80e | 3275 | u32 batch_len, |
351e3db2 BV |
3276 | bool is_master); |
3277 | ||
317c35d1 JB |
3278 | /* i915_suspend.c */ |
3279 | extern int i915_save_state(struct drm_device *dev); | |
3280 | extern int i915_restore_state(struct drm_device *dev); | |
0a3e67a4 | 3281 | |
0136db58 BW |
3282 | /* i915_sysfs.c */ |
3283 | void i915_setup_sysfs(struct drm_device *dev_priv); | |
3284 | void i915_teardown_sysfs(struct drm_device *dev_priv); | |
3285 | ||
f899fc64 CW |
3286 | /* intel_i2c.c */ |
3287 | extern int intel_setup_gmbus(struct drm_device *dev); | |
3288 | extern void intel_teardown_gmbus(struct drm_device *dev); | |
88ac7939 JN |
3289 | extern bool intel_gmbus_is_valid_pin(struct drm_i915_private *dev_priv, |
3290 | unsigned int pin); | |
3bd7d909 | 3291 | |
0184df46 JN |
3292 | extern struct i2c_adapter * |
3293 | intel_gmbus_get_adapter(struct drm_i915_private *dev_priv, unsigned int pin); | |
e957d772 CW |
3294 | extern void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed); |
3295 | extern void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit); | |
8f375e10 | 3296 | static inline bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter) |
b8232e90 CW |
3297 | { |
3298 | return container_of(adapter, struct intel_gmbus, adapter)->force_bit; | |
3299 | } | |
f899fc64 CW |
3300 | extern void intel_i2c_reset(struct drm_device *dev); |
3301 | ||
3b617967 | 3302 | /* intel_opregion.c */ |
44834a67 | 3303 | #ifdef CONFIG_ACPI |
27d50c82 | 3304 | extern int intel_opregion_setup(struct drm_device *dev); |
44834a67 CW |
3305 | extern void intel_opregion_init(struct drm_device *dev); |
3306 | extern void intel_opregion_fini(struct drm_device *dev); | |
3b617967 | 3307 | extern void intel_opregion_asle_intr(struct drm_device *dev); |
9c4b0a68 JN |
3308 | extern int intel_opregion_notify_encoder(struct intel_encoder *intel_encoder, |
3309 | bool enable); | |
ecbc5cf3 JN |
3310 | extern int intel_opregion_notify_adapter(struct drm_device *dev, |
3311 | pci_power_t state); | |
65e082c9 | 3312 | #else |
27d50c82 | 3313 | static inline int intel_opregion_setup(struct drm_device *dev) { return 0; } |
44834a67 CW |
3314 | static inline void intel_opregion_init(struct drm_device *dev) { return; } |
3315 | static inline void intel_opregion_fini(struct drm_device *dev) { return; } | |
3b617967 | 3316 | static inline void intel_opregion_asle_intr(struct drm_device *dev) { return; } |
9c4b0a68 JN |
3317 | static inline int |
3318 | intel_opregion_notify_encoder(struct intel_encoder *intel_encoder, bool enable) | |
3319 | { | |
3320 | return 0; | |
3321 | } | |
ecbc5cf3 JN |
3322 | static inline int |
3323 | intel_opregion_notify_adapter(struct drm_device *dev, pci_power_t state) | |
3324 | { | |
3325 | return 0; | |
3326 | } | |
65e082c9 | 3327 | #endif |
8ee1c3db | 3328 | |
723bfd70 JB |
3329 | /* intel_acpi.c */ |
3330 | #ifdef CONFIG_ACPI | |
3331 | extern void intel_register_dsm_handler(void); | |
3332 | extern void intel_unregister_dsm_handler(void); | |
3333 | #else | |
3334 | static inline void intel_register_dsm_handler(void) { return; } | |
3335 | static inline void intel_unregister_dsm_handler(void) { return; } | |
3336 | #endif /* CONFIG_ACPI */ | |
3337 | ||
79e53945 | 3338 | /* modesetting */ |
f817586c | 3339 | extern void intel_modeset_init_hw(struct drm_device *dev); |
79e53945 | 3340 | extern void intel_modeset_init(struct drm_device *dev); |
2c7111db | 3341 | extern void intel_modeset_gem_init(struct drm_device *dev); |
79e53945 | 3342 | extern void intel_modeset_cleanup(struct drm_device *dev); |
4932e2c3 | 3343 | extern void intel_connector_unregister(struct intel_connector *); |
28d52043 | 3344 | extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state); |
043e9bda | 3345 | extern void intel_display_resume(struct drm_device *dev); |
44cec740 | 3346 | extern void i915_redisable_vga(struct drm_device *dev); |
04098753 | 3347 | extern void i915_redisable_vga_power_on(struct drm_device *dev); |
7648fa99 | 3348 | extern bool ironlake_set_drps(struct drm_device *dev, u8 val); |
dde86e2d | 3349 | extern void intel_init_pch_refclk(struct drm_device *dev); |
ffe02b40 | 3350 | extern void intel_set_rps(struct drm_device *dev, u8 val); |
5209b1f4 ID |
3351 | extern void intel_set_memory_cxsr(struct drm_i915_private *dev_priv, |
3352 | bool enable); | |
0206e353 AJ |
3353 | extern void intel_detect_pch(struct drm_device *dev); |
3354 | extern int intel_trans_dp_port_sel(struct drm_crtc *crtc); | |
0136db58 | 3355 | extern int intel_enable_rc6(const struct drm_device *dev); |
3bad0781 | 3356 | |
2911a35b | 3357 | extern bool i915_semaphore_is_enabled(struct drm_device *dev); |
c0c7babc BW |
3358 | int i915_reg_read_ioctl(struct drm_device *dev, void *data, |
3359 | struct drm_file *file); | |
b6359918 MK |
3360 | int i915_get_reset_stats_ioctl(struct drm_device *dev, void *data, |
3361 | struct drm_file *file); | |
575155a9 | 3362 | |
6ef3d427 CW |
3363 | /* overlay */ |
3364 | extern struct intel_overlay_error_state *intel_overlay_capture_error_state(struct drm_device *dev); | |
edc3d884 MK |
3365 | extern void intel_overlay_print_error_state(struct drm_i915_error_state_buf *e, |
3366 | struct intel_overlay_error_state *error); | |
c4a1d9e4 CW |
3367 | |
3368 | extern struct intel_display_error_state *intel_display_capture_error_state(struct drm_device *dev); | |
edc3d884 | 3369 | extern void intel_display_print_error_state(struct drm_i915_error_state_buf *e, |
c4a1d9e4 CW |
3370 | struct drm_device *dev, |
3371 | struct intel_display_error_state *error); | |
6ef3d427 | 3372 | |
151a49d0 TR |
3373 | int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val); |
3374 | int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u32 mbox, u32 val); | |
59de0813 JN |
3375 | |
3376 | /* intel_sideband.c */ | |
707b6e3d D |
3377 | u32 vlv_punit_read(struct drm_i915_private *dev_priv, u32 addr); |
3378 | void vlv_punit_write(struct drm_i915_private *dev_priv, u32 addr, u32 val); | |
64936258 | 3379 | u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr); |
e9f882a3 JN |
3380 | u32 vlv_gpio_nc_read(struct drm_i915_private *dev_priv, u32 reg); |
3381 | void vlv_gpio_nc_write(struct drm_i915_private *dev_priv, u32 reg, u32 val); | |
3382 | u32 vlv_cck_read(struct drm_i915_private *dev_priv, u32 reg); | |
3383 | void vlv_cck_write(struct drm_i915_private *dev_priv, u32 reg, u32 val); | |
3384 | u32 vlv_ccu_read(struct drm_i915_private *dev_priv, u32 reg); | |
3385 | void vlv_ccu_write(struct drm_i915_private *dev_priv, u32 reg, u32 val); | |
f3419158 JB |
3386 | u32 vlv_bunit_read(struct drm_i915_private *dev_priv, u32 reg); |
3387 | void vlv_bunit_write(struct drm_i915_private *dev_priv, u32 reg, u32 val); | |
e9f882a3 JN |
3388 | u32 vlv_gps_core_read(struct drm_i915_private *dev_priv, u32 reg); |
3389 | void vlv_gps_core_write(struct drm_i915_private *dev_priv, u32 reg, u32 val); | |
5e69f97f CML |
3390 | u32 vlv_dpio_read(struct drm_i915_private *dev_priv, enum pipe pipe, int reg); |
3391 | void vlv_dpio_write(struct drm_i915_private *dev_priv, enum pipe pipe, int reg, u32 val); | |
59de0813 JN |
3392 | u32 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg, |
3393 | enum intel_sbi_destination destination); | |
3394 | void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value, | |
3395 | enum intel_sbi_destination destination); | |
e9fe51c6 SK |
3396 | u32 vlv_flisdsi_read(struct drm_i915_private *dev_priv, u32 reg); |
3397 | void vlv_flisdsi_write(struct drm_i915_private *dev_priv, u32 reg, u32 val); | |
0a073b84 | 3398 | |
616bc820 VS |
3399 | int intel_gpu_freq(struct drm_i915_private *dev_priv, int val); |
3400 | int intel_freq_opcode(struct drm_i915_private *dev_priv, int val); | |
c8d9a590 | 3401 | |
0b274481 BW |
3402 | #define I915_READ8(reg) dev_priv->uncore.funcs.mmio_readb(dev_priv, (reg), true) |
3403 | #define I915_WRITE8(reg, val) dev_priv->uncore.funcs.mmio_writeb(dev_priv, (reg), (val), true) | |
3404 | ||
3405 | #define I915_READ16(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), true) | |
3406 | #define I915_WRITE16(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), true) | |
3407 | #define I915_READ16_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), false) | |
3408 | #define I915_WRITE16_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), false) | |
3409 | ||
3410 | #define I915_READ(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), true) | |
3411 | #define I915_WRITE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), true) | |
3412 | #define I915_READ_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), false) | |
3413 | #define I915_WRITE_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), false) | |
3414 | ||
698b3135 CW |
3415 | /* Be very careful with read/write 64-bit values. On 32-bit machines, they |
3416 | * will be implemented using 2 32-bit writes in an arbitrary order with | |
3417 | * an arbitrary delay between them. This can cause the hardware to | |
3418 | * act upon the intermediate value, possibly leading to corruption and | |
3419 | * machine death. You have been warned. | |
3420 | */ | |
0b274481 BW |
3421 | #define I915_WRITE64(reg, val) dev_priv->uncore.funcs.mmio_writeq(dev_priv, (reg), (val), true) |
3422 | #define I915_READ64(reg) dev_priv->uncore.funcs.mmio_readq(dev_priv, (reg), true) | |
cae5852d | 3423 | |
50877445 | 3424 | #define I915_READ64_2x32(lower_reg, upper_reg) ({ \ |
acd29f7b CW |
3425 | u32 upper, lower, old_upper, loop = 0; \ |
3426 | upper = I915_READ(upper_reg); \ | |
ee0a227b | 3427 | do { \ |
acd29f7b | 3428 | old_upper = upper; \ |
ee0a227b | 3429 | lower = I915_READ(lower_reg); \ |
acd29f7b CW |
3430 | upper = I915_READ(upper_reg); \ |
3431 | } while (upper != old_upper && loop++ < 2); \ | |
ee0a227b | 3432 | (u64)upper << 32 | lower; }) |
50877445 | 3433 | |
cae5852d ZN |
3434 | #define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg) |
3435 | #define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg) | |
3436 | ||
a6111f7b CW |
3437 | /* These are untraced mmio-accessors that are only valid to be used inside |
3438 | * criticial sections inside IRQ handlers where forcewake is explicitly | |
3439 | * controlled. | |
3440 | * Think twice, and think again, before using these. | |
3441 | * Note: Should only be used between intel_uncore_forcewake_irqlock() and | |
3442 | * intel_uncore_forcewake_irqunlock(). | |
3443 | */ | |
3444 | #define I915_READ_FW(reg__) readl(dev_priv->regs + (reg__)) | |
3445 | #define I915_WRITE_FW(reg__, val__) writel(val__, dev_priv->regs + (reg__)) | |
3446 | #define POSTING_READ_FW(reg__) (void)I915_READ_FW(reg__) | |
3447 | ||
55bc60db VS |
3448 | /* "Broadcast RGB" property */ |
3449 | #define INTEL_BROADCAST_RGB_AUTO 0 | |
3450 | #define INTEL_BROADCAST_RGB_FULL 1 | |
3451 | #define INTEL_BROADCAST_RGB_LIMITED 2 | |
ba4f01a3 | 3452 | |
766aa1c4 VS |
3453 | static inline uint32_t i915_vgacntrl_reg(struct drm_device *dev) |
3454 | { | |
92e23b99 | 3455 | if (IS_VALLEYVIEW(dev)) |
766aa1c4 | 3456 | return VLV_VGACNTRL; |
92e23b99 SJ |
3457 | else if (INTEL_INFO(dev)->gen >= 5) |
3458 | return CPU_VGACNTRL; | |
766aa1c4 VS |
3459 | else |
3460 | return VGACNTRL; | |
3461 | } | |
3462 | ||
2bb4629a VS |
3463 | static inline void __user *to_user_ptr(u64 address) |
3464 | { | |
3465 | return (void __user *)(uintptr_t)address; | |
3466 | } | |
3467 | ||
df97729f ID |
3468 | static inline unsigned long msecs_to_jiffies_timeout(const unsigned int m) |
3469 | { | |
3470 | unsigned long j = msecs_to_jiffies(m); | |
3471 | ||
3472 | return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1); | |
3473 | } | |
3474 | ||
7bd0e226 DV |
3475 | static inline unsigned long nsecs_to_jiffies_timeout(const u64 n) |
3476 | { | |
3477 | return min_t(u64, MAX_JIFFY_OFFSET, nsecs_to_jiffies64(n) + 1); | |
3478 | } | |
3479 | ||
df97729f ID |
3480 | static inline unsigned long |
3481 | timespec_to_jiffies_timeout(const struct timespec *value) | |
3482 | { | |
3483 | unsigned long j = timespec_to_jiffies(value); | |
3484 | ||
3485 | return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1); | |
3486 | } | |
3487 | ||
dce56b3c PZ |
3488 | /* |
3489 | * If you need to wait X milliseconds between events A and B, but event B | |
3490 | * doesn't happen exactly after event A, you record the timestamp (jiffies) of | |
3491 | * when event A happened, then just before event B you call this function and | |
3492 | * pass the timestamp as the first argument, and X as the second argument. | |
3493 | */ | |
3494 | static inline void | |
3495 | wait_remaining_ms_from_jiffies(unsigned long timestamp_jiffies, int to_wait_ms) | |
3496 | { | |
ec5e0cfb | 3497 | unsigned long target_jiffies, tmp_jiffies, remaining_jiffies; |
dce56b3c PZ |
3498 | |
3499 | /* | |
3500 | * Don't re-read the value of "jiffies" every time since it may change | |
3501 | * behind our back and break the math. | |
3502 | */ | |
3503 | tmp_jiffies = jiffies; | |
3504 | target_jiffies = timestamp_jiffies + | |
3505 | msecs_to_jiffies_timeout(to_wait_ms); | |
3506 | ||
3507 | if (time_after(target_jiffies, tmp_jiffies)) { | |
ec5e0cfb ID |
3508 | remaining_jiffies = target_jiffies - tmp_jiffies; |
3509 | while (remaining_jiffies) | |
3510 | remaining_jiffies = | |
3511 | schedule_timeout_uninterruptible(remaining_jiffies); | |
dce56b3c PZ |
3512 | } |
3513 | } | |
3514 | ||
581c26e8 JH |
3515 | static inline void i915_trace_irq_get(struct intel_engine_cs *ring, |
3516 | struct drm_i915_gem_request *req) | |
3517 | { | |
3518 | if (ring->trace_irq_req == NULL && ring->irq_get(ring)) | |
3519 | i915_gem_request_assign(&ring->trace_irq_req, req); | |
3520 | } | |
3521 | ||
1da177e4 | 3522 | #endif |