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1da177e4 LT |
1 | /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*- |
2 | */ | |
0d6aa60b | 3 | /* |
bc54fd1a | 4 | * |
1da177e4 LT |
5 | * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. |
6 | * All Rights Reserved. | |
bc54fd1a DA |
7 | * |
8 | * Permission is hereby granted, free of charge, to any person obtaining a | |
9 | * copy of this software and associated documentation files (the | |
10 | * "Software"), to deal in the Software without restriction, including | |
11 | * without limitation the rights to use, copy, modify, merge, publish, | |
12 | * distribute, sub license, and/or sell copies of the Software, and to | |
13 | * permit persons to whom the Software is furnished to do so, subject to | |
14 | * the following conditions: | |
15 | * | |
16 | * The above copyright notice and this permission notice (including the | |
17 | * next paragraph) shall be included in all copies or substantial portions | |
18 | * of the Software. | |
19 | * | |
20 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS | |
21 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
22 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. | |
23 | * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR | |
24 | * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, | |
25 | * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE | |
26 | * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. | |
27 | * | |
0d6aa60b | 28 | */ |
1da177e4 LT |
29 | |
30 | #ifndef _I915_DRV_H_ | |
31 | #define _I915_DRV_H_ | |
32 | ||
e9b73c67 CW |
33 | #include <uapi/drm/i915_drm.h> |
34 | ||
585fb111 | 35 | #include "i915_reg.h" |
79e53945 | 36 | #include "intel_bios.h" |
8187a2b7 | 37 | #include "intel_ringbuffer.h" |
0839ccb8 | 38 | #include <linux/io-mapping.h> |
f899fc64 | 39 | #include <linux/i2c.h> |
c167a6fc | 40 | #include <linux/i2c-algo-bit.h> |
0ade6386 | 41 | #include <drm/intel-gtt.h> |
aaa6fd2a | 42 | #include <linux/backlight.h> |
2911a35b | 43 | #include <linux/intel-iommu.h> |
742cbee8 | 44 | #include <linux/kref.h> |
9ee32fea | 45 | #include <linux/pm_qos.h> |
585fb111 | 46 | |
1da177e4 LT |
47 | /* General customization: |
48 | */ | |
49 | ||
50 | #define DRIVER_AUTHOR "Tungsten Graphics, Inc." | |
51 | ||
52 | #define DRIVER_NAME "i915" | |
53 | #define DRIVER_DESC "Intel Graphics" | |
673a394b | 54 | #define DRIVER_DATE "20080730" |
1da177e4 | 55 | |
317c35d1 | 56 | enum pipe { |
752aa88a | 57 | INVALID_PIPE = -1, |
317c35d1 JB |
58 | PIPE_A = 0, |
59 | PIPE_B, | |
9db4a9c7 | 60 | PIPE_C, |
a57c774a AK |
61 | _PIPE_EDP, |
62 | I915_MAX_PIPES = _PIPE_EDP | |
317c35d1 | 63 | }; |
9db4a9c7 | 64 | #define pipe_name(p) ((p) + 'A') |
317c35d1 | 65 | |
a5c961d1 PZ |
66 | enum transcoder { |
67 | TRANSCODER_A = 0, | |
68 | TRANSCODER_B, | |
69 | TRANSCODER_C, | |
a57c774a AK |
70 | TRANSCODER_EDP, |
71 | I915_MAX_TRANSCODERS | |
a5c961d1 PZ |
72 | }; |
73 | #define transcoder_name(t) ((t) + 'A') | |
74 | ||
80824003 JB |
75 | enum plane { |
76 | PLANE_A = 0, | |
77 | PLANE_B, | |
9db4a9c7 | 78 | PLANE_C, |
80824003 | 79 | }; |
9db4a9c7 | 80 | #define plane_name(p) ((p) + 'A') |
52440211 | 81 | |
22d3fd46 | 82 | #define sprite_name(p, s) ((p) * INTEL_INFO(dev)->num_sprites + (s) + 'A') |
06da8da2 | 83 | |
2b139522 ED |
84 | enum port { |
85 | PORT_A = 0, | |
86 | PORT_B, | |
87 | PORT_C, | |
88 | PORT_D, | |
89 | PORT_E, | |
90 | I915_MAX_PORTS | |
91 | }; | |
92 | #define port_name(p) ((p) + 'A') | |
93 | ||
e4607fcf CML |
94 | #define I915_NUM_PHYS_VLV 1 |
95 | ||
96 | enum dpio_channel { | |
97 | DPIO_CH0, | |
98 | DPIO_CH1 | |
99 | }; | |
100 | ||
101 | enum dpio_phy { | |
102 | DPIO_PHY0, | |
103 | DPIO_PHY1 | |
104 | }; | |
105 | ||
b97186f0 PZ |
106 | enum intel_display_power_domain { |
107 | POWER_DOMAIN_PIPE_A, | |
108 | POWER_DOMAIN_PIPE_B, | |
109 | POWER_DOMAIN_PIPE_C, | |
110 | POWER_DOMAIN_PIPE_A_PANEL_FITTER, | |
111 | POWER_DOMAIN_PIPE_B_PANEL_FITTER, | |
112 | POWER_DOMAIN_PIPE_C_PANEL_FITTER, | |
113 | POWER_DOMAIN_TRANSCODER_A, | |
114 | POWER_DOMAIN_TRANSCODER_B, | |
115 | POWER_DOMAIN_TRANSCODER_C, | |
f52e353e | 116 | POWER_DOMAIN_TRANSCODER_EDP, |
cdf8dd7f | 117 | POWER_DOMAIN_VGA, |
fbeeaa23 | 118 | POWER_DOMAIN_AUDIO, |
baa70707 | 119 | POWER_DOMAIN_INIT, |
bddc7645 ID |
120 | |
121 | POWER_DOMAIN_NUM, | |
b97186f0 PZ |
122 | }; |
123 | ||
bddc7645 ID |
124 | #define POWER_DOMAIN_MASK (BIT(POWER_DOMAIN_NUM) - 1) |
125 | ||
b97186f0 PZ |
126 | #define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A) |
127 | #define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \ | |
128 | ((pipe) + POWER_DOMAIN_PIPE_A_PANEL_FITTER) | |
f52e353e ID |
129 | #define POWER_DOMAIN_TRANSCODER(tran) \ |
130 | ((tran) == TRANSCODER_EDP ? POWER_DOMAIN_TRANSCODER_EDP : \ | |
131 | (tran) + POWER_DOMAIN_TRANSCODER_A) | |
b97186f0 | 132 | |
bddc7645 ID |
133 | #define HSW_ALWAYS_ON_POWER_DOMAINS ( \ |
134 | BIT(POWER_DOMAIN_PIPE_A) | \ | |
135 | BIT(POWER_DOMAIN_TRANSCODER_EDP)) | |
6745a2ce PZ |
136 | #define BDW_ALWAYS_ON_POWER_DOMAINS ( \ |
137 | BIT(POWER_DOMAIN_PIPE_A) | \ | |
138 | BIT(POWER_DOMAIN_TRANSCODER_EDP) | \ | |
139 | BIT(POWER_DOMAIN_PIPE_A_PANEL_FITTER)) | |
bddc7645 | 140 | |
1d843f9d EE |
141 | enum hpd_pin { |
142 | HPD_NONE = 0, | |
143 | HPD_PORT_A = HPD_NONE, /* PORT_A is internal */ | |
144 | HPD_TV = HPD_NONE, /* TV is known to be unreliable */ | |
145 | HPD_CRT, | |
146 | HPD_SDVO_B, | |
147 | HPD_SDVO_C, | |
148 | HPD_PORT_B, | |
149 | HPD_PORT_C, | |
150 | HPD_PORT_D, | |
151 | HPD_NUM_PINS | |
152 | }; | |
153 | ||
2a2d5482 CW |
154 | #define I915_GEM_GPU_DOMAINS \ |
155 | (I915_GEM_DOMAIN_RENDER | \ | |
156 | I915_GEM_DOMAIN_SAMPLER | \ | |
157 | I915_GEM_DOMAIN_COMMAND | \ | |
158 | I915_GEM_DOMAIN_INSTRUCTION | \ | |
159 | I915_GEM_DOMAIN_VERTEX) | |
62fdfeaf | 160 | |
7eb552ae | 161 | #define for_each_pipe(p) for ((p) = 0; (p) < INTEL_INFO(dev)->num_pipes; (p)++) |
9db4a9c7 | 162 | |
6c2b7c12 DV |
163 | #define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \ |
164 | list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \ | |
165 | if ((intel_encoder)->base.crtc == (__crtc)) | |
166 | ||
53f5e3ca JB |
167 | #define for_each_connector_on_encoder(dev, __encoder, intel_connector) \ |
168 | list_for_each_entry((intel_connector), &(dev)->mode_config.connector_list, base.head) \ | |
169 | if ((intel_connector)->base.encoder == (__encoder)) | |
170 | ||
e7b903d2 DV |
171 | struct drm_i915_private; |
172 | ||
46edb027 DV |
173 | enum intel_dpll_id { |
174 | DPLL_ID_PRIVATE = -1, /* non-shared dpll in use */ | |
175 | /* real shared dpll ids must be >= 0 */ | |
176 | DPLL_ID_PCH_PLL_A, | |
177 | DPLL_ID_PCH_PLL_B, | |
178 | }; | |
179 | #define I915_NUM_PLLS 2 | |
180 | ||
5358901f | 181 | struct intel_dpll_hw_state { |
66e985c0 | 182 | uint32_t dpll; |
8bcc2795 | 183 | uint32_t dpll_md; |
66e985c0 DV |
184 | uint32_t fp0; |
185 | uint32_t fp1; | |
5358901f DV |
186 | }; |
187 | ||
e72f9fbf | 188 | struct intel_shared_dpll { |
ee7b9f93 JB |
189 | int refcount; /* count of number of CRTCs sharing this PLL */ |
190 | int active; /* count of number of active CRTCs (i.e. DPMS on) */ | |
191 | bool on; /* is the PLL actually active? Disabled during modeset */ | |
46edb027 DV |
192 | const char *name; |
193 | /* should match the index in the dev_priv->shared_dplls array */ | |
194 | enum intel_dpll_id id; | |
5358901f | 195 | struct intel_dpll_hw_state hw_state; |
15bdd4cf DV |
196 | void (*mode_set)(struct drm_i915_private *dev_priv, |
197 | struct intel_shared_dpll *pll); | |
e7b903d2 DV |
198 | void (*enable)(struct drm_i915_private *dev_priv, |
199 | struct intel_shared_dpll *pll); | |
200 | void (*disable)(struct drm_i915_private *dev_priv, | |
201 | struct intel_shared_dpll *pll); | |
5358901f DV |
202 | bool (*get_hw_state)(struct drm_i915_private *dev_priv, |
203 | struct intel_shared_dpll *pll, | |
204 | struct intel_dpll_hw_state *hw_state); | |
ee7b9f93 | 205 | }; |
ee7b9f93 | 206 | |
e69d0bc1 DV |
207 | /* Used by dp and fdi links */ |
208 | struct intel_link_m_n { | |
209 | uint32_t tu; | |
210 | uint32_t gmch_m; | |
211 | uint32_t gmch_n; | |
212 | uint32_t link_m; | |
213 | uint32_t link_n; | |
214 | }; | |
215 | ||
216 | void intel_link_compute_m_n(int bpp, int nlanes, | |
217 | int pixel_clock, int link_clock, | |
218 | struct intel_link_m_n *m_n); | |
219 | ||
6441ab5f PZ |
220 | struct intel_ddi_plls { |
221 | int spll_refcount; | |
222 | int wrpll1_refcount; | |
223 | int wrpll2_refcount; | |
224 | }; | |
225 | ||
1da177e4 LT |
226 | /* Interface history: |
227 | * | |
228 | * 1.1: Original. | |
0d6aa60b DA |
229 | * 1.2: Add Power Management |
230 | * 1.3: Add vblank support | |
de227f5f | 231 | * 1.4: Fix cmdbuffer path, add heap destroy |
702880f2 | 232 | * 1.5: Add vblank pipe configuration |
2228ed67 MD |
233 | * 1.6: - New ioctl for scheduling buffer swaps on vertical blank |
234 | * - Support vertical blank on secondary display pipe | |
1da177e4 LT |
235 | */ |
236 | #define DRIVER_MAJOR 1 | |
2228ed67 | 237 | #define DRIVER_MINOR 6 |
1da177e4 LT |
238 | #define DRIVER_PATCHLEVEL 0 |
239 | ||
23bc5982 | 240 | #define WATCH_LISTS 0 |
42d6ab48 | 241 | #define WATCH_GTT 0 |
673a394b | 242 | |
71acb5eb DA |
243 | #define I915_GEM_PHYS_CURSOR_0 1 |
244 | #define I915_GEM_PHYS_CURSOR_1 2 | |
245 | #define I915_GEM_PHYS_OVERLAY_REGS 3 | |
246 | #define I915_MAX_PHYS_OBJECT (I915_GEM_PHYS_OVERLAY_REGS) | |
247 | ||
248 | struct drm_i915_gem_phys_object { | |
249 | int id; | |
250 | struct page **page_list; | |
251 | drm_dma_handle_t *handle; | |
05394f39 | 252 | struct drm_i915_gem_object *cur_obj; |
71acb5eb DA |
253 | }; |
254 | ||
0a3e67a4 JB |
255 | struct opregion_header; |
256 | struct opregion_acpi; | |
257 | struct opregion_swsci; | |
258 | struct opregion_asle; | |
259 | ||
8ee1c3db | 260 | struct intel_opregion { |
5bc4418b BW |
261 | struct opregion_header __iomem *header; |
262 | struct opregion_acpi __iomem *acpi; | |
263 | struct opregion_swsci __iomem *swsci; | |
ebde53c7 JN |
264 | u32 swsci_gbda_sub_functions; |
265 | u32 swsci_sbcb_sub_functions; | |
5bc4418b BW |
266 | struct opregion_asle __iomem *asle; |
267 | void __iomem *vbt; | |
01fe9dbd | 268 | u32 __iomem *lid_state; |
91a60f20 | 269 | struct work_struct asle_work; |
8ee1c3db | 270 | }; |
44834a67 | 271 | #define OPREGION_SIZE (8*1024) |
8ee1c3db | 272 | |
6ef3d427 CW |
273 | struct intel_overlay; |
274 | struct intel_overlay_error_state; | |
275 | ||
7c1c2871 DA |
276 | struct drm_i915_master_private { |
277 | drm_local_map_t *sarea; | |
278 | struct _drm_i915_sarea *sarea_priv; | |
279 | }; | |
de151cf6 | 280 | #define I915_FENCE_REG_NONE -1 |
42b5aeab VS |
281 | #define I915_MAX_NUM_FENCES 32 |
282 | /* 32 fences + sign bit for FENCE_REG_NONE */ | |
283 | #define I915_MAX_NUM_FENCE_BITS 6 | |
de151cf6 JB |
284 | |
285 | struct drm_i915_fence_reg { | |
007cc8ac | 286 | struct list_head lru_list; |
caea7476 | 287 | struct drm_i915_gem_object *obj; |
1690e1eb | 288 | int pin_count; |
de151cf6 | 289 | }; |
7c1c2871 | 290 | |
9b9d172d | 291 | struct sdvo_device_mapping { |
e957d772 | 292 | u8 initialized; |
9b9d172d | 293 | u8 dvo_port; |
294 | u8 slave_addr; | |
295 | u8 dvo_wiring; | |
e957d772 | 296 | u8 i2c_pin; |
b1083333 | 297 | u8 ddc_pin; |
9b9d172d | 298 | }; |
299 | ||
c4a1d9e4 CW |
300 | struct intel_display_error_state; |
301 | ||
63eeaf38 | 302 | struct drm_i915_error_state { |
742cbee8 | 303 | struct kref ref; |
585b0288 BW |
304 | struct timeval time; |
305 | ||
306 | /* Generic register state */ | |
63eeaf38 JB |
307 | u32 eir; |
308 | u32 pgtbl_er; | |
be998e2e | 309 | u32 ier; |
b9a3906b | 310 | u32 ccid; |
0f3b6849 CW |
311 | u32 derrmr; |
312 | u32 forcewake; | |
585b0288 BW |
313 | u32 error; /* gen6+ */ |
314 | u32 err_int; /* gen7 */ | |
315 | u32 done_reg; | |
91ec5d11 BW |
316 | u32 gac_eco; |
317 | u32 gam_ecochk; | |
318 | u32 gab_ctl; | |
319 | u32 gfx_mode; | |
585b0288 | 320 | u32 extra_instdone[I915_NUM_INSTDONE_REG]; |
9db4a9c7 | 321 | u32 pipestat[I915_MAX_PIPES]; |
585b0288 BW |
322 | u64 fence[I915_MAX_NUM_FENCES]; |
323 | struct intel_overlay_error_state *overlay; | |
324 | struct intel_display_error_state *display; | |
325 | ||
52d39a21 | 326 | struct drm_i915_error_ring { |
372fbb8e | 327 | bool valid; |
362b8af7 BW |
328 | /* Software tracked state */ |
329 | bool waiting; | |
330 | int hangcheck_score; | |
331 | enum intel_ring_hangcheck_action hangcheck_action; | |
332 | int num_requests; | |
333 | ||
334 | /* our own tracking of ring head and tail */ | |
335 | u32 cpu_ring_head; | |
336 | u32 cpu_ring_tail; | |
337 | ||
338 | u32 semaphore_seqno[I915_NUM_RINGS - 1]; | |
339 | ||
340 | /* Register state */ | |
341 | u32 tail; | |
342 | u32 head; | |
343 | u32 ctl; | |
344 | u32 hws; | |
345 | u32 ipeir; | |
346 | u32 ipehr; | |
347 | u32 instdone; | |
348 | u32 acthd; | |
349 | u32 bbstate; | |
350 | u32 instpm; | |
351 | u32 instps; | |
352 | u32 seqno; | |
353 | u64 bbaddr; | |
354 | u32 fault_reg; | |
355 | u32 faddr; | |
356 | u32 rc_psmi; /* sleep state */ | |
357 | u32 semaphore_mboxes[I915_NUM_RINGS - 1]; | |
358 | ||
52d39a21 CW |
359 | struct drm_i915_error_object { |
360 | int page_count; | |
361 | u32 gtt_offset; | |
362 | u32 *pages[0]; | |
ab0e7ff9 | 363 | } *ringbuffer, *batchbuffer, *wa_batchbuffer, *ctx, *hws_page; |
362b8af7 | 364 | |
52d39a21 CW |
365 | struct drm_i915_error_request { |
366 | long jiffies; | |
367 | u32 seqno; | |
ee4f42b1 | 368 | u32 tail; |
52d39a21 | 369 | } *requests; |
6c7a01ec BW |
370 | |
371 | struct { | |
372 | u32 gfx_mode; | |
373 | union { | |
374 | u64 pdp[4]; | |
375 | u32 pp_dir_base; | |
376 | }; | |
377 | } vm_info; | |
ab0e7ff9 CW |
378 | |
379 | pid_t pid; | |
380 | char comm[TASK_COMM_LEN]; | |
52d39a21 | 381 | } ring[I915_NUM_RINGS]; |
9df30794 | 382 | struct drm_i915_error_buffer { |
a779e5ab | 383 | u32 size; |
9df30794 | 384 | u32 name; |
0201f1ec | 385 | u32 rseqno, wseqno; |
9df30794 CW |
386 | u32 gtt_offset; |
387 | u32 read_domains; | |
388 | u32 write_domain; | |
4b9de737 | 389 | s32 fence_reg:I915_MAX_NUM_FENCE_BITS; |
9df30794 CW |
390 | s32 pinned:2; |
391 | u32 tiling:2; | |
392 | u32 dirty:1; | |
393 | u32 purgeable:1; | |
5d1333fc | 394 | s32 ring:4; |
f56383cb | 395 | u32 cache_level:3; |
95f5301d | 396 | } **active_bo, **pinned_bo; |
6c7a01ec | 397 | |
95f5301d | 398 | u32 *active_bo_count, *pinned_bo_count; |
63eeaf38 JB |
399 | }; |
400 | ||
7bd688cd | 401 | struct intel_connector; |
b8cecdf5 | 402 | struct intel_crtc_config; |
0e8ffe1b | 403 | struct intel_crtc; |
ee9300bb DV |
404 | struct intel_limit; |
405 | struct dpll; | |
b8cecdf5 | 406 | |
e70236a8 | 407 | struct drm_i915_display_funcs { |
ee5382ae | 408 | bool (*fbc_enabled)(struct drm_device *dev); |
993495ae | 409 | void (*enable_fbc)(struct drm_crtc *crtc); |
e70236a8 JB |
410 | void (*disable_fbc)(struct drm_device *dev); |
411 | int (*get_display_clock_speed)(struct drm_device *dev); | |
412 | int (*get_fifo_size)(struct drm_device *dev, int plane); | |
ee9300bb DV |
413 | /** |
414 | * find_dpll() - Find the best values for the PLL | |
415 | * @limit: limits for the PLL | |
416 | * @crtc: current CRTC | |
417 | * @target: target frequency in kHz | |
418 | * @refclk: reference clock frequency in kHz | |
419 | * @match_clock: if provided, @best_clock P divider must | |
420 | * match the P divider from @match_clock | |
421 | * used for LVDS downclocking | |
422 | * @best_clock: best PLL values found | |
423 | * | |
424 | * Returns true on success, false on failure. | |
425 | */ | |
426 | bool (*find_dpll)(const struct intel_limit *limit, | |
427 | struct drm_crtc *crtc, | |
428 | int target, int refclk, | |
429 | struct dpll *match_clock, | |
430 | struct dpll *best_clock); | |
46ba614c | 431 | void (*update_wm)(struct drm_crtc *crtc); |
adf3d35e VS |
432 | void (*update_sprite_wm)(struct drm_plane *plane, |
433 | struct drm_crtc *crtc, | |
4c4ff43a | 434 | uint32_t sprite_width, int pixel_size, |
bdd57d03 | 435 | bool enable, bool scaled); |
47fab737 | 436 | void (*modeset_global_resources)(struct drm_device *dev); |
0e8ffe1b DV |
437 | /* Returns the active state of the crtc, and if the crtc is active, |
438 | * fills out the pipe-config with the hw state. */ | |
439 | bool (*get_pipe_config)(struct intel_crtc *, | |
440 | struct intel_crtc_config *); | |
f564048e | 441 | int (*crtc_mode_set)(struct drm_crtc *crtc, |
f564048e EA |
442 | int x, int y, |
443 | struct drm_framebuffer *old_fb); | |
76e5a89c DV |
444 | void (*crtc_enable)(struct drm_crtc *crtc); |
445 | void (*crtc_disable)(struct drm_crtc *crtc); | |
ee7b9f93 | 446 | void (*off)(struct drm_crtc *crtc); |
e0dac65e | 447 | void (*write_eld)(struct drm_connector *connector, |
34427052 JN |
448 | struct drm_crtc *crtc, |
449 | struct drm_display_mode *mode); | |
674cf967 | 450 | void (*fdi_link_train)(struct drm_crtc *crtc); |
6067aaea | 451 | void (*init_clock_gating)(struct drm_device *dev); |
8c9f3aaf JB |
452 | int (*queue_flip)(struct drm_device *dev, struct drm_crtc *crtc, |
453 | struct drm_framebuffer *fb, | |
ed8d1975 KP |
454 | struct drm_i915_gem_object *obj, |
455 | uint32_t flags); | |
17638cd6 JB |
456 | int (*update_plane)(struct drm_crtc *crtc, struct drm_framebuffer *fb, |
457 | int x, int y); | |
20afbda2 | 458 | void (*hpd_irq_setup)(struct drm_device *dev); |
e70236a8 JB |
459 | /* clock updates for mode set */ |
460 | /* cursor updates */ | |
461 | /* render clock increase/decrease */ | |
462 | /* display clock increase/decrease */ | |
463 | /* pll clock increase/decrease */ | |
7bd688cd JN |
464 | |
465 | int (*setup_backlight)(struct intel_connector *connector); | |
7bd688cd JN |
466 | uint32_t (*get_backlight)(struct intel_connector *connector); |
467 | void (*set_backlight)(struct intel_connector *connector, | |
468 | uint32_t level); | |
469 | void (*disable_backlight)(struct intel_connector *connector); | |
470 | void (*enable_backlight)(struct intel_connector *connector); | |
e70236a8 JB |
471 | }; |
472 | ||
907b28c5 | 473 | struct intel_uncore_funcs { |
c8d9a590 D |
474 | void (*force_wake_get)(struct drm_i915_private *dev_priv, |
475 | int fw_engine); | |
476 | void (*force_wake_put)(struct drm_i915_private *dev_priv, | |
477 | int fw_engine); | |
0b274481 BW |
478 | |
479 | uint8_t (*mmio_readb)(struct drm_i915_private *dev_priv, off_t offset, bool trace); | |
480 | uint16_t (*mmio_readw)(struct drm_i915_private *dev_priv, off_t offset, bool trace); | |
481 | uint32_t (*mmio_readl)(struct drm_i915_private *dev_priv, off_t offset, bool trace); | |
482 | uint64_t (*mmio_readq)(struct drm_i915_private *dev_priv, off_t offset, bool trace); | |
483 | ||
484 | void (*mmio_writeb)(struct drm_i915_private *dev_priv, off_t offset, | |
485 | uint8_t val, bool trace); | |
486 | void (*mmio_writew)(struct drm_i915_private *dev_priv, off_t offset, | |
487 | uint16_t val, bool trace); | |
488 | void (*mmio_writel)(struct drm_i915_private *dev_priv, off_t offset, | |
489 | uint32_t val, bool trace); | |
490 | void (*mmio_writeq)(struct drm_i915_private *dev_priv, off_t offset, | |
491 | uint64_t val, bool trace); | |
990bbdad CW |
492 | }; |
493 | ||
907b28c5 CW |
494 | struct intel_uncore { |
495 | spinlock_t lock; /** lock is also taken in irq contexts. */ | |
496 | ||
497 | struct intel_uncore_funcs funcs; | |
498 | ||
499 | unsigned fifo_count; | |
500 | unsigned forcewake_count; | |
aec347ab | 501 | |
940aece4 D |
502 | unsigned fw_rendercount; |
503 | unsigned fw_mediacount; | |
504 | ||
8232644c | 505 | struct timer_list force_wake_timer; |
907b28c5 CW |
506 | }; |
507 | ||
79fc46df DL |
508 | #define DEV_INFO_FOR_EACH_FLAG(func, sep) \ |
509 | func(is_mobile) sep \ | |
510 | func(is_i85x) sep \ | |
511 | func(is_i915g) sep \ | |
512 | func(is_i945gm) sep \ | |
513 | func(is_g33) sep \ | |
514 | func(need_gfx_hws) sep \ | |
515 | func(is_g4x) sep \ | |
516 | func(is_pineview) sep \ | |
517 | func(is_broadwater) sep \ | |
518 | func(is_crestline) sep \ | |
519 | func(is_ivybridge) sep \ | |
520 | func(is_valleyview) sep \ | |
521 | func(is_haswell) sep \ | |
b833d685 | 522 | func(is_preliminary) sep \ |
79fc46df DL |
523 | func(has_fbc) sep \ |
524 | func(has_pipe_cxsr) sep \ | |
525 | func(has_hotplug) sep \ | |
526 | func(cursor_needs_physical) sep \ | |
527 | func(has_overlay) sep \ | |
528 | func(overlay_needs_physical) sep \ | |
529 | func(supports_tv) sep \ | |
dd93be58 | 530 | func(has_llc) sep \ |
30568c45 DL |
531 | func(has_ddi) sep \ |
532 | func(has_fpga_dbg) | |
c96ea64e | 533 | |
a587f779 DL |
534 | #define DEFINE_FLAG(name) u8 name:1 |
535 | #define SEP_SEMICOLON ; | |
c96ea64e | 536 | |
cfdf1fa2 | 537 | struct intel_device_info { |
10fce67a | 538 | u32 display_mmio_offset; |
7eb552ae | 539 | u8 num_pipes:3; |
22d3fd46 | 540 | u8 num_sprites:2; |
c96c3a8c | 541 | u8 gen; |
73ae478c | 542 | u8 ring_mask; /* Rings supported by the HW */ |
a587f779 | 543 | DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG, SEP_SEMICOLON); |
a57c774a AK |
544 | /* Register offsets for the various display pipes and transcoders */ |
545 | int pipe_offsets[I915_MAX_TRANSCODERS]; | |
546 | int trans_offsets[I915_MAX_TRANSCODERS]; | |
547 | int dpll_offsets[I915_MAX_PIPES]; | |
548 | int dpll_md_offsets[I915_MAX_PIPES]; | |
549 | int palette_offsets[I915_MAX_PIPES]; | |
cfdf1fa2 KH |
550 | }; |
551 | ||
a587f779 DL |
552 | #undef DEFINE_FLAG |
553 | #undef SEP_SEMICOLON | |
554 | ||
7faf1ab2 DV |
555 | enum i915_cache_level { |
556 | I915_CACHE_NONE = 0, | |
350ec881 CW |
557 | I915_CACHE_LLC, /* also used for snoopable memory on non-LLC */ |
558 | I915_CACHE_L3_LLC, /* gen7+, L3 sits between the domain specifc | |
559 | caches, eg sampler/render caches, and the | |
560 | large Last-Level-Cache. LLC is coherent with | |
561 | the CPU, but L3 is only visible to the GPU. */ | |
651d794f | 562 | I915_CACHE_WT, /* hsw:gt3e WriteThrough for scanouts */ |
7faf1ab2 DV |
563 | }; |
564 | ||
2d04befb KG |
565 | typedef uint32_t gen6_gtt_pte_t; |
566 | ||
6f65e29a BW |
567 | /** |
568 | * A VMA represents a GEM BO that is bound into an address space. Therefore, a | |
569 | * VMA's presence cannot be guaranteed before binding, or after unbinding the | |
570 | * object into/from the address space. | |
571 | * | |
572 | * To make things as simple as possible (ie. no refcounting), a VMA's lifetime | |
573 | * will always be <= an objects lifetime. So object refcounting should cover us. | |
574 | */ | |
575 | struct i915_vma { | |
576 | struct drm_mm_node node; | |
577 | struct drm_i915_gem_object *obj; | |
578 | struct i915_address_space *vm; | |
579 | ||
580 | /** This object's place on the active/inactive lists */ | |
581 | struct list_head mm_list; | |
582 | ||
583 | struct list_head vma_link; /* Link in the object's VMA list */ | |
584 | ||
585 | /** This vma's place in the batchbuffer or on the eviction list */ | |
586 | struct list_head exec_list; | |
587 | ||
588 | /** | |
589 | * Used for performing relocations during execbuffer insertion. | |
590 | */ | |
591 | struct hlist_node exec_node; | |
592 | unsigned long exec_handle; | |
593 | struct drm_i915_gem_exec_object2 *exec_entry; | |
594 | ||
595 | /** | |
596 | * How many users have pinned this object in GTT space. The following | |
597 | * users can each hold at most one reference: pwrite/pread, pin_ioctl | |
598 | * (via user_pin_count), execbuffer (objects are not allowed multiple | |
599 | * times for the same batchbuffer), and the framebuffer code. When | |
600 | * switching/pageflipping, the framebuffer code has at most two buffers | |
601 | * pinned per crtc. | |
602 | * | |
603 | * In the worst case this is 1 + 1 + 1 + 2*2 = 7. That would fit into 3 | |
604 | * bits with absolutely no headroom. So use 4 bits. */ | |
605 | unsigned int pin_count:4; | |
606 | #define DRM_I915_GEM_OBJECT_MAX_PIN_COUNT 0xf | |
607 | ||
608 | /** Unmap an object from an address space. This usually consists of | |
609 | * setting the valid PTE entries to a reserved scratch page. */ | |
610 | void (*unbind_vma)(struct i915_vma *vma); | |
611 | /* Map an object into an address space with the given cache flags. */ | |
612 | #define GLOBAL_BIND (1<<0) | |
613 | void (*bind_vma)(struct i915_vma *vma, | |
614 | enum i915_cache_level cache_level, | |
615 | u32 flags); | |
616 | }; | |
617 | ||
853ba5d2 | 618 | struct i915_address_space { |
93bd8649 | 619 | struct drm_mm mm; |
853ba5d2 | 620 | struct drm_device *dev; |
a7bbbd63 | 621 | struct list_head global_link; |
853ba5d2 BW |
622 | unsigned long start; /* Start offset always 0 for dri2 */ |
623 | size_t total; /* size addr space maps (ex. 2GB for ggtt) */ | |
624 | ||
625 | struct { | |
626 | dma_addr_t addr; | |
627 | struct page *page; | |
628 | } scratch; | |
629 | ||
5cef07e1 BW |
630 | /** |
631 | * List of objects currently involved in rendering. | |
632 | * | |
633 | * Includes buffers having the contents of their GPU caches | |
634 | * flushed, not necessarily primitives. last_rendering_seqno | |
635 | * represents when the rendering involved will be completed. | |
636 | * | |
637 | * A reference is held on the buffer while on this list. | |
638 | */ | |
639 | struct list_head active_list; | |
640 | ||
641 | /** | |
642 | * LRU list of objects which are not in the ringbuffer and | |
643 | * are ready to unbind, but are still in the GTT. | |
644 | * | |
645 | * last_rendering_seqno is 0 while an object is in this list. | |
646 | * | |
647 | * A reference is not held on the buffer while on this list, | |
648 | * as merely being GTT-bound shouldn't prevent its being | |
649 | * freed, and we'll pull it off the list in the free path. | |
650 | */ | |
651 | struct list_head inactive_list; | |
652 | ||
853ba5d2 BW |
653 | /* FIXME: Need a more generic return type */ |
654 | gen6_gtt_pte_t (*pte_encode)(dma_addr_t addr, | |
b35b380e BW |
655 | enum i915_cache_level level, |
656 | bool valid); /* Create a valid PTE */ | |
853ba5d2 | 657 | void (*clear_range)(struct i915_address_space *vm, |
782f1495 BW |
658 | uint64_t start, |
659 | uint64_t length, | |
828c7908 | 660 | bool use_scratch); |
853ba5d2 BW |
661 | void (*insert_entries)(struct i915_address_space *vm, |
662 | struct sg_table *st, | |
782f1495 | 663 | uint64_t start, |
853ba5d2 BW |
664 | enum i915_cache_level cache_level); |
665 | void (*cleanup)(struct i915_address_space *vm); | |
666 | }; | |
667 | ||
5d4545ae BW |
668 | /* The Graphics Translation Table is the way in which GEN hardware translates a |
669 | * Graphics Virtual Address into a Physical Address. In addition to the normal | |
670 | * collateral associated with any va->pa translations GEN hardware also has a | |
671 | * portion of the GTT which can be mapped by the CPU and remain both coherent | |
672 | * and correct (in cases like swizzling). That region is referred to as GMADR in | |
673 | * the spec. | |
674 | */ | |
675 | struct i915_gtt { | |
853ba5d2 | 676 | struct i915_address_space base; |
baa09f5f | 677 | size_t stolen_size; /* Total size of stolen memory */ |
5d4545ae BW |
678 | |
679 | unsigned long mappable_end; /* End offset that we can CPU map */ | |
680 | struct io_mapping *mappable; /* Mapping to our CPU mappable region */ | |
681 | phys_addr_t mappable_base; /* PA of our GMADR */ | |
682 | ||
683 | /** "Graphics Stolen Memory" holds the global PTEs */ | |
684 | void __iomem *gsm; | |
a81cc00c BW |
685 | |
686 | bool do_idle_maps; | |
7faf1ab2 | 687 | |
911bdf0a | 688 | int mtrr; |
7faf1ab2 DV |
689 | |
690 | /* global gtt ops */ | |
baa09f5f | 691 | int (*gtt_probe)(struct drm_device *dev, size_t *gtt_total, |
41907ddc BW |
692 | size_t *stolen, phys_addr_t *mappable_base, |
693 | unsigned long *mappable_end); | |
5d4545ae | 694 | }; |
853ba5d2 | 695 | #define gtt_total_entries(gtt) ((gtt).base.total >> PAGE_SHIFT) |
5d4545ae | 696 | |
7ad47cf2 | 697 | #define GEN8_LEGACY_PDPS 4 |
1d2a314c | 698 | struct i915_hw_ppgtt { |
853ba5d2 | 699 | struct i915_address_space base; |
c7c48dfd | 700 | struct kref ref; |
c8d4c0d6 | 701 | struct drm_mm_node node; |
1d2a314c | 702 | unsigned num_pd_entries; |
5abbcca3 | 703 | unsigned num_pd_pages; /* gen8+ */ |
37aca44a BW |
704 | union { |
705 | struct page **pt_pages; | |
7ad47cf2 | 706 | struct page **gen8_pt_pages[GEN8_LEGACY_PDPS]; |
37aca44a BW |
707 | }; |
708 | struct page *pd_pages; | |
37aca44a BW |
709 | union { |
710 | uint32_t pd_offset; | |
7ad47cf2 | 711 | dma_addr_t pd_dma_addr[GEN8_LEGACY_PDPS]; |
37aca44a BW |
712 | }; |
713 | union { | |
714 | dma_addr_t *pt_dma_addr; | |
715 | dma_addr_t *gen8_pt_dma_addr[4]; | |
716 | }; | |
27173f1f | 717 | |
a3d67d23 | 718 | int (*enable)(struct i915_hw_ppgtt *ppgtt); |
eeb9488e BW |
719 | int (*switch_mm)(struct i915_hw_ppgtt *ppgtt, |
720 | struct intel_ring_buffer *ring, | |
721 | bool synchronous); | |
87d60b63 | 722 | void (*debug_dump)(struct i915_hw_ppgtt *ppgtt, struct seq_file *m); |
1d2a314c DV |
723 | }; |
724 | ||
e59ec13d MK |
725 | struct i915_ctx_hang_stats { |
726 | /* This context had batch pending when hang was declared */ | |
727 | unsigned batch_pending; | |
728 | ||
729 | /* This context had batch active when hang was declared */ | |
730 | unsigned batch_active; | |
be62acb4 MK |
731 | |
732 | /* Time when this context was last blamed for a GPU reset */ | |
733 | unsigned long guilty_ts; | |
734 | ||
735 | /* This context is banned to submit more work */ | |
736 | bool banned; | |
e59ec13d | 737 | }; |
40521054 BW |
738 | |
739 | /* This must match up with the value previously used for execbuf2.rsvd1. */ | |
740 | #define DEFAULT_CONTEXT_ID 0 | |
741 | struct i915_hw_context { | |
dce3271b | 742 | struct kref ref; |
40521054 | 743 | int id; |
e0556841 | 744 | bool is_initialized; |
3ccfd19d | 745 | uint8_t remap_slice; |
40521054 | 746 | struct drm_i915_file_private *file_priv; |
0009e46c | 747 | struct intel_ring_buffer *last_ring; |
40521054 | 748 | struct drm_i915_gem_object *obj; |
e59ec13d | 749 | struct i915_ctx_hang_stats hang_stats; |
c7c48dfd | 750 | struct i915_address_space *vm; |
a33afea5 BW |
751 | |
752 | struct list_head link; | |
40521054 BW |
753 | }; |
754 | ||
5c3fe8b0 BW |
755 | struct i915_fbc { |
756 | unsigned long size; | |
757 | unsigned int fb_id; | |
758 | enum plane plane; | |
759 | int y; | |
760 | ||
761 | struct drm_mm_node *compressed_fb; | |
762 | struct drm_mm_node *compressed_llb; | |
763 | ||
764 | struct intel_fbc_work { | |
765 | struct delayed_work work; | |
766 | struct drm_crtc *crtc; | |
767 | struct drm_framebuffer *fb; | |
5c3fe8b0 BW |
768 | } *fbc_work; |
769 | ||
29ebf90f CW |
770 | enum no_fbc_reason { |
771 | FBC_OK, /* FBC is enabled */ | |
772 | FBC_UNSUPPORTED, /* FBC is not supported by this chipset */ | |
5c3fe8b0 BW |
773 | FBC_NO_OUTPUT, /* no outputs enabled to compress */ |
774 | FBC_STOLEN_TOO_SMALL, /* not enough space for buffers */ | |
775 | FBC_UNSUPPORTED_MODE, /* interlace or doublescanned mode */ | |
776 | FBC_MODE_TOO_LARGE, /* mode too large for compression */ | |
777 | FBC_BAD_PLANE, /* fbc not supported on plane */ | |
778 | FBC_NOT_TILED, /* buffer not tiled */ | |
779 | FBC_MULTIPLE_PIPES, /* more than one pipe active */ | |
780 | FBC_MODULE_PARAM, | |
781 | FBC_CHIP_DEFAULT, /* disabled by default on this chip */ | |
782 | } no_fbc_reason; | |
b5e50c3f JB |
783 | }; |
784 | ||
a031d709 RV |
785 | struct i915_psr { |
786 | bool sink_support; | |
787 | bool source_ok; | |
3f51e471 | 788 | }; |
5c3fe8b0 | 789 | |
3bad0781 | 790 | enum intel_pch { |
f0350830 | 791 | PCH_NONE = 0, /* No PCH present */ |
3bad0781 ZW |
792 | PCH_IBX, /* Ibexpeak PCH */ |
793 | PCH_CPT, /* Cougarpoint PCH */ | |
eb877ebf | 794 | PCH_LPT, /* Lynxpoint PCH */ |
40c7ead9 | 795 | PCH_NOP, |
3bad0781 ZW |
796 | }; |
797 | ||
988d6ee8 PZ |
798 | enum intel_sbi_destination { |
799 | SBI_ICLK, | |
800 | SBI_MPHY, | |
801 | }; | |
802 | ||
b690e96c | 803 | #define QUIRK_PIPEA_FORCE (1<<0) |
435793df | 804 | #define QUIRK_LVDS_SSC_DISABLE (1<<1) |
4dca20ef | 805 | #define QUIRK_INVERT_BRIGHTNESS (1<<2) |
b690e96c | 806 | |
8be48d92 | 807 | struct intel_fbdev; |
1630fe75 | 808 | struct intel_fbc_work; |
38651674 | 809 | |
c2b9152f DV |
810 | struct intel_gmbus { |
811 | struct i2c_adapter adapter; | |
f2ce9faf | 812 | u32 force_bit; |
c2b9152f | 813 | u32 reg0; |
36c785f0 | 814 | u32 gpio_reg; |
c167a6fc | 815 | struct i2c_algo_bit_data bit_algo; |
c2b9152f DV |
816 | struct drm_i915_private *dev_priv; |
817 | }; | |
818 | ||
f4c956ad | 819 | struct i915_suspend_saved_registers { |
ba8bbcf6 JB |
820 | u8 saveLBB; |
821 | u32 saveDSPACNTR; | |
822 | u32 saveDSPBCNTR; | |
e948e994 | 823 | u32 saveDSPARB; |
ba8bbcf6 JB |
824 | u32 savePIPEACONF; |
825 | u32 savePIPEBCONF; | |
826 | u32 savePIPEASRC; | |
827 | u32 savePIPEBSRC; | |
828 | u32 saveFPA0; | |
829 | u32 saveFPA1; | |
830 | u32 saveDPLL_A; | |
831 | u32 saveDPLL_A_MD; | |
832 | u32 saveHTOTAL_A; | |
833 | u32 saveHBLANK_A; | |
834 | u32 saveHSYNC_A; | |
835 | u32 saveVTOTAL_A; | |
836 | u32 saveVBLANK_A; | |
837 | u32 saveVSYNC_A; | |
838 | u32 saveBCLRPAT_A; | |
5586c8bc | 839 | u32 saveTRANSACONF; |
42048781 ZW |
840 | u32 saveTRANS_HTOTAL_A; |
841 | u32 saveTRANS_HBLANK_A; | |
842 | u32 saveTRANS_HSYNC_A; | |
843 | u32 saveTRANS_VTOTAL_A; | |
844 | u32 saveTRANS_VBLANK_A; | |
845 | u32 saveTRANS_VSYNC_A; | |
0da3ea12 | 846 | u32 savePIPEASTAT; |
ba8bbcf6 JB |
847 | u32 saveDSPASTRIDE; |
848 | u32 saveDSPASIZE; | |
849 | u32 saveDSPAPOS; | |
585fb111 | 850 | u32 saveDSPAADDR; |
ba8bbcf6 JB |
851 | u32 saveDSPASURF; |
852 | u32 saveDSPATILEOFF; | |
853 | u32 savePFIT_PGM_RATIOS; | |
0eb96d6e | 854 | u32 saveBLC_HIST_CTL; |
ba8bbcf6 JB |
855 | u32 saveBLC_PWM_CTL; |
856 | u32 saveBLC_PWM_CTL2; | |
07bf139b | 857 | u32 saveBLC_HIST_CTL_B; |
42048781 ZW |
858 | u32 saveBLC_CPU_PWM_CTL; |
859 | u32 saveBLC_CPU_PWM_CTL2; | |
ba8bbcf6 JB |
860 | u32 saveFPB0; |
861 | u32 saveFPB1; | |
862 | u32 saveDPLL_B; | |
863 | u32 saveDPLL_B_MD; | |
864 | u32 saveHTOTAL_B; | |
865 | u32 saveHBLANK_B; | |
866 | u32 saveHSYNC_B; | |
867 | u32 saveVTOTAL_B; | |
868 | u32 saveVBLANK_B; | |
869 | u32 saveVSYNC_B; | |
870 | u32 saveBCLRPAT_B; | |
5586c8bc | 871 | u32 saveTRANSBCONF; |
42048781 ZW |
872 | u32 saveTRANS_HTOTAL_B; |
873 | u32 saveTRANS_HBLANK_B; | |
874 | u32 saveTRANS_HSYNC_B; | |
875 | u32 saveTRANS_VTOTAL_B; | |
876 | u32 saveTRANS_VBLANK_B; | |
877 | u32 saveTRANS_VSYNC_B; | |
0da3ea12 | 878 | u32 savePIPEBSTAT; |
ba8bbcf6 JB |
879 | u32 saveDSPBSTRIDE; |
880 | u32 saveDSPBSIZE; | |
881 | u32 saveDSPBPOS; | |
585fb111 | 882 | u32 saveDSPBADDR; |
ba8bbcf6 JB |
883 | u32 saveDSPBSURF; |
884 | u32 saveDSPBTILEOFF; | |
585fb111 JB |
885 | u32 saveVGA0; |
886 | u32 saveVGA1; | |
887 | u32 saveVGA_PD; | |
ba8bbcf6 JB |
888 | u32 saveVGACNTRL; |
889 | u32 saveADPA; | |
890 | u32 saveLVDS; | |
585fb111 JB |
891 | u32 savePP_ON_DELAYS; |
892 | u32 savePP_OFF_DELAYS; | |
ba8bbcf6 JB |
893 | u32 saveDVOA; |
894 | u32 saveDVOB; | |
895 | u32 saveDVOC; | |
896 | u32 savePP_ON; | |
897 | u32 savePP_OFF; | |
898 | u32 savePP_CONTROL; | |
585fb111 | 899 | u32 savePP_DIVISOR; |
ba8bbcf6 JB |
900 | u32 savePFIT_CONTROL; |
901 | u32 save_palette_a[256]; | |
902 | u32 save_palette_b[256]; | |
ba8bbcf6 | 903 | u32 saveFBC_CONTROL; |
0da3ea12 JB |
904 | u32 saveIER; |
905 | u32 saveIIR; | |
906 | u32 saveIMR; | |
42048781 ZW |
907 | u32 saveDEIER; |
908 | u32 saveDEIMR; | |
909 | u32 saveGTIER; | |
910 | u32 saveGTIMR; | |
911 | u32 saveFDI_RXA_IMR; | |
912 | u32 saveFDI_RXB_IMR; | |
1f84e550 | 913 | u32 saveCACHE_MODE_0; |
1f84e550 | 914 | u32 saveMI_ARB_STATE; |
ba8bbcf6 JB |
915 | u32 saveSWF0[16]; |
916 | u32 saveSWF1[16]; | |
917 | u32 saveSWF2[3]; | |
918 | u8 saveMSR; | |
919 | u8 saveSR[8]; | |
123f794f | 920 | u8 saveGR[25]; |
ba8bbcf6 | 921 | u8 saveAR_INDEX; |
a59e122a | 922 | u8 saveAR[21]; |
ba8bbcf6 | 923 | u8 saveDACMASK; |
a59e122a | 924 | u8 saveCR[37]; |
4b9de737 | 925 | uint64_t saveFENCE[I915_MAX_NUM_FENCES]; |
1fd1c624 EA |
926 | u32 saveCURACNTR; |
927 | u32 saveCURAPOS; | |
928 | u32 saveCURABASE; | |
929 | u32 saveCURBCNTR; | |
930 | u32 saveCURBPOS; | |
931 | u32 saveCURBBASE; | |
932 | u32 saveCURSIZE; | |
a4fc5ed6 KP |
933 | u32 saveDP_B; |
934 | u32 saveDP_C; | |
935 | u32 saveDP_D; | |
936 | u32 savePIPEA_GMCH_DATA_M; | |
937 | u32 savePIPEB_GMCH_DATA_M; | |
938 | u32 savePIPEA_GMCH_DATA_N; | |
939 | u32 savePIPEB_GMCH_DATA_N; | |
940 | u32 savePIPEA_DP_LINK_M; | |
941 | u32 savePIPEB_DP_LINK_M; | |
942 | u32 savePIPEA_DP_LINK_N; | |
943 | u32 savePIPEB_DP_LINK_N; | |
42048781 ZW |
944 | u32 saveFDI_RXA_CTL; |
945 | u32 saveFDI_TXA_CTL; | |
946 | u32 saveFDI_RXB_CTL; | |
947 | u32 saveFDI_TXB_CTL; | |
948 | u32 savePFA_CTL_1; | |
949 | u32 savePFB_CTL_1; | |
950 | u32 savePFA_WIN_SZ; | |
951 | u32 savePFB_WIN_SZ; | |
952 | u32 savePFA_WIN_POS; | |
953 | u32 savePFB_WIN_POS; | |
5586c8bc ZW |
954 | u32 savePCH_DREF_CONTROL; |
955 | u32 saveDISP_ARB_CTL; | |
956 | u32 savePIPEA_DATA_M1; | |
957 | u32 savePIPEA_DATA_N1; | |
958 | u32 savePIPEA_LINK_M1; | |
959 | u32 savePIPEA_LINK_N1; | |
960 | u32 savePIPEB_DATA_M1; | |
961 | u32 savePIPEB_DATA_N1; | |
962 | u32 savePIPEB_LINK_M1; | |
963 | u32 savePIPEB_LINK_N1; | |
b5b72e89 | 964 | u32 saveMCHBAR_RENDER_STANDBY; |
cda2bb78 | 965 | u32 savePCH_PORT_HOTPLUG; |
f4c956ad | 966 | }; |
c85aa885 DV |
967 | |
968 | struct intel_gen6_power_mgmt { | |
59cdb63d | 969 | /* work and pm_iir are protected by dev_priv->irq_lock */ |
c85aa885 DV |
970 | struct work_struct work; |
971 | u32 pm_iir; | |
59cdb63d | 972 | |
c85aa885 DV |
973 | u8 cur_delay; |
974 | u8 min_delay; | |
975 | u8 max_delay; | |
52ceb908 | 976 | u8 rpe_delay; |
dd75fdc8 CW |
977 | u8 rp1_delay; |
978 | u8 rp0_delay; | |
31c77388 | 979 | u8 hw_max; |
1a01ab3b | 980 | |
27544369 D |
981 | bool rp_up_masked; |
982 | bool rp_down_masked; | |
983 | ||
dd75fdc8 CW |
984 | int last_adj; |
985 | enum { LOW_POWER, BETWEEN, HIGH_POWER } power; | |
986 | ||
c0951f0c | 987 | bool enabled; |
1a01ab3b | 988 | struct delayed_work delayed_resume_work; |
4fc688ce JB |
989 | |
990 | /* | |
991 | * Protects RPS/RC6 register access and PCU communication. | |
992 | * Must be taken after struct_mutex if nested. | |
993 | */ | |
994 | struct mutex hw_lock; | |
c85aa885 DV |
995 | }; |
996 | ||
1a240d4d DV |
997 | /* defined intel_pm.c */ |
998 | extern spinlock_t mchdev_lock; | |
999 | ||
c85aa885 DV |
1000 | struct intel_ilk_power_mgmt { |
1001 | u8 cur_delay; | |
1002 | u8 min_delay; | |
1003 | u8 max_delay; | |
1004 | u8 fmax; | |
1005 | u8 fstart; | |
1006 | ||
1007 | u64 last_count1; | |
1008 | unsigned long last_time1; | |
1009 | unsigned long chipset_power; | |
1010 | u64 last_count2; | |
1011 | struct timespec last_time2; | |
1012 | unsigned long gfx_power; | |
1013 | u8 corr; | |
1014 | ||
1015 | int c_m; | |
1016 | int r_t; | |
3e373948 DV |
1017 | |
1018 | struct drm_i915_gem_object *pwrctx; | |
1019 | struct drm_i915_gem_object *renderctx; | |
c85aa885 DV |
1020 | }; |
1021 | ||
a38911a3 WX |
1022 | /* Power well structure for haswell */ |
1023 | struct i915_power_well { | |
c1ca727f | 1024 | const char *name; |
6f3ef5dd | 1025 | bool always_on; |
a38911a3 WX |
1026 | /* power well enable/disable usage count */ |
1027 | int count; | |
c1ca727f ID |
1028 | unsigned long domains; |
1029 | void *data; | |
da7e29bd | 1030 | void (*set)(struct drm_i915_private *dev_priv, struct i915_power_well *power_well, |
c1ca727f | 1031 | bool enable); |
da7e29bd | 1032 | bool (*is_enabled)(struct drm_i915_private *dev_priv, |
c1ca727f | 1033 | struct i915_power_well *power_well); |
a38911a3 WX |
1034 | }; |
1035 | ||
83c00f55 | 1036 | struct i915_power_domains { |
baa70707 ID |
1037 | /* |
1038 | * Power wells needed for initialization at driver init and suspend | |
1039 | * time are on. They are kept on until after the first modeset. | |
1040 | */ | |
1041 | bool init_power_on; | |
c1ca727f | 1042 | int power_well_count; |
baa70707 | 1043 | |
83c00f55 | 1044 | struct mutex lock; |
1da51581 | 1045 | int domain_use_count[POWER_DOMAIN_NUM]; |
c1ca727f | 1046 | struct i915_power_well *power_wells; |
83c00f55 ID |
1047 | }; |
1048 | ||
231f42a4 DV |
1049 | struct i915_dri1_state { |
1050 | unsigned allow_batchbuffer : 1; | |
1051 | u32 __iomem *gfx_hws_cpu_addr; | |
1052 | ||
1053 | unsigned int cpp; | |
1054 | int back_offset; | |
1055 | int front_offset; | |
1056 | int current_page; | |
1057 | int page_flipping; | |
1058 | ||
1059 | uint32_t counter; | |
1060 | }; | |
1061 | ||
db1b76ca DV |
1062 | struct i915_ums_state { |
1063 | /** | |
1064 | * Flag if the X Server, and thus DRM, is not currently in | |
1065 | * control of the device. | |
1066 | * | |
1067 | * This is set between LeaveVT and EnterVT. It needs to be | |
1068 | * replaced with a semaphore. It also needs to be | |
1069 | * transitioned away from for kernel modesetting. | |
1070 | */ | |
1071 | int mm_suspended; | |
1072 | }; | |
1073 | ||
35a85ac6 | 1074 | #define MAX_L3_SLICES 2 |
a4da4fa4 | 1075 | struct intel_l3_parity { |
35a85ac6 | 1076 | u32 *remap_info[MAX_L3_SLICES]; |
a4da4fa4 | 1077 | struct work_struct error_work; |
35a85ac6 | 1078 | int which_slice; |
a4da4fa4 DV |
1079 | }; |
1080 | ||
4b5aed62 | 1081 | struct i915_gem_mm { |
4b5aed62 DV |
1082 | /** Memory allocator for GTT stolen memory */ |
1083 | struct drm_mm stolen; | |
4b5aed62 DV |
1084 | /** List of all objects in gtt_space. Used to restore gtt |
1085 | * mappings on resume */ | |
1086 | struct list_head bound_list; | |
1087 | /** | |
1088 | * List of objects which are not bound to the GTT (thus | |
1089 | * are idle and not used by the GPU) but still have | |
1090 | * (presumably uncached) pages still attached. | |
1091 | */ | |
1092 | struct list_head unbound_list; | |
1093 | ||
1094 | /** Usable portion of the GTT for GEM */ | |
1095 | unsigned long stolen_base; /* limited to low memory (32-bit) */ | |
1096 | ||
4b5aed62 DV |
1097 | /** PPGTT used for aliasing the PPGTT with the GTT */ |
1098 | struct i915_hw_ppgtt *aliasing_ppgtt; | |
1099 | ||
1100 | struct shrinker inactive_shrinker; | |
1101 | bool shrinker_no_lock_stealing; | |
1102 | ||
4b5aed62 DV |
1103 | /** LRU list of objects with fence regs on them. */ |
1104 | struct list_head fence_list; | |
1105 | ||
1106 | /** | |
1107 | * We leave the user IRQ off as much as possible, | |
1108 | * but this means that requests will finish and never | |
1109 | * be retired once the system goes idle. Set a timer to | |
1110 | * fire periodically while the ring is running. When it | |
1111 | * fires, go retire requests. | |
1112 | */ | |
1113 | struct delayed_work retire_work; | |
1114 | ||
b29c19b6 CW |
1115 | /** |
1116 | * When we detect an idle GPU, we want to turn on | |
1117 | * powersaving features. So once we see that there | |
1118 | * are no more requests outstanding and no more | |
1119 | * arrive within a small period of time, we fire | |
1120 | * off the idle_work. | |
1121 | */ | |
1122 | struct delayed_work idle_work; | |
1123 | ||
4b5aed62 DV |
1124 | /** |
1125 | * Are we in a non-interruptible section of code like | |
1126 | * modesetting? | |
1127 | */ | |
1128 | bool interruptible; | |
1129 | ||
f62a0076 CW |
1130 | /** |
1131 | * Is the GPU currently considered idle, or busy executing userspace | |
1132 | * requests? Whilst idle, we attempt to power down the hardware and | |
1133 | * display clocks. In order to reduce the effect on performance, there | |
1134 | * is a slight delay before we do so. | |
1135 | */ | |
1136 | bool busy; | |
1137 | ||
4b5aed62 DV |
1138 | /** Bit 6 swizzling required for X tiling */ |
1139 | uint32_t bit_6_swizzle_x; | |
1140 | /** Bit 6 swizzling required for Y tiling */ | |
1141 | uint32_t bit_6_swizzle_y; | |
1142 | ||
1143 | /* storage for physical objects */ | |
1144 | struct drm_i915_gem_phys_object *phys_objs[I915_MAX_PHYS_OBJECT]; | |
1145 | ||
1146 | /* accounting, useful for userland debugging */ | |
c20e8355 | 1147 | spinlock_t object_stat_lock; |
4b5aed62 DV |
1148 | size_t object_memory; |
1149 | u32 object_count; | |
1150 | }; | |
1151 | ||
edc3d884 MK |
1152 | struct drm_i915_error_state_buf { |
1153 | unsigned bytes; | |
1154 | unsigned size; | |
1155 | int err; | |
1156 | u8 *buf; | |
1157 | loff_t start; | |
1158 | loff_t pos; | |
1159 | }; | |
1160 | ||
fc16b48b MK |
1161 | struct i915_error_state_file_priv { |
1162 | struct drm_device *dev; | |
1163 | struct drm_i915_error_state *error; | |
1164 | }; | |
1165 | ||
99584db3 DV |
1166 | struct i915_gpu_error { |
1167 | /* For hangcheck timer */ | |
1168 | #define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */ | |
1169 | #define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD) | |
be62acb4 MK |
1170 | /* Hang gpu twice in this window and your context gets banned */ |
1171 | #define DRM_I915_CTX_BAN_PERIOD DIV_ROUND_UP(8*DRM_I915_HANGCHECK_PERIOD, 1000) | |
1172 | ||
99584db3 | 1173 | struct timer_list hangcheck_timer; |
99584db3 DV |
1174 | |
1175 | /* For reset and error_state handling. */ | |
1176 | spinlock_t lock; | |
1177 | /* Protected by the above dev->gpu_error.lock. */ | |
1178 | struct drm_i915_error_state *first_error; | |
1179 | struct work_struct work; | |
99584db3 | 1180 | |
094f9a54 CW |
1181 | |
1182 | unsigned long missed_irq_rings; | |
1183 | ||
1f83fee0 | 1184 | /** |
2ac0f450 | 1185 | * State variable controlling the reset flow and count |
1f83fee0 | 1186 | * |
2ac0f450 MK |
1187 | * This is a counter which gets incremented when reset is triggered, |
1188 | * and again when reset has been handled. So odd values (lowest bit set) | |
1189 | * means that reset is in progress and even values that | |
1190 | * (reset_counter >> 1):th reset was successfully completed. | |
1191 | * | |
1192 | * If reset is not completed succesfully, the I915_WEDGE bit is | |
1193 | * set meaning that hardware is terminally sour and there is no | |
1194 | * recovery. All waiters on the reset_queue will be woken when | |
1195 | * that happens. | |
1196 | * | |
1197 | * This counter is used by the wait_seqno code to notice that reset | |
1198 | * event happened and it needs to restart the entire ioctl (since most | |
1199 | * likely the seqno it waited for won't ever signal anytime soon). | |
f69061be DV |
1200 | * |
1201 | * This is important for lock-free wait paths, where no contended lock | |
1202 | * naturally enforces the correct ordering between the bail-out of the | |
1203 | * waiter and the gpu reset work code. | |
1f83fee0 DV |
1204 | */ |
1205 | atomic_t reset_counter; | |
1206 | ||
1f83fee0 | 1207 | #define I915_RESET_IN_PROGRESS_FLAG 1 |
2ac0f450 | 1208 | #define I915_WEDGED (1 << 31) |
1f83fee0 DV |
1209 | |
1210 | /** | |
1211 | * Waitqueue to signal when the reset has completed. Used by clients | |
1212 | * that wait for dev_priv->mm.wedged to settle. | |
1213 | */ | |
1214 | wait_queue_head_t reset_queue; | |
33196ded | 1215 | |
99584db3 DV |
1216 | /* For gpu hang simulation. */ |
1217 | unsigned int stop_rings; | |
094f9a54 CW |
1218 | |
1219 | /* For missed irq/seqno simulation. */ | |
1220 | unsigned int test_irq_rings; | |
99584db3 DV |
1221 | }; |
1222 | ||
b8efb17b ZR |
1223 | enum modeset_restore { |
1224 | MODESET_ON_LID_OPEN, | |
1225 | MODESET_DONE, | |
1226 | MODESET_SUSPENDED, | |
1227 | }; | |
1228 | ||
6acab15a PZ |
1229 | struct ddi_vbt_port_info { |
1230 | uint8_t hdmi_level_shift; | |
311a2094 PZ |
1231 | |
1232 | uint8_t supports_dvi:1; | |
1233 | uint8_t supports_hdmi:1; | |
1234 | uint8_t supports_dp:1; | |
6acab15a PZ |
1235 | }; |
1236 | ||
41aa3448 RV |
1237 | struct intel_vbt_data { |
1238 | struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */ | |
1239 | struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */ | |
1240 | ||
1241 | /* Feature bits */ | |
1242 | unsigned int int_tv_support:1; | |
1243 | unsigned int lvds_dither:1; | |
1244 | unsigned int lvds_vbt:1; | |
1245 | unsigned int int_crt_support:1; | |
1246 | unsigned int lvds_use_ssc:1; | |
1247 | unsigned int display_clock_mode:1; | |
1248 | unsigned int fdi_rx_polarity_inverted:1; | |
1249 | int lvds_ssc_freq; | |
1250 | unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */ | |
1251 | ||
1252 | /* eDP */ | |
1253 | int edp_rate; | |
1254 | int edp_lanes; | |
1255 | int edp_preemphasis; | |
1256 | int edp_vswing; | |
1257 | bool edp_initialized; | |
1258 | bool edp_support; | |
1259 | int edp_bpp; | |
1260 | struct edp_power_seq edp_pps; | |
1261 | ||
f00076d2 JN |
1262 | struct { |
1263 | u16 pwm_freq_hz; | |
1264 | bool active_low_pwm; | |
1265 | } backlight; | |
1266 | ||
d17c5443 SK |
1267 | /* MIPI DSI */ |
1268 | struct { | |
1269 | u16 panel_id; | |
1270 | } dsi; | |
1271 | ||
41aa3448 RV |
1272 | int crt_ddc_pin; |
1273 | ||
1274 | int child_dev_num; | |
768f69c9 | 1275 | union child_device_config *child_dev; |
6acab15a PZ |
1276 | |
1277 | struct ddi_vbt_port_info ddi_port_info[I915_MAX_PORTS]; | |
41aa3448 RV |
1278 | }; |
1279 | ||
77c122bc VS |
1280 | enum intel_ddb_partitioning { |
1281 | INTEL_DDB_PART_1_2, | |
1282 | INTEL_DDB_PART_5_6, /* IVB+ */ | |
1283 | }; | |
1284 | ||
1fd527cc VS |
1285 | struct intel_wm_level { |
1286 | bool enable; | |
1287 | uint32_t pri_val; | |
1288 | uint32_t spr_val; | |
1289 | uint32_t cur_val; | |
1290 | uint32_t fbc_val; | |
1291 | }; | |
1292 | ||
820c1980 | 1293 | struct ilk_wm_values { |
609cedef VS |
1294 | uint32_t wm_pipe[3]; |
1295 | uint32_t wm_lp[3]; | |
1296 | uint32_t wm_lp_spr[3]; | |
1297 | uint32_t wm_linetime[3]; | |
1298 | bool enable_fbc_wm; | |
1299 | enum intel_ddb_partitioning partitioning; | |
1300 | }; | |
1301 | ||
c67a470b PZ |
1302 | /* |
1303 | * This struct tracks the state needed for the Package C8+ feature. | |
1304 | * | |
1305 | * Package states C8 and deeper are really deep PC states that can only be | |
1306 | * reached when all the devices on the system allow it, so even if the graphics | |
1307 | * device allows PC8+, it doesn't mean the system will actually get to these | |
1308 | * states. | |
1309 | * | |
1310 | * Our driver only allows PC8+ when all the outputs are disabled, the power well | |
1311 | * is disabled and the GPU is idle. When these conditions are met, we manually | |
1312 | * do the other conditions: disable the interrupts, clocks and switch LCPLL | |
1313 | * refclk to Fclk. | |
1314 | * | |
1315 | * When we really reach PC8 or deeper states (not just when we allow it) we lose | |
1316 | * the state of some registers, so when we come back from PC8+ we need to | |
1317 | * restore this state. We don't get into PC8+ if we're not in RC6, so we don't | |
1318 | * need to take care of the registers kept by RC6. | |
1319 | * | |
1320 | * The interrupt disabling is part of the requirements. We can only leave the | |
1321 | * PCH HPD interrupts enabled. If we're in PC8+ and we get another interrupt we | |
1322 | * can lock the machine. | |
1323 | * | |
1324 | * Ideally every piece of our code that needs PC8+ disabled would call | |
1325 | * hsw_disable_package_c8, which would increment disable_count and prevent the | |
1326 | * system from reaching PC8+. But we don't have a symmetric way to do this for | |
86c4ec0d PZ |
1327 | * everything, so we have the requirements_met variable. When we switch |
1328 | * requirements_met to true we decrease disable_count, and increase it in the | |
1329 | * opposite case. The requirements_met variable is true when all the CRTCs, | |
1330 | * encoders and the power well are disabled. | |
c67a470b PZ |
1331 | * |
1332 | * In addition to everything, we only actually enable PC8+ if disable_count | |
1333 | * stays at zero for at least some seconds. This is implemented with the | |
1334 | * enable_work variable. We do this so we don't enable/disable PC8 dozens of | |
1335 | * consecutive times when all screens are disabled and some background app | |
1336 | * queries the state of our connectors, or we have some application constantly | |
1337 | * waking up to use the GPU. Only after the enable_work function actually | |
1338 | * enables PC8+ the "enable" variable will become true, which means that it can | |
1339 | * be false even if disable_count is 0. | |
1340 | * | |
1341 | * The irqs_disabled variable becomes true exactly after we disable the IRQs and | |
1342 | * goes back to false exactly before we reenable the IRQs. We use this variable | |
1343 | * to check if someone is trying to enable/disable IRQs while they're supposed | |
1344 | * to be disabled. This shouldn't happen and we'll print some error messages in | |
1345 | * case it happens, but if it actually happens we'll also update the variables | |
1346 | * inside struct regsave so when we restore the IRQs they will contain the | |
1347 | * latest expected values. | |
1348 | * | |
1349 | * For more, read "Display Sequences for Package C8" on our documentation. | |
1350 | */ | |
1351 | struct i915_package_c8 { | |
1352 | bool requirements_met; | |
c67a470b PZ |
1353 | bool irqs_disabled; |
1354 | /* Only true after the delayed work task actually enables it. */ | |
1355 | bool enabled; | |
1356 | int disable_count; | |
1357 | struct mutex lock; | |
1358 | struct delayed_work enable_work; | |
1359 | ||
1360 | struct { | |
1361 | uint32_t deimr; | |
1362 | uint32_t sdeimr; | |
1363 | uint32_t gtimr; | |
1364 | uint32_t gtier; | |
1365 | uint32_t gen6_pmimr; | |
1366 | } regsave; | |
1367 | }; | |
1368 | ||
8a187455 PZ |
1369 | struct i915_runtime_pm { |
1370 | bool suspended; | |
1371 | }; | |
1372 | ||
926321d5 DV |
1373 | enum intel_pipe_crc_source { |
1374 | INTEL_PIPE_CRC_SOURCE_NONE, | |
1375 | INTEL_PIPE_CRC_SOURCE_PLANE1, | |
1376 | INTEL_PIPE_CRC_SOURCE_PLANE2, | |
1377 | INTEL_PIPE_CRC_SOURCE_PF, | |
5b3a856b | 1378 | INTEL_PIPE_CRC_SOURCE_PIPE, |
3d099a05 DV |
1379 | /* TV/DP on pre-gen5/vlv can't use the pipe source. */ |
1380 | INTEL_PIPE_CRC_SOURCE_TV, | |
1381 | INTEL_PIPE_CRC_SOURCE_DP_B, | |
1382 | INTEL_PIPE_CRC_SOURCE_DP_C, | |
1383 | INTEL_PIPE_CRC_SOURCE_DP_D, | |
46a19188 | 1384 | INTEL_PIPE_CRC_SOURCE_AUTO, |
926321d5 DV |
1385 | INTEL_PIPE_CRC_SOURCE_MAX, |
1386 | }; | |
1387 | ||
8bf1e9f1 | 1388 | struct intel_pipe_crc_entry { |
ac2300d4 | 1389 | uint32_t frame; |
8bf1e9f1 SH |
1390 | uint32_t crc[5]; |
1391 | }; | |
1392 | ||
b2c88f5b | 1393 | #define INTEL_PIPE_CRC_ENTRIES_NR 128 |
8bf1e9f1 | 1394 | struct intel_pipe_crc { |
d538bbdf DL |
1395 | spinlock_t lock; |
1396 | bool opened; /* exclusive access to the result file */ | |
e5f75aca | 1397 | struct intel_pipe_crc_entry *entries; |
926321d5 | 1398 | enum intel_pipe_crc_source source; |
d538bbdf | 1399 | int head, tail; |
07144428 | 1400 | wait_queue_head_t wq; |
8bf1e9f1 SH |
1401 | }; |
1402 | ||
f4c956ad DV |
1403 | typedef struct drm_i915_private { |
1404 | struct drm_device *dev; | |
42dcedd4 | 1405 | struct kmem_cache *slab; |
f4c956ad | 1406 | |
5c969aa7 | 1407 | const struct intel_device_info info; |
f4c956ad DV |
1408 | |
1409 | int relative_constants_mode; | |
1410 | ||
1411 | void __iomem *regs; | |
1412 | ||
907b28c5 | 1413 | struct intel_uncore uncore; |
f4c956ad DV |
1414 | |
1415 | struct intel_gmbus gmbus[GMBUS_NUM_PORTS]; | |
1416 | ||
28c70f16 | 1417 | |
f4c956ad DV |
1418 | /** gmbus_mutex protects against concurrent usage of the single hw gmbus |
1419 | * controller on different i2c buses. */ | |
1420 | struct mutex gmbus_mutex; | |
1421 | ||
1422 | /** | |
1423 | * Base address of the gmbus and gpio block. | |
1424 | */ | |
1425 | uint32_t gpio_mmio_base; | |
1426 | ||
28c70f16 DV |
1427 | wait_queue_head_t gmbus_wait_queue; |
1428 | ||
f4c956ad DV |
1429 | struct pci_dev *bridge_dev; |
1430 | struct intel_ring_buffer ring[I915_NUM_RINGS]; | |
f72b3435 | 1431 | uint32_t last_seqno, next_seqno; |
f4c956ad DV |
1432 | |
1433 | drm_dma_handle_t *status_page_dmah; | |
f4c956ad DV |
1434 | struct resource mch_res; |
1435 | ||
f4c956ad DV |
1436 | /* protects the irq masks */ |
1437 | spinlock_t irq_lock; | |
1438 | ||
9ee32fea DV |
1439 | /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */ |
1440 | struct pm_qos_request pm_qos; | |
1441 | ||
f4c956ad | 1442 | /* DPIO indirect register protection */ |
09153000 | 1443 | struct mutex dpio_lock; |
f4c956ad DV |
1444 | |
1445 | /** Cached value of IMR to avoid reads in updating the bitfield */ | |
abd58f01 BW |
1446 | union { |
1447 | u32 irq_mask; | |
1448 | u32 de_irq_mask[I915_MAX_PIPES]; | |
1449 | }; | |
f4c956ad | 1450 | u32 gt_irq_mask; |
605cd25b | 1451 | u32 pm_irq_mask; |
91d181dd | 1452 | u32 pipestat_irq_mask[I915_MAX_PIPES]; |
f4c956ad | 1453 | |
f4c956ad | 1454 | struct work_struct hotplug_work; |
52d7eced | 1455 | bool enable_hotplug_processing; |
b543fb04 EE |
1456 | struct { |
1457 | unsigned long hpd_last_jiffies; | |
1458 | int hpd_cnt; | |
1459 | enum { | |
1460 | HPD_ENABLED = 0, | |
1461 | HPD_DISABLED = 1, | |
1462 | HPD_MARK_DISABLED = 2 | |
1463 | } hpd_mark; | |
1464 | } hpd_stats[HPD_NUM_PINS]; | |
142e2398 | 1465 | u32 hpd_event_bits; |
ac4c16c5 | 1466 | struct timer_list hotplug_reenable_timer; |
f4c956ad | 1467 | |
5c3fe8b0 | 1468 | struct i915_fbc fbc; |
f4c956ad | 1469 | struct intel_opregion opregion; |
41aa3448 | 1470 | struct intel_vbt_data vbt; |
f4c956ad DV |
1471 | |
1472 | /* overlay */ | |
1473 | struct intel_overlay *overlay; | |
f4c956ad | 1474 | |
58c68779 JN |
1475 | /* backlight registers and fields in struct intel_panel */ |
1476 | spinlock_t backlight_lock; | |
31ad8ec6 | 1477 | |
f4c956ad | 1478 | /* LVDS info */ |
f4c956ad DV |
1479 | bool no_aux_handshake; |
1480 | ||
f4c956ad DV |
1481 | struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; /* assume 965 */ |
1482 | int fence_reg_start; /* 4 if userland hasn't ioctl'd us yet */ | |
1483 | int num_fence_regs; /* 8 on pre-965, 16 otherwise */ | |
1484 | ||
1485 | unsigned int fsb_freq, mem_freq, is_ddr3; | |
1486 | ||
645416f5 DV |
1487 | /** |
1488 | * wq - Driver workqueue for GEM. | |
1489 | * | |
1490 | * NOTE: Work items scheduled here are not allowed to grab any modeset | |
1491 | * locks, for otherwise the flushing done in the pageflip code will | |
1492 | * result in deadlocks. | |
1493 | */ | |
f4c956ad DV |
1494 | struct workqueue_struct *wq; |
1495 | ||
1496 | /* Display functions */ | |
1497 | struct drm_i915_display_funcs display; | |
1498 | ||
1499 | /* PCH chipset type */ | |
1500 | enum intel_pch pch_type; | |
17a303ec | 1501 | unsigned short pch_id; |
f4c956ad DV |
1502 | |
1503 | unsigned long quirks; | |
1504 | ||
b8efb17b ZR |
1505 | enum modeset_restore modeset_restore; |
1506 | struct mutex modeset_restore_lock; | |
673a394b | 1507 | |
a7bbbd63 | 1508 | struct list_head vm_list; /* Global list of all address spaces */ |
853ba5d2 | 1509 | struct i915_gtt gtt; /* VMA representing the global address space */ |
5d4545ae | 1510 | |
4b5aed62 | 1511 | struct i915_gem_mm mm; |
8781342d | 1512 | |
8781342d DV |
1513 | /* Kernel Modesetting */ |
1514 | ||
9b9d172d | 1515 | struct sdvo_device_mapping sdvo_mappings[2]; |
652c393a | 1516 | |
76c4ac04 DL |
1517 | struct drm_crtc *plane_to_crtc_mapping[I915_MAX_PIPES]; |
1518 | struct drm_crtc *pipe_to_crtc_mapping[I915_MAX_PIPES]; | |
6b95a207 KH |
1519 | wait_queue_head_t pending_flip_queue; |
1520 | ||
c4597872 DV |
1521 | #ifdef CONFIG_DEBUG_FS |
1522 | struct intel_pipe_crc pipe_crc[I915_MAX_PIPES]; | |
1523 | #endif | |
1524 | ||
e72f9fbf DV |
1525 | int num_shared_dpll; |
1526 | struct intel_shared_dpll shared_dplls[I915_NUM_PLLS]; | |
6441ab5f | 1527 | struct intel_ddi_plls ddi_plls; |
e4607fcf | 1528 | int dpio_phy_iosf_port[I915_NUM_PHYS_VLV]; |
ee7b9f93 | 1529 | |
652c393a JB |
1530 | /* Reclocking support */ |
1531 | bool render_reclock_avail; | |
1532 | bool lvds_downclock_avail; | |
18f9ed12 ZY |
1533 | /* indicates the reduced downclock for LVDS*/ |
1534 | int lvds_downclock; | |
652c393a | 1535 | u16 orig_clock; |
f97108d1 | 1536 | |
c4804411 | 1537 | bool mchbar_need_disable; |
f97108d1 | 1538 | |
a4da4fa4 DV |
1539 | struct intel_l3_parity l3_parity; |
1540 | ||
59124506 BW |
1541 | /* Cannot be determined by PCIID. You must always read a register. */ |
1542 | size_t ellc_size; | |
1543 | ||
c6a828d3 | 1544 | /* gen6+ rps state */ |
c85aa885 | 1545 | struct intel_gen6_power_mgmt rps; |
c6a828d3 | 1546 | |
20e4d407 DV |
1547 | /* ilk-only ips/rps state. Everything in here is protected by the global |
1548 | * mchdev_lock in intel_pm.c */ | |
c85aa885 | 1549 | struct intel_ilk_power_mgmt ips; |
b5e50c3f | 1550 | |
83c00f55 | 1551 | struct i915_power_domains power_domains; |
a38911a3 | 1552 | |
a031d709 | 1553 | struct i915_psr psr; |
3f51e471 | 1554 | |
99584db3 | 1555 | struct i915_gpu_error gpu_error; |
ae681d96 | 1556 | |
c9cddffc JB |
1557 | struct drm_i915_gem_object *vlv_pctx; |
1558 | ||
4520f53a | 1559 | #ifdef CONFIG_DRM_I915_FBDEV |
8be48d92 DA |
1560 | /* list of fbdev register on this device */ |
1561 | struct intel_fbdev *fbdev; | |
4520f53a | 1562 | #endif |
e953fd7b | 1563 | |
073f34d9 JB |
1564 | /* |
1565 | * The console may be contended at resume, but we don't | |
1566 | * want it to block on it. | |
1567 | */ | |
1568 | struct work_struct console_resume_work; | |
1569 | ||
e953fd7b | 1570 | struct drm_property *broadcast_rgb_property; |
3f43c48d | 1571 | struct drm_property *force_audio_property; |
e3689190 | 1572 | |
254f965c | 1573 | uint32_t hw_context_size; |
a33afea5 | 1574 | struct list_head context_list; |
f4c956ad | 1575 | |
3e68320e | 1576 | u32 fdi_rx_config; |
68d18ad7 | 1577 | |
f4c956ad | 1578 | struct i915_suspend_saved_registers regfile; |
231f42a4 | 1579 | |
53615a5e VS |
1580 | struct { |
1581 | /* | |
1582 | * Raw watermark latency values: | |
1583 | * in 0.1us units for WM0, | |
1584 | * in 0.5us units for WM1+. | |
1585 | */ | |
1586 | /* primary */ | |
1587 | uint16_t pri_latency[5]; | |
1588 | /* sprite */ | |
1589 | uint16_t spr_latency[5]; | |
1590 | /* cursor */ | |
1591 | uint16_t cur_latency[5]; | |
609cedef VS |
1592 | |
1593 | /* current hardware state */ | |
820c1980 | 1594 | struct ilk_wm_values hw; |
53615a5e VS |
1595 | } wm; |
1596 | ||
c67a470b PZ |
1597 | struct i915_package_c8 pc8; |
1598 | ||
8a187455 PZ |
1599 | struct i915_runtime_pm pm; |
1600 | ||
231f42a4 DV |
1601 | /* Old dri1 support infrastructure, beware the dragons ya fools entering |
1602 | * here! */ | |
1603 | struct i915_dri1_state dri1; | |
db1b76ca DV |
1604 | /* Old ums support infrastructure, same warning applies. */ |
1605 | struct i915_ums_state ums; | |
1da177e4 LT |
1606 | } drm_i915_private_t; |
1607 | ||
2c1792a1 CW |
1608 | static inline struct drm_i915_private *to_i915(const struct drm_device *dev) |
1609 | { | |
1610 | return dev->dev_private; | |
1611 | } | |
1612 | ||
b4519513 CW |
1613 | /* Iterate over initialised rings */ |
1614 | #define for_each_ring(ring__, dev_priv__, i__) \ | |
1615 | for ((i__) = 0; (i__) < I915_NUM_RINGS; (i__)++) \ | |
1616 | if (((ring__) = &(dev_priv__)->ring[(i__)]), intel_ring_initialized((ring__))) | |
1617 | ||
b1d7e4b4 WF |
1618 | enum hdmi_force_audio { |
1619 | HDMI_AUDIO_OFF_DVI = -2, /* no aux data for HDMI-DVI converter */ | |
1620 | HDMI_AUDIO_OFF, /* force turn off HDMI audio */ | |
1621 | HDMI_AUDIO_AUTO, /* trust EDID */ | |
1622 | HDMI_AUDIO_ON, /* force turn on HDMI audio */ | |
1623 | }; | |
1624 | ||
190d6cd5 | 1625 | #define I915_GTT_OFFSET_NONE ((u32)-1) |
ed2f3452 | 1626 | |
37e680a1 CW |
1627 | struct drm_i915_gem_object_ops { |
1628 | /* Interface between the GEM object and its backing storage. | |
1629 | * get_pages() is called once prior to the use of the associated set | |
1630 | * of pages before to binding them into the GTT, and put_pages() is | |
1631 | * called after we no longer need them. As we expect there to be | |
1632 | * associated cost with migrating pages between the backing storage | |
1633 | * and making them available for the GPU (e.g. clflush), we may hold | |
1634 | * onto the pages after they are no longer referenced by the GPU | |
1635 | * in case they may be used again shortly (for example migrating the | |
1636 | * pages to a different memory domain within the GTT). put_pages() | |
1637 | * will therefore most likely be called when the object itself is | |
1638 | * being released or under memory pressure (where we attempt to | |
1639 | * reap pages for the shrinker). | |
1640 | */ | |
1641 | int (*get_pages)(struct drm_i915_gem_object *); | |
1642 | void (*put_pages)(struct drm_i915_gem_object *); | |
1643 | }; | |
1644 | ||
673a394b | 1645 | struct drm_i915_gem_object { |
c397b908 | 1646 | struct drm_gem_object base; |
673a394b | 1647 | |
37e680a1 CW |
1648 | const struct drm_i915_gem_object_ops *ops; |
1649 | ||
2f633156 BW |
1650 | /** List of VMAs backed by this object */ |
1651 | struct list_head vma_list; | |
1652 | ||
c1ad11fc CW |
1653 | /** Stolen memory for this object, instead of being backed by shmem. */ |
1654 | struct drm_mm_node *stolen; | |
35c20a60 | 1655 | struct list_head global_list; |
673a394b | 1656 | |
69dc4987 | 1657 | struct list_head ring_list; |
b25cb2f8 BW |
1658 | /** Used in execbuf to temporarily hold a ref */ |
1659 | struct list_head obj_exec_link; | |
673a394b EA |
1660 | |
1661 | /** | |
65ce3027 CW |
1662 | * This is set if the object is on the active lists (has pending |
1663 | * rendering and so a non-zero seqno), and is not set if it i s on | |
1664 | * inactive (ready to be unbound) list. | |
673a394b | 1665 | */ |
0206e353 | 1666 | unsigned int active:1; |
673a394b EA |
1667 | |
1668 | /** | |
1669 | * This is set if the object has been written to since last bound | |
1670 | * to the GTT | |
1671 | */ | |
0206e353 | 1672 | unsigned int dirty:1; |
778c3544 DV |
1673 | |
1674 | /** | |
1675 | * Fence register bits (if any) for this object. Will be set | |
1676 | * as needed when mapped into the GTT. | |
1677 | * Protected by dev->struct_mutex. | |
778c3544 | 1678 | */ |
4b9de737 | 1679 | signed int fence_reg:I915_MAX_NUM_FENCE_BITS; |
778c3544 | 1680 | |
778c3544 DV |
1681 | /** |
1682 | * Advice: are the backing pages purgeable? | |
1683 | */ | |
0206e353 | 1684 | unsigned int madv:2; |
778c3544 | 1685 | |
778c3544 DV |
1686 | /** |
1687 | * Current tiling mode for the object. | |
1688 | */ | |
0206e353 | 1689 | unsigned int tiling_mode:2; |
5d82e3e6 CW |
1690 | /** |
1691 | * Whether the tiling parameters for the currently associated fence | |
1692 | * register have changed. Note that for the purposes of tracking | |
1693 | * tiling changes we also treat the unfenced register, the register | |
1694 | * slot that the object occupies whilst it executes a fenced | |
1695 | * command (such as BLT on gen2/3), as a "fence". | |
1696 | */ | |
1697 | unsigned int fence_dirty:1; | |
778c3544 | 1698 | |
75e9e915 DV |
1699 | /** |
1700 | * Is the object at the current location in the gtt mappable and | |
1701 | * fenceable? Used to avoid costly recalculations. | |
1702 | */ | |
0206e353 | 1703 | unsigned int map_and_fenceable:1; |
75e9e915 | 1704 | |
fb7d516a DV |
1705 | /** |
1706 | * Whether the current gtt mapping needs to be mappable (and isn't just | |
1707 | * mappable by accident). Track pin and fault separate for a more | |
1708 | * accurate mappable working set. | |
1709 | */ | |
0206e353 AJ |
1710 | unsigned int fault_mappable:1; |
1711 | unsigned int pin_mappable:1; | |
cc98b413 | 1712 | unsigned int pin_display:1; |
fb7d516a | 1713 | |
caea7476 CW |
1714 | /* |
1715 | * Is the GPU currently using a fence to access this buffer, | |
1716 | */ | |
1717 | unsigned int pending_fenced_gpu_access:1; | |
1718 | unsigned int fenced_gpu_access:1; | |
1719 | ||
651d794f | 1720 | unsigned int cache_level:3; |
93dfb40c | 1721 | |
7bddb01f | 1722 | unsigned int has_aliasing_ppgtt_mapping:1; |
74898d7e | 1723 | unsigned int has_global_gtt_mapping:1; |
9da3da66 | 1724 | unsigned int has_dma_mapping:1; |
7bddb01f | 1725 | |
9da3da66 | 1726 | struct sg_table *pages; |
a5570178 | 1727 | int pages_pin_count; |
673a394b | 1728 | |
1286ff73 | 1729 | /* prime dma-buf support */ |
9a70cc2a DA |
1730 | void *dma_buf_vmapping; |
1731 | int vmapping_count; | |
1732 | ||
caea7476 CW |
1733 | struct intel_ring_buffer *ring; |
1734 | ||
1c293ea3 | 1735 | /** Breadcrumb of last rendering to the buffer. */ |
0201f1ec CW |
1736 | uint32_t last_read_seqno; |
1737 | uint32_t last_write_seqno; | |
caea7476 CW |
1738 | /** Breadcrumb of last fenced GPU access to the buffer. */ |
1739 | uint32_t last_fenced_seqno; | |
673a394b | 1740 | |
778c3544 | 1741 | /** Current tiling stride for the object, if it's tiled. */ |
de151cf6 | 1742 | uint32_t stride; |
673a394b | 1743 | |
80075d49 DV |
1744 | /** References from framebuffers, locks out tiling changes. */ |
1745 | unsigned long framebuffer_references; | |
1746 | ||
280b713b | 1747 | /** Record of address bit 17 of each page at last unbind. */ |
d312ec25 | 1748 | unsigned long *bit_17; |
280b713b | 1749 | |
79e53945 | 1750 | /** User space pin count and filp owning the pin */ |
aa5f8021 | 1751 | unsigned long user_pin_count; |
79e53945 | 1752 | struct drm_file *pin_filp; |
71acb5eb DA |
1753 | |
1754 | /** for phy allocated objects */ | |
1755 | struct drm_i915_gem_phys_object *phys_obj; | |
673a394b | 1756 | }; |
b45305fc | 1757 | #define to_gem_object(obj) (&((struct drm_i915_gem_object *)(obj))->base) |
673a394b | 1758 | |
62b8b215 | 1759 | #define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base) |
23010e43 | 1760 | |
673a394b EA |
1761 | /** |
1762 | * Request queue structure. | |
1763 | * | |
1764 | * The request queue allows us to note sequence numbers that have been emitted | |
1765 | * and may be associated with active buffers to be retired. | |
1766 | * | |
1767 | * By keeping this list, we can avoid having to do questionable | |
1768 | * sequence-number comparisons on buffer last_rendering_seqnos, and associate | |
1769 | * an emission time with seqnos for tracking how far ahead of the GPU we are. | |
1770 | */ | |
1771 | struct drm_i915_gem_request { | |
852835f3 ZN |
1772 | /** On Which ring this request was generated */ |
1773 | struct intel_ring_buffer *ring; | |
1774 | ||
673a394b EA |
1775 | /** GEM sequence number associated with this request. */ |
1776 | uint32_t seqno; | |
1777 | ||
7d736f4f MK |
1778 | /** Position in the ringbuffer of the start of the request */ |
1779 | u32 head; | |
1780 | ||
1781 | /** Position in the ringbuffer of the end of the request */ | |
a71d8d94 CW |
1782 | u32 tail; |
1783 | ||
0e50e96b MK |
1784 | /** Context related to this request */ |
1785 | struct i915_hw_context *ctx; | |
1786 | ||
7d736f4f MK |
1787 | /** Batch buffer related to this request if any */ |
1788 | struct drm_i915_gem_object *batch_obj; | |
1789 | ||
673a394b EA |
1790 | /** Time at which this request was emitted, in jiffies. */ |
1791 | unsigned long emitted_jiffies; | |
1792 | ||
b962442e | 1793 | /** global list entry for this request */ |
673a394b | 1794 | struct list_head list; |
b962442e | 1795 | |
f787a5f5 | 1796 | struct drm_i915_file_private *file_priv; |
b962442e EA |
1797 | /** file_priv list entry for this request */ |
1798 | struct list_head client_list; | |
673a394b EA |
1799 | }; |
1800 | ||
1801 | struct drm_i915_file_private { | |
b29c19b6 | 1802 | struct drm_i915_private *dev_priv; |
ab0e7ff9 | 1803 | struct drm_file *file; |
b29c19b6 | 1804 | |
673a394b | 1805 | struct { |
99057c81 | 1806 | spinlock_t lock; |
b962442e | 1807 | struct list_head request_list; |
b29c19b6 | 1808 | struct delayed_work idle_work; |
673a394b | 1809 | } mm; |
40521054 | 1810 | struct idr context_idr; |
e59ec13d | 1811 | |
0eea67eb | 1812 | struct i915_hw_context *private_default_ctx; |
b29c19b6 | 1813 | atomic_t rps_wait_boost; |
673a394b EA |
1814 | }; |
1815 | ||
5c969aa7 | 1816 | #define INTEL_INFO(dev) (&to_i915(dev)->info) |
cae5852d | 1817 | |
ffbab09b VS |
1818 | #define IS_I830(dev) ((dev)->pdev->device == 0x3577) |
1819 | #define IS_845G(dev) ((dev)->pdev->device == 0x2562) | |
cae5852d | 1820 | #define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x) |
ffbab09b | 1821 | #define IS_I865G(dev) ((dev)->pdev->device == 0x2572) |
cae5852d | 1822 | #define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g) |
ffbab09b VS |
1823 | #define IS_I915GM(dev) ((dev)->pdev->device == 0x2592) |
1824 | #define IS_I945G(dev) ((dev)->pdev->device == 0x2772) | |
cae5852d ZN |
1825 | #define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm) |
1826 | #define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater) | |
1827 | #define IS_CRESTLINE(dev) (INTEL_INFO(dev)->is_crestline) | |
ffbab09b | 1828 | #define IS_GM45(dev) ((dev)->pdev->device == 0x2A42) |
cae5852d | 1829 | #define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x) |
ffbab09b VS |
1830 | #define IS_PINEVIEW_G(dev) ((dev)->pdev->device == 0xa001) |
1831 | #define IS_PINEVIEW_M(dev) ((dev)->pdev->device == 0xa011) | |
cae5852d ZN |
1832 | #define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview) |
1833 | #define IS_G33(dev) (INTEL_INFO(dev)->is_g33) | |
ffbab09b | 1834 | #define IS_IRONLAKE_M(dev) ((dev)->pdev->device == 0x0046) |
4b65177b | 1835 | #define IS_IVYBRIDGE(dev) (INTEL_INFO(dev)->is_ivybridge) |
ffbab09b VS |
1836 | #define IS_IVB_GT1(dev) ((dev)->pdev->device == 0x0156 || \ |
1837 | (dev)->pdev->device == 0x0152 || \ | |
1838 | (dev)->pdev->device == 0x015a) | |
1839 | #define IS_SNB_GT1(dev) ((dev)->pdev->device == 0x0102 || \ | |
1840 | (dev)->pdev->device == 0x0106 || \ | |
1841 | (dev)->pdev->device == 0x010A) | |
70a3eb7a | 1842 | #define IS_VALLEYVIEW(dev) (INTEL_INFO(dev)->is_valleyview) |
4cae9ae0 | 1843 | #define IS_HASWELL(dev) (INTEL_INFO(dev)->is_haswell) |
4e8058a2 | 1844 | #define IS_BROADWELL(dev) (INTEL_INFO(dev)->gen == 8) |
cae5852d | 1845 | #define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile) |
ed1c9e2c | 1846 | #define IS_HSW_EARLY_SDV(dev) (IS_HASWELL(dev) && \ |
ffbab09b | 1847 | ((dev)->pdev->device & 0xFF00) == 0x0C00) |
5dd8c4c3 BW |
1848 | #define IS_BDW_ULT(dev) (IS_BROADWELL(dev) && \ |
1849 | (((dev)->pdev->device & 0xf) == 0x2 || \ | |
1850 | ((dev)->pdev->device & 0xf) == 0x6 || \ | |
1851 | ((dev)->pdev->device & 0xf) == 0xe)) | |
1852 | #define IS_HSW_ULT(dev) (IS_HASWELL(dev) && \ | |
ffbab09b | 1853 | ((dev)->pdev->device & 0xFF00) == 0x0A00) |
5dd8c4c3 | 1854 | #define IS_ULT(dev) (IS_HSW_ULT(dev) || IS_BDW_ULT(dev)) |
9435373e | 1855 | #define IS_HSW_GT3(dev) (IS_HASWELL(dev) && \ |
ffbab09b | 1856 | ((dev)->pdev->device & 0x00F0) == 0x0020) |
b833d685 | 1857 | #define IS_PRELIMINARY_HW(intel_info) ((intel_info)->is_preliminary) |
cae5852d | 1858 | |
85436696 JB |
1859 | /* |
1860 | * The genX designation typically refers to the render engine, so render | |
1861 | * capability related checks should use IS_GEN, while display and other checks | |
1862 | * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular | |
1863 | * chips, etc.). | |
1864 | */ | |
cae5852d ZN |
1865 | #define IS_GEN2(dev) (INTEL_INFO(dev)->gen == 2) |
1866 | #define IS_GEN3(dev) (INTEL_INFO(dev)->gen == 3) | |
1867 | #define IS_GEN4(dev) (INTEL_INFO(dev)->gen == 4) | |
1868 | #define IS_GEN5(dev) (INTEL_INFO(dev)->gen == 5) | |
1869 | #define IS_GEN6(dev) (INTEL_INFO(dev)->gen == 6) | |
85436696 | 1870 | #define IS_GEN7(dev) (INTEL_INFO(dev)->gen == 7) |
d2980845 | 1871 | #define IS_GEN8(dev) (INTEL_INFO(dev)->gen == 8) |
cae5852d | 1872 | |
73ae478c BW |
1873 | #define RENDER_RING (1<<RCS) |
1874 | #define BSD_RING (1<<VCS) | |
1875 | #define BLT_RING (1<<BCS) | |
1876 | #define VEBOX_RING (1<<VECS) | |
1877 | #define HAS_BSD(dev) (INTEL_INFO(dev)->ring_mask & BSD_RING) | |
1878 | #define HAS_BLT(dev) (INTEL_INFO(dev)->ring_mask & BLT_RING) | |
1879 | #define HAS_VEBOX(dev) (INTEL_INFO(dev)->ring_mask & VEBOX_RING) | |
3d29b842 | 1880 | #define HAS_LLC(dev) (INTEL_INFO(dev)->has_llc) |
651d794f | 1881 | #define HAS_WT(dev) (IS_HASWELL(dev) && to_i915(dev)->ellc_size) |
cae5852d ZN |
1882 | #define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws) |
1883 | ||
254f965c | 1884 | #define HAS_HW_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 6) |
246cbfb5 | 1885 | #define HAS_ALIASING_PPGTT(dev) (INTEL_INFO(dev)->gen >= 6 && !IS_VALLEYVIEW(dev)) |
c5dc5cec BW |
1886 | #define HAS_PPGTT(dev) (INTEL_INFO(dev)->gen >= 7 && !IS_VALLEYVIEW(dev) \ |
1887 | && !IS_BROADWELL(dev)) | |
1888 | #define USES_PPGTT(dev) intel_enable_ppgtt(dev, false) | |
7e0d96bc | 1889 | #define USES_FULL_PPGTT(dev) intel_enable_ppgtt(dev, true) |
1d2a314c | 1890 | |
05394f39 | 1891 | #define HAS_OVERLAY(dev) (INTEL_INFO(dev)->has_overlay) |
cae5852d ZN |
1892 | #define OVERLAY_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->overlay_needs_physical) |
1893 | ||
b45305fc DV |
1894 | /* Early gen2 have a totally busted CS tlb and require pinned batches. */ |
1895 | #define HAS_BROKEN_CS_TLB(dev) (IS_I830(dev) || IS_845G(dev)) | |
1896 | ||
cae5852d ZN |
1897 | /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte |
1898 | * rows, which changed the alignment requirements and fence programming. | |
1899 | */ | |
1900 | #define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \ | |
1901 | IS_I915GM(dev))) | |
1902 | #define SUPPORTS_DIGITAL_OUTPUTS(dev) (!IS_GEN2(dev) && !IS_PINEVIEW(dev)) | |
1903 | #define SUPPORTS_INTEGRATED_HDMI(dev) (IS_G4X(dev) || IS_GEN5(dev)) | |
1904 | #define SUPPORTS_INTEGRATED_DP(dev) (IS_G4X(dev) || IS_GEN5(dev)) | |
cae5852d ZN |
1905 | #define SUPPORTS_TV(dev) (INTEL_INFO(dev)->supports_tv) |
1906 | #define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug) | |
cae5852d ZN |
1907 | |
1908 | #define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2) | |
1909 | #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr) | |
3a77c4c4 | 1910 | #define HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc) |
cae5852d | 1911 | |
2a114cc1 | 1912 | #define HAS_IPS(dev) (IS_ULT(dev) || IS_BROADWELL(dev)) |
f5adf94e | 1913 | |
dd93be58 | 1914 | #define HAS_DDI(dev) (INTEL_INFO(dev)->has_ddi) |
30568c45 | 1915 | #define HAS_FPGA_DBG_UNCLAIMED(dev) (INTEL_INFO(dev)->has_fpga_dbg) |
ed8546ac | 1916 | #define HAS_PSR(dev) (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
7c6c2652 | 1917 | #define HAS_PC8(dev) (IS_HASWELL(dev)) /* XXX HSW:ULX */ |
df4547d8 | 1918 | #define HAS_RUNTIME_PM(dev) (IS_HASWELL(dev)) |
affa9354 | 1919 | |
17a303ec PZ |
1920 | #define INTEL_PCH_DEVICE_ID_MASK 0xff00 |
1921 | #define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00 | |
1922 | #define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00 | |
1923 | #define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00 | |
1924 | #define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00 | |
1925 | #define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE 0x9c00 | |
1926 | ||
2c1792a1 | 1927 | #define INTEL_PCH_TYPE(dev) (to_i915(dev)->pch_type) |
eb877ebf | 1928 | #define HAS_PCH_LPT(dev) (INTEL_PCH_TYPE(dev) == PCH_LPT) |
cae5852d ZN |
1929 | #define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT) |
1930 | #define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX) | |
40c7ead9 | 1931 | #define HAS_PCH_NOP(dev) (INTEL_PCH_TYPE(dev) == PCH_NOP) |
45e6e3a1 | 1932 | #define HAS_PCH_SPLIT(dev) (INTEL_PCH_TYPE(dev) != PCH_NONE) |
cae5852d | 1933 | |
040d2baa BW |
1934 | /* DPF == dynamic parity feature */ |
1935 | #define HAS_L3_DPF(dev) (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) | |
1936 | #define NUM_L3_SLICES(dev) (IS_HSW_GT3(dev) ? 2 : HAS_L3_DPF(dev)) | |
e1ef7cc2 | 1937 | |
c8735b0c BW |
1938 | #define GT_FREQUENCY_MULTIPLIER 50 |
1939 | ||
05394f39 CW |
1940 | #include "i915_trace.h" |
1941 | ||
baa70943 | 1942 | extern const struct drm_ioctl_desc i915_ioctls[]; |
b3a83639 DA |
1943 | extern int i915_max_ioctl; |
1944 | ||
6a9ee8af DA |
1945 | extern int i915_suspend(struct drm_device *dev, pm_message_t state); |
1946 | extern int i915_resume(struct drm_device *dev); | |
7c1c2871 DA |
1947 | extern int i915_master_create(struct drm_device *dev, struct drm_master *master); |
1948 | extern void i915_master_destroy(struct drm_device *dev, struct drm_master *master); | |
1949 | ||
d330a953 JN |
1950 | /* i915_params.c */ |
1951 | struct i915_params { | |
1952 | int modeset; | |
1953 | int panel_ignore_lid; | |
1954 | unsigned int powersave; | |
1955 | int semaphores; | |
1956 | unsigned int lvds_downclock; | |
1957 | int lvds_channel_mode; | |
1958 | int panel_use_ssc; | |
1959 | int vbt_sdvo_panel_type; | |
1960 | int enable_rc6; | |
1961 | int enable_fbc; | |
d330a953 JN |
1962 | int enable_ppgtt; |
1963 | int enable_psr; | |
1964 | unsigned int preliminary_hw_support; | |
1965 | int disable_power_well; | |
1966 | int enable_ips; | |
d330a953 JN |
1967 | int enable_pc8; |
1968 | int pc8_timeout; | |
e5aa6541 DL |
1969 | int invert_brightness; |
1970 | /* leave bools at the end to not create holes */ | |
1971 | bool enable_hangcheck; | |
1972 | bool fastboot; | |
d330a953 JN |
1973 | bool prefault_disable; |
1974 | bool reset; | |
a0bae57f | 1975 | bool disable_display; |
d330a953 JN |
1976 | }; |
1977 | extern struct i915_params i915 __read_mostly; | |
1978 | ||
1da177e4 | 1979 | /* i915_dma.c */ |
d05c617e | 1980 | void i915_update_dri1_breadcrumb(struct drm_device *dev); |
84b1fd10 | 1981 | extern void i915_kernel_lost_context(struct drm_device * dev); |
22eae947 | 1982 | extern int i915_driver_load(struct drm_device *, unsigned long flags); |
ba8bbcf6 | 1983 | extern int i915_driver_unload(struct drm_device *); |
673a394b | 1984 | extern int i915_driver_open(struct drm_device *dev, struct drm_file *file_priv); |
84b1fd10 | 1985 | extern void i915_driver_lastclose(struct drm_device * dev); |
6c340eac EA |
1986 | extern void i915_driver_preclose(struct drm_device *dev, |
1987 | struct drm_file *file_priv); | |
673a394b EA |
1988 | extern void i915_driver_postclose(struct drm_device *dev, |
1989 | struct drm_file *file_priv); | |
84b1fd10 | 1990 | extern int i915_driver_device_is_agp(struct drm_device * dev); |
c43b5634 | 1991 | #ifdef CONFIG_COMPAT |
0d6aa60b DA |
1992 | extern long i915_compat_ioctl(struct file *filp, unsigned int cmd, |
1993 | unsigned long arg); | |
c43b5634 | 1994 | #endif |
673a394b | 1995 | extern int i915_emit_box(struct drm_device *dev, |
c4e7a414 CW |
1996 | struct drm_clip_rect *box, |
1997 | int DR1, int DR4); | |
8e96d9c4 | 1998 | extern int intel_gpu_reset(struct drm_device *dev); |
d4b8bb2a | 1999 | extern int i915_reset(struct drm_device *dev); |
7648fa99 JB |
2000 | extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv); |
2001 | extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv); | |
2002 | extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv); | |
2003 | extern void i915_update_gfx_val(struct drm_i915_private *dev_priv); | |
2004 | ||
073f34d9 | 2005 | extern void intel_console_resume(struct work_struct *work); |
af6061af | 2006 | |
1da177e4 | 2007 | /* i915_irq.c */ |
10cd45b6 | 2008 | void i915_queue_hangcheck(struct drm_device *dev); |
527f9e90 | 2009 | void i915_handle_error(struct drm_device *dev, bool wedged); |
1da177e4 | 2010 | |
76c3552f D |
2011 | void gen6_set_pm_mask(struct drm_i915_private *dev_priv, u32 pm_iir, |
2012 | int new_delay); | |
f71d4af4 | 2013 | extern void intel_irq_init(struct drm_device *dev); |
20afbda2 | 2014 | extern void intel_hpd_init(struct drm_device *dev); |
907b28c5 CW |
2015 | |
2016 | extern void intel_uncore_sanitize(struct drm_device *dev); | |
2017 | extern void intel_uncore_early_sanitize(struct drm_device *dev); | |
2018 | extern void intel_uncore_init(struct drm_device *dev); | |
907b28c5 | 2019 | extern void intel_uncore_check_errors(struct drm_device *dev); |
aec347ab | 2020 | extern void intel_uncore_fini(struct drm_device *dev); |
b1f14ad0 | 2021 | |
7c463586 | 2022 | void |
755e9019 ID |
2023 | i915_enable_pipestat(drm_i915_private_t *dev_priv, enum pipe pipe, |
2024 | u32 status_mask); | |
7c463586 KP |
2025 | |
2026 | void | |
755e9019 ID |
2027 | i915_disable_pipestat(drm_i915_private_t *dev_priv, enum pipe pipe, |
2028 | u32 status_mask); | |
7c463586 | 2029 | |
673a394b EA |
2030 | /* i915_gem.c */ |
2031 | int i915_gem_init_ioctl(struct drm_device *dev, void *data, | |
2032 | struct drm_file *file_priv); | |
2033 | int i915_gem_create_ioctl(struct drm_device *dev, void *data, | |
2034 | struct drm_file *file_priv); | |
2035 | int i915_gem_pread_ioctl(struct drm_device *dev, void *data, | |
2036 | struct drm_file *file_priv); | |
2037 | int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data, | |
2038 | struct drm_file *file_priv); | |
2039 | int i915_gem_mmap_ioctl(struct drm_device *dev, void *data, | |
2040 | struct drm_file *file_priv); | |
de151cf6 JB |
2041 | int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data, |
2042 | struct drm_file *file_priv); | |
673a394b EA |
2043 | int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data, |
2044 | struct drm_file *file_priv); | |
2045 | int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data, | |
2046 | struct drm_file *file_priv); | |
2047 | int i915_gem_execbuffer(struct drm_device *dev, void *data, | |
2048 | struct drm_file *file_priv); | |
76446cac JB |
2049 | int i915_gem_execbuffer2(struct drm_device *dev, void *data, |
2050 | struct drm_file *file_priv); | |
673a394b EA |
2051 | int i915_gem_pin_ioctl(struct drm_device *dev, void *data, |
2052 | struct drm_file *file_priv); | |
2053 | int i915_gem_unpin_ioctl(struct drm_device *dev, void *data, | |
2054 | struct drm_file *file_priv); | |
2055 | int i915_gem_busy_ioctl(struct drm_device *dev, void *data, | |
2056 | struct drm_file *file_priv); | |
199adf40 BW |
2057 | int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data, |
2058 | struct drm_file *file); | |
2059 | int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data, | |
2060 | struct drm_file *file); | |
673a394b EA |
2061 | int i915_gem_throttle_ioctl(struct drm_device *dev, void *data, |
2062 | struct drm_file *file_priv); | |
3ef94daa CW |
2063 | int i915_gem_madvise_ioctl(struct drm_device *dev, void *data, |
2064 | struct drm_file *file_priv); | |
673a394b EA |
2065 | int i915_gem_entervt_ioctl(struct drm_device *dev, void *data, |
2066 | struct drm_file *file_priv); | |
2067 | int i915_gem_leavevt_ioctl(struct drm_device *dev, void *data, | |
2068 | struct drm_file *file_priv); | |
2069 | int i915_gem_set_tiling(struct drm_device *dev, void *data, | |
2070 | struct drm_file *file_priv); | |
2071 | int i915_gem_get_tiling(struct drm_device *dev, void *data, | |
2072 | struct drm_file *file_priv); | |
5a125c3c EA |
2073 | int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data, |
2074 | struct drm_file *file_priv); | |
23ba4fd0 BW |
2075 | int i915_gem_wait_ioctl(struct drm_device *dev, void *data, |
2076 | struct drm_file *file_priv); | |
673a394b | 2077 | void i915_gem_load(struct drm_device *dev); |
42dcedd4 CW |
2078 | void *i915_gem_object_alloc(struct drm_device *dev); |
2079 | void i915_gem_object_free(struct drm_i915_gem_object *obj); | |
37e680a1 CW |
2080 | void i915_gem_object_init(struct drm_i915_gem_object *obj, |
2081 | const struct drm_i915_gem_object_ops *ops); | |
05394f39 CW |
2082 | struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev, |
2083 | size_t size); | |
7e0d96bc BW |
2084 | void i915_init_vm(struct drm_i915_private *dev_priv, |
2085 | struct i915_address_space *vm); | |
673a394b | 2086 | void i915_gem_free_object(struct drm_gem_object *obj); |
2f633156 | 2087 | void i915_gem_vma_destroy(struct i915_vma *vma); |
42dcedd4 | 2088 | |
1ec9e26d DV |
2089 | #define PIN_MAPPABLE 0x1 |
2090 | #define PIN_NONBLOCK 0x2 | |
bf3d149b | 2091 | #define PIN_GLOBAL 0x4 |
2021746e | 2092 | int __must_check i915_gem_object_pin(struct drm_i915_gem_object *obj, |
c37e2204 | 2093 | struct i915_address_space *vm, |
2021746e | 2094 | uint32_t alignment, |
1ec9e26d | 2095 | unsigned flags); |
07fe0b12 | 2096 | int __must_check i915_vma_unbind(struct i915_vma *vma); |
dd624afd | 2097 | int i915_gem_object_put_pages(struct drm_i915_gem_object *obj); |
48018a57 | 2098 | void i915_gem_release_all_mmaps(struct drm_i915_private *dev_priv); |
05394f39 | 2099 | void i915_gem_release_mmap(struct drm_i915_gem_object *obj); |
673a394b | 2100 | void i915_gem_lastclose(struct drm_device *dev); |
f787a5f5 | 2101 | |
37e680a1 | 2102 | int __must_check i915_gem_object_get_pages(struct drm_i915_gem_object *obj); |
9da3da66 CW |
2103 | static inline struct page *i915_gem_object_get_page(struct drm_i915_gem_object *obj, int n) |
2104 | { | |
67d5a50c ID |
2105 | struct sg_page_iter sg_iter; |
2106 | ||
2107 | for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, n) | |
2db76d7c | 2108 | return sg_page_iter_page(&sg_iter); |
67d5a50c ID |
2109 | |
2110 | return NULL; | |
9da3da66 | 2111 | } |
a5570178 CW |
2112 | static inline void i915_gem_object_pin_pages(struct drm_i915_gem_object *obj) |
2113 | { | |
2114 | BUG_ON(obj->pages == NULL); | |
2115 | obj->pages_pin_count++; | |
2116 | } | |
2117 | static inline void i915_gem_object_unpin_pages(struct drm_i915_gem_object *obj) | |
2118 | { | |
2119 | BUG_ON(obj->pages_pin_count == 0); | |
2120 | obj->pages_pin_count--; | |
2121 | } | |
2122 | ||
54cf91dc | 2123 | int __must_check i915_mutex_lock_interruptible(struct drm_device *dev); |
2911a35b BW |
2124 | int i915_gem_object_sync(struct drm_i915_gem_object *obj, |
2125 | struct intel_ring_buffer *to); | |
e2d05a8b BW |
2126 | void i915_vma_move_to_active(struct i915_vma *vma, |
2127 | struct intel_ring_buffer *ring); | |
ff72145b DA |
2128 | int i915_gem_dumb_create(struct drm_file *file_priv, |
2129 | struct drm_device *dev, | |
2130 | struct drm_mode_create_dumb *args); | |
2131 | int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev, | |
2132 | uint32_t handle, uint64_t *offset); | |
f787a5f5 CW |
2133 | /** |
2134 | * Returns true if seq1 is later than seq2. | |
2135 | */ | |
2136 | static inline bool | |
2137 | i915_seqno_passed(uint32_t seq1, uint32_t seq2) | |
2138 | { | |
2139 | return (int32_t)(seq1 - seq2) >= 0; | |
2140 | } | |
2141 | ||
fca26bb4 MK |
2142 | int __must_check i915_gem_get_seqno(struct drm_device *dev, u32 *seqno); |
2143 | int __must_check i915_gem_set_seqno(struct drm_device *dev, u32 seqno); | |
06d98131 | 2144 | int __must_check i915_gem_object_get_fence(struct drm_i915_gem_object *obj); |
d9e86c0e | 2145 | int __must_check i915_gem_object_put_fence(struct drm_i915_gem_object *obj); |
2021746e | 2146 | |
9a5a53b3 | 2147 | static inline bool |
1690e1eb CW |
2148 | i915_gem_object_pin_fence(struct drm_i915_gem_object *obj) |
2149 | { | |
2150 | if (obj->fence_reg != I915_FENCE_REG_NONE) { | |
2151 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; | |
2152 | dev_priv->fence_regs[obj->fence_reg].pin_count++; | |
9a5a53b3 CW |
2153 | return true; |
2154 | } else | |
2155 | return false; | |
1690e1eb CW |
2156 | } |
2157 | ||
2158 | static inline void | |
2159 | i915_gem_object_unpin_fence(struct drm_i915_gem_object *obj) | |
2160 | { | |
2161 | if (obj->fence_reg != I915_FENCE_REG_NONE) { | |
2162 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; | |
b8c3af76 | 2163 | WARN_ON(dev_priv->fence_regs[obj->fence_reg].pin_count <= 0); |
1690e1eb CW |
2164 | dev_priv->fence_regs[obj->fence_reg].pin_count--; |
2165 | } | |
2166 | } | |
2167 | ||
8d9fc7fd CW |
2168 | struct drm_i915_gem_request * |
2169 | i915_gem_find_active_request(struct intel_ring_buffer *ring); | |
2170 | ||
b29c19b6 | 2171 | bool i915_gem_retire_requests(struct drm_device *dev); |
a71d8d94 | 2172 | void i915_gem_retire_requests_ring(struct intel_ring_buffer *ring); |
33196ded | 2173 | int __must_check i915_gem_check_wedge(struct i915_gpu_error *error, |
d6b2c790 | 2174 | bool interruptible); |
1f83fee0 DV |
2175 | static inline bool i915_reset_in_progress(struct i915_gpu_error *error) |
2176 | { | |
2177 | return unlikely(atomic_read(&error->reset_counter) | |
2ac0f450 | 2178 | & (I915_RESET_IN_PROGRESS_FLAG | I915_WEDGED)); |
1f83fee0 DV |
2179 | } |
2180 | ||
2181 | static inline bool i915_terminally_wedged(struct i915_gpu_error *error) | |
2182 | { | |
2ac0f450 MK |
2183 | return atomic_read(&error->reset_counter) & I915_WEDGED; |
2184 | } | |
2185 | ||
2186 | static inline u32 i915_reset_count(struct i915_gpu_error *error) | |
2187 | { | |
2188 | return ((atomic_read(&error->reset_counter) & ~I915_WEDGED) + 1) / 2; | |
1f83fee0 | 2189 | } |
a71d8d94 | 2190 | |
069efc1d | 2191 | void i915_gem_reset(struct drm_device *dev); |
000433b6 | 2192 | bool i915_gem_clflush_object(struct drm_i915_gem_object *obj, bool force); |
a8198eea | 2193 | int __must_check i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj); |
1070a42b | 2194 | int __must_check i915_gem_init(struct drm_device *dev); |
f691e2f4 | 2195 | int __must_check i915_gem_init_hw(struct drm_device *dev); |
c3787e2e | 2196 | int i915_gem_l3_remap(struct intel_ring_buffer *ring, int slice); |
f691e2f4 | 2197 | void i915_gem_init_swizzling(struct drm_device *dev); |
79e53945 | 2198 | void i915_gem_cleanup_ringbuffer(struct drm_device *dev); |
b2da9fe5 | 2199 | int __must_check i915_gpu_idle(struct drm_device *dev); |
45c5f202 | 2200 | int __must_check i915_gem_suspend(struct drm_device *dev); |
0025c077 MK |
2201 | int __i915_add_request(struct intel_ring_buffer *ring, |
2202 | struct drm_file *file, | |
7d736f4f | 2203 | struct drm_i915_gem_object *batch_obj, |
0025c077 MK |
2204 | u32 *seqno); |
2205 | #define i915_add_request(ring, seqno) \ | |
854c94a7 | 2206 | __i915_add_request(ring, NULL, NULL, seqno) |
199b2bc2 BW |
2207 | int __must_check i915_wait_seqno(struct intel_ring_buffer *ring, |
2208 | uint32_t seqno); | |
de151cf6 | 2209 | int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf); |
2021746e CW |
2210 | int __must_check |
2211 | i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, | |
2212 | bool write); | |
2213 | int __must_check | |
dabdfe02 CW |
2214 | i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write); |
2215 | int __must_check | |
2da3b9b9 CW |
2216 | i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj, |
2217 | u32 alignment, | |
2021746e | 2218 | struct intel_ring_buffer *pipelined); |
cc98b413 | 2219 | void i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object *obj); |
71acb5eb | 2220 | int i915_gem_attach_phys_object(struct drm_device *dev, |
05394f39 | 2221 | struct drm_i915_gem_object *obj, |
6eeefaf3 CW |
2222 | int id, |
2223 | int align); | |
71acb5eb | 2224 | void i915_gem_detach_phys_object(struct drm_device *dev, |
05394f39 | 2225 | struct drm_i915_gem_object *obj); |
71acb5eb | 2226 | void i915_gem_free_all_phys_object(struct drm_device *dev); |
b29c19b6 | 2227 | int i915_gem_open(struct drm_device *dev, struct drm_file *file); |
05394f39 | 2228 | void i915_gem_release(struct drm_device *dev, struct drm_file *file); |
673a394b | 2229 | |
0fa87796 ID |
2230 | uint32_t |
2231 | i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode); | |
467cffba | 2232 | uint32_t |
d865110c ID |
2233 | i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size, |
2234 | int tiling_mode, bool fenced); | |
467cffba | 2235 | |
e4ffd173 CW |
2236 | int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj, |
2237 | enum i915_cache_level cache_level); | |
2238 | ||
1286ff73 DV |
2239 | struct drm_gem_object *i915_gem_prime_import(struct drm_device *dev, |
2240 | struct dma_buf *dma_buf); | |
2241 | ||
2242 | struct dma_buf *i915_gem_prime_export(struct drm_device *dev, | |
2243 | struct drm_gem_object *gem_obj, int flags); | |
2244 | ||
19b2dbde CW |
2245 | void i915_gem_restore_fences(struct drm_device *dev); |
2246 | ||
a70a3148 BW |
2247 | unsigned long i915_gem_obj_offset(struct drm_i915_gem_object *o, |
2248 | struct i915_address_space *vm); | |
2249 | bool i915_gem_obj_bound_any(struct drm_i915_gem_object *o); | |
2250 | bool i915_gem_obj_bound(struct drm_i915_gem_object *o, | |
2251 | struct i915_address_space *vm); | |
2252 | unsigned long i915_gem_obj_size(struct drm_i915_gem_object *o, | |
2253 | struct i915_address_space *vm); | |
2254 | struct i915_vma *i915_gem_obj_to_vma(struct drm_i915_gem_object *obj, | |
2255 | struct i915_address_space *vm); | |
accfef2e BW |
2256 | struct i915_vma * |
2257 | i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object *obj, | |
2258 | struct i915_address_space *vm); | |
5c2abbea BW |
2259 | |
2260 | struct i915_vma *i915_gem_obj_to_ggtt(struct drm_i915_gem_object *obj); | |
d7f46fc4 BW |
2261 | static inline bool i915_gem_obj_is_pinned(struct drm_i915_gem_object *obj) { |
2262 | struct i915_vma *vma; | |
2263 | list_for_each_entry(vma, &obj->vma_list, vma_link) | |
2264 | if (vma->pin_count > 0) | |
2265 | return true; | |
2266 | return false; | |
2267 | } | |
5c2abbea | 2268 | |
a70a3148 BW |
2269 | /* Some GGTT VM helpers */ |
2270 | #define obj_to_ggtt(obj) \ | |
2271 | (&((struct drm_i915_private *)(obj)->base.dev->dev_private)->gtt.base) | |
2272 | static inline bool i915_is_ggtt(struct i915_address_space *vm) | |
2273 | { | |
2274 | struct i915_address_space *ggtt = | |
2275 | &((struct drm_i915_private *)(vm)->dev->dev_private)->gtt.base; | |
2276 | return vm == ggtt; | |
2277 | } | |
2278 | ||
2279 | static inline bool i915_gem_obj_ggtt_bound(struct drm_i915_gem_object *obj) | |
2280 | { | |
2281 | return i915_gem_obj_bound(obj, obj_to_ggtt(obj)); | |
2282 | } | |
2283 | ||
2284 | static inline unsigned long | |
2285 | i915_gem_obj_ggtt_offset(struct drm_i915_gem_object *obj) | |
2286 | { | |
2287 | return i915_gem_obj_offset(obj, obj_to_ggtt(obj)); | |
2288 | } | |
2289 | ||
2290 | static inline unsigned long | |
2291 | i915_gem_obj_ggtt_size(struct drm_i915_gem_object *obj) | |
2292 | { | |
2293 | return i915_gem_obj_size(obj, obj_to_ggtt(obj)); | |
2294 | } | |
c37e2204 BW |
2295 | |
2296 | static inline int __must_check | |
2297 | i915_gem_obj_ggtt_pin(struct drm_i915_gem_object *obj, | |
2298 | uint32_t alignment, | |
1ec9e26d | 2299 | unsigned flags) |
c37e2204 | 2300 | { |
bf3d149b | 2301 | return i915_gem_object_pin(obj, obj_to_ggtt(obj), alignment, flags | PIN_GLOBAL); |
c37e2204 | 2302 | } |
a70a3148 | 2303 | |
b287110e DV |
2304 | static inline int |
2305 | i915_gem_object_ggtt_unbind(struct drm_i915_gem_object *obj) | |
2306 | { | |
2307 | return i915_vma_unbind(i915_gem_obj_to_ggtt(obj)); | |
2308 | } | |
2309 | ||
2310 | void i915_gem_object_ggtt_unpin(struct drm_i915_gem_object *obj); | |
2311 | ||
254f965c | 2312 | /* i915_gem_context.c */ |
0eea67eb | 2313 | #define ctx_to_ppgtt(ctx) container_of((ctx)->vm, struct i915_hw_ppgtt, base) |
8245be31 | 2314 | int __must_check i915_gem_context_init(struct drm_device *dev); |
254f965c | 2315 | void i915_gem_context_fini(struct drm_device *dev); |
acce9ffa | 2316 | void i915_gem_context_reset(struct drm_device *dev); |
e422b888 | 2317 | int i915_gem_context_open(struct drm_device *dev, struct drm_file *file); |
2fa48d8d | 2318 | int i915_gem_context_enable(struct drm_i915_private *dev_priv); |
254f965c | 2319 | void i915_gem_context_close(struct drm_device *dev, struct drm_file *file); |
e0556841 | 2320 | int i915_switch_context(struct intel_ring_buffer *ring, |
41bde553 BW |
2321 | struct drm_file *file, struct i915_hw_context *to); |
2322 | struct i915_hw_context * | |
2323 | i915_gem_context_get(struct drm_i915_file_private *file_priv, u32 id); | |
dce3271b MK |
2324 | void i915_gem_context_free(struct kref *ctx_ref); |
2325 | static inline void i915_gem_context_reference(struct i915_hw_context *ctx) | |
2326 | { | |
c482972a BW |
2327 | if (ctx->obj && HAS_HW_CONTEXTS(ctx->obj->base.dev)) |
2328 | kref_get(&ctx->ref); | |
dce3271b MK |
2329 | } |
2330 | ||
2331 | static inline void i915_gem_context_unreference(struct i915_hw_context *ctx) | |
2332 | { | |
c482972a BW |
2333 | if (ctx->obj && HAS_HW_CONTEXTS(ctx->obj->base.dev)) |
2334 | kref_put(&ctx->ref, i915_gem_context_free); | |
dce3271b MK |
2335 | } |
2336 | ||
3fac8978 MK |
2337 | static inline bool i915_gem_context_is_default(const struct i915_hw_context *c) |
2338 | { | |
2339 | return c->id == DEFAULT_CONTEXT_ID; | |
2340 | } | |
2341 | ||
84624813 BW |
2342 | int i915_gem_context_create_ioctl(struct drm_device *dev, void *data, |
2343 | struct drm_file *file); | |
2344 | int i915_gem_context_destroy_ioctl(struct drm_device *dev, void *data, | |
2345 | struct drm_file *file); | |
1286ff73 | 2346 | |
679845ed BW |
2347 | /* i915_gem_evict.c */ |
2348 | int __must_check i915_gem_evict_something(struct drm_device *dev, | |
2349 | struct i915_address_space *vm, | |
2350 | int min_size, | |
2351 | unsigned alignment, | |
2352 | unsigned cache_level, | |
1ec9e26d | 2353 | unsigned flags); |
679845ed BW |
2354 | int i915_gem_evict_vm(struct i915_address_space *vm, bool do_idle); |
2355 | int i915_gem_evict_everything(struct drm_device *dev); | |
1d2a314c | 2356 | |
76aaf220 | 2357 | /* i915_gem_gtt.c */ |
828c7908 BW |
2358 | void i915_check_and_clear_faults(struct drm_device *dev); |
2359 | void i915_gem_suspend_gtt_mappings(struct drm_device *dev); | |
76aaf220 | 2360 | void i915_gem_restore_gtt_mappings(struct drm_device *dev); |
74163907 | 2361 | int __must_check i915_gem_gtt_prepare_object(struct drm_i915_gem_object *obj); |
74163907 | 2362 | void i915_gem_gtt_finish_object(struct drm_i915_gem_object *obj); |
d7e5008f BW |
2363 | void i915_gem_init_global_gtt(struct drm_device *dev); |
2364 | void i915_gem_setup_global_gtt(struct drm_device *dev, unsigned long start, | |
2365 | unsigned long mappable_end, unsigned long end); | |
e76e9aeb | 2366 | int i915_gem_gtt_init(struct drm_device *dev); |
d09105c6 | 2367 | static inline void i915_gem_chipset_flush(struct drm_device *dev) |
e76e9aeb BW |
2368 | { |
2369 | if (INTEL_INFO(dev)->gen < 6) | |
2370 | intel_gtt_chipset_flush(); | |
2371 | } | |
246cbfb5 BW |
2372 | int i915_gem_init_ppgtt(struct drm_device *dev, struct i915_hw_ppgtt *ppgtt); |
2373 | static inline bool intel_enable_ppgtt(struct drm_device *dev, bool full) | |
2374 | { | |
d330a953 | 2375 | if (i915.enable_ppgtt == 0 || !HAS_ALIASING_PPGTT(dev)) |
246cbfb5 | 2376 | return false; |
e76e9aeb | 2377 | |
d330a953 | 2378 | if (i915.enable_ppgtt == 1 && full) |
7e0d96bc | 2379 | return false; |
76aaf220 | 2380 | |
246cbfb5 BW |
2381 | #ifdef CONFIG_INTEL_IOMMU |
2382 | /* Disable ppgtt on SNB if VT-d is on. */ | |
2383 | if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped) { | |
2384 | DRM_INFO("Disabling PPGTT because VT-d is on\n"); | |
2385 | return false; | |
2386 | } | |
2387 | #endif | |
2388 | ||
7e0d96bc BW |
2389 | if (full) |
2390 | return HAS_PPGTT(dev); | |
2391 | else | |
2392 | return HAS_ALIASING_PPGTT(dev); | |
246cbfb5 BW |
2393 | } |
2394 | ||
9797fbfb CW |
2395 | /* i915_gem_stolen.c */ |
2396 | int i915_gem_init_stolen(struct drm_device *dev); | |
11be49eb CW |
2397 | int i915_gem_stolen_setup_compression(struct drm_device *dev, int size); |
2398 | void i915_gem_stolen_cleanup_compression(struct drm_device *dev); | |
9797fbfb | 2399 | void i915_gem_cleanup_stolen(struct drm_device *dev); |
0104fdbb CW |
2400 | struct drm_i915_gem_object * |
2401 | i915_gem_object_create_stolen(struct drm_device *dev, u32 size); | |
866d12b4 CW |
2402 | struct drm_i915_gem_object * |
2403 | i915_gem_object_create_stolen_for_preallocated(struct drm_device *dev, | |
2404 | u32 stolen_offset, | |
2405 | u32 gtt_offset, | |
2406 | u32 size); | |
0104fdbb | 2407 | void i915_gem_object_release_stolen(struct drm_i915_gem_object *obj); |
9797fbfb | 2408 | |
673a394b | 2409 | /* i915_gem_tiling.c */ |
2c1792a1 | 2410 | static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj) |
e9b73c67 CW |
2411 | { |
2412 | drm_i915_private_t *dev_priv = obj->base.dev->dev_private; | |
2413 | ||
2414 | return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 && | |
2415 | obj->tiling_mode != I915_TILING_NONE; | |
2416 | } | |
2417 | ||
673a394b | 2418 | void i915_gem_detect_bit_6_swizzle(struct drm_device *dev); |
05394f39 CW |
2419 | void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj); |
2420 | void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj); | |
673a394b EA |
2421 | |
2422 | /* i915_gem_debug.c */ | |
23bc5982 CW |
2423 | #if WATCH_LISTS |
2424 | int i915_verify_lists(struct drm_device *dev); | |
673a394b | 2425 | #else |
23bc5982 | 2426 | #define i915_verify_lists(dev) 0 |
673a394b | 2427 | #endif |
1da177e4 | 2428 | |
2017263e | 2429 | /* i915_debugfs.c */ |
27c202ad BG |
2430 | int i915_debugfs_init(struct drm_minor *minor); |
2431 | void i915_debugfs_cleanup(struct drm_minor *minor); | |
f8c168fa | 2432 | #ifdef CONFIG_DEBUG_FS |
07144428 DL |
2433 | void intel_display_crc_init(struct drm_device *dev); |
2434 | #else | |
f8c168fa | 2435 | static inline void intel_display_crc_init(struct drm_device *dev) {} |
07144428 | 2436 | #endif |
84734a04 MK |
2437 | |
2438 | /* i915_gpu_error.c */ | |
edc3d884 MK |
2439 | __printf(2, 3) |
2440 | void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...); | |
fc16b48b MK |
2441 | int i915_error_state_to_str(struct drm_i915_error_state_buf *estr, |
2442 | const struct i915_error_state_file_priv *error); | |
4dc955f7 MK |
2443 | int i915_error_state_buf_init(struct drm_i915_error_state_buf *eb, |
2444 | size_t count, loff_t pos); | |
2445 | static inline void i915_error_state_buf_release( | |
2446 | struct drm_i915_error_state_buf *eb) | |
2447 | { | |
2448 | kfree(eb->buf); | |
2449 | } | |
84734a04 MK |
2450 | void i915_capture_error_state(struct drm_device *dev); |
2451 | void i915_error_state_get(struct drm_device *dev, | |
2452 | struct i915_error_state_file_priv *error_priv); | |
2453 | void i915_error_state_put(struct i915_error_state_file_priv *error_priv); | |
2454 | void i915_destroy_error_state(struct drm_device *dev); | |
2455 | ||
2456 | void i915_get_extra_instdone(struct drm_device *dev, uint32_t *instdone); | |
2457 | const char *i915_cache_level_str(int type); | |
2017263e | 2458 | |
317c35d1 JB |
2459 | /* i915_suspend.c */ |
2460 | extern int i915_save_state(struct drm_device *dev); | |
2461 | extern int i915_restore_state(struct drm_device *dev); | |
0a3e67a4 | 2462 | |
d8157a36 DV |
2463 | /* i915_ums.c */ |
2464 | void i915_save_display_reg(struct drm_device *dev); | |
2465 | void i915_restore_display_reg(struct drm_device *dev); | |
317c35d1 | 2466 | |
0136db58 BW |
2467 | /* i915_sysfs.c */ |
2468 | void i915_setup_sysfs(struct drm_device *dev_priv); | |
2469 | void i915_teardown_sysfs(struct drm_device *dev_priv); | |
2470 | ||
f899fc64 CW |
2471 | /* intel_i2c.c */ |
2472 | extern int intel_setup_gmbus(struct drm_device *dev); | |
2473 | extern void intel_teardown_gmbus(struct drm_device *dev); | |
8f375e10 | 2474 | static inline bool intel_gmbus_is_port_valid(unsigned port) |
3bd7d909 | 2475 | { |
2ed06c93 | 2476 | return (port >= GMBUS_PORT_SSC && port <= GMBUS_PORT_DPD); |
3bd7d909 DK |
2477 | } |
2478 | ||
2479 | extern struct i2c_adapter *intel_gmbus_get_adapter( | |
2480 | struct drm_i915_private *dev_priv, unsigned port); | |
e957d772 CW |
2481 | extern void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed); |
2482 | extern void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit); | |
8f375e10 | 2483 | static inline bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter) |
b8232e90 CW |
2484 | { |
2485 | return container_of(adapter, struct intel_gmbus, adapter)->force_bit; | |
2486 | } | |
f899fc64 CW |
2487 | extern void intel_i2c_reset(struct drm_device *dev); |
2488 | ||
3b617967 | 2489 | /* intel_opregion.c */ |
9c4b0a68 | 2490 | struct intel_encoder; |
44834a67 CW |
2491 | extern int intel_opregion_setup(struct drm_device *dev); |
2492 | #ifdef CONFIG_ACPI | |
2493 | extern void intel_opregion_init(struct drm_device *dev); | |
2494 | extern void intel_opregion_fini(struct drm_device *dev); | |
3b617967 | 2495 | extern void intel_opregion_asle_intr(struct drm_device *dev); |
9c4b0a68 JN |
2496 | extern int intel_opregion_notify_encoder(struct intel_encoder *intel_encoder, |
2497 | bool enable); | |
ecbc5cf3 JN |
2498 | extern int intel_opregion_notify_adapter(struct drm_device *dev, |
2499 | pci_power_t state); | |
65e082c9 | 2500 | #else |
44834a67 CW |
2501 | static inline void intel_opregion_init(struct drm_device *dev) { return; } |
2502 | static inline void intel_opregion_fini(struct drm_device *dev) { return; } | |
3b617967 | 2503 | static inline void intel_opregion_asle_intr(struct drm_device *dev) { return; } |
9c4b0a68 JN |
2504 | static inline int |
2505 | intel_opregion_notify_encoder(struct intel_encoder *intel_encoder, bool enable) | |
2506 | { | |
2507 | return 0; | |
2508 | } | |
ecbc5cf3 JN |
2509 | static inline int |
2510 | intel_opregion_notify_adapter(struct drm_device *dev, pci_power_t state) | |
2511 | { | |
2512 | return 0; | |
2513 | } | |
65e082c9 | 2514 | #endif |
8ee1c3db | 2515 | |
723bfd70 JB |
2516 | /* intel_acpi.c */ |
2517 | #ifdef CONFIG_ACPI | |
2518 | extern void intel_register_dsm_handler(void); | |
2519 | extern void intel_unregister_dsm_handler(void); | |
2520 | #else | |
2521 | static inline void intel_register_dsm_handler(void) { return; } | |
2522 | static inline void intel_unregister_dsm_handler(void) { return; } | |
2523 | #endif /* CONFIG_ACPI */ | |
2524 | ||
79e53945 | 2525 | /* modesetting */ |
f817586c | 2526 | extern void intel_modeset_init_hw(struct drm_device *dev); |
7d708ee4 | 2527 | extern void intel_modeset_suspend_hw(struct drm_device *dev); |
79e53945 | 2528 | extern void intel_modeset_init(struct drm_device *dev); |
2c7111db | 2529 | extern void intel_modeset_gem_init(struct drm_device *dev); |
79e53945 | 2530 | extern void intel_modeset_cleanup(struct drm_device *dev); |
4932e2c3 | 2531 | extern void intel_connector_unregister(struct intel_connector *); |
28d52043 | 2532 | extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state); |
45e2b5f6 DV |
2533 | extern void intel_modeset_setup_hw_state(struct drm_device *dev, |
2534 | bool force_restore); | |
44cec740 | 2535 | extern void i915_redisable_vga(struct drm_device *dev); |
04098753 | 2536 | extern void i915_redisable_vga_power_on(struct drm_device *dev); |
ee5382ae | 2537 | extern bool intel_fbc_enabled(struct drm_device *dev); |
43a9539f | 2538 | extern void intel_disable_fbc(struct drm_device *dev); |
7648fa99 | 2539 | extern bool ironlake_set_drps(struct drm_device *dev, u8 val); |
dde86e2d | 2540 | extern void intel_init_pch_refclk(struct drm_device *dev); |
3b8d8d91 | 2541 | extern void gen6_set_rps(struct drm_device *dev, u8 val); |
0a073b84 JB |
2542 | extern void valleyview_set_rps(struct drm_device *dev, u8 val); |
2543 | extern int valleyview_rps_max_freq(struct drm_i915_private *dev_priv); | |
2544 | extern int valleyview_rps_min_freq(struct drm_i915_private *dev_priv); | |
0206e353 AJ |
2545 | extern void intel_detect_pch(struct drm_device *dev); |
2546 | extern int intel_trans_dp_port_sel(struct drm_crtc *crtc); | |
0136db58 | 2547 | extern int intel_enable_rc6(const struct drm_device *dev); |
3bad0781 | 2548 | |
2911a35b | 2549 | extern bool i915_semaphore_is_enabled(struct drm_device *dev); |
c0c7babc BW |
2550 | int i915_reg_read_ioctl(struct drm_device *dev, void *data, |
2551 | struct drm_file *file); | |
b6359918 MK |
2552 | int i915_get_reset_stats_ioctl(struct drm_device *dev, void *data, |
2553 | struct drm_file *file); | |
575155a9 | 2554 | |
6ef3d427 CW |
2555 | /* overlay */ |
2556 | extern struct intel_overlay_error_state *intel_overlay_capture_error_state(struct drm_device *dev); | |
edc3d884 MK |
2557 | extern void intel_overlay_print_error_state(struct drm_i915_error_state_buf *e, |
2558 | struct intel_overlay_error_state *error); | |
c4a1d9e4 CW |
2559 | |
2560 | extern struct intel_display_error_state *intel_display_capture_error_state(struct drm_device *dev); | |
edc3d884 | 2561 | extern void intel_display_print_error_state(struct drm_i915_error_state_buf *e, |
c4a1d9e4 CW |
2562 | struct drm_device *dev, |
2563 | struct intel_display_error_state *error); | |
6ef3d427 | 2564 | |
b7287d80 BW |
2565 | /* On SNB platform, before reading ring registers forcewake bit |
2566 | * must be set to prevent GT core from power down and stale values being | |
2567 | * returned. | |
2568 | */ | |
c8d9a590 D |
2569 | void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv, int fw_engine); |
2570 | void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv, int fw_engine); | |
e998c40f | 2571 | void assert_force_wake_inactive(struct drm_i915_private *dev_priv); |
b7287d80 | 2572 | |
42c0526c BW |
2573 | int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u8 mbox, u32 *val); |
2574 | int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val); | |
59de0813 JN |
2575 | |
2576 | /* intel_sideband.c */ | |
64936258 JN |
2577 | u32 vlv_punit_read(struct drm_i915_private *dev_priv, u8 addr); |
2578 | void vlv_punit_write(struct drm_i915_private *dev_priv, u8 addr, u32 val); | |
2579 | u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr); | |
e9f882a3 JN |
2580 | u32 vlv_gpio_nc_read(struct drm_i915_private *dev_priv, u32 reg); |
2581 | void vlv_gpio_nc_write(struct drm_i915_private *dev_priv, u32 reg, u32 val); | |
2582 | u32 vlv_cck_read(struct drm_i915_private *dev_priv, u32 reg); | |
2583 | void vlv_cck_write(struct drm_i915_private *dev_priv, u32 reg, u32 val); | |
2584 | u32 vlv_ccu_read(struct drm_i915_private *dev_priv, u32 reg); | |
2585 | void vlv_ccu_write(struct drm_i915_private *dev_priv, u32 reg, u32 val); | |
f3419158 JB |
2586 | u32 vlv_bunit_read(struct drm_i915_private *dev_priv, u32 reg); |
2587 | void vlv_bunit_write(struct drm_i915_private *dev_priv, u32 reg, u32 val); | |
e9f882a3 JN |
2588 | u32 vlv_gps_core_read(struct drm_i915_private *dev_priv, u32 reg); |
2589 | void vlv_gps_core_write(struct drm_i915_private *dev_priv, u32 reg, u32 val); | |
5e69f97f CML |
2590 | u32 vlv_dpio_read(struct drm_i915_private *dev_priv, enum pipe pipe, int reg); |
2591 | void vlv_dpio_write(struct drm_i915_private *dev_priv, enum pipe pipe, int reg, u32 val); | |
59de0813 JN |
2592 | u32 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg, |
2593 | enum intel_sbi_destination destination); | |
2594 | void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value, | |
2595 | enum intel_sbi_destination destination); | |
e9fe51c6 SK |
2596 | u32 vlv_flisdsi_read(struct drm_i915_private *dev_priv, u32 reg); |
2597 | void vlv_flisdsi_write(struct drm_i915_private *dev_priv, u32 reg, u32 val); | |
0a073b84 | 2598 | |
2ec3815f VS |
2599 | int vlv_gpu_freq(struct drm_i915_private *dev_priv, int val); |
2600 | int vlv_freq_opcode(struct drm_i915_private *dev_priv, int val); | |
42c0526c | 2601 | |
940aece4 D |
2602 | void vlv_force_wake_get(struct drm_i915_private *dev_priv, int fw_engine); |
2603 | void vlv_force_wake_put(struct drm_i915_private *dev_priv, int fw_engine); | |
2604 | ||
2605 | #define FORCEWAKE_VLV_RENDER_RANGE_OFFSET(reg) \ | |
2606 | (((reg) >= 0x2000 && (reg) < 0x4000) ||\ | |
2607 | ((reg) >= 0x5000 && (reg) < 0x8000) ||\ | |
2608 | ((reg) >= 0xB000 && (reg) < 0x12000) ||\ | |
2609 | ((reg) >= 0x2E000 && (reg) < 0x30000)) | |
2610 | ||
2611 | #define FORCEWAKE_VLV_MEDIA_RANGE_OFFSET(reg)\ | |
2612 | (((reg) >= 0x12000 && (reg) < 0x14000) ||\ | |
2613 | ((reg) >= 0x22000 && (reg) < 0x24000) ||\ | |
2614 | ((reg) >= 0x30000 && (reg) < 0x40000)) | |
2615 | ||
c8d9a590 D |
2616 | #define FORCEWAKE_RENDER (1 << 0) |
2617 | #define FORCEWAKE_MEDIA (1 << 1) | |
2618 | #define FORCEWAKE_ALL (FORCEWAKE_RENDER | FORCEWAKE_MEDIA) | |
2619 | ||
2620 | ||
0b274481 BW |
2621 | #define I915_READ8(reg) dev_priv->uncore.funcs.mmio_readb(dev_priv, (reg), true) |
2622 | #define I915_WRITE8(reg, val) dev_priv->uncore.funcs.mmio_writeb(dev_priv, (reg), (val), true) | |
2623 | ||
2624 | #define I915_READ16(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), true) | |
2625 | #define I915_WRITE16(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), true) | |
2626 | #define I915_READ16_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), false) | |
2627 | #define I915_WRITE16_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), false) | |
2628 | ||
2629 | #define I915_READ(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), true) | |
2630 | #define I915_WRITE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), true) | |
2631 | #define I915_READ_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), false) | |
2632 | #define I915_WRITE_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), false) | |
2633 | ||
2634 | #define I915_WRITE64(reg, val) dev_priv->uncore.funcs.mmio_writeq(dev_priv, (reg), (val), true) | |
2635 | #define I915_READ64(reg) dev_priv->uncore.funcs.mmio_readq(dev_priv, (reg), true) | |
cae5852d ZN |
2636 | |
2637 | #define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg) | |
2638 | #define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg) | |
2639 | ||
55bc60db VS |
2640 | /* "Broadcast RGB" property */ |
2641 | #define INTEL_BROADCAST_RGB_AUTO 0 | |
2642 | #define INTEL_BROADCAST_RGB_FULL 1 | |
2643 | #define INTEL_BROADCAST_RGB_LIMITED 2 | |
ba4f01a3 | 2644 | |
766aa1c4 VS |
2645 | static inline uint32_t i915_vgacntrl_reg(struct drm_device *dev) |
2646 | { | |
2647 | if (HAS_PCH_SPLIT(dev)) | |
2648 | return CPU_VGACNTRL; | |
2649 | else if (IS_VALLEYVIEW(dev)) | |
2650 | return VLV_VGACNTRL; | |
2651 | else | |
2652 | return VGACNTRL; | |
2653 | } | |
2654 | ||
2bb4629a VS |
2655 | static inline void __user *to_user_ptr(u64 address) |
2656 | { | |
2657 | return (void __user *)(uintptr_t)address; | |
2658 | } | |
2659 | ||
df97729f ID |
2660 | static inline unsigned long msecs_to_jiffies_timeout(const unsigned int m) |
2661 | { | |
2662 | unsigned long j = msecs_to_jiffies(m); | |
2663 | ||
2664 | return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1); | |
2665 | } | |
2666 | ||
2667 | static inline unsigned long | |
2668 | timespec_to_jiffies_timeout(const struct timespec *value) | |
2669 | { | |
2670 | unsigned long j = timespec_to_jiffies(value); | |
2671 | ||
2672 | return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1); | |
2673 | } | |
2674 | ||
dce56b3c PZ |
2675 | /* |
2676 | * If you need to wait X milliseconds between events A and B, but event B | |
2677 | * doesn't happen exactly after event A, you record the timestamp (jiffies) of | |
2678 | * when event A happened, then just before event B you call this function and | |
2679 | * pass the timestamp as the first argument, and X as the second argument. | |
2680 | */ | |
2681 | static inline void | |
2682 | wait_remaining_ms_from_jiffies(unsigned long timestamp_jiffies, int to_wait_ms) | |
2683 | { | |
ec5e0cfb | 2684 | unsigned long target_jiffies, tmp_jiffies, remaining_jiffies; |
dce56b3c PZ |
2685 | |
2686 | /* | |
2687 | * Don't re-read the value of "jiffies" every time since it may change | |
2688 | * behind our back and break the math. | |
2689 | */ | |
2690 | tmp_jiffies = jiffies; | |
2691 | target_jiffies = timestamp_jiffies + | |
2692 | msecs_to_jiffies_timeout(to_wait_ms); | |
2693 | ||
2694 | if (time_after(target_jiffies, tmp_jiffies)) { | |
ec5e0cfb ID |
2695 | remaining_jiffies = target_jiffies - tmp_jiffies; |
2696 | while (remaining_jiffies) | |
2697 | remaining_jiffies = | |
2698 | schedule_timeout_uninterruptible(remaining_jiffies); | |
dce56b3c PZ |
2699 | } |
2700 | } | |
2701 | ||
1da177e4 | 2702 | #endif |