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drm/i915: Filter pci devices based on PCI_CLASS_DISPLAY_VGA
[mirror_ubuntu-artful-kernel.git] / drivers / gpu / drm / i915 / i915_drv.h
CommitLineData
1da177e4
LT		 1/* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
2 */
0d6aa60b 3/*
bc54fd1a 4 *
1da177e4
LT		 5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
6 * All Rights Reserved.
bc54fd1a
DA		 7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
15 *
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
18 * of the Software.
19 *
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27 *
0d6aa60b 28 */
1da177e4
LT		 29
30#ifndef _I915_DRV_H_
31#define _I915_DRV_H_
32
585fb111 33#include "i915_reg.h"
0839ccb8 34#include <linux/io-mapping.h>
585fb111 35
1da177e4
LT		 36/* General customization:
37 */
38
39#define DRIVER_AUTHOR "Tungsten Graphics, Inc."
40
41#define DRIVER_NAME "i915"
42#define DRIVER_DESC "Intel Graphics"
673a394b 43#define DRIVER_DATE "20080730"
1da177e4 44
317c35d1
JB		 45enum pipe {
46 PIPE_A = 0,
47 PIPE_B,
48};
49
1da177e4
LT		 50/* Interface history:
51 *
52 * 1.1: Original.
0d6aa60b
DA		 53 * 1.2: Add Power Management
54 * 1.3: Add vblank support
de227f5f 55 * 1.4: Fix cmdbuffer path, add heap destroy
702880f2 56 * 1.5: Add vblank pipe configuration
2228ed67
MD		 57 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
58 * - Support vertical blank on secondary display pipe
1da177e4
LT		 59 */
60#define DRIVER_MAJOR 1
2228ed67 61#define DRIVER_MINOR 6
1da177e4
LT		 62#define DRIVER_PATCHLEVEL 0
63
673a394b
EA		 64#define WATCH_COHERENCY 0
65#define WATCH_BUF 0
66#define WATCH_EXEC 0
67#define WATCH_LRU 0
68#define WATCH_RELOC 0
69#define WATCH_INACTIVE 0
70#define WATCH_PWRITE 0
71
1da177e4
LT		 72typedef struct _drm_i915_ring_buffer {
73 int tail_mask;
1da177e4
LT		 74 unsigned long Size;
75 u8 *virtual_start;
76 int head;
77 int tail;
78 int space;
79 drm_local_map_t map;
673a394b 80 struct drm_gem_object *ring_obj;
1da177e4
LT		 81} drm_i915_ring_buffer_t;
82
83struct mem_block {
84 struct mem_block *next;
85 struct mem_block *prev;
86 int start;
87 int size;
6c340eac 88 struct drm_file *file_priv; /* NULL: free, -1: heap, other: real files */
1da177e4
LT		 89};
90
0a3e67a4
JB		 91struct opregion_header;
92struct opregion_acpi;
93struct opregion_swsci;
94struct opregion_asle;
95
8ee1c3db
MG		 96struct intel_opregion {
97 struct opregion_header *header;
98 struct opregion_acpi *acpi;
99 struct opregion_swsci *swsci;
100 struct opregion_asle *asle;
101 int enabled;
102};
103
1da177e4 104typedef struct drm_i915_private {
673a394b
EA		 105 struct drm_device *dev;
106
3043c60c 107 void __iomem *regs;
1da177e4 108 drm_local_map_t *sarea;
1da177e4
LT		 109
110 drm_i915_sarea_t *sarea_priv;
111 drm_i915_ring_buffer_t ring;
112
9c8da5eb 113 drm_dma_handle_t *status_page_dmah;
1da177e4 114 void *hw_status_page;
1da177e4 115 dma_addr_t dma_status_page;
0a3e67a4 116 uint32_t counter;
dc7a9319
WZ		 117 unsigned int status_gfx_addr;
118 drm_local_map_t hws_map;
673a394b 119 struct drm_gem_object *hws_obj;
1da177e4 120
a6b54f3f 121 unsigned int cpp;
1da177e4
LT		 122 int back_offset;
123 int front_offset;
124 int current_page;
125 int page_flipping;
1da177e4
LT		 126
127 wait_queue_head_t irq_queue;
128 atomic_t irq_received;
ed4cb414
EA		 129 /** Protects user_irq_refcount and irq_mask_reg */
130 spinlock_t user_irq_lock;
131 /** Refcount for i915_user_irq_get() versus i915_user_irq_put(). */
132 int user_irq_refcount;
133 /** Cached value of IMR to avoid reads in updating the bitfield */
134 u32 irq_mask_reg;
1da177e4
LT		 135
136 int tex_lru_log_granularity;
137 int allow_batchbuffer;
138 struct mem_block *agp_heap;
0d6aa60b 139 unsigned int sr01, adpa, ppcr, dvob, dvoc, lvds;
702880f2 140 int vblank_pipe;
a6b54f3f 141
8ee1c3db
MG		 142 struct intel_opregion opregion;
143
ba8bbcf6
JB		 144 /* Register state */
145 u8 saveLBB;
146 u32 saveDSPACNTR;
147 u32 saveDSPBCNTR;
e948e994 148 u32 saveDSPARB;
881ee988 149 u32 saveRENDERSTANDBY;
ba8bbcf6
JB		 150 u32 savePIPEACONF;
151 u32 savePIPEBCONF;
152 u32 savePIPEASRC;
153 u32 savePIPEBSRC;
154 u32 saveFPA0;
155 u32 saveFPA1;
156 u32 saveDPLL_A;
157 u32 saveDPLL_A_MD;
158 u32 saveHTOTAL_A;
159 u32 saveHBLANK_A;
160 u32 saveHSYNC_A;
161 u32 saveVTOTAL_A;
162 u32 saveVBLANK_A;
163 u32 saveVSYNC_A;
164 u32 saveBCLRPAT_A;
0da3ea12 165 u32 savePIPEASTAT;
ba8bbcf6
JB		 166 u32 saveDSPASTRIDE;
167 u32 saveDSPASIZE;
168 u32 saveDSPAPOS;
585fb111 169 u32 saveDSPAADDR;
ba8bbcf6
JB		 170 u32 saveDSPASURF;
171 u32 saveDSPATILEOFF;
172 u32 savePFIT_PGM_RATIOS;
173 u32 saveBLC_PWM_CTL;
174 u32 saveBLC_PWM_CTL2;
175 u32 saveFPB0;
176 u32 saveFPB1;
177 u32 saveDPLL_B;
178 u32 saveDPLL_B_MD;
179 u32 saveHTOTAL_B;
180 u32 saveHBLANK_B;
181 u32 saveHSYNC_B;
182 u32 saveVTOTAL_B;
183 u32 saveVBLANK_B;
184 u32 saveVSYNC_B;
185 u32 saveBCLRPAT_B;
0da3ea12 186 u32 savePIPEBSTAT;
ba8bbcf6
JB		 187 u32 saveDSPBSTRIDE;
188 u32 saveDSPBSIZE;
189 u32 saveDSPBPOS;
585fb111 190 u32 saveDSPBADDR;
ba8bbcf6
JB		 191 u32 saveDSPBSURF;
192 u32 saveDSPBTILEOFF;
585fb111
JB		 193 u32 saveVGA0;
194 u32 saveVGA1;
195 u32 saveVGA_PD;
ba8bbcf6
JB		 196 u32 saveVGACNTRL;
197 u32 saveADPA;
198 u32 saveLVDS;
585fb111
JB		 199 u32 savePP_ON_DELAYS;
200 u32 savePP_OFF_DELAYS;
ba8bbcf6
JB		 201 u32 saveDVOA;
202 u32 saveDVOB;
203 u32 saveDVOC;
204 u32 savePP_ON;
205 u32 savePP_OFF;
206 u32 savePP_CONTROL;
585fb111 207 u32 savePP_DIVISOR;
ba8bbcf6
JB		 208 u32 savePFIT_CONTROL;
209 u32 save_palette_a[256];
210 u32 save_palette_b[256];
211 u32 saveFBC_CFB_BASE;
212 u32 saveFBC_LL_BASE;
213 u32 saveFBC_CONTROL;
214 u32 saveFBC_CONTROL2;
0da3ea12
JB		 215 u32 saveIER;
216 u32 saveIIR;
217 u32 saveIMR;
1f84e550 218 u32 saveCACHE_MODE_0;
e948e994 219 u32 saveD_STATE;
585fb111 220 u32 saveCG_2D_DIS;
1f84e550 221 u32 saveMI_ARB_STATE;
ba8bbcf6
JB		 222 u32 saveSWF0[16];
223 u32 saveSWF1[16];
224 u32 saveSWF2[3];
225 u8 saveMSR;
226 u8 saveSR[8];
123f794f 227 u8 saveGR[25];
ba8bbcf6 228 u8 saveAR_INDEX;
a59e122a 229 u8 saveAR[21];
ba8bbcf6
JB		 230 u8 saveDACMASK;
231 u8 saveDACDATA[256*3]; /* 256 3-byte colors */
a59e122a 232 u8 saveCR[37];
673a394b
EA		 233
234 struct {
235 struct drm_mm gtt_space;
236
0839ccb8
KP		 237 struct io_mapping *gtt_mapping;
238
673a394b
EA		 239 /**
240 * List of objects currently involved in rendering from the
241 * ringbuffer.
242 *
243 * A reference is held on the buffer while on this list.
244 */
245 struct list_head active_list;
246
247 /**
248 * List of objects which are not in the ringbuffer but which
249 * still have a write_domain which needs to be flushed before
250 * unbinding.
251 *
252 * A reference is held on the buffer while on this list.
253 */
254 struct list_head flushing_list;
255
256 /**
257 * LRU list of objects which are not in the ringbuffer and
258 * are ready to unbind, but are still in the GTT.
259 *
260 * A reference is not held on the buffer while on this list,
261 * as merely being GTT-bound shouldn't prevent its being
262 * freed, and we'll pull it off the list in the free path.
263 */
264 struct list_head inactive_list;
265
266 /**
267 * List of breadcrumbs associated with GPU requests currently
268 * outstanding.
269 */
270 struct list_head request_list;
271
272 /**
273 * We leave the user IRQ off as much as possible,
274 * but this means that requests will finish and never
275 * be retired once the system goes idle. Set a timer to
276 * fire periodically while the ring is running. When it
277 * fires, go retire requests.
278 */
279 struct delayed_work retire_work;
280
281 uint32_t next_gem_seqno;
282
283 /**
284 * Waiting sequence number, if any
285 */
286 uint32_t waiting_gem_seqno;
287
288 /**
289 * Last seq seen at irq time
290 */
291 uint32_t irq_gem_seqno;
292
293 /**
294 * Flag if the X Server, and thus DRM, is not currently in
295 * control of the device.
296 *
297 * This is set between LeaveVT and EnterVT. It needs to be
298 * replaced with a semaphore. It also needs to be
299 * transitioned away from for kernel modesetting.
300 */
301 int suspended;
302
303 /**
304 * Flag if the hardware appears to be wedged.
305 *
306 * This is set when attempts to idle the device timeout.
307 * It prevents command submission from occuring and makes
308 * every pending request fail
309 */
310 int wedged;
311
312 /** Bit 6 swizzling required for X tiling */
313 uint32_t bit_6_swizzle_x;
314 /** Bit 6 swizzling required for Y tiling */
315 uint32_t bit_6_swizzle_y;
316 } mm;
1da177e4
LT		 317} drm_i915_private_t;
318
673a394b
EA		 319/** driver private structure attached to each drm_gem_object */
320struct drm_i915_gem_object {
321 struct drm_gem_object *obj;
322
323 /** Current space allocated to this object in the GTT, if any. */
324 struct drm_mm_node *gtt_space;
325
326 /** This object's place on the active/flushing/inactive lists */
327 struct list_head list;
328
329 /**
330 * This is set if the object is on the active or flushing lists
331 * (has pending rendering), and is not set if it's on inactive (ready
332 * to be unbound).
333 */
334 int active;
335
336 /**
337 * This is set if the object has been written to since last bound
338 * to the GTT
339 */
340 int dirty;
341
342 /** AGP memory structure for our GTT binding. */
343 DRM_AGP_MEM *agp_mem;
344
345 struct page **page_list;
346
347 /**
348 * Current offset of the object in GTT space.
349 *
350 * This is the same as gtt_space->start
351 */
352 uint32_t gtt_offset;
353
354 /** Boolean whether this object has a valid gtt offset. */
355 int gtt_bound;
356
357 /** How many users have pinned this object in GTT space */
358 int pin_count;
359
360 /** Breadcrumb of last rendering to the buffer. */
361 uint32_t last_rendering_seqno;
362
363 /** Current tiling mode for the object. */
364 uint32_t tiling_mode;
365
ba1eb1d8
KP		 366 /** AGP mapping type (AGP_USER_MEMORY or AGP_USER_CACHED_MEMORY */
367 uint32_t agp_type;
368
673a394b
EA		 369 /**
370 * Flagging of which individual pages are valid in GEM_DOMAIN_CPU when
371 * GEM_DOMAIN_CPU is not in the object's read domain.
372 */
373 uint8_t *page_cpu_valid;
374};
375
376/**
377 * Request queue structure.
378 *
379 * The request queue allows us to note sequence numbers that have been emitted
380 * and may be associated with active buffers to be retired.
381 *
382 * By keeping this list, we can avoid having to do questionable
383 * sequence-number comparisons on buffer last_rendering_seqnos, and associate
384 * an emission time with seqnos for tracking how far ahead of the GPU we are.
385 */
386struct drm_i915_gem_request {
387 /** GEM sequence number associated with this request. */
388 uint32_t seqno;
389
390 /** Time at which this request was emitted, in jiffies. */
391 unsigned long emitted_jiffies;
392
393 /** Cache domains that were flushed at the start of the request. */
394 uint32_t flush_domains;
395
396 struct list_head list;
397};
398
399struct drm_i915_file_private {
400 struct {
401 uint32_t last_gem_seqno;
402 uint32_t last_gem_throttle_seqno;
403 } mm;
404};
405
c153f45f 406extern struct drm_ioctl_desc i915_ioctls[];
b3a83639
DA		 407extern int i915_max_ioctl;
408
1da177e4 409 /* i915_dma.c */
84b1fd10 410extern void i915_kernel_lost_context(struct drm_device * dev);
22eae947 411extern int i915_driver_load(struct drm_device *, unsigned long flags);
ba8bbcf6 412extern int i915_driver_unload(struct drm_device *);
673a394b 413extern int i915_driver_open(struct drm_device *dev, struct drm_file *file_priv);
84b1fd10 414extern void i915_driver_lastclose(struct drm_device * dev);
6c340eac
EA		 415extern void i915_driver_preclose(struct drm_device *dev,
416 struct drm_file *file_priv);
673a394b
EA		 417extern void i915_driver_postclose(struct drm_device *dev,
418 struct drm_file *file_priv);
84b1fd10 419extern int i915_driver_device_is_agp(struct drm_device * dev);
0d6aa60b
DA		 420extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
421 unsigned long arg);
673a394b
EA		 422extern int i915_emit_box(struct drm_device *dev,
423 struct drm_clip_rect __user *boxes,
424 int i, int DR1, int DR4);
af6061af 425
1da177e4 426/* i915_irq.c */
c153f45f
EA		 427extern int i915_irq_emit(struct drm_device *dev, void *data,
428 struct drm_file *file_priv);
429extern int i915_irq_wait(struct drm_device *dev, void *data,
430 struct drm_file *file_priv);
673a394b
EA		 431void i915_user_irq_get(struct drm_device *dev);
432void i915_user_irq_put(struct drm_device *dev);
1da177e4
LT		 433
434extern irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS);
84b1fd10 435extern void i915_driver_irq_preinstall(struct drm_device * dev);
0a3e67a4 436extern int i915_driver_irq_postinstall(struct drm_device *dev);
84b1fd10 437extern void i915_driver_irq_uninstall(struct drm_device * dev);
c153f45f
EA		 438extern int i915_vblank_pipe_set(struct drm_device *dev, void *data,
439 struct drm_file *file_priv);
440extern int i915_vblank_pipe_get(struct drm_device *dev, void *data,
441 struct drm_file *file_priv);
0a3e67a4
JB		 442extern int i915_enable_vblank(struct drm_device *dev, int crtc);
443extern void i915_disable_vblank(struct drm_device *dev, int crtc);
444extern u32 i915_get_vblank_counter(struct drm_device *dev, int crtc);
c153f45f
EA		 445extern int i915_vblank_swap(struct drm_device *dev, void *data,
446 struct drm_file *file_priv);
8ee1c3db 447extern void i915_enable_irq(drm_i915_private_t *dev_priv, u32 mask);
1da177e4
LT		 448
449/* i915_mem.c */
c153f45f
EA		 450extern int i915_mem_alloc(struct drm_device *dev, void *data,
451 struct drm_file *file_priv);
452extern int i915_mem_free(struct drm_device *dev, void *data,
453 struct drm_file *file_priv);
454extern int i915_mem_init_heap(struct drm_device *dev, void *data,
455 struct drm_file *file_priv);
456extern int i915_mem_destroy_heap(struct drm_device *dev, void *data,
457 struct drm_file *file_priv);
1da177e4 458extern void i915_mem_takedown(struct mem_block **heap);
84b1fd10 459extern void i915_mem_release(struct drm_device * dev,
6c340eac 460 struct drm_file *file_priv, struct mem_block *heap);
673a394b
EA		 461/* i915_gem.c */
462int i915_gem_init_ioctl(struct drm_device *dev, void *data,
463 struct drm_file *file_priv);
464int i915_gem_create_ioctl(struct drm_device *dev, void *data,
465 struct drm_file *file_priv);
466int i915_gem_pread_ioctl(struct drm_device *dev, void *data,
467 struct drm_file *file_priv);
468int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
469 struct drm_file *file_priv);
470int i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
471 struct drm_file *file_priv);
472int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
473 struct drm_file *file_priv);
474int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
475 struct drm_file *file_priv);
476int i915_gem_execbuffer(struct drm_device *dev, void *data,
477 struct drm_file *file_priv);
478int i915_gem_pin_ioctl(struct drm_device *dev, void *data,
479 struct drm_file *file_priv);
480int i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
481 struct drm_file *file_priv);
482int i915_gem_busy_ioctl(struct drm_device *dev, void *data,
483 struct drm_file *file_priv);
484int i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
485 struct drm_file *file_priv);
486int i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
487 struct drm_file *file_priv);
488int i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
489 struct drm_file *file_priv);
490int i915_gem_set_tiling(struct drm_device *dev, void *data,
491 struct drm_file *file_priv);
492int i915_gem_get_tiling(struct drm_device *dev, void *data,
493 struct drm_file *file_priv);
5a125c3c
EA		 494int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
495 struct drm_file *file_priv);
673a394b
EA		 496void i915_gem_load(struct drm_device *dev);
497int i915_gem_proc_init(struct drm_minor *minor);
498void i915_gem_proc_cleanup(struct drm_minor *minor);
499int i915_gem_init_object(struct drm_gem_object *obj);
500void i915_gem_free_object(struct drm_gem_object *obj);
501int i915_gem_object_pin(struct drm_gem_object *obj, uint32_t alignment);
502void i915_gem_object_unpin(struct drm_gem_object *obj);
503void i915_gem_lastclose(struct drm_device *dev);
504uint32_t i915_get_gem_seqno(struct drm_device *dev);
505void i915_gem_retire_requests(struct drm_device *dev);
506void i915_gem_retire_work_handler(struct work_struct *work);
507void i915_gem_clflush_object(struct drm_gem_object *obj);
508
509/* i915_gem_tiling.c */
510void i915_gem_detect_bit_6_swizzle(struct drm_device *dev);
511
512/* i915_gem_debug.c */
513void i915_gem_dump_object(struct drm_gem_object *obj, int len,
514 const char *where, uint32_t mark);
515#if WATCH_INACTIVE
516void i915_verify_inactive(struct drm_device *dev, char *file, int line);
517#else
518#define i915_verify_inactive(dev, file, line)
519#endif
520void i915_gem_object_check_coherency(struct drm_gem_object *obj, int handle);
521void i915_gem_dump_object(struct drm_gem_object *obj, int len,
522 const char *where, uint32_t mark);
523void i915_dump_lru(struct drm_device *dev, const char *where);
1da177e4 524
317c35d1
JB		 525/* i915_suspend.c */
526extern int i915_save_state(struct drm_device *dev);
527extern int i915_restore_state(struct drm_device *dev);
0a3e67a4
JB		 528
529/* i915_suspend.c */
530extern int i915_save_state(struct drm_device *dev);
531extern int i915_restore_state(struct drm_device *dev);
317c35d1 532
65e082c9 533#ifdef CONFIG_ACPI
8ee1c3db
MG		 534/* i915_opregion.c */
535extern int intel_opregion_init(struct drm_device *dev);
536extern void intel_opregion_free(struct drm_device *dev);
537extern void opregion_asle_intr(struct drm_device *dev);
538extern void opregion_enable_asle(struct drm_device *dev);
65e082c9
LB		 539#else
540static inline int intel_opregion_init(struct drm_device *dev) { return 0; }
541static inline void intel_opregion_free(struct drm_device *dev) { return; }
542static inline void opregion_asle_intr(struct drm_device *dev) { return; }
543static inline void opregion_enable_asle(struct drm_device *dev) { return; }
544#endif
8ee1c3db 545
546b0974
EA		 546/**
547 * Lock test for when it's just for synchronization of ring access.
548 *
549 * In that case, we don't need to do it when GEM is initialized as nobody else
550 * has access to the ring.
551 */
552#define RING_LOCK_TEST_WITH_RETURN(dev, file_priv) do { \
553 if (((drm_i915_private_t *)dev->dev_private)->ring.ring_obj == NULL) \
554 LOCK_TEST_WITH_RETURN(dev, file_priv); \
555} while (0)
556
3043c60c
EA		 557#define I915_READ(reg) readl(dev_priv->regs + (reg))
558#define I915_WRITE(reg, val) writel(val, dev_priv->regs + (reg))
559#define I915_READ16(reg) readw(dev_priv->regs + (reg))
560#define I915_WRITE16(reg, val) writel(val, dev_priv->regs + (reg))
561#define I915_READ8(reg) readb(dev_priv->regs + (reg))
562#define I915_WRITE8(reg, val) writeb(val, dev_priv->regs + (reg))
1da177e4
LT		 563
564#define I915_VERBOSE 0
565
566#define RING_LOCALS unsigned int outring, ringmask, outcount; \
567 volatile char *virt;
568
569#define BEGIN_LP_RING(n) do { \
570 if (I915_VERBOSE) \
3e684eae
MN		 571 DRM_DEBUG("BEGIN_LP_RING(%d)\n", (n)); \
572 if (dev_priv->ring.space < (n)*4) \
bf9d8929 573 i915_wait_ring(dev, (n)*4, __func__); \
1da177e4
LT		 574 outcount = 0; \
575 outring = dev_priv->ring.tail; \
576 ringmask = dev_priv->ring.tail_mask; \
577 virt = dev_priv->ring.virtual_start; \
578} while (0)
579
580#define OUT_RING(n) do { \
581 if (I915_VERBOSE) DRM_DEBUG(" OUT_RING %x\n", (int)(n)); \
c29b669c 582 *(volatile unsigned int *)(virt + outring) = (n); \
1da177e4
LT		 583 outcount++; \
584 outring += 4; \
585 outring &= ringmask; \
586} while (0)
587
588#define ADVANCE_LP_RING() do { \
589 if (I915_VERBOSE) DRM_DEBUG("ADVANCE_LP_RING %x\n", outring); \
590 dev_priv->ring.tail = outring; \
591 dev_priv->ring.space -= outcount * 4; \
585fb111 592 I915_WRITE(PRB0_TAIL, outring); \
1da177e4
LT		 593} while(0)
594
ba8bbcf6 595/**
585fb111
JB		 596 * Reads a dword out of the status page, which is written to from the command
597 * queue by automatic updates, MI_REPORT_HEAD, MI_STORE_DATA_INDEX, or
598 * MI_STORE_DATA_IMM.
ba8bbcf6 599 *
585fb111 600 * The following dwords have a reserved meaning:
0cdad7e8
KP		 601 * 0x00: ISR copy, updated when an ISR bit not set in the HWSTAM changes.
602 * 0x04: ring 0 head pointer
603 * 0x05: ring 1 head pointer (915-class)
604 * 0x06: ring 2 head pointer (915-class)
605 * 0x10-0x1b: Context status DWords (GM45)
606 * 0x1f: Last written status offset. (GM45)
ba8bbcf6 607 *
0cdad7e8 608 * The area from dword 0x20 to 0x3ff is available for driver usage.
ba8bbcf6 609 */
585fb111
JB		 610#define READ_HWSP(dev_priv, reg) (((volatile u32*)(dev_priv->hw_status_page))[reg])
611#define READ_BREADCRUMB(dev_priv) READ_HWSP(dev_priv, 5)
0cdad7e8 612#define I915_GEM_HWS_INDEX 0x20
ba8bbcf6 613
585fb111 614extern int i915_wait_ring(struct drm_device * dev, int n, const char *caller);
ba8bbcf6
JB		 615
616#define IS_I830(dev) ((dev)->pci_device == 0x3577)
617#define IS_845G(dev) ((dev)->pci_device == 0x2562)
618#define IS_I85X(dev) ((dev)->pci_device == 0x3582)
619#define IS_I855(dev) ((dev)->pci_device == 0x3582)
620#define IS_I865G(dev) ((dev)->pci_device == 0x2572)
621
4d1f7888 622#define IS_I915G(dev) ((dev)->pci_device == 0x2582 || (dev)->pci_device == 0x258a)
ba8bbcf6
JB		 623#define IS_I915GM(dev) ((dev)->pci_device == 0x2592)
624#define IS_I945G(dev) ((dev)->pci_device == 0x2772)
3bf48468
JB		 625#define IS_I945GM(dev) ((dev)->pci_device == 0x27A2 ||\
626 (dev)->pci_device == 0x27AE)
ba8bbcf6
JB		 627#define IS_I965G(dev) ((dev)->pci_device == 0x2972 || \
628 (dev)->pci_device == 0x2982 || \
629 (dev)->pci_device == 0x2992 || \
630 (dev)->pci_device == 0x29A2 || \
631 (dev)->pci_device == 0x2A02 || \
5f5f9d4c 632 (dev)->pci_device == 0x2A12 || \
d3adbc0c
ZW		 633 (dev)->pci_device == 0x2A42 || \
634 (dev)->pci_device == 0x2E02 || \
635 (dev)->pci_device == 0x2E12 || \
636 (dev)->pci_device == 0x2E22)
ba8bbcf6
JB		 637
638#define IS_I965GM(dev) ((dev)->pci_device == 0x2A02)
639
b9bfdfe6 640#define IS_GM45(dev) ((dev)->pci_device == 0x2A42)
5f5f9d4c 641
d3adbc0c
ZW		 642#define IS_G4X(dev) ((dev)->pci_device == 0x2E02 || \
643 (dev)->pci_device == 0x2E12 || \
644 (dev)->pci_device == 0x2E22)
645
ba8bbcf6
JB		 646#define IS_G33(dev) ((dev)->pci_device == 0x29C2 || \
647 (dev)->pci_device == 0x29B2 || \
648 (dev)->pci_device == 0x29D2)
649
650#define IS_I9XX(dev) (IS_I915G(dev) || IS_I915GM(dev) || IS_I945G(dev) || \
651 IS_I945GM(dev) || IS_I965G(dev) || IS_G33(dev))
652
653#define IS_MOBILE(dev) (IS_I830(dev) || IS_I85X(dev) || IS_I915GM(dev) || \
b9bfdfe6 654 IS_I945GM(dev) || IS_I965GM(dev) || IS_GM45(dev))
ba8bbcf6 655
b9bfdfe6 656#define I915_NEED_GFX_HWS(dev) (IS_G33(dev) || IS_GM45(dev) || IS_G4X(dev))
b39d50e5 657
ba8bbcf6 658#define PRIMARY_RINGBUFFER_SIZE (128*1024)
0d6aa60b 659
1da177e4 660#endif
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