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Commit | Line | Data |
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673a394b EA |
1 | /* |
2 | * Copyright © 2008 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | * | |
26 | */ | |
27 | ||
28 | #include "drmP.h" | |
29 | #include "drm.h" | |
30 | #include "i915_drm.h" | |
31 | #include "i915_drv.h" | |
1c5d22f7 | 32 | #include "i915_trace.h" |
652c393a | 33 | #include "intel_drv.h" |
5a0e3ad6 | 34 | #include <linux/slab.h> |
673a394b | 35 | #include <linux/swap.h> |
79e53945 | 36 | #include <linux/pci.h> |
f8f235e5 | 37 | #include <linux/intel-gtt.h> |
673a394b | 38 | |
0108a3ed | 39 | static uint32_t i915_gem_get_gtt_alignment(struct drm_gem_object *obj); |
ba3d8d74 DV |
40 | |
41 | static int i915_gem_object_flush_gpu_write_domain(struct drm_gem_object *obj, | |
42 | bool pipelined); | |
e47c68e9 EA |
43 | static void i915_gem_object_flush_gtt_write_domain(struct drm_gem_object *obj); |
44 | static void i915_gem_object_flush_cpu_write_domain(struct drm_gem_object *obj); | |
e47c68e9 EA |
45 | static int i915_gem_object_set_to_cpu_domain(struct drm_gem_object *obj, |
46 | int write); | |
47 | static int i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object *obj, | |
48 | uint64_t offset, | |
49 | uint64_t size); | |
50 | static void i915_gem_object_set_to_full_cpu_read_domain(struct drm_gem_object *obj); | |
ba3d8d74 | 51 | static int i915_gem_object_wait_rendering(struct drm_gem_object *obj); |
de151cf6 JB |
52 | static int i915_gem_object_bind_to_gtt(struct drm_gem_object *obj, |
53 | unsigned alignment); | |
de151cf6 | 54 | static void i915_gem_clear_fence_reg(struct drm_gem_object *obj); |
71acb5eb DA |
55 | static int i915_gem_phys_pwrite(struct drm_device *dev, struct drm_gem_object *obj, |
56 | struct drm_i915_gem_pwrite *args, | |
57 | struct drm_file *file_priv); | |
be72615b | 58 | static void i915_gem_free_object_tail(struct drm_gem_object *obj); |
673a394b | 59 | |
31169714 CW |
60 | static LIST_HEAD(shrink_list); |
61 | static DEFINE_SPINLOCK(shrink_list_lock); | |
62 | ||
7d1c4804 CW |
63 | static inline bool |
64 | i915_gem_object_is_inactive(struct drm_i915_gem_object *obj_priv) | |
65 | { | |
66 | return obj_priv->gtt_space && | |
67 | !obj_priv->active && | |
68 | obj_priv->pin_count == 0; | |
69 | } | |
70 | ||
79e53945 JB |
71 | int i915_gem_do_init(struct drm_device *dev, unsigned long start, |
72 | unsigned long end) | |
673a394b EA |
73 | { |
74 | drm_i915_private_t *dev_priv = dev->dev_private; | |
673a394b | 75 | |
79e53945 JB |
76 | if (start >= end || |
77 | (start & (PAGE_SIZE - 1)) != 0 || | |
78 | (end & (PAGE_SIZE - 1)) != 0) { | |
673a394b EA |
79 | return -EINVAL; |
80 | } | |
81 | ||
79e53945 JB |
82 | drm_mm_init(&dev_priv->mm.gtt_space, start, |
83 | end - start); | |
673a394b | 84 | |
79e53945 JB |
85 | dev->gtt_total = (uint32_t) (end - start); |
86 | ||
87 | return 0; | |
88 | } | |
673a394b | 89 | |
79e53945 JB |
90 | int |
91 | i915_gem_init_ioctl(struct drm_device *dev, void *data, | |
92 | struct drm_file *file_priv) | |
93 | { | |
94 | struct drm_i915_gem_init *args = data; | |
95 | int ret; | |
96 | ||
97 | mutex_lock(&dev->struct_mutex); | |
98 | ret = i915_gem_do_init(dev, args->gtt_start, args->gtt_end); | |
673a394b EA |
99 | mutex_unlock(&dev->struct_mutex); |
100 | ||
79e53945 | 101 | return ret; |
673a394b EA |
102 | } |
103 | ||
5a125c3c EA |
104 | int |
105 | i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data, | |
106 | struct drm_file *file_priv) | |
107 | { | |
5a125c3c | 108 | struct drm_i915_gem_get_aperture *args = data; |
5a125c3c EA |
109 | |
110 | if (!(dev->driver->driver_features & DRIVER_GEM)) | |
111 | return -ENODEV; | |
112 | ||
113 | args->aper_size = dev->gtt_total; | |
2678d9d6 KP |
114 | args->aper_available_size = (args->aper_size - |
115 | atomic_read(&dev->pin_memory)); | |
5a125c3c EA |
116 | |
117 | return 0; | |
118 | } | |
119 | ||
673a394b EA |
120 | |
121 | /** | |
122 | * Creates a new mm object and returns a handle to it. | |
123 | */ | |
124 | int | |
125 | i915_gem_create_ioctl(struct drm_device *dev, void *data, | |
126 | struct drm_file *file_priv) | |
127 | { | |
128 | struct drm_i915_gem_create *args = data; | |
129 | struct drm_gem_object *obj; | |
a1a2d1d3 PP |
130 | int ret; |
131 | u32 handle; | |
673a394b EA |
132 | |
133 | args->size = roundup(args->size, PAGE_SIZE); | |
134 | ||
135 | /* Allocate the new object */ | |
ac52bc56 | 136 | obj = i915_gem_alloc_object(dev, args->size); |
673a394b EA |
137 | if (obj == NULL) |
138 | return -ENOMEM; | |
139 | ||
140 | ret = drm_gem_handle_create(file_priv, obj, &handle); | |
1dfd9754 CW |
141 | if (ret) { |
142 | drm_gem_object_unreference_unlocked(obj); | |
673a394b | 143 | return ret; |
1dfd9754 | 144 | } |
673a394b | 145 | |
1dfd9754 CW |
146 | /* Sink the floating reference from kref_init(handlecount) */ |
147 | drm_gem_object_handle_unreference_unlocked(obj); | |
673a394b | 148 | |
1dfd9754 | 149 | args->handle = handle; |
673a394b EA |
150 | return 0; |
151 | } | |
152 | ||
eb01459f EA |
153 | static inline int |
154 | fast_shmem_read(struct page **pages, | |
155 | loff_t page_base, int page_offset, | |
156 | char __user *data, | |
157 | int length) | |
158 | { | |
159 | char __iomem *vaddr; | |
2bc43b5c | 160 | int unwritten; |
eb01459f EA |
161 | |
162 | vaddr = kmap_atomic(pages[page_base >> PAGE_SHIFT], KM_USER0); | |
163 | if (vaddr == NULL) | |
164 | return -ENOMEM; | |
2bc43b5c | 165 | unwritten = __copy_to_user_inatomic(data, vaddr + page_offset, length); |
eb01459f EA |
166 | kunmap_atomic(vaddr, KM_USER0); |
167 | ||
2bc43b5c FM |
168 | if (unwritten) |
169 | return -EFAULT; | |
170 | ||
171 | return 0; | |
eb01459f EA |
172 | } |
173 | ||
280b713b EA |
174 | static int i915_gem_object_needs_bit17_swizzle(struct drm_gem_object *obj) |
175 | { | |
176 | drm_i915_private_t *dev_priv = obj->dev->dev_private; | |
23010e43 | 177 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
280b713b EA |
178 | |
179 | return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 && | |
180 | obj_priv->tiling_mode != I915_TILING_NONE; | |
181 | } | |
182 | ||
99a03df5 | 183 | static inline void |
40123c1f EA |
184 | slow_shmem_copy(struct page *dst_page, |
185 | int dst_offset, | |
186 | struct page *src_page, | |
187 | int src_offset, | |
188 | int length) | |
189 | { | |
190 | char *dst_vaddr, *src_vaddr; | |
191 | ||
99a03df5 CW |
192 | dst_vaddr = kmap(dst_page); |
193 | src_vaddr = kmap(src_page); | |
40123c1f EA |
194 | |
195 | memcpy(dst_vaddr + dst_offset, src_vaddr + src_offset, length); | |
196 | ||
99a03df5 CW |
197 | kunmap(src_page); |
198 | kunmap(dst_page); | |
40123c1f EA |
199 | } |
200 | ||
99a03df5 | 201 | static inline void |
280b713b EA |
202 | slow_shmem_bit17_copy(struct page *gpu_page, |
203 | int gpu_offset, | |
204 | struct page *cpu_page, | |
205 | int cpu_offset, | |
206 | int length, | |
207 | int is_read) | |
208 | { | |
209 | char *gpu_vaddr, *cpu_vaddr; | |
210 | ||
211 | /* Use the unswizzled path if this page isn't affected. */ | |
212 | if ((page_to_phys(gpu_page) & (1 << 17)) == 0) { | |
213 | if (is_read) | |
214 | return slow_shmem_copy(cpu_page, cpu_offset, | |
215 | gpu_page, gpu_offset, length); | |
216 | else | |
217 | return slow_shmem_copy(gpu_page, gpu_offset, | |
218 | cpu_page, cpu_offset, length); | |
219 | } | |
220 | ||
99a03df5 CW |
221 | gpu_vaddr = kmap(gpu_page); |
222 | cpu_vaddr = kmap(cpu_page); | |
280b713b EA |
223 | |
224 | /* Copy the data, XORing A6 with A17 (1). The user already knows he's | |
225 | * XORing with the other bits (A9 for Y, A9 and A10 for X) | |
226 | */ | |
227 | while (length > 0) { | |
228 | int cacheline_end = ALIGN(gpu_offset + 1, 64); | |
229 | int this_length = min(cacheline_end - gpu_offset, length); | |
230 | int swizzled_gpu_offset = gpu_offset ^ 64; | |
231 | ||
232 | if (is_read) { | |
233 | memcpy(cpu_vaddr + cpu_offset, | |
234 | gpu_vaddr + swizzled_gpu_offset, | |
235 | this_length); | |
236 | } else { | |
237 | memcpy(gpu_vaddr + swizzled_gpu_offset, | |
238 | cpu_vaddr + cpu_offset, | |
239 | this_length); | |
240 | } | |
241 | cpu_offset += this_length; | |
242 | gpu_offset += this_length; | |
243 | length -= this_length; | |
244 | } | |
245 | ||
99a03df5 CW |
246 | kunmap(cpu_page); |
247 | kunmap(gpu_page); | |
280b713b EA |
248 | } |
249 | ||
eb01459f EA |
250 | /** |
251 | * This is the fast shmem pread path, which attempts to copy_from_user directly | |
252 | * from the backing pages of the object to the user's address space. On a | |
253 | * fault, it fails so we can fall back to i915_gem_shmem_pwrite_slow(). | |
254 | */ | |
255 | static int | |
256 | i915_gem_shmem_pread_fast(struct drm_device *dev, struct drm_gem_object *obj, | |
257 | struct drm_i915_gem_pread *args, | |
258 | struct drm_file *file_priv) | |
259 | { | |
23010e43 | 260 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
eb01459f EA |
261 | ssize_t remain; |
262 | loff_t offset, page_base; | |
263 | char __user *user_data; | |
264 | int page_offset, page_length; | |
265 | int ret; | |
266 | ||
267 | user_data = (char __user *) (uintptr_t) args->data_ptr; | |
268 | remain = args->size; | |
269 | ||
270 | mutex_lock(&dev->struct_mutex); | |
271 | ||
4bdadb97 | 272 | ret = i915_gem_object_get_pages(obj, 0); |
eb01459f EA |
273 | if (ret != 0) |
274 | goto fail_unlock; | |
275 | ||
276 | ret = i915_gem_object_set_cpu_read_domain_range(obj, args->offset, | |
277 | args->size); | |
278 | if (ret != 0) | |
279 | goto fail_put_pages; | |
280 | ||
23010e43 | 281 | obj_priv = to_intel_bo(obj); |
eb01459f EA |
282 | offset = args->offset; |
283 | ||
284 | while (remain > 0) { | |
285 | /* Operation in this page | |
286 | * | |
287 | * page_base = page offset within aperture | |
288 | * page_offset = offset within page | |
289 | * page_length = bytes to copy for this page | |
290 | */ | |
291 | page_base = (offset & ~(PAGE_SIZE-1)); | |
292 | page_offset = offset & (PAGE_SIZE-1); | |
293 | page_length = remain; | |
294 | if ((page_offset + remain) > PAGE_SIZE) | |
295 | page_length = PAGE_SIZE - page_offset; | |
296 | ||
297 | ret = fast_shmem_read(obj_priv->pages, | |
298 | page_base, page_offset, | |
299 | user_data, page_length); | |
300 | if (ret) | |
301 | goto fail_put_pages; | |
302 | ||
303 | remain -= page_length; | |
304 | user_data += page_length; | |
305 | offset += page_length; | |
306 | } | |
307 | ||
308 | fail_put_pages: | |
309 | i915_gem_object_put_pages(obj); | |
310 | fail_unlock: | |
311 | mutex_unlock(&dev->struct_mutex); | |
312 | ||
313 | return ret; | |
314 | } | |
315 | ||
07f73f69 CW |
316 | static int |
317 | i915_gem_object_get_pages_or_evict(struct drm_gem_object *obj) | |
318 | { | |
319 | int ret; | |
320 | ||
4bdadb97 | 321 | ret = i915_gem_object_get_pages(obj, __GFP_NORETRY | __GFP_NOWARN); |
07f73f69 CW |
322 | |
323 | /* If we've insufficient memory to map in the pages, attempt | |
324 | * to make some space by throwing out some old buffers. | |
325 | */ | |
326 | if (ret == -ENOMEM) { | |
327 | struct drm_device *dev = obj->dev; | |
07f73f69 | 328 | |
0108a3ed DV |
329 | ret = i915_gem_evict_something(dev, obj->size, |
330 | i915_gem_get_gtt_alignment(obj)); | |
07f73f69 CW |
331 | if (ret) |
332 | return ret; | |
333 | ||
4bdadb97 | 334 | ret = i915_gem_object_get_pages(obj, 0); |
07f73f69 CW |
335 | } |
336 | ||
337 | return ret; | |
338 | } | |
339 | ||
eb01459f EA |
340 | /** |
341 | * This is the fallback shmem pread path, which allocates temporary storage | |
342 | * in kernel space to copy_to_user into outside of the struct_mutex, so we | |
343 | * can copy out of the object's backing pages while holding the struct mutex | |
344 | * and not take page faults. | |
345 | */ | |
346 | static int | |
347 | i915_gem_shmem_pread_slow(struct drm_device *dev, struct drm_gem_object *obj, | |
348 | struct drm_i915_gem_pread *args, | |
349 | struct drm_file *file_priv) | |
350 | { | |
23010e43 | 351 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
eb01459f EA |
352 | struct mm_struct *mm = current->mm; |
353 | struct page **user_pages; | |
354 | ssize_t remain; | |
355 | loff_t offset, pinned_pages, i; | |
356 | loff_t first_data_page, last_data_page, num_pages; | |
357 | int shmem_page_index, shmem_page_offset; | |
358 | int data_page_index, data_page_offset; | |
359 | int page_length; | |
360 | int ret; | |
361 | uint64_t data_ptr = args->data_ptr; | |
280b713b | 362 | int do_bit17_swizzling; |
eb01459f EA |
363 | |
364 | remain = args->size; | |
365 | ||
366 | /* Pin the user pages containing the data. We can't fault while | |
367 | * holding the struct mutex, yet we want to hold it while | |
368 | * dereferencing the user data. | |
369 | */ | |
370 | first_data_page = data_ptr / PAGE_SIZE; | |
371 | last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE; | |
372 | num_pages = last_data_page - first_data_page + 1; | |
373 | ||
8e7d2b2c | 374 | user_pages = drm_calloc_large(num_pages, sizeof(struct page *)); |
eb01459f EA |
375 | if (user_pages == NULL) |
376 | return -ENOMEM; | |
377 | ||
378 | down_read(&mm->mmap_sem); | |
379 | pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr, | |
e5e9ecde | 380 | num_pages, 1, 0, user_pages, NULL); |
eb01459f EA |
381 | up_read(&mm->mmap_sem); |
382 | if (pinned_pages < num_pages) { | |
383 | ret = -EFAULT; | |
384 | goto fail_put_user_pages; | |
385 | } | |
386 | ||
280b713b EA |
387 | do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj); |
388 | ||
eb01459f EA |
389 | mutex_lock(&dev->struct_mutex); |
390 | ||
07f73f69 CW |
391 | ret = i915_gem_object_get_pages_or_evict(obj); |
392 | if (ret) | |
eb01459f EA |
393 | goto fail_unlock; |
394 | ||
395 | ret = i915_gem_object_set_cpu_read_domain_range(obj, args->offset, | |
396 | args->size); | |
397 | if (ret != 0) | |
398 | goto fail_put_pages; | |
399 | ||
23010e43 | 400 | obj_priv = to_intel_bo(obj); |
eb01459f EA |
401 | offset = args->offset; |
402 | ||
403 | while (remain > 0) { | |
404 | /* Operation in this page | |
405 | * | |
406 | * shmem_page_index = page number within shmem file | |
407 | * shmem_page_offset = offset within page in shmem file | |
408 | * data_page_index = page number in get_user_pages return | |
409 | * data_page_offset = offset with data_page_index page. | |
410 | * page_length = bytes to copy for this page | |
411 | */ | |
412 | shmem_page_index = offset / PAGE_SIZE; | |
413 | shmem_page_offset = offset & ~PAGE_MASK; | |
414 | data_page_index = data_ptr / PAGE_SIZE - first_data_page; | |
415 | data_page_offset = data_ptr & ~PAGE_MASK; | |
416 | ||
417 | page_length = remain; | |
418 | if ((shmem_page_offset + page_length) > PAGE_SIZE) | |
419 | page_length = PAGE_SIZE - shmem_page_offset; | |
420 | if ((data_page_offset + page_length) > PAGE_SIZE) | |
421 | page_length = PAGE_SIZE - data_page_offset; | |
422 | ||
280b713b | 423 | if (do_bit17_swizzling) { |
99a03df5 | 424 | slow_shmem_bit17_copy(obj_priv->pages[shmem_page_index], |
280b713b | 425 | shmem_page_offset, |
99a03df5 CW |
426 | user_pages[data_page_index], |
427 | data_page_offset, | |
428 | page_length, | |
429 | 1); | |
430 | } else { | |
431 | slow_shmem_copy(user_pages[data_page_index], | |
432 | data_page_offset, | |
433 | obj_priv->pages[shmem_page_index], | |
434 | shmem_page_offset, | |
435 | page_length); | |
280b713b | 436 | } |
eb01459f EA |
437 | |
438 | remain -= page_length; | |
439 | data_ptr += page_length; | |
440 | offset += page_length; | |
441 | } | |
442 | ||
443 | fail_put_pages: | |
444 | i915_gem_object_put_pages(obj); | |
445 | fail_unlock: | |
446 | mutex_unlock(&dev->struct_mutex); | |
447 | fail_put_user_pages: | |
448 | for (i = 0; i < pinned_pages; i++) { | |
449 | SetPageDirty(user_pages[i]); | |
450 | page_cache_release(user_pages[i]); | |
451 | } | |
8e7d2b2c | 452 | drm_free_large(user_pages); |
eb01459f EA |
453 | |
454 | return ret; | |
455 | } | |
456 | ||
673a394b EA |
457 | /** |
458 | * Reads data from the object referenced by handle. | |
459 | * | |
460 | * On error, the contents of *data are undefined. | |
461 | */ | |
462 | int | |
463 | i915_gem_pread_ioctl(struct drm_device *dev, void *data, | |
464 | struct drm_file *file_priv) | |
465 | { | |
466 | struct drm_i915_gem_pread *args = data; | |
467 | struct drm_gem_object *obj; | |
468 | struct drm_i915_gem_object *obj_priv; | |
673a394b EA |
469 | int ret; |
470 | ||
471 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); | |
472 | if (obj == NULL) | |
bf79cb91 | 473 | return -ENOENT; |
23010e43 | 474 | obj_priv = to_intel_bo(obj); |
673a394b EA |
475 | |
476 | /* Bounds check source. | |
477 | * | |
478 | * XXX: This could use review for overflow issues... | |
479 | */ | |
480 | if (args->offset > obj->size || args->size > obj->size || | |
481 | args->offset + args->size > obj->size) { | |
bc9025bd | 482 | drm_gem_object_unreference_unlocked(obj); |
673a394b EA |
483 | return -EINVAL; |
484 | } | |
485 | ||
280b713b | 486 | if (i915_gem_object_needs_bit17_swizzle(obj)) { |
eb01459f | 487 | ret = i915_gem_shmem_pread_slow(dev, obj, args, file_priv); |
280b713b EA |
488 | } else { |
489 | ret = i915_gem_shmem_pread_fast(dev, obj, args, file_priv); | |
490 | if (ret != 0) | |
491 | ret = i915_gem_shmem_pread_slow(dev, obj, args, | |
492 | file_priv); | |
493 | } | |
673a394b | 494 | |
bc9025bd | 495 | drm_gem_object_unreference_unlocked(obj); |
673a394b | 496 | |
eb01459f | 497 | return ret; |
673a394b EA |
498 | } |
499 | ||
0839ccb8 KP |
500 | /* This is the fast write path which cannot handle |
501 | * page faults in the source data | |
9b7530cc | 502 | */ |
0839ccb8 KP |
503 | |
504 | static inline int | |
505 | fast_user_write(struct io_mapping *mapping, | |
506 | loff_t page_base, int page_offset, | |
507 | char __user *user_data, | |
508 | int length) | |
9b7530cc | 509 | { |
9b7530cc | 510 | char *vaddr_atomic; |
0839ccb8 | 511 | unsigned long unwritten; |
9b7530cc | 512 | |
fca3ec01 | 513 | vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base, KM_USER0); |
0839ccb8 KP |
514 | unwritten = __copy_from_user_inatomic_nocache(vaddr_atomic + page_offset, |
515 | user_data, length); | |
fca3ec01 | 516 | io_mapping_unmap_atomic(vaddr_atomic, KM_USER0); |
0839ccb8 KP |
517 | if (unwritten) |
518 | return -EFAULT; | |
519 | return 0; | |
520 | } | |
521 | ||
522 | /* Here's the write path which can sleep for | |
523 | * page faults | |
524 | */ | |
525 | ||
ab34c226 | 526 | static inline void |
3de09aa3 EA |
527 | slow_kernel_write(struct io_mapping *mapping, |
528 | loff_t gtt_base, int gtt_offset, | |
529 | struct page *user_page, int user_offset, | |
530 | int length) | |
0839ccb8 | 531 | { |
ab34c226 CW |
532 | char __iomem *dst_vaddr; |
533 | char *src_vaddr; | |
0839ccb8 | 534 | |
ab34c226 CW |
535 | dst_vaddr = io_mapping_map_wc(mapping, gtt_base); |
536 | src_vaddr = kmap(user_page); | |
537 | ||
538 | memcpy_toio(dst_vaddr + gtt_offset, | |
539 | src_vaddr + user_offset, | |
540 | length); | |
541 | ||
542 | kunmap(user_page); | |
543 | io_mapping_unmap(dst_vaddr); | |
9b7530cc LT |
544 | } |
545 | ||
40123c1f EA |
546 | static inline int |
547 | fast_shmem_write(struct page **pages, | |
548 | loff_t page_base, int page_offset, | |
549 | char __user *data, | |
550 | int length) | |
551 | { | |
552 | char __iomem *vaddr; | |
d0088775 | 553 | unsigned long unwritten; |
40123c1f EA |
554 | |
555 | vaddr = kmap_atomic(pages[page_base >> PAGE_SHIFT], KM_USER0); | |
556 | if (vaddr == NULL) | |
557 | return -ENOMEM; | |
d0088775 | 558 | unwritten = __copy_from_user_inatomic(vaddr + page_offset, data, length); |
40123c1f EA |
559 | kunmap_atomic(vaddr, KM_USER0); |
560 | ||
d0088775 DA |
561 | if (unwritten) |
562 | return -EFAULT; | |
40123c1f EA |
563 | return 0; |
564 | } | |
565 | ||
3de09aa3 EA |
566 | /** |
567 | * This is the fast pwrite path, where we copy the data directly from the | |
568 | * user into the GTT, uncached. | |
569 | */ | |
673a394b | 570 | static int |
3de09aa3 EA |
571 | i915_gem_gtt_pwrite_fast(struct drm_device *dev, struct drm_gem_object *obj, |
572 | struct drm_i915_gem_pwrite *args, | |
573 | struct drm_file *file_priv) | |
673a394b | 574 | { |
23010e43 | 575 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
0839ccb8 | 576 | drm_i915_private_t *dev_priv = dev->dev_private; |
673a394b | 577 | ssize_t remain; |
0839ccb8 | 578 | loff_t offset, page_base; |
673a394b | 579 | char __user *user_data; |
0839ccb8 KP |
580 | int page_offset, page_length; |
581 | int ret; | |
673a394b EA |
582 | |
583 | user_data = (char __user *) (uintptr_t) args->data_ptr; | |
584 | remain = args->size; | |
585 | if (!access_ok(VERIFY_READ, user_data, remain)) | |
586 | return -EFAULT; | |
587 | ||
588 | ||
589 | mutex_lock(&dev->struct_mutex); | |
590 | ret = i915_gem_object_pin(obj, 0); | |
591 | if (ret) { | |
592 | mutex_unlock(&dev->struct_mutex); | |
593 | return ret; | |
594 | } | |
2ef7eeaa | 595 | ret = i915_gem_object_set_to_gtt_domain(obj, 1); |
673a394b EA |
596 | if (ret) |
597 | goto fail; | |
598 | ||
23010e43 | 599 | obj_priv = to_intel_bo(obj); |
673a394b | 600 | offset = obj_priv->gtt_offset + args->offset; |
673a394b EA |
601 | |
602 | while (remain > 0) { | |
603 | /* Operation in this page | |
604 | * | |
0839ccb8 KP |
605 | * page_base = page offset within aperture |
606 | * page_offset = offset within page | |
607 | * page_length = bytes to copy for this page | |
673a394b | 608 | */ |
0839ccb8 KP |
609 | page_base = (offset & ~(PAGE_SIZE-1)); |
610 | page_offset = offset & (PAGE_SIZE-1); | |
611 | page_length = remain; | |
612 | if ((page_offset + remain) > PAGE_SIZE) | |
613 | page_length = PAGE_SIZE - page_offset; | |
614 | ||
615 | ret = fast_user_write (dev_priv->mm.gtt_mapping, page_base, | |
616 | page_offset, user_data, page_length); | |
617 | ||
618 | /* If we get a fault while copying data, then (presumably) our | |
3de09aa3 EA |
619 | * source page isn't available. Return the error and we'll |
620 | * retry in the slow path. | |
0839ccb8 | 621 | */ |
3de09aa3 EA |
622 | if (ret) |
623 | goto fail; | |
673a394b | 624 | |
0839ccb8 KP |
625 | remain -= page_length; |
626 | user_data += page_length; | |
627 | offset += page_length; | |
673a394b | 628 | } |
673a394b EA |
629 | |
630 | fail: | |
631 | i915_gem_object_unpin(obj); | |
632 | mutex_unlock(&dev->struct_mutex); | |
633 | ||
634 | return ret; | |
635 | } | |
636 | ||
3de09aa3 EA |
637 | /** |
638 | * This is the fallback GTT pwrite path, which uses get_user_pages to pin | |
639 | * the memory and maps it using kmap_atomic for copying. | |
640 | * | |
641 | * This code resulted in x11perf -rgb10text consuming about 10% more CPU | |
642 | * than using i915_gem_gtt_pwrite_fast on a G45 (32-bit). | |
643 | */ | |
3043c60c | 644 | static int |
3de09aa3 EA |
645 | i915_gem_gtt_pwrite_slow(struct drm_device *dev, struct drm_gem_object *obj, |
646 | struct drm_i915_gem_pwrite *args, | |
647 | struct drm_file *file_priv) | |
673a394b | 648 | { |
23010e43 | 649 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
3de09aa3 EA |
650 | drm_i915_private_t *dev_priv = dev->dev_private; |
651 | ssize_t remain; | |
652 | loff_t gtt_page_base, offset; | |
653 | loff_t first_data_page, last_data_page, num_pages; | |
654 | loff_t pinned_pages, i; | |
655 | struct page **user_pages; | |
656 | struct mm_struct *mm = current->mm; | |
657 | int gtt_page_offset, data_page_offset, data_page_index, page_length; | |
673a394b | 658 | int ret; |
3de09aa3 EA |
659 | uint64_t data_ptr = args->data_ptr; |
660 | ||
661 | remain = args->size; | |
662 | ||
663 | /* Pin the user pages containing the data. We can't fault while | |
664 | * holding the struct mutex, and all of the pwrite implementations | |
665 | * want to hold it while dereferencing the user data. | |
666 | */ | |
667 | first_data_page = data_ptr / PAGE_SIZE; | |
668 | last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE; | |
669 | num_pages = last_data_page - first_data_page + 1; | |
670 | ||
8e7d2b2c | 671 | user_pages = drm_calloc_large(num_pages, sizeof(struct page *)); |
3de09aa3 EA |
672 | if (user_pages == NULL) |
673 | return -ENOMEM; | |
674 | ||
675 | down_read(&mm->mmap_sem); | |
676 | pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr, | |
677 | num_pages, 0, 0, user_pages, NULL); | |
678 | up_read(&mm->mmap_sem); | |
679 | if (pinned_pages < num_pages) { | |
680 | ret = -EFAULT; | |
681 | goto out_unpin_pages; | |
682 | } | |
673a394b EA |
683 | |
684 | mutex_lock(&dev->struct_mutex); | |
3de09aa3 EA |
685 | ret = i915_gem_object_pin(obj, 0); |
686 | if (ret) | |
687 | goto out_unlock; | |
688 | ||
689 | ret = i915_gem_object_set_to_gtt_domain(obj, 1); | |
690 | if (ret) | |
691 | goto out_unpin_object; | |
692 | ||
23010e43 | 693 | obj_priv = to_intel_bo(obj); |
3de09aa3 EA |
694 | offset = obj_priv->gtt_offset + args->offset; |
695 | ||
696 | while (remain > 0) { | |
697 | /* Operation in this page | |
698 | * | |
699 | * gtt_page_base = page offset within aperture | |
700 | * gtt_page_offset = offset within page in aperture | |
701 | * data_page_index = page number in get_user_pages return | |
702 | * data_page_offset = offset with data_page_index page. | |
703 | * page_length = bytes to copy for this page | |
704 | */ | |
705 | gtt_page_base = offset & PAGE_MASK; | |
706 | gtt_page_offset = offset & ~PAGE_MASK; | |
707 | data_page_index = data_ptr / PAGE_SIZE - first_data_page; | |
708 | data_page_offset = data_ptr & ~PAGE_MASK; | |
709 | ||
710 | page_length = remain; | |
711 | if ((gtt_page_offset + page_length) > PAGE_SIZE) | |
712 | page_length = PAGE_SIZE - gtt_page_offset; | |
713 | if ((data_page_offset + page_length) > PAGE_SIZE) | |
714 | page_length = PAGE_SIZE - data_page_offset; | |
715 | ||
ab34c226 CW |
716 | slow_kernel_write(dev_priv->mm.gtt_mapping, |
717 | gtt_page_base, gtt_page_offset, | |
718 | user_pages[data_page_index], | |
719 | data_page_offset, | |
720 | page_length); | |
3de09aa3 EA |
721 | |
722 | remain -= page_length; | |
723 | offset += page_length; | |
724 | data_ptr += page_length; | |
725 | } | |
726 | ||
727 | out_unpin_object: | |
728 | i915_gem_object_unpin(obj); | |
729 | out_unlock: | |
730 | mutex_unlock(&dev->struct_mutex); | |
731 | out_unpin_pages: | |
732 | for (i = 0; i < pinned_pages; i++) | |
733 | page_cache_release(user_pages[i]); | |
8e7d2b2c | 734 | drm_free_large(user_pages); |
3de09aa3 EA |
735 | |
736 | return ret; | |
737 | } | |
738 | ||
40123c1f EA |
739 | /** |
740 | * This is the fast shmem pwrite path, which attempts to directly | |
741 | * copy_from_user into the kmapped pages backing the object. | |
742 | */ | |
3043c60c | 743 | static int |
40123c1f EA |
744 | i915_gem_shmem_pwrite_fast(struct drm_device *dev, struct drm_gem_object *obj, |
745 | struct drm_i915_gem_pwrite *args, | |
746 | struct drm_file *file_priv) | |
673a394b | 747 | { |
23010e43 | 748 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
40123c1f EA |
749 | ssize_t remain; |
750 | loff_t offset, page_base; | |
751 | char __user *user_data; | |
752 | int page_offset, page_length; | |
673a394b | 753 | int ret; |
40123c1f EA |
754 | |
755 | user_data = (char __user *) (uintptr_t) args->data_ptr; | |
756 | remain = args->size; | |
673a394b EA |
757 | |
758 | mutex_lock(&dev->struct_mutex); | |
759 | ||
4bdadb97 | 760 | ret = i915_gem_object_get_pages(obj, 0); |
40123c1f EA |
761 | if (ret != 0) |
762 | goto fail_unlock; | |
673a394b | 763 | |
e47c68e9 | 764 | ret = i915_gem_object_set_to_cpu_domain(obj, 1); |
40123c1f EA |
765 | if (ret != 0) |
766 | goto fail_put_pages; | |
767 | ||
23010e43 | 768 | obj_priv = to_intel_bo(obj); |
40123c1f EA |
769 | offset = args->offset; |
770 | obj_priv->dirty = 1; | |
771 | ||
772 | while (remain > 0) { | |
773 | /* Operation in this page | |
774 | * | |
775 | * page_base = page offset within aperture | |
776 | * page_offset = offset within page | |
777 | * page_length = bytes to copy for this page | |
778 | */ | |
779 | page_base = (offset & ~(PAGE_SIZE-1)); | |
780 | page_offset = offset & (PAGE_SIZE-1); | |
781 | page_length = remain; | |
782 | if ((page_offset + remain) > PAGE_SIZE) | |
783 | page_length = PAGE_SIZE - page_offset; | |
784 | ||
785 | ret = fast_shmem_write(obj_priv->pages, | |
786 | page_base, page_offset, | |
787 | user_data, page_length); | |
788 | if (ret) | |
789 | goto fail_put_pages; | |
790 | ||
791 | remain -= page_length; | |
792 | user_data += page_length; | |
793 | offset += page_length; | |
794 | } | |
795 | ||
796 | fail_put_pages: | |
797 | i915_gem_object_put_pages(obj); | |
798 | fail_unlock: | |
799 | mutex_unlock(&dev->struct_mutex); | |
800 | ||
801 | return ret; | |
802 | } | |
803 | ||
804 | /** | |
805 | * This is the fallback shmem pwrite path, which uses get_user_pages to pin | |
806 | * the memory and maps it using kmap_atomic for copying. | |
807 | * | |
808 | * This avoids taking mmap_sem for faulting on the user's address while the | |
809 | * struct_mutex is held. | |
810 | */ | |
811 | static int | |
812 | i915_gem_shmem_pwrite_slow(struct drm_device *dev, struct drm_gem_object *obj, | |
813 | struct drm_i915_gem_pwrite *args, | |
814 | struct drm_file *file_priv) | |
815 | { | |
23010e43 | 816 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
40123c1f EA |
817 | struct mm_struct *mm = current->mm; |
818 | struct page **user_pages; | |
819 | ssize_t remain; | |
820 | loff_t offset, pinned_pages, i; | |
821 | loff_t first_data_page, last_data_page, num_pages; | |
822 | int shmem_page_index, shmem_page_offset; | |
823 | int data_page_index, data_page_offset; | |
824 | int page_length; | |
825 | int ret; | |
826 | uint64_t data_ptr = args->data_ptr; | |
280b713b | 827 | int do_bit17_swizzling; |
40123c1f EA |
828 | |
829 | remain = args->size; | |
830 | ||
831 | /* Pin the user pages containing the data. We can't fault while | |
832 | * holding the struct mutex, and all of the pwrite implementations | |
833 | * want to hold it while dereferencing the user data. | |
834 | */ | |
835 | first_data_page = data_ptr / PAGE_SIZE; | |
836 | last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE; | |
837 | num_pages = last_data_page - first_data_page + 1; | |
838 | ||
8e7d2b2c | 839 | user_pages = drm_calloc_large(num_pages, sizeof(struct page *)); |
40123c1f EA |
840 | if (user_pages == NULL) |
841 | return -ENOMEM; | |
842 | ||
843 | down_read(&mm->mmap_sem); | |
844 | pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr, | |
845 | num_pages, 0, 0, user_pages, NULL); | |
846 | up_read(&mm->mmap_sem); | |
847 | if (pinned_pages < num_pages) { | |
848 | ret = -EFAULT; | |
849 | goto fail_put_user_pages; | |
673a394b EA |
850 | } |
851 | ||
280b713b EA |
852 | do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj); |
853 | ||
40123c1f EA |
854 | mutex_lock(&dev->struct_mutex); |
855 | ||
07f73f69 CW |
856 | ret = i915_gem_object_get_pages_or_evict(obj); |
857 | if (ret) | |
40123c1f EA |
858 | goto fail_unlock; |
859 | ||
860 | ret = i915_gem_object_set_to_cpu_domain(obj, 1); | |
861 | if (ret != 0) | |
862 | goto fail_put_pages; | |
863 | ||
23010e43 | 864 | obj_priv = to_intel_bo(obj); |
673a394b | 865 | offset = args->offset; |
40123c1f | 866 | obj_priv->dirty = 1; |
673a394b | 867 | |
40123c1f EA |
868 | while (remain > 0) { |
869 | /* Operation in this page | |
870 | * | |
871 | * shmem_page_index = page number within shmem file | |
872 | * shmem_page_offset = offset within page in shmem file | |
873 | * data_page_index = page number in get_user_pages return | |
874 | * data_page_offset = offset with data_page_index page. | |
875 | * page_length = bytes to copy for this page | |
876 | */ | |
877 | shmem_page_index = offset / PAGE_SIZE; | |
878 | shmem_page_offset = offset & ~PAGE_MASK; | |
879 | data_page_index = data_ptr / PAGE_SIZE - first_data_page; | |
880 | data_page_offset = data_ptr & ~PAGE_MASK; | |
881 | ||
882 | page_length = remain; | |
883 | if ((shmem_page_offset + page_length) > PAGE_SIZE) | |
884 | page_length = PAGE_SIZE - shmem_page_offset; | |
885 | if ((data_page_offset + page_length) > PAGE_SIZE) | |
886 | page_length = PAGE_SIZE - data_page_offset; | |
887 | ||
280b713b | 888 | if (do_bit17_swizzling) { |
99a03df5 | 889 | slow_shmem_bit17_copy(obj_priv->pages[shmem_page_index], |
280b713b EA |
890 | shmem_page_offset, |
891 | user_pages[data_page_index], | |
892 | data_page_offset, | |
99a03df5 CW |
893 | page_length, |
894 | 0); | |
895 | } else { | |
896 | slow_shmem_copy(obj_priv->pages[shmem_page_index], | |
897 | shmem_page_offset, | |
898 | user_pages[data_page_index], | |
899 | data_page_offset, | |
900 | page_length); | |
280b713b | 901 | } |
40123c1f EA |
902 | |
903 | remain -= page_length; | |
904 | data_ptr += page_length; | |
905 | offset += page_length; | |
673a394b EA |
906 | } |
907 | ||
40123c1f EA |
908 | fail_put_pages: |
909 | i915_gem_object_put_pages(obj); | |
910 | fail_unlock: | |
673a394b | 911 | mutex_unlock(&dev->struct_mutex); |
40123c1f EA |
912 | fail_put_user_pages: |
913 | for (i = 0; i < pinned_pages; i++) | |
914 | page_cache_release(user_pages[i]); | |
8e7d2b2c | 915 | drm_free_large(user_pages); |
673a394b | 916 | |
40123c1f | 917 | return ret; |
673a394b EA |
918 | } |
919 | ||
920 | /** | |
921 | * Writes data to the object referenced by handle. | |
922 | * | |
923 | * On error, the contents of the buffer that were to be modified are undefined. | |
924 | */ | |
925 | int | |
926 | i915_gem_pwrite_ioctl(struct drm_device *dev, void *data, | |
927 | struct drm_file *file_priv) | |
928 | { | |
929 | struct drm_i915_gem_pwrite *args = data; | |
930 | struct drm_gem_object *obj; | |
931 | struct drm_i915_gem_object *obj_priv; | |
932 | int ret = 0; | |
933 | ||
934 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); | |
935 | if (obj == NULL) | |
bf79cb91 | 936 | return -ENOENT; |
23010e43 | 937 | obj_priv = to_intel_bo(obj); |
673a394b EA |
938 | |
939 | /* Bounds check destination. | |
940 | * | |
941 | * XXX: This could use review for overflow issues... | |
942 | */ | |
943 | if (args->offset > obj->size || args->size > obj->size || | |
944 | args->offset + args->size > obj->size) { | |
bc9025bd | 945 | drm_gem_object_unreference_unlocked(obj); |
673a394b EA |
946 | return -EINVAL; |
947 | } | |
948 | ||
949 | /* We can only do the GTT pwrite on untiled buffers, as otherwise | |
950 | * it would end up going through the fenced access, and we'll get | |
951 | * different detiling behavior between reading and writing. | |
952 | * pread/pwrite currently are reading and writing from the CPU | |
953 | * perspective, requiring manual detiling by the client. | |
954 | */ | |
71acb5eb DA |
955 | if (obj_priv->phys_obj) |
956 | ret = i915_gem_phys_pwrite(dev, obj, args, file_priv); | |
957 | else if (obj_priv->tiling_mode == I915_TILING_NONE && | |
9b8c4a0b CW |
958 | dev->gtt_total != 0 && |
959 | obj->write_domain != I915_GEM_DOMAIN_CPU) { | |
3de09aa3 EA |
960 | ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file_priv); |
961 | if (ret == -EFAULT) { | |
962 | ret = i915_gem_gtt_pwrite_slow(dev, obj, args, | |
963 | file_priv); | |
964 | } | |
280b713b EA |
965 | } else if (i915_gem_object_needs_bit17_swizzle(obj)) { |
966 | ret = i915_gem_shmem_pwrite_slow(dev, obj, args, file_priv); | |
40123c1f EA |
967 | } else { |
968 | ret = i915_gem_shmem_pwrite_fast(dev, obj, args, file_priv); | |
969 | if (ret == -EFAULT) { | |
970 | ret = i915_gem_shmem_pwrite_slow(dev, obj, args, | |
971 | file_priv); | |
972 | } | |
973 | } | |
673a394b EA |
974 | |
975 | #if WATCH_PWRITE | |
976 | if (ret) | |
977 | DRM_INFO("pwrite failed %d\n", ret); | |
978 | #endif | |
979 | ||
bc9025bd | 980 | drm_gem_object_unreference_unlocked(obj); |
673a394b EA |
981 | |
982 | return ret; | |
983 | } | |
984 | ||
985 | /** | |
2ef7eeaa EA |
986 | * Called when user space prepares to use an object with the CPU, either |
987 | * through the mmap ioctl's mapping or a GTT mapping. | |
673a394b EA |
988 | */ |
989 | int | |
990 | i915_gem_set_domain_ioctl(struct drm_device *dev, void *data, | |
991 | struct drm_file *file_priv) | |
992 | { | |
a09ba7fa | 993 | struct drm_i915_private *dev_priv = dev->dev_private; |
673a394b EA |
994 | struct drm_i915_gem_set_domain *args = data; |
995 | struct drm_gem_object *obj; | |
652c393a | 996 | struct drm_i915_gem_object *obj_priv; |
2ef7eeaa EA |
997 | uint32_t read_domains = args->read_domains; |
998 | uint32_t write_domain = args->write_domain; | |
673a394b EA |
999 | int ret; |
1000 | ||
1001 | if (!(dev->driver->driver_features & DRIVER_GEM)) | |
1002 | return -ENODEV; | |
1003 | ||
2ef7eeaa | 1004 | /* Only handle setting domains to types used by the CPU. */ |
21d509e3 | 1005 | if (write_domain & I915_GEM_GPU_DOMAINS) |
2ef7eeaa EA |
1006 | return -EINVAL; |
1007 | ||
21d509e3 | 1008 | if (read_domains & I915_GEM_GPU_DOMAINS) |
2ef7eeaa EA |
1009 | return -EINVAL; |
1010 | ||
1011 | /* Having something in the write domain implies it's in the read | |
1012 | * domain, and only that read domain. Enforce that in the request. | |
1013 | */ | |
1014 | if (write_domain != 0 && read_domains != write_domain) | |
1015 | return -EINVAL; | |
1016 | ||
673a394b EA |
1017 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); |
1018 | if (obj == NULL) | |
bf79cb91 | 1019 | return -ENOENT; |
23010e43 | 1020 | obj_priv = to_intel_bo(obj); |
673a394b EA |
1021 | |
1022 | mutex_lock(&dev->struct_mutex); | |
652c393a JB |
1023 | |
1024 | intel_mark_busy(dev, obj); | |
1025 | ||
673a394b | 1026 | #if WATCH_BUF |
cfd43c02 | 1027 | DRM_INFO("set_domain_ioctl %p(%zd), %08x %08x\n", |
2ef7eeaa | 1028 | obj, obj->size, read_domains, write_domain); |
673a394b | 1029 | #endif |
2ef7eeaa EA |
1030 | if (read_domains & I915_GEM_DOMAIN_GTT) { |
1031 | ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0); | |
02354392 | 1032 | |
a09ba7fa EA |
1033 | /* Update the LRU on the fence for the CPU access that's |
1034 | * about to occur. | |
1035 | */ | |
1036 | if (obj_priv->fence_reg != I915_FENCE_REG_NONE) { | |
007cc8ac DV |
1037 | struct drm_i915_fence_reg *reg = |
1038 | &dev_priv->fence_regs[obj_priv->fence_reg]; | |
1039 | list_move_tail(®->lru_list, | |
a09ba7fa EA |
1040 | &dev_priv->mm.fence_list); |
1041 | } | |
1042 | ||
02354392 EA |
1043 | /* Silently promote "you're not bound, there was nothing to do" |
1044 | * to success, since the client was just asking us to | |
1045 | * make sure everything was done. | |
1046 | */ | |
1047 | if (ret == -EINVAL) | |
1048 | ret = 0; | |
2ef7eeaa | 1049 | } else { |
e47c68e9 | 1050 | ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0); |
2ef7eeaa EA |
1051 | } |
1052 | ||
7d1c4804 CW |
1053 | |
1054 | /* Maintain LRU order of "inactive" objects */ | |
1055 | if (ret == 0 && i915_gem_object_is_inactive(obj_priv)) | |
1056 | list_move_tail(&obj_priv->list, &dev_priv->mm.inactive_list); | |
1057 | ||
673a394b EA |
1058 | drm_gem_object_unreference(obj); |
1059 | mutex_unlock(&dev->struct_mutex); | |
1060 | return ret; | |
1061 | } | |
1062 | ||
1063 | /** | |
1064 | * Called when user space has done writes to this buffer | |
1065 | */ | |
1066 | int | |
1067 | i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data, | |
1068 | struct drm_file *file_priv) | |
1069 | { | |
1070 | struct drm_i915_gem_sw_finish *args = data; | |
1071 | struct drm_gem_object *obj; | |
1072 | struct drm_i915_gem_object *obj_priv; | |
1073 | int ret = 0; | |
1074 | ||
1075 | if (!(dev->driver->driver_features & DRIVER_GEM)) | |
1076 | return -ENODEV; | |
1077 | ||
1078 | mutex_lock(&dev->struct_mutex); | |
1079 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); | |
1080 | if (obj == NULL) { | |
1081 | mutex_unlock(&dev->struct_mutex); | |
bf79cb91 | 1082 | return -ENOENT; |
673a394b EA |
1083 | } |
1084 | ||
1085 | #if WATCH_BUF | |
cfd43c02 | 1086 | DRM_INFO("%s: sw_finish %d (%p %zd)\n", |
673a394b EA |
1087 | __func__, args->handle, obj, obj->size); |
1088 | #endif | |
23010e43 | 1089 | obj_priv = to_intel_bo(obj); |
673a394b EA |
1090 | |
1091 | /* Pinned buffers may be scanout, so flush the cache */ | |
e47c68e9 EA |
1092 | if (obj_priv->pin_count) |
1093 | i915_gem_object_flush_cpu_write_domain(obj); | |
1094 | ||
673a394b EA |
1095 | drm_gem_object_unreference(obj); |
1096 | mutex_unlock(&dev->struct_mutex); | |
1097 | return ret; | |
1098 | } | |
1099 | ||
1100 | /** | |
1101 | * Maps the contents of an object, returning the address it is mapped | |
1102 | * into. | |
1103 | * | |
1104 | * While the mapping holds a reference on the contents of the object, it doesn't | |
1105 | * imply a ref on the object itself. | |
1106 | */ | |
1107 | int | |
1108 | i915_gem_mmap_ioctl(struct drm_device *dev, void *data, | |
1109 | struct drm_file *file_priv) | |
1110 | { | |
1111 | struct drm_i915_gem_mmap *args = data; | |
1112 | struct drm_gem_object *obj; | |
1113 | loff_t offset; | |
1114 | unsigned long addr; | |
1115 | ||
1116 | if (!(dev->driver->driver_features & DRIVER_GEM)) | |
1117 | return -ENODEV; | |
1118 | ||
1119 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); | |
1120 | if (obj == NULL) | |
bf79cb91 | 1121 | return -ENOENT; |
673a394b EA |
1122 | |
1123 | offset = args->offset; | |
1124 | ||
1125 | down_write(¤t->mm->mmap_sem); | |
1126 | addr = do_mmap(obj->filp, 0, args->size, | |
1127 | PROT_READ | PROT_WRITE, MAP_SHARED, | |
1128 | args->offset); | |
1129 | up_write(¤t->mm->mmap_sem); | |
bc9025bd | 1130 | drm_gem_object_unreference_unlocked(obj); |
673a394b EA |
1131 | if (IS_ERR((void *)addr)) |
1132 | return addr; | |
1133 | ||
1134 | args->addr_ptr = (uint64_t) addr; | |
1135 | ||
1136 | return 0; | |
1137 | } | |
1138 | ||
de151cf6 JB |
1139 | /** |
1140 | * i915_gem_fault - fault a page into the GTT | |
1141 | * vma: VMA in question | |
1142 | * vmf: fault info | |
1143 | * | |
1144 | * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped | |
1145 | * from userspace. The fault handler takes care of binding the object to | |
1146 | * the GTT (if needed), allocating and programming a fence register (again, | |
1147 | * only if needed based on whether the old reg is still valid or the object | |
1148 | * is tiled) and inserting a new PTE into the faulting process. | |
1149 | * | |
1150 | * Note that the faulting process may involve evicting existing objects | |
1151 | * from the GTT and/or fence registers to make room. So performance may | |
1152 | * suffer if the GTT working set is large or there are few fence registers | |
1153 | * left. | |
1154 | */ | |
1155 | int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf) | |
1156 | { | |
1157 | struct drm_gem_object *obj = vma->vm_private_data; | |
1158 | struct drm_device *dev = obj->dev; | |
7d1c4804 | 1159 | drm_i915_private_t *dev_priv = dev->dev_private; |
23010e43 | 1160 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
de151cf6 JB |
1161 | pgoff_t page_offset; |
1162 | unsigned long pfn; | |
1163 | int ret = 0; | |
0f973f27 | 1164 | bool write = !!(vmf->flags & FAULT_FLAG_WRITE); |
de151cf6 JB |
1165 | |
1166 | /* We don't use vmf->pgoff since that has the fake offset */ | |
1167 | page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >> | |
1168 | PAGE_SHIFT; | |
1169 | ||
1170 | /* Now bind it into the GTT if needed */ | |
1171 | mutex_lock(&dev->struct_mutex); | |
1172 | if (!obj_priv->gtt_space) { | |
e67b8ce1 | 1173 | ret = i915_gem_object_bind_to_gtt(obj, 0); |
c715089f CW |
1174 | if (ret) |
1175 | goto unlock; | |
07f4f3e8 | 1176 | |
07f4f3e8 | 1177 | ret = i915_gem_object_set_to_gtt_domain(obj, write); |
c715089f CW |
1178 | if (ret) |
1179 | goto unlock; | |
de151cf6 JB |
1180 | } |
1181 | ||
1182 | /* Need a new fence register? */ | |
a09ba7fa | 1183 | if (obj_priv->tiling_mode != I915_TILING_NONE) { |
8c4b8c3f | 1184 | ret = i915_gem_object_get_fence_reg(obj); |
c715089f CW |
1185 | if (ret) |
1186 | goto unlock; | |
d9ddcb96 | 1187 | } |
de151cf6 | 1188 | |
7d1c4804 CW |
1189 | if (i915_gem_object_is_inactive(obj_priv)) |
1190 | list_move_tail(&obj_priv->list, &dev_priv->mm.inactive_list); | |
1191 | ||
de151cf6 JB |
1192 | pfn = ((dev->agp->base + obj_priv->gtt_offset) >> PAGE_SHIFT) + |
1193 | page_offset; | |
1194 | ||
1195 | /* Finally, remap it using the new GTT offset */ | |
1196 | ret = vm_insert_pfn(vma, (unsigned long)vmf->virtual_address, pfn); | |
c715089f | 1197 | unlock: |
de151cf6 JB |
1198 | mutex_unlock(&dev->struct_mutex); |
1199 | ||
1200 | switch (ret) { | |
c715089f CW |
1201 | case 0: |
1202 | case -ERESTARTSYS: | |
1203 | return VM_FAULT_NOPAGE; | |
de151cf6 JB |
1204 | case -ENOMEM: |
1205 | case -EAGAIN: | |
1206 | return VM_FAULT_OOM; | |
de151cf6 | 1207 | default: |
c715089f | 1208 | return VM_FAULT_SIGBUS; |
de151cf6 JB |
1209 | } |
1210 | } | |
1211 | ||
1212 | /** | |
1213 | * i915_gem_create_mmap_offset - create a fake mmap offset for an object | |
1214 | * @obj: obj in question | |
1215 | * | |
1216 | * GEM memory mapping works by handing back to userspace a fake mmap offset | |
1217 | * it can use in a subsequent mmap(2) call. The DRM core code then looks | |
1218 | * up the object based on the offset and sets up the various memory mapping | |
1219 | * structures. | |
1220 | * | |
1221 | * This routine allocates and attaches a fake offset for @obj. | |
1222 | */ | |
1223 | static int | |
1224 | i915_gem_create_mmap_offset(struct drm_gem_object *obj) | |
1225 | { | |
1226 | struct drm_device *dev = obj->dev; | |
1227 | struct drm_gem_mm *mm = dev->mm_private; | |
23010e43 | 1228 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
de151cf6 | 1229 | struct drm_map_list *list; |
f77d390c | 1230 | struct drm_local_map *map; |
de151cf6 JB |
1231 | int ret = 0; |
1232 | ||
1233 | /* Set the object up for mmap'ing */ | |
1234 | list = &obj->map_list; | |
9a298b2a | 1235 | list->map = kzalloc(sizeof(struct drm_map_list), GFP_KERNEL); |
de151cf6 JB |
1236 | if (!list->map) |
1237 | return -ENOMEM; | |
1238 | ||
1239 | map = list->map; | |
1240 | map->type = _DRM_GEM; | |
1241 | map->size = obj->size; | |
1242 | map->handle = obj; | |
1243 | ||
1244 | /* Get a DRM GEM mmap offset allocated... */ | |
1245 | list->file_offset_node = drm_mm_search_free(&mm->offset_manager, | |
1246 | obj->size / PAGE_SIZE, 0, 0); | |
1247 | if (!list->file_offset_node) { | |
1248 | DRM_ERROR("failed to allocate offset for bo %d\n", obj->name); | |
1249 | ret = -ENOMEM; | |
1250 | goto out_free_list; | |
1251 | } | |
1252 | ||
1253 | list->file_offset_node = drm_mm_get_block(list->file_offset_node, | |
1254 | obj->size / PAGE_SIZE, 0); | |
1255 | if (!list->file_offset_node) { | |
1256 | ret = -ENOMEM; | |
1257 | goto out_free_list; | |
1258 | } | |
1259 | ||
1260 | list->hash.key = list->file_offset_node->start; | |
1261 | if (drm_ht_insert_item(&mm->offset_hash, &list->hash)) { | |
1262 | DRM_ERROR("failed to add to map hash\n"); | |
5618ca6a | 1263 | ret = -ENOMEM; |
de151cf6 JB |
1264 | goto out_free_mm; |
1265 | } | |
1266 | ||
1267 | /* By now we should be all set, any drm_mmap request on the offset | |
1268 | * below will get to our mmap & fault handler */ | |
1269 | obj_priv->mmap_offset = ((uint64_t) list->hash.key) << PAGE_SHIFT; | |
1270 | ||
1271 | return 0; | |
1272 | ||
1273 | out_free_mm: | |
1274 | drm_mm_put_block(list->file_offset_node); | |
1275 | out_free_list: | |
9a298b2a | 1276 | kfree(list->map); |
de151cf6 JB |
1277 | |
1278 | return ret; | |
1279 | } | |
1280 | ||
901782b2 CW |
1281 | /** |
1282 | * i915_gem_release_mmap - remove physical page mappings | |
1283 | * @obj: obj in question | |
1284 | * | |
af901ca1 | 1285 | * Preserve the reservation of the mmapping with the DRM core code, but |
901782b2 CW |
1286 | * relinquish ownership of the pages back to the system. |
1287 | * | |
1288 | * It is vital that we remove the page mapping if we have mapped a tiled | |
1289 | * object through the GTT and then lose the fence register due to | |
1290 | * resource pressure. Similarly if the object has been moved out of the | |
1291 | * aperture, than pages mapped into userspace must be revoked. Removing the | |
1292 | * mapping will then trigger a page fault on the next user access, allowing | |
1293 | * fixup by i915_gem_fault(). | |
1294 | */ | |
d05ca301 | 1295 | void |
901782b2 CW |
1296 | i915_gem_release_mmap(struct drm_gem_object *obj) |
1297 | { | |
1298 | struct drm_device *dev = obj->dev; | |
23010e43 | 1299 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
901782b2 CW |
1300 | |
1301 | if (dev->dev_mapping) | |
1302 | unmap_mapping_range(dev->dev_mapping, | |
1303 | obj_priv->mmap_offset, obj->size, 1); | |
1304 | } | |
1305 | ||
ab00b3e5 JB |
1306 | static void |
1307 | i915_gem_free_mmap_offset(struct drm_gem_object *obj) | |
1308 | { | |
1309 | struct drm_device *dev = obj->dev; | |
23010e43 | 1310 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
ab00b3e5 JB |
1311 | struct drm_gem_mm *mm = dev->mm_private; |
1312 | struct drm_map_list *list; | |
1313 | ||
1314 | list = &obj->map_list; | |
1315 | drm_ht_remove_item(&mm->offset_hash, &list->hash); | |
1316 | ||
1317 | if (list->file_offset_node) { | |
1318 | drm_mm_put_block(list->file_offset_node); | |
1319 | list->file_offset_node = NULL; | |
1320 | } | |
1321 | ||
1322 | if (list->map) { | |
9a298b2a | 1323 | kfree(list->map); |
ab00b3e5 JB |
1324 | list->map = NULL; |
1325 | } | |
1326 | ||
1327 | obj_priv->mmap_offset = 0; | |
1328 | } | |
1329 | ||
de151cf6 JB |
1330 | /** |
1331 | * i915_gem_get_gtt_alignment - return required GTT alignment for an object | |
1332 | * @obj: object to check | |
1333 | * | |
1334 | * Return the required GTT alignment for an object, taking into account | |
1335 | * potential fence register mapping if needed. | |
1336 | */ | |
1337 | static uint32_t | |
1338 | i915_gem_get_gtt_alignment(struct drm_gem_object *obj) | |
1339 | { | |
1340 | struct drm_device *dev = obj->dev; | |
23010e43 | 1341 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
de151cf6 JB |
1342 | int start, i; |
1343 | ||
1344 | /* | |
1345 | * Minimum alignment is 4k (GTT page size), but might be greater | |
1346 | * if a fence register is needed for the object. | |
1347 | */ | |
1348 | if (IS_I965G(dev) || obj_priv->tiling_mode == I915_TILING_NONE) | |
1349 | return 4096; | |
1350 | ||
1351 | /* | |
1352 | * Previous chips need to be aligned to the size of the smallest | |
1353 | * fence register that can contain the object. | |
1354 | */ | |
1355 | if (IS_I9XX(dev)) | |
1356 | start = 1024*1024; | |
1357 | else | |
1358 | start = 512*1024; | |
1359 | ||
1360 | for (i = start; i < obj->size; i <<= 1) | |
1361 | ; | |
1362 | ||
1363 | return i; | |
1364 | } | |
1365 | ||
1366 | /** | |
1367 | * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing | |
1368 | * @dev: DRM device | |
1369 | * @data: GTT mapping ioctl data | |
1370 | * @file_priv: GEM object info | |
1371 | * | |
1372 | * Simply returns the fake offset to userspace so it can mmap it. | |
1373 | * The mmap call will end up in drm_gem_mmap(), which will set things | |
1374 | * up so we can get faults in the handler above. | |
1375 | * | |
1376 | * The fault handler will take care of binding the object into the GTT | |
1377 | * (since it may have been evicted to make room for something), allocating | |
1378 | * a fence register, and mapping the appropriate aperture address into | |
1379 | * userspace. | |
1380 | */ | |
1381 | int | |
1382 | i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data, | |
1383 | struct drm_file *file_priv) | |
1384 | { | |
1385 | struct drm_i915_gem_mmap_gtt *args = data; | |
de151cf6 JB |
1386 | struct drm_gem_object *obj; |
1387 | struct drm_i915_gem_object *obj_priv; | |
1388 | int ret; | |
1389 | ||
1390 | if (!(dev->driver->driver_features & DRIVER_GEM)) | |
1391 | return -ENODEV; | |
1392 | ||
1393 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); | |
1394 | if (obj == NULL) | |
bf79cb91 | 1395 | return -ENOENT; |
de151cf6 JB |
1396 | |
1397 | mutex_lock(&dev->struct_mutex); | |
1398 | ||
23010e43 | 1399 | obj_priv = to_intel_bo(obj); |
de151cf6 | 1400 | |
ab18282d CW |
1401 | if (obj_priv->madv != I915_MADV_WILLNEED) { |
1402 | DRM_ERROR("Attempting to mmap a purgeable buffer\n"); | |
1403 | drm_gem_object_unreference(obj); | |
1404 | mutex_unlock(&dev->struct_mutex); | |
1405 | return -EINVAL; | |
1406 | } | |
1407 | ||
1408 | ||
de151cf6 JB |
1409 | if (!obj_priv->mmap_offset) { |
1410 | ret = i915_gem_create_mmap_offset(obj); | |
13af1062 CW |
1411 | if (ret) { |
1412 | drm_gem_object_unreference(obj); | |
1413 | mutex_unlock(&dev->struct_mutex); | |
de151cf6 | 1414 | return ret; |
13af1062 | 1415 | } |
de151cf6 JB |
1416 | } |
1417 | ||
1418 | args->offset = obj_priv->mmap_offset; | |
1419 | ||
de151cf6 JB |
1420 | /* |
1421 | * Pull it into the GTT so that we have a page list (makes the | |
1422 | * initial fault faster and any subsequent flushing possible). | |
1423 | */ | |
1424 | if (!obj_priv->agp_mem) { | |
e67b8ce1 | 1425 | ret = i915_gem_object_bind_to_gtt(obj, 0); |
de151cf6 JB |
1426 | if (ret) { |
1427 | drm_gem_object_unreference(obj); | |
1428 | mutex_unlock(&dev->struct_mutex); | |
1429 | return ret; | |
1430 | } | |
de151cf6 JB |
1431 | } |
1432 | ||
1433 | drm_gem_object_unreference(obj); | |
1434 | mutex_unlock(&dev->struct_mutex); | |
1435 | ||
1436 | return 0; | |
1437 | } | |
1438 | ||
6911a9b8 | 1439 | void |
856fa198 | 1440 | i915_gem_object_put_pages(struct drm_gem_object *obj) |
673a394b | 1441 | { |
23010e43 | 1442 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
673a394b EA |
1443 | int page_count = obj->size / PAGE_SIZE; |
1444 | int i; | |
1445 | ||
856fa198 | 1446 | BUG_ON(obj_priv->pages_refcount == 0); |
bb6baf76 | 1447 | BUG_ON(obj_priv->madv == __I915_MADV_PURGED); |
673a394b | 1448 | |
856fa198 EA |
1449 | if (--obj_priv->pages_refcount != 0) |
1450 | return; | |
673a394b | 1451 | |
280b713b EA |
1452 | if (obj_priv->tiling_mode != I915_TILING_NONE) |
1453 | i915_gem_object_save_bit_17_swizzle(obj); | |
1454 | ||
3ef94daa | 1455 | if (obj_priv->madv == I915_MADV_DONTNEED) |
13a05fd9 | 1456 | obj_priv->dirty = 0; |
3ef94daa CW |
1457 | |
1458 | for (i = 0; i < page_count; i++) { | |
3ef94daa CW |
1459 | if (obj_priv->dirty) |
1460 | set_page_dirty(obj_priv->pages[i]); | |
1461 | ||
1462 | if (obj_priv->madv == I915_MADV_WILLNEED) | |
856fa198 | 1463 | mark_page_accessed(obj_priv->pages[i]); |
3ef94daa CW |
1464 | |
1465 | page_cache_release(obj_priv->pages[i]); | |
1466 | } | |
673a394b EA |
1467 | obj_priv->dirty = 0; |
1468 | ||
8e7d2b2c | 1469 | drm_free_large(obj_priv->pages); |
856fa198 | 1470 | obj_priv->pages = NULL; |
673a394b EA |
1471 | } |
1472 | ||
e35a41de | 1473 | static uint32_t |
a6910434 DV |
1474 | i915_gem_next_request_seqno(struct drm_device *dev, |
1475 | struct intel_ring_buffer *ring) | |
e35a41de DV |
1476 | { |
1477 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1478 | ||
a6910434 DV |
1479 | ring->outstanding_lazy_request = true; |
1480 | ||
e35a41de DV |
1481 | return dev_priv->next_seqno; |
1482 | } | |
1483 | ||
673a394b | 1484 | static void |
617dbe27 | 1485 | i915_gem_object_move_to_active(struct drm_gem_object *obj, |
852835f3 | 1486 | struct intel_ring_buffer *ring) |
673a394b EA |
1487 | { |
1488 | struct drm_device *dev = obj->dev; | |
1489 | drm_i915_private_t *dev_priv = dev->dev_private; | |
23010e43 | 1490 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
617dbe27 DV |
1491 | uint32_t seqno = i915_gem_next_request_seqno(dev, ring); |
1492 | ||
852835f3 ZN |
1493 | BUG_ON(ring == NULL); |
1494 | obj_priv->ring = ring; | |
673a394b EA |
1495 | |
1496 | /* Add a reference if we're newly entering the active list. */ | |
1497 | if (!obj_priv->active) { | |
1498 | drm_gem_object_reference(obj); | |
1499 | obj_priv->active = 1; | |
1500 | } | |
e35a41de | 1501 | |
673a394b | 1502 | /* Move from whatever list we were on to the tail of execution. */ |
5e118f41 | 1503 | spin_lock(&dev_priv->mm.active_list_lock); |
852835f3 | 1504 | list_move_tail(&obj_priv->list, &ring->active_list); |
5e118f41 | 1505 | spin_unlock(&dev_priv->mm.active_list_lock); |
ce44b0ea | 1506 | obj_priv->last_rendering_seqno = seqno; |
673a394b EA |
1507 | } |
1508 | ||
ce44b0ea EA |
1509 | static void |
1510 | i915_gem_object_move_to_flushing(struct drm_gem_object *obj) | |
1511 | { | |
1512 | struct drm_device *dev = obj->dev; | |
1513 | drm_i915_private_t *dev_priv = dev->dev_private; | |
23010e43 | 1514 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
ce44b0ea EA |
1515 | |
1516 | BUG_ON(!obj_priv->active); | |
1517 | list_move_tail(&obj_priv->list, &dev_priv->mm.flushing_list); | |
1518 | obj_priv->last_rendering_seqno = 0; | |
1519 | } | |
673a394b | 1520 | |
963b4836 CW |
1521 | /* Immediately discard the backing storage */ |
1522 | static void | |
1523 | i915_gem_object_truncate(struct drm_gem_object *obj) | |
1524 | { | |
23010e43 | 1525 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
bb6baf76 | 1526 | struct inode *inode; |
963b4836 | 1527 | |
ae9fed6b CW |
1528 | /* Our goal here is to return as much of the memory as |
1529 | * is possible back to the system as we are called from OOM. | |
1530 | * To do this we must instruct the shmfs to drop all of its | |
1531 | * backing pages, *now*. Here we mirror the actions taken | |
1532 | * when by shmem_delete_inode() to release the backing store. | |
1533 | */ | |
bb6baf76 | 1534 | inode = obj->filp->f_path.dentry->d_inode; |
ae9fed6b CW |
1535 | truncate_inode_pages(inode->i_mapping, 0); |
1536 | if (inode->i_op->truncate_range) | |
1537 | inode->i_op->truncate_range(inode, 0, (loff_t)-1); | |
bb6baf76 CW |
1538 | |
1539 | obj_priv->madv = __I915_MADV_PURGED; | |
963b4836 CW |
1540 | } |
1541 | ||
1542 | static inline int | |
1543 | i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj_priv) | |
1544 | { | |
1545 | return obj_priv->madv == I915_MADV_DONTNEED; | |
1546 | } | |
1547 | ||
673a394b EA |
1548 | static void |
1549 | i915_gem_object_move_to_inactive(struct drm_gem_object *obj) | |
1550 | { | |
1551 | struct drm_device *dev = obj->dev; | |
1552 | drm_i915_private_t *dev_priv = dev->dev_private; | |
23010e43 | 1553 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
673a394b EA |
1554 | |
1555 | i915_verify_inactive(dev, __FILE__, __LINE__); | |
1556 | if (obj_priv->pin_count != 0) | |
1557 | list_del_init(&obj_priv->list); | |
1558 | else | |
1559 | list_move_tail(&obj_priv->list, &dev_priv->mm.inactive_list); | |
1560 | ||
99fcb766 DV |
1561 | BUG_ON(!list_empty(&obj_priv->gpu_write_list)); |
1562 | ||
ce44b0ea | 1563 | obj_priv->last_rendering_seqno = 0; |
852835f3 | 1564 | obj_priv->ring = NULL; |
673a394b EA |
1565 | if (obj_priv->active) { |
1566 | obj_priv->active = 0; | |
1567 | drm_gem_object_unreference(obj); | |
1568 | } | |
1569 | i915_verify_inactive(dev, __FILE__, __LINE__); | |
1570 | } | |
1571 | ||
8a1a49f9 | 1572 | void |
63560396 | 1573 | i915_gem_process_flushing_list(struct drm_device *dev, |
8a1a49f9 | 1574 | uint32_t flush_domains, |
852835f3 | 1575 | struct intel_ring_buffer *ring) |
63560396 DV |
1576 | { |
1577 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1578 | struct drm_i915_gem_object *obj_priv, *next; | |
1579 | ||
1580 | list_for_each_entry_safe(obj_priv, next, | |
1581 | &dev_priv->mm.gpu_write_list, | |
1582 | gpu_write_list) { | |
a8089e84 | 1583 | struct drm_gem_object *obj = &obj_priv->base; |
63560396 DV |
1584 | |
1585 | if ((obj->write_domain & flush_domains) == | |
852835f3 ZN |
1586 | obj->write_domain && |
1587 | obj_priv->ring->ring_flag == ring->ring_flag) { | |
63560396 DV |
1588 | uint32_t old_write_domain = obj->write_domain; |
1589 | ||
1590 | obj->write_domain = 0; | |
1591 | list_del_init(&obj_priv->gpu_write_list); | |
617dbe27 | 1592 | i915_gem_object_move_to_active(obj, ring); |
63560396 DV |
1593 | |
1594 | /* update the fence lru list */ | |
007cc8ac DV |
1595 | if (obj_priv->fence_reg != I915_FENCE_REG_NONE) { |
1596 | struct drm_i915_fence_reg *reg = | |
1597 | &dev_priv->fence_regs[obj_priv->fence_reg]; | |
1598 | list_move_tail(®->lru_list, | |
63560396 | 1599 | &dev_priv->mm.fence_list); |
007cc8ac | 1600 | } |
63560396 DV |
1601 | |
1602 | trace_i915_gem_object_change_domain(obj, | |
1603 | obj->read_domains, | |
1604 | old_write_domain); | |
1605 | } | |
1606 | } | |
1607 | } | |
8187a2b7 | 1608 | |
5a5a0c64 | 1609 | uint32_t |
8a1a49f9 DV |
1610 | i915_add_request(struct drm_device *dev, |
1611 | struct drm_file *file_priv, | |
8dc5d147 | 1612 | struct drm_i915_gem_request *request, |
8a1a49f9 | 1613 | struct intel_ring_buffer *ring) |
673a394b EA |
1614 | { |
1615 | drm_i915_private_t *dev_priv = dev->dev_private; | |
b962442e | 1616 | struct drm_i915_file_private *i915_file_priv = NULL; |
673a394b EA |
1617 | uint32_t seqno; |
1618 | int was_empty; | |
673a394b | 1619 | |
b962442e EA |
1620 | if (file_priv != NULL) |
1621 | i915_file_priv = file_priv->driver_priv; | |
1622 | ||
8dc5d147 CW |
1623 | if (request == NULL) { |
1624 | request = kzalloc(sizeof(*request), GFP_KERNEL); | |
1625 | if (request == NULL) | |
1626 | return 0; | |
1627 | } | |
673a394b | 1628 | |
8a1a49f9 | 1629 | seqno = ring->add_request(dev, ring, file_priv, 0); |
673a394b EA |
1630 | |
1631 | request->seqno = seqno; | |
852835f3 | 1632 | request->ring = ring; |
673a394b | 1633 | request->emitted_jiffies = jiffies; |
852835f3 ZN |
1634 | was_empty = list_empty(&ring->request_list); |
1635 | list_add_tail(&request->list, &ring->request_list); | |
1636 | ||
b962442e EA |
1637 | if (i915_file_priv) { |
1638 | list_add_tail(&request->client_list, | |
1639 | &i915_file_priv->mm.request_list); | |
1640 | } else { | |
1641 | INIT_LIST_HEAD(&request->client_list); | |
1642 | } | |
673a394b | 1643 | |
f65d9421 BG |
1644 | if (!dev_priv->mm.suspended) { |
1645 | mod_timer(&dev_priv->hangcheck_timer, jiffies + DRM_I915_HANGCHECK_PERIOD); | |
1646 | if (was_empty) | |
1647 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ); | |
1648 | } | |
673a394b EA |
1649 | return seqno; |
1650 | } | |
1651 | ||
1652 | /** | |
1653 | * Command execution barrier | |
1654 | * | |
1655 | * Ensures that all commands in the ring are finished | |
1656 | * before signalling the CPU | |
1657 | */ | |
8a1a49f9 | 1658 | static void |
852835f3 | 1659 | i915_retire_commands(struct drm_device *dev, struct intel_ring_buffer *ring) |
673a394b | 1660 | { |
673a394b | 1661 | uint32_t flush_domains = 0; |
673a394b EA |
1662 | |
1663 | /* The sampler always gets flushed on i965 (sigh) */ | |
1664 | if (IS_I965G(dev)) | |
1665 | flush_domains |= I915_GEM_DOMAIN_SAMPLER; | |
852835f3 ZN |
1666 | |
1667 | ring->flush(dev, ring, | |
1668 | I915_GEM_DOMAIN_COMMAND, flush_domains); | |
673a394b EA |
1669 | } |
1670 | ||
1671 | /** | |
1672 | * Moves buffers associated only with the given active seqno from the active | |
1673 | * to inactive list, potentially freeing them. | |
1674 | */ | |
1675 | static void | |
1676 | i915_gem_retire_request(struct drm_device *dev, | |
1677 | struct drm_i915_gem_request *request) | |
1678 | { | |
1679 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1680 | ||
1c5d22f7 CW |
1681 | trace_i915_gem_request_retire(dev, request->seqno); |
1682 | ||
673a394b EA |
1683 | /* Move any buffers on the active list that are no longer referenced |
1684 | * by the ringbuffer to the flushing/inactive lists as appropriate. | |
1685 | */ | |
5e118f41 | 1686 | spin_lock(&dev_priv->mm.active_list_lock); |
852835f3 | 1687 | while (!list_empty(&request->ring->active_list)) { |
673a394b EA |
1688 | struct drm_gem_object *obj; |
1689 | struct drm_i915_gem_object *obj_priv; | |
1690 | ||
852835f3 | 1691 | obj_priv = list_first_entry(&request->ring->active_list, |
673a394b EA |
1692 | struct drm_i915_gem_object, |
1693 | list); | |
a8089e84 | 1694 | obj = &obj_priv->base; |
673a394b EA |
1695 | |
1696 | /* If the seqno being retired doesn't match the oldest in the | |
1697 | * list, then the oldest in the list must still be newer than | |
1698 | * this seqno. | |
1699 | */ | |
1700 | if (obj_priv->last_rendering_seqno != request->seqno) | |
5e118f41 | 1701 | goto out; |
de151cf6 | 1702 | |
673a394b EA |
1703 | #if WATCH_LRU |
1704 | DRM_INFO("%s: retire %d moves to inactive list %p\n", | |
1705 | __func__, request->seqno, obj); | |
1706 | #endif | |
1707 | ||
ce44b0ea EA |
1708 | if (obj->write_domain != 0) |
1709 | i915_gem_object_move_to_flushing(obj); | |
68c84342 SL |
1710 | else { |
1711 | /* Take a reference on the object so it won't be | |
1712 | * freed while the spinlock is held. The list | |
1713 | * protection for this spinlock is safe when breaking | |
1714 | * the lock like this since the next thing we do | |
1715 | * is just get the head of the list again. | |
1716 | */ | |
1717 | drm_gem_object_reference(obj); | |
673a394b | 1718 | i915_gem_object_move_to_inactive(obj); |
68c84342 SL |
1719 | spin_unlock(&dev_priv->mm.active_list_lock); |
1720 | drm_gem_object_unreference(obj); | |
1721 | spin_lock(&dev_priv->mm.active_list_lock); | |
1722 | } | |
673a394b | 1723 | } |
5e118f41 CW |
1724 | out: |
1725 | spin_unlock(&dev_priv->mm.active_list_lock); | |
673a394b EA |
1726 | } |
1727 | ||
1728 | /** | |
1729 | * Returns true if seq1 is later than seq2. | |
1730 | */ | |
22be1724 | 1731 | bool |
673a394b EA |
1732 | i915_seqno_passed(uint32_t seq1, uint32_t seq2) |
1733 | { | |
1734 | return (int32_t)(seq1 - seq2) >= 0; | |
1735 | } | |
1736 | ||
1737 | uint32_t | |
852835f3 | 1738 | i915_get_gem_seqno(struct drm_device *dev, |
d1b851fc | 1739 | struct intel_ring_buffer *ring) |
673a394b | 1740 | { |
852835f3 | 1741 | return ring->get_gem_seqno(dev, ring); |
673a394b EA |
1742 | } |
1743 | ||
1744 | /** | |
1745 | * This function clears the request list as sequence numbers are passed. | |
1746 | */ | |
b09a1fec CW |
1747 | static void |
1748 | i915_gem_retire_requests_ring(struct drm_device *dev, | |
1749 | struct intel_ring_buffer *ring) | |
673a394b EA |
1750 | { |
1751 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1752 | uint32_t seqno; | |
1753 | ||
8187a2b7 | 1754 | if (!ring->status_page.page_addr |
852835f3 | 1755 | || list_empty(&ring->request_list)) |
6c0594a3 KW |
1756 | return; |
1757 | ||
852835f3 | 1758 | seqno = i915_get_gem_seqno(dev, ring); |
673a394b | 1759 | |
852835f3 | 1760 | while (!list_empty(&ring->request_list)) { |
673a394b EA |
1761 | struct drm_i915_gem_request *request; |
1762 | uint32_t retiring_seqno; | |
1763 | ||
852835f3 | 1764 | request = list_first_entry(&ring->request_list, |
673a394b EA |
1765 | struct drm_i915_gem_request, |
1766 | list); | |
1767 | retiring_seqno = request->seqno; | |
1768 | ||
1769 | if (i915_seqno_passed(seqno, retiring_seqno) || | |
ba1234d1 | 1770 | atomic_read(&dev_priv->mm.wedged)) { |
673a394b EA |
1771 | i915_gem_retire_request(dev, request); |
1772 | ||
1773 | list_del(&request->list); | |
b962442e | 1774 | list_del(&request->client_list); |
9a298b2a | 1775 | kfree(request); |
673a394b EA |
1776 | } else |
1777 | break; | |
1778 | } | |
9d34e5db CW |
1779 | |
1780 | if (unlikely (dev_priv->trace_irq_seqno && | |
1781 | i915_seqno_passed(dev_priv->trace_irq_seqno, seqno))) { | |
8187a2b7 ZN |
1782 | |
1783 | ring->user_irq_put(dev, ring); | |
9d34e5db CW |
1784 | dev_priv->trace_irq_seqno = 0; |
1785 | } | |
673a394b EA |
1786 | } |
1787 | ||
b09a1fec CW |
1788 | void |
1789 | i915_gem_retire_requests(struct drm_device *dev) | |
1790 | { | |
1791 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1792 | ||
be72615b CW |
1793 | if (!list_empty(&dev_priv->mm.deferred_free_list)) { |
1794 | struct drm_i915_gem_object *obj_priv, *tmp; | |
1795 | ||
1796 | /* We must be careful that during unbind() we do not | |
1797 | * accidentally infinitely recurse into retire requests. | |
1798 | * Currently: | |
1799 | * retire -> free -> unbind -> wait -> retire_ring | |
1800 | */ | |
1801 | list_for_each_entry_safe(obj_priv, tmp, | |
1802 | &dev_priv->mm.deferred_free_list, | |
1803 | list) | |
1804 | i915_gem_free_object_tail(&obj_priv->base); | |
1805 | } | |
1806 | ||
b09a1fec CW |
1807 | i915_gem_retire_requests_ring(dev, &dev_priv->render_ring); |
1808 | if (HAS_BSD(dev)) | |
1809 | i915_gem_retire_requests_ring(dev, &dev_priv->bsd_ring); | |
1810 | } | |
1811 | ||
75ef9da2 | 1812 | static void |
673a394b EA |
1813 | i915_gem_retire_work_handler(struct work_struct *work) |
1814 | { | |
1815 | drm_i915_private_t *dev_priv; | |
1816 | struct drm_device *dev; | |
1817 | ||
1818 | dev_priv = container_of(work, drm_i915_private_t, | |
1819 | mm.retire_work.work); | |
1820 | dev = dev_priv->dev; | |
1821 | ||
1822 | mutex_lock(&dev->struct_mutex); | |
b09a1fec | 1823 | i915_gem_retire_requests(dev); |
d1b851fc | 1824 | |
6dbe2772 | 1825 | if (!dev_priv->mm.suspended && |
d1b851fc ZN |
1826 | (!list_empty(&dev_priv->render_ring.request_list) || |
1827 | (HAS_BSD(dev) && | |
1828 | !list_empty(&dev_priv->bsd_ring.request_list)))) | |
9c9fe1f8 | 1829 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ); |
673a394b EA |
1830 | mutex_unlock(&dev->struct_mutex); |
1831 | } | |
1832 | ||
5a5a0c64 | 1833 | int |
852835f3 | 1834 | i915_do_wait_request(struct drm_device *dev, uint32_t seqno, |
8a1a49f9 | 1835 | bool interruptible, struct intel_ring_buffer *ring) |
673a394b EA |
1836 | { |
1837 | drm_i915_private_t *dev_priv = dev->dev_private; | |
802c7eb6 | 1838 | u32 ier; |
673a394b EA |
1839 | int ret = 0; |
1840 | ||
1841 | BUG_ON(seqno == 0); | |
1842 | ||
e35a41de | 1843 | if (seqno == dev_priv->next_seqno) { |
8dc5d147 | 1844 | seqno = i915_add_request(dev, NULL, NULL, ring); |
e35a41de DV |
1845 | if (seqno == 0) |
1846 | return -ENOMEM; | |
1847 | } | |
1848 | ||
ba1234d1 | 1849 | if (atomic_read(&dev_priv->mm.wedged)) |
ffed1d09 BG |
1850 | return -EIO; |
1851 | ||
852835f3 | 1852 | if (!i915_seqno_passed(ring->get_gem_seqno(dev, ring), seqno)) { |
bad720ff | 1853 | if (HAS_PCH_SPLIT(dev)) |
036a4a7d ZW |
1854 | ier = I915_READ(DEIER) | I915_READ(GTIER); |
1855 | else | |
1856 | ier = I915_READ(IER); | |
802c7eb6 JB |
1857 | if (!ier) { |
1858 | DRM_ERROR("something (likely vbetool) disabled " | |
1859 | "interrupts, re-enabling\n"); | |
1860 | i915_driver_irq_preinstall(dev); | |
1861 | i915_driver_irq_postinstall(dev); | |
1862 | } | |
1863 | ||
1c5d22f7 CW |
1864 | trace_i915_gem_request_wait_begin(dev, seqno); |
1865 | ||
852835f3 | 1866 | ring->waiting_gem_seqno = seqno; |
8187a2b7 | 1867 | ring->user_irq_get(dev, ring); |
48764bf4 | 1868 | if (interruptible) |
852835f3 ZN |
1869 | ret = wait_event_interruptible(ring->irq_queue, |
1870 | i915_seqno_passed( | |
1871 | ring->get_gem_seqno(dev, ring), seqno) | |
1872 | || atomic_read(&dev_priv->mm.wedged)); | |
48764bf4 | 1873 | else |
852835f3 ZN |
1874 | wait_event(ring->irq_queue, |
1875 | i915_seqno_passed( | |
1876 | ring->get_gem_seqno(dev, ring), seqno) | |
1877 | || atomic_read(&dev_priv->mm.wedged)); | |
48764bf4 | 1878 | |
8187a2b7 | 1879 | ring->user_irq_put(dev, ring); |
852835f3 | 1880 | ring->waiting_gem_seqno = 0; |
1c5d22f7 CW |
1881 | |
1882 | trace_i915_gem_request_wait_end(dev, seqno); | |
673a394b | 1883 | } |
ba1234d1 | 1884 | if (atomic_read(&dev_priv->mm.wedged)) |
673a394b EA |
1885 | ret = -EIO; |
1886 | ||
1887 | if (ret && ret != -ERESTARTSYS) | |
8bff917c DV |
1888 | DRM_ERROR("%s returns %d (awaiting %d at %d, next %d)\n", |
1889 | __func__, ret, seqno, ring->get_gem_seqno(dev, ring), | |
1890 | dev_priv->next_seqno); | |
673a394b EA |
1891 | |
1892 | /* Directly dispatch request retiring. While we have the work queue | |
1893 | * to handle this, the waiter on a request often wants an associated | |
1894 | * buffer to have made it to the inactive list, and we would need | |
1895 | * a separate wait queue to handle that. | |
1896 | */ | |
1897 | if (ret == 0) | |
b09a1fec | 1898 | i915_gem_retire_requests_ring(dev, ring); |
673a394b EA |
1899 | |
1900 | return ret; | |
1901 | } | |
1902 | ||
48764bf4 DV |
1903 | /** |
1904 | * Waits for a sequence number to be signaled, and cleans up the | |
1905 | * request and object lists appropriately for that event. | |
1906 | */ | |
1907 | static int | |
852835f3 ZN |
1908 | i915_wait_request(struct drm_device *dev, uint32_t seqno, |
1909 | struct intel_ring_buffer *ring) | |
48764bf4 | 1910 | { |
852835f3 | 1911 | return i915_do_wait_request(dev, seqno, 1, ring); |
48764bf4 DV |
1912 | } |
1913 | ||
8187a2b7 ZN |
1914 | static void |
1915 | i915_gem_flush(struct drm_device *dev, | |
1916 | uint32_t invalidate_domains, | |
1917 | uint32_t flush_domains) | |
1918 | { | |
1919 | drm_i915_private_t *dev_priv = dev->dev_private; | |
8bff917c | 1920 | |
8187a2b7 ZN |
1921 | if (flush_domains & I915_GEM_DOMAIN_CPU) |
1922 | drm_agp_chipset_flush(dev); | |
8bff917c | 1923 | |
8187a2b7 ZN |
1924 | dev_priv->render_ring.flush(dev, &dev_priv->render_ring, |
1925 | invalidate_domains, | |
1926 | flush_domains); | |
d1b851fc ZN |
1927 | |
1928 | if (HAS_BSD(dev)) | |
1929 | dev_priv->bsd_ring.flush(dev, &dev_priv->bsd_ring, | |
1930 | invalidate_domains, | |
1931 | flush_domains); | |
8187a2b7 ZN |
1932 | } |
1933 | ||
673a394b EA |
1934 | /** |
1935 | * Ensures that all rendering to the object has completed and the object is | |
1936 | * safe to unbind from the GTT or access from the CPU. | |
1937 | */ | |
1938 | static int | |
ba3d8d74 | 1939 | i915_gem_object_wait_rendering(struct drm_gem_object *obj) |
673a394b EA |
1940 | { |
1941 | struct drm_device *dev = obj->dev; | |
23010e43 | 1942 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
673a394b EA |
1943 | int ret; |
1944 | ||
e47c68e9 EA |
1945 | /* This function only exists to support waiting for existing rendering, |
1946 | * not for emitting required flushes. | |
673a394b | 1947 | */ |
e47c68e9 | 1948 | BUG_ON((obj->write_domain & I915_GEM_GPU_DOMAINS) != 0); |
673a394b EA |
1949 | |
1950 | /* If there is rendering queued on the buffer being evicted, wait for | |
1951 | * it. | |
1952 | */ | |
1953 | if (obj_priv->active) { | |
1954 | #if WATCH_BUF | |
1955 | DRM_INFO("%s: object %p wait for seqno %08x\n", | |
1956 | __func__, obj, obj_priv->last_rendering_seqno); | |
1957 | #endif | |
ba3d8d74 DV |
1958 | ret = i915_wait_request(dev, |
1959 | obj_priv->last_rendering_seqno, | |
1960 | obj_priv->ring); | |
673a394b EA |
1961 | if (ret != 0) |
1962 | return ret; | |
1963 | } | |
1964 | ||
1965 | return 0; | |
1966 | } | |
1967 | ||
1968 | /** | |
1969 | * Unbinds an object from the GTT aperture. | |
1970 | */ | |
0f973f27 | 1971 | int |
673a394b EA |
1972 | i915_gem_object_unbind(struct drm_gem_object *obj) |
1973 | { | |
1974 | struct drm_device *dev = obj->dev; | |
4a87b8ca | 1975 | drm_i915_private_t *dev_priv = dev->dev_private; |
23010e43 | 1976 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
673a394b EA |
1977 | int ret = 0; |
1978 | ||
1979 | #if WATCH_BUF | |
1980 | DRM_INFO("%s:%d %p\n", __func__, __LINE__, obj); | |
1981 | DRM_INFO("gtt_space %p\n", obj_priv->gtt_space); | |
1982 | #endif | |
1983 | if (obj_priv->gtt_space == NULL) | |
1984 | return 0; | |
1985 | ||
1986 | if (obj_priv->pin_count != 0) { | |
1987 | DRM_ERROR("Attempting to unbind pinned buffer\n"); | |
1988 | return -EINVAL; | |
1989 | } | |
1990 | ||
5323fd04 EA |
1991 | /* blow away mappings if mapped through GTT */ |
1992 | i915_gem_release_mmap(obj); | |
1993 | ||
673a394b EA |
1994 | /* Move the object to the CPU domain to ensure that |
1995 | * any possible CPU writes while it's not in the GTT | |
1996 | * are flushed when we go to remap it. This will | |
1997 | * also ensure that all pending GPU writes are finished | |
1998 | * before we unbind. | |
1999 | */ | |
e47c68e9 | 2000 | ret = i915_gem_object_set_to_cpu_domain(obj, 1); |
8dc1775d | 2001 | if (ret == -ERESTARTSYS) |
673a394b | 2002 | return ret; |
8dc1775d CW |
2003 | /* Continue on if we fail due to EIO, the GPU is hung so we |
2004 | * should be safe and we need to cleanup or else we might | |
2005 | * cause memory corruption through use-after-free. | |
2006 | */ | |
673a394b | 2007 | |
96b47b65 DV |
2008 | /* release the fence reg _after_ flushing */ |
2009 | if (obj_priv->fence_reg != I915_FENCE_REG_NONE) | |
2010 | i915_gem_clear_fence_reg(obj); | |
2011 | ||
673a394b EA |
2012 | if (obj_priv->agp_mem != NULL) { |
2013 | drm_unbind_agp(obj_priv->agp_mem); | |
2014 | drm_free_agp(obj_priv->agp_mem, obj->size / PAGE_SIZE); | |
2015 | obj_priv->agp_mem = NULL; | |
2016 | } | |
2017 | ||
856fa198 | 2018 | i915_gem_object_put_pages(obj); |
a32808c0 | 2019 | BUG_ON(obj_priv->pages_refcount); |
673a394b EA |
2020 | |
2021 | if (obj_priv->gtt_space) { | |
2022 | atomic_dec(&dev->gtt_count); | |
2023 | atomic_sub(obj->size, &dev->gtt_memory); | |
2024 | ||
2025 | drm_mm_put_block(obj_priv->gtt_space); | |
2026 | obj_priv->gtt_space = NULL; | |
2027 | } | |
2028 | ||
2029 | /* Remove ourselves from the LRU list if present. */ | |
4a87b8ca | 2030 | spin_lock(&dev_priv->mm.active_list_lock); |
673a394b EA |
2031 | if (!list_empty(&obj_priv->list)) |
2032 | list_del_init(&obj_priv->list); | |
4a87b8ca | 2033 | spin_unlock(&dev_priv->mm.active_list_lock); |
673a394b | 2034 | |
963b4836 CW |
2035 | if (i915_gem_object_is_purgeable(obj_priv)) |
2036 | i915_gem_object_truncate(obj); | |
2037 | ||
1c5d22f7 CW |
2038 | trace_i915_gem_object_unbind(obj); |
2039 | ||
8dc1775d | 2040 | return ret; |
673a394b EA |
2041 | } |
2042 | ||
b47eb4a2 | 2043 | int |
4df2faf4 DV |
2044 | i915_gpu_idle(struct drm_device *dev) |
2045 | { | |
2046 | drm_i915_private_t *dev_priv = dev->dev_private; | |
2047 | bool lists_empty; | |
852835f3 | 2048 | int ret; |
4df2faf4 DV |
2049 | |
2050 | spin_lock(&dev_priv->mm.active_list_lock); | |
d1b851fc ZN |
2051 | lists_empty = (list_empty(&dev_priv->mm.flushing_list) && |
2052 | list_empty(&dev_priv->render_ring.active_list) && | |
2053 | (!HAS_BSD(dev) || | |
2054 | list_empty(&dev_priv->bsd_ring.active_list))); | |
4df2faf4 DV |
2055 | spin_unlock(&dev_priv->mm.active_list_lock); |
2056 | ||
2057 | if (lists_empty) | |
2058 | return 0; | |
2059 | ||
2060 | /* Flush everything onto the inactive list. */ | |
2061 | i915_gem_flush(dev, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS); | |
4fc6ee76 DV |
2062 | |
2063 | ret = i915_wait_request(dev, | |
2064 | i915_gem_next_request_seqno(dev, &dev_priv->render_ring), | |
2065 | &dev_priv->render_ring); | |
8a1a49f9 DV |
2066 | if (ret) |
2067 | return ret; | |
d1b851fc ZN |
2068 | |
2069 | if (HAS_BSD(dev)) { | |
4fc6ee76 DV |
2070 | ret = i915_wait_request(dev, |
2071 | i915_gem_next_request_seqno(dev, &dev_priv->bsd_ring), | |
2072 | &dev_priv->bsd_ring); | |
d1b851fc ZN |
2073 | if (ret) |
2074 | return ret; | |
2075 | } | |
2076 | ||
8a1a49f9 | 2077 | return 0; |
4df2faf4 DV |
2078 | } |
2079 | ||
6911a9b8 | 2080 | int |
4bdadb97 CW |
2081 | i915_gem_object_get_pages(struct drm_gem_object *obj, |
2082 | gfp_t gfpmask) | |
673a394b | 2083 | { |
23010e43 | 2084 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
673a394b EA |
2085 | int page_count, i; |
2086 | struct address_space *mapping; | |
2087 | struct inode *inode; | |
2088 | struct page *page; | |
673a394b | 2089 | |
778c3544 DV |
2090 | BUG_ON(obj_priv->pages_refcount |
2091 | == DRM_I915_GEM_OBJECT_MAX_PAGES_REFCOUNT); | |
2092 | ||
856fa198 | 2093 | if (obj_priv->pages_refcount++ != 0) |
673a394b EA |
2094 | return 0; |
2095 | ||
2096 | /* Get the list of pages out of our struct file. They'll be pinned | |
2097 | * at this point until we release them. | |
2098 | */ | |
2099 | page_count = obj->size / PAGE_SIZE; | |
856fa198 | 2100 | BUG_ON(obj_priv->pages != NULL); |
8e7d2b2c | 2101 | obj_priv->pages = drm_calloc_large(page_count, sizeof(struct page *)); |
856fa198 | 2102 | if (obj_priv->pages == NULL) { |
856fa198 | 2103 | obj_priv->pages_refcount--; |
673a394b EA |
2104 | return -ENOMEM; |
2105 | } | |
2106 | ||
2107 | inode = obj->filp->f_path.dentry->d_inode; | |
2108 | mapping = inode->i_mapping; | |
2109 | for (i = 0; i < page_count; i++) { | |
4bdadb97 | 2110 | page = read_cache_page_gfp(mapping, i, |
985b823b | 2111 | GFP_HIGHUSER | |
4bdadb97 | 2112 | __GFP_COLD | |
cd9f040d | 2113 | __GFP_RECLAIMABLE | |
4bdadb97 | 2114 | gfpmask); |
1f2b1013 CW |
2115 | if (IS_ERR(page)) |
2116 | goto err_pages; | |
2117 | ||
856fa198 | 2118 | obj_priv->pages[i] = page; |
673a394b | 2119 | } |
280b713b EA |
2120 | |
2121 | if (obj_priv->tiling_mode != I915_TILING_NONE) | |
2122 | i915_gem_object_do_bit_17_swizzle(obj); | |
2123 | ||
673a394b | 2124 | return 0; |
1f2b1013 CW |
2125 | |
2126 | err_pages: | |
2127 | while (i--) | |
2128 | page_cache_release(obj_priv->pages[i]); | |
2129 | ||
2130 | drm_free_large(obj_priv->pages); | |
2131 | obj_priv->pages = NULL; | |
2132 | obj_priv->pages_refcount--; | |
2133 | return PTR_ERR(page); | |
673a394b EA |
2134 | } |
2135 | ||
4e901fdc EA |
2136 | static void sandybridge_write_fence_reg(struct drm_i915_fence_reg *reg) |
2137 | { | |
2138 | struct drm_gem_object *obj = reg->obj; | |
2139 | struct drm_device *dev = obj->dev; | |
2140 | drm_i915_private_t *dev_priv = dev->dev_private; | |
23010e43 | 2141 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
4e901fdc EA |
2142 | int regnum = obj_priv->fence_reg; |
2143 | uint64_t val; | |
2144 | ||
2145 | val = (uint64_t)((obj_priv->gtt_offset + obj->size - 4096) & | |
2146 | 0xfffff000) << 32; | |
2147 | val |= obj_priv->gtt_offset & 0xfffff000; | |
2148 | val |= (uint64_t)((obj_priv->stride / 128) - 1) << | |
2149 | SANDYBRIDGE_FENCE_PITCH_SHIFT; | |
2150 | ||
2151 | if (obj_priv->tiling_mode == I915_TILING_Y) | |
2152 | val |= 1 << I965_FENCE_TILING_Y_SHIFT; | |
2153 | val |= I965_FENCE_REG_VALID; | |
2154 | ||
2155 | I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + (regnum * 8), val); | |
2156 | } | |
2157 | ||
de151cf6 JB |
2158 | static void i965_write_fence_reg(struct drm_i915_fence_reg *reg) |
2159 | { | |
2160 | struct drm_gem_object *obj = reg->obj; | |
2161 | struct drm_device *dev = obj->dev; | |
2162 | drm_i915_private_t *dev_priv = dev->dev_private; | |
23010e43 | 2163 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
de151cf6 JB |
2164 | int regnum = obj_priv->fence_reg; |
2165 | uint64_t val; | |
2166 | ||
2167 | val = (uint64_t)((obj_priv->gtt_offset + obj->size - 4096) & | |
2168 | 0xfffff000) << 32; | |
2169 | val |= obj_priv->gtt_offset & 0xfffff000; | |
2170 | val |= ((obj_priv->stride / 128) - 1) << I965_FENCE_PITCH_SHIFT; | |
2171 | if (obj_priv->tiling_mode == I915_TILING_Y) | |
2172 | val |= 1 << I965_FENCE_TILING_Y_SHIFT; | |
2173 | val |= I965_FENCE_REG_VALID; | |
2174 | ||
2175 | I915_WRITE64(FENCE_REG_965_0 + (regnum * 8), val); | |
2176 | } | |
2177 | ||
2178 | static void i915_write_fence_reg(struct drm_i915_fence_reg *reg) | |
2179 | { | |
2180 | struct drm_gem_object *obj = reg->obj; | |
2181 | struct drm_device *dev = obj->dev; | |
2182 | drm_i915_private_t *dev_priv = dev->dev_private; | |
23010e43 | 2183 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
de151cf6 | 2184 | int regnum = obj_priv->fence_reg; |
0f973f27 | 2185 | int tile_width; |
dc529a4f | 2186 | uint32_t fence_reg, val; |
de151cf6 JB |
2187 | uint32_t pitch_val; |
2188 | ||
2189 | if ((obj_priv->gtt_offset & ~I915_FENCE_START_MASK) || | |
2190 | (obj_priv->gtt_offset & (obj->size - 1))) { | |
f06da264 | 2191 | WARN(1, "%s: object 0x%08x not 1M or size (0x%zx) aligned\n", |
0f973f27 | 2192 | __func__, obj_priv->gtt_offset, obj->size); |
de151cf6 JB |
2193 | return; |
2194 | } | |
2195 | ||
0f973f27 JB |
2196 | if (obj_priv->tiling_mode == I915_TILING_Y && |
2197 | HAS_128_BYTE_Y_TILING(dev)) | |
2198 | tile_width = 128; | |
de151cf6 | 2199 | else |
0f973f27 JB |
2200 | tile_width = 512; |
2201 | ||
2202 | /* Note: pitch better be a power of two tile widths */ | |
2203 | pitch_val = obj_priv->stride / tile_width; | |
2204 | pitch_val = ffs(pitch_val) - 1; | |
de151cf6 | 2205 | |
c36a2a6d DV |
2206 | if (obj_priv->tiling_mode == I915_TILING_Y && |
2207 | HAS_128_BYTE_Y_TILING(dev)) | |
2208 | WARN_ON(pitch_val > I830_FENCE_MAX_PITCH_VAL); | |
2209 | else | |
2210 | WARN_ON(pitch_val > I915_FENCE_MAX_PITCH_VAL); | |
2211 | ||
de151cf6 JB |
2212 | val = obj_priv->gtt_offset; |
2213 | if (obj_priv->tiling_mode == I915_TILING_Y) | |
2214 | val |= 1 << I830_FENCE_TILING_Y_SHIFT; | |
2215 | val |= I915_FENCE_SIZE_BITS(obj->size); | |
2216 | val |= pitch_val << I830_FENCE_PITCH_SHIFT; | |
2217 | val |= I830_FENCE_REG_VALID; | |
2218 | ||
dc529a4f EA |
2219 | if (regnum < 8) |
2220 | fence_reg = FENCE_REG_830_0 + (regnum * 4); | |
2221 | else | |
2222 | fence_reg = FENCE_REG_945_8 + ((regnum - 8) * 4); | |
2223 | I915_WRITE(fence_reg, val); | |
de151cf6 JB |
2224 | } |
2225 | ||
2226 | static void i830_write_fence_reg(struct drm_i915_fence_reg *reg) | |
2227 | { | |
2228 | struct drm_gem_object *obj = reg->obj; | |
2229 | struct drm_device *dev = obj->dev; | |
2230 | drm_i915_private_t *dev_priv = dev->dev_private; | |
23010e43 | 2231 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
de151cf6 JB |
2232 | int regnum = obj_priv->fence_reg; |
2233 | uint32_t val; | |
2234 | uint32_t pitch_val; | |
8d7773a3 | 2235 | uint32_t fence_size_bits; |
de151cf6 | 2236 | |
8d7773a3 | 2237 | if ((obj_priv->gtt_offset & ~I830_FENCE_START_MASK) || |
de151cf6 | 2238 | (obj_priv->gtt_offset & (obj->size - 1))) { |
8d7773a3 | 2239 | WARN(1, "%s: object 0x%08x not 512K or size aligned\n", |
0f973f27 | 2240 | __func__, obj_priv->gtt_offset); |
de151cf6 JB |
2241 | return; |
2242 | } | |
2243 | ||
e76a16de EA |
2244 | pitch_val = obj_priv->stride / 128; |
2245 | pitch_val = ffs(pitch_val) - 1; | |
2246 | WARN_ON(pitch_val > I830_FENCE_MAX_PITCH_VAL); | |
2247 | ||
de151cf6 JB |
2248 | val = obj_priv->gtt_offset; |
2249 | if (obj_priv->tiling_mode == I915_TILING_Y) | |
2250 | val |= 1 << I830_FENCE_TILING_Y_SHIFT; | |
8d7773a3 DV |
2251 | fence_size_bits = I830_FENCE_SIZE_BITS(obj->size); |
2252 | WARN_ON(fence_size_bits & ~0x00000f00); | |
2253 | val |= fence_size_bits; | |
de151cf6 JB |
2254 | val |= pitch_val << I830_FENCE_PITCH_SHIFT; |
2255 | val |= I830_FENCE_REG_VALID; | |
2256 | ||
2257 | I915_WRITE(FENCE_REG_830_0 + (regnum * 4), val); | |
de151cf6 JB |
2258 | } |
2259 | ||
ae3db24a DV |
2260 | static int i915_find_fence_reg(struct drm_device *dev) |
2261 | { | |
2262 | struct drm_i915_fence_reg *reg = NULL; | |
2263 | struct drm_i915_gem_object *obj_priv = NULL; | |
2264 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2265 | struct drm_gem_object *obj = NULL; | |
2266 | int i, avail, ret; | |
2267 | ||
2268 | /* First try to find a free reg */ | |
2269 | avail = 0; | |
2270 | for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) { | |
2271 | reg = &dev_priv->fence_regs[i]; | |
2272 | if (!reg->obj) | |
2273 | return i; | |
2274 | ||
23010e43 | 2275 | obj_priv = to_intel_bo(reg->obj); |
ae3db24a DV |
2276 | if (!obj_priv->pin_count) |
2277 | avail++; | |
2278 | } | |
2279 | ||
2280 | if (avail == 0) | |
2281 | return -ENOSPC; | |
2282 | ||
2283 | /* None available, try to steal one or wait for a user to finish */ | |
2284 | i = I915_FENCE_REG_NONE; | |
007cc8ac DV |
2285 | list_for_each_entry(reg, &dev_priv->mm.fence_list, |
2286 | lru_list) { | |
2287 | obj = reg->obj; | |
2288 | obj_priv = to_intel_bo(obj); | |
ae3db24a DV |
2289 | |
2290 | if (obj_priv->pin_count) | |
2291 | continue; | |
2292 | ||
2293 | /* found one! */ | |
2294 | i = obj_priv->fence_reg; | |
2295 | break; | |
2296 | } | |
2297 | ||
2298 | BUG_ON(i == I915_FENCE_REG_NONE); | |
2299 | ||
2300 | /* We only have a reference on obj from the active list. put_fence_reg | |
2301 | * might drop that one, causing a use-after-free in it. So hold a | |
2302 | * private reference to obj like the other callers of put_fence_reg | |
2303 | * (set_tiling ioctl) do. */ | |
2304 | drm_gem_object_reference(obj); | |
2305 | ret = i915_gem_object_put_fence_reg(obj); | |
2306 | drm_gem_object_unreference(obj); | |
2307 | if (ret != 0) | |
2308 | return ret; | |
2309 | ||
2310 | return i; | |
2311 | } | |
2312 | ||
de151cf6 JB |
2313 | /** |
2314 | * i915_gem_object_get_fence_reg - set up a fence reg for an object | |
2315 | * @obj: object to map through a fence reg | |
2316 | * | |
2317 | * When mapping objects through the GTT, userspace wants to be able to write | |
2318 | * to them without having to worry about swizzling if the object is tiled. | |
2319 | * | |
2320 | * This function walks the fence regs looking for a free one for @obj, | |
2321 | * stealing one if it can't find any. | |
2322 | * | |
2323 | * It then sets up the reg based on the object's properties: address, pitch | |
2324 | * and tiling format. | |
2325 | */ | |
8c4b8c3f CW |
2326 | int |
2327 | i915_gem_object_get_fence_reg(struct drm_gem_object *obj) | |
de151cf6 JB |
2328 | { |
2329 | struct drm_device *dev = obj->dev; | |
79e53945 | 2330 | struct drm_i915_private *dev_priv = dev->dev_private; |
23010e43 | 2331 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
de151cf6 | 2332 | struct drm_i915_fence_reg *reg = NULL; |
ae3db24a | 2333 | int ret; |
de151cf6 | 2334 | |
a09ba7fa EA |
2335 | /* Just update our place in the LRU if our fence is getting used. */ |
2336 | if (obj_priv->fence_reg != I915_FENCE_REG_NONE) { | |
007cc8ac DV |
2337 | reg = &dev_priv->fence_regs[obj_priv->fence_reg]; |
2338 | list_move_tail(®->lru_list, &dev_priv->mm.fence_list); | |
a09ba7fa EA |
2339 | return 0; |
2340 | } | |
2341 | ||
de151cf6 JB |
2342 | switch (obj_priv->tiling_mode) { |
2343 | case I915_TILING_NONE: | |
2344 | WARN(1, "allocating a fence for non-tiled object?\n"); | |
2345 | break; | |
2346 | case I915_TILING_X: | |
0f973f27 JB |
2347 | if (!obj_priv->stride) |
2348 | return -EINVAL; | |
2349 | WARN((obj_priv->stride & (512 - 1)), | |
2350 | "object 0x%08x is X tiled but has non-512B pitch\n", | |
2351 | obj_priv->gtt_offset); | |
de151cf6 JB |
2352 | break; |
2353 | case I915_TILING_Y: | |
0f973f27 JB |
2354 | if (!obj_priv->stride) |
2355 | return -EINVAL; | |
2356 | WARN((obj_priv->stride & (128 - 1)), | |
2357 | "object 0x%08x is Y tiled but has non-128B pitch\n", | |
2358 | obj_priv->gtt_offset); | |
de151cf6 JB |
2359 | break; |
2360 | } | |
2361 | ||
ae3db24a DV |
2362 | ret = i915_find_fence_reg(dev); |
2363 | if (ret < 0) | |
2364 | return ret; | |
de151cf6 | 2365 | |
ae3db24a DV |
2366 | obj_priv->fence_reg = ret; |
2367 | reg = &dev_priv->fence_regs[obj_priv->fence_reg]; | |
007cc8ac | 2368 | list_add_tail(®->lru_list, &dev_priv->mm.fence_list); |
a09ba7fa | 2369 | |
de151cf6 JB |
2370 | reg->obj = obj; |
2371 | ||
4e901fdc EA |
2372 | if (IS_GEN6(dev)) |
2373 | sandybridge_write_fence_reg(reg); | |
2374 | else if (IS_I965G(dev)) | |
de151cf6 JB |
2375 | i965_write_fence_reg(reg); |
2376 | else if (IS_I9XX(dev)) | |
2377 | i915_write_fence_reg(reg); | |
2378 | else | |
2379 | i830_write_fence_reg(reg); | |
d9ddcb96 | 2380 | |
ae3db24a DV |
2381 | trace_i915_gem_object_get_fence(obj, obj_priv->fence_reg, |
2382 | obj_priv->tiling_mode); | |
1c5d22f7 | 2383 | |
d9ddcb96 | 2384 | return 0; |
de151cf6 JB |
2385 | } |
2386 | ||
2387 | /** | |
2388 | * i915_gem_clear_fence_reg - clear out fence register info | |
2389 | * @obj: object to clear | |
2390 | * | |
2391 | * Zeroes out the fence register itself and clears out the associated | |
2392 | * data structures in dev_priv and obj_priv. | |
2393 | */ | |
2394 | static void | |
2395 | i915_gem_clear_fence_reg(struct drm_gem_object *obj) | |
2396 | { | |
2397 | struct drm_device *dev = obj->dev; | |
79e53945 | 2398 | drm_i915_private_t *dev_priv = dev->dev_private; |
23010e43 | 2399 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
007cc8ac DV |
2400 | struct drm_i915_fence_reg *reg = |
2401 | &dev_priv->fence_regs[obj_priv->fence_reg]; | |
de151cf6 | 2402 | |
4e901fdc EA |
2403 | if (IS_GEN6(dev)) { |
2404 | I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + | |
2405 | (obj_priv->fence_reg * 8), 0); | |
2406 | } else if (IS_I965G(dev)) { | |
de151cf6 | 2407 | I915_WRITE64(FENCE_REG_965_0 + (obj_priv->fence_reg * 8), 0); |
4e901fdc | 2408 | } else { |
dc529a4f EA |
2409 | uint32_t fence_reg; |
2410 | ||
2411 | if (obj_priv->fence_reg < 8) | |
2412 | fence_reg = FENCE_REG_830_0 + obj_priv->fence_reg * 4; | |
2413 | else | |
2414 | fence_reg = FENCE_REG_945_8 + (obj_priv->fence_reg - | |
2415 | 8) * 4; | |
2416 | ||
2417 | I915_WRITE(fence_reg, 0); | |
2418 | } | |
de151cf6 | 2419 | |
007cc8ac | 2420 | reg->obj = NULL; |
de151cf6 | 2421 | obj_priv->fence_reg = I915_FENCE_REG_NONE; |
007cc8ac | 2422 | list_del_init(®->lru_list); |
de151cf6 JB |
2423 | } |
2424 | ||
52dc7d32 CW |
2425 | /** |
2426 | * i915_gem_object_put_fence_reg - waits on outstanding fenced access | |
2427 | * to the buffer to finish, and then resets the fence register. | |
2428 | * @obj: tiled object holding a fence register. | |
2429 | * | |
2430 | * Zeroes out the fence register itself and clears out the associated | |
2431 | * data structures in dev_priv and obj_priv. | |
2432 | */ | |
2433 | int | |
2434 | i915_gem_object_put_fence_reg(struct drm_gem_object *obj) | |
2435 | { | |
2436 | struct drm_device *dev = obj->dev; | |
23010e43 | 2437 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
52dc7d32 CW |
2438 | |
2439 | if (obj_priv->fence_reg == I915_FENCE_REG_NONE) | |
2440 | return 0; | |
2441 | ||
10ae9bd2 DV |
2442 | /* If we've changed tiling, GTT-mappings of the object |
2443 | * need to re-fault to ensure that the correct fence register | |
2444 | * setup is in place. | |
2445 | */ | |
2446 | i915_gem_release_mmap(obj); | |
2447 | ||
52dc7d32 CW |
2448 | /* On the i915, GPU access to tiled buffers is via a fence, |
2449 | * therefore we must wait for any outstanding access to complete | |
2450 | * before clearing the fence. | |
2451 | */ | |
2452 | if (!IS_I965G(dev)) { | |
2453 | int ret; | |
2454 | ||
ba3d8d74 | 2455 | ret = i915_gem_object_flush_gpu_write_domain(obj, false); |
52dc7d32 CW |
2456 | if (ret != 0) |
2457 | return ret; | |
2458 | } | |
2459 | ||
4a726612 | 2460 | i915_gem_object_flush_gtt_write_domain(obj); |
52dc7d32 CW |
2461 | i915_gem_clear_fence_reg (obj); |
2462 | ||
2463 | return 0; | |
2464 | } | |
2465 | ||
673a394b EA |
2466 | /** |
2467 | * Finds free space in the GTT aperture and binds the object there. | |
2468 | */ | |
2469 | static int | |
2470 | i915_gem_object_bind_to_gtt(struct drm_gem_object *obj, unsigned alignment) | |
2471 | { | |
2472 | struct drm_device *dev = obj->dev; | |
2473 | drm_i915_private_t *dev_priv = dev->dev_private; | |
23010e43 | 2474 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
673a394b | 2475 | struct drm_mm_node *free_space; |
4bdadb97 | 2476 | gfp_t gfpmask = __GFP_NORETRY | __GFP_NOWARN; |
07f73f69 | 2477 | int ret; |
673a394b | 2478 | |
bb6baf76 | 2479 | if (obj_priv->madv != I915_MADV_WILLNEED) { |
3ef94daa CW |
2480 | DRM_ERROR("Attempting to bind a purgeable object\n"); |
2481 | return -EINVAL; | |
2482 | } | |
2483 | ||
673a394b | 2484 | if (alignment == 0) |
0f973f27 | 2485 | alignment = i915_gem_get_gtt_alignment(obj); |
8d7773a3 | 2486 | if (alignment & (i915_gem_get_gtt_alignment(obj) - 1)) { |
673a394b EA |
2487 | DRM_ERROR("Invalid object alignment requested %u\n", alignment); |
2488 | return -EINVAL; | |
2489 | } | |
2490 | ||
654fc607 CW |
2491 | /* If the object is bigger than the entire aperture, reject it early |
2492 | * before evicting everything in a vain attempt to find space. | |
2493 | */ | |
2494 | if (obj->size > dev->gtt_total) { | |
2495 | DRM_ERROR("Attempting to bind an object larger than the aperture\n"); | |
2496 | return -E2BIG; | |
2497 | } | |
2498 | ||
673a394b EA |
2499 | search_free: |
2500 | free_space = drm_mm_search_free(&dev_priv->mm.gtt_space, | |
2501 | obj->size, alignment, 0); | |
2502 | if (free_space != NULL) { | |
2503 | obj_priv->gtt_space = drm_mm_get_block(free_space, obj->size, | |
2504 | alignment); | |
db3307a9 | 2505 | if (obj_priv->gtt_space != NULL) |
673a394b | 2506 | obj_priv->gtt_offset = obj_priv->gtt_space->start; |
673a394b EA |
2507 | } |
2508 | if (obj_priv->gtt_space == NULL) { | |
2509 | /* If the gtt is empty and we're still having trouble | |
2510 | * fitting our object in, we're out of memory. | |
2511 | */ | |
2512 | #if WATCH_LRU | |
2513 | DRM_INFO("%s: GTT full, evicting something\n", __func__); | |
2514 | #endif | |
0108a3ed | 2515 | ret = i915_gem_evict_something(dev, obj->size, alignment); |
9731129c | 2516 | if (ret) |
673a394b | 2517 | return ret; |
9731129c | 2518 | |
673a394b EA |
2519 | goto search_free; |
2520 | } | |
2521 | ||
2522 | #if WATCH_BUF | |
cfd43c02 | 2523 | DRM_INFO("Binding object of size %zd at 0x%08x\n", |
673a394b EA |
2524 | obj->size, obj_priv->gtt_offset); |
2525 | #endif | |
4bdadb97 | 2526 | ret = i915_gem_object_get_pages(obj, gfpmask); |
673a394b EA |
2527 | if (ret) { |
2528 | drm_mm_put_block(obj_priv->gtt_space); | |
2529 | obj_priv->gtt_space = NULL; | |
07f73f69 CW |
2530 | |
2531 | if (ret == -ENOMEM) { | |
2532 | /* first try to clear up some space from the GTT */ | |
0108a3ed DV |
2533 | ret = i915_gem_evict_something(dev, obj->size, |
2534 | alignment); | |
07f73f69 | 2535 | if (ret) { |
07f73f69 | 2536 | /* now try to shrink everyone else */ |
4bdadb97 CW |
2537 | if (gfpmask) { |
2538 | gfpmask = 0; | |
2539 | goto search_free; | |
07f73f69 CW |
2540 | } |
2541 | ||
2542 | return ret; | |
2543 | } | |
2544 | ||
2545 | goto search_free; | |
2546 | } | |
2547 | ||
673a394b EA |
2548 | return ret; |
2549 | } | |
2550 | ||
673a394b EA |
2551 | /* Create an AGP memory structure pointing at our pages, and bind it |
2552 | * into the GTT. | |
2553 | */ | |
2554 | obj_priv->agp_mem = drm_agp_bind_pages(dev, | |
856fa198 | 2555 | obj_priv->pages, |
07f73f69 | 2556 | obj->size >> PAGE_SHIFT, |
ba1eb1d8 KP |
2557 | obj_priv->gtt_offset, |
2558 | obj_priv->agp_type); | |
673a394b | 2559 | if (obj_priv->agp_mem == NULL) { |
856fa198 | 2560 | i915_gem_object_put_pages(obj); |
673a394b EA |
2561 | drm_mm_put_block(obj_priv->gtt_space); |
2562 | obj_priv->gtt_space = NULL; | |
07f73f69 | 2563 | |
0108a3ed | 2564 | ret = i915_gem_evict_something(dev, obj->size, alignment); |
9731129c | 2565 | if (ret) |
07f73f69 | 2566 | return ret; |
07f73f69 CW |
2567 | |
2568 | goto search_free; | |
673a394b EA |
2569 | } |
2570 | atomic_inc(&dev->gtt_count); | |
2571 | atomic_add(obj->size, &dev->gtt_memory); | |
2572 | ||
bf1a1092 CW |
2573 | /* keep track of bounds object by adding it to the inactive list */ |
2574 | list_add_tail(&obj_priv->list, &dev_priv->mm.inactive_list); | |
2575 | ||
673a394b EA |
2576 | /* Assert that the object is not currently in any GPU domain. As it |
2577 | * wasn't in the GTT, there shouldn't be any way it could have been in | |
2578 | * a GPU cache | |
2579 | */ | |
21d509e3 CW |
2580 | BUG_ON(obj->read_domains & I915_GEM_GPU_DOMAINS); |
2581 | BUG_ON(obj->write_domain & I915_GEM_GPU_DOMAINS); | |
673a394b | 2582 | |
1c5d22f7 CW |
2583 | trace_i915_gem_object_bind(obj, obj_priv->gtt_offset); |
2584 | ||
673a394b EA |
2585 | return 0; |
2586 | } | |
2587 | ||
2588 | void | |
2589 | i915_gem_clflush_object(struct drm_gem_object *obj) | |
2590 | { | |
23010e43 | 2591 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
673a394b EA |
2592 | |
2593 | /* If we don't have a page list set up, then we're not pinned | |
2594 | * to GPU, and we can ignore the cache flush because it'll happen | |
2595 | * again at bind time. | |
2596 | */ | |
856fa198 | 2597 | if (obj_priv->pages == NULL) |
673a394b EA |
2598 | return; |
2599 | ||
1c5d22f7 | 2600 | trace_i915_gem_object_clflush(obj); |
cfa16a0d | 2601 | |
856fa198 | 2602 | drm_clflush_pages(obj_priv->pages, obj->size / PAGE_SIZE); |
673a394b EA |
2603 | } |
2604 | ||
e47c68e9 | 2605 | /** Flushes any GPU write domain for the object if it's dirty. */ |
2dafb1e0 | 2606 | static int |
ba3d8d74 DV |
2607 | i915_gem_object_flush_gpu_write_domain(struct drm_gem_object *obj, |
2608 | bool pipelined) | |
e47c68e9 EA |
2609 | { |
2610 | struct drm_device *dev = obj->dev; | |
1c5d22f7 | 2611 | uint32_t old_write_domain; |
e47c68e9 EA |
2612 | |
2613 | if ((obj->write_domain & I915_GEM_GPU_DOMAINS) == 0) | |
2dafb1e0 | 2614 | return 0; |
e47c68e9 EA |
2615 | |
2616 | /* Queue the GPU write cache flushing we need. */ | |
1c5d22f7 | 2617 | old_write_domain = obj->write_domain; |
e47c68e9 | 2618 | i915_gem_flush(dev, 0, obj->write_domain); |
1c5d22f7 CW |
2619 | |
2620 | trace_i915_gem_object_change_domain(obj, | |
2621 | obj->read_domains, | |
2622 | old_write_domain); | |
ba3d8d74 DV |
2623 | |
2624 | if (pipelined) | |
2625 | return 0; | |
2626 | ||
2627 | return i915_gem_object_wait_rendering(obj); | |
e47c68e9 EA |
2628 | } |
2629 | ||
2630 | /** Flushes the GTT write domain for the object if it's dirty. */ | |
2631 | static void | |
2632 | i915_gem_object_flush_gtt_write_domain(struct drm_gem_object *obj) | |
2633 | { | |
1c5d22f7 CW |
2634 | uint32_t old_write_domain; |
2635 | ||
e47c68e9 EA |
2636 | if (obj->write_domain != I915_GEM_DOMAIN_GTT) |
2637 | return; | |
2638 | ||
2639 | /* No actual flushing is required for the GTT write domain. Writes | |
2640 | * to it immediately go to main memory as far as we know, so there's | |
2641 | * no chipset flush. It also doesn't land in render cache. | |
2642 | */ | |
1c5d22f7 | 2643 | old_write_domain = obj->write_domain; |
e47c68e9 | 2644 | obj->write_domain = 0; |
1c5d22f7 CW |
2645 | |
2646 | trace_i915_gem_object_change_domain(obj, | |
2647 | obj->read_domains, | |
2648 | old_write_domain); | |
e47c68e9 EA |
2649 | } |
2650 | ||
2651 | /** Flushes the CPU write domain for the object if it's dirty. */ | |
2652 | static void | |
2653 | i915_gem_object_flush_cpu_write_domain(struct drm_gem_object *obj) | |
2654 | { | |
2655 | struct drm_device *dev = obj->dev; | |
1c5d22f7 | 2656 | uint32_t old_write_domain; |
e47c68e9 EA |
2657 | |
2658 | if (obj->write_domain != I915_GEM_DOMAIN_CPU) | |
2659 | return; | |
2660 | ||
2661 | i915_gem_clflush_object(obj); | |
2662 | drm_agp_chipset_flush(dev); | |
1c5d22f7 | 2663 | old_write_domain = obj->write_domain; |
e47c68e9 | 2664 | obj->write_domain = 0; |
1c5d22f7 CW |
2665 | |
2666 | trace_i915_gem_object_change_domain(obj, | |
2667 | obj->read_domains, | |
2668 | old_write_domain); | |
e47c68e9 EA |
2669 | } |
2670 | ||
2dafb1e0 | 2671 | int |
6b95a207 KH |
2672 | i915_gem_object_flush_write_domain(struct drm_gem_object *obj) |
2673 | { | |
2dafb1e0 CW |
2674 | int ret = 0; |
2675 | ||
6b95a207 KH |
2676 | switch (obj->write_domain) { |
2677 | case I915_GEM_DOMAIN_GTT: | |
2678 | i915_gem_object_flush_gtt_write_domain(obj); | |
2679 | break; | |
2680 | case I915_GEM_DOMAIN_CPU: | |
2681 | i915_gem_object_flush_cpu_write_domain(obj); | |
2682 | break; | |
2683 | default: | |
ba3d8d74 | 2684 | ret = i915_gem_object_flush_gpu_write_domain(obj, true); |
6b95a207 KH |
2685 | break; |
2686 | } | |
2dafb1e0 CW |
2687 | |
2688 | return ret; | |
6b95a207 KH |
2689 | } |
2690 | ||
2ef7eeaa EA |
2691 | /** |
2692 | * Moves a single object to the GTT read, and possibly write domain. | |
2693 | * | |
2694 | * This function returns when the move is complete, including waiting on | |
2695 | * flushes to occur. | |
2696 | */ | |
79e53945 | 2697 | int |
2ef7eeaa EA |
2698 | i915_gem_object_set_to_gtt_domain(struct drm_gem_object *obj, int write) |
2699 | { | |
23010e43 | 2700 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
1c5d22f7 | 2701 | uint32_t old_write_domain, old_read_domains; |
e47c68e9 | 2702 | int ret; |
2ef7eeaa | 2703 | |
02354392 EA |
2704 | /* Not valid to be called on unbound objects. */ |
2705 | if (obj_priv->gtt_space == NULL) | |
2706 | return -EINVAL; | |
2707 | ||
ba3d8d74 | 2708 | ret = i915_gem_object_flush_gpu_write_domain(obj, false); |
e47c68e9 EA |
2709 | if (ret != 0) |
2710 | return ret; | |
2711 | ||
1c5d22f7 CW |
2712 | old_write_domain = obj->write_domain; |
2713 | old_read_domains = obj->read_domains; | |
2714 | ||
e47c68e9 EA |
2715 | /* If we're writing through the GTT domain, then CPU and GPU caches |
2716 | * will need to be invalidated at next use. | |
2ef7eeaa | 2717 | */ |
ba3d8d74 DV |
2718 | if (write) { |
2719 | ret = i915_gem_object_wait_rendering(obj); | |
2720 | if (ret) | |
2721 | return ret; | |
2722 | ||
e47c68e9 | 2723 | obj->read_domains &= I915_GEM_DOMAIN_GTT; |
ba3d8d74 | 2724 | } |
2ef7eeaa | 2725 | |
e47c68e9 | 2726 | i915_gem_object_flush_cpu_write_domain(obj); |
2ef7eeaa | 2727 | |
e47c68e9 EA |
2728 | /* It should now be out of any other write domains, and we can update |
2729 | * the domain values for our changes. | |
2730 | */ | |
2731 | BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_GTT) != 0); | |
2732 | obj->read_domains |= I915_GEM_DOMAIN_GTT; | |
2733 | if (write) { | |
2734 | obj->write_domain = I915_GEM_DOMAIN_GTT; | |
2735 | obj_priv->dirty = 1; | |
2ef7eeaa EA |
2736 | } |
2737 | ||
1c5d22f7 CW |
2738 | trace_i915_gem_object_change_domain(obj, |
2739 | old_read_domains, | |
2740 | old_write_domain); | |
2741 | ||
e47c68e9 EA |
2742 | return 0; |
2743 | } | |
2744 | ||
b9241ea3 ZW |
2745 | /* |
2746 | * Prepare buffer for display plane. Use uninterruptible for possible flush | |
2747 | * wait, as in modesetting process we're not supposed to be interrupted. | |
2748 | */ | |
2749 | int | |
2750 | i915_gem_object_set_to_display_plane(struct drm_gem_object *obj) | |
2751 | { | |
23010e43 | 2752 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
ba3d8d74 | 2753 | uint32_t old_read_domains; |
b9241ea3 ZW |
2754 | int ret; |
2755 | ||
2756 | /* Not valid to be called on unbound objects. */ | |
2757 | if (obj_priv->gtt_space == NULL) | |
2758 | return -EINVAL; | |
2759 | ||
ba3d8d74 | 2760 | ret = i915_gem_object_flush_gpu_write_domain(obj, true); |
e35a41de DV |
2761 | if (ret != 0) |
2762 | return ret; | |
b9241ea3 | 2763 | |
b118c1e3 CW |
2764 | i915_gem_object_flush_cpu_write_domain(obj); |
2765 | ||
b9241ea3 | 2766 | old_read_domains = obj->read_domains; |
b118c1e3 | 2767 | obj->read_domains = I915_GEM_DOMAIN_GTT; |
b9241ea3 ZW |
2768 | |
2769 | trace_i915_gem_object_change_domain(obj, | |
2770 | old_read_domains, | |
ba3d8d74 | 2771 | obj->write_domain); |
b9241ea3 ZW |
2772 | |
2773 | return 0; | |
2774 | } | |
2775 | ||
e47c68e9 EA |
2776 | /** |
2777 | * Moves a single object to the CPU read, and possibly write domain. | |
2778 | * | |
2779 | * This function returns when the move is complete, including waiting on | |
2780 | * flushes to occur. | |
2781 | */ | |
2782 | static int | |
2783 | i915_gem_object_set_to_cpu_domain(struct drm_gem_object *obj, int write) | |
2784 | { | |
1c5d22f7 | 2785 | uint32_t old_write_domain, old_read_domains; |
e47c68e9 EA |
2786 | int ret; |
2787 | ||
ba3d8d74 | 2788 | ret = i915_gem_object_flush_gpu_write_domain(obj, false); |
e47c68e9 EA |
2789 | if (ret != 0) |
2790 | return ret; | |
2ef7eeaa | 2791 | |
e47c68e9 | 2792 | i915_gem_object_flush_gtt_write_domain(obj); |
2ef7eeaa | 2793 | |
e47c68e9 EA |
2794 | /* If we have a partially-valid cache of the object in the CPU, |
2795 | * finish invalidating it and free the per-page flags. | |
2ef7eeaa | 2796 | */ |
e47c68e9 | 2797 | i915_gem_object_set_to_full_cpu_read_domain(obj); |
2ef7eeaa | 2798 | |
1c5d22f7 CW |
2799 | old_write_domain = obj->write_domain; |
2800 | old_read_domains = obj->read_domains; | |
2801 | ||
e47c68e9 EA |
2802 | /* Flush the CPU cache if it's still invalid. */ |
2803 | if ((obj->read_domains & I915_GEM_DOMAIN_CPU) == 0) { | |
2ef7eeaa | 2804 | i915_gem_clflush_object(obj); |
2ef7eeaa | 2805 | |
e47c68e9 | 2806 | obj->read_domains |= I915_GEM_DOMAIN_CPU; |
2ef7eeaa EA |
2807 | } |
2808 | ||
2809 | /* It should now be out of any other write domains, and we can update | |
2810 | * the domain values for our changes. | |
2811 | */ | |
e47c68e9 EA |
2812 | BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_CPU) != 0); |
2813 | ||
2814 | /* If we're writing through the CPU, then the GPU read domains will | |
2815 | * need to be invalidated at next use. | |
2816 | */ | |
2817 | if (write) { | |
ba3d8d74 DV |
2818 | ret = i915_gem_object_wait_rendering(obj); |
2819 | if (ret) | |
2820 | return ret; | |
2821 | ||
e47c68e9 EA |
2822 | obj->read_domains &= I915_GEM_DOMAIN_CPU; |
2823 | obj->write_domain = I915_GEM_DOMAIN_CPU; | |
2824 | } | |
2ef7eeaa | 2825 | |
1c5d22f7 CW |
2826 | trace_i915_gem_object_change_domain(obj, |
2827 | old_read_domains, | |
2828 | old_write_domain); | |
2829 | ||
2ef7eeaa EA |
2830 | return 0; |
2831 | } | |
2832 | ||
673a394b EA |
2833 | /* |
2834 | * Set the next domain for the specified object. This | |
2835 | * may not actually perform the necessary flushing/invaliding though, | |
2836 | * as that may want to be batched with other set_domain operations | |
2837 | * | |
2838 | * This is (we hope) the only really tricky part of gem. The goal | |
2839 | * is fairly simple -- track which caches hold bits of the object | |
2840 | * and make sure they remain coherent. A few concrete examples may | |
2841 | * help to explain how it works. For shorthand, we use the notation | |
2842 | * (read_domains, write_domain), e.g. (CPU, CPU) to indicate the | |
2843 | * a pair of read and write domain masks. | |
2844 | * | |
2845 | * Case 1: the batch buffer | |
2846 | * | |
2847 | * 1. Allocated | |
2848 | * 2. Written by CPU | |
2849 | * 3. Mapped to GTT | |
2850 | * 4. Read by GPU | |
2851 | * 5. Unmapped from GTT | |
2852 | * 6. Freed | |
2853 | * | |
2854 | * Let's take these a step at a time | |
2855 | * | |
2856 | * 1. Allocated | |
2857 | * Pages allocated from the kernel may still have | |
2858 | * cache contents, so we set them to (CPU, CPU) always. | |
2859 | * 2. Written by CPU (using pwrite) | |
2860 | * The pwrite function calls set_domain (CPU, CPU) and | |
2861 | * this function does nothing (as nothing changes) | |
2862 | * 3. Mapped by GTT | |
2863 | * This function asserts that the object is not | |
2864 | * currently in any GPU-based read or write domains | |
2865 | * 4. Read by GPU | |
2866 | * i915_gem_execbuffer calls set_domain (COMMAND, 0). | |
2867 | * As write_domain is zero, this function adds in the | |
2868 | * current read domains (CPU+COMMAND, 0). | |
2869 | * flush_domains is set to CPU. | |
2870 | * invalidate_domains is set to COMMAND | |
2871 | * clflush is run to get data out of the CPU caches | |
2872 | * then i915_dev_set_domain calls i915_gem_flush to | |
2873 | * emit an MI_FLUSH and drm_agp_chipset_flush | |
2874 | * 5. Unmapped from GTT | |
2875 | * i915_gem_object_unbind calls set_domain (CPU, CPU) | |
2876 | * flush_domains and invalidate_domains end up both zero | |
2877 | * so no flushing/invalidating happens | |
2878 | * 6. Freed | |
2879 | * yay, done | |
2880 | * | |
2881 | * Case 2: The shared render buffer | |
2882 | * | |
2883 | * 1. Allocated | |
2884 | * 2. Mapped to GTT | |
2885 | * 3. Read/written by GPU | |
2886 | * 4. set_domain to (CPU,CPU) | |
2887 | * 5. Read/written by CPU | |
2888 | * 6. Read/written by GPU | |
2889 | * | |
2890 | * 1. Allocated | |
2891 | * Same as last example, (CPU, CPU) | |
2892 | * 2. Mapped to GTT | |
2893 | * Nothing changes (assertions find that it is not in the GPU) | |
2894 | * 3. Read/written by GPU | |
2895 | * execbuffer calls set_domain (RENDER, RENDER) | |
2896 | * flush_domains gets CPU | |
2897 | * invalidate_domains gets GPU | |
2898 | * clflush (obj) | |
2899 | * MI_FLUSH and drm_agp_chipset_flush | |
2900 | * 4. set_domain (CPU, CPU) | |
2901 | * flush_domains gets GPU | |
2902 | * invalidate_domains gets CPU | |
2903 | * wait_rendering (obj) to make sure all drawing is complete. | |
2904 | * This will include an MI_FLUSH to get the data from GPU | |
2905 | * to memory | |
2906 | * clflush (obj) to invalidate the CPU cache | |
2907 | * Another MI_FLUSH in i915_gem_flush (eliminate this somehow?) | |
2908 | * 5. Read/written by CPU | |
2909 | * cache lines are loaded and dirtied | |
2910 | * 6. Read written by GPU | |
2911 | * Same as last GPU access | |
2912 | * | |
2913 | * Case 3: The constant buffer | |
2914 | * | |
2915 | * 1. Allocated | |
2916 | * 2. Written by CPU | |
2917 | * 3. Read by GPU | |
2918 | * 4. Updated (written) by CPU again | |
2919 | * 5. Read by GPU | |
2920 | * | |
2921 | * 1. Allocated | |
2922 | * (CPU, CPU) | |
2923 | * 2. Written by CPU | |
2924 | * (CPU, CPU) | |
2925 | * 3. Read by GPU | |
2926 | * (CPU+RENDER, 0) | |
2927 | * flush_domains = CPU | |
2928 | * invalidate_domains = RENDER | |
2929 | * clflush (obj) | |
2930 | * MI_FLUSH | |
2931 | * drm_agp_chipset_flush | |
2932 | * 4. Updated (written) by CPU again | |
2933 | * (CPU, CPU) | |
2934 | * flush_domains = 0 (no previous write domain) | |
2935 | * invalidate_domains = 0 (no new read domains) | |
2936 | * 5. Read by GPU | |
2937 | * (CPU+RENDER, 0) | |
2938 | * flush_domains = CPU | |
2939 | * invalidate_domains = RENDER | |
2940 | * clflush (obj) | |
2941 | * MI_FLUSH | |
2942 | * drm_agp_chipset_flush | |
2943 | */ | |
c0d90829 | 2944 | static void |
8b0e378a | 2945 | i915_gem_object_set_to_gpu_domain(struct drm_gem_object *obj) |
673a394b EA |
2946 | { |
2947 | struct drm_device *dev = obj->dev; | |
23010e43 | 2948 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
673a394b EA |
2949 | uint32_t invalidate_domains = 0; |
2950 | uint32_t flush_domains = 0; | |
1c5d22f7 | 2951 | uint32_t old_read_domains; |
e47c68e9 | 2952 | |
8b0e378a EA |
2953 | BUG_ON(obj->pending_read_domains & I915_GEM_DOMAIN_CPU); |
2954 | BUG_ON(obj->pending_write_domain == I915_GEM_DOMAIN_CPU); | |
673a394b | 2955 | |
652c393a JB |
2956 | intel_mark_busy(dev, obj); |
2957 | ||
673a394b EA |
2958 | #if WATCH_BUF |
2959 | DRM_INFO("%s: object %p read %08x -> %08x write %08x -> %08x\n", | |
2960 | __func__, obj, | |
8b0e378a EA |
2961 | obj->read_domains, obj->pending_read_domains, |
2962 | obj->write_domain, obj->pending_write_domain); | |
673a394b EA |
2963 | #endif |
2964 | /* | |
2965 | * If the object isn't moving to a new write domain, | |
2966 | * let the object stay in multiple read domains | |
2967 | */ | |
8b0e378a EA |
2968 | if (obj->pending_write_domain == 0) |
2969 | obj->pending_read_domains |= obj->read_domains; | |
673a394b EA |
2970 | else |
2971 | obj_priv->dirty = 1; | |
2972 | ||
2973 | /* | |
2974 | * Flush the current write domain if | |
2975 | * the new read domains don't match. Invalidate | |
2976 | * any read domains which differ from the old | |
2977 | * write domain | |
2978 | */ | |
8b0e378a EA |
2979 | if (obj->write_domain && |
2980 | obj->write_domain != obj->pending_read_domains) { | |
673a394b | 2981 | flush_domains |= obj->write_domain; |
8b0e378a EA |
2982 | invalidate_domains |= |
2983 | obj->pending_read_domains & ~obj->write_domain; | |
673a394b EA |
2984 | } |
2985 | /* | |
2986 | * Invalidate any read caches which may have | |
2987 | * stale data. That is, any new read domains. | |
2988 | */ | |
8b0e378a | 2989 | invalidate_domains |= obj->pending_read_domains & ~obj->read_domains; |
673a394b EA |
2990 | if ((flush_domains | invalidate_domains) & I915_GEM_DOMAIN_CPU) { |
2991 | #if WATCH_BUF | |
2992 | DRM_INFO("%s: CPU domain flush %08x invalidate %08x\n", | |
2993 | __func__, flush_domains, invalidate_domains); | |
2994 | #endif | |
673a394b EA |
2995 | i915_gem_clflush_object(obj); |
2996 | } | |
2997 | ||
1c5d22f7 CW |
2998 | old_read_domains = obj->read_domains; |
2999 | ||
efbeed96 EA |
3000 | /* The actual obj->write_domain will be updated with |
3001 | * pending_write_domain after we emit the accumulated flush for all | |
3002 | * of our domain changes in execbuffers (which clears objects' | |
3003 | * write_domains). So if we have a current write domain that we | |
3004 | * aren't changing, set pending_write_domain to that. | |
3005 | */ | |
3006 | if (flush_domains == 0 && obj->pending_write_domain == 0) | |
3007 | obj->pending_write_domain = obj->write_domain; | |
8b0e378a | 3008 | obj->read_domains = obj->pending_read_domains; |
673a394b EA |
3009 | |
3010 | dev->invalidate_domains |= invalidate_domains; | |
3011 | dev->flush_domains |= flush_domains; | |
3012 | #if WATCH_BUF | |
3013 | DRM_INFO("%s: read %08x write %08x invalidate %08x flush %08x\n", | |
3014 | __func__, | |
3015 | obj->read_domains, obj->write_domain, | |
3016 | dev->invalidate_domains, dev->flush_domains); | |
3017 | #endif | |
1c5d22f7 CW |
3018 | |
3019 | trace_i915_gem_object_change_domain(obj, | |
3020 | old_read_domains, | |
3021 | obj->write_domain); | |
673a394b EA |
3022 | } |
3023 | ||
3024 | /** | |
e47c68e9 | 3025 | * Moves the object from a partially CPU read to a full one. |
673a394b | 3026 | * |
e47c68e9 EA |
3027 | * Note that this only resolves i915_gem_object_set_cpu_read_domain_range(), |
3028 | * and doesn't handle transitioning from !(read_domains & I915_GEM_DOMAIN_CPU). | |
673a394b | 3029 | */ |
e47c68e9 EA |
3030 | static void |
3031 | i915_gem_object_set_to_full_cpu_read_domain(struct drm_gem_object *obj) | |
673a394b | 3032 | { |
23010e43 | 3033 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
673a394b | 3034 | |
e47c68e9 EA |
3035 | if (!obj_priv->page_cpu_valid) |
3036 | return; | |
3037 | ||
3038 | /* If we're partially in the CPU read domain, finish moving it in. | |
3039 | */ | |
3040 | if (obj->read_domains & I915_GEM_DOMAIN_CPU) { | |
3041 | int i; | |
3042 | ||
3043 | for (i = 0; i <= (obj->size - 1) / PAGE_SIZE; i++) { | |
3044 | if (obj_priv->page_cpu_valid[i]) | |
3045 | continue; | |
856fa198 | 3046 | drm_clflush_pages(obj_priv->pages + i, 1); |
e47c68e9 | 3047 | } |
e47c68e9 EA |
3048 | } |
3049 | ||
3050 | /* Free the page_cpu_valid mappings which are now stale, whether | |
3051 | * or not we've got I915_GEM_DOMAIN_CPU. | |
3052 | */ | |
9a298b2a | 3053 | kfree(obj_priv->page_cpu_valid); |
e47c68e9 EA |
3054 | obj_priv->page_cpu_valid = NULL; |
3055 | } | |
3056 | ||
3057 | /** | |
3058 | * Set the CPU read domain on a range of the object. | |
3059 | * | |
3060 | * The object ends up with I915_GEM_DOMAIN_CPU in its read flags although it's | |
3061 | * not entirely valid. The page_cpu_valid member of the object flags which | |
3062 | * pages have been flushed, and will be respected by | |
3063 | * i915_gem_object_set_to_cpu_domain() if it's called on to get a valid mapping | |
3064 | * of the whole object. | |
3065 | * | |
3066 | * This function returns when the move is complete, including waiting on | |
3067 | * flushes to occur. | |
3068 | */ | |
3069 | static int | |
3070 | i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object *obj, | |
3071 | uint64_t offset, uint64_t size) | |
3072 | { | |
23010e43 | 3073 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
1c5d22f7 | 3074 | uint32_t old_read_domains; |
e47c68e9 | 3075 | int i, ret; |
673a394b | 3076 | |
e47c68e9 EA |
3077 | if (offset == 0 && size == obj->size) |
3078 | return i915_gem_object_set_to_cpu_domain(obj, 0); | |
673a394b | 3079 | |
ba3d8d74 | 3080 | ret = i915_gem_object_flush_gpu_write_domain(obj, false); |
e47c68e9 | 3081 | if (ret != 0) |
6a47baa6 | 3082 | return ret; |
e47c68e9 EA |
3083 | i915_gem_object_flush_gtt_write_domain(obj); |
3084 | ||
3085 | /* If we're already fully in the CPU read domain, we're done. */ | |
3086 | if (obj_priv->page_cpu_valid == NULL && | |
3087 | (obj->read_domains & I915_GEM_DOMAIN_CPU) != 0) | |
3088 | return 0; | |
673a394b | 3089 | |
e47c68e9 EA |
3090 | /* Otherwise, create/clear the per-page CPU read domain flag if we're |
3091 | * newly adding I915_GEM_DOMAIN_CPU | |
3092 | */ | |
673a394b | 3093 | if (obj_priv->page_cpu_valid == NULL) { |
9a298b2a EA |
3094 | obj_priv->page_cpu_valid = kzalloc(obj->size / PAGE_SIZE, |
3095 | GFP_KERNEL); | |
e47c68e9 EA |
3096 | if (obj_priv->page_cpu_valid == NULL) |
3097 | return -ENOMEM; | |
3098 | } else if ((obj->read_domains & I915_GEM_DOMAIN_CPU) == 0) | |
3099 | memset(obj_priv->page_cpu_valid, 0, obj->size / PAGE_SIZE); | |
673a394b EA |
3100 | |
3101 | /* Flush the cache on any pages that are still invalid from the CPU's | |
3102 | * perspective. | |
3103 | */ | |
e47c68e9 EA |
3104 | for (i = offset / PAGE_SIZE; i <= (offset + size - 1) / PAGE_SIZE; |
3105 | i++) { | |
673a394b EA |
3106 | if (obj_priv->page_cpu_valid[i]) |
3107 | continue; | |
3108 | ||
856fa198 | 3109 | drm_clflush_pages(obj_priv->pages + i, 1); |
673a394b EA |
3110 | |
3111 | obj_priv->page_cpu_valid[i] = 1; | |
3112 | } | |
3113 | ||
e47c68e9 EA |
3114 | /* It should now be out of any other write domains, and we can update |
3115 | * the domain values for our changes. | |
3116 | */ | |
3117 | BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_CPU) != 0); | |
3118 | ||
1c5d22f7 | 3119 | old_read_domains = obj->read_domains; |
e47c68e9 EA |
3120 | obj->read_domains |= I915_GEM_DOMAIN_CPU; |
3121 | ||
1c5d22f7 CW |
3122 | trace_i915_gem_object_change_domain(obj, |
3123 | old_read_domains, | |
3124 | obj->write_domain); | |
3125 | ||
673a394b EA |
3126 | return 0; |
3127 | } | |
3128 | ||
673a394b EA |
3129 | /** |
3130 | * Pin an object to the GTT and evaluate the relocations landing in it. | |
3131 | */ | |
3132 | static int | |
3133 | i915_gem_object_pin_and_relocate(struct drm_gem_object *obj, | |
3134 | struct drm_file *file_priv, | |
76446cac | 3135 | struct drm_i915_gem_exec_object2 *entry, |
40a5f0de | 3136 | struct drm_i915_gem_relocation_entry *relocs) |
673a394b EA |
3137 | { |
3138 | struct drm_device *dev = obj->dev; | |
0839ccb8 | 3139 | drm_i915_private_t *dev_priv = dev->dev_private; |
23010e43 | 3140 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
673a394b | 3141 | int i, ret; |
0839ccb8 | 3142 | void __iomem *reloc_page; |
76446cac JB |
3143 | bool need_fence; |
3144 | ||
3145 | need_fence = entry->flags & EXEC_OBJECT_NEEDS_FENCE && | |
3146 | obj_priv->tiling_mode != I915_TILING_NONE; | |
3147 | ||
3148 | /* Check fence reg constraints and rebind if necessary */ | |
808b24d6 CW |
3149 | if (need_fence && |
3150 | !i915_gem_object_fence_offset_ok(obj, | |
3151 | obj_priv->tiling_mode)) { | |
3152 | ret = i915_gem_object_unbind(obj); | |
3153 | if (ret) | |
3154 | return ret; | |
3155 | } | |
673a394b EA |
3156 | |
3157 | /* Choose the GTT offset for our buffer and put it there. */ | |
3158 | ret = i915_gem_object_pin(obj, (uint32_t) entry->alignment); | |
3159 | if (ret) | |
3160 | return ret; | |
3161 | ||
76446cac JB |
3162 | /* |
3163 | * Pre-965 chips need a fence register set up in order to | |
3164 | * properly handle blits to/from tiled surfaces. | |
3165 | */ | |
3166 | if (need_fence) { | |
3167 | ret = i915_gem_object_get_fence_reg(obj); | |
3168 | if (ret != 0) { | |
76446cac JB |
3169 | i915_gem_object_unpin(obj); |
3170 | return ret; | |
3171 | } | |
3172 | } | |
3173 | ||
673a394b EA |
3174 | entry->offset = obj_priv->gtt_offset; |
3175 | ||
673a394b EA |
3176 | /* Apply the relocations, using the GTT aperture to avoid cache |
3177 | * flushing requirements. | |
3178 | */ | |
3179 | for (i = 0; i < entry->relocation_count; i++) { | |
40a5f0de | 3180 | struct drm_i915_gem_relocation_entry *reloc= &relocs[i]; |
673a394b EA |
3181 | struct drm_gem_object *target_obj; |
3182 | struct drm_i915_gem_object *target_obj_priv; | |
3043c60c EA |
3183 | uint32_t reloc_val, reloc_offset; |
3184 | uint32_t __iomem *reloc_entry; | |
673a394b | 3185 | |
673a394b | 3186 | target_obj = drm_gem_object_lookup(obj->dev, file_priv, |
40a5f0de | 3187 | reloc->target_handle); |
673a394b EA |
3188 | if (target_obj == NULL) { |
3189 | i915_gem_object_unpin(obj); | |
bf79cb91 | 3190 | return -ENOENT; |
673a394b | 3191 | } |
23010e43 | 3192 | target_obj_priv = to_intel_bo(target_obj); |
673a394b | 3193 | |
8542a0bb CW |
3194 | #if WATCH_RELOC |
3195 | DRM_INFO("%s: obj %p offset %08x target %d " | |
3196 | "read %08x write %08x gtt %08x " | |
3197 | "presumed %08x delta %08x\n", | |
3198 | __func__, | |
3199 | obj, | |
3200 | (int) reloc->offset, | |
3201 | (int) reloc->target_handle, | |
3202 | (int) reloc->read_domains, | |
3203 | (int) reloc->write_domain, | |
3204 | (int) target_obj_priv->gtt_offset, | |
3205 | (int) reloc->presumed_offset, | |
3206 | reloc->delta); | |
3207 | #endif | |
3208 | ||
673a394b EA |
3209 | /* The target buffer should have appeared before us in the |
3210 | * exec_object list, so it should have a GTT space bound by now. | |
3211 | */ | |
3212 | if (target_obj_priv->gtt_space == NULL) { | |
3213 | DRM_ERROR("No GTT space found for object %d\n", | |
40a5f0de | 3214 | reloc->target_handle); |
673a394b EA |
3215 | drm_gem_object_unreference(target_obj); |
3216 | i915_gem_object_unpin(obj); | |
3217 | return -EINVAL; | |
3218 | } | |
3219 | ||
8542a0bb | 3220 | /* Validate that the target is in a valid r/w GPU domain */ |
16edd550 DV |
3221 | if (reloc->write_domain & (reloc->write_domain - 1)) { |
3222 | DRM_ERROR("reloc with multiple write domains: " | |
3223 | "obj %p target %d offset %d " | |
3224 | "read %08x write %08x", | |
3225 | obj, reloc->target_handle, | |
3226 | (int) reloc->offset, | |
3227 | reloc->read_domains, | |
3228 | reloc->write_domain); | |
3229 | return -EINVAL; | |
3230 | } | |
40a5f0de EA |
3231 | if (reloc->write_domain & I915_GEM_DOMAIN_CPU || |
3232 | reloc->read_domains & I915_GEM_DOMAIN_CPU) { | |
e47c68e9 EA |
3233 | DRM_ERROR("reloc with read/write CPU domains: " |
3234 | "obj %p target %d offset %d " | |
3235 | "read %08x write %08x", | |
40a5f0de EA |
3236 | obj, reloc->target_handle, |
3237 | (int) reloc->offset, | |
3238 | reloc->read_domains, | |
3239 | reloc->write_domain); | |
491152b8 CW |
3240 | drm_gem_object_unreference(target_obj); |
3241 | i915_gem_object_unpin(obj); | |
e47c68e9 EA |
3242 | return -EINVAL; |
3243 | } | |
40a5f0de EA |
3244 | if (reloc->write_domain && target_obj->pending_write_domain && |
3245 | reloc->write_domain != target_obj->pending_write_domain) { | |
673a394b EA |
3246 | DRM_ERROR("Write domain conflict: " |
3247 | "obj %p target %d offset %d " | |
3248 | "new %08x old %08x\n", | |
40a5f0de EA |
3249 | obj, reloc->target_handle, |
3250 | (int) reloc->offset, | |
3251 | reloc->write_domain, | |
673a394b EA |
3252 | target_obj->pending_write_domain); |
3253 | drm_gem_object_unreference(target_obj); | |
3254 | i915_gem_object_unpin(obj); | |
3255 | return -EINVAL; | |
3256 | } | |
3257 | ||
40a5f0de EA |
3258 | target_obj->pending_read_domains |= reloc->read_domains; |
3259 | target_obj->pending_write_domain |= reloc->write_domain; | |
673a394b EA |
3260 | |
3261 | /* If the relocation already has the right value in it, no | |
3262 | * more work needs to be done. | |
3263 | */ | |
40a5f0de | 3264 | if (target_obj_priv->gtt_offset == reloc->presumed_offset) { |
673a394b EA |
3265 | drm_gem_object_unreference(target_obj); |
3266 | continue; | |
3267 | } | |
3268 | ||
8542a0bb CW |
3269 | /* Check that the relocation address is valid... */ |
3270 | if (reloc->offset > obj->size - 4) { | |
3271 | DRM_ERROR("Relocation beyond object bounds: " | |
3272 | "obj %p target %d offset %d size %d.\n", | |
3273 | obj, reloc->target_handle, | |
3274 | (int) reloc->offset, (int) obj->size); | |
3275 | drm_gem_object_unreference(target_obj); | |
3276 | i915_gem_object_unpin(obj); | |
3277 | return -EINVAL; | |
3278 | } | |
3279 | if (reloc->offset & 3) { | |
3280 | DRM_ERROR("Relocation not 4-byte aligned: " | |
3281 | "obj %p target %d offset %d.\n", | |
3282 | obj, reloc->target_handle, | |
3283 | (int) reloc->offset); | |
3284 | drm_gem_object_unreference(target_obj); | |
3285 | i915_gem_object_unpin(obj); | |
3286 | return -EINVAL; | |
3287 | } | |
3288 | ||
3289 | /* and points to somewhere within the target object. */ | |
3290 | if (reloc->delta >= target_obj->size) { | |
3291 | DRM_ERROR("Relocation beyond target object bounds: " | |
3292 | "obj %p target %d delta %d size %d.\n", | |
3293 | obj, reloc->target_handle, | |
3294 | (int) reloc->delta, (int) target_obj->size); | |
3295 | drm_gem_object_unreference(target_obj); | |
3296 | i915_gem_object_unpin(obj); | |
3297 | return -EINVAL; | |
3298 | } | |
3299 | ||
2ef7eeaa EA |
3300 | ret = i915_gem_object_set_to_gtt_domain(obj, 1); |
3301 | if (ret != 0) { | |
3302 | drm_gem_object_unreference(target_obj); | |
3303 | i915_gem_object_unpin(obj); | |
3304 | return -EINVAL; | |
673a394b EA |
3305 | } |
3306 | ||
3307 | /* Map the page containing the relocation we're going to | |
3308 | * perform. | |
3309 | */ | |
40a5f0de | 3310 | reloc_offset = obj_priv->gtt_offset + reloc->offset; |
0839ccb8 KP |
3311 | reloc_page = io_mapping_map_atomic_wc(dev_priv->mm.gtt_mapping, |
3312 | (reloc_offset & | |
fca3ec01 CW |
3313 | ~(PAGE_SIZE - 1)), |
3314 | KM_USER0); | |
3043c60c | 3315 | reloc_entry = (uint32_t __iomem *)(reloc_page + |
0839ccb8 | 3316 | (reloc_offset & (PAGE_SIZE - 1))); |
40a5f0de | 3317 | reloc_val = target_obj_priv->gtt_offset + reloc->delta; |
673a394b EA |
3318 | |
3319 | #if WATCH_BUF | |
3320 | DRM_INFO("Applied relocation: %p@0x%08x %08x -> %08x\n", | |
40a5f0de | 3321 | obj, (unsigned int) reloc->offset, |
673a394b EA |
3322 | readl(reloc_entry), reloc_val); |
3323 | #endif | |
3324 | writel(reloc_val, reloc_entry); | |
fca3ec01 | 3325 | io_mapping_unmap_atomic(reloc_page, KM_USER0); |
673a394b | 3326 | |
40a5f0de EA |
3327 | /* The updated presumed offset for this entry will be |
3328 | * copied back out to the user. | |
673a394b | 3329 | */ |
40a5f0de | 3330 | reloc->presumed_offset = target_obj_priv->gtt_offset; |
673a394b EA |
3331 | |
3332 | drm_gem_object_unreference(target_obj); | |
3333 | } | |
3334 | ||
673a394b EA |
3335 | #if WATCH_BUF |
3336 | if (0) | |
3337 | i915_gem_dump_object(obj, 128, __func__, ~0); | |
3338 | #endif | |
3339 | return 0; | |
3340 | } | |
3341 | ||
673a394b EA |
3342 | /* Throttle our rendering by waiting until the ring has completed our requests |
3343 | * emitted over 20 msec ago. | |
3344 | * | |
b962442e EA |
3345 | * Note that if we were to use the current jiffies each time around the loop, |
3346 | * we wouldn't escape the function with any frames outstanding if the time to | |
3347 | * render a frame was over 20ms. | |
3348 | * | |
673a394b EA |
3349 | * This should get us reasonable parallelism between CPU and GPU but also |
3350 | * relatively low latency when blocking on a particular request to finish. | |
3351 | */ | |
3352 | static int | |
3353 | i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file_priv) | |
3354 | { | |
3355 | struct drm_i915_file_private *i915_file_priv = file_priv->driver_priv; | |
3356 | int ret = 0; | |
b962442e | 3357 | unsigned long recent_enough = jiffies - msecs_to_jiffies(20); |
673a394b EA |
3358 | |
3359 | mutex_lock(&dev->struct_mutex); | |
b962442e EA |
3360 | while (!list_empty(&i915_file_priv->mm.request_list)) { |
3361 | struct drm_i915_gem_request *request; | |
3362 | ||
3363 | request = list_first_entry(&i915_file_priv->mm.request_list, | |
3364 | struct drm_i915_gem_request, | |
3365 | client_list); | |
3366 | ||
3367 | if (time_after_eq(request->emitted_jiffies, recent_enough)) | |
3368 | break; | |
3369 | ||
852835f3 | 3370 | ret = i915_wait_request(dev, request->seqno, request->ring); |
b962442e EA |
3371 | if (ret != 0) |
3372 | break; | |
3373 | } | |
673a394b | 3374 | mutex_unlock(&dev->struct_mutex); |
b962442e | 3375 | |
673a394b EA |
3376 | return ret; |
3377 | } | |
3378 | ||
40a5f0de | 3379 | static int |
76446cac | 3380 | i915_gem_get_relocs_from_user(struct drm_i915_gem_exec_object2 *exec_list, |
40a5f0de EA |
3381 | uint32_t buffer_count, |
3382 | struct drm_i915_gem_relocation_entry **relocs) | |
3383 | { | |
3384 | uint32_t reloc_count = 0, reloc_index = 0, i; | |
3385 | int ret; | |
3386 | ||
3387 | *relocs = NULL; | |
3388 | for (i = 0; i < buffer_count; i++) { | |
3389 | if (reloc_count + exec_list[i].relocation_count < reloc_count) | |
3390 | return -EINVAL; | |
3391 | reloc_count += exec_list[i].relocation_count; | |
3392 | } | |
3393 | ||
8e7d2b2c | 3394 | *relocs = drm_calloc_large(reloc_count, sizeof(**relocs)); |
76446cac JB |
3395 | if (*relocs == NULL) { |
3396 | DRM_ERROR("failed to alloc relocs, count %d\n", reloc_count); | |
40a5f0de | 3397 | return -ENOMEM; |
76446cac | 3398 | } |
40a5f0de EA |
3399 | |
3400 | for (i = 0; i < buffer_count; i++) { | |
3401 | struct drm_i915_gem_relocation_entry __user *user_relocs; | |
3402 | ||
3403 | user_relocs = (void __user *)(uintptr_t)exec_list[i].relocs_ptr; | |
3404 | ||
3405 | ret = copy_from_user(&(*relocs)[reloc_index], | |
3406 | user_relocs, | |
3407 | exec_list[i].relocation_count * | |
3408 | sizeof(**relocs)); | |
3409 | if (ret != 0) { | |
8e7d2b2c | 3410 | drm_free_large(*relocs); |
40a5f0de | 3411 | *relocs = NULL; |
2bc43b5c | 3412 | return -EFAULT; |
40a5f0de EA |
3413 | } |
3414 | ||
3415 | reloc_index += exec_list[i].relocation_count; | |
3416 | } | |
3417 | ||
2bc43b5c | 3418 | return 0; |
40a5f0de EA |
3419 | } |
3420 | ||
3421 | static int | |
76446cac | 3422 | i915_gem_put_relocs_to_user(struct drm_i915_gem_exec_object2 *exec_list, |
40a5f0de EA |
3423 | uint32_t buffer_count, |
3424 | struct drm_i915_gem_relocation_entry *relocs) | |
3425 | { | |
3426 | uint32_t reloc_count = 0, i; | |
2bc43b5c | 3427 | int ret = 0; |
40a5f0de | 3428 | |
93533c29 CW |
3429 | if (relocs == NULL) |
3430 | return 0; | |
3431 | ||
40a5f0de EA |
3432 | for (i = 0; i < buffer_count; i++) { |
3433 | struct drm_i915_gem_relocation_entry __user *user_relocs; | |
2bc43b5c | 3434 | int unwritten; |
40a5f0de EA |
3435 | |
3436 | user_relocs = (void __user *)(uintptr_t)exec_list[i].relocs_ptr; | |
3437 | ||
2bc43b5c FM |
3438 | unwritten = copy_to_user(user_relocs, |
3439 | &relocs[reloc_count], | |
3440 | exec_list[i].relocation_count * | |
3441 | sizeof(*relocs)); | |
3442 | ||
3443 | if (unwritten) { | |
3444 | ret = -EFAULT; | |
3445 | goto err; | |
40a5f0de EA |
3446 | } |
3447 | ||
3448 | reloc_count += exec_list[i].relocation_count; | |
3449 | } | |
3450 | ||
2bc43b5c | 3451 | err: |
8e7d2b2c | 3452 | drm_free_large(relocs); |
40a5f0de EA |
3453 | |
3454 | return ret; | |
3455 | } | |
3456 | ||
83d60795 | 3457 | static int |
76446cac | 3458 | i915_gem_check_execbuffer (struct drm_i915_gem_execbuffer2 *exec, |
83d60795 CW |
3459 | uint64_t exec_offset) |
3460 | { | |
3461 | uint32_t exec_start, exec_len; | |
3462 | ||
3463 | exec_start = (uint32_t) exec_offset + exec->batch_start_offset; | |
3464 | exec_len = (uint32_t) exec->batch_len; | |
3465 | ||
3466 | if ((exec_start | exec_len) & 0x7) | |
3467 | return -EINVAL; | |
3468 | ||
3469 | if (!exec_start) | |
3470 | return -EINVAL; | |
3471 | ||
3472 | return 0; | |
3473 | } | |
3474 | ||
6b95a207 KH |
3475 | static int |
3476 | i915_gem_wait_for_pending_flip(struct drm_device *dev, | |
3477 | struct drm_gem_object **object_list, | |
3478 | int count) | |
3479 | { | |
3480 | drm_i915_private_t *dev_priv = dev->dev_private; | |
3481 | struct drm_i915_gem_object *obj_priv; | |
3482 | DEFINE_WAIT(wait); | |
3483 | int i, ret = 0; | |
3484 | ||
3485 | for (;;) { | |
3486 | prepare_to_wait(&dev_priv->pending_flip_queue, | |
3487 | &wait, TASK_INTERRUPTIBLE); | |
3488 | for (i = 0; i < count; i++) { | |
23010e43 | 3489 | obj_priv = to_intel_bo(object_list[i]); |
6b95a207 KH |
3490 | if (atomic_read(&obj_priv->pending_flip) > 0) |
3491 | break; | |
3492 | } | |
3493 | if (i == count) | |
3494 | break; | |
3495 | ||
3496 | if (!signal_pending(current)) { | |
3497 | mutex_unlock(&dev->struct_mutex); | |
3498 | schedule(); | |
3499 | mutex_lock(&dev->struct_mutex); | |
3500 | continue; | |
3501 | } | |
3502 | ret = -ERESTARTSYS; | |
3503 | break; | |
3504 | } | |
3505 | finish_wait(&dev_priv->pending_flip_queue, &wait); | |
3506 | ||
3507 | return ret; | |
3508 | } | |
3509 | ||
8dc5d147 | 3510 | static int |
76446cac JB |
3511 | i915_gem_do_execbuffer(struct drm_device *dev, void *data, |
3512 | struct drm_file *file_priv, | |
3513 | struct drm_i915_gem_execbuffer2 *args, | |
3514 | struct drm_i915_gem_exec_object2 *exec_list) | |
673a394b EA |
3515 | { |
3516 | drm_i915_private_t *dev_priv = dev->dev_private; | |
673a394b EA |
3517 | struct drm_gem_object **object_list = NULL; |
3518 | struct drm_gem_object *batch_obj; | |
b70d11da | 3519 | struct drm_i915_gem_object *obj_priv; |
201361a5 | 3520 | struct drm_clip_rect *cliprects = NULL; |
93533c29 | 3521 | struct drm_i915_gem_relocation_entry *relocs = NULL; |
8dc5d147 | 3522 | struct drm_i915_gem_request *request = NULL; |
76446cac | 3523 | int ret = 0, ret2, i, pinned = 0; |
673a394b | 3524 | uint64_t exec_offset; |
8a1a49f9 | 3525 | uint32_t seqno, reloc_index; |
6b95a207 | 3526 | int pin_tries, flips; |
673a394b | 3527 | |
852835f3 ZN |
3528 | struct intel_ring_buffer *ring = NULL; |
3529 | ||
673a394b EA |
3530 | #if WATCH_EXEC |
3531 | DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n", | |
3532 | (int) args->buffers_ptr, args->buffer_count, args->batch_len); | |
3533 | #endif | |
d1b851fc ZN |
3534 | if (args->flags & I915_EXEC_BSD) { |
3535 | if (!HAS_BSD(dev)) { | |
3536 | DRM_ERROR("execbuf with wrong flag\n"); | |
3537 | return -EINVAL; | |
3538 | } | |
3539 | ring = &dev_priv->bsd_ring; | |
3540 | } else { | |
3541 | ring = &dev_priv->render_ring; | |
3542 | } | |
3543 | ||
4f481ed2 EA |
3544 | if (args->buffer_count < 1) { |
3545 | DRM_ERROR("execbuf with %d buffers\n", args->buffer_count); | |
3546 | return -EINVAL; | |
3547 | } | |
c8e0f93a | 3548 | object_list = drm_malloc_ab(sizeof(*object_list), args->buffer_count); |
76446cac JB |
3549 | if (object_list == NULL) { |
3550 | DRM_ERROR("Failed to allocate object list for %d buffers\n", | |
673a394b EA |
3551 | args->buffer_count); |
3552 | ret = -ENOMEM; | |
3553 | goto pre_mutex_err; | |
3554 | } | |
673a394b | 3555 | |
201361a5 | 3556 | if (args->num_cliprects != 0) { |
9a298b2a EA |
3557 | cliprects = kcalloc(args->num_cliprects, sizeof(*cliprects), |
3558 | GFP_KERNEL); | |
a40e8d31 OA |
3559 | if (cliprects == NULL) { |
3560 | ret = -ENOMEM; | |
201361a5 | 3561 | goto pre_mutex_err; |
a40e8d31 | 3562 | } |
201361a5 EA |
3563 | |
3564 | ret = copy_from_user(cliprects, | |
3565 | (struct drm_clip_rect __user *) | |
3566 | (uintptr_t) args->cliprects_ptr, | |
3567 | sizeof(*cliprects) * args->num_cliprects); | |
3568 | if (ret != 0) { | |
3569 | DRM_ERROR("copy %d cliprects failed: %d\n", | |
3570 | args->num_cliprects, ret); | |
c877cdce | 3571 | ret = -EFAULT; |
201361a5 EA |
3572 | goto pre_mutex_err; |
3573 | } | |
3574 | } | |
3575 | ||
8dc5d147 CW |
3576 | request = kzalloc(sizeof(*request), GFP_KERNEL); |
3577 | if (request == NULL) { | |
3578 | ret = -ENOMEM; | |
3579 | goto pre_mutex_err; | |
3580 | } | |
3581 | ||
40a5f0de EA |
3582 | ret = i915_gem_get_relocs_from_user(exec_list, args->buffer_count, |
3583 | &relocs); | |
3584 | if (ret != 0) | |
3585 | goto pre_mutex_err; | |
3586 | ||
673a394b EA |
3587 | mutex_lock(&dev->struct_mutex); |
3588 | ||
3589 | i915_verify_inactive(dev, __FILE__, __LINE__); | |
3590 | ||
ba1234d1 | 3591 | if (atomic_read(&dev_priv->mm.wedged)) { |
673a394b | 3592 | mutex_unlock(&dev->struct_mutex); |
a198bc80 CW |
3593 | ret = -EIO; |
3594 | goto pre_mutex_err; | |
673a394b EA |
3595 | } |
3596 | ||
3597 | if (dev_priv->mm.suspended) { | |
673a394b | 3598 | mutex_unlock(&dev->struct_mutex); |
a198bc80 CW |
3599 | ret = -EBUSY; |
3600 | goto pre_mutex_err; | |
673a394b EA |
3601 | } |
3602 | ||
ac94a962 | 3603 | /* Look up object handles */ |
6b95a207 | 3604 | flips = 0; |
673a394b EA |
3605 | for (i = 0; i < args->buffer_count; i++) { |
3606 | object_list[i] = drm_gem_object_lookup(dev, file_priv, | |
3607 | exec_list[i].handle); | |
3608 | if (object_list[i] == NULL) { | |
3609 | DRM_ERROR("Invalid object handle %d at index %d\n", | |
3610 | exec_list[i].handle, i); | |
0ce907f8 CW |
3611 | /* prevent error path from reading uninitialized data */ |
3612 | args->buffer_count = i + 1; | |
bf79cb91 | 3613 | ret = -ENOENT; |
673a394b EA |
3614 | goto err; |
3615 | } | |
b70d11da | 3616 | |
23010e43 | 3617 | obj_priv = to_intel_bo(object_list[i]); |
b70d11da KH |
3618 | if (obj_priv->in_execbuffer) { |
3619 | DRM_ERROR("Object %p appears more than once in object list\n", | |
3620 | object_list[i]); | |
0ce907f8 CW |
3621 | /* prevent error path from reading uninitialized data */ |
3622 | args->buffer_count = i + 1; | |
bf79cb91 | 3623 | ret = -EINVAL; |
b70d11da KH |
3624 | goto err; |
3625 | } | |
3626 | obj_priv->in_execbuffer = true; | |
6b95a207 KH |
3627 | flips += atomic_read(&obj_priv->pending_flip); |
3628 | } | |
3629 | ||
3630 | if (flips > 0) { | |
3631 | ret = i915_gem_wait_for_pending_flip(dev, object_list, | |
3632 | args->buffer_count); | |
3633 | if (ret) | |
3634 | goto err; | |
ac94a962 | 3635 | } |
673a394b | 3636 | |
ac94a962 KP |
3637 | /* Pin and relocate */ |
3638 | for (pin_tries = 0; ; pin_tries++) { | |
3639 | ret = 0; | |
40a5f0de EA |
3640 | reloc_index = 0; |
3641 | ||
ac94a962 KP |
3642 | for (i = 0; i < args->buffer_count; i++) { |
3643 | object_list[i]->pending_read_domains = 0; | |
3644 | object_list[i]->pending_write_domain = 0; | |
3645 | ret = i915_gem_object_pin_and_relocate(object_list[i], | |
3646 | file_priv, | |
40a5f0de EA |
3647 | &exec_list[i], |
3648 | &relocs[reloc_index]); | |
ac94a962 KP |
3649 | if (ret) |
3650 | break; | |
3651 | pinned = i + 1; | |
40a5f0de | 3652 | reloc_index += exec_list[i].relocation_count; |
ac94a962 KP |
3653 | } |
3654 | /* success */ | |
3655 | if (ret == 0) | |
3656 | break; | |
3657 | ||
3658 | /* error other than GTT full, or we've already tried again */ | |
2939e1f5 | 3659 | if (ret != -ENOSPC || pin_tries >= 1) { |
07f73f69 CW |
3660 | if (ret != -ERESTARTSYS) { |
3661 | unsigned long long total_size = 0; | |
3d1cc470 CW |
3662 | int num_fences = 0; |
3663 | for (i = 0; i < args->buffer_count; i++) { | |
43b27f40 | 3664 | obj_priv = to_intel_bo(object_list[i]); |
3d1cc470 | 3665 | |
07f73f69 | 3666 | total_size += object_list[i]->size; |
3d1cc470 CW |
3667 | num_fences += |
3668 | exec_list[i].flags & EXEC_OBJECT_NEEDS_FENCE && | |
3669 | obj_priv->tiling_mode != I915_TILING_NONE; | |
3670 | } | |
3671 | DRM_ERROR("Failed to pin buffer %d of %d, total %llu bytes, %d fences: %d\n", | |
07f73f69 | 3672 | pinned+1, args->buffer_count, |
3d1cc470 CW |
3673 | total_size, num_fences, |
3674 | ret); | |
07f73f69 CW |
3675 | DRM_ERROR("%d objects [%d pinned], " |
3676 | "%d object bytes [%d pinned], " | |
3677 | "%d/%d gtt bytes\n", | |
3678 | atomic_read(&dev->object_count), | |
3679 | atomic_read(&dev->pin_count), | |
3680 | atomic_read(&dev->object_memory), | |
3681 | atomic_read(&dev->pin_memory), | |
3682 | atomic_read(&dev->gtt_memory), | |
3683 | dev->gtt_total); | |
3684 | } | |
673a394b EA |
3685 | goto err; |
3686 | } | |
ac94a962 KP |
3687 | |
3688 | /* unpin all of our buffers */ | |
3689 | for (i = 0; i < pinned; i++) | |
3690 | i915_gem_object_unpin(object_list[i]); | |
b1177636 | 3691 | pinned = 0; |
ac94a962 KP |
3692 | |
3693 | /* evict everyone we can from the aperture */ | |
3694 | ret = i915_gem_evict_everything(dev); | |
07f73f69 | 3695 | if (ret && ret != -ENOSPC) |
ac94a962 | 3696 | goto err; |
673a394b EA |
3697 | } |
3698 | ||
3699 | /* Set the pending read domains for the batch buffer to COMMAND */ | |
3700 | batch_obj = object_list[args->buffer_count-1]; | |
5f26a2c7 CW |
3701 | if (batch_obj->pending_write_domain) { |
3702 | DRM_ERROR("Attempting to use self-modifying batch buffer\n"); | |
3703 | ret = -EINVAL; | |
3704 | goto err; | |
3705 | } | |
3706 | batch_obj->pending_read_domains |= I915_GEM_DOMAIN_COMMAND; | |
673a394b | 3707 | |
83d60795 CW |
3708 | /* Sanity check the batch buffer, prior to moving objects */ |
3709 | exec_offset = exec_list[args->buffer_count - 1].offset; | |
3710 | ret = i915_gem_check_execbuffer (args, exec_offset); | |
3711 | if (ret != 0) { | |
3712 | DRM_ERROR("execbuf with invalid offset/length\n"); | |
3713 | goto err; | |
3714 | } | |
3715 | ||
673a394b EA |
3716 | i915_verify_inactive(dev, __FILE__, __LINE__); |
3717 | ||
646f0f6e KP |
3718 | /* Zero the global flush/invalidate flags. These |
3719 | * will be modified as new domains are computed | |
3720 | * for each object | |
3721 | */ | |
3722 | dev->invalidate_domains = 0; | |
3723 | dev->flush_domains = 0; | |
3724 | ||
673a394b EA |
3725 | for (i = 0; i < args->buffer_count; i++) { |
3726 | struct drm_gem_object *obj = object_list[i]; | |
673a394b | 3727 | |
646f0f6e | 3728 | /* Compute new gpu domains and update invalidate/flush */ |
8b0e378a | 3729 | i915_gem_object_set_to_gpu_domain(obj); |
673a394b EA |
3730 | } |
3731 | ||
3732 | i915_verify_inactive(dev, __FILE__, __LINE__); | |
3733 | ||
646f0f6e KP |
3734 | if (dev->invalidate_domains | dev->flush_domains) { |
3735 | #if WATCH_EXEC | |
3736 | DRM_INFO("%s: invalidate_domains %08x flush_domains %08x\n", | |
3737 | __func__, | |
3738 | dev->invalidate_domains, | |
3739 | dev->flush_domains); | |
3740 | #endif | |
3741 | i915_gem_flush(dev, | |
3742 | dev->invalidate_domains, | |
3743 | dev->flush_domains); | |
a6910434 DV |
3744 | } |
3745 | ||
3746 | if (dev_priv->render_ring.outstanding_lazy_request) { | |
8dc5d147 | 3747 | (void)i915_add_request(dev, file_priv, NULL, &dev_priv->render_ring); |
a6910434 DV |
3748 | dev_priv->render_ring.outstanding_lazy_request = false; |
3749 | } | |
3750 | if (dev_priv->bsd_ring.outstanding_lazy_request) { | |
8dc5d147 | 3751 | (void)i915_add_request(dev, file_priv, NULL, &dev_priv->bsd_ring); |
a6910434 | 3752 | dev_priv->bsd_ring.outstanding_lazy_request = false; |
646f0f6e | 3753 | } |
673a394b | 3754 | |
efbeed96 EA |
3755 | for (i = 0; i < args->buffer_count; i++) { |
3756 | struct drm_gem_object *obj = object_list[i]; | |
23010e43 | 3757 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
1c5d22f7 | 3758 | uint32_t old_write_domain = obj->write_domain; |
efbeed96 EA |
3759 | |
3760 | obj->write_domain = obj->pending_write_domain; | |
99fcb766 DV |
3761 | if (obj->write_domain) |
3762 | list_move_tail(&obj_priv->gpu_write_list, | |
3763 | &dev_priv->mm.gpu_write_list); | |
3764 | else | |
3765 | list_del_init(&obj_priv->gpu_write_list); | |
3766 | ||
1c5d22f7 CW |
3767 | trace_i915_gem_object_change_domain(obj, |
3768 | obj->read_domains, | |
3769 | old_write_domain); | |
efbeed96 EA |
3770 | } |
3771 | ||
673a394b EA |
3772 | i915_verify_inactive(dev, __FILE__, __LINE__); |
3773 | ||
3774 | #if WATCH_COHERENCY | |
3775 | for (i = 0; i < args->buffer_count; i++) { | |
3776 | i915_gem_object_check_coherency(object_list[i], | |
3777 | exec_list[i].handle); | |
3778 | } | |
3779 | #endif | |
3780 | ||
673a394b | 3781 | #if WATCH_EXEC |
6911a9b8 | 3782 | i915_gem_dump_object(batch_obj, |
673a394b EA |
3783 | args->batch_len, |
3784 | __func__, | |
3785 | ~0); | |
3786 | #endif | |
3787 | ||
673a394b | 3788 | /* Exec the batchbuffer */ |
852835f3 ZN |
3789 | ret = ring->dispatch_gem_execbuffer(dev, ring, args, |
3790 | cliprects, exec_offset); | |
673a394b EA |
3791 | if (ret) { |
3792 | DRM_ERROR("dispatch failed %d\n", ret); | |
3793 | goto err; | |
3794 | } | |
3795 | ||
3796 | /* | |
3797 | * Ensure that the commands in the batch buffer are | |
3798 | * finished before the interrupt fires | |
3799 | */ | |
8a1a49f9 | 3800 | i915_retire_commands(dev, ring); |
673a394b EA |
3801 | |
3802 | i915_verify_inactive(dev, __FILE__, __LINE__); | |
3803 | ||
617dbe27 DV |
3804 | for (i = 0; i < args->buffer_count; i++) { |
3805 | struct drm_gem_object *obj = object_list[i]; | |
3806 | obj_priv = to_intel_bo(obj); | |
3807 | ||
3808 | i915_gem_object_move_to_active(obj, ring); | |
3809 | #if WATCH_LRU | |
3810 | DRM_INFO("%s: move to exec list %p\n", __func__, obj); | |
3811 | #endif | |
3812 | } | |
3813 | ||
673a394b EA |
3814 | /* |
3815 | * Get a seqno representing the execution of the current buffer, | |
3816 | * which we can wait on. We would like to mitigate these interrupts, | |
3817 | * likely by only creating seqnos occasionally (so that we have | |
3818 | * *some* interrupts representing completion of buffers that we can | |
3819 | * wait on when trying to clear up gtt space). | |
3820 | */ | |
8dc5d147 CW |
3821 | seqno = i915_add_request(dev, file_priv, request, ring); |
3822 | request = NULL; | |
673a394b | 3823 | |
673a394b EA |
3824 | #if WATCH_LRU |
3825 | i915_dump_lru(dev, __func__); | |
3826 | #endif | |
3827 | ||
3828 | i915_verify_inactive(dev, __FILE__, __LINE__); | |
3829 | ||
673a394b | 3830 | err: |
aad87dff JL |
3831 | for (i = 0; i < pinned; i++) |
3832 | i915_gem_object_unpin(object_list[i]); | |
3833 | ||
b70d11da KH |
3834 | for (i = 0; i < args->buffer_count; i++) { |
3835 | if (object_list[i]) { | |
23010e43 | 3836 | obj_priv = to_intel_bo(object_list[i]); |
b70d11da KH |
3837 | obj_priv->in_execbuffer = false; |
3838 | } | |
aad87dff | 3839 | drm_gem_object_unreference(object_list[i]); |
b70d11da | 3840 | } |
673a394b | 3841 | |
673a394b EA |
3842 | mutex_unlock(&dev->struct_mutex); |
3843 | ||
93533c29 | 3844 | pre_mutex_err: |
40a5f0de EA |
3845 | /* Copy the updated relocations out regardless of current error |
3846 | * state. Failure to update the relocs would mean that the next | |
3847 | * time userland calls execbuf, it would do so with presumed offset | |
3848 | * state that didn't match the actual object state. | |
3849 | */ | |
3850 | ret2 = i915_gem_put_relocs_to_user(exec_list, args->buffer_count, | |
3851 | relocs); | |
3852 | if (ret2 != 0) { | |
3853 | DRM_ERROR("Failed to copy relocations back out: %d\n", ret2); | |
3854 | ||
3855 | if (ret == 0) | |
3856 | ret = ret2; | |
3857 | } | |
3858 | ||
8e7d2b2c | 3859 | drm_free_large(object_list); |
9a298b2a | 3860 | kfree(cliprects); |
8dc5d147 | 3861 | kfree(request); |
673a394b EA |
3862 | |
3863 | return ret; | |
3864 | } | |
3865 | ||
76446cac JB |
3866 | /* |
3867 | * Legacy execbuffer just creates an exec2 list from the original exec object | |
3868 | * list array and passes it to the real function. | |
3869 | */ | |
3870 | int | |
3871 | i915_gem_execbuffer(struct drm_device *dev, void *data, | |
3872 | struct drm_file *file_priv) | |
3873 | { | |
3874 | struct drm_i915_gem_execbuffer *args = data; | |
3875 | struct drm_i915_gem_execbuffer2 exec2; | |
3876 | struct drm_i915_gem_exec_object *exec_list = NULL; | |
3877 | struct drm_i915_gem_exec_object2 *exec2_list = NULL; | |
3878 | int ret, i; | |
3879 | ||
3880 | #if WATCH_EXEC | |
3881 | DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n", | |
3882 | (int) args->buffers_ptr, args->buffer_count, args->batch_len); | |
3883 | #endif | |
3884 | ||
3885 | if (args->buffer_count < 1) { | |
3886 | DRM_ERROR("execbuf with %d buffers\n", args->buffer_count); | |
3887 | return -EINVAL; | |
3888 | } | |
3889 | ||
3890 | /* Copy in the exec list from userland */ | |
3891 | exec_list = drm_malloc_ab(sizeof(*exec_list), args->buffer_count); | |
3892 | exec2_list = drm_malloc_ab(sizeof(*exec2_list), args->buffer_count); | |
3893 | if (exec_list == NULL || exec2_list == NULL) { | |
3894 | DRM_ERROR("Failed to allocate exec list for %d buffers\n", | |
3895 | args->buffer_count); | |
3896 | drm_free_large(exec_list); | |
3897 | drm_free_large(exec2_list); | |
3898 | return -ENOMEM; | |
3899 | } | |
3900 | ret = copy_from_user(exec_list, | |
3901 | (struct drm_i915_relocation_entry __user *) | |
3902 | (uintptr_t) args->buffers_ptr, | |
3903 | sizeof(*exec_list) * args->buffer_count); | |
3904 | if (ret != 0) { | |
3905 | DRM_ERROR("copy %d exec entries failed %d\n", | |
3906 | args->buffer_count, ret); | |
3907 | drm_free_large(exec_list); | |
3908 | drm_free_large(exec2_list); | |
3909 | return -EFAULT; | |
3910 | } | |
3911 | ||
3912 | for (i = 0; i < args->buffer_count; i++) { | |
3913 | exec2_list[i].handle = exec_list[i].handle; | |
3914 | exec2_list[i].relocation_count = exec_list[i].relocation_count; | |
3915 | exec2_list[i].relocs_ptr = exec_list[i].relocs_ptr; | |
3916 | exec2_list[i].alignment = exec_list[i].alignment; | |
3917 | exec2_list[i].offset = exec_list[i].offset; | |
3918 | if (!IS_I965G(dev)) | |
3919 | exec2_list[i].flags = EXEC_OBJECT_NEEDS_FENCE; | |
3920 | else | |
3921 | exec2_list[i].flags = 0; | |
3922 | } | |
3923 | ||
3924 | exec2.buffers_ptr = args->buffers_ptr; | |
3925 | exec2.buffer_count = args->buffer_count; | |
3926 | exec2.batch_start_offset = args->batch_start_offset; | |
3927 | exec2.batch_len = args->batch_len; | |
3928 | exec2.DR1 = args->DR1; | |
3929 | exec2.DR4 = args->DR4; | |
3930 | exec2.num_cliprects = args->num_cliprects; | |
3931 | exec2.cliprects_ptr = args->cliprects_ptr; | |
852835f3 | 3932 | exec2.flags = I915_EXEC_RENDER; |
76446cac JB |
3933 | |
3934 | ret = i915_gem_do_execbuffer(dev, data, file_priv, &exec2, exec2_list); | |
3935 | if (!ret) { | |
3936 | /* Copy the new buffer offsets back to the user's exec list. */ | |
3937 | for (i = 0; i < args->buffer_count; i++) | |
3938 | exec_list[i].offset = exec2_list[i].offset; | |
3939 | /* ... and back out to userspace */ | |
3940 | ret = copy_to_user((struct drm_i915_relocation_entry __user *) | |
3941 | (uintptr_t) args->buffers_ptr, | |
3942 | exec_list, | |
3943 | sizeof(*exec_list) * args->buffer_count); | |
3944 | if (ret) { | |
3945 | ret = -EFAULT; | |
3946 | DRM_ERROR("failed to copy %d exec entries " | |
3947 | "back to user (%d)\n", | |
3948 | args->buffer_count, ret); | |
3949 | } | |
76446cac JB |
3950 | } |
3951 | ||
3952 | drm_free_large(exec_list); | |
3953 | drm_free_large(exec2_list); | |
3954 | return ret; | |
3955 | } | |
3956 | ||
3957 | int | |
3958 | i915_gem_execbuffer2(struct drm_device *dev, void *data, | |
3959 | struct drm_file *file_priv) | |
3960 | { | |
3961 | struct drm_i915_gem_execbuffer2 *args = data; | |
3962 | struct drm_i915_gem_exec_object2 *exec2_list = NULL; | |
3963 | int ret; | |
3964 | ||
3965 | #if WATCH_EXEC | |
3966 | DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n", | |
3967 | (int) args->buffers_ptr, args->buffer_count, args->batch_len); | |
3968 | #endif | |
3969 | ||
3970 | if (args->buffer_count < 1) { | |
3971 | DRM_ERROR("execbuf2 with %d buffers\n", args->buffer_count); | |
3972 | return -EINVAL; | |
3973 | } | |
3974 | ||
3975 | exec2_list = drm_malloc_ab(sizeof(*exec2_list), args->buffer_count); | |
3976 | if (exec2_list == NULL) { | |
3977 | DRM_ERROR("Failed to allocate exec list for %d buffers\n", | |
3978 | args->buffer_count); | |
3979 | return -ENOMEM; | |
3980 | } | |
3981 | ret = copy_from_user(exec2_list, | |
3982 | (struct drm_i915_relocation_entry __user *) | |
3983 | (uintptr_t) args->buffers_ptr, | |
3984 | sizeof(*exec2_list) * args->buffer_count); | |
3985 | if (ret != 0) { | |
3986 | DRM_ERROR("copy %d exec entries failed %d\n", | |
3987 | args->buffer_count, ret); | |
3988 | drm_free_large(exec2_list); | |
3989 | return -EFAULT; | |
3990 | } | |
3991 | ||
3992 | ret = i915_gem_do_execbuffer(dev, data, file_priv, args, exec2_list); | |
3993 | if (!ret) { | |
3994 | /* Copy the new buffer offsets back to the user's exec list. */ | |
3995 | ret = copy_to_user((struct drm_i915_relocation_entry __user *) | |
3996 | (uintptr_t) args->buffers_ptr, | |
3997 | exec2_list, | |
3998 | sizeof(*exec2_list) * args->buffer_count); | |
3999 | if (ret) { | |
4000 | ret = -EFAULT; | |
4001 | DRM_ERROR("failed to copy %d exec entries " | |
4002 | "back to user (%d)\n", | |
4003 | args->buffer_count, ret); | |
4004 | } | |
4005 | } | |
4006 | ||
4007 | drm_free_large(exec2_list); | |
4008 | return ret; | |
4009 | } | |
4010 | ||
673a394b EA |
4011 | int |
4012 | i915_gem_object_pin(struct drm_gem_object *obj, uint32_t alignment) | |
4013 | { | |
4014 | struct drm_device *dev = obj->dev; | |
23010e43 | 4015 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
673a394b EA |
4016 | int ret; |
4017 | ||
778c3544 DV |
4018 | BUG_ON(obj_priv->pin_count == DRM_I915_GEM_OBJECT_MAX_PIN_COUNT); |
4019 | ||
673a394b | 4020 | i915_verify_inactive(dev, __FILE__, __LINE__); |
ac0c6b5a CW |
4021 | |
4022 | if (obj_priv->gtt_space != NULL) { | |
4023 | if (alignment == 0) | |
4024 | alignment = i915_gem_get_gtt_alignment(obj); | |
4025 | if (obj_priv->gtt_offset & (alignment - 1)) { | |
ae7d49d8 CW |
4026 | WARN(obj_priv->pin_count, |
4027 | "bo is already pinned with incorrect alignment:" | |
4028 | " offset=%x, req.alignment=%x\n", | |
4029 | obj_priv->gtt_offset, alignment); | |
ac0c6b5a CW |
4030 | ret = i915_gem_object_unbind(obj); |
4031 | if (ret) | |
4032 | return ret; | |
4033 | } | |
4034 | } | |
4035 | ||
673a394b EA |
4036 | if (obj_priv->gtt_space == NULL) { |
4037 | ret = i915_gem_object_bind_to_gtt(obj, alignment); | |
9731129c | 4038 | if (ret) |
673a394b | 4039 | return ret; |
22c344e9 | 4040 | } |
76446cac | 4041 | |
673a394b EA |
4042 | obj_priv->pin_count++; |
4043 | ||
4044 | /* If the object is not active and not pending a flush, | |
4045 | * remove it from the inactive list | |
4046 | */ | |
4047 | if (obj_priv->pin_count == 1) { | |
4048 | atomic_inc(&dev->pin_count); | |
4049 | atomic_add(obj->size, &dev->pin_memory); | |
4050 | if (!obj_priv->active && | |
bf1a1092 | 4051 | (obj->write_domain & I915_GEM_GPU_DOMAINS) == 0) |
673a394b EA |
4052 | list_del_init(&obj_priv->list); |
4053 | } | |
4054 | i915_verify_inactive(dev, __FILE__, __LINE__); | |
4055 | ||
4056 | return 0; | |
4057 | } | |
4058 | ||
4059 | void | |
4060 | i915_gem_object_unpin(struct drm_gem_object *obj) | |
4061 | { | |
4062 | struct drm_device *dev = obj->dev; | |
4063 | drm_i915_private_t *dev_priv = dev->dev_private; | |
23010e43 | 4064 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
673a394b EA |
4065 | |
4066 | i915_verify_inactive(dev, __FILE__, __LINE__); | |
4067 | obj_priv->pin_count--; | |
4068 | BUG_ON(obj_priv->pin_count < 0); | |
4069 | BUG_ON(obj_priv->gtt_space == NULL); | |
4070 | ||
4071 | /* If the object is no longer pinned, and is | |
4072 | * neither active nor being flushed, then stick it on | |
4073 | * the inactive list | |
4074 | */ | |
4075 | if (obj_priv->pin_count == 0) { | |
4076 | if (!obj_priv->active && | |
21d509e3 | 4077 | (obj->write_domain & I915_GEM_GPU_DOMAINS) == 0) |
673a394b EA |
4078 | list_move_tail(&obj_priv->list, |
4079 | &dev_priv->mm.inactive_list); | |
4080 | atomic_dec(&dev->pin_count); | |
4081 | atomic_sub(obj->size, &dev->pin_memory); | |
4082 | } | |
4083 | i915_verify_inactive(dev, __FILE__, __LINE__); | |
4084 | } | |
4085 | ||
4086 | int | |
4087 | i915_gem_pin_ioctl(struct drm_device *dev, void *data, | |
4088 | struct drm_file *file_priv) | |
4089 | { | |
4090 | struct drm_i915_gem_pin *args = data; | |
4091 | struct drm_gem_object *obj; | |
4092 | struct drm_i915_gem_object *obj_priv; | |
4093 | int ret; | |
4094 | ||
4095 | mutex_lock(&dev->struct_mutex); | |
4096 | ||
4097 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); | |
4098 | if (obj == NULL) { | |
4099 | DRM_ERROR("Bad handle in i915_gem_pin_ioctl(): %d\n", | |
4100 | args->handle); | |
4101 | mutex_unlock(&dev->struct_mutex); | |
bf79cb91 | 4102 | return -ENOENT; |
673a394b | 4103 | } |
23010e43 | 4104 | obj_priv = to_intel_bo(obj); |
673a394b | 4105 | |
bb6baf76 CW |
4106 | if (obj_priv->madv != I915_MADV_WILLNEED) { |
4107 | DRM_ERROR("Attempting to pin a purgeable buffer\n"); | |
3ef94daa CW |
4108 | drm_gem_object_unreference(obj); |
4109 | mutex_unlock(&dev->struct_mutex); | |
4110 | return -EINVAL; | |
4111 | } | |
4112 | ||
79e53945 JB |
4113 | if (obj_priv->pin_filp != NULL && obj_priv->pin_filp != file_priv) { |
4114 | DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n", | |
4115 | args->handle); | |
96dec61d | 4116 | drm_gem_object_unreference(obj); |
673a394b | 4117 | mutex_unlock(&dev->struct_mutex); |
79e53945 JB |
4118 | return -EINVAL; |
4119 | } | |
4120 | ||
4121 | obj_priv->user_pin_count++; | |
4122 | obj_priv->pin_filp = file_priv; | |
4123 | if (obj_priv->user_pin_count == 1) { | |
4124 | ret = i915_gem_object_pin(obj, args->alignment); | |
4125 | if (ret != 0) { | |
4126 | drm_gem_object_unreference(obj); | |
4127 | mutex_unlock(&dev->struct_mutex); | |
4128 | return ret; | |
4129 | } | |
673a394b EA |
4130 | } |
4131 | ||
4132 | /* XXX - flush the CPU caches for pinned objects | |
4133 | * as the X server doesn't manage domains yet | |
4134 | */ | |
e47c68e9 | 4135 | i915_gem_object_flush_cpu_write_domain(obj); |
673a394b EA |
4136 | args->offset = obj_priv->gtt_offset; |
4137 | drm_gem_object_unreference(obj); | |
4138 | mutex_unlock(&dev->struct_mutex); | |
4139 | ||
4140 | return 0; | |
4141 | } | |
4142 | ||
4143 | int | |
4144 | i915_gem_unpin_ioctl(struct drm_device *dev, void *data, | |
4145 | struct drm_file *file_priv) | |
4146 | { | |
4147 | struct drm_i915_gem_pin *args = data; | |
4148 | struct drm_gem_object *obj; | |
79e53945 | 4149 | struct drm_i915_gem_object *obj_priv; |
673a394b EA |
4150 | |
4151 | mutex_lock(&dev->struct_mutex); | |
4152 | ||
4153 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); | |
4154 | if (obj == NULL) { | |
4155 | DRM_ERROR("Bad handle in i915_gem_unpin_ioctl(): %d\n", | |
4156 | args->handle); | |
4157 | mutex_unlock(&dev->struct_mutex); | |
bf79cb91 | 4158 | return -ENOENT; |
673a394b EA |
4159 | } |
4160 | ||
23010e43 | 4161 | obj_priv = to_intel_bo(obj); |
79e53945 JB |
4162 | if (obj_priv->pin_filp != file_priv) { |
4163 | DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n", | |
4164 | args->handle); | |
4165 | drm_gem_object_unreference(obj); | |
4166 | mutex_unlock(&dev->struct_mutex); | |
4167 | return -EINVAL; | |
4168 | } | |
4169 | obj_priv->user_pin_count--; | |
4170 | if (obj_priv->user_pin_count == 0) { | |
4171 | obj_priv->pin_filp = NULL; | |
4172 | i915_gem_object_unpin(obj); | |
4173 | } | |
673a394b EA |
4174 | |
4175 | drm_gem_object_unreference(obj); | |
4176 | mutex_unlock(&dev->struct_mutex); | |
4177 | return 0; | |
4178 | } | |
4179 | ||
4180 | int | |
4181 | i915_gem_busy_ioctl(struct drm_device *dev, void *data, | |
4182 | struct drm_file *file_priv) | |
4183 | { | |
4184 | struct drm_i915_gem_busy *args = data; | |
4185 | struct drm_gem_object *obj; | |
4186 | struct drm_i915_gem_object *obj_priv; | |
4187 | ||
673a394b EA |
4188 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); |
4189 | if (obj == NULL) { | |
4190 | DRM_ERROR("Bad handle in i915_gem_busy_ioctl(): %d\n", | |
4191 | args->handle); | |
bf79cb91 | 4192 | return -ENOENT; |
673a394b EA |
4193 | } |
4194 | ||
b1ce786c | 4195 | mutex_lock(&dev->struct_mutex); |
d1b851fc | 4196 | |
0be555b6 CW |
4197 | /* Count all active objects as busy, even if they are currently not used |
4198 | * by the gpu. Users of this interface expect objects to eventually | |
4199 | * become non-busy without any further actions, therefore emit any | |
4200 | * necessary flushes here. | |
c4de0a5d | 4201 | */ |
0be555b6 CW |
4202 | obj_priv = to_intel_bo(obj); |
4203 | args->busy = obj_priv->active; | |
4204 | if (args->busy) { | |
4205 | /* Unconditionally flush objects, even when the gpu still uses this | |
4206 | * object. Userspace calling this function indicates that it wants to | |
4207 | * use this buffer rather sooner than later, so issuing the required | |
4208 | * flush earlier is beneficial. | |
4209 | */ | |
4210 | if (obj->write_domain) { | |
4211 | i915_gem_flush(dev, 0, obj->write_domain); | |
8dc5d147 | 4212 | (void)i915_add_request(dev, file_priv, NULL, obj_priv->ring); |
0be555b6 CW |
4213 | } |
4214 | ||
4215 | /* Update the active list for the hardware's current position. | |
4216 | * Otherwise this only updates on a delayed timer or when irqs | |
4217 | * are actually unmasked, and our working set ends up being | |
4218 | * larger than required. | |
4219 | */ | |
4220 | i915_gem_retire_requests_ring(dev, obj_priv->ring); | |
4221 | ||
4222 | args->busy = obj_priv->active; | |
4223 | } | |
673a394b EA |
4224 | |
4225 | drm_gem_object_unreference(obj); | |
4226 | mutex_unlock(&dev->struct_mutex); | |
4227 | return 0; | |
4228 | } | |
4229 | ||
4230 | int | |
4231 | i915_gem_throttle_ioctl(struct drm_device *dev, void *data, | |
4232 | struct drm_file *file_priv) | |
4233 | { | |
4234 | return i915_gem_ring_throttle(dev, file_priv); | |
4235 | } | |
4236 | ||
3ef94daa CW |
4237 | int |
4238 | i915_gem_madvise_ioctl(struct drm_device *dev, void *data, | |
4239 | struct drm_file *file_priv) | |
4240 | { | |
4241 | struct drm_i915_gem_madvise *args = data; | |
4242 | struct drm_gem_object *obj; | |
4243 | struct drm_i915_gem_object *obj_priv; | |
4244 | ||
4245 | switch (args->madv) { | |
4246 | case I915_MADV_DONTNEED: | |
4247 | case I915_MADV_WILLNEED: | |
4248 | break; | |
4249 | default: | |
4250 | return -EINVAL; | |
4251 | } | |
4252 | ||
4253 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); | |
4254 | if (obj == NULL) { | |
4255 | DRM_ERROR("Bad handle in i915_gem_madvise_ioctl(): %d\n", | |
4256 | args->handle); | |
bf79cb91 | 4257 | return -ENOENT; |
3ef94daa CW |
4258 | } |
4259 | ||
4260 | mutex_lock(&dev->struct_mutex); | |
23010e43 | 4261 | obj_priv = to_intel_bo(obj); |
3ef94daa CW |
4262 | |
4263 | if (obj_priv->pin_count) { | |
4264 | drm_gem_object_unreference(obj); | |
4265 | mutex_unlock(&dev->struct_mutex); | |
4266 | ||
4267 | DRM_ERROR("Attempted i915_gem_madvise_ioctl() on a pinned object\n"); | |
4268 | return -EINVAL; | |
4269 | } | |
4270 | ||
bb6baf76 CW |
4271 | if (obj_priv->madv != __I915_MADV_PURGED) |
4272 | obj_priv->madv = args->madv; | |
3ef94daa | 4273 | |
2d7ef395 CW |
4274 | /* if the object is no longer bound, discard its backing storage */ |
4275 | if (i915_gem_object_is_purgeable(obj_priv) && | |
4276 | obj_priv->gtt_space == NULL) | |
4277 | i915_gem_object_truncate(obj); | |
4278 | ||
bb6baf76 CW |
4279 | args->retained = obj_priv->madv != __I915_MADV_PURGED; |
4280 | ||
3ef94daa CW |
4281 | drm_gem_object_unreference(obj); |
4282 | mutex_unlock(&dev->struct_mutex); | |
4283 | ||
4284 | return 0; | |
4285 | } | |
4286 | ||
ac52bc56 DV |
4287 | struct drm_gem_object * i915_gem_alloc_object(struct drm_device *dev, |
4288 | size_t size) | |
4289 | { | |
c397b908 | 4290 | struct drm_i915_gem_object *obj; |
ac52bc56 | 4291 | |
c397b908 DV |
4292 | obj = kzalloc(sizeof(*obj), GFP_KERNEL); |
4293 | if (obj == NULL) | |
4294 | return NULL; | |
673a394b | 4295 | |
c397b908 DV |
4296 | if (drm_gem_object_init(dev, &obj->base, size) != 0) { |
4297 | kfree(obj); | |
4298 | return NULL; | |
4299 | } | |
673a394b | 4300 | |
c397b908 DV |
4301 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; |
4302 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; | |
673a394b | 4303 | |
c397b908 | 4304 | obj->agp_type = AGP_USER_MEMORY; |
62b8b215 | 4305 | obj->base.driver_private = NULL; |
c397b908 DV |
4306 | obj->fence_reg = I915_FENCE_REG_NONE; |
4307 | INIT_LIST_HEAD(&obj->list); | |
4308 | INIT_LIST_HEAD(&obj->gpu_write_list); | |
c397b908 | 4309 | obj->madv = I915_MADV_WILLNEED; |
de151cf6 | 4310 | |
c397b908 DV |
4311 | trace_i915_gem_object_create(&obj->base); |
4312 | ||
4313 | return &obj->base; | |
4314 | } | |
4315 | ||
4316 | int i915_gem_init_object(struct drm_gem_object *obj) | |
4317 | { | |
4318 | BUG(); | |
de151cf6 | 4319 | |
673a394b EA |
4320 | return 0; |
4321 | } | |
4322 | ||
be72615b | 4323 | static void i915_gem_free_object_tail(struct drm_gem_object *obj) |
673a394b | 4324 | { |
de151cf6 | 4325 | struct drm_device *dev = obj->dev; |
be72615b | 4326 | drm_i915_private_t *dev_priv = dev->dev_private; |
23010e43 | 4327 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
be72615b | 4328 | int ret; |
673a394b | 4329 | |
be72615b CW |
4330 | ret = i915_gem_object_unbind(obj); |
4331 | if (ret == -ERESTARTSYS) { | |
4332 | list_move(&obj_priv->list, | |
4333 | &dev_priv->mm.deferred_free_list); | |
4334 | return; | |
4335 | } | |
673a394b | 4336 | |
7e616158 CW |
4337 | if (obj_priv->mmap_offset) |
4338 | i915_gem_free_mmap_offset(obj); | |
de151cf6 | 4339 | |
c397b908 DV |
4340 | drm_gem_object_release(obj); |
4341 | ||
9a298b2a | 4342 | kfree(obj_priv->page_cpu_valid); |
280b713b | 4343 | kfree(obj_priv->bit_17); |
c397b908 | 4344 | kfree(obj_priv); |
673a394b EA |
4345 | } |
4346 | ||
be72615b CW |
4347 | void i915_gem_free_object(struct drm_gem_object *obj) |
4348 | { | |
4349 | struct drm_device *dev = obj->dev; | |
4350 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); | |
4351 | ||
4352 | trace_i915_gem_object_destroy(obj); | |
4353 | ||
4354 | while (obj_priv->pin_count > 0) | |
4355 | i915_gem_object_unpin(obj); | |
4356 | ||
4357 | if (obj_priv->phys_obj) | |
4358 | i915_gem_detach_phys_object(dev, obj); | |
4359 | ||
4360 | i915_gem_free_object_tail(obj); | |
4361 | } | |
4362 | ||
29105ccc CW |
4363 | int |
4364 | i915_gem_idle(struct drm_device *dev) | |
4365 | { | |
4366 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4367 | int ret; | |
28dfe52a | 4368 | |
29105ccc | 4369 | mutex_lock(&dev->struct_mutex); |
1c5d22f7 | 4370 | |
8187a2b7 | 4371 | if (dev_priv->mm.suspended || |
d1b851fc ZN |
4372 | (dev_priv->render_ring.gem_object == NULL) || |
4373 | (HAS_BSD(dev) && | |
4374 | dev_priv->bsd_ring.gem_object == NULL)) { | |
29105ccc CW |
4375 | mutex_unlock(&dev->struct_mutex); |
4376 | return 0; | |
28dfe52a EA |
4377 | } |
4378 | ||
29105ccc | 4379 | ret = i915_gpu_idle(dev); |
6dbe2772 KP |
4380 | if (ret) { |
4381 | mutex_unlock(&dev->struct_mutex); | |
673a394b | 4382 | return ret; |
6dbe2772 | 4383 | } |
673a394b | 4384 | |
29105ccc CW |
4385 | /* Under UMS, be paranoid and evict. */ |
4386 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) { | |
b47eb4a2 | 4387 | ret = i915_gem_evict_inactive(dev); |
29105ccc CW |
4388 | if (ret) { |
4389 | mutex_unlock(&dev->struct_mutex); | |
4390 | return ret; | |
4391 | } | |
4392 | } | |
4393 | ||
4394 | /* Hack! Don't let anybody do execbuf while we don't control the chip. | |
4395 | * We need to replace this with a semaphore, or something. | |
4396 | * And not confound mm.suspended! | |
4397 | */ | |
4398 | dev_priv->mm.suspended = 1; | |
bc0c7f14 | 4399 | del_timer_sync(&dev_priv->hangcheck_timer); |
29105ccc CW |
4400 | |
4401 | i915_kernel_lost_context(dev); | |
6dbe2772 | 4402 | i915_gem_cleanup_ringbuffer(dev); |
29105ccc | 4403 | |
6dbe2772 KP |
4404 | mutex_unlock(&dev->struct_mutex); |
4405 | ||
29105ccc CW |
4406 | /* Cancel the retire work handler, which should be idle now. */ |
4407 | cancel_delayed_work_sync(&dev_priv->mm.retire_work); | |
4408 | ||
673a394b EA |
4409 | return 0; |
4410 | } | |
4411 | ||
e552eb70 JB |
4412 | /* |
4413 | * 965+ support PIPE_CONTROL commands, which provide finer grained control | |
4414 | * over cache flushing. | |
4415 | */ | |
8187a2b7 | 4416 | static int |
e552eb70 JB |
4417 | i915_gem_init_pipe_control(struct drm_device *dev) |
4418 | { | |
4419 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4420 | struct drm_gem_object *obj; | |
4421 | struct drm_i915_gem_object *obj_priv; | |
4422 | int ret; | |
4423 | ||
34dc4d44 | 4424 | obj = i915_gem_alloc_object(dev, 4096); |
e552eb70 JB |
4425 | if (obj == NULL) { |
4426 | DRM_ERROR("Failed to allocate seqno page\n"); | |
4427 | ret = -ENOMEM; | |
4428 | goto err; | |
4429 | } | |
4430 | obj_priv = to_intel_bo(obj); | |
4431 | obj_priv->agp_type = AGP_USER_CACHED_MEMORY; | |
4432 | ||
4433 | ret = i915_gem_object_pin(obj, 4096); | |
4434 | if (ret) | |
4435 | goto err_unref; | |
4436 | ||
4437 | dev_priv->seqno_gfx_addr = obj_priv->gtt_offset; | |
4438 | dev_priv->seqno_page = kmap(obj_priv->pages[0]); | |
4439 | if (dev_priv->seqno_page == NULL) | |
4440 | goto err_unpin; | |
4441 | ||
4442 | dev_priv->seqno_obj = obj; | |
4443 | memset(dev_priv->seqno_page, 0, PAGE_SIZE); | |
4444 | ||
4445 | return 0; | |
4446 | ||
4447 | err_unpin: | |
4448 | i915_gem_object_unpin(obj); | |
4449 | err_unref: | |
4450 | drm_gem_object_unreference(obj); | |
4451 | err: | |
4452 | return ret; | |
4453 | } | |
4454 | ||
8187a2b7 ZN |
4455 | |
4456 | static void | |
e552eb70 JB |
4457 | i915_gem_cleanup_pipe_control(struct drm_device *dev) |
4458 | { | |
4459 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4460 | struct drm_gem_object *obj; | |
4461 | struct drm_i915_gem_object *obj_priv; | |
4462 | ||
4463 | obj = dev_priv->seqno_obj; | |
4464 | obj_priv = to_intel_bo(obj); | |
4465 | kunmap(obj_priv->pages[0]); | |
4466 | i915_gem_object_unpin(obj); | |
4467 | drm_gem_object_unreference(obj); | |
4468 | dev_priv->seqno_obj = NULL; | |
4469 | ||
4470 | dev_priv->seqno_page = NULL; | |
673a394b EA |
4471 | } |
4472 | ||
8187a2b7 ZN |
4473 | int |
4474 | i915_gem_init_ringbuffer(struct drm_device *dev) | |
4475 | { | |
4476 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4477 | int ret; | |
68f95ba9 | 4478 | |
8187a2b7 | 4479 | dev_priv->render_ring = render_ring; |
68f95ba9 | 4480 | |
8187a2b7 ZN |
4481 | if (!I915_NEED_GFX_HWS(dev)) { |
4482 | dev_priv->render_ring.status_page.page_addr | |
4483 | = dev_priv->status_page_dmah->vaddr; | |
4484 | memset(dev_priv->render_ring.status_page.page_addr, | |
4485 | 0, PAGE_SIZE); | |
4486 | } | |
68f95ba9 | 4487 | |
8187a2b7 ZN |
4488 | if (HAS_PIPE_CONTROL(dev)) { |
4489 | ret = i915_gem_init_pipe_control(dev); | |
4490 | if (ret) | |
4491 | return ret; | |
4492 | } | |
68f95ba9 | 4493 | |
8187a2b7 | 4494 | ret = intel_init_ring_buffer(dev, &dev_priv->render_ring); |
68f95ba9 CW |
4495 | if (ret) |
4496 | goto cleanup_pipe_control; | |
4497 | ||
4498 | if (HAS_BSD(dev)) { | |
d1b851fc ZN |
4499 | dev_priv->bsd_ring = bsd_ring; |
4500 | ret = intel_init_ring_buffer(dev, &dev_priv->bsd_ring); | |
68f95ba9 CW |
4501 | if (ret) |
4502 | goto cleanup_render_ring; | |
d1b851fc | 4503 | } |
68f95ba9 | 4504 | |
6f392d54 CW |
4505 | dev_priv->next_seqno = 1; |
4506 | ||
68f95ba9 CW |
4507 | return 0; |
4508 | ||
4509 | cleanup_render_ring: | |
4510 | intel_cleanup_ring_buffer(dev, &dev_priv->render_ring); | |
4511 | cleanup_pipe_control: | |
4512 | if (HAS_PIPE_CONTROL(dev)) | |
4513 | i915_gem_cleanup_pipe_control(dev); | |
8187a2b7 ZN |
4514 | return ret; |
4515 | } | |
4516 | ||
4517 | void | |
4518 | i915_gem_cleanup_ringbuffer(struct drm_device *dev) | |
4519 | { | |
4520 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4521 | ||
4522 | intel_cleanup_ring_buffer(dev, &dev_priv->render_ring); | |
d1b851fc ZN |
4523 | if (HAS_BSD(dev)) |
4524 | intel_cleanup_ring_buffer(dev, &dev_priv->bsd_ring); | |
8187a2b7 ZN |
4525 | if (HAS_PIPE_CONTROL(dev)) |
4526 | i915_gem_cleanup_pipe_control(dev); | |
4527 | } | |
4528 | ||
673a394b EA |
4529 | int |
4530 | i915_gem_entervt_ioctl(struct drm_device *dev, void *data, | |
4531 | struct drm_file *file_priv) | |
4532 | { | |
4533 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4534 | int ret; | |
4535 | ||
79e53945 JB |
4536 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
4537 | return 0; | |
4538 | ||
ba1234d1 | 4539 | if (atomic_read(&dev_priv->mm.wedged)) { |
673a394b | 4540 | DRM_ERROR("Reenabling wedged hardware, good luck\n"); |
ba1234d1 | 4541 | atomic_set(&dev_priv->mm.wedged, 0); |
673a394b EA |
4542 | } |
4543 | ||
673a394b | 4544 | mutex_lock(&dev->struct_mutex); |
9bb2d6f9 EA |
4545 | dev_priv->mm.suspended = 0; |
4546 | ||
4547 | ret = i915_gem_init_ringbuffer(dev); | |
d816f6ac WF |
4548 | if (ret != 0) { |
4549 | mutex_unlock(&dev->struct_mutex); | |
9bb2d6f9 | 4550 | return ret; |
d816f6ac | 4551 | } |
9bb2d6f9 | 4552 | |
5e118f41 | 4553 | spin_lock(&dev_priv->mm.active_list_lock); |
852835f3 | 4554 | BUG_ON(!list_empty(&dev_priv->render_ring.active_list)); |
d1b851fc | 4555 | BUG_ON(HAS_BSD(dev) && !list_empty(&dev_priv->bsd_ring.active_list)); |
5e118f41 CW |
4556 | spin_unlock(&dev_priv->mm.active_list_lock); |
4557 | ||
673a394b EA |
4558 | BUG_ON(!list_empty(&dev_priv->mm.flushing_list)); |
4559 | BUG_ON(!list_empty(&dev_priv->mm.inactive_list)); | |
852835f3 | 4560 | BUG_ON(!list_empty(&dev_priv->render_ring.request_list)); |
d1b851fc | 4561 | BUG_ON(HAS_BSD(dev) && !list_empty(&dev_priv->bsd_ring.request_list)); |
673a394b | 4562 | mutex_unlock(&dev->struct_mutex); |
dbb19d30 | 4563 | |
5f35308b CW |
4564 | ret = drm_irq_install(dev); |
4565 | if (ret) | |
4566 | goto cleanup_ringbuffer; | |
dbb19d30 | 4567 | |
673a394b | 4568 | return 0; |
5f35308b CW |
4569 | |
4570 | cleanup_ringbuffer: | |
4571 | mutex_lock(&dev->struct_mutex); | |
4572 | i915_gem_cleanup_ringbuffer(dev); | |
4573 | dev_priv->mm.suspended = 1; | |
4574 | mutex_unlock(&dev->struct_mutex); | |
4575 | ||
4576 | return ret; | |
673a394b EA |
4577 | } |
4578 | ||
4579 | int | |
4580 | i915_gem_leavevt_ioctl(struct drm_device *dev, void *data, | |
4581 | struct drm_file *file_priv) | |
4582 | { | |
79e53945 JB |
4583 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
4584 | return 0; | |
4585 | ||
dbb19d30 | 4586 | drm_irq_uninstall(dev); |
e6890f6f | 4587 | return i915_gem_idle(dev); |
673a394b EA |
4588 | } |
4589 | ||
4590 | void | |
4591 | i915_gem_lastclose(struct drm_device *dev) | |
4592 | { | |
4593 | int ret; | |
673a394b | 4594 | |
e806b495 EA |
4595 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
4596 | return; | |
4597 | ||
6dbe2772 KP |
4598 | ret = i915_gem_idle(dev); |
4599 | if (ret) | |
4600 | DRM_ERROR("failed to idle hardware: %d\n", ret); | |
673a394b EA |
4601 | } |
4602 | ||
4603 | void | |
4604 | i915_gem_load(struct drm_device *dev) | |
4605 | { | |
b5aa8a0f | 4606 | int i; |
673a394b EA |
4607 | drm_i915_private_t *dev_priv = dev->dev_private; |
4608 | ||
5e118f41 | 4609 | spin_lock_init(&dev_priv->mm.active_list_lock); |
673a394b | 4610 | INIT_LIST_HEAD(&dev_priv->mm.flushing_list); |
99fcb766 | 4611 | INIT_LIST_HEAD(&dev_priv->mm.gpu_write_list); |
673a394b | 4612 | INIT_LIST_HEAD(&dev_priv->mm.inactive_list); |
a09ba7fa | 4613 | INIT_LIST_HEAD(&dev_priv->mm.fence_list); |
be72615b | 4614 | INIT_LIST_HEAD(&dev_priv->mm.deferred_free_list); |
852835f3 ZN |
4615 | INIT_LIST_HEAD(&dev_priv->render_ring.active_list); |
4616 | INIT_LIST_HEAD(&dev_priv->render_ring.request_list); | |
d1b851fc ZN |
4617 | if (HAS_BSD(dev)) { |
4618 | INIT_LIST_HEAD(&dev_priv->bsd_ring.active_list); | |
4619 | INIT_LIST_HEAD(&dev_priv->bsd_ring.request_list); | |
4620 | } | |
007cc8ac DV |
4621 | for (i = 0; i < 16; i++) |
4622 | INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list); | |
673a394b EA |
4623 | INIT_DELAYED_WORK(&dev_priv->mm.retire_work, |
4624 | i915_gem_retire_work_handler); | |
31169714 CW |
4625 | spin_lock(&shrink_list_lock); |
4626 | list_add(&dev_priv->mm.shrink_list, &shrink_list); | |
4627 | spin_unlock(&shrink_list_lock); | |
4628 | ||
94400120 DA |
4629 | /* On GEN3 we really need to make sure the ARB C3 LP bit is set */ |
4630 | if (IS_GEN3(dev)) { | |
4631 | u32 tmp = I915_READ(MI_ARB_STATE); | |
4632 | if (!(tmp & MI_ARB_C3_LP_WRITE_ENABLE)) { | |
4633 | /* arb state is a masked write, so set bit + bit in mask */ | |
4634 | tmp = MI_ARB_C3_LP_WRITE_ENABLE | (MI_ARB_C3_LP_WRITE_ENABLE << MI_ARB_MASK_SHIFT); | |
4635 | I915_WRITE(MI_ARB_STATE, tmp); | |
4636 | } | |
4637 | } | |
4638 | ||
de151cf6 | 4639 | /* Old X drivers will take 0-2 for front, back, depth buffers */ |
b397c836 EA |
4640 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) |
4641 | dev_priv->fence_reg_start = 3; | |
de151cf6 | 4642 | |
0f973f27 | 4643 | if (IS_I965G(dev) || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) |
de151cf6 JB |
4644 | dev_priv->num_fence_regs = 16; |
4645 | else | |
4646 | dev_priv->num_fence_regs = 8; | |
4647 | ||
b5aa8a0f GH |
4648 | /* Initialize fence registers to zero */ |
4649 | if (IS_I965G(dev)) { | |
4650 | for (i = 0; i < 16; i++) | |
4651 | I915_WRITE64(FENCE_REG_965_0 + (i * 8), 0); | |
4652 | } else { | |
4653 | for (i = 0; i < 8; i++) | |
4654 | I915_WRITE(FENCE_REG_830_0 + (i * 4), 0); | |
4655 | if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) | |
4656 | for (i = 0; i < 8; i++) | |
4657 | I915_WRITE(FENCE_REG_945_8 + (i * 4), 0); | |
4658 | } | |
673a394b | 4659 | i915_gem_detect_bit_6_swizzle(dev); |
6b95a207 | 4660 | init_waitqueue_head(&dev_priv->pending_flip_queue); |
673a394b | 4661 | } |
71acb5eb DA |
4662 | |
4663 | /* | |
4664 | * Create a physically contiguous memory object for this object | |
4665 | * e.g. for cursor + overlay regs | |
4666 | */ | |
4667 | int i915_gem_init_phys_object(struct drm_device *dev, | |
6eeefaf3 | 4668 | int id, int size, int align) |
71acb5eb DA |
4669 | { |
4670 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4671 | struct drm_i915_gem_phys_object *phys_obj; | |
4672 | int ret; | |
4673 | ||
4674 | if (dev_priv->mm.phys_objs[id - 1] || !size) | |
4675 | return 0; | |
4676 | ||
9a298b2a | 4677 | phys_obj = kzalloc(sizeof(struct drm_i915_gem_phys_object), GFP_KERNEL); |
71acb5eb DA |
4678 | if (!phys_obj) |
4679 | return -ENOMEM; | |
4680 | ||
4681 | phys_obj->id = id; | |
4682 | ||
6eeefaf3 | 4683 | phys_obj->handle = drm_pci_alloc(dev, size, align); |
71acb5eb DA |
4684 | if (!phys_obj->handle) { |
4685 | ret = -ENOMEM; | |
4686 | goto kfree_obj; | |
4687 | } | |
4688 | #ifdef CONFIG_X86 | |
4689 | set_memory_wc((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE); | |
4690 | #endif | |
4691 | ||
4692 | dev_priv->mm.phys_objs[id - 1] = phys_obj; | |
4693 | ||
4694 | return 0; | |
4695 | kfree_obj: | |
9a298b2a | 4696 | kfree(phys_obj); |
71acb5eb DA |
4697 | return ret; |
4698 | } | |
4699 | ||
4700 | void i915_gem_free_phys_object(struct drm_device *dev, int id) | |
4701 | { | |
4702 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4703 | struct drm_i915_gem_phys_object *phys_obj; | |
4704 | ||
4705 | if (!dev_priv->mm.phys_objs[id - 1]) | |
4706 | return; | |
4707 | ||
4708 | phys_obj = dev_priv->mm.phys_objs[id - 1]; | |
4709 | if (phys_obj->cur_obj) { | |
4710 | i915_gem_detach_phys_object(dev, phys_obj->cur_obj); | |
4711 | } | |
4712 | ||
4713 | #ifdef CONFIG_X86 | |
4714 | set_memory_wb((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE); | |
4715 | #endif | |
4716 | drm_pci_free(dev, phys_obj->handle); | |
4717 | kfree(phys_obj); | |
4718 | dev_priv->mm.phys_objs[id - 1] = NULL; | |
4719 | } | |
4720 | ||
4721 | void i915_gem_free_all_phys_object(struct drm_device *dev) | |
4722 | { | |
4723 | int i; | |
4724 | ||
260883c8 | 4725 | for (i = I915_GEM_PHYS_CURSOR_0; i <= I915_MAX_PHYS_OBJECT; i++) |
71acb5eb DA |
4726 | i915_gem_free_phys_object(dev, i); |
4727 | } | |
4728 | ||
4729 | void i915_gem_detach_phys_object(struct drm_device *dev, | |
4730 | struct drm_gem_object *obj) | |
4731 | { | |
4732 | struct drm_i915_gem_object *obj_priv; | |
4733 | int i; | |
4734 | int ret; | |
4735 | int page_count; | |
4736 | ||
23010e43 | 4737 | obj_priv = to_intel_bo(obj); |
71acb5eb DA |
4738 | if (!obj_priv->phys_obj) |
4739 | return; | |
4740 | ||
4bdadb97 | 4741 | ret = i915_gem_object_get_pages(obj, 0); |
71acb5eb DA |
4742 | if (ret) |
4743 | goto out; | |
4744 | ||
4745 | page_count = obj->size / PAGE_SIZE; | |
4746 | ||
4747 | for (i = 0; i < page_count; i++) { | |
856fa198 | 4748 | char *dst = kmap_atomic(obj_priv->pages[i], KM_USER0); |
71acb5eb DA |
4749 | char *src = obj_priv->phys_obj->handle->vaddr + (i * PAGE_SIZE); |
4750 | ||
4751 | memcpy(dst, src, PAGE_SIZE); | |
4752 | kunmap_atomic(dst, KM_USER0); | |
4753 | } | |
856fa198 | 4754 | drm_clflush_pages(obj_priv->pages, page_count); |
71acb5eb | 4755 | drm_agp_chipset_flush(dev); |
d78b47b9 CW |
4756 | |
4757 | i915_gem_object_put_pages(obj); | |
71acb5eb DA |
4758 | out: |
4759 | obj_priv->phys_obj->cur_obj = NULL; | |
4760 | obj_priv->phys_obj = NULL; | |
4761 | } | |
4762 | ||
4763 | int | |
4764 | i915_gem_attach_phys_object(struct drm_device *dev, | |
6eeefaf3 CW |
4765 | struct drm_gem_object *obj, |
4766 | int id, | |
4767 | int align) | |
71acb5eb DA |
4768 | { |
4769 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4770 | struct drm_i915_gem_object *obj_priv; | |
4771 | int ret = 0; | |
4772 | int page_count; | |
4773 | int i; | |
4774 | ||
4775 | if (id > I915_MAX_PHYS_OBJECT) | |
4776 | return -EINVAL; | |
4777 | ||
23010e43 | 4778 | obj_priv = to_intel_bo(obj); |
71acb5eb DA |
4779 | |
4780 | if (obj_priv->phys_obj) { | |
4781 | if (obj_priv->phys_obj->id == id) | |
4782 | return 0; | |
4783 | i915_gem_detach_phys_object(dev, obj); | |
4784 | } | |
4785 | ||
71acb5eb DA |
4786 | /* create a new object */ |
4787 | if (!dev_priv->mm.phys_objs[id - 1]) { | |
4788 | ret = i915_gem_init_phys_object(dev, id, | |
6eeefaf3 | 4789 | obj->size, align); |
71acb5eb | 4790 | if (ret) { |
aeb565df | 4791 | DRM_ERROR("failed to init phys object %d size: %zu\n", id, obj->size); |
71acb5eb DA |
4792 | goto out; |
4793 | } | |
4794 | } | |
4795 | ||
4796 | /* bind to the object */ | |
4797 | obj_priv->phys_obj = dev_priv->mm.phys_objs[id - 1]; | |
4798 | obj_priv->phys_obj->cur_obj = obj; | |
4799 | ||
4bdadb97 | 4800 | ret = i915_gem_object_get_pages(obj, 0); |
71acb5eb DA |
4801 | if (ret) { |
4802 | DRM_ERROR("failed to get page list\n"); | |
4803 | goto out; | |
4804 | } | |
4805 | ||
4806 | page_count = obj->size / PAGE_SIZE; | |
4807 | ||
4808 | for (i = 0; i < page_count; i++) { | |
856fa198 | 4809 | char *src = kmap_atomic(obj_priv->pages[i], KM_USER0); |
71acb5eb DA |
4810 | char *dst = obj_priv->phys_obj->handle->vaddr + (i * PAGE_SIZE); |
4811 | ||
4812 | memcpy(dst, src, PAGE_SIZE); | |
4813 | kunmap_atomic(src, KM_USER0); | |
4814 | } | |
4815 | ||
d78b47b9 CW |
4816 | i915_gem_object_put_pages(obj); |
4817 | ||
71acb5eb DA |
4818 | return 0; |
4819 | out: | |
4820 | return ret; | |
4821 | } | |
4822 | ||
4823 | static int | |
4824 | i915_gem_phys_pwrite(struct drm_device *dev, struct drm_gem_object *obj, | |
4825 | struct drm_i915_gem_pwrite *args, | |
4826 | struct drm_file *file_priv) | |
4827 | { | |
23010e43 | 4828 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
71acb5eb DA |
4829 | void *obj_addr; |
4830 | int ret; | |
4831 | char __user *user_data; | |
4832 | ||
4833 | user_data = (char __user *) (uintptr_t) args->data_ptr; | |
4834 | obj_addr = obj_priv->phys_obj->handle->vaddr + args->offset; | |
4835 | ||
44d98a61 | 4836 | DRM_DEBUG_DRIVER("obj_addr %p, %lld\n", obj_addr, args->size); |
71acb5eb DA |
4837 | ret = copy_from_user(obj_addr, user_data, args->size); |
4838 | if (ret) | |
4839 | return -EFAULT; | |
4840 | ||
4841 | drm_agp_chipset_flush(dev); | |
4842 | return 0; | |
4843 | } | |
b962442e EA |
4844 | |
4845 | void i915_gem_release(struct drm_device * dev, struct drm_file *file_priv) | |
4846 | { | |
4847 | struct drm_i915_file_private *i915_file_priv = file_priv->driver_priv; | |
4848 | ||
4849 | /* Clean up our request list when the client is going away, so that | |
4850 | * later retire_requests won't dereference our soon-to-be-gone | |
4851 | * file_priv. | |
4852 | */ | |
4853 | mutex_lock(&dev->struct_mutex); | |
4854 | while (!list_empty(&i915_file_priv->mm.request_list)) | |
4855 | list_del_init(i915_file_priv->mm.request_list.next); | |
4856 | mutex_unlock(&dev->struct_mutex); | |
4857 | } | |
31169714 | 4858 | |
1637ef41 CW |
4859 | static int |
4860 | i915_gpu_is_active(struct drm_device *dev) | |
4861 | { | |
4862 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4863 | int lists_empty; | |
4864 | ||
4865 | spin_lock(&dev_priv->mm.active_list_lock); | |
4866 | lists_empty = list_empty(&dev_priv->mm.flushing_list) && | |
852835f3 | 4867 | list_empty(&dev_priv->render_ring.active_list); |
d1b851fc ZN |
4868 | if (HAS_BSD(dev)) |
4869 | lists_empty &= list_empty(&dev_priv->bsd_ring.active_list); | |
1637ef41 CW |
4870 | spin_unlock(&dev_priv->mm.active_list_lock); |
4871 | ||
4872 | return !lists_empty; | |
4873 | } | |
4874 | ||
31169714 | 4875 | static int |
7f8275d0 | 4876 | i915_gem_shrink(struct shrinker *shrink, int nr_to_scan, gfp_t gfp_mask) |
31169714 CW |
4877 | { |
4878 | drm_i915_private_t *dev_priv, *next_dev; | |
4879 | struct drm_i915_gem_object *obj_priv, *next_obj; | |
4880 | int cnt = 0; | |
4881 | int would_deadlock = 1; | |
4882 | ||
4883 | /* "fast-path" to count number of available objects */ | |
4884 | if (nr_to_scan == 0) { | |
4885 | spin_lock(&shrink_list_lock); | |
4886 | list_for_each_entry(dev_priv, &shrink_list, mm.shrink_list) { | |
4887 | struct drm_device *dev = dev_priv->dev; | |
4888 | ||
4889 | if (mutex_trylock(&dev->struct_mutex)) { | |
4890 | list_for_each_entry(obj_priv, | |
4891 | &dev_priv->mm.inactive_list, | |
4892 | list) | |
4893 | cnt++; | |
4894 | mutex_unlock(&dev->struct_mutex); | |
4895 | } | |
4896 | } | |
4897 | spin_unlock(&shrink_list_lock); | |
4898 | ||
4899 | return (cnt / 100) * sysctl_vfs_cache_pressure; | |
4900 | } | |
4901 | ||
4902 | spin_lock(&shrink_list_lock); | |
4903 | ||
1637ef41 | 4904 | rescan: |
31169714 CW |
4905 | /* first scan for clean buffers */ |
4906 | list_for_each_entry_safe(dev_priv, next_dev, | |
4907 | &shrink_list, mm.shrink_list) { | |
4908 | struct drm_device *dev = dev_priv->dev; | |
4909 | ||
4910 | if (! mutex_trylock(&dev->struct_mutex)) | |
4911 | continue; | |
4912 | ||
4913 | spin_unlock(&shrink_list_lock); | |
b09a1fec | 4914 | i915_gem_retire_requests(dev); |
31169714 CW |
4915 | |
4916 | list_for_each_entry_safe(obj_priv, next_obj, | |
4917 | &dev_priv->mm.inactive_list, | |
4918 | list) { | |
4919 | if (i915_gem_object_is_purgeable(obj_priv)) { | |
a8089e84 | 4920 | i915_gem_object_unbind(&obj_priv->base); |
31169714 CW |
4921 | if (--nr_to_scan <= 0) |
4922 | break; | |
4923 | } | |
4924 | } | |
4925 | ||
4926 | spin_lock(&shrink_list_lock); | |
4927 | mutex_unlock(&dev->struct_mutex); | |
4928 | ||
963b4836 CW |
4929 | would_deadlock = 0; |
4930 | ||
31169714 CW |
4931 | if (nr_to_scan <= 0) |
4932 | break; | |
4933 | } | |
4934 | ||
4935 | /* second pass, evict/count anything still on the inactive list */ | |
4936 | list_for_each_entry_safe(dev_priv, next_dev, | |
4937 | &shrink_list, mm.shrink_list) { | |
4938 | struct drm_device *dev = dev_priv->dev; | |
4939 | ||
4940 | if (! mutex_trylock(&dev->struct_mutex)) | |
4941 | continue; | |
4942 | ||
4943 | spin_unlock(&shrink_list_lock); | |
4944 | ||
4945 | list_for_each_entry_safe(obj_priv, next_obj, | |
4946 | &dev_priv->mm.inactive_list, | |
4947 | list) { | |
4948 | if (nr_to_scan > 0) { | |
a8089e84 | 4949 | i915_gem_object_unbind(&obj_priv->base); |
31169714 CW |
4950 | nr_to_scan--; |
4951 | } else | |
4952 | cnt++; | |
4953 | } | |
4954 | ||
4955 | spin_lock(&shrink_list_lock); | |
4956 | mutex_unlock(&dev->struct_mutex); | |
4957 | ||
4958 | would_deadlock = 0; | |
4959 | } | |
4960 | ||
1637ef41 CW |
4961 | if (nr_to_scan) { |
4962 | int active = 0; | |
4963 | ||
4964 | /* | |
4965 | * We are desperate for pages, so as a last resort, wait | |
4966 | * for the GPU to finish and discard whatever we can. | |
4967 | * This has a dramatic impact to reduce the number of | |
4968 | * OOM-killer events whilst running the GPU aggressively. | |
4969 | */ | |
4970 | list_for_each_entry(dev_priv, &shrink_list, mm.shrink_list) { | |
4971 | struct drm_device *dev = dev_priv->dev; | |
4972 | ||
4973 | if (!mutex_trylock(&dev->struct_mutex)) | |
4974 | continue; | |
4975 | ||
4976 | spin_unlock(&shrink_list_lock); | |
4977 | ||
4978 | if (i915_gpu_is_active(dev)) { | |
4979 | i915_gpu_idle(dev); | |
4980 | active++; | |
4981 | } | |
4982 | ||
4983 | spin_lock(&shrink_list_lock); | |
4984 | mutex_unlock(&dev->struct_mutex); | |
4985 | } | |
4986 | ||
4987 | if (active) | |
4988 | goto rescan; | |
4989 | } | |
4990 | ||
31169714 CW |
4991 | spin_unlock(&shrink_list_lock); |
4992 | ||
4993 | if (would_deadlock) | |
4994 | return -1; | |
4995 | else if (cnt > 0) | |
4996 | return (cnt / 100) * sysctl_vfs_cache_pressure; | |
4997 | else | |
4998 | return 0; | |
4999 | } | |
5000 | ||
5001 | static struct shrinker shrinker = { | |
5002 | .shrink = i915_gem_shrink, | |
5003 | .seeks = DEFAULT_SEEKS, | |
5004 | }; | |
5005 | ||
5006 | __init void | |
5007 | i915_gem_shrinker_init(void) | |
5008 | { | |
5009 | register_shrinker(&shrinker); | |
5010 | } | |
5011 | ||
5012 | __exit void | |
5013 | i915_gem_shrinker_exit(void) | |
5014 | { | |
5015 | unregister_shrinker(&shrinker); | |
5016 | } |