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Commit | Line | Data |
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673a394b EA |
1 | /* |
2 | * Copyright © 2008 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | * | |
26 | */ | |
27 | ||
760285e7 | 28 | #include <drm/drmP.h> |
0de23977 | 29 | #include <drm/drm_vma_manager.h> |
760285e7 | 30 | #include <drm/i915_drm.h> |
673a394b | 31 | #include "i915_drv.h" |
1c5d22f7 | 32 | #include "i915_trace.h" |
652c393a | 33 | #include "intel_drv.h" |
5949eac4 | 34 | #include <linux/shmem_fs.h> |
5a0e3ad6 | 35 | #include <linux/slab.h> |
673a394b | 36 | #include <linux/swap.h> |
79e53945 | 37 | #include <linux/pci.h> |
1286ff73 | 38 | #include <linux/dma-buf.h> |
673a394b | 39 | |
05394f39 | 40 | static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj); |
2c22569b CW |
41 | static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj, |
42 | bool force); | |
07fe0b12 BW |
43 | static __must_check int |
44 | i915_gem_object_bind_to_vm(struct drm_i915_gem_object *obj, | |
45 | struct i915_address_space *vm, | |
46 | unsigned alignment, | |
47 | bool map_and_fenceable, | |
48 | bool nonblocking); | |
05394f39 CW |
49 | static int i915_gem_phys_pwrite(struct drm_device *dev, |
50 | struct drm_i915_gem_object *obj, | |
71acb5eb | 51 | struct drm_i915_gem_pwrite *args, |
05394f39 | 52 | struct drm_file *file); |
673a394b | 53 | |
61050808 CW |
54 | static void i915_gem_write_fence(struct drm_device *dev, int reg, |
55 | struct drm_i915_gem_object *obj); | |
56 | static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj, | |
57 | struct drm_i915_fence_reg *fence, | |
58 | bool enable); | |
59 | ||
17250b71 | 60 | static int i915_gem_inactive_shrink(struct shrinker *shrinker, |
1495f230 | 61 | struct shrink_control *sc); |
6c085a72 CW |
62 | static long i915_gem_purge(struct drm_i915_private *dev_priv, long target); |
63 | static void i915_gem_shrink_all(struct drm_i915_private *dev_priv); | |
8c59967c | 64 | static void i915_gem_object_truncate(struct drm_i915_gem_object *obj); |
31169714 | 65 | |
c76ce038 CW |
66 | static bool cpu_cache_is_coherent(struct drm_device *dev, |
67 | enum i915_cache_level level) | |
68 | { | |
69 | return HAS_LLC(dev) || level != I915_CACHE_NONE; | |
70 | } | |
71 | ||
2c22569b CW |
72 | static bool cpu_write_needs_clflush(struct drm_i915_gem_object *obj) |
73 | { | |
74 | if (!cpu_cache_is_coherent(obj->base.dev, obj->cache_level)) | |
75 | return true; | |
76 | ||
77 | return obj->pin_display; | |
78 | } | |
79 | ||
61050808 CW |
80 | static inline void i915_gem_object_fence_lost(struct drm_i915_gem_object *obj) |
81 | { | |
82 | if (obj->tiling_mode) | |
83 | i915_gem_release_mmap(obj); | |
84 | ||
85 | /* As we do not have an associated fence register, we will force | |
86 | * a tiling change if we ever need to acquire one. | |
87 | */ | |
5d82e3e6 | 88 | obj->fence_dirty = false; |
61050808 CW |
89 | obj->fence_reg = I915_FENCE_REG_NONE; |
90 | } | |
91 | ||
73aa808f CW |
92 | /* some bookkeeping */ |
93 | static void i915_gem_info_add_obj(struct drm_i915_private *dev_priv, | |
94 | size_t size) | |
95 | { | |
c20e8355 | 96 | spin_lock(&dev_priv->mm.object_stat_lock); |
73aa808f CW |
97 | dev_priv->mm.object_count++; |
98 | dev_priv->mm.object_memory += size; | |
c20e8355 | 99 | spin_unlock(&dev_priv->mm.object_stat_lock); |
73aa808f CW |
100 | } |
101 | ||
102 | static void i915_gem_info_remove_obj(struct drm_i915_private *dev_priv, | |
103 | size_t size) | |
104 | { | |
c20e8355 | 105 | spin_lock(&dev_priv->mm.object_stat_lock); |
73aa808f CW |
106 | dev_priv->mm.object_count--; |
107 | dev_priv->mm.object_memory -= size; | |
c20e8355 | 108 | spin_unlock(&dev_priv->mm.object_stat_lock); |
73aa808f CW |
109 | } |
110 | ||
21dd3734 | 111 | static int |
33196ded | 112 | i915_gem_wait_for_error(struct i915_gpu_error *error) |
30dbf0c0 | 113 | { |
30dbf0c0 CW |
114 | int ret; |
115 | ||
7abb690a DV |
116 | #define EXIT_COND (!i915_reset_in_progress(error) || \ |
117 | i915_terminally_wedged(error)) | |
1f83fee0 | 118 | if (EXIT_COND) |
30dbf0c0 CW |
119 | return 0; |
120 | ||
0a6759c6 DV |
121 | /* |
122 | * Only wait 10 seconds for the gpu reset to complete to avoid hanging | |
123 | * userspace. If it takes that long something really bad is going on and | |
124 | * we should simply try to bail out and fail as gracefully as possible. | |
125 | */ | |
1f83fee0 DV |
126 | ret = wait_event_interruptible_timeout(error->reset_queue, |
127 | EXIT_COND, | |
128 | 10*HZ); | |
0a6759c6 DV |
129 | if (ret == 0) { |
130 | DRM_ERROR("Timed out waiting for the gpu reset to complete\n"); | |
131 | return -EIO; | |
132 | } else if (ret < 0) { | |
30dbf0c0 | 133 | return ret; |
0a6759c6 | 134 | } |
1f83fee0 | 135 | #undef EXIT_COND |
30dbf0c0 | 136 | |
21dd3734 | 137 | return 0; |
30dbf0c0 CW |
138 | } |
139 | ||
54cf91dc | 140 | int i915_mutex_lock_interruptible(struct drm_device *dev) |
76c1dec1 | 141 | { |
33196ded | 142 | struct drm_i915_private *dev_priv = dev->dev_private; |
76c1dec1 CW |
143 | int ret; |
144 | ||
33196ded | 145 | ret = i915_gem_wait_for_error(&dev_priv->gpu_error); |
76c1dec1 CW |
146 | if (ret) |
147 | return ret; | |
148 | ||
149 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
150 | if (ret) | |
151 | return ret; | |
152 | ||
23bc5982 | 153 | WARN_ON(i915_verify_lists(dev)); |
76c1dec1 CW |
154 | return 0; |
155 | } | |
30dbf0c0 | 156 | |
7d1c4804 | 157 | static inline bool |
05394f39 | 158 | i915_gem_object_is_inactive(struct drm_i915_gem_object *obj) |
7d1c4804 | 159 | { |
9843877d | 160 | return i915_gem_obj_bound_any(obj) && !obj->active; |
7d1c4804 CW |
161 | } |
162 | ||
79e53945 JB |
163 | int |
164 | i915_gem_init_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 165 | struct drm_file *file) |
79e53945 | 166 | { |
93d18799 | 167 | struct drm_i915_private *dev_priv = dev->dev_private; |
79e53945 | 168 | struct drm_i915_gem_init *args = data; |
2021746e | 169 | |
7bb6fb8d DV |
170 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
171 | return -ENODEV; | |
172 | ||
2021746e CW |
173 | if (args->gtt_start >= args->gtt_end || |
174 | (args->gtt_end | args->gtt_start) & (PAGE_SIZE - 1)) | |
175 | return -EINVAL; | |
79e53945 | 176 | |
f534bc0b DV |
177 | /* GEM with user mode setting was never supported on ilk and later. */ |
178 | if (INTEL_INFO(dev)->gen >= 5) | |
179 | return -ENODEV; | |
180 | ||
79e53945 | 181 | mutex_lock(&dev->struct_mutex); |
d7e5008f BW |
182 | i915_gem_setup_global_gtt(dev, args->gtt_start, args->gtt_end, |
183 | args->gtt_end); | |
93d18799 | 184 | dev_priv->gtt.mappable_end = args->gtt_end; |
673a394b EA |
185 | mutex_unlock(&dev->struct_mutex); |
186 | ||
2021746e | 187 | return 0; |
673a394b EA |
188 | } |
189 | ||
5a125c3c EA |
190 | int |
191 | i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 192 | struct drm_file *file) |
5a125c3c | 193 | { |
73aa808f | 194 | struct drm_i915_private *dev_priv = dev->dev_private; |
5a125c3c | 195 | struct drm_i915_gem_get_aperture *args = data; |
6299f992 CW |
196 | struct drm_i915_gem_object *obj; |
197 | size_t pinned; | |
5a125c3c | 198 | |
6299f992 | 199 | pinned = 0; |
73aa808f | 200 | mutex_lock(&dev->struct_mutex); |
35c20a60 | 201 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) |
1b50247a | 202 | if (obj->pin_count) |
f343c5f6 | 203 | pinned += i915_gem_obj_ggtt_size(obj); |
73aa808f | 204 | mutex_unlock(&dev->struct_mutex); |
5a125c3c | 205 | |
853ba5d2 | 206 | args->aper_size = dev_priv->gtt.base.total; |
0206e353 | 207 | args->aper_available_size = args->aper_size - pinned; |
6299f992 | 208 | |
5a125c3c EA |
209 | return 0; |
210 | } | |
211 | ||
42dcedd4 CW |
212 | void *i915_gem_object_alloc(struct drm_device *dev) |
213 | { | |
214 | struct drm_i915_private *dev_priv = dev->dev_private; | |
fac15c10 | 215 | return kmem_cache_zalloc(dev_priv->slab, GFP_KERNEL); |
42dcedd4 CW |
216 | } |
217 | ||
218 | void i915_gem_object_free(struct drm_i915_gem_object *obj) | |
219 | { | |
220 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; | |
221 | kmem_cache_free(dev_priv->slab, obj); | |
222 | } | |
223 | ||
ff72145b DA |
224 | static int |
225 | i915_gem_create(struct drm_file *file, | |
226 | struct drm_device *dev, | |
227 | uint64_t size, | |
228 | uint32_t *handle_p) | |
673a394b | 229 | { |
05394f39 | 230 | struct drm_i915_gem_object *obj; |
a1a2d1d3 PP |
231 | int ret; |
232 | u32 handle; | |
673a394b | 233 | |
ff72145b | 234 | size = roundup(size, PAGE_SIZE); |
8ffc0246 CW |
235 | if (size == 0) |
236 | return -EINVAL; | |
673a394b EA |
237 | |
238 | /* Allocate the new object */ | |
ff72145b | 239 | obj = i915_gem_alloc_object(dev, size); |
673a394b EA |
240 | if (obj == NULL) |
241 | return -ENOMEM; | |
242 | ||
05394f39 | 243 | ret = drm_gem_handle_create(file, &obj->base, &handle); |
202f2fef | 244 | /* drop reference from allocate - handle holds it now */ |
d861e338 DV |
245 | drm_gem_object_unreference_unlocked(&obj->base); |
246 | if (ret) | |
247 | return ret; | |
202f2fef | 248 | |
ff72145b | 249 | *handle_p = handle; |
673a394b EA |
250 | return 0; |
251 | } | |
252 | ||
ff72145b DA |
253 | int |
254 | i915_gem_dumb_create(struct drm_file *file, | |
255 | struct drm_device *dev, | |
256 | struct drm_mode_create_dumb *args) | |
257 | { | |
258 | /* have to work out size/pitch and return them */ | |
ed0291fd | 259 | args->pitch = ALIGN(args->width * ((args->bpp + 7) / 8), 64); |
ff72145b DA |
260 | args->size = args->pitch * args->height; |
261 | return i915_gem_create(file, dev, | |
262 | args->size, &args->handle); | |
263 | } | |
264 | ||
ff72145b DA |
265 | /** |
266 | * Creates a new mm object and returns a handle to it. | |
267 | */ | |
268 | int | |
269 | i915_gem_create_ioctl(struct drm_device *dev, void *data, | |
270 | struct drm_file *file) | |
271 | { | |
272 | struct drm_i915_gem_create *args = data; | |
63ed2cb2 | 273 | |
ff72145b DA |
274 | return i915_gem_create(file, dev, |
275 | args->size, &args->handle); | |
276 | } | |
277 | ||
8461d226 DV |
278 | static inline int |
279 | __copy_to_user_swizzled(char __user *cpu_vaddr, | |
280 | const char *gpu_vaddr, int gpu_offset, | |
281 | int length) | |
282 | { | |
283 | int ret, cpu_offset = 0; | |
284 | ||
285 | while (length > 0) { | |
286 | int cacheline_end = ALIGN(gpu_offset + 1, 64); | |
287 | int this_length = min(cacheline_end - gpu_offset, length); | |
288 | int swizzled_gpu_offset = gpu_offset ^ 64; | |
289 | ||
290 | ret = __copy_to_user(cpu_vaddr + cpu_offset, | |
291 | gpu_vaddr + swizzled_gpu_offset, | |
292 | this_length); | |
293 | if (ret) | |
294 | return ret + length; | |
295 | ||
296 | cpu_offset += this_length; | |
297 | gpu_offset += this_length; | |
298 | length -= this_length; | |
299 | } | |
300 | ||
301 | return 0; | |
302 | } | |
303 | ||
8c59967c | 304 | static inline int |
4f0c7cfb BW |
305 | __copy_from_user_swizzled(char *gpu_vaddr, int gpu_offset, |
306 | const char __user *cpu_vaddr, | |
8c59967c DV |
307 | int length) |
308 | { | |
309 | int ret, cpu_offset = 0; | |
310 | ||
311 | while (length > 0) { | |
312 | int cacheline_end = ALIGN(gpu_offset + 1, 64); | |
313 | int this_length = min(cacheline_end - gpu_offset, length); | |
314 | int swizzled_gpu_offset = gpu_offset ^ 64; | |
315 | ||
316 | ret = __copy_from_user(gpu_vaddr + swizzled_gpu_offset, | |
317 | cpu_vaddr + cpu_offset, | |
318 | this_length); | |
319 | if (ret) | |
320 | return ret + length; | |
321 | ||
322 | cpu_offset += this_length; | |
323 | gpu_offset += this_length; | |
324 | length -= this_length; | |
325 | } | |
326 | ||
327 | return 0; | |
328 | } | |
329 | ||
d174bd64 DV |
330 | /* Per-page copy function for the shmem pread fastpath. |
331 | * Flushes invalid cachelines before reading the target if | |
332 | * needs_clflush is set. */ | |
eb01459f | 333 | static int |
d174bd64 DV |
334 | shmem_pread_fast(struct page *page, int shmem_page_offset, int page_length, |
335 | char __user *user_data, | |
336 | bool page_do_bit17_swizzling, bool needs_clflush) | |
337 | { | |
338 | char *vaddr; | |
339 | int ret; | |
340 | ||
e7e58eb5 | 341 | if (unlikely(page_do_bit17_swizzling)) |
d174bd64 DV |
342 | return -EINVAL; |
343 | ||
344 | vaddr = kmap_atomic(page); | |
345 | if (needs_clflush) | |
346 | drm_clflush_virt_range(vaddr + shmem_page_offset, | |
347 | page_length); | |
348 | ret = __copy_to_user_inatomic(user_data, | |
349 | vaddr + shmem_page_offset, | |
350 | page_length); | |
351 | kunmap_atomic(vaddr); | |
352 | ||
f60d7f0c | 353 | return ret ? -EFAULT : 0; |
d174bd64 DV |
354 | } |
355 | ||
23c18c71 DV |
356 | static void |
357 | shmem_clflush_swizzled_range(char *addr, unsigned long length, | |
358 | bool swizzled) | |
359 | { | |
e7e58eb5 | 360 | if (unlikely(swizzled)) { |
23c18c71 DV |
361 | unsigned long start = (unsigned long) addr; |
362 | unsigned long end = (unsigned long) addr + length; | |
363 | ||
364 | /* For swizzling simply ensure that we always flush both | |
365 | * channels. Lame, but simple and it works. Swizzled | |
366 | * pwrite/pread is far from a hotpath - current userspace | |
367 | * doesn't use it at all. */ | |
368 | start = round_down(start, 128); | |
369 | end = round_up(end, 128); | |
370 | ||
371 | drm_clflush_virt_range((void *)start, end - start); | |
372 | } else { | |
373 | drm_clflush_virt_range(addr, length); | |
374 | } | |
375 | ||
376 | } | |
377 | ||
d174bd64 DV |
378 | /* Only difference to the fast-path function is that this can handle bit17 |
379 | * and uses non-atomic copy and kmap functions. */ | |
380 | static int | |
381 | shmem_pread_slow(struct page *page, int shmem_page_offset, int page_length, | |
382 | char __user *user_data, | |
383 | bool page_do_bit17_swizzling, bool needs_clflush) | |
384 | { | |
385 | char *vaddr; | |
386 | int ret; | |
387 | ||
388 | vaddr = kmap(page); | |
389 | if (needs_clflush) | |
23c18c71 DV |
390 | shmem_clflush_swizzled_range(vaddr + shmem_page_offset, |
391 | page_length, | |
392 | page_do_bit17_swizzling); | |
d174bd64 DV |
393 | |
394 | if (page_do_bit17_swizzling) | |
395 | ret = __copy_to_user_swizzled(user_data, | |
396 | vaddr, shmem_page_offset, | |
397 | page_length); | |
398 | else | |
399 | ret = __copy_to_user(user_data, | |
400 | vaddr + shmem_page_offset, | |
401 | page_length); | |
402 | kunmap(page); | |
403 | ||
f60d7f0c | 404 | return ret ? - EFAULT : 0; |
d174bd64 DV |
405 | } |
406 | ||
eb01459f | 407 | static int |
dbf7bff0 DV |
408 | i915_gem_shmem_pread(struct drm_device *dev, |
409 | struct drm_i915_gem_object *obj, | |
410 | struct drm_i915_gem_pread *args, | |
411 | struct drm_file *file) | |
eb01459f | 412 | { |
8461d226 | 413 | char __user *user_data; |
eb01459f | 414 | ssize_t remain; |
8461d226 | 415 | loff_t offset; |
eb2c0c81 | 416 | int shmem_page_offset, page_length, ret = 0; |
8461d226 | 417 | int obj_do_bit17_swizzling, page_do_bit17_swizzling; |
96d79b52 | 418 | int prefaulted = 0; |
8489731c | 419 | int needs_clflush = 0; |
67d5a50c | 420 | struct sg_page_iter sg_iter; |
eb01459f | 421 | |
2bb4629a | 422 | user_data = to_user_ptr(args->data_ptr); |
eb01459f EA |
423 | remain = args->size; |
424 | ||
8461d226 | 425 | obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj); |
eb01459f | 426 | |
8489731c DV |
427 | if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU)) { |
428 | /* If we're not in the cpu read domain, set ourself into the gtt | |
429 | * read domain and manually flush cachelines (if required). This | |
430 | * optimizes for the case when the gpu will dirty the data | |
431 | * anyway again before the next pread happens. */ | |
c76ce038 | 432 | needs_clflush = !cpu_cache_is_coherent(dev, obj->cache_level); |
9843877d | 433 | if (i915_gem_obj_bound_any(obj)) { |
6c085a72 CW |
434 | ret = i915_gem_object_set_to_gtt_domain(obj, false); |
435 | if (ret) | |
436 | return ret; | |
437 | } | |
8489731c | 438 | } |
eb01459f | 439 | |
f60d7f0c CW |
440 | ret = i915_gem_object_get_pages(obj); |
441 | if (ret) | |
442 | return ret; | |
443 | ||
444 | i915_gem_object_pin_pages(obj); | |
445 | ||
8461d226 | 446 | offset = args->offset; |
eb01459f | 447 | |
67d5a50c ID |
448 | for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, |
449 | offset >> PAGE_SHIFT) { | |
2db76d7c | 450 | struct page *page = sg_page_iter_page(&sg_iter); |
9da3da66 CW |
451 | |
452 | if (remain <= 0) | |
453 | break; | |
454 | ||
eb01459f EA |
455 | /* Operation in this page |
456 | * | |
eb01459f | 457 | * shmem_page_offset = offset within page in shmem file |
eb01459f EA |
458 | * page_length = bytes to copy for this page |
459 | */ | |
c8cbbb8b | 460 | shmem_page_offset = offset_in_page(offset); |
eb01459f EA |
461 | page_length = remain; |
462 | if ((shmem_page_offset + page_length) > PAGE_SIZE) | |
463 | page_length = PAGE_SIZE - shmem_page_offset; | |
eb01459f | 464 | |
8461d226 DV |
465 | page_do_bit17_swizzling = obj_do_bit17_swizzling && |
466 | (page_to_phys(page) & (1 << 17)) != 0; | |
467 | ||
d174bd64 DV |
468 | ret = shmem_pread_fast(page, shmem_page_offset, page_length, |
469 | user_data, page_do_bit17_swizzling, | |
470 | needs_clflush); | |
471 | if (ret == 0) | |
472 | goto next_page; | |
dbf7bff0 | 473 | |
dbf7bff0 DV |
474 | mutex_unlock(&dev->struct_mutex); |
475 | ||
0b74b508 | 476 | if (likely(!i915_prefault_disable) && !prefaulted) { |
f56f821f | 477 | ret = fault_in_multipages_writeable(user_data, remain); |
96d79b52 DV |
478 | /* Userspace is tricking us, but we've already clobbered |
479 | * its pages with the prefault and promised to write the | |
480 | * data up to the first fault. Hence ignore any errors | |
481 | * and just continue. */ | |
482 | (void)ret; | |
483 | prefaulted = 1; | |
484 | } | |
eb01459f | 485 | |
d174bd64 DV |
486 | ret = shmem_pread_slow(page, shmem_page_offset, page_length, |
487 | user_data, page_do_bit17_swizzling, | |
488 | needs_clflush); | |
eb01459f | 489 | |
dbf7bff0 | 490 | mutex_lock(&dev->struct_mutex); |
f60d7f0c | 491 | |
dbf7bff0 | 492 | next_page: |
e5281ccd | 493 | mark_page_accessed(page); |
e5281ccd | 494 | |
f60d7f0c | 495 | if (ret) |
8461d226 | 496 | goto out; |
8461d226 | 497 | |
eb01459f | 498 | remain -= page_length; |
8461d226 | 499 | user_data += page_length; |
eb01459f EA |
500 | offset += page_length; |
501 | } | |
502 | ||
4f27b75d | 503 | out: |
f60d7f0c CW |
504 | i915_gem_object_unpin_pages(obj); |
505 | ||
eb01459f EA |
506 | return ret; |
507 | } | |
508 | ||
673a394b EA |
509 | /** |
510 | * Reads data from the object referenced by handle. | |
511 | * | |
512 | * On error, the contents of *data are undefined. | |
513 | */ | |
514 | int | |
515 | i915_gem_pread_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 516 | struct drm_file *file) |
673a394b EA |
517 | { |
518 | struct drm_i915_gem_pread *args = data; | |
05394f39 | 519 | struct drm_i915_gem_object *obj; |
35b62a89 | 520 | int ret = 0; |
673a394b | 521 | |
51311d0a CW |
522 | if (args->size == 0) |
523 | return 0; | |
524 | ||
525 | if (!access_ok(VERIFY_WRITE, | |
2bb4629a | 526 | to_user_ptr(args->data_ptr), |
51311d0a CW |
527 | args->size)) |
528 | return -EFAULT; | |
529 | ||
4f27b75d | 530 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 531 | if (ret) |
4f27b75d | 532 | return ret; |
673a394b | 533 | |
05394f39 | 534 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 535 | if (&obj->base == NULL) { |
1d7cfea1 CW |
536 | ret = -ENOENT; |
537 | goto unlock; | |
4f27b75d | 538 | } |
673a394b | 539 | |
7dcd2499 | 540 | /* Bounds check source. */ |
05394f39 CW |
541 | if (args->offset > obj->base.size || |
542 | args->size > obj->base.size - args->offset) { | |
ce9d419d | 543 | ret = -EINVAL; |
35b62a89 | 544 | goto out; |
ce9d419d CW |
545 | } |
546 | ||
1286ff73 DV |
547 | /* prime objects have no backing filp to GEM pread/pwrite |
548 | * pages from. | |
549 | */ | |
550 | if (!obj->base.filp) { | |
551 | ret = -EINVAL; | |
552 | goto out; | |
553 | } | |
554 | ||
db53a302 CW |
555 | trace_i915_gem_object_pread(obj, args->offset, args->size); |
556 | ||
dbf7bff0 | 557 | ret = i915_gem_shmem_pread(dev, obj, args, file); |
673a394b | 558 | |
35b62a89 | 559 | out: |
05394f39 | 560 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 561 | unlock: |
4f27b75d | 562 | mutex_unlock(&dev->struct_mutex); |
eb01459f | 563 | return ret; |
673a394b EA |
564 | } |
565 | ||
0839ccb8 KP |
566 | /* This is the fast write path which cannot handle |
567 | * page faults in the source data | |
9b7530cc | 568 | */ |
0839ccb8 KP |
569 | |
570 | static inline int | |
571 | fast_user_write(struct io_mapping *mapping, | |
572 | loff_t page_base, int page_offset, | |
573 | char __user *user_data, | |
574 | int length) | |
9b7530cc | 575 | { |
4f0c7cfb BW |
576 | void __iomem *vaddr_atomic; |
577 | void *vaddr; | |
0839ccb8 | 578 | unsigned long unwritten; |
9b7530cc | 579 | |
3e4d3af5 | 580 | vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base); |
4f0c7cfb BW |
581 | /* We can use the cpu mem copy function because this is X86. */ |
582 | vaddr = (void __force*)vaddr_atomic + page_offset; | |
583 | unwritten = __copy_from_user_inatomic_nocache(vaddr, | |
0839ccb8 | 584 | user_data, length); |
3e4d3af5 | 585 | io_mapping_unmap_atomic(vaddr_atomic); |
fbd5a26d | 586 | return unwritten; |
0839ccb8 KP |
587 | } |
588 | ||
3de09aa3 EA |
589 | /** |
590 | * This is the fast pwrite path, where we copy the data directly from the | |
591 | * user into the GTT, uncached. | |
592 | */ | |
673a394b | 593 | static int |
05394f39 CW |
594 | i915_gem_gtt_pwrite_fast(struct drm_device *dev, |
595 | struct drm_i915_gem_object *obj, | |
3de09aa3 | 596 | struct drm_i915_gem_pwrite *args, |
05394f39 | 597 | struct drm_file *file) |
673a394b | 598 | { |
0839ccb8 | 599 | drm_i915_private_t *dev_priv = dev->dev_private; |
673a394b | 600 | ssize_t remain; |
0839ccb8 | 601 | loff_t offset, page_base; |
673a394b | 602 | char __user *user_data; |
935aaa69 DV |
603 | int page_offset, page_length, ret; |
604 | ||
c37e2204 | 605 | ret = i915_gem_obj_ggtt_pin(obj, 0, true, true); |
935aaa69 DV |
606 | if (ret) |
607 | goto out; | |
608 | ||
609 | ret = i915_gem_object_set_to_gtt_domain(obj, true); | |
610 | if (ret) | |
611 | goto out_unpin; | |
612 | ||
613 | ret = i915_gem_object_put_fence(obj); | |
614 | if (ret) | |
615 | goto out_unpin; | |
673a394b | 616 | |
2bb4629a | 617 | user_data = to_user_ptr(args->data_ptr); |
673a394b | 618 | remain = args->size; |
673a394b | 619 | |
f343c5f6 | 620 | offset = i915_gem_obj_ggtt_offset(obj) + args->offset; |
673a394b EA |
621 | |
622 | while (remain > 0) { | |
623 | /* Operation in this page | |
624 | * | |
0839ccb8 KP |
625 | * page_base = page offset within aperture |
626 | * page_offset = offset within page | |
627 | * page_length = bytes to copy for this page | |
673a394b | 628 | */ |
c8cbbb8b CW |
629 | page_base = offset & PAGE_MASK; |
630 | page_offset = offset_in_page(offset); | |
0839ccb8 KP |
631 | page_length = remain; |
632 | if ((page_offset + remain) > PAGE_SIZE) | |
633 | page_length = PAGE_SIZE - page_offset; | |
634 | ||
0839ccb8 | 635 | /* If we get a fault while copying data, then (presumably) our |
3de09aa3 EA |
636 | * source page isn't available. Return the error and we'll |
637 | * retry in the slow path. | |
0839ccb8 | 638 | */ |
5d4545ae | 639 | if (fast_user_write(dev_priv->gtt.mappable, page_base, |
935aaa69 DV |
640 | page_offset, user_data, page_length)) { |
641 | ret = -EFAULT; | |
642 | goto out_unpin; | |
643 | } | |
673a394b | 644 | |
0839ccb8 KP |
645 | remain -= page_length; |
646 | user_data += page_length; | |
647 | offset += page_length; | |
673a394b | 648 | } |
673a394b | 649 | |
935aaa69 DV |
650 | out_unpin: |
651 | i915_gem_object_unpin(obj); | |
652 | out: | |
3de09aa3 | 653 | return ret; |
673a394b EA |
654 | } |
655 | ||
d174bd64 DV |
656 | /* Per-page copy function for the shmem pwrite fastpath. |
657 | * Flushes invalid cachelines before writing to the target if | |
658 | * needs_clflush_before is set and flushes out any written cachelines after | |
659 | * writing if needs_clflush is set. */ | |
3043c60c | 660 | static int |
d174bd64 DV |
661 | shmem_pwrite_fast(struct page *page, int shmem_page_offset, int page_length, |
662 | char __user *user_data, | |
663 | bool page_do_bit17_swizzling, | |
664 | bool needs_clflush_before, | |
665 | bool needs_clflush_after) | |
673a394b | 666 | { |
d174bd64 | 667 | char *vaddr; |
673a394b | 668 | int ret; |
3de09aa3 | 669 | |
e7e58eb5 | 670 | if (unlikely(page_do_bit17_swizzling)) |
d174bd64 | 671 | return -EINVAL; |
3de09aa3 | 672 | |
d174bd64 DV |
673 | vaddr = kmap_atomic(page); |
674 | if (needs_clflush_before) | |
675 | drm_clflush_virt_range(vaddr + shmem_page_offset, | |
676 | page_length); | |
677 | ret = __copy_from_user_inatomic_nocache(vaddr + shmem_page_offset, | |
678 | user_data, | |
679 | page_length); | |
680 | if (needs_clflush_after) | |
681 | drm_clflush_virt_range(vaddr + shmem_page_offset, | |
682 | page_length); | |
683 | kunmap_atomic(vaddr); | |
3de09aa3 | 684 | |
755d2218 | 685 | return ret ? -EFAULT : 0; |
3de09aa3 EA |
686 | } |
687 | ||
d174bd64 DV |
688 | /* Only difference to the fast-path function is that this can handle bit17 |
689 | * and uses non-atomic copy and kmap functions. */ | |
3043c60c | 690 | static int |
d174bd64 DV |
691 | shmem_pwrite_slow(struct page *page, int shmem_page_offset, int page_length, |
692 | char __user *user_data, | |
693 | bool page_do_bit17_swizzling, | |
694 | bool needs_clflush_before, | |
695 | bool needs_clflush_after) | |
673a394b | 696 | { |
d174bd64 DV |
697 | char *vaddr; |
698 | int ret; | |
e5281ccd | 699 | |
d174bd64 | 700 | vaddr = kmap(page); |
e7e58eb5 | 701 | if (unlikely(needs_clflush_before || page_do_bit17_swizzling)) |
23c18c71 DV |
702 | shmem_clflush_swizzled_range(vaddr + shmem_page_offset, |
703 | page_length, | |
704 | page_do_bit17_swizzling); | |
d174bd64 DV |
705 | if (page_do_bit17_swizzling) |
706 | ret = __copy_from_user_swizzled(vaddr, shmem_page_offset, | |
e5281ccd CW |
707 | user_data, |
708 | page_length); | |
d174bd64 DV |
709 | else |
710 | ret = __copy_from_user(vaddr + shmem_page_offset, | |
711 | user_data, | |
712 | page_length); | |
713 | if (needs_clflush_after) | |
23c18c71 DV |
714 | shmem_clflush_swizzled_range(vaddr + shmem_page_offset, |
715 | page_length, | |
716 | page_do_bit17_swizzling); | |
d174bd64 | 717 | kunmap(page); |
40123c1f | 718 | |
755d2218 | 719 | return ret ? -EFAULT : 0; |
40123c1f EA |
720 | } |
721 | ||
40123c1f | 722 | static int |
e244a443 DV |
723 | i915_gem_shmem_pwrite(struct drm_device *dev, |
724 | struct drm_i915_gem_object *obj, | |
725 | struct drm_i915_gem_pwrite *args, | |
726 | struct drm_file *file) | |
40123c1f | 727 | { |
40123c1f | 728 | ssize_t remain; |
8c59967c DV |
729 | loff_t offset; |
730 | char __user *user_data; | |
eb2c0c81 | 731 | int shmem_page_offset, page_length, ret = 0; |
8c59967c | 732 | int obj_do_bit17_swizzling, page_do_bit17_swizzling; |
e244a443 | 733 | int hit_slowpath = 0; |
58642885 DV |
734 | int needs_clflush_after = 0; |
735 | int needs_clflush_before = 0; | |
67d5a50c | 736 | struct sg_page_iter sg_iter; |
40123c1f | 737 | |
2bb4629a | 738 | user_data = to_user_ptr(args->data_ptr); |
40123c1f EA |
739 | remain = args->size; |
740 | ||
8c59967c | 741 | obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj); |
40123c1f | 742 | |
58642885 DV |
743 | if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) { |
744 | /* If we're not in the cpu write domain, set ourself into the gtt | |
745 | * write domain and manually flush cachelines (if required). This | |
746 | * optimizes for the case when the gpu will use the data | |
747 | * right away and we therefore have to clflush anyway. */ | |
2c22569b | 748 | needs_clflush_after = cpu_write_needs_clflush(obj); |
9843877d | 749 | if (i915_gem_obj_bound_any(obj)) { |
6c085a72 CW |
750 | ret = i915_gem_object_set_to_gtt_domain(obj, true); |
751 | if (ret) | |
752 | return ret; | |
753 | } | |
58642885 | 754 | } |
c76ce038 CW |
755 | /* Same trick applies to invalidate partially written cachelines read |
756 | * before writing. */ | |
757 | if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) | |
758 | needs_clflush_before = | |
759 | !cpu_cache_is_coherent(dev, obj->cache_level); | |
58642885 | 760 | |
755d2218 CW |
761 | ret = i915_gem_object_get_pages(obj); |
762 | if (ret) | |
763 | return ret; | |
764 | ||
765 | i915_gem_object_pin_pages(obj); | |
766 | ||
673a394b | 767 | offset = args->offset; |
05394f39 | 768 | obj->dirty = 1; |
673a394b | 769 | |
67d5a50c ID |
770 | for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, |
771 | offset >> PAGE_SHIFT) { | |
2db76d7c | 772 | struct page *page = sg_page_iter_page(&sg_iter); |
58642885 | 773 | int partial_cacheline_write; |
e5281ccd | 774 | |
9da3da66 CW |
775 | if (remain <= 0) |
776 | break; | |
777 | ||
40123c1f EA |
778 | /* Operation in this page |
779 | * | |
40123c1f | 780 | * shmem_page_offset = offset within page in shmem file |
40123c1f EA |
781 | * page_length = bytes to copy for this page |
782 | */ | |
c8cbbb8b | 783 | shmem_page_offset = offset_in_page(offset); |
40123c1f EA |
784 | |
785 | page_length = remain; | |
786 | if ((shmem_page_offset + page_length) > PAGE_SIZE) | |
787 | page_length = PAGE_SIZE - shmem_page_offset; | |
40123c1f | 788 | |
58642885 DV |
789 | /* If we don't overwrite a cacheline completely we need to be |
790 | * careful to have up-to-date data by first clflushing. Don't | |
791 | * overcomplicate things and flush the entire patch. */ | |
792 | partial_cacheline_write = needs_clflush_before && | |
793 | ((shmem_page_offset | page_length) | |
794 | & (boot_cpu_data.x86_clflush_size - 1)); | |
795 | ||
8c59967c DV |
796 | page_do_bit17_swizzling = obj_do_bit17_swizzling && |
797 | (page_to_phys(page) & (1 << 17)) != 0; | |
798 | ||
d174bd64 DV |
799 | ret = shmem_pwrite_fast(page, shmem_page_offset, page_length, |
800 | user_data, page_do_bit17_swizzling, | |
801 | partial_cacheline_write, | |
802 | needs_clflush_after); | |
803 | if (ret == 0) | |
804 | goto next_page; | |
e244a443 DV |
805 | |
806 | hit_slowpath = 1; | |
e244a443 | 807 | mutex_unlock(&dev->struct_mutex); |
d174bd64 DV |
808 | ret = shmem_pwrite_slow(page, shmem_page_offset, page_length, |
809 | user_data, page_do_bit17_swizzling, | |
810 | partial_cacheline_write, | |
811 | needs_clflush_after); | |
40123c1f | 812 | |
e244a443 | 813 | mutex_lock(&dev->struct_mutex); |
755d2218 | 814 | |
e244a443 | 815 | next_page: |
e5281ccd CW |
816 | set_page_dirty(page); |
817 | mark_page_accessed(page); | |
e5281ccd | 818 | |
755d2218 | 819 | if (ret) |
8c59967c | 820 | goto out; |
8c59967c | 821 | |
40123c1f | 822 | remain -= page_length; |
8c59967c | 823 | user_data += page_length; |
40123c1f | 824 | offset += page_length; |
673a394b EA |
825 | } |
826 | ||
fbd5a26d | 827 | out: |
755d2218 CW |
828 | i915_gem_object_unpin_pages(obj); |
829 | ||
e244a443 | 830 | if (hit_slowpath) { |
8dcf015e DV |
831 | /* |
832 | * Fixup: Flush cpu caches in case we didn't flush the dirty | |
833 | * cachelines in-line while writing and the object moved | |
834 | * out of the cpu write domain while we've dropped the lock. | |
835 | */ | |
836 | if (!needs_clflush_after && | |
837 | obj->base.write_domain != I915_GEM_DOMAIN_CPU) { | |
000433b6 CW |
838 | if (i915_gem_clflush_object(obj, obj->pin_display)) |
839 | i915_gem_chipset_flush(dev); | |
e244a443 | 840 | } |
8c59967c | 841 | } |
673a394b | 842 | |
58642885 | 843 | if (needs_clflush_after) |
e76e9aeb | 844 | i915_gem_chipset_flush(dev); |
58642885 | 845 | |
40123c1f | 846 | return ret; |
673a394b EA |
847 | } |
848 | ||
849 | /** | |
850 | * Writes data to the object referenced by handle. | |
851 | * | |
852 | * On error, the contents of the buffer that were to be modified are undefined. | |
853 | */ | |
854 | int | |
855 | i915_gem_pwrite_ioctl(struct drm_device *dev, void *data, | |
fbd5a26d | 856 | struct drm_file *file) |
673a394b EA |
857 | { |
858 | struct drm_i915_gem_pwrite *args = data; | |
05394f39 | 859 | struct drm_i915_gem_object *obj; |
51311d0a CW |
860 | int ret; |
861 | ||
862 | if (args->size == 0) | |
863 | return 0; | |
864 | ||
865 | if (!access_ok(VERIFY_READ, | |
2bb4629a | 866 | to_user_ptr(args->data_ptr), |
51311d0a CW |
867 | args->size)) |
868 | return -EFAULT; | |
869 | ||
0b74b508 XZ |
870 | if (likely(!i915_prefault_disable)) { |
871 | ret = fault_in_multipages_readable(to_user_ptr(args->data_ptr), | |
872 | args->size); | |
873 | if (ret) | |
874 | return -EFAULT; | |
875 | } | |
673a394b | 876 | |
fbd5a26d | 877 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 878 | if (ret) |
fbd5a26d | 879 | return ret; |
1d7cfea1 | 880 | |
05394f39 | 881 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 882 | if (&obj->base == NULL) { |
1d7cfea1 CW |
883 | ret = -ENOENT; |
884 | goto unlock; | |
fbd5a26d | 885 | } |
673a394b | 886 | |
7dcd2499 | 887 | /* Bounds check destination. */ |
05394f39 CW |
888 | if (args->offset > obj->base.size || |
889 | args->size > obj->base.size - args->offset) { | |
ce9d419d | 890 | ret = -EINVAL; |
35b62a89 | 891 | goto out; |
ce9d419d CW |
892 | } |
893 | ||
1286ff73 DV |
894 | /* prime objects have no backing filp to GEM pread/pwrite |
895 | * pages from. | |
896 | */ | |
897 | if (!obj->base.filp) { | |
898 | ret = -EINVAL; | |
899 | goto out; | |
900 | } | |
901 | ||
db53a302 CW |
902 | trace_i915_gem_object_pwrite(obj, args->offset, args->size); |
903 | ||
935aaa69 | 904 | ret = -EFAULT; |
673a394b EA |
905 | /* We can only do the GTT pwrite on untiled buffers, as otherwise |
906 | * it would end up going through the fenced access, and we'll get | |
907 | * different detiling behavior between reading and writing. | |
908 | * pread/pwrite currently are reading and writing from the CPU | |
909 | * perspective, requiring manual detiling by the client. | |
910 | */ | |
5c0480f2 | 911 | if (obj->phys_obj) { |
fbd5a26d | 912 | ret = i915_gem_phys_pwrite(dev, obj, args, file); |
5c0480f2 DV |
913 | goto out; |
914 | } | |
915 | ||
2c22569b CW |
916 | if (obj->tiling_mode == I915_TILING_NONE && |
917 | obj->base.write_domain != I915_GEM_DOMAIN_CPU && | |
918 | cpu_write_needs_clflush(obj)) { | |
fbd5a26d | 919 | ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file); |
935aaa69 DV |
920 | /* Note that the gtt paths might fail with non-page-backed user |
921 | * pointers (e.g. gtt mappings when moving data between | |
922 | * textures). Fallback to the shmem path in that case. */ | |
fbd5a26d | 923 | } |
673a394b | 924 | |
86a1ee26 | 925 | if (ret == -EFAULT || ret == -ENOSPC) |
935aaa69 | 926 | ret = i915_gem_shmem_pwrite(dev, obj, args, file); |
5c0480f2 | 927 | |
35b62a89 | 928 | out: |
05394f39 | 929 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 930 | unlock: |
fbd5a26d | 931 | mutex_unlock(&dev->struct_mutex); |
673a394b EA |
932 | return ret; |
933 | } | |
934 | ||
b361237b | 935 | int |
33196ded | 936 | i915_gem_check_wedge(struct i915_gpu_error *error, |
b361237b CW |
937 | bool interruptible) |
938 | { | |
1f83fee0 | 939 | if (i915_reset_in_progress(error)) { |
b361237b CW |
940 | /* Non-interruptible callers can't handle -EAGAIN, hence return |
941 | * -EIO unconditionally for these. */ | |
942 | if (!interruptible) | |
943 | return -EIO; | |
944 | ||
1f83fee0 DV |
945 | /* Recovery complete, but the reset failed ... */ |
946 | if (i915_terminally_wedged(error)) | |
b361237b CW |
947 | return -EIO; |
948 | ||
949 | return -EAGAIN; | |
950 | } | |
951 | ||
952 | return 0; | |
953 | } | |
954 | ||
955 | /* | |
956 | * Compare seqno against outstanding lazy request. Emit a request if they are | |
957 | * equal. | |
958 | */ | |
959 | static int | |
960 | i915_gem_check_olr(struct intel_ring_buffer *ring, u32 seqno) | |
961 | { | |
962 | int ret; | |
963 | ||
964 | BUG_ON(!mutex_is_locked(&ring->dev->struct_mutex)); | |
965 | ||
966 | ret = 0; | |
1823521d | 967 | if (seqno == ring->outstanding_lazy_seqno) |
0025c077 | 968 | ret = i915_add_request(ring, NULL); |
b361237b CW |
969 | |
970 | return ret; | |
971 | } | |
972 | ||
973 | /** | |
974 | * __wait_seqno - wait until execution of seqno has finished | |
975 | * @ring: the ring expected to report seqno | |
976 | * @seqno: duh! | |
f69061be | 977 | * @reset_counter: reset sequence associated with the given seqno |
b361237b CW |
978 | * @interruptible: do an interruptible wait (normally yes) |
979 | * @timeout: in - how long to wait (NULL forever); out - how much time remaining | |
980 | * | |
f69061be DV |
981 | * Note: It is of utmost importance that the passed in seqno and reset_counter |
982 | * values have been read by the caller in an smp safe manner. Where read-side | |
983 | * locks are involved, it is sufficient to read the reset_counter before | |
984 | * unlocking the lock that protects the seqno. For lockless tricks, the | |
985 | * reset_counter _must_ be read before, and an appropriate smp_rmb must be | |
986 | * inserted. | |
987 | * | |
b361237b CW |
988 | * Returns 0 if the seqno was found within the alloted time. Else returns the |
989 | * errno with remaining time filled in timeout argument. | |
990 | */ | |
991 | static int __wait_seqno(struct intel_ring_buffer *ring, u32 seqno, | |
f69061be | 992 | unsigned reset_counter, |
b361237b CW |
993 | bool interruptible, struct timespec *timeout) |
994 | { | |
995 | drm_i915_private_t *dev_priv = ring->dev->dev_private; | |
996 | struct timespec before, now, wait_time={1,0}; | |
997 | unsigned long timeout_jiffies; | |
998 | long end; | |
999 | bool wait_forever = true; | |
1000 | int ret; | |
1001 | ||
c67a470b PZ |
1002 | WARN(dev_priv->pc8.irqs_disabled, "IRQs disabled\n"); |
1003 | ||
b361237b CW |
1004 | if (i915_seqno_passed(ring->get_seqno(ring, true), seqno)) |
1005 | return 0; | |
1006 | ||
1007 | trace_i915_gem_request_wait_begin(ring, seqno); | |
1008 | ||
1009 | if (timeout != NULL) { | |
1010 | wait_time = *timeout; | |
1011 | wait_forever = false; | |
1012 | } | |
1013 | ||
e054cc39 | 1014 | timeout_jiffies = timespec_to_jiffies_timeout(&wait_time); |
b361237b CW |
1015 | |
1016 | if (WARN_ON(!ring->irq_get(ring))) | |
1017 | return -ENODEV; | |
1018 | ||
1019 | /* Record current time in case interrupted by signal, or wedged * */ | |
1020 | getrawmonotonic(&before); | |
1021 | ||
1022 | #define EXIT_COND \ | |
1023 | (i915_seqno_passed(ring->get_seqno(ring, false), seqno) || \ | |
f69061be DV |
1024 | i915_reset_in_progress(&dev_priv->gpu_error) || \ |
1025 | reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter)) | |
b361237b CW |
1026 | do { |
1027 | if (interruptible) | |
1028 | end = wait_event_interruptible_timeout(ring->irq_queue, | |
1029 | EXIT_COND, | |
1030 | timeout_jiffies); | |
1031 | else | |
1032 | end = wait_event_timeout(ring->irq_queue, EXIT_COND, | |
1033 | timeout_jiffies); | |
1034 | ||
f69061be DV |
1035 | /* We need to check whether any gpu reset happened in between |
1036 | * the caller grabbing the seqno and now ... */ | |
1037 | if (reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter)) | |
1038 | end = -EAGAIN; | |
1039 | ||
1040 | /* ... but upgrade the -EGAIN to an -EIO if the gpu is truely | |
1041 | * gone. */ | |
33196ded | 1042 | ret = i915_gem_check_wedge(&dev_priv->gpu_error, interruptible); |
b361237b CW |
1043 | if (ret) |
1044 | end = ret; | |
1045 | } while (end == 0 && wait_forever); | |
1046 | ||
1047 | getrawmonotonic(&now); | |
1048 | ||
1049 | ring->irq_put(ring); | |
1050 | trace_i915_gem_request_wait_end(ring, seqno); | |
1051 | #undef EXIT_COND | |
1052 | ||
1053 | if (timeout) { | |
1054 | struct timespec sleep_time = timespec_sub(now, before); | |
1055 | *timeout = timespec_sub(*timeout, sleep_time); | |
4f42f4ef CW |
1056 | if (!timespec_valid(timeout)) /* i.e. negative time remains */ |
1057 | set_normalized_timespec(timeout, 0, 0); | |
b361237b CW |
1058 | } |
1059 | ||
1060 | switch (end) { | |
1061 | case -EIO: | |
1062 | case -EAGAIN: /* Wedged */ | |
1063 | case -ERESTARTSYS: /* Signal */ | |
1064 | return (int)end; | |
1065 | case 0: /* Timeout */ | |
b361237b CW |
1066 | return -ETIME; |
1067 | default: /* Completed */ | |
1068 | WARN_ON(end < 0); /* We're not aware of other errors */ | |
1069 | return 0; | |
1070 | } | |
1071 | } | |
1072 | ||
1073 | /** | |
1074 | * Waits for a sequence number to be signaled, and cleans up the | |
1075 | * request and object lists appropriately for that event. | |
1076 | */ | |
1077 | int | |
1078 | i915_wait_seqno(struct intel_ring_buffer *ring, uint32_t seqno) | |
1079 | { | |
1080 | struct drm_device *dev = ring->dev; | |
1081 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1082 | bool interruptible = dev_priv->mm.interruptible; | |
1083 | int ret; | |
1084 | ||
1085 | BUG_ON(!mutex_is_locked(&dev->struct_mutex)); | |
1086 | BUG_ON(seqno == 0); | |
1087 | ||
33196ded | 1088 | ret = i915_gem_check_wedge(&dev_priv->gpu_error, interruptible); |
b361237b CW |
1089 | if (ret) |
1090 | return ret; | |
1091 | ||
1092 | ret = i915_gem_check_olr(ring, seqno); | |
1093 | if (ret) | |
1094 | return ret; | |
1095 | ||
f69061be DV |
1096 | return __wait_seqno(ring, seqno, |
1097 | atomic_read(&dev_priv->gpu_error.reset_counter), | |
1098 | interruptible, NULL); | |
b361237b CW |
1099 | } |
1100 | ||
d26e3af8 CW |
1101 | static int |
1102 | i915_gem_object_wait_rendering__tail(struct drm_i915_gem_object *obj, | |
1103 | struct intel_ring_buffer *ring) | |
1104 | { | |
1105 | i915_gem_retire_requests_ring(ring); | |
1106 | ||
1107 | /* Manually manage the write flush as we may have not yet | |
1108 | * retired the buffer. | |
1109 | * | |
1110 | * Note that the last_write_seqno is always the earlier of | |
1111 | * the two (read/write) seqno, so if we haved successfully waited, | |
1112 | * we know we have passed the last write. | |
1113 | */ | |
1114 | obj->last_write_seqno = 0; | |
1115 | obj->base.write_domain &= ~I915_GEM_GPU_DOMAINS; | |
1116 | ||
1117 | return 0; | |
1118 | } | |
1119 | ||
b361237b CW |
1120 | /** |
1121 | * Ensures that all rendering to the object has completed and the object is | |
1122 | * safe to unbind from the GTT or access from the CPU. | |
1123 | */ | |
1124 | static __must_check int | |
1125 | i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj, | |
1126 | bool readonly) | |
1127 | { | |
1128 | struct intel_ring_buffer *ring = obj->ring; | |
1129 | u32 seqno; | |
1130 | int ret; | |
1131 | ||
1132 | seqno = readonly ? obj->last_write_seqno : obj->last_read_seqno; | |
1133 | if (seqno == 0) | |
1134 | return 0; | |
1135 | ||
1136 | ret = i915_wait_seqno(ring, seqno); | |
1137 | if (ret) | |
1138 | return ret; | |
1139 | ||
d26e3af8 | 1140 | return i915_gem_object_wait_rendering__tail(obj, ring); |
b361237b CW |
1141 | } |
1142 | ||
3236f57a CW |
1143 | /* A nonblocking variant of the above wait. This is a highly dangerous routine |
1144 | * as the object state may change during this call. | |
1145 | */ | |
1146 | static __must_check int | |
1147 | i915_gem_object_wait_rendering__nonblocking(struct drm_i915_gem_object *obj, | |
1148 | bool readonly) | |
1149 | { | |
1150 | struct drm_device *dev = obj->base.dev; | |
1151 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1152 | struct intel_ring_buffer *ring = obj->ring; | |
f69061be | 1153 | unsigned reset_counter; |
3236f57a CW |
1154 | u32 seqno; |
1155 | int ret; | |
1156 | ||
1157 | BUG_ON(!mutex_is_locked(&dev->struct_mutex)); | |
1158 | BUG_ON(!dev_priv->mm.interruptible); | |
1159 | ||
1160 | seqno = readonly ? obj->last_write_seqno : obj->last_read_seqno; | |
1161 | if (seqno == 0) | |
1162 | return 0; | |
1163 | ||
33196ded | 1164 | ret = i915_gem_check_wedge(&dev_priv->gpu_error, true); |
3236f57a CW |
1165 | if (ret) |
1166 | return ret; | |
1167 | ||
1168 | ret = i915_gem_check_olr(ring, seqno); | |
1169 | if (ret) | |
1170 | return ret; | |
1171 | ||
f69061be | 1172 | reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter); |
3236f57a | 1173 | mutex_unlock(&dev->struct_mutex); |
f69061be | 1174 | ret = __wait_seqno(ring, seqno, reset_counter, true, NULL); |
3236f57a | 1175 | mutex_lock(&dev->struct_mutex); |
d26e3af8 CW |
1176 | if (ret) |
1177 | return ret; | |
3236f57a | 1178 | |
d26e3af8 | 1179 | return i915_gem_object_wait_rendering__tail(obj, ring); |
3236f57a CW |
1180 | } |
1181 | ||
673a394b | 1182 | /** |
2ef7eeaa EA |
1183 | * Called when user space prepares to use an object with the CPU, either |
1184 | * through the mmap ioctl's mapping or a GTT mapping. | |
673a394b EA |
1185 | */ |
1186 | int | |
1187 | i915_gem_set_domain_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 1188 | struct drm_file *file) |
673a394b EA |
1189 | { |
1190 | struct drm_i915_gem_set_domain *args = data; | |
05394f39 | 1191 | struct drm_i915_gem_object *obj; |
2ef7eeaa EA |
1192 | uint32_t read_domains = args->read_domains; |
1193 | uint32_t write_domain = args->write_domain; | |
673a394b EA |
1194 | int ret; |
1195 | ||
2ef7eeaa | 1196 | /* Only handle setting domains to types used by the CPU. */ |
21d509e3 | 1197 | if (write_domain & I915_GEM_GPU_DOMAINS) |
2ef7eeaa EA |
1198 | return -EINVAL; |
1199 | ||
21d509e3 | 1200 | if (read_domains & I915_GEM_GPU_DOMAINS) |
2ef7eeaa EA |
1201 | return -EINVAL; |
1202 | ||
1203 | /* Having something in the write domain implies it's in the read | |
1204 | * domain, and only that read domain. Enforce that in the request. | |
1205 | */ | |
1206 | if (write_domain != 0 && read_domains != write_domain) | |
1207 | return -EINVAL; | |
1208 | ||
76c1dec1 | 1209 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 1210 | if (ret) |
76c1dec1 | 1211 | return ret; |
1d7cfea1 | 1212 | |
05394f39 | 1213 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 1214 | if (&obj->base == NULL) { |
1d7cfea1 CW |
1215 | ret = -ENOENT; |
1216 | goto unlock; | |
76c1dec1 | 1217 | } |
673a394b | 1218 | |
3236f57a CW |
1219 | /* Try to flush the object off the GPU without holding the lock. |
1220 | * We will repeat the flush holding the lock in the normal manner | |
1221 | * to catch cases where we are gazumped. | |
1222 | */ | |
1223 | ret = i915_gem_object_wait_rendering__nonblocking(obj, !write_domain); | |
1224 | if (ret) | |
1225 | goto unref; | |
1226 | ||
2ef7eeaa EA |
1227 | if (read_domains & I915_GEM_DOMAIN_GTT) { |
1228 | ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0); | |
02354392 EA |
1229 | |
1230 | /* Silently promote "you're not bound, there was nothing to do" | |
1231 | * to success, since the client was just asking us to | |
1232 | * make sure everything was done. | |
1233 | */ | |
1234 | if (ret == -EINVAL) | |
1235 | ret = 0; | |
2ef7eeaa | 1236 | } else { |
e47c68e9 | 1237 | ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0); |
2ef7eeaa EA |
1238 | } |
1239 | ||
3236f57a | 1240 | unref: |
05394f39 | 1241 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 1242 | unlock: |
673a394b EA |
1243 | mutex_unlock(&dev->struct_mutex); |
1244 | return ret; | |
1245 | } | |
1246 | ||
1247 | /** | |
1248 | * Called when user space has done writes to this buffer | |
1249 | */ | |
1250 | int | |
1251 | i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 1252 | struct drm_file *file) |
673a394b EA |
1253 | { |
1254 | struct drm_i915_gem_sw_finish *args = data; | |
05394f39 | 1255 | struct drm_i915_gem_object *obj; |
673a394b EA |
1256 | int ret = 0; |
1257 | ||
76c1dec1 | 1258 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 1259 | if (ret) |
76c1dec1 | 1260 | return ret; |
1d7cfea1 | 1261 | |
05394f39 | 1262 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 1263 | if (&obj->base == NULL) { |
1d7cfea1 CW |
1264 | ret = -ENOENT; |
1265 | goto unlock; | |
673a394b EA |
1266 | } |
1267 | ||
673a394b | 1268 | /* Pinned buffers may be scanout, so flush the cache */ |
2c22569b CW |
1269 | if (obj->pin_display) |
1270 | i915_gem_object_flush_cpu_write_domain(obj, true); | |
e47c68e9 | 1271 | |
05394f39 | 1272 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 1273 | unlock: |
673a394b EA |
1274 | mutex_unlock(&dev->struct_mutex); |
1275 | return ret; | |
1276 | } | |
1277 | ||
1278 | /** | |
1279 | * Maps the contents of an object, returning the address it is mapped | |
1280 | * into. | |
1281 | * | |
1282 | * While the mapping holds a reference on the contents of the object, it doesn't | |
1283 | * imply a ref on the object itself. | |
1284 | */ | |
1285 | int | |
1286 | i915_gem_mmap_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 1287 | struct drm_file *file) |
673a394b EA |
1288 | { |
1289 | struct drm_i915_gem_mmap *args = data; | |
1290 | struct drm_gem_object *obj; | |
673a394b EA |
1291 | unsigned long addr; |
1292 | ||
05394f39 | 1293 | obj = drm_gem_object_lookup(dev, file, args->handle); |
673a394b | 1294 | if (obj == NULL) |
bf79cb91 | 1295 | return -ENOENT; |
673a394b | 1296 | |
1286ff73 DV |
1297 | /* prime objects have no backing filp to GEM mmap |
1298 | * pages from. | |
1299 | */ | |
1300 | if (!obj->filp) { | |
1301 | drm_gem_object_unreference_unlocked(obj); | |
1302 | return -EINVAL; | |
1303 | } | |
1304 | ||
6be5ceb0 | 1305 | addr = vm_mmap(obj->filp, 0, args->size, |
673a394b EA |
1306 | PROT_READ | PROT_WRITE, MAP_SHARED, |
1307 | args->offset); | |
bc9025bd | 1308 | drm_gem_object_unreference_unlocked(obj); |
673a394b EA |
1309 | if (IS_ERR((void *)addr)) |
1310 | return addr; | |
1311 | ||
1312 | args->addr_ptr = (uint64_t) addr; | |
1313 | ||
1314 | return 0; | |
1315 | } | |
1316 | ||
de151cf6 JB |
1317 | /** |
1318 | * i915_gem_fault - fault a page into the GTT | |
1319 | * vma: VMA in question | |
1320 | * vmf: fault info | |
1321 | * | |
1322 | * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped | |
1323 | * from userspace. The fault handler takes care of binding the object to | |
1324 | * the GTT (if needed), allocating and programming a fence register (again, | |
1325 | * only if needed based on whether the old reg is still valid or the object | |
1326 | * is tiled) and inserting a new PTE into the faulting process. | |
1327 | * | |
1328 | * Note that the faulting process may involve evicting existing objects | |
1329 | * from the GTT and/or fence registers to make room. So performance may | |
1330 | * suffer if the GTT working set is large or there are few fence registers | |
1331 | * left. | |
1332 | */ | |
1333 | int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf) | |
1334 | { | |
05394f39 CW |
1335 | struct drm_i915_gem_object *obj = to_intel_bo(vma->vm_private_data); |
1336 | struct drm_device *dev = obj->base.dev; | |
7d1c4804 | 1337 | drm_i915_private_t *dev_priv = dev->dev_private; |
de151cf6 JB |
1338 | pgoff_t page_offset; |
1339 | unsigned long pfn; | |
1340 | int ret = 0; | |
0f973f27 | 1341 | bool write = !!(vmf->flags & FAULT_FLAG_WRITE); |
de151cf6 JB |
1342 | |
1343 | /* We don't use vmf->pgoff since that has the fake offset */ | |
1344 | page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >> | |
1345 | PAGE_SHIFT; | |
1346 | ||
d9bc7e9f CW |
1347 | ret = i915_mutex_lock_interruptible(dev); |
1348 | if (ret) | |
1349 | goto out; | |
a00b10c3 | 1350 | |
db53a302 CW |
1351 | trace_i915_gem_object_fault(obj, page_offset, true, write); |
1352 | ||
eb119bd6 CW |
1353 | /* Access to snoopable pages through the GTT is incoherent. */ |
1354 | if (obj->cache_level != I915_CACHE_NONE && !HAS_LLC(dev)) { | |
1355 | ret = -EINVAL; | |
1356 | goto unlock; | |
1357 | } | |
1358 | ||
d9bc7e9f | 1359 | /* Now bind it into the GTT if needed */ |
c37e2204 | 1360 | ret = i915_gem_obj_ggtt_pin(obj, 0, true, false); |
c9839303 CW |
1361 | if (ret) |
1362 | goto unlock; | |
4a684a41 | 1363 | |
c9839303 CW |
1364 | ret = i915_gem_object_set_to_gtt_domain(obj, write); |
1365 | if (ret) | |
1366 | goto unpin; | |
74898d7e | 1367 | |
06d98131 | 1368 | ret = i915_gem_object_get_fence(obj); |
d9e86c0e | 1369 | if (ret) |
c9839303 | 1370 | goto unpin; |
7d1c4804 | 1371 | |
6299f992 CW |
1372 | obj->fault_mappable = true; |
1373 | ||
f343c5f6 BW |
1374 | pfn = dev_priv->gtt.mappable_base + i915_gem_obj_ggtt_offset(obj); |
1375 | pfn >>= PAGE_SHIFT; | |
1376 | pfn += page_offset; | |
de151cf6 JB |
1377 | |
1378 | /* Finally, remap it using the new GTT offset */ | |
1379 | ret = vm_insert_pfn(vma, (unsigned long)vmf->virtual_address, pfn); | |
c9839303 CW |
1380 | unpin: |
1381 | i915_gem_object_unpin(obj); | |
c715089f | 1382 | unlock: |
de151cf6 | 1383 | mutex_unlock(&dev->struct_mutex); |
d9bc7e9f | 1384 | out: |
de151cf6 | 1385 | switch (ret) { |
d9bc7e9f | 1386 | case -EIO: |
a9340cca DV |
1387 | /* If this -EIO is due to a gpu hang, give the reset code a |
1388 | * chance to clean up the mess. Otherwise return the proper | |
1389 | * SIGBUS. */ | |
1f83fee0 | 1390 | if (i915_terminally_wedged(&dev_priv->gpu_error)) |
a9340cca | 1391 | return VM_FAULT_SIGBUS; |
045e769a | 1392 | case -EAGAIN: |
d9bc7e9f CW |
1393 | /* Give the error handler a chance to run and move the |
1394 | * objects off the GPU active list. Next time we service the | |
1395 | * fault, we should be able to transition the page into the | |
1396 | * GTT without touching the GPU (and so avoid further | |
1397 | * EIO/EGAIN). If the GPU is wedged, then there is no issue | |
1398 | * with coherency, just lost writes. | |
1399 | */ | |
045e769a | 1400 | set_need_resched(); |
c715089f CW |
1401 | case 0: |
1402 | case -ERESTARTSYS: | |
bed636ab | 1403 | case -EINTR: |
e79e0fe3 DR |
1404 | case -EBUSY: |
1405 | /* | |
1406 | * EBUSY is ok: this just means that another thread | |
1407 | * already did the job. | |
1408 | */ | |
c715089f | 1409 | return VM_FAULT_NOPAGE; |
de151cf6 | 1410 | case -ENOMEM: |
de151cf6 | 1411 | return VM_FAULT_OOM; |
a7c2e1aa DV |
1412 | case -ENOSPC: |
1413 | return VM_FAULT_SIGBUS; | |
de151cf6 | 1414 | default: |
a7c2e1aa | 1415 | WARN_ONCE(ret, "unhandled error in i915_gem_fault: %i\n", ret); |
c715089f | 1416 | return VM_FAULT_SIGBUS; |
de151cf6 JB |
1417 | } |
1418 | } | |
1419 | ||
901782b2 CW |
1420 | /** |
1421 | * i915_gem_release_mmap - remove physical page mappings | |
1422 | * @obj: obj in question | |
1423 | * | |
af901ca1 | 1424 | * Preserve the reservation of the mmapping with the DRM core code, but |
901782b2 CW |
1425 | * relinquish ownership of the pages back to the system. |
1426 | * | |
1427 | * It is vital that we remove the page mapping if we have mapped a tiled | |
1428 | * object through the GTT and then lose the fence register due to | |
1429 | * resource pressure. Similarly if the object has been moved out of the | |
1430 | * aperture, than pages mapped into userspace must be revoked. Removing the | |
1431 | * mapping will then trigger a page fault on the next user access, allowing | |
1432 | * fixup by i915_gem_fault(). | |
1433 | */ | |
d05ca301 | 1434 | void |
05394f39 | 1435 | i915_gem_release_mmap(struct drm_i915_gem_object *obj) |
901782b2 | 1436 | { |
6299f992 CW |
1437 | if (!obj->fault_mappable) |
1438 | return; | |
901782b2 | 1439 | |
51335df9 | 1440 | drm_vma_node_unmap(&obj->base.vma_node, obj->base.dev->dev_mapping); |
6299f992 | 1441 | obj->fault_mappable = false; |
901782b2 CW |
1442 | } |
1443 | ||
0fa87796 | 1444 | uint32_t |
e28f8711 | 1445 | i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode) |
92b88aeb | 1446 | { |
e28f8711 | 1447 | uint32_t gtt_size; |
92b88aeb CW |
1448 | |
1449 | if (INTEL_INFO(dev)->gen >= 4 || | |
e28f8711 CW |
1450 | tiling_mode == I915_TILING_NONE) |
1451 | return size; | |
92b88aeb CW |
1452 | |
1453 | /* Previous chips need a power-of-two fence region when tiling */ | |
1454 | if (INTEL_INFO(dev)->gen == 3) | |
e28f8711 | 1455 | gtt_size = 1024*1024; |
92b88aeb | 1456 | else |
e28f8711 | 1457 | gtt_size = 512*1024; |
92b88aeb | 1458 | |
e28f8711 CW |
1459 | while (gtt_size < size) |
1460 | gtt_size <<= 1; | |
92b88aeb | 1461 | |
e28f8711 | 1462 | return gtt_size; |
92b88aeb CW |
1463 | } |
1464 | ||
de151cf6 JB |
1465 | /** |
1466 | * i915_gem_get_gtt_alignment - return required GTT alignment for an object | |
1467 | * @obj: object to check | |
1468 | * | |
1469 | * Return the required GTT alignment for an object, taking into account | |
5e783301 | 1470 | * potential fence register mapping. |
de151cf6 | 1471 | */ |
d865110c ID |
1472 | uint32_t |
1473 | i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size, | |
1474 | int tiling_mode, bool fenced) | |
de151cf6 | 1475 | { |
de151cf6 JB |
1476 | /* |
1477 | * Minimum alignment is 4k (GTT page size), but might be greater | |
1478 | * if a fence register is needed for the object. | |
1479 | */ | |
d865110c | 1480 | if (INTEL_INFO(dev)->gen >= 4 || (!fenced && IS_G33(dev)) || |
e28f8711 | 1481 | tiling_mode == I915_TILING_NONE) |
de151cf6 JB |
1482 | return 4096; |
1483 | ||
a00b10c3 CW |
1484 | /* |
1485 | * Previous chips need to be aligned to the size of the smallest | |
1486 | * fence register that can contain the object. | |
1487 | */ | |
e28f8711 | 1488 | return i915_gem_get_gtt_size(dev, size, tiling_mode); |
a00b10c3 CW |
1489 | } |
1490 | ||
d8cb5086 CW |
1491 | static int i915_gem_object_create_mmap_offset(struct drm_i915_gem_object *obj) |
1492 | { | |
1493 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; | |
1494 | int ret; | |
1495 | ||
0de23977 | 1496 | if (drm_vma_node_has_offset(&obj->base.vma_node)) |
d8cb5086 CW |
1497 | return 0; |
1498 | ||
da494d7c DV |
1499 | dev_priv->mm.shrinker_no_lock_stealing = true; |
1500 | ||
d8cb5086 CW |
1501 | ret = drm_gem_create_mmap_offset(&obj->base); |
1502 | if (ret != -ENOSPC) | |
da494d7c | 1503 | goto out; |
d8cb5086 CW |
1504 | |
1505 | /* Badly fragmented mmap space? The only way we can recover | |
1506 | * space is by destroying unwanted objects. We can't randomly release | |
1507 | * mmap_offsets as userspace expects them to be persistent for the | |
1508 | * lifetime of the objects. The closest we can is to release the | |
1509 | * offsets on purgeable objects by truncating it and marking it purged, | |
1510 | * which prevents userspace from ever using that object again. | |
1511 | */ | |
1512 | i915_gem_purge(dev_priv, obj->base.size >> PAGE_SHIFT); | |
1513 | ret = drm_gem_create_mmap_offset(&obj->base); | |
1514 | if (ret != -ENOSPC) | |
da494d7c | 1515 | goto out; |
d8cb5086 CW |
1516 | |
1517 | i915_gem_shrink_all(dev_priv); | |
da494d7c DV |
1518 | ret = drm_gem_create_mmap_offset(&obj->base); |
1519 | out: | |
1520 | dev_priv->mm.shrinker_no_lock_stealing = false; | |
1521 | ||
1522 | return ret; | |
d8cb5086 CW |
1523 | } |
1524 | ||
1525 | static void i915_gem_object_free_mmap_offset(struct drm_i915_gem_object *obj) | |
1526 | { | |
d8cb5086 CW |
1527 | drm_gem_free_mmap_offset(&obj->base); |
1528 | } | |
1529 | ||
de151cf6 | 1530 | int |
ff72145b DA |
1531 | i915_gem_mmap_gtt(struct drm_file *file, |
1532 | struct drm_device *dev, | |
1533 | uint32_t handle, | |
1534 | uint64_t *offset) | |
de151cf6 | 1535 | { |
da761a6e | 1536 | struct drm_i915_private *dev_priv = dev->dev_private; |
05394f39 | 1537 | struct drm_i915_gem_object *obj; |
de151cf6 JB |
1538 | int ret; |
1539 | ||
76c1dec1 | 1540 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 1541 | if (ret) |
76c1dec1 | 1542 | return ret; |
de151cf6 | 1543 | |
ff72145b | 1544 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle)); |
c8725226 | 1545 | if (&obj->base == NULL) { |
1d7cfea1 CW |
1546 | ret = -ENOENT; |
1547 | goto unlock; | |
1548 | } | |
de151cf6 | 1549 | |
5d4545ae | 1550 | if (obj->base.size > dev_priv->gtt.mappable_end) { |
da761a6e | 1551 | ret = -E2BIG; |
ff56b0bc | 1552 | goto out; |
da761a6e CW |
1553 | } |
1554 | ||
05394f39 | 1555 | if (obj->madv != I915_MADV_WILLNEED) { |
ab18282d | 1556 | DRM_ERROR("Attempting to mmap a purgeable buffer\n"); |
1d7cfea1 CW |
1557 | ret = -EINVAL; |
1558 | goto out; | |
ab18282d CW |
1559 | } |
1560 | ||
d8cb5086 CW |
1561 | ret = i915_gem_object_create_mmap_offset(obj); |
1562 | if (ret) | |
1563 | goto out; | |
de151cf6 | 1564 | |
0de23977 | 1565 | *offset = drm_vma_node_offset_addr(&obj->base.vma_node); |
de151cf6 | 1566 | |
1d7cfea1 | 1567 | out: |
05394f39 | 1568 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 1569 | unlock: |
de151cf6 | 1570 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 1571 | return ret; |
de151cf6 JB |
1572 | } |
1573 | ||
ff72145b DA |
1574 | /** |
1575 | * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing | |
1576 | * @dev: DRM device | |
1577 | * @data: GTT mapping ioctl data | |
1578 | * @file: GEM object info | |
1579 | * | |
1580 | * Simply returns the fake offset to userspace so it can mmap it. | |
1581 | * The mmap call will end up in drm_gem_mmap(), which will set things | |
1582 | * up so we can get faults in the handler above. | |
1583 | * | |
1584 | * The fault handler will take care of binding the object into the GTT | |
1585 | * (since it may have been evicted to make room for something), allocating | |
1586 | * a fence register, and mapping the appropriate aperture address into | |
1587 | * userspace. | |
1588 | */ | |
1589 | int | |
1590 | i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data, | |
1591 | struct drm_file *file) | |
1592 | { | |
1593 | struct drm_i915_gem_mmap_gtt *args = data; | |
1594 | ||
ff72145b DA |
1595 | return i915_gem_mmap_gtt(file, dev, args->handle, &args->offset); |
1596 | } | |
1597 | ||
225067ee DV |
1598 | /* Immediately discard the backing storage */ |
1599 | static void | |
1600 | i915_gem_object_truncate(struct drm_i915_gem_object *obj) | |
e5281ccd | 1601 | { |
e5281ccd | 1602 | struct inode *inode; |
e5281ccd | 1603 | |
4d6294bf | 1604 | i915_gem_object_free_mmap_offset(obj); |
1286ff73 | 1605 | |
4d6294bf CW |
1606 | if (obj->base.filp == NULL) |
1607 | return; | |
e5281ccd | 1608 | |
225067ee DV |
1609 | /* Our goal here is to return as much of the memory as |
1610 | * is possible back to the system as we are called from OOM. | |
1611 | * To do this we must instruct the shmfs to drop all of its | |
1612 | * backing pages, *now*. | |
1613 | */ | |
496ad9aa | 1614 | inode = file_inode(obj->base.filp); |
225067ee | 1615 | shmem_truncate_range(inode, 0, (loff_t)-1); |
e5281ccd | 1616 | |
225067ee DV |
1617 | obj->madv = __I915_MADV_PURGED; |
1618 | } | |
e5281ccd | 1619 | |
225067ee DV |
1620 | static inline int |
1621 | i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj) | |
1622 | { | |
1623 | return obj->madv == I915_MADV_DONTNEED; | |
e5281ccd CW |
1624 | } |
1625 | ||
5cdf5881 | 1626 | static void |
05394f39 | 1627 | i915_gem_object_put_pages_gtt(struct drm_i915_gem_object *obj) |
673a394b | 1628 | { |
90797e6d ID |
1629 | struct sg_page_iter sg_iter; |
1630 | int ret; | |
1286ff73 | 1631 | |
05394f39 | 1632 | BUG_ON(obj->madv == __I915_MADV_PURGED); |
673a394b | 1633 | |
6c085a72 CW |
1634 | ret = i915_gem_object_set_to_cpu_domain(obj, true); |
1635 | if (ret) { | |
1636 | /* In the event of a disaster, abandon all caches and | |
1637 | * hope for the best. | |
1638 | */ | |
1639 | WARN_ON(ret != -EIO); | |
2c22569b | 1640 | i915_gem_clflush_object(obj, true); |
6c085a72 CW |
1641 | obj->base.read_domains = obj->base.write_domain = I915_GEM_DOMAIN_CPU; |
1642 | } | |
1643 | ||
6dacfd2f | 1644 | if (i915_gem_object_needs_bit17_swizzle(obj)) |
280b713b EA |
1645 | i915_gem_object_save_bit_17_swizzle(obj); |
1646 | ||
05394f39 CW |
1647 | if (obj->madv == I915_MADV_DONTNEED) |
1648 | obj->dirty = 0; | |
3ef94daa | 1649 | |
90797e6d | 1650 | for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, 0) { |
2db76d7c | 1651 | struct page *page = sg_page_iter_page(&sg_iter); |
9da3da66 | 1652 | |
05394f39 | 1653 | if (obj->dirty) |
9da3da66 | 1654 | set_page_dirty(page); |
3ef94daa | 1655 | |
05394f39 | 1656 | if (obj->madv == I915_MADV_WILLNEED) |
9da3da66 | 1657 | mark_page_accessed(page); |
3ef94daa | 1658 | |
9da3da66 | 1659 | page_cache_release(page); |
3ef94daa | 1660 | } |
05394f39 | 1661 | obj->dirty = 0; |
673a394b | 1662 | |
9da3da66 CW |
1663 | sg_free_table(obj->pages); |
1664 | kfree(obj->pages); | |
37e680a1 | 1665 | } |
6c085a72 | 1666 | |
dd624afd | 1667 | int |
37e680a1 CW |
1668 | i915_gem_object_put_pages(struct drm_i915_gem_object *obj) |
1669 | { | |
1670 | const struct drm_i915_gem_object_ops *ops = obj->ops; | |
1671 | ||
2f745ad3 | 1672 | if (obj->pages == NULL) |
37e680a1 CW |
1673 | return 0; |
1674 | ||
a5570178 CW |
1675 | if (obj->pages_pin_count) |
1676 | return -EBUSY; | |
1677 | ||
9843877d | 1678 | BUG_ON(i915_gem_obj_bound_any(obj)); |
3e123027 | 1679 | |
a2165e31 CW |
1680 | /* ->put_pages might need to allocate memory for the bit17 swizzle |
1681 | * array, hence protect them from being reaped by removing them from gtt | |
1682 | * lists early. */ | |
35c20a60 | 1683 | list_del(&obj->global_list); |
a2165e31 | 1684 | |
37e680a1 | 1685 | ops->put_pages(obj); |
05394f39 | 1686 | obj->pages = NULL; |
37e680a1 | 1687 | |
6c085a72 CW |
1688 | if (i915_gem_object_is_purgeable(obj)) |
1689 | i915_gem_object_truncate(obj); | |
1690 | ||
1691 | return 0; | |
1692 | } | |
1693 | ||
1694 | static long | |
93927ca5 DV |
1695 | __i915_gem_shrink(struct drm_i915_private *dev_priv, long target, |
1696 | bool purgeable_only) | |
6c085a72 CW |
1697 | { |
1698 | struct drm_i915_gem_object *obj, *next; | |
1699 | long count = 0; | |
1700 | ||
1701 | list_for_each_entry_safe(obj, next, | |
1702 | &dev_priv->mm.unbound_list, | |
35c20a60 | 1703 | global_list) { |
93927ca5 | 1704 | if ((i915_gem_object_is_purgeable(obj) || !purgeable_only) && |
37e680a1 | 1705 | i915_gem_object_put_pages(obj) == 0) { |
6c085a72 CW |
1706 | count += obj->base.size >> PAGE_SHIFT; |
1707 | if (count >= target) | |
1708 | return count; | |
1709 | } | |
1710 | } | |
1711 | ||
07fe0b12 BW |
1712 | list_for_each_entry_safe(obj, next, &dev_priv->mm.bound_list, |
1713 | global_list) { | |
1714 | struct i915_vma *vma, *v; | |
80dcfdbd BW |
1715 | |
1716 | if (!i915_gem_object_is_purgeable(obj) && purgeable_only) | |
1717 | continue; | |
1718 | ||
07fe0b12 BW |
1719 | list_for_each_entry_safe(vma, v, &obj->vma_list, vma_link) |
1720 | if (i915_vma_unbind(vma)) | |
1721 | break; | |
80dcfdbd BW |
1722 | |
1723 | if (!i915_gem_object_put_pages(obj)) { | |
6c085a72 CW |
1724 | count += obj->base.size >> PAGE_SHIFT; |
1725 | if (count >= target) | |
1726 | return count; | |
1727 | } | |
1728 | } | |
1729 | ||
1730 | return count; | |
1731 | } | |
1732 | ||
93927ca5 DV |
1733 | static long |
1734 | i915_gem_purge(struct drm_i915_private *dev_priv, long target) | |
1735 | { | |
1736 | return __i915_gem_shrink(dev_priv, target, true); | |
1737 | } | |
1738 | ||
6c085a72 CW |
1739 | static void |
1740 | i915_gem_shrink_all(struct drm_i915_private *dev_priv) | |
1741 | { | |
1742 | struct drm_i915_gem_object *obj, *next; | |
1743 | ||
1744 | i915_gem_evict_everything(dev_priv->dev); | |
1745 | ||
35c20a60 BW |
1746 | list_for_each_entry_safe(obj, next, &dev_priv->mm.unbound_list, |
1747 | global_list) | |
37e680a1 | 1748 | i915_gem_object_put_pages(obj); |
225067ee DV |
1749 | } |
1750 | ||
37e680a1 | 1751 | static int |
6c085a72 | 1752 | i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj) |
e5281ccd | 1753 | { |
6c085a72 | 1754 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
e5281ccd CW |
1755 | int page_count, i; |
1756 | struct address_space *mapping; | |
9da3da66 CW |
1757 | struct sg_table *st; |
1758 | struct scatterlist *sg; | |
90797e6d | 1759 | struct sg_page_iter sg_iter; |
e5281ccd | 1760 | struct page *page; |
90797e6d | 1761 | unsigned long last_pfn = 0; /* suppress gcc warning */ |
6c085a72 | 1762 | gfp_t gfp; |
e5281ccd | 1763 | |
6c085a72 CW |
1764 | /* Assert that the object is not currently in any GPU domain. As it |
1765 | * wasn't in the GTT, there shouldn't be any way it could have been in | |
1766 | * a GPU cache | |
1767 | */ | |
1768 | BUG_ON(obj->base.read_domains & I915_GEM_GPU_DOMAINS); | |
1769 | BUG_ON(obj->base.write_domain & I915_GEM_GPU_DOMAINS); | |
1770 | ||
9da3da66 CW |
1771 | st = kmalloc(sizeof(*st), GFP_KERNEL); |
1772 | if (st == NULL) | |
1773 | return -ENOMEM; | |
1774 | ||
05394f39 | 1775 | page_count = obj->base.size / PAGE_SIZE; |
9da3da66 | 1776 | if (sg_alloc_table(st, page_count, GFP_KERNEL)) { |
9da3da66 | 1777 | kfree(st); |
e5281ccd | 1778 | return -ENOMEM; |
9da3da66 | 1779 | } |
e5281ccd | 1780 | |
9da3da66 CW |
1781 | /* Get the list of pages out of our struct file. They'll be pinned |
1782 | * at this point until we release them. | |
1783 | * | |
1784 | * Fail silently without starting the shrinker | |
1785 | */ | |
496ad9aa | 1786 | mapping = file_inode(obj->base.filp)->i_mapping; |
6c085a72 | 1787 | gfp = mapping_gfp_mask(mapping); |
caf49191 | 1788 | gfp |= __GFP_NORETRY | __GFP_NOWARN | __GFP_NO_KSWAPD; |
6c085a72 | 1789 | gfp &= ~(__GFP_IO | __GFP_WAIT); |
90797e6d ID |
1790 | sg = st->sgl; |
1791 | st->nents = 0; | |
1792 | for (i = 0; i < page_count; i++) { | |
6c085a72 CW |
1793 | page = shmem_read_mapping_page_gfp(mapping, i, gfp); |
1794 | if (IS_ERR(page)) { | |
1795 | i915_gem_purge(dev_priv, page_count); | |
1796 | page = shmem_read_mapping_page_gfp(mapping, i, gfp); | |
1797 | } | |
1798 | if (IS_ERR(page)) { | |
1799 | /* We've tried hard to allocate the memory by reaping | |
1800 | * our own buffer, now let the real VM do its job and | |
1801 | * go down in flames if truly OOM. | |
1802 | */ | |
caf49191 | 1803 | gfp &= ~(__GFP_NORETRY | __GFP_NOWARN | __GFP_NO_KSWAPD); |
6c085a72 CW |
1804 | gfp |= __GFP_IO | __GFP_WAIT; |
1805 | ||
1806 | i915_gem_shrink_all(dev_priv); | |
1807 | page = shmem_read_mapping_page_gfp(mapping, i, gfp); | |
1808 | if (IS_ERR(page)) | |
1809 | goto err_pages; | |
1810 | ||
caf49191 | 1811 | gfp |= __GFP_NORETRY | __GFP_NOWARN | __GFP_NO_KSWAPD; |
6c085a72 CW |
1812 | gfp &= ~(__GFP_IO | __GFP_WAIT); |
1813 | } | |
426729dc KRW |
1814 | #ifdef CONFIG_SWIOTLB |
1815 | if (swiotlb_nr_tbl()) { | |
1816 | st->nents++; | |
1817 | sg_set_page(sg, page, PAGE_SIZE, 0); | |
1818 | sg = sg_next(sg); | |
1819 | continue; | |
1820 | } | |
1821 | #endif | |
90797e6d ID |
1822 | if (!i || page_to_pfn(page) != last_pfn + 1) { |
1823 | if (i) | |
1824 | sg = sg_next(sg); | |
1825 | st->nents++; | |
1826 | sg_set_page(sg, page, PAGE_SIZE, 0); | |
1827 | } else { | |
1828 | sg->length += PAGE_SIZE; | |
1829 | } | |
1830 | last_pfn = page_to_pfn(page); | |
e5281ccd | 1831 | } |
426729dc KRW |
1832 | #ifdef CONFIG_SWIOTLB |
1833 | if (!swiotlb_nr_tbl()) | |
1834 | #endif | |
1835 | sg_mark_end(sg); | |
74ce6b6c CW |
1836 | obj->pages = st; |
1837 | ||
6dacfd2f | 1838 | if (i915_gem_object_needs_bit17_swizzle(obj)) |
e5281ccd CW |
1839 | i915_gem_object_do_bit_17_swizzle(obj); |
1840 | ||
1841 | return 0; | |
1842 | ||
1843 | err_pages: | |
90797e6d ID |
1844 | sg_mark_end(sg); |
1845 | for_each_sg_page(st->sgl, &sg_iter, st->nents, 0) | |
2db76d7c | 1846 | page_cache_release(sg_page_iter_page(&sg_iter)); |
9da3da66 CW |
1847 | sg_free_table(st); |
1848 | kfree(st); | |
e5281ccd | 1849 | return PTR_ERR(page); |
673a394b EA |
1850 | } |
1851 | ||
37e680a1 CW |
1852 | /* Ensure that the associated pages are gathered from the backing storage |
1853 | * and pinned into our object. i915_gem_object_get_pages() may be called | |
1854 | * multiple times before they are released by a single call to | |
1855 | * i915_gem_object_put_pages() - once the pages are no longer referenced | |
1856 | * either as a result of memory pressure (reaping pages under the shrinker) | |
1857 | * or as the object is itself released. | |
1858 | */ | |
1859 | int | |
1860 | i915_gem_object_get_pages(struct drm_i915_gem_object *obj) | |
1861 | { | |
1862 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; | |
1863 | const struct drm_i915_gem_object_ops *ops = obj->ops; | |
1864 | int ret; | |
1865 | ||
2f745ad3 | 1866 | if (obj->pages) |
37e680a1 CW |
1867 | return 0; |
1868 | ||
43e28f09 CW |
1869 | if (obj->madv != I915_MADV_WILLNEED) { |
1870 | DRM_ERROR("Attempting to obtain a purgeable object\n"); | |
1871 | return -EINVAL; | |
1872 | } | |
1873 | ||
a5570178 CW |
1874 | BUG_ON(obj->pages_pin_count); |
1875 | ||
37e680a1 CW |
1876 | ret = ops->get_pages(obj); |
1877 | if (ret) | |
1878 | return ret; | |
1879 | ||
35c20a60 | 1880 | list_add_tail(&obj->global_list, &dev_priv->mm.unbound_list); |
37e680a1 | 1881 | return 0; |
673a394b EA |
1882 | } |
1883 | ||
54cf91dc | 1884 | void |
05394f39 | 1885 | i915_gem_object_move_to_active(struct drm_i915_gem_object *obj, |
9d773091 | 1886 | struct intel_ring_buffer *ring) |
673a394b | 1887 | { |
05394f39 | 1888 | struct drm_device *dev = obj->base.dev; |
69dc4987 | 1889 | struct drm_i915_private *dev_priv = dev->dev_private; |
9d773091 | 1890 | u32 seqno = intel_ring_get_seqno(ring); |
617dbe27 | 1891 | |
852835f3 | 1892 | BUG_ON(ring == NULL); |
02978ff5 CW |
1893 | if (obj->ring != ring && obj->last_write_seqno) { |
1894 | /* Keep the seqno relative to the current ring */ | |
1895 | obj->last_write_seqno = seqno; | |
1896 | } | |
05394f39 | 1897 | obj->ring = ring; |
673a394b EA |
1898 | |
1899 | /* Add a reference if we're newly entering the active list. */ | |
05394f39 CW |
1900 | if (!obj->active) { |
1901 | drm_gem_object_reference(&obj->base); | |
1902 | obj->active = 1; | |
673a394b | 1903 | } |
e35a41de | 1904 | |
05394f39 | 1905 | list_move_tail(&obj->ring_list, &ring->active_list); |
caea7476 | 1906 | |
0201f1ec | 1907 | obj->last_read_seqno = seqno; |
caea7476 | 1908 | |
7dd49065 | 1909 | if (obj->fenced_gpu_access) { |
caea7476 | 1910 | obj->last_fenced_seqno = seqno; |
caea7476 | 1911 | |
7dd49065 CW |
1912 | /* Bump MRU to take account of the delayed flush */ |
1913 | if (obj->fence_reg != I915_FENCE_REG_NONE) { | |
1914 | struct drm_i915_fence_reg *reg; | |
1915 | ||
1916 | reg = &dev_priv->fence_regs[obj->fence_reg]; | |
1917 | list_move_tail(®->lru_list, | |
1918 | &dev_priv->mm.fence_list); | |
1919 | } | |
caea7476 CW |
1920 | } |
1921 | } | |
1922 | ||
1923 | static void | |
caea7476 | 1924 | i915_gem_object_move_to_inactive(struct drm_i915_gem_object *obj) |
ce44b0ea | 1925 | { |
ca191b13 BW |
1926 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
1927 | struct i915_address_space *ggtt_vm = &dev_priv->gtt.base; | |
1928 | struct i915_vma *vma = i915_gem_obj_to_vma(obj, ggtt_vm); | |
ce44b0ea | 1929 | |
65ce3027 | 1930 | BUG_ON(obj->base.write_domain & ~I915_GEM_GPU_DOMAINS); |
05394f39 | 1931 | BUG_ON(!obj->active); |
caea7476 | 1932 | |
ca191b13 | 1933 | list_move_tail(&vma->mm_list, &ggtt_vm->inactive_list); |
caea7476 | 1934 | |
65ce3027 | 1935 | list_del_init(&obj->ring_list); |
caea7476 CW |
1936 | obj->ring = NULL; |
1937 | ||
65ce3027 CW |
1938 | obj->last_read_seqno = 0; |
1939 | obj->last_write_seqno = 0; | |
1940 | obj->base.write_domain = 0; | |
1941 | ||
1942 | obj->last_fenced_seqno = 0; | |
caea7476 | 1943 | obj->fenced_gpu_access = false; |
caea7476 CW |
1944 | |
1945 | obj->active = 0; | |
1946 | drm_gem_object_unreference(&obj->base); | |
1947 | ||
1948 | WARN_ON(i915_verify_lists(dev)); | |
ce44b0ea | 1949 | } |
673a394b | 1950 | |
9d773091 | 1951 | static int |
fca26bb4 | 1952 | i915_gem_init_seqno(struct drm_device *dev, u32 seqno) |
53d227f2 | 1953 | { |
9d773091 CW |
1954 | struct drm_i915_private *dev_priv = dev->dev_private; |
1955 | struct intel_ring_buffer *ring; | |
1956 | int ret, i, j; | |
53d227f2 | 1957 | |
107f27a5 | 1958 | /* Carefully retire all requests without writing to the rings */ |
9d773091 | 1959 | for_each_ring(ring, dev_priv, i) { |
107f27a5 CW |
1960 | ret = intel_ring_idle(ring); |
1961 | if (ret) | |
1962 | return ret; | |
9d773091 | 1963 | } |
9d773091 | 1964 | i915_gem_retire_requests(dev); |
107f27a5 CW |
1965 | |
1966 | /* Finally reset hw state */ | |
9d773091 | 1967 | for_each_ring(ring, dev_priv, i) { |
fca26bb4 | 1968 | intel_ring_init_seqno(ring, seqno); |
498d2ac1 | 1969 | |
9d773091 CW |
1970 | for (j = 0; j < ARRAY_SIZE(ring->sync_seqno); j++) |
1971 | ring->sync_seqno[j] = 0; | |
1972 | } | |
53d227f2 | 1973 | |
9d773091 | 1974 | return 0; |
53d227f2 DV |
1975 | } |
1976 | ||
fca26bb4 MK |
1977 | int i915_gem_set_seqno(struct drm_device *dev, u32 seqno) |
1978 | { | |
1979 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1980 | int ret; | |
1981 | ||
1982 | if (seqno == 0) | |
1983 | return -EINVAL; | |
1984 | ||
1985 | /* HWS page needs to be set less than what we | |
1986 | * will inject to ring | |
1987 | */ | |
1988 | ret = i915_gem_init_seqno(dev, seqno - 1); | |
1989 | if (ret) | |
1990 | return ret; | |
1991 | ||
1992 | /* Carefully set the last_seqno value so that wrap | |
1993 | * detection still works | |
1994 | */ | |
1995 | dev_priv->next_seqno = seqno; | |
1996 | dev_priv->last_seqno = seqno - 1; | |
1997 | if (dev_priv->last_seqno == 0) | |
1998 | dev_priv->last_seqno--; | |
1999 | ||
2000 | return 0; | |
2001 | } | |
2002 | ||
9d773091 CW |
2003 | int |
2004 | i915_gem_get_seqno(struct drm_device *dev, u32 *seqno) | |
53d227f2 | 2005 | { |
9d773091 CW |
2006 | struct drm_i915_private *dev_priv = dev->dev_private; |
2007 | ||
2008 | /* reserve 0 for non-seqno */ | |
2009 | if (dev_priv->next_seqno == 0) { | |
fca26bb4 | 2010 | int ret = i915_gem_init_seqno(dev, 0); |
9d773091 CW |
2011 | if (ret) |
2012 | return ret; | |
53d227f2 | 2013 | |
9d773091 CW |
2014 | dev_priv->next_seqno = 1; |
2015 | } | |
53d227f2 | 2016 | |
f72b3435 | 2017 | *seqno = dev_priv->last_seqno = dev_priv->next_seqno++; |
9d773091 | 2018 | return 0; |
53d227f2 DV |
2019 | } |
2020 | ||
0025c077 MK |
2021 | int __i915_add_request(struct intel_ring_buffer *ring, |
2022 | struct drm_file *file, | |
7d736f4f | 2023 | struct drm_i915_gem_object *obj, |
0025c077 | 2024 | u32 *out_seqno) |
673a394b | 2025 | { |
db53a302 | 2026 | drm_i915_private_t *dev_priv = ring->dev->dev_private; |
acb868d3 | 2027 | struct drm_i915_gem_request *request; |
7d736f4f | 2028 | u32 request_ring_position, request_start; |
673a394b | 2029 | int was_empty; |
3cce469c CW |
2030 | int ret; |
2031 | ||
7d736f4f | 2032 | request_start = intel_ring_get_tail(ring); |
cc889e0f DV |
2033 | /* |
2034 | * Emit any outstanding flushes - execbuf can fail to emit the flush | |
2035 | * after having emitted the batchbuffer command. Hence we need to fix | |
2036 | * things up similar to emitting the lazy request. The difference here | |
2037 | * is that the flush _must_ happen before the next request, no matter | |
2038 | * what. | |
2039 | */ | |
a7b9761d CW |
2040 | ret = intel_ring_flush_all_caches(ring); |
2041 | if (ret) | |
2042 | return ret; | |
cc889e0f | 2043 | |
3c0e234c CW |
2044 | request = ring->preallocated_lazy_request; |
2045 | if (WARN_ON(request == NULL)) | |
acb868d3 | 2046 | return -ENOMEM; |
cc889e0f | 2047 | |
a71d8d94 CW |
2048 | /* Record the position of the start of the request so that |
2049 | * should we detect the updated seqno part-way through the | |
2050 | * GPU processing the request, we never over-estimate the | |
2051 | * position of the head. | |
2052 | */ | |
2053 | request_ring_position = intel_ring_get_tail(ring); | |
2054 | ||
9d773091 | 2055 | ret = ring->add_request(ring); |
3c0e234c | 2056 | if (ret) |
3bb73aba | 2057 | return ret; |
673a394b | 2058 | |
9d773091 | 2059 | request->seqno = intel_ring_get_seqno(ring); |
852835f3 | 2060 | request->ring = ring; |
7d736f4f | 2061 | request->head = request_start; |
a71d8d94 | 2062 | request->tail = request_ring_position; |
7d736f4f MK |
2063 | |
2064 | /* Whilst this request exists, batch_obj will be on the | |
2065 | * active_list, and so will hold the active reference. Only when this | |
2066 | * request is retired will the the batch_obj be moved onto the | |
2067 | * inactive_list and lose its active reference. Hence we do not need | |
2068 | * to explicitly hold another reference here. | |
2069 | */ | |
9a7e0c2a | 2070 | request->batch_obj = obj; |
0e50e96b | 2071 | |
9a7e0c2a CW |
2072 | /* Hold a reference to the current context so that we can inspect |
2073 | * it later in case a hangcheck error event fires. | |
2074 | */ | |
2075 | request->ctx = ring->last_context; | |
0e50e96b MK |
2076 | if (request->ctx) |
2077 | i915_gem_context_reference(request->ctx); | |
2078 | ||
673a394b | 2079 | request->emitted_jiffies = jiffies; |
852835f3 ZN |
2080 | was_empty = list_empty(&ring->request_list); |
2081 | list_add_tail(&request->list, &ring->request_list); | |
3bb73aba | 2082 | request->file_priv = NULL; |
852835f3 | 2083 | |
db53a302 CW |
2084 | if (file) { |
2085 | struct drm_i915_file_private *file_priv = file->driver_priv; | |
2086 | ||
1c25595f | 2087 | spin_lock(&file_priv->mm.lock); |
f787a5f5 | 2088 | request->file_priv = file_priv; |
b962442e | 2089 | list_add_tail(&request->client_list, |
f787a5f5 | 2090 | &file_priv->mm.request_list); |
1c25595f | 2091 | spin_unlock(&file_priv->mm.lock); |
b962442e | 2092 | } |
673a394b | 2093 | |
9d773091 | 2094 | trace_i915_gem_request_add(ring, request->seqno); |
1823521d | 2095 | ring->outstanding_lazy_seqno = 0; |
3c0e234c | 2096 | ring->preallocated_lazy_request = NULL; |
db53a302 | 2097 | |
db1b76ca | 2098 | if (!dev_priv->ums.mm_suspended) { |
10cd45b6 MK |
2099 | i915_queue_hangcheck(ring->dev); |
2100 | ||
f047e395 | 2101 | if (was_empty) { |
b3b079db | 2102 | queue_delayed_work(dev_priv->wq, |
bcb45086 CW |
2103 | &dev_priv->mm.retire_work, |
2104 | round_jiffies_up_relative(HZ)); | |
f047e395 CW |
2105 | intel_mark_busy(dev_priv->dev); |
2106 | } | |
f65d9421 | 2107 | } |
cc889e0f | 2108 | |
acb868d3 | 2109 | if (out_seqno) |
9d773091 | 2110 | *out_seqno = request->seqno; |
3cce469c | 2111 | return 0; |
673a394b EA |
2112 | } |
2113 | ||
f787a5f5 CW |
2114 | static inline void |
2115 | i915_gem_request_remove_from_client(struct drm_i915_gem_request *request) | |
673a394b | 2116 | { |
1c25595f | 2117 | struct drm_i915_file_private *file_priv = request->file_priv; |
673a394b | 2118 | |
1c25595f CW |
2119 | if (!file_priv) |
2120 | return; | |
1c5d22f7 | 2121 | |
1c25595f | 2122 | spin_lock(&file_priv->mm.lock); |
09bfa517 HRK |
2123 | if (request->file_priv) { |
2124 | list_del(&request->client_list); | |
2125 | request->file_priv = NULL; | |
2126 | } | |
1c25595f | 2127 | spin_unlock(&file_priv->mm.lock); |
673a394b | 2128 | } |
673a394b | 2129 | |
d1ccbb5d BW |
2130 | static bool i915_head_inside_object(u32 acthd, struct drm_i915_gem_object *obj, |
2131 | struct i915_address_space *vm) | |
aa60c664 | 2132 | { |
d1ccbb5d BW |
2133 | if (acthd >= i915_gem_obj_offset(obj, vm) && |
2134 | acthd < i915_gem_obj_offset(obj, vm) + obj->base.size) | |
aa60c664 MK |
2135 | return true; |
2136 | ||
2137 | return false; | |
2138 | } | |
2139 | ||
2140 | static bool i915_head_inside_request(const u32 acthd_unmasked, | |
2141 | const u32 request_start, | |
2142 | const u32 request_end) | |
2143 | { | |
2144 | const u32 acthd = acthd_unmasked & HEAD_ADDR; | |
2145 | ||
2146 | if (request_start < request_end) { | |
2147 | if (acthd >= request_start && acthd < request_end) | |
2148 | return true; | |
2149 | } else if (request_start > request_end) { | |
2150 | if (acthd >= request_start || acthd < request_end) | |
2151 | return true; | |
2152 | } | |
2153 | ||
2154 | return false; | |
2155 | } | |
2156 | ||
d1ccbb5d BW |
2157 | static struct i915_address_space * |
2158 | request_to_vm(struct drm_i915_gem_request *request) | |
2159 | { | |
2160 | struct drm_i915_private *dev_priv = request->ring->dev->dev_private; | |
2161 | struct i915_address_space *vm; | |
2162 | ||
2163 | vm = &dev_priv->gtt.base; | |
2164 | ||
2165 | return vm; | |
2166 | } | |
2167 | ||
aa60c664 MK |
2168 | static bool i915_request_guilty(struct drm_i915_gem_request *request, |
2169 | const u32 acthd, bool *inside) | |
2170 | { | |
2171 | /* There is a possibility that unmasked head address | |
2172 | * pointing inside the ring, matches the batch_obj address range. | |
2173 | * However this is extremely unlikely. | |
2174 | */ | |
aa60c664 | 2175 | if (request->batch_obj) { |
d1ccbb5d BW |
2176 | if (i915_head_inside_object(acthd, request->batch_obj, |
2177 | request_to_vm(request))) { | |
aa60c664 MK |
2178 | *inside = true; |
2179 | return true; | |
2180 | } | |
2181 | } | |
2182 | ||
2183 | if (i915_head_inside_request(acthd, request->head, request->tail)) { | |
2184 | *inside = false; | |
2185 | return true; | |
2186 | } | |
2187 | ||
2188 | return false; | |
2189 | } | |
2190 | ||
be62acb4 MK |
2191 | static bool i915_context_is_banned(const struct i915_ctx_hang_stats *hs) |
2192 | { | |
2193 | const unsigned long elapsed = get_seconds() - hs->guilty_ts; | |
2194 | ||
2195 | if (hs->banned) | |
2196 | return true; | |
2197 | ||
2198 | if (elapsed <= DRM_I915_CTX_BAN_PERIOD) { | |
2199 | DRM_ERROR("context hanging too fast, declaring banned!\n"); | |
2200 | return true; | |
2201 | } | |
2202 | ||
2203 | return false; | |
2204 | } | |
2205 | ||
aa60c664 MK |
2206 | static void i915_set_reset_status(struct intel_ring_buffer *ring, |
2207 | struct drm_i915_gem_request *request, | |
2208 | u32 acthd) | |
2209 | { | |
2210 | struct i915_ctx_hang_stats *hs = NULL; | |
2211 | bool inside, guilty; | |
d1ccbb5d | 2212 | unsigned long offset = 0; |
aa60c664 MK |
2213 | |
2214 | /* Innocent until proven guilty */ | |
2215 | guilty = false; | |
2216 | ||
d1ccbb5d BW |
2217 | if (request->batch_obj) |
2218 | offset = i915_gem_obj_offset(request->batch_obj, | |
2219 | request_to_vm(request)); | |
2220 | ||
f2f4d82f | 2221 | if (ring->hangcheck.action != HANGCHECK_WAIT && |
aa60c664 | 2222 | i915_request_guilty(request, acthd, &inside)) { |
f343c5f6 | 2223 | DRM_ERROR("%s hung %s bo (0x%lx ctx %d) at 0x%x\n", |
aa60c664 MK |
2224 | ring->name, |
2225 | inside ? "inside" : "flushing", | |
d1ccbb5d | 2226 | offset, |
aa60c664 MK |
2227 | request->ctx ? request->ctx->id : 0, |
2228 | acthd); | |
2229 | ||
2230 | guilty = true; | |
2231 | } | |
2232 | ||
2233 | /* If contexts are disabled or this is the default context, use | |
2234 | * file_priv->reset_state | |
2235 | */ | |
2236 | if (request->ctx && request->ctx->id != DEFAULT_CONTEXT_ID) | |
2237 | hs = &request->ctx->hang_stats; | |
2238 | else if (request->file_priv) | |
2239 | hs = &request->file_priv->hang_stats; | |
2240 | ||
2241 | if (hs) { | |
be62acb4 MK |
2242 | if (guilty) { |
2243 | hs->banned = i915_context_is_banned(hs); | |
aa60c664 | 2244 | hs->batch_active++; |
be62acb4 MK |
2245 | hs->guilty_ts = get_seconds(); |
2246 | } else { | |
aa60c664 | 2247 | hs->batch_pending++; |
be62acb4 | 2248 | } |
aa60c664 MK |
2249 | } |
2250 | } | |
2251 | ||
0e50e96b MK |
2252 | static void i915_gem_free_request(struct drm_i915_gem_request *request) |
2253 | { | |
2254 | list_del(&request->list); | |
2255 | i915_gem_request_remove_from_client(request); | |
2256 | ||
2257 | if (request->ctx) | |
2258 | i915_gem_context_unreference(request->ctx); | |
2259 | ||
2260 | kfree(request); | |
2261 | } | |
2262 | ||
dfaae392 CW |
2263 | static void i915_gem_reset_ring_lists(struct drm_i915_private *dev_priv, |
2264 | struct intel_ring_buffer *ring) | |
9375e446 | 2265 | { |
aa60c664 MK |
2266 | u32 completed_seqno; |
2267 | u32 acthd; | |
2268 | ||
2269 | acthd = intel_ring_get_active_head(ring); | |
2270 | completed_seqno = ring->get_seqno(ring, false); | |
2271 | ||
dfaae392 CW |
2272 | while (!list_empty(&ring->request_list)) { |
2273 | struct drm_i915_gem_request *request; | |
673a394b | 2274 | |
dfaae392 CW |
2275 | request = list_first_entry(&ring->request_list, |
2276 | struct drm_i915_gem_request, | |
2277 | list); | |
de151cf6 | 2278 | |
aa60c664 MK |
2279 | if (request->seqno > completed_seqno) |
2280 | i915_set_reset_status(ring, request, acthd); | |
2281 | ||
0e50e96b | 2282 | i915_gem_free_request(request); |
dfaae392 | 2283 | } |
673a394b | 2284 | |
dfaae392 | 2285 | while (!list_empty(&ring->active_list)) { |
05394f39 | 2286 | struct drm_i915_gem_object *obj; |
9375e446 | 2287 | |
05394f39 CW |
2288 | obj = list_first_entry(&ring->active_list, |
2289 | struct drm_i915_gem_object, | |
2290 | ring_list); | |
9375e446 | 2291 | |
05394f39 | 2292 | i915_gem_object_move_to_inactive(obj); |
673a394b EA |
2293 | } |
2294 | } | |
2295 | ||
19b2dbde | 2296 | void i915_gem_restore_fences(struct drm_device *dev) |
312817a3 CW |
2297 | { |
2298 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2299 | int i; | |
2300 | ||
4b9de737 | 2301 | for (i = 0; i < dev_priv->num_fence_regs; i++) { |
312817a3 | 2302 | struct drm_i915_fence_reg *reg = &dev_priv->fence_regs[i]; |
7d2cb39c | 2303 | |
94a335db DV |
2304 | /* |
2305 | * Commit delayed tiling changes if we have an object still | |
2306 | * attached to the fence, otherwise just clear the fence. | |
2307 | */ | |
2308 | if (reg->obj) { | |
2309 | i915_gem_object_update_fence(reg->obj, reg, | |
2310 | reg->obj->tiling_mode); | |
2311 | } else { | |
2312 | i915_gem_write_fence(dev, i, NULL); | |
2313 | } | |
312817a3 CW |
2314 | } |
2315 | } | |
2316 | ||
069efc1d | 2317 | void i915_gem_reset(struct drm_device *dev) |
673a394b | 2318 | { |
77f01230 | 2319 | struct drm_i915_private *dev_priv = dev->dev_private; |
b4519513 | 2320 | struct intel_ring_buffer *ring; |
1ec14ad3 | 2321 | int i; |
673a394b | 2322 | |
b4519513 CW |
2323 | for_each_ring(ring, dev_priv, i) |
2324 | i915_gem_reset_ring_lists(dev_priv, ring); | |
dfaae392 | 2325 | |
19b2dbde | 2326 | i915_gem_restore_fences(dev); |
673a394b EA |
2327 | } |
2328 | ||
2329 | /** | |
2330 | * This function clears the request list as sequence numbers are passed. | |
2331 | */ | |
a71d8d94 | 2332 | void |
db53a302 | 2333 | i915_gem_retire_requests_ring(struct intel_ring_buffer *ring) |
673a394b | 2334 | { |
673a394b EA |
2335 | uint32_t seqno; |
2336 | ||
db53a302 | 2337 | if (list_empty(&ring->request_list)) |
6c0594a3 KW |
2338 | return; |
2339 | ||
db53a302 | 2340 | WARN_ON(i915_verify_lists(ring->dev)); |
673a394b | 2341 | |
b2eadbc8 | 2342 | seqno = ring->get_seqno(ring, true); |
1ec14ad3 | 2343 | |
852835f3 | 2344 | while (!list_empty(&ring->request_list)) { |
673a394b | 2345 | struct drm_i915_gem_request *request; |
673a394b | 2346 | |
852835f3 | 2347 | request = list_first_entry(&ring->request_list, |
673a394b EA |
2348 | struct drm_i915_gem_request, |
2349 | list); | |
673a394b | 2350 | |
dfaae392 | 2351 | if (!i915_seqno_passed(seqno, request->seqno)) |
b84d5f0c CW |
2352 | break; |
2353 | ||
db53a302 | 2354 | trace_i915_gem_request_retire(ring, request->seqno); |
a71d8d94 CW |
2355 | /* We know the GPU must have read the request to have |
2356 | * sent us the seqno + interrupt, so use the position | |
2357 | * of tail of the request to update the last known position | |
2358 | * of the GPU head. | |
2359 | */ | |
2360 | ring->last_retired_head = request->tail; | |
b84d5f0c | 2361 | |
0e50e96b | 2362 | i915_gem_free_request(request); |
b84d5f0c | 2363 | } |
673a394b | 2364 | |
b84d5f0c CW |
2365 | /* Move any buffers on the active list that are no longer referenced |
2366 | * by the ringbuffer to the flushing/inactive lists as appropriate. | |
2367 | */ | |
2368 | while (!list_empty(&ring->active_list)) { | |
05394f39 | 2369 | struct drm_i915_gem_object *obj; |
b84d5f0c | 2370 | |
0206e353 | 2371 | obj = list_first_entry(&ring->active_list, |
05394f39 CW |
2372 | struct drm_i915_gem_object, |
2373 | ring_list); | |
673a394b | 2374 | |
0201f1ec | 2375 | if (!i915_seqno_passed(seqno, obj->last_read_seqno)) |
673a394b | 2376 | break; |
b84d5f0c | 2377 | |
65ce3027 | 2378 | i915_gem_object_move_to_inactive(obj); |
673a394b | 2379 | } |
9d34e5db | 2380 | |
db53a302 CW |
2381 | if (unlikely(ring->trace_irq_seqno && |
2382 | i915_seqno_passed(seqno, ring->trace_irq_seqno))) { | |
1ec14ad3 | 2383 | ring->irq_put(ring); |
db53a302 | 2384 | ring->trace_irq_seqno = 0; |
9d34e5db | 2385 | } |
23bc5982 | 2386 | |
db53a302 | 2387 | WARN_ON(i915_verify_lists(ring->dev)); |
673a394b EA |
2388 | } |
2389 | ||
b09a1fec CW |
2390 | void |
2391 | i915_gem_retire_requests(struct drm_device *dev) | |
2392 | { | |
2393 | drm_i915_private_t *dev_priv = dev->dev_private; | |
b4519513 | 2394 | struct intel_ring_buffer *ring; |
1ec14ad3 | 2395 | int i; |
b09a1fec | 2396 | |
b4519513 CW |
2397 | for_each_ring(ring, dev_priv, i) |
2398 | i915_gem_retire_requests_ring(ring); | |
b09a1fec CW |
2399 | } |
2400 | ||
75ef9da2 | 2401 | static void |
673a394b EA |
2402 | i915_gem_retire_work_handler(struct work_struct *work) |
2403 | { | |
2404 | drm_i915_private_t *dev_priv; | |
2405 | struct drm_device *dev; | |
b4519513 | 2406 | struct intel_ring_buffer *ring; |
0a58705b CW |
2407 | bool idle; |
2408 | int i; | |
673a394b EA |
2409 | |
2410 | dev_priv = container_of(work, drm_i915_private_t, | |
2411 | mm.retire_work.work); | |
2412 | dev = dev_priv->dev; | |
2413 | ||
891b48cf CW |
2414 | /* Come back later if the device is busy... */ |
2415 | if (!mutex_trylock(&dev->struct_mutex)) { | |
bcb45086 CW |
2416 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, |
2417 | round_jiffies_up_relative(HZ)); | |
891b48cf CW |
2418 | return; |
2419 | } | |
673a394b | 2420 | |
b09a1fec | 2421 | i915_gem_retire_requests(dev); |
673a394b | 2422 | |
0a58705b CW |
2423 | /* Send a periodic flush down the ring so we don't hold onto GEM |
2424 | * objects indefinitely. | |
673a394b | 2425 | */ |
0a58705b | 2426 | idle = true; |
b4519513 | 2427 | for_each_ring(ring, dev_priv, i) { |
3bb73aba | 2428 | if (ring->gpu_caches_dirty) |
0025c077 | 2429 | i915_add_request(ring, NULL); |
0a58705b CW |
2430 | |
2431 | idle &= list_empty(&ring->request_list); | |
673a394b EA |
2432 | } |
2433 | ||
db1b76ca | 2434 | if (!dev_priv->ums.mm_suspended && !idle) |
bcb45086 CW |
2435 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, |
2436 | round_jiffies_up_relative(HZ)); | |
f047e395 CW |
2437 | if (idle) |
2438 | intel_mark_idle(dev); | |
0a58705b | 2439 | |
673a394b | 2440 | mutex_unlock(&dev->struct_mutex); |
673a394b EA |
2441 | } |
2442 | ||
30dfebf3 DV |
2443 | /** |
2444 | * Ensures that an object will eventually get non-busy by flushing any required | |
2445 | * write domains, emitting any outstanding lazy request and retiring and | |
2446 | * completed requests. | |
2447 | */ | |
2448 | static int | |
2449 | i915_gem_object_flush_active(struct drm_i915_gem_object *obj) | |
2450 | { | |
2451 | int ret; | |
2452 | ||
2453 | if (obj->active) { | |
0201f1ec | 2454 | ret = i915_gem_check_olr(obj->ring, obj->last_read_seqno); |
30dfebf3 DV |
2455 | if (ret) |
2456 | return ret; | |
2457 | ||
30dfebf3 DV |
2458 | i915_gem_retire_requests_ring(obj->ring); |
2459 | } | |
2460 | ||
2461 | return 0; | |
2462 | } | |
2463 | ||
23ba4fd0 BW |
2464 | /** |
2465 | * i915_gem_wait_ioctl - implements DRM_IOCTL_I915_GEM_WAIT | |
2466 | * @DRM_IOCTL_ARGS: standard ioctl arguments | |
2467 | * | |
2468 | * Returns 0 if successful, else an error is returned with the remaining time in | |
2469 | * the timeout parameter. | |
2470 | * -ETIME: object is still busy after timeout | |
2471 | * -ERESTARTSYS: signal interrupted the wait | |
2472 | * -ENONENT: object doesn't exist | |
2473 | * Also possible, but rare: | |
2474 | * -EAGAIN: GPU wedged | |
2475 | * -ENOMEM: damn | |
2476 | * -ENODEV: Internal IRQ fail | |
2477 | * -E?: The add request failed | |
2478 | * | |
2479 | * The wait ioctl with a timeout of 0 reimplements the busy ioctl. With any | |
2480 | * non-zero timeout parameter the wait ioctl will wait for the given number of | |
2481 | * nanoseconds on an object becoming unbusy. Since the wait itself does so | |
2482 | * without holding struct_mutex the object may become re-busied before this | |
2483 | * function completes. A similar but shorter * race condition exists in the busy | |
2484 | * ioctl | |
2485 | */ | |
2486 | int | |
2487 | i915_gem_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *file) | |
2488 | { | |
f69061be | 2489 | drm_i915_private_t *dev_priv = dev->dev_private; |
23ba4fd0 BW |
2490 | struct drm_i915_gem_wait *args = data; |
2491 | struct drm_i915_gem_object *obj; | |
2492 | struct intel_ring_buffer *ring = NULL; | |
eac1f14f | 2493 | struct timespec timeout_stack, *timeout = NULL; |
f69061be | 2494 | unsigned reset_counter; |
23ba4fd0 BW |
2495 | u32 seqno = 0; |
2496 | int ret = 0; | |
2497 | ||
eac1f14f BW |
2498 | if (args->timeout_ns >= 0) { |
2499 | timeout_stack = ns_to_timespec(args->timeout_ns); | |
2500 | timeout = &timeout_stack; | |
2501 | } | |
23ba4fd0 BW |
2502 | |
2503 | ret = i915_mutex_lock_interruptible(dev); | |
2504 | if (ret) | |
2505 | return ret; | |
2506 | ||
2507 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->bo_handle)); | |
2508 | if (&obj->base == NULL) { | |
2509 | mutex_unlock(&dev->struct_mutex); | |
2510 | return -ENOENT; | |
2511 | } | |
2512 | ||
30dfebf3 DV |
2513 | /* Need to make sure the object gets inactive eventually. */ |
2514 | ret = i915_gem_object_flush_active(obj); | |
23ba4fd0 BW |
2515 | if (ret) |
2516 | goto out; | |
2517 | ||
2518 | if (obj->active) { | |
0201f1ec | 2519 | seqno = obj->last_read_seqno; |
23ba4fd0 BW |
2520 | ring = obj->ring; |
2521 | } | |
2522 | ||
2523 | if (seqno == 0) | |
2524 | goto out; | |
2525 | ||
23ba4fd0 BW |
2526 | /* Do this after OLR check to make sure we make forward progress polling |
2527 | * on this IOCTL with a 0 timeout (like busy ioctl) | |
2528 | */ | |
2529 | if (!args->timeout_ns) { | |
2530 | ret = -ETIME; | |
2531 | goto out; | |
2532 | } | |
2533 | ||
2534 | drm_gem_object_unreference(&obj->base); | |
f69061be | 2535 | reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter); |
23ba4fd0 BW |
2536 | mutex_unlock(&dev->struct_mutex); |
2537 | ||
f69061be | 2538 | ret = __wait_seqno(ring, seqno, reset_counter, true, timeout); |
4f42f4ef | 2539 | if (timeout) |
eac1f14f | 2540 | args->timeout_ns = timespec_to_ns(timeout); |
23ba4fd0 BW |
2541 | return ret; |
2542 | ||
2543 | out: | |
2544 | drm_gem_object_unreference(&obj->base); | |
2545 | mutex_unlock(&dev->struct_mutex); | |
2546 | return ret; | |
2547 | } | |
2548 | ||
5816d648 BW |
2549 | /** |
2550 | * i915_gem_object_sync - sync an object to a ring. | |
2551 | * | |
2552 | * @obj: object which may be in use on another ring. | |
2553 | * @to: ring we wish to use the object on. May be NULL. | |
2554 | * | |
2555 | * This code is meant to abstract object synchronization with the GPU. | |
2556 | * Calling with NULL implies synchronizing the object with the CPU | |
2557 | * rather than a particular GPU ring. | |
2558 | * | |
2559 | * Returns 0 if successful, else propagates up the lower layer error. | |
2560 | */ | |
2911a35b BW |
2561 | int |
2562 | i915_gem_object_sync(struct drm_i915_gem_object *obj, | |
2563 | struct intel_ring_buffer *to) | |
2564 | { | |
2565 | struct intel_ring_buffer *from = obj->ring; | |
2566 | u32 seqno; | |
2567 | int ret, idx; | |
2568 | ||
2569 | if (from == NULL || to == from) | |
2570 | return 0; | |
2571 | ||
5816d648 | 2572 | if (to == NULL || !i915_semaphore_is_enabled(obj->base.dev)) |
0201f1ec | 2573 | return i915_gem_object_wait_rendering(obj, false); |
2911a35b BW |
2574 | |
2575 | idx = intel_ring_sync_index(from, to); | |
2576 | ||
0201f1ec | 2577 | seqno = obj->last_read_seqno; |
2911a35b BW |
2578 | if (seqno <= from->sync_seqno[idx]) |
2579 | return 0; | |
2580 | ||
b4aca010 BW |
2581 | ret = i915_gem_check_olr(obj->ring, seqno); |
2582 | if (ret) | |
2583 | return ret; | |
2911a35b | 2584 | |
1500f7ea | 2585 | ret = to->sync_to(to, from, seqno); |
e3a5a225 | 2586 | if (!ret) |
7b01e260 MK |
2587 | /* We use last_read_seqno because sync_to() |
2588 | * might have just caused seqno wrap under | |
2589 | * the radar. | |
2590 | */ | |
2591 | from->sync_seqno[idx] = obj->last_read_seqno; | |
2911a35b | 2592 | |
e3a5a225 | 2593 | return ret; |
2911a35b BW |
2594 | } |
2595 | ||
b5ffc9bc CW |
2596 | static void i915_gem_object_finish_gtt(struct drm_i915_gem_object *obj) |
2597 | { | |
2598 | u32 old_write_domain, old_read_domains; | |
2599 | ||
b5ffc9bc CW |
2600 | /* Force a pagefault for domain tracking on next user access */ |
2601 | i915_gem_release_mmap(obj); | |
2602 | ||
b97c3d9c KP |
2603 | if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0) |
2604 | return; | |
2605 | ||
97c809fd CW |
2606 | /* Wait for any direct GTT access to complete */ |
2607 | mb(); | |
2608 | ||
b5ffc9bc CW |
2609 | old_read_domains = obj->base.read_domains; |
2610 | old_write_domain = obj->base.write_domain; | |
2611 | ||
2612 | obj->base.read_domains &= ~I915_GEM_DOMAIN_GTT; | |
2613 | obj->base.write_domain &= ~I915_GEM_DOMAIN_GTT; | |
2614 | ||
2615 | trace_i915_gem_object_change_domain(obj, | |
2616 | old_read_domains, | |
2617 | old_write_domain); | |
2618 | } | |
2619 | ||
07fe0b12 | 2620 | int i915_vma_unbind(struct i915_vma *vma) |
673a394b | 2621 | { |
07fe0b12 | 2622 | struct drm_i915_gem_object *obj = vma->obj; |
7bddb01f | 2623 | drm_i915_private_t *dev_priv = obj->base.dev->dev_private; |
43e28f09 | 2624 | int ret; |
673a394b | 2625 | |
b93dab6e DV |
2626 | /* For now we only ever use 1 vma per object */ |
2627 | WARN_ON(!list_is_singular(&obj->vma_list)); | |
2628 | ||
07fe0b12 | 2629 | if (list_empty(&vma->vma_link)) |
673a394b EA |
2630 | return 0; |
2631 | ||
0ff501cb DV |
2632 | if (!drm_mm_node_allocated(&vma->node)) { |
2633 | i915_gem_vma_destroy(vma); | |
2634 | ||
2635 | return 0; | |
2636 | } | |
433544bd | 2637 | |
31d8d651 CW |
2638 | if (obj->pin_count) |
2639 | return -EBUSY; | |
673a394b | 2640 | |
c4670ad0 CW |
2641 | BUG_ON(obj->pages == NULL); |
2642 | ||
a8198eea | 2643 | ret = i915_gem_object_finish_gpu(obj); |
1488fc08 | 2644 | if (ret) |
a8198eea CW |
2645 | return ret; |
2646 | /* Continue on if we fail due to EIO, the GPU is hung so we | |
2647 | * should be safe and we need to cleanup or else we might | |
2648 | * cause memory corruption through use-after-free. | |
2649 | */ | |
2650 | ||
b5ffc9bc | 2651 | i915_gem_object_finish_gtt(obj); |
5323fd04 | 2652 | |
96b47b65 | 2653 | /* release the fence reg _after_ flushing */ |
d9e86c0e | 2654 | ret = i915_gem_object_put_fence(obj); |
1488fc08 | 2655 | if (ret) |
d9e86c0e | 2656 | return ret; |
96b47b65 | 2657 | |
07fe0b12 | 2658 | trace_i915_vma_unbind(vma); |
db53a302 | 2659 | |
74898d7e DV |
2660 | if (obj->has_global_gtt_mapping) |
2661 | i915_gem_gtt_unbind_object(obj); | |
7bddb01f DV |
2662 | if (obj->has_aliasing_ppgtt_mapping) { |
2663 | i915_ppgtt_unbind_object(dev_priv->mm.aliasing_ppgtt, obj); | |
2664 | obj->has_aliasing_ppgtt_mapping = 0; | |
2665 | } | |
74163907 | 2666 | i915_gem_gtt_finish_object(obj); |
401c29f6 | 2667 | i915_gem_object_unpin_pages(obj); |
7bddb01f | 2668 | |
ca191b13 | 2669 | list_del(&vma->mm_list); |
75e9e915 | 2670 | /* Avoid an unnecessary call to unbind on rebind. */ |
5cacaac7 BW |
2671 | if (i915_is_ggtt(vma->vm)) |
2672 | obj->map_and_fenceable = true; | |
673a394b | 2673 | |
2f633156 | 2674 | drm_mm_remove_node(&vma->node); |
433544bd | 2675 | |
2f633156 BW |
2676 | i915_gem_vma_destroy(vma); |
2677 | ||
2678 | /* Since the unbound list is global, only move to that list if | |
b93dab6e | 2679 | * no more VMAs exist. */ |
2f633156 BW |
2680 | if (list_empty(&obj->vma_list)) |
2681 | list_move_tail(&obj->global_list, &dev_priv->mm.unbound_list); | |
673a394b | 2682 | |
88241785 | 2683 | return 0; |
54cf91dc CW |
2684 | } |
2685 | ||
07fe0b12 BW |
2686 | /** |
2687 | * Unbinds an object from the global GTT aperture. | |
2688 | */ | |
2689 | int | |
2690 | i915_gem_object_ggtt_unbind(struct drm_i915_gem_object *obj) | |
2691 | { | |
2692 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; | |
2693 | struct i915_address_space *ggtt = &dev_priv->gtt.base; | |
2694 | ||
58e73e15 | 2695 | if (!i915_gem_obj_ggtt_bound(obj)) |
07fe0b12 BW |
2696 | return 0; |
2697 | ||
2698 | if (obj->pin_count) | |
2699 | return -EBUSY; | |
2700 | ||
2701 | BUG_ON(obj->pages == NULL); | |
2702 | ||
2703 | return i915_vma_unbind(i915_gem_obj_to_vma(obj, ggtt)); | |
2704 | } | |
2705 | ||
b2da9fe5 | 2706 | int i915_gpu_idle(struct drm_device *dev) |
4df2faf4 DV |
2707 | { |
2708 | drm_i915_private_t *dev_priv = dev->dev_private; | |
b4519513 | 2709 | struct intel_ring_buffer *ring; |
1ec14ad3 | 2710 | int ret, i; |
4df2faf4 | 2711 | |
4df2faf4 | 2712 | /* Flush everything onto the inactive list. */ |
b4519513 | 2713 | for_each_ring(ring, dev_priv, i) { |
b6c7488d BW |
2714 | ret = i915_switch_context(ring, NULL, DEFAULT_CONTEXT_ID); |
2715 | if (ret) | |
2716 | return ret; | |
2717 | ||
3e960501 | 2718 | ret = intel_ring_idle(ring); |
1ec14ad3 CW |
2719 | if (ret) |
2720 | return ret; | |
2721 | } | |
4df2faf4 | 2722 | |
8a1a49f9 | 2723 | return 0; |
4df2faf4 DV |
2724 | } |
2725 | ||
9ce079e4 CW |
2726 | static void i965_write_fence_reg(struct drm_device *dev, int reg, |
2727 | struct drm_i915_gem_object *obj) | |
de151cf6 | 2728 | { |
de151cf6 | 2729 | drm_i915_private_t *dev_priv = dev->dev_private; |
56c844e5 ID |
2730 | int fence_reg; |
2731 | int fence_pitch_shift; | |
de151cf6 | 2732 | |
56c844e5 ID |
2733 | if (INTEL_INFO(dev)->gen >= 6) { |
2734 | fence_reg = FENCE_REG_SANDYBRIDGE_0; | |
2735 | fence_pitch_shift = SANDYBRIDGE_FENCE_PITCH_SHIFT; | |
2736 | } else { | |
2737 | fence_reg = FENCE_REG_965_0; | |
2738 | fence_pitch_shift = I965_FENCE_PITCH_SHIFT; | |
2739 | } | |
2740 | ||
d18b9619 CW |
2741 | fence_reg += reg * 8; |
2742 | ||
2743 | /* To w/a incoherency with non-atomic 64-bit register updates, | |
2744 | * we split the 64-bit update into two 32-bit writes. In order | |
2745 | * for a partial fence not to be evaluated between writes, we | |
2746 | * precede the update with write to turn off the fence register, | |
2747 | * and only enable the fence as the last step. | |
2748 | * | |
2749 | * For extra levels of paranoia, we make sure each step lands | |
2750 | * before applying the next step. | |
2751 | */ | |
2752 | I915_WRITE(fence_reg, 0); | |
2753 | POSTING_READ(fence_reg); | |
2754 | ||
9ce079e4 | 2755 | if (obj) { |
f343c5f6 | 2756 | u32 size = i915_gem_obj_ggtt_size(obj); |
d18b9619 | 2757 | uint64_t val; |
de151cf6 | 2758 | |
f343c5f6 | 2759 | val = (uint64_t)((i915_gem_obj_ggtt_offset(obj) + size - 4096) & |
9ce079e4 | 2760 | 0xfffff000) << 32; |
f343c5f6 | 2761 | val |= i915_gem_obj_ggtt_offset(obj) & 0xfffff000; |
56c844e5 | 2762 | val |= (uint64_t)((obj->stride / 128) - 1) << fence_pitch_shift; |
9ce079e4 CW |
2763 | if (obj->tiling_mode == I915_TILING_Y) |
2764 | val |= 1 << I965_FENCE_TILING_Y_SHIFT; | |
2765 | val |= I965_FENCE_REG_VALID; | |
c6642782 | 2766 | |
d18b9619 CW |
2767 | I915_WRITE(fence_reg + 4, val >> 32); |
2768 | POSTING_READ(fence_reg + 4); | |
2769 | ||
2770 | I915_WRITE(fence_reg + 0, val); | |
2771 | POSTING_READ(fence_reg); | |
2772 | } else { | |
2773 | I915_WRITE(fence_reg + 4, 0); | |
2774 | POSTING_READ(fence_reg + 4); | |
2775 | } | |
de151cf6 JB |
2776 | } |
2777 | ||
9ce079e4 CW |
2778 | static void i915_write_fence_reg(struct drm_device *dev, int reg, |
2779 | struct drm_i915_gem_object *obj) | |
de151cf6 | 2780 | { |
de151cf6 | 2781 | drm_i915_private_t *dev_priv = dev->dev_private; |
9ce079e4 | 2782 | u32 val; |
de151cf6 | 2783 | |
9ce079e4 | 2784 | if (obj) { |
f343c5f6 | 2785 | u32 size = i915_gem_obj_ggtt_size(obj); |
9ce079e4 CW |
2786 | int pitch_val; |
2787 | int tile_width; | |
c6642782 | 2788 | |
f343c5f6 | 2789 | WARN((i915_gem_obj_ggtt_offset(obj) & ~I915_FENCE_START_MASK) || |
9ce079e4 | 2790 | (size & -size) != size || |
f343c5f6 BW |
2791 | (i915_gem_obj_ggtt_offset(obj) & (size - 1)), |
2792 | "object 0x%08lx [fenceable? %d] not 1M or pot-size (0x%08x) aligned\n", | |
2793 | i915_gem_obj_ggtt_offset(obj), obj->map_and_fenceable, size); | |
c6642782 | 2794 | |
9ce079e4 CW |
2795 | if (obj->tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev)) |
2796 | tile_width = 128; | |
2797 | else | |
2798 | tile_width = 512; | |
2799 | ||
2800 | /* Note: pitch better be a power of two tile widths */ | |
2801 | pitch_val = obj->stride / tile_width; | |
2802 | pitch_val = ffs(pitch_val) - 1; | |
2803 | ||
f343c5f6 | 2804 | val = i915_gem_obj_ggtt_offset(obj); |
9ce079e4 CW |
2805 | if (obj->tiling_mode == I915_TILING_Y) |
2806 | val |= 1 << I830_FENCE_TILING_Y_SHIFT; | |
2807 | val |= I915_FENCE_SIZE_BITS(size); | |
2808 | val |= pitch_val << I830_FENCE_PITCH_SHIFT; | |
2809 | val |= I830_FENCE_REG_VALID; | |
2810 | } else | |
2811 | val = 0; | |
2812 | ||
2813 | if (reg < 8) | |
2814 | reg = FENCE_REG_830_0 + reg * 4; | |
2815 | else | |
2816 | reg = FENCE_REG_945_8 + (reg - 8) * 4; | |
2817 | ||
2818 | I915_WRITE(reg, val); | |
2819 | POSTING_READ(reg); | |
de151cf6 JB |
2820 | } |
2821 | ||
9ce079e4 CW |
2822 | static void i830_write_fence_reg(struct drm_device *dev, int reg, |
2823 | struct drm_i915_gem_object *obj) | |
de151cf6 | 2824 | { |
de151cf6 | 2825 | drm_i915_private_t *dev_priv = dev->dev_private; |
de151cf6 | 2826 | uint32_t val; |
de151cf6 | 2827 | |
9ce079e4 | 2828 | if (obj) { |
f343c5f6 | 2829 | u32 size = i915_gem_obj_ggtt_size(obj); |
9ce079e4 | 2830 | uint32_t pitch_val; |
de151cf6 | 2831 | |
f343c5f6 | 2832 | WARN((i915_gem_obj_ggtt_offset(obj) & ~I830_FENCE_START_MASK) || |
9ce079e4 | 2833 | (size & -size) != size || |
f343c5f6 BW |
2834 | (i915_gem_obj_ggtt_offset(obj) & (size - 1)), |
2835 | "object 0x%08lx not 512K or pot-size 0x%08x aligned\n", | |
2836 | i915_gem_obj_ggtt_offset(obj), size); | |
e76a16de | 2837 | |
9ce079e4 CW |
2838 | pitch_val = obj->stride / 128; |
2839 | pitch_val = ffs(pitch_val) - 1; | |
de151cf6 | 2840 | |
f343c5f6 | 2841 | val = i915_gem_obj_ggtt_offset(obj); |
9ce079e4 CW |
2842 | if (obj->tiling_mode == I915_TILING_Y) |
2843 | val |= 1 << I830_FENCE_TILING_Y_SHIFT; | |
2844 | val |= I830_FENCE_SIZE_BITS(size); | |
2845 | val |= pitch_val << I830_FENCE_PITCH_SHIFT; | |
2846 | val |= I830_FENCE_REG_VALID; | |
2847 | } else | |
2848 | val = 0; | |
c6642782 | 2849 | |
9ce079e4 CW |
2850 | I915_WRITE(FENCE_REG_830_0 + reg * 4, val); |
2851 | POSTING_READ(FENCE_REG_830_0 + reg * 4); | |
2852 | } | |
2853 | ||
d0a57789 CW |
2854 | inline static bool i915_gem_object_needs_mb(struct drm_i915_gem_object *obj) |
2855 | { | |
2856 | return obj && obj->base.read_domains & I915_GEM_DOMAIN_GTT; | |
2857 | } | |
2858 | ||
9ce079e4 CW |
2859 | static void i915_gem_write_fence(struct drm_device *dev, int reg, |
2860 | struct drm_i915_gem_object *obj) | |
2861 | { | |
d0a57789 CW |
2862 | struct drm_i915_private *dev_priv = dev->dev_private; |
2863 | ||
2864 | /* Ensure that all CPU reads are completed before installing a fence | |
2865 | * and all writes before removing the fence. | |
2866 | */ | |
2867 | if (i915_gem_object_needs_mb(dev_priv->fence_regs[reg].obj)) | |
2868 | mb(); | |
2869 | ||
94a335db DV |
2870 | WARN(obj && (!obj->stride || !obj->tiling_mode), |
2871 | "bogus fence setup with stride: 0x%x, tiling mode: %i\n", | |
2872 | obj->stride, obj->tiling_mode); | |
2873 | ||
9ce079e4 CW |
2874 | switch (INTEL_INFO(dev)->gen) { |
2875 | case 7: | |
56c844e5 | 2876 | case 6: |
9ce079e4 CW |
2877 | case 5: |
2878 | case 4: i965_write_fence_reg(dev, reg, obj); break; | |
2879 | case 3: i915_write_fence_reg(dev, reg, obj); break; | |
2880 | case 2: i830_write_fence_reg(dev, reg, obj); break; | |
7dbf9d6e | 2881 | default: BUG(); |
9ce079e4 | 2882 | } |
d0a57789 CW |
2883 | |
2884 | /* And similarly be paranoid that no direct access to this region | |
2885 | * is reordered to before the fence is installed. | |
2886 | */ | |
2887 | if (i915_gem_object_needs_mb(obj)) | |
2888 | mb(); | |
de151cf6 JB |
2889 | } |
2890 | ||
61050808 CW |
2891 | static inline int fence_number(struct drm_i915_private *dev_priv, |
2892 | struct drm_i915_fence_reg *fence) | |
2893 | { | |
2894 | return fence - dev_priv->fence_regs; | |
2895 | } | |
2896 | ||
2897 | static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj, | |
2898 | struct drm_i915_fence_reg *fence, | |
2899 | bool enable) | |
2900 | { | |
2dc8aae0 | 2901 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
46a0b638 CW |
2902 | int reg = fence_number(dev_priv, fence); |
2903 | ||
2904 | i915_gem_write_fence(obj->base.dev, reg, enable ? obj : NULL); | |
61050808 CW |
2905 | |
2906 | if (enable) { | |
46a0b638 | 2907 | obj->fence_reg = reg; |
61050808 CW |
2908 | fence->obj = obj; |
2909 | list_move_tail(&fence->lru_list, &dev_priv->mm.fence_list); | |
2910 | } else { | |
2911 | obj->fence_reg = I915_FENCE_REG_NONE; | |
2912 | fence->obj = NULL; | |
2913 | list_del_init(&fence->lru_list); | |
2914 | } | |
94a335db | 2915 | obj->fence_dirty = false; |
61050808 CW |
2916 | } |
2917 | ||
d9e86c0e | 2918 | static int |
d0a57789 | 2919 | i915_gem_object_wait_fence(struct drm_i915_gem_object *obj) |
d9e86c0e | 2920 | { |
1c293ea3 | 2921 | if (obj->last_fenced_seqno) { |
86d5bc37 | 2922 | int ret = i915_wait_seqno(obj->ring, obj->last_fenced_seqno); |
18991845 CW |
2923 | if (ret) |
2924 | return ret; | |
d9e86c0e CW |
2925 | |
2926 | obj->last_fenced_seqno = 0; | |
d9e86c0e CW |
2927 | } |
2928 | ||
86d5bc37 | 2929 | obj->fenced_gpu_access = false; |
d9e86c0e CW |
2930 | return 0; |
2931 | } | |
2932 | ||
2933 | int | |
2934 | i915_gem_object_put_fence(struct drm_i915_gem_object *obj) | |
2935 | { | |
61050808 | 2936 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
f9c513e9 | 2937 | struct drm_i915_fence_reg *fence; |
d9e86c0e CW |
2938 | int ret; |
2939 | ||
d0a57789 | 2940 | ret = i915_gem_object_wait_fence(obj); |
d9e86c0e CW |
2941 | if (ret) |
2942 | return ret; | |
2943 | ||
61050808 CW |
2944 | if (obj->fence_reg == I915_FENCE_REG_NONE) |
2945 | return 0; | |
d9e86c0e | 2946 | |
f9c513e9 CW |
2947 | fence = &dev_priv->fence_regs[obj->fence_reg]; |
2948 | ||
61050808 | 2949 | i915_gem_object_fence_lost(obj); |
f9c513e9 | 2950 | i915_gem_object_update_fence(obj, fence, false); |
d9e86c0e CW |
2951 | |
2952 | return 0; | |
2953 | } | |
2954 | ||
2955 | static struct drm_i915_fence_reg * | |
a360bb1a | 2956 | i915_find_fence_reg(struct drm_device *dev) |
ae3db24a | 2957 | { |
ae3db24a | 2958 | struct drm_i915_private *dev_priv = dev->dev_private; |
8fe301ad | 2959 | struct drm_i915_fence_reg *reg, *avail; |
d9e86c0e | 2960 | int i; |
ae3db24a DV |
2961 | |
2962 | /* First try to find a free reg */ | |
d9e86c0e | 2963 | avail = NULL; |
ae3db24a DV |
2964 | for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) { |
2965 | reg = &dev_priv->fence_regs[i]; | |
2966 | if (!reg->obj) | |
d9e86c0e | 2967 | return reg; |
ae3db24a | 2968 | |
1690e1eb | 2969 | if (!reg->pin_count) |
d9e86c0e | 2970 | avail = reg; |
ae3db24a DV |
2971 | } |
2972 | ||
d9e86c0e CW |
2973 | if (avail == NULL) |
2974 | return NULL; | |
ae3db24a DV |
2975 | |
2976 | /* None available, try to steal one or wait for a user to finish */ | |
d9e86c0e | 2977 | list_for_each_entry(reg, &dev_priv->mm.fence_list, lru_list) { |
1690e1eb | 2978 | if (reg->pin_count) |
ae3db24a DV |
2979 | continue; |
2980 | ||
8fe301ad | 2981 | return reg; |
ae3db24a DV |
2982 | } |
2983 | ||
8fe301ad | 2984 | return NULL; |
ae3db24a DV |
2985 | } |
2986 | ||
de151cf6 | 2987 | /** |
9a5a53b3 | 2988 | * i915_gem_object_get_fence - set up fencing for an object |
de151cf6 JB |
2989 | * @obj: object to map through a fence reg |
2990 | * | |
2991 | * When mapping objects through the GTT, userspace wants to be able to write | |
2992 | * to them without having to worry about swizzling if the object is tiled. | |
de151cf6 JB |
2993 | * This function walks the fence regs looking for a free one for @obj, |
2994 | * stealing one if it can't find any. | |
2995 | * | |
2996 | * It then sets up the reg based on the object's properties: address, pitch | |
2997 | * and tiling format. | |
9a5a53b3 CW |
2998 | * |
2999 | * For an untiled surface, this removes any existing fence. | |
de151cf6 | 3000 | */ |
8c4b8c3f | 3001 | int |
06d98131 | 3002 | i915_gem_object_get_fence(struct drm_i915_gem_object *obj) |
de151cf6 | 3003 | { |
05394f39 | 3004 | struct drm_device *dev = obj->base.dev; |
79e53945 | 3005 | struct drm_i915_private *dev_priv = dev->dev_private; |
14415745 | 3006 | bool enable = obj->tiling_mode != I915_TILING_NONE; |
d9e86c0e | 3007 | struct drm_i915_fence_reg *reg; |
ae3db24a | 3008 | int ret; |
de151cf6 | 3009 | |
14415745 CW |
3010 | /* Have we updated the tiling parameters upon the object and so |
3011 | * will need to serialise the write to the associated fence register? | |
3012 | */ | |
5d82e3e6 | 3013 | if (obj->fence_dirty) { |
d0a57789 | 3014 | ret = i915_gem_object_wait_fence(obj); |
14415745 CW |
3015 | if (ret) |
3016 | return ret; | |
3017 | } | |
9a5a53b3 | 3018 | |
d9e86c0e | 3019 | /* Just update our place in the LRU if our fence is getting reused. */ |
05394f39 CW |
3020 | if (obj->fence_reg != I915_FENCE_REG_NONE) { |
3021 | reg = &dev_priv->fence_regs[obj->fence_reg]; | |
5d82e3e6 | 3022 | if (!obj->fence_dirty) { |
14415745 CW |
3023 | list_move_tail(®->lru_list, |
3024 | &dev_priv->mm.fence_list); | |
3025 | return 0; | |
3026 | } | |
3027 | } else if (enable) { | |
3028 | reg = i915_find_fence_reg(dev); | |
3029 | if (reg == NULL) | |
3030 | return -EDEADLK; | |
d9e86c0e | 3031 | |
14415745 CW |
3032 | if (reg->obj) { |
3033 | struct drm_i915_gem_object *old = reg->obj; | |
3034 | ||
d0a57789 | 3035 | ret = i915_gem_object_wait_fence(old); |
29c5a587 CW |
3036 | if (ret) |
3037 | return ret; | |
3038 | ||
14415745 | 3039 | i915_gem_object_fence_lost(old); |
29c5a587 | 3040 | } |
14415745 | 3041 | } else |
a09ba7fa | 3042 | return 0; |
a09ba7fa | 3043 | |
14415745 | 3044 | i915_gem_object_update_fence(obj, reg, enable); |
14415745 | 3045 | |
9ce079e4 | 3046 | return 0; |
de151cf6 JB |
3047 | } |
3048 | ||
42d6ab48 CW |
3049 | static bool i915_gem_valid_gtt_space(struct drm_device *dev, |
3050 | struct drm_mm_node *gtt_space, | |
3051 | unsigned long cache_level) | |
3052 | { | |
3053 | struct drm_mm_node *other; | |
3054 | ||
3055 | /* On non-LLC machines we have to be careful when putting differing | |
3056 | * types of snoopable memory together to avoid the prefetcher | |
4239ca77 | 3057 | * crossing memory domains and dying. |
42d6ab48 CW |
3058 | */ |
3059 | if (HAS_LLC(dev)) | |
3060 | return true; | |
3061 | ||
c6cfb325 | 3062 | if (!drm_mm_node_allocated(gtt_space)) |
42d6ab48 CW |
3063 | return true; |
3064 | ||
3065 | if (list_empty(>t_space->node_list)) | |
3066 | return true; | |
3067 | ||
3068 | other = list_entry(gtt_space->node_list.prev, struct drm_mm_node, node_list); | |
3069 | if (other->allocated && !other->hole_follows && other->color != cache_level) | |
3070 | return false; | |
3071 | ||
3072 | other = list_entry(gtt_space->node_list.next, struct drm_mm_node, node_list); | |
3073 | if (other->allocated && !gtt_space->hole_follows && other->color != cache_level) | |
3074 | return false; | |
3075 | ||
3076 | return true; | |
3077 | } | |
3078 | ||
3079 | static void i915_gem_verify_gtt(struct drm_device *dev) | |
3080 | { | |
3081 | #if WATCH_GTT | |
3082 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3083 | struct drm_i915_gem_object *obj; | |
3084 | int err = 0; | |
3085 | ||
35c20a60 | 3086 | list_for_each_entry(obj, &dev_priv->mm.gtt_list, global_list) { |
42d6ab48 CW |
3087 | if (obj->gtt_space == NULL) { |
3088 | printk(KERN_ERR "object found on GTT list with no space reserved\n"); | |
3089 | err++; | |
3090 | continue; | |
3091 | } | |
3092 | ||
3093 | if (obj->cache_level != obj->gtt_space->color) { | |
3094 | printk(KERN_ERR "object reserved space [%08lx, %08lx] with wrong color, cache_level=%x, color=%lx\n", | |
f343c5f6 BW |
3095 | i915_gem_obj_ggtt_offset(obj), |
3096 | i915_gem_obj_ggtt_offset(obj) + i915_gem_obj_ggtt_size(obj), | |
42d6ab48 CW |
3097 | obj->cache_level, |
3098 | obj->gtt_space->color); | |
3099 | err++; | |
3100 | continue; | |
3101 | } | |
3102 | ||
3103 | if (!i915_gem_valid_gtt_space(dev, | |
3104 | obj->gtt_space, | |
3105 | obj->cache_level)) { | |
3106 | printk(KERN_ERR "invalid GTT space found at [%08lx, %08lx] - color=%x\n", | |
f343c5f6 BW |
3107 | i915_gem_obj_ggtt_offset(obj), |
3108 | i915_gem_obj_ggtt_offset(obj) + i915_gem_obj_ggtt_size(obj), | |
42d6ab48 CW |
3109 | obj->cache_level); |
3110 | err++; | |
3111 | continue; | |
3112 | } | |
3113 | } | |
3114 | ||
3115 | WARN_ON(err); | |
3116 | #endif | |
3117 | } | |
3118 | ||
673a394b EA |
3119 | /** |
3120 | * Finds free space in the GTT aperture and binds the object there. | |
3121 | */ | |
3122 | static int | |
07fe0b12 BW |
3123 | i915_gem_object_bind_to_vm(struct drm_i915_gem_object *obj, |
3124 | struct i915_address_space *vm, | |
3125 | unsigned alignment, | |
3126 | bool map_and_fenceable, | |
3127 | bool nonblocking) | |
673a394b | 3128 | { |
05394f39 | 3129 | struct drm_device *dev = obj->base.dev; |
673a394b | 3130 | drm_i915_private_t *dev_priv = dev->dev_private; |
5e783301 | 3131 | u32 size, fence_size, fence_alignment, unfenced_alignment; |
07fe0b12 BW |
3132 | size_t gtt_max = |
3133 | map_and_fenceable ? dev_priv->gtt.mappable_end : vm->total; | |
2f633156 | 3134 | struct i915_vma *vma; |
07f73f69 | 3135 | int ret; |
673a394b | 3136 | |
e28f8711 CW |
3137 | fence_size = i915_gem_get_gtt_size(dev, |
3138 | obj->base.size, | |
3139 | obj->tiling_mode); | |
3140 | fence_alignment = i915_gem_get_gtt_alignment(dev, | |
3141 | obj->base.size, | |
d865110c | 3142 | obj->tiling_mode, true); |
e28f8711 | 3143 | unfenced_alignment = |
d865110c | 3144 | i915_gem_get_gtt_alignment(dev, |
e28f8711 | 3145 | obj->base.size, |
d865110c | 3146 | obj->tiling_mode, false); |
a00b10c3 | 3147 | |
673a394b | 3148 | if (alignment == 0) |
5e783301 DV |
3149 | alignment = map_and_fenceable ? fence_alignment : |
3150 | unfenced_alignment; | |
75e9e915 | 3151 | if (map_and_fenceable && alignment & (fence_alignment - 1)) { |
673a394b EA |
3152 | DRM_ERROR("Invalid object alignment requested %u\n", alignment); |
3153 | return -EINVAL; | |
3154 | } | |
3155 | ||
05394f39 | 3156 | size = map_and_fenceable ? fence_size : obj->base.size; |
a00b10c3 | 3157 | |
654fc607 CW |
3158 | /* If the object is bigger than the entire aperture, reject it early |
3159 | * before evicting everything in a vain attempt to find space. | |
3160 | */ | |
0a9ae0d7 | 3161 | if (obj->base.size > gtt_max) { |
3765f304 | 3162 | DRM_ERROR("Attempting to bind an object larger than the aperture: object=%zd > %s aperture=%zu\n", |
a36689cb CW |
3163 | obj->base.size, |
3164 | map_and_fenceable ? "mappable" : "total", | |
0a9ae0d7 | 3165 | gtt_max); |
654fc607 CW |
3166 | return -E2BIG; |
3167 | } | |
3168 | ||
37e680a1 | 3169 | ret = i915_gem_object_get_pages(obj); |
6c085a72 CW |
3170 | if (ret) |
3171 | return ret; | |
3172 | ||
fbdda6fb CW |
3173 | i915_gem_object_pin_pages(obj); |
3174 | ||
07fe0b12 | 3175 | BUG_ON(!i915_is_ggtt(vm)); |
07fe0b12 | 3176 | |
accfef2e | 3177 | vma = i915_gem_obj_lookup_or_create_vma(obj, vm); |
db473b36 | 3178 | if (IS_ERR(vma)) { |
bc6bc15b DV |
3179 | ret = PTR_ERR(vma); |
3180 | goto err_unpin; | |
2f633156 BW |
3181 | } |
3182 | ||
accfef2e BW |
3183 | /* For now we only ever use 1 vma per object */ |
3184 | WARN_ON(!list_is_singular(&obj->vma_list)); | |
3185 | ||
0a9ae0d7 | 3186 | search_free: |
07fe0b12 | 3187 | ret = drm_mm_insert_node_in_range_generic(&vm->mm, &vma->node, |
0a9ae0d7 | 3188 | size, alignment, |
31e5d7c6 DH |
3189 | obj->cache_level, 0, gtt_max, |
3190 | DRM_MM_SEARCH_DEFAULT); | |
dc9dd7a2 | 3191 | if (ret) { |
f6cd1f15 | 3192 | ret = i915_gem_evict_something(dev, vm, size, alignment, |
42d6ab48 | 3193 | obj->cache_level, |
86a1ee26 CW |
3194 | map_and_fenceable, |
3195 | nonblocking); | |
dc9dd7a2 CW |
3196 | if (ret == 0) |
3197 | goto search_free; | |
9731129c | 3198 | |
bc6bc15b | 3199 | goto err_free_vma; |
673a394b | 3200 | } |
2f633156 | 3201 | if (WARN_ON(!i915_gem_valid_gtt_space(dev, &vma->node, |
c6cfb325 | 3202 | obj->cache_level))) { |
2f633156 | 3203 | ret = -EINVAL; |
bc6bc15b | 3204 | goto err_remove_node; |
673a394b EA |
3205 | } |
3206 | ||
74163907 | 3207 | ret = i915_gem_gtt_prepare_object(obj); |
2f633156 | 3208 | if (ret) |
bc6bc15b | 3209 | goto err_remove_node; |
673a394b | 3210 | |
35c20a60 | 3211 | list_move_tail(&obj->global_list, &dev_priv->mm.bound_list); |
ca191b13 | 3212 | list_add_tail(&vma->mm_list, &vm->inactive_list); |
bf1a1092 | 3213 | |
4bd561b3 BW |
3214 | if (i915_is_ggtt(vm)) { |
3215 | bool mappable, fenceable; | |
a00b10c3 | 3216 | |
49987099 DV |
3217 | fenceable = (vma->node.size == fence_size && |
3218 | (vma->node.start & (fence_alignment - 1)) == 0); | |
4bd561b3 | 3219 | |
49987099 DV |
3220 | mappable = (vma->node.start + obj->base.size <= |
3221 | dev_priv->gtt.mappable_end); | |
a00b10c3 | 3222 | |
5cacaac7 | 3223 | obj->map_and_fenceable = mappable && fenceable; |
4bd561b3 | 3224 | } |
75e9e915 | 3225 | |
7ace7ef2 | 3226 | WARN_ON(map_and_fenceable && !obj->map_and_fenceable); |
75e9e915 | 3227 | |
07fe0b12 | 3228 | trace_i915_vma_bind(vma, map_and_fenceable); |
42d6ab48 | 3229 | i915_gem_verify_gtt(dev); |
673a394b | 3230 | return 0; |
2f633156 | 3231 | |
bc6bc15b | 3232 | err_remove_node: |
6286ef9b | 3233 | drm_mm_remove_node(&vma->node); |
bc6bc15b | 3234 | err_free_vma: |
2f633156 | 3235 | i915_gem_vma_destroy(vma); |
bc6bc15b | 3236 | err_unpin: |
2f633156 | 3237 | i915_gem_object_unpin_pages(obj); |
2f633156 | 3238 | return ret; |
673a394b EA |
3239 | } |
3240 | ||
000433b6 | 3241 | bool |
2c22569b CW |
3242 | i915_gem_clflush_object(struct drm_i915_gem_object *obj, |
3243 | bool force) | |
673a394b | 3244 | { |
673a394b EA |
3245 | /* If we don't have a page list set up, then we're not pinned |
3246 | * to GPU, and we can ignore the cache flush because it'll happen | |
3247 | * again at bind time. | |
3248 | */ | |
05394f39 | 3249 | if (obj->pages == NULL) |
000433b6 | 3250 | return false; |
673a394b | 3251 | |
769ce464 ID |
3252 | /* |
3253 | * Stolen memory is always coherent with the GPU as it is explicitly | |
3254 | * marked as wc by the system, or the system is cache-coherent. | |
3255 | */ | |
3256 | if (obj->stolen) | |
000433b6 | 3257 | return false; |
769ce464 | 3258 | |
9c23f7fc CW |
3259 | /* If the GPU is snooping the contents of the CPU cache, |
3260 | * we do not need to manually clear the CPU cache lines. However, | |
3261 | * the caches are only snooped when the render cache is | |
3262 | * flushed/invalidated. As we always have to emit invalidations | |
3263 | * and flushes when moving into and out of the RENDER domain, correct | |
3264 | * snooping behaviour occurs naturally as the result of our domain | |
3265 | * tracking. | |
3266 | */ | |
2c22569b | 3267 | if (!force && cpu_cache_is_coherent(obj->base.dev, obj->cache_level)) |
000433b6 | 3268 | return false; |
9c23f7fc | 3269 | |
1c5d22f7 | 3270 | trace_i915_gem_object_clflush(obj); |
9da3da66 | 3271 | drm_clflush_sg(obj->pages); |
000433b6 CW |
3272 | |
3273 | return true; | |
e47c68e9 EA |
3274 | } |
3275 | ||
3276 | /** Flushes the GTT write domain for the object if it's dirty. */ | |
3277 | static void | |
05394f39 | 3278 | i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj) |
e47c68e9 | 3279 | { |
1c5d22f7 CW |
3280 | uint32_t old_write_domain; |
3281 | ||
05394f39 | 3282 | if (obj->base.write_domain != I915_GEM_DOMAIN_GTT) |
e47c68e9 EA |
3283 | return; |
3284 | ||
63256ec5 | 3285 | /* No actual flushing is required for the GTT write domain. Writes |
e47c68e9 EA |
3286 | * to it immediately go to main memory as far as we know, so there's |
3287 | * no chipset flush. It also doesn't land in render cache. | |
63256ec5 CW |
3288 | * |
3289 | * However, we do have to enforce the order so that all writes through | |
3290 | * the GTT land before any writes to the device, such as updates to | |
3291 | * the GATT itself. | |
e47c68e9 | 3292 | */ |
63256ec5 CW |
3293 | wmb(); |
3294 | ||
05394f39 CW |
3295 | old_write_domain = obj->base.write_domain; |
3296 | obj->base.write_domain = 0; | |
1c5d22f7 CW |
3297 | |
3298 | trace_i915_gem_object_change_domain(obj, | |
05394f39 | 3299 | obj->base.read_domains, |
1c5d22f7 | 3300 | old_write_domain); |
e47c68e9 EA |
3301 | } |
3302 | ||
3303 | /** Flushes the CPU write domain for the object if it's dirty. */ | |
3304 | static void | |
2c22569b CW |
3305 | i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj, |
3306 | bool force) | |
e47c68e9 | 3307 | { |
1c5d22f7 | 3308 | uint32_t old_write_domain; |
e47c68e9 | 3309 | |
05394f39 | 3310 | if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) |
e47c68e9 EA |
3311 | return; |
3312 | ||
000433b6 CW |
3313 | if (i915_gem_clflush_object(obj, force)) |
3314 | i915_gem_chipset_flush(obj->base.dev); | |
3315 | ||
05394f39 CW |
3316 | old_write_domain = obj->base.write_domain; |
3317 | obj->base.write_domain = 0; | |
1c5d22f7 CW |
3318 | |
3319 | trace_i915_gem_object_change_domain(obj, | |
05394f39 | 3320 | obj->base.read_domains, |
1c5d22f7 | 3321 | old_write_domain); |
e47c68e9 EA |
3322 | } |
3323 | ||
2ef7eeaa EA |
3324 | /** |
3325 | * Moves a single object to the GTT read, and possibly write domain. | |
3326 | * | |
3327 | * This function returns when the move is complete, including waiting on | |
3328 | * flushes to occur. | |
3329 | */ | |
79e53945 | 3330 | int |
2021746e | 3331 | i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write) |
2ef7eeaa | 3332 | { |
8325a09d | 3333 | drm_i915_private_t *dev_priv = obj->base.dev->dev_private; |
1c5d22f7 | 3334 | uint32_t old_write_domain, old_read_domains; |
e47c68e9 | 3335 | int ret; |
2ef7eeaa | 3336 | |
02354392 | 3337 | /* Not valid to be called on unbound objects. */ |
9843877d | 3338 | if (!i915_gem_obj_bound_any(obj)) |
02354392 EA |
3339 | return -EINVAL; |
3340 | ||
8d7e3de1 CW |
3341 | if (obj->base.write_domain == I915_GEM_DOMAIN_GTT) |
3342 | return 0; | |
3343 | ||
0201f1ec | 3344 | ret = i915_gem_object_wait_rendering(obj, !write); |
88241785 CW |
3345 | if (ret) |
3346 | return ret; | |
3347 | ||
2c22569b | 3348 | i915_gem_object_flush_cpu_write_domain(obj, false); |
1c5d22f7 | 3349 | |
d0a57789 CW |
3350 | /* Serialise direct access to this object with the barriers for |
3351 | * coherent writes from the GPU, by effectively invalidating the | |
3352 | * GTT domain upon first access. | |
3353 | */ | |
3354 | if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0) | |
3355 | mb(); | |
3356 | ||
05394f39 CW |
3357 | old_write_domain = obj->base.write_domain; |
3358 | old_read_domains = obj->base.read_domains; | |
1c5d22f7 | 3359 | |
e47c68e9 EA |
3360 | /* It should now be out of any other write domains, and we can update |
3361 | * the domain values for our changes. | |
3362 | */ | |
05394f39 CW |
3363 | BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) != 0); |
3364 | obj->base.read_domains |= I915_GEM_DOMAIN_GTT; | |
e47c68e9 | 3365 | if (write) { |
05394f39 CW |
3366 | obj->base.read_domains = I915_GEM_DOMAIN_GTT; |
3367 | obj->base.write_domain = I915_GEM_DOMAIN_GTT; | |
3368 | obj->dirty = 1; | |
2ef7eeaa EA |
3369 | } |
3370 | ||
1c5d22f7 CW |
3371 | trace_i915_gem_object_change_domain(obj, |
3372 | old_read_domains, | |
3373 | old_write_domain); | |
3374 | ||
8325a09d | 3375 | /* And bump the LRU for this access */ |
ca191b13 BW |
3376 | if (i915_gem_object_is_inactive(obj)) { |
3377 | struct i915_vma *vma = i915_gem_obj_to_vma(obj, | |
3378 | &dev_priv->gtt.base); | |
3379 | if (vma) | |
3380 | list_move_tail(&vma->mm_list, | |
3381 | &dev_priv->gtt.base.inactive_list); | |
3382 | ||
3383 | } | |
8325a09d | 3384 | |
e47c68e9 EA |
3385 | return 0; |
3386 | } | |
3387 | ||
e4ffd173 CW |
3388 | int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj, |
3389 | enum i915_cache_level cache_level) | |
3390 | { | |
7bddb01f DV |
3391 | struct drm_device *dev = obj->base.dev; |
3392 | drm_i915_private_t *dev_priv = dev->dev_private; | |
3089c6f2 | 3393 | struct i915_vma *vma; |
e4ffd173 CW |
3394 | int ret; |
3395 | ||
3396 | if (obj->cache_level == cache_level) | |
3397 | return 0; | |
3398 | ||
3399 | if (obj->pin_count) { | |
3400 | DRM_DEBUG("can not change the cache level of pinned objects\n"); | |
3401 | return -EBUSY; | |
3402 | } | |
3403 | ||
3089c6f2 BW |
3404 | list_for_each_entry(vma, &obj->vma_list, vma_link) { |
3405 | if (!i915_gem_valid_gtt_space(dev, &vma->node, cache_level)) { | |
07fe0b12 | 3406 | ret = i915_vma_unbind(vma); |
3089c6f2 BW |
3407 | if (ret) |
3408 | return ret; | |
3409 | ||
3410 | break; | |
3411 | } | |
42d6ab48 CW |
3412 | } |
3413 | ||
3089c6f2 | 3414 | if (i915_gem_obj_bound_any(obj)) { |
e4ffd173 CW |
3415 | ret = i915_gem_object_finish_gpu(obj); |
3416 | if (ret) | |
3417 | return ret; | |
3418 | ||
3419 | i915_gem_object_finish_gtt(obj); | |
3420 | ||
3421 | /* Before SandyBridge, you could not use tiling or fence | |
3422 | * registers with snooped memory, so relinquish any fences | |
3423 | * currently pointing to our region in the aperture. | |
3424 | */ | |
42d6ab48 | 3425 | if (INTEL_INFO(dev)->gen < 6) { |
e4ffd173 CW |
3426 | ret = i915_gem_object_put_fence(obj); |
3427 | if (ret) | |
3428 | return ret; | |
3429 | } | |
3430 | ||
74898d7e DV |
3431 | if (obj->has_global_gtt_mapping) |
3432 | i915_gem_gtt_bind_object(obj, cache_level); | |
7bddb01f DV |
3433 | if (obj->has_aliasing_ppgtt_mapping) |
3434 | i915_ppgtt_bind_object(dev_priv->mm.aliasing_ppgtt, | |
3435 | obj, cache_level); | |
e4ffd173 CW |
3436 | } |
3437 | ||
2c22569b CW |
3438 | list_for_each_entry(vma, &obj->vma_list, vma_link) |
3439 | vma->node.color = cache_level; | |
3440 | obj->cache_level = cache_level; | |
3441 | ||
3442 | if (cpu_write_needs_clflush(obj)) { | |
e4ffd173 CW |
3443 | u32 old_read_domains, old_write_domain; |
3444 | ||
3445 | /* If we're coming from LLC cached, then we haven't | |
3446 | * actually been tracking whether the data is in the | |
3447 | * CPU cache or not, since we only allow one bit set | |
3448 | * in obj->write_domain and have been skipping the clflushes. | |
3449 | * Just set it to the CPU cache for now. | |
3450 | */ | |
3451 | WARN_ON(obj->base.write_domain & ~I915_GEM_DOMAIN_CPU); | |
e4ffd173 CW |
3452 | |
3453 | old_read_domains = obj->base.read_domains; | |
3454 | old_write_domain = obj->base.write_domain; | |
3455 | ||
3456 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; | |
3457 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; | |
3458 | ||
3459 | trace_i915_gem_object_change_domain(obj, | |
3460 | old_read_domains, | |
3461 | old_write_domain); | |
3462 | } | |
3463 | ||
42d6ab48 | 3464 | i915_gem_verify_gtt(dev); |
e4ffd173 CW |
3465 | return 0; |
3466 | } | |
3467 | ||
199adf40 BW |
3468 | int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data, |
3469 | struct drm_file *file) | |
e6994aee | 3470 | { |
199adf40 | 3471 | struct drm_i915_gem_caching *args = data; |
e6994aee CW |
3472 | struct drm_i915_gem_object *obj; |
3473 | int ret; | |
3474 | ||
3475 | ret = i915_mutex_lock_interruptible(dev); | |
3476 | if (ret) | |
3477 | return ret; | |
3478 | ||
3479 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); | |
3480 | if (&obj->base == NULL) { | |
3481 | ret = -ENOENT; | |
3482 | goto unlock; | |
3483 | } | |
3484 | ||
651d794f CW |
3485 | switch (obj->cache_level) { |
3486 | case I915_CACHE_LLC: | |
3487 | case I915_CACHE_L3_LLC: | |
3488 | args->caching = I915_CACHING_CACHED; | |
3489 | break; | |
3490 | ||
4257d3ba CW |
3491 | case I915_CACHE_WT: |
3492 | args->caching = I915_CACHING_DISPLAY; | |
3493 | break; | |
3494 | ||
651d794f CW |
3495 | default: |
3496 | args->caching = I915_CACHING_NONE; | |
3497 | break; | |
3498 | } | |
e6994aee CW |
3499 | |
3500 | drm_gem_object_unreference(&obj->base); | |
3501 | unlock: | |
3502 | mutex_unlock(&dev->struct_mutex); | |
3503 | return ret; | |
3504 | } | |
3505 | ||
199adf40 BW |
3506 | int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data, |
3507 | struct drm_file *file) | |
e6994aee | 3508 | { |
199adf40 | 3509 | struct drm_i915_gem_caching *args = data; |
e6994aee CW |
3510 | struct drm_i915_gem_object *obj; |
3511 | enum i915_cache_level level; | |
3512 | int ret; | |
3513 | ||
199adf40 BW |
3514 | switch (args->caching) { |
3515 | case I915_CACHING_NONE: | |
e6994aee CW |
3516 | level = I915_CACHE_NONE; |
3517 | break; | |
199adf40 | 3518 | case I915_CACHING_CACHED: |
e6994aee CW |
3519 | level = I915_CACHE_LLC; |
3520 | break; | |
4257d3ba CW |
3521 | case I915_CACHING_DISPLAY: |
3522 | level = HAS_WT(dev) ? I915_CACHE_WT : I915_CACHE_NONE; | |
3523 | break; | |
e6994aee CW |
3524 | default: |
3525 | return -EINVAL; | |
3526 | } | |
3527 | ||
3bc2913e BW |
3528 | ret = i915_mutex_lock_interruptible(dev); |
3529 | if (ret) | |
3530 | return ret; | |
3531 | ||
e6994aee CW |
3532 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
3533 | if (&obj->base == NULL) { | |
3534 | ret = -ENOENT; | |
3535 | goto unlock; | |
3536 | } | |
3537 | ||
3538 | ret = i915_gem_object_set_cache_level(obj, level); | |
3539 | ||
3540 | drm_gem_object_unreference(&obj->base); | |
3541 | unlock: | |
3542 | mutex_unlock(&dev->struct_mutex); | |
3543 | return ret; | |
3544 | } | |
3545 | ||
cc98b413 CW |
3546 | static bool is_pin_display(struct drm_i915_gem_object *obj) |
3547 | { | |
3548 | /* There are 3 sources that pin objects: | |
3549 | * 1. The display engine (scanouts, sprites, cursors); | |
3550 | * 2. Reservations for execbuffer; | |
3551 | * 3. The user. | |
3552 | * | |
3553 | * We can ignore reservations as we hold the struct_mutex and | |
3554 | * are only called outside of the reservation path. The user | |
3555 | * can only increment pin_count once, and so if after | |
3556 | * subtracting the potential reference by the user, any pin_count | |
3557 | * remains, it must be due to another use by the display engine. | |
3558 | */ | |
3559 | return obj->pin_count - !!obj->user_pin_count; | |
3560 | } | |
3561 | ||
b9241ea3 | 3562 | /* |
2da3b9b9 CW |
3563 | * Prepare buffer for display plane (scanout, cursors, etc). |
3564 | * Can be called from an uninterruptible phase (modesetting) and allows | |
3565 | * any flushes to be pipelined (for pageflips). | |
b9241ea3 ZW |
3566 | */ |
3567 | int | |
2da3b9b9 CW |
3568 | i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj, |
3569 | u32 alignment, | |
919926ae | 3570 | struct intel_ring_buffer *pipelined) |
b9241ea3 | 3571 | { |
2da3b9b9 | 3572 | u32 old_read_domains, old_write_domain; |
b9241ea3 ZW |
3573 | int ret; |
3574 | ||
0be73284 | 3575 | if (pipelined != obj->ring) { |
2911a35b BW |
3576 | ret = i915_gem_object_sync(obj, pipelined); |
3577 | if (ret) | |
b9241ea3 ZW |
3578 | return ret; |
3579 | } | |
3580 | ||
cc98b413 CW |
3581 | /* Mark the pin_display early so that we account for the |
3582 | * display coherency whilst setting up the cache domains. | |
3583 | */ | |
3584 | obj->pin_display = true; | |
3585 | ||
a7ef0640 EA |
3586 | /* The display engine is not coherent with the LLC cache on gen6. As |
3587 | * a result, we make sure that the pinning that is about to occur is | |
3588 | * done with uncached PTEs. This is lowest common denominator for all | |
3589 | * chipsets. | |
3590 | * | |
3591 | * However for gen6+, we could do better by using the GFDT bit instead | |
3592 | * of uncaching, which would allow us to flush all the LLC-cached data | |
3593 | * with that bit in the PTE to main memory with just one PIPE_CONTROL. | |
3594 | */ | |
651d794f CW |
3595 | ret = i915_gem_object_set_cache_level(obj, |
3596 | HAS_WT(obj->base.dev) ? I915_CACHE_WT : I915_CACHE_NONE); | |
a7ef0640 | 3597 | if (ret) |
cc98b413 | 3598 | goto err_unpin_display; |
a7ef0640 | 3599 | |
2da3b9b9 CW |
3600 | /* As the user may map the buffer once pinned in the display plane |
3601 | * (e.g. libkms for the bootup splash), we have to ensure that we | |
3602 | * always use map_and_fenceable for all scanout buffers. | |
3603 | */ | |
c37e2204 | 3604 | ret = i915_gem_obj_ggtt_pin(obj, alignment, true, false); |
2da3b9b9 | 3605 | if (ret) |
cc98b413 | 3606 | goto err_unpin_display; |
2da3b9b9 | 3607 | |
2c22569b | 3608 | i915_gem_object_flush_cpu_write_domain(obj, true); |
b118c1e3 | 3609 | |
2da3b9b9 | 3610 | old_write_domain = obj->base.write_domain; |
05394f39 | 3611 | old_read_domains = obj->base.read_domains; |
2da3b9b9 CW |
3612 | |
3613 | /* It should now be out of any other write domains, and we can update | |
3614 | * the domain values for our changes. | |
3615 | */ | |
e5f1d962 | 3616 | obj->base.write_domain = 0; |
05394f39 | 3617 | obj->base.read_domains |= I915_GEM_DOMAIN_GTT; |
b9241ea3 ZW |
3618 | |
3619 | trace_i915_gem_object_change_domain(obj, | |
3620 | old_read_domains, | |
2da3b9b9 | 3621 | old_write_domain); |
b9241ea3 ZW |
3622 | |
3623 | return 0; | |
cc98b413 CW |
3624 | |
3625 | err_unpin_display: | |
3626 | obj->pin_display = is_pin_display(obj); | |
3627 | return ret; | |
3628 | } | |
3629 | ||
3630 | void | |
3631 | i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object *obj) | |
3632 | { | |
3633 | i915_gem_object_unpin(obj); | |
3634 | obj->pin_display = is_pin_display(obj); | |
b9241ea3 ZW |
3635 | } |
3636 | ||
85345517 | 3637 | int |
a8198eea | 3638 | i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj) |
85345517 | 3639 | { |
88241785 CW |
3640 | int ret; |
3641 | ||
a8198eea | 3642 | if ((obj->base.read_domains & I915_GEM_GPU_DOMAINS) == 0) |
85345517 CW |
3643 | return 0; |
3644 | ||
0201f1ec | 3645 | ret = i915_gem_object_wait_rendering(obj, false); |
c501ae7f CW |
3646 | if (ret) |
3647 | return ret; | |
3648 | ||
a8198eea CW |
3649 | /* Ensure that we invalidate the GPU's caches and TLBs. */ |
3650 | obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS; | |
c501ae7f | 3651 | return 0; |
85345517 CW |
3652 | } |
3653 | ||
e47c68e9 EA |
3654 | /** |
3655 | * Moves a single object to the CPU read, and possibly write domain. | |
3656 | * | |
3657 | * This function returns when the move is complete, including waiting on | |
3658 | * flushes to occur. | |
3659 | */ | |
dabdfe02 | 3660 | int |
919926ae | 3661 | i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write) |
e47c68e9 | 3662 | { |
1c5d22f7 | 3663 | uint32_t old_write_domain, old_read_domains; |
e47c68e9 EA |
3664 | int ret; |
3665 | ||
8d7e3de1 CW |
3666 | if (obj->base.write_domain == I915_GEM_DOMAIN_CPU) |
3667 | return 0; | |
3668 | ||
0201f1ec | 3669 | ret = i915_gem_object_wait_rendering(obj, !write); |
88241785 CW |
3670 | if (ret) |
3671 | return ret; | |
3672 | ||
e47c68e9 | 3673 | i915_gem_object_flush_gtt_write_domain(obj); |
2ef7eeaa | 3674 | |
05394f39 CW |
3675 | old_write_domain = obj->base.write_domain; |
3676 | old_read_domains = obj->base.read_domains; | |
1c5d22f7 | 3677 | |
e47c68e9 | 3678 | /* Flush the CPU cache if it's still invalid. */ |
05394f39 | 3679 | if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) { |
2c22569b | 3680 | i915_gem_clflush_object(obj, false); |
2ef7eeaa | 3681 | |
05394f39 | 3682 | obj->base.read_domains |= I915_GEM_DOMAIN_CPU; |
2ef7eeaa EA |
3683 | } |
3684 | ||
3685 | /* It should now be out of any other write domains, and we can update | |
3686 | * the domain values for our changes. | |
3687 | */ | |
05394f39 | 3688 | BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) != 0); |
e47c68e9 EA |
3689 | |
3690 | /* If we're writing through the CPU, then the GPU read domains will | |
3691 | * need to be invalidated at next use. | |
3692 | */ | |
3693 | if (write) { | |
05394f39 CW |
3694 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; |
3695 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; | |
e47c68e9 | 3696 | } |
2ef7eeaa | 3697 | |
1c5d22f7 CW |
3698 | trace_i915_gem_object_change_domain(obj, |
3699 | old_read_domains, | |
3700 | old_write_domain); | |
3701 | ||
2ef7eeaa EA |
3702 | return 0; |
3703 | } | |
3704 | ||
673a394b EA |
3705 | /* Throttle our rendering by waiting until the ring has completed our requests |
3706 | * emitted over 20 msec ago. | |
3707 | * | |
b962442e EA |
3708 | * Note that if we were to use the current jiffies each time around the loop, |
3709 | * we wouldn't escape the function with any frames outstanding if the time to | |
3710 | * render a frame was over 20ms. | |
3711 | * | |
673a394b EA |
3712 | * This should get us reasonable parallelism between CPU and GPU but also |
3713 | * relatively low latency when blocking on a particular request to finish. | |
3714 | */ | |
40a5f0de | 3715 | static int |
f787a5f5 | 3716 | i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file) |
40a5f0de | 3717 | { |
f787a5f5 CW |
3718 | struct drm_i915_private *dev_priv = dev->dev_private; |
3719 | struct drm_i915_file_private *file_priv = file->driver_priv; | |
b962442e | 3720 | unsigned long recent_enough = jiffies - msecs_to_jiffies(20); |
f787a5f5 CW |
3721 | struct drm_i915_gem_request *request; |
3722 | struct intel_ring_buffer *ring = NULL; | |
f69061be | 3723 | unsigned reset_counter; |
f787a5f5 CW |
3724 | u32 seqno = 0; |
3725 | int ret; | |
93533c29 | 3726 | |
308887aa DV |
3727 | ret = i915_gem_wait_for_error(&dev_priv->gpu_error); |
3728 | if (ret) | |
3729 | return ret; | |
3730 | ||
3731 | ret = i915_gem_check_wedge(&dev_priv->gpu_error, false); | |
3732 | if (ret) | |
3733 | return ret; | |
e110e8d6 | 3734 | |
1c25595f | 3735 | spin_lock(&file_priv->mm.lock); |
f787a5f5 | 3736 | list_for_each_entry(request, &file_priv->mm.request_list, client_list) { |
b962442e EA |
3737 | if (time_after_eq(request->emitted_jiffies, recent_enough)) |
3738 | break; | |
40a5f0de | 3739 | |
f787a5f5 CW |
3740 | ring = request->ring; |
3741 | seqno = request->seqno; | |
b962442e | 3742 | } |
f69061be | 3743 | reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter); |
1c25595f | 3744 | spin_unlock(&file_priv->mm.lock); |
40a5f0de | 3745 | |
f787a5f5 CW |
3746 | if (seqno == 0) |
3747 | return 0; | |
2bc43b5c | 3748 | |
f69061be | 3749 | ret = __wait_seqno(ring, seqno, reset_counter, true, NULL); |
f787a5f5 CW |
3750 | if (ret == 0) |
3751 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, 0); | |
40a5f0de EA |
3752 | |
3753 | return ret; | |
3754 | } | |
3755 | ||
673a394b | 3756 | int |
05394f39 | 3757 | i915_gem_object_pin(struct drm_i915_gem_object *obj, |
c37e2204 | 3758 | struct i915_address_space *vm, |
05394f39 | 3759 | uint32_t alignment, |
86a1ee26 CW |
3760 | bool map_and_fenceable, |
3761 | bool nonblocking) | |
673a394b | 3762 | { |
07fe0b12 | 3763 | struct i915_vma *vma; |
673a394b EA |
3764 | int ret; |
3765 | ||
7e81a42e CW |
3766 | if (WARN_ON(obj->pin_count == DRM_I915_GEM_OBJECT_MAX_PIN_COUNT)) |
3767 | return -EBUSY; | |
ac0c6b5a | 3768 | |
07fe0b12 BW |
3769 | WARN_ON(map_and_fenceable && !i915_is_ggtt(vm)); |
3770 | ||
3771 | vma = i915_gem_obj_to_vma(obj, vm); | |
3772 | ||
3773 | if (vma) { | |
3774 | if ((alignment && | |
3775 | vma->node.start & (alignment - 1)) || | |
05394f39 CW |
3776 | (map_and_fenceable && !obj->map_and_fenceable)) { |
3777 | WARN(obj->pin_count, | |
ae7d49d8 | 3778 | "bo is already pinned with incorrect alignment:" |
f343c5f6 | 3779 | " offset=%lx, req.alignment=%x, req.map_and_fenceable=%d," |
75e9e915 | 3780 | " obj->map_and_fenceable=%d\n", |
07fe0b12 | 3781 | i915_gem_obj_offset(obj, vm), alignment, |
75e9e915 | 3782 | map_and_fenceable, |
05394f39 | 3783 | obj->map_and_fenceable); |
07fe0b12 | 3784 | ret = i915_vma_unbind(vma); |
ac0c6b5a CW |
3785 | if (ret) |
3786 | return ret; | |
3787 | } | |
3788 | } | |
3789 | ||
07fe0b12 | 3790 | if (!i915_gem_obj_bound(obj, vm)) { |
8742267a CW |
3791 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
3792 | ||
07fe0b12 BW |
3793 | ret = i915_gem_object_bind_to_vm(obj, vm, alignment, |
3794 | map_and_fenceable, | |
3795 | nonblocking); | |
9731129c | 3796 | if (ret) |
673a394b | 3797 | return ret; |
8742267a CW |
3798 | |
3799 | if (!dev_priv->mm.aliasing_ppgtt) | |
3800 | i915_gem_gtt_bind_object(obj, obj->cache_level); | |
22c344e9 | 3801 | } |
76446cac | 3802 | |
74898d7e DV |
3803 | if (!obj->has_global_gtt_mapping && map_and_fenceable) |
3804 | i915_gem_gtt_bind_object(obj, obj->cache_level); | |
3805 | ||
1b50247a | 3806 | obj->pin_count++; |
6299f992 | 3807 | obj->pin_mappable |= map_and_fenceable; |
673a394b EA |
3808 | |
3809 | return 0; | |
3810 | } | |
3811 | ||
3812 | void | |
05394f39 | 3813 | i915_gem_object_unpin(struct drm_i915_gem_object *obj) |
673a394b | 3814 | { |
05394f39 | 3815 | BUG_ON(obj->pin_count == 0); |
9843877d | 3816 | BUG_ON(!i915_gem_obj_bound_any(obj)); |
673a394b | 3817 | |
1b50247a | 3818 | if (--obj->pin_count == 0) |
6299f992 | 3819 | obj->pin_mappable = false; |
673a394b EA |
3820 | } |
3821 | ||
3822 | int | |
3823 | i915_gem_pin_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 3824 | struct drm_file *file) |
673a394b EA |
3825 | { |
3826 | struct drm_i915_gem_pin *args = data; | |
05394f39 | 3827 | struct drm_i915_gem_object *obj; |
673a394b EA |
3828 | int ret; |
3829 | ||
1d7cfea1 CW |
3830 | ret = i915_mutex_lock_interruptible(dev); |
3831 | if (ret) | |
3832 | return ret; | |
673a394b | 3833 | |
05394f39 | 3834 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 3835 | if (&obj->base == NULL) { |
1d7cfea1 CW |
3836 | ret = -ENOENT; |
3837 | goto unlock; | |
673a394b | 3838 | } |
673a394b | 3839 | |
05394f39 | 3840 | if (obj->madv != I915_MADV_WILLNEED) { |
bb6baf76 | 3841 | DRM_ERROR("Attempting to pin a purgeable buffer\n"); |
1d7cfea1 CW |
3842 | ret = -EINVAL; |
3843 | goto out; | |
3ef94daa CW |
3844 | } |
3845 | ||
05394f39 | 3846 | if (obj->pin_filp != NULL && obj->pin_filp != file) { |
79e53945 JB |
3847 | DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n", |
3848 | args->handle); | |
1d7cfea1 CW |
3849 | ret = -EINVAL; |
3850 | goto out; | |
79e53945 JB |
3851 | } |
3852 | ||
93be8788 | 3853 | if (obj->user_pin_count == 0) { |
c37e2204 | 3854 | ret = i915_gem_obj_ggtt_pin(obj, args->alignment, true, false); |
1d7cfea1 CW |
3855 | if (ret) |
3856 | goto out; | |
673a394b EA |
3857 | } |
3858 | ||
93be8788 CW |
3859 | obj->user_pin_count++; |
3860 | obj->pin_filp = file; | |
3861 | ||
f343c5f6 | 3862 | args->offset = i915_gem_obj_ggtt_offset(obj); |
1d7cfea1 | 3863 | out: |
05394f39 | 3864 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 3865 | unlock: |
673a394b | 3866 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 3867 | return ret; |
673a394b EA |
3868 | } |
3869 | ||
3870 | int | |
3871 | i915_gem_unpin_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 3872 | struct drm_file *file) |
673a394b EA |
3873 | { |
3874 | struct drm_i915_gem_pin *args = data; | |
05394f39 | 3875 | struct drm_i915_gem_object *obj; |
76c1dec1 | 3876 | int ret; |
673a394b | 3877 | |
1d7cfea1 CW |
3878 | ret = i915_mutex_lock_interruptible(dev); |
3879 | if (ret) | |
3880 | return ret; | |
673a394b | 3881 | |
05394f39 | 3882 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 3883 | if (&obj->base == NULL) { |
1d7cfea1 CW |
3884 | ret = -ENOENT; |
3885 | goto unlock; | |
673a394b | 3886 | } |
76c1dec1 | 3887 | |
05394f39 | 3888 | if (obj->pin_filp != file) { |
79e53945 JB |
3889 | DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n", |
3890 | args->handle); | |
1d7cfea1 CW |
3891 | ret = -EINVAL; |
3892 | goto out; | |
79e53945 | 3893 | } |
05394f39 CW |
3894 | obj->user_pin_count--; |
3895 | if (obj->user_pin_count == 0) { | |
3896 | obj->pin_filp = NULL; | |
79e53945 JB |
3897 | i915_gem_object_unpin(obj); |
3898 | } | |
673a394b | 3899 | |
1d7cfea1 | 3900 | out: |
05394f39 | 3901 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 3902 | unlock: |
673a394b | 3903 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 3904 | return ret; |
673a394b EA |
3905 | } |
3906 | ||
3907 | int | |
3908 | i915_gem_busy_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 3909 | struct drm_file *file) |
673a394b EA |
3910 | { |
3911 | struct drm_i915_gem_busy *args = data; | |
05394f39 | 3912 | struct drm_i915_gem_object *obj; |
30dbf0c0 CW |
3913 | int ret; |
3914 | ||
76c1dec1 | 3915 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 3916 | if (ret) |
76c1dec1 | 3917 | return ret; |
673a394b | 3918 | |
05394f39 | 3919 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 3920 | if (&obj->base == NULL) { |
1d7cfea1 CW |
3921 | ret = -ENOENT; |
3922 | goto unlock; | |
673a394b | 3923 | } |
d1b851fc | 3924 | |
0be555b6 CW |
3925 | /* Count all active objects as busy, even if they are currently not used |
3926 | * by the gpu. Users of this interface expect objects to eventually | |
3927 | * become non-busy without any further actions, therefore emit any | |
3928 | * necessary flushes here. | |
c4de0a5d | 3929 | */ |
30dfebf3 | 3930 | ret = i915_gem_object_flush_active(obj); |
0be555b6 | 3931 | |
30dfebf3 | 3932 | args->busy = obj->active; |
e9808edd CW |
3933 | if (obj->ring) { |
3934 | BUILD_BUG_ON(I915_NUM_RINGS > 16); | |
3935 | args->busy |= intel_ring_flag(obj->ring) << 16; | |
3936 | } | |
673a394b | 3937 | |
05394f39 | 3938 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 3939 | unlock: |
673a394b | 3940 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 3941 | return ret; |
673a394b EA |
3942 | } |
3943 | ||
3944 | int | |
3945 | i915_gem_throttle_ioctl(struct drm_device *dev, void *data, | |
3946 | struct drm_file *file_priv) | |
3947 | { | |
0206e353 | 3948 | return i915_gem_ring_throttle(dev, file_priv); |
673a394b EA |
3949 | } |
3950 | ||
3ef94daa CW |
3951 | int |
3952 | i915_gem_madvise_ioctl(struct drm_device *dev, void *data, | |
3953 | struct drm_file *file_priv) | |
3954 | { | |
3955 | struct drm_i915_gem_madvise *args = data; | |
05394f39 | 3956 | struct drm_i915_gem_object *obj; |
76c1dec1 | 3957 | int ret; |
3ef94daa CW |
3958 | |
3959 | switch (args->madv) { | |
3960 | case I915_MADV_DONTNEED: | |
3961 | case I915_MADV_WILLNEED: | |
3962 | break; | |
3963 | default: | |
3964 | return -EINVAL; | |
3965 | } | |
3966 | ||
1d7cfea1 CW |
3967 | ret = i915_mutex_lock_interruptible(dev); |
3968 | if (ret) | |
3969 | return ret; | |
3970 | ||
05394f39 | 3971 | obj = to_intel_bo(drm_gem_object_lookup(dev, file_priv, args->handle)); |
c8725226 | 3972 | if (&obj->base == NULL) { |
1d7cfea1 CW |
3973 | ret = -ENOENT; |
3974 | goto unlock; | |
3ef94daa | 3975 | } |
3ef94daa | 3976 | |
05394f39 | 3977 | if (obj->pin_count) { |
1d7cfea1 CW |
3978 | ret = -EINVAL; |
3979 | goto out; | |
3ef94daa CW |
3980 | } |
3981 | ||
05394f39 CW |
3982 | if (obj->madv != __I915_MADV_PURGED) |
3983 | obj->madv = args->madv; | |
3ef94daa | 3984 | |
6c085a72 CW |
3985 | /* if the object is no longer attached, discard its backing storage */ |
3986 | if (i915_gem_object_is_purgeable(obj) && obj->pages == NULL) | |
2d7ef395 CW |
3987 | i915_gem_object_truncate(obj); |
3988 | ||
05394f39 | 3989 | args->retained = obj->madv != __I915_MADV_PURGED; |
bb6baf76 | 3990 | |
1d7cfea1 | 3991 | out: |
05394f39 | 3992 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 3993 | unlock: |
3ef94daa | 3994 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 3995 | return ret; |
3ef94daa CW |
3996 | } |
3997 | ||
37e680a1 CW |
3998 | void i915_gem_object_init(struct drm_i915_gem_object *obj, |
3999 | const struct drm_i915_gem_object_ops *ops) | |
0327d6ba | 4000 | { |
35c20a60 | 4001 | INIT_LIST_HEAD(&obj->global_list); |
0327d6ba | 4002 | INIT_LIST_HEAD(&obj->ring_list); |
b25cb2f8 | 4003 | INIT_LIST_HEAD(&obj->obj_exec_link); |
2f633156 | 4004 | INIT_LIST_HEAD(&obj->vma_list); |
0327d6ba | 4005 | |
37e680a1 CW |
4006 | obj->ops = ops; |
4007 | ||
0327d6ba CW |
4008 | obj->fence_reg = I915_FENCE_REG_NONE; |
4009 | obj->madv = I915_MADV_WILLNEED; | |
4010 | /* Avoid an unnecessary call to unbind on the first bind. */ | |
4011 | obj->map_and_fenceable = true; | |
4012 | ||
4013 | i915_gem_info_add_obj(obj->base.dev->dev_private, obj->base.size); | |
4014 | } | |
4015 | ||
37e680a1 CW |
4016 | static const struct drm_i915_gem_object_ops i915_gem_object_ops = { |
4017 | .get_pages = i915_gem_object_get_pages_gtt, | |
4018 | .put_pages = i915_gem_object_put_pages_gtt, | |
4019 | }; | |
4020 | ||
05394f39 CW |
4021 | struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev, |
4022 | size_t size) | |
ac52bc56 | 4023 | { |
c397b908 | 4024 | struct drm_i915_gem_object *obj; |
5949eac4 | 4025 | struct address_space *mapping; |
1a240d4d | 4026 | gfp_t mask; |
ac52bc56 | 4027 | |
42dcedd4 | 4028 | obj = i915_gem_object_alloc(dev); |
c397b908 DV |
4029 | if (obj == NULL) |
4030 | return NULL; | |
673a394b | 4031 | |
c397b908 | 4032 | if (drm_gem_object_init(dev, &obj->base, size) != 0) { |
42dcedd4 | 4033 | i915_gem_object_free(obj); |
c397b908 DV |
4034 | return NULL; |
4035 | } | |
673a394b | 4036 | |
bed1ea95 CW |
4037 | mask = GFP_HIGHUSER | __GFP_RECLAIMABLE; |
4038 | if (IS_CRESTLINE(dev) || IS_BROADWATER(dev)) { | |
4039 | /* 965gm cannot relocate objects above 4GiB. */ | |
4040 | mask &= ~__GFP_HIGHMEM; | |
4041 | mask |= __GFP_DMA32; | |
4042 | } | |
4043 | ||
496ad9aa | 4044 | mapping = file_inode(obj->base.filp)->i_mapping; |
bed1ea95 | 4045 | mapping_set_gfp_mask(mapping, mask); |
5949eac4 | 4046 | |
37e680a1 | 4047 | i915_gem_object_init(obj, &i915_gem_object_ops); |
73aa808f | 4048 | |
c397b908 DV |
4049 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; |
4050 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; | |
673a394b | 4051 | |
3d29b842 ED |
4052 | if (HAS_LLC(dev)) { |
4053 | /* On some devices, we can have the GPU use the LLC (the CPU | |
a1871112 EA |
4054 | * cache) for about a 10% performance improvement |
4055 | * compared to uncached. Graphics requests other than | |
4056 | * display scanout are coherent with the CPU in | |
4057 | * accessing this cache. This means in this mode we | |
4058 | * don't need to clflush on the CPU side, and on the | |
4059 | * GPU side we only need to flush internal caches to | |
4060 | * get data visible to the CPU. | |
4061 | * | |
4062 | * However, we maintain the display planes as UC, and so | |
4063 | * need to rebind when first used as such. | |
4064 | */ | |
4065 | obj->cache_level = I915_CACHE_LLC; | |
4066 | } else | |
4067 | obj->cache_level = I915_CACHE_NONE; | |
4068 | ||
d861e338 DV |
4069 | trace_i915_gem_object_create(obj); |
4070 | ||
05394f39 | 4071 | return obj; |
c397b908 DV |
4072 | } |
4073 | ||
4074 | int i915_gem_init_object(struct drm_gem_object *obj) | |
4075 | { | |
4076 | BUG(); | |
de151cf6 | 4077 | |
673a394b EA |
4078 | return 0; |
4079 | } | |
4080 | ||
1488fc08 | 4081 | void i915_gem_free_object(struct drm_gem_object *gem_obj) |
673a394b | 4082 | { |
1488fc08 | 4083 | struct drm_i915_gem_object *obj = to_intel_bo(gem_obj); |
05394f39 | 4084 | struct drm_device *dev = obj->base.dev; |
be72615b | 4085 | drm_i915_private_t *dev_priv = dev->dev_private; |
07fe0b12 | 4086 | struct i915_vma *vma, *next; |
673a394b | 4087 | |
26e12f89 CW |
4088 | trace_i915_gem_object_destroy(obj); |
4089 | ||
1488fc08 CW |
4090 | if (obj->phys_obj) |
4091 | i915_gem_detach_phys_object(dev, obj); | |
4092 | ||
4093 | obj->pin_count = 0; | |
07fe0b12 BW |
4094 | /* NB: 0 or 1 elements */ |
4095 | WARN_ON(!list_empty(&obj->vma_list) && | |
4096 | !list_is_singular(&obj->vma_list)); | |
4097 | list_for_each_entry_safe(vma, next, &obj->vma_list, vma_link) { | |
4098 | int ret = i915_vma_unbind(vma); | |
4099 | if (WARN_ON(ret == -ERESTARTSYS)) { | |
4100 | bool was_interruptible; | |
1488fc08 | 4101 | |
07fe0b12 BW |
4102 | was_interruptible = dev_priv->mm.interruptible; |
4103 | dev_priv->mm.interruptible = false; | |
1488fc08 | 4104 | |
07fe0b12 | 4105 | WARN_ON(i915_vma_unbind(vma)); |
1488fc08 | 4106 | |
07fe0b12 BW |
4107 | dev_priv->mm.interruptible = was_interruptible; |
4108 | } | |
1488fc08 CW |
4109 | } |
4110 | ||
1d64ae71 BW |
4111 | /* Stolen objects don't hold a ref, but do hold pin count. Fix that up |
4112 | * before progressing. */ | |
4113 | if (obj->stolen) | |
4114 | i915_gem_object_unpin_pages(obj); | |
4115 | ||
401c29f6 BW |
4116 | if (WARN_ON(obj->pages_pin_count)) |
4117 | obj->pages_pin_count = 0; | |
37e680a1 | 4118 | i915_gem_object_put_pages(obj); |
d8cb5086 | 4119 | i915_gem_object_free_mmap_offset(obj); |
0104fdbb | 4120 | i915_gem_object_release_stolen(obj); |
de151cf6 | 4121 | |
9da3da66 CW |
4122 | BUG_ON(obj->pages); |
4123 | ||
2f745ad3 CW |
4124 | if (obj->base.import_attach) |
4125 | drm_prime_gem_destroy(&obj->base, NULL); | |
de151cf6 | 4126 | |
05394f39 CW |
4127 | drm_gem_object_release(&obj->base); |
4128 | i915_gem_info_remove_obj(dev_priv, obj->base.size); | |
c397b908 | 4129 | |
05394f39 | 4130 | kfree(obj->bit_17); |
42dcedd4 | 4131 | i915_gem_object_free(obj); |
673a394b EA |
4132 | } |
4133 | ||
e656a6cb | 4134 | struct i915_vma *i915_gem_obj_to_vma(struct drm_i915_gem_object *obj, |
2f633156 | 4135 | struct i915_address_space *vm) |
e656a6cb DV |
4136 | { |
4137 | struct i915_vma *vma; | |
4138 | list_for_each_entry(vma, &obj->vma_list, vma_link) | |
4139 | if (vma->vm == vm) | |
4140 | return vma; | |
4141 | ||
4142 | return NULL; | |
4143 | } | |
4144 | ||
4145 | static struct i915_vma *__i915_gem_vma_create(struct drm_i915_gem_object *obj, | |
4146 | struct i915_address_space *vm) | |
2f633156 BW |
4147 | { |
4148 | struct i915_vma *vma = kzalloc(sizeof(*vma), GFP_KERNEL); | |
4149 | if (vma == NULL) | |
4150 | return ERR_PTR(-ENOMEM); | |
4151 | ||
4152 | INIT_LIST_HEAD(&vma->vma_link); | |
ca191b13 | 4153 | INIT_LIST_HEAD(&vma->mm_list); |
82a55ad1 | 4154 | INIT_LIST_HEAD(&vma->exec_list); |
2f633156 BW |
4155 | vma->vm = vm; |
4156 | vma->obj = obj; | |
4157 | ||
8b9c2b94 BW |
4158 | /* Keep GGTT vmas first to make debug easier */ |
4159 | if (i915_is_ggtt(vm)) | |
4160 | list_add(&vma->vma_link, &obj->vma_list); | |
4161 | else | |
4162 | list_add_tail(&vma->vma_link, &obj->vma_list); | |
4163 | ||
2f633156 BW |
4164 | return vma; |
4165 | } | |
4166 | ||
e656a6cb DV |
4167 | struct i915_vma * |
4168 | i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object *obj, | |
4169 | struct i915_address_space *vm) | |
4170 | { | |
4171 | struct i915_vma *vma; | |
4172 | ||
4173 | vma = i915_gem_obj_to_vma(obj, vm); | |
4174 | if (!vma) | |
4175 | vma = __i915_gem_vma_create(obj, vm); | |
4176 | ||
4177 | return vma; | |
4178 | } | |
4179 | ||
2f633156 BW |
4180 | void i915_gem_vma_destroy(struct i915_vma *vma) |
4181 | { | |
4182 | WARN_ON(vma->node.allocated); | |
aaa05667 CW |
4183 | |
4184 | /* Keep the vma as a placeholder in the execbuffer reservation lists */ | |
4185 | if (!list_empty(&vma->exec_list)) | |
4186 | return; | |
4187 | ||
b93dab6e DV |
4188 | list_del(&vma->vma_link); |
4189 | ||
2f633156 BW |
4190 | kfree(vma); |
4191 | } | |
4192 | ||
29105ccc CW |
4193 | int |
4194 | i915_gem_idle(struct drm_device *dev) | |
4195 | { | |
4196 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4197 | int ret; | |
28dfe52a | 4198 | |
db1b76ca | 4199 | if (dev_priv->ums.mm_suspended) { |
29105ccc CW |
4200 | mutex_unlock(&dev->struct_mutex); |
4201 | return 0; | |
28dfe52a EA |
4202 | } |
4203 | ||
b2da9fe5 | 4204 | ret = i915_gpu_idle(dev); |
6dbe2772 KP |
4205 | if (ret) { |
4206 | mutex_unlock(&dev->struct_mutex); | |
673a394b | 4207 | return ret; |
6dbe2772 | 4208 | } |
b2da9fe5 | 4209 | i915_gem_retire_requests(dev); |
673a394b | 4210 | |
29105ccc | 4211 | /* Under UMS, be paranoid and evict. */ |
a39d7efc | 4212 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) |
6c085a72 | 4213 | i915_gem_evict_everything(dev); |
29105ccc | 4214 | |
99584db3 | 4215 | del_timer_sync(&dev_priv->gpu_error.hangcheck_timer); |
29105ccc CW |
4216 | |
4217 | i915_kernel_lost_context(dev); | |
6dbe2772 | 4218 | i915_gem_cleanup_ringbuffer(dev); |
29105ccc | 4219 | |
29105ccc CW |
4220 | /* Cancel the retire work handler, which should be idle now. */ |
4221 | cancel_delayed_work_sync(&dev_priv->mm.retire_work); | |
4222 | ||
673a394b EA |
4223 | return 0; |
4224 | } | |
4225 | ||
b9524a1e BW |
4226 | void i915_gem_l3_remap(struct drm_device *dev) |
4227 | { | |
4228 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4229 | u32 misccpctl; | |
4230 | int i; | |
4231 | ||
eb32e458 | 4232 | if (!HAS_L3_GPU_CACHE(dev)) |
b9524a1e BW |
4233 | return; |
4234 | ||
a4da4fa4 | 4235 | if (!dev_priv->l3_parity.remap_info) |
b9524a1e BW |
4236 | return; |
4237 | ||
4238 | misccpctl = I915_READ(GEN7_MISCCPCTL); | |
4239 | I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE); | |
4240 | POSTING_READ(GEN7_MISCCPCTL); | |
4241 | ||
4242 | for (i = 0; i < GEN7_L3LOG_SIZE; i += 4) { | |
4243 | u32 remap = I915_READ(GEN7_L3LOG_BASE + i); | |
a4da4fa4 | 4244 | if (remap && remap != dev_priv->l3_parity.remap_info[i/4]) |
b9524a1e BW |
4245 | DRM_DEBUG("0x%x was already programmed to %x\n", |
4246 | GEN7_L3LOG_BASE + i, remap); | |
a4da4fa4 | 4247 | if (remap && !dev_priv->l3_parity.remap_info[i/4]) |
b9524a1e | 4248 | DRM_DEBUG_DRIVER("Clearing remapped register\n"); |
a4da4fa4 | 4249 | I915_WRITE(GEN7_L3LOG_BASE + i, dev_priv->l3_parity.remap_info[i/4]); |
b9524a1e BW |
4250 | } |
4251 | ||
4252 | /* Make sure all the writes land before disabling dop clock gating */ | |
4253 | POSTING_READ(GEN7_L3LOG_BASE); | |
4254 | ||
4255 | I915_WRITE(GEN7_MISCCPCTL, misccpctl); | |
4256 | } | |
4257 | ||
f691e2f4 DV |
4258 | void i915_gem_init_swizzling(struct drm_device *dev) |
4259 | { | |
4260 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4261 | ||
11782b02 | 4262 | if (INTEL_INFO(dev)->gen < 5 || |
f691e2f4 DV |
4263 | dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE) |
4264 | return; | |
4265 | ||
4266 | I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) | | |
4267 | DISP_TILE_SURFACE_SWIZZLING); | |
4268 | ||
11782b02 DV |
4269 | if (IS_GEN5(dev)) |
4270 | return; | |
4271 | ||
f691e2f4 DV |
4272 | I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_SWZCTL); |
4273 | if (IS_GEN6(dev)) | |
6b26c86d | 4274 | I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB)); |
8782e26c | 4275 | else if (IS_GEN7(dev)) |
6b26c86d | 4276 | I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB)); |
8782e26c BW |
4277 | else |
4278 | BUG(); | |
f691e2f4 | 4279 | } |
e21af88d | 4280 | |
67b1b571 CW |
4281 | static bool |
4282 | intel_enable_blt(struct drm_device *dev) | |
4283 | { | |
4284 | if (!HAS_BLT(dev)) | |
4285 | return false; | |
4286 | ||
4287 | /* The blitter was dysfunctional on early prototypes */ | |
4288 | if (IS_GEN6(dev) && dev->pdev->revision < 8) { | |
4289 | DRM_INFO("BLT not supported on this pre-production hardware;" | |
4290 | " graphics performance will be degraded.\n"); | |
4291 | return false; | |
4292 | } | |
4293 | ||
4294 | return true; | |
4295 | } | |
4296 | ||
4fc7c971 | 4297 | static int i915_gem_init_rings(struct drm_device *dev) |
8187a2b7 | 4298 | { |
4fc7c971 | 4299 | struct drm_i915_private *dev_priv = dev->dev_private; |
8187a2b7 | 4300 | int ret; |
68f95ba9 | 4301 | |
5c1143bb | 4302 | ret = intel_init_render_ring_buffer(dev); |
68f95ba9 | 4303 | if (ret) |
b6913e4b | 4304 | return ret; |
68f95ba9 CW |
4305 | |
4306 | if (HAS_BSD(dev)) { | |
5c1143bb | 4307 | ret = intel_init_bsd_ring_buffer(dev); |
68f95ba9 CW |
4308 | if (ret) |
4309 | goto cleanup_render_ring; | |
d1b851fc | 4310 | } |
68f95ba9 | 4311 | |
67b1b571 | 4312 | if (intel_enable_blt(dev)) { |
549f7365 CW |
4313 | ret = intel_init_blt_ring_buffer(dev); |
4314 | if (ret) | |
4315 | goto cleanup_bsd_ring; | |
4316 | } | |
4317 | ||
9a8a2213 BW |
4318 | if (HAS_VEBOX(dev)) { |
4319 | ret = intel_init_vebox_ring_buffer(dev); | |
4320 | if (ret) | |
4321 | goto cleanup_blt_ring; | |
4322 | } | |
4323 | ||
4324 | ||
99433931 | 4325 | ret = i915_gem_set_seqno(dev, ((u32)~0 - 0x1000)); |
4fc7c971 | 4326 | if (ret) |
9a8a2213 | 4327 | goto cleanup_vebox_ring; |
4fc7c971 BW |
4328 | |
4329 | return 0; | |
4330 | ||
9a8a2213 BW |
4331 | cleanup_vebox_ring: |
4332 | intel_cleanup_ring_buffer(&dev_priv->ring[VECS]); | |
4fc7c971 BW |
4333 | cleanup_blt_ring: |
4334 | intel_cleanup_ring_buffer(&dev_priv->ring[BCS]); | |
4335 | cleanup_bsd_ring: | |
4336 | intel_cleanup_ring_buffer(&dev_priv->ring[VCS]); | |
4337 | cleanup_render_ring: | |
4338 | intel_cleanup_ring_buffer(&dev_priv->ring[RCS]); | |
4339 | ||
4340 | return ret; | |
4341 | } | |
4342 | ||
4343 | int | |
4344 | i915_gem_init_hw(struct drm_device *dev) | |
4345 | { | |
4346 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4347 | int ret; | |
4348 | ||
4349 | if (INTEL_INFO(dev)->gen < 6 && !intel_enable_gtt()) | |
4350 | return -EIO; | |
4351 | ||
59124506 | 4352 | if (dev_priv->ellc_size) |
05e21cc4 | 4353 | I915_WRITE(HSW_IDICR, I915_READ(HSW_IDICR) | IDIHASHMSK(0xf)); |
4fc7c971 | 4354 | |
9435373e RV |
4355 | if (IS_HSW_GT3(dev)) |
4356 | I915_WRITE(MI_PREDICATE_RESULT_2, LOWER_SLICE_ENABLED); | |
4357 | else | |
4358 | I915_WRITE(MI_PREDICATE_RESULT_2, LOWER_SLICE_DISABLED); | |
4359 | ||
88a2b2a3 BW |
4360 | if (HAS_PCH_NOP(dev)) { |
4361 | u32 temp = I915_READ(GEN7_MSG_CTL); | |
4362 | temp &= ~(WAIT_FOR_PCH_FLR_ACK | WAIT_FOR_PCH_RESET_ACK); | |
4363 | I915_WRITE(GEN7_MSG_CTL, temp); | |
4364 | } | |
4365 | ||
4fc7c971 BW |
4366 | i915_gem_l3_remap(dev); |
4367 | ||
4368 | i915_gem_init_swizzling(dev); | |
4369 | ||
4370 | ret = i915_gem_init_rings(dev); | |
99433931 MK |
4371 | if (ret) |
4372 | return ret; | |
4373 | ||
254f965c BW |
4374 | /* |
4375 | * XXX: There was some w/a described somewhere suggesting loading | |
4376 | * contexts before PPGTT. | |
4377 | */ | |
4378 | i915_gem_context_init(dev); | |
b7c36d25 BW |
4379 | if (dev_priv->mm.aliasing_ppgtt) { |
4380 | ret = dev_priv->mm.aliasing_ppgtt->enable(dev); | |
4381 | if (ret) { | |
4382 | i915_gem_cleanup_aliasing_ppgtt(dev); | |
4383 | DRM_INFO("PPGTT enable failed. This is not fatal, but unexpected\n"); | |
4384 | } | |
4385 | } | |
e21af88d | 4386 | |
68f95ba9 | 4387 | return 0; |
8187a2b7 ZN |
4388 | } |
4389 | ||
1070a42b CW |
4390 | int i915_gem_init(struct drm_device *dev) |
4391 | { | |
4392 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1070a42b CW |
4393 | int ret; |
4394 | ||
1070a42b | 4395 | mutex_lock(&dev->struct_mutex); |
d62b4892 JB |
4396 | |
4397 | if (IS_VALLEYVIEW(dev)) { | |
4398 | /* VLVA0 (potential hack), BIOS isn't actually waking us */ | |
4399 | I915_WRITE(VLV_GTLC_WAKE_CTRL, 1); | |
4400 | if (wait_for((I915_READ(VLV_GTLC_PW_STATUS) & 1) == 1, 10)) | |
4401 | DRM_DEBUG_DRIVER("allow wake ack timed out\n"); | |
4402 | } | |
4403 | ||
d7e5008f | 4404 | i915_gem_init_global_gtt(dev); |
d62b4892 | 4405 | |
1070a42b CW |
4406 | ret = i915_gem_init_hw(dev); |
4407 | mutex_unlock(&dev->struct_mutex); | |
4408 | if (ret) { | |
4409 | i915_gem_cleanup_aliasing_ppgtt(dev); | |
4410 | return ret; | |
4411 | } | |
4412 | ||
53ca26ca DV |
4413 | /* Allow hardware batchbuffers unless told otherwise, but not for KMS. */ |
4414 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) | |
4415 | dev_priv->dri1.allow_batchbuffer = 1; | |
1070a42b CW |
4416 | return 0; |
4417 | } | |
4418 | ||
8187a2b7 ZN |
4419 | void |
4420 | i915_gem_cleanup_ringbuffer(struct drm_device *dev) | |
4421 | { | |
4422 | drm_i915_private_t *dev_priv = dev->dev_private; | |
b4519513 | 4423 | struct intel_ring_buffer *ring; |
1ec14ad3 | 4424 | int i; |
8187a2b7 | 4425 | |
b4519513 CW |
4426 | for_each_ring(ring, dev_priv, i) |
4427 | intel_cleanup_ring_buffer(ring); | |
8187a2b7 ZN |
4428 | } |
4429 | ||
673a394b EA |
4430 | int |
4431 | i915_gem_entervt_ioctl(struct drm_device *dev, void *data, | |
4432 | struct drm_file *file_priv) | |
4433 | { | |
db1b76ca | 4434 | struct drm_i915_private *dev_priv = dev->dev_private; |
b4519513 | 4435 | int ret; |
673a394b | 4436 | |
79e53945 JB |
4437 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
4438 | return 0; | |
4439 | ||
1f83fee0 | 4440 | if (i915_reset_in_progress(&dev_priv->gpu_error)) { |
673a394b | 4441 | DRM_ERROR("Reenabling wedged hardware, good luck\n"); |
1f83fee0 | 4442 | atomic_set(&dev_priv->gpu_error.reset_counter, 0); |
673a394b EA |
4443 | } |
4444 | ||
673a394b | 4445 | mutex_lock(&dev->struct_mutex); |
db1b76ca | 4446 | dev_priv->ums.mm_suspended = 0; |
9bb2d6f9 | 4447 | |
f691e2f4 | 4448 | ret = i915_gem_init_hw(dev); |
d816f6ac WF |
4449 | if (ret != 0) { |
4450 | mutex_unlock(&dev->struct_mutex); | |
9bb2d6f9 | 4451 | return ret; |
d816f6ac | 4452 | } |
9bb2d6f9 | 4453 | |
5cef07e1 | 4454 | BUG_ON(!list_empty(&dev_priv->gtt.base.active_list)); |
673a394b | 4455 | mutex_unlock(&dev->struct_mutex); |
dbb19d30 | 4456 | |
5f35308b CW |
4457 | ret = drm_irq_install(dev); |
4458 | if (ret) | |
4459 | goto cleanup_ringbuffer; | |
dbb19d30 | 4460 | |
673a394b | 4461 | return 0; |
5f35308b CW |
4462 | |
4463 | cleanup_ringbuffer: | |
4464 | mutex_lock(&dev->struct_mutex); | |
4465 | i915_gem_cleanup_ringbuffer(dev); | |
db1b76ca | 4466 | dev_priv->ums.mm_suspended = 1; |
5f35308b CW |
4467 | mutex_unlock(&dev->struct_mutex); |
4468 | ||
4469 | return ret; | |
673a394b EA |
4470 | } |
4471 | ||
4472 | int | |
4473 | i915_gem_leavevt_ioctl(struct drm_device *dev, void *data, | |
4474 | struct drm_file *file_priv) | |
4475 | { | |
db1b76ca DV |
4476 | struct drm_i915_private *dev_priv = dev->dev_private; |
4477 | int ret; | |
4478 | ||
79e53945 JB |
4479 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
4480 | return 0; | |
4481 | ||
dbb19d30 | 4482 | drm_irq_uninstall(dev); |
db1b76ca DV |
4483 | |
4484 | mutex_lock(&dev->struct_mutex); | |
4485 | ret = i915_gem_idle(dev); | |
4486 | ||
4487 | /* Hack! Don't let anybody do execbuf while we don't control the chip. | |
4488 | * We need to replace this with a semaphore, or something. | |
4489 | * And not confound ums.mm_suspended! | |
4490 | */ | |
4491 | if (ret != 0) | |
4492 | dev_priv->ums.mm_suspended = 1; | |
4493 | mutex_unlock(&dev->struct_mutex); | |
4494 | ||
4495 | return ret; | |
673a394b EA |
4496 | } |
4497 | ||
4498 | void | |
4499 | i915_gem_lastclose(struct drm_device *dev) | |
4500 | { | |
4501 | int ret; | |
673a394b | 4502 | |
e806b495 EA |
4503 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
4504 | return; | |
4505 | ||
db1b76ca | 4506 | mutex_lock(&dev->struct_mutex); |
6dbe2772 KP |
4507 | ret = i915_gem_idle(dev); |
4508 | if (ret) | |
4509 | DRM_ERROR("failed to idle hardware: %d\n", ret); | |
db1b76ca | 4510 | mutex_unlock(&dev->struct_mutex); |
673a394b EA |
4511 | } |
4512 | ||
64193406 CW |
4513 | static void |
4514 | init_ring_lists(struct intel_ring_buffer *ring) | |
4515 | { | |
4516 | INIT_LIST_HEAD(&ring->active_list); | |
4517 | INIT_LIST_HEAD(&ring->request_list); | |
64193406 CW |
4518 | } |
4519 | ||
fc8c067e BW |
4520 | static void i915_init_vm(struct drm_i915_private *dev_priv, |
4521 | struct i915_address_space *vm) | |
4522 | { | |
4523 | vm->dev = dev_priv->dev; | |
4524 | INIT_LIST_HEAD(&vm->active_list); | |
4525 | INIT_LIST_HEAD(&vm->inactive_list); | |
4526 | INIT_LIST_HEAD(&vm->global_link); | |
4527 | list_add(&vm->global_link, &dev_priv->vm_list); | |
4528 | } | |
4529 | ||
673a394b EA |
4530 | void |
4531 | i915_gem_load(struct drm_device *dev) | |
4532 | { | |
4533 | drm_i915_private_t *dev_priv = dev->dev_private; | |
42dcedd4 CW |
4534 | int i; |
4535 | ||
4536 | dev_priv->slab = | |
4537 | kmem_cache_create("i915_gem_object", | |
4538 | sizeof(struct drm_i915_gem_object), 0, | |
4539 | SLAB_HWCACHE_ALIGN, | |
4540 | NULL); | |
673a394b | 4541 | |
fc8c067e BW |
4542 | INIT_LIST_HEAD(&dev_priv->vm_list); |
4543 | i915_init_vm(dev_priv, &dev_priv->gtt.base); | |
4544 | ||
6c085a72 CW |
4545 | INIT_LIST_HEAD(&dev_priv->mm.unbound_list); |
4546 | INIT_LIST_HEAD(&dev_priv->mm.bound_list); | |
a09ba7fa | 4547 | INIT_LIST_HEAD(&dev_priv->mm.fence_list); |
1ec14ad3 CW |
4548 | for (i = 0; i < I915_NUM_RINGS; i++) |
4549 | init_ring_lists(&dev_priv->ring[i]); | |
4b9de737 | 4550 | for (i = 0; i < I915_MAX_NUM_FENCES; i++) |
007cc8ac | 4551 | INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list); |
673a394b EA |
4552 | INIT_DELAYED_WORK(&dev_priv->mm.retire_work, |
4553 | i915_gem_retire_work_handler); | |
1f83fee0 | 4554 | init_waitqueue_head(&dev_priv->gpu_error.reset_queue); |
31169714 | 4555 | |
94400120 DA |
4556 | /* On GEN3 we really need to make sure the ARB C3 LP bit is set */ |
4557 | if (IS_GEN3(dev)) { | |
50743298 DV |
4558 | I915_WRITE(MI_ARB_STATE, |
4559 | _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE)); | |
94400120 DA |
4560 | } |
4561 | ||
72bfa19c CW |
4562 | dev_priv->relative_constants_mode = I915_EXEC_CONSTANTS_REL_GENERAL; |
4563 | ||
de151cf6 | 4564 | /* Old X drivers will take 0-2 for front, back, depth buffers */ |
b397c836 EA |
4565 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) |
4566 | dev_priv->fence_reg_start = 3; | |
de151cf6 | 4567 | |
42b5aeab VS |
4568 | if (INTEL_INFO(dev)->gen >= 7 && !IS_VALLEYVIEW(dev)) |
4569 | dev_priv->num_fence_regs = 32; | |
4570 | else if (INTEL_INFO(dev)->gen >= 4 || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) | |
de151cf6 JB |
4571 | dev_priv->num_fence_regs = 16; |
4572 | else | |
4573 | dev_priv->num_fence_regs = 8; | |
4574 | ||
b5aa8a0f | 4575 | /* Initialize fence registers to zero */ |
19b2dbde CW |
4576 | INIT_LIST_HEAD(&dev_priv->mm.fence_list); |
4577 | i915_gem_restore_fences(dev); | |
10ed13e4 | 4578 | |
673a394b | 4579 | i915_gem_detect_bit_6_swizzle(dev); |
6b95a207 | 4580 | init_waitqueue_head(&dev_priv->pending_flip_queue); |
17250b71 | 4581 | |
ce453d81 CW |
4582 | dev_priv->mm.interruptible = true; |
4583 | ||
17250b71 CW |
4584 | dev_priv->mm.inactive_shrinker.shrink = i915_gem_inactive_shrink; |
4585 | dev_priv->mm.inactive_shrinker.seeks = DEFAULT_SEEKS; | |
4586 | register_shrinker(&dev_priv->mm.inactive_shrinker); | |
673a394b | 4587 | } |
71acb5eb DA |
4588 | |
4589 | /* | |
4590 | * Create a physically contiguous memory object for this object | |
4591 | * e.g. for cursor + overlay regs | |
4592 | */ | |
995b6762 CW |
4593 | static int i915_gem_init_phys_object(struct drm_device *dev, |
4594 | int id, int size, int align) | |
71acb5eb DA |
4595 | { |
4596 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4597 | struct drm_i915_gem_phys_object *phys_obj; | |
4598 | int ret; | |
4599 | ||
4600 | if (dev_priv->mm.phys_objs[id - 1] || !size) | |
4601 | return 0; | |
4602 | ||
9a298b2a | 4603 | phys_obj = kzalloc(sizeof(struct drm_i915_gem_phys_object), GFP_KERNEL); |
71acb5eb DA |
4604 | if (!phys_obj) |
4605 | return -ENOMEM; | |
4606 | ||
4607 | phys_obj->id = id; | |
4608 | ||
6eeefaf3 | 4609 | phys_obj->handle = drm_pci_alloc(dev, size, align); |
71acb5eb DA |
4610 | if (!phys_obj->handle) { |
4611 | ret = -ENOMEM; | |
4612 | goto kfree_obj; | |
4613 | } | |
4614 | #ifdef CONFIG_X86 | |
4615 | set_memory_wc((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE); | |
4616 | #endif | |
4617 | ||
4618 | dev_priv->mm.phys_objs[id - 1] = phys_obj; | |
4619 | ||
4620 | return 0; | |
4621 | kfree_obj: | |
9a298b2a | 4622 | kfree(phys_obj); |
71acb5eb DA |
4623 | return ret; |
4624 | } | |
4625 | ||
995b6762 | 4626 | static void i915_gem_free_phys_object(struct drm_device *dev, int id) |
71acb5eb DA |
4627 | { |
4628 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4629 | struct drm_i915_gem_phys_object *phys_obj; | |
4630 | ||
4631 | if (!dev_priv->mm.phys_objs[id - 1]) | |
4632 | return; | |
4633 | ||
4634 | phys_obj = dev_priv->mm.phys_objs[id - 1]; | |
4635 | if (phys_obj->cur_obj) { | |
4636 | i915_gem_detach_phys_object(dev, phys_obj->cur_obj); | |
4637 | } | |
4638 | ||
4639 | #ifdef CONFIG_X86 | |
4640 | set_memory_wb((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE); | |
4641 | #endif | |
4642 | drm_pci_free(dev, phys_obj->handle); | |
4643 | kfree(phys_obj); | |
4644 | dev_priv->mm.phys_objs[id - 1] = NULL; | |
4645 | } | |
4646 | ||
4647 | void i915_gem_free_all_phys_object(struct drm_device *dev) | |
4648 | { | |
4649 | int i; | |
4650 | ||
260883c8 | 4651 | for (i = I915_GEM_PHYS_CURSOR_0; i <= I915_MAX_PHYS_OBJECT; i++) |
71acb5eb DA |
4652 | i915_gem_free_phys_object(dev, i); |
4653 | } | |
4654 | ||
4655 | void i915_gem_detach_phys_object(struct drm_device *dev, | |
05394f39 | 4656 | struct drm_i915_gem_object *obj) |
71acb5eb | 4657 | { |
496ad9aa | 4658 | struct address_space *mapping = file_inode(obj->base.filp)->i_mapping; |
e5281ccd | 4659 | char *vaddr; |
71acb5eb | 4660 | int i; |
71acb5eb DA |
4661 | int page_count; |
4662 | ||
05394f39 | 4663 | if (!obj->phys_obj) |
71acb5eb | 4664 | return; |
05394f39 | 4665 | vaddr = obj->phys_obj->handle->vaddr; |
71acb5eb | 4666 | |
05394f39 | 4667 | page_count = obj->base.size / PAGE_SIZE; |
71acb5eb | 4668 | for (i = 0; i < page_count; i++) { |
5949eac4 | 4669 | struct page *page = shmem_read_mapping_page(mapping, i); |
e5281ccd CW |
4670 | if (!IS_ERR(page)) { |
4671 | char *dst = kmap_atomic(page); | |
4672 | memcpy(dst, vaddr + i*PAGE_SIZE, PAGE_SIZE); | |
4673 | kunmap_atomic(dst); | |
4674 | ||
4675 | drm_clflush_pages(&page, 1); | |
4676 | ||
4677 | set_page_dirty(page); | |
4678 | mark_page_accessed(page); | |
4679 | page_cache_release(page); | |
4680 | } | |
71acb5eb | 4681 | } |
e76e9aeb | 4682 | i915_gem_chipset_flush(dev); |
d78b47b9 | 4683 | |
05394f39 CW |
4684 | obj->phys_obj->cur_obj = NULL; |
4685 | obj->phys_obj = NULL; | |
71acb5eb DA |
4686 | } |
4687 | ||
4688 | int | |
4689 | i915_gem_attach_phys_object(struct drm_device *dev, | |
05394f39 | 4690 | struct drm_i915_gem_object *obj, |
6eeefaf3 CW |
4691 | int id, |
4692 | int align) | |
71acb5eb | 4693 | { |
496ad9aa | 4694 | struct address_space *mapping = file_inode(obj->base.filp)->i_mapping; |
71acb5eb | 4695 | drm_i915_private_t *dev_priv = dev->dev_private; |
71acb5eb DA |
4696 | int ret = 0; |
4697 | int page_count; | |
4698 | int i; | |
4699 | ||
4700 | if (id > I915_MAX_PHYS_OBJECT) | |
4701 | return -EINVAL; | |
4702 | ||
05394f39 CW |
4703 | if (obj->phys_obj) { |
4704 | if (obj->phys_obj->id == id) | |
71acb5eb DA |
4705 | return 0; |
4706 | i915_gem_detach_phys_object(dev, obj); | |
4707 | } | |
4708 | ||
71acb5eb DA |
4709 | /* create a new object */ |
4710 | if (!dev_priv->mm.phys_objs[id - 1]) { | |
4711 | ret = i915_gem_init_phys_object(dev, id, | |
05394f39 | 4712 | obj->base.size, align); |
71acb5eb | 4713 | if (ret) { |
05394f39 CW |
4714 | DRM_ERROR("failed to init phys object %d size: %zu\n", |
4715 | id, obj->base.size); | |
e5281ccd | 4716 | return ret; |
71acb5eb DA |
4717 | } |
4718 | } | |
4719 | ||
4720 | /* bind to the object */ | |
05394f39 CW |
4721 | obj->phys_obj = dev_priv->mm.phys_objs[id - 1]; |
4722 | obj->phys_obj->cur_obj = obj; | |
71acb5eb | 4723 | |
05394f39 | 4724 | page_count = obj->base.size / PAGE_SIZE; |
71acb5eb DA |
4725 | |
4726 | for (i = 0; i < page_count; i++) { | |
e5281ccd CW |
4727 | struct page *page; |
4728 | char *dst, *src; | |
4729 | ||
5949eac4 | 4730 | page = shmem_read_mapping_page(mapping, i); |
e5281ccd CW |
4731 | if (IS_ERR(page)) |
4732 | return PTR_ERR(page); | |
71acb5eb | 4733 | |
ff75b9bc | 4734 | src = kmap_atomic(page); |
05394f39 | 4735 | dst = obj->phys_obj->handle->vaddr + (i * PAGE_SIZE); |
71acb5eb | 4736 | memcpy(dst, src, PAGE_SIZE); |
3e4d3af5 | 4737 | kunmap_atomic(src); |
71acb5eb | 4738 | |
e5281ccd CW |
4739 | mark_page_accessed(page); |
4740 | page_cache_release(page); | |
4741 | } | |
d78b47b9 | 4742 | |
71acb5eb | 4743 | return 0; |
71acb5eb DA |
4744 | } |
4745 | ||
4746 | static int | |
05394f39 CW |
4747 | i915_gem_phys_pwrite(struct drm_device *dev, |
4748 | struct drm_i915_gem_object *obj, | |
71acb5eb DA |
4749 | struct drm_i915_gem_pwrite *args, |
4750 | struct drm_file *file_priv) | |
4751 | { | |
05394f39 | 4752 | void *vaddr = obj->phys_obj->handle->vaddr + args->offset; |
2bb4629a | 4753 | char __user *user_data = to_user_ptr(args->data_ptr); |
71acb5eb | 4754 | |
b47b30cc CW |
4755 | if (__copy_from_user_inatomic_nocache(vaddr, user_data, args->size)) { |
4756 | unsigned long unwritten; | |
4757 | ||
4758 | /* The physical object once assigned is fixed for the lifetime | |
4759 | * of the obj, so we can safely drop the lock and continue | |
4760 | * to access vaddr. | |
4761 | */ | |
4762 | mutex_unlock(&dev->struct_mutex); | |
4763 | unwritten = copy_from_user(vaddr, user_data, args->size); | |
4764 | mutex_lock(&dev->struct_mutex); | |
4765 | if (unwritten) | |
4766 | return -EFAULT; | |
4767 | } | |
71acb5eb | 4768 | |
e76e9aeb | 4769 | i915_gem_chipset_flush(dev); |
71acb5eb DA |
4770 | return 0; |
4771 | } | |
b962442e | 4772 | |
f787a5f5 | 4773 | void i915_gem_release(struct drm_device *dev, struct drm_file *file) |
b962442e | 4774 | { |
f787a5f5 | 4775 | struct drm_i915_file_private *file_priv = file->driver_priv; |
b962442e EA |
4776 | |
4777 | /* Clean up our request list when the client is going away, so that | |
4778 | * later retire_requests won't dereference our soon-to-be-gone | |
4779 | * file_priv. | |
4780 | */ | |
1c25595f | 4781 | spin_lock(&file_priv->mm.lock); |
f787a5f5 CW |
4782 | while (!list_empty(&file_priv->mm.request_list)) { |
4783 | struct drm_i915_gem_request *request; | |
4784 | ||
4785 | request = list_first_entry(&file_priv->mm.request_list, | |
4786 | struct drm_i915_gem_request, | |
4787 | client_list); | |
4788 | list_del(&request->client_list); | |
4789 | request->file_priv = NULL; | |
4790 | } | |
1c25595f | 4791 | spin_unlock(&file_priv->mm.lock); |
b962442e | 4792 | } |
31169714 | 4793 | |
5774506f CW |
4794 | static bool mutex_is_locked_by(struct mutex *mutex, struct task_struct *task) |
4795 | { | |
4796 | if (!mutex_is_locked(mutex)) | |
4797 | return false; | |
4798 | ||
4799 | #if defined(CONFIG_SMP) || defined(CONFIG_DEBUG_MUTEXES) | |
4800 | return mutex->owner == task; | |
4801 | #else | |
4802 | /* Since UP may be pre-empted, we cannot assume that we own the lock */ | |
4803 | return false; | |
4804 | #endif | |
4805 | } | |
4806 | ||
31169714 | 4807 | static int |
1495f230 | 4808 | i915_gem_inactive_shrink(struct shrinker *shrinker, struct shrink_control *sc) |
31169714 | 4809 | { |
17250b71 CW |
4810 | struct drm_i915_private *dev_priv = |
4811 | container_of(shrinker, | |
4812 | struct drm_i915_private, | |
4813 | mm.inactive_shrinker); | |
4814 | struct drm_device *dev = dev_priv->dev; | |
6c085a72 | 4815 | struct drm_i915_gem_object *obj; |
1495f230 | 4816 | int nr_to_scan = sc->nr_to_scan; |
5774506f | 4817 | bool unlock = true; |
17250b71 CW |
4818 | int cnt; |
4819 | ||
5774506f CW |
4820 | if (!mutex_trylock(&dev->struct_mutex)) { |
4821 | if (!mutex_is_locked_by(&dev->struct_mutex, current)) | |
4822 | return 0; | |
4823 | ||
677feac2 DV |
4824 | if (dev_priv->mm.shrinker_no_lock_stealing) |
4825 | return 0; | |
4826 | ||
5774506f CW |
4827 | unlock = false; |
4828 | } | |
31169714 | 4829 | |
6c085a72 CW |
4830 | if (nr_to_scan) { |
4831 | nr_to_scan -= i915_gem_purge(dev_priv, nr_to_scan); | |
93927ca5 DV |
4832 | if (nr_to_scan > 0) |
4833 | nr_to_scan -= __i915_gem_shrink(dev_priv, nr_to_scan, | |
4834 | false); | |
6c085a72 CW |
4835 | if (nr_to_scan > 0) |
4836 | i915_gem_shrink_all(dev_priv); | |
31169714 CW |
4837 | } |
4838 | ||
17250b71 | 4839 | cnt = 0; |
35c20a60 | 4840 | list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) |
a5570178 CW |
4841 | if (obj->pages_pin_count == 0) |
4842 | cnt += obj->base.size >> PAGE_SHIFT; | |
fcb4a578 BW |
4843 | |
4844 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) { | |
4845 | if (obj->active) | |
4846 | continue; | |
4847 | ||
a5570178 | 4848 | if (obj->pin_count == 0 && obj->pages_pin_count == 0) |
6c085a72 | 4849 | cnt += obj->base.size >> PAGE_SHIFT; |
fcb4a578 | 4850 | } |
17250b71 | 4851 | |
5774506f CW |
4852 | if (unlock) |
4853 | mutex_unlock(&dev->struct_mutex); | |
6c085a72 | 4854 | return cnt; |
31169714 | 4855 | } |
a70a3148 BW |
4856 | |
4857 | /* All the new VM stuff */ | |
4858 | unsigned long i915_gem_obj_offset(struct drm_i915_gem_object *o, | |
4859 | struct i915_address_space *vm) | |
4860 | { | |
4861 | struct drm_i915_private *dev_priv = o->base.dev->dev_private; | |
4862 | struct i915_vma *vma; | |
4863 | ||
4864 | if (vm == &dev_priv->mm.aliasing_ppgtt->base) | |
4865 | vm = &dev_priv->gtt.base; | |
4866 | ||
4867 | BUG_ON(list_empty(&o->vma_list)); | |
4868 | list_for_each_entry(vma, &o->vma_list, vma_link) { | |
4869 | if (vma->vm == vm) | |
4870 | return vma->node.start; | |
4871 | ||
4872 | } | |
4873 | return -1; | |
4874 | } | |
4875 | ||
4876 | bool i915_gem_obj_bound(struct drm_i915_gem_object *o, | |
4877 | struct i915_address_space *vm) | |
4878 | { | |
4879 | struct i915_vma *vma; | |
4880 | ||
4881 | list_for_each_entry(vma, &o->vma_list, vma_link) | |
8b9c2b94 | 4882 | if (vma->vm == vm && drm_mm_node_allocated(&vma->node)) |
a70a3148 BW |
4883 | return true; |
4884 | ||
4885 | return false; | |
4886 | } | |
4887 | ||
4888 | bool i915_gem_obj_bound_any(struct drm_i915_gem_object *o) | |
4889 | { | |
4890 | struct drm_i915_private *dev_priv = o->base.dev->dev_private; | |
4891 | struct i915_address_space *vm; | |
4892 | ||
4893 | list_for_each_entry(vm, &dev_priv->vm_list, global_link) | |
4894 | if (i915_gem_obj_bound(o, vm)) | |
4895 | return true; | |
4896 | ||
4897 | return false; | |
4898 | } | |
4899 | ||
4900 | unsigned long i915_gem_obj_size(struct drm_i915_gem_object *o, | |
4901 | struct i915_address_space *vm) | |
4902 | { | |
4903 | struct drm_i915_private *dev_priv = o->base.dev->dev_private; | |
4904 | struct i915_vma *vma; | |
4905 | ||
4906 | if (vm == &dev_priv->mm.aliasing_ppgtt->base) | |
4907 | vm = &dev_priv->gtt.base; | |
4908 | ||
4909 | BUG_ON(list_empty(&o->vma_list)); | |
4910 | ||
4911 | list_for_each_entry(vma, &o->vma_list, vma_link) | |
4912 | if (vma->vm == vm) | |
4913 | return vma->node.size; | |
4914 | ||
4915 | return 0; | |
4916 | } |