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Merge branch 'drm-intel-next' of ssh://master.kernel.org/pub/scm/linux/kernel/git...
[mirror_ubuntu-focal-kernel.git] / drivers / gpu / drm / i915 / i915_gem.c
CommitLineData
673a394b
EA		 1/*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 *
26 */
27
28#include "drmP.h"
29#include "drm.h"
30#include "i915_drm.h"
31#include "i915_drv.h"
1c5d22f7 32#include "i915_trace.h"
652c393a 33#include "intel_drv.h"
5949eac4 34#include <linux/shmem_fs.h>
5a0e3ad6 35#include <linux/slab.h>
673a394b 36#include <linux/swap.h>
79e53945 37#include <linux/pci.h>
673a394b 38
88241785 39static __must_check int i915_gem_object_flush_gpu_write_domain(struct drm_i915_gem_object *obj);
05394f39
CW		 40static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj);
41static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj);
88241785
CW		 42static __must_check int i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj,
43 bool write);
44static __must_check int i915_gem_object_set_cpu_read_domain_range(struct drm_i915_gem_object *obj,
45 uint64_t offset,
46 uint64_t size);
05394f39 47static void i915_gem_object_set_to_full_cpu_read_domain(struct drm_i915_gem_object *obj);
88241785
CW		 48static __must_check int i915_gem_object_bind_to_gtt(struct drm_i915_gem_object *obj,
49 unsigned alignment,
50 bool map_and_fenceable);
d9e86c0e
CW		 51static void i915_gem_clear_fence_reg(struct drm_device *dev,
52 struct drm_i915_fence_reg *reg);
05394f39
CW		 53static int i915_gem_phys_pwrite(struct drm_device *dev,
54 struct drm_i915_gem_object *obj,
71acb5eb 55 struct drm_i915_gem_pwrite *args,
05394f39
CW		 56 struct drm_file *file);
57static void i915_gem_free_object_tail(struct drm_i915_gem_object *obj);
673a394b 58
17250b71 59static int i915_gem_inactive_shrink(struct shrinker *shrinker,
1495f230 60 struct shrink_control *sc);
31169714 61
73aa808f
CW		 62/* some bookkeeping */
63static void i915_gem_info_add_obj(struct drm_i915_private *dev_priv,
64 size_t size)
65{
66 dev_priv->mm.object_count++;
67 dev_priv->mm.object_memory += size;
68}
69
70static void i915_gem_info_remove_obj(struct drm_i915_private *dev_priv,
71 size_t size)
72{
73 dev_priv->mm.object_count--;
74 dev_priv->mm.object_memory -= size;
75}
76
21dd3734
CW		 77static int
78i915_gem_wait_for_error(struct drm_device *dev)
30dbf0c0
CW		 79{
80 struct drm_i915_private *dev_priv = dev->dev_private;
81 struct completion *x = &dev_priv->error_completion;
82 unsigned long flags;
83 int ret;
84
85 if (!atomic_read(&dev_priv->mm.wedged))
86 return 0;
87
88 ret = wait_for_completion_interruptible(x);
89 if (ret)
90 return ret;
91
21dd3734
CW		 92 if (atomic_read(&dev_priv->mm.wedged)) {
93 /* GPU is hung, bump the completion count to account for
94 * the token we just consumed so that we never hit zero and
95 * end up waiting upon a subsequent completion event that
96 * will never happen.
97 */
98 spin_lock_irqsave(&x->wait.lock, flags);
99 x->done++;
100 spin_unlock_irqrestore(&x->wait.lock, flags);
101 }
102 return 0;
30dbf0c0
CW		 103}
104
54cf91dc 105int i915_mutex_lock_interruptible(struct drm_device *dev)
76c1dec1 106{
76c1dec1
CW		 107 int ret;
108
21dd3734 109 ret = i915_gem_wait_for_error(dev);
76c1dec1
CW		 110 if (ret)
111 return ret;
112
113 ret = mutex_lock_interruptible(&dev->struct_mutex);
114 if (ret)
115 return ret;
116
23bc5982 117 WARN_ON(i915_verify_lists(dev));
76c1dec1
CW		 118 return 0;
119}
30dbf0c0 120
7d1c4804 121static inline bool
05394f39 122i915_gem_object_is_inactive(struct drm_i915_gem_object *obj)
7d1c4804 123{
05394f39 124 return obj->gtt_space && !obj->active && obj->pin_count == 0;
7d1c4804
CW		 125}
126
2021746e
CW		 127void i915_gem_do_init(struct drm_device *dev,
128 unsigned long start,
129 unsigned long mappable_end,
130 unsigned long end)
673a394b
EA		 131{
132 drm_i915_private_t *dev_priv = dev->dev_private;
673a394b 133
bee4a186 134 drm_mm_init(&dev_priv->mm.gtt_space, start, end - start);
673a394b 135
bee4a186
CW		 136 dev_priv->mm.gtt_start = start;
137 dev_priv->mm.gtt_mappable_end = mappable_end;
138 dev_priv->mm.gtt_end = end;
73aa808f 139 dev_priv->mm.gtt_total = end - start;
fb7d516a 140 dev_priv->mm.mappable_gtt_total = min(end, mappable_end) - start;
bee4a186
CW		 141
142 /* Take over this portion of the GTT */
143 intel_gtt_clear_range(start / PAGE_SIZE, (end-start) / PAGE_SIZE);
79e53945 144}
673a394b 145
79e53945
JB		 146int
147i915_gem_init_ioctl(struct drm_device *dev, void *data,
05394f39 148 struct drm_file *file)
79e53945
JB		 149{
150 struct drm_i915_gem_init *args = data;
2021746e
CW		 151
152 if (args->gtt_start >= args->gtt_end ||
153 (args->gtt_end | args->gtt_start) & (PAGE_SIZE - 1))
154 return -EINVAL;
79e53945
JB		 155
156 mutex_lock(&dev->struct_mutex);
2021746e 157 i915_gem_do_init(dev, args->gtt_start, args->gtt_end, args->gtt_end);
673a394b
EA		 158 mutex_unlock(&dev->struct_mutex);
159
2021746e 160 return 0;
673a394b
EA		 161}
162
5a125c3c
EA		 163int
164i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
05394f39 165 struct drm_file *file)
5a125c3c 166{
73aa808f 167 struct drm_i915_private *dev_priv = dev->dev_private;
5a125c3c 168 struct drm_i915_gem_get_aperture *args = data;
6299f992
CW		 169 struct drm_i915_gem_object *obj;
170 size_t pinned;
5a125c3c
EA		 171
172 if (!(dev->driver->driver_features & DRIVER_GEM))
173 return -ENODEV;
174
6299f992 175 pinned = 0;
73aa808f 176 mutex_lock(&dev->struct_mutex);
6299f992
CW		 177 list_for_each_entry(obj, &dev_priv->mm.pinned_list, mm_list)
178 pinned += obj->gtt_space->size;
73aa808f 179 mutex_unlock(&dev->struct_mutex);
5a125c3c 180
6299f992
CW		 181 args->aper_size = dev_priv->mm.gtt_total;
182 args->aper_available_size = args->aper_size -pinned;
183
5a125c3c
EA		 184 return 0;
185}
186
ff72145b
DA		 187static int
188i915_gem_create(struct drm_file *file,
189 struct drm_device *dev,
190 uint64_t size,
191 uint32_t *handle_p)
673a394b 192{
05394f39 193 struct drm_i915_gem_object *obj;
a1a2d1d3
PP		 194 int ret;
195 u32 handle;
673a394b 196
ff72145b 197 size = roundup(size, PAGE_SIZE);
673a394b
EA		 198
199 /* Allocate the new object */
ff72145b 200 obj = i915_gem_alloc_object(dev, size);
673a394b
EA		 201 if (obj == NULL)
202 return -ENOMEM;
203
05394f39 204 ret = drm_gem_handle_create(file, &obj->base, &handle);
1dfd9754 205 if (ret) {
05394f39
CW		 206 drm_gem_object_release(&obj->base);
207 i915_gem_info_remove_obj(dev->dev_private, obj->base.size);
202f2fef 208 kfree(obj);
673a394b 209 return ret;
1dfd9754 210 }
673a394b 211
202f2fef 212 /* drop reference from allocate - handle holds it now */
05394f39 213 drm_gem_object_unreference(&obj->base);
202f2fef
CW		 214 trace_i915_gem_object_create(obj);
215
ff72145b 216 *handle_p = handle;
673a394b
EA		 217 return 0;
218}
219
ff72145b
DA		 220int
221i915_gem_dumb_create(struct drm_file *file,
222 struct drm_device *dev,
223 struct drm_mode_create_dumb *args)
224{
225 /* have to work out size/pitch and return them */
ed0291fd 226 args->pitch = ALIGN(args->width * ((args->bpp + 7) / 8), 64);
ff72145b
DA		 227 args->size = args->pitch * args->height;
228 return i915_gem_create(file, dev,
229 args->size, &args->handle);
230}
231
232int i915_gem_dumb_destroy(struct drm_file *file,
233 struct drm_device *dev,
234 uint32_t handle)
235{
236 return drm_gem_handle_delete(file, handle);
237}
238
239/**
240 * Creates a new mm object and returns a handle to it.
241 */
242int
243i915_gem_create_ioctl(struct drm_device *dev, void *data,
244 struct drm_file *file)
245{
246 struct drm_i915_gem_create *args = data;
247 return i915_gem_create(file, dev,
248 args->size, &args->handle);
249}
250
05394f39 251static int i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj)
280b713b 252{
05394f39 253 drm_i915_private_t *dev_priv = obj->base.dev->dev_private;
280b713b
EA		 254
255 return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
05394f39 256 obj->tiling_mode != I915_TILING_NONE;
280b713b
EA		 257}
258
99a03df5 259static inline void
40123c1f
EA		 260slow_shmem_copy(struct page *dst_page,
261 int dst_offset,
262 struct page *src_page,
263 int src_offset,
264 int length)
265{
266 char *dst_vaddr, *src_vaddr;
267
99a03df5
CW		 268 dst_vaddr = kmap(dst_page);
269 src_vaddr = kmap(src_page);
40123c1f
EA		 270
271 memcpy(dst_vaddr + dst_offset, src_vaddr + src_offset, length);
272
99a03df5
CW		 273 kunmap(src_page);
274 kunmap(dst_page);
40123c1f
EA		 275}
276
99a03df5 277static inline void
280b713b
EA		 278slow_shmem_bit17_copy(struct page *gpu_page,
279 int gpu_offset,
280 struct page *cpu_page,
281 int cpu_offset,
282 int length,
283 int is_read)
284{
285 char *gpu_vaddr, *cpu_vaddr;
286
287 /* Use the unswizzled path if this page isn't affected. */
288 if ((page_to_phys(gpu_page) & (1 << 17)) == 0) {
289 if (is_read)
290 return slow_shmem_copy(cpu_page, cpu_offset,
291 gpu_page, gpu_offset, length);
292 else
293 return slow_shmem_copy(gpu_page, gpu_offset,
294 cpu_page, cpu_offset, length);
295 }
296
99a03df5
CW		 297 gpu_vaddr = kmap(gpu_page);
298 cpu_vaddr = kmap(cpu_page);
280b713b
EA		 299
300 /* Copy the data, XORing A6 with A17 (1). The user already knows he's
301 * XORing with the other bits (A9 for Y, A9 and A10 for X)
302 */
303 while (length > 0) {
304 int cacheline_end = ALIGN(gpu_offset + 1, 64);
305 int this_length = min(cacheline_end - gpu_offset, length);
306 int swizzled_gpu_offset = gpu_offset ^ 64;
307
308 if (is_read) {
309 memcpy(cpu_vaddr + cpu_offset,
310 gpu_vaddr + swizzled_gpu_offset,
311 this_length);
312 } else {
313 memcpy(gpu_vaddr + swizzled_gpu_offset,
314 cpu_vaddr + cpu_offset,
315 this_length);
316 }
317 cpu_offset += this_length;
318 gpu_offset += this_length;
319 length -= this_length;
320 }
321
99a03df5
CW		 322 kunmap(cpu_page);
323 kunmap(gpu_page);
280b713b
EA		 324}
325
eb01459f
EA		 326/**
327 * This is the fast shmem pread path, which attempts to copy_from_user directly
328 * from the backing pages of the object to the user's address space. On a
329 * fault, it fails so we can fall back to i915_gem_shmem_pwrite_slow().
330 */
331static int
05394f39
CW		 332i915_gem_shmem_pread_fast(struct drm_device *dev,
333 struct drm_i915_gem_object *obj,
eb01459f 334 struct drm_i915_gem_pread *args,
05394f39 335 struct drm_file *file)
eb01459f 336{
05394f39 337 struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping;
eb01459f 338 ssize_t remain;
e5281ccd 339 loff_t offset;
eb01459f
EA		 340 char __user *user_data;
341 int page_offset, page_length;
eb01459f
EA		 342
343 user_data = (char __user *) (uintptr_t) args->data_ptr;
344 remain = args->size;
345
eb01459f
EA		 346 offset = args->offset;
347
348 while (remain > 0) {
e5281ccd
CW		 349 struct page *page;
350 char *vaddr;
351 int ret;
352
eb01459f
EA		 353 /* Operation in this page
354 *
eb01459f
EA		 355 * page_offset = offset within page
356 * page_length = bytes to copy for this page
357 */
c8cbbb8b 358 page_offset = offset_in_page(offset);
eb01459f
EA		 359 page_length = remain;
360 if ((page_offset + remain) > PAGE_SIZE)
361 page_length = PAGE_SIZE - page_offset;
362
5949eac4 363 page = shmem_read_mapping_page(mapping, offset >> PAGE_SHIFT);
e5281ccd
CW		 364 if (IS_ERR(page))
365 return PTR_ERR(page);
366
367 vaddr = kmap_atomic(page);
368 ret = __copy_to_user_inatomic(user_data,
369 vaddr + page_offset,
370 page_length);
371 kunmap_atomic(vaddr);
372
373 mark_page_accessed(page);
374 page_cache_release(page);
375 if (ret)
4f27b75d 376 return -EFAULT;
eb01459f
EA		 377
378 remain -= page_length;
379 user_data += page_length;
380 offset += page_length;
381 }
382
4f27b75d 383 return 0;
eb01459f
EA		 384}
385
386/**
387 * This is the fallback shmem pread path, which allocates temporary storage
388 * in kernel space to copy_to_user into outside of the struct_mutex, so we
389 * can copy out of the object's backing pages while holding the struct mutex
390 * and not take page faults.
391 */
392static int
05394f39
CW		 393i915_gem_shmem_pread_slow(struct drm_device *dev,
394 struct drm_i915_gem_object *obj,
eb01459f 395 struct drm_i915_gem_pread *args,
05394f39 396 struct drm_file *file)
eb01459f 397{
05394f39 398 struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping;
eb01459f
EA		 399 struct mm_struct *mm = current->mm;
400 struct page **user_pages;
401 ssize_t remain;
402 loff_t offset, pinned_pages, i;
403 loff_t first_data_page, last_data_page, num_pages;
e5281ccd
CW		 404 int shmem_page_offset;
405 int data_page_index, data_page_offset;
eb01459f
EA		 406 int page_length;
407 int ret;
408 uint64_t data_ptr = args->data_ptr;
280b713b 409 int do_bit17_swizzling;
eb01459f
EA		 410
411 remain = args->size;
412
413 /* Pin the user pages containing the data. We can't fault while
414 * holding the struct mutex, yet we want to hold it while
415 * dereferencing the user data.
416 */
417 first_data_page = data_ptr / PAGE_SIZE;
418 last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE;
419 num_pages = last_data_page - first_data_page + 1;
420
4f27b75d 421 user_pages = drm_malloc_ab(num_pages, sizeof(struct page *));
eb01459f
EA		 422 if (user_pages == NULL)
423 return -ENOMEM;
424
4f27b75d 425 mutex_unlock(&dev->struct_mutex);
eb01459f
EA		 426 down_read(&mm->mmap_sem);
427 pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr,
e5e9ecde 428 num_pages, 1, 0, user_pages, NULL);
eb01459f 429 up_read(&mm->mmap_sem);
4f27b75d 430 mutex_lock(&dev->struct_mutex);
eb01459f
EA		 431 if (pinned_pages < num_pages) {
432 ret = -EFAULT;
4f27b75d 433 goto out;
eb01459f
EA		 434 }
435
4f27b75d
CW		 436 ret = i915_gem_object_set_cpu_read_domain_range(obj,
437 args->offset,
438 args->size);
07f73f69 439 if (ret)
4f27b75d 440 goto out;
eb01459f 441
4f27b75d 442 do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
eb01459f 443
eb01459f
EA		 444 offset = args->offset;
445
446 while (remain > 0) {
e5281ccd
CW		 447 struct page *page;
448
eb01459f
EA		 449 /* Operation in this page
450 *
eb01459f
EA		 451 * shmem_page_offset = offset within page in shmem file
452 * data_page_index = page number in get_user_pages return
453 * data_page_offset = offset with data_page_index page.
454 * page_length = bytes to copy for this page
455 */
c8cbbb8b 456 shmem_page_offset = offset_in_page(offset);
eb01459f 457 data_page_index = data_ptr / PAGE_SIZE - first_data_page;
c8cbbb8b 458 data_page_offset = offset_in_page(data_ptr);
eb01459f
EA		 459
460 page_length = remain;
461 if ((shmem_page_offset + page_length) > PAGE_SIZE)
462 page_length = PAGE_SIZE - shmem_page_offset;
463 if ((data_page_offset + page_length) > PAGE_SIZE)
464 page_length = PAGE_SIZE - data_page_offset;
465
5949eac4 466 page = shmem_read_mapping_page(mapping, offset >> PAGE_SHIFT);
b65552f0
JJ		 467 if (IS_ERR(page)) {
468 ret = PTR_ERR(page);
469 goto out;
470 }
e5281ccd 471
280b713b 472 if (do_bit17_swizzling) {
e5281ccd 473 slow_shmem_bit17_copy(page,
280b713b 474 shmem_page_offset,
99a03df5
CW		 475 user_pages[data_page_index],
476 data_page_offset,
477 page_length,
478 1);
479 } else {
480 slow_shmem_copy(user_pages[data_page_index],
481 data_page_offset,
e5281ccd 482 page,
99a03df5
CW		 483 shmem_page_offset,
484 page_length);
280b713b 485 }
eb01459f 486
e5281ccd
CW		 487 mark_page_accessed(page);
488 page_cache_release(page);
489
eb01459f
EA		 490 remain -= page_length;
491 data_ptr += page_length;
492 offset += page_length;
493 }
494
4f27b75d 495out:
eb01459f
EA		 496 for (i = 0; i < pinned_pages; i++) {
497 SetPageDirty(user_pages[i]);
e5281ccd 498 mark_page_accessed(user_pages[i]);
eb01459f
EA		 499 page_cache_release(user_pages[i]);
500 }
8e7d2b2c 501 drm_free_large(user_pages);
eb01459f
EA		 502
503 return ret;
504}
505
673a394b
EA		 506/**
507 * Reads data from the object referenced by handle.
508 *
509 * On error, the contents of *data are undefined.
510 */
511int
512i915_gem_pread_ioctl(struct drm_device *dev, void *data,
05394f39 513 struct drm_file *file)
673a394b
EA		 514{
515 struct drm_i915_gem_pread *args = data;
05394f39 516 struct drm_i915_gem_object *obj;
35b62a89 517 int ret = 0;
673a394b 518
51311d0a
CW		 519 if (args->size == 0)
520 return 0;
521
522 if (!access_ok(VERIFY_WRITE,
523 (char __user *)(uintptr_t)args->data_ptr,
524 args->size))
525 return -EFAULT;
526
527 ret = fault_in_pages_writeable((char __user *)(uintptr_t)args->data_ptr,
528 args->size);
529 if (ret)
530 return -EFAULT;
531
4f27b75d 532 ret = i915_mutex_lock_interruptible(dev);
1d7cfea1 533 if (ret)
4f27b75d 534 return ret;
673a394b 535
05394f39 536 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
c8725226 537 if (&obj->base == NULL) {
1d7cfea1
CW		 538 ret = -ENOENT;
539 goto unlock;
4f27b75d 540 }
673a394b 541
7dcd2499 542 /* Bounds check source. */
05394f39
CW		 543 if (args->offset > obj->base.size ||
544 args->size > obj->base.size - args->offset) {
ce9d419d 545 ret = -EINVAL;
35b62a89 546 goto out;
ce9d419d
CW		 547 }
548
db53a302
CW		 549 trace_i915_gem_object_pread(obj, args->offset, args->size);
550
4f27b75d
CW		 551 ret = i915_gem_object_set_cpu_read_domain_range(obj,
552 args->offset,
553 args->size);
554 if (ret)
e5281ccd 555 goto out;
4f27b75d
CW		 556
557 ret = -EFAULT;
558 if (!i915_gem_object_needs_bit17_swizzle(obj))
05394f39 559 ret = i915_gem_shmem_pread_fast(dev, obj, args, file);
4f27b75d 560 if (ret == -EFAULT)
05394f39 561 ret = i915_gem_shmem_pread_slow(dev, obj, args, file);
673a394b 562
35b62a89 563out:
05394f39 564 drm_gem_object_unreference(&obj->base);
1d7cfea1 565unlock:
4f27b75d 566 mutex_unlock(&dev->struct_mutex);
eb01459f 567 return ret;
673a394b
EA		 568}
569
0839ccb8
KP		 570/* This is the fast write path which cannot handle
571 * page faults in the source data
9b7530cc 572 */
0839ccb8
KP		 573
574static inline int
575fast_user_write(struct io_mapping *mapping,
576 loff_t page_base, int page_offset,
577 char __user *user_data,
578 int length)
9b7530cc 579{
9b7530cc 580 char *vaddr_atomic;
0839ccb8 581 unsigned long unwritten;
9b7530cc 582
3e4d3af5 583 vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base);
0839ccb8
KP		 584 unwritten = __copy_from_user_inatomic_nocache(vaddr_atomic + page_offset,
585 user_data, length);
3e4d3af5 586 io_mapping_unmap_atomic(vaddr_atomic);
fbd5a26d 587 return unwritten;
0839ccb8
KP		 588}
589
590/* Here's the write path which can sleep for
591 * page faults
592 */
593
ab34c226 594static inline void
3de09aa3
EA		 595slow_kernel_write(struct io_mapping *mapping,
596 loff_t gtt_base, int gtt_offset,
597 struct page *user_page, int user_offset,
598 int length)
0839ccb8 599{
ab34c226
CW		 600 char __iomem *dst_vaddr;
601 char *src_vaddr;
0839ccb8 602
ab34c226
CW		 603 dst_vaddr = io_mapping_map_wc(mapping, gtt_base);
604 src_vaddr = kmap(user_page);
605
606 memcpy_toio(dst_vaddr + gtt_offset,
607 src_vaddr + user_offset,
608 length);
609
610 kunmap(user_page);
611 io_mapping_unmap(dst_vaddr);
9b7530cc
LT		 612}
613
3de09aa3
EA		 614/**
615 * This is the fast pwrite path, where we copy the data directly from the
616 * user into the GTT, uncached.
617 */
673a394b 618static int
05394f39
CW		 619i915_gem_gtt_pwrite_fast(struct drm_device *dev,
620 struct drm_i915_gem_object *obj,
3de09aa3 621 struct drm_i915_gem_pwrite *args,
05394f39 622 struct drm_file *file)
673a394b 623{
0839ccb8 624 drm_i915_private_t *dev_priv = dev->dev_private;
673a394b 625 ssize_t remain;
0839ccb8 626 loff_t offset, page_base;
673a394b 627 char __user *user_data;
0839ccb8 628 int page_offset, page_length;
673a394b
EA		 629
630 user_data = (char __user *) (uintptr_t) args->data_ptr;
631 remain = args->size;
673a394b 632
05394f39 633 offset = obj->gtt_offset + args->offset;
673a394b
EA		 634
635 while (remain > 0) {
636 /* Operation in this page
637 *
0839ccb8
KP		 638 * page_base = page offset within aperture
639 * page_offset = offset within page
640 * page_length = bytes to copy for this page
673a394b 641 */
c8cbbb8b
CW		 642 page_base = offset & PAGE_MASK;
643 page_offset = offset_in_page(offset);
0839ccb8
KP		 644 page_length = remain;
645 if ((page_offset + remain) > PAGE_SIZE)
646 page_length = PAGE_SIZE - page_offset;
647
0839ccb8 648 /* If we get a fault while copying data, then (presumably) our
3de09aa3
EA		 649 * source page isn't available. Return the error and we'll
650 * retry in the slow path.
0839ccb8 651 */
fbd5a26d
CW		 652 if (fast_user_write(dev_priv->mm.gtt_mapping, page_base,
653 page_offset, user_data, page_length))
fbd5a26d 654 return -EFAULT;
673a394b 655
0839ccb8
KP		 656 remain -= page_length;
657 user_data += page_length;
658 offset += page_length;
673a394b 659 }
673a394b 660
fbd5a26d 661 return 0;
673a394b
EA		 662}
663
3de09aa3
EA		 664/**
665 * This is the fallback GTT pwrite path, which uses get_user_pages to pin
666 * the memory and maps it using kmap_atomic for copying.
667 *
668 * This code resulted in x11perf -rgb10text consuming about 10% more CPU
669 * than using i915_gem_gtt_pwrite_fast on a G45 (32-bit).
670 */
3043c60c 671static int
05394f39
CW		 672i915_gem_gtt_pwrite_slow(struct drm_device *dev,
673 struct drm_i915_gem_object *obj,
3de09aa3 674 struct drm_i915_gem_pwrite *args,
05394f39 675 struct drm_file *file)
673a394b 676{
3de09aa3
EA		 677 drm_i915_private_t *dev_priv = dev->dev_private;
678 ssize_t remain;
679 loff_t gtt_page_base, offset;
680 loff_t first_data_page, last_data_page, num_pages;
681 loff_t pinned_pages, i;
682 struct page **user_pages;
683 struct mm_struct *mm = current->mm;
684 int gtt_page_offset, data_page_offset, data_page_index, page_length;
673a394b 685 int ret;
3de09aa3
EA		 686 uint64_t data_ptr = args->data_ptr;
687
688 remain = args->size;
689
690 /* Pin the user pages containing the data. We can't fault while
691 * holding the struct mutex, and all of the pwrite implementations
692 * want to hold it while dereferencing the user data.
693 */
694 first_data_page = data_ptr / PAGE_SIZE;
695 last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE;
696 num_pages = last_data_page - first_data_page + 1;
697
fbd5a26d 698 user_pages = drm_malloc_ab(num_pages, sizeof(struct page *));
3de09aa3
EA		 699 if (user_pages == NULL)
700 return -ENOMEM;
701
fbd5a26d 702 mutex_unlock(&dev->struct_mutex);
3de09aa3
EA		 703 down_read(&mm->mmap_sem);
704 pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr,
705 num_pages, 0, 0, user_pages, NULL);
706 up_read(&mm->mmap_sem);
fbd5a26d 707 mutex_lock(&dev->struct_mutex);
3de09aa3
EA		 708 if (pinned_pages < num_pages) {
709 ret = -EFAULT;
710 goto out_unpin_pages;
711 }
673a394b 712
d9e86c0e
CW		 713 ret = i915_gem_object_set_to_gtt_domain(obj, true);
714 if (ret)
715 goto out_unpin_pages;
716
717 ret = i915_gem_object_put_fence(obj);
3de09aa3 718 if (ret)
fbd5a26d 719 goto out_unpin_pages;
3de09aa3 720
05394f39 721 offset = obj->gtt_offset + args->offset;
3de09aa3
EA		 722
723 while (remain > 0) {
724 /* Operation in this page
725 *
726 * gtt_page_base = page offset within aperture
727 * gtt_page_offset = offset within page in aperture
728 * data_page_index = page number in get_user_pages return
729 * data_page_offset = offset with data_page_index page.
730 * page_length = bytes to copy for this page
731 */
732 gtt_page_base = offset & PAGE_MASK;
c8cbbb8b 733 gtt_page_offset = offset_in_page(offset);
3de09aa3 734 data_page_index = data_ptr / PAGE_SIZE - first_data_page;
c8cbbb8b 735 data_page_offset = offset_in_page(data_ptr);
3de09aa3
EA		 736
737 page_length = remain;
738 if ((gtt_page_offset + page_length) > PAGE_SIZE)
739 page_length = PAGE_SIZE - gtt_page_offset;
740 if ((data_page_offset + page_length) > PAGE_SIZE)
741 page_length = PAGE_SIZE - data_page_offset;
742
ab34c226
CW		 743 slow_kernel_write(dev_priv->mm.gtt_mapping,
744 gtt_page_base, gtt_page_offset,
745 user_pages[data_page_index],
746 data_page_offset,
747 page_length);
3de09aa3
EA		 748
749 remain -= page_length;
750 offset += page_length;
751 data_ptr += page_length;
752 }
753
3de09aa3
EA		 754out_unpin_pages:
755 for (i = 0; i < pinned_pages; i++)
756 page_cache_release(user_pages[i]);
8e7d2b2c 757 drm_free_large(user_pages);
3de09aa3
EA		 758
759 return ret;
760}
761
40123c1f
EA		 762/**
763 * This is the fast shmem pwrite path, which attempts to directly
764 * copy_from_user into the kmapped pages backing the object.
765 */
3043c60c 766static int
05394f39
CW		 767i915_gem_shmem_pwrite_fast(struct drm_device *dev,
768 struct drm_i915_gem_object *obj,
40123c1f 769 struct drm_i915_gem_pwrite *args,
05394f39 770 struct drm_file *file)
673a394b 771{
05394f39 772 struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping;
40123c1f 773 ssize_t remain;
e5281ccd 774 loff_t offset;
40123c1f
EA		 775 char __user *user_data;
776 int page_offset, page_length;
40123c1f
EA		 777
778 user_data = (char __user *) (uintptr_t) args->data_ptr;
779 remain = args->size;
673a394b 780
40123c1f 781 offset = args->offset;
05394f39 782 obj->dirty = 1;
40123c1f
EA		 783
784 while (remain > 0) {
e5281ccd
CW		 785 struct page *page;
786 char *vaddr;
787 int ret;
788
40123c1f
EA		 789 /* Operation in this page
790 *
40123c1f
EA		 791 * page_offset = offset within page
792 * page_length = bytes to copy for this page
793 */
c8cbbb8b 794 page_offset = offset_in_page(offset);
40123c1f
EA		 795 page_length = remain;
796 if ((page_offset + remain) > PAGE_SIZE)
797 page_length = PAGE_SIZE - page_offset;
798
5949eac4 799 page = shmem_read_mapping_page(mapping, offset >> PAGE_SHIFT);
e5281ccd
CW		 800 if (IS_ERR(page))
801 return PTR_ERR(page);
802
803 vaddr = kmap_atomic(page, KM_USER0);
804 ret = __copy_from_user_inatomic(vaddr + page_offset,
805 user_data,
806 page_length);
807 kunmap_atomic(vaddr, KM_USER0);
808
809 set_page_dirty(page);
810 mark_page_accessed(page);
811 page_cache_release(page);
812
813 /* If we get a fault while copying data, then (presumably) our
814 * source page isn't available. Return the error and we'll
815 * retry in the slow path.
816 */
817 if (ret)
fbd5a26d 818 return -EFAULT;
40123c1f
EA		 819
820 remain -= page_length;
821 user_data += page_length;
822 offset += page_length;
823 }
824
fbd5a26d 825 return 0;
40123c1f
EA		 826}
827
828/**
829 * This is the fallback shmem pwrite path, which uses get_user_pages to pin
830 * the memory and maps it using kmap_atomic for copying.
831 *
832 * This avoids taking mmap_sem for faulting on the user's address while the
833 * struct_mutex is held.
834 */
835static int
05394f39
CW		 836i915_gem_shmem_pwrite_slow(struct drm_device *dev,
837 struct drm_i915_gem_object *obj,
40123c1f 838 struct drm_i915_gem_pwrite *args,
05394f39 839 struct drm_file *file)
40123c1f 840{
05394f39 841 struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping;
40123c1f
EA		 842 struct mm_struct *mm = current->mm;
843 struct page **user_pages;
844 ssize_t remain;
845 loff_t offset, pinned_pages, i;
846 loff_t first_data_page, last_data_page, num_pages;
e5281ccd 847 int shmem_page_offset;
40123c1f
EA		 848 int data_page_index, data_page_offset;
849 int page_length;
850 int ret;
851 uint64_t data_ptr = args->data_ptr;
280b713b 852 int do_bit17_swizzling;
40123c1f
EA		 853
854 remain = args->size;
855
856 /* Pin the user pages containing the data. We can't fault while
857 * holding the struct mutex, and all of the pwrite implementations
858 * want to hold it while dereferencing the user data.
859 */
860 first_data_page = data_ptr / PAGE_SIZE;
861 last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE;
862 num_pages = last_data_page - first_data_page + 1;
863
4f27b75d 864 user_pages = drm_malloc_ab(num_pages, sizeof(struct page *));
40123c1f
EA		 865 if (user_pages == NULL)
866 return -ENOMEM;
867
fbd5a26d 868 mutex_unlock(&dev->struct_mutex);
40123c1f
EA		 869 down_read(&mm->mmap_sem);
870 pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr,
871 num_pages, 0, 0, user_pages, NULL);
872 up_read(&mm->mmap_sem);
fbd5a26d 873 mutex_lock(&dev->struct_mutex);
40123c1f
EA		 874 if (pinned_pages < num_pages) {
875 ret = -EFAULT;
fbd5a26d 876 goto out;
673a394b
EA		 877 }
878
fbd5a26d 879 ret = i915_gem_object_set_to_cpu_domain(obj, 1);
07f73f69 880 if (ret)
fbd5a26d 881 goto out;
40123c1f 882
fbd5a26d 883 do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
40123c1f 884
673a394b 885 offset = args->offset;
05394f39 886 obj->dirty = 1;
673a394b 887
40123c1f 888 while (remain > 0) {
e5281ccd
CW		 889 struct page *page;
890
40123c1f
EA		 891 /* Operation in this page
892 *
40123c1f
EA		 893 * shmem_page_offset = offset within page in shmem file
894 * data_page_index = page number in get_user_pages return
895 * data_page_offset = offset with data_page_index page.
896 * page_length = bytes to copy for this page
897 */
c8cbbb8b 898 shmem_page_offset = offset_in_page(offset);
40123c1f 899 data_page_index = data_ptr / PAGE_SIZE - first_data_page;
c8cbbb8b 900 data_page_offset = offset_in_page(data_ptr);
40123c1f
EA		 901
902 page_length = remain;
903 if ((shmem_page_offset + page_length) > PAGE_SIZE)
904 page_length = PAGE_SIZE - shmem_page_offset;
905 if ((data_page_offset + page_length) > PAGE_SIZE)
906 page_length = PAGE_SIZE - data_page_offset;
907
5949eac4 908 page = shmem_read_mapping_page(mapping, offset >> PAGE_SHIFT);
e5281ccd
CW		 909 if (IS_ERR(page)) {
910 ret = PTR_ERR(page);
911 goto out;
912 }
913
280b713b 914 if (do_bit17_swizzling) {
e5281ccd 915 slow_shmem_bit17_copy(page,
280b713b
EA		 916 shmem_page_offset,
917 user_pages[data_page_index],
918 data_page_offset,
99a03df5
CW		 919 page_length,
920 0);
921 } else {
e5281ccd 922 slow_shmem_copy(page,
99a03df5
CW		 923 shmem_page_offset,
924 user_pages[data_page_index],
925 data_page_offset,
926 page_length);
280b713b 927 }
40123c1f 928
e5281ccd
CW		 929 set_page_dirty(page);
930 mark_page_accessed(page);
931 page_cache_release(page);
932
40123c1f
EA		 933 remain -= page_length;
934 data_ptr += page_length;
935 offset += page_length;
673a394b
EA		 936 }
937
fbd5a26d 938out:
40123c1f
EA		 939 for (i = 0; i < pinned_pages; i++)
940 page_cache_release(user_pages[i]);
8e7d2b2c 941 drm_free_large(user_pages);
673a394b 942
40123c1f 943 return ret;
673a394b
EA		 944}
945
946/**
947 * Writes data to the object referenced by handle.
948 *
949 * On error, the contents of the buffer that were to be modified are undefined.
950 */
951int
952i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
fbd5a26d 953 struct drm_file *file)
673a394b
EA		 954{
955 struct drm_i915_gem_pwrite *args = data;
05394f39 956 struct drm_i915_gem_object *obj;
51311d0a
CW		 957 int ret;
958
959 if (args->size == 0)
960 return 0;
961
962 if (!access_ok(VERIFY_READ,
963 (char __user *)(uintptr_t)args->data_ptr,
964 args->size))
965 return -EFAULT;
966
967 ret = fault_in_pages_readable((char __user *)(uintptr_t)args->data_ptr,
968 args->size);
969 if (ret)
970 return -EFAULT;
673a394b 971
fbd5a26d 972 ret = i915_mutex_lock_interruptible(dev);
1d7cfea1 973 if (ret)
fbd5a26d 974 return ret;
1d7cfea1 975
05394f39 976 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
c8725226 977 if (&obj->base == NULL) {
1d7cfea1
CW		 978 ret = -ENOENT;
979 goto unlock;
fbd5a26d 980 }
673a394b 981
7dcd2499 982 /* Bounds check destination. */
05394f39
CW		 983 if (args->offset > obj->base.size ||
984 args->size > obj->base.size - args->offset) {
ce9d419d 985 ret = -EINVAL;
35b62a89 986 goto out;
ce9d419d
CW		 987 }
988
db53a302
CW		 989 trace_i915_gem_object_pwrite(obj, args->offset, args->size);
990
673a394b
EA		 991 /* We can only do the GTT pwrite on untiled buffers, as otherwise
992 * it would end up going through the fenced access, and we'll get
993 * different detiling behavior between reading and writing.
994 * pread/pwrite currently are reading and writing from the CPU
995 * perspective, requiring manual detiling by the client.
996 */
05394f39 997 if (obj->phys_obj)
fbd5a26d 998 ret = i915_gem_phys_pwrite(dev, obj, args, file);
d9e86c0e 999 else if (obj->gtt_space &&
05394f39 1000 obj->base.write_domain != I915_GEM_DOMAIN_CPU) {
75e9e915 1001 ret = i915_gem_object_pin(obj, 0, true);
fbd5a26d
CW		 1002 if (ret)
1003 goto out;
1004
d9e86c0e
CW		 1005 ret = i915_gem_object_set_to_gtt_domain(obj, true);
1006 if (ret)
1007 goto out_unpin;
1008
1009 ret = i915_gem_object_put_fence(obj);
fbd5a26d
CW		 1010 if (ret)
1011 goto out_unpin;
1012
1013 ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file);
1014 if (ret == -EFAULT)
1015 ret = i915_gem_gtt_pwrite_slow(dev, obj, args, file);
1016
1017out_unpin:
1018 i915_gem_object_unpin(obj);
40123c1f 1019 } else {
fbd5a26d
CW		 1020 ret = i915_gem_object_set_to_cpu_domain(obj, 1);
1021 if (ret)
e5281ccd 1022 goto out;
673a394b 1023
fbd5a26d
CW		 1024 ret = -EFAULT;
1025 if (!i915_gem_object_needs_bit17_swizzle(obj))
1026 ret = i915_gem_shmem_pwrite_fast(dev, obj, args, file);
1027 if (ret == -EFAULT)
1028 ret = i915_gem_shmem_pwrite_slow(dev, obj, args, file);
fbd5a26d 1029 }
673a394b 1030
35b62a89 1031out:
05394f39 1032 drm_gem_object_unreference(&obj->base);
1d7cfea1 1033unlock:
fbd5a26d 1034 mutex_unlock(&dev->struct_mutex);
673a394b
EA		 1035 return ret;
1036}
1037
1038/**
2ef7eeaa
EA		 1039 * Called when user space prepares to use an object with the CPU, either
1040 * through the mmap ioctl's mapping or a GTT mapping.
673a394b
EA		 1041 */
1042int
1043i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
05394f39 1044 struct drm_file *file)
673a394b
EA		 1045{
1046 struct drm_i915_gem_set_domain *args = data;
05394f39 1047 struct drm_i915_gem_object *obj;
2ef7eeaa
EA		 1048 uint32_t read_domains = args->read_domains;
1049 uint32_t write_domain = args->write_domain;
673a394b
EA		 1050 int ret;
1051
1052 if (!(dev->driver->driver_features & DRIVER_GEM))
1053 return -ENODEV;
1054
2ef7eeaa 1055 /* Only handle setting domains to types used by the CPU. */
21d509e3 1056 if (write_domain & I915_GEM_GPU_DOMAINS)
2ef7eeaa
EA		 1057 return -EINVAL;
1058
21d509e3 1059 if (read_domains & I915_GEM_GPU_DOMAINS)
2ef7eeaa
EA		 1060 return -EINVAL;
1061
1062 /* Having something in the write domain implies it's in the read
1063 * domain, and only that read domain. Enforce that in the request.
1064 */
1065 if (write_domain != 0 && read_domains != write_domain)
1066 return -EINVAL;
1067
76c1dec1 1068 ret = i915_mutex_lock_interruptible(dev);
1d7cfea1 1069 if (ret)
76c1dec1 1070 return ret;
1d7cfea1 1071
05394f39 1072 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
c8725226 1073 if (&obj->base == NULL) {
1d7cfea1
CW		 1074 ret = -ENOENT;
1075 goto unlock;
76c1dec1 1076 }
673a394b 1077
2ef7eeaa
EA		 1078 if (read_domains & I915_GEM_DOMAIN_GTT) {
1079 ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0);
02354392
EA		 1080
1081 /* Silently promote "you're not bound, there was nothing to do"
1082 * to success, since the client was just asking us to
1083 * make sure everything was done.
1084 */
1085 if (ret == -EINVAL)
1086 ret = 0;
2ef7eeaa 1087 } else {
e47c68e9 1088 ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0);
2ef7eeaa
EA		 1089 }
1090
05394f39 1091 drm_gem_object_unreference(&obj->base);
1d7cfea1 1092unlock:
673a394b
EA		 1093 mutex_unlock(&dev->struct_mutex);
1094 return ret;
1095}
1096
1097/**
1098 * Called when user space has done writes to this buffer
1099 */
1100int
1101i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
05394f39 1102 struct drm_file *file)
673a394b
EA		 1103{
1104 struct drm_i915_gem_sw_finish *args = data;
05394f39 1105 struct drm_i915_gem_object *obj;
673a394b
EA		 1106 int ret = 0;
1107
1108 if (!(dev->driver->driver_features & DRIVER_GEM))
1109 return -ENODEV;
1110
76c1dec1 1111 ret = i915_mutex_lock_interruptible(dev);
1d7cfea1 1112 if (ret)
76c1dec1 1113 return ret;
1d7cfea1 1114
05394f39 1115 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
c8725226 1116 if (&obj->base == NULL) {
1d7cfea1
CW		 1117 ret = -ENOENT;
1118 goto unlock;
673a394b
EA		 1119 }
1120
673a394b 1121 /* Pinned buffers may be scanout, so flush the cache */
05394f39 1122 if (obj->pin_count)
e47c68e9
EA		 1123 i915_gem_object_flush_cpu_write_domain(obj);
1124
05394f39 1125 drm_gem_object_unreference(&obj->base);
1d7cfea1 1126unlock:
673a394b
EA		 1127 mutex_unlock(&dev->struct_mutex);
1128 return ret;
1129}
1130
1131/**
1132 * Maps the contents of an object, returning the address it is mapped
1133 * into.
1134 *
1135 * While the mapping holds a reference on the contents of the object, it doesn't
1136 * imply a ref on the object itself.
1137 */
1138int
1139i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
05394f39 1140 struct drm_file *file)
673a394b 1141{
da761a6e 1142 struct drm_i915_private *dev_priv = dev->dev_private;
673a394b
EA		 1143 struct drm_i915_gem_mmap *args = data;
1144 struct drm_gem_object *obj;
673a394b
EA		 1145 unsigned long addr;
1146
1147 if (!(dev->driver->driver_features & DRIVER_GEM))
1148 return -ENODEV;
1149
05394f39 1150 obj = drm_gem_object_lookup(dev, file, args->handle);
673a394b 1151 if (obj == NULL)
bf79cb91 1152 return -ENOENT;
673a394b 1153
da761a6e
CW		 1154 if (obj->size > dev_priv->mm.gtt_mappable_end) {
1155 drm_gem_object_unreference_unlocked(obj);
1156 return -E2BIG;
1157 }
1158
673a394b
EA		 1159 down_write(&current->mm->mmap_sem);
1160 addr = do_mmap(obj->filp, 0, args->size,
1161 PROT_READ | PROT_WRITE, MAP_SHARED,
1162 args->offset);
1163 up_write(&current->mm->mmap_sem);
bc9025bd 1164 drm_gem_object_unreference_unlocked(obj);
673a394b
EA		 1165 if (IS_ERR((void *)addr))
1166 return addr;
1167
1168 args->addr_ptr = (uint64_t) addr;
1169
1170 return 0;
1171}
1172
de151cf6
JB		 1173/**
1174 * i915_gem_fault - fault a page into the GTT
1175 * vma: VMA in question
1176 * vmf: fault info
1177 *
1178 * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
1179 * from userspace. The fault handler takes care of binding the object to
1180 * the GTT (if needed), allocating and programming a fence register (again,
1181 * only if needed based on whether the old reg is still valid or the object
1182 * is tiled) and inserting a new PTE into the faulting process.
1183 *
1184 * Note that the faulting process may involve evicting existing objects
1185 * from the GTT and/or fence registers to make room. So performance may
1186 * suffer if the GTT working set is large or there are few fence registers
1187 * left.
1188 */
1189int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
1190{
05394f39
CW		 1191 struct drm_i915_gem_object *obj = to_intel_bo(vma->vm_private_data);
1192 struct drm_device *dev = obj->base.dev;
7d1c4804 1193 drm_i915_private_t *dev_priv = dev->dev_private;
de151cf6
JB		 1194 pgoff_t page_offset;
1195 unsigned long pfn;
1196 int ret = 0;
0f973f27 1197 bool write = !!(vmf->flags & FAULT_FLAG_WRITE);
de151cf6
JB		 1198
1199 /* We don't use vmf->pgoff since that has the fake offset */
1200 page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >>
1201 PAGE_SHIFT;
1202
d9bc7e9f
CW		 1203 ret = i915_mutex_lock_interruptible(dev);
1204 if (ret)
1205 goto out;
a00b10c3 1206
db53a302
CW		 1207 trace_i915_gem_object_fault(obj, page_offset, true, write);
1208
d9bc7e9f 1209 /* Now bind it into the GTT if needed */
919926ae
CW		 1210 if (!obj->map_and_fenceable) {
1211 ret = i915_gem_object_unbind(obj);
1212 if (ret)
1213 goto unlock;
a00b10c3 1214 }
05394f39 1215 if (!obj->gtt_space) {
75e9e915 1216 ret = i915_gem_object_bind_to_gtt(obj, 0, true);
c715089f
CW		 1217 if (ret)
1218 goto unlock;
de151cf6 1219
e92d03bf
EA		 1220 ret = i915_gem_object_set_to_gtt_domain(obj, write);
1221 if (ret)
1222 goto unlock;
1223 }
4a684a41 1224
d9e86c0e
CW		 1225 if (obj->tiling_mode == I915_TILING_NONE)
1226 ret = i915_gem_object_put_fence(obj);
1227 else
ce453d81 1228 ret = i915_gem_object_get_fence(obj, NULL);
d9e86c0e
CW		 1229 if (ret)
1230 goto unlock;
de151cf6 1231
05394f39
CW		 1232 if (i915_gem_object_is_inactive(obj))
1233 list_move_tail(&obj->mm_list, &dev_priv->mm.inactive_list);
7d1c4804 1234
6299f992
CW		 1235 obj->fault_mappable = true;
1236
05394f39 1237 pfn = ((dev->agp->base + obj->gtt_offset) >> PAGE_SHIFT) +
de151cf6
JB		 1238 page_offset;
1239
1240 /* Finally, remap it using the new GTT offset */
1241 ret = vm_insert_pfn(vma, (unsigned long)vmf->virtual_address, pfn);
c715089f 1242unlock:
de151cf6 1243 mutex_unlock(&dev->struct_mutex);
d9bc7e9f 1244out:
de151cf6 1245 switch (ret) {
d9bc7e9f 1246 case -EIO:
045e769a 1247 case -EAGAIN:
d9bc7e9f
CW		 1248 /* Give the error handler a chance to run and move the
1249 * objects off the GPU active list. Next time we service the
1250 * fault, we should be able to transition the page into the
1251 * GTT without touching the GPU (and so avoid further
1252 * EIO/EGAIN). If the GPU is wedged, then there is no issue
1253 * with coherency, just lost writes.
1254 */
045e769a 1255 set_need_resched();
c715089f
CW		 1256 case 0:
1257 case -ERESTARTSYS:
bed636ab 1258 case -EINTR:
c715089f 1259 return VM_FAULT_NOPAGE;
de151cf6 1260 case -ENOMEM:
de151cf6 1261 return VM_FAULT_OOM;
de151cf6 1262 default:
c715089f 1263 return VM_FAULT_SIGBUS;
de151cf6
JB		 1264 }
1265}
1266
1267/**
1268 * i915_gem_create_mmap_offset - create a fake mmap offset for an object
1269 * @obj: obj in question
1270 *
1271 * GEM memory mapping works by handing back to userspace a fake mmap offset
1272 * it can use in a subsequent mmap(2) call. The DRM core code then looks
1273 * up the object based on the offset and sets up the various memory mapping
1274 * structures.
1275 *
1276 * This routine allocates and attaches a fake offset for @obj.
1277 */
1278static int
05394f39 1279i915_gem_create_mmap_offset(struct drm_i915_gem_object *obj)
de151cf6 1280{
05394f39 1281 struct drm_device *dev = obj->base.dev;
de151cf6 1282 struct drm_gem_mm *mm = dev->mm_private;
de151cf6 1283 struct drm_map_list *list;
f77d390c 1284 struct drm_local_map *map;
de151cf6
JB		 1285 int ret = 0;
1286
1287 /* Set the object up for mmap'ing */
05394f39 1288 list = &obj->base.map_list;
9a298b2a 1289 list->map = kzalloc(sizeof(struct drm_map_list), GFP_KERNEL);
de151cf6
JB		 1290 if (!list->map)
1291 return -ENOMEM;
1292
1293 map = list->map;
1294 map->type = _DRM_GEM;
05394f39 1295 map->size = obj->base.size;
de151cf6
JB		 1296 map->handle = obj;
1297
1298 /* Get a DRM GEM mmap offset allocated... */
1299 list->file_offset_node = drm_mm_search_free(&mm->offset_manager,
05394f39
CW		 1300 obj->base.size / PAGE_SIZE,
1301 0, 0);
de151cf6 1302 if (!list->file_offset_node) {
05394f39
CW		 1303 DRM_ERROR("failed to allocate offset for bo %d\n",
1304 obj->base.name);
9e0ae534 1305 ret = -ENOSPC;
de151cf6
JB		 1306 goto out_free_list;
1307 }
1308
1309 list->file_offset_node = drm_mm_get_block(list->file_offset_node,
05394f39
CW		 1310 obj->base.size / PAGE_SIZE,
1311 0);
de151cf6
JB		 1312 if (!list->file_offset_node) {
1313 ret = -ENOMEM;
1314 goto out_free_list;
1315 }
1316
1317 list->hash.key = list->file_offset_node->start;
9e0ae534
CW		 1318 ret = drm_ht_insert_item(&mm->offset_hash, &list->hash);
1319 if (ret) {
de151cf6
JB		 1320 DRM_ERROR("failed to add to map hash\n");
1321 goto out_free_mm;
1322 }
1323
de151cf6
JB		 1324 return 0;
1325
1326out_free_mm:
1327 drm_mm_put_block(list->file_offset_node);
1328out_free_list:
9a298b2a 1329 kfree(list->map);
39a01d1f 1330 list->map = NULL;
de151cf6
JB		 1331
1332 return ret;
1333}
1334
901782b2
CW		 1335/**
1336 * i915_gem_release_mmap - remove physical page mappings
1337 * @obj: obj in question
1338 *
af901ca1 1339 * Preserve the reservation of the mmapping with the DRM core code, but
901782b2
CW		 1340 * relinquish ownership of the pages back to the system.
1341 *
1342 * It is vital that we remove the page mapping if we have mapped a tiled
1343 * object through the GTT and then lose the fence register due to
1344 * resource pressure. Similarly if the object has been moved out of the
1345 * aperture, than pages mapped into userspace must be revoked. Removing the
1346 * mapping will then trigger a page fault on the next user access, allowing
1347 * fixup by i915_gem_fault().
1348 */
d05ca301 1349void
05394f39 1350i915_gem_release_mmap(struct drm_i915_gem_object *obj)
901782b2 1351{
6299f992
CW		 1352 if (!obj->fault_mappable)
1353 return;
901782b2 1354
f6e47884
CW		 1355 if (obj->base.dev->dev_mapping)
1356 unmap_mapping_range(obj->base.dev->dev_mapping,
1357 (loff_t)obj->base.map_list.hash.key<<PAGE_SHIFT,
1358 obj->base.size, 1);
fb7d516a 1359
6299f992 1360 obj->fault_mappable = false;
901782b2
CW		 1361}
1362
ab00b3e5 1363static void
05394f39 1364i915_gem_free_mmap_offset(struct drm_i915_gem_object *obj)
ab00b3e5 1365{
05394f39 1366 struct drm_device *dev = obj->base.dev;
ab00b3e5 1367 struct drm_gem_mm *mm = dev->mm_private;
05394f39 1368 struct drm_map_list *list = &obj->base.map_list;
ab00b3e5 1369
ab00b3e5 1370 drm_ht_remove_item(&mm->offset_hash, &list->hash);
39a01d1f
CW		 1371 drm_mm_put_block(list->file_offset_node);
1372 kfree(list->map);
1373 list->map = NULL;
ab00b3e5
JB		 1374}
1375
92b88aeb 1376static uint32_t
e28f8711 1377i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode)
92b88aeb 1378{
e28f8711 1379 uint32_t gtt_size;
92b88aeb
CW		 1380
1381 if (INTEL_INFO(dev)->gen >= 4 ||
e28f8711
CW		 1382 tiling_mode == I915_TILING_NONE)
1383 return size;
92b88aeb
CW		 1384
1385 /* Previous chips need a power-of-two fence region when tiling */
1386 if (INTEL_INFO(dev)->gen == 3)
e28f8711 1387 gtt_size = 1024*1024;
92b88aeb 1388 else
e28f8711 1389 gtt_size = 512*1024;
92b88aeb 1390
e28f8711
CW		 1391 while (gtt_size < size)
1392 gtt_size <<= 1;
92b88aeb 1393
e28f8711 1394 return gtt_size;
92b88aeb
CW		 1395}
1396
de151cf6
JB		 1397/**
1398 * i915_gem_get_gtt_alignment - return required GTT alignment for an object
1399 * @obj: object to check
1400 *
1401 * Return the required GTT alignment for an object, taking into account
5e783301 1402 * potential fence register mapping.
de151cf6
JB		 1403 */
1404static uint32_t
e28f8711
CW		 1405i915_gem_get_gtt_alignment(struct drm_device *dev,
1406 uint32_t size,
1407 int tiling_mode)
de151cf6 1408{
de151cf6
JB		 1409 /*
1410 * Minimum alignment is 4k (GTT page size), but might be greater
1411 * if a fence register is needed for the object.
1412 */
a00b10c3 1413 if (INTEL_INFO(dev)->gen >= 4 ||
e28f8711 1414 tiling_mode == I915_TILING_NONE)
de151cf6
JB		 1415 return 4096;
1416
a00b10c3
CW		 1417 /*
1418 * Previous chips need to be aligned to the size of the smallest
1419 * fence register that can contain the object.
1420 */
e28f8711 1421 return i915_gem_get_gtt_size(dev, size, tiling_mode);
a00b10c3
CW		 1422}
1423
5e783301
DV		 1424/**
1425 * i915_gem_get_unfenced_gtt_alignment - return required GTT alignment for an
1426 * unfenced object
e28f8711
CW		 1427 * @dev: the device
1428 * @size: size of the object
1429 * @tiling_mode: tiling mode of the object
5e783301
DV		 1430 *
1431 * Return the required GTT alignment for an object, only taking into account
1432 * unfenced tiled surface requirements.
1433 */
467cffba 1434uint32_t
e28f8711
CW		 1435i915_gem_get_unfenced_gtt_alignment(struct drm_device *dev,
1436 uint32_t size,
1437 int tiling_mode)
5e783301 1438{
5e783301
DV		 1439 /*
1440 * Minimum alignment is 4k (GTT page size) for sane hw.
1441 */
1442 if (INTEL_INFO(dev)->gen >= 4 || IS_G33(dev) ||
e28f8711 1443 tiling_mode == I915_TILING_NONE)
5e783301
DV		 1444 return 4096;
1445
e28f8711
CW		 1446 /* Previous hardware however needs to be aligned to a power-of-two
1447 * tile height. The simplest method for determining this is to reuse
1448 * the power-of-tile object size.
5e783301 1449 */
e28f8711 1450 return i915_gem_get_gtt_size(dev, size, tiling_mode);
5e783301
DV		 1451}
1452
de151cf6 1453int
ff72145b
DA		 1454i915_gem_mmap_gtt(struct drm_file *file,
1455 struct drm_device *dev,
1456 uint32_t handle,
1457 uint64_t *offset)
de151cf6 1458{
da761a6e 1459 struct drm_i915_private *dev_priv = dev->dev_private;
05394f39 1460 struct drm_i915_gem_object *obj;
de151cf6
JB		 1461 int ret;
1462
1463 if (!(dev->driver->driver_features & DRIVER_GEM))
1464 return -ENODEV;
1465
76c1dec1 1466 ret = i915_mutex_lock_interruptible(dev);
1d7cfea1 1467 if (ret)
76c1dec1 1468 return ret;
de151cf6 1469
ff72145b 1470 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
c8725226 1471 if (&obj->base == NULL) {
1d7cfea1
CW		 1472 ret = -ENOENT;
1473 goto unlock;
1474 }
de151cf6 1475
05394f39 1476 if (obj->base.size > dev_priv->mm.gtt_mappable_end) {
da761a6e
CW		 1477 ret = -E2BIG;
1478 goto unlock;
1479 }
1480
05394f39 1481 if (obj->madv != I915_MADV_WILLNEED) {
ab18282d 1482 DRM_ERROR("Attempting to mmap a purgeable buffer\n");
1d7cfea1
CW		 1483 ret = -EINVAL;
1484 goto out;
ab18282d
CW		 1485 }
1486
05394f39 1487 if (!obj->base.map_list.map) {
de151cf6 1488 ret = i915_gem_create_mmap_offset(obj);
1d7cfea1
CW		 1489 if (ret)
1490 goto out;
de151cf6
JB		 1491 }
1492
ff72145b 1493 *offset = (u64)obj->base.map_list.hash.key << PAGE_SHIFT;
de151cf6 1494
1d7cfea1 1495out:
05394f39 1496 drm_gem_object_unreference(&obj->base);
1d7cfea1 1497unlock:
de151cf6 1498 mutex_unlock(&dev->struct_mutex);
1d7cfea1 1499 return ret;
de151cf6
JB		 1500}
1501
ff72145b
DA		 1502/**
1503 * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
1504 * @dev: DRM device
1505 * @data: GTT mapping ioctl data
1506 * @file: GEM object info
1507 *
1508 * Simply returns the fake offset to userspace so it can mmap it.
1509 * The mmap call will end up in drm_gem_mmap(), which will set things
1510 * up so we can get faults in the handler above.
1511 *
1512 * The fault handler will take care of binding the object into the GTT
1513 * (since it may have been evicted to make room for something), allocating
1514 * a fence register, and mapping the appropriate aperture address into
1515 * userspace.
1516 */
1517int
1518i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
1519 struct drm_file *file)
1520{
1521 struct drm_i915_gem_mmap_gtt *args = data;
1522
1523 if (!(dev->driver->driver_features & DRIVER_GEM))
1524 return -ENODEV;
1525
1526 return i915_gem_mmap_gtt(file, dev, args->handle, &args->offset);
1527}
1528
1529
e5281ccd 1530static int
05394f39 1531i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj,
e5281ccd
CW		 1532 gfp_t gfpmask)
1533{
e5281ccd
CW		 1534 int page_count, i;
1535 struct address_space *mapping;
1536 struct inode *inode;
1537 struct page *page;
1538
1539 /* Get the list of pages out of our struct file. They'll be pinned
1540 * at this point until we release them.
1541 */
05394f39
CW		 1542 page_count = obj->base.size / PAGE_SIZE;
1543 BUG_ON(obj->pages != NULL);
1544 obj->pages = drm_malloc_ab(page_count, sizeof(struct page *));
1545 if (obj->pages == NULL)
e5281ccd
CW		 1546 return -ENOMEM;
1547
05394f39 1548 inode = obj->base.filp->f_path.dentry->d_inode;
e5281ccd 1549 mapping = inode->i_mapping;
5949eac4
HD		 1550 gfpmask |= mapping_gfp_mask(mapping);
1551
e5281ccd 1552 for (i = 0; i < page_count; i++) {
5949eac4 1553 page = shmem_read_mapping_page_gfp(mapping, i, gfpmask);
e5281ccd
CW		 1554 if (IS_ERR(page))
1555 goto err_pages;
1556
05394f39 1557 obj->pages[i] = page;
e5281ccd
CW		 1558 }
1559
05394f39 1560 if (obj->tiling_mode != I915_TILING_NONE)
e5281ccd
CW		 1561 i915_gem_object_do_bit_17_swizzle(obj);
1562
1563 return 0;
1564
1565err_pages:
1566 while (i--)
05394f39 1567 page_cache_release(obj->pages[i]);
e5281ccd 1568
05394f39
CW		 1569 drm_free_large(obj->pages);
1570 obj->pages = NULL;
e5281ccd
CW		 1571 return PTR_ERR(page);
1572}
1573
5cdf5881 1574static void
05394f39 1575i915_gem_object_put_pages_gtt(struct drm_i915_gem_object *obj)
673a394b 1576{
05394f39 1577 int page_count = obj->base.size / PAGE_SIZE;
673a394b
EA		 1578 int i;
1579
05394f39 1580 BUG_ON(obj->madv == __I915_MADV_PURGED);
673a394b 1581
05394f39 1582 if (obj->tiling_mode != I915_TILING_NONE)
280b713b
EA		 1583 i915_gem_object_save_bit_17_swizzle(obj);
1584
05394f39
CW		 1585 if (obj->madv == I915_MADV_DONTNEED)
1586 obj->dirty = 0;
3ef94daa
CW		 1587
1588 for (i = 0; i < page_count; i++) {
05394f39
CW		 1589 if (obj->dirty)
1590 set_page_dirty(obj->pages[i]);
3ef94daa 1591
05394f39
CW		 1592 if (obj->madv == I915_MADV_WILLNEED)
1593 mark_page_accessed(obj->pages[i]);
3ef94daa 1594
05394f39 1595 page_cache_release(obj->pages[i]);
3ef94daa 1596 }
05394f39 1597 obj->dirty = 0;
673a394b 1598
05394f39
CW		 1599 drm_free_large(obj->pages);
1600 obj->pages = NULL;
673a394b
EA		 1601}
1602
54cf91dc 1603void
05394f39 1604i915_gem_object_move_to_active(struct drm_i915_gem_object *obj,
1ec14ad3
CW		 1605 struct intel_ring_buffer *ring,
1606 u32 seqno)
673a394b 1607{
05394f39 1608 struct drm_device *dev = obj->base.dev;
69dc4987 1609 struct drm_i915_private *dev_priv = dev->dev_private;
617dbe27 1610
852835f3 1611 BUG_ON(ring == NULL);
05394f39 1612 obj->ring = ring;
673a394b
EA		 1613
1614 /* Add a reference if we're newly entering the active list. */
05394f39
CW		 1615 if (!obj->active) {
1616 drm_gem_object_reference(&obj->base);
1617 obj->active = 1;
673a394b 1618 }
e35a41de 1619
673a394b 1620 /* Move from whatever list we were on to the tail of execution. */
05394f39
CW		 1621 list_move_tail(&obj->mm_list, &dev_priv->mm.active_list);
1622 list_move_tail(&obj->ring_list, &ring->active_list);
caea7476 1623
05394f39 1624 obj->last_rendering_seqno = seqno;
caea7476
CW		 1625 if (obj->fenced_gpu_access) {
1626 struct drm_i915_fence_reg *reg;
1627
1628 BUG_ON(obj->fence_reg == I915_FENCE_REG_NONE);
1629
1630 obj->last_fenced_seqno = seqno;
1631 obj->last_fenced_ring = ring;
1632
1633 reg = &dev_priv->fence_regs[obj->fence_reg];
1634 list_move_tail(&reg->lru_list, &dev_priv->mm.fence_list);
1635 }
1636}
1637
1638static void
1639i915_gem_object_move_off_active(struct drm_i915_gem_object *obj)
1640{
1641 list_del_init(&obj->ring_list);
1642 obj->last_rendering_seqno = 0;
673a394b
EA		 1643}
1644
ce44b0ea 1645static void
05394f39 1646i915_gem_object_move_to_flushing(struct drm_i915_gem_object *obj)
ce44b0ea 1647{
05394f39 1648 struct drm_device *dev = obj->base.dev;
ce44b0ea 1649 drm_i915_private_t *dev_priv = dev->dev_private;
ce44b0ea 1650
05394f39
CW		 1651 BUG_ON(!obj->active);
1652 list_move_tail(&obj->mm_list, &dev_priv->mm.flushing_list);
caea7476
CW		 1653
1654 i915_gem_object_move_off_active(obj);
1655}
1656
1657static void
1658i915_gem_object_move_to_inactive(struct drm_i915_gem_object *obj)
1659{
1660 struct drm_device *dev = obj->base.dev;
1661 struct drm_i915_private *dev_priv = dev->dev_private;
1662
1663 if (obj->pin_count != 0)
1664 list_move_tail(&obj->mm_list, &dev_priv->mm.pinned_list);
1665 else
1666 list_move_tail(&obj->mm_list, &dev_priv->mm.inactive_list);
1667
1668 BUG_ON(!list_empty(&obj->gpu_write_list));
1669 BUG_ON(!obj->active);
1670 obj->ring = NULL;
1671
1672 i915_gem_object_move_off_active(obj);
1673 obj->fenced_gpu_access = false;
caea7476
CW		 1674
1675 obj->active = 0;
87ca9c8a 1676 obj->pending_gpu_write = false;
caea7476
CW		 1677 drm_gem_object_unreference(&obj->base);
1678
1679 WARN_ON(i915_verify_lists(dev));
ce44b0ea 1680}
673a394b 1681
963b4836
CW		 1682/* Immediately discard the backing storage */
1683static void
05394f39 1684i915_gem_object_truncate(struct drm_i915_gem_object *obj)
963b4836 1685{
bb6baf76 1686 struct inode *inode;
963b4836 1687
ae9fed6b
CW		 1688 /* Our goal here is to return as much of the memory as
1689 * is possible back to the system as we are called from OOM.
1690 * To do this we must instruct the shmfs to drop all of its
e2377fe0 1691 * backing pages, *now*.
ae9fed6b 1692 */
05394f39 1693 inode = obj->base.filp->f_path.dentry->d_inode;
e2377fe0 1694 shmem_truncate_range(inode, 0, (loff_t)-1);
bb6baf76 1695
05394f39 1696 obj->madv = __I915_MADV_PURGED;
963b4836
CW		 1697}
1698
1699static inline int
05394f39 1700i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj)
963b4836 1701{
05394f39 1702 return obj->madv == I915_MADV_DONTNEED;
963b4836
CW		 1703}
1704
63560396 1705static void
db53a302
CW		 1706i915_gem_process_flushing_list(struct intel_ring_buffer *ring,
1707 uint32_t flush_domains)
63560396 1708{
05394f39 1709 struct drm_i915_gem_object *obj, *next;
63560396 1710
05394f39 1711 list_for_each_entry_safe(obj, next,
64193406 1712 &ring->gpu_write_list,
63560396 1713 gpu_write_list) {
05394f39
CW		 1714 if (obj->base.write_domain & flush_domains) {
1715 uint32_t old_write_domain = obj->base.write_domain;
63560396 1716
05394f39
CW		 1717 obj->base.write_domain = 0;
1718 list_del_init(&obj->gpu_write_list);
1ec14ad3 1719 i915_gem_object_move_to_active(obj, ring,
db53a302 1720 i915_gem_next_request_seqno(ring));
63560396 1721
63560396 1722 trace_i915_gem_object_change_domain(obj,
05394f39 1723 obj->base.read_domains,
63560396
DV		 1724 old_write_domain);
1725 }
1726 }
1727}
8187a2b7 1728
3cce469c 1729int
db53a302 1730i915_add_request(struct intel_ring_buffer *ring,
f787a5f5 1731 struct drm_file *file,
db53a302 1732 struct drm_i915_gem_request *request)
673a394b 1733{
db53a302 1734 drm_i915_private_t *dev_priv = ring->dev->dev_private;
673a394b
EA		 1735 uint32_t seqno;
1736 int was_empty;
3cce469c
CW		 1737 int ret;
1738
1739 BUG_ON(request == NULL);
673a394b 1740
3cce469c
CW		 1741 ret = ring->add_request(ring, &seqno);
1742 if (ret)
1743 return ret;
673a394b 1744
db53a302 1745 trace_i915_gem_request_add(ring, seqno);
673a394b
EA		 1746
1747 request->seqno = seqno;
852835f3 1748 request->ring = ring;
673a394b 1749 request->emitted_jiffies = jiffies;
852835f3
ZN		 1750 was_empty = list_empty(&ring->request_list);
1751 list_add_tail(&request->list, &ring->request_list);
1752
db53a302
CW		 1753 if (file) {
1754 struct drm_i915_file_private *file_priv = file->driver_priv;
1755
1c25595f 1756 spin_lock(&file_priv->mm.lock);
f787a5f5 1757 request->file_priv = file_priv;
b962442e 1758 list_add_tail(&request->client_list,
f787a5f5 1759 &file_priv->mm.request_list);
1c25595f 1760 spin_unlock(&file_priv->mm.lock);
b962442e 1761 }
673a394b 1762
db53a302
CW		 1763 ring->outstanding_lazy_request = false;
1764
f65d9421 1765 if (!dev_priv->mm.suspended) {
3e0dc6b0
BW		 1766 if (i915_enable_hangcheck) {
1767 mod_timer(&dev_priv->hangcheck_timer,
1768 jiffies +
1769 msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD));
1770 }
f65d9421 1771 if (was_empty)
b3b079db
CW		 1772 queue_delayed_work(dev_priv->wq,
1773 &dev_priv->mm.retire_work, HZ);
f65d9421 1774 }
3cce469c 1775 return 0;
673a394b
EA		 1776}
1777
f787a5f5
CW		 1778static inline void
1779i915_gem_request_remove_from_client(struct drm_i915_gem_request *request)
673a394b 1780{
1c25595f 1781 struct drm_i915_file_private *file_priv = request->file_priv;
673a394b 1782
1c25595f
CW		 1783 if (!file_priv)
1784 return;
1c5d22f7 1785
1c25595f 1786 spin_lock(&file_priv->mm.lock);
09bfa517
HRK		 1787 if (request->file_priv) {
1788 list_del(&request->client_list);
1789 request->file_priv = NULL;
1790 }
1c25595f 1791 spin_unlock(&file_priv->mm.lock);
673a394b 1792}
673a394b 1793
dfaae392
CW		 1794static void i915_gem_reset_ring_lists(struct drm_i915_private *dev_priv,
1795 struct intel_ring_buffer *ring)
9375e446 1796{
dfaae392
CW		 1797 while (!list_empty(&ring->request_list)) {
1798 struct drm_i915_gem_request *request;
673a394b 1799
dfaae392
CW		 1800 request = list_first_entry(&ring->request_list,
1801 struct drm_i915_gem_request,
1802 list);
de151cf6 1803
dfaae392 1804 list_del(&request->list);
f787a5f5 1805 i915_gem_request_remove_from_client(request);
dfaae392
CW		 1806 kfree(request);
1807 }
673a394b 1808
dfaae392 1809 while (!list_empty(&ring->active_list)) {
05394f39 1810 struct drm_i915_gem_object *obj;
9375e446 1811
05394f39
CW		 1812 obj = list_first_entry(&ring->active_list,
1813 struct drm_i915_gem_object,
1814 ring_list);
9375e446 1815
05394f39
CW		 1816 obj->base.write_domain = 0;
1817 list_del_init(&obj->gpu_write_list);
1818 i915_gem_object_move_to_inactive(obj);
673a394b
EA		 1819 }
1820}
1821
312817a3
CW		 1822static void i915_gem_reset_fences(struct drm_device *dev)
1823{
1824 struct drm_i915_private *dev_priv = dev->dev_private;
1825 int i;
1826
1827 for (i = 0; i < 16; i++) {
1828 struct drm_i915_fence_reg *reg = &dev_priv->fence_regs[i];
7d2cb39c
CW		 1829 struct drm_i915_gem_object *obj = reg->obj;
1830
1831 if (!obj)
1832 continue;
1833
1834 if (obj->tiling_mode)
1835 i915_gem_release_mmap(obj);
1836
d9e86c0e
CW		 1837 reg->obj->fence_reg = I915_FENCE_REG_NONE;
1838 reg->obj->fenced_gpu_access = false;
1839 reg->obj->last_fenced_seqno = 0;
1840 reg->obj->last_fenced_ring = NULL;
1841 i915_gem_clear_fence_reg(dev, reg);
312817a3
CW		 1842 }
1843}
1844
069efc1d 1845void i915_gem_reset(struct drm_device *dev)
673a394b 1846{
77f01230 1847 struct drm_i915_private *dev_priv = dev->dev_private;
05394f39 1848 struct drm_i915_gem_object *obj;
1ec14ad3 1849 int i;
673a394b 1850
1ec14ad3
CW		 1851 for (i = 0; i < I915_NUM_RINGS; i++)
1852 i915_gem_reset_ring_lists(dev_priv, &dev_priv->ring[i]);
dfaae392
CW		 1853
1854 /* Remove anything from the flushing lists. The GPU cache is likely
1855 * to be lost on reset along with the data, so simply move the
1856 * lost bo to the inactive list.
1857 */
1858 while (!list_empty(&dev_priv->mm.flushing_list)) {
05394f39
CW		 1859 obj= list_first_entry(&dev_priv->mm.flushing_list,
1860 struct drm_i915_gem_object,
1861 mm_list);
dfaae392 1862
05394f39
CW		 1863 obj->base.write_domain = 0;
1864 list_del_init(&obj->gpu_write_list);
1865 i915_gem_object_move_to_inactive(obj);
dfaae392
CW		 1866 }
1867
1868 /* Move everything out of the GPU domains to ensure we do any
1869 * necessary invalidation upon reuse.
1870 */
05394f39 1871 list_for_each_entry(obj,
77f01230 1872 &dev_priv->mm.inactive_list,
69dc4987 1873 mm_list)
77f01230 1874 {
05394f39 1875 obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS;
77f01230 1876 }
069efc1d
CW		 1877
1878 /* The fence registers are invalidated so clear them out */
312817a3 1879 i915_gem_reset_fences(dev);
673a394b
EA		 1880}
1881
1882/**
1883 * This function clears the request list as sequence numbers are passed.
1884 */
b09a1fec 1885static void
db53a302 1886i915_gem_retire_requests_ring(struct intel_ring_buffer *ring)
673a394b 1887{
673a394b 1888 uint32_t seqno;
1ec14ad3 1889 int i;
673a394b 1890
db53a302 1891 if (list_empty(&ring->request_list))
6c0594a3
KW		 1892 return;
1893
db53a302 1894 WARN_ON(i915_verify_lists(ring->dev));
673a394b 1895
78501eac 1896 seqno = ring->get_seqno(ring);
1ec14ad3 1897
076e2c0e 1898 for (i = 0; i < ARRAY_SIZE(ring->sync_seqno); i++)
1ec14ad3
CW		 1899 if (seqno >= ring->sync_seqno[i])
1900 ring->sync_seqno[i] = 0;
1901
852835f3 1902 while (!list_empty(&ring->request_list)) {
673a394b 1903 struct drm_i915_gem_request *request;
673a394b 1904
852835f3 1905 request = list_first_entry(&ring->request_list,
673a394b
EA		 1906 struct drm_i915_gem_request,
1907 list);
673a394b 1908
dfaae392 1909 if (!i915_seqno_passed(seqno, request->seqno))
b84d5f0c
CW		 1910 break;
1911
db53a302 1912 trace_i915_gem_request_retire(ring, request->seqno);
b84d5f0c
CW		 1913
1914 list_del(&request->list);
f787a5f5 1915 i915_gem_request_remove_from_client(request);
b84d5f0c
CW		 1916 kfree(request);
1917 }
673a394b 1918
b84d5f0c
CW		 1919 /* Move any buffers on the active list that are no longer referenced
1920 * by the ringbuffer to the flushing/inactive lists as appropriate.
1921 */
1922 while (!list_empty(&ring->active_list)) {
05394f39 1923 struct drm_i915_gem_object *obj;
b84d5f0c 1924
05394f39
CW		 1925 obj= list_first_entry(&ring->active_list,
1926 struct drm_i915_gem_object,
1927 ring_list);
673a394b 1928
05394f39 1929 if (!i915_seqno_passed(seqno, obj->last_rendering_seqno))
673a394b 1930 break;
b84d5f0c 1931
05394f39 1932 if (obj->base.write_domain != 0)
b84d5f0c
CW		 1933 i915_gem_object_move_to_flushing(obj);
1934 else
1935 i915_gem_object_move_to_inactive(obj);
673a394b 1936 }
9d34e5db 1937
db53a302
CW		 1938 if (unlikely(ring->trace_irq_seqno &&
1939 i915_seqno_passed(seqno, ring->trace_irq_seqno))) {
1ec14ad3 1940 ring->irq_put(ring);
db53a302 1941 ring->trace_irq_seqno = 0;
9d34e5db 1942 }
23bc5982 1943
db53a302 1944 WARN_ON(i915_verify_lists(ring->dev));
673a394b
EA		 1945}
1946
b09a1fec
CW		 1947void
1948i915_gem_retire_requests(struct drm_device *dev)
1949{
1950 drm_i915_private_t *dev_priv = dev->dev_private;
1ec14ad3 1951 int i;
b09a1fec 1952
be72615b 1953 if (!list_empty(&dev_priv->mm.deferred_free_list)) {
05394f39 1954 struct drm_i915_gem_object *obj, *next;
be72615b
CW		 1955
1956 /* We must be careful that during unbind() we do not
1957 * accidentally infinitely recurse into retire requests.
1958 * Currently:
1959 * retire -> free -> unbind -> wait -> retire_ring
1960 */
05394f39 1961 list_for_each_entry_safe(obj, next,
be72615b 1962 &dev_priv->mm.deferred_free_list,
69dc4987 1963 mm_list)
05394f39 1964 i915_gem_free_object_tail(obj);
be72615b
CW		 1965 }
1966
1ec14ad3 1967 for (i = 0; i < I915_NUM_RINGS; i++)
db53a302 1968 i915_gem_retire_requests_ring(&dev_priv->ring[i]);
b09a1fec
CW		 1969}
1970
75ef9da2 1971static void
673a394b
EA		 1972i915_gem_retire_work_handler(struct work_struct *work)
1973{
1974 drm_i915_private_t *dev_priv;
1975 struct drm_device *dev;
0a58705b
CW		 1976 bool idle;
1977 int i;
673a394b
EA		 1978
1979 dev_priv = container_of(work, drm_i915_private_t,
1980 mm.retire_work.work);
1981 dev = dev_priv->dev;
1982
891b48cf
CW		 1983 /* Come back later if the device is busy... */
1984 if (!mutex_trylock(&dev->struct_mutex)) {
1985 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ);
1986 return;
1987 }
1988
b09a1fec 1989 i915_gem_retire_requests(dev);
d1b851fc 1990
0a58705b
CW		 1991 /* Send a periodic flush down the ring so we don't hold onto GEM
1992 * objects indefinitely.
1993 */
1994 idle = true;
1995 for (i = 0; i < I915_NUM_RINGS; i++) {
1996 struct intel_ring_buffer *ring = &dev_priv->ring[i];
1997
1998 if (!list_empty(&ring->gpu_write_list)) {
1999 struct drm_i915_gem_request *request;
2000 int ret;
2001
db53a302
CW		 2002 ret = i915_gem_flush_ring(ring,
2003 0, I915_GEM_GPU_DOMAINS);
0a58705b
CW		 2004 request = kzalloc(sizeof(*request), GFP_KERNEL);
2005 if (ret || request == NULL ||
db53a302 2006 i915_add_request(ring, NULL, request))
0a58705b
CW		 2007 kfree(request);
2008 }
2009
2010 idle &= list_empty(&ring->request_list);
2011 }
2012
2013 if (!dev_priv->mm.suspended && !idle)
9c9fe1f8 2014 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ);
0a58705b 2015
673a394b
EA		 2016 mutex_unlock(&dev->struct_mutex);
2017}
2018
db53a302
CW		 2019/**
2020 * Waits for a sequence number to be signaled, and cleans up the
2021 * request and object lists appropriately for that event.
2022 */
5a5a0c64 2023int
db53a302 2024i915_wait_request(struct intel_ring_buffer *ring,
ce453d81 2025 uint32_t seqno)
673a394b 2026{
db53a302 2027 drm_i915_private_t *dev_priv = ring->dev->dev_private;
802c7eb6 2028 u32 ier;
673a394b
EA		 2029 int ret = 0;
2030
2031 BUG_ON(seqno == 0);
2032
d9bc7e9f
CW		 2033 if (atomic_read(&dev_priv->mm.wedged)) {
2034 struct completion *x = &dev_priv->error_completion;
2035 bool recovery_complete;
2036 unsigned long flags;
2037
2038 /* Give the error handler a chance to run. */
2039 spin_lock_irqsave(&x->wait.lock, flags);
2040 recovery_complete = x->done > 0;
2041 spin_unlock_irqrestore(&x->wait.lock, flags);
2042
2043 return recovery_complete ? -EIO : -EAGAIN;
2044 }
30dbf0c0 2045
5d97eb69 2046 if (seqno == ring->outstanding_lazy_request) {
3cce469c
CW		 2047 struct drm_i915_gem_request *request;
2048
2049 request = kzalloc(sizeof(*request), GFP_KERNEL);
2050 if (request == NULL)
e35a41de 2051 return -ENOMEM;
3cce469c 2052
db53a302 2053 ret = i915_add_request(ring, NULL, request);
3cce469c
CW		 2054 if (ret) {
2055 kfree(request);
2056 return ret;
2057 }
2058
2059 seqno = request->seqno;
e35a41de 2060 }
ffed1d09 2061
78501eac 2062 if (!i915_seqno_passed(ring->get_seqno(ring), seqno)) {
db53a302 2063 if (HAS_PCH_SPLIT(ring->dev))
036a4a7d
ZW		 2064 ier = I915_READ(DEIER) | I915_READ(GTIER);
2065 else
2066 ier = I915_READ(IER);
802c7eb6
JB		 2067 if (!ier) {
2068 DRM_ERROR("something (likely vbetool) disabled "
2069 "interrupts, re-enabling\n");
f01c22fd
CW		 2070 ring->dev->driver->irq_preinstall(ring->dev);
2071 ring->dev->driver->irq_postinstall(ring->dev);
802c7eb6
JB		 2072 }
2073
db53a302 2074 trace_i915_gem_request_wait_begin(ring, seqno);
1c5d22f7 2075
b2223497 2076 ring->waiting_seqno = seqno;
b13c2b96 2077 if (ring->irq_get(ring)) {
ce453d81 2078 if (dev_priv->mm.interruptible)
b13c2b96
CW		 2079 ret = wait_event_interruptible(ring->irq_queue,
2080 i915_seqno_passed(ring->get_seqno(ring), seqno)
2081 || atomic_read(&dev_priv->mm.wedged));
2082 else
2083 wait_event(ring->irq_queue,
2084 i915_seqno_passed(ring->get_seqno(ring), seqno)
2085 || atomic_read(&dev_priv->mm.wedged));
2086
2087 ring->irq_put(ring);
b5ba177d
CW		 2088 } else if (wait_for(i915_seqno_passed(ring->get_seqno(ring),
2089 seqno) ||
2090 atomic_read(&dev_priv->mm.wedged), 3000))
2091 ret = -EBUSY;
b2223497 2092 ring->waiting_seqno = 0;
1c5d22f7 2093
db53a302 2094 trace_i915_gem_request_wait_end(ring, seqno);
673a394b 2095 }
ba1234d1 2096 if (atomic_read(&dev_priv->mm.wedged))
30dbf0c0 2097 ret = -EAGAIN;
673a394b
EA		 2098
2099 if (ret && ret != -ERESTARTSYS)
8bff917c 2100 DRM_ERROR("%s returns %d (awaiting %d at %d, next %d)\n",
78501eac 2101 __func__, ret, seqno, ring->get_seqno(ring),
8bff917c 2102 dev_priv->next_seqno);
673a394b
EA		 2103
2104 /* Directly dispatch request retiring. While we have the work queue
2105 * to handle this, the waiter on a request often wants an associated
2106 * buffer to have made it to the inactive list, and we would need
2107 * a separate wait queue to handle that.
2108 */
2109 if (ret == 0)
db53a302 2110 i915_gem_retire_requests_ring(ring);
673a394b
EA		 2111
2112 return ret;
2113}
2114
673a394b
EA		 2115/**
2116 * Ensures that all rendering to the object has completed and the object is
2117 * safe to unbind from the GTT or access from the CPU.
2118 */
54cf91dc 2119int
ce453d81 2120i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj)
673a394b 2121{
673a394b
EA		 2122 int ret;
2123
e47c68e9
EA		 2124 /* This function only exists to support waiting for existing rendering,
2125 * not for emitting required flushes.
673a394b 2126 */
05394f39 2127 BUG_ON((obj->base.write_domain & I915_GEM_GPU_DOMAINS) != 0);
673a394b
EA		 2128
2129 /* If there is rendering queued on the buffer being evicted, wait for
2130 * it.
2131 */
05394f39 2132 if (obj->active) {
ce453d81 2133 ret = i915_wait_request(obj->ring, obj->last_rendering_seqno);
2cf34d7b 2134 if (ret)
673a394b
EA		 2135 return ret;
2136 }
2137
2138 return 0;
2139}
2140
b5ffc9bc
CW		 2141static void i915_gem_object_finish_gtt(struct drm_i915_gem_object *obj)
2142{
2143 u32 old_write_domain, old_read_domains;
2144
b5ffc9bc
CW		 2145 /* Act a barrier for all accesses through the GTT */
2146 mb();
2147
2148 /* Force a pagefault for domain tracking on next user access */
2149 i915_gem_release_mmap(obj);
2150
b97c3d9c
KP		 2151 if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0)
2152 return;
2153
b5ffc9bc
CW		 2154 old_read_domains = obj->base.read_domains;
2155 old_write_domain = obj->base.write_domain;
2156
2157 obj->base.read_domains &= ~I915_GEM_DOMAIN_GTT;
2158 obj->base.write_domain &= ~I915_GEM_DOMAIN_GTT;
2159
2160 trace_i915_gem_object_change_domain(obj,
2161 old_read_domains,
2162 old_write_domain);
2163}
2164
673a394b
EA		 2165/**
2166 * Unbinds an object from the GTT aperture.
2167 */
0f973f27 2168int
05394f39 2169i915_gem_object_unbind(struct drm_i915_gem_object *obj)
673a394b 2170{
673a394b
EA		 2171 int ret = 0;
2172
05394f39 2173 if (obj->gtt_space == NULL)
673a394b
EA		 2174 return 0;
2175
05394f39 2176 if (obj->pin_count != 0) {
673a394b
EA		 2177 DRM_ERROR("Attempting to unbind pinned buffer\n");
2178 return -EINVAL;
2179 }
2180
a8198eea
CW		 2181 ret = i915_gem_object_finish_gpu(obj);
2182 if (ret == -ERESTARTSYS)
2183 return ret;
2184 /* Continue on if we fail due to EIO, the GPU is hung so we
2185 * should be safe and we need to cleanup or else we might
2186 * cause memory corruption through use-after-free.
2187 */
2188
b5ffc9bc 2189 i915_gem_object_finish_gtt(obj);
5323fd04 2190
673a394b
EA		 2191 /* Move the object to the CPU domain to ensure that
2192 * any possible CPU writes while it's not in the GTT
a8198eea 2193 * are flushed when we go to remap it.
673a394b 2194 */
a8198eea
CW		 2195 if (ret == 0)
2196 ret = i915_gem_object_set_to_cpu_domain(obj, 1);
8dc1775d 2197 if (ret == -ERESTARTSYS)
673a394b 2198 return ret;
812ed492 2199 if (ret) {
a8198eea
CW		 2200 /* In the event of a disaster, abandon all caches and
2201 * hope for the best.
2202 */
812ed492 2203 i915_gem_clflush_object(obj);
05394f39 2204 obj->base.read_domains = obj->base.write_domain = I915_GEM_DOMAIN_CPU;
812ed492 2205 }
673a394b 2206
96b47b65 2207 /* release the fence reg _after_ flushing */
d9e86c0e
CW		 2208 ret = i915_gem_object_put_fence(obj);
2209 if (ret == -ERESTARTSYS)
2210 return ret;
96b47b65 2211
db53a302
CW		 2212 trace_i915_gem_object_unbind(obj);
2213
7c2e6fdf 2214 i915_gem_gtt_unbind_object(obj);
e5281ccd 2215 i915_gem_object_put_pages_gtt(obj);
673a394b 2216
6299f992 2217 list_del_init(&obj->gtt_list);
05394f39 2218 list_del_init(&obj->mm_list);
75e9e915 2219 /* Avoid an unnecessary call to unbind on rebind. */
05394f39 2220 obj->map_and_fenceable = true;
673a394b 2221
05394f39
CW		 2222 drm_mm_put_block(obj->gtt_space);
2223 obj->gtt_space = NULL;
2224 obj->gtt_offset = 0;
673a394b 2225
05394f39 2226 if (i915_gem_object_is_purgeable(obj))
963b4836
CW		 2227 i915_gem_object_truncate(obj);
2228
8dc1775d 2229 return ret;
673a394b
EA		 2230}
2231
88241785 2232int
db53a302 2233i915_gem_flush_ring(struct intel_ring_buffer *ring,
54cf91dc
CW		 2234 uint32_t invalidate_domains,
2235 uint32_t flush_domains)
2236{
88241785
CW		 2237 int ret;
2238
36d527de
CW		 2239 if (((invalidate_domains | flush_domains) & I915_GEM_GPU_DOMAINS) == 0)
2240 return 0;
2241
db53a302
CW		 2242 trace_i915_gem_ring_flush(ring, invalidate_domains, flush_domains);
2243
88241785
CW		 2244 ret = ring->flush(ring, invalidate_domains, flush_domains);
2245 if (ret)
2246 return ret;
2247
36d527de
CW		 2248 if (flush_domains & I915_GEM_GPU_DOMAINS)
2249 i915_gem_process_flushing_list(ring, flush_domains);
2250
88241785 2251 return 0;
54cf91dc
CW		 2252}
2253
db53a302 2254static int i915_ring_idle(struct intel_ring_buffer *ring)
a56ba56c 2255{
88241785
CW		 2256 int ret;
2257
395b70be 2258 if (list_empty(&ring->gpu_write_list) && list_empty(&ring->active_list))
64193406
CW		 2259 return 0;
2260
88241785 2261 if (!list_empty(&ring->gpu_write_list)) {
db53a302 2262 ret = i915_gem_flush_ring(ring,
0ac74c6b 2263 I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
88241785
CW		 2264 if (ret)
2265 return ret;
2266 }
2267
ce453d81 2268 return i915_wait_request(ring, i915_gem_next_request_seqno(ring));
a56ba56c
CW		 2269}
2270
b47eb4a2 2271int
4df2faf4
DV		 2272i915_gpu_idle(struct drm_device *dev)
2273{
2274 drm_i915_private_t *dev_priv = dev->dev_private;
2275 bool lists_empty;
1ec14ad3 2276 int ret, i;
4df2faf4 2277
d1b851fc 2278 lists_empty = (list_empty(&dev_priv->mm.flushing_list) &&
395b70be 2279 list_empty(&dev_priv->mm.active_list));
4df2faf4
DV		 2280 if (lists_empty)
2281 return 0;
2282
2283 /* Flush everything onto the inactive list. */
1ec14ad3 2284 for (i = 0; i < I915_NUM_RINGS; i++) {
db53a302 2285 ret = i915_ring_idle(&dev_priv->ring[i]);
1ec14ad3
CW		 2286 if (ret)
2287 return ret;
2288 }
4df2faf4 2289
8a1a49f9 2290 return 0;
4df2faf4
DV		 2291}
2292
c6642782
DV		 2293static int sandybridge_write_fence_reg(struct drm_i915_gem_object *obj,
2294 struct intel_ring_buffer *pipelined)
4e901fdc 2295{
05394f39 2296 struct drm_device *dev = obj->base.dev;
4e901fdc 2297 drm_i915_private_t *dev_priv = dev->dev_private;
05394f39
CW		 2298 u32 size = obj->gtt_space->size;
2299 int regnum = obj->fence_reg;
4e901fdc
EA		 2300 uint64_t val;
2301
05394f39 2302 val = (uint64_t)((obj->gtt_offset + size - 4096) &
c6642782 2303 0xfffff000) << 32;
05394f39
CW		 2304 val |= obj->gtt_offset & 0xfffff000;
2305 val |= (uint64_t)((obj->stride / 128) - 1) <<
4e901fdc
EA		 2306 SANDYBRIDGE_FENCE_PITCH_SHIFT;
2307
05394f39 2308 if (obj->tiling_mode == I915_TILING_Y)
4e901fdc
EA		 2309 val |= 1 << I965_FENCE_TILING_Y_SHIFT;
2310 val |= I965_FENCE_REG_VALID;
2311
c6642782
DV		 2312 if (pipelined) {
2313 int ret = intel_ring_begin(pipelined, 6);
2314 if (ret)
2315 return ret;
2316
2317 intel_ring_emit(pipelined, MI_NOOP);
2318 intel_ring_emit(pipelined, MI_LOAD_REGISTER_IMM(2));
2319 intel_ring_emit(pipelined, FENCE_REG_SANDYBRIDGE_0 + regnum*8);
2320 intel_ring_emit(pipelined, (u32)val);
2321 intel_ring_emit(pipelined, FENCE_REG_SANDYBRIDGE_0 + regnum*8 + 4);
2322 intel_ring_emit(pipelined, (u32)(val >> 32));
2323 intel_ring_advance(pipelined);
2324 } else
2325 I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + regnum * 8, val);
2326
2327 return 0;
4e901fdc
EA		 2328}
2329
c6642782
DV		 2330static int i965_write_fence_reg(struct drm_i915_gem_object *obj,
2331 struct intel_ring_buffer *pipelined)
de151cf6 2332{
05394f39 2333 struct drm_device *dev = obj->base.dev;
de151cf6 2334 drm_i915_private_t *dev_priv = dev->dev_private;
05394f39
CW		 2335 u32 size = obj->gtt_space->size;
2336 int regnum = obj->fence_reg;
de151cf6
JB		 2337 uint64_t val;
2338
05394f39 2339 val = (uint64_t)((obj->gtt_offset + size - 4096) &
de151cf6 2340 0xfffff000) << 32;
05394f39
CW		 2341 val |= obj->gtt_offset & 0xfffff000;
2342 val |= ((obj->stride / 128) - 1) << I965_FENCE_PITCH_SHIFT;
2343 if (obj->tiling_mode == I915_TILING_Y)
de151cf6
JB		 2344 val |= 1 << I965_FENCE_TILING_Y_SHIFT;
2345 val |= I965_FENCE_REG_VALID;
2346
c6642782
DV		 2347 if (pipelined) {
2348 int ret = intel_ring_begin(pipelined, 6);
2349 if (ret)
2350 return ret;
2351
2352 intel_ring_emit(pipelined, MI_NOOP);
2353 intel_ring_emit(pipelined, MI_LOAD_REGISTER_IMM(2));
2354 intel_ring_emit(pipelined, FENCE_REG_965_0 + regnum*8);
2355 intel_ring_emit(pipelined, (u32)val);
2356 intel_ring_emit(pipelined, FENCE_REG_965_0 + regnum*8 + 4);
2357 intel_ring_emit(pipelined, (u32)(val >> 32));
2358 intel_ring_advance(pipelined);
2359 } else
2360 I915_WRITE64(FENCE_REG_965_0 + regnum * 8, val);
2361
2362 return 0;
de151cf6
JB		 2363}
2364
c6642782
DV		 2365static int i915_write_fence_reg(struct drm_i915_gem_object *obj,
2366 struct intel_ring_buffer *pipelined)
de151cf6 2367{
05394f39 2368 struct drm_device *dev = obj->base.dev;
de151cf6 2369 drm_i915_private_t *dev_priv = dev->dev_private;
05394f39 2370 u32 size = obj->gtt_space->size;
c6642782 2371 u32 fence_reg, val, pitch_val;
0f973f27 2372 int tile_width;
de151cf6 2373
c6642782
DV		 2374 if (WARN((obj->gtt_offset & ~I915_FENCE_START_MASK) ||
2375 (size & -size) != size ||
2376 (obj->gtt_offset & (size - 1)),
2377 "object 0x%08x [fenceable? %d] not 1M or pot-size (0x%08x) aligned\n",
2378 obj->gtt_offset, obj->map_and_fenceable, size))
2379 return -EINVAL;
de151cf6 2380
c6642782 2381 if (obj->tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev))
0f973f27 2382 tile_width = 128;
de151cf6 2383 else
0f973f27
JB		 2384 tile_width = 512;
2385
2386 /* Note: pitch better be a power of two tile widths */
05394f39 2387 pitch_val = obj->stride / tile_width;
0f973f27 2388 pitch_val = ffs(pitch_val) - 1;
de151cf6 2389
05394f39
CW		 2390 val = obj->gtt_offset;
2391 if (obj->tiling_mode == I915_TILING_Y)
de151cf6 2392 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
a00b10c3 2393 val |= I915_FENCE_SIZE_BITS(size);
de151cf6
JB		 2394 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
2395 val |= I830_FENCE_REG_VALID;
2396
05394f39 2397 fence_reg = obj->fence_reg;
a00b10c3
CW		 2398 if (fence_reg < 8)
2399 fence_reg = FENCE_REG_830_0 + fence_reg * 4;
dc529a4f 2400 else
a00b10c3 2401 fence_reg = FENCE_REG_945_8 + (fence_reg - 8) * 4;
c6642782
DV		 2402
2403 if (pipelined) {
2404 int ret = intel_ring_begin(pipelined, 4);
2405 if (ret)
2406 return ret;
2407
2408 intel_ring_emit(pipelined, MI_NOOP);
2409 intel_ring_emit(pipelined, MI_LOAD_REGISTER_IMM(1));
2410 intel_ring_emit(pipelined, fence_reg);
2411 intel_ring_emit(pipelined, val);
2412 intel_ring_advance(pipelined);
2413 } else
2414 I915_WRITE(fence_reg, val);
2415
2416 return 0;
de151cf6
JB		 2417}
2418
c6642782
DV		 2419static int i830_write_fence_reg(struct drm_i915_gem_object *obj,
2420 struct intel_ring_buffer *pipelined)
de151cf6 2421{
05394f39 2422 struct drm_device *dev = obj->base.dev;
de151cf6 2423 drm_i915_private_t *dev_priv = dev->dev_private;
05394f39
CW		 2424 u32 size = obj->gtt_space->size;
2425 int regnum = obj->fence_reg;
de151cf6
JB		 2426 uint32_t val;
2427 uint32_t pitch_val;
2428
c6642782
DV		 2429 if (WARN((obj->gtt_offset & ~I830_FENCE_START_MASK) ||
2430 (size & -size) != size ||
2431 (obj->gtt_offset & (size - 1)),
2432 "object 0x%08x not 512K or pot-size 0x%08x aligned\n",
2433 obj->gtt_offset, size))
2434 return -EINVAL;
de151cf6 2435
05394f39 2436 pitch_val = obj->stride / 128;
e76a16de 2437 pitch_val = ffs(pitch_val) - 1;
e76a16de 2438
05394f39
CW		 2439 val = obj->gtt_offset;
2440 if (obj->tiling_mode == I915_TILING_Y)
de151cf6 2441 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
c6642782 2442 val |= I830_FENCE_SIZE_BITS(size);
de151cf6
JB		 2443 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
2444 val |= I830_FENCE_REG_VALID;
2445
c6642782
DV		 2446 if (pipelined) {
2447 int ret = intel_ring_begin(pipelined, 4);
2448 if (ret)
2449 return ret;
2450
2451 intel_ring_emit(pipelined, MI_NOOP);
2452 intel_ring_emit(pipelined, MI_LOAD_REGISTER_IMM(1));
2453 intel_ring_emit(pipelined, FENCE_REG_830_0 + regnum*4);
2454 intel_ring_emit(pipelined, val);
2455 intel_ring_advance(pipelined);
2456 } else
2457 I915_WRITE(FENCE_REG_830_0 + regnum * 4, val);
2458
2459 return 0;
de151cf6
JB		 2460}
2461
d9e86c0e
CW		 2462static bool ring_passed_seqno(struct intel_ring_buffer *ring, u32 seqno)
2463{
2464 return i915_seqno_passed(ring->get_seqno(ring), seqno);
2465}
2466
2467static int
2468i915_gem_object_flush_fence(struct drm_i915_gem_object *obj,
ce453d81 2469 struct intel_ring_buffer *pipelined)
d9e86c0e
CW		 2470{
2471 int ret;
2472
2473 if (obj->fenced_gpu_access) {
88241785 2474 if (obj->base.write_domain & I915_GEM_GPU_DOMAINS) {
db53a302 2475 ret = i915_gem_flush_ring(obj->last_fenced_ring,
88241785
CW		 2476 0, obj->base.write_domain);
2477 if (ret)
2478 return ret;
2479 }
d9e86c0e
CW		 2480
2481 obj->fenced_gpu_access = false;
2482 }
2483
2484 if (obj->last_fenced_seqno && pipelined != obj->last_fenced_ring) {
2485 if (!ring_passed_seqno(obj->last_fenced_ring,
2486 obj->last_fenced_seqno)) {
db53a302 2487 ret = i915_wait_request(obj->last_fenced_ring,
ce453d81 2488 obj->last_fenced_seqno);
d9e86c0e
CW		 2489 if (ret)
2490 return ret;
2491 }
2492
2493 obj->last_fenced_seqno = 0;
2494 obj->last_fenced_ring = NULL;
2495 }
2496
63256ec5
CW		 2497 /* Ensure that all CPU reads are completed before installing a fence
2498 * and all writes before removing the fence.
2499 */
2500 if (obj->base.read_domains & I915_GEM_DOMAIN_GTT)
2501 mb();
2502
d9e86c0e
CW		 2503 return 0;
2504}
2505
2506int
2507i915_gem_object_put_fence(struct drm_i915_gem_object *obj)
2508{
2509 int ret;
2510
2511 if (obj->tiling_mode)
2512 i915_gem_release_mmap(obj);
2513
ce453d81 2514 ret = i915_gem_object_flush_fence(obj, NULL);
d9e86c0e
CW		 2515 if (ret)
2516 return ret;
2517
2518 if (obj->fence_reg != I915_FENCE_REG_NONE) {
2519 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2520 i915_gem_clear_fence_reg(obj->base.dev,
2521 &dev_priv->fence_regs[obj->fence_reg]);
2522
2523 obj->fence_reg = I915_FENCE_REG_NONE;
2524 }
2525
2526 return 0;
2527}
2528
2529static struct drm_i915_fence_reg *
2530i915_find_fence_reg(struct drm_device *dev,
2531 struct intel_ring_buffer *pipelined)
ae3db24a 2532{
ae3db24a 2533 struct drm_i915_private *dev_priv = dev->dev_private;
d9e86c0e
CW		 2534 struct drm_i915_fence_reg *reg, *first, *avail;
2535 int i;
ae3db24a
DV		 2536
2537 /* First try to find a free reg */
d9e86c0e 2538 avail = NULL;
ae3db24a
DV		 2539 for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) {
2540 reg = &dev_priv->fence_regs[i];
2541 if (!reg->obj)
d9e86c0e 2542 return reg;
ae3db24a 2543
05394f39 2544 if (!reg->obj->pin_count)
d9e86c0e 2545 avail = reg;
ae3db24a
DV		 2546 }
2547
d9e86c0e
CW		 2548 if (avail == NULL)
2549 return NULL;
ae3db24a
DV		 2550
2551 /* None available, try to steal one or wait for a user to finish */
d9e86c0e
CW		 2552 avail = first = NULL;
2553 list_for_each_entry(reg, &dev_priv->mm.fence_list, lru_list) {
2554 if (reg->obj->pin_count)
ae3db24a
DV		 2555 continue;
2556
d9e86c0e
CW		 2557 if (first == NULL)
2558 first = reg;
2559
2560 if (!pipelined ||
2561 !reg->obj->last_fenced_ring ||
2562 reg->obj->last_fenced_ring == pipelined) {
2563 avail = reg;
2564 break;
2565 }
ae3db24a
DV		 2566 }
2567
d9e86c0e
CW		 2568 if (avail == NULL)
2569 avail = first;
ae3db24a 2570
a00b10c3 2571 return avail;
ae3db24a
DV		 2572}
2573
de151cf6 2574/**
d9e86c0e 2575 * i915_gem_object_get_fence - set up a fence reg for an object
de151cf6 2576 * @obj: object to map through a fence reg
d9e86c0e
CW		 2577 * @pipelined: ring on which to queue the change, or NULL for CPU access
2578 * @interruptible: must we wait uninterruptibly for the register to retire?
de151cf6
JB		 2579 *
2580 * When mapping objects through the GTT, userspace wants to be able to write
2581 * to them without having to worry about swizzling if the object is tiled.
2582 *
2583 * This function walks the fence regs looking for a free one for @obj,
2584 * stealing one if it can't find any.
2585 *
2586 * It then sets up the reg based on the object's properties: address, pitch
2587 * and tiling format.
2588 */
8c4b8c3f 2589int
d9e86c0e 2590i915_gem_object_get_fence(struct drm_i915_gem_object *obj,
ce453d81 2591 struct intel_ring_buffer *pipelined)
de151cf6 2592{
05394f39 2593 struct drm_device *dev = obj->base.dev;
79e53945 2594 struct drm_i915_private *dev_priv = dev->dev_private;
d9e86c0e 2595 struct drm_i915_fence_reg *reg;
ae3db24a 2596 int ret;
de151cf6 2597
6bda10d1
CW		 2598 /* XXX disable pipelining. There are bugs. Shocking. */
2599 pipelined = NULL;
2600
d9e86c0e 2601 /* Just update our place in the LRU if our fence is getting reused. */
05394f39
CW		 2602 if (obj->fence_reg != I915_FENCE_REG_NONE) {
2603 reg = &dev_priv->fence_regs[obj->fence_reg];
007cc8ac 2604 list_move_tail(&reg->lru_list, &dev_priv->mm.fence_list);
d9e86c0e 2605
29c5a587
CW		 2606 if (obj->tiling_changed) {
2607 ret = i915_gem_object_flush_fence(obj, pipelined);
2608 if (ret)
2609 return ret;
2610
2611 if (!obj->fenced_gpu_access && !obj->last_fenced_seqno)
2612 pipelined = NULL;
2613
2614 if (pipelined) {
2615 reg->setup_seqno =
2616 i915_gem_next_request_seqno(pipelined);
2617 obj->last_fenced_seqno = reg->setup_seqno;
2618 obj->last_fenced_ring = pipelined;
2619 }
2620
2621 goto update;
2622 }
d9e86c0e
CW		 2623
2624 if (!pipelined) {
2625 if (reg->setup_seqno) {
2626 if (!ring_passed_seqno(obj->last_fenced_ring,
2627 reg->setup_seqno)) {
db53a302 2628 ret = i915_wait_request(obj->last_fenced_ring,
ce453d81 2629 reg->setup_seqno);
d9e86c0e
CW		 2630 if (ret)
2631 return ret;
2632 }
2633
2634 reg->setup_seqno = 0;
2635 }
2636 } else if (obj->last_fenced_ring &&
2637 obj->last_fenced_ring != pipelined) {
ce453d81 2638 ret = i915_gem_object_flush_fence(obj, pipelined);
d9e86c0e
CW		 2639 if (ret)
2640 return ret;
d9e86c0e
CW		 2641 }
2642
a09ba7fa
EA		 2643 return 0;
2644 }
2645
d9e86c0e
CW		 2646 reg = i915_find_fence_reg(dev, pipelined);
2647 if (reg == NULL)
2648 return -ENOSPC;
de151cf6 2649
ce453d81 2650 ret = i915_gem_object_flush_fence(obj, pipelined);
d9e86c0e 2651 if (ret)
ae3db24a 2652 return ret;
de151cf6 2653
d9e86c0e
CW		 2654 if (reg->obj) {
2655 struct drm_i915_gem_object *old = reg->obj;
2656
2657 drm_gem_object_reference(&old->base);
2658
2659 if (old->tiling_mode)
2660 i915_gem_release_mmap(old);
2661
ce453d81 2662 ret = i915_gem_object_flush_fence(old, pipelined);
d9e86c0e
CW		 2663 if (ret) {
2664 drm_gem_object_unreference(&old->base);
2665 return ret;
2666 }
2667
2668 if (old->last_fenced_seqno == 0 && obj->last_fenced_seqno == 0)
2669 pipelined = NULL;
2670
2671 old->fence_reg = I915_FENCE_REG_NONE;
2672 old->last_fenced_ring = pipelined;
2673 old->last_fenced_seqno =
db53a302 2674 pipelined ? i915_gem_next_request_seqno(pipelined) : 0;
d9e86c0e
CW		 2675
2676 drm_gem_object_unreference(&old->base);
2677 } else if (obj->last_fenced_seqno == 0)
2678 pipelined = NULL;
a09ba7fa 2679
de151cf6 2680 reg->obj = obj;
d9e86c0e
CW		 2681 list_move_tail(&reg->lru_list, &dev_priv->mm.fence_list);
2682 obj->fence_reg = reg - dev_priv->fence_regs;
2683 obj->last_fenced_ring = pipelined;
de151cf6 2684
d9e86c0e 2685 reg->setup_seqno =
db53a302 2686 pipelined ? i915_gem_next_request_seqno(pipelined) : 0;
d9e86c0e
CW		 2687 obj->last_fenced_seqno = reg->setup_seqno;
2688
2689update:
2690 obj->tiling_changed = false;
e259befd 2691 switch (INTEL_INFO(dev)->gen) {
25aebfc3 2692 case 7:
e259befd 2693 case 6:
c6642782 2694 ret = sandybridge_write_fence_reg(obj, pipelined);
e259befd
CW		 2695 break;
2696 case 5:
2697 case 4:
c6642782 2698 ret = i965_write_fence_reg(obj, pipelined);
e259befd
CW		 2699 break;
2700 case 3:
c6642782 2701 ret = i915_write_fence_reg(obj, pipelined);
e259befd
CW		 2702 break;
2703 case 2:
c6642782 2704 ret = i830_write_fence_reg(obj, pipelined);
e259befd
CW		 2705 break;
2706 }
d9ddcb96 2707
c6642782 2708 return ret;
de151cf6
JB		 2709}
2710
2711/**
2712 * i915_gem_clear_fence_reg - clear out fence register info
2713 * @obj: object to clear
2714 *
2715 * Zeroes out the fence register itself and clears out the associated
05394f39 2716 * data structures in dev_priv and obj.
de151cf6
JB		 2717 */
2718static void
d9e86c0e
CW		 2719i915_gem_clear_fence_reg(struct drm_device *dev,
2720 struct drm_i915_fence_reg *reg)
de151cf6 2721{
79e53945 2722 drm_i915_private_t *dev_priv = dev->dev_private;
d9e86c0e 2723 uint32_t fence_reg = reg - dev_priv->fence_regs;
de151cf6 2724
e259befd 2725 switch (INTEL_INFO(dev)->gen) {
25aebfc3 2726 case 7:
e259befd 2727 case 6:
d9e86c0e 2728 I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + fence_reg*8, 0);
e259befd
CW		 2729 break;
2730 case 5:
2731 case 4:
d9e86c0e 2732 I915_WRITE64(FENCE_REG_965_0 + fence_reg*8, 0);
e259befd
CW		 2733 break;
2734 case 3:
d9e86c0e
CW		 2735 if (fence_reg >= 8)
2736 fence_reg = FENCE_REG_945_8 + (fence_reg - 8) * 4;
dc529a4f 2737 else
e259befd 2738 case 2:
d9e86c0e 2739 fence_reg = FENCE_REG_830_0 + fence_reg * 4;
dc529a4f
EA		 2740
2741 I915_WRITE(fence_reg, 0);
e259befd 2742 break;
dc529a4f 2743 }
de151cf6 2744
007cc8ac 2745 list_del_init(&reg->lru_list);
d9e86c0e
CW		 2746 reg->obj = NULL;
2747 reg->setup_seqno = 0;
52dc7d32
CW		 2748}
2749
673a394b
EA		 2750/**
2751 * Finds free space in the GTT aperture and binds the object there.
2752 */
2753static int
05394f39 2754i915_gem_object_bind_to_gtt(struct drm_i915_gem_object *obj,
920afa77 2755 unsigned alignment,
75e9e915 2756 bool map_and_fenceable)
673a394b 2757{
05394f39 2758 struct drm_device *dev = obj->base.dev;
673a394b 2759 drm_i915_private_t *dev_priv = dev->dev_private;
673a394b 2760 struct drm_mm_node *free_space;
a00b10c3 2761 gfp_t gfpmask = __GFP_NORETRY | __GFP_NOWARN;
5e783301 2762 u32 size, fence_size, fence_alignment, unfenced_alignment;
75e9e915 2763 bool mappable, fenceable;
07f73f69 2764 int ret;
673a394b 2765
05394f39 2766 if (obj->madv != I915_MADV_WILLNEED) {
3ef94daa
CW		 2767 DRM_ERROR("Attempting to bind a purgeable object\n");
2768 return -EINVAL;
2769 }
2770
e28f8711
CW		 2771 fence_size = i915_gem_get_gtt_size(dev,
2772 obj->base.size,
2773 obj->tiling_mode);
2774 fence_alignment = i915_gem_get_gtt_alignment(dev,
2775 obj->base.size,
2776 obj->tiling_mode);
2777 unfenced_alignment =
2778 i915_gem_get_unfenced_gtt_alignment(dev,
2779 obj->base.size,
2780 obj->tiling_mode);
a00b10c3 2781
673a394b 2782 if (alignment == 0)
5e783301
DV		 2783 alignment = map_and_fenceable ? fence_alignment :
2784 unfenced_alignment;
75e9e915 2785 if (map_and_fenceable && alignment & (fence_alignment - 1)) {
673a394b
EA		 2786 DRM_ERROR("Invalid object alignment requested %u\n", alignment);
2787 return -EINVAL;
2788 }
2789
05394f39 2790 size = map_and_fenceable ? fence_size : obj->base.size;
a00b10c3 2791
654fc607
CW		 2792 /* If the object is bigger than the entire aperture, reject it early
2793 * before evicting everything in a vain attempt to find space.
2794 */
05394f39 2795 if (obj->base.size >
75e9e915 2796 (map_and_fenceable ? dev_priv->mm.gtt_mappable_end : dev_priv->mm.gtt_total)) {
654fc607
CW		 2797 DRM_ERROR("Attempting to bind an object larger than the aperture\n");
2798 return -E2BIG;
2799 }
2800
673a394b 2801 search_free:
75e9e915 2802 if (map_and_fenceable)
920afa77
DV		 2803 free_space =
2804 drm_mm_search_free_in_range(&dev_priv->mm.gtt_space,
a00b10c3 2805 size, alignment, 0,
920afa77
DV		 2806 dev_priv->mm.gtt_mappable_end,
2807 0);
2808 else
2809 free_space = drm_mm_search_free(&dev_priv->mm.gtt_space,
a00b10c3 2810 size, alignment, 0);
920afa77
DV		 2811
2812 if (free_space != NULL) {
75e9e915 2813 if (map_and_fenceable)
05394f39 2814 obj->gtt_space =
920afa77 2815 drm_mm_get_block_range_generic(free_space,
a00b10c3 2816 size, alignment, 0,
920afa77
DV		 2817 dev_priv->mm.gtt_mappable_end,
2818 0);
2819 else
05394f39 2820 obj->gtt_space =
a00b10c3 2821 drm_mm_get_block(free_space, size, alignment);
920afa77 2822 }
05394f39 2823 if (obj->gtt_space == NULL) {
673a394b
EA		 2824 /* If the gtt is empty and we're still having trouble
2825 * fitting our object in, we're out of memory.
2826 */
75e9e915
DV		 2827 ret = i915_gem_evict_something(dev, size, alignment,
2828 map_and_fenceable);
9731129c 2829 if (ret)
673a394b 2830 return ret;
9731129c 2831
673a394b
EA		 2832 goto search_free;
2833 }
2834
e5281ccd 2835 ret = i915_gem_object_get_pages_gtt(obj, gfpmask);
673a394b 2836 if (ret) {
05394f39
CW		 2837 drm_mm_put_block(obj->gtt_space);
2838 obj->gtt_space = NULL;
07f73f69
CW		 2839
2840 if (ret == -ENOMEM) {
809b6334
CW		 2841 /* first try to reclaim some memory by clearing the GTT */
2842 ret = i915_gem_evict_everything(dev, false);
07f73f69 2843 if (ret) {
07f73f69 2844 /* now try to shrink everyone else */
4bdadb97
CW		 2845 if (gfpmask) {
2846 gfpmask = 0;
2847 goto search_free;
07f73f69
CW		 2848 }
2849
809b6334 2850 return -ENOMEM;
07f73f69
CW		 2851 }
2852
2853 goto search_free;
2854 }
2855
673a394b
EA		 2856 return ret;
2857 }
2858
7c2e6fdf
DV		 2859 ret = i915_gem_gtt_bind_object(obj);
2860 if (ret) {
e5281ccd 2861 i915_gem_object_put_pages_gtt(obj);
05394f39
CW		 2862 drm_mm_put_block(obj->gtt_space);
2863 obj->gtt_space = NULL;
07f73f69 2864
809b6334 2865 if (i915_gem_evict_everything(dev, false))
07f73f69 2866 return ret;
07f73f69
CW		 2867
2868 goto search_free;
673a394b 2869 }
673a394b 2870
6299f992 2871 list_add_tail(&obj->gtt_list, &dev_priv->mm.gtt_list);
05394f39 2872 list_add_tail(&obj->mm_list, &dev_priv->mm.inactive_list);
bf1a1092 2873
673a394b
EA		 2874 /* Assert that the object is not currently in any GPU domain. As it
2875 * wasn't in the GTT, there shouldn't be any way it could have been in
2876 * a GPU cache
2877 */
05394f39
CW		 2878 BUG_ON(obj->base.read_domains & I915_GEM_GPU_DOMAINS);
2879 BUG_ON(obj->base.write_domain & I915_GEM_GPU_DOMAINS);
673a394b 2880
6299f992 2881 obj->gtt_offset = obj->gtt_space->start;
1c5d22f7 2882
75e9e915 2883 fenceable =
05394f39
CW		 2884 obj->gtt_space->size == fence_size &&
2885 (obj->gtt_space->start & (fence_alignment -1)) == 0;
a00b10c3 2886
75e9e915 2887 mappable =
05394f39 2888 obj->gtt_offset + obj->base.size <= dev_priv->mm.gtt_mappable_end;
a00b10c3 2889
05394f39 2890 obj->map_and_fenceable = mappable && fenceable;
75e9e915 2891
db53a302 2892 trace_i915_gem_object_bind(obj, map_and_fenceable);
673a394b
EA		 2893 return 0;
2894}
2895
2896void
05394f39 2897i915_gem_clflush_object(struct drm_i915_gem_object *obj)
673a394b 2898{
673a394b
EA		 2899 /* If we don't have a page list set up, then we're not pinned
2900 * to GPU, and we can ignore the cache flush because it'll happen
2901 * again at bind time.
2902 */
05394f39 2903 if (obj->pages == NULL)
673a394b
EA		 2904 return;
2905
9c23f7fc
CW		 2906 /* If the GPU is snooping the contents of the CPU cache,
2907 * we do not need to manually clear the CPU cache lines. However,
2908 * the caches are only snooped when the render cache is
2909 * flushed/invalidated. As we always have to emit invalidations
2910 * and flushes when moving into and out of the RENDER domain, correct
2911 * snooping behaviour occurs naturally as the result of our domain
2912 * tracking.
2913 */
2914 if (obj->cache_level != I915_CACHE_NONE)
2915 return;
2916
1c5d22f7 2917 trace_i915_gem_object_clflush(obj);
cfa16a0d 2918
05394f39 2919 drm_clflush_pages(obj->pages, obj->base.size / PAGE_SIZE);
673a394b
EA		 2920}
2921
e47c68e9 2922/** Flushes any GPU write domain for the object if it's dirty. */
88241785 2923static int
3619df03 2924i915_gem_object_flush_gpu_write_domain(struct drm_i915_gem_object *obj)
e47c68e9 2925{
05394f39 2926 if ((obj->base.write_domain & I915_GEM_GPU_DOMAINS) == 0)
88241785 2927 return 0;
e47c68e9
EA		 2928
2929 /* Queue the GPU write cache flushing we need. */
db53a302 2930 return i915_gem_flush_ring(obj->ring, 0, obj->base.write_domain);
e47c68e9
EA		 2931}
2932
2933/** Flushes the GTT write domain for the object if it's dirty. */
2934static void
05394f39 2935i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj)
e47c68e9 2936{
1c5d22f7
CW		 2937 uint32_t old_write_domain;
2938
05394f39 2939 if (obj->base.write_domain != I915_GEM_DOMAIN_GTT)
e47c68e9
EA		 2940 return;
2941
63256ec5 2942 /* No actual flushing is required for the GTT write domain. Writes
e47c68e9
EA		 2943 * to it immediately go to main memory as far as we know, so there's
2944 * no chipset flush. It also doesn't land in render cache.
63256ec5
CW		 2945 *
2946 * However, we do have to enforce the order so that all writes through
2947 * the GTT land before any writes to the device, such as updates to
2948 * the GATT itself.
e47c68e9 2949 */
63256ec5
CW		 2950 wmb();
2951
05394f39
CW		 2952 old_write_domain = obj->base.write_domain;
2953 obj->base.write_domain = 0;
1c5d22f7
CW		 2954
2955 trace_i915_gem_object_change_domain(obj,
05394f39 2956 obj->base.read_domains,
1c5d22f7 2957 old_write_domain);
e47c68e9
EA		 2958}
2959
2960/** Flushes the CPU write domain for the object if it's dirty. */
2961static void
05394f39 2962i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj)
e47c68e9 2963{
1c5d22f7 2964 uint32_t old_write_domain;
e47c68e9 2965
05394f39 2966 if (obj->base.write_domain != I915_GEM_DOMAIN_CPU)
e47c68e9
EA		 2967 return;
2968
2969 i915_gem_clflush_object(obj);
40ce6575 2970 intel_gtt_chipset_flush();
05394f39
CW		 2971 old_write_domain = obj->base.write_domain;
2972 obj->base.write_domain = 0;
1c5d22f7
CW		 2973
2974 trace_i915_gem_object_change_domain(obj,
05394f39 2975 obj->base.read_domains,
1c5d22f7 2976 old_write_domain);
e47c68e9
EA		 2977}
2978
2ef7eeaa
EA		 2979/**
2980 * Moves a single object to the GTT read, and possibly write domain.
2981 *
2982 * This function returns when the move is complete, including waiting on
2983 * flushes to occur.
2984 */
79e53945 2985int
2021746e 2986i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write)
2ef7eeaa 2987{
1c5d22f7 2988 uint32_t old_write_domain, old_read_domains;
e47c68e9 2989 int ret;
2ef7eeaa 2990
02354392 2991 /* Not valid to be called on unbound objects. */
05394f39 2992 if (obj->gtt_space == NULL)
02354392
EA		 2993 return -EINVAL;
2994
8d7e3de1
CW		 2995 if (obj->base.write_domain == I915_GEM_DOMAIN_GTT)
2996 return 0;
2997
88241785
CW		 2998 ret = i915_gem_object_flush_gpu_write_domain(obj);
2999 if (ret)
3000 return ret;
3001
87ca9c8a 3002 if (obj->pending_gpu_write || write) {
ce453d81 3003 ret = i915_gem_object_wait_rendering(obj);
87ca9c8a
CW		 3004 if (ret)
3005 return ret;
3006 }
2dafb1e0 3007
7213342d 3008 i915_gem_object_flush_cpu_write_domain(obj);
1c5d22f7 3009
05394f39
CW		 3010 old_write_domain = obj->base.write_domain;
3011 old_read_domains = obj->base.read_domains;
1c5d22f7 3012
e47c68e9
EA		 3013 /* It should now be out of any other write domains, and we can update
3014 * the domain values for our changes.
3015 */
05394f39
CW		 3016 BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) != 0);
3017 obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
e47c68e9 3018 if (write) {
05394f39
CW		 3019 obj->base.read_domains = I915_GEM_DOMAIN_GTT;
3020 obj->base.write_domain = I915_GEM_DOMAIN_GTT;
3021 obj->dirty = 1;
2ef7eeaa
EA		 3022 }
3023
1c5d22f7
CW		 3024 trace_i915_gem_object_change_domain(obj,
3025 old_read_domains,
3026 old_write_domain);
3027
e47c68e9
EA		 3028 return 0;
3029}
3030
e4ffd173
CW		 3031int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
3032 enum i915_cache_level cache_level)
3033{
3034 int ret;
3035
3036 if (obj->cache_level == cache_level)
3037 return 0;
3038
3039 if (obj->pin_count) {
3040 DRM_DEBUG("can not change the cache level of pinned objects\n");
3041 return -EBUSY;
3042 }
3043
3044 if (obj->gtt_space) {
3045 ret = i915_gem_object_finish_gpu(obj);
3046 if (ret)
3047 return ret;
3048
3049 i915_gem_object_finish_gtt(obj);
3050
3051 /* Before SandyBridge, you could not use tiling or fence
3052 * registers with snooped memory, so relinquish any fences
3053 * currently pointing to our region in the aperture.
3054 */
3055 if (INTEL_INFO(obj->base.dev)->gen < 6) {
3056 ret = i915_gem_object_put_fence(obj);
3057 if (ret)
3058 return ret;
3059 }
3060
3061 i915_gem_gtt_rebind_object(obj, cache_level);
3062 }
3063
3064 if (cache_level == I915_CACHE_NONE) {
3065 u32 old_read_domains, old_write_domain;
3066
3067 /* If we're coming from LLC cached, then we haven't
3068 * actually been tracking whether the data is in the
3069 * CPU cache or not, since we only allow one bit set
3070 * in obj->write_domain and have been skipping the clflushes.
3071 * Just set it to the CPU cache for now.
3072 */
3073 WARN_ON(obj->base.write_domain & ~I915_GEM_DOMAIN_CPU);
3074 WARN_ON(obj->base.read_domains & ~I915_GEM_DOMAIN_CPU);
3075
3076 old_read_domains = obj->base.read_domains;
3077 old_write_domain = obj->base.write_domain;
3078
3079 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
3080 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
3081
3082 trace_i915_gem_object_change_domain(obj,
3083 old_read_domains,
3084 old_write_domain);
3085 }
3086
3087 obj->cache_level = cache_level;
3088 return 0;
3089}
3090
b9241ea3 3091/*
2da3b9b9
CW		 3092 * Prepare buffer for display plane (scanout, cursors, etc).
3093 * Can be called from an uninterruptible phase (modesetting) and allows
3094 * any flushes to be pipelined (for pageflips).
3095 *
3096 * For the display plane, we want to be in the GTT but out of any write
3097 * domains. So in many ways this looks like set_to_gtt_domain() apart from the
3098 * ability to pipeline the waits, pinning and any additional subtleties
3099 * that may differentiate the display plane from ordinary buffers.
b9241ea3
ZW		 3100 */
3101int
2da3b9b9
CW		 3102i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
3103 u32 alignment,
919926ae 3104 struct intel_ring_buffer *pipelined)
b9241ea3 3105{
2da3b9b9 3106 u32 old_read_domains, old_write_domain;
b9241ea3
ZW		 3107 int ret;
3108
88241785
CW		 3109 ret = i915_gem_object_flush_gpu_write_domain(obj);
3110 if (ret)
3111 return ret;
3112
0be73284 3113 if (pipelined != obj->ring) {
ce453d81 3114 ret = i915_gem_object_wait_rendering(obj);
f0b69efc 3115 if (ret == -ERESTARTSYS)
b9241ea3
ZW		 3116 return ret;
3117 }
3118
a7ef0640
EA		 3119 /* The display engine is not coherent with the LLC cache on gen6. As
3120 * a result, we make sure that the pinning that is about to occur is
3121 * done with uncached PTEs. This is lowest common denominator for all
3122 * chipsets.
3123 *
3124 * However for gen6+, we could do better by using the GFDT bit instead
3125 * of uncaching, which would allow us to flush all the LLC-cached data
3126 * with that bit in the PTE to main memory with just one PIPE_CONTROL.
3127 */
3128 ret = i915_gem_object_set_cache_level(obj, I915_CACHE_NONE);
3129 if (ret)
3130 return ret;
3131
2da3b9b9
CW		 3132 /* As the user may map the buffer once pinned in the display plane
3133 * (e.g. libkms for the bootup splash), we have to ensure that we
3134 * always use map_and_fenceable for all scanout buffers.
3135 */
3136 ret = i915_gem_object_pin(obj, alignment, true);
3137 if (ret)
3138 return ret;
3139
b118c1e3
CW		 3140 i915_gem_object_flush_cpu_write_domain(obj);
3141
2da3b9b9 3142 old_write_domain = obj->base.write_domain;
05394f39 3143 old_read_domains = obj->base.read_domains;
2da3b9b9
CW		 3144
3145 /* It should now be out of any other write domains, and we can update
3146 * the domain values for our changes.
3147 */
3148 BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) != 0);
05394f39 3149 obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
b9241ea3
ZW		 3150
3151 trace_i915_gem_object_change_domain(obj,
3152 old_read_domains,
2da3b9b9 3153 old_write_domain);
b9241ea3
ZW		 3154
3155 return 0;
3156}
3157
85345517 3158int
a8198eea 3159i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj)
85345517 3160{
88241785
CW		 3161 int ret;
3162
a8198eea 3163 if ((obj->base.read_domains & I915_GEM_GPU_DOMAINS) == 0)
85345517
CW		 3164 return 0;
3165
88241785 3166 if (obj->base.write_domain & I915_GEM_GPU_DOMAINS) {
db53a302 3167 ret = i915_gem_flush_ring(obj->ring, 0, obj->base.write_domain);
88241785
CW		 3168 if (ret)
3169 return ret;
3170 }
85345517 3171
a8198eea
CW		 3172 /* Ensure that we invalidate the GPU's caches and TLBs. */
3173 obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS;
3174
ce453d81 3175 return i915_gem_object_wait_rendering(obj);
85345517
CW		 3176}
3177
e47c68e9
EA		 3178/**
3179 * Moves a single object to the CPU read, and possibly write domain.
3180 *
3181 * This function returns when the move is complete, including waiting on
3182 * flushes to occur.
3183 */
3184static int
919926ae 3185i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write)
e47c68e9 3186{
1c5d22f7 3187 uint32_t old_write_domain, old_read_domains;
e47c68e9
EA		 3188 int ret;
3189
8d7e3de1
CW		 3190 if (obj->base.write_domain == I915_GEM_DOMAIN_CPU)
3191 return 0;
3192
88241785
CW		 3193 ret = i915_gem_object_flush_gpu_write_domain(obj);
3194 if (ret)
3195 return ret;
3196
ce453d81 3197 ret = i915_gem_object_wait_rendering(obj);
de18a29e 3198 if (ret)
e47c68e9 3199 return ret;
2ef7eeaa 3200
e47c68e9 3201 i915_gem_object_flush_gtt_write_domain(obj);
2ef7eeaa 3202
e47c68e9
EA		 3203 /* If we have a partially-valid cache of the object in the CPU,
3204 * finish invalidating it and free the per-page flags.
2ef7eeaa 3205 */
e47c68e9 3206 i915_gem_object_set_to_full_cpu_read_domain(obj);
2ef7eeaa 3207
05394f39
CW		 3208 old_write_domain = obj->base.write_domain;
3209 old_read_domains = obj->base.read_domains;
1c5d22f7 3210
e47c68e9 3211 /* Flush the CPU cache if it's still invalid. */
05394f39 3212 if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) {
2ef7eeaa 3213 i915_gem_clflush_object(obj);
2ef7eeaa 3214
05394f39 3215 obj->base.read_domains |= I915_GEM_DOMAIN_CPU;
2ef7eeaa
EA		 3216 }
3217
3218 /* It should now be out of any other write domains, and we can update
3219 * the domain values for our changes.
3220 */
05394f39 3221 BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
e47c68e9
EA		 3222
3223 /* If we're writing through the CPU, then the GPU read domains will
3224 * need to be invalidated at next use.
3225 */
3226 if (write) {
05394f39
CW		 3227 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
3228 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
e47c68e9 3229 }
2ef7eeaa 3230
1c5d22f7
CW		 3231 trace_i915_gem_object_change_domain(obj,
3232 old_read_domains,
3233 old_write_domain);
3234
2ef7eeaa
EA		 3235 return 0;
3236}
3237
673a394b 3238/**
e47c68e9 3239 * Moves the object from a partially CPU read to a full one.
673a394b 3240 *
e47c68e9
EA		 3241 * Note that this only resolves i915_gem_object_set_cpu_read_domain_range(),
3242 * and doesn't handle transitioning from !(read_domains & I915_GEM_DOMAIN_CPU).
673a394b 3243 */
e47c68e9 3244static void
05394f39 3245i915_gem_object_set_to_full_cpu_read_domain(struct drm_i915_gem_object *obj)
673a394b 3246{
05394f39 3247 if (!obj->page_cpu_valid)
e47c68e9
EA		 3248 return;
3249
3250 /* If we're partially in the CPU read domain, finish moving it in.
3251 */
05394f39 3252 if (obj->base.read_domains & I915_GEM_DOMAIN_CPU) {
e47c68e9
EA		 3253 int i;
3254
05394f39
CW		 3255 for (i = 0; i <= (obj->base.size - 1) / PAGE_SIZE; i++) {
3256 if (obj->page_cpu_valid[i])
e47c68e9 3257 continue;
05394f39 3258 drm_clflush_pages(obj->pages + i, 1);
e47c68e9 3259 }
e47c68e9
EA		 3260 }
3261
3262 /* Free the page_cpu_valid mappings which are now stale, whether
3263 * or not we've got I915_GEM_DOMAIN_CPU.
3264 */
05394f39
CW		 3265 kfree(obj->page_cpu_valid);
3266 obj->page_cpu_valid = NULL;
e47c68e9
EA		 3267}
3268
3269/**
3270 * Set the CPU read domain on a range of the object.
3271 *
3272 * The object ends up with I915_GEM_DOMAIN_CPU in its read flags although it's
3273 * not entirely valid. The page_cpu_valid member of the object flags which
3274 * pages have been flushed, and will be respected by
3275 * i915_gem_object_set_to_cpu_domain() if it's called on to get a valid mapping
3276 * of the whole object.
3277 *
3278 * This function returns when the move is complete, including waiting on
3279 * flushes to occur.
3280 */
3281static int
05394f39 3282i915_gem_object_set_cpu_read_domain_range(struct drm_i915_gem_object *obj,
e47c68e9
EA		 3283 uint64_t offset, uint64_t size)
3284{
1c5d22f7 3285 uint32_t old_read_domains;
e47c68e9 3286 int i, ret;
673a394b 3287
05394f39 3288 if (offset == 0 && size == obj->base.size)
e47c68e9 3289 return i915_gem_object_set_to_cpu_domain(obj, 0);
673a394b 3290
88241785
CW		 3291 ret = i915_gem_object_flush_gpu_write_domain(obj);
3292 if (ret)
3293 return ret;
3294
ce453d81 3295 ret = i915_gem_object_wait_rendering(obj);
de18a29e 3296 if (ret)
6a47baa6 3297 return ret;
de18a29e 3298
e47c68e9
EA		 3299 i915_gem_object_flush_gtt_write_domain(obj);
3300
3301 /* If we're already fully in the CPU read domain, we're done. */
05394f39
CW		 3302 if (obj->page_cpu_valid == NULL &&
3303 (obj->base.read_domains & I915_GEM_DOMAIN_CPU) != 0)
e47c68e9 3304 return 0;
673a394b 3305
e47c68e9
EA		 3306 /* Otherwise, create/clear the per-page CPU read domain flag if we're
3307 * newly adding I915_GEM_DOMAIN_CPU
3308 */
05394f39
CW		 3309 if (obj->page_cpu_valid == NULL) {
3310 obj->page_cpu_valid = kzalloc(obj->base.size / PAGE_SIZE,
3311 GFP_KERNEL);
3312 if (obj->page_cpu_valid == NULL)
e47c68e9 3313 return -ENOMEM;
05394f39
CW		 3314 } else if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0)
3315 memset(obj->page_cpu_valid, 0, obj->base.size / PAGE_SIZE);
673a394b
EA		 3316
3317 /* Flush the cache on any pages that are still invalid from the CPU's
3318 * perspective.
3319 */
e47c68e9
EA		 3320 for (i = offset / PAGE_SIZE; i <= (offset + size - 1) / PAGE_SIZE;
3321 i++) {
05394f39 3322 if (obj->page_cpu_valid[i])
673a394b
EA		 3323 continue;
3324
05394f39 3325 drm_clflush_pages(obj->pages + i, 1);
673a394b 3326
05394f39 3327 obj->page_cpu_valid[i] = 1;
673a394b
EA		 3328 }
3329
e47c68e9
EA		 3330 /* It should now be out of any other write domains, and we can update
3331 * the domain values for our changes.
3332 */
05394f39 3333 BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
e47c68e9 3334
05394f39
CW		 3335 old_read_domains = obj->base.read_domains;
3336 obj->base.read_domains |= I915_GEM_DOMAIN_CPU;
e47c68e9 3337
1c5d22f7
CW		 3338 trace_i915_gem_object_change_domain(obj,
3339 old_read_domains,
05394f39 3340 obj->base.write_domain);
1c5d22f7 3341
673a394b
EA		 3342 return 0;
3343}
3344
673a394b
EA		 3345/* Throttle our rendering by waiting until the ring has completed our requests
3346 * emitted over 20 msec ago.
3347 *
b962442e
EA		 3348 * Note that if we were to use the current jiffies each time around the loop,
3349 * we wouldn't escape the function with any frames outstanding if the time to
3350 * render a frame was over 20ms.
3351 *
673a394b
EA		 3352 * This should get us reasonable parallelism between CPU and GPU but also
3353 * relatively low latency when blocking on a particular request to finish.
3354 */
40a5f0de 3355static int
f787a5f5 3356i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file)
40a5f0de 3357{
f787a5f5
CW		 3358 struct drm_i915_private *dev_priv = dev->dev_private;
3359 struct drm_i915_file_private *file_priv = file->driver_priv;
b962442e 3360 unsigned long recent_enough = jiffies - msecs_to_jiffies(20);
f787a5f5
CW		 3361 struct drm_i915_gem_request *request;
3362 struct intel_ring_buffer *ring = NULL;
3363 u32 seqno = 0;
3364 int ret;
93533c29 3365
e110e8d6
CW		 3366 if (atomic_read(&dev_priv->mm.wedged))
3367 return -EIO;
3368
1c25595f 3369 spin_lock(&file_priv->mm.lock);
f787a5f5 3370 list_for_each_entry(request, &file_priv->mm.request_list, client_list) {
b962442e
EA		 3371 if (time_after_eq(request->emitted_jiffies, recent_enough))
3372 break;
40a5f0de 3373
f787a5f5
CW		 3374 ring = request->ring;
3375 seqno = request->seqno;
b962442e 3376 }
1c25595f 3377 spin_unlock(&file_priv->mm.lock);
40a5f0de 3378
f787a5f5
CW		 3379 if (seqno == 0)
3380 return 0;
2bc43b5c 3381
f787a5f5 3382 ret = 0;
78501eac 3383 if (!i915_seqno_passed(ring->get_seqno(ring), seqno)) {
f787a5f5
CW		 3384 /* And wait for the seqno passing without holding any locks and
3385 * causing extra latency for others. This is safe as the irq
3386 * generation is designed to be run atomically and so is
3387 * lockless.
3388 */
b13c2b96
CW		 3389 if (ring->irq_get(ring)) {
3390 ret = wait_event_interruptible(ring->irq_queue,
3391 i915_seqno_passed(ring->get_seqno(ring), seqno)
3392 || atomic_read(&dev_priv->mm.wedged));
3393 ring->irq_put(ring);
40a5f0de 3394
b13c2b96
CW		 3395 if (ret == 0 && atomic_read(&dev_priv->mm.wedged))
3396 ret = -EIO;
3397 }
40a5f0de
EA		 3398 }
3399
f787a5f5
CW		 3400 if (ret == 0)
3401 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, 0);
40a5f0de
EA		 3402
3403 return ret;
3404}
3405
673a394b 3406int
05394f39
CW		 3407i915_gem_object_pin(struct drm_i915_gem_object *obj,
3408 uint32_t alignment,
75e9e915 3409 bool map_and_fenceable)
673a394b 3410{
05394f39 3411 struct drm_device *dev = obj->base.dev;
f13d3f73 3412 struct drm_i915_private *dev_priv = dev->dev_private;
673a394b
EA		 3413 int ret;
3414
05394f39 3415 BUG_ON(obj->pin_count == DRM_I915_GEM_OBJECT_MAX_PIN_COUNT);
23bc5982 3416 WARN_ON(i915_verify_lists(dev));
ac0c6b5a 3417
05394f39
CW		 3418 if (obj->gtt_space != NULL) {
3419 if ((alignment && obj->gtt_offset & (alignment - 1)) ||
3420 (map_and_fenceable && !obj->map_and_fenceable)) {
3421 WARN(obj->pin_count,
ae7d49d8 3422 "bo is already pinned with incorrect alignment:"
75e9e915
DV		 3423 " offset=%x, req.alignment=%x, req.map_and_fenceable=%d,"
3424 " obj->map_and_fenceable=%d\n",
05394f39 3425 obj->gtt_offset, alignment,
75e9e915 3426 map_and_fenceable,
05394f39 3427 obj->map_and_fenceable);
ac0c6b5a
CW		 3428 ret = i915_gem_object_unbind(obj);
3429 if (ret)
3430 return ret;
3431 }
3432 }
3433
05394f39 3434 if (obj->gtt_space == NULL) {
a00b10c3 3435 ret = i915_gem_object_bind_to_gtt(obj, alignment,
75e9e915 3436 map_and_fenceable);
9731129c 3437 if (ret)
673a394b 3438 return ret;
22c344e9 3439 }
76446cac 3440
05394f39 3441 if (obj->pin_count++ == 0) {
05394f39
CW		 3442 if (!obj->active)
3443 list_move_tail(&obj->mm_list,
f13d3f73 3444 &dev_priv->mm.pinned_list);
673a394b 3445 }
6299f992 3446 obj->pin_mappable |= map_and_fenceable;
673a394b 3447
23bc5982 3448 WARN_ON(i915_verify_lists(dev));
673a394b
EA		 3449 return 0;
3450}
3451
3452void
05394f39 3453i915_gem_object_unpin(struct drm_i915_gem_object *obj)
673a394b 3454{
05394f39 3455 struct drm_device *dev = obj->base.dev;
673a394b 3456 drm_i915_private_t *dev_priv = dev->dev_private;
673a394b 3457
23bc5982 3458 WARN_ON(i915_verify_lists(dev));
05394f39
CW		 3459 BUG_ON(obj->pin_count == 0);
3460 BUG_ON(obj->gtt_space == NULL);
673a394b 3461
05394f39
CW		 3462 if (--obj->pin_count == 0) {
3463 if (!obj->active)
3464 list_move_tail(&obj->mm_list,
673a394b 3465 &dev_priv->mm.inactive_list);
6299f992 3466 obj->pin_mappable = false;
673a394b 3467 }
23bc5982 3468 WARN_ON(i915_verify_lists(dev));
673a394b
EA		 3469}
3470
3471int
3472i915_gem_pin_ioctl(struct drm_device *dev, void *data,
05394f39 3473 struct drm_file *file)
673a394b
EA		 3474{
3475 struct drm_i915_gem_pin *args = data;
05394f39 3476 struct drm_i915_gem_object *obj;
673a394b
EA		 3477 int ret;
3478
1d7cfea1
CW		 3479 ret = i915_mutex_lock_interruptible(dev);
3480 if (ret)
3481 return ret;
673a394b 3482
05394f39 3483 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
c8725226 3484 if (&obj->base == NULL) {
1d7cfea1
CW		 3485 ret = -ENOENT;
3486 goto unlock;
673a394b 3487 }
673a394b 3488
05394f39 3489 if (obj->madv != I915_MADV_WILLNEED) {
bb6baf76 3490 DRM_ERROR("Attempting to pin a purgeable buffer\n");
1d7cfea1
CW		 3491 ret = -EINVAL;
3492 goto out;
3ef94daa
CW		 3493 }
3494
05394f39 3495 if (obj->pin_filp != NULL && obj->pin_filp != file) {
79e53945
JB		 3496 DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n",
3497 args->handle);
1d7cfea1
CW		 3498 ret = -EINVAL;
3499 goto out;
79e53945
JB		 3500 }
3501
05394f39
CW		 3502 obj->user_pin_count++;
3503 obj->pin_filp = file;
3504 if (obj->user_pin_count == 1) {
75e9e915 3505 ret = i915_gem_object_pin(obj, args->alignment, true);
1d7cfea1
CW		 3506 if (ret)
3507 goto out;
673a394b
EA		 3508 }
3509
3510 /* XXX - flush the CPU caches for pinned objects
3511 * as the X server doesn't manage domains yet
3512 */
e47c68e9 3513 i915_gem_object_flush_cpu_write_domain(obj);
05394f39 3514 args->offset = obj->gtt_offset;
1d7cfea1 3515out:
05394f39 3516 drm_gem_object_unreference(&obj->base);
1d7cfea1 3517unlock:
673a394b 3518 mutex_unlock(&dev->struct_mutex);
1d7cfea1 3519 return ret;
673a394b
EA		 3520}
3521
3522int
3523i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
05394f39 3524 struct drm_file *file)
673a394b
EA		 3525{
3526 struct drm_i915_gem_pin *args = data;
05394f39 3527 struct drm_i915_gem_object *obj;
76c1dec1 3528 int ret;
673a394b 3529
1d7cfea1
CW		 3530 ret = i915_mutex_lock_interruptible(dev);
3531 if (ret)
3532 return ret;
673a394b 3533
05394f39 3534 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
c8725226 3535 if (&obj->base == NULL) {
1d7cfea1
CW		 3536 ret = -ENOENT;
3537 goto unlock;
673a394b 3538 }
76c1dec1 3539
05394f39 3540 if (obj->pin_filp != file) {
79e53945
JB		 3541 DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n",
3542 args->handle);
1d7cfea1
CW		 3543 ret = -EINVAL;
3544 goto out;
79e53945 3545 }
05394f39
CW		 3546 obj->user_pin_count--;
3547 if (obj->user_pin_count == 0) {
3548 obj->pin_filp = NULL;
79e53945
JB		 3549 i915_gem_object_unpin(obj);
3550 }
673a394b 3551
1d7cfea1 3552out:
05394f39 3553 drm_gem_object_unreference(&obj->base);
1d7cfea1 3554unlock:
673a394b 3555 mutex_unlock(&dev->struct_mutex);
1d7cfea1 3556 return ret;
673a394b
EA		 3557}
3558
3559int
3560i915_gem_busy_ioctl(struct drm_device *dev, void *data,
05394f39 3561 struct drm_file *file)
673a394b
EA		 3562{
3563 struct drm_i915_gem_busy *args = data;
05394f39 3564 struct drm_i915_gem_object *obj;
30dbf0c0
CW		 3565 int ret;
3566
76c1dec1 3567 ret = i915_mutex_lock_interruptible(dev);
1d7cfea1 3568 if (ret)
76c1dec1 3569 return ret;
673a394b 3570
05394f39 3571 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
c8725226 3572 if (&obj->base == NULL) {
1d7cfea1
CW		 3573 ret = -ENOENT;
3574 goto unlock;
673a394b 3575 }
d1b851fc 3576
0be555b6
CW		 3577 /* Count all active objects as busy, even if they are currently not used
3578 * by the gpu. Users of this interface expect objects to eventually
3579 * become non-busy without any further actions, therefore emit any
3580 * necessary flushes here.
c4de0a5d 3581 */
05394f39 3582 args->busy = obj->active;
0be555b6
CW		 3583 if (args->busy) {
3584 /* Unconditionally flush objects, even when the gpu still uses this
3585 * object. Userspace calling this function indicates that it wants to
3586 * use this buffer rather sooner than later, so issuing the required
3587 * flush earlier is beneficial.
3588 */
1a1c6976 3589 if (obj->base.write_domain & I915_GEM_GPU_DOMAINS) {
db53a302 3590 ret = i915_gem_flush_ring(obj->ring,
88241785 3591 0, obj->base.write_domain);
1a1c6976
CW		 3592 } else if (obj->ring->outstanding_lazy_request ==
3593 obj->last_rendering_seqno) {
3594 struct drm_i915_gem_request *request;
3595
7a194876
CW		 3596 /* This ring is not being cleared by active usage,
3597 * so emit a request to do so.
3598 */
1a1c6976
CW		 3599 request = kzalloc(sizeof(*request), GFP_KERNEL);
3600 if (request)
db53a302 3601 ret = i915_add_request(obj->ring, NULL,request);
1a1c6976 3602 else
7a194876
CW		 3603 ret = -ENOMEM;
3604 }
0be555b6
CW		 3605
3606 /* Update the active list for the hardware's current position.
3607 * Otherwise this only updates on a delayed timer or when irqs
3608 * are actually unmasked, and our working set ends up being
3609 * larger than required.
3610 */
db53a302 3611 i915_gem_retire_requests_ring(obj->ring);
0be555b6 3612
05394f39 3613 args->busy = obj->active;
0be555b6 3614 }
673a394b 3615
05394f39 3616 drm_gem_object_unreference(&obj->base);
1d7cfea1 3617unlock:
673a394b 3618 mutex_unlock(&dev->struct_mutex);
1d7cfea1 3619 return ret;
673a394b
EA		 3620}
3621
3622int
3623i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
3624 struct drm_file *file_priv)
3625{
3626 return i915_gem_ring_throttle(dev, file_priv);
3627}
3628
3ef94daa
CW		 3629int
3630i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
3631 struct drm_file *file_priv)
3632{
3633 struct drm_i915_gem_madvise *args = data;
05394f39 3634 struct drm_i915_gem_object *obj;
76c1dec1 3635 int ret;
3ef94daa
CW		 3636
3637 switch (args->madv) {
3638 case I915_MADV_DONTNEED:
3639 case I915_MADV_WILLNEED:
3640 break;
3641 default:
3642 return -EINVAL;
3643 }
3644
1d7cfea1
CW		 3645 ret = i915_mutex_lock_interruptible(dev);
3646 if (ret)
3647 return ret;
3648
05394f39 3649 obj = to_intel_bo(drm_gem_object_lookup(dev, file_priv, args->handle));
c8725226 3650 if (&obj->base == NULL) {
1d7cfea1
CW		 3651 ret = -ENOENT;
3652 goto unlock;
3ef94daa 3653 }
3ef94daa 3654
05394f39 3655 if (obj->pin_count) {
1d7cfea1
CW		 3656 ret = -EINVAL;
3657 goto out;
3ef94daa
CW		 3658 }
3659
05394f39
CW		 3660 if (obj->madv != __I915_MADV_PURGED)
3661 obj->madv = args->madv;
3ef94daa 3662
2d7ef395 3663 /* if the object is no longer bound, discard its backing storage */
05394f39
CW		 3664 if (i915_gem_object_is_purgeable(obj) &&
3665 obj->gtt_space == NULL)
2d7ef395
CW		 3666 i915_gem_object_truncate(obj);
3667
05394f39 3668 args->retained = obj->madv != __I915_MADV_PURGED;
bb6baf76 3669
1d7cfea1 3670out:
05394f39 3671 drm_gem_object_unreference(&obj->base);
1d7cfea1 3672unlock:
3ef94daa 3673 mutex_unlock(&dev->struct_mutex);
1d7cfea1 3674 return ret;
3ef94daa
CW		 3675}
3676
05394f39
CW		 3677struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev,
3678 size_t size)
ac52bc56 3679{
73aa808f 3680 struct drm_i915_private *dev_priv = dev->dev_private;
c397b908 3681 struct drm_i915_gem_object *obj;
5949eac4 3682 struct address_space *mapping;
ac52bc56 3683
c397b908
DV		 3684 obj = kzalloc(sizeof(*obj), GFP_KERNEL);
3685 if (obj == NULL)
3686 return NULL;
673a394b 3687
c397b908
DV		 3688 if (drm_gem_object_init(dev, &obj->base, size) != 0) {
3689 kfree(obj);
3690 return NULL;
3691 }
673a394b 3692
5949eac4
HD		 3693 mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping;
3694 mapping_set_gfp_mask(mapping, GFP_HIGHUSER | __GFP_RECLAIMABLE);
3695
73aa808f
CW		 3696 i915_gem_info_add_obj(dev_priv, size);
3697
c397b908
DV		 3698 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
3699 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
673a394b 3700
a1871112
EA		 3701 if (IS_GEN6(dev)) {
3702 /* On Gen6, we can have the GPU use the LLC (the CPU
3703 * cache) for about a 10% performance improvement
3704 * compared to uncached. Graphics requests other than
3705 * display scanout are coherent with the CPU in
3706 * accessing this cache. This means in this mode we
3707 * don't need to clflush on the CPU side, and on the
3708 * GPU side we only need to flush internal caches to
3709 * get data visible to the CPU.
3710 *
3711 * However, we maintain the display planes as UC, and so
3712 * need to rebind when first used as such.
3713 */
3714 obj->cache_level = I915_CACHE_LLC;
3715 } else
3716 obj->cache_level = I915_CACHE_NONE;
3717
62b8b215 3718 obj->base.driver_private = NULL;
c397b908 3719 obj->fence_reg = I915_FENCE_REG_NONE;
69dc4987 3720 INIT_LIST_HEAD(&obj->mm_list);
93a37f20 3721 INIT_LIST_HEAD(&obj->gtt_list);
69dc4987 3722 INIT_LIST_HEAD(&obj->ring_list);
432e58ed 3723 INIT_LIST_HEAD(&obj->exec_list);
c397b908 3724 INIT_LIST_HEAD(&obj->gpu_write_list);
c397b908 3725 obj->madv = I915_MADV_WILLNEED;
75e9e915
DV		 3726 /* Avoid an unnecessary call to unbind on the first bind. */
3727 obj->map_and_fenceable = true;
de151cf6 3728
05394f39 3729 return obj;
c397b908
DV		 3730}
3731
3732int i915_gem_init_object(struct drm_gem_object *obj)
3733{
3734 BUG();
de151cf6 3735
673a394b
EA		 3736 return 0;
3737}
3738
05394f39 3739static void i915_gem_free_object_tail(struct drm_i915_gem_object *obj)
673a394b 3740{
05394f39 3741 struct drm_device *dev = obj->base.dev;
be72615b 3742 drm_i915_private_t *dev_priv = dev->dev_private;
be72615b 3743 int ret;
673a394b 3744
be72615b
CW		 3745 ret = i915_gem_object_unbind(obj);
3746 if (ret == -ERESTARTSYS) {
05394f39 3747 list_move(&obj->mm_list,
be72615b
CW		 3748 &dev_priv->mm.deferred_free_list);
3749 return;
3750 }
673a394b 3751
26e12f89
CW		 3752 trace_i915_gem_object_destroy(obj);
3753
05394f39 3754 if (obj->base.map_list.map)
7e616158 3755 i915_gem_free_mmap_offset(obj);
de151cf6 3756
05394f39
CW		 3757 drm_gem_object_release(&obj->base);
3758 i915_gem_info_remove_obj(dev_priv, obj->base.size);
c397b908 3759
05394f39
CW		 3760 kfree(obj->page_cpu_valid);
3761 kfree(obj->bit_17);
3762 kfree(obj);
673a394b
EA		 3763}
3764
05394f39 3765void i915_gem_free_object(struct drm_gem_object *gem_obj)
be72615b 3766{
05394f39
CW		 3767 struct drm_i915_gem_object *obj = to_intel_bo(gem_obj);
3768 struct drm_device *dev = obj->base.dev;
be72615b 3769
05394f39 3770 while (obj->pin_count > 0)
be72615b
CW		 3771 i915_gem_object_unpin(obj);
3772
05394f39 3773 if (obj->phys_obj)
be72615b
CW		 3774 i915_gem_detach_phys_object(dev, obj);
3775
3776 i915_gem_free_object_tail(obj);
3777}
3778
29105ccc
CW		 3779int
3780i915_gem_idle(struct drm_device *dev)
3781{
3782 drm_i915_private_t *dev_priv = dev->dev_private;
3783 int ret;
28dfe52a 3784
29105ccc 3785 mutex_lock(&dev->struct_mutex);
1c5d22f7 3786
87acb0a5 3787 if (dev_priv->mm.suspended) {
29105ccc
CW		 3788 mutex_unlock(&dev->struct_mutex);
3789 return 0;
28dfe52a
EA		 3790 }
3791
29105ccc 3792 ret = i915_gpu_idle(dev);
6dbe2772
KP		 3793 if (ret) {
3794 mutex_unlock(&dev->struct_mutex);
673a394b 3795 return ret;
6dbe2772 3796 }
673a394b 3797
29105ccc
CW		 3798 /* Under UMS, be paranoid and evict. */
3799 if (!drm_core_check_feature(dev, DRIVER_MODESET)) {
5eac3ab4 3800 ret = i915_gem_evict_inactive(dev, false);
29105ccc
CW		 3801 if (ret) {
3802 mutex_unlock(&dev->struct_mutex);
3803 return ret;
3804 }
3805 }
3806
312817a3
CW		 3807 i915_gem_reset_fences(dev);
3808
29105ccc
CW		 3809 /* Hack! Don't let anybody do execbuf while we don't control the chip.
3810 * We need to replace this with a semaphore, or something.
3811 * And not confound mm.suspended!
3812 */
3813 dev_priv->mm.suspended = 1;
bc0c7f14 3814 del_timer_sync(&dev_priv->hangcheck_timer);
29105ccc
CW		 3815
3816 i915_kernel_lost_context(dev);
6dbe2772 3817 i915_gem_cleanup_ringbuffer(dev);
29105ccc 3818
6dbe2772
KP		 3819 mutex_unlock(&dev->struct_mutex);
3820
29105ccc
CW		 3821 /* Cancel the retire work handler, which should be idle now. */
3822 cancel_delayed_work_sync(&dev_priv->mm.retire_work);
3823
673a394b
EA		 3824 return 0;
3825}
3826
8187a2b7
ZN		 3827int
3828i915_gem_init_ringbuffer(struct drm_device *dev)
3829{
3830 drm_i915_private_t *dev_priv = dev->dev_private;
3831 int ret;
68f95ba9 3832
5c1143bb 3833 ret = intel_init_render_ring_buffer(dev);
68f95ba9 3834 if (ret)
b6913e4b 3835 return ret;
68f95ba9
CW		 3836
3837 if (HAS_BSD(dev)) {
5c1143bb 3838 ret = intel_init_bsd_ring_buffer(dev);
68f95ba9
CW		 3839 if (ret)
3840 goto cleanup_render_ring;
d1b851fc 3841 }
68f95ba9 3842
549f7365
CW		 3843 if (HAS_BLT(dev)) {
3844 ret = intel_init_blt_ring_buffer(dev);
3845 if (ret)
3846 goto cleanup_bsd_ring;
3847 }
3848
6f392d54
CW		 3849 dev_priv->next_seqno = 1;
3850
68f95ba9
CW		 3851 return 0;
3852
549f7365 3853cleanup_bsd_ring:
1ec14ad3 3854 intel_cleanup_ring_buffer(&dev_priv->ring[VCS]);
68f95ba9 3855cleanup_render_ring:
1ec14ad3 3856 intel_cleanup_ring_buffer(&dev_priv->ring[RCS]);
8187a2b7
ZN		 3857 return ret;
3858}
3859
3860void
3861i915_gem_cleanup_ringbuffer(struct drm_device *dev)
3862{
3863 drm_i915_private_t *dev_priv = dev->dev_private;
1ec14ad3 3864 int i;
8187a2b7 3865
1ec14ad3
CW		 3866 for (i = 0; i < I915_NUM_RINGS; i++)
3867 intel_cleanup_ring_buffer(&dev_priv->ring[i]);
8187a2b7
ZN		 3868}
3869
673a394b
EA		 3870int
3871i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
3872 struct drm_file *file_priv)
3873{
3874 drm_i915_private_t *dev_priv = dev->dev_private;
1ec14ad3 3875 int ret, i;
673a394b 3876
79e53945
JB		 3877 if (drm_core_check_feature(dev, DRIVER_MODESET))
3878 return 0;
3879
ba1234d1 3880 if (atomic_read(&dev_priv->mm.wedged)) {
673a394b 3881 DRM_ERROR("Reenabling wedged hardware, good luck\n");
ba1234d1 3882 atomic_set(&dev_priv->mm.wedged, 0);
673a394b
EA		 3883 }
3884
673a394b 3885 mutex_lock(&dev->struct_mutex);
9bb2d6f9
EA		 3886 dev_priv->mm.suspended = 0;
3887
3888 ret = i915_gem_init_ringbuffer(dev);
d816f6ac
WF		 3889 if (ret != 0) {
3890 mutex_unlock(&dev->struct_mutex);
9bb2d6f9 3891 return ret;
d816f6ac 3892 }
9bb2d6f9 3893
69dc4987 3894 BUG_ON(!list_empty(&dev_priv->mm.active_list));
673a394b
EA		 3895 BUG_ON(!list_empty(&dev_priv->mm.flushing_list));
3896 BUG_ON(!list_empty(&dev_priv->mm.inactive_list));
1ec14ad3
CW		 3897 for (i = 0; i < I915_NUM_RINGS; i++) {
3898 BUG_ON(!list_empty(&dev_priv->ring[i].active_list));
3899 BUG_ON(!list_empty(&dev_priv->ring[i].request_list));
3900 }
673a394b 3901 mutex_unlock(&dev->struct_mutex);
dbb19d30 3902
5f35308b
CW		 3903 ret = drm_irq_install(dev);
3904 if (ret)
3905 goto cleanup_ringbuffer;
dbb19d30 3906
673a394b 3907 return 0;
5f35308b
CW		 3908
3909cleanup_ringbuffer:
3910 mutex_lock(&dev->struct_mutex);
3911 i915_gem_cleanup_ringbuffer(dev);
3912 dev_priv->mm.suspended = 1;
3913 mutex_unlock(&dev->struct_mutex);
3914
3915 return ret;
673a394b
EA		 3916}
3917
3918int
3919i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
3920 struct drm_file *file_priv)
3921{
79e53945
JB		 3922 if (drm_core_check_feature(dev, DRIVER_MODESET))
3923 return 0;
3924
dbb19d30 3925 drm_irq_uninstall(dev);
e6890f6f 3926 return i915_gem_idle(dev);
673a394b
EA		 3927}
3928
3929void
3930i915_gem_lastclose(struct drm_device *dev)
3931{
3932 int ret;
673a394b 3933
e806b495
EA		 3934 if (drm_core_check_feature(dev, DRIVER_MODESET))
3935 return;
3936
6dbe2772
KP		 3937 ret = i915_gem_idle(dev);
3938 if (ret)
3939 DRM_ERROR("failed to idle hardware: %d\n", ret);
673a394b
EA		 3940}
3941
64193406
CW		 3942static void
3943init_ring_lists(struct intel_ring_buffer *ring)
3944{
3945 INIT_LIST_HEAD(&ring->active_list);
3946 INIT_LIST_HEAD(&ring->request_list);
3947 INIT_LIST_HEAD(&ring->gpu_write_list);
3948}
3949
673a394b
EA		 3950void
3951i915_gem_load(struct drm_device *dev)
3952{
b5aa8a0f 3953 int i;
673a394b
EA		 3954 drm_i915_private_t *dev_priv = dev->dev_private;
3955
69dc4987 3956 INIT_LIST_HEAD(&dev_priv->mm.active_list);
673a394b
EA		 3957 INIT_LIST_HEAD(&dev_priv->mm.flushing_list);
3958 INIT_LIST_HEAD(&dev_priv->mm.inactive_list);
f13d3f73 3959 INIT_LIST_HEAD(&dev_priv->mm.pinned_list);
a09ba7fa 3960 INIT_LIST_HEAD(&dev_priv->mm.fence_list);
be72615b 3961 INIT_LIST_HEAD(&dev_priv->mm.deferred_free_list);
93a37f20 3962 INIT_LIST_HEAD(&dev_priv->mm.gtt_list);
1ec14ad3
CW		 3963 for (i = 0; i < I915_NUM_RINGS; i++)
3964 init_ring_lists(&dev_priv->ring[i]);
007cc8ac
DV		 3965 for (i = 0; i < 16; i++)
3966 INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list);
673a394b
EA		 3967 INIT_DELAYED_WORK(&dev_priv->mm.retire_work,
3968 i915_gem_retire_work_handler);
30dbf0c0 3969 init_completion(&dev_priv->error_completion);
31169714 3970
94400120
DA		 3971 /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
3972 if (IS_GEN3(dev)) {
3973 u32 tmp = I915_READ(MI_ARB_STATE);
3974 if (!(tmp & MI_ARB_C3_LP_WRITE_ENABLE)) {
3975 /* arb state is a masked write, so set bit + bit in mask */
3976 tmp = MI_ARB_C3_LP_WRITE_ENABLE | (MI_ARB_C3_LP_WRITE_ENABLE << MI_ARB_MASK_SHIFT);
3977 I915_WRITE(MI_ARB_STATE, tmp);
3978 }
3979 }
3980
72bfa19c
CW		 3981 dev_priv->relative_constants_mode = I915_EXEC_CONSTANTS_REL_GENERAL;
3982
de151cf6 3983 /* Old X drivers will take 0-2 for front, back, depth buffers */
b397c836
EA		 3984 if (!drm_core_check_feature(dev, DRIVER_MODESET))
3985 dev_priv->fence_reg_start = 3;
de151cf6 3986
a6c45cf0 3987 if (INTEL_INFO(dev)->gen >= 4 || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
de151cf6
JB		 3988 dev_priv->num_fence_regs = 16;
3989 else
3990 dev_priv->num_fence_regs = 8;
3991
b5aa8a0f 3992 /* Initialize fence registers to zero */
10ed13e4
EA		 3993 for (i = 0; i < dev_priv->num_fence_regs; i++) {
3994 i915_gem_clear_fence_reg(dev, &dev_priv->fence_regs[i]);
b5aa8a0f 3995 }
10ed13e4 3996
673a394b 3997 i915_gem_detect_bit_6_swizzle(dev);
6b95a207 3998 init_waitqueue_head(&dev_priv->pending_flip_queue);
17250b71 3999
ce453d81
CW		 4000 dev_priv->mm.interruptible = true;
4001
17250b71
CW		 4002 dev_priv->mm.inactive_shrinker.shrink = i915_gem_inactive_shrink;
4003 dev_priv->mm.inactive_shrinker.seeks = DEFAULT_SEEKS;
4004 register_shrinker(&dev_priv->mm.inactive_shrinker);
673a394b 4005}
71acb5eb
DA		 4006
4007/*
4008 * Create a physically contiguous memory object for this object
4009 * e.g. for cursor + overlay regs
4010 */
995b6762
CW		 4011static int i915_gem_init_phys_object(struct drm_device *dev,
4012 int id, int size, int align)
71acb5eb
DA		 4013{
4014 drm_i915_private_t *dev_priv = dev->dev_private;
4015 struct drm_i915_gem_phys_object *phys_obj;
4016 int ret;
4017
4018 if (dev_priv->mm.phys_objs[id - 1] || !size)
4019 return 0;
4020
9a298b2a 4021 phys_obj = kzalloc(sizeof(struct drm_i915_gem_phys_object), GFP_KERNEL);
71acb5eb
DA		 4022 if (!phys_obj)
4023 return -ENOMEM;
4024
4025 phys_obj->id = id;
4026
6eeefaf3 4027 phys_obj->handle = drm_pci_alloc(dev, size, align);
71acb5eb
DA		 4028 if (!phys_obj->handle) {
4029 ret = -ENOMEM;
4030 goto kfree_obj;
4031 }
4032#ifdef CONFIG_X86
4033 set_memory_wc((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE);
4034#endif
4035
4036 dev_priv->mm.phys_objs[id - 1] = phys_obj;
4037
4038 return 0;
4039kfree_obj:
9a298b2a 4040 kfree(phys_obj);
71acb5eb
DA		 4041 return ret;
4042}
4043
995b6762 4044static void i915_gem_free_phys_object(struct drm_device *dev, int id)
71acb5eb
DA		 4045{
4046 drm_i915_private_t *dev_priv = dev->dev_private;
4047 struct drm_i915_gem_phys_object *phys_obj;
4048
4049 if (!dev_priv->mm.phys_objs[id - 1])
4050 return;
4051
4052 phys_obj = dev_priv->mm.phys_objs[id - 1];
4053 if (phys_obj->cur_obj) {
4054 i915_gem_detach_phys_object(dev, phys_obj->cur_obj);
4055 }
4056
4057#ifdef CONFIG_X86
4058 set_memory_wb((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE);
4059#endif
4060 drm_pci_free(dev, phys_obj->handle);
4061 kfree(phys_obj);
4062 dev_priv->mm.phys_objs[id - 1] = NULL;
4063}
4064
4065void i915_gem_free_all_phys_object(struct drm_device *dev)
4066{
4067 int i;
4068
260883c8 4069 for (i = I915_GEM_PHYS_CURSOR_0; i <= I915_MAX_PHYS_OBJECT; i++)
71acb5eb
DA		 4070 i915_gem_free_phys_object(dev, i);
4071}
4072
4073void i915_gem_detach_phys_object(struct drm_device *dev,
05394f39 4074 struct drm_i915_gem_object *obj)
71acb5eb 4075{
05394f39 4076 struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping;
e5281ccd 4077 char *vaddr;
71acb5eb 4078 int i;
71acb5eb
DA		 4079 int page_count;
4080
05394f39 4081 if (!obj->phys_obj)
71acb5eb 4082 return;
05394f39 4083 vaddr = obj->phys_obj->handle->vaddr;
71acb5eb 4084
05394f39 4085 page_count = obj->base.size / PAGE_SIZE;
71acb5eb 4086 for (i = 0; i < page_count; i++) {
5949eac4 4087 struct page *page = shmem_read_mapping_page(mapping, i);
e5281ccd
CW		 4088 if (!IS_ERR(page)) {
4089 char *dst = kmap_atomic(page);
4090 memcpy(dst, vaddr + i*PAGE_SIZE, PAGE_SIZE);
4091 kunmap_atomic(dst);
4092
4093 drm_clflush_pages(&page, 1);
4094
4095 set_page_dirty(page);
4096 mark_page_accessed(page);
4097 page_cache_release(page);
4098 }
71acb5eb 4099 }
40ce6575 4100 intel_gtt_chipset_flush();
d78b47b9 4101
05394f39
CW		 4102 obj->phys_obj->cur_obj = NULL;
4103 obj->phys_obj = NULL;
71acb5eb
DA		 4104}
4105
4106int
4107i915_gem_attach_phys_object(struct drm_device *dev,
05394f39 4108 struct drm_i915_gem_object *obj,
6eeefaf3
CW		 4109 int id,
4110 int align)
71acb5eb 4111{
05394f39 4112 struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping;
71acb5eb 4113 drm_i915_private_t *dev_priv = dev->dev_private;
71acb5eb
DA		 4114 int ret = 0;
4115 int page_count;
4116 int i;
4117
4118 if (id > I915_MAX_PHYS_OBJECT)
4119 return -EINVAL;
4120
05394f39
CW		 4121 if (obj->phys_obj) {
4122 if (obj->phys_obj->id == id)
71acb5eb
DA		 4123 return 0;
4124 i915_gem_detach_phys_object(dev, obj);
4125 }
4126
71acb5eb
DA		 4127 /* create a new object */
4128 if (!dev_priv->mm.phys_objs[id - 1]) {
4129 ret = i915_gem_init_phys_object(dev, id,
05394f39 4130 obj->base.size, align);
71acb5eb 4131 if (ret) {
05394f39
CW		 4132 DRM_ERROR("failed to init phys object %d size: %zu\n",
4133 id, obj->base.size);
e5281ccd 4134 return ret;
71acb5eb
DA		 4135 }
4136 }
4137
4138 /* bind to the object */
05394f39
CW		 4139 obj->phys_obj = dev_priv->mm.phys_objs[id - 1];
4140 obj->phys_obj->cur_obj = obj;
71acb5eb 4141
05394f39 4142 page_count = obj->base.size / PAGE_SIZE;
71acb5eb
DA		 4143
4144 for (i = 0; i < page_count; i++) {
e5281ccd
CW		 4145 struct page *page;
4146 char *dst, *src;
4147
5949eac4 4148 page = shmem_read_mapping_page(mapping, i);
e5281ccd
CW		 4149 if (IS_ERR(page))
4150 return PTR_ERR(page);
71acb5eb 4151
ff75b9bc 4152 src = kmap_atomic(page);
05394f39 4153 dst = obj->phys_obj->handle->vaddr + (i * PAGE_SIZE);
71acb5eb 4154 memcpy(dst, src, PAGE_SIZE);
3e4d3af5 4155 kunmap_atomic(src);
71acb5eb 4156
e5281ccd
CW		 4157 mark_page_accessed(page);
4158 page_cache_release(page);
4159 }
d78b47b9 4160
71acb5eb 4161 return 0;
71acb5eb
DA		 4162}
4163
4164static int
05394f39
CW		 4165i915_gem_phys_pwrite(struct drm_device *dev,
4166 struct drm_i915_gem_object *obj,
71acb5eb
DA		 4167 struct drm_i915_gem_pwrite *args,
4168 struct drm_file *file_priv)
4169{
05394f39 4170 void *vaddr = obj->phys_obj->handle->vaddr + args->offset;
b47b30cc 4171 char __user *user_data = (char __user *) (uintptr_t) args->data_ptr;
71acb5eb 4172
b47b30cc
CW		 4173 if (__copy_from_user_inatomic_nocache(vaddr, user_data, args->size)) {
4174 unsigned long unwritten;
4175
4176 /* The physical object once assigned is fixed for the lifetime
4177 * of the obj, so we can safely drop the lock and continue
4178 * to access vaddr.
4179 */
4180 mutex_unlock(&dev->struct_mutex);
4181 unwritten = copy_from_user(vaddr, user_data, args->size);
4182 mutex_lock(&dev->struct_mutex);
4183 if (unwritten)
4184 return -EFAULT;
4185 }
71acb5eb 4186
40ce6575 4187 intel_gtt_chipset_flush();
71acb5eb
DA		 4188 return 0;
4189}
b962442e 4190
f787a5f5 4191void i915_gem_release(struct drm_device *dev, struct drm_file *file)
b962442e 4192{
f787a5f5 4193 struct drm_i915_file_private *file_priv = file->driver_priv;
b962442e
EA		 4194
4195 /* Clean up our request list when the client is going away, so that
4196 * later retire_requests won't dereference our soon-to-be-gone
4197 * file_priv.
4198 */
1c25595f 4199 spin_lock(&file_priv->mm.lock);
f787a5f5
CW		 4200 while (!list_empty(&file_priv->mm.request_list)) {
4201 struct drm_i915_gem_request *request;
4202
4203 request = list_first_entry(&file_priv->mm.request_list,
4204 struct drm_i915_gem_request,
4205 client_list);
4206 list_del(&request->client_list);
4207 request->file_priv = NULL;
4208 }
1c25595f 4209 spin_unlock(&file_priv->mm.lock);
b962442e 4210}
31169714 4211
1637ef41
CW		 4212static int
4213i915_gpu_is_active(struct drm_device *dev)
4214{
4215 drm_i915_private_t *dev_priv = dev->dev_private;
4216 int lists_empty;
4217
1637ef41 4218 lists_empty = list_empty(&dev_priv->mm.flushing_list) &&
17250b71 4219 list_empty(&dev_priv->mm.active_list);
1637ef41
CW		 4220
4221 return !lists_empty;
4222}
4223
31169714 4224static int
1495f230 4225i915_gem_inactive_shrink(struct shrinker *shrinker, struct shrink_control *sc)
31169714 4226{
17250b71
CW		 4227 struct drm_i915_private *dev_priv =
4228 container_of(shrinker,
4229 struct drm_i915_private,
4230 mm.inactive_shrinker);
4231 struct drm_device *dev = dev_priv->dev;
4232 struct drm_i915_gem_object *obj, *next;
1495f230 4233 int nr_to_scan = sc->nr_to_scan;
17250b71
CW		 4234 int cnt;
4235
4236 if (!mutex_trylock(&dev->struct_mutex))
bbe2e11a 4237 return 0;
31169714
CW		 4238
4239 /* "fast-path" to count number of available objects */
4240 if (nr_to_scan == 0) {
17250b71
CW		 4241 cnt = 0;
4242 list_for_each_entry(obj,
4243 &dev_priv->mm.inactive_list,
4244 mm_list)
4245 cnt++;
4246 mutex_unlock(&dev->struct_mutex);
4247 return cnt / 100 * sysctl_vfs_cache_pressure;
31169714
CW		 4248 }
4249
1637ef41 4250rescan:
31169714 4251 /* first scan for clean buffers */
17250b71 4252 i915_gem_retire_requests(dev);
31169714 4253
17250b71
CW		 4254 list_for_each_entry_safe(obj, next,
4255 &dev_priv->mm.inactive_list,
4256 mm_list) {
4257 if (i915_gem_object_is_purgeable(obj)) {
2021746e
CW		 4258 if (i915_gem_object_unbind(obj) == 0 &&
4259 --nr_to_scan == 0)
17250b71 4260 break;
31169714 4261 }
31169714
CW		 4262 }
4263
4264 /* second pass, evict/count anything still on the inactive list */
17250b71
CW		 4265 cnt = 0;
4266 list_for_each_entry_safe(obj, next,
4267 &dev_priv->mm.inactive_list,
4268 mm_list) {
2021746e
CW		 4269 if (nr_to_scan &&
4270 i915_gem_object_unbind(obj) == 0)
17250b71 4271 nr_to_scan--;
2021746e 4272 else
17250b71
CW		 4273 cnt++;
4274 }
4275
4276 if (nr_to_scan && i915_gpu_is_active(dev)) {
1637ef41
CW		 4277 /*
4278 * We are desperate for pages, so as a last resort, wait
4279 * for the GPU to finish and discard whatever we can.
4280 * This has a dramatic impact to reduce the number of
4281 * OOM-killer events whilst running the GPU aggressively.
4282 */
17250b71 4283 if (i915_gpu_idle(dev) == 0)
1637ef41
CW		 4284 goto rescan;
4285 }
17250b71
CW		 4286 mutex_unlock(&dev->struct_mutex);
4287 return cnt / 100 * sysctl_vfs_cache_pressure;
31169714 4288}
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