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Commit | Line | Data |
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673a394b EA |
1 | /* |
2 | * Copyright © 2008 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | * | |
26 | */ | |
27 | ||
760285e7 DH |
28 | #include <drm/drmP.h> |
29 | #include <drm/i915_drm.h> | |
673a394b | 30 | #include "i915_drv.h" |
1c5d22f7 | 31 | #include "i915_trace.h" |
652c393a | 32 | #include "intel_drv.h" |
5949eac4 | 33 | #include <linux/shmem_fs.h> |
5a0e3ad6 | 34 | #include <linux/slab.h> |
673a394b | 35 | #include <linux/swap.h> |
79e53945 | 36 | #include <linux/pci.h> |
1286ff73 | 37 | #include <linux/dma-buf.h> |
673a394b | 38 | |
05394f39 CW |
39 | static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj); |
40 | static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj); | |
88241785 CW |
41 | static __must_check int i915_gem_object_bind_to_gtt(struct drm_i915_gem_object *obj, |
42 | unsigned alignment, | |
86a1ee26 CW |
43 | bool map_and_fenceable, |
44 | bool nonblocking); | |
05394f39 CW |
45 | static int i915_gem_phys_pwrite(struct drm_device *dev, |
46 | struct drm_i915_gem_object *obj, | |
71acb5eb | 47 | struct drm_i915_gem_pwrite *args, |
05394f39 | 48 | struct drm_file *file); |
673a394b | 49 | |
61050808 CW |
50 | static void i915_gem_write_fence(struct drm_device *dev, int reg, |
51 | struct drm_i915_gem_object *obj); | |
52 | static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj, | |
53 | struct drm_i915_fence_reg *fence, | |
54 | bool enable); | |
55 | ||
17250b71 | 56 | static int i915_gem_inactive_shrink(struct shrinker *shrinker, |
1495f230 | 57 | struct shrink_control *sc); |
6c085a72 CW |
58 | static long i915_gem_purge(struct drm_i915_private *dev_priv, long target); |
59 | static void i915_gem_shrink_all(struct drm_i915_private *dev_priv); | |
8c59967c | 60 | static void i915_gem_object_truncate(struct drm_i915_gem_object *obj); |
31169714 | 61 | |
61050808 CW |
62 | static inline void i915_gem_object_fence_lost(struct drm_i915_gem_object *obj) |
63 | { | |
64 | if (obj->tiling_mode) | |
65 | i915_gem_release_mmap(obj); | |
66 | ||
67 | /* As we do not have an associated fence register, we will force | |
68 | * a tiling change if we ever need to acquire one. | |
69 | */ | |
5d82e3e6 | 70 | obj->fence_dirty = false; |
61050808 CW |
71 | obj->fence_reg = I915_FENCE_REG_NONE; |
72 | } | |
73 | ||
73aa808f CW |
74 | /* some bookkeeping */ |
75 | static void i915_gem_info_add_obj(struct drm_i915_private *dev_priv, | |
76 | size_t size) | |
77 | { | |
78 | dev_priv->mm.object_count++; | |
79 | dev_priv->mm.object_memory += size; | |
80 | } | |
81 | ||
82 | static void i915_gem_info_remove_obj(struct drm_i915_private *dev_priv, | |
83 | size_t size) | |
84 | { | |
85 | dev_priv->mm.object_count--; | |
86 | dev_priv->mm.object_memory -= size; | |
87 | } | |
88 | ||
21dd3734 | 89 | static int |
33196ded | 90 | i915_gem_wait_for_error(struct i915_gpu_error *error) |
30dbf0c0 | 91 | { |
30dbf0c0 CW |
92 | int ret; |
93 | ||
7abb690a DV |
94 | #define EXIT_COND (!i915_reset_in_progress(error) || \ |
95 | i915_terminally_wedged(error)) | |
1f83fee0 | 96 | if (EXIT_COND) |
30dbf0c0 CW |
97 | return 0; |
98 | ||
0a6759c6 DV |
99 | /* |
100 | * Only wait 10 seconds for the gpu reset to complete to avoid hanging | |
101 | * userspace. If it takes that long something really bad is going on and | |
102 | * we should simply try to bail out and fail as gracefully as possible. | |
103 | */ | |
1f83fee0 DV |
104 | ret = wait_event_interruptible_timeout(error->reset_queue, |
105 | EXIT_COND, | |
106 | 10*HZ); | |
0a6759c6 DV |
107 | if (ret == 0) { |
108 | DRM_ERROR("Timed out waiting for the gpu reset to complete\n"); | |
109 | return -EIO; | |
110 | } else if (ret < 0) { | |
30dbf0c0 | 111 | return ret; |
0a6759c6 | 112 | } |
1f83fee0 | 113 | #undef EXIT_COND |
30dbf0c0 | 114 | |
21dd3734 | 115 | return 0; |
30dbf0c0 CW |
116 | } |
117 | ||
54cf91dc | 118 | int i915_mutex_lock_interruptible(struct drm_device *dev) |
76c1dec1 | 119 | { |
33196ded | 120 | struct drm_i915_private *dev_priv = dev->dev_private; |
76c1dec1 CW |
121 | int ret; |
122 | ||
33196ded | 123 | ret = i915_gem_wait_for_error(&dev_priv->gpu_error); |
76c1dec1 CW |
124 | if (ret) |
125 | return ret; | |
126 | ||
127 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
128 | if (ret) | |
129 | return ret; | |
130 | ||
23bc5982 | 131 | WARN_ON(i915_verify_lists(dev)); |
76c1dec1 CW |
132 | return 0; |
133 | } | |
30dbf0c0 | 134 | |
7d1c4804 | 135 | static inline bool |
05394f39 | 136 | i915_gem_object_is_inactive(struct drm_i915_gem_object *obj) |
7d1c4804 | 137 | { |
6c085a72 | 138 | return obj->gtt_space && !obj->active; |
7d1c4804 CW |
139 | } |
140 | ||
79e53945 JB |
141 | int |
142 | i915_gem_init_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 143 | struct drm_file *file) |
79e53945 | 144 | { |
93d18799 | 145 | struct drm_i915_private *dev_priv = dev->dev_private; |
79e53945 | 146 | struct drm_i915_gem_init *args = data; |
2021746e | 147 | |
7bb6fb8d DV |
148 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
149 | return -ENODEV; | |
150 | ||
2021746e CW |
151 | if (args->gtt_start >= args->gtt_end || |
152 | (args->gtt_end | args->gtt_start) & (PAGE_SIZE - 1)) | |
153 | return -EINVAL; | |
79e53945 | 154 | |
f534bc0b DV |
155 | /* GEM with user mode setting was never supported on ilk and later. */ |
156 | if (INTEL_INFO(dev)->gen >= 5) | |
157 | return -ENODEV; | |
158 | ||
79e53945 | 159 | mutex_lock(&dev->struct_mutex); |
d7e5008f BW |
160 | i915_gem_setup_global_gtt(dev, args->gtt_start, args->gtt_end, |
161 | args->gtt_end); | |
93d18799 | 162 | dev_priv->gtt.mappable_end = args->gtt_end; |
673a394b EA |
163 | mutex_unlock(&dev->struct_mutex); |
164 | ||
2021746e | 165 | return 0; |
673a394b EA |
166 | } |
167 | ||
5a125c3c EA |
168 | int |
169 | i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 170 | struct drm_file *file) |
5a125c3c | 171 | { |
73aa808f | 172 | struct drm_i915_private *dev_priv = dev->dev_private; |
5a125c3c | 173 | struct drm_i915_gem_get_aperture *args = data; |
6299f992 CW |
174 | struct drm_i915_gem_object *obj; |
175 | size_t pinned; | |
5a125c3c | 176 | |
6299f992 | 177 | pinned = 0; |
73aa808f | 178 | mutex_lock(&dev->struct_mutex); |
6c085a72 | 179 | list_for_each_entry(obj, &dev_priv->mm.bound_list, gtt_list) |
1b50247a CW |
180 | if (obj->pin_count) |
181 | pinned += obj->gtt_space->size; | |
73aa808f | 182 | mutex_unlock(&dev->struct_mutex); |
5a125c3c | 183 | |
5d4545ae | 184 | args->aper_size = dev_priv->gtt.total; |
0206e353 | 185 | args->aper_available_size = args->aper_size - pinned; |
6299f992 | 186 | |
5a125c3c EA |
187 | return 0; |
188 | } | |
189 | ||
42dcedd4 CW |
190 | void *i915_gem_object_alloc(struct drm_device *dev) |
191 | { | |
192 | struct drm_i915_private *dev_priv = dev->dev_private; | |
193 | return kmem_cache_alloc(dev_priv->slab, GFP_KERNEL | __GFP_ZERO); | |
194 | } | |
195 | ||
196 | void i915_gem_object_free(struct drm_i915_gem_object *obj) | |
197 | { | |
198 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; | |
199 | kmem_cache_free(dev_priv->slab, obj); | |
200 | } | |
201 | ||
ff72145b DA |
202 | static int |
203 | i915_gem_create(struct drm_file *file, | |
204 | struct drm_device *dev, | |
205 | uint64_t size, | |
206 | uint32_t *handle_p) | |
673a394b | 207 | { |
05394f39 | 208 | struct drm_i915_gem_object *obj; |
a1a2d1d3 PP |
209 | int ret; |
210 | u32 handle; | |
673a394b | 211 | |
ff72145b | 212 | size = roundup(size, PAGE_SIZE); |
8ffc0246 CW |
213 | if (size == 0) |
214 | return -EINVAL; | |
673a394b EA |
215 | |
216 | /* Allocate the new object */ | |
ff72145b | 217 | obj = i915_gem_alloc_object(dev, size); |
673a394b EA |
218 | if (obj == NULL) |
219 | return -ENOMEM; | |
220 | ||
05394f39 | 221 | ret = drm_gem_handle_create(file, &obj->base, &handle); |
1dfd9754 | 222 | if (ret) { |
05394f39 CW |
223 | drm_gem_object_release(&obj->base); |
224 | i915_gem_info_remove_obj(dev->dev_private, obj->base.size); | |
42dcedd4 | 225 | i915_gem_object_free(obj); |
673a394b | 226 | return ret; |
1dfd9754 | 227 | } |
673a394b | 228 | |
202f2fef | 229 | /* drop reference from allocate - handle holds it now */ |
05394f39 | 230 | drm_gem_object_unreference(&obj->base); |
202f2fef CW |
231 | trace_i915_gem_object_create(obj); |
232 | ||
ff72145b | 233 | *handle_p = handle; |
673a394b EA |
234 | return 0; |
235 | } | |
236 | ||
ff72145b DA |
237 | int |
238 | i915_gem_dumb_create(struct drm_file *file, | |
239 | struct drm_device *dev, | |
240 | struct drm_mode_create_dumb *args) | |
241 | { | |
242 | /* have to work out size/pitch and return them */ | |
ed0291fd | 243 | args->pitch = ALIGN(args->width * ((args->bpp + 7) / 8), 64); |
ff72145b DA |
244 | args->size = args->pitch * args->height; |
245 | return i915_gem_create(file, dev, | |
246 | args->size, &args->handle); | |
247 | } | |
248 | ||
249 | int i915_gem_dumb_destroy(struct drm_file *file, | |
250 | struct drm_device *dev, | |
251 | uint32_t handle) | |
252 | { | |
253 | return drm_gem_handle_delete(file, handle); | |
254 | } | |
255 | ||
256 | /** | |
257 | * Creates a new mm object and returns a handle to it. | |
258 | */ | |
259 | int | |
260 | i915_gem_create_ioctl(struct drm_device *dev, void *data, | |
261 | struct drm_file *file) | |
262 | { | |
263 | struct drm_i915_gem_create *args = data; | |
63ed2cb2 | 264 | |
ff72145b DA |
265 | return i915_gem_create(file, dev, |
266 | args->size, &args->handle); | |
267 | } | |
268 | ||
8461d226 DV |
269 | static inline int |
270 | __copy_to_user_swizzled(char __user *cpu_vaddr, | |
271 | const char *gpu_vaddr, int gpu_offset, | |
272 | int length) | |
273 | { | |
274 | int ret, cpu_offset = 0; | |
275 | ||
276 | while (length > 0) { | |
277 | int cacheline_end = ALIGN(gpu_offset + 1, 64); | |
278 | int this_length = min(cacheline_end - gpu_offset, length); | |
279 | int swizzled_gpu_offset = gpu_offset ^ 64; | |
280 | ||
281 | ret = __copy_to_user(cpu_vaddr + cpu_offset, | |
282 | gpu_vaddr + swizzled_gpu_offset, | |
283 | this_length); | |
284 | if (ret) | |
285 | return ret + length; | |
286 | ||
287 | cpu_offset += this_length; | |
288 | gpu_offset += this_length; | |
289 | length -= this_length; | |
290 | } | |
291 | ||
292 | return 0; | |
293 | } | |
294 | ||
8c59967c | 295 | static inline int |
4f0c7cfb BW |
296 | __copy_from_user_swizzled(char *gpu_vaddr, int gpu_offset, |
297 | const char __user *cpu_vaddr, | |
8c59967c DV |
298 | int length) |
299 | { | |
300 | int ret, cpu_offset = 0; | |
301 | ||
302 | while (length > 0) { | |
303 | int cacheline_end = ALIGN(gpu_offset + 1, 64); | |
304 | int this_length = min(cacheline_end - gpu_offset, length); | |
305 | int swizzled_gpu_offset = gpu_offset ^ 64; | |
306 | ||
307 | ret = __copy_from_user(gpu_vaddr + swizzled_gpu_offset, | |
308 | cpu_vaddr + cpu_offset, | |
309 | this_length); | |
310 | if (ret) | |
311 | return ret + length; | |
312 | ||
313 | cpu_offset += this_length; | |
314 | gpu_offset += this_length; | |
315 | length -= this_length; | |
316 | } | |
317 | ||
318 | return 0; | |
319 | } | |
320 | ||
d174bd64 DV |
321 | /* Per-page copy function for the shmem pread fastpath. |
322 | * Flushes invalid cachelines before reading the target if | |
323 | * needs_clflush is set. */ | |
eb01459f | 324 | static int |
d174bd64 DV |
325 | shmem_pread_fast(struct page *page, int shmem_page_offset, int page_length, |
326 | char __user *user_data, | |
327 | bool page_do_bit17_swizzling, bool needs_clflush) | |
328 | { | |
329 | char *vaddr; | |
330 | int ret; | |
331 | ||
e7e58eb5 | 332 | if (unlikely(page_do_bit17_swizzling)) |
d174bd64 DV |
333 | return -EINVAL; |
334 | ||
335 | vaddr = kmap_atomic(page); | |
336 | if (needs_clflush) | |
337 | drm_clflush_virt_range(vaddr + shmem_page_offset, | |
338 | page_length); | |
339 | ret = __copy_to_user_inatomic(user_data, | |
340 | vaddr + shmem_page_offset, | |
341 | page_length); | |
342 | kunmap_atomic(vaddr); | |
343 | ||
f60d7f0c | 344 | return ret ? -EFAULT : 0; |
d174bd64 DV |
345 | } |
346 | ||
23c18c71 DV |
347 | static void |
348 | shmem_clflush_swizzled_range(char *addr, unsigned long length, | |
349 | bool swizzled) | |
350 | { | |
e7e58eb5 | 351 | if (unlikely(swizzled)) { |
23c18c71 DV |
352 | unsigned long start = (unsigned long) addr; |
353 | unsigned long end = (unsigned long) addr + length; | |
354 | ||
355 | /* For swizzling simply ensure that we always flush both | |
356 | * channels. Lame, but simple and it works. Swizzled | |
357 | * pwrite/pread is far from a hotpath - current userspace | |
358 | * doesn't use it at all. */ | |
359 | start = round_down(start, 128); | |
360 | end = round_up(end, 128); | |
361 | ||
362 | drm_clflush_virt_range((void *)start, end - start); | |
363 | } else { | |
364 | drm_clflush_virt_range(addr, length); | |
365 | } | |
366 | ||
367 | } | |
368 | ||
d174bd64 DV |
369 | /* Only difference to the fast-path function is that this can handle bit17 |
370 | * and uses non-atomic copy and kmap functions. */ | |
371 | static int | |
372 | shmem_pread_slow(struct page *page, int shmem_page_offset, int page_length, | |
373 | char __user *user_data, | |
374 | bool page_do_bit17_swizzling, bool needs_clflush) | |
375 | { | |
376 | char *vaddr; | |
377 | int ret; | |
378 | ||
379 | vaddr = kmap(page); | |
380 | if (needs_clflush) | |
23c18c71 DV |
381 | shmem_clflush_swizzled_range(vaddr + shmem_page_offset, |
382 | page_length, | |
383 | page_do_bit17_swizzling); | |
d174bd64 DV |
384 | |
385 | if (page_do_bit17_swizzling) | |
386 | ret = __copy_to_user_swizzled(user_data, | |
387 | vaddr, shmem_page_offset, | |
388 | page_length); | |
389 | else | |
390 | ret = __copy_to_user(user_data, | |
391 | vaddr + shmem_page_offset, | |
392 | page_length); | |
393 | kunmap(page); | |
394 | ||
f60d7f0c | 395 | return ret ? - EFAULT : 0; |
d174bd64 DV |
396 | } |
397 | ||
eb01459f | 398 | static int |
dbf7bff0 DV |
399 | i915_gem_shmem_pread(struct drm_device *dev, |
400 | struct drm_i915_gem_object *obj, | |
401 | struct drm_i915_gem_pread *args, | |
402 | struct drm_file *file) | |
eb01459f | 403 | { |
8461d226 | 404 | char __user *user_data; |
eb01459f | 405 | ssize_t remain; |
8461d226 | 406 | loff_t offset; |
eb2c0c81 | 407 | int shmem_page_offset, page_length, ret = 0; |
8461d226 | 408 | int obj_do_bit17_swizzling, page_do_bit17_swizzling; |
96d79b52 | 409 | int prefaulted = 0; |
8489731c | 410 | int needs_clflush = 0; |
67d5a50c | 411 | struct sg_page_iter sg_iter; |
eb01459f | 412 | |
2bb4629a | 413 | user_data = to_user_ptr(args->data_ptr); |
eb01459f EA |
414 | remain = args->size; |
415 | ||
8461d226 | 416 | obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj); |
eb01459f | 417 | |
8489731c DV |
418 | if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU)) { |
419 | /* If we're not in the cpu read domain, set ourself into the gtt | |
420 | * read domain and manually flush cachelines (if required). This | |
421 | * optimizes for the case when the gpu will dirty the data | |
422 | * anyway again before the next pread happens. */ | |
423 | if (obj->cache_level == I915_CACHE_NONE) | |
424 | needs_clflush = 1; | |
6c085a72 CW |
425 | if (obj->gtt_space) { |
426 | ret = i915_gem_object_set_to_gtt_domain(obj, false); | |
427 | if (ret) | |
428 | return ret; | |
429 | } | |
8489731c | 430 | } |
eb01459f | 431 | |
f60d7f0c CW |
432 | ret = i915_gem_object_get_pages(obj); |
433 | if (ret) | |
434 | return ret; | |
435 | ||
436 | i915_gem_object_pin_pages(obj); | |
437 | ||
8461d226 | 438 | offset = args->offset; |
eb01459f | 439 | |
67d5a50c ID |
440 | for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, |
441 | offset >> PAGE_SHIFT) { | |
2db76d7c | 442 | struct page *page = sg_page_iter_page(&sg_iter); |
9da3da66 CW |
443 | |
444 | if (remain <= 0) | |
445 | break; | |
446 | ||
eb01459f EA |
447 | /* Operation in this page |
448 | * | |
eb01459f | 449 | * shmem_page_offset = offset within page in shmem file |
eb01459f EA |
450 | * page_length = bytes to copy for this page |
451 | */ | |
c8cbbb8b | 452 | shmem_page_offset = offset_in_page(offset); |
eb01459f EA |
453 | page_length = remain; |
454 | if ((shmem_page_offset + page_length) > PAGE_SIZE) | |
455 | page_length = PAGE_SIZE - shmem_page_offset; | |
eb01459f | 456 | |
8461d226 DV |
457 | page_do_bit17_swizzling = obj_do_bit17_swizzling && |
458 | (page_to_phys(page) & (1 << 17)) != 0; | |
459 | ||
d174bd64 DV |
460 | ret = shmem_pread_fast(page, shmem_page_offset, page_length, |
461 | user_data, page_do_bit17_swizzling, | |
462 | needs_clflush); | |
463 | if (ret == 0) | |
464 | goto next_page; | |
dbf7bff0 | 465 | |
dbf7bff0 DV |
466 | mutex_unlock(&dev->struct_mutex); |
467 | ||
96d79b52 | 468 | if (!prefaulted) { |
f56f821f | 469 | ret = fault_in_multipages_writeable(user_data, remain); |
96d79b52 DV |
470 | /* Userspace is tricking us, but we've already clobbered |
471 | * its pages with the prefault and promised to write the | |
472 | * data up to the first fault. Hence ignore any errors | |
473 | * and just continue. */ | |
474 | (void)ret; | |
475 | prefaulted = 1; | |
476 | } | |
eb01459f | 477 | |
d174bd64 DV |
478 | ret = shmem_pread_slow(page, shmem_page_offset, page_length, |
479 | user_data, page_do_bit17_swizzling, | |
480 | needs_clflush); | |
eb01459f | 481 | |
dbf7bff0 | 482 | mutex_lock(&dev->struct_mutex); |
f60d7f0c | 483 | |
dbf7bff0 | 484 | next_page: |
e5281ccd | 485 | mark_page_accessed(page); |
e5281ccd | 486 | |
f60d7f0c | 487 | if (ret) |
8461d226 | 488 | goto out; |
8461d226 | 489 | |
eb01459f | 490 | remain -= page_length; |
8461d226 | 491 | user_data += page_length; |
eb01459f EA |
492 | offset += page_length; |
493 | } | |
494 | ||
4f27b75d | 495 | out: |
f60d7f0c CW |
496 | i915_gem_object_unpin_pages(obj); |
497 | ||
eb01459f EA |
498 | return ret; |
499 | } | |
500 | ||
673a394b EA |
501 | /** |
502 | * Reads data from the object referenced by handle. | |
503 | * | |
504 | * On error, the contents of *data are undefined. | |
505 | */ | |
506 | int | |
507 | i915_gem_pread_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 508 | struct drm_file *file) |
673a394b EA |
509 | { |
510 | struct drm_i915_gem_pread *args = data; | |
05394f39 | 511 | struct drm_i915_gem_object *obj; |
35b62a89 | 512 | int ret = 0; |
673a394b | 513 | |
51311d0a CW |
514 | if (args->size == 0) |
515 | return 0; | |
516 | ||
517 | if (!access_ok(VERIFY_WRITE, | |
2bb4629a | 518 | to_user_ptr(args->data_ptr), |
51311d0a CW |
519 | args->size)) |
520 | return -EFAULT; | |
521 | ||
4f27b75d | 522 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 523 | if (ret) |
4f27b75d | 524 | return ret; |
673a394b | 525 | |
05394f39 | 526 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 527 | if (&obj->base == NULL) { |
1d7cfea1 CW |
528 | ret = -ENOENT; |
529 | goto unlock; | |
4f27b75d | 530 | } |
673a394b | 531 | |
7dcd2499 | 532 | /* Bounds check source. */ |
05394f39 CW |
533 | if (args->offset > obj->base.size || |
534 | args->size > obj->base.size - args->offset) { | |
ce9d419d | 535 | ret = -EINVAL; |
35b62a89 | 536 | goto out; |
ce9d419d CW |
537 | } |
538 | ||
1286ff73 DV |
539 | /* prime objects have no backing filp to GEM pread/pwrite |
540 | * pages from. | |
541 | */ | |
542 | if (!obj->base.filp) { | |
543 | ret = -EINVAL; | |
544 | goto out; | |
545 | } | |
546 | ||
db53a302 CW |
547 | trace_i915_gem_object_pread(obj, args->offset, args->size); |
548 | ||
dbf7bff0 | 549 | ret = i915_gem_shmem_pread(dev, obj, args, file); |
673a394b | 550 | |
35b62a89 | 551 | out: |
05394f39 | 552 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 553 | unlock: |
4f27b75d | 554 | mutex_unlock(&dev->struct_mutex); |
eb01459f | 555 | return ret; |
673a394b EA |
556 | } |
557 | ||
0839ccb8 KP |
558 | /* This is the fast write path which cannot handle |
559 | * page faults in the source data | |
9b7530cc | 560 | */ |
0839ccb8 KP |
561 | |
562 | static inline int | |
563 | fast_user_write(struct io_mapping *mapping, | |
564 | loff_t page_base, int page_offset, | |
565 | char __user *user_data, | |
566 | int length) | |
9b7530cc | 567 | { |
4f0c7cfb BW |
568 | void __iomem *vaddr_atomic; |
569 | void *vaddr; | |
0839ccb8 | 570 | unsigned long unwritten; |
9b7530cc | 571 | |
3e4d3af5 | 572 | vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base); |
4f0c7cfb BW |
573 | /* We can use the cpu mem copy function because this is X86. */ |
574 | vaddr = (void __force*)vaddr_atomic + page_offset; | |
575 | unwritten = __copy_from_user_inatomic_nocache(vaddr, | |
0839ccb8 | 576 | user_data, length); |
3e4d3af5 | 577 | io_mapping_unmap_atomic(vaddr_atomic); |
fbd5a26d | 578 | return unwritten; |
0839ccb8 KP |
579 | } |
580 | ||
3de09aa3 EA |
581 | /** |
582 | * This is the fast pwrite path, where we copy the data directly from the | |
583 | * user into the GTT, uncached. | |
584 | */ | |
673a394b | 585 | static int |
05394f39 CW |
586 | i915_gem_gtt_pwrite_fast(struct drm_device *dev, |
587 | struct drm_i915_gem_object *obj, | |
3de09aa3 | 588 | struct drm_i915_gem_pwrite *args, |
05394f39 | 589 | struct drm_file *file) |
673a394b | 590 | { |
0839ccb8 | 591 | drm_i915_private_t *dev_priv = dev->dev_private; |
673a394b | 592 | ssize_t remain; |
0839ccb8 | 593 | loff_t offset, page_base; |
673a394b | 594 | char __user *user_data; |
935aaa69 DV |
595 | int page_offset, page_length, ret; |
596 | ||
86a1ee26 | 597 | ret = i915_gem_object_pin(obj, 0, true, true); |
935aaa69 DV |
598 | if (ret) |
599 | goto out; | |
600 | ||
601 | ret = i915_gem_object_set_to_gtt_domain(obj, true); | |
602 | if (ret) | |
603 | goto out_unpin; | |
604 | ||
605 | ret = i915_gem_object_put_fence(obj); | |
606 | if (ret) | |
607 | goto out_unpin; | |
673a394b | 608 | |
2bb4629a | 609 | user_data = to_user_ptr(args->data_ptr); |
673a394b | 610 | remain = args->size; |
673a394b | 611 | |
05394f39 | 612 | offset = obj->gtt_offset + args->offset; |
673a394b EA |
613 | |
614 | while (remain > 0) { | |
615 | /* Operation in this page | |
616 | * | |
0839ccb8 KP |
617 | * page_base = page offset within aperture |
618 | * page_offset = offset within page | |
619 | * page_length = bytes to copy for this page | |
673a394b | 620 | */ |
c8cbbb8b CW |
621 | page_base = offset & PAGE_MASK; |
622 | page_offset = offset_in_page(offset); | |
0839ccb8 KP |
623 | page_length = remain; |
624 | if ((page_offset + remain) > PAGE_SIZE) | |
625 | page_length = PAGE_SIZE - page_offset; | |
626 | ||
0839ccb8 | 627 | /* If we get a fault while copying data, then (presumably) our |
3de09aa3 EA |
628 | * source page isn't available. Return the error and we'll |
629 | * retry in the slow path. | |
0839ccb8 | 630 | */ |
5d4545ae | 631 | if (fast_user_write(dev_priv->gtt.mappable, page_base, |
935aaa69 DV |
632 | page_offset, user_data, page_length)) { |
633 | ret = -EFAULT; | |
634 | goto out_unpin; | |
635 | } | |
673a394b | 636 | |
0839ccb8 KP |
637 | remain -= page_length; |
638 | user_data += page_length; | |
639 | offset += page_length; | |
673a394b | 640 | } |
673a394b | 641 | |
935aaa69 DV |
642 | out_unpin: |
643 | i915_gem_object_unpin(obj); | |
644 | out: | |
3de09aa3 | 645 | return ret; |
673a394b EA |
646 | } |
647 | ||
d174bd64 DV |
648 | /* Per-page copy function for the shmem pwrite fastpath. |
649 | * Flushes invalid cachelines before writing to the target if | |
650 | * needs_clflush_before is set and flushes out any written cachelines after | |
651 | * writing if needs_clflush is set. */ | |
3043c60c | 652 | static int |
d174bd64 DV |
653 | shmem_pwrite_fast(struct page *page, int shmem_page_offset, int page_length, |
654 | char __user *user_data, | |
655 | bool page_do_bit17_swizzling, | |
656 | bool needs_clflush_before, | |
657 | bool needs_clflush_after) | |
673a394b | 658 | { |
d174bd64 | 659 | char *vaddr; |
673a394b | 660 | int ret; |
3de09aa3 | 661 | |
e7e58eb5 | 662 | if (unlikely(page_do_bit17_swizzling)) |
d174bd64 | 663 | return -EINVAL; |
3de09aa3 | 664 | |
d174bd64 DV |
665 | vaddr = kmap_atomic(page); |
666 | if (needs_clflush_before) | |
667 | drm_clflush_virt_range(vaddr + shmem_page_offset, | |
668 | page_length); | |
669 | ret = __copy_from_user_inatomic_nocache(vaddr + shmem_page_offset, | |
670 | user_data, | |
671 | page_length); | |
672 | if (needs_clflush_after) | |
673 | drm_clflush_virt_range(vaddr + shmem_page_offset, | |
674 | page_length); | |
675 | kunmap_atomic(vaddr); | |
3de09aa3 | 676 | |
755d2218 | 677 | return ret ? -EFAULT : 0; |
3de09aa3 EA |
678 | } |
679 | ||
d174bd64 DV |
680 | /* Only difference to the fast-path function is that this can handle bit17 |
681 | * and uses non-atomic copy and kmap functions. */ | |
3043c60c | 682 | static int |
d174bd64 DV |
683 | shmem_pwrite_slow(struct page *page, int shmem_page_offset, int page_length, |
684 | char __user *user_data, | |
685 | bool page_do_bit17_swizzling, | |
686 | bool needs_clflush_before, | |
687 | bool needs_clflush_after) | |
673a394b | 688 | { |
d174bd64 DV |
689 | char *vaddr; |
690 | int ret; | |
e5281ccd | 691 | |
d174bd64 | 692 | vaddr = kmap(page); |
e7e58eb5 | 693 | if (unlikely(needs_clflush_before || page_do_bit17_swizzling)) |
23c18c71 DV |
694 | shmem_clflush_swizzled_range(vaddr + shmem_page_offset, |
695 | page_length, | |
696 | page_do_bit17_swizzling); | |
d174bd64 DV |
697 | if (page_do_bit17_swizzling) |
698 | ret = __copy_from_user_swizzled(vaddr, shmem_page_offset, | |
e5281ccd CW |
699 | user_data, |
700 | page_length); | |
d174bd64 DV |
701 | else |
702 | ret = __copy_from_user(vaddr + shmem_page_offset, | |
703 | user_data, | |
704 | page_length); | |
705 | if (needs_clflush_after) | |
23c18c71 DV |
706 | shmem_clflush_swizzled_range(vaddr + shmem_page_offset, |
707 | page_length, | |
708 | page_do_bit17_swizzling); | |
d174bd64 | 709 | kunmap(page); |
40123c1f | 710 | |
755d2218 | 711 | return ret ? -EFAULT : 0; |
40123c1f EA |
712 | } |
713 | ||
40123c1f | 714 | static int |
e244a443 DV |
715 | i915_gem_shmem_pwrite(struct drm_device *dev, |
716 | struct drm_i915_gem_object *obj, | |
717 | struct drm_i915_gem_pwrite *args, | |
718 | struct drm_file *file) | |
40123c1f | 719 | { |
40123c1f | 720 | ssize_t remain; |
8c59967c DV |
721 | loff_t offset; |
722 | char __user *user_data; | |
eb2c0c81 | 723 | int shmem_page_offset, page_length, ret = 0; |
8c59967c | 724 | int obj_do_bit17_swizzling, page_do_bit17_swizzling; |
e244a443 | 725 | int hit_slowpath = 0; |
58642885 DV |
726 | int needs_clflush_after = 0; |
727 | int needs_clflush_before = 0; | |
67d5a50c | 728 | struct sg_page_iter sg_iter; |
40123c1f | 729 | |
2bb4629a | 730 | user_data = to_user_ptr(args->data_ptr); |
40123c1f EA |
731 | remain = args->size; |
732 | ||
8c59967c | 733 | obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj); |
40123c1f | 734 | |
58642885 DV |
735 | if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) { |
736 | /* If we're not in the cpu write domain, set ourself into the gtt | |
737 | * write domain and manually flush cachelines (if required). This | |
738 | * optimizes for the case when the gpu will use the data | |
739 | * right away and we therefore have to clflush anyway. */ | |
740 | if (obj->cache_level == I915_CACHE_NONE) | |
741 | needs_clflush_after = 1; | |
6c085a72 CW |
742 | if (obj->gtt_space) { |
743 | ret = i915_gem_object_set_to_gtt_domain(obj, true); | |
744 | if (ret) | |
745 | return ret; | |
746 | } | |
58642885 DV |
747 | } |
748 | /* Same trick applies for invalidate partially written cachelines before | |
749 | * writing. */ | |
750 | if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU) | |
751 | && obj->cache_level == I915_CACHE_NONE) | |
752 | needs_clflush_before = 1; | |
753 | ||
755d2218 CW |
754 | ret = i915_gem_object_get_pages(obj); |
755 | if (ret) | |
756 | return ret; | |
757 | ||
758 | i915_gem_object_pin_pages(obj); | |
759 | ||
673a394b | 760 | offset = args->offset; |
05394f39 | 761 | obj->dirty = 1; |
673a394b | 762 | |
67d5a50c ID |
763 | for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, |
764 | offset >> PAGE_SHIFT) { | |
2db76d7c | 765 | struct page *page = sg_page_iter_page(&sg_iter); |
58642885 | 766 | int partial_cacheline_write; |
e5281ccd | 767 | |
9da3da66 CW |
768 | if (remain <= 0) |
769 | break; | |
770 | ||
40123c1f EA |
771 | /* Operation in this page |
772 | * | |
40123c1f | 773 | * shmem_page_offset = offset within page in shmem file |
40123c1f EA |
774 | * page_length = bytes to copy for this page |
775 | */ | |
c8cbbb8b | 776 | shmem_page_offset = offset_in_page(offset); |
40123c1f EA |
777 | |
778 | page_length = remain; | |
779 | if ((shmem_page_offset + page_length) > PAGE_SIZE) | |
780 | page_length = PAGE_SIZE - shmem_page_offset; | |
40123c1f | 781 | |
58642885 DV |
782 | /* If we don't overwrite a cacheline completely we need to be |
783 | * careful to have up-to-date data by first clflushing. Don't | |
784 | * overcomplicate things and flush the entire patch. */ | |
785 | partial_cacheline_write = needs_clflush_before && | |
786 | ((shmem_page_offset | page_length) | |
787 | & (boot_cpu_data.x86_clflush_size - 1)); | |
788 | ||
8c59967c DV |
789 | page_do_bit17_swizzling = obj_do_bit17_swizzling && |
790 | (page_to_phys(page) & (1 << 17)) != 0; | |
791 | ||
d174bd64 DV |
792 | ret = shmem_pwrite_fast(page, shmem_page_offset, page_length, |
793 | user_data, page_do_bit17_swizzling, | |
794 | partial_cacheline_write, | |
795 | needs_clflush_after); | |
796 | if (ret == 0) | |
797 | goto next_page; | |
e244a443 DV |
798 | |
799 | hit_slowpath = 1; | |
e244a443 | 800 | mutex_unlock(&dev->struct_mutex); |
d174bd64 DV |
801 | ret = shmem_pwrite_slow(page, shmem_page_offset, page_length, |
802 | user_data, page_do_bit17_swizzling, | |
803 | partial_cacheline_write, | |
804 | needs_clflush_after); | |
40123c1f | 805 | |
e244a443 | 806 | mutex_lock(&dev->struct_mutex); |
755d2218 | 807 | |
e244a443 | 808 | next_page: |
e5281ccd CW |
809 | set_page_dirty(page); |
810 | mark_page_accessed(page); | |
e5281ccd | 811 | |
755d2218 | 812 | if (ret) |
8c59967c | 813 | goto out; |
8c59967c | 814 | |
40123c1f | 815 | remain -= page_length; |
8c59967c | 816 | user_data += page_length; |
40123c1f | 817 | offset += page_length; |
673a394b EA |
818 | } |
819 | ||
fbd5a26d | 820 | out: |
755d2218 CW |
821 | i915_gem_object_unpin_pages(obj); |
822 | ||
e244a443 | 823 | if (hit_slowpath) { |
8dcf015e DV |
824 | /* |
825 | * Fixup: Flush cpu caches in case we didn't flush the dirty | |
826 | * cachelines in-line while writing and the object moved | |
827 | * out of the cpu write domain while we've dropped the lock. | |
828 | */ | |
829 | if (!needs_clflush_after && | |
830 | obj->base.write_domain != I915_GEM_DOMAIN_CPU) { | |
e244a443 | 831 | i915_gem_clflush_object(obj); |
e76e9aeb | 832 | i915_gem_chipset_flush(dev); |
e244a443 | 833 | } |
8c59967c | 834 | } |
673a394b | 835 | |
58642885 | 836 | if (needs_clflush_after) |
e76e9aeb | 837 | i915_gem_chipset_flush(dev); |
58642885 | 838 | |
40123c1f | 839 | return ret; |
673a394b EA |
840 | } |
841 | ||
842 | /** | |
843 | * Writes data to the object referenced by handle. | |
844 | * | |
845 | * On error, the contents of the buffer that were to be modified are undefined. | |
846 | */ | |
847 | int | |
848 | i915_gem_pwrite_ioctl(struct drm_device *dev, void *data, | |
fbd5a26d | 849 | struct drm_file *file) |
673a394b EA |
850 | { |
851 | struct drm_i915_gem_pwrite *args = data; | |
05394f39 | 852 | struct drm_i915_gem_object *obj; |
51311d0a CW |
853 | int ret; |
854 | ||
855 | if (args->size == 0) | |
856 | return 0; | |
857 | ||
858 | if (!access_ok(VERIFY_READ, | |
2bb4629a | 859 | to_user_ptr(args->data_ptr), |
51311d0a CW |
860 | args->size)) |
861 | return -EFAULT; | |
862 | ||
2bb4629a | 863 | ret = fault_in_multipages_readable(to_user_ptr(args->data_ptr), |
f56f821f | 864 | args->size); |
51311d0a CW |
865 | if (ret) |
866 | return -EFAULT; | |
673a394b | 867 | |
fbd5a26d | 868 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 869 | if (ret) |
fbd5a26d | 870 | return ret; |
1d7cfea1 | 871 | |
05394f39 | 872 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 873 | if (&obj->base == NULL) { |
1d7cfea1 CW |
874 | ret = -ENOENT; |
875 | goto unlock; | |
fbd5a26d | 876 | } |
673a394b | 877 | |
7dcd2499 | 878 | /* Bounds check destination. */ |
05394f39 CW |
879 | if (args->offset > obj->base.size || |
880 | args->size > obj->base.size - args->offset) { | |
ce9d419d | 881 | ret = -EINVAL; |
35b62a89 | 882 | goto out; |
ce9d419d CW |
883 | } |
884 | ||
1286ff73 DV |
885 | /* prime objects have no backing filp to GEM pread/pwrite |
886 | * pages from. | |
887 | */ | |
888 | if (!obj->base.filp) { | |
889 | ret = -EINVAL; | |
890 | goto out; | |
891 | } | |
892 | ||
db53a302 CW |
893 | trace_i915_gem_object_pwrite(obj, args->offset, args->size); |
894 | ||
935aaa69 | 895 | ret = -EFAULT; |
673a394b EA |
896 | /* We can only do the GTT pwrite on untiled buffers, as otherwise |
897 | * it would end up going through the fenced access, and we'll get | |
898 | * different detiling behavior between reading and writing. | |
899 | * pread/pwrite currently are reading and writing from the CPU | |
900 | * perspective, requiring manual detiling by the client. | |
901 | */ | |
5c0480f2 | 902 | if (obj->phys_obj) { |
fbd5a26d | 903 | ret = i915_gem_phys_pwrite(dev, obj, args, file); |
5c0480f2 DV |
904 | goto out; |
905 | } | |
906 | ||
86a1ee26 | 907 | if (obj->cache_level == I915_CACHE_NONE && |
c07496fa | 908 | obj->tiling_mode == I915_TILING_NONE && |
5c0480f2 | 909 | obj->base.write_domain != I915_GEM_DOMAIN_CPU) { |
fbd5a26d | 910 | ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file); |
935aaa69 DV |
911 | /* Note that the gtt paths might fail with non-page-backed user |
912 | * pointers (e.g. gtt mappings when moving data between | |
913 | * textures). Fallback to the shmem path in that case. */ | |
fbd5a26d | 914 | } |
673a394b | 915 | |
86a1ee26 | 916 | if (ret == -EFAULT || ret == -ENOSPC) |
935aaa69 | 917 | ret = i915_gem_shmem_pwrite(dev, obj, args, file); |
5c0480f2 | 918 | |
35b62a89 | 919 | out: |
05394f39 | 920 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 921 | unlock: |
fbd5a26d | 922 | mutex_unlock(&dev->struct_mutex); |
673a394b EA |
923 | return ret; |
924 | } | |
925 | ||
b361237b | 926 | int |
33196ded | 927 | i915_gem_check_wedge(struct i915_gpu_error *error, |
b361237b CW |
928 | bool interruptible) |
929 | { | |
1f83fee0 | 930 | if (i915_reset_in_progress(error)) { |
b361237b CW |
931 | /* Non-interruptible callers can't handle -EAGAIN, hence return |
932 | * -EIO unconditionally for these. */ | |
933 | if (!interruptible) | |
934 | return -EIO; | |
935 | ||
1f83fee0 DV |
936 | /* Recovery complete, but the reset failed ... */ |
937 | if (i915_terminally_wedged(error)) | |
b361237b CW |
938 | return -EIO; |
939 | ||
940 | return -EAGAIN; | |
941 | } | |
942 | ||
943 | return 0; | |
944 | } | |
945 | ||
946 | /* | |
947 | * Compare seqno against outstanding lazy request. Emit a request if they are | |
948 | * equal. | |
949 | */ | |
950 | static int | |
951 | i915_gem_check_olr(struct intel_ring_buffer *ring, u32 seqno) | |
952 | { | |
953 | int ret; | |
954 | ||
955 | BUG_ON(!mutex_is_locked(&ring->dev->struct_mutex)); | |
956 | ||
957 | ret = 0; | |
958 | if (seqno == ring->outstanding_lazy_request) | |
959 | ret = i915_add_request(ring, NULL, NULL); | |
960 | ||
961 | return ret; | |
962 | } | |
963 | ||
964 | /** | |
965 | * __wait_seqno - wait until execution of seqno has finished | |
966 | * @ring: the ring expected to report seqno | |
967 | * @seqno: duh! | |
f69061be | 968 | * @reset_counter: reset sequence associated with the given seqno |
b361237b CW |
969 | * @interruptible: do an interruptible wait (normally yes) |
970 | * @timeout: in - how long to wait (NULL forever); out - how much time remaining | |
971 | * | |
f69061be DV |
972 | * Note: It is of utmost importance that the passed in seqno and reset_counter |
973 | * values have been read by the caller in an smp safe manner. Where read-side | |
974 | * locks are involved, it is sufficient to read the reset_counter before | |
975 | * unlocking the lock that protects the seqno. For lockless tricks, the | |
976 | * reset_counter _must_ be read before, and an appropriate smp_rmb must be | |
977 | * inserted. | |
978 | * | |
b361237b CW |
979 | * Returns 0 if the seqno was found within the alloted time. Else returns the |
980 | * errno with remaining time filled in timeout argument. | |
981 | */ | |
982 | static int __wait_seqno(struct intel_ring_buffer *ring, u32 seqno, | |
f69061be | 983 | unsigned reset_counter, |
b361237b CW |
984 | bool interruptible, struct timespec *timeout) |
985 | { | |
986 | drm_i915_private_t *dev_priv = ring->dev->dev_private; | |
987 | struct timespec before, now, wait_time={1,0}; | |
988 | unsigned long timeout_jiffies; | |
989 | long end; | |
990 | bool wait_forever = true; | |
991 | int ret; | |
992 | ||
993 | if (i915_seqno_passed(ring->get_seqno(ring, true), seqno)) | |
994 | return 0; | |
995 | ||
996 | trace_i915_gem_request_wait_begin(ring, seqno); | |
997 | ||
998 | if (timeout != NULL) { | |
999 | wait_time = *timeout; | |
1000 | wait_forever = false; | |
1001 | } | |
1002 | ||
e054cc39 | 1003 | timeout_jiffies = timespec_to_jiffies_timeout(&wait_time); |
b361237b CW |
1004 | |
1005 | if (WARN_ON(!ring->irq_get(ring))) | |
1006 | return -ENODEV; | |
1007 | ||
1008 | /* Record current time in case interrupted by signal, or wedged * */ | |
1009 | getrawmonotonic(&before); | |
1010 | ||
1011 | #define EXIT_COND \ | |
1012 | (i915_seqno_passed(ring->get_seqno(ring, false), seqno) || \ | |
f69061be DV |
1013 | i915_reset_in_progress(&dev_priv->gpu_error) || \ |
1014 | reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter)) | |
b361237b CW |
1015 | do { |
1016 | if (interruptible) | |
1017 | end = wait_event_interruptible_timeout(ring->irq_queue, | |
1018 | EXIT_COND, | |
1019 | timeout_jiffies); | |
1020 | else | |
1021 | end = wait_event_timeout(ring->irq_queue, EXIT_COND, | |
1022 | timeout_jiffies); | |
1023 | ||
f69061be DV |
1024 | /* We need to check whether any gpu reset happened in between |
1025 | * the caller grabbing the seqno and now ... */ | |
1026 | if (reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter)) | |
1027 | end = -EAGAIN; | |
1028 | ||
1029 | /* ... but upgrade the -EGAIN to an -EIO if the gpu is truely | |
1030 | * gone. */ | |
33196ded | 1031 | ret = i915_gem_check_wedge(&dev_priv->gpu_error, interruptible); |
b361237b CW |
1032 | if (ret) |
1033 | end = ret; | |
1034 | } while (end == 0 && wait_forever); | |
1035 | ||
1036 | getrawmonotonic(&now); | |
1037 | ||
1038 | ring->irq_put(ring); | |
1039 | trace_i915_gem_request_wait_end(ring, seqno); | |
1040 | #undef EXIT_COND | |
1041 | ||
1042 | if (timeout) { | |
1043 | struct timespec sleep_time = timespec_sub(now, before); | |
1044 | *timeout = timespec_sub(*timeout, sleep_time); | |
4f42f4ef CW |
1045 | if (!timespec_valid(timeout)) /* i.e. negative time remains */ |
1046 | set_normalized_timespec(timeout, 0, 0); | |
b361237b CW |
1047 | } |
1048 | ||
1049 | switch (end) { | |
1050 | case -EIO: | |
1051 | case -EAGAIN: /* Wedged */ | |
1052 | case -ERESTARTSYS: /* Signal */ | |
1053 | return (int)end; | |
1054 | case 0: /* Timeout */ | |
b361237b CW |
1055 | return -ETIME; |
1056 | default: /* Completed */ | |
1057 | WARN_ON(end < 0); /* We're not aware of other errors */ | |
1058 | return 0; | |
1059 | } | |
1060 | } | |
1061 | ||
1062 | /** | |
1063 | * Waits for a sequence number to be signaled, and cleans up the | |
1064 | * request and object lists appropriately for that event. | |
1065 | */ | |
1066 | int | |
1067 | i915_wait_seqno(struct intel_ring_buffer *ring, uint32_t seqno) | |
1068 | { | |
1069 | struct drm_device *dev = ring->dev; | |
1070 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1071 | bool interruptible = dev_priv->mm.interruptible; | |
1072 | int ret; | |
1073 | ||
1074 | BUG_ON(!mutex_is_locked(&dev->struct_mutex)); | |
1075 | BUG_ON(seqno == 0); | |
1076 | ||
33196ded | 1077 | ret = i915_gem_check_wedge(&dev_priv->gpu_error, interruptible); |
b361237b CW |
1078 | if (ret) |
1079 | return ret; | |
1080 | ||
1081 | ret = i915_gem_check_olr(ring, seqno); | |
1082 | if (ret) | |
1083 | return ret; | |
1084 | ||
f69061be DV |
1085 | return __wait_seqno(ring, seqno, |
1086 | atomic_read(&dev_priv->gpu_error.reset_counter), | |
1087 | interruptible, NULL); | |
b361237b CW |
1088 | } |
1089 | ||
1090 | /** | |
1091 | * Ensures that all rendering to the object has completed and the object is | |
1092 | * safe to unbind from the GTT or access from the CPU. | |
1093 | */ | |
1094 | static __must_check int | |
1095 | i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj, | |
1096 | bool readonly) | |
1097 | { | |
1098 | struct intel_ring_buffer *ring = obj->ring; | |
1099 | u32 seqno; | |
1100 | int ret; | |
1101 | ||
1102 | seqno = readonly ? obj->last_write_seqno : obj->last_read_seqno; | |
1103 | if (seqno == 0) | |
1104 | return 0; | |
1105 | ||
1106 | ret = i915_wait_seqno(ring, seqno); | |
1107 | if (ret) | |
1108 | return ret; | |
1109 | ||
1110 | i915_gem_retire_requests_ring(ring); | |
1111 | ||
1112 | /* Manually manage the write flush as we may have not yet | |
1113 | * retired the buffer. | |
1114 | */ | |
1115 | if (obj->last_write_seqno && | |
1116 | i915_seqno_passed(seqno, obj->last_write_seqno)) { | |
1117 | obj->last_write_seqno = 0; | |
1118 | obj->base.write_domain &= ~I915_GEM_GPU_DOMAINS; | |
1119 | } | |
1120 | ||
1121 | return 0; | |
1122 | } | |
1123 | ||
3236f57a CW |
1124 | /* A nonblocking variant of the above wait. This is a highly dangerous routine |
1125 | * as the object state may change during this call. | |
1126 | */ | |
1127 | static __must_check int | |
1128 | i915_gem_object_wait_rendering__nonblocking(struct drm_i915_gem_object *obj, | |
1129 | bool readonly) | |
1130 | { | |
1131 | struct drm_device *dev = obj->base.dev; | |
1132 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1133 | struct intel_ring_buffer *ring = obj->ring; | |
f69061be | 1134 | unsigned reset_counter; |
3236f57a CW |
1135 | u32 seqno; |
1136 | int ret; | |
1137 | ||
1138 | BUG_ON(!mutex_is_locked(&dev->struct_mutex)); | |
1139 | BUG_ON(!dev_priv->mm.interruptible); | |
1140 | ||
1141 | seqno = readonly ? obj->last_write_seqno : obj->last_read_seqno; | |
1142 | if (seqno == 0) | |
1143 | return 0; | |
1144 | ||
33196ded | 1145 | ret = i915_gem_check_wedge(&dev_priv->gpu_error, true); |
3236f57a CW |
1146 | if (ret) |
1147 | return ret; | |
1148 | ||
1149 | ret = i915_gem_check_olr(ring, seqno); | |
1150 | if (ret) | |
1151 | return ret; | |
1152 | ||
f69061be | 1153 | reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter); |
3236f57a | 1154 | mutex_unlock(&dev->struct_mutex); |
f69061be | 1155 | ret = __wait_seqno(ring, seqno, reset_counter, true, NULL); |
3236f57a CW |
1156 | mutex_lock(&dev->struct_mutex); |
1157 | ||
1158 | i915_gem_retire_requests_ring(ring); | |
1159 | ||
1160 | /* Manually manage the write flush as we may have not yet | |
1161 | * retired the buffer. | |
1162 | */ | |
1163 | if (obj->last_write_seqno && | |
1164 | i915_seqno_passed(seqno, obj->last_write_seqno)) { | |
1165 | obj->last_write_seqno = 0; | |
1166 | obj->base.write_domain &= ~I915_GEM_GPU_DOMAINS; | |
1167 | } | |
1168 | ||
1169 | return ret; | |
1170 | } | |
1171 | ||
673a394b | 1172 | /** |
2ef7eeaa EA |
1173 | * Called when user space prepares to use an object with the CPU, either |
1174 | * through the mmap ioctl's mapping or a GTT mapping. | |
673a394b EA |
1175 | */ |
1176 | int | |
1177 | i915_gem_set_domain_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 1178 | struct drm_file *file) |
673a394b EA |
1179 | { |
1180 | struct drm_i915_gem_set_domain *args = data; | |
05394f39 | 1181 | struct drm_i915_gem_object *obj; |
2ef7eeaa EA |
1182 | uint32_t read_domains = args->read_domains; |
1183 | uint32_t write_domain = args->write_domain; | |
673a394b EA |
1184 | int ret; |
1185 | ||
2ef7eeaa | 1186 | /* Only handle setting domains to types used by the CPU. */ |
21d509e3 | 1187 | if (write_domain & I915_GEM_GPU_DOMAINS) |
2ef7eeaa EA |
1188 | return -EINVAL; |
1189 | ||
21d509e3 | 1190 | if (read_domains & I915_GEM_GPU_DOMAINS) |
2ef7eeaa EA |
1191 | return -EINVAL; |
1192 | ||
1193 | /* Having something in the write domain implies it's in the read | |
1194 | * domain, and only that read domain. Enforce that in the request. | |
1195 | */ | |
1196 | if (write_domain != 0 && read_domains != write_domain) | |
1197 | return -EINVAL; | |
1198 | ||
76c1dec1 | 1199 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 1200 | if (ret) |
76c1dec1 | 1201 | return ret; |
1d7cfea1 | 1202 | |
05394f39 | 1203 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 1204 | if (&obj->base == NULL) { |
1d7cfea1 CW |
1205 | ret = -ENOENT; |
1206 | goto unlock; | |
76c1dec1 | 1207 | } |
673a394b | 1208 | |
3236f57a CW |
1209 | /* Try to flush the object off the GPU without holding the lock. |
1210 | * We will repeat the flush holding the lock in the normal manner | |
1211 | * to catch cases where we are gazumped. | |
1212 | */ | |
1213 | ret = i915_gem_object_wait_rendering__nonblocking(obj, !write_domain); | |
1214 | if (ret) | |
1215 | goto unref; | |
1216 | ||
2ef7eeaa EA |
1217 | if (read_domains & I915_GEM_DOMAIN_GTT) { |
1218 | ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0); | |
02354392 EA |
1219 | |
1220 | /* Silently promote "you're not bound, there was nothing to do" | |
1221 | * to success, since the client was just asking us to | |
1222 | * make sure everything was done. | |
1223 | */ | |
1224 | if (ret == -EINVAL) | |
1225 | ret = 0; | |
2ef7eeaa | 1226 | } else { |
e47c68e9 | 1227 | ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0); |
2ef7eeaa EA |
1228 | } |
1229 | ||
3236f57a | 1230 | unref: |
05394f39 | 1231 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 1232 | unlock: |
673a394b EA |
1233 | mutex_unlock(&dev->struct_mutex); |
1234 | return ret; | |
1235 | } | |
1236 | ||
1237 | /** | |
1238 | * Called when user space has done writes to this buffer | |
1239 | */ | |
1240 | int | |
1241 | i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 1242 | struct drm_file *file) |
673a394b EA |
1243 | { |
1244 | struct drm_i915_gem_sw_finish *args = data; | |
05394f39 | 1245 | struct drm_i915_gem_object *obj; |
673a394b EA |
1246 | int ret = 0; |
1247 | ||
76c1dec1 | 1248 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 1249 | if (ret) |
76c1dec1 | 1250 | return ret; |
1d7cfea1 | 1251 | |
05394f39 | 1252 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 1253 | if (&obj->base == NULL) { |
1d7cfea1 CW |
1254 | ret = -ENOENT; |
1255 | goto unlock; | |
673a394b EA |
1256 | } |
1257 | ||
673a394b | 1258 | /* Pinned buffers may be scanout, so flush the cache */ |
05394f39 | 1259 | if (obj->pin_count) |
e47c68e9 EA |
1260 | i915_gem_object_flush_cpu_write_domain(obj); |
1261 | ||
05394f39 | 1262 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 1263 | unlock: |
673a394b EA |
1264 | mutex_unlock(&dev->struct_mutex); |
1265 | return ret; | |
1266 | } | |
1267 | ||
1268 | /** | |
1269 | * Maps the contents of an object, returning the address it is mapped | |
1270 | * into. | |
1271 | * | |
1272 | * While the mapping holds a reference on the contents of the object, it doesn't | |
1273 | * imply a ref on the object itself. | |
1274 | */ | |
1275 | int | |
1276 | i915_gem_mmap_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 1277 | struct drm_file *file) |
673a394b EA |
1278 | { |
1279 | struct drm_i915_gem_mmap *args = data; | |
1280 | struct drm_gem_object *obj; | |
673a394b EA |
1281 | unsigned long addr; |
1282 | ||
05394f39 | 1283 | obj = drm_gem_object_lookup(dev, file, args->handle); |
673a394b | 1284 | if (obj == NULL) |
bf79cb91 | 1285 | return -ENOENT; |
673a394b | 1286 | |
1286ff73 DV |
1287 | /* prime objects have no backing filp to GEM mmap |
1288 | * pages from. | |
1289 | */ | |
1290 | if (!obj->filp) { | |
1291 | drm_gem_object_unreference_unlocked(obj); | |
1292 | return -EINVAL; | |
1293 | } | |
1294 | ||
6be5ceb0 | 1295 | addr = vm_mmap(obj->filp, 0, args->size, |
673a394b EA |
1296 | PROT_READ | PROT_WRITE, MAP_SHARED, |
1297 | args->offset); | |
bc9025bd | 1298 | drm_gem_object_unreference_unlocked(obj); |
673a394b EA |
1299 | if (IS_ERR((void *)addr)) |
1300 | return addr; | |
1301 | ||
1302 | args->addr_ptr = (uint64_t) addr; | |
1303 | ||
1304 | return 0; | |
1305 | } | |
1306 | ||
de151cf6 JB |
1307 | /** |
1308 | * i915_gem_fault - fault a page into the GTT | |
1309 | * vma: VMA in question | |
1310 | * vmf: fault info | |
1311 | * | |
1312 | * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped | |
1313 | * from userspace. The fault handler takes care of binding the object to | |
1314 | * the GTT (if needed), allocating and programming a fence register (again, | |
1315 | * only if needed based on whether the old reg is still valid or the object | |
1316 | * is tiled) and inserting a new PTE into the faulting process. | |
1317 | * | |
1318 | * Note that the faulting process may involve evicting existing objects | |
1319 | * from the GTT and/or fence registers to make room. So performance may | |
1320 | * suffer if the GTT working set is large or there are few fence registers | |
1321 | * left. | |
1322 | */ | |
1323 | int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf) | |
1324 | { | |
05394f39 CW |
1325 | struct drm_i915_gem_object *obj = to_intel_bo(vma->vm_private_data); |
1326 | struct drm_device *dev = obj->base.dev; | |
7d1c4804 | 1327 | drm_i915_private_t *dev_priv = dev->dev_private; |
de151cf6 JB |
1328 | pgoff_t page_offset; |
1329 | unsigned long pfn; | |
1330 | int ret = 0; | |
0f973f27 | 1331 | bool write = !!(vmf->flags & FAULT_FLAG_WRITE); |
de151cf6 JB |
1332 | |
1333 | /* We don't use vmf->pgoff since that has the fake offset */ | |
1334 | page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >> | |
1335 | PAGE_SHIFT; | |
1336 | ||
d9bc7e9f CW |
1337 | ret = i915_mutex_lock_interruptible(dev); |
1338 | if (ret) | |
1339 | goto out; | |
a00b10c3 | 1340 | |
db53a302 CW |
1341 | trace_i915_gem_object_fault(obj, page_offset, true, write); |
1342 | ||
eb119bd6 CW |
1343 | /* Access to snoopable pages through the GTT is incoherent. */ |
1344 | if (obj->cache_level != I915_CACHE_NONE && !HAS_LLC(dev)) { | |
1345 | ret = -EINVAL; | |
1346 | goto unlock; | |
1347 | } | |
1348 | ||
d9bc7e9f | 1349 | /* Now bind it into the GTT if needed */ |
c9839303 CW |
1350 | ret = i915_gem_object_pin(obj, 0, true, false); |
1351 | if (ret) | |
1352 | goto unlock; | |
4a684a41 | 1353 | |
c9839303 CW |
1354 | ret = i915_gem_object_set_to_gtt_domain(obj, write); |
1355 | if (ret) | |
1356 | goto unpin; | |
74898d7e | 1357 | |
06d98131 | 1358 | ret = i915_gem_object_get_fence(obj); |
d9e86c0e | 1359 | if (ret) |
c9839303 | 1360 | goto unpin; |
7d1c4804 | 1361 | |
6299f992 CW |
1362 | obj->fault_mappable = true; |
1363 | ||
5d4545ae | 1364 | pfn = ((dev_priv->gtt.mappable_base + obj->gtt_offset) >> PAGE_SHIFT) + |
de151cf6 JB |
1365 | page_offset; |
1366 | ||
1367 | /* Finally, remap it using the new GTT offset */ | |
1368 | ret = vm_insert_pfn(vma, (unsigned long)vmf->virtual_address, pfn); | |
c9839303 CW |
1369 | unpin: |
1370 | i915_gem_object_unpin(obj); | |
c715089f | 1371 | unlock: |
de151cf6 | 1372 | mutex_unlock(&dev->struct_mutex); |
d9bc7e9f | 1373 | out: |
de151cf6 | 1374 | switch (ret) { |
d9bc7e9f | 1375 | case -EIO: |
a9340cca DV |
1376 | /* If this -EIO is due to a gpu hang, give the reset code a |
1377 | * chance to clean up the mess. Otherwise return the proper | |
1378 | * SIGBUS. */ | |
1f83fee0 | 1379 | if (i915_terminally_wedged(&dev_priv->gpu_error)) |
a9340cca | 1380 | return VM_FAULT_SIGBUS; |
045e769a | 1381 | case -EAGAIN: |
d9bc7e9f CW |
1382 | /* Give the error handler a chance to run and move the |
1383 | * objects off the GPU active list. Next time we service the | |
1384 | * fault, we should be able to transition the page into the | |
1385 | * GTT without touching the GPU (and so avoid further | |
1386 | * EIO/EGAIN). If the GPU is wedged, then there is no issue | |
1387 | * with coherency, just lost writes. | |
1388 | */ | |
045e769a | 1389 | set_need_resched(); |
c715089f CW |
1390 | case 0: |
1391 | case -ERESTARTSYS: | |
bed636ab | 1392 | case -EINTR: |
e79e0fe3 DR |
1393 | case -EBUSY: |
1394 | /* | |
1395 | * EBUSY is ok: this just means that another thread | |
1396 | * already did the job. | |
1397 | */ | |
c715089f | 1398 | return VM_FAULT_NOPAGE; |
de151cf6 | 1399 | case -ENOMEM: |
de151cf6 | 1400 | return VM_FAULT_OOM; |
a7c2e1aa DV |
1401 | case -ENOSPC: |
1402 | return VM_FAULT_SIGBUS; | |
de151cf6 | 1403 | default: |
a7c2e1aa | 1404 | WARN_ONCE(ret, "unhandled error in i915_gem_fault: %i\n", ret); |
c715089f | 1405 | return VM_FAULT_SIGBUS; |
de151cf6 JB |
1406 | } |
1407 | } | |
1408 | ||
901782b2 CW |
1409 | /** |
1410 | * i915_gem_release_mmap - remove physical page mappings | |
1411 | * @obj: obj in question | |
1412 | * | |
af901ca1 | 1413 | * Preserve the reservation of the mmapping with the DRM core code, but |
901782b2 CW |
1414 | * relinquish ownership of the pages back to the system. |
1415 | * | |
1416 | * It is vital that we remove the page mapping if we have mapped a tiled | |
1417 | * object through the GTT and then lose the fence register due to | |
1418 | * resource pressure. Similarly if the object has been moved out of the | |
1419 | * aperture, than pages mapped into userspace must be revoked. Removing the | |
1420 | * mapping will then trigger a page fault on the next user access, allowing | |
1421 | * fixup by i915_gem_fault(). | |
1422 | */ | |
d05ca301 | 1423 | void |
05394f39 | 1424 | i915_gem_release_mmap(struct drm_i915_gem_object *obj) |
901782b2 | 1425 | { |
6299f992 CW |
1426 | if (!obj->fault_mappable) |
1427 | return; | |
901782b2 | 1428 | |
f6e47884 CW |
1429 | if (obj->base.dev->dev_mapping) |
1430 | unmap_mapping_range(obj->base.dev->dev_mapping, | |
1431 | (loff_t)obj->base.map_list.hash.key<<PAGE_SHIFT, | |
1432 | obj->base.size, 1); | |
fb7d516a | 1433 | |
6299f992 | 1434 | obj->fault_mappable = false; |
901782b2 CW |
1435 | } |
1436 | ||
0fa87796 | 1437 | uint32_t |
e28f8711 | 1438 | i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode) |
92b88aeb | 1439 | { |
e28f8711 | 1440 | uint32_t gtt_size; |
92b88aeb CW |
1441 | |
1442 | if (INTEL_INFO(dev)->gen >= 4 || | |
e28f8711 CW |
1443 | tiling_mode == I915_TILING_NONE) |
1444 | return size; | |
92b88aeb CW |
1445 | |
1446 | /* Previous chips need a power-of-two fence region when tiling */ | |
1447 | if (INTEL_INFO(dev)->gen == 3) | |
e28f8711 | 1448 | gtt_size = 1024*1024; |
92b88aeb | 1449 | else |
e28f8711 | 1450 | gtt_size = 512*1024; |
92b88aeb | 1451 | |
e28f8711 CW |
1452 | while (gtt_size < size) |
1453 | gtt_size <<= 1; | |
92b88aeb | 1454 | |
e28f8711 | 1455 | return gtt_size; |
92b88aeb CW |
1456 | } |
1457 | ||
de151cf6 JB |
1458 | /** |
1459 | * i915_gem_get_gtt_alignment - return required GTT alignment for an object | |
1460 | * @obj: object to check | |
1461 | * | |
1462 | * Return the required GTT alignment for an object, taking into account | |
5e783301 | 1463 | * potential fence register mapping. |
de151cf6 | 1464 | */ |
d865110c ID |
1465 | uint32_t |
1466 | i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size, | |
1467 | int tiling_mode, bool fenced) | |
de151cf6 | 1468 | { |
de151cf6 JB |
1469 | /* |
1470 | * Minimum alignment is 4k (GTT page size), but might be greater | |
1471 | * if a fence register is needed for the object. | |
1472 | */ | |
d865110c | 1473 | if (INTEL_INFO(dev)->gen >= 4 || (!fenced && IS_G33(dev)) || |
e28f8711 | 1474 | tiling_mode == I915_TILING_NONE) |
de151cf6 JB |
1475 | return 4096; |
1476 | ||
a00b10c3 CW |
1477 | /* |
1478 | * Previous chips need to be aligned to the size of the smallest | |
1479 | * fence register that can contain the object. | |
1480 | */ | |
e28f8711 | 1481 | return i915_gem_get_gtt_size(dev, size, tiling_mode); |
a00b10c3 CW |
1482 | } |
1483 | ||
d8cb5086 CW |
1484 | static int i915_gem_object_create_mmap_offset(struct drm_i915_gem_object *obj) |
1485 | { | |
1486 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; | |
1487 | int ret; | |
1488 | ||
1489 | if (obj->base.map_list.map) | |
1490 | return 0; | |
1491 | ||
da494d7c DV |
1492 | dev_priv->mm.shrinker_no_lock_stealing = true; |
1493 | ||
d8cb5086 CW |
1494 | ret = drm_gem_create_mmap_offset(&obj->base); |
1495 | if (ret != -ENOSPC) | |
da494d7c | 1496 | goto out; |
d8cb5086 CW |
1497 | |
1498 | /* Badly fragmented mmap space? The only way we can recover | |
1499 | * space is by destroying unwanted objects. We can't randomly release | |
1500 | * mmap_offsets as userspace expects them to be persistent for the | |
1501 | * lifetime of the objects. The closest we can is to release the | |
1502 | * offsets on purgeable objects by truncating it and marking it purged, | |
1503 | * which prevents userspace from ever using that object again. | |
1504 | */ | |
1505 | i915_gem_purge(dev_priv, obj->base.size >> PAGE_SHIFT); | |
1506 | ret = drm_gem_create_mmap_offset(&obj->base); | |
1507 | if (ret != -ENOSPC) | |
da494d7c | 1508 | goto out; |
d8cb5086 CW |
1509 | |
1510 | i915_gem_shrink_all(dev_priv); | |
da494d7c DV |
1511 | ret = drm_gem_create_mmap_offset(&obj->base); |
1512 | out: | |
1513 | dev_priv->mm.shrinker_no_lock_stealing = false; | |
1514 | ||
1515 | return ret; | |
d8cb5086 CW |
1516 | } |
1517 | ||
1518 | static void i915_gem_object_free_mmap_offset(struct drm_i915_gem_object *obj) | |
1519 | { | |
1520 | if (!obj->base.map_list.map) | |
1521 | return; | |
1522 | ||
1523 | drm_gem_free_mmap_offset(&obj->base); | |
1524 | } | |
1525 | ||
de151cf6 | 1526 | int |
ff72145b DA |
1527 | i915_gem_mmap_gtt(struct drm_file *file, |
1528 | struct drm_device *dev, | |
1529 | uint32_t handle, | |
1530 | uint64_t *offset) | |
de151cf6 | 1531 | { |
da761a6e | 1532 | struct drm_i915_private *dev_priv = dev->dev_private; |
05394f39 | 1533 | struct drm_i915_gem_object *obj; |
de151cf6 JB |
1534 | int ret; |
1535 | ||
76c1dec1 | 1536 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 1537 | if (ret) |
76c1dec1 | 1538 | return ret; |
de151cf6 | 1539 | |
ff72145b | 1540 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle)); |
c8725226 | 1541 | if (&obj->base == NULL) { |
1d7cfea1 CW |
1542 | ret = -ENOENT; |
1543 | goto unlock; | |
1544 | } | |
de151cf6 | 1545 | |
5d4545ae | 1546 | if (obj->base.size > dev_priv->gtt.mappable_end) { |
da761a6e | 1547 | ret = -E2BIG; |
ff56b0bc | 1548 | goto out; |
da761a6e CW |
1549 | } |
1550 | ||
05394f39 | 1551 | if (obj->madv != I915_MADV_WILLNEED) { |
ab18282d | 1552 | DRM_ERROR("Attempting to mmap a purgeable buffer\n"); |
1d7cfea1 CW |
1553 | ret = -EINVAL; |
1554 | goto out; | |
ab18282d CW |
1555 | } |
1556 | ||
d8cb5086 CW |
1557 | ret = i915_gem_object_create_mmap_offset(obj); |
1558 | if (ret) | |
1559 | goto out; | |
de151cf6 | 1560 | |
ff72145b | 1561 | *offset = (u64)obj->base.map_list.hash.key << PAGE_SHIFT; |
de151cf6 | 1562 | |
1d7cfea1 | 1563 | out: |
05394f39 | 1564 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 1565 | unlock: |
de151cf6 | 1566 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 1567 | return ret; |
de151cf6 JB |
1568 | } |
1569 | ||
ff72145b DA |
1570 | /** |
1571 | * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing | |
1572 | * @dev: DRM device | |
1573 | * @data: GTT mapping ioctl data | |
1574 | * @file: GEM object info | |
1575 | * | |
1576 | * Simply returns the fake offset to userspace so it can mmap it. | |
1577 | * The mmap call will end up in drm_gem_mmap(), which will set things | |
1578 | * up so we can get faults in the handler above. | |
1579 | * | |
1580 | * The fault handler will take care of binding the object into the GTT | |
1581 | * (since it may have been evicted to make room for something), allocating | |
1582 | * a fence register, and mapping the appropriate aperture address into | |
1583 | * userspace. | |
1584 | */ | |
1585 | int | |
1586 | i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data, | |
1587 | struct drm_file *file) | |
1588 | { | |
1589 | struct drm_i915_gem_mmap_gtt *args = data; | |
1590 | ||
ff72145b DA |
1591 | return i915_gem_mmap_gtt(file, dev, args->handle, &args->offset); |
1592 | } | |
1593 | ||
225067ee DV |
1594 | /* Immediately discard the backing storage */ |
1595 | static void | |
1596 | i915_gem_object_truncate(struct drm_i915_gem_object *obj) | |
e5281ccd | 1597 | { |
e5281ccd | 1598 | struct inode *inode; |
e5281ccd | 1599 | |
4d6294bf | 1600 | i915_gem_object_free_mmap_offset(obj); |
1286ff73 | 1601 | |
4d6294bf CW |
1602 | if (obj->base.filp == NULL) |
1603 | return; | |
e5281ccd | 1604 | |
225067ee DV |
1605 | /* Our goal here is to return as much of the memory as |
1606 | * is possible back to the system as we are called from OOM. | |
1607 | * To do this we must instruct the shmfs to drop all of its | |
1608 | * backing pages, *now*. | |
1609 | */ | |
496ad9aa | 1610 | inode = file_inode(obj->base.filp); |
225067ee | 1611 | shmem_truncate_range(inode, 0, (loff_t)-1); |
e5281ccd | 1612 | |
225067ee DV |
1613 | obj->madv = __I915_MADV_PURGED; |
1614 | } | |
e5281ccd | 1615 | |
225067ee DV |
1616 | static inline int |
1617 | i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj) | |
1618 | { | |
1619 | return obj->madv == I915_MADV_DONTNEED; | |
e5281ccd CW |
1620 | } |
1621 | ||
5cdf5881 | 1622 | static void |
05394f39 | 1623 | i915_gem_object_put_pages_gtt(struct drm_i915_gem_object *obj) |
673a394b | 1624 | { |
90797e6d ID |
1625 | struct sg_page_iter sg_iter; |
1626 | int ret; | |
1286ff73 | 1627 | |
05394f39 | 1628 | BUG_ON(obj->madv == __I915_MADV_PURGED); |
673a394b | 1629 | |
6c085a72 CW |
1630 | ret = i915_gem_object_set_to_cpu_domain(obj, true); |
1631 | if (ret) { | |
1632 | /* In the event of a disaster, abandon all caches and | |
1633 | * hope for the best. | |
1634 | */ | |
1635 | WARN_ON(ret != -EIO); | |
1636 | i915_gem_clflush_object(obj); | |
1637 | obj->base.read_domains = obj->base.write_domain = I915_GEM_DOMAIN_CPU; | |
1638 | } | |
1639 | ||
6dacfd2f | 1640 | if (i915_gem_object_needs_bit17_swizzle(obj)) |
280b713b EA |
1641 | i915_gem_object_save_bit_17_swizzle(obj); |
1642 | ||
05394f39 CW |
1643 | if (obj->madv == I915_MADV_DONTNEED) |
1644 | obj->dirty = 0; | |
3ef94daa | 1645 | |
90797e6d | 1646 | for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, 0) { |
2db76d7c | 1647 | struct page *page = sg_page_iter_page(&sg_iter); |
9da3da66 | 1648 | |
05394f39 | 1649 | if (obj->dirty) |
9da3da66 | 1650 | set_page_dirty(page); |
3ef94daa | 1651 | |
05394f39 | 1652 | if (obj->madv == I915_MADV_WILLNEED) |
9da3da66 | 1653 | mark_page_accessed(page); |
3ef94daa | 1654 | |
9da3da66 | 1655 | page_cache_release(page); |
3ef94daa | 1656 | } |
05394f39 | 1657 | obj->dirty = 0; |
673a394b | 1658 | |
9da3da66 CW |
1659 | sg_free_table(obj->pages); |
1660 | kfree(obj->pages); | |
37e680a1 | 1661 | } |
6c085a72 | 1662 | |
dd624afd | 1663 | int |
37e680a1 CW |
1664 | i915_gem_object_put_pages(struct drm_i915_gem_object *obj) |
1665 | { | |
1666 | const struct drm_i915_gem_object_ops *ops = obj->ops; | |
1667 | ||
2f745ad3 | 1668 | if (obj->pages == NULL) |
37e680a1 CW |
1669 | return 0; |
1670 | ||
1671 | BUG_ON(obj->gtt_space); | |
6c085a72 | 1672 | |
a5570178 CW |
1673 | if (obj->pages_pin_count) |
1674 | return -EBUSY; | |
1675 | ||
a2165e31 CW |
1676 | /* ->put_pages might need to allocate memory for the bit17 swizzle |
1677 | * array, hence protect them from being reaped by removing them from gtt | |
1678 | * lists early. */ | |
1679 | list_del(&obj->gtt_list); | |
1680 | ||
37e680a1 | 1681 | ops->put_pages(obj); |
05394f39 | 1682 | obj->pages = NULL; |
37e680a1 | 1683 | |
6c085a72 CW |
1684 | if (i915_gem_object_is_purgeable(obj)) |
1685 | i915_gem_object_truncate(obj); | |
1686 | ||
1687 | return 0; | |
1688 | } | |
1689 | ||
1690 | static long | |
93927ca5 DV |
1691 | __i915_gem_shrink(struct drm_i915_private *dev_priv, long target, |
1692 | bool purgeable_only) | |
6c085a72 CW |
1693 | { |
1694 | struct drm_i915_gem_object *obj, *next; | |
1695 | long count = 0; | |
1696 | ||
1697 | list_for_each_entry_safe(obj, next, | |
1698 | &dev_priv->mm.unbound_list, | |
1699 | gtt_list) { | |
93927ca5 | 1700 | if ((i915_gem_object_is_purgeable(obj) || !purgeable_only) && |
37e680a1 | 1701 | i915_gem_object_put_pages(obj) == 0) { |
6c085a72 CW |
1702 | count += obj->base.size >> PAGE_SHIFT; |
1703 | if (count >= target) | |
1704 | return count; | |
1705 | } | |
1706 | } | |
1707 | ||
1708 | list_for_each_entry_safe(obj, next, | |
1709 | &dev_priv->mm.inactive_list, | |
1710 | mm_list) { | |
93927ca5 | 1711 | if ((i915_gem_object_is_purgeable(obj) || !purgeable_only) && |
6c085a72 | 1712 | i915_gem_object_unbind(obj) == 0 && |
37e680a1 | 1713 | i915_gem_object_put_pages(obj) == 0) { |
6c085a72 CW |
1714 | count += obj->base.size >> PAGE_SHIFT; |
1715 | if (count >= target) | |
1716 | return count; | |
1717 | } | |
1718 | } | |
1719 | ||
1720 | return count; | |
1721 | } | |
1722 | ||
93927ca5 DV |
1723 | static long |
1724 | i915_gem_purge(struct drm_i915_private *dev_priv, long target) | |
1725 | { | |
1726 | return __i915_gem_shrink(dev_priv, target, true); | |
1727 | } | |
1728 | ||
6c085a72 CW |
1729 | static void |
1730 | i915_gem_shrink_all(struct drm_i915_private *dev_priv) | |
1731 | { | |
1732 | struct drm_i915_gem_object *obj, *next; | |
1733 | ||
1734 | i915_gem_evict_everything(dev_priv->dev); | |
1735 | ||
1736 | list_for_each_entry_safe(obj, next, &dev_priv->mm.unbound_list, gtt_list) | |
37e680a1 | 1737 | i915_gem_object_put_pages(obj); |
225067ee DV |
1738 | } |
1739 | ||
37e680a1 | 1740 | static int |
6c085a72 | 1741 | i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj) |
e5281ccd | 1742 | { |
6c085a72 | 1743 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
e5281ccd CW |
1744 | int page_count, i; |
1745 | struct address_space *mapping; | |
9da3da66 CW |
1746 | struct sg_table *st; |
1747 | struct scatterlist *sg; | |
90797e6d | 1748 | struct sg_page_iter sg_iter; |
e5281ccd | 1749 | struct page *page; |
90797e6d | 1750 | unsigned long last_pfn = 0; /* suppress gcc warning */ |
6c085a72 | 1751 | gfp_t gfp; |
e5281ccd | 1752 | |
6c085a72 CW |
1753 | /* Assert that the object is not currently in any GPU domain. As it |
1754 | * wasn't in the GTT, there shouldn't be any way it could have been in | |
1755 | * a GPU cache | |
1756 | */ | |
1757 | BUG_ON(obj->base.read_domains & I915_GEM_GPU_DOMAINS); | |
1758 | BUG_ON(obj->base.write_domain & I915_GEM_GPU_DOMAINS); | |
1759 | ||
9da3da66 CW |
1760 | st = kmalloc(sizeof(*st), GFP_KERNEL); |
1761 | if (st == NULL) | |
1762 | return -ENOMEM; | |
1763 | ||
05394f39 | 1764 | page_count = obj->base.size / PAGE_SIZE; |
9da3da66 CW |
1765 | if (sg_alloc_table(st, page_count, GFP_KERNEL)) { |
1766 | sg_free_table(st); | |
1767 | kfree(st); | |
e5281ccd | 1768 | return -ENOMEM; |
9da3da66 | 1769 | } |
e5281ccd | 1770 | |
9da3da66 CW |
1771 | /* Get the list of pages out of our struct file. They'll be pinned |
1772 | * at this point until we release them. | |
1773 | * | |
1774 | * Fail silently without starting the shrinker | |
1775 | */ | |
496ad9aa | 1776 | mapping = file_inode(obj->base.filp)->i_mapping; |
6c085a72 | 1777 | gfp = mapping_gfp_mask(mapping); |
caf49191 | 1778 | gfp |= __GFP_NORETRY | __GFP_NOWARN | __GFP_NO_KSWAPD; |
6c085a72 | 1779 | gfp &= ~(__GFP_IO | __GFP_WAIT); |
90797e6d ID |
1780 | sg = st->sgl; |
1781 | st->nents = 0; | |
1782 | for (i = 0; i < page_count; i++) { | |
6c085a72 CW |
1783 | page = shmem_read_mapping_page_gfp(mapping, i, gfp); |
1784 | if (IS_ERR(page)) { | |
1785 | i915_gem_purge(dev_priv, page_count); | |
1786 | page = shmem_read_mapping_page_gfp(mapping, i, gfp); | |
1787 | } | |
1788 | if (IS_ERR(page)) { | |
1789 | /* We've tried hard to allocate the memory by reaping | |
1790 | * our own buffer, now let the real VM do its job and | |
1791 | * go down in flames if truly OOM. | |
1792 | */ | |
caf49191 | 1793 | gfp &= ~(__GFP_NORETRY | __GFP_NOWARN | __GFP_NO_KSWAPD); |
6c085a72 CW |
1794 | gfp |= __GFP_IO | __GFP_WAIT; |
1795 | ||
1796 | i915_gem_shrink_all(dev_priv); | |
1797 | page = shmem_read_mapping_page_gfp(mapping, i, gfp); | |
1798 | if (IS_ERR(page)) | |
1799 | goto err_pages; | |
1800 | ||
caf49191 | 1801 | gfp |= __GFP_NORETRY | __GFP_NOWARN | __GFP_NO_KSWAPD; |
6c085a72 CW |
1802 | gfp &= ~(__GFP_IO | __GFP_WAIT); |
1803 | } | |
e5281ccd | 1804 | |
90797e6d ID |
1805 | if (!i || page_to_pfn(page) != last_pfn + 1) { |
1806 | if (i) | |
1807 | sg = sg_next(sg); | |
1808 | st->nents++; | |
1809 | sg_set_page(sg, page, PAGE_SIZE, 0); | |
1810 | } else { | |
1811 | sg->length += PAGE_SIZE; | |
1812 | } | |
1813 | last_pfn = page_to_pfn(page); | |
e5281ccd CW |
1814 | } |
1815 | ||
90797e6d | 1816 | sg_mark_end(sg); |
74ce6b6c CW |
1817 | obj->pages = st; |
1818 | ||
6dacfd2f | 1819 | if (i915_gem_object_needs_bit17_swizzle(obj)) |
e5281ccd CW |
1820 | i915_gem_object_do_bit_17_swizzle(obj); |
1821 | ||
1822 | return 0; | |
1823 | ||
1824 | err_pages: | |
90797e6d ID |
1825 | sg_mark_end(sg); |
1826 | for_each_sg_page(st->sgl, &sg_iter, st->nents, 0) | |
2db76d7c | 1827 | page_cache_release(sg_page_iter_page(&sg_iter)); |
9da3da66 CW |
1828 | sg_free_table(st); |
1829 | kfree(st); | |
e5281ccd | 1830 | return PTR_ERR(page); |
673a394b EA |
1831 | } |
1832 | ||
37e680a1 CW |
1833 | /* Ensure that the associated pages are gathered from the backing storage |
1834 | * and pinned into our object. i915_gem_object_get_pages() may be called | |
1835 | * multiple times before they are released by a single call to | |
1836 | * i915_gem_object_put_pages() - once the pages are no longer referenced | |
1837 | * either as a result of memory pressure (reaping pages under the shrinker) | |
1838 | * or as the object is itself released. | |
1839 | */ | |
1840 | int | |
1841 | i915_gem_object_get_pages(struct drm_i915_gem_object *obj) | |
1842 | { | |
1843 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; | |
1844 | const struct drm_i915_gem_object_ops *ops = obj->ops; | |
1845 | int ret; | |
1846 | ||
2f745ad3 | 1847 | if (obj->pages) |
37e680a1 CW |
1848 | return 0; |
1849 | ||
43e28f09 CW |
1850 | if (obj->madv != I915_MADV_WILLNEED) { |
1851 | DRM_ERROR("Attempting to obtain a purgeable object\n"); | |
1852 | return -EINVAL; | |
1853 | } | |
1854 | ||
a5570178 CW |
1855 | BUG_ON(obj->pages_pin_count); |
1856 | ||
37e680a1 CW |
1857 | ret = ops->get_pages(obj); |
1858 | if (ret) | |
1859 | return ret; | |
1860 | ||
1861 | list_add_tail(&obj->gtt_list, &dev_priv->mm.unbound_list); | |
1862 | return 0; | |
673a394b EA |
1863 | } |
1864 | ||
54cf91dc | 1865 | void |
05394f39 | 1866 | i915_gem_object_move_to_active(struct drm_i915_gem_object *obj, |
9d773091 | 1867 | struct intel_ring_buffer *ring) |
673a394b | 1868 | { |
05394f39 | 1869 | struct drm_device *dev = obj->base.dev; |
69dc4987 | 1870 | struct drm_i915_private *dev_priv = dev->dev_private; |
9d773091 | 1871 | u32 seqno = intel_ring_get_seqno(ring); |
617dbe27 | 1872 | |
852835f3 | 1873 | BUG_ON(ring == NULL); |
05394f39 | 1874 | obj->ring = ring; |
673a394b EA |
1875 | |
1876 | /* Add a reference if we're newly entering the active list. */ | |
05394f39 CW |
1877 | if (!obj->active) { |
1878 | drm_gem_object_reference(&obj->base); | |
1879 | obj->active = 1; | |
673a394b | 1880 | } |
e35a41de | 1881 | |
673a394b | 1882 | /* Move from whatever list we were on to the tail of execution. */ |
05394f39 CW |
1883 | list_move_tail(&obj->mm_list, &dev_priv->mm.active_list); |
1884 | list_move_tail(&obj->ring_list, &ring->active_list); | |
caea7476 | 1885 | |
0201f1ec | 1886 | obj->last_read_seqno = seqno; |
caea7476 | 1887 | |
7dd49065 | 1888 | if (obj->fenced_gpu_access) { |
caea7476 | 1889 | obj->last_fenced_seqno = seqno; |
caea7476 | 1890 | |
7dd49065 CW |
1891 | /* Bump MRU to take account of the delayed flush */ |
1892 | if (obj->fence_reg != I915_FENCE_REG_NONE) { | |
1893 | struct drm_i915_fence_reg *reg; | |
1894 | ||
1895 | reg = &dev_priv->fence_regs[obj->fence_reg]; | |
1896 | list_move_tail(®->lru_list, | |
1897 | &dev_priv->mm.fence_list); | |
1898 | } | |
caea7476 CW |
1899 | } |
1900 | } | |
1901 | ||
1902 | static void | |
caea7476 | 1903 | i915_gem_object_move_to_inactive(struct drm_i915_gem_object *obj) |
ce44b0ea | 1904 | { |
05394f39 | 1905 | struct drm_device *dev = obj->base.dev; |
caea7476 | 1906 | struct drm_i915_private *dev_priv = dev->dev_private; |
ce44b0ea | 1907 | |
65ce3027 | 1908 | BUG_ON(obj->base.write_domain & ~I915_GEM_GPU_DOMAINS); |
05394f39 | 1909 | BUG_ON(!obj->active); |
caea7476 | 1910 | |
1b50247a | 1911 | list_move_tail(&obj->mm_list, &dev_priv->mm.inactive_list); |
caea7476 | 1912 | |
65ce3027 | 1913 | list_del_init(&obj->ring_list); |
caea7476 CW |
1914 | obj->ring = NULL; |
1915 | ||
65ce3027 CW |
1916 | obj->last_read_seqno = 0; |
1917 | obj->last_write_seqno = 0; | |
1918 | obj->base.write_domain = 0; | |
1919 | ||
1920 | obj->last_fenced_seqno = 0; | |
caea7476 | 1921 | obj->fenced_gpu_access = false; |
caea7476 CW |
1922 | |
1923 | obj->active = 0; | |
1924 | drm_gem_object_unreference(&obj->base); | |
1925 | ||
1926 | WARN_ON(i915_verify_lists(dev)); | |
ce44b0ea | 1927 | } |
673a394b | 1928 | |
9d773091 | 1929 | static int |
fca26bb4 | 1930 | i915_gem_init_seqno(struct drm_device *dev, u32 seqno) |
53d227f2 | 1931 | { |
9d773091 CW |
1932 | struct drm_i915_private *dev_priv = dev->dev_private; |
1933 | struct intel_ring_buffer *ring; | |
1934 | int ret, i, j; | |
53d227f2 | 1935 | |
107f27a5 | 1936 | /* Carefully retire all requests without writing to the rings */ |
9d773091 | 1937 | for_each_ring(ring, dev_priv, i) { |
107f27a5 CW |
1938 | ret = intel_ring_idle(ring); |
1939 | if (ret) | |
1940 | return ret; | |
9d773091 | 1941 | } |
9d773091 | 1942 | i915_gem_retire_requests(dev); |
107f27a5 CW |
1943 | |
1944 | /* Finally reset hw state */ | |
9d773091 | 1945 | for_each_ring(ring, dev_priv, i) { |
fca26bb4 | 1946 | intel_ring_init_seqno(ring, seqno); |
498d2ac1 | 1947 | |
9d773091 CW |
1948 | for (j = 0; j < ARRAY_SIZE(ring->sync_seqno); j++) |
1949 | ring->sync_seqno[j] = 0; | |
1950 | } | |
53d227f2 | 1951 | |
9d773091 | 1952 | return 0; |
53d227f2 DV |
1953 | } |
1954 | ||
fca26bb4 MK |
1955 | int i915_gem_set_seqno(struct drm_device *dev, u32 seqno) |
1956 | { | |
1957 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1958 | int ret; | |
1959 | ||
1960 | if (seqno == 0) | |
1961 | return -EINVAL; | |
1962 | ||
1963 | /* HWS page needs to be set less than what we | |
1964 | * will inject to ring | |
1965 | */ | |
1966 | ret = i915_gem_init_seqno(dev, seqno - 1); | |
1967 | if (ret) | |
1968 | return ret; | |
1969 | ||
1970 | /* Carefully set the last_seqno value so that wrap | |
1971 | * detection still works | |
1972 | */ | |
1973 | dev_priv->next_seqno = seqno; | |
1974 | dev_priv->last_seqno = seqno - 1; | |
1975 | if (dev_priv->last_seqno == 0) | |
1976 | dev_priv->last_seqno--; | |
1977 | ||
1978 | return 0; | |
1979 | } | |
1980 | ||
9d773091 CW |
1981 | int |
1982 | i915_gem_get_seqno(struct drm_device *dev, u32 *seqno) | |
53d227f2 | 1983 | { |
9d773091 CW |
1984 | struct drm_i915_private *dev_priv = dev->dev_private; |
1985 | ||
1986 | /* reserve 0 for non-seqno */ | |
1987 | if (dev_priv->next_seqno == 0) { | |
fca26bb4 | 1988 | int ret = i915_gem_init_seqno(dev, 0); |
9d773091 CW |
1989 | if (ret) |
1990 | return ret; | |
53d227f2 | 1991 | |
9d773091 CW |
1992 | dev_priv->next_seqno = 1; |
1993 | } | |
53d227f2 | 1994 | |
f72b3435 | 1995 | *seqno = dev_priv->last_seqno = dev_priv->next_seqno++; |
9d773091 | 1996 | return 0; |
53d227f2 DV |
1997 | } |
1998 | ||
3cce469c | 1999 | int |
db53a302 | 2000 | i915_add_request(struct intel_ring_buffer *ring, |
f787a5f5 | 2001 | struct drm_file *file, |
acb868d3 | 2002 | u32 *out_seqno) |
673a394b | 2003 | { |
db53a302 | 2004 | drm_i915_private_t *dev_priv = ring->dev->dev_private; |
acb868d3 | 2005 | struct drm_i915_gem_request *request; |
a71d8d94 | 2006 | u32 request_ring_position; |
673a394b | 2007 | int was_empty; |
3cce469c CW |
2008 | int ret; |
2009 | ||
cc889e0f DV |
2010 | /* |
2011 | * Emit any outstanding flushes - execbuf can fail to emit the flush | |
2012 | * after having emitted the batchbuffer command. Hence we need to fix | |
2013 | * things up similar to emitting the lazy request. The difference here | |
2014 | * is that the flush _must_ happen before the next request, no matter | |
2015 | * what. | |
2016 | */ | |
a7b9761d CW |
2017 | ret = intel_ring_flush_all_caches(ring); |
2018 | if (ret) | |
2019 | return ret; | |
cc889e0f | 2020 | |
acb868d3 CW |
2021 | request = kmalloc(sizeof(*request), GFP_KERNEL); |
2022 | if (request == NULL) | |
2023 | return -ENOMEM; | |
cc889e0f | 2024 | |
673a394b | 2025 | |
a71d8d94 CW |
2026 | /* Record the position of the start of the request so that |
2027 | * should we detect the updated seqno part-way through the | |
2028 | * GPU processing the request, we never over-estimate the | |
2029 | * position of the head. | |
2030 | */ | |
2031 | request_ring_position = intel_ring_get_tail(ring); | |
2032 | ||
9d773091 | 2033 | ret = ring->add_request(ring); |
3bb73aba CW |
2034 | if (ret) { |
2035 | kfree(request); | |
2036 | return ret; | |
2037 | } | |
673a394b | 2038 | |
9d773091 | 2039 | request->seqno = intel_ring_get_seqno(ring); |
852835f3 | 2040 | request->ring = ring; |
a71d8d94 | 2041 | request->tail = request_ring_position; |
673a394b | 2042 | request->emitted_jiffies = jiffies; |
852835f3 ZN |
2043 | was_empty = list_empty(&ring->request_list); |
2044 | list_add_tail(&request->list, &ring->request_list); | |
3bb73aba | 2045 | request->file_priv = NULL; |
852835f3 | 2046 | |
db53a302 CW |
2047 | if (file) { |
2048 | struct drm_i915_file_private *file_priv = file->driver_priv; | |
2049 | ||
1c25595f | 2050 | spin_lock(&file_priv->mm.lock); |
f787a5f5 | 2051 | request->file_priv = file_priv; |
b962442e | 2052 | list_add_tail(&request->client_list, |
f787a5f5 | 2053 | &file_priv->mm.request_list); |
1c25595f | 2054 | spin_unlock(&file_priv->mm.lock); |
b962442e | 2055 | } |
673a394b | 2056 | |
9d773091 | 2057 | trace_i915_gem_request_add(ring, request->seqno); |
5391d0cf | 2058 | ring->outstanding_lazy_request = 0; |
db53a302 | 2059 | |
f65d9421 | 2060 | if (!dev_priv->mm.suspended) { |
3e0dc6b0 | 2061 | if (i915_enable_hangcheck) { |
99584db3 | 2062 | mod_timer(&dev_priv->gpu_error.hangcheck_timer, |
cecc21fe | 2063 | round_jiffies_up(jiffies + DRM_I915_HANGCHECK_JIFFIES)); |
3e0dc6b0 | 2064 | } |
f047e395 | 2065 | if (was_empty) { |
b3b079db | 2066 | queue_delayed_work(dev_priv->wq, |
bcb45086 CW |
2067 | &dev_priv->mm.retire_work, |
2068 | round_jiffies_up_relative(HZ)); | |
f047e395 CW |
2069 | intel_mark_busy(dev_priv->dev); |
2070 | } | |
f65d9421 | 2071 | } |
cc889e0f | 2072 | |
acb868d3 | 2073 | if (out_seqno) |
9d773091 | 2074 | *out_seqno = request->seqno; |
3cce469c | 2075 | return 0; |
673a394b EA |
2076 | } |
2077 | ||
f787a5f5 CW |
2078 | static inline void |
2079 | i915_gem_request_remove_from_client(struct drm_i915_gem_request *request) | |
673a394b | 2080 | { |
1c25595f | 2081 | struct drm_i915_file_private *file_priv = request->file_priv; |
673a394b | 2082 | |
1c25595f CW |
2083 | if (!file_priv) |
2084 | return; | |
1c5d22f7 | 2085 | |
1c25595f | 2086 | spin_lock(&file_priv->mm.lock); |
09bfa517 HRK |
2087 | if (request->file_priv) { |
2088 | list_del(&request->client_list); | |
2089 | request->file_priv = NULL; | |
2090 | } | |
1c25595f | 2091 | spin_unlock(&file_priv->mm.lock); |
673a394b | 2092 | } |
673a394b | 2093 | |
dfaae392 CW |
2094 | static void i915_gem_reset_ring_lists(struct drm_i915_private *dev_priv, |
2095 | struct intel_ring_buffer *ring) | |
9375e446 | 2096 | { |
dfaae392 CW |
2097 | while (!list_empty(&ring->request_list)) { |
2098 | struct drm_i915_gem_request *request; | |
673a394b | 2099 | |
dfaae392 CW |
2100 | request = list_first_entry(&ring->request_list, |
2101 | struct drm_i915_gem_request, | |
2102 | list); | |
de151cf6 | 2103 | |
dfaae392 | 2104 | list_del(&request->list); |
f787a5f5 | 2105 | i915_gem_request_remove_from_client(request); |
dfaae392 CW |
2106 | kfree(request); |
2107 | } | |
673a394b | 2108 | |
dfaae392 | 2109 | while (!list_empty(&ring->active_list)) { |
05394f39 | 2110 | struct drm_i915_gem_object *obj; |
9375e446 | 2111 | |
05394f39 CW |
2112 | obj = list_first_entry(&ring->active_list, |
2113 | struct drm_i915_gem_object, | |
2114 | ring_list); | |
9375e446 | 2115 | |
05394f39 | 2116 | i915_gem_object_move_to_inactive(obj); |
673a394b EA |
2117 | } |
2118 | } | |
2119 | ||
19b2dbde | 2120 | void i915_gem_restore_fences(struct drm_device *dev) |
312817a3 CW |
2121 | { |
2122 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2123 | int i; | |
2124 | ||
4b9de737 | 2125 | for (i = 0; i < dev_priv->num_fence_regs; i++) { |
312817a3 | 2126 | struct drm_i915_fence_reg *reg = &dev_priv->fence_regs[i]; |
19b2dbde | 2127 | i915_gem_write_fence(dev, i, reg->obj); |
312817a3 CW |
2128 | } |
2129 | } | |
2130 | ||
069efc1d | 2131 | void i915_gem_reset(struct drm_device *dev) |
673a394b | 2132 | { |
77f01230 | 2133 | struct drm_i915_private *dev_priv = dev->dev_private; |
05394f39 | 2134 | struct drm_i915_gem_object *obj; |
b4519513 | 2135 | struct intel_ring_buffer *ring; |
1ec14ad3 | 2136 | int i; |
673a394b | 2137 | |
b4519513 CW |
2138 | for_each_ring(ring, dev_priv, i) |
2139 | i915_gem_reset_ring_lists(dev_priv, ring); | |
dfaae392 | 2140 | |
dfaae392 CW |
2141 | /* Move everything out of the GPU domains to ensure we do any |
2142 | * necessary invalidation upon reuse. | |
2143 | */ | |
05394f39 | 2144 | list_for_each_entry(obj, |
77f01230 | 2145 | &dev_priv->mm.inactive_list, |
69dc4987 | 2146 | mm_list) |
77f01230 | 2147 | { |
05394f39 | 2148 | obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS; |
77f01230 | 2149 | } |
069efc1d | 2150 | |
19b2dbde | 2151 | i915_gem_restore_fences(dev); |
673a394b EA |
2152 | } |
2153 | ||
2154 | /** | |
2155 | * This function clears the request list as sequence numbers are passed. | |
2156 | */ | |
a71d8d94 | 2157 | void |
db53a302 | 2158 | i915_gem_retire_requests_ring(struct intel_ring_buffer *ring) |
673a394b | 2159 | { |
673a394b EA |
2160 | uint32_t seqno; |
2161 | ||
db53a302 | 2162 | if (list_empty(&ring->request_list)) |
6c0594a3 KW |
2163 | return; |
2164 | ||
db53a302 | 2165 | WARN_ON(i915_verify_lists(ring->dev)); |
673a394b | 2166 | |
b2eadbc8 | 2167 | seqno = ring->get_seqno(ring, true); |
1ec14ad3 | 2168 | |
852835f3 | 2169 | while (!list_empty(&ring->request_list)) { |
673a394b | 2170 | struct drm_i915_gem_request *request; |
673a394b | 2171 | |
852835f3 | 2172 | request = list_first_entry(&ring->request_list, |
673a394b EA |
2173 | struct drm_i915_gem_request, |
2174 | list); | |
673a394b | 2175 | |
dfaae392 | 2176 | if (!i915_seqno_passed(seqno, request->seqno)) |
b84d5f0c CW |
2177 | break; |
2178 | ||
db53a302 | 2179 | trace_i915_gem_request_retire(ring, request->seqno); |
a71d8d94 CW |
2180 | /* We know the GPU must have read the request to have |
2181 | * sent us the seqno + interrupt, so use the position | |
2182 | * of tail of the request to update the last known position | |
2183 | * of the GPU head. | |
2184 | */ | |
2185 | ring->last_retired_head = request->tail; | |
b84d5f0c CW |
2186 | |
2187 | list_del(&request->list); | |
f787a5f5 | 2188 | i915_gem_request_remove_from_client(request); |
b84d5f0c CW |
2189 | kfree(request); |
2190 | } | |
673a394b | 2191 | |
b84d5f0c CW |
2192 | /* Move any buffers on the active list that are no longer referenced |
2193 | * by the ringbuffer to the flushing/inactive lists as appropriate. | |
2194 | */ | |
2195 | while (!list_empty(&ring->active_list)) { | |
05394f39 | 2196 | struct drm_i915_gem_object *obj; |
b84d5f0c | 2197 | |
0206e353 | 2198 | obj = list_first_entry(&ring->active_list, |
05394f39 CW |
2199 | struct drm_i915_gem_object, |
2200 | ring_list); | |
673a394b | 2201 | |
0201f1ec | 2202 | if (!i915_seqno_passed(seqno, obj->last_read_seqno)) |
673a394b | 2203 | break; |
b84d5f0c | 2204 | |
65ce3027 | 2205 | i915_gem_object_move_to_inactive(obj); |
673a394b | 2206 | } |
9d34e5db | 2207 | |
db53a302 CW |
2208 | if (unlikely(ring->trace_irq_seqno && |
2209 | i915_seqno_passed(seqno, ring->trace_irq_seqno))) { | |
1ec14ad3 | 2210 | ring->irq_put(ring); |
db53a302 | 2211 | ring->trace_irq_seqno = 0; |
9d34e5db | 2212 | } |
23bc5982 | 2213 | |
db53a302 | 2214 | WARN_ON(i915_verify_lists(ring->dev)); |
673a394b EA |
2215 | } |
2216 | ||
b09a1fec CW |
2217 | void |
2218 | i915_gem_retire_requests(struct drm_device *dev) | |
2219 | { | |
2220 | drm_i915_private_t *dev_priv = dev->dev_private; | |
b4519513 | 2221 | struct intel_ring_buffer *ring; |
1ec14ad3 | 2222 | int i; |
b09a1fec | 2223 | |
b4519513 CW |
2224 | for_each_ring(ring, dev_priv, i) |
2225 | i915_gem_retire_requests_ring(ring); | |
b09a1fec CW |
2226 | } |
2227 | ||
75ef9da2 | 2228 | static void |
673a394b EA |
2229 | i915_gem_retire_work_handler(struct work_struct *work) |
2230 | { | |
2231 | drm_i915_private_t *dev_priv; | |
2232 | struct drm_device *dev; | |
b4519513 | 2233 | struct intel_ring_buffer *ring; |
0a58705b CW |
2234 | bool idle; |
2235 | int i; | |
673a394b EA |
2236 | |
2237 | dev_priv = container_of(work, drm_i915_private_t, | |
2238 | mm.retire_work.work); | |
2239 | dev = dev_priv->dev; | |
2240 | ||
891b48cf CW |
2241 | /* Come back later if the device is busy... */ |
2242 | if (!mutex_trylock(&dev->struct_mutex)) { | |
bcb45086 CW |
2243 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, |
2244 | round_jiffies_up_relative(HZ)); | |
891b48cf CW |
2245 | return; |
2246 | } | |
673a394b | 2247 | |
b09a1fec | 2248 | i915_gem_retire_requests(dev); |
673a394b | 2249 | |
0a58705b CW |
2250 | /* Send a periodic flush down the ring so we don't hold onto GEM |
2251 | * objects indefinitely. | |
673a394b | 2252 | */ |
0a58705b | 2253 | idle = true; |
b4519513 | 2254 | for_each_ring(ring, dev_priv, i) { |
3bb73aba CW |
2255 | if (ring->gpu_caches_dirty) |
2256 | i915_add_request(ring, NULL, NULL); | |
0a58705b CW |
2257 | |
2258 | idle &= list_empty(&ring->request_list); | |
673a394b EA |
2259 | } |
2260 | ||
0a58705b | 2261 | if (!dev_priv->mm.suspended && !idle) |
bcb45086 CW |
2262 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, |
2263 | round_jiffies_up_relative(HZ)); | |
f047e395 CW |
2264 | if (idle) |
2265 | intel_mark_idle(dev); | |
0a58705b | 2266 | |
673a394b | 2267 | mutex_unlock(&dev->struct_mutex); |
673a394b EA |
2268 | } |
2269 | ||
30dfebf3 DV |
2270 | /** |
2271 | * Ensures that an object will eventually get non-busy by flushing any required | |
2272 | * write domains, emitting any outstanding lazy request and retiring and | |
2273 | * completed requests. | |
2274 | */ | |
2275 | static int | |
2276 | i915_gem_object_flush_active(struct drm_i915_gem_object *obj) | |
2277 | { | |
2278 | int ret; | |
2279 | ||
2280 | if (obj->active) { | |
0201f1ec | 2281 | ret = i915_gem_check_olr(obj->ring, obj->last_read_seqno); |
30dfebf3 DV |
2282 | if (ret) |
2283 | return ret; | |
2284 | ||
30dfebf3 DV |
2285 | i915_gem_retire_requests_ring(obj->ring); |
2286 | } | |
2287 | ||
2288 | return 0; | |
2289 | } | |
2290 | ||
23ba4fd0 BW |
2291 | /** |
2292 | * i915_gem_wait_ioctl - implements DRM_IOCTL_I915_GEM_WAIT | |
2293 | * @DRM_IOCTL_ARGS: standard ioctl arguments | |
2294 | * | |
2295 | * Returns 0 if successful, else an error is returned with the remaining time in | |
2296 | * the timeout parameter. | |
2297 | * -ETIME: object is still busy after timeout | |
2298 | * -ERESTARTSYS: signal interrupted the wait | |
2299 | * -ENONENT: object doesn't exist | |
2300 | * Also possible, but rare: | |
2301 | * -EAGAIN: GPU wedged | |
2302 | * -ENOMEM: damn | |
2303 | * -ENODEV: Internal IRQ fail | |
2304 | * -E?: The add request failed | |
2305 | * | |
2306 | * The wait ioctl with a timeout of 0 reimplements the busy ioctl. With any | |
2307 | * non-zero timeout parameter the wait ioctl will wait for the given number of | |
2308 | * nanoseconds on an object becoming unbusy. Since the wait itself does so | |
2309 | * without holding struct_mutex the object may become re-busied before this | |
2310 | * function completes. A similar but shorter * race condition exists in the busy | |
2311 | * ioctl | |
2312 | */ | |
2313 | int | |
2314 | i915_gem_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *file) | |
2315 | { | |
f69061be | 2316 | drm_i915_private_t *dev_priv = dev->dev_private; |
23ba4fd0 BW |
2317 | struct drm_i915_gem_wait *args = data; |
2318 | struct drm_i915_gem_object *obj; | |
2319 | struct intel_ring_buffer *ring = NULL; | |
eac1f14f | 2320 | struct timespec timeout_stack, *timeout = NULL; |
f69061be | 2321 | unsigned reset_counter; |
23ba4fd0 BW |
2322 | u32 seqno = 0; |
2323 | int ret = 0; | |
2324 | ||
eac1f14f BW |
2325 | if (args->timeout_ns >= 0) { |
2326 | timeout_stack = ns_to_timespec(args->timeout_ns); | |
2327 | timeout = &timeout_stack; | |
2328 | } | |
23ba4fd0 BW |
2329 | |
2330 | ret = i915_mutex_lock_interruptible(dev); | |
2331 | if (ret) | |
2332 | return ret; | |
2333 | ||
2334 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->bo_handle)); | |
2335 | if (&obj->base == NULL) { | |
2336 | mutex_unlock(&dev->struct_mutex); | |
2337 | return -ENOENT; | |
2338 | } | |
2339 | ||
30dfebf3 DV |
2340 | /* Need to make sure the object gets inactive eventually. */ |
2341 | ret = i915_gem_object_flush_active(obj); | |
23ba4fd0 BW |
2342 | if (ret) |
2343 | goto out; | |
2344 | ||
2345 | if (obj->active) { | |
0201f1ec | 2346 | seqno = obj->last_read_seqno; |
23ba4fd0 BW |
2347 | ring = obj->ring; |
2348 | } | |
2349 | ||
2350 | if (seqno == 0) | |
2351 | goto out; | |
2352 | ||
23ba4fd0 BW |
2353 | /* Do this after OLR check to make sure we make forward progress polling |
2354 | * on this IOCTL with a 0 timeout (like busy ioctl) | |
2355 | */ | |
2356 | if (!args->timeout_ns) { | |
2357 | ret = -ETIME; | |
2358 | goto out; | |
2359 | } | |
2360 | ||
2361 | drm_gem_object_unreference(&obj->base); | |
f69061be | 2362 | reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter); |
23ba4fd0 BW |
2363 | mutex_unlock(&dev->struct_mutex); |
2364 | ||
f69061be | 2365 | ret = __wait_seqno(ring, seqno, reset_counter, true, timeout); |
4f42f4ef | 2366 | if (timeout) |
eac1f14f | 2367 | args->timeout_ns = timespec_to_ns(timeout); |
23ba4fd0 BW |
2368 | return ret; |
2369 | ||
2370 | out: | |
2371 | drm_gem_object_unreference(&obj->base); | |
2372 | mutex_unlock(&dev->struct_mutex); | |
2373 | return ret; | |
2374 | } | |
2375 | ||
5816d648 BW |
2376 | /** |
2377 | * i915_gem_object_sync - sync an object to a ring. | |
2378 | * | |
2379 | * @obj: object which may be in use on another ring. | |
2380 | * @to: ring we wish to use the object on. May be NULL. | |
2381 | * | |
2382 | * This code is meant to abstract object synchronization with the GPU. | |
2383 | * Calling with NULL implies synchronizing the object with the CPU | |
2384 | * rather than a particular GPU ring. | |
2385 | * | |
2386 | * Returns 0 if successful, else propagates up the lower layer error. | |
2387 | */ | |
2911a35b BW |
2388 | int |
2389 | i915_gem_object_sync(struct drm_i915_gem_object *obj, | |
2390 | struct intel_ring_buffer *to) | |
2391 | { | |
2392 | struct intel_ring_buffer *from = obj->ring; | |
2393 | u32 seqno; | |
2394 | int ret, idx; | |
2395 | ||
2396 | if (from == NULL || to == from) | |
2397 | return 0; | |
2398 | ||
5816d648 | 2399 | if (to == NULL || !i915_semaphore_is_enabled(obj->base.dev)) |
0201f1ec | 2400 | return i915_gem_object_wait_rendering(obj, false); |
2911a35b BW |
2401 | |
2402 | idx = intel_ring_sync_index(from, to); | |
2403 | ||
0201f1ec | 2404 | seqno = obj->last_read_seqno; |
2911a35b BW |
2405 | if (seqno <= from->sync_seqno[idx]) |
2406 | return 0; | |
2407 | ||
b4aca010 BW |
2408 | ret = i915_gem_check_olr(obj->ring, seqno); |
2409 | if (ret) | |
2410 | return ret; | |
2911a35b | 2411 | |
1500f7ea | 2412 | ret = to->sync_to(to, from, seqno); |
e3a5a225 | 2413 | if (!ret) |
7b01e260 MK |
2414 | /* We use last_read_seqno because sync_to() |
2415 | * might have just caused seqno wrap under | |
2416 | * the radar. | |
2417 | */ | |
2418 | from->sync_seqno[idx] = obj->last_read_seqno; | |
2911a35b | 2419 | |
e3a5a225 | 2420 | return ret; |
2911a35b BW |
2421 | } |
2422 | ||
b5ffc9bc CW |
2423 | static void i915_gem_object_finish_gtt(struct drm_i915_gem_object *obj) |
2424 | { | |
2425 | u32 old_write_domain, old_read_domains; | |
2426 | ||
b5ffc9bc CW |
2427 | /* Force a pagefault for domain tracking on next user access */ |
2428 | i915_gem_release_mmap(obj); | |
2429 | ||
b97c3d9c KP |
2430 | if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0) |
2431 | return; | |
2432 | ||
97c809fd CW |
2433 | /* Wait for any direct GTT access to complete */ |
2434 | mb(); | |
2435 | ||
b5ffc9bc CW |
2436 | old_read_domains = obj->base.read_domains; |
2437 | old_write_domain = obj->base.write_domain; | |
2438 | ||
2439 | obj->base.read_domains &= ~I915_GEM_DOMAIN_GTT; | |
2440 | obj->base.write_domain &= ~I915_GEM_DOMAIN_GTT; | |
2441 | ||
2442 | trace_i915_gem_object_change_domain(obj, | |
2443 | old_read_domains, | |
2444 | old_write_domain); | |
2445 | } | |
2446 | ||
673a394b EA |
2447 | /** |
2448 | * Unbinds an object from the GTT aperture. | |
2449 | */ | |
0f973f27 | 2450 | int |
05394f39 | 2451 | i915_gem_object_unbind(struct drm_i915_gem_object *obj) |
673a394b | 2452 | { |
7bddb01f | 2453 | drm_i915_private_t *dev_priv = obj->base.dev->dev_private; |
43e28f09 | 2454 | int ret; |
673a394b | 2455 | |
05394f39 | 2456 | if (obj->gtt_space == NULL) |
673a394b EA |
2457 | return 0; |
2458 | ||
31d8d651 CW |
2459 | if (obj->pin_count) |
2460 | return -EBUSY; | |
673a394b | 2461 | |
c4670ad0 CW |
2462 | BUG_ON(obj->pages == NULL); |
2463 | ||
a8198eea | 2464 | ret = i915_gem_object_finish_gpu(obj); |
1488fc08 | 2465 | if (ret) |
a8198eea CW |
2466 | return ret; |
2467 | /* Continue on if we fail due to EIO, the GPU is hung so we | |
2468 | * should be safe and we need to cleanup or else we might | |
2469 | * cause memory corruption through use-after-free. | |
2470 | */ | |
2471 | ||
b5ffc9bc | 2472 | i915_gem_object_finish_gtt(obj); |
5323fd04 | 2473 | |
96b47b65 | 2474 | /* release the fence reg _after_ flushing */ |
d9e86c0e | 2475 | ret = i915_gem_object_put_fence(obj); |
1488fc08 | 2476 | if (ret) |
d9e86c0e | 2477 | return ret; |
96b47b65 | 2478 | |
db53a302 CW |
2479 | trace_i915_gem_object_unbind(obj); |
2480 | ||
74898d7e DV |
2481 | if (obj->has_global_gtt_mapping) |
2482 | i915_gem_gtt_unbind_object(obj); | |
7bddb01f DV |
2483 | if (obj->has_aliasing_ppgtt_mapping) { |
2484 | i915_ppgtt_unbind_object(dev_priv->mm.aliasing_ppgtt, obj); | |
2485 | obj->has_aliasing_ppgtt_mapping = 0; | |
2486 | } | |
74163907 | 2487 | i915_gem_gtt_finish_object(obj); |
7bddb01f | 2488 | |
6c085a72 CW |
2489 | list_del(&obj->mm_list); |
2490 | list_move_tail(&obj->gtt_list, &dev_priv->mm.unbound_list); | |
75e9e915 | 2491 | /* Avoid an unnecessary call to unbind on rebind. */ |
05394f39 | 2492 | obj->map_and_fenceable = true; |
673a394b | 2493 | |
05394f39 CW |
2494 | drm_mm_put_block(obj->gtt_space); |
2495 | obj->gtt_space = NULL; | |
2496 | obj->gtt_offset = 0; | |
673a394b | 2497 | |
88241785 | 2498 | return 0; |
54cf91dc CW |
2499 | } |
2500 | ||
b2da9fe5 | 2501 | int i915_gpu_idle(struct drm_device *dev) |
4df2faf4 DV |
2502 | { |
2503 | drm_i915_private_t *dev_priv = dev->dev_private; | |
b4519513 | 2504 | struct intel_ring_buffer *ring; |
1ec14ad3 | 2505 | int ret, i; |
4df2faf4 | 2506 | |
4df2faf4 | 2507 | /* Flush everything onto the inactive list. */ |
b4519513 | 2508 | for_each_ring(ring, dev_priv, i) { |
b6c7488d BW |
2509 | ret = i915_switch_context(ring, NULL, DEFAULT_CONTEXT_ID); |
2510 | if (ret) | |
2511 | return ret; | |
2512 | ||
3e960501 | 2513 | ret = intel_ring_idle(ring); |
1ec14ad3 CW |
2514 | if (ret) |
2515 | return ret; | |
2516 | } | |
4df2faf4 | 2517 | |
8a1a49f9 | 2518 | return 0; |
4df2faf4 DV |
2519 | } |
2520 | ||
9ce079e4 CW |
2521 | static void i965_write_fence_reg(struct drm_device *dev, int reg, |
2522 | struct drm_i915_gem_object *obj) | |
de151cf6 | 2523 | { |
de151cf6 | 2524 | drm_i915_private_t *dev_priv = dev->dev_private; |
56c844e5 ID |
2525 | int fence_reg; |
2526 | int fence_pitch_shift; | |
de151cf6 JB |
2527 | uint64_t val; |
2528 | ||
56c844e5 ID |
2529 | if (INTEL_INFO(dev)->gen >= 6) { |
2530 | fence_reg = FENCE_REG_SANDYBRIDGE_0; | |
2531 | fence_pitch_shift = SANDYBRIDGE_FENCE_PITCH_SHIFT; | |
2532 | } else { | |
2533 | fence_reg = FENCE_REG_965_0; | |
2534 | fence_pitch_shift = I965_FENCE_PITCH_SHIFT; | |
2535 | } | |
2536 | ||
9ce079e4 CW |
2537 | if (obj) { |
2538 | u32 size = obj->gtt_space->size; | |
de151cf6 | 2539 | |
9ce079e4 CW |
2540 | val = (uint64_t)((obj->gtt_offset + size - 4096) & |
2541 | 0xfffff000) << 32; | |
2542 | val |= obj->gtt_offset & 0xfffff000; | |
56c844e5 | 2543 | val |= (uint64_t)((obj->stride / 128) - 1) << fence_pitch_shift; |
9ce079e4 CW |
2544 | if (obj->tiling_mode == I915_TILING_Y) |
2545 | val |= 1 << I965_FENCE_TILING_Y_SHIFT; | |
2546 | val |= I965_FENCE_REG_VALID; | |
2547 | } else | |
2548 | val = 0; | |
c6642782 | 2549 | |
56c844e5 ID |
2550 | fence_reg += reg * 8; |
2551 | I915_WRITE64(fence_reg, val); | |
2552 | POSTING_READ(fence_reg); | |
de151cf6 JB |
2553 | } |
2554 | ||
9ce079e4 CW |
2555 | static void i915_write_fence_reg(struct drm_device *dev, int reg, |
2556 | struct drm_i915_gem_object *obj) | |
de151cf6 | 2557 | { |
de151cf6 | 2558 | drm_i915_private_t *dev_priv = dev->dev_private; |
9ce079e4 | 2559 | u32 val; |
de151cf6 | 2560 | |
9ce079e4 CW |
2561 | if (obj) { |
2562 | u32 size = obj->gtt_space->size; | |
2563 | int pitch_val; | |
2564 | int tile_width; | |
c6642782 | 2565 | |
9ce079e4 CW |
2566 | WARN((obj->gtt_offset & ~I915_FENCE_START_MASK) || |
2567 | (size & -size) != size || | |
2568 | (obj->gtt_offset & (size - 1)), | |
2569 | "object 0x%08x [fenceable? %d] not 1M or pot-size (0x%08x) aligned\n", | |
2570 | obj->gtt_offset, obj->map_and_fenceable, size); | |
c6642782 | 2571 | |
9ce079e4 CW |
2572 | if (obj->tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev)) |
2573 | tile_width = 128; | |
2574 | else | |
2575 | tile_width = 512; | |
2576 | ||
2577 | /* Note: pitch better be a power of two tile widths */ | |
2578 | pitch_val = obj->stride / tile_width; | |
2579 | pitch_val = ffs(pitch_val) - 1; | |
2580 | ||
2581 | val = obj->gtt_offset; | |
2582 | if (obj->tiling_mode == I915_TILING_Y) | |
2583 | val |= 1 << I830_FENCE_TILING_Y_SHIFT; | |
2584 | val |= I915_FENCE_SIZE_BITS(size); | |
2585 | val |= pitch_val << I830_FENCE_PITCH_SHIFT; | |
2586 | val |= I830_FENCE_REG_VALID; | |
2587 | } else | |
2588 | val = 0; | |
2589 | ||
2590 | if (reg < 8) | |
2591 | reg = FENCE_REG_830_0 + reg * 4; | |
2592 | else | |
2593 | reg = FENCE_REG_945_8 + (reg - 8) * 4; | |
2594 | ||
2595 | I915_WRITE(reg, val); | |
2596 | POSTING_READ(reg); | |
de151cf6 JB |
2597 | } |
2598 | ||
9ce079e4 CW |
2599 | static void i830_write_fence_reg(struct drm_device *dev, int reg, |
2600 | struct drm_i915_gem_object *obj) | |
de151cf6 | 2601 | { |
de151cf6 | 2602 | drm_i915_private_t *dev_priv = dev->dev_private; |
de151cf6 | 2603 | uint32_t val; |
de151cf6 | 2604 | |
9ce079e4 CW |
2605 | if (obj) { |
2606 | u32 size = obj->gtt_space->size; | |
2607 | uint32_t pitch_val; | |
de151cf6 | 2608 | |
9ce079e4 CW |
2609 | WARN((obj->gtt_offset & ~I830_FENCE_START_MASK) || |
2610 | (size & -size) != size || | |
2611 | (obj->gtt_offset & (size - 1)), | |
2612 | "object 0x%08x not 512K or pot-size 0x%08x aligned\n", | |
2613 | obj->gtt_offset, size); | |
e76a16de | 2614 | |
9ce079e4 CW |
2615 | pitch_val = obj->stride / 128; |
2616 | pitch_val = ffs(pitch_val) - 1; | |
de151cf6 | 2617 | |
9ce079e4 CW |
2618 | val = obj->gtt_offset; |
2619 | if (obj->tiling_mode == I915_TILING_Y) | |
2620 | val |= 1 << I830_FENCE_TILING_Y_SHIFT; | |
2621 | val |= I830_FENCE_SIZE_BITS(size); | |
2622 | val |= pitch_val << I830_FENCE_PITCH_SHIFT; | |
2623 | val |= I830_FENCE_REG_VALID; | |
2624 | } else | |
2625 | val = 0; | |
c6642782 | 2626 | |
9ce079e4 CW |
2627 | I915_WRITE(FENCE_REG_830_0 + reg * 4, val); |
2628 | POSTING_READ(FENCE_REG_830_0 + reg * 4); | |
2629 | } | |
2630 | ||
d0a57789 CW |
2631 | inline static bool i915_gem_object_needs_mb(struct drm_i915_gem_object *obj) |
2632 | { | |
2633 | return obj && obj->base.read_domains & I915_GEM_DOMAIN_GTT; | |
2634 | } | |
2635 | ||
9ce079e4 CW |
2636 | static void i915_gem_write_fence(struct drm_device *dev, int reg, |
2637 | struct drm_i915_gem_object *obj) | |
2638 | { | |
d0a57789 CW |
2639 | struct drm_i915_private *dev_priv = dev->dev_private; |
2640 | ||
2641 | /* Ensure that all CPU reads are completed before installing a fence | |
2642 | * and all writes before removing the fence. | |
2643 | */ | |
2644 | if (i915_gem_object_needs_mb(dev_priv->fence_regs[reg].obj)) | |
2645 | mb(); | |
2646 | ||
9ce079e4 CW |
2647 | switch (INTEL_INFO(dev)->gen) { |
2648 | case 7: | |
56c844e5 | 2649 | case 6: |
9ce079e4 CW |
2650 | case 5: |
2651 | case 4: i965_write_fence_reg(dev, reg, obj); break; | |
2652 | case 3: i915_write_fence_reg(dev, reg, obj); break; | |
2653 | case 2: i830_write_fence_reg(dev, reg, obj); break; | |
7dbf9d6e | 2654 | default: BUG(); |
9ce079e4 | 2655 | } |
d0a57789 CW |
2656 | |
2657 | /* And similarly be paranoid that no direct access to this region | |
2658 | * is reordered to before the fence is installed. | |
2659 | */ | |
2660 | if (i915_gem_object_needs_mb(obj)) | |
2661 | mb(); | |
de151cf6 JB |
2662 | } |
2663 | ||
61050808 CW |
2664 | static inline int fence_number(struct drm_i915_private *dev_priv, |
2665 | struct drm_i915_fence_reg *fence) | |
2666 | { | |
2667 | return fence - dev_priv->fence_regs; | |
2668 | } | |
2669 | ||
25ff1195 CW |
2670 | static void i915_gem_write_fence__ipi(void *data) |
2671 | { | |
2672 | wbinvd(); | |
2673 | } | |
2674 | ||
61050808 CW |
2675 | static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj, |
2676 | struct drm_i915_fence_reg *fence, | |
2677 | bool enable) | |
2678 | { | |
25ff1195 CW |
2679 | struct drm_device *dev = obj->base.dev; |
2680 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2681 | int fence_reg = fence_number(dev_priv, fence); | |
2682 | ||
2683 | /* In order to fully serialize access to the fenced region and | |
2684 | * the update to the fence register we need to take extreme | |
2685 | * measures on SNB+. In theory, the write to the fence register | |
2686 | * flushes all memory transactions before, and coupled with the | |
2687 | * mb() placed around the register write we serialise all memory | |
2688 | * operations with respect to the changes in the tiler. Yet, on | |
2689 | * SNB+ we need to take a step further and emit an explicit wbinvd() | |
2690 | * on each processor in order to manually flush all memory | |
2691 | * transactions before updating the fence register. | |
2692 | */ | |
2693 | if (HAS_LLC(obj->base.dev)) | |
2694 | on_each_cpu(i915_gem_write_fence__ipi, NULL, 1); | |
2695 | i915_gem_write_fence(dev, fence_reg, enable ? obj : NULL); | |
61050808 CW |
2696 | |
2697 | if (enable) { | |
25ff1195 | 2698 | obj->fence_reg = fence_reg; |
61050808 CW |
2699 | fence->obj = obj; |
2700 | list_move_tail(&fence->lru_list, &dev_priv->mm.fence_list); | |
2701 | } else { | |
2702 | obj->fence_reg = I915_FENCE_REG_NONE; | |
2703 | fence->obj = NULL; | |
2704 | list_del_init(&fence->lru_list); | |
2705 | } | |
2706 | } | |
2707 | ||
d9e86c0e | 2708 | static int |
d0a57789 | 2709 | i915_gem_object_wait_fence(struct drm_i915_gem_object *obj) |
d9e86c0e | 2710 | { |
1c293ea3 | 2711 | if (obj->last_fenced_seqno) { |
86d5bc37 | 2712 | int ret = i915_wait_seqno(obj->ring, obj->last_fenced_seqno); |
18991845 CW |
2713 | if (ret) |
2714 | return ret; | |
d9e86c0e CW |
2715 | |
2716 | obj->last_fenced_seqno = 0; | |
d9e86c0e CW |
2717 | } |
2718 | ||
86d5bc37 | 2719 | obj->fenced_gpu_access = false; |
d9e86c0e CW |
2720 | return 0; |
2721 | } | |
2722 | ||
2723 | int | |
2724 | i915_gem_object_put_fence(struct drm_i915_gem_object *obj) | |
2725 | { | |
61050808 | 2726 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
f9c513e9 | 2727 | struct drm_i915_fence_reg *fence; |
d9e86c0e CW |
2728 | int ret; |
2729 | ||
d0a57789 | 2730 | ret = i915_gem_object_wait_fence(obj); |
d9e86c0e CW |
2731 | if (ret) |
2732 | return ret; | |
2733 | ||
61050808 CW |
2734 | if (obj->fence_reg == I915_FENCE_REG_NONE) |
2735 | return 0; | |
d9e86c0e | 2736 | |
f9c513e9 CW |
2737 | fence = &dev_priv->fence_regs[obj->fence_reg]; |
2738 | ||
61050808 | 2739 | i915_gem_object_fence_lost(obj); |
f9c513e9 | 2740 | i915_gem_object_update_fence(obj, fence, false); |
d9e86c0e CW |
2741 | |
2742 | return 0; | |
2743 | } | |
2744 | ||
2745 | static struct drm_i915_fence_reg * | |
a360bb1a | 2746 | i915_find_fence_reg(struct drm_device *dev) |
ae3db24a | 2747 | { |
ae3db24a | 2748 | struct drm_i915_private *dev_priv = dev->dev_private; |
8fe301ad | 2749 | struct drm_i915_fence_reg *reg, *avail; |
d9e86c0e | 2750 | int i; |
ae3db24a DV |
2751 | |
2752 | /* First try to find a free reg */ | |
d9e86c0e | 2753 | avail = NULL; |
ae3db24a DV |
2754 | for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) { |
2755 | reg = &dev_priv->fence_regs[i]; | |
2756 | if (!reg->obj) | |
d9e86c0e | 2757 | return reg; |
ae3db24a | 2758 | |
1690e1eb | 2759 | if (!reg->pin_count) |
d9e86c0e | 2760 | avail = reg; |
ae3db24a DV |
2761 | } |
2762 | ||
d9e86c0e CW |
2763 | if (avail == NULL) |
2764 | return NULL; | |
ae3db24a DV |
2765 | |
2766 | /* None available, try to steal one or wait for a user to finish */ | |
d9e86c0e | 2767 | list_for_each_entry(reg, &dev_priv->mm.fence_list, lru_list) { |
1690e1eb | 2768 | if (reg->pin_count) |
ae3db24a DV |
2769 | continue; |
2770 | ||
8fe301ad | 2771 | return reg; |
ae3db24a DV |
2772 | } |
2773 | ||
8fe301ad | 2774 | return NULL; |
ae3db24a DV |
2775 | } |
2776 | ||
de151cf6 | 2777 | /** |
9a5a53b3 | 2778 | * i915_gem_object_get_fence - set up fencing for an object |
de151cf6 JB |
2779 | * @obj: object to map through a fence reg |
2780 | * | |
2781 | * When mapping objects through the GTT, userspace wants to be able to write | |
2782 | * to them without having to worry about swizzling if the object is tiled. | |
de151cf6 JB |
2783 | * This function walks the fence regs looking for a free one for @obj, |
2784 | * stealing one if it can't find any. | |
2785 | * | |
2786 | * It then sets up the reg based on the object's properties: address, pitch | |
2787 | * and tiling format. | |
9a5a53b3 CW |
2788 | * |
2789 | * For an untiled surface, this removes any existing fence. | |
de151cf6 | 2790 | */ |
8c4b8c3f | 2791 | int |
06d98131 | 2792 | i915_gem_object_get_fence(struct drm_i915_gem_object *obj) |
de151cf6 | 2793 | { |
05394f39 | 2794 | struct drm_device *dev = obj->base.dev; |
79e53945 | 2795 | struct drm_i915_private *dev_priv = dev->dev_private; |
14415745 | 2796 | bool enable = obj->tiling_mode != I915_TILING_NONE; |
d9e86c0e | 2797 | struct drm_i915_fence_reg *reg; |
ae3db24a | 2798 | int ret; |
de151cf6 | 2799 | |
14415745 CW |
2800 | /* Have we updated the tiling parameters upon the object and so |
2801 | * will need to serialise the write to the associated fence register? | |
2802 | */ | |
5d82e3e6 | 2803 | if (obj->fence_dirty) { |
d0a57789 | 2804 | ret = i915_gem_object_wait_fence(obj); |
14415745 CW |
2805 | if (ret) |
2806 | return ret; | |
2807 | } | |
9a5a53b3 | 2808 | |
d9e86c0e | 2809 | /* Just update our place in the LRU if our fence is getting reused. */ |
05394f39 CW |
2810 | if (obj->fence_reg != I915_FENCE_REG_NONE) { |
2811 | reg = &dev_priv->fence_regs[obj->fence_reg]; | |
5d82e3e6 | 2812 | if (!obj->fence_dirty) { |
14415745 CW |
2813 | list_move_tail(®->lru_list, |
2814 | &dev_priv->mm.fence_list); | |
2815 | return 0; | |
2816 | } | |
2817 | } else if (enable) { | |
2818 | reg = i915_find_fence_reg(dev); | |
2819 | if (reg == NULL) | |
2820 | return -EDEADLK; | |
d9e86c0e | 2821 | |
14415745 CW |
2822 | if (reg->obj) { |
2823 | struct drm_i915_gem_object *old = reg->obj; | |
2824 | ||
d0a57789 | 2825 | ret = i915_gem_object_wait_fence(old); |
29c5a587 CW |
2826 | if (ret) |
2827 | return ret; | |
2828 | ||
14415745 | 2829 | i915_gem_object_fence_lost(old); |
29c5a587 | 2830 | } |
14415745 | 2831 | } else |
a09ba7fa | 2832 | return 0; |
a09ba7fa | 2833 | |
14415745 | 2834 | i915_gem_object_update_fence(obj, reg, enable); |
5d82e3e6 | 2835 | obj->fence_dirty = false; |
14415745 | 2836 | |
9ce079e4 | 2837 | return 0; |
de151cf6 JB |
2838 | } |
2839 | ||
42d6ab48 CW |
2840 | static bool i915_gem_valid_gtt_space(struct drm_device *dev, |
2841 | struct drm_mm_node *gtt_space, | |
2842 | unsigned long cache_level) | |
2843 | { | |
2844 | struct drm_mm_node *other; | |
2845 | ||
2846 | /* On non-LLC machines we have to be careful when putting differing | |
2847 | * types of snoopable memory together to avoid the prefetcher | |
4239ca77 | 2848 | * crossing memory domains and dying. |
42d6ab48 CW |
2849 | */ |
2850 | if (HAS_LLC(dev)) | |
2851 | return true; | |
2852 | ||
2853 | if (gtt_space == NULL) | |
2854 | return true; | |
2855 | ||
2856 | if (list_empty(>t_space->node_list)) | |
2857 | return true; | |
2858 | ||
2859 | other = list_entry(gtt_space->node_list.prev, struct drm_mm_node, node_list); | |
2860 | if (other->allocated && !other->hole_follows && other->color != cache_level) | |
2861 | return false; | |
2862 | ||
2863 | other = list_entry(gtt_space->node_list.next, struct drm_mm_node, node_list); | |
2864 | if (other->allocated && !gtt_space->hole_follows && other->color != cache_level) | |
2865 | return false; | |
2866 | ||
2867 | return true; | |
2868 | } | |
2869 | ||
2870 | static void i915_gem_verify_gtt(struct drm_device *dev) | |
2871 | { | |
2872 | #if WATCH_GTT | |
2873 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2874 | struct drm_i915_gem_object *obj; | |
2875 | int err = 0; | |
2876 | ||
2877 | list_for_each_entry(obj, &dev_priv->mm.gtt_list, gtt_list) { | |
2878 | if (obj->gtt_space == NULL) { | |
2879 | printk(KERN_ERR "object found on GTT list with no space reserved\n"); | |
2880 | err++; | |
2881 | continue; | |
2882 | } | |
2883 | ||
2884 | if (obj->cache_level != obj->gtt_space->color) { | |
2885 | printk(KERN_ERR "object reserved space [%08lx, %08lx] with wrong color, cache_level=%x, color=%lx\n", | |
2886 | obj->gtt_space->start, | |
2887 | obj->gtt_space->start + obj->gtt_space->size, | |
2888 | obj->cache_level, | |
2889 | obj->gtt_space->color); | |
2890 | err++; | |
2891 | continue; | |
2892 | } | |
2893 | ||
2894 | if (!i915_gem_valid_gtt_space(dev, | |
2895 | obj->gtt_space, | |
2896 | obj->cache_level)) { | |
2897 | printk(KERN_ERR "invalid GTT space found at [%08lx, %08lx] - color=%x\n", | |
2898 | obj->gtt_space->start, | |
2899 | obj->gtt_space->start + obj->gtt_space->size, | |
2900 | obj->cache_level); | |
2901 | err++; | |
2902 | continue; | |
2903 | } | |
2904 | } | |
2905 | ||
2906 | WARN_ON(err); | |
2907 | #endif | |
2908 | } | |
2909 | ||
673a394b EA |
2910 | /** |
2911 | * Finds free space in the GTT aperture and binds the object there. | |
2912 | */ | |
2913 | static int | |
05394f39 | 2914 | i915_gem_object_bind_to_gtt(struct drm_i915_gem_object *obj, |
920afa77 | 2915 | unsigned alignment, |
86a1ee26 CW |
2916 | bool map_and_fenceable, |
2917 | bool nonblocking) | |
673a394b | 2918 | { |
05394f39 | 2919 | struct drm_device *dev = obj->base.dev; |
673a394b | 2920 | drm_i915_private_t *dev_priv = dev->dev_private; |
dc9dd7a2 | 2921 | struct drm_mm_node *node; |
5e783301 | 2922 | u32 size, fence_size, fence_alignment, unfenced_alignment; |
75e9e915 | 2923 | bool mappable, fenceable; |
07f73f69 | 2924 | int ret; |
673a394b | 2925 | |
e28f8711 CW |
2926 | fence_size = i915_gem_get_gtt_size(dev, |
2927 | obj->base.size, | |
2928 | obj->tiling_mode); | |
2929 | fence_alignment = i915_gem_get_gtt_alignment(dev, | |
2930 | obj->base.size, | |
d865110c | 2931 | obj->tiling_mode, true); |
e28f8711 | 2932 | unfenced_alignment = |
d865110c | 2933 | i915_gem_get_gtt_alignment(dev, |
e28f8711 | 2934 | obj->base.size, |
d865110c | 2935 | obj->tiling_mode, false); |
a00b10c3 | 2936 | |
673a394b | 2937 | if (alignment == 0) |
5e783301 DV |
2938 | alignment = map_and_fenceable ? fence_alignment : |
2939 | unfenced_alignment; | |
75e9e915 | 2940 | if (map_and_fenceable && alignment & (fence_alignment - 1)) { |
673a394b EA |
2941 | DRM_ERROR("Invalid object alignment requested %u\n", alignment); |
2942 | return -EINVAL; | |
2943 | } | |
2944 | ||
05394f39 | 2945 | size = map_and_fenceable ? fence_size : obj->base.size; |
a00b10c3 | 2946 | |
654fc607 CW |
2947 | /* If the object is bigger than the entire aperture, reject it early |
2948 | * before evicting everything in a vain attempt to find space. | |
2949 | */ | |
05394f39 | 2950 | if (obj->base.size > |
5d4545ae | 2951 | (map_and_fenceable ? dev_priv->gtt.mappable_end : dev_priv->gtt.total)) { |
654fc607 CW |
2952 | DRM_ERROR("Attempting to bind an object larger than the aperture\n"); |
2953 | return -E2BIG; | |
2954 | } | |
2955 | ||
37e680a1 | 2956 | ret = i915_gem_object_get_pages(obj); |
6c085a72 CW |
2957 | if (ret) |
2958 | return ret; | |
2959 | ||
fbdda6fb CW |
2960 | i915_gem_object_pin_pages(obj); |
2961 | ||
dc9dd7a2 CW |
2962 | node = kzalloc(sizeof(*node), GFP_KERNEL); |
2963 | if (node == NULL) { | |
2964 | i915_gem_object_unpin_pages(obj); | |
2965 | return -ENOMEM; | |
2966 | } | |
2967 | ||
673a394b | 2968 | search_free: |
75e9e915 | 2969 | if (map_and_fenceable) |
dc9dd7a2 CW |
2970 | ret = drm_mm_insert_node_in_range_generic(&dev_priv->mm.gtt_space, node, |
2971 | size, alignment, obj->cache_level, | |
5d4545ae | 2972 | 0, dev_priv->gtt.mappable_end); |
920afa77 | 2973 | else |
dc9dd7a2 CW |
2974 | ret = drm_mm_insert_node_generic(&dev_priv->mm.gtt_space, node, |
2975 | size, alignment, obj->cache_level); | |
2976 | if (ret) { | |
75e9e915 | 2977 | ret = i915_gem_evict_something(dev, size, alignment, |
42d6ab48 | 2978 | obj->cache_level, |
86a1ee26 CW |
2979 | map_and_fenceable, |
2980 | nonblocking); | |
dc9dd7a2 CW |
2981 | if (ret == 0) |
2982 | goto search_free; | |
9731129c | 2983 | |
dc9dd7a2 CW |
2984 | i915_gem_object_unpin_pages(obj); |
2985 | kfree(node); | |
2986 | return ret; | |
673a394b | 2987 | } |
dc9dd7a2 | 2988 | if (WARN_ON(!i915_gem_valid_gtt_space(dev, node, obj->cache_level))) { |
fbdda6fb | 2989 | i915_gem_object_unpin_pages(obj); |
dc9dd7a2 | 2990 | drm_mm_put_block(node); |
42d6ab48 | 2991 | return -EINVAL; |
673a394b EA |
2992 | } |
2993 | ||
74163907 | 2994 | ret = i915_gem_gtt_prepare_object(obj); |
7c2e6fdf | 2995 | if (ret) { |
fbdda6fb | 2996 | i915_gem_object_unpin_pages(obj); |
dc9dd7a2 | 2997 | drm_mm_put_block(node); |
6c085a72 | 2998 | return ret; |
673a394b | 2999 | } |
673a394b | 3000 | |
6c085a72 | 3001 | list_move_tail(&obj->gtt_list, &dev_priv->mm.bound_list); |
05394f39 | 3002 | list_add_tail(&obj->mm_list, &dev_priv->mm.inactive_list); |
bf1a1092 | 3003 | |
dc9dd7a2 CW |
3004 | obj->gtt_space = node; |
3005 | obj->gtt_offset = node->start; | |
1c5d22f7 | 3006 | |
75e9e915 | 3007 | fenceable = |
dc9dd7a2 CW |
3008 | node->size == fence_size && |
3009 | (node->start & (fence_alignment - 1)) == 0; | |
a00b10c3 | 3010 | |
75e9e915 | 3011 | mappable = |
5d4545ae | 3012 | obj->gtt_offset + obj->base.size <= dev_priv->gtt.mappable_end; |
a00b10c3 | 3013 | |
05394f39 | 3014 | obj->map_and_fenceable = mappable && fenceable; |
75e9e915 | 3015 | |
fbdda6fb | 3016 | i915_gem_object_unpin_pages(obj); |
db53a302 | 3017 | trace_i915_gem_object_bind(obj, map_and_fenceable); |
42d6ab48 | 3018 | i915_gem_verify_gtt(dev); |
673a394b EA |
3019 | return 0; |
3020 | } | |
3021 | ||
3022 | void | |
05394f39 | 3023 | i915_gem_clflush_object(struct drm_i915_gem_object *obj) |
673a394b | 3024 | { |
673a394b EA |
3025 | /* If we don't have a page list set up, then we're not pinned |
3026 | * to GPU, and we can ignore the cache flush because it'll happen | |
3027 | * again at bind time. | |
3028 | */ | |
05394f39 | 3029 | if (obj->pages == NULL) |
673a394b EA |
3030 | return; |
3031 | ||
769ce464 ID |
3032 | /* |
3033 | * Stolen memory is always coherent with the GPU as it is explicitly | |
3034 | * marked as wc by the system, or the system is cache-coherent. | |
3035 | */ | |
3036 | if (obj->stolen) | |
3037 | return; | |
3038 | ||
9c23f7fc CW |
3039 | /* If the GPU is snooping the contents of the CPU cache, |
3040 | * we do not need to manually clear the CPU cache lines. However, | |
3041 | * the caches are only snooped when the render cache is | |
3042 | * flushed/invalidated. As we always have to emit invalidations | |
3043 | * and flushes when moving into and out of the RENDER domain, correct | |
3044 | * snooping behaviour occurs naturally as the result of our domain | |
3045 | * tracking. | |
3046 | */ | |
3047 | if (obj->cache_level != I915_CACHE_NONE) | |
3048 | return; | |
3049 | ||
1c5d22f7 | 3050 | trace_i915_gem_object_clflush(obj); |
cfa16a0d | 3051 | |
9da3da66 | 3052 | drm_clflush_sg(obj->pages); |
e47c68e9 EA |
3053 | } |
3054 | ||
3055 | /** Flushes the GTT write domain for the object if it's dirty. */ | |
3056 | static void | |
05394f39 | 3057 | i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj) |
e47c68e9 | 3058 | { |
1c5d22f7 CW |
3059 | uint32_t old_write_domain; |
3060 | ||
05394f39 | 3061 | if (obj->base.write_domain != I915_GEM_DOMAIN_GTT) |
e47c68e9 EA |
3062 | return; |
3063 | ||
63256ec5 | 3064 | /* No actual flushing is required for the GTT write domain. Writes |
e47c68e9 EA |
3065 | * to it immediately go to main memory as far as we know, so there's |
3066 | * no chipset flush. It also doesn't land in render cache. | |
63256ec5 CW |
3067 | * |
3068 | * However, we do have to enforce the order so that all writes through | |
3069 | * the GTT land before any writes to the device, such as updates to | |
3070 | * the GATT itself. | |
e47c68e9 | 3071 | */ |
63256ec5 CW |
3072 | wmb(); |
3073 | ||
05394f39 CW |
3074 | old_write_domain = obj->base.write_domain; |
3075 | obj->base.write_domain = 0; | |
1c5d22f7 CW |
3076 | |
3077 | trace_i915_gem_object_change_domain(obj, | |
05394f39 | 3078 | obj->base.read_domains, |
1c5d22f7 | 3079 | old_write_domain); |
e47c68e9 EA |
3080 | } |
3081 | ||
3082 | /** Flushes the CPU write domain for the object if it's dirty. */ | |
3083 | static void | |
05394f39 | 3084 | i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj) |
e47c68e9 | 3085 | { |
1c5d22f7 | 3086 | uint32_t old_write_domain; |
e47c68e9 | 3087 | |
05394f39 | 3088 | if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) |
e47c68e9 EA |
3089 | return; |
3090 | ||
3091 | i915_gem_clflush_object(obj); | |
e76e9aeb | 3092 | i915_gem_chipset_flush(obj->base.dev); |
05394f39 CW |
3093 | old_write_domain = obj->base.write_domain; |
3094 | obj->base.write_domain = 0; | |
1c5d22f7 CW |
3095 | |
3096 | trace_i915_gem_object_change_domain(obj, | |
05394f39 | 3097 | obj->base.read_domains, |
1c5d22f7 | 3098 | old_write_domain); |
e47c68e9 EA |
3099 | } |
3100 | ||
2ef7eeaa EA |
3101 | /** |
3102 | * Moves a single object to the GTT read, and possibly write domain. | |
3103 | * | |
3104 | * This function returns when the move is complete, including waiting on | |
3105 | * flushes to occur. | |
3106 | */ | |
79e53945 | 3107 | int |
2021746e | 3108 | i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write) |
2ef7eeaa | 3109 | { |
8325a09d | 3110 | drm_i915_private_t *dev_priv = obj->base.dev->dev_private; |
1c5d22f7 | 3111 | uint32_t old_write_domain, old_read_domains; |
e47c68e9 | 3112 | int ret; |
2ef7eeaa | 3113 | |
02354392 | 3114 | /* Not valid to be called on unbound objects. */ |
05394f39 | 3115 | if (obj->gtt_space == NULL) |
02354392 EA |
3116 | return -EINVAL; |
3117 | ||
8d7e3de1 CW |
3118 | if (obj->base.write_domain == I915_GEM_DOMAIN_GTT) |
3119 | return 0; | |
3120 | ||
0201f1ec | 3121 | ret = i915_gem_object_wait_rendering(obj, !write); |
88241785 CW |
3122 | if (ret) |
3123 | return ret; | |
3124 | ||
7213342d | 3125 | i915_gem_object_flush_cpu_write_domain(obj); |
1c5d22f7 | 3126 | |
d0a57789 CW |
3127 | /* Serialise direct access to this object with the barriers for |
3128 | * coherent writes from the GPU, by effectively invalidating the | |
3129 | * GTT domain upon first access. | |
3130 | */ | |
3131 | if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0) | |
3132 | mb(); | |
3133 | ||
05394f39 CW |
3134 | old_write_domain = obj->base.write_domain; |
3135 | old_read_domains = obj->base.read_domains; | |
1c5d22f7 | 3136 | |
e47c68e9 EA |
3137 | /* It should now be out of any other write domains, and we can update |
3138 | * the domain values for our changes. | |
3139 | */ | |
05394f39 CW |
3140 | BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) != 0); |
3141 | obj->base.read_domains |= I915_GEM_DOMAIN_GTT; | |
e47c68e9 | 3142 | if (write) { |
05394f39 CW |
3143 | obj->base.read_domains = I915_GEM_DOMAIN_GTT; |
3144 | obj->base.write_domain = I915_GEM_DOMAIN_GTT; | |
3145 | obj->dirty = 1; | |
2ef7eeaa EA |
3146 | } |
3147 | ||
1c5d22f7 CW |
3148 | trace_i915_gem_object_change_domain(obj, |
3149 | old_read_domains, | |
3150 | old_write_domain); | |
3151 | ||
8325a09d CW |
3152 | /* And bump the LRU for this access */ |
3153 | if (i915_gem_object_is_inactive(obj)) | |
3154 | list_move_tail(&obj->mm_list, &dev_priv->mm.inactive_list); | |
3155 | ||
e47c68e9 EA |
3156 | return 0; |
3157 | } | |
3158 | ||
e4ffd173 CW |
3159 | int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj, |
3160 | enum i915_cache_level cache_level) | |
3161 | { | |
7bddb01f DV |
3162 | struct drm_device *dev = obj->base.dev; |
3163 | drm_i915_private_t *dev_priv = dev->dev_private; | |
e4ffd173 CW |
3164 | int ret; |
3165 | ||
3166 | if (obj->cache_level == cache_level) | |
3167 | return 0; | |
3168 | ||
3169 | if (obj->pin_count) { | |
3170 | DRM_DEBUG("can not change the cache level of pinned objects\n"); | |
3171 | return -EBUSY; | |
3172 | } | |
3173 | ||
42d6ab48 CW |
3174 | if (!i915_gem_valid_gtt_space(dev, obj->gtt_space, cache_level)) { |
3175 | ret = i915_gem_object_unbind(obj); | |
3176 | if (ret) | |
3177 | return ret; | |
3178 | } | |
3179 | ||
e4ffd173 CW |
3180 | if (obj->gtt_space) { |
3181 | ret = i915_gem_object_finish_gpu(obj); | |
3182 | if (ret) | |
3183 | return ret; | |
3184 | ||
3185 | i915_gem_object_finish_gtt(obj); | |
3186 | ||
3187 | /* Before SandyBridge, you could not use tiling or fence | |
3188 | * registers with snooped memory, so relinquish any fences | |
3189 | * currently pointing to our region in the aperture. | |
3190 | */ | |
42d6ab48 | 3191 | if (INTEL_INFO(dev)->gen < 6) { |
e4ffd173 CW |
3192 | ret = i915_gem_object_put_fence(obj); |
3193 | if (ret) | |
3194 | return ret; | |
3195 | } | |
3196 | ||
74898d7e DV |
3197 | if (obj->has_global_gtt_mapping) |
3198 | i915_gem_gtt_bind_object(obj, cache_level); | |
7bddb01f DV |
3199 | if (obj->has_aliasing_ppgtt_mapping) |
3200 | i915_ppgtt_bind_object(dev_priv->mm.aliasing_ppgtt, | |
3201 | obj, cache_level); | |
42d6ab48 CW |
3202 | |
3203 | obj->gtt_space->color = cache_level; | |
e4ffd173 CW |
3204 | } |
3205 | ||
3206 | if (cache_level == I915_CACHE_NONE) { | |
3207 | u32 old_read_domains, old_write_domain; | |
3208 | ||
3209 | /* If we're coming from LLC cached, then we haven't | |
3210 | * actually been tracking whether the data is in the | |
3211 | * CPU cache or not, since we only allow one bit set | |
3212 | * in obj->write_domain and have been skipping the clflushes. | |
3213 | * Just set it to the CPU cache for now. | |
3214 | */ | |
3215 | WARN_ON(obj->base.write_domain & ~I915_GEM_DOMAIN_CPU); | |
3216 | WARN_ON(obj->base.read_domains & ~I915_GEM_DOMAIN_CPU); | |
3217 | ||
3218 | old_read_domains = obj->base.read_domains; | |
3219 | old_write_domain = obj->base.write_domain; | |
3220 | ||
3221 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; | |
3222 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; | |
3223 | ||
3224 | trace_i915_gem_object_change_domain(obj, | |
3225 | old_read_domains, | |
3226 | old_write_domain); | |
3227 | } | |
3228 | ||
3229 | obj->cache_level = cache_level; | |
42d6ab48 | 3230 | i915_gem_verify_gtt(dev); |
e4ffd173 CW |
3231 | return 0; |
3232 | } | |
3233 | ||
199adf40 BW |
3234 | int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data, |
3235 | struct drm_file *file) | |
e6994aee | 3236 | { |
199adf40 | 3237 | struct drm_i915_gem_caching *args = data; |
e6994aee CW |
3238 | struct drm_i915_gem_object *obj; |
3239 | int ret; | |
3240 | ||
3241 | ret = i915_mutex_lock_interruptible(dev); | |
3242 | if (ret) | |
3243 | return ret; | |
3244 | ||
3245 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); | |
3246 | if (&obj->base == NULL) { | |
3247 | ret = -ENOENT; | |
3248 | goto unlock; | |
3249 | } | |
3250 | ||
199adf40 | 3251 | args->caching = obj->cache_level != I915_CACHE_NONE; |
e6994aee CW |
3252 | |
3253 | drm_gem_object_unreference(&obj->base); | |
3254 | unlock: | |
3255 | mutex_unlock(&dev->struct_mutex); | |
3256 | return ret; | |
3257 | } | |
3258 | ||
199adf40 BW |
3259 | int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data, |
3260 | struct drm_file *file) | |
e6994aee | 3261 | { |
199adf40 | 3262 | struct drm_i915_gem_caching *args = data; |
e6994aee CW |
3263 | struct drm_i915_gem_object *obj; |
3264 | enum i915_cache_level level; | |
3265 | int ret; | |
3266 | ||
199adf40 BW |
3267 | switch (args->caching) { |
3268 | case I915_CACHING_NONE: | |
e6994aee CW |
3269 | level = I915_CACHE_NONE; |
3270 | break; | |
199adf40 | 3271 | case I915_CACHING_CACHED: |
e6994aee CW |
3272 | level = I915_CACHE_LLC; |
3273 | break; | |
3274 | default: | |
3275 | return -EINVAL; | |
3276 | } | |
3277 | ||
3bc2913e BW |
3278 | ret = i915_mutex_lock_interruptible(dev); |
3279 | if (ret) | |
3280 | return ret; | |
3281 | ||
e6994aee CW |
3282 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
3283 | if (&obj->base == NULL) { | |
3284 | ret = -ENOENT; | |
3285 | goto unlock; | |
3286 | } | |
3287 | ||
3288 | ret = i915_gem_object_set_cache_level(obj, level); | |
3289 | ||
3290 | drm_gem_object_unreference(&obj->base); | |
3291 | unlock: | |
3292 | mutex_unlock(&dev->struct_mutex); | |
3293 | return ret; | |
3294 | } | |
3295 | ||
b9241ea3 | 3296 | /* |
2da3b9b9 CW |
3297 | * Prepare buffer for display plane (scanout, cursors, etc). |
3298 | * Can be called from an uninterruptible phase (modesetting) and allows | |
3299 | * any flushes to be pipelined (for pageflips). | |
b9241ea3 ZW |
3300 | */ |
3301 | int | |
2da3b9b9 CW |
3302 | i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj, |
3303 | u32 alignment, | |
919926ae | 3304 | struct intel_ring_buffer *pipelined) |
b9241ea3 | 3305 | { |
2da3b9b9 | 3306 | u32 old_read_domains, old_write_domain; |
b9241ea3 ZW |
3307 | int ret; |
3308 | ||
0be73284 | 3309 | if (pipelined != obj->ring) { |
2911a35b BW |
3310 | ret = i915_gem_object_sync(obj, pipelined); |
3311 | if (ret) | |
b9241ea3 ZW |
3312 | return ret; |
3313 | } | |
3314 | ||
a7ef0640 EA |
3315 | /* The display engine is not coherent with the LLC cache on gen6. As |
3316 | * a result, we make sure that the pinning that is about to occur is | |
3317 | * done with uncached PTEs. This is lowest common denominator for all | |
3318 | * chipsets. | |
3319 | * | |
3320 | * However for gen6+, we could do better by using the GFDT bit instead | |
3321 | * of uncaching, which would allow us to flush all the LLC-cached data | |
3322 | * with that bit in the PTE to main memory with just one PIPE_CONTROL. | |
3323 | */ | |
3324 | ret = i915_gem_object_set_cache_level(obj, I915_CACHE_NONE); | |
3325 | if (ret) | |
3326 | return ret; | |
3327 | ||
2da3b9b9 CW |
3328 | /* As the user may map the buffer once pinned in the display plane |
3329 | * (e.g. libkms for the bootup splash), we have to ensure that we | |
3330 | * always use map_and_fenceable for all scanout buffers. | |
3331 | */ | |
86a1ee26 | 3332 | ret = i915_gem_object_pin(obj, alignment, true, false); |
2da3b9b9 CW |
3333 | if (ret) |
3334 | return ret; | |
3335 | ||
b118c1e3 CW |
3336 | i915_gem_object_flush_cpu_write_domain(obj); |
3337 | ||
2da3b9b9 | 3338 | old_write_domain = obj->base.write_domain; |
05394f39 | 3339 | old_read_domains = obj->base.read_domains; |
2da3b9b9 CW |
3340 | |
3341 | /* It should now be out of any other write domains, and we can update | |
3342 | * the domain values for our changes. | |
3343 | */ | |
e5f1d962 | 3344 | obj->base.write_domain = 0; |
05394f39 | 3345 | obj->base.read_domains |= I915_GEM_DOMAIN_GTT; |
b9241ea3 ZW |
3346 | |
3347 | trace_i915_gem_object_change_domain(obj, | |
3348 | old_read_domains, | |
2da3b9b9 | 3349 | old_write_domain); |
b9241ea3 ZW |
3350 | |
3351 | return 0; | |
3352 | } | |
3353 | ||
85345517 | 3354 | int |
a8198eea | 3355 | i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj) |
85345517 | 3356 | { |
88241785 CW |
3357 | int ret; |
3358 | ||
a8198eea | 3359 | if ((obj->base.read_domains & I915_GEM_GPU_DOMAINS) == 0) |
85345517 CW |
3360 | return 0; |
3361 | ||
0201f1ec | 3362 | ret = i915_gem_object_wait_rendering(obj, false); |
c501ae7f CW |
3363 | if (ret) |
3364 | return ret; | |
3365 | ||
a8198eea CW |
3366 | /* Ensure that we invalidate the GPU's caches and TLBs. */ |
3367 | obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS; | |
c501ae7f | 3368 | return 0; |
85345517 CW |
3369 | } |
3370 | ||
e47c68e9 EA |
3371 | /** |
3372 | * Moves a single object to the CPU read, and possibly write domain. | |
3373 | * | |
3374 | * This function returns when the move is complete, including waiting on | |
3375 | * flushes to occur. | |
3376 | */ | |
dabdfe02 | 3377 | int |
919926ae | 3378 | i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write) |
e47c68e9 | 3379 | { |
1c5d22f7 | 3380 | uint32_t old_write_domain, old_read_domains; |
e47c68e9 EA |
3381 | int ret; |
3382 | ||
8d7e3de1 CW |
3383 | if (obj->base.write_domain == I915_GEM_DOMAIN_CPU) |
3384 | return 0; | |
3385 | ||
0201f1ec | 3386 | ret = i915_gem_object_wait_rendering(obj, !write); |
88241785 CW |
3387 | if (ret) |
3388 | return ret; | |
3389 | ||
e47c68e9 | 3390 | i915_gem_object_flush_gtt_write_domain(obj); |
2ef7eeaa | 3391 | |
05394f39 CW |
3392 | old_write_domain = obj->base.write_domain; |
3393 | old_read_domains = obj->base.read_domains; | |
1c5d22f7 | 3394 | |
e47c68e9 | 3395 | /* Flush the CPU cache if it's still invalid. */ |
05394f39 | 3396 | if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) { |
2ef7eeaa | 3397 | i915_gem_clflush_object(obj); |
2ef7eeaa | 3398 | |
05394f39 | 3399 | obj->base.read_domains |= I915_GEM_DOMAIN_CPU; |
2ef7eeaa EA |
3400 | } |
3401 | ||
3402 | /* It should now be out of any other write domains, and we can update | |
3403 | * the domain values for our changes. | |
3404 | */ | |
05394f39 | 3405 | BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) != 0); |
e47c68e9 EA |
3406 | |
3407 | /* If we're writing through the CPU, then the GPU read domains will | |
3408 | * need to be invalidated at next use. | |
3409 | */ | |
3410 | if (write) { | |
05394f39 CW |
3411 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; |
3412 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; | |
e47c68e9 | 3413 | } |
2ef7eeaa | 3414 | |
1c5d22f7 CW |
3415 | trace_i915_gem_object_change_domain(obj, |
3416 | old_read_domains, | |
3417 | old_write_domain); | |
3418 | ||
2ef7eeaa EA |
3419 | return 0; |
3420 | } | |
3421 | ||
673a394b EA |
3422 | /* Throttle our rendering by waiting until the ring has completed our requests |
3423 | * emitted over 20 msec ago. | |
3424 | * | |
b962442e EA |
3425 | * Note that if we were to use the current jiffies each time around the loop, |
3426 | * we wouldn't escape the function with any frames outstanding if the time to | |
3427 | * render a frame was over 20ms. | |
3428 | * | |
673a394b EA |
3429 | * This should get us reasonable parallelism between CPU and GPU but also |
3430 | * relatively low latency when blocking on a particular request to finish. | |
3431 | */ | |
40a5f0de | 3432 | static int |
f787a5f5 | 3433 | i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file) |
40a5f0de | 3434 | { |
f787a5f5 CW |
3435 | struct drm_i915_private *dev_priv = dev->dev_private; |
3436 | struct drm_i915_file_private *file_priv = file->driver_priv; | |
b962442e | 3437 | unsigned long recent_enough = jiffies - msecs_to_jiffies(20); |
f787a5f5 CW |
3438 | struct drm_i915_gem_request *request; |
3439 | struct intel_ring_buffer *ring = NULL; | |
f69061be | 3440 | unsigned reset_counter; |
f787a5f5 CW |
3441 | u32 seqno = 0; |
3442 | int ret; | |
93533c29 | 3443 | |
308887aa DV |
3444 | ret = i915_gem_wait_for_error(&dev_priv->gpu_error); |
3445 | if (ret) | |
3446 | return ret; | |
3447 | ||
3448 | ret = i915_gem_check_wedge(&dev_priv->gpu_error, false); | |
3449 | if (ret) | |
3450 | return ret; | |
e110e8d6 | 3451 | |
1c25595f | 3452 | spin_lock(&file_priv->mm.lock); |
f787a5f5 | 3453 | list_for_each_entry(request, &file_priv->mm.request_list, client_list) { |
b962442e EA |
3454 | if (time_after_eq(request->emitted_jiffies, recent_enough)) |
3455 | break; | |
40a5f0de | 3456 | |
f787a5f5 CW |
3457 | ring = request->ring; |
3458 | seqno = request->seqno; | |
b962442e | 3459 | } |
f69061be | 3460 | reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter); |
1c25595f | 3461 | spin_unlock(&file_priv->mm.lock); |
40a5f0de | 3462 | |
f787a5f5 CW |
3463 | if (seqno == 0) |
3464 | return 0; | |
2bc43b5c | 3465 | |
f69061be | 3466 | ret = __wait_seqno(ring, seqno, reset_counter, true, NULL); |
f787a5f5 CW |
3467 | if (ret == 0) |
3468 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, 0); | |
40a5f0de EA |
3469 | |
3470 | return ret; | |
3471 | } | |
3472 | ||
673a394b | 3473 | int |
05394f39 CW |
3474 | i915_gem_object_pin(struct drm_i915_gem_object *obj, |
3475 | uint32_t alignment, | |
86a1ee26 CW |
3476 | bool map_and_fenceable, |
3477 | bool nonblocking) | |
673a394b | 3478 | { |
673a394b EA |
3479 | int ret; |
3480 | ||
7e81a42e CW |
3481 | if (WARN_ON(obj->pin_count == DRM_I915_GEM_OBJECT_MAX_PIN_COUNT)) |
3482 | return -EBUSY; | |
ac0c6b5a | 3483 | |
05394f39 CW |
3484 | if (obj->gtt_space != NULL) { |
3485 | if ((alignment && obj->gtt_offset & (alignment - 1)) || | |
3486 | (map_and_fenceable && !obj->map_and_fenceable)) { | |
3487 | WARN(obj->pin_count, | |
ae7d49d8 | 3488 | "bo is already pinned with incorrect alignment:" |
75e9e915 DV |
3489 | " offset=%x, req.alignment=%x, req.map_and_fenceable=%d," |
3490 | " obj->map_and_fenceable=%d\n", | |
05394f39 | 3491 | obj->gtt_offset, alignment, |
75e9e915 | 3492 | map_and_fenceable, |
05394f39 | 3493 | obj->map_and_fenceable); |
ac0c6b5a CW |
3494 | ret = i915_gem_object_unbind(obj); |
3495 | if (ret) | |
3496 | return ret; | |
3497 | } | |
3498 | } | |
3499 | ||
05394f39 | 3500 | if (obj->gtt_space == NULL) { |
8742267a CW |
3501 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
3502 | ||
a00b10c3 | 3503 | ret = i915_gem_object_bind_to_gtt(obj, alignment, |
86a1ee26 CW |
3504 | map_and_fenceable, |
3505 | nonblocking); | |
9731129c | 3506 | if (ret) |
673a394b | 3507 | return ret; |
8742267a CW |
3508 | |
3509 | if (!dev_priv->mm.aliasing_ppgtt) | |
3510 | i915_gem_gtt_bind_object(obj, obj->cache_level); | |
22c344e9 | 3511 | } |
76446cac | 3512 | |
74898d7e DV |
3513 | if (!obj->has_global_gtt_mapping && map_and_fenceable) |
3514 | i915_gem_gtt_bind_object(obj, obj->cache_level); | |
3515 | ||
1b50247a | 3516 | obj->pin_count++; |
6299f992 | 3517 | obj->pin_mappable |= map_and_fenceable; |
673a394b EA |
3518 | |
3519 | return 0; | |
3520 | } | |
3521 | ||
3522 | void | |
05394f39 | 3523 | i915_gem_object_unpin(struct drm_i915_gem_object *obj) |
673a394b | 3524 | { |
05394f39 CW |
3525 | BUG_ON(obj->pin_count == 0); |
3526 | BUG_ON(obj->gtt_space == NULL); | |
673a394b | 3527 | |
1b50247a | 3528 | if (--obj->pin_count == 0) |
6299f992 | 3529 | obj->pin_mappable = false; |
673a394b EA |
3530 | } |
3531 | ||
3532 | int | |
3533 | i915_gem_pin_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 3534 | struct drm_file *file) |
673a394b EA |
3535 | { |
3536 | struct drm_i915_gem_pin *args = data; | |
05394f39 | 3537 | struct drm_i915_gem_object *obj; |
673a394b EA |
3538 | int ret; |
3539 | ||
1d7cfea1 CW |
3540 | ret = i915_mutex_lock_interruptible(dev); |
3541 | if (ret) | |
3542 | return ret; | |
673a394b | 3543 | |
05394f39 | 3544 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 3545 | if (&obj->base == NULL) { |
1d7cfea1 CW |
3546 | ret = -ENOENT; |
3547 | goto unlock; | |
673a394b | 3548 | } |
673a394b | 3549 | |
05394f39 | 3550 | if (obj->madv != I915_MADV_WILLNEED) { |
bb6baf76 | 3551 | DRM_ERROR("Attempting to pin a purgeable buffer\n"); |
1d7cfea1 CW |
3552 | ret = -EINVAL; |
3553 | goto out; | |
3ef94daa CW |
3554 | } |
3555 | ||
05394f39 | 3556 | if (obj->pin_filp != NULL && obj->pin_filp != file) { |
79e53945 JB |
3557 | DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n", |
3558 | args->handle); | |
1d7cfea1 CW |
3559 | ret = -EINVAL; |
3560 | goto out; | |
79e53945 JB |
3561 | } |
3562 | ||
93be8788 | 3563 | if (obj->user_pin_count == 0) { |
86a1ee26 | 3564 | ret = i915_gem_object_pin(obj, args->alignment, true, false); |
1d7cfea1 CW |
3565 | if (ret) |
3566 | goto out; | |
673a394b EA |
3567 | } |
3568 | ||
93be8788 CW |
3569 | obj->user_pin_count++; |
3570 | obj->pin_filp = file; | |
3571 | ||
673a394b EA |
3572 | /* XXX - flush the CPU caches for pinned objects |
3573 | * as the X server doesn't manage domains yet | |
3574 | */ | |
e47c68e9 | 3575 | i915_gem_object_flush_cpu_write_domain(obj); |
05394f39 | 3576 | args->offset = obj->gtt_offset; |
1d7cfea1 | 3577 | out: |
05394f39 | 3578 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 3579 | unlock: |
673a394b | 3580 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 3581 | return ret; |
673a394b EA |
3582 | } |
3583 | ||
3584 | int | |
3585 | i915_gem_unpin_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 3586 | struct drm_file *file) |
673a394b EA |
3587 | { |
3588 | struct drm_i915_gem_pin *args = data; | |
05394f39 | 3589 | struct drm_i915_gem_object *obj; |
76c1dec1 | 3590 | int ret; |
673a394b | 3591 | |
1d7cfea1 CW |
3592 | ret = i915_mutex_lock_interruptible(dev); |
3593 | if (ret) | |
3594 | return ret; | |
673a394b | 3595 | |
05394f39 | 3596 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 3597 | if (&obj->base == NULL) { |
1d7cfea1 CW |
3598 | ret = -ENOENT; |
3599 | goto unlock; | |
673a394b | 3600 | } |
76c1dec1 | 3601 | |
05394f39 | 3602 | if (obj->pin_filp != file) { |
79e53945 JB |
3603 | DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n", |
3604 | args->handle); | |
1d7cfea1 CW |
3605 | ret = -EINVAL; |
3606 | goto out; | |
79e53945 | 3607 | } |
05394f39 CW |
3608 | obj->user_pin_count--; |
3609 | if (obj->user_pin_count == 0) { | |
3610 | obj->pin_filp = NULL; | |
79e53945 JB |
3611 | i915_gem_object_unpin(obj); |
3612 | } | |
673a394b | 3613 | |
1d7cfea1 | 3614 | out: |
05394f39 | 3615 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 3616 | unlock: |
673a394b | 3617 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 3618 | return ret; |
673a394b EA |
3619 | } |
3620 | ||
3621 | int | |
3622 | i915_gem_busy_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 3623 | struct drm_file *file) |
673a394b EA |
3624 | { |
3625 | struct drm_i915_gem_busy *args = data; | |
05394f39 | 3626 | struct drm_i915_gem_object *obj; |
30dbf0c0 CW |
3627 | int ret; |
3628 | ||
76c1dec1 | 3629 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 3630 | if (ret) |
76c1dec1 | 3631 | return ret; |
673a394b | 3632 | |
05394f39 | 3633 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 3634 | if (&obj->base == NULL) { |
1d7cfea1 CW |
3635 | ret = -ENOENT; |
3636 | goto unlock; | |
673a394b | 3637 | } |
d1b851fc | 3638 | |
0be555b6 CW |
3639 | /* Count all active objects as busy, even if they are currently not used |
3640 | * by the gpu. Users of this interface expect objects to eventually | |
3641 | * become non-busy without any further actions, therefore emit any | |
3642 | * necessary flushes here. | |
c4de0a5d | 3643 | */ |
30dfebf3 | 3644 | ret = i915_gem_object_flush_active(obj); |
0be555b6 | 3645 | |
30dfebf3 | 3646 | args->busy = obj->active; |
e9808edd CW |
3647 | if (obj->ring) { |
3648 | BUILD_BUG_ON(I915_NUM_RINGS > 16); | |
3649 | args->busy |= intel_ring_flag(obj->ring) << 16; | |
3650 | } | |
673a394b | 3651 | |
05394f39 | 3652 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 3653 | unlock: |
673a394b | 3654 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 3655 | return ret; |
673a394b EA |
3656 | } |
3657 | ||
3658 | int | |
3659 | i915_gem_throttle_ioctl(struct drm_device *dev, void *data, | |
3660 | struct drm_file *file_priv) | |
3661 | { | |
0206e353 | 3662 | return i915_gem_ring_throttle(dev, file_priv); |
673a394b EA |
3663 | } |
3664 | ||
3ef94daa CW |
3665 | int |
3666 | i915_gem_madvise_ioctl(struct drm_device *dev, void *data, | |
3667 | struct drm_file *file_priv) | |
3668 | { | |
3669 | struct drm_i915_gem_madvise *args = data; | |
05394f39 | 3670 | struct drm_i915_gem_object *obj; |
76c1dec1 | 3671 | int ret; |
3ef94daa CW |
3672 | |
3673 | switch (args->madv) { | |
3674 | case I915_MADV_DONTNEED: | |
3675 | case I915_MADV_WILLNEED: | |
3676 | break; | |
3677 | default: | |
3678 | return -EINVAL; | |
3679 | } | |
3680 | ||
1d7cfea1 CW |
3681 | ret = i915_mutex_lock_interruptible(dev); |
3682 | if (ret) | |
3683 | return ret; | |
3684 | ||
05394f39 | 3685 | obj = to_intel_bo(drm_gem_object_lookup(dev, file_priv, args->handle)); |
c8725226 | 3686 | if (&obj->base == NULL) { |
1d7cfea1 CW |
3687 | ret = -ENOENT; |
3688 | goto unlock; | |
3ef94daa | 3689 | } |
3ef94daa | 3690 | |
05394f39 | 3691 | if (obj->pin_count) { |
1d7cfea1 CW |
3692 | ret = -EINVAL; |
3693 | goto out; | |
3ef94daa CW |
3694 | } |
3695 | ||
05394f39 CW |
3696 | if (obj->madv != __I915_MADV_PURGED) |
3697 | obj->madv = args->madv; | |
3ef94daa | 3698 | |
6c085a72 CW |
3699 | /* if the object is no longer attached, discard its backing storage */ |
3700 | if (i915_gem_object_is_purgeable(obj) && obj->pages == NULL) | |
2d7ef395 CW |
3701 | i915_gem_object_truncate(obj); |
3702 | ||
05394f39 | 3703 | args->retained = obj->madv != __I915_MADV_PURGED; |
bb6baf76 | 3704 | |
1d7cfea1 | 3705 | out: |
05394f39 | 3706 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 3707 | unlock: |
3ef94daa | 3708 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 3709 | return ret; |
3ef94daa CW |
3710 | } |
3711 | ||
37e680a1 CW |
3712 | void i915_gem_object_init(struct drm_i915_gem_object *obj, |
3713 | const struct drm_i915_gem_object_ops *ops) | |
0327d6ba | 3714 | { |
0327d6ba CW |
3715 | INIT_LIST_HEAD(&obj->mm_list); |
3716 | INIT_LIST_HEAD(&obj->gtt_list); | |
3717 | INIT_LIST_HEAD(&obj->ring_list); | |
3718 | INIT_LIST_HEAD(&obj->exec_list); | |
3719 | ||
37e680a1 CW |
3720 | obj->ops = ops; |
3721 | ||
0327d6ba CW |
3722 | obj->fence_reg = I915_FENCE_REG_NONE; |
3723 | obj->madv = I915_MADV_WILLNEED; | |
3724 | /* Avoid an unnecessary call to unbind on the first bind. */ | |
3725 | obj->map_and_fenceable = true; | |
3726 | ||
3727 | i915_gem_info_add_obj(obj->base.dev->dev_private, obj->base.size); | |
3728 | } | |
3729 | ||
37e680a1 CW |
3730 | static const struct drm_i915_gem_object_ops i915_gem_object_ops = { |
3731 | .get_pages = i915_gem_object_get_pages_gtt, | |
3732 | .put_pages = i915_gem_object_put_pages_gtt, | |
3733 | }; | |
3734 | ||
05394f39 CW |
3735 | struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev, |
3736 | size_t size) | |
ac52bc56 | 3737 | { |
c397b908 | 3738 | struct drm_i915_gem_object *obj; |
5949eac4 | 3739 | struct address_space *mapping; |
1a240d4d | 3740 | gfp_t mask; |
ac52bc56 | 3741 | |
42dcedd4 | 3742 | obj = i915_gem_object_alloc(dev); |
c397b908 DV |
3743 | if (obj == NULL) |
3744 | return NULL; | |
673a394b | 3745 | |
c397b908 | 3746 | if (drm_gem_object_init(dev, &obj->base, size) != 0) { |
42dcedd4 | 3747 | i915_gem_object_free(obj); |
c397b908 DV |
3748 | return NULL; |
3749 | } | |
673a394b | 3750 | |
bed1ea95 CW |
3751 | mask = GFP_HIGHUSER | __GFP_RECLAIMABLE; |
3752 | if (IS_CRESTLINE(dev) || IS_BROADWATER(dev)) { | |
3753 | /* 965gm cannot relocate objects above 4GiB. */ | |
3754 | mask &= ~__GFP_HIGHMEM; | |
3755 | mask |= __GFP_DMA32; | |
3756 | } | |
3757 | ||
496ad9aa | 3758 | mapping = file_inode(obj->base.filp)->i_mapping; |
bed1ea95 | 3759 | mapping_set_gfp_mask(mapping, mask); |
5949eac4 | 3760 | |
37e680a1 | 3761 | i915_gem_object_init(obj, &i915_gem_object_ops); |
73aa808f | 3762 | |
c397b908 DV |
3763 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; |
3764 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; | |
673a394b | 3765 | |
3d29b842 ED |
3766 | if (HAS_LLC(dev)) { |
3767 | /* On some devices, we can have the GPU use the LLC (the CPU | |
a1871112 EA |
3768 | * cache) for about a 10% performance improvement |
3769 | * compared to uncached. Graphics requests other than | |
3770 | * display scanout are coherent with the CPU in | |
3771 | * accessing this cache. This means in this mode we | |
3772 | * don't need to clflush on the CPU side, and on the | |
3773 | * GPU side we only need to flush internal caches to | |
3774 | * get data visible to the CPU. | |
3775 | * | |
3776 | * However, we maintain the display planes as UC, and so | |
3777 | * need to rebind when first used as such. | |
3778 | */ | |
3779 | obj->cache_level = I915_CACHE_LLC; | |
3780 | } else | |
3781 | obj->cache_level = I915_CACHE_NONE; | |
3782 | ||
05394f39 | 3783 | return obj; |
c397b908 DV |
3784 | } |
3785 | ||
3786 | int i915_gem_init_object(struct drm_gem_object *obj) | |
3787 | { | |
3788 | BUG(); | |
de151cf6 | 3789 | |
673a394b EA |
3790 | return 0; |
3791 | } | |
3792 | ||
1488fc08 | 3793 | void i915_gem_free_object(struct drm_gem_object *gem_obj) |
673a394b | 3794 | { |
1488fc08 | 3795 | struct drm_i915_gem_object *obj = to_intel_bo(gem_obj); |
05394f39 | 3796 | struct drm_device *dev = obj->base.dev; |
be72615b | 3797 | drm_i915_private_t *dev_priv = dev->dev_private; |
673a394b | 3798 | |
26e12f89 CW |
3799 | trace_i915_gem_object_destroy(obj); |
3800 | ||
1488fc08 CW |
3801 | if (obj->phys_obj) |
3802 | i915_gem_detach_phys_object(dev, obj); | |
3803 | ||
3804 | obj->pin_count = 0; | |
3805 | if (WARN_ON(i915_gem_object_unbind(obj) == -ERESTARTSYS)) { | |
3806 | bool was_interruptible; | |
3807 | ||
3808 | was_interruptible = dev_priv->mm.interruptible; | |
3809 | dev_priv->mm.interruptible = false; | |
3810 | ||
3811 | WARN_ON(i915_gem_object_unbind(obj)); | |
3812 | ||
3813 | dev_priv->mm.interruptible = was_interruptible; | |
3814 | } | |
3815 | ||
a5570178 | 3816 | obj->pages_pin_count = 0; |
37e680a1 | 3817 | i915_gem_object_put_pages(obj); |
d8cb5086 | 3818 | i915_gem_object_free_mmap_offset(obj); |
0104fdbb | 3819 | i915_gem_object_release_stolen(obj); |
de151cf6 | 3820 | |
9da3da66 CW |
3821 | BUG_ON(obj->pages); |
3822 | ||
2f745ad3 CW |
3823 | if (obj->base.import_attach) |
3824 | drm_prime_gem_destroy(&obj->base, NULL); | |
de151cf6 | 3825 | |
05394f39 CW |
3826 | drm_gem_object_release(&obj->base); |
3827 | i915_gem_info_remove_obj(dev_priv, obj->base.size); | |
c397b908 | 3828 | |
05394f39 | 3829 | kfree(obj->bit_17); |
42dcedd4 | 3830 | i915_gem_object_free(obj); |
673a394b EA |
3831 | } |
3832 | ||
29105ccc CW |
3833 | int |
3834 | i915_gem_idle(struct drm_device *dev) | |
3835 | { | |
3836 | drm_i915_private_t *dev_priv = dev->dev_private; | |
3837 | int ret; | |
28dfe52a | 3838 | |
29105ccc | 3839 | mutex_lock(&dev->struct_mutex); |
1c5d22f7 | 3840 | |
87acb0a5 | 3841 | if (dev_priv->mm.suspended) { |
29105ccc CW |
3842 | mutex_unlock(&dev->struct_mutex); |
3843 | return 0; | |
28dfe52a EA |
3844 | } |
3845 | ||
b2da9fe5 | 3846 | ret = i915_gpu_idle(dev); |
6dbe2772 KP |
3847 | if (ret) { |
3848 | mutex_unlock(&dev->struct_mutex); | |
673a394b | 3849 | return ret; |
6dbe2772 | 3850 | } |
b2da9fe5 | 3851 | i915_gem_retire_requests(dev); |
673a394b | 3852 | |
29105ccc | 3853 | /* Under UMS, be paranoid and evict. */ |
a39d7efc | 3854 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) |
6c085a72 | 3855 | i915_gem_evict_everything(dev); |
29105ccc CW |
3856 | |
3857 | /* Hack! Don't let anybody do execbuf while we don't control the chip. | |
3858 | * We need to replace this with a semaphore, or something. | |
3859 | * And not confound mm.suspended! | |
3860 | */ | |
3861 | dev_priv->mm.suspended = 1; | |
99584db3 | 3862 | del_timer_sync(&dev_priv->gpu_error.hangcheck_timer); |
29105ccc CW |
3863 | |
3864 | i915_kernel_lost_context(dev); | |
6dbe2772 | 3865 | i915_gem_cleanup_ringbuffer(dev); |
29105ccc | 3866 | |
6dbe2772 KP |
3867 | mutex_unlock(&dev->struct_mutex); |
3868 | ||
29105ccc CW |
3869 | /* Cancel the retire work handler, which should be idle now. */ |
3870 | cancel_delayed_work_sync(&dev_priv->mm.retire_work); | |
3871 | ||
673a394b EA |
3872 | return 0; |
3873 | } | |
3874 | ||
b9524a1e BW |
3875 | void i915_gem_l3_remap(struct drm_device *dev) |
3876 | { | |
3877 | drm_i915_private_t *dev_priv = dev->dev_private; | |
3878 | u32 misccpctl; | |
3879 | int i; | |
3880 | ||
eb32e458 | 3881 | if (!HAS_L3_GPU_CACHE(dev)) |
b9524a1e BW |
3882 | return; |
3883 | ||
a4da4fa4 | 3884 | if (!dev_priv->l3_parity.remap_info) |
b9524a1e BW |
3885 | return; |
3886 | ||
3887 | misccpctl = I915_READ(GEN7_MISCCPCTL); | |
3888 | I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE); | |
3889 | POSTING_READ(GEN7_MISCCPCTL); | |
3890 | ||
3891 | for (i = 0; i < GEN7_L3LOG_SIZE; i += 4) { | |
3892 | u32 remap = I915_READ(GEN7_L3LOG_BASE + i); | |
a4da4fa4 | 3893 | if (remap && remap != dev_priv->l3_parity.remap_info[i/4]) |
b9524a1e BW |
3894 | DRM_DEBUG("0x%x was already programmed to %x\n", |
3895 | GEN7_L3LOG_BASE + i, remap); | |
a4da4fa4 | 3896 | if (remap && !dev_priv->l3_parity.remap_info[i/4]) |
b9524a1e | 3897 | DRM_DEBUG_DRIVER("Clearing remapped register\n"); |
a4da4fa4 | 3898 | I915_WRITE(GEN7_L3LOG_BASE + i, dev_priv->l3_parity.remap_info[i/4]); |
b9524a1e BW |
3899 | } |
3900 | ||
3901 | /* Make sure all the writes land before disabling dop clock gating */ | |
3902 | POSTING_READ(GEN7_L3LOG_BASE); | |
3903 | ||
3904 | I915_WRITE(GEN7_MISCCPCTL, misccpctl); | |
3905 | } | |
3906 | ||
f691e2f4 DV |
3907 | void i915_gem_init_swizzling(struct drm_device *dev) |
3908 | { | |
3909 | drm_i915_private_t *dev_priv = dev->dev_private; | |
3910 | ||
11782b02 | 3911 | if (INTEL_INFO(dev)->gen < 5 || |
f691e2f4 DV |
3912 | dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE) |
3913 | return; | |
3914 | ||
3915 | I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) | | |
3916 | DISP_TILE_SURFACE_SWIZZLING); | |
3917 | ||
11782b02 DV |
3918 | if (IS_GEN5(dev)) |
3919 | return; | |
3920 | ||
f691e2f4 DV |
3921 | I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_SWZCTL); |
3922 | if (IS_GEN6(dev)) | |
6b26c86d | 3923 | I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB)); |
8782e26c | 3924 | else if (IS_GEN7(dev)) |
6b26c86d | 3925 | I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB)); |
8782e26c BW |
3926 | else |
3927 | BUG(); | |
f691e2f4 | 3928 | } |
e21af88d | 3929 | |
67b1b571 CW |
3930 | static bool |
3931 | intel_enable_blt(struct drm_device *dev) | |
3932 | { | |
3933 | if (!HAS_BLT(dev)) | |
3934 | return false; | |
3935 | ||
3936 | /* The blitter was dysfunctional on early prototypes */ | |
3937 | if (IS_GEN6(dev) && dev->pdev->revision < 8) { | |
3938 | DRM_INFO("BLT not supported on this pre-production hardware;" | |
3939 | " graphics performance will be degraded.\n"); | |
3940 | return false; | |
3941 | } | |
3942 | ||
3943 | return true; | |
3944 | } | |
3945 | ||
4fc7c971 | 3946 | static int i915_gem_init_rings(struct drm_device *dev) |
8187a2b7 | 3947 | { |
4fc7c971 | 3948 | struct drm_i915_private *dev_priv = dev->dev_private; |
8187a2b7 | 3949 | int ret; |
68f95ba9 | 3950 | |
5c1143bb | 3951 | ret = intel_init_render_ring_buffer(dev); |
68f95ba9 | 3952 | if (ret) |
b6913e4b | 3953 | return ret; |
68f95ba9 CW |
3954 | |
3955 | if (HAS_BSD(dev)) { | |
5c1143bb | 3956 | ret = intel_init_bsd_ring_buffer(dev); |
68f95ba9 CW |
3957 | if (ret) |
3958 | goto cleanup_render_ring; | |
d1b851fc | 3959 | } |
68f95ba9 | 3960 | |
67b1b571 | 3961 | if (intel_enable_blt(dev)) { |
549f7365 CW |
3962 | ret = intel_init_blt_ring_buffer(dev); |
3963 | if (ret) | |
3964 | goto cleanup_bsd_ring; | |
3965 | } | |
3966 | ||
99433931 | 3967 | ret = i915_gem_set_seqno(dev, ((u32)~0 - 0x1000)); |
4fc7c971 BW |
3968 | if (ret) |
3969 | goto cleanup_blt_ring; | |
3970 | ||
3971 | return 0; | |
3972 | ||
3973 | cleanup_blt_ring: | |
3974 | intel_cleanup_ring_buffer(&dev_priv->ring[BCS]); | |
3975 | cleanup_bsd_ring: | |
3976 | intel_cleanup_ring_buffer(&dev_priv->ring[VCS]); | |
3977 | cleanup_render_ring: | |
3978 | intel_cleanup_ring_buffer(&dev_priv->ring[RCS]); | |
3979 | ||
3980 | return ret; | |
3981 | } | |
3982 | ||
3983 | int | |
3984 | i915_gem_init_hw(struct drm_device *dev) | |
3985 | { | |
3986 | drm_i915_private_t *dev_priv = dev->dev_private; | |
3987 | int ret; | |
3988 | ||
3989 | if (INTEL_INFO(dev)->gen < 6 && !intel_enable_gtt()) | |
3990 | return -EIO; | |
3991 | ||
3992 | if (IS_HASWELL(dev) && (I915_READ(0x120010) == 1)) | |
3993 | I915_WRITE(0x9008, I915_READ(0x9008) | 0xf0000); | |
3994 | ||
88a2b2a3 BW |
3995 | if (HAS_PCH_NOP(dev)) { |
3996 | u32 temp = I915_READ(GEN7_MSG_CTL); | |
3997 | temp &= ~(WAIT_FOR_PCH_FLR_ACK | WAIT_FOR_PCH_RESET_ACK); | |
3998 | I915_WRITE(GEN7_MSG_CTL, temp); | |
3999 | } | |
4000 | ||
4fc7c971 BW |
4001 | i915_gem_l3_remap(dev); |
4002 | ||
4003 | i915_gem_init_swizzling(dev); | |
4004 | ||
4005 | ret = i915_gem_init_rings(dev); | |
99433931 MK |
4006 | if (ret) |
4007 | return ret; | |
4008 | ||
254f965c BW |
4009 | /* |
4010 | * XXX: There was some w/a described somewhere suggesting loading | |
4011 | * contexts before PPGTT. | |
4012 | */ | |
4013 | i915_gem_context_init(dev); | |
b7c36d25 BW |
4014 | if (dev_priv->mm.aliasing_ppgtt) { |
4015 | ret = dev_priv->mm.aliasing_ppgtt->enable(dev); | |
4016 | if (ret) { | |
4017 | i915_gem_cleanup_aliasing_ppgtt(dev); | |
4018 | DRM_INFO("PPGTT enable failed. This is not fatal, but unexpected\n"); | |
4019 | } | |
4020 | } | |
e21af88d | 4021 | |
68f95ba9 | 4022 | return 0; |
8187a2b7 ZN |
4023 | } |
4024 | ||
1070a42b CW |
4025 | int i915_gem_init(struct drm_device *dev) |
4026 | { | |
4027 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1070a42b CW |
4028 | int ret; |
4029 | ||
1070a42b | 4030 | mutex_lock(&dev->struct_mutex); |
d62b4892 JB |
4031 | |
4032 | if (IS_VALLEYVIEW(dev)) { | |
4033 | /* VLVA0 (potential hack), BIOS isn't actually waking us */ | |
4034 | I915_WRITE(VLV_GTLC_WAKE_CTRL, 1); | |
4035 | if (wait_for((I915_READ(VLV_GTLC_PW_STATUS) & 1) == 1, 10)) | |
4036 | DRM_DEBUG_DRIVER("allow wake ack timed out\n"); | |
4037 | } | |
4038 | ||
d7e5008f | 4039 | i915_gem_init_global_gtt(dev); |
d62b4892 | 4040 | |
1070a42b CW |
4041 | ret = i915_gem_init_hw(dev); |
4042 | mutex_unlock(&dev->struct_mutex); | |
4043 | if (ret) { | |
4044 | i915_gem_cleanup_aliasing_ppgtt(dev); | |
4045 | return ret; | |
4046 | } | |
4047 | ||
53ca26ca DV |
4048 | /* Allow hardware batchbuffers unless told otherwise, but not for KMS. */ |
4049 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) | |
4050 | dev_priv->dri1.allow_batchbuffer = 1; | |
1070a42b CW |
4051 | return 0; |
4052 | } | |
4053 | ||
8187a2b7 ZN |
4054 | void |
4055 | i915_gem_cleanup_ringbuffer(struct drm_device *dev) | |
4056 | { | |
4057 | drm_i915_private_t *dev_priv = dev->dev_private; | |
b4519513 | 4058 | struct intel_ring_buffer *ring; |
1ec14ad3 | 4059 | int i; |
8187a2b7 | 4060 | |
b4519513 CW |
4061 | for_each_ring(ring, dev_priv, i) |
4062 | intel_cleanup_ring_buffer(ring); | |
8187a2b7 ZN |
4063 | } |
4064 | ||
673a394b EA |
4065 | int |
4066 | i915_gem_entervt_ioctl(struct drm_device *dev, void *data, | |
4067 | struct drm_file *file_priv) | |
4068 | { | |
4069 | drm_i915_private_t *dev_priv = dev->dev_private; | |
b4519513 | 4070 | int ret; |
673a394b | 4071 | |
79e53945 JB |
4072 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
4073 | return 0; | |
4074 | ||
1f83fee0 | 4075 | if (i915_reset_in_progress(&dev_priv->gpu_error)) { |
673a394b | 4076 | DRM_ERROR("Reenabling wedged hardware, good luck\n"); |
1f83fee0 | 4077 | atomic_set(&dev_priv->gpu_error.reset_counter, 0); |
673a394b EA |
4078 | } |
4079 | ||
673a394b | 4080 | mutex_lock(&dev->struct_mutex); |
9bb2d6f9 EA |
4081 | dev_priv->mm.suspended = 0; |
4082 | ||
f691e2f4 | 4083 | ret = i915_gem_init_hw(dev); |
d816f6ac WF |
4084 | if (ret != 0) { |
4085 | mutex_unlock(&dev->struct_mutex); | |
9bb2d6f9 | 4086 | return ret; |
d816f6ac | 4087 | } |
9bb2d6f9 | 4088 | |
69dc4987 | 4089 | BUG_ON(!list_empty(&dev_priv->mm.active_list)); |
673a394b | 4090 | mutex_unlock(&dev->struct_mutex); |
dbb19d30 | 4091 | |
5f35308b CW |
4092 | ret = drm_irq_install(dev); |
4093 | if (ret) | |
4094 | goto cleanup_ringbuffer; | |
dbb19d30 | 4095 | |
673a394b | 4096 | return 0; |
5f35308b CW |
4097 | |
4098 | cleanup_ringbuffer: | |
4099 | mutex_lock(&dev->struct_mutex); | |
4100 | i915_gem_cleanup_ringbuffer(dev); | |
4101 | dev_priv->mm.suspended = 1; | |
4102 | mutex_unlock(&dev->struct_mutex); | |
4103 | ||
4104 | return ret; | |
673a394b EA |
4105 | } |
4106 | ||
4107 | int | |
4108 | i915_gem_leavevt_ioctl(struct drm_device *dev, void *data, | |
4109 | struct drm_file *file_priv) | |
4110 | { | |
79e53945 JB |
4111 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
4112 | return 0; | |
4113 | ||
dbb19d30 | 4114 | drm_irq_uninstall(dev); |
e6890f6f | 4115 | return i915_gem_idle(dev); |
673a394b EA |
4116 | } |
4117 | ||
4118 | void | |
4119 | i915_gem_lastclose(struct drm_device *dev) | |
4120 | { | |
4121 | int ret; | |
673a394b | 4122 | |
e806b495 EA |
4123 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
4124 | return; | |
4125 | ||
6dbe2772 KP |
4126 | ret = i915_gem_idle(dev); |
4127 | if (ret) | |
4128 | DRM_ERROR("failed to idle hardware: %d\n", ret); | |
673a394b EA |
4129 | } |
4130 | ||
64193406 CW |
4131 | static void |
4132 | init_ring_lists(struct intel_ring_buffer *ring) | |
4133 | { | |
4134 | INIT_LIST_HEAD(&ring->active_list); | |
4135 | INIT_LIST_HEAD(&ring->request_list); | |
64193406 CW |
4136 | } |
4137 | ||
673a394b EA |
4138 | void |
4139 | i915_gem_load(struct drm_device *dev) | |
4140 | { | |
4141 | drm_i915_private_t *dev_priv = dev->dev_private; | |
42dcedd4 CW |
4142 | int i; |
4143 | ||
4144 | dev_priv->slab = | |
4145 | kmem_cache_create("i915_gem_object", | |
4146 | sizeof(struct drm_i915_gem_object), 0, | |
4147 | SLAB_HWCACHE_ALIGN, | |
4148 | NULL); | |
673a394b | 4149 | |
69dc4987 | 4150 | INIT_LIST_HEAD(&dev_priv->mm.active_list); |
673a394b | 4151 | INIT_LIST_HEAD(&dev_priv->mm.inactive_list); |
6c085a72 CW |
4152 | INIT_LIST_HEAD(&dev_priv->mm.unbound_list); |
4153 | INIT_LIST_HEAD(&dev_priv->mm.bound_list); | |
a09ba7fa | 4154 | INIT_LIST_HEAD(&dev_priv->mm.fence_list); |
1ec14ad3 CW |
4155 | for (i = 0; i < I915_NUM_RINGS; i++) |
4156 | init_ring_lists(&dev_priv->ring[i]); | |
4b9de737 | 4157 | for (i = 0; i < I915_MAX_NUM_FENCES; i++) |
007cc8ac | 4158 | INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list); |
673a394b EA |
4159 | INIT_DELAYED_WORK(&dev_priv->mm.retire_work, |
4160 | i915_gem_retire_work_handler); | |
1f83fee0 | 4161 | init_waitqueue_head(&dev_priv->gpu_error.reset_queue); |
31169714 | 4162 | |
94400120 DA |
4163 | /* On GEN3 we really need to make sure the ARB C3 LP bit is set */ |
4164 | if (IS_GEN3(dev)) { | |
50743298 DV |
4165 | I915_WRITE(MI_ARB_STATE, |
4166 | _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE)); | |
94400120 DA |
4167 | } |
4168 | ||
72bfa19c CW |
4169 | dev_priv->relative_constants_mode = I915_EXEC_CONSTANTS_REL_GENERAL; |
4170 | ||
de151cf6 | 4171 | /* Old X drivers will take 0-2 for front, back, depth buffers */ |
b397c836 EA |
4172 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) |
4173 | dev_priv->fence_reg_start = 3; | |
de151cf6 | 4174 | |
42b5aeab VS |
4175 | if (INTEL_INFO(dev)->gen >= 7 && !IS_VALLEYVIEW(dev)) |
4176 | dev_priv->num_fence_regs = 32; | |
4177 | else if (INTEL_INFO(dev)->gen >= 4 || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) | |
de151cf6 JB |
4178 | dev_priv->num_fence_regs = 16; |
4179 | else | |
4180 | dev_priv->num_fence_regs = 8; | |
4181 | ||
b5aa8a0f | 4182 | /* Initialize fence registers to zero */ |
19b2dbde CW |
4183 | INIT_LIST_HEAD(&dev_priv->mm.fence_list); |
4184 | i915_gem_restore_fences(dev); | |
10ed13e4 | 4185 | |
673a394b | 4186 | i915_gem_detect_bit_6_swizzle(dev); |
6b95a207 | 4187 | init_waitqueue_head(&dev_priv->pending_flip_queue); |
17250b71 | 4188 | |
ce453d81 CW |
4189 | dev_priv->mm.interruptible = true; |
4190 | ||
17250b71 CW |
4191 | dev_priv->mm.inactive_shrinker.shrink = i915_gem_inactive_shrink; |
4192 | dev_priv->mm.inactive_shrinker.seeks = DEFAULT_SEEKS; | |
4193 | register_shrinker(&dev_priv->mm.inactive_shrinker); | |
673a394b | 4194 | } |
71acb5eb DA |
4195 | |
4196 | /* | |
4197 | * Create a physically contiguous memory object for this object | |
4198 | * e.g. for cursor + overlay regs | |
4199 | */ | |
995b6762 CW |
4200 | static int i915_gem_init_phys_object(struct drm_device *dev, |
4201 | int id, int size, int align) | |
71acb5eb DA |
4202 | { |
4203 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4204 | struct drm_i915_gem_phys_object *phys_obj; | |
4205 | int ret; | |
4206 | ||
4207 | if (dev_priv->mm.phys_objs[id - 1] || !size) | |
4208 | return 0; | |
4209 | ||
9a298b2a | 4210 | phys_obj = kzalloc(sizeof(struct drm_i915_gem_phys_object), GFP_KERNEL); |
71acb5eb DA |
4211 | if (!phys_obj) |
4212 | return -ENOMEM; | |
4213 | ||
4214 | phys_obj->id = id; | |
4215 | ||
6eeefaf3 | 4216 | phys_obj->handle = drm_pci_alloc(dev, size, align); |
71acb5eb DA |
4217 | if (!phys_obj->handle) { |
4218 | ret = -ENOMEM; | |
4219 | goto kfree_obj; | |
4220 | } | |
4221 | #ifdef CONFIG_X86 | |
4222 | set_memory_wc((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE); | |
4223 | #endif | |
4224 | ||
4225 | dev_priv->mm.phys_objs[id - 1] = phys_obj; | |
4226 | ||
4227 | return 0; | |
4228 | kfree_obj: | |
9a298b2a | 4229 | kfree(phys_obj); |
71acb5eb DA |
4230 | return ret; |
4231 | } | |
4232 | ||
995b6762 | 4233 | static void i915_gem_free_phys_object(struct drm_device *dev, int id) |
71acb5eb DA |
4234 | { |
4235 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4236 | struct drm_i915_gem_phys_object *phys_obj; | |
4237 | ||
4238 | if (!dev_priv->mm.phys_objs[id - 1]) | |
4239 | return; | |
4240 | ||
4241 | phys_obj = dev_priv->mm.phys_objs[id - 1]; | |
4242 | if (phys_obj->cur_obj) { | |
4243 | i915_gem_detach_phys_object(dev, phys_obj->cur_obj); | |
4244 | } | |
4245 | ||
4246 | #ifdef CONFIG_X86 | |
4247 | set_memory_wb((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE); | |
4248 | #endif | |
4249 | drm_pci_free(dev, phys_obj->handle); | |
4250 | kfree(phys_obj); | |
4251 | dev_priv->mm.phys_objs[id - 1] = NULL; | |
4252 | } | |
4253 | ||
4254 | void i915_gem_free_all_phys_object(struct drm_device *dev) | |
4255 | { | |
4256 | int i; | |
4257 | ||
260883c8 | 4258 | for (i = I915_GEM_PHYS_CURSOR_0; i <= I915_MAX_PHYS_OBJECT; i++) |
71acb5eb DA |
4259 | i915_gem_free_phys_object(dev, i); |
4260 | } | |
4261 | ||
4262 | void i915_gem_detach_phys_object(struct drm_device *dev, | |
05394f39 | 4263 | struct drm_i915_gem_object *obj) |
71acb5eb | 4264 | { |
496ad9aa | 4265 | struct address_space *mapping = file_inode(obj->base.filp)->i_mapping; |
e5281ccd | 4266 | char *vaddr; |
71acb5eb | 4267 | int i; |
71acb5eb DA |
4268 | int page_count; |
4269 | ||
05394f39 | 4270 | if (!obj->phys_obj) |
71acb5eb | 4271 | return; |
05394f39 | 4272 | vaddr = obj->phys_obj->handle->vaddr; |
71acb5eb | 4273 | |
05394f39 | 4274 | page_count = obj->base.size / PAGE_SIZE; |
71acb5eb | 4275 | for (i = 0; i < page_count; i++) { |
5949eac4 | 4276 | struct page *page = shmem_read_mapping_page(mapping, i); |
e5281ccd CW |
4277 | if (!IS_ERR(page)) { |
4278 | char *dst = kmap_atomic(page); | |
4279 | memcpy(dst, vaddr + i*PAGE_SIZE, PAGE_SIZE); | |
4280 | kunmap_atomic(dst); | |
4281 | ||
4282 | drm_clflush_pages(&page, 1); | |
4283 | ||
4284 | set_page_dirty(page); | |
4285 | mark_page_accessed(page); | |
4286 | page_cache_release(page); | |
4287 | } | |
71acb5eb | 4288 | } |
e76e9aeb | 4289 | i915_gem_chipset_flush(dev); |
d78b47b9 | 4290 | |
05394f39 CW |
4291 | obj->phys_obj->cur_obj = NULL; |
4292 | obj->phys_obj = NULL; | |
71acb5eb DA |
4293 | } |
4294 | ||
4295 | int | |
4296 | i915_gem_attach_phys_object(struct drm_device *dev, | |
05394f39 | 4297 | struct drm_i915_gem_object *obj, |
6eeefaf3 CW |
4298 | int id, |
4299 | int align) | |
71acb5eb | 4300 | { |
496ad9aa | 4301 | struct address_space *mapping = file_inode(obj->base.filp)->i_mapping; |
71acb5eb | 4302 | drm_i915_private_t *dev_priv = dev->dev_private; |
71acb5eb DA |
4303 | int ret = 0; |
4304 | int page_count; | |
4305 | int i; | |
4306 | ||
4307 | if (id > I915_MAX_PHYS_OBJECT) | |
4308 | return -EINVAL; | |
4309 | ||
05394f39 CW |
4310 | if (obj->phys_obj) { |
4311 | if (obj->phys_obj->id == id) | |
71acb5eb DA |
4312 | return 0; |
4313 | i915_gem_detach_phys_object(dev, obj); | |
4314 | } | |
4315 | ||
71acb5eb DA |
4316 | /* create a new object */ |
4317 | if (!dev_priv->mm.phys_objs[id - 1]) { | |
4318 | ret = i915_gem_init_phys_object(dev, id, | |
05394f39 | 4319 | obj->base.size, align); |
71acb5eb | 4320 | if (ret) { |
05394f39 CW |
4321 | DRM_ERROR("failed to init phys object %d size: %zu\n", |
4322 | id, obj->base.size); | |
e5281ccd | 4323 | return ret; |
71acb5eb DA |
4324 | } |
4325 | } | |
4326 | ||
4327 | /* bind to the object */ | |
05394f39 CW |
4328 | obj->phys_obj = dev_priv->mm.phys_objs[id - 1]; |
4329 | obj->phys_obj->cur_obj = obj; | |
71acb5eb | 4330 | |
05394f39 | 4331 | page_count = obj->base.size / PAGE_SIZE; |
71acb5eb DA |
4332 | |
4333 | for (i = 0; i < page_count; i++) { | |
e5281ccd CW |
4334 | struct page *page; |
4335 | char *dst, *src; | |
4336 | ||
5949eac4 | 4337 | page = shmem_read_mapping_page(mapping, i); |
e5281ccd CW |
4338 | if (IS_ERR(page)) |
4339 | return PTR_ERR(page); | |
71acb5eb | 4340 | |
ff75b9bc | 4341 | src = kmap_atomic(page); |
05394f39 | 4342 | dst = obj->phys_obj->handle->vaddr + (i * PAGE_SIZE); |
71acb5eb | 4343 | memcpy(dst, src, PAGE_SIZE); |
3e4d3af5 | 4344 | kunmap_atomic(src); |
71acb5eb | 4345 | |
e5281ccd CW |
4346 | mark_page_accessed(page); |
4347 | page_cache_release(page); | |
4348 | } | |
d78b47b9 | 4349 | |
71acb5eb | 4350 | return 0; |
71acb5eb DA |
4351 | } |
4352 | ||
4353 | static int | |
05394f39 CW |
4354 | i915_gem_phys_pwrite(struct drm_device *dev, |
4355 | struct drm_i915_gem_object *obj, | |
71acb5eb DA |
4356 | struct drm_i915_gem_pwrite *args, |
4357 | struct drm_file *file_priv) | |
4358 | { | |
05394f39 | 4359 | void *vaddr = obj->phys_obj->handle->vaddr + args->offset; |
2bb4629a | 4360 | char __user *user_data = to_user_ptr(args->data_ptr); |
71acb5eb | 4361 | |
b47b30cc CW |
4362 | if (__copy_from_user_inatomic_nocache(vaddr, user_data, args->size)) { |
4363 | unsigned long unwritten; | |
4364 | ||
4365 | /* The physical object once assigned is fixed for the lifetime | |
4366 | * of the obj, so we can safely drop the lock and continue | |
4367 | * to access vaddr. | |
4368 | */ | |
4369 | mutex_unlock(&dev->struct_mutex); | |
4370 | unwritten = copy_from_user(vaddr, user_data, args->size); | |
4371 | mutex_lock(&dev->struct_mutex); | |
4372 | if (unwritten) | |
4373 | return -EFAULT; | |
4374 | } | |
71acb5eb | 4375 | |
e76e9aeb | 4376 | i915_gem_chipset_flush(dev); |
71acb5eb DA |
4377 | return 0; |
4378 | } | |
b962442e | 4379 | |
f787a5f5 | 4380 | void i915_gem_release(struct drm_device *dev, struct drm_file *file) |
b962442e | 4381 | { |
f787a5f5 | 4382 | struct drm_i915_file_private *file_priv = file->driver_priv; |
b962442e EA |
4383 | |
4384 | /* Clean up our request list when the client is going away, so that | |
4385 | * later retire_requests won't dereference our soon-to-be-gone | |
4386 | * file_priv. | |
4387 | */ | |
1c25595f | 4388 | spin_lock(&file_priv->mm.lock); |
f787a5f5 CW |
4389 | while (!list_empty(&file_priv->mm.request_list)) { |
4390 | struct drm_i915_gem_request *request; | |
4391 | ||
4392 | request = list_first_entry(&file_priv->mm.request_list, | |
4393 | struct drm_i915_gem_request, | |
4394 | client_list); | |
4395 | list_del(&request->client_list); | |
4396 | request->file_priv = NULL; | |
4397 | } | |
1c25595f | 4398 | spin_unlock(&file_priv->mm.lock); |
b962442e | 4399 | } |
31169714 | 4400 | |
5774506f CW |
4401 | static bool mutex_is_locked_by(struct mutex *mutex, struct task_struct *task) |
4402 | { | |
4403 | if (!mutex_is_locked(mutex)) | |
4404 | return false; | |
4405 | ||
4406 | #if defined(CONFIG_SMP) || defined(CONFIG_DEBUG_MUTEXES) | |
4407 | return mutex->owner == task; | |
4408 | #else | |
4409 | /* Since UP may be pre-empted, we cannot assume that we own the lock */ | |
4410 | return false; | |
4411 | #endif | |
4412 | } | |
4413 | ||
31169714 | 4414 | static int |
1495f230 | 4415 | i915_gem_inactive_shrink(struct shrinker *shrinker, struct shrink_control *sc) |
31169714 | 4416 | { |
17250b71 CW |
4417 | struct drm_i915_private *dev_priv = |
4418 | container_of(shrinker, | |
4419 | struct drm_i915_private, | |
4420 | mm.inactive_shrinker); | |
4421 | struct drm_device *dev = dev_priv->dev; | |
6c085a72 | 4422 | struct drm_i915_gem_object *obj; |
1495f230 | 4423 | int nr_to_scan = sc->nr_to_scan; |
5774506f | 4424 | bool unlock = true; |
17250b71 CW |
4425 | int cnt; |
4426 | ||
5774506f CW |
4427 | if (!mutex_trylock(&dev->struct_mutex)) { |
4428 | if (!mutex_is_locked_by(&dev->struct_mutex, current)) | |
4429 | return 0; | |
4430 | ||
677feac2 DV |
4431 | if (dev_priv->mm.shrinker_no_lock_stealing) |
4432 | return 0; | |
4433 | ||
5774506f CW |
4434 | unlock = false; |
4435 | } | |
31169714 | 4436 | |
6c085a72 CW |
4437 | if (nr_to_scan) { |
4438 | nr_to_scan -= i915_gem_purge(dev_priv, nr_to_scan); | |
93927ca5 DV |
4439 | if (nr_to_scan > 0) |
4440 | nr_to_scan -= __i915_gem_shrink(dev_priv, nr_to_scan, | |
4441 | false); | |
6c085a72 CW |
4442 | if (nr_to_scan > 0) |
4443 | i915_gem_shrink_all(dev_priv); | |
31169714 CW |
4444 | } |
4445 | ||
17250b71 | 4446 | cnt = 0; |
6c085a72 | 4447 | list_for_each_entry(obj, &dev_priv->mm.unbound_list, gtt_list) |
a5570178 CW |
4448 | if (obj->pages_pin_count == 0) |
4449 | cnt += obj->base.size >> PAGE_SHIFT; | |
93927ca5 | 4450 | list_for_each_entry(obj, &dev_priv->mm.inactive_list, gtt_list) |
a5570178 | 4451 | if (obj->pin_count == 0 && obj->pages_pin_count == 0) |
6c085a72 | 4452 | cnt += obj->base.size >> PAGE_SHIFT; |
17250b71 | 4453 | |
5774506f CW |
4454 | if (unlock) |
4455 | mutex_unlock(&dev->struct_mutex); | |
6c085a72 | 4456 | return cnt; |
31169714 | 4457 | } |