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Commit | Line | Data |
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673a394b EA |
1 | /* |
2 | * Copyright © 2008 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | * | |
26 | */ | |
27 | ||
28 | #include "drmP.h" | |
29 | #include "drm.h" | |
30 | #include "i915_drm.h" | |
31 | #include "i915_drv.h" | |
1c5d22f7 | 32 | #include "i915_trace.h" |
652c393a | 33 | #include "intel_drv.h" |
5949eac4 | 34 | #include <linux/shmem_fs.h> |
5a0e3ad6 | 35 | #include <linux/slab.h> |
673a394b | 36 | #include <linux/swap.h> |
79e53945 | 37 | #include <linux/pci.h> |
673a394b | 38 | |
88241785 | 39 | static __must_check int i915_gem_object_flush_gpu_write_domain(struct drm_i915_gem_object *obj); |
05394f39 CW |
40 | static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj); |
41 | static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj); | |
88241785 CW |
42 | static __must_check int i915_gem_object_bind_to_gtt(struct drm_i915_gem_object *obj, |
43 | unsigned alignment, | |
44 | bool map_and_fenceable); | |
05394f39 CW |
45 | static int i915_gem_phys_pwrite(struct drm_device *dev, |
46 | struct drm_i915_gem_object *obj, | |
71acb5eb | 47 | struct drm_i915_gem_pwrite *args, |
05394f39 CW |
48 | struct drm_file *file); |
49 | static void i915_gem_free_object_tail(struct drm_i915_gem_object *obj); | |
673a394b | 50 | |
61050808 CW |
51 | static void i915_gem_write_fence(struct drm_device *dev, int reg, |
52 | struct drm_i915_gem_object *obj); | |
53 | static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj, | |
54 | struct drm_i915_fence_reg *fence, | |
55 | bool enable); | |
56 | ||
17250b71 | 57 | static int i915_gem_inactive_shrink(struct shrinker *shrinker, |
1495f230 | 58 | struct shrink_control *sc); |
8c59967c | 59 | static void i915_gem_object_truncate(struct drm_i915_gem_object *obj); |
31169714 | 60 | |
61050808 CW |
61 | static inline void i915_gem_object_fence_lost(struct drm_i915_gem_object *obj) |
62 | { | |
63 | if (obj->tiling_mode) | |
64 | i915_gem_release_mmap(obj); | |
65 | ||
66 | /* As we do not have an associated fence register, we will force | |
67 | * a tiling change if we ever need to acquire one. | |
68 | */ | |
69 | obj->tiling_changed = false; | |
70 | obj->fence_reg = I915_FENCE_REG_NONE; | |
71 | } | |
72 | ||
73aa808f CW |
73 | /* some bookkeeping */ |
74 | static void i915_gem_info_add_obj(struct drm_i915_private *dev_priv, | |
75 | size_t size) | |
76 | { | |
77 | dev_priv->mm.object_count++; | |
78 | dev_priv->mm.object_memory += size; | |
79 | } | |
80 | ||
81 | static void i915_gem_info_remove_obj(struct drm_i915_private *dev_priv, | |
82 | size_t size) | |
83 | { | |
84 | dev_priv->mm.object_count--; | |
85 | dev_priv->mm.object_memory -= size; | |
86 | } | |
87 | ||
21dd3734 CW |
88 | static int |
89 | i915_gem_wait_for_error(struct drm_device *dev) | |
30dbf0c0 CW |
90 | { |
91 | struct drm_i915_private *dev_priv = dev->dev_private; | |
92 | struct completion *x = &dev_priv->error_completion; | |
93 | unsigned long flags; | |
94 | int ret; | |
95 | ||
96 | if (!atomic_read(&dev_priv->mm.wedged)) | |
97 | return 0; | |
98 | ||
99 | ret = wait_for_completion_interruptible(x); | |
100 | if (ret) | |
101 | return ret; | |
102 | ||
21dd3734 CW |
103 | if (atomic_read(&dev_priv->mm.wedged)) { |
104 | /* GPU is hung, bump the completion count to account for | |
105 | * the token we just consumed so that we never hit zero and | |
106 | * end up waiting upon a subsequent completion event that | |
107 | * will never happen. | |
108 | */ | |
109 | spin_lock_irqsave(&x->wait.lock, flags); | |
110 | x->done++; | |
111 | spin_unlock_irqrestore(&x->wait.lock, flags); | |
112 | } | |
113 | return 0; | |
30dbf0c0 CW |
114 | } |
115 | ||
54cf91dc | 116 | int i915_mutex_lock_interruptible(struct drm_device *dev) |
76c1dec1 | 117 | { |
76c1dec1 CW |
118 | int ret; |
119 | ||
21dd3734 | 120 | ret = i915_gem_wait_for_error(dev); |
76c1dec1 CW |
121 | if (ret) |
122 | return ret; | |
123 | ||
124 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
125 | if (ret) | |
126 | return ret; | |
127 | ||
23bc5982 | 128 | WARN_ON(i915_verify_lists(dev)); |
76c1dec1 CW |
129 | return 0; |
130 | } | |
30dbf0c0 | 131 | |
7d1c4804 | 132 | static inline bool |
05394f39 | 133 | i915_gem_object_is_inactive(struct drm_i915_gem_object *obj) |
7d1c4804 | 134 | { |
05394f39 | 135 | return obj->gtt_space && !obj->active && obj->pin_count == 0; |
7d1c4804 CW |
136 | } |
137 | ||
79e53945 JB |
138 | int |
139 | i915_gem_init_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 140 | struct drm_file *file) |
79e53945 JB |
141 | { |
142 | struct drm_i915_gem_init *args = data; | |
2021746e CW |
143 | |
144 | if (args->gtt_start >= args->gtt_end || | |
145 | (args->gtt_end | args->gtt_start) & (PAGE_SIZE - 1)) | |
146 | return -EINVAL; | |
79e53945 | 147 | |
f534bc0b DV |
148 | /* GEM with user mode setting was never supported on ilk and later. */ |
149 | if (INTEL_INFO(dev)->gen >= 5) | |
150 | return -ENODEV; | |
151 | ||
79e53945 | 152 | mutex_lock(&dev->struct_mutex); |
644ec02b DV |
153 | i915_gem_init_global_gtt(dev, args->gtt_start, |
154 | args->gtt_end, args->gtt_end); | |
673a394b EA |
155 | mutex_unlock(&dev->struct_mutex); |
156 | ||
2021746e | 157 | return 0; |
673a394b EA |
158 | } |
159 | ||
5a125c3c EA |
160 | int |
161 | i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 162 | struct drm_file *file) |
5a125c3c | 163 | { |
73aa808f | 164 | struct drm_i915_private *dev_priv = dev->dev_private; |
5a125c3c | 165 | struct drm_i915_gem_get_aperture *args = data; |
6299f992 CW |
166 | struct drm_i915_gem_object *obj; |
167 | size_t pinned; | |
5a125c3c EA |
168 | |
169 | if (!(dev->driver->driver_features & DRIVER_GEM)) | |
170 | return -ENODEV; | |
171 | ||
6299f992 | 172 | pinned = 0; |
73aa808f | 173 | mutex_lock(&dev->struct_mutex); |
6299f992 CW |
174 | list_for_each_entry(obj, &dev_priv->mm.pinned_list, mm_list) |
175 | pinned += obj->gtt_space->size; | |
73aa808f | 176 | mutex_unlock(&dev->struct_mutex); |
5a125c3c | 177 | |
6299f992 | 178 | args->aper_size = dev_priv->mm.gtt_total; |
0206e353 | 179 | args->aper_available_size = args->aper_size - pinned; |
6299f992 | 180 | |
5a125c3c EA |
181 | return 0; |
182 | } | |
183 | ||
ff72145b DA |
184 | static int |
185 | i915_gem_create(struct drm_file *file, | |
186 | struct drm_device *dev, | |
187 | uint64_t size, | |
188 | uint32_t *handle_p) | |
673a394b | 189 | { |
05394f39 | 190 | struct drm_i915_gem_object *obj; |
a1a2d1d3 PP |
191 | int ret; |
192 | u32 handle; | |
673a394b | 193 | |
ff72145b | 194 | size = roundup(size, PAGE_SIZE); |
8ffc0246 CW |
195 | if (size == 0) |
196 | return -EINVAL; | |
673a394b EA |
197 | |
198 | /* Allocate the new object */ | |
ff72145b | 199 | obj = i915_gem_alloc_object(dev, size); |
673a394b EA |
200 | if (obj == NULL) |
201 | return -ENOMEM; | |
202 | ||
05394f39 | 203 | ret = drm_gem_handle_create(file, &obj->base, &handle); |
1dfd9754 | 204 | if (ret) { |
05394f39 CW |
205 | drm_gem_object_release(&obj->base); |
206 | i915_gem_info_remove_obj(dev->dev_private, obj->base.size); | |
202f2fef | 207 | kfree(obj); |
673a394b | 208 | return ret; |
1dfd9754 | 209 | } |
673a394b | 210 | |
202f2fef | 211 | /* drop reference from allocate - handle holds it now */ |
05394f39 | 212 | drm_gem_object_unreference(&obj->base); |
202f2fef CW |
213 | trace_i915_gem_object_create(obj); |
214 | ||
ff72145b | 215 | *handle_p = handle; |
673a394b EA |
216 | return 0; |
217 | } | |
218 | ||
ff72145b DA |
219 | int |
220 | i915_gem_dumb_create(struct drm_file *file, | |
221 | struct drm_device *dev, | |
222 | struct drm_mode_create_dumb *args) | |
223 | { | |
224 | /* have to work out size/pitch and return them */ | |
ed0291fd | 225 | args->pitch = ALIGN(args->width * ((args->bpp + 7) / 8), 64); |
ff72145b DA |
226 | args->size = args->pitch * args->height; |
227 | return i915_gem_create(file, dev, | |
228 | args->size, &args->handle); | |
229 | } | |
230 | ||
231 | int i915_gem_dumb_destroy(struct drm_file *file, | |
232 | struct drm_device *dev, | |
233 | uint32_t handle) | |
234 | { | |
235 | return drm_gem_handle_delete(file, handle); | |
236 | } | |
237 | ||
238 | /** | |
239 | * Creates a new mm object and returns a handle to it. | |
240 | */ | |
241 | int | |
242 | i915_gem_create_ioctl(struct drm_device *dev, void *data, | |
243 | struct drm_file *file) | |
244 | { | |
245 | struct drm_i915_gem_create *args = data; | |
246 | return i915_gem_create(file, dev, | |
247 | args->size, &args->handle); | |
248 | } | |
249 | ||
05394f39 | 250 | static int i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj) |
280b713b | 251 | { |
05394f39 | 252 | drm_i915_private_t *dev_priv = obj->base.dev->dev_private; |
280b713b EA |
253 | |
254 | return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 && | |
05394f39 | 255 | obj->tiling_mode != I915_TILING_NONE; |
280b713b EA |
256 | } |
257 | ||
8461d226 DV |
258 | static inline int |
259 | __copy_to_user_swizzled(char __user *cpu_vaddr, | |
260 | const char *gpu_vaddr, int gpu_offset, | |
261 | int length) | |
262 | { | |
263 | int ret, cpu_offset = 0; | |
264 | ||
265 | while (length > 0) { | |
266 | int cacheline_end = ALIGN(gpu_offset + 1, 64); | |
267 | int this_length = min(cacheline_end - gpu_offset, length); | |
268 | int swizzled_gpu_offset = gpu_offset ^ 64; | |
269 | ||
270 | ret = __copy_to_user(cpu_vaddr + cpu_offset, | |
271 | gpu_vaddr + swizzled_gpu_offset, | |
272 | this_length); | |
273 | if (ret) | |
274 | return ret + length; | |
275 | ||
276 | cpu_offset += this_length; | |
277 | gpu_offset += this_length; | |
278 | length -= this_length; | |
279 | } | |
280 | ||
281 | return 0; | |
282 | } | |
283 | ||
8c59967c DV |
284 | static inline int |
285 | __copy_from_user_swizzled(char __user *gpu_vaddr, int gpu_offset, | |
286 | const char *cpu_vaddr, | |
287 | int length) | |
288 | { | |
289 | int ret, cpu_offset = 0; | |
290 | ||
291 | while (length > 0) { | |
292 | int cacheline_end = ALIGN(gpu_offset + 1, 64); | |
293 | int this_length = min(cacheline_end - gpu_offset, length); | |
294 | int swizzled_gpu_offset = gpu_offset ^ 64; | |
295 | ||
296 | ret = __copy_from_user(gpu_vaddr + swizzled_gpu_offset, | |
297 | cpu_vaddr + cpu_offset, | |
298 | this_length); | |
299 | if (ret) | |
300 | return ret + length; | |
301 | ||
302 | cpu_offset += this_length; | |
303 | gpu_offset += this_length; | |
304 | length -= this_length; | |
305 | } | |
306 | ||
307 | return 0; | |
308 | } | |
309 | ||
d174bd64 DV |
310 | /* Per-page copy function for the shmem pread fastpath. |
311 | * Flushes invalid cachelines before reading the target if | |
312 | * needs_clflush is set. */ | |
eb01459f | 313 | static int |
d174bd64 DV |
314 | shmem_pread_fast(struct page *page, int shmem_page_offset, int page_length, |
315 | char __user *user_data, | |
316 | bool page_do_bit17_swizzling, bool needs_clflush) | |
317 | { | |
318 | char *vaddr; | |
319 | int ret; | |
320 | ||
e7e58eb5 | 321 | if (unlikely(page_do_bit17_swizzling)) |
d174bd64 DV |
322 | return -EINVAL; |
323 | ||
324 | vaddr = kmap_atomic(page); | |
325 | if (needs_clflush) | |
326 | drm_clflush_virt_range(vaddr + shmem_page_offset, | |
327 | page_length); | |
328 | ret = __copy_to_user_inatomic(user_data, | |
329 | vaddr + shmem_page_offset, | |
330 | page_length); | |
331 | kunmap_atomic(vaddr); | |
332 | ||
333 | return ret; | |
334 | } | |
335 | ||
23c18c71 DV |
336 | static void |
337 | shmem_clflush_swizzled_range(char *addr, unsigned long length, | |
338 | bool swizzled) | |
339 | { | |
e7e58eb5 | 340 | if (unlikely(swizzled)) { |
23c18c71 DV |
341 | unsigned long start = (unsigned long) addr; |
342 | unsigned long end = (unsigned long) addr + length; | |
343 | ||
344 | /* For swizzling simply ensure that we always flush both | |
345 | * channels. Lame, but simple and it works. Swizzled | |
346 | * pwrite/pread is far from a hotpath - current userspace | |
347 | * doesn't use it at all. */ | |
348 | start = round_down(start, 128); | |
349 | end = round_up(end, 128); | |
350 | ||
351 | drm_clflush_virt_range((void *)start, end - start); | |
352 | } else { | |
353 | drm_clflush_virt_range(addr, length); | |
354 | } | |
355 | ||
356 | } | |
357 | ||
d174bd64 DV |
358 | /* Only difference to the fast-path function is that this can handle bit17 |
359 | * and uses non-atomic copy and kmap functions. */ | |
360 | static int | |
361 | shmem_pread_slow(struct page *page, int shmem_page_offset, int page_length, | |
362 | char __user *user_data, | |
363 | bool page_do_bit17_swizzling, bool needs_clflush) | |
364 | { | |
365 | char *vaddr; | |
366 | int ret; | |
367 | ||
368 | vaddr = kmap(page); | |
369 | if (needs_clflush) | |
23c18c71 DV |
370 | shmem_clflush_swizzled_range(vaddr + shmem_page_offset, |
371 | page_length, | |
372 | page_do_bit17_swizzling); | |
d174bd64 DV |
373 | |
374 | if (page_do_bit17_swizzling) | |
375 | ret = __copy_to_user_swizzled(user_data, | |
376 | vaddr, shmem_page_offset, | |
377 | page_length); | |
378 | else | |
379 | ret = __copy_to_user(user_data, | |
380 | vaddr + shmem_page_offset, | |
381 | page_length); | |
382 | kunmap(page); | |
383 | ||
384 | return ret; | |
385 | } | |
386 | ||
eb01459f | 387 | static int |
dbf7bff0 DV |
388 | i915_gem_shmem_pread(struct drm_device *dev, |
389 | struct drm_i915_gem_object *obj, | |
390 | struct drm_i915_gem_pread *args, | |
391 | struct drm_file *file) | |
eb01459f | 392 | { |
05394f39 | 393 | struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping; |
8461d226 | 394 | char __user *user_data; |
eb01459f | 395 | ssize_t remain; |
8461d226 | 396 | loff_t offset; |
eb2c0c81 | 397 | int shmem_page_offset, page_length, ret = 0; |
8461d226 | 398 | int obj_do_bit17_swizzling, page_do_bit17_swizzling; |
dbf7bff0 | 399 | int hit_slowpath = 0; |
96d79b52 | 400 | int prefaulted = 0; |
8489731c | 401 | int needs_clflush = 0; |
692a576b | 402 | int release_page; |
eb01459f | 403 | |
8461d226 | 404 | user_data = (char __user *) (uintptr_t) args->data_ptr; |
eb01459f EA |
405 | remain = args->size; |
406 | ||
8461d226 | 407 | obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj); |
eb01459f | 408 | |
8489731c DV |
409 | if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU)) { |
410 | /* If we're not in the cpu read domain, set ourself into the gtt | |
411 | * read domain and manually flush cachelines (if required). This | |
412 | * optimizes for the case when the gpu will dirty the data | |
413 | * anyway again before the next pread happens. */ | |
414 | if (obj->cache_level == I915_CACHE_NONE) | |
415 | needs_clflush = 1; | |
416 | ret = i915_gem_object_set_to_gtt_domain(obj, false); | |
417 | if (ret) | |
418 | return ret; | |
419 | } | |
eb01459f | 420 | |
8461d226 | 421 | offset = args->offset; |
eb01459f EA |
422 | |
423 | while (remain > 0) { | |
e5281ccd CW |
424 | struct page *page; |
425 | ||
eb01459f EA |
426 | /* Operation in this page |
427 | * | |
eb01459f | 428 | * shmem_page_offset = offset within page in shmem file |
eb01459f EA |
429 | * page_length = bytes to copy for this page |
430 | */ | |
c8cbbb8b | 431 | shmem_page_offset = offset_in_page(offset); |
eb01459f EA |
432 | page_length = remain; |
433 | if ((shmem_page_offset + page_length) > PAGE_SIZE) | |
434 | page_length = PAGE_SIZE - shmem_page_offset; | |
eb01459f | 435 | |
692a576b DV |
436 | if (obj->pages) { |
437 | page = obj->pages[offset >> PAGE_SHIFT]; | |
438 | release_page = 0; | |
439 | } else { | |
440 | page = shmem_read_mapping_page(mapping, offset >> PAGE_SHIFT); | |
441 | if (IS_ERR(page)) { | |
442 | ret = PTR_ERR(page); | |
443 | goto out; | |
444 | } | |
445 | release_page = 1; | |
b65552f0 | 446 | } |
e5281ccd | 447 | |
8461d226 DV |
448 | page_do_bit17_swizzling = obj_do_bit17_swizzling && |
449 | (page_to_phys(page) & (1 << 17)) != 0; | |
450 | ||
d174bd64 DV |
451 | ret = shmem_pread_fast(page, shmem_page_offset, page_length, |
452 | user_data, page_do_bit17_swizzling, | |
453 | needs_clflush); | |
454 | if (ret == 0) | |
455 | goto next_page; | |
dbf7bff0 DV |
456 | |
457 | hit_slowpath = 1; | |
692a576b | 458 | page_cache_get(page); |
dbf7bff0 DV |
459 | mutex_unlock(&dev->struct_mutex); |
460 | ||
96d79b52 | 461 | if (!prefaulted) { |
f56f821f | 462 | ret = fault_in_multipages_writeable(user_data, remain); |
96d79b52 DV |
463 | /* Userspace is tricking us, but we've already clobbered |
464 | * its pages with the prefault and promised to write the | |
465 | * data up to the first fault. Hence ignore any errors | |
466 | * and just continue. */ | |
467 | (void)ret; | |
468 | prefaulted = 1; | |
469 | } | |
eb01459f | 470 | |
d174bd64 DV |
471 | ret = shmem_pread_slow(page, shmem_page_offset, page_length, |
472 | user_data, page_do_bit17_swizzling, | |
473 | needs_clflush); | |
eb01459f | 474 | |
dbf7bff0 | 475 | mutex_lock(&dev->struct_mutex); |
e5281ccd | 476 | page_cache_release(page); |
dbf7bff0 | 477 | next_page: |
e5281ccd | 478 | mark_page_accessed(page); |
692a576b DV |
479 | if (release_page) |
480 | page_cache_release(page); | |
e5281ccd | 481 | |
8461d226 DV |
482 | if (ret) { |
483 | ret = -EFAULT; | |
484 | goto out; | |
485 | } | |
486 | ||
eb01459f | 487 | remain -= page_length; |
8461d226 | 488 | user_data += page_length; |
eb01459f EA |
489 | offset += page_length; |
490 | } | |
491 | ||
4f27b75d | 492 | out: |
dbf7bff0 DV |
493 | if (hit_slowpath) { |
494 | /* Fixup: Kill any reinstated backing storage pages */ | |
495 | if (obj->madv == __I915_MADV_PURGED) | |
496 | i915_gem_object_truncate(obj); | |
497 | } | |
eb01459f EA |
498 | |
499 | return ret; | |
500 | } | |
501 | ||
673a394b EA |
502 | /** |
503 | * Reads data from the object referenced by handle. | |
504 | * | |
505 | * On error, the contents of *data are undefined. | |
506 | */ | |
507 | int | |
508 | i915_gem_pread_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 509 | struct drm_file *file) |
673a394b EA |
510 | { |
511 | struct drm_i915_gem_pread *args = data; | |
05394f39 | 512 | struct drm_i915_gem_object *obj; |
35b62a89 | 513 | int ret = 0; |
673a394b | 514 | |
51311d0a CW |
515 | if (args->size == 0) |
516 | return 0; | |
517 | ||
518 | if (!access_ok(VERIFY_WRITE, | |
519 | (char __user *)(uintptr_t)args->data_ptr, | |
520 | args->size)) | |
521 | return -EFAULT; | |
522 | ||
4f27b75d | 523 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 524 | if (ret) |
4f27b75d | 525 | return ret; |
673a394b | 526 | |
05394f39 | 527 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 528 | if (&obj->base == NULL) { |
1d7cfea1 CW |
529 | ret = -ENOENT; |
530 | goto unlock; | |
4f27b75d | 531 | } |
673a394b | 532 | |
7dcd2499 | 533 | /* Bounds check source. */ |
05394f39 CW |
534 | if (args->offset > obj->base.size || |
535 | args->size > obj->base.size - args->offset) { | |
ce9d419d | 536 | ret = -EINVAL; |
35b62a89 | 537 | goto out; |
ce9d419d CW |
538 | } |
539 | ||
db53a302 CW |
540 | trace_i915_gem_object_pread(obj, args->offset, args->size); |
541 | ||
dbf7bff0 | 542 | ret = i915_gem_shmem_pread(dev, obj, args, file); |
673a394b | 543 | |
35b62a89 | 544 | out: |
05394f39 | 545 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 546 | unlock: |
4f27b75d | 547 | mutex_unlock(&dev->struct_mutex); |
eb01459f | 548 | return ret; |
673a394b EA |
549 | } |
550 | ||
0839ccb8 KP |
551 | /* This is the fast write path which cannot handle |
552 | * page faults in the source data | |
9b7530cc | 553 | */ |
0839ccb8 KP |
554 | |
555 | static inline int | |
556 | fast_user_write(struct io_mapping *mapping, | |
557 | loff_t page_base, int page_offset, | |
558 | char __user *user_data, | |
559 | int length) | |
9b7530cc | 560 | { |
9b7530cc | 561 | char *vaddr_atomic; |
0839ccb8 | 562 | unsigned long unwritten; |
9b7530cc | 563 | |
3e4d3af5 | 564 | vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base); |
0839ccb8 KP |
565 | unwritten = __copy_from_user_inatomic_nocache(vaddr_atomic + page_offset, |
566 | user_data, length); | |
3e4d3af5 | 567 | io_mapping_unmap_atomic(vaddr_atomic); |
fbd5a26d | 568 | return unwritten; |
0839ccb8 KP |
569 | } |
570 | ||
3de09aa3 EA |
571 | /** |
572 | * This is the fast pwrite path, where we copy the data directly from the | |
573 | * user into the GTT, uncached. | |
574 | */ | |
673a394b | 575 | static int |
05394f39 CW |
576 | i915_gem_gtt_pwrite_fast(struct drm_device *dev, |
577 | struct drm_i915_gem_object *obj, | |
3de09aa3 | 578 | struct drm_i915_gem_pwrite *args, |
05394f39 | 579 | struct drm_file *file) |
673a394b | 580 | { |
0839ccb8 | 581 | drm_i915_private_t *dev_priv = dev->dev_private; |
673a394b | 582 | ssize_t remain; |
0839ccb8 | 583 | loff_t offset, page_base; |
673a394b | 584 | char __user *user_data; |
935aaa69 DV |
585 | int page_offset, page_length, ret; |
586 | ||
587 | ret = i915_gem_object_pin(obj, 0, true); | |
588 | if (ret) | |
589 | goto out; | |
590 | ||
591 | ret = i915_gem_object_set_to_gtt_domain(obj, true); | |
592 | if (ret) | |
593 | goto out_unpin; | |
594 | ||
595 | ret = i915_gem_object_put_fence(obj); | |
596 | if (ret) | |
597 | goto out_unpin; | |
673a394b EA |
598 | |
599 | user_data = (char __user *) (uintptr_t) args->data_ptr; | |
600 | remain = args->size; | |
673a394b | 601 | |
05394f39 | 602 | offset = obj->gtt_offset + args->offset; |
673a394b EA |
603 | |
604 | while (remain > 0) { | |
605 | /* Operation in this page | |
606 | * | |
0839ccb8 KP |
607 | * page_base = page offset within aperture |
608 | * page_offset = offset within page | |
609 | * page_length = bytes to copy for this page | |
673a394b | 610 | */ |
c8cbbb8b CW |
611 | page_base = offset & PAGE_MASK; |
612 | page_offset = offset_in_page(offset); | |
0839ccb8 KP |
613 | page_length = remain; |
614 | if ((page_offset + remain) > PAGE_SIZE) | |
615 | page_length = PAGE_SIZE - page_offset; | |
616 | ||
0839ccb8 | 617 | /* If we get a fault while copying data, then (presumably) our |
3de09aa3 EA |
618 | * source page isn't available. Return the error and we'll |
619 | * retry in the slow path. | |
0839ccb8 | 620 | */ |
fbd5a26d | 621 | if (fast_user_write(dev_priv->mm.gtt_mapping, page_base, |
935aaa69 DV |
622 | page_offset, user_data, page_length)) { |
623 | ret = -EFAULT; | |
624 | goto out_unpin; | |
625 | } | |
673a394b | 626 | |
0839ccb8 KP |
627 | remain -= page_length; |
628 | user_data += page_length; | |
629 | offset += page_length; | |
673a394b | 630 | } |
673a394b | 631 | |
935aaa69 DV |
632 | out_unpin: |
633 | i915_gem_object_unpin(obj); | |
634 | out: | |
3de09aa3 | 635 | return ret; |
673a394b EA |
636 | } |
637 | ||
d174bd64 DV |
638 | /* Per-page copy function for the shmem pwrite fastpath. |
639 | * Flushes invalid cachelines before writing to the target if | |
640 | * needs_clflush_before is set and flushes out any written cachelines after | |
641 | * writing if needs_clflush is set. */ | |
3043c60c | 642 | static int |
d174bd64 DV |
643 | shmem_pwrite_fast(struct page *page, int shmem_page_offset, int page_length, |
644 | char __user *user_data, | |
645 | bool page_do_bit17_swizzling, | |
646 | bool needs_clflush_before, | |
647 | bool needs_clflush_after) | |
673a394b | 648 | { |
d174bd64 | 649 | char *vaddr; |
673a394b | 650 | int ret; |
3de09aa3 | 651 | |
e7e58eb5 | 652 | if (unlikely(page_do_bit17_swizzling)) |
d174bd64 | 653 | return -EINVAL; |
3de09aa3 | 654 | |
d174bd64 DV |
655 | vaddr = kmap_atomic(page); |
656 | if (needs_clflush_before) | |
657 | drm_clflush_virt_range(vaddr + shmem_page_offset, | |
658 | page_length); | |
659 | ret = __copy_from_user_inatomic_nocache(vaddr + shmem_page_offset, | |
660 | user_data, | |
661 | page_length); | |
662 | if (needs_clflush_after) | |
663 | drm_clflush_virt_range(vaddr + shmem_page_offset, | |
664 | page_length); | |
665 | kunmap_atomic(vaddr); | |
3de09aa3 EA |
666 | |
667 | return ret; | |
668 | } | |
669 | ||
d174bd64 DV |
670 | /* Only difference to the fast-path function is that this can handle bit17 |
671 | * and uses non-atomic copy and kmap functions. */ | |
3043c60c | 672 | static int |
d174bd64 DV |
673 | shmem_pwrite_slow(struct page *page, int shmem_page_offset, int page_length, |
674 | char __user *user_data, | |
675 | bool page_do_bit17_swizzling, | |
676 | bool needs_clflush_before, | |
677 | bool needs_clflush_after) | |
673a394b | 678 | { |
d174bd64 DV |
679 | char *vaddr; |
680 | int ret; | |
e5281ccd | 681 | |
d174bd64 | 682 | vaddr = kmap(page); |
e7e58eb5 | 683 | if (unlikely(needs_clflush_before || page_do_bit17_swizzling)) |
23c18c71 DV |
684 | shmem_clflush_swizzled_range(vaddr + shmem_page_offset, |
685 | page_length, | |
686 | page_do_bit17_swizzling); | |
d174bd64 DV |
687 | if (page_do_bit17_swizzling) |
688 | ret = __copy_from_user_swizzled(vaddr, shmem_page_offset, | |
e5281ccd CW |
689 | user_data, |
690 | page_length); | |
d174bd64 DV |
691 | else |
692 | ret = __copy_from_user(vaddr + shmem_page_offset, | |
693 | user_data, | |
694 | page_length); | |
695 | if (needs_clflush_after) | |
23c18c71 DV |
696 | shmem_clflush_swizzled_range(vaddr + shmem_page_offset, |
697 | page_length, | |
698 | page_do_bit17_swizzling); | |
d174bd64 | 699 | kunmap(page); |
40123c1f | 700 | |
d174bd64 | 701 | return ret; |
40123c1f EA |
702 | } |
703 | ||
40123c1f | 704 | static int |
e244a443 DV |
705 | i915_gem_shmem_pwrite(struct drm_device *dev, |
706 | struct drm_i915_gem_object *obj, | |
707 | struct drm_i915_gem_pwrite *args, | |
708 | struct drm_file *file) | |
40123c1f | 709 | { |
05394f39 | 710 | struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping; |
40123c1f | 711 | ssize_t remain; |
8c59967c DV |
712 | loff_t offset; |
713 | char __user *user_data; | |
eb2c0c81 | 714 | int shmem_page_offset, page_length, ret = 0; |
8c59967c | 715 | int obj_do_bit17_swizzling, page_do_bit17_swizzling; |
e244a443 | 716 | int hit_slowpath = 0; |
58642885 DV |
717 | int needs_clflush_after = 0; |
718 | int needs_clflush_before = 0; | |
692a576b | 719 | int release_page; |
40123c1f | 720 | |
8c59967c | 721 | user_data = (char __user *) (uintptr_t) args->data_ptr; |
40123c1f EA |
722 | remain = args->size; |
723 | ||
8c59967c | 724 | obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj); |
40123c1f | 725 | |
58642885 DV |
726 | if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) { |
727 | /* If we're not in the cpu write domain, set ourself into the gtt | |
728 | * write domain and manually flush cachelines (if required). This | |
729 | * optimizes for the case when the gpu will use the data | |
730 | * right away and we therefore have to clflush anyway. */ | |
731 | if (obj->cache_level == I915_CACHE_NONE) | |
732 | needs_clflush_after = 1; | |
733 | ret = i915_gem_object_set_to_gtt_domain(obj, true); | |
734 | if (ret) | |
735 | return ret; | |
736 | } | |
737 | /* Same trick applies for invalidate partially written cachelines before | |
738 | * writing. */ | |
739 | if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU) | |
740 | && obj->cache_level == I915_CACHE_NONE) | |
741 | needs_clflush_before = 1; | |
742 | ||
673a394b | 743 | offset = args->offset; |
05394f39 | 744 | obj->dirty = 1; |
673a394b | 745 | |
40123c1f | 746 | while (remain > 0) { |
e5281ccd | 747 | struct page *page; |
58642885 | 748 | int partial_cacheline_write; |
e5281ccd | 749 | |
40123c1f EA |
750 | /* Operation in this page |
751 | * | |
40123c1f | 752 | * shmem_page_offset = offset within page in shmem file |
40123c1f EA |
753 | * page_length = bytes to copy for this page |
754 | */ | |
c8cbbb8b | 755 | shmem_page_offset = offset_in_page(offset); |
40123c1f EA |
756 | |
757 | page_length = remain; | |
758 | if ((shmem_page_offset + page_length) > PAGE_SIZE) | |
759 | page_length = PAGE_SIZE - shmem_page_offset; | |
40123c1f | 760 | |
58642885 DV |
761 | /* If we don't overwrite a cacheline completely we need to be |
762 | * careful to have up-to-date data by first clflushing. Don't | |
763 | * overcomplicate things and flush the entire patch. */ | |
764 | partial_cacheline_write = needs_clflush_before && | |
765 | ((shmem_page_offset | page_length) | |
766 | & (boot_cpu_data.x86_clflush_size - 1)); | |
767 | ||
692a576b DV |
768 | if (obj->pages) { |
769 | page = obj->pages[offset >> PAGE_SHIFT]; | |
770 | release_page = 0; | |
771 | } else { | |
772 | page = shmem_read_mapping_page(mapping, offset >> PAGE_SHIFT); | |
773 | if (IS_ERR(page)) { | |
774 | ret = PTR_ERR(page); | |
775 | goto out; | |
776 | } | |
777 | release_page = 1; | |
e5281ccd CW |
778 | } |
779 | ||
8c59967c DV |
780 | page_do_bit17_swizzling = obj_do_bit17_swizzling && |
781 | (page_to_phys(page) & (1 << 17)) != 0; | |
782 | ||
d174bd64 DV |
783 | ret = shmem_pwrite_fast(page, shmem_page_offset, page_length, |
784 | user_data, page_do_bit17_swizzling, | |
785 | partial_cacheline_write, | |
786 | needs_clflush_after); | |
787 | if (ret == 0) | |
788 | goto next_page; | |
e244a443 DV |
789 | |
790 | hit_slowpath = 1; | |
692a576b | 791 | page_cache_get(page); |
e244a443 DV |
792 | mutex_unlock(&dev->struct_mutex); |
793 | ||
d174bd64 DV |
794 | ret = shmem_pwrite_slow(page, shmem_page_offset, page_length, |
795 | user_data, page_do_bit17_swizzling, | |
796 | partial_cacheline_write, | |
797 | needs_clflush_after); | |
40123c1f | 798 | |
e244a443 | 799 | mutex_lock(&dev->struct_mutex); |
692a576b | 800 | page_cache_release(page); |
e244a443 | 801 | next_page: |
e5281ccd CW |
802 | set_page_dirty(page); |
803 | mark_page_accessed(page); | |
692a576b DV |
804 | if (release_page) |
805 | page_cache_release(page); | |
e5281ccd | 806 | |
8c59967c DV |
807 | if (ret) { |
808 | ret = -EFAULT; | |
809 | goto out; | |
810 | } | |
811 | ||
40123c1f | 812 | remain -= page_length; |
8c59967c | 813 | user_data += page_length; |
40123c1f | 814 | offset += page_length; |
673a394b EA |
815 | } |
816 | ||
fbd5a26d | 817 | out: |
e244a443 DV |
818 | if (hit_slowpath) { |
819 | /* Fixup: Kill any reinstated backing storage pages */ | |
820 | if (obj->madv == __I915_MADV_PURGED) | |
821 | i915_gem_object_truncate(obj); | |
822 | /* and flush dirty cachelines in case the object isn't in the cpu write | |
823 | * domain anymore. */ | |
824 | if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) { | |
825 | i915_gem_clflush_object(obj); | |
826 | intel_gtt_chipset_flush(); | |
827 | } | |
8c59967c | 828 | } |
673a394b | 829 | |
58642885 DV |
830 | if (needs_clflush_after) |
831 | intel_gtt_chipset_flush(); | |
832 | ||
40123c1f | 833 | return ret; |
673a394b EA |
834 | } |
835 | ||
836 | /** | |
837 | * Writes data to the object referenced by handle. | |
838 | * | |
839 | * On error, the contents of the buffer that were to be modified are undefined. | |
840 | */ | |
841 | int | |
842 | i915_gem_pwrite_ioctl(struct drm_device *dev, void *data, | |
fbd5a26d | 843 | struct drm_file *file) |
673a394b EA |
844 | { |
845 | struct drm_i915_gem_pwrite *args = data; | |
05394f39 | 846 | struct drm_i915_gem_object *obj; |
51311d0a CW |
847 | int ret; |
848 | ||
849 | if (args->size == 0) | |
850 | return 0; | |
851 | ||
852 | if (!access_ok(VERIFY_READ, | |
853 | (char __user *)(uintptr_t)args->data_ptr, | |
854 | args->size)) | |
855 | return -EFAULT; | |
856 | ||
f56f821f DV |
857 | ret = fault_in_multipages_readable((char __user *)(uintptr_t)args->data_ptr, |
858 | args->size); | |
51311d0a CW |
859 | if (ret) |
860 | return -EFAULT; | |
673a394b | 861 | |
fbd5a26d | 862 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 863 | if (ret) |
fbd5a26d | 864 | return ret; |
1d7cfea1 | 865 | |
05394f39 | 866 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 867 | if (&obj->base == NULL) { |
1d7cfea1 CW |
868 | ret = -ENOENT; |
869 | goto unlock; | |
fbd5a26d | 870 | } |
673a394b | 871 | |
7dcd2499 | 872 | /* Bounds check destination. */ |
05394f39 CW |
873 | if (args->offset > obj->base.size || |
874 | args->size > obj->base.size - args->offset) { | |
ce9d419d | 875 | ret = -EINVAL; |
35b62a89 | 876 | goto out; |
ce9d419d CW |
877 | } |
878 | ||
db53a302 CW |
879 | trace_i915_gem_object_pwrite(obj, args->offset, args->size); |
880 | ||
935aaa69 | 881 | ret = -EFAULT; |
673a394b EA |
882 | /* We can only do the GTT pwrite on untiled buffers, as otherwise |
883 | * it would end up going through the fenced access, and we'll get | |
884 | * different detiling behavior between reading and writing. | |
885 | * pread/pwrite currently are reading and writing from the CPU | |
886 | * perspective, requiring manual detiling by the client. | |
887 | */ | |
5c0480f2 | 888 | if (obj->phys_obj) { |
fbd5a26d | 889 | ret = i915_gem_phys_pwrite(dev, obj, args, file); |
5c0480f2 DV |
890 | goto out; |
891 | } | |
892 | ||
893 | if (obj->gtt_space && | |
3ae53783 | 894 | obj->cache_level == I915_CACHE_NONE && |
c07496fa | 895 | obj->tiling_mode == I915_TILING_NONE && |
ffc62976 | 896 | obj->map_and_fenceable && |
5c0480f2 | 897 | obj->base.write_domain != I915_GEM_DOMAIN_CPU) { |
fbd5a26d | 898 | ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file); |
935aaa69 DV |
899 | /* Note that the gtt paths might fail with non-page-backed user |
900 | * pointers (e.g. gtt mappings when moving data between | |
901 | * textures). Fallback to the shmem path in that case. */ | |
fbd5a26d | 902 | } |
673a394b | 903 | |
5c0480f2 | 904 | if (ret == -EFAULT) |
935aaa69 | 905 | ret = i915_gem_shmem_pwrite(dev, obj, args, file); |
5c0480f2 | 906 | |
35b62a89 | 907 | out: |
05394f39 | 908 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 909 | unlock: |
fbd5a26d | 910 | mutex_unlock(&dev->struct_mutex); |
673a394b EA |
911 | return ret; |
912 | } | |
913 | ||
914 | /** | |
2ef7eeaa EA |
915 | * Called when user space prepares to use an object with the CPU, either |
916 | * through the mmap ioctl's mapping or a GTT mapping. | |
673a394b EA |
917 | */ |
918 | int | |
919 | i915_gem_set_domain_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 920 | struct drm_file *file) |
673a394b EA |
921 | { |
922 | struct drm_i915_gem_set_domain *args = data; | |
05394f39 | 923 | struct drm_i915_gem_object *obj; |
2ef7eeaa EA |
924 | uint32_t read_domains = args->read_domains; |
925 | uint32_t write_domain = args->write_domain; | |
673a394b EA |
926 | int ret; |
927 | ||
928 | if (!(dev->driver->driver_features & DRIVER_GEM)) | |
929 | return -ENODEV; | |
930 | ||
2ef7eeaa | 931 | /* Only handle setting domains to types used by the CPU. */ |
21d509e3 | 932 | if (write_domain & I915_GEM_GPU_DOMAINS) |
2ef7eeaa EA |
933 | return -EINVAL; |
934 | ||
21d509e3 | 935 | if (read_domains & I915_GEM_GPU_DOMAINS) |
2ef7eeaa EA |
936 | return -EINVAL; |
937 | ||
938 | /* Having something in the write domain implies it's in the read | |
939 | * domain, and only that read domain. Enforce that in the request. | |
940 | */ | |
941 | if (write_domain != 0 && read_domains != write_domain) | |
942 | return -EINVAL; | |
943 | ||
76c1dec1 | 944 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 945 | if (ret) |
76c1dec1 | 946 | return ret; |
1d7cfea1 | 947 | |
05394f39 | 948 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 949 | if (&obj->base == NULL) { |
1d7cfea1 CW |
950 | ret = -ENOENT; |
951 | goto unlock; | |
76c1dec1 | 952 | } |
673a394b | 953 | |
2ef7eeaa EA |
954 | if (read_domains & I915_GEM_DOMAIN_GTT) { |
955 | ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0); | |
02354392 EA |
956 | |
957 | /* Silently promote "you're not bound, there was nothing to do" | |
958 | * to success, since the client was just asking us to | |
959 | * make sure everything was done. | |
960 | */ | |
961 | if (ret == -EINVAL) | |
962 | ret = 0; | |
2ef7eeaa | 963 | } else { |
e47c68e9 | 964 | ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0); |
2ef7eeaa EA |
965 | } |
966 | ||
05394f39 | 967 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 968 | unlock: |
673a394b EA |
969 | mutex_unlock(&dev->struct_mutex); |
970 | return ret; | |
971 | } | |
972 | ||
973 | /** | |
974 | * Called when user space has done writes to this buffer | |
975 | */ | |
976 | int | |
977 | i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 978 | struct drm_file *file) |
673a394b EA |
979 | { |
980 | struct drm_i915_gem_sw_finish *args = data; | |
05394f39 | 981 | struct drm_i915_gem_object *obj; |
673a394b EA |
982 | int ret = 0; |
983 | ||
984 | if (!(dev->driver->driver_features & DRIVER_GEM)) | |
985 | return -ENODEV; | |
986 | ||
76c1dec1 | 987 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 988 | if (ret) |
76c1dec1 | 989 | return ret; |
1d7cfea1 | 990 | |
05394f39 | 991 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 992 | if (&obj->base == NULL) { |
1d7cfea1 CW |
993 | ret = -ENOENT; |
994 | goto unlock; | |
673a394b EA |
995 | } |
996 | ||
673a394b | 997 | /* Pinned buffers may be scanout, so flush the cache */ |
05394f39 | 998 | if (obj->pin_count) |
e47c68e9 EA |
999 | i915_gem_object_flush_cpu_write_domain(obj); |
1000 | ||
05394f39 | 1001 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 1002 | unlock: |
673a394b EA |
1003 | mutex_unlock(&dev->struct_mutex); |
1004 | return ret; | |
1005 | } | |
1006 | ||
1007 | /** | |
1008 | * Maps the contents of an object, returning the address it is mapped | |
1009 | * into. | |
1010 | * | |
1011 | * While the mapping holds a reference on the contents of the object, it doesn't | |
1012 | * imply a ref on the object itself. | |
1013 | */ | |
1014 | int | |
1015 | i915_gem_mmap_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 1016 | struct drm_file *file) |
673a394b EA |
1017 | { |
1018 | struct drm_i915_gem_mmap *args = data; | |
1019 | struct drm_gem_object *obj; | |
673a394b EA |
1020 | unsigned long addr; |
1021 | ||
1022 | if (!(dev->driver->driver_features & DRIVER_GEM)) | |
1023 | return -ENODEV; | |
1024 | ||
05394f39 | 1025 | obj = drm_gem_object_lookup(dev, file, args->handle); |
673a394b | 1026 | if (obj == NULL) |
bf79cb91 | 1027 | return -ENOENT; |
673a394b | 1028 | |
673a394b EA |
1029 | down_write(¤t->mm->mmap_sem); |
1030 | addr = do_mmap(obj->filp, 0, args->size, | |
1031 | PROT_READ | PROT_WRITE, MAP_SHARED, | |
1032 | args->offset); | |
1033 | up_write(¤t->mm->mmap_sem); | |
bc9025bd | 1034 | drm_gem_object_unreference_unlocked(obj); |
673a394b EA |
1035 | if (IS_ERR((void *)addr)) |
1036 | return addr; | |
1037 | ||
1038 | args->addr_ptr = (uint64_t) addr; | |
1039 | ||
1040 | return 0; | |
1041 | } | |
1042 | ||
de151cf6 JB |
1043 | /** |
1044 | * i915_gem_fault - fault a page into the GTT | |
1045 | * vma: VMA in question | |
1046 | * vmf: fault info | |
1047 | * | |
1048 | * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped | |
1049 | * from userspace. The fault handler takes care of binding the object to | |
1050 | * the GTT (if needed), allocating and programming a fence register (again, | |
1051 | * only if needed based on whether the old reg is still valid or the object | |
1052 | * is tiled) and inserting a new PTE into the faulting process. | |
1053 | * | |
1054 | * Note that the faulting process may involve evicting existing objects | |
1055 | * from the GTT and/or fence registers to make room. So performance may | |
1056 | * suffer if the GTT working set is large or there are few fence registers | |
1057 | * left. | |
1058 | */ | |
1059 | int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf) | |
1060 | { | |
05394f39 CW |
1061 | struct drm_i915_gem_object *obj = to_intel_bo(vma->vm_private_data); |
1062 | struct drm_device *dev = obj->base.dev; | |
7d1c4804 | 1063 | drm_i915_private_t *dev_priv = dev->dev_private; |
de151cf6 JB |
1064 | pgoff_t page_offset; |
1065 | unsigned long pfn; | |
1066 | int ret = 0; | |
0f973f27 | 1067 | bool write = !!(vmf->flags & FAULT_FLAG_WRITE); |
de151cf6 JB |
1068 | |
1069 | /* We don't use vmf->pgoff since that has the fake offset */ | |
1070 | page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >> | |
1071 | PAGE_SHIFT; | |
1072 | ||
d9bc7e9f CW |
1073 | ret = i915_mutex_lock_interruptible(dev); |
1074 | if (ret) | |
1075 | goto out; | |
a00b10c3 | 1076 | |
db53a302 CW |
1077 | trace_i915_gem_object_fault(obj, page_offset, true, write); |
1078 | ||
d9bc7e9f | 1079 | /* Now bind it into the GTT if needed */ |
919926ae CW |
1080 | if (!obj->map_and_fenceable) { |
1081 | ret = i915_gem_object_unbind(obj); | |
1082 | if (ret) | |
1083 | goto unlock; | |
a00b10c3 | 1084 | } |
05394f39 | 1085 | if (!obj->gtt_space) { |
75e9e915 | 1086 | ret = i915_gem_object_bind_to_gtt(obj, 0, true); |
c715089f CW |
1087 | if (ret) |
1088 | goto unlock; | |
de151cf6 | 1089 | |
e92d03bf EA |
1090 | ret = i915_gem_object_set_to_gtt_domain(obj, write); |
1091 | if (ret) | |
1092 | goto unlock; | |
1093 | } | |
4a684a41 | 1094 | |
74898d7e DV |
1095 | if (!obj->has_global_gtt_mapping) |
1096 | i915_gem_gtt_bind_object(obj, obj->cache_level); | |
1097 | ||
06d98131 | 1098 | ret = i915_gem_object_get_fence(obj); |
d9e86c0e CW |
1099 | if (ret) |
1100 | goto unlock; | |
de151cf6 | 1101 | |
05394f39 CW |
1102 | if (i915_gem_object_is_inactive(obj)) |
1103 | list_move_tail(&obj->mm_list, &dev_priv->mm.inactive_list); | |
7d1c4804 | 1104 | |
6299f992 CW |
1105 | obj->fault_mappable = true; |
1106 | ||
05394f39 | 1107 | pfn = ((dev->agp->base + obj->gtt_offset) >> PAGE_SHIFT) + |
de151cf6 JB |
1108 | page_offset; |
1109 | ||
1110 | /* Finally, remap it using the new GTT offset */ | |
1111 | ret = vm_insert_pfn(vma, (unsigned long)vmf->virtual_address, pfn); | |
c715089f | 1112 | unlock: |
de151cf6 | 1113 | mutex_unlock(&dev->struct_mutex); |
d9bc7e9f | 1114 | out: |
de151cf6 | 1115 | switch (ret) { |
d9bc7e9f | 1116 | case -EIO: |
045e769a | 1117 | case -EAGAIN: |
d9bc7e9f CW |
1118 | /* Give the error handler a chance to run and move the |
1119 | * objects off the GPU active list. Next time we service the | |
1120 | * fault, we should be able to transition the page into the | |
1121 | * GTT without touching the GPU (and so avoid further | |
1122 | * EIO/EGAIN). If the GPU is wedged, then there is no issue | |
1123 | * with coherency, just lost writes. | |
1124 | */ | |
045e769a | 1125 | set_need_resched(); |
c715089f CW |
1126 | case 0: |
1127 | case -ERESTARTSYS: | |
bed636ab | 1128 | case -EINTR: |
c715089f | 1129 | return VM_FAULT_NOPAGE; |
de151cf6 | 1130 | case -ENOMEM: |
de151cf6 | 1131 | return VM_FAULT_OOM; |
de151cf6 | 1132 | default: |
c715089f | 1133 | return VM_FAULT_SIGBUS; |
de151cf6 JB |
1134 | } |
1135 | } | |
1136 | ||
901782b2 CW |
1137 | /** |
1138 | * i915_gem_release_mmap - remove physical page mappings | |
1139 | * @obj: obj in question | |
1140 | * | |
af901ca1 | 1141 | * Preserve the reservation of the mmapping with the DRM core code, but |
901782b2 CW |
1142 | * relinquish ownership of the pages back to the system. |
1143 | * | |
1144 | * It is vital that we remove the page mapping if we have mapped a tiled | |
1145 | * object through the GTT and then lose the fence register due to | |
1146 | * resource pressure. Similarly if the object has been moved out of the | |
1147 | * aperture, than pages mapped into userspace must be revoked. Removing the | |
1148 | * mapping will then trigger a page fault on the next user access, allowing | |
1149 | * fixup by i915_gem_fault(). | |
1150 | */ | |
d05ca301 | 1151 | void |
05394f39 | 1152 | i915_gem_release_mmap(struct drm_i915_gem_object *obj) |
901782b2 | 1153 | { |
6299f992 CW |
1154 | if (!obj->fault_mappable) |
1155 | return; | |
901782b2 | 1156 | |
f6e47884 CW |
1157 | if (obj->base.dev->dev_mapping) |
1158 | unmap_mapping_range(obj->base.dev->dev_mapping, | |
1159 | (loff_t)obj->base.map_list.hash.key<<PAGE_SHIFT, | |
1160 | obj->base.size, 1); | |
fb7d516a | 1161 | |
6299f992 | 1162 | obj->fault_mappable = false; |
901782b2 CW |
1163 | } |
1164 | ||
92b88aeb | 1165 | static uint32_t |
e28f8711 | 1166 | i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode) |
92b88aeb | 1167 | { |
e28f8711 | 1168 | uint32_t gtt_size; |
92b88aeb CW |
1169 | |
1170 | if (INTEL_INFO(dev)->gen >= 4 || | |
e28f8711 CW |
1171 | tiling_mode == I915_TILING_NONE) |
1172 | return size; | |
92b88aeb CW |
1173 | |
1174 | /* Previous chips need a power-of-two fence region when tiling */ | |
1175 | if (INTEL_INFO(dev)->gen == 3) | |
e28f8711 | 1176 | gtt_size = 1024*1024; |
92b88aeb | 1177 | else |
e28f8711 | 1178 | gtt_size = 512*1024; |
92b88aeb | 1179 | |
e28f8711 CW |
1180 | while (gtt_size < size) |
1181 | gtt_size <<= 1; | |
92b88aeb | 1182 | |
e28f8711 | 1183 | return gtt_size; |
92b88aeb CW |
1184 | } |
1185 | ||
de151cf6 JB |
1186 | /** |
1187 | * i915_gem_get_gtt_alignment - return required GTT alignment for an object | |
1188 | * @obj: object to check | |
1189 | * | |
1190 | * Return the required GTT alignment for an object, taking into account | |
5e783301 | 1191 | * potential fence register mapping. |
de151cf6 JB |
1192 | */ |
1193 | static uint32_t | |
e28f8711 CW |
1194 | i915_gem_get_gtt_alignment(struct drm_device *dev, |
1195 | uint32_t size, | |
1196 | int tiling_mode) | |
de151cf6 | 1197 | { |
de151cf6 JB |
1198 | /* |
1199 | * Minimum alignment is 4k (GTT page size), but might be greater | |
1200 | * if a fence register is needed for the object. | |
1201 | */ | |
a00b10c3 | 1202 | if (INTEL_INFO(dev)->gen >= 4 || |
e28f8711 | 1203 | tiling_mode == I915_TILING_NONE) |
de151cf6 JB |
1204 | return 4096; |
1205 | ||
a00b10c3 CW |
1206 | /* |
1207 | * Previous chips need to be aligned to the size of the smallest | |
1208 | * fence register that can contain the object. | |
1209 | */ | |
e28f8711 | 1210 | return i915_gem_get_gtt_size(dev, size, tiling_mode); |
a00b10c3 CW |
1211 | } |
1212 | ||
5e783301 DV |
1213 | /** |
1214 | * i915_gem_get_unfenced_gtt_alignment - return required GTT alignment for an | |
1215 | * unfenced object | |
e28f8711 CW |
1216 | * @dev: the device |
1217 | * @size: size of the object | |
1218 | * @tiling_mode: tiling mode of the object | |
5e783301 DV |
1219 | * |
1220 | * Return the required GTT alignment for an object, only taking into account | |
1221 | * unfenced tiled surface requirements. | |
1222 | */ | |
467cffba | 1223 | uint32_t |
e28f8711 CW |
1224 | i915_gem_get_unfenced_gtt_alignment(struct drm_device *dev, |
1225 | uint32_t size, | |
1226 | int tiling_mode) | |
5e783301 | 1227 | { |
5e783301 DV |
1228 | /* |
1229 | * Minimum alignment is 4k (GTT page size) for sane hw. | |
1230 | */ | |
1231 | if (INTEL_INFO(dev)->gen >= 4 || IS_G33(dev) || | |
e28f8711 | 1232 | tiling_mode == I915_TILING_NONE) |
5e783301 DV |
1233 | return 4096; |
1234 | ||
e28f8711 CW |
1235 | /* Previous hardware however needs to be aligned to a power-of-two |
1236 | * tile height. The simplest method for determining this is to reuse | |
1237 | * the power-of-tile object size. | |
5e783301 | 1238 | */ |
e28f8711 | 1239 | return i915_gem_get_gtt_size(dev, size, tiling_mode); |
5e783301 DV |
1240 | } |
1241 | ||
de151cf6 | 1242 | int |
ff72145b DA |
1243 | i915_gem_mmap_gtt(struct drm_file *file, |
1244 | struct drm_device *dev, | |
1245 | uint32_t handle, | |
1246 | uint64_t *offset) | |
de151cf6 | 1247 | { |
da761a6e | 1248 | struct drm_i915_private *dev_priv = dev->dev_private; |
05394f39 | 1249 | struct drm_i915_gem_object *obj; |
de151cf6 JB |
1250 | int ret; |
1251 | ||
1252 | if (!(dev->driver->driver_features & DRIVER_GEM)) | |
1253 | return -ENODEV; | |
1254 | ||
76c1dec1 | 1255 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 1256 | if (ret) |
76c1dec1 | 1257 | return ret; |
de151cf6 | 1258 | |
ff72145b | 1259 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle)); |
c8725226 | 1260 | if (&obj->base == NULL) { |
1d7cfea1 CW |
1261 | ret = -ENOENT; |
1262 | goto unlock; | |
1263 | } | |
de151cf6 | 1264 | |
05394f39 | 1265 | if (obj->base.size > dev_priv->mm.gtt_mappable_end) { |
da761a6e | 1266 | ret = -E2BIG; |
ff56b0bc | 1267 | goto out; |
da761a6e CW |
1268 | } |
1269 | ||
05394f39 | 1270 | if (obj->madv != I915_MADV_WILLNEED) { |
ab18282d | 1271 | DRM_ERROR("Attempting to mmap a purgeable buffer\n"); |
1d7cfea1 CW |
1272 | ret = -EINVAL; |
1273 | goto out; | |
ab18282d CW |
1274 | } |
1275 | ||
05394f39 | 1276 | if (!obj->base.map_list.map) { |
b464e9a2 | 1277 | ret = drm_gem_create_mmap_offset(&obj->base); |
1d7cfea1 CW |
1278 | if (ret) |
1279 | goto out; | |
de151cf6 JB |
1280 | } |
1281 | ||
ff72145b | 1282 | *offset = (u64)obj->base.map_list.hash.key << PAGE_SHIFT; |
de151cf6 | 1283 | |
1d7cfea1 | 1284 | out: |
05394f39 | 1285 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 1286 | unlock: |
de151cf6 | 1287 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 1288 | return ret; |
de151cf6 JB |
1289 | } |
1290 | ||
ff72145b DA |
1291 | /** |
1292 | * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing | |
1293 | * @dev: DRM device | |
1294 | * @data: GTT mapping ioctl data | |
1295 | * @file: GEM object info | |
1296 | * | |
1297 | * Simply returns the fake offset to userspace so it can mmap it. | |
1298 | * The mmap call will end up in drm_gem_mmap(), which will set things | |
1299 | * up so we can get faults in the handler above. | |
1300 | * | |
1301 | * The fault handler will take care of binding the object into the GTT | |
1302 | * (since it may have been evicted to make room for something), allocating | |
1303 | * a fence register, and mapping the appropriate aperture address into | |
1304 | * userspace. | |
1305 | */ | |
1306 | int | |
1307 | i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data, | |
1308 | struct drm_file *file) | |
1309 | { | |
1310 | struct drm_i915_gem_mmap_gtt *args = data; | |
1311 | ||
1312 | if (!(dev->driver->driver_features & DRIVER_GEM)) | |
1313 | return -ENODEV; | |
1314 | ||
1315 | return i915_gem_mmap_gtt(file, dev, args->handle, &args->offset); | |
1316 | } | |
1317 | ||
1318 | ||
e5281ccd | 1319 | static int |
05394f39 | 1320 | i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj, |
e5281ccd CW |
1321 | gfp_t gfpmask) |
1322 | { | |
e5281ccd CW |
1323 | int page_count, i; |
1324 | struct address_space *mapping; | |
1325 | struct inode *inode; | |
1326 | struct page *page; | |
1327 | ||
1328 | /* Get the list of pages out of our struct file. They'll be pinned | |
1329 | * at this point until we release them. | |
1330 | */ | |
05394f39 CW |
1331 | page_count = obj->base.size / PAGE_SIZE; |
1332 | BUG_ON(obj->pages != NULL); | |
1333 | obj->pages = drm_malloc_ab(page_count, sizeof(struct page *)); | |
1334 | if (obj->pages == NULL) | |
e5281ccd CW |
1335 | return -ENOMEM; |
1336 | ||
05394f39 | 1337 | inode = obj->base.filp->f_path.dentry->d_inode; |
e5281ccd | 1338 | mapping = inode->i_mapping; |
5949eac4 HD |
1339 | gfpmask |= mapping_gfp_mask(mapping); |
1340 | ||
e5281ccd | 1341 | for (i = 0; i < page_count; i++) { |
5949eac4 | 1342 | page = shmem_read_mapping_page_gfp(mapping, i, gfpmask); |
e5281ccd CW |
1343 | if (IS_ERR(page)) |
1344 | goto err_pages; | |
1345 | ||
05394f39 | 1346 | obj->pages[i] = page; |
e5281ccd CW |
1347 | } |
1348 | ||
6dacfd2f | 1349 | if (i915_gem_object_needs_bit17_swizzle(obj)) |
e5281ccd CW |
1350 | i915_gem_object_do_bit_17_swizzle(obj); |
1351 | ||
1352 | return 0; | |
1353 | ||
1354 | err_pages: | |
1355 | while (i--) | |
05394f39 | 1356 | page_cache_release(obj->pages[i]); |
e5281ccd | 1357 | |
05394f39 CW |
1358 | drm_free_large(obj->pages); |
1359 | obj->pages = NULL; | |
e5281ccd CW |
1360 | return PTR_ERR(page); |
1361 | } | |
1362 | ||
5cdf5881 | 1363 | static void |
05394f39 | 1364 | i915_gem_object_put_pages_gtt(struct drm_i915_gem_object *obj) |
673a394b | 1365 | { |
05394f39 | 1366 | int page_count = obj->base.size / PAGE_SIZE; |
673a394b EA |
1367 | int i; |
1368 | ||
05394f39 | 1369 | BUG_ON(obj->madv == __I915_MADV_PURGED); |
673a394b | 1370 | |
6dacfd2f | 1371 | if (i915_gem_object_needs_bit17_swizzle(obj)) |
280b713b EA |
1372 | i915_gem_object_save_bit_17_swizzle(obj); |
1373 | ||
05394f39 CW |
1374 | if (obj->madv == I915_MADV_DONTNEED) |
1375 | obj->dirty = 0; | |
3ef94daa CW |
1376 | |
1377 | for (i = 0; i < page_count; i++) { | |
05394f39 CW |
1378 | if (obj->dirty) |
1379 | set_page_dirty(obj->pages[i]); | |
3ef94daa | 1380 | |
05394f39 CW |
1381 | if (obj->madv == I915_MADV_WILLNEED) |
1382 | mark_page_accessed(obj->pages[i]); | |
3ef94daa | 1383 | |
05394f39 | 1384 | page_cache_release(obj->pages[i]); |
3ef94daa | 1385 | } |
05394f39 | 1386 | obj->dirty = 0; |
673a394b | 1387 | |
05394f39 CW |
1388 | drm_free_large(obj->pages); |
1389 | obj->pages = NULL; | |
673a394b EA |
1390 | } |
1391 | ||
54cf91dc | 1392 | void |
05394f39 | 1393 | i915_gem_object_move_to_active(struct drm_i915_gem_object *obj, |
1ec14ad3 CW |
1394 | struct intel_ring_buffer *ring, |
1395 | u32 seqno) | |
673a394b | 1396 | { |
05394f39 | 1397 | struct drm_device *dev = obj->base.dev; |
69dc4987 | 1398 | struct drm_i915_private *dev_priv = dev->dev_private; |
617dbe27 | 1399 | |
852835f3 | 1400 | BUG_ON(ring == NULL); |
05394f39 | 1401 | obj->ring = ring; |
673a394b EA |
1402 | |
1403 | /* Add a reference if we're newly entering the active list. */ | |
05394f39 CW |
1404 | if (!obj->active) { |
1405 | drm_gem_object_reference(&obj->base); | |
1406 | obj->active = 1; | |
673a394b | 1407 | } |
e35a41de | 1408 | |
673a394b | 1409 | /* Move from whatever list we were on to the tail of execution. */ |
05394f39 CW |
1410 | list_move_tail(&obj->mm_list, &dev_priv->mm.active_list); |
1411 | list_move_tail(&obj->ring_list, &ring->active_list); | |
caea7476 | 1412 | |
05394f39 | 1413 | obj->last_rendering_seqno = seqno; |
caea7476 | 1414 | |
7dd49065 | 1415 | if (obj->fenced_gpu_access) { |
caea7476 | 1416 | obj->last_fenced_seqno = seqno; |
caea7476 | 1417 | |
7dd49065 CW |
1418 | /* Bump MRU to take account of the delayed flush */ |
1419 | if (obj->fence_reg != I915_FENCE_REG_NONE) { | |
1420 | struct drm_i915_fence_reg *reg; | |
1421 | ||
1422 | reg = &dev_priv->fence_regs[obj->fence_reg]; | |
1423 | list_move_tail(®->lru_list, | |
1424 | &dev_priv->mm.fence_list); | |
1425 | } | |
caea7476 CW |
1426 | } |
1427 | } | |
1428 | ||
1429 | static void | |
1430 | i915_gem_object_move_off_active(struct drm_i915_gem_object *obj) | |
1431 | { | |
1432 | list_del_init(&obj->ring_list); | |
1433 | obj->last_rendering_seqno = 0; | |
15a13bbd | 1434 | obj->last_fenced_seqno = 0; |
673a394b EA |
1435 | } |
1436 | ||
ce44b0ea | 1437 | static void |
05394f39 | 1438 | i915_gem_object_move_to_flushing(struct drm_i915_gem_object *obj) |
ce44b0ea | 1439 | { |
05394f39 | 1440 | struct drm_device *dev = obj->base.dev; |
ce44b0ea | 1441 | drm_i915_private_t *dev_priv = dev->dev_private; |
ce44b0ea | 1442 | |
05394f39 CW |
1443 | BUG_ON(!obj->active); |
1444 | list_move_tail(&obj->mm_list, &dev_priv->mm.flushing_list); | |
caea7476 CW |
1445 | |
1446 | i915_gem_object_move_off_active(obj); | |
1447 | } | |
1448 | ||
1449 | static void | |
1450 | i915_gem_object_move_to_inactive(struct drm_i915_gem_object *obj) | |
1451 | { | |
1452 | struct drm_device *dev = obj->base.dev; | |
1453 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1454 | ||
1455 | if (obj->pin_count != 0) | |
1456 | list_move_tail(&obj->mm_list, &dev_priv->mm.pinned_list); | |
1457 | else | |
1458 | list_move_tail(&obj->mm_list, &dev_priv->mm.inactive_list); | |
1459 | ||
1460 | BUG_ON(!list_empty(&obj->gpu_write_list)); | |
1461 | BUG_ON(!obj->active); | |
1462 | obj->ring = NULL; | |
1463 | ||
1464 | i915_gem_object_move_off_active(obj); | |
1465 | obj->fenced_gpu_access = false; | |
caea7476 CW |
1466 | |
1467 | obj->active = 0; | |
87ca9c8a | 1468 | obj->pending_gpu_write = false; |
caea7476 CW |
1469 | drm_gem_object_unreference(&obj->base); |
1470 | ||
1471 | WARN_ON(i915_verify_lists(dev)); | |
ce44b0ea | 1472 | } |
673a394b | 1473 | |
963b4836 CW |
1474 | /* Immediately discard the backing storage */ |
1475 | static void | |
05394f39 | 1476 | i915_gem_object_truncate(struct drm_i915_gem_object *obj) |
963b4836 | 1477 | { |
bb6baf76 | 1478 | struct inode *inode; |
963b4836 | 1479 | |
ae9fed6b CW |
1480 | /* Our goal here is to return as much of the memory as |
1481 | * is possible back to the system as we are called from OOM. | |
1482 | * To do this we must instruct the shmfs to drop all of its | |
e2377fe0 | 1483 | * backing pages, *now*. |
ae9fed6b | 1484 | */ |
05394f39 | 1485 | inode = obj->base.filp->f_path.dentry->d_inode; |
e2377fe0 | 1486 | shmem_truncate_range(inode, 0, (loff_t)-1); |
bb6baf76 | 1487 | |
a14917ee CW |
1488 | if (obj->base.map_list.map) |
1489 | drm_gem_free_mmap_offset(&obj->base); | |
1490 | ||
05394f39 | 1491 | obj->madv = __I915_MADV_PURGED; |
963b4836 CW |
1492 | } |
1493 | ||
1494 | static inline int | |
05394f39 | 1495 | i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj) |
963b4836 | 1496 | { |
05394f39 | 1497 | return obj->madv == I915_MADV_DONTNEED; |
963b4836 CW |
1498 | } |
1499 | ||
63560396 | 1500 | static void |
db53a302 CW |
1501 | i915_gem_process_flushing_list(struct intel_ring_buffer *ring, |
1502 | uint32_t flush_domains) | |
63560396 | 1503 | { |
05394f39 | 1504 | struct drm_i915_gem_object *obj, *next; |
63560396 | 1505 | |
05394f39 | 1506 | list_for_each_entry_safe(obj, next, |
64193406 | 1507 | &ring->gpu_write_list, |
63560396 | 1508 | gpu_write_list) { |
05394f39 CW |
1509 | if (obj->base.write_domain & flush_domains) { |
1510 | uint32_t old_write_domain = obj->base.write_domain; | |
63560396 | 1511 | |
05394f39 CW |
1512 | obj->base.write_domain = 0; |
1513 | list_del_init(&obj->gpu_write_list); | |
1ec14ad3 | 1514 | i915_gem_object_move_to_active(obj, ring, |
db53a302 | 1515 | i915_gem_next_request_seqno(ring)); |
63560396 | 1516 | |
63560396 | 1517 | trace_i915_gem_object_change_domain(obj, |
05394f39 | 1518 | obj->base.read_domains, |
63560396 DV |
1519 | old_write_domain); |
1520 | } | |
1521 | } | |
1522 | } | |
8187a2b7 | 1523 | |
53d227f2 DV |
1524 | static u32 |
1525 | i915_gem_get_seqno(struct drm_device *dev) | |
1526 | { | |
1527 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1528 | u32 seqno = dev_priv->next_seqno; | |
1529 | ||
1530 | /* reserve 0 for non-seqno */ | |
1531 | if (++dev_priv->next_seqno == 0) | |
1532 | dev_priv->next_seqno = 1; | |
1533 | ||
1534 | return seqno; | |
1535 | } | |
1536 | ||
1537 | u32 | |
1538 | i915_gem_next_request_seqno(struct intel_ring_buffer *ring) | |
1539 | { | |
1540 | if (ring->outstanding_lazy_request == 0) | |
1541 | ring->outstanding_lazy_request = i915_gem_get_seqno(ring->dev); | |
1542 | ||
1543 | return ring->outstanding_lazy_request; | |
1544 | } | |
1545 | ||
3cce469c | 1546 | int |
db53a302 | 1547 | i915_add_request(struct intel_ring_buffer *ring, |
f787a5f5 | 1548 | struct drm_file *file, |
db53a302 | 1549 | struct drm_i915_gem_request *request) |
673a394b | 1550 | { |
db53a302 | 1551 | drm_i915_private_t *dev_priv = ring->dev->dev_private; |
673a394b | 1552 | uint32_t seqno; |
a71d8d94 | 1553 | u32 request_ring_position; |
673a394b | 1554 | int was_empty; |
3cce469c CW |
1555 | int ret; |
1556 | ||
1557 | BUG_ON(request == NULL); | |
53d227f2 | 1558 | seqno = i915_gem_next_request_seqno(ring); |
673a394b | 1559 | |
a71d8d94 CW |
1560 | /* Record the position of the start of the request so that |
1561 | * should we detect the updated seqno part-way through the | |
1562 | * GPU processing the request, we never over-estimate the | |
1563 | * position of the head. | |
1564 | */ | |
1565 | request_ring_position = intel_ring_get_tail(ring); | |
1566 | ||
3cce469c CW |
1567 | ret = ring->add_request(ring, &seqno); |
1568 | if (ret) | |
1569 | return ret; | |
673a394b | 1570 | |
db53a302 | 1571 | trace_i915_gem_request_add(ring, seqno); |
673a394b EA |
1572 | |
1573 | request->seqno = seqno; | |
852835f3 | 1574 | request->ring = ring; |
a71d8d94 | 1575 | request->tail = request_ring_position; |
673a394b | 1576 | request->emitted_jiffies = jiffies; |
852835f3 ZN |
1577 | was_empty = list_empty(&ring->request_list); |
1578 | list_add_tail(&request->list, &ring->request_list); | |
1579 | ||
db53a302 CW |
1580 | if (file) { |
1581 | struct drm_i915_file_private *file_priv = file->driver_priv; | |
1582 | ||
1c25595f | 1583 | spin_lock(&file_priv->mm.lock); |
f787a5f5 | 1584 | request->file_priv = file_priv; |
b962442e | 1585 | list_add_tail(&request->client_list, |
f787a5f5 | 1586 | &file_priv->mm.request_list); |
1c25595f | 1587 | spin_unlock(&file_priv->mm.lock); |
b962442e | 1588 | } |
673a394b | 1589 | |
5391d0cf | 1590 | ring->outstanding_lazy_request = 0; |
db53a302 | 1591 | |
f65d9421 | 1592 | if (!dev_priv->mm.suspended) { |
3e0dc6b0 BW |
1593 | if (i915_enable_hangcheck) { |
1594 | mod_timer(&dev_priv->hangcheck_timer, | |
1595 | jiffies + | |
1596 | msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)); | |
1597 | } | |
f65d9421 | 1598 | if (was_empty) |
b3b079db CW |
1599 | queue_delayed_work(dev_priv->wq, |
1600 | &dev_priv->mm.retire_work, HZ); | |
f65d9421 | 1601 | } |
3cce469c | 1602 | return 0; |
673a394b EA |
1603 | } |
1604 | ||
f787a5f5 CW |
1605 | static inline void |
1606 | i915_gem_request_remove_from_client(struct drm_i915_gem_request *request) | |
673a394b | 1607 | { |
1c25595f | 1608 | struct drm_i915_file_private *file_priv = request->file_priv; |
673a394b | 1609 | |
1c25595f CW |
1610 | if (!file_priv) |
1611 | return; | |
1c5d22f7 | 1612 | |
1c25595f | 1613 | spin_lock(&file_priv->mm.lock); |
09bfa517 HRK |
1614 | if (request->file_priv) { |
1615 | list_del(&request->client_list); | |
1616 | request->file_priv = NULL; | |
1617 | } | |
1c25595f | 1618 | spin_unlock(&file_priv->mm.lock); |
673a394b | 1619 | } |
673a394b | 1620 | |
dfaae392 CW |
1621 | static void i915_gem_reset_ring_lists(struct drm_i915_private *dev_priv, |
1622 | struct intel_ring_buffer *ring) | |
9375e446 | 1623 | { |
dfaae392 CW |
1624 | while (!list_empty(&ring->request_list)) { |
1625 | struct drm_i915_gem_request *request; | |
673a394b | 1626 | |
dfaae392 CW |
1627 | request = list_first_entry(&ring->request_list, |
1628 | struct drm_i915_gem_request, | |
1629 | list); | |
de151cf6 | 1630 | |
dfaae392 | 1631 | list_del(&request->list); |
f787a5f5 | 1632 | i915_gem_request_remove_from_client(request); |
dfaae392 CW |
1633 | kfree(request); |
1634 | } | |
673a394b | 1635 | |
dfaae392 | 1636 | while (!list_empty(&ring->active_list)) { |
05394f39 | 1637 | struct drm_i915_gem_object *obj; |
9375e446 | 1638 | |
05394f39 CW |
1639 | obj = list_first_entry(&ring->active_list, |
1640 | struct drm_i915_gem_object, | |
1641 | ring_list); | |
9375e446 | 1642 | |
05394f39 CW |
1643 | obj->base.write_domain = 0; |
1644 | list_del_init(&obj->gpu_write_list); | |
1645 | i915_gem_object_move_to_inactive(obj); | |
673a394b EA |
1646 | } |
1647 | } | |
1648 | ||
312817a3 CW |
1649 | static void i915_gem_reset_fences(struct drm_device *dev) |
1650 | { | |
1651 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1652 | int i; | |
1653 | ||
4b9de737 | 1654 | for (i = 0; i < dev_priv->num_fence_regs; i++) { |
312817a3 | 1655 | struct drm_i915_fence_reg *reg = &dev_priv->fence_regs[i]; |
7d2cb39c | 1656 | |
ada726c7 | 1657 | i915_gem_write_fence(dev, i, NULL); |
7d2cb39c | 1658 | |
ada726c7 CW |
1659 | if (reg->obj) |
1660 | i915_gem_object_fence_lost(reg->obj); | |
7d2cb39c | 1661 | |
ada726c7 CW |
1662 | reg->pin_count = 0; |
1663 | reg->obj = NULL; | |
1664 | INIT_LIST_HEAD(®->lru_list); | |
312817a3 | 1665 | } |
ada726c7 CW |
1666 | |
1667 | INIT_LIST_HEAD(&dev_priv->mm.fence_list); | |
312817a3 CW |
1668 | } |
1669 | ||
069efc1d | 1670 | void i915_gem_reset(struct drm_device *dev) |
673a394b | 1671 | { |
77f01230 | 1672 | struct drm_i915_private *dev_priv = dev->dev_private; |
05394f39 | 1673 | struct drm_i915_gem_object *obj; |
1ec14ad3 | 1674 | int i; |
673a394b | 1675 | |
1ec14ad3 CW |
1676 | for (i = 0; i < I915_NUM_RINGS; i++) |
1677 | i915_gem_reset_ring_lists(dev_priv, &dev_priv->ring[i]); | |
dfaae392 CW |
1678 | |
1679 | /* Remove anything from the flushing lists. The GPU cache is likely | |
1680 | * to be lost on reset along with the data, so simply move the | |
1681 | * lost bo to the inactive list. | |
1682 | */ | |
1683 | while (!list_empty(&dev_priv->mm.flushing_list)) { | |
0206e353 | 1684 | obj = list_first_entry(&dev_priv->mm.flushing_list, |
05394f39 CW |
1685 | struct drm_i915_gem_object, |
1686 | mm_list); | |
dfaae392 | 1687 | |
05394f39 CW |
1688 | obj->base.write_domain = 0; |
1689 | list_del_init(&obj->gpu_write_list); | |
1690 | i915_gem_object_move_to_inactive(obj); | |
dfaae392 CW |
1691 | } |
1692 | ||
1693 | /* Move everything out of the GPU domains to ensure we do any | |
1694 | * necessary invalidation upon reuse. | |
1695 | */ | |
05394f39 | 1696 | list_for_each_entry(obj, |
77f01230 | 1697 | &dev_priv->mm.inactive_list, |
69dc4987 | 1698 | mm_list) |
77f01230 | 1699 | { |
05394f39 | 1700 | obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS; |
77f01230 | 1701 | } |
069efc1d CW |
1702 | |
1703 | /* The fence registers are invalidated so clear them out */ | |
312817a3 | 1704 | i915_gem_reset_fences(dev); |
673a394b EA |
1705 | } |
1706 | ||
1707 | /** | |
1708 | * This function clears the request list as sequence numbers are passed. | |
1709 | */ | |
a71d8d94 | 1710 | void |
db53a302 | 1711 | i915_gem_retire_requests_ring(struct intel_ring_buffer *ring) |
673a394b | 1712 | { |
673a394b | 1713 | uint32_t seqno; |
1ec14ad3 | 1714 | int i; |
673a394b | 1715 | |
db53a302 | 1716 | if (list_empty(&ring->request_list)) |
6c0594a3 KW |
1717 | return; |
1718 | ||
db53a302 | 1719 | WARN_ON(i915_verify_lists(ring->dev)); |
673a394b | 1720 | |
78501eac | 1721 | seqno = ring->get_seqno(ring); |
1ec14ad3 | 1722 | |
076e2c0e | 1723 | for (i = 0; i < ARRAY_SIZE(ring->sync_seqno); i++) |
1ec14ad3 CW |
1724 | if (seqno >= ring->sync_seqno[i]) |
1725 | ring->sync_seqno[i] = 0; | |
1726 | ||
852835f3 | 1727 | while (!list_empty(&ring->request_list)) { |
673a394b | 1728 | struct drm_i915_gem_request *request; |
673a394b | 1729 | |
852835f3 | 1730 | request = list_first_entry(&ring->request_list, |
673a394b EA |
1731 | struct drm_i915_gem_request, |
1732 | list); | |
673a394b | 1733 | |
dfaae392 | 1734 | if (!i915_seqno_passed(seqno, request->seqno)) |
b84d5f0c CW |
1735 | break; |
1736 | ||
db53a302 | 1737 | trace_i915_gem_request_retire(ring, request->seqno); |
a71d8d94 CW |
1738 | /* We know the GPU must have read the request to have |
1739 | * sent us the seqno + interrupt, so use the position | |
1740 | * of tail of the request to update the last known position | |
1741 | * of the GPU head. | |
1742 | */ | |
1743 | ring->last_retired_head = request->tail; | |
b84d5f0c CW |
1744 | |
1745 | list_del(&request->list); | |
f787a5f5 | 1746 | i915_gem_request_remove_from_client(request); |
b84d5f0c CW |
1747 | kfree(request); |
1748 | } | |
673a394b | 1749 | |
b84d5f0c CW |
1750 | /* Move any buffers on the active list that are no longer referenced |
1751 | * by the ringbuffer to the flushing/inactive lists as appropriate. | |
1752 | */ | |
1753 | while (!list_empty(&ring->active_list)) { | |
05394f39 | 1754 | struct drm_i915_gem_object *obj; |
b84d5f0c | 1755 | |
0206e353 | 1756 | obj = list_first_entry(&ring->active_list, |
05394f39 CW |
1757 | struct drm_i915_gem_object, |
1758 | ring_list); | |
673a394b | 1759 | |
05394f39 | 1760 | if (!i915_seqno_passed(seqno, obj->last_rendering_seqno)) |
673a394b | 1761 | break; |
b84d5f0c | 1762 | |
05394f39 | 1763 | if (obj->base.write_domain != 0) |
b84d5f0c CW |
1764 | i915_gem_object_move_to_flushing(obj); |
1765 | else | |
1766 | i915_gem_object_move_to_inactive(obj); | |
673a394b | 1767 | } |
9d34e5db | 1768 | |
db53a302 CW |
1769 | if (unlikely(ring->trace_irq_seqno && |
1770 | i915_seqno_passed(seqno, ring->trace_irq_seqno))) { | |
1ec14ad3 | 1771 | ring->irq_put(ring); |
db53a302 | 1772 | ring->trace_irq_seqno = 0; |
9d34e5db | 1773 | } |
23bc5982 | 1774 | |
db53a302 | 1775 | WARN_ON(i915_verify_lists(ring->dev)); |
673a394b EA |
1776 | } |
1777 | ||
b09a1fec CW |
1778 | void |
1779 | i915_gem_retire_requests(struct drm_device *dev) | |
1780 | { | |
1781 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1ec14ad3 | 1782 | int i; |
b09a1fec | 1783 | |
be72615b | 1784 | if (!list_empty(&dev_priv->mm.deferred_free_list)) { |
05394f39 | 1785 | struct drm_i915_gem_object *obj, *next; |
be72615b CW |
1786 | |
1787 | /* We must be careful that during unbind() we do not | |
1788 | * accidentally infinitely recurse into retire requests. | |
1789 | * Currently: | |
1790 | * retire -> free -> unbind -> wait -> retire_ring | |
1791 | */ | |
05394f39 | 1792 | list_for_each_entry_safe(obj, next, |
be72615b | 1793 | &dev_priv->mm.deferred_free_list, |
69dc4987 | 1794 | mm_list) |
05394f39 | 1795 | i915_gem_free_object_tail(obj); |
be72615b CW |
1796 | } |
1797 | ||
1ec14ad3 | 1798 | for (i = 0; i < I915_NUM_RINGS; i++) |
db53a302 | 1799 | i915_gem_retire_requests_ring(&dev_priv->ring[i]); |
b09a1fec CW |
1800 | } |
1801 | ||
75ef9da2 | 1802 | static void |
673a394b EA |
1803 | i915_gem_retire_work_handler(struct work_struct *work) |
1804 | { | |
1805 | drm_i915_private_t *dev_priv; | |
1806 | struct drm_device *dev; | |
0a58705b CW |
1807 | bool idle; |
1808 | int i; | |
673a394b EA |
1809 | |
1810 | dev_priv = container_of(work, drm_i915_private_t, | |
1811 | mm.retire_work.work); | |
1812 | dev = dev_priv->dev; | |
1813 | ||
891b48cf CW |
1814 | /* Come back later if the device is busy... */ |
1815 | if (!mutex_trylock(&dev->struct_mutex)) { | |
1816 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ); | |
1817 | return; | |
1818 | } | |
1819 | ||
b09a1fec | 1820 | i915_gem_retire_requests(dev); |
d1b851fc | 1821 | |
0a58705b CW |
1822 | /* Send a periodic flush down the ring so we don't hold onto GEM |
1823 | * objects indefinitely. | |
1824 | */ | |
1825 | idle = true; | |
1826 | for (i = 0; i < I915_NUM_RINGS; i++) { | |
1827 | struct intel_ring_buffer *ring = &dev_priv->ring[i]; | |
1828 | ||
1829 | if (!list_empty(&ring->gpu_write_list)) { | |
1830 | struct drm_i915_gem_request *request; | |
1831 | int ret; | |
1832 | ||
db53a302 CW |
1833 | ret = i915_gem_flush_ring(ring, |
1834 | 0, I915_GEM_GPU_DOMAINS); | |
0a58705b CW |
1835 | request = kzalloc(sizeof(*request), GFP_KERNEL); |
1836 | if (ret || request == NULL || | |
db53a302 | 1837 | i915_add_request(ring, NULL, request)) |
0a58705b CW |
1838 | kfree(request); |
1839 | } | |
1840 | ||
1841 | idle &= list_empty(&ring->request_list); | |
1842 | } | |
1843 | ||
1844 | if (!dev_priv->mm.suspended && !idle) | |
9c9fe1f8 | 1845 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ); |
0a58705b | 1846 | |
673a394b EA |
1847 | mutex_unlock(&dev->struct_mutex); |
1848 | } | |
1849 | ||
db53a302 CW |
1850 | /** |
1851 | * Waits for a sequence number to be signaled, and cleans up the | |
1852 | * request and object lists appropriately for that event. | |
1853 | */ | |
5a5a0c64 | 1854 | int |
db53a302 | 1855 | i915_wait_request(struct intel_ring_buffer *ring, |
b93f9cf1 BW |
1856 | uint32_t seqno, |
1857 | bool do_retire) | |
673a394b | 1858 | { |
db53a302 | 1859 | drm_i915_private_t *dev_priv = ring->dev->dev_private; |
802c7eb6 | 1860 | u32 ier; |
673a394b EA |
1861 | int ret = 0; |
1862 | ||
1863 | BUG_ON(seqno == 0); | |
1864 | ||
d9bc7e9f CW |
1865 | if (atomic_read(&dev_priv->mm.wedged)) { |
1866 | struct completion *x = &dev_priv->error_completion; | |
1867 | bool recovery_complete; | |
1868 | unsigned long flags; | |
1869 | ||
1870 | /* Give the error handler a chance to run. */ | |
1871 | spin_lock_irqsave(&x->wait.lock, flags); | |
1872 | recovery_complete = x->done > 0; | |
1873 | spin_unlock_irqrestore(&x->wait.lock, flags); | |
1874 | ||
1875 | return recovery_complete ? -EIO : -EAGAIN; | |
1876 | } | |
30dbf0c0 | 1877 | |
5d97eb69 | 1878 | if (seqno == ring->outstanding_lazy_request) { |
3cce469c CW |
1879 | struct drm_i915_gem_request *request; |
1880 | ||
1881 | request = kzalloc(sizeof(*request), GFP_KERNEL); | |
1882 | if (request == NULL) | |
e35a41de | 1883 | return -ENOMEM; |
3cce469c | 1884 | |
db53a302 | 1885 | ret = i915_add_request(ring, NULL, request); |
3cce469c CW |
1886 | if (ret) { |
1887 | kfree(request); | |
1888 | return ret; | |
1889 | } | |
1890 | ||
1891 | seqno = request->seqno; | |
e35a41de | 1892 | } |
ffed1d09 | 1893 | |
78501eac | 1894 | if (!i915_seqno_passed(ring->get_seqno(ring), seqno)) { |
db53a302 | 1895 | if (HAS_PCH_SPLIT(ring->dev)) |
036a4a7d | 1896 | ier = I915_READ(DEIER) | I915_READ(GTIER); |
23e3f9b3 JB |
1897 | else if (IS_VALLEYVIEW(ring->dev)) |
1898 | ier = I915_READ(GTIER) | I915_READ(VLV_IER); | |
036a4a7d ZW |
1899 | else |
1900 | ier = I915_READ(IER); | |
802c7eb6 JB |
1901 | if (!ier) { |
1902 | DRM_ERROR("something (likely vbetool) disabled " | |
1903 | "interrupts, re-enabling\n"); | |
f01c22fd CW |
1904 | ring->dev->driver->irq_preinstall(ring->dev); |
1905 | ring->dev->driver->irq_postinstall(ring->dev); | |
802c7eb6 JB |
1906 | } |
1907 | ||
db53a302 | 1908 | trace_i915_gem_request_wait_begin(ring, seqno); |
1c5d22f7 | 1909 | |
b2223497 | 1910 | ring->waiting_seqno = seqno; |
b13c2b96 | 1911 | if (ring->irq_get(ring)) { |
ce453d81 | 1912 | if (dev_priv->mm.interruptible) |
b13c2b96 CW |
1913 | ret = wait_event_interruptible(ring->irq_queue, |
1914 | i915_seqno_passed(ring->get_seqno(ring), seqno) | |
1915 | || atomic_read(&dev_priv->mm.wedged)); | |
1916 | else | |
1917 | wait_event(ring->irq_queue, | |
1918 | i915_seqno_passed(ring->get_seqno(ring), seqno) | |
1919 | || atomic_read(&dev_priv->mm.wedged)); | |
1920 | ||
1921 | ring->irq_put(ring); | |
e959b5db EA |
1922 | } else if (wait_for_atomic(i915_seqno_passed(ring->get_seqno(ring), |
1923 | seqno) || | |
1924 | atomic_read(&dev_priv->mm.wedged), 3000)) | |
b5ba177d | 1925 | ret = -EBUSY; |
b2223497 | 1926 | ring->waiting_seqno = 0; |
1c5d22f7 | 1927 | |
db53a302 | 1928 | trace_i915_gem_request_wait_end(ring, seqno); |
673a394b | 1929 | } |
ba1234d1 | 1930 | if (atomic_read(&dev_priv->mm.wedged)) |
30dbf0c0 | 1931 | ret = -EAGAIN; |
673a394b | 1932 | |
673a394b EA |
1933 | /* Directly dispatch request retiring. While we have the work queue |
1934 | * to handle this, the waiter on a request often wants an associated | |
1935 | * buffer to have made it to the inactive list, and we would need | |
1936 | * a separate wait queue to handle that. | |
1937 | */ | |
b93f9cf1 | 1938 | if (ret == 0 && do_retire) |
db53a302 | 1939 | i915_gem_retire_requests_ring(ring); |
673a394b EA |
1940 | |
1941 | return ret; | |
1942 | } | |
1943 | ||
673a394b EA |
1944 | /** |
1945 | * Ensures that all rendering to the object has completed and the object is | |
1946 | * safe to unbind from the GTT or access from the CPU. | |
1947 | */ | |
54cf91dc | 1948 | int |
ce453d81 | 1949 | i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj) |
673a394b | 1950 | { |
673a394b EA |
1951 | int ret; |
1952 | ||
e47c68e9 EA |
1953 | /* This function only exists to support waiting for existing rendering, |
1954 | * not for emitting required flushes. | |
673a394b | 1955 | */ |
05394f39 | 1956 | BUG_ON((obj->base.write_domain & I915_GEM_GPU_DOMAINS) != 0); |
673a394b EA |
1957 | |
1958 | /* If there is rendering queued on the buffer being evicted, wait for | |
1959 | * it. | |
1960 | */ | |
05394f39 | 1961 | if (obj->active) { |
b93f9cf1 BW |
1962 | ret = i915_wait_request(obj->ring, obj->last_rendering_seqno, |
1963 | true); | |
2cf34d7b | 1964 | if (ret) |
673a394b EA |
1965 | return ret; |
1966 | } | |
1967 | ||
1968 | return 0; | |
1969 | } | |
1970 | ||
5816d648 BW |
1971 | /** |
1972 | * i915_gem_object_sync - sync an object to a ring. | |
1973 | * | |
1974 | * @obj: object which may be in use on another ring. | |
1975 | * @to: ring we wish to use the object on. May be NULL. | |
1976 | * | |
1977 | * This code is meant to abstract object synchronization with the GPU. | |
1978 | * Calling with NULL implies synchronizing the object with the CPU | |
1979 | * rather than a particular GPU ring. | |
1980 | * | |
1981 | * Returns 0 if successful, else propagates up the lower layer error. | |
1982 | */ | |
2911a35b BW |
1983 | int |
1984 | i915_gem_object_sync(struct drm_i915_gem_object *obj, | |
1985 | struct intel_ring_buffer *to) | |
1986 | { | |
1987 | struct intel_ring_buffer *from = obj->ring; | |
1988 | u32 seqno; | |
1989 | int ret, idx; | |
1990 | ||
1991 | if (from == NULL || to == from) | |
1992 | return 0; | |
1993 | ||
5816d648 | 1994 | if (to == NULL || !i915_semaphore_is_enabled(obj->base.dev)) |
2911a35b BW |
1995 | return i915_gem_object_wait_rendering(obj); |
1996 | ||
1997 | idx = intel_ring_sync_index(from, to); | |
1998 | ||
1999 | seqno = obj->last_rendering_seqno; | |
2000 | if (seqno <= from->sync_seqno[idx]) | |
2001 | return 0; | |
2002 | ||
2003 | if (seqno == from->outstanding_lazy_request) { | |
2004 | struct drm_i915_gem_request *request; | |
2005 | ||
2006 | request = kzalloc(sizeof(*request), GFP_KERNEL); | |
2007 | if (request == NULL) | |
2008 | return -ENOMEM; | |
2009 | ||
2010 | ret = i915_add_request(from, NULL, request); | |
2011 | if (ret) { | |
2012 | kfree(request); | |
2013 | return ret; | |
2014 | } | |
2015 | ||
2016 | seqno = request->seqno; | |
2017 | } | |
2018 | ||
2911a35b | 2019 | |
1500f7ea | 2020 | ret = to->sync_to(to, from, seqno); |
e3a5a225 BW |
2021 | if (!ret) |
2022 | from->sync_seqno[idx] = seqno; | |
2911a35b | 2023 | |
e3a5a225 | 2024 | return ret; |
2911a35b BW |
2025 | } |
2026 | ||
b5ffc9bc CW |
2027 | static void i915_gem_object_finish_gtt(struct drm_i915_gem_object *obj) |
2028 | { | |
2029 | u32 old_write_domain, old_read_domains; | |
2030 | ||
b5ffc9bc CW |
2031 | /* Act a barrier for all accesses through the GTT */ |
2032 | mb(); | |
2033 | ||
2034 | /* Force a pagefault for domain tracking on next user access */ | |
2035 | i915_gem_release_mmap(obj); | |
2036 | ||
b97c3d9c KP |
2037 | if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0) |
2038 | return; | |
2039 | ||
b5ffc9bc CW |
2040 | old_read_domains = obj->base.read_domains; |
2041 | old_write_domain = obj->base.write_domain; | |
2042 | ||
2043 | obj->base.read_domains &= ~I915_GEM_DOMAIN_GTT; | |
2044 | obj->base.write_domain &= ~I915_GEM_DOMAIN_GTT; | |
2045 | ||
2046 | trace_i915_gem_object_change_domain(obj, | |
2047 | old_read_domains, | |
2048 | old_write_domain); | |
2049 | } | |
2050 | ||
673a394b EA |
2051 | /** |
2052 | * Unbinds an object from the GTT aperture. | |
2053 | */ | |
0f973f27 | 2054 | int |
05394f39 | 2055 | i915_gem_object_unbind(struct drm_i915_gem_object *obj) |
673a394b | 2056 | { |
7bddb01f | 2057 | drm_i915_private_t *dev_priv = obj->base.dev->dev_private; |
673a394b EA |
2058 | int ret = 0; |
2059 | ||
05394f39 | 2060 | if (obj->gtt_space == NULL) |
673a394b EA |
2061 | return 0; |
2062 | ||
05394f39 | 2063 | if (obj->pin_count != 0) { |
673a394b EA |
2064 | DRM_ERROR("Attempting to unbind pinned buffer\n"); |
2065 | return -EINVAL; | |
2066 | } | |
2067 | ||
a8198eea CW |
2068 | ret = i915_gem_object_finish_gpu(obj); |
2069 | if (ret == -ERESTARTSYS) | |
2070 | return ret; | |
2071 | /* Continue on if we fail due to EIO, the GPU is hung so we | |
2072 | * should be safe and we need to cleanup or else we might | |
2073 | * cause memory corruption through use-after-free. | |
2074 | */ | |
2075 | ||
b5ffc9bc | 2076 | i915_gem_object_finish_gtt(obj); |
5323fd04 | 2077 | |
673a394b EA |
2078 | /* Move the object to the CPU domain to ensure that |
2079 | * any possible CPU writes while it's not in the GTT | |
a8198eea | 2080 | * are flushed when we go to remap it. |
673a394b | 2081 | */ |
a8198eea CW |
2082 | if (ret == 0) |
2083 | ret = i915_gem_object_set_to_cpu_domain(obj, 1); | |
8dc1775d | 2084 | if (ret == -ERESTARTSYS) |
673a394b | 2085 | return ret; |
812ed492 | 2086 | if (ret) { |
a8198eea CW |
2087 | /* In the event of a disaster, abandon all caches and |
2088 | * hope for the best. | |
2089 | */ | |
812ed492 | 2090 | i915_gem_clflush_object(obj); |
05394f39 | 2091 | obj->base.read_domains = obj->base.write_domain = I915_GEM_DOMAIN_CPU; |
812ed492 | 2092 | } |
673a394b | 2093 | |
96b47b65 | 2094 | /* release the fence reg _after_ flushing */ |
d9e86c0e CW |
2095 | ret = i915_gem_object_put_fence(obj); |
2096 | if (ret == -ERESTARTSYS) | |
2097 | return ret; | |
96b47b65 | 2098 | |
db53a302 CW |
2099 | trace_i915_gem_object_unbind(obj); |
2100 | ||
74898d7e DV |
2101 | if (obj->has_global_gtt_mapping) |
2102 | i915_gem_gtt_unbind_object(obj); | |
7bddb01f DV |
2103 | if (obj->has_aliasing_ppgtt_mapping) { |
2104 | i915_ppgtt_unbind_object(dev_priv->mm.aliasing_ppgtt, obj); | |
2105 | obj->has_aliasing_ppgtt_mapping = 0; | |
2106 | } | |
74163907 | 2107 | i915_gem_gtt_finish_object(obj); |
7bddb01f | 2108 | |
e5281ccd | 2109 | i915_gem_object_put_pages_gtt(obj); |
673a394b | 2110 | |
6299f992 | 2111 | list_del_init(&obj->gtt_list); |
05394f39 | 2112 | list_del_init(&obj->mm_list); |
75e9e915 | 2113 | /* Avoid an unnecessary call to unbind on rebind. */ |
05394f39 | 2114 | obj->map_and_fenceable = true; |
673a394b | 2115 | |
05394f39 CW |
2116 | drm_mm_put_block(obj->gtt_space); |
2117 | obj->gtt_space = NULL; | |
2118 | obj->gtt_offset = 0; | |
673a394b | 2119 | |
05394f39 | 2120 | if (i915_gem_object_is_purgeable(obj)) |
963b4836 CW |
2121 | i915_gem_object_truncate(obj); |
2122 | ||
8dc1775d | 2123 | return ret; |
673a394b EA |
2124 | } |
2125 | ||
88241785 | 2126 | int |
db53a302 | 2127 | i915_gem_flush_ring(struct intel_ring_buffer *ring, |
54cf91dc CW |
2128 | uint32_t invalidate_domains, |
2129 | uint32_t flush_domains) | |
2130 | { | |
88241785 CW |
2131 | int ret; |
2132 | ||
36d527de CW |
2133 | if (((invalidate_domains | flush_domains) & I915_GEM_GPU_DOMAINS) == 0) |
2134 | return 0; | |
2135 | ||
db53a302 CW |
2136 | trace_i915_gem_ring_flush(ring, invalidate_domains, flush_domains); |
2137 | ||
88241785 CW |
2138 | ret = ring->flush(ring, invalidate_domains, flush_domains); |
2139 | if (ret) | |
2140 | return ret; | |
2141 | ||
36d527de CW |
2142 | if (flush_domains & I915_GEM_GPU_DOMAINS) |
2143 | i915_gem_process_flushing_list(ring, flush_domains); | |
2144 | ||
88241785 | 2145 | return 0; |
54cf91dc CW |
2146 | } |
2147 | ||
b93f9cf1 | 2148 | static int i915_ring_idle(struct intel_ring_buffer *ring, bool do_retire) |
a56ba56c | 2149 | { |
88241785 CW |
2150 | int ret; |
2151 | ||
395b70be | 2152 | if (list_empty(&ring->gpu_write_list) && list_empty(&ring->active_list)) |
64193406 CW |
2153 | return 0; |
2154 | ||
88241785 | 2155 | if (!list_empty(&ring->gpu_write_list)) { |
db53a302 | 2156 | ret = i915_gem_flush_ring(ring, |
0ac74c6b | 2157 | I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS); |
88241785 CW |
2158 | if (ret) |
2159 | return ret; | |
2160 | } | |
2161 | ||
b93f9cf1 BW |
2162 | return i915_wait_request(ring, i915_gem_next_request_seqno(ring), |
2163 | do_retire); | |
a56ba56c CW |
2164 | } |
2165 | ||
b93f9cf1 | 2166 | int i915_gpu_idle(struct drm_device *dev, bool do_retire) |
4df2faf4 DV |
2167 | { |
2168 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1ec14ad3 | 2169 | int ret, i; |
4df2faf4 | 2170 | |
4df2faf4 | 2171 | /* Flush everything onto the inactive list. */ |
1ec14ad3 | 2172 | for (i = 0; i < I915_NUM_RINGS; i++) { |
b93f9cf1 | 2173 | ret = i915_ring_idle(&dev_priv->ring[i], do_retire); |
1ec14ad3 CW |
2174 | if (ret) |
2175 | return ret; | |
2176 | } | |
4df2faf4 | 2177 | |
8a1a49f9 | 2178 | return 0; |
4df2faf4 DV |
2179 | } |
2180 | ||
9ce079e4 CW |
2181 | static void sandybridge_write_fence_reg(struct drm_device *dev, int reg, |
2182 | struct drm_i915_gem_object *obj) | |
4e901fdc | 2183 | { |
4e901fdc | 2184 | drm_i915_private_t *dev_priv = dev->dev_private; |
4e901fdc EA |
2185 | uint64_t val; |
2186 | ||
9ce079e4 CW |
2187 | if (obj) { |
2188 | u32 size = obj->gtt_space->size; | |
4e901fdc | 2189 | |
9ce079e4 CW |
2190 | val = (uint64_t)((obj->gtt_offset + size - 4096) & |
2191 | 0xfffff000) << 32; | |
2192 | val |= obj->gtt_offset & 0xfffff000; | |
2193 | val |= (uint64_t)((obj->stride / 128) - 1) << | |
2194 | SANDYBRIDGE_FENCE_PITCH_SHIFT; | |
4e901fdc | 2195 | |
9ce079e4 CW |
2196 | if (obj->tiling_mode == I915_TILING_Y) |
2197 | val |= 1 << I965_FENCE_TILING_Y_SHIFT; | |
2198 | val |= I965_FENCE_REG_VALID; | |
2199 | } else | |
2200 | val = 0; | |
c6642782 | 2201 | |
9ce079e4 CW |
2202 | I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + reg * 8, val); |
2203 | POSTING_READ(FENCE_REG_SANDYBRIDGE_0 + reg * 8); | |
4e901fdc EA |
2204 | } |
2205 | ||
9ce079e4 CW |
2206 | static void i965_write_fence_reg(struct drm_device *dev, int reg, |
2207 | struct drm_i915_gem_object *obj) | |
de151cf6 | 2208 | { |
de151cf6 | 2209 | drm_i915_private_t *dev_priv = dev->dev_private; |
de151cf6 JB |
2210 | uint64_t val; |
2211 | ||
9ce079e4 CW |
2212 | if (obj) { |
2213 | u32 size = obj->gtt_space->size; | |
de151cf6 | 2214 | |
9ce079e4 CW |
2215 | val = (uint64_t)((obj->gtt_offset + size - 4096) & |
2216 | 0xfffff000) << 32; | |
2217 | val |= obj->gtt_offset & 0xfffff000; | |
2218 | val |= ((obj->stride / 128) - 1) << I965_FENCE_PITCH_SHIFT; | |
2219 | if (obj->tiling_mode == I915_TILING_Y) | |
2220 | val |= 1 << I965_FENCE_TILING_Y_SHIFT; | |
2221 | val |= I965_FENCE_REG_VALID; | |
2222 | } else | |
2223 | val = 0; | |
c6642782 | 2224 | |
9ce079e4 CW |
2225 | I915_WRITE64(FENCE_REG_965_0 + reg * 8, val); |
2226 | POSTING_READ(FENCE_REG_965_0 + reg * 8); | |
de151cf6 JB |
2227 | } |
2228 | ||
9ce079e4 CW |
2229 | static void i915_write_fence_reg(struct drm_device *dev, int reg, |
2230 | struct drm_i915_gem_object *obj) | |
de151cf6 | 2231 | { |
de151cf6 | 2232 | drm_i915_private_t *dev_priv = dev->dev_private; |
9ce079e4 | 2233 | u32 val; |
de151cf6 | 2234 | |
9ce079e4 CW |
2235 | if (obj) { |
2236 | u32 size = obj->gtt_space->size; | |
2237 | int pitch_val; | |
2238 | int tile_width; | |
c6642782 | 2239 | |
9ce079e4 CW |
2240 | WARN((obj->gtt_offset & ~I915_FENCE_START_MASK) || |
2241 | (size & -size) != size || | |
2242 | (obj->gtt_offset & (size - 1)), | |
2243 | "object 0x%08x [fenceable? %d] not 1M or pot-size (0x%08x) aligned\n", | |
2244 | obj->gtt_offset, obj->map_and_fenceable, size); | |
c6642782 | 2245 | |
9ce079e4 CW |
2246 | if (obj->tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev)) |
2247 | tile_width = 128; | |
2248 | else | |
2249 | tile_width = 512; | |
2250 | ||
2251 | /* Note: pitch better be a power of two tile widths */ | |
2252 | pitch_val = obj->stride / tile_width; | |
2253 | pitch_val = ffs(pitch_val) - 1; | |
2254 | ||
2255 | val = obj->gtt_offset; | |
2256 | if (obj->tiling_mode == I915_TILING_Y) | |
2257 | val |= 1 << I830_FENCE_TILING_Y_SHIFT; | |
2258 | val |= I915_FENCE_SIZE_BITS(size); | |
2259 | val |= pitch_val << I830_FENCE_PITCH_SHIFT; | |
2260 | val |= I830_FENCE_REG_VALID; | |
2261 | } else | |
2262 | val = 0; | |
2263 | ||
2264 | if (reg < 8) | |
2265 | reg = FENCE_REG_830_0 + reg * 4; | |
2266 | else | |
2267 | reg = FENCE_REG_945_8 + (reg - 8) * 4; | |
2268 | ||
2269 | I915_WRITE(reg, val); | |
2270 | POSTING_READ(reg); | |
de151cf6 JB |
2271 | } |
2272 | ||
9ce079e4 CW |
2273 | static void i830_write_fence_reg(struct drm_device *dev, int reg, |
2274 | struct drm_i915_gem_object *obj) | |
de151cf6 | 2275 | { |
de151cf6 | 2276 | drm_i915_private_t *dev_priv = dev->dev_private; |
de151cf6 | 2277 | uint32_t val; |
de151cf6 | 2278 | |
9ce079e4 CW |
2279 | if (obj) { |
2280 | u32 size = obj->gtt_space->size; | |
2281 | uint32_t pitch_val; | |
de151cf6 | 2282 | |
9ce079e4 CW |
2283 | WARN((obj->gtt_offset & ~I830_FENCE_START_MASK) || |
2284 | (size & -size) != size || | |
2285 | (obj->gtt_offset & (size - 1)), | |
2286 | "object 0x%08x not 512K or pot-size 0x%08x aligned\n", | |
2287 | obj->gtt_offset, size); | |
e76a16de | 2288 | |
9ce079e4 CW |
2289 | pitch_val = obj->stride / 128; |
2290 | pitch_val = ffs(pitch_val) - 1; | |
de151cf6 | 2291 | |
9ce079e4 CW |
2292 | val = obj->gtt_offset; |
2293 | if (obj->tiling_mode == I915_TILING_Y) | |
2294 | val |= 1 << I830_FENCE_TILING_Y_SHIFT; | |
2295 | val |= I830_FENCE_SIZE_BITS(size); | |
2296 | val |= pitch_val << I830_FENCE_PITCH_SHIFT; | |
2297 | val |= I830_FENCE_REG_VALID; | |
2298 | } else | |
2299 | val = 0; | |
c6642782 | 2300 | |
9ce079e4 CW |
2301 | I915_WRITE(FENCE_REG_830_0 + reg * 4, val); |
2302 | POSTING_READ(FENCE_REG_830_0 + reg * 4); | |
2303 | } | |
2304 | ||
2305 | static void i915_gem_write_fence(struct drm_device *dev, int reg, | |
2306 | struct drm_i915_gem_object *obj) | |
2307 | { | |
2308 | switch (INTEL_INFO(dev)->gen) { | |
2309 | case 7: | |
2310 | case 6: sandybridge_write_fence_reg(dev, reg, obj); break; | |
2311 | case 5: | |
2312 | case 4: i965_write_fence_reg(dev, reg, obj); break; | |
2313 | case 3: i915_write_fence_reg(dev, reg, obj); break; | |
2314 | case 2: i830_write_fence_reg(dev, reg, obj); break; | |
2315 | default: break; | |
2316 | } | |
de151cf6 JB |
2317 | } |
2318 | ||
61050808 CW |
2319 | static inline int fence_number(struct drm_i915_private *dev_priv, |
2320 | struct drm_i915_fence_reg *fence) | |
2321 | { | |
2322 | return fence - dev_priv->fence_regs; | |
2323 | } | |
2324 | ||
2325 | static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj, | |
2326 | struct drm_i915_fence_reg *fence, | |
2327 | bool enable) | |
2328 | { | |
2329 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; | |
2330 | int reg = fence_number(dev_priv, fence); | |
2331 | ||
2332 | i915_gem_write_fence(obj->base.dev, reg, enable ? obj : NULL); | |
2333 | ||
2334 | if (enable) { | |
2335 | obj->fence_reg = reg; | |
2336 | fence->obj = obj; | |
2337 | list_move_tail(&fence->lru_list, &dev_priv->mm.fence_list); | |
2338 | } else { | |
2339 | obj->fence_reg = I915_FENCE_REG_NONE; | |
2340 | fence->obj = NULL; | |
2341 | list_del_init(&fence->lru_list); | |
2342 | } | |
2343 | } | |
2344 | ||
d9e86c0e | 2345 | static int |
a360bb1a | 2346 | i915_gem_object_flush_fence(struct drm_i915_gem_object *obj) |
d9e86c0e CW |
2347 | { |
2348 | int ret; | |
2349 | ||
2350 | if (obj->fenced_gpu_access) { | |
88241785 | 2351 | if (obj->base.write_domain & I915_GEM_GPU_DOMAINS) { |
1c293ea3 | 2352 | ret = i915_gem_flush_ring(obj->ring, |
88241785 CW |
2353 | 0, obj->base.write_domain); |
2354 | if (ret) | |
2355 | return ret; | |
2356 | } | |
d9e86c0e CW |
2357 | |
2358 | obj->fenced_gpu_access = false; | |
2359 | } | |
2360 | ||
1c293ea3 | 2361 | if (obj->last_fenced_seqno) { |
18991845 CW |
2362 | ret = i915_wait_request(obj->ring, |
2363 | obj->last_fenced_seqno, | |
14415745 | 2364 | false); |
18991845 CW |
2365 | if (ret) |
2366 | return ret; | |
d9e86c0e CW |
2367 | |
2368 | obj->last_fenced_seqno = 0; | |
d9e86c0e CW |
2369 | } |
2370 | ||
63256ec5 CW |
2371 | /* Ensure that all CPU reads are completed before installing a fence |
2372 | * and all writes before removing the fence. | |
2373 | */ | |
2374 | if (obj->base.read_domains & I915_GEM_DOMAIN_GTT) | |
2375 | mb(); | |
2376 | ||
d9e86c0e CW |
2377 | return 0; |
2378 | } | |
2379 | ||
2380 | int | |
2381 | i915_gem_object_put_fence(struct drm_i915_gem_object *obj) | |
2382 | { | |
61050808 | 2383 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
d9e86c0e CW |
2384 | int ret; |
2385 | ||
a360bb1a | 2386 | ret = i915_gem_object_flush_fence(obj); |
d9e86c0e CW |
2387 | if (ret) |
2388 | return ret; | |
2389 | ||
61050808 CW |
2390 | if (obj->fence_reg == I915_FENCE_REG_NONE) |
2391 | return 0; | |
d9e86c0e | 2392 | |
61050808 CW |
2393 | i915_gem_object_update_fence(obj, |
2394 | &dev_priv->fence_regs[obj->fence_reg], | |
2395 | false); | |
2396 | i915_gem_object_fence_lost(obj); | |
d9e86c0e CW |
2397 | |
2398 | return 0; | |
2399 | } | |
2400 | ||
2401 | static struct drm_i915_fence_reg * | |
a360bb1a | 2402 | i915_find_fence_reg(struct drm_device *dev) |
ae3db24a | 2403 | { |
ae3db24a | 2404 | struct drm_i915_private *dev_priv = dev->dev_private; |
8fe301ad | 2405 | struct drm_i915_fence_reg *reg, *avail; |
d9e86c0e | 2406 | int i; |
ae3db24a DV |
2407 | |
2408 | /* First try to find a free reg */ | |
d9e86c0e | 2409 | avail = NULL; |
ae3db24a DV |
2410 | for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) { |
2411 | reg = &dev_priv->fence_regs[i]; | |
2412 | if (!reg->obj) | |
d9e86c0e | 2413 | return reg; |
ae3db24a | 2414 | |
1690e1eb | 2415 | if (!reg->pin_count) |
d9e86c0e | 2416 | avail = reg; |
ae3db24a DV |
2417 | } |
2418 | ||
d9e86c0e CW |
2419 | if (avail == NULL) |
2420 | return NULL; | |
ae3db24a DV |
2421 | |
2422 | /* None available, try to steal one or wait for a user to finish */ | |
d9e86c0e | 2423 | list_for_each_entry(reg, &dev_priv->mm.fence_list, lru_list) { |
1690e1eb | 2424 | if (reg->pin_count) |
ae3db24a DV |
2425 | continue; |
2426 | ||
8fe301ad | 2427 | return reg; |
ae3db24a DV |
2428 | } |
2429 | ||
8fe301ad | 2430 | return NULL; |
ae3db24a DV |
2431 | } |
2432 | ||
de151cf6 | 2433 | /** |
9a5a53b3 | 2434 | * i915_gem_object_get_fence - set up fencing for an object |
de151cf6 JB |
2435 | * @obj: object to map through a fence reg |
2436 | * | |
2437 | * When mapping objects through the GTT, userspace wants to be able to write | |
2438 | * to them without having to worry about swizzling if the object is tiled. | |
de151cf6 JB |
2439 | * This function walks the fence regs looking for a free one for @obj, |
2440 | * stealing one if it can't find any. | |
2441 | * | |
2442 | * It then sets up the reg based on the object's properties: address, pitch | |
2443 | * and tiling format. | |
9a5a53b3 CW |
2444 | * |
2445 | * For an untiled surface, this removes any existing fence. | |
de151cf6 | 2446 | */ |
8c4b8c3f | 2447 | int |
06d98131 | 2448 | i915_gem_object_get_fence(struct drm_i915_gem_object *obj) |
de151cf6 | 2449 | { |
05394f39 | 2450 | struct drm_device *dev = obj->base.dev; |
79e53945 | 2451 | struct drm_i915_private *dev_priv = dev->dev_private; |
14415745 | 2452 | bool enable = obj->tiling_mode != I915_TILING_NONE; |
d9e86c0e | 2453 | struct drm_i915_fence_reg *reg; |
ae3db24a | 2454 | int ret; |
de151cf6 | 2455 | |
14415745 CW |
2456 | /* Have we updated the tiling parameters upon the object and so |
2457 | * will need to serialise the write to the associated fence register? | |
2458 | */ | |
2459 | if (obj->tiling_changed) { | |
2460 | ret = i915_gem_object_flush_fence(obj); | |
2461 | if (ret) | |
2462 | return ret; | |
2463 | } | |
9a5a53b3 | 2464 | |
d9e86c0e | 2465 | /* Just update our place in the LRU if our fence is getting reused. */ |
05394f39 CW |
2466 | if (obj->fence_reg != I915_FENCE_REG_NONE) { |
2467 | reg = &dev_priv->fence_regs[obj->fence_reg]; | |
14415745 CW |
2468 | if (!obj->tiling_changed) { |
2469 | list_move_tail(®->lru_list, | |
2470 | &dev_priv->mm.fence_list); | |
2471 | return 0; | |
2472 | } | |
2473 | } else if (enable) { | |
2474 | reg = i915_find_fence_reg(dev); | |
2475 | if (reg == NULL) | |
2476 | return -EDEADLK; | |
d9e86c0e | 2477 | |
14415745 CW |
2478 | if (reg->obj) { |
2479 | struct drm_i915_gem_object *old = reg->obj; | |
2480 | ||
2481 | ret = i915_gem_object_flush_fence(old); | |
29c5a587 CW |
2482 | if (ret) |
2483 | return ret; | |
2484 | ||
14415745 | 2485 | i915_gem_object_fence_lost(old); |
29c5a587 | 2486 | } |
14415745 | 2487 | } else |
a09ba7fa | 2488 | return 0; |
a09ba7fa | 2489 | |
14415745 | 2490 | i915_gem_object_update_fence(obj, reg, enable); |
d9e86c0e | 2491 | obj->tiling_changed = false; |
14415745 | 2492 | |
9ce079e4 | 2493 | return 0; |
de151cf6 JB |
2494 | } |
2495 | ||
673a394b EA |
2496 | /** |
2497 | * Finds free space in the GTT aperture and binds the object there. | |
2498 | */ | |
2499 | static int | |
05394f39 | 2500 | i915_gem_object_bind_to_gtt(struct drm_i915_gem_object *obj, |
920afa77 | 2501 | unsigned alignment, |
75e9e915 | 2502 | bool map_and_fenceable) |
673a394b | 2503 | { |
05394f39 | 2504 | struct drm_device *dev = obj->base.dev; |
673a394b | 2505 | drm_i915_private_t *dev_priv = dev->dev_private; |
673a394b | 2506 | struct drm_mm_node *free_space; |
a00b10c3 | 2507 | gfp_t gfpmask = __GFP_NORETRY | __GFP_NOWARN; |
5e783301 | 2508 | u32 size, fence_size, fence_alignment, unfenced_alignment; |
75e9e915 | 2509 | bool mappable, fenceable; |
07f73f69 | 2510 | int ret; |
673a394b | 2511 | |
05394f39 | 2512 | if (obj->madv != I915_MADV_WILLNEED) { |
3ef94daa CW |
2513 | DRM_ERROR("Attempting to bind a purgeable object\n"); |
2514 | return -EINVAL; | |
2515 | } | |
2516 | ||
e28f8711 CW |
2517 | fence_size = i915_gem_get_gtt_size(dev, |
2518 | obj->base.size, | |
2519 | obj->tiling_mode); | |
2520 | fence_alignment = i915_gem_get_gtt_alignment(dev, | |
2521 | obj->base.size, | |
2522 | obj->tiling_mode); | |
2523 | unfenced_alignment = | |
2524 | i915_gem_get_unfenced_gtt_alignment(dev, | |
2525 | obj->base.size, | |
2526 | obj->tiling_mode); | |
a00b10c3 | 2527 | |
673a394b | 2528 | if (alignment == 0) |
5e783301 DV |
2529 | alignment = map_and_fenceable ? fence_alignment : |
2530 | unfenced_alignment; | |
75e9e915 | 2531 | if (map_and_fenceable && alignment & (fence_alignment - 1)) { |
673a394b EA |
2532 | DRM_ERROR("Invalid object alignment requested %u\n", alignment); |
2533 | return -EINVAL; | |
2534 | } | |
2535 | ||
05394f39 | 2536 | size = map_and_fenceable ? fence_size : obj->base.size; |
a00b10c3 | 2537 | |
654fc607 CW |
2538 | /* If the object is bigger than the entire aperture, reject it early |
2539 | * before evicting everything in a vain attempt to find space. | |
2540 | */ | |
05394f39 | 2541 | if (obj->base.size > |
75e9e915 | 2542 | (map_and_fenceable ? dev_priv->mm.gtt_mappable_end : dev_priv->mm.gtt_total)) { |
654fc607 CW |
2543 | DRM_ERROR("Attempting to bind an object larger than the aperture\n"); |
2544 | return -E2BIG; | |
2545 | } | |
2546 | ||
673a394b | 2547 | search_free: |
75e9e915 | 2548 | if (map_and_fenceable) |
920afa77 DV |
2549 | free_space = |
2550 | drm_mm_search_free_in_range(&dev_priv->mm.gtt_space, | |
a00b10c3 | 2551 | size, alignment, 0, |
920afa77 DV |
2552 | dev_priv->mm.gtt_mappable_end, |
2553 | 0); | |
2554 | else | |
2555 | free_space = drm_mm_search_free(&dev_priv->mm.gtt_space, | |
a00b10c3 | 2556 | size, alignment, 0); |
920afa77 DV |
2557 | |
2558 | if (free_space != NULL) { | |
75e9e915 | 2559 | if (map_and_fenceable) |
05394f39 | 2560 | obj->gtt_space = |
920afa77 | 2561 | drm_mm_get_block_range_generic(free_space, |
a00b10c3 | 2562 | size, alignment, 0, |
920afa77 DV |
2563 | dev_priv->mm.gtt_mappable_end, |
2564 | 0); | |
2565 | else | |
05394f39 | 2566 | obj->gtt_space = |
a00b10c3 | 2567 | drm_mm_get_block(free_space, size, alignment); |
920afa77 | 2568 | } |
05394f39 | 2569 | if (obj->gtt_space == NULL) { |
673a394b EA |
2570 | /* If the gtt is empty and we're still having trouble |
2571 | * fitting our object in, we're out of memory. | |
2572 | */ | |
75e9e915 DV |
2573 | ret = i915_gem_evict_something(dev, size, alignment, |
2574 | map_and_fenceable); | |
9731129c | 2575 | if (ret) |
673a394b | 2576 | return ret; |
9731129c | 2577 | |
673a394b EA |
2578 | goto search_free; |
2579 | } | |
2580 | ||
e5281ccd | 2581 | ret = i915_gem_object_get_pages_gtt(obj, gfpmask); |
673a394b | 2582 | if (ret) { |
05394f39 CW |
2583 | drm_mm_put_block(obj->gtt_space); |
2584 | obj->gtt_space = NULL; | |
07f73f69 CW |
2585 | |
2586 | if (ret == -ENOMEM) { | |
809b6334 CW |
2587 | /* first try to reclaim some memory by clearing the GTT */ |
2588 | ret = i915_gem_evict_everything(dev, false); | |
07f73f69 | 2589 | if (ret) { |
07f73f69 | 2590 | /* now try to shrink everyone else */ |
4bdadb97 CW |
2591 | if (gfpmask) { |
2592 | gfpmask = 0; | |
2593 | goto search_free; | |
07f73f69 CW |
2594 | } |
2595 | ||
809b6334 | 2596 | return -ENOMEM; |
07f73f69 CW |
2597 | } |
2598 | ||
2599 | goto search_free; | |
2600 | } | |
2601 | ||
673a394b EA |
2602 | return ret; |
2603 | } | |
2604 | ||
74163907 | 2605 | ret = i915_gem_gtt_prepare_object(obj); |
7c2e6fdf | 2606 | if (ret) { |
e5281ccd | 2607 | i915_gem_object_put_pages_gtt(obj); |
05394f39 CW |
2608 | drm_mm_put_block(obj->gtt_space); |
2609 | obj->gtt_space = NULL; | |
07f73f69 | 2610 | |
809b6334 | 2611 | if (i915_gem_evict_everything(dev, false)) |
07f73f69 | 2612 | return ret; |
07f73f69 CW |
2613 | |
2614 | goto search_free; | |
673a394b | 2615 | } |
673a394b | 2616 | |
0ebb9829 DV |
2617 | if (!dev_priv->mm.aliasing_ppgtt) |
2618 | i915_gem_gtt_bind_object(obj, obj->cache_level); | |
673a394b | 2619 | |
6299f992 | 2620 | list_add_tail(&obj->gtt_list, &dev_priv->mm.gtt_list); |
05394f39 | 2621 | list_add_tail(&obj->mm_list, &dev_priv->mm.inactive_list); |
bf1a1092 | 2622 | |
673a394b EA |
2623 | /* Assert that the object is not currently in any GPU domain. As it |
2624 | * wasn't in the GTT, there shouldn't be any way it could have been in | |
2625 | * a GPU cache | |
2626 | */ | |
05394f39 CW |
2627 | BUG_ON(obj->base.read_domains & I915_GEM_GPU_DOMAINS); |
2628 | BUG_ON(obj->base.write_domain & I915_GEM_GPU_DOMAINS); | |
673a394b | 2629 | |
6299f992 | 2630 | obj->gtt_offset = obj->gtt_space->start; |
1c5d22f7 | 2631 | |
75e9e915 | 2632 | fenceable = |
05394f39 | 2633 | obj->gtt_space->size == fence_size && |
0206e353 | 2634 | (obj->gtt_space->start & (fence_alignment - 1)) == 0; |
a00b10c3 | 2635 | |
75e9e915 | 2636 | mappable = |
05394f39 | 2637 | obj->gtt_offset + obj->base.size <= dev_priv->mm.gtt_mappable_end; |
a00b10c3 | 2638 | |
05394f39 | 2639 | obj->map_and_fenceable = mappable && fenceable; |
75e9e915 | 2640 | |
db53a302 | 2641 | trace_i915_gem_object_bind(obj, map_and_fenceable); |
673a394b EA |
2642 | return 0; |
2643 | } | |
2644 | ||
2645 | void | |
05394f39 | 2646 | i915_gem_clflush_object(struct drm_i915_gem_object *obj) |
673a394b | 2647 | { |
673a394b EA |
2648 | /* If we don't have a page list set up, then we're not pinned |
2649 | * to GPU, and we can ignore the cache flush because it'll happen | |
2650 | * again at bind time. | |
2651 | */ | |
05394f39 | 2652 | if (obj->pages == NULL) |
673a394b EA |
2653 | return; |
2654 | ||
9c23f7fc CW |
2655 | /* If the GPU is snooping the contents of the CPU cache, |
2656 | * we do not need to manually clear the CPU cache lines. However, | |
2657 | * the caches are only snooped when the render cache is | |
2658 | * flushed/invalidated. As we always have to emit invalidations | |
2659 | * and flushes when moving into and out of the RENDER domain, correct | |
2660 | * snooping behaviour occurs naturally as the result of our domain | |
2661 | * tracking. | |
2662 | */ | |
2663 | if (obj->cache_level != I915_CACHE_NONE) | |
2664 | return; | |
2665 | ||
1c5d22f7 | 2666 | trace_i915_gem_object_clflush(obj); |
cfa16a0d | 2667 | |
05394f39 | 2668 | drm_clflush_pages(obj->pages, obj->base.size / PAGE_SIZE); |
673a394b EA |
2669 | } |
2670 | ||
e47c68e9 | 2671 | /** Flushes any GPU write domain for the object if it's dirty. */ |
88241785 | 2672 | static int |
3619df03 | 2673 | i915_gem_object_flush_gpu_write_domain(struct drm_i915_gem_object *obj) |
e47c68e9 | 2674 | { |
05394f39 | 2675 | if ((obj->base.write_domain & I915_GEM_GPU_DOMAINS) == 0) |
88241785 | 2676 | return 0; |
e47c68e9 EA |
2677 | |
2678 | /* Queue the GPU write cache flushing we need. */ | |
db53a302 | 2679 | return i915_gem_flush_ring(obj->ring, 0, obj->base.write_domain); |
e47c68e9 EA |
2680 | } |
2681 | ||
2682 | /** Flushes the GTT write domain for the object if it's dirty. */ | |
2683 | static void | |
05394f39 | 2684 | i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj) |
e47c68e9 | 2685 | { |
1c5d22f7 CW |
2686 | uint32_t old_write_domain; |
2687 | ||
05394f39 | 2688 | if (obj->base.write_domain != I915_GEM_DOMAIN_GTT) |
e47c68e9 EA |
2689 | return; |
2690 | ||
63256ec5 | 2691 | /* No actual flushing is required for the GTT write domain. Writes |
e47c68e9 EA |
2692 | * to it immediately go to main memory as far as we know, so there's |
2693 | * no chipset flush. It also doesn't land in render cache. | |
63256ec5 CW |
2694 | * |
2695 | * However, we do have to enforce the order so that all writes through | |
2696 | * the GTT land before any writes to the device, such as updates to | |
2697 | * the GATT itself. | |
e47c68e9 | 2698 | */ |
63256ec5 CW |
2699 | wmb(); |
2700 | ||
05394f39 CW |
2701 | old_write_domain = obj->base.write_domain; |
2702 | obj->base.write_domain = 0; | |
1c5d22f7 CW |
2703 | |
2704 | trace_i915_gem_object_change_domain(obj, | |
05394f39 | 2705 | obj->base.read_domains, |
1c5d22f7 | 2706 | old_write_domain); |
e47c68e9 EA |
2707 | } |
2708 | ||
2709 | /** Flushes the CPU write domain for the object if it's dirty. */ | |
2710 | static void | |
05394f39 | 2711 | i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj) |
e47c68e9 | 2712 | { |
1c5d22f7 | 2713 | uint32_t old_write_domain; |
e47c68e9 | 2714 | |
05394f39 | 2715 | if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) |
e47c68e9 EA |
2716 | return; |
2717 | ||
2718 | i915_gem_clflush_object(obj); | |
40ce6575 | 2719 | intel_gtt_chipset_flush(); |
05394f39 CW |
2720 | old_write_domain = obj->base.write_domain; |
2721 | obj->base.write_domain = 0; | |
1c5d22f7 CW |
2722 | |
2723 | trace_i915_gem_object_change_domain(obj, | |
05394f39 | 2724 | obj->base.read_domains, |
1c5d22f7 | 2725 | old_write_domain); |
e47c68e9 EA |
2726 | } |
2727 | ||
2ef7eeaa EA |
2728 | /** |
2729 | * Moves a single object to the GTT read, and possibly write domain. | |
2730 | * | |
2731 | * This function returns when the move is complete, including waiting on | |
2732 | * flushes to occur. | |
2733 | */ | |
79e53945 | 2734 | int |
2021746e | 2735 | i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write) |
2ef7eeaa | 2736 | { |
1c5d22f7 | 2737 | uint32_t old_write_domain, old_read_domains; |
e47c68e9 | 2738 | int ret; |
2ef7eeaa | 2739 | |
02354392 | 2740 | /* Not valid to be called on unbound objects. */ |
05394f39 | 2741 | if (obj->gtt_space == NULL) |
02354392 EA |
2742 | return -EINVAL; |
2743 | ||
8d7e3de1 CW |
2744 | if (obj->base.write_domain == I915_GEM_DOMAIN_GTT) |
2745 | return 0; | |
2746 | ||
88241785 CW |
2747 | ret = i915_gem_object_flush_gpu_write_domain(obj); |
2748 | if (ret) | |
2749 | return ret; | |
2750 | ||
87ca9c8a | 2751 | if (obj->pending_gpu_write || write) { |
ce453d81 | 2752 | ret = i915_gem_object_wait_rendering(obj); |
87ca9c8a CW |
2753 | if (ret) |
2754 | return ret; | |
2755 | } | |
2dafb1e0 | 2756 | |
7213342d | 2757 | i915_gem_object_flush_cpu_write_domain(obj); |
1c5d22f7 | 2758 | |
05394f39 CW |
2759 | old_write_domain = obj->base.write_domain; |
2760 | old_read_domains = obj->base.read_domains; | |
1c5d22f7 | 2761 | |
e47c68e9 EA |
2762 | /* It should now be out of any other write domains, and we can update |
2763 | * the domain values for our changes. | |
2764 | */ | |
05394f39 CW |
2765 | BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) != 0); |
2766 | obj->base.read_domains |= I915_GEM_DOMAIN_GTT; | |
e47c68e9 | 2767 | if (write) { |
05394f39 CW |
2768 | obj->base.read_domains = I915_GEM_DOMAIN_GTT; |
2769 | obj->base.write_domain = I915_GEM_DOMAIN_GTT; | |
2770 | obj->dirty = 1; | |
2ef7eeaa EA |
2771 | } |
2772 | ||
1c5d22f7 CW |
2773 | trace_i915_gem_object_change_domain(obj, |
2774 | old_read_domains, | |
2775 | old_write_domain); | |
2776 | ||
e47c68e9 EA |
2777 | return 0; |
2778 | } | |
2779 | ||
e4ffd173 CW |
2780 | int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj, |
2781 | enum i915_cache_level cache_level) | |
2782 | { | |
7bddb01f DV |
2783 | struct drm_device *dev = obj->base.dev; |
2784 | drm_i915_private_t *dev_priv = dev->dev_private; | |
e4ffd173 CW |
2785 | int ret; |
2786 | ||
2787 | if (obj->cache_level == cache_level) | |
2788 | return 0; | |
2789 | ||
2790 | if (obj->pin_count) { | |
2791 | DRM_DEBUG("can not change the cache level of pinned objects\n"); | |
2792 | return -EBUSY; | |
2793 | } | |
2794 | ||
2795 | if (obj->gtt_space) { | |
2796 | ret = i915_gem_object_finish_gpu(obj); | |
2797 | if (ret) | |
2798 | return ret; | |
2799 | ||
2800 | i915_gem_object_finish_gtt(obj); | |
2801 | ||
2802 | /* Before SandyBridge, you could not use tiling or fence | |
2803 | * registers with snooped memory, so relinquish any fences | |
2804 | * currently pointing to our region in the aperture. | |
2805 | */ | |
2806 | if (INTEL_INFO(obj->base.dev)->gen < 6) { | |
2807 | ret = i915_gem_object_put_fence(obj); | |
2808 | if (ret) | |
2809 | return ret; | |
2810 | } | |
2811 | ||
74898d7e DV |
2812 | if (obj->has_global_gtt_mapping) |
2813 | i915_gem_gtt_bind_object(obj, cache_level); | |
7bddb01f DV |
2814 | if (obj->has_aliasing_ppgtt_mapping) |
2815 | i915_ppgtt_bind_object(dev_priv->mm.aliasing_ppgtt, | |
2816 | obj, cache_level); | |
e4ffd173 CW |
2817 | } |
2818 | ||
2819 | if (cache_level == I915_CACHE_NONE) { | |
2820 | u32 old_read_domains, old_write_domain; | |
2821 | ||
2822 | /* If we're coming from LLC cached, then we haven't | |
2823 | * actually been tracking whether the data is in the | |
2824 | * CPU cache or not, since we only allow one bit set | |
2825 | * in obj->write_domain and have been skipping the clflushes. | |
2826 | * Just set it to the CPU cache for now. | |
2827 | */ | |
2828 | WARN_ON(obj->base.write_domain & ~I915_GEM_DOMAIN_CPU); | |
2829 | WARN_ON(obj->base.read_domains & ~I915_GEM_DOMAIN_CPU); | |
2830 | ||
2831 | old_read_domains = obj->base.read_domains; | |
2832 | old_write_domain = obj->base.write_domain; | |
2833 | ||
2834 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; | |
2835 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; | |
2836 | ||
2837 | trace_i915_gem_object_change_domain(obj, | |
2838 | old_read_domains, | |
2839 | old_write_domain); | |
2840 | } | |
2841 | ||
2842 | obj->cache_level = cache_level; | |
2843 | return 0; | |
2844 | } | |
2845 | ||
b9241ea3 | 2846 | /* |
2da3b9b9 CW |
2847 | * Prepare buffer for display plane (scanout, cursors, etc). |
2848 | * Can be called from an uninterruptible phase (modesetting) and allows | |
2849 | * any flushes to be pipelined (for pageflips). | |
b9241ea3 ZW |
2850 | */ |
2851 | int | |
2da3b9b9 CW |
2852 | i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj, |
2853 | u32 alignment, | |
919926ae | 2854 | struct intel_ring_buffer *pipelined) |
b9241ea3 | 2855 | { |
2da3b9b9 | 2856 | u32 old_read_domains, old_write_domain; |
b9241ea3 ZW |
2857 | int ret; |
2858 | ||
88241785 CW |
2859 | ret = i915_gem_object_flush_gpu_write_domain(obj); |
2860 | if (ret) | |
2861 | return ret; | |
2862 | ||
0be73284 | 2863 | if (pipelined != obj->ring) { |
2911a35b BW |
2864 | ret = i915_gem_object_sync(obj, pipelined); |
2865 | if (ret) | |
b9241ea3 ZW |
2866 | return ret; |
2867 | } | |
2868 | ||
a7ef0640 EA |
2869 | /* The display engine is not coherent with the LLC cache on gen6. As |
2870 | * a result, we make sure that the pinning that is about to occur is | |
2871 | * done with uncached PTEs. This is lowest common denominator for all | |
2872 | * chipsets. | |
2873 | * | |
2874 | * However for gen6+, we could do better by using the GFDT bit instead | |
2875 | * of uncaching, which would allow us to flush all the LLC-cached data | |
2876 | * with that bit in the PTE to main memory with just one PIPE_CONTROL. | |
2877 | */ | |
2878 | ret = i915_gem_object_set_cache_level(obj, I915_CACHE_NONE); | |
2879 | if (ret) | |
2880 | return ret; | |
2881 | ||
2da3b9b9 CW |
2882 | /* As the user may map the buffer once pinned in the display plane |
2883 | * (e.g. libkms for the bootup splash), we have to ensure that we | |
2884 | * always use map_and_fenceable for all scanout buffers. | |
2885 | */ | |
2886 | ret = i915_gem_object_pin(obj, alignment, true); | |
2887 | if (ret) | |
2888 | return ret; | |
2889 | ||
b118c1e3 CW |
2890 | i915_gem_object_flush_cpu_write_domain(obj); |
2891 | ||
2da3b9b9 | 2892 | old_write_domain = obj->base.write_domain; |
05394f39 | 2893 | old_read_domains = obj->base.read_domains; |
2da3b9b9 CW |
2894 | |
2895 | /* It should now be out of any other write domains, and we can update | |
2896 | * the domain values for our changes. | |
2897 | */ | |
2898 | BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) != 0); | |
05394f39 | 2899 | obj->base.read_domains |= I915_GEM_DOMAIN_GTT; |
b9241ea3 ZW |
2900 | |
2901 | trace_i915_gem_object_change_domain(obj, | |
2902 | old_read_domains, | |
2da3b9b9 | 2903 | old_write_domain); |
b9241ea3 ZW |
2904 | |
2905 | return 0; | |
2906 | } | |
2907 | ||
85345517 | 2908 | int |
a8198eea | 2909 | i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj) |
85345517 | 2910 | { |
88241785 CW |
2911 | int ret; |
2912 | ||
a8198eea | 2913 | if ((obj->base.read_domains & I915_GEM_GPU_DOMAINS) == 0) |
85345517 CW |
2914 | return 0; |
2915 | ||
88241785 | 2916 | if (obj->base.write_domain & I915_GEM_GPU_DOMAINS) { |
db53a302 | 2917 | ret = i915_gem_flush_ring(obj->ring, 0, obj->base.write_domain); |
88241785 CW |
2918 | if (ret) |
2919 | return ret; | |
2920 | } | |
85345517 | 2921 | |
c501ae7f CW |
2922 | ret = i915_gem_object_wait_rendering(obj); |
2923 | if (ret) | |
2924 | return ret; | |
2925 | ||
a8198eea CW |
2926 | /* Ensure that we invalidate the GPU's caches and TLBs. */ |
2927 | obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS; | |
c501ae7f | 2928 | return 0; |
85345517 CW |
2929 | } |
2930 | ||
e47c68e9 EA |
2931 | /** |
2932 | * Moves a single object to the CPU read, and possibly write domain. | |
2933 | * | |
2934 | * This function returns when the move is complete, including waiting on | |
2935 | * flushes to occur. | |
2936 | */ | |
dabdfe02 | 2937 | int |
919926ae | 2938 | i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write) |
e47c68e9 | 2939 | { |
1c5d22f7 | 2940 | uint32_t old_write_domain, old_read_domains; |
e47c68e9 EA |
2941 | int ret; |
2942 | ||
8d7e3de1 CW |
2943 | if (obj->base.write_domain == I915_GEM_DOMAIN_CPU) |
2944 | return 0; | |
2945 | ||
88241785 CW |
2946 | ret = i915_gem_object_flush_gpu_write_domain(obj); |
2947 | if (ret) | |
2948 | return ret; | |
2949 | ||
f8413190 CW |
2950 | if (write || obj->pending_gpu_write) { |
2951 | ret = i915_gem_object_wait_rendering(obj); | |
2952 | if (ret) | |
2953 | return ret; | |
2954 | } | |
2ef7eeaa | 2955 | |
e47c68e9 | 2956 | i915_gem_object_flush_gtt_write_domain(obj); |
2ef7eeaa | 2957 | |
05394f39 CW |
2958 | old_write_domain = obj->base.write_domain; |
2959 | old_read_domains = obj->base.read_domains; | |
1c5d22f7 | 2960 | |
e47c68e9 | 2961 | /* Flush the CPU cache if it's still invalid. */ |
05394f39 | 2962 | if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) { |
2ef7eeaa | 2963 | i915_gem_clflush_object(obj); |
2ef7eeaa | 2964 | |
05394f39 | 2965 | obj->base.read_domains |= I915_GEM_DOMAIN_CPU; |
2ef7eeaa EA |
2966 | } |
2967 | ||
2968 | /* It should now be out of any other write domains, and we can update | |
2969 | * the domain values for our changes. | |
2970 | */ | |
05394f39 | 2971 | BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) != 0); |
e47c68e9 EA |
2972 | |
2973 | /* If we're writing through the CPU, then the GPU read domains will | |
2974 | * need to be invalidated at next use. | |
2975 | */ | |
2976 | if (write) { | |
05394f39 CW |
2977 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; |
2978 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; | |
e47c68e9 | 2979 | } |
2ef7eeaa | 2980 | |
1c5d22f7 CW |
2981 | trace_i915_gem_object_change_domain(obj, |
2982 | old_read_domains, | |
2983 | old_write_domain); | |
2984 | ||
2ef7eeaa EA |
2985 | return 0; |
2986 | } | |
2987 | ||
673a394b EA |
2988 | /* Throttle our rendering by waiting until the ring has completed our requests |
2989 | * emitted over 20 msec ago. | |
2990 | * | |
b962442e EA |
2991 | * Note that if we were to use the current jiffies each time around the loop, |
2992 | * we wouldn't escape the function with any frames outstanding if the time to | |
2993 | * render a frame was over 20ms. | |
2994 | * | |
673a394b EA |
2995 | * This should get us reasonable parallelism between CPU and GPU but also |
2996 | * relatively low latency when blocking on a particular request to finish. | |
2997 | */ | |
40a5f0de | 2998 | static int |
f787a5f5 | 2999 | i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file) |
40a5f0de | 3000 | { |
f787a5f5 CW |
3001 | struct drm_i915_private *dev_priv = dev->dev_private; |
3002 | struct drm_i915_file_private *file_priv = file->driver_priv; | |
b962442e | 3003 | unsigned long recent_enough = jiffies - msecs_to_jiffies(20); |
f787a5f5 CW |
3004 | struct drm_i915_gem_request *request; |
3005 | struct intel_ring_buffer *ring = NULL; | |
3006 | u32 seqno = 0; | |
3007 | int ret; | |
93533c29 | 3008 | |
e110e8d6 CW |
3009 | if (atomic_read(&dev_priv->mm.wedged)) |
3010 | return -EIO; | |
3011 | ||
1c25595f | 3012 | spin_lock(&file_priv->mm.lock); |
f787a5f5 | 3013 | list_for_each_entry(request, &file_priv->mm.request_list, client_list) { |
b962442e EA |
3014 | if (time_after_eq(request->emitted_jiffies, recent_enough)) |
3015 | break; | |
40a5f0de | 3016 | |
f787a5f5 CW |
3017 | ring = request->ring; |
3018 | seqno = request->seqno; | |
b962442e | 3019 | } |
1c25595f | 3020 | spin_unlock(&file_priv->mm.lock); |
40a5f0de | 3021 | |
f787a5f5 CW |
3022 | if (seqno == 0) |
3023 | return 0; | |
2bc43b5c | 3024 | |
f787a5f5 | 3025 | ret = 0; |
78501eac | 3026 | if (!i915_seqno_passed(ring->get_seqno(ring), seqno)) { |
f787a5f5 CW |
3027 | /* And wait for the seqno passing without holding any locks and |
3028 | * causing extra latency for others. This is safe as the irq | |
3029 | * generation is designed to be run atomically and so is | |
3030 | * lockless. | |
3031 | */ | |
b13c2b96 CW |
3032 | if (ring->irq_get(ring)) { |
3033 | ret = wait_event_interruptible(ring->irq_queue, | |
3034 | i915_seqno_passed(ring->get_seqno(ring), seqno) | |
3035 | || atomic_read(&dev_priv->mm.wedged)); | |
3036 | ring->irq_put(ring); | |
40a5f0de | 3037 | |
b13c2b96 CW |
3038 | if (ret == 0 && atomic_read(&dev_priv->mm.wedged)) |
3039 | ret = -EIO; | |
e959b5db EA |
3040 | } else if (wait_for_atomic(i915_seqno_passed(ring->get_seqno(ring), |
3041 | seqno) || | |
7ea29b13 EA |
3042 | atomic_read(&dev_priv->mm.wedged), 3000)) { |
3043 | ret = -EBUSY; | |
b13c2b96 | 3044 | } |
40a5f0de EA |
3045 | } |
3046 | ||
f787a5f5 CW |
3047 | if (ret == 0) |
3048 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, 0); | |
40a5f0de EA |
3049 | |
3050 | return ret; | |
3051 | } | |
3052 | ||
673a394b | 3053 | int |
05394f39 CW |
3054 | i915_gem_object_pin(struct drm_i915_gem_object *obj, |
3055 | uint32_t alignment, | |
75e9e915 | 3056 | bool map_and_fenceable) |
673a394b | 3057 | { |
05394f39 | 3058 | struct drm_device *dev = obj->base.dev; |
f13d3f73 | 3059 | struct drm_i915_private *dev_priv = dev->dev_private; |
673a394b EA |
3060 | int ret; |
3061 | ||
05394f39 | 3062 | BUG_ON(obj->pin_count == DRM_I915_GEM_OBJECT_MAX_PIN_COUNT); |
23bc5982 | 3063 | WARN_ON(i915_verify_lists(dev)); |
ac0c6b5a | 3064 | |
05394f39 CW |
3065 | if (obj->gtt_space != NULL) { |
3066 | if ((alignment && obj->gtt_offset & (alignment - 1)) || | |
3067 | (map_and_fenceable && !obj->map_and_fenceable)) { | |
3068 | WARN(obj->pin_count, | |
ae7d49d8 | 3069 | "bo is already pinned with incorrect alignment:" |
75e9e915 DV |
3070 | " offset=%x, req.alignment=%x, req.map_and_fenceable=%d," |
3071 | " obj->map_and_fenceable=%d\n", | |
05394f39 | 3072 | obj->gtt_offset, alignment, |
75e9e915 | 3073 | map_and_fenceable, |
05394f39 | 3074 | obj->map_and_fenceable); |
ac0c6b5a CW |
3075 | ret = i915_gem_object_unbind(obj); |
3076 | if (ret) | |
3077 | return ret; | |
3078 | } | |
3079 | } | |
3080 | ||
05394f39 | 3081 | if (obj->gtt_space == NULL) { |
a00b10c3 | 3082 | ret = i915_gem_object_bind_to_gtt(obj, alignment, |
75e9e915 | 3083 | map_and_fenceable); |
9731129c | 3084 | if (ret) |
673a394b | 3085 | return ret; |
22c344e9 | 3086 | } |
76446cac | 3087 | |
74898d7e DV |
3088 | if (!obj->has_global_gtt_mapping && map_and_fenceable) |
3089 | i915_gem_gtt_bind_object(obj, obj->cache_level); | |
3090 | ||
05394f39 | 3091 | if (obj->pin_count++ == 0) { |
05394f39 CW |
3092 | if (!obj->active) |
3093 | list_move_tail(&obj->mm_list, | |
f13d3f73 | 3094 | &dev_priv->mm.pinned_list); |
673a394b | 3095 | } |
6299f992 | 3096 | obj->pin_mappable |= map_and_fenceable; |
673a394b | 3097 | |
23bc5982 | 3098 | WARN_ON(i915_verify_lists(dev)); |
673a394b EA |
3099 | return 0; |
3100 | } | |
3101 | ||
3102 | void | |
05394f39 | 3103 | i915_gem_object_unpin(struct drm_i915_gem_object *obj) |
673a394b | 3104 | { |
05394f39 | 3105 | struct drm_device *dev = obj->base.dev; |
673a394b | 3106 | drm_i915_private_t *dev_priv = dev->dev_private; |
673a394b | 3107 | |
23bc5982 | 3108 | WARN_ON(i915_verify_lists(dev)); |
05394f39 CW |
3109 | BUG_ON(obj->pin_count == 0); |
3110 | BUG_ON(obj->gtt_space == NULL); | |
673a394b | 3111 | |
05394f39 CW |
3112 | if (--obj->pin_count == 0) { |
3113 | if (!obj->active) | |
3114 | list_move_tail(&obj->mm_list, | |
673a394b | 3115 | &dev_priv->mm.inactive_list); |
6299f992 | 3116 | obj->pin_mappable = false; |
673a394b | 3117 | } |
23bc5982 | 3118 | WARN_ON(i915_verify_lists(dev)); |
673a394b EA |
3119 | } |
3120 | ||
3121 | int | |
3122 | i915_gem_pin_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 3123 | struct drm_file *file) |
673a394b EA |
3124 | { |
3125 | struct drm_i915_gem_pin *args = data; | |
05394f39 | 3126 | struct drm_i915_gem_object *obj; |
673a394b EA |
3127 | int ret; |
3128 | ||
1d7cfea1 CW |
3129 | ret = i915_mutex_lock_interruptible(dev); |
3130 | if (ret) | |
3131 | return ret; | |
673a394b | 3132 | |
05394f39 | 3133 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 3134 | if (&obj->base == NULL) { |
1d7cfea1 CW |
3135 | ret = -ENOENT; |
3136 | goto unlock; | |
673a394b | 3137 | } |
673a394b | 3138 | |
05394f39 | 3139 | if (obj->madv != I915_MADV_WILLNEED) { |
bb6baf76 | 3140 | DRM_ERROR("Attempting to pin a purgeable buffer\n"); |
1d7cfea1 CW |
3141 | ret = -EINVAL; |
3142 | goto out; | |
3ef94daa CW |
3143 | } |
3144 | ||
05394f39 | 3145 | if (obj->pin_filp != NULL && obj->pin_filp != file) { |
79e53945 JB |
3146 | DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n", |
3147 | args->handle); | |
1d7cfea1 CW |
3148 | ret = -EINVAL; |
3149 | goto out; | |
79e53945 JB |
3150 | } |
3151 | ||
05394f39 CW |
3152 | obj->user_pin_count++; |
3153 | obj->pin_filp = file; | |
3154 | if (obj->user_pin_count == 1) { | |
75e9e915 | 3155 | ret = i915_gem_object_pin(obj, args->alignment, true); |
1d7cfea1 CW |
3156 | if (ret) |
3157 | goto out; | |
673a394b EA |
3158 | } |
3159 | ||
3160 | /* XXX - flush the CPU caches for pinned objects | |
3161 | * as the X server doesn't manage domains yet | |
3162 | */ | |
e47c68e9 | 3163 | i915_gem_object_flush_cpu_write_domain(obj); |
05394f39 | 3164 | args->offset = obj->gtt_offset; |
1d7cfea1 | 3165 | out: |
05394f39 | 3166 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 3167 | unlock: |
673a394b | 3168 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 3169 | return ret; |
673a394b EA |
3170 | } |
3171 | ||
3172 | int | |
3173 | i915_gem_unpin_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 3174 | struct drm_file *file) |
673a394b EA |
3175 | { |
3176 | struct drm_i915_gem_pin *args = data; | |
05394f39 | 3177 | struct drm_i915_gem_object *obj; |
76c1dec1 | 3178 | int ret; |
673a394b | 3179 | |
1d7cfea1 CW |
3180 | ret = i915_mutex_lock_interruptible(dev); |
3181 | if (ret) | |
3182 | return ret; | |
673a394b | 3183 | |
05394f39 | 3184 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 3185 | if (&obj->base == NULL) { |
1d7cfea1 CW |
3186 | ret = -ENOENT; |
3187 | goto unlock; | |
673a394b | 3188 | } |
76c1dec1 | 3189 | |
05394f39 | 3190 | if (obj->pin_filp != file) { |
79e53945 JB |
3191 | DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n", |
3192 | args->handle); | |
1d7cfea1 CW |
3193 | ret = -EINVAL; |
3194 | goto out; | |
79e53945 | 3195 | } |
05394f39 CW |
3196 | obj->user_pin_count--; |
3197 | if (obj->user_pin_count == 0) { | |
3198 | obj->pin_filp = NULL; | |
79e53945 JB |
3199 | i915_gem_object_unpin(obj); |
3200 | } | |
673a394b | 3201 | |
1d7cfea1 | 3202 | out: |
05394f39 | 3203 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 3204 | unlock: |
673a394b | 3205 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 3206 | return ret; |
673a394b EA |
3207 | } |
3208 | ||
3209 | int | |
3210 | i915_gem_busy_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 3211 | struct drm_file *file) |
673a394b EA |
3212 | { |
3213 | struct drm_i915_gem_busy *args = data; | |
05394f39 | 3214 | struct drm_i915_gem_object *obj; |
30dbf0c0 CW |
3215 | int ret; |
3216 | ||
76c1dec1 | 3217 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 3218 | if (ret) |
76c1dec1 | 3219 | return ret; |
673a394b | 3220 | |
05394f39 | 3221 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 3222 | if (&obj->base == NULL) { |
1d7cfea1 CW |
3223 | ret = -ENOENT; |
3224 | goto unlock; | |
673a394b | 3225 | } |
d1b851fc | 3226 | |
0be555b6 CW |
3227 | /* Count all active objects as busy, even if they are currently not used |
3228 | * by the gpu. Users of this interface expect objects to eventually | |
3229 | * become non-busy without any further actions, therefore emit any | |
3230 | * necessary flushes here. | |
c4de0a5d | 3231 | */ |
05394f39 | 3232 | args->busy = obj->active; |
0be555b6 CW |
3233 | if (args->busy) { |
3234 | /* Unconditionally flush objects, even when the gpu still uses this | |
3235 | * object. Userspace calling this function indicates that it wants to | |
3236 | * use this buffer rather sooner than later, so issuing the required | |
3237 | * flush earlier is beneficial. | |
3238 | */ | |
1a1c6976 | 3239 | if (obj->base.write_domain & I915_GEM_GPU_DOMAINS) { |
db53a302 | 3240 | ret = i915_gem_flush_ring(obj->ring, |
88241785 | 3241 | 0, obj->base.write_domain); |
1a1c6976 CW |
3242 | } else if (obj->ring->outstanding_lazy_request == |
3243 | obj->last_rendering_seqno) { | |
3244 | struct drm_i915_gem_request *request; | |
3245 | ||
7a194876 CW |
3246 | /* This ring is not being cleared by active usage, |
3247 | * so emit a request to do so. | |
3248 | */ | |
1a1c6976 | 3249 | request = kzalloc(sizeof(*request), GFP_KERNEL); |
457eafce | 3250 | if (request) { |
0206e353 | 3251 | ret = i915_add_request(obj->ring, NULL, request); |
457eafce RM |
3252 | if (ret) |
3253 | kfree(request); | |
3254 | } else | |
7a194876 CW |
3255 | ret = -ENOMEM; |
3256 | } | |
0be555b6 CW |
3257 | |
3258 | /* Update the active list for the hardware's current position. | |
3259 | * Otherwise this only updates on a delayed timer or when irqs | |
3260 | * are actually unmasked, and our working set ends up being | |
3261 | * larger than required. | |
3262 | */ | |
db53a302 | 3263 | i915_gem_retire_requests_ring(obj->ring); |
0be555b6 | 3264 | |
05394f39 | 3265 | args->busy = obj->active; |
0be555b6 | 3266 | } |
673a394b | 3267 | |
05394f39 | 3268 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 3269 | unlock: |
673a394b | 3270 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 3271 | return ret; |
673a394b EA |
3272 | } |
3273 | ||
3274 | int | |
3275 | i915_gem_throttle_ioctl(struct drm_device *dev, void *data, | |
3276 | struct drm_file *file_priv) | |
3277 | { | |
0206e353 | 3278 | return i915_gem_ring_throttle(dev, file_priv); |
673a394b EA |
3279 | } |
3280 | ||
3ef94daa CW |
3281 | int |
3282 | i915_gem_madvise_ioctl(struct drm_device *dev, void *data, | |
3283 | struct drm_file *file_priv) | |
3284 | { | |
3285 | struct drm_i915_gem_madvise *args = data; | |
05394f39 | 3286 | struct drm_i915_gem_object *obj; |
76c1dec1 | 3287 | int ret; |
3ef94daa CW |
3288 | |
3289 | switch (args->madv) { | |
3290 | case I915_MADV_DONTNEED: | |
3291 | case I915_MADV_WILLNEED: | |
3292 | break; | |
3293 | default: | |
3294 | return -EINVAL; | |
3295 | } | |
3296 | ||
1d7cfea1 CW |
3297 | ret = i915_mutex_lock_interruptible(dev); |
3298 | if (ret) | |
3299 | return ret; | |
3300 | ||
05394f39 | 3301 | obj = to_intel_bo(drm_gem_object_lookup(dev, file_priv, args->handle)); |
c8725226 | 3302 | if (&obj->base == NULL) { |
1d7cfea1 CW |
3303 | ret = -ENOENT; |
3304 | goto unlock; | |
3ef94daa | 3305 | } |
3ef94daa | 3306 | |
05394f39 | 3307 | if (obj->pin_count) { |
1d7cfea1 CW |
3308 | ret = -EINVAL; |
3309 | goto out; | |
3ef94daa CW |
3310 | } |
3311 | ||
05394f39 CW |
3312 | if (obj->madv != __I915_MADV_PURGED) |
3313 | obj->madv = args->madv; | |
3ef94daa | 3314 | |
2d7ef395 | 3315 | /* if the object is no longer bound, discard its backing storage */ |
05394f39 CW |
3316 | if (i915_gem_object_is_purgeable(obj) && |
3317 | obj->gtt_space == NULL) | |
2d7ef395 CW |
3318 | i915_gem_object_truncate(obj); |
3319 | ||
05394f39 | 3320 | args->retained = obj->madv != __I915_MADV_PURGED; |
bb6baf76 | 3321 | |
1d7cfea1 | 3322 | out: |
05394f39 | 3323 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 3324 | unlock: |
3ef94daa | 3325 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 3326 | return ret; |
3ef94daa CW |
3327 | } |
3328 | ||
05394f39 CW |
3329 | struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev, |
3330 | size_t size) | |
ac52bc56 | 3331 | { |
73aa808f | 3332 | struct drm_i915_private *dev_priv = dev->dev_private; |
c397b908 | 3333 | struct drm_i915_gem_object *obj; |
5949eac4 | 3334 | struct address_space *mapping; |
ac52bc56 | 3335 | |
c397b908 DV |
3336 | obj = kzalloc(sizeof(*obj), GFP_KERNEL); |
3337 | if (obj == NULL) | |
3338 | return NULL; | |
673a394b | 3339 | |
c397b908 DV |
3340 | if (drm_gem_object_init(dev, &obj->base, size) != 0) { |
3341 | kfree(obj); | |
3342 | return NULL; | |
3343 | } | |
673a394b | 3344 | |
5949eac4 HD |
3345 | mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping; |
3346 | mapping_set_gfp_mask(mapping, GFP_HIGHUSER | __GFP_RECLAIMABLE); | |
3347 | ||
73aa808f CW |
3348 | i915_gem_info_add_obj(dev_priv, size); |
3349 | ||
c397b908 DV |
3350 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; |
3351 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; | |
673a394b | 3352 | |
3d29b842 ED |
3353 | if (HAS_LLC(dev)) { |
3354 | /* On some devices, we can have the GPU use the LLC (the CPU | |
a1871112 EA |
3355 | * cache) for about a 10% performance improvement |
3356 | * compared to uncached. Graphics requests other than | |
3357 | * display scanout are coherent with the CPU in | |
3358 | * accessing this cache. This means in this mode we | |
3359 | * don't need to clflush on the CPU side, and on the | |
3360 | * GPU side we only need to flush internal caches to | |
3361 | * get data visible to the CPU. | |
3362 | * | |
3363 | * However, we maintain the display planes as UC, and so | |
3364 | * need to rebind when first used as such. | |
3365 | */ | |
3366 | obj->cache_level = I915_CACHE_LLC; | |
3367 | } else | |
3368 | obj->cache_level = I915_CACHE_NONE; | |
3369 | ||
62b8b215 | 3370 | obj->base.driver_private = NULL; |
c397b908 | 3371 | obj->fence_reg = I915_FENCE_REG_NONE; |
69dc4987 | 3372 | INIT_LIST_HEAD(&obj->mm_list); |
93a37f20 | 3373 | INIT_LIST_HEAD(&obj->gtt_list); |
69dc4987 | 3374 | INIT_LIST_HEAD(&obj->ring_list); |
432e58ed | 3375 | INIT_LIST_HEAD(&obj->exec_list); |
c397b908 | 3376 | INIT_LIST_HEAD(&obj->gpu_write_list); |
c397b908 | 3377 | obj->madv = I915_MADV_WILLNEED; |
75e9e915 DV |
3378 | /* Avoid an unnecessary call to unbind on the first bind. */ |
3379 | obj->map_and_fenceable = true; | |
de151cf6 | 3380 | |
05394f39 | 3381 | return obj; |
c397b908 DV |
3382 | } |
3383 | ||
3384 | int i915_gem_init_object(struct drm_gem_object *obj) | |
3385 | { | |
3386 | BUG(); | |
de151cf6 | 3387 | |
673a394b EA |
3388 | return 0; |
3389 | } | |
3390 | ||
05394f39 | 3391 | static void i915_gem_free_object_tail(struct drm_i915_gem_object *obj) |
673a394b | 3392 | { |
05394f39 | 3393 | struct drm_device *dev = obj->base.dev; |
be72615b | 3394 | drm_i915_private_t *dev_priv = dev->dev_private; |
be72615b | 3395 | int ret; |
673a394b | 3396 | |
be72615b CW |
3397 | ret = i915_gem_object_unbind(obj); |
3398 | if (ret == -ERESTARTSYS) { | |
05394f39 | 3399 | list_move(&obj->mm_list, |
be72615b CW |
3400 | &dev_priv->mm.deferred_free_list); |
3401 | return; | |
3402 | } | |
673a394b | 3403 | |
26e12f89 CW |
3404 | trace_i915_gem_object_destroy(obj); |
3405 | ||
05394f39 | 3406 | if (obj->base.map_list.map) |
b464e9a2 | 3407 | drm_gem_free_mmap_offset(&obj->base); |
de151cf6 | 3408 | |
05394f39 CW |
3409 | drm_gem_object_release(&obj->base); |
3410 | i915_gem_info_remove_obj(dev_priv, obj->base.size); | |
c397b908 | 3411 | |
05394f39 CW |
3412 | kfree(obj->bit_17); |
3413 | kfree(obj); | |
673a394b EA |
3414 | } |
3415 | ||
05394f39 | 3416 | void i915_gem_free_object(struct drm_gem_object *gem_obj) |
be72615b | 3417 | { |
05394f39 CW |
3418 | struct drm_i915_gem_object *obj = to_intel_bo(gem_obj); |
3419 | struct drm_device *dev = obj->base.dev; | |
be72615b | 3420 | |
05394f39 | 3421 | while (obj->pin_count > 0) |
be72615b CW |
3422 | i915_gem_object_unpin(obj); |
3423 | ||
05394f39 | 3424 | if (obj->phys_obj) |
be72615b CW |
3425 | i915_gem_detach_phys_object(dev, obj); |
3426 | ||
3427 | i915_gem_free_object_tail(obj); | |
3428 | } | |
3429 | ||
29105ccc CW |
3430 | int |
3431 | i915_gem_idle(struct drm_device *dev) | |
3432 | { | |
3433 | drm_i915_private_t *dev_priv = dev->dev_private; | |
3434 | int ret; | |
28dfe52a | 3435 | |
29105ccc | 3436 | mutex_lock(&dev->struct_mutex); |
1c5d22f7 | 3437 | |
87acb0a5 | 3438 | if (dev_priv->mm.suspended) { |
29105ccc CW |
3439 | mutex_unlock(&dev->struct_mutex); |
3440 | return 0; | |
28dfe52a EA |
3441 | } |
3442 | ||
b93f9cf1 | 3443 | ret = i915_gpu_idle(dev, true); |
6dbe2772 KP |
3444 | if (ret) { |
3445 | mutex_unlock(&dev->struct_mutex); | |
673a394b | 3446 | return ret; |
6dbe2772 | 3447 | } |
673a394b | 3448 | |
29105ccc CW |
3449 | /* Under UMS, be paranoid and evict. */ |
3450 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) { | |
5eac3ab4 | 3451 | ret = i915_gem_evict_inactive(dev, false); |
29105ccc CW |
3452 | if (ret) { |
3453 | mutex_unlock(&dev->struct_mutex); | |
3454 | return ret; | |
3455 | } | |
3456 | } | |
3457 | ||
312817a3 CW |
3458 | i915_gem_reset_fences(dev); |
3459 | ||
29105ccc CW |
3460 | /* Hack! Don't let anybody do execbuf while we don't control the chip. |
3461 | * We need to replace this with a semaphore, or something. | |
3462 | * And not confound mm.suspended! | |
3463 | */ | |
3464 | dev_priv->mm.suspended = 1; | |
bc0c7f14 | 3465 | del_timer_sync(&dev_priv->hangcheck_timer); |
29105ccc CW |
3466 | |
3467 | i915_kernel_lost_context(dev); | |
6dbe2772 | 3468 | i915_gem_cleanup_ringbuffer(dev); |
29105ccc | 3469 | |
6dbe2772 KP |
3470 | mutex_unlock(&dev->struct_mutex); |
3471 | ||
29105ccc CW |
3472 | /* Cancel the retire work handler, which should be idle now. */ |
3473 | cancel_delayed_work_sync(&dev_priv->mm.retire_work); | |
3474 | ||
673a394b EA |
3475 | return 0; |
3476 | } | |
3477 | ||
f691e2f4 DV |
3478 | void i915_gem_init_swizzling(struct drm_device *dev) |
3479 | { | |
3480 | drm_i915_private_t *dev_priv = dev->dev_private; | |
3481 | ||
11782b02 | 3482 | if (INTEL_INFO(dev)->gen < 5 || |
f691e2f4 DV |
3483 | dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE) |
3484 | return; | |
3485 | ||
3486 | I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) | | |
3487 | DISP_TILE_SURFACE_SWIZZLING); | |
3488 | ||
11782b02 DV |
3489 | if (IS_GEN5(dev)) |
3490 | return; | |
3491 | ||
f691e2f4 DV |
3492 | I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_SWZCTL); |
3493 | if (IS_GEN6(dev)) | |
3494 | I915_WRITE(ARB_MODE, ARB_MODE_ENABLE(ARB_MODE_SWIZZLE_SNB)); | |
3495 | else | |
3496 | I915_WRITE(ARB_MODE, ARB_MODE_ENABLE(ARB_MODE_SWIZZLE_IVB)); | |
3497 | } | |
e21af88d DV |
3498 | |
3499 | void i915_gem_init_ppgtt(struct drm_device *dev) | |
3500 | { | |
3501 | drm_i915_private_t *dev_priv = dev->dev_private; | |
3502 | uint32_t pd_offset; | |
3503 | struct intel_ring_buffer *ring; | |
55a254ac DV |
3504 | struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt; |
3505 | uint32_t __iomem *pd_addr; | |
3506 | uint32_t pd_entry; | |
e21af88d DV |
3507 | int i; |
3508 | ||
3509 | if (!dev_priv->mm.aliasing_ppgtt) | |
3510 | return; | |
3511 | ||
55a254ac DV |
3512 | |
3513 | pd_addr = dev_priv->mm.gtt->gtt + ppgtt->pd_offset/sizeof(uint32_t); | |
3514 | for (i = 0; i < ppgtt->num_pd_entries; i++) { | |
3515 | dma_addr_t pt_addr; | |
3516 | ||
3517 | if (dev_priv->mm.gtt->needs_dmar) | |
3518 | pt_addr = ppgtt->pt_dma_addr[i]; | |
3519 | else | |
3520 | pt_addr = page_to_phys(ppgtt->pt_pages[i]); | |
3521 | ||
3522 | pd_entry = GEN6_PDE_ADDR_ENCODE(pt_addr); | |
3523 | pd_entry |= GEN6_PDE_VALID; | |
3524 | ||
3525 | writel(pd_entry, pd_addr + i); | |
3526 | } | |
3527 | readl(pd_addr); | |
3528 | ||
3529 | pd_offset = ppgtt->pd_offset; | |
e21af88d DV |
3530 | pd_offset /= 64; /* in cachelines, */ |
3531 | pd_offset <<= 16; | |
3532 | ||
3533 | if (INTEL_INFO(dev)->gen == 6) { | |
48ecfa10 DV |
3534 | uint32_t ecochk, gab_ctl, ecobits; |
3535 | ||
3536 | ecobits = I915_READ(GAC_ECO_BITS); | |
3537 | I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_PPGTT_CACHE64B); | |
be901a5a DV |
3538 | |
3539 | gab_ctl = I915_READ(GAB_CTL); | |
3540 | I915_WRITE(GAB_CTL, gab_ctl | GAB_CTL_CONT_AFTER_PAGEFAULT); | |
3541 | ||
3542 | ecochk = I915_READ(GAM_ECOCHK); | |
e21af88d DV |
3543 | I915_WRITE(GAM_ECOCHK, ecochk | ECOCHK_SNB_BIT | |
3544 | ECOCHK_PPGTT_CACHE64B); | |
3545 | I915_WRITE(GFX_MODE, GFX_MODE_ENABLE(GFX_PPGTT_ENABLE)); | |
3546 | } else if (INTEL_INFO(dev)->gen >= 7) { | |
3547 | I915_WRITE(GAM_ECOCHK, ECOCHK_PPGTT_CACHE64B); | |
3548 | /* GFX_MODE is per-ring on gen7+ */ | |
3549 | } | |
3550 | ||
3551 | for (i = 0; i < I915_NUM_RINGS; i++) { | |
3552 | ring = &dev_priv->ring[i]; | |
3553 | ||
3554 | if (INTEL_INFO(dev)->gen >= 7) | |
3555 | I915_WRITE(RING_MODE_GEN7(ring), | |
3556 | GFX_MODE_ENABLE(GFX_PPGTT_ENABLE)); | |
3557 | ||
3558 | I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G); | |
3559 | I915_WRITE(RING_PP_DIR_BASE(ring), pd_offset); | |
3560 | } | |
3561 | } | |
3562 | ||
8187a2b7 | 3563 | int |
f691e2f4 | 3564 | i915_gem_init_hw(struct drm_device *dev) |
8187a2b7 ZN |
3565 | { |
3566 | drm_i915_private_t *dev_priv = dev->dev_private; | |
3567 | int ret; | |
68f95ba9 | 3568 | |
f691e2f4 DV |
3569 | i915_gem_init_swizzling(dev); |
3570 | ||
5c1143bb | 3571 | ret = intel_init_render_ring_buffer(dev); |
68f95ba9 | 3572 | if (ret) |
b6913e4b | 3573 | return ret; |
68f95ba9 CW |
3574 | |
3575 | if (HAS_BSD(dev)) { | |
5c1143bb | 3576 | ret = intel_init_bsd_ring_buffer(dev); |
68f95ba9 CW |
3577 | if (ret) |
3578 | goto cleanup_render_ring; | |
d1b851fc | 3579 | } |
68f95ba9 | 3580 | |
549f7365 CW |
3581 | if (HAS_BLT(dev)) { |
3582 | ret = intel_init_blt_ring_buffer(dev); | |
3583 | if (ret) | |
3584 | goto cleanup_bsd_ring; | |
3585 | } | |
3586 | ||
6f392d54 CW |
3587 | dev_priv->next_seqno = 1; |
3588 | ||
e21af88d DV |
3589 | i915_gem_init_ppgtt(dev); |
3590 | ||
68f95ba9 CW |
3591 | return 0; |
3592 | ||
549f7365 | 3593 | cleanup_bsd_ring: |
1ec14ad3 | 3594 | intel_cleanup_ring_buffer(&dev_priv->ring[VCS]); |
68f95ba9 | 3595 | cleanup_render_ring: |
1ec14ad3 | 3596 | intel_cleanup_ring_buffer(&dev_priv->ring[RCS]); |
8187a2b7 ZN |
3597 | return ret; |
3598 | } | |
3599 | ||
3600 | void | |
3601 | i915_gem_cleanup_ringbuffer(struct drm_device *dev) | |
3602 | { | |
3603 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1ec14ad3 | 3604 | int i; |
8187a2b7 | 3605 | |
1ec14ad3 CW |
3606 | for (i = 0; i < I915_NUM_RINGS; i++) |
3607 | intel_cleanup_ring_buffer(&dev_priv->ring[i]); | |
8187a2b7 ZN |
3608 | } |
3609 | ||
673a394b EA |
3610 | int |
3611 | i915_gem_entervt_ioctl(struct drm_device *dev, void *data, | |
3612 | struct drm_file *file_priv) | |
3613 | { | |
3614 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1ec14ad3 | 3615 | int ret, i; |
673a394b | 3616 | |
79e53945 JB |
3617 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
3618 | return 0; | |
3619 | ||
ba1234d1 | 3620 | if (atomic_read(&dev_priv->mm.wedged)) { |
673a394b | 3621 | DRM_ERROR("Reenabling wedged hardware, good luck\n"); |
ba1234d1 | 3622 | atomic_set(&dev_priv->mm.wedged, 0); |
673a394b EA |
3623 | } |
3624 | ||
673a394b | 3625 | mutex_lock(&dev->struct_mutex); |
9bb2d6f9 EA |
3626 | dev_priv->mm.suspended = 0; |
3627 | ||
f691e2f4 | 3628 | ret = i915_gem_init_hw(dev); |
d816f6ac WF |
3629 | if (ret != 0) { |
3630 | mutex_unlock(&dev->struct_mutex); | |
9bb2d6f9 | 3631 | return ret; |
d816f6ac | 3632 | } |
9bb2d6f9 | 3633 | |
69dc4987 | 3634 | BUG_ON(!list_empty(&dev_priv->mm.active_list)); |
673a394b EA |
3635 | BUG_ON(!list_empty(&dev_priv->mm.flushing_list)); |
3636 | BUG_ON(!list_empty(&dev_priv->mm.inactive_list)); | |
1ec14ad3 CW |
3637 | for (i = 0; i < I915_NUM_RINGS; i++) { |
3638 | BUG_ON(!list_empty(&dev_priv->ring[i].active_list)); | |
3639 | BUG_ON(!list_empty(&dev_priv->ring[i].request_list)); | |
3640 | } | |
673a394b | 3641 | mutex_unlock(&dev->struct_mutex); |
dbb19d30 | 3642 | |
5f35308b CW |
3643 | ret = drm_irq_install(dev); |
3644 | if (ret) | |
3645 | goto cleanup_ringbuffer; | |
dbb19d30 | 3646 | |
673a394b | 3647 | return 0; |
5f35308b CW |
3648 | |
3649 | cleanup_ringbuffer: | |
3650 | mutex_lock(&dev->struct_mutex); | |
3651 | i915_gem_cleanup_ringbuffer(dev); | |
3652 | dev_priv->mm.suspended = 1; | |
3653 | mutex_unlock(&dev->struct_mutex); | |
3654 | ||
3655 | return ret; | |
673a394b EA |
3656 | } |
3657 | ||
3658 | int | |
3659 | i915_gem_leavevt_ioctl(struct drm_device *dev, void *data, | |
3660 | struct drm_file *file_priv) | |
3661 | { | |
79e53945 JB |
3662 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
3663 | return 0; | |
3664 | ||
dbb19d30 | 3665 | drm_irq_uninstall(dev); |
e6890f6f | 3666 | return i915_gem_idle(dev); |
673a394b EA |
3667 | } |
3668 | ||
3669 | void | |
3670 | i915_gem_lastclose(struct drm_device *dev) | |
3671 | { | |
3672 | int ret; | |
673a394b | 3673 | |
e806b495 EA |
3674 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
3675 | return; | |
3676 | ||
6dbe2772 KP |
3677 | ret = i915_gem_idle(dev); |
3678 | if (ret) | |
3679 | DRM_ERROR("failed to idle hardware: %d\n", ret); | |
673a394b EA |
3680 | } |
3681 | ||
64193406 CW |
3682 | static void |
3683 | init_ring_lists(struct intel_ring_buffer *ring) | |
3684 | { | |
3685 | INIT_LIST_HEAD(&ring->active_list); | |
3686 | INIT_LIST_HEAD(&ring->request_list); | |
3687 | INIT_LIST_HEAD(&ring->gpu_write_list); | |
3688 | } | |
3689 | ||
673a394b EA |
3690 | void |
3691 | i915_gem_load(struct drm_device *dev) | |
3692 | { | |
b5aa8a0f | 3693 | int i; |
673a394b EA |
3694 | drm_i915_private_t *dev_priv = dev->dev_private; |
3695 | ||
69dc4987 | 3696 | INIT_LIST_HEAD(&dev_priv->mm.active_list); |
673a394b EA |
3697 | INIT_LIST_HEAD(&dev_priv->mm.flushing_list); |
3698 | INIT_LIST_HEAD(&dev_priv->mm.inactive_list); | |
f13d3f73 | 3699 | INIT_LIST_HEAD(&dev_priv->mm.pinned_list); |
a09ba7fa | 3700 | INIT_LIST_HEAD(&dev_priv->mm.fence_list); |
be72615b | 3701 | INIT_LIST_HEAD(&dev_priv->mm.deferred_free_list); |
93a37f20 | 3702 | INIT_LIST_HEAD(&dev_priv->mm.gtt_list); |
1ec14ad3 CW |
3703 | for (i = 0; i < I915_NUM_RINGS; i++) |
3704 | init_ring_lists(&dev_priv->ring[i]); | |
4b9de737 | 3705 | for (i = 0; i < I915_MAX_NUM_FENCES; i++) |
007cc8ac | 3706 | INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list); |
673a394b EA |
3707 | INIT_DELAYED_WORK(&dev_priv->mm.retire_work, |
3708 | i915_gem_retire_work_handler); | |
30dbf0c0 | 3709 | init_completion(&dev_priv->error_completion); |
31169714 | 3710 | |
94400120 DA |
3711 | /* On GEN3 we really need to make sure the ARB C3 LP bit is set */ |
3712 | if (IS_GEN3(dev)) { | |
3713 | u32 tmp = I915_READ(MI_ARB_STATE); | |
3714 | if (!(tmp & MI_ARB_C3_LP_WRITE_ENABLE)) { | |
3715 | /* arb state is a masked write, so set bit + bit in mask */ | |
3716 | tmp = MI_ARB_C3_LP_WRITE_ENABLE | (MI_ARB_C3_LP_WRITE_ENABLE << MI_ARB_MASK_SHIFT); | |
3717 | I915_WRITE(MI_ARB_STATE, tmp); | |
3718 | } | |
3719 | } | |
3720 | ||
72bfa19c CW |
3721 | dev_priv->relative_constants_mode = I915_EXEC_CONSTANTS_REL_GENERAL; |
3722 | ||
de151cf6 | 3723 | /* Old X drivers will take 0-2 for front, back, depth buffers */ |
b397c836 EA |
3724 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) |
3725 | dev_priv->fence_reg_start = 3; | |
de151cf6 | 3726 | |
a6c45cf0 | 3727 | if (INTEL_INFO(dev)->gen >= 4 || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) |
de151cf6 JB |
3728 | dev_priv->num_fence_regs = 16; |
3729 | else | |
3730 | dev_priv->num_fence_regs = 8; | |
3731 | ||
b5aa8a0f | 3732 | /* Initialize fence registers to zero */ |
ada726c7 | 3733 | i915_gem_reset_fences(dev); |
10ed13e4 | 3734 | |
673a394b | 3735 | i915_gem_detect_bit_6_swizzle(dev); |
6b95a207 | 3736 | init_waitqueue_head(&dev_priv->pending_flip_queue); |
17250b71 | 3737 | |
ce453d81 CW |
3738 | dev_priv->mm.interruptible = true; |
3739 | ||
17250b71 CW |
3740 | dev_priv->mm.inactive_shrinker.shrink = i915_gem_inactive_shrink; |
3741 | dev_priv->mm.inactive_shrinker.seeks = DEFAULT_SEEKS; | |
3742 | register_shrinker(&dev_priv->mm.inactive_shrinker); | |
673a394b | 3743 | } |
71acb5eb DA |
3744 | |
3745 | /* | |
3746 | * Create a physically contiguous memory object for this object | |
3747 | * e.g. for cursor + overlay regs | |
3748 | */ | |
995b6762 CW |
3749 | static int i915_gem_init_phys_object(struct drm_device *dev, |
3750 | int id, int size, int align) | |
71acb5eb DA |
3751 | { |
3752 | drm_i915_private_t *dev_priv = dev->dev_private; | |
3753 | struct drm_i915_gem_phys_object *phys_obj; | |
3754 | int ret; | |
3755 | ||
3756 | if (dev_priv->mm.phys_objs[id - 1] || !size) | |
3757 | return 0; | |
3758 | ||
9a298b2a | 3759 | phys_obj = kzalloc(sizeof(struct drm_i915_gem_phys_object), GFP_KERNEL); |
71acb5eb DA |
3760 | if (!phys_obj) |
3761 | return -ENOMEM; | |
3762 | ||
3763 | phys_obj->id = id; | |
3764 | ||
6eeefaf3 | 3765 | phys_obj->handle = drm_pci_alloc(dev, size, align); |
71acb5eb DA |
3766 | if (!phys_obj->handle) { |
3767 | ret = -ENOMEM; | |
3768 | goto kfree_obj; | |
3769 | } | |
3770 | #ifdef CONFIG_X86 | |
3771 | set_memory_wc((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE); | |
3772 | #endif | |
3773 | ||
3774 | dev_priv->mm.phys_objs[id - 1] = phys_obj; | |
3775 | ||
3776 | return 0; | |
3777 | kfree_obj: | |
9a298b2a | 3778 | kfree(phys_obj); |
71acb5eb DA |
3779 | return ret; |
3780 | } | |
3781 | ||
995b6762 | 3782 | static void i915_gem_free_phys_object(struct drm_device *dev, int id) |
71acb5eb DA |
3783 | { |
3784 | drm_i915_private_t *dev_priv = dev->dev_private; | |
3785 | struct drm_i915_gem_phys_object *phys_obj; | |
3786 | ||
3787 | if (!dev_priv->mm.phys_objs[id - 1]) | |
3788 | return; | |
3789 | ||
3790 | phys_obj = dev_priv->mm.phys_objs[id - 1]; | |
3791 | if (phys_obj->cur_obj) { | |
3792 | i915_gem_detach_phys_object(dev, phys_obj->cur_obj); | |
3793 | } | |
3794 | ||
3795 | #ifdef CONFIG_X86 | |
3796 | set_memory_wb((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE); | |
3797 | #endif | |
3798 | drm_pci_free(dev, phys_obj->handle); | |
3799 | kfree(phys_obj); | |
3800 | dev_priv->mm.phys_objs[id - 1] = NULL; | |
3801 | } | |
3802 | ||
3803 | void i915_gem_free_all_phys_object(struct drm_device *dev) | |
3804 | { | |
3805 | int i; | |
3806 | ||
260883c8 | 3807 | for (i = I915_GEM_PHYS_CURSOR_0; i <= I915_MAX_PHYS_OBJECT; i++) |
71acb5eb DA |
3808 | i915_gem_free_phys_object(dev, i); |
3809 | } | |
3810 | ||
3811 | void i915_gem_detach_phys_object(struct drm_device *dev, | |
05394f39 | 3812 | struct drm_i915_gem_object *obj) |
71acb5eb | 3813 | { |
05394f39 | 3814 | struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping; |
e5281ccd | 3815 | char *vaddr; |
71acb5eb | 3816 | int i; |
71acb5eb DA |
3817 | int page_count; |
3818 | ||
05394f39 | 3819 | if (!obj->phys_obj) |
71acb5eb | 3820 | return; |
05394f39 | 3821 | vaddr = obj->phys_obj->handle->vaddr; |
71acb5eb | 3822 | |
05394f39 | 3823 | page_count = obj->base.size / PAGE_SIZE; |
71acb5eb | 3824 | for (i = 0; i < page_count; i++) { |
5949eac4 | 3825 | struct page *page = shmem_read_mapping_page(mapping, i); |
e5281ccd CW |
3826 | if (!IS_ERR(page)) { |
3827 | char *dst = kmap_atomic(page); | |
3828 | memcpy(dst, vaddr + i*PAGE_SIZE, PAGE_SIZE); | |
3829 | kunmap_atomic(dst); | |
3830 | ||
3831 | drm_clflush_pages(&page, 1); | |
3832 | ||
3833 | set_page_dirty(page); | |
3834 | mark_page_accessed(page); | |
3835 | page_cache_release(page); | |
3836 | } | |
71acb5eb | 3837 | } |
40ce6575 | 3838 | intel_gtt_chipset_flush(); |
d78b47b9 | 3839 | |
05394f39 CW |
3840 | obj->phys_obj->cur_obj = NULL; |
3841 | obj->phys_obj = NULL; | |
71acb5eb DA |
3842 | } |
3843 | ||
3844 | int | |
3845 | i915_gem_attach_phys_object(struct drm_device *dev, | |
05394f39 | 3846 | struct drm_i915_gem_object *obj, |
6eeefaf3 CW |
3847 | int id, |
3848 | int align) | |
71acb5eb | 3849 | { |
05394f39 | 3850 | struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping; |
71acb5eb | 3851 | drm_i915_private_t *dev_priv = dev->dev_private; |
71acb5eb DA |
3852 | int ret = 0; |
3853 | int page_count; | |
3854 | int i; | |
3855 | ||
3856 | if (id > I915_MAX_PHYS_OBJECT) | |
3857 | return -EINVAL; | |
3858 | ||
05394f39 CW |
3859 | if (obj->phys_obj) { |
3860 | if (obj->phys_obj->id == id) | |
71acb5eb DA |
3861 | return 0; |
3862 | i915_gem_detach_phys_object(dev, obj); | |
3863 | } | |
3864 | ||
71acb5eb DA |
3865 | /* create a new object */ |
3866 | if (!dev_priv->mm.phys_objs[id - 1]) { | |
3867 | ret = i915_gem_init_phys_object(dev, id, | |
05394f39 | 3868 | obj->base.size, align); |
71acb5eb | 3869 | if (ret) { |
05394f39 CW |
3870 | DRM_ERROR("failed to init phys object %d size: %zu\n", |
3871 | id, obj->base.size); | |
e5281ccd | 3872 | return ret; |
71acb5eb DA |
3873 | } |
3874 | } | |
3875 | ||
3876 | /* bind to the object */ | |
05394f39 CW |
3877 | obj->phys_obj = dev_priv->mm.phys_objs[id - 1]; |
3878 | obj->phys_obj->cur_obj = obj; | |
71acb5eb | 3879 | |
05394f39 | 3880 | page_count = obj->base.size / PAGE_SIZE; |
71acb5eb DA |
3881 | |
3882 | for (i = 0; i < page_count; i++) { | |
e5281ccd CW |
3883 | struct page *page; |
3884 | char *dst, *src; | |
3885 | ||
5949eac4 | 3886 | page = shmem_read_mapping_page(mapping, i); |
e5281ccd CW |
3887 | if (IS_ERR(page)) |
3888 | return PTR_ERR(page); | |
71acb5eb | 3889 | |
ff75b9bc | 3890 | src = kmap_atomic(page); |
05394f39 | 3891 | dst = obj->phys_obj->handle->vaddr + (i * PAGE_SIZE); |
71acb5eb | 3892 | memcpy(dst, src, PAGE_SIZE); |
3e4d3af5 | 3893 | kunmap_atomic(src); |
71acb5eb | 3894 | |
e5281ccd CW |
3895 | mark_page_accessed(page); |
3896 | page_cache_release(page); | |
3897 | } | |
d78b47b9 | 3898 | |
71acb5eb | 3899 | return 0; |
71acb5eb DA |
3900 | } |
3901 | ||
3902 | static int | |
05394f39 CW |
3903 | i915_gem_phys_pwrite(struct drm_device *dev, |
3904 | struct drm_i915_gem_object *obj, | |
71acb5eb DA |
3905 | struct drm_i915_gem_pwrite *args, |
3906 | struct drm_file *file_priv) | |
3907 | { | |
05394f39 | 3908 | void *vaddr = obj->phys_obj->handle->vaddr + args->offset; |
b47b30cc | 3909 | char __user *user_data = (char __user *) (uintptr_t) args->data_ptr; |
71acb5eb | 3910 | |
b47b30cc CW |
3911 | if (__copy_from_user_inatomic_nocache(vaddr, user_data, args->size)) { |
3912 | unsigned long unwritten; | |
3913 | ||
3914 | /* The physical object once assigned is fixed for the lifetime | |
3915 | * of the obj, so we can safely drop the lock and continue | |
3916 | * to access vaddr. | |
3917 | */ | |
3918 | mutex_unlock(&dev->struct_mutex); | |
3919 | unwritten = copy_from_user(vaddr, user_data, args->size); | |
3920 | mutex_lock(&dev->struct_mutex); | |
3921 | if (unwritten) | |
3922 | return -EFAULT; | |
3923 | } | |
71acb5eb | 3924 | |
40ce6575 | 3925 | intel_gtt_chipset_flush(); |
71acb5eb DA |
3926 | return 0; |
3927 | } | |
b962442e | 3928 | |
f787a5f5 | 3929 | void i915_gem_release(struct drm_device *dev, struct drm_file *file) |
b962442e | 3930 | { |
f787a5f5 | 3931 | struct drm_i915_file_private *file_priv = file->driver_priv; |
b962442e EA |
3932 | |
3933 | /* Clean up our request list when the client is going away, so that | |
3934 | * later retire_requests won't dereference our soon-to-be-gone | |
3935 | * file_priv. | |
3936 | */ | |
1c25595f | 3937 | spin_lock(&file_priv->mm.lock); |
f787a5f5 CW |
3938 | while (!list_empty(&file_priv->mm.request_list)) { |
3939 | struct drm_i915_gem_request *request; | |
3940 | ||
3941 | request = list_first_entry(&file_priv->mm.request_list, | |
3942 | struct drm_i915_gem_request, | |
3943 | client_list); | |
3944 | list_del(&request->client_list); | |
3945 | request->file_priv = NULL; | |
3946 | } | |
1c25595f | 3947 | spin_unlock(&file_priv->mm.lock); |
b962442e | 3948 | } |
31169714 | 3949 | |
1637ef41 CW |
3950 | static int |
3951 | i915_gpu_is_active(struct drm_device *dev) | |
3952 | { | |
3953 | drm_i915_private_t *dev_priv = dev->dev_private; | |
3954 | int lists_empty; | |
3955 | ||
1637ef41 | 3956 | lists_empty = list_empty(&dev_priv->mm.flushing_list) && |
17250b71 | 3957 | list_empty(&dev_priv->mm.active_list); |
1637ef41 CW |
3958 | |
3959 | return !lists_empty; | |
3960 | } | |
3961 | ||
31169714 | 3962 | static int |
1495f230 | 3963 | i915_gem_inactive_shrink(struct shrinker *shrinker, struct shrink_control *sc) |
31169714 | 3964 | { |
17250b71 CW |
3965 | struct drm_i915_private *dev_priv = |
3966 | container_of(shrinker, | |
3967 | struct drm_i915_private, | |
3968 | mm.inactive_shrinker); | |
3969 | struct drm_device *dev = dev_priv->dev; | |
3970 | struct drm_i915_gem_object *obj, *next; | |
1495f230 | 3971 | int nr_to_scan = sc->nr_to_scan; |
17250b71 CW |
3972 | int cnt; |
3973 | ||
3974 | if (!mutex_trylock(&dev->struct_mutex)) | |
bbe2e11a | 3975 | return 0; |
31169714 CW |
3976 | |
3977 | /* "fast-path" to count number of available objects */ | |
3978 | if (nr_to_scan == 0) { | |
17250b71 CW |
3979 | cnt = 0; |
3980 | list_for_each_entry(obj, | |
3981 | &dev_priv->mm.inactive_list, | |
3982 | mm_list) | |
3983 | cnt++; | |
3984 | mutex_unlock(&dev->struct_mutex); | |
3985 | return cnt / 100 * sysctl_vfs_cache_pressure; | |
31169714 CW |
3986 | } |
3987 | ||
1637ef41 | 3988 | rescan: |
31169714 | 3989 | /* first scan for clean buffers */ |
17250b71 | 3990 | i915_gem_retire_requests(dev); |
31169714 | 3991 | |
17250b71 CW |
3992 | list_for_each_entry_safe(obj, next, |
3993 | &dev_priv->mm.inactive_list, | |
3994 | mm_list) { | |
3995 | if (i915_gem_object_is_purgeable(obj)) { | |
2021746e CW |
3996 | if (i915_gem_object_unbind(obj) == 0 && |
3997 | --nr_to_scan == 0) | |
17250b71 | 3998 | break; |
31169714 | 3999 | } |
31169714 CW |
4000 | } |
4001 | ||
4002 | /* second pass, evict/count anything still on the inactive list */ | |
17250b71 CW |
4003 | cnt = 0; |
4004 | list_for_each_entry_safe(obj, next, | |
4005 | &dev_priv->mm.inactive_list, | |
4006 | mm_list) { | |
2021746e CW |
4007 | if (nr_to_scan && |
4008 | i915_gem_object_unbind(obj) == 0) | |
17250b71 | 4009 | nr_to_scan--; |
2021746e | 4010 | else |
17250b71 CW |
4011 | cnt++; |
4012 | } | |
4013 | ||
4014 | if (nr_to_scan && i915_gpu_is_active(dev)) { | |
1637ef41 CW |
4015 | /* |
4016 | * We are desperate for pages, so as a last resort, wait | |
4017 | * for the GPU to finish and discard whatever we can. | |
4018 | * This has a dramatic impact to reduce the number of | |
4019 | * OOM-killer events whilst running the GPU aggressively. | |
4020 | */ | |
b93f9cf1 | 4021 | if (i915_gpu_idle(dev, true) == 0) |
1637ef41 CW |
4022 | goto rescan; |
4023 | } | |
17250b71 CW |
4024 | mutex_unlock(&dev->struct_mutex); |
4025 | return cnt / 100 * sysctl_vfs_cache_pressure; | |
31169714 | 4026 | } |