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Commit | Line | Data |
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673a394b EA |
1 | /* |
2 | * Copyright © 2008 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | * | |
26 | */ | |
27 | ||
760285e7 | 28 | #include <drm/drmP.h> |
0de23977 | 29 | #include <drm/drm_vma_manager.h> |
760285e7 | 30 | #include <drm/i915_drm.h> |
673a394b | 31 | #include "i915_drv.h" |
1c5d22f7 | 32 | #include "i915_trace.h" |
652c393a | 33 | #include "intel_drv.h" |
2cfcd32a | 34 | #include <linux/oom.h> |
5949eac4 | 35 | #include <linux/shmem_fs.h> |
5a0e3ad6 | 36 | #include <linux/slab.h> |
673a394b | 37 | #include <linux/swap.h> |
79e53945 | 38 | #include <linux/pci.h> |
1286ff73 | 39 | #include <linux/dma-buf.h> |
673a394b | 40 | |
05394f39 | 41 | static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj); |
2c22569b CW |
42 | static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj, |
43 | bool force); | |
07fe0b12 | 44 | static __must_check int |
23f54483 BW |
45 | i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj, |
46 | bool readonly); | |
c8725f3d CW |
47 | static void |
48 | i915_gem_object_retire(struct drm_i915_gem_object *obj); | |
49 | ||
61050808 CW |
50 | static void i915_gem_write_fence(struct drm_device *dev, int reg, |
51 | struct drm_i915_gem_object *obj); | |
52 | static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj, | |
53 | struct drm_i915_fence_reg *fence, | |
54 | bool enable); | |
55 | ||
ceabbba5 | 56 | static unsigned long i915_gem_shrinker_count(struct shrinker *shrinker, |
7dc19d5a | 57 | struct shrink_control *sc); |
ceabbba5 | 58 | static unsigned long i915_gem_shrinker_scan(struct shrinker *shrinker, |
7dc19d5a | 59 | struct shrink_control *sc); |
2cfcd32a CW |
60 | static int i915_gem_shrinker_oom(struct notifier_block *nb, |
61 | unsigned long event, | |
62 | void *ptr); | |
d9973b43 | 63 | static unsigned long i915_gem_shrink_all(struct drm_i915_private *dev_priv); |
31169714 | 64 | |
c76ce038 CW |
65 | static bool cpu_cache_is_coherent(struct drm_device *dev, |
66 | enum i915_cache_level level) | |
67 | { | |
68 | return HAS_LLC(dev) || level != I915_CACHE_NONE; | |
69 | } | |
70 | ||
2c22569b CW |
71 | static bool cpu_write_needs_clflush(struct drm_i915_gem_object *obj) |
72 | { | |
73 | if (!cpu_cache_is_coherent(obj->base.dev, obj->cache_level)) | |
74 | return true; | |
75 | ||
76 | return obj->pin_display; | |
77 | } | |
78 | ||
61050808 CW |
79 | static inline void i915_gem_object_fence_lost(struct drm_i915_gem_object *obj) |
80 | { | |
81 | if (obj->tiling_mode) | |
82 | i915_gem_release_mmap(obj); | |
83 | ||
84 | /* As we do not have an associated fence register, we will force | |
85 | * a tiling change if we ever need to acquire one. | |
86 | */ | |
5d82e3e6 | 87 | obj->fence_dirty = false; |
61050808 CW |
88 | obj->fence_reg = I915_FENCE_REG_NONE; |
89 | } | |
90 | ||
73aa808f CW |
91 | /* some bookkeeping */ |
92 | static void i915_gem_info_add_obj(struct drm_i915_private *dev_priv, | |
93 | size_t size) | |
94 | { | |
c20e8355 | 95 | spin_lock(&dev_priv->mm.object_stat_lock); |
73aa808f CW |
96 | dev_priv->mm.object_count++; |
97 | dev_priv->mm.object_memory += size; | |
c20e8355 | 98 | spin_unlock(&dev_priv->mm.object_stat_lock); |
73aa808f CW |
99 | } |
100 | ||
101 | static void i915_gem_info_remove_obj(struct drm_i915_private *dev_priv, | |
102 | size_t size) | |
103 | { | |
c20e8355 | 104 | spin_lock(&dev_priv->mm.object_stat_lock); |
73aa808f CW |
105 | dev_priv->mm.object_count--; |
106 | dev_priv->mm.object_memory -= size; | |
c20e8355 | 107 | spin_unlock(&dev_priv->mm.object_stat_lock); |
73aa808f CW |
108 | } |
109 | ||
21dd3734 | 110 | static int |
33196ded | 111 | i915_gem_wait_for_error(struct i915_gpu_error *error) |
30dbf0c0 | 112 | { |
30dbf0c0 CW |
113 | int ret; |
114 | ||
7abb690a DV |
115 | #define EXIT_COND (!i915_reset_in_progress(error) || \ |
116 | i915_terminally_wedged(error)) | |
1f83fee0 | 117 | if (EXIT_COND) |
30dbf0c0 CW |
118 | return 0; |
119 | ||
0a6759c6 DV |
120 | /* |
121 | * Only wait 10 seconds for the gpu reset to complete to avoid hanging | |
122 | * userspace. If it takes that long something really bad is going on and | |
123 | * we should simply try to bail out and fail as gracefully as possible. | |
124 | */ | |
1f83fee0 DV |
125 | ret = wait_event_interruptible_timeout(error->reset_queue, |
126 | EXIT_COND, | |
127 | 10*HZ); | |
0a6759c6 DV |
128 | if (ret == 0) { |
129 | DRM_ERROR("Timed out waiting for the gpu reset to complete\n"); | |
130 | return -EIO; | |
131 | } else if (ret < 0) { | |
30dbf0c0 | 132 | return ret; |
0a6759c6 | 133 | } |
1f83fee0 | 134 | #undef EXIT_COND |
30dbf0c0 | 135 | |
21dd3734 | 136 | return 0; |
30dbf0c0 CW |
137 | } |
138 | ||
54cf91dc | 139 | int i915_mutex_lock_interruptible(struct drm_device *dev) |
76c1dec1 | 140 | { |
33196ded | 141 | struct drm_i915_private *dev_priv = dev->dev_private; |
76c1dec1 CW |
142 | int ret; |
143 | ||
33196ded | 144 | ret = i915_gem_wait_for_error(&dev_priv->gpu_error); |
76c1dec1 CW |
145 | if (ret) |
146 | return ret; | |
147 | ||
148 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
149 | if (ret) | |
150 | return ret; | |
151 | ||
23bc5982 | 152 | WARN_ON(i915_verify_lists(dev)); |
76c1dec1 CW |
153 | return 0; |
154 | } | |
30dbf0c0 | 155 | |
7d1c4804 | 156 | static inline bool |
05394f39 | 157 | i915_gem_object_is_inactive(struct drm_i915_gem_object *obj) |
7d1c4804 | 158 | { |
9843877d | 159 | return i915_gem_obj_bound_any(obj) && !obj->active; |
7d1c4804 CW |
160 | } |
161 | ||
5a125c3c EA |
162 | int |
163 | i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 164 | struct drm_file *file) |
5a125c3c | 165 | { |
73aa808f | 166 | struct drm_i915_private *dev_priv = dev->dev_private; |
5a125c3c | 167 | struct drm_i915_gem_get_aperture *args = data; |
6299f992 CW |
168 | struct drm_i915_gem_object *obj; |
169 | size_t pinned; | |
5a125c3c | 170 | |
6299f992 | 171 | pinned = 0; |
73aa808f | 172 | mutex_lock(&dev->struct_mutex); |
35c20a60 | 173 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) |
d7f46fc4 | 174 | if (i915_gem_obj_is_pinned(obj)) |
f343c5f6 | 175 | pinned += i915_gem_obj_ggtt_size(obj); |
73aa808f | 176 | mutex_unlock(&dev->struct_mutex); |
5a125c3c | 177 | |
853ba5d2 | 178 | args->aper_size = dev_priv->gtt.base.total; |
0206e353 | 179 | args->aper_available_size = args->aper_size - pinned; |
6299f992 | 180 | |
5a125c3c EA |
181 | return 0; |
182 | } | |
183 | ||
6a2c4232 CW |
184 | static int |
185 | i915_gem_object_get_pages_phys(struct drm_i915_gem_object *obj) | |
00731155 | 186 | { |
6a2c4232 CW |
187 | struct address_space *mapping = file_inode(obj->base.filp)->i_mapping; |
188 | char *vaddr = obj->phys_handle->vaddr; | |
189 | struct sg_table *st; | |
190 | struct scatterlist *sg; | |
191 | int i; | |
00731155 | 192 | |
6a2c4232 CW |
193 | if (WARN_ON(i915_gem_object_needs_bit17_swizzle(obj))) |
194 | return -EINVAL; | |
195 | ||
196 | for (i = 0; i < obj->base.size / PAGE_SIZE; i++) { | |
197 | struct page *page; | |
198 | char *src; | |
199 | ||
200 | page = shmem_read_mapping_page(mapping, i); | |
201 | if (IS_ERR(page)) | |
202 | return PTR_ERR(page); | |
203 | ||
204 | src = kmap_atomic(page); | |
205 | memcpy(vaddr, src, PAGE_SIZE); | |
206 | drm_clflush_virt_range(vaddr, PAGE_SIZE); | |
207 | kunmap_atomic(src); | |
208 | ||
209 | page_cache_release(page); | |
210 | vaddr += PAGE_SIZE; | |
211 | } | |
212 | ||
213 | i915_gem_chipset_flush(obj->base.dev); | |
214 | ||
215 | st = kmalloc(sizeof(*st), GFP_KERNEL); | |
216 | if (st == NULL) | |
217 | return -ENOMEM; | |
218 | ||
219 | if (sg_alloc_table(st, 1, GFP_KERNEL)) { | |
220 | kfree(st); | |
221 | return -ENOMEM; | |
222 | } | |
223 | ||
224 | sg = st->sgl; | |
225 | sg->offset = 0; | |
226 | sg->length = obj->base.size; | |
00731155 | 227 | |
6a2c4232 CW |
228 | sg_dma_address(sg) = obj->phys_handle->busaddr; |
229 | sg_dma_len(sg) = obj->base.size; | |
230 | ||
231 | obj->pages = st; | |
232 | obj->has_dma_mapping = true; | |
233 | return 0; | |
234 | } | |
235 | ||
236 | static void | |
237 | i915_gem_object_put_pages_phys(struct drm_i915_gem_object *obj) | |
238 | { | |
239 | int ret; | |
240 | ||
241 | BUG_ON(obj->madv == __I915_MADV_PURGED); | |
00731155 | 242 | |
6a2c4232 CW |
243 | ret = i915_gem_object_set_to_cpu_domain(obj, true); |
244 | if (ret) { | |
245 | /* In the event of a disaster, abandon all caches and | |
246 | * hope for the best. | |
247 | */ | |
248 | WARN_ON(ret != -EIO); | |
249 | obj->base.read_domains = obj->base.write_domain = I915_GEM_DOMAIN_CPU; | |
250 | } | |
251 | ||
252 | if (obj->madv == I915_MADV_DONTNEED) | |
253 | obj->dirty = 0; | |
254 | ||
255 | if (obj->dirty) { | |
00731155 | 256 | struct address_space *mapping = file_inode(obj->base.filp)->i_mapping; |
6a2c4232 | 257 | char *vaddr = obj->phys_handle->vaddr; |
00731155 CW |
258 | int i; |
259 | ||
260 | for (i = 0; i < obj->base.size / PAGE_SIZE; i++) { | |
6a2c4232 CW |
261 | struct page *page; |
262 | char *dst; | |
263 | ||
264 | page = shmem_read_mapping_page(mapping, i); | |
265 | if (IS_ERR(page)) | |
266 | continue; | |
267 | ||
268 | dst = kmap_atomic(page); | |
269 | drm_clflush_virt_range(vaddr, PAGE_SIZE); | |
270 | memcpy(dst, vaddr, PAGE_SIZE); | |
271 | kunmap_atomic(dst); | |
272 | ||
273 | set_page_dirty(page); | |
274 | if (obj->madv == I915_MADV_WILLNEED) | |
00731155 | 275 | mark_page_accessed(page); |
6a2c4232 | 276 | page_cache_release(page); |
00731155 CW |
277 | vaddr += PAGE_SIZE; |
278 | } | |
6a2c4232 | 279 | obj->dirty = 0; |
00731155 CW |
280 | } |
281 | ||
6a2c4232 CW |
282 | sg_free_table(obj->pages); |
283 | kfree(obj->pages); | |
284 | ||
285 | obj->has_dma_mapping = false; | |
286 | } | |
287 | ||
288 | static void | |
289 | i915_gem_object_release_phys(struct drm_i915_gem_object *obj) | |
290 | { | |
291 | drm_pci_free(obj->base.dev, obj->phys_handle); | |
292 | } | |
293 | ||
294 | static const struct drm_i915_gem_object_ops i915_gem_phys_ops = { | |
295 | .get_pages = i915_gem_object_get_pages_phys, | |
296 | .put_pages = i915_gem_object_put_pages_phys, | |
297 | .release = i915_gem_object_release_phys, | |
298 | }; | |
299 | ||
300 | static int | |
301 | drop_pages(struct drm_i915_gem_object *obj) | |
302 | { | |
303 | struct i915_vma *vma, *next; | |
304 | int ret; | |
305 | ||
306 | drm_gem_object_reference(&obj->base); | |
307 | list_for_each_entry_safe(vma, next, &obj->vma_list, vma_link) | |
308 | if (i915_vma_unbind(vma)) | |
309 | break; | |
310 | ||
311 | ret = i915_gem_object_put_pages(obj); | |
312 | drm_gem_object_unreference(&obj->base); | |
313 | ||
314 | return ret; | |
00731155 CW |
315 | } |
316 | ||
317 | int | |
318 | i915_gem_object_attach_phys(struct drm_i915_gem_object *obj, | |
319 | int align) | |
320 | { | |
321 | drm_dma_handle_t *phys; | |
6a2c4232 | 322 | int ret; |
00731155 CW |
323 | |
324 | if (obj->phys_handle) { | |
325 | if ((unsigned long)obj->phys_handle->vaddr & (align -1)) | |
326 | return -EBUSY; | |
327 | ||
328 | return 0; | |
329 | } | |
330 | ||
331 | if (obj->madv != I915_MADV_WILLNEED) | |
332 | return -EFAULT; | |
333 | ||
334 | if (obj->base.filp == NULL) | |
335 | return -EINVAL; | |
336 | ||
6a2c4232 CW |
337 | ret = drop_pages(obj); |
338 | if (ret) | |
339 | return ret; | |
340 | ||
00731155 CW |
341 | /* create a new object */ |
342 | phys = drm_pci_alloc(obj->base.dev, obj->base.size, align); | |
343 | if (!phys) | |
344 | return -ENOMEM; | |
345 | ||
00731155 | 346 | obj->phys_handle = phys; |
6a2c4232 CW |
347 | obj->ops = &i915_gem_phys_ops; |
348 | ||
349 | return i915_gem_object_get_pages(obj); | |
00731155 CW |
350 | } |
351 | ||
352 | static int | |
353 | i915_gem_phys_pwrite(struct drm_i915_gem_object *obj, | |
354 | struct drm_i915_gem_pwrite *args, | |
355 | struct drm_file *file_priv) | |
356 | { | |
357 | struct drm_device *dev = obj->base.dev; | |
358 | void *vaddr = obj->phys_handle->vaddr + args->offset; | |
359 | char __user *user_data = to_user_ptr(args->data_ptr); | |
6a2c4232 CW |
360 | int ret; |
361 | ||
362 | /* We manually control the domain here and pretend that it | |
363 | * remains coherent i.e. in the GTT domain, like shmem_pwrite. | |
364 | */ | |
365 | ret = i915_gem_object_wait_rendering(obj, false); | |
366 | if (ret) | |
367 | return ret; | |
00731155 CW |
368 | |
369 | if (__copy_from_user_inatomic_nocache(vaddr, user_data, args->size)) { | |
370 | unsigned long unwritten; | |
371 | ||
372 | /* The physical object once assigned is fixed for the lifetime | |
373 | * of the obj, so we can safely drop the lock and continue | |
374 | * to access vaddr. | |
375 | */ | |
376 | mutex_unlock(&dev->struct_mutex); | |
377 | unwritten = copy_from_user(vaddr, user_data, args->size); | |
378 | mutex_lock(&dev->struct_mutex); | |
379 | if (unwritten) | |
380 | return -EFAULT; | |
381 | } | |
382 | ||
6a2c4232 | 383 | drm_clflush_virt_range(vaddr, args->size); |
00731155 CW |
384 | i915_gem_chipset_flush(dev); |
385 | return 0; | |
386 | } | |
387 | ||
42dcedd4 CW |
388 | void *i915_gem_object_alloc(struct drm_device *dev) |
389 | { | |
390 | struct drm_i915_private *dev_priv = dev->dev_private; | |
fac15c10 | 391 | return kmem_cache_zalloc(dev_priv->slab, GFP_KERNEL); |
42dcedd4 CW |
392 | } |
393 | ||
394 | void i915_gem_object_free(struct drm_i915_gem_object *obj) | |
395 | { | |
396 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; | |
397 | kmem_cache_free(dev_priv->slab, obj); | |
398 | } | |
399 | ||
ff72145b DA |
400 | static int |
401 | i915_gem_create(struct drm_file *file, | |
402 | struct drm_device *dev, | |
403 | uint64_t size, | |
355a7018 | 404 | bool dumb, |
ff72145b | 405 | uint32_t *handle_p) |
673a394b | 406 | { |
05394f39 | 407 | struct drm_i915_gem_object *obj; |
a1a2d1d3 PP |
408 | int ret; |
409 | u32 handle; | |
673a394b | 410 | |
ff72145b | 411 | size = roundup(size, PAGE_SIZE); |
8ffc0246 CW |
412 | if (size == 0) |
413 | return -EINVAL; | |
673a394b EA |
414 | |
415 | /* Allocate the new object */ | |
ff72145b | 416 | obj = i915_gem_alloc_object(dev, size); |
673a394b EA |
417 | if (obj == NULL) |
418 | return -ENOMEM; | |
419 | ||
355a7018 | 420 | obj->base.dumb = dumb; |
05394f39 | 421 | ret = drm_gem_handle_create(file, &obj->base, &handle); |
202f2fef | 422 | /* drop reference from allocate - handle holds it now */ |
d861e338 DV |
423 | drm_gem_object_unreference_unlocked(&obj->base); |
424 | if (ret) | |
425 | return ret; | |
202f2fef | 426 | |
ff72145b | 427 | *handle_p = handle; |
673a394b EA |
428 | return 0; |
429 | } | |
430 | ||
ff72145b DA |
431 | int |
432 | i915_gem_dumb_create(struct drm_file *file, | |
433 | struct drm_device *dev, | |
434 | struct drm_mode_create_dumb *args) | |
435 | { | |
436 | /* have to work out size/pitch and return them */ | |
de45eaf7 | 437 | args->pitch = ALIGN(args->width * DIV_ROUND_UP(args->bpp, 8), 64); |
ff72145b DA |
438 | args->size = args->pitch * args->height; |
439 | return i915_gem_create(file, dev, | |
355a7018 | 440 | args->size, true, &args->handle); |
ff72145b DA |
441 | } |
442 | ||
ff72145b DA |
443 | /** |
444 | * Creates a new mm object and returns a handle to it. | |
445 | */ | |
446 | int | |
447 | i915_gem_create_ioctl(struct drm_device *dev, void *data, | |
448 | struct drm_file *file) | |
449 | { | |
450 | struct drm_i915_gem_create *args = data; | |
63ed2cb2 | 451 | |
ff72145b | 452 | return i915_gem_create(file, dev, |
355a7018 | 453 | args->size, false, &args->handle); |
ff72145b DA |
454 | } |
455 | ||
8461d226 DV |
456 | static inline int |
457 | __copy_to_user_swizzled(char __user *cpu_vaddr, | |
458 | const char *gpu_vaddr, int gpu_offset, | |
459 | int length) | |
460 | { | |
461 | int ret, cpu_offset = 0; | |
462 | ||
463 | while (length > 0) { | |
464 | int cacheline_end = ALIGN(gpu_offset + 1, 64); | |
465 | int this_length = min(cacheline_end - gpu_offset, length); | |
466 | int swizzled_gpu_offset = gpu_offset ^ 64; | |
467 | ||
468 | ret = __copy_to_user(cpu_vaddr + cpu_offset, | |
469 | gpu_vaddr + swizzled_gpu_offset, | |
470 | this_length); | |
471 | if (ret) | |
472 | return ret + length; | |
473 | ||
474 | cpu_offset += this_length; | |
475 | gpu_offset += this_length; | |
476 | length -= this_length; | |
477 | } | |
478 | ||
479 | return 0; | |
480 | } | |
481 | ||
8c59967c | 482 | static inline int |
4f0c7cfb BW |
483 | __copy_from_user_swizzled(char *gpu_vaddr, int gpu_offset, |
484 | const char __user *cpu_vaddr, | |
8c59967c DV |
485 | int length) |
486 | { | |
487 | int ret, cpu_offset = 0; | |
488 | ||
489 | while (length > 0) { | |
490 | int cacheline_end = ALIGN(gpu_offset + 1, 64); | |
491 | int this_length = min(cacheline_end - gpu_offset, length); | |
492 | int swizzled_gpu_offset = gpu_offset ^ 64; | |
493 | ||
494 | ret = __copy_from_user(gpu_vaddr + swizzled_gpu_offset, | |
495 | cpu_vaddr + cpu_offset, | |
496 | this_length); | |
497 | if (ret) | |
498 | return ret + length; | |
499 | ||
500 | cpu_offset += this_length; | |
501 | gpu_offset += this_length; | |
502 | length -= this_length; | |
503 | } | |
504 | ||
505 | return 0; | |
506 | } | |
507 | ||
4c914c0c BV |
508 | /* |
509 | * Pins the specified object's pages and synchronizes the object with | |
510 | * GPU accesses. Sets needs_clflush to non-zero if the caller should | |
511 | * flush the object from the CPU cache. | |
512 | */ | |
513 | int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj, | |
514 | int *needs_clflush) | |
515 | { | |
516 | int ret; | |
517 | ||
518 | *needs_clflush = 0; | |
519 | ||
520 | if (!obj->base.filp) | |
521 | return -EINVAL; | |
522 | ||
523 | if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU)) { | |
524 | /* If we're not in the cpu read domain, set ourself into the gtt | |
525 | * read domain and manually flush cachelines (if required). This | |
526 | * optimizes for the case when the gpu will dirty the data | |
527 | * anyway again before the next pread happens. */ | |
528 | *needs_clflush = !cpu_cache_is_coherent(obj->base.dev, | |
529 | obj->cache_level); | |
530 | ret = i915_gem_object_wait_rendering(obj, true); | |
531 | if (ret) | |
532 | return ret; | |
c8725f3d CW |
533 | |
534 | i915_gem_object_retire(obj); | |
4c914c0c BV |
535 | } |
536 | ||
537 | ret = i915_gem_object_get_pages(obj); | |
538 | if (ret) | |
539 | return ret; | |
540 | ||
541 | i915_gem_object_pin_pages(obj); | |
542 | ||
543 | return ret; | |
544 | } | |
545 | ||
d174bd64 DV |
546 | /* Per-page copy function for the shmem pread fastpath. |
547 | * Flushes invalid cachelines before reading the target if | |
548 | * needs_clflush is set. */ | |
eb01459f | 549 | static int |
d174bd64 DV |
550 | shmem_pread_fast(struct page *page, int shmem_page_offset, int page_length, |
551 | char __user *user_data, | |
552 | bool page_do_bit17_swizzling, bool needs_clflush) | |
553 | { | |
554 | char *vaddr; | |
555 | int ret; | |
556 | ||
e7e58eb5 | 557 | if (unlikely(page_do_bit17_swizzling)) |
d174bd64 DV |
558 | return -EINVAL; |
559 | ||
560 | vaddr = kmap_atomic(page); | |
561 | if (needs_clflush) | |
562 | drm_clflush_virt_range(vaddr + shmem_page_offset, | |
563 | page_length); | |
564 | ret = __copy_to_user_inatomic(user_data, | |
565 | vaddr + shmem_page_offset, | |
566 | page_length); | |
567 | kunmap_atomic(vaddr); | |
568 | ||
f60d7f0c | 569 | return ret ? -EFAULT : 0; |
d174bd64 DV |
570 | } |
571 | ||
23c18c71 DV |
572 | static void |
573 | shmem_clflush_swizzled_range(char *addr, unsigned long length, | |
574 | bool swizzled) | |
575 | { | |
e7e58eb5 | 576 | if (unlikely(swizzled)) { |
23c18c71 DV |
577 | unsigned long start = (unsigned long) addr; |
578 | unsigned long end = (unsigned long) addr + length; | |
579 | ||
580 | /* For swizzling simply ensure that we always flush both | |
581 | * channels. Lame, but simple and it works. Swizzled | |
582 | * pwrite/pread is far from a hotpath - current userspace | |
583 | * doesn't use it at all. */ | |
584 | start = round_down(start, 128); | |
585 | end = round_up(end, 128); | |
586 | ||
587 | drm_clflush_virt_range((void *)start, end - start); | |
588 | } else { | |
589 | drm_clflush_virt_range(addr, length); | |
590 | } | |
591 | ||
592 | } | |
593 | ||
d174bd64 DV |
594 | /* Only difference to the fast-path function is that this can handle bit17 |
595 | * and uses non-atomic copy and kmap functions. */ | |
596 | static int | |
597 | shmem_pread_slow(struct page *page, int shmem_page_offset, int page_length, | |
598 | char __user *user_data, | |
599 | bool page_do_bit17_swizzling, bool needs_clflush) | |
600 | { | |
601 | char *vaddr; | |
602 | int ret; | |
603 | ||
604 | vaddr = kmap(page); | |
605 | if (needs_clflush) | |
23c18c71 DV |
606 | shmem_clflush_swizzled_range(vaddr + shmem_page_offset, |
607 | page_length, | |
608 | page_do_bit17_swizzling); | |
d174bd64 DV |
609 | |
610 | if (page_do_bit17_swizzling) | |
611 | ret = __copy_to_user_swizzled(user_data, | |
612 | vaddr, shmem_page_offset, | |
613 | page_length); | |
614 | else | |
615 | ret = __copy_to_user(user_data, | |
616 | vaddr + shmem_page_offset, | |
617 | page_length); | |
618 | kunmap(page); | |
619 | ||
f60d7f0c | 620 | return ret ? - EFAULT : 0; |
d174bd64 DV |
621 | } |
622 | ||
eb01459f | 623 | static int |
dbf7bff0 DV |
624 | i915_gem_shmem_pread(struct drm_device *dev, |
625 | struct drm_i915_gem_object *obj, | |
626 | struct drm_i915_gem_pread *args, | |
627 | struct drm_file *file) | |
eb01459f | 628 | { |
8461d226 | 629 | char __user *user_data; |
eb01459f | 630 | ssize_t remain; |
8461d226 | 631 | loff_t offset; |
eb2c0c81 | 632 | int shmem_page_offset, page_length, ret = 0; |
8461d226 | 633 | int obj_do_bit17_swizzling, page_do_bit17_swizzling; |
96d79b52 | 634 | int prefaulted = 0; |
8489731c | 635 | int needs_clflush = 0; |
67d5a50c | 636 | struct sg_page_iter sg_iter; |
eb01459f | 637 | |
2bb4629a | 638 | user_data = to_user_ptr(args->data_ptr); |
eb01459f EA |
639 | remain = args->size; |
640 | ||
8461d226 | 641 | obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj); |
eb01459f | 642 | |
4c914c0c | 643 | ret = i915_gem_obj_prepare_shmem_read(obj, &needs_clflush); |
f60d7f0c CW |
644 | if (ret) |
645 | return ret; | |
646 | ||
8461d226 | 647 | offset = args->offset; |
eb01459f | 648 | |
67d5a50c ID |
649 | for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, |
650 | offset >> PAGE_SHIFT) { | |
2db76d7c | 651 | struct page *page = sg_page_iter_page(&sg_iter); |
9da3da66 CW |
652 | |
653 | if (remain <= 0) | |
654 | break; | |
655 | ||
eb01459f EA |
656 | /* Operation in this page |
657 | * | |
eb01459f | 658 | * shmem_page_offset = offset within page in shmem file |
eb01459f EA |
659 | * page_length = bytes to copy for this page |
660 | */ | |
c8cbbb8b | 661 | shmem_page_offset = offset_in_page(offset); |
eb01459f EA |
662 | page_length = remain; |
663 | if ((shmem_page_offset + page_length) > PAGE_SIZE) | |
664 | page_length = PAGE_SIZE - shmem_page_offset; | |
eb01459f | 665 | |
8461d226 DV |
666 | page_do_bit17_swizzling = obj_do_bit17_swizzling && |
667 | (page_to_phys(page) & (1 << 17)) != 0; | |
668 | ||
d174bd64 DV |
669 | ret = shmem_pread_fast(page, shmem_page_offset, page_length, |
670 | user_data, page_do_bit17_swizzling, | |
671 | needs_clflush); | |
672 | if (ret == 0) | |
673 | goto next_page; | |
dbf7bff0 | 674 | |
dbf7bff0 DV |
675 | mutex_unlock(&dev->struct_mutex); |
676 | ||
d330a953 | 677 | if (likely(!i915.prefault_disable) && !prefaulted) { |
f56f821f | 678 | ret = fault_in_multipages_writeable(user_data, remain); |
96d79b52 DV |
679 | /* Userspace is tricking us, but we've already clobbered |
680 | * its pages with the prefault and promised to write the | |
681 | * data up to the first fault. Hence ignore any errors | |
682 | * and just continue. */ | |
683 | (void)ret; | |
684 | prefaulted = 1; | |
685 | } | |
eb01459f | 686 | |
d174bd64 DV |
687 | ret = shmem_pread_slow(page, shmem_page_offset, page_length, |
688 | user_data, page_do_bit17_swizzling, | |
689 | needs_clflush); | |
eb01459f | 690 | |
dbf7bff0 | 691 | mutex_lock(&dev->struct_mutex); |
f60d7f0c | 692 | |
f60d7f0c | 693 | if (ret) |
8461d226 | 694 | goto out; |
8461d226 | 695 | |
17793c9a | 696 | next_page: |
eb01459f | 697 | remain -= page_length; |
8461d226 | 698 | user_data += page_length; |
eb01459f EA |
699 | offset += page_length; |
700 | } | |
701 | ||
4f27b75d | 702 | out: |
f60d7f0c CW |
703 | i915_gem_object_unpin_pages(obj); |
704 | ||
eb01459f EA |
705 | return ret; |
706 | } | |
707 | ||
673a394b EA |
708 | /** |
709 | * Reads data from the object referenced by handle. | |
710 | * | |
711 | * On error, the contents of *data are undefined. | |
712 | */ | |
713 | int | |
714 | i915_gem_pread_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 715 | struct drm_file *file) |
673a394b EA |
716 | { |
717 | struct drm_i915_gem_pread *args = data; | |
05394f39 | 718 | struct drm_i915_gem_object *obj; |
35b62a89 | 719 | int ret = 0; |
673a394b | 720 | |
51311d0a CW |
721 | if (args->size == 0) |
722 | return 0; | |
723 | ||
724 | if (!access_ok(VERIFY_WRITE, | |
2bb4629a | 725 | to_user_ptr(args->data_ptr), |
51311d0a CW |
726 | args->size)) |
727 | return -EFAULT; | |
728 | ||
4f27b75d | 729 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 730 | if (ret) |
4f27b75d | 731 | return ret; |
673a394b | 732 | |
05394f39 | 733 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 734 | if (&obj->base == NULL) { |
1d7cfea1 CW |
735 | ret = -ENOENT; |
736 | goto unlock; | |
4f27b75d | 737 | } |
673a394b | 738 | |
7dcd2499 | 739 | /* Bounds check source. */ |
05394f39 CW |
740 | if (args->offset > obj->base.size || |
741 | args->size > obj->base.size - args->offset) { | |
ce9d419d | 742 | ret = -EINVAL; |
35b62a89 | 743 | goto out; |
ce9d419d CW |
744 | } |
745 | ||
1286ff73 DV |
746 | /* prime objects have no backing filp to GEM pread/pwrite |
747 | * pages from. | |
748 | */ | |
749 | if (!obj->base.filp) { | |
750 | ret = -EINVAL; | |
751 | goto out; | |
752 | } | |
753 | ||
db53a302 CW |
754 | trace_i915_gem_object_pread(obj, args->offset, args->size); |
755 | ||
dbf7bff0 | 756 | ret = i915_gem_shmem_pread(dev, obj, args, file); |
673a394b | 757 | |
35b62a89 | 758 | out: |
05394f39 | 759 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 760 | unlock: |
4f27b75d | 761 | mutex_unlock(&dev->struct_mutex); |
eb01459f | 762 | return ret; |
673a394b EA |
763 | } |
764 | ||
0839ccb8 KP |
765 | /* This is the fast write path which cannot handle |
766 | * page faults in the source data | |
9b7530cc | 767 | */ |
0839ccb8 KP |
768 | |
769 | static inline int | |
770 | fast_user_write(struct io_mapping *mapping, | |
771 | loff_t page_base, int page_offset, | |
772 | char __user *user_data, | |
773 | int length) | |
9b7530cc | 774 | { |
4f0c7cfb BW |
775 | void __iomem *vaddr_atomic; |
776 | void *vaddr; | |
0839ccb8 | 777 | unsigned long unwritten; |
9b7530cc | 778 | |
3e4d3af5 | 779 | vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base); |
4f0c7cfb BW |
780 | /* We can use the cpu mem copy function because this is X86. */ |
781 | vaddr = (void __force*)vaddr_atomic + page_offset; | |
782 | unwritten = __copy_from_user_inatomic_nocache(vaddr, | |
0839ccb8 | 783 | user_data, length); |
3e4d3af5 | 784 | io_mapping_unmap_atomic(vaddr_atomic); |
fbd5a26d | 785 | return unwritten; |
0839ccb8 KP |
786 | } |
787 | ||
3de09aa3 EA |
788 | /** |
789 | * This is the fast pwrite path, where we copy the data directly from the | |
790 | * user into the GTT, uncached. | |
791 | */ | |
673a394b | 792 | static int |
05394f39 CW |
793 | i915_gem_gtt_pwrite_fast(struct drm_device *dev, |
794 | struct drm_i915_gem_object *obj, | |
3de09aa3 | 795 | struct drm_i915_gem_pwrite *args, |
05394f39 | 796 | struct drm_file *file) |
673a394b | 797 | { |
3e31c6c0 | 798 | struct drm_i915_private *dev_priv = dev->dev_private; |
673a394b | 799 | ssize_t remain; |
0839ccb8 | 800 | loff_t offset, page_base; |
673a394b | 801 | char __user *user_data; |
935aaa69 DV |
802 | int page_offset, page_length, ret; |
803 | ||
1ec9e26d | 804 | ret = i915_gem_obj_ggtt_pin(obj, 0, PIN_MAPPABLE | PIN_NONBLOCK); |
935aaa69 DV |
805 | if (ret) |
806 | goto out; | |
807 | ||
808 | ret = i915_gem_object_set_to_gtt_domain(obj, true); | |
809 | if (ret) | |
810 | goto out_unpin; | |
811 | ||
812 | ret = i915_gem_object_put_fence(obj); | |
813 | if (ret) | |
814 | goto out_unpin; | |
673a394b | 815 | |
2bb4629a | 816 | user_data = to_user_ptr(args->data_ptr); |
673a394b | 817 | remain = args->size; |
673a394b | 818 | |
f343c5f6 | 819 | offset = i915_gem_obj_ggtt_offset(obj) + args->offset; |
673a394b EA |
820 | |
821 | while (remain > 0) { | |
822 | /* Operation in this page | |
823 | * | |
0839ccb8 KP |
824 | * page_base = page offset within aperture |
825 | * page_offset = offset within page | |
826 | * page_length = bytes to copy for this page | |
673a394b | 827 | */ |
c8cbbb8b CW |
828 | page_base = offset & PAGE_MASK; |
829 | page_offset = offset_in_page(offset); | |
0839ccb8 KP |
830 | page_length = remain; |
831 | if ((page_offset + remain) > PAGE_SIZE) | |
832 | page_length = PAGE_SIZE - page_offset; | |
833 | ||
0839ccb8 | 834 | /* If we get a fault while copying data, then (presumably) our |
3de09aa3 EA |
835 | * source page isn't available. Return the error and we'll |
836 | * retry in the slow path. | |
0839ccb8 | 837 | */ |
5d4545ae | 838 | if (fast_user_write(dev_priv->gtt.mappable, page_base, |
935aaa69 DV |
839 | page_offset, user_data, page_length)) { |
840 | ret = -EFAULT; | |
841 | goto out_unpin; | |
842 | } | |
673a394b | 843 | |
0839ccb8 KP |
844 | remain -= page_length; |
845 | user_data += page_length; | |
846 | offset += page_length; | |
673a394b | 847 | } |
673a394b | 848 | |
935aaa69 | 849 | out_unpin: |
d7f46fc4 | 850 | i915_gem_object_ggtt_unpin(obj); |
935aaa69 | 851 | out: |
3de09aa3 | 852 | return ret; |
673a394b EA |
853 | } |
854 | ||
d174bd64 DV |
855 | /* Per-page copy function for the shmem pwrite fastpath. |
856 | * Flushes invalid cachelines before writing to the target if | |
857 | * needs_clflush_before is set and flushes out any written cachelines after | |
858 | * writing if needs_clflush is set. */ | |
3043c60c | 859 | static int |
d174bd64 DV |
860 | shmem_pwrite_fast(struct page *page, int shmem_page_offset, int page_length, |
861 | char __user *user_data, | |
862 | bool page_do_bit17_swizzling, | |
863 | bool needs_clflush_before, | |
864 | bool needs_clflush_after) | |
673a394b | 865 | { |
d174bd64 | 866 | char *vaddr; |
673a394b | 867 | int ret; |
3de09aa3 | 868 | |
e7e58eb5 | 869 | if (unlikely(page_do_bit17_swizzling)) |
d174bd64 | 870 | return -EINVAL; |
3de09aa3 | 871 | |
d174bd64 DV |
872 | vaddr = kmap_atomic(page); |
873 | if (needs_clflush_before) | |
874 | drm_clflush_virt_range(vaddr + shmem_page_offset, | |
875 | page_length); | |
c2831a94 CW |
876 | ret = __copy_from_user_inatomic(vaddr + shmem_page_offset, |
877 | user_data, page_length); | |
d174bd64 DV |
878 | if (needs_clflush_after) |
879 | drm_clflush_virt_range(vaddr + shmem_page_offset, | |
880 | page_length); | |
881 | kunmap_atomic(vaddr); | |
3de09aa3 | 882 | |
755d2218 | 883 | return ret ? -EFAULT : 0; |
3de09aa3 EA |
884 | } |
885 | ||
d174bd64 DV |
886 | /* Only difference to the fast-path function is that this can handle bit17 |
887 | * and uses non-atomic copy and kmap functions. */ | |
3043c60c | 888 | static int |
d174bd64 DV |
889 | shmem_pwrite_slow(struct page *page, int shmem_page_offset, int page_length, |
890 | char __user *user_data, | |
891 | bool page_do_bit17_swizzling, | |
892 | bool needs_clflush_before, | |
893 | bool needs_clflush_after) | |
673a394b | 894 | { |
d174bd64 DV |
895 | char *vaddr; |
896 | int ret; | |
e5281ccd | 897 | |
d174bd64 | 898 | vaddr = kmap(page); |
e7e58eb5 | 899 | if (unlikely(needs_clflush_before || page_do_bit17_swizzling)) |
23c18c71 DV |
900 | shmem_clflush_swizzled_range(vaddr + shmem_page_offset, |
901 | page_length, | |
902 | page_do_bit17_swizzling); | |
d174bd64 DV |
903 | if (page_do_bit17_swizzling) |
904 | ret = __copy_from_user_swizzled(vaddr, shmem_page_offset, | |
e5281ccd CW |
905 | user_data, |
906 | page_length); | |
d174bd64 DV |
907 | else |
908 | ret = __copy_from_user(vaddr + shmem_page_offset, | |
909 | user_data, | |
910 | page_length); | |
911 | if (needs_clflush_after) | |
23c18c71 DV |
912 | shmem_clflush_swizzled_range(vaddr + shmem_page_offset, |
913 | page_length, | |
914 | page_do_bit17_swizzling); | |
d174bd64 | 915 | kunmap(page); |
40123c1f | 916 | |
755d2218 | 917 | return ret ? -EFAULT : 0; |
40123c1f EA |
918 | } |
919 | ||
40123c1f | 920 | static int |
e244a443 DV |
921 | i915_gem_shmem_pwrite(struct drm_device *dev, |
922 | struct drm_i915_gem_object *obj, | |
923 | struct drm_i915_gem_pwrite *args, | |
924 | struct drm_file *file) | |
40123c1f | 925 | { |
40123c1f | 926 | ssize_t remain; |
8c59967c DV |
927 | loff_t offset; |
928 | char __user *user_data; | |
eb2c0c81 | 929 | int shmem_page_offset, page_length, ret = 0; |
8c59967c | 930 | int obj_do_bit17_swizzling, page_do_bit17_swizzling; |
e244a443 | 931 | int hit_slowpath = 0; |
58642885 DV |
932 | int needs_clflush_after = 0; |
933 | int needs_clflush_before = 0; | |
67d5a50c | 934 | struct sg_page_iter sg_iter; |
40123c1f | 935 | |
2bb4629a | 936 | user_data = to_user_ptr(args->data_ptr); |
40123c1f EA |
937 | remain = args->size; |
938 | ||
8c59967c | 939 | obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj); |
40123c1f | 940 | |
58642885 DV |
941 | if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) { |
942 | /* If we're not in the cpu write domain, set ourself into the gtt | |
943 | * write domain and manually flush cachelines (if required). This | |
944 | * optimizes for the case when the gpu will use the data | |
945 | * right away and we therefore have to clflush anyway. */ | |
2c22569b | 946 | needs_clflush_after = cpu_write_needs_clflush(obj); |
23f54483 BW |
947 | ret = i915_gem_object_wait_rendering(obj, false); |
948 | if (ret) | |
949 | return ret; | |
c8725f3d CW |
950 | |
951 | i915_gem_object_retire(obj); | |
58642885 | 952 | } |
c76ce038 CW |
953 | /* Same trick applies to invalidate partially written cachelines read |
954 | * before writing. */ | |
955 | if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) | |
956 | needs_clflush_before = | |
957 | !cpu_cache_is_coherent(dev, obj->cache_level); | |
58642885 | 958 | |
755d2218 CW |
959 | ret = i915_gem_object_get_pages(obj); |
960 | if (ret) | |
961 | return ret; | |
962 | ||
963 | i915_gem_object_pin_pages(obj); | |
964 | ||
673a394b | 965 | offset = args->offset; |
05394f39 | 966 | obj->dirty = 1; |
673a394b | 967 | |
67d5a50c ID |
968 | for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, |
969 | offset >> PAGE_SHIFT) { | |
2db76d7c | 970 | struct page *page = sg_page_iter_page(&sg_iter); |
58642885 | 971 | int partial_cacheline_write; |
e5281ccd | 972 | |
9da3da66 CW |
973 | if (remain <= 0) |
974 | break; | |
975 | ||
40123c1f EA |
976 | /* Operation in this page |
977 | * | |
40123c1f | 978 | * shmem_page_offset = offset within page in shmem file |
40123c1f EA |
979 | * page_length = bytes to copy for this page |
980 | */ | |
c8cbbb8b | 981 | shmem_page_offset = offset_in_page(offset); |
40123c1f EA |
982 | |
983 | page_length = remain; | |
984 | if ((shmem_page_offset + page_length) > PAGE_SIZE) | |
985 | page_length = PAGE_SIZE - shmem_page_offset; | |
40123c1f | 986 | |
58642885 DV |
987 | /* If we don't overwrite a cacheline completely we need to be |
988 | * careful to have up-to-date data by first clflushing. Don't | |
989 | * overcomplicate things and flush the entire patch. */ | |
990 | partial_cacheline_write = needs_clflush_before && | |
991 | ((shmem_page_offset | page_length) | |
992 | & (boot_cpu_data.x86_clflush_size - 1)); | |
993 | ||
8c59967c DV |
994 | page_do_bit17_swizzling = obj_do_bit17_swizzling && |
995 | (page_to_phys(page) & (1 << 17)) != 0; | |
996 | ||
d174bd64 DV |
997 | ret = shmem_pwrite_fast(page, shmem_page_offset, page_length, |
998 | user_data, page_do_bit17_swizzling, | |
999 | partial_cacheline_write, | |
1000 | needs_clflush_after); | |
1001 | if (ret == 0) | |
1002 | goto next_page; | |
e244a443 DV |
1003 | |
1004 | hit_slowpath = 1; | |
e244a443 | 1005 | mutex_unlock(&dev->struct_mutex); |
d174bd64 DV |
1006 | ret = shmem_pwrite_slow(page, shmem_page_offset, page_length, |
1007 | user_data, page_do_bit17_swizzling, | |
1008 | partial_cacheline_write, | |
1009 | needs_clflush_after); | |
40123c1f | 1010 | |
e244a443 | 1011 | mutex_lock(&dev->struct_mutex); |
755d2218 | 1012 | |
755d2218 | 1013 | if (ret) |
8c59967c | 1014 | goto out; |
8c59967c | 1015 | |
17793c9a | 1016 | next_page: |
40123c1f | 1017 | remain -= page_length; |
8c59967c | 1018 | user_data += page_length; |
40123c1f | 1019 | offset += page_length; |
673a394b EA |
1020 | } |
1021 | ||
fbd5a26d | 1022 | out: |
755d2218 CW |
1023 | i915_gem_object_unpin_pages(obj); |
1024 | ||
e244a443 | 1025 | if (hit_slowpath) { |
8dcf015e DV |
1026 | /* |
1027 | * Fixup: Flush cpu caches in case we didn't flush the dirty | |
1028 | * cachelines in-line while writing and the object moved | |
1029 | * out of the cpu write domain while we've dropped the lock. | |
1030 | */ | |
1031 | if (!needs_clflush_after && | |
1032 | obj->base.write_domain != I915_GEM_DOMAIN_CPU) { | |
000433b6 CW |
1033 | if (i915_gem_clflush_object(obj, obj->pin_display)) |
1034 | i915_gem_chipset_flush(dev); | |
e244a443 | 1035 | } |
8c59967c | 1036 | } |
673a394b | 1037 | |
58642885 | 1038 | if (needs_clflush_after) |
e76e9aeb | 1039 | i915_gem_chipset_flush(dev); |
58642885 | 1040 | |
40123c1f | 1041 | return ret; |
673a394b EA |
1042 | } |
1043 | ||
1044 | /** | |
1045 | * Writes data to the object referenced by handle. | |
1046 | * | |
1047 | * On error, the contents of the buffer that were to be modified are undefined. | |
1048 | */ | |
1049 | int | |
1050 | i915_gem_pwrite_ioctl(struct drm_device *dev, void *data, | |
fbd5a26d | 1051 | struct drm_file *file) |
673a394b EA |
1052 | { |
1053 | struct drm_i915_gem_pwrite *args = data; | |
05394f39 | 1054 | struct drm_i915_gem_object *obj; |
51311d0a CW |
1055 | int ret; |
1056 | ||
1057 | if (args->size == 0) | |
1058 | return 0; | |
1059 | ||
1060 | if (!access_ok(VERIFY_READ, | |
2bb4629a | 1061 | to_user_ptr(args->data_ptr), |
51311d0a CW |
1062 | args->size)) |
1063 | return -EFAULT; | |
1064 | ||
d330a953 | 1065 | if (likely(!i915.prefault_disable)) { |
0b74b508 XZ |
1066 | ret = fault_in_multipages_readable(to_user_ptr(args->data_ptr), |
1067 | args->size); | |
1068 | if (ret) | |
1069 | return -EFAULT; | |
1070 | } | |
673a394b | 1071 | |
fbd5a26d | 1072 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 1073 | if (ret) |
fbd5a26d | 1074 | return ret; |
1d7cfea1 | 1075 | |
05394f39 | 1076 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 1077 | if (&obj->base == NULL) { |
1d7cfea1 CW |
1078 | ret = -ENOENT; |
1079 | goto unlock; | |
fbd5a26d | 1080 | } |
673a394b | 1081 | |
7dcd2499 | 1082 | /* Bounds check destination. */ |
05394f39 CW |
1083 | if (args->offset > obj->base.size || |
1084 | args->size > obj->base.size - args->offset) { | |
ce9d419d | 1085 | ret = -EINVAL; |
35b62a89 | 1086 | goto out; |
ce9d419d CW |
1087 | } |
1088 | ||
1286ff73 DV |
1089 | /* prime objects have no backing filp to GEM pread/pwrite |
1090 | * pages from. | |
1091 | */ | |
1092 | if (!obj->base.filp) { | |
1093 | ret = -EINVAL; | |
1094 | goto out; | |
1095 | } | |
1096 | ||
db53a302 CW |
1097 | trace_i915_gem_object_pwrite(obj, args->offset, args->size); |
1098 | ||
935aaa69 | 1099 | ret = -EFAULT; |
673a394b EA |
1100 | /* We can only do the GTT pwrite on untiled buffers, as otherwise |
1101 | * it would end up going through the fenced access, and we'll get | |
1102 | * different detiling behavior between reading and writing. | |
1103 | * pread/pwrite currently are reading and writing from the CPU | |
1104 | * perspective, requiring manual detiling by the client. | |
1105 | */ | |
2c22569b CW |
1106 | if (obj->tiling_mode == I915_TILING_NONE && |
1107 | obj->base.write_domain != I915_GEM_DOMAIN_CPU && | |
1108 | cpu_write_needs_clflush(obj)) { | |
fbd5a26d | 1109 | ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file); |
935aaa69 DV |
1110 | /* Note that the gtt paths might fail with non-page-backed user |
1111 | * pointers (e.g. gtt mappings when moving data between | |
1112 | * textures). Fallback to the shmem path in that case. */ | |
fbd5a26d | 1113 | } |
673a394b | 1114 | |
6a2c4232 CW |
1115 | if (ret == -EFAULT || ret == -ENOSPC) { |
1116 | if (obj->phys_handle) | |
1117 | ret = i915_gem_phys_pwrite(obj, args, file); | |
1118 | else | |
1119 | ret = i915_gem_shmem_pwrite(dev, obj, args, file); | |
1120 | } | |
5c0480f2 | 1121 | |
35b62a89 | 1122 | out: |
05394f39 | 1123 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 1124 | unlock: |
fbd5a26d | 1125 | mutex_unlock(&dev->struct_mutex); |
673a394b EA |
1126 | return ret; |
1127 | } | |
1128 | ||
b361237b | 1129 | int |
33196ded | 1130 | i915_gem_check_wedge(struct i915_gpu_error *error, |
b361237b CW |
1131 | bool interruptible) |
1132 | { | |
1f83fee0 | 1133 | if (i915_reset_in_progress(error)) { |
b361237b CW |
1134 | /* Non-interruptible callers can't handle -EAGAIN, hence return |
1135 | * -EIO unconditionally for these. */ | |
1136 | if (!interruptible) | |
1137 | return -EIO; | |
1138 | ||
1f83fee0 DV |
1139 | /* Recovery complete, but the reset failed ... */ |
1140 | if (i915_terminally_wedged(error)) | |
b361237b CW |
1141 | return -EIO; |
1142 | ||
6689c167 MA |
1143 | /* |
1144 | * Check if GPU Reset is in progress - we need intel_ring_begin | |
1145 | * to work properly to reinit the hw state while the gpu is | |
1146 | * still marked as reset-in-progress. Handle this with a flag. | |
1147 | */ | |
1148 | if (!error->reload_in_reset) | |
1149 | return -EAGAIN; | |
b361237b CW |
1150 | } |
1151 | ||
1152 | return 0; | |
1153 | } | |
1154 | ||
1155 | /* | |
b6660d59 | 1156 | * Compare arbitrary request against outstanding lazy request. Emit on match. |
b361237b | 1157 | */ |
84c33a64 | 1158 | int |
b6660d59 | 1159 | i915_gem_check_olr(struct drm_i915_gem_request *req) |
b361237b CW |
1160 | { |
1161 | int ret; | |
1162 | ||
b6660d59 | 1163 | WARN_ON(!mutex_is_locked(&req->ring->dev->struct_mutex)); |
b361237b CW |
1164 | |
1165 | ret = 0; | |
b6660d59 | 1166 | if (req == req->ring->outstanding_lazy_request) |
9400ae5c | 1167 | ret = i915_add_request(req->ring); |
b361237b CW |
1168 | |
1169 | return ret; | |
1170 | } | |
1171 | ||
094f9a54 CW |
1172 | static void fake_irq(unsigned long data) |
1173 | { | |
1174 | wake_up_process((struct task_struct *)data); | |
1175 | } | |
1176 | ||
1177 | static bool missed_irq(struct drm_i915_private *dev_priv, | |
a4872ba6 | 1178 | struct intel_engine_cs *ring) |
094f9a54 CW |
1179 | { |
1180 | return test_bit(ring->id, &dev_priv->gpu_error.missed_irq_rings); | |
1181 | } | |
1182 | ||
b29c19b6 CW |
1183 | static bool can_wait_boost(struct drm_i915_file_private *file_priv) |
1184 | { | |
1185 | if (file_priv == NULL) | |
1186 | return true; | |
1187 | ||
1188 | return !atomic_xchg(&file_priv->rps_wait_boost, true); | |
1189 | } | |
1190 | ||
b361237b | 1191 | /** |
9c654818 JH |
1192 | * __i915_wait_request - wait until execution of request has finished |
1193 | * @req: duh! | |
1194 | * @reset_counter: reset sequence associated with the given request | |
b361237b CW |
1195 | * @interruptible: do an interruptible wait (normally yes) |
1196 | * @timeout: in - how long to wait (NULL forever); out - how much time remaining | |
1197 | * | |
f69061be DV |
1198 | * Note: It is of utmost importance that the passed in seqno and reset_counter |
1199 | * values have been read by the caller in an smp safe manner. Where read-side | |
1200 | * locks are involved, it is sufficient to read the reset_counter before | |
1201 | * unlocking the lock that protects the seqno. For lockless tricks, the | |
1202 | * reset_counter _must_ be read before, and an appropriate smp_rmb must be | |
1203 | * inserted. | |
1204 | * | |
9c654818 | 1205 | * Returns 0 if the request was found within the alloted time. Else returns the |
b361237b CW |
1206 | * errno with remaining time filled in timeout argument. |
1207 | */ | |
9c654818 | 1208 | int __i915_wait_request(struct drm_i915_gem_request *req, |
f69061be | 1209 | unsigned reset_counter, |
b29c19b6 | 1210 | bool interruptible, |
5ed0bdf2 | 1211 | s64 *timeout, |
b29c19b6 | 1212 | struct drm_i915_file_private *file_priv) |
b361237b | 1213 | { |
9c654818 | 1214 | struct intel_engine_cs *ring = i915_gem_request_get_ring(req); |
3d13ef2e | 1215 | struct drm_device *dev = ring->dev; |
3e31c6c0 | 1216 | struct drm_i915_private *dev_priv = dev->dev_private; |
168c3f21 MK |
1217 | const bool irq_test_in_progress = |
1218 | ACCESS_ONCE(dev_priv->gpu_error.test_irq_rings) & intel_ring_flag(ring); | |
094f9a54 | 1219 | DEFINE_WAIT(wait); |
47e9766d | 1220 | unsigned long timeout_expire; |
5ed0bdf2 | 1221 | s64 before, now; |
b361237b CW |
1222 | int ret; |
1223 | ||
9df7575f | 1224 | WARN(!intel_irqs_enabled(dev_priv), "IRQs disabled"); |
c67a470b | 1225 | |
1b5a433a | 1226 | if (i915_gem_request_completed(req, true)) |
b361237b CW |
1227 | return 0; |
1228 | ||
5ed0bdf2 | 1229 | timeout_expire = timeout ? jiffies + nsecs_to_jiffies((u64)*timeout) : 0; |
b361237b | 1230 | |
ec5cc0f9 | 1231 | if (INTEL_INFO(dev)->gen >= 6 && ring->id == RCS && can_wait_boost(file_priv)) { |
b29c19b6 CW |
1232 | gen6_rps_boost(dev_priv); |
1233 | if (file_priv) | |
1234 | mod_delayed_work(dev_priv->wq, | |
1235 | &file_priv->mm.idle_work, | |
1236 | msecs_to_jiffies(100)); | |
1237 | } | |
1238 | ||
168c3f21 | 1239 | if (!irq_test_in_progress && WARN_ON(!ring->irq_get(ring))) |
b361237b CW |
1240 | return -ENODEV; |
1241 | ||
094f9a54 | 1242 | /* Record current time in case interrupted by signal, or wedged */ |
74328ee5 | 1243 | trace_i915_gem_request_wait_begin(req); |
5ed0bdf2 | 1244 | before = ktime_get_raw_ns(); |
094f9a54 CW |
1245 | for (;;) { |
1246 | struct timer_list timer; | |
b361237b | 1247 | |
094f9a54 CW |
1248 | prepare_to_wait(&ring->irq_queue, &wait, |
1249 | interruptible ? TASK_INTERRUPTIBLE : TASK_UNINTERRUPTIBLE); | |
b361237b | 1250 | |
f69061be DV |
1251 | /* We need to check whether any gpu reset happened in between |
1252 | * the caller grabbing the seqno and now ... */ | |
094f9a54 CW |
1253 | if (reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter)) { |
1254 | /* ... but upgrade the -EAGAIN to an -EIO if the gpu | |
1255 | * is truely gone. */ | |
1256 | ret = i915_gem_check_wedge(&dev_priv->gpu_error, interruptible); | |
1257 | if (ret == 0) | |
1258 | ret = -EAGAIN; | |
1259 | break; | |
1260 | } | |
f69061be | 1261 | |
1b5a433a | 1262 | if (i915_gem_request_completed(req, false)) { |
094f9a54 CW |
1263 | ret = 0; |
1264 | break; | |
1265 | } | |
b361237b | 1266 | |
094f9a54 CW |
1267 | if (interruptible && signal_pending(current)) { |
1268 | ret = -ERESTARTSYS; | |
1269 | break; | |
1270 | } | |
1271 | ||
47e9766d | 1272 | if (timeout && time_after_eq(jiffies, timeout_expire)) { |
094f9a54 CW |
1273 | ret = -ETIME; |
1274 | break; | |
1275 | } | |
1276 | ||
1277 | timer.function = NULL; | |
1278 | if (timeout || missed_irq(dev_priv, ring)) { | |
47e9766d MK |
1279 | unsigned long expire; |
1280 | ||
094f9a54 | 1281 | setup_timer_on_stack(&timer, fake_irq, (unsigned long)current); |
47e9766d | 1282 | expire = missed_irq(dev_priv, ring) ? jiffies + 1 : timeout_expire; |
094f9a54 CW |
1283 | mod_timer(&timer, expire); |
1284 | } | |
1285 | ||
5035c275 | 1286 | io_schedule(); |
094f9a54 | 1287 | |
094f9a54 CW |
1288 | if (timer.function) { |
1289 | del_singleshot_timer_sync(&timer); | |
1290 | destroy_timer_on_stack(&timer); | |
1291 | } | |
1292 | } | |
5ed0bdf2 | 1293 | now = ktime_get_raw_ns(); |
74328ee5 | 1294 | trace_i915_gem_request_wait_end(req); |
b361237b | 1295 | |
168c3f21 MK |
1296 | if (!irq_test_in_progress) |
1297 | ring->irq_put(ring); | |
094f9a54 CW |
1298 | |
1299 | finish_wait(&ring->irq_queue, &wait); | |
b361237b CW |
1300 | |
1301 | if (timeout) { | |
5ed0bdf2 TG |
1302 | s64 tres = *timeout - (now - before); |
1303 | ||
1304 | *timeout = tres < 0 ? 0 : tres; | |
b361237b CW |
1305 | } |
1306 | ||
094f9a54 | 1307 | return ret; |
b361237b CW |
1308 | } |
1309 | ||
1310 | /** | |
a4b3a571 | 1311 | * Waits for a request to be signaled, and cleans up the |
b361237b CW |
1312 | * request and object lists appropriately for that event. |
1313 | */ | |
1314 | int | |
a4b3a571 | 1315 | i915_wait_request(struct drm_i915_gem_request *req) |
b361237b | 1316 | { |
a4b3a571 DV |
1317 | struct drm_device *dev; |
1318 | struct drm_i915_private *dev_priv; | |
1319 | bool interruptible; | |
16e9a21f | 1320 | unsigned reset_counter; |
b361237b CW |
1321 | int ret; |
1322 | ||
a4b3a571 DV |
1323 | BUG_ON(req == NULL); |
1324 | ||
1325 | dev = req->ring->dev; | |
1326 | dev_priv = dev->dev_private; | |
1327 | interruptible = dev_priv->mm.interruptible; | |
1328 | ||
b361237b | 1329 | BUG_ON(!mutex_is_locked(&dev->struct_mutex)); |
b361237b | 1330 | |
33196ded | 1331 | ret = i915_gem_check_wedge(&dev_priv->gpu_error, interruptible); |
b361237b CW |
1332 | if (ret) |
1333 | return ret; | |
1334 | ||
a4b3a571 | 1335 | ret = i915_gem_check_olr(req); |
b361237b CW |
1336 | if (ret) |
1337 | return ret; | |
1338 | ||
16e9a21f | 1339 | reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter); |
a4b3a571 | 1340 | i915_gem_request_reference(req); |
9c654818 JH |
1341 | ret = __i915_wait_request(req, reset_counter, |
1342 | interruptible, NULL, NULL); | |
a4b3a571 DV |
1343 | i915_gem_request_unreference(req); |
1344 | return ret; | |
b361237b CW |
1345 | } |
1346 | ||
d26e3af8 | 1347 | static int |
8e639549 | 1348 | i915_gem_object_wait_rendering__tail(struct drm_i915_gem_object *obj) |
d26e3af8 | 1349 | { |
c8725f3d CW |
1350 | if (!obj->active) |
1351 | return 0; | |
d26e3af8 CW |
1352 | |
1353 | /* Manually manage the write flush as we may have not yet | |
1354 | * retired the buffer. | |
1355 | * | |
97b2a6a1 JH |
1356 | * Note that the last_write_req is always the earlier of |
1357 | * the two (read/write) requests, so if we haved successfully waited, | |
d26e3af8 CW |
1358 | * we know we have passed the last write. |
1359 | */ | |
97b2a6a1 | 1360 | i915_gem_request_assign(&obj->last_write_req, NULL); |
d26e3af8 CW |
1361 | |
1362 | return 0; | |
1363 | } | |
1364 | ||
b361237b CW |
1365 | /** |
1366 | * Ensures that all rendering to the object has completed and the object is | |
1367 | * safe to unbind from the GTT or access from the CPU. | |
1368 | */ | |
1369 | static __must_check int | |
1370 | i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj, | |
1371 | bool readonly) | |
1372 | { | |
97b2a6a1 | 1373 | struct drm_i915_gem_request *req; |
b361237b CW |
1374 | int ret; |
1375 | ||
97b2a6a1 JH |
1376 | req = readonly ? obj->last_write_req : obj->last_read_req; |
1377 | if (!req) | |
b361237b CW |
1378 | return 0; |
1379 | ||
a4b3a571 | 1380 | ret = i915_wait_request(req); |
b361237b CW |
1381 | if (ret) |
1382 | return ret; | |
1383 | ||
8e639549 | 1384 | return i915_gem_object_wait_rendering__tail(obj); |
b361237b CW |
1385 | } |
1386 | ||
3236f57a CW |
1387 | /* A nonblocking variant of the above wait. This is a highly dangerous routine |
1388 | * as the object state may change during this call. | |
1389 | */ | |
1390 | static __must_check int | |
1391 | i915_gem_object_wait_rendering__nonblocking(struct drm_i915_gem_object *obj, | |
6e4930f6 | 1392 | struct drm_i915_file_private *file_priv, |
3236f57a CW |
1393 | bool readonly) |
1394 | { | |
97b2a6a1 | 1395 | struct drm_i915_gem_request *req; |
3236f57a CW |
1396 | struct drm_device *dev = obj->base.dev; |
1397 | struct drm_i915_private *dev_priv = dev->dev_private; | |
f69061be | 1398 | unsigned reset_counter; |
3236f57a CW |
1399 | int ret; |
1400 | ||
1401 | BUG_ON(!mutex_is_locked(&dev->struct_mutex)); | |
1402 | BUG_ON(!dev_priv->mm.interruptible); | |
1403 | ||
97b2a6a1 JH |
1404 | req = readonly ? obj->last_write_req : obj->last_read_req; |
1405 | if (!req) | |
3236f57a CW |
1406 | return 0; |
1407 | ||
33196ded | 1408 | ret = i915_gem_check_wedge(&dev_priv->gpu_error, true); |
3236f57a CW |
1409 | if (ret) |
1410 | return ret; | |
1411 | ||
b6660d59 | 1412 | ret = i915_gem_check_olr(req); |
3236f57a CW |
1413 | if (ret) |
1414 | return ret; | |
1415 | ||
f69061be | 1416 | reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter); |
ff865885 | 1417 | i915_gem_request_reference(req); |
3236f57a | 1418 | mutex_unlock(&dev->struct_mutex); |
9c654818 | 1419 | ret = __i915_wait_request(req, reset_counter, true, NULL, file_priv); |
3236f57a | 1420 | mutex_lock(&dev->struct_mutex); |
ff865885 | 1421 | i915_gem_request_unreference(req); |
d26e3af8 CW |
1422 | if (ret) |
1423 | return ret; | |
3236f57a | 1424 | |
8e639549 | 1425 | return i915_gem_object_wait_rendering__tail(obj); |
3236f57a CW |
1426 | } |
1427 | ||
673a394b | 1428 | /** |
2ef7eeaa EA |
1429 | * Called when user space prepares to use an object with the CPU, either |
1430 | * through the mmap ioctl's mapping or a GTT mapping. | |
673a394b EA |
1431 | */ |
1432 | int | |
1433 | i915_gem_set_domain_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 1434 | struct drm_file *file) |
673a394b EA |
1435 | { |
1436 | struct drm_i915_gem_set_domain *args = data; | |
05394f39 | 1437 | struct drm_i915_gem_object *obj; |
2ef7eeaa EA |
1438 | uint32_t read_domains = args->read_domains; |
1439 | uint32_t write_domain = args->write_domain; | |
673a394b EA |
1440 | int ret; |
1441 | ||
2ef7eeaa | 1442 | /* Only handle setting domains to types used by the CPU. */ |
21d509e3 | 1443 | if (write_domain & I915_GEM_GPU_DOMAINS) |
2ef7eeaa EA |
1444 | return -EINVAL; |
1445 | ||
21d509e3 | 1446 | if (read_domains & I915_GEM_GPU_DOMAINS) |
2ef7eeaa EA |
1447 | return -EINVAL; |
1448 | ||
1449 | /* Having something in the write domain implies it's in the read | |
1450 | * domain, and only that read domain. Enforce that in the request. | |
1451 | */ | |
1452 | if (write_domain != 0 && read_domains != write_domain) | |
1453 | return -EINVAL; | |
1454 | ||
76c1dec1 | 1455 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 1456 | if (ret) |
76c1dec1 | 1457 | return ret; |
1d7cfea1 | 1458 | |
05394f39 | 1459 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 1460 | if (&obj->base == NULL) { |
1d7cfea1 CW |
1461 | ret = -ENOENT; |
1462 | goto unlock; | |
76c1dec1 | 1463 | } |
673a394b | 1464 | |
3236f57a CW |
1465 | /* Try to flush the object off the GPU without holding the lock. |
1466 | * We will repeat the flush holding the lock in the normal manner | |
1467 | * to catch cases where we are gazumped. | |
1468 | */ | |
6e4930f6 CW |
1469 | ret = i915_gem_object_wait_rendering__nonblocking(obj, |
1470 | file->driver_priv, | |
1471 | !write_domain); | |
3236f57a CW |
1472 | if (ret) |
1473 | goto unref; | |
1474 | ||
2ef7eeaa EA |
1475 | if (read_domains & I915_GEM_DOMAIN_GTT) { |
1476 | ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0); | |
02354392 EA |
1477 | |
1478 | /* Silently promote "you're not bound, there was nothing to do" | |
1479 | * to success, since the client was just asking us to | |
1480 | * make sure everything was done. | |
1481 | */ | |
1482 | if (ret == -EINVAL) | |
1483 | ret = 0; | |
2ef7eeaa | 1484 | } else { |
e47c68e9 | 1485 | ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0); |
2ef7eeaa EA |
1486 | } |
1487 | ||
3236f57a | 1488 | unref: |
05394f39 | 1489 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 1490 | unlock: |
673a394b EA |
1491 | mutex_unlock(&dev->struct_mutex); |
1492 | return ret; | |
1493 | } | |
1494 | ||
1495 | /** | |
1496 | * Called when user space has done writes to this buffer | |
1497 | */ | |
1498 | int | |
1499 | i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 1500 | struct drm_file *file) |
673a394b EA |
1501 | { |
1502 | struct drm_i915_gem_sw_finish *args = data; | |
05394f39 | 1503 | struct drm_i915_gem_object *obj; |
673a394b EA |
1504 | int ret = 0; |
1505 | ||
76c1dec1 | 1506 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 1507 | if (ret) |
76c1dec1 | 1508 | return ret; |
1d7cfea1 | 1509 | |
05394f39 | 1510 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 1511 | if (&obj->base == NULL) { |
1d7cfea1 CW |
1512 | ret = -ENOENT; |
1513 | goto unlock; | |
673a394b EA |
1514 | } |
1515 | ||
673a394b | 1516 | /* Pinned buffers may be scanout, so flush the cache */ |
2c22569b CW |
1517 | if (obj->pin_display) |
1518 | i915_gem_object_flush_cpu_write_domain(obj, true); | |
e47c68e9 | 1519 | |
05394f39 | 1520 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 1521 | unlock: |
673a394b EA |
1522 | mutex_unlock(&dev->struct_mutex); |
1523 | return ret; | |
1524 | } | |
1525 | ||
1526 | /** | |
1527 | * Maps the contents of an object, returning the address it is mapped | |
1528 | * into. | |
1529 | * | |
1530 | * While the mapping holds a reference on the contents of the object, it doesn't | |
1531 | * imply a ref on the object itself. | |
34367381 DV |
1532 | * |
1533 | * IMPORTANT: | |
1534 | * | |
1535 | * DRM driver writers who look a this function as an example for how to do GEM | |
1536 | * mmap support, please don't implement mmap support like here. The modern way | |
1537 | * to implement DRM mmap support is with an mmap offset ioctl (like | |
1538 | * i915_gem_mmap_gtt) and then using the mmap syscall on the DRM fd directly. | |
1539 | * That way debug tooling like valgrind will understand what's going on, hiding | |
1540 | * the mmap call in a driver private ioctl will break that. The i915 driver only | |
1541 | * does cpu mmaps this way because we didn't know better. | |
673a394b EA |
1542 | */ |
1543 | int | |
1544 | i915_gem_mmap_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 1545 | struct drm_file *file) |
673a394b EA |
1546 | { |
1547 | struct drm_i915_gem_mmap *args = data; | |
1548 | struct drm_gem_object *obj; | |
673a394b EA |
1549 | unsigned long addr; |
1550 | ||
05394f39 | 1551 | obj = drm_gem_object_lookup(dev, file, args->handle); |
673a394b | 1552 | if (obj == NULL) |
bf79cb91 | 1553 | return -ENOENT; |
673a394b | 1554 | |
1286ff73 DV |
1555 | /* prime objects have no backing filp to GEM mmap |
1556 | * pages from. | |
1557 | */ | |
1558 | if (!obj->filp) { | |
1559 | drm_gem_object_unreference_unlocked(obj); | |
1560 | return -EINVAL; | |
1561 | } | |
1562 | ||
6be5ceb0 | 1563 | addr = vm_mmap(obj->filp, 0, args->size, |
673a394b EA |
1564 | PROT_READ | PROT_WRITE, MAP_SHARED, |
1565 | args->offset); | |
bc9025bd | 1566 | drm_gem_object_unreference_unlocked(obj); |
673a394b EA |
1567 | if (IS_ERR((void *)addr)) |
1568 | return addr; | |
1569 | ||
1570 | args->addr_ptr = (uint64_t) addr; | |
1571 | ||
1572 | return 0; | |
1573 | } | |
1574 | ||
de151cf6 JB |
1575 | /** |
1576 | * i915_gem_fault - fault a page into the GTT | |
1577 | * vma: VMA in question | |
1578 | * vmf: fault info | |
1579 | * | |
1580 | * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped | |
1581 | * from userspace. The fault handler takes care of binding the object to | |
1582 | * the GTT (if needed), allocating and programming a fence register (again, | |
1583 | * only if needed based on whether the old reg is still valid or the object | |
1584 | * is tiled) and inserting a new PTE into the faulting process. | |
1585 | * | |
1586 | * Note that the faulting process may involve evicting existing objects | |
1587 | * from the GTT and/or fence registers to make room. So performance may | |
1588 | * suffer if the GTT working set is large or there are few fence registers | |
1589 | * left. | |
1590 | */ | |
1591 | int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf) | |
1592 | { | |
05394f39 CW |
1593 | struct drm_i915_gem_object *obj = to_intel_bo(vma->vm_private_data); |
1594 | struct drm_device *dev = obj->base.dev; | |
3e31c6c0 | 1595 | struct drm_i915_private *dev_priv = dev->dev_private; |
de151cf6 JB |
1596 | pgoff_t page_offset; |
1597 | unsigned long pfn; | |
1598 | int ret = 0; | |
0f973f27 | 1599 | bool write = !!(vmf->flags & FAULT_FLAG_WRITE); |
de151cf6 | 1600 | |
f65c9168 PZ |
1601 | intel_runtime_pm_get(dev_priv); |
1602 | ||
de151cf6 JB |
1603 | /* We don't use vmf->pgoff since that has the fake offset */ |
1604 | page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >> | |
1605 | PAGE_SHIFT; | |
1606 | ||
d9bc7e9f CW |
1607 | ret = i915_mutex_lock_interruptible(dev); |
1608 | if (ret) | |
1609 | goto out; | |
a00b10c3 | 1610 | |
db53a302 CW |
1611 | trace_i915_gem_object_fault(obj, page_offset, true, write); |
1612 | ||
6e4930f6 CW |
1613 | /* Try to flush the object off the GPU first without holding the lock. |
1614 | * Upon reacquiring the lock, we will perform our sanity checks and then | |
1615 | * repeat the flush holding the lock in the normal manner to catch cases | |
1616 | * where we are gazumped. | |
1617 | */ | |
1618 | ret = i915_gem_object_wait_rendering__nonblocking(obj, NULL, !write); | |
1619 | if (ret) | |
1620 | goto unlock; | |
1621 | ||
eb119bd6 CW |
1622 | /* Access to snoopable pages through the GTT is incoherent. */ |
1623 | if (obj->cache_level != I915_CACHE_NONE && !HAS_LLC(dev)) { | |
ddeff6ee | 1624 | ret = -EFAULT; |
eb119bd6 CW |
1625 | goto unlock; |
1626 | } | |
1627 | ||
d9bc7e9f | 1628 | /* Now bind it into the GTT if needed */ |
1ec9e26d | 1629 | ret = i915_gem_obj_ggtt_pin(obj, 0, PIN_MAPPABLE); |
c9839303 CW |
1630 | if (ret) |
1631 | goto unlock; | |
4a684a41 | 1632 | |
c9839303 CW |
1633 | ret = i915_gem_object_set_to_gtt_domain(obj, write); |
1634 | if (ret) | |
1635 | goto unpin; | |
74898d7e | 1636 | |
06d98131 | 1637 | ret = i915_gem_object_get_fence(obj); |
d9e86c0e | 1638 | if (ret) |
c9839303 | 1639 | goto unpin; |
7d1c4804 | 1640 | |
b90b91d8 | 1641 | /* Finally, remap it using the new GTT offset */ |
f343c5f6 BW |
1642 | pfn = dev_priv->gtt.mappable_base + i915_gem_obj_ggtt_offset(obj); |
1643 | pfn >>= PAGE_SHIFT; | |
de151cf6 | 1644 | |
b90b91d8 | 1645 | if (!obj->fault_mappable) { |
beff0d0f VS |
1646 | unsigned long size = min_t(unsigned long, |
1647 | vma->vm_end - vma->vm_start, | |
1648 | obj->base.size); | |
b90b91d8 CW |
1649 | int i; |
1650 | ||
beff0d0f | 1651 | for (i = 0; i < size >> PAGE_SHIFT; i++) { |
b90b91d8 CW |
1652 | ret = vm_insert_pfn(vma, |
1653 | (unsigned long)vma->vm_start + i * PAGE_SIZE, | |
1654 | pfn + i); | |
1655 | if (ret) | |
1656 | break; | |
1657 | } | |
1658 | ||
1659 | obj->fault_mappable = true; | |
1660 | } else | |
1661 | ret = vm_insert_pfn(vma, | |
1662 | (unsigned long)vmf->virtual_address, | |
1663 | pfn + page_offset); | |
c9839303 | 1664 | unpin: |
d7f46fc4 | 1665 | i915_gem_object_ggtt_unpin(obj); |
c715089f | 1666 | unlock: |
de151cf6 | 1667 | mutex_unlock(&dev->struct_mutex); |
d9bc7e9f | 1668 | out: |
de151cf6 | 1669 | switch (ret) { |
d9bc7e9f | 1670 | case -EIO: |
2232f031 DV |
1671 | /* |
1672 | * We eat errors when the gpu is terminally wedged to avoid | |
1673 | * userspace unduly crashing (gl has no provisions for mmaps to | |
1674 | * fail). But any other -EIO isn't ours (e.g. swap in failure) | |
1675 | * and so needs to be reported. | |
1676 | */ | |
1677 | if (!i915_terminally_wedged(&dev_priv->gpu_error)) { | |
f65c9168 PZ |
1678 | ret = VM_FAULT_SIGBUS; |
1679 | break; | |
1680 | } | |
045e769a | 1681 | case -EAGAIN: |
571c608d DV |
1682 | /* |
1683 | * EAGAIN means the gpu is hung and we'll wait for the error | |
1684 | * handler to reset everything when re-faulting in | |
1685 | * i915_mutex_lock_interruptible. | |
d9bc7e9f | 1686 | */ |
c715089f CW |
1687 | case 0: |
1688 | case -ERESTARTSYS: | |
bed636ab | 1689 | case -EINTR: |
e79e0fe3 DR |
1690 | case -EBUSY: |
1691 | /* | |
1692 | * EBUSY is ok: this just means that another thread | |
1693 | * already did the job. | |
1694 | */ | |
f65c9168 PZ |
1695 | ret = VM_FAULT_NOPAGE; |
1696 | break; | |
de151cf6 | 1697 | case -ENOMEM: |
f65c9168 PZ |
1698 | ret = VM_FAULT_OOM; |
1699 | break; | |
a7c2e1aa | 1700 | case -ENOSPC: |
45d67817 | 1701 | case -EFAULT: |
f65c9168 PZ |
1702 | ret = VM_FAULT_SIGBUS; |
1703 | break; | |
de151cf6 | 1704 | default: |
a7c2e1aa | 1705 | WARN_ONCE(ret, "unhandled error in i915_gem_fault: %i\n", ret); |
f65c9168 PZ |
1706 | ret = VM_FAULT_SIGBUS; |
1707 | break; | |
de151cf6 | 1708 | } |
f65c9168 PZ |
1709 | |
1710 | intel_runtime_pm_put(dev_priv); | |
1711 | return ret; | |
de151cf6 JB |
1712 | } |
1713 | ||
901782b2 CW |
1714 | /** |
1715 | * i915_gem_release_mmap - remove physical page mappings | |
1716 | * @obj: obj in question | |
1717 | * | |
af901ca1 | 1718 | * Preserve the reservation of the mmapping with the DRM core code, but |
901782b2 CW |
1719 | * relinquish ownership of the pages back to the system. |
1720 | * | |
1721 | * It is vital that we remove the page mapping if we have mapped a tiled | |
1722 | * object through the GTT and then lose the fence register due to | |
1723 | * resource pressure. Similarly if the object has been moved out of the | |
1724 | * aperture, than pages mapped into userspace must be revoked. Removing the | |
1725 | * mapping will then trigger a page fault on the next user access, allowing | |
1726 | * fixup by i915_gem_fault(). | |
1727 | */ | |
d05ca301 | 1728 | void |
05394f39 | 1729 | i915_gem_release_mmap(struct drm_i915_gem_object *obj) |
901782b2 | 1730 | { |
6299f992 CW |
1731 | if (!obj->fault_mappable) |
1732 | return; | |
901782b2 | 1733 | |
6796cb16 DH |
1734 | drm_vma_node_unmap(&obj->base.vma_node, |
1735 | obj->base.dev->anon_inode->i_mapping); | |
6299f992 | 1736 | obj->fault_mappable = false; |
901782b2 CW |
1737 | } |
1738 | ||
eedd10f4 CW |
1739 | void |
1740 | i915_gem_release_all_mmaps(struct drm_i915_private *dev_priv) | |
1741 | { | |
1742 | struct drm_i915_gem_object *obj; | |
1743 | ||
1744 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) | |
1745 | i915_gem_release_mmap(obj); | |
1746 | } | |
1747 | ||
0fa87796 | 1748 | uint32_t |
e28f8711 | 1749 | i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode) |
92b88aeb | 1750 | { |
e28f8711 | 1751 | uint32_t gtt_size; |
92b88aeb CW |
1752 | |
1753 | if (INTEL_INFO(dev)->gen >= 4 || | |
e28f8711 CW |
1754 | tiling_mode == I915_TILING_NONE) |
1755 | return size; | |
92b88aeb CW |
1756 | |
1757 | /* Previous chips need a power-of-two fence region when tiling */ | |
1758 | if (INTEL_INFO(dev)->gen == 3) | |
e28f8711 | 1759 | gtt_size = 1024*1024; |
92b88aeb | 1760 | else |
e28f8711 | 1761 | gtt_size = 512*1024; |
92b88aeb | 1762 | |
e28f8711 CW |
1763 | while (gtt_size < size) |
1764 | gtt_size <<= 1; | |
92b88aeb | 1765 | |
e28f8711 | 1766 | return gtt_size; |
92b88aeb CW |
1767 | } |
1768 | ||
de151cf6 JB |
1769 | /** |
1770 | * i915_gem_get_gtt_alignment - return required GTT alignment for an object | |
1771 | * @obj: object to check | |
1772 | * | |
1773 | * Return the required GTT alignment for an object, taking into account | |
5e783301 | 1774 | * potential fence register mapping. |
de151cf6 | 1775 | */ |
d865110c ID |
1776 | uint32_t |
1777 | i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size, | |
1778 | int tiling_mode, bool fenced) | |
de151cf6 | 1779 | { |
de151cf6 JB |
1780 | /* |
1781 | * Minimum alignment is 4k (GTT page size), but might be greater | |
1782 | * if a fence register is needed for the object. | |
1783 | */ | |
d865110c | 1784 | if (INTEL_INFO(dev)->gen >= 4 || (!fenced && IS_G33(dev)) || |
e28f8711 | 1785 | tiling_mode == I915_TILING_NONE) |
de151cf6 JB |
1786 | return 4096; |
1787 | ||
a00b10c3 CW |
1788 | /* |
1789 | * Previous chips need to be aligned to the size of the smallest | |
1790 | * fence register that can contain the object. | |
1791 | */ | |
e28f8711 | 1792 | return i915_gem_get_gtt_size(dev, size, tiling_mode); |
a00b10c3 CW |
1793 | } |
1794 | ||
d8cb5086 CW |
1795 | static int i915_gem_object_create_mmap_offset(struct drm_i915_gem_object *obj) |
1796 | { | |
1797 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; | |
1798 | int ret; | |
1799 | ||
0de23977 | 1800 | if (drm_vma_node_has_offset(&obj->base.vma_node)) |
d8cb5086 CW |
1801 | return 0; |
1802 | ||
da494d7c DV |
1803 | dev_priv->mm.shrinker_no_lock_stealing = true; |
1804 | ||
d8cb5086 CW |
1805 | ret = drm_gem_create_mmap_offset(&obj->base); |
1806 | if (ret != -ENOSPC) | |
da494d7c | 1807 | goto out; |
d8cb5086 CW |
1808 | |
1809 | /* Badly fragmented mmap space? The only way we can recover | |
1810 | * space is by destroying unwanted objects. We can't randomly release | |
1811 | * mmap_offsets as userspace expects them to be persistent for the | |
1812 | * lifetime of the objects. The closest we can is to release the | |
1813 | * offsets on purgeable objects by truncating it and marking it purged, | |
1814 | * which prevents userspace from ever using that object again. | |
1815 | */ | |
21ab4e74 CW |
1816 | i915_gem_shrink(dev_priv, |
1817 | obj->base.size >> PAGE_SHIFT, | |
1818 | I915_SHRINK_BOUND | | |
1819 | I915_SHRINK_UNBOUND | | |
1820 | I915_SHRINK_PURGEABLE); | |
d8cb5086 CW |
1821 | ret = drm_gem_create_mmap_offset(&obj->base); |
1822 | if (ret != -ENOSPC) | |
da494d7c | 1823 | goto out; |
d8cb5086 CW |
1824 | |
1825 | i915_gem_shrink_all(dev_priv); | |
da494d7c DV |
1826 | ret = drm_gem_create_mmap_offset(&obj->base); |
1827 | out: | |
1828 | dev_priv->mm.shrinker_no_lock_stealing = false; | |
1829 | ||
1830 | return ret; | |
d8cb5086 CW |
1831 | } |
1832 | ||
1833 | static void i915_gem_object_free_mmap_offset(struct drm_i915_gem_object *obj) | |
1834 | { | |
d8cb5086 CW |
1835 | drm_gem_free_mmap_offset(&obj->base); |
1836 | } | |
1837 | ||
355a7018 | 1838 | static int |
ff72145b DA |
1839 | i915_gem_mmap_gtt(struct drm_file *file, |
1840 | struct drm_device *dev, | |
355a7018 | 1841 | uint32_t handle, bool dumb, |
ff72145b | 1842 | uint64_t *offset) |
de151cf6 | 1843 | { |
da761a6e | 1844 | struct drm_i915_private *dev_priv = dev->dev_private; |
05394f39 | 1845 | struct drm_i915_gem_object *obj; |
de151cf6 JB |
1846 | int ret; |
1847 | ||
76c1dec1 | 1848 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 1849 | if (ret) |
76c1dec1 | 1850 | return ret; |
de151cf6 | 1851 | |
ff72145b | 1852 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle)); |
c8725226 | 1853 | if (&obj->base == NULL) { |
1d7cfea1 CW |
1854 | ret = -ENOENT; |
1855 | goto unlock; | |
1856 | } | |
de151cf6 | 1857 | |
355a7018 TH |
1858 | /* |
1859 | * We don't allow dumb mmaps on objects created using another | |
1860 | * interface. | |
1861 | */ | |
1862 | WARN_ONCE(dumb && !(obj->base.dumb || obj->base.import_attach), | |
1863 | "Illegal dumb map of accelerated buffer.\n"); | |
1864 | ||
5d4545ae | 1865 | if (obj->base.size > dev_priv->gtt.mappable_end) { |
da761a6e | 1866 | ret = -E2BIG; |
ff56b0bc | 1867 | goto out; |
da761a6e CW |
1868 | } |
1869 | ||
05394f39 | 1870 | if (obj->madv != I915_MADV_WILLNEED) { |
bd9b6a4e | 1871 | DRM_DEBUG("Attempting to mmap a purgeable buffer\n"); |
8c99e57d | 1872 | ret = -EFAULT; |
1d7cfea1 | 1873 | goto out; |
ab18282d CW |
1874 | } |
1875 | ||
d8cb5086 CW |
1876 | ret = i915_gem_object_create_mmap_offset(obj); |
1877 | if (ret) | |
1878 | goto out; | |
de151cf6 | 1879 | |
0de23977 | 1880 | *offset = drm_vma_node_offset_addr(&obj->base.vma_node); |
de151cf6 | 1881 | |
1d7cfea1 | 1882 | out: |
05394f39 | 1883 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 1884 | unlock: |
de151cf6 | 1885 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 1886 | return ret; |
de151cf6 JB |
1887 | } |
1888 | ||
355a7018 TH |
1889 | int |
1890 | i915_gem_dumb_map_offset(struct drm_file *file, | |
1891 | struct drm_device *dev, | |
1892 | uint32_t handle, | |
1893 | uint64_t *offset) | |
1894 | { | |
1895 | return i915_gem_mmap_gtt(file, dev, handle, true, offset); | |
1896 | } | |
1897 | ||
ff72145b DA |
1898 | /** |
1899 | * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing | |
1900 | * @dev: DRM device | |
1901 | * @data: GTT mapping ioctl data | |
1902 | * @file: GEM object info | |
1903 | * | |
1904 | * Simply returns the fake offset to userspace so it can mmap it. | |
1905 | * The mmap call will end up in drm_gem_mmap(), which will set things | |
1906 | * up so we can get faults in the handler above. | |
1907 | * | |
1908 | * The fault handler will take care of binding the object into the GTT | |
1909 | * (since it may have been evicted to make room for something), allocating | |
1910 | * a fence register, and mapping the appropriate aperture address into | |
1911 | * userspace. | |
1912 | */ | |
1913 | int | |
1914 | i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data, | |
1915 | struct drm_file *file) | |
1916 | { | |
1917 | struct drm_i915_gem_mmap_gtt *args = data; | |
1918 | ||
355a7018 | 1919 | return i915_gem_mmap_gtt(file, dev, args->handle, false, &args->offset); |
ff72145b DA |
1920 | } |
1921 | ||
5537252b CW |
1922 | static inline int |
1923 | i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj) | |
1924 | { | |
1925 | return obj->madv == I915_MADV_DONTNEED; | |
1926 | } | |
1927 | ||
225067ee DV |
1928 | /* Immediately discard the backing storage */ |
1929 | static void | |
1930 | i915_gem_object_truncate(struct drm_i915_gem_object *obj) | |
e5281ccd | 1931 | { |
4d6294bf | 1932 | i915_gem_object_free_mmap_offset(obj); |
1286ff73 | 1933 | |
4d6294bf CW |
1934 | if (obj->base.filp == NULL) |
1935 | return; | |
e5281ccd | 1936 | |
225067ee DV |
1937 | /* Our goal here is to return as much of the memory as |
1938 | * is possible back to the system as we are called from OOM. | |
1939 | * To do this we must instruct the shmfs to drop all of its | |
1940 | * backing pages, *now*. | |
1941 | */ | |
5537252b | 1942 | shmem_truncate_range(file_inode(obj->base.filp), 0, (loff_t)-1); |
225067ee DV |
1943 | obj->madv = __I915_MADV_PURGED; |
1944 | } | |
e5281ccd | 1945 | |
5537252b CW |
1946 | /* Try to discard unwanted pages */ |
1947 | static void | |
1948 | i915_gem_object_invalidate(struct drm_i915_gem_object *obj) | |
225067ee | 1949 | { |
5537252b CW |
1950 | struct address_space *mapping; |
1951 | ||
1952 | switch (obj->madv) { | |
1953 | case I915_MADV_DONTNEED: | |
1954 | i915_gem_object_truncate(obj); | |
1955 | case __I915_MADV_PURGED: | |
1956 | return; | |
1957 | } | |
1958 | ||
1959 | if (obj->base.filp == NULL) | |
1960 | return; | |
1961 | ||
1962 | mapping = file_inode(obj->base.filp)->i_mapping, | |
1963 | invalidate_mapping_pages(mapping, 0, (loff_t)-1); | |
e5281ccd CW |
1964 | } |
1965 | ||
5cdf5881 | 1966 | static void |
05394f39 | 1967 | i915_gem_object_put_pages_gtt(struct drm_i915_gem_object *obj) |
673a394b | 1968 | { |
90797e6d ID |
1969 | struct sg_page_iter sg_iter; |
1970 | int ret; | |
1286ff73 | 1971 | |
05394f39 | 1972 | BUG_ON(obj->madv == __I915_MADV_PURGED); |
673a394b | 1973 | |
6c085a72 CW |
1974 | ret = i915_gem_object_set_to_cpu_domain(obj, true); |
1975 | if (ret) { | |
1976 | /* In the event of a disaster, abandon all caches and | |
1977 | * hope for the best. | |
1978 | */ | |
1979 | WARN_ON(ret != -EIO); | |
2c22569b | 1980 | i915_gem_clflush_object(obj, true); |
6c085a72 CW |
1981 | obj->base.read_domains = obj->base.write_domain = I915_GEM_DOMAIN_CPU; |
1982 | } | |
1983 | ||
6dacfd2f | 1984 | if (i915_gem_object_needs_bit17_swizzle(obj)) |
280b713b EA |
1985 | i915_gem_object_save_bit_17_swizzle(obj); |
1986 | ||
05394f39 CW |
1987 | if (obj->madv == I915_MADV_DONTNEED) |
1988 | obj->dirty = 0; | |
3ef94daa | 1989 | |
90797e6d | 1990 | for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, 0) { |
2db76d7c | 1991 | struct page *page = sg_page_iter_page(&sg_iter); |
9da3da66 | 1992 | |
05394f39 | 1993 | if (obj->dirty) |
9da3da66 | 1994 | set_page_dirty(page); |
3ef94daa | 1995 | |
05394f39 | 1996 | if (obj->madv == I915_MADV_WILLNEED) |
9da3da66 | 1997 | mark_page_accessed(page); |
3ef94daa | 1998 | |
9da3da66 | 1999 | page_cache_release(page); |
3ef94daa | 2000 | } |
05394f39 | 2001 | obj->dirty = 0; |
673a394b | 2002 | |
9da3da66 CW |
2003 | sg_free_table(obj->pages); |
2004 | kfree(obj->pages); | |
37e680a1 | 2005 | } |
6c085a72 | 2006 | |
dd624afd | 2007 | int |
37e680a1 CW |
2008 | i915_gem_object_put_pages(struct drm_i915_gem_object *obj) |
2009 | { | |
2010 | const struct drm_i915_gem_object_ops *ops = obj->ops; | |
2011 | ||
2f745ad3 | 2012 | if (obj->pages == NULL) |
37e680a1 CW |
2013 | return 0; |
2014 | ||
a5570178 CW |
2015 | if (obj->pages_pin_count) |
2016 | return -EBUSY; | |
2017 | ||
9843877d | 2018 | BUG_ON(i915_gem_obj_bound_any(obj)); |
3e123027 | 2019 | |
a2165e31 CW |
2020 | /* ->put_pages might need to allocate memory for the bit17 swizzle |
2021 | * array, hence protect them from being reaped by removing them from gtt | |
2022 | * lists early. */ | |
35c20a60 | 2023 | list_del(&obj->global_list); |
a2165e31 | 2024 | |
37e680a1 | 2025 | ops->put_pages(obj); |
05394f39 | 2026 | obj->pages = NULL; |
37e680a1 | 2027 | |
5537252b | 2028 | i915_gem_object_invalidate(obj); |
6c085a72 CW |
2029 | |
2030 | return 0; | |
2031 | } | |
2032 | ||
21ab4e74 CW |
2033 | unsigned long |
2034 | i915_gem_shrink(struct drm_i915_private *dev_priv, | |
2035 | long target, unsigned flags) | |
6c085a72 | 2036 | { |
60a53727 CW |
2037 | const struct { |
2038 | struct list_head *list; | |
2039 | unsigned int bit; | |
2040 | } phases[] = { | |
2041 | { &dev_priv->mm.unbound_list, I915_SHRINK_UNBOUND }, | |
2042 | { &dev_priv->mm.bound_list, I915_SHRINK_BOUND }, | |
2043 | { NULL, 0 }, | |
2044 | }, *phase; | |
d9973b43 | 2045 | unsigned long count = 0; |
6c085a72 | 2046 | |
57094f82 | 2047 | /* |
c8725f3d | 2048 | * As we may completely rewrite the (un)bound list whilst unbinding |
57094f82 CW |
2049 | * (due to retiring requests) we have to strictly process only |
2050 | * one element of the list at the time, and recheck the list | |
2051 | * on every iteration. | |
c8725f3d CW |
2052 | * |
2053 | * In particular, we must hold a reference whilst removing the | |
2054 | * object as we may end up waiting for and/or retiring the objects. | |
2055 | * This might release the final reference (held by the active list) | |
2056 | * and result in the object being freed from under us. This is | |
2057 | * similar to the precautions the eviction code must take whilst | |
2058 | * removing objects. | |
2059 | * | |
2060 | * Also note that although these lists do not hold a reference to | |
2061 | * the object we can safely grab one here: The final object | |
2062 | * unreferencing and the bound_list are both protected by the | |
2063 | * dev->struct_mutex and so we won't ever be able to observe an | |
2064 | * object on the bound_list with a reference count equals 0. | |
57094f82 | 2065 | */ |
60a53727 | 2066 | for (phase = phases; phase->list; phase++) { |
21ab4e74 | 2067 | struct list_head still_in_list; |
c8725f3d | 2068 | |
60a53727 CW |
2069 | if ((flags & phase->bit) == 0) |
2070 | continue; | |
80dcfdbd | 2071 | |
21ab4e74 | 2072 | INIT_LIST_HEAD(&still_in_list); |
60a53727 | 2073 | while (count < target && !list_empty(phase->list)) { |
21ab4e74 CW |
2074 | struct drm_i915_gem_object *obj; |
2075 | struct i915_vma *vma, *v; | |
57094f82 | 2076 | |
60a53727 | 2077 | obj = list_first_entry(phase->list, |
21ab4e74 CW |
2078 | typeof(*obj), global_list); |
2079 | list_move_tail(&obj->global_list, &still_in_list); | |
80dcfdbd | 2080 | |
60a53727 CW |
2081 | if (flags & I915_SHRINK_PURGEABLE && |
2082 | !i915_gem_object_is_purgeable(obj)) | |
21ab4e74 | 2083 | continue; |
57094f82 | 2084 | |
21ab4e74 | 2085 | drm_gem_object_reference(&obj->base); |
80dcfdbd | 2086 | |
60a53727 CW |
2087 | /* For the unbound phase, this should be a no-op! */ |
2088 | list_for_each_entry_safe(vma, v, | |
2089 | &obj->vma_list, vma_link) | |
21ab4e74 CW |
2090 | if (i915_vma_unbind(vma)) |
2091 | break; | |
57094f82 | 2092 | |
21ab4e74 CW |
2093 | if (i915_gem_object_put_pages(obj) == 0) |
2094 | count += obj->base.size >> PAGE_SHIFT; | |
2095 | ||
2096 | drm_gem_object_unreference(&obj->base); | |
2097 | } | |
60a53727 | 2098 | list_splice(&still_in_list, phase->list); |
6c085a72 CW |
2099 | } |
2100 | ||
2101 | return count; | |
2102 | } | |
2103 | ||
d9973b43 | 2104 | static unsigned long |
6c085a72 CW |
2105 | i915_gem_shrink_all(struct drm_i915_private *dev_priv) |
2106 | { | |
6c085a72 | 2107 | i915_gem_evict_everything(dev_priv->dev); |
21ab4e74 CW |
2108 | return i915_gem_shrink(dev_priv, LONG_MAX, |
2109 | I915_SHRINK_BOUND | I915_SHRINK_UNBOUND); | |
225067ee DV |
2110 | } |
2111 | ||
37e680a1 | 2112 | static int |
6c085a72 | 2113 | i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj) |
e5281ccd | 2114 | { |
6c085a72 | 2115 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
e5281ccd CW |
2116 | int page_count, i; |
2117 | struct address_space *mapping; | |
9da3da66 CW |
2118 | struct sg_table *st; |
2119 | struct scatterlist *sg; | |
90797e6d | 2120 | struct sg_page_iter sg_iter; |
e5281ccd | 2121 | struct page *page; |
90797e6d | 2122 | unsigned long last_pfn = 0; /* suppress gcc warning */ |
6c085a72 | 2123 | gfp_t gfp; |
e5281ccd | 2124 | |
6c085a72 CW |
2125 | /* Assert that the object is not currently in any GPU domain. As it |
2126 | * wasn't in the GTT, there shouldn't be any way it could have been in | |
2127 | * a GPU cache | |
2128 | */ | |
2129 | BUG_ON(obj->base.read_domains & I915_GEM_GPU_DOMAINS); | |
2130 | BUG_ON(obj->base.write_domain & I915_GEM_GPU_DOMAINS); | |
2131 | ||
9da3da66 CW |
2132 | st = kmalloc(sizeof(*st), GFP_KERNEL); |
2133 | if (st == NULL) | |
2134 | return -ENOMEM; | |
2135 | ||
05394f39 | 2136 | page_count = obj->base.size / PAGE_SIZE; |
9da3da66 | 2137 | if (sg_alloc_table(st, page_count, GFP_KERNEL)) { |
9da3da66 | 2138 | kfree(st); |
e5281ccd | 2139 | return -ENOMEM; |
9da3da66 | 2140 | } |
e5281ccd | 2141 | |
9da3da66 CW |
2142 | /* Get the list of pages out of our struct file. They'll be pinned |
2143 | * at this point until we release them. | |
2144 | * | |
2145 | * Fail silently without starting the shrinker | |
2146 | */ | |
496ad9aa | 2147 | mapping = file_inode(obj->base.filp)->i_mapping; |
6c085a72 | 2148 | gfp = mapping_gfp_mask(mapping); |
caf49191 | 2149 | gfp |= __GFP_NORETRY | __GFP_NOWARN | __GFP_NO_KSWAPD; |
6c085a72 | 2150 | gfp &= ~(__GFP_IO | __GFP_WAIT); |
90797e6d ID |
2151 | sg = st->sgl; |
2152 | st->nents = 0; | |
2153 | for (i = 0; i < page_count; i++) { | |
6c085a72 CW |
2154 | page = shmem_read_mapping_page_gfp(mapping, i, gfp); |
2155 | if (IS_ERR(page)) { | |
21ab4e74 CW |
2156 | i915_gem_shrink(dev_priv, |
2157 | page_count, | |
2158 | I915_SHRINK_BOUND | | |
2159 | I915_SHRINK_UNBOUND | | |
2160 | I915_SHRINK_PURGEABLE); | |
6c085a72 CW |
2161 | page = shmem_read_mapping_page_gfp(mapping, i, gfp); |
2162 | } | |
2163 | if (IS_ERR(page)) { | |
2164 | /* We've tried hard to allocate the memory by reaping | |
2165 | * our own buffer, now let the real VM do its job and | |
2166 | * go down in flames if truly OOM. | |
2167 | */ | |
6c085a72 | 2168 | i915_gem_shrink_all(dev_priv); |
f461d1be | 2169 | page = shmem_read_mapping_page(mapping, i); |
6c085a72 CW |
2170 | if (IS_ERR(page)) |
2171 | goto err_pages; | |
6c085a72 | 2172 | } |
426729dc KRW |
2173 | #ifdef CONFIG_SWIOTLB |
2174 | if (swiotlb_nr_tbl()) { | |
2175 | st->nents++; | |
2176 | sg_set_page(sg, page, PAGE_SIZE, 0); | |
2177 | sg = sg_next(sg); | |
2178 | continue; | |
2179 | } | |
2180 | #endif | |
90797e6d ID |
2181 | if (!i || page_to_pfn(page) != last_pfn + 1) { |
2182 | if (i) | |
2183 | sg = sg_next(sg); | |
2184 | st->nents++; | |
2185 | sg_set_page(sg, page, PAGE_SIZE, 0); | |
2186 | } else { | |
2187 | sg->length += PAGE_SIZE; | |
2188 | } | |
2189 | last_pfn = page_to_pfn(page); | |
3bbbe706 DV |
2190 | |
2191 | /* Check that the i965g/gm workaround works. */ | |
2192 | WARN_ON((gfp & __GFP_DMA32) && (last_pfn >= 0x00100000UL)); | |
e5281ccd | 2193 | } |
426729dc KRW |
2194 | #ifdef CONFIG_SWIOTLB |
2195 | if (!swiotlb_nr_tbl()) | |
2196 | #endif | |
2197 | sg_mark_end(sg); | |
74ce6b6c CW |
2198 | obj->pages = st; |
2199 | ||
6dacfd2f | 2200 | if (i915_gem_object_needs_bit17_swizzle(obj)) |
e5281ccd CW |
2201 | i915_gem_object_do_bit_17_swizzle(obj); |
2202 | ||
656bfa3a DV |
2203 | if (obj->tiling_mode != I915_TILING_NONE && |
2204 | dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES) | |
2205 | i915_gem_object_pin_pages(obj); | |
2206 | ||
e5281ccd CW |
2207 | return 0; |
2208 | ||
2209 | err_pages: | |
90797e6d ID |
2210 | sg_mark_end(sg); |
2211 | for_each_sg_page(st->sgl, &sg_iter, st->nents, 0) | |
2db76d7c | 2212 | page_cache_release(sg_page_iter_page(&sg_iter)); |
9da3da66 CW |
2213 | sg_free_table(st); |
2214 | kfree(st); | |
0820baf3 CW |
2215 | |
2216 | /* shmemfs first checks if there is enough memory to allocate the page | |
2217 | * and reports ENOSPC should there be insufficient, along with the usual | |
2218 | * ENOMEM for a genuine allocation failure. | |
2219 | * | |
2220 | * We use ENOSPC in our driver to mean that we have run out of aperture | |
2221 | * space and so want to translate the error from shmemfs back to our | |
2222 | * usual understanding of ENOMEM. | |
2223 | */ | |
2224 | if (PTR_ERR(page) == -ENOSPC) | |
2225 | return -ENOMEM; | |
2226 | else | |
2227 | return PTR_ERR(page); | |
673a394b EA |
2228 | } |
2229 | ||
37e680a1 CW |
2230 | /* Ensure that the associated pages are gathered from the backing storage |
2231 | * and pinned into our object. i915_gem_object_get_pages() may be called | |
2232 | * multiple times before they are released by a single call to | |
2233 | * i915_gem_object_put_pages() - once the pages are no longer referenced | |
2234 | * either as a result of memory pressure (reaping pages under the shrinker) | |
2235 | * or as the object is itself released. | |
2236 | */ | |
2237 | int | |
2238 | i915_gem_object_get_pages(struct drm_i915_gem_object *obj) | |
2239 | { | |
2240 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; | |
2241 | const struct drm_i915_gem_object_ops *ops = obj->ops; | |
2242 | int ret; | |
2243 | ||
2f745ad3 | 2244 | if (obj->pages) |
37e680a1 CW |
2245 | return 0; |
2246 | ||
43e28f09 | 2247 | if (obj->madv != I915_MADV_WILLNEED) { |
bd9b6a4e | 2248 | DRM_DEBUG("Attempting to obtain a purgeable object\n"); |
8c99e57d | 2249 | return -EFAULT; |
43e28f09 CW |
2250 | } |
2251 | ||
a5570178 CW |
2252 | BUG_ON(obj->pages_pin_count); |
2253 | ||
37e680a1 CW |
2254 | ret = ops->get_pages(obj); |
2255 | if (ret) | |
2256 | return ret; | |
2257 | ||
35c20a60 | 2258 | list_add_tail(&obj->global_list, &dev_priv->mm.unbound_list); |
37e680a1 | 2259 | return 0; |
673a394b EA |
2260 | } |
2261 | ||
e2d05a8b | 2262 | static void |
05394f39 | 2263 | i915_gem_object_move_to_active(struct drm_i915_gem_object *obj, |
a4872ba6 | 2264 | struct intel_engine_cs *ring) |
673a394b | 2265 | { |
97b2a6a1 | 2266 | struct drm_i915_gem_request *req = intel_ring_get_request(ring); |
617dbe27 | 2267 | |
852835f3 | 2268 | BUG_ON(ring == NULL); |
97b2a6a1 JH |
2269 | if (obj->ring != ring && obj->last_write_req) { |
2270 | /* Keep the request relative to the current ring */ | |
2271 | i915_gem_request_assign(&obj->last_write_req, req); | |
02978ff5 | 2272 | } |
05394f39 | 2273 | obj->ring = ring; |
673a394b EA |
2274 | |
2275 | /* Add a reference if we're newly entering the active list. */ | |
05394f39 CW |
2276 | if (!obj->active) { |
2277 | drm_gem_object_reference(&obj->base); | |
2278 | obj->active = 1; | |
673a394b | 2279 | } |
e35a41de | 2280 | |
05394f39 | 2281 | list_move_tail(&obj->ring_list, &ring->active_list); |
caea7476 | 2282 | |
97b2a6a1 | 2283 | i915_gem_request_assign(&obj->last_read_req, req); |
caea7476 CW |
2284 | } |
2285 | ||
e2d05a8b | 2286 | void i915_vma_move_to_active(struct i915_vma *vma, |
a4872ba6 | 2287 | struct intel_engine_cs *ring) |
e2d05a8b BW |
2288 | { |
2289 | list_move_tail(&vma->mm_list, &vma->vm->active_list); | |
2290 | return i915_gem_object_move_to_active(vma->obj, ring); | |
2291 | } | |
2292 | ||
caea7476 | 2293 | static void |
caea7476 | 2294 | i915_gem_object_move_to_inactive(struct drm_i915_gem_object *obj) |
ce44b0ea | 2295 | { |
ca191b13 | 2296 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
feb822cf BW |
2297 | struct i915_address_space *vm; |
2298 | struct i915_vma *vma; | |
ce44b0ea | 2299 | |
65ce3027 | 2300 | BUG_ON(obj->base.write_domain & ~I915_GEM_GPU_DOMAINS); |
05394f39 | 2301 | BUG_ON(!obj->active); |
caea7476 | 2302 | |
feb822cf BW |
2303 | list_for_each_entry(vm, &dev_priv->vm_list, global_link) { |
2304 | vma = i915_gem_obj_to_vma(obj, vm); | |
2305 | if (vma && !list_empty(&vma->mm_list)) | |
2306 | list_move_tail(&vma->mm_list, &vm->inactive_list); | |
2307 | } | |
caea7476 | 2308 | |
f99d7069 DV |
2309 | intel_fb_obj_flush(obj, true); |
2310 | ||
65ce3027 | 2311 | list_del_init(&obj->ring_list); |
caea7476 CW |
2312 | obj->ring = NULL; |
2313 | ||
97b2a6a1 JH |
2314 | i915_gem_request_assign(&obj->last_read_req, NULL); |
2315 | i915_gem_request_assign(&obj->last_write_req, NULL); | |
65ce3027 CW |
2316 | obj->base.write_domain = 0; |
2317 | ||
97b2a6a1 | 2318 | i915_gem_request_assign(&obj->last_fenced_req, NULL); |
caea7476 CW |
2319 | |
2320 | obj->active = 0; | |
2321 | drm_gem_object_unreference(&obj->base); | |
2322 | ||
2323 | WARN_ON(i915_verify_lists(dev)); | |
ce44b0ea | 2324 | } |
673a394b | 2325 | |
c8725f3d CW |
2326 | static void |
2327 | i915_gem_object_retire(struct drm_i915_gem_object *obj) | |
2328 | { | |
a4872ba6 | 2329 | struct intel_engine_cs *ring = obj->ring; |
c8725f3d CW |
2330 | |
2331 | if (ring == NULL) | |
2332 | return; | |
2333 | ||
1b5a433a | 2334 | if (i915_gem_request_completed(obj->last_read_req, true)) |
c8725f3d CW |
2335 | i915_gem_object_move_to_inactive(obj); |
2336 | } | |
2337 | ||
9d773091 | 2338 | static int |
fca26bb4 | 2339 | i915_gem_init_seqno(struct drm_device *dev, u32 seqno) |
53d227f2 | 2340 | { |
9d773091 | 2341 | struct drm_i915_private *dev_priv = dev->dev_private; |
a4872ba6 | 2342 | struct intel_engine_cs *ring; |
9d773091 | 2343 | int ret, i, j; |
53d227f2 | 2344 | |
107f27a5 | 2345 | /* Carefully retire all requests without writing to the rings */ |
9d773091 | 2346 | for_each_ring(ring, dev_priv, i) { |
107f27a5 CW |
2347 | ret = intel_ring_idle(ring); |
2348 | if (ret) | |
2349 | return ret; | |
9d773091 | 2350 | } |
9d773091 | 2351 | i915_gem_retire_requests(dev); |
107f27a5 CW |
2352 | |
2353 | /* Finally reset hw state */ | |
9d773091 | 2354 | for_each_ring(ring, dev_priv, i) { |
fca26bb4 | 2355 | intel_ring_init_seqno(ring, seqno); |
498d2ac1 | 2356 | |
ebc348b2 BW |
2357 | for (j = 0; j < ARRAY_SIZE(ring->semaphore.sync_seqno); j++) |
2358 | ring->semaphore.sync_seqno[j] = 0; | |
9d773091 | 2359 | } |
53d227f2 | 2360 | |
9d773091 | 2361 | return 0; |
53d227f2 DV |
2362 | } |
2363 | ||
fca26bb4 MK |
2364 | int i915_gem_set_seqno(struct drm_device *dev, u32 seqno) |
2365 | { | |
2366 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2367 | int ret; | |
2368 | ||
2369 | if (seqno == 0) | |
2370 | return -EINVAL; | |
2371 | ||
2372 | /* HWS page needs to be set less than what we | |
2373 | * will inject to ring | |
2374 | */ | |
2375 | ret = i915_gem_init_seqno(dev, seqno - 1); | |
2376 | if (ret) | |
2377 | return ret; | |
2378 | ||
2379 | /* Carefully set the last_seqno value so that wrap | |
2380 | * detection still works | |
2381 | */ | |
2382 | dev_priv->next_seqno = seqno; | |
2383 | dev_priv->last_seqno = seqno - 1; | |
2384 | if (dev_priv->last_seqno == 0) | |
2385 | dev_priv->last_seqno--; | |
2386 | ||
2387 | return 0; | |
2388 | } | |
2389 | ||
9d773091 CW |
2390 | int |
2391 | i915_gem_get_seqno(struct drm_device *dev, u32 *seqno) | |
53d227f2 | 2392 | { |
9d773091 CW |
2393 | struct drm_i915_private *dev_priv = dev->dev_private; |
2394 | ||
2395 | /* reserve 0 for non-seqno */ | |
2396 | if (dev_priv->next_seqno == 0) { | |
fca26bb4 | 2397 | int ret = i915_gem_init_seqno(dev, 0); |
9d773091 CW |
2398 | if (ret) |
2399 | return ret; | |
53d227f2 | 2400 | |
9d773091 CW |
2401 | dev_priv->next_seqno = 1; |
2402 | } | |
53d227f2 | 2403 | |
f72b3435 | 2404 | *seqno = dev_priv->last_seqno = dev_priv->next_seqno++; |
9d773091 | 2405 | return 0; |
53d227f2 DV |
2406 | } |
2407 | ||
a4872ba6 | 2408 | int __i915_add_request(struct intel_engine_cs *ring, |
0025c077 | 2409 | struct drm_file *file, |
9400ae5c | 2410 | struct drm_i915_gem_object *obj) |
673a394b | 2411 | { |
3e31c6c0 | 2412 | struct drm_i915_private *dev_priv = ring->dev->dev_private; |
acb868d3 | 2413 | struct drm_i915_gem_request *request; |
48e29f55 | 2414 | struct intel_ringbuffer *ringbuf; |
7d736f4f | 2415 | u32 request_ring_position, request_start; |
3cce469c CW |
2416 | int ret; |
2417 | ||
6259cead | 2418 | request = ring->outstanding_lazy_request; |
48e29f55 OM |
2419 | if (WARN_ON(request == NULL)) |
2420 | return -ENOMEM; | |
2421 | ||
2422 | if (i915.enable_execlists) { | |
2423 | struct intel_context *ctx = request->ctx; | |
2424 | ringbuf = ctx->engine[ring->id].ringbuf; | |
2425 | } else | |
2426 | ringbuf = ring->buffer; | |
2427 | ||
2428 | request_start = intel_ring_get_tail(ringbuf); | |
cc889e0f DV |
2429 | /* |
2430 | * Emit any outstanding flushes - execbuf can fail to emit the flush | |
2431 | * after having emitted the batchbuffer command. Hence we need to fix | |
2432 | * things up similar to emitting the lazy request. The difference here | |
2433 | * is that the flush _must_ happen before the next request, no matter | |
2434 | * what. | |
2435 | */ | |
48e29f55 OM |
2436 | if (i915.enable_execlists) { |
2437 | ret = logical_ring_flush_all_caches(ringbuf); | |
2438 | if (ret) | |
2439 | return ret; | |
2440 | } else { | |
2441 | ret = intel_ring_flush_all_caches(ring); | |
2442 | if (ret) | |
2443 | return ret; | |
2444 | } | |
cc889e0f | 2445 | |
a71d8d94 CW |
2446 | /* Record the position of the start of the request so that |
2447 | * should we detect the updated seqno part-way through the | |
2448 | * GPU processing the request, we never over-estimate the | |
2449 | * position of the head. | |
2450 | */ | |
48e29f55 | 2451 | request_ring_position = intel_ring_get_tail(ringbuf); |
a71d8d94 | 2452 | |
48e29f55 OM |
2453 | if (i915.enable_execlists) { |
2454 | ret = ring->emit_request(ringbuf); | |
2455 | if (ret) | |
2456 | return ret; | |
2457 | } else { | |
2458 | ret = ring->add_request(ring); | |
2459 | if (ret) | |
2460 | return ret; | |
2461 | } | |
673a394b | 2462 | |
7d736f4f | 2463 | request->head = request_start; |
a71d8d94 | 2464 | request->tail = request_ring_position; |
7d736f4f MK |
2465 | |
2466 | /* Whilst this request exists, batch_obj will be on the | |
2467 | * active_list, and so will hold the active reference. Only when this | |
2468 | * request is retired will the the batch_obj be moved onto the | |
2469 | * inactive_list and lose its active reference. Hence we do not need | |
2470 | * to explicitly hold another reference here. | |
2471 | */ | |
9a7e0c2a | 2472 | request->batch_obj = obj; |
0e50e96b | 2473 | |
48e29f55 OM |
2474 | if (!i915.enable_execlists) { |
2475 | /* Hold a reference to the current context so that we can inspect | |
2476 | * it later in case a hangcheck error event fires. | |
2477 | */ | |
2478 | request->ctx = ring->last_context; | |
2479 | if (request->ctx) | |
2480 | i915_gem_context_reference(request->ctx); | |
2481 | } | |
0e50e96b | 2482 | |
673a394b | 2483 | request->emitted_jiffies = jiffies; |
852835f3 | 2484 | list_add_tail(&request->list, &ring->request_list); |
3bb73aba | 2485 | request->file_priv = NULL; |
852835f3 | 2486 | |
db53a302 CW |
2487 | if (file) { |
2488 | struct drm_i915_file_private *file_priv = file->driver_priv; | |
2489 | ||
1c25595f | 2490 | spin_lock(&file_priv->mm.lock); |
f787a5f5 | 2491 | request->file_priv = file_priv; |
b962442e | 2492 | list_add_tail(&request->client_list, |
f787a5f5 | 2493 | &file_priv->mm.request_list); |
1c25595f | 2494 | spin_unlock(&file_priv->mm.lock); |
b962442e | 2495 | } |
673a394b | 2496 | |
74328ee5 | 2497 | trace_i915_gem_request_add(request); |
6259cead | 2498 | ring->outstanding_lazy_request = NULL; |
db53a302 | 2499 | |
87255483 | 2500 | i915_queue_hangcheck(ring->dev); |
10cd45b6 | 2501 | |
87255483 DV |
2502 | cancel_delayed_work_sync(&dev_priv->mm.idle_work); |
2503 | queue_delayed_work(dev_priv->wq, | |
2504 | &dev_priv->mm.retire_work, | |
2505 | round_jiffies_up_relative(HZ)); | |
2506 | intel_mark_busy(dev_priv->dev); | |
cc889e0f | 2507 | |
3cce469c | 2508 | return 0; |
673a394b EA |
2509 | } |
2510 | ||
f787a5f5 CW |
2511 | static inline void |
2512 | i915_gem_request_remove_from_client(struct drm_i915_gem_request *request) | |
673a394b | 2513 | { |
1c25595f | 2514 | struct drm_i915_file_private *file_priv = request->file_priv; |
673a394b | 2515 | |
1c25595f CW |
2516 | if (!file_priv) |
2517 | return; | |
1c5d22f7 | 2518 | |
1c25595f | 2519 | spin_lock(&file_priv->mm.lock); |
b29c19b6 CW |
2520 | list_del(&request->client_list); |
2521 | request->file_priv = NULL; | |
1c25595f | 2522 | spin_unlock(&file_priv->mm.lock); |
673a394b | 2523 | } |
673a394b | 2524 | |
939fd762 | 2525 | static bool i915_context_is_banned(struct drm_i915_private *dev_priv, |
273497e5 | 2526 | const struct intel_context *ctx) |
be62acb4 | 2527 | { |
44e2c070 | 2528 | unsigned long elapsed; |
be62acb4 | 2529 | |
44e2c070 MK |
2530 | elapsed = get_seconds() - ctx->hang_stats.guilty_ts; |
2531 | ||
2532 | if (ctx->hang_stats.banned) | |
be62acb4 MK |
2533 | return true; |
2534 | ||
2535 | if (elapsed <= DRM_I915_CTX_BAN_PERIOD) { | |
ccc7bed0 | 2536 | if (!i915_gem_context_is_default(ctx)) { |
3fac8978 | 2537 | DRM_DEBUG("context hanging too fast, banning!\n"); |
ccc7bed0 | 2538 | return true; |
88b4aa87 MK |
2539 | } else if (i915_stop_ring_allow_ban(dev_priv)) { |
2540 | if (i915_stop_ring_allow_warn(dev_priv)) | |
2541 | DRM_ERROR("gpu hanging too fast, banning!\n"); | |
ccc7bed0 | 2542 | return true; |
3fac8978 | 2543 | } |
be62acb4 MK |
2544 | } |
2545 | ||
2546 | return false; | |
2547 | } | |
2548 | ||
939fd762 | 2549 | static void i915_set_reset_status(struct drm_i915_private *dev_priv, |
273497e5 | 2550 | struct intel_context *ctx, |
b6b0fac0 | 2551 | const bool guilty) |
aa60c664 | 2552 | { |
44e2c070 MK |
2553 | struct i915_ctx_hang_stats *hs; |
2554 | ||
2555 | if (WARN_ON(!ctx)) | |
2556 | return; | |
aa60c664 | 2557 | |
44e2c070 MK |
2558 | hs = &ctx->hang_stats; |
2559 | ||
2560 | if (guilty) { | |
939fd762 | 2561 | hs->banned = i915_context_is_banned(dev_priv, ctx); |
44e2c070 MK |
2562 | hs->batch_active++; |
2563 | hs->guilty_ts = get_seconds(); | |
2564 | } else { | |
2565 | hs->batch_pending++; | |
aa60c664 MK |
2566 | } |
2567 | } | |
2568 | ||
0e50e96b MK |
2569 | static void i915_gem_free_request(struct drm_i915_gem_request *request) |
2570 | { | |
2571 | list_del(&request->list); | |
2572 | i915_gem_request_remove_from_client(request); | |
2573 | ||
abfe262a JH |
2574 | i915_gem_request_unreference(request); |
2575 | } | |
2576 | ||
2577 | void i915_gem_request_free(struct kref *req_ref) | |
2578 | { | |
2579 | struct drm_i915_gem_request *req = container_of(req_ref, | |
2580 | typeof(*req), ref); | |
2581 | struct intel_context *ctx = req->ctx; | |
2582 | ||
0794aed3 TD |
2583 | if (ctx) { |
2584 | if (i915.enable_execlists) { | |
abfe262a | 2585 | struct intel_engine_cs *ring = req->ring; |
0e50e96b | 2586 | |
0794aed3 TD |
2587 | if (ctx != ring->default_context) |
2588 | intel_lr_context_unpin(ring, ctx); | |
2589 | } | |
abfe262a | 2590 | |
dcb4c12a OM |
2591 | i915_gem_context_unreference(ctx); |
2592 | } | |
abfe262a JH |
2593 | |
2594 | kfree(req); | |
0e50e96b MK |
2595 | } |
2596 | ||
8d9fc7fd | 2597 | struct drm_i915_gem_request * |
a4872ba6 | 2598 | i915_gem_find_active_request(struct intel_engine_cs *ring) |
9375e446 | 2599 | { |
4db080f9 CW |
2600 | struct drm_i915_gem_request *request; |
2601 | ||
2602 | list_for_each_entry(request, &ring->request_list, list) { | |
1b5a433a | 2603 | if (i915_gem_request_completed(request, false)) |
4db080f9 | 2604 | continue; |
aa60c664 | 2605 | |
b6b0fac0 | 2606 | return request; |
4db080f9 | 2607 | } |
b6b0fac0 MK |
2608 | |
2609 | return NULL; | |
2610 | } | |
2611 | ||
2612 | static void i915_gem_reset_ring_status(struct drm_i915_private *dev_priv, | |
a4872ba6 | 2613 | struct intel_engine_cs *ring) |
b6b0fac0 MK |
2614 | { |
2615 | struct drm_i915_gem_request *request; | |
2616 | bool ring_hung; | |
2617 | ||
8d9fc7fd | 2618 | request = i915_gem_find_active_request(ring); |
b6b0fac0 MK |
2619 | |
2620 | if (request == NULL) | |
2621 | return; | |
2622 | ||
2623 | ring_hung = ring->hangcheck.score >= HANGCHECK_SCORE_RING_HUNG; | |
2624 | ||
939fd762 | 2625 | i915_set_reset_status(dev_priv, request->ctx, ring_hung); |
b6b0fac0 MK |
2626 | |
2627 | list_for_each_entry_continue(request, &ring->request_list, list) | |
939fd762 | 2628 | i915_set_reset_status(dev_priv, request->ctx, false); |
4db080f9 | 2629 | } |
aa60c664 | 2630 | |
4db080f9 | 2631 | static void i915_gem_reset_ring_cleanup(struct drm_i915_private *dev_priv, |
a4872ba6 | 2632 | struct intel_engine_cs *ring) |
4db080f9 | 2633 | { |
dfaae392 | 2634 | while (!list_empty(&ring->active_list)) { |
05394f39 | 2635 | struct drm_i915_gem_object *obj; |
9375e446 | 2636 | |
05394f39 CW |
2637 | obj = list_first_entry(&ring->active_list, |
2638 | struct drm_i915_gem_object, | |
2639 | ring_list); | |
9375e446 | 2640 | |
05394f39 | 2641 | i915_gem_object_move_to_inactive(obj); |
673a394b | 2642 | } |
1d62beea | 2643 | |
dcb4c12a OM |
2644 | /* |
2645 | * Clear the execlists queue up before freeing the requests, as those | |
2646 | * are the ones that keep the context and ringbuffer backing objects | |
2647 | * pinned in place. | |
2648 | */ | |
2649 | while (!list_empty(&ring->execlist_queue)) { | |
2650 | struct intel_ctx_submit_request *submit_req; | |
2651 | ||
2652 | submit_req = list_first_entry(&ring->execlist_queue, | |
2653 | struct intel_ctx_submit_request, | |
2654 | execlist_link); | |
2655 | list_del(&submit_req->execlist_link); | |
2656 | intel_runtime_pm_put(dev_priv); | |
2657 | i915_gem_context_unreference(submit_req->ctx); | |
2658 | kfree(submit_req); | |
2659 | } | |
2660 | ||
1d62beea BW |
2661 | /* |
2662 | * We must free the requests after all the corresponding objects have | |
2663 | * been moved off active lists. Which is the same order as the normal | |
2664 | * retire_requests function does. This is important if object hold | |
2665 | * implicit references on things like e.g. ppgtt address spaces through | |
2666 | * the request. | |
2667 | */ | |
2668 | while (!list_empty(&ring->request_list)) { | |
2669 | struct drm_i915_gem_request *request; | |
2670 | ||
2671 | request = list_first_entry(&ring->request_list, | |
2672 | struct drm_i915_gem_request, | |
2673 | list); | |
2674 | ||
2675 | i915_gem_free_request(request); | |
2676 | } | |
e3efda49 | 2677 | |
6259cead JH |
2678 | /* This may not have been flushed before the reset, so clean it now */ |
2679 | i915_gem_request_assign(&ring->outstanding_lazy_request, NULL); | |
673a394b EA |
2680 | } |
2681 | ||
19b2dbde | 2682 | void i915_gem_restore_fences(struct drm_device *dev) |
312817a3 CW |
2683 | { |
2684 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2685 | int i; | |
2686 | ||
4b9de737 | 2687 | for (i = 0; i < dev_priv->num_fence_regs; i++) { |
312817a3 | 2688 | struct drm_i915_fence_reg *reg = &dev_priv->fence_regs[i]; |
7d2cb39c | 2689 | |
94a335db DV |
2690 | /* |
2691 | * Commit delayed tiling changes if we have an object still | |
2692 | * attached to the fence, otherwise just clear the fence. | |
2693 | */ | |
2694 | if (reg->obj) { | |
2695 | i915_gem_object_update_fence(reg->obj, reg, | |
2696 | reg->obj->tiling_mode); | |
2697 | } else { | |
2698 | i915_gem_write_fence(dev, i, NULL); | |
2699 | } | |
312817a3 CW |
2700 | } |
2701 | } | |
2702 | ||
069efc1d | 2703 | void i915_gem_reset(struct drm_device *dev) |
673a394b | 2704 | { |
77f01230 | 2705 | struct drm_i915_private *dev_priv = dev->dev_private; |
a4872ba6 | 2706 | struct intel_engine_cs *ring; |
1ec14ad3 | 2707 | int i; |
673a394b | 2708 | |
4db080f9 CW |
2709 | /* |
2710 | * Before we free the objects from the requests, we need to inspect | |
2711 | * them for finding the guilty party. As the requests only borrow | |
2712 | * their reference to the objects, the inspection must be done first. | |
2713 | */ | |
2714 | for_each_ring(ring, dev_priv, i) | |
2715 | i915_gem_reset_ring_status(dev_priv, ring); | |
2716 | ||
b4519513 | 2717 | for_each_ring(ring, dev_priv, i) |
4db080f9 | 2718 | i915_gem_reset_ring_cleanup(dev_priv, ring); |
dfaae392 | 2719 | |
acce9ffa BW |
2720 | i915_gem_context_reset(dev); |
2721 | ||
19b2dbde | 2722 | i915_gem_restore_fences(dev); |
673a394b EA |
2723 | } |
2724 | ||
2725 | /** | |
2726 | * This function clears the request list as sequence numbers are passed. | |
2727 | */ | |
1cf0ba14 | 2728 | void |
a4872ba6 | 2729 | i915_gem_retire_requests_ring(struct intel_engine_cs *ring) |
673a394b | 2730 | { |
db53a302 | 2731 | if (list_empty(&ring->request_list)) |
6c0594a3 KW |
2732 | return; |
2733 | ||
db53a302 | 2734 | WARN_ON(i915_verify_lists(ring->dev)); |
673a394b | 2735 | |
e9103038 CW |
2736 | /* Move any buffers on the active list that are no longer referenced |
2737 | * by the ringbuffer to the flushing/inactive lists as appropriate, | |
2738 | * before we free the context associated with the requests. | |
2739 | */ | |
2740 | while (!list_empty(&ring->active_list)) { | |
2741 | struct drm_i915_gem_object *obj; | |
2742 | ||
2743 | obj = list_first_entry(&ring->active_list, | |
2744 | struct drm_i915_gem_object, | |
2745 | ring_list); | |
2746 | ||
1b5a433a | 2747 | if (!i915_gem_request_completed(obj->last_read_req, true)) |
e9103038 CW |
2748 | break; |
2749 | ||
2750 | i915_gem_object_move_to_inactive(obj); | |
2751 | } | |
2752 | ||
2753 | ||
852835f3 | 2754 | while (!list_empty(&ring->request_list)) { |
673a394b | 2755 | struct drm_i915_gem_request *request; |
48e29f55 | 2756 | struct intel_ringbuffer *ringbuf; |
673a394b | 2757 | |
852835f3 | 2758 | request = list_first_entry(&ring->request_list, |
673a394b EA |
2759 | struct drm_i915_gem_request, |
2760 | list); | |
673a394b | 2761 | |
1b5a433a | 2762 | if (!i915_gem_request_completed(request, true)) |
b84d5f0c CW |
2763 | break; |
2764 | ||
74328ee5 | 2765 | trace_i915_gem_request_retire(request); |
48e29f55 OM |
2766 | |
2767 | /* This is one of the few common intersection points | |
2768 | * between legacy ringbuffer submission and execlists: | |
2769 | * we need to tell them apart in order to find the correct | |
2770 | * ringbuffer to which the request belongs to. | |
2771 | */ | |
2772 | if (i915.enable_execlists) { | |
2773 | struct intel_context *ctx = request->ctx; | |
2774 | ringbuf = ctx->engine[ring->id].ringbuf; | |
2775 | } else | |
2776 | ringbuf = ring->buffer; | |
2777 | ||
a71d8d94 CW |
2778 | /* We know the GPU must have read the request to have |
2779 | * sent us the seqno + interrupt, so use the position | |
2780 | * of tail of the request to update the last known position | |
2781 | * of the GPU head. | |
2782 | */ | |
48e29f55 | 2783 | ringbuf->last_retired_head = request->tail; |
b84d5f0c | 2784 | |
0e50e96b | 2785 | i915_gem_free_request(request); |
b84d5f0c | 2786 | } |
673a394b | 2787 | |
db53a302 | 2788 | if (unlikely(ring->trace_irq_seqno && |
1b5a433a JH |
2789 | i915_seqno_passed(ring->get_seqno(ring, true), |
2790 | ring->trace_irq_seqno))) { | |
1ec14ad3 | 2791 | ring->irq_put(ring); |
db53a302 | 2792 | ring->trace_irq_seqno = 0; |
9d34e5db | 2793 | } |
23bc5982 | 2794 | |
db53a302 | 2795 | WARN_ON(i915_verify_lists(ring->dev)); |
673a394b EA |
2796 | } |
2797 | ||
b29c19b6 | 2798 | bool |
b09a1fec CW |
2799 | i915_gem_retire_requests(struct drm_device *dev) |
2800 | { | |
3e31c6c0 | 2801 | struct drm_i915_private *dev_priv = dev->dev_private; |
a4872ba6 | 2802 | struct intel_engine_cs *ring; |
b29c19b6 | 2803 | bool idle = true; |
1ec14ad3 | 2804 | int i; |
b09a1fec | 2805 | |
b29c19b6 | 2806 | for_each_ring(ring, dev_priv, i) { |
b4519513 | 2807 | i915_gem_retire_requests_ring(ring); |
b29c19b6 | 2808 | idle &= list_empty(&ring->request_list); |
c86ee3a9 TD |
2809 | if (i915.enable_execlists) { |
2810 | unsigned long flags; | |
2811 | ||
2812 | spin_lock_irqsave(&ring->execlist_lock, flags); | |
2813 | idle &= list_empty(&ring->execlist_queue); | |
2814 | spin_unlock_irqrestore(&ring->execlist_lock, flags); | |
2815 | ||
2816 | intel_execlists_retire_requests(ring); | |
2817 | } | |
b29c19b6 CW |
2818 | } |
2819 | ||
2820 | if (idle) | |
2821 | mod_delayed_work(dev_priv->wq, | |
2822 | &dev_priv->mm.idle_work, | |
2823 | msecs_to_jiffies(100)); | |
2824 | ||
2825 | return idle; | |
b09a1fec CW |
2826 | } |
2827 | ||
75ef9da2 | 2828 | static void |
673a394b EA |
2829 | i915_gem_retire_work_handler(struct work_struct *work) |
2830 | { | |
b29c19b6 CW |
2831 | struct drm_i915_private *dev_priv = |
2832 | container_of(work, typeof(*dev_priv), mm.retire_work.work); | |
2833 | struct drm_device *dev = dev_priv->dev; | |
0a58705b | 2834 | bool idle; |
673a394b | 2835 | |
891b48cf | 2836 | /* Come back later if the device is busy... */ |
b29c19b6 CW |
2837 | idle = false; |
2838 | if (mutex_trylock(&dev->struct_mutex)) { | |
2839 | idle = i915_gem_retire_requests(dev); | |
2840 | mutex_unlock(&dev->struct_mutex); | |
673a394b | 2841 | } |
b29c19b6 | 2842 | if (!idle) |
bcb45086 CW |
2843 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, |
2844 | round_jiffies_up_relative(HZ)); | |
b29c19b6 | 2845 | } |
0a58705b | 2846 | |
b29c19b6 CW |
2847 | static void |
2848 | i915_gem_idle_work_handler(struct work_struct *work) | |
2849 | { | |
2850 | struct drm_i915_private *dev_priv = | |
2851 | container_of(work, typeof(*dev_priv), mm.idle_work.work); | |
2852 | ||
2853 | intel_mark_idle(dev_priv->dev); | |
673a394b EA |
2854 | } |
2855 | ||
30dfebf3 DV |
2856 | /** |
2857 | * Ensures that an object will eventually get non-busy by flushing any required | |
2858 | * write domains, emitting any outstanding lazy request and retiring and | |
2859 | * completed requests. | |
2860 | */ | |
2861 | static int | |
2862 | i915_gem_object_flush_active(struct drm_i915_gem_object *obj) | |
2863 | { | |
2864 | int ret; | |
2865 | ||
2866 | if (obj->active) { | |
b6660d59 | 2867 | ret = i915_gem_check_olr(obj->last_read_req); |
30dfebf3 DV |
2868 | if (ret) |
2869 | return ret; | |
2870 | ||
30dfebf3 DV |
2871 | i915_gem_retire_requests_ring(obj->ring); |
2872 | } | |
2873 | ||
2874 | return 0; | |
2875 | } | |
2876 | ||
23ba4fd0 BW |
2877 | /** |
2878 | * i915_gem_wait_ioctl - implements DRM_IOCTL_I915_GEM_WAIT | |
2879 | * @DRM_IOCTL_ARGS: standard ioctl arguments | |
2880 | * | |
2881 | * Returns 0 if successful, else an error is returned with the remaining time in | |
2882 | * the timeout parameter. | |
2883 | * -ETIME: object is still busy after timeout | |
2884 | * -ERESTARTSYS: signal interrupted the wait | |
2885 | * -ENONENT: object doesn't exist | |
2886 | * Also possible, but rare: | |
2887 | * -EAGAIN: GPU wedged | |
2888 | * -ENOMEM: damn | |
2889 | * -ENODEV: Internal IRQ fail | |
2890 | * -E?: The add request failed | |
2891 | * | |
2892 | * The wait ioctl with a timeout of 0 reimplements the busy ioctl. With any | |
2893 | * non-zero timeout parameter the wait ioctl will wait for the given number of | |
2894 | * nanoseconds on an object becoming unbusy. Since the wait itself does so | |
2895 | * without holding struct_mutex the object may become re-busied before this | |
2896 | * function completes. A similar but shorter * race condition exists in the busy | |
2897 | * ioctl | |
2898 | */ | |
2899 | int | |
2900 | i915_gem_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *file) | |
2901 | { | |
3e31c6c0 | 2902 | struct drm_i915_private *dev_priv = dev->dev_private; |
23ba4fd0 BW |
2903 | struct drm_i915_gem_wait *args = data; |
2904 | struct drm_i915_gem_object *obj; | |
ff865885 | 2905 | struct drm_i915_gem_request *req; |
f69061be | 2906 | unsigned reset_counter; |
23ba4fd0 BW |
2907 | int ret = 0; |
2908 | ||
11b5d511 DV |
2909 | if (args->flags != 0) |
2910 | return -EINVAL; | |
2911 | ||
23ba4fd0 BW |
2912 | ret = i915_mutex_lock_interruptible(dev); |
2913 | if (ret) | |
2914 | return ret; | |
2915 | ||
2916 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->bo_handle)); | |
2917 | if (&obj->base == NULL) { | |
2918 | mutex_unlock(&dev->struct_mutex); | |
2919 | return -ENOENT; | |
2920 | } | |
2921 | ||
30dfebf3 DV |
2922 | /* Need to make sure the object gets inactive eventually. */ |
2923 | ret = i915_gem_object_flush_active(obj); | |
23ba4fd0 BW |
2924 | if (ret) |
2925 | goto out; | |
2926 | ||
97b2a6a1 JH |
2927 | if (!obj->active || !obj->last_read_req) |
2928 | goto out; | |
23ba4fd0 | 2929 | |
ff865885 | 2930 | req = obj->last_read_req; |
23ba4fd0 | 2931 | |
23ba4fd0 | 2932 | /* Do this after OLR check to make sure we make forward progress polling |
5ed0bdf2 | 2933 | * on this IOCTL with a timeout <=0 (like busy ioctl) |
23ba4fd0 | 2934 | */ |
5ed0bdf2 | 2935 | if (args->timeout_ns <= 0) { |
23ba4fd0 BW |
2936 | ret = -ETIME; |
2937 | goto out; | |
2938 | } | |
2939 | ||
2940 | drm_gem_object_unreference(&obj->base); | |
f69061be | 2941 | reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter); |
ff865885 | 2942 | i915_gem_request_reference(req); |
23ba4fd0 BW |
2943 | mutex_unlock(&dev->struct_mutex); |
2944 | ||
9c654818 JH |
2945 | ret = __i915_wait_request(req, reset_counter, true, &args->timeout_ns, |
2946 | file->driver_priv); | |
ff865885 JH |
2947 | mutex_lock(&dev->struct_mutex); |
2948 | i915_gem_request_unreference(req); | |
2949 | mutex_unlock(&dev->struct_mutex); | |
2950 | return ret; | |
23ba4fd0 BW |
2951 | |
2952 | out: | |
2953 | drm_gem_object_unreference(&obj->base); | |
2954 | mutex_unlock(&dev->struct_mutex); | |
2955 | return ret; | |
2956 | } | |
2957 | ||
5816d648 BW |
2958 | /** |
2959 | * i915_gem_object_sync - sync an object to a ring. | |
2960 | * | |
2961 | * @obj: object which may be in use on another ring. | |
2962 | * @to: ring we wish to use the object on. May be NULL. | |
2963 | * | |
2964 | * This code is meant to abstract object synchronization with the GPU. | |
2965 | * Calling with NULL implies synchronizing the object with the CPU | |
2966 | * rather than a particular GPU ring. | |
2967 | * | |
2968 | * Returns 0 if successful, else propagates up the lower layer error. | |
2969 | */ | |
2911a35b BW |
2970 | int |
2971 | i915_gem_object_sync(struct drm_i915_gem_object *obj, | |
a4872ba6 | 2972 | struct intel_engine_cs *to) |
2911a35b | 2973 | { |
a4872ba6 | 2974 | struct intel_engine_cs *from = obj->ring; |
2911a35b BW |
2975 | u32 seqno; |
2976 | int ret, idx; | |
2977 | ||
2978 | if (from == NULL || to == from) | |
2979 | return 0; | |
2980 | ||
5816d648 | 2981 | if (to == NULL || !i915_semaphore_is_enabled(obj->base.dev)) |
0201f1ec | 2982 | return i915_gem_object_wait_rendering(obj, false); |
2911a35b BW |
2983 | |
2984 | idx = intel_ring_sync_index(from, to); | |
2985 | ||
97b2a6a1 | 2986 | seqno = i915_gem_request_get_seqno(obj->last_read_req); |
ddd4dbc6 RV |
2987 | /* Optimization: Avoid semaphore sync when we are sure we already |
2988 | * waited for an object with higher seqno */ | |
ebc348b2 | 2989 | if (seqno <= from->semaphore.sync_seqno[idx]) |
2911a35b BW |
2990 | return 0; |
2991 | ||
b6660d59 | 2992 | ret = i915_gem_check_olr(obj->last_read_req); |
b4aca010 BW |
2993 | if (ret) |
2994 | return ret; | |
2911a35b | 2995 | |
74328ee5 | 2996 | trace_i915_gem_ring_sync_to(from, to, obj->last_read_req); |
ebc348b2 | 2997 | ret = to->semaphore.sync_to(to, from, seqno); |
e3a5a225 | 2998 | if (!ret) |
97b2a6a1 | 2999 | /* We use last_read_req because sync_to() |
7b01e260 MK |
3000 | * might have just caused seqno wrap under |
3001 | * the radar. | |
3002 | */ | |
97b2a6a1 JH |
3003 | from->semaphore.sync_seqno[idx] = |
3004 | i915_gem_request_get_seqno(obj->last_read_req); | |
2911a35b | 3005 | |
e3a5a225 | 3006 | return ret; |
2911a35b BW |
3007 | } |
3008 | ||
b5ffc9bc CW |
3009 | static void i915_gem_object_finish_gtt(struct drm_i915_gem_object *obj) |
3010 | { | |
3011 | u32 old_write_domain, old_read_domains; | |
3012 | ||
b5ffc9bc CW |
3013 | /* Force a pagefault for domain tracking on next user access */ |
3014 | i915_gem_release_mmap(obj); | |
3015 | ||
b97c3d9c KP |
3016 | if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0) |
3017 | return; | |
3018 | ||
97c809fd CW |
3019 | /* Wait for any direct GTT access to complete */ |
3020 | mb(); | |
3021 | ||
b5ffc9bc CW |
3022 | old_read_domains = obj->base.read_domains; |
3023 | old_write_domain = obj->base.write_domain; | |
3024 | ||
3025 | obj->base.read_domains &= ~I915_GEM_DOMAIN_GTT; | |
3026 | obj->base.write_domain &= ~I915_GEM_DOMAIN_GTT; | |
3027 | ||
3028 | trace_i915_gem_object_change_domain(obj, | |
3029 | old_read_domains, | |
3030 | old_write_domain); | |
3031 | } | |
3032 | ||
07fe0b12 | 3033 | int i915_vma_unbind(struct i915_vma *vma) |
673a394b | 3034 | { |
07fe0b12 | 3035 | struct drm_i915_gem_object *obj = vma->obj; |
3e31c6c0 | 3036 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
43e28f09 | 3037 | int ret; |
673a394b | 3038 | |
07fe0b12 | 3039 | if (list_empty(&vma->vma_link)) |
673a394b EA |
3040 | return 0; |
3041 | ||
0ff501cb DV |
3042 | if (!drm_mm_node_allocated(&vma->node)) { |
3043 | i915_gem_vma_destroy(vma); | |
0ff501cb DV |
3044 | return 0; |
3045 | } | |
433544bd | 3046 | |
d7f46fc4 | 3047 | if (vma->pin_count) |
31d8d651 | 3048 | return -EBUSY; |
673a394b | 3049 | |
c4670ad0 CW |
3050 | BUG_ON(obj->pages == NULL); |
3051 | ||
a8198eea | 3052 | ret = i915_gem_object_finish_gpu(obj); |
1488fc08 | 3053 | if (ret) |
a8198eea CW |
3054 | return ret; |
3055 | /* Continue on if we fail due to EIO, the GPU is hung so we | |
3056 | * should be safe and we need to cleanup or else we might | |
3057 | * cause memory corruption through use-after-free. | |
3058 | */ | |
3059 | ||
1d1ef21d CW |
3060 | /* Throw away the active reference before moving to the unbound list */ |
3061 | i915_gem_object_retire(obj); | |
3062 | ||
8b1bc9b4 DV |
3063 | if (i915_is_ggtt(vma->vm)) { |
3064 | i915_gem_object_finish_gtt(obj); | |
5323fd04 | 3065 | |
8b1bc9b4 DV |
3066 | /* release the fence reg _after_ flushing */ |
3067 | ret = i915_gem_object_put_fence(obj); | |
3068 | if (ret) | |
3069 | return ret; | |
3070 | } | |
96b47b65 | 3071 | |
07fe0b12 | 3072 | trace_i915_vma_unbind(vma); |
db53a302 | 3073 | |
6f65e29a BW |
3074 | vma->unbind_vma(vma); |
3075 | ||
64bf9303 | 3076 | list_del_init(&vma->mm_list); |
5cacaac7 | 3077 | if (i915_is_ggtt(vma->vm)) |
e6a84468 | 3078 | obj->map_and_fenceable = false; |
673a394b | 3079 | |
2f633156 BW |
3080 | drm_mm_remove_node(&vma->node); |
3081 | i915_gem_vma_destroy(vma); | |
3082 | ||
3083 | /* Since the unbound list is global, only move to that list if | |
b93dab6e | 3084 | * no more VMAs exist. */ |
9490edb5 AR |
3085 | if (list_empty(&obj->vma_list)) { |
3086 | i915_gem_gtt_finish_object(obj); | |
2f633156 | 3087 | list_move_tail(&obj->global_list, &dev_priv->mm.unbound_list); |
9490edb5 | 3088 | } |
673a394b | 3089 | |
70903c3b CW |
3090 | /* And finally now the object is completely decoupled from this vma, |
3091 | * we can drop its hold on the backing storage and allow it to be | |
3092 | * reaped by the shrinker. | |
3093 | */ | |
3094 | i915_gem_object_unpin_pages(obj); | |
3095 | ||
88241785 | 3096 | return 0; |
54cf91dc CW |
3097 | } |
3098 | ||
b2da9fe5 | 3099 | int i915_gpu_idle(struct drm_device *dev) |
4df2faf4 | 3100 | { |
3e31c6c0 | 3101 | struct drm_i915_private *dev_priv = dev->dev_private; |
a4872ba6 | 3102 | struct intel_engine_cs *ring; |
1ec14ad3 | 3103 | int ret, i; |
4df2faf4 | 3104 | |
4df2faf4 | 3105 | /* Flush everything onto the inactive list. */ |
b4519513 | 3106 | for_each_ring(ring, dev_priv, i) { |
ecdb5fd8 TD |
3107 | if (!i915.enable_execlists) { |
3108 | ret = i915_switch_context(ring, ring->default_context); | |
3109 | if (ret) | |
3110 | return ret; | |
3111 | } | |
b6c7488d | 3112 | |
3e960501 | 3113 | ret = intel_ring_idle(ring); |
1ec14ad3 CW |
3114 | if (ret) |
3115 | return ret; | |
3116 | } | |
4df2faf4 | 3117 | |
8a1a49f9 | 3118 | return 0; |
4df2faf4 DV |
3119 | } |
3120 | ||
9ce079e4 CW |
3121 | static void i965_write_fence_reg(struct drm_device *dev, int reg, |
3122 | struct drm_i915_gem_object *obj) | |
de151cf6 | 3123 | { |
3e31c6c0 | 3124 | struct drm_i915_private *dev_priv = dev->dev_private; |
56c844e5 ID |
3125 | int fence_reg; |
3126 | int fence_pitch_shift; | |
de151cf6 | 3127 | |
56c844e5 ID |
3128 | if (INTEL_INFO(dev)->gen >= 6) { |
3129 | fence_reg = FENCE_REG_SANDYBRIDGE_0; | |
3130 | fence_pitch_shift = SANDYBRIDGE_FENCE_PITCH_SHIFT; | |
3131 | } else { | |
3132 | fence_reg = FENCE_REG_965_0; | |
3133 | fence_pitch_shift = I965_FENCE_PITCH_SHIFT; | |
3134 | } | |
3135 | ||
d18b9619 CW |
3136 | fence_reg += reg * 8; |
3137 | ||
3138 | /* To w/a incoherency with non-atomic 64-bit register updates, | |
3139 | * we split the 64-bit update into two 32-bit writes. In order | |
3140 | * for a partial fence not to be evaluated between writes, we | |
3141 | * precede the update with write to turn off the fence register, | |
3142 | * and only enable the fence as the last step. | |
3143 | * | |
3144 | * For extra levels of paranoia, we make sure each step lands | |
3145 | * before applying the next step. | |
3146 | */ | |
3147 | I915_WRITE(fence_reg, 0); | |
3148 | POSTING_READ(fence_reg); | |
3149 | ||
9ce079e4 | 3150 | if (obj) { |
f343c5f6 | 3151 | u32 size = i915_gem_obj_ggtt_size(obj); |
d18b9619 | 3152 | uint64_t val; |
de151cf6 | 3153 | |
f343c5f6 | 3154 | val = (uint64_t)((i915_gem_obj_ggtt_offset(obj) + size - 4096) & |
9ce079e4 | 3155 | 0xfffff000) << 32; |
f343c5f6 | 3156 | val |= i915_gem_obj_ggtt_offset(obj) & 0xfffff000; |
56c844e5 | 3157 | val |= (uint64_t)((obj->stride / 128) - 1) << fence_pitch_shift; |
9ce079e4 CW |
3158 | if (obj->tiling_mode == I915_TILING_Y) |
3159 | val |= 1 << I965_FENCE_TILING_Y_SHIFT; | |
3160 | val |= I965_FENCE_REG_VALID; | |
c6642782 | 3161 | |
d18b9619 CW |
3162 | I915_WRITE(fence_reg + 4, val >> 32); |
3163 | POSTING_READ(fence_reg + 4); | |
3164 | ||
3165 | I915_WRITE(fence_reg + 0, val); | |
3166 | POSTING_READ(fence_reg); | |
3167 | } else { | |
3168 | I915_WRITE(fence_reg + 4, 0); | |
3169 | POSTING_READ(fence_reg + 4); | |
3170 | } | |
de151cf6 JB |
3171 | } |
3172 | ||
9ce079e4 CW |
3173 | static void i915_write_fence_reg(struct drm_device *dev, int reg, |
3174 | struct drm_i915_gem_object *obj) | |
de151cf6 | 3175 | { |
3e31c6c0 | 3176 | struct drm_i915_private *dev_priv = dev->dev_private; |
9ce079e4 | 3177 | u32 val; |
de151cf6 | 3178 | |
9ce079e4 | 3179 | if (obj) { |
f343c5f6 | 3180 | u32 size = i915_gem_obj_ggtt_size(obj); |
9ce079e4 CW |
3181 | int pitch_val; |
3182 | int tile_width; | |
c6642782 | 3183 | |
f343c5f6 | 3184 | WARN((i915_gem_obj_ggtt_offset(obj) & ~I915_FENCE_START_MASK) || |
9ce079e4 | 3185 | (size & -size) != size || |
f343c5f6 BW |
3186 | (i915_gem_obj_ggtt_offset(obj) & (size - 1)), |
3187 | "object 0x%08lx [fenceable? %d] not 1M or pot-size (0x%08x) aligned\n", | |
3188 | i915_gem_obj_ggtt_offset(obj), obj->map_and_fenceable, size); | |
c6642782 | 3189 | |
9ce079e4 CW |
3190 | if (obj->tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev)) |
3191 | tile_width = 128; | |
3192 | else | |
3193 | tile_width = 512; | |
3194 | ||
3195 | /* Note: pitch better be a power of two tile widths */ | |
3196 | pitch_val = obj->stride / tile_width; | |
3197 | pitch_val = ffs(pitch_val) - 1; | |
3198 | ||
f343c5f6 | 3199 | val = i915_gem_obj_ggtt_offset(obj); |
9ce079e4 CW |
3200 | if (obj->tiling_mode == I915_TILING_Y) |
3201 | val |= 1 << I830_FENCE_TILING_Y_SHIFT; | |
3202 | val |= I915_FENCE_SIZE_BITS(size); | |
3203 | val |= pitch_val << I830_FENCE_PITCH_SHIFT; | |
3204 | val |= I830_FENCE_REG_VALID; | |
3205 | } else | |
3206 | val = 0; | |
3207 | ||
3208 | if (reg < 8) | |
3209 | reg = FENCE_REG_830_0 + reg * 4; | |
3210 | else | |
3211 | reg = FENCE_REG_945_8 + (reg - 8) * 4; | |
3212 | ||
3213 | I915_WRITE(reg, val); | |
3214 | POSTING_READ(reg); | |
de151cf6 JB |
3215 | } |
3216 | ||
9ce079e4 CW |
3217 | static void i830_write_fence_reg(struct drm_device *dev, int reg, |
3218 | struct drm_i915_gem_object *obj) | |
de151cf6 | 3219 | { |
3e31c6c0 | 3220 | struct drm_i915_private *dev_priv = dev->dev_private; |
de151cf6 | 3221 | uint32_t val; |
de151cf6 | 3222 | |
9ce079e4 | 3223 | if (obj) { |
f343c5f6 | 3224 | u32 size = i915_gem_obj_ggtt_size(obj); |
9ce079e4 | 3225 | uint32_t pitch_val; |
de151cf6 | 3226 | |
f343c5f6 | 3227 | WARN((i915_gem_obj_ggtt_offset(obj) & ~I830_FENCE_START_MASK) || |
9ce079e4 | 3228 | (size & -size) != size || |
f343c5f6 BW |
3229 | (i915_gem_obj_ggtt_offset(obj) & (size - 1)), |
3230 | "object 0x%08lx not 512K or pot-size 0x%08x aligned\n", | |
3231 | i915_gem_obj_ggtt_offset(obj), size); | |
e76a16de | 3232 | |
9ce079e4 CW |
3233 | pitch_val = obj->stride / 128; |
3234 | pitch_val = ffs(pitch_val) - 1; | |
de151cf6 | 3235 | |
f343c5f6 | 3236 | val = i915_gem_obj_ggtt_offset(obj); |
9ce079e4 CW |
3237 | if (obj->tiling_mode == I915_TILING_Y) |
3238 | val |= 1 << I830_FENCE_TILING_Y_SHIFT; | |
3239 | val |= I830_FENCE_SIZE_BITS(size); | |
3240 | val |= pitch_val << I830_FENCE_PITCH_SHIFT; | |
3241 | val |= I830_FENCE_REG_VALID; | |
3242 | } else | |
3243 | val = 0; | |
c6642782 | 3244 | |
9ce079e4 CW |
3245 | I915_WRITE(FENCE_REG_830_0 + reg * 4, val); |
3246 | POSTING_READ(FENCE_REG_830_0 + reg * 4); | |
3247 | } | |
3248 | ||
d0a57789 CW |
3249 | inline static bool i915_gem_object_needs_mb(struct drm_i915_gem_object *obj) |
3250 | { | |
3251 | return obj && obj->base.read_domains & I915_GEM_DOMAIN_GTT; | |
3252 | } | |
3253 | ||
9ce079e4 CW |
3254 | static void i915_gem_write_fence(struct drm_device *dev, int reg, |
3255 | struct drm_i915_gem_object *obj) | |
3256 | { | |
d0a57789 CW |
3257 | struct drm_i915_private *dev_priv = dev->dev_private; |
3258 | ||
3259 | /* Ensure that all CPU reads are completed before installing a fence | |
3260 | * and all writes before removing the fence. | |
3261 | */ | |
3262 | if (i915_gem_object_needs_mb(dev_priv->fence_regs[reg].obj)) | |
3263 | mb(); | |
3264 | ||
94a335db DV |
3265 | WARN(obj && (!obj->stride || !obj->tiling_mode), |
3266 | "bogus fence setup with stride: 0x%x, tiling mode: %i\n", | |
3267 | obj->stride, obj->tiling_mode); | |
3268 | ||
9ce079e4 | 3269 | switch (INTEL_INFO(dev)->gen) { |
01209dd5 | 3270 | case 9: |
5ab31333 | 3271 | case 8: |
9ce079e4 | 3272 | case 7: |
56c844e5 | 3273 | case 6: |
9ce079e4 CW |
3274 | case 5: |
3275 | case 4: i965_write_fence_reg(dev, reg, obj); break; | |
3276 | case 3: i915_write_fence_reg(dev, reg, obj); break; | |
3277 | case 2: i830_write_fence_reg(dev, reg, obj); break; | |
7dbf9d6e | 3278 | default: BUG(); |
9ce079e4 | 3279 | } |
d0a57789 CW |
3280 | |
3281 | /* And similarly be paranoid that no direct access to this region | |
3282 | * is reordered to before the fence is installed. | |
3283 | */ | |
3284 | if (i915_gem_object_needs_mb(obj)) | |
3285 | mb(); | |
de151cf6 JB |
3286 | } |
3287 | ||
61050808 CW |
3288 | static inline int fence_number(struct drm_i915_private *dev_priv, |
3289 | struct drm_i915_fence_reg *fence) | |
3290 | { | |
3291 | return fence - dev_priv->fence_regs; | |
3292 | } | |
3293 | ||
3294 | static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj, | |
3295 | struct drm_i915_fence_reg *fence, | |
3296 | bool enable) | |
3297 | { | |
2dc8aae0 | 3298 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
46a0b638 CW |
3299 | int reg = fence_number(dev_priv, fence); |
3300 | ||
3301 | i915_gem_write_fence(obj->base.dev, reg, enable ? obj : NULL); | |
61050808 CW |
3302 | |
3303 | if (enable) { | |
46a0b638 | 3304 | obj->fence_reg = reg; |
61050808 CW |
3305 | fence->obj = obj; |
3306 | list_move_tail(&fence->lru_list, &dev_priv->mm.fence_list); | |
3307 | } else { | |
3308 | obj->fence_reg = I915_FENCE_REG_NONE; | |
3309 | fence->obj = NULL; | |
3310 | list_del_init(&fence->lru_list); | |
3311 | } | |
94a335db | 3312 | obj->fence_dirty = false; |
61050808 CW |
3313 | } |
3314 | ||
d9e86c0e | 3315 | static int |
d0a57789 | 3316 | i915_gem_object_wait_fence(struct drm_i915_gem_object *obj) |
d9e86c0e | 3317 | { |
97b2a6a1 | 3318 | if (obj->last_fenced_req) { |
a4b3a571 | 3319 | int ret = i915_wait_request(obj->last_fenced_req); |
18991845 CW |
3320 | if (ret) |
3321 | return ret; | |
d9e86c0e | 3322 | |
97b2a6a1 | 3323 | i915_gem_request_assign(&obj->last_fenced_req, NULL); |
d9e86c0e CW |
3324 | } |
3325 | ||
3326 | return 0; | |
3327 | } | |
3328 | ||
3329 | int | |
3330 | i915_gem_object_put_fence(struct drm_i915_gem_object *obj) | |
3331 | { | |
61050808 | 3332 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
f9c513e9 | 3333 | struct drm_i915_fence_reg *fence; |
d9e86c0e CW |
3334 | int ret; |
3335 | ||
d0a57789 | 3336 | ret = i915_gem_object_wait_fence(obj); |
d9e86c0e CW |
3337 | if (ret) |
3338 | return ret; | |
3339 | ||
61050808 CW |
3340 | if (obj->fence_reg == I915_FENCE_REG_NONE) |
3341 | return 0; | |
d9e86c0e | 3342 | |
f9c513e9 CW |
3343 | fence = &dev_priv->fence_regs[obj->fence_reg]; |
3344 | ||
aff10b30 DV |
3345 | if (WARN_ON(fence->pin_count)) |
3346 | return -EBUSY; | |
3347 | ||
61050808 | 3348 | i915_gem_object_fence_lost(obj); |
f9c513e9 | 3349 | i915_gem_object_update_fence(obj, fence, false); |
d9e86c0e CW |
3350 | |
3351 | return 0; | |
3352 | } | |
3353 | ||
3354 | static struct drm_i915_fence_reg * | |
a360bb1a | 3355 | i915_find_fence_reg(struct drm_device *dev) |
ae3db24a | 3356 | { |
ae3db24a | 3357 | struct drm_i915_private *dev_priv = dev->dev_private; |
8fe301ad | 3358 | struct drm_i915_fence_reg *reg, *avail; |
d9e86c0e | 3359 | int i; |
ae3db24a DV |
3360 | |
3361 | /* First try to find a free reg */ | |
d9e86c0e | 3362 | avail = NULL; |
ae3db24a DV |
3363 | for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) { |
3364 | reg = &dev_priv->fence_regs[i]; | |
3365 | if (!reg->obj) | |
d9e86c0e | 3366 | return reg; |
ae3db24a | 3367 | |
1690e1eb | 3368 | if (!reg->pin_count) |
d9e86c0e | 3369 | avail = reg; |
ae3db24a DV |
3370 | } |
3371 | ||
d9e86c0e | 3372 | if (avail == NULL) |
5dce5b93 | 3373 | goto deadlock; |
ae3db24a DV |
3374 | |
3375 | /* None available, try to steal one or wait for a user to finish */ | |
d9e86c0e | 3376 | list_for_each_entry(reg, &dev_priv->mm.fence_list, lru_list) { |
1690e1eb | 3377 | if (reg->pin_count) |
ae3db24a DV |
3378 | continue; |
3379 | ||
8fe301ad | 3380 | return reg; |
ae3db24a DV |
3381 | } |
3382 | ||
5dce5b93 CW |
3383 | deadlock: |
3384 | /* Wait for completion of pending flips which consume fences */ | |
3385 | if (intel_has_pending_fb_unpin(dev)) | |
3386 | return ERR_PTR(-EAGAIN); | |
3387 | ||
3388 | return ERR_PTR(-EDEADLK); | |
ae3db24a DV |
3389 | } |
3390 | ||
de151cf6 | 3391 | /** |
9a5a53b3 | 3392 | * i915_gem_object_get_fence - set up fencing for an object |
de151cf6 JB |
3393 | * @obj: object to map through a fence reg |
3394 | * | |
3395 | * When mapping objects through the GTT, userspace wants to be able to write | |
3396 | * to them without having to worry about swizzling if the object is tiled. | |
de151cf6 JB |
3397 | * This function walks the fence regs looking for a free one for @obj, |
3398 | * stealing one if it can't find any. | |
3399 | * | |
3400 | * It then sets up the reg based on the object's properties: address, pitch | |
3401 | * and tiling format. | |
9a5a53b3 CW |
3402 | * |
3403 | * For an untiled surface, this removes any existing fence. | |
de151cf6 | 3404 | */ |
8c4b8c3f | 3405 | int |
06d98131 | 3406 | i915_gem_object_get_fence(struct drm_i915_gem_object *obj) |
de151cf6 | 3407 | { |
05394f39 | 3408 | struct drm_device *dev = obj->base.dev; |
79e53945 | 3409 | struct drm_i915_private *dev_priv = dev->dev_private; |
14415745 | 3410 | bool enable = obj->tiling_mode != I915_TILING_NONE; |
d9e86c0e | 3411 | struct drm_i915_fence_reg *reg; |
ae3db24a | 3412 | int ret; |
de151cf6 | 3413 | |
14415745 CW |
3414 | /* Have we updated the tiling parameters upon the object and so |
3415 | * will need to serialise the write to the associated fence register? | |
3416 | */ | |
5d82e3e6 | 3417 | if (obj->fence_dirty) { |
d0a57789 | 3418 | ret = i915_gem_object_wait_fence(obj); |
14415745 CW |
3419 | if (ret) |
3420 | return ret; | |
3421 | } | |
9a5a53b3 | 3422 | |
d9e86c0e | 3423 | /* Just update our place in the LRU if our fence is getting reused. */ |
05394f39 CW |
3424 | if (obj->fence_reg != I915_FENCE_REG_NONE) { |
3425 | reg = &dev_priv->fence_regs[obj->fence_reg]; | |
5d82e3e6 | 3426 | if (!obj->fence_dirty) { |
14415745 CW |
3427 | list_move_tail(®->lru_list, |
3428 | &dev_priv->mm.fence_list); | |
3429 | return 0; | |
3430 | } | |
3431 | } else if (enable) { | |
e6a84468 CW |
3432 | if (WARN_ON(!obj->map_and_fenceable)) |
3433 | return -EINVAL; | |
3434 | ||
14415745 | 3435 | reg = i915_find_fence_reg(dev); |
5dce5b93 CW |
3436 | if (IS_ERR(reg)) |
3437 | return PTR_ERR(reg); | |
d9e86c0e | 3438 | |
14415745 CW |
3439 | if (reg->obj) { |
3440 | struct drm_i915_gem_object *old = reg->obj; | |
3441 | ||
d0a57789 | 3442 | ret = i915_gem_object_wait_fence(old); |
29c5a587 CW |
3443 | if (ret) |
3444 | return ret; | |
3445 | ||
14415745 | 3446 | i915_gem_object_fence_lost(old); |
29c5a587 | 3447 | } |
14415745 | 3448 | } else |
a09ba7fa | 3449 | return 0; |
a09ba7fa | 3450 | |
14415745 | 3451 | i915_gem_object_update_fence(obj, reg, enable); |
14415745 | 3452 | |
9ce079e4 | 3453 | return 0; |
de151cf6 JB |
3454 | } |
3455 | ||
4144f9b5 | 3456 | static bool i915_gem_valid_gtt_space(struct i915_vma *vma, |
42d6ab48 CW |
3457 | unsigned long cache_level) |
3458 | { | |
4144f9b5 | 3459 | struct drm_mm_node *gtt_space = &vma->node; |
42d6ab48 CW |
3460 | struct drm_mm_node *other; |
3461 | ||
4144f9b5 CW |
3462 | /* |
3463 | * On some machines we have to be careful when putting differing types | |
3464 | * of snoopable memory together to avoid the prefetcher crossing memory | |
3465 | * domains and dying. During vm initialisation, we decide whether or not | |
3466 | * these constraints apply and set the drm_mm.color_adjust | |
3467 | * appropriately. | |
42d6ab48 | 3468 | */ |
4144f9b5 | 3469 | if (vma->vm->mm.color_adjust == NULL) |
42d6ab48 CW |
3470 | return true; |
3471 | ||
c6cfb325 | 3472 | if (!drm_mm_node_allocated(gtt_space)) |
42d6ab48 CW |
3473 | return true; |
3474 | ||
3475 | if (list_empty(>t_space->node_list)) | |
3476 | return true; | |
3477 | ||
3478 | other = list_entry(gtt_space->node_list.prev, struct drm_mm_node, node_list); | |
3479 | if (other->allocated && !other->hole_follows && other->color != cache_level) | |
3480 | return false; | |
3481 | ||
3482 | other = list_entry(gtt_space->node_list.next, struct drm_mm_node, node_list); | |
3483 | if (other->allocated && !gtt_space->hole_follows && other->color != cache_level) | |
3484 | return false; | |
3485 | ||
3486 | return true; | |
3487 | } | |
3488 | ||
673a394b EA |
3489 | /** |
3490 | * Finds free space in the GTT aperture and binds the object there. | |
3491 | */ | |
262de145 | 3492 | static struct i915_vma * |
07fe0b12 BW |
3493 | i915_gem_object_bind_to_vm(struct drm_i915_gem_object *obj, |
3494 | struct i915_address_space *vm, | |
3495 | unsigned alignment, | |
d23db88c | 3496 | uint64_t flags) |
673a394b | 3497 | { |
05394f39 | 3498 | struct drm_device *dev = obj->base.dev; |
3e31c6c0 | 3499 | struct drm_i915_private *dev_priv = dev->dev_private; |
5e783301 | 3500 | u32 size, fence_size, fence_alignment, unfenced_alignment; |
d23db88c CW |
3501 | unsigned long start = |
3502 | flags & PIN_OFFSET_BIAS ? flags & PIN_OFFSET_MASK : 0; | |
3503 | unsigned long end = | |
1ec9e26d | 3504 | flags & PIN_MAPPABLE ? dev_priv->gtt.mappable_end : vm->total; |
2f633156 | 3505 | struct i915_vma *vma; |
07f73f69 | 3506 | int ret; |
673a394b | 3507 | |
e28f8711 CW |
3508 | fence_size = i915_gem_get_gtt_size(dev, |
3509 | obj->base.size, | |
3510 | obj->tiling_mode); | |
3511 | fence_alignment = i915_gem_get_gtt_alignment(dev, | |
3512 | obj->base.size, | |
d865110c | 3513 | obj->tiling_mode, true); |
e28f8711 | 3514 | unfenced_alignment = |
d865110c | 3515 | i915_gem_get_gtt_alignment(dev, |
1ec9e26d DV |
3516 | obj->base.size, |
3517 | obj->tiling_mode, false); | |
a00b10c3 | 3518 | |
673a394b | 3519 | if (alignment == 0) |
1ec9e26d | 3520 | alignment = flags & PIN_MAPPABLE ? fence_alignment : |
5e783301 | 3521 | unfenced_alignment; |
1ec9e26d | 3522 | if (flags & PIN_MAPPABLE && alignment & (fence_alignment - 1)) { |
bd9b6a4e | 3523 | DRM_DEBUG("Invalid object alignment requested %u\n", alignment); |
262de145 | 3524 | return ERR_PTR(-EINVAL); |
673a394b EA |
3525 | } |
3526 | ||
1ec9e26d | 3527 | size = flags & PIN_MAPPABLE ? fence_size : obj->base.size; |
a00b10c3 | 3528 | |
654fc607 CW |
3529 | /* If the object is bigger than the entire aperture, reject it early |
3530 | * before evicting everything in a vain attempt to find space. | |
3531 | */ | |
d23db88c CW |
3532 | if (obj->base.size > end) { |
3533 | DRM_DEBUG("Attempting to bind an object larger than the aperture: object=%zd > %s aperture=%lu\n", | |
a36689cb | 3534 | obj->base.size, |
1ec9e26d | 3535 | flags & PIN_MAPPABLE ? "mappable" : "total", |
d23db88c | 3536 | end); |
262de145 | 3537 | return ERR_PTR(-E2BIG); |
654fc607 CW |
3538 | } |
3539 | ||
37e680a1 | 3540 | ret = i915_gem_object_get_pages(obj); |
6c085a72 | 3541 | if (ret) |
262de145 | 3542 | return ERR_PTR(ret); |
6c085a72 | 3543 | |
fbdda6fb CW |
3544 | i915_gem_object_pin_pages(obj); |
3545 | ||
accfef2e | 3546 | vma = i915_gem_obj_lookup_or_create_vma(obj, vm); |
262de145 | 3547 | if (IS_ERR(vma)) |
bc6bc15b | 3548 | goto err_unpin; |
2f633156 | 3549 | |
0a9ae0d7 | 3550 | search_free: |
07fe0b12 | 3551 | ret = drm_mm_insert_node_in_range_generic(&vm->mm, &vma->node, |
0a9ae0d7 | 3552 | size, alignment, |
d23db88c CW |
3553 | obj->cache_level, |
3554 | start, end, | |
62347f9e LK |
3555 | DRM_MM_SEARCH_DEFAULT, |
3556 | DRM_MM_CREATE_DEFAULT); | |
dc9dd7a2 | 3557 | if (ret) { |
f6cd1f15 | 3558 | ret = i915_gem_evict_something(dev, vm, size, alignment, |
d23db88c CW |
3559 | obj->cache_level, |
3560 | start, end, | |
3561 | flags); | |
dc9dd7a2 CW |
3562 | if (ret == 0) |
3563 | goto search_free; | |
9731129c | 3564 | |
bc6bc15b | 3565 | goto err_free_vma; |
673a394b | 3566 | } |
4144f9b5 | 3567 | if (WARN_ON(!i915_gem_valid_gtt_space(vma, obj->cache_level))) { |
2f633156 | 3568 | ret = -EINVAL; |
bc6bc15b | 3569 | goto err_remove_node; |
673a394b EA |
3570 | } |
3571 | ||
74163907 | 3572 | ret = i915_gem_gtt_prepare_object(obj); |
2f633156 | 3573 | if (ret) |
bc6bc15b | 3574 | goto err_remove_node; |
673a394b | 3575 | |
35c20a60 | 3576 | list_move_tail(&obj->global_list, &dev_priv->mm.bound_list); |
ca191b13 | 3577 | list_add_tail(&vma->mm_list, &vm->inactive_list); |
bf1a1092 | 3578 | |
1ec9e26d | 3579 | trace_i915_vma_bind(vma, flags); |
8ea99c92 | 3580 | vma->bind_vma(vma, obj->cache_level, |
c826c449 | 3581 | flags & PIN_GLOBAL ? GLOBAL_BIND : 0); |
8ea99c92 | 3582 | |
262de145 | 3583 | return vma; |
2f633156 | 3584 | |
bc6bc15b | 3585 | err_remove_node: |
6286ef9b | 3586 | drm_mm_remove_node(&vma->node); |
bc6bc15b | 3587 | err_free_vma: |
2f633156 | 3588 | i915_gem_vma_destroy(vma); |
262de145 | 3589 | vma = ERR_PTR(ret); |
bc6bc15b | 3590 | err_unpin: |
2f633156 | 3591 | i915_gem_object_unpin_pages(obj); |
262de145 | 3592 | return vma; |
673a394b EA |
3593 | } |
3594 | ||
000433b6 | 3595 | bool |
2c22569b CW |
3596 | i915_gem_clflush_object(struct drm_i915_gem_object *obj, |
3597 | bool force) | |
673a394b | 3598 | { |
673a394b EA |
3599 | /* If we don't have a page list set up, then we're not pinned |
3600 | * to GPU, and we can ignore the cache flush because it'll happen | |
3601 | * again at bind time. | |
3602 | */ | |
05394f39 | 3603 | if (obj->pages == NULL) |
000433b6 | 3604 | return false; |
673a394b | 3605 | |
769ce464 ID |
3606 | /* |
3607 | * Stolen memory is always coherent with the GPU as it is explicitly | |
3608 | * marked as wc by the system, or the system is cache-coherent. | |
3609 | */ | |
6a2c4232 | 3610 | if (obj->stolen || obj->phys_handle) |
000433b6 | 3611 | return false; |
769ce464 | 3612 | |
9c23f7fc CW |
3613 | /* If the GPU is snooping the contents of the CPU cache, |
3614 | * we do not need to manually clear the CPU cache lines. However, | |
3615 | * the caches are only snooped when the render cache is | |
3616 | * flushed/invalidated. As we always have to emit invalidations | |
3617 | * and flushes when moving into and out of the RENDER domain, correct | |
3618 | * snooping behaviour occurs naturally as the result of our domain | |
3619 | * tracking. | |
3620 | */ | |
2c22569b | 3621 | if (!force && cpu_cache_is_coherent(obj->base.dev, obj->cache_level)) |
000433b6 | 3622 | return false; |
9c23f7fc | 3623 | |
1c5d22f7 | 3624 | trace_i915_gem_object_clflush(obj); |
9da3da66 | 3625 | drm_clflush_sg(obj->pages); |
000433b6 CW |
3626 | |
3627 | return true; | |
e47c68e9 EA |
3628 | } |
3629 | ||
3630 | /** Flushes the GTT write domain for the object if it's dirty. */ | |
3631 | static void | |
05394f39 | 3632 | i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj) |
e47c68e9 | 3633 | { |
1c5d22f7 CW |
3634 | uint32_t old_write_domain; |
3635 | ||
05394f39 | 3636 | if (obj->base.write_domain != I915_GEM_DOMAIN_GTT) |
e47c68e9 EA |
3637 | return; |
3638 | ||
63256ec5 | 3639 | /* No actual flushing is required for the GTT write domain. Writes |
e47c68e9 EA |
3640 | * to it immediately go to main memory as far as we know, so there's |
3641 | * no chipset flush. It also doesn't land in render cache. | |
63256ec5 CW |
3642 | * |
3643 | * However, we do have to enforce the order so that all writes through | |
3644 | * the GTT land before any writes to the device, such as updates to | |
3645 | * the GATT itself. | |
e47c68e9 | 3646 | */ |
63256ec5 CW |
3647 | wmb(); |
3648 | ||
05394f39 CW |
3649 | old_write_domain = obj->base.write_domain; |
3650 | obj->base.write_domain = 0; | |
1c5d22f7 | 3651 | |
f99d7069 DV |
3652 | intel_fb_obj_flush(obj, false); |
3653 | ||
1c5d22f7 | 3654 | trace_i915_gem_object_change_domain(obj, |
05394f39 | 3655 | obj->base.read_domains, |
1c5d22f7 | 3656 | old_write_domain); |
e47c68e9 EA |
3657 | } |
3658 | ||
3659 | /** Flushes the CPU write domain for the object if it's dirty. */ | |
3660 | static void | |
2c22569b CW |
3661 | i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj, |
3662 | bool force) | |
e47c68e9 | 3663 | { |
1c5d22f7 | 3664 | uint32_t old_write_domain; |
e47c68e9 | 3665 | |
05394f39 | 3666 | if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) |
e47c68e9 EA |
3667 | return; |
3668 | ||
000433b6 CW |
3669 | if (i915_gem_clflush_object(obj, force)) |
3670 | i915_gem_chipset_flush(obj->base.dev); | |
3671 | ||
05394f39 CW |
3672 | old_write_domain = obj->base.write_domain; |
3673 | obj->base.write_domain = 0; | |
1c5d22f7 | 3674 | |
f99d7069 DV |
3675 | intel_fb_obj_flush(obj, false); |
3676 | ||
1c5d22f7 | 3677 | trace_i915_gem_object_change_domain(obj, |
05394f39 | 3678 | obj->base.read_domains, |
1c5d22f7 | 3679 | old_write_domain); |
e47c68e9 EA |
3680 | } |
3681 | ||
2ef7eeaa EA |
3682 | /** |
3683 | * Moves a single object to the GTT read, and possibly write domain. | |
3684 | * | |
3685 | * This function returns when the move is complete, including waiting on | |
3686 | * flushes to occur. | |
3687 | */ | |
79e53945 | 3688 | int |
2021746e | 3689 | i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write) |
2ef7eeaa | 3690 | { |
3e31c6c0 | 3691 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
dc8cd1e7 | 3692 | struct i915_vma *vma = i915_gem_obj_to_ggtt(obj); |
1c5d22f7 | 3693 | uint32_t old_write_domain, old_read_domains; |
e47c68e9 | 3694 | int ret; |
2ef7eeaa | 3695 | |
02354392 | 3696 | /* Not valid to be called on unbound objects. */ |
dc8cd1e7 | 3697 | if (vma == NULL) |
02354392 EA |
3698 | return -EINVAL; |
3699 | ||
8d7e3de1 CW |
3700 | if (obj->base.write_domain == I915_GEM_DOMAIN_GTT) |
3701 | return 0; | |
3702 | ||
0201f1ec | 3703 | ret = i915_gem_object_wait_rendering(obj, !write); |
88241785 CW |
3704 | if (ret) |
3705 | return ret; | |
3706 | ||
c8725f3d | 3707 | i915_gem_object_retire(obj); |
2c22569b | 3708 | i915_gem_object_flush_cpu_write_domain(obj, false); |
1c5d22f7 | 3709 | |
d0a57789 CW |
3710 | /* Serialise direct access to this object with the barriers for |
3711 | * coherent writes from the GPU, by effectively invalidating the | |
3712 | * GTT domain upon first access. | |
3713 | */ | |
3714 | if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0) | |
3715 | mb(); | |
3716 | ||
05394f39 CW |
3717 | old_write_domain = obj->base.write_domain; |
3718 | old_read_domains = obj->base.read_domains; | |
1c5d22f7 | 3719 | |
e47c68e9 EA |
3720 | /* It should now be out of any other write domains, and we can update |
3721 | * the domain values for our changes. | |
3722 | */ | |
05394f39 CW |
3723 | BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) != 0); |
3724 | obj->base.read_domains |= I915_GEM_DOMAIN_GTT; | |
e47c68e9 | 3725 | if (write) { |
05394f39 CW |
3726 | obj->base.read_domains = I915_GEM_DOMAIN_GTT; |
3727 | obj->base.write_domain = I915_GEM_DOMAIN_GTT; | |
3728 | obj->dirty = 1; | |
2ef7eeaa EA |
3729 | } |
3730 | ||
f99d7069 DV |
3731 | if (write) |
3732 | intel_fb_obj_invalidate(obj, NULL); | |
3733 | ||
1c5d22f7 CW |
3734 | trace_i915_gem_object_change_domain(obj, |
3735 | old_read_domains, | |
3736 | old_write_domain); | |
3737 | ||
8325a09d | 3738 | /* And bump the LRU for this access */ |
dc8cd1e7 CW |
3739 | if (i915_gem_object_is_inactive(obj)) |
3740 | list_move_tail(&vma->mm_list, | |
3741 | &dev_priv->gtt.base.inactive_list); | |
8325a09d | 3742 | |
e47c68e9 EA |
3743 | return 0; |
3744 | } | |
3745 | ||
e4ffd173 CW |
3746 | int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj, |
3747 | enum i915_cache_level cache_level) | |
3748 | { | |
7bddb01f | 3749 | struct drm_device *dev = obj->base.dev; |
df6f783a | 3750 | struct i915_vma *vma, *next; |
e4ffd173 CW |
3751 | int ret; |
3752 | ||
3753 | if (obj->cache_level == cache_level) | |
3754 | return 0; | |
3755 | ||
d7f46fc4 | 3756 | if (i915_gem_obj_is_pinned(obj)) { |
e4ffd173 CW |
3757 | DRM_DEBUG("can not change the cache level of pinned objects\n"); |
3758 | return -EBUSY; | |
3759 | } | |
3760 | ||
df6f783a | 3761 | list_for_each_entry_safe(vma, next, &obj->vma_list, vma_link) { |
4144f9b5 | 3762 | if (!i915_gem_valid_gtt_space(vma, cache_level)) { |
07fe0b12 | 3763 | ret = i915_vma_unbind(vma); |
3089c6f2 BW |
3764 | if (ret) |
3765 | return ret; | |
3089c6f2 | 3766 | } |
42d6ab48 CW |
3767 | } |
3768 | ||
3089c6f2 | 3769 | if (i915_gem_obj_bound_any(obj)) { |
e4ffd173 CW |
3770 | ret = i915_gem_object_finish_gpu(obj); |
3771 | if (ret) | |
3772 | return ret; | |
3773 | ||
3774 | i915_gem_object_finish_gtt(obj); | |
3775 | ||
3776 | /* Before SandyBridge, you could not use tiling or fence | |
3777 | * registers with snooped memory, so relinquish any fences | |
3778 | * currently pointing to our region in the aperture. | |
3779 | */ | |
42d6ab48 | 3780 | if (INTEL_INFO(dev)->gen < 6) { |
e4ffd173 CW |
3781 | ret = i915_gem_object_put_fence(obj); |
3782 | if (ret) | |
3783 | return ret; | |
3784 | } | |
3785 | ||
6f65e29a | 3786 | list_for_each_entry(vma, &obj->vma_list, vma_link) |
8ea99c92 DV |
3787 | if (drm_mm_node_allocated(&vma->node)) |
3788 | vma->bind_vma(vma, cache_level, | |
aff43766 | 3789 | vma->bound & GLOBAL_BIND); |
e4ffd173 CW |
3790 | } |
3791 | ||
2c22569b CW |
3792 | list_for_each_entry(vma, &obj->vma_list, vma_link) |
3793 | vma->node.color = cache_level; | |
3794 | obj->cache_level = cache_level; | |
3795 | ||
3796 | if (cpu_write_needs_clflush(obj)) { | |
e4ffd173 CW |
3797 | u32 old_read_domains, old_write_domain; |
3798 | ||
3799 | /* If we're coming from LLC cached, then we haven't | |
3800 | * actually been tracking whether the data is in the | |
3801 | * CPU cache or not, since we only allow one bit set | |
3802 | * in obj->write_domain and have been skipping the clflushes. | |
3803 | * Just set it to the CPU cache for now. | |
3804 | */ | |
c8725f3d | 3805 | i915_gem_object_retire(obj); |
e4ffd173 | 3806 | WARN_ON(obj->base.write_domain & ~I915_GEM_DOMAIN_CPU); |
e4ffd173 CW |
3807 | |
3808 | old_read_domains = obj->base.read_domains; | |
3809 | old_write_domain = obj->base.write_domain; | |
3810 | ||
3811 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; | |
3812 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; | |
3813 | ||
3814 | trace_i915_gem_object_change_domain(obj, | |
3815 | old_read_domains, | |
3816 | old_write_domain); | |
3817 | } | |
3818 | ||
e4ffd173 CW |
3819 | return 0; |
3820 | } | |
3821 | ||
199adf40 BW |
3822 | int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data, |
3823 | struct drm_file *file) | |
e6994aee | 3824 | { |
199adf40 | 3825 | struct drm_i915_gem_caching *args = data; |
e6994aee CW |
3826 | struct drm_i915_gem_object *obj; |
3827 | int ret; | |
3828 | ||
3829 | ret = i915_mutex_lock_interruptible(dev); | |
3830 | if (ret) | |
3831 | return ret; | |
3832 | ||
3833 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); | |
3834 | if (&obj->base == NULL) { | |
3835 | ret = -ENOENT; | |
3836 | goto unlock; | |
3837 | } | |
3838 | ||
651d794f CW |
3839 | switch (obj->cache_level) { |
3840 | case I915_CACHE_LLC: | |
3841 | case I915_CACHE_L3_LLC: | |
3842 | args->caching = I915_CACHING_CACHED; | |
3843 | break; | |
3844 | ||
4257d3ba CW |
3845 | case I915_CACHE_WT: |
3846 | args->caching = I915_CACHING_DISPLAY; | |
3847 | break; | |
3848 | ||
651d794f CW |
3849 | default: |
3850 | args->caching = I915_CACHING_NONE; | |
3851 | break; | |
3852 | } | |
e6994aee CW |
3853 | |
3854 | drm_gem_object_unreference(&obj->base); | |
3855 | unlock: | |
3856 | mutex_unlock(&dev->struct_mutex); | |
3857 | return ret; | |
3858 | } | |
3859 | ||
199adf40 BW |
3860 | int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data, |
3861 | struct drm_file *file) | |
e6994aee | 3862 | { |
199adf40 | 3863 | struct drm_i915_gem_caching *args = data; |
e6994aee CW |
3864 | struct drm_i915_gem_object *obj; |
3865 | enum i915_cache_level level; | |
3866 | int ret; | |
3867 | ||
199adf40 BW |
3868 | switch (args->caching) { |
3869 | case I915_CACHING_NONE: | |
e6994aee CW |
3870 | level = I915_CACHE_NONE; |
3871 | break; | |
199adf40 | 3872 | case I915_CACHING_CACHED: |
e6994aee CW |
3873 | level = I915_CACHE_LLC; |
3874 | break; | |
4257d3ba CW |
3875 | case I915_CACHING_DISPLAY: |
3876 | level = HAS_WT(dev) ? I915_CACHE_WT : I915_CACHE_NONE; | |
3877 | break; | |
e6994aee CW |
3878 | default: |
3879 | return -EINVAL; | |
3880 | } | |
3881 | ||
3bc2913e BW |
3882 | ret = i915_mutex_lock_interruptible(dev); |
3883 | if (ret) | |
3884 | return ret; | |
3885 | ||
e6994aee CW |
3886 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
3887 | if (&obj->base == NULL) { | |
3888 | ret = -ENOENT; | |
3889 | goto unlock; | |
3890 | } | |
3891 | ||
3892 | ret = i915_gem_object_set_cache_level(obj, level); | |
3893 | ||
3894 | drm_gem_object_unreference(&obj->base); | |
3895 | unlock: | |
3896 | mutex_unlock(&dev->struct_mutex); | |
3897 | return ret; | |
3898 | } | |
3899 | ||
cc98b413 CW |
3900 | static bool is_pin_display(struct drm_i915_gem_object *obj) |
3901 | { | |
19656430 OM |
3902 | struct i915_vma *vma; |
3903 | ||
19656430 OM |
3904 | vma = i915_gem_obj_to_ggtt(obj); |
3905 | if (!vma) | |
3906 | return false; | |
3907 | ||
4feb7659 | 3908 | /* There are 2 sources that pin objects: |
cc98b413 CW |
3909 | * 1. The display engine (scanouts, sprites, cursors); |
3910 | * 2. Reservations for execbuffer; | |
cc98b413 CW |
3911 | * |
3912 | * We can ignore reservations as we hold the struct_mutex and | |
4feb7659 | 3913 | * are only called outside of the reservation path. |
cc98b413 | 3914 | */ |
4feb7659 | 3915 | return vma->pin_count; |
cc98b413 CW |
3916 | } |
3917 | ||
b9241ea3 | 3918 | /* |
2da3b9b9 CW |
3919 | * Prepare buffer for display plane (scanout, cursors, etc). |
3920 | * Can be called from an uninterruptible phase (modesetting) and allows | |
3921 | * any flushes to be pipelined (for pageflips). | |
b9241ea3 ZW |
3922 | */ |
3923 | int | |
2da3b9b9 CW |
3924 | i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj, |
3925 | u32 alignment, | |
a4872ba6 | 3926 | struct intel_engine_cs *pipelined) |
b9241ea3 | 3927 | { |
2da3b9b9 | 3928 | u32 old_read_domains, old_write_domain; |
19656430 | 3929 | bool was_pin_display; |
b9241ea3 ZW |
3930 | int ret; |
3931 | ||
0be73284 | 3932 | if (pipelined != obj->ring) { |
2911a35b BW |
3933 | ret = i915_gem_object_sync(obj, pipelined); |
3934 | if (ret) | |
b9241ea3 ZW |
3935 | return ret; |
3936 | } | |
3937 | ||
cc98b413 CW |
3938 | /* Mark the pin_display early so that we account for the |
3939 | * display coherency whilst setting up the cache domains. | |
3940 | */ | |
19656430 | 3941 | was_pin_display = obj->pin_display; |
cc98b413 CW |
3942 | obj->pin_display = true; |
3943 | ||
a7ef0640 EA |
3944 | /* The display engine is not coherent with the LLC cache on gen6. As |
3945 | * a result, we make sure that the pinning that is about to occur is | |
3946 | * done with uncached PTEs. This is lowest common denominator for all | |
3947 | * chipsets. | |
3948 | * | |
3949 | * However for gen6+, we could do better by using the GFDT bit instead | |
3950 | * of uncaching, which would allow us to flush all the LLC-cached data | |
3951 | * with that bit in the PTE to main memory with just one PIPE_CONTROL. | |
3952 | */ | |
651d794f CW |
3953 | ret = i915_gem_object_set_cache_level(obj, |
3954 | HAS_WT(obj->base.dev) ? I915_CACHE_WT : I915_CACHE_NONE); | |
a7ef0640 | 3955 | if (ret) |
cc98b413 | 3956 | goto err_unpin_display; |
a7ef0640 | 3957 | |
2da3b9b9 CW |
3958 | /* As the user may map the buffer once pinned in the display plane |
3959 | * (e.g. libkms for the bootup splash), we have to ensure that we | |
3960 | * always use map_and_fenceable for all scanout buffers. | |
3961 | */ | |
1ec9e26d | 3962 | ret = i915_gem_obj_ggtt_pin(obj, alignment, PIN_MAPPABLE); |
2da3b9b9 | 3963 | if (ret) |
cc98b413 | 3964 | goto err_unpin_display; |
2da3b9b9 | 3965 | |
2c22569b | 3966 | i915_gem_object_flush_cpu_write_domain(obj, true); |
b118c1e3 | 3967 | |
2da3b9b9 | 3968 | old_write_domain = obj->base.write_domain; |
05394f39 | 3969 | old_read_domains = obj->base.read_domains; |
2da3b9b9 CW |
3970 | |
3971 | /* It should now be out of any other write domains, and we can update | |
3972 | * the domain values for our changes. | |
3973 | */ | |
e5f1d962 | 3974 | obj->base.write_domain = 0; |
05394f39 | 3975 | obj->base.read_domains |= I915_GEM_DOMAIN_GTT; |
b9241ea3 ZW |
3976 | |
3977 | trace_i915_gem_object_change_domain(obj, | |
3978 | old_read_domains, | |
2da3b9b9 | 3979 | old_write_domain); |
b9241ea3 ZW |
3980 | |
3981 | return 0; | |
cc98b413 CW |
3982 | |
3983 | err_unpin_display: | |
19656430 OM |
3984 | WARN_ON(was_pin_display != is_pin_display(obj)); |
3985 | obj->pin_display = was_pin_display; | |
cc98b413 CW |
3986 | return ret; |
3987 | } | |
3988 | ||
3989 | void | |
3990 | i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object *obj) | |
3991 | { | |
d7f46fc4 | 3992 | i915_gem_object_ggtt_unpin(obj); |
cc98b413 | 3993 | obj->pin_display = is_pin_display(obj); |
b9241ea3 ZW |
3994 | } |
3995 | ||
85345517 | 3996 | int |
a8198eea | 3997 | i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj) |
85345517 | 3998 | { |
88241785 CW |
3999 | int ret; |
4000 | ||
a8198eea | 4001 | if ((obj->base.read_domains & I915_GEM_GPU_DOMAINS) == 0) |
85345517 CW |
4002 | return 0; |
4003 | ||
0201f1ec | 4004 | ret = i915_gem_object_wait_rendering(obj, false); |
c501ae7f CW |
4005 | if (ret) |
4006 | return ret; | |
4007 | ||
a8198eea CW |
4008 | /* Ensure that we invalidate the GPU's caches and TLBs. */ |
4009 | obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS; | |
c501ae7f | 4010 | return 0; |
85345517 CW |
4011 | } |
4012 | ||
e47c68e9 EA |
4013 | /** |
4014 | * Moves a single object to the CPU read, and possibly write domain. | |
4015 | * | |
4016 | * This function returns when the move is complete, including waiting on | |
4017 | * flushes to occur. | |
4018 | */ | |
dabdfe02 | 4019 | int |
919926ae | 4020 | i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write) |
e47c68e9 | 4021 | { |
1c5d22f7 | 4022 | uint32_t old_write_domain, old_read_domains; |
e47c68e9 EA |
4023 | int ret; |
4024 | ||
8d7e3de1 CW |
4025 | if (obj->base.write_domain == I915_GEM_DOMAIN_CPU) |
4026 | return 0; | |
4027 | ||
0201f1ec | 4028 | ret = i915_gem_object_wait_rendering(obj, !write); |
88241785 CW |
4029 | if (ret) |
4030 | return ret; | |
4031 | ||
c8725f3d | 4032 | i915_gem_object_retire(obj); |
e47c68e9 | 4033 | i915_gem_object_flush_gtt_write_domain(obj); |
2ef7eeaa | 4034 | |
05394f39 CW |
4035 | old_write_domain = obj->base.write_domain; |
4036 | old_read_domains = obj->base.read_domains; | |
1c5d22f7 | 4037 | |
e47c68e9 | 4038 | /* Flush the CPU cache if it's still invalid. */ |
05394f39 | 4039 | if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) { |
2c22569b | 4040 | i915_gem_clflush_object(obj, false); |
2ef7eeaa | 4041 | |
05394f39 | 4042 | obj->base.read_domains |= I915_GEM_DOMAIN_CPU; |
2ef7eeaa EA |
4043 | } |
4044 | ||
4045 | /* It should now be out of any other write domains, and we can update | |
4046 | * the domain values for our changes. | |
4047 | */ | |
05394f39 | 4048 | BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) != 0); |
e47c68e9 EA |
4049 | |
4050 | /* If we're writing through the CPU, then the GPU read domains will | |
4051 | * need to be invalidated at next use. | |
4052 | */ | |
4053 | if (write) { | |
05394f39 CW |
4054 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; |
4055 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; | |
e47c68e9 | 4056 | } |
2ef7eeaa | 4057 | |
f99d7069 DV |
4058 | if (write) |
4059 | intel_fb_obj_invalidate(obj, NULL); | |
4060 | ||
1c5d22f7 CW |
4061 | trace_i915_gem_object_change_domain(obj, |
4062 | old_read_domains, | |
4063 | old_write_domain); | |
4064 | ||
2ef7eeaa EA |
4065 | return 0; |
4066 | } | |
4067 | ||
673a394b EA |
4068 | /* Throttle our rendering by waiting until the ring has completed our requests |
4069 | * emitted over 20 msec ago. | |
4070 | * | |
b962442e EA |
4071 | * Note that if we were to use the current jiffies each time around the loop, |
4072 | * we wouldn't escape the function with any frames outstanding if the time to | |
4073 | * render a frame was over 20ms. | |
4074 | * | |
673a394b EA |
4075 | * This should get us reasonable parallelism between CPU and GPU but also |
4076 | * relatively low latency when blocking on a particular request to finish. | |
4077 | */ | |
40a5f0de | 4078 | static int |
f787a5f5 | 4079 | i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file) |
40a5f0de | 4080 | { |
f787a5f5 CW |
4081 | struct drm_i915_private *dev_priv = dev->dev_private; |
4082 | struct drm_i915_file_private *file_priv = file->driver_priv; | |
b962442e | 4083 | unsigned long recent_enough = jiffies - msecs_to_jiffies(20); |
54fb2411 | 4084 | struct drm_i915_gem_request *request, *target = NULL; |
f69061be | 4085 | unsigned reset_counter; |
f787a5f5 | 4086 | int ret; |
93533c29 | 4087 | |
308887aa DV |
4088 | ret = i915_gem_wait_for_error(&dev_priv->gpu_error); |
4089 | if (ret) | |
4090 | return ret; | |
4091 | ||
4092 | ret = i915_gem_check_wedge(&dev_priv->gpu_error, false); | |
4093 | if (ret) | |
4094 | return ret; | |
e110e8d6 | 4095 | |
1c25595f | 4096 | spin_lock(&file_priv->mm.lock); |
f787a5f5 | 4097 | list_for_each_entry(request, &file_priv->mm.request_list, client_list) { |
b962442e EA |
4098 | if (time_after_eq(request->emitted_jiffies, recent_enough)) |
4099 | break; | |
40a5f0de | 4100 | |
54fb2411 | 4101 | target = request; |
b962442e | 4102 | } |
f69061be | 4103 | reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter); |
ff865885 JH |
4104 | if (target) |
4105 | i915_gem_request_reference(target); | |
1c25595f | 4106 | spin_unlock(&file_priv->mm.lock); |
40a5f0de | 4107 | |
54fb2411 | 4108 | if (target == NULL) |
f787a5f5 | 4109 | return 0; |
2bc43b5c | 4110 | |
9c654818 | 4111 | ret = __i915_wait_request(target, reset_counter, true, NULL, NULL); |
f787a5f5 CW |
4112 | if (ret == 0) |
4113 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, 0); | |
40a5f0de | 4114 | |
ff865885 JH |
4115 | mutex_lock(&dev->struct_mutex); |
4116 | i915_gem_request_unreference(target); | |
4117 | mutex_unlock(&dev->struct_mutex); | |
4118 | ||
40a5f0de EA |
4119 | return ret; |
4120 | } | |
4121 | ||
d23db88c CW |
4122 | static bool |
4123 | i915_vma_misplaced(struct i915_vma *vma, uint32_t alignment, uint64_t flags) | |
4124 | { | |
4125 | struct drm_i915_gem_object *obj = vma->obj; | |
4126 | ||
4127 | if (alignment && | |
4128 | vma->node.start & (alignment - 1)) | |
4129 | return true; | |
4130 | ||
4131 | if (flags & PIN_MAPPABLE && !obj->map_and_fenceable) | |
4132 | return true; | |
4133 | ||
4134 | if (flags & PIN_OFFSET_BIAS && | |
4135 | vma->node.start < (flags & PIN_OFFSET_MASK)) | |
4136 | return true; | |
4137 | ||
4138 | return false; | |
4139 | } | |
4140 | ||
673a394b | 4141 | int |
05394f39 | 4142 | i915_gem_object_pin(struct drm_i915_gem_object *obj, |
c37e2204 | 4143 | struct i915_address_space *vm, |
05394f39 | 4144 | uint32_t alignment, |
d23db88c | 4145 | uint64_t flags) |
673a394b | 4146 | { |
6e7186af | 4147 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
07fe0b12 | 4148 | struct i915_vma *vma; |
ef79e17c | 4149 | unsigned bound; |
673a394b EA |
4150 | int ret; |
4151 | ||
6e7186af BW |
4152 | if (WARN_ON(vm == &dev_priv->mm.aliasing_ppgtt->base)) |
4153 | return -ENODEV; | |
4154 | ||
bf3d149b | 4155 | if (WARN_ON(flags & (PIN_GLOBAL | PIN_MAPPABLE) && !i915_is_ggtt(vm))) |
1ec9e26d | 4156 | return -EINVAL; |
07fe0b12 | 4157 | |
c826c449 CW |
4158 | if (WARN_ON((flags & (PIN_MAPPABLE | PIN_GLOBAL)) == PIN_MAPPABLE)) |
4159 | return -EINVAL; | |
4160 | ||
07fe0b12 | 4161 | vma = i915_gem_obj_to_vma(obj, vm); |
07fe0b12 | 4162 | if (vma) { |
d7f46fc4 BW |
4163 | if (WARN_ON(vma->pin_count == DRM_I915_GEM_OBJECT_MAX_PIN_COUNT)) |
4164 | return -EBUSY; | |
4165 | ||
d23db88c | 4166 | if (i915_vma_misplaced(vma, alignment, flags)) { |
d7f46fc4 | 4167 | WARN(vma->pin_count, |
ae7d49d8 | 4168 | "bo is already pinned with incorrect alignment:" |
f343c5f6 | 4169 | " offset=%lx, req.alignment=%x, req.map_and_fenceable=%d," |
75e9e915 | 4170 | " obj->map_and_fenceable=%d\n", |
07fe0b12 | 4171 | i915_gem_obj_offset(obj, vm), alignment, |
d23db88c | 4172 | !!(flags & PIN_MAPPABLE), |
05394f39 | 4173 | obj->map_and_fenceable); |
07fe0b12 | 4174 | ret = i915_vma_unbind(vma); |
ac0c6b5a CW |
4175 | if (ret) |
4176 | return ret; | |
8ea99c92 DV |
4177 | |
4178 | vma = NULL; | |
ac0c6b5a CW |
4179 | } |
4180 | } | |
4181 | ||
ef79e17c | 4182 | bound = vma ? vma->bound : 0; |
8ea99c92 | 4183 | if (vma == NULL || !drm_mm_node_allocated(&vma->node)) { |
262de145 DV |
4184 | vma = i915_gem_object_bind_to_vm(obj, vm, alignment, flags); |
4185 | if (IS_ERR(vma)) | |
4186 | return PTR_ERR(vma); | |
22c344e9 | 4187 | } |
76446cac | 4188 | |
aff43766 | 4189 | if (flags & PIN_GLOBAL && !(vma->bound & GLOBAL_BIND)) |
8ea99c92 | 4190 | vma->bind_vma(vma, obj->cache_level, GLOBAL_BIND); |
74898d7e | 4191 | |
ef79e17c CW |
4192 | if ((bound ^ vma->bound) & GLOBAL_BIND) { |
4193 | bool mappable, fenceable; | |
4194 | u32 fence_size, fence_alignment; | |
4195 | ||
4196 | fence_size = i915_gem_get_gtt_size(obj->base.dev, | |
4197 | obj->base.size, | |
4198 | obj->tiling_mode); | |
4199 | fence_alignment = i915_gem_get_gtt_alignment(obj->base.dev, | |
4200 | obj->base.size, | |
4201 | obj->tiling_mode, | |
4202 | true); | |
4203 | ||
4204 | fenceable = (vma->node.size == fence_size && | |
4205 | (vma->node.start & (fence_alignment - 1)) == 0); | |
4206 | ||
4207 | mappable = (vma->node.start + obj->base.size <= | |
4208 | dev_priv->gtt.mappable_end); | |
4209 | ||
4210 | obj->map_and_fenceable = mappable && fenceable; | |
4211 | } | |
4212 | ||
4213 | WARN_ON(flags & PIN_MAPPABLE && !obj->map_and_fenceable); | |
4214 | ||
8ea99c92 | 4215 | vma->pin_count++; |
1ec9e26d DV |
4216 | if (flags & PIN_MAPPABLE) |
4217 | obj->pin_mappable |= true; | |
673a394b EA |
4218 | |
4219 | return 0; | |
4220 | } | |
4221 | ||
4222 | void | |
d7f46fc4 | 4223 | i915_gem_object_ggtt_unpin(struct drm_i915_gem_object *obj) |
673a394b | 4224 | { |
d7f46fc4 | 4225 | struct i915_vma *vma = i915_gem_obj_to_ggtt(obj); |
673a394b | 4226 | |
d7f46fc4 BW |
4227 | BUG_ON(!vma); |
4228 | BUG_ON(vma->pin_count == 0); | |
4229 | BUG_ON(!i915_gem_obj_ggtt_bound(obj)); | |
4230 | ||
4231 | if (--vma->pin_count == 0) | |
6299f992 | 4232 | obj->pin_mappable = false; |
673a394b EA |
4233 | } |
4234 | ||
d8ffa60b DV |
4235 | bool |
4236 | i915_gem_object_pin_fence(struct drm_i915_gem_object *obj) | |
4237 | { | |
4238 | if (obj->fence_reg != I915_FENCE_REG_NONE) { | |
4239 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; | |
4240 | struct i915_vma *ggtt_vma = i915_gem_obj_to_ggtt(obj); | |
4241 | ||
4242 | WARN_ON(!ggtt_vma || | |
4243 | dev_priv->fence_regs[obj->fence_reg].pin_count > | |
4244 | ggtt_vma->pin_count); | |
4245 | dev_priv->fence_regs[obj->fence_reg].pin_count++; | |
4246 | return true; | |
4247 | } else | |
4248 | return false; | |
4249 | } | |
4250 | ||
4251 | void | |
4252 | i915_gem_object_unpin_fence(struct drm_i915_gem_object *obj) | |
4253 | { | |
4254 | if (obj->fence_reg != I915_FENCE_REG_NONE) { | |
4255 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; | |
4256 | WARN_ON(dev_priv->fence_regs[obj->fence_reg].pin_count <= 0); | |
4257 | dev_priv->fence_regs[obj->fence_reg].pin_count--; | |
4258 | } | |
4259 | } | |
4260 | ||
673a394b EA |
4261 | int |
4262 | i915_gem_busy_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 4263 | struct drm_file *file) |
673a394b EA |
4264 | { |
4265 | struct drm_i915_gem_busy *args = data; | |
05394f39 | 4266 | struct drm_i915_gem_object *obj; |
30dbf0c0 CW |
4267 | int ret; |
4268 | ||
76c1dec1 | 4269 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 4270 | if (ret) |
76c1dec1 | 4271 | return ret; |
673a394b | 4272 | |
05394f39 | 4273 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 4274 | if (&obj->base == NULL) { |
1d7cfea1 CW |
4275 | ret = -ENOENT; |
4276 | goto unlock; | |
673a394b | 4277 | } |
d1b851fc | 4278 | |
0be555b6 CW |
4279 | /* Count all active objects as busy, even if they are currently not used |
4280 | * by the gpu. Users of this interface expect objects to eventually | |
4281 | * become non-busy without any further actions, therefore emit any | |
4282 | * necessary flushes here. | |
c4de0a5d | 4283 | */ |
30dfebf3 | 4284 | ret = i915_gem_object_flush_active(obj); |
0be555b6 | 4285 | |
30dfebf3 | 4286 | args->busy = obj->active; |
e9808edd CW |
4287 | if (obj->ring) { |
4288 | BUILD_BUG_ON(I915_NUM_RINGS > 16); | |
4289 | args->busy |= intel_ring_flag(obj->ring) << 16; | |
4290 | } | |
673a394b | 4291 | |
05394f39 | 4292 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 4293 | unlock: |
673a394b | 4294 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 4295 | return ret; |
673a394b EA |
4296 | } |
4297 | ||
4298 | int | |
4299 | i915_gem_throttle_ioctl(struct drm_device *dev, void *data, | |
4300 | struct drm_file *file_priv) | |
4301 | { | |
0206e353 | 4302 | return i915_gem_ring_throttle(dev, file_priv); |
673a394b EA |
4303 | } |
4304 | ||
3ef94daa CW |
4305 | int |
4306 | i915_gem_madvise_ioctl(struct drm_device *dev, void *data, | |
4307 | struct drm_file *file_priv) | |
4308 | { | |
656bfa3a | 4309 | struct drm_i915_private *dev_priv = dev->dev_private; |
3ef94daa | 4310 | struct drm_i915_gem_madvise *args = data; |
05394f39 | 4311 | struct drm_i915_gem_object *obj; |
76c1dec1 | 4312 | int ret; |
3ef94daa CW |
4313 | |
4314 | switch (args->madv) { | |
4315 | case I915_MADV_DONTNEED: | |
4316 | case I915_MADV_WILLNEED: | |
4317 | break; | |
4318 | default: | |
4319 | return -EINVAL; | |
4320 | } | |
4321 | ||
1d7cfea1 CW |
4322 | ret = i915_mutex_lock_interruptible(dev); |
4323 | if (ret) | |
4324 | return ret; | |
4325 | ||
05394f39 | 4326 | obj = to_intel_bo(drm_gem_object_lookup(dev, file_priv, args->handle)); |
c8725226 | 4327 | if (&obj->base == NULL) { |
1d7cfea1 CW |
4328 | ret = -ENOENT; |
4329 | goto unlock; | |
3ef94daa | 4330 | } |
3ef94daa | 4331 | |
d7f46fc4 | 4332 | if (i915_gem_obj_is_pinned(obj)) { |
1d7cfea1 CW |
4333 | ret = -EINVAL; |
4334 | goto out; | |
3ef94daa CW |
4335 | } |
4336 | ||
656bfa3a DV |
4337 | if (obj->pages && |
4338 | obj->tiling_mode != I915_TILING_NONE && | |
4339 | dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES) { | |
4340 | if (obj->madv == I915_MADV_WILLNEED) | |
4341 | i915_gem_object_unpin_pages(obj); | |
4342 | if (args->madv == I915_MADV_WILLNEED) | |
4343 | i915_gem_object_pin_pages(obj); | |
4344 | } | |
4345 | ||
05394f39 CW |
4346 | if (obj->madv != __I915_MADV_PURGED) |
4347 | obj->madv = args->madv; | |
3ef94daa | 4348 | |
6c085a72 CW |
4349 | /* if the object is no longer attached, discard its backing storage */ |
4350 | if (i915_gem_object_is_purgeable(obj) && obj->pages == NULL) | |
2d7ef395 CW |
4351 | i915_gem_object_truncate(obj); |
4352 | ||
05394f39 | 4353 | args->retained = obj->madv != __I915_MADV_PURGED; |
bb6baf76 | 4354 | |
1d7cfea1 | 4355 | out: |
05394f39 | 4356 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 4357 | unlock: |
3ef94daa | 4358 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 4359 | return ret; |
3ef94daa CW |
4360 | } |
4361 | ||
37e680a1 CW |
4362 | void i915_gem_object_init(struct drm_i915_gem_object *obj, |
4363 | const struct drm_i915_gem_object_ops *ops) | |
0327d6ba | 4364 | { |
35c20a60 | 4365 | INIT_LIST_HEAD(&obj->global_list); |
0327d6ba | 4366 | INIT_LIST_HEAD(&obj->ring_list); |
b25cb2f8 | 4367 | INIT_LIST_HEAD(&obj->obj_exec_link); |
2f633156 | 4368 | INIT_LIST_HEAD(&obj->vma_list); |
0327d6ba | 4369 | |
37e680a1 CW |
4370 | obj->ops = ops; |
4371 | ||
0327d6ba CW |
4372 | obj->fence_reg = I915_FENCE_REG_NONE; |
4373 | obj->madv = I915_MADV_WILLNEED; | |
0327d6ba CW |
4374 | |
4375 | i915_gem_info_add_obj(obj->base.dev->dev_private, obj->base.size); | |
4376 | } | |
4377 | ||
37e680a1 CW |
4378 | static const struct drm_i915_gem_object_ops i915_gem_object_ops = { |
4379 | .get_pages = i915_gem_object_get_pages_gtt, | |
4380 | .put_pages = i915_gem_object_put_pages_gtt, | |
4381 | }; | |
4382 | ||
05394f39 CW |
4383 | struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev, |
4384 | size_t size) | |
ac52bc56 | 4385 | { |
c397b908 | 4386 | struct drm_i915_gem_object *obj; |
5949eac4 | 4387 | struct address_space *mapping; |
1a240d4d | 4388 | gfp_t mask; |
ac52bc56 | 4389 | |
42dcedd4 | 4390 | obj = i915_gem_object_alloc(dev); |
c397b908 DV |
4391 | if (obj == NULL) |
4392 | return NULL; | |
673a394b | 4393 | |
c397b908 | 4394 | if (drm_gem_object_init(dev, &obj->base, size) != 0) { |
42dcedd4 | 4395 | i915_gem_object_free(obj); |
c397b908 DV |
4396 | return NULL; |
4397 | } | |
673a394b | 4398 | |
bed1ea95 CW |
4399 | mask = GFP_HIGHUSER | __GFP_RECLAIMABLE; |
4400 | if (IS_CRESTLINE(dev) || IS_BROADWATER(dev)) { | |
4401 | /* 965gm cannot relocate objects above 4GiB. */ | |
4402 | mask &= ~__GFP_HIGHMEM; | |
4403 | mask |= __GFP_DMA32; | |
4404 | } | |
4405 | ||
496ad9aa | 4406 | mapping = file_inode(obj->base.filp)->i_mapping; |
bed1ea95 | 4407 | mapping_set_gfp_mask(mapping, mask); |
5949eac4 | 4408 | |
37e680a1 | 4409 | i915_gem_object_init(obj, &i915_gem_object_ops); |
73aa808f | 4410 | |
c397b908 DV |
4411 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; |
4412 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; | |
673a394b | 4413 | |
3d29b842 ED |
4414 | if (HAS_LLC(dev)) { |
4415 | /* On some devices, we can have the GPU use the LLC (the CPU | |
a1871112 EA |
4416 | * cache) for about a 10% performance improvement |
4417 | * compared to uncached. Graphics requests other than | |
4418 | * display scanout are coherent with the CPU in | |
4419 | * accessing this cache. This means in this mode we | |
4420 | * don't need to clflush on the CPU side, and on the | |
4421 | * GPU side we only need to flush internal caches to | |
4422 | * get data visible to the CPU. | |
4423 | * | |
4424 | * However, we maintain the display planes as UC, and so | |
4425 | * need to rebind when first used as such. | |
4426 | */ | |
4427 | obj->cache_level = I915_CACHE_LLC; | |
4428 | } else | |
4429 | obj->cache_level = I915_CACHE_NONE; | |
4430 | ||
d861e338 DV |
4431 | trace_i915_gem_object_create(obj); |
4432 | ||
05394f39 | 4433 | return obj; |
c397b908 DV |
4434 | } |
4435 | ||
340fbd8c CW |
4436 | static bool discard_backing_storage(struct drm_i915_gem_object *obj) |
4437 | { | |
4438 | /* If we are the last user of the backing storage (be it shmemfs | |
4439 | * pages or stolen etc), we know that the pages are going to be | |
4440 | * immediately released. In this case, we can then skip copying | |
4441 | * back the contents from the GPU. | |
4442 | */ | |
4443 | ||
4444 | if (obj->madv != I915_MADV_WILLNEED) | |
4445 | return false; | |
4446 | ||
4447 | if (obj->base.filp == NULL) | |
4448 | return true; | |
4449 | ||
4450 | /* At first glance, this looks racy, but then again so would be | |
4451 | * userspace racing mmap against close. However, the first external | |
4452 | * reference to the filp can only be obtained through the | |
4453 | * i915_gem_mmap_ioctl() which safeguards us against the user | |
4454 | * acquiring such a reference whilst we are in the middle of | |
4455 | * freeing the object. | |
4456 | */ | |
4457 | return atomic_long_read(&obj->base.filp->f_count) == 1; | |
4458 | } | |
4459 | ||
1488fc08 | 4460 | void i915_gem_free_object(struct drm_gem_object *gem_obj) |
673a394b | 4461 | { |
1488fc08 | 4462 | struct drm_i915_gem_object *obj = to_intel_bo(gem_obj); |
05394f39 | 4463 | struct drm_device *dev = obj->base.dev; |
3e31c6c0 | 4464 | struct drm_i915_private *dev_priv = dev->dev_private; |
07fe0b12 | 4465 | struct i915_vma *vma, *next; |
673a394b | 4466 | |
f65c9168 PZ |
4467 | intel_runtime_pm_get(dev_priv); |
4468 | ||
26e12f89 CW |
4469 | trace_i915_gem_object_destroy(obj); |
4470 | ||
07fe0b12 | 4471 | list_for_each_entry_safe(vma, next, &obj->vma_list, vma_link) { |
d7f46fc4 BW |
4472 | int ret; |
4473 | ||
4474 | vma->pin_count = 0; | |
4475 | ret = i915_vma_unbind(vma); | |
07fe0b12 BW |
4476 | if (WARN_ON(ret == -ERESTARTSYS)) { |
4477 | bool was_interruptible; | |
1488fc08 | 4478 | |
07fe0b12 BW |
4479 | was_interruptible = dev_priv->mm.interruptible; |
4480 | dev_priv->mm.interruptible = false; | |
1488fc08 | 4481 | |
07fe0b12 | 4482 | WARN_ON(i915_vma_unbind(vma)); |
1488fc08 | 4483 | |
07fe0b12 BW |
4484 | dev_priv->mm.interruptible = was_interruptible; |
4485 | } | |
1488fc08 CW |
4486 | } |
4487 | ||
1d64ae71 BW |
4488 | /* Stolen objects don't hold a ref, but do hold pin count. Fix that up |
4489 | * before progressing. */ | |
4490 | if (obj->stolen) | |
4491 | i915_gem_object_unpin_pages(obj); | |
4492 | ||
a071fa00 DV |
4493 | WARN_ON(obj->frontbuffer_bits); |
4494 | ||
656bfa3a DV |
4495 | if (obj->pages && obj->madv == I915_MADV_WILLNEED && |
4496 | dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES && | |
4497 | obj->tiling_mode != I915_TILING_NONE) | |
4498 | i915_gem_object_unpin_pages(obj); | |
4499 | ||
401c29f6 BW |
4500 | if (WARN_ON(obj->pages_pin_count)) |
4501 | obj->pages_pin_count = 0; | |
340fbd8c | 4502 | if (discard_backing_storage(obj)) |
5537252b | 4503 | obj->madv = I915_MADV_DONTNEED; |
37e680a1 | 4504 | i915_gem_object_put_pages(obj); |
d8cb5086 | 4505 | i915_gem_object_free_mmap_offset(obj); |
de151cf6 | 4506 | |
9da3da66 CW |
4507 | BUG_ON(obj->pages); |
4508 | ||
2f745ad3 CW |
4509 | if (obj->base.import_attach) |
4510 | drm_prime_gem_destroy(&obj->base, NULL); | |
de151cf6 | 4511 | |
5cc9ed4b CW |
4512 | if (obj->ops->release) |
4513 | obj->ops->release(obj); | |
4514 | ||
05394f39 CW |
4515 | drm_gem_object_release(&obj->base); |
4516 | i915_gem_info_remove_obj(dev_priv, obj->base.size); | |
c397b908 | 4517 | |
05394f39 | 4518 | kfree(obj->bit_17); |
42dcedd4 | 4519 | i915_gem_object_free(obj); |
f65c9168 PZ |
4520 | |
4521 | intel_runtime_pm_put(dev_priv); | |
673a394b EA |
4522 | } |
4523 | ||
e656a6cb | 4524 | struct i915_vma *i915_gem_obj_to_vma(struct drm_i915_gem_object *obj, |
2f633156 | 4525 | struct i915_address_space *vm) |
e656a6cb DV |
4526 | { |
4527 | struct i915_vma *vma; | |
4528 | list_for_each_entry(vma, &obj->vma_list, vma_link) | |
4529 | if (vma->vm == vm) | |
4530 | return vma; | |
4531 | ||
4532 | return NULL; | |
4533 | } | |
4534 | ||
2f633156 BW |
4535 | void i915_gem_vma_destroy(struct i915_vma *vma) |
4536 | { | |
b9d06dd9 | 4537 | struct i915_address_space *vm = NULL; |
2f633156 | 4538 | WARN_ON(vma->node.allocated); |
aaa05667 CW |
4539 | |
4540 | /* Keep the vma as a placeholder in the execbuffer reservation lists */ | |
4541 | if (!list_empty(&vma->exec_list)) | |
4542 | return; | |
4543 | ||
b9d06dd9 | 4544 | vm = vma->vm; |
b9d06dd9 | 4545 | |
841cd773 DV |
4546 | if (!i915_is_ggtt(vm)) |
4547 | i915_ppgtt_put(i915_vm_to_ppgtt(vm)); | |
b9d06dd9 | 4548 | |
8b9c2b94 | 4549 | list_del(&vma->vma_link); |
b93dab6e | 4550 | |
2f633156 BW |
4551 | kfree(vma); |
4552 | } | |
4553 | ||
e3efda49 CW |
4554 | static void |
4555 | i915_gem_stop_ringbuffers(struct drm_device *dev) | |
4556 | { | |
4557 | struct drm_i915_private *dev_priv = dev->dev_private; | |
a4872ba6 | 4558 | struct intel_engine_cs *ring; |
e3efda49 CW |
4559 | int i; |
4560 | ||
4561 | for_each_ring(ring, dev_priv, i) | |
a83014d3 | 4562 | dev_priv->gt.stop_ring(ring); |
e3efda49 CW |
4563 | } |
4564 | ||
29105ccc | 4565 | int |
45c5f202 | 4566 | i915_gem_suspend(struct drm_device *dev) |
29105ccc | 4567 | { |
3e31c6c0 | 4568 | struct drm_i915_private *dev_priv = dev->dev_private; |
45c5f202 | 4569 | int ret = 0; |
28dfe52a | 4570 | |
45c5f202 | 4571 | mutex_lock(&dev->struct_mutex); |
b2da9fe5 | 4572 | ret = i915_gpu_idle(dev); |
f7403347 | 4573 | if (ret) |
45c5f202 | 4574 | goto err; |
f7403347 | 4575 | |
b2da9fe5 | 4576 | i915_gem_retire_requests(dev); |
673a394b | 4577 | |
29105ccc | 4578 | /* Under UMS, be paranoid and evict. */ |
a39d7efc | 4579 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) |
6c085a72 | 4580 | i915_gem_evict_everything(dev); |
29105ccc | 4581 | |
e3efda49 | 4582 | i915_gem_stop_ringbuffers(dev); |
45c5f202 CW |
4583 | mutex_unlock(&dev->struct_mutex); |
4584 | ||
4585 | del_timer_sync(&dev_priv->gpu_error.hangcheck_timer); | |
29105ccc | 4586 | cancel_delayed_work_sync(&dev_priv->mm.retire_work); |
274fa1c1 | 4587 | flush_delayed_work(&dev_priv->mm.idle_work); |
29105ccc | 4588 | |
bdcf120b CW |
4589 | /* Assert that we sucessfully flushed all the work and |
4590 | * reset the GPU back to its idle, low power state. | |
4591 | */ | |
4592 | WARN_ON(dev_priv->mm.busy); | |
4593 | ||
673a394b | 4594 | return 0; |
45c5f202 CW |
4595 | |
4596 | err: | |
4597 | mutex_unlock(&dev->struct_mutex); | |
4598 | return ret; | |
673a394b EA |
4599 | } |
4600 | ||
a4872ba6 | 4601 | int i915_gem_l3_remap(struct intel_engine_cs *ring, int slice) |
b9524a1e | 4602 | { |
c3787e2e | 4603 | struct drm_device *dev = ring->dev; |
3e31c6c0 | 4604 | struct drm_i915_private *dev_priv = dev->dev_private; |
35a85ac6 BW |
4605 | u32 reg_base = GEN7_L3LOG_BASE + (slice * 0x200); |
4606 | u32 *remap_info = dev_priv->l3_parity.remap_info[slice]; | |
c3787e2e | 4607 | int i, ret; |
b9524a1e | 4608 | |
040d2baa | 4609 | if (!HAS_L3_DPF(dev) || !remap_info) |
c3787e2e | 4610 | return 0; |
b9524a1e | 4611 | |
c3787e2e BW |
4612 | ret = intel_ring_begin(ring, GEN7_L3LOG_SIZE / 4 * 3); |
4613 | if (ret) | |
4614 | return ret; | |
b9524a1e | 4615 | |
c3787e2e BW |
4616 | /* |
4617 | * Note: We do not worry about the concurrent register cacheline hang | |
4618 | * here because no other code should access these registers other than | |
4619 | * at initialization time. | |
4620 | */ | |
b9524a1e | 4621 | for (i = 0; i < GEN7_L3LOG_SIZE; i += 4) { |
c3787e2e BW |
4622 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); |
4623 | intel_ring_emit(ring, reg_base + i); | |
4624 | intel_ring_emit(ring, remap_info[i/4]); | |
b9524a1e BW |
4625 | } |
4626 | ||
c3787e2e | 4627 | intel_ring_advance(ring); |
b9524a1e | 4628 | |
c3787e2e | 4629 | return ret; |
b9524a1e BW |
4630 | } |
4631 | ||
f691e2f4 DV |
4632 | void i915_gem_init_swizzling(struct drm_device *dev) |
4633 | { | |
3e31c6c0 | 4634 | struct drm_i915_private *dev_priv = dev->dev_private; |
f691e2f4 | 4635 | |
11782b02 | 4636 | if (INTEL_INFO(dev)->gen < 5 || |
f691e2f4 DV |
4637 | dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE) |
4638 | return; | |
4639 | ||
4640 | I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) | | |
4641 | DISP_TILE_SURFACE_SWIZZLING); | |
4642 | ||
11782b02 DV |
4643 | if (IS_GEN5(dev)) |
4644 | return; | |
4645 | ||
f691e2f4 DV |
4646 | I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_SWZCTL); |
4647 | if (IS_GEN6(dev)) | |
6b26c86d | 4648 | I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB)); |
8782e26c | 4649 | else if (IS_GEN7(dev)) |
6b26c86d | 4650 | I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB)); |
31a5336e BW |
4651 | else if (IS_GEN8(dev)) |
4652 | I915_WRITE(GAMTARBMODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_BDW)); | |
8782e26c BW |
4653 | else |
4654 | BUG(); | |
f691e2f4 | 4655 | } |
e21af88d | 4656 | |
67b1b571 CW |
4657 | static bool |
4658 | intel_enable_blt(struct drm_device *dev) | |
4659 | { | |
4660 | if (!HAS_BLT(dev)) | |
4661 | return false; | |
4662 | ||
4663 | /* The blitter was dysfunctional on early prototypes */ | |
4664 | if (IS_GEN6(dev) && dev->pdev->revision < 8) { | |
4665 | DRM_INFO("BLT not supported on this pre-production hardware;" | |
4666 | " graphics performance will be degraded.\n"); | |
4667 | return false; | |
4668 | } | |
4669 | ||
4670 | return true; | |
4671 | } | |
4672 | ||
81e7f200 VS |
4673 | static void init_unused_ring(struct drm_device *dev, u32 base) |
4674 | { | |
4675 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4676 | ||
4677 | I915_WRITE(RING_CTL(base), 0); | |
4678 | I915_WRITE(RING_HEAD(base), 0); | |
4679 | I915_WRITE(RING_TAIL(base), 0); | |
4680 | I915_WRITE(RING_START(base), 0); | |
4681 | } | |
4682 | ||
4683 | static void init_unused_rings(struct drm_device *dev) | |
4684 | { | |
4685 | if (IS_I830(dev)) { | |
4686 | init_unused_ring(dev, PRB1_BASE); | |
4687 | init_unused_ring(dev, SRB0_BASE); | |
4688 | init_unused_ring(dev, SRB1_BASE); | |
4689 | init_unused_ring(dev, SRB2_BASE); | |
4690 | init_unused_ring(dev, SRB3_BASE); | |
4691 | } else if (IS_GEN2(dev)) { | |
4692 | init_unused_ring(dev, SRB0_BASE); | |
4693 | init_unused_ring(dev, SRB1_BASE); | |
4694 | } else if (IS_GEN3(dev)) { | |
4695 | init_unused_ring(dev, PRB1_BASE); | |
4696 | init_unused_ring(dev, PRB2_BASE); | |
4697 | } | |
4698 | } | |
4699 | ||
a83014d3 | 4700 | int i915_gem_init_rings(struct drm_device *dev) |
8187a2b7 | 4701 | { |
4fc7c971 | 4702 | struct drm_i915_private *dev_priv = dev->dev_private; |
8187a2b7 | 4703 | int ret; |
68f95ba9 | 4704 | |
81e7f200 VS |
4705 | /* |
4706 | * At least 830 can leave some of the unused rings | |
4707 | * "active" (ie. head != tail) after resume which | |
4708 | * will prevent c3 entry. Makes sure all unused rings | |
4709 | * are totally idle. | |
4710 | */ | |
4711 | init_unused_rings(dev); | |
4712 | ||
5c1143bb | 4713 | ret = intel_init_render_ring_buffer(dev); |
68f95ba9 | 4714 | if (ret) |
b6913e4b | 4715 | return ret; |
68f95ba9 CW |
4716 | |
4717 | if (HAS_BSD(dev)) { | |
5c1143bb | 4718 | ret = intel_init_bsd_ring_buffer(dev); |
68f95ba9 CW |
4719 | if (ret) |
4720 | goto cleanup_render_ring; | |
d1b851fc | 4721 | } |
68f95ba9 | 4722 | |
67b1b571 | 4723 | if (intel_enable_blt(dev)) { |
549f7365 CW |
4724 | ret = intel_init_blt_ring_buffer(dev); |
4725 | if (ret) | |
4726 | goto cleanup_bsd_ring; | |
4727 | } | |
4728 | ||
9a8a2213 BW |
4729 | if (HAS_VEBOX(dev)) { |
4730 | ret = intel_init_vebox_ring_buffer(dev); | |
4731 | if (ret) | |
4732 | goto cleanup_blt_ring; | |
4733 | } | |
4734 | ||
845f74a7 ZY |
4735 | if (HAS_BSD2(dev)) { |
4736 | ret = intel_init_bsd2_ring_buffer(dev); | |
4737 | if (ret) | |
4738 | goto cleanup_vebox_ring; | |
4739 | } | |
9a8a2213 | 4740 | |
99433931 | 4741 | ret = i915_gem_set_seqno(dev, ((u32)~0 - 0x1000)); |
4fc7c971 | 4742 | if (ret) |
845f74a7 | 4743 | goto cleanup_bsd2_ring; |
4fc7c971 BW |
4744 | |
4745 | return 0; | |
4746 | ||
845f74a7 ZY |
4747 | cleanup_bsd2_ring: |
4748 | intel_cleanup_ring_buffer(&dev_priv->ring[VCS2]); | |
9a8a2213 BW |
4749 | cleanup_vebox_ring: |
4750 | intel_cleanup_ring_buffer(&dev_priv->ring[VECS]); | |
4fc7c971 BW |
4751 | cleanup_blt_ring: |
4752 | intel_cleanup_ring_buffer(&dev_priv->ring[BCS]); | |
4753 | cleanup_bsd_ring: | |
4754 | intel_cleanup_ring_buffer(&dev_priv->ring[VCS]); | |
4755 | cleanup_render_ring: | |
4756 | intel_cleanup_ring_buffer(&dev_priv->ring[RCS]); | |
4757 | ||
4758 | return ret; | |
4759 | } | |
4760 | ||
4761 | int | |
4762 | i915_gem_init_hw(struct drm_device *dev) | |
4763 | { | |
3e31c6c0 | 4764 | struct drm_i915_private *dev_priv = dev->dev_private; |
35a85ac6 | 4765 | int ret, i; |
4fc7c971 BW |
4766 | |
4767 | if (INTEL_INFO(dev)->gen < 6 && !intel_enable_gtt()) | |
4768 | return -EIO; | |
4769 | ||
59124506 | 4770 | if (dev_priv->ellc_size) |
05e21cc4 | 4771 | I915_WRITE(HSW_IDICR, I915_READ(HSW_IDICR) | IDIHASHMSK(0xf)); |
4fc7c971 | 4772 | |
0bf21347 VS |
4773 | if (IS_HASWELL(dev)) |
4774 | I915_WRITE(MI_PREDICATE_RESULT_2, IS_HSW_GT3(dev) ? | |
4775 | LOWER_SLICE_ENABLED : LOWER_SLICE_DISABLED); | |
9435373e | 4776 | |
88a2b2a3 | 4777 | if (HAS_PCH_NOP(dev)) { |
6ba844b0 DV |
4778 | if (IS_IVYBRIDGE(dev)) { |
4779 | u32 temp = I915_READ(GEN7_MSG_CTL); | |
4780 | temp &= ~(WAIT_FOR_PCH_FLR_ACK | WAIT_FOR_PCH_RESET_ACK); | |
4781 | I915_WRITE(GEN7_MSG_CTL, temp); | |
4782 | } else if (INTEL_INFO(dev)->gen >= 7) { | |
4783 | u32 temp = I915_READ(HSW_NDE_RSTWRN_OPT); | |
4784 | temp &= ~RESET_PCH_HANDSHAKE_ENABLE; | |
4785 | I915_WRITE(HSW_NDE_RSTWRN_OPT, temp); | |
4786 | } | |
88a2b2a3 BW |
4787 | } |
4788 | ||
4fc7c971 BW |
4789 | i915_gem_init_swizzling(dev); |
4790 | ||
a83014d3 | 4791 | ret = dev_priv->gt.init_rings(dev); |
99433931 MK |
4792 | if (ret) |
4793 | return ret; | |
4794 | ||
c3787e2e BW |
4795 | for (i = 0; i < NUM_L3_SLICES(dev); i++) |
4796 | i915_gem_l3_remap(&dev_priv->ring[RCS], i); | |
4797 | ||
254f965c | 4798 | /* |
2fa48d8d BW |
4799 | * XXX: Contexts should only be initialized once. Doing a switch to the |
4800 | * default context switch however is something we'd like to do after | |
4801 | * reset or thaw (the latter may not actually be necessary for HW, but | |
4802 | * goes with our code better). Context switching requires rings (for | |
4803 | * the do_switch), but before enabling PPGTT. So don't move this. | |
254f965c | 4804 | */ |
2fa48d8d | 4805 | ret = i915_gem_context_enable(dev_priv); |
60990320 | 4806 | if (ret && ret != -EIO) { |
2fa48d8d | 4807 | DRM_ERROR("Context enable failed %d\n", ret); |
60990320 | 4808 | i915_gem_cleanup_ringbuffer(dev); |
82460d97 DV |
4809 | |
4810 | return ret; | |
4811 | } | |
4812 | ||
4813 | ret = i915_ppgtt_init_hw(dev); | |
4814 | if (ret && ret != -EIO) { | |
4815 | DRM_ERROR("PPGTT enable failed %d\n", ret); | |
4816 | i915_gem_cleanup_ringbuffer(dev); | |
b7c36d25 | 4817 | } |
e21af88d | 4818 | |
2fa48d8d | 4819 | return ret; |
8187a2b7 ZN |
4820 | } |
4821 | ||
1070a42b CW |
4822 | int i915_gem_init(struct drm_device *dev) |
4823 | { | |
4824 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1070a42b CW |
4825 | int ret; |
4826 | ||
127f1003 OM |
4827 | i915.enable_execlists = intel_sanitize_enable_execlists(dev, |
4828 | i915.enable_execlists); | |
4829 | ||
1070a42b | 4830 | mutex_lock(&dev->struct_mutex); |
d62b4892 JB |
4831 | |
4832 | if (IS_VALLEYVIEW(dev)) { | |
4833 | /* VLVA0 (potential hack), BIOS isn't actually waking us */ | |
981a5aea ID |
4834 | I915_WRITE(VLV_GTLC_WAKE_CTRL, VLV_GTLC_ALLOWWAKEREQ); |
4835 | if (wait_for((I915_READ(VLV_GTLC_PW_STATUS) & | |
4836 | VLV_GTLC_ALLOWWAKEACK), 10)) | |
d62b4892 JB |
4837 | DRM_DEBUG_DRIVER("allow wake ack timed out\n"); |
4838 | } | |
4839 | ||
a83014d3 OM |
4840 | if (!i915.enable_execlists) { |
4841 | dev_priv->gt.do_execbuf = i915_gem_ringbuffer_submission; | |
4842 | dev_priv->gt.init_rings = i915_gem_init_rings; | |
4843 | dev_priv->gt.cleanup_ring = intel_cleanup_ring_buffer; | |
4844 | dev_priv->gt.stop_ring = intel_stop_ring_buffer; | |
454afebd OM |
4845 | } else { |
4846 | dev_priv->gt.do_execbuf = intel_execlists_submission; | |
4847 | dev_priv->gt.init_rings = intel_logical_rings_init; | |
4848 | dev_priv->gt.cleanup_ring = intel_logical_ring_cleanup; | |
4849 | dev_priv->gt.stop_ring = intel_logical_ring_stop; | |
a83014d3 OM |
4850 | } |
4851 | ||
6c5566a8 DV |
4852 | ret = i915_gem_init_userptr(dev); |
4853 | if (ret) { | |
4854 | mutex_unlock(&dev->struct_mutex); | |
4855 | return ret; | |
4856 | } | |
4857 | ||
d7e5008f | 4858 | i915_gem_init_global_gtt(dev); |
d62b4892 | 4859 | |
2fa48d8d | 4860 | ret = i915_gem_context_init(dev); |
e3848694 MK |
4861 | if (ret) { |
4862 | mutex_unlock(&dev->struct_mutex); | |
2fa48d8d | 4863 | return ret; |
e3848694 | 4864 | } |
2fa48d8d | 4865 | |
1070a42b | 4866 | ret = i915_gem_init_hw(dev); |
60990320 CW |
4867 | if (ret == -EIO) { |
4868 | /* Allow ring initialisation to fail by marking the GPU as | |
4869 | * wedged. But we only want to do this where the GPU is angry, | |
4870 | * for all other failure, such as an allocation failure, bail. | |
4871 | */ | |
4872 | DRM_ERROR("Failed to initialize GPU, declaring it wedged\n"); | |
4873 | atomic_set_mask(I915_WEDGED, &dev_priv->gpu_error.reset_counter); | |
4874 | ret = 0; | |
1070a42b | 4875 | } |
60990320 | 4876 | mutex_unlock(&dev->struct_mutex); |
1070a42b | 4877 | |
60990320 | 4878 | return ret; |
1070a42b CW |
4879 | } |
4880 | ||
8187a2b7 ZN |
4881 | void |
4882 | i915_gem_cleanup_ringbuffer(struct drm_device *dev) | |
4883 | { | |
3e31c6c0 | 4884 | struct drm_i915_private *dev_priv = dev->dev_private; |
a4872ba6 | 4885 | struct intel_engine_cs *ring; |
1ec14ad3 | 4886 | int i; |
8187a2b7 | 4887 | |
b4519513 | 4888 | for_each_ring(ring, dev_priv, i) |
a83014d3 | 4889 | dev_priv->gt.cleanup_ring(ring); |
8187a2b7 ZN |
4890 | } |
4891 | ||
64193406 | 4892 | static void |
a4872ba6 | 4893 | init_ring_lists(struct intel_engine_cs *ring) |
64193406 CW |
4894 | { |
4895 | INIT_LIST_HEAD(&ring->active_list); | |
4896 | INIT_LIST_HEAD(&ring->request_list); | |
64193406 CW |
4897 | } |
4898 | ||
7e0d96bc BW |
4899 | void i915_init_vm(struct drm_i915_private *dev_priv, |
4900 | struct i915_address_space *vm) | |
fc8c067e | 4901 | { |
7e0d96bc BW |
4902 | if (!i915_is_ggtt(vm)) |
4903 | drm_mm_init(&vm->mm, vm->start, vm->total); | |
fc8c067e BW |
4904 | vm->dev = dev_priv->dev; |
4905 | INIT_LIST_HEAD(&vm->active_list); | |
4906 | INIT_LIST_HEAD(&vm->inactive_list); | |
4907 | INIT_LIST_HEAD(&vm->global_link); | |
f72d21ed | 4908 | list_add_tail(&vm->global_link, &dev_priv->vm_list); |
fc8c067e BW |
4909 | } |
4910 | ||
673a394b EA |
4911 | void |
4912 | i915_gem_load(struct drm_device *dev) | |
4913 | { | |
3e31c6c0 | 4914 | struct drm_i915_private *dev_priv = dev->dev_private; |
42dcedd4 CW |
4915 | int i; |
4916 | ||
4917 | dev_priv->slab = | |
4918 | kmem_cache_create("i915_gem_object", | |
4919 | sizeof(struct drm_i915_gem_object), 0, | |
4920 | SLAB_HWCACHE_ALIGN, | |
4921 | NULL); | |
673a394b | 4922 | |
fc8c067e BW |
4923 | INIT_LIST_HEAD(&dev_priv->vm_list); |
4924 | i915_init_vm(dev_priv, &dev_priv->gtt.base); | |
4925 | ||
a33afea5 | 4926 | INIT_LIST_HEAD(&dev_priv->context_list); |
6c085a72 CW |
4927 | INIT_LIST_HEAD(&dev_priv->mm.unbound_list); |
4928 | INIT_LIST_HEAD(&dev_priv->mm.bound_list); | |
a09ba7fa | 4929 | INIT_LIST_HEAD(&dev_priv->mm.fence_list); |
1ec14ad3 CW |
4930 | for (i = 0; i < I915_NUM_RINGS; i++) |
4931 | init_ring_lists(&dev_priv->ring[i]); | |
4b9de737 | 4932 | for (i = 0; i < I915_MAX_NUM_FENCES; i++) |
007cc8ac | 4933 | INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list); |
673a394b EA |
4934 | INIT_DELAYED_WORK(&dev_priv->mm.retire_work, |
4935 | i915_gem_retire_work_handler); | |
b29c19b6 CW |
4936 | INIT_DELAYED_WORK(&dev_priv->mm.idle_work, |
4937 | i915_gem_idle_work_handler); | |
1f83fee0 | 4938 | init_waitqueue_head(&dev_priv->gpu_error.reset_queue); |
31169714 | 4939 | |
94400120 | 4940 | /* On GEN3 we really need to make sure the ARB C3 LP bit is set */ |
dbb42748 | 4941 | if (!drm_core_check_feature(dev, DRIVER_MODESET) && IS_GEN3(dev)) { |
50743298 DV |
4942 | I915_WRITE(MI_ARB_STATE, |
4943 | _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE)); | |
94400120 DA |
4944 | } |
4945 | ||
72bfa19c CW |
4946 | dev_priv->relative_constants_mode = I915_EXEC_CONSTANTS_REL_GENERAL; |
4947 | ||
de151cf6 | 4948 | /* Old X drivers will take 0-2 for front, back, depth buffers */ |
b397c836 EA |
4949 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) |
4950 | dev_priv->fence_reg_start = 3; | |
de151cf6 | 4951 | |
42b5aeab VS |
4952 | if (INTEL_INFO(dev)->gen >= 7 && !IS_VALLEYVIEW(dev)) |
4953 | dev_priv->num_fence_regs = 32; | |
4954 | else if (INTEL_INFO(dev)->gen >= 4 || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) | |
de151cf6 JB |
4955 | dev_priv->num_fence_regs = 16; |
4956 | else | |
4957 | dev_priv->num_fence_regs = 8; | |
4958 | ||
b5aa8a0f | 4959 | /* Initialize fence registers to zero */ |
19b2dbde CW |
4960 | INIT_LIST_HEAD(&dev_priv->mm.fence_list); |
4961 | i915_gem_restore_fences(dev); | |
10ed13e4 | 4962 | |
673a394b | 4963 | i915_gem_detect_bit_6_swizzle(dev); |
6b95a207 | 4964 | init_waitqueue_head(&dev_priv->pending_flip_queue); |
17250b71 | 4965 | |
ce453d81 CW |
4966 | dev_priv->mm.interruptible = true; |
4967 | ||
ceabbba5 CW |
4968 | dev_priv->mm.shrinker.scan_objects = i915_gem_shrinker_scan; |
4969 | dev_priv->mm.shrinker.count_objects = i915_gem_shrinker_count; | |
4970 | dev_priv->mm.shrinker.seeks = DEFAULT_SEEKS; | |
4971 | register_shrinker(&dev_priv->mm.shrinker); | |
2cfcd32a CW |
4972 | |
4973 | dev_priv->mm.oom_notifier.notifier_call = i915_gem_shrinker_oom; | |
4974 | register_oom_notifier(&dev_priv->mm.oom_notifier); | |
f99d7069 DV |
4975 | |
4976 | mutex_init(&dev_priv->fb_tracking.lock); | |
673a394b | 4977 | } |
71acb5eb | 4978 | |
f787a5f5 | 4979 | void i915_gem_release(struct drm_device *dev, struct drm_file *file) |
b962442e | 4980 | { |
f787a5f5 | 4981 | struct drm_i915_file_private *file_priv = file->driver_priv; |
b962442e | 4982 | |
b29c19b6 CW |
4983 | cancel_delayed_work_sync(&file_priv->mm.idle_work); |
4984 | ||
b962442e EA |
4985 | /* Clean up our request list when the client is going away, so that |
4986 | * later retire_requests won't dereference our soon-to-be-gone | |
4987 | * file_priv. | |
4988 | */ | |
1c25595f | 4989 | spin_lock(&file_priv->mm.lock); |
f787a5f5 CW |
4990 | while (!list_empty(&file_priv->mm.request_list)) { |
4991 | struct drm_i915_gem_request *request; | |
4992 | ||
4993 | request = list_first_entry(&file_priv->mm.request_list, | |
4994 | struct drm_i915_gem_request, | |
4995 | client_list); | |
4996 | list_del(&request->client_list); | |
4997 | request->file_priv = NULL; | |
4998 | } | |
1c25595f | 4999 | spin_unlock(&file_priv->mm.lock); |
b962442e | 5000 | } |
31169714 | 5001 | |
b29c19b6 CW |
5002 | static void |
5003 | i915_gem_file_idle_work_handler(struct work_struct *work) | |
5004 | { | |
5005 | struct drm_i915_file_private *file_priv = | |
5006 | container_of(work, typeof(*file_priv), mm.idle_work.work); | |
5007 | ||
5008 | atomic_set(&file_priv->rps_wait_boost, false); | |
5009 | } | |
5010 | ||
5011 | int i915_gem_open(struct drm_device *dev, struct drm_file *file) | |
5012 | { | |
5013 | struct drm_i915_file_private *file_priv; | |
e422b888 | 5014 | int ret; |
b29c19b6 CW |
5015 | |
5016 | DRM_DEBUG_DRIVER("\n"); | |
5017 | ||
5018 | file_priv = kzalloc(sizeof(*file_priv), GFP_KERNEL); | |
5019 | if (!file_priv) | |
5020 | return -ENOMEM; | |
5021 | ||
5022 | file->driver_priv = file_priv; | |
5023 | file_priv->dev_priv = dev->dev_private; | |
ab0e7ff9 | 5024 | file_priv->file = file; |
b29c19b6 CW |
5025 | |
5026 | spin_lock_init(&file_priv->mm.lock); | |
5027 | INIT_LIST_HEAD(&file_priv->mm.request_list); | |
5028 | INIT_DELAYED_WORK(&file_priv->mm.idle_work, | |
5029 | i915_gem_file_idle_work_handler); | |
5030 | ||
e422b888 BW |
5031 | ret = i915_gem_context_open(dev, file); |
5032 | if (ret) | |
5033 | kfree(file_priv); | |
b29c19b6 | 5034 | |
e422b888 | 5035 | return ret; |
b29c19b6 CW |
5036 | } |
5037 | ||
b680c37a DV |
5038 | /** |
5039 | * i915_gem_track_fb - update frontbuffer tracking | |
5040 | * old: current GEM buffer for the frontbuffer slots | |
5041 | * new: new GEM buffer for the frontbuffer slots | |
5042 | * frontbuffer_bits: bitmask of frontbuffer slots | |
5043 | * | |
5044 | * This updates the frontbuffer tracking bits @frontbuffer_bits by clearing them | |
5045 | * from @old and setting them in @new. Both @old and @new can be NULL. | |
5046 | */ | |
a071fa00 DV |
5047 | void i915_gem_track_fb(struct drm_i915_gem_object *old, |
5048 | struct drm_i915_gem_object *new, | |
5049 | unsigned frontbuffer_bits) | |
5050 | { | |
5051 | if (old) { | |
5052 | WARN_ON(!mutex_is_locked(&old->base.dev->struct_mutex)); | |
5053 | WARN_ON(!(old->frontbuffer_bits & frontbuffer_bits)); | |
5054 | old->frontbuffer_bits &= ~frontbuffer_bits; | |
5055 | } | |
5056 | ||
5057 | if (new) { | |
5058 | WARN_ON(!mutex_is_locked(&new->base.dev->struct_mutex)); | |
5059 | WARN_ON(new->frontbuffer_bits & frontbuffer_bits); | |
5060 | new->frontbuffer_bits |= frontbuffer_bits; | |
5061 | } | |
5062 | } | |
5063 | ||
5774506f CW |
5064 | static bool mutex_is_locked_by(struct mutex *mutex, struct task_struct *task) |
5065 | { | |
5066 | if (!mutex_is_locked(mutex)) | |
5067 | return false; | |
5068 | ||
5069 | #if defined(CONFIG_SMP) || defined(CONFIG_DEBUG_MUTEXES) | |
5070 | return mutex->owner == task; | |
5071 | #else | |
5072 | /* Since UP may be pre-empted, we cannot assume that we own the lock */ | |
5073 | return false; | |
5074 | #endif | |
5075 | } | |
5076 | ||
b453c4db CW |
5077 | static bool i915_gem_shrinker_lock(struct drm_device *dev, bool *unlock) |
5078 | { | |
5079 | if (!mutex_trylock(&dev->struct_mutex)) { | |
5080 | if (!mutex_is_locked_by(&dev->struct_mutex, current)) | |
5081 | return false; | |
5082 | ||
5083 | if (to_i915(dev)->mm.shrinker_no_lock_stealing) | |
5084 | return false; | |
5085 | ||
5086 | *unlock = false; | |
5087 | } else | |
5088 | *unlock = true; | |
5089 | ||
5090 | return true; | |
5091 | } | |
5092 | ||
ceabbba5 CW |
5093 | static int num_vma_bound(struct drm_i915_gem_object *obj) |
5094 | { | |
5095 | struct i915_vma *vma; | |
5096 | int count = 0; | |
5097 | ||
5098 | list_for_each_entry(vma, &obj->vma_list, vma_link) | |
5099 | if (drm_mm_node_allocated(&vma->node)) | |
5100 | count++; | |
5101 | ||
5102 | return count; | |
5103 | } | |
5104 | ||
7dc19d5a | 5105 | static unsigned long |
ceabbba5 | 5106 | i915_gem_shrinker_count(struct shrinker *shrinker, struct shrink_control *sc) |
31169714 | 5107 | { |
17250b71 | 5108 | struct drm_i915_private *dev_priv = |
ceabbba5 | 5109 | container_of(shrinker, struct drm_i915_private, mm.shrinker); |
17250b71 | 5110 | struct drm_device *dev = dev_priv->dev; |
6c085a72 | 5111 | struct drm_i915_gem_object *obj; |
7dc19d5a | 5112 | unsigned long count; |
b453c4db | 5113 | bool unlock; |
17250b71 | 5114 | |
b453c4db CW |
5115 | if (!i915_gem_shrinker_lock(dev, &unlock)) |
5116 | return 0; | |
31169714 | 5117 | |
7dc19d5a | 5118 | count = 0; |
35c20a60 | 5119 | list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) |
a5570178 | 5120 | if (obj->pages_pin_count == 0) |
7dc19d5a | 5121 | count += obj->base.size >> PAGE_SHIFT; |
fcb4a578 BW |
5122 | |
5123 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) { | |
ceabbba5 CW |
5124 | if (!i915_gem_obj_is_pinned(obj) && |
5125 | obj->pages_pin_count == num_vma_bound(obj)) | |
7dc19d5a | 5126 | count += obj->base.size >> PAGE_SHIFT; |
fcb4a578 | 5127 | } |
17250b71 | 5128 | |
5774506f CW |
5129 | if (unlock) |
5130 | mutex_unlock(&dev->struct_mutex); | |
d9973b43 | 5131 | |
7dc19d5a | 5132 | return count; |
31169714 | 5133 | } |
a70a3148 BW |
5134 | |
5135 | /* All the new VM stuff */ | |
5136 | unsigned long i915_gem_obj_offset(struct drm_i915_gem_object *o, | |
5137 | struct i915_address_space *vm) | |
5138 | { | |
5139 | struct drm_i915_private *dev_priv = o->base.dev->dev_private; | |
5140 | struct i915_vma *vma; | |
5141 | ||
896ab1a5 | 5142 | WARN_ON(vm == &dev_priv->mm.aliasing_ppgtt->base); |
a70a3148 | 5143 | |
a70a3148 BW |
5144 | list_for_each_entry(vma, &o->vma_list, vma_link) { |
5145 | if (vma->vm == vm) | |
5146 | return vma->node.start; | |
5147 | ||
5148 | } | |
f25748ea DV |
5149 | WARN(1, "%s vma for this object not found.\n", |
5150 | i915_is_ggtt(vm) ? "global" : "ppgtt"); | |
a70a3148 BW |
5151 | return -1; |
5152 | } | |
5153 | ||
5154 | bool i915_gem_obj_bound(struct drm_i915_gem_object *o, | |
5155 | struct i915_address_space *vm) | |
5156 | { | |
5157 | struct i915_vma *vma; | |
5158 | ||
5159 | list_for_each_entry(vma, &o->vma_list, vma_link) | |
8b9c2b94 | 5160 | if (vma->vm == vm && drm_mm_node_allocated(&vma->node)) |
a70a3148 BW |
5161 | return true; |
5162 | ||
5163 | return false; | |
5164 | } | |
5165 | ||
5166 | bool i915_gem_obj_bound_any(struct drm_i915_gem_object *o) | |
5167 | { | |
5a1d5eb0 | 5168 | struct i915_vma *vma; |
a70a3148 | 5169 | |
5a1d5eb0 CW |
5170 | list_for_each_entry(vma, &o->vma_list, vma_link) |
5171 | if (drm_mm_node_allocated(&vma->node)) | |
a70a3148 BW |
5172 | return true; |
5173 | ||
5174 | return false; | |
5175 | } | |
5176 | ||
5177 | unsigned long i915_gem_obj_size(struct drm_i915_gem_object *o, | |
5178 | struct i915_address_space *vm) | |
5179 | { | |
5180 | struct drm_i915_private *dev_priv = o->base.dev->dev_private; | |
5181 | struct i915_vma *vma; | |
5182 | ||
896ab1a5 | 5183 | WARN_ON(vm == &dev_priv->mm.aliasing_ppgtt->base); |
a70a3148 BW |
5184 | |
5185 | BUG_ON(list_empty(&o->vma_list)); | |
5186 | ||
5187 | list_for_each_entry(vma, &o->vma_list, vma_link) | |
5188 | if (vma->vm == vm) | |
5189 | return vma->node.size; | |
5190 | ||
5191 | return 0; | |
5192 | } | |
5193 | ||
7dc19d5a | 5194 | static unsigned long |
ceabbba5 | 5195 | i915_gem_shrinker_scan(struct shrinker *shrinker, struct shrink_control *sc) |
7dc19d5a DC |
5196 | { |
5197 | struct drm_i915_private *dev_priv = | |
ceabbba5 | 5198 | container_of(shrinker, struct drm_i915_private, mm.shrinker); |
7dc19d5a | 5199 | struct drm_device *dev = dev_priv->dev; |
7dc19d5a | 5200 | unsigned long freed; |
b453c4db | 5201 | bool unlock; |
7dc19d5a | 5202 | |
b453c4db CW |
5203 | if (!i915_gem_shrinker_lock(dev, &unlock)) |
5204 | return SHRINK_STOP; | |
7dc19d5a | 5205 | |
21ab4e74 CW |
5206 | freed = i915_gem_shrink(dev_priv, |
5207 | sc->nr_to_scan, | |
5208 | I915_SHRINK_BOUND | | |
5209 | I915_SHRINK_UNBOUND | | |
5210 | I915_SHRINK_PURGEABLE); | |
d9973b43 | 5211 | if (freed < sc->nr_to_scan) |
21ab4e74 CW |
5212 | freed += i915_gem_shrink(dev_priv, |
5213 | sc->nr_to_scan - freed, | |
5214 | I915_SHRINK_BOUND | | |
5215 | I915_SHRINK_UNBOUND); | |
7dc19d5a DC |
5216 | if (unlock) |
5217 | mutex_unlock(&dev->struct_mutex); | |
d9973b43 | 5218 | |
7dc19d5a DC |
5219 | return freed; |
5220 | } | |
5c2abbea | 5221 | |
2cfcd32a CW |
5222 | static int |
5223 | i915_gem_shrinker_oom(struct notifier_block *nb, unsigned long event, void *ptr) | |
5224 | { | |
5225 | struct drm_i915_private *dev_priv = | |
5226 | container_of(nb, struct drm_i915_private, mm.oom_notifier); | |
5227 | struct drm_device *dev = dev_priv->dev; | |
5228 | struct drm_i915_gem_object *obj; | |
5229 | unsigned long timeout = msecs_to_jiffies(5000) + 1; | |
005445c5 | 5230 | unsigned long pinned, bound, unbound, freed_pages; |
2cfcd32a CW |
5231 | bool was_interruptible; |
5232 | bool unlock; | |
5233 | ||
a1db2fa7 | 5234 | while (!i915_gem_shrinker_lock(dev, &unlock) && --timeout) { |
2cfcd32a | 5235 | schedule_timeout_killable(1); |
a1db2fa7 CW |
5236 | if (fatal_signal_pending(current)) |
5237 | return NOTIFY_DONE; | |
5238 | } | |
2cfcd32a CW |
5239 | if (timeout == 0) { |
5240 | pr_err("Unable to purge GPU memory due lock contention.\n"); | |
5241 | return NOTIFY_DONE; | |
5242 | } | |
5243 | ||
5244 | was_interruptible = dev_priv->mm.interruptible; | |
5245 | dev_priv->mm.interruptible = false; | |
5246 | ||
005445c5 | 5247 | freed_pages = i915_gem_shrink_all(dev_priv); |
2cfcd32a CW |
5248 | |
5249 | dev_priv->mm.interruptible = was_interruptible; | |
5250 | ||
5251 | /* Because we may be allocating inside our own driver, we cannot | |
5252 | * assert that there are no objects with pinned pages that are not | |
5253 | * being pointed to by hardware. | |
5254 | */ | |
5255 | unbound = bound = pinned = 0; | |
5256 | list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) { | |
5257 | if (!obj->base.filp) /* not backed by a freeable object */ | |
5258 | continue; | |
5259 | ||
5260 | if (obj->pages_pin_count) | |
5261 | pinned += obj->base.size; | |
5262 | else | |
5263 | unbound += obj->base.size; | |
5264 | } | |
5265 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) { | |
5266 | if (!obj->base.filp) | |
5267 | continue; | |
5268 | ||
5269 | if (obj->pages_pin_count) | |
5270 | pinned += obj->base.size; | |
5271 | else | |
5272 | bound += obj->base.size; | |
5273 | } | |
5274 | ||
5275 | if (unlock) | |
5276 | mutex_unlock(&dev->struct_mutex); | |
5277 | ||
bb9059d3 CW |
5278 | if (freed_pages || unbound || bound) |
5279 | pr_info("Purging GPU memory, %lu bytes freed, %lu bytes still pinned.\n", | |
5280 | freed_pages << PAGE_SHIFT, pinned); | |
2cfcd32a CW |
5281 | if (unbound || bound) |
5282 | pr_err("%lu and %lu bytes still available in the " | |
5283 | "bound and unbound GPU page lists.\n", | |
5284 | bound, unbound); | |
5285 | ||
005445c5 | 5286 | *(unsigned long *)ptr += freed_pages; |
2cfcd32a CW |
5287 | return NOTIFY_DONE; |
5288 | } | |
5289 | ||
5c2abbea BW |
5290 | struct i915_vma *i915_gem_obj_to_ggtt(struct drm_i915_gem_object *obj) |
5291 | { | |
5292 | struct i915_vma *vma; | |
5293 | ||
5c2abbea | 5294 | vma = list_first_entry(&obj->vma_list, typeof(*vma), vma_link); |
5dc383b0 | 5295 | if (vma->vm != i915_obj_to_ggtt(obj)) |
5c2abbea BW |
5296 | return NULL; |
5297 | ||
5298 | return vma; | |
5299 | } |