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Commit | Line | Data |
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673a394b EA |
1 | /* |
2 | * Copyright © 2008 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | * | |
26 | */ | |
27 | ||
28 | #include "drmP.h" | |
29 | #include "drm.h" | |
30 | #include "i915_drm.h" | |
31 | #include "i915_drv.h" | |
1c5d22f7 | 32 | #include "i915_trace.h" |
652c393a | 33 | #include "intel_drv.h" |
5949eac4 | 34 | #include <linux/shmem_fs.h> |
5a0e3ad6 | 35 | #include <linux/slab.h> |
673a394b | 36 | #include <linux/swap.h> |
79e53945 | 37 | #include <linux/pci.h> |
673a394b | 38 | |
88241785 | 39 | static __must_check int i915_gem_object_flush_gpu_write_domain(struct drm_i915_gem_object *obj); |
05394f39 CW |
40 | static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj); |
41 | static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj); | |
88241785 CW |
42 | static __must_check int i915_gem_object_bind_to_gtt(struct drm_i915_gem_object *obj, |
43 | unsigned alignment, | |
44 | bool map_and_fenceable); | |
d9e86c0e CW |
45 | static void i915_gem_clear_fence_reg(struct drm_device *dev, |
46 | struct drm_i915_fence_reg *reg); | |
05394f39 CW |
47 | static int i915_gem_phys_pwrite(struct drm_device *dev, |
48 | struct drm_i915_gem_object *obj, | |
71acb5eb | 49 | struct drm_i915_gem_pwrite *args, |
05394f39 CW |
50 | struct drm_file *file); |
51 | static void i915_gem_free_object_tail(struct drm_i915_gem_object *obj); | |
673a394b | 52 | |
17250b71 | 53 | static int i915_gem_inactive_shrink(struct shrinker *shrinker, |
1495f230 | 54 | struct shrink_control *sc); |
8c59967c | 55 | static void i915_gem_object_truncate(struct drm_i915_gem_object *obj); |
31169714 | 56 | |
73aa808f CW |
57 | /* some bookkeeping */ |
58 | static void i915_gem_info_add_obj(struct drm_i915_private *dev_priv, | |
59 | size_t size) | |
60 | { | |
61 | dev_priv->mm.object_count++; | |
62 | dev_priv->mm.object_memory += size; | |
63 | } | |
64 | ||
65 | static void i915_gem_info_remove_obj(struct drm_i915_private *dev_priv, | |
66 | size_t size) | |
67 | { | |
68 | dev_priv->mm.object_count--; | |
69 | dev_priv->mm.object_memory -= size; | |
70 | } | |
71 | ||
21dd3734 CW |
72 | static int |
73 | i915_gem_wait_for_error(struct drm_device *dev) | |
30dbf0c0 CW |
74 | { |
75 | struct drm_i915_private *dev_priv = dev->dev_private; | |
76 | struct completion *x = &dev_priv->error_completion; | |
77 | unsigned long flags; | |
78 | int ret; | |
79 | ||
80 | if (!atomic_read(&dev_priv->mm.wedged)) | |
81 | return 0; | |
82 | ||
83 | ret = wait_for_completion_interruptible(x); | |
84 | if (ret) | |
85 | return ret; | |
86 | ||
21dd3734 CW |
87 | if (atomic_read(&dev_priv->mm.wedged)) { |
88 | /* GPU is hung, bump the completion count to account for | |
89 | * the token we just consumed so that we never hit zero and | |
90 | * end up waiting upon a subsequent completion event that | |
91 | * will never happen. | |
92 | */ | |
93 | spin_lock_irqsave(&x->wait.lock, flags); | |
94 | x->done++; | |
95 | spin_unlock_irqrestore(&x->wait.lock, flags); | |
96 | } | |
97 | return 0; | |
30dbf0c0 CW |
98 | } |
99 | ||
54cf91dc | 100 | int i915_mutex_lock_interruptible(struct drm_device *dev) |
76c1dec1 | 101 | { |
76c1dec1 CW |
102 | int ret; |
103 | ||
21dd3734 | 104 | ret = i915_gem_wait_for_error(dev); |
76c1dec1 CW |
105 | if (ret) |
106 | return ret; | |
107 | ||
108 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
109 | if (ret) | |
110 | return ret; | |
111 | ||
23bc5982 | 112 | WARN_ON(i915_verify_lists(dev)); |
76c1dec1 CW |
113 | return 0; |
114 | } | |
30dbf0c0 | 115 | |
7d1c4804 | 116 | static inline bool |
05394f39 | 117 | i915_gem_object_is_inactive(struct drm_i915_gem_object *obj) |
7d1c4804 | 118 | { |
05394f39 | 119 | return obj->gtt_space && !obj->active && obj->pin_count == 0; |
7d1c4804 CW |
120 | } |
121 | ||
79e53945 JB |
122 | int |
123 | i915_gem_init_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 124 | struct drm_file *file) |
79e53945 JB |
125 | { |
126 | struct drm_i915_gem_init *args = data; | |
2021746e CW |
127 | |
128 | if (args->gtt_start >= args->gtt_end || | |
129 | (args->gtt_end | args->gtt_start) & (PAGE_SIZE - 1)) | |
130 | return -EINVAL; | |
79e53945 JB |
131 | |
132 | mutex_lock(&dev->struct_mutex); | |
644ec02b DV |
133 | i915_gem_init_global_gtt(dev, args->gtt_start, |
134 | args->gtt_end, args->gtt_end); | |
673a394b EA |
135 | mutex_unlock(&dev->struct_mutex); |
136 | ||
2021746e | 137 | return 0; |
673a394b EA |
138 | } |
139 | ||
5a125c3c EA |
140 | int |
141 | i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 142 | struct drm_file *file) |
5a125c3c | 143 | { |
73aa808f | 144 | struct drm_i915_private *dev_priv = dev->dev_private; |
5a125c3c | 145 | struct drm_i915_gem_get_aperture *args = data; |
6299f992 CW |
146 | struct drm_i915_gem_object *obj; |
147 | size_t pinned; | |
5a125c3c EA |
148 | |
149 | if (!(dev->driver->driver_features & DRIVER_GEM)) | |
150 | return -ENODEV; | |
151 | ||
6299f992 | 152 | pinned = 0; |
73aa808f | 153 | mutex_lock(&dev->struct_mutex); |
6299f992 CW |
154 | list_for_each_entry(obj, &dev_priv->mm.pinned_list, mm_list) |
155 | pinned += obj->gtt_space->size; | |
73aa808f | 156 | mutex_unlock(&dev->struct_mutex); |
5a125c3c | 157 | |
6299f992 | 158 | args->aper_size = dev_priv->mm.gtt_total; |
0206e353 | 159 | args->aper_available_size = args->aper_size - pinned; |
6299f992 | 160 | |
5a125c3c EA |
161 | return 0; |
162 | } | |
163 | ||
ff72145b DA |
164 | static int |
165 | i915_gem_create(struct drm_file *file, | |
166 | struct drm_device *dev, | |
167 | uint64_t size, | |
168 | uint32_t *handle_p) | |
673a394b | 169 | { |
05394f39 | 170 | struct drm_i915_gem_object *obj; |
a1a2d1d3 PP |
171 | int ret; |
172 | u32 handle; | |
673a394b | 173 | |
ff72145b | 174 | size = roundup(size, PAGE_SIZE); |
8ffc0246 CW |
175 | if (size == 0) |
176 | return -EINVAL; | |
673a394b EA |
177 | |
178 | /* Allocate the new object */ | |
ff72145b | 179 | obj = i915_gem_alloc_object(dev, size); |
673a394b EA |
180 | if (obj == NULL) |
181 | return -ENOMEM; | |
182 | ||
05394f39 | 183 | ret = drm_gem_handle_create(file, &obj->base, &handle); |
1dfd9754 | 184 | if (ret) { |
05394f39 CW |
185 | drm_gem_object_release(&obj->base); |
186 | i915_gem_info_remove_obj(dev->dev_private, obj->base.size); | |
202f2fef | 187 | kfree(obj); |
673a394b | 188 | return ret; |
1dfd9754 | 189 | } |
673a394b | 190 | |
202f2fef | 191 | /* drop reference from allocate - handle holds it now */ |
05394f39 | 192 | drm_gem_object_unreference(&obj->base); |
202f2fef CW |
193 | trace_i915_gem_object_create(obj); |
194 | ||
ff72145b | 195 | *handle_p = handle; |
673a394b EA |
196 | return 0; |
197 | } | |
198 | ||
ff72145b DA |
199 | int |
200 | i915_gem_dumb_create(struct drm_file *file, | |
201 | struct drm_device *dev, | |
202 | struct drm_mode_create_dumb *args) | |
203 | { | |
204 | /* have to work out size/pitch and return them */ | |
ed0291fd | 205 | args->pitch = ALIGN(args->width * ((args->bpp + 7) / 8), 64); |
ff72145b DA |
206 | args->size = args->pitch * args->height; |
207 | return i915_gem_create(file, dev, | |
208 | args->size, &args->handle); | |
209 | } | |
210 | ||
211 | int i915_gem_dumb_destroy(struct drm_file *file, | |
212 | struct drm_device *dev, | |
213 | uint32_t handle) | |
214 | { | |
215 | return drm_gem_handle_delete(file, handle); | |
216 | } | |
217 | ||
218 | /** | |
219 | * Creates a new mm object and returns a handle to it. | |
220 | */ | |
221 | int | |
222 | i915_gem_create_ioctl(struct drm_device *dev, void *data, | |
223 | struct drm_file *file) | |
224 | { | |
225 | struct drm_i915_gem_create *args = data; | |
226 | return i915_gem_create(file, dev, | |
227 | args->size, &args->handle); | |
228 | } | |
229 | ||
05394f39 | 230 | static int i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj) |
280b713b | 231 | { |
05394f39 | 232 | drm_i915_private_t *dev_priv = obj->base.dev->dev_private; |
280b713b EA |
233 | |
234 | return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 && | |
05394f39 | 235 | obj->tiling_mode != I915_TILING_NONE; |
280b713b EA |
236 | } |
237 | ||
8461d226 DV |
238 | static inline int |
239 | __copy_to_user_swizzled(char __user *cpu_vaddr, | |
240 | const char *gpu_vaddr, int gpu_offset, | |
241 | int length) | |
242 | { | |
243 | int ret, cpu_offset = 0; | |
244 | ||
245 | while (length > 0) { | |
246 | int cacheline_end = ALIGN(gpu_offset + 1, 64); | |
247 | int this_length = min(cacheline_end - gpu_offset, length); | |
248 | int swizzled_gpu_offset = gpu_offset ^ 64; | |
249 | ||
250 | ret = __copy_to_user(cpu_vaddr + cpu_offset, | |
251 | gpu_vaddr + swizzled_gpu_offset, | |
252 | this_length); | |
253 | if (ret) | |
254 | return ret + length; | |
255 | ||
256 | cpu_offset += this_length; | |
257 | gpu_offset += this_length; | |
258 | length -= this_length; | |
259 | } | |
260 | ||
261 | return 0; | |
262 | } | |
263 | ||
8c59967c DV |
264 | static inline int |
265 | __copy_from_user_swizzled(char __user *gpu_vaddr, int gpu_offset, | |
266 | const char *cpu_vaddr, | |
267 | int length) | |
268 | { | |
269 | int ret, cpu_offset = 0; | |
270 | ||
271 | while (length > 0) { | |
272 | int cacheline_end = ALIGN(gpu_offset + 1, 64); | |
273 | int this_length = min(cacheline_end - gpu_offset, length); | |
274 | int swizzled_gpu_offset = gpu_offset ^ 64; | |
275 | ||
276 | ret = __copy_from_user(gpu_vaddr + swizzled_gpu_offset, | |
277 | cpu_vaddr + cpu_offset, | |
278 | this_length); | |
279 | if (ret) | |
280 | return ret + length; | |
281 | ||
282 | cpu_offset += this_length; | |
283 | gpu_offset += this_length; | |
284 | length -= this_length; | |
285 | } | |
286 | ||
287 | return 0; | |
288 | } | |
289 | ||
eb01459f | 290 | static int |
dbf7bff0 DV |
291 | i915_gem_shmem_pread(struct drm_device *dev, |
292 | struct drm_i915_gem_object *obj, | |
293 | struct drm_i915_gem_pread *args, | |
294 | struct drm_file *file) | |
eb01459f | 295 | { |
05394f39 | 296 | struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping; |
8461d226 | 297 | char __user *user_data; |
eb01459f | 298 | ssize_t remain; |
8461d226 | 299 | loff_t offset; |
eb2c0c81 | 300 | int shmem_page_offset, page_length, ret = 0; |
8461d226 | 301 | int obj_do_bit17_swizzling, page_do_bit17_swizzling; |
dbf7bff0 | 302 | int hit_slowpath = 0; |
8489731c | 303 | int needs_clflush = 0; |
eb01459f | 304 | |
8461d226 | 305 | user_data = (char __user *) (uintptr_t) args->data_ptr; |
eb01459f EA |
306 | remain = args->size; |
307 | ||
8461d226 | 308 | obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj); |
eb01459f | 309 | |
8489731c DV |
310 | if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU)) { |
311 | /* If we're not in the cpu read domain, set ourself into the gtt | |
312 | * read domain and manually flush cachelines (if required). This | |
313 | * optimizes for the case when the gpu will dirty the data | |
314 | * anyway again before the next pread happens. */ | |
315 | if (obj->cache_level == I915_CACHE_NONE) | |
316 | needs_clflush = 1; | |
317 | ret = i915_gem_object_set_to_gtt_domain(obj, false); | |
318 | if (ret) | |
319 | return ret; | |
320 | } | |
321 | ||
8461d226 | 322 | offset = args->offset; |
eb01459f | 323 | |
eb01459f | 324 | while (remain > 0) { |
e5281ccd | 325 | struct page *page; |
8461d226 | 326 | char *vaddr; |
e5281ccd | 327 | |
eb01459f EA |
328 | /* Operation in this page |
329 | * | |
eb01459f | 330 | * shmem_page_offset = offset within page in shmem file |
eb01459f EA |
331 | * page_length = bytes to copy for this page |
332 | */ | |
c8cbbb8b | 333 | shmem_page_offset = offset_in_page(offset); |
eb01459f EA |
334 | page_length = remain; |
335 | if ((shmem_page_offset + page_length) > PAGE_SIZE) | |
336 | page_length = PAGE_SIZE - shmem_page_offset; | |
eb01459f | 337 | |
5949eac4 | 338 | page = shmem_read_mapping_page(mapping, offset >> PAGE_SHIFT); |
b65552f0 JJ |
339 | if (IS_ERR(page)) { |
340 | ret = PTR_ERR(page); | |
341 | goto out; | |
342 | } | |
e5281ccd | 343 | |
8461d226 DV |
344 | page_do_bit17_swizzling = obj_do_bit17_swizzling && |
345 | (page_to_phys(page) & (1 << 17)) != 0; | |
346 | ||
dbf7bff0 DV |
347 | if (!page_do_bit17_swizzling) { |
348 | vaddr = kmap_atomic(page); | |
8489731c DV |
349 | if (needs_clflush) |
350 | drm_clflush_virt_range(vaddr + shmem_page_offset, | |
351 | page_length); | |
dbf7bff0 DV |
352 | ret = __copy_to_user_inatomic(user_data, |
353 | vaddr + shmem_page_offset, | |
354 | page_length); | |
355 | kunmap_atomic(vaddr); | |
356 | if (ret == 0) | |
357 | goto next_page; | |
358 | } | |
359 | ||
360 | hit_slowpath = 1; | |
361 | ||
362 | mutex_unlock(&dev->struct_mutex); | |
363 | ||
8461d226 | 364 | vaddr = kmap(page); |
8489731c DV |
365 | if (needs_clflush) |
366 | drm_clflush_virt_range(vaddr + shmem_page_offset, | |
367 | page_length); | |
368 | ||
8461d226 DV |
369 | if (page_do_bit17_swizzling) |
370 | ret = __copy_to_user_swizzled(user_data, | |
371 | vaddr, shmem_page_offset, | |
372 | page_length); | |
373 | else | |
374 | ret = __copy_to_user(user_data, | |
375 | vaddr + shmem_page_offset, | |
376 | page_length); | |
377 | kunmap(page); | |
eb01459f | 378 | |
dbf7bff0 DV |
379 | mutex_lock(&dev->struct_mutex); |
380 | next_page: | |
e5281ccd CW |
381 | mark_page_accessed(page); |
382 | page_cache_release(page); | |
383 | ||
8461d226 DV |
384 | if (ret) { |
385 | ret = -EFAULT; | |
386 | goto out; | |
387 | } | |
388 | ||
eb01459f | 389 | remain -= page_length; |
8461d226 | 390 | user_data += page_length; |
eb01459f EA |
391 | offset += page_length; |
392 | } | |
393 | ||
4f27b75d | 394 | out: |
dbf7bff0 DV |
395 | if (hit_slowpath) { |
396 | /* Fixup: Kill any reinstated backing storage pages */ | |
397 | if (obj->madv == __I915_MADV_PURGED) | |
398 | i915_gem_object_truncate(obj); | |
399 | } | |
eb01459f EA |
400 | |
401 | return ret; | |
402 | } | |
403 | ||
673a394b EA |
404 | /** |
405 | * Reads data from the object referenced by handle. | |
406 | * | |
407 | * On error, the contents of *data are undefined. | |
408 | */ | |
409 | int | |
410 | i915_gem_pread_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 411 | struct drm_file *file) |
673a394b EA |
412 | { |
413 | struct drm_i915_gem_pread *args = data; | |
05394f39 | 414 | struct drm_i915_gem_object *obj; |
35b62a89 | 415 | int ret = 0; |
673a394b | 416 | |
51311d0a CW |
417 | if (args->size == 0) |
418 | return 0; | |
419 | ||
420 | if (!access_ok(VERIFY_WRITE, | |
421 | (char __user *)(uintptr_t)args->data_ptr, | |
422 | args->size)) | |
423 | return -EFAULT; | |
424 | ||
425 | ret = fault_in_pages_writeable((char __user *)(uintptr_t)args->data_ptr, | |
426 | args->size); | |
427 | if (ret) | |
428 | return -EFAULT; | |
429 | ||
4f27b75d | 430 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 431 | if (ret) |
4f27b75d | 432 | return ret; |
673a394b | 433 | |
05394f39 | 434 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 435 | if (&obj->base == NULL) { |
1d7cfea1 CW |
436 | ret = -ENOENT; |
437 | goto unlock; | |
4f27b75d | 438 | } |
673a394b | 439 | |
7dcd2499 | 440 | /* Bounds check source. */ |
05394f39 CW |
441 | if (args->offset > obj->base.size || |
442 | args->size > obj->base.size - args->offset) { | |
ce9d419d | 443 | ret = -EINVAL; |
35b62a89 | 444 | goto out; |
ce9d419d CW |
445 | } |
446 | ||
db53a302 CW |
447 | trace_i915_gem_object_pread(obj, args->offset, args->size); |
448 | ||
dbf7bff0 | 449 | ret = i915_gem_shmem_pread(dev, obj, args, file); |
673a394b | 450 | |
35b62a89 | 451 | out: |
05394f39 | 452 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 453 | unlock: |
4f27b75d | 454 | mutex_unlock(&dev->struct_mutex); |
eb01459f | 455 | return ret; |
673a394b EA |
456 | } |
457 | ||
0839ccb8 KP |
458 | /* This is the fast write path which cannot handle |
459 | * page faults in the source data | |
9b7530cc | 460 | */ |
0839ccb8 KP |
461 | |
462 | static inline int | |
463 | fast_user_write(struct io_mapping *mapping, | |
464 | loff_t page_base, int page_offset, | |
465 | char __user *user_data, | |
466 | int length) | |
9b7530cc | 467 | { |
9b7530cc | 468 | char *vaddr_atomic; |
0839ccb8 | 469 | unsigned long unwritten; |
9b7530cc | 470 | |
3e4d3af5 | 471 | vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base); |
0839ccb8 KP |
472 | unwritten = __copy_from_user_inatomic_nocache(vaddr_atomic + page_offset, |
473 | user_data, length); | |
3e4d3af5 | 474 | io_mapping_unmap_atomic(vaddr_atomic); |
fbd5a26d | 475 | return unwritten; |
0839ccb8 KP |
476 | } |
477 | ||
478 | /* Here's the write path which can sleep for | |
479 | * page faults | |
480 | */ | |
481 | ||
ab34c226 | 482 | static inline void |
3de09aa3 EA |
483 | slow_kernel_write(struct io_mapping *mapping, |
484 | loff_t gtt_base, int gtt_offset, | |
485 | struct page *user_page, int user_offset, | |
486 | int length) | |
0839ccb8 | 487 | { |
ab34c226 CW |
488 | char __iomem *dst_vaddr; |
489 | char *src_vaddr; | |
0839ccb8 | 490 | |
ab34c226 CW |
491 | dst_vaddr = io_mapping_map_wc(mapping, gtt_base); |
492 | src_vaddr = kmap(user_page); | |
493 | ||
494 | memcpy_toio(dst_vaddr + gtt_offset, | |
495 | src_vaddr + user_offset, | |
496 | length); | |
497 | ||
498 | kunmap(user_page); | |
499 | io_mapping_unmap(dst_vaddr); | |
9b7530cc LT |
500 | } |
501 | ||
3de09aa3 EA |
502 | /** |
503 | * This is the fast pwrite path, where we copy the data directly from the | |
504 | * user into the GTT, uncached. | |
505 | */ | |
673a394b | 506 | static int |
05394f39 CW |
507 | i915_gem_gtt_pwrite_fast(struct drm_device *dev, |
508 | struct drm_i915_gem_object *obj, | |
3de09aa3 | 509 | struct drm_i915_gem_pwrite *args, |
05394f39 | 510 | struct drm_file *file) |
673a394b | 511 | { |
0839ccb8 | 512 | drm_i915_private_t *dev_priv = dev->dev_private; |
673a394b | 513 | ssize_t remain; |
0839ccb8 | 514 | loff_t offset, page_base; |
673a394b | 515 | char __user *user_data; |
0839ccb8 | 516 | int page_offset, page_length; |
673a394b EA |
517 | |
518 | user_data = (char __user *) (uintptr_t) args->data_ptr; | |
519 | remain = args->size; | |
673a394b | 520 | |
05394f39 | 521 | offset = obj->gtt_offset + args->offset; |
673a394b EA |
522 | |
523 | while (remain > 0) { | |
524 | /* Operation in this page | |
525 | * | |
0839ccb8 KP |
526 | * page_base = page offset within aperture |
527 | * page_offset = offset within page | |
528 | * page_length = bytes to copy for this page | |
673a394b | 529 | */ |
c8cbbb8b CW |
530 | page_base = offset & PAGE_MASK; |
531 | page_offset = offset_in_page(offset); | |
0839ccb8 KP |
532 | page_length = remain; |
533 | if ((page_offset + remain) > PAGE_SIZE) | |
534 | page_length = PAGE_SIZE - page_offset; | |
535 | ||
0839ccb8 | 536 | /* If we get a fault while copying data, then (presumably) our |
3de09aa3 EA |
537 | * source page isn't available. Return the error and we'll |
538 | * retry in the slow path. | |
0839ccb8 | 539 | */ |
fbd5a26d CW |
540 | if (fast_user_write(dev_priv->mm.gtt_mapping, page_base, |
541 | page_offset, user_data, page_length)) | |
fbd5a26d | 542 | return -EFAULT; |
673a394b | 543 | |
0839ccb8 KP |
544 | remain -= page_length; |
545 | user_data += page_length; | |
546 | offset += page_length; | |
673a394b | 547 | } |
673a394b | 548 | |
fbd5a26d | 549 | return 0; |
673a394b EA |
550 | } |
551 | ||
3de09aa3 EA |
552 | /** |
553 | * This is the fallback GTT pwrite path, which uses get_user_pages to pin | |
554 | * the memory and maps it using kmap_atomic for copying. | |
555 | * | |
556 | * This code resulted in x11perf -rgb10text consuming about 10% more CPU | |
557 | * than using i915_gem_gtt_pwrite_fast on a G45 (32-bit). | |
558 | */ | |
3043c60c | 559 | static int |
05394f39 CW |
560 | i915_gem_gtt_pwrite_slow(struct drm_device *dev, |
561 | struct drm_i915_gem_object *obj, | |
3de09aa3 | 562 | struct drm_i915_gem_pwrite *args, |
05394f39 | 563 | struct drm_file *file) |
673a394b | 564 | { |
3de09aa3 EA |
565 | drm_i915_private_t *dev_priv = dev->dev_private; |
566 | ssize_t remain; | |
567 | loff_t gtt_page_base, offset; | |
568 | loff_t first_data_page, last_data_page, num_pages; | |
569 | loff_t pinned_pages, i; | |
570 | struct page **user_pages; | |
571 | struct mm_struct *mm = current->mm; | |
572 | int gtt_page_offset, data_page_offset, data_page_index, page_length; | |
673a394b | 573 | int ret; |
3de09aa3 EA |
574 | uint64_t data_ptr = args->data_ptr; |
575 | ||
576 | remain = args->size; | |
577 | ||
578 | /* Pin the user pages containing the data. We can't fault while | |
579 | * holding the struct mutex, and all of the pwrite implementations | |
580 | * want to hold it while dereferencing the user data. | |
581 | */ | |
582 | first_data_page = data_ptr / PAGE_SIZE; | |
583 | last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE; | |
584 | num_pages = last_data_page - first_data_page + 1; | |
585 | ||
fbd5a26d | 586 | user_pages = drm_malloc_ab(num_pages, sizeof(struct page *)); |
3de09aa3 EA |
587 | if (user_pages == NULL) |
588 | return -ENOMEM; | |
589 | ||
fbd5a26d | 590 | mutex_unlock(&dev->struct_mutex); |
3de09aa3 EA |
591 | down_read(&mm->mmap_sem); |
592 | pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr, | |
593 | num_pages, 0, 0, user_pages, NULL); | |
594 | up_read(&mm->mmap_sem); | |
fbd5a26d | 595 | mutex_lock(&dev->struct_mutex); |
3de09aa3 EA |
596 | if (pinned_pages < num_pages) { |
597 | ret = -EFAULT; | |
598 | goto out_unpin_pages; | |
599 | } | |
673a394b | 600 | |
d9e86c0e CW |
601 | ret = i915_gem_object_set_to_gtt_domain(obj, true); |
602 | if (ret) | |
603 | goto out_unpin_pages; | |
604 | ||
605 | ret = i915_gem_object_put_fence(obj); | |
3de09aa3 | 606 | if (ret) |
fbd5a26d | 607 | goto out_unpin_pages; |
3de09aa3 | 608 | |
05394f39 | 609 | offset = obj->gtt_offset + args->offset; |
3de09aa3 EA |
610 | |
611 | while (remain > 0) { | |
612 | /* Operation in this page | |
613 | * | |
614 | * gtt_page_base = page offset within aperture | |
615 | * gtt_page_offset = offset within page in aperture | |
616 | * data_page_index = page number in get_user_pages return | |
617 | * data_page_offset = offset with data_page_index page. | |
618 | * page_length = bytes to copy for this page | |
619 | */ | |
620 | gtt_page_base = offset & PAGE_MASK; | |
c8cbbb8b | 621 | gtt_page_offset = offset_in_page(offset); |
3de09aa3 | 622 | data_page_index = data_ptr / PAGE_SIZE - first_data_page; |
c8cbbb8b | 623 | data_page_offset = offset_in_page(data_ptr); |
3de09aa3 EA |
624 | |
625 | page_length = remain; | |
626 | if ((gtt_page_offset + page_length) > PAGE_SIZE) | |
627 | page_length = PAGE_SIZE - gtt_page_offset; | |
628 | if ((data_page_offset + page_length) > PAGE_SIZE) | |
629 | page_length = PAGE_SIZE - data_page_offset; | |
630 | ||
ab34c226 CW |
631 | slow_kernel_write(dev_priv->mm.gtt_mapping, |
632 | gtt_page_base, gtt_page_offset, | |
633 | user_pages[data_page_index], | |
634 | data_page_offset, | |
635 | page_length); | |
3de09aa3 EA |
636 | |
637 | remain -= page_length; | |
638 | offset += page_length; | |
639 | data_ptr += page_length; | |
640 | } | |
641 | ||
3de09aa3 EA |
642 | out_unpin_pages: |
643 | for (i = 0; i < pinned_pages; i++) | |
644 | page_cache_release(user_pages[i]); | |
8e7d2b2c | 645 | drm_free_large(user_pages); |
3de09aa3 EA |
646 | |
647 | return ret; | |
648 | } | |
649 | ||
3043c60c | 650 | static int |
e244a443 DV |
651 | i915_gem_shmem_pwrite(struct drm_device *dev, |
652 | struct drm_i915_gem_object *obj, | |
653 | struct drm_i915_gem_pwrite *args, | |
654 | struct drm_file *file) | |
40123c1f | 655 | { |
05394f39 | 656 | struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping; |
40123c1f | 657 | ssize_t remain; |
8c59967c DV |
658 | loff_t offset; |
659 | char __user *user_data; | |
eb2c0c81 | 660 | int shmem_page_offset, page_length, ret = 0; |
8c59967c | 661 | int obj_do_bit17_swizzling, page_do_bit17_swizzling; |
e244a443 | 662 | int hit_slowpath = 0; |
40123c1f | 663 | |
8c59967c | 664 | user_data = (char __user *) (uintptr_t) args->data_ptr; |
40123c1f EA |
665 | remain = args->size; |
666 | ||
8c59967c | 667 | obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj); |
40123c1f | 668 | |
673a394b | 669 | offset = args->offset; |
05394f39 | 670 | obj->dirty = 1; |
673a394b | 671 | |
40123c1f | 672 | while (remain > 0) { |
e5281ccd | 673 | struct page *page; |
8c59967c | 674 | char *vaddr; |
e5281ccd | 675 | |
40123c1f EA |
676 | /* Operation in this page |
677 | * | |
40123c1f | 678 | * shmem_page_offset = offset within page in shmem file |
40123c1f EA |
679 | * page_length = bytes to copy for this page |
680 | */ | |
c8cbbb8b | 681 | shmem_page_offset = offset_in_page(offset); |
40123c1f EA |
682 | |
683 | page_length = remain; | |
684 | if ((shmem_page_offset + page_length) > PAGE_SIZE) | |
685 | page_length = PAGE_SIZE - shmem_page_offset; | |
40123c1f | 686 | |
5949eac4 | 687 | page = shmem_read_mapping_page(mapping, offset >> PAGE_SHIFT); |
e5281ccd CW |
688 | if (IS_ERR(page)) { |
689 | ret = PTR_ERR(page); | |
690 | goto out; | |
691 | } | |
692 | ||
8c59967c DV |
693 | page_do_bit17_swizzling = obj_do_bit17_swizzling && |
694 | (page_to_phys(page) & (1 << 17)) != 0; | |
695 | ||
e244a443 DV |
696 | if (!page_do_bit17_swizzling) { |
697 | vaddr = kmap_atomic(page); | |
698 | ret = __copy_from_user_inatomic(vaddr + shmem_page_offset, | |
699 | user_data, | |
700 | page_length); | |
701 | kunmap_atomic(vaddr); | |
702 | ||
703 | if (ret == 0) | |
704 | goto next_page; | |
705 | } | |
706 | ||
707 | hit_slowpath = 1; | |
708 | ||
709 | mutex_unlock(&dev->struct_mutex); | |
710 | ||
8c59967c DV |
711 | vaddr = kmap(page); |
712 | if (page_do_bit17_swizzling) | |
713 | ret = __copy_from_user_swizzled(vaddr, shmem_page_offset, | |
714 | user_data, | |
715 | page_length); | |
716 | else | |
717 | ret = __copy_from_user(vaddr + shmem_page_offset, | |
718 | user_data, | |
719 | page_length); | |
720 | kunmap(page); | |
40123c1f | 721 | |
e244a443 DV |
722 | mutex_lock(&dev->struct_mutex); |
723 | next_page: | |
e5281ccd CW |
724 | set_page_dirty(page); |
725 | mark_page_accessed(page); | |
726 | page_cache_release(page); | |
727 | ||
8c59967c DV |
728 | if (ret) { |
729 | ret = -EFAULT; | |
730 | goto out; | |
731 | } | |
732 | ||
40123c1f | 733 | remain -= page_length; |
8c59967c | 734 | user_data += page_length; |
40123c1f | 735 | offset += page_length; |
673a394b EA |
736 | } |
737 | ||
fbd5a26d | 738 | out: |
e244a443 DV |
739 | if (hit_slowpath) { |
740 | /* Fixup: Kill any reinstated backing storage pages */ | |
741 | if (obj->madv == __I915_MADV_PURGED) | |
742 | i915_gem_object_truncate(obj); | |
743 | /* and flush dirty cachelines in case the object isn't in the cpu write | |
744 | * domain anymore. */ | |
745 | if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) { | |
746 | i915_gem_clflush_object(obj); | |
747 | intel_gtt_chipset_flush(); | |
748 | } | |
8c59967c | 749 | } |
673a394b | 750 | |
40123c1f | 751 | return ret; |
673a394b EA |
752 | } |
753 | ||
754 | /** | |
755 | * Writes data to the object referenced by handle. | |
756 | * | |
757 | * On error, the contents of the buffer that were to be modified are undefined. | |
758 | */ | |
759 | int | |
760 | i915_gem_pwrite_ioctl(struct drm_device *dev, void *data, | |
fbd5a26d | 761 | struct drm_file *file) |
673a394b EA |
762 | { |
763 | struct drm_i915_gem_pwrite *args = data; | |
05394f39 | 764 | struct drm_i915_gem_object *obj; |
51311d0a CW |
765 | int ret; |
766 | ||
767 | if (args->size == 0) | |
768 | return 0; | |
769 | ||
770 | if (!access_ok(VERIFY_READ, | |
771 | (char __user *)(uintptr_t)args->data_ptr, | |
772 | args->size)) | |
773 | return -EFAULT; | |
774 | ||
775 | ret = fault_in_pages_readable((char __user *)(uintptr_t)args->data_ptr, | |
776 | args->size); | |
777 | if (ret) | |
778 | return -EFAULT; | |
673a394b | 779 | |
fbd5a26d | 780 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 781 | if (ret) |
fbd5a26d | 782 | return ret; |
1d7cfea1 | 783 | |
05394f39 | 784 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 785 | if (&obj->base == NULL) { |
1d7cfea1 CW |
786 | ret = -ENOENT; |
787 | goto unlock; | |
fbd5a26d | 788 | } |
673a394b | 789 | |
7dcd2499 | 790 | /* Bounds check destination. */ |
05394f39 CW |
791 | if (args->offset > obj->base.size || |
792 | args->size > obj->base.size - args->offset) { | |
ce9d419d | 793 | ret = -EINVAL; |
35b62a89 | 794 | goto out; |
ce9d419d CW |
795 | } |
796 | ||
db53a302 CW |
797 | trace_i915_gem_object_pwrite(obj, args->offset, args->size); |
798 | ||
673a394b EA |
799 | /* We can only do the GTT pwrite on untiled buffers, as otherwise |
800 | * it would end up going through the fenced access, and we'll get | |
801 | * different detiling behavior between reading and writing. | |
802 | * pread/pwrite currently are reading and writing from the CPU | |
803 | * perspective, requiring manual detiling by the client. | |
804 | */ | |
5c0480f2 | 805 | if (obj->phys_obj) { |
fbd5a26d | 806 | ret = i915_gem_phys_pwrite(dev, obj, args, file); |
5c0480f2 DV |
807 | goto out; |
808 | } | |
809 | ||
810 | if (obj->gtt_space && | |
3ae53783 | 811 | obj->cache_level == I915_CACHE_NONE && |
5c0480f2 | 812 | obj->base.write_domain != I915_GEM_DOMAIN_CPU) { |
75e9e915 | 813 | ret = i915_gem_object_pin(obj, 0, true); |
fbd5a26d CW |
814 | if (ret) |
815 | goto out; | |
816 | ||
d9e86c0e CW |
817 | ret = i915_gem_object_set_to_gtt_domain(obj, true); |
818 | if (ret) | |
819 | goto out_unpin; | |
820 | ||
821 | ret = i915_gem_object_put_fence(obj); | |
fbd5a26d CW |
822 | if (ret) |
823 | goto out_unpin; | |
824 | ||
825 | ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file); | |
826 | if (ret == -EFAULT) | |
827 | ret = i915_gem_gtt_pwrite_slow(dev, obj, args, file); | |
828 | ||
829 | out_unpin: | |
830 | i915_gem_object_unpin(obj); | |
673a394b | 831 | |
5c0480f2 DV |
832 | if (ret != -EFAULT) |
833 | goto out; | |
834 | /* Fall through to the shmfs paths because the gtt paths might | |
835 | * fail with non-page-backed user pointers (e.g. gtt mappings | |
836 | * when moving data between textures). */ | |
fbd5a26d | 837 | } |
673a394b | 838 | |
5c0480f2 DV |
839 | ret = i915_gem_object_set_to_cpu_domain(obj, 1); |
840 | if (ret) | |
841 | goto out; | |
842 | ||
e244a443 | 843 | ret = i915_gem_shmem_pwrite(dev, obj, args, file); |
5c0480f2 | 844 | |
35b62a89 | 845 | out: |
05394f39 | 846 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 847 | unlock: |
fbd5a26d | 848 | mutex_unlock(&dev->struct_mutex); |
673a394b EA |
849 | return ret; |
850 | } | |
851 | ||
852 | /** | |
2ef7eeaa EA |
853 | * Called when user space prepares to use an object with the CPU, either |
854 | * through the mmap ioctl's mapping or a GTT mapping. | |
673a394b EA |
855 | */ |
856 | int | |
857 | i915_gem_set_domain_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 858 | struct drm_file *file) |
673a394b EA |
859 | { |
860 | struct drm_i915_gem_set_domain *args = data; | |
05394f39 | 861 | struct drm_i915_gem_object *obj; |
2ef7eeaa EA |
862 | uint32_t read_domains = args->read_domains; |
863 | uint32_t write_domain = args->write_domain; | |
673a394b EA |
864 | int ret; |
865 | ||
866 | if (!(dev->driver->driver_features & DRIVER_GEM)) | |
867 | return -ENODEV; | |
868 | ||
2ef7eeaa | 869 | /* Only handle setting domains to types used by the CPU. */ |
21d509e3 | 870 | if (write_domain & I915_GEM_GPU_DOMAINS) |
2ef7eeaa EA |
871 | return -EINVAL; |
872 | ||
21d509e3 | 873 | if (read_domains & I915_GEM_GPU_DOMAINS) |
2ef7eeaa EA |
874 | return -EINVAL; |
875 | ||
876 | /* Having something in the write domain implies it's in the read | |
877 | * domain, and only that read domain. Enforce that in the request. | |
878 | */ | |
879 | if (write_domain != 0 && read_domains != write_domain) | |
880 | return -EINVAL; | |
881 | ||
76c1dec1 | 882 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 883 | if (ret) |
76c1dec1 | 884 | return ret; |
1d7cfea1 | 885 | |
05394f39 | 886 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 887 | if (&obj->base == NULL) { |
1d7cfea1 CW |
888 | ret = -ENOENT; |
889 | goto unlock; | |
76c1dec1 | 890 | } |
673a394b | 891 | |
2ef7eeaa EA |
892 | if (read_domains & I915_GEM_DOMAIN_GTT) { |
893 | ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0); | |
02354392 EA |
894 | |
895 | /* Silently promote "you're not bound, there was nothing to do" | |
896 | * to success, since the client was just asking us to | |
897 | * make sure everything was done. | |
898 | */ | |
899 | if (ret == -EINVAL) | |
900 | ret = 0; | |
2ef7eeaa | 901 | } else { |
e47c68e9 | 902 | ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0); |
2ef7eeaa EA |
903 | } |
904 | ||
05394f39 | 905 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 906 | unlock: |
673a394b EA |
907 | mutex_unlock(&dev->struct_mutex); |
908 | return ret; | |
909 | } | |
910 | ||
911 | /** | |
912 | * Called when user space has done writes to this buffer | |
913 | */ | |
914 | int | |
915 | i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 916 | struct drm_file *file) |
673a394b EA |
917 | { |
918 | struct drm_i915_gem_sw_finish *args = data; | |
05394f39 | 919 | struct drm_i915_gem_object *obj; |
673a394b EA |
920 | int ret = 0; |
921 | ||
922 | if (!(dev->driver->driver_features & DRIVER_GEM)) | |
923 | return -ENODEV; | |
924 | ||
76c1dec1 | 925 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 926 | if (ret) |
76c1dec1 | 927 | return ret; |
1d7cfea1 | 928 | |
05394f39 | 929 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 930 | if (&obj->base == NULL) { |
1d7cfea1 CW |
931 | ret = -ENOENT; |
932 | goto unlock; | |
673a394b EA |
933 | } |
934 | ||
673a394b | 935 | /* Pinned buffers may be scanout, so flush the cache */ |
05394f39 | 936 | if (obj->pin_count) |
e47c68e9 EA |
937 | i915_gem_object_flush_cpu_write_domain(obj); |
938 | ||
05394f39 | 939 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 940 | unlock: |
673a394b EA |
941 | mutex_unlock(&dev->struct_mutex); |
942 | return ret; | |
943 | } | |
944 | ||
945 | /** | |
946 | * Maps the contents of an object, returning the address it is mapped | |
947 | * into. | |
948 | * | |
949 | * While the mapping holds a reference on the contents of the object, it doesn't | |
950 | * imply a ref on the object itself. | |
951 | */ | |
952 | int | |
953 | i915_gem_mmap_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 954 | struct drm_file *file) |
673a394b EA |
955 | { |
956 | struct drm_i915_gem_mmap *args = data; | |
957 | struct drm_gem_object *obj; | |
673a394b EA |
958 | unsigned long addr; |
959 | ||
960 | if (!(dev->driver->driver_features & DRIVER_GEM)) | |
961 | return -ENODEV; | |
962 | ||
05394f39 | 963 | obj = drm_gem_object_lookup(dev, file, args->handle); |
673a394b | 964 | if (obj == NULL) |
bf79cb91 | 965 | return -ENOENT; |
673a394b | 966 | |
673a394b EA |
967 | down_write(¤t->mm->mmap_sem); |
968 | addr = do_mmap(obj->filp, 0, args->size, | |
969 | PROT_READ | PROT_WRITE, MAP_SHARED, | |
970 | args->offset); | |
971 | up_write(¤t->mm->mmap_sem); | |
bc9025bd | 972 | drm_gem_object_unreference_unlocked(obj); |
673a394b EA |
973 | if (IS_ERR((void *)addr)) |
974 | return addr; | |
975 | ||
976 | args->addr_ptr = (uint64_t) addr; | |
977 | ||
978 | return 0; | |
979 | } | |
980 | ||
de151cf6 JB |
981 | /** |
982 | * i915_gem_fault - fault a page into the GTT | |
983 | * vma: VMA in question | |
984 | * vmf: fault info | |
985 | * | |
986 | * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped | |
987 | * from userspace. The fault handler takes care of binding the object to | |
988 | * the GTT (if needed), allocating and programming a fence register (again, | |
989 | * only if needed based on whether the old reg is still valid or the object | |
990 | * is tiled) and inserting a new PTE into the faulting process. | |
991 | * | |
992 | * Note that the faulting process may involve evicting existing objects | |
993 | * from the GTT and/or fence registers to make room. So performance may | |
994 | * suffer if the GTT working set is large or there are few fence registers | |
995 | * left. | |
996 | */ | |
997 | int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf) | |
998 | { | |
05394f39 CW |
999 | struct drm_i915_gem_object *obj = to_intel_bo(vma->vm_private_data); |
1000 | struct drm_device *dev = obj->base.dev; | |
7d1c4804 | 1001 | drm_i915_private_t *dev_priv = dev->dev_private; |
de151cf6 JB |
1002 | pgoff_t page_offset; |
1003 | unsigned long pfn; | |
1004 | int ret = 0; | |
0f973f27 | 1005 | bool write = !!(vmf->flags & FAULT_FLAG_WRITE); |
de151cf6 JB |
1006 | |
1007 | /* We don't use vmf->pgoff since that has the fake offset */ | |
1008 | page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >> | |
1009 | PAGE_SHIFT; | |
1010 | ||
d9bc7e9f CW |
1011 | ret = i915_mutex_lock_interruptible(dev); |
1012 | if (ret) | |
1013 | goto out; | |
a00b10c3 | 1014 | |
db53a302 CW |
1015 | trace_i915_gem_object_fault(obj, page_offset, true, write); |
1016 | ||
d9bc7e9f | 1017 | /* Now bind it into the GTT if needed */ |
919926ae CW |
1018 | if (!obj->map_and_fenceable) { |
1019 | ret = i915_gem_object_unbind(obj); | |
1020 | if (ret) | |
1021 | goto unlock; | |
a00b10c3 | 1022 | } |
05394f39 | 1023 | if (!obj->gtt_space) { |
75e9e915 | 1024 | ret = i915_gem_object_bind_to_gtt(obj, 0, true); |
c715089f CW |
1025 | if (ret) |
1026 | goto unlock; | |
de151cf6 | 1027 | |
e92d03bf EA |
1028 | ret = i915_gem_object_set_to_gtt_domain(obj, write); |
1029 | if (ret) | |
1030 | goto unlock; | |
1031 | } | |
4a684a41 | 1032 | |
74898d7e DV |
1033 | if (!obj->has_global_gtt_mapping) |
1034 | i915_gem_gtt_bind_object(obj, obj->cache_level); | |
1035 | ||
d9e86c0e CW |
1036 | if (obj->tiling_mode == I915_TILING_NONE) |
1037 | ret = i915_gem_object_put_fence(obj); | |
1038 | else | |
ce453d81 | 1039 | ret = i915_gem_object_get_fence(obj, NULL); |
d9e86c0e CW |
1040 | if (ret) |
1041 | goto unlock; | |
de151cf6 | 1042 | |
05394f39 CW |
1043 | if (i915_gem_object_is_inactive(obj)) |
1044 | list_move_tail(&obj->mm_list, &dev_priv->mm.inactive_list); | |
7d1c4804 | 1045 | |
6299f992 CW |
1046 | obj->fault_mappable = true; |
1047 | ||
05394f39 | 1048 | pfn = ((dev->agp->base + obj->gtt_offset) >> PAGE_SHIFT) + |
de151cf6 JB |
1049 | page_offset; |
1050 | ||
1051 | /* Finally, remap it using the new GTT offset */ | |
1052 | ret = vm_insert_pfn(vma, (unsigned long)vmf->virtual_address, pfn); | |
c715089f | 1053 | unlock: |
de151cf6 | 1054 | mutex_unlock(&dev->struct_mutex); |
d9bc7e9f | 1055 | out: |
de151cf6 | 1056 | switch (ret) { |
d9bc7e9f | 1057 | case -EIO: |
045e769a | 1058 | case -EAGAIN: |
d9bc7e9f CW |
1059 | /* Give the error handler a chance to run and move the |
1060 | * objects off the GPU active list. Next time we service the | |
1061 | * fault, we should be able to transition the page into the | |
1062 | * GTT without touching the GPU (and so avoid further | |
1063 | * EIO/EGAIN). If the GPU is wedged, then there is no issue | |
1064 | * with coherency, just lost writes. | |
1065 | */ | |
045e769a | 1066 | set_need_resched(); |
c715089f CW |
1067 | case 0: |
1068 | case -ERESTARTSYS: | |
bed636ab | 1069 | case -EINTR: |
c715089f | 1070 | return VM_FAULT_NOPAGE; |
de151cf6 | 1071 | case -ENOMEM: |
de151cf6 | 1072 | return VM_FAULT_OOM; |
de151cf6 | 1073 | default: |
c715089f | 1074 | return VM_FAULT_SIGBUS; |
de151cf6 JB |
1075 | } |
1076 | } | |
1077 | ||
901782b2 CW |
1078 | /** |
1079 | * i915_gem_release_mmap - remove physical page mappings | |
1080 | * @obj: obj in question | |
1081 | * | |
af901ca1 | 1082 | * Preserve the reservation of the mmapping with the DRM core code, but |
901782b2 CW |
1083 | * relinquish ownership of the pages back to the system. |
1084 | * | |
1085 | * It is vital that we remove the page mapping if we have mapped a tiled | |
1086 | * object through the GTT and then lose the fence register due to | |
1087 | * resource pressure. Similarly if the object has been moved out of the | |
1088 | * aperture, than pages mapped into userspace must be revoked. Removing the | |
1089 | * mapping will then trigger a page fault on the next user access, allowing | |
1090 | * fixup by i915_gem_fault(). | |
1091 | */ | |
d05ca301 | 1092 | void |
05394f39 | 1093 | i915_gem_release_mmap(struct drm_i915_gem_object *obj) |
901782b2 | 1094 | { |
6299f992 CW |
1095 | if (!obj->fault_mappable) |
1096 | return; | |
901782b2 | 1097 | |
f6e47884 CW |
1098 | if (obj->base.dev->dev_mapping) |
1099 | unmap_mapping_range(obj->base.dev->dev_mapping, | |
1100 | (loff_t)obj->base.map_list.hash.key<<PAGE_SHIFT, | |
1101 | obj->base.size, 1); | |
fb7d516a | 1102 | |
6299f992 | 1103 | obj->fault_mappable = false; |
901782b2 CW |
1104 | } |
1105 | ||
92b88aeb | 1106 | static uint32_t |
e28f8711 | 1107 | i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode) |
92b88aeb | 1108 | { |
e28f8711 | 1109 | uint32_t gtt_size; |
92b88aeb CW |
1110 | |
1111 | if (INTEL_INFO(dev)->gen >= 4 || | |
e28f8711 CW |
1112 | tiling_mode == I915_TILING_NONE) |
1113 | return size; | |
92b88aeb CW |
1114 | |
1115 | /* Previous chips need a power-of-two fence region when tiling */ | |
1116 | if (INTEL_INFO(dev)->gen == 3) | |
e28f8711 | 1117 | gtt_size = 1024*1024; |
92b88aeb | 1118 | else |
e28f8711 | 1119 | gtt_size = 512*1024; |
92b88aeb | 1120 | |
e28f8711 CW |
1121 | while (gtt_size < size) |
1122 | gtt_size <<= 1; | |
92b88aeb | 1123 | |
e28f8711 | 1124 | return gtt_size; |
92b88aeb CW |
1125 | } |
1126 | ||
de151cf6 JB |
1127 | /** |
1128 | * i915_gem_get_gtt_alignment - return required GTT alignment for an object | |
1129 | * @obj: object to check | |
1130 | * | |
1131 | * Return the required GTT alignment for an object, taking into account | |
5e783301 | 1132 | * potential fence register mapping. |
de151cf6 JB |
1133 | */ |
1134 | static uint32_t | |
e28f8711 CW |
1135 | i915_gem_get_gtt_alignment(struct drm_device *dev, |
1136 | uint32_t size, | |
1137 | int tiling_mode) | |
de151cf6 | 1138 | { |
de151cf6 JB |
1139 | /* |
1140 | * Minimum alignment is 4k (GTT page size), but might be greater | |
1141 | * if a fence register is needed for the object. | |
1142 | */ | |
a00b10c3 | 1143 | if (INTEL_INFO(dev)->gen >= 4 || |
e28f8711 | 1144 | tiling_mode == I915_TILING_NONE) |
de151cf6 JB |
1145 | return 4096; |
1146 | ||
a00b10c3 CW |
1147 | /* |
1148 | * Previous chips need to be aligned to the size of the smallest | |
1149 | * fence register that can contain the object. | |
1150 | */ | |
e28f8711 | 1151 | return i915_gem_get_gtt_size(dev, size, tiling_mode); |
a00b10c3 CW |
1152 | } |
1153 | ||
5e783301 DV |
1154 | /** |
1155 | * i915_gem_get_unfenced_gtt_alignment - return required GTT alignment for an | |
1156 | * unfenced object | |
e28f8711 CW |
1157 | * @dev: the device |
1158 | * @size: size of the object | |
1159 | * @tiling_mode: tiling mode of the object | |
5e783301 DV |
1160 | * |
1161 | * Return the required GTT alignment for an object, only taking into account | |
1162 | * unfenced tiled surface requirements. | |
1163 | */ | |
467cffba | 1164 | uint32_t |
e28f8711 CW |
1165 | i915_gem_get_unfenced_gtt_alignment(struct drm_device *dev, |
1166 | uint32_t size, | |
1167 | int tiling_mode) | |
5e783301 | 1168 | { |
5e783301 DV |
1169 | /* |
1170 | * Minimum alignment is 4k (GTT page size) for sane hw. | |
1171 | */ | |
1172 | if (INTEL_INFO(dev)->gen >= 4 || IS_G33(dev) || | |
e28f8711 | 1173 | tiling_mode == I915_TILING_NONE) |
5e783301 DV |
1174 | return 4096; |
1175 | ||
e28f8711 CW |
1176 | /* Previous hardware however needs to be aligned to a power-of-two |
1177 | * tile height. The simplest method for determining this is to reuse | |
1178 | * the power-of-tile object size. | |
5e783301 | 1179 | */ |
e28f8711 | 1180 | return i915_gem_get_gtt_size(dev, size, tiling_mode); |
5e783301 DV |
1181 | } |
1182 | ||
de151cf6 | 1183 | int |
ff72145b DA |
1184 | i915_gem_mmap_gtt(struct drm_file *file, |
1185 | struct drm_device *dev, | |
1186 | uint32_t handle, | |
1187 | uint64_t *offset) | |
de151cf6 | 1188 | { |
da761a6e | 1189 | struct drm_i915_private *dev_priv = dev->dev_private; |
05394f39 | 1190 | struct drm_i915_gem_object *obj; |
de151cf6 JB |
1191 | int ret; |
1192 | ||
1193 | if (!(dev->driver->driver_features & DRIVER_GEM)) | |
1194 | return -ENODEV; | |
1195 | ||
76c1dec1 | 1196 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 1197 | if (ret) |
76c1dec1 | 1198 | return ret; |
de151cf6 | 1199 | |
ff72145b | 1200 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle)); |
c8725226 | 1201 | if (&obj->base == NULL) { |
1d7cfea1 CW |
1202 | ret = -ENOENT; |
1203 | goto unlock; | |
1204 | } | |
de151cf6 | 1205 | |
05394f39 | 1206 | if (obj->base.size > dev_priv->mm.gtt_mappable_end) { |
da761a6e | 1207 | ret = -E2BIG; |
ff56b0bc | 1208 | goto out; |
da761a6e CW |
1209 | } |
1210 | ||
05394f39 | 1211 | if (obj->madv != I915_MADV_WILLNEED) { |
ab18282d | 1212 | DRM_ERROR("Attempting to mmap a purgeable buffer\n"); |
1d7cfea1 CW |
1213 | ret = -EINVAL; |
1214 | goto out; | |
ab18282d CW |
1215 | } |
1216 | ||
05394f39 | 1217 | if (!obj->base.map_list.map) { |
b464e9a2 | 1218 | ret = drm_gem_create_mmap_offset(&obj->base); |
1d7cfea1 CW |
1219 | if (ret) |
1220 | goto out; | |
de151cf6 JB |
1221 | } |
1222 | ||
ff72145b | 1223 | *offset = (u64)obj->base.map_list.hash.key << PAGE_SHIFT; |
de151cf6 | 1224 | |
1d7cfea1 | 1225 | out: |
05394f39 | 1226 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 1227 | unlock: |
de151cf6 | 1228 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 1229 | return ret; |
de151cf6 JB |
1230 | } |
1231 | ||
ff72145b DA |
1232 | /** |
1233 | * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing | |
1234 | * @dev: DRM device | |
1235 | * @data: GTT mapping ioctl data | |
1236 | * @file: GEM object info | |
1237 | * | |
1238 | * Simply returns the fake offset to userspace so it can mmap it. | |
1239 | * The mmap call will end up in drm_gem_mmap(), which will set things | |
1240 | * up so we can get faults in the handler above. | |
1241 | * | |
1242 | * The fault handler will take care of binding the object into the GTT | |
1243 | * (since it may have been evicted to make room for something), allocating | |
1244 | * a fence register, and mapping the appropriate aperture address into | |
1245 | * userspace. | |
1246 | */ | |
1247 | int | |
1248 | i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data, | |
1249 | struct drm_file *file) | |
1250 | { | |
1251 | struct drm_i915_gem_mmap_gtt *args = data; | |
1252 | ||
1253 | if (!(dev->driver->driver_features & DRIVER_GEM)) | |
1254 | return -ENODEV; | |
1255 | ||
1256 | return i915_gem_mmap_gtt(file, dev, args->handle, &args->offset); | |
1257 | } | |
1258 | ||
1259 | ||
e5281ccd | 1260 | static int |
05394f39 | 1261 | i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj, |
e5281ccd CW |
1262 | gfp_t gfpmask) |
1263 | { | |
e5281ccd CW |
1264 | int page_count, i; |
1265 | struct address_space *mapping; | |
1266 | struct inode *inode; | |
1267 | struct page *page; | |
1268 | ||
1269 | /* Get the list of pages out of our struct file. They'll be pinned | |
1270 | * at this point until we release them. | |
1271 | */ | |
05394f39 CW |
1272 | page_count = obj->base.size / PAGE_SIZE; |
1273 | BUG_ON(obj->pages != NULL); | |
1274 | obj->pages = drm_malloc_ab(page_count, sizeof(struct page *)); | |
1275 | if (obj->pages == NULL) | |
e5281ccd CW |
1276 | return -ENOMEM; |
1277 | ||
05394f39 | 1278 | inode = obj->base.filp->f_path.dentry->d_inode; |
e5281ccd | 1279 | mapping = inode->i_mapping; |
5949eac4 HD |
1280 | gfpmask |= mapping_gfp_mask(mapping); |
1281 | ||
e5281ccd | 1282 | for (i = 0; i < page_count; i++) { |
5949eac4 | 1283 | page = shmem_read_mapping_page_gfp(mapping, i, gfpmask); |
e5281ccd CW |
1284 | if (IS_ERR(page)) |
1285 | goto err_pages; | |
1286 | ||
05394f39 | 1287 | obj->pages[i] = page; |
e5281ccd CW |
1288 | } |
1289 | ||
6dacfd2f | 1290 | if (i915_gem_object_needs_bit17_swizzle(obj)) |
e5281ccd CW |
1291 | i915_gem_object_do_bit_17_swizzle(obj); |
1292 | ||
1293 | return 0; | |
1294 | ||
1295 | err_pages: | |
1296 | while (i--) | |
05394f39 | 1297 | page_cache_release(obj->pages[i]); |
e5281ccd | 1298 | |
05394f39 CW |
1299 | drm_free_large(obj->pages); |
1300 | obj->pages = NULL; | |
e5281ccd CW |
1301 | return PTR_ERR(page); |
1302 | } | |
1303 | ||
5cdf5881 | 1304 | static void |
05394f39 | 1305 | i915_gem_object_put_pages_gtt(struct drm_i915_gem_object *obj) |
673a394b | 1306 | { |
05394f39 | 1307 | int page_count = obj->base.size / PAGE_SIZE; |
673a394b EA |
1308 | int i; |
1309 | ||
05394f39 | 1310 | BUG_ON(obj->madv == __I915_MADV_PURGED); |
673a394b | 1311 | |
6dacfd2f | 1312 | if (i915_gem_object_needs_bit17_swizzle(obj)) |
280b713b EA |
1313 | i915_gem_object_save_bit_17_swizzle(obj); |
1314 | ||
05394f39 CW |
1315 | if (obj->madv == I915_MADV_DONTNEED) |
1316 | obj->dirty = 0; | |
3ef94daa CW |
1317 | |
1318 | for (i = 0; i < page_count; i++) { | |
05394f39 CW |
1319 | if (obj->dirty) |
1320 | set_page_dirty(obj->pages[i]); | |
3ef94daa | 1321 | |
05394f39 CW |
1322 | if (obj->madv == I915_MADV_WILLNEED) |
1323 | mark_page_accessed(obj->pages[i]); | |
3ef94daa | 1324 | |
05394f39 | 1325 | page_cache_release(obj->pages[i]); |
3ef94daa | 1326 | } |
05394f39 | 1327 | obj->dirty = 0; |
673a394b | 1328 | |
05394f39 CW |
1329 | drm_free_large(obj->pages); |
1330 | obj->pages = NULL; | |
673a394b EA |
1331 | } |
1332 | ||
54cf91dc | 1333 | void |
05394f39 | 1334 | i915_gem_object_move_to_active(struct drm_i915_gem_object *obj, |
1ec14ad3 CW |
1335 | struct intel_ring_buffer *ring, |
1336 | u32 seqno) | |
673a394b | 1337 | { |
05394f39 | 1338 | struct drm_device *dev = obj->base.dev; |
69dc4987 | 1339 | struct drm_i915_private *dev_priv = dev->dev_private; |
617dbe27 | 1340 | |
852835f3 | 1341 | BUG_ON(ring == NULL); |
05394f39 | 1342 | obj->ring = ring; |
673a394b EA |
1343 | |
1344 | /* Add a reference if we're newly entering the active list. */ | |
05394f39 CW |
1345 | if (!obj->active) { |
1346 | drm_gem_object_reference(&obj->base); | |
1347 | obj->active = 1; | |
673a394b | 1348 | } |
e35a41de | 1349 | |
673a394b | 1350 | /* Move from whatever list we were on to the tail of execution. */ |
05394f39 CW |
1351 | list_move_tail(&obj->mm_list, &dev_priv->mm.active_list); |
1352 | list_move_tail(&obj->ring_list, &ring->active_list); | |
caea7476 | 1353 | |
05394f39 | 1354 | obj->last_rendering_seqno = seqno; |
caea7476 CW |
1355 | if (obj->fenced_gpu_access) { |
1356 | struct drm_i915_fence_reg *reg; | |
1357 | ||
1358 | BUG_ON(obj->fence_reg == I915_FENCE_REG_NONE); | |
1359 | ||
1360 | obj->last_fenced_seqno = seqno; | |
1361 | obj->last_fenced_ring = ring; | |
1362 | ||
1363 | reg = &dev_priv->fence_regs[obj->fence_reg]; | |
1364 | list_move_tail(®->lru_list, &dev_priv->mm.fence_list); | |
1365 | } | |
1366 | } | |
1367 | ||
1368 | static void | |
1369 | i915_gem_object_move_off_active(struct drm_i915_gem_object *obj) | |
1370 | { | |
1371 | list_del_init(&obj->ring_list); | |
1372 | obj->last_rendering_seqno = 0; | |
673a394b EA |
1373 | } |
1374 | ||
ce44b0ea | 1375 | static void |
05394f39 | 1376 | i915_gem_object_move_to_flushing(struct drm_i915_gem_object *obj) |
ce44b0ea | 1377 | { |
05394f39 | 1378 | struct drm_device *dev = obj->base.dev; |
ce44b0ea | 1379 | drm_i915_private_t *dev_priv = dev->dev_private; |
ce44b0ea | 1380 | |
05394f39 CW |
1381 | BUG_ON(!obj->active); |
1382 | list_move_tail(&obj->mm_list, &dev_priv->mm.flushing_list); | |
caea7476 CW |
1383 | |
1384 | i915_gem_object_move_off_active(obj); | |
1385 | } | |
1386 | ||
1387 | static void | |
1388 | i915_gem_object_move_to_inactive(struct drm_i915_gem_object *obj) | |
1389 | { | |
1390 | struct drm_device *dev = obj->base.dev; | |
1391 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1392 | ||
1393 | if (obj->pin_count != 0) | |
1394 | list_move_tail(&obj->mm_list, &dev_priv->mm.pinned_list); | |
1395 | else | |
1396 | list_move_tail(&obj->mm_list, &dev_priv->mm.inactive_list); | |
1397 | ||
1398 | BUG_ON(!list_empty(&obj->gpu_write_list)); | |
1399 | BUG_ON(!obj->active); | |
1400 | obj->ring = NULL; | |
1401 | ||
1402 | i915_gem_object_move_off_active(obj); | |
1403 | obj->fenced_gpu_access = false; | |
caea7476 CW |
1404 | |
1405 | obj->active = 0; | |
87ca9c8a | 1406 | obj->pending_gpu_write = false; |
caea7476 CW |
1407 | drm_gem_object_unreference(&obj->base); |
1408 | ||
1409 | WARN_ON(i915_verify_lists(dev)); | |
ce44b0ea | 1410 | } |
673a394b | 1411 | |
963b4836 CW |
1412 | /* Immediately discard the backing storage */ |
1413 | static void | |
05394f39 | 1414 | i915_gem_object_truncate(struct drm_i915_gem_object *obj) |
963b4836 | 1415 | { |
bb6baf76 | 1416 | struct inode *inode; |
963b4836 | 1417 | |
ae9fed6b CW |
1418 | /* Our goal here is to return as much of the memory as |
1419 | * is possible back to the system as we are called from OOM. | |
1420 | * To do this we must instruct the shmfs to drop all of its | |
e2377fe0 | 1421 | * backing pages, *now*. |
ae9fed6b | 1422 | */ |
05394f39 | 1423 | inode = obj->base.filp->f_path.dentry->d_inode; |
e2377fe0 | 1424 | shmem_truncate_range(inode, 0, (loff_t)-1); |
bb6baf76 | 1425 | |
a14917ee CW |
1426 | if (obj->base.map_list.map) |
1427 | drm_gem_free_mmap_offset(&obj->base); | |
1428 | ||
05394f39 | 1429 | obj->madv = __I915_MADV_PURGED; |
963b4836 CW |
1430 | } |
1431 | ||
1432 | static inline int | |
05394f39 | 1433 | i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj) |
963b4836 | 1434 | { |
05394f39 | 1435 | return obj->madv == I915_MADV_DONTNEED; |
963b4836 CW |
1436 | } |
1437 | ||
63560396 | 1438 | static void |
db53a302 CW |
1439 | i915_gem_process_flushing_list(struct intel_ring_buffer *ring, |
1440 | uint32_t flush_domains) | |
63560396 | 1441 | { |
05394f39 | 1442 | struct drm_i915_gem_object *obj, *next; |
63560396 | 1443 | |
05394f39 | 1444 | list_for_each_entry_safe(obj, next, |
64193406 | 1445 | &ring->gpu_write_list, |
63560396 | 1446 | gpu_write_list) { |
05394f39 CW |
1447 | if (obj->base.write_domain & flush_domains) { |
1448 | uint32_t old_write_domain = obj->base.write_domain; | |
63560396 | 1449 | |
05394f39 CW |
1450 | obj->base.write_domain = 0; |
1451 | list_del_init(&obj->gpu_write_list); | |
1ec14ad3 | 1452 | i915_gem_object_move_to_active(obj, ring, |
db53a302 | 1453 | i915_gem_next_request_seqno(ring)); |
63560396 | 1454 | |
63560396 | 1455 | trace_i915_gem_object_change_domain(obj, |
05394f39 | 1456 | obj->base.read_domains, |
63560396 DV |
1457 | old_write_domain); |
1458 | } | |
1459 | } | |
1460 | } | |
8187a2b7 | 1461 | |
53d227f2 DV |
1462 | static u32 |
1463 | i915_gem_get_seqno(struct drm_device *dev) | |
1464 | { | |
1465 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1466 | u32 seqno = dev_priv->next_seqno; | |
1467 | ||
1468 | /* reserve 0 for non-seqno */ | |
1469 | if (++dev_priv->next_seqno == 0) | |
1470 | dev_priv->next_seqno = 1; | |
1471 | ||
1472 | return seqno; | |
1473 | } | |
1474 | ||
1475 | u32 | |
1476 | i915_gem_next_request_seqno(struct intel_ring_buffer *ring) | |
1477 | { | |
1478 | if (ring->outstanding_lazy_request == 0) | |
1479 | ring->outstanding_lazy_request = i915_gem_get_seqno(ring->dev); | |
1480 | ||
1481 | return ring->outstanding_lazy_request; | |
1482 | } | |
1483 | ||
3cce469c | 1484 | int |
db53a302 | 1485 | i915_add_request(struct intel_ring_buffer *ring, |
f787a5f5 | 1486 | struct drm_file *file, |
db53a302 | 1487 | struct drm_i915_gem_request *request) |
673a394b | 1488 | { |
db53a302 | 1489 | drm_i915_private_t *dev_priv = ring->dev->dev_private; |
673a394b | 1490 | uint32_t seqno; |
a71d8d94 | 1491 | u32 request_ring_position; |
673a394b | 1492 | int was_empty; |
3cce469c CW |
1493 | int ret; |
1494 | ||
1495 | BUG_ON(request == NULL); | |
53d227f2 | 1496 | seqno = i915_gem_next_request_seqno(ring); |
673a394b | 1497 | |
a71d8d94 CW |
1498 | /* Record the position of the start of the request so that |
1499 | * should we detect the updated seqno part-way through the | |
1500 | * GPU processing the request, we never over-estimate the | |
1501 | * position of the head. | |
1502 | */ | |
1503 | request_ring_position = intel_ring_get_tail(ring); | |
1504 | ||
3cce469c CW |
1505 | ret = ring->add_request(ring, &seqno); |
1506 | if (ret) | |
1507 | return ret; | |
673a394b | 1508 | |
db53a302 | 1509 | trace_i915_gem_request_add(ring, seqno); |
673a394b EA |
1510 | |
1511 | request->seqno = seqno; | |
852835f3 | 1512 | request->ring = ring; |
a71d8d94 | 1513 | request->tail = request_ring_position; |
673a394b | 1514 | request->emitted_jiffies = jiffies; |
852835f3 ZN |
1515 | was_empty = list_empty(&ring->request_list); |
1516 | list_add_tail(&request->list, &ring->request_list); | |
1517 | ||
db53a302 CW |
1518 | if (file) { |
1519 | struct drm_i915_file_private *file_priv = file->driver_priv; | |
1520 | ||
1c25595f | 1521 | spin_lock(&file_priv->mm.lock); |
f787a5f5 | 1522 | request->file_priv = file_priv; |
b962442e | 1523 | list_add_tail(&request->client_list, |
f787a5f5 | 1524 | &file_priv->mm.request_list); |
1c25595f | 1525 | spin_unlock(&file_priv->mm.lock); |
b962442e | 1526 | } |
673a394b | 1527 | |
5391d0cf | 1528 | ring->outstanding_lazy_request = 0; |
db53a302 | 1529 | |
f65d9421 | 1530 | if (!dev_priv->mm.suspended) { |
3e0dc6b0 BW |
1531 | if (i915_enable_hangcheck) { |
1532 | mod_timer(&dev_priv->hangcheck_timer, | |
1533 | jiffies + | |
1534 | msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)); | |
1535 | } | |
f65d9421 | 1536 | if (was_empty) |
b3b079db CW |
1537 | queue_delayed_work(dev_priv->wq, |
1538 | &dev_priv->mm.retire_work, HZ); | |
f65d9421 | 1539 | } |
3cce469c | 1540 | return 0; |
673a394b EA |
1541 | } |
1542 | ||
f787a5f5 CW |
1543 | static inline void |
1544 | i915_gem_request_remove_from_client(struct drm_i915_gem_request *request) | |
673a394b | 1545 | { |
1c25595f | 1546 | struct drm_i915_file_private *file_priv = request->file_priv; |
673a394b | 1547 | |
1c25595f CW |
1548 | if (!file_priv) |
1549 | return; | |
1c5d22f7 | 1550 | |
1c25595f | 1551 | spin_lock(&file_priv->mm.lock); |
09bfa517 HRK |
1552 | if (request->file_priv) { |
1553 | list_del(&request->client_list); | |
1554 | request->file_priv = NULL; | |
1555 | } | |
1c25595f | 1556 | spin_unlock(&file_priv->mm.lock); |
673a394b | 1557 | } |
673a394b | 1558 | |
dfaae392 CW |
1559 | static void i915_gem_reset_ring_lists(struct drm_i915_private *dev_priv, |
1560 | struct intel_ring_buffer *ring) | |
9375e446 | 1561 | { |
dfaae392 CW |
1562 | while (!list_empty(&ring->request_list)) { |
1563 | struct drm_i915_gem_request *request; | |
673a394b | 1564 | |
dfaae392 CW |
1565 | request = list_first_entry(&ring->request_list, |
1566 | struct drm_i915_gem_request, | |
1567 | list); | |
de151cf6 | 1568 | |
dfaae392 | 1569 | list_del(&request->list); |
f787a5f5 | 1570 | i915_gem_request_remove_from_client(request); |
dfaae392 CW |
1571 | kfree(request); |
1572 | } | |
673a394b | 1573 | |
dfaae392 | 1574 | while (!list_empty(&ring->active_list)) { |
05394f39 | 1575 | struct drm_i915_gem_object *obj; |
9375e446 | 1576 | |
05394f39 CW |
1577 | obj = list_first_entry(&ring->active_list, |
1578 | struct drm_i915_gem_object, | |
1579 | ring_list); | |
9375e446 | 1580 | |
05394f39 CW |
1581 | obj->base.write_domain = 0; |
1582 | list_del_init(&obj->gpu_write_list); | |
1583 | i915_gem_object_move_to_inactive(obj); | |
673a394b EA |
1584 | } |
1585 | } | |
1586 | ||
312817a3 CW |
1587 | static void i915_gem_reset_fences(struct drm_device *dev) |
1588 | { | |
1589 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1590 | int i; | |
1591 | ||
4b9de737 | 1592 | for (i = 0; i < dev_priv->num_fence_regs; i++) { |
312817a3 | 1593 | struct drm_i915_fence_reg *reg = &dev_priv->fence_regs[i]; |
7d2cb39c CW |
1594 | struct drm_i915_gem_object *obj = reg->obj; |
1595 | ||
1596 | if (!obj) | |
1597 | continue; | |
1598 | ||
1599 | if (obj->tiling_mode) | |
1600 | i915_gem_release_mmap(obj); | |
1601 | ||
d9e86c0e CW |
1602 | reg->obj->fence_reg = I915_FENCE_REG_NONE; |
1603 | reg->obj->fenced_gpu_access = false; | |
1604 | reg->obj->last_fenced_seqno = 0; | |
1605 | reg->obj->last_fenced_ring = NULL; | |
1606 | i915_gem_clear_fence_reg(dev, reg); | |
312817a3 CW |
1607 | } |
1608 | } | |
1609 | ||
069efc1d | 1610 | void i915_gem_reset(struct drm_device *dev) |
673a394b | 1611 | { |
77f01230 | 1612 | struct drm_i915_private *dev_priv = dev->dev_private; |
05394f39 | 1613 | struct drm_i915_gem_object *obj; |
1ec14ad3 | 1614 | int i; |
673a394b | 1615 | |
1ec14ad3 CW |
1616 | for (i = 0; i < I915_NUM_RINGS; i++) |
1617 | i915_gem_reset_ring_lists(dev_priv, &dev_priv->ring[i]); | |
dfaae392 CW |
1618 | |
1619 | /* Remove anything from the flushing lists. The GPU cache is likely | |
1620 | * to be lost on reset along with the data, so simply move the | |
1621 | * lost bo to the inactive list. | |
1622 | */ | |
1623 | while (!list_empty(&dev_priv->mm.flushing_list)) { | |
0206e353 | 1624 | obj = list_first_entry(&dev_priv->mm.flushing_list, |
05394f39 CW |
1625 | struct drm_i915_gem_object, |
1626 | mm_list); | |
dfaae392 | 1627 | |
05394f39 CW |
1628 | obj->base.write_domain = 0; |
1629 | list_del_init(&obj->gpu_write_list); | |
1630 | i915_gem_object_move_to_inactive(obj); | |
dfaae392 CW |
1631 | } |
1632 | ||
1633 | /* Move everything out of the GPU domains to ensure we do any | |
1634 | * necessary invalidation upon reuse. | |
1635 | */ | |
05394f39 | 1636 | list_for_each_entry(obj, |
77f01230 | 1637 | &dev_priv->mm.inactive_list, |
69dc4987 | 1638 | mm_list) |
77f01230 | 1639 | { |
05394f39 | 1640 | obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS; |
77f01230 | 1641 | } |
069efc1d CW |
1642 | |
1643 | /* The fence registers are invalidated so clear them out */ | |
312817a3 | 1644 | i915_gem_reset_fences(dev); |
673a394b EA |
1645 | } |
1646 | ||
1647 | /** | |
1648 | * This function clears the request list as sequence numbers are passed. | |
1649 | */ | |
a71d8d94 | 1650 | void |
db53a302 | 1651 | i915_gem_retire_requests_ring(struct intel_ring_buffer *ring) |
673a394b | 1652 | { |
673a394b | 1653 | uint32_t seqno; |
1ec14ad3 | 1654 | int i; |
673a394b | 1655 | |
db53a302 | 1656 | if (list_empty(&ring->request_list)) |
6c0594a3 KW |
1657 | return; |
1658 | ||
db53a302 | 1659 | WARN_ON(i915_verify_lists(ring->dev)); |
673a394b | 1660 | |
78501eac | 1661 | seqno = ring->get_seqno(ring); |
1ec14ad3 | 1662 | |
076e2c0e | 1663 | for (i = 0; i < ARRAY_SIZE(ring->sync_seqno); i++) |
1ec14ad3 CW |
1664 | if (seqno >= ring->sync_seqno[i]) |
1665 | ring->sync_seqno[i] = 0; | |
1666 | ||
852835f3 | 1667 | while (!list_empty(&ring->request_list)) { |
673a394b | 1668 | struct drm_i915_gem_request *request; |
673a394b | 1669 | |
852835f3 | 1670 | request = list_first_entry(&ring->request_list, |
673a394b EA |
1671 | struct drm_i915_gem_request, |
1672 | list); | |
673a394b | 1673 | |
dfaae392 | 1674 | if (!i915_seqno_passed(seqno, request->seqno)) |
b84d5f0c CW |
1675 | break; |
1676 | ||
db53a302 | 1677 | trace_i915_gem_request_retire(ring, request->seqno); |
a71d8d94 CW |
1678 | /* We know the GPU must have read the request to have |
1679 | * sent us the seqno + interrupt, so use the position | |
1680 | * of tail of the request to update the last known position | |
1681 | * of the GPU head. | |
1682 | */ | |
1683 | ring->last_retired_head = request->tail; | |
b84d5f0c CW |
1684 | |
1685 | list_del(&request->list); | |
f787a5f5 | 1686 | i915_gem_request_remove_from_client(request); |
b84d5f0c CW |
1687 | kfree(request); |
1688 | } | |
673a394b | 1689 | |
b84d5f0c CW |
1690 | /* Move any buffers on the active list that are no longer referenced |
1691 | * by the ringbuffer to the flushing/inactive lists as appropriate. | |
1692 | */ | |
1693 | while (!list_empty(&ring->active_list)) { | |
05394f39 | 1694 | struct drm_i915_gem_object *obj; |
b84d5f0c | 1695 | |
0206e353 | 1696 | obj = list_first_entry(&ring->active_list, |
05394f39 CW |
1697 | struct drm_i915_gem_object, |
1698 | ring_list); | |
673a394b | 1699 | |
05394f39 | 1700 | if (!i915_seqno_passed(seqno, obj->last_rendering_seqno)) |
673a394b | 1701 | break; |
b84d5f0c | 1702 | |
05394f39 | 1703 | if (obj->base.write_domain != 0) |
b84d5f0c CW |
1704 | i915_gem_object_move_to_flushing(obj); |
1705 | else | |
1706 | i915_gem_object_move_to_inactive(obj); | |
673a394b | 1707 | } |
9d34e5db | 1708 | |
db53a302 CW |
1709 | if (unlikely(ring->trace_irq_seqno && |
1710 | i915_seqno_passed(seqno, ring->trace_irq_seqno))) { | |
1ec14ad3 | 1711 | ring->irq_put(ring); |
db53a302 | 1712 | ring->trace_irq_seqno = 0; |
9d34e5db | 1713 | } |
23bc5982 | 1714 | |
db53a302 | 1715 | WARN_ON(i915_verify_lists(ring->dev)); |
673a394b EA |
1716 | } |
1717 | ||
b09a1fec CW |
1718 | void |
1719 | i915_gem_retire_requests(struct drm_device *dev) | |
1720 | { | |
1721 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1ec14ad3 | 1722 | int i; |
b09a1fec | 1723 | |
be72615b | 1724 | if (!list_empty(&dev_priv->mm.deferred_free_list)) { |
05394f39 | 1725 | struct drm_i915_gem_object *obj, *next; |
be72615b CW |
1726 | |
1727 | /* We must be careful that during unbind() we do not | |
1728 | * accidentally infinitely recurse into retire requests. | |
1729 | * Currently: | |
1730 | * retire -> free -> unbind -> wait -> retire_ring | |
1731 | */ | |
05394f39 | 1732 | list_for_each_entry_safe(obj, next, |
be72615b | 1733 | &dev_priv->mm.deferred_free_list, |
69dc4987 | 1734 | mm_list) |
05394f39 | 1735 | i915_gem_free_object_tail(obj); |
be72615b CW |
1736 | } |
1737 | ||
1ec14ad3 | 1738 | for (i = 0; i < I915_NUM_RINGS; i++) |
db53a302 | 1739 | i915_gem_retire_requests_ring(&dev_priv->ring[i]); |
b09a1fec CW |
1740 | } |
1741 | ||
75ef9da2 | 1742 | static void |
673a394b EA |
1743 | i915_gem_retire_work_handler(struct work_struct *work) |
1744 | { | |
1745 | drm_i915_private_t *dev_priv; | |
1746 | struct drm_device *dev; | |
0a58705b CW |
1747 | bool idle; |
1748 | int i; | |
673a394b EA |
1749 | |
1750 | dev_priv = container_of(work, drm_i915_private_t, | |
1751 | mm.retire_work.work); | |
1752 | dev = dev_priv->dev; | |
1753 | ||
891b48cf CW |
1754 | /* Come back later if the device is busy... */ |
1755 | if (!mutex_trylock(&dev->struct_mutex)) { | |
1756 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ); | |
1757 | return; | |
1758 | } | |
1759 | ||
b09a1fec | 1760 | i915_gem_retire_requests(dev); |
d1b851fc | 1761 | |
0a58705b CW |
1762 | /* Send a periodic flush down the ring so we don't hold onto GEM |
1763 | * objects indefinitely. | |
1764 | */ | |
1765 | idle = true; | |
1766 | for (i = 0; i < I915_NUM_RINGS; i++) { | |
1767 | struct intel_ring_buffer *ring = &dev_priv->ring[i]; | |
1768 | ||
1769 | if (!list_empty(&ring->gpu_write_list)) { | |
1770 | struct drm_i915_gem_request *request; | |
1771 | int ret; | |
1772 | ||
db53a302 CW |
1773 | ret = i915_gem_flush_ring(ring, |
1774 | 0, I915_GEM_GPU_DOMAINS); | |
0a58705b CW |
1775 | request = kzalloc(sizeof(*request), GFP_KERNEL); |
1776 | if (ret || request == NULL || | |
db53a302 | 1777 | i915_add_request(ring, NULL, request)) |
0a58705b CW |
1778 | kfree(request); |
1779 | } | |
1780 | ||
1781 | idle &= list_empty(&ring->request_list); | |
1782 | } | |
1783 | ||
1784 | if (!dev_priv->mm.suspended && !idle) | |
9c9fe1f8 | 1785 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ); |
0a58705b | 1786 | |
673a394b EA |
1787 | mutex_unlock(&dev->struct_mutex); |
1788 | } | |
1789 | ||
db53a302 CW |
1790 | /** |
1791 | * Waits for a sequence number to be signaled, and cleans up the | |
1792 | * request and object lists appropriately for that event. | |
1793 | */ | |
5a5a0c64 | 1794 | int |
db53a302 | 1795 | i915_wait_request(struct intel_ring_buffer *ring, |
b93f9cf1 BW |
1796 | uint32_t seqno, |
1797 | bool do_retire) | |
673a394b | 1798 | { |
db53a302 | 1799 | drm_i915_private_t *dev_priv = ring->dev->dev_private; |
802c7eb6 | 1800 | u32 ier; |
673a394b EA |
1801 | int ret = 0; |
1802 | ||
1803 | BUG_ON(seqno == 0); | |
1804 | ||
d9bc7e9f CW |
1805 | if (atomic_read(&dev_priv->mm.wedged)) { |
1806 | struct completion *x = &dev_priv->error_completion; | |
1807 | bool recovery_complete; | |
1808 | unsigned long flags; | |
1809 | ||
1810 | /* Give the error handler a chance to run. */ | |
1811 | spin_lock_irqsave(&x->wait.lock, flags); | |
1812 | recovery_complete = x->done > 0; | |
1813 | spin_unlock_irqrestore(&x->wait.lock, flags); | |
1814 | ||
1815 | return recovery_complete ? -EIO : -EAGAIN; | |
1816 | } | |
30dbf0c0 | 1817 | |
5d97eb69 | 1818 | if (seqno == ring->outstanding_lazy_request) { |
3cce469c CW |
1819 | struct drm_i915_gem_request *request; |
1820 | ||
1821 | request = kzalloc(sizeof(*request), GFP_KERNEL); | |
1822 | if (request == NULL) | |
e35a41de | 1823 | return -ENOMEM; |
3cce469c | 1824 | |
db53a302 | 1825 | ret = i915_add_request(ring, NULL, request); |
3cce469c CW |
1826 | if (ret) { |
1827 | kfree(request); | |
1828 | return ret; | |
1829 | } | |
1830 | ||
1831 | seqno = request->seqno; | |
e35a41de | 1832 | } |
ffed1d09 | 1833 | |
78501eac | 1834 | if (!i915_seqno_passed(ring->get_seqno(ring), seqno)) { |
db53a302 | 1835 | if (HAS_PCH_SPLIT(ring->dev)) |
036a4a7d ZW |
1836 | ier = I915_READ(DEIER) | I915_READ(GTIER); |
1837 | else | |
1838 | ier = I915_READ(IER); | |
802c7eb6 JB |
1839 | if (!ier) { |
1840 | DRM_ERROR("something (likely vbetool) disabled " | |
1841 | "interrupts, re-enabling\n"); | |
f01c22fd CW |
1842 | ring->dev->driver->irq_preinstall(ring->dev); |
1843 | ring->dev->driver->irq_postinstall(ring->dev); | |
802c7eb6 JB |
1844 | } |
1845 | ||
db53a302 | 1846 | trace_i915_gem_request_wait_begin(ring, seqno); |
1c5d22f7 | 1847 | |
b2223497 | 1848 | ring->waiting_seqno = seqno; |
b13c2b96 | 1849 | if (ring->irq_get(ring)) { |
ce453d81 | 1850 | if (dev_priv->mm.interruptible) |
b13c2b96 CW |
1851 | ret = wait_event_interruptible(ring->irq_queue, |
1852 | i915_seqno_passed(ring->get_seqno(ring), seqno) | |
1853 | || atomic_read(&dev_priv->mm.wedged)); | |
1854 | else | |
1855 | wait_event(ring->irq_queue, | |
1856 | i915_seqno_passed(ring->get_seqno(ring), seqno) | |
1857 | || atomic_read(&dev_priv->mm.wedged)); | |
1858 | ||
1859 | ring->irq_put(ring); | |
e959b5db EA |
1860 | } else if (wait_for_atomic(i915_seqno_passed(ring->get_seqno(ring), |
1861 | seqno) || | |
1862 | atomic_read(&dev_priv->mm.wedged), 3000)) | |
b5ba177d | 1863 | ret = -EBUSY; |
b2223497 | 1864 | ring->waiting_seqno = 0; |
1c5d22f7 | 1865 | |
db53a302 | 1866 | trace_i915_gem_request_wait_end(ring, seqno); |
673a394b | 1867 | } |
ba1234d1 | 1868 | if (atomic_read(&dev_priv->mm.wedged)) |
30dbf0c0 | 1869 | ret = -EAGAIN; |
673a394b | 1870 | |
673a394b EA |
1871 | /* Directly dispatch request retiring. While we have the work queue |
1872 | * to handle this, the waiter on a request often wants an associated | |
1873 | * buffer to have made it to the inactive list, and we would need | |
1874 | * a separate wait queue to handle that. | |
1875 | */ | |
b93f9cf1 | 1876 | if (ret == 0 && do_retire) |
db53a302 | 1877 | i915_gem_retire_requests_ring(ring); |
673a394b EA |
1878 | |
1879 | return ret; | |
1880 | } | |
1881 | ||
673a394b EA |
1882 | /** |
1883 | * Ensures that all rendering to the object has completed and the object is | |
1884 | * safe to unbind from the GTT or access from the CPU. | |
1885 | */ | |
54cf91dc | 1886 | int |
ce453d81 | 1887 | i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj) |
673a394b | 1888 | { |
673a394b EA |
1889 | int ret; |
1890 | ||
e47c68e9 EA |
1891 | /* This function only exists to support waiting for existing rendering, |
1892 | * not for emitting required flushes. | |
673a394b | 1893 | */ |
05394f39 | 1894 | BUG_ON((obj->base.write_domain & I915_GEM_GPU_DOMAINS) != 0); |
673a394b EA |
1895 | |
1896 | /* If there is rendering queued on the buffer being evicted, wait for | |
1897 | * it. | |
1898 | */ | |
05394f39 | 1899 | if (obj->active) { |
b93f9cf1 BW |
1900 | ret = i915_wait_request(obj->ring, obj->last_rendering_seqno, |
1901 | true); | |
2cf34d7b | 1902 | if (ret) |
673a394b EA |
1903 | return ret; |
1904 | } | |
1905 | ||
1906 | return 0; | |
1907 | } | |
1908 | ||
b5ffc9bc CW |
1909 | static void i915_gem_object_finish_gtt(struct drm_i915_gem_object *obj) |
1910 | { | |
1911 | u32 old_write_domain, old_read_domains; | |
1912 | ||
b5ffc9bc CW |
1913 | /* Act a barrier for all accesses through the GTT */ |
1914 | mb(); | |
1915 | ||
1916 | /* Force a pagefault for domain tracking on next user access */ | |
1917 | i915_gem_release_mmap(obj); | |
1918 | ||
b97c3d9c KP |
1919 | if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0) |
1920 | return; | |
1921 | ||
b5ffc9bc CW |
1922 | old_read_domains = obj->base.read_domains; |
1923 | old_write_domain = obj->base.write_domain; | |
1924 | ||
1925 | obj->base.read_domains &= ~I915_GEM_DOMAIN_GTT; | |
1926 | obj->base.write_domain &= ~I915_GEM_DOMAIN_GTT; | |
1927 | ||
1928 | trace_i915_gem_object_change_domain(obj, | |
1929 | old_read_domains, | |
1930 | old_write_domain); | |
1931 | } | |
1932 | ||
673a394b EA |
1933 | /** |
1934 | * Unbinds an object from the GTT aperture. | |
1935 | */ | |
0f973f27 | 1936 | int |
05394f39 | 1937 | i915_gem_object_unbind(struct drm_i915_gem_object *obj) |
673a394b | 1938 | { |
7bddb01f | 1939 | drm_i915_private_t *dev_priv = obj->base.dev->dev_private; |
673a394b EA |
1940 | int ret = 0; |
1941 | ||
05394f39 | 1942 | if (obj->gtt_space == NULL) |
673a394b EA |
1943 | return 0; |
1944 | ||
05394f39 | 1945 | if (obj->pin_count != 0) { |
673a394b EA |
1946 | DRM_ERROR("Attempting to unbind pinned buffer\n"); |
1947 | return -EINVAL; | |
1948 | } | |
1949 | ||
a8198eea CW |
1950 | ret = i915_gem_object_finish_gpu(obj); |
1951 | if (ret == -ERESTARTSYS) | |
1952 | return ret; | |
1953 | /* Continue on if we fail due to EIO, the GPU is hung so we | |
1954 | * should be safe and we need to cleanup or else we might | |
1955 | * cause memory corruption through use-after-free. | |
1956 | */ | |
1957 | ||
b5ffc9bc | 1958 | i915_gem_object_finish_gtt(obj); |
5323fd04 | 1959 | |
673a394b EA |
1960 | /* Move the object to the CPU domain to ensure that |
1961 | * any possible CPU writes while it's not in the GTT | |
a8198eea | 1962 | * are flushed when we go to remap it. |
673a394b | 1963 | */ |
a8198eea CW |
1964 | if (ret == 0) |
1965 | ret = i915_gem_object_set_to_cpu_domain(obj, 1); | |
8dc1775d | 1966 | if (ret == -ERESTARTSYS) |
673a394b | 1967 | return ret; |
812ed492 | 1968 | if (ret) { |
a8198eea CW |
1969 | /* In the event of a disaster, abandon all caches and |
1970 | * hope for the best. | |
1971 | */ | |
812ed492 | 1972 | i915_gem_clflush_object(obj); |
05394f39 | 1973 | obj->base.read_domains = obj->base.write_domain = I915_GEM_DOMAIN_CPU; |
812ed492 | 1974 | } |
673a394b | 1975 | |
96b47b65 | 1976 | /* release the fence reg _after_ flushing */ |
d9e86c0e CW |
1977 | ret = i915_gem_object_put_fence(obj); |
1978 | if (ret == -ERESTARTSYS) | |
1979 | return ret; | |
96b47b65 | 1980 | |
db53a302 CW |
1981 | trace_i915_gem_object_unbind(obj); |
1982 | ||
74898d7e DV |
1983 | if (obj->has_global_gtt_mapping) |
1984 | i915_gem_gtt_unbind_object(obj); | |
7bddb01f DV |
1985 | if (obj->has_aliasing_ppgtt_mapping) { |
1986 | i915_ppgtt_unbind_object(dev_priv->mm.aliasing_ppgtt, obj); | |
1987 | obj->has_aliasing_ppgtt_mapping = 0; | |
1988 | } | |
74163907 | 1989 | i915_gem_gtt_finish_object(obj); |
7bddb01f | 1990 | |
e5281ccd | 1991 | i915_gem_object_put_pages_gtt(obj); |
673a394b | 1992 | |
6299f992 | 1993 | list_del_init(&obj->gtt_list); |
05394f39 | 1994 | list_del_init(&obj->mm_list); |
75e9e915 | 1995 | /* Avoid an unnecessary call to unbind on rebind. */ |
05394f39 | 1996 | obj->map_and_fenceable = true; |
673a394b | 1997 | |
05394f39 CW |
1998 | drm_mm_put_block(obj->gtt_space); |
1999 | obj->gtt_space = NULL; | |
2000 | obj->gtt_offset = 0; | |
673a394b | 2001 | |
05394f39 | 2002 | if (i915_gem_object_is_purgeable(obj)) |
963b4836 CW |
2003 | i915_gem_object_truncate(obj); |
2004 | ||
8dc1775d | 2005 | return ret; |
673a394b EA |
2006 | } |
2007 | ||
88241785 | 2008 | int |
db53a302 | 2009 | i915_gem_flush_ring(struct intel_ring_buffer *ring, |
54cf91dc CW |
2010 | uint32_t invalidate_domains, |
2011 | uint32_t flush_domains) | |
2012 | { | |
88241785 CW |
2013 | int ret; |
2014 | ||
36d527de CW |
2015 | if (((invalidate_domains | flush_domains) & I915_GEM_GPU_DOMAINS) == 0) |
2016 | return 0; | |
2017 | ||
db53a302 CW |
2018 | trace_i915_gem_ring_flush(ring, invalidate_domains, flush_domains); |
2019 | ||
88241785 CW |
2020 | ret = ring->flush(ring, invalidate_domains, flush_domains); |
2021 | if (ret) | |
2022 | return ret; | |
2023 | ||
36d527de CW |
2024 | if (flush_domains & I915_GEM_GPU_DOMAINS) |
2025 | i915_gem_process_flushing_list(ring, flush_domains); | |
2026 | ||
88241785 | 2027 | return 0; |
54cf91dc CW |
2028 | } |
2029 | ||
b93f9cf1 | 2030 | static int i915_ring_idle(struct intel_ring_buffer *ring, bool do_retire) |
a56ba56c | 2031 | { |
88241785 CW |
2032 | int ret; |
2033 | ||
395b70be | 2034 | if (list_empty(&ring->gpu_write_list) && list_empty(&ring->active_list)) |
64193406 CW |
2035 | return 0; |
2036 | ||
88241785 | 2037 | if (!list_empty(&ring->gpu_write_list)) { |
db53a302 | 2038 | ret = i915_gem_flush_ring(ring, |
0ac74c6b | 2039 | I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS); |
88241785 CW |
2040 | if (ret) |
2041 | return ret; | |
2042 | } | |
2043 | ||
b93f9cf1 BW |
2044 | return i915_wait_request(ring, i915_gem_next_request_seqno(ring), |
2045 | do_retire); | |
a56ba56c CW |
2046 | } |
2047 | ||
b93f9cf1 | 2048 | int i915_gpu_idle(struct drm_device *dev, bool do_retire) |
4df2faf4 DV |
2049 | { |
2050 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1ec14ad3 | 2051 | int ret, i; |
4df2faf4 | 2052 | |
4df2faf4 | 2053 | /* Flush everything onto the inactive list. */ |
1ec14ad3 | 2054 | for (i = 0; i < I915_NUM_RINGS; i++) { |
b93f9cf1 | 2055 | ret = i915_ring_idle(&dev_priv->ring[i], do_retire); |
1ec14ad3 CW |
2056 | if (ret) |
2057 | return ret; | |
2058 | } | |
4df2faf4 | 2059 | |
8a1a49f9 | 2060 | return 0; |
4df2faf4 DV |
2061 | } |
2062 | ||
c6642782 DV |
2063 | static int sandybridge_write_fence_reg(struct drm_i915_gem_object *obj, |
2064 | struct intel_ring_buffer *pipelined) | |
4e901fdc | 2065 | { |
05394f39 | 2066 | struct drm_device *dev = obj->base.dev; |
4e901fdc | 2067 | drm_i915_private_t *dev_priv = dev->dev_private; |
05394f39 CW |
2068 | u32 size = obj->gtt_space->size; |
2069 | int regnum = obj->fence_reg; | |
4e901fdc EA |
2070 | uint64_t val; |
2071 | ||
05394f39 | 2072 | val = (uint64_t)((obj->gtt_offset + size - 4096) & |
c6642782 | 2073 | 0xfffff000) << 32; |
05394f39 CW |
2074 | val |= obj->gtt_offset & 0xfffff000; |
2075 | val |= (uint64_t)((obj->stride / 128) - 1) << | |
4e901fdc EA |
2076 | SANDYBRIDGE_FENCE_PITCH_SHIFT; |
2077 | ||
05394f39 | 2078 | if (obj->tiling_mode == I915_TILING_Y) |
4e901fdc EA |
2079 | val |= 1 << I965_FENCE_TILING_Y_SHIFT; |
2080 | val |= I965_FENCE_REG_VALID; | |
2081 | ||
c6642782 DV |
2082 | if (pipelined) { |
2083 | int ret = intel_ring_begin(pipelined, 6); | |
2084 | if (ret) | |
2085 | return ret; | |
2086 | ||
2087 | intel_ring_emit(pipelined, MI_NOOP); | |
2088 | intel_ring_emit(pipelined, MI_LOAD_REGISTER_IMM(2)); | |
2089 | intel_ring_emit(pipelined, FENCE_REG_SANDYBRIDGE_0 + regnum*8); | |
2090 | intel_ring_emit(pipelined, (u32)val); | |
2091 | intel_ring_emit(pipelined, FENCE_REG_SANDYBRIDGE_0 + regnum*8 + 4); | |
2092 | intel_ring_emit(pipelined, (u32)(val >> 32)); | |
2093 | intel_ring_advance(pipelined); | |
2094 | } else | |
2095 | I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + regnum * 8, val); | |
2096 | ||
2097 | return 0; | |
4e901fdc EA |
2098 | } |
2099 | ||
c6642782 DV |
2100 | static int i965_write_fence_reg(struct drm_i915_gem_object *obj, |
2101 | struct intel_ring_buffer *pipelined) | |
de151cf6 | 2102 | { |
05394f39 | 2103 | struct drm_device *dev = obj->base.dev; |
de151cf6 | 2104 | drm_i915_private_t *dev_priv = dev->dev_private; |
05394f39 CW |
2105 | u32 size = obj->gtt_space->size; |
2106 | int regnum = obj->fence_reg; | |
de151cf6 JB |
2107 | uint64_t val; |
2108 | ||
05394f39 | 2109 | val = (uint64_t)((obj->gtt_offset + size - 4096) & |
de151cf6 | 2110 | 0xfffff000) << 32; |
05394f39 CW |
2111 | val |= obj->gtt_offset & 0xfffff000; |
2112 | val |= ((obj->stride / 128) - 1) << I965_FENCE_PITCH_SHIFT; | |
2113 | if (obj->tiling_mode == I915_TILING_Y) | |
de151cf6 JB |
2114 | val |= 1 << I965_FENCE_TILING_Y_SHIFT; |
2115 | val |= I965_FENCE_REG_VALID; | |
2116 | ||
c6642782 DV |
2117 | if (pipelined) { |
2118 | int ret = intel_ring_begin(pipelined, 6); | |
2119 | if (ret) | |
2120 | return ret; | |
2121 | ||
2122 | intel_ring_emit(pipelined, MI_NOOP); | |
2123 | intel_ring_emit(pipelined, MI_LOAD_REGISTER_IMM(2)); | |
2124 | intel_ring_emit(pipelined, FENCE_REG_965_0 + regnum*8); | |
2125 | intel_ring_emit(pipelined, (u32)val); | |
2126 | intel_ring_emit(pipelined, FENCE_REG_965_0 + regnum*8 + 4); | |
2127 | intel_ring_emit(pipelined, (u32)(val >> 32)); | |
2128 | intel_ring_advance(pipelined); | |
2129 | } else | |
2130 | I915_WRITE64(FENCE_REG_965_0 + regnum * 8, val); | |
2131 | ||
2132 | return 0; | |
de151cf6 JB |
2133 | } |
2134 | ||
c6642782 DV |
2135 | static int i915_write_fence_reg(struct drm_i915_gem_object *obj, |
2136 | struct intel_ring_buffer *pipelined) | |
de151cf6 | 2137 | { |
05394f39 | 2138 | struct drm_device *dev = obj->base.dev; |
de151cf6 | 2139 | drm_i915_private_t *dev_priv = dev->dev_private; |
05394f39 | 2140 | u32 size = obj->gtt_space->size; |
c6642782 | 2141 | u32 fence_reg, val, pitch_val; |
0f973f27 | 2142 | int tile_width; |
de151cf6 | 2143 | |
c6642782 DV |
2144 | if (WARN((obj->gtt_offset & ~I915_FENCE_START_MASK) || |
2145 | (size & -size) != size || | |
2146 | (obj->gtt_offset & (size - 1)), | |
2147 | "object 0x%08x [fenceable? %d] not 1M or pot-size (0x%08x) aligned\n", | |
2148 | obj->gtt_offset, obj->map_and_fenceable, size)) | |
2149 | return -EINVAL; | |
de151cf6 | 2150 | |
c6642782 | 2151 | if (obj->tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev)) |
0f973f27 | 2152 | tile_width = 128; |
de151cf6 | 2153 | else |
0f973f27 JB |
2154 | tile_width = 512; |
2155 | ||
2156 | /* Note: pitch better be a power of two tile widths */ | |
05394f39 | 2157 | pitch_val = obj->stride / tile_width; |
0f973f27 | 2158 | pitch_val = ffs(pitch_val) - 1; |
de151cf6 | 2159 | |
05394f39 CW |
2160 | val = obj->gtt_offset; |
2161 | if (obj->tiling_mode == I915_TILING_Y) | |
de151cf6 | 2162 | val |= 1 << I830_FENCE_TILING_Y_SHIFT; |
a00b10c3 | 2163 | val |= I915_FENCE_SIZE_BITS(size); |
de151cf6 JB |
2164 | val |= pitch_val << I830_FENCE_PITCH_SHIFT; |
2165 | val |= I830_FENCE_REG_VALID; | |
2166 | ||
05394f39 | 2167 | fence_reg = obj->fence_reg; |
a00b10c3 CW |
2168 | if (fence_reg < 8) |
2169 | fence_reg = FENCE_REG_830_0 + fence_reg * 4; | |
dc529a4f | 2170 | else |
a00b10c3 | 2171 | fence_reg = FENCE_REG_945_8 + (fence_reg - 8) * 4; |
c6642782 DV |
2172 | |
2173 | if (pipelined) { | |
2174 | int ret = intel_ring_begin(pipelined, 4); | |
2175 | if (ret) | |
2176 | return ret; | |
2177 | ||
2178 | intel_ring_emit(pipelined, MI_NOOP); | |
2179 | intel_ring_emit(pipelined, MI_LOAD_REGISTER_IMM(1)); | |
2180 | intel_ring_emit(pipelined, fence_reg); | |
2181 | intel_ring_emit(pipelined, val); | |
2182 | intel_ring_advance(pipelined); | |
2183 | } else | |
2184 | I915_WRITE(fence_reg, val); | |
2185 | ||
2186 | return 0; | |
de151cf6 JB |
2187 | } |
2188 | ||
c6642782 DV |
2189 | static int i830_write_fence_reg(struct drm_i915_gem_object *obj, |
2190 | struct intel_ring_buffer *pipelined) | |
de151cf6 | 2191 | { |
05394f39 | 2192 | struct drm_device *dev = obj->base.dev; |
de151cf6 | 2193 | drm_i915_private_t *dev_priv = dev->dev_private; |
05394f39 CW |
2194 | u32 size = obj->gtt_space->size; |
2195 | int regnum = obj->fence_reg; | |
de151cf6 JB |
2196 | uint32_t val; |
2197 | uint32_t pitch_val; | |
2198 | ||
c6642782 DV |
2199 | if (WARN((obj->gtt_offset & ~I830_FENCE_START_MASK) || |
2200 | (size & -size) != size || | |
2201 | (obj->gtt_offset & (size - 1)), | |
2202 | "object 0x%08x not 512K or pot-size 0x%08x aligned\n", | |
2203 | obj->gtt_offset, size)) | |
2204 | return -EINVAL; | |
de151cf6 | 2205 | |
05394f39 | 2206 | pitch_val = obj->stride / 128; |
e76a16de | 2207 | pitch_val = ffs(pitch_val) - 1; |
e76a16de | 2208 | |
05394f39 CW |
2209 | val = obj->gtt_offset; |
2210 | if (obj->tiling_mode == I915_TILING_Y) | |
de151cf6 | 2211 | val |= 1 << I830_FENCE_TILING_Y_SHIFT; |
c6642782 | 2212 | val |= I830_FENCE_SIZE_BITS(size); |
de151cf6 JB |
2213 | val |= pitch_val << I830_FENCE_PITCH_SHIFT; |
2214 | val |= I830_FENCE_REG_VALID; | |
2215 | ||
c6642782 DV |
2216 | if (pipelined) { |
2217 | int ret = intel_ring_begin(pipelined, 4); | |
2218 | if (ret) | |
2219 | return ret; | |
2220 | ||
2221 | intel_ring_emit(pipelined, MI_NOOP); | |
2222 | intel_ring_emit(pipelined, MI_LOAD_REGISTER_IMM(1)); | |
2223 | intel_ring_emit(pipelined, FENCE_REG_830_0 + regnum*4); | |
2224 | intel_ring_emit(pipelined, val); | |
2225 | intel_ring_advance(pipelined); | |
2226 | } else | |
2227 | I915_WRITE(FENCE_REG_830_0 + regnum * 4, val); | |
2228 | ||
2229 | return 0; | |
de151cf6 JB |
2230 | } |
2231 | ||
d9e86c0e CW |
2232 | static bool ring_passed_seqno(struct intel_ring_buffer *ring, u32 seqno) |
2233 | { | |
2234 | return i915_seqno_passed(ring->get_seqno(ring), seqno); | |
2235 | } | |
2236 | ||
2237 | static int | |
2238 | i915_gem_object_flush_fence(struct drm_i915_gem_object *obj, | |
ce453d81 | 2239 | struct intel_ring_buffer *pipelined) |
d9e86c0e CW |
2240 | { |
2241 | int ret; | |
2242 | ||
2243 | if (obj->fenced_gpu_access) { | |
88241785 | 2244 | if (obj->base.write_domain & I915_GEM_GPU_DOMAINS) { |
db53a302 | 2245 | ret = i915_gem_flush_ring(obj->last_fenced_ring, |
88241785 CW |
2246 | 0, obj->base.write_domain); |
2247 | if (ret) | |
2248 | return ret; | |
2249 | } | |
d9e86c0e CW |
2250 | |
2251 | obj->fenced_gpu_access = false; | |
2252 | } | |
2253 | ||
2254 | if (obj->last_fenced_seqno && pipelined != obj->last_fenced_ring) { | |
2255 | if (!ring_passed_seqno(obj->last_fenced_ring, | |
2256 | obj->last_fenced_seqno)) { | |
db53a302 | 2257 | ret = i915_wait_request(obj->last_fenced_ring, |
b93f9cf1 BW |
2258 | obj->last_fenced_seqno, |
2259 | true); | |
d9e86c0e CW |
2260 | if (ret) |
2261 | return ret; | |
2262 | } | |
2263 | ||
2264 | obj->last_fenced_seqno = 0; | |
2265 | obj->last_fenced_ring = NULL; | |
2266 | } | |
2267 | ||
63256ec5 CW |
2268 | /* Ensure that all CPU reads are completed before installing a fence |
2269 | * and all writes before removing the fence. | |
2270 | */ | |
2271 | if (obj->base.read_domains & I915_GEM_DOMAIN_GTT) | |
2272 | mb(); | |
2273 | ||
d9e86c0e CW |
2274 | return 0; |
2275 | } | |
2276 | ||
2277 | int | |
2278 | i915_gem_object_put_fence(struct drm_i915_gem_object *obj) | |
2279 | { | |
2280 | int ret; | |
2281 | ||
2282 | if (obj->tiling_mode) | |
2283 | i915_gem_release_mmap(obj); | |
2284 | ||
ce453d81 | 2285 | ret = i915_gem_object_flush_fence(obj, NULL); |
d9e86c0e CW |
2286 | if (ret) |
2287 | return ret; | |
2288 | ||
2289 | if (obj->fence_reg != I915_FENCE_REG_NONE) { | |
2290 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; | |
1690e1eb CW |
2291 | |
2292 | WARN_ON(dev_priv->fence_regs[obj->fence_reg].pin_count); | |
d9e86c0e CW |
2293 | i915_gem_clear_fence_reg(obj->base.dev, |
2294 | &dev_priv->fence_regs[obj->fence_reg]); | |
2295 | ||
2296 | obj->fence_reg = I915_FENCE_REG_NONE; | |
2297 | } | |
2298 | ||
2299 | return 0; | |
2300 | } | |
2301 | ||
2302 | static struct drm_i915_fence_reg * | |
2303 | i915_find_fence_reg(struct drm_device *dev, | |
2304 | struct intel_ring_buffer *pipelined) | |
ae3db24a | 2305 | { |
ae3db24a | 2306 | struct drm_i915_private *dev_priv = dev->dev_private; |
d9e86c0e CW |
2307 | struct drm_i915_fence_reg *reg, *first, *avail; |
2308 | int i; | |
ae3db24a DV |
2309 | |
2310 | /* First try to find a free reg */ | |
d9e86c0e | 2311 | avail = NULL; |
ae3db24a DV |
2312 | for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) { |
2313 | reg = &dev_priv->fence_regs[i]; | |
2314 | if (!reg->obj) | |
d9e86c0e | 2315 | return reg; |
ae3db24a | 2316 | |
1690e1eb | 2317 | if (!reg->pin_count) |
d9e86c0e | 2318 | avail = reg; |
ae3db24a DV |
2319 | } |
2320 | ||
d9e86c0e CW |
2321 | if (avail == NULL) |
2322 | return NULL; | |
ae3db24a DV |
2323 | |
2324 | /* None available, try to steal one or wait for a user to finish */ | |
d9e86c0e CW |
2325 | avail = first = NULL; |
2326 | list_for_each_entry(reg, &dev_priv->mm.fence_list, lru_list) { | |
1690e1eb | 2327 | if (reg->pin_count) |
ae3db24a DV |
2328 | continue; |
2329 | ||
d9e86c0e CW |
2330 | if (first == NULL) |
2331 | first = reg; | |
2332 | ||
2333 | if (!pipelined || | |
2334 | !reg->obj->last_fenced_ring || | |
2335 | reg->obj->last_fenced_ring == pipelined) { | |
2336 | avail = reg; | |
2337 | break; | |
2338 | } | |
ae3db24a DV |
2339 | } |
2340 | ||
d9e86c0e CW |
2341 | if (avail == NULL) |
2342 | avail = first; | |
ae3db24a | 2343 | |
a00b10c3 | 2344 | return avail; |
ae3db24a DV |
2345 | } |
2346 | ||
de151cf6 | 2347 | /** |
d9e86c0e | 2348 | * i915_gem_object_get_fence - set up a fence reg for an object |
de151cf6 | 2349 | * @obj: object to map through a fence reg |
d9e86c0e CW |
2350 | * @pipelined: ring on which to queue the change, or NULL for CPU access |
2351 | * @interruptible: must we wait uninterruptibly for the register to retire? | |
de151cf6 JB |
2352 | * |
2353 | * When mapping objects through the GTT, userspace wants to be able to write | |
2354 | * to them without having to worry about swizzling if the object is tiled. | |
2355 | * | |
2356 | * This function walks the fence regs looking for a free one for @obj, | |
2357 | * stealing one if it can't find any. | |
2358 | * | |
2359 | * It then sets up the reg based on the object's properties: address, pitch | |
2360 | * and tiling format. | |
2361 | */ | |
8c4b8c3f | 2362 | int |
d9e86c0e | 2363 | i915_gem_object_get_fence(struct drm_i915_gem_object *obj, |
ce453d81 | 2364 | struct intel_ring_buffer *pipelined) |
de151cf6 | 2365 | { |
05394f39 | 2366 | struct drm_device *dev = obj->base.dev; |
79e53945 | 2367 | struct drm_i915_private *dev_priv = dev->dev_private; |
d9e86c0e | 2368 | struct drm_i915_fence_reg *reg; |
ae3db24a | 2369 | int ret; |
de151cf6 | 2370 | |
6bda10d1 CW |
2371 | /* XXX disable pipelining. There are bugs. Shocking. */ |
2372 | pipelined = NULL; | |
2373 | ||
d9e86c0e | 2374 | /* Just update our place in the LRU if our fence is getting reused. */ |
05394f39 CW |
2375 | if (obj->fence_reg != I915_FENCE_REG_NONE) { |
2376 | reg = &dev_priv->fence_regs[obj->fence_reg]; | |
007cc8ac | 2377 | list_move_tail(®->lru_list, &dev_priv->mm.fence_list); |
d9e86c0e | 2378 | |
29c5a587 CW |
2379 | if (obj->tiling_changed) { |
2380 | ret = i915_gem_object_flush_fence(obj, pipelined); | |
2381 | if (ret) | |
2382 | return ret; | |
2383 | ||
2384 | if (!obj->fenced_gpu_access && !obj->last_fenced_seqno) | |
2385 | pipelined = NULL; | |
2386 | ||
2387 | if (pipelined) { | |
2388 | reg->setup_seqno = | |
2389 | i915_gem_next_request_seqno(pipelined); | |
2390 | obj->last_fenced_seqno = reg->setup_seqno; | |
2391 | obj->last_fenced_ring = pipelined; | |
2392 | } | |
2393 | ||
2394 | goto update; | |
2395 | } | |
d9e86c0e CW |
2396 | |
2397 | if (!pipelined) { | |
2398 | if (reg->setup_seqno) { | |
2399 | if (!ring_passed_seqno(obj->last_fenced_ring, | |
2400 | reg->setup_seqno)) { | |
db53a302 | 2401 | ret = i915_wait_request(obj->last_fenced_ring, |
b93f9cf1 BW |
2402 | reg->setup_seqno, |
2403 | true); | |
d9e86c0e CW |
2404 | if (ret) |
2405 | return ret; | |
2406 | } | |
2407 | ||
2408 | reg->setup_seqno = 0; | |
2409 | } | |
2410 | } else if (obj->last_fenced_ring && | |
2411 | obj->last_fenced_ring != pipelined) { | |
ce453d81 | 2412 | ret = i915_gem_object_flush_fence(obj, pipelined); |
d9e86c0e CW |
2413 | if (ret) |
2414 | return ret; | |
d9e86c0e CW |
2415 | } |
2416 | ||
a09ba7fa EA |
2417 | return 0; |
2418 | } | |
2419 | ||
d9e86c0e CW |
2420 | reg = i915_find_fence_reg(dev, pipelined); |
2421 | if (reg == NULL) | |
39965b37 | 2422 | return -EDEADLK; |
de151cf6 | 2423 | |
ce453d81 | 2424 | ret = i915_gem_object_flush_fence(obj, pipelined); |
d9e86c0e | 2425 | if (ret) |
ae3db24a | 2426 | return ret; |
de151cf6 | 2427 | |
d9e86c0e CW |
2428 | if (reg->obj) { |
2429 | struct drm_i915_gem_object *old = reg->obj; | |
2430 | ||
2431 | drm_gem_object_reference(&old->base); | |
2432 | ||
2433 | if (old->tiling_mode) | |
2434 | i915_gem_release_mmap(old); | |
2435 | ||
ce453d81 | 2436 | ret = i915_gem_object_flush_fence(old, pipelined); |
d9e86c0e CW |
2437 | if (ret) { |
2438 | drm_gem_object_unreference(&old->base); | |
2439 | return ret; | |
2440 | } | |
2441 | ||
2442 | if (old->last_fenced_seqno == 0 && obj->last_fenced_seqno == 0) | |
2443 | pipelined = NULL; | |
2444 | ||
2445 | old->fence_reg = I915_FENCE_REG_NONE; | |
2446 | old->last_fenced_ring = pipelined; | |
2447 | old->last_fenced_seqno = | |
db53a302 | 2448 | pipelined ? i915_gem_next_request_seqno(pipelined) : 0; |
d9e86c0e CW |
2449 | |
2450 | drm_gem_object_unreference(&old->base); | |
2451 | } else if (obj->last_fenced_seqno == 0) | |
2452 | pipelined = NULL; | |
a09ba7fa | 2453 | |
de151cf6 | 2454 | reg->obj = obj; |
d9e86c0e CW |
2455 | list_move_tail(®->lru_list, &dev_priv->mm.fence_list); |
2456 | obj->fence_reg = reg - dev_priv->fence_regs; | |
2457 | obj->last_fenced_ring = pipelined; | |
de151cf6 | 2458 | |
d9e86c0e | 2459 | reg->setup_seqno = |
db53a302 | 2460 | pipelined ? i915_gem_next_request_seqno(pipelined) : 0; |
d9e86c0e CW |
2461 | obj->last_fenced_seqno = reg->setup_seqno; |
2462 | ||
2463 | update: | |
2464 | obj->tiling_changed = false; | |
e259befd | 2465 | switch (INTEL_INFO(dev)->gen) { |
25aebfc3 | 2466 | case 7: |
e259befd | 2467 | case 6: |
c6642782 | 2468 | ret = sandybridge_write_fence_reg(obj, pipelined); |
e259befd CW |
2469 | break; |
2470 | case 5: | |
2471 | case 4: | |
c6642782 | 2472 | ret = i965_write_fence_reg(obj, pipelined); |
e259befd CW |
2473 | break; |
2474 | case 3: | |
c6642782 | 2475 | ret = i915_write_fence_reg(obj, pipelined); |
e259befd CW |
2476 | break; |
2477 | case 2: | |
c6642782 | 2478 | ret = i830_write_fence_reg(obj, pipelined); |
e259befd CW |
2479 | break; |
2480 | } | |
d9ddcb96 | 2481 | |
c6642782 | 2482 | return ret; |
de151cf6 JB |
2483 | } |
2484 | ||
2485 | /** | |
2486 | * i915_gem_clear_fence_reg - clear out fence register info | |
2487 | * @obj: object to clear | |
2488 | * | |
2489 | * Zeroes out the fence register itself and clears out the associated | |
05394f39 | 2490 | * data structures in dev_priv and obj. |
de151cf6 JB |
2491 | */ |
2492 | static void | |
d9e86c0e CW |
2493 | i915_gem_clear_fence_reg(struct drm_device *dev, |
2494 | struct drm_i915_fence_reg *reg) | |
de151cf6 | 2495 | { |
79e53945 | 2496 | drm_i915_private_t *dev_priv = dev->dev_private; |
d9e86c0e | 2497 | uint32_t fence_reg = reg - dev_priv->fence_regs; |
de151cf6 | 2498 | |
e259befd | 2499 | switch (INTEL_INFO(dev)->gen) { |
25aebfc3 | 2500 | case 7: |
e259befd | 2501 | case 6: |
d9e86c0e | 2502 | I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + fence_reg*8, 0); |
e259befd CW |
2503 | break; |
2504 | case 5: | |
2505 | case 4: | |
d9e86c0e | 2506 | I915_WRITE64(FENCE_REG_965_0 + fence_reg*8, 0); |
e259befd CW |
2507 | break; |
2508 | case 3: | |
d9e86c0e CW |
2509 | if (fence_reg >= 8) |
2510 | fence_reg = FENCE_REG_945_8 + (fence_reg - 8) * 4; | |
dc529a4f | 2511 | else |
e259befd | 2512 | case 2: |
d9e86c0e | 2513 | fence_reg = FENCE_REG_830_0 + fence_reg * 4; |
dc529a4f EA |
2514 | |
2515 | I915_WRITE(fence_reg, 0); | |
e259befd | 2516 | break; |
dc529a4f | 2517 | } |
de151cf6 | 2518 | |
007cc8ac | 2519 | list_del_init(®->lru_list); |
d9e86c0e CW |
2520 | reg->obj = NULL; |
2521 | reg->setup_seqno = 0; | |
1690e1eb | 2522 | reg->pin_count = 0; |
52dc7d32 CW |
2523 | } |
2524 | ||
673a394b EA |
2525 | /** |
2526 | * Finds free space in the GTT aperture and binds the object there. | |
2527 | */ | |
2528 | static int | |
05394f39 | 2529 | i915_gem_object_bind_to_gtt(struct drm_i915_gem_object *obj, |
920afa77 | 2530 | unsigned alignment, |
75e9e915 | 2531 | bool map_and_fenceable) |
673a394b | 2532 | { |
05394f39 | 2533 | struct drm_device *dev = obj->base.dev; |
673a394b | 2534 | drm_i915_private_t *dev_priv = dev->dev_private; |
673a394b | 2535 | struct drm_mm_node *free_space; |
a00b10c3 | 2536 | gfp_t gfpmask = __GFP_NORETRY | __GFP_NOWARN; |
5e783301 | 2537 | u32 size, fence_size, fence_alignment, unfenced_alignment; |
75e9e915 | 2538 | bool mappable, fenceable; |
07f73f69 | 2539 | int ret; |
673a394b | 2540 | |
05394f39 | 2541 | if (obj->madv != I915_MADV_WILLNEED) { |
3ef94daa CW |
2542 | DRM_ERROR("Attempting to bind a purgeable object\n"); |
2543 | return -EINVAL; | |
2544 | } | |
2545 | ||
e28f8711 CW |
2546 | fence_size = i915_gem_get_gtt_size(dev, |
2547 | obj->base.size, | |
2548 | obj->tiling_mode); | |
2549 | fence_alignment = i915_gem_get_gtt_alignment(dev, | |
2550 | obj->base.size, | |
2551 | obj->tiling_mode); | |
2552 | unfenced_alignment = | |
2553 | i915_gem_get_unfenced_gtt_alignment(dev, | |
2554 | obj->base.size, | |
2555 | obj->tiling_mode); | |
a00b10c3 | 2556 | |
673a394b | 2557 | if (alignment == 0) |
5e783301 DV |
2558 | alignment = map_and_fenceable ? fence_alignment : |
2559 | unfenced_alignment; | |
75e9e915 | 2560 | if (map_and_fenceable && alignment & (fence_alignment - 1)) { |
673a394b EA |
2561 | DRM_ERROR("Invalid object alignment requested %u\n", alignment); |
2562 | return -EINVAL; | |
2563 | } | |
2564 | ||
05394f39 | 2565 | size = map_and_fenceable ? fence_size : obj->base.size; |
a00b10c3 | 2566 | |
654fc607 CW |
2567 | /* If the object is bigger than the entire aperture, reject it early |
2568 | * before evicting everything in a vain attempt to find space. | |
2569 | */ | |
05394f39 | 2570 | if (obj->base.size > |
75e9e915 | 2571 | (map_and_fenceable ? dev_priv->mm.gtt_mappable_end : dev_priv->mm.gtt_total)) { |
654fc607 CW |
2572 | DRM_ERROR("Attempting to bind an object larger than the aperture\n"); |
2573 | return -E2BIG; | |
2574 | } | |
2575 | ||
673a394b | 2576 | search_free: |
75e9e915 | 2577 | if (map_and_fenceable) |
920afa77 DV |
2578 | free_space = |
2579 | drm_mm_search_free_in_range(&dev_priv->mm.gtt_space, | |
a00b10c3 | 2580 | size, alignment, 0, |
920afa77 DV |
2581 | dev_priv->mm.gtt_mappable_end, |
2582 | 0); | |
2583 | else | |
2584 | free_space = drm_mm_search_free(&dev_priv->mm.gtt_space, | |
a00b10c3 | 2585 | size, alignment, 0); |
920afa77 DV |
2586 | |
2587 | if (free_space != NULL) { | |
75e9e915 | 2588 | if (map_and_fenceable) |
05394f39 | 2589 | obj->gtt_space = |
920afa77 | 2590 | drm_mm_get_block_range_generic(free_space, |
a00b10c3 | 2591 | size, alignment, 0, |
920afa77 DV |
2592 | dev_priv->mm.gtt_mappable_end, |
2593 | 0); | |
2594 | else | |
05394f39 | 2595 | obj->gtt_space = |
a00b10c3 | 2596 | drm_mm_get_block(free_space, size, alignment); |
920afa77 | 2597 | } |
05394f39 | 2598 | if (obj->gtt_space == NULL) { |
673a394b EA |
2599 | /* If the gtt is empty and we're still having trouble |
2600 | * fitting our object in, we're out of memory. | |
2601 | */ | |
75e9e915 DV |
2602 | ret = i915_gem_evict_something(dev, size, alignment, |
2603 | map_and_fenceable); | |
9731129c | 2604 | if (ret) |
673a394b | 2605 | return ret; |
9731129c | 2606 | |
673a394b EA |
2607 | goto search_free; |
2608 | } | |
2609 | ||
e5281ccd | 2610 | ret = i915_gem_object_get_pages_gtt(obj, gfpmask); |
673a394b | 2611 | if (ret) { |
05394f39 CW |
2612 | drm_mm_put_block(obj->gtt_space); |
2613 | obj->gtt_space = NULL; | |
07f73f69 CW |
2614 | |
2615 | if (ret == -ENOMEM) { | |
809b6334 CW |
2616 | /* first try to reclaim some memory by clearing the GTT */ |
2617 | ret = i915_gem_evict_everything(dev, false); | |
07f73f69 | 2618 | if (ret) { |
07f73f69 | 2619 | /* now try to shrink everyone else */ |
4bdadb97 CW |
2620 | if (gfpmask) { |
2621 | gfpmask = 0; | |
2622 | goto search_free; | |
07f73f69 CW |
2623 | } |
2624 | ||
809b6334 | 2625 | return -ENOMEM; |
07f73f69 CW |
2626 | } |
2627 | ||
2628 | goto search_free; | |
2629 | } | |
2630 | ||
673a394b EA |
2631 | return ret; |
2632 | } | |
2633 | ||
74163907 | 2634 | ret = i915_gem_gtt_prepare_object(obj); |
7c2e6fdf | 2635 | if (ret) { |
e5281ccd | 2636 | i915_gem_object_put_pages_gtt(obj); |
05394f39 CW |
2637 | drm_mm_put_block(obj->gtt_space); |
2638 | obj->gtt_space = NULL; | |
07f73f69 | 2639 | |
809b6334 | 2640 | if (i915_gem_evict_everything(dev, false)) |
07f73f69 | 2641 | return ret; |
07f73f69 CW |
2642 | |
2643 | goto search_free; | |
673a394b | 2644 | } |
0ebb9829 DV |
2645 | |
2646 | if (!dev_priv->mm.aliasing_ppgtt) | |
2647 | i915_gem_gtt_bind_object(obj, obj->cache_level); | |
673a394b | 2648 | |
6299f992 | 2649 | list_add_tail(&obj->gtt_list, &dev_priv->mm.gtt_list); |
05394f39 | 2650 | list_add_tail(&obj->mm_list, &dev_priv->mm.inactive_list); |
bf1a1092 | 2651 | |
673a394b EA |
2652 | /* Assert that the object is not currently in any GPU domain. As it |
2653 | * wasn't in the GTT, there shouldn't be any way it could have been in | |
2654 | * a GPU cache | |
2655 | */ | |
05394f39 CW |
2656 | BUG_ON(obj->base.read_domains & I915_GEM_GPU_DOMAINS); |
2657 | BUG_ON(obj->base.write_domain & I915_GEM_GPU_DOMAINS); | |
673a394b | 2658 | |
6299f992 | 2659 | obj->gtt_offset = obj->gtt_space->start; |
1c5d22f7 | 2660 | |
75e9e915 | 2661 | fenceable = |
05394f39 | 2662 | obj->gtt_space->size == fence_size && |
0206e353 | 2663 | (obj->gtt_space->start & (fence_alignment - 1)) == 0; |
a00b10c3 | 2664 | |
75e9e915 | 2665 | mappable = |
05394f39 | 2666 | obj->gtt_offset + obj->base.size <= dev_priv->mm.gtt_mappable_end; |
a00b10c3 | 2667 | |
05394f39 | 2668 | obj->map_and_fenceable = mappable && fenceable; |
75e9e915 | 2669 | |
db53a302 | 2670 | trace_i915_gem_object_bind(obj, map_and_fenceable); |
673a394b EA |
2671 | return 0; |
2672 | } | |
2673 | ||
2674 | void | |
05394f39 | 2675 | i915_gem_clflush_object(struct drm_i915_gem_object *obj) |
673a394b | 2676 | { |
673a394b EA |
2677 | /* If we don't have a page list set up, then we're not pinned |
2678 | * to GPU, and we can ignore the cache flush because it'll happen | |
2679 | * again at bind time. | |
2680 | */ | |
05394f39 | 2681 | if (obj->pages == NULL) |
673a394b EA |
2682 | return; |
2683 | ||
9c23f7fc CW |
2684 | /* If the GPU is snooping the contents of the CPU cache, |
2685 | * we do not need to manually clear the CPU cache lines. However, | |
2686 | * the caches are only snooped when the render cache is | |
2687 | * flushed/invalidated. As we always have to emit invalidations | |
2688 | * and flushes when moving into and out of the RENDER domain, correct | |
2689 | * snooping behaviour occurs naturally as the result of our domain | |
2690 | * tracking. | |
2691 | */ | |
2692 | if (obj->cache_level != I915_CACHE_NONE) | |
2693 | return; | |
2694 | ||
1c5d22f7 | 2695 | trace_i915_gem_object_clflush(obj); |
cfa16a0d | 2696 | |
05394f39 | 2697 | drm_clflush_pages(obj->pages, obj->base.size / PAGE_SIZE); |
673a394b EA |
2698 | } |
2699 | ||
e47c68e9 | 2700 | /** Flushes any GPU write domain for the object if it's dirty. */ |
88241785 | 2701 | static int |
3619df03 | 2702 | i915_gem_object_flush_gpu_write_domain(struct drm_i915_gem_object *obj) |
e47c68e9 | 2703 | { |
05394f39 | 2704 | if ((obj->base.write_domain & I915_GEM_GPU_DOMAINS) == 0) |
88241785 | 2705 | return 0; |
e47c68e9 EA |
2706 | |
2707 | /* Queue the GPU write cache flushing we need. */ | |
db53a302 | 2708 | return i915_gem_flush_ring(obj->ring, 0, obj->base.write_domain); |
e47c68e9 EA |
2709 | } |
2710 | ||
2711 | /** Flushes the GTT write domain for the object if it's dirty. */ | |
2712 | static void | |
05394f39 | 2713 | i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj) |
e47c68e9 | 2714 | { |
1c5d22f7 CW |
2715 | uint32_t old_write_domain; |
2716 | ||
05394f39 | 2717 | if (obj->base.write_domain != I915_GEM_DOMAIN_GTT) |
e47c68e9 EA |
2718 | return; |
2719 | ||
63256ec5 | 2720 | /* No actual flushing is required for the GTT write domain. Writes |
e47c68e9 EA |
2721 | * to it immediately go to main memory as far as we know, so there's |
2722 | * no chipset flush. It also doesn't land in render cache. | |
63256ec5 CW |
2723 | * |
2724 | * However, we do have to enforce the order so that all writes through | |
2725 | * the GTT land before any writes to the device, such as updates to | |
2726 | * the GATT itself. | |
e47c68e9 | 2727 | */ |
63256ec5 CW |
2728 | wmb(); |
2729 | ||
05394f39 CW |
2730 | old_write_domain = obj->base.write_domain; |
2731 | obj->base.write_domain = 0; | |
1c5d22f7 CW |
2732 | |
2733 | trace_i915_gem_object_change_domain(obj, | |
05394f39 | 2734 | obj->base.read_domains, |
1c5d22f7 | 2735 | old_write_domain); |
e47c68e9 EA |
2736 | } |
2737 | ||
2738 | /** Flushes the CPU write domain for the object if it's dirty. */ | |
2739 | static void | |
05394f39 | 2740 | i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj) |
e47c68e9 | 2741 | { |
1c5d22f7 | 2742 | uint32_t old_write_domain; |
e47c68e9 | 2743 | |
05394f39 | 2744 | if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) |
e47c68e9 EA |
2745 | return; |
2746 | ||
2747 | i915_gem_clflush_object(obj); | |
40ce6575 | 2748 | intel_gtt_chipset_flush(); |
05394f39 CW |
2749 | old_write_domain = obj->base.write_domain; |
2750 | obj->base.write_domain = 0; | |
1c5d22f7 CW |
2751 | |
2752 | trace_i915_gem_object_change_domain(obj, | |
05394f39 | 2753 | obj->base.read_domains, |
1c5d22f7 | 2754 | old_write_domain); |
e47c68e9 EA |
2755 | } |
2756 | ||
2ef7eeaa EA |
2757 | /** |
2758 | * Moves a single object to the GTT read, and possibly write domain. | |
2759 | * | |
2760 | * This function returns when the move is complete, including waiting on | |
2761 | * flushes to occur. | |
2762 | */ | |
79e53945 | 2763 | int |
2021746e | 2764 | i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write) |
2ef7eeaa | 2765 | { |
1c5d22f7 | 2766 | uint32_t old_write_domain, old_read_domains; |
e47c68e9 | 2767 | int ret; |
2ef7eeaa | 2768 | |
02354392 | 2769 | /* Not valid to be called on unbound objects. */ |
05394f39 | 2770 | if (obj->gtt_space == NULL) |
02354392 EA |
2771 | return -EINVAL; |
2772 | ||
8d7e3de1 CW |
2773 | if (obj->base.write_domain == I915_GEM_DOMAIN_GTT) |
2774 | return 0; | |
2775 | ||
88241785 CW |
2776 | ret = i915_gem_object_flush_gpu_write_domain(obj); |
2777 | if (ret) | |
2778 | return ret; | |
2779 | ||
87ca9c8a | 2780 | if (obj->pending_gpu_write || write) { |
ce453d81 | 2781 | ret = i915_gem_object_wait_rendering(obj); |
87ca9c8a CW |
2782 | if (ret) |
2783 | return ret; | |
2784 | } | |
2dafb1e0 | 2785 | |
7213342d | 2786 | i915_gem_object_flush_cpu_write_domain(obj); |
1c5d22f7 | 2787 | |
05394f39 CW |
2788 | old_write_domain = obj->base.write_domain; |
2789 | old_read_domains = obj->base.read_domains; | |
1c5d22f7 | 2790 | |
e47c68e9 EA |
2791 | /* It should now be out of any other write domains, and we can update |
2792 | * the domain values for our changes. | |
2793 | */ | |
05394f39 CW |
2794 | BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) != 0); |
2795 | obj->base.read_domains |= I915_GEM_DOMAIN_GTT; | |
e47c68e9 | 2796 | if (write) { |
05394f39 CW |
2797 | obj->base.read_domains = I915_GEM_DOMAIN_GTT; |
2798 | obj->base.write_domain = I915_GEM_DOMAIN_GTT; | |
2799 | obj->dirty = 1; | |
2ef7eeaa EA |
2800 | } |
2801 | ||
1c5d22f7 CW |
2802 | trace_i915_gem_object_change_domain(obj, |
2803 | old_read_domains, | |
2804 | old_write_domain); | |
2805 | ||
e47c68e9 EA |
2806 | return 0; |
2807 | } | |
2808 | ||
e4ffd173 CW |
2809 | int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj, |
2810 | enum i915_cache_level cache_level) | |
2811 | { | |
7bddb01f DV |
2812 | struct drm_device *dev = obj->base.dev; |
2813 | drm_i915_private_t *dev_priv = dev->dev_private; | |
e4ffd173 CW |
2814 | int ret; |
2815 | ||
2816 | if (obj->cache_level == cache_level) | |
2817 | return 0; | |
2818 | ||
2819 | if (obj->pin_count) { | |
2820 | DRM_DEBUG("can not change the cache level of pinned objects\n"); | |
2821 | return -EBUSY; | |
2822 | } | |
2823 | ||
2824 | if (obj->gtt_space) { | |
2825 | ret = i915_gem_object_finish_gpu(obj); | |
2826 | if (ret) | |
2827 | return ret; | |
2828 | ||
2829 | i915_gem_object_finish_gtt(obj); | |
2830 | ||
2831 | /* Before SandyBridge, you could not use tiling or fence | |
2832 | * registers with snooped memory, so relinquish any fences | |
2833 | * currently pointing to our region in the aperture. | |
2834 | */ | |
2835 | if (INTEL_INFO(obj->base.dev)->gen < 6) { | |
2836 | ret = i915_gem_object_put_fence(obj); | |
2837 | if (ret) | |
2838 | return ret; | |
2839 | } | |
2840 | ||
74898d7e DV |
2841 | if (obj->has_global_gtt_mapping) |
2842 | i915_gem_gtt_bind_object(obj, cache_level); | |
7bddb01f DV |
2843 | if (obj->has_aliasing_ppgtt_mapping) |
2844 | i915_ppgtt_bind_object(dev_priv->mm.aliasing_ppgtt, | |
2845 | obj, cache_level); | |
e4ffd173 CW |
2846 | } |
2847 | ||
2848 | if (cache_level == I915_CACHE_NONE) { | |
2849 | u32 old_read_domains, old_write_domain; | |
2850 | ||
2851 | /* If we're coming from LLC cached, then we haven't | |
2852 | * actually been tracking whether the data is in the | |
2853 | * CPU cache or not, since we only allow one bit set | |
2854 | * in obj->write_domain and have been skipping the clflushes. | |
2855 | * Just set it to the CPU cache for now. | |
2856 | */ | |
2857 | WARN_ON(obj->base.write_domain & ~I915_GEM_DOMAIN_CPU); | |
2858 | WARN_ON(obj->base.read_domains & ~I915_GEM_DOMAIN_CPU); | |
2859 | ||
2860 | old_read_domains = obj->base.read_domains; | |
2861 | old_write_domain = obj->base.write_domain; | |
2862 | ||
2863 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; | |
2864 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; | |
2865 | ||
2866 | trace_i915_gem_object_change_domain(obj, | |
2867 | old_read_domains, | |
2868 | old_write_domain); | |
2869 | } | |
2870 | ||
2871 | obj->cache_level = cache_level; | |
2872 | return 0; | |
2873 | } | |
2874 | ||
b9241ea3 | 2875 | /* |
2da3b9b9 CW |
2876 | * Prepare buffer for display plane (scanout, cursors, etc). |
2877 | * Can be called from an uninterruptible phase (modesetting) and allows | |
2878 | * any flushes to be pipelined (for pageflips). | |
2879 | * | |
2880 | * For the display plane, we want to be in the GTT but out of any write | |
2881 | * domains. So in many ways this looks like set_to_gtt_domain() apart from the | |
2882 | * ability to pipeline the waits, pinning and any additional subtleties | |
2883 | * that may differentiate the display plane from ordinary buffers. | |
b9241ea3 ZW |
2884 | */ |
2885 | int | |
2da3b9b9 CW |
2886 | i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj, |
2887 | u32 alignment, | |
919926ae | 2888 | struct intel_ring_buffer *pipelined) |
b9241ea3 | 2889 | { |
2da3b9b9 | 2890 | u32 old_read_domains, old_write_domain; |
b9241ea3 ZW |
2891 | int ret; |
2892 | ||
88241785 CW |
2893 | ret = i915_gem_object_flush_gpu_write_domain(obj); |
2894 | if (ret) | |
2895 | return ret; | |
2896 | ||
0be73284 | 2897 | if (pipelined != obj->ring) { |
ce453d81 | 2898 | ret = i915_gem_object_wait_rendering(obj); |
f0b69efc | 2899 | if (ret == -ERESTARTSYS) |
b9241ea3 ZW |
2900 | return ret; |
2901 | } | |
2902 | ||
a7ef0640 EA |
2903 | /* The display engine is not coherent with the LLC cache on gen6. As |
2904 | * a result, we make sure that the pinning that is about to occur is | |
2905 | * done with uncached PTEs. This is lowest common denominator for all | |
2906 | * chipsets. | |
2907 | * | |
2908 | * However for gen6+, we could do better by using the GFDT bit instead | |
2909 | * of uncaching, which would allow us to flush all the LLC-cached data | |
2910 | * with that bit in the PTE to main memory with just one PIPE_CONTROL. | |
2911 | */ | |
2912 | ret = i915_gem_object_set_cache_level(obj, I915_CACHE_NONE); | |
2913 | if (ret) | |
2914 | return ret; | |
2915 | ||
2da3b9b9 CW |
2916 | /* As the user may map the buffer once pinned in the display plane |
2917 | * (e.g. libkms for the bootup splash), we have to ensure that we | |
2918 | * always use map_and_fenceable for all scanout buffers. | |
2919 | */ | |
2920 | ret = i915_gem_object_pin(obj, alignment, true); | |
2921 | if (ret) | |
2922 | return ret; | |
2923 | ||
b118c1e3 CW |
2924 | i915_gem_object_flush_cpu_write_domain(obj); |
2925 | ||
2da3b9b9 | 2926 | old_write_domain = obj->base.write_domain; |
05394f39 | 2927 | old_read_domains = obj->base.read_domains; |
2da3b9b9 CW |
2928 | |
2929 | /* It should now be out of any other write domains, and we can update | |
2930 | * the domain values for our changes. | |
2931 | */ | |
2932 | BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) != 0); | |
05394f39 | 2933 | obj->base.read_domains |= I915_GEM_DOMAIN_GTT; |
b9241ea3 ZW |
2934 | |
2935 | trace_i915_gem_object_change_domain(obj, | |
2936 | old_read_domains, | |
2da3b9b9 | 2937 | old_write_domain); |
b9241ea3 ZW |
2938 | |
2939 | return 0; | |
2940 | } | |
2941 | ||
85345517 | 2942 | int |
a8198eea | 2943 | i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj) |
85345517 | 2944 | { |
88241785 CW |
2945 | int ret; |
2946 | ||
a8198eea | 2947 | if ((obj->base.read_domains & I915_GEM_GPU_DOMAINS) == 0) |
85345517 CW |
2948 | return 0; |
2949 | ||
88241785 | 2950 | if (obj->base.write_domain & I915_GEM_GPU_DOMAINS) { |
db53a302 | 2951 | ret = i915_gem_flush_ring(obj->ring, 0, obj->base.write_domain); |
88241785 CW |
2952 | if (ret) |
2953 | return ret; | |
2954 | } | |
85345517 | 2955 | |
c501ae7f CW |
2956 | ret = i915_gem_object_wait_rendering(obj); |
2957 | if (ret) | |
2958 | return ret; | |
2959 | ||
a8198eea CW |
2960 | /* Ensure that we invalidate the GPU's caches and TLBs. */ |
2961 | obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS; | |
c501ae7f | 2962 | return 0; |
85345517 CW |
2963 | } |
2964 | ||
e47c68e9 EA |
2965 | /** |
2966 | * Moves a single object to the CPU read, and possibly write domain. | |
2967 | * | |
2968 | * This function returns when the move is complete, including waiting on | |
2969 | * flushes to occur. | |
2970 | */ | |
dabdfe02 | 2971 | int |
919926ae | 2972 | i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write) |
e47c68e9 | 2973 | { |
1c5d22f7 | 2974 | uint32_t old_write_domain, old_read_domains; |
e47c68e9 EA |
2975 | int ret; |
2976 | ||
8d7e3de1 CW |
2977 | if (obj->base.write_domain == I915_GEM_DOMAIN_CPU) |
2978 | return 0; | |
2979 | ||
88241785 CW |
2980 | ret = i915_gem_object_flush_gpu_write_domain(obj); |
2981 | if (ret) | |
2982 | return ret; | |
2983 | ||
ce453d81 | 2984 | ret = i915_gem_object_wait_rendering(obj); |
de18a29e | 2985 | if (ret) |
e47c68e9 | 2986 | return ret; |
2ef7eeaa | 2987 | |
e47c68e9 | 2988 | i915_gem_object_flush_gtt_write_domain(obj); |
2ef7eeaa | 2989 | |
05394f39 CW |
2990 | old_write_domain = obj->base.write_domain; |
2991 | old_read_domains = obj->base.read_domains; | |
1c5d22f7 | 2992 | |
e47c68e9 | 2993 | /* Flush the CPU cache if it's still invalid. */ |
05394f39 | 2994 | if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) { |
2ef7eeaa | 2995 | i915_gem_clflush_object(obj); |
2ef7eeaa | 2996 | |
05394f39 | 2997 | obj->base.read_domains |= I915_GEM_DOMAIN_CPU; |
2ef7eeaa EA |
2998 | } |
2999 | ||
3000 | /* It should now be out of any other write domains, and we can update | |
3001 | * the domain values for our changes. | |
3002 | */ | |
05394f39 | 3003 | BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) != 0); |
e47c68e9 EA |
3004 | |
3005 | /* If we're writing through the CPU, then the GPU read domains will | |
3006 | * need to be invalidated at next use. | |
3007 | */ | |
3008 | if (write) { | |
05394f39 CW |
3009 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; |
3010 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; | |
e47c68e9 | 3011 | } |
2ef7eeaa | 3012 | |
1c5d22f7 CW |
3013 | trace_i915_gem_object_change_domain(obj, |
3014 | old_read_domains, | |
3015 | old_write_domain); | |
3016 | ||
2ef7eeaa EA |
3017 | return 0; |
3018 | } | |
3019 | ||
673a394b EA |
3020 | /* Throttle our rendering by waiting until the ring has completed our requests |
3021 | * emitted over 20 msec ago. | |
3022 | * | |
b962442e EA |
3023 | * Note that if we were to use the current jiffies each time around the loop, |
3024 | * we wouldn't escape the function with any frames outstanding if the time to | |
3025 | * render a frame was over 20ms. | |
3026 | * | |
673a394b EA |
3027 | * This should get us reasonable parallelism between CPU and GPU but also |
3028 | * relatively low latency when blocking on a particular request to finish. | |
3029 | */ | |
40a5f0de | 3030 | static int |
f787a5f5 | 3031 | i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file) |
40a5f0de | 3032 | { |
f787a5f5 CW |
3033 | struct drm_i915_private *dev_priv = dev->dev_private; |
3034 | struct drm_i915_file_private *file_priv = file->driver_priv; | |
b962442e | 3035 | unsigned long recent_enough = jiffies - msecs_to_jiffies(20); |
f787a5f5 CW |
3036 | struct drm_i915_gem_request *request; |
3037 | struct intel_ring_buffer *ring = NULL; | |
3038 | u32 seqno = 0; | |
3039 | int ret; | |
93533c29 | 3040 | |
e110e8d6 CW |
3041 | if (atomic_read(&dev_priv->mm.wedged)) |
3042 | return -EIO; | |
3043 | ||
1c25595f | 3044 | spin_lock(&file_priv->mm.lock); |
f787a5f5 | 3045 | list_for_each_entry(request, &file_priv->mm.request_list, client_list) { |
b962442e EA |
3046 | if (time_after_eq(request->emitted_jiffies, recent_enough)) |
3047 | break; | |
40a5f0de | 3048 | |
f787a5f5 CW |
3049 | ring = request->ring; |
3050 | seqno = request->seqno; | |
b962442e | 3051 | } |
1c25595f | 3052 | spin_unlock(&file_priv->mm.lock); |
40a5f0de | 3053 | |
f787a5f5 CW |
3054 | if (seqno == 0) |
3055 | return 0; | |
2bc43b5c | 3056 | |
f787a5f5 | 3057 | ret = 0; |
78501eac | 3058 | if (!i915_seqno_passed(ring->get_seqno(ring), seqno)) { |
f787a5f5 CW |
3059 | /* And wait for the seqno passing without holding any locks and |
3060 | * causing extra latency for others. This is safe as the irq | |
3061 | * generation is designed to be run atomically and so is | |
3062 | * lockless. | |
3063 | */ | |
b13c2b96 CW |
3064 | if (ring->irq_get(ring)) { |
3065 | ret = wait_event_interruptible(ring->irq_queue, | |
3066 | i915_seqno_passed(ring->get_seqno(ring), seqno) | |
3067 | || atomic_read(&dev_priv->mm.wedged)); | |
3068 | ring->irq_put(ring); | |
40a5f0de | 3069 | |
b13c2b96 CW |
3070 | if (ret == 0 && atomic_read(&dev_priv->mm.wedged)) |
3071 | ret = -EIO; | |
e959b5db EA |
3072 | } else if (wait_for_atomic(i915_seqno_passed(ring->get_seqno(ring), |
3073 | seqno) || | |
7ea29b13 EA |
3074 | atomic_read(&dev_priv->mm.wedged), 3000)) { |
3075 | ret = -EBUSY; | |
b13c2b96 | 3076 | } |
40a5f0de EA |
3077 | } |
3078 | ||
f787a5f5 CW |
3079 | if (ret == 0) |
3080 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, 0); | |
40a5f0de EA |
3081 | |
3082 | return ret; | |
3083 | } | |
3084 | ||
673a394b | 3085 | int |
05394f39 CW |
3086 | i915_gem_object_pin(struct drm_i915_gem_object *obj, |
3087 | uint32_t alignment, | |
75e9e915 | 3088 | bool map_and_fenceable) |
673a394b | 3089 | { |
05394f39 | 3090 | struct drm_device *dev = obj->base.dev; |
f13d3f73 | 3091 | struct drm_i915_private *dev_priv = dev->dev_private; |
673a394b EA |
3092 | int ret; |
3093 | ||
05394f39 | 3094 | BUG_ON(obj->pin_count == DRM_I915_GEM_OBJECT_MAX_PIN_COUNT); |
23bc5982 | 3095 | WARN_ON(i915_verify_lists(dev)); |
ac0c6b5a | 3096 | |
05394f39 CW |
3097 | if (obj->gtt_space != NULL) { |
3098 | if ((alignment && obj->gtt_offset & (alignment - 1)) || | |
3099 | (map_and_fenceable && !obj->map_and_fenceable)) { | |
3100 | WARN(obj->pin_count, | |
ae7d49d8 | 3101 | "bo is already pinned with incorrect alignment:" |
75e9e915 DV |
3102 | " offset=%x, req.alignment=%x, req.map_and_fenceable=%d," |
3103 | " obj->map_and_fenceable=%d\n", | |
05394f39 | 3104 | obj->gtt_offset, alignment, |
75e9e915 | 3105 | map_and_fenceable, |
05394f39 | 3106 | obj->map_and_fenceable); |
ac0c6b5a CW |
3107 | ret = i915_gem_object_unbind(obj); |
3108 | if (ret) | |
3109 | return ret; | |
3110 | } | |
3111 | } | |
3112 | ||
05394f39 | 3113 | if (obj->gtt_space == NULL) { |
a00b10c3 | 3114 | ret = i915_gem_object_bind_to_gtt(obj, alignment, |
75e9e915 | 3115 | map_and_fenceable); |
9731129c | 3116 | if (ret) |
673a394b | 3117 | return ret; |
22c344e9 | 3118 | } |
76446cac | 3119 | |
74898d7e DV |
3120 | if (!obj->has_global_gtt_mapping && map_and_fenceable) |
3121 | i915_gem_gtt_bind_object(obj, obj->cache_level); | |
3122 | ||
05394f39 | 3123 | if (obj->pin_count++ == 0) { |
05394f39 CW |
3124 | if (!obj->active) |
3125 | list_move_tail(&obj->mm_list, | |
f13d3f73 | 3126 | &dev_priv->mm.pinned_list); |
673a394b | 3127 | } |
6299f992 | 3128 | obj->pin_mappable |= map_and_fenceable; |
673a394b | 3129 | |
23bc5982 | 3130 | WARN_ON(i915_verify_lists(dev)); |
673a394b EA |
3131 | return 0; |
3132 | } | |
3133 | ||
3134 | void | |
05394f39 | 3135 | i915_gem_object_unpin(struct drm_i915_gem_object *obj) |
673a394b | 3136 | { |
05394f39 | 3137 | struct drm_device *dev = obj->base.dev; |
673a394b | 3138 | drm_i915_private_t *dev_priv = dev->dev_private; |
673a394b | 3139 | |
23bc5982 | 3140 | WARN_ON(i915_verify_lists(dev)); |
05394f39 CW |
3141 | BUG_ON(obj->pin_count == 0); |
3142 | BUG_ON(obj->gtt_space == NULL); | |
673a394b | 3143 | |
05394f39 CW |
3144 | if (--obj->pin_count == 0) { |
3145 | if (!obj->active) | |
3146 | list_move_tail(&obj->mm_list, | |
673a394b | 3147 | &dev_priv->mm.inactive_list); |
6299f992 | 3148 | obj->pin_mappable = false; |
673a394b | 3149 | } |
23bc5982 | 3150 | WARN_ON(i915_verify_lists(dev)); |
673a394b EA |
3151 | } |
3152 | ||
3153 | int | |
3154 | i915_gem_pin_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 3155 | struct drm_file *file) |
673a394b EA |
3156 | { |
3157 | struct drm_i915_gem_pin *args = data; | |
05394f39 | 3158 | struct drm_i915_gem_object *obj; |
673a394b EA |
3159 | int ret; |
3160 | ||
1d7cfea1 CW |
3161 | ret = i915_mutex_lock_interruptible(dev); |
3162 | if (ret) | |
3163 | return ret; | |
673a394b | 3164 | |
05394f39 | 3165 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 3166 | if (&obj->base == NULL) { |
1d7cfea1 CW |
3167 | ret = -ENOENT; |
3168 | goto unlock; | |
673a394b | 3169 | } |
673a394b | 3170 | |
05394f39 | 3171 | if (obj->madv != I915_MADV_WILLNEED) { |
bb6baf76 | 3172 | DRM_ERROR("Attempting to pin a purgeable buffer\n"); |
1d7cfea1 CW |
3173 | ret = -EINVAL; |
3174 | goto out; | |
3ef94daa CW |
3175 | } |
3176 | ||
05394f39 | 3177 | if (obj->pin_filp != NULL && obj->pin_filp != file) { |
79e53945 JB |
3178 | DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n", |
3179 | args->handle); | |
1d7cfea1 CW |
3180 | ret = -EINVAL; |
3181 | goto out; | |
79e53945 JB |
3182 | } |
3183 | ||
05394f39 CW |
3184 | obj->user_pin_count++; |
3185 | obj->pin_filp = file; | |
3186 | if (obj->user_pin_count == 1) { | |
75e9e915 | 3187 | ret = i915_gem_object_pin(obj, args->alignment, true); |
1d7cfea1 CW |
3188 | if (ret) |
3189 | goto out; | |
673a394b EA |
3190 | } |
3191 | ||
3192 | /* XXX - flush the CPU caches for pinned objects | |
3193 | * as the X server doesn't manage domains yet | |
3194 | */ | |
e47c68e9 | 3195 | i915_gem_object_flush_cpu_write_domain(obj); |
05394f39 | 3196 | args->offset = obj->gtt_offset; |
1d7cfea1 | 3197 | out: |
05394f39 | 3198 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 3199 | unlock: |
673a394b | 3200 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 3201 | return ret; |
673a394b EA |
3202 | } |
3203 | ||
3204 | int | |
3205 | i915_gem_unpin_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 3206 | struct drm_file *file) |
673a394b EA |
3207 | { |
3208 | struct drm_i915_gem_pin *args = data; | |
05394f39 | 3209 | struct drm_i915_gem_object *obj; |
76c1dec1 | 3210 | int ret; |
673a394b | 3211 | |
1d7cfea1 CW |
3212 | ret = i915_mutex_lock_interruptible(dev); |
3213 | if (ret) | |
3214 | return ret; | |
673a394b | 3215 | |
05394f39 | 3216 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 3217 | if (&obj->base == NULL) { |
1d7cfea1 CW |
3218 | ret = -ENOENT; |
3219 | goto unlock; | |
673a394b | 3220 | } |
76c1dec1 | 3221 | |
05394f39 | 3222 | if (obj->pin_filp != file) { |
79e53945 JB |
3223 | DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n", |
3224 | args->handle); | |
1d7cfea1 CW |
3225 | ret = -EINVAL; |
3226 | goto out; | |
79e53945 | 3227 | } |
05394f39 CW |
3228 | obj->user_pin_count--; |
3229 | if (obj->user_pin_count == 0) { | |
3230 | obj->pin_filp = NULL; | |
79e53945 JB |
3231 | i915_gem_object_unpin(obj); |
3232 | } | |
673a394b | 3233 | |
1d7cfea1 | 3234 | out: |
05394f39 | 3235 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 3236 | unlock: |
673a394b | 3237 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 3238 | return ret; |
673a394b EA |
3239 | } |
3240 | ||
3241 | int | |
3242 | i915_gem_busy_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 3243 | struct drm_file *file) |
673a394b EA |
3244 | { |
3245 | struct drm_i915_gem_busy *args = data; | |
05394f39 | 3246 | struct drm_i915_gem_object *obj; |
30dbf0c0 CW |
3247 | int ret; |
3248 | ||
76c1dec1 | 3249 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 3250 | if (ret) |
76c1dec1 | 3251 | return ret; |
673a394b | 3252 | |
05394f39 | 3253 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 3254 | if (&obj->base == NULL) { |
1d7cfea1 CW |
3255 | ret = -ENOENT; |
3256 | goto unlock; | |
673a394b | 3257 | } |
d1b851fc | 3258 | |
0be555b6 CW |
3259 | /* Count all active objects as busy, even if they are currently not used |
3260 | * by the gpu. Users of this interface expect objects to eventually | |
3261 | * become non-busy without any further actions, therefore emit any | |
3262 | * necessary flushes here. | |
c4de0a5d | 3263 | */ |
05394f39 | 3264 | args->busy = obj->active; |
0be555b6 CW |
3265 | if (args->busy) { |
3266 | /* Unconditionally flush objects, even when the gpu still uses this | |
3267 | * object. Userspace calling this function indicates that it wants to | |
3268 | * use this buffer rather sooner than later, so issuing the required | |
3269 | * flush earlier is beneficial. | |
3270 | */ | |
1a1c6976 | 3271 | if (obj->base.write_domain & I915_GEM_GPU_DOMAINS) { |
db53a302 | 3272 | ret = i915_gem_flush_ring(obj->ring, |
88241785 | 3273 | 0, obj->base.write_domain); |
1a1c6976 CW |
3274 | } else if (obj->ring->outstanding_lazy_request == |
3275 | obj->last_rendering_seqno) { | |
3276 | struct drm_i915_gem_request *request; | |
3277 | ||
7a194876 CW |
3278 | /* This ring is not being cleared by active usage, |
3279 | * so emit a request to do so. | |
3280 | */ | |
1a1c6976 | 3281 | request = kzalloc(sizeof(*request), GFP_KERNEL); |
457eafce | 3282 | if (request) { |
0206e353 | 3283 | ret = i915_add_request(obj->ring, NULL, request); |
457eafce RM |
3284 | if (ret) |
3285 | kfree(request); | |
3286 | } else | |
7a194876 CW |
3287 | ret = -ENOMEM; |
3288 | } | |
0be555b6 CW |
3289 | |
3290 | /* Update the active list for the hardware's current position. | |
3291 | * Otherwise this only updates on a delayed timer or when irqs | |
3292 | * are actually unmasked, and our working set ends up being | |
3293 | * larger than required. | |
3294 | */ | |
db53a302 | 3295 | i915_gem_retire_requests_ring(obj->ring); |
0be555b6 | 3296 | |
05394f39 | 3297 | args->busy = obj->active; |
0be555b6 | 3298 | } |
673a394b | 3299 | |
05394f39 | 3300 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 3301 | unlock: |
673a394b | 3302 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 3303 | return ret; |
673a394b EA |
3304 | } |
3305 | ||
3306 | int | |
3307 | i915_gem_throttle_ioctl(struct drm_device *dev, void *data, | |
3308 | struct drm_file *file_priv) | |
3309 | { | |
0206e353 | 3310 | return i915_gem_ring_throttle(dev, file_priv); |
673a394b EA |
3311 | } |
3312 | ||
3ef94daa CW |
3313 | int |
3314 | i915_gem_madvise_ioctl(struct drm_device *dev, void *data, | |
3315 | struct drm_file *file_priv) | |
3316 | { | |
3317 | struct drm_i915_gem_madvise *args = data; | |
05394f39 | 3318 | struct drm_i915_gem_object *obj; |
76c1dec1 | 3319 | int ret; |
3ef94daa CW |
3320 | |
3321 | switch (args->madv) { | |
3322 | case I915_MADV_DONTNEED: | |
3323 | case I915_MADV_WILLNEED: | |
3324 | break; | |
3325 | default: | |
3326 | return -EINVAL; | |
3327 | } | |
3328 | ||
1d7cfea1 CW |
3329 | ret = i915_mutex_lock_interruptible(dev); |
3330 | if (ret) | |
3331 | return ret; | |
3332 | ||
05394f39 | 3333 | obj = to_intel_bo(drm_gem_object_lookup(dev, file_priv, args->handle)); |
c8725226 | 3334 | if (&obj->base == NULL) { |
1d7cfea1 CW |
3335 | ret = -ENOENT; |
3336 | goto unlock; | |
3ef94daa | 3337 | } |
3ef94daa | 3338 | |
05394f39 | 3339 | if (obj->pin_count) { |
1d7cfea1 CW |
3340 | ret = -EINVAL; |
3341 | goto out; | |
3ef94daa CW |
3342 | } |
3343 | ||
05394f39 CW |
3344 | if (obj->madv != __I915_MADV_PURGED) |
3345 | obj->madv = args->madv; | |
3ef94daa | 3346 | |
2d7ef395 | 3347 | /* if the object is no longer bound, discard its backing storage */ |
05394f39 CW |
3348 | if (i915_gem_object_is_purgeable(obj) && |
3349 | obj->gtt_space == NULL) | |
2d7ef395 CW |
3350 | i915_gem_object_truncate(obj); |
3351 | ||
05394f39 | 3352 | args->retained = obj->madv != __I915_MADV_PURGED; |
bb6baf76 | 3353 | |
1d7cfea1 | 3354 | out: |
05394f39 | 3355 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 3356 | unlock: |
3ef94daa | 3357 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 3358 | return ret; |
3ef94daa CW |
3359 | } |
3360 | ||
05394f39 CW |
3361 | struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev, |
3362 | size_t size) | |
ac52bc56 | 3363 | { |
73aa808f | 3364 | struct drm_i915_private *dev_priv = dev->dev_private; |
c397b908 | 3365 | struct drm_i915_gem_object *obj; |
5949eac4 | 3366 | struct address_space *mapping; |
ac52bc56 | 3367 | |
c397b908 DV |
3368 | obj = kzalloc(sizeof(*obj), GFP_KERNEL); |
3369 | if (obj == NULL) | |
3370 | return NULL; | |
673a394b | 3371 | |
c397b908 DV |
3372 | if (drm_gem_object_init(dev, &obj->base, size) != 0) { |
3373 | kfree(obj); | |
3374 | return NULL; | |
3375 | } | |
673a394b | 3376 | |
5949eac4 HD |
3377 | mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping; |
3378 | mapping_set_gfp_mask(mapping, GFP_HIGHUSER | __GFP_RECLAIMABLE); | |
3379 | ||
73aa808f CW |
3380 | i915_gem_info_add_obj(dev_priv, size); |
3381 | ||
c397b908 DV |
3382 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; |
3383 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; | |
673a394b | 3384 | |
3d29b842 ED |
3385 | if (HAS_LLC(dev)) { |
3386 | /* On some devices, we can have the GPU use the LLC (the CPU | |
a1871112 EA |
3387 | * cache) for about a 10% performance improvement |
3388 | * compared to uncached. Graphics requests other than | |
3389 | * display scanout are coherent with the CPU in | |
3390 | * accessing this cache. This means in this mode we | |
3391 | * don't need to clflush on the CPU side, and on the | |
3392 | * GPU side we only need to flush internal caches to | |
3393 | * get data visible to the CPU. | |
3394 | * | |
3395 | * However, we maintain the display planes as UC, and so | |
3396 | * need to rebind when first used as such. | |
3397 | */ | |
3398 | obj->cache_level = I915_CACHE_LLC; | |
3399 | } else | |
3400 | obj->cache_level = I915_CACHE_NONE; | |
3401 | ||
62b8b215 | 3402 | obj->base.driver_private = NULL; |
c397b908 | 3403 | obj->fence_reg = I915_FENCE_REG_NONE; |
69dc4987 | 3404 | INIT_LIST_HEAD(&obj->mm_list); |
93a37f20 | 3405 | INIT_LIST_HEAD(&obj->gtt_list); |
69dc4987 | 3406 | INIT_LIST_HEAD(&obj->ring_list); |
432e58ed | 3407 | INIT_LIST_HEAD(&obj->exec_list); |
c397b908 | 3408 | INIT_LIST_HEAD(&obj->gpu_write_list); |
c397b908 | 3409 | obj->madv = I915_MADV_WILLNEED; |
75e9e915 DV |
3410 | /* Avoid an unnecessary call to unbind on the first bind. */ |
3411 | obj->map_and_fenceable = true; | |
de151cf6 | 3412 | |
05394f39 | 3413 | return obj; |
c397b908 DV |
3414 | } |
3415 | ||
3416 | int i915_gem_init_object(struct drm_gem_object *obj) | |
3417 | { | |
3418 | BUG(); | |
de151cf6 | 3419 | |
673a394b EA |
3420 | return 0; |
3421 | } | |
3422 | ||
05394f39 | 3423 | static void i915_gem_free_object_tail(struct drm_i915_gem_object *obj) |
673a394b | 3424 | { |
05394f39 | 3425 | struct drm_device *dev = obj->base.dev; |
be72615b | 3426 | drm_i915_private_t *dev_priv = dev->dev_private; |
be72615b | 3427 | int ret; |
673a394b | 3428 | |
be72615b CW |
3429 | ret = i915_gem_object_unbind(obj); |
3430 | if (ret == -ERESTARTSYS) { | |
05394f39 | 3431 | list_move(&obj->mm_list, |
be72615b CW |
3432 | &dev_priv->mm.deferred_free_list); |
3433 | return; | |
3434 | } | |
673a394b | 3435 | |
26e12f89 CW |
3436 | trace_i915_gem_object_destroy(obj); |
3437 | ||
05394f39 | 3438 | if (obj->base.map_list.map) |
b464e9a2 | 3439 | drm_gem_free_mmap_offset(&obj->base); |
de151cf6 | 3440 | |
05394f39 CW |
3441 | drm_gem_object_release(&obj->base); |
3442 | i915_gem_info_remove_obj(dev_priv, obj->base.size); | |
c397b908 | 3443 | |
05394f39 CW |
3444 | kfree(obj->bit_17); |
3445 | kfree(obj); | |
673a394b EA |
3446 | } |
3447 | ||
05394f39 | 3448 | void i915_gem_free_object(struct drm_gem_object *gem_obj) |
be72615b | 3449 | { |
05394f39 CW |
3450 | struct drm_i915_gem_object *obj = to_intel_bo(gem_obj); |
3451 | struct drm_device *dev = obj->base.dev; | |
be72615b | 3452 | |
05394f39 | 3453 | while (obj->pin_count > 0) |
be72615b CW |
3454 | i915_gem_object_unpin(obj); |
3455 | ||
05394f39 | 3456 | if (obj->phys_obj) |
be72615b CW |
3457 | i915_gem_detach_phys_object(dev, obj); |
3458 | ||
3459 | i915_gem_free_object_tail(obj); | |
3460 | } | |
3461 | ||
29105ccc CW |
3462 | int |
3463 | i915_gem_idle(struct drm_device *dev) | |
3464 | { | |
3465 | drm_i915_private_t *dev_priv = dev->dev_private; | |
3466 | int ret; | |
28dfe52a | 3467 | |
29105ccc | 3468 | mutex_lock(&dev->struct_mutex); |
1c5d22f7 | 3469 | |
87acb0a5 | 3470 | if (dev_priv->mm.suspended) { |
29105ccc CW |
3471 | mutex_unlock(&dev->struct_mutex); |
3472 | return 0; | |
28dfe52a EA |
3473 | } |
3474 | ||
b93f9cf1 | 3475 | ret = i915_gpu_idle(dev, true); |
6dbe2772 KP |
3476 | if (ret) { |
3477 | mutex_unlock(&dev->struct_mutex); | |
673a394b | 3478 | return ret; |
6dbe2772 | 3479 | } |
673a394b | 3480 | |
29105ccc CW |
3481 | /* Under UMS, be paranoid and evict. */ |
3482 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) { | |
5eac3ab4 | 3483 | ret = i915_gem_evict_inactive(dev, false); |
29105ccc CW |
3484 | if (ret) { |
3485 | mutex_unlock(&dev->struct_mutex); | |
3486 | return ret; | |
3487 | } | |
3488 | } | |
3489 | ||
312817a3 CW |
3490 | i915_gem_reset_fences(dev); |
3491 | ||
29105ccc CW |
3492 | /* Hack! Don't let anybody do execbuf while we don't control the chip. |
3493 | * We need to replace this with a semaphore, or something. | |
3494 | * And not confound mm.suspended! | |
3495 | */ | |
3496 | dev_priv->mm.suspended = 1; | |
bc0c7f14 | 3497 | del_timer_sync(&dev_priv->hangcheck_timer); |
29105ccc CW |
3498 | |
3499 | i915_kernel_lost_context(dev); | |
6dbe2772 | 3500 | i915_gem_cleanup_ringbuffer(dev); |
29105ccc | 3501 | |
6dbe2772 KP |
3502 | mutex_unlock(&dev->struct_mutex); |
3503 | ||
29105ccc CW |
3504 | /* Cancel the retire work handler, which should be idle now. */ |
3505 | cancel_delayed_work_sync(&dev_priv->mm.retire_work); | |
3506 | ||
673a394b EA |
3507 | return 0; |
3508 | } | |
3509 | ||
f691e2f4 DV |
3510 | void i915_gem_init_swizzling(struct drm_device *dev) |
3511 | { | |
3512 | drm_i915_private_t *dev_priv = dev->dev_private; | |
3513 | ||
11782b02 | 3514 | if (INTEL_INFO(dev)->gen < 5 || |
f691e2f4 DV |
3515 | dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE) |
3516 | return; | |
3517 | ||
3518 | I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) | | |
3519 | DISP_TILE_SURFACE_SWIZZLING); | |
3520 | ||
11782b02 DV |
3521 | if (IS_GEN5(dev)) |
3522 | return; | |
3523 | ||
f691e2f4 DV |
3524 | I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_SWZCTL); |
3525 | if (IS_GEN6(dev)) | |
3526 | I915_WRITE(ARB_MODE, ARB_MODE_ENABLE(ARB_MODE_SWIZZLE_SNB)); | |
3527 | else | |
3528 | I915_WRITE(ARB_MODE, ARB_MODE_ENABLE(ARB_MODE_SWIZZLE_IVB)); | |
3529 | } | |
e21af88d DV |
3530 | |
3531 | void i915_gem_init_ppgtt(struct drm_device *dev) | |
3532 | { | |
3533 | drm_i915_private_t *dev_priv = dev->dev_private; | |
3534 | uint32_t pd_offset; | |
3535 | struct intel_ring_buffer *ring; | |
3536 | int i; | |
3537 | ||
3538 | if (!dev_priv->mm.aliasing_ppgtt) | |
3539 | return; | |
3540 | ||
3541 | pd_offset = dev_priv->mm.aliasing_ppgtt->pd_offset; | |
3542 | pd_offset /= 64; /* in cachelines, */ | |
3543 | pd_offset <<= 16; | |
3544 | ||
3545 | if (INTEL_INFO(dev)->gen == 6) { | |
3546 | uint32_t ecochk = I915_READ(GAM_ECOCHK); | |
3547 | I915_WRITE(GAM_ECOCHK, ecochk | ECOCHK_SNB_BIT | | |
3548 | ECOCHK_PPGTT_CACHE64B); | |
3549 | I915_WRITE(GFX_MODE, GFX_MODE_ENABLE(GFX_PPGTT_ENABLE)); | |
3550 | } else if (INTEL_INFO(dev)->gen >= 7) { | |
3551 | I915_WRITE(GAM_ECOCHK, ECOCHK_PPGTT_CACHE64B); | |
3552 | /* GFX_MODE is per-ring on gen7+ */ | |
3553 | } | |
3554 | ||
3555 | for (i = 0; i < I915_NUM_RINGS; i++) { | |
3556 | ring = &dev_priv->ring[i]; | |
3557 | ||
3558 | if (INTEL_INFO(dev)->gen >= 7) | |
3559 | I915_WRITE(RING_MODE_GEN7(ring), | |
3560 | GFX_MODE_ENABLE(GFX_PPGTT_ENABLE)); | |
3561 | ||
3562 | I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G); | |
3563 | I915_WRITE(RING_PP_DIR_BASE(ring), pd_offset); | |
3564 | } | |
3565 | } | |
3566 | ||
8187a2b7 | 3567 | int |
f691e2f4 | 3568 | i915_gem_init_hw(struct drm_device *dev) |
8187a2b7 ZN |
3569 | { |
3570 | drm_i915_private_t *dev_priv = dev->dev_private; | |
3571 | int ret; | |
68f95ba9 | 3572 | |
f691e2f4 DV |
3573 | i915_gem_init_swizzling(dev); |
3574 | ||
5c1143bb | 3575 | ret = intel_init_render_ring_buffer(dev); |
68f95ba9 | 3576 | if (ret) |
b6913e4b | 3577 | return ret; |
68f95ba9 CW |
3578 | |
3579 | if (HAS_BSD(dev)) { | |
5c1143bb | 3580 | ret = intel_init_bsd_ring_buffer(dev); |
68f95ba9 CW |
3581 | if (ret) |
3582 | goto cleanup_render_ring; | |
d1b851fc | 3583 | } |
68f95ba9 | 3584 | |
549f7365 CW |
3585 | if (HAS_BLT(dev)) { |
3586 | ret = intel_init_blt_ring_buffer(dev); | |
3587 | if (ret) | |
3588 | goto cleanup_bsd_ring; | |
3589 | } | |
3590 | ||
6f392d54 CW |
3591 | dev_priv->next_seqno = 1; |
3592 | ||
e21af88d DV |
3593 | i915_gem_init_ppgtt(dev); |
3594 | ||
68f95ba9 CW |
3595 | return 0; |
3596 | ||
549f7365 | 3597 | cleanup_bsd_ring: |
1ec14ad3 | 3598 | intel_cleanup_ring_buffer(&dev_priv->ring[VCS]); |
68f95ba9 | 3599 | cleanup_render_ring: |
1ec14ad3 | 3600 | intel_cleanup_ring_buffer(&dev_priv->ring[RCS]); |
8187a2b7 ZN |
3601 | return ret; |
3602 | } | |
3603 | ||
3604 | void | |
3605 | i915_gem_cleanup_ringbuffer(struct drm_device *dev) | |
3606 | { | |
3607 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1ec14ad3 | 3608 | int i; |
8187a2b7 | 3609 | |
1ec14ad3 CW |
3610 | for (i = 0; i < I915_NUM_RINGS; i++) |
3611 | intel_cleanup_ring_buffer(&dev_priv->ring[i]); | |
8187a2b7 ZN |
3612 | } |
3613 | ||
673a394b EA |
3614 | int |
3615 | i915_gem_entervt_ioctl(struct drm_device *dev, void *data, | |
3616 | struct drm_file *file_priv) | |
3617 | { | |
3618 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1ec14ad3 | 3619 | int ret, i; |
673a394b | 3620 | |
79e53945 JB |
3621 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
3622 | return 0; | |
3623 | ||
ba1234d1 | 3624 | if (atomic_read(&dev_priv->mm.wedged)) { |
673a394b | 3625 | DRM_ERROR("Reenabling wedged hardware, good luck\n"); |
ba1234d1 | 3626 | atomic_set(&dev_priv->mm.wedged, 0); |
673a394b EA |
3627 | } |
3628 | ||
673a394b | 3629 | mutex_lock(&dev->struct_mutex); |
9bb2d6f9 EA |
3630 | dev_priv->mm.suspended = 0; |
3631 | ||
f691e2f4 | 3632 | ret = i915_gem_init_hw(dev); |
d816f6ac WF |
3633 | if (ret != 0) { |
3634 | mutex_unlock(&dev->struct_mutex); | |
9bb2d6f9 | 3635 | return ret; |
d816f6ac | 3636 | } |
9bb2d6f9 | 3637 | |
69dc4987 | 3638 | BUG_ON(!list_empty(&dev_priv->mm.active_list)); |
673a394b EA |
3639 | BUG_ON(!list_empty(&dev_priv->mm.flushing_list)); |
3640 | BUG_ON(!list_empty(&dev_priv->mm.inactive_list)); | |
1ec14ad3 CW |
3641 | for (i = 0; i < I915_NUM_RINGS; i++) { |
3642 | BUG_ON(!list_empty(&dev_priv->ring[i].active_list)); | |
3643 | BUG_ON(!list_empty(&dev_priv->ring[i].request_list)); | |
3644 | } | |
673a394b | 3645 | mutex_unlock(&dev->struct_mutex); |
dbb19d30 | 3646 | |
5f35308b CW |
3647 | ret = drm_irq_install(dev); |
3648 | if (ret) | |
3649 | goto cleanup_ringbuffer; | |
dbb19d30 | 3650 | |
673a394b | 3651 | return 0; |
5f35308b CW |
3652 | |
3653 | cleanup_ringbuffer: | |
3654 | mutex_lock(&dev->struct_mutex); | |
3655 | i915_gem_cleanup_ringbuffer(dev); | |
3656 | dev_priv->mm.suspended = 1; | |
3657 | mutex_unlock(&dev->struct_mutex); | |
3658 | ||
3659 | return ret; | |
673a394b EA |
3660 | } |
3661 | ||
3662 | int | |
3663 | i915_gem_leavevt_ioctl(struct drm_device *dev, void *data, | |
3664 | struct drm_file *file_priv) | |
3665 | { | |
79e53945 JB |
3666 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
3667 | return 0; | |
3668 | ||
dbb19d30 | 3669 | drm_irq_uninstall(dev); |
e6890f6f | 3670 | return i915_gem_idle(dev); |
673a394b EA |
3671 | } |
3672 | ||
3673 | void | |
3674 | i915_gem_lastclose(struct drm_device *dev) | |
3675 | { | |
3676 | int ret; | |
673a394b | 3677 | |
e806b495 EA |
3678 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
3679 | return; | |
3680 | ||
6dbe2772 KP |
3681 | ret = i915_gem_idle(dev); |
3682 | if (ret) | |
3683 | DRM_ERROR("failed to idle hardware: %d\n", ret); | |
673a394b EA |
3684 | } |
3685 | ||
64193406 CW |
3686 | static void |
3687 | init_ring_lists(struct intel_ring_buffer *ring) | |
3688 | { | |
3689 | INIT_LIST_HEAD(&ring->active_list); | |
3690 | INIT_LIST_HEAD(&ring->request_list); | |
3691 | INIT_LIST_HEAD(&ring->gpu_write_list); | |
3692 | } | |
3693 | ||
673a394b EA |
3694 | void |
3695 | i915_gem_load(struct drm_device *dev) | |
3696 | { | |
b5aa8a0f | 3697 | int i; |
673a394b EA |
3698 | drm_i915_private_t *dev_priv = dev->dev_private; |
3699 | ||
69dc4987 | 3700 | INIT_LIST_HEAD(&dev_priv->mm.active_list); |
673a394b EA |
3701 | INIT_LIST_HEAD(&dev_priv->mm.flushing_list); |
3702 | INIT_LIST_HEAD(&dev_priv->mm.inactive_list); | |
f13d3f73 | 3703 | INIT_LIST_HEAD(&dev_priv->mm.pinned_list); |
a09ba7fa | 3704 | INIT_LIST_HEAD(&dev_priv->mm.fence_list); |
be72615b | 3705 | INIT_LIST_HEAD(&dev_priv->mm.deferred_free_list); |
93a37f20 | 3706 | INIT_LIST_HEAD(&dev_priv->mm.gtt_list); |
1ec14ad3 CW |
3707 | for (i = 0; i < I915_NUM_RINGS; i++) |
3708 | init_ring_lists(&dev_priv->ring[i]); | |
4b9de737 | 3709 | for (i = 0; i < I915_MAX_NUM_FENCES; i++) |
007cc8ac | 3710 | INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list); |
673a394b EA |
3711 | INIT_DELAYED_WORK(&dev_priv->mm.retire_work, |
3712 | i915_gem_retire_work_handler); | |
30dbf0c0 | 3713 | init_completion(&dev_priv->error_completion); |
31169714 | 3714 | |
94400120 DA |
3715 | /* On GEN3 we really need to make sure the ARB C3 LP bit is set */ |
3716 | if (IS_GEN3(dev)) { | |
3717 | u32 tmp = I915_READ(MI_ARB_STATE); | |
3718 | if (!(tmp & MI_ARB_C3_LP_WRITE_ENABLE)) { | |
3719 | /* arb state is a masked write, so set bit + bit in mask */ | |
3720 | tmp = MI_ARB_C3_LP_WRITE_ENABLE | (MI_ARB_C3_LP_WRITE_ENABLE << MI_ARB_MASK_SHIFT); | |
3721 | I915_WRITE(MI_ARB_STATE, tmp); | |
3722 | } | |
3723 | } | |
3724 | ||
72bfa19c CW |
3725 | dev_priv->relative_constants_mode = I915_EXEC_CONSTANTS_REL_GENERAL; |
3726 | ||
de151cf6 | 3727 | /* Old X drivers will take 0-2 for front, back, depth buffers */ |
b397c836 EA |
3728 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) |
3729 | dev_priv->fence_reg_start = 3; | |
de151cf6 | 3730 | |
a6c45cf0 | 3731 | if (INTEL_INFO(dev)->gen >= 4 || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) |
de151cf6 JB |
3732 | dev_priv->num_fence_regs = 16; |
3733 | else | |
3734 | dev_priv->num_fence_regs = 8; | |
3735 | ||
b5aa8a0f | 3736 | /* Initialize fence registers to zero */ |
10ed13e4 EA |
3737 | for (i = 0; i < dev_priv->num_fence_regs; i++) { |
3738 | i915_gem_clear_fence_reg(dev, &dev_priv->fence_regs[i]); | |
b5aa8a0f | 3739 | } |
10ed13e4 | 3740 | |
673a394b | 3741 | i915_gem_detect_bit_6_swizzle(dev); |
6b95a207 | 3742 | init_waitqueue_head(&dev_priv->pending_flip_queue); |
17250b71 | 3743 | |
ce453d81 CW |
3744 | dev_priv->mm.interruptible = true; |
3745 | ||
17250b71 CW |
3746 | dev_priv->mm.inactive_shrinker.shrink = i915_gem_inactive_shrink; |
3747 | dev_priv->mm.inactive_shrinker.seeks = DEFAULT_SEEKS; | |
3748 | register_shrinker(&dev_priv->mm.inactive_shrinker); | |
673a394b | 3749 | } |
71acb5eb DA |
3750 | |
3751 | /* | |
3752 | * Create a physically contiguous memory object for this object | |
3753 | * e.g. for cursor + overlay regs | |
3754 | */ | |
995b6762 CW |
3755 | static int i915_gem_init_phys_object(struct drm_device *dev, |
3756 | int id, int size, int align) | |
71acb5eb DA |
3757 | { |
3758 | drm_i915_private_t *dev_priv = dev->dev_private; | |
3759 | struct drm_i915_gem_phys_object *phys_obj; | |
3760 | int ret; | |
3761 | ||
3762 | if (dev_priv->mm.phys_objs[id - 1] || !size) | |
3763 | return 0; | |
3764 | ||
9a298b2a | 3765 | phys_obj = kzalloc(sizeof(struct drm_i915_gem_phys_object), GFP_KERNEL); |
71acb5eb DA |
3766 | if (!phys_obj) |
3767 | return -ENOMEM; | |
3768 | ||
3769 | phys_obj->id = id; | |
3770 | ||
6eeefaf3 | 3771 | phys_obj->handle = drm_pci_alloc(dev, size, align); |
71acb5eb DA |
3772 | if (!phys_obj->handle) { |
3773 | ret = -ENOMEM; | |
3774 | goto kfree_obj; | |
3775 | } | |
3776 | #ifdef CONFIG_X86 | |
3777 | set_memory_wc((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE); | |
3778 | #endif | |
3779 | ||
3780 | dev_priv->mm.phys_objs[id - 1] = phys_obj; | |
3781 | ||
3782 | return 0; | |
3783 | kfree_obj: | |
9a298b2a | 3784 | kfree(phys_obj); |
71acb5eb DA |
3785 | return ret; |
3786 | } | |
3787 | ||
995b6762 | 3788 | static void i915_gem_free_phys_object(struct drm_device *dev, int id) |
71acb5eb DA |
3789 | { |
3790 | drm_i915_private_t *dev_priv = dev->dev_private; | |
3791 | struct drm_i915_gem_phys_object *phys_obj; | |
3792 | ||
3793 | if (!dev_priv->mm.phys_objs[id - 1]) | |
3794 | return; | |
3795 | ||
3796 | phys_obj = dev_priv->mm.phys_objs[id - 1]; | |
3797 | if (phys_obj->cur_obj) { | |
3798 | i915_gem_detach_phys_object(dev, phys_obj->cur_obj); | |
3799 | } | |
3800 | ||
3801 | #ifdef CONFIG_X86 | |
3802 | set_memory_wb((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE); | |
3803 | #endif | |
3804 | drm_pci_free(dev, phys_obj->handle); | |
3805 | kfree(phys_obj); | |
3806 | dev_priv->mm.phys_objs[id - 1] = NULL; | |
3807 | } | |
3808 | ||
3809 | void i915_gem_free_all_phys_object(struct drm_device *dev) | |
3810 | { | |
3811 | int i; | |
3812 | ||
260883c8 | 3813 | for (i = I915_GEM_PHYS_CURSOR_0; i <= I915_MAX_PHYS_OBJECT; i++) |
71acb5eb DA |
3814 | i915_gem_free_phys_object(dev, i); |
3815 | } | |
3816 | ||
3817 | void i915_gem_detach_phys_object(struct drm_device *dev, | |
05394f39 | 3818 | struct drm_i915_gem_object *obj) |
71acb5eb | 3819 | { |
05394f39 | 3820 | struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping; |
e5281ccd | 3821 | char *vaddr; |
71acb5eb | 3822 | int i; |
71acb5eb DA |
3823 | int page_count; |
3824 | ||
05394f39 | 3825 | if (!obj->phys_obj) |
71acb5eb | 3826 | return; |
05394f39 | 3827 | vaddr = obj->phys_obj->handle->vaddr; |
71acb5eb | 3828 | |
05394f39 | 3829 | page_count = obj->base.size / PAGE_SIZE; |
71acb5eb | 3830 | for (i = 0; i < page_count; i++) { |
5949eac4 | 3831 | struct page *page = shmem_read_mapping_page(mapping, i); |
e5281ccd CW |
3832 | if (!IS_ERR(page)) { |
3833 | char *dst = kmap_atomic(page); | |
3834 | memcpy(dst, vaddr + i*PAGE_SIZE, PAGE_SIZE); | |
3835 | kunmap_atomic(dst); | |
3836 | ||
3837 | drm_clflush_pages(&page, 1); | |
3838 | ||
3839 | set_page_dirty(page); | |
3840 | mark_page_accessed(page); | |
3841 | page_cache_release(page); | |
3842 | } | |
71acb5eb | 3843 | } |
40ce6575 | 3844 | intel_gtt_chipset_flush(); |
d78b47b9 | 3845 | |
05394f39 CW |
3846 | obj->phys_obj->cur_obj = NULL; |
3847 | obj->phys_obj = NULL; | |
71acb5eb DA |
3848 | } |
3849 | ||
3850 | int | |
3851 | i915_gem_attach_phys_object(struct drm_device *dev, | |
05394f39 | 3852 | struct drm_i915_gem_object *obj, |
6eeefaf3 CW |
3853 | int id, |
3854 | int align) | |
71acb5eb | 3855 | { |
05394f39 | 3856 | struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping; |
71acb5eb | 3857 | drm_i915_private_t *dev_priv = dev->dev_private; |
71acb5eb DA |
3858 | int ret = 0; |
3859 | int page_count; | |
3860 | int i; | |
3861 | ||
3862 | if (id > I915_MAX_PHYS_OBJECT) | |
3863 | return -EINVAL; | |
3864 | ||
05394f39 CW |
3865 | if (obj->phys_obj) { |
3866 | if (obj->phys_obj->id == id) | |
71acb5eb DA |
3867 | return 0; |
3868 | i915_gem_detach_phys_object(dev, obj); | |
3869 | } | |
3870 | ||
71acb5eb DA |
3871 | /* create a new object */ |
3872 | if (!dev_priv->mm.phys_objs[id - 1]) { | |
3873 | ret = i915_gem_init_phys_object(dev, id, | |
05394f39 | 3874 | obj->base.size, align); |
71acb5eb | 3875 | if (ret) { |
05394f39 CW |
3876 | DRM_ERROR("failed to init phys object %d size: %zu\n", |
3877 | id, obj->base.size); | |
e5281ccd | 3878 | return ret; |
71acb5eb DA |
3879 | } |
3880 | } | |
3881 | ||
3882 | /* bind to the object */ | |
05394f39 CW |
3883 | obj->phys_obj = dev_priv->mm.phys_objs[id - 1]; |
3884 | obj->phys_obj->cur_obj = obj; | |
71acb5eb | 3885 | |
05394f39 | 3886 | page_count = obj->base.size / PAGE_SIZE; |
71acb5eb DA |
3887 | |
3888 | for (i = 0; i < page_count; i++) { | |
e5281ccd CW |
3889 | struct page *page; |
3890 | char *dst, *src; | |
3891 | ||
5949eac4 | 3892 | page = shmem_read_mapping_page(mapping, i); |
e5281ccd CW |
3893 | if (IS_ERR(page)) |
3894 | return PTR_ERR(page); | |
71acb5eb | 3895 | |
ff75b9bc | 3896 | src = kmap_atomic(page); |
05394f39 | 3897 | dst = obj->phys_obj->handle->vaddr + (i * PAGE_SIZE); |
71acb5eb | 3898 | memcpy(dst, src, PAGE_SIZE); |
3e4d3af5 | 3899 | kunmap_atomic(src); |
71acb5eb | 3900 | |
e5281ccd CW |
3901 | mark_page_accessed(page); |
3902 | page_cache_release(page); | |
3903 | } | |
d78b47b9 | 3904 | |
71acb5eb | 3905 | return 0; |
71acb5eb DA |
3906 | } |
3907 | ||
3908 | static int | |
05394f39 CW |
3909 | i915_gem_phys_pwrite(struct drm_device *dev, |
3910 | struct drm_i915_gem_object *obj, | |
71acb5eb DA |
3911 | struct drm_i915_gem_pwrite *args, |
3912 | struct drm_file *file_priv) | |
3913 | { | |
05394f39 | 3914 | void *vaddr = obj->phys_obj->handle->vaddr + args->offset; |
b47b30cc | 3915 | char __user *user_data = (char __user *) (uintptr_t) args->data_ptr; |
71acb5eb | 3916 | |
b47b30cc CW |
3917 | if (__copy_from_user_inatomic_nocache(vaddr, user_data, args->size)) { |
3918 | unsigned long unwritten; | |
3919 | ||
3920 | /* The physical object once assigned is fixed for the lifetime | |
3921 | * of the obj, so we can safely drop the lock and continue | |
3922 | * to access vaddr. | |
3923 | */ | |
3924 | mutex_unlock(&dev->struct_mutex); | |
3925 | unwritten = copy_from_user(vaddr, user_data, args->size); | |
3926 | mutex_lock(&dev->struct_mutex); | |
3927 | if (unwritten) | |
3928 | return -EFAULT; | |
3929 | } | |
71acb5eb | 3930 | |
40ce6575 | 3931 | intel_gtt_chipset_flush(); |
71acb5eb DA |
3932 | return 0; |
3933 | } | |
b962442e | 3934 | |
f787a5f5 | 3935 | void i915_gem_release(struct drm_device *dev, struct drm_file *file) |
b962442e | 3936 | { |
f787a5f5 | 3937 | struct drm_i915_file_private *file_priv = file->driver_priv; |
b962442e EA |
3938 | |
3939 | /* Clean up our request list when the client is going away, so that | |
3940 | * later retire_requests won't dereference our soon-to-be-gone | |
3941 | * file_priv. | |
3942 | */ | |
1c25595f | 3943 | spin_lock(&file_priv->mm.lock); |
f787a5f5 CW |
3944 | while (!list_empty(&file_priv->mm.request_list)) { |
3945 | struct drm_i915_gem_request *request; | |
3946 | ||
3947 | request = list_first_entry(&file_priv->mm.request_list, | |
3948 | struct drm_i915_gem_request, | |
3949 | client_list); | |
3950 | list_del(&request->client_list); | |
3951 | request->file_priv = NULL; | |
3952 | } | |
1c25595f | 3953 | spin_unlock(&file_priv->mm.lock); |
b962442e | 3954 | } |
31169714 | 3955 | |
1637ef41 CW |
3956 | static int |
3957 | i915_gpu_is_active(struct drm_device *dev) | |
3958 | { | |
3959 | drm_i915_private_t *dev_priv = dev->dev_private; | |
3960 | int lists_empty; | |
3961 | ||
1637ef41 | 3962 | lists_empty = list_empty(&dev_priv->mm.flushing_list) && |
17250b71 | 3963 | list_empty(&dev_priv->mm.active_list); |
1637ef41 CW |
3964 | |
3965 | return !lists_empty; | |
3966 | } | |
3967 | ||
31169714 | 3968 | static int |
1495f230 | 3969 | i915_gem_inactive_shrink(struct shrinker *shrinker, struct shrink_control *sc) |
31169714 | 3970 | { |
17250b71 CW |
3971 | struct drm_i915_private *dev_priv = |
3972 | container_of(shrinker, | |
3973 | struct drm_i915_private, | |
3974 | mm.inactive_shrinker); | |
3975 | struct drm_device *dev = dev_priv->dev; | |
3976 | struct drm_i915_gem_object *obj, *next; | |
1495f230 | 3977 | int nr_to_scan = sc->nr_to_scan; |
17250b71 CW |
3978 | int cnt; |
3979 | ||
3980 | if (!mutex_trylock(&dev->struct_mutex)) | |
bbe2e11a | 3981 | return 0; |
31169714 CW |
3982 | |
3983 | /* "fast-path" to count number of available objects */ | |
3984 | if (nr_to_scan == 0) { | |
17250b71 CW |
3985 | cnt = 0; |
3986 | list_for_each_entry(obj, | |
3987 | &dev_priv->mm.inactive_list, | |
3988 | mm_list) | |
3989 | cnt++; | |
3990 | mutex_unlock(&dev->struct_mutex); | |
3991 | return cnt / 100 * sysctl_vfs_cache_pressure; | |
31169714 CW |
3992 | } |
3993 | ||
1637ef41 | 3994 | rescan: |
31169714 | 3995 | /* first scan for clean buffers */ |
17250b71 | 3996 | i915_gem_retire_requests(dev); |
31169714 | 3997 | |
17250b71 CW |
3998 | list_for_each_entry_safe(obj, next, |
3999 | &dev_priv->mm.inactive_list, | |
4000 | mm_list) { | |
4001 | if (i915_gem_object_is_purgeable(obj)) { | |
2021746e CW |
4002 | if (i915_gem_object_unbind(obj) == 0 && |
4003 | --nr_to_scan == 0) | |
17250b71 | 4004 | break; |
31169714 | 4005 | } |
31169714 CW |
4006 | } |
4007 | ||
4008 | /* second pass, evict/count anything still on the inactive list */ | |
17250b71 CW |
4009 | cnt = 0; |
4010 | list_for_each_entry_safe(obj, next, | |
4011 | &dev_priv->mm.inactive_list, | |
4012 | mm_list) { | |
2021746e CW |
4013 | if (nr_to_scan && |
4014 | i915_gem_object_unbind(obj) == 0) | |
17250b71 | 4015 | nr_to_scan--; |
2021746e | 4016 | else |
17250b71 CW |
4017 | cnt++; |
4018 | } | |
4019 | ||
4020 | if (nr_to_scan && i915_gpu_is_active(dev)) { | |
1637ef41 CW |
4021 | /* |
4022 | * We are desperate for pages, so as a last resort, wait | |
4023 | * for the GPU to finish and discard whatever we can. | |
4024 | * This has a dramatic impact to reduce the number of | |
4025 | * OOM-killer events whilst running the GPU aggressively. | |
4026 | */ | |
b93f9cf1 | 4027 | if (i915_gpu_idle(dev, true) == 0) |
1637ef41 CW |
4028 | goto rescan; |
4029 | } | |
17250b71 CW |
4030 | mutex_unlock(&dev->struct_mutex); |
4031 | return cnt / 100 * sysctl_vfs_cache_pressure; | |
31169714 | 4032 | } |