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673a394b | 1 | /* |
be6a0376 | 2 | * Copyright © 2008-2015 Intel Corporation |
673a394b EA |
3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | * | |
26 | */ | |
27 | ||
760285e7 | 28 | #include <drm/drmP.h> |
0de23977 | 29 | #include <drm/drm_vma_manager.h> |
760285e7 | 30 | #include <drm/i915_drm.h> |
673a394b | 31 | #include "i915_drv.h" |
eb82289a | 32 | #include "i915_vgpu.h" |
1c5d22f7 | 33 | #include "i915_trace.h" |
652c393a | 34 | #include "intel_drv.h" |
5d723d7a | 35 | #include "intel_frontbuffer.h" |
0ccdacf6 | 36 | #include "intel_mocs.h" |
6b5e90f5 | 37 | #include <linux/dma-fence-array.h> |
fe3288b5 | 38 | #include <linux/kthread.h> |
c13d87ea | 39 | #include <linux/reservation.h> |
5949eac4 | 40 | #include <linux/shmem_fs.h> |
5a0e3ad6 | 41 | #include <linux/slab.h> |
20e4933c | 42 | #include <linux/stop_machine.h> |
673a394b | 43 | #include <linux/swap.h> |
79e53945 | 44 | #include <linux/pci.h> |
1286ff73 | 45 | #include <linux/dma-buf.h> |
673a394b | 46 | |
fbbd37b3 | 47 | static void i915_gem_flush_free_objects(struct drm_i915_private *i915); |
05394f39 | 48 | static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj); |
e62b59e4 | 49 | static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj); |
61050808 | 50 | |
c76ce038 CW |
51 | static bool cpu_cache_is_coherent(struct drm_device *dev, |
52 | enum i915_cache_level level) | |
53 | { | |
0031fb96 | 54 | return HAS_LLC(to_i915(dev)) || level != I915_CACHE_NONE; |
c76ce038 CW |
55 | } |
56 | ||
2c22569b CW |
57 | static bool cpu_write_needs_clflush(struct drm_i915_gem_object *obj) |
58 | { | |
b50a5371 AS |
59 | if (obj->base.write_domain == I915_GEM_DOMAIN_CPU) |
60 | return false; | |
61 | ||
2c22569b CW |
62 | if (!cpu_cache_is_coherent(obj->base.dev, obj->cache_level)) |
63 | return true; | |
64 | ||
65 | return obj->pin_display; | |
66 | } | |
67 | ||
4f1959ee | 68 | static int |
bb6dc8d9 | 69 | insert_mappable_node(struct i915_ggtt *ggtt, |
4f1959ee AS |
70 | struct drm_mm_node *node, u32 size) |
71 | { | |
72 | memset(node, 0, sizeof(*node)); | |
4e64e553 CW |
73 | return drm_mm_insert_node_in_range(&ggtt->base.mm, node, |
74 | size, 0, I915_COLOR_UNEVICTABLE, | |
75 | 0, ggtt->mappable_end, | |
76 | DRM_MM_INSERT_LOW); | |
4f1959ee AS |
77 | } |
78 | ||
79 | static void | |
80 | remove_mappable_node(struct drm_mm_node *node) | |
81 | { | |
82 | drm_mm_remove_node(node); | |
83 | } | |
84 | ||
73aa808f CW |
85 | /* some bookkeeping */ |
86 | static void i915_gem_info_add_obj(struct drm_i915_private *dev_priv, | |
3ef7f228 | 87 | u64 size) |
73aa808f | 88 | { |
c20e8355 | 89 | spin_lock(&dev_priv->mm.object_stat_lock); |
73aa808f CW |
90 | dev_priv->mm.object_count++; |
91 | dev_priv->mm.object_memory += size; | |
c20e8355 | 92 | spin_unlock(&dev_priv->mm.object_stat_lock); |
73aa808f CW |
93 | } |
94 | ||
95 | static void i915_gem_info_remove_obj(struct drm_i915_private *dev_priv, | |
3ef7f228 | 96 | u64 size) |
73aa808f | 97 | { |
c20e8355 | 98 | spin_lock(&dev_priv->mm.object_stat_lock); |
73aa808f CW |
99 | dev_priv->mm.object_count--; |
100 | dev_priv->mm.object_memory -= size; | |
c20e8355 | 101 | spin_unlock(&dev_priv->mm.object_stat_lock); |
73aa808f CW |
102 | } |
103 | ||
21dd3734 | 104 | static int |
33196ded | 105 | i915_gem_wait_for_error(struct i915_gpu_error *error) |
30dbf0c0 | 106 | { |
30dbf0c0 CW |
107 | int ret; |
108 | ||
4c7d62c6 CW |
109 | might_sleep(); |
110 | ||
d98c52cf | 111 | if (!i915_reset_in_progress(error)) |
30dbf0c0 CW |
112 | return 0; |
113 | ||
0a6759c6 DV |
114 | /* |
115 | * Only wait 10 seconds for the gpu reset to complete to avoid hanging | |
116 | * userspace. If it takes that long something really bad is going on and | |
117 | * we should simply try to bail out and fail as gracefully as possible. | |
118 | */ | |
1f83fee0 | 119 | ret = wait_event_interruptible_timeout(error->reset_queue, |
d98c52cf | 120 | !i915_reset_in_progress(error), |
b52992c0 | 121 | I915_RESET_TIMEOUT); |
0a6759c6 DV |
122 | if (ret == 0) { |
123 | DRM_ERROR("Timed out waiting for the gpu reset to complete\n"); | |
124 | return -EIO; | |
125 | } else if (ret < 0) { | |
30dbf0c0 | 126 | return ret; |
d98c52cf CW |
127 | } else { |
128 | return 0; | |
0a6759c6 | 129 | } |
30dbf0c0 CW |
130 | } |
131 | ||
54cf91dc | 132 | int i915_mutex_lock_interruptible(struct drm_device *dev) |
76c1dec1 | 133 | { |
fac5e23e | 134 | struct drm_i915_private *dev_priv = to_i915(dev); |
76c1dec1 CW |
135 | int ret; |
136 | ||
33196ded | 137 | ret = i915_gem_wait_for_error(&dev_priv->gpu_error); |
76c1dec1 CW |
138 | if (ret) |
139 | return ret; | |
140 | ||
141 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
142 | if (ret) | |
143 | return ret; | |
144 | ||
76c1dec1 CW |
145 | return 0; |
146 | } | |
30dbf0c0 | 147 | |
5a125c3c EA |
148 | int |
149 | i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 150 | struct drm_file *file) |
5a125c3c | 151 | { |
72e96d64 | 152 | struct drm_i915_private *dev_priv = to_i915(dev); |
62106b4f | 153 | struct i915_ggtt *ggtt = &dev_priv->ggtt; |
72e96d64 | 154 | struct drm_i915_gem_get_aperture *args = data; |
ca1543be | 155 | struct i915_vma *vma; |
6299f992 | 156 | size_t pinned; |
5a125c3c | 157 | |
6299f992 | 158 | pinned = 0; |
73aa808f | 159 | mutex_lock(&dev->struct_mutex); |
1c7f4bca | 160 | list_for_each_entry(vma, &ggtt->base.active_list, vm_link) |
20dfbde4 | 161 | if (i915_vma_is_pinned(vma)) |
ca1543be | 162 | pinned += vma->node.size; |
1c7f4bca | 163 | list_for_each_entry(vma, &ggtt->base.inactive_list, vm_link) |
20dfbde4 | 164 | if (i915_vma_is_pinned(vma)) |
ca1543be | 165 | pinned += vma->node.size; |
73aa808f | 166 | mutex_unlock(&dev->struct_mutex); |
5a125c3c | 167 | |
72e96d64 | 168 | args->aper_size = ggtt->base.total; |
0206e353 | 169 | args->aper_available_size = args->aper_size - pinned; |
6299f992 | 170 | |
5a125c3c EA |
171 | return 0; |
172 | } | |
173 | ||
03ac84f1 | 174 | static struct sg_table * |
6a2c4232 | 175 | i915_gem_object_get_pages_phys(struct drm_i915_gem_object *obj) |
00731155 | 176 | { |
93c76a3d | 177 | struct address_space *mapping = obj->base.filp->f_mapping; |
dbb4351b | 178 | drm_dma_handle_t *phys; |
6a2c4232 CW |
179 | struct sg_table *st; |
180 | struct scatterlist *sg; | |
dbb4351b | 181 | char *vaddr; |
6a2c4232 | 182 | int i; |
00731155 | 183 | |
6a2c4232 | 184 | if (WARN_ON(i915_gem_object_needs_bit17_swizzle(obj))) |
03ac84f1 | 185 | return ERR_PTR(-EINVAL); |
6a2c4232 | 186 | |
dbb4351b CW |
187 | /* Always aligning to the object size, allows a single allocation |
188 | * to handle all possible callers, and given typical object sizes, | |
189 | * the alignment of the buddy allocation will naturally match. | |
190 | */ | |
191 | phys = drm_pci_alloc(obj->base.dev, | |
192 | obj->base.size, | |
193 | roundup_pow_of_two(obj->base.size)); | |
194 | if (!phys) | |
195 | return ERR_PTR(-ENOMEM); | |
196 | ||
197 | vaddr = phys->vaddr; | |
6a2c4232 CW |
198 | for (i = 0; i < obj->base.size / PAGE_SIZE; i++) { |
199 | struct page *page; | |
200 | char *src; | |
201 | ||
202 | page = shmem_read_mapping_page(mapping, i); | |
dbb4351b CW |
203 | if (IS_ERR(page)) { |
204 | st = ERR_CAST(page); | |
205 | goto err_phys; | |
206 | } | |
6a2c4232 CW |
207 | |
208 | src = kmap_atomic(page); | |
209 | memcpy(vaddr, src, PAGE_SIZE); | |
210 | drm_clflush_virt_range(vaddr, PAGE_SIZE); | |
211 | kunmap_atomic(src); | |
212 | ||
09cbfeaf | 213 | put_page(page); |
6a2c4232 CW |
214 | vaddr += PAGE_SIZE; |
215 | } | |
216 | ||
c033666a | 217 | i915_gem_chipset_flush(to_i915(obj->base.dev)); |
6a2c4232 CW |
218 | |
219 | st = kmalloc(sizeof(*st), GFP_KERNEL); | |
dbb4351b CW |
220 | if (!st) { |
221 | st = ERR_PTR(-ENOMEM); | |
222 | goto err_phys; | |
223 | } | |
6a2c4232 CW |
224 | |
225 | if (sg_alloc_table(st, 1, GFP_KERNEL)) { | |
226 | kfree(st); | |
dbb4351b CW |
227 | st = ERR_PTR(-ENOMEM); |
228 | goto err_phys; | |
6a2c4232 CW |
229 | } |
230 | ||
231 | sg = st->sgl; | |
232 | sg->offset = 0; | |
233 | sg->length = obj->base.size; | |
00731155 | 234 | |
dbb4351b | 235 | sg_dma_address(sg) = phys->busaddr; |
6a2c4232 CW |
236 | sg_dma_len(sg) = obj->base.size; |
237 | ||
dbb4351b CW |
238 | obj->phys_handle = phys; |
239 | return st; | |
240 | ||
241 | err_phys: | |
242 | drm_pci_free(obj->base.dev, phys); | |
03ac84f1 | 243 | return st; |
6a2c4232 CW |
244 | } |
245 | ||
246 | static void | |
2b3c8317 | 247 | __i915_gem_object_release_shmem(struct drm_i915_gem_object *obj, |
e5facdf9 CW |
248 | struct sg_table *pages, |
249 | bool needs_clflush) | |
6a2c4232 | 250 | { |
a4f5ea64 | 251 | GEM_BUG_ON(obj->mm.madv == __I915_MADV_PURGED); |
00731155 | 252 | |
a4f5ea64 CW |
253 | if (obj->mm.madv == I915_MADV_DONTNEED) |
254 | obj->mm.dirty = false; | |
6a2c4232 | 255 | |
e5facdf9 CW |
256 | if (needs_clflush && |
257 | (obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0 && | |
05c34837 | 258 | !cpu_cache_is_coherent(obj->base.dev, obj->cache_level)) |
2b3c8317 | 259 | drm_clflush_sg(pages); |
03ac84f1 CW |
260 | |
261 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; | |
262 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; | |
263 | } | |
264 | ||
265 | static void | |
266 | i915_gem_object_put_pages_phys(struct drm_i915_gem_object *obj, | |
267 | struct sg_table *pages) | |
268 | { | |
e5facdf9 | 269 | __i915_gem_object_release_shmem(obj, pages, false); |
03ac84f1 | 270 | |
a4f5ea64 | 271 | if (obj->mm.dirty) { |
93c76a3d | 272 | struct address_space *mapping = obj->base.filp->f_mapping; |
6a2c4232 | 273 | char *vaddr = obj->phys_handle->vaddr; |
00731155 CW |
274 | int i; |
275 | ||
276 | for (i = 0; i < obj->base.size / PAGE_SIZE; i++) { | |
6a2c4232 CW |
277 | struct page *page; |
278 | char *dst; | |
279 | ||
280 | page = shmem_read_mapping_page(mapping, i); | |
281 | if (IS_ERR(page)) | |
282 | continue; | |
283 | ||
284 | dst = kmap_atomic(page); | |
285 | drm_clflush_virt_range(vaddr, PAGE_SIZE); | |
286 | memcpy(dst, vaddr, PAGE_SIZE); | |
287 | kunmap_atomic(dst); | |
288 | ||
289 | set_page_dirty(page); | |
a4f5ea64 | 290 | if (obj->mm.madv == I915_MADV_WILLNEED) |
00731155 | 291 | mark_page_accessed(page); |
09cbfeaf | 292 | put_page(page); |
00731155 CW |
293 | vaddr += PAGE_SIZE; |
294 | } | |
a4f5ea64 | 295 | obj->mm.dirty = false; |
00731155 CW |
296 | } |
297 | ||
03ac84f1 CW |
298 | sg_free_table(pages); |
299 | kfree(pages); | |
dbb4351b CW |
300 | |
301 | drm_pci_free(obj->base.dev, obj->phys_handle); | |
6a2c4232 CW |
302 | } |
303 | ||
304 | static void | |
305 | i915_gem_object_release_phys(struct drm_i915_gem_object *obj) | |
306 | { | |
a4f5ea64 | 307 | i915_gem_object_unpin_pages(obj); |
6a2c4232 CW |
308 | } |
309 | ||
310 | static const struct drm_i915_gem_object_ops i915_gem_phys_ops = { | |
311 | .get_pages = i915_gem_object_get_pages_phys, | |
312 | .put_pages = i915_gem_object_put_pages_phys, | |
313 | .release = i915_gem_object_release_phys, | |
314 | }; | |
315 | ||
35a9611c | 316 | int i915_gem_object_unbind(struct drm_i915_gem_object *obj) |
aa653a68 CW |
317 | { |
318 | struct i915_vma *vma; | |
319 | LIST_HEAD(still_in_list); | |
02bef8f9 CW |
320 | int ret; |
321 | ||
322 | lockdep_assert_held(&obj->base.dev->struct_mutex); | |
aa653a68 | 323 | |
02bef8f9 CW |
324 | /* Closed vma are removed from the obj->vma_list - but they may |
325 | * still have an active binding on the object. To remove those we | |
326 | * must wait for all rendering to complete to the object (as unbinding | |
327 | * must anyway), and retire the requests. | |
aa653a68 | 328 | */ |
e95433c7 CW |
329 | ret = i915_gem_object_wait(obj, |
330 | I915_WAIT_INTERRUPTIBLE | | |
331 | I915_WAIT_LOCKED | | |
332 | I915_WAIT_ALL, | |
333 | MAX_SCHEDULE_TIMEOUT, | |
334 | NULL); | |
02bef8f9 CW |
335 | if (ret) |
336 | return ret; | |
337 | ||
338 | i915_gem_retire_requests(to_i915(obj->base.dev)); | |
339 | ||
aa653a68 CW |
340 | while ((vma = list_first_entry_or_null(&obj->vma_list, |
341 | struct i915_vma, | |
342 | obj_link))) { | |
343 | list_move_tail(&vma->obj_link, &still_in_list); | |
344 | ret = i915_vma_unbind(vma); | |
345 | if (ret) | |
346 | break; | |
347 | } | |
348 | list_splice(&still_in_list, &obj->vma_list); | |
349 | ||
350 | return ret; | |
351 | } | |
352 | ||
e95433c7 CW |
353 | static long |
354 | i915_gem_object_wait_fence(struct dma_fence *fence, | |
355 | unsigned int flags, | |
356 | long timeout, | |
357 | struct intel_rps_client *rps) | |
00e60f26 | 358 | { |
e95433c7 | 359 | struct drm_i915_gem_request *rq; |
00e60f26 | 360 | |
e95433c7 | 361 | BUILD_BUG_ON(I915_WAIT_INTERRUPTIBLE != 0x1); |
00e60f26 | 362 | |
e95433c7 CW |
363 | if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &fence->flags)) |
364 | return timeout; | |
365 | ||
366 | if (!dma_fence_is_i915(fence)) | |
367 | return dma_fence_wait_timeout(fence, | |
368 | flags & I915_WAIT_INTERRUPTIBLE, | |
369 | timeout); | |
370 | ||
371 | rq = to_request(fence); | |
372 | if (i915_gem_request_completed(rq)) | |
373 | goto out; | |
374 | ||
375 | /* This client is about to stall waiting for the GPU. In many cases | |
376 | * this is undesirable and limits the throughput of the system, as | |
377 | * many clients cannot continue processing user input/output whilst | |
378 | * blocked. RPS autotuning may take tens of milliseconds to respond | |
379 | * to the GPU load and thus incurs additional latency for the client. | |
380 | * We can circumvent that by promoting the GPU frequency to maximum | |
381 | * before we wait. This makes the GPU throttle up much more quickly | |
382 | * (good for benchmarks and user experience, e.g. window animations), | |
383 | * but at a cost of spending more power processing the workload | |
384 | * (bad for battery). Not all clients even want their results | |
385 | * immediately and for them we should just let the GPU select its own | |
386 | * frequency to maximise efficiency. To prevent a single client from | |
387 | * forcing the clocks too high for the whole system, we only allow | |
388 | * each client to waitboost once in a busy period. | |
389 | */ | |
390 | if (rps) { | |
391 | if (INTEL_GEN(rq->i915) >= 6) | |
392 | gen6_rps_boost(rq->i915, rps, rq->emitted_jiffies); | |
393 | else | |
394 | rps = NULL; | |
00e60f26 CW |
395 | } |
396 | ||
e95433c7 CW |
397 | timeout = i915_wait_request(rq, flags, timeout); |
398 | ||
399 | out: | |
400 | if (flags & I915_WAIT_LOCKED && i915_gem_request_completed(rq)) | |
401 | i915_gem_request_retire_upto(rq); | |
402 | ||
cb399eab | 403 | if (rps && rq->global_seqno == intel_engine_last_submit(rq->engine)) { |
e95433c7 CW |
404 | /* The GPU is now idle and this client has stalled. |
405 | * Since no other client has submitted a request in the | |
406 | * meantime, assume that this client is the only one | |
407 | * supplying work to the GPU but is unable to keep that | |
408 | * work supplied because it is waiting. Since the GPU is | |
409 | * then never kept fully busy, RPS autoclocking will | |
410 | * keep the clocks relatively low, causing further delays. | |
411 | * Compensate by giving the synchronous client credit for | |
412 | * a waitboost next time. | |
413 | */ | |
414 | spin_lock(&rq->i915->rps.client_lock); | |
415 | list_del_init(&rps->link); | |
416 | spin_unlock(&rq->i915->rps.client_lock); | |
417 | } | |
418 | ||
419 | return timeout; | |
420 | } | |
421 | ||
422 | static long | |
423 | i915_gem_object_wait_reservation(struct reservation_object *resv, | |
424 | unsigned int flags, | |
425 | long timeout, | |
426 | struct intel_rps_client *rps) | |
427 | { | |
428 | struct dma_fence *excl; | |
429 | ||
430 | if (flags & I915_WAIT_ALL) { | |
431 | struct dma_fence **shared; | |
432 | unsigned int count, i; | |
00e60f26 CW |
433 | int ret; |
434 | ||
e95433c7 CW |
435 | ret = reservation_object_get_fences_rcu(resv, |
436 | &excl, &count, &shared); | |
00e60f26 CW |
437 | if (ret) |
438 | return ret; | |
00e60f26 | 439 | |
e95433c7 CW |
440 | for (i = 0; i < count; i++) { |
441 | timeout = i915_gem_object_wait_fence(shared[i], | |
442 | flags, timeout, | |
443 | rps); | |
444 | if (timeout <= 0) | |
445 | break; | |
00e60f26 | 446 | |
e95433c7 CW |
447 | dma_fence_put(shared[i]); |
448 | } | |
449 | ||
450 | for (; i < count; i++) | |
451 | dma_fence_put(shared[i]); | |
452 | kfree(shared); | |
453 | } else { | |
454 | excl = reservation_object_get_excl_rcu(resv); | |
00e60f26 CW |
455 | } |
456 | ||
e95433c7 CW |
457 | if (excl && timeout > 0) |
458 | timeout = i915_gem_object_wait_fence(excl, flags, timeout, rps); | |
459 | ||
460 | dma_fence_put(excl); | |
461 | ||
462 | return timeout; | |
00e60f26 CW |
463 | } |
464 | ||
6b5e90f5 CW |
465 | static void __fence_set_priority(struct dma_fence *fence, int prio) |
466 | { | |
467 | struct drm_i915_gem_request *rq; | |
468 | struct intel_engine_cs *engine; | |
469 | ||
470 | if (!dma_fence_is_i915(fence)) | |
471 | return; | |
472 | ||
473 | rq = to_request(fence); | |
474 | engine = rq->engine; | |
475 | if (!engine->schedule) | |
476 | return; | |
477 | ||
478 | engine->schedule(rq, prio); | |
479 | } | |
480 | ||
481 | static void fence_set_priority(struct dma_fence *fence, int prio) | |
482 | { | |
483 | /* Recurse once into a fence-array */ | |
484 | if (dma_fence_is_array(fence)) { | |
485 | struct dma_fence_array *array = to_dma_fence_array(fence); | |
486 | int i; | |
487 | ||
488 | for (i = 0; i < array->num_fences; i++) | |
489 | __fence_set_priority(array->fences[i], prio); | |
490 | } else { | |
491 | __fence_set_priority(fence, prio); | |
492 | } | |
493 | } | |
494 | ||
495 | int | |
496 | i915_gem_object_wait_priority(struct drm_i915_gem_object *obj, | |
497 | unsigned int flags, | |
498 | int prio) | |
499 | { | |
500 | struct dma_fence *excl; | |
501 | ||
502 | if (flags & I915_WAIT_ALL) { | |
503 | struct dma_fence **shared; | |
504 | unsigned int count, i; | |
505 | int ret; | |
506 | ||
507 | ret = reservation_object_get_fences_rcu(obj->resv, | |
508 | &excl, &count, &shared); | |
509 | if (ret) | |
510 | return ret; | |
511 | ||
512 | for (i = 0; i < count; i++) { | |
513 | fence_set_priority(shared[i], prio); | |
514 | dma_fence_put(shared[i]); | |
515 | } | |
516 | ||
517 | kfree(shared); | |
518 | } else { | |
519 | excl = reservation_object_get_excl_rcu(obj->resv); | |
520 | } | |
521 | ||
522 | if (excl) { | |
523 | fence_set_priority(excl, prio); | |
524 | dma_fence_put(excl); | |
525 | } | |
526 | return 0; | |
527 | } | |
528 | ||
e95433c7 CW |
529 | /** |
530 | * Waits for rendering to the object to be completed | |
531 | * @obj: i915 gem object | |
532 | * @flags: how to wait (under a lock, for all rendering or just for writes etc) | |
533 | * @timeout: how long to wait | |
534 | * @rps: client (user process) to charge for any waitboosting | |
00e60f26 | 535 | */ |
e95433c7 CW |
536 | int |
537 | i915_gem_object_wait(struct drm_i915_gem_object *obj, | |
538 | unsigned int flags, | |
539 | long timeout, | |
540 | struct intel_rps_client *rps) | |
00e60f26 | 541 | { |
e95433c7 CW |
542 | might_sleep(); |
543 | #if IS_ENABLED(CONFIG_LOCKDEP) | |
544 | GEM_BUG_ON(debug_locks && | |
545 | !!lockdep_is_held(&obj->base.dev->struct_mutex) != | |
546 | !!(flags & I915_WAIT_LOCKED)); | |
547 | #endif | |
548 | GEM_BUG_ON(timeout < 0); | |
00e60f26 | 549 | |
d07f0e59 CW |
550 | timeout = i915_gem_object_wait_reservation(obj->resv, |
551 | flags, timeout, | |
552 | rps); | |
e95433c7 | 553 | return timeout < 0 ? timeout : 0; |
00e60f26 CW |
554 | } |
555 | ||
556 | static struct intel_rps_client *to_rps_client(struct drm_file *file) | |
557 | { | |
558 | struct drm_i915_file_private *fpriv = file->driver_priv; | |
559 | ||
560 | return &fpriv->rps; | |
561 | } | |
562 | ||
00731155 CW |
563 | int |
564 | i915_gem_object_attach_phys(struct drm_i915_gem_object *obj, | |
565 | int align) | |
566 | { | |
6a2c4232 | 567 | int ret; |
00731155 | 568 | |
dbb4351b CW |
569 | if (align > obj->base.size) |
570 | return -EINVAL; | |
00731155 | 571 | |
dbb4351b | 572 | if (obj->ops == &i915_gem_phys_ops) |
00731155 | 573 | return 0; |
00731155 | 574 | |
a4f5ea64 | 575 | if (obj->mm.madv != I915_MADV_WILLNEED) |
00731155 CW |
576 | return -EFAULT; |
577 | ||
578 | if (obj->base.filp == NULL) | |
579 | return -EINVAL; | |
580 | ||
4717ca9e CW |
581 | ret = i915_gem_object_unbind(obj); |
582 | if (ret) | |
583 | return ret; | |
584 | ||
548625ee | 585 | __i915_gem_object_put_pages(obj, I915_MM_NORMAL); |
03ac84f1 CW |
586 | if (obj->mm.pages) |
587 | return -EBUSY; | |
6a2c4232 | 588 | |
6a2c4232 CW |
589 | obj->ops = &i915_gem_phys_ops; |
590 | ||
a4f5ea64 | 591 | return i915_gem_object_pin_pages(obj); |
00731155 CW |
592 | } |
593 | ||
594 | static int | |
595 | i915_gem_phys_pwrite(struct drm_i915_gem_object *obj, | |
596 | struct drm_i915_gem_pwrite *args, | |
03ac84f1 | 597 | struct drm_file *file) |
00731155 | 598 | { |
00731155 | 599 | void *vaddr = obj->phys_handle->vaddr + args->offset; |
3ed605bc | 600 | char __user *user_data = u64_to_user_ptr(args->data_ptr); |
6a2c4232 CW |
601 | |
602 | /* We manually control the domain here and pretend that it | |
603 | * remains coherent i.e. in the GTT domain, like shmem_pwrite. | |
604 | */ | |
77a0d1ca | 605 | intel_fb_obj_invalidate(obj, ORIGIN_CPU); |
10466d2a CW |
606 | if (copy_from_user(vaddr, user_data, args->size)) |
607 | return -EFAULT; | |
00731155 | 608 | |
6a2c4232 | 609 | drm_clflush_virt_range(vaddr, args->size); |
10466d2a | 610 | i915_gem_chipset_flush(to_i915(obj->base.dev)); |
063e4e6b | 611 | |
de152b62 | 612 | intel_fb_obj_flush(obj, false, ORIGIN_CPU); |
10466d2a | 613 | return 0; |
00731155 CW |
614 | } |
615 | ||
187685cb | 616 | void *i915_gem_object_alloc(struct drm_i915_private *dev_priv) |
42dcedd4 | 617 | { |
efab6d8d | 618 | return kmem_cache_zalloc(dev_priv->objects, GFP_KERNEL); |
42dcedd4 CW |
619 | } |
620 | ||
621 | void i915_gem_object_free(struct drm_i915_gem_object *obj) | |
622 | { | |
fac5e23e | 623 | struct drm_i915_private *dev_priv = to_i915(obj->base.dev); |
efab6d8d | 624 | kmem_cache_free(dev_priv->objects, obj); |
42dcedd4 CW |
625 | } |
626 | ||
ff72145b DA |
627 | static int |
628 | i915_gem_create(struct drm_file *file, | |
12d79d78 | 629 | struct drm_i915_private *dev_priv, |
ff72145b DA |
630 | uint64_t size, |
631 | uint32_t *handle_p) | |
673a394b | 632 | { |
05394f39 | 633 | struct drm_i915_gem_object *obj; |
a1a2d1d3 PP |
634 | int ret; |
635 | u32 handle; | |
673a394b | 636 | |
ff72145b | 637 | size = roundup(size, PAGE_SIZE); |
8ffc0246 CW |
638 | if (size == 0) |
639 | return -EINVAL; | |
673a394b EA |
640 | |
641 | /* Allocate the new object */ | |
12d79d78 | 642 | obj = i915_gem_object_create(dev_priv, size); |
fe3db79b CW |
643 | if (IS_ERR(obj)) |
644 | return PTR_ERR(obj); | |
673a394b | 645 | |
05394f39 | 646 | ret = drm_gem_handle_create(file, &obj->base, &handle); |
202f2fef | 647 | /* drop reference from allocate - handle holds it now */ |
f0cd5182 | 648 | i915_gem_object_put(obj); |
d861e338 DV |
649 | if (ret) |
650 | return ret; | |
202f2fef | 651 | |
ff72145b | 652 | *handle_p = handle; |
673a394b EA |
653 | return 0; |
654 | } | |
655 | ||
ff72145b DA |
656 | int |
657 | i915_gem_dumb_create(struct drm_file *file, | |
658 | struct drm_device *dev, | |
659 | struct drm_mode_create_dumb *args) | |
660 | { | |
661 | /* have to work out size/pitch and return them */ | |
de45eaf7 | 662 | args->pitch = ALIGN(args->width * DIV_ROUND_UP(args->bpp, 8), 64); |
ff72145b | 663 | args->size = args->pitch * args->height; |
12d79d78 | 664 | return i915_gem_create(file, to_i915(dev), |
da6b51d0 | 665 | args->size, &args->handle); |
ff72145b DA |
666 | } |
667 | ||
ff72145b DA |
668 | /** |
669 | * Creates a new mm object and returns a handle to it. | |
14bb2c11 TU |
670 | * @dev: drm device pointer |
671 | * @data: ioctl data blob | |
672 | * @file: drm file pointer | |
ff72145b DA |
673 | */ |
674 | int | |
675 | i915_gem_create_ioctl(struct drm_device *dev, void *data, | |
676 | struct drm_file *file) | |
677 | { | |
12d79d78 | 678 | struct drm_i915_private *dev_priv = to_i915(dev); |
ff72145b | 679 | struct drm_i915_gem_create *args = data; |
63ed2cb2 | 680 | |
12d79d78 | 681 | i915_gem_flush_free_objects(dev_priv); |
fbbd37b3 | 682 | |
12d79d78 | 683 | return i915_gem_create(file, dev_priv, |
da6b51d0 | 684 | args->size, &args->handle); |
ff72145b DA |
685 | } |
686 | ||
8461d226 DV |
687 | static inline int |
688 | __copy_to_user_swizzled(char __user *cpu_vaddr, | |
689 | const char *gpu_vaddr, int gpu_offset, | |
690 | int length) | |
691 | { | |
692 | int ret, cpu_offset = 0; | |
693 | ||
694 | while (length > 0) { | |
695 | int cacheline_end = ALIGN(gpu_offset + 1, 64); | |
696 | int this_length = min(cacheline_end - gpu_offset, length); | |
697 | int swizzled_gpu_offset = gpu_offset ^ 64; | |
698 | ||
699 | ret = __copy_to_user(cpu_vaddr + cpu_offset, | |
700 | gpu_vaddr + swizzled_gpu_offset, | |
701 | this_length); | |
702 | if (ret) | |
703 | return ret + length; | |
704 | ||
705 | cpu_offset += this_length; | |
706 | gpu_offset += this_length; | |
707 | length -= this_length; | |
708 | } | |
709 | ||
710 | return 0; | |
711 | } | |
712 | ||
8c59967c | 713 | static inline int |
4f0c7cfb BW |
714 | __copy_from_user_swizzled(char *gpu_vaddr, int gpu_offset, |
715 | const char __user *cpu_vaddr, | |
8c59967c DV |
716 | int length) |
717 | { | |
718 | int ret, cpu_offset = 0; | |
719 | ||
720 | while (length > 0) { | |
721 | int cacheline_end = ALIGN(gpu_offset + 1, 64); | |
722 | int this_length = min(cacheline_end - gpu_offset, length); | |
723 | int swizzled_gpu_offset = gpu_offset ^ 64; | |
724 | ||
725 | ret = __copy_from_user(gpu_vaddr + swizzled_gpu_offset, | |
726 | cpu_vaddr + cpu_offset, | |
727 | this_length); | |
728 | if (ret) | |
729 | return ret + length; | |
730 | ||
731 | cpu_offset += this_length; | |
732 | gpu_offset += this_length; | |
733 | length -= this_length; | |
734 | } | |
735 | ||
736 | return 0; | |
737 | } | |
738 | ||
4c914c0c BV |
739 | /* |
740 | * Pins the specified object's pages and synchronizes the object with | |
741 | * GPU accesses. Sets needs_clflush to non-zero if the caller should | |
742 | * flush the object from the CPU cache. | |
743 | */ | |
744 | int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj, | |
43394c7d | 745 | unsigned int *needs_clflush) |
4c914c0c BV |
746 | { |
747 | int ret; | |
748 | ||
e95433c7 | 749 | lockdep_assert_held(&obj->base.dev->struct_mutex); |
4c914c0c | 750 | |
e95433c7 | 751 | *needs_clflush = 0; |
43394c7d CW |
752 | if (!i915_gem_object_has_struct_page(obj)) |
753 | return -ENODEV; | |
4c914c0c | 754 | |
e95433c7 CW |
755 | ret = i915_gem_object_wait(obj, |
756 | I915_WAIT_INTERRUPTIBLE | | |
757 | I915_WAIT_LOCKED, | |
758 | MAX_SCHEDULE_TIMEOUT, | |
759 | NULL); | |
c13d87ea CW |
760 | if (ret) |
761 | return ret; | |
762 | ||
a4f5ea64 | 763 | ret = i915_gem_object_pin_pages(obj); |
9764951e CW |
764 | if (ret) |
765 | return ret; | |
766 | ||
a314d5cb CW |
767 | i915_gem_object_flush_gtt_write_domain(obj); |
768 | ||
43394c7d CW |
769 | /* If we're not in the cpu read domain, set ourself into the gtt |
770 | * read domain and manually flush cachelines (if required). This | |
771 | * optimizes for the case when the gpu will dirty the data | |
772 | * anyway again before the next pread happens. | |
773 | */ | |
774 | if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU)) | |
4c914c0c BV |
775 | *needs_clflush = !cpu_cache_is_coherent(obj->base.dev, |
776 | obj->cache_level); | |
43394c7d | 777 | |
43394c7d CW |
778 | if (*needs_clflush && !static_cpu_has(X86_FEATURE_CLFLUSH)) { |
779 | ret = i915_gem_object_set_to_cpu_domain(obj, false); | |
9764951e CW |
780 | if (ret) |
781 | goto err_unpin; | |
782 | ||
43394c7d | 783 | *needs_clflush = 0; |
4c914c0c BV |
784 | } |
785 | ||
9764951e | 786 | /* return with the pages pinned */ |
43394c7d | 787 | return 0; |
9764951e CW |
788 | |
789 | err_unpin: | |
790 | i915_gem_object_unpin_pages(obj); | |
791 | return ret; | |
43394c7d CW |
792 | } |
793 | ||
794 | int i915_gem_obj_prepare_shmem_write(struct drm_i915_gem_object *obj, | |
795 | unsigned int *needs_clflush) | |
796 | { | |
797 | int ret; | |
798 | ||
e95433c7 CW |
799 | lockdep_assert_held(&obj->base.dev->struct_mutex); |
800 | ||
43394c7d CW |
801 | *needs_clflush = 0; |
802 | if (!i915_gem_object_has_struct_page(obj)) | |
803 | return -ENODEV; | |
804 | ||
e95433c7 CW |
805 | ret = i915_gem_object_wait(obj, |
806 | I915_WAIT_INTERRUPTIBLE | | |
807 | I915_WAIT_LOCKED | | |
808 | I915_WAIT_ALL, | |
809 | MAX_SCHEDULE_TIMEOUT, | |
810 | NULL); | |
43394c7d CW |
811 | if (ret) |
812 | return ret; | |
813 | ||
a4f5ea64 | 814 | ret = i915_gem_object_pin_pages(obj); |
9764951e CW |
815 | if (ret) |
816 | return ret; | |
817 | ||
a314d5cb CW |
818 | i915_gem_object_flush_gtt_write_domain(obj); |
819 | ||
43394c7d CW |
820 | /* If we're not in the cpu write domain, set ourself into the |
821 | * gtt write domain and manually flush cachelines (as required). | |
822 | * This optimizes for the case when the gpu will use the data | |
823 | * right away and we therefore have to clflush anyway. | |
824 | */ | |
825 | if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) | |
826 | *needs_clflush |= cpu_write_needs_clflush(obj) << 1; | |
827 | ||
828 | /* Same trick applies to invalidate partially written cachelines read | |
829 | * before writing. | |
830 | */ | |
831 | if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU)) | |
832 | *needs_clflush |= !cpu_cache_is_coherent(obj->base.dev, | |
833 | obj->cache_level); | |
834 | ||
43394c7d CW |
835 | if (*needs_clflush && !static_cpu_has(X86_FEATURE_CLFLUSH)) { |
836 | ret = i915_gem_object_set_to_cpu_domain(obj, true); | |
9764951e CW |
837 | if (ret) |
838 | goto err_unpin; | |
839 | ||
43394c7d CW |
840 | *needs_clflush = 0; |
841 | } | |
842 | ||
843 | if ((*needs_clflush & CLFLUSH_AFTER) == 0) | |
844 | obj->cache_dirty = true; | |
845 | ||
846 | intel_fb_obj_invalidate(obj, ORIGIN_CPU); | |
a4f5ea64 | 847 | obj->mm.dirty = true; |
9764951e | 848 | /* return with the pages pinned */ |
43394c7d | 849 | return 0; |
9764951e CW |
850 | |
851 | err_unpin: | |
852 | i915_gem_object_unpin_pages(obj); | |
853 | return ret; | |
4c914c0c BV |
854 | } |
855 | ||
23c18c71 DV |
856 | static void |
857 | shmem_clflush_swizzled_range(char *addr, unsigned long length, | |
858 | bool swizzled) | |
859 | { | |
e7e58eb5 | 860 | if (unlikely(swizzled)) { |
23c18c71 DV |
861 | unsigned long start = (unsigned long) addr; |
862 | unsigned long end = (unsigned long) addr + length; | |
863 | ||
864 | /* For swizzling simply ensure that we always flush both | |
865 | * channels. Lame, but simple and it works. Swizzled | |
866 | * pwrite/pread is far from a hotpath - current userspace | |
867 | * doesn't use it at all. */ | |
868 | start = round_down(start, 128); | |
869 | end = round_up(end, 128); | |
870 | ||
871 | drm_clflush_virt_range((void *)start, end - start); | |
872 | } else { | |
873 | drm_clflush_virt_range(addr, length); | |
874 | } | |
875 | ||
876 | } | |
877 | ||
d174bd64 DV |
878 | /* Only difference to the fast-path function is that this can handle bit17 |
879 | * and uses non-atomic copy and kmap functions. */ | |
880 | static int | |
bb6dc8d9 | 881 | shmem_pread_slow(struct page *page, int offset, int length, |
d174bd64 DV |
882 | char __user *user_data, |
883 | bool page_do_bit17_swizzling, bool needs_clflush) | |
884 | { | |
885 | char *vaddr; | |
886 | int ret; | |
887 | ||
888 | vaddr = kmap(page); | |
889 | if (needs_clflush) | |
bb6dc8d9 | 890 | shmem_clflush_swizzled_range(vaddr + offset, length, |
23c18c71 | 891 | page_do_bit17_swizzling); |
d174bd64 DV |
892 | |
893 | if (page_do_bit17_swizzling) | |
bb6dc8d9 | 894 | ret = __copy_to_user_swizzled(user_data, vaddr, offset, length); |
d174bd64 | 895 | else |
bb6dc8d9 | 896 | ret = __copy_to_user(user_data, vaddr + offset, length); |
d174bd64 DV |
897 | kunmap(page); |
898 | ||
f60d7f0c | 899 | return ret ? - EFAULT : 0; |
d174bd64 DV |
900 | } |
901 | ||
bb6dc8d9 CW |
902 | static int |
903 | shmem_pread(struct page *page, int offset, int length, char __user *user_data, | |
904 | bool page_do_bit17_swizzling, bool needs_clflush) | |
905 | { | |
906 | int ret; | |
907 | ||
908 | ret = -ENODEV; | |
909 | if (!page_do_bit17_swizzling) { | |
910 | char *vaddr = kmap_atomic(page); | |
911 | ||
912 | if (needs_clflush) | |
913 | drm_clflush_virt_range(vaddr + offset, length); | |
914 | ret = __copy_to_user_inatomic(user_data, vaddr + offset, length); | |
915 | kunmap_atomic(vaddr); | |
916 | } | |
917 | if (ret == 0) | |
918 | return 0; | |
919 | ||
920 | return shmem_pread_slow(page, offset, length, user_data, | |
921 | page_do_bit17_swizzling, needs_clflush); | |
922 | } | |
923 | ||
924 | static int | |
925 | i915_gem_shmem_pread(struct drm_i915_gem_object *obj, | |
926 | struct drm_i915_gem_pread *args) | |
927 | { | |
928 | char __user *user_data; | |
929 | u64 remain; | |
930 | unsigned int obj_do_bit17_swizzling; | |
931 | unsigned int needs_clflush; | |
932 | unsigned int idx, offset; | |
933 | int ret; | |
934 | ||
935 | obj_do_bit17_swizzling = 0; | |
936 | if (i915_gem_object_needs_bit17_swizzle(obj)) | |
937 | obj_do_bit17_swizzling = BIT(17); | |
938 | ||
939 | ret = mutex_lock_interruptible(&obj->base.dev->struct_mutex); | |
940 | if (ret) | |
941 | return ret; | |
942 | ||
943 | ret = i915_gem_obj_prepare_shmem_read(obj, &needs_clflush); | |
944 | mutex_unlock(&obj->base.dev->struct_mutex); | |
945 | if (ret) | |
946 | return ret; | |
947 | ||
948 | remain = args->size; | |
949 | user_data = u64_to_user_ptr(args->data_ptr); | |
950 | offset = offset_in_page(args->offset); | |
951 | for (idx = args->offset >> PAGE_SHIFT; remain; idx++) { | |
952 | struct page *page = i915_gem_object_get_page(obj, idx); | |
953 | int length; | |
954 | ||
955 | length = remain; | |
956 | if (offset + length > PAGE_SIZE) | |
957 | length = PAGE_SIZE - offset; | |
958 | ||
959 | ret = shmem_pread(page, offset, length, user_data, | |
960 | page_to_phys(page) & obj_do_bit17_swizzling, | |
961 | needs_clflush); | |
962 | if (ret) | |
963 | break; | |
964 | ||
965 | remain -= length; | |
966 | user_data += length; | |
967 | offset = 0; | |
968 | } | |
969 | ||
970 | i915_gem_obj_finish_shmem_access(obj); | |
971 | return ret; | |
972 | } | |
973 | ||
974 | static inline bool | |
975 | gtt_user_read(struct io_mapping *mapping, | |
976 | loff_t base, int offset, | |
977 | char __user *user_data, int length) | |
b50a5371 | 978 | { |
b50a5371 | 979 | void *vaddr; |
bb6dc8d9 | 980 | unsigned long unwritten; |
b50a5371 | 981 | |
b50a5371 | 982 | /* We can use the cpu mem copy function because this is X86. */ |
bb6dc8d9 CW |
983 | vaddr = (void __force *)io_mapping_map_atomic_wc(mapping, base); |
984 | unwritten = __copy_to_user_inatomic(user_data, vaddr + offset, length); | |
985 | io_mapping_unmap_atomic(vaddr); | |
986 | if (unwritten) { | |
987 | vaddr = (void __force *) | |
988 | io_mapping_map_wc(mapping, base, PAGE_SIZE); | |
989 | unwritten = copy_to_user(user_data, vaddr + offset, length); | |
990 | io_mapping_unmap(vaddr); | |
991 | } | |
b50a5371 AS |
992 | return unwritten; |
993 | } | |
994 | ||
995 | static int | |
bb6dc8d9 CW |
996 | i915_gem_gtt_pread(struct drm_i915_gem_object *obj, |
997 | const struct drm_i915_gem_pread *args) | |
b50a5371 | 998 | { |
bb6dc8d9 CW |
999 | struct drm_i915_private *i915 = to_i915(obj->base.dev); |
1000 | struct i915_ggtt *ggtt = &i915->ggtt; | |
b50a5371 | 1001 | struct drm_mm_node node; |
bb6dc8d9 CW |
1002 | struct i915_vma *vma; |
1003 | void __user *user_data; | |
1004 | u64 remain, offset; | |
b50a5371 AS |
1005 | int ret; |
1006 | ||
bb6dc8d9 CW |
1007 | ret = mutex_lock_interruptible(&i915->drm.struct_mutex); |
1008 | if (ret) | |
1009 | return ret; | |
1010 | ||
1011 | intel_runtime_pm_get(i915); | |
1012 | vma = i915_gem_object_ggtt_pin(obj, NULL, 0, 0, | |
1013 | PIN_MAPPABLE | PIN_NONBLOCK); | |
18034584 CW |
1014 | if (!IS_ERR(vma)) { |
1015 | node.start = i915_ggtt_offset(vma); | |
1016 | node.allocated = false; | |
49ef5294 | 1017 | ret = i915_vma_put_fence(vma); |
18034584 CW |
1018 | if (ret) { |
1019 | i915_vma_unpin(vma); | |
1020 | vma = ERR_PTR(ret); | |
1021 | } | |
1022 | } | |
058d88c4 | 1023 | if (IS_ERR(vma)) { |
bb6dc8d9 | 1024 | ret = insert_mappable_node(ggtt, &node, PAGE_SIZE); |
b50a5371 | 1025 | if (ret) |
bb6dc8d9 CW |
1026 | goto out_unlock; |
1027 | GEM_BUG_ON(!node.allocated); | |
b50a5371 AS |
1028 | } |
1029 | ||
1030 | ret = i915_gem_object_set_to_gtt_domain(obj, false); | |
1031 | if (ret) | |
1032 | goto out_unpin; | |
1033 | ||
bb6dc8d9 | 1034 | mutex_unlock(&i915->drm.struct_mutex); |
b50a5371 | 1035 | |
bb6dc8d9 CW |
1036 | user_data = u64_to_user_ptr(args->data_ptr); |
1037 | remain = args->size; | |
1038 | offset = args->offset; | |
b50a5371 AS |
1039 | |
1040 | while (remain > 0) { | |
1041 | /* Operation in this page | |
1042 | * | |
1043 | * page_base = page offset within aperture | |
1044 | * page_offset = offset within page | |
1045 | * page_length = bytes to copy for this page | |
1046 | */ | |
1047 | u32 page_base = node.start; | |
1048 | unsigned page_offset = offset_in_page(offset); | |
1049 | unsigned page_length = PAGE_SIZE - page_offset; | |
1050 | page_length = remain < page_length ? remain : page_length; | |
1051 | if (node.allocated) { | |
1052 | wmb(); | |
1053 | ggtt->base.insert_page(&ggtt->base, | |
1054 | i915_gem_object_get_dma_address(obj, offset >> PAGE_SHIFT), | |
bb6dc8d9 | 1055 | node.start, I915_CACHE_NONE, 0); |
b50a5371 AS |
1056 | wmb(); |
1057 | } else { | |
1058 | page_base += offset & PAGE_MASK; | |
1059 | } | |
bb6dc8d9 CW |
1060 | |
1061 | if (gtt_user_read(&ggtt->mappable, page_base, page_offset, | |
1062 | user_data, page_length)) { | |
b50a5371 AS |
1063 | ret = -EFAULT; |
1064 | break; | |
1065 | } | |
1066 | ||
1067 | remain -= page_length; | |
1068 | user_data += page_length; | |
1069 | offset += page_length; | |
1070 | } | |
1071 | ||
bb6dc8d9 | 1072 | mutex_lock(&i915->drm.struct_mutex); |
b50a5371 AS |
1073 | out_unpin: |
1074 | if (node.allocated) { | |
1075 | wmb(); | |
1076 | ggtt->base.clear_range(&ggtt->base, | |
4fb84d99 | 1077 | node.start, node.size); |
b50a5371 AS |
1078 | remove_mappable_node(&node); |
1079 | } else { | |
058d88c4 | 1080 | i915_vma_unpin(vma); |
b50a5371 | 1081 | } |
bb6dc8d9 CW |
1082 | out_unlock: |
1083 | intel_runtime_pm_put(i915); | |
1084 | mutex_unlock(&i915->drm.struct_mutex); | |
f60d7f0c | 1085 | |
eb01459f EA |
1086 | return ret; |
1087 | } | |
1088 | ||
673a394b EA |
1089 | /** |
1090 | * Reads data from the object referenced by handle. | |
14bb2c11 TU |
1091 | * @dev: drm device pointer |
1092 | * @data: ioctl data blob | |
1093 | * @file: drm file pointer | |
673a394b EA |
1094 | * |
1095 | * On error, the contents of *data are undefined. | |
1096 | */ | |
1097 | int | |
1098 | i915_gem_pread_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 1099 | struct drm_file *file) |
673a394b EA |
1100 | { |
1101 | struct drm_i915_gem_pread *args = data; | |
05394f39 | 1102 | struct drm_i915_gem_object *obj; |
bb6dc8d9 | 1103 | int ret; |
673a394b | 1104 | |
51311d0a CW |
1105 | if (args->size == 0) |
1106 | return 0; | |
1107 | ||
1108 | if (!access_ok(VERIFY_WRITE, | |
3ed605bc | 1109 | u64_to_user_ptr(args->data_ptr), |
51311d0a CW |
1110 | args->size)) |
1111 | return -EFAULT; | |
1112 | ||
03ac0642 | 1113 | obj = i915_gem_object_lookup(file, args->handle); |
258a5ede CW |
1114 | if (!obj) |
1115 | return -ENOENT; | |
673a394b | 1116 | |
7dcd2499 | 1117 | /* Bounds check source. */ |
966d5bf5 | 1118 | if (range_overflows_t(u64, args->offset, args->size, obj->base.size)) { |
ce9d419d | 1119 | ret = -EINVAL; |
bb6dc8d9 | 1120 | goto out; |
ce9d419d CW |
1121 | } |
1122 | ||
db53a302 CW |
1123 | trace_i915_gem_object_pread(obj, args->offset, args->size); |
1124 | ||
e95433c7 CW |
1125 | ret = i915_gem_object_wait(obj, |
1126 | I915_WAIT_INTERRUPTIBLE, | |
1127 | MAX_SCHEDULE_TIMEOUT, | |
1128 | to_rps_client(file)); | |
258a5ede | 1129 | if (ret) |
bb6dc8d9 | 1130 | goto out; |
258a5ede | 1131 | |
bb6dc8d9 | 1132 | ret = i915_gem_object_pin_pages(obj); |
258a5ede | 1133 | if (ret) |
bb6dc8d9 | 1134 | goto out; |
673a394b | 1135 | |
bb6dc8d9 | 1136 | ret = i915_gem_shmem_pread(obj, args); |
9c870d03 | 1137 | if (ret == -EFAULT || ret == -ENODEV) |
bb6dc8d9 | 1138 | ret = i915_gem_gtt_pread(obj, args); |
b50a5371 | 1139 | |
bb6dc8d9 CW |
1140 | i915_gem_object_unpin_pages(obj); |
1141 | out: | |
f0cd5182 | 1142 | i915_gem_object_put(obj); |
eb01459f | 1143 | return ret; |
673a394b EA |
1144 | } |
1145 | ||
0839ccb8 KP |
1146 | /* This is the fast write path which cannot handle |
1147 | * page faults in the source data | |
9b7530cc | 1148 | */ |
0839ccb8 | 1149 | |
fe115628 CW |
1150 | static inline bool |
1151 | ggtt_write(struct io_mapping *mapping, | |
1152 | loff_t base, int offset, | |
1153 | char __user *user_data, int length) | |
9b7530cc | 1154 | { |
4f0c7cfb | 1155 | void *vaddr; |
0839ccb8 | 1156 | unsigned long unwritten; |
9b7530cc | 1157 | |
4f0c7cfb | 1158 | /* We can use the cpu mem copy function because this is X86. */ |
fe115628 CW |
1159 | vaddr = (void __force *)io_mapping_map_atomic_wc(mapping, base); |
1160 | unwritten = __copy_from_user_inatomic_nocache(vaddr + offset, | |
0839ccb8 | 1161 | user_data, length); |
fe115628 CW |
1162 | io_mapping_unmap_atomic(vaddr); |
1163 | if (unwritten) { | |
1164 | vaddr = (void __force *) | |
1165 | io_mapping_map_wc(mapping, base, PAGE_SIZE); | |
1166 | unwritten = copy_from_user(vaddr + offset, user_data, length); | |
1167 | io_mapping_unmap(vaddr); | |
1168 | } | |
bb6dc8d9 | 1169 | |
bb6dc8d9 CW |
1170 | return unwritten; |
1171 | } | |
1172 | ||
3de09aa3 EA |
1173 | /** |
1174 | * This is the fast pwrite path, where we copy the data directly from the | |
1175 | * user into the GTT, uncached. | |
fe115628 | 1176 | * @obj: i915 GEM object |
14bb2c11 | 1177 | * @args: pwrite arguments structure |
3de09aa3 | 1178 | */ |
673a394b | 1179 | static int |
fe115628 CW |
1180 | i915_gem_gtt_pwrite_fast(struct drm_i915_gem_object *obj, |
1181 | const struct drm_i915_gem_pwrite *args) | |
673a394b | 1182 | { |
fe115628 | 1183 | struct drm_i915_private *i915 = to_i915(obj->base.dev); |
4f1959ee AS |
1184 | struct i915_ggtt *ggtt = &i915->ggtt; |
1185 | struct drm_mm_node node; | |
fe115628 CW |
1186 | struct i915_vma *vma; |
1187 | u64 remain, offset; | |
1188 | void __user *user_data; | |
4f1959ee | 1189 | int ret; |
b50a5371 | 1190 | |
fe115628 CW |
1191 | ret = mutex_lock_interruptible(&i915->drm.struct_mutex); |
1192 | if (ret) | |
1193 | return ret; | |
935aaa69 | 1194 | |
9c870d03 | 1195 | intel_runtime_pm_get(i915); |
058d88c4 | 1196 | vma = i915_gem_object_ggtt_pin(obj, NULL, 0, 0, |
de895082 | 1197 | PIN_MAPPABLE | PIN_NONBLOCK); |
18034584 CW |
1198 | if (!IS_ERR(vma)) { |
1199 | node.start = i915_ggtt_offset(vma); | |
1200 | node.allocated = false; | |
49ef5294 | 1201 | ret = i915_vma_put_fence(vma); |
18034584 CW |
1202 | if (ret) { |
1203 | i915_vma_unpin(vma); | |
1204 | vma = ERR_PTR(ret); | |
1205 | } | |
1206 | } | |
058d88c4 | 1207 | if (IS_ERR(vma)) { |
bb6dc8d9 | 1208 | ret = insert_mappable_node(ggtt, &node, PAGE_SIZE); |
4f1959ee | 1209 | if (ret) |
fe115628 CW |
1210 | goto out_unlock; |
1211 | GEM_BUG_ON(!node.allocated); | |
4f1959ee | 1212 | } |
935aaa69 DV |
1213 | |
1214 | ret = i915_gem_object_set_to_gtt_domain(obj, true); | |
1215 | if (ret) | |
1216 | goto out_unpin; | |
1217 | ||
fe115628 CW |
1218 | mutex_unlock(&i915->drm.struct_mutex); |
1219 | ||
b19482d7 | 1220 | intel_fb_obj_invalidate(obj, ORIGIN_CPU); |
063e4e6b | 1221 | |
4f1959ee AS |
1222 | user_data = u64_to_user_ptr(args->data_ptr); |
1223 | offset = args->offset; | |
1224 | remain = args->size; | |
1225 | while (remain) { | |
673a394b EA |
1226 | /* Operation in this page |
1227 | * | |
0839ccb8 KP |
1228 | * page_base = page offset within aperture |
1229 | * page_offset = offset within page | |
1230 | * page_length = bytes to copy for this page | |
673a394b | 1231 | */ |
4f1959ee | 1232 | u32 page_base = node.start; |
bb6dc8d9 CW |
1233 | unsigned int page_offset = offset_in_page(offset); |
1234 | unsigned int page_length = PAGE_SIZE - page_offset; | |
4f1959ee AS |
1235 | page_length = remain < page_length ? remain : page_length; |
1236 | if (node.allocated) { | |
1237 | wmb(); /* flush the write before we modify the GGTT */ | |
1238 | ggtt->base.insert_page(&ggtt->base, | |
1239 | i915_gem_object_get_dma_address(obj, offset >> PAGE_SHIFT), | |
1240 | node.start, I915_CACHE_NONE, 0); | |
1241 | wmb(); /* flush modifications to the GGTT (insert_page) */ | |
1242 | } else { | |
1243 | page_base += offset & PAGE_MASK; | |
1244 | } | |
0839ccb8 | 1245 | /* If we get a fault while copying data, then (presumably) our |
3de09aa3 EA |
1246 | * source page isn't available. Return the error and we'll |
1247 | * retry in the slow path. | |
b50a5371 AS |
1248 | * If the object is non-shmem backed, we retry again with the |
1249 | * path that handles page fault. | |
0839ccb8 | 1250 | */ |
fe115628 CW |
1251 | if (ggtt_write(&ggtt->mappable, page_base, page_offset, |
1252 | user_data, page_length)) { | |
1253 | ret = -EFAULT; | |
1254 | break; | |
935aaa69 | 1255 | } |
673a394b | 1256 | |
0839ccb8 KP |
1257 | remain -= page_length; |
1258 | user_data += page_length; | |
1259 | offset += page_length; | |
673a394b | 1260 | } |
b19482d7 | 1261 | intel_fb_obj_flush(obj, false, ORIGIN_CPU); |
fe115628 CW |
1262 | |
1263 | mutex_lock(&i915->drm.struct_mutex); | |
935aaa69 | 1264 | out_unpin: |
4f1959ee AS |
1265 | if (node.allocated) { |
1266 | wmb(); | |
1267 | ggtt->base.clear_range(&ggtt->base, | |
4fb84d99 | 1268 | node.start, node.size); |
4f1959ee AS |
1269 | remove_mappable_node(&node); |
1270 | } else { | |
058d88c4 | 1271 | i915_vma_unpin(vma); |
4f1959ee | 1272 | } |
fe115628 | 1273 | out_unlock: |
9c870d03 | 1274 | intel_runtime_pm_put(i915); |
fe115628 | 1275 | mutex_unlock(&i915->drm.struct_mutex); |
3de09aa3 | 1276 | return ret; |
673a394b EA |
1277 | } |
1278 | ||
3043c60c | 1279 | static int |
fe115628 | 1280 | shmem_pwrite_slow(struct page *page, int offset, int length, |
d174bd64 DV |
1281 | char __user *user_data, |
1282 | bool page_do_bit17_swizzling, | |
1283 | bool needs_clflush_before, | |
1284 | bool needs_clflush_after) | |
673a394b | 1285 | { |
d174bd64 DV |
1286 | char *vaddr; |
1287 | int ret; | |
e5281ccd | 1288 | |
d174bd64 | 1289 | vaddr = kmap(page); |
e7e58eb5 | 1290 | if (unlikely(needs_clflush_before || page_do_bit17_swizzling)) |
fe115628 | 1291 | shmem_clflush_swizzled_range(vaddr + offset, length, |
23c18c71 | 1292 | page_do_bit17_swizzling); |
d174bd64 | 1293 | if (page_do_bit17_swizzling) |
fe115628 CW |
1294 | ret = __copy_from_user_swizzled(vaddr, offset, user_data, |
1295 | length); | |
d174bd64 | 1296 | else |
fe115628 | 1297 | ret = __copy_from_user(vaddr + offset, user_data, length); |
d174bd64 | 1298 | if (needs_clflush_after) |
fe115628 | 1299 | shmem_clflush_swizzled_range(vaddr + offset, length, |
23c18c71 | 1300 | page_do_bit17_swizzling); |
d174bd64 | 1301 | kunmap(page); |
40123c1f | 1302 | |
755d2218 | 1303 | return ret ? -EFAULT : 0; |
40123c1f EA |
1304 | } |
1305 | ||
fe115628 CW |
1306 | /* Per-page copy function for the shmem pwrite fastpath. |
1307 | * Flushes invalid cachelines before writing to the target if | |
1308 | * needs_clflush_before is set and flushes out any written cachelines after | |
1309 | * writing if needs_clflush is set. | |
1310 | */ | |
40123c1f | 1311 | static int |
fe115628 CW |
1312 | shmem_pwrite(struct page *page, int offset, int len, char __user *user_data, |
1313 | bool page_do_bit17_swizzling, | |
1314 | bool needs_clflush_before, | |
1315 | bool needs_clflush_after) | |
40123c1f | 1316 | { |
fe115628 CW |
1317 | int ret; |
1318 | ||
1319 | ret = -ENODEV; | |
1320 | if (!page_do_bit17_swizzling) { | |
1321 | char *vaddr = kmap_atomic(page); | |
1322 | ||
1323 | if (needs_clflush_before) | |
1324 | drm_clflush_virt_range(vaddr + offset, len); | |
1325 | ret = __copy_from_user_inatomic(vaddr + offset, user_data, len); | |
1326 | if (needs_clflush_after) | |
1327 | drm_clflush_virt_range(vaddr + offset, len); | |
1328 | ||
1329 | kunmap_atomic(vaddr); | |
1330 | } | |
1331 | if (ret == 0) | |
1332 | return ret; | |
1333 | ||
1334 | return shmem_pwrite_slow(page, offset, len, user_data, | |
1335 | page_do_bit17_swizzling, | |
1336 | needs_clflush_before, | |
1337 | needs_clflush_after); | |
1338 | } | |
1339 | ||
1340 | static int | |
1341 | i915_gem_shmem_pwrite(struct drm_i915_gem_object *obj, | |
1342 | const struct drm_i915_gem_pwrite *args) | |
1343 | { | |
1344 | struct drm_i915_private *i915 = to_i915(obj->base.dev); | |
1345 | void __user *user_data; | |
1346 | u64 remain; | |
1347 | unsigned int obj_do_bit17_swizzling; | |
1348 | unsigned int partial_cacheline_write; | |
43394c7d | 1349 | unsigned int needs_clflush; |
fe115628 CW |
1350 | unsigned int offset, idx; |
1351 | int ret; | |
40123c1f | 1352 | |
fe115628 | 1353 | ret = mutex_lock_interruptible(&i915->drm.struct_mutex); |
755d2218 CW |
1354 | if (ret) |
1355 | return ret; | |
1356 | ||
fe115628 CW |
1357 | ret = i915_gem_obj_prepare_shmem_write(obj, &needs_clflush); |
1358 | mutex_unlock(&i915->drm.struct_mutex); | |
1359 | if (ret) | |
1360 | return ret; | |
673a394b | 1361 | |
fe115628 CW |
1362 | obj_do_bit17_swizzling = 0; |
1363 | if (i915_gem_object_needs_bit17_swizzle(obj)) | |
1364 | obj_do_bit17_swizzling = BIT(17); | |
e5281ccd | 1365 | |
fe115628 CW |
1366 | /* If we don't overwrite a cacheline completely we need to be |
1367 | * careful to have up-to-date data by first clflushing. Don't | |
1368 | * overcomplicate things and flush the entire patch. | |
1369 | */ | |
1370 | partial_cacheline_write = 0; | |
1371 | if (needs_clflush & CLFLUSH_BEFORE) | |
1372 | partial_cacheline_write = boot_cpu_data.x86_clflush_size - 1; | |
9da3da66 | 1373 | |
fe115628 CW |
1374 | user_data = u64_to_user_ptr(args->data_ptr); |
1375 | remain = args->size; | |
1376 | offset = offset_in_page(args->offset); | |
1377 | for (idx = args->offset >> PAGE_SHIFT; remain; idx++) { | |
1378 | struct page *page = i915_gem_object_get_page(obj, idx); | |
1379 | int length; | |
40123c1f | 1380 | |
fe115628 CW |
1381 | length = remain; |
1382 | if (offset + length > PAGE_SIZE) | |
1383 | length = PAGE_SIZE - offset; | |
755d2218 | 1384 | |
fe115628 CW |
1385 | ret = shmem_pwrite(page, offset, length, user_data, |
1386 | page_to_phys(page) & obj_do_bit17_swizzling, | |
1387 | (offset | length) & partial_cacheline_write, | |
1388 | needs_clflush & CLFLUSH_AFTER); | |
755d2218 | 1389 | if (ret) |
fe115628 | 1390 | break; |
755d2218 | 1391 | |
fe115628 CW |
1392 | remain -= length; |
1393 | user_data += length; | |
1394 | offset = 0; | |
8c59967c | 1395 | } |
673a394b | 1396 | |
de152b62 | 1397 | intel_fb_obj_flush(obj, false, ORIGIN_CPU); |
fe115628 | 1398 | i915_gem_obj_finish_shmem_access(obj); |
40123c1f | 1399 | return ret; |
673a394b EA |
1400 | } |
1401 | ||
1402 | /** | |
1403 | * Writes data to the object referenced by handle. | |
14bb2c11 TU |
1404 | * @dev: drm device |
1405 | * @data: ioctl data blob | |
1406 | * @file: drm file | |
673a394b EA |
1407 | * |
1408 | * On error, the contents of the buffer that were to be modified are undefined. | |
1409 | */ | |
1410 | int | |
1411 | i915_gem_pwrite_ioctl(struct drm_device *dev, void *data, | |
fbd5a26d | 1412 | struct drm_file *file) |
673a394b EA |
1413 | { |
1414 | struct drm_i915_gem_pwrite *args = data; | |
05394f39 | 1415 | struct drm_i915_gem_object *obj; |
51311d0a CW |
1416 | int ret; |
1417 | ||
1418 | if (args->size == 0) | |
1419 | return 0; | |
1420 | ||
1421 | if (!access_ok(VERIFY_READ, | |
3ed605bc | 1422 | u64_to_user_ptr(args->data_ptr), |
51311d0a CW |
1423 | args->size)) |
1424 | return -EFAULT; | |
1425 | ||
03ac0642 | 1426 | obj = i915_gem_object_lookup(file, args->handle); |
258a5ede CW |
1427 | if (!obj) |
1428 | return -ENOENT; | |
673a394b | 1429 | |
7dcd2499 | 1430 | /* Bounds check destination. */ |
966d5bf5 | 1431 | if (range_overflows_t(u64, args->offset, args->size, obj->base.size)) { |
ce9d419d | 1432 | ret = -EINVAL; |
258a5ede | 1433 | goto err; |
ce9d419d CW |
1434 | } |
1435 | ||
db53a302 CW |
1436 | trace_i915_gem_object_pwrite(obj, args->offset, args->size); |
1437 | ||
e95433c7 CW |
1438 | ret = i915_gem_object_wait(obj, |
1439 | I915_WAIT_INTERRUPTIBLE | | |
1440 | I915_WAIT_ALL, | |
1441 | MAX_SCHEDULE_TIMEOUT, | |
1442 | to_rps_client(file)); | |
258a5ede CW |
1443 | if (ret) |
1444 | goto err; | |
1445 | ||
fe115628 | 1446 | ret = i915_gem_object_pin_pages(obj); |
258a5ede | 1447 | if (ret) |
fe115628 | 1448 | goto err; |
258a5ede | 1449 | |
935aaa69 | 1450 | ret = -EFAULT; |
673a394b EA |
1451 | /* We can only do the GTT pwrite on untiled buffers, as otherwise |
1452 | * it would end up going through the fenced access, and we'll get | |
1453 | * different detiling behavior between reading and writing. | |
1454 | * pread/pwrite currently are reading and writing from the CPU | |
1455 | * perspective, requiring manual detiling by the client. | |
1456 | */ | |
6eae0059 | 1457 | if (!i915_gem_object_has_struct_page(obj) || |
9c870d03 | 1458 | cpu_write_needs_clflush(obj)) |
935aaa69 DV |
1459 | /* Note that the gtt paths might fail with non-page-backed user |
1460 | * pointers (e.g. gtt mappings when moving data between | |
9c870d03 CW |
1461 | * textures). Fallback to the shmem path in that case. |
1462 | */ | |
fe115628 | 1463 | ret = i915_gem_gtt_pwrite_fast(obj, args); |
673a394b | 1464 | |
d1054ee4 | 1465 | if (ret == -EFAULT || ret == -ENOSPC) { |
6a2c4232 CW |
1466 | if (obj->phys_handle) |
1467 | ret = i915_gem_phys_pwrite(obj, args, file); | |
b50a5371 | 1468 | else |
fe115628 | 1469 | ret = i915_gem_shmem_pwrite(obj, args); |
6a2c4232 | 1470 | } |
5c0480f2 | 1471 | |
fe115628 | 1472 | i915_gem_object_unpin_pages(obj); |
258a5ede | 1473 | err: |
f0cd5182 | 1474 | i915_gem_object_put(obj); |
258a5ede | 1475 | return ret; |
673a394b EA |
1476 | } |
1477 | ||
d243ad82 | 1478 | static inline enum fb_op_origin |
aeecc969 CW |
1479 | write_origin(struct drm_i915_gem_object *obj, unsigned domain) |
1480 | { | |
50349247 CW |
1481 | return (domain == I915_GEM_DOMAIN_GTT ? |
1482 | obj->frontbuffer_ggtt_origin : ORIGIN_CPU); | |
aeecc969 CW |
1483 | } |
1484 | ||
40e62d5d CW |
1485 | static void i915_gem_object_bump_inactive_ggtt(struct drm_i915_gem_object *obj) |
1486 | { | |
1487 | struct drm_i915_private *i915; | |
1488 | struct list_head *list; | |
1489 | struct i915_vma *vma; | |
1490 | ||
1491 | list_for_each_entry(vma, &obj->vma_list, obj_link) { | |
1492 | if (!i915_vma_is_ggtt(vma)) | |
28f412e0 | 1493 | break; |
40e62d5d CW |
1494 | |
1495 | if (i915_vma_is_active(vma)) | |
1496 | continue; | |
1497 | ||
1498 | if (!drm_mm_node_allocated(&vma->node)) | |
1499 | continue; | |
1500 | ||
1501 | list_move_tail(&vma->vm_link, &vma->vm->inactive_list); | |
1502 | } | |
1503 | ||
1504 | i915 = to_i915(obj->base.dev); | |
1505 | list = obj->bind_count ? &i915->mm.bound_list : &i915->mm.unbound_list; | |
56cea323 | 1506 | list_move_tail(&obj->global_link, list); |
40e62d5d CW |
1507 | } |
1508 | ||
673a394b | 1509 | /** |
2ef7eeaa EA |
1510 | * Called when user space prepares to use an object with the CPU, either |
1511 | * through the mmap ioctl's mapping or a GTT mapping. | |
14bb2c11 TU |
1512 | * @dev: drm device |
1513 | * @data: ioctl data blob | |
1514 | * @file: drm file | |
673a394b EA |
1515 | */ |
1516 | int | |
1517 | i915_gem_set_domain_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 1518 | struct drm_file *file) |
673a394b EA |
1519 | { |
1520 | struct drm_i915_gem_set_domain *args = data; | |
05394f39 | 1521 | struct drm_i915_gem_object *obj; |
2ef7eeaa EA |
1522 | uint32_t read_domains = args->read_domains; |
1523 | uint32_t write_domain = args->write_domain; | |
40e62d5d | 1524 | int err; |
673a394b | 1525 | |
2ef7eeaa | 1526 | /* Only handle setting domains to types used by the CPU. */ |
b8f9096d | 1527 | if ((write_domain | read_domains) & I915_GEM_GPU_DOMAINS) |
2ef7eeaa EA |
1528 | return -EINVAL; |
1529 | ||
1530 | /* Having something in the write domain implies it's in the read | |
1531 | * domain, and only that read domain. Enforce that in the request. | |
1532 | */ | |
1533 | if (write_domain != 0 && read_domains != write_domain) | |
1534 | return -EINVAL; | |
1535 | ||
03ac0642 | 1536 | obj = i915_gem_object_lookup(file, args->handle); |
b8f9096d CW |
1537 | if (!obj) |
1538 | return -ENOENT; | |
673a394b | 1539 | |
3236f57a CW |
1540 | /* Try to flush the object off the GPU without holding the lock. |
1541 | * We will repeat the flush holding the lock in the normal manner | |
1542 | * to catch cases where we are gazumped. | |
1543 | */ | |
40e62d5d | 1544 | err = i915_gem_object_wait(obj, |
e95433c7 CW |
1545 | I915_WAIT_INTERRUPTIBLE | |
1546 | (write_domain ? I915_WAIT_ALL : 0), | |
1547 | MAX_SCHEDULE_TIMEOUT, | |
1548 | to_rps_client(file)); | |
40e62d5d | 1549 | if (err) |
f0cd5182 | 1550 | goto out; |
b8f9096d | 1551 | |
40e62d5d CW |
1552 | /* Flush and acquire obj->pages so that we are coherent through |
1553 | * direct access in memory with previous cached writes through | |
1554 | * shmemfs and that our cache domain tracking remains valid. | |
1555 | * For example, if the obj->filp was moved to swap without us | |
1556 | * being notified and releasing the pages, we would mistakenly | |
1557 | * continue to assume that the obj remained out of the CPU cached | |
1558 | * domain. | |
1559 | */ | |
1560 | err = i915_gem_object_pin_pages(obj); | |
1561 | if (err) | |
f0cd5182 | 1562 | goto out; |
40e62d5d CW |
1563 | |
1564 | err = i915_mutex_lock_interruptible(dev); | |
1565 | if (err) | |
f0cd5182 | 1566 | goto out_unpin; |
3236f57a | 1567 | |
43566ded | 1568 | if (read_domains & I915_GEM_DOMAIN_GTT) |
40e62d5d | 1569 | err = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0); |
43566ded | 1570 | else |
40e62d5d | 1571 | err = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0); |
2ef7eeaa | 1572 | |
40e62d5d CW |
1573 | /* And bump the LRU for this access */ |
1574 | i915_gem_object_bump_inactive_ggtt(obj); | |
031b698a | 1575 | |
673a394b | 1576 | mutex_unlock(&dev->struct_mutex); |
b8f9096d | 1577 | |
40e62d5d CW |
1578 | if (write_domain != 0) |
1579 | intel_fb_obj_invalidate(obj, write_origin(obj, write_domain)); | |
1580 | ||
f0cd5182 | 1581 | out_unpin: |
40e62d5d | 1582 | i915_gem_object_unpin_pages(obj); |
f0cd5182 CW |
1583 | out: |
1584 | i915_gem_object_put(obj); | |
40e62d5d | 1585 | return err; |
673a394b EA |
1586 | } |
1587 | ||
1588 | /** | |
1589 | * Called when user space has done writes to this buffer | |
14bb2c11 TU |
1590 | * @dev: drm device |
1591 | * @data: ioctl data blob | |
1592 | * @file: drm file | |
673a394b EA |
1593 | */ |
1594 | int | |
1595 | i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 1596 | struct drm_file *file) |
673a394b EA |
1597 | { |
1598 | struct drm_i915_gem_sw_finish *args = data; | |
05394f39 | 1599 | struct drm_i915_gem_object *obj; |
c21724cc | 1600 | int err = 0; |
1d7cfea1 | 1601 | |
03ac0642 | 1602 | obj = i915_gem_object_lookup(file, args->handle); |
c21724cc CW |
1603 | if (!obj) |
1604 | return -ENOENT; | |
673a394b | 1605 | |
673a394b | 1606 | /* Pinned buffers may be scanout, so flush the cache */ |
c21724cc CW |
1607 | if (READ_ONCE(obj->pin_display)) { |
1608 | err = i915_mutex_lock_interruptible(dev); | |
1609 | if (!err) { | |
1610 | i915_gem_object_flush_cpu_write_domain(obj); | |
1611 | mutex_unlock(&dev->struct_mutex); | |
1612 | } | |
1613 | } | |
e47c68e9 | 1614 | |
f0cd5182 | 1615 | i915_gem_object_put(obj); |
c21724cc | 1616 | return err; |
673a394b EA |
1617 | } |
1618 | ||
1619 | /** | |
14bb2c11 TU |
1620 | * i915_gem_mmap_ioctl - Maps the contents of an object, returning the address |
1621 | * it is mapped to. | |
1622 | * @dev: drm device | |
1623 | * @data: ioctl data blob | |
1624 | * @file: drm file | |
673a394b EA |
1625 | * |
1626 | * While the mapping holds a reference on the contents of the object, it doesn't | |
1627 | * imply a ref on the object itself. | |
34367381 DV |
1628 | * |
1629 | * IMPORTANT: | |
1630 | * | |
1631 | * DRM driver writers who look a this function as an example for how to do GEM | |
1632 | * mmap support, please don't implement mmap support like here. The modern way | |
1633 | * to implement DRM mmap support is with an mmap offset ioctl (like | |
1634 | * i915_gem_mmap_gtt) and then using the mmap syscall on the DRM fd directly. | |
1635 | * That way debug tooling like valgrind will understand what's going on, hiding | |
1636 | * the mmap call in a driver private ioctl will break that. The i915 driver only | |
1637 | * does cpu mmaps this way because we didn't know better. | |
673a394b EA |
1638 | */ |
1639 | int | |
1640 | i915_gem_mmap_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 1641 | struct drm_file *file) |
673a394b EA |
1642 | { |
1643 | struct drm_i915_gem_mmap *args = data; | |
03ac0642 | 1644 | struct drm_i915_gem_object *obj; |
673a394b EA |
1645 | unsigned long addr; |
1646 | ||
1816f923 AG |
1647 | if (args->flags & ~(I915_MMAP_WC)) |
1648 | return -EINVAL; | |
1649 | ||
568a58e5 | 1650 | if (args->flags & I915_MMAP_WC && !boot_cpu_has(X86_FEATURE_PAT)) |
1816f923 AG |
1651 | return -ENODEV; |
1652 | ||
03ac0642 CW |
1653 | obj = i915_gem_object_lookup(file, args->handle); |
1654 | if (!obj) | |
bf79cb91 | 1655 | return -ENOENT; |
673a394b | 1656 | |
1286ff73 DV |
1657 | /* prime objects have no backing filp to GEM mmap |
1658 | * pages from. | |
1659 | */ | |
03ac0642 | 1660 | if (!obj->base.filp) { |
f0cd5182 | 1661 | i915_gem_object_put(obj); |
1286ff73 DV |
1662 | return -EINVAL; |
1663 | } | |
1664 | ||
03ac0642 | 1665 | addr = vm_mmap(obj->base.filp, 0, args->size, |
673a394b EA |
1666 | PROT_READ | PROT_WRITE, MAP_SHARED, |
1667 | args->offset); | |
1816f923 AG |
1668 | if (args->flags & I915_MMAP_WC) { |
1669 | struct mm_struct *mm = current->mm; | |
1670 | struct vm_area_struct *vma; | |
1671 | ||
80a89a5e | 1672 | if (down_write_killable(&mm->mmap_sem)) { |
f0cd5182 | 1673 | i915_gem_object_put(obj); |
80a89a5e MH |
1674 | return -EINTR; |
1675 | } | |
1816f923 AG |
1676 | vma = find_vma(mm, addr); |
1677 | if (vma) | |
1678 | vma->vm_page_prot = | |
1679 | pgprot_writecombine(vm_get_page_prot(vma->vm_flags)); | |
1680 | else | |
1681 | addr = -ENOMEM; | |
1682 | up_write(&mm->mmap_sem); | |
aeecc969 CW |
1683 | |
1684 | /* This may race, but that's ok, it only gets set */ | |
50349247 | 1685 | WRITE_ONCE(obj->frontbuffer_ggtt_origin, ORIGIN_CPU); |
1816f923 | 1686 | } |
f0cd5182 | 1687 | i915_gem_object_put(obj); |
673a394b EA |
1688 | if (IS_ERR((void *)addr)) |
1689 | return addr; | |
1690 | ||
1691 | args->addr_ptr = (uint64_t) addr; | |
1692 | ||
1693 | return 0; | |
1694 | } | |
1695 | ||
03af84fe CW |
1696 | static unsigned int tile_row_pages(struct drm_i915_gem_object *obj) |
1697 | { | |
6649a0b6 | 1698 | return i915_gem_object_get_tile_row_size(obj) >> PAGE_SHIFT; |
03af84fe CW |
1699 | } |
1700 | ||
4cc69075 CW |
1701 | /** |
1702 | * i915_gem_mmap_gtt_version - report the current feature set for GTT mmaps | |
1703 | * | |
1704 | * A history of the GTT mmap interface: | |
1705 | * | |
1706 | * 0 - Everything had to fit into the GTT. Both parties of a memcpy had to | |
1707 | * aligned and suitable for fencing, and still fit into the available | |
1708 | * mappable space left by the pinned display objects. A classic problem | |
1709 | * we called the page-fault-of-doom where we would ping-pong between | |
1710 | * two objects that could not fit inside the GTT and so the memcpy | |
1711 | * would page one object in at the expense of the other between every | |
1712 | * single byte. | |
1713 | * | |
1714 | * 1 - Objects can be any size, and have any compatible fencing (X Y, or none | |
1715 | * as set via i915_gem_set_tiling() [DRM_I915_GEM_SET_TILING]). If the | |
1716 | * object is too large for the available space (or simply too large | |
1717 | * for the mappable aperture!), a view is created instead and faulted | |
1718 | * into userspace. (This view is aligned and sized appropriately for | |
1719 | * fenced access.) | |
1720 | * | |
1721 | * Restrictions: | |
1722 | * | |
1723 | * * snoopable objects cannot be accessed via the GTT. It can cause machine | |
1724 | * hangs on some architectures, corruption on others. An attempt to service | |
1725 | * a GTT page fault from a snoopable object will generate a SIGBUS. | |
1726 | * | |
1727 | * * the object must be able to fit into RAM (physical memory, though no | |
1728 | * limited to the mappable aperture). | |
1729 | * | |
1730 | * | |
1731 | * Caveats: | |
1732 | * | |
1733 | * * a new GTT page fault will synchronize rendering from the GPU and flush | |
1734 | * all data to system memory. Subsequent access will not be synchronized. | |
1735 | * | |
1736 | * * all mappings are revoked on runtime device suspend. | |
1737 | * | |
1738 | * * there are only 8, 16 or 32 fence registers to share between all users | |
1739 | * (older machines require fence register for display and blitter access | |
1740 | * as well). Contention of the fence registers will cause the previous users | |
1741 | * to be unmapped and any new access will generate new page faults. | |
1742 | * | |
1743 | * * running out of memory while servicing a fault may generate a SIGBUS, | |
1744 | * rather than the expected SIGSEGV. | |
1745 | */ | |
1746 | int i915_gem_mmap_gtt_version(void) | |
1747 | { | |
1748 | return 1; | |
1749 | } | |
1750 | ||
2d4281bb CW |
1751 | static inline struct i915_ggtt_view |
1752 | compute_partial_view(struct drm_i915_gem_object *obj, | |
2d4281bb CW |
1753 | pgoff_t page_offset, |
1754 | unsigned int chunk) | |
1755 | { | |
1756 | struct i915_ggtt_view view; | |
1757 | ||
1758 | if (i915_gem_object_is_tiled(obj)) | |
1759 | chunk = roundup(chunk, tile_row_pages(obj)); | |
1760 | ||
2d4281bb | 1761 | view.type = I915_GGTT_VIEW_PARTIAL; |
8bab1193 CW |
1762 | view.partial.offset = rounddown(page_offset, chunk); |
1763 | view.partial.size = | |
2d4281bb | 1764 | min_t(unsigned int, chunk, |
8bab1193 | 1765 | (obj->base.size >> PAGE_SHIFT) - view.partial.offset); |
2d4281bb CW |
1766 | |
1767 | /* If the partial covers the entire object, just create a normal VMA. */ | |
1768 | if (chunk >= obj->base.size >> PAGE_SHIFT) | |
1769 | view.type = I915_GGTT_VIEW_NORMAL; | |
1770 | ||
1771 | return view; | |
1772 | } | |
1773 | ||
de151cf6 JB |
1774 | /** |
1775 | * i915_gem_fault - fault a page into the GTT | |
058d88c4 | 1776 | * @area: CPU VMA in question |
d9072a3e | 1777 | * @vmf: fault info |
de151cf6 JB |
1778 | * |
1779 | * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped | |
1780 | * from userspace. The fault handler takes care of binding the object to | |
1781 | * the GTT (if needed), allocating and programming a fence register (again, | |
1782 | * only if needed based on whether the old reg is still valid or the object | |
1783 | * is tiled) and inserting a new PTE into the faulting process. | |
1784 | * | |
1785 | * Note that the faulting process may involve evicting existing objects | |
1786 | * from the GTT and/or fence registers to make room. So performance may | |
1787 | * suffer if the GTT working set is large or there are few fence registers | |
1788 | * left. | |
4cc69075 CW |
1789 | * |
1790 | * The current feature set supported by i915_gem_fault() and thus GTT mmaps | |
1791 | * is exposed via I915_PARAM_MMAP_GTT_VERSION (see i915_gem_mmap_gtt_version). | |
de151cf6 | 1792 | */ |
058d88c4 | 1793 | int i915_gem_fault(struct vm_area_struct *area, struct vm_fault *vmf) |
de151cf6 | 1794 | { |
03af84fe | 1795 | #define MIN_CHUNK_PAGES ((1 << 20) >> PAGE_SHIFT) /* 1 MiB */ |
058d88c4 | 1796 | struct drm_i915_gem_object *obj = to_intel_bo(area->vm_private_data); |
05394f39 | 1797 | struct drm_device *dev = obj->base.dev; |
72e96d64 JL |
1798 | struct drm_i915_private *dev_priv = to_i915(dev); |
1799 | struct i915_ggtt *ggtt = &dev_priv->ggtt; | |
b8f9096d | 1800 | bool write = !!(vmf->flags & FAULT_FLAG_WRITE); |
058d88c4 | 1801 | struct i915_vma *vma; |
de151cf6 | 1802 | pgoff_t page_offset; |
82118877 | 1803 | unsigned int flags; |
b8f9096d | 1804 | int ret; |
f65c9168 | 1805 | |
de151cf6 | 1806 | /* We don't use vmf->pgoff since that has the fake offset */ |
1a29d85e | 1807 | page_offset = (vmf->address - area->vm_start) >> PAGE_SHIFT; |
de151cf6 | 1808 | |
db53a302 CW |
1809 | trace_i915_gem_object_fault(obj, page_offset, true, write); |
1810 | ||
6e4930f6 | 1811 | /* Try to flush the object off the GPU first without holding the lock. |
b8f9096d | 1812 | * Upon acquiring the lock, we will perform our sanity checks and then |
6e4930f6 CW |
1813 | * repeat the flush holding the lock in the normal manner to catch cases |
1814 | * where we are gazumped. | |
1815 | */ | |
e95433c7 CW |
1816 | ret = i915_gem_object_wait(obj, |
1817 | I915_WAIT_INTERRUPTIBLE, | |
1818 | MAX_SCHEDULE_TIMEOUT, | |
1819 | NULL); | |
6e4930f6 | 1820 | if (ret) |
b8f9096d CW |
1821 | goto err; |
1822 | ||
40e62d5d CW |
1823 | ret = i915_gem_object_pin_pages(obj); |
1824 | if (ret) | |
1825 | goto err; | |
1826 | ||
b8f9096d CW |
1827 | intel_runtime_pm_get(dev_priv); |
1828 | ||
1829 | ret = i915_mutex_lock_interruptible(dev); | |
1830 | if (ret) | |
1831 | goto err_rpm; | |
6e4930f6 | 1832 | |
eb119bd6 | 1833 | /* Access to snoopable pages through the GTT is incoherent. */ |
0031fb96 | 1834 | if (obj->cache_level != I915_CACHE_NONE && !HAS_LLC(dev_priv)) { |
ddeff6ee | 1835 | ret = -EFAULT; |
b8f9096d | 1836 | goto err_unlock; |
eb119bd6 CW |
1837 | } |
1838 | ||
82118877 CW |
1839 | /* If the object is smaller than a couple of partial vma, it is |
1840 | * not worth only creating a single partial vma - we may as well | |
1841 | * clear enough space for the full object. | |
1842 | */ | |
1843 | flags = PIN_MAPPABLE; | |
1844 | if (obj->base.size > 2 * MIN_CHUNK_PAGES << PAGE_SHIFT) | |
1845 | flags |= PIN_NONBLOCK | PIN_NONFAULT; | |
1846 | ||
a61007a8 | 1847 | /* Now pin it into the GTT as needed */ |
82118877 | 1848 | vma = i915_gem_object_ggtt_pin(obj, NULL, 0, 0, flags); |
a61007a8 | 1849 | if (IS_ERR(vma)) { |
a61007a8 | 1850 | /* Use a partial view if it is bigger than available space */ |
2d4281bb | 1851 | struct i915_ggtt_view view = |
8201c1fa | 1852 | compute_partial_view(obj, page_offset, MIN_CHUNK_PAGES); |
aa136d9d | 1853 | |
50349247 CW |
1854 | /* Userspace is now writing through an untracked VMA, abandon |
1855 | * all hope that the hardware is able to track future writes. | |
1856 | */ | |
1857 | obj->frontbuffer_ggtt_origin = ORIGIN_CPU; | |
1858 | ||
a61007a8 CW |
1859 | vma = i915_gem_object_ggtt_pin(obj, &view, 0, 0, PIN_MAPPABLE); |
1860 | } | |
058d88c4 CW |
1861 | if (IS_ERR(vma)) { |
1862 | ret = PTR_ERR(vma); | |
b8f9096d | 1863 | goto err_unlock; |
058d88c4 | 1864 | } |
4a684a41 | 1865 | |
c9839303 CW |
1866 | ret = i915_gem_object_set_to_gtt_domain(obj, write); |
1867 | if (ret) | |
b8f9096d | 1868 | goto err_unpin; |
74898d7e | 1869 | |
49ef5294 | 1870 | ret = i915_vma_get_fence(vma); |
d9e86c0e | 1871 | if (ret) |
b8f9096d | 1872 | goto err_unpin; |
7d1c4804 | 1873 | |
275f039d | 1874 | /* Mark as being mmapped into userspace for later revocation */ |
9c870d03 | 1875 | assert_rpm_wakelock_held(dev_priv); |
275f039d CW |
1876 | if (list_empty(&obj->userfault_link)) |
1877 | list_add(&obj->userfault_link, &dev_priv->mm.userfault_list); | |
275f039d | 1878 | |
b90b91d8 | 1879 | /* Finally, remap it using the new GTT offset */ |
c58305af | 1880 | ret = remap_io_mapping(area, |
8bab1193 | 1881 | area->vm_start + (vma->ggtt_view.partial.offset << PAGE_SHIFT), |
c58305af CW |
1882 | (ggtt->mappable_base + vma->node.start) >> PAGE_SHIFT, |
1883 | min_t(u64, vma->size, area->vm_end - area->vm_start), | |
1884 | &ggtt->mappable); | |
a61007a8 | 1885 | |
b8f9096d | 1886 | err_unpin: |
058d88c4 | 1887 | __i915_vma_unpin(vma); |
b8f9096d | 1888 | err_unlock: |
de151cf6 | 1889 | mutex_unlock(&dev->struct_mutex); |
b8f9096d CW |
1890 | err_rpm: |
1891 | intel_runtime_pm_put(dev_priv); | |
40e62d5d | 1892 | i915_gem_object_unpin_pages(obj); |
b8f9096d | 1893 | err: |
de151cf6 | 1894 | switch (ret) { |
d9bc7e9f | 1895 | case -EIO: |
2232f031 DV |
1896 | /* |
1897 | * We eat errors when the gpu is terminally wedged to avoid | |
1898 | * userspace unduly crashing (gl has no provisions for mmaps to | |
1899 | * fail). But any other -EIO isn't ours (e.g. swap in failure) | |
1900 | * and so needs to be reported. | |
1901 | */ | |
1902 | if (!i915_terminally_wedged(&dev_priv->gpu_error)) { | |
f65c9168 PZ |
1903 | ret = VM_FAULT_SIGBUS; |
1904 | break; | |
1905 | } | |
045e769a | 1906 | case -EAGAIN: |
571c608d DV |
1907 | /* |
1908 | * EAGAIN means the gpu is hung and we'll wait for the error | |
1909 | * handler to reset everything when re-faulting in | |
1910 | * i915_mutex_lock_interruptible. | |
d9bc7e9f | 1911 | */ |
c715089f CW |
1912 | case 0: |
1913 | case -ERESTARTSYS: | |
bed636ab | 1914 | case -EINTR: |
e79e0fe3 DR |
1915 | case -EBUSY: |
1916 | /* | |
1917 | * EBUSY is ok: this just means that another thread | |
1918 | * already did the job. | |
1919 | */ | |
f65c9168 PZ |
1920 | ret = VM_FAULT_NOPAGE; |
1921 | break; | |
de151cf6 | 1922 | case -ENOMEM: |
f65c9168 PZ |
1923 | ret = VM_FAULT_OOM; |
1924 | break; | |
a7c2e1aa | 1925 | case -ENOSPC: |
45d67817 | 1926 | case -EFAULT: |
f65c9168 PZ |
1927 | ret = VM_FAULT_SIGBUS; |
1928 | break; | |
de151cf6 | 1929 | default: |
a7c2e1aa | 1930 | WARN_ONCE(ret, "unhandled error in i915_gem_fault: %i\n", ret); |
f65c9168 PZ |
1931 | ret = VM_FAULT_SIGBUS; |
1932 | break; | |
de151cf6 | 1933 | } |
f65c9168 | 1934 | return ret; |
de151cf6 JB |
1935 | } |
1936 | ||
901782b2 CW |
1937 | /** |
1938 | * i915_gem_release_mmap - remove physical page mappings | |
1939 | * @obj: obj in question | |
1940 | * | |
af901ca1 | 1941 | * Preserve the reservation of the mmapping with the DRM core code, but |
901782b2 CW |
1942 | * relinquish ownership of the pages back to the system. |
1943 | * | |
1944 | * It is vital that we remove the page mapping if we have mapped a tiled | |
1945 | * object through the GTT and then lose the fence register due to | |
1946 | * resource pressure. Similarly if the object has been moved out of the | |
1947 | * aperture, than pages mapped into userspace must be revoked. Removing the | |
1948 | * mapping will then trigger a page fault on the next user access, allowing | |
1949 | * fixup by i915_gem_fault(). | |
1950 | */ | |
d05ca301 | 1951 | void |
05394f39 | 1952 | i915_gem_release_mmap(struct drm_i915_gem_object *obj) |
901782b2 | 1953 | { |
275f039d | 1954 | struct drm_i915_private *i915 = to_i915(obj->base.dev); |
275f039d | 1955 | |
349f2ccf CW |
1956 | /* Serialisation between user GTT access and our code depends upon |
1957 | * revoking the CPU's PTE whilst the mutex is held. The next user | |
1958 | * pagefault then has to wait until we release the mutex. | |
9c870d03 CW |
1959 | * |
1960 | * Note that RPM complicates somewhat by adding an additional | |
1961 | * requirement that operations to the GGTT be made holding the RPM | |
1962 | * wakeref. | |
349f2ccf | 1963 | */ |
275f039d | 1964 | lockdep_assert_held(&i915->drm.struct_mutex); |
9c870d03 | 1965 | intel_runtime_pm_get(i915); |
349f2ccf | 1966 | |
3594a3e2 | 1967 | if (list_empty(&obj->userfault_link)) |
9c870d03 | 1968 | goto out; |
901782b2 | 1969 | |
3594a3e2 | 1970 | list_del_init(&obj->userfault_link); |
6796cb16 DH |
1971 | drm_vma_node_unmap(&obj->base.vma_node, |
1972 | obj->base.dev->anon_inode->i_mapping); | |
349f2ccf CW |
1973 | |
1974 | /* Ensure that the CPU's PTE are revoked and there are not outstanding | |
1975 | * memory transactions from userspace before we return. The TLB | |
1976 | * flushing implied above by changing the PTE above *should* be | |
1977 | * sufficient, an extra barrier here just provides us with a bit | |
1978 | * of paranoid documentation about our requirement to serialise | |
1979 | * memory writes before touching registers / GSM. | |
1980 | */ | |
1981 | wmb(); | |
9c870d03 CW |
1982 | |
1983 | out: | |
1984 | intel_runtime_pm_put(i915); | |
901782b2 CW |
1985 | } |
1986 | ||
7c108fd8 | 1987 | void i915_gem_runtime_suspend(struct drm_i915_private *dev_priv) |
eedd10f4 | 1988 | { |
3594a3e2 | 1989 | struct drm_i915_gem_object *obj, *on; |
7c108fd8 | 1990 | int i; |
eedd10f4 | 1991 | |
3594a3e2 CW |
1992 | /* |
1993 | * Only called during RPM suspend. All users of the userfault_list | |
1994 | * must be holding an RPM wakeref to ensure that this can not | |
1995 | * run concurrently with themselves (and use the struct_mutex for | |
1996 | * protection between themselves). | |
1997 | */ | |
275f039d | 1998 | |
3594a3e2 CW |
1999 | list_for_each_entry_safe(obj, on, |
2000 | &dev_priv->mm.userfault_list, userfault_link) { | |
2001 | list_del_init(&obj->userfault_link); | |
275f039d CW |
2002 | drm_vma_node_unmap(&obj->base.vma_node, |
2003 | obj->base.dev->anon_inode->i_mapping); | |
275f039d | 2004 | } |
7c108fd8 CW |
2005 | |
2006 | /* The fence will be lost when the device powers down. If any were | |
2007 | * in use by hardware (i.e. they are pinned), we should not be powering | |
2008 | * down! All other fences will be reacquired by the user upon waking. | |
2009 | */ | |
2010 | for (i = 0; i < dev_priv->num_fence_regs; i++) { | |
2011 | struct drm_i915_fence_reg *reg = &dev_priv->fence_regs[i]; | |
2012 | ||
e0ec3ec6 CW |
2013 | /* Ideally we want to assert that the fence register is not |
2014 | * live at this point (i.e. that no piece of code will be | |
2015 | * trying to write through fence + GTT, as that both violates | |
2016 | * our tracking of activity and associated locking/barriers, | |
2017 | * but also is illegal given that the hw is powered down). | |
2018 | * | |
2019 | * Previously we used reg->pin_count as a "liveness" indicator. | |
2020 | * That is not sufficient, and we need a more fine-grained | |
2021 | * tool if we want to have a sanity check here. | |
2022 | */ | |
7c108fd8 CW |
2023 | |
2024 | if (!reg->vma) | |
2025 | continue; | |
2026 | ||
2027 | GEM_BUG_ON(!list_empty(®->vma->obj->userfault_link)); | |
2028 | reg->dirty = true; | |
2029 | } | |
eedd10f4 CW |
2030 | } |
2031 | ||
d8cb5086 CW |
2032 | static int i915_gem_object_create_mmap_offset(struct drm_i915_gem_object *obj) |
2033 | { | |
fac5e23e | 2034 | struct drm_i915_private *dev_priv = to_i915(obj->base.dev); |
f3f6184c | 2035 | int err; |
da494d7c | 2036 | |
f3f6184c | 2037 | err = drm_gem_create_mmap_offset(&obj->base); |
b42a13d9 | 2038 | if (likely(!err)) |
f3f6184c | 2039 | return 0; |
d8cb5086 | 2040 | |
b42a13d9 CW |
2041 | /* Attempt to reap some mmap space from dead objects */ |
2042 | do { | |
2043 | err = i915_gem_wait_for_idle(dev_priv, I915_WAIT_INTERRUPTIBLE); | |
2044 | if (err) | |
2045 | break; | |
f3f6184c | 2046 | |
b42a13d9 | 2047 | i915_gem_drain_freed_objects(dev_priv); |
f3f6184c | 2048 | err = drm_gem_create_mmap_offset(&obj->base); |
b42a13d9 CW |
2049 | if (!err) |
2050 | break; | |
2051 | ||
2052 | } while (flush_delayed_work(&dev_priv->gt.retire_work)); | |
da494d7c | 2053 | |
f3f6184c | 2054 | return err; |
d8cb5086 CW |
2055 | } |
2056 | ||
2057 | static void i915_gem_object_free_mmap_offset(struct drm_i915_gem_object *obj) | |
2058 | { | |
d8cb5086 CW |
2059 | drm_gem_free_mmap_offset(&obj->base); |
2060 | } | |
2061 | ||
da6b51d0 | 2062 | int |
ff72145b DA |
2063 | i915_gem_mmap_gtt(struct drm_file *file, |
2064 | struct drm_device *dev, | |
da6b51d0 | 2065 | uint32_t handle, |
ff72145b | 2066 | uint64_t *offset) |
de151cf6 | 2067 | { |
05394f39 | 2068 | struct drm_i915_gem_object *obj; |
de151cf6 JB |
2069 | int ret; |
2070 | ||
03ac0642 | 2071 | obj = i915_gem_object_lookup(file, handle); |
f3f6184c CW |
2072 | if (!obj) |
2073 | return -ENOENT; | |
ab18282d | 2074 | |
d8cb5086 | 2075 | ret = i915_gem_object_create_mmap_offset(obj); |
f3f6184c CW |
2076 | if (ret == 0) |
2077 | *offset = drm_vma_node_offset_addr(&obj->base.vma_node); | |
de151cf6 | 2078 | |
f0cd5182 | 2079 | i915_gem_object_put(obj); |
1d7cfea1 | 2080 | return ret; |
de151cf6 JB |
2081 | } |
2082 | ||
ff72145b DA |
2083 | /** |
2084 | * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing | |
2085 | * @dev: DRM device | |
2086 | * @data: GTT mapping ioctl data | |
2087 | * @file: GEM object info | |
2088 | * | |
2089 | * Simply returns the fake offset to userspace so it can mmap it. | |
2090 | * The mmap call will end up in drm_gem_mmap(), which will set things | |
2091 | * up so we can get faults in the handler above. | |
2092 | * | |
2093 | * The fault handler will take care of binding the object into the GTT | |
2094 | * (since it may have been evicted to make room for something), allocating | |
2095 | * a fence register, and mapping the appropriate aperture address into | |
2096 | * userspace. | |
2097 | */ | |
2098 | int | |
2099 | i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data, | |
2100 | struct drm_file *file) | |
2101 | { | |
2102 | struct drm_i915_gem_mmap_gtt *args = data; | |
2103 | ||
da6b51d0 | 2104 | return i915_gem_mmap_gtt(file, dev, args->handle, &args->offset); |
ff72145b DA |
2105 | } |
2106 | ||
225067ee DV |
2107 | /* Immediately discard the backing storage */ |
2108 | static void | |
2109 | i915_gem_object_truncate(struct drm_i915_gem_object *obj) | |
e5281ccd | 2110 | { |
4d6294bf | 2111 | i915_gem_object_free_mmap_offset(obj); |
1286ff73 | 2112 | |
4d6294bf CW |
2113 | if (obj->base.filp == NULL) |
2114 | return; | |
e5281ccd | 2115 | |
225067ee DV |
2116 | /* Our goal here is to return as much of the memory as |
2117 | * is possible back to the system as we are called from OOM. | |
2118 | * To do this we must instruct the shmfs to drop all of its | |
2119 | * backing pages, *now*. | |
2120 | */ | |
5537252b | 2121 | shmem_truncate_range(file_inode(obj->base.filp), 0, (loff_t)-1); |
a4f5ea64 | 2122 | obj->mm.madv = __I915_MADV_PURGED; |
225067ee | 2123 | } |
e5281ccd | 2124 | |
5537252b | 2125 | /* Try to discard unwanted pages */ |
03ac84f1 | 2126 | void __i915_gem_object_invalidate(struct drm_i915_gem_object *obj) |
225067ee | 2127 | { |
5537252b CW |
2128 | struct address_space *mapping; |
2129 | ||
1233e2db CW |
2130 | lockdep_assert_held(&obj->mm.lock); |
2131 | GEM_BUG_ON(obj->mm.pages); | |
2132 | ||
a4f5ea64 | 2133 | switch (obj->mm.madv) { |
5537252b CW |
2134 | case I915_MADV_DONTNEED: |
2135 | i915_gem_object_truncate(obj); | |
2136 | case __I915_MADV_PURGED: | |
2137 | return; | |
2138 | } | |
2139 | ||
2140 | if (obj->base.filp == NULL) | |
2141 | return; | |
2142 | ||
93c76a3d | 2143 | mapping = obj->base.filp->f_mapping, |
5537252b | 2144 | invalidate_mapping_pages(mapping, 0, (loff_t)-1); |
e5281ccd CW |
2145 | } |
2146 | ||
5cdf5881 | 2147 | static void |
03ac84f1 CW |
2148 | i915_gem_object_put_pages_gtt(struct drm_i915_gem_object *obj, |
2149 | struct sg_table *pages) | |
673a394b | 2150 | { |
85d1225e DG |
2151 | struct sgt_iter sgt_iter; |
2152 | struct page *page; | |
1286ff73 | 2153 | |
e5facdf9 | 2154 | __i915_gem_object_release_shmem(obj, pages, true); |
673a394b | 2155 | |
03ac84f1 | 2156 | i915_gem_gtt_finish_pages(obj, pages); |
e2273302 | 2157 | |
6dacfd2f | 2158 | if (i915_gem_object_needs_bit17_swizzle(obj)) |
03ac84f1 | 2159 | i915_gem_object_save_bit_17_swizzle(obj, pages); |
280b713b | 2160 | |
03ac84f1 | 2161 | for_each_sgt_page(page, sgt_iter, pages) { |
a4f5ea64 | 2162 | if (obj->mm.dirty) |
9da3da66 | 2163 | set_page_dirty(page); |
3ef94daa | 2164 | |
a4f5ea64 | 2165 | if (obj->mm.madv == I915_MADV_WILLNEED) |
9da3da66 | 2166 | mark_page_accessed(page); |
3ef94daa | 2167 | |
09cbfeaf | 2168 | put_page(page); |
3ef94daa | 2169 | } |
a4f5ea64 | 2170 | obj->mm.dirty = false; |
673a394b | 2171 | |
03ac84f1 CW |
2172 | sg_free_table(pages); |
2173 | kfree(pages); | |
37e680a1 | 2174 | } |
6c085a72 | 2175 | |
96d77634 CW |
2176 | static void __i915_gem_object_reset_page_iter(struct drm_i915_gem_object *obj) |
2177 | { | |
2178 | struct radix_tree_iter iter; | |
2179 | void **slot; | |
2180 | ||
a4f5ea64 CW |
2181 | radix_tree_for_each_slot(slot, &obj->mm.get_page.radix, &iter, 0) |
2182 | radix_tree_delete(&obj->mm.get_page.radix, iter.index); | |
96d77634 CW |
2183 | } |
2184 | ||
548625ee CW |
2185 | void __i915_gem_object_put_pages(struct drm_i915_gem_object *obj, |
2186 | enum i915_mm_subclass subclass) | |
37e680a1 | 2187 | { |
03ac84f1 | 2188 | struct sg_table *pages; |
37e680a1 | 2189 | |
a4f5ea64 | 2190 | if (i915_gem_object_has_pinned_pages(obj)) |
03ac84f1 | 2191 | return; |
a5570178 | 2192 | |
15717de2 | 2193 | GEM_BUG_ON(obj->bind_count); |
1233e2db CW |
2194 | if (!READ_ONCE(obj->mm.pages)) |
2195 | return; | |
2196 | ||
2197 | /* May be called by shrinker from within get_pages() (on another bo) */ | |
548625ee | 2198 | mutex_lock_nested(&obj->mm.lock, subclass); |
1233e2db CW |
2199 | if (unlikely(atomic_read(&obj->mm.pages_pin_count))) |
2200 | goto unlock; | |
3e123027 | 2201 | |
a2165e31 CW |
2202 | /* ->put_pages might need to allocate memory for the bit17 swizzle |
2203 | * array, hence protect them from being reaped by removing them from gtt | |
2204 | * lists early. */ | |
03ac84f1 CW |
2205 | pages = fetch_and_zero(&obj->mm.pages); |
2206 | GEM_BUG_ON(!pages); | |
a2165e31 | 2207 | |
a4f5ea64 | 2208 | if (obj->mm.mapping) { |
4b30cb23 CW |
2209 | void *ptr; |
2210 | ||
a4f5ea64 | 2211 | ptr = ptr_mask_bits(obj->mm.mapping); |
4b30cb23 CW |
2212 | if (is_vmalloc_addr(ptr)) |
2213 | vunmap(ptr); | |
fb8621d3 | 2214 | else |
4b30cb23 CW |
2215 | kunmap(kmap_to_page(ptr)); |
2216 | ||
a4f5ea64 | 2217 | obj->mm.mapping = NULL; |
0a798eb9 CW |
2218 | } |
2219 | ||
96d77634 CW |
2220 | __i915_gem_object_reset_page_iter(obj); |
2221 | ||
03ac84f1 | 2222 | obj->ops->put_pages(obj, pages); |
1233e2db CW |
2223 | unlock: |
2224 | mutex_unlock(&obj->mm.lock); | |
6c085a72 CW |
2225 | } |
2226 | ||
935a2f77 | 2227 | static bool i915_sg_trim(struct sg_table *orig_st) |
0c40ce13 TU |
2228 | { |
2229 | struct sg_table new_st; | |
2230 | struct scatterlist *sg, *new_sg; | |
2231 | unsigned int i; | |
2232 | ||
2233 | if (orig_st->nents == orig_st->orig_nents) | |
935a2f77 | 2234 | return false; |
0c40ce13 | 2235 | |
8bfc478f | 2236 | if (sg_alloc_table(&new_st, orig_st->nents, GFP_KERNEL | __GFP_NOWARN)) |
935a2f77 | 2237 | return false; |
0c40ce13 TU |
2238 | |
2239 | new_sg = new_st.sgl; | |
2240 | for_each_sg(orig_st->sgl, sg, orig_st->nents, i) { | |
2241 | sg_set_page(new_sg, sg_page(sg), sg->length, 0); | |
2242 | /* called before being DMA mapped, no need to copy sg->dma_* */ | |
2243 | new_sg = sg_next(new_sg); | |
2244 | } | |
c2dc6cc9 | 2245 | GEM_BUG_ON(new_sg); /* Should walk exactly nents and hit the end */ |
0c40ce13 TU |
2246 | |
2247 | sg_free_table(orig_st); | |
2248 | ||
2249 | *orig_st = new_st; | |
935a2f77 | 2250 | return true; |
0c40ce13 TU |
2251 | } |
2252 | ||
03ac84f1 | 2253 | static struct sg_table * |
6c085a72 | 2254 | i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj) |
e5281ccd | 2255 | { |
fac5e23e | 2256 | struct drm_i915_private *dev_priv = to_i915(obj->base.dev); |
d766ef53 CW |
2257 | const unsigned long page_count = obj->base.size / PAGE_SIZE; |
2258 | unsigned long i; | |
e5281ccd | 2259 | struct address_space *mapping; |
9da3da66 CW |
2260 | struct sg_table *st; |
2261 | struct scatterlist *sg; | |
85d1225e | 2262 | struct sgt_iter sgt_iter; |
e5281ccd | 2263 | struct page *page; |
90797e6d | 2264 | unsigned long last_pfn = 0; /* suppress gcc warning */ |
4ff340f0 | 2265 | unsigned int max_segment; |
e2273302 | 2266 | int ret; |
6c085a72 | 2267 | gfp_t gfp; |
e5281ccd | 2268 | |
6c085a72 CW |
2269 | /* Assert that the object is not currently in any GPU domain. As it |
2270 | * wasn't in the GTT, there shouldn't be any way it could have been in | |
2271 | * a GPU cache | |
2272 | */ | |
03ac84f1 CW |
2273 | GEM_BUG_ON(obj->base.read_domains & I915_GEM_GPU_DOMAINS); |
2274 | GEM_BUG_ON(obj->base.write_domain & I915_GEM_GPU_DOMAINS); | |
6c085a72 | 2275 | |
7453c549 | 2276 | max_segment = swiotlb_max_segment(); |
871dfbd6 | 2277 | if (!max_segment) |
4ff340f0 | 2278 | max_segment = rounddown(UINT_MAX, PAGE_SIZE); |
871dfbd6 | 2279 | |
9da3da66 CW |
2280 | st = kmalloc(sizeof(*st), GFP_KERNEL); |
2281 | if (st == NULL) | |
03ac84f1 | 2282 | return ERR_PTR(-ENOMEM); |
9da3da66 | 2283 | |
d766ef53 | 2284 | rebuild_st: |
9da3da66 | 2285 | if (sg_alloc_table(st, page_count, GFP_KERNEL)) { |
9da3da66 | 2286 | kfree(st); |
03ac84f1 | 2287 | return ERR_PTR(-ENOMEM); |
9da3da66 | 2288 | } |
e5281ccd | 2289 | |
9da3da66 CW |
2290 | /* Get the list of pages out of our struct file. They'll be pinned |
2291 | * at this point until we release them. | |
2292 | * | |
2293 | * Fail silently without starting the shrinker | |
2294 | */ | |
93c76a3d | 2295 | mapping = obj->base.filp->f_mapping; |
c62d2555 | 2296 | gfp = mapping_gfp_constraint(mapping, ~(__GFP_IO | __GFP_RECLAIM)); |
d0164adc | 2297 | gfp |= __GFP_NORETRY | __GFP_NOWARN; |
90797e6d ID |
2298 | sg = st->sgl; |
2299 | st->nents = 0; | |
2300 | for (i = 0; i < page_count; i++) { | |
6c085a72 CW |
2301 | page = shmem_read_mapping_page_gfp(mapping, i, gfp); |
2302 | if (IS_ERR(page)) { | |
21ab4e74 CW |
2303 | i915_gem_shrink(dev_priv, |
2304 | page_count, | |
2305 | I915_SHRINK_BOUND | | |
2306 | I915_SHRINK_UNBOUND | | |
2307 | I915_SHRINK_PURGEABLE); | |
6c085a72 CW |
2308 | page = shmem_read_mapping_page_gfp(mapping, i, gfp); |
2309 | } | |
2310 | if (IS_ERR(page)) { | |
2311 | /* We've tried hard to allocate the memory by reaping | |
2312 | * our own buffer, now let the real VM do its job and | |
2313 | * go down in flames if truly OOM. | |
2314 | */ | |
f461d1be | 2315 | page = shmem_read_mapping_page(mapping, i); |
e2273302 ID |
2316 | if (IS_ERR(page)) { |
2317 | ret = PTR_ERR(page); | |
b17993b7 | 2318 | goto err_sg; |
e2273302 | 2319 | } |
6c085a72 | 2320 | } |
871dfbd6 CW |
2321 | if (!i || |
2322 | sg->length >= max_segment || | |
2323 | page_to_pfn(page) != last_pfn + 1) { | |
90797e6d ID |
2324 | if (i) |
2325 | sg = sg_next(sg); | |
2326 | st->nents++; | |
2327 | sg_set_page(sg, page, PAGE_SIZE, 0); | |
2328 | } else { | |
2329 | sg->length += PAGE_SIZE; | |
2330 | } | |
2331 | last_pfn = page_to_pfn(page); | |
3bbbe706 DV |
2332 | |
2333 | /* Check that the i965g/gm workaround works. */ | |
2334 | WARN_ON((gfp & __GFP_DMA32) && (last_pfn >= 0x00100000UL)); | |
e5281ccd | 2335 | } |
871dfbd6 | 2336 | if (sg) /* loop terminated early; short sg table */ |
426729dc | 2337 | sg_mark_end(sg); |
74ce6b6c | 2338 | |
0c40ce13 TU |
2339 | /* Trim unused sg entries to avoid wasting memory. */ |
2340 | i915_sg_trim(st); | |
2341 | ||
03ac84f1 | 2342 | ret = i915_gem_gtt_prepare_pages(obj, st); |
d766ef53 CW |
2343 | if (ret) { |
2344 | /* DMA remapping failed? One possible cause is that | |
2345 | * it could not reserve enough large entries, asking | |
2346 | * for PAGE_SIZE chunks instead may be helpful. | |
2347 | */ | |
2348 | if (max_segment > PAGE_SIZE) { | |
2349 | for_each_sgt_page(page, sgt_iter, st) | |
2350 | put_page(page); | |
2351 | sg_free_table(st); | |
2352 | ||
2353 | max_segment = PAGE_SIZE; | |
2354 | goto rebuild_st; | |
2355 | } else { | |
2356 | dev_warn(&dev_priv->drm.pdev->dev, | |
2357 | "Failed to DMA remap %lu pages\n", | |
2358 | page_count); | |
2359 | goto err_pages; | |
2360 | } | |
2361 | } | |
e2273302 | 2362 | |
6dacfd2f | 2363 | if (i915_gem_object_needs_bit17_swizzle(obj)) |
03ac84f1 | 2364 | i915_gem_object_do_bit_17_swizzle(obj, st); |
e5281ccd | 2365 | |
03ac84f1 | 2366 | return st; |
e5281ccd | 2367 | |
b17993b7 | 2368 | err_sg: |
90797e6d | 2369 | sg_mark_end(sg); |
b17993b7 | 2370 | err_pages: |
85d1225e DG |
2371 | for_each_sgt_page(page, sgt_iter, st) |
2372 | put_page(page); | |
9da3da66 CW |
2373 | sg_free_table(st); |
2374 | kfree(st); | |
0820baf3 CW |
2375 | |
2376 | /* shmemfs first checks if there is enough memory to allocate the page | |
2377 | * and reports ENOSPC should there be insufficient, along with the usual | |
2378 | * ENOMEM for a genuine allocation failure. | |
2379 | * | |
2380 | * We use ENOSPC in our driver to mean that we have run out of aperture | |
2381 | * space and so want to translate the error from shmemfs back to our | |
2382 | * usual understanding of ENOMEM. | |
2383 | */ | |
e2273302 ID |
2384 | if (ret == -ENOSPC) |
2385 | ret = -ENOMEM; | |
2386 | ||
03ac84f1 CW |
2387 | return ERR_PTR(ret); |
2388 | } | |
2389 | ||
2390 | void __i915_gem_object_set_pages(struct drm_i915_gem_object *obj, | |
2391 | struct sg_table *pages) | |
2392 | { | |
1233e2db | 2393 | lockdep_assert_held(&obj->mm.lock); |
03ac84f1 CW |
2394 | |
2395 | obj->mm.get_page.sg_pos = pages->sgl; | |
2396 | obj->mm.get_page.sg_idx = 0; | |
2397 | ||
2398 | obj->mm.pages = pages; | |
2c3a3f44 CW |
2399 | |
2400 | if (i915_gem_object_is_tiled(obj) && | |
2401 | to_i915(obj->base.dev)->quirks & QUIRK_PIN_SWIZZLED_PAGES) { | |
2402 | GEM_BUG_ON(obj->mm.quirked); | |
2403 | __i915_gem_object_pin_pages(obj); | |
2404 | obj->mm.quirked = true; | |
2405 | } | |
03ac84f1 CW |
2406 | } |
2407 | ||
2408 | static int ____i915_gem_object_get_pages(struct drm_i915_gem_object *obj) | |
2409 | { | |
2410 | struct sg_table *pages; | |
2411 | ||
2c3a3f44 CW |
2412 | GEM_BUG_ON(i915_gem_object_has_pinned_pages(obj)); |
2413 | ||
03ac84f1 CW |
2414 | if (unlikely(obj->mm.madv != I915_MADV_WILLNEED)) { |
2415 | DRM_DEBUG("Attempting to obtain a purgeable object\n"); | |
2416 | return -EFAULT; | |
2417 | } | |
2418 | ||
2419 | pages = obj->ops->get_pages(obj); | |
2420 | if (unlikely(IS_ERR(pages))) | |
2421 | return PTR_ERR(pages); | |
2422 | ||
2423 | __i915_gem_object_set_pages(obj, pages); | |
2424 | return 0; | |
673a394b EA |
2425 | } |
2426 | ||
37e680a1 | 2427 | /* Ensure that the associated pages are gathered from the backing storage |
1233e2db | 2428 | * and pinned into our object. i915_gem_object_pin_pages() may be called |
37e680a1 | 2429 | * multiple times before they are released by a single call to |
1233e2db | 2430 | * i915_gem_object_unpin_pages() - once the pages are no longer referenced |
37e680a1 CW |
2431 | * either as a result of memory pressure (reaping pages under the shrinker) |
2432 | * or as the object is itself released. | |
2433 | */ | |
a4f5ea64 | 2434 | int __i915_gem_object_get_pages(struct drm_i915_gem_object *obj) |
37e680a1 | 2435 | { |
03ac84f1 | 2436 | int err; |
37e680a1 | 2437 | |
1233e2db CW |
2438 | err = mutex_lock_interruptible(&obj->mm.lock); |
2439 | if (err) | |
2440 | return err; | |
4c7d62c6 | 2441 | |
2c3a3f44 CW |
2442 | if (unlikely(!obj->mm.pages)) { |
2443 | err = ____i915_gem_object_get_pages(obj); | |
2444 | if (err) | |
2445 | goto unlock; | |
37e680a1 | 2446 | |
2c3a3f44 CW |
2447 | smp_mb__before_atomic(); |
2448 | } | |
2449 | atomic_inc(&obj->mm.pages_pin_count); | |
ee286370 | 2450 | |
1233e2db CW |
2451 | unlock: |
2452 | mutex_unlock(&obj->mm.lock); | |
03ac84f1 | 2453 | return err; |
673a394b EA |
2454 | } |
2455 | ||
dd6034c6 | 2456 | /* The 'mapping' part of i915_gem_object_pin_map() below */ |
d31d7cb1 CW |
2457 | static void *i915_gem_object_map(const struct drm_i915_gem_object *obj, |
2458 | enum i915_map_type type) | |
dd6034c6 DG |
2459 | { |
2460 | unsigned long n_pages = obj->base.size >> PAGE_SHIFT; | |
a4f5ea64 | 2461 | struct sg_table *sgt = obj->mm.pages; |
85d1225e DG |
2462 | struct sgt_iter sgt_iter; |
2463 | struct page *page; | |
b338fa47 DG |
2464 | struct page *stack_pages[32]; |
2465 | struct page **pages = stack_pages; | |
dd6034c6 | 2466 | unsigned long i = 0; |
d31d7cb1 | 2467 | pgprot_t pgprot; |
dd6034c6 DG |
2468 | void *addr; |
2469 | ||
2470 | /* A single page can always be kmapped */ | |
d31d7cb1 | 2471 | if (n_pages == 1 && type == I915_MAP_WB) |
dd6034c6 DG |
2472 | return kmap(sg_page(sgt->sgl)); |
2473 | ||
b338fa47 DG |
2474 | if (n_pages > ARRAY_SIZE(stack_pages)) { |
2475 | /* Too big for stack -- allocate temporary array instead */ | |
2476 | pages = drm_malloc_gfp(n_pages, sizeof(*pages), GFP_TEMPORARY); | |
2477 | if (!pages) | |
2478 | return NULL; | |
2479 | } | |
dd6034c6 | 2480 | |
85d1225e DG |
2481 | for_each_sgt_page(page, sgt_iter, sgt) |
2482 | pages[i++] = page; | |
dd6034c6 DG |
2483 | |
2484 | /* Check that we have the expected number of pages */ | |
2485 | GEM_BUG_ON(i != n_pages); | |
2486 | ||
d31d7cb1 CW |
2487 | switch (type) { |
2488 | case I915_MAP_WB: | |
2489 | pgprot = PAGE_KERNEL; | |
2490 | break; | |
2491 | case I915_MAP_WC: | |
2492 | pgprot = pgprot_writecombine(PAGE_KERNEL_IO); | |
2493 | break; | |
2494 | } | |
2495 | addr = vmap(pages, n_pages, 0, pgprot); | |
dd6034c6 | 2496 | |
b338fa47 DG |
2497 | if (pages != stack_pages) |
2498 | drm_free_large(pages); | |
dd6034c6 DG |
2499 | |
2500 | return addr; | |
2501 | } | |
2502 | ||
2503 | /* get, pin, and map the pages of the object into kernel space */ | |
d31d7cb1 CW |
2504 | void *i915_gem_object_pin_map(struct drm_i915_gem_object *obj, |
2505 | enum i915_map_type type) | |
0a798eb9 | 2506 | { |
d31d7cb1 CW |
2507 | enum i915_map_type has_type; |
2508 | bool pinned; | |
2509 | void *ptr; | |
0a798eb9 CW |
2510 | int ret; |
2511 | ||
d31d7cb1 | 2512 | GEM_BUG_ON(!i915_gem_object_has_struct_page(obj)); |
0a798eb9 | 2513 | |
1233e2db | 2514 | ret = mutex_lock_interruptible(&obj->mm.lock); |
0a798eb9 CW |
2515 | if (ret) |
2516 | return ERR_PTR(ret); | |
2517 | ||
1233e2db CW |
2518 | pinned = true; |
2519 | if (!atomic_inc_not_zero(&obj->mm.pages_pin_count)) { | |
2c3a3f44 CW |
2520 | if (unlikely(!obj->mm.pages)) { |
2521 | ret = ____i915_gem_object_get_pages(obj); | |
2522 | if (ret) | |
2523 | goto err_unlock; | |
1233e2db | 2524 | |
2c3a3f44 CW |
2525 | smp_mb__before_atomic(); |
2526 | } | |
2527 | atomic_inc(&obj->mm.pages_pin_count); | |
1233e2db CW |
2528 | pinned = false; |
2529 | } | |
2530 | GEM_BUG_ON(!obj->mm.pages); | |
0a798eb9 | 2531 | |
a4f5ea64 | 2532 | ptr = ptr_unpack_bits(obj->mm.mapping, has_type); |
d31d7cb1 CW |
2533 | if (ptr && has_type != type) { |
2534 | if (pinned) { | |
2535 | ret = -EBUSY; | |
1233e2db | 2536 | goto err_unpin; |
0a798eb9 | 2537 | } |
d31d7cb1 CW |
2538 | |
2539 | if (is_vmalloc_addr(ptr)) | |
2540 | vunmap(ptr); | |
2541 | else | |
2542 | kunmap(kmap_to_page(ptr)); | |
2543 | ||
a4f5ea64 | 2544 | ptr = obj->mm.mapping = NULL; |
0a798eb9 CW |
2545 | } |
2546 | ||
d31d7cb1 CW |
2547 | if (!ptr) { |
2548 | ptr = i915_gem_object_map(obj, type); | |
2549 | if (!ptr) { | |
2550 | ret = -ENOMEM; | |
1233e2db | 2551 | goto err_unpin; |
d31d7cb1 CW |
2552 | } |
2553 | ||
a4f5ea64 | 2554 | obj->mm.mapping = ptr_pack_bits(ptr, type); |
d31d7cb1 CW |
2555 | } |
2556 | ||
1233e2db CW |
2557 | out_unlock: |
2558 | mutex_unlock(&obj->mm.lock); | |
d31d7cb1 CW |
2559 | return ptr; |
2560 | ||
1233e2db CW |
2561 | err_unpin: |
2562 | atomic_dec(&obj->mm.pages_pin_count); | |
2563 | err_unlock: | |
2564 | ptr = ERR_PTR(ret); | |
2565 | goto out_unlock; | |
0a798eb9 CW |
2566 | } |
2567 | ||
6095868a | 2568 | static bool ban_context(const struct i915_gem_context *ctx) |
be62acb4 | 2569 | { |
6095868a CW |
2570 | return (i915_gem_context_is_bannable(ctx) && |
2571 | ctx->ban_score >= CONTEXT_SCORE_BAN_THRESHOLD); | |
be62acb4 MK |
2572 | } |
2573 | ||
e5e1fc47 | 2574 | static void i915_gem_context_mark_guilty(struct i915_gem_context *ctx) |
aa60c664 | 2575 | { |
bc1d53c6 | 2576 | ctx->guilty_count++; |
6095868a CW |
2577 | ctx->ban_score += CONTEXT_SCORE_GUILTY; |
2578 | if (ban_context(ctx)) | |
2579 | i915_gem_context_set_banned(ctx); | |
b083a087 MK |
2580 | |
2581 | DRM_DEBUG_DRIVER("context %s marked guilty (score %d) banned? %s\n", | |
bc1d53c6 | 2582 | ctx->name, ctx->ban_score, |
6095868a | 2583 | yesno(i915_gem_context_is_banned(ctx))); |
b083a087 | 2584 | |
6095868a | 2585 | if (!i915_gem_context_is_banned(ctx) || IS_ERR_OR_NULL(ctx->file_priv)) |
b083a087 MK |
2586 | return; |
2587 | ||
d9e9da64 CW |
2588 | ctx->file_priv->context_bans++; |
2589 | DRM_DEBUG_DRIVER("client %s has had %d context banned\n", | |
2590 | ctx->name, ctx->file_priv->context_bans); | |
e5e1fc47 MK |
2591 | } |
2592 | ||
2593 | static void i915_gem_context_mark_innocent(struct i915_gem_context *ctx) | |
2594 | { | |
bc1d53c6 | 2595 | ctx->active_count++; |
aa60c664 MK |
2596 | } |
2597 | ||
8d9fc7fd | 2598 | struct drm_i915_gem_request * |
0bc40be8 | 2599 | i915_gem_find_active_request(struct intel_engine_cs *engine) |
9375e446 | 2600 | { |
4db080f9 CW |
2601 | struct drm_i915_gem_request *request; |
2602 | ||
f69a02c9 CW |
2603 | /* We are called by the error capture and reset at a random |
2604 | * point in time. In particular, note that neither is crucially | |
2605 | * ordered with an interrupt. After a hang, the GPU is dead and we | |
2606 | * assume that no more writes can happen (we waited long enough for | |
2607 | * all writes that were in transaction to be flushed) - adding an | |
2608 | * extra delay for a recent interrupt is pointless. Hence, we do | |
2609 | * not need an engine->irq_seqno_barrier() before the seqno reads. | |
2610 | */ | |
73cb9701 | 2611 | list_for_each_entry(request, &engine->timeline->requests, link) { |
80b204bc | 2612 | if (__i915_gem_request_completed(request)) |
4db080f9 | 2613 | continue; |
aa60c664 | 2614 | |
36193acd | 2615 | GEM_BUG_ON(request->engine != engine); |
c00122f3 CW |
2616 | GEM_BUG_ON(test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, |
2617 | &request->fence.flags)); | |
b6b0fac0 | 2618 | return request; |
4db080f9 | 2619 | } |
b6b0fac0 MK |
2620 | |
2621 | return NULL; | |
2622 | } | |
2623 | ||
bf2f0436 MK |
2624 | static bool engine_stalled(struct intel_engine_cs *engine) |
2625 | { | |
2626 | if (!engine->hangcheck.stalled) | |
2627 | return false; | |
2628 | ||
2629 | /* Check for possible seqno movement after hang declaration */ | |
2630 | if (engine->hangcheck.seqno != intel_engine_get_seqno(engine)) { | |
2631 | DRM_DEBUG_DRIVER("%s pardoned\n", engine->name); | |
2632 | return false; | |
2633 | } | |
2634 | ||
2635 | return true; | |
2636 | } | |
2637 | ||
0e178aef | 2638 | int i915_gem_reset_prepare(struct drm_i915_private *dev_priv) |
4c965543 CW |
2639 | { |
2640 | struct intel_engine_cs *engine; | |
2641 | enum intel_engine_id id; | |
0e178aef | 2642 | int err = 0; |
4c965543 CW |
2643 | |
2644 | /* Ensure irq handler finishes, and not run again. */ | |
0e178aef CW |
2645 | for_each_engine(engine, dev_priv, id) { |
2646 | struct drm_i915_gem_request *request; | |
2647 | ||
fe3288b5 CW |
2648 | /* Prevent the signaler thread from updating the request |
2649 | * state (by calling dma_fence_signal) as we are processing | |
2650 | * the reset. The write from the GPU of the seqno is | |
2651 | * asynchronous and the signaler thread may see a different | |
2652 | * value to us and declare the request complete, even though | |
2653 | * the reset routine have picked that request as the active | |
2654 | * (incomplete) request. This conflict is not handled | |
2655 | * gracefully! | |
2656 | */ | |
2657 | kthread_park(engine->breadcrumbs.signaler); | |
2658 | ||
1f7b847d CW |
2659 | /* Prevent request submission to the hardware until we have |
2660 | * completed the reset in i915_gem_reset_finish(). If a request | |
2661 | * is completed by one engine, it may then queue a request | |
2662 | * to a second via its engine->irq_tasklet *just* as we are | |
2663 | * calling engine->init_hw() and also writing the ELSP. | |
2664 | * Turning off the engine->irq_tasklet until the reset is over | |
2665 | * prevents the race. | |
2666 | */ | |
4c965543 | 2667 | tasklet_kill(&engine->irq_tasklet); |
1d309634 | 2668 | tasklet_disable(&engine->irq_tasklet); |
4c965543 | 2669 | |
8c12d121 CW |
2670 | if (engine->irq_seqno_barrier) |
2671 | engine->irq_seqno_barrier(engine); | |
2672 | ||
0e178aef CW |
2673 | if (engine_stalled(engine)) { |
2674 | request = i915_gem_find_active_request(engine); | |
2675 | if (request && request->fence.error == -EIO) | |
2676 | err = -EIO; /* Previous reset failed! */ | |
2677 | } | |
2678 | } | |
2679 | ||
4c965543 | 2680 | i915_gem_revoke_fences(dev_priv); |
0e178aef CW |
2681 | |
2682 | return err; | |
4c965543 CW |
2683 | } |
2684 | ||
36193acd | 2685 | static void skip_request(struct drm_i915_gem_request *request) |
821ed7df CW |
2686 | { |
2687 | void *vaddr = request->ring->vaddr; | |
2688 | u32 head; | |
2689 | ||
2690 | /* As this request likely depends on state from the lost | |
2691 | * context, clear out all the user operations leaving the | |
2692 | * breadcrumb at the end (so we get the fence notifications). | |
2693 | */ | |
2694 | head = request->head; | |
2695 | if (request->postfix < head) { | |
2696 | memset(vaddr + head, 0, request->ring->size - head); | |
2697 | head = 0; | |
2698 | } | |
2699 | memset(vaddr + head, 0, request->postfix - head); | |
c0d5f32c CW |
2700 | |
2701 | dma_fence_set_error(&request->fence, -EIO); | |
821ed7df CW |
2702 | } |
2703 | ||
36193acd MK |
2704 | static void engine_skip_context(struct drm_i915_gem_request *request) |
2705 | { | |
2706 | struct intel_engine_cs *engine = request->engine; | |
2707 | struct i915_gem_context *hung_ctx = request->ctx; | |
2708 | struct intel_timeline *timeline; | |
2709 | unsigned long flags; | |
2710 | ||
2711 | timeline = i915_gem_context_lookup_timeline(hung_ctx, engine); | |
2712 | ||
2713 | spin_lock_irqsave(&engine->timeline->lock, flags); | |
2714 | spin_lock(&timeline->lock); | |
2715 | ||
2716 | list_for_each_entry_continue(request, &engine->timeline->requests, link) | |
2717 | if (request->ctx == hung_ctx) | |
2718 | skip_request(request); | |
2719 | ||
2720 | list_for_each_entry(request, &timeline->requests, link) | |
2721 | skip_request(request); | |
2722 | ||
2723 | spin_unlock(&timeline->lock); | |
2724 | spin_unlock_irqrestore(&engine->timeline->lock, flags); | |
2725 | } | |
2726 | ||
61da5362 MK |
2727 | /* Returns true if the request was guilty of hang */ |
2728 | static bool i915_gem_reset_request(struct drm_i915_gem_request *request) | |
2729 | { | |
2730 | /* Read once and return the resolution */ | |
2731 | const bool guilty = engine_stalled(request->engine); | |
2732 | ||
71895a08 MK |
2733 | /* The guilty request will get skipped on a hung engine. |
2734 | * | |
2735 | * Users of client default contexts do not rely on logical | |
2736 | * state preserved between batches so it is safe to execute | |
2737 | * queued requests following the hang. Non default contexts | |
2738 | * rely on preserved state, so skipping a batch loses the | |
2739 | * evolution of the state and it needs to be considered corrupted. | |
2740 | * Executing more queued batches on top of corrupted state is | |
2741 | * risky. But we take the risk by trying to advance through | |
2742 | * the queued requests in order to make the client behaviour | |
2743 | * more predictable around resets, by not throwing away random | |
2744 | * amount of batches it has prepared for execution. Sophisticated | |
2745 | * clients can use gem_reset_stats_ioctl and dma fence status | |
2746 | * (exported via sync_file info ioctl on explicit fences) to observe | |
2747 | * when it loses the context state and should rebuild accordingly. | |
2748 | * | |
2749 | * The context ban, and ultimately the client ban, mechanism are safety | |
2750 | * valves if client submission ends up resulting in nothing more than | |
2751 | * subsequent hangs. | |
2752 | */ | |
2753 | ||
61da5362 MK |
2754 | if (guilty) { |
2755 | i915_gem_context_mark_guilty(request->ctx); | |
2756 | skip_request(request); | |
2757 | } else { | |
2758 | i915_gem_context_mark_innocent(request->ctx); | |
2759 | dma_fence_set_error(&request->fence, -EAGAIN); | |
2760 | } | |
2761 | ||
2762 | return guilty; | |
2763 | } | |
2764 | ||
821ed7df | 2765 | static void i915_gem_reset_engine(struct intel_engine_cs *engine) |
b6b0fac0 MK |
2766 | { |
2767 | struct drm_i915_gem_request *request; | |
b6b0fac0 | 2768 | |
0bc40be8 | 2769 | request = i915_gem_find_active_request(engine); |
c0dcb203 CW |
2770 | if (request && i915_gem_reset_request(request)) { |
2771 | DRM_DEBUG_DRIVER("resetting %s to restart from tail of request 0x%x\n", | |
2772 | engine->name, request->global_seqno); | |
821ed7df | 2773 | |
c0dcb203 CW |
2774 | /* If this context is now banned, skip all pending requests. */ |
2775 | if (i915_gem_context_is_banned(request->ctx)) | |
2776 | engine_skip_context(request); | |
2777 | } | |
821ed7df CW |
2778 | |
2779 | /* Setup the CS to resume from the breadcrumb of the hung request */ | |
2780 | engine->reset_hw(engine, request); | |
4db080f9 | 2781 | } |
aa60c664 | 2782 | |
d8027093 | 2783 | void i915_gem_reset(struct drm_i915_private *dev_priv) |
4db080f9 | 2784 | { |
821ed7df | 2785 | struct intel_engine_cs *engine; |
3b3f1650 | 2786 | enum intel_engine_id id; |
608c1a52 | 2787 | |
4c7d62c6 CW |
2788 | lockdep_assert_held(&dev_priv->drm.struct_mutex); |
2789 | ||
821ed7df CW |
2790 | i915_gem_retire_requests(dev_priv); |
2791 | ||
2ae55738 CW |
2792 | for_each_engine(engine, dev_priv, id) { |
2793 | struct i915_gem_context *ctx; | |
2794 | ||
821ed7df | 2795 | i915_gem_reset_engine(engine); |
2ae55738 CW |
2796 | ctx = fetch_and_zero(&engine->last_retired_context); |
2797 | if (ctx) | |
2798 | engine->context_unpin(engine, ctx); | |
2799 | } | |
821ed7df | 2800 | |
4362f4f6 | 2801 | i915_gem_restore_fences(dev_priv); |
f2a91d1a CW |
2802 | |
2803 | if (dev_priv->gt.awake) { | |
2804 | intel_sanitize_gt_powersave(dev_priv); | |
2805 | intel_enable_gt_powersave(dev_priv); | |
2806 | if (INTEL_GEN(dev_priv) >= 6) | |
2807 | gen6_rps_busy(dev_priv); | |
2808 | } | |
821ed7df CW |
2809 | } |
2810 | ||
d8027093 CW |
2811 | void i915_gem_reset_finish(struct drm_i915_private *dev_priv) |
2812 | { | |
1f7b847d CW |
2813 | struct intel_engine_cs *engine; |
2814 | enum intel_engine_id id; | |
2815 | ||
d8027093 | 2816 | lockdep_assert_held(&dev_priv->drm.struct_mutex); |
1f7b847d | 2817 | |
fe3288b5 | 2818 | for_each_engine(engine, dev_priv, id) { |
1f7b847d | 2819 | tasklet_enable(&engine->irq_tasklet); |
fe3288b5 CW |
2820 | kthread_unpark(engine->breadcrumbs.signaler); |
2821 | } | |
d8027093 CW |
2822 | } |
2823 | ||
821ed7df CW |
2824 | static void nop_submit_request(struct drm_i915_gem_request *request) |
2825 | { | |
3cd9442f | 2826 | dma_fence_set_error(&request->fence, -EIO); |
3dcf93f7 CW |
2827 | i915_gem_request_submit(request); |
2828 | intel_engine_init_global_seqno(request->engine, request->global_seqno); | |
821ed7df CW |
2829 | } |
2830 | ||
2a20d6f8 | 2831 | static void engine_set_wedged(struct intel_engine_cs *engine) |
821ed7df | 2832 | { |
3cd9442f CW |
2833 | struct drm_i915_gem_request *request; |
2834 | unsigned long flags; | |
2835 | ||
20e4933c CW |
2836 | /* We need to be sure that no thread is running the old callback as |
2837 | * we install the nop handler (otherwise we would submit a request | |
2838 | * to hardware that will never complete). In order to prevent this | |
2839 | * race, we wait until the machine is idle before making the swap | |
2840 | * (using stop_machine()). | |
2841 | */ | |
821ed7df | 2842 | engine->submit_request = nop_submit_request; |
70c2a24d | 2843 | |
3cd9442f CW |
2844 | /* Mark all executing requests as skipped */ |
2845 | spin_lock_irqsave(&engine->timeline->lock, flags); | |
2846 | list_for_each_entry(request, &engine->timeline->requests, link) | |
2847 | dma_fence_set_error(&request->fence, -EIO); | |
2848 | spin_unlock_irqrestore(&engine->timeline->lock, flags); | |
2849 | ||
c4b0930b CW |
2850 | /* Mark all pending requests as complete so that any concurrent |
2851 | * (lockless) lookup doesn't try and wait upon the request as we | |
2852 | * reset it. | |
2853 | */ | |
73cb9701 | 2854 | intel_engine_init_global_seqno(engine, |
cb399eab | 2855 | intel_engine_last_submit(engine)); |
c4b0930b | 2856 | |
dcb4c12a OM |
2857 | /* |
2858 | * Clear the execlists queue up before freeing the requests, as those | |
2859 | * are the ones that keep the context and ringbuffer backing objects | |
2860 | * pinned in place. | |
2861 | */ | |
dcb4c12a | 2862 | |
7de1691a | 2863 | if (i915.enable_execlists) { |
663f71e7 CW |
2864 | unsigned long flags; |
2865 | ||
2866 | spin_lock_irqsave(&engine->timeline->lock, flags); | |
2867 | ||
70c2a24d CW |
2868 | i915_gem_request_put(engine->execlist_port[0].request); |
2869 | i915_gem_request_put(engine->execlist_port[1].request); | |
2870 | memset(engine->execlist_port, 0, sizeof(engine->execlist_port)); | |
20311bd3 CW |
2871 | engine->execlist_queue = RB_ROOT; |
2872 | engine->execlist_first = NULL; | |
663f71e7 CW |
2873 | |
2874 | spin_unlock_irqrestore(&engine->timeline->lock, flags); | |
dcb4c12a | 2875 | } |
673a394b EA |
2876 | } |
2877 | ||
20e4933c | 2878 | static int __i915_gem_set_wedged_BKL(void *data) |
673a394b | 2879 | { |
20e4933c | 2880 | struct drm_i915_private *i915 = data; |
e2f80391 | 2881 | struct intel_engine_cs *engine; |
3b3f1650 | 2882 | enum intel_engine_id id; |
673a394b | 2883 | |
20e4933c | 2884 | for_each_engine(engine, i915, id) |
2a20d6f8 | 2885 | engine_set_wedged(engine); |
20e4933c CW |
2886 | |
2887 | return 0; | |
2888 | } | |
2889 | ||
2890 | void i915_gem_set_wedged(struct drm_i915_private *dev_priv) | |
2891 | { | |
821ed7df CW |
2892 | lockdep_assert_held(&dev_priv->drm.struct_mutex); |
2893 | set_bit(I915_WEDGED, &dev_priv->gpu_error.flags); | |
4db080f9 | 2894 | |
20e4933c | 2895 | stop_machine(__i915_gem_set_wedged_BKL, dev_priv, NULL); |
dfaae392 | 2896 | |
20e4933c | 2897 | i915_gem_context_lost(dev_priv); |
821ed7df | 2898 | i915_gem_retire_requests(dev_priv); |
20e4933c CW |
2899 | |
2900 | mod_delayed_work(dev_priv->wq, &dev_priv->gt.idle_work, 0); | |
673a394b EA |
2901 | } |
2902 | ||
75ef9da2 | 2903 | static void |
673a394b EA |
2904 | i915_gem_retire_work_handler(struct work_struct *work) |
2905 | { | |
b29c19b6 | 2906 | struct drm_i915_private *dev_priv = |
67d97da3 | 2907 | container_of(work, typeof(*dev_priv), gt.retire_work.work); |
91c8a326 | 2908 | struct drm_device *dev = &dev_priv->drm; |
673a394b | 2909 | |
891b48cf | 2910 | /* Come back later if the device is busy... */ |
b29c19b6 | 2911 | if (mutex_trylock(&dev->struct_mutex)) { |
67d97da3 | 2912 | i915_gem_retire_requests(dev_priv); |
b29c19b6 | 2913 | mutex_unlock(&dev->struct_mutex); |
673a394b | 2914 | } |
67d97da3 CW |
2915 | |
2916 | /* Keep the retire handler running until we are finally idle. | |
2917 | * We do not need to do this test under locking as in the worst-case | |
2918 | * we queue the retire worker once too often. | |
2919 | */ | |
c9615613 CW |
2920 | if (READ_ONCE(dev_priv->gt.awake)) { |
2921 | i915_queue_hangcheck(dev_priv); | |
67d97da3 CW |
2922 | queue_delayed_work(dev_priv->wq, |
2923 | &dev_priv->gt.retire_work, | |
bcb45086 | 2924 | round_jiffies_up_relative(HZ)); |
c9615613 | 2925 | } |
b29c19b6 | 2926 | } |
0a58705b | 2927 | |
b29c19b6 CW |
2928 | static void |
2929 | i915_gem_idle_work_handler(struct work_struct *work) | |
2930 | { | |
2931 | struct drm_i915_private *dev_priv = | |
67d97da3 | 2932 | container_of(work, typeof(*dev_priv), gt.idle_work.work); |
91c8a326 | 2933 | struct drm_device *dev = &dev_priv->drm; |
b4ac5afc | 2934 | struct intel_engine_cs *engine; |
3b3f1650 | 2935 | enum intel_engine_id id; |
67d97da3 CW |
2936 | bool rearm_hangcheck; |
2937 | ||
2938 | if (!READ_ONCE(dev_priv->gt.awake)) | |
2939 | return; | |
2940 | ||
0cb5670b ID |
2941 | /* |
2942 | * Wait for last execlists context complete, but bail out in case a | |
2943 | * new request is submitted. | |
2944 | */ | |
2945 | wait_for(READ_ONCE(dev_priv->gt.active_requests) || | |
2946 | intel_execlists_idle(dev_priv), 10); | |
2947 | ||
28176ef4 | 2948 | if (READ_ONCE(dev_priv->gt.active_requests)) |
67d97da3 CW |
2949 | return; |
2950 | ||
2951 | rearm_hangcheck = | |
2952 | cancel_delayed_work_sync(&dev_priv->gpu_error.hangcheck_work); | |
2953 | ||
2954 | if (!mutex_trylock(&dev->struct_mutex)) { | |
2955 | /* Currently busy, come back later */ | |
2956 | mod_delayed_work(dev_priv->wq, | |
2957 | &dev_priv->gt.idle_work, | |
2958 | msecs_to_jiffies(50)); | |
2959 | goto out_rearm; | |
2960 | } | |
2961 | ||
93c97dc1 ID |
2962 | /* |
2963 | * New request retired after this work handler started, extend active | |
2964 | * period until next instance of the work. | |
2965 | */ | |
2966 | if (work_pending(work)) | |
2967 | goto out_unlock; | |
2968 | ||
28176ef4 | 2969 | if (dev_priv->gt.active_requests) |
67d97da3 | 2970 | goto out_unlock; |
b29c19b6 | 2971 | |
0cb5670b ID |
2972 | if (wait_for(intel_execlists_idle(dev_priv), 10)) |
2973 | DRM_ERROR("Timeout waiting for engines to idle\n"); | |
2974 | ||
3b3f1650 | 2975 | for_each_engine(engine, dev_priv, id) |
67d97da3 | 2976 | i915_gem_batch_pool_fini(&engine->batch_pool); |
35c94185 | 2977 | |
67d97da3 CW |
2978 | GEM_BUG_ON(!dev_priv->gt.awake); |
2979 | dev_priv->gt.awake = false; | |
2980 | rearm_hangcheck = false; | |
30ecad77 | 2981 | |
67d97da3 CW |
2982 | if (INTEL_GEN(dev_priv) >= 6) |
2983 | gen6_rps_idle(dev_priv); | |
2984 | intel_runtime_pm_put(dev_priv); | |
2985 | out_unlock: | |
2986 | mutex_unlock(&dev->struct_mutex); | |
b29c19b6 | 2987 | |
67d97da3 CW |
2988 | out_rearm: |
2989 | if (rearm_hangcheck) { | |
2990 | GEM_BUG_ON(!dev_priv->gt.awake); | |
2991 | i915_queue_hangcheck(dev_priv); | |
35c94185 | 2992 | } |
673a394b EA |
2993 | } |
2994 | ||
b1f788c6 CW |
2995 | void i915_gem_close_object(struct drm_gem_object *gem, struct drm_file *file) |
2996 | { | |
2997 | struct drm_i915_gem_object *obj = to_intel_bo(gem); | |
2998 | struct drm_i915_file_private *fpriv = file->driver_priv; | |
2999 | struct i915_vma *vma, *vn; | |
3000 | ||
3001 | mutex_lock(&obj->base.dev->struct_mutex); | |
3002 | list_for_each_entry_safe(vma, vn, &obj->vma_list, obj_link) | |
3003 | if (vma->vm->file == fpriv) | |
3004 | i915_vma_close(vma); | |
f8a7fde4 CW |
3005 | |
3006 | if (i915_gem_object_is_active(obj) && | |
3007 | !i915_gem_object_has_active_reference(obj)) { | |
3008 | i915_gem_object_set_active_reference(obj); | |
3009 | i915_gem_object_get(obj); | |
3010 | } | |
b1f788c6 CW |
3011 | mutex_unlock(&obj->base.dev->struct_mutex); |
3012 | } | |
3013 | ||
e95433c7 CW |
3014 | static unsigned long to_wait_timeout(s64 timeout_ns) |
3015 | { | |
3016 | if (timeout_ns < 0) | |
3017 | return MAX_SCHEDULE_TIMEOUT; | |
3018 | ||
3019 | if (timeout_ns == 0) | |
3020 | return 0; | |
3021 | ||
3022 | return nsecs_to_jiffies_timeout(timeout_ns); | |
3023 | } | |
3024 | ||
23ba4fd0 BW |
3025 | /** |
3026 | * i915_gem_wait_ioctl - implements DRM_IOCTL_I915_GEM_WAIT | |
14bb2c11 TU |
3027 | * @dev: drm device pointer |
3028 | * @data: ioctl data blob | |
3029 | * @file: drm file pointer | |
23ba4fd0 BW |
3030 | * |
3031 | * Returns 0 if successful, else an error is returned with the remaining time in | |
3032 | * the timeout parameter. | |
3033 | * -ETIME: object is still busy after timeout | |
3034 | * -ERESTARTSYS: signal interrupted the wait | |
3035 | * -ENONENT: object doesn't exist | |
3036 | * Also possible, but rare: | |
3037 | * -EAGAIN: GPU wedged | |
3038 | * -ENOMEM: damn | |
3039 | * -ENODEV: Internal IRQ fail | |
3040 | * -E?: The add request failed | |
3041 | * | |
3042 | * The wait ioctl with a timeout of 0 reimplements the busy ioctl. With any | |
3043 | * non-zero timeout parameter the wait ioctl will wait for the given number of | |
3044 | * nanoseconds on an object becoming unbusy. Since the wait itself does so | |
3045 | * without holding struct_mutex the object may become re-busied before this | |
3046 | * function completes. A similar but shorter * race condition exists in the busy | |
3047 | * ioctl | |
3048 | */ | |
3049 | int | |
3050 | i915_gem_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *file) | |
3051 | { | |
3052 | struct drm_i915_gem_wait *args = data; | |
3053 | struct drm_i915_gem_object *obj; | |
e95433c7 CW |
3054 | ktime_t start; |
3055 | long ret; | |
23ba4fd0 | 3056 | |
11b5d511 DV |
3057 | if (args->flags != 0) |
3058 | return -EINVAL; | |
3059 | ||
03ac0642 | 3060 | obj = i915_gem_object_lookup(file, args->bo_handle); |
033d549b | 3061 | if (!obj) |
23ba4fd0 | 3062 | return -ENOENT; |
23ba4fd0 | 3063 | |
e95433c7 CW |
3064 | start = ktime_get(); |
3065 | ||
3066 | ret = i915_gem_object_wait(obj, | |
3067 | I915_WAIT_INTERRUPTIBLE | I915_WAIT_ALL, | |
3068 | to_wait_timeout(args->timeout_ns), | |
3069 | to_rps_client(file)); | |
3070 | ||
3071 | if (args->timeout_ns > 0) { | |
3072 | args->timeout_ns -= ktime_to_ns(ktime_sub(ktime_get(), start)); | |
3073 | if (args->timeout_ns < 0) | |
3074 | args->timeout_ns = 0; | |
b4716185 CW |
3075 | } |
3076 | ||
f0cd5182 | 3077 | i915_gem_object_put(obj); |
ff865885 | 3078 | return ret; |
23ba4fd0 BW |
3079 | } |
3080 | ||
73cb9701 | 3081 | static int wait_for_timeline(struct i915_gem_timeline *tl, unsigned int flags) |
4df2faf4 | 3082 | { |
73cb9701 | 3083 | int ret, i; |
4df2faf4 | 3084 | |
73cb9701 CW |
3085 | for (i = 0; i < ARRAY_SIZE(tl->engine); i++) { |
3086 | ret = i915_gem_active_wait(&tl->engine[i].last_request, flags); | |
3087 | if (ret) | |
3088 | return ret; | |
3089 | } | |
62e63007 | 3090 | |
73cb9701 CW |
3091 | return 0; |
3092 | } | |
3093 | ||
3094 | int i915_gem_wait_for_idle(struct drm_i915_private *i915, unsigned int flags) | |
3095 | { | |
73cb9701 CW |
3096 | int ret; |
3097 | ||
9caa34aa CW |
3098 | if (flags & I915_WAIT_LOCKED) { |
3099 | struct i915_gem_timeline *tl; | |
3100 | ||
3101 | lockdep_assert_held(&i915->drm.struct_mutex); | |
3102 | ||
3103 | list_for_each_entry(tl, &i915->gt.timelines, link) { | |
3104 | ret = wait_for_timeline(tl, flags); | |
3105 | if (ret) | |
3106 | return ret; | |
3107 | } | |
3108 | } else { | |
3109 | ret = wait_for_timeline(&i915->gt.global_timeline, flags); | |
1ec14ad3 CW |
3110 | if (ret) |
3111 | return ret; | |
3112 | } | |
4df2faf4 | 3113 | |
8a1a49f9 | 3114 | return 0; |
4df2faf4 DV |
3115 | } |
3116 | ||
d0da48cf CW |
3117 | void i915_gem_clflush_object(struct drm_i915_gem_object *obj, |
3118 | bool force) | |
673a394b | 3119 | { |
673a394b EA |
3120 | /* If we don't have a page list set up, then we're not pinned |
3121 | * to GPU, and we can ignore the cache flush because it'll happen | |
3122 | * again at bind time. | |
3123 | */ | |
a4f5ea64 | 3124 | if (!obj->mm.pages) |
d0da48cf | 3125 | return; |
673a394b | 3126 | |
769ce464 ID |
3127 | /* |
3128 | * Stolen memory is always coherent with the GPU as it is explicitly | |
3129 | * marked as wc by the system, or the system is cache-coherent. | |
3130 | */ | |
6a2c4232 | 3131 | if (obj->stolen || obj->phys_handle) |
d0da48cf | 3132 | return; |
769ce464 | 3133 | |
9c23f7fc CW |
3134 | /* If the GPU is snooping the contents of the CPU cache, |
3135 | * we do not need to manually clear the CPU cache lines. However, | |
3136 | * the caches are only snooped when the render cache is | |
3137 | * flushed/invalidated. As we always have to emit invalidations | |
3138 | * and flushes when moving into and out of the RENDER domain, correct | |
3139 | * snooping behaviour occurs naturally as the result of our domain | |
3140 | * tracking. | |
3141 | */ | |
0f71979a CW |
3142 | if (!force && cpu_cache_is_coherent(obj->base.dev, obj->cache_level)) { |
3143 | obj->cache_dirty = true; | |
d0da48cf | 3144 | return; |
0f71979a | 3145 | } |
9c23f7fc | 3146 | |
1c5d22f7 | 3147 | trace_i915_gem_object_clflush(obj); |
a4f5ea64 | 3148 | drm_clflush_sg(obj->mm.pages); |
0f71979a | 3149 | obj->cache_dirty = false; |
e47c68e9 EA |
3150 | } |
3151 | ||
3152 | /** Flushes the GTT write domain for the object if it's dirty. */ | |
3153 | static void | |
05394f39 | 3154 | i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj) |
e47c68e9 | 3155 | { |
3b5724d7 | 3156 | struct drm_i915_private *dev_priv = to_i915(obj->base.dev); |
1c5d22f7 | 3157 | |
05394f39 | 3158 | if (obj->base.write_domain != I915_GEM_DOMAIN_GTT) |
e47c68e9 EA |
3159 | return; |
3160 | ||
63256ec5 | 3161 | /* No actual flushing is required for the GTT write domain. Writes |
3b5724d7 | 3162 | * to it "immediately" go to main memory as far as we know, so there's |
e47c68e9 | 3163 | * no chipset flush. It also doesn't land in render cache. |
63256ec5 CW |
3164 | * |
3165 | * However, we do have to enforce the order so that all writes through | |
3166 | * the GTT land before any writes to the device, such as updates to | |
3167 | * the GATT itself. | |
3b5724d7 CW |
3168 | * |
3169 | * We also have to wait a bit for the writes to land from the GTT. | |
3170 | * An uncached read (i.e. mmio) seems to be ideal for the round-trip | |
3171 | * timing. This issue has only been observed when switching quickly | |
3172 | * between GTT writes and CPU reads from inside the kernel on recent hw, | |
3173 | * and it appears to only affect discrete GTT blocks (i.e. on LLC | |
3174 | * system agents we cannot reproduce this behaviour). | |
e47c68e9 | 3175 | */ |
63256ec5 | 3176 | wmb(); |
3b5724d7 | 3177 | if (INTEL_GEN(dev_priv) >= 6 && !HAS_LLC(dev_priv)) |
3b3f1650 | 3178 | POSTING_READ(RING_ACTHD(dev_priv->engine[RCS]->mmio_base)); |
63256ec5 | 3179 | |
d243ad82 | 3180 | intel_fb_obj_flush(obj, false, write_origin(obj, I915_GEM_DOMAIN_GTT)); |
f99d7069 | 3181 | |
b0dc465f | 3182 | obj->base.write_domain = 0; |
1c5d22f7 | 3183 | trace_i915_gem_object_change_domain(obj, |
05394f39 | 3184 | obj->base.read_domains, |
b0dc465f | 3185 | I915_GEM_DOMAIN_GTT); |
e47c68e9 EA |
3186 | } |
3187 | ||
3188 | /** Flushes the CPU write domain for the object if it's dirty. */ | |
3189 | static void | |
e62b59e4 | 3190 | i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj) |
e47c68e9 | 3191 | { |
05394f39 | 3192 | if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) |
e47c68e9 EA |
3193 | return; |
3194 | ||
d0da48cf | 3195 | i915_gem_clflush_object(obj, obj->pin_display); |
de152b62 | 3196 | intel_fb_obj_flush(obj, false, ORIGIN_CPU); |
f99d7069 | 3197 | |
b0dc465f | 3198 | obj->base.write_domain = 0; |
1c5d22f7 | 3199 | trace_i915_gem_object_change_domain(obj, |
05394f39 | 3200 | obj->base.read_domains, |
b0dc465f | 3201 | I915_GEM_DOMAIN_CPU); |
e47c68e9 EA |
3202 | } |
3203 | ||
2ef7eeaa EA |
3204 | /** |
3205 | * Moves a single object to the GTT read, and possibly write domain. | |
14bb2c11 TU |
3206 | * @obj: object to act on |
3207 | * @write: ask for write access or read only | |
2ef7eeaa EA |
3208 | * |
3209 | * This function returns when the move is complete, including waiting on | |
3210 | * flushes to occur. | |
3211 | */ | |
79e53945 | 3212 | int |
2021746e | 3213 | i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write) |
2ef7eeaa | 3214 | { |
1c5d22f7 | 3215 | uint32_t old_write_domain, old_read_domains; |
e47c68e9 | 3216 | int ret; |
2ef7eeaa | 3217 | |
e95433c7 | 3218 | lockdep_assert_held(&obj->base.dev->struct_mutex); |
4c7d62c6 | 3219 | |
e95433c7 CW |
3220 | ret = i915_gem_object_wait(obj, |
3221 | I915_WAIT_INTERRUPTIBLE | | |
3222 | I915_WAIT_LOCKED | | |
3223 | (write ? I915_WAIT_ALL : 0), | |
3224 | MAX_SCHEDULE_TIMEOUT, | |
3225 | NULL); | |
88241785 CW |
3226 | if (ret) |
3227 | return ret; | |
3228 | ||
c13d87ea CW |
3229 | if (obj->base.write_domain == I915_GEM_DOMAIN_GTT) |
3230 | return 0; | |
3231 | ||
43566ded CW |
3232 | /* Flush and acquire obj->pages so that we are coherent through |
3233 | * direct access in memory with previous cached writes through | |
3234 | * shmemfs and that our cache domain tracking remains valid. | |
3235 | * For example, if the obj->filp was moved to swap without us | |
3236 | * being notified and releasing the pages, we would mistakenly | |
3237 | * continue to assume that the obj remained out of the CPU cached | |
3238 | * domain. | |
3239 | */ | |
a4f5ea64 | 3240 | ret = i915_gem_object_pin_pages(obj); |
43566ded CW |
3241 | if (ret) |
3242 | return ret; | |
3243 | ||
e62b59e4 | 3244 | i915_gem_object_flush_cpu_write_domain(obj); |
1c5d22f7 | 3245 | |
d0a57789 CW |
3246 | /* Serialise direct access to this object with the barriers for |
3247 | * coherent writes from the GPU, by effectively invalidating the | |
3248 | * GTT domain upon first access. | |
3249 | */ | |
3250 | if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0) | |
3251 | mb(); | |
3252 | ||
05394f39 CW |
3253 | old_write_domain = obj->base.write_domain; |
3254 | old_read_domains = obj->base.read_domains; | |
1c5d22f7 | 3255 | |
e47c68e9 EA |
3256 | /* It should now be out of any other write domains, and we can update |
3257 | * the domain values for our changes. | |
3258 | */ | |
40e62d5d | 3259 | GEM_BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) != 0); |
05394f39 | 3260 | obj->base.read_domains |= I915_GEM_DOMAIN_GTT; |
e47c68e9 | 3261 | if (write) { |
05394f39 CW |
3262 | obj->base.read_domains = I915_GEM_DOMAIN_GTT; |
3263 | obj->base.write_domain = I915_GEM_DOMAIN_GTT; | |
a4f5ea64 | 3264 | obj->mm.dirty = true; |
2ef7eeaa EA |
3265 | } |
3266 | ||
1c5d22f7 CW |
3267 | trace_i915_gem_object_change_domain(obj, |
3268 | old_read_domains, | |
3269 | old_write_domain); | |
3270 | ||
a4f5ea64 | 3271 | i915_gem_object_unpin_pages(obj); |
e47c68e9 EA |
3272 | return 0; |
3273 | } | |
3274 | ||
ef55f92a CW |
3275 | /** |
3276 | * Changes the cache-level of an object across all VMA. | |
14bb2c11 TU |
3277 | * @obj: object to act on |
3278 | * @cache_level: new cache level to set for the object | |
ef55f92a CW |
3279 | * |
3280 | * After this function returns, the object will be in the new cache-level | |
3281 | * across all GTT and the contents of the backing storage will be coherent, | |
3282 | * with respect to the new cache-level. In order to keep the backing storage | |
3283 | * coherent for all users, we only allow a single cache level to be set | |
3284 | * globally on the object and prevent it from being changed whilst the | |
3285 | * hardware is reading from the object. That is if the object is currently | |
3286 | * on the scanout it will be set to uncached (or equivalent display | |
3287 | * cache coherency) and all non-MOCS GPU access will also be uncached so | |
3288 | * that all direct access to the scanout remains coherent. | |
3289 | */ | |
e4ffd173 CW |
3290 | int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj, |
3291 | enum i915_cache_level cache_level) | |
3292 | { | |
aa653a68 | 3293 | struct i915_vma *vma; |
a6a7cc4b | 3294 | int ret; |
e4ffd173 | 3295 | |
4c7d62c6 CW |
3296 | lockdep_assert_held(&obj->base.dev->struct_mutex); |
3297 | ||
e4ffd173 | 3298 | if (obj->cache_level == cache_level) |
a6a7cc4b | 3299 | return 0; |
e4ffd173 | 3300 | |
ef55f92a CW |
3301 | /* Inspect the list of currently bound VMA and unbind any that would |
3302 | * be invalid given the new cache-level. This is principally to | |
3303 | * catch the issue of the CS prefetch crossing page boundaries and | |
3304 | * reading an invalid PTE on older architectures. | |
3305 | */ | |
aa653a68 CW |
3306 | restart: |
3307 | list_for_each_entry(vma, &obj->vma_list, obj_link) { | |
ef55f92a CW |
3308 | if (!drm_mm_node_allocated(&vma->node)) |
3309 | continue; | |
3310 | ||
20dfbde4 | 3311 | if (i915_vma_is_pinned(vma)) { |
ef55f92a CW |
3312 | DRM_DEBUG("can not change the cache level of pinned objects\n"); |
3313 | return -EBUSY; | |
3314 | } | |
3315 | ||
aa653a68 CW |
3316 | if (i915_gem_valid_gtt_space(vma, cache_level)) |
3317 | continue; | |
3318 | ||
3319 | ret = i915_vma_unbind(vma); | |
3320 | if (ret) | |
3321 | return ret; | |
3322 | ||
3323 | /* As unbinding may affect other elements in the | |
3324 | * obj->vma_list (due to side-effects from retiring | |
3325 | * an active vma), play safe and restart the iterator. | |
3326 | */ | |
3327 | goto restart; | |
42d6ab48 CW |
3328 | } |
3329 | ||
ef55f92a CW |
3330 | /* We can reuse the existing drm_mm nodes but need to change the |
3331 | * cache-level on the PTE. We could simply unbind them all and | |
3332 | * rebind with the correct cache-level on next use. However since | |
3333 | * we already have a valid slot, dma mapping, pages etc, we may as | |
3334 | * rewrite the PTE in the belief that doing so tramples upon less | |
3335 | * state and so involves less work. | |
3336 | */ | |
15717de2 | 3337 | if (obj->bind_count) { |
ef55f92a CW |
3338 | /* Before we change the PTE, the GPU must not be accessing it. |
3339 | * If we wait upon the object, we know that all the bound | |
3340 | * VMA are no longer active. | |
3341 | */ | |
e95433c7 CW |
3342 | ret = i915_gem_object_wait(obj, |
3343 | I915_WAIT_INTERRUPTIBLE | | |
3344 | I915_WAIT_LOCKED | | |
3345 | I915_WAIT_ALL, | |
3346 | MAX_SCHEDULE_TIMEOUT, | |
3347 | NULL); | |
e4ffd173 CW |
3348 | if (ret) |
3349 | return ret; | |
3350 | ||
0031fb96 TU |
3351 | if (!HAS_LLC(to_i915(obj->base.dev)) && |
3352 | cache_level != I915_CACHE_NONE) { | |
ef55f92a CW |
3353 | /* Access to snoopable pages through the GTT is |
3354 | * incoherent and on some machines causes a hard | |
3355 | * lockup. Relinquish the CPU mmaping to force | |
3356 | * userspace to refault in the pages and we can | |
3357 | * then double check if the GTT mapping is still | |
3358 | * valid for that pointer access. | |
3359 | */ | |
3360 | i915_gem_release_mmap(obj); | |
3361 | ||
3362 | /* As we no longer need a fence for GTT access, | |
3363 | * we can relinquish it now (and so prevent having | |
3364 | * to steal a fence from someone else on the next | |
3365 | * fence request). Note GPU activity would have | |
3366 | * dropped the fence as all snoopable access is | |
3367 | * supposed to be linear. | |
3368 | */ | |
49ef5294 CW |
3369 | list_for_each_entry(vma, &obj->vma_list, obj_link) { |
3370 | ret = i915_vma_put_fence(vma); | |
3371 | if (ret) | |
3372 | return ret; | |
3373 | } | |
ef55f92a CW |
3374 | } else { |
3375 | /* We either have incoherent backing store and | |
3376 | * so no GTT access or the architecture is fully | |
3377 | * coherent. In such cases, existing GTT mmaps | |
3378 | * ignore the cache bit in the PTE and we can | |
3379 | * rewrite it without confusing the GPU or having | |
3380 | * to force userspace to fault back in its mmaps. | |
3381 | */ | |
e4ffd173 CW |
3382 | } |
3383 | ||
1c7f4bca | 3384 | list_for_each_entry(vma, &obj->vma_list, obj_link) { |
ef55f92a CW |
3385 | if (!drm_mm_node_allocated(&vma->node)) |
3386 | continue; | |
3387 | ||
3388 | ret = i915_vma_bind(vma, cache_level, PIN_UPDATE); | |
3389 | if (ret) | |
3390 | return ret; | |
3391 | } | |
e4ffd173 CW |
3392 | } |
3393 | ||
a6a7cc4b CW |
3394 | if (obj->base.write_domain == I915_GEM_DOMAIN_CPU && |
3395 | cpu_cache_is_coherent(obj->base.dev, obj->cache_level)) | |
3396 | obj->cache_dirty = true; | |
3397 | ||
1c7f4bca | 3398 | list_for_each_entry(vma, &obj->vma_list, obj_link) |
2c22569b CW |
3399 | vma->node.color = cache_level; |
3400 | obj->cache_level = cache_level; | |
3401 | ||
e4ffd173 CW |
3402 | return 0; |
3403 | } | |
3404 | ||
199adf40 BW |
3405 | int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data, |
3406 | struct drm_file *file) | |
e6994aee | 3407 | { |
199adf40 | 3408 | struct drm_i915_gem_caching *args = data; |
e6994aee | 3409 | struct drm_i915_gem_object *obj; |
fbbd37b3 | 3410 | int err = 0; |
e6994aee | 3411 | |
fbbd37b3 CW |
3412 | rcu_read_lock(); |
3413 | obj = i915_gem_object_lookup_rcu(file, args->handle); | |
3414 | if (!obj) { | |
3415 | err = -ENOENT; | |
3416 | goto out; | |
3417 | } | |
e6994aee | 3418 | |
651d794f CW |
3419 | switch (obj->cache_level) { |
3420 | case I915_CACHE_LLC: | |
3421 | case I915_CACHE_L3_LLC: | |
3422 | args->caching = I915_CACHING_CACHED; | |
3423 | break; | |
3424 | ||
4257d3ba CW |
3425 | case I915_CACHE_WT: |
3426 | args->caching = I915_CACHING_DISPLAY; | |
3427 | break; | |
3428 | ||
651d794f CW |
3429 | default: |
3430 | args->caching = I915_CACHING_NONE; | |
3431 | break; | |
3432 | } | |
fbbd37b3 CW |
3433 | out: |
3434 | rcu_read_unlock(); | |
3435 | return err; | |
e6994aee CW |
3436 | } |
3437 | ||
199adf40 BW |
3438 | int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data, |
3439 | struct drm_file *file) | |
e6994aee | 3440 | { |
9c870d03 | 3441 | struct drm_i915_private *i915 = to_i915(dev); |
199adf40 | 3442 | struct drm_i915_gem_caching *args = data; |
e6994aee CW |
3443 | struct drm_i915_gem_object *obj; |
3444 | enum i915_cache_level level; | |
d65415df | 3445 | int ret = 0; |
e6994aee | 3446 | |
199adf40 BW |
3447 | switch (args->caching) { |
3448 | case I915_CACHING_NONE: | |
e6994aee CW |
3449 | level = I915_CACHE_NONE; |
3450 | break; | |
199adf40 | 3451 | case I915_CACHING_CACHED: |
e5756c10 ID |
3452 | /* |
3453 | * Due to a HW issue on BXT A stepping, GPU stores via a | |
3454 | * snooped mapping may leave stale data in a corresponding CPU | |
3455 | * cacheline, whereas normally such cachelines would get | |
3456 | * invalidated. | |
3457 | */ | |
9c870d03 | 3458 | if (!HAS_LLC(i915) && !HAS_SNOOP(i915)) |
e5756c10 ID |
3459 | return -ENODEV; |
3460 | ||
e6994aee CW |
3461 | level = I915_CACHE_LLC; |
3462 | break; | |
4257d3ba | 3463 | case I915_CACHING_DISPLAY: |
9c870d03 | 3464 | level = HAS_WT(i915) ? I915_CACHE_WT : I915_CACHE_NONE; |
4257d3ba | 3465 | break; |
e6994aee CW |
3466 | default: |
3467 | return -EINVAL; | |
3468 | } | |
3469 | ||
d65415df CW |
3470 | obj = i915_gem_object_lookup(file, args->handle); |
3471 | if (!obj) | |
3472 | return -ENOENT; | |
3473 | ||
3474 | if (obj->cache_level == level) | |
3475 | goto out; | |
3476 | ||
3477 | ret = i915_gem_object_wait(obj, | |
3478 | I915_WAIT_INTERRUPTIBLE, | |
3479 | MAX_SCHEDULE_TIMEOUT, | |
3480 | to_rps_client(file)); | |
3bc2913e | 3481 | if (ret) |
d65415df | 3482 | goto out; |
3bc2913e | 3483 | |
d65415df CW |
3484 | ret = i915_mutex_lock_interruptible(dev); |
3485 | if (ret) | |
3486 | goto out; | |
e6994aee CW |
3487 | |
3488 | ret = i915_gem_object_set_cache_level(obj, level); | |
e6994aee | 3489 | mutex_unlock(&dev->struct_mutex); |
d65415df CW |
3490 | |
3491 | out: | |
3492 | i915_gem_object_put(obj); | |
e6994aee CW |
3493 | return ret; |
3494 | } | |
3495 | ||
b9241ea3 | 3496 | /* |
2da3b9b9 CW |
3497 | * Prepare buffer for display plane (scanout, cursors, etc). |
3498 | * Can be called from an uninterruptible phase (modesetting) and allows | |
3499 | * any flushes to be pipelined (for pageflips). | |
b9241ea3 | 3500 | */ |
058d88c4 | 3501 | struct i915_vma * |
2da3b9b9 CW |
3502 | i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj, |
3503 | u32 alignment, | |
e6617330 | 3504 | const struct i915_ggtt_view *view) |
b9241ea3 | 3505 | { |
058d88c4 | 3506 | struct i915_vma *vma; |
2da3b9b9 | 3507 | u32 old_read_domains, old_write_domain; |
b9241ea3 ZW |
3508 | int ret; |
3509 | ||
4c7d62c6 CW |
3510 | lockdep_assert_held(&obj->base.dev->struct_mutex); |
3511 | ||
cc98b413 CW |
3512 | /* Mark the pin_display early so that we account for the |
3513 | * display coherency whilst setting up the cache domains. | |
3514 | */ | |
8a0c39b1 | 3515 | obj->pin_display++; |
cc98b413 | 3516 | |
a7ef0640 EA |
3517 | /* The display engine is not coherent with the LLC cache on gen6. As |
3518 | * a result, we make sure that the pinning that is about to occur is | |
3519 | * done with uncached PTEs. This is lowest common denominator for all | |
3520 | * chipsets. | |
3521 | * | |
3522 | * However for gen6+, we could do better by using the GFDT bit instead | |
3523 | * of uncaching, which would allow us to flush all the LLC-cached data | |
3524 | * with that bit in the PTE to main memory with just one PIPE_CONTROL. | |
3525 | */ | |
651d794f | 3526 | ret = i915_gem_object_set_cache_level(obj, |
8652744b TU |
3527 | HAS_WT(to_i915(obj->base.dev)) ? |
3528 | I915_CACHE_WT : I915_CACHE_NONE); | |
058d88c4 CW |
3529 | if (ret) { |
3530 | vma = ERR_PTR(ret); | |
cc98b413 | 3531 | goto err_unpin_display; |
058d88c4 | 3532 | } |
a7ef0640 | 3533 | |
2da3b9b9 CW |
3534 | /* As the user may map the buffer once pinned in the display plane |
3535 | * (e.g. libkms for the bootup splash), we have to ensure that we | |
2efb813d CW |
3536 | * always use map_and_fenceable for all scanout buffers. However, |
3537 | * it may simply be too big to fit into mappable, in which case | |
3538 | * put it anyway and hope that userspace can cope (but always first | |
3539 | * try to preserve the existing ABI). | |
2da3b9b9 | 3540 | */ |
2efb813d | 3541 | vma = ERR_PTR(-ENOSPC); |
47a8e3f6 | 3542 | if (!view || view->type == I915_GGTT_VIEW_NORMAL) |
2efb813d CW |
3543 | vma = i915_gem_object_ggtt_pin(obj, view, 0, alignment, |
3544 | PIN_MAPPABLE | PIN_NONBLOCK); | |
767a222e CW |
3545 | if (IS_ERR(vma)) { |
3546 | struct drm_i915_private *i915 = to_i915(obj->base.dev); | |
3547 | unsigned int flags; | |
3548 | ||
3549 | /* Valleyview is definitely limited to scanning out the first | |
3550 | * 512MiB. Lets presume this behaviour was inherited from the | |
3551 | * g4x display engine and that all earlier gen are similarly | |
3552 | * limited. Testing suggests that it is a little more | |
3553 | * complicated than this. For example, Cherryview appears quite | |
3554 | * happy to scanout from anywhere within its global aperture. | |
3555 | */ | |
3556 | flags = 0; | |
3557 | if (HAS_GMCH_DISPLAY(i915)) | |
3558 | flags = PIN_MAPPABLE; | |
3559 | vma = i915_gem_object_ggtt_pin(obj, view, 0, alignment, flags); | |
3560 | } | |
058d88c4 | 3561 | if (IS_ERR(vma)) |
cc98b413 | 3562 | goto err_unpin_display; |
2da3b9b9 | 3563 | |
d8923dcf CW |
3564 | vma->display_alignment = max_t(u64, vma->display_alignment, alignment); |
3565 | ||
a6a7cc4b | 3566 | /* Treat this as an end-of-frame, like intel_user_framebuffer_dirty() */ |
69aeafea | 3567 | if (obj->cache_dirty || obj->base.write_domain == I915_GEM_DOMAIN_CPU) { |
a6a7cc4b CW |
3568 | i915_gem_clflush_object(obj, true); |
3569 | intel_fb_obj_flush(obj, false, ORIGIN_DIRTYFB); | |
3570 | } | |
b118c1e3 | 3571 | |
2da3b9b9 | 3572 | old_write_domain = obj->base.write_domain; |
05394f39 | 3573 | old_read_domains = obj->base.read_domains; |
2da3b9b9 CW |
3574 | |
3575 | /* It should now be out of any other write domains, and we can update | |
3576 | * the domain values for our changes. | |
3577 | */ | |
e5f1d962 | 3578 | obj->base.write_domain = 0; |
05394f39 | 3579 | obj->base.read_domains |= I915_GEM_DOMAIN_GTT; |
b9241ea3 ZW |
3580 | |
3581 | trace_i915_gem_object_change_domain(obj, | |
3582 | old_read_domains, | |
2da3b9b9 | 3583 | old_write_domain); |
b9241ea3 | 3584 | |
058d88c4 | 3585 | return vma; |
cc98b413 CW |
3586 | |
3587 | err_unpin_display: | |
8a0c39b1 | 3588 | obj->pin_display--; |
058d88c4 | 3589 | return vma; |
cc98b413 CW |
3590 | } |
3591 | ||
3592 | void | |
058d88c4 | 3593 | i915_gem_object_unpin_from_display_plane(struct i915_vma *vma) |
cc98b413 | 3594 | { |
49d73912 | 3595 | lockdep_assert_held(&vma->vm->i915->drm.struct_mutex); |
4c7d62c6 | 3596 | |
058d88c4 | 3597 | if (WARN_ON(vma->obj->pin_display == 0)) |
8a0c39b1 TU |
3598 | return; |
3599 | ||
d8923dcf | 3600 | if (--vma->obj->pin_display == 0) |
f51455d4 | 3601 | vma->display_alignment = I915_GTT_MIN_ALIGNMENT; |
e6617330 | 3602 | |
383d5823 | 3603 | /* Bump the LRU to try and avoid premature eviction whilst flipping */ |
befedbb7 | 3604 | i915_gem_object_bump_inactive_ggtt(vma->obj); |
383d5823 | 3605 | |
058d88c4 | 3606 | i915_vma_unpin(vma); |
b9241ea3 ZW |
3607 | } |
3608 | ||
e47c68e9 EA |
3609 | /** |
3610 | * Moves a single object to the CPU read, and possibly write domain. | |
14bb2c11 TU |
3611 | * @obj: object to act on |
3612 | * @write: requesting write or read-only access | |
e47c68e9 EA |
3613 | * |
3614 | * This function returns when the move is complete, including waiting on | |
3615 | * flushes to occur. | |
3616 | */ | |
dabdfe02 | 3617 | int |
919926ae | 3618 | i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write) |
e47c68e9 | 3619 | { |
1c5d22f7 | 3620 | uint32_t old_write_domain, old_read_domains; |
e47c68e9 EA |
3621 | int ret; |
3622 | ||
e95433c7 | 3623 | lockdep_assert_held(&obj->base.dev->struct_mutex); |
4c7d62c6 | 3624 | |
e95433c7 CW |
3625 | ret = i915_gem_object_wait(obj, |
3626 | I915_WAIT_INTERRUPTIBLE | | |
3627 | I915_WAIT_LOCKED | | |
3628 | (write ? I915_WAIT_ALL : 0), | |
3629 | MAX_SCHEDULE_TIMEOUT, | |
3630 | NULL); | |
88241785 CW |
3631 | if (ret) |
3632 | return ret; | |
3633 | ||
c13d87ea CW |
3634 | if (obj->base.write_domain == I915_GEM_DOMAIN_CPU) |
3635 | return 0; | |
3636 | ||
e47c68e9 | 3637 | i915_gem_object_flush_gtt_write_domain(obj); |
2ef7eeaa | 3638 | |
05394f39 CW |
3639 | old_write_domain = obj->base.write_domain; |
3640 | old_read_domains = obj->base.read_domains; | |
1c5d22f7 | 3641 | |
e47c68e9 | 3642 | /* Flush the CPU cache if it's still invalid. */ |
05394f39 | 3643 | if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) { |
2c22569b | 3644 | i915_gem_clflush_object(obj, false); |
2ef7eeaa | 3645 | |
05394f39 | 3646 | obj->base.read_domains |= I915_GEM_DOMAIN_CPU; |
2ef7eeaa EA |
3647 | } |
3648 | ||
3649 | /* It should now be out of any other write domains, and we can update | |
3650 | * the domain values for our changes. | |
3651 | */ | |
40e62d5d | 3652 | GEM_BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) != 0); |
e47c68e9 EA |
3653 | |
3654 | /* If we're writing through the CPU, then the GPU read domains will | |
3655 | * need to be invalidated at next use. | |
3656 | */ | |
3657 | if (write) { | |
05394f39 CW |
3658 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; |
3659 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; | |
e47c68e9 | 3660 | } |
2ef7eeaa | 3661 | |
1c5d22f7 CW |
3662 | trace_i915_gem_object_change_domain(obj, |
3663 | old_read_domains, | |
3664 | old_write_domain); | |
3665 | ||
2ef7eeaa EA |
3666 | return 0; |
3667 | } | |
3668 | ||
673a394b EA |
3669 | /* Throttle our rendering by waiting until the ring has completed our requests |
3670 | * emitted over 20 msec ago. | |
3671 | * | |
b962442e EA |
3672 | * Note that if we were to use the current jiffies each time around the loop, |
3673 | * we wouldn't escape the function with any frames outstanding if the time to | |
3674 | * render a frame was over 20ms. | |
3675 | * | |
673a394b EA |
3676 | * This should get us reasonable parallelism between CPU and GPU but also |
3677 | * relatively low latency when blocking on a particular request to finish. | |
3678 | */ | |
40a5f0de | 3679 | static int |
f787a5f5 | 3680 | i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file) |
40a5f0de | 3681 | { |
fac5e23e | 3682 | struct drm_i915_private *dev_priv = to_i915(dev); |
f787a5f5 | 3683 | struct drm_i915_file_private *file_priv = file->driver_priv; |
d0bc54f2 | 3684 | unsigned long recent_enough = jiffies - DRM_I915_THROTTLE_JIFFIES; |
54fb2411 | 3685 | struct drm_i915_gem_request *request, *target = NULL; |
e95433c7 | 3686 | long ret; |
93533c29 | 3687 | |
f4457ae7 CW |
3688 | /* ABI: return -EIO if already wedged */ |
3689 | if (i915_terminally_wedged(&dev_priv->gpu_error)) | |
3690 | return -EIO; | |
e110e8d6 | 3691 | |
1c25595f | 3692 | spin_lock(&file_priv->mm.lock); |
f787a5f5 | 3693 | list_for_each_entry(request, &file_priv->mm.request_list, client_list) { |
b962442e EA |
3694 | if (time_after_eq(request->emitted_jiffies, recent_enough)) |
3695 | break; | |
40a5f0de | 3696 | |
fcfa423c JH |
3697 | /* |
3698 | * Note that the request might not have been submitted yet. | |
3699 | * In which case emitted_jiffies will be zero. | |
3700 | */ | |
3701 | if (!request->emitted_jiffies) | |
3702 | continue; | |
3703 | ||
54fb2411 | 3704 | target = request; |
b962442e | 3705 | } |
ff865885 | 3706 | if (target) |
e8a261ea | 3707 | i915_gem_request_get(target); |
1c25595f | 3708 | spin_unlock(&file_priv->mm.lock); |
40a5f0de | 3709 | |
54fb2411 | 3710 | if (target == NULL) |
f787a5f5 | 3711 | return 0; |
2bc43b5c | 3712 | |
e95433c7 CW |
3713 | ret = i915_wait_request(target, |
3714 | I915_WAIT_INTERRUPTIBLE, | |
3715 | MAX_SCHEDULE_TIMEOUT); | |
e8a261ea | 3716 | i915_gem_request_put(target); |
ff865885 | 3717 | |
e95433c7 | 3718 | return ret < 0 ? ret : 0; |
40a5f0de EA |
3719 | } |
3720 | ||
058d88c4 | 3721 | struct i915_vma * |
ec7adb6e JL |
3722 | i915_gem_object_ggtt_pin(struct drm_i915_gem_object *obj, |
3723 | const struct i915_ggtt_view *view, | |
91b2db6f | 3724 | u64 size, |
2ffffd0f CW |
3725 | u64 alignment, |
3726 | u64 flags) | |
ec7adb6e | 3727 | { |
ad16d2ed CW |
3728 | struct drm_i915_private *dev_priv = to_i915(obj->base.dev); |
3729 | struct i915_address_space *vm = &dev_priv->ggtt.base; | |
59bfa124 CW |
3730 | struct i915_vma *vma; |
3731 | int ret; | |
72e96d64 | 3732 | |
4c7d62c6 CW |
3733 | lockdep_assert_held(&obj->base.dev->struct_mutex); |
3734 | ||
718659a6 | 3735 | vma = i915_vma_instance(obj, vm, view); |
e0216b76 | 3736 | if (unlikely(IS_ERR(vma))) |
058d88c4 | 3737 | return vma; |
59bfa124 CW |
3738 | |
3739 | if (i915_vma_misplaced(vma, size, alignment, flags)) { | |
3740 | if (flags & PIN_NONBLOCK && | |
3741 | (i915_vma_is_pinned(vma) || i915_vma_is_active(vma))) | |
058d88c4 | 3742 | return ERR_PTR(-ENOSPC); |
59bfa124 | 3743 | |
ad16d2ed | 3744 | if (flags & PIN_MAPPABLE) { |
ad16d2ed CW |
3745 | /* If the required space is larger than the available |
3746 | * aperture, we will not able to find a slot for the | |
3747 | * object and unbinding the object now will be in | |
3748 | * vain. Worse, doing so may cause us to ping-pong | |
3749 | * the object in and out of the Global GTT and | |
3750 | * waste a lot of cycles under the mutex. | |
3751 | */ | |
944397f0 | 3752 | if (vma->fence_size > dev_priv->ggtt.mappable_end) |
ad16d2ed CW |
3753 | return ERR_PTR(-E2BIG); |
3754 | ||
3755 | /* If NONBLOCK is set the caller is optimistically | |
3756 | * trying to cache the full object within the mappable | |
3757 | * aperture, and *must* have a fallback in place for | |
3758 | * situations where we cannot bind the object. We | |
3759 | * can be a little more lax here and use the fallback | |
3760 | * more often to avoid costly migrations of ourselves | |
3761 | * and other objects within the aperture. | |
3762 | * | |
3763 | * Half-the-aperture is used as a simple heuristic. | |
3764 | * More interesting would to do search for a free | |
3765 | * block prior to making the commitment to unbind. | |
3766 | * That caters for the self-harm case, and with a | |
3767 | * little more heuristics (e.g. NOFAULT, NOEVICT) | |
3768 | * we could try to minimise harm to others. | |
3769 | */ | |
3770 | if (flags & PIN_NONBLOCK && | |
944397f0 | 3771 | vma->fence_size > dev_priv->ggtt.mappable_end / 2) |
ad16d2ed CW |
3772 | return ERR_PTR(-ENOSPC); |
3773 | } | |
3774 | ||
59bfa124 CW |
3775 | WARN(i915_vma_is_pinned(vma), |
3776 | "bo is already pinned in ggtt with incorrect alignment:" | |
05a20d09 CW |
3777 | " offset=%08x, req.alignment=%llx," |
3778 | " req.map_and_fenceable=%d, vma->map_and_fenceable=%d\n", | |
3779 | i915_ggtt_offset(vma), alignment, | |
59bfa124 | 3780 | !!(flags & PIN_MAPPABLE), |
05a20d09 | 3781 | i915_vma_is_map_and_fenceable(vma)); |
59bfa124 CW |
3782 | ret = i915_vma_unbind(vma); |
3783 | if (ret) | |
058d88c4 | 3784 | return ERR_PTR(ret); |
59bfa124 CW |
3785 | } |
3786 | ||
058d88c4 CW |
3787 | ret = i915_vma_pin(vma, size, alignment, flags | PIN_GLOBAL); |
3788 | if (ret) | |
3789 | return ERR_PTR(ret); | |
ec7adb6e | 3790 | |
058d88c4 | 3791 | return vma; |
673a394b EA |
3792 | } |
3793 | ||
edf6b76f | 3794 | static __always_inline unsigned int __busy_read_flag(unsigned int id) |
3fdc13c7 CW |
3795 | { |
3796 | /* Note that we could alias engines in the execbuf API, but | |
3797 | * that would be very unwise as it prevents userspace from | |
3798 | * fine control over engine selection. Ahem. | |
3799 | * | |
3800 | * This should be something like EXEC_MAX_ENGINE instead of | |
3801 | * I915_NUM_ENGINES. | |
3802 | */ | |
3803 | BUILD_BUG_ON(I915_NUM_ENGINES > 16); | |
3804 | return 0x10000 << id; | |
3805 | } | |
3806 | ||
3807 | static __always_inline unsigned int __busy_write_id(unsigned int id) | |
3808 | { | |
70cb472c CW |
3809 | /* The uABI guarantees an active writer is also amongst the read |
3810 | * engines. This would be true if we accessed the activity tracking | |
3811 | * under the lock, but as we perform the lookup of the object and | |
3812 | * its activity locklessly we can not guarantee that the last_write | |
3813 | * being active implies that we have set the same engine flag from | |
3814 | * last_read - hence we always set both read and write busy for | |
3815 | * last_write. | |
3816 | */ | |
3817 | return id | __busy_read_flag(id); | |
3fdc13c7 CW |
3818 | } |
3819 | ||
edf6b76f | 3820 | static __always_inline unsigned int |
d07f0e59 | 3821 | __busy_set_if_active(const struct dma_fence *fence, |
3fdc13c7 CW |
3822 | unsigned int (*flag)(unsigned int id)) |
3823 | { | |
d07f0e59 | 3824 | struct drm_i915_gem_request *rq; |
3fdc13c7 | 3825 | |
d07f0e59 CW |
3826 | /* We have to check the current hw status of the fence as the uABI |
3827 | * guarantees forward progress. We could rely on the idle worker | |
3828 | * to eventually flush us, but to minimise latency just ask the | |
3829 | * hardware. | |
1255501d | 3830 | * |
d07f0e59 | 3831 | * Note we only report on the status of native fences. |
1255501d | 3832 | */ |
d07f0e59 CW |
3833 | if (!dma_fence_is_i915(fence)) |
3834 | return 0; | |
3835 | ||
3836 | /* opencode to_request() in order to avoid const warnings */ | |
3837 | rq = container_of(fence, struct drm_i915_gem_request, fence); | |
3838 | if (i915_gem_request_completed(rq)) | |
3839 | return 0; | |
3840 | ||
3841 | return flag(rq->engine->exec_id); | |
3fdc13c7 CW |
3842 | } |
3843 | ||
edf6b76f | 3844 | static __always_inline unsigned int |
d07f0e59 | 3845 | busy_check_reader(const struct dma_fence *fence) |
3fdc13c7 | 3846 | { |
d07f0e59 | 3847 | return __busy_set_if_active(fence, __busy_read_flag); |
3fdc13c7 CW |
3848 | } |
3849 | ||
edf6b76f | 3850 | static __always_inline unsigned int |
d07f0e59 | 3851 | busy_check_writer(const struct dma_fence *fence) |
3fdc13c7 | 3852 | { |
d07f0e59 CW |
3853 | if (!fence) |
3854 | return 0; | |
3855 | ||
3856 | return __busy_set_if_active(fence, __busy_write_id); | |
3fdc13c7 CW |
3857 | } |
3858 | ||
673a394b EA |
3859 | int |
3860 | i915_gem_busy_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 3861 | struct drm_file *file) |
673a394b EA |
3862 | { |
3863 | struct drm_i915_gem_busy *args = data; | |
05394f39 | 3864 | struct drm_i915_gem_object *obj; |
d07f0e59 CW |
3865 | struct reservation_object_list *list; |
3866 | unsigned int seq; | |
fbbd37b3 | 3867 | int err; |
673a394b | 3868 | |
d07f0e59 | 3869 | err = -ENOENT; |
fbbd37b3 CW |
3870 | rcu_read_lock(); |
3871 | obj = i915_gem_object_lookup_rcu(file, args->handle); | |
d07f0e59 | 3872 | if (!obj) |
fbbd37b3 | 3873 | goto out; |
d1b851fc | 3874 | |
d07f0e59 CW |
3875 | /* A discrepancy here is that we do not report the status of |
3876 | * non-i915 fences, i.e. even though we may report the object as idle, | |
3877 | * a call to set-domain may still stall waiting for foreign rendering. | |
3878 | * This also means that wait-ioctl may report an object as busy, | |
3879 | * where busy-ioctl considers it idle. | |
3880 | * | |
3881 | * We trade the ability to warn of foreign fences to report on which | |
3882 | * i915 engines are active for the object. | |
3883 | * | |
3884 | * Alternatively, we can trade that extra information on read/write | |
3885 | * activity with | |
3886 | * args->busy = | |
3887 | * !reservation_object_test_signaled_rcu(obj->resv, true); | |
3888 | * to report the overall busyness. This is what the wait-ioctl does. | |
3889 | * | |
3890 | */ | |
3891 | retry: | |
3892 | seq = raw_read_seqcount(&obj->resv->seq); | |
426960be | 3893 | |
d07f0e59 CW |
3894 | /* Translate the exclusive fence to the READ *and* WRITE engine */ |
3895 | args->busy = busy_check_writer(rcu_dereference(obj->resv->fence_excl)); | |
3fdc13c7 | 3896 | |
d07f0e59 CW |
3897 | /* Translate shared fences to READ set of engines */ |
3898 | list = rcu_dereference(obj->resv->fence); | |
3899 | if (list) { | |
3900 | unsigned int shared_count = list->shared_count, i; | |
3fdc13c7 | 3901 | |
d07f0e59 CW |
3902 | for (i = 0; i < shared_count; ++i) { |
3903 | struct dma_fence *fence = | |
3904 | rcu_dereference(list->shared[i]); | |
3905 | ||
3906 | args->busy |= busy_check_reader(fence); | |
3907 | } | |
426960be | 3908 | } |
673a394b | 3909 | |
d07f0e59 CW |
3910 | if (args->busy && read_seqcount_retry(&obj->resv->seq, seq)) |
3911 | goto retry; | |
3912 | ||
3913 | err = 0; | |
fbbd37b3 CW |
3914 | out: |
3915 | rcu_read_unlock(); | |
3916 | return err; | |
673a394b EA |
3917 | } |
3918 | ||
3919 | int | |
3920 | i915_gem_throttle_ioctl(struct drm_device *dev, void *data, | |
3921 | struct drm_file *file_priv) | |
3922 | { | |
0206e353 | 3923 | return i915_gem_ring_throttle(dev, file_priv); |
673a394b EA |
3924 | } |
3925 | ||
3ef94daa CW |
3926 | int |
3927 | i915_gem_madvise_ioctl(struct drm_device *dev, void *data, | |
3928 | struct drm_file *file_priv) | |
3929 | { | |
fac5e23e | 3930 | struct drm_i915_private *dev_priv = to_i915(dev); |
3ef94daa | 3931 | struct drm_i915_gem_madvise *args = data; |
05394f39 | 3932 | struct drm_i915_gem_object *obj; |
1233e2db | 3933 | int err; |
3ef94daa CW |
3934 | |
3935 | switch (args->madv) { | |
3936 | case I915_MADV_DONTNEED: | |
3937 | case I915_MADV_WILLNEED: | |
3938 | break; | |
3939 | default: | |
3940 | return -EINVAL; | |
3941 | } | |
3942 | ||
03ac0642 | 3943 | obj = i915_gem_object_lookup(file_priv, args->handle); |
1233e2db CW |
3944 | if (!obj) |
3945 | return -ENOENT; | |
3946 | ||
3947 | err = mutex_lock_interruptible(&obj->mm.lock); | |
3948 | if (err) | |
3949 | goto out; | |
3ef94daa | 3950 | |
a4f5ea64 | 3951 | if (obj->mm.pages && |
3e510a8e | 3952 | i915_gem_object_is_tiled(obj) && |
656bfa3a | 3953 | dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES) { |
bc0629a7 CW |
3954 | if (obj->mm.madv == I915_MADV_WILLNEED) { |
3955 | GEM_BUG_ON(!obj->mm.quirked); | |
a4f5ea64 | 3956 | __i915_gem_object_unpin_pages(obj); |
bc0629a7 CW |
3957 | obj->mm.quirked = false; |
3958 | } | |
3959 | if (args->madv == I915_MADV_WILLNEED) { | |
2c3a3f44 | 3960 | GEM_BUG_ON(obj->mm.quirked); |
a4f5ea64 | 3961 | __i915_gem_object_pin_pages(obj); |
bc0629a7 CW |
3962 | obj->mm.quirked = true; |
3963 | } | |
656bfa3a DV |
3964 | } |
3965 | ||
a4f5ea64 CW |
3966 | if (obj->mm.madv != __I915_MADV_PURGED) |
3967 | obj->mm.madv = args->madv; | |
3ef94daa | 3968 | |
6c085a72 | 3969 | /* if the object is no longer attached, discard its backing storage */ |
a4f5ea64 | 3970 | if (obj->mm.madv == I915_MADV_DONTNEED && !obj->mm.pages) |
2d7ef395 CW |
3971 | i915_gem_object_truncate(obj); |
3972 | ||
a4f5ea64 | 3973 | args->retained = obj->mm.madv != __I915_MADV_PURGED; |
1233e2db | 3974 | mutex_unlock(&obj->mm.lock); |
bb6baf76 | 3975 | |
1233e2db | 3976 | out: |
f8c417cd | 3977 | i915_gem_object_put(obj); |
1233e2db | 3978 | return err; |
3ef94daa CW |
3979 | } |
3980 | ||
5b8c8aec CW |
3981 | static void |
3982 | frontbuffer_retire(struct i915_gem_active *active, | |
3983 | struct drm_i915_gem_request *request) | |
3984 | { | |
3985 | struct drm_i915_gem_object *obj = | |
3986 | container_of(active, typeof(*obj), frontbuffer_write); | |
3987 | ||
3988 | intel_fb_obj_flush(obj, true, ORIGIN_CS); | |
3989 | } | |
3990 | ||
37e680a1 CW |
3991 | void i915_gem_object_init(struct drm_i915_gem_object *obj, |
3992 | const struct drm_i915_gem_object_ops *ops) | |
0327d6ba | 3993 | { |
1233e2db CW |
3994 | mutex_init(&obj->mm.lock); |
3995 | ||
56cea323 | 3996 | INIT_LIST_HEAD(&obj->global_link); |
275f039d | 3997 | INIT_LIST_HEAD(&obj->userfault_link); |
b25cb2f8 | 3998 | INIT_LIST_HEAD(&obj->obj_exec_link); |
2f633156 | 3999 | INIT_LIST_HEAD(&obj->vma_list); |
8d9d5744 | 4000 | INIT_LIST_HEAD(&obj->batch_pool_link); |
0327d6ba | 4001 | |
37e680a1 CW |
4002 | obj->ops = ops; |
4003 | ||
d07f0e59 CW |
4004 | reservation_object_init(&obj->__builtin_resv); |
4005 | obj->resv = &obj->__builtin_resv; | |
4006 | ||
50349247 | 4007 | obj->frontbuffer_ggtt_origin = ORIGIN_GTT; |
5b8c8aec | 4008 | init_request_active(&obj->frontbuffer_write, frontbuffer_retire); |
a4f5ea64 CW |
4009 | |
4010 | obj->mm.madv = I915_MADV_WILLNEED; | |
4011 | INIT_RADIX_TREE(&obj->mm.get_page.radix, GFP_KERNEL | __GFP_NOWARN); | |
4012 | mutex_init(&obj->mm.get_page.lock); | |
0327d6ba | 4013 | |
f19ec8cb | 4014 | i915_gem_info_add_obj(to_i915(obj->base.dev), obj->base.size); |
0327d6ba CW |
4015 | } |
4016 | ||
37e680a1 | 4017 | static const struct drm_i915_gem_object_ops i915_gem_object_ops = { |
3599a91c TU |
4018 | .flags = I915_GEM_OBJECT_HAS_STRUCT_PAGE | |
4019 | I915_GEM_OBJECT_IS_SHRINKABLE, | |
37e680a1 CW |
4020 | .get_pages = i915_gem_object_get_pages_gtt, |
4021 | .put_pages = i915_gem_object_put_pages_gtt, | |
4022 | }; | |
4023 | ||
b4bcbe2a | 4024 | struct drm_i915_gem_object * |
12d79d78 | 4025 | i915_gem_object_create(struct drm_i915_private *dev_priv, u64 size) |
ac52bc56 | 4026 | { |
c397b908 | 4027 | struct drm_i915_gem_object *obj; |
5949eac4 | 4028 | struct address_space *mapping; |
1a240d4d | 4029 | gfp_t mask; |
fe3db79b | 4030 | int ret; |
ac52bc56 | 4031 | |
b4bcbe2a CW |
4032 | /* There is a prevalence of the assumption that we fit the object's |
4033 | * page count inside a 32bit _signed_ variable. Let's document this and | |
4034 | * catch if we ever need to fix it. In the meantime, if you do spot | |
4035 | * such a local variable, please consider fixing! | |
4036 | */ | |
4037 | if (WARN_ON(size >> PAGE_SHIFT > INT_MAX)) | |
4038 | return ERR_PTR(-E2BIG); | |
4039 | ||
4040 | if (overflows_type(size, obj->base.size)) | |
4041 | return ERR_PTR(-E2BIG); | |
4042 | ||
187685cb | 4043 | obj = i915_gem_object_alloc(dev_priv); |
c397b908 | 4044 | if (obj == NULL) |
fe3db79b | 4045 | return ERR_PTR(-ENOMEM); |
673a394b | 4046 | |
12d79d78 | 4047 | ret = drm_gem_object_init(&dev_priv->drm, &obj->base, size); |
fe3db79b CW |
4048 | if (ret) |
4049 | goto fail; | |
673a394b | 4050 | |
bed1ea95 | 4051 | mask = GFP_HIGHUSER | __GFP_RECLAIMABLE; |
c0f86832 | 4052 | if (IS_I965GM(dev_priv) || IS_I965G(dev_priv)) { |
bed1ea95 CW |
4053 | /* 965gm cannot relocate objects above 4GiB. */ |
4054 | mask &= ~__GFP_HIGHMEM; | |
4055 | mask |= __GFP_DMA32; | |
4056 | } | |
4057 | ||
93c76a3d | 4058 | mapping = obj->base.filp->f_mapping; |
bed1ea95 | 4059 | mapping_set_gfp_mask(mapping, mask); |
5949eac4 | 4060 | |
37e680a1 | 4061 | i915_gem_object_init(obj, &i915_gem_object_ops); |
73aa808f | 4062 | |
c397b908 DV |
4063 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; |
4064 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; | |
673a394b | 4065 | |
0031fb96 | 4066 | if (HAS_LLC(dev_priv)) { |
3d29b842 | 4067 | /* On some devices, we can have the GPU use the LLC (the CPU |
a1871112 EA |
4068 | * cache) for about a 10% performance improvement |
4069 | * compared to uncached. Graphics requests other than | |
4070 | * display scanout are coherent with the CPU in | |
4071 | * accessing this cache. This means in this mode we | |
4072 | * don't need to clflush on the CPU side, and on the | |
4073 | * GPU side we only need to flush internal caches to | |
4074 | * get data visible to the CPU. | |
4075 | * | |
4076 | * However, we maintain the display planes as UC, and so | |
4077 | * need to rebind when first used as such. | |
4078 | */ | |
4079 | obj->cache_level = I915_CACHE_LLC; | |
4080 | } else | |
4081 | obj->cache_level = I915_CACHE_NONE; | |
4082 | ||
d861e338 DV |
4083 | trace_i915_gem_object_create(obj); |
4084 | ||
05394f39 | 4085 | return obj; |
fe3db79b CW |
4086 | |
4087 | fail: | |
4088 | i915_gem_object_free(obj); | |
fe3db79b | 4089 | return ERR_PTR(ret); |
c397b908 DV |
4090 | } |
4091 | ||
340fbd8c CW |
4092 | static bool discard_backing_storage(struct drm_i915_gem_object *obj) |
4093 | { | |
4094 | /* If we are the last user of the backing storage (be it shmemfs | |
4095 | * pages or stolen etc), we know that the pages are going to be | |
4096 | * immediately released. In this case, we can then skip copying | |
4097 | * back the contents from the GPU. | |
4098 | */ | |
4099 | ||
a4f5ea64 | 4100 | if (obj->mm.madv != I915_MADV_WILLNEED) |
340fbd8c CW |
4101 | return false; |
4102 | ||
4103 | if (obj->base.filp == NULL) | |
4104 | return true; | |
4105 | ||
4106 | /* At first glance, this looks racy, but then again so would be | |
4107 | * userspace racing mmap against close. However, the first external | |
4108 | * reference to the filp can only be obtained through the | |
4109 | * i915_gem_mmap_ioctl() which safeguards us against the user | |
4110 | * acquiring such a reference whilst we are in the middle of | |
4111 | * freeing the object. | |
4112 | */ | |
4113 | return atomic_long_read(&obj->base.filp->f_count) == 1; | |
4114 | } | |
4115 | ||
fbbd37b3 CW |
4116 | static void __i915_gem_free_objects(struct drm_i915_private *i915, |
4117 | struct llist_node *freed) | |
673a394b | 4118 | { |
fbbd37b3 | 4119 | struct drm_i915_gem_object *obj, *on; |
673a394b | 4120 | |
fbbd37b3 CW |
4121 | mutex_lock(&i915->drm.struct_mutex); |
4122 | intel_runtime_pm_get(i915); | |
4123 | llist_for_each_entry(obj, freed, freed) { | |
4124 | struct i915_vma *vma, *vn; | |
4125 | ||
4126 | trace_i915_gem_object_destroy(obj); | |
4127 | ||
4128 | GEM_BUG_ON(i915_gem_object_is_active(obj)); | |
4129 | list_for_each_entry_safe(vma, vn, | |
4130 | &obj->vma_list, obj_link) { | |
4131 | GEM_BUG_ON(!i915_vma_is_ggtt(vma)); | |
4132 | GEM_BUG_ON(i915_vma_is_active(vma)); | |
4133 | vma->flags &= ~I915_VMA_PIN_MASK; | |
4134 | i915_vma_close(vma); | |
4135 | } | |
db6c2b41 CW |
4136 | GEM_BUG_ON(!list_empty(&obj->vma_list)); |
4137 | GEM_BUG_ON(!RB_EMPTY_ROOT(&obj->vma_tree)); | |
fbbd37b3 | 4138 | |
56cea323 | 4139 | list_del(&obj->global_link); |
fbbd37b3 CW |
4140 | } |
4141 | intel_runtime_pm_put(i915); | |
4142 | mutex_unlock(&i915->drm.struct_mutex); | |
4143 | ||
4144 | llist_for_each_entry_safe(obj, on, freed, freed) { | |
4145 | GEM_BUG_ON(obj->bind_count); | |
4146 | GEM_BUG_ON(atomic_read(&obj->frontbuffer_bits)); | |
4147 | ||
4148 | if (obj->ops->release) | |
4149 | obj->ops->release(obj); | |
f65c9168 | 4150 | |
fbbd37b3 CW |
4151 | if (WARN_ON(i915_gem_object_has_pinned_pages(obj))) |
4152 | atomic_set(&obj->mm.pages_pin_count, 0); | |
548625ee | 4153 | __i915_gem_object_put_pages(obj, I915_MM_NORMAL); |
fbbd37b3 CW |
4154 | GEM_BUG_ON(obj->mm.pages); |
4155 | ||
4156 | if (obj->base.import_attach) | |
4157 | drm_prime_gem_destroy(&obj->base, NULL); | |
4158 | ||
d07f0e59 | 4159 | reservation_object_fini(&obj->__builtin_resv); |
fbbd37b3 CW |
4160 | drm_gem_object_release(&obj->base); |
4161 | i915_gem_info_remove_obj(i915, obj->base.size); | |
4162 | ||
4163 | kfree(obj->bit_17); | |
4164 | i915_gem_object_free(obj); | |
4165 | } | |
4166 | } | |
4167 | ||
4168 | static void i915_gem_flush_free_objects(struct drm_i915_private *i915) | |
4169 | { | |
4170 | struct llist_node *freed; | |
4171 | ||
4172 | freed = llist_del_all(&i915->mm.free_list); | |
4173 | if (unlikely(freed)) | |
4174 | __i915_gem_free_objects(i915, freed); | |
4175 | } | |
4176 | ||
4177 | static void __i915_gem_free_work(struct work_struct *work) | |
4178 | { | |
4179 | struct drm_i915_private *i915 = | |
4180 | container_of(work, struct drm_i915_private, mm.free_work); | |
4181 | struct llist_node *freed; | |
26e12f89 | 4182 | |
b1f788c6 CW |
4183 | /* All file-owned VMA should have been released by this point through |
4184 | * i915_gem_close_object(), or earlier by i915_gem_context_close(). | |
4185 | * However, the object may also be bound into the global GTT (e.g. | |
4186 | * older GPUs without per-process support, or for direct access through | |
4187 | * the GTT either for the user or for scanout). Those VMA still need to | |
4188 | * unbound now. | |
4189 | */ | |
1488fc08 | 4190 | |
fbbd37b3 CW |
4191 | while ((freed = llist_del_all(&i915->mm.free_list))) |
4192 | __i915_gem_free_objects(i915, freed); | |
4193 | } | |
a071fa00 | 4194 | |
fbbd37b3 CW |
4195 | static void __i915_gem_free_object_rcu(struct rcu_head *head) |
4196 | { | |
4197 | struct drm_i915_gem_object *obj = | |
4198 | container_of(head, typeof(*obj), rcu); | |
4199 | struct drm_i915_private *i915 = to_i915(obj->base.dev); | |
4200 | ||
4201 | /* We can't simply use call_rcu() from i915_gem_free_object() | |
4202 | * as we need to block whilst unbinding, and the call_rcu | |
4203 | * task may be called from softirq context. So we take a | |
4204 | * detour through a worker. | |
4205 | */ | |
4206 | if (llist_add(&obj->freed, &i915->mm.free_list)) | |
4207 | schedule_work(&i915->mm.free_work); | |
4208 | } | |
656bfa3a | 4209 | |
fbbd37b3 CW |
4210 | void i915_gem_free_object(struct drm_gem_object *gem_obj) |
4211 | { | |
4212 | struct drm_i915_gem_object *obj = to_intel_bo(gem_obj); | |
a4f5ea64 | 4213 | |
bc0629a7 CW |
4214 | if (obj->mm.quirked) |
4215 | __i915_gem_object_unpin_pages(obj); | |
4216 | ||
340fbd8c | 4217 | if (discard_backing_storage(obj)) |
a4f5ea64 | 4218 | obj->mm.madv = I915_MADV_DONTNEED; |
de151cf6 | 4219 | |
fbbd37b3 CW |
4220 | /* Before we free the object, make sure any pure RCU-only |
4221 | * read-side critical sections are complete, e.g. | |
4222 | * i915_gem_busy_ioctl(). For the corresponding synchronized | |
4223 | * lookup see i915_gem_object_lookup_rcu(). | |
4224 | */ | |
4225 | call_rcu(&obj->rcu, __i915_gem_free_object_rcu); | |
673a394b EA |
4226 | } |
4227 | ||
f8a7fde4 CW |
4228 | void __i915_gem_object_release_unless_active(struct drm_i915_gem_object *obj) |
4229 | { | |
4230 | lockdep_assert_held(&obj->base.dev->struct_mutex); | |
4231 | ||
4232 | GEM_BUG_ON(i915_gem_object_has_active_reference(obj)); | |
4233 | if (i915_gem_object_is_active(obj)) | |
4234 | i915_gem_object_set_active_reference(obj); | |
4235 | else | |
4236 | i915_gem_object_put(obj); | |
4237 | } | |
4238 | ||
3033acab CW |
4239 | static void assert_kernel_context_is_current(struct drm_i915_private *dev_priv) |
4240 | { | |
4241 | struct intel_engine_cs *engine; | |
4242 | enum intel_engine_id id; | |
4243 | ||
4244 | for_each_engine(engine, dev_priv, id) | |
f131e356 CW |
4245 | GEM_BUG_ON(engine->last_retired_context && |
4246 | !i915_gem_context_is_kernel(engine->last_retired_context)); | |
3033acab CW |
4247 | } |
4248 | ||
24145517 CW |
4249 | void i915_gem_sanitize(struct drm_i915_private *i915) |
4250 | { | |
4251 | /* | |
4252 | * If we inherit context state from the BIOS or earlier occupants | |
4253 | * of the GPU, the GPU may be in an inconsistent state when we | |
4254 | * try to take over. The only way to remove the earlier state | |
4255 | * is by resetting. However, resetting on earlier gen is tricky as | |
4256 | * it may impact the display and we are uncertain about the stability | |
4257 | * of the reset, so we only reset recent machines with logical | |
4258 | * context support (that must be reset to remove any stray contexts). | |
4259 | */ | |
4260 | if (HAS_HW_CONTEXTS(i915)) { | |
4261 | int reset = intel_gpu_reset(i915, ALL_ENGINES); | |
4262 | WARN_ON(reset && reset != -ENODEV); | |
4263 | } | |
4264 | } | |
4265 | ||
bf9e8429 | 4266 | int i915_gem_suspend(struct drm_i915_private *dev_priv) |
29105ccc | 4267 | { |
bf9e8429 | 4268 | struct drm_device *dev = &dev_priv->drm; |
dcff85c8 | 4269 | int ret; |
28dfe52a | 4270 | |
54b4f68f CW |
4271 | intel_suspend_gt_powersave(dev_priv); |
4272 | ||
45c5f202 | 4273 | mutex_lock(&dev->struct_mutex); |
5ab57c70 CW |
4274 | |
4275 | /* We have to flush all the executing contexts to main memory so | |
4276 | * that they can saved in the hibernation image. To ensure the last | |
4277 | * context image is coherent, we have to switch away from it. That | |
4278 | * leaves the dev_priv->kernel_context still active when | |
4279 | * we actually suspend, and its image in memory may not match the GPU | |
4280 | * state. Fortunately, the kernel_context is disposable and we do | |
4281 | * not rely on its state. | |
4282 | */ | |
4283 | ret = i915_gem_switch_to_kernel_context(dev_priv); | |
4284 | if (ret) | |
4285 | goto err; | |
4286 | ||
22dd3bb9 CW |
4287 | ret = i915_gem_wait_for_idle(dev_priv, |
4288 | I915_WAIT_INTERRUPTIBLE | | |
4289 | I915_WAIT_LOCKED); | |
f7403347 | 4290 | if (ret) |
45c5f202 | 4291 | goto err; |
f7403347 | 4292 | |
c033666a | 4293 | i915_gem_retire_requests(dev_priv); |
28176ef4 | 4294 | GEM_BUG_ON(dev_priv->gt.active_requests); |
673a394b | 4295 | |
3033acab | 4296 | assert_kernel_context_is_current(dev_priv); |
b2e862d0 | 4297 | i915_gem_context_lost(dev_priv); |
45c5f202 CW |
4298 | mutex_unlock(&dev->struct_mutex); |
4299 | ||
737b1506 | 4300 | cancel_delayed_work_sync(&dev_priv->gpu_error.hangcheck_work); |
67d97da3 | 4301 | cancel_delayed_work_sync(&dev_priv->gt.retire_work); |
bdeb9785 CW |
4302 | |
4303 | /* As the idle_work is rearming if it detects a race, play safe and | |
4304 | * repeat the flush until it is definitely idle. | |
4305 | */ | |
4306 | while (flush_delayed_work(&dev_priv->gt.idle_work)) | |
4307 | ; | |
4308 | ||
4309 | i915_gem_drain_freed_objects(dev_priv); | |
29105ccc | 4310 | |
bdcf120b CW |
4311 | /* Assert that we sucessfully flushed all the work and |
4312 | * reset the GPU back to its idle, low power state. | |
4313 | */ | |
67d97da3 | 4314 | WARN_ON(dev_priv->gt.awake); |
31ab49ab | 4315 | WARN_ON(!intel_execlists_idle(dev_priv)); |
bdcf120b | 4316 | |
1c777c5d ID |
4317 | /* |
4318 | * Neither the BIOS, ourselves or any other kernel | |
4319 | * expects the system to be in execlists mode on startup, | |
4320 | * so we need to reset the GPU back to legacy mode. And the only | |
4321 | * known way to disable logical contexts is through a GPU reset. | |
4322 | * | |
4323 | * So in order to leave the system in a known default configuration, | |
4324 | * always reset the GPU upon unload and suspend. Afterwards we then | |
4325 | * clean up the GEM state tracking, flushing off the requests and | |
4326 | * leaving the system in a known idle state. | |
4327 | * | |
4328 | * Note that is of the upmost importance that the GPU is idle and | |
4329 | * all stray writes are flushed *before* we dismantle the backing | |
4330 | * storage for the pinned objects. | |
4331 | * | |
4332 | * However, since we are uncertain that resetting the GPU on older | |
4333 | * machines is a good idea, we don't - just in case it leaves the | |
4334 | * machine in an unusable condition. | |
4335 | */ | |
24145517 | 4336 | i915_gem_sanitize(dev_priv); |
1c777c5d | 4337 | |
673a394b | 4338 | return 0; |
45c5f202 CW |
4339 | |
4340 | err: | |
4341 | mutex_unlock(&dev->struct_mutex); | |
4342 | return ret; | |
673a394b EA |
4343 | } |
4344 | ||
bf9e8429 | 4345 | void i915_gem_resume(struct drm_i915_private *dev_priv) |
5ab57c70 | 4346 | { |
bf9e8429 | 4347 | struct drm_device *dev = &dev_priv->drm; |
5ab57c70 | 4348 | |
31ab49ab ID |
4349 | WARN_ON(dev_priv->gt.awake); |
4350 | ||
5ab57c70 | 4351 | mutex_lock(&dev->struct_mutex); |
275a991c | 4352 | i915_gem_restore_gtt_mappings(dev_priv); |
5ab57c70 CW |
4353 | |
4354 | /* As we didn't flush the kernel context before suspend, we cannot | |
4355 | * guarantee that the context image is complete. So let's just reset | |
4356 | * it and start again. | |
4357 | */ | |
821ed7df | 4358 | dev_priv->gt.resume(dev_priv); |
5ab57c70 CW |
4359 | |
4360 | mutex_unlock(&dev->struct_mutex); | |
4361 | } | |
4362 | ||
c6be607a | 4363 | void i915_gem_init_swizzling(struct drm_i915_private *dev_priv) |
f691e2f4 | 4364 | { |
c6be607a | 4365 | if (INTEL_GEN(dev_priv) < 5 || |
f691e2f4 DV |
4366 | dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE) |
4367 | return; | |
4368 | ||
4369 | I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) | | |
4370 | DISP_TILE_SURFACE_SWIZZLING); | |
4371 | ||
5db94019 | 4372 | if (IS_GEN5(dev_priv)) |
11782b02 DV |
4373 | return; |
4374 | ||
f691e2f4 | 4375 | I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_SWZCTL); |
5db94019 | 4376 | if (IS_GEN6(dev_priv)) |
6b26c86d | 4377 | I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB)); |
5db94019 | 4378 | else if (IS_GEN7(dev_priv)) |
6b26c86d | 4379 | I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB)); |
5db94019 | 4380 | else if (IS_GEN8(dev_priv)) |
31a5336e | 4381 | I915_WRITE(GAMTARBMODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_BDW)); |
8782e26c BW |
4382 | else |
4383 | BUG(); | |
f691e2f4 | 4384 | } |
e21af88d | 4385 | |
50a0bc90 | 4386 | static void init_unused_ring(struct drm_i915_private *dev_priv, u32 base) |
81e7f200 | 4387 | { |
81e7f200 VS |
4388 | I915_WRITE(RING_CTL(base), 0); |
4389 | I915_WRITE(RING_HEAD(base), 0); | |
4390 | I915_WRITE(RING_TAIL(base), 0); | |
4391 | I915_WRITE(RING_START(base), 0); | |
4392 | } | |
4393 | ||
50a0bc90 | 4394 | static void init_unused_rings(struct drm_i915_private *dev_priv) |
81e7f200 | 4395 | { |
50a0bc90 TU |
4396 | if (IS_I830(dev_priv)) { |
4397 | init_unused_ring(dev_priv, PRB1_BASE); | |
4398 | init_unused_ring(dev_priv, SRB0_BASE); | |
4399 | init_unused_ring(dev_priv, SRB1_BASE); | |
4400 | init_unused_ring(dev_priv, SRB2_BASE); | |
4401 | init_unused_ring(dev_priv, SRB3_BASE); | |
4402 | } else if (IS_GEN2(dev_priv)) { | |
4403 | init_unused_ring(dev_priv, SRB0_BASE); | |
4404 | init_unused_ring(dev_priv, SRB1_BASE); | |
4405 | } else if (IS_GEN3(dev_priv)) { | |
4406 | init_unused_ring(dev_priv, PRB1_BASE); | |
4407 | init_unused_ring(dev_priv, PRB2_BASE); | |
81e7f200 VS |
4408 | } |
4409 | } | |
4410 | ||
20a8a74a | 4411 | static int __i915_gem_restart_engines(void *data) |
4fc7c971 | 4412 | { |
20a8a74a | 4413 | struct drm_i915_private *i915 = data; |
e2f80391 | 4414 | struct intel_engine_cs *engine; |
3b3f1650 | 4415 | enum intel_engine_id id; |
20a8a74a CW |
4416 | int err; |
4417 | ||
4418 | for_each_engine(engine, i915, id) { | |
4419 | err = engine->init_hw(engine); | |
4420 | if (err) | |
4421 | return err; | |
4422 | } | |
4423 | ||
4424 | return 0; | |
4425 | } | |
4426 | ||
4427 | int i915_gem_init_hw(struct drm_i915_private *dev_priv) | |
4428 | { | |
d200cda6 | 4429 | int ret; |
4fc7c971 | 4430 | |
de867c20 CW |
4431 | dev_priv->gt.last_init_time = ktime_get(); |
4432 | ||
5e4f5189 CW |
4433 | /* Double layer security blanket, see i915_gem_init() */ |
4434 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); | |
4435 | ||
0031fb96 | 4436 | if (HAS_EDRAM(dev_priv) && INTEL_GEN(dev_priv) < 9) |
05e21cc4 | 4437 | I915_WRITE(HSW_IDICR, I915_READ(HSW_IDICR) | IDIHASHMSK(0xf)); |
4fc7c971 | 4438 | |
772c2a51 | 4439 | if (IS_HASWELL(dev_priv)) |
50a0bc90 | 4440 | I915_WRITE(MI_PREDICATE_RESULT_2, IS_HSW_GT3(dev_priv) ? |
0bf21347 | 4441 | LOWER_SLICE_ENABLED : LOWER_SLICE_DISABLED); |
9435373e | 4442 | |
6e266956 | 4443 | if (HAS_PCH_NOP(dev_priv)) { |
fd6b8f43 | 4444 | if (IS_IVYBRIDGE(dev_priv)) { |
6ba844b0 DV |
4445 | u32 temp = I915_READ(GEN7_MSG_CTL); |
4446 | temp &= ~(WAIT_FOR_PCH_FLR_ACK | WAIT_FOR_PCH_RESET_ACK); | |
4447 | I915_WRITE(GEN7_MSG_CTL, temp); | |
c6be607a | 4448 | } else if (INTEL_GEN(dev_priv) >= 7) { |
6ba844b0 DV |
4449 | u32 temp = I915_READ(HSW_NDE_RSTWRN_OPT); |
4450 | temp &= ~RESET_PCH_HANDSHAKE_ENABLE; | |
4451 | I915_WRITE(HSW_NDE_RSTWRN_OPT, temp); | |
4452 | } | |
88a2b2a3 BW |
4453 | } |
4454 | ||
c6be607a | 4455 | i915_gem_init_swizzling(dev_priv); |
4fc7c971 | 4456 | |
d5abdfda DV |
4457 | /* |
4458 | * At least 830 can leave some of the unused rings | |
4459 | * "active" (ie. head != tail) after resume which | |
4460 | * will prevent c3 entry. Makes sure all unused rings | |
4461 | * are totally idle. | |
4462 | */ | |
50a0bc90 | 4463 | init_unused_rings(dev_priv); |
d5abdfda | 4464 | |
ed54c1a1 | 4465 | BUG_ON(!dev_priv->kernel_context); |
90638cc1 | 4466 | |
c6be607a | 4467 | ret = i915_ppgtt_init_hw(dev_priv); |
4ad2fd88 JH |
4468 | if (ret) { |
4469 | DRM_ERROR("PPGTT enable HW failed %d\n", ret); | |
4470 | goto out; | |
4471 | } | |
4472 | ||
4473 | /* Need to do basic initialisation of all rings first: */ | |
20a8a74a CW |
4474 | ret = __i915_gem_restart_engines(dev_priv); |
4475 | if (ret) | |
4476 | goto out; | |
99433931 | 4477 | |
bf9e8429 | 4478 | intel_mocs_init_l3cc_table(dev_priv); |
0ccdacf6 | 4479 | |
33a732f4 | 4480 | /* We can't enable contexts until all firmware is loaded */ |
bf9e8429 | 4481 | ret = intel_guc_setup(dev_priv); |
e556f7c1 DG |
4482 | if (ret) |
4483 | goto out; | |
33a732f4 | 4484 | |
5e4f5189 CW |
4485 | out: |
4486 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); | |
2fa48d8d | 4487 | return ret; |
8187a2b7 ZN |
4488 | } |
4489 | ||
39df9190 CW |
4490 | bool intel_sanitize_semaphores(struct drm_i915_private *dev_priv, int value) |
4491 | { | |
4492 | if (INTEL_INFO(dev_priv)->gen < 6) | |
4493 | return false; | |
4494 | ||
4495 | /* TODO: make semaphores and Execlists play nicely together */ | |
4496 | if (i915.enable_execlists) | |
4497 | return false; | |
4498 | ||
4499 | if (value >= 0) | |
4500 | return value; | |
4501 | ||
4502 | #ifdef CONFIG_INTEL_IOMMU | |
4503 | /* Enable semaphores on SNB when IO remapping is off */ | |
4504 | if (INTEL_INFO(dev_priv)->gen == 6 && intel_iommu_gfx_mapped) | |
4505 | return false; | |
4506 | #endif | |
4507 | ||
4508 | return true; | |
4509 | } | |
4510 | ||
bf9e8429 | 4511 | int i915_gem_init(struct drm_i915_private *dev_priv) |
1070a42b | 4512 | { |
1070a42b CW |
4513 | int ret; |
4514 | ||
bf9e8429 | 4515 | mutex_lock(&dev_priv->drm.struct_mutex); |
d62b4892 | 4516 | |
a83014d3 | 4517 | if (!i915.enable_execlists) { |
821ed7df | 4518 | dev_priv->gt.resume = intel_legacy_submission_resume; |
7e37f889 | 4519 | dev_priv->gt.cleanup_engine = intel_engine_cleanup; |
454afebd | 4520 | } else { |
821ed7df | 4521 | dev_priv->gt.resume = intel_lr_context_resume; |
117897f4 | 4522 | dev_priv->gt.cleanup_engine = intel_logical_ring_cleanup; |
a83014d3 OM |
4523 | } |
4524 | ||
5e4f5189 CW |
4525 | /* This is just a security blanket to placate dragons. |
4526 | * On some systems, we very sporadically observe that the first TLBs | |
4527 | * used by the CS may be stale, despite us poking the TLB reset. If | |
4528 | * we hold the forcewake during initialisation these problems | |
4529 | * just magically go away. | |
4530 | */ | |
4531 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); | |
4532 | ||
72778cb2 | 4533 | i915_gem_init_userptr(dev_priv); |
f6b9d5ca CW |
4534 | |
4535 | ret = i915_gem_init_ggtt(dev_priv); | |
4536 | if (ret) | |
4537 | goto out_unlock; | |
d62b4892 | 4538 | |
bf9e8429 | 4539 | ret = i915_gem_context_init(dev_priv); |
7bcc3777 JN |
4540 | if (ret) |
4541 | goto out_unlock; | |
2fa48d8d | 4542 | |
bf9e8429 | 4543 | ret = intel_engines_init(dev_priv); |
35a57ffb | 4544 | if (ret) |
7bcc3777 | 4545 | goto out_unlock; |
2fa48d8d | 4546 | |
bf9e8429 | 4547 | ret = i915_gem_init_hw(dev_priv); |
60990320 | 4548 | if (ret == -EIO) { |
7e21d648 | 4549 | /* Allow engine initialisation to fail by marking the GPU as |
60990320 CW |
4550 | * wedged. But we only want to do this where the GPU is angry, |
4551 | * for all other failure, such as an allocation failure, bail. | |
4552 | */ | |
4553 | DRM_ERROR("Failed to initialize GPU, declaring it wedged\n"); | |
821ed7df | 4554 | i915_gem_set_wedged(dev_priv); |
60990320 | 4555 | ret = 0; |
1070a42b | 4556 | } |
7bcc3777 JN |
4557 | |
4558 | out_unlock: | |
5e4f5189 | 4559 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); |
bf9e8429 | 4560 | mutex_unlock(&dev_priv->drm.struct_mutex); |
1070a42b | 4561 | |
60990320 | 4562 | return ret; |
1070a42b CW |
4563 | } |
4564 | ||
24145517 CW |
4565 | void i915_gem_init_mmio(struct drm_i915_private *i915) |
4566 | { | |
4567 | i915_gem_sanitize(i915); | |
4568 | } | |
4569 | ||
8187a2b7 | 4570 | void |
cb15d9f8 | 4571 | i915_gem_cleanup_engines(struct drm_i915_private *dev_priv) |
8187a2b7 | 4572 | { |
e2f80391 | 4573 | struct intel_engine_cs *engine; |
3b3f1650 | 4574 | enum intel_engine_id id; |
8187a2b7 | 4575 | |
3b3f1650 | 4576 | for_each_engine(engine, dev_priv, id) |
117897f4 | 4577 | dev_priv->gt.cleanup_engine(engine); |
8187a2b7 ZN |
4578 | } |
4579 | ||
40ae4e16 ID |
4580 | void |
4581 | i915_gem_load_init_fences(struct drm_i915_private *dev_priv) | |
4582 | { | |
49ef5294 | 4583 | int i; |
40ae4e16 ID |
4584 | |
4585 | if (INTEL_INFO(dev_priv)->gen >= 7 && !IS_VALLEYVIEW(dev_priv) && | |
4586 | !IS_CHERRYVIEW(dev_priv)) | |
4587 | dev_priv->num_fence_regs = 32; | |
73f67aa8 JN |
4588 | else if (INTEL_INFO(dev_priv)->gen >= 4 || |
4589 | IS_I945G(dev_priv) || IS_I945GM(dev_priv) || | |
4590 | IS_G33(dev_priv) || IS_PINEVIEW(dev_priv)) | |
40ae4e16 ID |
4591 | dev_priv->num_fence_regs = 16; |
4592 | else | |
4593 | dev_priv->num_fence_regs = 8; | |
4594 | ||
c033666a | 4595 | if (intel_vgpu_active(dev_priv)) |
40ae4e16 ID |
4596 | dev_priv->num_fence_regs = |
4597 | I915_READ(vgtif_reg(avail_rs.fence_num)); | |
4598 | ||
4599 | /* Initialize fence registers to zero */ | |
49ef5294 CW |
4600 | for (i = 0; i < dev_priv->num_fence_regs; i++) { |
4601 | struct drm_i915_fence_reg *fence = &dev_priv->fence_regs[i]; | |
4602 | ||
4603 | fence->i915 = dev_priv; | |
4604 | fence->id = i; | |
4605 | list_add_tail(&fence->link, &dev_priv->mm.fence_list); | |
4606 | } | |
4362f4f6 | 4607 | i915_gem_restore_fences(dev_priv); |
40ae4e16 | 4608 | |
4362f4f6 | 4609 | i915_gem_detect_bit_6_swizzle(dev_priv); |
40ae4e16 ID |
4610 | } |
4611 | ||
73cb9701 | 4612 | int |
cb15d9f8 | 4613 | i915_gem_load_init(struct drm_i915_private *dev_priv) |
673a394b | 4614 | { |
a933568e | 4615 | int err = -ENOMEM; |
42dcedd4 | 4616 | |
a933568e TU |
4617 | dev_priv->objects = KMEM_CACHE(drm_i915_gem_object, SLAB_HWCACHE_ALIGN); |
4618 | if (!dev_priv->objects) | |
73cb9701 | 4619 | goto err_out; |
73cb9701 | 4620 | |
a933568e TU |
4621 | dev_priv->vmas = KMEM_CACHE(i915_vma, SLAB_HWCACHE_ALIGN); |
4622 | if (!dev_priv->vmas) | |
73cb9701 | 4623 | goto err_objects; |
73cb9701 | 4624 | |
a933568e TU |
4625 | dev_priv->requests = KMEM_CACHE(drm_i915_gem_request, |
4626 | SLAB_HWCACHE_ALIGN | | |
4627 | SLAB_RECLAIM_ACCOUNT | | |
4628 | SLAB_DESTROY_BY_RCU); | |
4629 | if (!dev_priv->requests) | |
73cb9701 | 4630 | goto err_vmas; |
73cb9701 | 4631 | |
52e54209 CW |
4632 | dev_priv->dependencies = KMEM_CACHE(i915_dependency, |
4633 | SLAB_HWCACHE_ALIGN | | |
4634 | SLAB_RECLAIM_ACCOUNT); | |
4635 | if (!dev_priv->dependencies) | |
4636 | goto err_requests; | |
4637 | ||
73cb9701 CW |
4638 | mutex_lock(&dev_priv->drm.struct_mutex); |
4639 | INIT_LIST_HEAD(&dev_priv->gt.timelines); | |
bb89485e | 4640 | err = i915_gem_timeline_init__global(dev_priv); |
73cb9701 CW |
4641 | mutex_unlock(&dev_priv->drm.struct_mutex); |
4642 | if (err) | |
52e54209 | 4643 | goto err_dependencies; |
673a394b | 4644 | |
a33afea5 | 4645 | INIT_LIST_HEAD(&dev_priv->context_list); |
fbbd37b3 CW |
4646 | INIT_WORK(&dev_priv->mm.free_work, __i915_gem_free_work); |
4647 | init_llist_head(&dev_priv->mm.free_list); | |
6c085a72 CW |
4648 | INIT_LIST_HEAD(&dev_priv->mm.unbound_list); |
4649 | INIT_LIST_HEAD(&dev_priv->mm.bound_list); | |
a09ba7fa | 4650 | INIT_LIST_HEAD(&dev_priv->mm.fence_list); |
275f039d | 4651 | INIT_LIST_HEAD(&dev_priv->mm.userfault_list); |
67d97da3 | 4652 | INIT_DELAYED_WORK(&dev_priv->gt.retire_work, |
673a394b | 4653 | i915_gem_retire_work_handler); |
67d97da3 | 4654 | INIT_DELAYED_WORK(&dev_priv->gt.idle_work, |
b29c19b6 | 4655 | i915_gem_idle_work_handler); |
1f15b76f | 4656 | init_waitqueue_head(&dev_priv->gpu_error.wait_queue); |
1f83fee0 | 4657 | init_waitqueue_head(&dev_priv->gpu_error.reset_queue); |
31169714 | 4658 | |
72bfa19c CW |
4659 | dev_priv->relative_constants_mode = I915_EXEC_CONSTANTS_REL_GENERAL; |
4660 | ||
6b95a207 | 4661 | init_waitqueue_head(&dev_priv->pending_flip_queue); |
17250b71 | 4662 | |
ce453d81 CW |
4663 | dev_priv->mm.interruptible = true; |
4664 | ||
6f633402 JL |
4665 | atomic_set(&dev_priv->mm.bsd_engine_dispatch_index, 0); |
4666 | ||
b5add959 | 4667 | spin_lock_init(&dev_priv->fb_tracking.lock); |
73cb9701 CW |
4668 | |
4669 | return 0; | |
4670 | ||
52e54209 CW |
4671 | err_dependencies: |
4672 | kmem_cache_destroy(dev_priv->dependencies); | |
73cb9701 CW |
4673 | err_requests: |
4674 | kmem_cache_destroy(dev_priv->requests); | |
4675 | err_vmas: | |
4676 | kmem_cache_destroy(dev_priv->vmas); | |
4677 | err_objects: | |
4678 | kmem_cache_destroy(dev_priv->objects); | |
4679 | err_out: | |
4680 | return err; | |
673a394b | 4681 | } |
71acb5eb | 4682 | |
cb15d9f8 | 4683 | void i915_gem_load_cleanup(struct drm_i915_private *dev_priv) |
d64aa096 | 4684 | { |
c4d4c1c6 | 4685 | i915_gem_drain_freed_objects(dev_priv); |
7d5d59e5 | 4686 | WARN_ON(!llist_empty(&dev_priv->mm.free_list)); |
c4d4c1c6 | 4687 | WARN_ON(dev_priv->mm.object_count); |
7d5d59e5 | 4688 | |
ea84aa77 MA |
4689 | mutex_lock(&dev_priv->drm.struct_mutex); |
4690 | i915_gem_timeline_fini(&dev_priv->gt.global_timeline); | |
4691 | WARN_ON(!list_empty(&dev_priv->gt.timelines)); | |
4692 | mutex_unlock(&dev_priv->drm.struct_mutex); | |
4693 | ||
52e54209 | 4694 | kmem_cache_destroy(dev_priv->dependencies); |
d64aa096 ID |
4695 | kmem_cache_destroy(dev_priv->requests); |
4696 | kmem_cache_destroy(dev_priv->vmas); | |
4697 | kmem_cache_destroy(dev_priv->objects); | |
0eafec6d CW |
4698 | |
4699 | /* And ensure that our DESTROY_BY_RCU slabs are truly destroyed */ | |
4700 | rcu_barrier(); | |
d64aa096 ID |
4701 | } |
4702 | ||
6a800eab CW |
4703 | int i915_gem_freeze(struct drm_i915_private *dev_priv) |
4704 | { | |
6a800eab CW |
4705 | mutex_lock(&dev_priv->drm.struct_mutex); |
4706 | i915_gem_shrink_all(dev_priv); | |
4707 | mutex_unlock(&dev_priv->drm.struct_mutex); | |
4708 | ||
6a800eab CW |
4709 | return 0; |
4710 | } | |
4711 | ||
461fb99c CW |
4712 | int i915_gem_freeze_late(struct drm_i915_private *dev_priv) |
4713 | { | |
4714 | struct drm_i915_gem_object *obj; | |
7aab2d53 CW |
4715 | struct list_head *phases[] = { |
4716 | &dev_priv->mm.unbound_list, | |
4717 | &dev_priv->mm.bound_list, | |
4718 | NULL | |
4719 | }, **p; | |
461fb99c CW |
4720 | |
4721 | /* Called just before we write the hibernation image. | |
4722 | * | |
4723 | * We need to update the domain tracking to reflect that the CPU | |
4724 | * will be accessing all the pages to create and restore from the | |
4725 | * hibernation, and so upon restoration those pages will be in the | |
4726 | * CPU domain. | |
4727 | * | |
4728 | * To make sure the hibernation image contains the latest state, | |
4729 | * we update that state just before writing out the image. | |
7aab2d53 CW |
4730 | * |
4731 | * To try and reduce the hibernation image, we manually shrink | |
4732 | * the objects as well. | |
461fb99c CW |
4733 | */ |
4734 | ||
6a800eab CW |
4735 | mutex_lock(&dev_priv->drm.struct_mutex); |
4736 | i915_gem_shrink(dev_priv, -1UL, I915_SHRINK_UNBOUND); | |
461fb99c | 4737 | |
7aab2d53 | 4738 | for (p = phases; *p; p++) { |
56cea323 | 4739 | list_for_each_entry(obj, *p, global_link) { |
7aab2d53 CW |
4740 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; |
4741 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; | |
4742 | } | |
461fb99c | 4743 | } |
6a800eab | 4744 | mutex_unlock(&dev_priv->drm.struct_mutex); |
461fb99c CW |
4745 | |
4746 | return 0; | |
4747 | } | |
4748 | ||
f787a5f5 | 4749 | void i915_gem_release(struct drm_device *dev, struct drm_file *file) |
b962442e | 4750 | { |
f787a5f5 | 4751 | struct drm_i915_file_private *file_priv = file->driver_priv; |
15f7bbc7 | 4752 | struct drm_i915_gem_request *request; |
b962442e EA |
4753 | |
4754 | /* Clean up our request list when the client is going away, so that | |
4755 | * later retire_requests won't dereference our soon-to-be-gone | |
4756 | * file_priv. | |
4757 | */ | |
1c25595f | 4758 | spin_lock(&file_priv->mm.lock); |
15f7bbc7 | 4759 | list_for_each_entry(request, &file_priv->mm.request_list, client_list) |
f787a5f5 | 4760 | request->file_priv = NULL; |
1c25595f | 4761 | spin_unlock(&file_priv->mm.lock); |
b29c19b6 | 4762 | |
2e1b8730 | 4763 | if (!list_empty(&file_priv->rps.link)) { |
8d3afd7d | 4764 | spin_lock(&to_i915(dev)->rps.client_lock); |
2e1b8730 | 4765 | list_del(&file_priv->rps.link); |
8d3afd7d | 4766 | spin_unlock(&to_i915(dev)->rps.client_lock); |
1854d5ca | 4767 | } |
b29c19b6 CW |
4768 | } |
4769 | ||
4770 | int i915_gem_open(struct drm_device *dev, struct drm_file *file) | |
4771 | { | |
4772 | struct drm_i915_file_private *file_priv; | |
e422b888 | 4773 | int ret; |
b29c19b6 | 4774 | |
c4c29d7b | 4775 | DRM_DEBUG("\n"); |
b29c19b6 CW |
4776 | |
4777 | file_priv = kzalloc(sizeof(*file_priv), GFP_KERNEL); | |
4778 | if (!file_priv) | |
4779 | return -ENOMEM; | |
4780 | ||
4781 | file->driver_priv = file_priv; | |
f19ec8cb | 4782 | file_priv->dev_priv = to_i915(dev); |
ab0e7ff9 | 4783 | file_priv->file = file; |
2e1b8730 | 4784 | INIT_LIST_HEAD(&file_priv->rps.link); |
b29c19b6 CW |
4785 | |
4786 | spin_lock_init(&file_priv->mm.lock); | |
4787 | INIT_LIST_HEAD(&file_priv->mm.request_list); | |
b29c19b6 | 4788 | |
c80ff16e | 4789 | file_priv->bsd_engine = -1; |
de1add36 | 4790 | |
e422b888 BW |
4791 | ret = i915_gem_context_open(dev, file); |
4792 | if (ret) | |
4793 | kfree(file_priv); | |
b29c19b6 | 4794 | |
e422b888 | 4795 | return ret; |
b29c19b6 CW |
4796 | } |
4797 | ||
b680c37a DV |
4798 | /** |
4799 | * i915_gem_track_fb - update frontbuffer tracking | |
d9072a3e GT |
4800 | * @old: current GEM buffer for the frontbuffer slots |
4801 | * @new: new GEM buffer for the frontbuffer slots | |
4802 | * @frontbuffer_bits: bitmask of frontbuffer slots | |
b680c37a DV |
4803 | * |
4804 | * This updates the frontbuffer tracking bits @frontbuffer_bits by clearing them | |
4805 | * from @old and setting them in @new. Both @old and @new can be NULL. | |
4806 | */ | |
a071fa00 DV |
4807 | void i915_gem_track_fb(struct drm_i915_gem_object *old, |
4808 | struct drm_i915_gem_object *new, | |
4809 | unsigned frontbuffer_bits) | |
4810 | { | |
faf5bf0a CW |
4811 | /* Control of individual bits within the mask are guarded by |
4812 | * the owning plane->mutex, i.e. we can never see concurrent | |
4813 | * manipulation of individual bits. But since the bitfield as a whole | |
4814 | * is updated using RMW, we need to use atomics in order to update | |
4815 | * the bits. | |
4816 | */ | |
4817 | BUILD_BUG_ON(INTEL_FRONTBUFFER_BITS_PER_PIPE * I915_MAX_PIPES > | |
4818 | sizeof(atomic_t) * BITS_PER_BYTE); | |
4819 | ||
a071fa00 | 4820 | if (old) { |
faf5bf0a CW |
4821 | WARN_ON(!(atomic_read(&old->frontbuffer_bits) & frontbuffer_bits)); |
4822 | atomic_andnot(frontbuffer_bits, &old->frontbuffer_bits); | |
a071fa00 DV |
4823 | } |
4824 | ||
4825 | if (new) { | |
faf5bf0a CW |
4826 | WARN_ON(atomic_read(&new->frontbuffer_bits) & frontbuffer_bits); |
4827 | atomic_or(frontbuffer_bits, &new->frontbuffer_bits); | |
a071fa00 DV |
4828 | } |
4829 | } | |
4830 | ||
ea70299d DG |
4831 | /* Allocate a new GEM object and fill it with the supplied data */ |
4832 | struct drm_i915_gem_object * | |
12d79d78 | 4833 | i915_gem_object_create_from_data(struct drm_i915_private *dev_priv, |
ea70299d DG |
4834 | const void *data, size_t size) |
4835 | { | |
4836 | struct drm_i915_gem_object *obj; | |
4837 | struct sg_table *sg; | |
4838 | size_t bytes; | |
4839 | int ret; | |
4840 | ||
12d79d78 | 4841 | obj = i915_gem_object_create(dev_priv, round_up(size, PAGE_SIZE)); |
fe3db79b | 4842 | if (IS_ERR(obj)) |
ea70299d DG |
4843 | return obj; |
4844 | ||
4845 | ret = i915_gem_object_set_to_cpu_domain(obj, true); | |
4846 | if (ret) | |
4847 | goto fail; | |
4848 | ||
a4f5ea64 | 4849 | ret = i915_gem_object_pin_pages(obj); |
ea70299d DG |
4850 | if (ret) |
4851 | goto fail; | |
4852 | ||
a4f5ea64 | 4853 | sg = obj->mm.pages; |
ea70299d | 4854 | bytes = sg_copy_from_buffer(sg->sgl, sg->nents, (void *)data, size); |
a4f5ea64 | 4855 | obj->mm.dirty = true; /* Backing store is now out of date */ |
ea70299d DG |
4856 | i915_gem_object_unpin_pages(obj); |
4857 | ||
4858 | if (WARN_ON(bytes != size)) { | |
4859 | DRM_ERROR("Incomplete copy, wrote %zu of %zu", bytes, size); | |
4860 | ret = -EFAULT; | |
4861 | goto fail; | |
4862 | } | |
4863 | ||
4864 | return obj; | |
4865 | ||
4866 | fail: | |
f8c417cd | 4867 | i915_gem_object_put(obj); |
ea70299d DG |
4868 | return ERR_PTR(ret); |
4869 | } | |
96d77634 CW |
4870 | |
4871 | struct scatterlist * | |
4872 | i915_gem_object_get_sg(struct drm_i915_gem_object *obj, | |
4873 | unsigned int n, | |
4874 | unsigned int *offset) | |
4875 | { | |
a4f5ea64 | 4876 | struct i915_gem_object_page_iter *iter = &obj->mm.get_page; |
96d77634 CW |
4877 | struct scatterlist *sg; |
4878 | unsigned int idx, count; | |
4879 | ||
4880 | might_sleep(); | |
4881 | GEM_BUG_ON(n >= obj->base.size >> PAGE_SHIFT); | |
a4f5ea64 | 4882 | GEM_BUG_ON(!i915_gem_object_has_pinned_pages(obj)); |
96d77634 CW |
4883 | |
4884 | /* As we iterate forward through the sg, we record each entry in a | |
4885 | * radixtree for quick repeated (backwards) lookups. If we have seen | |
4886 | * this index previously, we will have an entry for it. | |
4887 | * | |
4888 | * Initial lookup is O(N), but this is amortized to O(1) for | |
4889 | * sequential page access (where each new request is consecutive | |
4890 | * to the previous one). Repeated lookups are O(lg(obj->base.size)), | |
4891 | * i.e. O(1) with a large constant! | |
4892 | */ | |
4893 | if (n < READ_ONCE(iter->sg_idx)) | |
4894 | goto lookup; | |
4895 | ||
4896 | mutex_lock(&iter->lock); | |
4897 | ||
4898 | /* We prefer to reuse the last sg so that repeated lookup of this | |
4899 | * (or the subsequent) sg are fast - comparing against the last | |
4900 | * sg is faster than going through the radixtree. | |
4901 | */ | |
4902 | ||
4903 | sg = iter->sg_pos; | |
4904 | idx = iter->sg_idx; | |
4905 | count = __sg_page_count(sg); | |
4906 | ||
4907 | while (idx + count <= n) { | |
4908 | unsigned long exception, i; | |
4909 | int ret; | |
4910 | ||
4911 | /* If we cannot allocate and insert this entry, or the | |
4912 | * individual pages from this range, cancel updating the | |
4913 | * sg_idx so that on this lookup we are forced to linearly | |
4914 | * scan onwards, but on future lookups we will try the | |
4915 | * insertion again (in which case we need to be careful of | |
4916 | * the error return reporting that we have already inserted | |
4917 | * this index). | |
4918 | */ | |
4919 | ret = radix_tree_insert(&iter->radix, idx, sg); | |
4920 | if (ret && ret != -EEXIST) | |
4921 | goto scan; | |
4922 | ||
4923 | exception = | |
4924 | RADIX_TREE_EXCEPTIONAL_ENTRY | | |
4925 | idx << RADIX_TREE_EXCEPTIONAL_SHIFT; | |
4926 | for (i = 1; i < count; i++) { | |
4927 | ret = radix_tree_insert(&iter->radix, idx + i, | |
4928 | (void *)exception); | |
4929 | if (ret && ret != -EEXIST) | |
4930 | goto scan; | |
4931 | } | |
4932 | ||
4933 | idx += count; | |
4934 | sg = ____sg_next(sg); | |
4935 | count = __sg_page_count(sg); | |
4936 | } | |
4937 | ||
4938 | scan: | |
4939 | iter->sg_pos = sg; | |
4940 | iter->sg_idx = idx; | |
4941 | ||
4942 | mutex_unlock(&iter->lock); | |
4943 | ||
4944 | if (unlikely(n < idx)) /* insertion completed by another thread */ | |
4945 | goto lookup; | |
4946 | ||
4947 | /* In case we failed to insert the entry into the radixtree, we need | |
4948 | * to look beyond the current sg. | |
4949 | */ | |
4950 | while (idx + count <= n) { | |
4951 | idx += count; | |
4952 | sg = ____sg_next(sg); | |
4953 | count = __sg_page_count(sg); | |
4954 | } | |
4955 | ||
4956 | *offset = n - idx; | |
4957 | return sg; | |
4958 | ||
4959 | lookup: | |
4960 | rcu_read_lock(); | |
4961 | ||
4962 | sg = radix_tree_lookup(&iter->radix, n); | |
4963 | GEM_BUG_ON(!sg); | |
4964 | ||
4965 | /* If this index is in the middle of multi-page sg entry, | |
4966 | * the radixtree will contain an exceptional entry that points | |
4967 | * to the start of that range. We will return the pointer to | |
4968 | * the base page and the offset of this page within the | |
4969 | * sg entry's range. | |
4970 | */ | |
4971 | *offset = 0; | |
4972 | if (unlikely(radix_tree_exception(sg))) { | |
4973 | unsigned long base = | |
4974 | (unsigned long)sg >> RADIX_TREE_EXCEPTIONAL_SHIFT; | |
4975 | ||
4976 | sg = radix_tree_lookup(&iter->radix, base); | |
4977 | GEM_BUG_ON(!sg); | |
4978 | ||
4979 | *offset = n - base; | |
4980 | } | |
4981 | ||
4982 | rcu_read_unlock(); | |
4983 | ||
4984 | return sg; | |
4985 | } | |
4986 | ||
4987 | struct page * | |
4988 | i915_gem_object_get_page(struct drm_i915_gem_object *obj, unsigned int n) | |
4989 | { | |
4990 | struct scatterlist *sg; | |
4991 | unsigned int offset; | |
4992 | ||
4993 | GEM_BUG_ON(!i915_gem_object_has_struct_page(obj)); | |
4994 | ||
4995 | sg = i915_gem_object_get_sg(obj, n, &offset); | |
4996 | return nth_page(sg_page(sg), offset); | |
4997 | } | |
4998 | ||
4999 | /* Like i915_gem_object_get_page(), but mark the returned page dirty */ | |
5000 | struct page * | |
5001 | i915_gem_object_get_dirty_page(struct drm_i915_gem_object *obj, | |
5002 | unsigned int n) | |
5003 | { | |
5004 | struct page *page; | |
5005 | ||
5006 | page = i915_gem_object_get_page(obj, n); | |
a4f5ea64 | 5007 | if (!obj->mm.dirty) |
96d77634 CW |
5008 | set_page_dirty(page); |
5009 | ||
5010 | return page; | |
5011 | } | |
5012 | ||
5013 | dma_addr_t | |
5014 | i915_gem_object_get_dma_address(struct drm_i915_gem_object *obj, | |
5015 | unsigned long n) | |
5016 | { | |
5017 | struct scatterlist *sg; | |
5018 | unsigned int offset; | |
5019 | ||
5020 | sg = i915_gem_object_get_sg(obj, n, &offset); | |
5021 | return sg_dma_address(sg) + (offset << PAGE_SHIFT); | |
5022 | } | |
935a2f77 CW |
5023 | |
5024 | #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST) | |
5025 | #include "selftests/scatterlist.c" | |
66d9cb5d | 5026 | #include "selftests/mock_gem_device.c" |
44653988 | 5027 | #include "selftests/huge_gem_object.c" |
8335fd65 | 5028 | #include "selftests/i915_gem_object.c" |
935a2f77 | 5029 | #endif |