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Commit | Line | Data |
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673a394b EA |
1 | /* |
2 | * Copyright © 2008 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | * | |
26 | */ | |
27 | ||
760285e7 | 28 | #include <drm/drmP.h> |
0de23977 | 29 | #include <drm/drm_vma_manager.h> |
760285e7 | 30 | #include <drm/i915_drm.h> |
673a394b | 31 | #include "i915_drv.h" |
1c5d22f7 | 32 | #include "i915_trace.h" |
652c393a | 33 | #include "intel_drv.h" |
5949eac4 | 34 | #include <linux/shmem_fs.h> |
5a0e3ad6 | 35 | #include <linux/slab.h> |
673a394b | 36 | #include <linux/swap.h> |
79e53945 | 37 | #include <linux/pci.h> |
1286ff73 | 38 | #include <linux/dma-buf.h> |
673a394b | 39 | |
05394f39 | 40 | static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj); |
2c22569b CW |
41 | static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj, |
42 | bool force); | |
07fe0b12 | 43 | static __must_check int |
23f54483 BW |
44 | i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj, |
45 | bool readonly); | |
46 | static __must_check int | |
07fe0b12 BW |
47 | i915_gem_object_bind_to_vm(struct drm_i915_gem_object *obj, |
48 | struct i915_address_space *vm, | |
49 | unsigned alignment, | |
50 | bool map_and_fenceable, | |
51 | bool nonblocking); | |
05394f39 CW |
52 | static int i915_gem_phys_pwrite(struct drm_device *dev, |
53 | struct drm_i915_gem_object *obj, | |
71acb5eb | 54 | struct drm_i915_gem_pwrite *args, |
05394f39 | 55 | struct drm_file *file); |
673a394b | 56 | |
61050808 CW |
57 | static void i915_gem_write_fence(struct drm_device *dev, int reg, |
58 | struct drm_i915_gem_object *obj); | |
59 | static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj, | |
60 | struct drm_i915_fence_reg *fence, | |
61 | bool enable); | |
62 | ||
7dc19d5a DC |
63 | static unsigned long i915_gem_inactive_count(struct shrinker *shrinker, |
64 | struct shrink_control *sc); | |
65 | static unsigned long i915_gem_inactive_scan(struct shrinker *shrinker, | |
66 | struct shrink_control *sc); | |
6c085a72 | 67 | static long i915_gem_purge(struct drm_i915_private *dev_priv, long target); |
7dc19d5a | 68 | static long i915_gem_shrink_all(struct drm_i915_private *dev_priv); |
8c59967c | 69 | static void i915_gem_object_truncate(struct drm_i915_gem_object *obj); |
31169714 | 70 | |
c76ce038 CW |
71 | static bool cpu_cache_is_coherent(struct drm_device *dev, |
72 | enum i915_cache_level level) | |
73 | { | |
74 | return HAS_LLC(dev) || level != I915_CACHE_NONE; | |
75 | } | |
76 | ||
2c22569b CW |
77 | static bool cpu_write_needs_clflush(struct drm_i915_gem_object *obj) |
78 | { | |
79 | if (!cpu_cache_is_coherent(obj->base.dev, obj->cache_level)) | |
80 | return true; | |
81 | ||
82 | return obj->pin_display; | |
83 | } | |
84 | ||
61050808 CW |
85 | static inline void i915_gem_object_fence_lost(struct drm_i915_gem_object *obj) |
86 | { | |
87 | if (obj->tiling_mode) | |
88 | i915_gem_release_mmap(obj); | |
89 | ||
90 | /* As we do not have an associated fence register, we will force | |
91 | * a tiling change if we ever need to acquire one. | |
92 | */ | |
5d82e3e6 | 93 | obj->fence_dirty = false; |
61050808 CW |
94 | obj->fence_reg = I915_FENCE_REG_NONE; |
95 | } | |
96 | ||
73aa808f CW |
97 | /* some bookkeeping */ |
98 | static void i915_gem_info_add_obj(struct drm_i915_private *dev_priv, | |
99 | size_t size) | |
100 | { | |
c20e8355 | 101 | spin_lock(&dev_priv->mm.object_stat_lock); |
73aa808f CW |
102 | dev_priv->mm.object_count++; |
103 | dev_priv->mm.object_memory += size; | |
c20e8355 | 104 | spin_unlock(&dev_priv->mm.object_stat_lock); |
73aa808f CW |
105 | } |
106 | ||
107 | static void i915_gem_info_remove_obj(struct drm_i915_private *dev_priv, | |
108 | size_t size) | |
109 | { | |
c20e8355 | 110 | spin_lock(&dev_priv->mm.object_stat_lock); |
73aa808f CW |
111 | dev_priv->mm.object_count--; |
112 | dev_priv->mm.object_memory -= size; | |
c20e8355 | 113 | spin_unlock(&dev_priv->mm.object_stat_lock); |
73aa808f CW |
114 | } |
115 | ||
21dd3734 | 116 | static int |
33196ded | 117 | i915_gem_wait_for_error(struct i915_gpu_error *error) |
30dbf0c0 | 118 | { |
30dbf0c0 CW |
119 | int ret; |
120 | ||
7abb690a DV |
121 | #define EXIT_COND (!i915_reset_in_progress(error) || \ |
122 | i915_terminally_wedged(error)) | |
1f83fee0 | 123 | if (EXIT_COND) |
30dbf0c0 CW |
124 | return 0; |
125 | ||
0a6759c6 DV |
126 | /* |
127 | * Only wait 10 seconds for the gpu reset to complete to avoid hanging | |
128 | * userspace. If it takes that long something really bad is going on and | |
129 | * we should simply try to bail out and fail as gracefully as possible. | |
130 | */ | |
1f83fee0 DV |
131 | ret = wait_event_interruptible_timeout(error->reset_queue, |
132 | EXIT_COND, | |
133 | 10*HZ); | |
0a6759c6 DV |
134 | if (ret == 0) { |
135 | DRM_ERROR("Timed out waiting for the gpu reset to complete\n"); | |
136 | return -EIO; | |
137 | } else if (ret < 0) { | |
30dbf0c0 | 138 | return ret; |
0a6759c6 | 139 | } |
1f83fee0 | 140 | #undef EXIT_COND |
30dbf0c0 | 141 | |
21dd3734 | 142 | return 0; |
30dbf0c0 CW |
143 | } |
144 | ||
54cf91dc | 145 | int i915_mutex_lock_interruptible(struct drm_device *dev) |
76c1dec1 | 146 | { |
33196ded | 147 | struct drm_i915_private *dev_priv = dev->dev_private; |
76c1dec1 CW |
148 | int ret; |
149 | ||
33196ded | 150 | ret = i915_gem_wait_for_error(&dev_priv->gpu_error); |
76c1dec1 CW |
151 | if (ret) |
152 | return ret; | |
153 | ||
154 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
155 | if (ret) | |
156 | return ret; | |
157 | ||
23bc5982 | 158 | WARN_ON(i915_verify_lists(dev)); |
76c1dec1 CW |
159 | return 0; |
160 | } | |
30dbf0c0 | 161 | |
7d1c4804 | 162 | static inline bool |
05394f39 | 163 | i915_gem_object_is_inactive(struct drm_i915_gem_object *obj) |
7d1c4804 | 164 | { |
9843877d | 165 | return i915_gem_obj_bound_any(obj) && !obj->active; |
7d1c4804 CW |
166 | } |
167 | ||
79e53945 JB |
168 | int |
169 | i915_gem_init_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 170 | struct drm_file *file) |
79e53945 | 171 | { |
93d18799 | 172 | struct drm_i915_private *dev_priv = dev->dev_private; |
79e53945 | 173 | struct drm_i915_gem_init *args = data; |
2021746e | 174 | |
7bb6fb8d DV |
175 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
176 | return -ENODEV; | |
177 | ||
2021746e CW |
178 | if (args->gtt_start >= args->gtt_end || |
179 | (args->gtt_end | args->gtt_start) & (PAGE_SIZE - 1)) | |
180 | return -EINVAL; | |
79e53945 | 181 | |
f534bc0b DV |
182 | /* GEM with user mode setting was never supported on ilk and later. */ |
183 | if (INTEL_INFO(dev)->gen >= 5) | |
184 | return -ENODEV; | |
185 | ||
79e53945 | 186 | mutex_lock(&dev->struct_mutex); |
d7e5008f BW |
187 | i915_gem_setup_global_gtt(dev, args->gtt_start, args->gtt_end, |
188 | args->gtt_end); | |
93d18799 | 189 | dev_priv->gtt.mappable_end = args->gtt_end; |
673a394b EA |
190 | mutex_unlock(&dev->struct_mutex); |
191 | ||
2021746e | 192 | return 0; |
673a394b EA |
193 | } |
194 | ||
5a125c3c EA |
195 | int |
196 | i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 197 | struct drm_file *file) |
5a125c3c | 198 | { |
73aa808f | 199 | struct drm_i915_private *dev_priv = dev->dev_private; |
5a125c3c | 200 | struct drm_i915_gem_get_aperture *args = data; |
6299f992 CW |
201 | struct drm_i915_gem_object *obj; |
202 | size_t pinned; | |
5a125c3c | 203 | |
6299f992 | 204 | pinned = 0; |
73aa808f | 205 | mutex_lock(&dev->struct_mutex); |
35c20a60 | 206 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) |
1b50247a | 207 | if (obj->pin_count) |
f343c5f6 | 208 | pinned += i915_gem_obj_ggtt_size(obj); |
73aa808f | 209 | mutex_unlock(&dev->struct_mutex); |
5a125c3c | 210 | |
853ba5d2 | 211 | args->aper_size = dev_priv->gtt.base.total; |
0206e353 | 212 | args->aper_available_size = args->aper_size - pinned; |
6299f992 | 213 | |
5a125c3c EA |
214 | return 0; |
215 | } | |
216 | ||
42dcedd4 CW |
217 | void *i915_gem_object_alloc(struct drm_device *dev) |
218 | { | |
219 | struct drm_i915_private *dev_priv = dev->dev_private; | |
fac15c10 | 220 | return kmem_cache_zalloc(dev_priv->slab, GFP_KERNEL); |
42dcedd4 CW |
221 | } |
222 | ||
223 | void i915_gem_object_free(struct drm_i915_gem_object *obj) | |
224 | { | |
225 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; | |
226 | kmem_cache_free(dev_priv->slab, obj); | |
227 | } | |
228 | ||
ff72145b DA |
229 | static int |
230 | i915_gem_create(struct drm_file *file, | |
231 | struct drm_device *dev, | |
232 | uint64_t size, | |
233 | uint32_t *handle_p) | |
673a394b | 234 | { |
05394f39 | 235 | struct drm_i915_gem_object *obj; |
a1a2d1d3 PP |
236 | int ret; |
237 | u32 handle; | |
673a394b | 238 | |
ff72145b | 239 | size = roundup(size, PAGE_SIZE); |
8ffc0246 CW |
240 | if (size == 0) |
241 | return -EINVAL; | |
673a394b EA |
242 | |
243 | /* Allocate the new object */ | |
ff72145b | 244 | obj = i915_gem_alloc_object(dev, size); |
673a394b EA |
245 | if (obj == NULL) |
246 | return -ENOMEM; | |
247 | ||
05394f39 | 248 | ret = drm_gem_handle_create(file, &obj->base, &handle); |
202f2fef | 249 | /* drop reference from allocate - handle holds it now */ |
d861e338 DV |
250 | drm_gem_object_unreference_unlocked(&obj->base); |
251 | if (ret) | |
252 | return ret; | |
202f2fef | 253 | |
ff72145b | 254 | *handle_p = handle; |
673a394b EA |
255 | return 0; |
256 | } | |
257 | ||
ff72145b DA |
258 | int |
259 | i915_gem_dumb_create(struct drm_file *file, | |
260 | struct drm_device *dev, | |
261 | struct drm_mode_create_dumb *args) | |
262 | { | |
263 | /* have to work out size/pitch and return them */ | |
ed0291fd | 264 | args->pitch = ALIGN(args->width * ((args->bpp + 7) / 8), 64); |
ff72145b DA |
265 | args->size = args->pitch * args->height; |
266 | return i915_gem_create(file, dev, | |
267 | args->size, &args->handle); | |
268 | } | |
269 | ||
ff72145b DA |
270 | /** |
271 | * Creates a new mm object and returns a handle to it. | |
272 | */ | |
273 | int | |
274 | i915_gem_create_ioctl(struct drm_device *dev, void *data, | |
275 | struct drm_file *file) | |
276 | { | |
277 | struct drm_i915_gem_create *args = data; | |
63ed2cb2 | 278 | |
ff72145b DA |
279 | return i915_gem_create(file, dev, |
280 | args->size, &args->handle); | |
281 | } | |
282 | ||
8461d226 DV |
283 | static inline int |
284 | __copy_to_user_swizzled(char __user *cpu_vaddr, | |
285 | const char *gpu_vaddr, int gpu_offset, | |
286 | int length) | |
287 | { | |
288 | int ret, cpu_offset = 0; | |
289 | ||
290 | while (length > 0) { | |
291 | int cacheline_end = ALIGN(gpu_offset + 1, 64); | |
292 | int this_length = min(cacheline_end - gpu_offset, length); | |
293 | int swizzled_gpu_offset = gpu_offset ^ 64; | |
294 | ||
295 | ret = __copy_to_user(cpu_vaddr + cpu_offset, | |
296 | gpu_vaddr + swizzled_gpu_offset, | |
297 | this_length); | |
298 | if (ret) | |
299 | return ret + length; | |
300 | ||
301 | cpu_offset += this_length; | |
302 | gpu_offset += this_length; | |
303 | length -= this_length; | |
304 | } | |
305 | ||
306 | return 0; | |
307 | } | |
308 | ||
8c59967c | 309 | static inline int |
4f0c7cfb BW |
310 | __copy_from_user_swizzled(char *gpu_vaddr, int gpu_offset, |
311 | const char __user *cpu_vaddr, | |
8c59967c DV |
312 | int length) |
313 | { | |
314 | int ret, cpu_offset = 0; | |
315 | ||
316 | while (length > 0) { | |
317 | int cacheline_end = ALIGN(gpu_offset + 1, 64); | |
318 | int this_length = min(cacheline_end - gpu_offset, length); | |
319 | int swizzled_gpu_offset = gpu_offset ^ 64; | |
320 | ||
321 | ret = __copy_from_user(gpu_vaddr + swizzled_gpu_offset, | |
322 | cpu_vaddr + cpu_offset, | |
323 | this_length); | |
324 | if (ret) | |
325 | return ret + length; | |
326 | ||
327 | cpu_offset += this_length; | |
328 | gpu_offset += this_length; | |
329 | length -= this_length; | |
330 | } | |
331 | ||
332 | return 0; | |
333 | } | |
334 | ||
d174bd64 DV |
335 | /* Per-page copy function for the shmem pread fastpath. |
336 | * Flushes invalid cachelines before reading the target if | |
337 | * needs_clflush is set. */ | |
eb01459f | 338 | static int |
d174bd64 DV |
339 | shmem_pread_fast(struct page *page, int shmem_page_offset, int page_length, |
340 | char __user *user_data, | |
341 | bool page_do_bit17_swizzling, bool needs_clflush) | |
342 | { | |
343 | char *vaddr; | |
344 | int ret; | |
345 | ||
e7e58eb5 | 346 | if (unlikely(page_do_bit17_swizzling)) |
d174bd64 DV |
347 | return -EINVAL; |
348 | ||
349 | vaddr = kmap_atomic(page); | |
350 | if (needs_clflush) | |
351 | drm_clflush_virt_range(vaddr + shmem_page_offset, | |
352 | page_length); | |
353 | ret = __copy_to_user_inatomic(user_data, | |
354 | vaddr + shmem_page_offset, | |
355 | page_length); | |
356 | kunmap_atomic(vaddr); | |
357 | ||
f60d7f0c | 358 | return ret ? -EFAULT : 0; |
d174bd64 DV |
359 | } |
360 | ||
23c18c71 DV |
361 | static void |
362 | shmem_clflush_swizzled_range(char *addr, unsigned long length, | |
363 | bool swizzled) | |
364 | { | |
e7e58eb5 | 365 | if (unlikely(swizzled)) { |
23c18c71 DV |
366 | unsigned long start = (unsigned long) addr; |
367 | unsigned long end = (unsigned long) addr + length; | |
368 | ||
369 | /* For swizzling simply ensure that we always flush both | |
370 | * channels. Lame, but simple and it works. Swizzled | |
371 | * pwrite/pread is far from a hotpath - current userspace | |
372 | * doesn't use it at all. */ | |
373 | start = round_down(start, 128); | |
374 | end = round_up(end, 128); | |
375 | ||
376 | drm_clflush_virt_range((void *)start, end - start); | |
377 | } else { | |
378 | drm_clflush_virt_range(addr, length); | |
379 | } | |
380 | ||
381 | } | |
382 | ||
d174bd64 DV |
383 | /* Only difference to the fast-path function is that this can handle bit17 |
384 | * and uses non-atomic copy and kmap functions. */ | |
385 | static int | |
386 | shmem_pread_slow(struct page *page, int shmem_page_offset, int page_length, | |
387 | char __user *user_data, | |
388 | bool page_do_bit17_swizzling, bool needs_clflush) | |
389 | { | |
390 | char *vaddr; | |
391 | int ret; | |
392 | ||
393 | vaddr = kmap(page); | |
394 | if (needs_clflush) | |
23c18c71 DV |
395 | shmem_clflush_swizzled_range(vaddr + shmem_page_offset, |
396 | page_length, | |
397 | page_do_bit17_swizzling); | |
d174bd64 DV |
398 | |
399 | if (page_do_bit17_swizzling) | |
400 | ret = __copy_to_user_swizzled(user_data, | |
401 | vaddr, shmem_page_offset, | |
402 | page_length); | |
403 | else | |
404 | ret = __copy_to_user(user_data, | |
405 | vaddr + shmem_page_offset, | |
406 | page_length); | |
407 | kunmap(page); | |
408 | ||
f60d7f0c | 409 | return ret ? - EFAULT : 0; |
d174bd64 DV |
410 | } |
411 | ||
eb01459f | 412 | static int |
dbf7bff0 DV |
413 | i915_gem_shmem_pread(struct drm_device *dev, |
414 | struct drm_i915_gem_object *obj, | |
415 | struct drm_i915_gem_pread *args, | |
416 | struct drm_file *file) | |
eb01459f | 417 | { |
8461d226 | 418 | char __user *user_data; |
eb01459f | 419 | ssize_t remain; |
8461d226 | 420 | loff_t offset; |
eb2c0c81 | 421 | int shmem_page_offset, page_length, ret = 0; |
8461d226 | 422 | int obj_do_bit17_swizzling, page_do_bit17_swizzling; |
96d79b52 | 423 | int prefaulted = 0; |
8489731c | 424 | int needs_clflush = 0; |
67d5a50c | 425 | struct sg_page_iter sg_iter; |
eb01459f | 426 | |
2bb4629a | 427 | user_data = to_user_ptr(args->data_ptr); |
eb01459f EA |
428 | remain = args->size; |
429 | ||
8461d226 | 430 | obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj); |
eb01459f | 431 | |
8489731c DV |
432 | if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU)) { |
433 | /* If we're not in the cpu read domain, set ourself into the gtt | |
434 | * read domain and manually flush cachelines (if required). This | |
435 | * optimizes for the case when the gpu will dirty the data | |
436 | * anyway again before the next pread happens. */ | |
c76ce038 | 437 | needs_clflush = !cpu_cache_is_coherent(dev, obj->cache_level); |
23f54483 BW |
438 | ret = i915_gem_object_wait_rendering(obj, true); |
439 | if (ret) | |
440 | return ret; | |
8489731c | 441 | } |
eb01459f | 442 | |
f60d7f0c CW |
443 | ret = i915_gem_object_get_pages(obj); |
444 | if (ret) | |
445 | return ret; | |
446 | ||
447 | i915_gem_object_pin_pages(obj); | |
448 | ||
8461d226 | 449 | offset = args->offset; |
eb01459f | 450 | |
67d5a50c ID |
451 | for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, |
452 | offset >> PAGE_SHIFT) { | |
2db76d7c | 453 | struct page *page = sg_page_iter_page(&sg_iter); |
9da3da66 CW |
454 | |
455 | if (remain <= 0) | |
456 | break; | |
457 | ||
eb01459f EA |
458 | /* Operation in this page |
459 | * | |
eb01459f | 460 | * shmem_page_offset = offset within page in shmem file |
eb01459f EA |
461 | * page_length = bytes to copy for this page |
462 | */ | |
c8cbbb8b | 463 | shmem_page_offset = offset_in_page(offset); |
eb01459f EA |
464 | page_length = remain; |
465 | if ((shmem_page_offset + page_length) > PAGE_SIZE) | |
466 | page_length = PAGE_SIZE - shmem_page_offset; | |
eb01459f | 467 | |
8461d226 DV |
468 | page_do_bit17_swizzling = obj_do_bit17_swizzling && |
469 | (page_to_phys(page) & (1 << 17)) != 0; | |
470 | ||
d174bd64 DV |
471 | ret = shmem_pread_fast(page, shmem_page_offset, page_length, |
472 | user_data, page_do_bit17_swizzling, | |
473 | needs_clflush); | |
474 | if (ret == 0) | |
475 | goto next_page; | |
dbf7bff0 | 476 | |
dbf7bff0 DV |
477 | mutex_unlock(&dev->struct_mutex); |
478 | ||
0b74b508 | 479 | if (likely(!i915_prefault_disable) && !prefaulted) { |
f56f821f | 480 | ret = fault_in_multipages_writeable(user_data, remain); |
96d79b52 DV |
481 | /* Userspace is tricking us, but we've already clobbered |
482 | * its pages with the prefault and promised to write the | |
483 | * data up to the first fault. Hence ignore any errors | |
484 | * and just continue. */ | |
485 | (void)ret; | |
486 | prefaulted = 1; | |
487 | } | |
eb01459f | 488 | |
d174bd64 DV |
489 | ret = shmem_pread_slow(page, shmem_page_offset, page_length, |
490 | user_data, page_do_bit17_swizzling, | |
491 | needs_clflush); | |
eb01459f | 492 | |
dbf7bff0 | 493 | mutex_lock(&dev->struct_mutex); |
f60d7f0c | 494 | |
dbf7bff0 | 495 | next_page: |
e5281ccd | 496 | mark_page_accessed(page); |
e5281ccd | 497 | |
f60d7f0c | 498 | if (ret) |
8461d226 | 499 | goto out; |
8461d226 | 500 | |
eb01459f | 501 | remain -= page_length; |
8461d226 | 502 | user_data += page_length; |
eb01459f EA |
503 | offset += page_length; |
504 | } | |
505 | ||
4f27b75d | 506 | out: |
f60d7f0c CW |
507 | i915_gem_object_unpin_pages(obj); |
508 | ||
eb01459f EA |
509 | return ret; |
510 | } | |
511 | ||
673a394b EA |
512 | /** |
513 | * Reads data from the object referenced by handle. | |
514 | * | |
515 | * On error, the contents of *data are undefined. | |
516 | */ | |
517 | int | |
518 | i915_gem_pread_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 519 | struct drm_file *file) |
673a394b EA |
520 | { |
521 | struct drm_i915_gem_pread *args = data; | |
05394f39 | 522 | struct drm_i915_gem_object *obj; |
35b62a89 | 523 | int ret = 0; |
673a394b | 524 | |
51311d0a CW |
525 | if (args->size == 0) |
526 | return 0; | |
527 | ||
528 | if (!access_ok(VERIFY_WRITE, | |
2bb4629a | 529 | to_user_ptr(args->data_ptr), |
51311d0a CW |
530 | args->size)) |
531 | return -EFAULT; | |
532 | ||
4f27b75d | 533 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 534 | if (ret) |
4f27b75d | 535 | return ret; |
673a394b | 536 | |
05394f39 | 537 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 538 | if (&obj->base == NULL) { |
1d7cfea1 CW |
539 | ret = -ENOENT; |
540 | goto unlock; | |
4f27b75d | 541 | } |
673a394b | 542 | |
7dcd2499 | 543 | /* Bounds check source. */ |
05394f39 CW |
544 | if (args->offset > obj->base.size || |
545 | args->size > obj->base.size - args->offset) { | |
ce9d419d | 546 | ret = -EINVAL; |
35b62a89 | 547 | goto out; |
ce9d419d CW |
548 | } |
549 | ||
1286ff73 DV |
550 | /* prime objects have no backing filp to GEM pread/pwrite |
551 | * pages from. | |
552 | */ | |
553 | if (!obj->base.filp) { | |
554 | ret = -EINVAL; | |
555 | goto out; | |
556 | } | |
557 | ||
db53a302 CW |
558 | trace_i915_gem_object_pread(obj, args->offset, args->size); |
559 | ||
dbf7bff0 | 560 | ret = i915_gem_shmem_pread(dev, obj, args, file); |
673a394b | 561 | |
35b62a89 | 562 | out: |
05394f39 | 563 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 564 | unlock: |
4f27b75d | 565 | mutex_unlock(&dev->struct_mutex); |
eb01459f | 566 | return ret; |
673a394b EA |
567 | } |
568 | ||
0839ccb8 KP |
569 | /* This is the fast write path which cannot handle |
570 | * page faults in the source data | |
9b7530cc | 571 | */ |
0839ccb8 KP |
572 | |
573 | static inline int | |
574 | fast_user_write(struct io_mapping *mapping, | |
575 | loff_t page_base, int page_offset, | |
576 | char __user *user_data, | |
577 | int length) | |
9b7530cc | 578 | { |
4f0c7cfb BW |
579 | void __iomem *vaddr_atomic; |
580 | void *vaddr; | |
0839ccb8 | 581 | unsigned long unwritten; |
9b7530cc | 582 | |
3e4d3af5 | 583 | vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base); |
4f0c7cfb BW |
584 | /* We can use the cpu mem copy function because this is X86. */ |
585 | vaddr = (void __force*)vaddr_atomic + page_offset; | |
586 | unwritten = __copy_from_user_inatomic_nocache(vaddr, | |
0839ccb8 | 587 | user_data, length); |
3e4d3af5 | 588 | io_mapping_unmap_atomic(vaddr_atomic); |
fbd5a26d | 589 | return unwritten; |
0839ccb8 KP |
590 | } |
591 | ||
3de09aa3 EA |
592 | /** |
593 | * This is the fast pwrite path, where we copy the data directly from the | |
594 | * user into the GTT, uncached. | |
595 | */ | |
673a394b | 596 | static int |
05394f39 CW |
597 | i915_gem_gtt_pwrite_fast(struct drm_device *dev, |
598 | struct drm_i915_gem_object *obj, | |
3de09aa3 | 599 | struct drm_i915_gem_pwrite *args, |
05394f39 | 600 | struct drm_file *file) |
673a394b | 601 | { |
0839ccb8 | 602 | drm_i915_private_t *dev_priv = dev->dev_private; |
673a394b | 603 | ssize_t remain; |
0839ccb8 | 604 | loff_t offset, page_base; |
673a394b | 605 | char __user *user_data; |
935aaa69 DV |
606 | int page_offset, page_length, ret; |
607 | ||
c37e2204 | 608 | ret = i915_gem_obj_ggtt_pin(obj, 0, true, true); |
935aaa69 DV |
609 | if (ret) |
610 | goto out; | |
611 | ||
612 | ret = i915_gem_object_set_to_gtt_domain(obj, true); | |
613 | if (ret) | |
614 | goto out_unpin; | |
615 | ||
616 | ret = i915_gem_object_put_fence(obj); | |
617 | if (ret) | |
618 | goto out_unpin; | |
673a394b | 619 | |
2bb4629a | 620 | user_data = to_user_ptr(args->data_ptr); |
673a394b | 621 | remain = args->size; |
673a394b | 622 | |
f343c5f6 | 623 | offset = i915_gem_obj_ggtt_offset(obj) + args->offset; |
673a394b EA |
624 | |
625 | while (remain > 0) { | |
626 | /* Operation in this page | |
627 | * | |
0839ccb8 KP |
628 | * page_base = page offset within aperture |
629 | * page_offset = offset within page | |
630 | * page_length = bytes to copy for this page | |
673a394b | 631 | */ |
c8cbbb8b CW |
632 | page_base = offset & PAGE_MASK; |
633 | page_offset = offset_in_page(offset); | |
0839ccb8 KP |
634 | page_length = remain; |
635 | if ((page_offset + remain) > PAGE_SIZE) | |
636 | page_length = PAGE_SIZE - page_offset; | |
637 | ||
0839ccb8 | 638 | /* If we get a fault while copying data, then (presumably) our |
3de09aa3 EA |
639 | * source page isn't available. Return the error and we'll |
640 | * retry in the slow path. | |
0839ccb8 | 641 | */ |
5d4545ae | 642 | if (fast_user_write(dev_priv->gtt.mappable, page_base, |
935aaa69 DV |
643 | page_offset, user_data, page_length)) { |
644 | ret = -EFAULT; | |
645 | goto out_unpin; | |
646 | } | |
673a394b | 647 | |
0839ccb8 KP |
648 | remain -= page_length; |
649 | user_data += page_length; | |
650 | offset += page_length; | |
673a394b | 651 | } |
673a394b | 652 | |
935aaa69 DV |
653 | out_unpin: |
654 | i915_gem_object_unpin(obj); | |
655 | out: | |
3de09aa3 | 656 | return ret; |
673a394b EA |
657 | } |
658 | ||
d174bd64 DV |
659 | /* Per-page copy function for the shmem pwrite fastpath. |
660 | * Flushes invalid cachelines before writing to the target if | |
661 | * needs_clflush_before is set and flushes out any written cachelines after | |
662 | * writing if needs_clflush is set. */ | |
3043c60c | 663 | static int |
d174bd64 DV |
664 | shmem_pwrite_fast(struct page *page, int shmem_page_offset, int page_length, |
665 | char __user *user_data, | |
666 | bool page_do_bit17_swizzling, | |
667 | bool needs_clflush_before, | |
668 | bool needs_clflush_after) | |
673a394b | 669 | { |
d174bd64 | 670 | char *vaddr; |
673a394b | 671 | int ret; |
3de09aa3 | 672 | |
e7e58eb5 | 673 | if (unlikely(page_do_bit17_swizzling)) |
d174bd64 | 674 | return -EINVAL; |
3de09aa3 | 675 | |
d174bd64 DV |
676 | vaddr = kmap_atomic(page); |
677 | if (needs_clflush_before) | |
678 | drm_clflush_virt_range(vaddr + shmem_page_offset, | |
679 | page_length); | |
680 | ret = __copy_from_user_inatomic_nocache(vaddr + shmem_page_offset, | |
681 | user_data, | |
682 | page_length); | |
683 | if (needs_clflush_after) | |
684 | drm_clflush_virt_range(vaddr + shmem_page_offset, | |
685 | page_length); | |
686 | kunmap_atomic(vaddr); | |
3de09aa3 | 687 | |
755d2218 | 688 | return ret ? -EFAULT : 0; |
3de09aa3 EA |
689 | } |
690 | ||
d174bd64 DV |
691 | /* Only difference to the fast-path function is that this can handle bit17 |
692 | * and uses non-atomic copy and kmap functions. */ | |
3043c60c | 693 | static int |
d174bd64 DV |
694 | shmem_pwrite_slow(struct page *page, int shmem_page_offset, int page_length, |
695 | char __user *user_data, | |
696 | bool page_do_bit17_swizzling, | |
697 | bool needs_clflush_before, | |
698 | bool needs_clflush_after) | |
673a394b | 699 | { |
d174bd64 DV |
700 | char *vaddr; |
701 | int ret; | |
e5281ccd | 702 | |
d174bd64 | 703 | vaddr = kmap(page); |
e7e58eb5 | 704 | if (unlikely(needs_clflush_before || page_do_bit17_swizzling)) |
23c18c71 DV |
705 | shmem_clflush_swizzled_range(vaddr + shmem_page_offset, |
706 | page_length, | |
707 | page_do_bit17_swizzling); | |
d174bd64 DV |
708 | if (page_do_bit17_swizzling) |
709 | ret = __copy_from_user_swizzled(vaddr, shmem_page_offset, | |
e5281ccd CW |
710 | user_data, |
711 | page_length); | |
d174bd64 DV |
712 | else |
713 | ret = __copy_from_user(vaddr + shmem_page_offset, | |
714 | user_data, | |
715 | page_length); | |
716 | if (needs_clflush_after) | |
23c18c71 DV |
717 | shmem_clflush_swizzled_range(vaddr + shmem_page_offset, |
718 | page_length, | |
719 | page_do_bit17_swizzling); | |
d174bd64 | 720 | kunmap(page); |
40123c1f | 721 | |
755d2218 | 722 | return ret ? -EFAULT : 0; |
40123c1f EA |
723 | } |
724 | ||
40123c1f | 725 | static int |
e244a443 DV |
726 | i915_gem_shmem_pwrite(struct drm_device *dev, |
727 | struct drm_i915_gem_object *obj, | |
728 | struct drm_i915_gem_pwrite *args, | |
729 | struct drm_file *file) | |
40123c1f | 730 | { |
40123c1f | 731 | ssize_t remain; |
8c59967c DV |
732 | loff_t offset; |
733 | char __user *user_data; | |
eb2c0c81 | 734 | int shmem_page_offset, page_length, ret = 0; |
8c59967c | 735 | int obj_do_bit17_swizzling, page_do_bit17_swizzling; |
e244a443 | 736 | int hit_slowpath = 0; |
58642885 DV |
737 | int needs_clflush_after = 0; |
738 | int needs_clflush_before = 0; | |
67d5a50c | 739 | struct sg_page_iter sg_iter; |
40123c1f | 740 | |
2bb4629a | 741 | user_data = to_user_ptr(args->data_ptr); |
40123c1f EA |
742 | remain = args->size; |
743 | ||
8c59967c | 744 | obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj); |
40123c1f | 745 | |
58642885 DV |
746 | if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) { |
747 | /* If we're not in the cpu write domain, set ourself into the gtt | |
748 | * write domain and manually flush cachelines (if required). This | |
749 | * optimizes for the case when the gpu will use the data | |
750 | * right away and we therefore have to clflush anyway. */ | |
2c22569b | 751 | needs_clflush_after = cpu_write_needs_clflush(obj); |
23f54483 BW |
752 | ret = i915_gem_object_wait_rendering(obj, false); |
753 | if (ret) | |
754 | return ret; | |
58642885 | 755 | } |
c76ce038 CW |
756 | /* Same trick applies to invalidate partially written cachelines read |
757 | * before writing. */ | |
758 | if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) | |
759 | needs_clflush_before = | |
760 | !cpu_cache_is_coherent(dev, obj->cache_level); | |
58642885 | 761 | |
755d2218 CW |
762 | ret = i915_gem_object_get_pages(obj); |
763 | if (ret) | |
764 | return ret; | |
765 | ||
766 | i915_gem_object_pin_pages(obj); | |
767 | ||
673a394b | 768 | offset = args->offset; |
05394f39 | 769 | obj->dirty = 1; |
673a394b | 770 | |
67d5a50c ID |
771 | for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, |
772 | offset >> PAGE_SHIFT) { | |
2db76d7c | 773 | struct page *page = sg_page_iter_page(&sg_iter); |
58642885 | 774 | int partial_cacheline_write; |
e5281ccd | 775 | |
9da3da66 CW |
776 | if (remain <= 0) |
777 | break; | |
778 | ||
40123c1f EA |
779 | /* Operation in this page |
780 | * | |
40123c1f | 781 | * shmem_page_offset = offset within page in shmem file |
40123c1f EA |
782 | * page_length = bytes to copy for this page |
783 | */ | |
c8cbbb8b | 784 | shmem_page_offset = offset_in_page(offset); |
40123c1f EA |
785 | |
786 | page_length = remain; | |
787 | if ((shmem_page_offset + page_length) > PAGE_SIZE) | |
788 | page_length = PAGE_SIZE - shmem_page_offset; | |
40123c1f | 789 | |
58642885 DV |
790 | /* If we don't overwrite a cacheline completely we need to be |
791 | * careful to have up-to-date data by first clflushing. Don't | |
792 | * overcomplicate things and flush the entire patch. */ | |
793 | partial_cacheline_write = needs_clflush_before && | |
794 | ((shmem_page_offset | page_length) | |
795 | & (boot_cpu_data.x86_clflush_size - 1)); | |
796 | ||
8c59967c DV |
797 | page_do_bit17_swizzling = obj_do_bit17_swizzling && |
798 | (page_to_phys(page) & (1 << 17)) != 0; | |
799 | ||
d174bd64 DV |
800 | ret = shmem_pwrite_fast(page, shmem_page_offset, page_length, |
801 | user_data, page_do_bit17_swizzling, | |
802 | partial_cacheline_write, | |
803 | needs_clflush_after); | |
804 | if (ret == 0) | |
805 | goto next_page; | |
e244a443 DV |
806 | |
807 | hit_slowpath = 1; | |
e244a443 | 808 | mutex_unlock(&dev->struct_mutex); |
d174bd64 DV |
809 | ret = shmem_pwrite_slow(page, shmem_page_offset, page_length, |
810 | user_data, page_do_bit17_swizzling, | |
811 | partial_cacheline_write, | |
812 | needs_clflush_after); | |
40123c1f | 813 | |
e244a443 | 814 | mutex_lock(&dev->struct_mutex); |
755d2218 | 815 | |
e244a443 | 816 | next_page: |
e5281ccd CW |
817 | set_page_dirty(page); |
818 | mark_page_accessed(page); | |
e5281ccd | 819 | |
755d2218 | 820 | if (ret) |
8c59967c | 821 | goto out; |
8c59967c | 822 | |
40123c1f | 823 | remain -= page_length; |
8c59967c | 824 | user_data += page_length; |
40123c1f | 825 | offset += page_length; |
673a394b EA |
826 | } |
827 | ||
fbd5a26d | 828 | out: |
755d2218 CW |
829 | i915_gem_object_unpin_pages(obj); |
830 | ||
e244a443 | 831 | if (hit_slowpath) { |
8dcf015e DV |
832 | /* |
833 | * Fixup: Flush cpu caches in case we didn't flush the dirty | |
834 | * cachelines in-line while writing and the object moved | |
835 | * out of the cpu write domain while we've dropped the lock. | |
836 | */ | |
837 | if (!needs_clflush_after && | |
838 | obj->base.write_domain != I915_GEM_DOMAIN_CPU) { | |
000433b6 CW |
839 | if (i915_gem_clflush_object(obj, obj->pin_display)) |
840 | i915_gem_chipset_flush(dev); | |
e244a443 | 841 | } |
8c59967c | 842 | } |
673a394b | 843 | |
58642885 | 844 | if (needs_clflush_after) |
e76e9aeb | 845 | i915_gem_chipset_flush(dev); |
58642885 | 846 | |
40123c1f | 847 | return ret; |
673a394b EA |
848 | } |
849 | ||
850 | /** | |
851 | * Writes data to the object referenced by handle. | |
852 | * | |
853 | * On error, the contents of the buffer that were to be modified are undefined. | |
854 | */ | |
855 | int | |
856 | i915_gem_pwrite_ioctl(struct drm_device *dev, void *data, | |
fbd5a26d | 857 | struct drm_file *file) |
673a394b EA |
858 | { |
859 | struct drm_i915_gem_pwrite *args = data; | |
05394f39 | 860 | struct drm_i915_gem_object *obj; |
51311d0a CW |
861 | int ret; |
862 | ||
863 | if (args->size == 0) | |
864 | return 0; | |
865 | ||
866 | if (!access_ok(VERIFY_READ, | |
2bb4629a | 867 | to_user_ptr(args->data_ptr), |
51311d0a CW |
868 | args->size)) |
869 | return -EFAULT; | |
870 | ||
0b74b508 XZ |
871 | if (likely(!i915_prefault_disable)) { |
872 | ret = fault_in_multipages_readable(to_user_ptr(args->data_ptr), | |
873 | args->size); | |
874 | if (ret) | |
875 | return -EFAULT; | |
876 | } | |
673a394b | 877 | |
fbd5a26d | 878 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 879 | if (ret) |
fbd5a26d | 880 | return ret; |
1d7cfea1 | 881 | |
05394f39 | 882 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 883 | if (&obj->base == NULL) { |
1d7cfea1 CW |
884 | ret = -ENOENT; |
885 | goto unlock; | |
fbd5a26d | 886 | } |
673a394b | 887 | |
7dcd2499 | 888 | /* Bounds check destination. */ |
05394f39 CW |
889 | if (args->offset > obj->base.size || |
890 | args->size > obj->base.size - args->offset) { | |
ce9d419d | 891 | ret = -EINVAL; |
35b62a89 | 892 | goto out; |
ce9d419d CW |
893 | } |
894 | ||
1286ff73 DV |
895 | /* prime objects have no backing filp to GEM pread/pwrite |
896 | * pages from. | |
897 | */ | |
898 | if (!obj->base.filp) { | |
899 | ret = -EINVAL; | |
900 | goto out; | |
901 | } | |
902 | ||
db53a302 CW |
903 | trace_i915_gem_object_pwrite(obj, args->offset, args->size); |
904 | ||
935aaa69 | 905 | ret = -EFAULT; |
673a394b EA |
906 | /* We can only do the GTT pwrite on untiled buffers, as otherwise |
907 | * it would end up going through the fenced access, and we'll get | |
908 | * different detiling behavior between reading and writing. | |
909 | * pread/pwrite currently are reading and writing from the CPU | |
910 | * perspective, requiring manual detiling by the client. | |
911 | */ | |
5c0480f2 | 912 | if (obj->phys_obj) { |
fbd5a26d | 913 | ret = i915_gem_phys_pwrite(dev, obj, args, file); |
5c0480f2 DV |
914 | goto out; |
915 | } | |
916 | ||
2c22569b CW |
917 | if (obj->tiling_mode == I915_TILING_NONE && |
918 | obj->base.write_domain != I915_GEM_DOMAIN_CPU && | |
919 | cpu_write_needs_clflush(obj)) { | |
fbd5a26d | 920 | ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file); |
935aaa69 DV |
921 | /* Note that the gtt paths might fail with non-page-backed user |
922 | * pointers (e.g. gtt mappings when moving data between | |
923 | * textures). Fallback to the shmem path in that case. */ | |
fbd5a26d | 924 | } |
673a394b | 925 | |
86a1ee26 | 926 | if (ret == -EFAULT || ret == -ENOSPC) |
935aaa69 | 927 | ret = i915_gem_shmem_pwrite(dev, obj, args, file); |
5c0480f2 | 928 | |
35b62a89 | 929 | out: |
05394f39 | 930 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 931 | unlock: |
fbd5a26d | 932 | mutex_unlock(&dev->struct_mutex); |
673a394b EA |
933 | return ret; |
934 | } | |
935 | ||
b361237b | 936 | int |
33196ded | 937 | i915_gem_check_wedge(struct i915_gpu_error *error, |
b361237b CW |
938 | bool interruptible) |
939 | { | |
1f83fee0 | 940 | if (i915_reset_in_progress(error)) { |
b361237b CW |
941 | /* Non-interruptible callers can't handle -EAGAIN, hence return |
942 | * -EIO unconditionally for these. */ | |
943 | if (!interruptible) | |
944 | return -EIO; | |
945 | ||
1f83fee0 DV |
946 | /* Recovery complete, but the reset failed ... */ |
947 | if (i915_terminally_wedged(error)) | |
b361237b CW |
948 | return -EIO; |
949 | ||
950 | return -EAGAIN; | |
951 | } | |
952 | ||
953 | return 0; | |
954 | } | |
955 | ||
956 | /* | |
957 | * Compare seqno against outstanding lazy request. Emit a request if they are | |
958 | * equal. | |
959 | */ | |
960 | static int | |
961 | i915_gem_check_olr(struct intel_ring_buffer *ring, u32 seqno) | |
962 | { | |
963 | int ret; | |
964 | ||
965 | BUG_ON(!mutex_is_locked(&ring->dev->struct_mutex)); | |
966 | ||
967 | ret = 0; | |
1823521d | 968 | if (seqno == ring->outstanding_lazy_seqno) |
0025c077 | 969 | ret = i915_add_request(ring, NULL); |
b361237b CW |
970 | |
971 | return ret; | |
972 | } | |
973 | ||
974 | /** | |
975 | * __wait_seqno - wait until execution of seqno has finished | |
976 | * @ring: the ring expected to report seqno | |
977 | * @seqno: duh! | |
f69061be | 978 | * @reset_counter: reset sequence associated with the given seqno |
b361237b CW |
979 | * @interruptible: do an interruptible wait (normally yes) |
980 | * @timeout: in - how long to wait (NULL forever); out - how much time remaining | |
981 | * | |
f69061be DV |
982 | * Note: It is of utmost importance that the passed in seqno and reset_counter |
983 | * values have been read by the caller in an smp safe manner. Where read-side | |
984 | * locks are involved, it is sufficient to read the reset_counter before | |
985 | * unlocking the lock that protects the seqno. For lockless tricks, the | |
986 | * reset_counter _must_ be read before, and an appropriate smp_rmb must be | |
987 | * inserted. | |
988 | * | |
b361237b CW |
989 | * Returns 0 if the seqno was found within the alloted time. Else returns the |
990 | * errno with remaining time filled in timeout argument. | |
991 | */ | |
992 | static int __wait_seqno(struct intel_ring_buffer *ring, u32 seqno, | |
f69061be | 993 | unsigned reset_counter, |
b361237b CW |
994 | bool interruptible, struct timespec *timeout) |
995 | { | |
996 | drm_i915_private_t *dev_priv = ring->dev->dev_private; | |
997 | struct timespec before, now, wait_time={1,0}; | |
998 | unsigned long timeout_jiffies; | |
999 | long end; | |
1000 | bool wait_forever = true; | |
1001 | int ret; | |
1002 | ||
c67a470b PZ |
1003 | WARN(dev_priv->pc8.irqs_disabled, "IRQs disabled\n"); |
1004 | ||
b361237b CW |
1005 | if (i915_seqno_passed(ring->get_seqno(ring, true), seqno)) |
1006 | return 0; | |
1007 | ||
1008 | trace_i915_gem_request_wait_begin(ring, seqno); | |
1009 | ||
1010 | if (timeout != NULL) { | |
1011 | wait_time = *timeout; | |
1012 | wait_forever = false; | |
1013 | } | |
1014 | ||
e054cc39 | 1015 | timeout_jiffies = timespec_to_jiffies_timeout(&wait_time); |
b361237b CW |
1016 | |
1017 | if (WARN_ON(!ring->irq_get(ring))) | |
1018 | return -ENODEV; | |
1019 | ||
1020 | /* Record current time in case interrupted by signal, or wedged * */ | |
1021 | getrawmonotonic(&before); | |
1022 | ||
1023 | #define EXIT_COND \ | |
1024 | (i915_seqno_passed(ring->get_seqno(ring, false), seqno) || \ | |
f69061be DV |
1025 | i915_reset_in_progress(&dev_priv->gpu_error) || \ |
1026 | reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter)) | |
b361237b CW |
1027 | do { |
1028 | if (interruptible) | |
1029 | end = wait_event_interruptible_timeout(ring->irq_queue, | |
1030 | EXIT_COND, | |
1031 | timeout_jiffies); | |
1032 | else | |
1033 | end = wait_event_timeout(ring->irq_queue, EXIT_COND, | |
1034 | timeout_jiffies); | |
1035 | ||
f69061be DV |
1036 | /* We need to check whether any gpu reset happened in between |
1037 | * the caller grabbing the seqno and now ... */ | |
1038 | if (reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter)) | |
1039 | end = -EAGAIN; | |
1040 | ||
1041 | /* ... but upgrade the -EGAIN to an -EIO if the gpu is truely | |
1042 | * gone. */ | |
33196ded | 1043 | ret = i915_gem_check_wedge(&dev_priv->gpu_error, interruptible); |
b361237b CW |
1044 | if (ret) |
1045 | end = ret; | |
1046 | } while (end == 0 && wait_forever); | |
1047 | ||
1048 | getrawmonotonic(&now); | |
1049 | ||
1050 | ring->irq_put(ring); | |
1051 | trace_i915_gem_request_wait_end(ring, seqno); | |
1052 | #undef EXIT_COND | |
1053 | ||
1054 | if (timeout) { | |
1055 | struct timespec sleep_time = timespec_sub(now, before); | |
1056 | *timeout = timespec_sub(*timeout, sleep_time); | |
4f42f4ef CW |
1057 | if (!timespec_valid(timeout)) /* i.e. negative time remains */ |
1058 | set_normalized_timespec(timeout, 0, 0); | |
b361237b CW |
1059 | } |
1060 | ||
1061 | switch (end) { | |
1062 | case -EIO: | |
1063 | case -EAGAIN: /* Wedged */ | |
1064 | case -ERESTARTSYS: /* Signal */ | |
1065 | return (int)end; | |
1066 | case 0: /* Timeout */ | |
b361237b CW |
1067 | return -ETIME; |
1068 | default: /* Completed */ | |
1069 | WARN_ON(end < 0); /* We're not aware of other errors */ | |
1070 | return 0; | |
1071 | } | |
1072 | } | |
1073 | ||
1074 | /** | |
1075 | * Waits for a sequence number to be signaled, and cleans up the | |
1076 | * request and object lists appropriately for that event. | |
1077 | */ | |
1078 | int | |
1079 | i915_wait_seqno(struct intel_ring_buffer *ring, uint32_t seqno) | |
1080 | { | |
1081 | struct drm_device *dev = ring->dev; | |
1082 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1083 | bool interruptible = dev_priv->mm.interruptible; | |
1084 | int ret; | |
1085 | ||
1086 | BUG_ON(!mutex_is_locked(&dev->struct_mutex)); | |
1087 | BUG_ON(seqno == 0); | |
1088 | ||
33196ded | 1089 | ret = i915_gem_check_wedge(&dev_priv->gpu_error, interruptible); |
b361237b CW |
1090 | if (ret) |
1091 | return ret; | |
1092 | ||
1093 | ret = i915_gem_check_olr(ring, seqno); | |
1094 | if (ret) | |
1095 | return ret; | |
1096 | ||
f69061be DV |
1097 | return __wait_seqno(ring, seqno, |
1098 | atomic_read(&dev_priv->gpu_error.reset_counter), | |
1099 | interruptible, NULL); | |
b361237b CW |
1100 | } |
1101 | ||
d26e3af8 CW |
1102 | static int |
1103 | i915_gem_object_wait_rendering__tail(struct drm_i915_gem_object *obj, | |
1104 | struct intel_ring_buffer *ring) | |
1105 | { | |
1106 | i915_gem_retire_requests_ring(ring); | |
1107 | ||
1108 | /* Manually manage the write flush as we may have not yet | |
1109 | * retired the buffer. | |
1110 | * | |
1111 | * Note that the last_write_seqno is always the earlier of | |
1112 | * the two (read/write) seqno, so if we haved successfully waited, | |
1113 | * we know we have passed the last write. | |
1114 | */ | |
1115 | obj->last_write_seqno = 0; | |
1116 | obj->base.write_domain &= ~I915_GEM_GPU_DOMAINS; | |
1117 | ||
1118 | return 0; | |
1119 | } | |
1120 | ||
b361237b CW |
1121 | /** |
1122 | * Ensures that all rendering to the object has completed and the object is | |
1123 | * safe to unbind from the GTT or access from the CPU. | |
1124 | */ | |
1125 | static __must_check int | |
1126 | i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj, | |
1127 | bool readonly) | |
1128 | { | |
1129 | struct intel_ring_buffer *ring = obj->ring; | |
1130 | u32 seqno; | |
1131 | int ret; | |
1132 | ||
1133 | seqno = readonly ? obj->last_write_seqno : obj->last_read_seqno; | |
1134 | if (seqno == 0) | |
1135 | return 0; | |
1136 | ||
1137 | ret = i915_wait_seqno(ring, seqno); | |
1138 | if (ret) | |
1139 | return ret; | |
1140 | ||
d26e3af8 | 1141 | return i915_gem_object_wait_rendering__tail(obj, ring); |
b361237b CW |
1142 | } |
1143 | ||
3236f57a CW |
1144 | /* A nonblocking variant of the above wait. This is a highly dangerous routine |
1145 | * as the object state may change during this call. | |
1146 | */ | |
1147 | static __must_check int | |
1148 | i915_gem_object_wait_rendering__nonblocking(struct drm_i915_gem_object *obj, | |
1149 | bool readonly) | |
1150 | { | |
1151 | struct drm_device *dev = obj->base.dev; | |
1152 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1153 | struct intel_ring_buffer *ring = obj->ring; | |
f69061be | 1154 | unsigned reset_counter; |
3236f57a CW |
1155 | u32 seqno; |
1156 | int ret; | |
1157 | ||
1158 | BUG_ON(!mutex_is_locked(&dev->struct_mutex)); | |
1159 | BUG_ON(!dev_priv->mm.interruptible); | |
1160 | ||
1161 | seqno = readonly ? obj->last_write_seqno : obj->last_read_seqno; | |
1162 | if (seqno == 0) | |
1163 | return 0; | |
1164 | ||
33196ded | 1165 | ret = i915_gem_check_wedge(&dev_priv->gpu_error, true); |
3236f57a CW |
1166 | if (ret) |
1167 | return ret; | |
1168 | ||
1169 | ret = i915_gem_check_olr(ring, seqno); | |
1170 | if (ret) | |
1171 | return ret; | |
1172 | ||
f69061be | 1173 | reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter); |
3236f57a | 1174 | mutex_unlock(&dev->struct_mutex); |
f69061be | 1175 | ret = __wait_seqno(ring, seqno, reset_counter, true, NULL); |
3236f57a | 1176 | mutex_lock(&dev->struct_mutex); |
d26e3af8 CW |
1177 | if (ret) |
1178 | return ret; | |
3236f57a | 1179 | |
d26e3af8 | 1180 | return i915_gem_object_wait_rendering__tail(obj, ring); |
3236f57a CW |
1181 | } |
1182 | ||
673a394b | 1183 | /** |
2ef7eeaa EA |
1184 | * Called when user space prepares to use an object with the CPU, either |
1185 | * through the mmap ioctl's mapping or a GTT mapping. | |
673a394b EA |
1186 | */ |
1187 | int | |
1188 | i915_gem_set_domain_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 1189 | struct drm_file *file) |
673a394b EA |
1190 | { |
1191 | struct drm_i915_gem_set_domain *args = data; | |
05394f39 | 1192 | struct drm_i915_gem_object *obj; |
2ef7eeaa EA |
1193 | uint32_t read_domains = args->read_domains; |
1194 | uint32_t write_domain = args->write_domain; | |
673a394b EA |
1195 | int ret; |
1196 | ||
2ef7eeaa | 1197 | /* Only handle setting domains to types used by the CPU. */ |
21d509e3 | 1198 | if (write_domain & I915_GEM_GPU_DOMAINS) |
2ef7eeaa EA |
1199 | return -EINVAL; |
1200 | ||
21d509e3 | 1201 | if (read_domains & I915_GEM_GPU_DOMAINS) |
2ef7eeaa EA |
1202 | return -EINVAL; |
1203 | ||
1204 | /* Having something in the write domain implies it's in the read | |
1205 | * domain, and only that read domain. Enforce that in the request. | |
1206 | */ | |
1207 | if (write_domain != 0 && read_domains != write_domain) | |
1208 | return -EINVAL; | |
1209 | ||
76c1dec1 | 1210 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 1211 | if (ret) |
76c1dec1 | 1212 | return ret; |
1d7cfea1 | 1213 | |
05394f39 | 1214 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 1215 | if (&obj->base == NULL) { |
1d7cfea1 CW |
1216 | ret = -ENOENT; |
1217 | goto unlock; | |
76c1dec1 | 1218 | } |
673a394b | 1219 | |
3236f57a CW |
1220 | /* Try to flush the object off the GPU without holding the lock. |
1221 | * We will repeat the flush holding the lock in the normal manner | |
1222 | * to catch cases where we are gazumped. | |
1223 | */ | |
1224 | ret = i915_gem_object_wait_rendering__nonblocking(obj, !write_domain); | |
1225 | if (ret) | |
1226 | goto unref; | |
1227 | ||
2ef7eeaa EA |
1228 | if (read_domains & I915_GEM_DOMAIN_GTT) { |
1229 | ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0); | |
02354392 EA |
1230 | |
1231 | /* Silently promote "you're not bound, there was nothing to do" | |
1232 | * to success, since the client was just asking us to | |
1233 | * make sure everything was done. | |
1234 | */ | |
1235 | if (ret == -EINVAL) | |
1236 | ret = 0; | |
2ef7eeaa | 1237 | } else { |
e47c68e9 | 1238 | ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0); |
2ef7eeaa EA |
1239 | } |
1240 | ||
3236f57a | 1241 | unref: |
05394f39 | 1242 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 1243 | unlock: |
673a394b EA |
1244 | mutex_unlock(&dev->struct_mutex); |
1245 | return ret; | |
1246 | } | |
1247 | ||
1248 | /** | |
1249 | * Called when user space has done writes to this buffer | |
1250 | */ | |
1251 | int | |
1252 | i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 1253 | struct drm_file *file) |
673a394b EA |
1254 | { |
1255 | struct drm_i915_gem_sw_finish *args = data; | |
05394f39 | 1256 | struct drm_i915_gem_object *obj; |
673a394b EA |
1257 | int ret = 0; |
1258 | ||
76c1dec1 | 1259 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 1260 | if (ret) |
76c1dec1 | 1261 | return ret; |
1d7cfea1 | 1262 | |
05394f39 | 1263 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 1264 | if (&obj->base == NULL) { |
1d7cfea1 CW |
1265 | ret = -ENOENT; |
1266 | goto unlock; | |
673a394b EA |
1267 | } |
1268 | ||
673a394b | 1269 | /* Pinned buffers may be scanout, so flush the cache */ |
2c22569b CW |
1270 | if (obj->pin_display) |
1271 | i915_gem_object_flush_cpu_write_domain(obj, true); | |
e47c68e9 | 1272 | |
05394f39 | 1273 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 1274 | unlock: |
673a394b EA |
1275 | mutex_unlock(&dev->struct_mutex); |
1276 | return ret; | |
1277 | } | |
1278 | ||
1279 | /** | |
1280 | * Maps the contents of an object, returning the address it is mapped | |
1281 | * into. | |
1282 | * | |
1283 | * While the mapping holds a reference on the contents of the object, it doesn't | |
1284 | * imply a ref on the object itself. | |
1285 | */ | |
1286 | int | |
1287 | i915_gem_mmap_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 1288 | struct drm_file *file) |
673a394b EA |
1289 | { |
1290 | struct drm_i915_gem_mmap *args = data; | |
1291 | struct drm_gem_object *obj; | |
673a394b EA |
1292 | unsigned long addr; |
1293 | ||
05394f39 | 1294 | obj = drm_gem_object_lookup(dev, file, args->handle); |
673a394b | 1295 | if (obj == NULL) |
bf79cb91 | 1296 | return -ENOENT; |
673a394b | 1297 | |
1286ff73 DV |
1298 | /* prime objects have no backing filp to GEM mmap |
1299 | * pages from. | |
1300 | */ | |
1301 | if (!obj->filp) { | |
1302 | drm_gem_object_unreference_unlocked(obj); | |
1303 | return -EINVAL; | |
1304 | } | |
1305 | ||
6be5ceb0 | 1306 | addr = vm_mmap(obj->filp, 0, args->size, |
673a394b EA |
1307 | PROT_READ | PROT_WRITE, MAP_SHARED, |
1308 | args->offset); | |
bc9025bd | 1309 | drm_gem_object_unreference_unlocked(obj); |
673a394b EA |
1310 | if (IS_ERR((void *)addr)) |
1311 | return addr; | |
1312 | ||
1313 | args->addr_ptr = (uint64_t) addr; | |
1314 | ||
1315 | return 0; | |
1316 | } | |
1317 | ||
de151cf6 JB |
1318 | /** |
1319 | * i915_gem_fault - fault a page into the GTT | |
1320 | * vma: VMA in question | |
1321 | * vmf: fault info | |
1322 | * | |
1323 | * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped | |
1324 | * from userspace. The fault handler takes care of binding the object to | |
1325 | * the GTT (if needed), allocating and programming a fence register (again, | |
1326 | * only if needed based on whether the old reg is still valid or the object | |
1327 | * is tiled) and inserting a new PTE into the faulting process. | |
1328 | * | |
1329 | * Note that the faulting process may involve evicting existing objects | |
1330 | * from the GTT and/or fence registers to make room. So performance may | |
1331 | * suffer if the GTT working set is large or there are few fence registers | |
1332 | * left. | |
1333 | */ | |
1334 | int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf) | |
1335 | { | |
05394f39 CW |
1336 | struct drm_i915_gem_object *obj = to_intel_bo(vma->vm_private_data); |
1337 | struct drm_device *dev = obj->base.dev; | |
7d1c4804 | 1338 | drm_i915_private_t *dev_priv = dev->dev_private; |
de151cf6 JB |
1339 | pgoff_t page_offset; |
1340 | unsigned long pfn; | |
1341 | int ret = 0; | |
0f973f27 | 1342 | bool write = !!(vmf->flags & FAULT_FLAG_WRITE); |
de151cf6 JB |
1343 | |
1344 | /* We don't use vmf->pgoff since that has the fake offset */ | |
1345 | page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >> | |
1346 | PAGE_SHIFT; | |
1347 | ||
d9bc7e9f CW |
1348 | ret = i915_mutex_lock_interruptible(dev); |
1349 | if (ret) | |
1350 | goto out; | |
a00b10c3 | 1351 | |
db53a302 CW |
1352 | trace_i915_gem_object_fault(obj, page_offset, true, write); |
1353 | ||
eb119bd6 CW |
1354 | /* Access to snoopable pages through the GTT is incoherent. */ |
1355 | if (obj->cache_level != I915_CACHE_NONE && !HAS_LLC(dev)) { | |
1356 | ret = -EINVAL; | |
1357 | goto unlock; | |
1358 | } | |
1359 | ||
d9bc7e9f | 1360 | /* Now bind it into the GTT if needed */ |
c37e2204 | 1361 | ret = i915_gem_obj_ggtt_pin(obj, 0, true, false); |
c9839303 CW |
1362 | if (ret) |
1363 | goto unlock; | |
4a684a41 | 1364 | |
c9839303 CW |
1365 | ret = i915_gem_object_set_to_gtt_domain(obj, write); |
1366 | if (ret) | |
1367 | goto unpin; | |
74898d7e | 1368 | |
06d98131 | 1369 | ret = i915_gem_object_get_fence(obj); |
d9e86c0e | 1370 | if (ret) |
c9839303 | 1371 | goto unpin; |
7d1c4804 | 1372 | |
6299f992 CW |
1373 | obj->fault_mappable = true; |
1374 | ||
f343c5f6 BW |
1375 | pfn = dev_priv->gtt.mappable_base + i915_gem_obj_ggtt_offset(obj); |
1376 | pfn >>= PAGE_SHIFT; | |
1377 | pfn += page_offset; | |
de151cf6 JB |
1378 | |
1379 | /* Finally, remap it using the new GTT offset */ | |
1380 | ret = vm_insert_pfn(vma, (unsigned long)vmf->virtual_address, pfn); | |
c9839303 CW |
1381 | unpin: |
1382 | i915_gem_object_unpin(obj); | |
c715089f | 1383 | unlock: |
de151cf6 | 1384 | mutex_unlock(&dev->struct_mutex); |
d9bc7e9f | 1385 | out: |
de151cf6 | 1386 | switch (ret) { |
d9bc7e9f | 1387 | case -EIO: |
a9340cca DV |
1388 | /* If this -EIO is due to a gpu hang, give the reset code a |
1389 | * chance to clean up the mess. Otherwise return the proper | |
1390 | * SIGBUS. */ | |
1f83fee0 | 1391 | if (i915_terminally_wedged(&dev_priv->gpu_error)) |
a9340cca | 1392 | return VM_FAULT_SIGBUS; |
045e769a | 1393 | case -EAGAIN: |
571c608d DV |
1394 | /* |
1395 | * EAGAIN means the gpu is hung and we'll wait for the error | |
1396 | * handler to reset everything when re-faulting in | |
1397 | * i915_mutex_lock_interruptible. | |
d9bc7e9f | 1398 | */ |
c715089f CW |
1399 | case 0: |
1400 | case -ERESTARTSYS: | |
bed636ab | 1401 | case -EINTR: |
e79e0fe3 DR |
1402 | case -EBUSY: |
1403 | /* | |
1404 | * EBUSY is ok: this just means that another thread | |
1405 | * already did the job. | |
1406 | */ | |
c715089f | 1407 | return VM_FAULT_NOPAGE; |
de151cf6 | 1408 | case -ENOMEM: |
de151cf6 | 1409 | return VM_FAULT_OOM; |
a7c2e1aa DV |
1410 | case -ENOSPC: |
1411 | return VM_FAULT_SIGBUS; | |
de151cf6 | 1412 | default: |
a7c2e1aa | 1413 | WARN_ONCE(ret, "unhandled error in i915_gem_fault: %i\n", ret); |
c715089f | 1414 | return VM_FAULT_SIGBUS; |
de151cf6 JB |
1415 | } |
1416 | } | |
1417 | ||
901782b2 CW |
1418 | /** |
1419 | * i915_gem_release_mmap - remove physical page mappings | |
1420 | * @obj: obj in question | |
1421 | * | |
af901ca1 | 1422 | * Preserve the reservation of the mmapping with the DRM core code, but |
901782b2 CW |
1423 | * relinquish ownership of the pages back to the system. |
1424 | * | |
1425 | * It is vital that we remove the page mapping if we have mapped a tiled | |
1426 | * object through the GTT and then lose the fence register due to | |
1427 | * resource pressure. Similarly if the object has been moved out of the | |
1428 | * aperture, than pages mapped into userspace must be revoked. Removing the | |
1429 | * mapping will then trigger a page fault on the next user access, allowing | |
1430 | * fixup by i915_gem_fault(). | |
1431 | */ | |
d05ca301 | 1432 | void |
05394f39 | 1433 | i915_gem_release_mmap(struct drm_i915_gem_object *obj) |
901782b2 | 1434 | { |
6299f992 CW |
1435 | if (!obj->fault_mappable) |
1436 | return; | |
901782b2 | 1437 | |
51335df9 | 1438 | drm_vma_node_unmap(&obj->base.vma_node, obj->base.dev->dev_mapping); |
6299f992 | 1439 | obj->fault_mappable = false; |
901782b2 CW |
1440 | } |
1441 | ||
0fa87796 | 1442 | uint32_t |
e28f8711 | 1443 | i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode) |
92b88aeb | 1444 | { |
e28f8711 | 1445 | uint32_t gtt_size; |
92b88aeb CW |
1446 | |
1447 | if (INTEL_INFO(dev)->gen >= 4 || | |
e28f8711 CW |
1448 | tiling_mode == I915_TILING_NONE) |
1449 | return size; | |
92b88aeb CW |
1450 | |
1451 | /* Previous chips need a power-of-two fence region when tiling */ | |
1452 | if (INTEL_INFO(dev)->gen == 3) | |
e28f8711 | 1453 | gtt_size = 1024*1024; |
92b88aeb | 1454 | else |
e28f8711 | 1455 | gtt_size = 512*1024; |
92b88aeb | 1456 | |
e28f8711 CW |
1457 | while (gtt_size < size) |
1458 | gtt_size <<= 1; | |
92b88aeb | 1459 | |
e28f8711 | 1460 | return gtt_size; |
92b88aeb CW |
1461 | } |
1462 | ||
de151cf6 JB |
1463 | /** |
1464 | * i915_gem_get_gtt_alignment - return required GTT alignment for an object | |
1465 | * @obj: object to check | |
1466 | * | |
1467 | * Return the required GTT alignment for an object, taking into account | |
5e783301 | 1468 | * potential fence register mapping. |
de151cf6 | 1469 | */ |
d865110c ID |
1470 | uint32_t |
1471 | i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size, | |
1472 | int tiling_mode, bool fenced) | |
de151cf6 | 1473 | { |
de151cf6 JB |
1474 | /* |
1475 | * Minimum alignment is 4k (GTT page size), but might be greater | |
1476 | * if a fence register is needed for the object. | |
1477 | */ | |
d865110c | 1478 | if (INTEL_INFO(dev)->gen >= 4 || (!fenced && IS_G33(dev)) || |
e28f8711 | 1479 | tiling_mode == I915_TILING_NONE) |
de151cf6 JB |
1480 | return 4096; |
1481 | ||
a00b10c3 CW |
1482 | /* |
1483 | * Previous chips need to be aligned to the size of the smallest | |
1484 | * fence register that can contain the object. | |
1485 | */ | |
e28f8711 | 1486 | return i915_gem_get_gtt_size(dev, size, tiling_mode); |
a00b10c3 CW |
1487 | } |
1488 | ||
d8cb5086 CW |
1489 | static int i915_gem_object_create_mmap_offset(struct drm_i915_gem_object *obj) |
1490 | { | |
1491 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; | |
1492 | int ret; | |
1493 | ||
0de23977 | 1494 | if (drm_vma_node_has_offset(&obj->base.vma_node)) |
d8cb5086 CW |
1495 | return 0; |
1496 | ||
da494d7c DV |
1497 | dev_priv->mm.shrinker_no_lock_stealing = true; |
1498 | ||
d8cb5086 CW |
1499 | ret = drm_gem_create_mmap_offset(&obj->base); |
1500 | if (ret != -ENOSPC) | |
da494d7c | 1501 | goto out; |
d8cb5086 CW |
1502 | |
1503 | /* Badly fragmented mmap space? The only way we can recover | |
1504 | * space is by destroying unwanted objects. We can't randomly release | |
1505 | * mmap_offsets as userspace expects them to be persistent for the | |
1506 | * lifetime of the objects. The closest we can is to release the | |
1507 | * offsets on purgeable objects by truncating it and marking it purged, | |
1508 | * which prevents userspace from ever using that object again. | |
1509 | */ | |
1510 | i915_gem_purge(dev_priv, obj->base.size >> PAGE_SHIFT); | |
1511 | ret = drm_gem_create_mmap_offset(&obj->base); | |
1512 | if (ret != -ENOSPC) | |
da494d7c | 1513 | goto out; |
d8cb5086 CW |
1514 | |
1515 | i915_gem_shrink_all(dev_priv); | |
da494d7c DV |
1516 | ret = drm_gem_create_mmap_offset(&obj->base); |
1517 | out: | |
1518 | dev_priv->mm.shrinker_no_lock_stealing = false; | |
1519 | ||
1520 | return ret; | |
d8cb5086 CW |
1521 | } |
1522 | ||
1523 | static void i915_gem_object_free_mmap_offset(struct drm_i915_gem_object *obj) | |
1524 | { | |
d8cb5086 CW |
1525 | drm_gem_free_mmap_offset(&obj->base); |
1526 | } | |
1527 | ||
de151cf6 | 1528 | int |
ff72145b DA |
1529 | i915_gem_mmap_gtt(struct drm_file *file, |
1530 | struct drm_device *dev, | |
1531 | uint32_t handle, | |
1532 | uint64_t *offset) | |
de151cf6 | 1533 | { |
da761a6e | 1534 | struct drm_i915_private *dev_priv = dev->dev_private; |
05394f39 | 1535 | struct drm_i915_gem_object *obj; |
de151cf6 JB |
1536 | int ret; |
1537 | ||
76c1dec1 | 1538 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 1539 | if (ret) |
76c1dec1 | 1540 | return ret; |
de151cf6 | 1541 | |
ff72145b | 1542 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle)); |
c8725226 | 1543 | if (&obj->base == NULL) { |
1d7cfea1 CW |
1544 | ret = -ENOENT; |
1545 | goto unlock; | |
1546 | } | |
de151cf6 | 1547 | |
5d4545ae | 1548 | if (obj->base.size > dev_priv->gtt.mappable_end) { |
da761a6e | 1549 | ret = -E2BIG; |
ff56b0bc | 1550 | goto out; |
da761a6e CW |
1551 | } |
1552 | ||
05394f39 | 1553 | if (obj->madv != I915_MADV_WILLNEED) { |
ab18282d | 1554 | DRM_ERROR("Attempting to mmap a purgeable buffer\n"); |
1d7cfea1 CW |
1555 | ret = -EINVAL; |
1556 | goto out; | |
ab18282d CW |
1557 | } |
1558 | ||
d8cb5086 CW |
1559 | ret = i915_gem_object_create_mmap_offset(obj); |
1560 | if (ret) | |
1561 | goto out; | |
de151cf6 | 1562 | |
0de23977 | 1563 | *offset = drm_vma_node_offset_addr(&obj->base.vma_node); |
de151cf6 | 1564 | |
1d7cfea1 | 1565 | out: |
05394f39 | 1566 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 1567 | unlock: |
de151cf6 | 1568 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 1569 | return ret; |
de151cf6 JB |
1570 | } |
1571 | ||
ff72145b DA |
1572 | /** |
1573 | * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing | |
1574 | * @dev: DRM device | |
1575 | * @data: GTT mapping ioctl data | |
1576 | * @file: GEM object info | |
1577 | * | |
1578 | * Simply returns the fake offset to userspace so it can mmap it. | |
1579 | * The mmap call will end up in drm_gem_mmap(), which will set things | |
1580 | * up so we can get faults in the handler above. | |
1581 | * | |
1582 | * The fault handler will take care of binding the object into the GTT | |
1583 | * (since it may have been evicted to make room for something), allocating | |
1584 | * a fence register, and mapping the appropriate aperture address into | |
1585 | * userspace. | |
1586 | */ | |
1587 | int | |
1588 | i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data, | |
1589 | struct drm_file *file) | |
1590 | { | |
1591 | struct drm_i915_gem_mmap_gtt *args = data; | |
1592 | ||
ff72145b DA |
1593 | return i915_gem_mmap_gtt(file, dev, args->handle, &args->offset); |
1594 | } | |
1595 | ||
225067ee DV |
1596 | /* Immediately discard the backing storage */ |
1597 | static void | |
1598 | i915_gem_object_truncate(struct drm_i915_gem_object *obj) | |
e5281ccd | 1599 | { |
e5281ccd | 1600 | struct inode *inode; |
e5281ccd | 1601 | |
4d6294bf | 1602 | i915_gem_object_free_mmap_offset(obj); |
1286ff73 | 1603 | |
4d6294bf CW |
1604 | if (obj->base.filp == NULL) |
1605 | return; | |
e5281ccd | 1606 | |
225067ee DV |
1607 | /* Our goal here is to return as much of the memory as |
1608 | * is possible back to the system as we are called from OOM. | |
1609 | * To do this we must instruct the shmfs to drop all of its | |
1610 | * backing pages, *now*. | |
1611 | */ | |
496ad9aa | 1612 | inode = file_inode(obj->base.filp); |
225067ee | 1613 | shmem_truncate_range(inode, 0, (loff_t)-1); |
e5281ccd | 1614 | |
225067ee DV |
1615 | obj->madv = __I915_MADV_PURGED; |
1616 | } | |
e5281ccd | 1617 | |
225067ee DV |
1618 | static inline int |
1619 | i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj) | |
1620 | { | |
1621 | return obj->madv == I915_MADV_DONTNEED; | |
e5281ccd CW |
1622 | } |
1623 | ||
5cdf5881 | 1624 | static void |
05394f39 | 1625 | i915_gem_object_put_pages_gtt(struct drm_i915_gem_object *obj) |
673a394b | 1626 | { |
90797e6d ID |
1627 | struct sg_page_iter sg_iter; |
1628 | int ret; | |
1286ff73 | 1629 | |
05394f39 | 1630 | BUG_ON(obj->madv == __I915_MADV_PURGED); |
673a394b | 1631 | |
6c085a72 CW |
1632 | ret = i915_gem_object_set_to_cpu_domain(obj, true); |
1633 | if (ret) { | |
1634 | /* In the event of a disaster, abandon all caches and | |
1635 | * hope for the best. | |
1636 | */ | |
1637 | WARN_ON(ret != -EIO); | |
2c22569b | 1638 | i915_gem_clflush_object(obj, true); |
6c085a72 CW |
1639 | obj->base.read_domains = obj->base.write_domain = I915_GEM_DOMAIN_CPU; |
1640 | } | |
1641 | ||
6dacfd2f | 1642 | if (i915_gem_object_needs_bit17_swizzle(obj)) |
280b713b EA |
1643 | i915_gem_object_save_bit_17_swizzle(obj); |
1644 | ||
05394f39 CW |
1645 | if (obj->madv == I915_MADV_DONTNEED) |
1646 | obj->dirty = 0; | |
3ef94daa | 1647 | |
90797e6d | 1648 | for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, 0) { |
2db76d7c | 1649 | struct page *page = sg_page_iter_page(&sg_iter); |
9da3da66 | 1650 | |
05394f39 | 1651 | if (obj->dirty) |
9da3da66 | 1652 | set_page_dirty(page); |
3ef94daa | 1653 | |
05394f39 | 1654 | if (obj->madv == I915_MADV_WILLNEED) |
9da3da66 | 1655 | mark_page_accessed(page); |
3ef94daa | 1656 | |
9da3da66 | 1657 | page_cache_release(page); |
3ef94daa | 1658 | } |
05394f39 | 1659 | obj->dirty = 0; |
673a394b | 1660 | |
9da3da66 CW |
1661 | sg_free_table(obj->pages); |
1662 | kfree(obj->pages); | |
37e680a1 | 1663 | } |
6c085a72 | 1664 | |
dd624afd | 1665 | int |
37e680a1 CW |
1666 | i915_gem_object_put_pages(struct drm_i915_gem_object *obj) |
1667 | { | |
1668 | const struct drm_i915_gem_object_ops *ops = obj->ops; | |
1669 | ||
2f745ad3 | 1670 | if (obj->pages == NULL) |
37e680a1 CW |
1671 | return 0; |
1672 | ||
a5570178 CW |
1673 | if (obj->pages_pin_count) |
1674 | return -EBUSY; | |
1675 | ||
9843877d | 1676 | BUG_ON(i915_gem_obj_bound_any(obj)); |
3e123027 | 1677 | |
a2165e31 CW |
1678 | /* ->put_pages might need to allocate memory for the bit17 swizzle |
1679 | * array, hence protect them from being reaped by removing them from gtt | |
1680 | * lists early. */ | |
35c20a60 | 1681 | list_del(&obj->global_list); |
a2165e31 | 1682 | |
37e680a1 | 1683 | ops->put_pages(obj); |
05394f39 | 1684 | obj->pages = NULL; |
37e680a1 | 1685 | |
6c085a72 CW |
1686 | if (i915_gem_object_is_purgeable(obj)) |
1687 | i915_gem_object_truncate(obj); | |
1688 | ||
1689 | return 0; | |
1690 | } | |
1691 | ||
1692 | static long | |
93927ca5 DV |
1693 | __i915_gem_shrink(struct drm_i915_private *dev_priv, long target, |
1694 | bool purgeable_only) | |
6c085a72 | 1695 | { |
57094f82 | 1696 | struct list_head still_bound_list; |
6c085a72 CW |
1697 | struct drm_i915_gem_object *obj, *next; |
1698 | long count = 0; | |
1699 | ||
1700 | list_for_each_entry_safe(obj, next, | |
1701 | &dev_priv->mm.unbound_list, | |
35c20a60 | 1702 | global_list) { |
93927ca5 | 1703 | if ((i915_gem_object_is_purgeable(obj) || !purgeable_only) && |
37e680a1 | 1704 | i915_gem_object_put_pages(obj) == 0) { |
6c085a72 CW |
1705 | count += obj->base.size >> PAGE_SHIFT; |
1706 | if (count >= target) | |
1707 | return count; | |
1708 | } | |
1709 | } | |
1710 | ||
57094f82 CW |
1711 | /* |
1712 | * As we may completely rewrite the bound list whilst unbinding | |
1713 | * (due to retiring requests) we have to strictly process only | |
1714 | * one element of the list at the time, and recheck the list | |
1715 | * on every iteration. | |
1716 | */ | |
1717 | INIT_LIST_HEAD(&still_bound_list); | |
1718 | while (count < target && !list_empty(&dev_priv->mm.bound_list)) { | |
07fe0b12 | 1719 | struct i915_vma *vma, *v; |
80dcfdbd | 1720 | |
57094f82 CW |
1721 | obj = list_first_entry(&dev_priv->mm.bound_list, |
1722 | typeof(*obj), global_list); | |
1723 | list_move_tail(&obj->global_list, &still_bound_list); | |
1724 | ||
80dcfdbd BW |
1725 | if (!i915_gem_object_is_purgeable(obj) && purgeable_only) |
1726 | continue; | |
1727 | ||
57094f82 CW |
1728 | /* |
1729 | * Hold a reference whilst we unbind this object, as we may | |
1730 | * end up waiting for and retiring requests. This might | |
1731 | * release the final reference (held by the active list) | |
1732 | * and result in the object being freed from under us. | |
1733 | * in this object being freed. | |
1734 | * | |
1735 | * Note 1: Shrinking the bound list is special since only active | |
1736 | * (and hence bound objects) can contain such limbo objects, so | |
1737 | * we don't need special tricks for shrinking the unbound list. | |
1738 | * The only other place where we have to be careful with active | |
1739 | * objects suddenly disappearing due to retiring requests is the | |
1740 | * eviction code. | |
1741 | * | |
1742 | * Note 2: Even though the bound list doesn't hold a reference | |
1743 | * to the object we can safely grab one here: The final object | |
1744 | * unreferencing and the bound_list are both protected by the | |
1745 | * dev->struct_mutex and so we won't ever be able to observe an | |
1746 | * object on the bound_list with a reference count equals 0. | |
1747 | */ | |
1748 | drm_gem_object_reference(&obj->base); | |
1749 | ||
07fe0b12 BW |
1750 | list_for_each_entry_safe(vma, v, &obj->vma_list, vma_link) |
1751 | if (i915_vma_unbind(vma)) | |
1752 | break; | |
80dcfdbd | 1753 | |
57094f82 | 1754 | if (i915_gem_object_put_pages(obj) == 0) |
6c085a72 | 1755 | count += obj->base.size >> PAGE_SHIFT; |
57094f82 CW |
1756 | |
1757 | drm_gem_object_unreference(&obj->base); | |
6c085a72 | 1758 | } |
57094f82 | 1759 | list_splice(&still_bound_list, &dev_priv->mm.bound_list); |
6c085a72 CW |
1760 | |
1761 | return count; | |
1762 | } | |
1763 | ||
93927ca5 DV |
1764 | static long |
1765 | i915_gem_purge(struct drm_i915_private *dev_priv, long target) | |
1766 | { | |
1767 | return __i915_gem_shrink(dev_priv, target, true); | |
1768 | } | |
1769 | ||
7dc19d5a | 1770 | static long |
6c085a72 CW |
1771 | i915_gem_shrink_all(struct drm_i915_private *dev_priv) |
1772 | { | |
1773 | struct drm_i915_gem_object *obj, *next; | |
7dc19d5a | 1774 | long freed = 0; |
6c085a72 CW |
1775 | |
1776 | i915_gem_evict_everything(dev_priv->dev); | |
1777 | ||
35c20a60 | 1778 | list_for_each_entry_safe(obj, next, &dev_priv->mm.unbound_list, |
7dc19d5a DC |
1779 | global_list) { |
1780 | if (obj->pages_pin_count == 0) | |
1781 | freed += obj->base.size >> PAGE_SHIFT; | |
37e680a1 | 1782 | i915_gem_object_put_pages(obj); |
7dc19d5a DC |
1783 | } |
1784 | return freed; | |
225067ee DV |
1785 | } |
1786 | ||
37e680a1 | 1787 | static int |
6c085a72 | 1788 | i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj) |
e5281ccd | 1789 | { |
6c085a72 | 1790 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
e5281ccd CW |
1791 | int page_count, i; |
1792 | struct address_space *mapping; | |
9da3da66 CW |
1793 | struct sg_table *st; |
1794 | struct scatterlist *sg; | |
90797e6d | 1795 | struct sg_page_iter sg_iter; |
e5281ccd | 1796 | struct page *page; |
90797e6d | 1797 | unsigned long last_pfn = 0; /* suppress gcc warning */ |
6c085a72 | 1798 | gfp_t gfp; |
e5281ccd | 1799 | |
6c085a72 CW |
1800 | /* Assert that the object is not currently in any GPU domain. As it |
1801 | * wasn't in the GTT, there shouldn't be any way it could have been in | |
1802 | * a GPU cache | |
1803 | */ | |
1804 | BUG_ON(obj->base.read_domains & I915_GEM_GPU_DOMAINS); | |
1805 | BUG_ON(obj->base.write_domain & I915_GEM_GPU_DOMAINS); | |
1806 | ||
9da3da66 CW |
1807 | st = kmalloc(sizeof(*st), GFP_KERNEL); |
1808 | if (st == NULL) | |
1809 | return -ENOMEM; | |
1810 | ||
05394f39 | 1811 | page_count = obj->base.size / PAGE_SIZE; |
9da3da66 | 1812 | if (sg_alloc_table(st, page_count, GFP_KERNEL)) { |
9da3da66 | 1813 | kfree(st); |
e5281ccd | 1814 | return -ENOMEM; |
9da3da66 | 1815 | } |
e5281ccd | 1816 | |
9da3da66 CW |
1817 | /* Get the list of pages out of our struct file. They'll be pinned |
1818 | * at this point until we release them. | |
1819 | * | |
1820 | * Fail silently without starting the shrinker | |
1821 | */ | |
496ad9aa | 1822 | mapping = file_inode(obj->base.filp)->i_mapping; |
6c085a72 | 1823 | gfp = mapping_gfp_mask(mapping); |
caf49191 | 1824 | gfp |= __GFP_NORETRY | __GFP_NOWARN | __GFP_NO_KSWAPD; |
6c085a72 | 1825 | gfp &= ~(__GFP_IO | __GFP_WAIT); |
90797e6d ID |
1826 | sg = st->sgl; |
1827 | st->nents = 0; | |
1828 | for (i = 0; i < page_count; i++) { | |
6c085a72 CW |
1829 | page = shmem_read_mapping_page_gfp(mapping, i, gfp); |
1830 | if (IS_ERR(page)) { | |
1831 | i915_gem_purge(dev_priv, page_count); | |
1832 | page = shmem_read_mapping_page_gfp(mapping, i, gfp); | |
1833 | } | |
1834 | if (IS_ERR(page)) { | |
1835 | /* We've tried hard to allocate the memory by reaping | |
1836 | * our own buffer, now let the real VM do its job and | |
1837 | * go down in flames if truly OOM. | |
1838 | */ | |
caf49191 | 1839 | gfp &= ~(__GFP_NORETRY | __GFP_NOWARN | __GFP_NO_KSWAPD); |
6c085a72 CW |
1840 | gfp |= __GFP_IO | __GFP_WAIT; |
1841 | ||
1842 | i915_gem_shrink_all(dev_priv); | |
1843 | page = shmem_read_mapping_page_gfp(mapping, i, gfp); | |
1844 | if (IS_ERR(page)) | |
1845 | goto err_pages; | |
1846 | ||
caf49191 | 1847 | gfp |= __GFP_NORETRY | __GFP_NOWARN | __GFP_NO_KSWAPD; |
6c085a72 CW |
1848 | gfp &= ~(__GFP_IO | __GFP_WAIT); |
1849 | } | |
426729dc KRW |
1850 | #ifdef CONFIG_SWIOTLB |
1851 | if (swiotlb_nr_tbl()) { | |
1852 | st->nents++; | |
1853 | sg_set_page(sg, page, PAGE_SIZE, 0); | |
1854 | sg = sg_next(sg); | |
1855 | continue; | |
1856 | } | |
1857 | #endif | |
90797e6d ID |
1858 | if (!i || page_to_pfn(page) != last_pfn + 1) { |
1859 | if (i) | |
1860 | sg = sg_next(sg); | |
1861 | st->nents++; | |
1862 | sg_set_page(sg, page, PAGE_SIZE, 0); | |
1863 | } else { | |
1864 | sg->length += PAGE_SIZE; | |
1865 | } | |
1866 | last_pfn = page_to_pfn(page); | |
e5281ccd | 1867 | } |
426729dc KRW |
1868 | #ifdef CONFIG_SWIOTLB |
1869 | if (!swiotlb_nr_tbl()) | |
1870 | #endif | |
1871 | sg_mark_end(sg); | |
74ce6b6c CW |
1872 | obj->pages = st; |
1873 | ||
6dacfd2f | 1874 | if (i915_gem_object_needs_bit17_swizzle(obj)) |
e5281ccd CW |
1875 | i915_gem_object_do_bit_17_swizzle(obj); |
1876 | ||
1877 | return 0; | |
1878 | ||
1879 | err_pages: | |
90797e6d ID |
1880 | sg_mark_end(sg); |
1881 | for_each_sg_page(st->sgl, &sg_iter, st->nents, 0) | |
2db76d7c | 1882 | page_cache_release(sg_page_iter_page(&sg_iter)); |
9da3da66 CW |
1883 | sg_free_table(st); |
1884 | kfree(st); | |
e5281ccd | 1885 | return PTR_ERR(page); |
673a394b EA |
1886 | } |
1887 | ||
37e680a1 CW |
1888 | /* Ensure that the associated pages are gathered from the backing storage |
1889 | * and pinned into our object. i915_gem_object_get_pages() may be called | |
1890 | * multiple times before they are released by a single call to | |
1891 | * i915_gem_object_put_pages() - once the pages are no longer referenced | |
1892 | * either as a result of memory pressure (reaping pages under the shrinker) | |
1893 | * or as the object is itself released. | |
1894 | */ | |
1895 | int | |
1896 | i915_gem_object_get_pages(struct drm_i915_gem_object *obj) | |
1897 | { | |
1898 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; | |
1899 | const struct drm_i915_gem_object_ops *ops = obj->ops; | |
1900 | int ret; | |
1901 | ||
2f745ad3 | 1902 | if (obj->pages) |
37e680a1 CW |
1903 | return 0; |
1904 | ||
43e28f09 CW |
1905 | if (obj->madv != I915_MADV_WILLNEED) { |
1906 | DRM_ERROR("Attempting to obtain a purgeable object\n"); | |
1907 | return -EINVAL; | |
1908 | } | |
1909 | ||
a5570178 CW |
1910 | BUG_ON(obj->pages_pin_count); |
1911 | ||
37e680a1 CW |
1912 | ret = ops->get_pages(obj); |
1913 | if (ret) | |
1914 | return ret; | |
1915 | ||
35c20a60 | 1916 | list_add_tail(&obj->global_list, &dev_priv->mm.unbound_list); |
37e680a1 | 1917 | return 0; |
673a394b EA |
1918 | } |
1919 | ||
54cf91dc | 1920 | void |
05394f39 | 1921 | i915_gem_object_move_to_active(struct drm_i915_gem_object *obj, |
9d773091 | 1922 | struct intel_ring_buffer *ring) |
673a394b | 1923 | { |
05394f39 | 1924 | struct drm_device *dev = obj->base.dev; |
69dc4987 | 1925 | struct drm_i915_private *dev_priv = dev->dev_private; |
9d773091 | 1926 | u32 seqno = intel_ring_get_seqno(ring); |
617dbe27 | 1927 | |
852835f3 | 1928 | BUG_ON(ring == NULL); |
02978ff5 CW |
1929 | if (obj->ring != ring && obj->last_write_seqno) { |
1930 | /* Keep the seqno relative to the current ring */ | |
1931 | obj->last_write_seqno = seqno; | |
1932 | } | |
05394f39 | 1933 | obj->ring = ring; |
673a394b EA |
1934 | |
1935 | /* Add a reference if we're newly entering the active list. */ | |
05394f39 CW |
1936 | if (!obj->active) { |
1937 | drm_gem_object_reference(&obj->base); | |
1938 | obj->active = 1; | |
673a394b | 1939 | } |
e35a41de | 1940 | |
05394f39 | 1941 | list_move_tail(&obj->ring_list, &ring->active_list); |
caea7476 | 1942 | |
0201f1ec | 1943 | obj->last_read_seqno = seqno; |
caea7476 | 1944 | |
7dd49065 | 1945 | if (obj->fenced_gpu_access) { |
caea7476 | 1946 | obj->last_fenced_seqno = seqno; |
caea7476 | 1947 | |
7dd49065 CW |
1948 | /* Bump MRU to take account of the delayed flush */ |
1949 | if (obj->fence_reg != I915_FENCE_REG_NONE) { | |
1950 | struct drm_i915_fence_reg *reg; | |
1951 | ||
1952 | reg = &dev_priv->fence_regs[obj->fence_reg]; | |
1953 | list_move_tail(®->lru_list, | |
1954 | &dev_priv->mm.fence_list); | |
1955 | } | |
caea7476 CW |
1956 | } |
1957 | } | |
1958 | ||
1959 | static void | |
caea7476 | 1960 | i915_gem_object_move_to_inactive(struct drm_i915_gem_object *obj) |
ce44b0ea | 1961 | { |
ca191b13 BW |
1962 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
1963 | struct i915_address_space *ggtt_vm = &dev_priv->gtt.base; | |
1964 | struct i915_vma *vma = i915_gem_obj_to_vma(obj, ggtt_vm); | |
ce44b0ea | 1965 | |
65ce3027 | 1966 | BUG_ON(obj->base.write_domain & ~I915_GEM_GPU_DOMAINS); |
05394f39 | 1967 | BUG_ON(!obj->active); |
caea7476 | 1968 | |
ca191b13 | 1969 | list_move_tail(&vma->mm_list, &ggtt_vm->inactive_list); |
caea7476 | 1970 | |
65ce3027 | 1971 | list_del_init(&obj->ring_list); |
caea7476 CW |
1972 | obj->ring = NULL; |
1973 | ||
65ce3027 CW |
1974 | obj->last_read_seqno = 0; |
1975 | obj->last_write_seqno = 0; | |
1976 | obj->base.write_domain = 0; | |
1977 | ||
1978 | obj->last_fenced_seqno = 0; | |
caea7476 | 1979 | obj->fenced_gpu_access = false; |
caea7476 CW |
1980 | |
1981 | obj->active = 0; | |
1982 | drm_gem_object_unreference(&obj->base); | |
1983 | ||
1984 | WARN_ON(i915_verify_lists(dev)); | |
ce44b0ea | 1985 | } |
673a394b | 1986 | |
9d773091 | 1987 | static int |
fca26bb4 | 1988 | i915_gem_init_seqno(struct drm_device *dev, u32 seqno) |
53d227f2 | 1989 | { |
9d773091 CW |
1990 | struct drm_i915_private *dev_priv = dev->dev_private; |
1991 | struct intel_ring_buffer *ring; | |
1992 | int ret, i, j; | |
53d227f2 | 1993 | |
107f27a5 | 1994 | /* Carefully retire all requests without writing to the rings */ |
9d773091 | 1995 | for_each_ring(ring, dev_priv, i) { |
107f27a5 CW |
1996 | ret = intel_ring_idle(ring); |
1997 | if (ret) | |
1998 | return ret; | |
9d773091 | 1999 | } |
9d773091 | 2000 | i915_gem_retire_requests(dev); |
107f27a5 CW |
2001 | |
2002 | /* Finally reset hw state */ | |
9d773091 | 2003 | for_each_ring(ring, dev_priv, i) { |
fca26bb4 | 2004 | intel_ring_init_seqno(ring, seqno); |
498d2ac1 | 2005 | |
9d773091 CW |
2006 | for (j = 0; j < ARRAY_SIZE(ring->sync_seqno); j++) |
2007 | ring->sync_seqno[j] = 0; | |
2008 | } | |
53d227f2 | 2009 | |
9d773091 | 2010 | return 0; |
53d227f2 DV |
2011 | } |
2012 | ||
fca26bb4 MK |
2013 | int i915_gem_set_seqno(struct drm_device *dev, u32 seqno) |
2014 | { | |
2015 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2016 | int ret; | |
2017 | ||
2018 | if (seqno == 0) | |
2019 | return -EINVAL; | |
2020 | ||
2021 | /* HWS page needs to be set less than what we | |
2022 | * will inject to ring | |
2023 | */ | |
2024 | ret = i915_gem_init_seqno(dev, seqno - 1); | |
2025 | if (ret) | |
2026 | return ret; | |
2027 | ||
2028 | /* Carefully set the last_seqno value so that wrap | |
2029 | * detection still works | |
2030 | */ | |
2031 | dev_priv->next_seqno = seqno; | |
2032 | dev_priv->last_seqno = seqno - 1; | |
2033 | if (dev_priv->last_seqno == 0) | |
2034 | dev_priv->last_seqno--; | |
2035 | ||
2036 | return 0; | |
2037 | } | |
2038 | ||
9d773091 CW |
2039 | int |
2040 | i915_gem_get_seqno(struct drm_device *dev, u32 *seqno) | |
53d227f2 | 2041 | { |
9d773091 CW |
2042 | struct drm_i915_private *dev_priv = dev->dev_private; |
2043 | ||
2044 | /* reserve 0 for non-seqno */ | |
2045 | if (dev_priv->next_seqno == 0) { | |
fca26bb4 | 2046 | int ret = i915_gem_init_seqno(dev, 0); |
9d773091 CW |
2047 | if (ret) |
2048 | return ret; | |
53d227f2 | 2049 | |
9d773091 CW |
2050 | dev_priv->next_seqno = 1; |
2051 | } | |
53d227f2 | 2052 | |
f72b3435 | 2053 | *seqno = dev_priv->last_seqno = dev_priv->next_seqno++; |
9d773091 | 2054 | return 0; |
53d227f2 DV |
2055 | } |
2056 | ||
0025c077 MK |
2057 | int __i915_add_request(struct intel_ring_buffer *ring, |
2058 | struct drm_file *file, | |
7d736f4f | 2059 | struct drm_i915_gem_object *obj, |
0025c077 | 2060 | u32 *out_seqno) |
673a394b | 2061 | { |
db53a302 | 2062 | drm_i915_private_t *dev_priv = ring->dev->dev_private; |
acb868d3 | 2063 | struct drm_i915_gem_request *request; |
7d736f4f | 2064 | u32 request_ring_position, request_start; |
673a394b | 2065 | int was_empty; |
3cce469c CW |
2066 | int ret; |
2067 | ||
7d736f4f | 2068 | request_start = intel_ring_get_tail(ring); |
cc889e0f DV |
2069 | /* |
2070 | * Emit any outstanding flushes - execbuf can fail to emit the flush | |
2071 | * after having emitted the batchbuffer command. Hence we need to fix | |
2072 | * things up similar to emitting the lazy request. The difference here | |
2073 | * is that the flush _must_ happen before the next request, no matter | |
2074 | * what. | |
2075 | */ | |
a7b9761d CW |
2076 | ret = intel_ring_flush_all_caches(ring); |
2077 | if (ret) | |
2078 | return ret; | |
cc889e0f | 2079 | |
3c0e234c CW |
2080 | request = ring->preallocated_lazy_request; |
2081 | if (WARN_ON(request == NULL)) | |
acb868d3 | 2082 | return -ENOMEM; |
cc889e0f | 2083 | |
a71d8d94 CW |
2084 | /* Record the position of the start of the request so that |
2085 | * should we detect the updated seqno part-way through the | |
2086 | * GPU processing the request, we never over-estimate the | |
2087 | * position of the head. | |
2088 | */ | |
2089 | request_ring_position = intel_ring_get_tail(ring); | |
2090 | ||
9d773091 | 2091 | ret = ring->add_request(ring); |
3c0e234c | 2092 | if (ret) |
3bb73aba | 2093 | return ret; |
673a394b | 2094 | |
9d773091 | 2095 | request->seqno = intel_ring_get_seqno(ring); |
852835f3 | 2096 | request->ring = ring; |
7d736f4f | 2097 | request->head = request_start; |
a71d8d94 | 2098 | request->tail = request_ring_position; |
7d736f4f MK |
2099 | |
2100 | /* Whilst this request exists, batch_obj will be on the | |
2101 | * active_list, and so will hold the active reference. Only when this | |
2102 | * request is retired will the the batch_obj be moved onto the | |
2103 | * inactive_list and lose its active reference. Hence we do not need | |
2104 | * to explicitly hold another reference here. | |
2105 | */ | |
9a7e0c2a | 2106 | request->batch_obj = obj; |
0e50e96b | 2107 | |
9a7e0c2a CW |
2108 | /* Hold a reference to the current context so that we can inspect |
2109 | * it later in case a hangcheck error event fires. | |
2110 | */ | |
2111 | request->ctx = ring->last_context; | |
0e50e96b MK |
2112 | if (request->ctx) |
2113 | i915_gem_context_reference(request->ctx); | |
2114 | ||
673a394b | 2115 | request->emitted_jiffies = jiffies; |
852835f3 ZN |
2116 | was_empty = list_empty(&ring->request_list); |
2117 | list_add_tail(&request->list, &ring->request_list); | |
3bb73aba | 2118 | request->file_priv = NULL; |
852835f3 | 2119 | |
db53a302 CW |
2120 | if (file) { |
2121 | struct drm_i915_file_private *file_priv = file->driver_priv; | |
2122 | ||
1c25595f | 2123 | spin_lock(&file_priv->mm.lock); |
f787a5f5 | 2124 | request->file_priv = file_priv; |
b962442e | 2125 | list_add_tail(&request->client_list, |
f787a5f5 | 2126 | &file_priv->mm.request_list); |
1c25595f | 2127 | spin_unlock(&file_priv->mm.lock); |
b962442e | 2128 | } |
673a394b | 2129 | |
9d773091 | 2130 | trace_i915_gem_request_add(ring, request->seqno); |
1823521d | 2131 | ring->outstanding_lazy_seqno = 0; |
3c0e234c | 2132 | ring->preallocated_lazy_request = NULL; |
db53a302 | 2133 | |
db1b76ca | 2134 | if (!dev_priv->ums.mm_suspended) { |
10cd45b6 MK |
2135 | i915_queue_hangcheck(ring->dev); |
2136 | ||
f047e395 | 2137 | if (was_empty) { |
b3b079db | 2138 | queue_delayed_work(dev_priv->wq, |
bcb45086 CW |
2139 | &dev_priv->mm.retire_work, |
2140 | round_jiffies_up_relative(HZ)); | |
f047e395 CW |
2141 | intel_mark_busy(dev_priv->dev); |
2142 | } | |
f65d9421 | 2143 | } |
cc889e0f | 2144 | |
acb868d3 | 2145 | if (out_seqno) |
9d773091 | 2146 | *out_seqno = request->seqno; |
3cce469c | 2147 | return 0; |
673a394b EA |
2148 | } |
2149 | ||
f787a5f5 CW |
2150 | static inline void |
2151 | i915_gem_request_remove_from_client(struct drm_i915_gem_request *request) | |
673a394b | 2152 | { |
1c25595f | 2153 | struct drm_i915_file_private *file_priv = request->file_priv; |
673a394b | 2154 | |
1c25595f CW |
2155 | if (!file_priv) |
2156 | return; | |
1c5d22f7 | 2157 | |
1c25595f | 2158 | spin_lock(&file_priv->mm.lock); |
09bfa517 HRK |
2159 | if (request->file_priv) { |
2160 | list_del(&request->client_list); | |
2161 | request->file_priv = NULL; | |
2162 | } | |
1c25595f | 2163 | spin_unlock(&file_priv->mm.lock); |
673a394b | 2164 | } |
673a394b | 2165 | |
d1ccbb5d BW |
2166 | static bool i915_head_inside_object(u32 acthd, struct drm_i915_gem_object *obj, |
2167 | struct i915_address_space *vm) | |
aa60c664 | 2168 | { |
d1ccbb5d BW |
2169 | if (acthd >= i915_gem_obj_offset(obj, vm) && |
2170 | acthd < i915_gem_obj_offset(obj, vm) + obj->base.size) | |
aa60c664 MK |
2171 | return true; |
2172 | ||
2173 | return false; | |
2174 | } | |
2175 | ||
2176 | static bool i915_head_inside_request(const u32 acthd_unmasked, | |
2177 | const u32 request_start, | |
2178 | const u32 request_end) | |
2179 | { | |
2180 | const u32 acthd = acthd_unmasked & HEAD_ADDR; | |
2181 | ||
2182 | if (request_start < request_end) { | |
2183 | if (acthd >= request_start && acthd < request_end) | |
2184 | return true; | |
2185 | } else if (request_start > request_end) { | |
2186 | if (acthd >= request_start || acthd < request_end) | |
2187 | return true; | |
2188 | } | |
2189 | ||
2190 | return false; | |
2191 | } | |
2192 | ||
d1ccbb5d BW |
2193 | static struct i915_address_space * |
2194 | request_to_vm(struct drm_i915_gem_request *request) | |
2195 | { | |
2196 | struct drm_i915_private *dev_priv = request->ring->dev->dev_private; | |
2197 | struct i915_address_space *vm; | |
2198 | ||
2199 | vm = &dev_priv->gtt.base; | |
2200 | ||
2201 | return vm; | |
2202 | } | |
2203 | ||
aa60c664 MK |
2204 | static bool i915_request_guilty(struct drm_i915_gem_request *request, |
2205 | const u32 acthd, bool *inside) | |
2206 | { | |
2207 | /* There is a possibility that unmasked head address | |
2208 | * pointing inside the ring, matches the batch_obj address range. | |
2209 | * However this is extremely unlikely. | |
2210 | */ | |
aa60c664 | 2211 | if (request->batch_obj) { |
d1ccbb5d BW |
2212 | if (i915_head_inside_object(acthd, request->batch_obj, |
2213 | request_to_vm(request))) { | |
aa60c664 MK |
2214 | *inside = true; |
2215 | return true; | |
2216 | } | |
2217 | } | |
2218 | ||
2219 | if (i915_head_inside_request(acthd, request->head, request->tail)) { | |
2220 | *inside = false; | |
2221 | return true; | |
2222 | } | |
2223 | ||
2224 | return false; | |
2225 | } | |
2226 | ||
be62acb4 MK |
2227 | static bool i915_context_is_banned(const struct i915_ctx_hang_stats *hs) |
2228 | { | |
2229 | const unsigned long elapsed = get_seconds() - hs->guilty_ts; | |
2230 | ||
2231 | if (hs->banned) | |
2232 | return true; | |
2233 | ||
2234 | if (elapsed <= DRM_I915_CTX_BAN_PERIOD) { | |
2235 | DRM_ERROR("context hanging too fast, declaring banned!\n"); | |
2236 | return true; | |
2237 | } | |
2238 | ||
2239 | return false; | |
2240 | } | |
2241 | ||
aa60c664 MK |
2242 | static void i915_set_reset_status(struct intel_ring_buffer *ring, |
2243 | struct drm_i915_gem_request *request, | |
2244 | u32 acthd) | |
2245 | { | |
2246 | struct i915_ctx_hang_stats *hs = NULL; | |
2247 | bool inside, guilty; | |
d1ccbb5d | 2248 | unsigned long offset = 0; |
aa60c664 MK |
2249 | |
2250 | /* Innocent until proven guilty */ | |
2251 | guilty = false; | |
2252 | ||
d1ccbb5d BW |
2253 | if (request->batch_obj) |
2254 | offset = i915_gem_obj_offset(request->batch_obj, | |
2255 | request_to_vm(request)); | |
2256 | ||
f2f4d82f | 2257 | if (ring->hangcheck.action != HANGCHECK_WAIT && |
aa60c664 | 2258 | i915_request_guilty(request, acthd, &inside)) { |
f343c5f6 | 2259 | DRM_ERROR("%s hung %s bo (0x%lx ctx %d) at 0x%x\n", |
aa60c664 MK |
2260 | ring->name, |
2261 | inside ? "inside" : "flushing", | |
d1ccbb5d | 2262 | offset, |
aa60c664 MK |
2263 | request->ctx ? request->ctx->id : 0, |
2264 | acthd); | |
2265 | ||
2266 | guilty = true; | |
2267 | } | |
2268 | ||
2269 | /* If contexts are disabled or this is the default context, use | |
2270 | * file_priv->reset_state | |
2271 | */ | |
2272 | if (request->ctx && request->ctx->id != DEFAULT_CONTEXT_ID) | |
2273 | hs = &request->ctx->hang_stats; | |
2274 | else if (request->file_priv) | |
2275 | hs = &request->file_priv->hang_stats; | |
2276 | ||
2277 | if (hs) { | |
be62acb4 MK |
2278 | if (guilty) { |
2279 | hs->banned = i915_context_is_banned(hs); | |
aa60c664 | 2280 | hs->batch_active++; |
be62acb4 MK |
2281 | hs->guilty_ts = get_seconds(); |
2282 | } else { | |
aa60c664 | 2283 | hs->batch_pending++; |
be62acb4 | 2284 | } |
aa60c664 MK |
2285 | } |
2286 | } | |
2287 | ||
0e50e96b MK |
2288 | static void i915_gem_free_request(struct drm_i915_gem_request *request) |
2289 | { | |
2290 | list_del(&request->list); | |
2291 | i915_gem_request_remove_from_client(request); | |
2292 | ||
2293 | if (request->ctx) | |
2294 | i915_gem_context_unreference(request->ctx); | |
2295 | ||
2296 | kfree(request); | |
2297 | } | |
2298 | ||
dfaae392 CW |
2299 | static void i915_gem_reset_ring_lists(struct drm_i915_private *dev_priv, |
2300 | struct intel_ring_buffer *ring) | |
9375e446 | 2301 | { |
aa60c664 MK |
2302 | u32 completed_seqno; |
2303 | u32 acthd; | |
2304 | ||
2305 | acthd = intel_ring_get_active_head(ring); | |
2306 | completed_seqno = ring->get_seqno(ring, false); | |
2307 | ||
dfaae392 CW |
2308 | while (!list_empty(&ring->request_list)) { |
2309 | struct drm_i915_gem_request *request; | |
673a394b | 2310 | |
dfaae392 CW |
2311 | request = list_first_entry(&ring->request_list, |
2312 | struct drm_i915_gem_request, | |
2313 | list); | |
de151cf6 | 2314 | |
aa60c664 MK |
2315 | if (request->seqno > completed_seqno) |
2316 | i915_set_reset_status(ring, request, acthd); | |
2317 | ||
0e50e96b | 2318 | i915_gem_free_request(request); |
dfaae392 | 2319 | } |
673a394b | 2320 | |
dfaae392 | 2321 | while (!list_empty(&ring->active_list)) { |
05394f39 | 2322 | struct drm_i915_gem_object *obj; |
9375e446 | 2323 | |
05394f39 CW |
2324 | obj = list_first_entry(&ring->active_list, |
2325 | struct drm_i915_gem_object, | |
2326 | ring_list); | |
9375e446 | 2327 | |
05394f39 | 2328 | i915_gem_object_move_to_inactive(obj); |
673a394b EA |
2329 | } |
2330 | } | |
2331 | ||
19b2dbde | 2332 | void i915_gem_restore_fences(struct drm_device *dev) |
312817a3 CW |
2333 | { |
2334 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2335 | int i; | |
2336 | ||
4b9de737 | 2337 | for (i = 0; i < dev_priv->num_fence_regs; i++) { |
312817a3 | 2338 | struct drm_i915_fence_reg *reg = &dev_priv->fence_regs[i]; |
7d2cb39c | 2339 | |
94a335db DV |
2340 | /* |
2341 | * Commit delayed tiling changes if we have an object still | |
2342 | * attached to the fence, otherwise just clear the fence. | |
2343 | */ | |
2344 | if (reg->obj) { | |
2345 | i915_gem_object_update_fence(reg->obj, reg, | |
2346 | reg->obj->tiling_mode); | |
2347 | } else { | |
2348 | i915_gem_write_fence(dev, i, NULL); | |
2349 | } | |
312817a3 CW |
2350 | } |
2351 | } | |
2352 | ||
069efc1d | 2353 | void i915_gem_reset(struct drm_device *dev) |
673a394b | 2354 | { |
77f01230 | 2355 | struct drm_i915_private *dev_priv = dev->dev_private; |
b4519513 | 2356 | struct intel_ring_buffer *ring; |
1ec14ad3 | 2357 | int i; |
673a394b | 2358 | |
b4519513 CW |
2359 | for_each_ring(ring, dev_priv, i) |
2360 | i915_gem_reset_ring_lists(dev_priv, ring); | |
dfaae392 | 2361 | |
19b2dbde | 2362 | i915_gem_restore_fences(dev); |
673a394b EA |
2363 | } |
2364 | ||
2365 | /** | |
2366 | * This function clears the request list as sequence numbers are passed. | |
2367 | */ | |
a71d8d94 | 2368 | void |
db53a302 | 2369 | i915_gem_retire_requests_ring(struct intel_ring_buffer *ring) |
673a394b | 2370 | { |
673a394b EA |
2371 | uint32_t seqno; |
2372 | ||
db53a302 | 2373 | if (list_empty(&ring->request_list)) |
6c0594a3 KW |
2374 | return; |
2375 | ||
db53a302 | 2376 | WARN_ON(i915_verify_lists(ring->dev)); |
673a394b | 2377 | |
b2eadbc8 | 2378 | seqno = ring->get_seqno(ring, true); |
1ec14ad3 | 2379 | |
852835f3 | 2380 | while (!list_empty(&ring->request_list)) { |
673a394b | 2381 | struct drm_i915_gem_request *request; |
673a394b | 2382 | |
852835f3 | 2383 | request = list_first_entry(&ring->request_list, |
673a394b EA |
2384 | struct drm_i915_gem_request, |
2385 | list); | |
673a394b | 2386 | |
dfaae392 | 2387 | if (!i915_seqno_passed(seqno, request->seqno)) |
b84d5f0c CW |
2388 | break; |
2389 | ||
db53a302 | 2390 | trace_i915_gem_request_retire(ring, request->seqno); |
a71d8d94 CW |
2391 | /* We know the GPU must have read the request to have |
2392 | * sent us the seqno + interrupt, so use the position | |
2393 | * of tail of the request to update the last known position | |
2394 | * of the GPU head. | |
2395 | */ | |
2396 | ring->last_retired_head = request->tail; | |
b84d5f0c | 2397 | |
0e50e96b | 2398 | i915_gem_free_request(request); |
b84d5f0c | 2399 | } |
673a394b | 2400 | |
b84d5f0c CW |
2401 | /* Move any buffers on the active list that are no longer referenced |
2402 | * by the ringbuffer to the flushing/inactive lists as appropriate. | |
2403 | */ | |
2404 | while (!list_empty(&ring->active_list)) { | |
05394f39 | 2405 | struct drm_i915_gem_object *obj; |
b84d5f0c | 2406 | |
0206e353 | 2407 | obj = list_first_entry(&ring->active_list, |
05394f39 CW |
2408 | struct drm_i915_gem_object, |
2409 | ring_list); | |
673a394b | 2410 | |
0201f1ec | 2411 | if (!i915_seqno_passed(seqno, obj->last_read_seqno)) |
673a394b | 2412 | break; |
b84d5f0c | 2413 | |
65ce3027 | 2414 | i915_gem_object_move_to_inactive(obj); |
673a394b | 2415 | } |
9d34e5db | 2416 | |
db53a302 CW |
2417 | if (unlikely(ring->trace_irq_seqno && |
2418 | i915_seqno_passed(seqno, ring->trace_irq_seqno))) { | |
1ec14ad3 | 2419 | ring->irq_put(ring); |
db53a302 | 2420 | ring->trace_irq_seqno = 0; |
9d34e5db | 2421 | } |
23bc5982 | 2422 | |
db53a302 | 2423 | WARN_ON(i915_verify_lists(ring->dev)); |
673a394b EA |
2424 | } |
2425 | ||
b09a1fec CW |
2426 | void |
2427 | i915_gem_retire_requests(struct drm_device *dev) | |
2428 | { | |
2429 | drm_i915_private_t *dev_priv = dev->dev_private; | |
b4519513 | 2430 | struct intel_ring_buffer *ring; |
1ec14ad3 | 2431 | int i; |
b09a1fec | 2432 | |
b4519513 CW |
2433 | for_each_ring(ring, dev_priv, i) |
2434 | i915_gem_retire_requests_ring(ring); | |
b09a1fec CW |
2435 | } |
2436 | ||
75ef9da2 | 2437 | static void |
673a394b EA |
2438 | i915_gem_retire_work_handler(struct work_struct *work) |
2439 | { | |
2440 | drm_i915_private_t *dev_priv; | |
2441 | struct drm_device *dev; | |
b4519513 | 2442 | struct intel_ring_buffer *ring; |
0a58705b CW |
2443 | bool idle; |
2444 | int i; | |
673a394b EA |
2445 | |
2446 | dev_priv = container_of(work, drm_i915_private_t, | |
2447 | mm.retire_work.work); | |
2448 | dev = dev_priv->dev; | |
2449 | ||
891b48cf CW |
2450 | /* Come back later if the device is busy... */ |
2451 | if (!mutex_trylock(&dev->struct_mutex)) { | |
bcb45086 CW |
2452 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, |
2453 | round_jiffies_up_relative(HZ)); | |
891b48cf CW |
2454 | return; |
2455 | } | |
673a394b | 2456 | |
b09a1fec | 2457 | i915_gem_retire_requests(dev); |
673a394b | 2458 | |
0a58705b CW |
2459 | /* Send a periodic flush down the ring so we don't hold onto GEM |
2460 | * objects indefinitely. | |
673a394b | 2461 | */ |
0a58705b | 2462 | idle = true; |
b4519513 | 2463 | for_each_ring(ring, dev_priv, i) { |
3bb73aba | 2464 | if (ring->gpu_caches_dirty) |
0025c077 | 2465 | i915_add_request(ring, NULL); |
0a58705b CW |
2466 | |
2467 | idle &= list_empty(&ring->request_list); | |
673a394b EA |
2468 | } |
2469 | ||
db1b76ca | 2470 | if (!dev_priv->ums.mm_suspended && !idle) |
bcb45086 CW |
2471 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, |
2472 | round_jiffies_up_relative(HZ)); | |
f047e395 CW |
2473 | if (idle) |
2474 | intel_mark_idle(dev); | |
0a58705b | 2475 | |
673a394b | 2476 | mutex_unlock(&dev->struct_mutex); |
673a394b EA |
2477 | } |
2478 | ||
30dfebf3 DV |
2479 | /** |
2480 | * Ensures that an object will eventually get non-busy by flushing any required | |
2481 | * write domains, emitting any outstanding lazy request and retiring and | |
2482 | * completed requests. | |
2483 | */ | |
2484 | static int | |
2485 | i915_gem_object_flush_active(struct drm_i915_gem_object *obj) | |
2486 | { | |
2487 | int ret; | |
2488 | ||
2489 | if (obj->active) { | |
0201f1ec | 2490 | ret = i915_gem_check_olr(obj->ring, obj->last_read_seqno); |
30dfebf3 DV |
2491 | if (ret) |
2492 | return ret; | |
2493 | ||
30dfebf3 DV |
2494 | i915_gem_retire_requests_ring(obj->ring); |
2495 | } | |
2496 | ||
2497 | return 0; | |
2498 | } | |
2499 | ||
23ba4fd0 BW |
2500 | /** |
2501 | * i915_gem_wait_ioctl - implements DRM_IOCTL_I915_GEM_WAIT | |
2502 | * @DRM_IOCTL_ARGS: standard ioctl arguments | |
2503 | * | |
2504 | * Returns 0 if successful, else an error is returned with the remaining time in | |
2505 | * the timeout parameter. | |
2506 | * -ETIME: object is still busy after timeout | |
2507 | * -ERESTARTSYS: signal interrupted the wait | |
2508 | * -ENONENT: object doesn't exist | |
2509 | * Also possible, but rare: | |
2510 | * -EAGAIN: GPU wedged | |
2511 | * -ENOMEM: damn | |
2512 | * -ENODEV: Internal IRQ fail | |
2513 | * -E?: The add request failed | |
2514 | * | |
2515 | * The wait ioctl with a timeout of 0 reimplements the busy ioctl. With any | |
2516 | * non-zero timeout parameter the wait ioctl will wait for the given number of | |
2517 | * nanoseconds on an object becoming unbusy. Since the wait itself does so | |
2518 | * without holding struct_mutex the object may become re-busied before this | |
2519 | * function completes. A similar but shorter * race condition exists in the busy | |
2520 | * ioctl | |
2521 | */ | |
2522 | int | |
2523 | i915_gem_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *file) | |
2524 | { | |
f69061be | 2525 | drm_i915_private_t *dev_priv = dev->dev_private; |
23ba4fd0 BW |
2526 | struct drm_i915_gem_wait *args = data; |
2527 | struct drm_i915_gem_object *obj; | |
2528 | struct intel_ring_buffer *ring = NULL; | |
eac1f14f | 2529 | struct timespec timeout_stack, *timeout = NULL; |
f69061be | 2530 | unsigned reset_counter; |
23ba4fd0 BW |
2531 | u32 seqno = 0; |
2532 | int ret = 0; | |
2533 | ||
eac1f14f BW |
2534 | if (args->timeout_ns >= 0) { |
2535 | timeout_stack = ns_to_timespec(args->timeout_ns); | |
2536 | timeout = &timeout_stack; | |
2537 | } | |
23ba4fd0 BW |
2538 | |
2539 | ret = i915_mutex_lock_interruptible(dev); | |
2540 | if (ret) | |
2541 | return ret; | |
2542 | ||
2543 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->bo_handle)); | |
2544 | if (&obj->base == NULL) { | |
2545 | mutex_unlock(&dev->struct_mutex); | |
2546 | return -ENOENT; | |
2547 | } | |
2548 | ||
30dfebf3 DV |
2549 | /* Need to make sure the object gets inactive eventually. */ |
2550 | ret = i915_gem_object_flush_active(obj); | |
23ba4fd0 BW |
2551 | if (ret) |
2552 | goto out; | |
2553 | ||
2554 | if (obj->active) { | |
0201f1ec | 2555 | seqno = obj->last_read_seqno; |
23ba4fd0 BW |
2556 | ring = obj->ring; |
2557 | } | |
2558 | ||
2559 | if (seqno == 0) | |
2560 | goto out; | |
2561 | ||
23ba4fd0 BW |
2562 | /* Do this after OLR check to make sure we make forward progress polling |
2563 | * on this IOCTL with a 0 timeout (like busy ioctl) | |
2564 | */ | |
2565 | if (!args->timeout_ns) { | |
2566 | ret = -ETIME; | |
2567 | goto out; | |
2568 | } | |
2569 | ||
2570 | drm_gem_object_unreference(&obj->base); | |
f69061be | 2571 | reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter); |
23ba4fd0 BW |
2572 | mutex_unlock(&dev->struct_mutex); |
2573 | ||
f69061be | 2574 | ret = __wait_seqno(ring, seqno, reset_counter, true, timeout); |
4f42f4ef | 2575 | if (timeout) |
eac1f14f | 2576 | args->timeout_ns = timespec_to_ns(timeout); |
23ba4fd0 BW |
2577 | return ret; |
2578 | ||
2579 | out: | |
2580 | drm_gem_object_unreference(&obj->base); | |
2581 | mutex_unlock(&dev->struct_mutex); | |
2582 | return ret; | |
2583 | } | |
2584 | ||
5816d648 BW |
2585 | /** |
2586 | * i915_gem_object_sync - sync an object to a ring. | |
2587 | * | |
2588 | * @obj: object which may be in use on another ring. | |
2589 | * @to: ring we wish to use the object on. May be NULL. | |
2590 | * | |
2591 | * This code is meant to abstract object synchronization with the GPU. | |
2592 | * Calling with NULL implies synchronizing the object with the CPU | |
2593 | * rather than a particular GPU ring. | |
2594 | * | |
2595 | * Returns 0 if successful, else propagates up the lower layer error. | |
2596 | */ | |
2911a35b BW |
2597 | int |
2598 | i915_gem_object_sync(struct drm_i915_gem_object *obj, | |
2599 | struct intel_ring_buffer *to) | |
2600 | { | |
2601 | struct intel_ring_buffer *from = obj->ring; | |
2602 | u32 seqno; | |
2603 | int ret, idx; | |
2604 | ||
2605 | if (from == NULL || to == from) | |
2606 | return 0; | |
2607 | ||
5816d648 | 2608 | if (to == NULL || !i915_semaphore_is_enabled(obj->base.dev)) |
0201f1ec | 2609 | return i915_gem_object_wait_rendering(obj, false); |
2911a35b BW |
2610 | |
2611 | idx = intel_ring_sync_index(from, to); | |
2612 | ||
0201f1ec | 2613 | seqno = obj->last_read_seqno; |
2911a35b BW |
2614 | if (seqno <= from->sync_seqno[idx]) |
2615 | return 0; | |
2616 | ||
b4aca010 BW |
2617 | ret = i915_gem_check_olr(obj->ring, seqno); |
2618 | if (ret) | |
2619 | return ret; | |
2911a35b | 2620 | |
1500f7ea | 2621 | ret = to->sync_to(to, from, seqno); |
e3a5a225 | 2622 | if (!ret) |
7b01e260 MK |
2623 | /* We use last_read_seqno because sync_to() |
2624 | * might have just caused seqno wrap under | |
2625 | * the radar. | |
2626 | */ | |
2627 | from->sync_seqno[idx] = obj->last_read_seqno; | |
2911a35b | 2628 | |
e3a5a225 | 2629 | return ret; |
2911a35b BW |
2630 | } |
2631 | ||
b5ffc9bc CW |
2632 | static void i915_gem_object_finish_gtt(struct drm_i915_gem_object *obj) |
2633 | { | |
2634 | u32 old_write_domain, old_read_domains; | |
2635 | ||
b5ffc9bc CW |
2636 | /* Force a pagefault for domain tracking on next user access */ |
2637 | i915_gem_release_mmap(obj); | |
2638 | ||
b97c3d9c KP |
2639 | if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0) |
2640 | return; | |
2641 | ||
97c809fd CW |
2642 | /* Wait for any direct GTT access to complete */ |
2643 | mb(); | |
2644 | ||
b5ffc9bc CW |
2645 | old_read_domains = obj->base.read_domains; |
2646 | old_write_domain = obj->base.write_domain; | |
2647 | ||
2648 | obj->base.read_domains &= ~I915_GEM_DOMAIN_GTT; | |
2649 | obj->base.write_domain &= ~I915_GEM_DOMAIN_GTT; | |
2650 | ||
2651 | trace_i915_gem_object_change_domain(obj, | |
2652 | old_read_domains, | |
2653 | old_write_domain); | |
2654 | } | |
2655 | ||
07fe0b12 | 2656 | int i915_vma_unbind(struct i915_vma *vma) |
673a394b | 2657 | { |
07fe0b12 | 2658 | struct drm_i915_gem_object *obj = vma->obj; |
7bddb01f | 2659 | drm_i915_private_t *dev_priv = obj->base.dev->dev_private; |
43e28f09 | 2660 | int ret; |
673a394b | 2661 | |
b93dab6e DV |
2662 | /* For now we only ever use 1 vma per object */ |
2663 | WARN_ON(!list_is_singular(&obj->vma_list)); | |
2664 | ||
07fe0b12 | 2665 | if (list_empty(&vma->vma_link)) |
673a394b EA |
2666 | return 0; |
2667 | ||
0ff501cb DV |
2668 | if (!drm_mm_node_allocated(&vma->node)) { |
2669 | i915_gem_vma_destroy(vma); | |
2670 | ||
2671 | return 0; | |
2672 | } | |
433544bd | 2673 | |
31d8d651 CW |
2674 | if (obj->pin_count) |
2675 | return -EBUSY; | |
673a394b | 2676 | |
c4670ad0 CW |
2677 | BUG_ON(obj->pages == NULL); |
2678 | ||
a8198eea | 2679 | ret = i915_gem_object_finish_gpu(obj); |
1488fc08 | 2680 | if (ret) |
a8198eea CW |
2681 | return ret; |
2682 | /* Continue on if we fail due to EIO, the GPU is hung so we | |
2683 | * should be safe and we need to cleanup or else we might | |
2684 | * cause memory corruption through use-after-free. | |
2685 | */ | |
2686 | ||
b5ffc9bc | 2687 | i915_gem_object_finish_gtt(obj); |
5323fd04 | 2688 | |
96b47b65 | 2689 | /* release the fence reg _after_ flushing */ |
d9e86c0e | 2690 | ret = i915_gem_object_put_fence(obj); |
1488fc08 | 2691 | if (ret) |
d9e86c0e | 2692 | return ret; |
96b47b65 | 2693 | |
07fe0b12 | 2694 | trace_i915_vma_unbind(vma); |
db53a302 | 2695 | |
74898d7e DV |
2696 | if (obj->has_global_gtt_mapping) |
2697 | i915_gem_gtt_unbind_object(obj); | |
7bddb01f DV |
2698 | if (obj->has_aliasing_ppgtt_mapping) { |
2699 | i915_ppgtt_unbind_object(dev_priv->mm.aliasing_ppgtt, obj); | |
2700 | obj->has_aliasing_ppgtt_mapping = 0; | |
2701 | } | |
74163907 | 2702 | i915_gem_gtt_finish_object(obj); |
401c29f6 | 2703 | i915_gem_object_unpin_pages(obj); |
7bddb01f | 2704 | |
ca191b13 | 2705 | list_del(&vma->mm_list); |
75e9e915 | 2706 | /* Avoid an unnecessary call to unbind on rebind. */ |
5cacaac7 BW |
2707 | if (i915_is_ggtt(vma->vm)) |
2708 | obj->map_and_fenceable = true; | |
673a394b | 2709 | |
2f633156 | 2710 | drm_mm_remove_node(&vma->node); |
433544bd | 2711 | |
2f633156 BW |
2712 | i915_gem_vma_destroy(vma); |
2713 | ||
2714 | /* Since the unbound list is global, only move to that list if | |
b93dab6e | 2715 | * no more VMAs exist. */ |
2f633156 BW |
2716 | if (list_empty(&obj->vma_list)) |
2717 | list_move_tail(&obj->global_list, &dev_priv->mm.unbound_list); | |
673a394b | 2718 | |
88241785 | 2719 | return 0; |
54cf91dc CW |
2720 | } |
2721 | ||
07fe0b12 BW |
2722 | /** |
2723 | * Unbinds an object from the global GTT aperture. | |
2724 | */ | |
2725 | int | |
2726 | i915_gem_object_ggtt_unbind(struct drm_i915_gem_object *obj) | |
2727 | { | |
2728 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; | |
2729 | struct i915_address_space *ggtt = &dev_priv->gtt.base; | |
2730 | ||
58e73e15 | 2731 | if (!i915_gem_obj_ggtt_bound(obj)) |
07fe0b12 BW |
2732 | return 0; |
2733 | ||
2734 | if (obj->pin_count) | |
2735 | return -EBUSY; | |
2736 | ||
2737 | BUG_ON(obj->pages == NULL); | |
2738 | ||
2739 | return i915_vma_unbind(i915_gem_obj_to_vma(obj, ggtt)); | |
2740 | } | |
2741 | ||
b2da9fe5 | 2742 | int i915_gpu_idle(struct drm_device *dev) |
4df2faf4 DV |
2743 | { |
2744 | drm_i915_private_t *dev_priv = dev->dev_private; | |
b4519513 | 2745 | struct intel_ring_buffer *ring; |
1ec14ad3 | 2746 | int ret, i; |
4df2faf4 | 2747 | |
4df2faf4 | 2748 | /* Flush everything onto the inactive list. */ |
b4519513 | 2749 | for_each_ring(ring, dev_priv, i) { |
b6c7488d BW |
2750 | ret = i915_switch_context(ring, NULL, DEFAULT_CONTEXT_ID); |
2751 | if (ret) | |
2752 | return ret; | |
2753 | ||
3e960501 | 2754 | ret = intel_ring_idle(ring); |
1ec14ad3 CW |
2755 | if (ret) |
2756 | return ret; | |
2757 | } | |
4df2faf4 | 2758 | |
8a1a49f9 | 2759 | return 0; |
4df2faf4 DV |
2760 | } |
2761 | ||
9ce079e4 CW |
2762 | static void i965_write_fence_reg(struct drm_device *dev, int reg, |
2763 | struct drm_i915_gem_object *obj) | |
de151cf6 | 2764 | { |
de151cf6 | 2765 | drm_i915_private_t *dev_priv = dev->dev_private; |
56c844e5 ID |
2766 | int fence_reg; |
2767 | int fence_pitch_shift; | |
de151cf6 | 2768 | |
56c844e5 ID |
2769 | if (INTEL_INFO(dev)->gen >= 6) { |
2770 | fence_reg = FENCE_REG_SANDYBRIDGE_0; | |
2771 | fence_pitch_shift = SANDYBRIDGE_FENCE_PITCH_SHIFT; | |
2772 | } else { | |
2773 | fence_reg = FENCE_REG_965_0; | |
2774 | fence_pitch_shift = I965_FENCE_PITCH_SHIFT; | |
2775 | } | |
2776 | ||
d18b9619 CW |
2777 | fence_reg += reg * 8; |
2778 | ||
2779 | /* To w/a incoherency with non-atomic 64-bit register updates, | |
2780 | * we split the 64-bit update into two 32-bit writes. In order | |
2781 | * for a partial fence not to be evaluated between writes, we | |
2782 | * precede the update with write to turn off the fence register, | |
2783 | * and only enable the fence as the last step. | |
2784 | * | |
2785 | * For extra levels of paranoia, we make sure each step lands | |
2786 | * before applying the next step. | |
2787 | */ | |
2788 | I915_WRITE(fence_reg, 0); | |
2789 | POSTING_READ(fence_reg); | |
2790 | ||
9ce079e4 | 2791 | if (obj) { |
f343c5f6 | 2792 | u32 size = i915_gem_obj_ggtt_size(obj); |
d18b9619 | 2793 | uint64_t val; |
de151cf6 | 2794 | |
f343c5f6 | 2795 | val = (uint64_t)((i915_gem_obj_ggtt_offset(obj) + size - 4096) & |
9ce079e4 | 2796 | 0xfffff000) << 32; |
f343c5f6 | 2797 | val |= i915_gem_obj_ggtt_offset(obj) & 0xfffff000; |
56c844e5 | 2798 | val |= (uint64_t)((obj->stride / 128) - 1) << fence_pitch_shift; |
9ce079e4 CW |
2799 | if (obj->tiling_mode == I915_TILING_Y) |
2800 | val |= 1 << I965_FENCE_TILING_Y_SHIFT; | |
2801 | val |= I965_FENCE_REG_VALID; | |
c6642782 | 2802 | |
d18b9619 CW |
2803 | I915_WRITE(fence_reg + 4, val >> 32); |
2804 | POSTING_READ(fence_reg + 4); | |
2805 | ||
2806 | I915_WRITE(fence_reg + 0, val); | |
2807 | POSTING_READ(fence_reg); | |
2808 | } else { | |
2809 | I915_WRITE(fence_reg + 4, 0); | |
2810 | POSTING_READ(fence_reg + 4); | |
2811 | } | |
de151cf6 JB |
2812 | } |
2813 | ||
9ce079e4 CW |
2814 | static void i915_write_fence_reg(struct drm_device *dev, int reg, |
2815 | struct drm_i915_gem_object *obj) | |
de151cf6 | 2816 | { |
de151cf6 | 2817 | drm_i915_private_t *dev_priv = dev->dev_private; |
9ce079e4 | 2818 | u32 val; |
de151cf6 | 2819 | |
9ce079e4 | 2820 | if (obj) { |
f343c5f6 | 2821 | u32 size = i915_gem_obj_ggtt_size(obj); |
9ce079e4 CW |
2822 | int pitch_val; |
2823 | int tile_width; | |
c6642782 | 2824 | |
f343c5f6 | 2825 | WARN((i915_gem_obj_ggtt_offset(obj) & ~I915_FENCE_START_MASK) || |
9ce079e4 | 2826 | (size & -size) != size || |
f343c5f6 BW |
2827 | (i915_gem_obj_ggtt_offset(obj) & (size - 1)), |
2828 | "object 0x%08lx [fenceable? %d] not 1M or pot-size (0x%08x) aligned\n", | |
2829 | i915_gem_obj_ggtt_offset(obj), obj->map_and_fenceable, size); | |
c6642782 | 2830 | |
9ce079e4 CW |
2831 | if (obj->tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev)) |
2832 | tile_width = 128; | |
2833 | else | |
2834 | tile_width = 512; | |
2835 | ||
2836 | /* Note: pitch better be a power of two tile widths */ | |
2837 | pitch_val = obj->stride / tile_width; | |
2838 | pitch_val = ffs(pitch_val) - 1; | |
2839 | ||
f343c5f6 | 2840 | val = i915_gem_obj_ggtt_offset(obj); |
9ce079e4 CW |
2841 | if (obj->tiling_mode == I915_TILING_Y) |
2842 | val |= 1 << I830_FENCE_TILING_Y_SHIFT; | |
2843 | val |= I915_FENCE_SIZE_BITS(size); | |
2844 | val |= pitch_val << I830_FENCE_PITCH_SHIFT; | |
2845 | val |= I830_FENCE_REG_VALID; | |
2846 | } else | |
2847 | val = 0; | |
2848 | ||
2849 | if (reg < 8) | |
2850 | reg = FENCE_REG_830_0 + reg * 4; | |
2851 | else | |
2852 | reg = FENCE_REG_945_8 + (reg - 8) * 4; | |
2853 | ||
2854 | I915_WRITE(reg, val); | |
2855 | POSTING_READ(reg); | |
de151cf6 JB |
2856 | } |
2857 | ||
9ce079e4 CW |
2858 | static void i830_write_fence_reg(struct drm_device *dev, int reg, |
2859 | struct drm_i915_gem_object *obj) | |
de151cf6 | 2860 | { |
de151cf6 | 2861 | drm_i915_private_t *dev_priv = dev->dev_private; |
de151cf6 | 2862 | uint32_t val; |
de151cf6 | 2863 | |
9ce079e4 | 2864 | if (obj) { |
f343c5f6 | 2865 | u32 size = i915_gem_obj_ggtt_size(obj); |
9ce079e4 | 2866 | uint32_t pitch_val; |
de151cf6 | 2867 | |
f343c5f6 | 2868 | WARN((i915_gem_obj_ggtt_offset(obj) & ~I830_FENCE_START_MASK) || |
9ce079e4 | 2869 | (size & -size) != size || |
f343c5f6 BW |
2870 | (i915_gem_obj_ggtt_offset(obj) & (size - 1)), |
2871 | "object 0x%08lx not 512K or pot-size 0x%08x aligned\n", | |
2872 | i915_gem_obj_ggtt_offset(obj), size); | |
e76a16de | 2873 | |
9ce079e4 CW |
2874 | pitch_val = obj->stride / 128; |
2875 | pitch_val = ffs(pitch_val) - 1; | |
de151cf6 | 2876 | |
f343c5f6 | 2877 | val = i915_gem_obj_ggtt_offset(obj); |
9ce079e4 CW |
2878 | if (obj->tiling_mode == I915_TILING_Y) |
2879 | val |= 1 << I830_FENCE_TILING_Y_SHIFT; | |
2880 | val |= I830_FENCE_SIZE_BITS(size); | |
2881 | val |= pitch_val << I830_FENCE_PITCH_SHIFT; | |
2882 | val |= I830_FENCE_REG_VALID; | |
2883 | } else | |
2884 | val = 0; | |
c6642782 | 2885 | |
9ce079e4 CW |
2886 | I915_WRITE(FENCE_REG_830_0 + reg * 4, val); |
2887 | POSTING_READ(FENCE_REG_830_0 + reg * 4); | |
2888 | } | |
2889 | ||
d0a57789 CW |
2890 | inline static bool i915_gem_object_needs_mb(struct drm_i915_gem_object *obj) |
2891 | { | |
2892 | return obj && obj->base.read_domains & I915_GEM_DOMAIN_GTT; | |
2893 | } | |
2894 | ||
9ce079e4 CW |
2895 | static void i915_gem_write_fence(struct drm_device *dev, int reg, |
2896 | struct drm_i915_gem_object *obj) | |
2897 | { | |
d0a57789 CW |
2898 | struct drm_i915_private *dev_priv = dev->dev_private; |
2899 | ||
2900 | /* Ensure that all CPU reads are completed before installing a fence | |
2901 | * and all writes before removing the fence. | |
2902 | */ | |
2903 | if (i915_gem_object_needs_mb(dev_priv->fence_regs[reg].obj)) | |
2904 | mb(); | |
2905 | ||
94a335db DV |
2906 | WARN(obj && (!obj->stride || !obj->tiling_mode), |
2907 | "bogus fence setup with stride: 0x%x, tiling mode: %i\n", | |
2908 | obj->stride, obj->tiling_mode); | |
2909 | ||
9ce079e4 CW |
2910 | switch (INTEL_INFO(dev)->gen) { |
2911 | case 7: | |
56c844e5 | 2912 | case 6: |
9ce079e4 CW |
2913 | case 5: |
2914 | case 4: i965_write_fence_reg(dev, reg, obj); break; | |
2915 | case 3: i915_write_fence_reg(dev, reg, obj); break; | |
2916 | case 2: i830_write_fence_reg(dev, reg, obj); break; | |
7dbf9d6e | 2917 | default: BUG(); |
9ce079e4 | 2918 | } |
d0a57789 CW |
2919 | |
2920 | /* And similarly be paranoid that no direct access to this region | |
2921 | * is reordered to before the fence is installed. | |
2922 | */ | |
2923 | if (i915_gem_object_needs_mb(obj)) | |
2924 | mb(); | |
de151cf6 JB |
2925 | } |
2926 | ||
61050808 CW |
2927 | static inline int fence_number(struct drm_i915_private *dev_priv, |
2928 | struct drm_i915_fence_reg *fence) | |
2929 | { | |
2930 | return fence - dev_priv->fence_regs; | |
2931 | } | |
2932 | ||
2933 | static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj, | |
2934 | struct drm_i915_fence_reg *fence, | |
2935 | bool enable) | |
2936 | { | |
2dc8aae0 | 2937 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
46a0b638 CW |
2938 | int reg = fence_number(dev_priv, fence); |
2939 | ||
2940 | i915_gem_write_fence(obj->base.dev, reg, enable ? obj : NULL); | |
61050808 CW |
2941 | |
2942 | if (enable) { | |
46a0b638 | 2943 | obj->fence_reg = reg; |
61050808 CW |
2944 | fence->obj = obj; |
2945 | list_move_tail(&fence->lru_list, &dev_priv->mm.fence_list); | |
2946 | } else { | |
2947 | obj->fence_reg = I915_FENCE_REG_NONE; | |
2948 | fence->obj = NULL; | |
2949 | list_del_init(&fence->lru_list); | |
2950 | } | |
94a335db | 2951 | obj->fence_dirty = false; |
61050808 CW |
2952 | } |
2953 | ||
d9e86c0e | 2954 | static int |
d0a57789 | 2955 | i915_gem_object_wait_fence(struct drm_i915_gem_object *obj) |
d9e86c0e | 2956 | { |
1c293ea3 | 2957 | if (obj->last_fenced_seqno) { |
86d5bc37 | 2958 | int ret = i915_wait_seqno(obj->ring, obj->last_fenced_seqno); |
18991845 CW |
2959 | if (ret) |
2960 | return ret; | |
d9e86c0e CW |
2961 | |
2962 | obj->last_fenced_seqno = 0; | |
d9e86c0e CW |
2963 | } |
2964 | ||
86d5bc37 | 2965 | obj->fenced_gpu_access = false; |
d9e86c0e CW |
2966 | return 0; |
2967 | } | |
2968 | ||
2969 | int | |
2970 | i915_gem_object_put_fence(struct drm_i915_gem_object *obj) | |
2971 | { | |
61050808 | 2972 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
f9c513e9 | 2973 | struct drm_i915_fence_reg *fence; |
d9e86c0e CW |
2974 | int ret; |
2975 | ||
d0a57789 | 2976 | ret = i915_gem_object_wait_fence(obj); |
d9e86c0e CW |
2977 | if (ret) |
2978 | return ret; | |
2979 | ||
61050808 CW |
2980 | if (obj->fence_reg == I915_FENCE_REG_NONE) |
2981 | return 0; | |
d9e86c0e | 2982 | |
f9c513e9 CW |
2983 | fence = &dev_priv->fence_regs[obj->fence_reg]; |
2984 | ||
61050808 | 2985 | i915_gem_object_fence_lost(obj); |
f9c513e9 | 2986 | i915_gem_object_update_fence(obj, fence, false); |
d9e86c0e CW |
2987 | |
2988 | return 0; | |
2989 | } | |
2990 | ||
2991 | static struct drm_i915_fence_reg * | |
a360bb1a | 2992 | i915_find_fence_reg(struct drm_device *dev) |
ae3db24a | 2993 | { |
ae3db24a | 2994 | struct drm_i915_private *dev_priv = dev->dev_private; |
8fe301ad | 2995 | struct drm_i915_fence_reg *reg, *avail; |
d9e86c0e | 2996 | int i; |
ae3db24a DV |
2997 | |
2998 | /* First try to find a free reg */ | |
d9e86c0e | 2999 | avail = NULL; |
ae3db24a DV |
3000 | for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) { |
3001 | reg = &dev_priv->fence_regs[i]; | |
3002 | if (!reg->obj) | |
d9e86c0e | 3003 | return reg; |
ae3db24a | 3004 | |
1690e1eb | 3005 | if (!reg->pin_count) |
d9e86c0e | 3006 | avail = reg; |
ae3db24a DV |
3007 | } |
3008 | ||
d9e86c0e CW |
3009 | if (avail == NULL) |
3010 | return NULL; | |
ae3db24a DV |
3011 | |
3012 | /* None available, try to steal one or wait for a user to finish */ | |
d9e86c0e | 3013 | list_for_each_entry(reg, &dev_priv->mm.fence_list, lru_list) { |
1690e1eb | 3014 | if (reg->pin_count) |
ae3db24a DV |
3015 | continue; |
3016 | ||
8fe301ad | 3017 | return reg; |
ae3db24a DV |
3018 | } |
3019 | ||
8fe301ad | 3020 | return NULL; |
ae3db24a DV |
3021 | } |
3022 | ||
de151cf6 | 3023 | /** |
9a5a53b3 | 3024 | * i915_gem_object_get_fence - set up fencing for an object |
de151cf6 JB |
3025 | * @obj: object to map through a fence reg |
3026 | * | |
3027 | * When mapping objects through the GTT, userspace wants to be able to write | |
3028 | * to them without having to worry about swizzling if the object is tiled. | |
de151cf6 JB |
3029 | * This function walks the fence regs looking for a free one for @obj, |
3030 | * stealing one if it can't find any. | |
3031 | * | |
3032 | * It then sets up the reg based on the object's properties: address, pitch | |
3033 | * and tiling format. | |
9a5a53b3 CW |
3034 | * |
3035 | * For an untiled surface, this removes any existing fence. | |
de151cf6 | 3036 | */ |
8c4b8c3f | 3037 | int |
06d98131 | 3038 | i915_gem_object_get_fence(struct drm_i915_gem_object *obj) |
de151cf6 | 3039 | { |
05394f39 | 3040 | struct drm_device *dev = obj->base.dev; |
79e53945 | 3041 | struct drm_i915_private *dev_priv = dev->dev_private; |
14415745 | 3042 | bool enable = obj->tiling_mode != I915_TILING_NONE; |
d9e86c0e | 3043 | struct drm_i915_fence_reg *reg; |
ae3db24a | 3044 | int ret; |
de151cf6 | 3045 | |
14415745 CW |
3046 | /* Have we updated the tiling parameters upon the object and so |
3047 | * will need to serialise the write to the associated fence register? | |
3048 | */ | |
5d82e3e6 | 3049 | if (obj->fence_dirty) { |
d0a57789 | 3050 | ret = i915_gem_object_wait_fence(obj); |
14415745 CW |
3051 | if (ret) |
3052 | return ret; | |
3053 | } | |
9a5a53b3 | 3054 | |
d9e86c0e | 3055 | /* Just update our place in the LRU if our fence is getting reused. */ |
05394f39 CW |
3056 | if (obj->fence_reg != I915_FENCE_REG_NONE) { |
3057 | reg = &dev_priv->fence_regs[obj->fence_reg]; | |
5d82e3e6 | 3058 | if (!obj->fence_dirty) { |
14415745 CW |
3059 | list_move_tail(®->lru_list, |
3060 | &dev_priv->mm.fence_list); | |
3061 | return 0; | |
3062 | } | |
3063 | } else if (enable) { | |
3064 | reg = i915_find_fence_reg(dev); | |
3065 | if (reg == NULL) | |
3066 | return -EDEADLK; | |
d9e86c0e | 3067 | |
14415745 CW |
3068 | if (reg->obj) { |
3069 | struct drm_i915_gem_object *old = reg->obj; | |
3070 | ||
d0a57789 | 3071 | ret = i915_gem_object_wait_fence(old); |
29c5a587 CW |
3072 | if (ret) |
3073 | return ret; | |
3074 | ||
14415745 | 3075 | i915_gem_object_fence_lost(old); |
29c5a587 | 3076 | } |
14415745 | 3077 | } else |
a09ba7fa | 3078 | return 0; |
a09ba7fa | 3079 | |
14415745 | 3080 | i915_gem_object_update_fence(obj, reg, enable); |
14415745 | 3081 | |
9ce079e4 | 3082 | return 0; |
de151cf6 JB |
3083 | } |
3084 | ||
42d6ab48 CW |
3085 | static bool i915_gem_valid_gtt_space(struct drm_device *dev, |
3086 | struct drm_mm_node *gtt_space, | |
3087 | unsigned long cache_level) | |
3088 | { | |
3089 | struct drm_mm_node *other; | |
3090 | ||
3091 | /* On non-LLC machines we have to be careful when putting differing | |
3092 | * types of snoopable memory together to avoid the prefetcher | |
4239ca77 | 3093 | * crossing memory domains and dying. |
42d6ab48 CW |
3094 | */ |
3095 | if (HAS_LLC(dev)) | |
3096 | return true; | |
3097 | ||
c6cfb325 | 3098 | if (!drm_mm_node_allocated(gtt_space)) |
42d6ab48 CW |
3099 | return true; |
3100 | ||
3101 | if (list_empty(>t_space->node_list)) | |
3102 | return true; | |
3103 | ||
3104 | other = list_entry(gtt_space->node_list.prev, struct drm_mm_node, node_list); | |
3105 | if (other->allocated && !other->hole_follows && other->color != cache_level) | |
3106 | return false; | |
3107 | ||
3108 | other = list_entry(gtt_space->node_list.next, struct drm_mm_node, node_list); | |
3109 | if (other->allocated && !gtt_space->hole_follows && other->color != cache_level) | |
3110 | return false; | |
3111 | ||
3112 | return true; | |
3113 | } | |
3114 | ||
3115 | static void i915_gem_verify_gtt(struct drm_device *dev) | |
3116 | { | |
3117 | #if WATCH_GTT | |
3118 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3119 | struct drm_i915_gem_object *obj; | |
3120 | int err = 0; | |
3121 | ||
35c20a60 | 3122 | list_for_each_entry(obj, &dev_priv->mm.gtt_list, global_list) { |
42d6ab48 CW |
3123 | if (obj->gtt_space == NULL) { |
3124 | printk(KERN_ERR "object found on GTT list with no space reserved\n"); | |
3125 | err++; | |
3126 | continue; | |
3127 | } | |
3128 | ||
3129 | if (obj->cache_level != obj->gtt_space->color) { | |
3130 | printk(KERN_ERR "object reserved space [%08lx, %08lx] with wrong color, cache_level=%x, color=%lx\n", | |
f343c5f6 BW |
3131 | i915_gem_obj_ggtt_offset(obj), |
3132 | i915_gem_obj_ggtt_offset(obj) + i915_gem_obj_ggtt_size(obj), | |
42d6ab48 CW |
3133 | obj->cache_level, |
3134 | obj->gtt_space->color); | |
3135 | err++; | |
3136 | continue; | |
3137 | } | |
3138 | ||
3139 | if (!i915_gem_valid_gtt_space(dev, | |
3140 | obj->gtt_space, | |
3141 | obj->cache_level)) { | |
3142 | printk(KERN_ERR "invalid GTT space found at [%08lx, %08lx] - color=%x\n", | |
f343c5f6 BW |
3143 | i915_gem_obj_ggtt_offset(obj), |
3144 | i915_gem_obj_ggtt_offset(obj) + i915_gem_obj_ggtt_size(obj), | |
42d6ab48 CW |
3145 | obj->cache_level); |
3146 | err++; | |
3147 | continue; | |
3148 | } | |
3149 | } | |
3150 | ||
3151 | WARN_ON(err); | |
3152 | #endif | |
3153 | } | |
3154 | ||
673a394b EA |
3155 | /** |
3156 | * Finds free space in the GTT aperture and binds the object there. | |
3157 | */ | |
3158 | static int | |
07fe0b12 BW |
3159 | i915_gem_object_bind_to_vm(struct drm_i915_gem_object *obj, |
3160 | struct i915_address_space *vm, | |
3161 | unsigned alignment, | |
3162 | bool map_and_fenceable, | |
3163 | bool nonblocking) | |
673a394b | 3164 | { |
05394f39 | 3165 | struct drm_device *dev = obj->base.dev; |
673a394b | 3166 | drm_i915_private_t *dev_priv = dev->dev_private; |
5e783301 | 3167 | u32 size, fence_size, fence_alignment, unfenced_alignment; |
07fe0b12 BW |
3168 | size_t gtt_max = |
3169 | map_and_fenceable ? dev_priv->gtt.mappable_end : vm->total; | |
2f633156 | 3170 | struct i915_vma *vma; |
07f73f69 | 3171 | int ret; |
673a394b | 3172 | |
e28f8711 CW |
3173 | fence_size = i915_gem_get_gtt_size(dev, |
3174 | obj->base.size, | |
3175 | obj->tiling_mode); | |
3176 | fence_alignment = i915_gem_get_gtt_alignment(dev, | |
3177 | obj->base.size, | |
d865110c | 3178 | obj->tiling_mode, true); |
e28f8711 | 3179 | unfenced_alignment = |
d865110c | 3180 | i915_gem_get_gtt_alignment(dev, |
e28f8711 | 3181 | obj->base.size, |
d865110c | 3182 | obj->tiling_mode, false); |
a00b10c3 | 3183 | |
673a394b | 3184 | if (alignment == 0) |
5e783301 DV |
3185 | alignment = map_and_fenceable ? fence_alignment : |
3186 | unfenced_alignment; | |
75e9e915 | 3187 | if (map_and_fenceable && alignment & (fence_alignment - 1)) { |
673a394b EA |
3188 | DRM_ERROR("Invalid object alignment requested %u\n", alignment); |
3189 | return -EINVAL; | |
3190 | } | |
3191 | ||
05394f39 | 3192 | size = map_and_fenceable ? fence_size : obj->base.size; |
a00b10c3 | 3193 | |
654fc607 CW |
3194 | /* If the object is bigger than the entire aperture, reject it early |
3195 | * before evicting everything in a vain attempt to find space. | |
3196 | */ | |
0a9ae0d7 | 3197 | if (obj->base.size > gtt_max) { |
3765f304 | 3198 | DRM_ERROR("Attempting to bind an object larger than the aperture: object=%zd > %s aperture=%zu\n", |
a36689cb CW |
3199 | obj->base.size, |
3200 | map_and_fenceable ? "mappable" : "total", | |
0a9ae0d7 | 3201 | gtt_max); |
654fc607 CW |
3202 | return -E2BIG; |
3203 | } | |
3204 | ||
37e680a1 | 3205 | ret = i915_gem_object_get_pages(obj); |
6c085a72 CW |
3206 | if (ret) |
3207 | return ret; | |
3208 | ||
fbdda6fb CW |
3209 | i915_gem_object_pin_pages(obj); |
3210 | ||
07fe0b12 | 3211 | BUG_ON(!i915_is_ggtt(vm)); |
07fe0b12 | 3212 | |
accfef2e | 3213 | vma = i915_gem_obj_lookup_or_create_vma(obj, vm); |
db473b36 | 3214 | if (IS_ERR(vma)) { |
bc6bc15b DV |
3215 | ret = PTR_ERR(vma); |
3216 | goto err_unpin; | |
2f633156 BW |
3217 | } |
3218 | ||
accfef2e BW |
3219 | /* For now we only ever use 1 vma per object */ |
3220 | WARN_ON(!list_is_singular(&obj->vma_list)); | |
3221 | ||
0a9ae0d7 | 3222 | search_free: |
07fe0b12 | 3223 | ret = drm_mm_insert_node_in_range_generic(&vm->mm, &vma->node, |
0a9ae0d7 | 3224 | size, alignment, |
31e5d7c6 DH |
3225 | obj->cache_level, 0, gtt_max, |
3226 | DRM_MM_SEARCH_DEFAULT); | |
dc9dd7a2 | 3227 | if (ret) { |
f6cd1f15 | 3228 | ret = i915_gem_evict_something(dev, vm, size, alignment, |
42d6ab48 | 3229 | obj->cache_level, |
86a1ee26 CW |
3230 | map_and_fenceable, |
3231 | nonblocking); | |
dc9dd7a2 CW |
3232 | if (ret == 0) |
3233 | goto search_free; | |
9731129c | 3234 | |
bc6bc15b | 3235 | goto err_free_vma; |
673a394b | 3236 | } |
2f633156 | 3237 | if (WARN_ON(!i915_gem_valid_gtt_space(dev, &vma->node, |
c6cfb325 | 3238 | obj->cache_level))) { |
2f633156 | 3239 | ret = -EINVAL; |
bc6bc15b | 3240 | goto err_remove_node; |
673a394b EA |
3241 | } |
3242 | ||
74163907 | 3243 | ret = i915_gem_gtt_prepare_object(obj); |
2f633156 | 3244 | if (ret) |
bc6bc15b | 3245 | goto err_remove_node; |
673a394b | 3246 | |
35c20a60 | 3247 | list_move_tail(&obj->global_list, &dev_priv->mm.bound_list); |
ca191b13 | 3248 | list_add_tail(&vma->mm_list, &vm->inactive_list); |
bf1a1092 | 3249 | |
4bd561b3 BW |
3250 | if (i915_is_ggtt(vm)) { |
3251 | bool mappable, fenceable; | |
a00b10c3 | 3252 | |
49987099 DV |
3253 | fenceable = (vma->node.size == fence_size && |
3254 | (vma->node.start & (fence_alignment - 1)) == 0); | |
4bd561b3 | 3255 | |
49987099 DV |
3256 | mappable = (vma->node.start + obj->base.size <= |
3257 | dev_priv->gtt.mappable_end); | |
a00b10c3 | 3258 | |
5cacaac7 | 3259 | obj->map_and_fenceable = mappable && fenceable; |
4bd561b3 | 3260 | } |
75e9e915 | 3261 | |
7ace7ef2 | 3262 | WARN_ON(map_and_fenceable && !obj->map_and_fenceable); |
75e9e915 | 3263 | |
07fe0b12 | 3264 | trace_i915_vma_bind(vma, map_and_fenceable); |
42d6ab48 | 3265 | i915_gem_verify_gtt(dev); |
673a394b | 3266 | return 0; |
2f633156 | 3267 | |
bc6bc15b | 3268 | err_remove_node: |
6286ef9b | 3269 | drm_mm_remove_node(&vma->node); |
bc6bc15b | 3270 | err_free_vma: |
2f633156 | 3271 | i915_gem_vma_destroy(vma); |
bc6bc15b | 3272 | err_unpin: |
2f633156 | 3273 | i915_gem_object_unpin_pages(obj); |
2f633156 | 3274 | return ret; |
673a394b EA |
3275 | } |
3276 | ||
000433b6 | 3277 | bool |
2c22569b CW |
3278 | i915_gem_clflush_object(struct drm_i915_gem_object *obj, |
3279 | bool force) | |
673a394b | 3280 | { |
673a394b EA |
3281 | /* If we don't have a page list set up, then we're not pinned |
3282 | * to GPU, and we can ignore the cache flush because it'll happen | |
3283 | * again at bind time. | |
3284 | */ | |
05394f39 | 3285 | if (obj->pages == NULL) |
000433b6 | 3286 | return false; |
673a394b | 3287 | |
769ce464 ID |
3288 | /* |
3289 | * Stolen memory is always coherent with the GPU as it is explicitly | |
3290 | * marked as wc by the system, or the system is cache-coherent. | |
3291 | */ | |
3292 | if (obj->stolen) | |
000433b6 | 3293 | return false; |
769ce464 | 3294 | |
9c23f7fc CW |
3295 | /* If the GPU is snooping the contents of the CPU cache, |
3296 | * we do not need to manually clear the CPU cache lines. However, | |
3297 | * the caches are only snooped when the render cache is | |
3298 | * flushed/invalidated. As we always have to emit invalidations | |
3299 | * and flushes when moving into and out of the RENDER domain, correct | |
3300 | * snooping behaviour occurs naturally as the result of our domain | |
3301 | * tracking. | |
3302 | */ | |
2c22569b | 3303 | if (!force && cpu_cache_is_coherent(obj->base.dev, obj->cache_level)) |
000433b6 | 3304 | return false; |
9c23f7fc | 3305 | |
1c5d22f7 | 3306 | trace_i915_gem_object_clflush(obj); |
9da3da66 | 3307 | drm_clflush_sg(obj->pages); |
000433b6 CW |
3308 | |
3309 | return true; | |
e47c68e9 EA |
3310 | } |
3311 | ||
3312 | /** Flushes the GTT write domain for the object if it's dirty. */ | |
3313 | static void | |
05394f39 | 3314 | i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj) |
e47c68e9 | 3315 | { |
1c5d22f7 CW |
3316 | uint32_t old_write_domain; |
3317 | ||
05394f39 | 3318 | if (obj->base.write_domain != I915_GEM_DOMAIN_GTT) |
e47c68e9 EA |
3319 | return; |
3320 | ||
63256ec5 | 3321 | /* No actual flushing is required for the GTT write domain. Writes |
e47c68e9 EA |
3322 | * to it immediately go to main memory as far as we know, so there's |
3323 | * no chipset flush. It also doesn't land in render cache. | |
63256ec5 CW |
3324 | * |
3325 | * However, we do have to enforce the order so that all writes through | |
3326 | * the GTT land before any writes to the device, such as updates to | |
3327 | * the GATT itself. | |
e47c68e9 | 3328 | */ |
63256ec5 CW |
3329 | wmb(); |
3330 | ||
05394f39 CW |
3331 | old_write_domain = obj->base.write_domain; |
3332 | obj->base.write_domain = 0; | |
1c5d22f7 CW |
3333 | |
3334 | trace_i915_gem_object_change_domain(obj, | |
05394f39 | 3335 | obj->base.read_domains, |
1c5d22f7 | 3336 | old_write_domain); |
e47c68e9 EA |
3337 | } |
3338 | ||
3339 | /** Flushes the CPU write domain for the object if it's dirty. */ | |
3340 | static void | |
2c22569b CW |
3341 | i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj, |
3342 | bool force) | |
e47c68e9 | 3343 | { |
1c5d22f7 | 3344 | uint32_t old_write_domain; |
e47c68e9 | 3345 | |
05394f39 | 3346 | if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) |
e47c68e9 EA |
3347 | return; |
3348 | ||
000433b6 CW |
3349 | if (i915_gem_clflush_object(obj, force)) |
3350 | i915_gem_chipset_flush(obj->base.dev); | |
3351 | ||
05394f39 CW |
3352 | old_write_domain = obj->base.write_domain; |
3353 | obj->base.write_domain = 0; | |
1c5d22f7 CW |
3354 | |
3355 | trace_i915_gem_object_change_domain(obj, | |
05394f39 | 3356 | obj->base.read_domains, |
1c5d22f7 | 3357 | old_write_domain); |
e47c68e9 EA |
3358 | } |
3359 | ||
2ef7eeaa EA |
3360 | /** |
3361 | * Moves a single object to the GTT read, and possibly write domain. | |
3362 | * | |
3363 | * This function returns when the move is complete, including waiting on | |
3364 | * flushes to occur. | |
3365 | */ | |
79e53945 | 3366 | int |
2021746e | 3367 | i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write) |
2ef7eeaa | 3368 | { |
8325a09d | 3369 | drm_i915_private_t *dev_priv = obj->base.dev->dev_private; |
1c5d22f7 | 3370 | uint32_t old_write_domain, old_read_domains; |
e47c68e9 | 3371 | int ret; |
2ef7eeaa | 3372 | |
02354392 | 3373 | /* Not valid to be called on unbound objects. */ |
9843877d | 3374 | if (!i915_gem_obj_bound_any(obj)) |
02354392 EA |
3375 | return -EINVAL; |
3376 | ||
8d7e3de1 CW |
3377 | if (obj->base.write_domain == I915_GEM_DOMAIN_GTT) |
3378 | return 0; | |
3379 | ||
0201f1ec | 3380 | ret = i915_gem_object_wait_rendering(obj, !write); |
88241785 CW |
3381 | if (ret) |
3382 | return ret; | |
3383 | ||
2c22569b | 3384 | i915_gem_object_flush_cpu_write_domain(obj, false); |
1c5d22f7 | 3385 | |
d0a57789 CW |
3386 | /* Serialise direct access to this object with the barriers for |
3387 | * coherent writes from the GPU, by effectively invalidating the | |
3388 | * GTT domain upon first access. | |
3389 | */ | |
3390 | if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0) | |
3391 | mb(); | |
3392 | ||
05394f39 CW |
3393 | old_write_domain = obj->base.write_domain; |
3394 | old_read_domains = obj->base.read_domains; | |
1c5d22f7 | 3395 | |
e47c68e9 EA |
3396 | /* It should now be out of any other write domains, and we can update |
3397 | * the domain values for our changes. | |
3398 | */ | |
05394f39 CW |
3399 | BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) != 0); |
3400 | obj->base.read_domains |= I915_GEM_DOMAIN_GTT; | |
e47c68e9 | 3401 | if (write) { |
05394f39 CW |
3402 | obj->base.read_domains = I915_GEM_DOMAIN_GTT; |
3403 | obj->base.write_domain = I915_GEM_DOMAIN_GTT; | |
3404 | obj->dirty = 1; | |
2ef7eeaa EA |
3405 | } |
3406 | ||
1c5d22f7 CW |
3407 | trace_i915_gem_object_change_domain(obj, |
3408 | old_read_domains, | |
3409 | old_write_domain); | |
3410 | ||
8325a09d | 3411 | /* And bump the LRU for this access */ |
ca191b13 BW |
3412 | if (i915_gem_object_is_inactive(obj)) { |
3413 | struct i915_vma *vma = i915_gem_obj_to_vma(obj, | |
3414 | &dev_priv->gtt.base); | |
3415 | if (vma) | |
3416 | list_move_tail(&vma->mm_list, | |
3417 | &dev_priv->gtt.base.inactive_list); | |
3418 | ||
3419 | } | |
8325a09d | 3420 | |
e47c68e9 EA |
3421 | return 0; |
3422 | } | |
3423 | ||
e4ffd173 CW |
3424 | int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj, |
3425 | enum i915_cache_level cache_level) | |
3426 | { | |
7bddb01f DV |
3427 | struct drm_device *dev = obj->base.dev; |
3428 | drm_i915_private_t *dev_priv = dev->dev_private; | |
3089c6f2 | 3429 | struct i915_vma *vma; |
e4ffd173 CW |
3430 | int ret; |
3431 | ||
3432 | if (obj->cache_level == cache_level) | |
3433 | return 0; | |
3434 | ||
3435 | if (obj->pin_count) { | |
3436 | DRM_DEBUG("can not change the cache level of pinned objects\n"); | |
3437 | return -EBUSY; | |
3438 | } | |
3439 | ||
3089c6f2 BW |
3440 | list_for_each_entry(vma, &obj->vma_list, vma_link) { |
3441 | if (!i915_gem_valid_gtt_space(dev, &vma->node, cache_level)) { | |
07fe0b12 | 3442 | ret = i915_vma_unbind(vma); |
3089c6f2 BW |
3443 | if (ret) |
3444 | return ret; | |
3445 | ||
3446 | break; | |
3447 | } | |
42d6ab48 CW |
3448 | } |
3449 | ||
3089c6f2 | 3450 | if (i915_gem_obj_bound_any(obj)) { |
e4ffd173 CW |
3451 | ret = i915_gem_object_finish_gpu(obj); |
3452 | if (ret) | |
3453 | return ret; | |
3454 | ||
3455 | i915_gem_object_finish_gtt(obj); | |
3456 | ||
3457 | /* Before SandyBridge, you could not use tiling or fence | |
3458 | * registers with snooped memory, so relinquish any fences | |
3459 | * currently pointing to our region in the aperture. | |
3460 | */ | |
42d6ab48 | 3461 | if (INTEL_INFO(dev)->gen < 6) { |
e4ffd173 CW |
3462 | ret = i915_gem_object_put_fence(obj); |
3463 | if (ret) | |
3464 | return ret; | |
3465 | } | |
3466 | ||
74898d7e DV |
3467 | if (obj->has_global_gtt_mapping) |
3468 | i915_gem_gtt_bind_object(obj, cache_level); | |
7bddb01f DV |
3469 | if (obj->has_aliasing_ppgtt_mapping) |
3470 | i915_ppgtt_bind_object(dev_priv->mm.aliasing_ppgtt, | |
3471 | obj, cache_level); | |
e4ffd173 CW |
3472 | } |
3473 | ||
2c22569b CW |
3474 | list_for_each_entry(vma, &obj->vma_list, vma_link) |
3475 | vma->node.color = cache_level; | |
3476 | obj->cache_level = cache_level; | |
3477 | ||
3478 | if (cpu_write_needs_clflush(obj)) { | |
e4ffd173 CW |
3479 | u32 old_read_domains, old_write_domain; |
3480 | ||
3481 | /* If we're coming from LLC cached, then we haven't | |
3482 | * actually been tracking whether the data is in the | |
3483 | * CPU cache or not, since we only allow one bit set | |
3484 | * in obj->write_domain and have been skipping the clflushes. | |
3485 | * Just set it to the CPU cache for now. | |
3486 | */ | |
3487 | WARN_ON(obj->base.write_domain & ~I915_GEM_DOMAIN_CPU); | |
e4ffd173 CW |
3488 | |
3489 | old_read_domains = obj->base.read_domains; | |
3490 | old_write_domain = obj->base.write_domain; | |
3491 | ||
3492 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; | |
3493 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; | |
3494 | ||
3495 | trace_i915_gem_object_change_domain(obj, | |
3496 | old_read_domains, | |
3497 | old_write_domain); | |
3498 | } | |
3499 | ||
42d6ab48 | 3500 | i915_gem_verify_gtt(dev); |
e4ffd173 CW |
3501 | return 0; |
3502 | } | |
3503 | ||
199adf40 BW |
3504 | int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data, |
3505 | struct drm_file *file) | |
e6994aee | 3506 | { |
199adf40 | 3507 | struct drm_i915_gem_caching *args = data; |
e6994aee CW |
3508 | struct drm_i915_gem_object *obj; |
3509 | int ret; | |
3510 | ||
3511 | ret = i915_mutex_lock_interruptible(dev); | |
3512 | if (ret) | |
3513 | return ret; | |
3514 | ||
3515 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); | |
3516 | if (&obj->base == NULL) { | |
3517 | ret = -ENOENT; | |
3518 | goto unlock; | |
3519 | } | |
3520 | ||
651d794f CW |
3521 | switch (obj->cache_level) { |
3522 | case I915_CACHE_LLC: | |
3523 | case I915_CACHE_L3_LLC: | |
3524 | args->caching = I915_CACHING_CACHED; | |
3525 | break; | |
3526 | ||
4257d3ba CW |
3527 | case I915_CACHE_WT: |
3528 | args->caching = I915_CACHING_DISPLAY; | |
3529 | break; | |
3530 | ||
651d794f CW |
3531 | default: |
3532 | args->caching = I915_CACHING_NONE; | |
3533 | break; | |
3534 | } | |
e6994aee CW |
3535 | |
3536 | drm_gem_object_unreference(&obj->base); | |
3537 | unlock: | |
3538 | mutex_unlock(&dev->struct_mutex); | |
3539 | return ret; | |
3540 | } | |
3541 | ||
199adf40 BW |
3542 | int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data, |
3543 | struct drm_file *file) | |
e6994aee | 3544 | { |
199adf40 | 3545 | struct drm_i915_gem_caching *args = data; |
e6994aee CW |
3546 | struct drm_i915_gem_object *obj; |
3547 | enum i915_cache_level level; | |
3548 | int ret; | |
3549 | ||
199adf40 BW |
3550 | switch (args->caching) { |
3551 | case I915_CACHING_NONE: | |
e6994aee CW |
3552 | level = I915_CACHE_NONE; |
3553 | break; | |
199adf40 | 3554 | case I915_CACHING_CACHED: |
e6994aee CW |
3555 | level = I915_CACHE_LLC; |
3556 | break; | |
4257d3ba CW |
3557 | case I915_CACHING_DISPLAY: |
3558 | level = HAS_WT(dev) ? I915_CACHE_WT : I915_CACHE_NONE; | |
3559 | break; | |
e6994aee CW |
3560 | default: |
3561 | return -EINVAL; | |
3562 | } | |
3563 | ||
3bc2913e BW |
3564 | ret = i915_mutex_lock_interruptible(dev); |
3565 | if (ret) | |
3566 | return ret; | |
3567 | ||
e6994aee CW |
3568 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
3569 | if (&obj->base == NULL) { | |
3570 | ret = -ENOENT; | |
3571 | goto unlock; | |
3572 | } | |
3573 | ||
3574 | ret = i915_gem_object_set_cache_level(obj, level); | |
3575 | ||
3576 | drm_gem_object_unreference(&obj->base); | |
3577 | unlock: | |
3578 | mutex_unlock(&dev->struct_mutex); | |
3579 | return ret; | |
3580 | } | |
3581 | ||
cc98b413 CW |
3582 | static bool is_pin_display(struct drm_i915_gem_object *obj) |
3583 | { | |
3584 | /* There are 3 sources that pin objects: | |
3585 | * 1. The display engine (scanouts, sprites, cursors); | |
3586 | * 2. Reservations for execbuffer; | |
3587 | * 3. The user. | |
3588 | * | |
3589 | * We can ignore reservations as we hold the struct_mutex and | |
3590 | * are only called outside of the reservation path. The user | |
3591 | * can only increment pin_count once, and so if after | |
3592 | * subtracting the potential reference by the user, any pin_count | |
3593 | * remains, it must be due to another use by the display engine. | |
3594 | */ | |
3595 | return obj->pin_count - !!obj->user_pin_count; | |
3596 | } | |
3597 | ||
b9241ea3 | 3598 | /* |
2da3b9b9 CW |
3599 | * Prepare buffer for display plane (scanout, cursors, etc). |
3600 | * Can be called from an uninterruptible phase (modesetting) and allows | |
3601 | * any flushes to be pipelined (for pageflips). | |
b9241ea3 ZW |
3602 | */ |
3603 | int | |
2da3b9b9 CW |
3604 | i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj, |
3605 | u32 alignment, | |
919926ae | 3606 | struct intel_ring_buffer *pipelined) |
b9241ea3 | 3607 | { |
2da3b9b9 | 3608 | u32 old_read_domains, old_write_domain; |
b9241ea3 ZW |
3609 | int ret; |
3610 | ||
0be73284 | 3611 | if (pipelined != obj->ring) { |
2911a35b BW |
3612 | ret = i915_gem_object_sync(obj, pipelined); |
3613 | if (ret) | |
b9241ea3 ZW |
3614 | return ret; |
3615 | } | |
3616 | ||
cc98b413 CW |
3617 | /* Mark the pin_display early so that we account for the |
3618 | * display coherency whilst setting up the cache domains. | |
3619 | */ | |
3620 | obj->pin_display = true; | |
3621 | ||
a7ef0640 EA |
3622 | /* The display engine is not coherent with the LLC cache on gen6. As |
3623 | * a result, we make sure that the pinning that is about to occur is | |
3624 | * done with uncached PTEs. This is lowest common denominator for all | |
3625 | * chipsets. | |
3626 | * | |
3627 | * However for gen6+, we could do better by using the GFDT bit instead | |
3628 | * of uncaching, which would allow us to flush all the LLC-cached data | |
3629 | * with that bit in the PTE to main memory with just one PIPE_CONTROL. | |
3630 | */ | |
651d794f CW |
3631 | ret = i915_gem_object_set_cache_level(obj, |
3632 | HAS_WT(obj->base.dev) ? I915_CACHE_WT : I915_CACHE_NONE); | |
a7ef0640 | 3633 | if (ret) |
cc98b413 | 3634 | goto err_unpin_display; |
a7ef0640 | 3635 | |
2da3b9b9 CW |
3636 | /* As the user may map the buffer once pinned in the display plane |
3637 | * (e.g. libkms for the bootup splash), we have to ensure that we | |
3638 | * always use map_and_fenceable for all scanout buffers. | |
3639 | */ | |
c37e2204 | 3640 | ret = i915_gem_obj_ggtt_pin(obj, alignment, true, false); |
2da3b9b9 | 3641 | if (ret) |
cc98b413 | 3642 | goto err_unpin_display; |
2da3b9b9 | 3643 | |
2c22569b | 3644 | i915_gem_object_flush_cpu_write_domain(obj, true); |
b118c1e3 | 3645 | |
2da3b9b9 | 3646 | old_write_domain = obj->base.write_domain; |
05394f39 | 3647 | old_read_domains = obj->base.read_domains; |
2da3b9b9 CW |
3648 | |
3649 | /* It should now be out of any other write domains, and we can update | |
3650 | * the domain values for our changes. | |
3651 | */ | |
e5f1d962 | 3652 | obj->base.write_domain = 0; |
05394f39 | 3653 | obj->base.read_domains |= I915_GEM_DOMAIN_GTT; |
b9241ea3 ZW |
3654 | |
3655 | trace_i915_gem_object_change_domain(obj, | |
3656 | old_read_domains, | |
2da3b9b9 | 3657 | old_write_domain); |
b9241ea3 ZW |
3658 | |
3659 | return 0; | |
cc98b413 CW |
3660 | |
3661 | err_unpin_display: | |
3662 | obj->pin_display = is_pin_display(obj); | |
3663 | return ret; | |
3664 | } | |
3665 | ||
3666 | void | |
3667 | i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object *obj) | |
3668 | { | |
3669 | i915_gem_object_unpin(obj); | |
3670 | obj->pin_display = is_pin_display(obj); | |
b9241ea3 ZW |
3671 | } |
3672 | ||
85345517 | 3673 | int |
a8198eea | 3674 | i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj) |
85345517 | 3675 | { |
88241785 CW |
3676 | int ret; |
3677 | ||
a8198eea | 3678 | if ((obj->base.read_domains & I915_GEM_GPU_DOMAINS) == 0) |
85345517 CW |
3679 | return 0; |
3680 | ||
0201f1ec | 3681 | ret = i915_gem_object_wait_rendering(obj, false); |
c501ae7f CW |
3682 | if (ret) |
3683 | return ret; | |
3684 | ||
a8198eea CW |
3685 | /* Ensure that we invalidate the GPU's caches and TLBs. */ |
3686 | obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS; | |
c501ae7f | 3687 | return 0; |
85345517 CW |
3688 | } |
3689 | ||
e47c68e9 EA |
3690 | /** |
3691 | * Moves a single object to the CPU read, and possibly write domain. | |
3692 | * | |
3693 | * This function returns when the move is complete, including waiting on | |
3694 | * flushes to occur. | |
3695 | */ | |
dabdfe02 | 3696 | int |
919926ae | 3697 | i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write) |
e47c68e9 | 3698 | { |
1c5d22f7 | 3699 | uint32_t old_write_domain, old_read_domains; |
e47c68e9 EA |
3700 | int ret; |
3701 | ||
8d7e3de1 CW |
3702 | if (obj->base.write_domain == I915_GEM_DOMAIN_CPU) |
3703 | return 0; | |
3704 | ||
0201f1ec | 3705 | ret = i915_gem_object_wait_rendering(obj, !write); |
88241785 CW |
3706 | if (ret) |
3707 | return ret; | |
3708 | ||
e47c68e9 | 3709 | i915_gem_object_flush_gtt_write_domain(obj); |
2ef7eeaa | 3710 | |
05394f39 CW |
3711 | old_write_domain = obj->base.write_domain; |
3712 | old_read_domains = obj->base.read_domains; | |
1c5d22f7 | 3713 | |
e47c68e9 | 3714 | /* Flush the CPU cache if it's still invalid. */ |
05394f39 | 3715 | if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) { |
2c22569b | 3716 | i915_gem_clflush_object(obj, false); |
2ef7eeaa | 3717 | |
05394f39 | 3718 | obj->base.read_domains |= I915_GEM_DOMAIN_CPU; |
2ef7eeaa EA |
3719 | } |
3720 | ||
3721 | /* It should now be out of any other write domains, and we can update | |
3722 | * the domain values for our changes. | |
3723 | */ | |
05394f39 | 3724 | BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) != 0); |
e47c68e9 EA |
3725 | |
3726 | /* If we're writing through the CPU, then the GPU read domains will | |
3727 | * need to be invalidated at next use. | |
3728 | */ | |
3729 | if (write) { | |
05394f39 CW |
3730 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; |
3731 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; | |
e47c68e9 | 3732 | } |
2ef7eeaa | 3733 | |
1c5d22f7 CW |
3734 | trace_i915_gem_object_change_domain(obj, |
3735 | old_read_domains, | |
3736 | old_write_domain); | |
3737 | ||
2ef7eeaa EA |
3738 | return 0; |
3739 | } | |
3740 | ||
673a394b EA |
3741 | /* Throttle our rendering by waiting until the ring has completed our requests |
3742 | * emitted over 20 msec ago. | |
3743 | * | |
b962442e EA |
3744 | * Note that if we were to use the current jiffies each time around the loop, |
3745 | * we wouldn't escape the function with any frames outstanding if the time to | |
3746 | * render a frame was over 20ms. | |
3747 | * | |
673a394b EA |
3748 | * This should get us reasonable parallelism between CPU and GPU but also |
3749 | * relatively low latency when blocking on a particular request to finish. | |
3750 | */ | |
40a5f0de | 3751 | static int |
f787a5f5 | 3752 | i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file) |
40a5f0de | 3753 | { |
f787a5f5 CW |
3754 | struct drm_i915_private *dev_priv = dev->dev_private; |
3755 | struct drm_i915_file_private *file_priv = file->driver_priv; | |
b962442e | 3756 | unsigned long recent_enough = jiffies - msecs_to_jiffies(20); |
f787a5f5 CW |
3757 | struct drm_i915_gem_request *request; |
3758 | struct intel_ring_buffer *ring = NULL; | |
f69061be | 3759 | unsigned reset_counter; |
f787a5f5 CW |
3760 | u32 seqno = 0; |
3761 | int ret; | |
93533c29 | 3762 | |
308887aa DV |
3763 | ret = i915_gem_wait_for_error(&dev_priv->gpu_error); |
3764 | if (ret) | |
3765 | return ret; | |
3766 | ||
3767 | ret = i915_gem_check_wedge(&dev_priv->gpu_error, false); | |
3768 | if (ret) | |
3769 | return ret; | |
e110e8d6 | 3770 | |
1c25595f | 3771 | spin_lock(&file_priv->mm.lock); |
f787a5f5 | 3772 | list_for_each_entry(request, &file_priv->mm.request_list, client_list) { |
b962442e EA |
3773 | if (time_after_eq(request->emitted_jiffies, recent_enough)) |
3774 | break; | |
40a5f0de | 3775 | |
f787a5f5 CW |
3776 | ring = request->ring; |
3777 | seqno = request->seqno; | |
b962442e | 3778 | } |
f69061be | 3779 | reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter); |
1c25595f | 3780 | spin_unlock(&file_priv->mm.lock); |
40a5f0de | 3781 | |
f787a5f5 CW |
3782 | if (seqno == 0) |
3783 | return 0; | |
2bc43b5c | 3784 | |
f69061be | 3785 | ret = __wait_seqno(ring, seqno, reset_counter, true, NULL); |
f787a5f5 CW |
3786 | if (ret == 0) |
3787 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, 0); | |
40a5f0de EA |
3788 | |
3789 | return ret; | |
3790 | } | |
3791 | ||
673a394b | 3792 | int |
05394f39 | 3793 | i915_gem_object_pin(struct drm_i915_gem_object *obj, |
c37e2204 | 3794 | struct i915_address_space *vm, |
05394f39 | 3795 | uint32_t alignment, |
86a1ee26 CW |
3796 | bool map_and_fenceable, |
3797 | bool nonblocking) | |
673a394b | 3798 | { |
07fe0b12 | 3799 | struct i915_vma *vma; |
673a394b EA |
3800 | int ret; |
3801 | ||
7e81a42e CW |
3802 | if (WARN_ON(obj->pin_count == DRM_I915_GEM_OBJECT_MAX_PIN_COUNT)) |
3803 | return -EBUSY; | |
ac0c6b5a | 3804 | |
07fe0b12 BW |
3805 | WARN_ON(map_and_fenceable && !i915_is_ggtt(vm)); |
3806 | ||
3807 | vma = i915_gem_obj_to_vma(obj, vm); | |
3808 | ||
3809 | if (vma) { | |
3810 | if ((alignment && | |
3811 | vma->node.start & (alignment - 1)) || | |
05394f39 CW |
3812 | (map_and_fenceable && !obj->map_and_fenceable)) { |
3813 | WARN(obj->pin_count, | |
ae7d49d8 | 3814 | "bo is already pinned with incorrect alignment:" |
f343c5f6 | 3815 | " offset=%lx, req.alignment=%x, req.map_and_fenceable=%d," |
75e9e915 | 3816 | " obj->map_and_fenceable=%d\n", |
07fe0b12 | 3817 | i915_gem_obj_offset(obj, vm), alignment, |
75e9e915 | 3818 | map_and_fenceable, |
05394f39 | 3819 | obj->map_and_fenceable); |
07fe0b12 | 3820 | ret = i915_vma_unbind(vma); |
ac0c6b5a CW |
3821 | if (ret) |
3822 | return ret; | |
3823 | } | |
3824 | } | |
3825 | ||
07fe0b12 | 3826 | if (!i915_gem_obj_bound(obj, vm)) { |
8742267a CW |
3827 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
3828 | ||
07fe0b12 BW |
3829 | ret = i915_gem_object_bind_to_vm(obj, vm, alignment, |
3830 | map_and_fenceable, | |
3831 | nonblocking); | |
9731129c | 3832 | if (ret) |
673a394b | 3833 | return ret; |
8742267a CW |
3834 | |
3835 | if (!dev_priv->mm.aliasing_ppgtt) | |
3836 | i915_gem_gtt_bind_object(obj, obj->cache_level); | |
22c344e9 | 3837 | } |
76446cac | 3838 | |
74898d7e DV |
3839 | if (!obj->has_global_gtt_mapping && map_and_fenceable) |
3840 | i915_gem_gtt_bind_object(obj, obj->cache_level); | |
3841 | ||
1b50247a | 3842 | obj->pin_count++; |
6299f992 | 3843 | obj->pin_mappable |= map_and_fenceable; |
673a394b EA |
3844 | |
3845 | return 0; | |
3846 | } | |
3847 | ||
3848 | void | |
05394f39 | 3849 | i915_gem_object_unpin(struct drm_i915_gem_object *obj) |
673a394b | 3850 | { |
05394f39 | 3851 | BUG_ON(obj->pin_count == 0); |
9843877d | 3852 | BUG_ON(!i915_gem_obj_bound_any(obj)); |
673a394b | 3853 | |
1b50247a | 3854 | if (--obj->pin_count == 0) |
6299f992 | 3855 | obj->pin_mappable = false; |
673a394b EA |
3856 | } |
3857 | ||
3858 | int | |
3859 | i915_gem_pin_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 3860 | struct drm_file *file) |
673a394b EA |
3861 | { |
3862 | struct drm_i915_gem_pin *args = data; | |
05394f39 | 3863 | struct drm_i915_gem_object *obj; |
673a394b EA |
3864 | int ret; |
3865 | ||
1d7cfea1 CW |
3866 | ret = i915_mutex_lock_interruptible(dev); |
3867 | if (ret) | |
3868 | return ret; | |
673a394b | 3869 | |
05394f39 | 3870 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 3871 | if (&obj->base == NULL) { |
1d7cfea1 CW |
3872 | ret = -ENOENT; |
3873 | goto unlock; | |
673a394b | 3874 | } |
673a394b | 3875 | |
05394f39 | 3876 | if (obj->madv != I915_MADV_WILLNEED) { |
bb6baf76 | 3877 | DRM_ERROR("Attempting to pin a purgeable buffer\n"); |
1d7cfea1 CW |
3878 | ret = -EINVAL; |
3879 | goto out; | |
3ef94daa CW |
3880 | } |
3881 | ||
05394f39 | 3882 | if (obj->pin_filp != NULL && obj->pin_filp != file) { |
79e53945 JB |
3883 | DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n", |
3884 | args->handle); | |
1d7cfea1 CW |
3885 | ret = -EINVAL; |
3886 | goto out; | |
79e53945 JB |
3887 | } |
3888 | ||
93be8788 | 3889 | if (obj->user_pin_count == 0) { |
c37e2204 | 3890 | ret = i915_gem_obj_ggtt_pin(obj, args->alignment, true, false); |
1d7cfea1 CW |
3891 | if (ret) |
3892 | goto out; | |
673a394b EA |
3893 | } |
3894 | ||
93be8788 CW |
3895 | obj->user_pin_count++; |
3896 | obj->pin_filp = file; | |
3897 | ||
f343c5f6 | 3898 | args->offset = i915_gem_obj_ggtt_offset(obj); |
1d7cfea1 | 3899 | out: |
05394f39 | 3900 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 3901 | unlock: |
673a394b | 3902 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 3903 | return ret; |
673a394b EA |
3904 | } |
3905 | ||
3906 | int | |
3907 | i915_gem_unpin_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 3908 | struct drm_file *file) |
673a394b EA |
3909 | { |
3910 | struct drm_i915_gem_pin *args = data; | |
05394f39 | 3911 | struct drm_i915_gem_object *obj; |
76c1dec1 | 3912 | int ret; |
673a394b | 3913 | |
1d7cfea1 CW |
3914 | ret = i915_mutex_lock_interruptible(dev); |
3915 | if (ret) | |
3916 | return ret; | |
673a394b | 3917 | |
05394f39 | 3918 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 3919 | if (&obj->base == NULL) { |
1d7cfea1 CW |
3920 | ret = -ENOENT; |
3921 | goto unlock; | |
673a394b | 3922 | } |
76c1dec1 | 3923 | |
05394f39 | 3924 | if (obj->pin_filp != file) { |
79e53945 JB |
3925 | DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n", |
3926 | args->handle); | |
1d7cfea1 CW |
3927 | ret = -EINVAL; |
3928 | goto out; | |
79e53945 | 3929 | } |
05394f39 CW |
3930 | obj->user_pin_count--; |
3931 | if (obj->user_pin_count == 0) { | |
3932 | obj->pin_filp = NULL; | |
79e53945 JB |
3933 | i915_gem_object_unpin(obj); |
3934 | } | |
673a394b | 3935 | |
1d7cfea1 | 3936 | out: |
05394f39 | 3937 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 3938 | unlock: |
673a394b | 3939 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 3940 | return ret; |
673a394b EA |
3941 | } |
3942 | ||
3943 | int | |
3944 | i915_gem_busy_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 3945 | struct drm_file *file) |
673a394b EA |
3946 | { |
3947 | struct drm_i915_gem_busy *args = data; | |
05394f39 | 3948 | struct drm_i915_gem_object *obj; |
30dbf0c0 CW |
3949 | int ret; |
3950 | ||
76c1dec1 | 3951 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 3952 | if (ret) |
76c1dec1 | 3953 | return ret; |
673a394b | 3954 | |
05394f39 | 3955 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 3956 | if (&obj->base == NULL) { |
1d7cfea1 CW |
3957 | ret = -ENOENT; |
3958 | goto unlock; | |
673a394b | 3959 | } |
d1b851fc | 3960 | |
0be555b6 CW |
3961 | /* Count all active objects as busy, even if they are currently not used |
3962 | * by the gpu. Users of this interface expect objects to eventually | |
3963 | * become non-busy without any further actions, therefore emit any | |
3964 | * necessary flushes here. | |
c4de0a5d | 3965 | */ |
30dfebf3 | 3966 | ret = i915_gem_object_flush_active(obj); |
0be555b6 | 3967 | |
30dfebf3 | 3968 | args->busy = obj->active; |
e9808edd CW |
3969 | if (obj->ring) { |
3970 | BUILD_BUG_ON(I915_NUM_RINGS > 16); | |
3971 | args->busy |= intel_ring_flag(obj->ring) << 16; | |
3972 | } | |
673a394b | 3973 | |
05394f39 | 3974 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 3975 | unlock: |
673a394b | 3976 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 3977 | return ret; |
673a394b EA |
3978 | } |
3979 | ||
3980 | int | |
3981 | i915_gem_throttle_ioctl(struct drm_device *dev, void *data, | |
3982 | struct drm_file *file_priv) | |
3983 | { | |
0206e353 | 3984 | return i915_gem_ring_throttle(dev, file_priv); |
673a394b EA |
3985 | } |
3986 | ||
3ef94daa CW |
3987 | int |
3988 | i915_gem_madvise_ioctl(struct drm_device *dev, void *data, | |
3989 | struct drm_file *file_priv) | |
3990 | { | |
3991 | struct drm_i915_gem_madvise *args = data; | |
05394f39 | 3992 | struct drm_i915_gem_object *obj; |
76c1dec1 | 3993 | int ret; |
3ef94daa CW |
3994 | |
3995 | switch (args->madv) { | |
3996 | case I915_MADV_DONTNEED: | |
3997 | case I915_MADV_WILLNEED: | |
3998 | break; | |
3999 | default: | |
4000 | return -EINVAL; | |
4001 | } | |
4002 | ||
1d7cfea1 CW |
4003 | ret = i915_mutex_lock_interruptible(dev); |
4004 | if (ret) | |
4005 | return ret; | |
4006 | ||
05394f39 | 4007 | obj = to_intel_bo(drm_gem_object_lookup(dev, file_priv, args->handle)); |
c8725226 | 4008 | if (&obj->base == NULL) { |
1d7cfea1 CW |
4009 | ret = -ENOENT; |
4010 | goto unlock; | |
3ef94daa | 4011 | } |
3ef94daa | 4012 | |
05394f39 | 4013 | if (obj->pin_count) { |
1d7cfea1 CW |
4014 | ret = -EINVAL; |
4015 | goto out; | |
3ef94daa CW |
4016 | } |
4017 | ||
05394f39 CW |
4018 | if (obj->madv != __I915_MADV_PURGED) |
4019 | obj->madv = args->madv; | |
3ef94daa | 4020 | |
6c085a72 CW |
4021 | /* if the object is no longer attached, discard its backing storage */ |
4022 | if (i915_gem_object_is_purgeable(obj) && obj->pages == NULL) | |
2d7ef395 CW |
4023 | i915_gem_object_truncate(obj); |
4024 | ||
05394f39 | 4025 | args->retained = obj->madv != __I915_MADV_PURGED; |
bb6baf76 | 4026 | |
1d7cfea1 | 4027 | out: |
05394f39 | 4028 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 4029 | unlock: |
3ef94daa | 4030 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 4031 | return ret; |
3ef94daa CW |
4032 | } |
4033 | ||
37e680a1 CW |
4034 | void i915_gem_object_init(struct drm_i915_gem_object *obj, |
4035 | const struct drm_i915_gem_object_ops *ops) | |
0327d6ba | 4036 | { |
35c20a60 | 4037 | INIT_LIST_HEAD(&obj->global_list); |
0327d6ba | 4038 | INIT_LIST_HEAD(&obj->ring_list); |
b25cb2f8 | 4039 | INIT_LIST_HEAD(&obj->obj_exec_link); |
2f633156 | 4040 | INIT_LIST_HEAD(&obj->vma_list); |
0327d6ba | 4041 | |
37e680a1 CW |
4042 | obj->ops = ops; |
4043 | ||
0327d6ba CW |
4044 | obj->fence_reg = I915_FENCE_REG_NONE; |
4045 | obj->madv = I915_MADV_WILLNEED; | |
4046 | /* Avoid an unnecessary call to unbind on the first bind. */ | |
4047 | obj->map_and_fenceable = true; | |
4048 | ||
4049 | i915_gem_info_add_obj(obj->base.dev->dev_private, obj->base.size); | |
4050 | } | |
4051 | ||
37e680a1 CW |
4052 | static const struct drm_i915_gem_object_ops i915_gem_object_ops = { |
4053 | .get_pages = i915_gem_object_get_pages_gtt, | |
4054 | .put_pages = i915_gem_object_put_pages_gtt, | |
4055 | }; | |
4056 | ||
05394f39 CW |
4057 | struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev, |
4058 | size_t size) | |
ac52bc56 | 4059 | { |
c397b908 | 4060 | struct drm_i915_gem_object *obj; |
5949eac4 | 4061 | struct address_space *mapping; |
1a240d4d | 4062 | gfp_t mask; |
ac52bc56 | 4063 | |
42dcedd4 | 4064 | obj = i915_gem_object_alloc(dev); |
c397b908 DV |
4065 | if (obj == NULL) |
4066 | return NULL; | |
673a394b | 4067 | |
c397b908 | 4068 | if (drm_gem_object_init(dev, &obj->base, size) != 0) { |
42dcedd4 | 4069 | i915_gem_object_free(obj); |
c397b908 DV |
4070 | return NULL; |
4071 | } | |
673a394b | 4072 | |
bed1ea95 CW |
4073 | mask = GFP_HIGHUSER | __GFP_RECLAIMABLE; |
4074 | if (IS_CRESTLINE(dev) || IS_BROADWATER(dev)) { | |
4075 | /* 965gm cannot relocate objects above 4GiB. */ | |
4076 | mask &= ~__GFP_HIGHMEM; | |
4077 | mask |= __GFP_DMA32; | |
4078 | } | |
4079 | ||
496ad9aa | 4080 | mapping = file_inode(obj->base.filp)->i_mapping; |
bed1ea95 | 4081 | mapping_set_gfp_mask(mapping, mask); |
5949eac4 | 4082 | |
37e680a1 | 4083 | i915_gem_object_init(obj, &i915_gem_object_ops); |
73aa808f | 4084 | |
c397b908 DV |
4085 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; |
4086 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; | |
673a394b | 4087 | |
3d29b842 ED |
4088 | if (HAS_LLC(dev)) { |
4089 | /* On some devices, we can have the GPU use the LLC (the CPU | |
a1871112 EA |
4090 | * cache) for about a 10% performance improvement |
4091 | * compared to uncached. Graphics requests other than | |
4092 | * display scanout are coherent with the CPU in | |
4093 | * accessing this cache. This means in this mode we | |
4094 | * don't need to clflush on the CPU side, and on the | |
4095 | * GPU side we only need to flush internal caches to | |
4096 | * get data visible to the CPU. | |
4097 | * | |
4098 | * However, we maintain the display planes as UC, and so | |
4099 | * need to rebind when first used as such. | |
4100 | */ | |
4101 | obj->cache_level = I915_CACHE_LLC; | |
4102 | } else | |
4103 | obj->cache_level = I915_CACHE_NONE; | |
4104 | ||
d861e338 DV |
4105 | trace_i915_gem_object_create(obj); |
4106 | ||
05394f39 | 4107 | return obj; |
c397b908 DV |
4108 | } |
4109 | ||
4110 | int i915_gem_init_object(struct drm_gem_object *obj) | |
4111 | { | |
4112 | BUG(); | |
de151cf6 | 4113 | |
673a394b EA |
4114 | return 0; |
4115 | } | |
4116 | ||
1488fc08 | 4117 | void i915_gem_free_object(struct drm_gem_object *gem_obj) |
673a394b | 4118 | { |
1488fc08 | 4119 | struct drm_i915_gem_object *obj = to_intel_bo(gem_obj); |
05394f39 | 4120 | struct drm_device *dev = obj->base.dev; |
be72615b | 4121 | drm_i915_private_t *dev_priv = dev->dev_private; |
07fe0b12 | 4122 | struct i915_vma *vma, *next; |
673a394b | 4123 | |
26e12f89 CW |
4124 | trace_i915_gem_object_destroy(obj); |
4125 | ||
1488fc08 CW |
4126 | if (obj->phys_obj) |
4127 | i915_gem_detach_phys_object(dev, obj); | |
4128 | ||
4129 | obj->pin_count = 0; | |
07fe0b12 BW |
4130 | /* NB: 0 or 1 elements */ |
4131 | WARN_ON(!list_empty(&obj->vma_list) && | |
4132 | !list_is_singular(&obj->vma_list)); | |
4133 | list_for_each_entry_safe(vma, next, &obj->vma_list, vma_link) { | |
4134 | int ret = i915_vma_unbind(vma); | |
4135 | if (WARN_ON(ret == -ERESTARTSYS)) { | |
4136 | bool was_interruptible; | |
1488fc08 | 4137 | |
07fe0b12 BW |
4138 | was_interruptible = dev_priv->mm.interruptible; |
4139 | dev_priv->mm.interruptible = false; | |
1488fc08 | 4140 | |
07fe0b12 | 4141 | WARN_ON(i915_vma_unbind(vma)); |
1488fc08 | 4142 | |
07fe0b12 BW |
4143 | dev_priv->mm.interruptible = was_interruptible; |
4144 | } | |
1488fc08 CW |
4145 | } |
4146 | ||
1d64ae71 BW |
4147 | /* Stolen objects don't hold a ref, but do hold pin count. Fix that up |
4148 | * before progressing. */ | |
4149 | if (obj->stolen) | |
4150 | i915_gem_object_unpin_pages(obj); | |
4151 | ||
401c29f6 BW |
4152 | if (WARN_ON(obj->pages_pin_count)) |
4153 | obj->pages_pin_count = 0; | |
37e680a1 | 4154 | i915_gem_object_put_pages(obj); |
d8cb5086 | 4155 | i915_gem_object_free_mmap_offset(obj); |
0104fdbb | 4156 | i915_gem_object_release_stolen(obj); |
de151cf6 | 4157 | |
9da3da66 CW |
4158 | BUG_ON(obj->pages); |
4159 | ||
2f745ad3 CW |
4160 | if (obj->base.import_attach) |
4161 | drm_prime_gem_destroy(&obj->base, NULL); | |
de151cf6 | 4162 | |
05394f39 CW |
4163 | drm_gem_object_release(&obj->base); |
4164 | i915_gem_info_remove_obj(dev_priv, obj->base.size); | |
c397b908 | 4165 | |
05394f39 | 4166 | kfree(obj->bit_17); |
42dcedd4 | 4167 | i915_gem_object_free(obj); |
673a394b EA |
4168 | } |
4169 | ||
e656a6cb | 4170 | struct i915_vma *i915_gem_obj_to_vma(struct drm_i915_gem_object *obj, |
2f633156 | 4171 | struct i915_address_space *vm) |
e656a6cb DV |
4172 | { |
4173 | struct i915_vma *vma; | |
4174 | list_for_each_entry(vma, &obj->vma_list, vma_link) | |
4175 | if (vma->vm == vm) | |
4176 | return vma; | |
4177 | ||
4178 | return NULL; | |
4179 | } | |
4180 | ||
4181 | static struct i915_vma *__i915_gem_vma_create(struct drm_i915_gem_object *obj, | |
4182 | struct i915_address_space *vm) | |
2f633156 BW |
4183 | { |
4184 | struct i915_vma *vma = kzalloc(sizeof(*vma), GFP_KERNEL); | |
4185 | if (vma == NULL) | |
4186 | return ERR_PTR(-ENOMEM); | |
4187 | ||
4188 | INIT_LIST_HEAD(&vma->vma_link); | |
ca191b13 | 4189 | INIT_LIST_HEAD(&vma->mm_list); |
82a55ad1 | 4190 | INIT_LIST_HEAD(&vma->exec_list); |
2f633156 BW |
4191 | vma->vm = vm; |
4192 | vma->obj = obj; | |
4193 | ||
8b9c2b94 BW |
4194 | /* Keep GGTT vmas first to make debug easier */ |
4195 | if (i915_is_ggtt(vm)) | |
4196 | list_add(&vma->vma_link, &obj->vma_list); | |
4197 | else | |
4198 | list_add_tail(&vma->vma_link, &obj->vma_list); | |
4199 | ||
2f633156 BW |
4200 | return vma; |
4201 | } | |
4202 | ||
e656a6cb DV |
4203 | struct i915_vma * |
4204 | i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object *obj, | |
4205 | struct i915_address_space *vm) | |
4206 | { | |
4207 | struct i915_vma *vma; | |
4208 | ||
4209 | vma = i915_gem_obj_to_vma(obj, vm); | |
4210 | if (!vma) | |
4211 | vma = __i915_gem_vma_create(obj, vm); | |
4212 | ||
4213 | return vma; | |
4214 | } | |
4215 | ||
2f633156 BW |
4216 | void i915_gem_vma_destroy(struct i915_vma *vma) |
4217 | { | |
4218 | WARN_ON(vma->node.allocated); | |
aaa05667 CW |
4219 | |
4220 | /* Keep the vma as a placeholder in the execbuffer reservation lists */ | |
4221 | if (!list_empty(&vma->exec_list)) | |
4222 | return; | |
4223 | ||
8b9c2b94 | 4224 | list_del(&vma->vma_link); |
b93dab6e | 4225 | |
2f633156 BW |
4226 | kfree(vma); |
4227 | } | |
4228 | ||
29105ccc CW |
4229 | int |
4230 | i915_gem_idle(struct drm_device *dev) | |
4231 | { | |
4232 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4233 | int ret; | |
28dfe52a | 4234 | |
db1b76ca | 4235 | if (dev_priv->ums.mm_suspended) { |
29105ccc CW |
4236 | mutex_unlock(&dev->struct_mutex); |
4237 | return 0; | |
28dfe52a EA |
4238 | } |
4239 | ||
b2da9fe5 | 4240 | ret = i915_gpu_idle(dev); |
6dbe2772 KP |
4241 | if (ret) { |
4242 | mutex_unlock(&dev->struct_mutex); | |
673a394b | 4243 | return ret; |
6dbe2772 | 4244 | } |
b2da9fe5 | 4245 | i915_gem_retire_requests(dev); |
673a394b | 4246 | |
29105ccc | 4247 | /* Under UMS, be paranoid and evict. */ |
a39d7efc | 4248 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) |
6c085a72 | 4249 | i915_gem_evict_everything(dev); |
29105ccc | 4250 | |
99584db3 | 4251 | del_timer_sync(&dev_priv->gpu_error.hangcheck_timer); |
29105ccc CW |
4252 | |
4253 | i915_kernel_lost_context(dev); | |
6dbe2772 | 4254 | i915_gem_cleanup_ringbuffer(dev); |
29105ccc | 4255 | |
29105ccc CW |
4256 | /* Cancel the retire work handler, which should be idle now. */ |
4257 | cancel_delayed_work_sync(&dev_priv->mm.retire_work); | |
4258 | ||
673a394b EA |
4259 | return 0; |
4260 | } | |
4261 | ||
c3787e2e | 4262 | int i915_gem_l3_remap(struct intel_ring_buffer *ring, int slice) |
b9524a1e | 4263 | { |
c3787e2e | 4264 | struct drm_device *dev = ring->dev; |
b9524a1e | 4265 | drm_i915_private_t *dev_priv = dev->dev_private; |
35a85ac6 BW |
4266 | u32 reg_base = GEN7_L3LOG_BASE + (slice * 0x200); |
4267 | u32 *remap_info = dev_priv->l3_parity.remap_info[slice]; | |
c3787e2e | 4268 | int i, ret; |
b9524a1e | 4269 | |
040d2baa | 4270 | if (!HAS_L3_DPF(dev) || !remap_info) |
c3787e2e | 4271 | return 0; |
b9524a1e | 4272 | |
c3787e2e BW |
4273 | ret = intel_ring_begin(ring, GEN7_L3LOG_SIZE / 4 * 3); |
4274 | if (ret) | |
4275 | return ret; | |
b9524a1e | 4276 | |
c3787e2e BW |
4277 | /* |
4278 | * Note: We do not worry about the concurrent register cacheline hang | |
4279 | * here because no other code should access these registers other than | |
4280 | * at initialization time. | |
4281 | */ | |
b9524a1e | 4282 | for (i = 0; i < GEN7_L3LOG_SIZE; i += 4) { |
c3787e2e BW |
4283 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); |
4284 | intel_ring_emit(ring, reg_base + i); | |
4285 | intel_ring_emit(ring, remap_info[i/4]); | |
b9524a1e BW |
4286 | } |
4287 | ||
c3787e2e | 4288 | intel_ring_advance(ring); |
b9524a1e | 4289 | |
c3787e2e | 4290 | return ret; |
b9524a1e BW |
4291 | } |
4292 | ||
f691e2f4 DV |
4293 | void i915_gem_init_swizzling(struct drm_device *dev) |
4294 | { | |
4295 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4296 | ||
11782b02 | 4297 | if (INTEL_INFO(dev)->gen < 5 || |
f691e2f4 DV |
4298 | dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE) |
4299 | return; | |
4300 | ||
4301 | I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) | | |
4302 | DISP_TILE_SURFACE_SWIZZLING); | |
4303 | ||
11782b02 DV |
4304 | if (IS_GEN5(dev)) |
4305 | return; | |
4306 | ||
f691e2f4 DV |
4307 | I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_SWZCTL); |
4308 | if (IS_GEN6(dev)) | |
6b26c86d | 4309 | I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB)); |
8782e26c | 4310 | else if (IS_GEN7(dev)) |
6b26c86d | 4311 | I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB)); |
8782e26c BW |
4312 | else |
4313 | BUG(); | |
f691e2f4 | 4314 | } |
e21af88d | 4315 | |
67b1b571 CW |
4316 | static bool |
4317 | intel_enable_blt(struct drm_device *dev) | |
4318 | { | |
4319 | if (!HAS_BLT(dev)) | |
4320 | return false; | |
4321 | ||
4322 | /* The blitter was dysfunctional on early prototypes */ | |
4323 | if (IS_GEN6(dev) && dev->pdev->revision < 8) { | |
4324 | DRM_INFO("BLT not supported on this pre-production hardware;" | |
4325 | " graphics performance will be degraded.\n"); | |
4326 | return false; | |
4327 | } | |
4328 | ||
4329 | return true; | |
4330 | } | |
4331 | ||
4fc7c971 | 4332 | static int i915_gem_init_rings(struct drm_device *dev) |
8187a2b7 | 4333 | { |
4fc7c971 | 4334 | struct drm_i915_private *dev_priv = dev->dev_private; |
8187a2b7 | 4335 | int ret; |
68f95ba9 | 4336 | |
5c1143bb | 4337 | ret = intel_init_render_ring_buffer(dev); |
68f95ba9 | 4338 | if (ret) |
b6913e4b | 4339 | return ret; |
68f95ba9 CW |
4340 | |
4341 | if (HAS_BSD(dev)) { | |
5c1143bb | 4342 | ret = intel_init_bsd_ring_buffer(dev); |
68f95ba9 CW |
4343 | if (ret) |
4344 | goto cleanup_render_ring; | |
d1b851fc | 4345 | } |
68f95ba9 | 4346 | |
67b1b571 | 4347 | if (intel_enable_blt(dev)) { |
549f7365 CW |
4348 | ret = intel_init_blt_ring_buffer(dev); |
4349 | if (ret) | |
4350 | goto cleanup_bsd_ring; | |
4351 | } | |
4352 | ||
9a8a2213 BW |
4353 | if (HAS_VEBOX(dev)) { |
4354 | ret = intel_init_vebox_ring_buffer(dev); | |
4355 | if (ret) | |
4356 | goto cleanup_blt_ring; | |
4357 | } | |
4358 | ||
4359 | ||
99433931 | 4360 | ret = i915_gem_set_seqno(dev, ((u32)~0 - 0x1000)); |
4fc7c971 | 4361 | if (ret) |
9a8a2213 | 4362 | goto cleanup_vebox_ring; |
4fc7c971 BW |
4363 | |
4364 | return 0; | |
4365 | ||
9a8a2213 BW |
4366 | cleanup_vebox_ring: |
4367 | intel_cleanup_ring_buffer(&dev_priv->ring[VECS]); | |
4fc7c971 BW |
4368 | cleanup_blt_ring: |
4369 | intel_cleanup_ring_buffer(&dev_priv->ring[BCS]); | |
4370 | cleanup_bsd_ring: | |
4371 | intel_cleanup_ring_buffer(&dev_priv->ring[VCS]); | |
4372 | cleanup_render_ring: | |
4373 | intel_cleanup_ring_buffer(&dev_priv->ring[RCS]); | |
4374 | ||
4375 | return ret; | |
4376 | } | |
4377 | ||
4378 | int | |
4379 | i915_gem_init_hw(struct drm_device *dev) | |
4380 | { | |
4381 | drm_i915_private_t *dev_priv = dev->dev_private; | |
35a85ac6 | 4382 | int ret, i; |
4fc7c971 BW |
4383 | |
4384 | if (INTEL_INFO(dev)->gen < 6 && !intel_enable_gtt()) | |
4385 | return -EIO; | |
4386 | ||
59124506 | 4387 | if (dev_priv->ellc_size) |
05e21cc4 | 4388 | I915_WRITE(HSW_IDICR, I915_READ(HSW_IDICR) | IDIHASHMSK(0xf)); |
4fc7c971 | 4389 | |
9435373e RV |
4390 | if (IS_HSW_GT3(dev)) |
4391 | I915_WRITE(MI_PREDICATE_RESULT_2, LOWER_SLICE_ENABLED); | |
4392 | else | |
4393 | I915_WRITE(MI_PREDICATE_RESULT_2, LOWER_SLICE_DISABLED); | |
4394 | ||
88a2b2a3 BW |
4395 | if (HAS_PCH_NOP(dev)) { |
4396 | u32 temp = I915_READ(GEN7_MSG_CTL); | |
4397 | temp &= ~(WAIT_FOR_PCH_FLR_ACK | WAIT_FOR_PCH_RESET_ACK); | |
4398 | I915_WRITE(GEN7_MSG_CTL, temp); | |
4399 | } | |
4400 | ||
4fc7c971 BW |
4401 | i915_gem_init_swizzling(dev); |
4402 | ||
4403 | ret = i915_gem_init_rings(dev); | |
99433931 MK |
4404 | if (ret) |
4405 | return ret; | |
4406 | ||
c3787e2e BW |
4407 | for (i = 0; i < NUM_L3_SLICES(dev); i++) |
4408 | i915_gem_l3_remap(&dev_priv->ring[RCS], i); | |
4409 | ||
254f965c BW |
4410 | /* |
4411 | * XXX: There was some w/a described somewhere suggesting loading | |
4412 | * contexts before PPGTT. | |
4413 | */ | |
4414 | i915_gem_context_init(dev); | |
b7c36d25 BW |
4415 | if (dev_priv->mm.aliasing_ppgtt) { |
4416 | ret = dev_priv->mm.aliasing_ppgtt->enable(dev); | |
4417 | if (ret) { | |
4418 | i915_gem_cleanup_aliasing_ppgtt(dev); | |
4419 | DRM_INFO("PPGTT enable failed. This is not fatal, but unexpected\n"); | |
4420 | } | |
4421 | } | |
e21af88d | 4422 | |
68f95ba9 | 4423 | return 0; |
8187a2b7 ZN |
4424 | } |
4425 | ||
1070a42b CW |
4426 | int i915_gem_init(struct drm_device *dev) |
4427 | { | |
4428 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1070a42b CW |
4429 | int ret; |
4430 | ||
1070a42b | 4431 | mutex_lock(&dev->struct_mutex); |
d62b4892 JB |
4432 | |
4433 | if (IS_VALLEYVIEW(dev)) { | |
4434 | /* VLVA0 (potential hack), BIOS isn't actually waking us */ | |
4435 | I915_WRITE(VLV_GTLC_WAKE_CTRL, 1); | |
4436 | if (wait_for((I915_READ(VLV_GTLC_PW_STATUS) & 1) == 1, 10)) | |
4437 | DRM_DEBUG_DRIVER("allow wake ack timed out\n"); | |
4438 | } | |
4439 | ||
d7e5008f | 4440 | i915_gem_init_global_gtt(dev); |
d62b4892 | 4441 | |
1070a42b CW |
4442 | ret = i915_gem_init_hw(dev); |
4443 | mutex_unlock(&dev->struct_mutex); | |
4444 | if (ret) { | |
4445 | i915_gem_cleanup_aliasing_ppgtt(dev); | |
4446 | return ret; | |
4447 | } | |
4448 | ||
53ca26ca DV |
4449 | /* Allow hardware batchbuffers unless told otherwise, but not for KMS. */ |
4450 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) | |
4451 | dev_priv->dri1.allow_batchbuffer = 1; | |
1070a42b CW |
4452 | return 0; |
4453 | } | |
4454 | ||
8187a2b7 ZN |
4455 | void |
4456 | i915_gem_cleanup_ringbuffer(struct drm_device *dev) | |
4457 | { | |
4458 | drm_i915_private_t *dev_priv = dev->dev_private; | |
b4519513 | 4459 | struct intel_ring_buffer *ring; |
1ec14ad3 | 4460 | int i; |
8187a2b7 | 4461 | |
b4519513 CW |
4462 | for_each_ring(ring, dev_priv, i) |
4463 | intel_cleanup_ring_buffer(ring); | |
8187a2b7 ZN |
4464 | } |
4465 | ||
673a394b EA |
4466 | int |
4467 | i915_gem_entervt_ioctl(struct drm_device *dev, void *data, | |
4468 | struct drm_file *file_priv) | |
4469 | { | |
db1b76ca | 4470 | struct drm_i915_private *dev_priv = dev->dev_private; |
b4519513 | 4471 | int ret; |
673a394b | 4472 | |
79e53945 JB |
4473 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
4474 | return 0; | |
4475 | ||
1f83fee0 | 4476 | if (i915_reset_in_progress(&dev_priv->gpu_error)) { |
673a394b | 4477 | DRM_ERROR("Reenabling wedged hardware, good luck\n"); |
1f83fee0 | 4478 | atomic_set(&dev_priv->gpu_error.reset_counter, 0); |
673a394b EA |
4479 | } |
4480 | ||
673a394b | 4481 | mutex_lock(&dev->struct_mutex); |
db1b76ca | 4482 | dev_priv->ums.mm_suspended = 0; |
9bb2d6f9 | 4483 | |
f691e2f4 | 4484 | ret = i915_gem_init_hw(dev); |
d816f6ac WF |
4485 | if (ret != 0) { |
4486 | mutex_unlock(&dev->struct_mutex); | |
9bb2d6f9 | 4487 | return ret; |
d816f6ac | 4488 | } |
9bb2d6f9 | 4489 | |
5cef07e1 | 4490 | BUG_ON(!list_empty(&dev_priv->gtt.base.active_list)); |
673a394b | 4491 | mutex_unlock(&dev->struct_mutex); |
dbb19d30 | 4492 | |
5f35308b CW |
4493 | ret = drm_irq_install(dev); |
4494 | if (ret) | |
4495 | goto cleanup_ringbuffer; | |
dbb19d30 | 4496 | |
673a394b | 4497 | return 0; |
5f35308b CW |
4498 | |
4499 | cleanup_ringbuffer: | |
4500 | mutex_lock(&dev->struct_mutex); | |
4501 | i915_gem_cleanup_ringbuffer(dev); | |
db1b76ca | 4502 | dev_priv->ums.mm_suspended = 1; |
5f35308b CW |
4503 | mutex_unlock(&dev->struct_mutex); |
4504 | ||
4505 | return ret; | |
673a394b EA |
4506 | } |
4507 | ||
4508 | int | |
4509 | i915_gem_leavevt_ioctl(struct drm_device *dev, void *data, | |
4510 | struct drm_file *file_priv) | |
4511 | { | |
db1b76ca DV |
4512 | struct drm_i915_private *dev_priv = dev->dev_private; |
4513 | int ret; | |
4514 | ||
79e53945 JB |
4515 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
4516 | return 0; | |
4517 | ||
dbb19d30 | 4518 | drm_irq_uninstall(dev); |
db1b76ca DV |
4519 | |
4520 | mutex_lock(&dev->struct_mutex); | |
4521 | ret = i915_gem_idle(dev); | |
4522 | ||
4523 | /* Hack! Don't let anybody do execbuf while we don't control the chip. | |
4524 | * We need to replace this with a semaphore, or something. | |
4525 | * And not confound ums.mm_suspended! | |
4526 | */ | |
4527 | if (ret != 0) | |
4528 | dev_priv->ums.mm_suspended = 1; | |
4529 | mutex_unlock(&dev->struct_mutex); | |
4530 | ||
4531 | return ret; | |
673a394b EA |
4532 | } |
4533 | ||
4534 | void | |
4535 | i915_gem_lastclose(struct drm_device *dev) | |
4536 | { | |
4537 | int ret; | |
673a394b | 4538 | |
e806b495 EA |
4539 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
4540 | return; | |
4541 | ||
db1b76ca | 4542 | mutex_lock(&dev->struct_mutex); |
6dbe2772 KP |
4543 | ret = i915_gem_idle(dev); |
4544 | if (ret) | |
4545 | DRM_ERROR("failed to idle hardware: %d\n", ret); | |
db1b76ca | 4546 | mutex_unlock(&dev->struct_mutex); |
673a394b EA |
4547 | } |
4548 | ||
64193406 CW |
4549 | static void |
4550 | init_ring_lists(struct intel_ring_buffer *ring) | |
4551 | { | |
4552 | INIT_LIST_HEAD(&ring->active_list); | |
4553 | INIT_LIST_HEAD(&ring->request_list); | |
64193406 CW |
4554 | } |
4555 | ||
fc8c067e BW |
4556 | static void i915_init_vm(struct drm_i915_private *dev_priv, |
4557 | struct i915_address_space *vm) | |
4558 | { | |
4559 | vm->dev = dev_priv->dev; | |
4560 | INIT_LIST_HEAD(&vm->active_list); | |
4561 | INIT_LIST_HEAD(&vm->inactive_list); | |
4562 | INIT_LIST_HEAD(&vm->global_link); | |
4563 | list_add(&vm->global_link, &dev_priv->vm_list); | |
4564 | } | |
4565 | ||
673a394b EA |
4566 | void |
4567 | i915_gem_load(struct drm_device *dev) | |
4568 | { | |
4569 | drm_i915_private_t *dev_priv = dev->dev_private; | |
42dcedd4 CW |
4570 | int i; |
4571 | ||
4572 | dev_priv->slab = | |
4573 | kmem_cache_create("i915_gem_object", | |
4574 | sizeof(struct drm_i915_gem_object), 0, | |
4575 | SLAB_HWCACHE_ALIGN, | |
4576 | NULL); | |
673a394b | 4577 | |
fc8c067e BW |
4578 | INIT_LIST_HEAD(&dev_priv->vm_list); |
4579 | i915_init_vm(dev_priv, &dev_priv->gtt.base); | |
4580 | ||
a33afea5 | 4581 | INIT_LIST_HEAD(&dev_priv->context_list); |
6c085a72 CW |
4582 | INIT_LIST_HEAD(&dev_priv->mm.unbound_list); |
4583 | INIT_LIST_HEAD(&dev_priv->mm.bound_list); | |
a09ba7fa | 4584 | INIT_LIST_HEAD(&dev_priv->mm.fence_list); |
1ec14ad3 CW |
4585 | for (i = 0; i < I915_NUM_RINGS; i++) |
4586 | init_ring_lists(&dev_priv->ring[i]); | |
4b9de737 | 4587 | for (i = 0; i < I915_MAX_NUM_FENCES; i++) |
007cc8ac | 4588 | INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list); |
673a394b EA |
4589 | INIT_DELAYED_WORK(&dev_priv->mm.retire_work, |
4590 | i915_gem_retire_work_handler); | |
1f83fee0 | 4591 | init_waitqueue_head(&dev_priv->gpu_error.reset_queue); |
31169714 | 4592 | |
94400120 DA |
4593 | /* On GEN3 we really need to make sure the ARB C3 LP bit is set */ |
4594 | if (IS_GEN3(dev)) { | |
50743298 DV |
4595 | I915_WRITE(MI_ARB_STATE, |
4596 | _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE)); | |
94400120 DA |
4597 | } |
4598 | ||
72bfa19c CW |
4599 | dev_priv->relative_constants_mode = I915_EXEC_CONSTANTS_REL_GENERAL; |
4600 | ||
de151cf6 | 4601 | /* Old X drivers will take 0-2 for front, back, depth buffers */ |
b397c836 EA |
4602 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) |
4603 | dev_priv->fence_reg_start = 3; | |
de151cf6 | 4604 | |
42b5aeab VS |
4605 | if (INTEL_INFO(dev)->gen >= 7 && !IS_VALLEYVIEW(dev)) |
4606 | dev_priv->num_fence_regs = 32; | |
4607 | else if (INTEL_INFO(dev)->gen >= 4 || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) | |
de151cf6 JB |
4608 | dev_priv->num_fence_regs = 16; |
4609 | else | |
4610 | dev_priv->num_fence_regs = 8; | |
4611 | ||
b5aa8a0f | 4612 | /* Initialize fence registers to zero */ |
19b2dbde CW |
4613 | INIT_LIST_HEAD(&dev_priv->mm.fence_list); |
4614 | i915_gem_restore_fences(dev); | |
10ed13e4 | 4615 | |
673a394b | 4616 | i915_gem_detect_bit_6_swizzle(dev); |
6b95a207 | 4617 | init_waitqueue_head(&dev_priv->pending_flip_queue); |
17250b71 | 4618 | |
ce453d81 CW |
4619 | dev_priv->mm.interruptible = true; |
4620 | ||
7dc19d5a DC |
4621 | dev_priv->mm.inactive_shrinker.scan_objects = i915_gem_inactive_scan; |
4622 | dev_priv->mm.inactive_shrinker.count_objects = i915_gem_inactive_count; | |
17250b71 CW |
4623 | dev_priv->mm.inactive_shrinker.seeks = DEFAULT_SEEKS; |
4624 | register_shrinker(&dev_priv->mm.inactive_shrinker); | |
673a394b | 4625 | } |
71acb5eb DA |
4626 | |
4627 | /* | |
4628 | * Create a physically contiguous memory object for this object | |
4629 | * e.g. for cursor + overlay regs | |
4630 | */ | |
995b6762 CW |
4631 | static int i915_gem_init_phys_object(struct drm_device *dev, |
4632 | int id, int size, int align) | |
71acb5eb DA |
4633 | { |
4634 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4635 | struct drm_i915_gem_phys_object *phys_obj; | |
4636 | int ret; | |
4637 | ||
4638 | if (dev_priv->mm.phys_objs[id - 1] || !size) | |
4639 | return 0; | |
4640 | ||
9a298b2a | 4641 | phys_obj = kzalloc(sizeof(struct drm_i915_gem_phys_object), GFP_KERNEL); |
71acb5eb DA |
4642 | if (!phys_obj) |
4643 | return -ENOMEM; | |
4644 | ||
4645 | phys_obj->id = id; | |
4646 | ||
6eeefaf3 | 4647 | phys_obj->handle = drm_pci_alloc(dev, size, align); |
71acb5eb DA |
4648 | if (!phys_obj->handle) { |
4649 | ret = -ENOMEM; | |
4650 | goto kfree_obj; | |
4651 | } | |
4652 | #ifdef CONFIG_X86 | |
4653 | set_memory_wc((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE); | |
4654 | #endif | |
4655 | ||
4656 | dev_priv->mm.phys_objs[id - 1] = phys_obj; | |
4657 | ||
4658 | return 0; | |
4659 | kfree_obj: | |
9a298b2a | 4660 | kfree(phys_obj); |
71acb5eb DA |
4661 | return ret; |
4662 | } | |
4663 | ||
995b6762 | 4664 | static void i915_gem_free_phys_object(struct drm_device *dev, int id) |
71acb5eb DA |
4665 | { |
4666 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4667 | struct drm_i915_gem_phys_object *phys_obj; | |
4668 | ||
4669 | if (!dev_priv->mm.phys_objs[id - 1]) | |
4670 | return; | |
4671 | ||
4672 | phys_obj = dev_priv->mm.phys_objs[id - 1]; | |
4673 | if (phys_obj->cur_obj) { | |
4674 | i915_gem_detach_phys_object(dev, phys_obj->cur_obj); | |
4675 | } | |
4676 | ||
4677 | #ifdef CONFIG_X86 | |
4678 | set_memory_wb((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE); | |
4679 | #endif | |
4680 | drm_pci_free(dev, phys_obj->handle); | |
4681 | kfree(phys_obj); | |
4682 | dev_priv->mm.phys_objs[id - 1] = NULL; | |
4683 | } | |
4684 | ||
4685 | void i915_gem_free_all_phys_object(struct drm_device *dev) | |
4686 | { | |
4687 | int i; | |
4688 | ||
260883c8 | 4689 | for (i = I915_GEM_PHYS_CURSOR_0; i <= I915_MAX_PHYS_OBJECT; i++) |
71acb5eb DA |
4690 | i915_gem_free_phys_object(dev, i); |
4691 | } | |
4692 | ||
4693 | void i915_gem_detach_phys_object(struct drm_device *dev, | |
05394f39 | 4694 | struct drm_i915_gem_object *obj) |
71acb5eb | 4695 | { |
496ad9aa | 4696 | struct address_space *mapping = file_inode(obj->base.filp)->i_mapping; |
e5281ccd | 4697 | char *vaddr; |
71acb5eb | 4698 | int i; |
71acb5eb DA |
4699 | int page_count; |
4700 | ||
05394f39 | 4701 | if (!obj->phys_obj) |
71acb5eb | 4702 | return; |
05394f39 | 4703 | vaddr = obj->phys_obj->handle->vaddr; |
71acb5eb | 4704 | |
05394f39 | 4705 | page_count = obj->base.size / PAGE_SIZE; |
71acb5eb | 4706 | for (i = 0; i < page_count; i++) { |
5949eac4 | 4707 | struct page *page = shmem_read_mapping_page(mapping, i); |
e5281ccd CW |
4708 | if (!IS_ERR(page)) { |
4709 | char *dst = kmap_atomic(page); | |
4710 | memcpy(dst, vaddr + i*PAGE_SIZE, PAGE_SIZE); | |
4711 | kunmap_atomic(dst); | |
4712 | ||
4713 | drm_clflush_pages(&page, 1); | |
4714 | ||
4715 | set_page_dirty(page); | |
4716 | mark_page_accessed(page); | |
4717 | page_cache_release(page); | |
4718 | } | |
71acb5eb | 4719 | } |
e76e9aeb | 4720 | i915_gem_chipset_flush(dev); |
d78b47b9 | 4721 | |
05394f39 CW |
4722 | obj->phys_obj->cur_obj = NULL; |
4723 | obj->phys_obj = NULL; | |
71acb5eb DA |
4724 | } |
4725 | ||
4726 | int | |
4727 | i915_gem_attach_phys_object(struct drm_device *dev, | |
05394f39 | 4728 | struct drm_i915_gem_object *obj, |
6eeefaf3 CW |
4729 | int id, |
4730 | int align) | |
71acb5eb | 4731 | { |
496ad9aa | 4732 | struct address_space *mapping = file_inode(obj->base.filp)->i_mapping; |
71acb5eb | 4733 | drm_i915_private_t *dev_priv = dev->dev_private; |
71acb5eb DA |
4734 | int ret = 0; |
4735 | int page_count; | |
4736 | int i; | |
4737 | ||
4738 | if (id > I915_MAX_PHYS_OBJECT) | |
4739 | return -EINVAL; | |
4740 | ||
05394f39 CW |
4741 | if (obj->phys_obj) { |
4742 | if (obj->phys_obj->id == id) | |
71acb5eb DA |
4743 | return 0; |
4744 | i915_gem_detach_phys_object(dev, obj); | |
4745 | } | |
4746 | ||
71acb5eb DA |
4747 | /* create a new object */ |
4748 | if (!dev_priv->mm.phys_objs[id - 1]) { | |
4749 | ret = i915_gem_init_phys_object(dev, id, | |
05394f39 | 4750 | obj->base.size, align); |
71acb5eb | 4751 | if (ret) { |
05394f39 CW |
4752 | DRM_ERROR("failed to init phys object %d size: %zu\n", |
4753 | id, obj->base.size); | |
e5281ccd | 4754 | return ret; |
71acb5eb DA |
4755 | } |
4756 | } | |
4757 | ||
4758 | /* bind to the object */ | |
05394f39 CW |
4759 | obj->phys_obj = dev_priv->mm.phys_objs[id - 1]; |
4760 | obj->phys_obj->cur_obj = obj; | |
71acb5eb | 4761 | |
05394f39 | 4762 | page_count = obj->base.size / PAGE_SIZE; |
71acb5eb DA |
4763 | |
4764 | for (i = 0; i < page_count; i++) { | |
e5281ccd CW |
4765 | struct page *page; |
4766 | char *dst, *src; | |
4767 | ||
5949eac4 | 4768 | page = shmem_read_mapping_page(mapping, i); |
e5281ccd CW |
4769 | if (IS_ERR(page)) |
4770 | return PTR_ERR(page); | |
71acb5eb | 4771 | |
ff75b9bc | 4772 | src = kmap_atomic(page); |
05394f39 | 4773 | dst = obj->phys_obj->handle->vaddr + (i * PAGE_SIZE); |
71acb5eb | 4774 | memcpy(dst, src, PAGE_SIZE); |
3e4d3af5 | 4775 | kunmap_atomic(src); |
71acb5eb | 4776 | |
e5281ccd CW |
4777 | mark_page_accessed(page); |
4778 | page_cache_release(page); | |
4779 | } | |
d78b47b9 | 4780 | |
71acb5eb | 4781 | return 0; |
71acb5eb DA |
4782 | } |
4783 | ||
4784 | static int | |
05394f39 CW |
4785 | i915_gem_phys_pwrite(struct drm_device *dev, |
4786 | struct drm_i915_gem_object *obj, | |
71acb5eb DA |
4787 | struct drm_i915_gem_pwrite *args, |
4788 | struct drm_file *file_priv) | |
4789 | { | |
05394f39 | 4790 | void *vaddr = obj->phys_obj->handle->vaddr + args->offset; |
2bb4629a | 4791 | char __user *user_data = to_user_ptr(args->data_ptr); |
71acb5eb | 4792 | |
b47b30cc CW |
4793 | if (__copy_from_user_inatomic_nocache(vaddr, user_data, args->size)) { |
4794 | unsigned long unwritten; | |
4795 | ||
4796 | /* The physical object once assigned is fixed for the lifetime | |
4797 | * of the obj, so we can safely drop the lock and continue | |
4798 | * to access vaddr. | |
4799 | */ | |
4800 | mutex_unlock(&dev->struct_mutex); | |
4801 | unwritten = copy_from_user(vaddr, user_data, args->size); | |
4802 | mutex_lock(&dev->struct_mutex); | |
4803 | if (unwritten) | |
4804 | return -EFAULT; | |
4805 | } | |
71acb5eb | 4806 | |
e76e9aeb | 4807 | i915_gem_chipset_flush(dev); |
71acb5eb DA |
4808 | return 0; |
4809 | } | |
b962442e | 4810 | |
f787a5f5 | 4811 | void i915_gem_release(struct drm_device *dev, struct drm_file *file) |
b962442e | 4812 | { |
f787a5f5 | 4813 | struct drm_i915_file_private *file_priv = file->driver_priv; |
b962442e EA |
4814 | |
4815 | /* Clean up our request list when the client is going away, so that | |
4816 | * later retire_requests won't dereference our soon-to-be-gone | |
4817 | * file_priv. | |
4818 | */ | |
1c25595f | 4819 | spin_lock(&file_priv->mm.lock); |
f787a5f5 CW |
4820 | while (!list_empty(&file_priv->mm.request_list)) { |
4821 | struct drm_i915_gem_request *request; | |
4822 | ||
4823 | request = list_first_entry(&file_priv->mm.request_list, | |
4824 | struct drm_i915_gem_request, | |
4825 | client_list); | |
4826 | list_del(&request->client_list); | |
4827 | request->file_priv = NULL; | |
4828 | } | |
1c25595f | 4829 | spin_unlock(&file_priv->mm.lock); |
b962442e | 4830 | } |
31169714 | 4831 | |
5774506f CW |
4832 | static bool mutex_is_locked_by(struct mutex *mutex, struct task_struct *task) |
4833 | { | |
4834 | if (!mutex_is_locked(mutex)) | |
4835 | return false; | |
4836 | ||
4837 | #if defined(CONFIG_SMP) || defined(CONFIG_DEBUG_MUTEXES) | |
4838 | return mutex->owner == task; | |
4839 | #else | |
4840 | /* Since UP may be pre-empted, we cannot assume that we own the lock */ | |
4841 | return false; | |
4842 | #endif | |
4843 | } | |
4844 | ||
7dc19d5a DC |
4845 | static unsigned long |
4846 | i915_gem_inactive_count(struct shrinker *shrinker, struct shrink_control *sc) | |
31169714 | 4847 | { |
17250b71 CW |
4848 | struct drm_i915_private *dev_priv = |
4849 | container_of(shrinker, | |
4850 | struct drm_i915_private, | |
4851 | mm.inactive_shrinker); | |
4852 | struct drm_device *dev = dev_priv->dev; | |
6c085a72 | 4853 | struct drm_i915_gem_object *obj; |
5774506f | 4854 | bool unlock = true; |
7dc19d5a | 4855 | unsigned long count; |
17250b71 | 4856 | |
5774506f CW |
4857 | if (!mutex_trylock(&dev->struct_mutex)) { |
4858 | if (!mutex_is_locked_by(&dev->struct_mutex, current)) | |
d3227046 | 4859 | return 0; |
5774506f | 4860 | |
677feac2 | 4861 | if (dev_priv->mm.shrinker_no_lock_stealing) |
d3227046 | 4862 | return 0; |
677feac2 | 4863 | |
5774506f CW |
4864 | unlock = false; |
4865 | } | |
31169714 | 4866 | |
7dc19d5a | 4867 | count = 0; |
35c20a60 | 4868 | list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) |
a5570178 | 4869 | if (obj->pages_pin_count == 0) |
7dc19d5a | 4870 | count += obj->base.size >> PAGE_SHIFT; |
fcb4a578 BW |
4871 | |
4872 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) { | |
4873 | if (obj->active) | |
4874 | continue; | |
4875 | ||
a5570178 | 4876 | if (obj->pin_count == 0 && obj->pages_pin_count == 0) |
7dc19d5a | 4877 | count += obj->base.size >> PAGE_SHIFT; |
fcb4a578 | 4878 | } |
17250b71 | 4879 | |
5774506f CW |
4880 | if (unlock) |
4881 | mutex_unlock(&dev->struct_mutex); | |
7dc19d5a | 4882 | return count; |
31169714 | 4883 | } |
a70a3148 BW |
4884 | |
4885 | /* All the new VM stuff */ | |
4886 | unsigned long i915_gem_obj_offset(struct drm_i915_gem_object *o, | |
4887 | struct i915_address_space *vm) | |
4888 | { | |
4889 | struct drm_i915_private *dev_priv = o->base.dev->dev_private; | |
4890 | struct i915_vma *vma; | |
4891 | ||
4892 | if (vm == &dev_priv->mm.aliasing_ppgtt->base) | |
4893 | vm = &dev_priv->gtt.base; | |
4894 | ||
4895 | BUG_ON(list_empty(&o->vma_list)); | |
4896 | list_for_each_entry(vma, &o->vma_list, vma_link) { | |
4897 | if (vma->vm == vm) | |
4898 | return vma->node.start; | |
4899 | ||
4900 | } | |
4901 | return -1; | |
4902 | } | |
4903 | ||
4904 | bool i915_gem_obj_bound(struct drm_i915_gem_object *o, | |
4905 | struct i915_address_space *vm) | |
4906 | { | |
4907 | struct i915_vma *vma; | |
4908 | ||
4909 | list_for_each_entry(vma, &o->vma_list, vma_link) | |
8b9c2b94 | 4910 | if (vma->vm == vm && drm_mm_node_allocated(&vma->node)) |
a70a3148 BW |
4911 | return true; |
4912 | ||
4913 | return false; | |
4914 | } | |
4915 | ||
4916 | bool i915_gem_obj_bound_any(struct drm_i915_gem_object *o) | |
4917 | { | |
5a1d5eb0 | 4918 | struct i915_vma *vma; |
a70a3148 | 4919 | |
5a1d5eb0 CW |
4920 | list_for_each_entry(vma, &o->vma_list, vma_link) |
4921 | if (drm_mm_node_allocated(&vma->node)) | |
a70a3148 BW |
4922 | return true; |
4923 | ||
4924 | return false; | |
4925 | } | |
4926 | ||
4927 | unsigned long i915_gem_obj_size(struct drm_i915_gem_object *o, | |
4928 | struct i915_address_space *vm) | |
4929 | { | |
4930 | struct drm_i915_private *dev_priv = o->base.dev->dev_private; | |
4931 | struct i915_vma *vma; | |
4932 | ||
4933 | if (vm == &dev_priv->mm.aliasing_ppgtt->base) | |
4934 | vm = &dev_priv->gtt.base; | |
4935 | ||
4936 | BUG_ON(list_empty(&o->vma_list)); | |
4937 | ||
4938 | list_for_each_entry(vma, &o->vma_list, vma_link) | |
4939 | if (vma->vm == vm) | |
4940 | return vma->node.size; | |
4941 | ||
4942 | return 0; | |
4943 | } | |
4944 | ||
7dc19d5a DC |
4945 | static unsigned long |
4946 | i915_gem_inactive_scan(struct shrinker *shrinker, struct shrink_control *sc) | |
4947 | { | |
4948 | struct drm_i915_private *dev_priv = | |
4949 | container_of(shrinker, | |
4950 | struct drm_i915_private, | |
4951 | mm.inactive_shrinker); | |
4952 | struct drm_device *dev = dev_priv->dev; | |
4953 | int nr_to_scan = sc->nr_to_scan; | |
4954 | unsigned long freed; | |
4955 | bool unlock = true; | |
4956 | ||
4957 | if (!mutex_trylock(&dev->struct_mutex)) { | |
4958 | if (!mutex_is_locked_by(&dev->struct_mutex, current)) | |
d3227046 | 4959 | return SHRINK_STOP; |
7dc19d5a DC |
4960 | |
4961 | if (dev_priv->mm.shrinker_no_lock_stealing) | |
d3227046 | 4962 | return SHRINK_STOP; |
7dc19d5a DC |
4963 | |
4964 | unlock = false; | |
4965 | } | |
4966 | ||
4967 | freed = i915_gem_purge(dev_priv, nr_to_scan); | |
4968 | if (freed < nr_to_scan) | |
4969 | freed += __i915_gem_shrink(dev_priv, nr_to_scan, | |
4970 | false); | |
4971 | if (freed < nr_to_scan) | |
4972 | freed += i915_gem_shrink_all(dev_priv); | |
4973 | ||
4974 | if (unlock) | |
4975 | mutex_unlock(&dev->struct_mutex); | |
4976 | return freed; | |
4977 | } |