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Commit | Line | Data |
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673a394b EA |
1 | /* |
2 | * Copyright © 2008 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | * | |
26 | */ | |
27 | ||
28 | #include "drmP.h" | |
29 | #include "drm.h" | |
30 | #include "i915_drm.h" | |
31 | #include "i915_drv.h" | |
1c5d22f7 | 32 | #include "i915_trace.h" |
652c393a | 33 | #include "intel_drv.h" |
5949eac4 | 34 | #include <linux/shmem_fs.h> |
5a0e3ad6 | 35 | #include <linux/slab.h> |
673a394b | 36 | #include <linux/swap.h> |
79e53945 | 37 | #include <linux/pci.h> |
1286ff73 | 38 | #include <linux/dma-buf.h> |
673a394b | 39 | |
05394f39 CW |
40 | static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj); |
41 | static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj); | |
88241785 CW |
42 | static __must_check int i915_gem_object_bind_to_gtt(struct drm_i915_gem_object *obj, |
43 | unsigned alignment, | |
86a1ee26 CW |
44 | bool map_and_fenceable, |
45 | bool nonblocking); | |
05394f39 CW |
46 | static int i915_gem_phys_pwrite(struct drm_device *dev, |
47 | struct drm_i915_gem_object *obj, | |
71acb5eb | 48 | struct drm_i915_gem_pwrite *args, |
05394f39 | 49 | struct drm_file *file); |
673a394b | 50 | |
61050808 CW |
51 | static void i915_gem_write_fence(struct drm_device *dev, int reg, |
52 | struct drm_i915_gem_object *obj); | |
53 | static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj, | |
54 | struct drm_i915_fence_reg *fence, | |
55 | bool enable); | |
56 | ||
17250b71 | 57 | static int i915_gem_inactive_shrink(struct shrinker *shrinker, |
1495f230 | 58 | struct shrink_control *sc); |
6c085a72 CW |
59 | static long i915_gem_purge(struct drm_i915_private *dev_priv, long target); |
60 | static void i915_gem_shrink_all(struct drm_i915_private *dev_priv); | |
8c59967c | 61 | static void i915_gem_object_truncate(struct drm_i915_gem_object *obj); |
31169714 | 62 | |
61050808 CW |
63 | static inline void i915_gem_object_fence_lost(struct drm_i915_gem_object *obj) |
64 | { | |
65 | if (obj->tiling_mode) | |
66 | i915_gem_release_mmap(obj); | |
67 | ||
68 | /* As we do not have an associated fence register, we will force | |
69 | * a tiling change if we ever need to acquire one. | |
70 | */ | |
5d82e3e6 | 71 | obj->fence_dirty = false; |
61050808 CW |
72 | obj->fence_reg = I915_FENCE_REG_NONE; |
73 | } | |
74 | ||
73aa808f CW |
75 | /* some bookkeeping */ |
76 | static void i915_gem_info_add_obj(struct drm_i915_private *dev_priv, | |
77 | size_t size) | |
78 | { | |
79 | dev_priv->mm.object_count++; | |
80 | dev_priv->mm.object_memory += size; | |
81 | } | |
82 | ||
83 | static void i915_gem_info_remove_obj(struct drm_i915_private *dev_priv, | |
84 | size_t size) | |
85 | { | |
86 | dev_priv->mm.object_count--; | |
87 | dev_priv->mm.object_memory -= size; | |
88 | } | |
89 | ||
21dd3734 CW |
90 | static int |
91 | i915_gem_wait_for_error(struct drm_device *dev) | |
30dbf0c0 CW |
92 | { |
93 | struct drm_i915_private *dev_priv = dev->dev_private; | |
94 | struct completion *x = &dev_priv->error_completion; | |
95 | unsigned long flags; | |
96 | int ret; | |
97 | ||
98 | if (!atomic_read(&dev_priv->mm.wedged)) | |
99 | return 0; | |
100 | ||
0a6759c6 DV |
101 | /* |
102 | * Only wait 10 seconds for the gpu reset to complete to avoid hanging | |
103 | * userspace. If it takes that long something really bad is going on and | |
104 | * we should simply try to bail out and fail as gracefully as possible. | |
105 | */ | |
106 | ret = wait_for_completion_interruptible_timeout(x, 10*HZ); | |
107 | if (ret == 0) { | |
108 | DRM_ERROR("Timed out waiting for the gpu reset to complete\n"); | |
109 | return -EIO; | |
110 | } else if (ret < 0) { | |
30dbf0c0 | 111 | return ret; |
0a6759c6 | 112 | } |
30dbf0c0 | 113 | |
21dd3734 CW |
114 | if (atomic_read(&dev_priv->mm.wedged)) { |
115 | /* GPU is hung, bump the completion count to account for | |
116 | * the token we just consumed so that we never hit zero and | |
117 | * end up waiting upon a subsequent completion event that | |
118 | * will never happen. | |
119 | */ | |
120 | spin_lock_irqsave(&x->wait.lock, flags); | |
121 | x->done++; | |
122 | spin_unlock_irqrestore(&x->wait.lock, flags); | |
123 | } | |
124 | return 0; | |
30dbf0c0 CW |
125 | } |
126 | ||
54cf91dc | 127 | int i915_mutex_lock_interruptible(struct drm_device *dev) |
76c1dec1 | 128 | { |
76c1dec1 CW |
129 | int ret; |
130 | ||
21dd3734 | 131 | ret = i915_gem_wait_for_error(dev); |
76c1dec1 CW |
132 | if (ret) |
133 | return ret; | |
134 | ||
135 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
136 | if (ret) | |
137 | return ret; | |
138 | ||
23bc5982 | 139 | WARN_ON(i915_verify_lists(dev)); |
76c1dec1 CW |
140 | return 0; |
141 | } | |
30dbf0c0 | 142 | |
7d1c4804 | 143 | static inline bool |
05394f39 | 144 | i915_gem_object_is_inactive(struct drm_i915_gem_object *obj) |
7d1c4804 | 145 | { |
6c085a72 | 146 | return obj->gtt_space && !obj->active; |
7d1c4804 CW |
147 | } |
148 | ||
79e53945 JB |
149 | int |
150 | i915_gem_init_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 151 | struct drm_file *file) |
79e53945 JB |
152 | { |
153 | struct drm_i915_gem_init *args = data; | |
2021746e | 154 | |
7bb6fb8d DV |
155 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
156 | return -ENODEV; | |
157 | ||
2021746e CW |
158 | if (args->gtt_start >= args->gtt_end || |
159 | (args->gtt_end | args->gtt_start) & (PAGE_SIZE - 1)) | |
160 | return -EINVAL; | |
79e53945 | 161 | |
f534bc0b DV |
162 | /* GEM with user mode setting was never supported on ilk and later. */ |
163 | if (INTEL_INFO(dev)->gen >= 5) | |
164 | return -ENODEV; | |
165 | ||
79e53945 | 166 | mutex_lock(&dev->struct_mutex); |
644ec02b DV |
167 | i915_gem_init_global_gtt(dev, args->gtt_start, |
168 | args->gtt_end, args->gtt_end); | |
673a394b EA |
169 | mutex_unlock(&dev->struct_mutex); |
170 | ||
2021746e | 171 | return 0; |
673a394b EA |
172 | } |
173 | ||
5a125c3c EA |
174 | int |
175 | i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 176 | struct drm_file *file) |
5a125c3c | 177 | { |
73aa808f | 178 | struct drm_i915_private *dev_priv = dev->dev_private; |
5a125c3c | 179 | struct drm_i915_gem_get_aperture *args = data; |
6299f992 CW |
180 | struct drm_i915_gem_object *obj; |
181 | size_t pinned; | |
5a125c3c | 182 | |
6299f992 | 183 | pinned = 0; |
73aa808f | 184 | mutex_lock(&dev->struct_mutex); |
6c085a72 | 185 | list_for_each_entry(obj, &dev_priv->mm.bound_list, gtt_list) |
1b50247a CW |
186 | if (obj->pin_count) |
187 | pinned += obj->gtt_space->size; | |
73aa808f | 188 | mutex_unlock(&dev->struct_mutex); |
5a125c3c | 189 | |
6299f992 | 190 | args->aper_size = dev_priv->mm.gtt_total; |
0206e353 | 191 | args->aper_available_size = args->aper_size - pinned; |
6299f992 | 192 | |
5a125c3c EA |
193 | return 0; |
194 | } | |
195 | ||
ff72145b DA |
196 | static int |
197 | i915_gem_create(struct drm_file *file, | |
198 | struct drm_device *dev, | |
199 | uint64_t size, | |
200 | uint32_t *handle_p) | |
673a394b | 201 | { |
05394f39 | 202 | struct drm_i915_gem_object *obj; |
a1a2d1d3 PP |
203 | int ret; |
204 | u32 handle; | |
673a394b | 205 | |
ff72145b | 206 | size = roundup(size, PAGE_SIZE); |
8ffc0246 CW |
207 | if (size == 0) |
208 | return -EINVAL; | |
673a394b EA |
209 | |
210 | /* Allocate the new object */ | |
ff72145b | 211 | obj = i915_gem_alloc_object(dev, size); |
673a394b EA |
212 | if (obj == NULL) |
213 | return -ENOMEM; | |
214 | ||
05394f39 | 215 | ret = drm_gem_handle_create(file, &obj->base, &handle); |
1dfd9754 | 216 | if (ret) { |
05394f39 CW |
217 | drm_gem_object_release(&obj->base); |
218 | i915_gem_info_remove_obj(dev->dev_private, obj->base.size); | |
202f2fef | 219 | kfree(obj); |
673a394b | 220 | return ret; |
1dfd9754 | 221 | } |
673a394b | 222 | |
202f2fef | 223 | /* drop reference from allocate - handle holds it now */ |
05394f39 | 224 | drm_gem_object_unreference(&obj->base); |
202f2fef CW |
225 | trace_i915_gem_object_create(obj); |
226 | ||
ff72145b | 227 | *handle_p = handle; |
673a394b EA |
228 | return 0; |
229 | } | |
230 | ||
ff72145b DA |
231 | int |
232 | i915_gem_dumb_create(struct drm_file *file, | |
233 | struct drm_device *dev, | |
234 | struct drm_mode_create_dumb *args) | |
235 | { | |
236 | /* have to work out size/pitch and return them */ | |
ed0291fd | 237 | args->pitch = ALIGN(args->width * ((args->bpp + 7) / 8), 64); |
ff72145b DA |
238 | args->size = args->pitch * args->height; |
239 | return i915_gem_create(file, dev, | |
240 | args->size, &args->handle); | |
241 | } | |
242 | ||
243 | int i915_gem_dumb_destroy(struct drm_file *file, | |
244 | struct drm_device *dev, | |
245 | uint32_t handle) | |
246 | { | |
247 | return drm_gem_handle_delete(file, handle); | |
248 | } | |
249 | ||
250 | /** | |
251 | * Creates a new mm object and returns a handle to it. | |
252 | */ | |
253 | int | |
254 | i915_gem_create_ioctl(struct drm_device *dev, void *data, | |
255 | struct drm_file *file) | |
256 | { | |
257 | struct drm_i915_gem_create *args = data; | |
63ed2cb2 | 258 | |
ff72145b DA |
259 | return i915_gem_create(file, dev, |
260 | args->size, &args->handle); | |
261 | } | |
262 | ||
05394f39 | 263 | static int i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj) |
280b713b | 264 | { |
05394f39 | 265 | drm_i915_private_t *dev_priv = obj->base.dev->dev_private; |
280b713b EA |
266 | |
267 | return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 && | |
05394f39 | 268 | obj->tiling_mode != I915_TILING_NONE; |
280b713b EA |
269 | } |
270 | ||
8461d226 DV |
271 | static inline int |
272 | __copy_to_user_swizzled(char __user *cpu_vaddr, | |
273 | const char *gpu_vaddr, int gpu_offset, | |
274 | int length) | |
275 | { | |
276 | int ret, cpu_offset = 0; | |
277 | ||
278 | while (length > 0) { | |
279 | int cacheline_end = ALIGN(gpu_offset + 1, 64); | |
280 | int this_length = min(cacheline_end - gpu_offset, length); | |
281 | int swizzled_gpu_offset = gpu_offset ^ 64; | |
282 | ||
283 | ret = __copy_to_user(cpu_vaddr + cpu_offset, | |
284 | gpu_vaddr + swizzled_gpu_offset, | |
285 | this_length); | |
286 | if (ret) | |
287 | return ret + length; | |
288 | ||
289 | cpu_offset += this_length; | |
290 | gpu_offset += this_length; | |
291 | length -= this_length; | |
292 | } | |
293 | ||
294 | return 0; | |
295 | } | |
296 | ||
8c59967c | 297 | static inline int |
4f0c7cfb BW |
298 | __copy_from_user_swizzled(char *gpu_vaddr, int gpu_offset, |
299 | const char __user *cpu_vaddr, | |
8c59967c DV |
300 | int length) |
301 | { | |
302 | int ret, cpu_offset = 0; | |
303 | ||
304 | while (length > 0) { | |
305 | int cacheline_end = ALIGN(gpu_offset + 1, 64); | |
306 | int this_length = min(cacheline_end - gpu_offset, length); | |
307 | int swizzled_gpu_offset = gpu_offset ^ 64; | |
308 | ||
309 | ret = __copy_from_user(gpu_vaddr + swizzled_gpu_offset, | |
310 | cpu_vaddr + cpu_offset, | |
311 | this_length); | |
312 | if (ret) | |
313 | return ret + length; | |
314 | ||
315 | cpu_offset += this_length; | |
316 | gpu_offset += this_length; | |
317 | length -= this_length; | |
318 | } | |
319 | ||
320 | return 0; | |
321 | } | |
322 | ||
d174bd64 DV |
323 | /* Per-page copy function for the shmem pread fastpath. |
324 | * Flushes invalid cachelines before reading the target if | |
325 | * needs_clflush is set. */ | |
eb01459f | 326 | static int |
d174bd64 DV |
327 | shmem_pread_fast(struct page *page, int shmem_page_offset, int page_length, |
328 | char __user *user_data, | |
329 | bool page_do_bit17_swizzling, bool needs_clflush) | |
330 | { | |
331 | char *vaddr; | |
332 | int ret; | |
333 | ||
e7e58eb5 | 334 | if (unlikely(page_do_bit17_swizzling)) |
d174bd64 DV |
335 | return -EINVAL; |
336 | ||
337 | vaddr = kmap_atomic(page); | |
338 | if (needs_clflush) | |
339 | drm_clflush_virt_range(vaddr + shmem_page_offset, | |
340 | page_length); | |
341 | ret = __copy_to_user_inatomic(user_data, | |
342 | vaddr + shmem_page_offset, | |
343 | page_length); | |
344 | kunmap_atomic(vaddr); | |
345 | ||
346 | return ret; | |
347 | } | |
348 | ||
23c18c71 DV |
349 | static void |
350 | shmem_clflush_swizzled_range(char *addr, unsigned long length, | |
351 | bool swizzled) | |
352 | { | |
e7e58eb5 | 353 | if (unlikely(swizzled)) { |
23c18c71 DV |
354 | unsigned long start = (unsigned long) addr; |
355 | unsigned long end = (unsigned long) addr + length; | |
356 | ||
357 | /* For swizzling simply ensure that we always flush both | |
358 | * channels. Lame, but simple and it works. Swizzled | |
359 | * pwrite/pread is far from a hotpath - current userspace | |
360 | * doesn't use it at all. */ | |
361 | start = round_down(start, 128); | |
362 | end = round_up(end, 128); | |
363 | ||
364 | drm_clflush_virt_range((void *)start, end - start); | |
365 | } else { | |
366 | drm_clflush_virt_range(addr, length); | |
367 | } | |
368 | ||
369 | } | |
370 | ||
d174bd64 DV |
371 | /* Only difference to the fast-path function is that this can handle bit17 |
372 | * and uses non-atomic copy and kmap functions. */ | |
373 | static int | |
374 | shmem_pread_slow(struct page *page, int shmem_page_offset, int page_length, | |
375 | char __user *user_data, | |
376 | bool page_do_bit17_swizzling, bool needs_clflush) | |
377 | { | |
378 | char *vaddr; | |
379 | int ret; | |
380 | ||
381 | vaddr = kmap(page); | |
382 | if (needs_clflush) | |
23c18c71 DV |
383 | shmem_clflush_swizzled_range(vaddr + shmem_page_offset, |
384 | page_length, | |
385 | page_do_bit17_swizzling); | |
d174bd64 DV |
386 | |
387 | if (page_do_bit17_swizzling) | |
388 | ret = __copy_to_user_swizzled(user_data, | |
389 | vaddr, shmem_page_offset, | |
390 | page_length); | |
391 | else | |
392 | ret = __copy_to_user(user_data, | |
393 | vaddr + shmem_page_offset, | |
394 | page_length); | |
395 | kunmap(page); | |
396 | ||
397 | return ret; | |
398 | } | |
399 | ||
eb01459f | 400 | static int |
dbf7bff0 DV |
401 | i915_gem_shmem_pread(struct drm_device *dev, |
402 | struct drm_i915_gem_object *obj, | |
403 | struct drm_i915_gem_pread *args, | |
404 | struct drm_file *file) | |
eb01459f | 405 | { |
05394f39 | 406 | struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping; |
8461d226 | 407 | char __user *user_data; |
eb01459f | 408 | ssize_t remain; |
8461d226 | 409 | loff_t offset; |
eb2c0c81 | 410 | int shmem_page_offset, page_length, ret = 0; |
8461d226 | 411 | int obj_do_bit17_swizzling, page_do_bit17_swizzling; |
dbf7bff0 | 412 | int hit_slowpath = 0; |
96d79b52 | 413 | int prefaulted = 0; |
8489731c | 414 | int needs_clflush = 0; |
692a576b | 415 | int release_page; |
eb01459f | 416 | |
8461d226 | 417 | user_data = (char __user *) (uintptr_t) args->data_ptr; |
eb01459f EA |
418 | remain = args->size; |
419 | ||
8461d226 | 420 | obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj); |
eb01459f | 421 | |
8489731c DV |
422 | if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU)) { |
423 | /* If we're not in the cpu read domain, set ourself into the gtt | |
424 | * read domain and manually flush cachelines (if required). This | |
425 | * optimizes for the case when the gpu will dirty the data | |
426 | * anyway again before the next pread happens. */ | |
427 | if (obj->cache_level == I915_CACHE_NONE) | |
428 | needs_clflush = 1; | |
6c085a72 CW |
429 | if (obj->gtt_space) { |
430 | ret = i915_gem_object_set_to_gtt_domain(obj, false); | |
431 | if (ret) | |
432 | return ret; | |
433 | } | |
8489731c | 434 | } |
eb01459f | 435 | |
8461d226 | 436 | offset = args->offset; |
eb01459f EA |
437 | |
438 | while (remain > 0) { | |
e5281ccd CW |
439 | struct page *page; |
440 | ||
eb01459f EA |
441 | /* Operation in this page |
442 | * | |
eb01459f | 443 | * shmem_page_offset = offset within page in shmem file |
eb01459f EA |
444 | * page_length = bytes to copy for this page |
445 | */ | |
c8cbbb8b | 446 | shmem_page_offset = offset_in_page(offset); |
eb01459f EA |
447 | page_length = remain; |
448 | if ((shmem_page_offset + page_length) > PAGE_SIZE) | |
449 | page_length = PAGE_SIZE - shmem_page_offset; | |
eb01459f | 450 | |
692a576b DV |
451 | if (obj->pages) { |
452 | page = obj->pages[offset >> PAGE_SHIFT]; | |
453 | release_page = 0; | |
454 | } else { | |
455 | page = shmem_read_mapping_page(mapping, offset >> PAGE_SHIFT); | |
456 | if (IS_ERR(page)) { | |
457 | ret = PTR_ERR(page); | |
458 | goto out; | |
459 | } | |
460 | release_page = 1; | |
b65552f0 | 461 | } |
e5281ccd | 462 | |
8461d226 DV |
463 | page_do_bit17_swizzling = obj_do_bit17_swizzling && |
464 | (page_to_phys(page) & (1 << 17)) != 0; | |
465 | ||
d174bd64 DV |
466 | ret = shmem_pread_fast(page, shmem_page_offset, page_length, |
467 | user_data, page_do_bit17_swizzling, | |
468 | needs_clflush); | |
469 | if (ret == 0) | |
470 | goto next_page; | |
dbf7bff0 DV |
471 | |
472 | hit_slowpath = 1; | |
692a576b | 473 | page_cache_get(page); |
dbf7bff0 DV |
474 | mutex_unlock(&dev->struct_mutex); |
475 | ||
96d79b52 | 476 | if (!prefaulted) { |
f56f821f | 477 | ret = fault_in_multipages_writeable(user_data, remain); |
96d79b52 DV |
478 | /* Userspace is tricking us, but we've already clobbered |
479 | * its pages with the prefault and promised to write the | |
480 | * data up to the first fault. Hence ignore any errors | |
481 | * and just continue. */ | |
482 | (void)ret; | |
483 | prefaulted = 1; | |
484 | } | |
eb01459f | 485 | |
d174bd64 DV |
486 | ret = shmem_pread_slow(page, shmem_page_offset, page_length, |
487 | user_data, page_do_bit17_swizzling, | |
488 | needs_clflush); | |
eb01459f | 489 | |
dbf7bff0 | 490 | mutex_lock(&dev->struct_mutex); |
e5281ccd | 491 | page_cache_release(page); |
dbf7bff0 | 492 | next_page: |
e5281ccd | 493 | mark_page_accessed(page); |
692a576b DV |
494 | if (release_page) |
495 | page_cache_release(page); | |
e5281ccd | 496 | |
8461d226 DV |
497 | if (ret) { |
498 | ret = -EFAULT; | |
499 | goto out; | |
500 | } | |
501 | ||
eb01459f | 502 | remain -= page_length; |
8461d226 | 503 | user_data += page_length; |
eb01459f EA |
504 | offset += page_length; |
505 | } | |
506 | ||
4f27b75d | 507 | out: |
dbf7bff0 DV |
508 | if (hit_slowpath) { |
509 | /* Fixup: Kill any reinstated backing storage pages */ | |
510 | if (obj->madv == __I915_MADV_PURGED) | |
511 | i915_gem_object_truncate(obj); | |
512 | } | |
eb01459f EA |
513 | |
514 | return ret; | |
515 | } | |
516 | ||
673a394b EA |
517 | /** |
518 | * Reads data from the object referenced by handle. | |
519 | * | |
520 | * On error, the contents of *data are undefined. | |
521 | */ | |
522 | int | |
523 | i915_gem_pread_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 524 | struct drm_file *file) |
673a394b EA |
525 | { |
526 | struct drm_i915_gem_pread *args = data; | |
05394f39 | 527 | struct drm_i915_gem_object *obj; |
35b62a89 | 528 | int ret = 0; |
673a394b | 529 | |
51311d0a CW |
530 | if (args->size == 0) |
531 | return 0; | |
532 | ||
533 | if (!access_ok(VERIFY_WRITE, | |
534 | (char __user *)(uintptr_t)args->data_ptr, | |
535 | args->size)) | |
536 | return -EFAULT; | |
537 | ||
4f27b75d | 538 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 539 | if (ret) |
4f27b75d | 540 | return ret; |
673a394b | 541 | |
05394f39 | 542 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 543 | if (&obj->base == NULL) { |
1d7cfea1 CW |
544 | ret = -ENOENT; |
545 | goto unlock; | |
4f27b75d | 546 | } |
673a394b | 547 | |
7dcd2499 | 548 | /* Bounds check source. */ |
05394f39 CW |
549 | if (args->offset > obj->base.size || |
550 | args->size > obj->base.size - args->offset) { | |
ce9d419d | 551 | ret = -EINVAL; |
35b62a89 | 552 | goto out; |
ce9d419d CW |
553 | } |
554 | ||
1286ff73 DV |
555 | /* prime objects have no backing filp to GEM pread/pwrite |
556 | * pages from. | |
557 | */ | |
558 | if (!obj->base.filp) { | |
559 | ret = -EINVAL; | |
560 | goto out; | |
561 | } | |
562 | ||
db53a302 CW |
563 | trace_i915_gem_object_pread(obj, args->offset, args->size); |
564 | ||
dbf7bff0 | 565 | ret = i915_gem_shmem_pread(dev, obj, args, file); |
673a394b | 566 | |
35b62a89 | 567 | out: |
05394f39 | 568 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 569 | unlock: |
4f27b75d | 570 | mutex_unlock(&dev->struct_mutex); |
eb01459f | 571 | return ret; |
673a394b EA |
572 | } |
573 | ||
0839ccb8 KP |
574 | /* This is the fast write path which cannot handle |
575 | * page faults in the source data | |
9b7530cc | 576 | */ |
0839ccb8 KP |
577 | |
578 | static inline int | |
579 | fast_user_write(struct io_mapping *mapping, | |
580 | loff_t page_base, int page_offset, | |
581 | char __user *user_data, | |
582 | int length) | |
9b7530cc | 583 | { |
4f0c7cfb BW |
584 | void __iomem *vaddr_atomic; |
585 | void *vaddr; | |
0839ccb8 | 586 | unsigned long unwritten; |
9b7530cc | 587 | |
3e4d3af5 | 588 | vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base); |
4f0c7cfb BW |
589 | /* We can use the cpu mem copy function because this is X86. */ |
590 | vaddr = (void __force*)vaddr_atomic + page_offset; | |
591 | unwritten = __copy_from_user_inatomic_nocache(vaddr, | |
0839ccb8 | 592 | user_data, length); |
3e4d3af5 | 593 | io_mapping_unmap_atomic(vaddr_atomic); |
fbd5a26d | 594 | return unwritten; |
0839ccb8 KP |
595 | } |
596 | ||
3de09aa3 EA |
597 | /** |
598 | * This is the fast pwrite path, where we copy the data directly from the | |
599 | * user into the GTT, uncached. | |
600 | */ | |
673a394b | 601 | static int |
05394f39 CW |
602 | i915_gem_gtt_pwrite_fast(struct drm_device *dev, |
603 | struct drm_i915_gem_object *obj, | |
3de09aa3 | 604 | struct drm_i915_gem_pwrite *args, |
05394f39 | 605 | struct drm_file *file) |
673a394b | 606 | { |
0839ccb8 | 607 | drm_i915_private_t *dev_priv = dev->dev_private; |
673a394b | 608 | ssize_t remain; |
0839ccb8 | 609 | loff_t offset, page_base; |
673a394b | 610 | char __user *user_data; |
935aaa69 DV |
611 | int page_offset, page_length, ret; |
612 | ||
86a1ee26 | 613 | ret = i915_gem_object_pin(obj, 0, true, true); |
935aaa69 DV |
614 | if (ret) |
615 | goto out; | |
616 | ||
617 | ret = i915_gem_object_set_to_gtt_domain(obj, true); | |
618 | if (ret) | |
619 | goto out_unpin; | |
620 | ||
621 | ret = i915_gem_object_put_fence(obj); | |
622 | if (ret) | |
623 | goto out_unpin; | |
673a394b EA |
624 | |
625 | user_data = (char __user *) (uintptr_t) args->data_ptr; | |
626 | remain = args->size; | |
673a394b | 627 | |
05394f39 | 628 | offset = obj->gtt_offset + args->offset; |
673a394b EA |
629 | |
630 | while (remain > 0) { | |
631 | /* Operation in this page | |
632 | * | |
0839ccb8 KP |
633 | * page_base = page offset within aperture |
634 | * page_offset = offset within page | |
635 | * page_length = bytes to copy for this page | |
673a394b | 636 | */ |
c8cbbb8b CW |
637 | page_base = offset & PAGE_MASK; |
638 | page_offset = offset_in_page(offset); | |
0839ccb8 KP |
639 | page_length = remain; |
640 | if ((page_offset + remain) > PAGE_SIZE) | |
641 | page_length = PAGE_SIZE - page_offset; | |
642 | ||
0839ccb8 | 643 | /* If we get a fault while copying data, then (presumably) our |
3de09aa3 EA |
644 | * source page isn't available. Return the error and we'll |
645 | * retry in the slow path. | |
0839ccb8 | 646 | */ |
fbd5a26d | 647 | if (fast_user_write(dev_priv->mm.gtt_mapping, page_base, |
935aaa69 DV |
648 | page_offset, user_data, page_length)) { |
649 | ret = -EFAULT; | |
650 | goto out_unpin; | |
651 | } | |
673a394b | 652 | |
0839ccb8 KP |
653 | remain -= page_length; |
654 | user_data += page_length; | |
655 | offset += page_length; | |
673a394b | 656 | } |
673a394b | 657 | |
935aaa69 DV |
658 | out_unpin: |
659 | i915_gem_object_unpin(obj); | |
660 | out: | |
3de09aa3 | 661 | return ret; |
673a394b EA |
662 | } |
663 | ||
d174bd64 DV |
664 | /* Per-page copy function for the shmem pwrite fastpath. |
665 | * Flushes invalid cachelines before writing to the target if | |
666 | * needs_clflush_before is set and flushes out any written cachelines after | |
667 | * writing if needs_clflush is set. */ | |
3043c60c | 668 | static int |
d174bd64 DV |
669 | shmem_pwrite_fast(struct page *page, int shmem_page_offset, int page_length, |
670 | char __user *user_data, | |
671 | bool page_do_bit17_swizzling, | |
672 | bool needs_clflush_before, | |
673 | bool needs_clflush_after) | |
673a394b | 674 | { |
d174bd64 | 675 | char *vaddr; |
673a394b | 676 | int ret; |
3de09aa3 | 677 | |
e7e58eb5 | 678 | if (unlikely(page_do_bit17_swizzling)) |
d174bd64 | 679 | return -EINVAL; |
3de09aa3 | 680 | |
d174bd64 DV |
681 | vaddr = kmap_atomic(page); |
682 | if (needs_clflush_before) | |
683 | drm_clflush_virt_range(vaddr + shmem_page_offset, | |
684 | page_length); | |
685 | ret = __copy_from_user_inatomic_nocache(vaddr + shmem_page_offset, | |
686 | user_data, | |
687 | page_length); | |
688 | if (needs_clflush_after) | |
689 | drm_clflush_virt_range(vaddr + shmem_page_offset, | |
690 | page_length); | |
691 | kunmap_atomic(vaddr); | |
3de09aa3 EA |
692 | |
693 | return ret; | |
694 | } | |
695 | ||
d174bd64 DV |
696 | /* Only difference to the fast-path function is that this can handle bit17 |
697 | * and uses non-atomic copy and kmap functions. */ | |
3043c60c | 698 | static int |
d174bd64 DV |
699 | shmem_pwrite_slow(struct page *page, int shmem_page_offset, int page_length, |
700 | char __user *user_data, | |
701 | bool page_do_bit17_swizzling, | |
702 | bool needs_clflush_before, | |
703 | bool needs_clflush_after) | |
673a394b | 704 | { |
d174bd64 DV |
705 | char *vaddr; |
706 | int ret; | |
e5281ccd | 707 | |
d174bd64 | 708 | vaddr = kmap(page); |
e7e58eb5 | 709 | if (unlikely(needs_clflush_before || page_do_bit17_swizzling)) |
23c18c71 DV |
710 | shmem_clflush_swizzled_range(vaddr + shmem_page_offset, |
711 | page_length, | |
712 | page_do_bit17_swizzling); | |
d174bd64 DV |
713 | if (page_do_bit17_swizzling) |
714 | ret = __copy_from_user_swizzled(vaddr, shmem_page_offset, | |
e5281ccd CW |
715 | user_data, |
716 | page_length); | |
d174bd64 DV |
717 | else |
718 | ret = __copy_from_user(vaddr + shmem_page_offset, | |
719 | user_data, | |
720 | page_length); | |
721 | if (needs_clflush_after) | |
23c18c71 DV |
722 | shmem_clflush_swizzled_range(vaddr + shmem_page_offset, |
723 | page_length, | |
724 | page_do_bit17_swizzling); | |
d174bd64 | 725 | kunmap(page); |
40123c1f | 726 | |
d174bd64 | 727 | return ret; |
40123c1f EA |
728 | } |
729 | ||
40123c1f | 730 | static int |
e244a443 DV |
731 | i915_gem_shmem_pwrite(struct drm_device *dev, |
732 | struct drm_i915_gem_object *obj, | |
733 | struct drm_i915_gem_pwrite *args, | |
734 | struct drm_file *file) | |
40123c1f | 735 | { |
05394f39 | 736 | struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping; |
40123c1f | 737 | ssize_t remain; |
8c59967c DV |
738 | loff_t offset; |
739 | char __user *user_data; | |
eb2c0c81 | 740 | int shmem_page_offset, page_length, ret = 0; |
8c59967c | 741 | int obj_do_bit17_swizzling, page_do_bit17_swizzling; |
e244a443 | 742 | int hit_slowpath = 0; |
58642885 DV |
743 | int needs_clflush_after = 0; |
744 | int needs_clflush_before = 0; | |
692a576b | 745 | int release_page; |
40123c1f | 746 | |
8c59967c | 747 | user_data = (char __user *) (uintptr_t) args->data_ptr; |
40123c1f EA |
748 | remain = args->size; |
749 | ||
8c59967c | 750 | obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj); |
40123c1f | 751 | |
58642885 DV |
752 | if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) { |
753 | /* If we're not in the cpu write domain, set ourself into the gtt | |
754 | * write domain and manually flush cachelines (if required). This | |
755 | * optimizes for the case when the gpu will use the data | |
756 | * right away and we therefore have to clflush anyway. */ | |
757 | if (obj->cache_level == I915_CACHE_NONE) | |
758 | needs_clflush_after = 1; | |
6c085a72 CW |
759 | if (obj->gtt_space) { |
760 | ret = i915_gem_object_set_to_gtt_domain(obj, true); | |
761 | if (ret) | |
762 | return ret; | |
763 | } | |
58642885 DV |
764 | } |
765 | /* Same trick applies for invalidate partially written cachelines before | |
766 | * writing. */ | |
767 | if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU) | |
768 | && obj->cache_level == I915_CACHE_NONE) | |
769 | needs_clflush_before = 1; | |
770 | ||
673a394b | 771 | offset = args->offset; |
05394f39 | 772 | obj->dirty = 1; |
673a394b | 773 | |
40123c1f | 774 | while (remain > 0) { |
e5281ccd | 775 | struct page *page; |
58642885 | 776 | int partial_cacheline_write; |
e5281ccd | 777 | |
40123c1f EA |
778 | /* Operation in this page |
779 | * | |
40123c1f | 780 | * shmem_page_offset = offset within page in shmem file |
40123c1f EA |
781 | * page_length = bytes to copy for this page |
782 | */ | |
c8cbbb8b | 783 | shmem_page_offset = offset_in_page(offset); |
40123c1f EA |
784 | |
785 | page_length = remain; | |
786 | if ((shmem_page_offset + page_length) > PAGE_SIZE) | |
787 | page_length = PAGE_SIZE - shmem_page_offset; | |
40123c1f | 788 | |
58642885 DV |
789 | /* If we don't overwrite a cacheline completely we need to be |
790 | * careful to have up-to-date data by first clflushing. Don't | |
791 | * overcomplicate things and flush the entire patch. */ | |
792 | partial_cacheline_write = needs_clflush_before && | |
793 | ((shmem_page_offset | page_length) | |
794 | & (boot_cpu_data.x86_clflush_size - 1)); | |
795 | ||
692a576b DV |
796 | if (obj->pages) { |
797 | page = obj->pages[offset >> PAGE_SHIFT]; | |
798 | release_page = 0; | |
799 | } else { | |
800 | page = shmem_read_mapping_page(mapping, offset >> PAGE_SHIFT); | |
801 | if (IS_ERR(page)) { | |
802 | ret = PTR_ERR(page); | |
803 | goto out; | |
804 | } | |
805 | release_page = 1; | |
e5281ccd CW |
806 | } |
807 | ||
8c59967c DV |
808 | page_do_bit17_swizzling = obj_do_bit17_swizzling && |
809 | (page_to_phys(page) & (1 << 17)) != 0; | |
810 | ||
d174bd64 DV |
811 | ret = shmem_pwrite_fast(page, shmem_page_offset, page_length, |
812 | user_data, page_do_bit17_swizzling, | |
813 | partial_cacheline_write, | |
814 | needs_clflush_after); | |
815 | if (ret == 0) | |
816 | goto next_page; | |
e244a443 DV |
817 | |
818 | hit_slowpath = 1; | |
692a576b | 819 | page_cache_get(page); |
e244a443 DV |
820 | mutex_unlock(&dev->struct_mutex); |
821 | ||
d174bd64 DV |
822 | ret = shmem_pwrite_slow(page, shmem_page_offset, page_length, |
823 | user_data, page_do_bit17_swizzling, | |
824 | partial_cacheline_write, | |
825 | needs_clflush_after); | |
40123c1f | 826 | |
e244a443 | 827 | mutex_lock(&dev->struct_mutex); |
692a576b | 828 | page_cache_release(page); |
e244a443 | 829 | next_page: |
e5281ccd CW |
830 | set_page_dirty(page); |
831 | mark_page_accessed(page); | |
692a576b DV |
832 | if (release_page) |
833 | page_cache_release(page); | |
e5281ccd | 834 | |
8c59967c DV |
835 | if (ret) { |
836 | ret = -EFAULT; | |
837 | goto out; | |
838 | } | |
839 | ||
40123c1f | 840 | remain -= page_length; |
8c59967c | 841 | user_data += page_length; |
40123c1f | 842 | offset += page_length; |
673a394b EA |
843 | } |
844 | ||
fbd5a26d | 845 | out: |
e244a443 DV |
846 | if (hit_slowpath) { |
847 | /* Fixup: Kill any reinstated backing storage pages */ | |
848 | if (obj->madv == __I915_MADV_PURGED) | |
849 | i915_gem_object_truncate(obj); | |
850 | /* and flush dirty cachelines in case the object isn't in the cpu write | |
851 | * domain anymore. */ | |
852 | if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) { | |
853 | i915_gem_clflush_object(obj); | |
854 | intel_gtt_chipset_flush(); | |
855 | } | |
8c59967c | 856 | } |
673a394b | 857 | |
58642885 DV |
858 | if (needs_clflush_after) |
859 | intel_gtt_chipset_flush(); | |
860 | ||
40123c1f | 861 | return ret; |
673a394b EA |
862 | } |
863 | ||
864 | /** | |
865 | * Writes data to the object referenced by handle. | |
866 | * | |
867 | * On error, the contents of the buffer that were to be modified are undefined. | |
868 | */ | |
869 | int | |
870 | i915_gem_pwrite_ioctl(struct drm_device *dev, void *data, | |
fbd5a26d | 871 | struct drm_file *file) |
673a394b EA |
872 | { |
873 | struct drm_i915_gem_pwrite *args = data; | |
05394f39 | 874 | struct drm_i915_gem_object *obj; |
51311d0a CW |
875 | int ret; |
876 | ||
877 | if (args->size == 0) | |
878 | return 0; | |
879 | ||
880 | if (!access_ok(VERIFY_READ, | |
881 | (char __user *)(uintptr_t)args->data_ptr, | |
882 | args->size)) | |
883 | return -EFAULT; | |
884 | ||
f56f821f DV |
885 | ret = fault_in_multipages_readable((char __user *)(uintptr_t)args->data_ptr, |
886 | args->size); | |
51311d0a CW |
887 | if (ret) |
888 | return -EFAULT; | |
673a394b | 889 | |
fbd5a26d | 890 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 891 | if (ret) |
fbd5a26d | 892 | return ret; |
1d7cfea1 | 893 | |
05394f39 | 894 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 895 | if (&obj->base == NULL) { |
1d7cfea1 CW |
896 | ret = -ENOENT; |
897 | goto unlock; | |
fbd5a26d | 898 | } |
673a394b | 899 | |
7dcd2499 | 900 | /* Bounds check destination. */ |
05394f39 CW |
901 | if (args->offset > obj->base.size || |
902 | args->size > obj->base.size - args->offset) { | |
ce9d419d | 903 | ret = -EINVAL; |
35b62a89 | 904 | goto out; |
ce9d419d CW |
905 | } |
906 | ||
1286ff73 DV |
907 | /* prime objects have no backing filp to GEM pread/pwrite |
908 | * pages from. | |
909 | */ | |
910 | if (!obj->base.filp) { | |
911 | ret = -EINVAL; | |
912 | goto out; | |
913 | } | |
914 | ||
db53a302 CW |
915 | trace_i915_gem_object_pwrite(obj, args->offset, args->size); |
916 | ||
935aaa69 | 917 | ret = -EFAULT; |
673a394b EA |
918 | /* We can only do the GTT pwrite on untiled buffers, as otherwise |
919 | * it would end up going through the fenced access, and we'll get | |
920 | * different detiling behavior between reading and writing. | |
921 | * pread/pwrite currently are reading and writing from the CPU | |
922 | * perspective, requiring manual detiling by the client. | |
923 | */ | |
5c0480f2 | 924 | if (obj->phys_obj) { |
fbd5a26d | 925 | ret = i915_gem_phys_pwrite(dev, obj, args, file); |
5c0480f2 DV |
926 | goto out; |
927 | } | |
928 | ||
86a1ee26 | 929 | if (obj->cache_level == I915_CACHE_NONE && |
c07496fa | 930 | obj->tiling_mode == I915_TILING_NONE && |
5c0480f2 | 931 | obj->base.write_domain != I915_GEM_DOMAIN_CPU) { |
fbd5a26d | 932 | ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file); |
935aaa69 DV |
933 | /* Note that the gtt paths might fail with non-page-backed user |
934 | * pointers (e.g. gtt mappings when moving data between | |
935 | * textures). Fallback to the shmem path in that case. */ | |
fbd5a26d | 936 | } |
673a394b | 937 | |
86a1ee26 | 938 | if (ret == -EFAULT || ret == -ENOSPC) |
935aaa69 | 939 | ret = i915_gem_shmem_pwrite(dev, obj, args, file); |
5c0480f2 | 940 | |
35b62a89 | 941 | out: |
05394f39 | 942 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 943 | unlock: |
fbd5a26d | 944 | mutex_unlock(&dev->struct_mutex); |
673a394b EA |
945 | return ret; |
946 | } | |
947 | ||
948 | /** | |
2ef7eeaa EA |
949 | * Called when user space prepares to use an object with the CPU, either |
950 | * through the mmap ioctl's mapping or a GTT mapping. | |
673a394b EA |
951 | */ |
952 | int | |
953 | i915_gem_set_domain_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 954 | struct drm_file *file) |
673a394b EA |
955 | { |
956 | struct drm_i915_gem_set_domain *args = data; | |
05394f39 | 957 | struct drm_i915_gem_object *obj; |
2ef7eeaa EA |
958 | uint32_t read_domains = args->read_domains; |
959 | uint32_t write_domain = args->write_domain; | |
673a394b EA |
960 | int ret; |
961 | ||
2ef7eeaa | 962 | /* Only handle setting domains to types used by the CPU. */ |
21d509e3 | 963 | if (write_domain & I915_GEM_GPU_DOMAINS) |
2ef7eeaa EA |
964 | return -EINVAL; |
965 | ||
21d509e3 | 966 | if (read_domains & I915_GEM_GPU_DOMAINS) |
2ef7eeaa EA |
967 | return -EINVAL; |
968 | ||
969 | /* Having something in the write domain implies it's in the read | |
970 | * domain, and only that read domain. Enforce that in the request. | |
971 | */ | |
972 | if (write_domain != 0 && read_domains != write_domain) | |
973 | return -EINVAL; | |
974 | ||
76c1dec1 | 975 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 976 | if (ret) |
76c1dec1 | 977 | return ret; |
1d7cfea1 | 978 | |
05394f39 | 979 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 980 | if (&obj->base == NULL) { |
1d7cfea1 CW |
981 | ret = -ENOENT; |
982 | goto unlock; | |
76c1dec1 | 983 | } |
673a394b | 984 | |
2ef7eeaa EA |
985 | if (read_domains & I915_GEM_DOMAIN_GTT) { |
986 | ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0); | |
02354392 EA |
987 | |
988 | /* Silently promote "you're not bound, there was nothing to do" | |
989 | * to success, since the client was just asking us to | |
990 | * make sure everything was done. | |
991 | */ | |
992 | if (ret == -EINVAL) | |
993 | ret = 0; | |
2ef7eeaa | 994 | } else { |
e47c68e9 | 995 | ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0); |
2ef7eeaa EA |
996 | } |
997 | ||
05394f39 | 998 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 999 | unlock: |
673a394b EA |
1000 | mutex_unlock(&dev->struct_mutex); |
1001 | return ret; | |
1002 | } | |
1003 | ||
1004 | /** | |
1005 | * Called when user space has done writes to this buffer | |
1006 | */ | |
1007 | int | |
1008 | i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 1009 | struct drm_file *file) |
673a394b EA |
1010 | { |
1011 | struct drm_i915_gem_sw_finish *args = data; | |
05394f39 | 1012 | struct drm_i915_gem_object *obj; |
673a394b EA |
1013 | int ret = 0; |
1014 | ||
76c1dec1 | 1015 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 1016 | if (ret) |
76c1dec1 | 1017 | return ret; |
1d7cfea1 | 1018 | |
05394f39 | 1019 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 1020 | if (&obj->base == NULL) { |
1d7cfea1 CW |
1021 | ret = -ENOENT; |
1022 | goto unlock; | |
673a394b EA |
1023 | } |
1024 | ||
673a394b | 1025 | /* Pinned buffers may be scanout, so flush the cache */ |
05394f39 | 1026 | if (obj->pin_count) |
e47c68e9 EA |
1027 | i915_gem_object_flush_cpu_write_domain(obj); |
1028 | ||
05394f39 | 1029 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 1030 | unlock: |
673a394b EA |
1031 | mutex_unlock(&dev->struct_mutex); |
1032 | return ret; | |
1033 | } | |
1034 | ||
1035 | /** | |
1036 | * Maps the contents of an object, returning the address it is mapped | |
1037 | * into. | |
1038 | * | |
1039 | * While the mapping holds a reference on the contents of the object, it doesn't | |
1040 | * imply a ref on the object itself. | |
1041 | */ | |
1042 | int | |
1043 | i915_gem_mmap_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 1044 | struct drm_file *file) |
673a394b EA |
1045 | { |
1046 | struct drm_i915_gem_mmap *args = data; | |
1047 | struct drm_gem_object *obj; | |
673a394b EA |
1048 | unsigned long addr; |
1049 | ||
05394f39 | 1050 | obj = drm_gem_object_lookup(dev, file, args->handle); |
673a394b | 1051 | if (obj == NULL) |
bf79cb91 | 1052 | return -ENOENT; |
673a394b | 1053 | |
1286ff73 DV |
1054 | /* prime objects have no backing filp to GEM mmap |
1055 | * pages from. | |
1056 | */ | |
1057 | if (!obj->filp) { | |
1058 | drm_gem_object_unreference_unlocked(obj); | |
1059 | return -EINVAL; | |
1060 | } | |
1061 | ||
6be5ceb0 | 1062 | addr = vm_mmap(obj->filp, 0, args->size, |
673a394b EA |
1063 | PROT_READ | PROT_WRITE, MAP_SHARED, |
1064 | args->offset); | |
bc9025bd | 1065 | drm_gem_object_unreference_unlocked(obj); |
673a394b EA |
1066 | if (IS_ERR((void *)addr)) |
1067 | return addr; | |
1068 | ||
1069 | args->addr_ptr = (uint64_t) addr; | |
1070 | ||
1071 | return 0; | |
1072 | } | |
1073 | ||
de151cf6 JB |
1074 | /** |
1075 | * i915_gem_fault - fault a page into the GTT | |
1076 | * vma: VMA in question | |
1077 | * vmf: fault info | |
1078 | * | |
1079 | * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped | |
1080 | * from userspace. The fault handler takes care of binding the object to | |
1081 | * the GTT (if needed), allocating and programming a fence register (again, | |
1082 | * only if needed based on whether the old reg is still valid or the object | |
1083 | * is tiled) and inserting a new PTE into the faulting process. | |
1084 | * | |
1085 | * Note that the faulting process may involve evicting existing objects | |
1086 | * from the GTT and/or fence registers to make room. So performance may | |
1087 | * suffer if the GTT working set is large or there are few fence registers | |
1088 | * left. | |
1089 | */ | |
1090 | int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf) | |
1091 | { | |
05394f39 CW |
1092 | struct drm_i915_gem_object *obj = to_intel_bo(vma->vm_private_data); |
1093 | struct drm_device *dev = obj->base.dev; | |
7d1c4804 | 1094 | drm_i915_private_t *dev_priv = dev->dev_private; |
de151cf6 JB |
1095 | pgoff_t page_offset; |
1096 | unsigned long pfn; | |
1097 | int ret = 0; | |
0f973f27 | 1098 | bool write = !!(vmf->flags & FAULT_FLAG_WRITE); |
de151cf6 JB |
1099 | |
1100 | /* We don't use vmf->pgoff since that has the fake offset */ | |
1101 | page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >> | |
1102 | PAGE_SHIFT; | |
1103 | ||
d9bc7e9f CW |
1104 | ret = i915_mutex_lock_interruptible(dev); |
1105 | if (ret) | |
1106 | goto out; | |
a00b10c3 | 1107 | |
db53a302 CW |
1108 | trace_i915_gem_object_fault(obj, page_offset, true, write); |
1109 | ||
d9bc7e9f | 1110 | /* Now bind it into the GTT if needed */ |
919926ae CW |
1111 | if (!obj->map_and_fenceable) { |
1112 | ret = i915_gem_object_unbind(obj); | |
1113 | if (ret) | |
1114 | goto unlock; | |
a00b10c3 | 1115 | } |
05394f39 | 1116 | if (!obj->gtt_space) { |
86a1ee26 | 1117 | ret = i915_gem_object_bind_to_gtt(obj, 0, true, false); |
c715089f CW |
1118 | if (ret) |
1119 | goto unlock; | |
de151cf6 | 1120 | |
e92d03bf EA |
1121 | ret = i915_gem_object_set_to_gtt_domain(obj, write); |
1122 | if (ret) | |
1123 | goto unlock; | |
1124 | } | |
4a684a41 | 1125 | |
74898d7e DV |
1126 | if (!obj->has_global_gtt_mapping) |
1127 | i915_gem_gtt_bind_object(obj, obj->cache_level); | |
1128 | ||
06d98131 | 1129 | ret = i915_gem_object_get_fence(obj); |
d9e86c0e CW |
1130 | if (ret) |
1131 | goto unlock; | |
de151cf6 | 1132 | |
05394f39 CW |
1133 | if (i915_gem_object_is_inactive(obj)) |
1134 | list_move_tail(&obj->mm_list, &dev_priv->mm.inactive_list); | |
7d1c4804 | 1135 | |
6299f992 CW |
1136 | obj->fault_mappable = true; |
1137 | ||
dd2757f8 | 1138 | pfn = ((dev_priv->mm.gtt_base_addr + obj->gtt_offset) >> PAGE_SHIFT) + |
de151cf6 JB |
1139 | page_offset; |
1140 | ||
1141 | /* Finally, remap it using the new GTT offset */ | |
1142 | ret = vm_insert_pfn(vma, (unsigned long)vmf->virtual_address, pfn); | |
c715089f | 1143 | unlock: |
de151cf6 | 1144 | mutex_unlock(&dev->struct_mutex); |
d9bc7e9f | 1145 | out: |
de151cf6 | 1146 | switch (ret) { |
d9bc7e9f | 1147 | case -EIO: |
a9340cca DV |
1148 | /* If this -EIO is due to a gpu hang, give the reset code a |
1149 | * chance to clean up the mess. Otherwise return the proper | |
1150 | * SIGBUS. */ | |
1151 | if (!atomic_read(&dev_priv->mm.wedged)) | |
1152 | return VM_FAULT_SIGBUS; | |
045e769a | 1153 | case -EAGAIN: |
d9bc7e9f CW |
1154 | /* Give the error handler a chance to run and move the |
1155 | * objects off the GPU active list. Next time we service the | |
1156 | * fault, we should be able to transition the page into the | |
1157 | * GTT without touching the GPU (and so avoid further | |
1158 | * EIO/EGAIN). If the GPU is wedged, then there is no issue | |
1159 | * with coherency, just lost writes. | |
1160 | */ | |
045e769a | 1161 | set_need_resched(); |
c715089f CW |
1162 | case 0: |
1163 | case -ERESTARTSYS: | |
bed636ab | 1164 | case -EINTR: |
c715089f | 1165 | return VM_FAULT_NOPAGE; |
de151cf6 | 1166 | case -ENOMEM: |
de151cf6 | 1167 | return VM_FAULT_OOM; |
de151cf6 | 1168 | default: |
c715089f | 1169 | return VM_FAULT_SIGBUS; |
de151cf6 JB |
1170 | } |
1171 | } | |
1172 | ||
901782b2 CW |
1173 | /** |
1174 | * i915_gem_release_mmap - remove physical page mappings | |
1175 | * @obj: obj in question | |
1176 | * | |
af901ca1 | 1177 | * Preserve the reservation of the mmapping with the DRM core code, but |
901782b2 CW |
1178 | * relinquish ownership of the pages back to the system. |
1179 | * | |
1180 | * It is vital that we remove the page mapping if we have mapped a tiled | |
1181 | * object through the GTT and then lose the fence register due to | |
1182 | * resource pressure. Similarly if the object has been moved out of the | |
1183 | * aperture, than pages mapped into userspace must be revoked. Removing the | |
1184 | * mapping will then trigger a page fault on the next user access, allowing | |
1185 | * fixup by i915_gem_fault(). | |
1186 | */ | |
d05ca301 | 1187 | void |
05394f39 | 1188 | i915_gem_release_mmap(struct drm_i915_gem_object *obj) |
901782b2 | 1189 | { |
6299f992 CW |
1190 | if (!obj->fault_mappable) |
1191 | return; | |
901782b2 | 1192 | |
f6e47884 CW |
1193 | if (obj->base.dev->dev_mapping) |
1194 | unmap_mapping_range(obj->base.dev->dev_mapping, | |
1195 | (loff_t)obj->base.map_list.hash.key<<PAGE_SHIFT, | |
1196 | obj->base.size, 1); | |
fb7d516a | 1197 | |
6299f992 | 1198 | obj->fault_mappable = false; |
901782b2 CW |
1199 | } |
1200 | ||
92b88aeb | 1201 | static uint32_t |
e28f8711 | 1202 | i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode) |
92b88aeb | 1203 | { |
e28f8711 | 1204 | uint32_t gtt_size; |
92b88aeb CW |
1205 | |
1206 | if (INTEL_INFO(dev)->gen >= 4 || | |
e28f8711 CW |
1207 | tiling_mode == I915_TILING_NONE) |
1208 | return size; | |
92b88aeb CW |
1209 | |
1210 | /* Previous chips need a power-of-two fence region when tiling */ | |
1211 | if (INTEL_INFO(dev)->gen == 3) | |
e28f8711 | 1212 | gtt_size = 1024*1024; |
92b88aeb | 1213 | else |
e28f8711 | 1214 | gtt_size = 512*1024; |
92b88aeb | 1215 | |
e28f8711 CW |
1216 | while (gtt_size < size) |
1217 | gtt_size <<= 1; | |
92b88aeb | 1218 | |
e28f8711 | 1219 | return gtt_size; |
92b88aeb CW |
1220 | } |
1221 | ||
de151cf6 JB |
1222 | /** |
1223 | * i915_gem_get_gtt_alignment - return required GTT alignment for an object | |
1224 | * @obj: object to check | |
1225 | * | |
1226 | * Return the required GTT alignment for an object, taking into account | |
5e783301 | 1227 | * potential fence register mapping. |
de151cf6 JB |
1228 | */ |
1229 | static uint32_t | |
e28f8711 CW |
1230 | i915_gem_get_gtt_alignment(struct drm_device *dev, |
1231 | uint32_t size, | |
1232 | int tiling_mode) | |
de151cf6 | 1233 | { |
de151cf6 JB |
1234 | /* |
1235 | * Minimum alignment is 4k (GTT page size), but might be greater | |
1236 | * if a fence register is needed for the object. | |
1237 | */ | |
a00b10c3 | 1238 | if (INTEL_INFO(dev)->gen >= 4 || |
e28f8711 | 1239 | tiling_mode == I915_TILING_NONE) |
de151cf6 JB |
1240 | return 4096; |
1241 | ||
a00b10c3 CW |
1242 | /* |
1243 | * Previous chips need to be aligned to the size of the smallest | |
1244 | * fence register that can contain the object. | |
1245 | */ | |
e28f8711 | 1246 | return i915_gem_get_gtt_size(dev, size, tiling_mode); |
a00b10c3 CW |
1247 | } |
1248 | ||
5e783301 DV |
1249 | /** |
1250 | * i915_gem_get_unfenced_gtt_alignment - return required GTT alignment for an | |
1251 | * unfenced object | |
e28f8711 CW |
1252 | * @dev: the device |
1253 | * @size: size of the object | |
1254 | * @tiling_mode: tiling mode of the object | |
5e783301 DV |
1255 | * |
1256 | * Return the required GTT alignment for an object, only taking into account | |
1257 | * unfenced tiled surface requirements. | |
1258 | */ | |
467cffba | 1259 | uint32_t |
e28f8711 CW |
1260 | i915_gem_get_unfenced_gtt_alignment(struct drm_device *dev, |
1261 | uint32_t size, | |
1262 | int tiling_mode) | |
5e783301 | 1263 | { |
5e783301 DV |
1264 | /* |
1265 | * Minimum alignment is 4k (GTT page size) for sane hw. | |
1266 | */ | |
1267 | if (INTEL_INFO(dev)->gen >= 4 || IS_G33(dev) || | |
e28f8711 | 1268 | tiling_mode == I915_TILING_NONE) |
5e783301 DV |
1269 | return 4096; |
1270 | ||
e28f8711 CW |
1271 | /* Previous hardware however needs to be aligned to a power-of-two |
1272 | * tile height. The simplest method for determining this is to reuse | |
1273 | * the power-of-tile object size. | |
5e783301 | 1274 | */ |
e28f8711 | 1275 | return i915_gem_get_gtt_size(dev, size, tiling_mode); |
5e783301 DV |
1276 | } |
1277 | ||
d8cb5086 CW |
1278 | static int i915_gem_object_create_mmap_offset(struct drm_i915_gem_object *obj) |
1279 | { | |
1280 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; | |
1281 | int ret; | |
1282 | ||
1283 | if (obj->base.map_list.map) | |
1284 | return 0; | |
1285 | ||
1286 | ret = drm_gem_create_mmap_offset(&obj->base); | |
1287 | if (ret != -ENOSPC) | |
1288 | return ret; | |
1289 | ||
1290 | /* Badly fragmented mmap space? The only way we can recover | |
1291 | * space is by destroying unwanted objects. We can't randomly release | |
1292 | * mmap_offsets as userspace expects them to be persistent for the | |
1293 | * lifetime of the objects. The closest we can is to release the | |
1294 | * offsets on purgeable objects by truncating it and marking it purged, | |
1295 | * which prevents userspace from ever using that object again. | |
1296 | */ | |
1297 | i915_gem_purge(dev_priv, obj->base.size >> PAGE_SHIFT); | |
1298 | ret = drm_gem_create_mmap_offset(&obj->base); | |
1299 | if (ret != -ENOSPC) | |
1300 | return ret; | |
1301 | ||
1302 | i915_gem_shrink_all(dev_priv); | |
1303 | return drm_gem_create_mmap_offset(&obj->base); | |
1304 | } | |
1305 | ||
1306 | static void i915_gem_object_free_mmap_offset(struct drm_i915_gem_object *obj) | |
1307 | { | |
1308 | if (!obj->base.map_list.map) | |
1309 | return; | |
1310 | ||
1311 | drm_gem_free_mmap_offset(&obj->base); | |
1312 | } | |
1313 | ||
de151cf6 | 1314 | int |
ff72145b DA |
1315 | i915_gem_mmap_gtt(struct drm_file *file, |
1316 | struct drm_device *dev, | |
1317 | uint32_t handle, | |
1318 | uint64_t *offset) | |
de151cf6 | 1319 | { |
da761a6e | 1320 | struct drm_i915_private *dev_priv = dev->dev_private; |
05394f39 | 1321 | struct drm_i915_gem_object *obj; |
de151cf6 JB |
1322 | int ret; |
1323 | ||
76c1dec1 | 1324 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 1325 | if (ret) |
76c1dec1 | 1326 | return ret; |
de151cf6 | 1327 | |
ff72145b | 1328 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle)); |
c8725226 | 1329 | if (&obj->base == NULL) { |
1d7cfea1 CW |
1330 | ret = -ENOENT; |
1331 | goto unlock; | |
1332 | } | |
de151cf6 | 1333 | |
05394f39 | 1334 | if (obj->base.size > dev_priv->mm.gtt_mappable_end) { |
da761a6e | 1335 | ret = -E2BIG; |
ff56b0bc | 1336 | goto out; |
da761a6e CW |
1337 | } |
1338 | ||
05394f39 | 1339 | if (obj->madv != I915_MADV_WILLNEED) { |
ab18282d | 1340 | DRM_ERROR("Attempting to mmap a purgeable buffer\n"); |
1d7cfea1 CW |
1341 | ret = -EINVAL; |
1342 | goto out; | |
ab18282d CW |
1343 | } |
1344 | ||
d8cb5086 CW |
1345 | ret = i915_gem_object_create_mmap_offset(obj); |
1346 | if (ret) | |
1347 | goto out; | |
de151cf6 | 1348 | |
ff72145b | 1349 | *offset = (u64)obj->base.map_list.hash.key << PAGE_SHIFT; |
de151cf6 | 1350 | |
1d7cfea1 | 1351 | out: |
05394f39 | 1352 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 1353 | unlock: |
de151cf6 | 1354 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 1355 | return ret; |
de151cf6 JB |
1356 | } |
1357 | ||
ff72145b DA |
1358 | /** |
1359 | * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing | |
1360 | * @dev: DRM device | |
1361 | * @data: GTT mapping ioctl data | |
1362 | * @file: GEM object info | |
1363 | * | |
1364 | * Simply returns the fake offset to userspace so it can mmap it. | |
1365 | * The mmap call will end up in drm_gem_mmap(), which will set things | |
1366 | * up so we can get faults in the handler above. | |
1367 | * | |
1368 | * The fault handler will take care of binding the object into the GTT | |
1369 | * (since it may have been evicted to make room for something), allocating | |
1370 | * a fence register, and mapping the appropriate aperture address into | |
1371 | * userspace. | |
1372 | */ | |
1373 | int | |
1374 | i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data, | |
1375 | struct drm_file *file) | |
1376 | { | |
1377 | struct drm_i915_gem_mmap_gtt *args = data; | |
1378 | ||
ff72145b DA |
1379 | return i915_gem_mmap_gtt(file, dev, args->handle, &args->offset); |
1380 | } | |
1381 | ||
225067ee DV |
1382 | /* Immediately discard the backing storage */ |
1383 | static void | |
1384 | i915_gem_object_truncate(struct drm_i915_gem_object *obj) | |
1385 | { | |
1386 | struct inode *inode; | |
1387 | ||
4d6294bf CW |
1388 | i915_gem_object_free_mmap_offset(obj); |
1389 | ||
1390 | if (obj->base.filp == NULL) | |
1391 | return; | |
1392 | ||
225067ee DV |
1393 | /* Our goal here is to return as much of the memory as |
1394 | * is possible back to the system as we are called from OOM. | |
1395 | * To do this we must instruct the shmfs to drop all of its | |
1396 | * backing pages, *now*. | |
1397 | */ | |
1398 | inode = obj->base.filp->f_path.dentry->d_inode; | |
1399 | shmem_truncate_range(inode, 0, (loff_t)-1); | |
1400 | ||
225067ee DV |
1401 | obj->madv = __I915_MADV_PURGED; |
1402 | } | |
1403 | ||
1404 | static inline int | |
1405 | i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj) | |
1406 | { | |
1407 | return obj->madv == I915_MADV_DONTNEED; | |
1408 | } | |
1409 | ||
6c085a72 | 1410 | static int |
225067ee DV |
1411 | i915_gem_object_put_pages_gtt(struct drm_i915_gem_object *obj) |
1412 | { | |
1413 | int page_count = obj->base.size / PAGE_SIZE; | |
6c085a72 | 1414 | int ret, i; |
225067ee | 1415 | |
c4670ad0 CW |
1416 | BUG_ON(obj->gtt_space); |
1417 | ||
6c085a72 CW |
1418 | if (obj->pages == NULL) |
1419 | return 0; | |
225067ee | 1420 | |
6c085a72 | 1421 | BUG_ON(obj->gtt_space); |
225067ee DV |
1422 | BUG_ON(obj->madv == __I915_MADV_PURGED); |
1423 | ||
6c085a72 CW |
1424 | ret = i915_gem_object_set_to_cpu_domain(obj, true); |
1425 | if (ret) { | |
1426 | /* In the event of a disaster, abandon all caches and | |
1427 | * hope for the best. | |
1428 | */ | |
1429 | WARN_ON(ret != -EIO); | |
1430 | i915_gem_clflush_object(obj); | |
1431 | obj->base.read_domains = obj->base.write_domain = I915_GEM_DOMAIN_CPU; | |
1432 | } | |
1433 | ||
225067ee DV |
1434 | if (i915_gem_object_needs_bit17_swizzle(obj)) |
1435 | i915_gem_object_save_bit_17_swizzle(obj); | |
1436 | ||
1437 | if (obj->madv == I915_MADV_DONTNEED) | |
1438 | obj->dirty = 0; | |
1439 | ||
1440 | for (i = 0; i < page_count; i++) { | |
1441 | if (obj->dirty) | |
1442 | set_page_dirty(obj->pages[i]); | |
1443 | ||
1444 | if (obj->madv == I915_MADV_WILLNEED) | |
1445 | mark_page_accessed(obj->pages[i]); | |
1446 | ||
1447 | page_cache_release(obj->pages[i]); | |
1448 | } | |
1449 | obj->dirty = 0; | |
1450 | ||
1451 | drm_free_large(obj->pages); | |
1452 | obj->pages = NULL; | |
6c085a72 CW |
1453 | |
1454 | list_del(&obj->gtt_list); | |
1455 | ||
1456 | if (i915_gem_object_is_purgeable(obj)) | |
1457 | i915_gem_object_truncate(obj); | |
1458 | ||
1459 | return 0; | |
1460 | } | |
1461 | ||
1462 | static long | |
1463 | i915_gem_purge(struct drm_i915_private *dev_priv, long target) | |
1464 | { | |
1465 | struct drm_i915_gem_object *obj, *next; | |
1466 | long count = 0; | |
1467 | ||
1468 | list_for_each_entry_safe(obj, next, | |
1469 | &dev_priv->mm.unbound_list, | |
1470 | gtt_list) { | |
1471 | if (i915_gem_object_is_purgeable(obj) && | |
1472 | i915_gem_object_put_pages_gtt(obj) == 0) { | |
1473 | count += obj->base.size >> PAGE_SHIFT; | |
1474 | if (count >= target) | |
1475 | return count; | |
1476 | } | |
1477 | } | |
1478 | ||
1479 | list_for_each_entry_safe(obj, next, | |
1480 | &dev_priv->mm.inactive_list, | |
1481 | mm_list) { | |
1482 | if (i915_gem_object_is_purgeable(obj) && | |
1483 | i915_gem_object_unbind(obj) == 0 && | |
1484 | i915_gem_object_put_pages_gtt(obj) == 0) { | |
1485 | count += obj->base.size >> PAGE_SHIFT; | |
1486 | if (count >= target) | |
1487 | return count; | |
1488 | } | |
1489 | } | |
1490 | ||
1491 | return count; | |
1492 | } | |
1493 | ||
1494 | static void | |
1495 | i915_gem_shrink_all(struct drm_i915_private *dev_priv) | |
1496 | { | |
1497 | struct drm_i915_gem_object *obj, *next; | |
1498 | ||
1499 | i915_gem_evict_everything(dev_priv->dev); | |
1500 | ||
1501 | list_for_each_entry_safe(obj, next, &dev_priv->mm.unbound_list, gtt_list) | |
1502 | i915_gem_object_put_pages_gtt(obj); | |
225067ee DV |
1503 | } |
1504 | ||
1286ff73 | 1505 | int |
6c085a72 | 1506 | i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj) |
e5281ccd | 1507 | { |
6c085a72 | 1508 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
e5281ccd CW |
1509 | int page_count, i; |
1510 | struct address_space *mapping; | |
e5281ccd | 1511 | struct page *page; |
6c085a72 | 1512 | gfp_t gfp; |
e5281ccd | 1513 | |
1286ff73 DV |
1514 | if (obj->pages || obj->sg_table) |
1515 | return 0; | |
1516 | ||
6c085a72 CW |
1517 | /* Assert that the object is not currently in any GPU domain. As it |
1518 | * wasn't in the GTT, there shouldn't be any way it could have been in | |
1519 | * a GPU cache | |
1520 | */ | |
1521 | BUG_ON(obj->base.read_domains & I915_GEM_GPU_DOMAINS); | |
1522 | BUG_ON(obj->base.write_domain & I915_GEM_GPU_DOMAINS); | |
1523 | ||
e5281ccd CW |
1524 | /* Get the list of pages out of our struct file. They'll be pinned |
1525 | * at this point until we release them. | |
1526 | */ | |
05394f39 | 1527 | page_count = obj->base.size / PAGE_SIZE; |
05394f39 CW |
1528 | obj->pages = drm_malloc_ab(page_count, sizeof(struct page *)); |
1529 | if (obj->pages == NULL) | |
e5281ccd CW |
1530 | return -ENOMEM; |
1531 | ||
6c085a72 CW |
1532 | /* Fail silently without starting the shrinker */ |
1533 | mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping; | |
1534 | gfp = mapping_gfp_mask(mapping); | |
1535 | gfp |= __GFP_NORETRY | __GFP_NOWARN | __GFP_NO_KSWAPD; | |
1536 | gfp &= ~(__GFP_IO | __GFP_WAIT); | |
e5281ccd | 1537 | for (i = 0; i < page_count; i++) { |
6c085a72 CW |
1538 | page = shmem_read_mapping_page_gfp(mapping, i, gfp); |
1539 | if (IS_ERR(page)) { | |
1540 | i915_gem_purge(dev_priv, page_count); | |
1541 | page = shmem_read_mapping_page_gfp(mapping, i, gfp); | |
1542 | } | |
1543 | if (IS_ERR(page)) { | |
1544 | /* We've tried hard to allocate the memory by reaping | |
1545 | * our own buffer, now let the real VM do its job and | |
1546 | * go down in flames if truly OOM. | |
1547 | */ | |
1548 | gfp &= ~(__GFP_NORETRY | __GFP_NOWARN | __GFP_NO_KSWAPD); | |
1549 | gfp |= __GFP_IO | __GFP_WAIT; | |
1550 | ||
1551 | i915_gem_shrink_all(dev_priv); | |
1552 | page = shmem_read_mapping_page_gfp(mapping, i, gfp); | |
1553 | if (IS_ERR(page)) | |
1554 | goto err_pages; | |
1555 | ||
1556 | gfp |= __GFP_NORETRY | __GFP_NOWARN | __GFP_NO_KSWAPD; | |
1557 | gfp &= ~(__GFP_IO | __GFP_WAIT); | |
1558 | } | |
e5281ccd | 1559 | |
05394f39 | 1560 | obj->pages[i] = page; |
e5281ccd CW |
1561 | } |
1562 | ||
6dacfd2f | 1563 | if (i915_gem_object_needs_bit17_swizzle(obj)) |
e5281ccd CW |
1564 | i915_gem_object_do_bit_17_swizzle(obj); |
1565 | ||
6c085a72 | 1566 | list_add_tail(&obj->gtt_list, &dev_priv->mm.unbound_list); |
e5281ccd CW |
1567 | return 0; |
1568 | ||
1569 | err_pages: | |
1570 | while (i--) | |
05394f39 | 1571 | page_cache_release(obj->pages[i]); |
e5281ccd | 1572 | |
05394f39 CW |
1573 | drm_free_large(obj->pages); |
1574 | obj->pages = NULL; | |
e5281ccd CW |
1575 | return PTR_ERR(page); |
1576 | } | |
1577 | ||
54cf91dc | 1578 | void |
05394f39 | 1579 | i915_gem_object_move_to_active(struct drm_i915_gem_object *obj, |
1ec14ad3 CW |
1580 | struct intel_ring_buffer *ring, |
1581 | u32 seqno) | |
673a394b | 1582 | { |
05394f39 | 1583 | struct drm_device *dev = obj->base.dev; |
69dc4987 | 1584 | struct drm_i915_private *dev_priv = dev->dev_private; |
617dbe27 | 1585 | |
852835f3 | 1586 | BUG_ON(ring == NULL); |
05394f39 | 1587 | obj->ring = ring; |
673a394b EA |
1588 | |
1589 | /* Add a reference if we're newly entering the active list. */ | |
05394f39 CW |
1590 | if (!obj->active) { |
1591 | drm_gem_object_reference(&obj->base); | |
1592 | obj->active = 1; | |
673a394b | 1593 | } |
e35a41de | 1594 | |
673a394b | 1595 | /* Move from whatever list we were on to the tail of execution. */ |
05394f39 CW |
1596 | list_move_tail(&obj->mm_list, &dev_priv->mm.active_list); |
1597 | list_move_tail(&obj->ring_list, &ring->active_list); | |
caea7476 | 1598 | |
0201f1ec | 1599 | obj->last_read_seqno = seqno; |
caea7476 | 1600 | |
7dd49065 | 1601 | if (obj->fenced_gpu_access) { |
caea7476 | 1602 | obj->last_fenced_seqno = seqno; |
caea7476 | 1603 | |
7dd49065 CW |
1604 | /* Bump MRU to take account of the delayed flush */ |
1605 | if (obj->fence_reg != I915_FENCE_REG_NONE) { | |
1606 | struct drm_i915_fence_reg *reg; | |
1607 | ||
1608 | reg = &dev_priv->fence_regs[obj->fence_reg]; | |
1609 | list_move_tail(®->lru_list, | |
1610 | &dev_priv->mm.fence_list); | |
1611 | } | |
caea7476 CW |
1612 | } |
1613 | } | |
1614 | ||
caea7476 CW |
1615 | static void |
1616 | i915_gem_object_move_to_inactive(struct drm_i915_gem_object *obj) | |
1617 | { | |
1618 | struct drm_device *dev = obj->base.dev; | |
1619 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1620 | ||
65ce3027 | 1621 | BUG_ON(obj->base.write_domain & ~I915_GEM_GPU_DOMAINS); |
caea7476 | 1622 | BUG_ON(!obj->active); |
65ce3027 | 1623 | |
f047e395 CW |
1624 | if (obj->pin_count) /* are we a framebuffer? */ |
1625 | intel_mark_fb_idle(obj); | |
1626 | ||
1627 | list_move_tail(&obj->mm_list, &dev_priv->mm.inactive_list); | |
1628 | ||
65ce3027 | 1629 | list_del_init(&obj->ring_list); |
caea7476 CW |
1630 | obj->ring = NULL; |
1631 | ||
65ce3027 CW |
1632 | obj->last_read_seqno = 0; |
1633 | obj->last_write_seqno = 0; | |
1634 | obj->base.write_domain = 0; | |
1635 | ||
1636 | obj->last_fenced_seqno = 0; | |
caea7476 | 1637 | obj->fenced_gpu_access = false; |
caea7476 CW |
1638 | |
1639 | obj->active = 0; | |
1640 | drm_gem_object_unreference(&obj->base); | |
1641 | ||
1642 | WARN_ON(i915_verify_lists(dev)); | |
ce44b0ea | 1643 | } |
673a394b | 1644 | |
53d227f2 DV |
1645 | static u32 |
1646 | i915_gem_get_seqno(struct drm_device *dev) | |
1647 | { | |
1648 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1649 | u32 seqno = dev_priv->next_seqno; | |
1650 | ||
1651 | /* reserve 0 for non-seqno */ | |
1652 | if (++dev_priv->next_seqno == 0) | |
1653 | dev_priv->next_seqno = 1; | |
1654 | ||
1655 | return seqno; | |
1656 | } | |
1657 | ||
1658 | u32 | |
1659 | i915_gem_next_request_seqno(struct intel_ring_buffer *ring) | |
1660 | { | |
1661 | if (ring->outstanding_lazy_request == 0) | |
1662 | ring->outstanding_lazy_request = i915_gem_get_seqno(ring->dev); | |
1663 | ||
1664 | return ring->outstanding_lazy_request; | |
1665 | } | |
1666 | ||
3cce469c | 1667 | int |
db53a302 | 1668 | i915_add_request(struct intel_ring_buffer *ring, |
f787a5f5 | 1669 | struct drm_file *file, |
db53a302 | 1670 | struct drm_i915_gem_request *request) |
673a394b | 1671 | { |
db53a302 | 1672 | drm_i915_private_t *dev_priv = ring->dev->dev_private; |
673a394b | 1673 | uint32_t seqno; |
a71d8d94 | 1674 | u32 request_ring_position; |
673a394b | 1675 | int was_empty; |
3cce469c CW |
1676 | int ret; |
1677 | ||
cc889e0f DV |
1678 | /* |
1679 | * Emit any outstanding flushes - execbuf can fail to emit the flush | |
1680 | * after having emitted the batchbuffer command. Hence we need to fix | |
1681 | * things up similar to emitting the lazy request. The difference here | |
1682 | * is that the flush _must_ happen before the next request, no matter | |
1683 | * what. | |
1684 | */ | |
a7b9761d CW |
1685 | ret = intel_ring_flush_all_caches(ring); |
1686 | if (ret) | |
1687 | return ret; | |
cc889e0f | 1688 | |
3bb73aba CW |
1689 | if (request == NULL) { |
1690 | request = kmalloc(sizeof(*request), GFP_KERNEL); | |
1691 | if (request == NULL) | |
1692 | return -ENOMEM; | |
1693 | } | |
1694 | ||
53d227f2 | 1695 | seqno = i915_gem_next_request_seqno(ring); |
673a394b | 1696 | |
a71d8d94 CW |
1697 | /* Record the position of the start of the request so that |
1698 | * should we detect the updated seqno part-way through the | |
1699 | * GPU processing the request, we never over-estimate the | |
1700 | * position of the head. | |
1701 | */ | |
1702 | request_ring_position = intel_ring_get_tail(ring); | |
1703 | ||
3cce469c | 1704 | ret = ring->add_request(ring, &seqno); |
3bb73aba CW |
1705 | if (ret) { |
1706 | kfree(request); | |
1707 | return ret; | |
1708 | } | |
673a394b | 1709 | |
db53a302 | 1710 | trace_i915_gem_request_add(ring, seqno); |
673a394b EA |
1711 | |
1712 | request->seqno = seqno; | |
852835f3 | 1713 | request->ring = ring; |
a71d8d94 | 1714 | request->tail = request_ring_position; |
673a394b | 1715 | request->emitted_jiffies = jiffies; |
852835f3 ZN |
1716 | was_empty = list_empty(&ring->request_list); |
1717 | list_add_tail(&request->list, &ring->request_list); | |
3bb73aba | 1718 | request->file_priv = NULL; |
852835f3 | 1719 | |
db53a302 CW |
1720 | if (file) { |
1721 | struct drm_i915_file_private *file_priv = file->driver_priv; | |
1722 | ||
1c25595f | 1723 | spin_lock(&file_priv->mm.lock); |
f787a5f5 | 1724 | request->file_priv = file_priv; |
b962442e | 1725 | list_add_tail(&request->client_list, |
f787a5f5 | 1726 | &file_priv->mm.request_list); |
1c25595f | 1727 | spin_unlock(&file_priv->mm.lock); |
b962442e | 1728 | } |
673a394b | 1729 | |
5391d0cf | 1730 | ring->outstanding_lazy_request = 0; |
db53a302 | 1731 | |
f65d9421 | 1732 | if (!dev_priv->mm.suspended) { |
3e0dc6b0 BW |
1733 | if (i915_enable_hangcheck) { |
1734 | mod_timer(&dev_priv->hangcheck_timer, | |
1735 | jiffies + | |
1736 | msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)); | |
1737 | } | |
f047e395 | 1738 | if (was_empty) { |
b3b079db CW |
1739 | queue_delayed_work(dev_priv->wq, |
1740 | &dev_priv->mm.retire_work, HZ); | |
f047e395 CW |
1741 | intel_mark_busy(dev_priv->dev); |
1742 | } | |
f65d9421 | 1743 | } |
cc889e0f | 1744 | |
3cce469c | 1745 | return 0; |
673a394b EA |
1746 | } |
1747 | ||
f787a5f5 CW |
1748 | static inline void |
1749 | i915_gem_request_remove_from_client(struct drm_i915_gem_request *request) | |
673a394b | 1750 | { |
1c25595f | 1751 | struct drm_i915_file_private *file_priv = request->file_priv; |
673a394b | 1752 | |
1c25595f CW |
1753 | if (!file_priv) |
1754 | return; | |
1c5d22f7 | 1755 | |
1c25595f | 1756 | spin_lock(&file_priv->mm.lock); |
09bfa517 HRK |
1757 | if (request->file_priv) { |
1758 | list_del(&request->client_list); | |
1759 | request->file_priv = NULL; | |
1760 | } | |
1c25595f | 1761 | spin_unlock(&file_priv->mm.lock); |
673a394b | 1762 | } |
673a394b | 1763 | |
dfaae392 CW |
1764 | static void i915_gem_reset_ring_lists(struct drm_i915_private *dev_priv, |
1765 | struct intel_ring_buffer *ring) | |
9375e446 | 1766 | { |
dfaae392 CW |
1767 | while (!list_empty(&ring->request_list)) { |
1768 | struct drm_i915_gem_request *request; | |
673a394b | 1769 | |
dfaae392 CW |
1770 | request = list_first_entry(&ring->request_list, |
1771 | struct drm_i915_gem_request, | |
1772 | list); | |
de151cf6 | 1773 | |
dfaae392 | 1774 | list_del(&request->list); |
f787a5f5 | 1775 | i915_gem_request_remove_from_client(request); |
dfaae392 CW |
1776 | kfree(request); |
1777 | } | |
673a394b | 1778 | |
dfaae392 | 1779 | while (!list_empty(&ring->active_list)) { |
05394f39 | 1780 | struct drm_i915_gem_object *obj; |
9375e446 | 1781 | |
05394f39 CW |
1782 | obj = list_first_entry(&ring->active_list, |
1783 | struct drm_i915_gem_object, | |
1784 | ring_list); | |
9375e446 | 1785 | |
05394f39 | 1786 | i915_gem_object_move_to_inactive(obj); |
673a394b EA |
1787 | } |
1788 | } | |
1789 | ||
312817a3 CW |
1790 | static void i915_gem_reset_fences(struct drm_device *dev) |
1791 | { | |
1792 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1793 | int i; | |
1794 | ||
4b9de737 | 1795 | for (i = 0; i < dev_priv->num_fence_regs; i++) { |
312817a3 | 1796 | struct drm_i915_fence_reg *reg = &dev_priv->fence_regs[i]; |
7d2cb39c | 1797 | |
ada726c7 | 1798 | i915_gem_write_fence(dev, i, NULL); |
7d2cb39c | 1799 | |
ada726c7 CW |
1800 | if (reg->obj) |
1801 | i915_gem_object_fence_lost(reg->obj); | |
7d2cb39c | 1802 | |
ada726c7 CW |
1803 | reg->pin_count = 0; |
1804 | reg->obj = NULL; | |
1805 | INIT_LIST_HEAD(®->lru_list); | |
312817a3 | 1806 | } |
ada726c7 CW |
1807 | |
1808 | INIT_LIST_HEAD(&dev_priv->mm.fence_list); | |
312817a3 CW |
1809 | } |
1810 | ||
069efc1d | 1811 | void i915_gem_reset(struct drm_device *dev) |
673a394b | 1812 | { |
77f01230 | 1813 | struct drm_i915_private *dev_priv = dev->dev_private; |
05394f39 | 1814 | struct drm_i915_gem_object *obj; |
b4519513 | 1815 | struct intel_ring_buffer *ring; |
1ec14ad3 | 1816 | int i; |
673a394b | 1817 | |
b4519513 CW |
1818 | for_each_ring(ring, dev_priv, i) |
1819 | i915_gem_reset_ring_lists(dev_priv, ring); | |
dfaae392 | 1820 | |
dfaae392 CW |
1821 | /* Move everything out of the GPU domains to ensure we do any |
1822 | * necessary invalidation upon reuse. | |
1823 | */ | |
05394f39 | 1824 | list_for_each_entry(obj, |
77f01230 | 1825 | &dev_priv->mm.inactive_list, |
69dc4987 | 1826 | mm_list) |
77f01230 | 1827 | { |
05394f39 | 1828 | obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS; |
77f01230 | 1829 | } |
069efc1d | 1830 | |
6c085a72 | 1831 | |
069efc1d | 1832 | /* The fence registers are invalidated so clear them out */ |
312817a3 | 1833 | i915_gem_reset_fences(dev); |
673a394b EA |
1834 | } |
1835 | ||
1836 | /** | |
1837 | * This function clears the request list as sequence numbers are passed. | |
1838 | */ | |
a71d8d94 | 1839 | void |
db53a302 | 1840 | i915_gem_retire_requests_ring(struct intel_ring_buffer *ring) |
673a394b | 1841 | { |
673a394b | 1842 | uint32_t seqno; |
1ec14ad3 | 1843 | int i; |
673a394b | 1844 | |
db53a302 | 1845 | if (list_empty(&ring->request_list)) |
6c0594a3 KW |
1846 | return; |
1847 | ||
db53a302 | 1848 | WARN_ON(i915_verify_lists(ring->dev)); |
673a394b | 1849 | |
b2eadbc8 | 1850 | seqno = ring->get_seqno(ring, true); |
1ec14ad3 | 1851 | |
076e2c0e | 1852 | for (i = 0; i < ARRAY_SIZE(ring->sync_seqno); i++) |
1ec14ad3 CW |
1853 | if (seqno >= ring->sync_seqno[i]) |
1854 | ring->sync_seqno[i] = 0; | |
1855 | ||
852835f3 | 1856 | while (!list_empty(&ring->request_list)) { |
673a394b | 1857 | struct drm_i915_gem_request *request; |
673a394b | 1858 | |
852835f3 | 1859 | request = list_first_entry(&ring->request_list, |
673a394b EA |
1860 | struct drm_i915_gem_request, |
1861 | list); | |
673a394b | 1862 | |
dfaae392 | 1863 | if (!i915_seqno_passed(seqno, request->seqno)) |
b84d5f0c CW |
1864 | break; |
1865 | ||
db53a302 | 1866 | trace_i915_gem_request_retire(ring, request->seqno); |
a71d8d94 CW |
1867 | /* We know the GPU must have read the request to have |
1868 | * sent us the seqno + interrupt, so use the position | |
1869 | * of tail of the request to update the last known position | |
1870 | * of the GPU head. | |
1871 | */ | |
1872 | ring->last_retired_head = request->tail; | |
b84d5f0c CW |
1873 | |
1874 | list_del(&request->list); | |
f787a5f5 | 1875 | i915_gem_request_remove_from_client(request); |
b84d5f0c CW |
1876 | kfree(request); |
1877 | } | |
673a394b | 1878 | |
b84d5f0c CW |
1879 | /* Move any buffers on the active list that are no longer referenced |
1880 | * by the ringbuffer to the flushing/inactive lists as appropriate. | |
1881 | */ | |
1882 | while (!list_empty(&ring->active_list)) { | |
05394f39 | 1883 | struct drm_i915_gem_object *obj; |
b84d5f0c | 1884 | |
0206e353 | 1885 | obj = list_first_entry(&ring->active_list, |
05394f39 CW |
1886 | struct drm_i915_gem_object, |
1887 | ring_list); | |
673a394b | 1888 | |
0201f1ec | 1889 | if (!i915_seqno_passed(seqno, obj->last_read_seqno)) |
673a394b | 1890 | break; |
b84d5f0c | 1891 | |
65ce3027 | 1892 | i915_gem_object_move_to_inactive(obj); |
673a394b | 1893 | } |
9d34e5db | 1894 | |
db53a302 CW |
1895 | if (unlikely(ring->trace_irq_seqno && |
1896 | i915_seqno_passed(seqno, ring->trace_irq_seqno))) { | |
1ec14ad3 | 1897 | ring->irq_put(ring); |
db53a302 | 1898 | ring->trace_irq_seqno = 0; |
9d34e5db | 1899 | } |
23bc5982 | 1900 | |
db53a302 | 1901 | WARN_ON(i915_verify_lists(ring->dev)); |
673a394b EA |
1902 | } |
1903 | ||
b09a1fec CW |
1904 | void |
1905 | i915_gem_retire_requests(struct drm_device *dev) | |
1906 | { | |
1907 | drm_i915_private_t *dev_priv = dev->dev_private; | |
b4519513 | 1908 | struct intel_ring_buffer *ring; |
1ec14ad3 | 1909 | int i; |
b09a1fec | 1910 | |
b4519513 CW |
1911 | for_each_ring(ring, dev_priv, i) |
1912 | i915_gem_retire_requests_ring(ring); | |
b09a1fec CW |
1913 | } |
1914 | ||
75ef9da2 | 1915 | static void |
673a394b EA |
1916 | i915_gem_retire_work_handler(struct work_struct *work) |
1917 | { | |
1918 | drm_i915_private_t *dev_priv; | |
1919 | struct drm_device *dev; | |
b4519513 | 1920 | struct intel_ring_buffer *ring; |
0a58705b CW |
1921 | bool idle; |
1922 | int i; | |
673a394b EA |
1923 | |
1924 | dev_priv = container_of(work, drm_i915_private_t, | |
1925 | mm.retire_work.work); | |
1926 | dev = dev_priv->dev; | |
1927 | ||
891b48cf CW |
1928 | /* Come back later if the device is busy... */ |
1929 | if (!mutex_trylock(&dev->struct_mutex)) { | |
1930 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ); | |
1931 | return; | |
1932 | } | |
1933 | ||
b09a1fec | 1934 | i915_gem_retire_requests(dev); |
d1b851fc | 1935 | |
0a58705b CW |
1936 | /* Send a periodic flush down the ring so we don't hold onto GEM |
1937 | * objects indefinitely. | |
1938 | */ | |
1939 | idle = true; | |
b4519513 | 1940 | for_each_ring(ring, dev_priv, i) { |
3bb73aba CW |
1941 | if (ring->gpu_caches_dirty) |
1942 | i915_add_request(ring, NULL, NULL); | |
0a58705b CW |
1943 | |
1944 | idle &= list_empty(&ring->request_list); | |
1945 | } | |
1946 | ||
1947 | if (!dev_priv->mm.suspended && !idle) | |
9c9fe1f8 | 1948 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ); |
f047e395 CW |
1949 | if (idle) |
1950 | intel_mark_idle(dev); | |
0a58705b | 1951 | |
673a394b EA |
1952 | mutex_unlock(&dev->struct_mutex); |
1953 | } | |
1954 | ||
d6b2c790 DV |
1955 | int |
1956 | i915_gem_check_wedge(struct drm_i915_private *dev_priv, | |
1957 | bool interruptible) | |
b4aca010 | 1958 | { |
b4aca010 BW |
1959 | if (atomic_read(&dev_priv->mm.wedged)) { |
1960 | struct completion *x = &dev_priv->error_completion; | |
1961 | bool recovery_complete; | |
1962 | unsigned long flags; | |
1963 | ||
1964 | /* Give the error handler a chance to run. */ | |
1965 | spin_lock_irqsave(&x->wait.lock, flags); | |
1966 | recovery_complete = x->done > 0; | |
1967 | spin_unlock_irqrestore(&x->wait.lock, flags); | |
1968 | ||
d6b2c790 DV |
1969 | /* Non-interruptible callers can't handle -EAGAIN, hence return |
1970 | * -EIO unconditionally for these. */ | |
1971 | if (!interruptible) | |
1972 | return -EIO; | |
1973 | ||
1974 | /* Recovery complete, but still wedged means reset failure. */ | |
1975 | if (recovery_complete) | |
1976 | return -EIO; | |
1977 | ||
1978 | return -EAGAIN; | |
b4aca010 BW |
1979 | } |
1980 | ||
1981 | return 0; | |
1982 | } | |
1983 | ||
1984 | /* | |
1985 | * Compare seqno against outstanding lazy request. Emit a request if they are | |
1986 | * equal. | |
1987 | */ | |
1988 | static int | |
1989 | i915_gem_check_olr(struct intel_ring_buffer *ring, u32 seqno) | |
1990 | { | |
3bb73aba | 1991 | int ret; |
b4aca010 BW |
1992 | |
1993 | BUG_ON(!mutex_is_locked(&ring->dev->struct_mutex)); | |
1994 | ||
3bb73aba CW |
1995 | ret = 0; |
1996 | if (seqno == ring->outstanding_lazy_request) | |
1997 | ret = i915_add_request(ring, NULL, NULL); | |
b4aca010 BW |
1998 | |
1999 | return ret; | |
2000 | } | |
2001 | ||
5c81fe85 BW |
2002 | /** |
2003 | * __wait_seqno - wait until execution of seqno has finished | |
2004 | * @ring: the ring expected to report seqno | |
2005 | * @seqno: duh! | |
2006 | * @interruptible: do an interruptible wait (normally yes) | |
2007 | * @timeout: in - how long to wait (NULL forever); out - how much time remaining | |
2008 | * | |
2009 | * Returns 0 if the seqno was found within the alloted time. Else returns the | |
2010 | * errno with remaining time filled in timeout argument. | |
2011 | */ | |
604dd3ec | 2012 | static int __wait_seqno(struct intel_ring_buffer *ring, u32 seqno, |
5c81fe85 | 2013 | bool interruptible, struct timespec *timeout) |
604dd3ec BW |
2014 | { |
2015 | drm_i915_private_t *dev_priv = ring->dev->dev_private; | |
5c81fe85 BW |
2016 | struct timespec before, now, wait_time={1,0}; |
2017 | unsigned long timeout_jiffies; | |
2018 | long end; | |
2019 | bool wait_forever = true; | |
d6b2c790 | 2020 | int ret; |
604dd3ec | 2021 | |
b2eadbc8 | 2022 | if (i915_seqno_passed(ring->get_seqno(ring, true), seqno)) |
604dd3ec BW |
2023 | return 0; |
2024 | ||
2025 | trace_i915_gem_request_wait_begin(ring, seqno); | |
5c81fe85 BW |
2026 | |
2027 | if (timeout != NULL) { | |
2028 | wait_time = *timeout; | |
2029 | wait_forever = false; | |
2030 | } | |
2031 | ||
2032 | timeout_jiffies = timespec_to_jiffies(&wait_time); | |
2033 | ||
604dd3ec BW |
2034 | if (WARN_ON(!ring->irq_get(ring))) |
2035 | return -ENODEV; | |
2036 | ||
5c81fe85 BW |
2037 | /* Record current time in case interrupted by signal, or wedged * */ |
2038 | getrawmonotonic(&before); | |
2039 | ||
604dd3ec | 2040 | #define EXIT_COND \ |
b2eadbc8 | 2041 | (i915_seqno_passed(ring->get_seqno(ring, false), seqno) || \ |
604dd3ec | 2042 | atomic_read(&dev_priv->mm.wedged)) |
5c81fe85 BW |
2043 | do { |
2044 | if (interruptible) | |
2045 | end = wait_event_interruptible_timeout(ring->irq_queue, | |
2046 | EXIT_COND, | |
2047 | timeout_jiffies); | |
2048 | else | |
2049 | end = wait_event_timeout(ring->irq_queue, EXIT_COND, | |
2050 | timeout_jiffies); | |
604dd3ec | 2051 | |
d6b2c790 DV |
2052 | ret = i915_gem_check_wedge(dev_priv, interruptible); |
2053 | if (ret) | |
2054 | end = ret; | |
5c81fe85 BW |
2055 | } while (end == 0 && wait_forever); |
2056 | ||
2057 | getrawmonotonic(&now); | |
604dd3ec BW |
2058 | |
2059 | ring->irq_put(ring); | |
2060 | trace_i915_gem_request_wait_end(ring, seqno); | |
2061 | #undef EXIT_COND | |
2062 | ||
5c81fe85 BW |
2063 | if (timeout) { |
2064 | struct timespec sleep_time = timespec_sub(now, before); | |
2065 | *timeout = timespec_sub(*timeout, sleep_time); | |
2066 | } | |
2067 | ||
2068 | switch (end) { | |
eeef9b38 | 2069 | case -EIO: |
5c81fe85 BW |
2070 | case -EAGAIN: /* Wedged */ |
2071 | case -ERESTARTSYS: /* Signal */ | |
2072 | return (int)end; | |
2073 | case 0: /* Timeout */ | |
2074 | if (timeout) | |
2075 | set_normalized_timespec(timeout, 0, 0); | |
2076 | return -ETIME; | |
2077 | default: /* Completed */ | |
2078 | WARN_ON(end < 0); /* We're not aware of other errors */ | |
2079 | return 0; | |
2080 | } | |
604dd3ec BW |
2081 | } |
2082 | ||
db53a302 CW |
2083 | /** |
2084 | * Waits for a sequence number to be signaled, and cleans up the | |
2085 | * request and object lists appropriately for that event. | |
2086 | */ | |
5a5a0c64 | 2087 | int |
199b2bc2 | 2088 | i915_wait_seqno(struct intel_ring_buffer *ring, uint32_t seqno) |
673a394b | 2089 | { |
db53a302 | 2090 | drm_i915_private_t *dev_priv = ring->dev->dev_private; |
673a394b EA |
2091 | int ret = 0; |
2092 | ||
2093 | BUG_ON(seqno == 0); | |
2094 | ||
d6b2c790 | 2095 | ret = i915_gem_check_wedge(dev_priv, dev_priv->mm.interruptible); |
b4aca010 BW |
2096 | if (ret) |
2097 | return ret; | |
3cce469c | 2098 | |
b4aca010 BW |
2099 | ret = i915_gem_check_olr(ring, seqno); |
2100 | if (ret) | |
2101 | return ret; | |
ffed1d09 | 2102 | |
5c81fe85 | 2103 | ret = __wait_seqno(ring, seqno, dev_priv->mm.interruptible, NULL); |
673a394b | 2104 | |
673a394b EA |
2105 | return ret; |
2106 | } | |
2107 | ||
673a394b EA |
2108 | /** |
2109 | * Ensures that all rendering to the object has completed and the object is | |
2110 | * safe to unbind from the GTT or access from the CPU. | |
2111 | */ | |
0201f1ec CW |
2112 | static __must_check int |
2113 | i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj, | |
2114 | bool readonly) | |
673a394b | 2115 | { |
0201f1ec | 2116 | u32 seqno; |
673a394b EA |
2117 | int ret; |
2118 | ||
673a394b EA |
2119 | /* If there is rendering queued on the buffer being evicted, wait for |
2120 | * it. | |
2121 | */ | |
0201f1ec CW |
2122 | if (readonly) |
2123 | seqno = obj->last_write_seqno; | |
2124 | else | |
2125 | seqno = obj->last_read_seqno; | |
2126 | if (seqno == 0) | |
2127 | return 0; | |
2128 | ||
2129 | ret = i915_wait_seqno(obj->ring, seqno); | |
2130 | if (ret) | |
2131 | return ret; | |
2132 | ||
2133 | /* Manually manage the write flush as we may have not yet retired | |
2134 | * the buffer. | |
2135 | */ | |
2136 | if (obj->last_write_seqno && | |
2137 | i915_seqno_passed(seqno, obj->last_write_seqno)) { | |
2138 | obj->last_write_seqno = 0; | |
2139 | obj->base.write_domain &= ~I915_GEM_GPU_DOMAINS; | |
673a394b EA |
2140 | } |
2141 | ||
0201f1ec | 2142 | i915_gem_retire_requests_ring(obj->ring); |
673a394b EA |
2143 | return 0; |
2144 | } | |
2145 | ||
30dfebf3 DV |
2146 | /** |
2147 | * Ensures that an object will eventually get non-busy by flushing any required | |
2148 | * write domains, emitting any outstanding lazy request and retiring and | |
2149 | * completed requests. | |
2150 | */ | |
2151 | static int | |
2152 | i915_gem_object_flush_active(struct drm_i915_gem_object *obj) | |
2153 | { | |
2154 | int ret; | |
2155 | ||
2156 | if (obj->active) { | |
0201f1ec | 2157 | ret = i915_gem_check_olr(obj->ring, obj->last_read_seqno); |
30dfebf3 DV |
2158 | if (ret) |
2159 | return ret; | |
0201f1ec | 2160 | |
30dfebf3 DV |
2161 | i915_gem_retire_requests_ring(obj->ring); |
2162 | } | |
2163 | ||
2164 | return 0; | |
2165 | } | |
2166 | ||
23ba4fd0 BW |
2167 | /** |
2168 | * i915_gem_wait_ioctl - implements DRM_IOCTL_I915_GEM_WAIT | |
2169 | * @DRM_IOCTL_ARGS: standard ioctl arguments | |
2170 | * | |
2171 | * Returns 0 if successful, else an error is returned with the remaining time in | |
2172 | * the timeout parameter. | |
2173 | * -ETIME: object is still busy after timeout | |
2174 | * -ERESTARTSYS: signal interrupted the wait | |
2175 | * -ENONENT: object doesn't exist | |
2176 | * Also possible, but rare: | |
2177 | * -EAGAIN: GPU wedged | |
2178 | * -ENOMEM: damn | |
2179 | * -ENODEV: Internal IRQ fail | |
2180 | * -E?: The add request failed | |
2181 | * | |
2182 | * The wait ioctl with a timeout of 0 reimplements the busy ioctl. With any | |
2183 | * non-zero timeout parameter the wait ioctl will wait for the given number of | |
2184 | * nanoseconds on an object becoming unbusy. Since the wait itself does so | |
2185 | * without holding struct_mutex the object may become re-busied before this | |
2186 | * function completes. A similar but shorter * race condition exists in the busy | |
2187 | * ioctl | |
2188 | */ | |
2189 | int | |
2190 | i915_gem_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *file) | |
2191 | { | |
2192 | struct drm_i915_gem_wait *args = data; | |
2193 | struct drm_i915_gem_object *obj; | |
2194 | struct intel_ring_buffer *ring = NULL; | |
eac1f14f | 2195 | struct timespec timeout_stack, *timeout = NULL; |
23ba4fd0 BW |
2196 | u32 seqno = 0; |
2197 | int ret = 0; | |
2198 | ||
eac1f14f BW |
2199 | if (args->timeout_ns >= 0) { |
2200 | timeout_stack = ns_to_timespec(args->timeout_ns); | |
2201 | timeout = &timeout_stack; | |
2202 | } | |
23ba4fd0 BW |
2203 | |
2204 | ret = i915_mutex_lock_interruptible(dev); | |
2205 | if (ret) | |
2206 | return ret; | |
2207 | ||
2208 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->bo_handle)); | |
2209 | if (&obj->base == NULL) { | |
2210 | mutex_unlock(&dev->struct_mutex); | |
2211 | return -ENOENT; | |
2212 | } | |
2213 | ||
30dfebf3 DV |
2214 | /* Need to make sure the object gets inactive eventually. */ |
2215 | ret = i915_gem_object_flush_active(obj); | |
23ba4fd0 BW |
2216 | if (ret) |
2217 | goto out; | |
2218 | ||
2219 | if (obj->active) { | |
0201f1ec | 2220 | seqno = obj->last_read_seqno; |
23ba4fd0 BW |
2221 | ring = obj->ring; |
2222 | } | |
2223 | ||
2224 | if (seqno == 0) | |
2225 | goto out; | |
2226 | ||
23ba4fd0 BW |
2227 | /* Do this after OLR check to make sure we make forward progress polling |
2228 | * on this IOCTL with a 0 timeout (like busy ioctl) | |
2229 | */ | |
2230 | if (!args->timeout_ns) { | |
2231 | ret = -ETIME; | |
2232 | goto out; | |
2233 | } | |
2234 | ||
2235 | drm_gem_object_unreference(&obj->base); | |
2236 | mutex_unlock(&dev->struct_mutex); | |
2237 | ||
eac1f14f BW |
2238 | ret = __wait_seqno(ring, seqno, true, timeout); |
2239 | if (timeout) { | |
2240 | WARN_ON(!timespec_valid(timeout)); | |
2241 | args->timeout_ns = timespec_to_ns(timeout); | |
2242 | } | |
23ba4fd0 BW |
2243 | return ret; |
2244 | ||
2245 | out: | |
2246 | drm_gem_object_unreference(&obj->base); | |
2247 | mutex_unlock(&dev->struct_mutex); | |
2248 | return ret; | |
2249 | } | |
2250 | ||
5816d648 BW |
2251 | /** |
2252 | * i915_gem_object_sync - sync an object to a ring. | |
2253 | * | |
2254 | * @obj: object which may be in use on another ring. | |
2255 | * @to: ring we wish to use the object on. May be NULL. | |
2256 | * | |
2257 | * This code is meant to abstract object synchronization with the GPU. | |
2258 | * Calling with NULL implies synchronizing the object with the CPU | |
2259 | * rather than a particular GPU ring. | |
2260 | * | |
2261 | * Returns 0 if successful, else propagates up the lower layer error. | |
2262 | */ | |
2911a35b BW |
2263 | int |
2264 | i915_gem_object_sync(struct drm_i915_gem_object *obj, | |
2265 | struct intel_ring_buffer *to) | |
2266 | { | |
2267 | struct intel_ring_buffer *from = obj->ring; | |
2268 | u32 seqno; | |
2269 | int ret, idx; | |
2270 | ||
2271 | if (from == NULL || to == from) | |
2272 | return 0; | |
2273 | ||
5816d648 | 2274 | if (to == NULL || !i915_semaphore_is_enabled(obj->base.dev)) |
0201f1ec | 2275 | return i915_gem_object_wait_rendering(obj, false); |
2911a35b BW |
2276 | |
2277 | idx = intel_ring_sync_index(from, to); | |
2278 | ||
0201f1ec | 2279 | seqno = obj->last_read_seqno; |
2911a35b BW |
2280 | if (seqno <= from->sync_seqno[idx]) |
2281 | return 0; | |
2282 | ||
b4aca010 BW |
2283 | ret = i915_gem_check_olr(obj->ring, seqno); |
2284 | if (ret) | |
2285 | return ret; | |
2911a35b | 2286 | |
1500f7ea | 2287 | ret = to->sync_to(to, from, seqno); |
e3a5a225 BW |
2288 | if (!ret) |
2289 | from->sync_seqno[idx] = seqno; | |
2911a35b | 2290 | |
e3a5a225 | 2291 | return ret; |
2911a35b BW |
2292 | } |
2293 | ||
b5ffc9bc CW |
2294 | static void i915_gem_object_finish_gtt(struct drm_i915_gem_object *obj) |
2295 | { | |
2296 | u32 old_write_domain, old_read_domains; | |
2297 | ||
b5ffc9bc CW |
2298 | /* Act a barrier for all accesses through the GTT */ |
2299 | mb(); | |
2300 | ||
2301 | /* Force a pagefault for domain tracking on next user access */ | |
2302 | i915_gem_release_mmap(obj); | |
2303 | ||
b97c3d9c KP |
2304 | if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0) |
2305 | return; | |
2306 | ||
b5ffc9bc CW |
2307 | old_read_domains = obj->base.read_domains; |
2308 | old_write_domain = obj->base.write_domain; | |
2309 | ||
2310 | obj->base.read_domains &= ~I915_GEM_DOMAIN_GTT; | |
2311 | obj->base.write_domain &= ~I915_GEM_DOMAIN_GTT; | |
2312 | ||
2313 | trace_i915_gem_object_change_domain(obj, | |
2314 | old_read_domains, | |
2315 | old_write_domain); | |
2316 | } | |
2317 | ||
673a394b EA |
2318 | /** |
2319 | * Unbinds an object from the GTT aperture. | |
2320 | */ | |
0f973f27 | 2321 | int |
05394f39 | 2322 | i915_gem_object_unbind(struct drm_i915_gem_object *obj) |
673a394b | 2323 | { |
7bddb01f | 2324 | drm_i915_private_t *dev_priv = obj->base.dev->dev_private; |
673a394b EA |
2325 | int ret = 0; |
2326 | ||
05394f39 | 2327 | if (obj->gtt_space == NULL) |
673a394b EA |
2328 | return 0; |
2329 | ||
31d8d651 CW |
2330 | if (obj->pin_count) |
2331 | return -EBUSY; | |
673a394b | 2332 | |
c4670ad0 CW |
2333 | BUG_ON(obj->pages == NULL); |
2334 | ||
a8198eea | 2335 | ret = i915_gem_object_finish_gpu(obj); |
1488fc08 | 2336 | if (ret) |
a8198eea CW |
2337 | return ret; |
2338 | /* Continue on if we fail due to EIO, the GPU is hung so we | |
2339 | * should be safe and we need to cleanup or else we might | |
2340 | * cause memory corruption through use-after-free. | |
2341 | */ | |
2342 | ||
b5ffc9bc | 2343 | i915_gem_object_finish_gtt(obj); |
5323fd04 | 2344 | |
96b47b65 | 2345 | /* release the fence reg _after_ flushing */ |
d9e86c0e | 2346 | ret = i915_gem_object_put_fence(obj); |
1488fc08 | 2347 | if (ret) |
d9e86c0e | 2348 | return ret; |
96b47b65 | 2349 | |
db53a302 CW |
2350 | trace_i915_gem_object_unbind(obj); |
2351 | ||
74898d7e DV |
2352 | if (obj->has_global_gtt_mapping) |
2353 | i915_gem_gtt_unbind_object(obj); | |
7bddb01f DV |
2354 | if (obj->has_aliasing_ppgtt_mapping) { |
2355 | i915_ppgtt_unbind_object(dev_priv->mm.aliasing_ppgtt, obj); | |
2356 | obj->has_aliasing_ppgtt_mapping = 0; | |
2357 | } | |
74163907 | 2358 | i915_gem_gtt_finish_object(obj); |
7bddb01f | 2359 | |
6c085a72 CW |
2360 | list_del(&obj->mm_list); |
2361 | list_move_tail(&obj->gtt_list, &dev_priv->mm.unbound_list); | |
75e9e915 | 2362 | /* Avoid an unnecessary call to unbind on rebind. */ |
05394f39 | 2363 | obj->map_and_fenceable = true; |
673a394b | 2364 | |
05394f39 CW |
2365 | drm_mm_put_block(obj->gtt_space); |
2366 | obj->gtt_space = NULL; | |
2367 | obj->gtt_offset = 0; | |
673a394b | 2368 | |
6c085a72 | 2369 | return 0; |
673a394b EA |
2370 | } |
2371 | ||
b2da9fe5 | 2372 | static int i915_ring_idle(struct intel_ring_buffer *ring) |
a56ba56c | 2373 | { |
69c2fc89 | 2374 | if (list_empty(&ring->active_list)) |
64193406 CW |
2375 | return 0; |
2376 | ||
199b2bc2 | 2377 | return i915_wait_seqno(ring, i915_gem_next_request_seqno(ring)); |
a56ba56c CW |
2378 | } |
2379 | ||
b2da9fe5 | 2380 | int i915_gpu_idle(struct drm_device *dev) |
4df2faf4 DV |
2381 | { |
2382 | drm_i915_private_t *dev_priv = dev->dev_private; | |
b4519513 | 2383 | struct intel_ring_buffer *ring; |
1ec14ad3 | 2384 | int ret, i; |
4df2faf4 | 2385 | |
4df2faf4 | 2386 | /* Flush everything onto the inactive list. */ |
b4519513 CW |
2387 | for_each_ring(ring, dev_priv, i) { |
2388 | ret = i915_ring_idle(ring); | |
1ec14ad3 CW |
2389 | if (ret) |
2390 | return ret; | |
b4519513 | 2391 | |
f2ef6eb1 BW |
2392 | ret = i915_switch_context(ring, NULL, DEFAULT_CONTEXT_ID); |
2393 | if (ret) | |
2394 | return ret; | |
1ec14ad3 | 2395 | } |
4df2faf4 | 2396 | |
8a1a49f9 | 2397 | return 0; |
4df2faf4 DV |
2398 | } |
2399 | ||
9ce079e4 CW |
2400 | static void sandybridge_write_fence_reg(struct drm_device *dev, int reg, |
2401 | struct drm_i915_gem_object *obj) | |
4e901fdc | 2402 | { |
4e901fdc | 2403 | drm_i915_private_t *dev_priv = dev->dev_private; |
4e901fdc EA |
2404 | uint64_t val; |
2405 | ||
9ce079e4 CW |
2406 | if (obj) { |
2407 | u32 size = obj->gtt_space->size; | |
4e901fdc | 2408 | |
9ce079e4 CW |
2409 | val = (uint64_t)((obj->gtt_offset + size - 4096) & |
2410 | 0xfffff000) << 32; | |
2411 | val |= obj->gtt_offset & 0xfffff000; | |
2412 | val |= (uint64_t)((obj->stride / 128) - 1) << | |
2413 | SANDYBRIDGE_FENCE_PITCH_SHIFT; | |
4e901fdc | 2414 | |
9ce079e4 CW |
2415 | if (obj->tiling_mode == I915_TILING_Y) |
2416 | val |= 1 << I965_FENCE_TILING_Y_SHIFT; | |
2417 | val |= I965_FENCE_REG_VALID; | |
2418 | } else | |
2419 | val = 0; | |
c6642782 | 2420 | |
9ce079e4 CW |
2421 | I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + reg * 8, val); |
2422 | POSTING_READ(FENCE_REG_SANDYBRIDGE_0 + reg * 8); | |
4e901fdc EA |
2423 | } |
2424 | ||
9ce079e4 CW |
2425 | static void i965_write_fence_reg(struct drm_device *dev, int reg, |
2426 | struct drm_i915_gem_object *obj) | |
de151cf6 | 2427 | { |
de151cf6 | 2428 | drm_i915_private_t *dev_priv = dev->dev_private; |
de151cf6 JB |
2429 | uint64_t val; |
2430 | ||
9ce079e4 CW |
2431 | if (obj) { |
2432 | u32 size = obj->gtt_space->size; | |
de151cf6 | 2433 | |
9ce079e4 CW |
2434 | val = (uint64_t)((obj->gtt_offset + size - 4096) & |
2435 | 0xfffff000) << 32; | |
2436 | val |= obj->gtt_offset & 0xfffff000; | |
2437 | val |= ((obj->stride / 128) - 1) << I965_FENCE_PITCH_SHIFT; | |
2438 | if (obj->tiling_mode == I915_TILING_Y) | |
2439 | val |= 1 << I965_FENCE_TILING_Y_SHIFT; | |
2440 | val |= I965_FENCE_REG_VALID; | |
2441 | } else | |
2442 | val = 0; | |
c6642782 | 2443 | |
9ce079e4 CW |
2444 | I915_WRITE64(FENCE_REG_965_0 + reg * 8, val); |
2445 | POSTING_READ(FENCE_REG_965_0 + reg * 8); | |
de151cf6 JB |
2446 | } |
2447 | ||
9ce079e4 CW |
2448 | static void i915_write_fence_reg(struct drm_device *dev, int reg, |
2449 | struct drm_i915_gem_object *obj) | |
de151cf6 | 2450 | { |
de151cf6 | 2451 | drm_i915_private_t *dev_priv = dev->dev_private; |
9ce079e4 | 2452 | u32 val; |
de151cf6 | 2453 | |
9ce079e4 CW |
2454 | if (obj) { |
2455 | u32 size = obj->gtt_space->size; | |
2456 | int pitch_val; | |
2457 | int tile_width; | |
c6642782 | 2458 | |
9ce079e4 CW |
2459 | WARN((obj->gtt_offset & ~I915_FENCE_START_MASK) || |
2460 | (size & -size) != size || | |
2461 | (obj->gtt_offset & (size - 1)), | |
2462 | "object 0x%08x [fenceable? %d] not 1M or pot-size (0x%08x) aligned\n", | |
2463 | obj->gtt_offset, obj->map_and_fenceable, size); | |
c6642782 | 2464 | |
9ce079e4 CW |
2465 | if (obj->tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev)) |
2466 | tile_width = 128; | |
2467 | else | |
2468 | tile_width = 512; | |
2469 | ||
2470 | /* Note: pitch better be a power of two tile widths */ | |
2471 | pitch_val = obj->stride / tile_width; | |
2472 | pitch_val = ffs(pitch_val) - 1; | |
2473 | ||
2474 | val = obj->gtt_offset; | |
2475 | if (obj->tiling_mode == I915_TILING_Y) | |
2476 | val |= 1 << I830_FENCE_TILING_Y_SHIFT; | |
2477 | val |= I915_FENCE_SIZE_BITS(size); | |
2478 | val |= pitch_val << I830_FENCE_PITCH_SHIFT; | |
2479 | val |= I830_FENCE_REG_VALID; | |
2480 | } else | |
2481 | val = 0; | |
2482 | ||
2483 | if (reg < 8) | |
2484 | reg = FENCE_REG_830_0 + reg * 4; | |
2485 | else | |
2486 | reg = FENCE_REG_945_8 + (reg - 8) * 4; | |
2487 | ||
2488 | I915_WRITE(reg, val); | |
2489 | POSTING_READ(reg); | |
de151cf6 JB |
2490 | } |
2491 | ||
9ce079e4 CW |
2492 | static void i830_write_fence_reg(struct drm_device *dev, int reg, |
2493 | struct drm_i915_gem_object *obj) | |
de151cf6 | 2494 | { |
de151cf6 | 2495 | drm_i915_private_t *dev_priv = dev->dev_private; |
de151cf6 | 2496 | uint32_t val; |
de151cf6 | 2497 | |
9ce079e4 CW |
2498 | if (obj) { |
2499 | u32 size = obj->gtt_space->size; | |
2500 | uint32_t pitch_val; | |
de151cf6 | 2501 | |
9ce079e4 CW |
2502 | WARN((obj->gtt_offset & ~I830_FENCE_START_MASK) || |
2503 | (size & -size) != size || | |
2504 | (obj->gtt_offset & (size - 1)), | |
2505 | "object 0x%08x not 512K or pot-size 0x%08x aligned\n", | |
2506 | obj->gtt_offset, size); | |
e76a16de | 2507 | |
9ce079e4 CW |
2508 | pitch_val = obj->stride / 128; |
2509 | pitch_val = ffs(pitch_val) - 1; | |
de151cf6 | 2510 | |
9ce079e4 CW |
2511 | val = obj->gtt_offset; |
2512 | if (obj->tiling_mode == I915_TILING_Y) | |
2513 | val |= 1 << I830_FENCE_TILING_Y_SHIFT; | |
2514 | val |= I830_FENCE_SIZE_BITS(size); | |
2515 | val |= pitch_val << I830_FENCE_PITCH_SHIFT; | |
2516 | val |= I830_FENCE_REG_VALID; | |
2517 | } else | |
2518 | val = 0; | |
c6642782 | 2519 | |
9ce079e4 CW |
2520 | I915_WRITE(FENCE_REG_830_0 + reg * 4, val); |
2521 | POSTING_READ(FENCE_REG_830_0 + reg * 4); | |
2522 | } | |
2523 | ||
2524 | static void i915_gem_write_fence(struct drm_device *dev, int reg, | |
2525 | struct drm_i915_gem_object *obj) | |
2526 | { | |
2527 | switch (INTEL_INFO(dev)->gen) { | |
2528 | case 7: | |
2529 | case 6: sandybridge_write_fence_reg(dev, reg, obj); break; | |
2530 | case 5: | |
2531 | case 4: i965_write_fence_reg(dev, reg, obj); break; | |
2532 | case 3: i915_write_fence_reg(dev, reg, obj); break; | |
2533 | case 2: i830_write_fence_reg(dev, reg, obj); break; | |
2534 | default: break; | |
2535 | } | |
de151cf6 JB |
2536 | } |
2537 | ||
61050808 CW |
2538 | static inline int fence_number(struct drm_i915_private *dev_priv, |
2539 | struct drm_i915_fence_reg *fence) | |
2540 | { | |
2541 | return fence - dev_priv->fence_regs; | |
2542 | } | |
2543 | ||
2544 | static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj, | |
2545 | struct drm_i915_fence_reg *fence, | |
2546 | bool enable) | |
2547 | { | |
2548 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; | |
2549 | int reg = fence_number(dev_priv, fence); | |
2550 | ||
2551 | i915_gem_write_fence(obj->base.dev, reg, enable ? obj : NULL); | |
2552 | ||
2553 | if (enable) { | |
2554 | obj->fence_reg = reg; | |
2555 | fence->obj = obj; | |
2556 | list_move_tail(&fence->lru_list, &dev_priv->mm.fence_list); | |
2557 | } else { | |
2558 | obj->fence_reg = I915_FENCE_REG_NONE; | |
2559 | fence->obj = NULL; | |
2560 | list_del_init(&fence->lru_list); | |
2561 | } | |
2562 | } | |
2563 | ||
d9e86c0e | 2564 | static int |
a360bb1a | 2565 | i915_gem_object_flush_fence(struct drm_i915_gem_object *obj) |
d9e86c0e | 2566 | { |
1c293ea3 | 2567 | if (obj->last_fenced_seqno) { |
86d5bc37 | 2568 | int ret = i915_wait_seqno(obj->ring, obj->last_fenced_seqno); |
18991845 CW |
2569 | if (ret) |
2570 | return ret; | |
d9e86c0e CW |
2571 | |
2572 | obj->last_fenced_seqno = 0; | |
d9e86c0e CW |
2573 | } |
2574 | ||
63256ec5 CW |
2575 | /* Ensure that all CPU reads are completed before installing a fence |
2576 | * and all writes before removing the fence. | |
2577 | */ | |
2578 | if (obj->base.read_domains & I915_GEM_DOMAIN_GTT) | |
2579 | mb(); | |
2580 | ||
86d5bc37 | 2581 | obj->fenced_gpu_access = false; |
d9e86c0e CW |
2582 | return 0; |
2583 | } | |
2584 | ||
2585 | int | |
2586 | i915_gem_object_put_fence(struct drm_i915_gem_object *obj) | |
2587 | { | |
61050808 | 2588 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
d9e86c0e CW |
2589 | int ret; |
2590 | ||
a360bb1a | 2591 | ret = i915_gem_object_flush_fence(obj); |
d9e86c0e CW |
2592 | if (ret) |
2593 | return ret; | |
2594 | ||
61050808 CW |
2595 | if (obj->fence_reg == I915_FENCE_REG_NONE) |
2596 | return 0; | |
d9e86c0e | 2597 | |
61050808 CW |
2598 | i915_gem_object_update_fence(obj, |
2599 | &dev_priv->fence_regs[obj->fence_reg], | |
2600 | false); | |
2601 | i915_gem_object_fence_lost(obj); | |
d9e86c0e CW |
2602 | |
2603 | return 0; | |
2604 | } | |
2605 | ||
2606 | static struct drm_i915_fence_reg * | |
a360bb1a | 2607 | i915_find_fence_reg(struct drm_device *dev) |
ae3db24a | 2608 | { |
ae3db24a | 2609 | struct drm_i915_private *dev_priv = dev->dev_private; |
8fe301ad | 2610 | struct drm_i915_fence_reg *reg, *avail; |
d9e86c0e | 2611 | int i; |
ae3db24a DV |
2612 | |
2613 | /* First try to find a free reg */ | |
d9e86c0e | 2614 | avail = NULL; |
ae3db24a DV |
2615 | for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) { |
2616 | reg = &dev_priv->fence_regs[i]; | |
2617 | if (!reg->obj) | |
d9e86c0e | 2618 | return reg; |
ae3db24a | 2619 | |
1690e1eb | 2620 | if (!reg->pin_count) |
d9e86c0e | 2621 | avail = reg; |
ae3db24a DV |
2622 | } |
2623 | ||
d9e86c0e CW |
2624 | if (avail == NULL) |
2625 | return NULL; | |
ae3db24a DV |
2626 | |
2627 | /* None available, try to steal one or wait for a user to finish */ | |
d9e86c0e | 2628 | list_for_each_entry(reg, &dev_priv->mm.fence_list, lru_list) { |
1690e1eb | 2629 | if (reg->pin_count) |
ae3db24a DV |
2630 | continue; |
2631 | ||
8fe301ad | 2632 | return reg; |
ae3db24a DV |
2633 | } |
2634 | ||
8fe301ad | 2635 | return NULL; |
ae3db24a DV |
2636 | } |
2637 | ||
de151cf6 | 2638 | /** |
9a5a53b3 | 2639 | * i915_gem_object_get_fence - set up fencing for an object |
de151cf6 JB |
2640 | * @obj: object to map through a fence reg |
2641 | * | |
2642 | * When mapping objects through the GTT, userspace wants to be able to write | |
2643 | * to them without having to worry about swizzling if the object is tiled. | |
de151cf6 JB |
2644 | * This function walks the fence regs looking for a free one for @obj, |
2645 | * stealing one if it can't find any. | |
2646 | * | |
2647 | * It then sets up the reg based on the object's properties: address, pitch | |
2648 | * and tiling format. | |
9a5a53b3 CW |
2649 | * |
2650 | * For an untiled surface, this removes any existing fence. | |
de151cf6 | 2651 | */ |
8c4b8c3f | 2652 | int |
06d98131 | 2653 | i915_gem_object_get_fence(struct drm_i915_gem_object *obj) |
de151cf6 | 2654 | { |
05394f39 | 2655 | struct drm_device *dev = obj->base.dev; |
79e53945 | 2656 | struct drm_i915_private *dev_priv = dev->dev_private; |
14415745 | 2657 | bool enable = obj->tiling_mode != I915_TILING_NONE; |
d9e86c0e | 2658 | struct drm_i915_fence_reg *reg; |
ae3db24a | 2659 | int ret; |
de151cf6 | 2660 | |
14415745 CW |
2661 | /* Have we updated the tiling parameters upon the object and so |
2662 | * will need to serialise the write to the associated fence register? | |
2663 | */ | |
5d82e3e6 | 2664 | if (obj->fence_dirty) { |
14415745 CW |
2665 | ret = i915_gem_object_flush_fence(obj); |
2666 | if (ret) | |
2667 | return ret; | |
2668 | } | |
9a5a53b3 | 2669 | |
d9e86c0e | 2670 | /* Just update our place in the LRU if our fence is getting reused. */ |
05394f39 CW |
2671 | if (obj->fence_reg != I915_FENCE_REG_NONE) { |
2672 | reg = &dev_priv->fence_regs[obj->fence_reg]; | |
5d82e3e6 | 2673 | if (!obj->fence_dirty) { |
14415745 CW |
2674 | list_move_tail(®->lru_list, |
2675 | &dev_priv->mm.fence_list); | |
2676 | return 0; | |
2677 | } | |
2678 | } else if (enable) { | |
2679 | reg = i915_find_fence_reg(dev); | |
2680 | if (reg == NULL) | |
2681 | return -EDEADLK; | |
d9e86c0e | 2682 | |
14415745 CW |
2683 | if (reg->obj) { |
2684 | struct drm_i915_gem_object *old = reg->obj; | |
2685 | ||
2686 | ret = i915_gem_object_flush_fence(old); | |
29c5a587 CW |
2687 | if (ret) |
2688 | return ret; | |
2689 | ||
14415745 | 2690 | i915_gem_object_fence_lost(old); |
29c5a587 | 2691 | } |
14415745 | 2692 | } else |
a09ba7fa | 2693 | return 0; |
a09ba7fa | 2694 | |
14415745 | 2695 | i915_gem_object_update_fence(obj, reg, enable); |
5d82e3e6 | 2696 | obj->fence_dirty = false; |
14415745 | 2697 | |
9ce079e4 | 2698 | return 0; |
de151cf6 JB |
2699 | } |
2700 | ||
42d6ab48 CW |
2701 | static bool i915_gem_valid_gtt_space(struct drm_device *dev, |
2702 | struct drm_mm_node *gtt_space, | |
2703 | unsigned long cache_level) | |
2704 | { | |
2705 | struct drm_mm_node *other; | |
2706 | ||
2707 | /* On non-LLC machines we have to be careful when putting differing | |
2708 | * types of snoopable memory together to avoid the prefetcher | |
2709 | * crossing memory domains and dieing. | |
2710 | */ | |
2711 | if (HAS_LLC(dev)) | |
2712 | return true; | |
2713 | ||
2714 | if (gtt_space == NULL) | |
2715 | return true; | |
2716 | ||
2717 | if (list_empty(>t_space->node_list)) | |
2718 | return true; | |
2719 | ||
2720 | other = list_entry(gtt_space->node_list.prev, struct drm_mm_node, node_list); | |
2721 | if (other->allocated && !other->hole_follows && other->color != cache_level) | |
2722 | return false; | |
2723 | ||
2724 | other = list_entry(gtt_space->node_list.next, struct drm_mm_node, node_list); | |
2725 | if (other->allocated && !gtt_space->hole_follows && other->color != cache_level) | |
2726 | return false; | |
2727 | ||
2728 | return true; | |
2729 | } | |
2730 | ||
2731 | static void i915_gem_verify_gtt(struct drm_device *dev) | |
2732 | { | |
2733 | #if WATCH_GTT | |
2734 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2735 | struct drm_i915_gem_object *obj; | |
2736 | int err = 0; | |
2737 | ||
2738 | list_for_each_entry(obj, &dev_priv->mm.gtt_list, gtt_list) { | |
2739 | if (obj->gtt_space == NULL) { | |
2740 | printk(KERN_ERR "object found on GTT list with no space reserved\n"); | |
2741 | err++; | |
2742 | continue; | |
2743 | } | |
2744 | ||
2745 | if (obj->cache_level != obj->gtt_space->color) { | |
2746 | printk(KERN_ERR "object reserved space [%08lx, %08lx] with wrong color, cache_level=%x, color=%lx\n", | |
2747 | obj->gtt_space->start, | |
2748 | obj->gtt_space->start + obj->gtt_space->size, | |
2749 | obj->cache_level, | |
2750 | obj->gtt_space->color); | |
2751 | err++; | |
2752 | continue; | |
2753 | } | |
2754 | ||
2755 | if (!i915_gem_valid_gtt_space(dev, | |
2756 | obj->gtt_space, | |
2757 | obj->cache_level)) { | |
2758 | printk(KERN_ERR "invalid GTT space found at [%08lx, %08lx] - color=%x\n", | |
2759 | obj->gtt_space->start, | |
2760 | obj->gtt_space->start + obj->gtt_space->size, | |
2761 | obj->cache_level); | |
2762 | err++; | |
2763 | continue; | |
2764 | } | |
2765 | } | |
2766 | ||
2767 | WARN_ON(err); | |
2768 | #endif | |
2769 | } | |
2770 | ||
673a394b EA |
2771 | /** |
2772 | * Finds free space in the GTT aperture and binds the object there. | |
2773 | */ | |
2774 | static int | |
05394f39 | 2775 | i915_gem_object_bind_to_gtt(struct drm_i915_gem_object *obj, |
920afa77 | 2776 | unsigned alignment, |
86a1ee26 CW |
2777 | bool map_and_fenceable, |
2778 | bool nonblocking) | |
673a394b | 2779 | { |
05394f39 | 2780 | struct drm_device *dev = obj->base.dev; |
673a394b | 2781 | drm_i915_private_t *dev_priv = dev->dev_private; |
673a394b | 2782 | struct drm_mm_node *free_space; |
5e783301 | 2783 | u32 size, fence_size, fence_alignment, unfenced_alignment; |
75e9e915 | 2784 | bool mappable, fenceable; |
07f73f69 | 2785 | int ret; |
673a394b | 2786 | |
05394f39 | 2787 | if (obj->madv != I915_MADV_WILLNEED) { |
3ef94daa CW |
2788 | DRM_ERROR("Attempting to bind a purgeable object\n"); |
2789 | return -EINVAL; | |
2790 | } | |
2791 | ||
e28f8711 CW |
2792 | fence_size = i915_gem_get_gtt_size(dev, |
2793 | obj->base.size, | |
2794 | obj->tiling_mode); | |
2795 | fence_alignment = i915_gem_get_gtt_alignment(dev, | |
2796 | obj->base.size, | |
2797 | obj->tiling_mode); | |
2798 | unfenced_alignment = | |
2799 | i915_gem_get_unfenced_gtt_alignment(dev, | |
2800 | obj->base.size, | |
2801 | obj->tiling_mode); | |
a00b10c3 | 2802 | |
673a394b | 2803 | if (alignment == 0) |
5e783301 DV |
2804 | alignment = map_and_fenceable ? fence_alignment : |
2805 | unfenced_alignment; | |
75e9e915 | 2806 | if (map_and_fenceable && alignment & (fence_alignment - 1)) { |
673a394b EA |
2807 | DRM_ERROR("Invalid object alignment requested %u\n", alignment); |
2808 | return -EINVAL; | |
2809 | } | |
2810 | ||
05394f39 | 2811 | size = map_and_fenceable ? fence_size : obj->base.size; |
a00b10c3 | 2812 | |
654fc607 CW |
2813 | /* If the object is bigger than the entire aperture, reject it early |
2814 | * before evicting everything in a vain attempt to find space. | |
2815 | */ | |
05394f39 | 2816 | if (obj->base.size > |
75e9e915 | 2817 | (map_and_fenceable ? dev_priv->mm.gtt_mappable_end : dev_priv->mm.gtt_total)) { |
654fc607 CW |
2818 | DRM_ERROR("Attempting to bind an object larger than the aperture\n"); |
2819 | return -E2BIG; | |
2820 | } | |
2821 | ||
6c085a72 CW |
2822 | ret = i915_gem_object_get_pages_gtt(obj); |
2823 | if (ret) | |
2824 | return ret; | |
2825 | ||
673a394b | 2826 | search_free: |
75e9e915 | 2827 | if (map_and_fenceable) |
920afa77 | 2828 | free_space = |
42d6ab48 CW |
2829 | drm_mm_search_free_in_range_color(&dev_priv->mm.gtt_space, |
2830 | size, alignment, obj->cache_level, | |
2831 | 0, dev_priv->mm.gtt_mappable_end, | |
2832 | false); | |
920afa77 | 2833 | else |
42d6ab48 CW |
2834 | free_space = drm_mm_search_free_color(&dev_priv->mm.gtt_space, |
2835 | size, alignment, obj->cache_level, | |
2836 | false); | |
920afa77 DV |
2837 | |
2838 | if (free_space != NULL) { | |
75e9e915 | 2839 | if (map_and_fenceable) |
05394f39 | 2840 | obj->gtt_space = |
920afa77 | 2841 | drm_mm_get_block_range_generic(free_space, |
42d6ab48 | 2842 | size, alignment, obj->cache_level, |
6b9d89b4 | 2843 | 0, dev_priv->mm.gtt_mappable_end, |
42d6ab48 | 2844 | false); |
920afa77 | 2845 | else |
05394f39 | 2846 | obj->gtt_space = |
42d6ab48 CW |
2847 | drm_mm_get_block_generic(free_space, |
2848 | size, alignment, obj->cache_level, | |
2849 | false); | |
920afa77 | 2850 | } |
05394f39 | 2851 | if (obj->gtt_space == NULL) { |
75e9e915 | 2852 | ret = i915_gem_evict_something(dev, size, alignment, |
42d6ab48 | 2853 | obj->cache_level, |
86a1ee26 CW |
2854 | map_and_fenceable, |
2855 | nonblocking); | |
9731129c | 2856 | if (ret) |
673a394b | 2857 | return ret; |
9731129c | 2858 | |
673a394b EA |
2859 | goto search_free; |
2860 | } | |
42d6ab48 CW |
2861 | if (WARN_ON(!i915_gem_valid_gtt_space(dev, |
2862 | obj->gtt_space, | |
2863 | obj->cache_level))) { | |
2864 | drm_mm_put_block(obj->gtt_space); | |
2865 | obj->gtt_space = NULL; | |
2866 | return -EINVAL; | |
2867 | } | |
673a394b | 2868 | |
673a394b | 2869 | |
74163907 | 2870 | ret = i915_gem_gtt_prepare_object(obj); |
7c2e6fdf | 2871 | if (ret) { |
05394f39 CW |
2872 | drm_mm_put_block(obj->gtt_space); |
2873 | obj->gtt_space = NULL; | |
6c085a72 | 2874 | return ret; |
673a394b | 2875 | } |
673a394b | 2876 | |
0ebb9829 DV |
2877 | if (!dev_priv->mm.aliasing_ppgtt) |
2878 | i915_gem_gtt_bind_object(obj, obj->cache_level); | |
673a394b | 2879 | |
6c085a72 | 2880 | list_move_tail(&obj->gtt_list, &dev_priv->mm.bound_list); |
05394f39 | 2881 | list_add_tail(&obj->mm_list, &dev_priv->mm.inactive_list); |
bf1a1092 | 2882 | |
6299f992 | 2883 | obj->gtt_offset = obj->gtt_space->start; |
1c5d22f7 | 2884 | |
75e9e915 | 2885 | fenceable = |
05394f39 | 2886 | obj->gtt_space->size == fence_size && |
0206e353 | 2887 | (obj->gtt_space->start & (fence_alignment - 1)) == 0; |
a00b10c3 | 2888 | |
75e9e915 | 2889 | mappable = |
05394f39 | 2890 | obj->gtt_offset + obj->base.size <= dev_priv->mm.gtt_mappable_end; |
a00b10c3 | 2891 | |
05394f39 | 2892 | obj->map_and_fenceable = mappable && fenceable; |
75e9e915 | 2893 | |
db53a302 | 2894 | trace_i915_gem_object_bind(obj, map_and_fenceable); |
42d6ab48 | 2895 | i915_gem_verify_gtt(dev); |
673a394b EA |
2896 | return 0; |
2897 | } | |
2898 | ||
2899 | void | |
05394f39 | 2900 | i915_gem_clflush_object(struct drm_i915_gem_object *obj) |
673a394b | 2901 | { |
673a394b EA |
2902 | /* If we don't have a page list set up, then we're not pinned |
2903 | * to GPU, and we can ignore the cache flush because it'll happen | |
2904 | * again at bind time. | |
2905 | */ | |
05394f39 | 2906 | if (obj->pages == NULL) |
673a394b EA |
2907 | return; |
2908 | ||
9c23f7fc CW |
2909 | /* If the GPU is snooping the contents of the CPU cache, |
2910 | * we do not need to manually clear the CPU cache lines. However, | |
2911 | * the caches are only snooped when the render cache is | |
2912 | * flushed/invalidated. As we always have to emit invalidations | |
2913 | * and flushes when moving into and out of the RENDER domain, correct | |
2914 | * snooping behaviour occurs naturally as the result of our domain | |
2915 | * tracking. | |
2916 | */ | |
2917 | if (obj->cache_level != I915_CACHE_NONE) | |
2918 | return; | |
2919 | ||
1c5d22f7 | 2920 | trace_i915_gem_object_clflush(obj); |
cfa16a0d | 2921 | |
05394f39 | 2922 | drm_clflush_pages(obj->pages, obj->base.size / PAGE_SIZE); |
673a394b EA |
2923 | } |
2924 | ||
e47c68e9 EA |
2925 | /** Flushes the GTT write domain for the object if it's dirty. */ |
2926 | static void | |
05394f39 | 2927 | i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj) |
e47c68e9 | 2928 | { |
1c5d22f7 CW |
2929 | uint32_t old_write_domain; |
2930 | ||
05394f39 | 2931 | if (obj->base.write_domain != I915_GEM_DOMAIN_GTT) |
e47c68e9 EA |
2932 | return; |
2933 | ||
63256ec5 | 2934 | /* No actual flushing is required for the GTT write domain. Writes |
e47c68e9 EA |
2935 | * to it immediately go to main memory as far as we know, so there's |
2936 | * no chipset flush. It also doesn't land in render cache. | |
63256ec5 CW |
2937 | * |
2938 | * However, we do have to enforce the order so that all writes through | |
2939 | * the GTT land before any writes to the device, such as updates to | |
2940 | * the GATT itself. | |
e47c68e9 | 2941 | */ |
63256ec5 CW |
2942 | wmb(); |
2943 | ||
05394f39 CW |
2944 | old_write_domain = obj->base.write_domain; |
2945 | obj->base.write_domain = 0; | |
1c5d22f7 CW |
2946 | |
2947 | trace_i915_gem_object_change_domain(obj, | |
05394f39 | 2948 | obj->base.read_domains, |
1c5d22f7 | 2949 | old_write_domain); |
e47c68e9 EA |
2950 | } |
2951 | ||
2952 | /** Flushes the CPU write domain for the object if it's dirty. */ | |
2953 | static void | |
05394f39 | 2954 | i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj) |
e47c68e9 | 2955 | { |
1c5d22f7 | 2956 | uint32_t old_write_domain; |
e47c68e9 | 2957 | |
05394f39 | 2958 | if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) |
e47c68e9 EA |
2959 | return; |
2960 | ||
2961 | i915_gem_clflush_object(obj); | |
40ce6575 | 2962 | intel_gtt_chipset_flush(); |
05394f39 CW |
2963 | old_write_domain = obj->base.write_domain; |
2964 | obj->base.write_domain = 0; | |
1c5d22f7 CW |
2965 | |
2966 | trace_i915_gem_object_change_domain(obj, | |
05394f39 | 2967 | obj->base.read_domains, |
1c5d22f7 | 2968 | old_write_domain); |
e47c68e9 EA |
2969 | } |
2970 | ||
2ef7eeaa EA |
2971 | /** |
2972 | * Moves a single object to the GTT read, and possibly write domain. | |
2973 | * | |
2974 | * This function returns when the move is complete, including waiting on | |
2975 | * flushes to occur. | |
2976 | */ | |
79e53945 | 2977 | int |
2021746e | 2978 | i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write) |
2ef7eeaa | 2979 | { |
8325a09d | 2980 | drm_i915_private_t *dev_priv = obj->base.dev->dev_private; |
1c5d22f7 | 2981 | uint32_t old_write_domain, old_read_domains; |
e47c68e9 | 2982 | int ret; |
2ef7eeaa | 2983 | |
02354392 | 2984 | /* Not valid to be called on unbound objects. */ |
05394f39 | 2985 | if (obj->gtt_space == NULL) |
02354392 EA |
2986 | return -EINVAL; |
2987 | ||
8d7e3de1 CW |
2988 | if (obj->base.write_domain == I915_GEM_DOMAIN_GTT) |
2989 | return 0; | |
2990 | ||
0201f1ec CW |
2991 | ret = i915_gem_object_wait_rendering(obj, !write); |
2992 | if (ret) | |
2993 | return ret; | |
2dafb1e0 | 2994 | |
7213342d | 2995 | i915_gem_object_flush_cpu_write_domain(obj); |
1c5d22f7 | 2996 | |
05394f39 CW |
2997 | old_write_domain = obj->base.write_domain; |
2998 | old_read_domains = obj->base.read_domains; | |
1c5d22f7 | 2999 | |
e47c68e9 EA |
3000 | /* It should now be out of any other write domains, and we can update |
3001 | * the domain values for our changes. | |
3002 | */ | |
05394f39 CW |
3003 | BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) != 0); |
3004 | obj->base.read_domains |= I915_GEM_DOMAIN_GTT; | |
e47c68e9 | 3005 | if (write) { |
05394f39 CW |
3006 | obj->base.read_domains = I915_GEM_DOMAIN_GTT; |
3007 | obj->base.write_domain = I915_GEM_DOMAIN_GTT; | |
3008 | obj->dirty = 1; | |
2ef7eeaa EA |
3009 | } |
3010 | ||
1c5d22f7 CW |
3011 | trace_i915_gem_object_change_domain(obj, |
3012 | old_read_domains, | |
3013 | old_write_domain); | |
3014 | ||
8325a09d CW |
3015 | /* And bump the LRU for this access */ |
3016 | if (i915_gem_object_is_inactive(obj)) | |
3017 | list_move_tail(&obj->mm_list, &dev_priv->mm.inactive_list); | |
3018 | ||
e47c68e9 EA |
3019 | return 0; |
3020 | } | |
3021 | ||
e4ffd173 CW |
3022 | int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj, |
3023 | enum i915_cache_level cache_level) | |
3024 | { | |
7bddb01f DV |
3025 | struct drm_device *dev = obj->base.dev; |
3026 | drm_i915_private_t *dev_priv = dev->dev_private; | |
e4ffd173 CW |
3027 | int ret; |
3028 | ||
3029 | if (obj->cache_level == cache_level) | |
3030 | return 0; | |
3031 | ||
3032 | if (obj->pin_count) { | |
3033 | DRM_DEBUG("can not change the cache level of pinned objects\n"); | |
3034 | return -EBUSY; | |
3035 | } | |
3036 | ||
42d6ab48 CW |
3037 | if (!i915_gem_valid_gtt_space(dev, obj->gtt_space, cache_level)) { |
3038 | ret = i915_gem_object_unbind(obj); | |
3039 | if (ret) | |
3040 | return ret; | |
3041 | } | |
3042 | ||
e4ffd173 CW |
3043 | if (obj->gtt_space) { |
3044 | ret = i915_gem_object_finish_gpu(obj); | |
3045 | if (ret) | |
3046 | return ret; | |
3047 | ||
3048 | i915_gem_object_finish_gtt(obj); | |
3049 | ||
3050 | /* Before SandyBridge, you could not use tiling or fence | |
3051 | * registers with snooped memory, so relinquish any fences | |
3052 | * currently pointing to our region in the aperture. | |
3053 | */ | |
42d6ab48 | 3054 | if (INTEL_INFO(dev)->gen < 6) { |
e4ffd173 CW |
3055 | ret = i915_gem_object_put_fence(obj); |
3056 | if (ret) | |
3057 | return ret; | |
3058 | } | |
3059 | ||
74898d7e DV |
3060 | if (obj->has_global_gtt_mapping) |
3061 | i915_gem_gtt_bind_object(obj, cache_level); | |
7bddb01f DV |
3062 | if (obj->has_aliasing_ppgtt_mapping) |
3063 | i915_ppgtt_bind_object(dev_priv->mm.aliasing_ppgtt, | |
3064 | obj, cache_level); | |
42d6ab48 CW |
3065 | |
3066 | obj->gtt_space->color = cache_level; | |
e4ffd173 CW |
3067 | } |
3068 | ||
3069 | if (cache_level == I915_CACHE_NONE) { | |
3070 | u32 old_read_domains, old_write_domain; | |
3071 | ||
3072 | /* If we're coming from LLC cached, then we haven't | |
3073 | * actually been tracking whether the data is in the | |
3074 | * CPU cache or not, since we only allow one bit set | |
3075 | * in obj->write_domain and have been skipping the clflushes. | |
3076 | * Just set it to the CPU cache for now. | |
3077 | */ | |
3078 | WARN_ON(obj->base.write_domain & ~I915_GEM_DOMAIN_CPU); | |
3079 | WARN_ON(obj->base.read_domains & ~I915_GEM_DOMAIN_CPU); | |
3080 | ||
3081 | old_read_domains = obj->base.read_domains; | |
3082 | old_write_domain = obj->base.write_domain; | |
3083 | ||
3084 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; | |
3085 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; | |
3086 | ||
3087 | trace_i915_gem_object_change_domain(obj, | |
3088 | old_read_domains, | |
3089 | old_write_domain); | |
3090 | } | |
3091 | ||
3092 | obj->cache_level = cache_level; | |
42d6ab48 | 3093 | i915_gem_verify_gtt(dev); |
e4ffd173 CW |
3094 | return 0; |
3095 | } | |
3096 | ||
e6994aee CW |
3097 | int i915_gem_get_cacheing_ioctl(struct drm_device *dev, void *data, |
3098 | struct drm_file *file) | |
3099 | { | |
3100 | struct drm_i915_gem_cacheing *args = data; | |
3101 | struct drm_i915_gem_object *obj; | |
3102 | int ret; | |
3103 | ||
3104 | ret = i915_mutex_lock_interruptible(dev); | |
3105 | if (ret) | |
3106 | return ret; | |
3107 | ||
3108 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); | |
3109 | if (&obj->base == NULL) { | |
3110 | ret = -ENOENT; | |
3111 | goto unlock; | |
3112 | } | |
3113 | ||
3114 | args->cacheing = obj->cache_level != I915_CACHE_NONE; | |
3115 | ||
3116 | drm_gem_object_unreference(&obj->base); | |
3117 | unlock: | |
3118 | mutex_unlock(&dev->struct_mutex); | |
3119 | return ret; | |
3120 | } | |
3121 | ||
3122 | int i915_gem_set_cacheing_ioctl(struct drm_device *dev, void *data, | |
3123 | struct drm_file *file) | |
3124 | { | |
3125 | struct drm_i915_gem_cacheing *args = data; | |
3126 | struct drm_i915_gem_object *obj; | |
3127 | enum i915_cache_level level; | |
3128 | int ret; | |
3129 | ||
3130 | ret = i915_mutex_lock_interruptible(dev); | |
3131 | if (ret) | |
3132 | return ret; | |
3133 | ||
3134 | switch (args->cacheing) { | |
3135 | case I915_CACHEING_NONE: | |
3136 | level = I915_CACHE_NONE; | |
3137 | break; | |
3138 | case I915_CACHEING_CACHED: | |
3139 | level = I915_CACHE_LLC; | |
3140 | break; | |
3141 | default: | |
3142 | return -EINVAL; | |
3143 | } | |
3144 | ||
3145 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); | |
3146 | if (&obj->base == NULL) { | |
3147 | ret = -ENOENT; | |
3148 | goto unlock; | |
3149 | } | |
3150 | ||
3151 | ret = i915_gem_object_set_cache_level(obj, level); | |
3152 | ||
3153 | drm_gem_object_unreference(&obj->base); | |
3154 | unlock: | |
3155 | mutex_unlock(&dev->struct_mutex); | |
3156 | return ret; | |
3157 | } | |
3158 | ||
b9241ea3 | 3159 | /* |
2da3b9b9 CW |
3160 | * Prepare buffer for display plane (scanout, cursors, etc). |
3161 | * Can be called from an uninterruptible phase (modesetting) and allows | |
3162 | * any flushes to be pipelined (for pageflips). | |
b9241ea3 ZW |
3163 | */ |
3164 | int | |
2da3b9b9 CW |
3165 | i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj, |
3166 | u32 alignment, | |
919926ae | 3167 | struct intel_ring_buffer *pipelined) |
b9241ea3 | 3168 | { |
2da3b9b9 | 3169 | u32 old_read_domains, old_write_domain; |
b9241ea3 ZW |
3170 | int ret; |
3171 | ||
0be73284 | 3172 | if (pipelined != obj->ring) { |
2911a35b BW |
3173 | ret = i915_gem_object_sync(obj, pipelined); |
3174 | if (ret) | |
b9241ea3 ZW |
3175 | return ret; |
3176 | } | |
3177 | ||
a7ef0640 EA |
3178 | /* The display engine is not coherent with the LLC cache on gen6. As |
3179 | * a result, we make sure that the pinning that is about to occur is | |
3180 | * done with uncached PTEs. This is lowest common denominator for all | |
3181 | * chipsets. | |
3182 | * | |
3183 | * However for gen6+, we could do better by using the GFDT bit instead | |
3184 | * of uncaching, which would allow us to flush all the LLC-cached data | |
3185 | * with that bit in the PTE to main memory with just one PIPE_CONTROL. | |
3186 | */ | |
3187 | ret = i915_gem_object_set_cache_level(obj, I915_CACHE_NONE); | |
3188 | if (ret) | |
3189 | return ret; | |
3190 | ||
2da3b9b9 CW |
3191 | /* As the user may map the buffer once pinned in the display plane |
3192 | * (e.g. libkms for the bootup splash), we have to ensure that we | |
3193 | * always use map_and_fenceable for all scanout buffers. | |
3194 | */ | |
86a1ee26 | 3195 | ret = i915_gem_object_pin(obj, alignment, true, false); |
2da3b9b9 CW |
3196 | if (ret) |
3197 | return ret; | |
3198 | ||
b118c1e3 CW |
3199 | i915_gem_object_flush_cpu_write_domain(obj); |
3200 | ||
2da3b9b9 | 3201 | old_write_domain = obj->base.write_domain; |
05394f39 | 3202 | old_read_domains = obj->base.read_domains; |
2da3b9b9 CW |
3203 | |
3204 | /* It should now be out of any other write domains, and we can update | |
3205 | * the domain values for our changes. | |
3206 | */ | |
e5f1d962 | 3207 | obj->base.write_domain = 0; |
05394f39 | 3208 | obj->base.read_domains |= I915_GEM_DOMAIN_GTT; |
b9241ea3 ZW |
3209 | |
3210 | trace_i915_gem_object_change_domain(obj, | |
3211 | old_read_domains, | |
2da3b9b9 | 3212 | old_write_domain); |
b9241ea3 ZW |
3213 | |
3214 | return 0; | |
3215 | } | |
3216 | ||
85345517 | 3217 | int |
a8198eea | 3218 | i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj) |
85345517 | 3219 | { |
88241785 CW |
3220 | int ret; |
3221 | ||
a8198eea | 3222 | if ((obj->base.read_domains & I915_GEM_GPU_DOMAINS) == 0) |
85345517 CW |
3223 | return 0; |
3224 | ||
0201f1ec | 3225 | ret = i915_gem_object_wait_rendering(obj, false); |
c501ae7f CW |
3226 | if (ret) |
3227 | return ret; | |
3228 | ||
a8198eea CW |
3229 | /* Ensure that we invalidate the GPU's caches and TLBs. */ |
3230 | obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS; | |
c501ae7f | 3231 | return 0; |
85345517 CW |
3232 | } |
3233 | ||
e47c68e9 EA |
3234 | /** |
3235 | * Moves a single object to the CPU read, and possibly write domain. | |
3236 | * | |
3237 | * This function returns when the move is complete, including waiting on | |
3238 | * flushes to occur. | |
3239 | */ | |
dabdfe02 | 3240 | int |
919926ae | 3241 | i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write) |
e47c68e9 | 3242 | { |
1c5d22f7 | 3243 | uint32_t old_write_domain, old_read_domains; |
e47c68e9 EA |
3244 | int ret; |
3245 | ||
8d7e3de1 CW |
3246 | if (obj->base.write_domain == I915_GEM_DOMAIN_CPU) |
3247 | return 0; | |
3248 | ||
0201f1ec CW |
3249 | ret = i915_gem_object_wait_rendering(obj, !write); |
3250 | if (ret) | |
3251 | return ret; | |
2ef7eeaa | 3252 | |
e47c68e9 | 3253 | i915_gem_object_flush_gtt_write_domain(obj); |
2ef7eeaa | 3254 | |
05394f39 CW |
3255 | old_write_domain = obj->base.write_domain; |
3256 | old_read_domains = obj->base.read_domains; | |
1c5d22f7 | 3257 | |
e47c68e9 | 3258 | /* Flush the CPU cache if it's still invalid. */ |
05394f39 | 3259 | if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) { |
2ef7eeaa | 3260 | i915_gem_clflush_object(obj); |
2ef7eeaa | 3261 | |
05394f39 | 3262 | obj->base.read_domains |= I915_GEM_DOMAIN_CPU; |
2ef7eeaa EA |
3263 | } |
3264 | ||
3265 | /* It should now be out of any other write domains, and we can update | |
3266 | * the domain values for our changes. | |
3267 | */ | |
05394f39 | 3268 | BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) != 0); |
e47c68e9 EA |
3269 | |
3270 | /* If we're writing through the CPU, then the GPU read domains will | |
3271 | * need to be invalidated at next use. | |
3272 | */ | |
3273 | if (write) { | |
05394f39 CW |
3274 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; |
3275 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; | |
e47c68e9 | 3276 | } |
2ef7eeaa | 3277 | |
1c5d22f7 CW |
3278 | trace_i915_gem_object_change_domain(obj, |
3279 | old_read_domains, | |
3280 | old_write_domain); | |
3281 | ||
2ef7eeaa EA |
3282 | return 0; |
3283 | } | |
3284 | ||
673a394b EA |
3285 | /* Throttle our rendering by waiting until the ring has completed our requests |
3286 | * emitted over 20 msec ago. | |
3287 | * | |
b962442e EA |
3288 | * Note that if we were to use the current jiffies each time around the loop, |
3289 | * we wouldn't escape the function with any frames outstanding if the time to | |
3290 | * render a frame was over 20ms. | |
3291 | * | |
673a394b EA |
3292 | * This should get us reasonable parallelism between CPU and GPU but also |
3293 | * relatively low latency when blocking on a particular request to finish. | |
3294 | */ | |
40a5f0de | 3295 | static int |
f787a5f5 | 3296 | i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file) |
40a5f0de | 3297 | { |
f787a5f5 CW |
3298 | struct drm_i915_private *dev_priv = dev->dev_private; |
3299 | struct drm_i915_file_private *file_priv = file->driver_priv; | |
b962442e | 3300 | unsigned long recent_enough = jiffies - msecs_to_jiffies(20); |
f787a5f5 CW |
3301 | struct drm_i915_gem_request *request; |
3302 | struct intel_ring_buffer *ring = NULL; | |
3303 | u32 seqno = 0; | |
3304 | int ret; | |
93533c29 | 3305 | |
e110e8d6 CW |
3306 | if (atomic_read(&dev_priv->mm.wedged)) |
3307 | return -EIO; | |
3308 | ||
1c25595f | 3309 | spin_lock(&file_priv->mm.lock); |
f787a5f5 | 3310 | list_for_each_entry(request, &file_priv->mm.request_list, client_list) { |
b962442e EA |
3311 | if (time_after_eq(request->emitted_jiffies, recent_enough)) |
3312 | break; | |
40a5f0de | 3313 | |
f787a5f5 CW |
3314 | ring = request->ring; |
3315 | seqno = request->seqno; | |
b962442e | 3316 | } |
1c25595f | 3317 | spin_unlock(&file_priv->mm.lock); |
40a5f0de | 3318 | |
f787a5f5 CW |
3319 | if (seqno == 0) |
3320 | return 0; | |
2bc43b5c | 3321 | |
5c81fe85 | 3322 | ret = __wait_seqno(ring, seqno, true, NULL); |
f787a5f5 CW |
3323 | if (ret == 0) |
3324 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, 0); | |
40a5f0de EA |
3325 | |
3326 | return ret; | |
3327 | } | |
3328 | ||
673a394b | 3329 | int |
05394f39 CW |
3330 | i915_gem_object_pin(struct drm_i915_gem_object *obj, |
3331 | uint32_t alignment, | |
86a1ee26 CW |
3332 | bool map_and_fenceable, |
3333 | bool nonblocking) | |
673a394b | 3334 | { |
673a394b EA |
3335 | int ret; |
3336 | ||
05394f39 | 3337 | BUG_ON(obj->pin_count == DRM_I915_GEM_OBJECT_MAX_PIN_COUNT); |
ac0c6b5a | 3338 | |
05394f39 CW |
3339 | if (obj->gtt_space != NULL) { |
3340 | if ((alignment && obj->gtt_offset & (alignment - 1)) || | |
3341 | (map_and_fenceable && !obj->map_and_fenceable)) { | |
3342 | WARN(obj->pin_count, | |
ae7d49d8 | 3343 | "bo is already pinned with incorrect alignment:" |
75e9e915 DV |
3344 | " offset=%x, req.alignment=%x, req.map_and_fenceable=%d," |
3345 | " obj->map_and_fenceable=%d\n", | |
05394f39 | 3346 | obj->gtt_offset, alignment, |
75e9e915 | 3347 | map_and_fenceable, |
05394f39 | 3348 | obj->map_and_fenceable); |
ac0c6b5a CW |
3349 | ret = i915_gem_object_unbind(obj); |
3350 | if (ret) | |
3351 | return ret; | |
3352 | } | |
3353 | } | |
3354 | ||
05394f39 | 3355 | if (obj->gtt_space == NULL) { |
a00b10c3 | 3356 | ret = i915_gem_object_bind_to_gtt(obj, alignment, |
86a1ee26 CW |
3357 | map_and_fenceable, |
3358 | nonblocking); | |
9731129c | 3359 | if (ret) |
673a394b | 3360 | return ret; |
22c344e9 | 3361 | } |
76446cac | 3362 | |
74898d7e DV |
3363 | if (!obj->has_global_gtt_mapping && map_and_fenceable) |
3364 | i915_gem_gtt_bind_object(obj, obj->cache_level); | |
3365 | ||
1b50247a | 3366 | obj->pin_count++; |
6299f992 | 3367 | obj->pin_mappable |= map_and_fenceable; |
673a394b EA |
3368 | |
3369 | return 0; | |
3370 | } | |
3371 | ||
3372 | void | |
05394f39 | 3373 | i915_gem_object_unpin(struct drm_i915_gem_object *obj) |
673a394b | 3374 | { |
05394f39 CW |
3375 | BUG_ON(obj->pin_count == 0); |
3376 | BUG_ON(obj->gtt_space == NULL); | |
673a394b | 3377 | |
1b50247a | 3378 | if (--obj->pin_count == 0) |
6299f992 | 3379 | obj->pin_mappable = false; |
673a394b EA |
3380 | } |
3381 | ||
3382 | int | |
3383 | i915_gem_pin_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 3384 | struct drm_file *file) |
673a394b EA |
3385 | { |
3386 | struct drm_i915_gem_pin *args = data; | |
05394f39 | 3387 | struct drm_i915_gem_object *obj; |
673a394b EA |
3388 | int ret; |
3389 | ||
1d7cfea1 CW |
3390 | ret = i915_mutex_lock_interruptible(dev); |
3391 | if (ret) | |
3392 | return ret; | |
673a394b | 3393 | |
05394f39 | 3394 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 3395 | if (&obj->base == NULL) { |
1d7cfea1 CW |
3396 | ret = -ENOENT; |
3397 | goto unlock; | |
673a394b | 3398 | } |
673a394b | 3399 | |
05394f39 | 3400 | if (obj->madv != I915_MADV_WILLNEED) { |
bb6baf76 | 3401 | DRM_ERROR("Attempting to pin a purgeable buffer\n"); |
1d7cfea1 CW |
3402 | ret = -EINVAL; |
3403 | goto out; | |
3ef94daa CW |
3404 | } |
3405 | ||
05394f39 | 3406 | if (obj->pin_filp != NULL && obj->pin_filp != file) { |
79e53945 JB |
3407 | DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n", |
3408 | args->handle); | |
1d7cfea1 CW |
3409 | ret = -EINVAL; |
3410 | goto out; | |
79e53945 JB |
3411 | } |
3412 | ||
05394f39 CW |
3413 | obj->user_pin_count++; |
3414 | obj->pin_filp = file; | |
3415 | if (obj->user_pin_count == 1) { | |
86a1ee26 | 3416 | ret = i915_gem_object_pin(obj, args->alignment, true, false); |
1d7cfea1 CW |
3417 | if (ret) |
3418 | goto out; | |
673a394b EA |
3419 | } |
3420 | ||
3421 | /* XXX - flush the CPU caches for pinned objects | |
3422 | * as the X server doesn't manage domains yet | |
3423 | */ | |
e47c68e9 | 3424 | i915_gem_object_flush_cpu_write_domain(obj); |
05394f39 | 3425 | args->offset = obj->gtt_offset; |
1d7cfea1 | 3426 | out: |
05394f39 | 3427 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 3428 | unlock: |
673a394b | 3429 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 3430 | return ret; |
673a394b EA |
3431 | } |
3432 | ||
3433 | int | |
3434 | i915_gem_unpin_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 3435 | struct drm_file *file) |
673a394b EA |
3436 | { |
3437 | struct drm_i915_gem_pin *args = data; | |
05394f39 | 3438 | struct drm_i915_gem_object *obj; |
76c1dec1 | 3439 | int ret; |
673a394b | 3440 | |
1d7cfea1 CW |
3441 | ret = i915_mutex_lock_interruptible(dev); |
3442 | if (ret) | |
3443 | return ret; | |
673a394b | 3444 | |
05394f39 | 3445 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 3446 | if (&obj->base == NULL) { |
1d7cfea1 CW |
3447 | ret = -ENOENT; |
3448 | goto unlock; | |
673a394b | 3449 | } |
76c1dec1 | 3450 | |
05394f39 | 3451 | if (obj->pin_filp != file) { |
79e53945 JB |
3452 | DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n", |
3453 | args->handle); | |
1d7cfea1 CW |
3454 | ret = -EINVAL; |
3455 | goto out; | |
79e53945 | 3456 | } |
05394f39 CW |
3457 | obj->user_pin_count--; |
3458 | if (obj->user_pin_count == 0) { | |
3459 | obj->pin_filp = NULL; | |
79e53945 JB |
3460 | i915_gem_object_unpin(obj); |
3461 | } | |
673a394b | 3462 | |
1d7cfea1 | 3463 | out: |
05394f39 | 3464 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 3465 | unlock: |
673a394b | 3466 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 3467 | return ret; |
673a394b EA |
3468 | } |
3469 | ||
3470 | int | |
3471 | i915_gem_busy_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 3472 | struct drm_file *file) |
673a394b EA |
3473 | { |
3474 | struct drm_i915_gem_busy *args = data; | |
05394f39 | 3475 | struct drm_i915_gem_object *obj; |
30dbf0c0 CW |
3476 | int ret; |
3477 | ||
76c1dec1 | 3478 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 3479 | if (ret) |
76c1dec1 | 3480 | return ret; |
673a394b | 3481 | |
05394f39 | 3482 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 3483 | if (&obj->base == NULL) { |
1d7cfea1 CW |
3484 | ret = -ENOENT; |
3485 | goto unlock; | |
673a394b | 3486 | } |
d1b851fc | 3487 | |
0be555b6 CW |
3488 | /* Count all active objects as busy, even if they are currently not used |
3489 | * by the gpu. Users of this interface expect objects to eventually | |
3490 | * become non-busy without any further actions, therefore emit any | |
3491 | * necessary flushes here. | |
c4de0a5d | 3492 | */ |
30dfebf3 | 3493 | ret = i915_gem_object_flush_active(obj); |
0be555b6 | 3494 | |
30dfebf3 | 3495 | args->busy = obj->active; |
e9808edd CW |
3496 | if (obj->ring) { |
3497 | BUILD_BUG_ON(I915_NUM_RINGS > 16); | |
3498 | args->busy |= intel_ring_flag(obj->ring) << 16; | |
3499 | } | |
673a394b | 3500 | |
05394f39 | 3501 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 3502 | unlock: |
673a394b | 3503 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 3504 | return ret; |
673a394b EA |
3505 | } |
3506 | ||
3507 | int | |
3508 | i915_gem_throttle_ioctl(struct drm_device *dev, void *data, | |
3509 | struct drm_file *file_priv) | |
3510 | { | |
0206e353 | 3511 | return i915_gem_ring_throttle(dev, file_priv); |
673a394b EA |
3512 | } |
3513 | ||
3ef94daa CW |
3514 | int |
3515 | i915_gem_madvise_ioctl(struct drm_device *dev, void *data, | |
3516 | struct drm_file *file_priv) | |
3517 | { | |
3518 | struct drm_i915_gem_madvise *args = data; | |
05394f39 | 3519 | struct drm_i915_gem_object *obj; |
76c1dec1 | 3520 | int ret; |
3ef94daa CW |
3521 | |
3522 | switch (args->madv) { | |
3523 | case I915_MADV_DONTNEED: | |
3524 | case I915_MADV_WILLNEED: | |
3525 | break; | |
3526 | default: | |
3527 | return -EINVAL; | |
3528 | } | |
3529 | ||
1d7cfea1 CW |
3530 | ret = i915_mutex_lock_interruptible(dev); |
3531 | if (ret) | |
3532 | return ret; | |
3533 | ||
05394f39 | 3534 | obj = to_intel_bo(drm_gem_object_lookup(dev, file_priv, args->handle)); |
c8725226 | 3535 | if (&obj->base == NULL) { |
1d7cfea1 CW |
3536 | ret = -ENOENT; |
3537 | goto unlock; | |
3ef94daa | 3538 | } |
3ef94daa | 3539 | |
05394f39 | 3540 | if (obj->pin_count) { |
1d7cfea1 CW |
3541 | ret = -EINVAL; |
3542 | goto out; | |
3ef94daa CW |
3543 | } |
3544 | ||
05394f39 CW |
3545 | if (obj->madv != __I915_MADV_PURGED) |
3546 | obj->madv = args->madv; | |
3ef94daa | 3547 | |
6c085a72 CW |
3548 | /* if the object is no longer attached, discard its backing storage */ |
3549 | if (i915_gem_object_is_purgeable(obj) && obj->pages == NULL) | |
2d7ef395 CW |
3550 | i915_gem_object_truncate(obj); |
3551 | ||
05394f39 | 3552 | args->retained = obj->madv != __I915_MADV_PURGED; |
bb6baf76 | 3553 | |
1d7cfea1 | 3554 | out: |
05394f39 | 3555 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 3556 | unlock: |
3ef94daa | 3557 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 3558 | return ret; |
3ef94daa CW |
3559 | } |
3560 | ||
05394f39 CW |
3561 | struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev, |
3562 | size_t size) | |
ac52bc56 | 3563 | { |
73aa808f | 3564 | struct drm_i915_private *dev_priv = dev->dev_private; |
c397b908 | 3565 | struct drm_i915_gem_object *obj; |
5949eac4 | 3566 | struct address_space *mapping; |
bed1ea95 | 3567 | u32 mask; |
ac52bc56 | 3568 | |
c397b908 DV |
3569 | obj = kzalloc(sizeof(*obj), GFP_KERNEL); |
3570 | if (obj == NULL) | |
3571 | return NULL; | |
673a394b | 3572 | |
c397b908 DV |
3573 | if (drm_gem_object_init(dev, &obj->base, size) != 0) { |
3574 | kfree(obj); | |
3575 | return NULL; | |
3576 | } | |
673a394b | 3577 | |
bed1ea95 CW |
3578 | mask = GFP_HIGHUSER | __GFP_RECLAIMABLE; |
3579 | if (IS_CRESTLINE(dev) || IS_BROADWATER(dev)) { | |
3580 | /* 965gm cannot relocate objects above 4GiB. */ | |
3581 | mask &= ~__GFP_HIGHMEM; | |
3582 | mask |= __GFP_DMA32; | |
3583 | } | |
3584 | ||
5949eac4 | 3585 | mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping; |
bed1ea95 | 3586 | mapping_set_gfp_mask(mapping, mask); |
5949eac4 | 3587 | |
73aa808f CW |
3588 | i915_gem_info_add_obj(dev_priv, size); |
3589 | ||
c397b908 DV |
3590 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; |
3591 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; | |
673a394b | 3592 | |
3d29b842 ED |
3593 | if (HAS_LLC(dev)) { |
3594 | /* On some devices, we can have the GPU use the LLC (the CPU | |
a1871112 EA |
3595 | * cache) for about a 10% performance improvement |
3596 | * compared to uncached. Graphics requests other than | |
3597 | * display scanout are coherent with the CPU in | |
3598 | * accessing this cache. This means in this mode we | |
3599 | * don't need to clflush on the CPU side, and on the | |
3600 | * GPU side we only need to flush internal caches to | |
3601 | * get data visible to the CPU. | |
3602 | * | |
3603 | * However, we maintain the display planes as UC, and so | |
3604 | * need to rebind when first used as such. | |
3605 | */ | |
3606 | obj->cache_level = I915_CACHE_LLC; | |
3607 | } else | |
3608 | obj->cache_level = I915_CACHE_NONE; | |
3609 | ||
62b8b215 | 3610 | obj->base.driver_private = NULL; |
c397b908 | 3611 | obj->fence_reg = I915_FENCE_REG_NONE; |
69dc4987 | 3612 | INIT_LIST_HEAD(&obj->mm_list); |
93a37f20 | 3613 | INIT_LIST_HEAD(&obj->gtt_list); |
69dc4987 | 3614 | INIT_LIST_HEAD(&obj->ring_list); |
432e58ed | 3615 | INIT_LIST_HEAD(&obj->exec_list); |
c397b908 | 3616 | obj->madv = I915_MADV_WILLNEED; |
75e9e915 DV |
3617 | /* Avoid an unnecessary call to unbind on the first bind. */ |
3618 | obj->map_and_fenceable = true; | |
de151cf6 | 3619 | |
05394f39 | 3620 | return obj; |
c397b908 DV |
3621 | } |
3622 | ||
3623 | int i915_gem_init_object(struct drm_gem_object *obj) | |
3624 | { | |
3625 | BUG(); | |
de151cf6 | 3626 | |
673a394b EA |
3627 | return 0; |
3628 | } | |
3629 | ||
1488fc08 | 3630 | void i915_gem_free_object(struct drm_gem_object *gem_obj) |
673a394b | 3631 | { |
1488fc08 | 3632 | struct drm_i915_gem_object *obj = to_intel_bo(gem_obj); |
05394f39 | 3633 | struct drm_device *dev = obj->base.dev; |
be72615b | 3634 | drm_i915_private_t *dev_priv = dev->dev_private; |
673a394b | 3635 | |
26e12f89 CW |
3636 | trace_i915_gem_object_destroy(obj); |
3637 | ||
1286ff73 DV |
3638 | if (gem_obj->import_attach) |
3639 | drm_prime_gem_destroy(gem_obj, obj->sg_table); | |
3640 | ||
1488fc08 CW |
3641 | if (obj->phys_obj) |
3642 | i915_gem_detach_phys_object(dev, obj); | |
3643 | ||
3644 | obj->pin_count = 0; | |
3645 | if (WARN_ON(i915_gem_object_unbind(obj) == -ERESTARTSYS)) { | |
3646 | bool was_interruptible; | |
3647 | ||
3648 | was_interruptible = dev_priv->mm.interruptible; | |
3649 | dev_priv->mm.interruptible = false; | |
3650 | ||
3651 | WARN_ON(i915_gem_object_unbind(obj)); | |
3652 | ||
3653 | dev_priv->mm.interruptible = was_interruptible; | |
3654 | } | |
3655 | ||
6c085a72 | 3656 | i915_gem_object_put_pages_gtt(obj); |
d8cb5086 | 3657 | i915_gem_object_free_mmap_offset(obj); |
de151cf6 | 3658 | |
05394f39 CW |
3659 | drm_gem_object_release(&obj->base); |
3660 | i915_gem_info_remove_obj(dev_priv, obj->base.size); | |
c397b908 | 3661 | |
05394f39 CW |
3662 | kfree(obj->bit_17); |
3663 | kfree(obj); | |
673a394b EA |
3664 | } |
3665 | ||
29105ccc CW |
3666 | int |
3667 | i915_gem_idle(struct drm_device *dev) | |
3668 | { | |
3669 | drm_i915_private_t *dev_priv = dev->dev_private; | |
3670 | int ret; | |
28dfe52a | 3671 | |
29105ccc | 3672 | mutex_lock(&dev->struct_mutex); |
1c5d22f7 | 3673 | |
87acb0a5 | 3674 | if (dev_priv->mm.suspended) { |
29105ccc CW |
3675 | mutex_unlock(&dev->struct_mutex); |
3676 | return 0; | |
28dfe52a EA |
3677 | } |
3678 | ||
b2da9fe5 | 3679 | ret = i915_gpu_idle(dev); |
6dbe2772 KP |
3680 | if (ret) { |
3681 | mutex_unlock(&dev->struct_mutex); | |
673a394b | 3682 | return ret; |
6dbe2772 | 3683 | } |
b2da9fe5 | 3684 | i915_gem_retire_requests(dev); |
673a394b | 3685 | |
29105ccc | 3686 | /* Under UMS, be paranoid and evict. */ |
a39d7efc | 3687 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) |
6c085a72 | 3688 | i915_gem_evict_everything(dev); |
29105ccc | 3689 | |
312817a3 CW |
3690 | i915_gem_reset_fences(dev); |
3691 | ||
29105ccc CW |
3692 | /* Hack! Don't let anybody do execbuf while we don't control the chip. |
3693 | * We need to replace this with a semaphore, or something. | |
3694 | * And not confound mm.suspended! | |
3695 | */ | |
3696 | dev_priv->mm.suspended = 1; | |
bc0c7f14 | 3697 | del_timer_sync(&dev_priv->hangcheck_timer); |
29105ccc CW |
3698 | |
3699 | i915_kernel_lost_context(dev); | |
6dbe2772 | 3700 | i915_gem_cleanup_ringbuffer(dev); |
29105ccc | 3701 | |
6dbe2772 KP |
3702 | mutex_unlock(&dev->struct_mutex); |
3703 | ||
29105ccc CW |
3704 | /* Cancel the retire work handler, which should be idle now. */ |
3705 | cancel_delayed_work_sync(&dev_priv->mm.retire_work); | |
3706 | ||
673a394b EA |
3707 | return 0; |
3708 | } | |
3709 | ||
b9524a1e BW |
3710 | void i915_gem_l3_remap(struct drm_device *dev) |
3711 | { | |
3712 | drm_i915_private_t *dev_priv = dev->dev_private; | |
3713 | u32 misccpctl; | |
3714 | int i; | |
3715 | ||
3716 | if (!IS_IVYBRIDGE(dev)) | |
3717 | return; | |
3718 | ||
3719 | if (!dev_priv->mm.l3_remap_info) | |
3720 | return; | |
3721 | ||
3722 | misccpctl = I915_READ(GEN7_MISCCPCTL); | |
3723 | I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE); | |
3724 | POSTING_READ(GEN7_MISCCPCTL); | |
3725 | ||
3726 | for (i = 0; i < GEN7_L3LOG_SIZE; i += 4) { | |
3727 | u32 remap = I915_READ(GEN7_L3LOG_BASE + i); | |
3728 | if (remap && remap != dev_priv->mm.l3_remap_info[i/4]) | |
3729 | DRM_DEBUG("0x%x was already programmed to %x\n", | |
3730 | GEN7_L3LOG_BASE + i, remap); | |
3731 | if (remap && !dev_priv->mm.l3_remap_info[i/4]) | |
3732 | DRM_DEBUG_DRIVER("Clearing remapped register\n"); | |
3733 | I915_WRITE(GEN7_L3LOG_BASE + i, dev_priv->mm.l3_remap_info[i/4]); | |
3734 | } | |
3735 | ||
3736 | /* Make sure all the writes land before disabling dop clock gating */ | |
3737 | POSTING_READ(GEN7_L3LOG_BASE); | |
3738 | ||
3739 | I915_WRITE(GEN7_MISCCPCTL, misccpctl); | |
3740 | } | |
3741 | ||
f691e2f4 DV |
3742 | void i915_gem_init_swizzling(struct drm_device *dev) |
3743 | { | |
3744 | drm_i915_private_t *dev_priv = dev->dev_private; | |
3745 | ||
11782b02 | 3746 | if (INTEL_INFO(dev)->gen < 5 || |
f691e2f4 DV |
3747 | dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE) |
3748 | return; | |
3749 | ||
3750 | I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) | | |
3751 | DISP_TILE_SURFACE_SWIZZLING); | |
3752 | ||
11782b02 DV |
3753 | if (IS_GEN5(dev)) |
3754 | return; | |
3755 | ||
f691e2f4 DV |
3756 | I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_SWZCTL); |
3757 | if (IS_GEN6(dev)) | |
6b26c86d | 3758 | I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB)); |
f691e2f4 | 3759 | else |
6b26c86d | 3760 | I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB)); |
f691e2f4 | 3761 | } |
e21af88d DV |
3762 | |
3763 | void i915_gem_init_ppgtt(struct drm_device *dev) | |
3764 | { | |
3765 | drm_i915_private_t *dev_priv = dev->dev_private; | |
3766 | uint32_t pd_offset; | |
3767 | struct intel_ring_buffer *ring; | |
55a254ac DV |
3768 | struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt; |
3769 | uint32_t __iomem *pd_addr; | |
3770 | uint32_t pd_entry; | |
e21af88d DV |
3771 | int i; |
3772 | ||
3773 | if (!dev_priv->mm.aliasing_ppgtt) | |
3774 | return; | |
3775 | ||
55a254ac DV |
3776 | |
3777 | pd_addr = dev_priv->mm.gtt->gtt + ppgtt->pd_offset/sizeof(uint32_t); | |
3778 | for (i = 0; i < ppgtt->num_pd_entries; i++) { | |
3779 | dma_addr_t pt_addr; | |
3780 | ||
3781 | if (dev_priv->mm.gtt->needs_dmar) | |
3782 | pt_addr = ppgtt->pt_dma_addr[i]; | |
3783 | else | |
3784 | pt_addr = page_to_phys(ppgtt->pt_pages[i]); | |
3785 | ||
3786 | pd_entry = GEN6_PDE_ADDR_ENCODE(pt_addr); | |
3787 | pd_entry |= GEN6_PDE_VALID; | |
3788 | ||
3789 | writel(pd_entry, pd_addr + i); | |
3790 | } | |
3791 | readl(pd_addr); | |
3792 | ||
3793 | pd_offset = ppgtt->pd_offset; | |
e21af88d DV |
3794 | pd_offset /= 64; /* in cachelines, */ |
3795 | pd_offset <<= 16; | |
3796 | ||
3797 | if (INTEL_INFO(dev)->gen == 6) { | |
48ecfa10 DV |
3798 | uint32_t ecochk, gab_ctl, ecobits; |
3799 | ||
3800 | ecobits = I915_READ(GAC_ECO_BITS); | |
3801 | I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_PPGTT_CACHE64B); | |
be901a5a DV |
3802 | |
3803 | gab_ctl = I915_READ(GAB_CTL); | |
3804 | I915_WRITE(GAB_CTL, gab_ctl | GAB_CTL_CONT_AFTER_PAGEFAULT); | |
3805 | ||
3806 | ecochk = I915_READ(GAM_ECOCHK); | |
e21af88d DV |
3807 | I915_WRITE(GAM_ECOCHK, ecochk | ECOCHK_SNB_BIT | |
3808 | ECOCHK_PPGTT_CACHE64B); | |
6b26c86d | 3809 | I915_WRITE(GFX_MODE, _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE)); |
e21af88d DV |
3810 | } else if (INTEL_INFO(dev)->gen >= 7) { |
3811 | I915_WRITE(GAM_ECOCHK, ECOCHK_PPGTT_CACHE64B); | |
3812 | /* GFX_MODE is per-ring on gen7+ */ | |
3813 | } | |
3814 | ||
b4519513 | 3815 | for_each_ring(ring, dev_priv, i) { |
e21af88d DV |
3816 | if (INTEL_INFO(dev)->gen >= 7) |
3817 | I915_WRITE(RING_MODE_GEN7(ring), | |
6b26c86d | 3818 | _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE)); |
e21af88d DV |
3819 | |
3820 | I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G); | |
3821 | I915_WRITE(RING_PP_DIR_BASE(ring), pd_offset); | |
3822 | } | |
3823 | } | |
3824 | ||
67b1b571 CW |
3825 | static bool |
3826 | intel_enable_blt(struct drm_device *dev) | |
3827 | { | |
3828 | if (!HAS_BLT(dev)) | |
3829 | return false; | |
3830 | ||
3831 | /* The blitter was dysfunctional on early prototypes */ | |
3832 | if (IS_GEN6(dev) && dev->pdev->revision < 8) { | |
3833 | DRM_INFO("BLT not supported on this pre-production hardware;" | |
3834 | " graphics performance will be degraded.\n"); | |
3835 | return false; | |
3836 | } | |
3837 | ||
3838 | return true; | |
3839 | } | |
3840 | ||
8187a2b7 | 3841 | int |
f691e2f4 | 3842 | i915_gem_init_hw(struct drm_device *dev) |
8187a2b7 ZN |
3843 | { |
3844 | drm_i915_private_t *dev_priv = dev->dev_private; | |
3845 | int ret; | |
68f95ba9 | 3846 | |
8ecd1a66 DV |
3847 | if (!intel_enable_gtt()) |
3848 | return -EIO; | |
3849 | ||
b9524a1e BW |
3850 | i915_gem_l3_remap(dev); |
3851 | ||
f691e2f4 DV |
3852 | i915_gem_init_swizzling(dev); |
3853 | ||
5c1143bb | 3854 | ret = intel_init_render_ring_buffer(dev); |
68f95ba9 | 3855 | if (ret) |
b6913e4b | 3856 | return ret; |
68f95ba9 CW |
3857 | |
3858 | if (HAS_BSD(dev)) { | |
5c1143bb | 3859 | ret = intel_init_bsd_ring_buffer(dev); |
68f95ba9 CW |
3860 | if (ret) |
3861 | goto cleanup_render_ring; | |
d1b851fc | 3862 | } |
68f95ba9 | 3863 | |
67b1b571 | 3864 | if (intel_enable_blt(dev)) { |
549f7365 CW |
3865 | ret = intel_init_blt_ring_buffer(dev); |
3866 | if (ret) | |
3867 | goto cleanup_bsd_ring; | |
3868 | } | |
3869 | ||
6f392d54 CW |
3870 | dev_priv->next_seqno = 1; |
3871 | ||
254f965c BW |
3872 | /* |
3873 | * XXX: There was some w/a described somewhere suggesting loading | |
3874 | * contexts before PPGTT. | |
3875 | */ | |
3876 | i915_gem_context_init(dev); | |
e21af88d DV |
3877 | i915_gem_init_ppgtt(dev); |
3878 | ||
68f95ba9 CW |
3879 | return 0; |
3880 | ||
549f7365 | 3881 | cleanup_bsd_ring: |
1ec14ad3 | 3882 | intel_cleanup_ring_buffer(&dev_priv->ring[VCS]); |
68f95ba9 | 3883 | cleanup_render_ring: |
1ec14ad3 | 3884 | intel_cleanup_ring_buffer(&dev_priv->ring[RCS]); |
8187a2b7 ZN |
3885 | return ret; |
3886 | } | |
3887 | ||
1070a42b CW |
3888 | static bool |
3889 | intel_enable_ppgtt(struct drm_device *dev) | |
3890 | { | |
3891 | if (i915_enable_ppgtt >= 0) | |
3892 | return i915_enable_ppgtt; | |
3893 | ||
3894 | #ifdef CONFIG_INTEL_IOMMU | |
3895 | /* Disable ppgtt on SNB if VT-d is on. */ | |
3896 | if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped) | |
3897 | return false; | |
3898 | #endif | |
3899 | ||
3900 | return true; | |
3901 | } | |
3902 | ||
3903 | int i915_gem_init(struct drm_device *dev) | |
3904 | { | |
3905 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3906 | unsigned long gtt_size, mappable_size; | |
3907 | int ret; | |
3908 | ||
3909 | gtt_size = dev_priv->mm.gtt->gtt_total_entries << PAGE_SHIFT; | |
3910 | mappable_size = dev_priv->mm.gtt->gtt_mappable_entries << PAGE_SHIFT; | |
3911 | ||
3912 | mutex_lock(&dev->struct_mutex); | |
3913 | if (intel_enable_ppgtt(dev) && HAS_ALIASING_PPGTT(dev)) { | |
3914 | /* PPGTT pdes are stolen from global gtt ptes, so shrink the | |
3915 | * aperture accordingly when using aliasing ppgtt. */ | |
3916 | gtt_size -= I915_PPGTT_PD_ENTRIES*PAGE_SIZE; | |
3917 | ||
3918 | i915_gem_init_global_gtt(dev, 0, mappable_size, gtt_size); | |
3919 | ||
3920 | ret = i915_gem_init_aliasing_ppgtt(dev); | |
3921 | if (ret) { | |
3922 | mutex_unlock(&dev->struct_mutex); | |
3923 | return ret; | |
3924 | } | |
3925 | } else { | |
3926 | /* Let GEM Manage all of the aperture. | |
3927 | * | |
3928 | * However, leave one page at the end still bound to the scratch | |
3929 | * page. There are a number of places where the hardware | |
3930 | * apparently prefetches past the end of the object, and we've | |
3931 | * seen multiple hangs with the GPU head pointer stuck in a | |
3932 | * batchbuffer bound at the last page of the aperture. One page | |
3933 | * should be enough to keep any prefetching inside of the | |
3934 | * aperture. | |
3935 | */ | |
3936 | i915_gem_init_global_gtt(dev, 0, mappable_size, | |
3937 | gtt_size); | |
3938 | } | |
3939 | ||
3940 | ret = i915_gem_init_hw(dev); | |
3941 | mutex_unlock(&dev->struct_mutex); | |
3942 | if (ret) { | |
3943 | i915_gem_cleanup_aliasing_ppgtt(dev); | |
3944 | return ret; | |
3945 | } | |
3946 | ||
53ca26ca DV |
3947 | /* Allow hardware batchbuffers unless told otherwise, but not for KMS. */ |
3948 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) | |
3949 | dev_priv->dri1.allow_batchbuffer = 1; | |
1070a42b CW |
3950 | return 0; |
3951 | } | |
3952 | ||
8187a2b7 ZN |
3953 | void |
3954 | i915_gem_cleanup_ringbuffer(struct drm_device *dev) | |
3955 | { | |
3956 | drm_i915_private_t *dev_priv = dev->dev_private; | |
b4519513 | 3957 | struct intel_ring_buffer *ring; |
1ec14ad3 | 3958 | int i; |
8187a2b7 | 3959 | |
b4519513 CW |
3960 | for_each_ring(ring, dev_priv, i) |
3961 | intel_cleanup_ring_buffer(ring); | |
8187a2b7 ZN |
3962 | } |
3963 | ||
673a394b EA |
3964 | int |
3965 | i915_gem_entervt_ioctl(struct drm_device *dev, void *data, | |
3966 | struct drm_file *file_priv) | |
3967 | { | |
3968 | drm_i915_private_t *dev_priv = dev->dev_private; | |
b4519513 | 3969 | int ret; |
673a394b | 3970 | |
79e53945 JB |
3971 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
3972 | return 0; | |
3973 | ||
ba1234d1 | 3974 | if (atomic_read(&dev_priv->mm.wedged)) { |
673a394b | 3975 | DRM_ERROR("Reenabling wedged hardware, good luck\n"); |
ba1234d1 | 3976 | atomic_set(&dev_priv->mm.wedged, 0); |
673a394b EA |
3977 | } |
3978 | ||
673a394b | 3979 | mutex_lock(&dev->struct_mutex); |
9bb2d6f9 EA |
3980 | dev_priv->mm.suspended = 0; |
3981 | ||
f691e2f4 | 3982 | ret = i915_gem_init_hw(dev); |
d816f6ac WF |
3983 | if (ret != 0) { |
3984 | mutex_unlock(&dev->struct_mutex); | |
9bb2d6f9 | 3985 | return ret; |
d816f6ac | 3986 | } |
9bb2d6f9 | 3987 | |
69dc4987 | 3988 | BUG_ON(!list_empty(&dev_priv->mm.active_list)); |
673a394b | 3989 | BUG_ON(!list_empty(&dev_priv->mm.inactive_list)); |
673a394b | 3990 | mutex_unlock(&dev->struct_mutex); |
dbb19d30 | 3991 | |
5f35308b CW |
3992 | ret = drm_irq_install(dev); |
3993 | if (ret) | |
3994 | goto cleanup_ringbuffer; | |
dbb19d30 | 3995 | |
673a394b | 3996 | return 0; |
5f35308b CW |
3997 | |
3998 | cleanup_ringbuffer: | |
3999 | mutex_lock(&dev->struct_mutex); | |
4000 | i915_gem_cleanup_ringbuffer(dev); | |
4001 | dev_priv->mm.suspended = 1; | |
4002 | mutex_unlock(&dev->struct_mutex); | |
4003 | ||
4004 | return ret; | |
673a394b EA |
4005 | } |
4006 | ||
4007 | int | |
4008 | i915_gem_leavevt_ioctl(struct drm_device *dev, void *data, | |
4009 | struct drm_file *file_priv) | |
4010 | { | |
79e53945 JB |
4011 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
4012 | return 0; | |
4013 | ||
dbb19d30 | 4014 | drm_irq_uninstall(dev); |
e6890f6f | 4015 | return i915_gem_idle(dev); |
673a394b EA |
4016 | } |
4017 | ||
4018 | void | |
4019 | i915_gem_lastclose(struct drm_device *dev) | |
4020 | { | |
4021 | int ret; | |
673a394b | 4022 | |
e806b495 EA |
4023 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
4024 | return; | |
4025 | ||
6dbe2772 KP |
4026 | ret = i915_gem_idle(dev); |
4027 | if (ret) | |
4028 | DRM_ERROR("failed to idle hardware: %d\n", ret); | |
673a394b EA |
4029 | } |
4030 | ||
64193406 CW |
4031 | static void |
4032 | init_ring_lists(struct intel_ring_buffer *ring) | |
4033 | { | |
4034 | INIT_LIST_HEAD(&ring->active_list); | |
4035 | INIT_LIST_HEAD(&ring->request_list); | |
64193406 CW |
4036 | } |
4037 | ||
673a394b EA |
4038 | void |
4039 | i915_gem_load(struct drm_device *dev) | |
4040 | { | |
b5aa8a0f | 4041 | int i; |
673a394b EA |
4042 | drm_i915_private_t *dev_priv = dev->dev_private; |
4043 | ||
69dc4987 | 4044 | INIT_LIST_HEAD(&dev_priv->mm.active_list); |
673a394b | 4045 | INIT_LIST_HEAD(&dev_priv->mm.inactive_list); |
6c085a72 CW |
4046 | INIT_LIST_HEAD(&dev_priv->mm.unbound_list); |
4047 | INIT_LIST_HEAD(&dev_priv->mm.bound_list); | |
a09ba7fa | 4048 | INIT_LIST_HEAD(&dev_priv->mm.fence_list); |
1ec14ad3 CW |
4049 | for (i = 0; i < I915_NUM_RINGS; i++) |
4050 | init_ring_lists(&dev_priv->ring[i]); | |
4b9de737 | 4051 | for (i = 0; i < I915_MAX_NUM_FENCES; i++) |
007cc8ac | 4052 | INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list); |
673a394b EA |
4053 | INIT_DELAYED_WORK(&dev_priv->mm.retire_work, |
4054 | i915_gem_retire_work_handler); | |
30dbf0c0 | 4055 | init_completion(&dev_priv->error_completion); |
31169714 | 4056 | |
94400120 DA |
4057 | /* On GEN3 we really need to make sure the ARB C3 LP bit is set */ |
4058 | if (IS_GEN3(dev)) { | |
50743298 DV |
4059 | I915_WRITE(MI_ARB_STATE, |
4060 | _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE)); | |
94400120 DA |
4061 | } |
4062 | ||
72bfa19c CW |
4063 | dev_priv->relative_constants_mode = I915_EXEC_CONSTANTS_REL_GENERAL; |
4064 | ||
de151cf6 | 4065 | /* Old X drivers will take 0-2 for front, back, depth buffers */ |
b397c836 EA |
4066 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) |
4067 | dev_priv->fence_reg_start = 3; | |
de151cf6 | 4068 | |
a6c45cf0 | 4069 | if (INTEL_INFO(dev)->gen >= 4 || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) |
de151cf6 JB |
4070 | dev_priv->num_fence_regs = 16; |
4071 | else | |
4072 | dev_priv->num_fence_regs = 8; | |
4073 | ||
b5aa8a0f | 4074 | /* Initialize fence registers to zero */ |
ada726c7 | 4075 | i915_gem_reset_fences(dev); |
10ed13e4 | 4076 | |
673a394b | 4077 | i915_gem_detect_bit_6_swizzle(dev); |
6b95a207 | 4078 | init_waitqueue_head(&dev_priv->pending_flip_queue); |
17250b71 | 4079 | |
ce453d81 CW |
4080 | dev_priv->mm.interruptible = true; |
4081 | ||
17250b71 CW |
4082 | dev_priv->mm.inactive_shrinker.shrink = i915_gem_inactive_shrink; |
4083 | dev_priv->mm.inactive_shrinker.seeks = DEFAULT_SEEKS; | |
4084 | register_shrinker(&dev_priv->mm.inactive_shrinker); | |
673a394b | 4085 | } |
71acb5eb DA |
4086 | |
4087 | /* | |
4088 | * Create a physically contiguous memory object for this object | |
4089 | * e.g. for cursor + overlay regs | |
4090 | */ | |
995b6762 CW |
4091 | static int i915_gem_init_phys_object(struct drm_device *dev, |
4092 | int id, int size, int align) | |
71acb5eb DA |
4093 | { |
4094 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4095 | struct drm_i915_gem_phys_object *phys_obj; | |
4096 | int ret; | |
4097 | ||
4098 | if (dev_priv->mm.phys_objs[id - 1] || !size) | |
4099 | return 0; | |
4100 | ||
9a298b2a | 4101 | phys_obj = kzalloc(sizeof(struct drm_i915_gem_phys_object), GFP_KERNEL); |
71acb5eb DA |
4102 | if (!phys_obj) |
4103 | return -ENOMEM; | |
4104 | ||
4105 | phys_obj->id = id; | |
4106 | ||
6eeefaf3 | 4107 | phys_obj->handle = drm_pci_alloc(dev, size, align); |
71acb5eb DA |
4108 | if (!phys_obj->handle) { |
4109 | ret = -ENOMEM; | |
4110 | goto kfree_obj; | |
4111 | } | |
4112 | #ifdef CONFIG_X86 | |
4113 | set_memory_wc((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE); | |
4114 | #endif | |
4115 | ||
4116 | dev_priv->mm.phys_objs[id - 1] = phys_obj; | |
4117 | ||
4118 | return 0; | |
4119 | kfree_obj: | |
9a298b2a | 4120 | kfree(phys_obj); |
71acb5eb DA |
4121 | return ret; |
4122 | } | |
4123 | ||
995b6762 | 4124 | static void i915_gem_free_phys_object(struct drm_device *dev, int id) |
71acb5eb DA |
4125 | { |
4126 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4127 | struct drm_i915_gem_phys_object *phys_obj; | |
4128 | ||
4129 | if (!dev_priv->mm.phys_objs[id - 1]) | |
4130 | return; | |
4131 | ||
4132 | phys_obj = dev_priv->mm.phys_objs[id - 1]; | |
4133 | if (phys_obj->cur_obj) { | |
4134 | i915_gem_detach_phys_object(dev, phys_obj->cur_obj); | |
4135 | } | |
4136 | ||
4137 | #ifdef CONFIG_X86 | |
4138 | set_memory_wb((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE); | |
4139 | #endif | |
4140 | drm_pci_free(dev, phys_obj->handle); | |
4141 | kfree(phys_obj); | |
4142 | dev_priv->mm.phys_objs[id - 1] = NULL; | |
4143 | } | |
4144 | ||
4145 | void i915_gem_free_all_phys_object(struct drm_device *dev) | |
4146 | { | |
4147 | int i; | |
4148 | ||
260883c8 | 4149 | for (i = I915_GEM_PHYS_CURSOR_0; i <= I915_MAX_PHYS_OBJECT; i++) |
71acb5eb DA |
4150 | i915_gem_free_phys_object(dev, i); |
4151 | } | |
4152 | ||
4153 | void i915_gem_detach_phys_object(struct drm_device *dev, | |
05394f39 | 4154 | struct drm_i915_gem_object *obj) |
71acb5eb | 4155 | { |
05394f39 | 4156 | struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping; |
e5281ccd | 4157 | char *vaddr; |
71acb5eb | 4158 | int i; |
71acb5eb DA |
4159 | int page_count; |
4160 | ||
05394f39 | 4161 | if (!obj->phys_obj) |
71acb5eb | 4162 | return; |
05394f39 | 4163 | vaddr = obj->phys_obj->handle->vaddr; |
71acb5eb | 4164 | |
05394f39 | 4165 | page_count = obj->base.size / PAGE_SIZE; |
71acb5eb | 4166 | for (i = 0; i < page_count; i++) { |
5949eac4 | 4167 | struct page *page = shmem_read_mapping_page(mapping, i); |
e5281ccd CW |
4168 | if (!IS_ERR(page)) { |
4169 | char *dst = kmap_atomic(page); | |
4170 | memcpy(dst, vaddr + i*PAGE_SIZE, PAGE_SIZE); | |
4171 | kunmap_atomic(dst); | |
4172 | ||
4173 | drm_clflush_pages(&page, 1); | |
4174 | ||
4175 | set_page_dirty(page); | |
4176 | mark_page_accessed(page); | |
4177 | page_cache_release(page); | |
4178 | } | |
71acb5eb | 4179 | } |
40ce6575 | 4180 | intel_gtt_chipset_flush(); |
d78b47b9 | 4181 | |
05394f39 CW |
4182 | obj->phys_obj->cur_obj = NULL; |
4183 | obj->phys_obj = NULL; | |
71acb5eb DA |
4184 | } |
4185 | ||
4186 | int | |
4187 | i915_gem_attach_phys_object(struct drm_device *dev, | |
05394f39 | 4188 | struct drm_i915_gem_object *obj, |
6eeefaf3 CW |
4189 | int id, |
4190 | int align) | |
71acb5eb | 4191 | { |
05394f39 | 4192 | struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping; |
71acb5eb | 4193 | drm_i915_private_t *dev_priv = dev->dev_private; |
71acb5eb DA |
4194 | int ret = 0; |
4195 | int page_count; | |
4196 | int i; | |
4197 | ||
4198 | if (id > I915_MAX_PHYS_OBJECT) | |
4199 | return -EINVAL; | |
4200 | ||
05394f39 CW |
4201 | if (obj->phys_obj) { |
4202 | if (obj->phys_obj->id == id) | |
71acb5eb DA |
4203 | return 0; |
4204 | i915_gem_detach_phys_object(dev, obj); | |
4205 | } | |
4206 | ||
71acb5eb DA |
4207 | /* create a new object */ |
4208 | if (!dev_priv->mm.phys_objs[id - 1]) { | |
4209 | ret = i915_gem_init_phys_object(dev, id, | |
05394f39 | 4210 | obj->base.size, align); |
71acb5eb | 4211 | if (ret) { |
05394f39 CW |
4212 | DRM_ERROR("failed to init phys object %d size: %zu\n", |
4213 | id, obj->base.size); | |
e5281ccd | 4214 | return ret; |
71acb5eb DA |
4215 | } |
4216 | } | |
4217 | ||
4218 | /* bind to the object */ | |
05394f39 CW |
4219 | obj->phys_obj = dev_priv->mm.phys_objs[id - 1]; |
4220 | obj->phys_obj->cur_obj = obj; | |
71acb5eb | 4221 | |
05394f39 | 4222 | page_count = obj->base.size / PAGE_SIZE; |
71acb5eb DA |
4223 | |
4224 | for (i = 0; i < page_count; i++) { | |
e5281ccd CW |
4225 | struct page *page; |
4226 | char *dst, *src; | |
4227 | ||
5949eac4 | 4228 | page = shmem_read_mapping_page(mapping, i); |
e5281ccd CW |
4229 | if (IS_ERR(page)) |
4230 | return PTR_ERR(page); | |
71acb5eb | 4231 | |
ff75b9bc | 4232 | src = kmap_atomic(page); |
05394f39 | 4233 | dst = obj->phys_obj->handle->vaddr + (i * PAGE_SIZE); |
71acb5eb | 4234 | memcpy(dst, src, PAGE_SIZE); |
3e4d3af5 | 4235 | kunmap_atomic(src); |
71acb5eb | 4236 | |
e5281ccd CW |
4237 | mark_page_accessed(page); |
4238 | page_cache_release(page); | |
4239 | } | |
d78b47b9 | 4240 | |
71acb5eb | 4241 | return 0; |
71acb5eb DA |
4242 | } |
4243 | ||
4244 | static int | |
05394f39 CW |
4245 | i915_gem_phys_pwrite(struct drm_device *dev, |
4246 | struct drm_i915_gem_object *obj, | |
71acb5eb DA |
4247 | struct drm_i915_gem_pwrite *args, |
4248 | struct drm_file *file_priv) | |
4249 | { | |
05394f39 | 4250 | void *vaddr = obj->phys_obj->handle->vaddr + args->offset; |
b47b30cc | 4251 | char __user *user_data = (char __user *) (uintptr_t) args->data_ptr; |
71acb5eb | 4252 | |
b47b30cc CW |
4253 | if (__copy_from_user_inatomic_nocache(vaddr, user_data, args->size)) { |
4254 | unsigned long unwritten; | |
4255 | ||
4256 | /* The physical object once assigned is fixed for the lifetime | |
4257 | * of the obj, so we can safely drop the lock and continue | |
4258 | * to access vaddr. | |
4259 | */ | |
4260 | mutex_unlock(&dev->struct_mutex); | |
4261 | unwritten = copy_from_user(vaddr, user_data, args->size); | |
4262 | mutex_lock(&dev->struct_mutex); | |
4263 | if (unwritten) | |
4264 | return -EFAULT; | |
4265 | } | |
71acb5eb | 4266 | |
40ce6575 | 4267 | intel_gtt_chipset_flush(); |
71acb5eb DA |
4268 | return 0; |
4269 | } | |
b962442e | 4270 | |
f787a5f5 | 4271 | void i915_gem_release(struct drm_device *dev, struct drm_file *file) |
b962442e | 4272 | { |
f787a5f5 | 4273 | struct drm_i915_file_private *file_priv = file->driver_priv; |
b962442e EA |
4274 | |
4275 | /* Clean up our request list when the client is going away, so that | |
4276 | * later retire_requests won't dereference our soon-to-be-gone | |
4277 | * file_priv. | |
4278 | */ | |
1c25595f | 4279 | spin_lock(&file_priv->mm.lock); |
f787a5f5 CW |
4280 | while (!list_empty(&file_priv->mm.request_list)) { |
4281 | struct drm_i915_gem_request *request; | |
4282 | ||
4283 | request = list_first_entry(&file_priv->mm.request_list, | |
4284 | struct drm_i915_gem_request, | |
4285 | client_list); | |
4286 | list_del(&request->client_list); | |
4287 | request->file_priv = NULL; | |
4288 | } | |
1c25595f | 4289 | spin_unlock(&file_priv->mm.lock); |
b962442e | 4290 | } |
31169714 | 4291 | |
31169714 | 4292 | static int |
1495f230 | 4293 | i915_gem_inactive_shrink(struct shrinker *shrinker, struct shrink_control *sc) |
31169714 | 4294 | { |
17250b71 CW |
4295 | struct drm_i915_private *dev_priv = |
4296 | container_of(shrinker, | |
4297 | struct drm_i915_private, | |
4298 | mm.inactive_shrinker); | |
4299 | struct drm_device *dev = dev_priv->dev; | |
6c085a72 | 4300 | struct drm_i915_gem_object *obj; |
1495f230 | 4301 | int nr_to_scan = sc->nr_to_scan; |
17250b71 CW |
4302 | int cnt; |
4303 | ||
4304 | if (!mutex_trylock(&dev->struct_mutex)) | |
bbe2e11a | 4305 | return 0; |
31169714 | 4306 | |
6c085a72 CW |
4307 | if (nr_to_scan) { |
4308 | nr_to_scan -= i915_gem_purge(dev_priv, nr_to_scan); | |
4309 | if (nr_to_scan > 0) | |
4310 | i915_gem_shrink_all(dev_priv); | |
31169714 CW |
4311 | } |
4312 | ||
17250b71 | 4313 | cnt = 0; |
6c085a72 CW |
4314 | list_for_each_entry(obj, &dev_priv->mm.unbound_list, gtt_list) |
4315 | cnt += obj->base.size >> PAGE_SHIFT; | |
4316 | list_for_each_entry(obj, &dev_priv->mm.bound_list, gtt_list) | |
4317 | if (obj->pin_count == 0) | |
4318 | cnt += obj->base.size >> PAGE_SHIFT; | |
17250b71 | 4319 | |
17250b71 | 4320 | mutex_unlock(&dev->struct_mutex); |
6c085a72 | 4321 | return cnt; |
31169714 | 4322 | } |