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Commit | Line | Data |
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673a394b EA |
1 | /* |
2 | * Copyright © 2008 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | * | |
26 | */ | |
27 | ||
28 | #include "drmP.h" | |
29 | #include "drm.h" | |
30 | #include "i915_drm.h" | |
31 | #include "i915_drv.h" | |
1c5d22f7 | 32 | #include "i915_trace.h" |
652c393a | 33 | #include "intel_drv.h" |
5a0e3ad6 | 34 | #include <linux/slab.h> |
673a394b | 35 | #include <linux/swap.h> |
79e53945 | 36 | #include <linux/pci.h> |
f8f235e5 | 37 | #include <linux/intel-gtt.h> |
673a394b | 38 | |
0108a3ed | 39 | static uint32_t i915_gem_get_gtt_alignment(struct drm_gem_object *obj); |
ba3d8d74 DV |
40 | |
41 | static int i915_gem_object_flush_gpu_write_domain(struct drm_gem_object *obj, | |
42 | bool pipelined); | |
e47c68e9 EA |
43 | static void i915_gem_object_flush_gtt_write_domain(struct drm_gem_object *obj); |
44 | static void i915_gem_object_flush_cpu_write_domain(struct drm_gem_object *obj); | |
e47c68e9 EA |
45 | static int i915_gem_object_set_to_cpu_domain(struct drm_gem_object *obj, |
46 | int write); | |
47 | static int i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object *obj, | |
48 | uint64_t offset, | |
49 | uint64_t size); | |
50 | static void i915_gem_object_set_to_full_cpu_read_domain(struct drm_gem_object *obj); | |
2cf34d7b CW |
51 | static int i915_gem_object_wait_rendering(struct drm_gem_object *obj, |
52 | bool interruptible); | |
de151cf6 JB |
53 | static int i915_gem_object_bind_to_gtt(struct drm_gem_object *obj, |
54 | unsigned alignment); | |
de151cf6 | 55 | static void i915_gem_clear_fence_reg(struct drm_gem_object *obj); |
71acb5eb DA |
56 | static int i915_gem_phys_pwrite(struct drm_device *dev, struct drm_gem_object *obj, |
57 | struct drm_i915_gem_pwrite *args, | |
58 | struct drm_file *file_priv); | |
be72615b | 59 | static void i915_gem_free_object_tail(struct drm_gem_object *obj); |
673a394b | 60 | |
5cdf5881 CW |
61 | static int |
62 | i915_gem_object_get_pages(struct drm_gem_object *obj, | |
63 | gfp_t gfpmask); | |
64 | ||
65 | static void | |
66 | i915_gem_object_put_pages(struct drm_gem_object *obj); | |
67 | ||
31169714 CW |
68 | static LIST_HEAD(shrink_list); |
69 | static DEFINE_SPINLOCK(shrink_list_lock); | |
70 | ||
73aa808f CW |
71 | /* some bookkeeping */ |
72 | static void i915_gem_info_add_obj(struct drm_i915_private *dev_priv, | |
73 | size_t size) | |
74 | { | |
75 | dev_priv->mm.object_count++; | |
76 | dev_priv->mm.object_memory += size; | |
77 | } | |
78 | ||
79 | static void i915_gem_info_remove_obj(struct drm_i915_private *dev_priv, | |
80 | size_t size) | |
81 | { | |
82 | dev_priv->mm.object_count--; | |
83 | dev_priv->mm.object_memory -= size; | |
84 | } | |
85 | ||
86 | static void i915_gem_info_add_gtt(struct drm_i915_private *dev_priv, | |
87 | size_t size) | |
88 | { | |
89 | dev_priv->mm.gtt_count++; | |
90 | dev_priv->mm.gtt_memory += size; | |
91 | } | |
92 | ||
93 | static void i915_gem_info_remove_gtt(struct drm_i915_private *dev_priv, | |
94 | size_t size) | |
95 | { | |
96 | dev_priv->mm.gtt_count--; | |
97 | dev_priv->mm.gtt_memory -= size; | |
98 | } | |
99 | ||
100 | static void i915_gem_info_add_pin(struct drm_i915_private *dev_priv, | |
101 | size_t size) | |
102 | { | |
103 | dev_priv->mm.pin_count++; | |
104 | dev_priv->mm.pin_memory += size; | |
105 | } | |
106 | ||
107 | static void i915_gem_info_remove_pin(struct drm_i915_private *dev_priv, | |
108 | size_t size) | |
109 | { | |
110 | dev_priv->mm.pin_count--; | |
111 | dev_priv->mm.pin_memory -= size; | |
112 | } | |
113 | ||
30dbf0c0 CW |
114 | int |
115 | i915_gem_check_is_wedged(struct drm_device *dev) | |
116 | { | |
117 | struct drm_i915_private *dev_priv = dev->dev_private; | |
118 | struct completion *x = &dev_priv->error_completion; | |
119 | unsigned long flags; | |
120 | int ret; | |
121 | ||
122 | if (!atomic_read(&dev_priv->mm.wedged)) | |
123 | return 0; | |
124 | ||
125 | ret = wait_for_completion_interruptible(x); | |
126 | if (ret) | |
127 | return ret; | |
128 | ||
129 | /* Success, we reset the GPU! */ | |
130 | if (!atomic_read(&dev_priv->mm.wedged)) | |
131 | return 0; | |
132 | ||
133 | /* GPU is hung, bump the completion count to account for | |
134 | * the token we just consumed so that we never hit zero and | |
135 | * end up waiting upon a subsequent completion event that | |
136 | * will never happen. | |
137 | */ | |
138 | spin_lock_irqsave(&x->wait.lock, flags); | |
139 | x->done++; | |
140 | spin_unlock_irqrestore(&x->wait.lock, flags); | |
141 | return -EIO; | |
142 | } | |
143 | ||
76c1dec1 CW |
144 | static int i915_mutex_lock_interruptible(struct drm_device *dev) |
145 | { | |
146 | struct drm_i915_private *dev_priv = dev->dev_private; | |
147 | int ret; | |
148 | ||
149 | ret = i915_gem_check_is_wedged(dev); | |
150 | if (ret) | |
151 | return ret; | |
152 | ||
153 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
154 | if (ret) | |
155 | return ret; | |
156 | ||
157 | if (atomic_read(&dev_priv->mm.wedged)) { | |
158 | mutex_unlock(&dev->struct_mutex); | |
159 | return -EAGAIN; | |
160 | } | |
161 | ||
23bc5982 | 162 | WARN_ON(i915_verify_lists(dev)); |
76c1dec1 CW |
163 | return 0; |
164 | } | |
30dbf0c0 | 165 | |
7d1c4804 CW |
166 | static inline bool |
167 | i915_gem_object_is_inactive(struct drm_i915_gem_object *obj_priv) | |
168 | { | |
169 | return obj_priv->gtt_space && | |
170 | !obj_priv->active && | |
171 | obj_priv->pin_count == 0; | |
172 | } | |
173 | ||
73aa808f CW |
174 | int i915_gem_do_init(struct drm_device *dev, |
175 | unsigned long start, | |
79e53945 | 176 | unsigned long end) |
673a394b EA |
177 | { |
178 | drm_i915_private_t *dev_priv = dev->dev_private; | |
673a394b | 179 | |
79e53945 JB |
180 | if (start >= end || |
181 | (start & (PAGE_SIZE - 1)) != 0 || | |
182 | (end & (PAGE_SIZE - 1)) != 0) { | |
673a394b EA |
183 | return -EINVAL; |
184 | } | |
185 | ||
79e53945 JB |
186 | drm_mm_init(&dev_priv->mm.gtt_space, start, |
187 | end - start); | |
673a394b | 188 | |
73aa808f | 189 | dev_priv->mm.gtt_total = end - start; |
79e53945 JB |
190 | |
191 | return 0; | |
192 | } | |
673a394b | 193 | |
79e53945 JB |
194 | int |
195 | i915_gem_init_ioctl(struct drm_device *dev, void *data, | |
196 | struct drm_file *file_priv) | |
197 | { | |
198 | struct drm_i915_gem_init *args = data; | |
199 | int ret; | |
200 | ||
201 | mutex_lock(&dev->struct_mutex); | |
202 | ret = i915_gem_do_init(dev, args->gtt_start, args->gtt_end); | |
673a394b EA |
203 | mutex_unlock(&dev->struct_mutex); |
204 | ||
79e53945 | 205 | return ret; |
673a394b EA |
206 | } |
207 | ||
5a125c3c EA |
208 | int |
209 | i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data, | |
210 | struct drm_file *file_priv) | |
211 | { | |
73aa808f | 212 | struct drm_i915_private *dev_priv = dev->dev_private; |
5a125c3c | 213 | struct drm_i915_gem_get_aperture *args = data; |
5a125c3c EA |
214 | |
215 | if (!(dev->driver->driver_features & DRIVER_GEM)) | |
216 | return -ENODEV; | |
217 | ||
73aa808f CW |
218 | mutex_lock(&dev->struct_mutex); |
219 | args->aper_size = dev_priv->mm.gtt_total; | |
220 | args->aper_available_size = args->aper_size - dev_priv->mm.pin_memory; | |
221 | mutex_unlock(&dev->struct_mutex); | |
5a125c3c EA |
222 | |
223 | return 0; | |
224 | } | |
225 | ||
673a394b EA |
226 | |
227 | /** | |
228 | * Creates a new mm object and returns a handle to it. | |
229 | */ | |
230 | int | |
231 | i915_gem_create_ioctl(struct drm_device *dev, void *data, | |
232 | struct drm_file *file_priv) | |
233 | { | |
234 | struct drm_i915_gem_create *args = data; | |
235 | struct drm_gem_object *obj; | |
a1a2d1d3 PP |
236 | int ret; |
237 | u32 handle; | |
673a394b EA |
238 | |
239 | args->size = roundup(args->size, PAGE_SIZE); | |
240 | ||
241 | /* Allocate the new object */ | |
ac52bc56 | 242 | obj = i915_gem_alloc_object(dev, args->size); |
673a394b EA |
243 | if (obj == NULL) |
244 | return -ENOMEM; | |
245 | ||
246 | ret = drm_gem_handle_create(file_priv, obj, &handle); | |
29d08b3e DA |
247 | /* drop reference from allocate - handle holds it now */ |
248 | drm_gem_object_unreference_unlocked(obj); | |
1dfd9754 | 249 | if (ret) { |
673a394b | 250 | return ret; |
1dfd9754 | 251 | } |
673a394b | 252 | |
1dfd9754 | 253 | args->handle = handle; |
673a394b EA |
254 | return 0; |
255 | } | |
256 | ||
eb01459f EA |
257 | static inline int |
258 | fast_shmem_read(struct page **pages, | |
259 | loff_t page_base, int page_offset, | |
260 | char __user *data, | |
261 | int length) | |
262 | { | |
263 | char __iomem *vaddr; | |
2bc43b5c | 264 | int unwritten; |
eb01459f EA |
265 | |
266 | vaddr = kmap_atomic(pages[page_base >> PAGE_SHIFT], KM_USER0); | |
267 | if (vaddr == NULL) | |
268 | return -ENOMEM; | |
2bc43b5c | 269 | unwritten = __copy_to_user_inatomic(data, vaddr + page_offset, length); |
eb01459f EA |
270 | kunmap_atomic(vaddr, KM_USER0); |
271 | ||
2bc43b5c FM |
272 | if (unwritten) |
273 | return -EFAULT; | |
274 | ||
275 | return 0; | |
eb01459f EA |
276 | } |
277 | ||
280b713b EA |
278 | static int i915_gem_object_needs_bit17_swizzle(struct drm_gem_object *obj) |
279 | { | |
280 | drm_i915_private_t *dev_priv = obj->dev->dev_private; | |
23010e43 | 281 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
280b713b EA |
282 | |
283 | return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 && | |
284 | obj_priv->tiling_mode != I915_TILING_NONE; | |
285 | } | |
286 | ||
99a03df5 | 287 | static inline void |
40123c1f EA |
288 | slow_shmem_copy(struct page *dst_page, |
289 | int dst_offset, | |
290 | struct page *src_page, | |
291 | int src_offset, | |
292 | int length) | |
293 | { | |
294 | char *dst_vaddr, *src_vaddr; | |
295 | ||
99a03df5 CW |
296 | dst_vaddr = kmap(dst_page); |
297 | src_vaddr = kmap(src_page); | |
40123c1f EA |
298 | |
299 | memcpy(dst_vaddr + dst_offset, src_vaddr + src_offset, length); | |
300 | ||
99a03df5 CW |
301 | kunmap(src_page); |
302 | kunmap(dst_page); | |
40123c1f EA |
303 | } |
304 | ||
99a03df5 | 305 | static inline void |
280b713b EA |
306 | slow_shmem_bit17_copy(struct page *gpu_page, |
307 | int gpu_offset, | |
308 | struct page *cpu_page, | |
309 | int cpu_offset, | |
310 | int length, | |
311 | int is_read) | |
312 | { | |
313 | char *gpu_vaddr, *cpu_vaddr; | |
314 | ||
315 | /* Use the unswizzled path if this page isn't affected. */ | |
316 | if ((page_to_phys(gpu_page) & (1 << 17)) == 0) { | |
317 | if (is_read) | |
318 | return slow_shmem_copy(cpu_page, cpu_offset, | |
319 | gpu_page, gpu_offset, length); | |
320 | else | |
321 | return slow_shmem_copy(gpu_page, gpu_offset, | |
322 | cpu_page, cpu_offset, length); | |
323 | } | |
324 | ||
99a03df5 CW |
325 | gpu_vaddr = kmap(gpu_page); |
326 | cpu_vaddr = kmap(cpu_page); | |
280b713b EA |
327 | |
328 | /* Copy the data, XORing A6 with A17 (1). The user already knows he's | |
329 | * XORing with the other bits (A9 for Y, A9 and A10 for X) | |
330 | */ | |
331 | while (length > 0) { | |
332 | int cacheline_end = ALIGN(gpu_offset + 1, 64); | |
333 | int this_length = min(cacheline_end - gpu_offset, length); | |
334 | int swizzled_gpu_offset = gpu_offset ^ 64; | |
335 | ||
336 | if (is_read) { | |
337 | memcpy(cpu_vaddr + cpu_offset, | |
338 | gpu_vaddr + swizzled_gpu_offset, | |
339 | this_length); | |
340 | } else { | |
341 | memcpy(gpu_vaddr + swizzled_gpu_offset, | |
342 | cpu_vaddr + cpu_offset, | |
343 | this_length); | |
344 | } | |
345 | cpu_offset += this_length; | |
346 | gpu_offset += this_length; | |
347 | length -= this_length; | |
348 | } | |
349 | ||
99a03df5 CW |
350 | kunmap(cpu_page); |
351 | kunmap(gpu_page); | |
280b713b EA |
352 | } |
353 | ||
eb01459f EA |
354 | /** |
355 | * This is the fast shmem pread path, which attempts to copy_from_user directly | |
356 | * from the backing pages of the object to the user's address space. On a | |
357 | * fault, it fails so we can fall back to i915_gem_shmem_pwrite_slow(). | |
358 | */ | |
359 | static int | |
360 | i915_gem_shmem_pread_fast(struct drm_device *dev, struct drm_gem_object *obj, | |
361 | struct drm_i915_gem_pread *args, | |
362 | struct drm_file *file_priv) | |
363 | { | |
23010e43 | 364 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
eb01459f EA |
365 | ssize_t remain; |
366 | loff_t offset, page_base; | |
367 | char __user *user_data; | |
368 | int page_offset, page_length; | |
369 | int ret; | |
370 | ||
371 | user_data = (char __user *) (uintptr_t) args->data_ptr; | |
372 | remain = args->size; | |
373 | ||
76c1dec1 CW |
374 | ret = i915_mutex_lock_interruptible(dev); |
375 | if (ret) | |
376 | return ret; | |
eb01459f | 377 | |
4bdadb97 | 378 | ret = i915_gem_object_get_pages(obj, 0); |
eb01459f EA |
379 | if (ret != 0) |
380 | goto fail_unlock; | |
381 | ||
382 | ret = i915_gem_object_set_cpu_read_domain_range(obj, args->offset, | |
383 | args->size); | |
384 | if (ret != 0) | |
385 | goto fail_put_pages; | |
386 | ||
23010e43 | 387 | obj_priv = to_intel_bo(obj); |
eb01459f EA |
388 | offset = args->offset; |
389 | ||
390 | while (remain > 0) { | |
391 | /* Operation in this page | |
392 | * | |
393 | * page_base = page offset within aperture | |
394 | * page_offset = offset within page | |
395 | * page_length = bytes to copy for this page | |
396 | */ | |
397 | page_base = (offset & ~(PAGE_SIZE-1)); | |
398 | page_offset = offset & (PAGE_SIZE-1); | |
399 | page_length = remain; | |
400 | if ((page_offset + remain) > PAGE_SIZE) | |
401 | page_length = PAGE_SIZE - page_offset; | |
402 | ||
403 | ret = fast_shmem_read(obj_priv->pages, | |
404 | page_base, page_offset, | |
405 | user_data, page_length); | |
406 | if (ret) | |
407 | goto fail_put_pages; | |
408 | ||
409 | remain -= page_length; | |
410 | user_data += page_length; | |
411 | offset += page_length; | |
412 | } | |
413 | ||
414 | fail_put_pages: | |
415 | i915_gem_object_put_pages(obj); | |
416 | fail_unlock: | |
417 | mutex_unlock(&dev->struct_mutex); | |
418 | ||
419 | return ret; | |
420 | } | |
421 | ||
07f73f69 CW |
422 | static int |
423 | i915_gem_object_get_pages_or_evict(struct drm_gem_object *obj) | |
424 | { | |
425 | int ret; | |
426 | ||
4bdadb97 | 427 | ret = i915_gem_object_get_pages(obj, __GFP_NORETRY | __GFP_NOWARN); |
07f73f69 CW |
428 | |
429 | /* If we've insufficient memory to map in the pages, attempt | |
430 | * to make some space by throwing out some old buffers. | |
431 | */ | |
432 | if (ret == -ENOMEM) { | |
433 | struct drm_device *dev = obj->dev; | |
07f73f69 | 434 | |
0108a3ed DV |
435 | ret = i915_gem_evict_something(dev, obj->size, |
436 | i915_gem_get_gtt_alignment(obj)); | |
07f73f69 CW |
437 | if (ret) |
438 | return ret; | |
439 | ||
4bdadb97 | 440 | ret = i915_gem_object_get_pages(obj, 0); |
07f73f69 CW |
441 | } |
442 | ||
443 | return ret; | |
444 | } | |
445 | ||
eb01459f EA |
446 | /** |
447 | * This is the fallback shmem pread path, which allocates temporary storage | |
448 | * in kernel space to copy_to_user into outside of the struct_mutex, so we | |
449 | * can copy out of the object's backing pages while holding the struct mutex | |
450 | * and not take page faults. | |
451 | */ | |
452 | static int | |
453 | i915_gem_shmem_pread_slow(struct drm_device *dev, struct drm_gem_object *obj, | |
454 | struct drm_i915_gem_pread *args, | |
455 | struct drm_file *file_priv) | |
456 | { | |
23010e43 | 457 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
eb01459f EA |
458 | struct mm_struct *mm = current->mm; |
459 | struct page **user_pages; | |
460 | ssize_t remain; | |
461 | loff_t offset, pinned_pages, i; | |
462 | loff_t first_data_page, last_data_page, num_pages; | |
463 | int shmem_page_index, shmem_page_offset; | |
464 | int data_page_index, data_page_offset; | |
465 | int page_length; | |
466 | int ret; | |
467 | uint64_t data_ptr = args->data_ptr; | |
280b713b | 468 | int do_bit17_swizzling; |
eb01459f EA |
469 | |
470 | remain = args->size; | |
471 | ||
472 | /* Pin the user pages containing the data. We can't fault while | |
473 | * holding the struct mutex, yet we want to hold it while | |
474 | * dereferencing the user data. | |
475 | */ | |
476 | first_data_page = data_ptr / PAGE_SIZE; | |
477 | last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE; | |
478 | num_pages = last_data_page - first_data_page + 1; | |
479 | ||
8e7d2b2c | 480 | user_pages = drm_calloc_large(num_pages, sizeof(struct page *)); |
eb01459f EA |
481 | if (user_pages == NULL) |
482 | return -ENOMEM; | |
483 | ||
484 | down_read(&mm->mmap_sem); | |
485 | pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr, | |
e5e9ecde | 486 | num_pages, 1, 0, user_pages, NULL); |
eb01459f EA |
487 | up_read(&mm->mmap_sem); |
488 | if (pinned_pages < num_pages) { | |
489 | ret = -EFAULT; | |
490 | goto fail_put_user_pages; | |
491 | } | |
492 | ||
280b713b EA |
493 | do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj); |
494 | ||
76c1dec1 CW |
495 | ret = i915_mutex_lock_interruptible(dev); |
496 | if (ret) | |
497 | goto fail_put_user_pages; | |
eb01459f | 498 | |
07f73f69 CW |
499 | ret = i915_gem_object_get_pages_or_evict(obj); |
500 | if (ret) | |
eb01459f EA |
501 | goto fail_unlock; |
502 | ||
503 | ret = i915_gem_object_set_cpu_read_domain_range(obj, args->offset, | |
504 | args->size); | |
505 | if (ret != 0) | |
506 | goto fail_put_pages; | |
507 | ||
23010e43 | 508 | obj_priv = to_intel_bo(obj); |
eb01459f EA |
509 | offset = args->offset; |
510 | ||
511 | while (remain > 0) { | |
512 | /* Operation in this page | |
513 | * | |
514 | * shmem_page_index = page number within shmem file | |
515 | * shmem_page_offset = offset within page in shmem file | |
516 | * data_page_index = page number in get_user_pages return | |
517 | * data_page_offset = offset with data_page_index page. | |
518 | * page_length = bytes to copy for this page | |
519 | */ | |
520 | shmem_page_index = offset / PAGE_SIZE; | |
521 | shmem_page_offset = offset & ~PAGE_MASK; | |
522 | data_page_index = data_ptr / PAGE_SIZE - first_data_page; | |
523 | data_page_offset = data_ptr & ~PAGE_MASK; | |
524 | ||
525 | page_length = remain; | |
526 | if ((shmem_page_offset + page_length) > PAGE_SIZE) | |
527 | page_length = PAGE_SIZE - shmem_page_offset; | |
528 | if ((data_page_offset + page_length) > PAGE_SIZE) | |
529 | page_length = PAGE_SIZE - data_page_offset; | |
530 | ||
280b713b | 531 | if (do_bit17_swizzling) { |
99a03df5 | 532 | slow_shmem_bit17_copy(obj_priv->pages[shmem_page_index], |
280b713b | 533 | shmem_page_offset, |
99a03df5 CW |
534 | user_pages[data_page_index], |
535 | data_page_offset, | |
536 | page_length, | |
537 | 1); | |
538 | } else { | |
539 | slow_shmem_copy(user_pages[data_page_index], | |
540 | data_page_offset, | |
541 | obj_priv->pages[shmem_page_index], | |
542 | shmem_page_offset, | |
543 | page_length); | |
280b713b | 544 | } |
eb01459f EA |
545 | |
546 | remain -= page_length; | |
547 | data_ptr += page_length; | |
548 | offset += page_length; | |
549 | } | |
550 | ||
551 | fail_put_pages: | |
552 | i915_gem_object_put_pages(obj); | |
553 | fail_unlock: | |
554 | mutex_unlock(&dev->struct_mutex); | |
555 | fail_put_user_pages: | |
556 | for (i = 0; i < pinned_pages; i++) { | |
557 | SetPageDirty(user_pages[i]); | |
558 | page_cache_release(user_pages[i]); | |
559 | } | |
8e7d2b2c | 560 | drm_free_large(user_pages); |
eb01459f EA |
561 | |
562 | return ret; | |
563 | } | |
564 | ||
673a394b EA |
565 | /** |
566 | * Reads data from the object referenced by handle. | |
567 | * | |
568 | * On error, the contents of *data are undefined. | |
569 | */ | |
570 | int | |
571 | i915_gem_pread_ioctl(struct drm_device *dev, void *data, | |
572 | struct drm_file *file_priv) | |
573 | { | |
574 | struct drm_i915_gem_pread *args = data; | |
575 | struct drm_gem_object *obj; | |
576 | struct drm_i915_gem_object *obj_priv; | |
35b62a89 | 577 | int ret = 0; |
673a394b EA |
578 | |
579 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); | |
580 | if (obj == NULL) | |
bf79cb91 | 581 | return -ENOENT; |
23010e43 | 582 | obj_priv = to_intel_bo(obj); |
673a394b | 583 | |
7dcd2499 CW |
584 | /* Bounds check source. */ |
585 | if (args->offset > obj->size || args->size > obj->size - args->offset) { | |
ce9d419d | 586 | ret = -EINVAL; |
35b62a89 | 587 | goto out; |
ce9d419d CW |
588 | } |
589 | ||
35b62a89 CW |
590 | if (args->size == 0) |
591 | goto out; | |
592 | ||
ce9d419d CW |
593 | if (!access_ok(VERIFY_WRITE, |
594 | (char __user *)(uintptr_t)args->data_ptr, | |
595 | args->size)) { | |
596 | ret = -EFAULT; | |
35b62a89 | 597 | goto out; |
673a394b EA |
598 | } |
599 | ||
280b713b | 600 | if (i915_gem_object_needs_bit17_swizzle(obj)) { |
eb01459f | 601 | ret = i915_gem_shmem_pread_slow(dev, obj, args, file_priv); |
280b713b EA |
602 | } else { |
603 | ret = i915_gem_shmem_pread_fast(dev, obj, args, file_priv); | |
604 | if (ret != 0) | |
605 | ret = i915_gem_shmem_pread_slow(dev, obj, args, | |
606 | file_priv); | |
607 | } | |
673a394b | 608 | |
35b62a89 | 609 | out: |
bc9025bd | 610 | drm_gem_object_unreference_unlocked(obj); |
eb01459f | 611 | return ret; |
673a394b EA |
612 | } |
613 | ||
0839ccb8 KP |
614 | /* This is the fast write path which cannot handle |
615 | * page faults in the source data | |
9b7530cc | 616 | */ |
0839ccb8 KP |
617 | |
618 | static inline int | |
619 | fast_user_write(struct io_mapping *mapping, | |
620 | loff_t page_base, int page_offset, | |
621 | char __user *user_data, | |
622 | int length) | |
9b7530cc | 623 | { |
9b7530cc | 624 | char *vaddr_atomic; |
0839ccb8 | 625 | unsigned long unwritten; |
9b7530cc | 626 | |
fca3ec01 | 627 | vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base, KM_USER0); |
0839ccb8 KP |
628 | unwritten = __copy_from_user_inatomic_nocache(vaddr_atomic + page_offset, |
629 | user_data, length); | |
fca3ec01 | 630 | io_mapping_unmap_atomic(vaddr_atomic, KM_USER0); |
0839ccb8 KP |
631 | if (unwritten) |
632 | return -EFAULT; | |
633 | return 0; | |
634 | } | |
635 | ||
636 | /* Here's the write path which can sleep for | |
637 | * page faults | |
638 | */ | |
639 | ||
ab34c226 | 640 | static inline void |
3de09aa3 EA |
641 | slow_kernel_write(struct io_mapping *mapping, |
642 | loff_t gtt_base, int gtt_offset, | |
643 | struct page *user_page, int user_offset, | |
644 | int length) | |
0839ccb8 | 645 | { |
ab34c226 CW |
646 | char __iomem *dst_vaddr; |
647 | char *src_vaddr; | |
0839ccb8 | 648 | |
ab34c226 CW |
649 | dst_vaddr = io_mapping_map_wc(mapping, gtt_base); |
650 | src_vaddr = kmap(user_page); | |
651 | ||
652 | memcpy_toio(dst_vaddr + gtt_offset, | |
653 | src_vaddr + user_offset, | |
654 | length); | |
655 | ||
656 | kunmap(user_page); | |
657 | io_mapping_unmap(dst_vaddr); | |
9b7530cc LT |
658 | } |
659 | ||
40123c1f EA |
660 | static inline int |
661 | fast_shmem_write(struct page **pages, | |
662 | loff_t page_base, int page_offset, | |
663 | char __user *data, | |
664 | int length) | |
665 | { | |
666 | char __iomem *vaddr; | |
d0088775 | 667 | unsigned long unwritten; |
40123c1f EA |
668 | |
669 | vaddr = kmap_atomic(pages[page_base >> PAGE_SHIFT], KM_USER0); | |
670 | if (vaddr == NULL) | |
671 | return -ENOMEM; | |
d0088775 | 672 | unwritten = __copy_from_user_inatomic(vaddr + page_offset, data, length); |
40123c1f EA |
673 | kunmap_atomic(vaddr, KM_USER0); |
674 | ||
d0088775 DA |
675 | if (unwritten) |
676 | return -EFAULT; | |
40123c1f EA |
677 | return 0; |
678 | } | |
679 | ||
3de09aa3 EA |
680 | /** |
681 | * This is the fast pwrite path, where we copy the data directly from the | |
682 | * user into the GTT, uncached. | |
683 | */ | |
673a394b | 684 | static int |
3de09aa3 EA |
685 | i915_gem_gtt_pwrite_fast(struct drm_device *dev, struct drm_gem_object *obj, |
686 | struct drm_i915_gem_pwrite *args, | |
687 | struct drm_file *file_priv) | |
673a394b | 688 | { |
23010e43 | 689 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
0839ccb8 | 690 | drm_i915_private_t *dev_priv = dev->dev_private; |
673a394b | 691 | ssize_t remain; |
0839ccb8 | 692 | loff_t offset, page_base; |
673a394b | 693 | char __user *user_data; |
0839ccb8 KP |
694 | int page_offset, page_length; |
695 | int ret; | |
673a394b EA |
696 | |
697 | user_data = (char __user *) (uintptr_t) args->data_ptr; | |
698 | remain = args->size; | |
673a394b | 699 | |
76c1dec1 CW |
700 | ret = i915_mutex_lock_interruptible(dev); |
701 | if (ret) | |
702 | return ret; | |
673a394b | 703 | |
673a394b EA |
704 | ret = i915_gem_object_pin(obj, 0); |
705 | if (ret) { | |
706 | mutex_unlock(&dev->struct_mutex); | |
707 | return ret; | |
708 | } | |
2ef7eeaa | 709 | ret = i915_gem_object_set_to_gtt_domain(obj, 1); |
673a394b EA |
710 | if (ret) |
711 | goto fail; | |
712 | ||
23010e43 | 713 | obj_priv = to_intel_bo(obj); |
673a394b | 714 | offset = obj_priv->gtt_offset + args->offset; |
673a394b EA |
715 | |
716 | while (remain > 0) { | |
717 | /* Operation in this page | |
718 | * | |
0839ccb8 KP |
719 | * page_base = page offset within aperture |
720 | * page_offset = offset within page | |
721 | * page_length = bytes to copy for this page | |
673a394b | 722 | */ |
0839ccb8 KP |
723 | page_base = (offset & ~(PAGE_SIZE-1)); |
724 | page_offset = offset & (PAGE_SIZE-1); | |
725 | page_length = remain; | |
726 | if ((page_offset + remain) > PAGE_SIZE) | |
727 | page_length = PAGE_SIZE - page_offset; | |
728 | ||
729 | ret = fast_user_write (dev_priv->mm.gtt_mapping, page_base, | |
730 | page_offset, user_data, page_length); | |
731 | ||
732 | /* If we get a fault while copying data, then (presumably) our | |
3de09aa3 EA |
733 | * source page isn't available. Return the error and we'll |
734 | * retry in the slow path. | |
0839ccb8 | 735 | */ |
3de09aa3 EA |
736 | if (ret) |
737 | goto fail; | |
673a394b | 738 | |
0839ccb8 KP |
739 | remain -= page_length; |
740 | user_data += page_length; | |
741 | offset += page_length; | |
673a394b | 742 | } |
673a394b EA |
743 | |
744 | fail: | |
745 | i915_gem_object_unpin(obj); | |
746 | mutex_unlock(&dev->struct_mutex); | |
747 | ||
748 | return ret; | |
749 | } | |
750 | ||
3de09aa3 EA |
751 | /** |
752 | * This is the fallback GTT pwrite path, which uses get_user_pages to pin | |
753 | * the memory and maps it using kmap_atomic for copying. | |
754 | * | |
755 | * This code resulted in x11perf -rgb10text consuming about 10% more CPU | |
756 | * than using i915_gem_gtt_pwrite_fast on a G45 (32-bit). | |
757 | */ | |
3043c60c | 758 | static int |
3de09aa3 EA |
759 | i915_gem_gtt_pwrite_slow(struct drm_device *dev, struct drm_gem_object *obj, |
760 | struct drm_i915_gem_pwrite *args, | |
761 | struct drm_file *file_priv) | |
673a394b | 762 | { |
23010e43 | 763 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
3de09aa3 EA |
764 | drm_i915_private_t *dev_priv = dev->dev_private; |
765 | ssize_t remain; | |
766 | loff_t gtt_page_base, offset; | |
767 | loff_t first_data_page, last_data_page, num_pages; | |
768 | loff_t pinned_pages, i; | |
769 | struct page **user_pages; | |
770 | struct mm_struct *mm = current->mm; | |
771 | int gtt_page_offset, data_page_offset, data_page_index, page_length; | |
673a394b | 772 | int ret; |
3de09aa3 EA |
773 | uint64_t data_ptr = args->data_ptr; |
774 | ||
775 | remain = args->size; | |
776 | ||
777 | /* Pin the user pages containing the data. We can't fault while | |
778 | * holding the struct mutex, and all of the pwrite implementations | |
779 | * want to hold it while dereferencing the user data. | |
780 | */ | |
781 | first_data_page = data_ptr / PAGE_SIZE; | |
782 | last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE; | |
783 | num_pages = last_data_page - first_data_page + 1; | |
784 | ||
8e7d2b2c | 785 | user_pages = drm_calloc_large(num_pages, sizeof(struct page *)); |
3de09aa3 EA |
786 | if (user_pages == NULL) |
787 | return -ENOMEM; | |
788 | ||
789 | down_read(&mm->mmap_sem); | |
790 | pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr, | |
791 | num_pages, 0, 0, user_pages, NULL); | |
792 | up_read(&mm->mmap_sem); | |
793 | if (pinned_pages < num_pages) { | |
794 | ret = -EFAULT; | |
795 | goto out_unpin_pages; | |
796 | } | |
673a394b | 797 | |
76c1dec1 CW |
798 | ret = i915_mutex_lock_interruptible(dev); |
799 | if (ret) | |
800 | goto out_unpin_pages; | |
801 | ||
3de09aa3 EA |
802 | ret = i915_gem_object_pin(obj, 0); |
803 | if (ret) | |
804 | goto out_unlock; | |
805 | ||
806 | ret = i915_gem_object_set_to_gtt_domain(obj, 1); | |
807 | if (ret) | |
808 | goto out_unpin_object; | |
809 | ||
23010e43 | 810 | obj_priv = to_intel_bo(obj); |
3de09aa3 EA |
811 | offset = obj_priv->gtt_offset + args->offset; |
812 | ||
813 | while (remain > 0) { | |
814 | /* Operation in this page | |
815 | * | |
816 | * gtt_page_base = page offset within aperture | |
817 | * gtt_page_offset = offset within page in aperture | |
818 | * data_page_index = page number in get_user_pages return | |
819 | * data_page_offset = offset with data_page_index page. | |
820 | * page_length = bytes to copy for this page | |
821 | */ | |
822 | gtt_page_base = offset & PAGE_MASK; | |
823 | gtt_page_offset = offset & ~PAGE_MASK; | |
824 | data_page_index = data_ptr / PAGE_SIZE - first_data_page; | |
825 | data_page_offset = data_ptr & ~PAGE_MASK; | |
826 | ||
827 | page_length = remain; | |
828 | if ((gtt_page_offset + page_length) > PAGE_SIZE) | |
829 | page_length = PAGE_SIZE - gtt_page_offset; | |
830 | if ((data_page_offset + page_length) > PAGE_SIZE) | |
831 | page_length = PAGE_SIZE - data_page_offset; | |
832 | ||
ab34c226 CW |
833 | slow_kernel_write(dev_priv->mm.gtt_mapping, |
834 | gtt_page_base, gtt_page_offset, | |
835 | user_pages[data_page_index], | |
836 | data_page_offset, | |
837 | page_length); | |
3de09aa3 EA |
838 | |
839 | remain -= page_length; | |
840 | offset += page_length; | |
841 | data_ptr += page_length; | |
842 | } | |
843 | ||
844 | out_unpin_object: | |
845 | i915_gem_object_unpin(obj); | |
846 | out_unlock: | |
847 | mutex_unlock(&dev->struct_mutex); | |
848 | out_unpin_pages: | |
849 | for (i = 0; i < pinned_pages; i++) | |
850 | page_cache_release(user_pages[i]); | |
8e7d2b2c | 851 | drm_free_large(user_pages); |
3de09aa3 EA |
852 | |
853 | return ret; | |
854 | } | |
855 | ||
40123c1f EA |
856 | /** |
857 | * This is the fast shmem pwrite path, which attempts to directly | |
858 | * copy_from_user into the kmapped pages backing the object. | |
859 | */ | |
3043c60c | 860 | static int |
40123c1f EA |
861 | i915_gem_shmem_pwrite_fast(struct drm_device *dev, struct drm_gem_object *obj, |
862 | struct drm_i915_gem_pwrite *args, | |
863 | struct drm_file *file_priv) | |
673a394b | 864 | { |
23010e43 | 865 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
40123c1f EA |
866 | ssize_t remain; |
867 | loff_t offset, page_base; | |
868 | char __user *user_data; | |
869 | int page_offset, page_length; | |
673a394b | 870 | int ret; |
40123c1f EA |
871 | |
872 | user_data = (char __user *) (uintptr_t) args->data_ptr; | |
873 | remain = args->size; | |
673a394b | 874 | |
76c1dec1 CW |
875 | ret = i915_mutex_lock_interruptible(dev); |
876 | if (ret) | |
877 | return ret; | |
673a394b | 878 | |
4bdadb97 | 879 | ret = i915_gem_object_get_pages(obj, 0); |
40123c1f EA |
880 | if (ret != 0) |
881 | goto fail_unlock; | |
673a394b | 882 | |
e47c68e9 | 883 | ret = i915_gem_object_set_to_cpu_domain(obj, 1); |
40123c1f EA |
884 | if (ret != 0) |
885 | goto fail_put_pages; | |
886 | ||
23010e43 | 887 | obj_priv = to_intel_bo(obj); |
40123c1f EA |
888 | offset = args->offset; |
889 | obj_priv->dirty = 1; | |
890 | ||
891 | while (remain > 0) { | |
892 | /* Operation in this page | |
893 | * | |
894 | * page_base = page offset within aperture | |
895 | * page_offset = offset within page | |
896 | * page_length = bytes to copy for this page | |
897 | */ | |
898 | page_base = (offset & ~(PAGE_SIZE-1)); | |
899 | page_offset = offset & (PAGE_SIZE-1); | |
900 | page_length = remain; | |
901 | if ((page_offset + remain) > PAGE_SIZE) | |
902 | page_length = PAGE_SIZE - page_offset; | |
903 | ||
904 | ret = fast_shmem_write(obj_priv->pages, | |
905 | page_base, page_offset, | |
906 | user_data, page_length); | |
907 | if (ret) | |
908 | goto fail_put_pages; | |
909 | ||
910 | remain -= page_length; | |
911 | user_data += page_length; | |
912 | offset += page_length; | |
913 | } | |
914 | ||
915 | fail_put_pages: | |
916 | i915_gem_object_put_pages(obj); | |
917 | fail_unlock: | |
918 | mutex_unlock(&dev->struct_mutex); | |
919 | ||
920 | return ret; | |
921 | } | |
922 | ||
923 | /** | |
924 | * This is the fallback shmem pwrite path, which uses get_user_pages to pin | |
925 | * the memory and maps it using kmap_atomic for copying. | |
926 | * | |
927 | * This avoids taking mmap_sem for faulting on the user's address while the | |
928 | * struct_mutex is held. | |
929 | */ | |
930 | static int | |
931 | i915_gem_shmem_pwrite_slow(struct drm_device *dev, struct drm_gem_object *obj, | |
932 | struct drm_i915_gem_pwrite *args, | |
933 | struct drm_file *file_priv) | |
934 | { | |
23010e43 | 935 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
40123c1f EA |
936 | struct mm_struct *mm = current->mm; |
937 | struct page **user_pages; | |
938 | ssize_t remain; | |
939 | loff_t offset, pinned_pages, i; | |
940 | loff_t first_data_page, last_data_page, num_pages; | |
941 | int shmem_page_index, shmem_page_offset; | |
942 | int data_page_index, data_page_offset; | |
943 | int page_length; | |
944 | int ret; | |
945 | uint64_t data_ptr = args->data_ptr; | |
280b713b | 946 | int do_bit17_swizzling; |
40123c1f EA |
947 | |
948 | remain = args->size; | |
949 | ||
950 | /* Pin the user pages containing the data. We can't fault while | |
951 | * holding the struct mutex, and all of the pwrite implementations | |
952 | * want to hold it while dereferencing the user data. | |
953 | */ | |
954 | first_data_page = data_ptr / PAGE_SIZE; | |
955 | last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE; | |
956 | num_pages = last_data_page - first_data_page + 1; | |
957 | ||
8e7d2b2c | 958 | user_pages = drm_calloc_large(num_pages, sizeof(struct page *)); |
40123c1f EA |
959 | if (user_pages == NULL) |
960 | return -ENOMEM; | |
961 | ||
962 | down_read(&mm->mmap_sem); | |
963 | pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr, | |
964 | num_pages, 0, 0, user_pages, NULL); | |
965 | up_read(&mm->mmap_sem); | |
966 | if (pinned_pages < num_pages) { | |
967 | ret = -EFAULT; | |
968 | goto fail_put_user_pages; | |
673a394b EA |
969 | } |
970 | ||
280b713b EA |
971 | do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj); |
972 | ||
76c1dec1 CW |
973 | ret = i915_mutex_lock_interruptible(dev); |
974 | if (ret) | |
975 | goto fail_put_user_pages; | |
40123c1f | 976 | |
07f73f69 CW |
977 | ret = i915_gem_object_get_pages_or_evict(obj); |
978 | if (ret) | |
40123c1f EA |
979 | goto fail_unlock; |
980 | ||
981 | ret = i915_gem_object_set_to_cpu_domain(obj, 1); | |
982 | if (ret != 0) | |
983 | goto fail_put_pages; | |
984 | ||
23010e43 | 985 | obj_priv = to_intel_bo(obj); |
673a394b | 986 | offset = args->offset; |
40123c1f | 987 | obj_priv->dirty = 1; |
673a394b | 988 | |
40123c1f EA |
989 | while (remain > 0) { |
990 | /* Operation in this page | |
991 | * | |
992 | * shmem_page_index = page number within shmem file | |
993 | * shmem_page_offset = offset within page in shmem file | |
994 | * data_page_index = page number in get_user_pages return | |
995 | * data_page_offset = offset with data_page_index page. | |
996 | * page_length = bytes to copy for this page | |
997 | */ | |
998 | shmem_page_index = offset / PAGE_SIZE; | |
999 | shmem_page_offset = offset & ~PAGE_MASK; | |
1000 | data_page_index = data_ptr / PAGE_SIZE - first_data_page; | |
1001 | data_page_offset = data_ptr & ~PAGE_MASK; | |
1002 | ||
1003 | page_length = remain; | |
1004 | if ((shmem_page_offset + page_length) > PAGE_SIZE) | |
1005 | page_length = PAGE_SIZE - shmem_page_offset; | |
1006 | if ((data_page_offset + page_length) > PAGE_SIZE) | |
1007 | page_length = PAGE_SIZE - data_page_offset; | |
1008 | ||
280b713b | 1009 | if (do_bit17_swizzling) { |
99a03df5 | 1010 | slow_shmem_bit17_copy(obj_priv->pages[shmem_page_index], |
280b713b EA |
1011 | shmem_page_offset, |
1012 | user_pages[data_page_index], | |
1013 | data_page_offset, | |
99a03df5 CW |
1014 | page_length, |
1015 | 0); | |
1016 | } else { | |
1017 | slow_shmem_copy(obj_priv->pages[shmem_page_index], | |
1018 | shmem_page_offset, | |
1019 | user_pages[data_page_index], | |
1020 | data_page_offset, | |
1021 | page_length); | |
280b713b | 1022 | } |
40123c1f EA |
1023 | |
1024 | remain -= page_length; | |
1025 | data_ptr += page_length; | |
1026 | offset += page_length; | |
673a394b EA |
1027 | } |
1028 | ||
40123c1f EA |
1029 | fail_put_pages: |
1030 | i915_gem_object_put_pages(obj); | |
1031 | fail_unlock: | |
673a394b | 1032 | mutex_unlock(&dev->struct_mutex); |
40123c1f EA |
1033 | fail_put_user_pages: |
1034 | for (i = 0; i < pinned_pages; i++) | |
1035 | page_cache_release(user_pages[i]); | |
8e7d2b2c | 1036 | drm_free_large(user_pages); |
673a394b | 1037 | |
40123c1f | 1038 | return ret; |
673a394b EA |
1039 | } |
1040 | ||
1041 | /** | |
1042 | * Writes data to the object referenced by handle. | |
1043 | * | |
1044 | * On error, the contents of the buffer that were to be modified are undefined. | |
1045 | */ | |
1046 | int | |
1047 | i915_gem_pwrite_ioctl(struct drm_device *dev, void *data, | |
1048 | struct drm_file *file_priv) | |
1049 | { | |
1050 | struct drm_i915_gem_pwrite *args = data; | |
1051 | struct drm_gem_object *obj; | |
1052 | struct drm_i915_gem_object *obj_priv; | |
1053 | int ret = 0; | |
1054 | ||
1055 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); | |
1056 | if (obj == NULL) | |
bf79cb91 | 1057 | return -ENOENT; |
23010e43 | 1058 | obj_priv = to_intel_bo(obj); |
673a394b | 1059 | |
7dcd2499 CW |
1060 | /* Bounds check destination. */ |
1061 | if (args->offset > obj->size || args->size > obj->size - args->offset) { | |
ce9d419d | 1062 | ret = -EINVAL; |
35b62a89 | 1063 | goto out; |
ce9d419d CW |
1064 | } |
1065 | ||
35b62a89 CW |
1066 | if (args->size == 0) |
1067 | goto out; | |
1068 | ||
ce9d419d CW |
1069 | if (!access_ok(VERIFY_READ, |
1070 | (char __user *)(uintptr_t)args->data_ptr, | |
1071 | args->size)) { | |
1072 | ret = -EFAULT; | |
35b62a89 | 1073 | goto out; |
673a394b EA |
1074 | } |
1075 | ||
1076 | /* We can only do the GTT pwrite on untiled buffers, as otherwise | |
1077 | * it would end up going through the fenced access, and we'll get | |
1078 | * different detiling behavior between reading and writing. | |
1079 | * pread/pwrite currently are reading and writing from the CPU | |
1080 | * perspective, requiring manual detiling by the client. | |
1081 | */ | |
71acb5eb DA |
1082 | if (obj_priv->phys_obj) |
1083 | ret = i915_gem_phys_pwrite(dev, obj, args, file_priv); | |
1084 | else if (obj_priv->tiling_mode == I915_TILING_NONE && | |
5cdf5881 | 1085 | obj_priv->gtt_space && |
9b8c4a0b | 1086 | obj->write_domain != I915_GEM_DOMAIN_CPU) { |
3de09aa3 EA |
1087 | ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file_priv); |
1088 | if (ret == -EFAULT) { | |
1089 | ret = i915_gem_gtt_pwrite_slow(dev, obj, args, | |
1090 | file_priv); | |
1091 | } | |
280b713b EA |
1092 | } else if (i915_gem_object_needs_bit17_swizzle(obj)) { |
1093 | ret = i915_gem_shmem_pwrite_slow(dev, obj, args, file_priv); | |
40123c1f EA |
1094 | } else { |
1095 | ret = i915_gem_shmem_pwrite_fast(dev, obj, args, file_priv); | |
1096 | if (ret == -EFAULT) { | |
1097 | ret = i915_gem_shmem_pwrite_slow(dev, obj, args, | |
1098 | file_priv); | |
1099 | } | |
1100 | } | |
673a394b EA |
1101 | |
1102 | #if WATCH_PWRITE | |
1103 | if (ret) | |
1104 | DRM_INFO("pwrite failed %d\n", ret); | |
1105 | #endif | |
1106 | ||
35b62a89 | 1107 | out: |
bc9025bd | 1108 | drm_gem_object_unreference_unlocked(obj); |
673a394b EA |
1109 | return ret; |
1110 | } | |
1111 | ||
1112 | /** | |
2ef7eeaa EA |
1113 | * Called when user space prepares to use an object with the CPU, either |
1114 | * through the mmap ioctl's mapping or a GTT mapping. | |
673a394b EA |
1115 | */ |
1116 | int | |
1117 | i915_gem_set_domain_ioctl(struct drm_device *dev, void *data, | |
1118 | struct drm_file *file_priv) | |
1119 | { | |
a09ba7fa | 1120 | struct drm_i915_private *dev_priv = dev->dev_private; |
673a394b EA |
1121 | struct drm_i915_gem_set_domain *args = data; |
1122 | struct drm_gem_object *obj; | |
652c393a | 1123 | struct drm_i915_gem_object *obj_priv; |
2ef7eeaa EA |
1124 | uint32_t read_domains = args->read_domains; |
1125 | uint32_t write_domain = args->write_domain; | |
673a394b EA |
1126 | int ret; |
1127 | ||
1128 | if (!(dev->driver->driver_features & DRIVER_GEM)) | |
1129 | return -ENODEV; | |
1130 | ||
2ef7eeaa | 1131 | /* Only handle setting domains to types used by the CPU. */ |
21d509e3 | 1132 | if (write_domain & I915_GEM_GPU_DOMAINS) |
2ef7eeaa EA |
1133 | return -EINVAL; |
1134 | ||
21d509e3 | 1135 | if (read_domains & I915_GEM_GPU_DOMAINS) |
2ef7eeaa EA |
1136 | return -EINVAL; |
1137 | ||
1138 | /* Having something in the write domain implies it's in the read | |
1139 | * domain, and only that read domain. Enforce that in the request. | |
1140 | */ | |
1141 | if (write_domain != 0 && read_domains != write_domain) | |
1142 | return -EINVAL; | |
1143 | ||
673a394b EA |
1144 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); |
1145 | if (obj == NULL) | |
bf79cb91 | 1146 | return -ENOENT; |
23010e43 | 1147 | obj_priv = to_intel_bo(obj); |
673a394b | 1148 | |
76c1dec1 CW |
1149 | ret = i915_mutex_lock_interruptible(dev); |
1150 | if (ret) { | |
1151 | drm_gem_object_unreference_unlocked(obj); | |
1152 | return ret; | |
1153 | } | |
652c393a JB |
1154 | |
1155 | intel_mark_busy(dev, obj); | |
1156 | ||
2ef7eeaa EA |
1157 | if (read_domains & I915_GEM_DOMAIN_GTT) { |
1158 | ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0); | |
02354392 | 1159 | |
a09ba7fa EA |
1160 | /* Update the LRU on the fence for the CPU access that's |
1161 | * about to occur. | |
1162 | */ | |
1163 | if (obj_priv->fence_reg != I915_FENCE_REG_NONE) { | |
007cc8ac DV |
1164 | struct drm_i915_fence_reg *reg = |
1165 | &dev_priv->fence_regs[obj_priv->fence_reg]; | |
1166 | list_move_tail(®->lru_list, | |
a09ba7fa EA |
1167 | &dev_priv->mm.fence_list); |
1168 | } | |
1169 | ||
02354392 EA |
1170 | /* Silently promote "you're not bound, there was nothing to do" |
1171 | * to success, since the client was just asking us to | |
1172 | * make sure everything was done. | |
1173 | */ | |
1174 | if (ret == -EINVAL) | |
1175 | ret = 0; | |
2ef7eeaa | 1176 | } else { |
e47c68e9 | 1177 | ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0); |
2ef7eeaa EA |
1178 | } |
1179 | ||
7d1c4804 CW |
1180 | /* Maintain LRU order of "inactive" objects */ |
1181 | if (ret == 0 && i915_gem_object_is_inactive(obj_priv)) | |
1182 | list_move_tail(&obj_priv->list, &dev_priv->mm.inactive_list); | |
1183 | ||
673a394b EA |
1184 | drm_gem_object_unreference(obj); |
1185 | mutex_unlock(&dev->struct_mutex); | |
1186 | return ret; | |
1187 | } | |
1188 | ||
1189 | /** | |
1190 | * Called when user space has done writes to this buffer | |
1191 | */ | |
1192 | int | |
1193 | i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data, | |
1194 | struct drm_file *file_priv) | |
1195 | { | |
1196 | struct drm_i915_gem_sw_finish *args = data; | |
1197 | struct drm_gem_object *obj; | |
673a394b EA |
1198 | int ret = 0; |
1199 | ||
1200 | if (!(dev->driver->driver_features & DRIVER_GEM)) | |
1201 | return -ENODEV; | |
1202 | ||
673a394b | 1203 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); |
76c1dec1 | 1204 | if (obj == NULL) |
bf79cb91 | 1205 | return -ENOENT; |
76c1dec1 CW |
1206 | |
1207 | ret = i915_mutex_lock_interruptible(dev); | |
1208 | if (ret) { | |
1209 | drm_gem_object_unreference_unlocked(obj); | |
1210 | return ret; | |
673a394b EA |
1211 | } |
1212 | ||
673a394b | 1213 | /* Pinned buffers may be scanout, so flush the cache */ |
3d2a812a | 1214 | if (to_intel_bo(obj)->pin_count) |
e47c68e9 EA |
1215 | i915_gem_object_flush_cpu_write_domain(obj); |
1216 | ||
673a394b EA |
1217 | drm_gem_object_unreference(obj); |
1218 | mutex_unlock(&dev->struct_mutex); | |
1219 | return ret; | |
1220 | } | |
1221 | ||
1222 | /** | |
1223 | * Maps the contents of an object, returning the address it is mapped | |
1224 | * into. | |
1225 | * | |
1226 | * While the mapping holds a reference on the contents of the object, it doesn't | |
1227 | * imply a ref on the object itself. | |
1228 | */ | |
1229 | int | |
1230 | i915_gem_mmap_ioctl(struct drm_device *dev, void *data, | |
1231 | struct drm_file *file_priv) | |
1232 | { | |
1233 | struct drm_i915_gem_mmap *args = data; | |
1234 | struct drm_gem_object *obj; | |
1235 | loff_t offset; | |
1236 | unsigned long addr; | |
1237 | ||
1238 | if (!(dev->driver->driver_features & DRIVER_GEM)) | |
1239 | return -ENODEV; | |
1240 | ||
1241 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); | |
1242 | if (obj == NULL) | |
bf79cb91 | 1243 | return -ENOENT; |
673a394b EA |
1244 | |
1245 | offset = args->offset; | |
1246 | ||
1247 | down_write(¤t->mm->mmap_sem); | |
1248 | addr = do_mmap(obj->filp, 0, args->size, | |
1249 | PROT_READ | PROT_WRITE, MAP_SHARED, | |
1250 | args->offset); | |
1251 | up_write(¤t->mm->mmap_sem); | |
bc9025bd | 1252 | drm_gem_object_unreference_unlocked(obj); |
673a394b EA |
1253 | if (IS_ERR((void *)addr)) |
1254 | return addr; | |
1255 | ||
1256 | args->addr_ptr = (uint64_t) addr; | |
1257 | ||
1258 | return 0; | |
1259 | } | |
1260 | ||
de151cf6 JB |
1261 | /** |
1262 | * i915_gem_fault - fault a page into the GTT | |
1263 | * vma: VMA in question | |
1264 | * vmf: fault info | |
1265 | * | |
1266 | * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped | |
1267 | * from userspace. The fault handler takes care of binding the object to | |
1268 | * the GTT (if needed), allocating and programming a fence register (again, | |
1269 | * only if needed based on whether the old reg is still valid or the object | |
1270 | * is tiled) and inserting a new PTE into the faulting process. | |
1271 | * | |
1272 | * Note that the faulting process may involve evicting existing objects | |
1273 | * from the GTT and/or fence registers to make room. So performance may | |
1274 | * suffer if the GTT working set is large or there are few fence registers | |
1275 | * left. | |
1276 | */ | |
1277 | int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf) | |
1278 | { | |
1279 | struct drm_gem_object *obj = vma->vm_private_data; | |
1280 | struct drm_device *dev = obj->dev; | |
7d1c4804 | 1281 | drm_i915_private_t *dev_priv = dev->dev_private; |
23010e43 | 1282 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
de151cf6 JB |
1283 | pgoff_t page_offset; |
1284 | unsigned long pfn; | |
1285 | int ret = 0; | |
0f973f27 | 1286 | bool write = !!(vmf->flags & FAULT_FLAG_WRITE); |
de151cf6 JB |
1287 | |
1288 | /* We don't use vmf->pgoff since that has the fake offset */ | |
1289 | page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >> | |
1290 | PAGE_SHIFT; | |
1291 | ||
1292 | /* Now bind it into the GTT if needed */ | |
1293 | mutex_lock(&dev->struct_mutex); | |
1294 | if (!obj_priv->gtt_space) { | |
e67b8ce1 | 1295 | ret = i915_gem_object_bind_to_gtt(obj, 0); |
c715089f CW |
1296 | if (ret) |
1297 | goto unlock; | |
07f4f3e8 | 1298 | |
07f4f3e8 | 1299 | ret = i915_gem_object_set_to_gtt_domain(obj, write); |
c715089f CW |
1300 | if (ret) |
1301 | goto unlock; | |
de151cf6 JB |
1302 | } |
1303 | ||
1304 | /* Need a new fence register? */ | |
a09ba7fa | 1305 | if (obj_priv->tiling_mode != I915_TILING_NONE) { |
2cf34d7b | 1306 | ret = i915_gem_object_get_fence_reg(obj, true); |
c715089f CW |
1307 | if (ret) |
1308 | goto unlock; | |
d9ddcb96 | 1309 | } |
de151cf6 | 1310 | |
7d1c4804 CW |
1311 | if (i915_gem_object_is_inactive(obj_priv)) |
1312 | list_move_tail(&obj_priv->list, &dev_priv->mm.inactive_list); | |
1313 | ||
de151cf6 JB |
1314 | pfn = ((dev->agp->base + obj_priv->gtt_offset) >> PAGE_SHIFT) + |
1315 | page_offset; | |
1316 | ||
1317 | /* Finally, remap it using the new GTT offset */ | |
1318 | ret = vm_insert_pfn(vma, (unsigned long)vmf->virtual_address, pfn); | |
c715089f | 1319 | unlock: |
de151cf6 JB |
1320 | mutex_unlock(&dev->struct_mutex); |
1321 | ||
1322 | switch (ret) { | |
c715089f CW |
1323 | case 0: |
1324 | case -ERESTARTSYS: | |
1325 | return VM_FAULT_NOPAGE; | |
de151cf6 JB |
1326 | case -ENOMEM: |
1327 | case -EAGAIN: | |
1328 | return VM_FAULT_OOM; | |
de151cf6 | 1329 | default: |
c715089f | 1330 | return VM_FAULT_SIGBUS; |
de151cf6 JB |
1331 | } |
1332 | } | |
1333 | ||
1334 | /** | |
1335 | * i915_gem_create_mmap_offset - create a fake mmap offset for an object | |
1336 | * @obj: obj in question | |
1337 | * | |
1338 | * GEM memory mapping works by handing back to userspace a fake mmap offset | |
1339 | * it can use in a subsequent mmap(2) call. The DRM core code then looks | |
1340 | * up the object based on the offset and sets up the various memory mapping | |
1341 | * structures. | |
1342 | * | |
1343 | * This routine allocates and attaches a fake offset for @obj. | |
1344 | */ | |
1345 | static int | |
1346 | i915_gem_create_mmap_offset(struct drm_gem_object *obj) | |
1347 | { | |
1348 | struct drm_device *dev = obj->dev; | |
1349 | struct drm_gem_mm *mm = dev->mm_private; | |
23010e43 | 1350 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
de151cf6 | 1351 | struct drm_map_list *list; |
f77d390c | 1352 | struct drm_local_map *map; |
de151cf6 JB |
1353 | int ret = 0; |
1354 | ||
1355 | /* Set the object up for mmap'ing */ | |
1356 | list = &obj->map_list; | |
9a298b2a | 1357 | list->map = kzalloc(sizeof(struct drm_map_list), GFP_KERNEL); |
de151cf6 JB |
1358 | if (!list->map) |
1359 | return -ENOMEM; | |
1360 | ||
1361 | map = list->map; | |
1362 | map->type = _DRM_GEM; | |
1363 | map->size = obj->size; | |
1364 | map->handle = obj; | |
1365 | ||
1366 | /* Get a DRM GEM mmap offset allocated... */ | |
1367 | list->file_offset_node = drm_mm_search_free(&mm->offset_manager, | |
1368 | obj->size / PAGE_SIZE, 0, 0); | |
1369 | if (!list->file_offset_node) { | |
1370 | DRM_ERROR("failed to allocate offset for bo %d\n", obj->name); | |
9e0ae534 | 1371 | ret = -ENOSPC; |
de151cf6 JB |
1372 | goto out_free_list; |
1373 | } | |
1374 | ||
1375 | list->file_offset_node = drm_mm_get_block(list->file_offset_node, | |
1376 | obj->size / PAGE_SIZE, 0); | |
1377 | if (!list->file_offset_node) { | |
1378 | ret = -ENOMEM; | |
1379 | goto out_free_list; | |
1380 | } | |
1381 | ||
1382 | list->hash.key = list->file_offset_node->start; | |
9e0ae534 CW |
1383 | ret = drm_ht_insert_item(&mm->offset_hash, &list->hash); |
1384 | if (ret) { | |
de151cf6 JB |
1385 | DRM_ERROR("failed to add to map hash\n"); |
1386 | goto out_free_mm; | |
1387 | } | |
1388 | ||
1389 | /* By now we should be all set, any drm_mmap request on the offset | |
1390 | * below will get to our mmap & fault handler */ | |
1391 | obj_priv->mmap_offset = ((uint64_t) list->hash.key) << PAGE_SHIFT; | |
1392 | ||
1393 | return 0; | |
1394 | ||
1395 | out_free_mm: | |
1396 | drm_mm_put_block(list->file_offset_node); | |
1397 | out_free_list: | |
9a298b2a | 1398 | kfree(list->map); |
de151cf6 JB |
1399 | |
1400 | return ret; | |
1401 | } | |
1402 | ||
901782b2 CW |
1403 | /** |
1404 | * i915_gem_release_mmap - remove physical page mappings | |
1405 | * @obj: obj in question | |
1406 | * | |
af901ca1 | 1407 | * Preserve the reservation of the mmapping with the DRM core code, but |
901782b2 CW |
1408 | * relinquish ownership of the pages back to the system. |
1409 | * | |
1410 | * It is vital that we remove the page mapping if we have mapped a tiled | |
1411 | * object through the GTT and then lose the fence register due to | |
1412 | * resource pressure. Similarly if the object has been moved out of the | |
1413 | * aperture, than pages mapped into userspace must be revoked. Removing the | |
1414 | * mapping will then trigger a page fault on the next user access, allowing | |
1415 | * fixup by i915_gem_fault(). | |
1416 | */ | |
d05ca301 | 1417 | void |
901782b2 CW |
1418 | i915_gem_release_mmap(struct drm_gem_object *obj) |
1419 | { | |
1420 | struct drm_device *dev = obj->dev; | |
23010e43 | 1421 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
901782b2 CW |
1422 | |
1423 | if (dev->dev_mapping) | |
1424 | unmap_mapping_range(dev->dev_mapping, | |
1425 | obj_priv->mmap_offset, obj->size, 1); | |
1426 | } | |
1427 | ||
ab00b3e5 JB |
1428 | static void |
1429 | i915_gem_free_mmap_offset(struct drm_gem_object *obj) | |
1430 | { | |
1431 | struct drm_device *dev = obj->dev; | |
23010e43 | 1432 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
ab00b3e5 JB |
1433 | struct drm_gem_mm *mm = dev->mm_private; |
1434 | struct drm_map_list *list; | |
1435 | ||
1436 | list = &obj->map_list; | |
1437 | drm_ht_remove_item(&mm->offset_hash, &list->hash); | |
1438 | ||
1439 | if (list->file_offset_node) { | |
1440 | drm_mm_put_block(list->file_offset_node); | |
1441 | list->file_offset_node = NULL; | |
1442 | } | |
1443 | ||
1444 | if (list->map) { | |
9a298b2a | 1445 | kfree(list->map); |
ab00b3e5 JB |
1446 | list->map = NULL; |
1447 | } | |
1448 | ||
1449 | obj_priv->mmap_offset = 0; | |
1450 | } | |
1451 | ||
de151cf6 JB |
1452 | /** |
1453 | * i915_gem_get_gtt_alignment - return required GTT alignment for an object | |
1454 | * @obj: object to check | |
1455 | * | |
1456 | * Return the required GTT alignment for an object, taking into account | |
1457 | * potential fence register mapping if needed. | |
1458 | */ | |
1459 | static uint32_t | |
1460 | i915_gem_get_gtt_alignment(struct drm_gem_object *obj) | |
1461 | { | |
1462 | struct drm_device *dev = obj->dev; | |
23010e43 | 1463 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
de151cf6 JB |
1464 | int start, i; |
1465 | ||
1466 | /* | |
1467 | * Minimum alignment is 4k (GTT page size), but might be greater | |
1468 | * if a fence register is needed for the object. | |
1469 | */ | |
a6c45cf0 | 1470 | if (INTEL_INFO(dev)->gen >= 4 || obj_priv->tiling_mode == I915_TILING_NONE) |
de151cf6 JB |
1471 | return 4096; |
1472 | ||
1473 | /* | |
1474 | * Previous chips need to be aligned to the size of the smallest | |
1475 | * fence register that can contain the object. | |
1476 | */ | |
a6c45cf0 | 1477 | if (INTEL_INFO(dev)->gen == 3) |
de151cf6 JB |
1478 | start = 1024*1024; |
1479 | else | |
1480 | start = 512*1024; | |
1481 | ||
1482 | for (i = start; i < obj->size; i <<= 1) | |
1483 | ; | |
1484 | ||
1485 | return i; | |
1486 | } | |
1487 | ||
1488 | /** | |
1489 | * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing | |
1490 | * @dev: DRM device | |
1491 | * @data: GTT mapping ioctl data | |
1492 | * @file_priv: GEM object info | |
1493 | * | |
1494 | * Simply returns the fake offset to userspace so it can mmap it. | |
1495 | * The mmap call will end up in drm_gem_mmap(), which will set things | |
1496 | * up so we can get faults in the handler above. | |
1497 | * | |
1498 | * The fault handler will take care of binding the object into the GTT | |
1499 | * (since it may have been evicted to make room for something), allocating | |
1500 | * a fence register, and mapping the appropriate aperture address into | |
1501 | * userspace. | |
1502 | */ | |
1503 | int | |
1504 | i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data, | |
1505 | struct drm_file *file_priv) | |
1506 | { | |
1507 | struct drm_i915_gem_mmap_gtt *args = data; | |
de151cf6 JB |
1508 | struct drm_gem_object *obj; |
1509 | struct drm_i915_gem_object *obj_priv; | |
1510 | int ret; | |
1511 | ||
1512 | if (!(dev->driver->driver_features & DRIVER_GEM)) | |
1513 | return -ENODEV; | |
1514 | ||
1515 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); | |
1516 | if (obj == NULL) | |
bf79cb91 | 1517 | return -ENOENT; |
de151cf6 | 1518 | |
76c1dec1 CW |
1519 | ret = i915_mutex_lock_interruptible(dev); |
1520 | if (ret) { | |
1521 | drm_gem_object_unreference_unlocked(obj); | |
1522 | return ret; | |
1523 | } | |
de151cf6 | 1524 | |
23010e43 | 1525 | obj_priv = to_intel_bo(obj); |
de151cf6 | 1526 | |
ab18282d CW |
1527 | if (obj_priv->madv != I915_MADV_WILLNEED) { |
1528 | DRM_ERROR("Attempting to mmap a purgeable buffer\n"); | |
1529 | drm_gem_object_unreference(obj); | |
1530 | mutex_unlock(&dev->struct_mutex); | |
1531 | return -EINVAL; | |
1532 | } | |
1533 | ||
1534 | ||
de151cf6 JB |
1535 | if (!obj_priv->mmap_offset) { |
1536 | ret = i915_gem_create_mmap_offset(obj); | |
13af1062 CW |
1537 | if (ret) { |
1538 | drm_gem_object_unreference(obj); | |
1539 | mutex_unlock(&dev->struct_mutex); | |
de151cf6 | 1540 | return ret; |
13af1062 | 1541 | } |
de151cf6 JB |
1542 | } |
1543 | ||
1544 | args->offset = obj_priv->mmap_offset; | |
1545 | ||
de151cf6 JB |
1546 | /* |
1547 | * Pull it into the GTT so that we have a page list (makes the | |
1548 | * initial fault faster and any subsequent flushing possible). | |
1549 | */ | |
1550 | if (!obj_priv->agp_mem) { | |
e67b8ce1 | 1551 | ret = i915_gem_object_bind_to_gtt(obj, 0); |
de151cf6 JB |
1552 | if (ret) { |
1553 | drm_gem_object_unreference(obj); | |
1554 | mutex_unlock(&dev->struct_mutex); | |
1555 | return ret; | |
1556 | } | |
de151cf6 JB |
1557 | } |
1558 | ||
1559 | drm_gem_object_unreference(obj); | |
1560 | mutex_unlock(&dev->struct_mutex); | |
1561 | ||
1562 | return 0; | |
1563 | } | |
1564 | ||
5cdf5881 | 1565 | static void |
856fa198 | 1566 | i915_gem_object_put_pages(struct drm_gem_object *obj) |
673a394b | 1567 | { |
23010e43 | 1568 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
673a394b EA |
1569 | int page_count = obj->size / PAGE_SIZE; |
1570 | int i; | |
1571 | ||
856fa198 | 1572 | BUG_ON(obj_priv->pages_refcount == 0); |
bb6baf76 | 1573 | BUG_ON(obj_priv->madv == __I915_MADV_PURGED); |
673a394b | 1574 | |
856fa198 EA |
1575 | if (--obj_priv->pages_refcount != 0) |
1576 | return; | |
673a394b | 1577 | |
280b713b EA |
1578 | if (obj_priv->tiling_mode != I915_TILING_NONE) |
1579 | i915_gem_object_save_bit_17_swizzle(obj); | |
1580 | ||
3ef94daa | 1581 | if (obj_priv->madv == I915_MADV_DONTNEED) |
13a05fd9 | 1582 | obj_priv->dirty = 0; |
3ef94daa CW |
1583 | |
1584 | for (i = 0; i < page_count; i++) { | |
3ef94daa CW |
1585 | if (obj_priv->dirty) |
1586 | set_page_dirty(obj_priv->pages[i]); | |
1587 | ||
1588 | if (obj_priv->madv == I915_MADV_WILLNEED) | |
856fa198 | 1589 | mark_page_accessed(obj_priv->pages[i]); |
3ef94daa CW |
1590 | |
1591 | page_cache_release(obj_priv->pages[i]); | |
1592 | } | |
673a394b EA |
1593 | obj_priv->dirty = 0; |
1594 | ||
8e7d2b2c | 1595 | drm_free_large(obj_priv->pages); |
856fa198 | 1596 | obj_priv->pages = NULL; |
673a394b EA |
1597 | } |
1598 | ||
a56ba56c CW |
1599 | static uint32_t |
1600 | i915_gem_next_request_seqno(struct drm_device *dev, | |
1601 | struct intel_ring_buffer *ring) | |
1602 | { | |
1603 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1604 | ||
1605 | ring->outstanding_lazy_request = true; | |
1606 | return dev_priv->next_seqno; | |
1607 | } | |
1608 | ||
673a394b | 1609 | static void |
617dbe27 | 1610 | i915_gem_object_move_to_active(struct drm_gem_object *obj, |
852835f3 | 1611 | struct intel_ring_buffer *ring) |
673a394b | 1612 | { |
a56ba56c | 1613 | struct drm_device *dev = obj->dev; |
23010e43 | 1614 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
a56ba56c | 1615 | uint32_t seqno = i915_gem_next_request_seqno(dev, ring); |
617dbe27 | 1616 | |
852835f3 ZN |
1617 | BUG_ON(ring == NULL); |
1618 | obj_priv->ring = ring; | |
673a394b EA |
1619 | |
1620 | /* Add a reference if we're newly entering the active list. */ | |
1621 | if (!obj_priv->active) { | |
1622 | drm_gem_object_reference(obj); | |
1623 | obj_priv->active = 1; | |
1624 | } | |
e35a41de | 1625 | |
673a394b | 1626 | /* Move from whatever list we were on to the tail of execution. */ |
852835f3 | 1627 | list_move_tail(&obj_priv->list, &ring->active_list); |
a56ba56c | 1628 | obj_priv->last_rendering_seqno = seqno; |
673a394b EA |
1629 | } |
1630 | ||
ce44b0ea EA |
1631 | static void |
1632 | i915_gem_object_move_to_flushing(struct drm_gem_object *obj) | |
1633 | { | |
1634 | struct drm_device *dev = obj->dev; | |
1635 | drm_i915_private_t *dev_priv = dev->dev_private; | |
23010e43 | 1636 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
ce44b0ea EA |
1637 | |
1638 | BUG_ON(!obj_priv->active); | |
1639 | list_move_tail(&obj_priv->list, &dev_priv->mm.flushing_list); | |
1640 | obj_priv->last_rendering_seqno = 0; | |
1641 | } | |
673a394b | 1642 | |
963b4836 CW |
1643 | /* Immediately discard the backing storage */ |
1644 | static void | |
1645 | i915_gem_object_truncate(struct drm_gem_object *obj) | |
1646 | { | |
23010e43 | 1647 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
bb6baf76 | 1648 | struct inode *inode; |
963b4836 | 1649 | |
ae9fed6b CW |
1650 | /* Our goal here is to return as much of the memory as |
1651 | * is possible back to the system as we are called from OOM. | |
1652 | * To do this we must instruct the shmfs to drop all of its | |
1653 | * backing pages, *now*. Here we mirror the actions taken | |
1654 | * when by shmem_delete_inode() to release the backing store. | |
1655 | */ | |
bb6baf76 | 1656 | inode = obj->filp->f_path.dentry->d_inode; |
ae9fed6b CW |
1657 | truncate_inode_pages(inode->i_mapping, 0); |
1658 | if (inode->i_op->truncate_range) | |
1659 | inode->i_op->truncate_range(inode, 0, (loff_t)-1); | |
bb6baf76 CW |
1660 | |
1661 | obj_priv->madv = __I915_MADV_PURGED; | |
963b4836 CW |
1662 | } |
1663 | ||
1664 | static inline int | |
1665 | i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj_priv) | |
1666 | { | |
1667 | return obj_priv->madv == I915_MADV_DONTNEED; | |
1668 | } | |
1669 | ||
673a394b EA |
1670 | static void |
1671 | i915_gem_object_move_to_inactive(struct drm_gem_object *obj) | |
1672 | { | |
1673 | struct drm_device *dev = obj->dev; | |
1674 | drm_i915_private_t *dev_priv = dev->dev_private; | |
23010e43 | 1675 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
673a394b | 1676 | |
673a394b | 1677 | if (obj_priv->pin_count != 0) |
f13d3f73 | 1678 | list_move_tail(&obj_priv->list, &dev_priv->mm.pinned_list); |
673a394b EA |
1679 | else |
1680 | list_move_tail(&obj_priv->list, &dev_priv->mm.inactive_list); | |
1681 | ||
99fcb766 DV |
1682 | BUG_ON(!list_empty(&obj_priv->gpu_write_list)); |
1683 | ||
ce44b0ea | 1684 | obj_priv->last_rendering_seqno = 0; |
852835f3 | 1685 | obj_priv->ring = NULL; |
673a394b EA |
1686 | if (obj_priv->active) { |
1687 | obj_priv->active = 0; | |
1688 | drm_gem_object_unreference(obj); | |
1689 | } | |
23bc5982 | 1690 | WARN_ON(i915_verify_lists(dev)); |
673a394b EA |
1691 | } |
1692 | ||
9220434a | 1693 | static void |
63560396 | 1694 | i915_gem_process_flushing_list(struct drm_device *dev, |
8a1a49f9 | 1695 | uint32_t flush_domains, |
852835f3 | 1696 | struct intel_ring_buffer *ring) |
63560396 DV |
1697 | { |
1698 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1699 | struct drm_i915_gem_object *obj_priv, *next; | |
1700 | ||
1701 | list_for_each_entry_safe(obj_priv, next, | |
1702 | &dev_priv->mm.gpu_write_list, | |
1703 | gpu_write_list) { | |
a8089e84 | 1704 | struct drm_gem_object *obj = &obj_priv->base; |
63560396 | 1705 | |
2b6efaa4 CW |
1706 | if (obj->write_domain & flush_domains && |
1707 | obj_priv->ring == ring) { | |
63560396 DV |
1708 | uint32_t old_write_domain = obj->write_domain; |
1709 | ||
1710 | obj->write_domain = 0; | |
1711 | list_del_init(&obj_priv->gpu_write_list); | |
617dbe27 | 1712 | i915_gem_object_move_to_active(obj, ring); |
63560396 DV |
1713 | |
1714 | /* update the fence lru list */ | |
007cc8ac DV |
1715 | if (obj_priv->fence_reg != I915_FENCE_REG_NONE) { |
1716 | struct drm_i915_fence_reg *reg = | |
1717 | &dev_priv->fence_regs[obj_priv->fence_reg]; | |
1718 | list_move_tail(®->lru_list, | |
63560396 | 1719 | &dev_priv->mm.fence_list); |
007cc8ac | 1720 | } |
63560396 DV |
1721 | |
1722 | trace_i915_gem_object_change_domain(obj, | |
1723 | obj->read_domains, | |
1724 | old_write_domain); | |
1725 | } | |
1726 | } | |
1727 | } | |
8187a2b7 | 1728 | |
5a5a0c64 | 1729 | uint32_t |
8a1a49f9 | 1730 | i915_add_request(struct drm_device *dev, |
f787a5f5 | 1731 | struct drm_file *file, |
8dc5d147 | 1732 | struct drm_i915_gem_request *request, |
8a1a49f9 | 1733 | struct intel_ring_buffer *ring) |
673a394b EA |
1734 | { |
1735 | drm_i915_private_t *dev_priv = dev->dev_private; | |
f787a5f5 | 1736 | struct drm_i915_file_private *file_priv = NULL; |
673a394b EA |
1737 | uint32_t seqno; |
1738 | int was_empty; | |
673a394b | 1739 | |
f787a5f5 CW |
1740 | if (file != NULL) |
1741 | file_priv = file->driver_priv; | |
b962442e | 1742 | |
8dc5d147 CW |
1743 | if (request == NULL) { |
1744 | request = kzalloc(sizeof(*request), GFP_KERNEL); | |
1745 | if (request == NULL) | |
1746 | return 0; | |
1747 | } | |
673a394b | 1748 | |
f787a5f5 | 1749 | seqno = ring->add_request(dev, ring, 0); |
a56ba56c | 1750 | ring->outstanding_lazy_request = false; |
673a394b EA |
1751 | |
1752 | request->seqno = seqno; | |
852835f3 | 1753 | request->ring = ring; |
673a394b | 1754 | request->emitted_jiffies = jiffies; |
852835f3 ZN |
1755 | was_empty = list_empty(&ring->request_list); |
1756 | list_add_tail(&request->list, &ring->request_list); | |
1757 | ||
f787a5f5 | 1758 | if (file_priv) { |
1c25595f | 1759 | spin_lock(&file_priv->mm.lock); |
f787a5f5 | 1760 | request->file_priv = file_priv; |
b962442e | 1761 | list_add_tail(&request->client_list, |
f787a5f5 | 1762 | &file_priv->mm.request_list); |
1c25595f | 1763 | spin_unlock(&file_priv->mm.lock); |
b962442e | 1764 | } |
673a394b | 1765 | |
f65d9421 | 1766 | if (!dev_priv->mm.suspended) { |
b3b079db CW |
1767 | mod_timer(&dev_priv->hangcheck_timer, |
1768 | jiffies + msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)); | |
f65d9421 | 1769 | if (was_empty) |
b3b079db CW |
1770 | queue_delayed_work(dev_priv->wq, |
1771 | &dev_priv->mm.retire_work, HZ); | |
f65d9421 | 1772 | } |
673a394b EA |
1773 | return seqno; |
1774 | } | |
1775 | ||
1776 | /** | |
1777 | * Command execution barrier | |
1778 | * | |
1779 | * Ensures that all commands in the ring are finished | |
1780 | * before signalling the CPU | |
1781 | */ | |
8a1a49f9 | 1782 | static void |
852835f3 | 1783 | i915_retire_commands(struct drm_device *dev, struct intel_ring_buffer *ring) |
673a394b | 1784 | { |
673a394b | 1785 | uint32_t flush_domains = 0; |
673a394b EA |
1786 | |
1787 | /* The sampler always gets flushed on i965 (sigh) */ | |
a6c45cf0 | 1788 | if (INTEL_INFO(dev)->gen >= 4) |
673a394b | 1789 | flush_domains |= I915_GEM_DOMAIN_SAMPLER; |
852835f3 ZN |
1790 | |
1791 | ring->flush(dev, ring, | |
1792 | I915_GEM_DOMAIN_COMMAND, flush_domains); | |
673a394b EA |
1793 | } |
1794 | ||
f787a5f5 CW |
1795 | static inline void |
1796 | i915_gem_request_remove_from_client(struct drm_i915_gem_request *request) | |
673a394b | 1797 | { |
1c25595f CW |
1798 | struct drm_i915_file_private *file_priv = request->file_priv; |
1799 | ||
1800 | if (!file_priv) | |
1801 | return; | |
1802 | ||
1803 | spin_lock(&file_priv->mm.lock); | |
1804 | list_del(&request->client_list); | |
1805 | request->file_priv = NULL; | |
1806 | spin_unlock(&file_priv->mm.lock); | |
673a394b EA |
1807 | } |
1808 | ||
dfaae392 CW |
1809 | static void i915_gem_reset_ring_lists(struct drm_i915_private *dev_priv, |
1810 | struct intel_ring_buffer *ring) | |
9375e446 | 1811 | { |
dfaae392 CW |
1812 | while (!list_empty(&ring->request_list)) { |
1813 | struct drm_i915_gem_request *request; | |
9375e446 | 1814 | |
dfaae392 CW |
1815 | request = list_first_entry(&ring->request_list, |
1816 | struct drm_i915_gem_request, | |
1817 | list); | |
1818 | ||
1819 | list_del(&request->list); | |
f787a5f5 | 1820 | i915_gem_request_remove_from_client(request); |
dfaae392 CW |
1821 | kfree(request); |
1822 | } | |
1823 | ||
1824 | while (!list_empty(&ring->active_list)) { | |
9375e446 CW |
1825 | struct drm_i915_gem_object *obj_priv; |
1826 | ||
dfaae392 | 1827 | obj_priv = list_first_entry(&ring->active_list, |
9375e446 CW |
1828 | struct drm_i915_gem_object, |
1829 | list); | |
1830 | ||
1831 | obj_priv->base.write_domain = 0; | |
dfaae392 | 1832 | list_del_init(&obj_priv->gpu_write_list); |
9375e446 CW |
1833 | i915_gem_object_move_to_inactive(&obj_priv->base); |
1834 | } | |
1835 | } | |
1836 | ||
069efc1d | 1837 | void i915_gem_reset(struct drm_device *dev) |
77f01230 CW |
1838 | { |
1839 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1840 | struct drm_i915_gem_object *obj_priv; | |
069efc1d | 1841 | int i; |
77f01230 | 1842 | |
dfaae392 CW |
1843 | i915_gem_reset_ring_lists(dev_priv, &dev_priv->render_ring); |
1844 | if (HAS_BSD(dev)) | |
1845 | i915_gem_reset_ring_lists(dev_priv, &dev_priv->bsd_ring); | |
1846 | ||
1847 | /* Remove anything from the flushing lists. The GPU cache is likely | |
1848 | * to be lost on reset along with the data, so simply move the | |
1849 | * lost bo to the inactive list. | |
1850 | */ | |
1851 | while (!list_empty(&dev_priv->mm.flushing_list)) { | |
1852 | obj_priv = list_first_entry(&dev_priv->mm.flushing_list, | |
1853 | struct drm_i915_gem_object, | |
1854 | list); | |
1855 | ||
1856 | obj_priv->base.write_domain = 0; | |
1857 | list_del_init(&obj_priv->gpu_write_list); | |
1858 | i915_gem_object_move_to_inactive(&obj_priv->base); | |
1859 | } | |
1860 | ||
1861 | /* Move everything out of the GPU domains to ensure we do any | |
1862 | * necessary invalidation upon reuse. | |
1863 | */ | |
77f01230 CW |
1864 | list_for_each_entry(obj_priv, |
1865 | &dev_priv->mm.inactive_list, | |
1866 | list) | |
1867 | { | |
1868 | obj_priv->base.read_domains &= ~I915_GEM_GPU_DOMAINS; | |
1869 | } | |
069efc1d CW |
1870 | |
1871 | /* The fence registers are invalidated so clear them out */ | |
1872 | for (i = 0; i < 16; i++) { | |
1873 | struct drm_i915_fence_reg *reg; | |
1874 | ||
1875 | reg = &dev_priv->fence_regs[i]; | |
1876 | if (!reg->obj) | |
1877 | continue; | |
1878 | ||
1879 | i915_gem_clear_fence_reg(reg->obj); | |
1880 | } | |
77f01230 CW |
1881 | } |
1882 | ||
673a394b EA |
1883 | /** |
1884 | * This function clears the request list as sequence numbers are passed. | |
1885 | */ | |
b09a1fec CW |
1886 | static void |
1887 | i915_gem_retire_requests_ring(struct drm_device *dev, | |
1888 | struct intel_ring_buffer *ring) | |
673a394b EA |
1889 | { |
1890 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1891 | uint32_t seqno; | |
1892 | ||
b84d5f0c CW |
1893 | if (!ring->status_page.page_addr || |
1894 | list_empty(&ring->request_list)) | |
6c0594a3 KW |
1895 | return; |
1896 | ||
23bc5982 CW |
1897 | WARN_ON(i915_verify_lists(dev)); |
1898 | ||
f787a5f5 | 1899 | seqno = ring->get_seqno(dev, ring); |
852835f3 | 1900 | while (!list_empty(&ring->request_list)) { |
673a394b | 1901 | struct drm_i915_gem_request *request; |
673a394b | 1902 | |
852835f3 | 1903 | request = list_first_entry(&ring->request_list, |
673a394b EA |
1904 | struct drm_i915_gem_request, |
1905 | list); | |
673a394b | 1906 | |
dfaae392 | 1907 | if (!i915_seqno_passed(seqno, request->seqno)) |
b84d5f0c CW |
1908 | break; |
1909 | ||
1910 | trace_i915_gem_request_retire(dev, request->seqno); | |
1911 | ||
1912 | list_del(&request->list); | |
f787a5f5 | 1913 | i915_gem_request_remove_from_client(request); |
b84d5f0c CW |
1914 | kfree(request); |
1915 | } | |
1916 | ||
1917 | /* Move any buffers on the active list that are no longer referenced | |
1918 | * by the ringbuffer to the flushing/inactive lists as appropriate. | |
1919 | */ | |
1920 | while (!list_empty(&ring->active_list)) { | |
1921 | struct drm_gem_object *obj; | |
1922 | struct drm_i915_gem_object *obj_priv; | |
1923 | ||
1924 | obj_priv = list_first_entry(&ring->active_list, | |
1925 | struct drm_i915_gem_object, | |
1926 | list); | |
673a394b | 1927 | |
dfaae392 | 1928 | if (!i915_seqno_passed(seqno, obj_priv->last_rendering_seqno)) |
673a394b | 1929 | break; |
b84d5f0c CW |
1930 | |
1931 | obj = &obj_priv->base; | |
b84d5f0c CW |
1932 | if (obj->write_domain != 0) |
1933 | i915_gem_object_move_to_flushing(obj); | |
1934 | else | |
1935 | i915_gem_object_move_to_inactive(obj); | |
673a394b | 1936 | } |
9d34e5db CW |
1937 | |
1938 | if (unlikely (dev_priv->trace_irq_seqno && | |
1939 | i915_seqno_passed(dev_priv->trace_irq_seqno, seqno))) { | |
8187a2b7 | 1940 | ring->user_irq_put(dev, ring); |
9d34e5db CW |
1941 | dev_priv->trace_irq_seqno = 0; |
1942 | } | |
23bc5982 CW |
1943 | |
1944 | WARN_ON(i915_verify_lists(dev)); | |
673a394b EA |
1945 | } |
1946 | ||
b09a1fec CW |
1947 | void |
1948 | i915_gem_retire_requests(struct drm_device *dev) | |
1949 | { | |
1950 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1951 | ||
be72615b CW |
1952 | if (!list_empty(&dev_priv->mm.deferred_free_list)) { |
1953 | struct drm_i915_gem_object *obj_priv, *tmp; | |
1954 | ||
1955 | /* We must be careful that during unbind() we do not | |
1956 | * accidentally infinitely recurse into retire requests. | |
1957 | * Currently: | |
1958 | * retire -> free -> unbind -> wait -> retire_ring | |
1959 | */ | |
1960 | list_for_each_entry_safe(obj_priv, tmp, | |
1961 | &dev_priv->mm.deferred_free_list, | |
1962 | list) | |
1963 | i915_gem_free_object_tail(&obj_priv->base); | |
1964 | } | |
1965 | ||
b09a1fec CW |
1966 | i915_gem_retire_requests_ring(dev, &dev_priv->render_ring); |
1967 | if (HAS_BSD(dev)) | |
1968 | i915_gem_retire_requests_ring(dev, &dev_priv->bsd_ring); | |
1969 | } | |
1970 | ||
75ef9da2 | 1971 | static void |
673a394b EA |
1972 | i915_gem_retire_work_handler(struct work_struct *work) |
1973 | { | |
1974 | drm_i915_private_t *dev_priv; | |
1975 | struct drm_device *dev; | |
1976 | ||
1977 | dev_priv = container_of(work, drm_i915_private_t, | |
1978 | mm.retire_work.work); | |
1979 | dev = dev_priv->dev; | |
1980 | ||
891b48cf CW |
1981 | /* Come back later if the device is busy... */ |
1982 | if (!mutex_trylock(&dev->struct_mutex)) { | |
1983 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ); | |
1984 | return; | |
1985 | } | |
1986 | ||
b09a1fec | 1987 | i915_gem_retire_requests(dev); |
d1b851fc | 1988 | |
6dbe2772 | 1989 | if (!dev_priv->mm.suspended && |
d1b851fc ZN |
1990 | (!list_empty(&dev_priv->render_ring.request_list) || |
1991 | (HAS_BSD(dev) && | |
1992 | !list_empty(&dev_priv->bsd_ring.request_list)))) | |
9c9fe1f8 | 1993 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ); |
673a394b EA |
1994 | mutex_unlock(&dev->struct_mutex); |
1995 | } | |
1996 | ||
5a5a0c64 | 1997 | int |
852835f3 | 1998 | i915_do_wait_request(struct drm_device *dev, uint32_t seqno, |
8a1a49f9 | 1999 | bool interruptible, struct intel_ring_buffer *ring) |
673a394b EA |
2000 | { |
2001 | drm_i915_private_t *dev_priv = dev->dev_private; | |
802c7eb6 | 2002 | u32 ier; |
673a394b EA |
2003 | int ret = 0; |
2004 | ||
2005 | BUG_ON(seqno == 0); | |
2006 | ||
30dbf0c0 CW |
2007 | if (atomic_read(&dev_priv->mm.wedged)) |
2008 | return -EAGAIN; | |
2009 | ||
a56ba56c | 2010 | if (ring->outstanding_lazy_request) { |
8dc5d147 | 2011 | seqno = i915_add_request(dev, NULL, NULL, ring); |
e35a41de DV |
2012 | if (seqno == 0) |
2013 | return -ENOMEM; | |
2014 | } | |
a56ba56c | 2015 | BUG_ON(seqno == dev_priv->next_seqno); |
e35a41de | 2016 | |
f787a5f5 | 2017 | if (!i915_seqno_passed(ring->get_seqno(dev, ring), seqno)) { |
bad720ff | 2018 | if (HAS_PCH_SPLIT(dev)) |
036a4a7d ZW |
2019 | ier = I915_READ(DEIER) | I915_READ(GTIER); |
2020 | else | |
2021 | ier = I915_READ(IER); | |
802c7eb6 JB |
2022 | if (!ier) { |
2023 | DRM_ERROR("something (likely vbetool) disabled " | |
2024 | "interrupts, re-enabling\n"); | |
2025 | i915_driver_irq_preinstall(dev); | |
2026 | i915_driver_irq_postinstall(dev); | |
2027 | } | |
2028 | ||
1c5d22f7 CW |
2029 | trace_i915_gem_request_wait_begin(dev, seqno); |
2030 | ||
852835f3 | 2031 | ring->waiting_gem_seqno = seqno; |
8187a2b7 | 2032 | ring->user_irq_get(dev, ring); |
48764bf4 | 2033 | if (interruptible) |
852835f3 ZN |
2034 | ret = wait_event_interruptible(ring->irq_queue, |
2035 | i915_seqno_passed( | |
f787a5f5 | 2036 | ring->get_seqno(dev, ring), seqno) |
852835f3 | 2037 | || atomic_read(&dev_priv->mm.wedged)); |
48764bf4 | 2038 | else |
852835f3 ZN |
2039 | wait_event(ring->irq_queue, |
2040 | i915_seqno_passed( | |
f787a5f5 | 2041 | ring->get_seqno(dev, ring), seqno) |
852835f3 | 2042 | || atomic_read(&dev_priv->mm.wedged)); |
48764bf4 | 2043 | |
8187a2b7 | 2044 | ring->user_irq_put(dev, ring); |
852835f3 | 2045 | ring->waiting_gem_seqno = 0; |
1c5d22f7 CW |
2046 | |
2047 | trace_i915_gem_request_wait_end(dev, seqno); | |
673a394b | 2048 | } |
ba1234d1 | 2049 | if (atomic_read(&dev_priv->mm.wedged)) |
30dbf0c0 | 2050 | ret = -EAGAIN; |
673a394b EA |
2051 | |
2052 | if (ret && ret != -ERESTARTSYS) | |
8bff917c | 2053 | DRM_ERROR("%s returns %d (awaiting %d at %d, next %d)\n", |
f787a5f5 | 2054 | __func__, ret, seqno, ring->get_seqno(dev, ring), |
8bff917c | 2055 | dev_priv->next_seqno); |
673a394b EA |
2056 | |
2057 | /* Directly dispatch request retiring. While we have the work queue | |
2058 | * to handle this, the waiter on a request often wants an associated | |
2059 | * buffer to have made it to the inactive list, and we would need | |
2060 | * a separate wait queue to handle that. | |
2061 | */ | |
2062 | if (ret == 0) | |
b09a1fec | 2063 | i915_gem_retire_requests_ring(dev, ring); |
673a394b EA |
2064 | |
2065 | return ret; | |
2066 | } | |
2067 | ||
48764bf4 DV |
2068 | /** |
2069 | * Waits for a sequence number to be signaled, and cleans up the | |
2070 | * request and object lists appropriately for that event. | |
2071 | */ | |
2072 | static int | |
852835f3 | 2073 | i915_wait_request(struct drm_device *dev, uint32_t seqno, |
a56ba56c | 2074 | struct intel_ring_buffer *ring) |
48764bf4 | 2075 | { |
852835f3 | 2076 | return i915_do_wait_request(dev, seqno, 1, ring); |
48764bf4 DV |
2077 | } |
2078 | ||
20f0cd55 | 2079 | static void |
9220434a | 2080 | i915_gem_flush_ring(struct drm_device *dev, |
c78ec30b | 2081 | struct drm_file *file_priv, |
9220434a CW |
2082 | struct intel_ring_buffer *ring, |
2083 | uint32_t invalidate_domains, | |
2084 | uint32_t flush_domains) | |
2085 | { | |
2086 | ring->flush(dev, ring, invalidate_domains, flush_domains); | |
2087 | i915_gem_process_flushing_list(dev, flush_domains, ring); | |
2088 | } | |
2089 | ||
8187a2b7 ZN |
2090 | static void |
2091 | i915_gem_flush(struct drm_device *dev, | |
c78ec30b | 2092 | struct drm_file *file_priv, |
8187a2b7 | 2093 | uint32_t invalidate_domains, |
9220434a CW |
2094 | uint32_t flush_domains, |
2095 | uint32_t flush_rings) | |
8187a2b7 ZN |
2096 | { |
2097 | drm_i915_private_t *dev_priv = dev->dev_private; | |
8bff917c | 2098 | |
8187a2b7 ZN |
2099 | if (flush_domains & I915_GEM_DOMAIN_CPU) |
2100 | drm_agp_chipset_flush(dev); | |
8bff917c | 2101 | |
9220434a CW |
2102 | if ((flush_domains | invalidate_domains) & I915_GEM_GPU_DOMAINS) { |
2103 | if (flush_rings & RING_RENDER) | |
c78ec30b | 2104 | i915_gem_flush_ring(dev, file_priv, |
9220434a CW |
2105 | &dev_priv->render_ring, |
2106 | invalidate_domains, flush_domains); | |
2107 | if (flush_rings & RING_BSD) | |
c78ec30b | 2108 | i915_gem_flush_ring(dev, file_priv, |
9220434a CW |
2109 | &dev_priv->bsd_ring, |
2110 | invalidate_domains, flush_domains); | |
2111 | } | |
8187a2b7 ZN |
2112 | } |
2113 | ||
673a394b EA |
2114 | /** |
2115 | * Ensures that all rendering to the object has completed and the object is | |
2116 | * safe to unbind from the GTT or access from the CPU. | |
2117 | */ | |
2118 | static int | |
2cf34d7b CW |
2119 | i915_gem_object_wait_rendering(struct drm_gem_object *obj, |
2120 | bool interruptible) | |
673a394b EA |
2121 | { |
2122 | struct drm_device *dev = obj->dev; | |
23010e43 | 2123 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
673a394b EA |
2124 | int ret; |
2125 | ||
e47c68e9 EA |
2126 | /* This function only exists to support waiting for existing rendering, |
2127 | * not for emitting required flushes. | |
673a394b | 2128 | */ |
e47c68e9 | 2129 | BUG_ON((obj->write_domain & I915_GEM_GPU_DOMAINS) != 0); |
673a394b EA |
2130 | |
2131 | /* If there is rendering queued on the buffer being evicted, wait for | |
2132 | * it. | |
2133 | */ | |
2134 | if (obj_priv->active) { | |
2cf34d7b CW |
2135 | ret = i915_do_wait_request(dev, |
2136 | obj_priv->last_rendering_seqno, | |
2137 | interruptible, | |
2138 | obj_priv->ring); | |
2139 | if (ret) | |
673a394b EA |
2140 | return ret; |
2141 | } | |
2142 | ||
2143 | return 0; | |
2144 | } | |
2145 | ||
2146 | /** | |
2147 | * Unbinds an object from the GTT aperture. | |
2148 | */ | |
0f973f27 | 2149 | int |
673a394b EA |
2150 | i915_gem_object_unbind(struct drm_gem_object *obj) |
2151 | { | |
2152 | struct drm_device *dev = obj->dev; | |
73aa808f | 2153 | struct drm_i915_private *dev_priv = dev->dev_private; |
23010e43 | 2154 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
673a394b EA |
2155 | int ret = 0; |
2156 | ||
673a394b EA |
2157 | if (obj_priv->gtt_space == NULL) |
2158 | return 0; | |
2159 | ||
2160 | if (obj_priv->pin_count != 0) { | |
2161 | DRM_ERROR("Attempting to unbind pinned buffer\n"); | |
2162 | return -EINVAL; | |
2163 | } | |
2164 | ||
5323fd04 EA |
2165 | /* blow away mappings if mapped through GTT */ |
2166 | i915_gem_release_mmap(obj); | |
2167 | ||
673a394b EA |
2168 | /* Move the object to the CPU domain to ensure that |
2169 | * any possible CPU writes while it's not in the GTT | |
2170 | * are flushed when we go to remap it. This will | |
2171 | * also ensure that all pending GPU writes are finished | |
2172 | * before we unbind. | |
2173 | */ | |
e47c68e9 | 2174 | ret = i915_gem_object_set_to_cpu_domain(obj, 1); |
8dc1775d | 2175 | if (ret == -ERESTARTSYS) |
673a394b | 2176 | return ret; |
8dc1775d CW |
2177 | /* Continue on if we fail due to EIO, the GPU is hung so we |
2178 | * should be safe and we need to cleanup or else we might | |
2179 | * cause memory corruption through use-after-free. | |
2180 | */ | |
812ed492 CW |
2181 | if (ret) { |
2182 | i915_gem_clflush_object(obj); | |
2183 | obj->read_domains = obj->write_domain = I915_GEM_DOMAIN_CPU; | |
2184 | } | |
673a394b | 2185 | |
96b47b65 DV |
2186 | /* release the fence reg _after_ flushing */ |
2187 | if (obj_priv->fence_reg != I915_FENCE_REG_NONE) | |
2188 | i915_gem_clear_fence_reg(obj); | |
2189 | ||
73aa808f CW |
2190 | drm_unbind_agp(obj_priv->agp_mem); |
2191 | drm_free_agp(obj_priv->agp_mem, obj->size / PAGE_SIZE); | |
673a394b | 2192 | |
856fa198 | 2193 | i915_gem_object_put_pages(obj); |
a32808c0 | 2194 | BUG_ON(obj_priv->pages_refcount); |
673a394b | 2195 | |
73aa808f | 2196 | i915_gem_info_remove_gtt(dev_priv, obj->size); |
f13d3f73 | 2197 | list_del_init(&obj_priv->list); |
673a394b | 2198 | |
73aa808f CW |
2199 | drm_mm_put_block(obj_priv->gtt_space); |
2200 | obj_priv->gtt_space = NULL; | |
2201 | ||
963b4836 CW |
2202 | if (i915_gem_object_is_purgeable(obj_priv)) |
2203 | i915_gem_object_truncate(obj); | |
2204 | ||
1c5d22f7 CW |
2205 | trace_i915_gem_object_unbind(obj); |
2206 | ||
8dc1775d | 2207 | return ret; |
673a394b EA |
2208 | } |
2209 | ||
a56ba56c CW |
2210 | static int i915_ring_idle(struct drm_device *dev, |
2211 | struct intel_ring_buffer *ring) | |
2212 | { | |
2213 | i915_gem_flush_ring(dev, NULL, ring, | |
2214 | I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS); | |
2215 | return i915_wait_request(dev, | |
2216 | i915_gem_next_request_seqno(dev, ring), | |
2217 | ring); | |
2218 | } | |
2219 | ||
b47eb4a2 | 2220 | int |
4df2faf4 DV |
2221 | i915_gpu_idle(struct drm_device *dev) |
2222 | { | |
2223 | drm_i915_private_t *dev_priv = dev->dev_private; | |
2224 | bool lists_empty; | |
852835f3 | 2225 | int ret; |
4df2faf4 | 2226 | |
d1b851fc ZN |
2227 | lists_empty = (list_empty(&dev_priv->mm.flushing_list) && |
2228 | list_empty(&dev_priv->render_ring.active_list) && | |
2229 | (!HAS_BSD(dev) || | |
2230 | list_empty(&dev_priv->bsd_ring.active_list))); | |
4df2faf4 DV |
2231 | if (lists_empty) |
2232 | return 0; | |
2233 | ||
2234 | /* Flush everything onto the inactive list. */ | |
a56ba56c | 2235 | ret = i915_ring_idle(dev, &dev_priv->render_ring); |
8a1a49f9 DV |
2236 | if (ret) |
2237 | return ret; | |
d1b851fc ZN |
2238 | |
2239 | if (HAS_BSD(dev)) { | |
a56ba56c | 2240 | ret = i915_ring_idle(dev, &dev_priv->bsd_ring); |
d1b851fc ZN |
2241 | if (ret) |
2242 | return ret; | |
2243 | } | |
2244 | ||
8a1a49f9 | 2245 | return 0; |
4df2faf4 DV |
2246 | } |
2247 | ||
5cdf5881 | 2248 | static int |
4bdadb97 CW |
2249 | i915_gem_object_get_pages(struct drm_gem_object *obj, |
2250 | gfp_t gfpmask) | |
673a394b | 2251 | { |
23010e43 | 2252 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
673a394b EA |
2253 | int page_count, i; |
2254 | struct address_space *mapping; | |
2255 | struct inode *inode; | |
2256 | struct page *page; | |
673a394b | 2257 | |
778c3544 DV |
2258 | BUG_ON(obj_priv->pages_refcount |
2259 | == DRM_I915_GEM_OBJECT_MAX_PAGES_REFCOUNT); | |
2260 | ||
856fa198 | 2261 | if (obj_priv->pages_refcount++ != 0) |
673a394b EA |
2262 | return 0; |
2263 | ||
2264 | /* Get the list of pages out of our struct file. They'll be pinned | |
2265 | * at this point until we release them. | |
2266 | */ | |
2267 | page_count = obj->size / PAGE_SIZE; | |
856fa198 | 2268 | BUG_ON(obj_priv->pages != NULL); |
8e7d2b2c | 2269 | obj_priv->pages = drm_calloc_large(page_count, sizeof(struct page *)); |
856fa198 | 2270 | if (obj_priv->pages == NULL) { |
856fa198 | 2271 | obj_priv->pages_refcount--; |
673a394b EA |
2272 | return -ENOMEM; |
2273 | } | |
2274 | ||
2275 | inode = obj->filp->f_path.dentry->d_inode; | |
2276 | mapping = inode->i_mapping; | |
2277 | for (i = 0; i < page_count; i++) { | |
4bdadb97 | 2278 | page = read_cache_page_gfp(mapping, i, |
985b823b | 2279 | GFP_HIGHUSER | |
4bdadb97 | 2280 | __GFP_COLD | |
cd9f040d | 2281 | __GFP_RECLAIMABLE | |
4bdadb97 | 2282 | gfpmask); |
1f2b1013 CW |
2283 | if (IS_ERR(page)) |
2284 | goto err_pages; | |
2285 | ||
856fa198 | 2286 | obj_priv->pages[i] = page; |
673a394b | 2287 | } |
280b713b EA |
2288 | |
2289 | if (obj_priv->tiling_mode != I915_TILING_NONE) | |
2290 | i915_gem_object_do_bit_17_swizzle(obj); | |
2291 | ||
673a394b | 2292 | return 0; |
1f2b1013 CW |
2293 | |
2294 | err_pages: | |
2295 | while (i--) | |
2296 | page_cache_release(obj_priv->pages[i]); | |
2297 | ||
2298 | drm_free_large(obj_priv->pages); | |
2299 | obj_priv->pages = NULL; | |
2300 | obj_priv->pages_refcount--; | |
2301 | return PTR_ERR(page); | |
673a394b EA |
2302 | } |
2303 | ||
4e901fdc EA |
2304 | static void sandybridge_write_fence_reg(struct drm_i915_fence_reg *reg) |
2305 | { | |
2306 | struct drm_gem_object *obj = reg->obj; | |
2307 | struct drm_device *dev = obj->dev; | |
2308 | drm_i915_private_t *dev_priv = dev->dev_private; | |
23010e43 | 2309 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
4e901fdc EA |
2310 | int regnum = obj_priv->fence_reg; |
2311 | uint64_t val; | |
2312 | ||
2313 | val = (uint64_t)((obj_priv->gtt_offset + obj->size - 4096) & | |
2314 | 0xfffff000) << 32; | |
2315 | val |= obj_priv->gtt_offset & 0xfffff000; | |
2316 | val |= (uint64_t)((obj_priv->stride / 128) - 1) << | |
2317 | SANDYBRIDGE_FENCE_PITCH_SHIFT; | |
2318 | ||
2319 | if (obj_priv->tiling_mode == I915_TILING_Y) | |
2320 | val |= 1 << I965_FENCE_TILING_Y_SHIFT; | |
2321 | val |= I965_FENCE_REG_VALID; | |
2322 | ||
2323 | I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + (regnum * 8), val); | |
2324 | } | |
2325 | ||
de151cf6 JB |
2326 | static void i965_write_fence_reg(struct drm_i915_fence_reg *reg) |
2327 | { | |
2328 | struct drm_gem_object *obj = reg->obj; | |
2329 | struct drm_device *dev = obj->dev; | |
2330 | drm_i915_private_t *dev_priv = dev->dev_private; | |
23010e43 | 2331 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
de151cf6 JB |
2332 | int regnum = obj_priv->fence_reg; |
2333 | uint64_t val; | |
2334 | ||
2335 | val = (uint64_t)((obj_priv->gtt_offset + obj->size - 4096) & | |
2336 | 0xfffff000) << 32; | |
2337 | val |= obj_priv->gtt_offset & 0xfffff000; | |
2338 | val |= ((obj_priv->stride / 128) - 1) << I965_FENCE_PITCH_SHIFT; | |
2339 | if (obj_priv->tiling_mode == I915_TILING_Y) | |
2340 | val |= 1 << I965_FENCE_TILING_Y_SHIFT; | |
2341 | val |= I965_FENCE_REG_VALID; | |
2342 | ||
2343 | I915_WRITE64(FENCE_REG_965_0 + (regnum * 8), val); | |
2344 | } | |
2345 | ||
2346 | static void i915_write_fence_reg(struct drm_i915_fence_reg *reg) | |
2347 | { | |
2348 | struct drm_gem_object *obj = reg->obj; | |
2349 | struct drm_device *dev = obj->dev; | |
2350 | drm_i915_private_t *dev_priv = dev->dev_private; | |
23010e43 | 2351 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
de151cf6 | 2352 | int regnum = obj_priv->fence_reg; |
0f973f27 | 2353 | int tile_width; |
dc529a4f | 2354 | uint32_t fence_reg, val; |
de151cf6 JB |
2355 | uint32_t pitch_val; |
2356 | ||
2357 | if ((obj_priv->gtt_offset & ~I915_FENCE_START_MASK) || | |
2358 | (obj_priv->gtt_offset & (obj->size - 1))) { | |
f06da264 | 2359 | WARN(1, "%s: object 0x%08x not 1M or size (0x%zx) aligned\n", |
0f973f27 | 2360 | __func__, obj_priv->gtt_offset, obj->size); |
de151cf6 JB |
2361 | return; |
2362 | } | |
2363 | ||
0f973f27 JB |
2364 | if (obj_priv->tiling_mode == I915_TILING_Y && |
2365 | HAS_128_BYTE_Y_TILING(dev)) | |
2366 | tile_width = 128; | |
de151cf6 | 2367 | else |
0f973f27 JB |
2368 | tile_width = 512; |
2369 | ||
2370 | /* Note: pitch better be a power of two tile widths */ | |
2371 | pitch_val = obj_priv->stride / tile_width; | |
2372 | pitch_val = ffs(pitch_val) - 1; | |
de151cf6 | 2373 | |
c36a2a6d DV |
2374 | if (obj_priv->tiling_mode == I915_TILING_Y && |
2375 | HAS_128_BYTE_Y_TILING(dev)) | |
2376 | WARN_ON(pitch_val > I830_FENCE_MAX_PITCH_VAL); | |
2377 | else | |
2378 | WARN_ON(pitch_val > I915_FENCE_MAX_PITCH_VAL); | |
2379 | ||
de151cf6 JB |
2380 | val = obj_priv->gtt_offset; |
2381 | if (obj_priv->tiling_mode == I915_TILING_Y) | |
2382 | val |= 1 << I830_FENCE_TILING_Y_SHIFT; | |
2383 | val |= I915_FENCE_SIZE_BITS(obj->size); | |
2384 | val |= pitch_val << I830_FENCE_PITCH_SHIFT; | |
2385 | val |= I830_FENCE_REG_VALID; | |
2386 | ||
dc529a4f EA |
2387 | if (regnum < 8) |
2388 | fence_reg = FENCE_REG_830_0 + (regnum * 4); | |
2389 | else | |
2390 | fence_reg = FENCE_REG_945_8 + ((regnum - 8) * 4); | |
2391 | I915_WRITE(fence_reg, val); | |
de151cf6 JB |
2392 | } |
2393 | ||
2394 | static void i830_write_fence_reg(struct drm_i915_fence_reg *reg) | |
2395 | { | |
2396 | struct drm_gem_object *obj = reg->obj; | |
2397 | struct drm_device *dev = obj->dev; | |
2398 | drm_i915_private_t *dev_priv = dev->dev_private; | |
23010e43 | 2399 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
de151cf6 JB |
2400 | int regnum = obj_priv->fence_reg; |
2401 | uint32_t val; | |
2402 | uint32_t pitch_val; | |
8d7773a3 | 2403 | uint32_t fence_size_bits; |
de151cf6 | 2404 | |
8d7773a3 | 2405 | if ((obj_priv->gtt_offset & ~I830_FENCE_START_MASK) || |
de151cf6 | 2406 | (obj_priv->gtt_offset & (obj->size - 1))) { |
8d7773a3 | 2407 | WARN(1, "%s: object 0x%08x not 512K or size aligned\n", |
0f973f27 | 2408 | __func__, obj_priv->gtt_offset); |
de151cf6 JB |
2409 | return; |
2410 | } | |
2411 | ||
e76a16de EA |
2412 | pitch_val = obj_priv->stride / 128; |
2413 | pitch_val = ffs(pitch_val) - 1; | |
2414 | WARN_ON(pitch_val > I830_FENCE_MAX_PITCH_VAL); | |
2415 | ||
de151cf6 JB |
2416 | val = obj_priv->gtt_offset; |
2417 | if (obj_priv->tiling_mode == I915_TILING_Y) | |
2418 | val |= 1 << I830_FENCE_TILING_Y_SHIFT; | |
8d7773a3 DV |
2419 | fence_size_bits = I830_FENCE_SIZE_BITS(obj->size); |
2420 | WARN_ON(fence_size_bits & ~0x00000f00); | |
2421 | val |= fence_size_bits; | |
de151cf6 JB |
2422 | val |= pitch_val << I830_FENCE_PITCH_SHIFT; |
2423 | val |= I830_FENCE_REG_VALID; | |
2424 | ||
2425 | I915_WRITE(FENCE_REG_830_0 + (regnum * 4), val); | |
de151cf6 JB |
2426 | } |
2427 | ||
2cf34d7b CW |
2428 | static int i915_find_fence_reg(struct drm_device *dev, |
2429 | bool interruptible) | |
ae3db24a DV |
2430 | { |
2431 | struct drm_i915_fence_reg *reg = NULL; | |
2432 | struct drm_i915_gem_object *obj_priv = NULL; | |
2433 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2434 | struct drm_gem_object *obj = NULL; | |
2435 | int i, avail, ret; | |
2436 | ||
2437 | /* First try to find a free reg */ | |
2438 | avail = 0; | |
2439 | for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) { | |
2440 | reg = &dev_priv->fence_regs[i]; | |
2441 | if (!reg->obj) | |
2442 | return i; | |
2443 | ||
23010e43 | 2444 | obj_priv = to_intel_bo(reg->obj); |
ae3db24a DV |
2445 | if (!obj_priv->pin_count) |
2446 | avail++; | |
2447 | } | |
2448 | ||
2449 | if (avail == 0) | |
2450 | return -ENOSPC; | |
2451 | ||
2452 | /* None available, try to steal one or wait for a user to finish */ | |
2453 | i = I915_FENCE_REG_NONE; | |
007cc8ac DV |
2454 | list_for_each_entry(reg, &dev_priv->mm.fence_list, |
2455 | lru_list) { | |
2456 | obj = reg->obj; | |
2457 | obj_priv = to_intel_bo(obj); | |
ae3db24a DV |
2458 | |
2459 | if (obj_priv->pin_count) | |
2460 | continue; | |
2461 | ||
2462 | /* found one! */ | |
2463 | i = obj_priv->fence_reg; | |
2464 | break; | |
2465 | } | |
2466 | ||
2467 | BUG_ON(i == I915_FENCE_REG_NONE); | |
2468 | ||
2469 | /* We only have a reference on obj from the active list. put_fence_reg | |
2470 | * might drop that one, causing a use-after-free in it. So hold a | |
2471 | * private reference to obj like the other callers of put_fence_reg | |
2472 | * (set_tiling ioctl) do. */ | |
2473 | drm_gem_object_reference(obj); | |
2cf34d7b | 2474 | ret = i915_gem_object_put_fence_reg(obj, interruptible); |
ae3db24a DV |
2475 | drm_gem_object_unreference(obj); |
2476 | if (ret != 0) | |
2477 | return ret; | |
2478 | ||
2479 | return i; | |
2480 | } | |
2481 | ||
de151cf6 JB |
2482 | /** |
2483 | * i915_gem_object_get_fence_reg - set up a fence reg for an object | |
2484 | * @obj: object to map through a fence reg | |
2485 | * | |
2486 | * When mapping objects through the GTT, userspace wants to be able to write | |
2487 | * to them without having to worry about swizzling if the object is tiled. | |
2488 | * | |
2489 | * This function walks the fence regs looking for a free one for @obj, | |
2490 | * stealing one if it can't find any. | |
2491 | * | |
2492 | * It then sets up the reg based on the object's properties: address, pitch | |
2493 | * and tiling format. | |
2494 | */ | |
8c4b8c3f | 2495 | int |
2cf34d7b CW |
2496 | i915_gem_object_get_fence_reg(struct drm_gem_object *obj, |
2497 | bool interruptible) | |
de151cf6 JB |
2498 | { |
2499 | struct drm_device *dev = obj->dev; | |
79e53945 | 2500 | struct drm_i915_private *dev_priv = dev->dev_private; |
23010e43 | 2501 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
de151cf6 | 2502 | struct drm_i915_fence_reg *reg = NULL; |
ae3db24a | 2503 | int ret; |
de151cf6 | 2504 | |
a09ba7fa EA |
2505 | /* Just update our place in the LRU if our fence is getting used. */ |
2506 | if (obj_priv->fence_reg != I915_FENCE_REG_NONE) { | |
007cc8ac DV |
2507 | reg = &dev_priv->fence_regs[obj_priv->fence_reg]; |
2508 | list_move_tail(®->lru_list, &dev_priv->mm.fence_list); | |
a09ba7fa EA |
2509 | return 0; |
2510 | } | |
2511 | ||
de151cf6 JB |
2512 | switch (obj_priv->tiling_mode) { |
2513 | case I915_TILING_NONE: | |
2514 | WARN(1, "allocating a fence for non-tiled object?\n"); | |
2515 | break; | |
2516 | case I915_TILING_X: | |
0f973f27 JB |
2517 | if (!obj_priv->stride) |
2518 | return -EINVAL; | |
2519 | WARN((obj_priv->stride & (512 - 1)), | |
2520 | "object 0x%08x is X tiled but has non-512B pitch\n", | |
2521 | obj_priv->gtt_offset); | |
de151cf6 JB |
2522 | break; |
2523 | case I915_TILING_Y: | |
0f973f27 JB |
2524 | if (!obj_priv->stride) |
2525 | return -EINVAL; | |
2526 | WARN((obj_priv->stride & (128 - 1)), | |
2527 | "object 0x%08x is Y tiled but has non-128B pitch\n", | |
2528 | obj_priv->gtt_offset); | |
de151cf6 JB |
2529 | break; |
2530 | } | |
2531 | ||
2cf34d7b | 2532 | ret = i915_find_fence_reg(dev, interruptible); |
ae3db24a DV |
2533 | if (ret < 0) |
2534 | return ret; | |
de151cf6 | 2535 | |
ae3db24a DV |
2536 | obj_priv->fence_reg = ret; |
2537 | reg = &dev_priv->fence_regs[obj_priv->fence_reg]; | |
007cc8ac | 2538 | list_add_tail(®->lru_list, &dev_priv->mm.fence_list); |
a09ba7fa | 2539 | |
de151cf6 JB |
2540 | reg->obj = obj; |
2541 | ||
e259befd CW |
2542 | switch (INTEL_INFO(dev)->gen) { |
2543 | case 6: | |
4e901fdc | 2544 | sandybridge_write_fence_reg(reg); |
e259befd CW |
2545 | break; |
2546 | case 5: | |
2547 | case 4: | |
de151cf6 | 2548 | i965_write_fence_reg(reg); |
e259befd CW |
2549 | break; |
2550 | case 3: | |
de151cf6 | 2551 | i915_write_fence_reg(reg); |
e259befd CW |
2552 | break; |
2553 | case 2: | |
de151cf6 | 2554 | i830_write_fence_reg(reg); |
e259befd CW |
2555 | break; |
2556 | } | |
d9ddcb96 | 2557 | |
ae3db24a DV |
2558 | trace_i915_gem_object_get_fence(obj, obj_priv->fence_reg, |
2559 | obj_priv->tiling_mode); | |
1c5d22f7 | 2560 | |
d9ddcb96 | 2561 | return 0; |
de151cf6 JB |
2562 | } |
2563 | ||
2564 | /** | |
2565 | * i915_gem_clear_fence_reg - clear out fence register info | |
2566 | * @obj: object to clear | |
2567 | * | |
2568 | * Zeroes out the fence register itself and clears out the associated | |
2569 | * data structures in dev_priv and obj_priv. | |
2570 | */ | |
2571 | static void | |
2572 | i915_gem_clear_fence_reg(struct drm_gem_object *obj) | |
2573 | { | |
2574 | struct drm_device *dev = obj->dev; | |
79e53945 | 2575 | drm_i915_private_t *dev_priv = dev->dev_private; |
23010e43 | 2576 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
007cc8ac DV |
2577 | struct drm_i915_fence_reg *reg = |
2578 | &dev_priv->fence_regs[obj_priv->fence_reg]; | |
e259befd | 2579 | uint32_t fence_reg; |
de151cf6 | 2580 | |
e259befd CW |
2581 | switch (INTEL_INFO(dev)->gen) { |
2582 | case 6: | |
4e901fdc EA |
2583 | I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + |
2584 | (obj_priv->fence_reg * 8), 0); | |
e259befd CW |
2585 | break; |
2586 | case 5: | |
2587 | case 4: | |
de151cf6 | 2588 | I915_WRITE64(FENCE_REG_965_0 + (obj_priv->fence_reg * 8), 0); |
e259befd CW |
2589 | break; |
2590 | case 3: | |
9b74f734 | 2591 | if (obj_priv->fence_reg >= 8) |
e259befd | 2592 | fence_reg = FENCE_REG_945_8 + (obj_priv->fence_reg - 8) * 4; |
dc529a4f | 2593 | else |
e259befd CW |
2594 | case 2: |
2595 | fence_reg = FENCE_REG_830_0 + obj_priv->fence_reg * 4; | |
dc529a4f EA |
2596 | |
2597 | I915_WRITE(fence_reg, 0); | |
e259befd | 2598 | break; |
dc529a4f | 2599 | } |
de151cf6 | 2600 | |
007cc8ac | 2601 | reg->obj = NULL; |
de151cf6 | 2602 | obj_priv->fence_reg = I915_FENCE_REG_NONE; |
007cc8ac | 2603 | list_del_init(®->lru_list); |
de151cf6 JB |
2604 | } |
2605 | ||
52dc7d32 CW |
2606 | /** |
2607 | * i915_gem_object_put_fence_reg - waits on outstanding fenced access | |
2608 | * to the buffer to finish, and then resets the fence register. | |
2609 | * @obj: tiled object holding a fence register. | |
2cf34d7b | 2610 | * @bool: whether the wait upon the fence is interruptible |
52dc7d32 CW |
2611 | * |
2612 | * Zeroes out the fence register itself and clears out the associated | |
2613 | * data structures in dev_priv and obj_priv. | |
2614 | */ | |
2615 | int | |
2cf34d7b CW |
2616 | i915_gem_object_put_fence_reg(struct drm_gem_object *obj, |
2617 | bool interruptible) | |
52dc7d32 CW |
2618 | { |
2619 | struct drm_device *dev = obj->dev; | |
53640e1d | 2620 | struct drm_i915_private *dev_priv = dev->dev_private; |
23010e43 | 2621 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
53640e1d | 2622 | struct drm_i915_fence_reg *reg; |
52dc7d32 CW |
2623 | |
2624 | if (obj_priv->fence_reg == I915_FENCE_REG_NONE) | |
2625 | return 0; | |
2626 | ||
10ae9bd2 DV |
2627 | /* If we've changed tiling, GTT-mappings of the object |
2628 | * need to re-fault to ensure that the correct fence register | |
2629 | * setup is in place. | |
2630 | */ | |
2631 | i915_gem_release_mmap(obj); | |
2632 | ||
52dc7d32 CW |
2633 | /* On the i915, GPU access to tiled buffers is via a fence, |
2634 | * therefore we must wait for any outstanding access to complete | |
2635 | * before clearing the fence. | |
2636 | */ | |
53640e1d CW |
2637 | reg = &dev_priv->fence_regs[obj_priv->fence_reg]; |
2638 | if (reg->gpu) { | |
52dc7d32 CW |
2639 | int ret; |
2640 | ||
2cf34d7b | 2641 | ret = i915_gem_object_flush_gpu_write_domain(obj, true); |
0bc23aad CW |
2642 | if (ret) |
2643 | return ret; | |
2644 | ||
2cf34d7b | 2645 | ret = i915_gem_object_wait_rendering(obj, interruptible); |
0bc23aad | 2646 | if (ret) |
52dc7d32 | 2647 | return ret; |
53640e1d CW |
2648 | |
2649 | reg->gpu = false; | |
52dc7d32 CW |
2650 | } |
2651 | ||
4a726612 | 2652 | i915_gem_object_flush_gtt_write_domain(obj); |
0bc23aad | 2653 | i915_gem_clear_fence_reg(obj); |
52dc7d32 CW |
2654 | |
2655 | return 0; | |
2656 | } | |
2657 | ||
673a394b EA |
2658 | /** |
2659 | * Finds free space in the GTT aperture and binds the object there. | |
2660 | */ | |
2661 | static int | |
2662 | i915_gem_object_bind_to_gtt(struct drm_gem_object *obj, unsigned alignment) | |
2663 | { | |
2664 | struct drm_device *dev = obj->dev; | |
2665 | drm_i915_private_t *dev_priv = dev->dev_private; | |
23010e43 | 2666 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
673a394b | 2667 | struct drm_mm_node *free_space; |
4bdadb97 | 2668 | gfp_t gfpmask = __GFP_NORETRY | __GFP_NOWARN; |
07f73f69 | 2669 | int ret; |
673a394b | 2670 | |
bb6baf76 | 2671 | if (obj_priv->madv != I915_MADV_WILLNEED) { |
3ef94daa CW |
2672 | DRM_ERROR("Attempting to bind a purgeable object\n"); |
2673 | return -EINVAL; | |
2674 | } | |
2675 | ||
673a394b | 2676 | if (alignment == 0) |
0f973f27 | 2677 | alignment = i915_gem_get_gtt_alignment(obj); |
8d7773a3 | 2678 | if (alignment & (i915_gem_get_gtt_alignment(obj) - 1)) { |
673a394b EA |
2679 | DRM_ERROR("Invalid object alignment requested %u\n", alignment); |
2680 | return -EINVAL; | |
2681 | } | |
2682 | ||
654fc607 CW |
2683 | /* If the object is bigger than the entire aperture, reject it early |
2684 | * before evicting everything in a vain attempt to find space. | |
2685 | */ | |
73aa808f | 2686 | if (obj->size > dev_priv->mm.gtt_total) { |
654fc607 CW |
2687 | DRM_ERROR("Attempting to bind an object larger than the aperture\n"); |
2688 | return -E2BIG; | |
2689 | } | |
2690 | ||
673a394b EA |
2691 | search_free: |
2692 | free_space = drm_mm_search_free(&dev_priv->mm.gtt_space, | |
2693 | obj->size, alignment, 0); | |
2694 | if (free_space != NULL) { | |
2695 | obj_priv->gtt_space = drm_mm_get_block(free_space, obj->size, | |
2696 | alignment); | |
db3307a9 | 2697 | if (obj_priv->gtt_space != NULL) |
673a394b | 2698 | obj_priv->gtt_offset = obj_priv->gtt_space->start; |
673a394b EA |
2699 | } |
2700 | if (obj_priv->gtt_space == NULL) { | |
2701 | /* If the gtt is empty and we're still having trouble | |
2702 | * fitting our object in, we're out of memory. | |
2703 | */ | |
0108a3ed | 2704 | ret = i915_gem_evict_something(dev, obj->size, alignment); |
9731129c | 2705 | if (ret) |
673a394b | 2706 | return ret; |
9731129c | 2707 | |
673a394b EA |
2708 | goto search_free; |
2709 | } | |
2710 | ||
4bdadb97 | 2711 | ret = i915_gem_object_get_pages(obj, gfpmask); |
673a394b EA |
2712 | if (ret) { |
2713 | drm_mm_put_block(obj_priv->gtt_space); | |
2714 | obj_priv->gtt_space = NULL; | |
07f73f69 CW |
2715 | |
2716 | if (ret == -ENOMEM) { | |
2717 | /* first try to clear up some space from the GTT */ | |
0108a3ed DV |
2718 | ret = i915_gem_evict_something(dev, obj->size, |
2719 | alignment); | |
07f73f69 | 2720 | if (ret) { |
07f73f69 | 2721 | /* now try to shrink everyone else */ |
4bdadb97 CW |
2722 | if (gfpmask) { |
2723 | gfpmask = 0; | |
2724 | goto search_free; | |
07f73f69 CW |
2725 | } |
2726 | ||
2727 | return ret; | |
2728 | } | |
2729 | ||
2730 | goto search_free; | |
2731 | } | |
2732 | ||
673a394b EA |
2733 | return ret; |
2734 | } | |
2735 | ||
673a394b EA |
2736 | /* Create an AGP memory structure pointing at our pages, and bind it |
2737 | * into the GTT. | |
2738 | */ | |
2739 | obj_priv->agp_mem = drm_agp_bind_pages(dev, | |
856fa198 | 2740 | obj_priv->pages, |
07f73f69 | 2741 | obj->size >> PAGE_SHIFT, |
ba1eb1d8 KP |
2742 | obj_priv->gtt_offset, |
2743 | obj_priv->agp_type); | |
673a394b | 2744 | if (obj_priv->agp_mem == NULL) { |
856fa198 | 2745 | i915_gem_object_put_pages(obj); |
673a394b EA |
2746 | drm_mm_put_block(obj_priv->gtt_space); |
2747 | obj_priv->gtt_space = NULL; | |
07f73f69 | 2748 | |
0108a3ed | 2749 | ret = i915_gem_evict_something(dev, obj->size, alignment); |
9731129c | 2750 | if (ret) |
07f73f69 | 2751 | return ret; |
07f73f69 CW |
2752 | |
2753 | goto search_free; | |
673a394b | 2754 | } |
673a394b | 2755 | |
bf1a1092 CW |
2756 | /* keep track of bounds object by adding it to the inactive list */ |
2757 | list_add_tail(&obj_priv->list, &dev_priv->mm.inactive_list); | |
73aa808f | 2758 | i915_gem_info_add_gtt(dev_priv, obj->size); |
bf1a1092 | 2759 | |
673a394b EA |
2760 | /* Assert that the object is not currently in any GPU domain. As it |
2761 | * wasn't in the GTT, there shouldn't be any way it could have been in | |
2762 | * a GPU cache | |
2763 | */ | |
21d509e3 CW |
2764 | BUG_ON(obj->read_domains & I915_GEM_GPU_DOMAINS); |
2765 | BUG_ON(obj->write_domain & I915_GEM_GPU_DOMAINS); | |
673a394b | 2766 | |
1c5d22f7 CW |
2767 | trace_i915_gem_object_bind(obj, obj_priv->gtt_offset); |
2768 | ||
673a394b EA |
2769 | return 0; |
2770 | } | |
2771 | ||
2772 | void | |
2773 | i915_gem_clflush_object(struct drm_gem_object *obj) | |
2774 | { | |
23010e43 | 2775 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
673a394b EA |
2776 | |
2777 | /* If we don't have a page list set up, then we're not pinned | |
2778 | * to GPU, and we can ignore the cache flush because it'll happen | |
2779 | * again at bind time. | |
2780 | */ | |
856fa198 | 2781 | if (obj_priv->pages == NULL) |
673a394b EA |
2782 | return; |
2783 | ||
1c5d22f7 | 2784 | trace_i915_gem_object_clflush(obj); |
cfa16a0d | 2785 | |
856fa198 | 2786 | drm_clflush_pages(obj_priv->pages, obj->size / PAGE_SIZE); |
673a394b EA |
2787 | } |
2788 | ||
e47c68e9 | 2789 | /** Flushes any GPU write domain for the object if it's dirty. */ |
2dafb1e0 | 2790 | static int |
ba3d8d74 DV |
2791 | i915_gem_object_flush_gpu_write_domain(struct drm_gem_object *obj, |
2792 | bool pipelined) | |
e47c68e9 EA |
2793 | { |
2794 | struct drm_device *dev = obj->dev; | |
1c5d22f7 | 2795 | uint32_t old_write_domain; |
e47c68e9 EA |
2796 | |
2797 | if ((obj->write_domain & I915_GEM_GPU_DOMAINS) == 0) | |
2dafb1e0 | 2798 | return 0; |
e47c68e9 EA |
2799 | |
2800 | /* Queue the GPU write cache flushing we need. */ | |
1c5d22f7 | 2801 | old_write_domain = obj->write_domain; |
c78ec30b | 2802 | i915_gem_flush_ring(dev, NULL, |
9220434a CW |
2803 | to_intel_bo(obj)->ring, |
2804 | 0, obj->write_domain); | |
48b956c5 | 2805 | BUG_ON(obj->write_domain); |
1c5d22f7 CW |
2806 | |
2807 | trace_i915_gem_object_change_domain(obj, | |
2808 | obj->read_domains, | |
2809 | old_write_domain); | |
ba3d8d74 DV |
2810 | |
2811 | if (pipelined) | |
2812 | return 0; | |
2813 | ||
2cf34d7b | 2814 | return i915_gem_object_wait_rendering(obj, true); |
e47c68e9 EA |
2815 | } |
2816 | ||
2817 | /** Flushes the GTT write domain for the object if it's dirty. */ | |
2818 | static void | |
2819 | i915_gem_object_flush_gtt_write_domain(struct drm_gem_object *obj) | |
2820 | { | |
1c5d22f7 CW |
2821 | uint32_t old_write_domain; |
2822 | ||
e47c68e9 EA |
2823 | if (obj->write_domain != I915_GEM_DOMAIN_GTT) |
2824 | return; | |
2825 | ||
2826 | /* No actual flushing is required for the GTT write domain. Writes | |
2827 | * to it immediately go to main memory as far as we know, so there's | |
2828 | * no chipset flush. It also doesn't land in render cache. | |
2829 | */ | |
1c5d22f7 | 2830 | old_write_domain = obj->write_domain; |
e47c68e9 | 2831 | obj->write_domain = 0; |
1c5d22f7 CW |
2832 | |
2833 | trace_i915_gem_object_change_domain(obj, | |
2834 | obj->read_domains, | |
2835 | old_write_domain); | |
e47c68e9 EA |
2836 | } |
2837 | ||
2838 | /** Flushes the CPU write domain for the object if it's dirty. */ | |
2839 | static void | |
2840 | i915_gem_object_flush_cpu_write_domain(struct drm_gem_object *obj) | |
2841 | { | |
2842 | struct drm_device *dev = obj->dev; | |
1c5d22f7 | 2843 | uint32_t old_write_domain; |
e47c68e9 EA |
2844 | |
2845 | if (obj->write_domain != I915_GEM_DOMAIN_CPU) | |
2846 | return; | |
2847 | ||
2848 | i915_gem_clflush_object(obj); | |
2849 | drm_agp_chipset_flush(dev); | |
1c5d22f7 | 2850 | old_write_domain = obj->write_domain; |
e47c68e9 | 2851 | obj->write_domain = 0; |
1c5d22f7 CW |
2852 | |
2853 | trace_i915_gem_object_change_domain(obj, | |
2854 | obj->read_domains, | |
2855 | old_write_domain); | |
e47c68e9 EA |
2856 | } |
2857 | ||
2ef7eeaa EA |
2858 | /** |
2859 | * Moves a single object to the GTT read, and possibly write domain. | |
2860 | * | |
2861 | * This function returns when the move is complete, including waiting on | |
2862 | * flushes to occur. | |
2863 | */ | |
79e53945 | 2864 | int |
2ef7eeaa EA |
2865 | i915_gem_object_set_to_gtt_domain(struct drm_gem_object *obj, int write) |
2866 | { | |
23010e43 | 2867 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
1c5d22f7 | 2868 | uint32_t old_write_domain, old_read_domains; |
e47c68e9 | 2869 | int ret; |
2ef7eeaa | 2870 | |
02354392 EA |
2871 | /* Not valid to be called on unbound objects. */ |
2872 | if (obj_priv->gtt_space == NULL) | |
2873 | return -EINVAL; | |
2874 | ||
ba3d8d74 | 2875 | ret = i915_gem_object_flush_gpu_write_domain(obj, false); |
e47c68e9 EA |
2876 | if (ret != 0) |
2877 | return ret; | |
2878 | ||
7213342d | 2879 | i915_gem_object_flush_cpu_write_domain(obj); |
1c5d22f7 | 2880 | |
ba3d8d74 | 2881 | if (write) { |
2cf34d7b | 2882 | ret = i915_gem_object_wait_rendering(obj, true); |
ba3d8d74 DV |
2883 | if (ret) |
2884 | return ret; | |
ba3d8d74 | 2885 | } |
2ef7eeaa | 2886 | |
7213342d CW |
2887 | old_write_domain = obj->write_domain; |
2888 | old_read_domains = obj->read_domains; | |
2ef7eeaa | 2889 | |
e47c68e9 EA |
2890 | /* It should now be out of any other write domains, and we can update |
2891 | * the domain values for our changes. | |
2892 | */ | |
2893 | BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_GTT) != 0); | |
2894 | obj->read_domains |= I915_GEM_DOMAIN_GTT; | |
2895 | if (write) { | |
7213342d | 2896 | obj->read_domains = I915_GEM_DOMAIN_GTT; |
e47c68e9 EA |
2897 | obj->write_domain = I915_GEM_DOMAIN_GTT; |
2898 | obj_priv->dirty = 1; | |
2ef7eeaa EA |
2899 | } |
2900 | ||
1c5d22f7 CW |
2901 | trace_i915_gem_object_change_domain(obj, |
2902 | old_read_domains, | |
2903 | old_write_domain); | |
2904 | ||
e47c68e9 EA |
2905 | return 0; |
2906 | } | |
2907 | ||
b9241ea3 ZW |
2908 | /* |
2909 | * Prepare buffer for display plane. Use uninterruptible for possible flush | |
2910 | * wait, as in modesetting process we're not supposed to be interrupted. | |
2911 | */ | |
2912 | int | |
48b956c5 CW |
2913 | i915_gem_object_set_to_display_plane(struct drm_gem_object *obj, |
2914 | bool pipelined) | |
b9241ea3 | 2915 | { |
23010e43 | 2916 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
ba3d8d74 | 2917 | uint32_t old_read_domains; |
b9241ea3 ZW |
2918 | int ret; |
2919 | ||
2920 | /* Not valid to be called on unbound objects. */ | |
2921 | if (obj_priv->gtt_space == NULL) | |
2922 | return -EINVAL; | |
2923 | ||
ced270fa | 2924 | ret = i915_gem_object_flush_gpu_write_domain(obj, true); |
48b956c5 | 2925 | if (ret) |
e35a41de | 2926 | return ret; |
b9241ea3 | 2927 | |
ced270fa CW |
2928 | /* Currently, we are always called from an non-interruptible context. */ |
2929 | if (!pipelined) { | |
2930 | ret = i915_gem_object_wait_rendering(obj, false); | |
2931 | if (ret) | |
2932 | return ret; | |
2933 | } | |
2934 | ||
b118c1e3 CW |
2935 | i915_gem_object_flush_cpu_write_domain(obj); |
2936 | ||
b9241ea3 | 2937 | old_read_domains = obj->read_domains; |
c78ec30b | 2938 | obj->read_domains |= I915_GEM_DOMAIN_GTT; |
b9241ea3 ZW |
2939 | |
2940 | trace_i915_gem_object_change_domain(obj, | |
2941 | old_read_domains, | |
ba3d8d74 | 2942 | obj->write_domain); |
b9241ea3 ZW |
2943 | |
2944 | return 0; | |
2945 | } | |
2946 | ||
e47c68e9 EA |
2947 | /** |
2948 | * Moves a single object to the CPU read, and possibly write domain. | |
2949 | * | |
2950 | * This function returns when the move is complete, including waiting on | |
2951 | * flushes to occur. | |
2952 | */ | |
2953 | static int | |
2954 | i915_gem_object_set_to_cpu_domain(struct drm_gem_object *obj, int write) | |
2955 | { | |
1c5d22f7 | 2956 | uint32_t old_write_domain, old_read_domains; |
e47c68e9 EA |
2957 | int ret; |
2958 | ||
ba3d8d74 | 2959 | ret = i915_gem_object_flush_gpu_write_domain(obj, false); |
e47c68e9 EA |
2960 | if (ret != 0) |
2961 | return ret; | |
2ef7eeaa | 2962 | |
e47c68e9 | 2963 | i915_gem_object_flush_gtt_write_domain(obj); |
2ef7eeaa | 2964 | |
e47c68e9 EA |
2965 | /* If we have a partially-valid cache of the object in the CPU, |
2966 | * finish invalidating it and free the per-page flags. | |
2ef7eeaa | 2967 | */ |
e47c68e9 | 2968 | i915_gem_object_set_to_full_cpu_read_domain(obj); |
2ef7eeaa | 2969 | |
7213342d | 2970 | if (write) { |
2cf34d7b | 2971 | ret = i915_gem_object_wait_rendering(obj, true); |
7213342d CW |
2972 | if (ret) |
2973 | return ret; | |
2974 | } | |
2975 | ||
1c5d22f7 CW |
2976 | old_write_domain = obj->write_domain; |
2977 | old_read_domains = obj->read_domains; | |
2978 | ||
e47c68e9 EA |
2979 | /* Flush the CPU cache if it's still invalid. */ |
2980 | if ((obj->read_domains & I915_GEM_DOMAIN_CPU) == 0) { | |
2ef7eeaa | 2981 | i915_gem_clflush_object(obj); |
2ef7eeaa | 2982 | |
e47c68e9 | 2983 | obj->read_domains |= I915_GEM_DOMAIN_CPU; |
2ef7eeaa EA |
2984 | } |
2985 | ||
2986 | /* It should now be out of any other write domains, and we can update | |
2987 | * the domain values for our changes. | |
2988 | */ | |
e47c68e9 EA |
2989 | BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_CPU) != 0); |
2990 | ||
2991 | /* If we're writing through the CPU, then the GPU read domains will | |
2992 | * need to be invalidated at next use. | |
2993 | */ | |
2994 | if (write) { | |
c78ec30b | 2995 | obj->read_domains = I915_GEM_DOMAIN_CPU; |
e47c68e9 EA |
2996 | obj->write_domain = I915_GEM_DOMAIN_CPU; |
2997 | } | |
2ef7eeaa | 2998 | |
1c5d22f7 CW |
2999 | trace_i915_gem_object_change_domain(obj, |
3000 | old_read_domains, | |
3001 | old_write_domain); | |
3002 | ||
2ef7eeaa EA |
3003 | return 0; |
3004 | } | |
3005 | ||
673a394b EA |
3006 | /* |
3007 | * Set the next domain for the specified object. This | |
3008 | * may not actually perform the necessary flushing/invaliding though, | |
3009 | * as that may want to be batched with other set_domain operations | |
3010 | * | |
3011 | * This is (we hope) the only really tricky part of gem. The goal | |
3012 | * is fairly simple -- track which caches hold bits of the object | |
3013 | * and make sure they remain coherent. A few concrete examples may | |
3014 | * help to explain how it works. For shorthand, we use the notation | |
3015 | * (read_domains, write_domain), e.g. (CPU, CPU) to indicate the | |
3016 | * a pair of read and write domain masks. | |
3017 | * | |
3018 | * Case 1: the batch buffer | |
3019 | * | |
3020 | * 1. Allocated | |
3021 | * 2. Written by CPU | |
3022 | * 3. Mapped to GTT | |
3023 | * 4. Read by GPU | |
3024 | * 5. Unmapped from GTT | |
3025 | * 6. Freed | |
3026 | * | |
3027 | * Let's take these a step at a time | |
3028 | * | |
3029 | * 1. Allocated | |
3030 | * Pages allocated from the kernel may still have | |
3031 | * cache contents, so we set them to (CPU, CPU) always. | |
3032 | * 2. Written by CPU (using pwrite) | |
3033 | * The pwrite function calls set_domain (CPU, CPU) and | |
3034 | * this function does nothing (as nothing changes) | |
3035 | * 3. Mapped by GTT | |
3036 | * This function asserts that the object is not | |
3037 | * currently in any GPU-based read or write domains | |
3038 | * 4. Read by GPU | |
3039 | * i915_gem_execbuffer calls set_domain (COMMAND, 0). | |
3040 | * As write_domain is zero, this function adds in the | |
3041 | * current read domains (CPU+COMMAND, 0). | |
3042 | * flush_domains is set to CPU. | |
3043 | * invalidate_domains is set to COMMAND | |
3044 | * clflush is run to get data out of the CPU caches | |
3045 | * then i915_dev_set_domain calls i915_gem_flush to | |
3046 | * emit an MI_FLUSH and drm_agp_chipset_flush | |
3047 | * 5. Unmapped from GTT | |
3048 | * i915_gem_object_unbind calls set_domain (CPU, CPU) | |
3049 | * flush_domains and invalidate_domains end up both zero | |
3050 | * so no flushing/invalidating happens | |
3051 | * 6. Freed | |
3052 | * yay, done | |
3053 | * | |
3054 | * Case 2: The shared render buffer | |
3055 | * | |
3056 | * 1. Allocated | |
3057 | * 2. Mapped to GTT | |
3058 | * 3. Read/written by GPU | |
3059 | * 4. set_domain to (CPU,CPU) | |
3060 | * 5. Read/written by CPU | |
3061 | * 6. Read/written by GPU | |
3062 | * | |
3063 | * 1. Allocated | |
3064 | * Same as last example, (CPU, CPU) | |
3065 | * 2. Mapped to GTT | |
3066 | * Nothing changes (assertions find that it is not in the GPU) | |
3067 | * 3. Read/written by GPU | |
3068 | * execbuffer calls set_domain (RENDER, RENDER) | |
3069 | * flush_domains gets CPU | |
3070 | * invalidate_domains gets GPU | |
3071 | * clflush (obj) | |
3072 | * MI_FLUSH and drm_agp_chipset_flush | |
3073 | * 4. set_domain (CPU, CPU) | |
3074 | * flush_domains gets GPU | |
3075 | * invalidate_domains gets CPU | |
3076 | * wait_rendering (obj) to make sure all drawing is complete. | |
3077 | * This will include an MI_FLUSH to get the data from GPU | |
3078 | * to memory | |
3079 | * clflush (obj) to invalidate the CPU cache | |
3080 | * Another MI_FLUSH in i915_gem_flush (eliminate this somehow?) | |
3081 | * 5. Read/written by CPU | |
3082 | * cache lines are loaded and dirtied | |
3083 | * 6. Read written by GPU | |
3084 | * Same as last GPU access | |
3085 | * | |
3086 | * Case 3: The constant buffer | |
3087 | * | |
3088 | * 1. Allocated | |
3089 | * 2. Written by CPU | |
3090 | * 3. Read by GPU | |
3091 | * 4. Updated (written) by CPU again | |
3092 | * 5. Read by GPU | |
3093 | * | |
3094 | * 1. Allocated | |
3095 | * (CPU, CPU) | |
3096 | * 2. Written by CPU | |
3097 | * (CPU, CPU) | |
3098 | * 3. Read by GPU | |
3099 | * (CPU+RENDER, 0) | |
3100 | * flush_domains = CPU | |
3101 | * invalidate_domains = RENDER | |
3102 | * clflush (obj) | |
3103 | * MI_FLUSH | |
3104 | * drm_agp_chipset_flush | |
3105 | * 4. Updated (written) by CPU again | |
3106 | * (CPU, CPU) | |
3107 | * flush_domains = 0 (no previous write domain) | |
3108 | * invalidate_domains = 0 (no new read domains) | |
3109 | * 5. Read by GPU | |
3110 | * (CPU+RENDER, 0) | |
3111 | * flush_domains = CPU | |
3112 | * invalidate_domains = RENDER | |
3113 | * clflush (obj) | |
3114 | * MI_FLUSH | |
3115 | * drm_agp_chipset_flush | |
3116 | */ | |
c0d90829 | 3117 | static void |
8b0e378a | 3118 | i915_gem_object_set_to_gpu_domain(struct drm_gem_object *obj) |
673a394b EA |
3119 | { |
3120 | struct drm_device *dev = obj->dev; | |
9220434a | 3121 | struct drm_i915_private *dev_priv = dev->dev_private; |
23010e43 | 3122 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
673a394b EA |
3123 | uint32_t invalidate_domains = 0; |
3124 | uint32_t flush_domains = 0; | |
1c5d22f7 | 3125 | uint32_t old_read_domains; |
e47c68e9 | 3126 | |
8b0e378a EA |
3127 | BUG_ON(obj->pending_read_domains & I915_GEM_DOMAIN_CPU); |
3128 | BUG_ON(obj->pending_write_domain == I915_GEM_DOMAIN_CPU); | |
673a394b | 3129 | |
652c393a JB |
3130 | intel_mark_busy(dev, obj); |
3131 | ||
673a394b EA |
3132 | /* |
3133 | * If the object isn't moving to a new write domain, | |
3134 | * let the object stay in multiple read domains | |
3135 | */ | |
8b0e378a EA |
3136 | if (obj->pending_write_domain == 0) |
3137 | obj->pending_read_domains |= obj->read_domains; | |
673a394b EA |
3138 | else |
3139 | obj_priv->dirty = 1; | |
3140 | ||
3141 | /* | |
3142 | * Flush the current write domain if | |
3143 | * the new read domains don't match. Invalidate | |
3144 | * any read domains which differ from the old | |
3145 | * write domain | |
3146 | */ | |
8b0e378a EA |
3147 | if (obj->write_domain && |
3148 | obj->write_domain != obj->pending_read_domains) { | |
673a394b | 3149 | flush_domains |= obj->write_domain; |
8b0e378a EA |
3150 | invalidate_domains |= |
3151 | obj->pending_read_domains & ~obj->write_domain; | |
673a394b EA |
3152 | } |
3153 | /* | |
3154 | * Invalidate any read caches which may have | |
3155 | * stale data. That is, any new read domains. | |
3156 | */ | |
8b0e378a | 3157 | invalidate_domains |= obj->pending_read_domains & ~obj->read_domains; |
3d2a812a | 3158 | if ((flush_domains | invalidate_domains) & I915_GEM_DOMAIN_CPU) |
673a394b | 3159 | i915_gem_clflush_object(obj); |
673a394b | 3160 | |
1c5d22f7 CW |
3161 | old_read_domains = obj->read_domains; |
3162 | ||
efbeed96 EA |
3163 | /* The actual obj->write_domain will be updated with |
3164 | * pending_write_domain after we emit the accumulated flush for all | |
3165 | * of our domain changes in execbuffers (which clears objects' | |
3166 | * write_domains). So if we have a current write domain that we | |
3167 | * aren't changing, set pending_write_domain to that. | |
3168 | */ | |
3169 | if (flush_domains == 0 && obj->pending_write_domain == 0) | |
3170 | obj->pending_write_domain = obj->write_domain; | |
8b0e378a | 3171 | obj->read_domains = obj->pending_read_domains; |
673a394b EA |
3172 | |
3173 | dev->invalidate_domains |= invalidate_domains; | |
3174 | dev->flush_domains |= flush_domains; | |
9220434a CW |
3175 | if (obj_priv->ring) |
3176 | dev_priv->mm.flush_rings |= obj_priv->ring->id; | |
1c5d22f7 CW |
3177 | |
3178 | trace_i915_gem_object_change_domain(obj, | |
3179 | old_read_domains, | |
3180 | obj->write_domain); | |
673a394b EA |
3181 | } |
3182 | ||
3183 | /** | |
e47c68e9 | 3184 | * Moves the object from a partially CPU read to a full one. |
673a394b | 3185 | * |
e47c68e9 EA |
3186 | * Note that this only resolves i915_gem_object_set_cpu_read_domain_range(), |
3187 | * and doesn't handle transitioning from !(read_domains & I915_GEM_DOMAIN_CPU). | |
673a394b | 3188 | */ |
e47c68e9 EA |
3189 | static void |
3190 | i915_gem_object_set_to_full_cpu_read_domain(struct drm_gem_object *obj) | |
673a394b | 3191 | { |
23010e43 | 3192 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
673a394b | 3193 | |
e47c68e9 EA |
3194 | if (!obj_priv->page_cpu_valid) |
3195 | return; | |
3196 | ||
3197 | /* If we're partially in the CPU read domain, finish moving it in. | |
3198 | */ | |
3199 | if (obj->read_domains & I915_GEM_DOMAIN_CPU) { | |
3200 | int i; | |
3201 | ||
3202 | for (i = 0; i <= (obj->size - 1) / PAGE_SIZE; i++) { | |
3203 | if (obj_priv->page_cpu_valid[i]) | |
3204 | continue; | |
856fa198 | 3205 | drm_clflush_pages(obj_priv->pages + i, 1); |
e47c68e9 | 3206 | } |
e47c68e9 EA |
3207 | } |
3208 | ||
3209 | /* Free the page_cpu_valid mappings which are now stale, whether | |
3210 | * or not we've got I915_GEM_DOMAIN_CPU. | |
3211 | */ | |
9a298b2a | 3212 | kfree(obj_priv->page_cpu_valid); |
e47c68e9 EA |
3213 | obj_priv->page_cpu_valid = NULL; |
3214 | } | |
3215 | ||
3216 | /** | |
3217 | * Set the CPU read domain on a range of the object. | |
3218 | * | |
3219 | * The object ends up with I915_GEM_DOMAIN_CPU in its read flags although it's | |
3220 | * not entirely valid. The page_cpu_valid member of the object flags which | |
3221 | * pages have been flushed, and will be respected by | |
3222 | * i915_gem_object_set_to_cpu_domain() if it's called on to get a valid mapping | |
3223 | * of the whole object. | |
3224 | * | |
3225 | * This function returns when the move is complete, including waiting on | |
3226 | * flushes to occur. | |
3227 | */ | |
3228 | static int | |
3229 | i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object *obj, | |
3230 | uint64_t offset, uint64_t size) | |
3231 | { | |
23010e43 | 3232 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
1c5d22f7 | 3233 | uint32_t old_read_domains; |
e47c68e9 | 3234 | int i, ret; |
673a394b | 3235 | |
e47c68e9 EA |
3236 | if (offset == 0 && size == obj->size) |
3237 | return i915_gem_object_set_to_cpu_domain(obj, 0); | |
673a394b | 3238 | |
ba3d8d74 | 3239 | ret = i915_gem_object_flush_gpu_write_domain(obj, false); |
e47c68e9 | 3240 | if (ret != 0) |
6a47baa6 | 3241 | return ret; |
e47c68e9 EA |
3242 | i915_gem_object_flush_gtt_write_domain(obj); |
3243 | ||
3244 | /* If we're already fully in the CPU read domain, we're done. */ | |
3245 | if (obj_priv->page_cpu_valid == NULL && | |
3246 | (obj->read_domains & I915_GEM_DOMAIN_CPU) != 0) | |
3247 | return 0; | |
673a394b | 3248 | |
e47c68e9 EA |
3249 | /* Otherwise, create/clear the per-page CPU read domain flag if we're |
3250 | * newly adding I915_GEM_DOMAIN_CPU | |
3251 | */ | |
673a394b | 3252 | if (obj_priv->page_cpu_valid == NULL) { |
9a298b2a EA |
3253 | obj_priv->page_cpu_valid = kzalloc(obj->size / PAGE_SIZE, |
3254 | GFP_KERNEL); | |
e47c68e9 EA |
3255 | if (obj_priv->page_cpu_valid == NULL) |
3256 | return -ENOMEM; | |
3257 | } else if ((obj->read_domains & I915_GEM_DOMAIN_CPU) == 0) | |
3258 | memset(obj_priv->page_cpu_valid, 0, obj->size / PAGE_SIZE); | |
673a394b EA |
3259 | |
3260 | /* Flush the cache on any pages that are still invalid from the CPU's | |
3261 | * perspective. | |
3262 | */ | |
e47c68e9 EA |
3263 | for (i = offset / PAGE_SIZE; i <= (offset + size - 1) / PAGE_SIZE; |
3264 | i++) { | |
673a394b EA |
3265 | if (obj_priv->page_cpu_valid[i]) |
3266 | continue; | |
3267 | ||
856fa198 | 3268 | drm_clflush_pages(obj_priv->pages + i, 1); |
673a394b EA |
3269 | |
3270 | obj_priv->page_cpu_valid[i] = 1; | |
3271 | } | |
3272 | ||
e47c68e9 EA |
3273 | /* It should now be out of any other write domains, and we can update |
3274 | * the domain values for our changes. | |
3275 | */ | |
3276 | BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_CPU) != 0); | |
3277 | ||
1c5d22f7 | 3278 | old_read_domains = obj->read_domains; |
e47c68e9 EA |
3279 | obj->read_domains |= I915_GEM_DOMAIN_CPU; |
3280 | ||
1c5d22f7 CW |
3281 | trace_i915_gem_object_change_domain(obj, |
3282 | old_read_domains, | |
3283 | obj->write_domain); | |
3284 | ||
673a394b EA |
3285 | return 0; |
3286 | } | |
3287 | ||
673a394b EA |
3288 | /** |
3289 | * Pin an object to the GTT and evaluate the relocations landing in it. | |
3290 | */ | |
3291 | static int | |
3292 | i915_gem_object_pin_and_relocate(struct drm_gem_object *obj, | |
3293 | struct drm_file *file_priv, | |
76446cac | 3294 | struct drm_i915_gem_exec_object2 *entry, |
40a5f0de | 3295 | struct drm_i915_gem_relocation_entry *relocs) |
673a394b EA |
3296 | { |
3297 | struct drm_device *dev = obj->dev; | |
0839ccb8 | 3298 | drm_i915_private_t *dev_priv = dev->dev_private; |
23010e43 | 3299 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
673a394b | 3300 | int i, ret; |
0839ccb8 | 3301 | void __iomem *reloc_page; |
76446cac JB |
3302 | bool need_fence; |
3303 | ||
3304 | need_fence = entry->flags & EXEC_OBJECT_NEEDS_FENCE && | |
3305 | obj_priv->tiling_mode != I915_TILING_NONE; | |
3306 | ||
3307 | /* Check fence reg constraints and rebind if necessary */ | |
808b24d6 CW |
3308 | if (need_fence && |
3309 | !i915_gem_object_fence_offset_ok(obj, | |
3310 | obj_priv->tiling_mode)) { | |
3311 | ret = i915_gem_object_unbind(obj); | |
3312 | if (ret) | |
3313 | return ret; | |
3314 | } | |
673a394b EA |
3315 | |
3316 | /* Choose the GTT offset for our buffer and put it there. */ | |
3317 | ret = i915_gem_object_pin(obj, (uint32_t) entry->alignment); | |
3318 | if (ret) | |
3319 | return ret; | |
3320 | ||
76446cac JB |
3321 | /* |
3322 | * Pre-965 chips need a fence register set up in order to | |
3323 | * properly handle blits to/from tiled surfaces. | |
3324 | */ | |
3325 | if (need_fence) { | |
53640e1d | 3326 | ret = i915_gem_object_get_fence_reg(obj, true); |
76446cac | 3327 | if (ret != 0) { |
76446cac JB |
3328 | i915_gem_object_unpin(obj); |
3329 | return ret; | |
3330 | } | |
53640e1d CW |
3331 | |
3332 | dev_priv->fence_regs[obj_priv->fence_reg].gpu = true; | |
76446cac JB |
3333 | } |
3334 | ||
673a394b EA |
3335 | entry->offset = obj_priv->gtt_offset; |
3336 | ||
673a394b EA |
3337 | /* Apply the relocations, using the GTT aperture to avoid cache |
3338 | * flushing requirements. | |
3339 | */ | |
3340 | for (i = 0; i < entry->relocation_count; i++) { | |
40a5f0de | 3341 | struct drm_i915_gem_relocation_entry *reloc= &relocs[i]; |
673a394b EA |
3342 | struct drm_gem_object *target_obj; |
3343 | struct drm_i915_gem_object *target_obj_priv; | |
3043c60c EA |
3344 | uint32_t reloc_val, reloc_offset; |
3345 | uint32_t __iomem *reloc_entry; | |
673a394b | 3346 | |
673a394b | 3347 | target_obj = drm_gem_object_lookup(obj->dev, file_priv, |
40a5f0de | 3348 | reloc->target_handle); |
673a394b EA |
3349 | if (target_obj == NULL) { |
3350 | i915_gem_object_unpin(obj); | |
bf79cb91 | 3351 | return -ENOENT; |
673a394b | 3352 | } |
23010e43 | 3353 | target_obj_priv = to_intel_bo(target_obj); |
673a394b | 3354 | |
8542a0bb CW |
3355 | #if WATCH_RELOC |
3356 | DRM_INFO("%s: obj %p offset %08x target %d " | |
3357 | "read %08x write %08x gtt %08x " | |
3358 | "presumed %08x delta %08x\n", | |
3359 | __func__, | |
3360 | obj, | |
3361 | (int) reloc->offset, | |
3362 | (int) reloc->target_handle, | |
3363 | (int) reloc->read_domains, | |
3364 | (int) reloc->write_domain, | |
3365 | (int) target_obj_priv->gtt_offset, | |
3366 | (int) reloc->presumed_offset, | |
3367 | reloc->delta); | |
3368 | #endif | |
3369 | ||
673a394b EA |
3370 | /* The target buffer should have appeared before us in the |
3371 | * exec_object list, so it should have a GTT space bound by now. | |
3372 | */ | |
3373 | if (target_obj_priv->gtt_space == NULL) { | |
3374 | DRM_ERROR("No GTT space found for object %d\n", | |
40a5f0de | 3375 | reloc->target_handle); |
673a394b EA |
3376 | drm_gem_object_unreference(target_obj); |
3377 | i915_gem_object_unpin(obj); | |
3378 | return -EINVAL; | |
3379 | } | |
3380 | ||
8542a0bb | 3381 | /* Validate that the target is in a valid r/w GPU domain */ |
16edd550 DV |
3382 | if (reloc->write_domain & (reloc->write_domain - 1)) { |
3383 | DRM_ERROR("reloc with multiple write domains: " | |
3384 | "obj %p target %d offset %d " | |
3385 | "read %08x write %08x", | |
3386 | obj, reloc->target_handle, | |
3387 | (int) reloc->offset, | |
3388 | reloc->read_domains, | |
3389 | reloc->write_domain); | |
929f49bf JL |
3390 | drm_gem_object_unreference(target_obj); |
3391 | i915_gem_object_unpin(obj); | |
16edd550 DV |
3392 | return -EINVAL; |
3393 | } | |
40a5f0de EA |
3394 | if (reloc->write_domain & I915_GEM_DOMAIN_CPU || |
3395 | reloc->read_domains & I915_GEM_DOMAIN_CPU) { | |
e47c68e9 EA |
3396 | DRM_ERROR("reloc with read/write CPU domains: " |
3397 | "obj %p target %d offset %d " | |
3398 | "read %08x write %08x", | |
40a5f0de EA |
3399 | obj, reloc->target_handle, |
3400 | (int) reloc->offset, | |
3401 | reloc->read_domains, | |
3402 | reloc->write_domain); | |
491152b8 CW |
3403 | drm_gem_object_unreference(target_obj); |
3404 | i915_gem_object_unpin(obj); | |
e47c68e9 EA |
3405 | return -EINVAL; |
3406 | } | |
40a5f0de EA |
3407 | if (reloc->write_domain && target_obj->pending_write_domain && |
3408 | reloc->write_domain != target_obj->pending_write_domain) { | |
673a394b EA |
3409 | DRM_ERROR("Write domain conflict: " |
3410 | "obj %p target %d offset %d " | |
3411 | "new %08x old %08x\n", | |
40a5f0de EA |
3412 | obj, reloc->target_handle, |
3413 | (int) reloc->offset, | |
3414 | reloc->write_domain, | |
673a394b EA |
3415 | target_obj->pending_write_domain); |
3416 | drm_gem_object_unreference(target_obj); | |
3417 | i915_gem_object_unpin(obj); | |
3418 | return -EINVAL; | |
3419 | } | |
3420 | ||
40a5f0de EA |
3421 | target_obj->pending_read_domains |= reloc->read_domains; |
3422 | target_obj->pending_write_domain |= reloc->write_domain; | |
673a394b EA |
3423 | |
3424 | /* If the relocation already has the right value in it, no | |
3425 | * more work needs to be done. | |
3426 | */ | |
40a5f0de | 3427 | if (target_obj_priv->gtt_offset == reloc->presumed_offset) { |
673a394b EA |
3428 | drm_gem_object_unreference(target_obj); |
3429 | continue; | |
3430 | } | |
3431 | ||
8542a0bb CW |
3432 | /* Check that the relocation address is valid... */ |
3433 | if (reloc->offset > obj->size - 4) { | |
3434 | DRM_ERROR("Relocation beyond object bounds: " | |
3435 | "obj %p target %d offset %d size %d.\n", | |
3436 | obj, reloc->target_handle, | |
3437 | (int) reloc->offset, (int) obj->size); | |
3438 | drm_gem_object_unreference(target_obj); | |
3439 | i915_gem_object_unpin(obj); | |
3440 | return -EINVAL; | |
3441 | } | |
3442 | if (reloc->offset & 3) { | |
3443 | DRM_ERROR("Relocation not 4-byte aligned: " | |
3444 | "obj %p target %d offset %d.\n", | |
3445 | obj, reloc->target_handle, | |
3446 | (int) reloc->offset); | |
3447 | drm_gem_object_unreference(target_obj); | |
3448 | i915_gem_object_unpin(obj); | |
3449 | return -EINVAL; | |
3450 | } | |
3451 | ||
3452 | /* and points to somewhere within the target object. */ | |
3453 | if (reloc->delta >= target_obj->size) { | |
3454 | DRM_ERROR("Relocation beyond target object bounds: " | |
3455 | "obj %p target %d delta %d size %d.\n", | |
3456 | obj, reloc->target_handle, | |
3457 | (int) reloc->delta, (int) target_obj->size); | |
3458 | drm_gem_object_unreference(target_obj); | |
3459 | i915_gem_object_unpin(obj); | |
3460 | return -EINVAL; | |
3461 | } | |
3462 | ||
2ef7eeaa EA |
3463 | ret = i915_gem_object_set_to_gtt_domain(obj, 1); |
3464 | if (ret != 0) { | |
3465 | drm_gem_object_unreference(target_obj); | |
3466 | i915_gem_object_unpin(obj); | |
1cdf7fef | 3467 | return ret; |
673a394b EA |
3468 | } |
3469 | ||
3470 | /* Map the page containing the relocation we're going to | |
3471 | * perform. | |
3472 | */ | |
40a5f0de | 3473 | reloc_offset = obj_priv->gtt_offset + reloc->offset; |
0839ccb8 KP |
3474 | reloc_page = io_mapping_map_atomic_wc(dev_priv->mm.gtt_mapping, |
3475 | (reloc_offset & | |
fca3ec01 CW |
3476 | ~(PAGE_SIZE - 1)), |
3477 | KM_USER0); | |
3043c60c | 3478 | reloc_entry = (uint32_t __iomem *)(reloc_page + |
0839ccb8 | 3479 | (reloc_offset & (PAGE_SIZE - 1))); |
40a5f0de | 3480 | reloc_val = target_obj_priv->gtt_offset + reloc->delta; |
673a394b | 3481 | |
673a394b | 3482 | writel(reloc_val, reloc_entry); |
fca3ec01 | 3483 | io_mapping_unmap_atomic(reloc_page, KM_USER0); |
673a394b | 3484 | |
40a5f0de EA |
3485 | /* The updated presumed offset for this entry will be |
3486 | * copied back out to the user. | |
673a394b | 3487 | */ |
40a5f0de | 3488 | reloc->presumed_offset = target_obj_priv->gtt_offset; |
673a394b EA |
3489 | |
3490 | drm_gem_object_unreference(target_obj); | |
3491 | } | |
3492 | ||
673a394b EA |
3493 | return 0; |
3494 | } | |
3495 | ||
673a394b EA |
3496 | /* Throttle our rendering by waiting until the ring has completed our requests |
3497 | * emitted over 20 msec ago. | |
3498 | * | |
b962442e EA |
3499 | * Note that if we were to use the current jiffies each time around the loop, |
3500 | * we wouldn't escape the function with any frames outstanding if the time to | |
3501 | * render a frame was over 20ms. | |
3502 | * | |
673a394b EA |
3503 | * This should get us reasonable parallelism between CPU and GPU but also |
3504 | * relatively low latency when blocking on a particular request to finish. | |
3505 | */ | |
3506 | static int | |
f787a5f5 | 3507 | i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file) |
673a394b | 3508 | { |
f787a5f5 CW |
3509 | struct drm_i915_private *dev_priv = dev->dev_private; |
3510 | struct drm_i915_file_private *file_priv = file->driver_priv; | |
b962442e | 3511 | unsigned long recent_enough = jiffies - msecs_to_jiffies(20); |
f787a5f5 CW |
3512 | struct drm_i915_gem_request *request; |
3513 | struct intel_ring_buffer *ring = NULL; | |
3514 | u32 seqno = 0; | |
3515 | int ret; | |
673a394b | 3516 | |
1c25595f | 3517 | spin_lock(&file_priv->mm.lock); |
f787a5f5 | 3518 | list_for_each_entry(request, &file_priv->mm.request_list, client_list) { |
b962442e EA |
3519 | if (time_after_eq(request->emitted_jiffies, recent_enough)) |
3520 | break; | |
3521 | ||
f787a5f5 CW |
3522 | ring = request->ring; |
3523 | seqno = request->seqno; | |
b962442e | 3524 | } |
1c25595f | 3525 | spin_unlock(&file_priv->mm.lock); |
f787a5f5 CW |
3526 | |
3527 | if (seqno == 0) | |
3528 | return 0; | |
3529 | ||
3530 | ret = 0; | |
3531 | if (!i915_seqno_passed(ring->get_seqno(dev, ring), seqno)) { | |
3532 | /* And wait for the seqno passing without holding any locks and | |
3533 | * causing extra latency for others. This is safe as the irq | |
3534 | * generation is designed to be run atomically and so is | |
3535 | * lockless. | |
3536 | */ | |
3537 | ring->user_irq_get(dev, ring); | |
3538 | ret = wait_event_interruptible(ring->irq_queue, | |
3539 | i915_seqno_passed(ring->get_seqno(dev, ring), seqno) | |
3540 | || atomic_read(&dev_priv->mm.wedged)); | |
3541 | ring->user_irq_put(dev, ring); | |
3542 | ||
3543 | if (ret == 0 && atomic_read(&dev_priv->mm.wedged)) | |
3544 | ret = -EIO; | |
3545 | } | |
3546 | ||
3547 | if (ret == 0) | |
3548 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, 0); | |
b962442e | 3549 | |
673a394b EA |
3550 | return ret; |
3551 | } | |
3552 | ||
40a5f0de | 3553 | static int |
76446cac | 3554 | i915_gem_get_relocs_from_user(struct drm_i915_gem_exec_object2 *exec_list, |
40a5f0de EA |
3555 | uint32_t buffer_count, |
3556 | struct drm_i915_gem_relocation_entry **relocs) | |
3557 | { | |
3558 | uint32_t reloc_count = 0, reloc_index = 0, i; | |
3559 | int ret; | |
3560 | ||
3561 | *relocs = NULL; | |
3562 | for (i = 0; i < buffer_count; i++) { | |
3563 | if (reloc_count + exec_list[i].relocation_count < reloc_count) | |
3564 | return -EINVAL; | |
3565 | reloc_count += exec_list[i].relocation_count; | |
3566 | } | |
3567 | ||
8e7d2b2c | 3568 | *relocs = drm_calloc_large(reloc_count, sizeof(**relocs)); |
76446cac JB |
3569 | if (*relocs == NULL) { |
3570 | DRM_ERROR("failed to alloc relocs, count %d\n", reloc_count); | |
40a5f0de | 3571 | return -ENOMEM; |
76446cac | 3572 | } |
40a5f0de EA |
3573 | |
3574 | for (i = 0; i < buffer_count; i++) { | |
3575 | struct drm_i915_gem_relocation_entry __user *user_relocs; | |
3576 | ||
3577 | user_relocs = (void __user *)(uintptr_t)exec_list[i].relocs_ptr; | |
3578 | ||
3579 | ret = copy_from_user(&(*relocs)[reloc_index], | |
3580 | user_relocs, | |
3581 | exec_list[i].relocation_count * | |
3582 | sizeof(**relocs)); | |
3583 | if (ret != 0) { | |
8e7d2b2c | 3584 | drm_free_large(*relocs); |
40a5f0de | 3585 | *relocs = NULL; |
2bc43b5c | 3586 | return -EFAULT; |
40a5f0de EA |
3587 | } |
3588 | ||
3589 | reloc_index += exec_list[i].relocation_count; | |
3590 | } | |
3591 | ||
2bc43b5c | 3592 | return 0; |
40a5f0de EA |
3593 | } |
3594 | ||
3595 | static int | |
76446cac | 3596 | i915_gem_put_relocs_to_user(struct drm_i915_gem_exec_object2 *exec_list, |
40a5f0de EA |
3597 | uint32_t buffer_count, |
3598 | struct drm_i915_gem_relocation_entry *relocs) | |
3599 | { | |
3600 | uint32_t reloc_count = 0, i; | |
2bc43b5c | 3601 | int ret = 0; |
40a5f0de | 3602 | |
93533c29 CW |
3603 | if (relocs == NULL) |
3604 | return 0; | |
3605 | ||
40a5f0de EA |
3606 | for (i = 0; i < buffer_count; i++) { |
3607 | struct drm_i915_gem_relocation_entry __user *user_relocs; | |
2bc43b5c | 3608 | int unwritten; |
40a5f0de EA |
3609 | |
3610 | user_relocs = (void __user *)(uintptr_t)exec_list[i].relocs_ptr; | |
3611 | ||
2bc43b5c FM |
3612 | unwritten = copy_to_user(user_relocs, |
3613 | &relocs[reloc_count], | |
3614 | exec_list[i].relocation_count * | |
3615 | sizeof(*relocs)); | |
3616 | ||
3617 | if (unwritten) { | |
3618 | ret = -EFAULT; | |
3619 | goto err; | |
40a5f0de EA |
3620 | } |
3621 | ||
3622 | reloc_count += exec_list[i].relocation_count; | |
3623 | } | |
3624 | ||
2bc43b5c | 3625 | err: |
8e7d2b2c | 3626 | drm_free_large(relocs); |
40a5f0de EA |
3627 | |
3628 | return ret; | |
3629 | } | |
3630 | ||
83d60795 | 3631 | static int |
76446cac | 3632 | i915_gem_check_execbuffer (struct drm_i915_gem_execbuffer2 *exec, |
83d60795 CW |
3633 | uint64_t exec_offset) |
3634 | { | |
3635 | uint32_t exec_start, exec_len; | |
3636 | ||
3637 | exec_start = (uint32_t) exec_offset + exec->batch_start_offset; | |
3638 | exec_len = (uint32_t) exec->batch_len; | |
3639 | ||
3640 | if ((exec_start | exec_len) & 0x7) | |
3641 | return -EINVAL; | |
3642 | ||
3643 | if (!exec_start) | |
3644 | return -EINVAL; | |
3645 | ||
3646 | return 0; | |
3647 | } | |
3648 | ||
8dc5d147 | 3649 | static int |
76446cac JB |
3650 | i915_gem_do_execbuffer(struct drm_device *dev, void *data, |
3651 | struct drm_file *file_priv, | |
3652 | struct drm_i915_gem_execbuffer2 *args, | |
3653 | struct drm_i915_gem_exec_object2 *exec_list) | |
673a394b EA |
3654 | { |
3655 | drm_i915_private_t *dev_priv = dev->dev_private; | |
673a394b EA |
3656 | struct drm_gem_object **object_list = NULL; |
3657 | struct drm_gem_object *batch_obj; | |
b70d11da | 3658 | struct drm_i915_gem_object *obj_priv; |
201361a5 | 3659 | struct drm_clip_rect *cliprects = NULL; |
93533c29 | 3660 | struct drm_i915_gem_relocation_entry *relocs = NULL; |
8dc5d147 | 3661 | struct drm_i915_gem_request *request = NULL; |
30dbf0c0 | 3662 | int ret, ret2, i, pinned = 0; |
673a394b | 3663 | uint64_t exec_offset; |
5c12a07e | 3664 | uint32_t reloc_index; |
6b95a207 | 3665 | int pin_tries, flips; |
673a394b | 3666 | |
852835f3 ZN |
3667 | struct intel_ring_buffer *ring = NULL; |
3668 | ||
30dbf0c0 CW |
3669 | ret = i915_gem_check_is_wedged(dev); |
3670 | if (ret) | |
3671 | return ret; | |
3672 | ||
673a394b EA |
3673 | #if WATCH_EXEC |
3674 | DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n", | |
3675 | (int) args->buffers_ptr, args->buffer_count, args->batch_len); | |
3676 | #endif | |
d1b851fc ZN |
3677 | if (args->flags & I915_EXEC_BSD) { |
3678 | if (!HAS_BSD(dev)) { | |
3679 | DRM_ERROR("execbuf with wrong flag\n"); | |
3680 | return -EINVAL; | |
3681 | } | |
3682 | ring = &dev_priv->bsd_ring; | |
3683 | } else { | |
3684 | ring = &dev_priv->render_ring; | |
3685 | } | |
3686 | ||
4f481ed2 EA |
3687 | if (args->buffer_count < 1) { |
3688 | DRM_ERROR("execbuf with %d buffers\n", args->buffer_count); | |
3689 | return -EINVAL; | |
3690 | } | |
c8e0f93a | 3691 | object_list = drm_malloc_ab(sizeof(*object_list), args->buffer_count); |
76446cac JB |
3692 | if (object_list == NULL) { |
3693 | DRM_ERROR("Failed to allocate object list for %d buffers\n", | |
673a394b EA |
3694 | args->buffer_count); |
3695 | ret = -ENOMEM; | |
3696 | goto pre_mutex_err; | |
3697 | } | |
673a394b | 3698 | |
201361a5 | 3699 | if (args->num_cliprects != 0) { |
9a298b2a EA |
3700 | cliprects = kcalloc(args->num_cliprects, sizeof(*cliprects), |
3701 | GFP_KERNEL); | |
a40e8d31 OA |
3702 | if (cliprects == NULL) { |
3703 | ret = -ENOMEM; | |
201361a5 | 3704 | goto pre_mutex_err; |
a40e8d31 | 3705 | } |
201361a5 EA |
3706 | |
3707 | ret = copy_from_user(cliprects, | |
3708 | (struct drm_clip_rect __user *) | |
3709 | (uintptr_t) args->cliprects_ptr, | |
3710 | sizeof(*cliprects) * args->num_cliprects); | |
3711 | if (ret != 0) { | |
3712 | DRM_ERROR("copy %d cliprects failed: %d\n", | |
3713 | args->num_cliprects, ret); | |
c877cdce | 3714 | ret = -EFAULT; |
201361a5 EA |
3715 | goto pre_mutex_err; |
3716 | } | |
3717 | } | |
3718 | ||
8dc5d147 CW |
3719 | request = kzalloc(sizeof(*request), GFP_KERNEL); |
3720 | if (request == NULL) { | |
3721 | ret = -ENOMEM; | |
3722 | goto pre_mutex_err; | |
3723 | } | |
3724 | ||
40a5f0de EA |
3725 | ret = i915_gem_get_relocs_from_user(exec_list, args->buffer_count, |
3726 | &relocs); | |
3727 | if (ret != 0) | |
3728 | goto pre_mutex_err; | |
3729 | ||
76c1dec1 CW |
3730 | ret = i915_mutex_lock_interruptible(dev); |
3731 | if (ret) | |
3732 | goto pre_mutex_err; | |
673a394b | 3733 | |
673a394b | 3734 | if (dev_priv->mm.suspended) { |
673a394b | 3735 | mutex_unlock(&dev->struct_mutex); |
a198bc80 CW |
3736 | ret = -EBUSY; |
3737 | goto pre_mutex_err; | |
673a394b EA |
3738 | } |
3739 | ||
ac94a962 | 3740 | /* Look up object handles */ |
673a394b EA |
3741 | for (i = 0; i < args->buffer_count; i++) { |
3742 | object_list[i] = drm_gem_object_lookup(dev, file_priv, | |
3743 | exec_list[i].handle); | |
3744 | if (object_list[i] == NULL) { | |
3745 | DRM_ERROR("Invalid object handle %d at index %d\n", | |
3746 | exec_list[i].handle, i); | |
0ce907f8 CW |
3747 | /* prevent error path from reading uninitialized data */ |
3748 | args->buffer_count = i + 1; | |
bf79cb91 | 3749 | ret = -ENOENT; |
673a394b EA |
3750 | goto err; |
3751 | } | |
b70d11da | 3752 | |
23010e43 | 3753 | obj_priv = to_intel_bo(object_list[i]); |
b70d11da KH |
3754 | if (obj_priv->in_execbuffer) { |
3755 | DRM_ERROR("Object %p appears more than once in object list\n", | |
3756 | object_list[i]); | |
0ce907f8 CW |
3757 | /* prevent error path from reading uninitialized data */ |
3758 | args->buffer_count = i + 1; | |
bf79cb91 | 3759 | ret = -EINVAL; |
b70d11da KH |
3760 | goto err; |
3761 | } | |
3762 | obj_priv->in_execbuffer = true; | |
ac94a962 | 3763 | } |
673a394b | 3764 | |
ac94a962 KP |
3765 | /* Pin and relocate */ |
3766 | for (pin_tries = 0; ; pin_tries++) { | |
3767 | ret = 0; | |
40a5f0de EA |
3768 | reloc_index = 0; |
3769 | ||
ac94a962 KP |
3770 | for (i = 0; i < args->buffer_count; i++) { |
3771 | object_list[i]->pending_read_domains = 0; | |
3772 | object_list[i]->pending_write_domain = 0; | |
3773 | ret = i915_gem_object_pin_and_relocate(object_list[i], | |
3774 | file_priv, | |
40a5f0de EA |
3775 | &exec_list[i], |
3776 | &relocs[reloc_index]); | |
ac94a962 KP |
3777 | if (ret) |
3778 | break; | |
3779 | pinned = i + 1; | |
40a5f0de | 3780 | reloc_index += exec_list[i].relocation_count; |
ac94a962 KP |
3781 | } |
3782 | /* success */ | |
3783 | if (ret == 0) | |
3784 | break; | |
3785 | ||
3786 | /* error other than GTT full, or we've already tried again */ | |
2939e1f5 | 3787 | if (ret != -ENOSPC || pin_tries >= 1) { |
07f73f69 CW |
3788 | if (ret != -ERESTARTSYS) { |
3789 | unsigned long long total_size = 0; | |
3d1cc470 CW |
3790 | int num_fences = 0; |
3791 | for (i = 0; i < args->buffer_count; i++) { | |
43b27f40 | 3792 | obj_priv = to_intel_bo(object_list[i]); |
3d1cc470 | 3793 | |
07f73f69 | 3794 | total_size += object_list[i]->size; |
3d1cc470 CW |
3795 | num_fences += |
3796 | exec_list[i].flags & EXEC_OBJECT_NEEDS_FENCE && | |
3797 | obj_priv->tiling_mode != I915_TILING_NONE; | |
3798 | } | |
3799 | DRM_ERROR("Failed to pin buffer %d of %d, total %llu bytes, %d fences: %d\n", | |
07f73f69 | 3800 | pinned+1, args->buffer_count, |
3d1cc470 CW |
3801 | total_size, num_fences, |
3802 | ret); | |
73aa808f CW |
3803 | DRM_ERROR("%u objects [%u pinned, %u GTT], " |
3804 | "%zu object bytes [%zu pinned], " | |
3805 | "%zu /%zu gtt bytes\n", | |
3806 | dev_priv->mm.object_count, | |
3807 | dev_priv->mm.pin_count, | |
3808 | dev_priv->mm.gtt_count, | |
3809 | dev_priv->mm.object_memory, | |
3810 | dev_priv->mm.pin_memory, | |
3811 | dev_priv->mm.gtt_memory, | |
3812 | dev_priv->mm.gtt_total); | |
07f73f69 | 3813 | } |
673a394b EA |
3814 | goto err; |
3815 | } | |
ac94a962 KP |
3816 | |
3817 | /* unpin all of our buffers */ | |
3818 | for (i = 0; i < pinned; i++) | |
3819 | i915_gem_object_unpin(object_list[i]); | |
b1177636 | 3820 | pinned = 0; |
ac94a962 KP |
3821 | |
3822 | /* evict everyone we can from the aperture */ | |
3823 | ret = i915_gem_evict_everything(dev); | |
07f73f69 | 3824 | if (ret && ret != -ENOSPC) |
ac94a962 | 3825 | goto err; |
673a394b EA |
3826 | } |
3827 | ||
3828 | /* Set the pending read domains for the batch buffer to COMMAND */ | |
3829 | batch_obj = object_list[args->buffer_count-1]; | |
5f26a2c7 CW |
3830 | if (batch_obj->pending_write_domain) { |
3831 | DRM_ERROR("Attempting to use self-modifying batch buffer\n"); | |
3832 | ret = -EINVAL; | |
3833 | goto err; | |
3834 | } | |
3835 | batch_obj->pending_read_domains |= I915_GEM_DOMAIN_COMMAND; | |
673a394b | 3836 | |
83d60795 CW |
3837 | /* Sanity check the batch buffer, prior to moving objects */ |
3838 | exec_offset = exec_list[args->buffer_count - 1].offset; | |
3839 | ret = i915_gem_check_execbuffer (args, exec_offset); | |
3840 | if (ret != 0) { | |
3841 | DRM_ERROR("execbuf with invalid offset/length\n"); | |
3842 | goto err; | |
3843 | } | |
3844 | ||
646f0f6e KP |
3845 | /* Zero the global flush/invalidate flags. These |
3846 | * will be modified as new domains are computed | |
3847 | * for each object | |
3848 | */ | |
3849 | dev->invalidate_domains = 0; | |
3850 | dev->flush_domains = 0; | |
9220434a | 3851 | dev_priv->mm.flush_rings = 0; |
646f0f6e | 3852 | |
673a394b EA |
3853 | for (i = 0; i < args->buffer_count; i++) { |
3854 | struct drm_gem_object *obj = object_list[i]; | |
673a394b | 3855 | |
646f0f6e | 3856 | /* Compute new gpu domains and update invalidate/flush */ |
8b0e378a | 3857 | i915_gem_object_set_to_gpu_domain(obj); |
673a394b EA |
3858 | } |
3859 | ||
646f0f6e KP |
3860 | if (dev->invalidate_domains | dev->flush_domains) { |
3861 | #if WATCH_EXEC | |
3862 | DRM_INFO("%s: invalidate_domains %08x flush_domains %08x\n", | |
3863 | __func__, | |
3864 | dev->invalidate_domains, | |
3865 | dev->flush_domains); | |
3866 | #endif | |
c78ec30b | 3867 | i915_gem_flush(dev, file_priv, |
646f0f6e | 3868 | dev->invalidate_domains, |
9220434a CW |
3869 | dev->flush_domains, |
3870 | dev_priv->mm.flush_rings); | |
a6910434 DV |
3871 | } |
3872 | ||
efbeed96 EA |
3873 | for (i = 0; i < args->buffer_count; i++) { |
3874 | struct drm_gem_object *obj = object_list[i]; | |
23010e43 | 3875 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
1c5d22f7 | 3876 | uint32_t old_write_domain = obj->write_domain; |
efbeed96 EA |
3877 | |
3878 | obj->write_domain = obj->pending_write_domain; | |
99fcb766 DV |
3879 | if (obj->write_domain) |
3880 | list_move_tail(&obj_priv->gpu_write_list, | |
3881 | &dev_priv->mm.gpu_write_list); | |
99fcb766 | 3882 | |
1c5d22f7 CW |
3883 | trace_i915_gem_object_change_domain(obj, |
3884 | obj->read_domains, | |
3885 | old_write_domain); | |
efbeed96 EA |
3886 | } |
3887 | ||
673a394b EA |
3888 | #if WATCH_COHERENCY |
3889 | for (i = 0; i < args->buffer_count; i++) { | |
3890 | i915_gem_object_check_coherency(object_list[i], | |
3891 | exec_list[i].handle); | |
3892 | } | |
3893 | #endif | |
3894 | ||
673a394b | 3895 | #if WATCH_EXEC |
6911a9b8 | 3896 | i915_gem_dump_object(batch_obj, |
673a394b EA |
3897 | args->batch_len, |
3898 | __func__, | |
3899 | ~0); | |
3900 | #endif | |
3901 | ||
e59f2bac CW |
3902 | /* Check for any pending flips. As we only maintain a flip queue depth |
3903 | * of 1, we can simply insert a WAIT for the next display flip prior | |
3904 | * to executing the batch and avoid stalling the CPU. | |
3905 | */ | |
3906 | flips = 0; | |
3907 | for (i = 0; i < args->buffer_count; i++) { | |
3908 | if (object_list[i]->write_domain) | |
3909 | flips |= atomic_read(&to_intel_bo(object_list[i])->pending_flip); | |
3910 | } | |
3911 | if (flips) { | |
3912 | int plane, flip_mask; | |
3913 | ||
3914 | for (plane = 0; flips >> plane; plane++) { | |
3915 | if (((flips >> plane) & 1) == 0) | |
3916 | continue; | |
3917 | ||
3918 | if (plane) | |
3919 | flip_mask = MI_WAIT_FOR_PLANE_B_FLIP; | |
3920 | else | |
3921 | flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; | |
3922 | ||
3923 | intel_ring_begin(dev, ring, 2); | |
3924 | intel_ring_emit(dev, ring, | |
3925 | MI_WAIT_FOR_EVENT | flip_mask); | |
3926 | intel_ring_emit(dev, ring, MI_NOOP); | |
3927 | intel_ring_advance(dev, ring); | |
3928 | } | |
3929 | } | |
3930 | ||
673a394b | 3931 | /* Exec the batchbuffer */ |
852835f3 | 3932 | ret = ring->dispatch_gem_execbuffer(dev, ring, args, |
e59f2bac | 3933 | cliprects, exec_offset); |
673a394b EA |
3934 | if (ret) { |
3935 | DRM_ERROR("dispatch failed %d\n", ret); | |
3936 | goto err; | |
3937 | } | |
3938 | ||
3939 | /* | |
3940 | * Ensure that the commands in the batch buffer are | |
3941 | * finished before the interrupt fires | |
3942 | */ | |
8a1a49f9 | 3943 | i915_retire_commands(dev, ring); |
673a394b | 3944 | |
617dbe27 DV |
3945 | for (i = 0; i < args->buffer_count; i++) { |
3946 | struct drm_gem_object *obj = object_list[i]; | |
3947 | obj_priv = to_intel_bo(obj); | |
3948 | ||
3949 | i915_gem_object_move_to_active(obj, ring); | |
617dbe27 | 3950 | } |
a56ba56c | 3951 | |
5c12a07e | 3952 | i915_add_request(dev, file_priv, request, ring); |
8dc5d147 | 3953 | request = NULL; |
673a394b | 3954 | |
673a394b | 3955 | err: |
aad87dff JL |
3956 | for (i = 0; i < pinned; i++) |
3957 | i915_gem_object_unpin(object_list[i]); | |
3958 | ||
b70d11da KH |
3959 | for (i = 0; i < args->buffer_count; i++) { |
3960 | if (object_list[i]) { | |
23010e43 | 3961 | obj_priv = to_intel_bo(object_list[i]); |
b70d11da KH |
3962 | obj_priv->in_execbuffer = false; |
3963 | } | |
aad87dff | 3964 | drm_gem_object_unreference(object_list[i]); |
b70d11da | 3965 | } |
673a394b | 3966 | |
673a394b EA |
3967 | mutex_unlock(&dev->struct_mutex); |
3968 | ||
93533c29 | 3969 | pre_mutex_err: |
40a5f0de EA |
3970 | /* Copy the updated relocations out regardless of current error |
3971 | * state. Failure to update the relocs would mean that the next | |
3972 | * time userland calls execbuf, it would do so with presumed offset | |
3973 | * state that didn't match the actual object state. | |
3974 | */ | |
3975 | ret2 = i915_gem_put_relocs_to_user(exec_list, args->buffer_count, | |
3976 | relocs); | |
3977 | if (ret2 != 0) { | |
3978 | DRM_ERROR("Failed to copy relocations back out: %d\n", ret2); | |
3979 | ||
3980 | if (ret == 0) | |
3981 | ret = ret2; | |
3982 | } | |
3983 | ||
8e7d2b2c | 3984 | drm_free_large(object_list); |
9a298b2a | 3985 | kfree(cliprects); |
8dc5d147 | 3986 | kfree(request); |
673a394b EA |
3987 | |
3988 | return ret; | |
3989 | } | |
3990 | ||
76446cac JB |
3991 | /* |
3992 | * Legacy execbuffer just creates an exec2 list from the original exec object | |
3993 | * list array and passes it to the real function. | |
3994 | */ | |
3995 | int | |
3996 | i915_gem_execbuffer(struct drm_device *dev, void *data, | |
3997 | struct drm_file *file_priv) | |
3998 | { | |
3999 | struct drm_i915_gem_execbuffer *args = data; | |
4000 | struct drm_i915_gem_execbuffer2 exec2; | |
4001 | struct drm_i915_gem_exec_object *exec_list = NULL; | |
4002 | struct drm_i915_gem_exec_object2 *exec2_list = NULL; | |
4003 | int ret, i; | |
4004 | ||
4005 | #if WATCH_EXEC | |
4006 | DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n", | |
4007 | (int) args->buffers_ptr, args->buffer_count, args->batch_len); | |
4008 | #endif | |
4009 | ||
4010 | if (args->buffer_count < 1) { | |
4011 | DRM_ERROR("execbuf with %d buffers\n", args->buffer_count); | |
4012 | return -EINVAL; | |
4013 | } | |
4014 | ||
4015 | /* Copy in the exec list from userland */ | |
4016 | exec_list = drm_malloc_ab(sizeof(*exec_list), args->buffer_count); | |
4017 | exec2_list = drm_malloc_ab(sizeof(*exec2_list), args->buffer_count); | |
4018 | if (exec_list == NULL || exec2_list == NULL) { | |
4019 | DRM_ERROR("Failed to allocate exec list for %d buffers\n", | |
4020 | args->buffer_count); | |
4021 | drm_free_large(exec_list); | |
4022 | drm_free_large(exec2_list); | |
4023 | return -ENOMEM; | |
4024 | } | |
4025 | ret = copy_from_user(exec_list, | |
4026 | (struct drm_i915_relocation_entry __user *) | |
4027 | (uintptr_t) args->buffers_ptr, | |
4028 | sizeof(*exec_list) * args->buffer_count); | |
4029 | if (ret != 0) { | |
4030 | DRM_ERROR("copy %d exec entries failed %d\n", | |
4031 | args->buffer_count, ret); | |
4032 | drm_free_large(exec_list); | |
4033 | drm_free_large(exec2_list); | |
4034 | return -EFAULT; | |
4035 | } | |
4036 | ||
4037 | for (i = 0; i < args->buffer_count; i++) { | |
4038 | exec2_list[i].handle = exec_list[i].handle; | |
4039 | exec2_list[i].relocation_count = exec_list[i].relocation_count; | |
4040 | exec2_list[i].relocs_ptr = exec_list[i].relocs_ptr; | |
4041 | exec2_list[i].alignment = exec_list[i].alignment; | |
4042 | exec2_list[i].offset = exec_list[i].offset; | |
a6c45cf0 | 4043 | if (INTEL_INFO(dev)->gen < 4) |
76446cac JB |
4044 | exec2_list[i].flags = EXEC_OBJECT_NEEDS_FENCE; |
4045 | else | |
4046 | exec2_list[i].flags = 0; | |
4047 | } | |
4048 | ||
4049 | exec2.buffers_ptr = args->buffers_ptr; | |
4050 | exec2.buffer_count = args->buffer_count; | |
4051 | exec2.batch_start_offset = args->batch_start_offset; | |
4052 | exec2.batch_len = args->batch_len; | |
4053 | exec2.DR1 = args->DR1; | |
4054 | exec2.DR4 = args->DR4; | |
4055 | exec2.num_cliprects = args->num_cliprects; | |
4056 | exec2.cliprects_ptr = args->cliprects_ptr; | |
852835f3 | 4057 | exec2.flags = I915_EXEC_RENDER; |
76446cac JB |
4058 | |
4059 | ret = i915_gem_do_execbuffer(dev, data, file_priv, &exec2, exec2_list); | |
4060 | if (!ret) { | |
4061 | /* Copy the new buffer offsets back to the user's exec list. */ | |
4062 | for (i = 0; i < args->buffer_count; i++) | |
4063 | exec_list[i].offset = exec2_list[i].offset; | |
4064 | /* ... and back out to userspace */ | |
4065 | ret = copy_to_user((struct drm_i915_relocation_entry __user *) | |
4066 | (uintptr_t) args->buffers_ptr, | |
4067 | exec_list, | |
4068 | sizeof(*exec_list) * args->buffer_count); | |
4069 | if (ret) { | |
4070 | ret = -EFAULT; | |
4071 | DRM_ERROR("failed to copy %d exec entries " | |
4072 | "back to user (%d)\n", | |
4073 | args->buffer_count, ret); | |
4074 | } | |
76446cac JB |
4075 | } |
4076 | ||
4077 | drm_free_large(exec_list); | |
4078 | drm_free_large(exec2_list); | |
4079 | return ret; | |
4080 | } | |
4081 | ||
4082 | int | |
4083 | i915_gem_execbuffer2(struct drm_device *dev, void *data, | |
4084 | struct drm_file *file_priv) | |
4085 | { | |
4086 | struct drm_i915_gem_execbuffer2 *args = data; | |
4087 | struct drm_i915_gem_exec_object2 *exec2_list = NULL; | |
4088 | int ret; | |
4089 | ||
4090 | #if WATCH_EXEC | |
4091 | DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n", | |
4092 | (int) args->buffers_ptr, args->buffer_count, args->batch_len); | |
4093 | #endif | |
4094 | ||
4095 | if (args->buffer_count < 1) { | |
4096 | DRM_ERROR("execbuf2 with %d buffers\n", args->buffer_count); | |
4097 | return -EINVAL; | |
4098 | } | |
4099 | ||
4100 | exec2_list = drm_malloc_ab(sizeof(*exec2_list), args->buffer_count); | |
4101 | if (exec2_list == NULL) { | |
4102 | DRM_ERROR("Failed to allocate exec list for %d buffers\n", | |
4103 | args->buffer_count); | |
4104 | return -ENOMEM; | |
4105 | } | |
4106 | ret = copy_from_user(exec2_list, | |
4107 | (struct drm_i915_relocation_entry __user *) | |
4108 | (uintptr_t) args->buffers_ptr, | |
4109 | sizeof(*exec2_list) * args->buffer_count); | |
4110 | if (ret != 0) { | |
4111 | DRM_ERROR("copy %d exec entries failed %d\n", | |
4112 | args->buffer_count, ret); | |
4113 | drm_free_large(exec2_list); | |
4114 | return -EFAULT; | |
4115 | } | |
4116 | ||
4117 | ret = i915_gem_do_execbuffer(dev, data, file_priv, args, exec2_list); | |
4118 | if (!ret) { | |
4119 | /* Copy the new buffer offsets back to the user's exec list. */ | |
4120 | ret = copy_to_user((struct drm_i915_relocation_entry __user *) | |
4121 | (uintptr_t) args->buffers_ptr, | |
4122 | exec2_list, | |
4123 | sizeof(*exec2_list) * args->buffer_count); | |
4124 | if (ret) { | |
4125 | ret = -EFAULT; | |
4126 | DRM_ERROR("failed to copy %d exec entries " | |
4127 | "back to user (%d)\n", | |
4128 | args->buffer_count, ret); | |
4129 | } | |
4130 | } | |
4131 | ||
4132 | drm_free_large(exec2_list); | |
4133 | return ret; | |
4134 | } | |
4135 | ||
673a394b EA |
4136 | int |
4137 | i915_gem_object_pin(struct drm_gem_object *obj, uint32_t alignment) | |
4138 | { | |
4139 | struct drm_device *dev = obj->dev; | |
f13d3f73 | 4140 | struct drm_i915_private *dev_priv = dev->dev_private; |
23010e43 | 4141 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
673a394b EA |
4142 | int ret; |
4143 | ||
778c3544 | 4144 | BUG_ON(obj_priv->pin_count == DRM_I915_GEM_OBJECT_MAX_PIN_COUNT); |
23bc5982 | 4145 | WARN_ON(i915_verify_lists(dev)); |
ac0c6b5a CW |
4146 | |
4147 | if (obj_priv->gtt_space != NULL) { | |
4148 | if (alignment == 0) | |
4149 | alignment = i915_gem_get_gtt_alignment(obj); | |
4150 | if (obj_priv->gtt_offset & (alignment - 1)) { | |
ae7d49d8 CW |
4151 | WARN(obj_priv->pin_count, |
4152 | "bo is already pinned with incorrect alignment:" | |
4153 | " offset=%x, req.alignment=%x\n", | |
4154 | obj_priv->gtt_offset, alignment); | |
ac0c6b5a CW |
4155 | ret = i915_gem_object_unbind(obj); |
4156 | if (ret) | |
4157 | return ret; | |
4158 | } | |
4159 | } | |
4160 | ||
673a394b EA |
4161 | if (obj_priv->gtt_space == NULL) { |
4162 | ret = i915_gem_object_bind_to_gtt(obj, alignment); | |
9731129c | 4163 | if (ret) |
673a394b | 4164 | return ret; |
22c344e9 | 4165 | } |
76446cac | 4166 | |
673a394b EA |
4167 | obj_priv->pin_count++; |
4168 | ||
4169 | /* If the object is not active and not pending a flush, | |
4170 | * remove it from the inactive list | |
4171 | */ | |
4172 | if (obj_priv->pin_count == 1) { | |
73aa808f | 4173 | i915_gem_info_add_pin(dev_priv, obj->size); |
f13d3f73 CW |
4174 | if (!obj_priv->active) |
4175 | list_move_tail(&obj_priv->list, | |
4176 | &dev_priv->mm.pinned_list); | |
673a394b | 4177 | } |
673a394b | 4178 | |
23bc5982 | 4179 | WARN_ON(i915_verify_lists(dev)); |
673a394b EA |
4180 | return 0; |
4181 | } | |
4182 | ||
4183 | void | |
4184 | i915_gem_object_unpin(struct drm_gem_object *obj) | |
4185 | { | |
4186 | struct drm_device *dev = obj->dev; | |
4187 | drm_i915_private_t *dev_priv = dev->dev_private; | |
23010e43 | 4188 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
673a394b | 4189 | |
23bc5982 | 4190 | WARN_ON(i915_verify_lists(dev)); |
673a394b EA |
4191 | obj_priv->pin_count--; |
4192 | BUG_ON(obj_priv->pin_count < 0); | |
4193 | BUG_ON(obj_priv->gtt_space == NULL); | |
4194 | ||
4195 | /* If the object is no longer pinned, and is | |
4196 | * neither active nor being flushed, then stick it on | |
4197 | * the inactive list | |
4198 | */ | |
4199 | if (obj_priv->pin_count == 0) { | |
f13d3f73 | 4200 | if (!obj_priv->active) |
673a394b EA |
4201 | list_move_tail(&obj_priv->list, |
4202 | &dev_priv->mm.inactive_list); | |
73aa808f | 4203 | i915_gem_info_remove_pin(dev_priv, obj->size); |
673a394b | 4204 | } |
23bc5982 | 4205 | WARN_ON(i915_verify_lists(dev)); |
673a394b EA |
4206 | } |
4207 | ||
4208 | int | |
4209 | i915_gem_pin_ioctl(struct drm_device *dev, void *data, | |
4210 | struct drm_file *file_priv) | |
4211 | { | |
4212 | struct drm_i915_gem_pin *args = data; | |
4213 | struct drm_gem_object *obj; | |
4214 | struct drm_i915_gem_object *obj_priv; | |
4215 | int ret; | |
4216 | ||
673a394b EA |
4217 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); |
4218 | if (obj == NULL) { | |
4219 | DRM_ERROR("Bad handle in i915_gem_pin_ioctl(): %d\n", | |
4220 | args->handle); | |
bf79cb91 | 4221 | return -ENOENT; |
673a394b | 4222 | } |
23010e43 | 4223 | obj_priv = to_intel_bo(obj); |
673a394b | 4224 | |
76c1dec1 CW |
4225 | ret = i915_mutex_lock_interruptible(dev); |
4226 | if (ret) { | |
4227 | drm_gem_object_unreference_unlocked(obj); | |
4228 | return ret; | |
4229 | } | |
4230 | ||
bb6baf76 CW |
4231 | if (obj_priv->madv != I915_MADV_WILLNEED) { |
4232 | DRM_ERROR("Attempting to pin a purgeable buffer\n"); | |
3ef94daa CW |
4233 | drm_gem_object_unreference(obj); |
4234 | mutex_unlock(&dev->struct_mutex); | |
4235 | return -EINVAL; | |
4236 | } | |
4237 | ||
79e53945 JB |
4238 | if (obj_priv->pin_filp != NULL && obj_priv->pin_filp != file_priv) { |
4239 | DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n", | |
4240 | args->handle); | |
96dec61d | 4241 | drm_gem_object_unreference(obj); |
673a394b | 4242 | mutex_unlock(&dev->struct_mutex); |
79e53945 JB |
4243 | return -EINVAL; |
4244 | } | |
4245 | ||
4246 | obj_priv->user_pin_count++; | |
4247 | obj_priv->pin_filp = file_priv; | |
4248 | if (obj_priv->user_pin_count == 1) { | |
4249 | ret = i915_gem_object_pin(obj, args->alignment); | |
4250 | if (ret != 0) { | |
4251 | drm_gem_object_unreference(obj); | |
4252 | mutex_unlock(&dev->struct_mutex); | |
4253 | return ret; | |
4254 | } | |
673a394b EA |
4255 | } |
4256 | ||
4257 | /* XXX - flush the CPU caches for pinned objects | |
4258 | * as the X server doesn't manage domains yet | |
4259 | */ | |
e47c68e9 | 4260 | i915_gem_object_flush_cpu_write_domain(obj); |
673a394b EA |
4261 | args->offset = obj_priv->gtt_offset; |
4262 | drm_gem_object_unreference(obj); | |
4263 | mutex_unlock(&dev->struct_mutex); | |
4264 | ||
4265 | return 0; | |
4266 | } | |
4267 | ||
4268 | int | |
4269 | i915_gem_unpin_ioctl(struct drm_device *dev, void *data, | |
4270 | struct drm_file *file_priv) | |
4271 | { | |
4272 | struct drm_i915_gem_pin *args = data; | |
4273 | struct drm_gem_object *obj; | |
79e53945 | 4274 | struct drm_i915_gem_object *obj_priv; |
76c1dec1 | 4275 | int ret; |
673a394b EA |
4276 | |
4277 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); | |
4278 | if (obj == NULL) { | |
4279 | DRM_ERROR("Bad handle in i915_gem_unpin_ioctl(): %d\n", | |
4280 | args->handle); | |
bf79cb91 | 4281 | return -ENOENT; |
673a394b EA |
4282 | } |
4283 | ||
23010e43 | 4284 | obj_priv = to_intel_bo(obj); |
76c1dec1 CW |
4285 | |
4286 | ret = i915_mutex_lock_interruptible(dev); | |
4287 | if (ret) { | |
4288 | drm_gem_object_unreference_unlocked(obj); | |
4289 | return ret; | |
4290 | } | |
4291 | ||
79e53945 JB |
4292 | if (obj_priv->pin_filp != file_priv) { |
4293 | DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n", | |
4294 | args->handle); | |
4295 | drm_gem_object_unreference(obj); | |
4296 | mutex_unlock(&dev->struct_mutex); | |
4297 | return -EINVAL; | |
4298 | } | |
4299 | obj_priv->user_pin_count--; | |
4300 | if (obj_priv->user_pin_count == 0) { | |
4301 | obj_priv->pin_filp = NULL; | |
4302 | i915_gem_object_unpin(obj); | |
4303 | } | |
673a394b EA |
4304 | |
4305 | drm_gem_object_unreference(obj); | |
4306 | mutex_unlock(&dev->struct_mutex); | |
4307 | return 0; | |
4308 | } | |
4309 | ||
4310 | int | |
4311 | i915_gem_busy_ioctl(struct drm_device *dev, void *data, | |
4312 | struct drm_file *file_priv) | |
4313 | { | |
4314 | struct drm_i915_gem_busy *args = data; | |
4315 | struct drm_gem_object *obj; | |
4316 | struct drm_i915_gem_object *obj_priv; | |
30dbf0c0 CW |
4317 | int ret; |
4318 | ||
673a394b EA |
4319 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); |
4320 | if (obj == NULL) { | |
4321 | DRM_ERROR("Bad handle in i915_gem_busy_ioctl(): %d\n", | |
4322 | args->handle); | |
bf79cb91 | 4323 | return -ENOENT; |
673a394b EA |
4324 | } |
4325 | ||
76c1dec1 CW |
4326 | ret = i915_mutex_lock_interruptible(dev); |
4327 | if (ret) { | |
4328 | drm_gem_object_unreference_unlocked(obj); | |
4329 | return ret; | |
30dbf0c0 CW |
4330 | } |
4331 | ||
0be555b6 CW |
4332 | /* Count all active objects as busy, even if they are currently not used |
4333 | * by the gpu. Users of this interface expect objects to eventually | |
4334 | * become non-busy without any further actions, therefore emit any | |
4335 | * necessary flushes here. | |
c4de0a5d | 4336 | */ |
0be555b6 CW |
4337 | obj_priv = to_intel_bo(obj); |
4338 | args->busy = obj_priv->active; | |
4339 | if (args->busy) { | |
4340 | /* Unconditionally flush objects, even when the gpu still uses this | |
4341 | * object. Userspace calling this function indicates that it wants to | |
4342 | * use this buffer rather sooner than later, so issuing the required | |
4343 | * flush earlier is beneficial. | |
4344 | */ | |
c78ec30b CW |
4345 | if (obj->write_domain & I915_GEM_GPU_DOMAINS) |
4346 | i915_gem_flush_ring(dev, file_priv, | |
9220434a CW |
4347 | obj_priv->ring, |
4348 | 0, obj->write_domain); | |
0be555b6 CW |
4349 | |
4350 | /* Update the active list for the hardware's current position. | |
4351 | * Otherwise this only updates on a delayed timer or when irqs | |
4352 | * are actually unmasked, and our working set ends up being | |
4353 | * larger than required. | |
4354 | */ | |
4355 | i915_gem_retire_requests_ring(dev, obj_priv->ring); | |
4356 | ||
4357 | args->busy = obj_priv->active; | |
4358 | } | |
673a394b EA |
4359 | |
4360 | drm_gem_object_unreference(obj); | |
4361 | mutex_unlock(&dev->struct_mutex); | |
76c1dec1 | 4362 | return 0; |
673a394b EA |
4363 | } |
4364 | ||
4365 | int | |
4366 | i915_gem_throttle_ioctl(struct drm_device *dev, void *data, | |
4367 | struct drm_file *file_priv) | |
4368 | { | |
4369 | return i915_gem_ring_throttle(dev, file_priv); | |
4370 | } | |
4371 | ||
3ef94daa CW |
4372 | int |
4373 | i915_gem_madvise_ioctl(struct drm_device *dev, void *data, | |
4374 | struct drm_file *file_priv) | |
4375 | { | |
4376 | struct drm_i915_gem_madvise *args = data; | |
4377 | struct drm_gem_object *obj; | |
4378 | struct drm_i915_gem_object *obj_priv; | |
76c1dec1 | 4379 | int ret; |
3ef94daa CW |
4380 | |
4381 | switch (args->madv) { | |
4382 | case I915_MADV_DONTNEED: | |
4383 | case I915_MADV_WILLNEED: | |
4384 | break; | |
4385 | default: | |
4386 | return -EINVAL; | |
4387 | } | |
4388 | ||
4389 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); | |
4390 | if (obj == NULL) { | |
4391 | DRM_ERROR("Bad handle in i915_gem_madvise_ioctl(): %d\n", | |
4392 | args->handle); | |
bf79cb91 | 4393 | return -ENOENT; |
3ef94daa | 4394 | } |
23010e43 | 4395 | obj_priv = to_intel_bo(obj); |
3ef94daa | 4396 | |
76c1dec1 CW |
4397 | ret = i915_mutex_lock_interruptible(dev); |
4398 | if (ret) { | |
4399 | drm_gem_object_unreference_unlocked(obj); | |
4400 | return ret; | |
4401 | } | |
4402 | ||
3ef94daa CW |
4403 | if (obj_priv->pin_count) { |
4404 | drm_gem_object_unreference(obj); | |
4405 | mutex_unlock(&dev->struct_mutex); | |
4406 | ||
4407 | DRM_ERROR("Attempted i915_gem_madvise_ioctl() on a pinned object\n"); | |
4408 | return -EINVAL; | |
4409 | } | |
4410 | ||
bb6baf76 CW |
4411 | if (obj_priv->madv != __I915_MADV_PURGED) |
4412 | obj_priv->madv = args->madv; | |
3ef94daa | 4413 | |
2d7ef395 CW |
4414 | /* if the object is no longer bound, discard its backing storage */ |
4415 | if (i915_gem_object_is_purgeable(obj_priv) && | |
4416 | obj_priv->gtt_space == NULL) | |
4417 | i915_gem_object_truncate(obj); | |
4418 | ||
bb6baf76 CW |
4419 | args->retained = obj_priv->madv != __I915_MADV_PURGED; |
4420 | ||
3ef94daa CW |
4421 | drm_gem_object_unreference(obj); |
4422 | mutex_unlock(&dev->struct_mutex); | |
4423 | ||
4424 | return 0; | |
4425 | } | |
4426 | ||
ac52bc56 DV |
4427 | struct drm_gem_object * i915_gem_alloc_object(struct drm_device *dev, |
4428 | size_t size) | |
4429 | { | |
73aa808f | 4430 | struct drm_i915_private *dev_priv = dev->dev_private; |
c397b908 | 4431 | struct drm_i915_gem_object *obj; |
ac52bc56 | 4432 | |
c397b908 DV |
4433 | obj = kzalloc(sizeof(*obj), GFP_KERNEL); |
4434 | if (obj == NULL) | |
4435 | return NULL; | |
673a394b | 4436 | |
c397b908 DV |
4437 | if (drm_gem_object_init(dev, &obj->base, size) != 0) { |
4438 | kfree(obj); | |
4439 | return NULL; | |
4440 | } | |
673a394b | 4441 | |
73aa808f CW |
4442 | i915_gem_info_add_obj(dev_priv, size); |
4443 | ||
c397b908 DV |
4444 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; |
4445 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; | |
673a394b | 4446 | |
c397b908 | 4447 | obj->agp_type = AGP_USER_MEMORY; |
62b8b215 | 4448 | obj->base.driver_private = NULL; |
c397b908 DV |
4449 | obj->fence_reg = I915_FENCE_REG_NONE; |
4450 | INIT_LIST_HEAD(&obj->list); | |
4451 | INIT_LIST_HEAD(&obj->gpu_write_list); | |
c397b908 | 4452 | obj->madv = I915_MADV_WILLNEED; |
de151cf6 | 4453 | |
c397b908 DV |
4454 | trace_i915_gem_object_create(&obj->base); |
4455 | ||
4456 | return &obj->base; | |
4457 | } | |
4458 | ||
4459 | int i915_gem_init_object(struct drm_gem_object *obj) | |
4460 | { | |
4461 | BUG(); | |
de151cf6 | 4462 | |
673a394b EA |
4463 | return 0; |
4464 | } | |
4465 | ||
be72615b | 4466 | static void i915_gem_free_object_tail(struct drm_gem_object *obj) |
673a394b | 4467 | { |
de151cf6 | 4468 | struct drm_device *dev = obj->dev; |
be72615b | 4469 | drm_i915_private_t *dev_priv = dev->dev_private; |
23010e43 | 4470 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
be72615b | 4471 | int ret; |
673a394b | 4472 | |
be72615b CW |
4473 | ret = i915_gem_object_unbind(obj); |
4474 | if (ret == -ERESTARTSYS) { | |
4475 | list_move(&obj_priv->list, | |
4476 | &dev_priv->mm.deferred_free_list); | |
4477 | return; | |
4478 | } | |
673a394b | 4479 | |
7e616158 CW |
4480 | if (obj_priv->mmap_offset) |
4481 | i915_gem_free_mmap_offset(obj); | |
de151cf6 | 4482 | |
c397b908 | 4483 | drm_gem_object_release(obj); |
73aa808f | 4484 | i915_gem_info_remove_obj(dev_priv, obj->size); |
c397b908 | 4485 | |
9a298b2a | 4486 | kfree(obj_priv->page_cpu_valid); |
280b713b | 4487 | kfree(obj_priv->bit_17); |
c397b908 | 4488 | kfree(obj_priv); |
673a394b EA |
4489 | } |
4490 | ||
be72615b CW |
4491 | void i915_gem_free_object(struct drm_gem_object *obj) |
4492 | { | |
4493 | struct drm_device *dev = obj->dev; | |
4494 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); | |
4495 | ||
4496 | trace_i915_gem_object_destroy(obj); | |
4497 | ||
4498 | while (obj_priv->pin_count > 0) | |
4499 | i915_gem_object_unpin(obj); | |
4500 | ||
4501 | if (obj_priv->phys_obj) | |
4502 | i915_gem_detach_phys_object(dev, obj); | |
4503 | ||
4504 | i915_gem_free_object_tail(obj); | |
4505 | } | |
4506 | ||
29105ccc CW |
4507 | int |
4508 | i915_gem_idle(struct drm_device *dev) | |
4509 | { | |
4510 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4511 | int ret; | |
28dfe52a | 4512 | |
29105ccc | 4513 | mutex_lock(&dev->struct_mutex); |
1c5d22f7 | 4514 | |
8187a2b7 | 4515 | if (dev_priv->mm.suspended || |
d1b851fc ZN |
4516 | (dev_priv->render_ring.gem_object == NULL) || |
4517 | (HAS_BSD(dev) && | |
4518 | dev_priv->bsd_ring.gem_object == NULL)) { | |
29105ccc CW |
4519 | mutex_unlock(&dev->struct_mutex); |
4520 | return 0; | |
28dfe52a EA |
4521 | } |
4522 | ||
29105ccc | 4523 | ret = i915_gpu_idle(dev); |
6dbe2772 KP |
4524 | if (ret) { |
4525 | mutex_unlock(&dev->struct_mutex); | |
673a394b | 4526 | return ret; |
6dbe2772 | 4527 | } |
673a394b | 4528 | |
29105ccc CW |
4529 | /* Under UMS, be paranoid and evict. */ |
4530 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) { | |
b47eb4a2 | 4531 | ret = i915_gem_evict_inactive(dev); |
29105ccc CW |
4532 | if (ret) { |
4533 | mutex_unlock(&dev->struct_mutex); | |
4534 | return ret; | |
4535 | } | |
4536 | } | |
4537 | ||
4538 | /* Hack! Don't let anybody do execbuf while we don't control the chip. | |
4539 | * We need to replace this with a semaphore, or something. | |
4540 | * And not confound mm.suspended! | |
4541 | */ | |
4542 | dev_priv->mm.suspended = 1; | |
bc0c7f14 | 4543 | del_timer_sync(&dev_priv->hangcheck_timer); |
29105ccc CW |
4544 | |
4545 | i915_kernel_lost_context(dev); | |
6dbe2772 | 4546 | i915_gem_cleanup_ringbuffer(dev); |
29105ccc | 4547 | |
6dbe2772 KP |
4548 | mutex_unlock(&dev->struct_mutex); |
4549 | ||
29105ccc CW |
4550 | /* Cancel the retire work handler, which should be idle now. */ |
4551 | cancel_delayed_work_sync(&dev_priv->mm.retire_work); | |
4552 | ||
673a394b EA |
4553 | return 0; |
4554 | } | |
4555 | ||
e552eb70 JB |
4556 | /* |
4557 | * 965+ support PIPE_CONTROL commands, which provide finer grained control | |
4558 | * over cache flushing. | |
4559 | */ | |
8187a2b7 | 4560 | static int |
e552eb70 JB |
4561 | i915_gem_init_pipe_control(struct drm_device *dev) |
4562 | { | |
4563 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4564 | struct drm_gem_object *obj; | |
4565 | struct drm_i915_gem_object *obj_priv; | |
4566 | int ret; | |
4567 | ||
34dc4d44 | 4568 | obj = i915_gem_alloc_object(dev, 4096); |
e552eb70 JB |
4569 | if (obj == NULL) { |
4570 | DRM_ERROR("Failed to allocate seqno page\n"); | |
4571 | ret = -ENOMEM; | |
4572 | goto err; | |
4573 | } | |
4574 | obj_priv = to_intel_bo(obj); | |
4575 | obj_priv->agp_type = AGP_USER_CACHED_MEMORY; | |
4576 | ||
4577 | ret = i915_gem_object_pin(obj, 4096); | |
4578 | if (ret) | |
4579 | goto err_unref; | |
4580 | ||
4581 | dev_priv->seqno_gfx_addr = obj_priv->gtt_offset; | |
4582 | dev_priv->seqno_page = kmap(obj_priv->pages[0]); | |
4583 | if (dev_priv->seqno_page == NULL) | |
4584 | goto err_unpin; | |
4585 | ||
4586 | dev_priv->seqno_obj = obj; | |
4587 | memset(dev_priv->seqno_page, 0, PAGE_SIZE); | |
4588 | ||
4589 | return 0; | |
4590 | ||
4591 | err_unpin: | |
4592 | i915_gem_object_unpin(obj); | |
4593 | err_unref: | |
4594 | drm_gem_object_unreference(obj); | |
4595 | err: | |
4596 | return ret; | |
4597 | } | |
4598 | ||
8187a2b7 ZN |
4599 | |
4600 | static void | |
e552eb70 JB |
4601 | i915_gem_cleanup_pipe_control(struct drm_device *dev) |
4602 | { | |
4603 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4604 | struct drm_gem_object *obj; | |
4605 | struct drm_i915_gem_object *obj_priv; | |
4606 | ||
4607 | obj = dev_priv->seqno_obj; | |
4608 | obj_priv = to_intel_bo(obj); | |
4609 | kunmap(obj_priv->pages[0]); | |
4610 | i915_gem_object_unpin(obj); | |
4611 | drm_gem_object_unreference(obj); | |
4612 | dev_priv->seqno_obj = NULL; | |
4613 | ||
4614 | dev_priv->seqno_page = NULL; | |
673a394b EA |
4615 | } |
4616 | ||
8187a2b7 ZN |
4617 | int |
4618 | i915_gem_init_ringbuffer(struct drm_device *dev) | |
4619 | { | |
4620 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4621 | int ret; | |
68f95ba9 | 4622 | |
8187a2b7 ZN |
4623 | if (HAS_PIPE_CONTROL(dev)) { |
4624 | ret = i915_gem_init_pipe_control(dev); | |
4625 | if (ret) | |
4626 | return ret; | |
4627 | } | |
68f95ba9 | 4628 | |
5c1143bb | 4629 | ret = intel_init_render_ring_buffer(dev); |
68f95ba9 CW |
4630 | if (ret) |
4631 | goto cleanup_pipe_control; | |
4632 | ||
4633 | if (HAS_BSD(dev)) { | |
5c1143bb | 4634 | ret = intel_init_bsd_ring_buffer(dev); |
68f95ba9 CW |
4635 | if (ret) |
4636 | goto cleanup_render_ring; | |
d1b851fc | 4637 | } |
68f95ba9 | 4638 | |
6f392d54 CW |
4639 | dev_priv->next_seqno = 1; |
4640 | ||
68f95ba9 CW |
4641 | return 0; |
4642 | ||
4643 | cleanup_render_ring: | |
4644 | intel_cleanup_ring_buffer(dev, &dev_priv->render_ring); | |
4645 | cleanup_pipe_control: | |
4646 | if (HAS_PIPE_CONTROL(dev)) | |
4647 | i915_gem_cleanup_pipe_control(dev); | |
8187a2b7 ZN |
4648 | return ret; |
4649 | } | |
4650 | ||
4651 | void | |
4652 | i915_gem_cleanup_ringbuffer(struct drm_device *dev) | |
4653 | { | |
4654 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4655 | ||
4656 | intel_cleanup_ring_buffer(dev, &dev_priv->render_ring); | |
d1b851fc ZN |
4657 | if (HAS_BSD(dev)) |
4658 | intel_cleanup_ring_buffer(dev, &dev_priv->bsd_ring); | |
8187a2b7 ZN |
4659 | if (HAS_PIPE_CONTROL(dev)) |
4660 | i915_gem_cleanup_pipe_control(dev); | |
4661 | } | |
4662 | ||
673a394b EA |
4663 | int |
4664 | i915_gem_entervt_ioctl(struct drm_device *dev, void *data, | |
4665 | struct drm_file *file_priv) | |
4666 | { | |
4667 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4668 | int ret; | |
4669 | ||
79e53945 JB |
4670 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
4671 | return 0; | |
4672 | ||
ba1234d1 | 4673 | if (atomic_read(&dev_priv->mm.wedged)) { |
673a394b | 4674 | DRM_ERROR("Reenabling wedged hardware, good luck\n"); |
ba1234d1 | 4675 | atomic_set(&dev_priv->mm.wedged, 0); |
673a394b EA |
4676 | } |
4677 | ||
673a394b | 4678 | mutex_lock(&dev->struct_mutex); |
9bb2d6f9 EA |
4679 | dev_priv->mm.suspended = 0; |
4680 | ||
4681 | ret = i915_gem_init_ringbuffer(dev); | |
d816f6ac WF |
4682 | if (ret != 0) { |
4683 | mutex_unlock(&dev->struct_mutex); | |
9bb2d6f9 | 4684 | return ret; |
d816f6ac | 4685 | } |
9bb2d6f9 | 4686 | |
852835f3 | 4687 | BUG_ON(!list_empty(&dev_priv->render_ring.active_list)); |
d1b851fc | 4688 | BUG_ON(HAS_BSD(dev) && !list_empty(&dev_priv->bsd_ring.active_list)); |
673a394b EA |
4689 | BUG_ON(!list_empty(&dev_priv->mm.flushing_list)); |
4690 | BUG_ON(!list_empty(&dev_priv->mm.inactive_list)); | |
852835f3 | 4691 | BUG_ON(!list_empty(&dev_priv->render_ring.request_list)); |
d1b851fc | 4692 | BUG_ON(HAS_BSD(dev) && !list_empty(&dev_priv->bsd_ring.request_list)); |
673a394b | 4693 | mutex_unlock(&dev->struct_mutex); |
dbb19d30 | 4694 | |
5f35308b CW |
4695 | ret = drm_irq_install(dev); |
4696 | if (ret) | |
4697 | goto cleanup_ringbuffer; | |
dbb19d30 | 4698 | |
673a394b | 4699 | return 0; |
5f35308b CW |
4700 | |
4701 | cleanup_ringbuffer: | |
4702 | mutex_lock(&dev->struct_mutex); | |
4703 | i915_gem_cleanup_ringbuffer(dev); | |
4704 | dev_priv->mm.suspended = 1; | |
4705 | mutex_unlock(&dev->struct_mutex); | |
4706 | ||
4707 | return ret; | |
673a394b EA |
4708 | } |
4709 | ||
4710 | int | |
4711 | i915_gem_leavevt_ioctl(struct drm_device *dev, void *data, | |
4712 | struct drm_file *file_priv) | |
4713 | { | |
79e53945 JB |
4714 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
4715 | return 0; | |
4716 | ||
dbb19d30 | 4717 | drm_irq_uninstall(dev); |
e6890f6f | 4718 | return i915_gem_idle(dev); |
673a394b EA |
4719 | } |
4720 | ||
4721 | void | |
4722 | i915_gem_lastclose(struct drm_device *dev) | |
4723 | { | |
4724 | int ret; | |
673a394b | 4725 | |
e806b495 EA |
4726 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
4727 | return; | |
4728 | ||
6dbe2772 KP |
4729 | ret = i915_gem_idle(dev); |
4730 | if (ret) | |
4731 | DRM_ERROR("failed to idle hardware: %d\n", ret); | |
673a394b EA |
4732 | } |
4733 | ||
4734 | void | |
4735 | i915_gem_load(struct drm_device *dev) | |
4736 | { | |
b5aa8a0f | 4737 | int i; |
673a394b EA |
4738 | drm_i915_private_t *dev_priv = dev->dev_private; |
4739 | ||
673a394b | 4740 | INIT_LIST_HEAD(&dev_priv->mm.flushing_list); |
99fcb766 | 4741 | INIT_LIST_HEAD(&dev_priv->mm.gpu_write_list); |
673a394b | 4742 | INIT_LIST_HEAD(&dev_priv->mm.inactive_list); |
f13d3f73 | 4743 | INIT_LIST_HEAD(&dev_priv->mm.pinned_list); |
a09ba7fa | 4744 | INIT_LIST_HEAD(&dev_priv->mm.fence_list); |
be72615b | 4745 | INIT_LIST_HEAD(&dev_priv->mm.deferred_free_list); |
852835f3 ZN |
4746 | INIT_LIST_HEAD(&dev_priv->render_ring.active_list); |
4747 | INIT_LIST_HEAD(&dev_priv->render_ring.request_list); | |
d1b851fc ZN |
4748 | if (HAS_BSD(dev)) { |
4749 | INIT_LIST_HEAD(&dev_priv->bsd_ring.active_list); | |
4750 | INIT_LIST_HEAD(&dev_priv->bsd_ring.request_list); | |
4751 | } | |
007cc8ac DV |
4752 | for (i = 0; i < 16; i++) |
4753 | INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list); | |
673a394b EA |
4754 | INIT_DELAYED_WORK(&dev_priv->mm.retire_work, |
4755 | i915_gem_retire_work_handler); | |
30dbf0c0 | 4756 | init_completion(&dev_priv->error_completion); |
31169714 CW |
4757 | spin_lock(&shrink_list_lock); |
4758 | list_add(&dev_priv->mm.shrink_list, &shrink_list); | |
4759 | spin_unlock(&shrink_list_lock); | |
4760 | ||
94400120 DA |
4761 | /* On GEN3 we really need to make sure the ARB C3 LP bit is set */ |
4762 | if (IS_GEN3(dev)) { | |
4763 | u32 tmp = I915_READ(MI_ARB_STATE); | |
4764 | if (!(tmp & MI_ARB_C3_LP_WRITE_ENABLE)) { | |
4765 | /* arb state is a masked write, so set bit + bit in mask */ | |
4766 | tmp = MI_ARB_C3_LP_WRITE_ENABLE | (MI_ARB_C3_LP_WRITE_ENABLE << MI_ARB_MASK_SHIFT); | |
4767 | I915_WRITE(MI_ARB_STATE, tmp); | |
4768 | } | |
4769 | } | |
4770 | ||
de151cf6 | 4771 | /* Old X drivers will take 0-2 for front, back, depth buffers */ |
b397c836 EA |
4772 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) |
4773 | dev_priv->fence_reg_start = 3; | |
de151cf6 | 4774 | |
a6c45cf0 | 4775 | if (INTEL_INFO(dev)->gen >= 4 || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) |
de151cf6 JB |
4776 | dev_priv->num_fence_regs = 16; |
4777 | else | |
4778 | dev_priv->num_fence_regs = 8; | |
4779 | ||
b5aa8a0f | 4780 | /* Initialize fence registers to zero */ |
a6c45cf0 CW |
4781 | switch (INTEL_INFO(dev)->gen) { |
4782 | case 6: | |
4783 | for (i = 0; i < 16; i++) | |
4784 | I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + (i * 8), 0); | |
4785 | break; | |
4786 | case 5: | |
4787 | case 4: | |
b5aa8a0f GH |
4788 | for (i = 0; i < 16; i++) |
4789 | I915_WRITE64(FENCE_REG_965_0 + (i * 8), 0); | |
a6c45cf0 CW |
4790 | break; |
4791 | case 3: | |
b5aa8a0f GH |
4792 | if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) |
4793 | for (i = 0; i < 8; i++) | |
4794 | I915_WRITE(FENCE_REG_945_8 + (i * 4), 0); | |
a6c45cf0 CW |
4795 | case 2: |
4796 | for (i = 0; i < 8; i++) | |
4797 | I915_WRITE(FENCE_REG_830_0 + (i * 4), 0); | |
4798 | break; | |
b5aa8a0f | 4799 | } |
673a394b | 4800 | i915_gem_detect_bit_6_swizzle(dev); |
6b95a207 | 4801 | init_waitqueue_head(&dev_priv->pending_flip_queue); |
673a394b | 4802 | } |
71acb5eb DA |
4803 | |
4804 | /* | |
4805 | * Create a physically contiguous memory object for this object | |
4806 | * e.g. for cursor + overlay regs | |
4807 | */ | |
995b6762 CW |
4808 | static int i915_gem_init_phys_object(struct drm_device *dev, |
4809 | int id, int size, int align) | |
71acb5eb DA |
4810 | { |
4811 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4812 | struct drm_i915_gem_phys_object *phys_obj; | |
4813 | int ret; | |
4814 | ||
4815 | if (dev_priv->mm.phys_objs[id - 1] || !size) | |
4816 | return 0; | |
4817 | ||
9a298b2a | 4818 | phys_obj = kzalloc(sizeof(struct drm_i915_gem_phys_object), GFP_KERNEL); |
71acb5eb DA |
4819 | if (!phys_obj) |
4820 | return -ENOMEM; | |
4821 | ||
4822 | phys_obj->id = id; | |
4823 | ||
6eeefaf3 | 4824 | phys_obj->handle = drm_pci_alloc(dev, size, align); |
71acb5eb DA |
4825 | if (!phys_obj->handle) { |
4826 | ret = -ENOMEM; | |
4827 | goto kfree_obj; | |
4828 | } | |
4829 | #ifdef CONFIG_X86 | |
4830 | set_memory_wc((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE); | |
4831 | #endif | |
4832 | ||
4833 | dev_priv->mm.phys_objs[id - 1] = phys_obj; | |
4834 | ||
4835 | return 0; | |
4836 | kfree_obj: | |
9a298b2a | 4837 | kfree(phys_obj); |
71acb5eb DA |
4838 | return ret; |
4839 | } | |
4840 | ||
995b6762 | 4841 | static void i915_gem_free_phys_object(struct drm_device *dev, int id) |
71acb5eb DA |
4842 | { |
4843 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4844 | struct drm_i915_gem_phys_object *phys_obj; | |
4845 | ||
4846 | if (!dev_priv->mm.phys_objs[id - 1]) | |
4847 | return; | |
4848 | ||
4849 | phys_obj = dev_priv->mm.phys_objs[id - 1]; | |
4850 | if (phys_obj->cur_obj) { | |
4851 | i915_gem_detach_phys_object(dev, phys_obj->cur_obj); | |
4852 | } | |
4853 | ||
4854 | #ifdef CONFIG_X86 | |
4855 | set_memory_wb((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE); | |
4856 | #endif | |
4857 | drm_pci_free(dev, phys_obj->handle); | |
4858 | kfree(phys_obj); | |
4859 | dev_priv->mm.phys_objs[id - 1] = NULL; | |
4860 | } | |
4861 | ||
4862 | void i915_gem_free_all_phys_object(struct drm_device *dev) | |
4863 | { | |
4864 | int i; | |
4865 | ||
260883c8 | 4866 | for (i = I915_GEM_PHYS_CURSOR_0; i <= I915_MAX_PHYS_OBJECT; i++) |
71acb5eb DA |
4867 | i915_gem_free_phys_object(dev, i); |
4868 | } | |
4869 | ||
4870 | void i915_gem_detach_phys_object(struct drm_device *dev, | |
4871 | struct drm_gem_object *obj) | |
4872 | { | |
4873 | struct drm_i915_gem_object *obj_priv; | |
4874 | int i; | |
4875 | int ret; | |
4876 | int page_count; | |
4877 | ||
23010e43 | 4878 | obj_priv = to_intel_bo(obj); |
71acb5eb DA |
4879 | if (!obj_priv->phys_obj) |
4880 | return; | |
4881 | ||
4bdadb97 | 4882 | ret = i915_gem_object_get_pages(obj, 0); |
71acb5eb DA |
4883 | if (ret) |
4884 | goto out; | |
4885 | ||
4886 | page_count = obj->size / PAGE_SIZE; | |
4887 | ||
4888 | for (i = 0; i < page_count; i++) { | |
856fa198 | 4889 | char *dst = kmap_atomic(obj_priv->pages[i], KM_USER0); |
71acb5eb DA |
4890 | char *src = obj_priv->phys_obj->handle->vaddr + (i * PAGE_SIZE); |
4891 | ||
4892 | memcpy(dst, src, PAGE_SIZE); | |
4893 | kunmap_atomic(dst, KM_USER0); | |
4894 | } | |
856fa198 | 4895 | drm_clflush_pages(obj_priv->pages, page_count); |
71acb5eb | 4896 | drm_agp_chipset_flush(dev); |
d78b47b9 CW |
4897 | |
4898 | i915_gem_object_put_pages(obj); | |
71acb5eb DA |
4899 | out: |
4900 | obj_priv->phys_obj->cur_obj = NULL; | |
4901 | obj_priv->phys_obj = NULL; | |
4902 | } | |
4903 | ||
4904 | int | |
4905 | i915_gem_attach_phys_object(struct drm_device *dev, | |
6eeefaf3 CW |
4906 | struct drm_gem_object *obj, |
4907 | int id, | |
4908 | int align) | |
71acb5eb DA |
4909 | { |
4910 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4911 | struct drm_i915_gem_object *obj_priv; | |
4912 | int ret = 0; | |
4913 | int page_count; | |
4914 | int i; | |
4915 | ||
4916 | if (id > I915_MAX_PHYS_OBJECT) | |
4917 | return -EINVAL; | |
4918 | ||
23010e43 | 4919 | obj_priv = to_intel_bo(obj); |
71acb5eb DA |
4920 | |
4921 | if (obj_priv->phys_obj) { | |
4922 | if (obj_priv->phys_obj->id == id) | |
4923 | return 0; | |
4924 | i915_gem_detach_phys_object(dev, obj); | |
4925 | } | |
4926 | ||
71acb5eb DA |
4927 | /* create a new object */ |
4928 | if (!dev_priv->mm.phys_objs[id - 1]) { | |
4929 | ret = i915_gem_init_phys_object(dev, id, | |
6eeefaf3 | 4930 | obj->size, align); |
71acb5eb | 4931 | if (ret) { |
aeb565df | 4932 | DRM_ERROR("failed to init phys object %d size: %zu\n", id, obj->size); |
71acb5eb DA |
4933 | goto out; |
4934 | } | |
4935 | } | |
4936 | ||
4937 | /* bind to the object */ | |
4938 | obj_priv->phys_obj = dev_priv->mm.phys_objs[id - 1]; | |
4939 | obj_priv->phys_obj->cur_obj = obj; | |
4940 | ||
4bdadb97 | 4941 | ret = i915_gem_object_get_pages(obj, 0); |
71acb5eb DA |
4942 | if (ret) { |
4943 | DRM_ERROR("failed to get page list\n"); | |
4944 | goto out; | |
4945 | } | |
4946 | ||
4947 | page_count = obj->size / PAGE_SIZE; | |
4948 | ||
4949 | for (i = 0; i < page_count; i++) { | |
856fa198 | 4950 | char *src = kmap_atomic(obj_priv->pages[i], KM_USER0); |
71acb5eb DA |
4951 | char *dst = obj_priv->phys_obj->handle->vaddr + (i * PAGE_SIZE); |
4952 | ||
4953 | memcpy(dst, src, PAGE_SIZE); | |
4954 | kunmap_atomic(src, KM_USER0); | |
4955 | } | |
4956 | ||
d78b47b9 CW |
4957 | i915_gem_object_put_pages(obj); |
4958 | ||
71acb5eb DA |
4959 | return 0; |
4960 | out: | |
4961 | return ret; | |
4962 | } | |
4963 | ||
4964 | static int | |
4965 | i915_gem_phys_pwrite(struct drm_device *dev, struct drm_gem_object *obj, | |
4966 | struct drm_i915_gem_pwrite *args, | |
4967 | struct drm_file *file_priv) | |
4968 | { | |
23010e43 | 4969 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
71acb5eb DA |
4970 | void *obj_addr; |
4971 | int ret; | |
4972 | char __user *user_data; | |
4973 | ||
4974 | user_data = (char __user *) (uintptr_t) args->data_ptr; | |
4975 | obj_addr = obj_priv->phys_obj->handle->vaddr + args->offset; | |
4976 | ||
44d98a61 | 4977 | DRM_DEBUG_DRIVER("obj_addr %p, %lld\n", obj_addr, args->size); |
71acb5eb DA |
4978 | ret = copy_from_user(obj_addr, user_data, args->size); |
4979 | if (ret) | |
4980 | return -EFAULT; | |
4981 | ||
4982 | drm_agp_chipset_flush(dev); | |
4983 | return 0; | |
4984 | } | |
b962442e | 4985 | |
f787a5f5 | 4986 | void i915_gem_release(struct drm_device *dev, struct drm_file *file) |
b962442e | 4987 | { |
f787a5f5 | 4988 | struct drm_i915_file_private *file_priv = file->driver_priv; |
b962442e EA |
4989 | |
4990 | /* Clean up our request list when the client is going away, so that | |
4991 | * later retire_requests won't dereference our soon-to-be-gone | |
4992 | * file_priv. | |
4993 | */ | |
1c25595f | 4994 | spin_lock(&file_priv->mm.lock); |
f787a5f5 CW |
4995 | while (!list_empty(&file_priv->mm.request_list)) { |
4996 | struct drm_i915_gem_request *request; | |
4997 | ||
4998 | request = list_first_entry(&file_priv->mm.request_list, | |
4999 | struct drm_i915_gem_request, | |
5000 | client_list); | |
5001 | list_del(&request->client_list); | |
5002 | request->file_priv = NULL; | |
5003 | } | |
1c25595f | 5004 | spin_unlock(&file_priv->mm.lock); |
b962442e | 5005 | } |
31169714 | 5006 | |
1637ef41 CW |
5007 | static int |
5008 | i915_gpu_is_active(struct drm_device *dev) | |
5009 | { | |
5010 | drm_i915_private_t *dev_priv = dev->dev_private; | |
5011 | int lists_empty; | |
5012 | ||
1637ef41 | 5013 | lists_empty = list_empty(&dev_priv->mm.flushing_list) && |
852835f3 | 5014 | list_empty(&dev_priv->render_ring.active_list); |
d1b851fc ZN |
5015 | if (HAS_BSD(dev)) |
5016 | lists_empty &= list_empty(&dev_priv->bsd_ring.active_list); | |
1637ef41 CW |
5017 | |
5018 | return !lists_empty; | |
5019 | } | |
5020 | ||
31169714 | 5021 | static int |
7f8275d0 | 5022 | i915_gem_shrink(struct shrinker *shrink, int nr_to_scan, gfp_t gfp_mask) |
31169714 CW |
5023 | { |
5024 | drm_i915_private_t *dev_priv, *next_dev; | |
5025 | struct drm_i915_gem_object *obj_priv, *next_obj; | |
5026 | int cnt = 0; | |
5027 | int would_deadlock = 1; | |
5028 | ||
5029 | /* "fast-path" to count number of available objects */ | |
5030 | if (nr_to_scan == 0) { | |
5031 | spin_lock(&shrink_list_lock); | |
5032 | list_for_each_entry(dev_priv, &shrink_list, mm.shrink_list) { | |
5033 | struct drm_device *dev = dev_priv->dev; | |
5034 | ||
5035 | if (mutex_trylock(&dev->struct_mutex)) { | |
5036 | list_for_each_entry(obj_priv, | |
5037 | &dev_priv->mm.inactive_list, | |
5038 | list) | |
5039 | cnt++; | |
5040 | mutex_unlock(&dev->struct_mutex); | |
5041 | } | |
5042 | } | |
5043 | spin_unlock(&shrink_list_lock); | |
5044 | ||
5045 | return (cnt / 100) * sysctl_vfs_cache_pressure; | |
5046 | } | |
5047 | ||
5048 | spin_lock(&shrink_list_lock); | |
5049 | ||
1637ef41 | 5050 | rescan: |
31169714 CW |
5051 | /* first scan for clean buffers */ |
5052 | list_for_each_entry_safe(dev_priv, next_dev, | |
5053 | &shrink_list, mm.shrink_list) { | |
5054 | struct drm_device *dev = dev_priv->dev; | |
5055 | ||
5056 | if (! mutex_trylock(&dev->struct_mutex)) | |
5057 | continue; | |
5058 | ||
5059 | spin_unlock(&shrink_list_lock); | |
b09a1fec | 5060 | i915_gem_retire_requests(dev); |
31169714 CW |
5061 | |
5062 | list_for_each_entry_safe(obj_priv, next_obj, | |
5063 | &dev_priv->mm.inactive_list, | |
5064 | list) { | |
5065 | if (i915_gem_object_is_purgeable(obj_priv)) { | |
a8089e84 | 5066 | i915_gem_object_unbind(&obj_priv->base); |
31169714 CW |
5067 | if (--nr_to_scan <= 0) |
5068 | break; | |
5069 | } | |
5070 | } | |
5071 | ||
5072 | spin_lock(&shrink_list_lock); | |
5073 | mutex_unlock(&dev->struct_mutex); | |
5074 | ||
963b4836 CW |
5075 | would_deadlock = 0; |
5076 | ||
31169714 CW |
5077 | if (nr_to_scan <= 0) |
5078 | break; | |
5079 | } | |
5080 | ||
5081 | /* second pass, evict/count anything still on the inactive list */ | |
5082 | list_for_each_entry_safe(dev_priv, next_dev, | |
5083 | &shrink_list, mm.shrink_list) { | |
5084 | struct drm_device *dev = dev_priv->dev; | |
5085 | ||
5086 | if (! mutex_trylock(&dev->struct_mutex)) | |
5087 | continue; | |
5088 | ||
5089 | spin_unlock(&shrink_list_lock); | |
5090 | ||
5091 | list_for_each_entry_safe(obj_priv, next_obj, | |
5092 | &dev_priv->mm.inactive_list, | |
5093 | list) { | |
5094 | if (nr_to_scan > 0) { | |
a8089e84 | 5095 | i915_gem_object_unbind(&obj_priv->base); |
31169714 CW |
5096 | nr_to_scan--; |
5097 | } else | |
5098 | cnt++; | |
5099 | } | |
5100 | ||
5101 | spin_lock(&shrink_list_lock); | |
5102 | mutex_unlock(&dev->struct_mutex); | |
5103 | ||
5104 | would_deadlock = 0; | |
5105 | } | |
5106 | ||
1637ef41 CW |
5107 | if (nr_to_scan) { |
5108 | int active = 0; | |
5109 | ||
5110 | /* | |
5111 | * We are desperate for pages, so as a last resort, wait | |
5112 | * for the GPU to finish and discard whatever we can. | |
5113 | * This has a dramatic impact to reduce the number of | |
5114 | * OOM-killer events whilst running the GPU aggressively. | |
5115 | */ | |
5116 | list_for_each_entry(dev_priv, &shrink_list, mm.shrink_list) { | |
5117 | struct drm_device *dev = dev_priv->dev; | |
5118 | ||
5119 | if (!mutex_trylock(&dev->struct_mutex)) | |
5120 | continue; | |
5121 | ||
5122 | spin_unlock(&shrink_list_lock); | |
5123 | ||
5124 | if (i915_gpu_is_active(dev)) { | |
5125 | i915_gpu_idle(dev); | |
5126 | active++; | |
5127 | } | |
5128 | ||
5129 | spin_lock(&shrink_list_lock); | |
5130 | mutex_unlock(&dev->struct_mutex); | |
5131 | } | |
5132 | ||
5133 | if (active) | |
5134 | goto rescan; | |
5135 | } | |
5136 | ||
31169714 CW |
5137 | spin_unlock(&shrink_list_lock); |
5138 | ||
5139 | if (would_deadlock) | |
5140 | return -1; | |
5141 | else if (cnt > 0) | |
5142 | return (cnt / 100) * sysctl_vfs_cache_pressure; | |
5143 | else | |
5144 | return 0; | |
5145 | } | |
5146 | ||
5147 | static struct shrinker shrinker = { | |
5148 | .shrink = i915_gem_shrink, | |
5149 | .seeks = DEFAULT_SEEKS, | |
5150 | }; | |
5151 | ||
5152 | __init void | |
5153 | i915_gem_shrinker_init(void) | |
5154 | { | |
5155 | register_shrinker(&shrinker); | |
5156 | } | |
5157 | ||
5158 | __exit void | |
5159 | i915_gem_shrinker_exit(void) | |
5160 | { | |
5161 | unregister_shrinker(&shrinker); | |
5162 | } |