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Commit | Line | Data |
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673a394b EA |
1 | /* |
2 | * Copyright © 2008 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | * | |
26 | */ | |
27 | ||
28 | #include "drmP.h" | |
29 | #include "drm.h" | |
30 | #include "i915_drm.h" | |
31 | #include "i915_drv.h" | |
1c5d22f7 | 32 | #include "i915_trace.h" |
652c393a | 33 | #include "intel_drv.h" |
5a0e3ad6 | 34 | #include <linux/slab.h> |
673a394b | 35 | #include <linux/swap.h> |
79e53945 | 36 | #include <linux/pci.h> |
f8f235e5 | 37 | #include <linux/intel-gtt.h> |
673a394b | 38 | |
0108a3ed | 39 | static uint32_t i915_gem_get_gtt_alignment(struct drm_gem_object *obj); |
ba3d8d74 DV |
40 | |
41 | static int i915_gem_object_flush_gpu_write_domain(struct drm_gem_object *obj, | |
42 | bool pipelined); | |
e47c68e9 EA |
43 | static void i915_gem_object_flush_gtt_write_domain(struct drm_gem_object *obj); |
44 | static void i915_gem_object_flush_cpu_write_domain(struct drm_gem_object *obj); | |
e47c68e9 EA |
45 | static int i915_gem_object_set_to_cpu_domain(struct drm_gem_object *obj, |
46 | int write); | |
47 | static int i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object *obj, | |
48 | uint64_t offset, | |
49 | uint64_t size); | |
50 | static void i915_gem_object_set_to_full_cpu_read_domain(struct drm_gem_object *obj); | |
2cf34d7b CW |
51 | static int i915_gem_object_wait_rendering(struct drm_gem_object *obj, |
52 | bool interruptible); | |
de151cf6 JB |
53 | static int i915_gem_object_bind_to_gtt(struct drm_gem_object *obj, |
54 | unsigned alignment); | |
de151cf6 | 55 | static void i915_gem_clear_fence_reg(struct drm_gem_object *obj); |
71acb5eb DA |
56 | static int i915_gem_phys_pwrite(struct drm_device *dev, struct drm_gem_object *obj, |
57 | struct drm_i915_gem_pwrite *args, | |
58 | struct drm_file *file_priv); | |
be72615b | 59 | static void i915_gem_free_object_tail(struct drm_gem_object *obj); |
673a394b | 60 | |
5cdf5881 CW |
61 | static int |
62 | i915_gem_object_get_pages(struct drm_gem_object *obj, | |
63 | gfp_t gfpmask); | |
64 | ||
65 | static void | |
66 | i915_gem_object_put_pages(struct drm_gem_object *obj); | |
67 | ||
31169714 CW |
68 | static LIST_HEAD(shrink_list); |
69 | static DEFINE_SPINLOCK(shrink_list_lock); | |
70 | ||
30dbf0c0 CW |
71 | int |
72 | i915_gem_check_is_wedged(struct drm_device *dev) | |
73 | { | |
74 | struct drm_i915_private *dev_priv = dev->dev_private; | |
75 | struct completion *x = &dev_priv->error_completion; | |
76 | unsigned long flags; | |
77 | int ret; | |
78 | ||
79 | if (!atomic_read(&dev_priv->mm.wedged)) | |
80 | return 0; | |
81 | ||
82 | ret = wait_for_completion_interruptible(x); | |
83 | if (ret) | |
84 | return ret; | |
85 | ||
86 | /* Success, we reset the GPU! */ | |
87 | if (!atomic_read(&dev_priv->mm.wedged)) | |
88 | return 0; | |
89 | ||
90 | /* GPU is hung, bump the completion count to account for | |
91 | * the token we just consumed so that we never hit zero and | |
92 | * end up waiting upon a subsequent completion event that | |
93 | * will never happen. | |
94 | */ | |
95 | spin_lock_irqsave(&x->wait.lock, flags); | |
96 | x->done++; | |
97 | spin_unlock_irqrestore(&x->wait.lock, flags); | |
98 | return -EIO; | |
99 | } | |
100 | ||
76c1dec1 CW |
101 | static int i915_mutex_lock_interruptible(struct drm_device *dev) |
102 | { | |
103 | struct drm_i915_private *dev_priv = dev->dev_private; | |
104 | int ret; | |
105 | ||
106 | ret = i915_gem_check_is_wedged(dev); | |
107 | if (ret) | |
108 | return ret; | |
109 | ||
110 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
111 | if (ret) | |
112 | return ret; | |
113 | ||
114 | if (atomic_read(&dev_priv->mm.wedged)) { | |
115 | mutex_unlock(&dev->struct_mutex); | |
116 | return -EAGAIN; | |
117 | } | |
118 | ||
23bc5982 | 119 | WARN_ON(i915_verify_lists(dev)); |
76c1dec1 CW |
120 | return 0; |
121 | } | |
30dbf0c0 | 122 | |
7d1c4804 CW |
123 | static inline bool |
124 | i915_gem_object_is_inactive(struct drm_i915_gem_object *obj_priv) | |
125 | { | |
126 | return obj_priv->gtt_space && | |
127 | !obj_priv->active && | |
128 | obj_priv->pin_count == 0; | |
129 | } | |
130 | ||
79e53945 JB |
131 | int i915_gem_do_init(struct drm_device *dev, unsigned long start, |
132 | unsigned long end) | |
673a394b EA |
133 | { |
134 | drm_i915_private_t *dev_priv = dev->dev_private; | |
673a394b | 135 | |
79e53945 JB |
136 | if (start >= end || |
137 | (start & (PAGE_SIZE - 1)) != 0 || | |
138 | (end & (PAGE_SIZE - 1)) != 0) { | |
673a394b EA |
139 | return -EINVAL; |
140 | } | |
141 | ||
79e53945 JB |
142 | drm_mm_init(&dev_priv->mm.gtt_space, start, |
143 | end - start); | |
673a394b | 144 | |
79e53945 JB |
145 | dev->gtt_total = (uint32_t) (end - start); |
146 | ||
147 | return 0; | |
148 | } | |
673a394b | 149 | |
79e53945 JB |
150 | int |
151 | i915_gem_init_ioctl(struct drm_device *dev, void *data, | |
152 | struct drm_file *file_priv) | |
153 | { | |
154 | struct drm_i915_gem_init *args = data; | |
155 | int ret; | |
156 | ||
157 | mutex_lock(&dev->struct_mutex); | |
158 | ret = i915_gem_do_init(dev, args->gtt_start, args->gtt_end); | |
673a394b EA |
159 | mutex_unlock(&dev->struct_mutex); |
160 | ||
79e53945 | 161 | return ret; |
673a394b EA |
162 | } |
163 | ||
5a125c3c EA |
164 | int |
165 | i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data, | |
166 | struct drm_file *file_priv) | |
167 | { | |
5a125c3c | 168 | struct drm_i915_gem_get_aperture *args = data; |
5a125c3c EA |
169 | |
170 | if (!(dev->driver->driver_features & DRIVER_GEM)) | |
171 | return -ENODEV; | |
172 | ||
173 | args->aper_size = dev->gtt_total; | |
2678d9d6 KP |
174 | args->aper_available_size = (args->aper_size - |
175 | atomic_read(&dev->pin_memory)); | |
5a125c3c EA |
176 | |
177 | return 0; | |
178 | } | |
179 | ||
673a394b EA |
180 | |
181 | /** | |
182 | * Creates a new mm object and returns a handle to it. | |
183 | */ | |
184 | int | |
185 | i915_gem_create_ioctl(struct drm_device *dev, void *data, | |
186 | struct drm_file *file_priv) | |
187 | { | |
188 | struct drm_i915_gem_create *args = data; | |
189 | struct drm_gem_object *obj; | |
a1a2d1d3 PP |
190 | int ret; |
191 | u32 handle; | |
673a394b EA |
192 | |
193 | args->size = roundup(args->size, PAGE_SIZE); | |
194 | ||
195 | /* Allocate the new object */ | |
ac52bc56 | 196 | obj = i915_gem_alloc_object(dev, args->size); |
673a394b EA |
197 | if (obj == NULL) |
198 | return -ENOMEM; | |
199 | ||
200 | ret = drm_gem_handle_create(file_priv, obj, &handle); | |
1dfd9754 CW |
201 | if (ret) { |
202 | drm_gem_object_unreference_unlocked(obj); | |
673a394b | 203 | return ret; |
1dfd9754 | 204 | } |
673a394b | 205 | |
1dfd9754 CW |
206 | /* Sink the floating reference from kref_init(handlecount) */ |
207 | drm_gem_object_handle_unreference_unlocked(obj); | |
673a394b | 208 | |
1dfd9754 | 209 | args->handle = handle; |
673a394b EA |
210 | return 0; |
211 | } | |
212 | ||
eb01459f EA |
213 | static inline int |
214 | fast_shmem_read(struct page **pages, | |
215 | loff_t page_base, int page_offset, | |
216 | char __user *data, | |
217 | int length) | |
218 | { | |
219 | char __iomem *vaddr; | |
2bc43b5c | 220 | int unwritten; |
eb01459f EA |
221 | |
222 | vaddr = kmap_atomic(pages[page_base >> PAGE_SHIFT], KM_USER0); | |
223 | if (vaddr == NULL) | |
224 | return -ENOMEM; | |
2bc43b5c | 225 | unwritten = __copy_to_user_inatomic(data, vaddr + page_offset, length); |
eb01459f EA |
226 | kunmap_atomic(vaddr, KM_USER0); |
227 | ||
2bc43b5c FM |
228 | if (unwritten) |
229 | return -EFAULT; | |
230 | ||
231 | return 0; | |
eb01459f EA |
232 | } |
233 | ||
280b713b EA |
234 | static int i915_gem_object_needs_bit17_swizzle(struct drm_gem_object *obj) |
235 | { | |
236 | drm_i915_private_t *dev_priv = obj->dev->dev_private; | |
23010e43 | 237 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
280b713b EA |
238 | |
239 | return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 && | |
240 | obj_priv->tiling_mode != I915_TILING_NONE; | |
241 | } | |
242 | ||
99a03df5 | 243 | static inline void |
40123c1f EA |
244 | slow_shmem_copy(struct page *dst_page, |
245 | int dst_offset, | |
246 | struct page *src_page, | |
247 | int src_offset, | |
248 | int length) | |
249 | { | |
250 | char *dst_vaddr, *src_vaddr; | |
251 | ||
99a03df5 CW |
252 | dst_vaddr = kmap(dst_page); |
253 | src_vaddr = kmap(src_page); | |
40123c1f EA |
254 | |
255 | memcpy(dst_vaddr + dst_offset, src_vaddr + src_offset, length); | |
256 | ||
99a03df5 CW |
257 | kunmap(src_page); |
258 | kunmap(dst_page); | |
40123c1f EA |
259 | } |
260 | ||
99a03df5 | 261 | static inline void |
280b713b EA |
262 | slow_shmem_bit17_copy(struct page *gpu_page, |
263 | int gpu_offset, | |
264 | struct page *cpu_page, | |
265 | int cpu_offset, | |
266 | int length, | |
267 | int is_read) | |
268 | { | |
269 | char *gpu_vaddr, *cpu_vaddr; | |
270 | ||
271 | /* Use the unswizzled path if this page isn't affected. */ | |
272 | if ((page_to_phys(gpu_page) & (1 << 17)) == 0) { | |
273 | if (is_read) | |
274 | return slow_shmem_copy(cpu_page, cpu_offset, | |
275 | gpu_page, gpu_offset, length); | |
276 | else | |
277 | return slow_shmem_copy(gpu_page, gpu_offset, | |
278 | cpu_page, cpu_offset, length); | |
279 | } | |
280 | ||
99a03df5 CW |
281 | gpu_vaddr = kmap(gpu_page); |
282 | cpu_vaddr = kmap(cpu_page); | |
280b713b EA |
283 | |
284 | /* Copy the data, XORing A6 with A17 (1). The user already knows he's | |
285 | * XORing with the other bits (A9 for Y, A9 and A10 for X) | |
286 | */ | |
287 | while (length > 0) { | |
288 | int cacheline_end = ALIGN(gpu_offset + 1, 64); | |
289 | int this_length = min(cacheline_end - gpu_offset, length); | |
290 | int swizzled_gpu_offset = gpu_offset ^ 64; | |
291 | ||
292 | if (is_read) { | |
293 | memcpy(cpu_vaddr + cpu_offset, | |
294 | gpu_vaddr + swizzled_gpu_offset, | |
295 | this_length); | |
296 | } else { | |
297 | memcpy(gpu_vaddr + swizzled_gpu_offset, | |
298 | cpu_vaddr + cpu_offset, | |
299 | this_length); | |
300 | } | |
301 | cpu_offset += this_length; | |
302 | gpu_offset += this_length; | |
303 | length -= this_length; | |
304 | } | |
305 | ||
99a03df5 CW |
306 | kunmap(cpu_page); |
307 | kunmap(gpu_page); | |
280b713b EA |
308 | } |
309 | ||
eb01459f EA |
310 | /** |
311 | * This is the fast shmem pread path, which attempts to copy_from_user directly | |
312 | * from the backing pages of the object to the user's address space. On a | |
313 | * fault, it fails so we can fall back to i915_gem_shmem_pwrite_slow(). | |
314 | */ | |
315 | static int | |
316 | i915_gem_shmem_pread_fast(struct drm_device *dev, struct drm_gem_object *obj, | |
317 | struct drm_i915_gem_pread *args, | |
318 | struct drm_file *file_priv) | |
319 | { | |
23010e43 | 320 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
eb01459f EA |
321 | ssize_t remain; |
322 | loff_t offset, page_base; | |
323 | char __user *user_data; | |
324 | int page_offset, page_length; | |
325 | int ret; | |
326 | ||
327 | user_data = (char __user *) (uintptr_t) args->data_ptr; | |
328 | remain = args->size; | |
329 | ||
76c1dec1 CW |
330 | ret = i915_mutex_lock_interruptible(dev); |
331 | if (ret) | |
332 | return ret; | |
eb01459f | 333 | |
4bdadb97 | 334 | ret = i915_gem_object_get_pages(obj, 0); |
eb01459f EA |
335 | if (ret != 0) |
336 | goto fail_unlock; | |
337 | ||
338 | ret = i915_gem_object_set_cpu_read_domain_range(obj, args->offset, | |
339 | args->size); | |
340 | if (ret != 0) | |
341 | goto fail_put_pages; | |
342 | ||
23010e43 | 343 | obj_priv = to_intel_bo(obj); |
eb01459f EA |
344 | offset = args->offset; |
345 | ||
346 | while (remain > 0) { | |
347 | /* Operation in this page | |
348 | * | |
349 | * page_base = page offset within aperture | |
350 | * page_offset = offset within page | |
351 | * page_length = bytes to copy for this page | |
352 | */ | |
353 | page_base = (offset & ~(PAGE_SIZE-1)); | |
354 | page_offset = offset & (PAGE_SIZE-1); | |
355 | page_length = remain; | |
356 | if ((page_offset + remain) > PAGE_SIZE) | |
357 | page_length = PAGE_SIZE - page_offset; | |
358 | ||
359 | ret = fast_shmem_read(obj_priv->pages, | |
360 | page_base, page_offset, | |
361 | user_data, page_length); | |
362 | if (ret) | |
363 | goto fail_put_pages; | |
364 | ||
365 | remain -= page_length; | |
366 | user_data += page_length; | |
367 | offset += page_length; | |
368 | } | |
369 | ||
370 | fail_put_pages: | |
371 | i915_gem_object_put_pages(obj); | |
372 | fail_unlock: | |
373 | mutex_unlock(&dev->struct_mutex); | |
374 | ||
375 | return ret; | |
376 | } | |
377 | ||
07f73f69 CW |
378 | static int |
379 | i915_gem_object_get_pages_or_evict(struct drm_gem_object *obj) | |
380 | { | |
381 | int ret; | |
382 | ||
4bdadb97 | 383 | ret = i915_gem_object_get_pages(obj, __GFP_NORETRY | __GFP_NOWARN); |
07f73f69 CW |
384 | |
385 | /* If we've insufficient memory to map in the pages, attempt | |
386 | * to make some space by throwing out some old buffers. | |
387 | */ | |
388 | if (ret == -ENOMEM) { | |
389 | struct drm_device *dev = obj->dev; | |
07f73f69 | 390 | |
0108a3ed DV |
391 | ret = i915_gem_evict_something(dev, obj->size, |
392 | i915_gem_get_gtt_alignment(obj)); | |
07f73f69 CW |
393 | if (ret) |
394 | return ret; | |
395 | ||
4bdadb97 | 396 | ret = i915_gem_object_get_pages(obj, 0); |
07f73f69 CW |
397 | } |
398 | ||
399 | return ret; | |
400 | } | |
401 | ||
eb01459f EA |
402 | /** |
403 | * This is the fallback shmem pread path, which allocates temporary storage | |
404 | * in kernel space to copy_to_user into outside of the struct_mutex, so we | |
405 | * can copy out of the object's backing pages while holding the struct mutex | |
406 | * and not take page faults. | |
407 | */ | |
408 | static int | |
409 | i915_gem_shmem_pread_slow(struct drm_device *dev, struct drm_gem_object *obj, | |
410 | struct drm_i915_gem_pread *args, | |
411 | struct drm_file *file_priv) | |
412 | { | |
23010e43 | 413 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
eb01459f EA |
414 | struct mm_struct *mm = current->mm; |
415 | struct page **user_pages; | |
416 | ssize_t remain; | |
417 | loff_t offset, pinned_pages, i; | |
418 | loff_t first_data_page, last_data_page, num_pages; | |
419 | int shmem_page_index, shmem_page_offset; | |
420 | int data_page_index, data_page_offset; | |
421 | int page_length; | |
422 | int ret; | |
423 | uint64_t data_ptr = args->data_ptr; | |
280b713b | 424 | int do_bit17_swizzling; |
eb01459f EA |
425 | |
426 | remain = args->size; | |
427 | ||
428 | /* Pin the user pages containing the data. We can't fault while | |
429 | * holding the struct mutex, yet we want to hold it while | |
430 | * dereferencing the user data. | |
431 | */ | |
432 | first_data_page = data_ptr / PAGE_SIZE; | |
433 | last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE; | |
434 | num_pages = last_data_page - first_data_page + 1; | |
435 | ||
8e7d2b2c | 436 | user_pages = drm_calloc_large(num_pages, sizeof(struct page *)); |
eb01459f EA |
437 | if (user_pages == NULL) |
438 | return -ENOMEM; | |
439 | ||
440 | down_read(&mm->mmap_sem); | |
441 | pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr, | |
e5e9ecde | 442 | num_pages, 1, 0, user_pages, NULL); |
eb01459f EA |
443 | up_read(&mm->mmap_sem); |
444 | if (pinned_pages < num_pages) { | |
445 | ret = -EFAULT; | |
446 | goto fail_put_user_pages; | |
447 | } | |
448 | ||
280b713b EA |
449 | do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj); |
450 | ||
76c1dec1 CW |
451 | ret = i915_mutex_lock_interruptible(dev); |
452 | if (ret) | |
453 | goto fail_put_user_pages; | |
eb01459f | 454 | |
07f73f69 CW |
455 | ret = i915_gem_object_get_pages_or_evict(obj); |
456 | if (ret) | |
eb01459f EA |
457 | goto fail_unlock; |
458 | ||
459 | ret = i915_gem_object_set_cpu_read_domain_range(obj, args->offset, | |
460 | args->size); | |
461 | if (ret != 0) | |
462 | goto fail_put_pages; | |
463 | ||
23010e43 | 464 | obj_priv = to_intel_bo(obj); |
eb01459f EA |
465 | offset = args->offset; |
466 | ||
467 | while (remain > 0) { | |
468 | /* Operation in this page | |
469 | * | |
470 | * shmem_page_index = page number within shmem file | |
471 | * shmem_page_offset = offset within page in shmem file | |
472 | * data_page_index = page number in get_user_pages return | |
473 | * data_page_offset = offset with data_page_index page. | |
474 | * page_length = bytes to copy for this page | |
475 | */ | |
476 | shmem_page_index = offset / PAGE_SIZE; | |
477 | shmem_page_offset = offset & ~PAGE_MASK; | |
478 | data_page_index = data_ptr / PAGE_SIZE - first_data_page; | |
479 | data_page_offset = data_ptr & ~PAGE_MASK; | |
480 | ||
481 | page_length = remain; | |
482 | if ((shmem_page_offset + page_length) > PAGE_SIZE) | |
483 | page_length = PAGE_SIZE - shmem_page_offset; | |
484 | if ((data_page_offset + page_length) > PAGE_SIZE) | |
485 | page_length = PAGE_SIZE - data_page_offset; | |
486 | ||
280b713b | 487 | if (do_bit17_swizzling) { |
99a03df5 | 488 | slow_shmem_bit17_copy(obj_priv->pages[shmem_page_index], |
280b713b | 489 | shmem_page_offset, |
99a03df5 CW |
490 | user_pages[data_page_index], |
491 | data_page_offset, | |
492 | page_length, | |
493 | 1); | |
494 | } else { | |
495 | slow_shmem_copy(user_pages[data_page_index], | |
496 | data_page_offset, | |
497 | obj_priv->pages[shmem_page_index], | |
498 | shmem_page_offset, | |
499 | page_length); | |
280b713b | 500 | } |
eb01459f EA |
501 | |
502 | remain -= page_length; | |
503 | data_ptr += page_length; | |
504 | offset += page_length; | |
505 | } | |
506 | ||
507 | fail_put_pages: | |
508 | i915_gem_object_put_pages(obj); | |
509 | fail_unlock: | |
510 | mutex_unlock(&dev->struct_mutex); | |
511 | fail_put_user_pages: | |
512 | for (i = 0; i < pinned_pages; i++) { | |
513 | SetPageDirty(user_pages[i]); | |
514 | page_cache_release(user_pages[i]); | |
515 | } | |
8e7d2b2c | 516 | drm_free_large(user_pages); |
eb01459f EA |
517 | |
518 | return ret; | |
519 | } | |
520 | ||
673a394b EA |
521 | /** |
522 | * Reads data from the object referenced by handle. | |
523 | * | |
524 | * On error, the contents of *data are undefined. | |
525 | */ | |
526 | int | |
527 | i915_gem_pread_ioctl(struct drm_device *dev, void *data, | |
528 | struct drm_file *file_priv) | |
529 | { | |
530 | struct drm_i915_gem_pread *args = data; | |
531 | struct drm_gem_object *obj; | |
532 | struct drm_i915_gem_object *obj_priv; | |
673a394b EA |
533 | int ret; |
534 | ||
535 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); | |
536 | if (obj == NULL) | |
bf79cb91 | 537 | return -ENOENT; |
23010e43 | 538 | obj_priv = to_intel_bo(obj); |
673a394b EA |
539 | |
540 | /* Bounds check source. | |
541 | * | |
542 | * XXX: This could use review for overflow issues... | |
543 | */ | |
544 | if (args->offset > obj->size || args->size > obj->size || | |
545 | args->offset + args->size > obj->size) { | |
bc9025bd | 546 | drm_gem_object_unreference_unlocked(obj); |
673a394b EA |
547 | return -EINVAL; |
548 | } | |
549 | ||
280b713b | 550 | if (i915_gem_object_needs_bit17_swizzle(obj)) { |
eb01459f | 551 | ret = i915_gem_shmem_pread_slow(dev, obj, args, file_priv); |
280b713b EA |
552 | } else { |
553 | ret = i915_gem_shmem_pread_fast(dev, obj, args, file_priv); | |
554 | if (ret != 0) | |
555 | ret = i915_gem_shmem_pread_slow(dev, obj, args, | |
556 | file_priv); | |
557 | } | |
673a394b | 558 | |
bc9025bd | 559 | drm_gem_object_unreference_unlocked(obj); |
673a394b | 560 | |
eb01459f | 561 | return ret; |
673a394b EA |
562 | } |
563 | ||
0839ccb8 KP |
564 | /* This is the fast write path which cannot handle |
565 | * page faults in the source data | |
9b7530cc | 566 | */ |
0839ccb8 KP |
567 | |
568 | static inline int | |
569 | fast_user_write(struct io_mapping *mapping, | |
570 | loff_t page_base, int page_offset, | |
571 | char __user *user_data, | |
572 | int length) | |
9b7530cc | 573 | { |
9b7530cc | 574 | char *vaddr_atomic; |
0839ccb8 | 575 | unsigned long unwritten; |
9b7530cc | 576 | |
fca3ec01 | 577 | vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base, KM_USER0); |
0839ccb8 KP |
578 | unwritten = __copy_from_user_inatomic_nocache(vaddr_atomic + page_offset, |
579 | user_data, length); | |
fca3ec01 | 580 | io_mapping_unmap_atomic(vaddr_atomic, KM_USER0); |
0839ccb8 KP |
581 | if (unwritten) |
582 | return -EFAULT; | |
583 | return 0; | |
584 | } | |
585 | ||
586 | /* Here's the write path which can sleep for | |
587 | * page faults | |
588 | */ | |
589 | ||
ab34c226 | 590 | static inline void |
3de09aa3 EA |
591 | slow_kernel_write(struct io_mapping *mapping, |
592 | loff_t gtt_base, int gtt_offset, | |
593 | struct page *user_page, int user_offset, | |
594 | int length) | |
0839ccb8 | 595 | { |
ab34c226 CW |
596 | char __iomem *dst_vaddr; |
597 | char *src_vaddr; | |
0839ccb8 | 598 | |
ab34c226 CW |
599 | dst_vaddr = io_mapping_map_wc(mapping, gtt_base); |
600 | src_vaddr = kmap(user_page); | |
601 | ||
602 | memcpy_toio(dst_vaddr + gtt_offset, | |
603 | src_vaddr + user_offset, | |
604 | length); | |
605 | ||
606 | kunmap(user_page); | |
607 | io_mapping_unmap(dst_vaddr); | |
9b7530cc LT |
608 | } |
609 | ||
40123c1f EA |
610 | static inline int |
611 | fast_shmem_write(struct page **pages, | |
612 | loff_t page_base, int page_offset, | |
613 | char __user *data, | |
614 | int length) | |
615 | { | |
616 | char __iomem *vaddr; | |
d0088775 | 617 | unsigned long unwritten; |
40123c1f EA |
618 | |
619 | vaddr = kmap_atomic(pages[page_base >> PAGE_SHIFT], KM_USER0); | |
620 | if (vaddr == NULL) | |
621 | return -ENOMEM; | |
d0088775 | 622 | unwritten = __copy_from_user_inatomic(vaddr + page_offset, data, length); |
40123c1f EA |
623 | kunmap_atomic(vaddr, KM_USER0); |
624 | ||
d0088775 DA |
625 | if (unwritten) |
626 | return -EFAULT; | |
40123c1f EA |
627 | return 0; |
628 | } | |
629 | ||
3de09aa3 EA |
630 | /** |
631 | * This is the fast pwrite path, where we copy the data directly from the | |
632 | * user into the GTT, uncached. | |
633 | */ | |
673a394b | 634 | static int |
3de09aa3 EA |
635 | i915_gem_gtt_pwrite_fast(struct drm_device *dev, struct drm_gem_object *obj, |
636 | struct drm_i915_gem_pwrite *args, | |
637 | struct drm_file *file_priv) | |
673a394b | 638 | { |
23010e43 | 639 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
0839ccb8 | 640 | drm_i915_private_t *dev_priv = dev->dev_private; |
673a394b | 641 | ssize_t remain; |
0839ccb8 | 642 | loff_t offset, page_base; |
673a394b | 643 | char __user *user_data; |
0839ccb8 KP |
644 | int page_offset, page_length; |
645 | int ret; | |
673a394b EA |
646 | |
647 | user_data = (char __user *) (uintptr_t) args->data_ptr; | |
648 | remain = args->size; | |
649 | if (!access_ok(VERIFY_READ, user_data, remain)) | |
650 | return -EFAULT; | |
651 | ||
76c1dec1 CW |
652 | ret = i915_mutex_lock_interruptible(dev); |
653 | if (ret) | |
654 | return ret; | |
673a394b | 655 | |
673a394b EA |
656 | ret = i915_gem_object_pin(obj, 0); |
657 | if (ret) { | |
658 | mutex_unlock(&dev->struct_mutex); | |
659 | return ret; | |
660 | } | |
2ef7eeaa | 661 | ret = i915_gem_object_set_to_gtt_domain(obj, 1); |
673a394b EA |
662 | if (ret) |
663 | goto fail; | |
664 | ||
23010e43 | 665 | obj_priv = to_intel_bo(obj); |
673a394b | 666 | offset = obj_priv->gtt_offset + args->offset; |
673a394b EA |
667 | |
668 | while (remain > 0) { | |
669 | /* Operation in this page | |
670 | * | |
0839ccb8 KP |
671 | * page_base = page offset within aperture |
672 | * page_offset = offset within page | |
673 | * page_length = bytes to copy for this page | |
673a394b | 674 | */ |
0839ccb8 KP |
675 | page_base = (offset & ~(PAGE_SIZE-1)); |
676 | page_offset = offset & (PAGE_SIZE-1); | |
677 | page_length = remain; | |
678 | if ((page_offset + remain) > PAGE_SIZE) | |
679 | page_length = PAGE_SIZE - page_offset; | |
680 | ||
681 | ret = fast_user_write (dev_priv->mm.gtt_mapping, page_base, | |
682 | page_offset, user_data, page_length); | |
683 | ||
684 | /* If we get a fault while copying data, then (presumably) our | |
3de09aa3 EA |
685 | * source page isn't available. Return the error and we'll |
686 | * retry in the slow path. | |
0839ccb8 | 687 | */ |
3de09aa3 EA |
688 | if (ret) |
689 | goto fail; | |
673a394b | 690 | |
0839ccb8 KP |
691 | remain -= page_length; |
692 | user_data += page_length; | |
693 | offset += page_length; | |
673a394b | 694 | } |
673a394b EA |
695 | |
696 | fail: | |
697 | i915_gem_object_unpin(obj); | |
698 | mutex_unlock(&dev->struct_mutex); | |
699 | ||
700 | return ret; | |
701 | } | |
702 | ||
3de09aa3 EA |
703 | /** |
704 | * This is the fallback GTT pwrite path, which uses get_user_pages to pin | |
705 | * the memory and maps it using kmap_atomic for copying. | |
706 | * | |
707 | * This code resulted in x11perf -rgb10text consuming about 10% more CPU | |
708 | * than using i915_gem_gtt_pwrite_fast on a G45 (32-bit). | |
709 | */ | |
3043c60c | 710 | static int |
3de09aa3 EA |
711 | i915_gem_gtt_pwrite_slow(struct drm_device *dev, struct drm_gem_object *obj, |
712 | struct drm_i915_gem_pwrite *args, | |
713 | struct drm_file *file_priv) | |
673a394b | 714 | { |
23010e43 | 715 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
3de09aa3 EA |
716 | drm_i915_private_t *dev_priv = dev->dev_private; |
717 | ssize_t remain; | |
718 | loff_t gtt_page_base, offset; | |
719 | loff_t first_data_page, last_data_page, num_pages; | |
720 | loff_t pinned_pages, i; | |
721 | struct page **user_pages; | |
722 | struct mm_struct *mm = current->mm; | |
723 | int gtt_page_offset, data_page_offset, data_page_index, page_length; | |
673a394b | 724 | int ret; |
3de09aa3 EA |
725 | uint64_t data_ptr = args->data_ptr; |
726 | ||
727 | remain = args->size; | |
728 | ||
729 | /* Pin the user pages containing the data. We can't fault while | |
730 | * holding the struct mutex, and all of the pwrite implementations | |
731 | * want to hold it while dereferencing the user data. | |
732 | */ | |
733 | first_data_page = data_ptr / PAGE_SIZE; | |
734 | last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE; | |
735 | num_pages = last_data_page - first_data_page + 1; | |
736 | ||
8e7d2b2c | 737 | user_pages = drm_calloc_large(num_pages, sizeof(struct page *)); |
3de09aa3 EA |
738 | if (user_pages == NULL) |
739 | return -ENOMEM; | |
740 | ||
741 | down_read(&mm->mmap_sem); | |
742 | pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr, | |
743 | num_pages, 0, 0, user_pages, NULL); | |
744 | up_read(&mm->mmap_sem); | |
745 | if (pinned_pages < num_pages) { | |
746 | ret = -EFAULT; | |
747 | goto out_unpin_pages; | |
748 | } | |
673a394b | 749 | |
76c1dec1 CW |
750 | ret = i915_mutex_lock_interruptible(dev); |
751 | if (ret) | |
752 | goto out_unpin_pages; | |
753 | ||
3de09aa3 EA |
754 | ret = i915_gem_object_pin(obj, 0); |
755 | if (ret) | |
756 | goto out_unlock; | |
757 | ||
758 | ret = i915_gem_object_set_to_gtt_domain(obj, 1); | |
759 | if (ret) | |
760 | goto out_unpin_object; | |
761 | ||
23010e43 | 762 | obj_priv = to_intel_bo(obj); |
3de09aa3 EA |
763 | offset = obj_priv->gtt_offset + args->offset; |
764 | ||
765 | while (remain > 0) { | |
766 | /* Operation in this page | |
767 | * | |
768 | * gtt_page_base = page offset within aperture | |
769 | * gtt_page_offset = offset within page in aperture | |
770 | * data_page_index = page number in get_user_pages return | |
771 | * data_page_offset = offset with data_page_index page. | |
772 | * page_length = bytes to copy for this page | |
773 | */ | |
774 | gtt_page_base = offset & PAGE_MASK; | |
775 | gtt_page_offset = offset & ~PAGE_MASK; | |
776 | data_page_index = data_ptr / PAGE_SIZE - first_data_page; | |
777 | data_page_offset = data_ptr & ~PAGE_MASK; | |
778 | ||
779 | page_length = remain; | |
780 | if ((gtt_page_offset + page_length) > PAGE_SIZE) | |
781 | page_length = PAGE_SIZE - gtt_page_offset; | |
782 | if ((data_page_offset + page_length) > PAGE_SIZE) | |
783 | page_length = PAGE_SIZE - data_page_offset; | |
784 | ||
ab34c226 CW |
785 | slow_kernel_write(dev_priv->mm.gtt_mapping, |
786 | gtt_page_base, gtt_page_offset, | |
787 | user_pages[data_page_index], | |
788 | data_page_offset, | |
789 | page_length); | |
3de09aa3 EA |
790 | |
791 | remain -= page_length; | |
792 | offset += page_length; | |
793 | data_ptr += page_length; | |
794 | } | |
795 | ||
796 | out_unpin_object: | |
797 | i915_gem_object_unpin(obj); | |
798 | out_unlock: | |
799 | mutex_unlock(&dev->struct_mutex); | |
800 | out_unpin_pages: | |
801 | for (i = 0; i < pinned_pages; i++) | |
802 | page_cache_release(user_pages[i]); | |
8e7d2b2c | 803 | drm_free_large(user_pages); |
3de09aa3 EA |
804 | |
805 | return ret; | |
806 | } | |
807 | ||
40123c1f EA |
808 | /** |
809 | * This is the fast shmem pwrite path, which attempts to directly | |
810 | * copy_from_user into the kmapped pages backing the object. | |
811 | */ | |
3043c60c | 812 | static int |
40123c1f EA |
813 | i915_gem_shmem_pwrite_fast(struct drm_device *dev, struct drm_gem_object *obj, |
814 | struct drm_i915_gem_pwrite *args, | |
815 | struct drm_file *file_priv) | |
673a394b | 816 | { |
23010e43 | 817 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
40123c1f EA |
818 | ssize_t remain; |
819 | loff_t offset, page_base; | |
820 | char __user *user_data; | |
821 | int page_offset, page_length; | |
673a394b | 822 | int ret; |
40123c1f EA |
823 | |
824 | user_data = (char __user *) (uintptr_t) args->data_ptr; | |
825 | remain = args->size; | |
673a394b | 826 | |
76c1dec1 CW |
827 | ret = i915_mutex_lock_interruptible(dev); |
828 | if (ret) | |
829 | return ret; | |
673a394b | 830 | |
4bdadb97 | 831 | ret = i915_gem_object_get_pages(obj, 0); |
40123c1f EA |
832 | if (ret != 0) |
833 | goto fail_unlock; | |
673a394b | 834 | |
e47c68e9 | 835 | ret = i915_gem_object_set_to_cpu_domain(obj, 1); |
40123c1f EA |
836 | if (ret != 0) |
837 | goto fail_put_pages; | |
838 | ||
23010e43 | 839 | obj_priv = to_intel_bo(obj); |
40123c1f EA |
840 | offset = args->offset; |
841 | obj_priv->dirty = 1; | |
842 | ||
843 | while (remain > 0) { | |
844 | /* Operation in this page | |
845 | * | |
846 | * page_base = page offset within aperture | |
847 | * page_offset = offset within page | |
848 | * page_length = bytes to copy for this page | |
849 | */ | |
850 | page_base = (offset & ~(PAGE_SIZE-1)); | |
851 | page_offset = offset & (PAGE_SIZE-1); | |
852 | page_length = remain; | |
853 | if ((page_offset + remain) > PAGE_SIZE) | |
854 | page_length = PAGE_SIZE - page_offset; | |
855 | ||
856 | ret = fast_shmem_write(obj_priv->pages, | |
857 | page_base, page_offset, | |
858 | user_data, page_length); | |
859 | if (ret) | |
860 | goto fail_put_pages; | |
861 | ||
862 | remain -= page_length; | |
863 | user_data += page_length; | |
864 | offset += page_length; | |
865 | } | |
866 | ||
867 | fail_put_pages: | |
868 | i915_gem_object_put_pages(obj); | |
869 | fail_unlock: | |
870 | mutex_unlock(&dev->struct_mutex); | |
871 | ||
872 | return ret; | |
873 | } | |
874 | ||
875 | /** | |
876 | * This is the fallback shmem pwrite path, which uses get_user_pages to pin | |
877 | * the memory and maps it using kmap_atomic for copying. | |
878 | * | |
879 | * This avoids taking mmap_sem for faulting on the user's address while the | |
880 | * struct_mutex is held. | |
881 | */ | |
882 | static int | |
883 | i915_gem_shmem_pwrite_slow(struct drm_device *dev, struct drm_gem_object *obj, | |
884 | struct drm_i915_gem_pwrite *args, | |
885 | struct drm_file *file_priv) | |
886 | { | |
23010e43 | 887 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
40123c1f EA |
888 | struct mm_struct *mm = current->mm; |
889 | struct page **user_pages; | |
890 | ssize_t remain; | |
891 | loff_t offset, pinned_pages, i; | |
892 | loff_t first_data_page, last_data_page, num_pages; | |
893 | int shmem_page_index, shmem_page_offset; | |
894 | int data_page_index, data_page_offset; | |
895 | int page_length; | |
896 | int ret; | |
897 | uint64_t data_ptr = args->data_ptr; | |
280b713b | 898 | int do_bit17_swizzling; |
40123c1f EA |
899 | |
900 | remain = args->size; | |
901 | ||
902 | /* Pin the user pages containing the data. We can't fault while | |
903 | * holding the struct mutex, and all of the pwrite implementations | |
904 | * want to hold it while dereferencing the user data. | |
905 | */ | |
906 | first_data_page = data_ptr / PAGE_SIZE; | |
907 | last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE; | |
908 | num_pages = last_data_page - first_data_page + 1; | |
909 | ||
8e7d2b2c | 910 | user_pages = drm_calloc_large(num_pages, sizeof(struct page *)); |
40123c1f EA |
911 | if (user_pages == NULL) |
912 | return -ENOMEM; | |
913 | ||
914 | down_read(&mm->mmap_sem); | |
915 | pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr, | |
916 | num_pages, 0, 0, user_pages, NULL); | |
917 | up_read(&mm->mmap_sem); | |
918 | if (pinned_pages < num_pages) { | |
919 | ret = -EFAULT; | |
920 | goto fail_put_user_pages; | |
673a394b EA |
921 | } |
922 | ||
280b713b EA |
923 | do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj); |
924 | ||
76c1dec1 CW |
925 | ret = i915_mutex_lock_interruptible(dev); |
926 | if (ret) | |
927 | goto fail_put_user_pages; | |
40123c1f | 928 | |
07f73f69 CW |
929 | ret = i915_gem_object_get_pages_or_evict(obj); |
930 | if (ret) | |
40123c1f EA |
931 | goto fail_unlock; |
932 | ||
933 | ret = i915_gem_object_set_to_cpu_domain(obj, 1); | |
934 | if (ret != 0) | |
935 | goto fail_put_pages; | |
936 | ||
23010e43 | 937 | obj_priv = to_intel_bo(obj); |
673a394b | 938 | offset = args->offset; |
40123c1f | 939 | obj_priv->dirty = 1; |
673a394b | 940 | |
40123c1f EA |
941 | while (remain > 0) { |
942 | /* Operation in this page | |
943 | * | |
944 | * shmem_page_index = page number within shmem file | |
945 | * shmem_page_offset = offset within page in shmem file | |
946 | * data_page_index = page number in get_user_pages return | |
947 | * data_page_offset = offset with data_page_index page. | |
948 | * page_length = bytes to copy for this page | |
949 | */ | |
950 | shmem_page_index = offset / PAGE_SIZE; | |
951 | shmem_page_offset = offset & ~PAGE_MASK; | |
952 | data_page_index = data_ptr / PAGE_SIZE - first_data_page; | |
953 | data_page_offset = data_ptr & ~PAGE_MASK; | |
954 | ||
955 | page_length = remain; | |
956 | if ((shmem_page_offset + page_length) > PAGE_SIZE) | |
957 | page_length = PAGE_SIZE - shmem_page_offset; | |
958 | if ((data_page_offset + page_length) > PAGE_SIZE) | |
959 | page_length = PAGE_SIZE - data_page_offset; | |
960 | ||
280b713b | 961 | if (do_bit17_swizzling) { |
99a03df5 | 962 | slow_shmem_bit17_copy(obj_priv->pages[shmem_page_index], |
280b713b EA |
963 | shmem_page_offset, |
964 | user_pages[data_page_index], | |
965 | data_page_offset, | |
99a03df5 CW |
966 | page_length, |
967 | 0); | |
968 | } else { | |
969 | slow_shmem_copy(obj_priv->pages[shmem_page_index], | |
970 | shmem_page_offset, | |
971 | user_pages[data_page_index], | |
972 | data_page_offset, | |
973 | page_length); | |
280b713b | 974 | } |
40123c1f EA |
975 | |
976 | remain -= page_length; | |
977 | data_ptr += page_length; | |
978 | offset += page_length; | |
673a394b EA |
979 | } |
980 | ||
40123c1f EA |
981 | fail_put_pages: |
982 | i915_gem_object_put_pages(obj); | |
983 | fail_unlock: | |
673a394b | 984 | mutex_unlock(&dev->struct_mutex); |
40123c1f EA |
985 | fail_put_user_pages: |
986 | for (i = 0; i < pinned_pages; i++) | |
987 | page_cache_release(user_pages[i]); | |
8e7d2b2c | 988 | drm_free_large(user_pages); |
673a394b | 989 | |
40123c1f | 990 | return ret; |
673a394b EA |
991 | } |
992 | ||
993 | /** | |
994 | * Writes data to the object referenced by handle. | |
995 | * | |
996 | * On error, the contents of the buffer that were to be modified are undefined. | |
997 | */ | |
998 | int | |
999 | i915_gem_pwrite_ioctl(struct drm_device *dev, void *data, | |
1000 | struct drm_file *file_priv) | |
1001 | { | |
1002 | struct drm_i915_gem_pwrite *args = data; | |
1003 | struct drm_gem_object *obj; | |
1004 | struct drm_i915_gem_object *obj_priv; | |
1005 | int ret = 0; | |
1006 | ||
1007 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); | |
1008 | if (obj == NULL) | |
bf79cb91 | 1009 | return -ENOENT; |
23010e43 | 1010 | obj_priv = to_intel_bo(obj); |
673a394b EA |
1011 | |
1012 | /* Bounds check destination. | |
1013 | * | |
1014 | * XXX: This could use review for overflow issues... | |
1015 | */ | |
1016 | if (args->offset > obj->size || args->size > obj->size || | |
1017 | args->offset + args->size > obj->size) { | |
bc9025bd | 1018 | drm_gem_object_unreference_unlocked(obj); |
673a394b EA |
1019 | return -EINVAL; |
1020 | } | |
1021 | ||
1022 | /* We can only do the GTT pwrite on untiled buffers, as otherwise | |
1023 | * it would end up going through the fenced access, and we'll get | |
1024 | * different detiling behavior between reading and writing. | |
1025 | * pread/pwrite currently are reading and writing from the CPU | |
1026 | * perspective, requiring manual detiling by the client. | |
1027 | */ | |
71acb5eb DA |
1028 | if (obj_priv->phys_obj) |
1029 | ret = i915_gem_phys_pwrite(dev, obj, args, file_priv); | |
1030 | else if (obj_priv->tiling_mode == I915_TILING_NONE && | |
5cdf5881 | 1031 | obj_priv->gtt_space && |
9b8c4a0b | 1032 | obj->write_domain != I915_GEM_DOMAIN_CPU) { |
3de09aa3 EA |
1033 | ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file_priv); |
1034 | if (ret == -EFAULT) { | |
1035 | ret = i915_gem_gtt_pwrite_slow(dev, obj, args, | |
1036 | file_priv); | |
1037 | } | |
280b713b EA |
1038 | } else if (i915_gem_object_needs_bit17_swizzle(obj)) { |
1039 | ret = i915_gem_shmem_pwrite_slow(dev, obj, args, file_priv); | |
40123c1f EA |
1040 | } else { |
1041 | ret = i915_gem_shmem_pwrite_fast(dev, obj, args, file_priv); | |
1042 | if (ret == -EFAULT) { | |
1043 | ret = i915_gem_shmem_pwrite_slow(dev, obj, args, | |
1044 | file_priv); | |
1045 | } | |
1046 | } | |
673a394b EA |
1047 | |
1048 | #if WATCH_PWRITE | |
1049 | if (ret) | |
1050 | DRM_INFO("pwrite failed %d\n", ret); | |
1051 | #endif | |
1052 | ||
bc9025bd | 1053 | drm_gem_object_unreference_unlocked(obj); |
673a394b EA |
1054 | |
1055 | return ret; | |
1056 | } | |
1057 | ||
1058 | /** | |
2ef7eeaa EA |
1059 | * Called when user space prepares to use an object with the CPU, either |
1060 | * through the mmap ioctl's mapping or a GTT mapping. | |
673a394b EA |
1061 | */ |
1062 | int | |
1063 | i915_gem_set_domain_ioctl(struct drm_device *dev, void *data, | |
1064 | struct drm_file *file_priv) | |
1065 | { | |
a09ba7fa | 1066 | struct drm_i915_private *dev_priv = dev->dev_private; |
673a394b EA |
1067 | struct drm_i915_gem_set_domain *args = data; |
1068 | struct drm_gem_object *obj; | |
652c393a | 1069 | struct drm_i915_gem_object *obj_priv; |
2ef7eeaa EA |
1070 | uint32_t read_domains = args->read_domains; |
1071 | uint32_t write_domain = args->write_domain; | |
673a394b EA |
1072 | int ret; |
1073 | ||
1074 | if (!(dev->driver->driver_features & DRIVER_GEM)) | |
1075 | return -ENODEV; | |
1076 | ||
2ef7eeaa | 1077 | /* Only handle setting domains to types used by the CPU. */ |
21d509e3 | 1078 | if (write_domain & I915_GEM_GPU_DOMAINS) |
2ef7eeaa EA |
1079 | return -EINVAL; |
1080 | ||
21d509e3 | 1081 | if (read_domains & I915_GEM_GPU_DOMAINS) |
2ef7eeaa EA |
1082 | return -EINVAL; |
1083 | ||
1084 | /* Having something in the write domain implies it's in the read | |
1085 | * domain, and only that read domain. Enforce that in the request. | |
1086 | */ | |
1087 | if (write_domain != 0 && read_domains != write_domain) | |
1088 | return -EINVAL; | |
1089 | ||
673a394b EA |
1090 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); |
1091 | if (obj == NULL) | |
bf79cb91 | 1092 | return -ENOENT; |
23010e43 | 1093 | obj_priv = to_intel_bo(obj); |
673a394b | 1094 | |
76c1dec1 CW |
1095 | ret = i915_mutex_lock_interruptible(dev); |
1096 | if (ret) { | |
1097 | drm_gem_object_unreference_unlocked(obj); | |
1098 | return ret; | |
1099 | } | |
652c393a JB |
1100 | |
1101 | intel_mark_busy(dev, obj); | |
1102 | ||
2ef7eeaa EA |
1103 | if (read_domains & I915_GEM_DOMAIN_GTT) { |
1104 | ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0); | |
02354392 | 1105 | |
a09ba7fa EA |
1106 | /* Update the LRU on the fence for the CPU access that's |
1107 | * about to occur. | |
1108 | */ | |
1109 | if (obj_priv->fence_reg != I915_FENCE_REG_NONE) { | |
007cc8ac DV |
1110 | struct drm_i915_fence_reg *reg = |
1111 | &dev_priv->fence_regs[obj_priv->fence_reg]; | |
1112 | list_move_tail(®->lru_list, | |
a09ba7fa EA |
1113 | &dev_priv->mm.fence_list); |
1114 | } | |
1115 | ||
02354392 EA |
1116 | /* Silently promote "you're not bound, there was nothing to do" |
1117 | * to success, since the client was just asking us to | |
1118 | * make sure everything was done. | |
1119 | */ | |
1120 | if (ret == -EINVAL) | |
1121 | ret = 0; | |
2ef7eeaa | 1122 | } else { |
e47c68e9 | 1123 | ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0); |
2ef7eeaa EA |
1124 | } |
1125 | ||
7d1c4804 CW |
1126 | /* Maintain LRU order of "inactive" objects */ |
1127 | if (ret == 0 && i915_gem_object_is_inactive(obj_priv)) | |
1128 | list_move_tail(&obj_priv->list, &dev_priv->mm.inactive_list); | |
1129 | ||
673a394b EA |
1130 | drm_gem_object_unreference(obj); |
1131 | mutex_unlock(&dev->struct_mutex); | |
1132 | return ret; | |
1133 | } | |
1134 | ||
1135 | /** | |
1136 | * Called when user space has done writes to this buffer | |
1137 | */ | |
1138 | int | |
1139 | i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data, | |
1140 | struct drm_file *file_priv) | |
1141 | { | |
1142 | struct drm_i915_gem_sw_finish *args = data; | |
1143 | struct drm_gem_object *obj; | |
673a394b EA |
1144 | int ret = 0; |
1145 | ||
1146 | if (!(dev->driver->driver_features & DRIVER_GEM)) | |
1147 | return -ENODEV; | |
1148 | ||
673a394b | 1149 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); |
76c1dec1 | 1150 | if (obj == NULL) |
bf79cb91 | 1151 | return -ENOENT; |
76c1dec1 CW |
1152 | |
1153 | ret = i915_mutex_lock_interruptible(dev); | |
1154 | if (ret) { | |
1155 | drm_gem_object_unreference_unlocked(obj); | |
1156 | return ret; | |
673a394b EA |
1157 | } |
1158 | ||
673a394b | 1159 | /* Pinned buffers may be scanout, so flush the cache */ |
3d2a812a | 1160 | if (to_intel_bo(obj)->pin_count) |
e47c68e9 EA |
1161 | i915_gem_object_flush_cpu_write_domain(obj); |
1162 | ||
673a394b EA |
1163 | drm_gem_object_unreference(obj); |
1164 | mutex_unlock(&dev->struct_mutex); | |
1165 | return ret; | |
1166 | } | |
1167 | ||
1168 | /** | |
1169 | * Maps the contents of an object, returning the address it is mapped | |
1170 | * into. | |
1171 | * | |
1172 | * While the mapping holds a reference on the contents of the object, it doesn't | |
1173 | * imply a ref on the object itself. | |
1174 | */ | |
1175 | int | |
1176 | i915_gem_mmap_ioctl(struct drm_device *dev, void *data, | |
1177 | struct drm_file *file_priv) | |
1178 | { | |
1179 | struct drm_i915_gem_mmap *args = data; | |
1180 | struct drm_gem_object *obj; | |
1181 | loff_t offset; | |
1182 | unsigned long addr; | |
1183 | ||
1184 | if (!(dev->driver->driver_features & DRIVER_GEM)) | |
1185 | return -ENODEV; | |
1186 | ||
1187 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); | |
1188 | if (obj == NULL) | |
bf79cb91 | 1189 | return -ENOENT; |
673a394b EA |
1190 | |
1191 | offset = args->offset; | |
1192 | ||
1193 | down_write(¤t->mm->mmap_sem); | |
1194 | addr = do_mmap(obj->filp, 0, args->size, | |
1195 | PROT_READ | PROT_WRITE, MAP_SHARED, | |
1196 | args->offset); | |
1197 | up_write(¤t->mm->mmap_sem); | |
bc9025bd | 1198 | drm_gem_object_unreference_unlocked(obj); |
673a394b EA |
1199 | if (IS_ERR((void *)addr)) |
1200 | return addr; | |
1201 | ||
1202 | args->addr_ptr = (uint64_t) addr; | |
1203 | ||
1204 | return 0; | |
1205 | } | |
1206 | ||
de151cf6 JB |
1207 | /** |
1208 | * i915_gem_fault - fault a page into the GTT | |
1209 | * vma: VMA in question | |
1210 | * vmf: fault info | |
1211 | * | |
1212 | * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped | |
1213 | * from userspace. The fault handler takes care of binding the object to | |
1214 | * the GTT (if needed), allocating and programming a fence register (again, | |
1215 | * only if needed based on whether the old reg is still valid or the object | |
1216 | * is tiled) and inserting a new PTE into the faulting process. | |
1217 | * | |
1218 | * Note that the faulting process may involve evicting existing objects | |
1219 | * from the GTT and/or fence registers to make room. So performance may | |
1220 | * suffer if the GTT working set is large or there are few fence registers | |
1221 | * left. | |
1222 | */ | |
1223 | int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf) | |
1224 | { | |
1225 | struct drm_gem_object *obj = vma->vm_private_data; | |
1226 | struct drm_device *dev = obj->dev; | |
7d1c4804 | 1227 | drm_i915_private_t *dev_priv = dev->dev_private; |
23010e43 | 1228 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
de151cf6 JB |
1229 | pgoff_t page_offset; |
1230 | unsigned long pfn; | |
1231 | int ret = 0; | |
0f973f27 | 1232 | bool write = !!(vmf->flags & FAULT_FLAG_WRITE); |
de151cf6 JB |
1233 | |
1234 | /* We don't use vmf->pgoff since that has the fake offset */ | |
1235 | page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >> | |
1236 | PAGE_SHIFT; | |
1237 | ||
1238 | /* Now bind it into the GTT if needed */ | |
1239 | mutex_lock(&dev->struct_mutex); | |
1240 | if (!obj_priv->gtt_space) { | |
e67b8ce1 | 1241 | ret = i915_gem_object_bind_to_gtt(obj, 0); |
c715089f CW |
1242 | if (ret) |
1243 | goto unlock; | |
07f4f3e8 | 1244 | |
07f4f3e8 | 1245 | ret = i915_gem_object_set_to_gtt_domain(obj, write); |
c715089f CW |
1246 | if (ret) |
1247 | goto unlock; | |
de151cf6 JB |
1248 | } |
1249 | ||
1250 | /* Need a new fence register? */ | |
a09ba7fa | 1251 | if (obj_priv->tiling_mode != I915_TILING_NONE) { |
2cf34d7b | 1252 | ret = i915_gem_object_get_fence_reg(obj, true); |
c715089f CW |
1253 | if (ret) |
1254 | goto unlock; | |
d9ddcb96 | 1255 | } |
de151cf6 | 1256 | |
7d1c4804 CW |
1257 | if (i915_gem_object_is_inactive(obj_priv)) |
1258 | list_move_tail(&obj_priv->list, &dev_priv->mm.inactive_list); | |
1259 | ||
de151cf6 JB |
1260 | pfn = ((dev->agp->base + obj_priv->gtt_offset) >> PAGE_SHIFT) + |
1261 | page_offset; | |
1262 | ||
1263 | /* Finally, remap it using the new GTT offset */ | |
1264 | ret = vm_insert_pfn(vma, (unsigned long)vmf->virtual_address, pfn); | |
c715089f | 1265 | unlock: |
de151cf6 JB |
1266 | mutex_unlock(&dev->struct_mutex); |
1267 | ||
1268 | switch (ret) { | |
c715089f CW |
1269 | case 0: |
1270 | case -ERESTARTSYS: | |
1271 | return VM_FAULT_NOPAGE; | |
de151cf6 JB |
1272 | case -ENOMEM: |
1273 | case -EAGAIN: | |
1274 | return VM_FAULT_OOM; | |
de151cf6 | 1275 | default: |
c715089f | 1276 | return VM_FAULT_SIGBUS; |
de151cf6 JB |
1277 | } |
1278 | } | |
1279 | ||
1280 | /** | |
1281 | * i915_gem_create_mmap_offset - create a fake mmap offset for an object | |
1282 | * @obj: obj in question | |
1283 | * | |
1284 | * GEM memory mapping works by handing back to userspace a fake mmap offset | |
1285 | * it can use in a subsequent mmap(2) call. The DRM core code then looks | |
1286 | * up the object based on the offset and sets up the various memory mapping | |
1287 | * structures. | |
1288 | * | |
1289 | * This routine allocates and attaches a fake offset for @obj. | |
1290 | */ | |
1291 | static int | |
1292 | i915_gem_create_mmap_offset(struct drm_gem_object *obj) | |
1293 | { | |
1294 | struct drm_device *dev = obj->dev; | |
1295 | struct drm_gem_mm *mm = dev->mm_private; | |
23010e43 | 1296 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
de151cf6 | 1297 | struct drm_map_list *list; |
f77d390c | 1298 | struct drm_local_map *map; |
de151cf6 JB |
1299 | int ret = 0; |
1300 | ||
1301 | /* Set the object up for mmap'ing */ | |
1302 | list = &obj->map_list; | |
9a298b2a | 1303 | list->map = kzalloc(sizeof(struct drm_map_list), GFP_KERNEL); |
de151cf6 JB |
1304 | if (!list->map) |
1305 | return -ENOMEM; | |
1306 | ||
1307 | map = list->map; | |
1308 | map->type = _DRM_GEM; | |
1309 | map->size = obj->size; | |
1310 | map->handle = obj; | |
1311 | ||
1312 | /* Get a DRM GEM mmap offset allocated... */ | |
1313 | list->file_offset_node = drm_mm_search_free(&mm->offset_manager, | |
1314 | obj->size / PAGE_SIZE, 0, 0); | |
1315 | if (!list->file_offset_node) { | |
1316 | DRM_ERROR("failed to allocate offset for bo %d\n", obj->name); | |
9e0ae534 | 1317 | ret = -ENOSPC; |
de151cf6 JB |
1318 | goto out_free_list; |
1319 | } | |
1320 | ||
1321 | list->file_offset_node = drm_mm_get_block(list->file_offset_node, | |
1322 | obj->size / PAGE_SIZE, 0); | |
1323 | if (!list->file_offset_node) { | |
1324 | ret = -ENOMEM; | |
1325 | goto out_free_list; | |
1326 | } | |
1327 | ||
1328 | list->hash.key = list->file_offset_node->start; | |
9e0ae534 CW |
1329 | ret = drm_ht_insert_item(&mm->offset_hash, &list->hash); |
1330 | if (ret) { | |
de151cf6 JB |
1331 | DRM_ERROR("failed to add to map hash\n"); |
1332 | goto out_free_mm; | |
1333 | } | |
1334 | ||
1335 | /* By now we should be all set, any drm_mmap request on the offset | |
1336 | * below will get to our mmap & fault handler */ | |
1337 | obj_priv->mmap_offset = ((uint64_t) list->hash.key) << PAGE_SHIFT; | |
1338 | ||
1339 | return 0; | |
1340 | ||
1341 | out_free_mm: | |
1342 | drm_mm_put_block(list->file_offset_node); | |
1343 | out_free_list: | |
9a298b2a | 1344 | kfree(list->map); |
de151cf6 JB |
1345 | |
1346 | return ret; | |
1347 | } | |
1348 | ||
901782b2 CW |
1349 | /** |
1350 | * i915_gem_release_mmap - remove physical page mappings | |
1351 | * @obj: obj in question | |
1352 | * | |
af901ca1 | 1353 | * Preserve the reservation of the mmapping with the DRM core code, but |
901782b2 CW |
1354 | * relinquish ownership of the pages back to the system. |
1355 | * | |
1356 | * It is vital that we remove the page mapping if we have mapped a tiled | |
1357 | * object through the GTT and then lose the fence register due to | |
1358 | * resource pressure. Similarly if the object has been moved out of the | |
1359 | * aperture, than pages mapped into userspace must be revoked. Removing the | |
1360 | * mapping will then trigger a page fault on the next user access, allowing | |
1361 | * fixup by i915_gem_fault(). | |
1362 | */ | |
d05ca301 | 1363 | void |
901782b2 CW |
1364 | i915_gem_release_mmap(struct drm_gem_object *obj) |
1365 | { | |
1366 | struct drm_device *dev = obj->dev; | |
23010e43 | 1367 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
901782b2 CW |
1368 | |
1369 | if (dev->dev_mapping) | |
1370 | unmap_mapping_range(dev->dev_mapping, | |
1371 | obj_priv->mmap_offset, obj->size, 1); | |
1372 | } | |
1373 | ||
ab00b3e5 JB |
1374 | static void |
1375 | i915_gem_free_mmap_offset(struct drm_gem_object *obj) | |
1376 | { | |
1377 | struct drm_device *dev = obj->dev; | |
23010e43 | 1378 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
ab00b3e5 JB |
1379 | struct drm_gem_mm *mm = dev->mm_private; |
1380 | struct drm_map_list *list; | |
1381 | ||
1382 | list = &obj->map_list; | |
1383 | drm_ht_remove_item(&mm->offset_hash, &list->hash); | |
1384 | ||
1385 | if (list->file_offset_node) { | |
1386 | drm_mm_put_block(list->file_offset_node); | |
1387 | list->file_offset_node = NULL; | |
1388 | } | |
1389 | ||
1390 | if (list->map) { | |
9a298b2a | 1391 | kfree(list->map); |
ab00b3e5 JB |
1392 | list->map = NULL; |
1393 | } | |
1394 | ||
1395 | obj_priv->mmap_offset = 0; | |
1396 | } | |
1397 | ||
de151cf6 JB |
1398 | /** |
1399 | * i915_gem_get_gtt_alignment - return required GTT alignment for an object | |
1400 | * @obj: object to check | |
1401 | * | |
1402 | * Return the required GTT alignment for an object, taking into account | |
1403 | * potential fence register mapping if needed. | |
1404 | */ | |
1405 | static uint32_t | |
1406 | i915_gem_get_gtt_alignment(struct drm_gem_object *obj) | |
1407 | { | |
1408 | struct drm_device *dev = obj->dev; | |
23010e43 | 1409 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
de151cf6 JB |
1410 | int start, i; |
1411 | ||
1412 | /* | |
1413 | * Minimum alignment is 4k (GTT page size), but might be greater | |
1414 | * if a fence register is needed for the object. | |
1415 | */ | |
a6c45cf0 | 1416 | if (INTEL_INFO(dev)->gen >= 4 || obj_priv->tiling_mode == I915_TILING_NONE) |
de151cf6 JB |
1417 | return 4096; |
1418 | ||
1419 | /* | |
1420 | * Previous chips need to be aligned to the size of the smallest | |
1421 | * fence register that can contain the object. | |
1422 | */ | |
a6c45cf0 | 1423 | if (INTEL_INFO(dev)->gen == 3) |
de151cf6 JB |
1424 | start = 1024*1024; |
1425 | else | |
1426 | start = 512*1024; | |
1427 | ||
1428 | for (i = start; i < obj->size; i <<= 1) | |
1429 | ; | |
1430 | ||
1431 | return i; | |
1432 | } | |
1433 | ||
1434 | /** | |
1435 | * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing | |
1436 | * @dev: DRM device | |
1437 | * @data: GTT mapping ioctl data | |
1438 | * @file_priv: GEM object info | |
1439 | * | |
1440 | * Simply returns the fake offset to userspace so it can mmap it. | |
1441 | * The mmap call will end up in drm_gem_mmap(), which will set things | |
1442 | * up so we can get faults in the handler above. | |
1443 | * | |
1444 | * The fault handler will take care of binding the object into the GTT | |
1445 | * (since it may have been evicted to make room for something), allocating | |
1446 | * a fence register, and mapping the appropriate aperture address into | |
1447 | * userspace. | |
1448 | */ | |
1449 | int | |
1450 | i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data, | |
1451 | struct drm_file *file_priv) | |
1452 | { | |
1453 | struct drm_i915_gem_mmap_gtt *args = data; | |
de151cf6 JB |
1454 | struct drm_gem_object *obj; |
1455 | struct drm_i915_gem_object *obj_priv; | |
1456 | int ret; | |
1457 | ||
1458 | if (!(dev->driver->driver_features & DRIVER_GEM)) | |
1459 | return -ENODEV; | |
1460 | ||
1461 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); | |
1462 | if (obj == NULL) | |
bf79cb91 | 1463 | return -ENOENT; |
de151cf6 | 1464 | |
76c1dec1 CW |
1465 | ret = i915_mutex_lock_interruptible(dev); |
1466 | if (ret) { | |
1467 | drm_gem_object_unreference_unlocked(obj); | |
1468 | return ret; | |
1469 | } | |
de151cf6 | 1470 | |
23010e43 | 1471 | obj_priv = to_intel_bo(obj); |
de151cf6 | 1472 | |
ab18282d CW |
1473 | if (obj_priv->madv != I915_MADV_WILLNEED) { |
1474 | DRM_ERROR("Attempting to mmap a purgeable buffer\n"); | |
1475 | drm_gem_object_unreference(obj); | |
1476 | mutex_unlock(&dev->struct_mutex); | |
1477 | return -EINVAL; | |
1478 | } | |
1479 | ||
1480 | ||
de151cf6 JB |
1481 | if (!obj_priv->mmap_offset) { |
1482 | ret = i915_gem_create_mmap_offset(obj); | |
13af1062 CW |
1483 | if (ret) { |
1484 | drm_gem_object_unreference(obj); | |
1485 | mutex_unlock(&dev->struct_mutex); | |
de151cf6 | 1486 | return ret; |
13af1062 | 1487 | } |
de151cf6 JB |
1488 | } |
1489 | ||
1490 | args->offset = obj_priv->mmap_offset; | |
1491 | ||
de151cf6 JB |
1492 | /* |
1493 | * Pull it into the GTT so that we have a page list (makes the | |
1494 | * initial fault faster and any subsequent flushing possible). | |
1495 | */ | |
1496 | if (!obj_priv->agp_mem) { | |
e67b8ce1 | 1497 | ret = i915_gem_object_bind_to_gtt(obj, 0); |
de151cf6 JB |
1498 | if (ret) { |
1499 | drm_gem_object_unreference(obj); | |
1500 | mutex_unlock(&dev->struct_mutex); | |
1501 | return ret; | |
1502 | } | |
de151cf6 JB |
1503 | } |
1504 | ||
1505 | drm_gem_object_unreference(obj); | |
1506 | mutex_unlock(&dev->struct_mutex); | |
1507 | ||
1508 | return 0; | |
1509 | } | |
1510 | ||
5cdf5881 | 1511 | static void |
856fa198 | 1512 | i915_gem_object_put_pages(struct drm_gem_object *obj) |
673a394b | 1513 | { |
23010e43 | 1514 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
673a394b EA |
1515 | int page_count = obj->size / PAGE_SIZE; |
1516 | int i; | |
1517 | ||
856fa198 | 1518 | BUG_ON(obj_priv->pages_refcount == 0); |
bb6baf76 | 1519 | BUG_ON(obj_priv->madv == __I915_MADV_PURGED); |
673a394b | 1520 | |
856fa198 EA |
1521 | if (--obj_priv->pages_refcount != 0) |
1522 | return; | |
673a394b | 1523 | |
280b713b EA |
1524 | if (obj_priv->tiling_mode != I915_TILING_NONE) |
1525 | i915_gem_object_save_bit_17_swizzle(obj); | |
1526 | ||
3ef94daa | 1527 | if (obj_priv->madv == I915_MADV_DONTNEED) |
13a05fd9 | 1528 | obj_priv->dirty = 0; |
3ef94daa CW |
1529 | |
1530 | for (i = 0; i < page_count; i++) { | |
3ef94daa CW |
1531 | if (obj_priv->dirty) |
1532 | set_page_dirty(obj_priv->pages[i]); | |
1533 | ||
1534 | if (obj_priv->madv == I915_MADV_WILLNEED) | |
856fa198 | 1535 | mark_page_accessed(obj_priv->pages[i]); |
3ef94daa CW |
1536 | |
1537 | page_cache_release(obj_priv->pages[i]); | |
1538 | } | |
673a394b EA |
1539 | obj_priv->dirty = 0; |
1540 | ||
8e7d2b2c | 1541 | drm_free_large(obj_priv->pages); |
856fa198 | 1542 | obj_priv->pages = NULL; |
673a394b EA |
1543 | } |
1544 | ||
a56ba56c CW |
1545 | static uint32_t |
1546 | i915_gem_next_request_seqno(struct drm_device *dev, | |
1547 | struct intel_ring_buffer *ring) | |
1548 | { | |
1549 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1550 | ||
1551 | ring->outstanding_lazy_request = true; | |
1552 | return dev_priv->next_seqno; | |
1553 | } | |
1554 | ||
673a394b | 1555 | static void |
617dbe27 | 1556 | i915_gem_object_move_to_active(struct drm_gem_object *obj, |
852835f3 | 1557 | struct intel_ring_buffer *ring) |
673a394b | 1558 | { |
a56ba56c | 1559 | struct drm_device *dev = obj->dev; |
23010e43 | 1560 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
a56ba56c | 1561 | uint32_t seqno = i915_gem_next_request_seqno(dev, ring); |
617dbe27 | 1562 | |
852835f3 ZN |
1563 | BUG_ON(ring == NULL); |
1564 | obj_priv->ring = ring; | |
673a394b EA |
1565 | |
1566 | /* Add a reference if we're newly entering the active list. */ | |
1567 | if (!obj_priv->active) { | |
1568 | drm_gem_object_reference(obj); | |
1569 | obj_priv->active = 1; | |
1570 | } | |
e35a41de | 1571 | |
673a394b | 1572 | /* Move from whatever list we were on to the tail of execution. */ |
852835f3 | 1573 | list_move_tail(&obj_priv->list, &ring->active_list); |
a56ba56c | 1574 | obj_priv->last_rendering_seqno = seqno; |
673a394b EA |
1575 | } |
1576 | ||
ce44b0ea EA |
1577 | static void |
1578 | i915_gem_object_move_to_flushing(struct drm_gem_object *obj) | |
1579 | { | |
1580 | struct drm_device *dev = obj->dev; | |
1581 | drm_i915_private_t *dev_priv = dev->dev_private; | |
23010e43 | 1582 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
ce44b0ea EA |
1583 | |
1584 | BUG_ON(!obj_priv->active); | |
1585 | list_move_tail(&obj_priv->list, &dev_priv->mm.flushing_list); | |
1586 | obj_priv->last_rendering_seqno = 0; | |
1587 | } | |
673a394b | 1588 | |
963b4836 CW |
1589 | /* Immediately discard the backing storage */ |
1590 | static void | |
1591 | i915_gem_object_truncate(struct drm_gem_object *obj) | |
1592 | { | |
23010e43 | 1593 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
bb6baf76 | 1594 | struct inode *inode; |
963b4836 | 1595 | |
ae9fed6b CW |
1596 | /* Our goal here is to return as much of the memory as |
1597 | * is possible back to the system as we are called from OOM. | |
1598 | * To do this we must instruct the shmfs to drop all of its | |
1599 | * backing pages, *now*. Here we mirror the actions taken | |
1600 | * when by shmem_delete_inode() to release the backing store. | |
1601 | */ | |
bb6baf76 | 1602 | inode = obj->filp->f_path.dentry->d_inode; |
ae9fed6b CW |
1603 | truncate_inode_pages(inode->i_mapping, 0); |
1604 | if (inode->i_op->truncate_range) | |
1605 | inode->i_op->truncate_range(inode, 0, (loff_t)-1); | |
bb6baf76 CW |
1606 | |
1607 | obj_priv->madv = __I915_MADV_PURGED; | |
963b4836 CW |
1608 | } |
1609 | ||
1610 | static inline int | |
1611 | i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj_priv) | |
1612 | { | |
1613 | return obj_priv->madv == I915_MADV_DONTNEED; | |
1614 | } | |
1615 | ||
673a394b EA |
1616 | static void |
1617 | i915_gem_object_move_to_inactive(struct drm_gem_object *obj) | |
1618 | { | |
1619 | struct drm_device *dev = obj->dev; | |
1620 | drm_i915_private_t *dev_priv = dev->dev_private; | |
23010e43 | 1621 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
673a394b | 1622 | |
673a394b | 1623 | if (obj_priv->pin_count != 0) |
f13d3f73 | 1624 | list_move_tail(&obj_priv->list, &dev_priv->mm.pinned_list); |
673a394b EA |
1625 | else |
1626 | list_move_tail(&obj_priv->list, &dev_priv->mm.inactive_list); | |
1627 | ||
99fcb766 DV |
1628 | BUG_ON(!list_empty(&obj_priv->gpu_write_list)); |
1629 | ||
ce44b0ea | 1630 | obj_priv->last_rendering_seqno = 0; |
852835f3 | 1631 | obj_priv->ring = NULL; |
673a394b EA |
1632 | if (obj_priv->active) { |
1633 | obj_priv->active = 0; | |
1634 | drm_gem_object_unreference(obj); | |
1635 | } | |
23bc5982 | 1636 | WARN_ON(i915_verify_lists(dev)); |
673a394b EA |
1637 | } |
1638 | ||
9220434a | 1639 | static void |
63560396 | 1640 | i915_gem_process_flushing_list(struct drm_device *dev, |
8a1a49f9 | 1641 | uint32_t flush_domains, |
852835f3 | 1642 | struct intel_ring_buffer *ring) |
63560396 DV |
1643 | { |
1644 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1645 | struct drm_i915_gem_object *obj_priv, *next; | |
1646 | ||
1647 | list_for_each_entry_safe(obj_priv, next, | |
1648 | &dev_priv->mm.gpu_write_list, | |
1649 | gpu_write_list) { | |
a8089e84 | 1650 | struct drm_gem_object *obj = &obj_priv->base; |
63560396 | 1651 | |
2b6efaa4 CW |
1652 | if (obj->write_domain & flush_domains && |
1653 | obj_priv->ring == ring) { | |
63560396 DV |
1654 | uint32_t old_write_domain = obj->write_domain; |
1655 | ||
1656 | obj->write_domain = 0; | |
1657 | list_del_init(&obj_priv->gpu_write_list); | |
617dbe27 | 1658 | i915_gem_object_move_to_active(obj, ring); |
63560396 DV |
1659 | |
1660 | /* update the fence lru list */ | |
007cc8ac DV |
1661 | if (obj_priv->fence_reg != I915_FENCE_REG_NONE) { |
1662 | struct drm_i915_fence_reg *reg = | |
1663 | &dev_priv->fence_regs[obj_priv->fence_reg]; | |
1664 | list_move_tail(®->lru_list, | |
63560396 | 1665 | &dev_priv->mm.fence_list); |
007cc8ac | 1666 | } |
63560396 DV |
1667 | |
1668 | trace_i915_gem_object_change_domain(obj, | |
1669 | obj->read_domains, | |
1670 | old_write_domain); | |
1671 | } | |
1672 | } | |
1673 | } | |
8187a2b7 | 1674 | |
5a5a0c64 | 1675 | uint32_t |
8a1a49f9 | 1676 | i915_add_request(struct drm_device *dev, |
f787a5f5 | 1677 | struct drm_file *file, |
8dc5d147 | 1678 | struct drm_i915_gem_request *request, |
8a1a49f9 | 1679 | struct intel_ring_buffer *ring) |
673a394b EA |
1680 | { |
1681 | drm_i915_private_t *dev_priv = dev->dev_private; | |
f787a5f5 | 1682 | struct drm_i915_file_private *file_priv = NULL; |
673a394b EA |
1683 | uint32_t seqno; |
1684 | int was_empty; | |
673a394b | 1685 | |
f787a5f5 CW |
1686 | if (file != NULL) |
1687 | file_priv = file->driver_priv; | |
b962442e | 1688 | |
8dc5d147 CW |
1689 | if (request == NULL) { |
1690 | request = kzalloc(sizeof(*request), GFP_KERNEL); | |
1691 | if (request == NULL) | |
1692 | return 0; | |
1693 | } | |
673a394b | 1694 | |
f787a5f5 | 1695 | seqno = ring->add_request(dev, ring, 0); |
a56ba56c | 1696 | ring->outstanding_lazy_request = false; |
673a394b EA |
1697 | |
1698 | request->seqno = seqno; | |
852835f3 | 1699 | request->ring = ring; |
673a394b | 1700 | request->emitted_jiffies = jiffies; |
852835f3 ZN |
1701 | was_empty = list_empty(&ring->request_list); |
1702 | list_add_tail(&request->list, &ring->request_list); | |
1703 | ||
f787a5f5 | 1704 | if (file_priv) { |
1c25595f | 1705 | spin_lock(&file_priv->mm.lock); |
f787a5f5 | 1706 | request->file_priv = file_priv; |
b962442e | 1707 | list_add_tail(&request->client_list, |
f787a5f5 | 1708 | &file_priv->mm.request_list); |
1c25595f | 1709 | spin_unlock(&file_priv->mm.lock); |
b962442e | 1710 | } |
673a394b | 1711 | |
f65d9421 | 1712 | if (!dev_priv->mm.suspended) { |
b3b079db CW |
1713 | mod_timer(&dev_priv->hangcheck_timer, |
1714 | jiffies + msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)); | |
f65d9421 | 1715 | if (was_empty) |
b3b079db CW |
1716 | queue_delayed_work(dev_priv->wq, |
1717 | &dev_priv->mm.retire_work, HZ); | |
f65d9421 | 1718 | } |
673a394b EA |
1719 | return seqno; |
1720 | } | |
1721 | ||
1722 | /** | |
1723 | * Command execution barrier | |
1724 | * | |
1725 | * Ensures that all commands in the ring are finished | |
1726 | * before signalling the CPU | |
1727 | */ | |
8a1a49f9 | 1728 | static void |
852835f3 | 1729 | i915_retire_commands(struct drm_device *dev, struct intel_ring_buffer *ring) |
673a394b | 1730 | { |
673a394b | 1731 | uint32_t flush_domains = 0; |
673a394b EA |
1732 | |
1733 | /* The sampler always gets flushed on i965 (sigh) */ | |
a6c45cf0 | 1734 | if (INTEL_INFO(dev)->gen >= 4) |
673a394b | 1735 | flush_domains |= I915_GEM_DOMAIN_SAMPLER; |
852835f3 ZN |
1736 | |
1737 | ring->flush(dev, ring, | |
1738 | I915_GEM_DOMAIN_COMMAND, flush_domains); | |
673a394b EA |
1739 | } |
1740 | ||
f787a5f5 CW |
1741 | static inline void |
1742 | i915_gem_request_remove_from_client(struct drm_i915_gem_request *request) | |
673a394b | 1743 | { |
1c25595f CW |
1744 | struct drm_i915_file_private *file_priv = request->file_priv; |
1745 | ||
1746 | if (!file_priv) | |
1747 | return; | |
1748 | ||
1749 | spin_lock(&file_priv->mm.lock); | |
1750 | list_del(&request->client_list); | |
1751 | request->file_priv = NULL; | |
1752 | spin_unlock(&file_priv->mm.lock); | |
673a394b EA |
1753 | } |
1754 | ||
dfaae392 CW |
1755 | static void i915_gem_reset_ring_lists(struct drm_i915_private *dev_priv, |
1756 | struct intel_ring_buffer *ring) | |
9375e446 | 1757 | { |
dfaae392 CW |
1758 | while (!list_empty(&ring->request_list)) { |
1759 | struct drm_i915_gem_request *request; | |
9375e446 | 1760 | |
dfaae392 CW |
1761 | request = list_first_entry(&ring->request_list, |
1762 | struct drm_i915_gem_request, | |
1763 | list); | |
1764 | ||
1765 | list_del(&request->list); | |
f787a5f5 | 1766 | i915_gem_request_remove_from_client(request); |
dfaae392 CW |
1767 | kfree(request); |
1768 | } | |
1769 | ||
1770 | while (!list_empty(&ring->active_list)) { | |
9375e446 CW |
1771 | struct drm_i915_gem_object *obj_priv; |
1772 | ||
dfaae392 | 1773 | obj_priv = list_first_entry(&ring->active_list, |
9375e446 CW |
1774 | struct drm_i915_gem_object, |
1775 | list); | |
1776 | ||
1777 | obj_priv->base.write_domain = 0; | |
dfaae392 | 1778 | list_del_init(&obj_priv->gpu_write_list); |
9375e446 CW |
1779 | i915_gem_object_move_to_inactive(&obj_priv->base); |
1780 | } | |
1781 | } | |
1782 | ||
dfaae392 | 1783 | void i915_gem_reset_lists(struct drm_device *dev) |
77f01230 CW |
1784 | { |
1785 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1786 | struct drm_i915_gem_object *obj_priv; | |
1787 | ||
dfaae392 CW |
1788 | i915_gem_reset_ring_lists(dev_priv, &dev_priv->render_ring); |
1789 | if (HAS_BSD(dev)) | |
1790 | i915_gem_reset_ring_lists(dev_priv, &dev_priv->bsd_ring); | |
1791 | ||
1792 | /* Remove anything from the flushing lists. The GPU cache is likely | |
1793 | * to be lost on reset along with the data, so simply move the | |
1794 | * lost bo to the inactive list. | |
1795 | */ | |
1796 | while (!list_empty(&dev_priv->mm.flushing_list)) { | |
1797 | obj_priv = list_first_entry(&dev_priv->mm.flushing_list, | |
1798 | struct drm_i915_gem_object, | |
1799 | list); | |
1800 | ||
1801 | obj_priv->base.write_domain = 0; | |
1802 | list_del_init(&obj_priv->gpu_write_list); | |
1803 | i915_gem_object_move_to_inactive(&obj_priv->base); | |
1804 | } | |
1805 | ||
1806 | /* Move everything out of the GPU domains to ensure we do any | |
1807 | * necessary invalidation upon reuse. | |
1808 | */ | |
77f01230 CW |
1809 | list_for_each_entry(obj_priv, |
1810 | &dev_priv->mm.inactive_list, | |
1811 | list) | |
1812 | { | |
1813 | obj_priv->base.read_domains &= ~I915_GEM_GPU_DOMAINS; | |
1814 | } | |
1815 | } | |
1816 | ||
673a394b EA |
1817 | /** |
1818 | * This function clears the request list as sequence numbers are passed. | |
1819 | */ | |
b09a1fec CW |
1820 | static void |
1821 | i915_gem_retire_requests_ring(struct drm_device *dev, | |
1822 | struct intel_ring_buffer *ring) | |
673a394b EA |
1823 | { |
1824 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1825 | uint32_t seqno; | |
1826 | ||
b84d5f0c CW |
1827 | if (!ring->status_page.page_addr || |
1828 | list_empty(&ring->request_list)) | |
6c0594a3 KW |
1829 | return; |
1830 | ||
23bc5982 CW |
1831 | WARN_ON(i915_verify_lists(dev)); |
1832 | ||
f787a5f5 | 1833 | seqno = ring->get_seqno(dev, ring); |
852835f3 | 1834 | while (!list_empty(&ring->request_list)) { |
673a394b | 1835 | struct drm_i915_gem_request *request; |
673a394b | 1836 | |
852835f3 | 1837 | request = list_first_entry(&ring->request_list, |
673a394b EA |
1838 | struct drm_i915_gem_request, |
1839 | list); | |
673a394b | 1840 | |
dfaae392 | 1841 | if (!i915_seqno_passed(seqno, request->seqno)) |
b84d5f0c CW |
1842 | break; |
1843 | ||
1844 | trace_i915_gem_request_retire(dev, request->seqno); | |
1845 | ||
1846 | list_del(&request->list); | |
f787a5f5 | 1847 | i915_gem_request_remove_from_client(request); |
b84d5f0c CW |
1848 | kfree(request); |
1849 | } | |
1850 | ||
1851 | /* Move any buffers on the active list that are no longer referenced | |
1852 | * by the ringbuffer to the flushing/inactive lists as appropriate. | |
1853 | */ | |
1854 | while (!list_empty(&ring->active_list)) { | |
1855 | struct drm_gem_object *obj; | |
1856 | struct drm_i915_gem_object *obj_priv; | |
1857 | ||
1858 | obj_priv = list_first_entry(&ring->active_list, | |
1859 | struct drm_i915_gem_object, | |
1860 | list); | |
673a394b | 1861 | |
dfaae392 | 1862 | if (!i915_seqno_passed(seqno, obj_priv->last_rendering_seqno)) |
673a394b | 1863 | break; |
b84d5f0c CW |
1864 | |
1865 | obj = &obj_priv->base; | |
b84d5f0c CW |
1866 | if (obj->write_domain != 0) |
1867 | i915_gem_object_move_to_flushing(obj); | |
1868 | else | |
1869 | i915_gem_object_move_to_inactive(obj); | |
673a394b | 1870 | } |
9d34e5db CW |
1871 | |
1872 | if (unlikely (dev_priv->trace_irq_seqno && | |
1873 | i915_seqno_passed(dev_priv->trace_irq_seqno, seqno))) { | |
8187a2b7 | 1874 | ring->user_irq_put(dev, ring); |
9d34e5db CW |
1875 | dev_priv->trace_irq_seqno = 0; |
1876 | } | |
23bc5982 CW |
1877 | |
1878 | WARN_ON(i915_verify_lists(dev)); | |
673a394b EA |
1879 | } |
1880 | ||
b09a1fec CW |
1881 | void |
1882 | i915_gem_retire_requests(struct drm_device *dev) | |
1883 | { | |
1884 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1885 | ||
be72615b CW |
1886 | if (!list_empty(&dev_priv->mm.deferred_free_list)) { |
1887 | struct drm_i915_gem_object *obj_priv, *tmp; | |
1888 | ||
1889 | /* We must be careful that during unbind() we do not | |
1890 | * accidentally infinitely recurse into retire requests. | |
1891 | * Currently: | |
1892 | * retire -> free -> unbind -> wait -> retire_ring | |
1893 | */ | |
1894 | list_for_each_entry_safe(obj_priv, tmp, | |
1895 | &dev_priv->mm.deferred_free_list, | |
1896 | list) | |
1897 | i915_gem_free_object_tail(&obj_priv->base); | |
1898 | } | |
1899 | ||
b09a1fec CW |
1900 | i915_gem_retire_requests_ring(dev, &dev_priv->render_ring); |
1901 | if (HAS_BSD(dev)) | |
1902 | i915_gem_retire_requests_ring(dev, &dev_priv->bsd_ring); | |
1903 | } | |
1904 | ||
75ef9da2 | 1905 | static void |
673a394b EA |
1906 | i915_gem_retire_work_handler(struct work_struct *work) |
1907 | { | |
1908 | drm_i915_private_t *dev_priv; | |
1909 | struct drm_device *dev; | |
1910 | ||
1911 | dev_priv = container_of(work, drm_i915_private_t, | |
1912 | mm.retire_work.work); | |
1913 | dev = dev_priv->dev; | |
1914 | ||
891b48cf CW |
1915 | /* Come back later if the device is busy... */ |
1916 | if (!mutex_trylock(&dev->struct_mutex)) { | |
1917 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ); | |
1918 | return; | |
1919 | } | |
1920 | ||
b09a1fec | 1921 | i915_gem_retire_requests(dev); |
d1b851fc | 1922 | |
6dbe2772 | 1923 | if (!dev_priv->mm.suspended && |
d1b851fc ZN |
1924 | (!list_empty(&dev_priv->render_ring.request_list) || |
1925 | (HAS_BSD(dev) && | |
1926 | !list_empty(&dev_priv->bsd_ring.request_list)))) | |
9c9fe1f8 | 1927 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ); |
673a394b EA |
1928 | mutex_unlock(&dev->struct_mutex); |
1929 | } | |
1930 | ||
5a5a0c64 | 1931 | int |
852835f3 | 1932 | i915_do_wait_request(struct drm_device *dev, uint32_t seqno, |
8a1a49f9 | 1933 | bool interruptible, struct intel_ring_buffer *ring) |
673a394b EA |
1934 | { |
1935 | drm_i915_private_t *dev_priv = dev->dev_private; | |
802c7eb6 | 1936 | u32 ier; |
673a394b EA |
1937 | int ret = 0; |
1938 | ||
1939 | BUG_ON(seqno == 0); | |
1940 | ||
30dbf0c0 CW |
1941 | if (atomic_read(&dev_priv->mm.wedged)) |
1942 | return -EAGAIN; | |
1943 | ||
a56ba56c | 1944 | if (ring->outstanding_lazy_request) { |
8dc5d147 | 1945 | seqno = i915_add_request(dev, NULL, NULL, ring); |
e35a41de DV |
1946 | if (seqno == 0) |
1947 | return -ENOMEM; | |
1948 | } | |
a56ba56c | 1949 | BUG_ON(seqno == dev_priv->next_seqno); |
e35a41de | 1950 | |
f787a5f5 | 1951 | if (!i915_seqno_passed(ring->get_seqno(dev, ring), seqno)) { |
bad720ff | 1952 | if (HAS_PCH_SPLIT(dev)) |
036a4a7d ZW |
1953 | ier = I915_READ(DEIER) | I915_READ(GTIER); |
1954 | else | |
1955 | ier = I915_READ(IER); | |
802c7eb6 JB |
1956 | if (!ier) { |
1957 | DRM_ERROR("something (likely vbetool) disabled " | |
1958 | "interrupts, re-enabling\n"); | |
1959 | i915_driver_irq_preinstall(dev); | |
1960 | i915_driver_irq_postinstall(dev); | |
1961 | } | |
1962 | ||
1c5d22f7 CW |
1963 | trace_i915_gem_request_wait_begin(dev, seqno); |
1964 | ||
852835f3 | 1965 | ring->waiting_gem_seqno = seqno; |
8187a2b7 | 1966 | ring->user_irq_get(dev, ring); |
48764bf4 | 1967 | if (interruptible) |
852835f3 ZN |
1968 | ret = wait_event_interruptible(ring->irq_queue, |
1969 | i915_seqno_passed( | |
f787a5f5 | 1970 | ring->get_seqno(dev, ring), seqno) |
852835f3 | 1971 | || atomic_read(&dev_priv->mm.wedged)); |
48764bf4 | 1972 | else |
852835f3 ZN |
1973 | wait_event(ring->irq_queue, |
1974 | i915_seqno_passed( | |
f787a5f5 | 1975 | ring->get_seqno(dev, ring), seqno) |
852835f3 | 1976 | || atomic_read(&dev_priv->mm.wedged)); |
48764bf4 | 1977 | |
8187a2b7 | 1978 | ring->user_irq_put(dev, ring); |
852835f3 | 1979 | ring->waiting_gem_seqno = 0; |
1c5d22f7 CW |
1980 | |
1981 | trace_i915_gem_request_wait_end(dev, seqno); | |
673a394b | 1982 | } |
ba1234d1 | 1983 | if (atomic_read(&dev_priv->mm.wedged)) |
30dbf0c0 | 1984 | ret = -EAGAIN; |
673a394b EA |
1985 | |
1986 | if (ret && ret != -ERESTARTSYS) | |
8bff917c | 1987 | DRM_ERROR("%s returns %d (awaiting %d at %d, next %d)\n", |
f787a5f5 | 1988 | __func__, ret, seqno, ring->get_seqno(dev, ring), |
8bff917c | 1989 | dev_priv->next_seqno); |
673a394b EA |
1990 | |
1991 | /* Directly dispatch request retiring. While we have the work queue | |
1992 | * to handle this, the waiter on a request often wants an associated | |
1993 | * buffer to have made it to the inactive list, and we would need | |
1994 | * a separate wait queue to handle that. | |
1995 | */ | |
1996 | if (ret == 0) | |
b09a1fec | 1997 | i915_gem_retire_requests_ring(dev, ring); |
673a394b EA |
1998 | |
1999 | return ret; | |
2000 | } | |
2001 | ||
48764bf4 DV |
2002 | /** |
2003 | * Waits for a sequence number to be signaled, and cleans up the | |
2004 | * request and object lists appropriately for that event. | |
2005 | */ | |
2006 | static int | |
852835f3 | 2007 | i915_wait_request(struct drm_device *dev, uint32_t seqno, |
a56ba56c | 2008 | struct intel_ring_buffer *ring) |
48764bf4 | 2009 | { |
852835f3 | 2010 | return i915_do_wait_request(dev, seqno, 1, ring); |
48764bf4 DV |
2011 | } |
2012 | ||
20f0cd55 | 2013 | static void |
9220434a | 2014 | i915_gem_flush_ring(struct drm_device *dev, |
c78ec30b | 2015 | struct drm_file *file_priv, |
9220434a CW |
2016 | struct intel_ring_buffer *ring, |
2017 | uint32_t invalidate_domains, | |
2018 | uint32_t flush_domains) | |
2019 | { | |
2020 | ring->flush(dev, ring, invalidate_domains, flush_domains); | |
2021 | i915_gem_process_flushing_list(dev, flush_domains, ring); | |
2022 | } | |
2023 | ||
8187a2b7 ZN |
2024 | static void |
2025 | i915_gem_flush(struct drm_device *dev, | |
c78ec30b | 2026 | struct drm_file *file_priv, |
8187a2b7 | 2027 | uint32_t invalidate_domains, |
9220434a CW |
2028 | uint32_t flush_domains, |
2029 | uint32_t flush_rings) | |
8187a2b7 ZN |
2030 | { |
2031 | drm_i915_private_t *dev_priv = dev->dev_private; | |
8bff917c | 2032 | |
8187a2b7 ZN |
2033 | if (flush_domains & I915_GEM_DOMAIN_CPU) |
2034 | drm_agp_chipset_flush(dev); | |
8bff917c | 2035 | |
9220434a CW |
2036 | if ((flush_domains | invalidate_domains) & I915_GEM_GPU_DOMAINS) { |
2037 | if (flush_rings & RING_RENDER) | |
c78ec30b | 2038 | i915_gem_flush_ring(dev, file_priv, |
9220434a CW |
2039 | &dev_priv->render_ring, |
2040 | invalidate_domains, flush_domains); | |
2041 | if (flush_rings & RING_BSD) | |
c78ec30b | 2042 | i915_gem_flush_ring(dev, file_priv, |
9220434a CW |
2043 | &dev_priv->bsd_ring, |
2044 | invalidate_domains, flush_domains); | |
2045 | } | |
8187a2b7 ZN |
2046 | } |
2047 | ||
673a394b EA |
2048 | /** |
2049 | * Ensures that all rendering to the object has completed and the object is | |
2050 | * safe to unbind from the GTT or access from the CPU. | |
2051 | */ | |
2052 | static int | |
2cf34d7b CW |
2053 | i915_gem_object_wait_rendering(struct drm_gem_object *obj, |
2054 | bool interruptible) | |
673a394b EA |
2055 | { |
2056 | struct drm_device *dev = obj->dev; | |
23010e43 | 2057 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
673a394b EA |
2058 | int ret; |
2059 | ||
e47c68e9 EA |
2060 | /* This function only exists to support waiting for existing rendering, |
2061 | * not for emitting required flushes. | |
673a394b | 2062 | */ |
e47c68e9 | 2063 | BUG_ON((obj->write_domain & I915_GEM_GPU_DOMAINS) != 0); |
673a394b EA |
2064 | |
2065 | /* If there is rendering queued on the buffer being evicted, wait for | |
2066 | * it. | |
2067 | */ | |
2068 | if (obj_priv->active) { | |
2cf34d7b CW |
2069 | ret = i915_do_wait_request(dev, |
2070 | obj_priv->last_rendering_seqno, | |
2071 | interruptible, | |
2072 | obj_priv->ring); | |
2073 | if (ret) | |
673a394b EA |
2074 | return ret; |
2075 | } | |
2076 | ||
2077 | return 0; | |
2078 | } | |
2079 | ||
2080 | /** | |
2081 | * Unbinds an object from the GTT aperture. | |
2082 | */ | |
0f973f27 | 2083 | int |
673a394b EA |
2084 | i915_gem_object_unbind(struct drm_gem_object *obj) |
2085 | { | |
2086 | struct drm_device *dev = obj->dev; | |
23010e43 | 2087 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
673a394b EA |
2088 | int ret = 0; |
2089 | ||
673a394b EA |
2090 | if (obj_priv->gtt_space == NULL) |
2091 | return 0; | |
2092 | ||
2093 | if (obj_priv->pin_count != 0) { | |
2094 | DRM_ERROR("Attempting to unbind pinned buffer\n"); | |
2095 | return -EINVAL; | |
2096 | } | |
2097 | ||
5323fd04 EA |
2098 | /* blow away mappings if mapped through GTT */ |
2099 | i915_gem_release_mmap(obj); | |
2100 | ||
673a394b EA |
2101 | /* Move the object to the CPU domain to ensure that |
2102 | * any possible CPU writes while it's not in the GTT | |
2103 | * are flushed when we go to remap it. This will | |
2104 | * also ensure that all pending GPU writes are finished | |
2105 | * before we unbind. | |
2106 | */ | |
e47c68e9 | 2107 | ret = i915_gem_object_set_to_cpu_domain(obj, 1); |
8dc1775d | 2108 | if (ret == -ERESTARTSYS) |
673a394b | 2109 | return ret; |
8dc1775d CW |
2110 | /* Continue on if we fail due to EIO, the GPU is hung so we |
2111 | * should be safe and we need to cleanup or else we might | |
2112 | * cause memory corruption through use-after-free. | |
2113 | */ | |
673a394b | 2114 | |
96b47b65 DV |
2115 | /* release the fence reg _after_ flushing */ |
2116 | if (obj_priv->fence_reg != I915_FENCE_REG_NONE) | |
2117 | i915_gem_clear_fence_reg(obj); | |
2118 | ||
673a394b EA |
2119 | if (obj_priv->agp_mem != NULL) { |
2120 | drm_unbind_agp(obj_priv->agp_mem); | |
2121 | drm_free_agp(obj_priv->agp_mem, obj->size / PAGE_SIZE); | |
2122 | obj_priv->agp_mem = NULL; | |
2123 | } | |
2124 | ||
856fa198 | 2125 | i915_gem_object_put_pages(obj); |
a32808c0 | 2126 | BUG_ON(obj_priv->pages_refcount); |
673a394b EA |
2127 | |
2128 | if (obj_priv->gtt_space) { | |
2129 | atomic_dec(&dev->gtt_count); | |
2130 | atomic_sub(obj->size, &dev->gtt_memory); | |
2131 | ||
2132 | drm_mm_put_block(obj_priv->gtt_space); | |
2133 | obj_priv->gtt_space = NULL; | |
2134 | } | |
2135 | ||
f13d3f73 | 2136 | list_del_init(&obj_priv->list); |
673a394b | 2137 | |
963b4836 CW |
2138 | if (i915_gem_object_is_purgeable(obj_priv)) |
2139 | i915_gem_object_truncate(obj); | |
2140 | ||
1c5d22f7 CW |
2141 | trace_i915_gem_object_unbind(obj); |
2142 | ||
8dc1775d | 2143 | return ret; |
673a394b EA |
2144 | } |
2145 | ||
a56ba56c CW |
2146 | static int i915_ring_idle(struct drm_device *dev, |
2147 | struct intel_ring_buffer *ring) | |
2148 | { | |
2149 | i915_gem_flush_ring(dev, NULL, ring, | |
2150 | I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS); | |
2151 | return i915_wait_request(dev, | |
2152 | i915_gem_next_request_seqno(dev, ring), | |
2153 | ring); | |
2154 | } | |
2155 | ||
b47eb4a2 | 2156 | int |
4df2faf4 DV |
2157 | i915_gpu_idle(struct drm_device *dev) |
2158 | { | |
2159 | drm_i915_private_t *dev_priv = dev->dev_private; | |
2160 | bool lists_empty; | |
852835f3 | 2161 | int ret; |
4df2faf4 | 2162 | |
d1b851fc ZN |
2163 | lists_empty = (list_empty(&dev_priv->mm.flushing_list) && |
2164 | list_empty(&dev_priv->render_ring.active_list) && | |
2165 | (!HAS_BSD(dev) || | |
2166 | list_empty(&dev_priv->bsd_ring.active_list))); | |
4df2faf4 DV |
2167 | if (lists_empty) |
2168 | return 0; | |
2169 | ||
2170 | /* Flush everything onto the inactive list. */ | |
a56ba56c | 2171 | ret = i915_ring_idle(dev, &dev_priv->render_ring); |
8a1a49f9 DV |
2172 | if (ret) |
2173 | return ret; | |
d1b851fc ZN |
2174 | |
2175 | if (HAS_BSD(dev)) { | |
a56ba56c | 2176 | ret = i915_ring_idle(dev, &dev_priv->bsd_ring); |
d1b851fc ZN |
2177 | if (ret) |
2178 | return ret; | |
2179 | } | |
2180 | ||
8a1a49f9 | 2181 | return 0; |
4df2faf4 DV |
2182 | } |
2183 | ||
5cdf5881 | 2184 | static int |
4bdadb97 CW |
2185 | i915_gem_object_get_pages(struct drm_gem_object *obj, |
2186 | gfp_t gfpmask) | |
673a394b | 2187 | { |
23010e43 | 2188 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
673a394b EA |
2189 | int page_count, i; |
2190 | struct address_space *mapping; | |
2191 | struct inode *inode; | |
2192 | struct page *page; | |
673a394b | 2193 | |
778c3544 DV |
2194 | BUG_ON(obj_priv->pages_refcount |
2195 | == DRM_I915_GEM_OBJECT_MAX_PAGES_REFCOUNT); | |
2196 | ||
856fa198 | 2197 | if (obj_priv->pages_refcount++ != 0) |
673a394b EA |
2198 | return 0; |
2199 | ||
2200 | /* Get the list of pages out of our struct file. They'll be pinned | |
2201 | * at this point until we release them. | |
2202 | */ | |
2203 | page_count = obj->size / PAGE_SIZE; | |
856fa198 | 2204 | BUG_ON(obj_priv->pages != NULL); |
8e7d2b2c | 2205 | obj_priv->pages = drm_calloc_large(page_count, sizeof(struct page *)); |
856fa198 | 2206 | if (obj_priv->pages == NULL) { |
856fa198 | 2207 | obj_priv->pages_refcount--; |
673a394b EA |
2208 | return -ENOMEM; |
2209 | } | |
2210 | ||
2211 | inode = obj->filp->f_path.dentry->d_inode; | |
2212 | mapping = inode->i_mapping; | |
2213 | for (i = 0; i < page_count; i++) { | |
4bdadb97 | 2214 | page = read_cache_page_gfp(mapping, i, |
985b823b | 2215 | GFP_HIGHUSER | |
4bdadb97 | 2216 | __GFP_COLD | |
cd9f040d | 2217 | __GFP_RECLAIMABLE | |
4bdadb97 | 2218 | gfpmask); |
1f2b1013 CW |
2219 | if (IS_ERR(page)) |
2220 | goto err_pages; | |
2221 | ||
856fa198 | 2222 | obj_priv->pages[i] = page; |
673a394b | 2223 | } |
280b713b EA |
2224 | |
2225 | if (obj_priv->tiling_mode != I915_TILING_NONE) | |
2226 | i915_gem_object_do_bit_17_swizzle(obj); | |
2227 | ||
673a394b | 2228 | return 0; |
1f2b1013 CW |
2229 | |
2230 | err_pages: | |
2231 | while (i--) | |
2232 | page_cache_release(obj_priv->pages[i]); | |
2233 | ||
2234 | drm_free_large(obj_priv->pages); | |
2235 | obj_priv->pages = NULL; | |
2236 | obj_priv->pages_refcount--; | |
2237 | return PTR_ERR(page); | |
673a394b EA |
2238 | } |
2239 | ||
4e901fdc EA |
2240 | static void sandybridge_write_fence_reg(struct drm_i915_fence_reg *reg) |
2241 | { | |
2242 | struct drm_gem_object *obj = reg->obj; | |
2243 | struct drm_device *dev = obj->dev; | |
2244 | drm_i915_private_t *dev_priv = dev->dev_private; | |
23010e43 | 2245 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
4e901fdc EA |
2246 | int regnum = obj_priv->fence_reg; |
2247 | uint64_t val; | |
2248 | ||
2249 | val = (uint64_t)((obj_priv->gtt_offset + obj->size - 4096) & | |
2250 | 0xfffff000) << 32; | |
2251 | val |= obj_priv->gtt_offset & 0xfffff000; | |
2252 | val |= (uint64_t)((obj_priv->stride / 128) - 1) << | |
2253 | SANDYBRIDGE_FENCE_PITCH_SHIFT; | |
2254 | ||
2255 | if (obj_priv->tiling_mode == I915_TILING_Y) | |
2256 | val |= 1 << I965_FENCE_TILING_Y_SHIFT; | |
2257 | val |= I965_FENCE_REG_VALID; | |
2258 | ||
2259 | I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + (regnum * 8), val); | |
2260 | } | |
2261 | ||
de151cf6 JB |
2262 | static void i965_write_fence_reg(struct drm_i915_fence_reg *reg) |
2263 | { | |
2264 | struct drm_gem_object *obj = reg->obj; | |
2265 | struct drm_device *dev = obj->dev; | |
2266 | drm_i915_private_t *dev_priv = dev->dev_private; | |
23010e43 | 2267 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
de151cf6 JB |
2268 | int regnum = obj_priv->fence_reg; |
2269 | uint64_t val; | |
2270 | ||
2271 | val = (uint64_t)((obj_priv->gtt_offset + obj->size - 4096) & | |
2272 | 0xfffff000) << 32; | |
2273 | val |= obj_priv->gtt_offset & 0xfffff000; | |
2274 | val |= ((obj_priv->stride / 128) - 1) << I965_FENCE_PITCH_SHIFT; | |
2275 | if (obj_priv->tiling_mode == I915_TILING_Y) | |
2276 | val |= 1 << I965_FENCE_TILING_Y_SHIFT; | |
2277 | val |= I965_FENCE_REG_VALID; | |
2278 | ||
2279 | I915_WRITE64(FENCE_REG_965_0 + (regnum * 8), val); | |
2280 | } | |
2281 | ||
2282 | static void i915_write_fence_reg(struct drm_i915_fence_reg *reg) | |
2283 | { | |
2284 | struct drm_gem_object *obj = reg->obj; | |
2285 | struct drm_device *dev = obj->dev; | |
2286 | drm_i915_private_t *dev_priv = dev->dev_private; | |
23010e43 | 2287 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
de151cf6 | 2288 | int regnum = obj_priv->fence_reg; |
0f973f27 | 2289 | int tile_width; |
dc529a4f | 2290 | uint32_t fence_reg, val; |
de151cf6 JB |
2291 | uint32_t pitch_val; |
2292 | ||
2293 | if ((obj_priv->gtt_offset & ~I915_FENCE_START_MASK) || | |
2294 | (obj_priv->gtt_offset & (obj->size - 1))) { | |
f06da264 | 2295 | WARN(1, "%s: object 0x%08x not 1M or size (0x%zx) aligned\n", |
0f973f27 | 2296 | __func__, obj_priv->gtt_offset, obj->size); |
de151cf6 JB |
2297 | return; |
2298 | } | |
2299 | ||
0f973f27 JB |
2300 | if (obj_priv->tiling_mode == I915_TILING_Y && |
2301 | HAS_128_BYTE_Y_TILING(dev)) | |
2302 | tile_width = 128; | |
de151cf6 | 2303 | else |
0f973f27 JB |
2304 | tile_width = 512; |
2305 | ||
2306 | /* Note: pitch better be a power of two tile widths */ | |
2307 | pitch_val = obj_priv->stride / tile_width; | |
2308 | pitch_val = ffs(pitch_val) - 1; | |
de151cf6 | 2309 | |
c36a2a6d DV |
2310 | if (obj_priv->tiling_mode == I915_TILING_Y && |
2311 | HAS_128_BYTE_Y_TILING(dev)) | |
2312 | WARN_ON(pitch_val > I830_FENCE_MAX_PITCH_VAL); | |
2313 | else | |
2314 | WARN_ON(pitch_val > I915_FENCE_MAX_PITCH_VAL); | |
2315 | ||
de151cf6 JB |
2316 | val = obj_priv->gtt_offset; |
2317 | if (obj_priv->tiling_mode == I915_TILING_Y) | |
2318 | val |= 1 << I830_FENCE_TILING_Y_SHIFT; | |
2319 | val |= I915_FENCE_SIZE_BITS(obj->size); | |
2320 | val |= pitch_val << I830_FENCE_PITCH_SHIFT; | |
2321 | val |= I830_FENCE_REG_VALID; | |
2322 | ||
dc529a4f EA |
2323 | if (regnum < 8) |
2324 | fence_reg = FENCE_REG_830_0 + (regnum * 4); | |
2325 | else | |
2326 | fence_reg = FENCE_REG_945_8 + ((regnum - 8) * 4); | |
2327 | I915_WRITE(fence_reg, val); | |
de151cf6 JB |
2328 | } |
2329 | ||
2330 | static void i830_write_fence_reg(struct drm_i915_fence_reg *reg) | |
2331 | { | |
2332 | struct drm_gem_object *obj = reg->obj; | |
2333 | struct drm_device *dev = obj->dev; | |
2334 | drm_i915_private_t *dev_priv = dev->dev_private; | |
23010e43 | 2335 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
de151cf6 JB |
2336 | int regnum = obj_priv->fence_reg; |
2337 | uint32_t val; | |
2338 | uint32_t pitch_val; | |
8d7773a3 | 2339 | uint32_t fence_size_bits; |
de151cf6 | 2340 | |
8d7773a3 | 2341 | if ((obj_priv->gtt_offset & ~I830_FENCE_START_MASK) || |
de151cf6 | 2342 | (obj_priv->gtt_offset & (obj->size - 1))) { |
8d7773a3 | 2343 | WARN(1, "%s: object 0x%08x not 512K or size aligned\n", |
0f973f27 | 2344 | __func__, obj_priv->gtt_offset); |
de151cf6 JB |
2345 | return; |
2346 | } | |
2347 | ||
e76a16de EA |
2348 | pitch_val = obj_priv->stride / 128; |
2349 | pitch_val = ffs(pitch_val) - 1; | |
2350 | WARN_ON(pitch_val > I830_FENCE_MAX_PITCH_VAL); | |
2351 | ||
de151cf6 JB |
2352 | val = obj_priv->gtt_offset; |
2353 | if (obj_priv->tiling_mode == I915_TILING_Y) | |
2354 | val |= 1 << I830_FENCE_TILING_Y_SHIFT; | |
8d7773a3 DV |
2355 | fence_size_bits = I830_FENCE_SIZE_BITS(obj->size); |
2356 | WARN_ON(fence_size_bits & ~0x00000f00); | |
2357 | val |= fence_size_bits; | |
de151cf6 JB |
2358 | val |= pitch_val << I830_FENCE_PITCH_SHIFT; |
2359 | val |= I830_FENCE_REG_VALID; | |
2360 | ||
2361 | I915_WRITE(FENCE_REG_830_0 + (regnum * 4), val); | |
de151cf6 JB |
2362 | } |
2363 | ||
2cf34d7b CW |
2364 | static int i915_find_fence_reg(struct drm_device *dev, |
2365 | bool interruptible) | |
ae3db24a DV |
2366 | { |
2367 | struct drm_i915_fence_reg *reg = NULL; | |
2368 | struct drm_i915_gem_object *obj_priv = NULL; | |
2369 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2370 | struct drm_gem_object *obj = NULL; | |
2371 | int i, avail, ret; | |
2372 | ||
2373 | /* First try to find a free reg */ | |
2374 | avail = 0; | |
2375 | for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) { | |
2376 | reg = &dev_priv->fence_regs[i]; | |
2377 | if (!reg->obj) | |
2378 | return i; | |
2379 | ||
23010e43 | 2380 | obj_priv = to_intel_bo(reg->obj); |
ae3db24a DV |
2381 | if (!obj_priv->pin_count) |
2382 | avail++; | |
2383 | } | |
2384 | ||
2385 | if (avail == 0) | |
2386 | return -ENOSPC; | |
2387 | ||
2388 | /* None available, try to steal one or wait for a user to finish */ | |
2389 | i = I915_FENCE_REG_NONE; | |
007cc8ac DV |
2390 | list_for_each_entry(reg, &dev_priv->mm.fence_list, |
2391 | lru_list) { | |
2392 | obj = reg->obj; | |
2393 | obj_priv = to_intel_bo(obj); | |
ae3db24a DV |
2394 | |
2395 | if (obj_priv->pin_count) | |
2396 | continue; | |
2397 | ||
2398 | /* found one! */ | |
2399 | i = obj_priv->fence_reg; | |
2400 | break; | |
2401 | } | |
2402 | ||
2403 | BUG_ON(i == I915_FENCE_REG_NONE); | |
2404 | ||
2405 | /* We only have a reference on obj from the active list. put_fence_reg | |
2406 | * might drop that one, causing a use-after-free in it. So hold a | |
2407 | * private reference to obj like the other callers of put_fence_reg | |
2408 | * (set_tiling ioctl) do. */ | |
2409 | drm_gem_object_reference(obj); | |
2cf34d7b | 2410 | ret = i915_gem_object_put_fence_reg(obj, interruptible); |
ae3db24a DV |
2411 | drm_gem_object_unreference(obj); |
2412 | if (ret != 0) | |
2413 | return ret; | |
2414 | ||
2415 | return i; | |
2416 | } | |
2417 | ||
de151cf6 JB |
2418 | /** |
2419 | * i915_gem_object_get_fence_reg - set up a fence reg for an object | |
2420 | * @obj: object to map through a fence reg | |
2421 | * | |
2422 | * When mapping objects through the GTT, userspace wants to be able to write | |
2423 | * to them without having to worry about swizzling if the object is tiled. | |
2424 | * | |
2425 | * This function walks the fence regs looking for a free one for @obj, | |
2426 | * stealing one if it can't find any. | |
2427 | * | |
2428 | * It then sets up the reg based on the object's properties: address, pitch | |
2429 | * and tiling format. | |
2430 | */ | |
8c4b8c3f | 2431 | int |
2cf34d7b CW |
2432 | i915_gem_object_get_fence_reg(struct drm_gem_object *obj, |
2433 | bool interruptible) | |
de151cf6 JB |
2434 | { |
2435 | struct drm_device *dev = obj->dev; | |
79e53945 | 2436 | struct drm_i915_private *dev_priv = dev->dev_private; |
23010e43 | 2437 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
de151cf6 | 2438 | struct drm_i915_fence_reg *reg = NULL; |
ae3db24a | 2439 | int ret; |
de151cf6 | 2440 | |
a09ba7fa EA |
2441 | /* Just update our place in the LRU if our fence is getting used. */ |
2442 | if (obj_priv->fence_reg != I915_FENCE_REG_NONE) { | |
007cc8ac DV |
2443 | reg = &dev_priv->fence_regs[obj_priv->fence_reg]; |
2444 | list_move_tail(®->lru_list, &dev_priv->mm.fence_list); | |
a09ba7fa EA |
2445 | return 0; |
2446 | } | |
2447 | ||
de151cf6 JB |
2448 | switch (obj_priv->tiling_mode) { |
2449 | case I915_TILING_NONE: | |
2450 | WARN(1, "allocating a fence for non-tiled object?\n"); | |
2451 | break; | |
2452 | case I915_TILING_X: | |
0f973f27 JB |
2453 | if (!obj_priv->stride) |
2454 | return -EINVAL; | |
2455 | WARN((obj_priv->stride & (512 - 1)), | |
2456 | "object 0x%08x is X tiled but has non-512B pitch\n", | |
2457 | obj_priv->gtt_offset); | |
de151cf6 JB |
2458 | break; |
2459 | case I915_TILING_Y: | |
0f973f27 JB |
2460 | if (!obj_priv->stride) |
2461 | return -EINVAL; | |
2462 | WARN((obj_priv->stride & (128 - 1)), | |
2463 | "object 0x%08x is Y tiled but has non-128B pitch\n", | |
2464 | obj_priv->gtt_offset); | |
de151cf6 JB |
2465 | break; |
2466 | } | |
2467 | ||
2cf34d7b | 2468 | ret = i915_find_fence_reg(dev, interruptible); |
ae3db24a DV |
2469 | if (ret < 0) |
2470 | return ret; | |
de151cf6 | 2471 | |
ae3db24a DV |
2472 | obj_priv->fence_reg = ret; |
2473 | reg = &dev_priv->fence_regs[obj_priv->fence_reg]; | |
007cc8ac | 2474 | list_add_tail(®->lru_list, &dev_priv->mm.fence_list); |
a09ba7fa | 2475 | |
de151cf6 JB |
2476 | reg->obj = obj; |
2477 | ||
e259befd CW |
2478 | switch (INTEL_INFO(dev)->gen) { |
2479 | case 6: | |
4e901fdc | 2480 | sandybridge_write_fence_reg(reg); |
e259befd CW |
2481 | break; |
2482 | case 5: | |
2483 | case 4: | |
de151cf6 | 2484 | i965_write_fence_reg(reg); |
e259befd CW |
2485 | break; |
2486 | case 3: | |
de151cf6 | 2487 | i915_write_fence_reg(reg); |
e259befd CW |
2488 | break; |
2489 | case 2: | |
de151cf6 | 2490 | i830_write_fence_reg(reg); |
e259befd CW |
2491 | break; |
2492 | } | |
d9ddcb96 | 2493 | |
ae3db24a DV |
2494 | trace_i915_gem_object_get_fence(obj, obj_priv->fence_reg, |
2495 | obj_priv->tiling_mode); | |
1c5d22f7 | 2496 | |
d9ddcb96 | 2497 | return 0; |
de151cf6 JB |
2498 | } |
2499 | ||
2500 | /** | |
2501 | * i915_gem_clear_fence_reg - clear out fence register info | |
2502 | * @obj: object to clear | |
2503 | * | |
2504 | * Zeroes out the fence register itself and clears out the associated | |
2505 | * data structures in dev_priv and obj_priv. | |
2506 | */ | |
2507 | static void | |
2508 | i915_gem_clear_fence_reg(struct drm_gem_object *obj) | |
2509 | { | |
2510 | struct drm_device *dev = obj->dev; | |
79e53945 | 2511 | drm_i915_private_t *dev_priv = dev->dev_private; |
23010e43 | 2512 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
007cc8ac DV |
2513 | struct drm_i915_fence_reg *reg = |
2514 | &dev_priv->fence_regs[obj_priv->fence_reg]; | |
e259befd | 2515 | uint32_t fence_reg; |
de151cf6 | 2516 | |
e259befd CW |
2517 | switch (INTEL_INFO(dev)->gen) { |
2518 | case 6: | |
4e901fdc EA |
2519 | I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + |
2520 | (obj_priv->fence_reg * 8), 0); | |
e259befd CW |
2521 | break; |
2522 | case 5: | |
2523 | case 4: | |
de151cf6 | 2524 | I915_WRITE64(FENCE_REG_965_0 + (obj_priv->fence_reg * 8), 0); |
e259befd CW |
2525 | break; |
2526 | case 3: | |
9b74f734 | 2527 | if (obj_priv->fence_reg >= 8) |
e259befd | 2528 | fence_reg = FENCE_REG_945_8 + (obj_priv->fence_reg - 8) * 4; |
dc529a4f | 2529 | else |
e259befd CW |
2530 | case 2: |
2531 | fence_reg = FENCE_REG_830_0 + obj_priv->fence_reg * 4; | |
dc529a4f EA |
2532 | |
2533 | I915_WRITE(fence_reg, 0); | |
e259befd | 2534 | break; |
dc529a4f | 2535 | } |
de151cf6 | 2536 | |
007cc8ac | 2537 | reg->obj = NULL; |
de151cf6 | 2538 | obj_priv->fence_reg = I915_FENCE_REG_NONE; |
007cc8ac | 2539 | list_del_init(®->lru_list); |
de151cf6 JB |
2540 | } |
2541 | ||
52dc7d32 CW |
2542 | /** |
2543 | * i915_gem_object_put_fence_reg - waits on outstanding fenced access | |
2544 | * to the buffer to finish, and then resets the fence register. | |
2545 | * @obj: tiled object holding a fence register. | |
2cf34d7b | 2546 | * @bool: whether the wait upon the fence is interruptible |
52dc7d32 CW |
2547 | * |
2548 | * Zeroes out the fence register itself and clears out the associated | |
2549 | * data structures in dev_priv and obj_priv. | |
2550 | */ | |
2551 | int | |
2cf34d7b CW |
2552 | i915_gem_object_put_fence_reg(struct drm_gem_object *obj, |
2553 | bool interruptible) | |
52dc7d32 CW |
2554 | { |
2555 | struct drm_device *dev = obj->dev; | |
53640e1d | 2556 | struct drm_i915_private *dev_priv = dev->dev_private; |
23010e43 | 2557 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
53640e1d | 2558 | struct drm_i915_fence_reg *reg; |
52dc7d32 CW |
2559 | |
2560 | if (obj_priv->fence_reg == I915_FENCE_REG_NONE) | |
2561 | return 0; | |
2562 | ||
10ae9bd2 DV |
2563 | /* If we've changed tiling, GTT-mappings of the object |
2564 | * need to re-fault to ensure that the correct fence register | |
2565 | * setup is in place. | |
2566 | */ | |
2567 | i915_gem_release_mmap(obj); | |
2568 | ||
52dc7d32 CW |
2569 | /* On the i915, GPU access to tiled buffers is via a fence, |
2570 | * therefore we must wait for any outstanding access to complete | |
2571 | * before clearing the fence. | |
2572 | */ | |
53640e1d CW |
2573 | reg = &dev_priv->fence_regs[obj_priv->fence_reg]; |
2574 | if (reg->gpu) { | |
52dc7d32 CW |
2575 | int ret; |
2576 | ||
2cf34d7b | 2577 | ret = i915_gem_object_flush_gpu_write_domain(obj, true); |
0bc23aad CW |
2578 | if (ret) |
2579 | return ret; | |
2580 | ||
2cf34d7b | 2581 | ret = i915_gem_object_wait_rendering(obj, interruptible); |
0bc23aad | 2582 | if (ret) |
52dc7d32 | 2583 | return ret; |
53640e1d CW |
2584 | |
2585 | reg->gpu = false; | |
52dc7d32 CW |
2586 | } |
2587 | ||
4a726612 | 2588 | i915_gem_object_flush_gtt_write_domain(obj); |
0bc23aad | 2589 | i915_gem_clear_fence_reg(obj); |
52dc7d32 CW |
2590 | |
2591 | return 0; | |
2592 | } | |
2593 | ||
673a394b EA |
2594 | /** |
2595 | * Finds free space in the GTT aperture and binds the object there. | |
2596 | */ | |
2597 | static int | |
2598 | i915_gem_object_bind_to_gtt(struct drm_gem_object *obj, unsigned alignment) | |
2599 | { | |
2600 | struct drm_device *dev = obj->dev; | |
2601 | drm_i915_private_t *dev_priv = dev->dev_private; | |
23010e43 | 2602 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
673a394b | 2603 | struct drm_mm_node *free_space; |
4bdadb97 | 2604 | gfp_t gfpmask = __GFP_NORETRY | __GFP_NOWARN; |
07f73f69 | 2605 | int ret; |
673a394b | 2606 | |
bb6baf76 | 2607 | if (obj_priv->madv != I915_MADV_WILLNEED) { |
3ef94daa CW |
2608 | DRM_ERROR("Attempting to bind a purgeable object\n"); |
2609 | return -EINVAL; | |
2610 | } | |
2611 | ||
673a394b | 2612 | if (alignment == 0) |
0f973f27 | 2613 | alignment = i915_gem_get_gtt_alignment(obj); |
8d7773a3 | 2614 | if (alignment & (i915_gem_get_gtt_alignment(obj) - 1)) { |
673a394b EA |
2615 | DRM_ERROR("Invalid object alignment requested %u\n", alignment); |
2616 | return -EINVAL; | |
2617 | } | |
2618 | ||
654fc607 CW |
2619 | /* If the object is bigger than the entire aperture, reject it early |
2620 | * before evicting everything in a vain attempt to find space. | |
2621 | */ | |
2622 | if (obj->size > dev->gtt_total) { | |
2623 | DRM_ERROR("Attempting to bind an object larger than the aperture\n"); | |
2624 | return -E2BIG; | |
2625 | } | |
2626 | ||
673a394b EA |
2627 | search_free: |
2628 | free_space = drm_mm_search_free(&dev_priv->mm.gtt_space, | |
2629 | obj->size, alignment, 0); | |
2630 | if (free_space != NULL) { | |
2631 | obj_priv->gtt_space = drm_mm_get_block(free_space, obj->size, | |
2632 | alignment); | |
db3307a9 | 2633 | if (obj_priv->gtt_space != NULL) |
673a394b | 2634 | obj_priv->gtt_offset = obj_priv->gtt_space->start; |
673a394b EA |
2635 | } |
2636 | if (obj_priv->gtt_space == NULL) { | |
2637 | /* If the gtt is empty and we're still having trouble | |
2638 | * fitting our object in, we're out of memory. | |
2639 | */ | |
0108a3ed | 2640 | ret = i915_gem_evict_something(dev, obj->size, alignment); |
9731129c | 2641 | if (ret) |
673a394b | 2642 | return ret; |
9731129c | 2643 | |
673a394b EA |
2644 | goto search_free; |
2645 | } | |
2646 | ||
4bdadb97 | 2647 | ret = i915_gem_object_get_pages(obj, gfpmask); |
673a394b EA |
2648 | if (ret) { |
2649 | drm_mm_put_block(obj_priv->gtt_space); | |
2650 | obj_priv->gtt_space = NULL; | |
07f73f69 CW |
2651 | |
2652 | if (ret == -ENOMEM) { | |
2653 | /* first try to clear up some space from the GTT */ | |
0108a3ed DV |
2654 | ret = i915_gem_evict_something(dev, obj->size, |
2655 | alignment); | |
07f73f69 | 2656 | if (ret) { |
07f73f69 | 2657 | /* now try to shrink everyone else */ |
4bdadb97 CW |
2658 | if (gfpmask) { |
2659 | gfpmask = 0; | |
2660 | goto search_free; | |
07f73f69 CW |
2661 | } |
2662 | ||
2663 | return ret; | |
2664 | } | |
2665 | ||
2666 | goto search_free; | |
2667 | } | |
2668 | ||
673a394b EA |
2669 | return ret; |
2670 | } | |
2671 | ||
673a394b EA |
2672 | /* Create an AGP memory structure pointing at our pages, and bind it |
2673 | * into the GTT. | |
2674 | */ | |
2675 | obj_priv->agp_mem = drm_agp_bind_pages(dev, | |
856fa198 | 2676 | obj_priv->pages, |
07f73f69 | 2677 | obj->size >> PAGE_SHIFT, |
ba1eb1d8 KP |
2678 | obj_priv->gtt_offset, |
2679 | obj_priv->agp_type); | |
673a394b | 2680 | if (obj_priv->agp_mem == NULL) { |
856fa198 | 2681 | i915_gem_object_put_pages(obj); |
673a394b EA |
2682 | drm_mm_put_block(obj_priv->gtt_space); |
2683 | obj_priv->gtt_space = NULL; | |
07f73f69 | 2684 | |
0108a3ed | 2685 | ret = i915_gem_evict_something(dev, obj->size, alignment); |
9731129c | 2686 | if (ret) |
07f73f69 | 2687 | return ret; |
07f73f69 CW |
2688 | |
2689 | goto search_free; | |
673a394b EA |
2690 | } |
2691 | atomic_inc(&dev->gtt_count); | |
2692 | atomic_add(obj->size, &dev->gtt_memory); | |
2693 | ||
bf1a1092 CW |
2694 | /* keep track of bounds object by adding it to the inactive list */ |
2695 | list_add_tail(&obj_priv->list, &dev_priv->mm.inactive_list); | |
2696 | ||
673a394b EA |
2697 | /* Assert that the object is not currently in any GPU domain. As it |
2698 | * wasn't in the GTT, there shouldn't be any way it could have been in | |
2699 | * a GPU cache | |
2700 | */ | |
21d509e3 CW |
2701 | BUG_ON(obj->read_domains & I915_GEM_GPU_DOMAINS); |
2702 | BUG_ON(obj->write_domain & I915_GEM_GPU_DOMAINS); | |
673a394b | 2703 | |
1c5d22f7 CW |
2704 | trace_i915_gem_object_bind(obj, obj_priv->gtt_offset); |
2705 | ||
673a394b EA |
2706 | return 0; |
2707 | } | |
2708 | ||
2709 | void | |
2710 | i915_gem_clflush_object(struct drm_gem_object *obj) | |
2711 | { | |
23010e43 | 2712 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
673a394b EA |
2713 | |
2714 | /* If we don't have a page list set up, then we're not pinned | |
2715 | * to GPU, and we can ignore the cache flush because it'll happen | |
2716 | * again at bind time. | |
2717 | */ | |
856fa198 | 2718 | if (obj_priv->pages == NULL) |
673a394b EA |
2719 | return; |
2720 | ||
1c5d22f7 | 2721 | trace_i915_gem_object_clflush(obj); |
cfa16a0d | 2722 | |
856fa198 | 2723 | drm_clflush_pages(obj_priv->pages, obj->size / PAGE_SIZE); |
673a394b EA |
2724 | } |
2725 | ||
e47c68e9 | 2726 | /** Flushes any GPU write domain for the object if it's dirty. */ |
2dafb1e0 | 2727 | static int |
ba3d8d74 DV |
2728 | i915_gem_object_flush_gpu_write_domain(struct drm_gem_object *obj, |
2729 | bool pipelined) | |
e47c68e9 EA |
2730 | { |
2731 | struct drm_device *dev = obj->dev; | |
1c5d22f7 | 2732 | uint32_t old_write_domain; |
e47c68e9 EA |
2733 | |
2734 | if ((obj->write_domain & I915_GEM_GPU_DOMAINS) == 0) | |
2dafb1e0 | 2735 | return 0; |
e47c68e9 EA |
2736 | |
2737 | /* Queue the GPU write cache flushing we need. */ | |
1c5d22f7 | 2738 | old_write_domain = obj->write_domain; |
c78ec30b | 2739 | i915_gem_flush_ring(dev, NULL, |
9220434a CW |
2740 | to_intel_bo(obj)->ring, |
2741 | 0, obj->write_domain); | |
48b956c5 | 2742 | BUG_ON(obj->write_domain); |
1c5d22f7 CW |
2743 | |
2744 | trace_i915_gem_object_change_domain(obj, | |
2745 | obj->read_domains, | |
2746 | old_write_domain); | |
ba3d8d74 DV |
2747 | |
2748 | if (pipelined) | |
2749 | return 0; | |
2750 | ||
2cf34d7b | 2751 | return i915_gem_object_wait_rendering(obj, true); |
e47c68e9 EA |
2752 | } |
2753 | ||
2754 | /** Flushes the GTT write domain for the object if it's dirty. */ | |
2755 | static void | |
2756 | i915_gem_object_flush_gtt_write_domain(struct drm_gem_object *obj) | |
2757 | { | |
1c5d22f7 CW |
2758 | uint32_t old_write_domain; |
2759 | ||
e47c68e9 EA |
2760 | if (obj->write_domain != I915_GEM_DOMAIN_GTT) |
2761 | return; | |
2762 | ||
2763 | /* No actual flushing is required for the GTT write domain. Writes | |
2764 | * to it immediately go to main memory as far as we know, so there's | |
2765 | * no chipset flush. It also doesn't land in render cache. | |
2766 | */ | |
1c5d22f7 | 2767 | old_write_domain = obj->write_domain; |
e47c68e9 | 2768 | obj->write_domain = 0; |
1c5d22f7 CW |
2769 | |
2770 | trace_i915_gem_object_change_domain(obj, | |
2771 | obj->read_domains, | |
2772 | old_write_domain); | |
e47c68e9 EA |
2773 | } |
2774 | ||
2775 | /** Flushes the CPU write domain for the object if it's dirty. */ | |
2776 | static void | |
2777 | i915_gem_object_flush_cpu_write_domain(struct drm_gem_object *obj) | |
2778 | { | |
2779 | struct drm_device *dev = obj->dev; | |
1c5d22f7 | 2780 | uint32_t old_write_domain; |
e47c68e9 EA |
2781 | |
2782 | if (obj->write_domain != I915_GEM_DOMAIN_CPU) | |
2783 | return; | |
2784 | ||
2785 | i915_gem_clflush_object(obj); | |
2786 | drm_agp_chipset_flush(dev); | |
1c5d22f7 | 2787 | old_write_domain = obj->write_domain; |
e47c68e9 | 2788 | obj->write_domain = 0; |
1c5d22f7 CW |
2789 | |
2790 | trace_i915_gem_object_change_domain(obj, | |
2791 | obj->read_domains, | |
2792 | old_write_domain); | |
e47c68e9 EA |
2793 | } |
2794 | ||
2ef7eeaa EA |
2795 | /** |
2796 | * Moves a single object to the GTT read, and possibly write domain. | |
2797 | * | |
2798 | * This function returns when the move is complete, including waiting on | |
2799 | * flushes to occur. | |
2800 | */ | |
79e53945 | 2801 | int |
2ef7eeaa EA |
2802 | i915_gem_object_set_to_gtt_domain(struct drm_gem_object *obj, int write) |
2803 | { | |
23010e43 | 2804 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
1c5d22f7 | 2805 | uint32_t old_write_domain, old_read_domains; |
e47c68e9 | 2806 | int ret; |
2ef7eeaa | 2807 | |
02354392 EA |
2808 | /* Not valid to be called on unbound objects. */ |
2809 | if (obj_priv->gtt_space == NULL) | |
2810 | return -EINVAL; | |
2811 | ||
ba3d8d74 | 2812 | ret = i915_gem_object_flush_gpu_write_domain(obj, false); |
e47c68e9 EA |
2813 | if (ret != 0) |
2814 | return ret; | |
2815 | ||
7213342d | 2816 | i915_gem_object_flush_cpu_write_domain(obj); |
1c5d22f7 | 2817 | |
ba3d8d74 | 2818 | if (write) { |
2cf34d7b | 2819 | ret = i915_gem_object_wait_rendering(obj, true); |
ba3d8d74 DV |
2820 | if (ret) |
2821 | return ret; | |
ba3d8d74 | 2822 | } |
2ef7eeaa | 2823 | |
7213342d CW |
2824 | old_write_domain = obj->write_domain; |
2825 | old_read_domains = obj->read_domains; | |
2ef7eeaa | 2826 | |
e47c68e9 EA |
2827 | /* It should now be out of any other write domains, and we can update |
2828 | * the domain values for our changes. | |
2829 | */ | |
2830 | BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_GTT) != 0); | |
2831 | obj->read_domains |= I915_GEM_DOMAIN_GTT; | |
2832 | if (write) { | |
7213342d | 2833 | obj->read_domains = I915_GEM_DOMAIN_GTT; |
e47c68e9 EA |
2834 | obj->write_domain = I915_GEM_DOMAIN_GTT; |
2835 | obj_priv->dirty = 1; | |
2ef7eeaa EA |
2836 | } |
2837 | ||
1c5d22f7 CW |
2838 | trace_i915_gem_object_change_domain(obj, |
2839 | old_read_domains, | |
2840 | old_write_domain); | |
2841 | ||
e47c68e9 EA |
2842 | return 0; |
2843 | } | |
2844 | ||
b9241ea3 ZW |
2845 | /* |
2846 | * Prepare buffer for display plane. Use uninterruptible for possible flush | |
2847 | * wait, as in modesetting process we're not supposed to be interrupted. | |
2848 | */ | |
2849 | int | |
48b956c5 CW |
2850 | i915_gem_object_set_to_display_plane(struct drm_gem_object *obj, |
2851 | bool pipelined) | |
b9241ea3 | 2852 | { |
23010e43 | 2853 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
ba3d8d74 | 2854 | uint32_t old_read_domains; |
b9241ea3 ZW |
2855 | int ret; |
2856 | ||
2857 | /* Not valid to be called on unbound objects. */ | |
2858 | if (obj_priv->gtt_space == NULL) | |
2859 | return -EINVAL; | |
2860 | ||
ced270fa | 2861 | ret = i915_gem_object_flush_gpu_write_domain(obj, true); |
48b956c5 | 2862 | if (ret) |
e35a41de | 2863 | return ret; |
b9241ea3 | 2864 | |
ced270fa CW |
2865 | /* Currently, we are always called from an non-interruptible context. */ |
2866 | if (!pipelined) { | |
2867 | ret = i915_gem_object_wait_rendering(obj, false); | |
2868 | if (ret) | |
2869 | return ret; | |
2870 | } | |
2871 | ||
b118c1e3 CW |
2872 | i915_gem_object_flush_cpu_write_domain(obj); |
2873 | ||
b9241ea3 | 2874 | old_read_domains = obj->read_domains; |
c78ec30b | 2875 | obj->read_domains |= I915_GEM_DOMAIN_GTT; |
b9241ea3 ZW |
2876 | |
2877 | trace_i915_gem_object_change_domain(obj, | |
2878 | old_read_domains, | |
ba3d8d74 | 2879 | obj->write_domain); |
b9241ea3 ZW |
2880 | |
2881 | return 0; | |
2882 | } | |
2883 | ||
e47c68e9 EA |
2884 | /** |
2885 | * Moves a single object to the CPU read, and possibly write domain. | |
2886 | * | |
2887 | * This function returns when the move is complete, including waiting on | |
2888 | * flushes to occur. | |
2889 | */ | |
2890 | static int | |
2891 | i915_gem_object_set_to_cpu_domain(struct drm_gem_object *obj, int write) | |
2892 | { | |
1c5d22f7 | 2893 | uint32_t old_write_domain, old_read_domains; |
e47c68e9 EA |
2894 | int ret; |
2895 | ||
ba3d8d74 | 2896 | ret = i915_gem_object_flush_gpu_write_domain(obj, false); |
e47c68e9 EA |
2897 | if (ret != 0) |
2898 | return ret; | |
2ef7eeaa | 2899 | |
e47c68e9 | 2900 | i915_gem_object_flush_gtt_write_domain(obj); |
2ef7eeaa | 2901 | |
e47c68e9 EA |
2902 | /* If we have a partially-valid cache of the object in the CPU, |
2903 | * finish invalidating it and free the per-page flags. | |
2ef7eeaa | 2904 | */ |
e47c68e9 | 2905 | i915_gem_object_set_to_full_cpu_read_domain(obj); |
2ef7eeaa | 2906 | |
7213342d | 2907 | if (write) { |
2cf34d7b | 2908 | ret = i915_gem_object_wait_rendering(obj, true); |
7213342d CW |
2909 | if (ret) |
2910 | return ret; | |
2911 | } | |
2912 | ||
1c5d22f7 CW |
2913 | old_write_domain = obj->write_domain; |
2914 | old_read_domains = obj->read_domains; | |
2915 | ||
e47c68e9 EA |
2916 | /* Flush the CPU cache if it's still invalid. */ |
2917 | if ((obj->read_domains & I915_GEM_DOMAIN_CPU) == 0) { | |
2ef7eeaa | 2918 | i915_gem_clflush_object(obj); |
2ef7eeaa | 2919 | |
e47c68e9 | 2920 | obj->read_domains |= I915_GEM_DOMAIN_CPU; |
2ef7eeaa EA |
2921 | } |
2922 | ||
2923 | /* It should now be out of any other write domains, and we can update | |
2924 | * the domain values for our changes. | |
2925 | */ | |
e47c68e9 EA |
2926 | BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_CPU) != 0); |
2927 | ||
2928 | /* If we're writing through the CPU, then the GPU read domains will | |
2929 | * need to be invalidated at next use. | |
2930 | */ | |
2931 | if (write) { | |
c78ec30b | 2932 | obj->read_domains = I915_GEM_DOMAIN_CPU; |
e47c68e9 EA |
2933 | obj->write_domain = I915_GEM_DOMAIN_CPU; |
2934 | } | |
2ef7eeaa | 2935 | |
1c5d22f7 CW |
2936 | trace_i915_gem_object_change_domain(obj, |
2937 | old_read_domains, | |
2938 | old_write_domain); | |
2939 | ||
2ef7eeaa EA |
2940 | return 0; |
2941 | } | |
2942 | ||
673a394b EA |
2943 | /* |
2944 | * Set the next domain for the specified object. This | |
2945 | * may not actually perform the necessary flushing/invaliding though, | |
2946 | * as that may want to be batched with other set_domain operations | |
2947 | * | |
2948 | * This is (we hope) the only really tricky part of gem. The goal | |
2949 | * is fairly simple -- track which caches hold bits of the object | |
2950 | * and make sure they remain coherent. A few concrete examples may | |
2951 | * help to explain how it works. For shorthand, we use the notation | |
2952 | * (read_domains, write_domain), e.g. (CPU, CPU) to indicate the | |
2953 | * a pair of read and write domain masks. | |
2954 | * | |
2955 | * Case 1: the batch buffer | |
2956 | * | |
2957 | * 1. Allocated | |
2958 | * 2. Written by CPU | |
2959 | * 3. Mapped to GTT | |
2960 | * 4. Read by GPU | |
2961 | * 5. Unmapped from GTT | |
2962 | * 6. Freed | |
2963 | * | |
2964 | * Let's take these a step at a time | |
2965 | * | |
2966 | * 1. Allocated | |
2967 | * Pages allocated from the kernel may still have | |
2968 | * cache contents, so we set them to (CPU, CPU) always. | |
2969 | * 2. Written by CPU (using pwrite) | |
2970 | * The pwrite function calls set_domain (CPU, CPU) and | |
2971 | * this function does nothing (as nothing changes) | |
2972 | * 3. Mapped by GTT | |
2973 | * This function asserts that the object is not | |
2974 | * currently in any GPU-based read or write domains | |
2975 | * 4. Read by GPU | |
2976 | * i915_gem_execbuffer calls set_domain (COMMAND, 0). | |
2977 | * As write_domain is zero, this function adds in the | |
2978 | * current read domains (CPU+COMMAND, 0). | |
2979 | * flush_domains is set to CPU. | |
2980 | * invalidate_domains is set to COMMAND | |
2981 | * clflush is run to get data out of the CPU caches | |
2982 | * then i915_dev_set_domain calls i915_gem_flush to | |
2983 | * emit an MI_FLUSH and drm_agp_chipset_flush | |
2984 | * 5. Unmapped from GTT | |
2985 | * i915_gem_object_unbind calls set_domain (CPU, CPU) | |
2986 | * flush_domains and invalidate_domains end up both zero | |
2987 | * so no flushing/invalidating happens | |
2988 | * 6. Freed | |
2989 | * yay, done | |
2990 | * | |
2991 | * Case 2: The shared render buffer | |
2992 | * | |
2993 | * 1. Allocated | |
2994 | * 2. Mapped to GTT | |
2995 | * 3. Read/written by GPU | |
2996 | * 4. set_domain to (CPU,CPU) | |
2997 | * 5. Read/written by CPU | |
2998 | * 6. Read/written by GPU | |
2999 | * | |
3000 | * 1. Allocated | |
3001 | * Same as last example, (CPU, CPU) | |
3002 | * 2. Mapped to GTT | |
3003 | * Nothing changes (assertions find that it is not in the GPU) | |
3004 | * 3. Read/written by GPU | |
3005 | * execbuffer calls set_domain (RENDER, RENDER) | |
3006 | * flush_domains gets CPU | |
3007 | * invalidate_domains gets GPU | |
3008 | * clflush (obj) | |
3009 | * MI_FLUSH and drm_agp_chipset_flush | |
3010 | * 4. set_domain (CPU, CPU) | |
3011 | * flush_domains gets GPU | |
3012 | * invalidate_domains gets CPU | |
3013 | * wait_rendering (obj) to make sure all drawing is complete. | |
3014 | * This will include an MI_FLUSH to get the data from GPU | |
3015 | * to memory | |
3016 | * clflush (obj) to invalidate the CPU cache | |
3017 | * Another MI_FLUSH in i915_gem_flush (eliminate this somehow?) | |
3018 | * 5. Read/written by CPU | |
3019 | * cache lines are loaded and dirtied | |
3020 | * 6. Read written by GPU | |
3021 | * Same as last GPU access | |
3022 | * | |
3023 | * Case 3: The constant buffer | |
3024 | * | |
3025 | * 1. Allocated | |
3026 | * 2. Written by CPU | |
3027 | * 3. Read by GPU | |
3028 | * 4. Updated (written) by CPU again | |
3029 | * 5. Read by GPU | |
3030 | * | |
3031 | * 1. Allocated | |
3032 | * (CPU, CPU) | |
3033 | * 2. Written by CPU | |
3034 | * (CPU, CPU) | |
3035 | * 3. Read by GPU | |
3036 | * (CPU+RENDER, 0) | |
3037 | * flush_domains = CPU | |
3038 | * invalidate_domains = RENDER | |
3039 | * clflush (obj) | |
3040 | * MI_FLUSH | |
3041 | * drm_agp_chipset_flush | |
3042 | * 4. Updated (written) by CPU again | |
3043 | * (CPU, CPU) | |
3044 | * flush_domains = 0 (no previous write domain) | |
3045 | * invalidate_domains = 0 (no new read domains) | |
3046 | * 5. Read by GPU | |
3047 | * (CPU+RENDER, 0) | |
3048 | * flush_domains = CPU | |
3049 | * invalidate_domains = RENDER | |
3050 | * clflush (obj) | |
3051 | * MI_FLUSH | |
3052 | * drm_agp_chipset_flush | |
3053 | */ | |
c0d90829 | 3054 | static void |
8b0e378a | 3055 | i915_gem_object_set_to_gpu_domain(struct drm_gem_object *obj) |
673a394b EA |
3056 | { |
3057 | struct drm_device *dev = obj->dev; | |
9220434a | 3058 | struct drm_i915_private *dev_priv = dev->dev_private; |
23010e43 | 3059 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
673a394b EA |
3060 | uint32_t invalidate_domains = 0; |
3061 | uint32_t flush_domains = 0; | |
1c5d22f7 | 3062 | uint32_t old_read_domains; |
e47c68e9 | 3063 | |
8b0e378a EA |
3064 | BUG_ON(obj->pending_read_domains & I915_GEM_DOMAIN_CPU); |
3065 | BUG_ON(obj->pending_write_domain == I915_GEM_DOMAIN_CPU); | |
673a394b | 3066 | |
652c393a JB |
3067 | intel_mark_busy(dev, obj); |
3068 | ||
673a394b EA |
3069 | /* |
3070 | * If the object isn't moving to a new write domain, | |
3071 | * let the object stay in multiple read domains | |
3072 | */ | |
8b0e378a EA |
3073 | if (obj->pending_write_domain == 0) |
3074 | obj->pending_read_domains |= obj->read_domains; | |
673a394b EA |
3075 | else |
3076 | obj_priv->dirty = 1; | |
3077 | ||
3078 | /* | |
3079 | * Flush the current write domain if | |
3080 | * the new read domains don't match. Invalidate | |
3081 | * any read domains which differ from the old | |
3082 | * write domain | |
3083 | */ | |
8b0e378a EA |
3084 | if (obj->write_domain && |
3085 | obj->write_domain != obj->pending_read_domains) { | |
673a394b | 3086 | flush_domains |= obj->write_domain; |
8b0e378a EA |
3087 | invalidate_domains |= |
3088 | obj->pending_read_domains & ~obj->write_domain; | |
673a394b EA |
3089 | } |
3090 | /* | |
3091 | * Invalidate any read caches which may have | |
3092 | * stale data. That is, any new read domains. | |
3093 | */ | |
8b0e378a | 3094 | invalidate_domains |= obj->pending_read_domains & ~obj->read_domains; |
3d2a812a | 3095 | if ((flush_domains | invalidate_domains) & I915_GEM_DOMAIN_CPU) |
673a394b | 3096 | i915_gem_clflush_object(obj); |
673a394b | 3097 | |
1c5d22f7 CW |
3098 | old_read_domains = obj->read_domains; |
3099 | ||
efbeed96 EA |
3100 | /* The actual obj->write_domain will be updated with |
3101 | * pending_write_domain after we emit the accumulated flush for all | |
3102 | * of our domain changes in execbuffers (which clears objects' | |
3103 | * write_domains). So if we have a current write domain that we | |
3104 | * aren't changing, set pending_write_domain to that. | |
3105 | */ | |
3106 | if (flush_domains == 0 && obj->pending_write_domain == 0) | |
3107 | obj->pending_write_domain = obj->write_domain; | |
8b0e378a | 3108 | obj->read_domains = obj->pending_read_domains; |
673a394b EA |
3109 | |
3110 | dev->invalidate_domains |= invalidate_domains; | |
3111 | dev->flush_domains |= flush_domains; | |
9220434a CW |
3112 | if (obj_priv->ring) |
3113 | dev_priv->mm.flush_rings |= obj_priv->ring->id; | |
1c5d22f7 CW |
3114 | |
3115 | trace_i915_gem_object_change_domain(obj, | |
3116 | old_read_domains, | |
3117 | obj->write_domain); | |
673a394b EA |
3118 | } |
3119 | ||
3120 | /** | |
e47c68e9 | 3121 | * Moves the object from a partially CPU read to a full one. |
673a394b | 3122 | * |
e47c68e9 EA |
3123 | * Note that this only resolves i915_gem_object_set_cpu_read_domain_range(), |
3124 | * and doesn't handle transitioning from !(read_domains & I915_GEM_DOMAIN_CPU). | |
673a394b | 3125 | */ |
e47c68e9 EA |
3126 | static void |
3127 | i915_gem_object_set_to_full_cpu_read_domain(struct drm_gem_object *obj) | |
673a394b | 3128 | { |
23010e43 | 3129 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
673a394b | 3130 | |
e47c68e9 EA |
3131 | if (!obj_priv->page_cpu_valid) |
3132 | return; | |
3133 | ||
3134 | /* If we're partially in the CPU read domain, finish moving it in. | |
3135 | */ | |
3136 | if (obj->read_domains & I915_GEM_DOMAIN_CPU) { | |
3137 | int i; | |
3138 | ||
3139 | for (i = 0; i <= (obj->size - 1) / PAGE_SIZE; i++) { | |
3140 | if (obj_priv->page_cpu_valid[i]) | |
3141 | continue; | |
856fa198 | 3142 | drm_clflush_pages(obj_priv->pages + i, 1); |
e47c68e9 | 3143 | } |
e47c68e9 EA |
3144 | } |
3145 | ||
3146 | /* Free the page_cpu_valid mappings which are now stale, whether | |
3147 | * or not we've got I915_GEM_DOMAIN_CPU. | |
3148 | */ | |
9a298b2a | 3149 | kfree(obj_priv->page_cpu_valid); |
e47c68e9 EA |
3150 | obj_priv->page_cpu_valid = NULL; |
3151 | } | |
3152 | ||
3153 | /** | |
3154 | * Set the CPU read domain on a range of the object. | |
3155 | * | |
3156 | * The object ends up with I915_GEM_DOMAIN_CPU in its read flags although it's | |
3157 | * not entirely valid. The page_cpu_valid member of the object flags which | |
3158 | * pages have been flushed, and will be respected by | |
3159 | * i915_gem_object_set_to_cpu_domain() if it's called on to get a valid mapping | |
3160 | * of the whole object. | |
3161 | * | |
3162 | * This function returns when the move is complete, including waiting on | |
3163 | * flushes to occur. | |
3164 | */ | |
3165 | static int | |
3166 | i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object *obj, | |
3167 | uint64_t offset, uint64_t size) | |
3168 | { | |
23010e43 | 3169 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
1c5d22f7 | 3170 | uint32_t old_read_domains; |
e47c68e9 | 3171 | int i, ret; |
673a394b | 3172 | |
e47c68e9 EA |
3173 | if (offset == 0 && size == obj->size) |
3174 | return i915_gem_object_set_to_cpu_domain(obj, 0); | |
673a394b | 3175 | |
ba3d8d74 | 3176 | ret = i915_gem_object_flush_gpu_write_domain(obj, false); |
e47c68e9 | 3177 | if (ret != 0) |
6a47baa6 | 3178 | return ret; |
e47c68e9 EA |
3179 | i915_gem_object_flush_gtt_write_domain(obj); |
3180 | ||
3181 | /* If we're already fully in the CPU read domain, we're done. */ | |
3182 | if (obj_priv->page_cpu_valid == NULL && | |
3183 | (obj->read_domains & I915_GEM_DOMAIN_CPU) != 0) | |
3184 | return 0; | |
673a394b | 3185 | |
e47c68e9 EA |
3186 | /* Otherwise, create/clear the per-page CPU read domain flag if we're |
3187 | * newly adding I915_GEM_DOMAIN_CPU | |
3188 | */ | |
673a394b | 3189 | if (obj_priv->page_cpu_valid == NULL) { |
9a298b2a EA |
3190 | obj_priv->page_cpu_valid = kzalloc(obj->size / PAGE_SIZE, |
3191 | GFP_KERNEL); | |
e47c68e9 EA |
3192 | if (obj_priv->page_cpu_valid == NULL) |
3193 | return -ENOMEM; | |
3194 | } else if ((obj->read_domains & I915_GEM_DOMAIN_CPU) == 0) | |
3195 | memset(obj_priv->page_cpu_valid, 0, obj->size / PAGE_SIZE); | |
673a394b EA |
3196 | |
3197 | /* Flush the cache on any pages that are still invalid from the CPU's | |
3198 | * perspective. | |
3199 | */ | |
e47c68e9 EA |
3200 | for (i = offset / PAGE_SIZE; i <= (offset + size - 1) / PAGE_SIZE; |
3201 | i++) { | |
673a394b EA |
3202 | if (obj_priv->page_cpu_valid[i]) |
3203 | continue; | |
3204 | ||
856fa198 | 3205 | drm_clflush_pages(obj_priv->pages + i, 1); |
673a394b EA |
3206 | |
3207 | obj_priv->page_cpu_valid[i] = 1; | |
3208 | } | |
3209 | ||
e47c68e9 EA |
3210 | /* It should now be out of any other write domains, and we can update |
3211 | * the domain values for our changes. | |
3212 | */ | |
3213 | BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_CPU) != 0); | |
3214 | ||
1c5d22f7 | 3215 | old_read_domains = obj->read_domains; |
e47c68e9 EA |
3216 | obj->read_domains |= I915_GEM_DOMAIN_CPU; |
3217 | ||
1c5d22f7 CW |
3218 | trace_i915_gem_object_change_domain(obj, |
3219 | old_read_domains, | |
3220 | obj->write_domain); | |
3221 | ||
673a394b EA |
3222 | return 0; |
3223 | } | |
3224 | ||
673a394b EA |
3225 | /** |
3226 | * Pin an object to the GTT and evaluate the relocations landing in it. | |
3227 | */ | |
3228 | static int | |
3229 | i915_gem_object_pin_and_relocate(struct drm_gem_object *obj, | |
3230 | struct drm_file *file_priv, | |
76446cac | 3231 | struct drm_i915_gem_exec_object2 *entry, |
40a5f0de | 3232 | struct drm_i915_gem_relocation_entry *relocs) |
673a394b EA |
3233 | { |
3234 | struct drm_device *dev = obj->dev; | |
0839ccb8 | 3235 | drm_i915_private_t *dev_priv = dev->dev_private; |
23010e43 | 3236 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
673a394b | 3237 | int i, ret; |
0839ccb8 | 3238 | void __iomem *reloc_page; |
76446cac JB |
3239 | bool need_fence; |
3240 | ||
3241 | need_fence = entry->flags & EXEC_OBJECT_NEEDS_FENCE && | |
3242 | obj_priv->tiling_mode != I915_TILING_NONE; | |
3243 | ||
3244 | /* Check fence reg constraints and rebind if necessary */ | |
808b24d6 CW |
3245 | if (need_fence && |
3246 | !i915_gem_object_fence_offset_ok(obj, | |
3247 | obj_priv->tiling_mode)) { | |
3248 | ret = i915_gem_object_unbind(obj); | |
3249 | if (ret) | |
3250 | return ret; | |
3251 | } | |
673a394b EA |
3252 | |
3253 | /* Choose the GTT offset for our buffer and put it there. */ | |
3254 | ret = i915_gem_object_pin(obj, (uint32_t) entry->alignment); | |
3255 | if (ret) | |
3256 | return ret; | |
3257 | ||
76446cac JB |
3258 | /* |
3259 | * Pre-965 chips need a fence register set up in order to | |
3260 | * properly handle blits to/from tiled surfaces. | |
3261 | */ | |
3262 | if (need_fence) { | |
53640e1d | 3263 | ret = i915_gem_object_get_fence_reg(obj, true); |
76446cac | 3264 | if (ret != 0) { |
76446cac JB |
3265 | i915_gem_object_unpin(obj); |
3266 | return ret; | |
3267 | } | |
53640e1d CW |
3268 | |
3269 | dev_priv->fence_regs[obj_priv->fence_reg].gpu = true; | |
76446cac JB |
3270 | } |
3271 | ||
673a394b EA |
3272 | entry->offset = obj_priv->gtt_offset; |
3273 | ||
673a394b EA |
3274 | /* Apply the relocations, using the GTT aperture to avoid cache |
3275 | * flushing requirements. | |
3276 | */ | |
3277 | for (i = 0; i < entry->relocation_count; i++) { | |
40a5f0de | 3278 | struct drm_i915_gem_relocation_entry *reloc= &relocs[i]; |
673a394b EA |
3279 | struct drm_gem_object *target_obj; |
3280 | struct drm_i915_gem_object *target_obj_priv; | |
3043c60c EA |
3281 | uint32_t reloc_val, reloc_offset; |
3282 | uint32_t __iomem *reloc_entry; | |
673a394b | 3283 | |
673a394b | 3284 | target_obj = drm_gem_object_lookup(obj->dev, file_priv, |
40a5f0de | 3285 | reloc->target_handle); |
673a394b EA |
3286 | if (target_obj == NULL) { |
3287 | i915_gem_object_unpin(obj); | |
bf79cb91 | 3288 | return -ENOENT; |
673a394b | 3289 | } |
23010e43 | 3290 | target_obj_priv = to_intel_bo(target_obj); |
673a394b | 3291 | |
8542a0bb CW |
3292 | #if WATCH_RELOC |
3293 | DRM_INFO("%s: obj %p offset %08x target %d " | |
3294 | "read %08x write %08x gtt %08x " | |
3295 | "presumed %08x delta %08x\n", | |
3296 | __func__, | |
3297 | obj, | |
3298 | (int) reloc->offset, | |
3299 | (int) reloc->target_handle, | |
3300 | (int) reloc->read_domains, | |
3301 | (int) reloc->write_domain, | |
3302 | (int) target_obj_priv->gtt_offset, | |
3303 | (int) reloc->presumed_offset, | |
3304 | reloc->delta); | |
3305 | #endif | |
3306 | ||
673a394b EA |
3307 | /* The target buffer should have appeared before us in the |
3308 | * exec_object list, so it should have a GTT space bound by now. | |
3309 | */ | |
3310 | if (target_obj_priv->gtt_space == NULL) { | |
3311 | DRM_ERROR("No GTT space found for object %d\n", | |
40a5f0de | 3312 | reloc->target_handle); |
673a394b EA |
3313 | drm_gem_object_unreference(target_obj); |
3314 | i915_gem_object_unpin(obj); | |
3315 | return -EINVAL; | |
3316 | } | |
3317 | ||
8542a0bb | 3318 | /* Validate that the target is in a valid r/w GPU domain */ |
16edd550 DV |
3319 | if (reloc->write_domain & (reloc->write_domain - 1)) { |
3320 | DRM_ERROR("reloc with multiple write domains: " | |
3321 | "obj %p target %d offset %d " | |
3322 | "read %08x write %08x", | |
3323 | obj, reloc->target_handle, | |
3324 | (int) reloc->offset, | |
3325 | reloc->read_domains, | |
3326 | reloc->write_domain); | |
3327 | return -EINVAL; | |
3328 | } | |
40a5f0de EA |
3329 | if (reloc->write_domain & I915_GEM_DOMAIN_CPU || |
3330 | reloc->read_domains & I915_GEM_DOMAIN_CPU) { | |
e47c68e9 EA |
3331 | DRM_ERROR("reloc with read/write CPU domains: " |
3332 | "obj %p target %d offset %d " | |
3333 | "read %08x write %08x", | |
40a5f0de EA |
3334 | obj, reloc->target_handle, |
3335 | (int) reloc->offset, | |
3336 | reloc->read_domains, | |
3337 | reloc->write_domain); | |
491152b8 CW |
3338 | drm_gem_object_unreference(target_obj); |
3339 | i915_gem_object_unpin(obj); | |
e47c68e9 EA |
3340 | return -EINVAL; |
3341 | } | |
40a5f0de EA |
3342 | if (reloc->write_domain && target_obj->pending_write_domain && |
3343 | reloc->write_domain != target_obj->pending_write_domain) { | |
673a394b EA |
3344 | DRM_ERROR("Write domain conflict: " |
3345 | "obj %p target %d offset %d " | |
3346 | "new %08x old %08x\n", | |
40a5f0de EA |
3347 | obj, reloc->target_handle, |
3348 | (int) reloc->offset, | |
3349 | reloc->write_domain, | |
673a394b EA |
3350 | target_obj->pending_write_domain); |
3351 | drm_gem_object_unreference(target_obj); | |
3352 | i915_gem_object_unpin(obj); | |
3353 | return -EINVAL; | |
3354 | } | |
3355 | ||
40a5f0de EA |
3356 | target_obj->pending_read_domains |= reloc->read_domains; |
3357 | target_obj->pending_write_domain |= reloc->write_domain; | |
673a394b EA |
3358 | |
3359 | /* If the relocation already has the right value in it, no | |
3360 | * more work needs to be done. | |
3361 | */ | |
40a5f0de | 3362 | if (target_obj_priv->gtt_offset == reloc->presumed_offset) { |
673a394b EA |
3363 | drm_gem_object_unreference(target_obj); |
3364 | continue; | |
3365 | } | |
3366 | ||
8542a0bb CW |
3367 | /* Check that the relocation address is valid... */ |
3368 | if (reloc->offset > obj->size - 4) { | |
3369 | DRM_ERROR("Relocation beyond object bounds: " | |
3370 | "obj %p target %d offset %d size %d.\n", | |
3371 | obj, reloc->target_handle, | |
3372 | (int) reloc->offset, (int) obj->size); | |
3373 | drm_gem_object_unreference(target_obj); | |
3374 | i915_gem_object_unpin(obj); | |
3375 | return -EINVAL; | |
3376 | } | |
3377 | if (reloc->offset & 3) { | |
3378 | DRM_ERROR("Relocation not 4-byte aligned: " | |
3379 | "obj %p target %d offset %d.\n", | |
3380 | obj, reloc->target_handle, | |
3381 | (int) reloc->offset); | |
3382 | drm_gem_object_unreference(target_obj); | |
3383 | i915_gem_object_unpin(obj); | |
3384 | return -EINVAL; | |
3385 | } | |
3386 | ||
3387 | /* and points to somewhere within the target object. */ | |
3388 | if (reloc->delta >= target_obj->size) { | |
3389 | DRM_ERROR("Relocation beyond target object bounds: " | |
3390 | "obj %p target %d delta %d size %d.\n", | |
3391 | obj, reloc->target_handle, | |
3392 | (int) reloc->delta, (int) target_obj->size); | |
3393 | drm_gem_object_unreference(target_obj); | |
3394 | i915_gem_object_unpin(obj); | |
3395 | return -EINVAL; | |
3396 | } | |
3397 | ||
2ef7eeaa EA |
3398 | ret = i915_gem_object_set_to_gtt_domain(obj, 1); |
3399 | if (ret != 0) { | |
3400 | drm_gem_object_unreference(target_obj); | |
3401 | i915_gem_object_unpin(obj); | |
3402 | return -EINVAL; | |
673a394b EA |
3403 | } |
3404 | ||
3405 | /* Map the page containing the relocation we're going to | |
3406 | * perform. | |
3407 | */ | |
40a5f0de | 3408 | reloc_offset = obj_priv->gtt_offset + reloc->offset; |
0839ccb8 KP |
3409 | reloc_page = io_mapping_map_atomic_wc(dev_priv->mm.gtt_mapping, |
3410 | (reloc_offset & | |
fca3ec01 CW |
3411 | ~(PAGE_SIZE - 1)), |
3412 | KM_USER0); | |
3043c60c | 3413 | reloc_entry = (uint32_t __iomem *)(reloc_page + |
0839ccb8 | 3414 | (reloc_offset & (PAGE_SIZE - 1))); |
40a5f0de | 3415 | reloc_val = target_obj_priv->gtt_offset + reloc->delta; |
673a394b | 3416 | |
673a394b | 3417 | writel(reloc_val, reloc_entry); |
fca3ec01 | 3418 | io_mapping_unmap_atomic(reloc_page, KM_USER0); |
673a394b | 3419 | |
40a5f0de EA |
3420 | /* The updated presumed offset for this entry will be |
3421 | * copied back out to the user. | |
673a394b | 3422 | */ |
40a5f0de | 3423 | reloc->presumed_offset = target_obj_priv->gtt_offset; |
673a394b EA |
3424 | |
3425 | drm_gem_object_unreference(target_obj); | |
3426 | } | |
3427 | ||
673a394b EA |
3428 | return 0; |
3429 | } | |
3430 | ||
673a394b EA |
3431 | /* Throttle our rendering by waiting until the ring has completed our requests |
3432 | * emitted over 20 msec ago. | |
3433 | * | |
b962442e EA |
3434 | * Note that if we were to use the current jiffies each time around the loop, |
3435 | * we wouldn't escape the function with any frames outstanding if the time to | |
3436 | * render a frame was over 20ms. | |
3437 | * | |
673a394b EA |
3438 | * This should get us reasonable parallelism between CPU and GPU but also |
3439 | * relatively low latency when blocking on a particular request to finish. | |
3440 | */ | |
3441 | static int | |
f787a5f5 | 3442 | i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file) |
673a394b | 3443 | { |
f787a5f5 CW |
3444 | struct drm_i915_private *dev_priv = dev->dev_private; |
3445 | struct drm_i915_file_private *file_priv = file->driver_priv; | |
b962442e | 3446 | unsigned long recent_enough = jiffies - msecs_to_jiffies(20); |
f787a5f5 CW |
3447 | struct drm_i915_gem_request *request; |
3448 | struct intel_ring_buffer *ring = NULL; | |
3449 | u32 seqno = 0; | |
3450 | int ret; | |
673a394b | 3451 | |
1c25595f | 3452 | spin_lock(&file_priv->mm.lock); |
f787a5f5 | 3453 | list_for_each_entry(request, &file_priv->mm.request_list, client_list) { |
b962442e EA |
3454 | if (time_after_eq(request->emitted_jiffies, recent_enough)) |
3455 | break; | |
3456 | ||
f787a5f5 CW |
3457 | ring = request->ring; |
3458 | seqno = request->seqno; | |
b962442e | 3459 | } |
1c25595f | 3460 | spin_unlock(&file_priv->mm.lock); |
f787a5f5 CW |
3461 | |
3462 | if (seqno == 0) | |
3463 | return 0; | |
3464 | ||
3465 | ret = 0; | |
3466 | if (!i915_seqno_passed(ring->get_seqno(dev, ring), seqno)) { | |
3467 | /* And wait for the seqno passing without holding any locks and | |
3468 | * causing extra latency for others. This is safe as the irq | |
3469 | * generation is designed to be run atomically and so is | |
3470 | * lockless. | |
3471 | */ | |
3472 | ring->user_irq_get(dev, ring); | |
3473 | ret = wait_event_interruptible(ring->irq_queue, | |
3474 | i915_seqno_passed(ring->get_seqno(dev, ring), seqno) | |
3475 | || atomic_read(&dev_priv->mm.wedged)); | |
3476 | ring->user_irq_put(dev, ring); | |
3477 | ||
3478 | if (ret == 0 && atomic_read(&dev_priv->mm.wedged)) | |
3479 | ret = -EIO; | |
3480 | } | |
3481 | ||
3482 | if (ret == 0) | |
3483 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, 0); | |
b962442e | 3484 | |
673a394b EA |
3485 | return ret; |
3486 | } | |
3487 | ||
40a5f0de | 3488 | static int |
76446cac | 3489 | i915_gem_get_relocs_from_user(struct drm_i915_gem_exec_object2 *exec_list, |
40a5f0de EA |
3490 | uint32_t buffer_count, |
3491 | struct drm_i915_gem_relocation_entry **relocs) | |
3492 | { | |
3493 | uint32_t reloc_count = 0, reloc_index = 0, i; | |
3494 | int ret; | |
3495 | ||
3496 | *relocs = NULL; | |
3497 | for (i = 0; i < buffer_count; i++) { | |
3498 | if (reloc_count + exec_list[i].relocation_count < reloc_count) | |
3499 | return -EINVAL; | |
3500 | reloc_count += exec_list[i].relocation_count; | |
3501 | } | |
3502 | ||
8e7d2b2c | 3503 | *relocs = drm_calloc_large(reloc_count, sizeof(**relocs)); |
76446cac JB |
3504 | if (*relocs == NULL) { |
3505 | DRM_ERROR("failed to alloc relocs, count %d\n", reloc_count); | |
40a5f0de | 3506 | return -ENOMEM; |
76446cac | 3507 | } |
40a5f0de EA |
3508 | |
3509 | for (i = 0; i < buffer_count; i++) { | |
3510 | struct drm_i915_gem_relocation_entry __user *user_relocs; | |
3511 | ||
3512 | user_relocs = (void __user *)(uintptr_t)exec_list[i].relocs_ptr; | |
3513 | ||
3514 | ret = copy_from_user(&(*relocs)[reloc_index], | |
3515 | user_relocs, | |
3516 | exec_list[i].relocation_count * | |
3517 | sizeof(**relocs)); | |
3518 | if (ret != 0) { | |
8e7d2b2c | 3519 | drm_free_large(*relocs); |
40a5f0de | 3520 | *relocs = NULL; |
2bc43b5c | 3521 | return -EFAULT; |
40a5f0de EA |
3522 | } |
3523 | ||
3524 | reloc_index += exec_list[i].relocation_count; | |
3525 | } | |
3526 | ||
2bc43b5c | 3527 | return 0; |
40a5f0de EA |
3528 | } |
3529 | ||
3530 | static int | |
76446cac | 3531 | i915_gem_put_relocs_to_user(struct drm_i915_gem_exec_object2 *exec_list, |
40a5f0de EA |
3532 | uint32_t buffer_count, |
3533 | struct drm_i915_gem_relocation_entry *relocs) | |
3534 | { | |
3535 | uint32_t reloc_count = 0, i; | |
2bc43b5c | 3536 | int ret = 0; |
40a5f0de | 3537 | |
93533c29 CW |
3538 | if (relocs == NULL) |
3539 | return 0; | |
3540 | ||
40a5f0de EA |
3541 | for (i = 0; i < buffer_count; i++) { |
3542 | struct drm_i915_gem_relocation_entry __user *user_relocs; | |
2bc43b5c | 3543 | int unwritten; |
40a5f0de EA |
3544 | |
3545 | user_relocs = (void __user *)(uintptr_t)exec_list[i].relocs_ptr; | |
3546 | ||
2bc43b5c FM |
3547 | unwritten = copy_to_user(user_relocs, |
3548 | &relocs[reloc_count], | |
3549 | exec_list[i].relocation_count * | |
3550 | sizeof(*relocs)); | |
3551 | ||
3552 | if (unwritten) { | |
3553 | ret = -EFAULT; | |
3554 | goto err; | |
40a5f0de EA |
3555 | } |
3556 | ||
3557 | reloc_count += exec_list[i].relocation_count; | |
3558 | } | |
3559 | ||
2bc43b5c | 3560 | err: |
8e7d2b2c | 3561 | drm_free_large(relocs); |
40a5f0de EA |
3562 | |
3563 | return ret; | |
3564 | } | |
3565 | ||
83d60795 | 3566 | static int |
76446cac | 3567 | i915_gem_check_execbuffer (struct drm_i915_gem_execbuffer2 *exec, |
83d60795 CW |
3568 | uint64_t exec_offset) |
3569 | { | |
3570 | uint32_t exec_start, exec_len; | |
3571 | ||
3572 | exec_start = (uint32_t) exec_offset + exec->batch_start_offset; | |
3573 | exec_len = (uint32_t) exec->batch_len; | |
3574 | ||
3575 | if ((exec_start | exec_len) & 0x7) | |
3576 | return -EINVAL; | |
3577 | ||
3578 | if (!exec_start) | |
3579 | return -EINVAL; | |
3580 | ||
3581 | return 0; | |
3582 | } | |
3583 | ||
e6c3a2a6 | 3584 | static int |
6b95a207 KH |
3585 | i915_gem_wait_for_pending_flip(struct drm_device *dev, |
3586 | struct drm_gem_object **object_list, | |
3587 | int count) | |
3588 | { | |
3589 | drm_i915_private_t *dev_priv = dev->dev_private; | |
3590 | struct drm_i915_gem_object *obj_priv; | |
3591 | DEFINE_WAIT(wait); | |
3592 | int i, ret = 0; | |
3593 | ||
3594 | for (;;) { | |
3595 | prepare_to_wait(&dev_priv->pending_flip_queue, | |
3596 | &wait, TASK_INTERRUPTIBLE); | |
3597 | for (i = 0; i < count; i++) { | |
23010e43 | 3598 | obj_priv = to_intel_bo(object_list[i]); |
6b95a207 KH |
3599 | if (atomic_read(&obj_priv->pending_flip) > 0) |
3600 | break; | |
3601 | } | |
3602 | if (i == count) | |
3603 | break; | |
3604 | ||
3605 | if (!signal_pending(current)) { | |
3606 | mutex_unlock(&dev->struct_mutex); | |
3607 | schedule(); | |
3608 | mutex_lock(&dev->struct_mutex); | |
3609 | continue; | |
3610 | } | |
3611 | ret = -ERESTARTSYS; | |
3612 | break; | |
3613 | } | |
3614 | finish_wait(&dev_priv->pending_flip_queue, &wait); | |
3615 | ||
3616 | return ret; | |
3617 | } | |
3618 | ||
8dc5d147 | 3619 | static int |
76446cac JB |
3620 | i915_gem_do_execbuffer(struct drm_device *dev, void *data, |
3621 | struct drm_file *file_priv, | |
3622 | struct drm_i915_gem_execbuffer2 *args, | |
3623 | struct drm_i915_gem_exec_object2 *exec_list) | |
673a394b EA |
3624 | { |
3625 | drm_i915_private_t *dev_priv = dev->dev_private; | |
673a394b EA |
3626 | struct drm_gem_object **object_list = NULL; |
3627 | struct drm_gem_object *batch_obj; | |
b70d11da | 3628 | struct drm_i915_gem_object *obj_priv; |
201361a5 | 3629 | struct drm_clip_rect *cliprects = NULL; |
93533c29 | 3630 | struct drm_i915_gem_relocation_entry *relocs = NULL; |
8dc5d147 | 3631 | struct drm_i915_gem_request *request = NULL; |
30dbf0c0 | 3632 | int ret, ret2, i, pinned = 0; |
673a394b | 3633 | uint64_t exec_offset; |
5c12a07e | 3634 | uint32_t reloc_index; |
6b95a207 | 3635 | int pin_tries, flips; |
673a394b | 3636 | |
852835f3 ZN |
3637 | struct intel_ring_buffer *ring = NULL; |
3638 | ||
30dbf0c0 CW |
3639 | ret = i915_gem_check_is_wedged(dev); |
3640 | if (ret) | |
3641 | return ret; | |
3642 | ||
673a394b EA |
3643 | #if WATCH_EXEC |
3644 | DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n", | |
3645 | (int) args->buffers_ptr, args->buffer_count, args->batch_len); | |
3646 | #endif | |
d1b851fc ZN |
3647 | if (args->flags & I915_EXEC_BSD) { |
3648 | if (!HAS_BSD(dev)) { | |
3649 | DRM_ERROR("execbuf with wrong flag\n"); | |
3650 | return -EINVAL; | |
3651 | } | |
3652 | ring = &dev_priv->bsd_ring; | |
3653 | } else { | |
3654 | ring = &dev_priv->render_ring; | |
3655 | } | |
3656 | ||
4f481ed2 EA |
3657 | if (args->buffer_count < 1) { |
3658 | DRM_ERROR("execbuf with %d buffers\n", args->buffer_count); | |
3659 | return -EINVAL; | |
3660 | } | |
c8e0f93a | 3661 | object_list = drm_malloc_ab(sizeof(*object_list), args->buffer_count); |
76446cac JB |
3662 | if (object_list == NULL) { |
3663 | DRM_ERROR("Failed to allocate object list for %d buffers\n", | |
673a394b EA |
3664 | args->buffer_count); |
3665 | ret = -ENOMEM; | |
3666 | goto pre_mutex_err; | |
3667 | } | |
673a394b | 3668 | |
201361a5 | 3669 | if (args->num_cliprects != 0) { |
9a298b2a EA |
3670 | cliprects = kcalloc(args->num_cliprects, sizeof(*cliprects), |
3671 | GFP_KERNEL); | |
a40e8d31 OA |
3672 | if (cliprects == NULL) { |
3673 | ret = -ENOMEM; | |
201361a5 | 3674 | goto pre_mutex_err; |
a40e8d31 | 3675 | } |
201361a5 EA |
3676 | |
3677 | ret = copy_from_user(cliprects, | |
3678 | (struct drm_clip_rect __user *) | |
3679 | (uintptr_t) args->cliprects_ptr, | |
3680 | sizeof(*cliprects) * args->num_cliprects); | |
3681 | if (ret != 0) { | |
3682 | DRM_ERROR("copy %d cliprects failed: %d\n", | |
3683 | args->num_cliprects, ret); | |
c877cdce | 3684 | ret = -EFAULT; |
201361a5 EA |
3685 | goto pre_mutex_err; |
3686 | } | |
3687 | } | |
3688 | ||
8dc5d147 CW |
3689 | request = kzalloc(sizeof(*request), GFP_KERNEL); |
3690 | if (request == NULL) { | |
3691 | ret = -ENOMEM; | |
3692 | goto pre_mutex_err; | |
3693 | } | |
3694 | ||
40a5f0de EA |
3695 | ret = i915_gem_get_relocs_from_user(exec_list, args->buffer_count, |
3696 | &relocs); | |
3697 | if (ret != 0) | |
3698 | goto pre_mutex_err; | |
3699 | ||
76c1dec1 CW |
3700 | ret = i915_mutex_lock_interruptible(dev); |
3701 | if (ret) | |
3702 | goto pre_mutex_err; | |
673a394b | 3703 | |
673a394b | 3704 | if (dev_priv->mm.suspended) { |
673a394b | 3705 | mutex_unlock(&dev->struct_mutex); |
a198bc80 CW |
3706 | ret = -EBUSY; |
3707 | goto pre_mutex_err; | |
673a394b EA |
3708 | } |
3709 | ||
ac94a962 | 3710 | /* Look up object handles */ |
6b95a207 | 3711 | flips = 0; |
673a394b EA |
3712 | for (i = 0; i < args->buffer_count; i++) { |
3713 | object_list[i] = drm_gem_object_lookup(dev, file_priv, | |
3714 | exec_list[i].handle); | |
3715 | if (object_list[i] == NULL) { | |
3716 | DRM_ERROR("Invalid object handle %d at index %d\n", | |
3717 | exec_list[i].handle, i); | |
0ce907f8 CW |
3718 | /* prevent error path from reading uninitialized data */ |
3719 | args->buffer_count = i + 1; | |
bf79cb91 | 3720 | ret = -ENOENT; |
673a394b EA |
3721 | goto err; |
3722 | } | |
b70d11da | 3723 | |
23010e43 | 3724 | obj_priv = to_intel_bo(object_list[i]); |
b70d11da KH |
3725 | if (obj_priv->in_execbuffer) { |
3726 | DRM_ERROR("Object %p appears more than once in object list\n", | |
3727 | object_list[i]); | |
0ce907f8 CW |
3728 | /* prevent error path from reading uninitialized data */ |
3729 | args->buffer_count = i + 1; | |
bf79cb91 | 3730 | ret = -EINVAL; |
b70d11da KH |
3731 | goto err; |
3732 | } | |
3733 | obj_priv->in_execbuffer = true; | |
6b95a207 KH |
3734 | flips += atomic_read(&obj_priv->pending_flip); |
3735 | } | |
3736 | ||
3737 | if (flips > 0) { | |
3738 | ret = i915_gem_wait_for_pending_flip(dev, object_list, | |
3739 | args->buffer_count); | |
3740 | if (ret) | |
3741 | goto err; | |
ac94a962 | 3742 | } |
673a394b | 3743 | |
ac94a962 KP |
3744 | /* Pin and relocate */ |
3745 | for (pin_tries = 0; ; pin_tries++) { | |
3746 | ret = 0; | |
40a5f0de EA |
3747 | reloc_index = 0; |
3748 | ||
ac94a962 KP |
3749 | for (i = 0; i < args->buffer_count; i++) { |
3750 | object_list[i]->pending_read_domains = 0; | |
3751 | object_list[i]->pending_write_domain = 0; | |
3752 | ret = i915_gem_object_pin_and_relocate(object_list[i], | |
3753 | file_priv, | |
40a5f0de EA |
3754 | &exec_list[i], |
3755 | &relocs[reloc_index]); | |
ac94a962 KP |
3756 | if (ret) |
3757 | break; | |
3758 | pinned = i + 1; | |
40a5f0de | 3759 | reloc_index += exec_list[i].relocation_count; |
ac94a962 KP |
3760 | } |
3761 | /* success */ | |
3762 | if (ret == 0) | |
3763 | break; | |
3764 | ||
3765 | /* error other than GTT full, or we've already tried again */ | |
2939e1f5 | 3766 | if (ret != -ENOSPC || pin_tries >= 1) { |
07f73f69 CW |
3767 | if (ret != -ERESTARTSYS) { |
3768 | unsigned long long total_size = 0; | |
3d1cc470 CW |
3769 | int num_fences = 0; |
3770 | for (i = 0; i < args->buffer_count; i++) { | |
43b27f40 | 3771 | obj_priv = to_intel_bo(object_list[i]); |
3d1cc470 | 3772 | |
07f73f69 | 3773 | total_size += object_list[i]->size; |
3d1cc470 CW |
3774 | num_fences += |
3775 | exec_list[i].flags & EXEC_OBJECT_NEEDS_FENCE && | |
3776 | obj_priv->tiling_mode != I915_TILING_NONE; | |
3777 | } | |
3778 | DRM_ERROR("Failed to pin buffer %d of %d, total %llu bytes, %d fences: %d\n", | |
07f73f69 | 3779 | pinned+1, args->buffer_count, |
3d1cc470 CW |
3780 | total_size, num_fences, |
3781 | ret); | |
07f73f69 CW |
3782 | DRM_ERROR("%d objects [%d pinned], " |
3783 | "%d object bytes [%d pinned], " | |
3784 | "%d/%d gtt bytes\n", | |
3785 | atomic_read(&dev->object_count), | |
3786 | atomic_read(&dev->pin_count), | |
3787 | atomic_read(&dev->object_memory), | |
3788 | atomic_read(&dev->pin_memory), | |
3789 | atomic_read(&dev->gtt_memory), | |
3790 | dev->gtt_total); | |
3791 | } | |
673a394b EA |
3792 | goto err; |
3793 | } | |
ac94a962 KP |
3794 | |
3795 | /* unpin all of our buffers */ | |
3796 | for (i = 0; i < pinned; i++) | |
3797 | i915_gem_object_unpin(object_list[i]); | |
b1177636 | 3798 | pinned = 0; |
ac94a962 KP |
3799 | |
3800 | /* evict everyone we can from the aperture */ | |
3801 | ret = i915_gem_evict_everything(dev); | |
07f73f69 | 3802 | if (ret && ret != -ENOSPC) |
ac94a962 | 3803 | goto err; |
673a394b EA |
3804 | } |
3805 | ||
3806 | /* Set the pending read domains for the batch buffer to COMMAND */ | |
3807 | batch_obj = object_list[args->buffer_count-1]; | |
5f26a2c7 CW |
3808 | if (batch_obj->pending_write_domain) { |
3809 | DRM_ERROR("Attempting to use self-modifying batch buffer\n"); | |
3810 | ret = -EINVAL; | |
3811 | goto err; | |
3812 | } | |
3813 | batch_obj->pending_read_domains |= I915_GEM_DOMAIN_COMMAND; | |
673a394b | 3814 | |
83d60795 CW |
3815 | /* Sanity check the batch buffer, prior to moving objects */ |
3816 | exec_offset = exec_list[args->buffer_count - 1].offset; | |
3817 | ret = i915_gem_check_execbuffer (args, exec_offset); | |
3818 | if (ret != 0) { | |
3819 | DRM_ERROR("execbuf with invalid offset/length\n"); | |
3820 | goto err; | |
3821 | } | |
3822 | ||
646f0f6e KP |
3823 | /* Zero the global flush/invalidate flags. These |
3824 | * will be modified as new domains are computed | |
3825 | * for each object | |
3826 | */ | |
3827 | dev->invalidate_domains = 0; | |
3828 | dev->flush_domains = 0; | |
9220434a | 3829 | dev_priv->mm.flush_rings = 0; |
646f0f6e | 3830 | |
673a394b EA |
3831 | for (i = 0; i < args->buffer_count; i++) { |
3832 | struct drm_gem_object *obj = object_list[i]; | |
673a394b | 3833 | |
646f0f6e | 3834 | /* Compute new gpu domains and update invalidate/flush */ |
8b0e378a | 3835 | i915_gem_object_set_to_gpu_domain(obj); |
673a394b EA |
3836 | } |
3837 | ||
646f0f6e KP |
3838 | if (dev->invalidate_domains | dev->flush_domains) { |
3839 | #if WATCH_EXEC | |
3840 | DRM_INFO("%s: invalidate_domains %08x flush_domains %08x\n", | |
3841 | __func__, | |
3842 | dev->invalidate_domains, | |
3843 | dev->flush_domains); | |
3844 | #endif | |
c78ec30b | 3845 | i915_gem_flush(dev, file_priv, |
646f0f6e | 3846 | dev->invalidate_domains, |
9220434a CW |
3847 | dev->flush_domains, |
3848 | dev_priv->mm.flush_rings); | |
a6910434 DV |
3849 | } |
3850 | ||
efbeed96 EA |
3851 | for (i = 0; i < args->buffer_count; i++) { |
3852 | struct drm_gem_object *obj = object_list[i]; | |
23010e43 | 3853 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
1c5d22f7 | 3854 | uint32_t old_write_domain = obj->write_domain; |
efbeed96 EA |
3855 | |
3856 | obj->write_domain = obj->pending_write_domain; | |
99fcb766 DV |
3857 | if (obj->write_domain) |
3858 | list_move_tail(&obj_priv->gpu_write_list, | |
3859 | &dev_priv->mm.gpu_write_list); | |
99fcb766 | 3860 | |
1c5d22f7 CW |
3861 | trace_i915_gem_object_change_domain(obj, |
3862 | obj->read_domains, | |
3863 | old_write_domain); | |
efbeed96 EA |
3864 | } |
3865 | ||
673a394b EA |
3866 | #if WATCH_COHERENCY |
3867 | for (i = 0; i < args->buffer_count; i++) { | |
3868 | i915_gem_object_check_coherency(object_list[i], | |
3869 | exec_list[i].handle); | |
3870 | } | |
3871 | #endif | |
3872 | ||
673a394b | 3873 | #if WATCH_EXEC |
6911a9b8 | 3874 | i915_gem_dump_object(batch_obj, |
673a394b EA |
3875 | args->batch_len, |
3876 | __func__, | |
3877 | ~0); | |
3878 | #endif | |
3879 | ||
673a394b | 3880 | /* Exec the batchbuffer */ |
852835f3 ZN |
3881 | ret = ring->dispatch_gem_execbuffer(dev, ring, args, |
3882 | cliprects, exec_offset); | |
673a394b EA |
3883 | if (ret) { |
3884 | DRM_ERROR("dispatch failed %d\n", ret); | |
3885 | goto err; | |
3886 | } | |
3887 | ||
3888 | /* | |
3889 | * Ensure that the commands in the batch buffer are | |
3890 | * finished before the interrupt fires | |
3891 | */ | |
8a1a49f9 | 3892 | i915_retire_commands(dev, ring); |
673a394b | 3893 | |
617dbe27 DV |
3894 | for (i = 0; i < args->buffer_count; i++) { |
3895 | struct drm_gem_object *obj = object_list[i]; | |
3896 | obj_priv = to_intel_bo(obj); | |
3897 | ||
3898 | i915_gem_object_move_to_active(obj, ring); | |
617dbe27 | 3899 | } |
a56ba56c | 3900 | |
5c12a07e | 3901 | i915_add_request(dev, file_priv, request, ring); |
8dc5d147 | 3902 | request = NULL; |
673a394b | 3903 | |
673a394b | 3904 | err: |
aad87dff JL |
3905 | for (i = 0; i < pinned; i++) |
3906 | i915_gem_object_unpin(object_list[i]); | |
3907 | ||
b70d11da KH |
3908 | for (i = 0; i < args->buffer_count; i++) { |
3909 | if (object_list[i]) { | |
23010e43 | 3910 | obj_priv = to_intel_bo(object_list[i]); |
b70d11da KH |
3911 | obj_priv->in_execbuffer = false; |
3912 | } | |
aad87dff | 3913 | drm_gem_object_unreference(object_list[i]); |
b70d11da | 3914 | } |
673a394b | 3915 | |
673a394b EA |
3916 | mutex_unlock(&dev->struct_mutex); |
3917 | ||
93533c29 | 3918 | pre_mutex_err: |
40a5f0de EA |
3919 | /* Copy the updated relocations out regardless of current error |
3920 | * state. Failure to update the relocs would mean that the next | |
3921 | * time userland calls execbuf, it would do so with presumed offset | |
3922 | * state that didn't match the actual object state. | |
3923 | */ | |
3924 | ret2 = i915_gem_put_relocs_to_user(exec_list, args->buffer_count, | |
3925 | relocs); | |
3926 | if (ret2 != 0) { | |
3927 | DRM_ERROR("Failed to copy relocations back out: %d\n", ret2); | |
3928 | ||
3929 | if (ret == 0) | |
3930 | ret = ret2; | |
3931 | } | |
3932 | ||
8e7d2b2c | 3933 | drm_free_large(object_list); |
9a298b2a | 3934 | kfree(cliprects); |
8dc5d147 | 3935 | kfree(request); |
673a394b EA |
3936 | |
3937 | return ret; | |
3938 | } | |
3939 | ||
76446cac JB |
3940 | /* |
3941 | * Legacy execbuffer just creates an exec2 list from the original exec object | |
3942 | * list array and passes it to the real function. | |
3943 | */ | |
3944 | int | |
3945 | i915_gem_execbuffer(struct drm_device *dev, void *data, | |
3946 | struct drm_file *file_priv) | |
3947 | { | |
3948 | struct drm_i915_gem_execbuffer *args = data; | |
3949 | struct drm_i915_gem_execbuffer2 exec2; | |
3950 | struct drm_i915_gem_exec_object *exec_list = NULL; | |
3951 | struct drm_i915_gem_exec_object2 *exec2_list = NULL; | |
3952 | int ret, i; | |
3953 | ||
3954 | #if WATCH_EXEC | |
3955 | DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n", | |
3956 | (int) args->buffers_ptr, args->buffer_count, args->batch_len); | |
3957 | #endif | |
3958 | ||
3959 | if (args->buffer_count < 1) { | |
3960 | DRM_ERROR("execbuf with %d buffers\n", args->buffer_count); | |
3961 | return -EINVAL; | |
3962 | } | |
3963 | ||
3964 | /* Copy in the exec list from userland */ | |
3965 | exec_list = drm_malloc_ab(sizeof(*exec_list), args->buffer_count); | |
3966 | exec2_list = drm_malloc_ab(sizeof(*exec2_list), args->buffer_count); | |
3967 | if (exec_list == NULL || exec2_list == NULL) { | |
3968 | DRM_ERROR("Failed to allocate exec list for %d buffers\n", | |
3969 | args->buffer_count); | |
3970 | drm_free_large(exec_list); | |
3971 | drm_free_large(exec2_list); | |
3972 | return -ENOMEM; | |
3973 | } | |
3974 | ret = copy_from_user(exec_list, | |
3975 | (struct drm_i915_relocation_entry __user *) | |
3976 | (uintptr_t) args->buffers_ptr, | |
3977 | sizeof(*exec_list) * args->buffer_count); | |
3978 | if (ret != 0) { | |
3979 | DRM_ERROR("copy %d exec entries failed %d\n", | |
3980 | args->buffer_count, ret); | |
3981 | drm_free_large(exec_list); | |
3982 | drm_free_large(exec2_list); | |
3983 | return -EFAULT; | |
3984 | } | |
3985 | ||
3986 | for (i = 0; i < args->buffer_count; i++) { | |
3987 | exec2_list[i].handle = exec_list[i].handle; | |
3988 | exec2_list[i].relocation_count = exec_list[i].relocation_count; | |
3989 | exec2_list[i].relocs_ptr = exec_list[i].relocs_ptr; | |
3990 | exec2_list[i].alignment = exec_list[i].alignment; | |
3991 | exec2_list[i].offset = exec_list[i].offset; | |
a6c45cf0 | 3992 | if (INTEL_INFO(dev)->gen < 4) |
76446cac JB |
3993 | exec2_list[i].flags = EXEC_OBJECT_NEEDS_FENCE; |
3994 | else | |
3995 | exec2_list[i].flags = 0; | |
3996 | } | |
3997 | ||
3998 | exec2.buffers_ptr = args->buffers_ptr; | |
3999 | exec2.buffer_count = args->buffer_count; | |
4000 | exec2.batch_start_offset = args->batch_start_offset; | |
4001 | exec2.batch_len = args->batch_len; | |
4002 | exec2.DR1 = args->DR1; | |
4003 | exec2.DR4 = args->DR4; | |
4004 | exec2.num_cliprects = args->num_cliprects; | |
4005 | exec2.cliprects_ptr = args->cliprects_ptr; | |
852835f3 | 4006 | exec2.flags = I915_EXEC_RENDER; |
76446cac JB |
4007 | |
4008 | ret = i915_gem_do_execbuffer(dev, data, file_priv, &exec2, exec2_list); | |
4009 | if (!ret) { | |
4010 | /* Copy the new buffer offsets back to the user's exec list. */ | |
4011 | for (i = 0; i < args->buffer_count; i++) | |
4012 | exec_list[i].offset = exec2_list[i].offset; | |
4013 | /* ... and back out to userspace */ | |
4014 | ret = copy_to_user((struct drm_i915_relocation_entry __user *) | |
4015 | (uintptr_t) args->buffers_ptr, | |
4016 | exec_list, | |
4017 | sizeof(*exec_list) * args->buffer_count); | |
4018 | if (ret) { | |
4019 | ret = -EFAULT; | |
4020 | DRM_ERROR("failed to copy %d exec entries " | |
4021 | "back to user (%d)\n", | |
4022 | args->buffer_count, ret); | |
4023 | } | |
76446cac JB |
4024 | } |
4025 | ||
4026 | drm_free_large(exec_list); | |
4027 | drm_free_large(exec2_list); | |
4028 | return ret; | |
4029 | } | |
4030 | ||
4031 | int | |
4032 | i915_gem_execbuffer2(struct drm_device *dev, void *data, | |
4033 | struct drm_file *file_priv) | |
4034 | { | |
4035 | struct drm_i915_gem_execbuffer2 *args = data; | |
4036 | struct drm_i915_gem_exec_object2 *exec2_list = NULL; | |
4037 | int ret; | |
4038 | ||
4039 | #if WATCH_EXEC | |
4040 | DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n", | |
4041 | (int) args->buffers_ptr, args->buffer_count, args->batch_len); | |
4042 | #endif | |
4043 | ||
4044 | if (args->buffer_count < 1) { | |
4045 | DRM_ERROR("execbuf2 with %d buffers\n", args->buffer_count); | |
4046 | return -EINVAL; | |
4047 | } | |
4048 | ||
4049 | exec2_list = drm_malloc_ab(sizeof(*exec2_list), args->buffer_count); | |
4050 | if (exec2_list == NULL) { | |
4051 | DRM_ERROR("Failed to allocate exec list for %d buffers\n", | |
4052 | args->buffer_count); | |
4053 | return -ENOMEM; | |
4054 | } | |
4055 | ret = copy_from_user(exec2_list, | |
4056 | (struct drm_i915_relocation_entry __user *) | |
4057 | (uintptr_t) args->buffers_ptr, | |
4058 | sizeof(*exec2_list) * args->buffer_count); | |
4059 | if (ret != 0) { | |
4060 | DRM_ERROR("copy %d exec entries failed %d\n", | |
4061 | args->buffer_count, ret); | |
4062 | drm_free_large(exec2_list); | |
4063 | return -EFAULT; | |
4064 | } | |
4065 | ||
4066 | ret = i915_gem_do_execbuffer(dev, data, file_priv, args, exec2_list); | |
4067 | if (!ret) { | |
4068 | /* Copy the new buffer offsets back to the user's exec list. */ | |
4069 | ret = copy_to_user((struct drm_i915_relocation_entry __user *) | |
4070 | (uintptr_t) args->buffers_ptr, | |
4071 | exec2_list, | |
4072 | sizeof(*exec2_list) * args->buffer_count); | |
4073 | if (ret) { | |
4074 | ret = -EFAULT; | |
4075 | DRM_ERROR("failed to copy %d exec entries " | |
4076 | "back to user (%d)\n", | |
4077 | args->buffer_count, ret); | |
4078 | } | |
4079 | } | |
4080 | ||
4081 | drm_free_large(exec2_list); | |
4082 | return ret; | |
4083 | } | |
4084 | ||
673a394b EA |
4085 | int |
4086 | i915_gem_object_pin(struct drm_gem_object *obj, uint32_t alignment) | |
4087 | { | |
4088 | struct drm_device *dev = obj->dev; | |
f13d3f73 | 4089 | struct drm_i915_private *dev_priv = dev->dev_private; |
23010e43 | 4090 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
673a394b EA |
4091 | int ret; |
4092 | ||
778c3544 | 4093 | BUG_ON(obj_priv->pin_count == DRM_I915_GEM_OBJECT_MAX_PIN_COUNT); |
23bc5982 | 4094 | WARN_ON(i915_verify_lists(dev)); |
ac0c6b5a CW |
4095 | |
4096 | if (obj_priv->gtt_space != NULL) { | |
4097 | if (alignment == 0) | |
4098 | alignment = i915_gem_get_gtt_alignment(obj); | |
4099 | if (obj_priv->gtt_offset & (alignment - 1)) { | |
ae7d49d8 CW |
4100 | WARN(obj_priv->pin_count, |
4101 | "bo is already pinned with incorrect alignment:" | |
4102 | " offset=%x, req.alignment=%x\n", | |
4103 | obj_priv->gtt_offset, alignment); | |
ac0c6b5a CW |
4104 | ret = i915_gem_object_unbind(obj); |
4105 | if (ret) | |
4106 | return ret; | |
4107 | } | |
4108 | } | |
4109 | ||
673a394b EA |
4110 | if (obj_priv->gtt_space == NULL) { |
4111 | ret = i915_gem_object_bind_to_gtt(obj, alignment); | |
9731129c | 4112 | if (ret) |
673a394b | 4113 | return ret; |
22c344e9 | 4114 | } |
76446cac | 4115 | |
673a394b EA |
4116 | obj_priv->pin_count++; |
4117 | ||
4118 | /* If the object is not active and not pending a flush, | |
4119 | * remove it from the inactive list | |
4120 | */ | |
4121 | if (obj_priv->pin_count == 1) { | |
4122 | atomic_inc(&dev->pin_count); | |
4123 | atomic_add(obj->size, &dev->pin_memory); | |
f13d3f73 CW |
4124 | if (!obj_priv->active) |
4125 | list_move_tail(&obj_priv->list, | |
4126 | &dev_priv->mm.pinned_list); | |
673a394b | 4127 | } |
673a394b | 4128 | |
23bc5982 | 4129 | WARN_ON(i915_verify_lists(dev)); |
673a394b EA |
4130 | return 0; |
4131 | } | |
4132 | ||
4133 | void | |
4134 | i915_gem_object_unpin(struct drm_gem_object *obj) | |
4135 | { | |
4136 | struct drm_device *dev = obj->dev; | |
4137 | drm_i915_private_t *dev_priv = dev->dev_private; | |
23010e43 | 4138 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
673a394b | 4139 | |
23bc5982 | 4140 | WARN_ON(i915_verify_lists(dev)); |
673a394b EA |
4141 | obj_priv->pin_count--; |
4142 | BUG_ON(obj_priv->pin_count < 0); | |
4143 | BUG_ON(obj_priv->gtt_space == NULL); | |
4144 | ||
4145 | /* If the object is no longer pinned, and is | |
4146 | * neither active nor being flushed, then stick it on | |
4147 | * the inactive list | |
4148 | */ | |
4149 | if (obj_priv->pin_count == 0) { | |
f13d3f73 | 4150 | if (!obj_priv->active) |
673a394b EA |
4151 | list_move_tail(&obj_priv->list, |
4152 | &dev_priv->mm.inactive_list); | |
4153 | atomic_dec(&dev->pin_count); | |
4154 | atomic_sub(obj->size, &dev->pin_memory); | |
4155 | } | |
23bc5982 | 4156 | WARN_ON(i915_verify_lists(dev)); |
673a394b EA |
4157 | } |
4158 | ||
4159 | int | |
4160 | i915_gem_pin_ioctl(struct drm_device *dev, void *data, | |
4161 | struct drm_file *file_priv) | |
4162 | { | |
4163 | struct drm_i915_gem_pin *args = data; | |
4164 | struct drm_gem_object *obj; | |
4165 | struct drm_i915_gem_object *obj_priv; | |
4166 | int ret; | |
4167 | ||
673a394b EA |
4168 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); |
4169 | if (obj == NULL) { | |
4170 | DRM_ERROR("Bad handle in i915_gem_pin_ioctl(): %d\n", | |
4171 | args->handle); | |
bf79cb91 | 4172 | return -ENOENT; |
673a394b | 4173 | } |
23010e43 | 4174 | obj_priv = to_intel_bo(obj); |
673a394b | 4175 | |
76c1dec1 CW |
4176 | ret = i915_mutex_lock_interruptible(dev); |
4177 | if (ret) { | |
4178 | drm_gem_object_unreference_unlocked(obj); | |
4179 | return ret; | |
4180 | } | |
4181 | ||
bb6baf76 CW |
4182 | if (obj_priv->madv != I915_MADV_WILLNEED) { |
4183 | DRM_ERROR("Attempting to pin a purgeable buffer\n"); | |
3ef94daa CW |
4184 | drm_gem_object_unreference(obj); |
4185 | mutex_unlock(&dev->struct_mutex); | |
4186 | return -EINVAL; | |
4187 | } | |
4188 | ||
79e53945 JB |
4189 | if (obj_priv->pin_filp != NULL && obj_priv->pin_filp != file_priv) { |
4190 | DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n", | |
4191 | args->handle); | |
96dec61d | 4192 | drm_gem_object_unreference(obj); |
673a394b | 4193 | mutex_unlock(&dev->struct_mutex); |
79e53945 JB |
4194 | return -EINVAL; |
4195 | } | |
4196 | ||
4197 | obj_priv->user_pin_count++; | |
4198 | obj_priv->pin_filp = file_priv; | |
4199 | if (obj_priv->user_pin_count == 1) { | |
4200 | ret = i915_gem_object_pin(obj, args->alignment); | |
4201 | if (ret != 0) { | |
4202 | drm_gem_object_unreference(obj); | |
4203 | mutex_unlock(&dev->struct_mutex); | |
4204 | return ret; | |
4205 | } | |
673a394b EA |
4206 | } |
4207 | ||
4208 | /* XXX - flush the CPU caches for pinned objects | |
4209 | * as the X server doesn't manage domains yet | |
4210 | */ | |
e47c68e9 | 4211 | i915_gem_object_flush_cpu_write_domain(obj); |
673a394b EA |
4212 | args->offset = obj_priv->gtt_offset; |
4213 | drm_gem_object_unreference(obj); | |
4214 | mutex_unlock(&dev->struct_mutex); | |
4215 | ||
4216 | return 0; | |
4217 | } | |
4218 | ||
4219 | int | |
4220 | i915_gem_unpin_ioctl(struct drm_device *dev, void *data, | |
4221 | struct drm_file *file_priv) | |
4222 | { | |
4223 | struct drm_i915_gem_pin *args = data; | |
4224 | struct drm_gem_object *obj; | |
79e53945 | 4225 | struct drm_i915_gem_object *obj_priv; |
76c1dec1 | 4226 | int ret; |
673a394b EA |
4227 | |
4228 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); | |
4229 | if (obj == NULL) { | |
4230 | DRM_ERROR("Bad handle in i915_gem_unpin_ioctl(): %d\n", | |
4231 | args->handle); | |
bf79cb91 | 4232 | return -ENOENT; |
673a394b EA |
4233 | } |
4234 | ||
23010e43 | 4235 | obj_priv = to_intel_bo(obj); |
76c1dec1 CW |
4236 | |
4237 | ret = i915_mutex_lock_interruptible(dev); | |
4238 | if (ret) { | |
4239 | drm_gem_object_unreference_unlocked(obj); | |
4240 | return ret; | |
4241 | } | |
4242 | ||
79e53945 JB |
4243 | if (obj_priv->pin_filp != file_priv) { |
4244 | DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n", | |
4245 | args->handle); | |
4246 | drm_gem_object_unreference(obj); | |
4247 | mutex_unlock(&dev->struct_mutex); | |
4248 | return -EINVAL; | |
4249 | } | |
4250 | obj_priv->user_pin_count--; | |
4251 | if (obj_priv->user_pin_count == 0) { | |
4252 | obj_priv->pin_filp = NULL; | |
4253 | i915_gem_object_unpin(obj); | |
4254 | } | |
673a394b EA |
4255 | |
4256 | drm_gem_object_unreference(obj); | |
4257 | mutex_unlock(&dev->struct_mutex); | |
4258 | return 0; | |
4259 | } | |
4260 | ||
4261 | int | |
4262 | i915_gem_busy_ioctl(struct drm_device *dev, void *data, | |
4263 | struct drm_file *file_priv) | |
4264 | { | |
4265 | struct drm_i915_gem_busy *args = data; | |
4266 | struct drm_gem_object *obj; | |
4267 | struct drm_i915_gem_object *obj_priv; | |
30dbf0c0 CW |
4268 | int ret; |
4269 | ||
673a394b EA |
4270 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); |
4271 | if (obj == NULL) { | |
4272 | DRM_ERROR("Bad handle in i915_gem_busy_ioctl(): %d\n", | |
4273 | args->handle); | |
bf79cb91 | 4274 | return -ENOENT; |
673a394b EA |
4275 | } |
4276 | ||
76c1dec1 CW |
4277 | ret = i915_mutex_lock_interruptible(dev); |
4278 | if (ret) { | |
4279 | drm_gem_object_unreference_unlocked(obj); | |
4280 | return ret; | |
30dbf0c0 CW |
4281 | } |
4282 | ||
0be555b6 CW |
4283 | /* Count all active objects as busy, even if they are currently not used |
4284 | * by the gpu. Users of this interface expect objects to eventually | |
4285 | * become non-busy without any further actions, therefore emit any | |
4286 | * necessary flushes here. | |
c4de0a5d | 4287 | */ |
0be555b6 CW |
4288 | obj_priv = to_intel_bo(obj); |
4289 | args->busy = obj_priv->active; | |
4290 | if (args->busy) { | |
4291 | /* Unconditionally flush objects, even when the gpu still uses this | |
4292 | * object. Userspace calling this function indicates that it wants to | |
4293 | * use this buffer rather sooner than later, so issuing the required | |
4294 | * flush earlier is beneficial. | |
4295 | */ | |
c78ec30b CW |
4296 | if (obj->write_domain & I915_GEM_GPU_DOMAINS) |
4297 | i915_gem_flush_ring(dev, file_priv, | |
9220434a CW |
4298 | obj_priv->ring, |
4299 | 0, obj->write_domain); | |
0be555b6 CW |
4300 | |
4301 | /* Update the active list for the hardware's current position. | |
4302 | * Otherwise this only updates on a delayed timer or when irqs | |
4303 | * are actually unmasked, and our working set ends up being | |
4304 | * larger than required. | |
4305 | */ | |
4306 | i915_gem_retire_requests_ring(dev, obj_priv->ring); | |
4307 | ||
4308 | args->busy = obj_priv->active; | |
4309 | } | |
673a394b EA |
4310 | |
4311 | drm_gem_object_unreference(obj); | |
4312 | mutex_unlock(&dev->struct_mutex); | |
76c1dec1 | 4313 | return 0; |
673a394b EA |
4314 | } |
4315 | ||
4316 | int | |
4317 | i915_gem_throttle_ioctl(struct drm_device *dev, void *data, | |
4318 | struct drm_file *file_priv) | |
4319 | { | |
4320 | return i915_gem_ring_throttle(dev, file_priv); | |
4321 | } | |
4322 | ||
3ef94daa CW |
4323 | int |
4324 | i915_gem_madvise_ioctl(struct drm_device *dev, void *data, | |
4325 | struct drm_file *file_priv) | |
4326 | { | |
4327 | struct drm_i915_gem_madvise *args = data; | |
4328 | struct drm_gem_object *obj; | |
4329 | struct drm_i915_gem_object *obj_priv; | |
76c1dec1 | 4330 | int ret; |
3ef94daa CW |
4331 | |
4332 | switch (args->madv) { | |
4333 | case I915_MADV_DONTNEED: | |
4334 | case I915_MADV_WILLNEED: | |
4335 | break; | |
4336 | default: | |
4337 | return -EINVAL; | |
4338 | } | |
4339 | ||
4340 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); | |
4341 | if (obj == NULL) { | |
4342 | DRM_ERROR("Bad handle in i915_gem_madvise_ioctl(): %d\n", | |
4343 | args->handle); | |
bf79cb91 | 4344 | return -ENOENT; |
3ef94daa | 4345 | } |
23010e43 | 4346 | obj_priv = to_intel_bo(obj); |
3ef94daa | 4347 | |
76c1dec1 CW |
4348 | ret = i915_mutex_lock_interruptible(dev); |
4349 | if (ret) { | |
4350 | drm_gem_object_unreference_unlocked(obj); | |
4351 | return ret; | |
4352 | } | |
4353 | ||
3ef94daa CW |
4354 | if (obj_priv->pin_count) { |
4355 | drm_gem_object_unreference(obj); | |
4356 | mutex_unlock(&dev->struct_mutex); | |
4357 | ||
4358 | DRM_ERROR("Attempted i915_gem_madvise_ioctl() on a pinned object\n"); | |
4359 | return -EINVAL; | |
4360 | } | |
4361 | ||
bb6baf76 CW |
4362 | if (obj_priv->madv != __I915_MADV_PURGED) |
4363 | obj_priv->madv = args->madv; | |
3ef94daa | 4364 | |
2d7ef395 CW |
4365 | /* if the object is no longer bound, discard its backing storage */ |
4366 | if (i915_gem_object_is_purgeable(obj_priv) && | |
4367 | obj_priv->gtt_space == NULL) | |
4368 | i915_gem_object_truncate(obj); | |
4369 | ||
bb6baf76 CW |
4370 | args->retained = obj_priv->madv != __I915_MADV_PURGED; |
4371 | ||
3ef94daa CW |
4372 | drm_gem_object_unreference(obj); |
4373 | mutex_unlock(&dev->struct_mutex); | |
4374 | ||
4375 | return 0; | |
4376 | } | |
4377 | ||
ac52bc56 DV |
4378 | struct drm_gem_object * i915_gem_alloc_object(struct drm_device *dev, |
4379 | size_t size) | |
4380 | { | |
c397b908 | 4381 | struct drm_i915_gem_object *obj; |
ac52bc56 | 4382 | |
c397b908 DV |
4383 | obj = kzalloc(sizeof(*obj), GFP_KERNEL); |
4384 | if (obj == NULL) | |
4385 | return NULL; | |
673a394b | 4386 | |
c397b908 DV |
4387 | if (drm_gem_object_init(dev, &obj->base, size) != 0) { |
4388 | kfree(obj); | |
4389 | return NULL; | |
4390 | } | |
673a394b | 4391 | |
c397b908 DV |
4392 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; |
4393 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; | |
673a394b | 4394 | |
c397b908 | 4395 | obj->agp_type = AGP_USER_MEMORY; |
62b8b215 | 4396 | obj->base.driver_private = NULL; |
c397b908 DV |
4397 | obj->fence_reg = I915_FENCE_REG_NONE; |
4398 | INIT_LIST_HEAD(&obj->list); | |
4399 | INIT_LIST_HEAD(&obj->gpu_write_list); | |
c397b908 | 4400 | obj->madv = I915_MADV_WILLNEED; |
de151cf6 | 4401 | |
c397b908 DV |
4402 | trace_i915_gem_object_create(&obj->base); |
4403 | ||
4404 | return &obj->base; | |
4405 | } | |
4406 | ||
4407 | int i915_gem_init_object(struct drm_gem_object *obj) | |
4408 | { | |
4409 | BUG(); | |
de151cf6 | 4410 | |
673a394b EA |
4411 | return 0; |
4412 | } | |
4413 | ||
be72615b | 4414 | static void i915_gem_free_object_tail(struct drm_gem_object *obj) |
673a394b | 4415 | { |
de151cf6 | 4416 | struct drm_device *dev = obj->dev; |
be72615b | 4417 | drm_i915_private_t *dev_priv = dev->dev_private; |
23010e43 | 4418 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
be72615b | 4419 | int ret; |
673a394b | 4420 | |
be72615b CW |
4421 | ret = i915_gem_object_unbind(obj); |
4422 | if (ret == -ERESTARTSYS) { | |
4423 | list_move(&obj_priv->list, | |
4424 | &dev_priv->mm.deferred_free_list); | |
4425 | return; | |
4426 | } | |
673a394b | 4427 | |
7e616158 CW |
4428 | if (obj_priv->mmap_offset) |
4429 | i915_gem_free_mmap_offset(obj); | |
de151cf6 | 4430 | |
c397b908 DV |
4431 | drm_gem_object_release(obj); |
4432 | ||
9a298b2a | 4433 | kfree(obj_priv->page_cpu_valid); |
280b713b | 4434 | kfree(obj_priv->bit_17); |
c397b908 | 4435 | kfree(obj_priv); |
673a394b EA |
4436 | } |
4437 | ||
be72615b CW |
4438 | void i915_gem_free_object(struct drm_gem_object *obj) |
4439 | { | |
4440 | struct drm_device *dev = obj->dev; | |
4441 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); | |
4442 | ||
4443 | trace_i915_gem_object_destroy(obj); | |
4444 | ||
4445 | while (obj_priv->pin_count > 0) | |
4446 | i915_gem_object_unpin(obj); | |
4447 | ||
4448 | if (obj_priv->phys_obj) | |
4449 | i915_gem_detach_phys_object(dev, obj); | |
4450 | ||
4451 | i915_gem_free_object_tail(obj); | |
4452 | } | |
4453 | ||
29105ccc CW |
4454 | int |
4455 | i915_gem_idle(struct drm_device *dev) | |
4456 | { | |
4457 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4458 | int ret; | |
28dfe52a | 4459 | |
29105ccc | 4460 | mutex_lock(&dev->struct_mutex); |
1c5d22f7 | 4461 | |
8187a2b7 | 4462 | if (dev_priv->mm.suspended || |
d1b851fc ZN |
4463 | (dev_priv->render_ring.gem_object == NULL) || |
4464 | (HAS_BSD(dev) && | |
4465 | dev_priv->bsd_ring.gem_object == NULL)) { | |
29105ccc CW |
4466 | mutex_unlock(&dev->struct_mutex); |
4467 | return 0; | |
28dfe52a EA |
4468 | } |
4469 | ||
29105ccc | 4470 | ret = i915_gpu_idle(dev); |
6dbe2772 KP |
4471 | if (ret) { |
4472 | mutex_unlock(&dev->struct_mutex); | |
673a394b | 4473 | return ret; |
6dbe2772 | 4474 | } |
673a394b | 4475 | |
29105ccc CW |
4476 | /* Under UMS, be paranoid and evict. */ |
4477 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) { | |
b47eb4a2 | 4478 | ret = i915_gem_evict_inactive(dev); |
29105ccc CW |
4479 | if (ret) { |
4480 | mutex_unlock(&dev->struct_mutex); | |
4481 | return ret; | |
4482 | } | |
4483 | } | |
4484 | ||
4485 | /* Hack! Don't let anybody do execbuf while we don't control the chip. | |
4486 | * We need to replace this with a semaphore, or something. | |
4487 | * And not confound mm.suspended! | |
4488 | */ | |
4489 | dev_priv->mm.suspended = 1; | |
bc0c7f14 | 4490 | del_timer_sync(&dev_priv->hangcheck_timer); |
29105ccc CW |
4491 | |
4492 | i915_kernel_lost_context(dev); | |
6dbe2772 | 4493 | i915_gem_cleanup_ringbuffer(dev); |
29105ccc | 4494 | |
6dbe2772 KP |
4495 | mutex_unlock(&dev->struct_mutex); |
4496 | ||
29105ccc CW |
4497 | /* Cancel the retire work handler, which should be idle now. */ |
4498 | cancel_delayed_work_sync(&dev_priv->mm.retire_work); | |
4499 | ||
673a394b EA |
4500 | return 0; |
4501 | } | |
4502 | ||
e552eb70 JB |
4503 | /* |
4504 | * 965+ support PIPE_CONTROL commands, which provide finer grained control | |
4505 | * over cache flushing. | |
4506 | */ | |
8187a2b7 | 4507 | static int |
e552eb70 JB |
4508 | i915_gem_init_pipe_control(struct drm_device *dev) |
4509 | { | |
4510 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4511 | struct drm_gem_object *obj; | |
4512 | struct drm_i915_gem_object *obj_priv; | |
4513 | int ret; | |
4514 | ||
34dc4d44 | 4515 | obj = i915_gem_alloc_object(dev, 4096); |
e552eb70 JB |
4516 | if (obj == NULL) { |
4517 | DRM_ERROR("Failed to allocate seqno page\n"); | |
4518 | ret = -ENOMEM; | |
4519 | goto err; | |
4520 | } | |
4521 | obj_priv = to_intel_bo(obj); | |
4522 | obj_priv->agp_type = AGP_USER_CACHED_MEMORY; | |
4523 | ||
4524 | ret = i915_gem_object_pin(obj, 4096); | |
4525 | if (ret) | |
4526 | goto err_unref; | |
4527 | ||
4528 | dev_priv->seqno_gfx_addr = obj_priv->gtt_offset; | |
4529 | dev_priv->seqno_page = kmap(obj_priv->pages[0]); | |
4530 | if (dev_priv->seqno_page == NULL) | |
4531 | goto err_unpin; | |
4532 | ||
4533 | dev_priv->seqno_obj = obj; | |
4534 | memset(dev_priv->seqno_page, 0, PAGE_SIZE); | |
4535 | ||
4536 | return 0; | |
4537 | ||
4538 | err_unpin: | |
4539 | i915_gem_object_unpin(obj); | |
4540 | err_unref: | |
4541 | drm_gem_object_unreference(obj); | |
4542 | err: | |
4543 | return ret; | |
4544 | } | |
4545 | ||
8187a2b7 ZN |
4546 | |
4547 | static void | |
e552eb70 JB |
4548 | i915_gem_cleanup_pipe_control(struct drm_device *dev) |
4549 | { | |
4550 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4551 | struct drm_gem_object *obj; | |
4552 | struct drm_i915_gem_object *obj_priv; | |
4553 | ||
4554 | obj = dev_priv->seqno_obj; | |
4555 | obj_priv = to_intel_bo(obj); | |
4556 | kunmap(obj_priv->pages[0]); | |
4557 | i915_gem_object_unpin(obj); | |
4558 | drm_gem_object_unreference(obj); | |
4559 | dev_priv->seqno_obj = NULL; | |
4560 | ||
4561 | dev_priv->seqno_page = NULL; | |
673a394b EA |
4562 | } |
4563 | ||
8187a2b7 ZN |
4564 | int |
4565 | i915_gem_init_ringbuffer(struct drm_device *dev) | |
4566 | { | |
4567 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4568 | int ret; | |
68f95ba9 | 4569 | |
8187a2b7 ZN |
4570 | if (HAS_PIPE_CONTROL(dev)) { |
4571 | ret = i915_gem_init_pipe_control(dev); | |
4572 | if (ret) | |
4573 | return ret; | |
4574 | } | |
68f95ba9 | 4575 | |
5c1143bb | 4576 | ret = intel_init_render_ring_buffer(dev); |
68f95ba9 CW |
4577 | if (ret) |
4578 | goto cleanup_pipe_control; | |
4579 | ||
4580 | if (HAS_BSD(dev)) { | |
5c1143bb | 4581 | ret = intel_init_bsd_ring_buffer(dev); |
68f95ba9 CW |
4582 | if (ret) |
4583 | goto cleanup_render_ring; | |
d1b851fc | 4584 | } |
68f95ba9 | 4585 | |
6f392d54 CW |
4586 | dev_priv->next_seqno = 1; |
4587 | ||
68f95ba9 CW |
4588 | return 0; |
4589 | ||
4590 | cleanup_render_ring: | |
4591 | intel_cleanup_ring_buffer(dev, &dev_priv->render_ring); | |
4592 | cleanup_pipe_control: | |
4593 | if (HAS_PIPE_CONTROL(dev)) | |
4594 | i915_gem_cleanup_pipe_control(dev); | |
8187a2b7 ZN |
4595 | return ret; |
4596 | } | |
4597 | ||
4598 | void | |
4599 | i915_gem_cleanup_ringbuffer(struct drm_device *dev) | |
4600 | { | |
4601 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4602 | ||
4603 | intel_cleanup_ring_buffer(dev, &dev_priv->render_ring); | |
d1b851fc ZN |
4604 | if (HAS_BSD(dev)) |
4605 | intel_cleanup_ring_buffer(dev, &dev_priv->bsd_ring); | |
8187a2b7 ZN |
4606 | if (HAS_PIPE_CONTROL(dev)) |
4607 | i915_gem_cleanup_pipe_control(dev); | |
4608 | } | |
4609 | ||
673a394b EA |
4610 | int |
4611 | i915_gem_entervt_ioctl(struct drm_device *dev, void *data, | |
4612 | struct drm_file *file_priv) | |
4613 | { | |
4614 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4615 | int ret; | |
4616 | ||
79e53945 JB |
4617 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
4618 | return 0; | |
4619 | ||
ba1234d1 | 4620 | if (atomic_read(&dev_priv->mm.wedged)) { |
673a394b | 4621 | DRM_ERROR("Reenabling wedged hardware, good luck\n"); |
ba1234d1 | 4622 | atomic_set(&dev_priv->mm.wedged, 0); |
673a394b EA |
4623 | } |
4624 | ||
673a394b | 4625 | mutex_lock(&dev->struct_mutex); |
9bb2d6f9 EA |
4626 | dev_priv->mm.suspended = 0; |
4627 | ||
4628 | ret = i915_gem_init_ringbuffer(dev); | |
d816f6ac WF |
4629 | if (ret != 0) { |
4630 | mutex_unlock(&dev->struct_mutex); | |
9bb2d6f9 | 4631 | return ret; |
d816f6ac | 4632 | } |
9bb2d6f9 | 4633 | |
852835f3 | 4634 | BUG_ON(!list_empty(&dev_priv->render_ring.active_list)); |
d1b851fc | 4635 | BUG_ON(HAS_BSD(dev) && !list_empty(&dev_priv->bsd_ring.active_list)); |
673a394b EA |
4636 | BUG_ON(!list_empty(&dev_priv->mm.flushing_list)); |
4637 | BUG_ON(!list_empty(&dev_priv->mm.inactive_list)); | |
852835f3 | 4638 | BUG_ON(!list_empty(&dev_priv->render_ring.request_list)); |
d1b851fc | 4639 | BUG_ON(HAS_BSD(dev) && !list_empty(&dev_priv->bsd_ring.request_list)); |
673a394b | 4640 | mutex_unlock(&dev->struct_mutex); |
dbb19d30 | 4641 | |
5f35308b CW |
4642 | ret = drm_irq_install(dev); |
4643 | if (ret) | |
4644 | goto cleanup_ringbuffer; | |
dbb19d30 | 4645 | |
673a394b | 4646 | return 0; |
5f35308b CW |
4647 | |
4648 | cleanup_ringbuffer: | |
4649 | mutex_lock(&dev->struct_mutex); | |
4650 | i915_gem_cleanup_ringbuffer(dev); | |
4651 | dev_priv->mm.suspended = 1; | |
4652 | mutex_unlock(&dev->struct_mutex); | |
4653 | ||
4654 | return ret; | |
673a394b EA |
4655 | } |
4656 | ||
4657 | int | |
4658 | i915_gem_leavevt_ioctl(struct drm_device *dev, void *data, | |
4659 | struct drm_file *file_priv) | |
4660 | { | |
79e53945 JB |
4661 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
4662 | return 0; | |
4663 | ||
dbb19d30 | 4664 | drm_irq_uninstall(dev); |
e6890f6f | 4665 | return i915_gem_idle(dev); |
673a394b EA |
4666 | } |
4667 | ||
4668 | void | |
4669 | i915_gem_lastclose(struct drm_device *dev) | |
4670 | { | |
4671 | int ret; | |
673a394b | 4672 | |
e806b495 EA |
4673 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
4674 | return; | |
4675 | ||
6dbe2772 KP |
4676 | ret = i915_gem_idle(dev); |
4677 | if (ret) | |
4678 | DRM_ERROR("failed to idle hardware: %d\n", ret); | |
673a394b EA |
4679 | } |
4680 | ||
4681 | void | |
4682 | i915_gem_load(struct drm_device *dev) | |
4683 | { | |
b5aa8a0f | 4684 | int i; |
673a394b EA |
4685 | drm_i915_private_t *dev_priv = dev->dev_private; |
4686 | ||
673a394b | 4687 | INIT_LIST_HEAD(&dev_priv->mm.flushing_list); |
99fcb766 | 4688 | INIT_LIST_HEAD(&dev_priv->mm.gpu_write_list); |
673a394b | 4689 | INIT_LIST_HEAD(&dev_priv->mm.inactive_list); |
f13d3f73 | 4690 | INIT_LIST_HEAD(&dev_priv->mm.pinned_list); |
a09ba7fa | 4691 | INIT_LIST_HEAD(&dev_priv->mm.fence_list); |
be72615b | 4692 | INIT_LIST_HEAD(&dev_priv->mm.deferred_free_list); |
852835f3 ZN |
4693 | INIT_LIST_HEAD(&dev_priv->render_ring.active_list); |
4694 | INIT_LIST_HEAD(&dev_priv->render_ring.request_list); | |
d1b851fc ZN |
4695 | if (HAS_BSD(dev)) { |
4696 | INIT_LIST_HEAD(&dev_priv->bsd_ring.active_list); | |
4697 | INIT_LIST_HEAD(&dev_priv->bsd_ring.request_list); | |
4698 | } | |
007cc8ac DV |
4699 | for (i = 0; i < 16; i++) |
4700 | INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list); | |
673a394b EA |
4701 | INIT_DELAYED_WORK(&dev_priv->mm.retire_work, |
4702 | i915_gem_retire_work_handler); | |
30dbf0c0 | 4703 | init_completion(&dev_priv->error_completion); |
31169714 CW |
4704 | spin_lock(&shrink_list_lock); |
4705 | list_add(&dev_priv->mm.shrink_list, &shrink_list); | |
4706 | spin_unlock(&shrink_list_lock); | |
4707 | ||
94400120 DA |
4708 | /* On GEN3 we really need to make sure the ARB C3 LP bit is set */ |
4709 | if (IS_GEN3(dev)) { | |
4710 | u32 tmp = I915_READ(MI_ARB_STATE); | |
4711 | if (!(tmp & MI_ARB_C3_LP_WRITE_ENABLE)) { | |
4712 | /* arb state is a masked write, so set bit + bit in mask */ | |
4713 | tmp = MI_ARB_C3_LP_WRITE_ENABLE | (MI_ARB_C3_LP_WRITE_ENABLE << MI_ARB_MASK_SHIFT); | |
4714 | I915_WRITE(MI_ARB_STATE, tmp); | |
4715 | } | |
4716 | } | |
4717 | ||
de151cf6 | 4718 | /* Old X drivers will take 0-2 for front, back, depth buffers */ |
b397c836 EA |
4719 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) |
4720 | dev_priv->fence_reg_start = 3; | |
de151cf6 | 4721 | |
a6c45cf0 | 4722 | if (INTEL_INFO(dev)->gen >= 4 || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) |
de151cf6 JB |
4723 | dev_priv->num_fence_regs = 16; |
4724 | else | |
4725 | dev_priv->num_fence_regs = 8; | |
4726 | ||
b5aa8a0f | 4727 | /* Initialize fence registers to zero */ |
a6c45cf0 CW |
4728 | switch (INTEL_INFO(dev)->gen) { |
4729 | case 6: | |
4730 | for (i = 0; i < 16; i++) | |
4731 | I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + (i * 8), 0); | |
4732 | break; | |
4733 | case 5: | |
4734 | case 4: | |
b5aa8a0f GH |
4735 | for (i = 0; i < 16; i++) |
4736 | I915_WRITE64(FENCE_REG_965_0 + (i * 8), 0); | |
a6c45cf0 CW |
4737 | break; |
4738 | case 3: | |
b5aa8a0f GH |
4739 | if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) |
4740 | for (i = 0; i < 8; i++) | |
4741 | I915_WRITE(FENCE_REG_945_8 + (i * 4), 0); | |
a6c45cf0 CW |
4742 | case 2: |
4743 | for (i = 0; i < 8; i++) | |
4744 | I915_WRITE(FENCE_REG_830_0 + (i * 4), 0); | |
4745 | break; | |
b5aa8a0f | 4746 | } |
673a394b | 4747 | i915_gem_detect_bit_6_swizzle(dev); |
6b95a207 | 4748 | init_waitqueue_head(&dev_priv->pending_flip_queue); |
673a394b | 4749 | } |
71acb5eb DA |
4750 | |
4751 | /* | |
4752 | * Create a physically contiguous memory object for this object | |
4753 | * e.g. for cursor + overlay regs | |
4754 | */ | |
995b6762 CW |
4755 | static int i915_gem_init_phys_object(struct drm_device *dev, |
4756 | int id, int size, int align) | |
71acb5eb DA |
4757 | { |
4758 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4759 | struct drm_i915_gem_phys_object *phys_obj; | |
4760 | int ret; | |
4761 | ||
4762 | if (dev_priv->mm.phys_objs[id - 1] || !size) | |
4763 | return 0; | |
4764 | ||
9a298b2a | 4765 | phys_obj = kzalloc(sizeof(struct drm_i915_gem_phys_object), GFP_KERNEL); |
71acb5eb DA |
4766 | if (!phys_obj) |
4767 | return -ENOMEM; | |
4768 | ||
4769 | phys_obj->id = id; | |
4770 | ||
6eeefaf3 | 4771 | phys_obj->handle = drm_pci_alloc(dev, size, align); |
71acb5eb DA |
4772 | if (!phys_obj->handle) { |
4773 | ret = -ENOMEM; | |
4774 | goto kfree_obj; | |
4775 | } | |
4776 | #ifdef CONFIG_X86 | |
4777 | set_memory_wc((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE); | |
4778 | #endif | |
4779 | ||
4780 | dev_priv->mm.phys_objs[id - 1] = phys_obj; | |
4781 | ||
4782 | return 0; | |
4783 | kfree_obj: | |
9a298b2a | 4784 | kfree(phys_obj); |
71acb5eb DA |
4785 | return ret; |
4786 | } | |
4787 | ||
995b6762 | 4788 | static void i915_gem_free_phys_object(struct drm_device *dev, int id) |
71acb5eb DA |
4789 | { |
4790 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4791 | struct drm_i915_gem_phys_object *phys_obj; | |
4792 | ||
4793 | if (!dev_priv->mm.phys_objs[id - 1]) | |
4794 | return; | |
4795 | ||
4796 | phys_obj = dev_priv->mm.phys_objs[id - 1]; | |
4797 | if (phys_obj->cur_obj) { | |
4798 | i915_gem_detach_phys_object(dev, phys_obj->cur_obj); | |
4799 | } | |
4800 | ||
4801 | #ifdef CONFIG_X86 | |
4802 | set_memory_wb((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE); | |
4803 | #endif | |
4804 | drm_pci_free(dev, phys_obj->handle); | |
4805 | kfree(phys_obj); | |
4806 | dev_priv->mm.phys_objs[id - 1] = NULL; | |
4807 | } | |
4808 | ||
4809 | void i915_gem_free_all_phys_object(struct drm_device *dev) | |
4810 | { | |
4811 | int i; | |
4812 | ||
260883c8 | 4813 | for (i = I915_GEM_PHYS_CURSOR_0; i <= I915_MAX_PHYS_OBJECT; i++) |
71acb5eb DA |
4814 | i915_gem_free_phys_object(dev, i); |
4815 | } | |
4816 | ||
4817 | void i915_gem_detach_phys_object(struct drm_device *dev, | |
4818 | struct drm_gem_object *obj) | |
4819 | { | |
4820 | struct drm_i915_gem_object *obj_priv; | |
4821 | int i; | |
4822 | int ret; | |
4823 | int page_count; | |
4824 | ||
23010e43 | 4825 | obj_priv = to_intel_bo(obj); |
71acb5eb DA |
4826 | if (!obj_priv->phys_obj) |
4827 | return; | |
4828 | ||
4bdadb97 | 4829 | ret = i915_gem_object_get_pages(obj, 0); |
71acb5eb DA |
4830 | if (ret) |
4831 | goto out; | |
4832 | ||
4833 | page_count = obj->size / PAGE_SIZE; | |
4834 | ||
4835 | for (i = 0; i < page_count; i++) { | |
856fa198 | 4836 | char *dst = kmap_atomic(obj_priv->pages[i], KM_USER0); |
71acb5eb DA |
4837 | char *src = obj_priv->phys_obj->handle->vaddr + (i * PAGE_SIZE); |
4838 | ||
4839 | memcpy(dst, src, PAGE_SIZE); | |
4840 | kunmap_atomic(dst, KM_USER0); | |
4841 | } | |
856fa198 | 4842 | drm_clflush_pages(obj_priv->pages, page_count); |
71acb5eb | 4843 | drm_agp_chipset_flush(dev); |
d78b47b9 CW |
4844 | |
4845 | i915_gem_object_put_pages(obj); | |
71acb5eb DA |
4846 | out: |
4847 | obj_priv->phys_obj->cur_obj = NULL; | |
4848 | obj_priv->phys_obj = NULL; | |
4849 | } | |
4850 | ||
4851 | int | |
4852 | i915_gem_attach_phys_object(struct drm_device *dev, | |
6eeefaf3 CW |
4853 | struct drm_gem_object *obj, |
4854 | int id, | |
4855 | int align) | |
71acb5eb DA |
4856 | { |
4857 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4858 | struct drm_i915_gem_object *obj_priv; | |
4859 | int ret = 0; | |
4860 | int page_count; | |
4861 | int i; | |
4862 | ||
4863 | if (id > I915_MAX_PHYS_OBJECT) | |
4864 | return -EINVAL; | |
4865 | ||
23010e43 | 4866 | obj_priv = to_intel_bo(obj); |
71acb5eb DA |
4867 | |
4868 | if (obj_priv->phys_obj) { | |
4869 | if (obj_priv->phys_obj->id == id) | |
4870 | return 0; | |
4871 | i915_gem_detach_phys_object(dev, obj); | |
4872 | } | |
4873 | ||
71acb5eb DA |
4874 | /* create a new object */ |
4875 | if (!dev_priv->mm.phys_objs[id - 1]) { | |
4876 | ret = i915_gem_init_phys_object(dev, id, | |
6eeefaf3 | 4877 | obj->size, align); |
71acb5eb | 4878 | if (ret) { |
aeb565df | 4879 | DRM_ERROR("failed to init phys object %d size: %zu\n", id, obj->size); |
71acb5eb DA |
4880 | goto out; |
4881 | } | |
4882 | } | |
4883 | ||
4884 | /* bind to the object */ | |
4885 | obj_priv->phys_obj = dev_priv->mm.phys_objs[id - 1]; | |
4886 | obj_priv->phys_obj->cur_obj = obj; | |
4887 | ||
4bdadb97 | 4888 | ret = i915_gem_object_get_pages(obj, 0); |
71acb5eb DA |
4889 | if (ret) { |
4890 | DRM_ERROR("failed to get page list\n"); | |
4891 | goto out; | |
4892 | } | |
4893 | ||
4894 | page_count = obj->size / PAGE_SIZE; | |
4895 | ||
4896 | for (i = 0; i < page_count; i++) { | |
856fa198 | 4897 | char *src = kmap_atomic(obj_priv->pages[i], KM_USER0); |
71acb5eb DA |
4898 | char *dst = obj_priv->phys_obj->handle->vaddr + (i * PAGE_SIZE); |
4899 | ||
4900 | memcpy(dst, src, PAGE_SIZE); | |
4901 | kunmap_atomic(src, KM_USER0); | |
4902 | } | |
4903 | ||
d78b47b9 CW |
4904 | i915_gem_object_put_pages(obj); |
4905 | ||
71acb5eb DA |
4906 | return 0; |
4907 | out: | |
4908 | return ret; | |
4909 | } | |
4910 | ||
4911 | static int | |
4912 | i915_gem_phys_pwrite(struct drm_device *dev, struct drm_gem_object *obj, | |
4913 | struct drm_i915_gem_pwrite *args, | |
4914 | struct drm_file *file_priv) | |
4915 | { | |
23010e43 | 4916 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
71acb5eb DA |
4917 | void *obj_addr; |
4918 | int ret; | |
4919 | char __user *user_data; | |
4920 | ||
4921 | user_data = (char __user *) (uintptr_t) args->data_ptr; | |
4922 | obj_addr = obj_priv->phys_obj->handle->vaddr + args->offset; | |
4923 | ||
44d98a61 | 4924 | DRM_DEBUG_DRIVER("obj_addr %p, %lld\n", obj_addr, args->size); |
71acb5eb DA |
4925 | ret = copy_from_user(obj_addr, user_data, args->size); |
4926 | if (ret) | |
4927 | return -EFAULT; | |
4928 | ||
4929 | drm_agp_chipset_flush(dev); | |
4930 | return 0; | |
4931 | } | |
b962442e | 4932 | |
f787a5f5 | 4933 | void i915_gem_release(struct drm_device *dev, struct drm_file *file) |
b962442e | 4934 | { |
f787a5f5 | 4935 | struct drm_i915_file_private *file_priv = file->driver_priv; |
b962442e EA |
4936 | |
4937 | /* Clean up our request list when the client is going away, so that | |
4938 | * later retire_requests won't dereference our soon-to-be-gone | |
4939 | * file_priv. | |
4940 | */ | |
1c25595f | 4941 | spin_lock(&file_priv->mm.lock); |
f787a5f5 CW |
4942 | while (!list_empty(&file_priv->mm.request_list)) { |
4943 | struct drm_i915_gem_request *request; | |
4944 | ||
4945 | request = list_first_entry(&file_priv->mm.request_list, | |
4946 | struct drm_i915_gem_request, | |
4947 | client_list); | |
4948 | list_del(&request->client_list); | |
4949 | request->file_priv = NULL; | |
4950 | } | |
1c25595f | 4951 | spin_unlock(&file_priv->mm.lock); |
b962442e | 4952 | } |
31169714 | 4953 | |
1637ef41 CW |
4954 | static int |
4955 | i915_gpu_is_active(struct drm_device *dev) | |
4956 | { | |
4957 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4958 | int lists_empty; | |
4959 | ||
1637ef41 | 4960 | lists_empty = list_empty(&dev_priv->mm.flushing_list) && |
852835f3 | 4961 | list_empty(&dev_priv->render_ring.active_list); |
d1b851fc ZN |
4962 | if (HAS_BSD(dev)) |
4963 | lists_empty &= list_empty(&dev_priv->bsd_ring.active_list); | |
1637ef41 CW |
4964 | |
4965 | return !lists_empty; | |
4966 | } | |
4967 | ||
31169714 | 4968 | static int |
7f8275d0 | 4969 | i915_gem_shrink(struct shrinker *shrink, int nr_to_scan, gfp_t gfp_mask) |
31169714 CW |
4970 | { |
4971 | drm_i915_private_t *dev_priv, *next_dev; | |
4972 | struct drm_i915_gem_object *obj_priv, *next_obj; | |
4973 | int cnt = 0; | |
4974 | int would_deadlock = 1; | |
4975 | ||
4976 | /* "fast-path" to count number of available objects */ | |
4977 | if (nr_to_scan == 0) { | |
4978 | spin_lock(&shrink_list_lock); | |
4979 | list_for_each_entry(dev_priv, &shrink_list, mm.shrink_list) { | |
4980 | struct drm_device *dev = dev_priv->dev; | |
4981 | ||
4982 | if (mutex_trylock(&dev->struct_mutex)) { | |
4983 | list_for_each_entry(obj_priv, | |
4984 | &dev_priv->mm.inactive_list, | |
4985 | list) | |
4986 | cnt++; | |
4987 | mutex_unlock(&dev->struct_mutex); | |
4988 | } | |
4989 | } | |
4990 | spin_unlock(&shrink_list_lock); | |
4991 | ||
4992 | return (cnt / 100) * sysctl_vfs_cache_pressure; | |
4993 | } | |
4994 | ||
4995 | spin_lock(&shrink_list_lock); | |
4996 | ||
1637ef41 | 4997 | rescan: |
31169714 CW |
4998 | /* first scan for clean buffers */ |
4999 | list_for_each_entry_safe(dev_priv, next_dev, | |
5000 | &shrink_list, mm.shrink_list) { | |
5001 | struct drm_device *dev = dev_priv->dev; | |
5002 | ||
5003 | if (! mutex_trylock(&dev->struct_mutex)) | |
5004 | continue; | |
5005 | ||
5006 | spin_unlock(&shrink_list_lock); | |
b09a1fec | 5007 | i915_gem_retire_requests(dev); |
31169714 CW |
5008 | |
5009 | list_for_each_entry_safe(obj_priv, next_obj, | |
5010 | &dev_priv->mm.inactive_list, | |
5011 | list) { | |
5012 | if (i915_gem_object_is_purgeable(obj_priv)) { | |
a8089e84 | 5013 | i915_gem_object_unbind(&obj_priv->base); |
31169714 CW |
5014 | if (--nr_to_scan <= 0) |
5015 | break; | |
5016 | } | |
5017 | } | |
5018 | ||
5019 | spin_lock(&shrink_list_lock); | |
5020 | mutex_unlock(&dev->struct_mutex); | |
5021 | ||
963b4836 CW |
5022 | would_deadlock = 0; |
5023 | ||
31169714 CW |
5024 | if (nr_to_scan <= 0) |
5025 | break; | |
5026 | } | |
5027 | ||
5028 | /* second pass, evict/count anything still on the inactive list */ | |
5029 | list_for_each_entry_safe(dev_priv, next_dev, | |
5030 | &shrink_list, mm.shrink_list) { | |
5031 | struct drm_device *dev = dev_priv->dev; | |
5032 | ||
5033 | if (! mutex_trylock(&dev->struct_mutex)) | |
5034 | continue; | |
5035 | ||
5036 | spin_unlock(&shrink_list_lock); | |
5037 | ||
5038 | list_for_each_entry_safe(obj_priv, next_obj, | |
5039 | &dev_priv->mm.inactive_list, | |
5040 | list) { | |
5041 | if (nr_to_scan > 0) { | |
a8089e84 | 5042 | i915_gem_object_unbind(&obj_priv->base); |
31169714 CW |
5043 | nr_to_scan--; |
5044 | } else | |
5045 | cnt++; | |
5046 | } | |
5047 | ||
5048 | spin_lock(&shrink_list_lock); | |
5049 | mutex_unlock(&dev->struct_mutex); | |
5050 | ||
5051 | would_deadlock = 0; | |
5052 | } | |
5053 | ||
1637ef41 CW |
5054 | if (nr_to_scan) { |
5055 | int active = 0; | |
5056 | ||
5057 | /* | |
5058 | * We are desperate for pages, so as a last resort, wait | |
5059 | * for the GPU to finish and discard whatever we can. | |
5060 | * This has a dramatic impact to reduce the number of | |
5061 | * OOM-killer events whilst running the GPU aggressively. | |
5062 | */ | |
5063 | list_for_each_entry(dev_priv, &shrink_list, mm.shrink_list) { | |
5064 | struct drm_device *dev = dev_priv->dev; | |
5065 | ||
5066 | if (!mutex_trylock(&dev->struct_mutex)) | |
5067 | continue; | |
5068 | ||
5069 | spin_unlock(&shrink_list_lock); | |
5070 | ||
5071 | if (i915_gpu_is_active(dev)) { | |
5072 | i915_gpu_idle(dev); | |
5073 | active++; | |
5074 | } | |
5075 | ||
5076 | spin_lock(&shrink_list_lock); | |
5077 | mutex_unlock(&dev->struct_mutex); | |
5078 | } | |
5079 | ||
5080 | if (active) | |
5081 | goto rescan; | |
5082 | } | |
5083 | ||
31169714 CW |
5084 | spin_unlock(&shrink_list_lock); |
5085 | ||
5086 | if (would_deadlock) | |
5087 | return -1; | |
5088 | else if (cnt > 0) | |
5089 | return (cnt / 100) * sysctl_vfs_cache_pressure; | |
5090 | else | |
5091 | return 0; | |
5092 | } | |
5093 | ||
5094 | static struct shrinker shrinker = { | |
5095 | .shrink = i915_gem_shrink, | |
5096 | .seeks = DEFAULT_SEEKS, | |
5097 | }; | |
5098 | ||
5099 | __init void | |
5100 | i915_gem_shrinker_init(void) | |
5101 | { | |
5102 | register_shrinker(&shrinker); | |
5103 | } | |
5104 | ||
5105 | __exit void | |
5106 | i915_gem_shrinker_exit(void) | |
5107 | { | |
5108 | unregister_shrinker(&shrinker); | |
5109 | } |