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Commit | Line | Data |
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673a394b EA |
1 | /* |
2 | * Copyright © 2008 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | * | |
26 | */ | |
27 | ||
760285e7 | 28 | #include <drm/drmP.h> |
0de23977 | 29 | #include <drm/drm_vma_manager.h> |
760285e7 | 30 | #include <drm/i915_drm.h> |
673a394b | 31 | #include "i915_drv.h" |
1c5d22f7 | 32 | #include "i915_trace.h" |
652c393a | 33 | #include "intel_drv.h" |
2cfcd32a | 34 | #include <linux/oom.h> |
5949eac4 | 35 | #include <linux/shmem_fs.h> |
5a0e3ad6 | 36 | #include <linux/slab.h> |
673a394b | 37 | #include <linux/swap.h> |
79e53945 | 38 | #include <linux/pci.h> |
1286ff73 | 39 | #include <linux/dma-buf.h> |
673a394b | 40 | |
05394f39 | 41 | static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj); |
e62b59e4 | 42 | static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj); |
07fe0b12 | 43 | static __must_check int |
23f54483 BW |
44 | i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj, |
45 | bool readonly); | |
c8725f3d CW |
46 | static void |
47 | i915_gem_object_retire(struct drm_i915_gem_object *obj); | |
48 | ||
61050808 CW |
49 | static void i915_gem_write_fence(struct drm_device *dev, int reg, |
50 | struct drm_i915_gem_object *obj); | |
51 | static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj, | |
52 | struct drm_i915_fence_reg *fence, | |
53 | bool enable); | |
54 | ||
ceabbba5 | 55 | static unsigned long i915_gem_shrinker_count(struct shrinker *shrinker, |
7dc19d5a | 56 | struct shrink_control *sc); |
ceabbba5 | 57 | static unsigned long i915_gem_shrinker_scan(struct shrinker *shrinker, |
7dc19d5a | 58 | struct shrink_control *sc); |
2cfcd32a CW |
59 | static int i915_gem_shrinker_oom(struct notifier_block *nb, |
60 | unsigned long event, | |
61 | void *ptr); | |
d9973b43 | 62 | static unsigned long i915_gem_shrink_all(struct drm_i915_private *dev_priv); |
31169714 | 63 | |
c76ce038 CW |
64 | static bool cpu_cache_is_coherent(struct drm_device *dev, |
65 | enum i915_cache_level level) | |
66 | { | |
67 | return HAS_LLC(dev) || level != I915_CACHE_NONE; | |
68 | } | |
69 | ||
2c22569b CW |
70 | static bool cpu_write_needs_clflush(struct drm_i915_gem_object *obj) |
71 | { | |
72 | if (!cpu_cache_is_coherent(obj->base.dev, obj->cache_level)) | |
73 | return true; | |
74 | ||
75 | return obj->pin_display; | |
76 | } | |
77 | ||
61050808 CW |
78 | static inline void i915_gem_object_fence_lost(struct drm_i915_gem_object *obj) |
79 | { | |
80 | if (obj->tiling_mode) | |
81 | i915_gem_release_mmap(obj); | |
82 | ||
83 | /* As we do not have an associated fence register, we will force | |
84 | * a tiling change if we ever need to acquire one. | |
85 | */ | |
5d82e3e6 | 86 | obj->fence_dirty = false; |
61050808 CW |
87 | obj->fence_reg = I915_FENCE_REG_NONE; |
88 | } | |
89 | ||
73aa808f CW |
90 | /* some bookkeeping */ |
91 | static void i915_gem_info_add_obj(struct drm_i915_private *dev_priv, | |
92 | size_t size) | |
93 | { | |
c20e8355 | 94 | spin_lock(&dev_priv->mm.object_stat_lock); |
73aa808f CW |
95 | dev_priv->mm.object_count++; |
96 | dev_priv->mm.object_memory += size; | |
c20e8355 | 97 | spin_unlock(&dev_priv->mm.object_stat_lock); |
73aa808f CW |
98 | } |
99 | ||
100 | static void i915_gem_info_remove_obj(struct drm_i915_private *dev_priv, | |
101 | size_t size) | |
102 | { | |
c20e8355 | 103 | spin_lock(&dev_priv->mm.object_stat_lock); |
73aa808f CW |
104 | dev_priv->mm.object_count--; |
105 | dev_priv->mm.object_memory -= size; | |
c20e8355 | 106 | spin_unlock(&dev_priv->mm.object_stat_lock); |
73aa808f CW |
107 | } |
108 | ||
21dd3734 | 109 | static int |
33196ded | 110 | i915_gem_wait_for_error(struct i915_gpu_error *error) |
30dbf0c0 | 111 | { |
30dbf0c0 CW |
112 | int ret; |
113 | ||
7abb690a DV |
114 | #define EXIT_COND (!i915_reset_in_progress(error) || \ |
115 | i915_terminally_wedged(error)) | |
1f83fee0 | 116 | if (EXIT_COND) |
30dbf0c0 CW |
117 | return 0; |
118 | ||
0a6759c6 DV |
119 | /* |
120 | * Only wait 10 seconds for the gpu reset to complete to avoid hanging | |
121 | * userspace. If it takes that long something really bad is going on and | |
122 | * we should simply try to bail out and fail as gracefully as possible. | |
123 | */ | |
1f83fee0 DV |
124 | ret = wait_event_interruptible_timeout(error->reset_queue, |
125 | EXIT_COND, | |
126 | 10*HZ); | |
0a6759c6 DV |
127 | if (ret == 0) { |
128 | DRM_ERROR("Timed out waiting for the gpu reset to complete\n"); | |
129 | return -EIO; | |
130 | } else if (ret < 0) { | |
30dbf0c0 | 131 | return ret; |
0a6759c6 | 132 | } |
1f83fee0 | 133 | #undef EXIT_COND |
30dbf0c0 | 134 | |
21dd3734 | 135 | return 0; |
30dbf0c0 CW |
136 | } |
137 | ||
54cf91dc | 138 | int i915_mutex_lock_interruptible(struct drm_device *dev) |
76c1dec1 | 139 | { |
33196ded | 140 | struct drm_i915_private *dev_priv = dev->dev_private; |
76c1dec1 CW |
141 | int ret; |
142 | ||
33196ded | 143 | ret = i915_gem_wait_for_error(&dev_priv->gpu_error); |
76c1dec1 CW |
144 | if (ret) |
145 | return ret; | |
146 | ||
147 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
148 | if (ret) | |
149 | return ret; | |
150 | ||
23bc5982 | 151 | WARN_ON(i915_verify_lists(dev)); |
76c1dec1 CW |
152 | return 0; |
153 | } | |
30dbf0c0 | 154 | |
5a125c3c EA |
155 | int |
156 | i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 157 | struct drm_file *file) |
5a125c3c | 158 | { |
73aa808f | 159 | struct drm_i915_private *dev_priv = dev->dev_private; |
5a125c3c | 160 | struct drm_i915_gem_get_aperture *args = data; |
6299f992 CW |
161 | struct drm_i915_gem_object *obj; |
162 | size_t pinned; | |
5a125c3c | 163 | |
6299f992 | 164 | pinned = 0; |
73aa808f | 165 | mutex_lock(&dev->struct_mutex); |
35c20a60 | 166 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) |
d7f46fc4 | 167 | if (i915_gem_obj_is_pinned(obj)) |
f343c5f6 | 168 | pinned += i915_gem_obj_ggtt_size(obj); |
73aa808f | 169 | mutex_unlock(&dev->struct_mutex); |
5a125c3c | 170 | |
853ba5d2 | 171 | args->aper_size = dev_priv->gtt.base.total; |
0206e353 | 172 | args->aper_available_size = args->aper_size - pinned; |
6299f992 | 173 | |
5a125c3c EA |
174 | return 0; |
175 | } | |
176 | ||
6a2c4232 CW |
177 | static int |
178 | i915_gem_object_get_pages_phys(struct drm_i915_gem_object *obj) | |
00731155 | 179 | { |
6a2c4232 CW |
180 | struct address_space *mapping = file_inode(obj->base.filp)->i_mapping; |
181 | char *vaddr = obj->phys_handle->vaddr; | |
182 | struct sg_table *st; | |
183 | struct scatterlist *sg; | |
184 | int i; | |
00731155 | 185 | |
6a2c4232 CW |
186 | if (WARN_ON(i915_gem_object_needs_bit17_swizzle(obj))) |
187 | return -EINVAL; | |
188 | ||
189 | for (i = 0; i < obj->base.size / PAGE_SIZE; i++) { | |
190 | struct page *page; | |
191 | char *src; | |
192 | ||
193 | page = shmem_read_mapping_page(mapping, i); | |
194 | if (IS_ERR(page)) | |
195 | return PTR_ERR(page); | |
196 | ||
197 | src = kmap_atomic(page); | |
198 | memcpy(vaddr, src, PAGE_SIZE); | |
199 | drm_clflush_virt_range(vaddr, PAGE_SIZE); | |
200 | kunmap_atomic(src); | |
201 | ||
202 | page_cache_release(page); | |
203 | vaddr += PAGE_SIZE; | |
204 | } | |
205 | ||
206 | i915_gem_chipset_flush(obj->base.dev); | |
207 | ||
208 | st = kmalloc(sizeof(*st), GFP_KERNEL); | |
209 | if (st == NULL) | |
210 | return -ENOMEM; | |
211 | ||
212 | if (sg_alloc_table(st, 1, GFP_KERNEL)) { | |
213 | kfree(st); | |
214 | return -ENOMEM; | |
215 | } | |
216 | ||
217 | sg = st->sgl; | |
218 | sg->offset = 0; | |
219 | sg->length = obj->base.size; | |
00731155 | 220 | |
6a2c4232 CW |
221 | sg_dma_address(sg) = obj->phys_handle->busaddr; |
222 | sg_dma_len(sg) = obj->base.size; | |
223 | ||
224 | obj->pages = st; | |
225 | obj->has_dma_mapping = true; | |
226 | return 0; | |
227 | } | |
228 | ||
229 | static void | |
230 | i915_gem_object_put_pages_phys(struct drm_i915_gem_object *obj) | |
231 | { | |
232 | int ret; | |
233 | ||
234 | BUG_ON(obj->madv == __I915_MADV_PURGED); | |
00731155 | 235 | |
6a2c4232 CW |
236 | ret = i915_gem_object_set_to_cpu_domain(obj, true); |
237 | if (ret) { | |
238 | /* In the event of a disaster, abandon all caches and | |
239 | * hope for the best. | |
240 | */ | |
241 | WARN_ON(ret != -EIO); | |
242 | obj->base.read_domains = obj->base.write_domain = I915_GEM_DOMAIN_CPU; | |
243 | } | |
244 | ||
245 | if (obj->madv == I915_MADV_DONTNEED) | |
246 | obj->dirty = 0; | |
247 | ||
248 | if (obj->dirty) { | |
00731155 | 249 | struct address_space *mapping = file_inode(obj->base.filp)->i_mapping; |
6a2c4232 | 250 | char *vaddr = obj->phys_handle->vaddr; |
00731155 CW |
251 | int i; |
252 | ||
253 | for (i = 0; i < obj->base.size / PAGE_SIZE; i++) { | |
6a2c4232 CW |
254 | struct page *page; |
255 | char *dst; | |
256 | ||
257 | page = shmem_read_mapping_page(mapping, i); | |
258 | if (IS_ERR(page)) | |
259 | continue; | |
260 | ||
261 | dst = kmap_atomic(page); | |
262 | drm_clflush_virt_range(vaddr, PAGE_SIZE); | |
263 | memcpy(dst, vaddr, PAGE_SIZE); | |
264 | kunmap_atomic(dst); | |
265 | ||
266 | set_page_dirty(page); | |
267 | if (obj->madv == I915_MADV_WILLNEED) | |
00731155 | 268 | mark_page_accessed(page); |
6a2c4232 | 269 | page_cache_release(page); |
00731155 CW |
270 | vaddr += PAGE_SIZE; |
271 | } | |
6a2c4232 | 272 | obj->dirty = 0; |
00731155 CW |
273 | } |
274 | ||
6a2c4232 CW |
275 | sg_free_table(obj->pages); |
276 | kfree(obj->pages); | |
277 | ||
278 | obj->has_dma_mapping = false; | |
279 | } | |
280 | ||
281 | static void | |
282 | i915_gem_object_release_phys(struct drm_i915_gem_object *obj) | |
283 | { | |
284 | drm_pci_free(obj->base.dev, obj->phys_handle); | |
285 | } | |
286 | ||
287 | static const struct drm_i915_gem_object_ops i915_gem_phys_ops = { | |
288 | .get_pages = i915_gem_object_get_pages_phys, | |
289 | .put_pages = i915_gem_object_put_pages_phys, | |
290 | .release = i915_gem_object_release_phys, | |
291 | }; | |
292 | ||
293 | static int | |
294 | drop_pages(struct drm_i915_gem_object *obj) | |
295 | { | |
296 | struct i915_vma *vma, *next; | |
297 | int ret; | |
298 | ||
299 | drm_gem_object_reference(&obj->base); | |
300 | list_for_each_entry_safe(vma, next, &obj->vma_list, vma_link) | |
301 | if (i915_vma_unbind(vma)) | |
302 | break; | |
303 | ||
304 | ret = i915_gem_object_put_pages(obj); | |
305 | drm_gem_object_unreference(&obj->base); | |
306 | ||
307 | return ret; | |
00731155 CW |
308 | } |
309 | ||
310 | int | |
311 | i915_gem_object_attach_phys(struct drm_i915_gem_object *obj, | |
312 | int align) | |
313 | { | |
314 | drm_dma_handle_t *phys; | |
6a2c4232 | 315 | int ret; |
00731155 CW |
316 | |
317 | if (obj->phys_handle) { | |
318 | if ((unsigned long)obj->phys_handle->vaddr & (align -1)) | |
319 | return -EBUSY; | |
320 | ||
321 | return 0; | |
322 | } | |
323 | ||
324 | if (obj->madv != I915_MADV_WILLNEED) | |
325 | return -EFAULT; | |
326 | ||
327 | if (obj->base.filp == NULL) | |
328 | return -EINVAL; | |
329 | ||
6a2c4232 CW |
330 | ret = drop_pages(obj); |
331 | if (ret) | |
332 | return ret; | |
333 | ||
00731155 CW |
334 | /* create a new object */ |
335 | phys = drm_pci_alloc(obj->base.dev, obj->base.size, align); | |
336 | if (!phys) | |
337 | return -ENOMEM; | |
338 | ||
00731155 | 339 | obj->phys_handle = phys; |
6a2c4232 CW |
340 | obj->ops = &i915_gem_phys_ops; |
341 | ||
342 | return i915_gem_object_get_pages(obj); | |
00731155 CW |
343 | } |
344 | ||
345 | static int | |
346 | i915_gem_phys_pwrite(struct drm_i915_gem_object *obj, | |
347 | struct drm_i915_gem_pwrite *args, | |
348 | struct drm_file *file_priv) | |
349 | { | |
350 | struct drm_device *dev = obj->base.dev; | |
351 | void *vaddr = obj->phys_handle->vaddr + args->offset; | |
352 | char __user *user_data = to_user_ptr(args->data_ptr); | |
6a2c4232 CW |
353 | int ret; |
354 | ||
355 | /* We manually control the domain here and pretend that it | |
356 | * remains coherent i.e. in the GTT domain, like shmem_pwrite. | |
357 | */ | |
358 | ret = i915_gem_object_wait_rendering(obj, false); | |
359 | if (ret) | |
360 | return ret; | |
00731155 CW |
361 | |
362 | if (__copy_from_user_inatomic_nocache(vaddr, user_data, args->size)) { | |
363 | unsigned long unwritten; | |
364 | ||
365 | /* The physical object once assigned is fixed for the lifetime | |
366 | * of the obj, so we can safely drop the lock and continue | |
367 | * to access vaddr. | |
368 | */ | |
369 | mutex_unlock(&dev->struct_mutex); | |
370 | unwritten = copy_from_user(vaddr, user_data, args->size); | |
371 | mutex_lock(&dev->struct_mutex); | |
372 | if (unwritten) | |
373 | return -EFAULT; | |
374 | } | |
375 | ||
6a2c4232 | 376 | drm_clflush_virt_range(vaddr, args->size); |
00731155 CW |
377 | i915_gem_chipset_flush(dev); |
378 | return 0; | |
379 | } | |
380 | ||
42dcedd4 CW |
381 | void *i915_gem_object_alloc(struct drm_device *dev) |
382 | { | |
383 | struct drm_i915_private *dev_priv = dev->dev_private; | |
fac15c10 | 384 | return kmem_cache_zalloc(dev_priv->slab, GFP_KERNEL); |
42dcedd4 CW |
385 | } |
386 | ||
387 | void i915_gem_object_free(struct drm_i915_gem_object *obj) | |
388 | { | |
389 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; | |
390 | kmem_cache_free(dev_priv->slab, obj); | |
391 | } | |
392 | ||
ff72145b DA |
393 | static int |
394 | i915_gem_create(struct drm_file *file, | |
395 | struct drm_device *dev, | |
396 | uint64_t size, | |
397 | uint32_t *handle_p) | |
673a394b | 398 | { |
05394f39 | 399 | struct drm_i915_gem_object *obj; |
a1a2d1d3 PP |
400 | int ret; |
401 | u32 handle; | |
673a394b | 402 | |
ff72145b | 403 | size = roundup(size, PAGE_SIZE); |
8ffc0246 CW |
404 | if (size == 0) |
405 | return -EINVAL; | |
673a394b EA |
406 | |
407 | /* Allocate the new object */ | |
ff72145b | 408 | obj = i915_gem_alloc_object(dev, size); |
673a394b EA |
409 | if (obj == NULL) |
410 | return -ENOMEM; | |
411 | ||
05394f39 | 412 | ret = drm_gem_handle_create(file, &obj->base, &handle); |
202f2fef | 413 | /* drop reference from allocate - handle holds it now */ |
d861e338 DV |
414 | drm_gem_object_unreference_unlocked(&obj->base); |
415 | if (ret) | |
416 | return ret; | |
202f2fef | 417 | |
ff72145b | 418 | *handle_p = handle; |
673a394b EA |
419 | return 0; |
420 | } | |
421 | ||
ff72145b DA |
422 | int |
423 | i915_gem_dumb_create(struct drm_file *file, | |
424 | struct drm_device *dev, | |
425 | struct drm_mode_create_dumb *args) | |
426 | { | |
427 | /* have to work out size/pitch and return them */ | |
de45eaf7 | 428 | args->pitch = ALIGN(args->width * DIV_ROUND_UP(args->bpp, 8), 64); |
ff72145b DA |
429 | args->size = args->pitch * args->height; |
430 | return i915_gem_create(file, dev, | |
da6b51d0 | 431 | args->size, &args->handle); |
ff72145b DA |
432 | } |
433 | ||
ff72145b DA |
434 | /** |
435 | * Creates a new mm object and returns a handle to it. | |
436 | */ | |
437 | int | |
438 | i915_gem_create_ioctl(struct drm_device *dev, void *data, | |
439 | struct drm_file *file) | |
440 | { | |
441 | struct drm_i915_gem_create *args = data; | |
63ed2cb2 | 442 | |
ff72145b | 443 | return i915_gem_create(file, dev, |
da6b51d0 | 444 | args->size, &args->handle); |
ff72145b DA |
445 | } |
446 | ||
8461d226 DV |
447 | static inline int |
448 | __copy_to_user_swizzled(char __user *cpu_vaddr, | |
449 | const char *gpu_vaddr, int gpu_offset, | |
450 | int length) | |
451 | { | |
452 | int ret, cpu_offset = 0; | |
453 | ||
454 | while (length > 0) { | |
455 | int cacheline_end = ALIGN(gpu_offset + 1, 64); | |
456 | int this_length = min(cacheline_end - gpu_offset, length); | |
457 | int swizzled_gpu_offset = gpu_offset ^ 64; | |
458 | ||
459 | ret = __copy_to_user(cpu_vaddr + cpu_offset, | |
460 | gpu_vaddr + swizzled_gpu_offset, | |
461 | this_length); | |
462 | if (ret) | |
463 | return ret + length; | |
464 | ||
465 | cpu_offset += this_length; | |
466 | gpu_offset += this_length; | |
467 | length -= this_length; | |
468 | } | |
469 | ||
470 | return 0; | |
471 | } | |
472 | ||
8c59967c | 473 | static inline int |
4f0c7cfb BW |
474 | __copy_from_user_swizzled(char *gpu_vaddr, int gpu_offset, |
475 | const char __user *cpu_vaddr, | |
8c59967c DV |
476 | int length) |
477 | { | |
478 | int ret, cpu_offset = 0; | |
479 | ||
480 | while (length > 0) { | |
481 | int cacheline_end = ALIGN(gpu_offset + 1, 64); | |
482 | int this_length = min(cacheline_end - gpu_offset, length); | |
483 | int swizzled_gpu_offset = gpu_offset ^ 64; | |
484 | ||
485 | ret = __copy_from_user(gpu_vaddr + swizzled_gpu_offset, | |
486 | cpu_vaddr + cpu_offset, | |
487 | this_length); | |
488 | if (ret) | |
489 | return ret + length; | |
490 | ||
491 | cpu_offset += this_length; | |
492 | gpu_offset += this_length; | |
493 | length -= this_length; | |
494 | } | |
495 | ||
496 | return 0; | |
497 | } | |
498 | ||
4c914c0c BV |
499 | /* |
500 | * Pins the specified object's pages and synchronizes the object with | |
501 | * GPU accesses. Sets needs_clflush to non-zero if the caller should | |
502 | * flush the object from the CPU cache. | |
503 | */ | |
504 | int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj, | |
505 | int *needs_clflush) | |
506 | { | |
507 | int ret; | |
508 | ||
509 | *needs_clflush = 0; | |
510 | ||
511 | if (!obj->base.filp) | |
512 | return -EINVAL; | |
513 | ||
514 | if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU)) { | |
515 | /* If we're not in the cpu read domain, set ourself into the gtt | |
516 | * read domain and manually flush cachelines (if required). This | |
517 | * optimizes for the case when the gpu will dirty the data | |
518 | * anyway again before the next pread happens. */ | |
519 | *needs_clflush = !cpu_cache_is_coherent(obj->base.dev, | |
520 | obj->cache_level); | |
521 | ret = i915_gem_object_wait_rendering(obj, true); | |
522 | if (ret) | |
523 | return ret; | |
c8725f3d CW |
524 | |
525 | i915_gem_object_retire(obj); | |
4c914c0c BV |
526 | } |
527 | ||
528 | ret = i915_gem_object_get_pages(obj); | |
529 | if (ret) | |
530 | return ret; | |
531 | ||
532 | i915_gem_object_pin_pages(obj); | |
533 | ||
534 | return ret; | |
535 | } | |
536 | ||
d174bd64 DV |
537 | /* Per-page copy function for the shmem pread fastpath. |
538 | * Flushes invalid cachelines before reading the target if | |
539 | * needs_clflush is set. */ | |
eb01459f | 540 | static int |
d174bd64 DV |
541 | shmem_pread_fast(struct page *page, int shmem_page_offset, int page_length, |
542 | char __user *user_data, | |
543 | bool page_do_bit17_swizzling, bool needs_clflush) | |
544 | { | |
545 | char *vaddr; | |
546 | int ret; | |
547 | ||
e7e58eb5 | 548 | if (unlikely(page_do_bit17_swizzling)) |
d174bd64 DV |
549 | return -EINVAL; |
550 | ||
551 | vaddr = kmap_atomic(page); | |
552 | if (needs_clflush) | |
553 | drm_clflush_virt_range(vaddr + shmem_page_offset, | |
554 | page_length); | |
555 | ret = __copy_to_user_inatomic(user_data, | |
556 | vaddr + shmem_page_offset, | |
557 | page_length); | |
558 | kunmap_atomic(vaddr); | |
559 | ||
f60d7f0c | 560 | return ret ? -EFAULT : 0; |
d174bd64 DV |
561 | } |
562 | ||
23c18c71 DV |
563 | static void |
564 | shmem_clflush_swizzled_range(char *addr, unsigned long length, | |
565 | bool swizzled) | |
566 | { | |
e7e58eb5 | 567 | if (unlikely(swizzled)) { |
23c18c71 DV |
568 | unsigned long start = (unsigned long) addr; |
569 | unsigned long end = (unsigned long) addr + length; | |
570 | ||
571 | /* For swizzling simply ensure that we always flush both | |
572 | * channels. Lame, but simple and it works. Swizzled | |
573 | * pwrite/pread is far from a hotpath - current userspace | |
574 | * doesn't use it at all. */ | |
575 | start = round_down(start, 128); | |
576 | end = round_up(end, 128); | |
577 | ||
578 | drm_clflush_virt_range((void *)start, end - start); | |
579 | } else { | |
580 | drm_clflush_virt_range(addr, length); | |
581 | } | |
582 | ||
583 | } | |
584 | ||
d174bd64 DV |
585 | /* Only difference to the fast-path function is that this can handle bit17 |
586 | * and uses non-atomic copy and kmap functions. */ | |
587 | static int | |
588 | shmem_pread_slow(struct page *page, int shmem_page_offset, int page_length, | |
589 | char __user *user_data, | |
590 | bool page_do_bit17_swizzling, bool needs_clflush) | |
591 | { | |
592 | char *vaddr; | |
593 | int ret; | |
594 | ||
595 | vaddr = kmap(page); | |
596 | if (needs_clflush) | |
23c18c71 DV |
597 | shmem_clflush_swizzled_range(vaddr + shmem_page_offset, |
598 | page_length, | |
599 | page_do_bit17_swizzling); | |
d174bd64 DV |
600 | |
601 | if (page_do_bit17_swizzling) | |
602 | ret = __copy_to_user_swizzled(user_data, | |
603 | vaddr, shmem_page_offset, | |
604 | page_length); | |
605 | else | |
606 | ret = __copy_to_user(user_data, | |
607 | vaddr + shmem_page_offset, | |
608 | page_length); | |
609 | kunmap(page); | |
610 | ||
f60d7f0c | 611 | return ret ? - EFAULT : 0; |
d174bd64 DV |
612 | } |
613 | ||
eb01459f | 614 | static int |
dbf7bff0 DV |
615 | i915_gem_shmem_pread(struct drm_device *dev, |
616 | struct drm_i915_gem_object *obj, | |
617 | struct drm_i915_gem_pread *args, | |
618 | struct drm_file *file) | |
eb01459f | 619 | { |
8461d226 | 620 | char __user *user_data; |
eb01459f | 621 | ssize_t remain; |
8461d226 | 622 | loff_t offset; |
eb2c0c81 | 623 | int shmem_page_offset, page_length, ret = 0; |
8461d226 | 624 | int obj_do_bit17_swizzling, page_do_bit17_swizzling; |
96d79b52 | 625 | int prefaulted = 0; |
8489731c | 626 | int needs_clflush = 0; |
67d5a50c | 627 | struct sg_page_iter sg_iter; |
eb01459f | 628 | |
2bb4629a | 629 | user_data = to_user_ptr(args->data_ptr); |
eb01459f EA |
630 | remain = args->size; |
631 | ||
8461d226 | 632 | obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj); |
eb01459f | 633 | |
4c914c0c | 634 | ret = i915_gem_obj_prepare_shmem_read(obj, &needs_clflush); |
f60d7f0c CW |
635 | if (ret) |
636 | return ret; | |
637 | ||
8461d226 | 638 | offset = args->offset; |
eb01459f | 639 | |
67d5a50c ID |
640 | for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, |
641 | offset >> PAGE_SHIFT) { | |
2db76d7c | 642 | struct page *page = sg_page_iter_page(&sg_iter); |
9da3da66 CW |
643 | |
644 | if (remain <= 0) | |
645 | break; | |
646 | ||
eb01459f EA |
647 | /* Operation in this page |
648 | * | |
eb01459f | 649 | * shmem_page_offset = offset within page in shmem file |
eb01459f EA |
650 | * page_length = bytes to copy for this page |
651 | */ | |
c8cbbb8b | 652 | shmem_page_offset = offset_in_page(offset); |
eb01459f EA |
653 | page_length = remain; |
654 | if ((shmem_page_offset + page_length) > PAGE_SIZE) | |
655 | page_length = PAGE_SIZE - shmem_page_offset; | |
eb01459f | 656 | |
8461d226 DV |
657 | page_do_bit17_swizzling = obj_do_bit17_swizzling && |
658 | (page_to_phys(page) & (1 << 17)) != 0; | |
659 | ||
d174bd64 DV |
660 | ret = shmem_pread_fast(page, shmem_page_offset, page_length, |
661 | user_data, page_do_bit17_swizzling, | |
662 | needs_clflush); | |
663 | if (ret == 0) | |
664 | goto next_page; | |
dbf7bff0 | 665 | |
dbf7bff0 DV |
666 | mutex_unlock(&dev->struct_mutex); |
667 | ||
d330a953 | 668 | if (likely(!i915.prefault_disable) && !prefaulted) { |
f56f821f | 669 | ret = fault_in_multipages_writeable(user_data, remain); |
96d79b52 DV |
670 | /* Userspace is tricking us, but we've already clobbered |
671 | * its pages with the prefault and promised to write the | |
672 | * data up to the first fault. Hence ignore any errors | |
673 | * and just continue. */ | |
674 | (void)ret; | |
675 | prefaulted = 1; | |
676 | } | |
eb01459f | 677 | |
d174bd64 DV |
678 | ret = shmem_pread_slow(page, shmem_page_offset, page_length, |
679 | user_data, page_do_bit17_swizzling, | |
680 | needs_clflush); | |
eb01459f | 681 | |
dbf7bff0 | 682 | mutex_lock(&dev->struct_mutex); |
f60d7f0c | 683 | |
f60d7f0c | 684 | if (ret) |
8461d226 | 685 | goto out; |
8461d226 | 686 | |
17793c9a | 687 | next_page: |
eb01459f | 688 | remain -= page_length; |
8461d226 | 689 | user_data += page_length; |
eb01459f EA |
690 | offset += page_length; |
691 | } | |
692 | ||
4f27b75d | 693 | out: |
f60d7f0c CW |
694 | i915_gem_object_unpin_pages(obj); |
695 | ||
eb01459f EA |
696 | return ret; |
697 | } | |
698 | ||
673a394b EA |
699 | /** |
700 | * Reads data from the object referenced by handle. | |
701 | * | |
702 | * On error, the contents of *data are undefined. | |
703 | */ | |
704 | int | |
705 | i915_gem_pread_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 706 | struct drm_file *file) |
673a394b EA |
707 | { |
708 | struct drm_i915_gem_pread *args = data; | |
05394f39 | 709 | struct drm_i915_gem_object *obj; |
35b62a89 | 710 | int ret = 0; |
673a394b | 711 | |
51311d0a CW |
712 | if (args->size == 0) |
713 | return 0; | |
714 | ||
715 | if (!access_ok(VERIFY_WRITE, | |
2bb4629a | 716 | to_user_ptr(args->data_ptr), |
51311d0a CW |
717 | args->size)) |
718 | return -EFAULT; | |
719 | ||
4f27b75d | 720 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 721 | if (ret) |
4f27b75d | 722 | return ret; |
673a394b | 723 | |
05394f39 | 724 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 725 | if (&obj->base == NULL) { |
1d7cfea1 CW |
726 | ret = -ENOENT; |
727 | goto unlock; | |
4f27b75d | 728 | } |
673a394b | 729 | |
7dcd2499 | 730 | /* Bounds check source. */ |
05394f39 CW |
731 | if (args->offset > obj->base.size || |
732 | args->size > obj->base.size - args->offset) { | |
ce9d419d | 733 | ret = -EINVAL; |
35b62a89 | 734 | goto out; |
ce9d419d CW |
735 | } |
736 | ||
1286ff73 DV |
737 | /* prime objects have no backing filp to GEM pread/pwrite |
738 | * pages from. | |
739 | */ | |
740 | if (!obj->base.filp) { | |
741 | ret = -EINVAL; | |
742 | goto out; | |
743 | } | |
744 | ||
db53a302 CW |
745 | trace_i915_gem_object_pread(obj, args->offset, args->size); |
746 | ||
dbf7bff0 | 747 | ret = i915_gem_shmem_pread(dev, obj, args, file); |
673a394b | 748 | |
35b62a89 | 749 | out: |
05394f39 | 750 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 751 | unlock: |
4f27b75d | 752 | mutex_unlock(&dev->struct_mutex); |
eb01459f | 753 | return ret; |
673a394b EA |
754 | } |
755 | ||
0839ccb8 KP |
756 | /* This is the fast write path which cannot handle |
757 | * page faults in the source data | |
9b7530cc | 758 | */ |
0839ccb8 KP |
759 | |
760 | static inline int | |
761 | fast_user_write(struct io_mapping *mapping, | |
762 | loff_t page_base, int page_offset, | |
763 | char __user *user_data, | |
764 | int length) | |
9b7530cc | 765 | { |
4f0c7cfb BW |
766 | void __iomem *vaddr_atomic; |
767 | void *vaddr; | |
0839ccb8 | 768 | unsigned long unwritten; |
9b7530cc | 769 | |
3e4d3af5 | 770 | vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base); |
4f0c7cfb BW |
771 | /* We can use the cpu mem copy function because this is X86. */ |
772 | vaddr = (void __force*)vaddr_atomic + page_offset; | |
773 | unwritten = __copy_from_user_inatomic_nocache(vaddr, | |
0839ccb8 | 774 | user_data, length); |
3e4d3af5 | 775 | io_mapping_unmap_atomic(vaddr_atomic); |
fbd5a26d | 776 | return unwritten; |
0839ccb8 KP |
777 | } |
778 | ||
3de09aa3 EA |
779 | /** |
780 | * This is the fast pwrite path, where we copy the data directly from the | |
781 | * user into the GTT, uncached. | |
782 | */ | |
673a394b | 783 | static int |
05394f39 CW |
784 | i915_gem_gtt_pwrite_fast(struct drm_device *dev, |
785 | struct drm_i915_gem_object *obj, | |
3de09aa3 | 786 | struct drm_i915_gem_pwrite *args, |
05394f39 | 787 | struct drm_file *file) |
673a394b | 788 | { |
3e31c6c0 | 789 | struct drm_i915_private *dev_priv = dev->dev_private; |
673a394b | 790 | ssize_t remain; |
0839ccb8 | 791 | loff_t offset, page_base; |
673a394b | 792 | char __user *user_data; |
935aaa69 DV |
793 | int page_offset, page_length, ret; |
794 | ||
1ec9e26d | 795 | ret = i915_gem_obj_ggtt_pin(obj, 0, PIN_MAPPABLE | PIN_NONBLOCK); |
935aaa69 DV |
796 | if (ret) |
797 | goto out; | |
798 | ||
799 | ret = i915_gem_object_set_to_gtt_domain(obj, true); | |
800 | if (ret) | |
801 | goto out_unpin; | |
802 | ||
803 | ret = i915_gem_object_put_fence(obj); | |
804 | if (ret) | |
805 | goto out_unpin; | |
673a394b | 806 | |
2bb4629a | 807 | user_data = to_user_ptr(args->data_ptr); |
673a394b | 808 | remain = args->size; |
673a394b | 809 | |
f343c5f6 | 810 | offset = i915_gem_obj_ggtt_offset(obj) + args->offset; |
673a394b EA |
811 | |
812 | while (remain > 0) { | |
813 | /* Operation in this page | |
814 | * | |
0839ccb8 KP |
815 | * page_base = page offset within aperture |
816 | * page_offset = offset within page | |
817 | * page_length = bytes to copy for this page | |
673a394b | 818 | */ |
c8cbbb8b CW |
819 | page_base = offset & PAGE_MASK; |
820 | page_offset = offset_in_page(offset); | |
0839ccb8 KP |
821 | page_length = remain; |
822 | if ((page_offset + remain) > PAGE_SIZE) | |
823 | page_length = PAGE_SIZE - page_offset; | |
824 | ||
0839ccb8 | 825 | /* If we get a fault while copying data, then (presumably) our |
3de09aa3 EA |
826 | * source page isn't available. Return the error and we'll |
827 | * retry in the slow path. | |
0839ccb8 | 828 | */ |
5d4545ae | 829 | if (fast_user_write(dev_priv->gtt.mappable, page_base, |
935aaa69 DV |
830 | page_offset, user_data, page_length)) { |
831 | ret = -EFAULT; | |
832 | goto out_unpin; | |
833 | } | |
673a394b | 834 | |
0839ccb8 KP |
835 | remain -= page_length; |
836 | user_data += page_length; | |
837 | offset += page_length; | |
673a394b | 838 | } |
673a394b | 839 | |
935aaa69 | 840 | out_unpin: |
d7f46fc4 | 841 | i915_gem_object_ggtt_unpin(obj); |
935aaa69 | 842 | out: |
3de09aa3 | 843 | return ret; |
673a394b EA |
844 | } |
845 | ||
d174bd64 DV |
846 | /* Per-page copy function for the shmem pwrite fastpath. |
847 | * Flushes invalid cachelines before writing to the target if | |
848 | * needs_clflush_before is set and flushes out any written cachelines after | |
849 | * writing if needs_clflush is set. */ | |
3043c60c | 850 | static int |
d174bd64 DV |
851 | shmem_pwrite_fast(struct page *page, int shmem_page_offset, int page_length, |
852 | char __user *user_data, | |
853 | bool page_do_bit17_swizzling, | |
854 | bool needs_clflush_before, | |
855 | bool needs_clflush_after) | |
673a394b | 856 | { |
d174bd64 | 857 | char *vaddr; |
673a394b | 858 | int ret; |
3de09aa3 | 859 | |
e7e58eb5 | 860 | if (unlikely(page_do_bit17_swizzling)) |
d174bd64 | 861 | return -EINVAL; |
3de09aa3 | 862 | |
d174bd64 DV |
863 | vaddr = kmap_atomic(page); |
864 | if (needs_clflush_before) | |
865 | drm_clflush_virt_range(vaddr + shmem_page_offset, | |
866 | page_length); | |
c2831a94 CW |
867 | ret = __copy_from_user_inatomic(vaddr + shmem_page_offset, |
868 | user_data, page_length); | |
d174bd64 DV |
869 | if (needs_clflush_after) |
870 | drm_clflush_virt_range(vaddr + shmem_page_offset, | |
871 | page_length); | |
872 | kunmap_atomic(vaddr); | |
3de09aa3 | 873 | |
755d2218 | 874 | return ret ? -EFAULT : 0; |
3de09aa3 EA |
875 | } |
876 | ||
d174bd64 DV |
877 | /* Only difference to the fast-path function is that this can handle bit17 |
878 | * and uses non-atomic copy and kmap functions. */ | |
3043c60c | 879 | static int |
d174bd64 DV |
880 | shmem_pwrite_slow(struct page *page, int shmem_page_offset, int page_length, |
881 | char __user *user_data, | |
882 | bool page_do_bit17_swizzling, | |
883 | bool needs_clflush_before, | |
884 | bool needs_clflush_after) | |
673a394b | 885 | { |
d174bd64 DV |
886 | char *vaddr; |
887 | int ret; | |
e5281ccd | 888 | |
d174bd64 | 889 | vaddr = kmap(page); |
e7e58eb5 | 890 | if (unlikely(needs_clflush_before || page_do_bit17_swizzling)) |
23c18c71 DV |
891 | shmem_clflush_swizzled_range(vaddr + shmem_page_offset, |
892 | page_length, | |
893 | page_do_bit17_swizzling); | |
d174bd64 DV |
894 | if (page_do_bit17_swizzling) |
895 | ret = __copy_from_user_swizzled(vaddr, shmem_page_offset, | |
e5281ccd CW |
896 | user_data, |
897 | page_length); | |
d174bd64 DV |
898 | else |
899 | ret = __copy_from_user(vaddr + shmem_page_offset, | |
900 | user_data, | |
901 | page_length); | |
902 | if (needs_clflush_after) | |
23c18c71 DV |
903 | shmem_clflush_swizzled_range(vaddr + shmem_page_offset, |
904 | page_length, | |
905 | page_do_bit17_swizzling); | |
d174bd64 | 906 | kunmap(page); |
40123c1f | 907 | |
755d2218 | 908 | return ret ? -EFAULT : 0; |
40123c1f EA |
909 | } |
910 | ||
40123c1f | 911 | static int |
e244a443 DV |
912 | i915_gem_shmem_pwrite(struct drm_device *dev, |
913 | struct drm_i915_gem_object *obj, | |
914 | struct drm_i915_gem_pwrite *args, | |
915 | struct drm_file *file) | |
40123c1f | 916 | { |
40123c1f | 917 | ssize_t remain; |
8c59967c DV |
918 | loff_t offset; |
919 | char __user *user_data; | |
eb2c0c81 | 920 | int shmem_page_offset, page_length, ret = 0; |
8c59967c | 921 | int obj_do_bit17_swizzling, page_do_bit17_swizzling; |
e244a443 | 922 | int hit_slowpath = 0; |
58642885 DV |
923 | int needs_clflush_after = 0; |
924 | int needs_clflush_before = 0; | |
67d5a50c | 925 | struct sg_page_iter sg_iter; |
40123c1f | 926 | |
2bb4629a | 927 | user_data = to_user_ptr(args->data_ptr); |
40123c1f EA |
928 | remain = args->size; |
929 | ||
8c59967c | 930 | obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj); |
40123c1f | 931 | |
58642885 DV |
932 | if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) { |
933 | /* If we're not in the cpu write domain, set ourself into the gtt | |
934 | * write domain and manually flush cachelines (if required). This | |
935 | * optimizes for the case when the gpu will use the data | |
936 | * right away and we therefore have to clflush anyway. */ | |
2c22569b | 937 | needs_clflush_after = cpu_write_needs_clflush(obj); |
23f54483 BW |
938 | ret = i915_gem_object_wait_rendering(obj, false); |
939 | if (ret) | |
940 | return ret; | |
c8725f3d CW |
941 | |
942 | i915_gem_object_retire(obj); | |
58642885 | 943 | } |
c76ce038 CW |
944 | /* Same trick applies to invalidate partially written cachelines read |
945 | * before writing. */ | |
946 | if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) | |
947 | needs_clflush_before = | |
948 | !cpu_cache_is_coherent(dev, obj->cache_level); | |
58642885 | 949 | |
755d2218 CW |
950 | ret = i915_gem_object_get_pages(obj); |
951 | if (ret) | |
952 | return ret; | |
953 | ||
954 | i915_gem_object_pin_pages(obj); | |
955 | ||
673a394b | 956 | offset = args->offset; |
05394f39 | 957 | obj->dirty = 1; |
673a394b | 958 | |
67d5a50c ID |
959 | for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, |
960 | offset >> PAGE_SHIFT) { | |
2db76d7c | 961 | struct page *page = sg_page_iter_page(&sg_iter); |
58642885 | 962 | int partial_cacheline_write; |
e5281ccd | 963 | |
9da3da66 CW |
964 | if (remain <= 0) |
965 | break; | |
966 | ||
40123c1f EA |
967 | /* Operation in this page |
968 | * | |
40123c1f | 969 | * shmem_page_offset = offset within page in shmem file |
40123c1f EA |
970 | * page_length = bytes to copy for this page |
971 | */ | |
c8cbbb8b | 972 | shmem_page_offset = offset_in_page(offset); |
40123c1f EA |
973 | |
974 | page_length = remain; | |
975 | if ((shmem_page_offset + page_length) > PAGE_SIZE) | |
976 | page_length = PAGE_SIZE - shmem_page_offset; | |
40123c1f | 977 | |
58642885 DV |
978 | /* If we don't overwrite a cacheline completely we need to be |
979 | * careful to have up-to-date data by first clflushing. Don't | |
980 | * overcomplicate things and flush the entire patch. */ | |
981 | partial_cacheline_write = needs_clflush_before && | |
982 | ((shmem_page_offset | page_length) | |
983 | & (boot_cpu_data.x86_clflush_size - 1)); | |
984 | ||
8c59967c DV |
985 | page_do_bit17_swizzling = obj_do_bit17_swizzling && |
986 | (page_to_phys(page) & (1 << 17)) != 0; | |
987 | ||
d174bd64 DV |
988 | ret = shmem_pwrite_fast(page, shmem_page_offset, page_length, |
989 | user_data, page_do_bit17_swizzling, | |
990 | partial_cacheline_write, | |
991 | needs_clflush_after); | |
992 | if (ret == 0) | |
993 | goto next_page; | |
e244a443 DV |
994 | |
995 | hit_slowpath = 1; | |
e244a443 | 996 | mutex_unlock(&dev->struct_mutex); |
d174bd64 DV |
997 | ret = shmem_pwrite_slow(page, shmem_page_offset, page_length, |
998 | user_data, page_do_bit17_swizzling, | |
999 | partial_cacheline_write, | |
1000 | needs_clflush_after); | |
40123c1f | 1001 | |
e244a443 | 1002 | mutex_lock(&dev->struct_mutex); |
755d2218 | 1003 | |
755d2218 | 1004 | if (ret) |
8c59967c | 1005 | goto out; |
8c59967c | 1006 | |
17793c9a | 1007 | next_page: |
40123c1f | 1008 | remain -= page_length; |
8c59967c | 1009 | user_data += page_length; |
40123c1f | 1010 | offset += page_length; |
673a394b EA |
1011 | } |
1012 | ||
fbd5a26d | 1013 | out: |
755d2218 CW |
1014 | i915_gem_object_unpin_pages(obj); |
1015 | ||
e244a443 | 1016 | if (hit_slowpath) { |
8dcf015e DV |
1017 | /* |
1018 | * Fixup: Flush cpu caches in case we didn't flush the dirty | |
1019 | * cachelines in-line while writing and the object moved | |
1020 | * out of the cpu write domain while we've dropped the lock. | |
1021 | */ | |
1022 | if (!needs_clflush_after && | |
1023 | obj->base.write_domain != I915_GEM_DOMAIN_CPU) { | |
000433b6 CW |
1024 | if (i915_gem_clflush_object(obj, obj->pin_display)) |
1025 | i915_gem_chipset_flush(dev); | |
e244a443 | 1026 | } |
8c59967c | 1027 | } |
673a394b | 1028 | |
58642885 | 1029 | if (needs_clflush_after) |
e76e9aeb | 1030 | i915_gem_chipset_flush(dev); |
58642885 | 1031 | |
40123c1f | 1032 | return ret; |
673a394b EA |
1033 | } |
1034 | ||
1035 | /** | |
1036 | * Writes data to the object referenced by handle. | |
1037 | * | |
1038 | * On error, the contents of the buffer that were to be modified are undefined. | |
1039 | */ | |
1040 | int | |
1041 | i915_gem_pwrite_ioctl(struct drm_device *dev, void *data, | |
fbd5a26d | 1042 | struct drm_file *file) |
673a394b | 1043 | { |
5d77d9c5 | 1044 | struct drm_i915_private *dev_priv = dev->dev_private; |
673a394b | 1045 | struct drm_i915_gem_pwrite *args = data; |
05394f39 | 1046 | struct drm_i915_gem_object *obj; |
51311d0a CW |
1047 | int ret; |
1048 | ||
1049 | if (args->size == 0) | |
1050 | return 0; | |
1051 | ||
1052 | if (!access_ok(VERIFY_READ, | |
2bb4629a | 1053 | to_user_ptr(args->data_ptr), |
51311d0a CW |
1054 | args->size)) |
1055 | return -EFAULT; | |
1056 | ||
d330a953 | 1057 | if (likely(!i915.prefault_disable)) { |
0b74b508 XZ |
1058 | ret = fault_in_multipages_readable(to_user_ptr(args->data_ptr), |
1059 | args->size); | |
1060 | if (ret) | |
1061 | return -EFAULT; | |
1062 | } | |
673a394b | 1063 | |
5d77d9c5 ID |
1064 | intel_runtime_pm_get(dev_priv); |
1065 | ||
fbd5a26d | 1066 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 1067 | if (ret) |
5d77d9c5 | 1068 | goto put_rpm; |
1d7cfea1 | 1069 | |
05394f39 | 1070 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 1071 | if (&obj->base == NULL) { |
1d7cfea1 CW |
1072 | ret = -ENOENT; |
1073 | goto unlock; | |
fbd5a26d | 1074 | } |
673a394b | 1075 | |
7dcd2499 | 1076 | /* Bounds check destination. */ |
05394f39 CW |
1077 | if (args->offset > obj->base.size || |
1078 | args->size > obj->base.size - args->offset) { | |
ce9d419d | 1079 | ret = -EINVAL; |
35b62a89 | 1080 | goto out; |
ce9d419d CW |
1081 | } |
1082 | ||
1286ff73 DV |
1083 | /* prime objects have no backing filp to GEM pread/pwrite |
1084 | * pages from. | |
1085 | */ | |
1086 | if (!obj->base.filp) { | |
1087 | ret = -EINVAL; | |
1088 | goto out; | |
1089 | } | |
1090 | ||
db53a302 CW |
1091 | trace_i915_gem_object_pwrite(obj, args->offset, args->size); |
1092 | ||
935aaa69 | 1093 | ret = -EFAULT; |
673a394b EA |
1094 | /* We can only do the GTT pwrite on untiled buffers, as otherwise |
1095 | * it would end up going through the fenced access, and we'll get | |
1096 | * different detiling behavior between reading and writing. | |
1097 | * pread/pwrite currently are reading and writing from the CPU | |
1098 | * perspective, requiring manual detiling by the client. | |
1099 | */ | |
2c22569b CW |
1100 | if (obj->tiling_mode == I915_TILING_NONE && |
1101 | obj->base.write_domain != I915_GEM_DOMAIN_CPU && | |
1102 | cpu_write_needs_clflush(obj)) { | |
fbd5a26d | 1103 | ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file); |
935aaa69 DV |
1104 | /* Note that the gtt paths might fail with non-page-backed user |
1105 | * pointers (e.g. gtt mappings when moving data between | |
1106 | * textures). Fallback to the shmem path in that case. */ | |
fbd5a26d | 1107 | } |
673a394b | 1108 | |
6a2c4232 CW |
1109 | if (ret == -EFAULT || ret == -ENOSPC) { |
1110 | if (obj->phys_handle) | |
1111 | ret = i915_gem_phys_pwrite(obj, args, file); | |
1112 | else | |
1113 | ret = i915_gem_shmem_pwrite(dev, obj, args, file); | |
1114 | } | |
5c0480f2 | 1115 | |
35b62a89 | 1116 | out: |
05394f39 | 1117 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 1118 | unlock: |
fbd5a26d | 1119 | mutex_unlock(&dev->struct_mutex); |
5d77d9c5 ID |
1120 | put_rpm: |
1121 | intel_runtime_pm_put(dev_priv); | |
1122 | ||
673a394b EA |
1123 | return ret; |
1124 | } | |
1125 | ||
b361237b | 1126 | int |
33196ded | 1127 | i915_gem_check_wedge(struct i915_gpu_error *error, |
b361237b CW |
1128 | bool interruptible) |
1129 | { | |
1f83fee0 | 1130 | if (i915_reset_in_progress(error)) { |
b361237b CW |
1131 | /* Non-interruptible callers can't handle -EAGAIN, hence return |
1132 | * -EIO unconditionally for these. */ | |
1133 | if (!interruptible) | |
1134 | return -EIO; | |
1135 | ||
1f83fee0 DV |
1136 | /* Recovery complete, but the reset failed ... */ |
1137 | if (i915_terminally_wedged(error)) | |
b361237b CW |
1138 | return -EIO; |
1139 | ||
6689c167 MA |
1140 | /* |
1141 | * Check if GPU Reset is in progress - we need intel_ring_begin | |
1142 | * to work properly to reinit the hw state while the gpu is | |
1143 | * still marked as reset-in-progress. Handle this with a flag. | |
1144 | */ | |
1145 | if (!error->reload_in_reset) | |
1146 | return -EAGAIN; | |
b361237b CW |
1147 | } |
1148 | ||
1149 | return 0; | |
1150 | } | |
1151 | ||
1152 | /* | |
b6660d59 | 1153 | * Compare arbitrary request against outstanding lazy request. Emit on match. |
b361237b | 1154 | */ |
84c33a64 | 1155 | int |
b6660d59 | 1156 | i915_gem_check_olr(struct drm_i915_gem_request *req) |
b361237b CW |
1157 | { |
1158 | int ret; | |
1159 | ||
b6660d59 | 1160 | WARN_ON(!mutex_is_locked(&req->ring->dev->struct_mutex)); |
b361237b CW |
1161 | |
1162 | ret = 0; | |
b6660d59 | 1163 | if (req == req->ring->outstanding_lazy_request) |
9400ae5c | 1164 | ret = i915_add_request(req->ring); |
b361237b CW |
1165 | |
1166 | return ret; | |
1167 | } | |
1168 | ||
094f9a54 CW |
1169 | static void fake_irq(unsigned long data) |
1170 | { | |
1171 | wake_up_process((struct task_struct *)data); | |
1172 | } | |
1173 | ||
1174 | static bool missed_irq(struct drm_i915_private *dev_priv, | |
a4872ba6 | 1175 | struct intel_engine_cs *ring) |
094f9a54 CW |
1176 | { |
1177 | return test_bit(ring->id, &dev_priv->gpu_error.missed_irq_rings); | |
1178 | } | |
1179 | ||
b29c19b6 CW |
1180 | static bool can_wait_boost(struct drm_i915_file_private *file_priv) |
1181 | { | |
1182 | if (file_priv == NULL) | |
1183 | return true; | |
1184 | ||
1185 | return !atomic_xchg(&file_priv->rps_wait_boost, true); | |
1186 | } | |
1187 | ||
b361237b | 1188 | /** |
9c654818 JH |
1189 | * __i915_wait_request - wait until execution of request has finished |
1190 | * @req: duh! | |
1191 | * @reset_counter: reset sequence associated with the given request | |
b361237b CW |
1192 | * @interruptible: do an interruptible wait (normally yes) |
1193 | * @timeout: in - how long to wait (NULL forever); out - how much time remaining | |
1194 | * | |
f69061be DV |
1195 | * Note: It is of utmost importance that the passed in seqno and reset_counter |
1196 | * values have been read by the caller in an smp safe manner. Where read-side | |
1197 | * locks are involved, it is sufficient to read the reset_counter before | |
1198 | * unlocking the lock that protects the seqno. For lockless tricks, the | |
1199 | * reset_counter _must_ be read before, and an appropriate smp_rmb must be | |
1200 | * inserted. | |
1201 | * | |
9c654818 | 1202 | * Returns 0 if the request was found within the alloted time. Else returns the |
b361237b CW |
1203 | * errno with remaining time filled in timeout argument. |
1204 | */ | |
9c654818 | 1205 | int __i915_wait_request(struct drm_i915_gem_request *req, |
f69061be | 1206 | unsigned reset_counter, |
b29c19b6 | 1207 | bool interruptible, |
5ed0bdf2 | 1208 | s64 *timeout, |
b29c19b6 | 1209 | struct drm_i915_file_private *file_priv) |
b361237b | 1210 | { |
9c654818 | 1211 | struct intel_engine_cs *ring = i915_gem_request_get_ring(req); |
3d13ef2e | 1212 | struct drm_device *dev = ring->dev; |
3e31c6c0 | 1213 | struct drm_i915_private *dev_priv = dev->dev_private; |
168c3f21 MK |
1214 | const bool irq_test_in_progress = |
1215 | ACCESS_ONCE(dev_priv->gpu_error.test_irq_rings) & intel_ring_flag(ring); | |
094f9a54 | 1216 | DEFINE_WAIT(wait); |
47e9766d | 1217 | unsigned long timeout_expire; |
5ed0bdf2 | 1218 | s64 before, now; |
b361237b CW |
1219 | int ret; |
1220 | ||
9df7575f | 1221 | WARN(!intel_irqs_enabled(dev_priv), "IRQs disabled"); |
c67a470b | 1222 | |
1b5a433a | 1223 | if (i915_gem_request_completed(req, true)) |
b361237b CW |
1224 | return 0; |
1225 | ||
7bd0e226 DV |
1226 | timeout_expire = timeout ? |
1227 | jiffies + nsecs_to_jiffies_timeout((u64)*timeout) : 0; | |
b361237b | 1228 | |
ec5cc0f9 | 1229 | if (INTEL_INFO(dev)->gen >= 6 && ring->id == RCS && can_wait_boost(file_priv)) { |
b29c19b6 CW |
1230 | gen6_rps_boost(dev_priv); |
1231 | if (file_priv) | |
1232 | mod_delayed_work(dev_priv->wq, | |
1233 | &file_priv->mm.idle_work, | |
1234 | msecs_to_jiffies(100)); | |
1235 | } | |
1236 | ||
168c3f21 | 1237 | if (!irq_test_in_progress && WARN_ON(!ring->irq_get(ring))) |
b361237b CW |
1238 | return -ENODEV; |
1239 | ||
094f9a54 | 1240 | /* Record current time in case interrupted by signal, or wedged */ |
74328ee5 | 1241 | trace_i915_gem_request_wait_begin(req); |
5ed0bdf2 | 1242 | before = ktime_get_raw_ns(); |
094f9a54 CW |
1243 | for (;;) { |
1244 | struct timer_list timer; | |
b361237b | 1245 | |
094f9a54 CW |
1246 | prepare_to_wait(&ring->irq_queue, &wait, |
1247 | interruptible ? TASK_INTERRUPTIBLE : TASK_UNINTERRUPTIBLE); | |
b361237b | 1248 | |
f69061be DV |
1249 | /* We need to check whether any gpu reset happened in between |
1250 | * the caller grabbing the seqno and now ... */ | |
094f9a54 CW |
1251 | if (reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter)) { |
1252 | /* ... but upgrade the -EAGAIN to an -EIO if the gpu | |
1253 | * is truely gone. */ | |
1254 | ret = i915_gem_check_wedge(&dev_priv->gpu_error, interruptible); | |
1255 | if (ret == 0) | |
1256 | ret = -EAGAIN; | |
1257 | break; | |
1258 | } | |
f69061be | 1259 | |
1b5a433a | 1260 | if (i915_gem_request_completed(req, false)) { |
094f9a54 CW |
1261 | ret = 0; |
1262 | break; | |
1263 | } | |
b361237b | 1264 | |
094f9a54 CW |
1265 | if (interruptible && signal_pending(current)) { |
1266 | ret = -ERESTARTSYS; | |
1267 | break; | |
1268 | } | |
1269 | ||
47e9766d | 1270 | if (timeout && time_after_eq(jiffies, timeout_expire)) { |
094f9a54 CW |
1271 | ret = -ETIME; |
1272 | break; | |
1273 | } | |
1274 | ||
1275 | timer.function = NULL; | |
1276 | if (timeout || missed_irq(dev_priv, ring)) { | |
47e9766d MK |
1277 | unsigned long expire; |
1278 | ||
094f9a54 | 1279 | setup_timer_on_stack(&timer, fake_irq, (unsigned long)current); |
47e9766d | 1280 | expire = missed_irq(dev_priv, ring) ? jiffies + 1 : timeout_expire; |
094f9a54 CW |
1281 | mod_timer(&timer, expire); |
1282 | } | |
1283 | ||
5035c275 | 1284 | io_schedule(); |
094f9a54 | 1285 | |
094f9a54 CW |
1286 | if (timer.function) { |
1287 | del_singleshot_timer_sync(&timer); | |
1288 | destroy_timer_on_stack(&timer); | |
1289 | } | |
1290 | } | |
5ed0bdf2 | 1291 | now = ktime_get_raw_ns(); |
74328ee5 | 1292 | trace_i915_gem_request_wait_end(req); |
b361237b | 1293 | |
168c3f21 MK |
1294 | if (!irq_test_in_progress) |
1295 | ring->irq_put(ring); | |
094f9a54 CW |
1296 | |
1297 | finish_wait(&ring->irq_queue, &wait); | |
b361237b CW |
1298 | |
1299 | if (timeout) { | |
5ed0bdf2 TG |
1300 | s64 tres = *timeout - (now - before); |
1301 | ||
1302 | *timeout = tres < 0 ? 0 : tres; | |
9cca3068 DV |
1303 | |
1304 | /* | |
1305 | * Apparently ktime isn't accurate enough and occasionally has a | |
1306 | * bit of mismatch in the jiffies<->nsecs<->ktime loop. So patch | |
1307 | * things up to make the test happy. We allow up to 1 jiffy. | |
1308 | * | |
1309 | * This is a regrssion from the timespec->ktime conversion. | |
1310 | */ | |
1311 | if (ret == -ETIME && *timeout < jiffies_to_usecs(1)*1000) | |
1312 | *timeout = 0; | |
b361237b CW |
1313 | } |
1314 | ||
094f9a54 | 1315 | return ret; |
b361237b CW |
1316 | } |
1317 | ||
1318 | /** | |
a4b3a571 | 1319 | * Waits for a request to be signaled, and cleans up the |
b361237b CW |
1320 | * request and object lists appropriately for that event. |
1321 | */ | |
1322 | int | |
a4b3a571 | 1323 | i915_wait_request(struct drm_i915_gem_request *req) |
b361237b | 1324 | { |
a4b3a571 DV |
1325 | struct drm_device *dev; |
1326 | struct drm_i915_private *dev_priv; | |
1327 | bool interruptible; | |
16e9a21f | 1328 | unsigned reset_counter; |
b361237b CW |
1329 | int ret; |
1330 | ||
a4b3a571 DV |
1331 | BUG_ON(req == NULL); |
1332 | ||
1333 | dev = req->ring->dev; | |
1334 | dev_priv = dev->dev_private; | |
1335 | interruptible = dev_priv->mm.interruptible; | |
1336 | ||
b361237b | 1337 | BUG_ON(!mutex_is_locked(&dev->struct_mutex)); |
b361237b | 1338 | |
33196ded | 1339 | ret = i915_gem_check_wedge(&dev_priv->gpu_error, interruptible); |
b361237b CW |
1340 | if (ret) |
1341 | return ret; | |
1342 | ||
a4b3a571 | 1343 | ret = i915_gem_check_olr(req); |
b361237b CW |
1344 | if (ret) |
1345 | return ret; | |
1346 | ||
16e9a21f | 1347 | reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter); |
a4b3a571 | 1348 | i915_gem_request_reference(req); |
9c654818 JH |
1349 | ret = __i915_wait_request(req, reset_counter, |
1350 | interruptible, NULL, NULL); | |
a4b3a571 DV |
1351 | i915_gem_request_unreference(req); |
1352 | return ret; | |
b361237b CW |
1353 | } |
1354 | ||
d26e3af8 | 1355 | static int |
8e639549 | 1356 | i915_gem_object_wait_rendering__tail(struct drm_i915_gem_object *obj) |
d26e3af8 | 1357 | { |
c8725f3d CW |
1358 | if (!obj->active) |
1359 | return 0; | |
d26e3af8 CW |
1360 | |
1361 | /* Manually manage the write flush as we may have not yet | |
1362 | * retired the buffer. | |
1363 | * | |
97b2a6a1 JH |
1364 | * Note that the last_write_req is always the earlier of |
1365 | * the two (read/write) requests, so if we haved successfully waited, | |
d26e3af8 CW |
1366 | * we know we have passed the last write. |
1367 | */ | |
97b2a6a1 | 1368 | i915_gem_request_assign(&obj->last_write_req, NULL); |
d26e3af8 CW |
1369 | |
1370 | return 0; | |
1371 | } | |
1372 | ||
b361237b CW |
1373 | /** |
1374 | * Ensures that all rendering to the object has completed and the object is | |
1375 | * safe to unbind from the GTT or access from the CPU. | |
1376 | */ | |
1377 | static __must_check int | |
1378 | i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj, | |
1379 | bool readonly) | |
1380 | { | |
97b2a6a1 | 1381 | struct drm_i915_gem_request *req; |
b361237b CW |
1382 | int ret; |
1383 | ||
97b2a6a1 JH |
1384 | req = readonly ? obj->last_write_req : obj->last_read_req; |
1385 | if (!req) | |
b361237b CW |
1386 | return 0; |
1387 | ||
a4b3a571 | 1388 | ret = i915_wait_request(req); |
b361237b CW |
1389 | if (ret) |
1390 | return ret; | |
1391 | ||
8e639549 | 1392 | return i915_gem_object_wait_rendering__tail(obj); |
b361237b CW |
1393 | } |
1394 | ||
3236f57a CW |
1395 | /* A nonblocking variant of the above wait. This is a highly dangerous routine |
1396 | * as the object state may change during this call. | |
1397 | */ | |
1398 | static __must_check int | |
1399 | i915_gem_object_wait_rendering__nonblocking(struct drm_i915_gem_object *obj, | |
6e4930f6 | 1400 | struct drm_i915_file_private *file_priv, |
3236f57a CW |
1401 | bool readonly) |
1402 | { | |
97b2a6a1 | 1403 | struct drm_i915_gem_request *req; |
3236f57a CW |
1404 | struct drm_device *dev = obj->base.dev; |
1405 | struct drm_i915_private *dev_priv = dev->dev_private; | |
f69061be | 1406 | unsigned reset_counter; |
3236f57a CW |
1407 | int ret; |
1408 | ||
1409 | BUG_ON(!mutex_is_locked(&dev->struct_mutex)); | |
1410 | BUG_ON(!dev_priv->mm.interruptible); | |
1411 | ||
97b2a6a1 JH |
1412 | req = readonly ? obj->last_write_req : obj->last_read_req; |
1413 | if (!req) | |
3236f57a CW |
1414 | return 0; |
1415 | ||
33196ded | 1416 | ret = i915_gem_check_wedge(&dev_priv->gpu_error, true); |
3236f57a CW |
1417 | if (ret) |
1418 | return ret; | |
1419 | ||
b6660d59 | 1420 | ret = i915_gem_check_olr(req); |
3236f57a CW |
1421 | if (ret) |
1422 | return ret; | |
1423 | ||
f69061be | 1424 | reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter); |
ff865885 | 1425 | i915_gem_request_reference(req); |
3236f57a | 1426 | mutex_unlock(&dev->struct_mutex); |
9c654818 | 1427 | ret = __i915_wait_request(req, reset_counter, true, NULL, file_priv); |
3236f57a | 1428 | mutex_lock(&dev->struct_mutex); |
ff865885 | 1429 | i915_gem_request_unreference(req); |
d26e3af8 CW |
1430 | if (ret) |
1431 | return ret; | |
3236f57a | 1432 | |
8e639549 | 1433 | return i915_gem_object_wait_rendering__tail(obj); |
3236f57a CW |
1434 | } |
1435 | ||
673a394b | 1436 | /** |
2ef7eeaa EA |
1437 | * Called when user space prepares to use an object with the CPU, either |
1438 | * through the mmap ioctl's mapping or a GTT mapping. | |
673a394b EA |
1439 | */ |
1440 | int | |
1441 | i915_gem_set_domain_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 1442 | struct drm_file *file) |
673a394b EA |
1443 | { |
1444 | struct drm_i915_gem_set_domain *args = data; | |
05394f39 | 1445 | struct drm_i915_gem_object *obj; |
2ef7eeaa EA |
1446 | uint32_t read_domains = args->read_domains; |
1447 | uint32_t write_domain = args->write_domain; | |
673a394b EA |
1448 | int ret; |
1449 | ||
2ef7eeaa | 1450 | /* Only handle setting domains to types used by the CPU. */ |
21d509e3 | 1451 | if (write_domain & I915_GEM_GPU_DOMAINS) |
2ef7eeaa EA |
1452 | return -EINVAL; |
1453 | ||
21d509e3 | 1454 | if (read_domains & I915_GEM_GPU_DOMAINS) |
2ef7eeaa EA |
1455 | return -EINVAL; |
1456 | ||
1457 | /* Having something in the write domain implies it's in the read | |
1458 | * domain, and only that read domain. Enforce that in the request. | |
1459 | */ | |
1460 | if (write_domain != 0 && read_domains != write_domain) | |
1461 | return -EINVAL; | |
1462 | ||
76c1dec1 | 1463 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 1464 | if (ret) |
76c1dec1 | 1465 | return ret; |
1d7cfea1 | 1466 | |
05394f39 | 1467 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 1468 | if (&obj->base == NULL) { |
1d7cfea1 CW |
1469 | ret = -ENOENT; |
1470 | goto unlock; | |
76c1dec1 | 1471 | } |
673a394b | 1472 | |
3236f57a CW |
1473 | /* Try to flush the object off the GPU without holding the lock. |
1474 | * We will repeat the flush holding the lock in the normal manner | |
1475 | * to catch cases where we are gazumped. | |
1476 | */ | |
6e4930f6 CW |
1477 | ret = i915_gem_object_wait_rendering__nonblocking(obj, |
1478 | file->driver_priv, | |
1479 | !write_domain); | |
3236f57a CW |
1480 | if (ret) |
1481 | goto unref; | |
1482 | ||
43566ded | 1483 | if (read_domains & I915_GEM_DOMAIN_GTT) |
2ef7eeaa | 1484 | ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0); |
43566ded | 1485 | else |
e47c68e9 | 1486 | ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0); |
2ef7eeaa | 1487 | |
3236f57a | 1488 | unref: |
05394f39 | 1489 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 1490 | unlock: |
673a394b EA |
1491 | mutex_unlock(&dev->struct_mutex); |
1492 | return ret; | |
1493 | } | |
1494 | ||
1495 | /** | |
1496 | * Called when user space has done writes to this buffer | |
1497 | */ | |
1498 | int | |
1499 | i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 1500 | struct drm_file *file) |
673a394b EA |
1501 | { |
1502 | struct drm_i915_gem_sw_finish *args = data; | |
05394f39 | 1503 | struct drm_i915_gem_object *obj; |
673a394b EA |
1504 | int ret = 0; |
1505 | ||
76c1dec1 | 1506 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 1507 | if (ret) |
76c1dec1 | 1508 | return ret; |
1d7cfea1 | 1509 | |
05394f39 | 1510 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 1511 | if (&obj->base == NULL) { |
1d7cfea1 CW |
1512 | ret = -ENOENT; |
1513 | goto unlock; | |
673a394b EA |
1514 | } |
1515 | ||
673a394b | 1516 | /* Pinned buffers may be scanout, so flush the cache */ |
2c22569b | 1517 | if (obj->pin_display) |
e62b59e4 | 1518 | i915_gem_object_flush_cpu_write_domain(obj); |
e47c68e9 | 1519 | |
05394f39 | 1520 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 1521 | unlock: |
673a394b EA |
1522 | mutex_unlock(&dev->struct_mutex); |
1523 | return ret; | |
1524 | } | |
1525 | ||
1526 | /** | |
1527 | * Maps the contents of an object, returning the address it is mapped | |
1528 | * into. | |
1529 | * | |
1530 | * While the mapping holds a reference on the contents of the object, it doesn't | |
1531 | * imply a ref on the object itself. | |
34367381 DV |
1532 | * |
1533 | * IMPORTANT: | |
1534 | * | |
1535 | * DRM driver writers who look a this function as an example for how to do GEM | |
1536 | * mmap support, please don't implement mmap support like here. The modern way | |
1537 | * to implement DRM mmap support is with an mmap offset ioctl (like | |
1538 | * i915_gem_mmap_gtt) and then using the mmap syscall on the DRM fd directly. | |
1539 | * That way debug tooling like valgrind will understand what's going on, hiding | |
1540 | * the mmap call in a driver private ioctl will break that. The i915 driver only | |
1541 | * does cpu mmaps this way because we didn't know better. | |
673a394b EA |
1542 | */ |
1543 | int | |
1544 | i915_gem_mmap_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 1545 | struct drm_file *file) |
673a394b EA |
1546 | { |
1547 | struct drm_i915_gem_mmap *args = data; | |
1548 | struct drm_gem_object *obj; | |
673a394b EA |
1549 | unsigned long addr; |
1550 | ||
1816f923 AG |
1551 | if (args->flags & ~(I915_MMAP_WC)) |
1552 | return -EINVAL; | |
1553 | ||
1554 | if (args->flags & I915_MMAP_WC && !cpu_has_pat) | |
1555 | return -ENODEV; | |
1556 | ||
05394f39 | 1557 | obj = drm_gem_object_lookup(dev, file, args->handle); |
673a394b | 1558 | if (obj == NULL) |
bf79cb91 | 1559 | return -ENOENT; |
673a394b | 1560 | |
1286ff73 DV |
1561 | /* prime objects have no backing filp to GEM mmap |
1562 | * pages from. | |
1563 | */ | |
1564 | if (!obj->filp) { | |
1565 | drm_gem_object_unreference_unlocked(obj); | |
1566 | return -EINVAL; | |
1567 | } | |
1568 | ||
6be5ceb0 | 1569 | addr = vm_mmap(obj->filp, 0, args->size, |
673a394b EA |
1570 | PROT_READ | PROT_WRITE, MAP_SHARED, |
1571 | args->offset); | |
1816f923 AG |
1572 | if (args->flags & I915_MMAP_WC) { |
1573 | struct mm_struct *mm = current->mm; | |
1574 | struct vm_area_struct *vma; | |
1575 | ||
1576 | down_write(&mm->mmap_sem); | |
1577 | vma = find_vma(mm, addr); | |
1578 | if (vma) | |
1579 | vma->vm_page_prot = | |
1580 | pgprot_writecombine(vm_get_page_prot(vma->vm_flags)); | |
1581 | else | |
1582 | addr = -ENOMEM; | |
1583 | up_write(&mm->mmap_sem); | |
1584 | } | |
bc9025bd | 1585 | drm_gem_object_unreference_unlocked(obj); |
673a394b EA |
1586 | if (IS_ERR((void *)addr)) |
1587 | return addr; | |
1588 | ||
1589 | args->addr_ptr = (uint64_t) addr; | |
1590 | ||
1591 | return 0; | |
1592 | } | |
1593 | ||
de151cf6 JB |
1594 | /** |
1595 | * i915_gem_fault - fault a page into the GTT | |
1596 | * vma: VMA in question | |
1597 | * vmf: fault info | |
1598 | * | |
1599 | * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped | |
1600 | * from userspace. The fault handler takes care of binding the object to | |
1601 | * the GTT (if needed), allocating and programming a fence register (again, | |
1602 | * only if needed based on whether the old reg is still valid or the object | |
1603 | * is tiled) and inserting a new PTE into the faulting process. | |
1604 | * | |
1605 | * Note that the faulting process may involve evicting existing objects | |
1606 | * from the GTT and/or fence registers to make room. So performance may | |
1607 | * suffer if the GTT working set is large or there are few fence registers | |
1608 | * left. | |
1609 | */ | |
1610 | int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf) | |
1611 | { | |
05394f39 CW |
1612 | struct drm_i915_gem_object *obj = to_intel_bo(vma->vm_private_data); |
1613 | struct drm_device *dev = obj->base.dev; | |
3e31c6c0 | 1614 | struct drm_i915_private *dev_priv = dev->dev_private; |
de151cf6 JB |
1615 | pgoff_t page_offset; |
1616 | unsigned long pfn; | |
1617 | int ret = 0; | |
0f973f27 | 1618 | bool write = !!(vmf->flags & FAULT_FLAG_WRITE); |
de151cf6 | 1619 | |
f65c9168 PZ |
1620 | intel_runtime_pm_get(dev_priv); |
1621 | ||
de151cf6 JB |
1622 | /* We don't use vmf->pgoff since that has the fake offset */ |
1623 | page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >> | |
1624 | PAGE_SHIFT; | |
1625 | ||
d9bc7e9f CW |
1626 | ret = i915_mutex_lock_interruptible(dev); |
1627 | if (ret) | |
1628 | goto out; | |
a00b10c3 | 1629 | |
db53a302 CW |
1630 | trace_i915_gem_object_fault(obj, page_offset, true, write); |
1631 | ||
6e4930f6 CW |
1632 | /* Try to flush the object off the GPU first without holding the lock. |
1633 | * Upon reacquiring the lock, we will perform our sanity checks and then | |
1634 | * repeat the flush holding the lock in the normal manner to catch cases | |
1635 | * where we are gazumped. | |
1636 | */ | |
1637 | ret = i915_gem_object_wait_rendering__nonblocking(obj, NULL, !write); | |
1638 | if (ret) | |
1639 | goto unlock; | |
1640 | ||
eb119bd6 CW |
1641 | /* Access to snoopable pages through the GTT is incoherent. */ |
1642 | if (obj->cache_level != I915_CACHE_NONE && !HAS_LLC(dev)) { | |
ddeff6ee | 1643 | ret = -EFAULT; |
eb119bd6 CW |
1644 | goto unlock; |
1645 | } | |
1646 | ||
d9bc7e9f | 1647 | /* Now bind it into the GTT if needed */ |
1ec9e26d | 1648 | ret = i915_gem_obj_ggtt_pin(obj, 0, PIN_MAPPABLE); |
c9839303 CW |
1649 | if (ret) |
1650 | goto unlock; | |
4a684a41 | 1651 | |
c9839303 CW |
1652 | ret = i915_gem_object_set_to_gtt_domain(obj, write); |
1653 | if (ret) | |
1654 | goto unpin; | |
74898d7e | 1655 | |
06d98131 | 1656 | ret = i915_gem_object_get_fence(obj); |
d9e86c0e | 1657 | if (ret) |
c9839303 | 1658 | goto unpin; |
7d1c4804 | 1659 | |
b90b91d8 | 1660 | /* Finally, remap it using the new GTT offset */ |
f343c5f6 BW |
1661 | pfn = dev_priv->gtt.mappable_base + i915_gem_obj_ggtt_offset(obj); |
1662 | pfn >>= PAGE_SHIFT; | |
de151cf6 | 1663 | |
b90b91d8 | 1664 | if (!obj->fault_mappable) { |
beff0d0f VS |
1665 | unsigned long size = min_t(unsigned long, |
1666 | vma->vm_end - vma->vm_start, | |
1667 | obj->base.size); | |
b90b91d8 CW |
1668 | int i; |
1669 | ||
beff0d0f | 1670 | for (i = 0; i < size >> PAGE_SHIFT; i++) { |
b90b91d8 CW |
1671 | ret = vm_insert_pfn(vma, |
1672 | (unsigned long)vma->vm_start + i * PAGE_SIZE, | |
1673 | pfn + i); | |
1674 | if (ret) | |
1675 | break; | |
1676 | } | |
1677 | ||
1678 | obj->fault_mappable = true; | |
1679 | } else | |
1680 | ret = vm_insert_pfn(vma, | |
1681 | (unsigned long)vmf->virtual_address, | |
1682 | pfn + page_offset); | |
c9839303 | 1683 | unpin: |
d7f46fc4 | 1684 | i915_gem_object_ggtt_unpin(obj); |
c715089f | 1685 | unlock: |
de151cf6 | 1686 | mutex_unlock(&dev->struct_mutex); |
d9bc7e9f | 1687 | out: |
de151cf6 | 1688 | switch (ret) { |
d9bc7e9f | 1689 | case -EIO: |
2232f031 DV |
1690 | /* |
1691 | * We eat errors when the gpu is terminally wedged to avoid | |
1692 | * userspace unduly crashing (gl has no provisions for mmaps to | |
1693 | * fail). But any other -EIO isn't ours (e.g. swap in failure) | |
1694 | * and so needs to be reported. | |
1695 | */ | |
1696 | if (!i915_terminally_wedged(&dev_priv->gpu_error)) { | |
f65c9168 PZ |
1697 | ret = VM_FAULT_SIGBUS; |
1698 | break; | |
1699 | } | |
045e769a | 1700 | case -EAGAIN: |
571c608d DV |
1701 | /* |
1702 | * EAGAIN means the gpu is hung and we'll wait for the error | |
1703 | * handler to reset everything when re-faulting in | |
1704 | * i915_mutex_lock_interruptible. | |
d9bc7e9f | 1705 | */ |
c715089f CW |
1706 | case 0: |
1707 | case -ERESTARTSYS: | |
bed636ab | 1708 | case -EINTR: |
e79e0fe3 DR |
1709 | case -EBUSY: |
1710 | /* | |
1711 | * EBUSY is ok: this just means that another thread | |
1712 | * already did the job. | |
1713 | */ | |
f65c9168 PZ |
1714 | ret = VM_FAULT_NOPAGE; |
1715 | break; | |
de151cf6 | 1716 | case -ENOMEM: |
f65c9168 PZ |
1717 | ret = VM_FAULT_OOM; |
1718 | break; | |
a7c2e1aa | 1719 | case -ENOSPC: |
45d67817 | 1720 | case -EFAULT: |
f65c9168 PZ |
1721 | ret = VM_FAULT_SIGBUS; |
1722 | break; | |
de151cf6 | 1723 | default: |
a7c2e1aa | 1724 | WARN_ONCE(ret, "unhandled error in i915_gem_fault: %i\n", ret); |
f65c9168 PZ |
1725 | ret = VM_FAULT_SIGBUS; |
1726 | break; | |
de151cf6 | 1727 | } |
f65c9168 PZ |
1728 | |
1729 | intel_runtime_pm_put(dev_priv); | |
1730 | return ret; | |
de151cf6 JB |
1731 | } |
1732 | ||
901782b2 CW |
1733 | /** |
1734 | * i915_gem_release_mmap - remove physical page mappings | |
1735 | * @obj: obj in question | |
1736 | * | |
af901ca1 | 1737 | * Preserve the reservation of the mmapping with the DRM core code, but |
901782b2 CW |
1738 | * relinquish ownership of the pages back to the system. |
1739 | * | |
1740 | * It is vital that we remove the page mapping if we have mapped a tiled | |
1741 | * object through the GTT and then lose the fence register due to | |
1742 | * resource pressure. Similarly if the object has been moved out of the | |
1743 | * aperture, than pages mapped into userspace must be revoked. Removing the | |
1744 | * mapping will then trigger a page fault on the next user access, allowing | |
1745 | * fixup by i915_gem_fault(). | |
1746 | */ | |
d05ca301 | 1747 | void |
05394f39 | 1748 | i915_gem_release_mmap(struct drm_i915_gem_object *obj) |
901782b2 | 1749 | { |
6299f992 CW |
1750 | if (!obj->fault_mappable) |
1751 | return; | |
901782b2 | 1752 | |
6796cb16 DH |
1753 | drm_vma_node_unmap(&obj->base.vma_node, |
1754 | obj->base.dev->anon_inode->i_mapping); | |
6299f992 | 1755 | obj->fault_mappable = false; |
901782b2 CW |
1756 | } |
1757 | ||
eedd10f4 CW |
1758 | void |
1759 | i915_gem_release_all_mmaps(struct drm_i915_private *dev_priv) | |
1760 | { | |
1761 | struct drm_i915_gem_object *obj; | |
1762 | ||
1763 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) | |
1764 | i915_gem_release_mmap(obj); | |
1765 | } | |
1766 | ||
0fa87796 | 1767 | uint32_t |
e28f8711 | 1768 | i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode) |
92b88aeb | 1769 | { |
e28f8711 | 1770 | uint32_t gtt_size; |
92b88aeb CW |
1771 | |
1772 | if (INTEL_INFO(dev)->gen >= 4 || | |
e28f8711 CW |
1773 | tiling_mode == I915_TILING_NONE) |
1774 | return size; | |
92b88aeb CW |
1775 | |
1776 | /* Previous chips need a power-of-two fence region when tiling */ | |
1777 | if (INTEL_INFO(dev)->gen == 3) | |
e28f8711 | 1778 | gtt_size = 1024*1024; |
92b88aeb | 1779 | else |
e28f8711 | 1780 | gtt_size = 512*1024; |
92b88aeb | 1781 | |
e28f8711 CW |
1782 | while (gtt_size < size) |
1783 | gtt_size <<= 1; | |
92b88aeb | 1784 | |
e28f8711 | 1785 | return gtt_size; |
92b88aeb CW |
1786 | } |
1787 | ||
de151cf6 JB |
1788 | /** |
1789 | * i915_gem_get_gtt_alignment - return required GTT alignment for an object | |
1790 | * @obj: object to check | |
1791 | * | |
1792 | * Return the required GTT alignment for an object, taking into account | |
5e783301 | 1793 | * potential fence register mapping. |
de151cf6 | 1794 | */ |
d865110c ID |
1795 | uint32_t |
1796 | i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size, | |
1797 | int tiling_mode, bool fenced) | |
de151cf6 | 1798 | { |
de151cf6 JB |
1799 | /* |
1800 | * Minimum alignment is 4k (GTT page size), but might be greater | |
1801 | * if a fence register is needed for the object. | |
1802 | */ | |
d865110c | 1803 | if (INTEL_INFO(dev)->gen >= 4 || (!fenced && IS_G33(dev)) || |
e28f8711 | 1804 | tiling_mode == I915_TILING_NONE) |
de151cf6 JB |
1805 | return 4096; |
1806 | ||
a00b10c3 CW |
1807 | /* |
1808 | * Previous chips need to be aligned to the size of the smallest | |
1809 | * fence register that can contain the object. | |
1810 | */ | |
e28f8711 | 1811 | return i915_gem_get_gtt_size(dev, size, tiling_mode); |
a00b10c3 CW |
1812 | } |
1813 | ||
d8cb5086 CW |
1814 | static int i915_gem_object_create_mmap_offset(struct drm_i915_gem_object *obj) |
1815 | { | |
1816 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; | |
1817 | int ret; | |
1818 | ||
0de23977 | 1819 | if (drm_vma_node_has_offset(&obj->base.vma_node)) |
d8cb5086 CW |
1820 | return 0; |
1821 | ||
da494d7c DV |
1822 | dev_priv->mm.shrinker_no_lock_stealing = true; |
1823 | ||
d8cb5086 CW |
1824 | ret = drm_gem_create_mmap_offset(&obj->base); |
1825 | if (ret != -ENOSPC) | |
da494d7c | 1826 | goto out; |
d8cb5086 CW |
1827 | |
1828 | /* Badly fragmented mmap space? The only way we can recover | |
1829 | * space is by destroying unwanted objects. We can't randomly release | |
1830 | * mmap_offsets as userspace expects them to be persistent for the | |
1831 | * lifetime of the objects. The closest we can is to release the | |
1832 | * offsets on purgeable objects by truncating it and marking it purged, | |
1833 | * which prevents userspace from ever using that object again. | |
1834 | */ | |
21ab4e74 CW |
1835 | i915_gem_shrink(dev_priv, |
1836 | obj->base.size >> PAGE_SHIFT, | |
1837 | I915_SHRINK_BOUND | | |
1838 | I915_SHRINK_UNBOUND | | |
1839 | I915_SHRINK_PURGEABLE); | |
d8cb5086 CW |
1840 | ret = drm_gem_create_mmap_offset(&obj->base); |
1841 | if (ret != -ENOSPC) | |
da494d7c | 1842 | goto out; |
d8cb5086 CW |
1843 | |
1844 | i915_gem_shrink_all(dev_priv); | |
da494d7c DV |
1845 | ret = drm_gem_create_mmap_offset(&obj->base); |
1846 | out: | |
1847 | dev_priv->mm.shrinker_no_lock_stealing = false; | |
1848 | ||
1849 | return ret; | |
d8cb5086 CW |
1850 | } |
1851 | ||
1852 | static void i915_gem_object_free_mmap_offset(struct drm_i915_gem_object *obj) | |
1853 | { | |
d8cb5086 CW |
1854 | drm_gem_free_mmap_offset(&obj->base); |
1855 | } | |
1856 | ||
da6b51d0 | 1857 | int |
ff72145b DA |
1858 | i915_gem_mmap_gtt(struct drm_file *file, |
1859 | struct drm_device *dev, | |
da6b51d0 | 1860 | uint32_t handle, |
ff72145b | 1861 | uint64_t *offset) |
de151cf6 | 1862 | { |
da761a6e | 1863 | struct drm_i915_private *dev_priv = dev->dev_private; |
05394f39 | 1864 | struct drm_i915_gem_object *obj; |
de151cf6 JB |
1865 | int ret; |
1866 | ||
76c1dec1 | 1867 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 1868 | if (ret) |
76c1dec1 | 1869 | return ret; |
de151cf6 | 1870 | |
ff72145b | 1871 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle)); |
c8725226 | 1872 | if (&obj->base == NULL) { |
1d7cfea1 CW |
1873 | ret = -ENOENT; |
1874 | goto unlock; | |
1875 | } | |
de151cf6 | 1876 | |
5d4545ae | 1877 | if (obj->base.size > dev_priv->gtt.mappable_end) { |
da761a6e | 1878 | ret = -E2BIG; |
ff56b0bc | 1879 | goto out; |
da761a6e CW |
1880 | } |
1881 | ||
05394f39 | 1882 | if (obj->madv != I915_MADV_WILLNEED) { |
bd9b6a4e | 1883 | DRM_DEBUG("Attempting to mmap a purgeable buffer\n"); |
8c99e57d | 1884 | ret = -EFAULT; |
1d7cfea1 | 1885 | goto out; |
ab18282d CW |
1886 | } |
1887 | ||
d8cb5086 CW |
1888 | ret = i915_gem_object_create_mmap_offset(obj); |
1889 | if (ret) | |
1890 | goto out; | |
de151cf6 | 1891 | |
0de23977 | 1892 | *offset = drm_vma_node_offset_addr(&obj->base.vma_node); |
de151cf6 | 1893 | |
1d7cfea1 | 1894 | out: |
05394f39 | 1895 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 1896 | unlock: |
de151cf6 | 1897 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 1898 | return ret; |
de151cf6 JB |
1899 | } |
1900 | ||
ff72145b DA |
1901 | /** |
1902 | * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing | |
1903 | * @dev: DRM device | |
1904 | * @data: GTT mapping ioctl data | |
1905 | * @file: GEM object info | |
1906 | * | |
1907 | * Simply returns the fake offset to userspace so it can mmap it. | |
1908 | * The mmap call will end up in drm_gem_mmap(), which will set things | |
1909 | * up so we can get faults in the handler above. | |
1910 | * | |
1911 | * The fault handler will take care of binding the object into the GTT | |
1912 | * (since it may have been evicted to make room for something), allocating | |
1913 | * a fence register, and mapping the appropriate aperture address into | |
1914 | * userspace. | |
1915 | */ | |
1916 | int | |
1917 | i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data, | |
1918 | struct drm_file *file) | |
1919 | { | |
1920 | struct drm_i915_gem_mmap_gtt *args = data; | |
1921 | ||
da6b51d0 | 1922 | return i915_gem_mmap_gtt(file, dev, args->handle, &args->offset); |
ff72145b DA |
1923 | } |
1924 | ||
5537252b CW |
1925 | static inline int |
1926 | i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj) | |
1927 | { | |
1928 | return obj->madv == I915_MADV_DONTNEED; | |
1929 | } | |
1930 | ||
225067ee DV |
1931 | /* Immediately discard the backing storage */ |
1932 | static void | |
1933 | i915_gem_object_truncate(struct drm_i915_gem_object *obj) | |
e5281ccd | 1934 | { |
4d6294bf | 1935 | i915_gem_object_free_mmap_offset(obj); |
1286ff73 | 1936 | |
4d6294bf CW |
1937 | if (obj->base.filp == NULL) |
1938 | return; | |
e5281ccd | 1939 | |
225067ee DV |
1940 | /* Our goal here is to return as much of the memory as |
1941 | * is possible back to the system as we are called from OOM. | |
1942 | * To do this we must instruct the shmfs to drop all of its | |
1943 | * backing pages, *now*. | |
1944 | */ | |
5537252b | 1945 | shmem_truncate_range(file_inode(obj->base.filp), 0, (loff_t)-1); |
225067ee DV |
1946 | obj->madv = __I915_MADV_PURGED; |
1947 | } | |
e5281ccd | 1948 | |
5537252b CW |
1949 | /* Try to discard unwanted pages */ |
1950 | static void | |
1951 | i915_gem_object_invalidate(struct drm_i915_gem_object *obj) | |
225067ee | 1952 | { |
5537252b CW |
1953 | struct address_space *mapping; |
1954 | ||
1955 | switch (obj->madv) { | |
1956 | case I915_MADV_DONTNEED: | |
1957 | i915_gem_object_truncate(obj); | |
1958 | case __I915_MADV_PURGED: | |
1959 | return; | |
1960 | } | |
1961 | ||
1962 | if (obj->base.filp == NULL) | |
1963 | return; | |
1964 | ||
1965 | mapping = file_inode(obj->base.filp)->i_mapping, | |
1966 | invalidate_mapping_pages(mapping, 0, (loff_t)-1); | |
e5281ccd CW |
1967 | } |
1968 | ||
5cdf5881 | 1969 | static void |
05394f39 | 1970 | i915_gem_object_put_pages_gtt(struct drm_i915_gem_object *obj) |
673a394b | 1971 | { |
90797e6d ID |
1972 | struct sg_page_iter sg_iter; |
1973 | int ret; | |
1286ff73 | 1974 | |
05394f39 | 1975 | BUG_ON(obj->madv == __I915_MADV_PURGED); |
673a394b | 1976 | |
6c085a72 CW |
1977 | ret = i915_gem_object_set_to_cpu_domain(obj, true); |
1978 | if (ret) { | |
1979 | /* In the event of a disaster, abandon all caches and | |
1980 | * hope for the best. | |
1981 | */ | |
1982 | WARN_ON(ret != -EIO); | |
2c22569b | 1983 | i915_gem_clflush_object(obj, true); |
6c085a72 CW |
1984 | obj->base.read_domains = obj->base.write_domain = I915_GEM_DOMAIN_CPU; |
1985 | } | |
1986 | ||
6dacfd2f | 1987 | if (i915_gem_object_needs_bit17_swizzle(obj)) |
280b713b EA |
1988 | i915_gem_object_save_bit_17_swizzle(obj); |
1989 | ||
05394f39 CW |
1990 | if (obj->madv == I915_MADV_DONTNEED) |
1991 | obj->dirty = 0; | |
3ef94daa | 1992 | |
90797e6d | 1993 | for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, 0) { |
2db76d7c | 1994 | struct page *page = sg_page_iter_page(&sg_iter); |
9da3da66 | 1995 | |
05394f39 | 1996 | if (obj->dirty) |
9da3da66 | 1997 | set_page_dirty(page); |
3ef94daa | 1998 | |
05394f39 | 1999 | if (obj->madv == I915_MADV_WILLNEED) |
9da3da66 | 2000 | mark_page_accessed(page); |
3ef94daa | 2001 | |
9da3da66 | 2002 | page_cache_release(page); |
3ef94daa | 2003 | } |
05394f39 | 2004 | obj->dirty = 0; |
673a394b | 2005 | |
9da3da66 CW |
2006 | sg_free_table(obj->pages); |
2007 | kfree(obj->pages); | |
37e680a1 | 2008 | } |
6c085a72 | 2009 | |
dd624afd | 2010 | int |
37e680a1 CW |
2011 | i915_gem_object_put_pages(struct drm_i915_gem_object *obj) |
2012 | { | |
2013 | const struct drm_i915_gem_object_ops *ops = obj->ops; | |
2014 | ||
2f745ad3 | 2015 | if (obj->pages == NULL) |
37e680a1 CW |
2016 | return 0; |
2017 | ||
a5570178 CW |
2018 | if (obj->pages_pin_count) |
2019 | return -EBUSY; | |
2020 | ||
9843877d | 2021 | BUG_ON(i915_gem_obj_bound_any(obj)); |
3e123027 | 2022 | |
a2165e31 CW |
2023 | /* ->put_pages might need to allocate memory for the bit17 swizzle |
2024 | * array, hence protect them from being reaped by removing them from gtt | |
2025 | * lists early. */ | |
35c20a60 | 2026 | list_del(&obj->global_list); |
a2165e31 | 2027 | |
37e680a1 | 2028 | ops->put_pages(obj); |
05394f39 | 2029 | obj->pages = NULL; |
37e680a1 | 2030 | |
5537252b | 2031 | i915_gem_object_invalidate(obj); |
6c085a72 CW |
2032 | |
2033 | return 0; | |
2034 | } | |
2035 | ||
21ab4e74 CW |
2036 | unsigned long |
2037 | i915_gem_shrink(struct drm_i915_private *dev_priv, | |
2038 | long target, unsigned flags) | |
6c085a72 | 2039 | { |
60a53727 CW |
2040 | const struct { |
2041 | struct list_head *list; | |
2042 | unsigned int bit; | |
2043 | } phases[] = { | |
2044 | { &dev_priv->mm.unbound_list, I915_SHRINK_UNBOUND }, | |
2045 | { &dev_priv->mm.bound_list, I915_SHRINK_BOUND }, | |
2046 | { NULL, 0 }, | |
2047 | }, *phase; | |
d9973b43 | 2048 | unsigned long count = 0; |
6c085a72 | 2049 | |
57094f82 | 2050 | /* |
c8725f3d | 2051 | * As we may completely rewrite the (un)bound list whilst unbinding |
57094f82 CW |
2052 | * (due to retiring requests) we have to strictly process only |
2053 | * one element of the list at the time, and recheck the list | |
2054 | * on every iteration. | |
c8725f3d CW |
2055 | * |
2056 | * In particular, we must hold a reference whilst removing the | |
2057 | * object as we may end up waiting for and/or retiring the objects. | |
2058 | * This might release the final reference (held by the active list) | |
2059 | * and result in the object being freed from under us. This is | |
2060 | * similar to the precautions the eviction code must take whilst | |
2061 | * removing objects. | |
2062 | * | |
2063 | * Also note that although these lists do not hold a reference to | |
2064 | * the object we can safely grab one here: The final object | |
2065 | * unreferencing and the bound_list are both protected by the | |
2066 | * dev->struct_mutex and so we won't ever be able to observe an | |
2067 | * object on the bound_list with a reference count equals 0. | |
57094f82 | 2068 | */ |
60a53727 | 2069 | for (phase = phases; phase->list; phase++) { |
21ab4e74 | 2070 | struct list_head still_in_list; |
c8725f3d | 2071 | |
60a53727 CW |
2072 | if ((flags & phase->bit) == 0) |
2073 | continue; | |
80dcfdbd | 2074 | |
21ab4e74 | 2075 | INIT_LIST_HEAD(&still_in_list); |
60a53727 | 2076 | while (count < target && !list_empty(phase->list)) { |
21ab4e74 CW |
2077 | struct drm_i915_gem_object *obj; |
2078 | struct i915_vma *vma, *v; | |
57094f82 | 2079 | |
60a53727 | 2080 | obj = list_first_entry(phase->list, |
21ab4e74 CW |
2081 | typeof(*obj), global_list); |
2082 | list_move_tail(&obj->global_list, &still_in_list); | |
80dcfdbd | 2083 | |
60a53727 CW |
2084 | if (flags & I915_SHRINK_PURGEABLE && |
2085 | !i915_gem_object_is_purgeable(obj)) | |
21ab4e74 | 2086 | continue; |
57094f82 | 2087 | |
21ab4e74 | 2088 | drm_gem_object_reference(&obj->base); |
80dcfdbd | 2089 | |
60a53727 CW |
2090 | /* For the unbound phase, this should be a no-op! */ |
2091 | list_for_each_entry_safe(vma, v, | |
2092 | &obj->vma_list, vma_link) | |
21ab4e74 CW |
2093 | if (i915_vma_unbind(vma)) |
2094 | break; | |
57094f82 | 2095 | |
21ab4e74 CW |
2096 | if (i915_gem_object_put_pages(obj) == 0) |
2097 | count += obj->base.size >> PAGE_SHIFT; | |
2098 | ||
2099 | drm_gem_object_unreference(&obj->base); | |
2100 | } | |
60a53727 | 2101 | list_splice(&still_in_list, phase->list); |
6c085a72 CW |
2102 | } |
2103 | ||
2104 | return count; | |
2105 | } | |
2106 | ||
d9973b43 | 2107 | static unsigned long |
6c085a72 CW |
2108 | i915_gem_shrink_all(struct drm_i915_private *dev_priv) |
2109 | { | |
6c085a72 | 2110 | i915_gem_evict_everything(dev_priv->dev); |
21ab4e74 CW |
2111 | return i915_gem_shrink(dev_priv, LONG_MAX, |
2112 | I915_SHRINK_BOUND | I915_SHRINK_UNBOUND); | |
225067ee DV |
2113 | } |
2114 | ||
37e680a1 | 2115 | static int |
6c085a72 | 2116 | i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj) |
e5281ccd | 2117 | { |
6c085a72 | 2118 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
e5281ccd CW |
2119 | int page_count, i; |
2120 | struct address_space *mapping; | |
9da3da66 CW |
2121 | struct sg_table *st; |
2122 | struct scatterlist *sg; | |
90797e6d | 2123 | struct sg_page_iter sg_iter; |
e5281ccd | 2124 | struct page *page; |
90797e6d | 2125 | unsigned long last_pfn = 0; /* suppress gcc warning */ |
6c085a72 | 2126 | gfp_t gfp; |
e5281ccd | 2127 | |
6c085a72 CW |
2128 | /* Assert that the object is not currently in any GPU domain. As it |
2129 | * wasn't in the GTT, there shouldn't be any way it could have been in | |
2130 | * a GPU cache | |
2131 | */ | |
2132 | BUG_ON(obj->base.read_domains & I915_GEM_GPU_DOMAINS); | |
2133 | BUG_ON(obj->base.write_domain & I915_GEM_GPU_DOMAINS); | |
2134 | ||
9da3da66 CW |
2135 | st = kmalloc(sizeof(*st), GFP_KERNEL); |
2136 | if (st == NULL) | |
2137 | return -ENOMEM; | |
2138 | ||
05394f39 | 2139 | page_count = obj->base.size / PAGE_SIZE; |
9da3da66 | 2140 | if (sg_alloc_table(st, page_count, GFP_KERNEL)) { |
9da3da66 | 2141 | kfree(st); |
e5281ccd | 2142 | return -ENOMEM; |
9da3da66 | 2143 | } |
e5281ccd | 2144 | |
9da3da66 CW |
2145 | /* Get the list of pages out of our struct file. They'll be pinned |
2146 | * at this point until we release them. | |
2147 | * | |
2148 | * Fail silently without starting the shrinker | |
2149 | */ | |
496ad9aa | 2150 | mapping = file_inode(obj->base.filp)->i_mapping; |
6c085a72 | 2151 | gfp = mapping_gfp_mask(mapping); |
caf49191 | 2152 | gfp |= __GFP_NORETRY | __GFP_NOWARN | __GFP_NO_KSWAPD; |
6c085a72 | 2153 | gfp &= ~(__GFP_IO | __GFP_WAIT); |
90797e6d ID |
2154 | sg = st->sgl; |
2155 | st->nents = 0; | |
2156 | for (i = 0; i < page_count; i++) { | |
6c085a72 CW |
2157 | page = shmem_read_mapping_page_gfp(mapping, i, gfp); |
2158 | if (IS_ERR(page)) { | |
21ab4e74 CW |
2159 | i915_gem_shrink(dev_priv, |
2160 | page_count, | |
2161 | I915_SHRINK_BOUND | | |
2162 | I915_SHRINK_UNBOUND | | |
2163 | I915_SHRINK_PURGEABLE); | |
6c085a72 CW |
2164 | page = shmem_read_mapping_page_gfp(mapping, i, gfp); |
2165 | } | |
2166 | if (IS_ERR(page)) { | |
2167 | /* We've tried hard to allocate the memory by reaping | |
2168 | * our own buffer, now let the real VM do its job and | |
2169 | * go down in flames if truly OOM. | |
2170 | */ | |
6c085a72 | 2171 | i915_gem_shrink_all(dev_priv); |
f461d1be | 2172 | page = shmem_read_mapping_page(mapping, i); |
6c085a72 CW |
2173 | if (IS_ERR(page)) |
2174 | goto err_pages; | |
6c085a72 | 2175 | } |
426729dc KRW |
2176 | #ifdef CONFIG_SWIOTLB |
2177 | if (swiotlb_nr_tbl()) { | |
2178 | st->nents++; | |
2179 | sg_set_page(sg, page, PAGE_SIZE, 0); | |
2180 | sg = sg_next(sg); | |
2181 | continue; | |
2182 | } | |
2183 | #endif | |
90797e6d ID |
2184 | if (!i || page_to_pfn(page) != last_pfn + 1) { |
2185 | if (i) | |
2186 | sg = sg_next(sg); | |
2187 | st->nents++; | |
2188 | sg_set_page(sg, page, PAGE_SIZE, 0); | |
2189 | } else { | |
2190 | sg->length += PAGE_SIZE; | |
2191 | } | |
2192 | last_pfn = page_to_pfn(page); | |
3bbbe706 DV |
2193 | |
2194 | /* Check that the i965g/gm workaround works. */ | |
2195 | WARN_ON((gfp & __GFP_DMA32) && (last_pfn >= 0x00100000UL)); | |
e5281ccd | 2196 | } |
426729dc KRW |
2197 | #ifdef CONFIG_SWIOTLB |
2198 | if (!swiotlb_nr_tbl()) | |
2199 | #endif | |
2200 | sg_mark_end(sg); | |
74ce6b6c CW |
2201 | obj->pages = st; |
2202 | ||
6dacfd2f | 2203 | if (i915_gem_object_needs_bit17_swizzle(obj)) |
e5281ccd CW |
2204 | i915_gem_object_do_bit_17_swizzle(obj); |
2205 | ||
656bfa3a DV |
2206 | if (obj->tiling_mode != I915_TILING_NONE && |
2207 | dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES) | |
2208 | i915_gem_object_pin_pages(obj); | |
2209 | ||
e5281ccd CW |
2210 | return 0; |
2211 | ||
2212 | err_pages: | |
90797e6d ID |
2213 | sg_mark_end(sg); |
2214 | for_each_sg_page(st->sgl, &sg_iter, st->nents, 0) | |
2db76d7c | 2215 | page_cache_release(sg_page_iter_page(&sg_iter)); |
9da3da66 CW |
2216 | sg_free_table(st); |
2217 | kfree(st); | |
0820baf3 CW |
2218 | |
2219 | /* shmemfs first checks if there is enough memory to allocate the page | |
2220 | * and reports ENOSPC should there be insufficient, along with the usual | |
2221 | * ENOMEM for a genuine allocation failure. | |
2222 | * | |
2223 | * We use ENOSPC in our driver to mean that we have run out of aperture | |
2224 | * space and so want to translate the error from shmemfs back to our | |
2225 | * usual understanding of ENOMEM. | |
2226 | */ | |
2227 | if (PTR_ERR(page) == -ENOSPC) | |
2228 | return -ENOMEM; | |
2229 | else | |
2230 | return PTR_ERR(page); | |
673a394b EA |
2231 | } |
2232 | ||
37e680a1 CW |
2233 | /* Ensure that the associated pages are gathered from the backing storage |
2234 | * and pinned into our object. i915_gem_object_get_pages() may be called | |
2235 | * multiple times before they are released by a single call to | |
2236 | * i915_gem_object_put_pages() - once the pages are no longer referenced | |
2237 | * either as a result of memory pressure (reaping pages under the shrinker) | |
2238 | * or as the object is itself released. | |
2239 | */ | |
2240 | int | |
2241 | i915_gem_object_get_pages(struct drm_i915_gem_object *obj) | |
2242 | { | |
2243 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; | |
2244 | const struct drm_i915_gem_object_ops *ops = obj->ops; | |
2245 | int ret; | |
2246 | ||
2f745ad3 | 2247 | if (obj->pages) |
37e680a1 CW |
2248 | return 0; |
2249 | ||
43e28f09 | 2250 | if (obj->madv != I915_MADV_WILLNEED) { |
bd9b6a4e | 2251 | DRM_DEBUG("Attempting to obtain a purgeable object\n"); |
8c99e57d | 2252 | return -EFAULT; |
43e28f09 CW |
2253 | } |
2254 | ||
a5570178 CW |
2255 | BUG_ON(obj->pages_pin_count); |
2256 | ||
37e680a1 CW |
2257 | ret = ops->get_pages(obj); |
2258 | if (ret) | |
2259 | return ret; | |
2260 | ||
35c20a60 | 2261 | list_add_tail(&obj->global_list, &dev_priv->mm.unbound_list); |
37e680a1 | 2262 | return 0; |
673a394b EA |
2263 | } |
2264 | ||
e2d05a8b | 2265 | static void |
05394f39 | 2266 | i915_gem_object_move_to_active(struct drm_i915_gem_object *obj, |
a4872ba6 | 2267 | struct intel_engine_cs *ring) |
673a394b | 2268 | { |
41c52415 JH |
2269 | struct drm_i915_gem_request *req; |
2270 | struct intel_engine_cs *old_ring; | |
617dbe27 | 2271 | |
852835f3 | 2272 | BUG_ON(ring == NULL); |
41c52415 JH |
2273 | |
2274 | req = intel_ring_get_request(ring); | |
2275 | old_ring = i915_gem_request_get_ring(obj->last_read_req); | |
2276 | ||
2277 | if (old_ring != ring && obj->last_write_req) { | |
97b2a6a1 JH |
2278 | /* Keep the request relative to the current ring */ |
2279 | i915_gem_request_assign(&obj->last_write_req, req); | |
02978ff5 | 2280 | } |
673a394b EA |
2281 | |
2282 | /* Add a reference if we're newly entering the active list. */ | |
05394f39 CW |
2283 | if (!obj->active) { |
2284 | drm_gem_object_reference(&obj->base); | |
2285 | obj->active = 1; | |
673a394b | 2286 | } |
e35a41de | 2287 | |
05394f39 | 2288 | list_move_tail(&obj->ring_list, &ring->active_list); |
caea7476 | 2289 | |
97b2a6a1 | 2290 | i915_gem_request_assign(&obj->last_read_req, req); |
caea7476 CW |
2291 | } |
2292 | ||
e2d05a8b | 2293 | void i915_vma_move_to_active(struct i915_vma *vma, |
a4872ba6 | 2294 | struct intel_engine_cs *ring) |
e2d05a8b BW |
2295 | { |
2296 | list_move_tail(&vma->mm_list, &vma->vm->active_list); | |
2297 | return i915_gem_object_move_to_active(vma->obj, ring); | |
2298 | } | |
2299 | ||
caea7476 | 2300 | static void |
caea7476 | 2301 | i915_gem_object_move_to_inactive(struct drm_i915_gem_object *obj) |
ce44b0ea | 2302 | { |
feb822cf | 2303 | struct i915_vma *vma; |
ce44b0ea | 2304 | |
65ce3027 | 2305 | BUG_ON(obj->base.write_domain & ~I915_GEM_GPU_DOMAINS); |
05394f39 | 2306 | BUG_ON(!obj->active); |
caea7476 | 2307 | |
fe14d5f4 TU |
2308 | list_for_each_entry(vma, &obj->vma_list, vma_link) { |
2309 | if (!list_empty(&vma->mm_list)) | |
2310 | list_move_tail(&vma->mm_list, &vma->vm->inactive_list); | |
feb822cf | 2311 | } |
caea7476 | 2312 | |
f99d7069 DV |
2313 | intel_fb_obj_flush(obj, true); |
2314 | ||
65ce3027 | 2315 | list_del_init(&obj->ring_list); |
caea7476 | 2316 | |
97b2a6a1 JH |
2317 | i915_gem_request_assign(&obj->last_read_req, NULL); |
2318 | i915_gem_request_assign(&obj->last_write_req, NULL); | |
65ce3027 CW |
2319 | obj->base.write_domain = 0; |
2320 | ||
97b2a6a1 | 2321 | i915_gem_request_assign(&obj->last_fenced_req, NULL); |
caea7476 CW |
2322 | |
2323 | obj->active = 0; | |
2324 | drm_gem_object_unreference(&obj->base); | |
2325 | ||
2326 | WARN_ON(i915_verify_lists(dev)); | |
ce44b0ea | 2327 | } |
673a394b | 2328 | |
c8725f3d CW |
2329 | static void |
2330 | i915_gem_object_retire(struct drm_i915_gem_object *obj) | |
2331 | { | |
41c52415 | 2332 | if (obj->last_read_req == NULL) |
c8725f3d CW |
2333 | return; |
2334 | ||
1b5a433a | 2335 | if (i915_gem_request_completed(obj->last_read_req, true)) |
c8725f3d CW |
2336 | i915_gem_object_move_to_inactive(obj); |
2337 | } | |
2338 | ||
9d773091 | 2339 | static int |
fca26bb4 | 2340 | i915_gem_init_seqno(struct drm_device *dev, u32 seqno) |
53d227f2 | 2341 | { |
9d773091 | 2342 | struct drm_i915_private *dev_priv = dev->dev_private; |
a4872ba6 | 2343 | struct intel_engine_cs *ring; |
9d773091 | 2344 | int ret, i, j; |
53d227f2 | 2345 | |
107f27a5 | 2346 | /* Carefully retire all requests without writing to the rings */ |
9d773091 | 2347 | for_each_ring(ring, dev_priv, i) { |
107f27a5 CW |
2348 | ret = intel_ring_idle(ring); |
2349 | if (ret) | |
2350 | return ret; | |
9d773091 | 2351 | } |
9d773091 | 2352 | i915_gem_retire_requests(dev); |
107f27a5 CW |
2353 | |
2354 | /* Finally reset hw state */ | |
9d773091 | 2355 | for_each_ring(ring, dev_priv, i) { |
fca26bb4 | 2356 | intel_ring_init_seqno(ring, seqno); |
498d2ac1 | 2357 | |
ebc348b2 BW |
2358 | for (j = 0; j < ARRAY_SIZE(ring->semaphore.sync_seqno); j++) |
2359 | ring->semaphore.sync_seqno[j] = 0; | |
9d773091 | 2360 | } |
53d227f2 | 2361 | |
9d773091 | 2362 | return 0; |
53d227f2 DV |
2363 | } |
2364 | ||
fca26bb4 MK |
2365 | int i915_gem_set_seqno(struct drm_device *dev, u32 seqno) |
2366 | { | |
2367 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2368 | int ret; | |
2369 | ||
2370 | if (seqno == 0) | |
2371 | return -EINVAL; | |
2372 | ||
2373 | /* HWS page needs to be set less than what we | |
2374 | * will inject to ring | |
2375 | */ | |
2376 | ret = i915_gem_init_seqno(dev, seqno - 1); | |
2377 | if (ret) | |
2378 | return ret; | |
2379 | ||
2380 | /* Carefully set the last_seqno value so that wrap | |
2381 | * detection still works | |
2382 | */ | |
2383 | dev_priv->next_seqno = seqno; | |
2384 | dev_priv->last_seqno = seqno - 1; | |
2385 | if (dev_priv->last_seqno == 0) | |
2386 | dev_priv->last_seqno--; | |
2387 | ||
2388 | return 0; | |
2389 | } | |
2390 | ||
9d773091 CW |
2391 | int |
2392 | i915_gem_get_seqno(struct drm_device *dev, u32 *seqno) | |
53d227f2 | 2393 | { |
9d773091 CW |
2394 | struct drm_i915_private *dev_priv = dev->dev_private; |
2395 | ||
2396 | /* reserve 0 for non-seqno */ | |
2397 | if (dev_priv->next_seqno == 0) { | |
fca26bb4 | 2398 | int ret = i915_gem_init_seqno(dev, 0); |
9d773091 CW |
2399 | if (ret) |
2400 | return ret; | |
53d227f2 | 2401 | |
9d773091 CW |
2402 | dev_priv->next_seqno = 1; |
2403 | } | |
53d227f2 | 2404 | |
f72b3435 | 2405 | *seqno = dev_priv->last_seqno = dev_priv->next_seqno++; |
9d773091 | 2406 | return 0; |
53d227f2 DV |
2407 | } |
2408 | ||
a4872ba6 | 2409 | int __i915_add_request(struct intel_engine_cs *ring, |
0025c077 | 2410 | struct drm_file *file, |
9400ae5c | 2411 | struct drm_i915_gem_object *obj) |
673a394b | 2412 | { |
3e31c6c0 | 2413 | struct drm_i915_private *dev_priv = ring->dev->dev_private; |
acb868d3 | 2414 | struct drm_i915_gem_request *request; |
48e29f55 | 2415 | struct intel_ringbuffer *ringbuf; |
6d3d8274 | 2416 | u32 request_start; |
3cce469c CW |
2417 | int ret; |
2418 | ||
6259cead | 2419 | request = ring->outstanding_lazy_request; |
48e29f55 OM |
2420 | if (WARN_ON(request == NULL)) |
2421 | return -ENOMEM; | |
2422 | ||
2423 | if (i915.enable_execlists) { | |
21076372 | 2424 | ringbuf = request->ctx->engine[ring->id].ringbuf; |
48e29f55 OM |
2425 | } else |
2426 | ringbuf = ring->buffer; | |
2427 | ||
2428 | request_start = intel_ring_get_tail(ringbuf); | |
cc889e0f DV |
2429 | /* |
2430 | * Emit any outstanding flushes - execbuf can fail to emit the flush | |
2431 | * after having emitted the batchbuffer command. Hence we need to fix | |
2432 | * things up similar to emitting the lazy request. The difference here | |
2433 | * is that the flush _must_ happen before the next request, no matter | |
2434 | * what. | |
2435 | */ | |
48e29f55 | 2436 | if (i915.enable_execlists) { |
21076372 | 2437 | ret = logical_ring_flush_all_caches(ringbuf, request->ctx); |
48e29f55 OM |
2438 | if (ret) |
2439 | return ret; | |
2440 | } else { | |
2441 | ret = intel_ring_flush_all_caches(ring); | |
2442 | if (ret) | |
2443 | return ret; | |
2444 | } | |
cc889e0f | 2445 | |
a71d8d94 CW |
2446 | /* Record the position of the start of the request so that |
2447 | * should we detect the updated seqno part-way through the | |
2448 | * GPU processing the request, we never over-estimate the | |
2449 | * position of the head. | |
2450 | */ | |
6d3d8274 | 2451 | request->postfix = intel_ring_get_tail(ringbuf); |
a71d8d94 | 2452 | |
48e29f55 | 2453 | if (i915.enable_execlists) { |
72f95afa | 2454 | ret = ring->emit_request(ringbuf, request); |
48e29f55 OM |
2455 | if (ret) |
2456 | return ret; | |
2457 | } else { | |
2458 | ret = ring->add_request(ring); | |
2459 | if (ret) | |
2460 | return ret; | |
2461 | } | |
673a394b | 2462 | |
7d736f4f | 2463 | request->head = request_start; |
6d3d8274 | 2464 | request->tail = intel_ring_get_tail(ringbuf); |
7d736f4f MK |
2465 | |
2466 | /* Whilst this request exists, batch_obj will be on the | |
2467 | * active_list, and so will hold the active reference. Only when this | |
2468 | * request is retired will the the batch_obj be moved onto the | |
2469 | * inactive_list and lose its active reference. Hence we do not need | |
2470 | * to explicitly hold another reference here. | |
2471 | */ | |
9a7e0c2a | 2472 | request->batch_obj = obj; |
0e50e96b | 2473 | |
48e29f55 OM |
2474 | if (!i915.enable_execlists) { |
2475 | /* Hold a reference to the current context so that we can inspect | |
2476 | * it later in case a hangcheck error event fires. | |
2477 | */ | |
2478 | request->ctx = ring->last_context; | |
2479 | if (request->ctx) | |
2480 | i915_gem_context_reference(request->ctx); | |
2481 | } | |
0e50e96b | 2482 | |
673a394b | 2483 | request->emitted_jiffies = jiffies; |
852835f3 | 2484 | list_add_tail(&request->list, &ring->request_list); |
3bb73aba | 2485 | request->file_priv = NULL; |
852835f3 | 2486 | |
db53a302 CW |
2487 | if (file) { |
2488 | struct drm_i915_file_private *file_priv = file->driver_priv; | |
2489 | ||
1c25595f | 2490 | spin_lock(&file_priv->mm.lock); |
f787a5f5 | 2491 | request->file_priv = file_priv; |
b962442e | 2492 | list_add_tail(&request->client_list, |
f787a5f5 | 2493 | &file_priv->mm.request_list); |
1c25595f | 2494 | spin_unlock(&file_priv->mm.lock); |
b962442e | 2495 | } |
673a394b | 2496 | |
74328ee5 | 2497 | trace_i915_gem_request_add(request); |
6259cead | 2498 | ring->outstanding_lazy_request = NULL; |
db53a302 | 2499 | |
87255483 | 2500 | i915_queue_hangcheck(ring->dev); |
10cd45b6 | 2501 | |
87255483 DV |
2502 | cancel_delayed_work_sync(&dev_priv->mm.idle_work); |
2503 | queue_delayed_work(dev_priv->wq, | |
2504 | &dev_priv->mm.retire_work, | |
2505 | round_jiffies_up_relative(HZ)); | |
2506 | intel_mark_busy(dev_priv->dev); | |
cc889e0f | 2507 | |
3cce469c | 2508 | return 0; |
673a394b EA |
2509 | } |
2510 | ||
f787a5f5 CW |
2511 | static inline void |
2512 | i915_gem_request_remove_from_client(struct drm_i915_gem_request *request) | |
673a394b | 2513 | { |
1c25595f | 2514 | struct drm_i915_file_private *file_priv = request->file_priv; |
673a394b | 2515 | |
1c25595f CW |
2516 | if (!file_priv) |
2517 | return; | |
1c5d22f7 | 2518 | |
1c25595f | 2519 | spin_lock(&file_priv->mm.lock); |
b29c19b6 CW |
2520 | list_del(&request->client_list); |
2521 | request->file_priv = NULL; | |
1c25595f | 2522 | spin_unlock(&file_priv->mm.lock); |
673a394b | 2523 | } |
673a394b | 2524 | |
939fd762 | 2525 | static bool i915_context_is_banned(struct drm_i915_private *dev_priv, |
273497e5 | 2526 | const struct intel_context *ctx) |
be62acb4 | 2527 | { |
44e2c070 | 2528 | unsigned long elapsed; |
be62acb4 | 2529 | |
44e2c070 MK |
2530 | elapsed = get_seconds() - ctx->hang_stats.guilty_ts; |
2531 | ||
2532 | if (ctx->hang_stats.banned) | |
be62acb4 MK |
2533 | return true; |
2534 | ||
676fa572 CW |
2535 | if (ctx->hang_stats.ban_period_seconds && |
2536 | elapsed <= ctx->hang_stats.ban_period_seconds) { | |
ccc7bed0 | 2537 | if (!i915_gem_context_is_default(ctx)) { |
3fac8978 | 2538 | DRM_DEBUG("context hanging too fast, banning!\n"); |
ccc7bed0 | 2539 | return true; |
88b4aa87 MK |
2540 | } else if (i915_stop_ring_allow_ban(dev_priv)) { |
2541 | if (i915_stop_ring_allow_warn(dev_priv)) | |
2542 | DRM_ERROR("gpu hanging too fast, banning!\n"); | |
ccc7bed0 | 2543 | return true; |
3fac8978 | 2544 | } |
be62acb4 MK |
2545 | } |
2546 | ||
2547 | return false; | |
2548 | } | |
2549 | ||
939fd762 | 2550 | static void i915_set_reset_status(struct drm_i915_private *dev_priv, |
273497e5 | 2551 | struct intel_context *ctx, |
b6b0fac0 | 2552 | const bool guilty) |
aa60c664 | 2553 | { |
44e2c070 MK |
2554 | struct i915_ctx_hang_stats *hs; |
2555 | ||
2556 | if (WARN_ON(!ctx)) | |
2557 | return; | |
aa60c664 | 2558 | |
44e2c070 MK |
2559 | hs = &ctx->hang_stats; |
2560 | ||
2561 | if (guilty) { | |
939fd762 | 2562 | hs->banned = i915_context_is_banned(dev_priv, ctx); |
44e2c070 MK |
2563 | hs->batch_active++; |
2564 | hs->guilty_ts = get_seconds(); | |
2565 | } else { | |
2566 | hs->batch_pending++; | |
aa60c664 MK |
2567 | } |
2568 | } | |
2569 | ||
0e50e96b MK |
2570 | static void i915_gem_free_request(struct drm_i915_gem_request *request) |
2571 | { | |
2572 | list_del(&request->list); | |
2573 | i915_gem_request_remove_from_client(request); | |
2574 | ||
abfe262a JH |
2575 | i915_gem_request_unreference(request); |
2576 | } | |
2577 | ||
2578 | void i915_gem_request_free(struct kref *req_ref) | |
2579 | { | |
2580 | struct drm_i915_gem_request *req = container_of(req_ref, | |
2581 | typeof(*req), ref); | |
2582 | struct intel_context *ctx = req->ctx; | |
2583 | ||
0794aed3 TD |
2584 | if (ctx) { |
2585 | if (i915.enable_execlists) { | |
abfe262a | 2586 | struct intel_engine_cs *ring = req->ring; |
0e50e96b | 2587 | |
0794aed3 TD |
2588 | if (ctx != ring->default_context) |
2589 | intel_lr_context_unpin(ring, ctx); | |
2590 | } | |
abfe262a | 2591 | |
dcb4c12a OM |
2592 | i915_gem_context_unreference(ctx); |
2593 | } | |
abfe262a JH |
2594 | |
2595 | kfree(req); | |
0e50e96b MK |
2596 | } |
2597 | ||
8d9fc7fd | 2598 | struct drm_i915_gem_request * |
a4872ba6 | 2599 | i915_gem_find_active_request(struct intel_engine_cs *ring) |
9375e446 | 2600 | { |
4db080f9 CW |
2601 | struct drm_i915_gem_request *request; |
2602 | ||
2603 | list_for_each_entry(request, &ring->request_list, list) { | |
1b5a433a | 2604 | if (i915_gem_request_completed(request, false)) |
4db080f9 | 2605 | continue; |
aa60c664 | 2606 | |
b6b0fac0 | 2607 | return request; |
4db080f9 | 2608 | } |
b6b0fac0 MK |
2609 | |
2610 | return NULL; | |
2611 | } | |
2612 | ||
2613 | static void i915_gem_reset_ring_status(struct drm_i915_private *dev_priv, | |
a4872ba6 | 2614 | struct intel_engine_cs *ring) |
b6b0fac0 MK |
2615 | { |
2616 | struct drm_i915_gem_request *request; | |
2617 | bool ring_hung; | |
2618 | ||
8d9fc7fd | 2619 | request = i915_gem_find_active_request(ring); |
b6b0fac0 MK |
2620 | |
2621 | if (request == NULL) | |
2622 | return; | |
2623 | ||
2624 | ring_hung = ring->hangcheck.score >= HANGCHECK_SCORE_RING_HUNG; | |
2625 | ||
939fd762 | 2626 | i915_set_reset_status(dev_priv, request->ctx, ring_hung); |
b6b0fac0 MK |
2627 | |
2628 | list_for_each_entry_continue(request, &ring->request_list, list) | |
939fd762 | 2629 | i915_set_reset_status(dev_priv, request->ctx, false); |
4db080f9 | 2630 | } |
aa60c664 | 2631 | |
4db080f9 | 2632 | static void i915_gem_reset_ring_cleanup(struct drm_i915_private *dev_priv, |
a4872ba6 | 2633 | struct intel_engine_cs *ring) |
4db080f9 | 2634 | { |
dfaae392 | 2635 | while (!list_empty(&ring->active_list)) { |
05394f39 | 2636 | struct drm_i915_gem_object *obj; |
9375e446 | 2637 | |
05394f39 CW |
2638 | obj = list_first_entry(&ring->active_list, |
2639 | struct drm_i915_gem_object, | |
2640 | ring_list); | |
9375e446 | 2641 | |
05394f39 | 2642 | i915_gem_object_move_to_inactive(obj); |
673a394b | 2643 | } |
1d62beea | 2644 | |
dcb4c12a OM |
2645 | /* |
2646 | * Clear the execlists queue up before freeing the requests, as those | |
2647 | * are the ones that keep the context and ringbuffer backing objects | |
2648 | * pinned in place. | |
2649 | */ | |
2650 | while (!list_empty(&ring->execlist_queue)) { | |
6d3d8274 | 2651 | struct drm_i915_gem_request *submit_req; |
dcb4c12a OM |
2652 | |
2653 | submit_req = list_first_entry(&ring->execlist_queue, | |
6d3d8274 | 2654 | struct drm_i915_gem_request, |
dcb4c12a OM |
2655 | execlist_link); |
2656 | list_del(&submit_req->execlist_link); | |
2657 | intel_runtime_pm_put(dev_priv); | |
1197b4f2 MK |
2658 | |
2659 | if (submit_req->ctx != ring->default_context) | |
2660 | intel_lr_context_unpin(ring, submit_req->ctx); | |
2661 | ||
b3a38998 | 2662 | i915_gem_request_unreference(submit_req); |
dcb4c12a OM |
2663 | } |
2664 | ||
1d62beea BW |
2665 | /* |
2666 | * We must free the requests after all the corresponding objects have | |
2667 | * been moved off active lists. Which is the same order as the normal | |
2668 | * retire_requests function does. This is important if object hold | |
2669 | * implicit references on things like e.g. ppgtt address spaces through | |
2670 | * the request. | |
2671 | */ | |
2672 | while (!list_empty(&ring->request_list)) { | |
2673 | struct drm_i915_gem_request *request; | |
2674 | ||
2675 | request = list_first_entry(&ring->request_list, | |
2676 | struct drm_i915_gem_request, | |
2677 | list); | |
2678 | ||
2679 | i915_gem_free_request(request); | |
2680 | } | |
e3efda49 | 2681 | |
6259cead JH |
2682 | /* This may not have been flushed before the reset, so clean it now */ |
2683 | i915_gem_request_assign(&ring->outstanding_lazy_request, NULL); | |
673a394b EA |
2684 | } |
2685 | ||
19b2dbde | 2686 | void i915_gem_restore_fences(struct drm_device *dev) |
312817a3 CW |
2687 | { |
2688 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2689 | int i; | |
2690 | ||
4b9de737 | 2691 | for (i = 0; i < dev_priv->num_fence_regs; i++) { |
312817a3 | 2692 | struct drm_i915_fence_reg *reg = &dev_priv->fence_regs[i]; |
7d2cb39c | 2693 | |
94a335db DV |
2694 | /* |
2695 | * Commit delayed tiling changes if we have an object still | |
2696 | * attached to the fence, otherwise just clear the fence. | |
2697 | */ | |
2698 | if (reg->obj) { | |
2699 | i915_gem_object_update_fence(reg->obj, reg, | |
2700 | reg->obj->tiling_mode); | |
2701 | } else { | |
2702 | i915_gem_write_fence(dev, i, NULL); | |
2703 | } | |
312817a3 CW |
2704 | } |
2705 | } | |
2706 | ||
069efc1d | 2707 | void i915_gem_reset(struct drm_device *dev) |
673a394b | 2708 | { |
77f01230 | 2709 | struct drm_i915_private *dev_priv = dev->dev_private; |
a4872ba6 | 2710 | struct intel_engine_cs *ring; |
1ec14ad3 | 2711 | int i; |
673a394b | 2712 | |
4db080f9 CW |
2713 | /* |
2714 | * Before we free the objects from the requests, we need to inspect | |
2715 | * them for finding the guilty party. As the requests only borrow | |
2716 | * their reference to the objects, the inspection must be done first. | |
2717 | */ | |
2718 | for_each_ring(ring, dev_priv, i) | |
2719 | i915_gem_reset_ring_status(dev_priv, ring); | |
2720 | ||
b4519513 | 2721 | for_each_ring(ring, dev_priv, i) |
4db080f9 | 2722 | i915_gem_reset_ring_cleanup(dev_priv, ring); |
dfaae392 | 2723 | |
acce9ffa BW |
2724 | i915_gem_context_reset(dev); |
2725 | ||
19b2dbde | 2726 | i915_gem_restore_fences(dev); |
673a394b EA |
2727 | } |
2728 | ||
2729 | /** | |
2730 | * This function clears the request list as sequence numbers are passed. | |
2731 | */ | |
1cf0ba14 | 2732 | void |
a4872ba6 | 2733 | i915_gem_retire_requests_ring(struct intel_engine_cs *ring) |
673a394b | 2734 | { |
db53a302 | 2735 | if (list_empty(&ring->request_list)) |
6c0594a3 KW |
2736 | return; |
2737 | ||
db53a302 | 2738 | WARN_ON(i915_verify_lists(ring->dev)); |
673a394b | 2739 | |
e9103038 CW |
2740 | /* Move any buffers on the active list that are no longer referenced |
2741 | * by the ringbuffer to the flushing/inactive lists as appropriate, | |
2742 | * before we free the context associated with the requests. | |
2743 | */ | |
2744 | while (!list_empty(&ring->active_list)) { | |
2745 | struct drm_i915_gem_object *obj; | |
2746 | ||
2747 | obj = list_first_entry(&ring->active_list, | |
2748 | struct drm_i915_gem_object, | |
2749 | ring_list); | |
2750 | ||
1b5a433a | 2751 | if (!i915_gem_request_completed(obj->last_read_req, true)) |
e9103038 CW |
2752 | break; |
2753 | ||
2754 | i915_gem_object_move_to_inactive(obj); | |
2755 | } | |
2756 | ||
2757 | ||
852835f3 | 2758 | while (!list_empty(&ring->request_list)) { |
673a394b | 2759 | struct drm_i915_gem_request *request; |
48e29f55 | 2760 | struct intel_ringbuffer *ringbuf; |
673a394b | 2761 | |
852835f3 | 2762 | request = list_first_entry(&ring->request_list, |
673a394b EA |
2763 | struct drm_i915_gem_request, |
2764 | list); | |
673a394b | 2765 | |
1b5a433a | 2766 | if (!i915_gem_request_completed(request, true)) |
b84d5f0c CW |
2767 | break; |
2768 | ||
74328ee5 | 2769 | trace_i915_gem_request_retire(request); |
48e29f55 OM |
2770 | |
2771 | /* This is one of the few common intersection points | |
2772 | * between legacy ringbuffer submission and execlists: | |
2773 | * we need to tell them apart in order to find the correct | |
2774 | * ringbuffer to which the request belongs to. | |
2775 | */ | |
2776 | if (i915.enable_execlists) { | |
2777 | struct intel_context *ctx = request->ctx; | |
2778 | ringbuf = ctx->engine[ring->id].ringbuf; | |
2779 | } else | |
2780 | ringbuf = ring->buffer; | |
2781 | ||
a71d8d94 CW |
2782 | /* We know the GPU must have read the request to have |
2783 | * sent us the seqno + interrupt, so use the position | |
2784 | * of tail of the request to update the last known position | |
2785 | * of the GPU head. | |
2786 | */ | |
72f95afa | 2787 | ringbuf->last_retired_head = request->postfix; |
b84d5f0c | 2788 | |
0e50e96b | 2789 | i915_gem_free_request(request); |
b84d5f0c | 2790 | } |
673a394b | 2791 | |
581c26e8 JH |
2792 | if (unlikely(ring->trace_irq_req && |
2793 | i915_gem_request_completed(ring->trace_irq_req, true))) { | |
1ec14ad3 | 2794 | ring->irq_put(ring); |
581c26e8 | 2795 | i915_gem_request_assign(&ring->trace_irq_req, NULL); |
9d34e5db | 2796 | } |
23bc5982 | 2797 | |
db53a302 | 2798 | WARN_ON(i915_verify_lists(ring->dev)); |
673a394b EA |
2799 | } |
2800 | ||
b29c19b6 | 2801 | bool |
b09a1fec CW |
2802 | i915_gem_retire_requests(struct drm_device *dev) |
2803 | { | |
3e31c6c0 | 2804 | struct drm_i915_private *dev_priv = dev->dev_private; |
a4872ba6 | 2805 | struct intel_engine_cs *ring; |
b29c19b6 | 2806 | bool idle = true; |
1ec14ad3 | 2807 | int i; |
b09a1fec | 2808 | |
b29c19b6 | 2809 | for_each_ring(ring, dev_priv, i) { |
b4519513 | 2810 | i915_gem_retire_requests_ring(ring); |
b29c19b6 | 2811 | idle &= list_empty(&ring->request_list); |
c86ee3a9 TD |
2812 | if (i915.enable_execlists) { |
2813 | unsigned long flags; | |
2814 | ||
2815 | spin_lock_irqsave(&ring->execlist_lock, flags); | |
2816 | idle &= list_empty(&ring->execlist_queue); | |
2817 | spin_unlock_irqrestore(&ring->execlist_lock, flags); | |
2818 | ||
2819 | intel_execlists_retire_requests(ring); | |
2820 | } | |
b29c19b6 CW |
2821 | } |
2822 | ||
2823 | if (idle) | |
2824 | mod_delayed_work(dev_priv->wq, | |
2825 | &dev_priv->mm.idle_work, | |
2826 | msecs_to_jiffies(100)); | |
2827 | ||
2828 | return idle; | |
b09a1fec CW |
2829 | } |
2830 | ||
75ef9da2 | 2831 | static void |
673a394b EA |
2832 | i915_gem_retire_work_handler(struct work_struct *work) |
2833 | { | |
b29c19b6 CW |
2834 | struct drm_i915_private *dev_priv = |
2835 | container_of(work, typeof(*dev_priv), mm.retire_work.work); | |
2836 | struct drm_device *dev = dev_priv->dev; | |
0a58705b | 2837 | bool idle; |
673a394b | 2838 | |
891b48cf | 2839 | /* Come back later if the device is busy... */ |
b29c19b6 CW |
2840 | idle = false; |
2841 | if (mutex_trylock(&dev->struct_mutex)) { | |
2842 | idle = i915_gem_retire_requests(dev); | |
2843 | mutex_unlock(&dev->struct_mutex); | |
673a394b | 2844 | } |
b29c19b6 | 2845 | if (!idle) |
bcb45086 CW |
2846 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, |
2847 | round_jiffies_up_relative(HZ)); | |
b29c19b6 | 2848 | } |
0a58705b | 2849 | |
b29c19b6 CW |
2850 | static void |
2851 | i915_gem_idle_work_handler(struct work_struct *work) | |
2852 | { | |
2853 | struct drm_i915_private *dev_priv = | |
2854 | container_of(work, typeof(*dev_priv), mm.idle_work.work); | |
2855 | ||
2856 | intel_mark_idle(dev_priv->dev); | |
673a394b EA |
2857 | } |
2858 | ||
30dfebf3 DV |
2859 | /** |
2860 | * Ensures that an object will eventually get non-busy by flushing any required | |
2861 | * write domains, emitting any outstanding lazy request and retiring and | |
2862 | * completed requests. | |
2863 | */ | |
2864 | static int | |
2865 | i915_gem_object_flush_active(struct drm_i915_gem_object *obj) | |
2866 | { | |
41c52415 | 2867 | struct intel_engine_cs *ring; |
30dfebf3 DV |
2868 | int ret; |
2869 | ||
2870 | if (obj->active) { | |
41c52415 JH |
2871 | ring = i915_gem_request_get_ring(obj->last_read_req); |
2872 | ||
b6660d59 | 2873 | ret = i915_gem_check_olr(obj->last_read_req); |
30dfebf3 DV |
2874 | if (ret) |
2875 | return ret; | |
2876 | ||
41c52415 | 2877 | i915_gem_retire_requests_ring(ring); |
30dfebf3 DV |
2878 | } |
2879 | ||
2880 | return 0; | |
2881 | } | |
2882 | ||
23ba4fd0 BW |
2883 | /** |
2884 | * i915_gem_wait_ioctl - implements DRM_IOCTL_I915_GEM_WAIT | |
2885 | * @DRM_IOCTL_ARGS: standard ioctl arguments | |
2886 | * | |
2887 | * Returns 0 if successful, else an error is returned with the remaining time in | |
2888 | * the timeout parameter. | |
2889 | * -ETIME: object is still busy after timeout | |
2890 | * -ERESTARTSYS: signal interrupted the wait | |
2891 | * -ENONENT: object doesn't exist | |
2892 | * Also possible, but rare: | |
2893 | * -EAGAIN: GPU wedged | |
2894 | * -ENOMEM: damn | |
2895 | * -ENODEV: Internal IRQ fail | |
2896 | * -E?: The add request failed | |
2897 | * | |
2898 | * The wait ioctl with a timeout of 0 reimplements the busy ioctl. With any | |
2899 | * non-zero timeout parameter the wait ioctl will wait for the given number of | |
2900 | * nanoseconds on an object becoming unbusy. Since the wait itself does so | |
2901 | * without holding struct_mutex the object may become re-busied before this | |
2902 | * function completes. A similar but shorter * race condition exists in the busy | |
2903 | * ioctl | |
2904 | */ | |
2905 | int | |
2906 | i915_gem_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *file) | |
2907 | { | |
3e31c6c0 | 2908 | struct drm_i915_private *dev_priv = dev->dev_private; |
23ba4fd0 BW |
2909 | struct drm_i915_gem_wait *args = data; |
2910 | struct drm_i915_gem_object *obj; | |
ff865885 | 2911 | struct drm_i915_gem_request *req; |
f69061be | 2912 | unsigned reset_counter; |
23ba4fd0 BW |
2913 | int ret = 0; |
2914 | ||
11b5d511 DV |
2915 | if (args->flags != 0) |
2916 | return -EINVAL; | |
2917 | ||
23ba4fd0 BW |
2918 | ret = i915_mutex_lock_interruptible(dev); |
2919 | if (ret) | |
2920 | return ret; | |
2921 | ||
2922 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->bo_handle)); | |
2923 | if (&obj->base == NULL) { | |
2924 | mutex_unlock(&dev->struct_mutex); | |
2925 | return -ENOENT; | |
2926 | } | |
2927 | ||
30dfebf3 DV |
2928 | /* Need to make sure the object gets inactive eventually. */ |
2929 | ret = i915_gem_object_flush_active(obj); | |
23ba4fd0 BW |
2930 | if (ret) |
2931 | goto out; | |
2932 | ||
97b2a6a1 JH |
2933 | if (!obj->active || !obj->last_read_req) |
2934 | goto out; | |
23ba4fd0 | 2935 | |
ff865885 | 2936 | req = obj->last_read_req; |
23ba4fd0 | 2937 | |
23ba4fd0 | 2938 | /* Do this after OLR check to make sure we make forward progress polling |
5ed0bdf2 | 2939 | * on this IOCTL with a timeout <=0 (like busy ioctl) |
23ba4fd0 | 2940 | */ |
5ed0bdf2 | 2941 | if (args->timeout_ns <= 0) { |
23ba4fd0 BW |
2942 | ret = -ETIME; |
2943 | goto out; | |
2944 | } | |
2945 | ||
2946 | drm_gem_object_unreference(&obj->base); | |
f69061be | 2947 | reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter); |
ff865885 | 2948 | i915_gem_request_reference(req); |
23ba4fd0 BW |
2949 | mutex_unlock(&dev->struct_mutex); |
2950 | ||
9c654818 JH |
2951 | ret = __i915_wait_request(req, reset_counter, true, &args->timeout_ns, |
2952 | file->driver_priv); | |
ff865885 JH |
2953 | mutex_lock(&dev->struct_mutex); |
2954 | i915_gem_request_unreference(req); | |
2955 | mutex_unlock(&dev->struct_mutex); | |
2956 | return ret; | |
23ba4fd0 BW |
2957 | |
2958 | out: | |
2959 | drm_gem_object_unreference(&obj->base); | |
2960 | mutex_unlock(&dev->struct_mutex); | |
2961 | return ret; | |
2962 | } | |
2963 | ||
5816d648 BW |
2964 | /** |
2965 | * i915_gem_object_sync - sync an object to a ring. | |
2966 | * | |
2967 | * @obj: object which may be in use on another ring. | |
2968 | * @to: ring we wish to use the object on. May be NULL. | |
2969 | * | |
2970 | * This code is meant to abstract object synchronization with the GPU. | |
2971 | * Calling with NULL implies synchronizing the object with the CPU | |
2972 | * rather than a particular GPU ring. | |
2973 | * | |
2974 | * Returns 0 if successful, else propagates up the lower layer error. | |
2975 | */ | |
2911a35b BW |
2976 | int |
2977 | i915_gem_object_sync(struct drm_i915_gem_object *obj, | |
a4872ba6 | 2978 | struct intel_engine_cs *to) |
2911a35b | 2979 | { |
41c52415 | 2980 | struct intel_engine_cs *from; |
2911a35b BW |
2981 | u32 seqno; |
2982 | int ret, idx; | |
2983 | ||
41c52415 JH |
2984 | from = i915_gem_request_get_ring(obj->last_read_req); |
2985 | ||
2911a35b BW |
2986 | if (from == NULL || to == from) |
2987 | return 0; | |
2988 | ||
5816d648 | 2989 | if (to == NULL || !i915_semaphore_is_enabled(obj->base.dev)) |
0201f1ec | 2990 | return i915_gem_object_wait_rendering(obj, false); |
2911a35b BW |
2991 | |
2992 | idx = intel_ring_sync_index(from, to); | |
2993 | ||
97b2a6a1 | 2994 | seqno = i915_gem_request_get_seqno(obj->last_read_req); |
ddd4dbc6 RV |
2995 | /* Optimization: Avoid semaphore sync when we are sure we already |
2996 | * waited for an object with higher seqno */ | |
ebc348b2 | 2997 | if (seqno <= from->semaphore.sync_seqno[idx]) |
2911a35b BW |
2998 | return 0; |
2999 | ||
b6660d59 | 3000 | ret = i915_gem_check_olr(obj->last_read_req); |
b4aca010 BW |
3001 | if (ret) |
3002 | return ret; | |
2911a35b | 3003 | |
74328ee5 | 3004 | trace_i915_gem_ring_sync_to(from, to, obj->last_read_req); |
ebc348b2 | 3005 | ret = to->semaphore.sync_to(to, from, seqno); |
e3a5a225 | 3006 | if (!ret) |
97b2a6a1 | 3007 | /* We use last_read_req because sync_to() |
7b01e260 MK |
3008 | * might have just caused seqno wrap under |
3009 | * the radar. | |
3010 | */ | |
97b2a6a1 JH |
3011 | from->semaphore.sync_seqno[idx] = |
3012 | i915_gem_request_get_seqno(obj->last_read_req); | |
2911a35b | 3013 | |
e3a5a225 | 3014 | return ret; |
2911a35b BW |
3015 | } |
3016 | ||
b5ffc9bc CW |
3017 | static void i915_gem_object_finish_gtt(struct drm_i915_gem_object *obj) |
3018 | { | |
3019 | u32 old_write_domain, old_read_domains; | |
3020 | ||
b5ffc9bc CW |
3021 | /* Force a pagefault for domain tracking on next user access */ |
3022 | i915_gem_release_mmap(obj); | |
3023 | ||
b97c3d9c KP |
3024 | if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0) |
3025 | return; | |
3026 | ||
97c809fd CW |
3027 | /* Wait for any direct GTT access to complete */ |
3028 | mb(); | |
3029 | ||
b5ffc9bc CW |
3030 | old_read_domains = obj->base.read_domains; |
3031 | old_write_domain = obj->base.write_domain; | |
3032 | ||
3033 | obj->base.read_domains &= ~I915_GEM_DOMAIN_GTT; | |
3034 | obj->base.write_domain &= ~I915_GEM_DOMAIN_GTT; | |
3035 | ||
3036 | trace_i915_gem_object_change_domain(obj, | |
3037 | old_read_domains, | |
3038 | old_write_domain); | |
3039 | } | |
3040 | ||
07fe0b12 | 3041 | int i915_vma_unbind(struct i915_vma *vma) |
673a394b | 3042 | { |
07fe0b12 | 3043 | struct drm_i915_gem_object *obj = vma->obj; |
3e31c6c0 | 3044 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
43e28f09 | 3045 | int ret; |
673a394b | 3046 | |
07fe0b12 | 3047 | if (list_empty(&vma->vma_link)) |
673a394b EA |
3048 | return 0; |
3049 | ||
0ff501cb DV |
3050 | if (!drm_mm_node_allocated(&vma->node)) { |
3051 | i915_gem_vma_destroy(vma); | |
0ff501cb DV |
3052 | return 0; |
3053 | } | |
433544bd | 3054 | |
d7f46fc4 | 3055 | if (vma->pin_count) |
31d8d651 | 3056 | return -EBUSY; |
673a394b | 3057 | |
c4670ad0 CW |
3058 | BUG_ON(obj->pages == NULL); |
3059 | ||
a8198eea | 3060 | ret = i915_gem_object_finish_gpu(obj); |
1488fc08 | 3061 | if (ret) |
a8198eea CW |
3062 | return ret; |
3063 | /* Continue on if we fail due to EIO, the GPU is hung so we | |
3064 | * should be safe and we need to cleanup or else we might | |
3065 | * cause memory corruption through use-after-free. | |
3066 | */ | |
3067 | ||
fe14d5f4 TU |
3068 | if (i915_is_ggtt(vma->vm) && |
3069 | vma->ggtt_view.type == I915_GGTT_VIEW_NORMAL) { | |
8b1bc9b4 | 3070 | i915_gem_object_finish_gtt(obj); |
5323fd04 | 3071 | |
8b1bc9b4 DV |
3072 | /* release the fence reg _after_ flushing */ |
3073 | ret = i915_gem_object_put_fence(obj); | |
3074 | if (ret) | |
3075 | return ret; | |
3076 | } | |
96b47b65 | 3077 | |
07fe0b12 | 3078 | trace_i915_vma_unbind(vma); |
db53a302 | 3079 | |
6f65e29a BW |
3080 | vma->unbind_vma(vma); |
3081 | ||
64bf9303 | 3082 | list_del_init(&vma->mm_list); |
fe14d5f4 TU |
3083 | if (i915_is_ggtt(vma->vm)) { |
3084 | if (vma->ggtt_view.type == I915_GGTT_VIEW_NORMAL) { | |
3085 | obj->map_and_fenceable = false; | |
3086 | } else if (vma->ggtt_view.pages) { | |
3087 | sg_free_table(vma->ggtt_view.pages); | |
3088 | kfree(vma->ggtt_view.pages); | |
3089 | vma->ggtt_view.pages = NULL; | |
3090 | } | |
3091 | } | |
673a394b | 3092 | |
2f633156 BW |
3093 | drm_mm_remove_node(&vma->node); |
3094 | i915_gem_vma_destroy(vma); | |
3095 | ||
3096 | /* Since the unbound list is global, only move to that list if | |
b93dab6e | 3097 | * no more VMAs exist. */ |
9490edb5 | 3098 | if (list_empty(&obj->vma_list)) { |
fe14d5f4 TU |
3099 | /* Throw away the active reference before |
3100 | * moving to the unbound list. */ | |
3101 | i915_gem_object_retire(obj); | |
3102 | ||
9490edb5 | 3103 | i915_gem_gtt_finish_object(obj); |
2f633156 | 3104 | list_move_tail(&obj->global_list, &dev_priv->mm.unbound_list); |
9490edb5 | 3105 | } |
673a394b | 3106 | |
70903c3b CW |
3107 | /* And finally now the object is completely decoupled from this vma, |
3108 | * we can drop its hold on the backing storage and allow it to be | |
3109 | * reaped by the shrinker. | |
3110 | */ | |
3111 | i915_gem_object_unpin_pages(obj); | |
3112 | ||
88241785 | 3113 | return 0; |
54cf91dc CW |
3114 | } |
3115 | ||
b2da9fe5 | 3116 | int i915_gpu_idle(struct drm_device *dev) |
4df2faf4 | 3117 | { |
3e31c6c0 | 3118 | struct drm_i915_private *dev_priv = dev->dev_private; |
a4872ba6 | 3119 | struct intel_engine_cs *ring; |
1ec14ad3 | 3120 | int ret, i; |
4df2faf4 | 3121 | |
4df2faf4 | 3122 | /* Flush everything onto the inactive list. */ |
b4519513 | 3123 | for_each_ring(ring, dev_priv, i) { |
ecdb5fd8 TD |
3124 | if (!i915.enable_execlists) { |
3125 | ret = i915_switch_context(ring, ring->default_context); | |
3126 | if (ret) | |
3127 | return ret; | |
3128 | } | |
b6c7488d | 3129 | |
3e960501 | 3130 | ret = intel_ring_idle(ring); |
1ec14ad3 CW |
3131 | if (ret) |
3132 | return ret; | |
3133 | } | |
4df2faf4 | 3134 | |
8a1a49f9 | 3135 | return 0; |
4df2faf4 DV |
3136 | } |
3137 | ||
9ce079e4 CW |
3138 | static void i965_write_fence_reg(struct drm_device *dev, int reg, |
3139 | struct drm_i915_gem_object *obj) | |
de151cf6 | 3140 | { |
3e31c6c0 | 3141 | struct drm_i915_private *dev_priv = dev->dev_private; |
56c844e5 ID |
3142 | int fence_reg; |
3143 | int fence_pitch_shift; | |
de151cf6 | 3144 | |
56c844e5 ID |
3145 | if (INTEL_INFO(dev)->gen >= 6) { |
3146 | fence_reg = FENCE_REG_SANDYBRIDGE_0; | |
3147 | fence_pitch_shift = SANDYBRIDGE_FENCE_PITCH_SHIFT; | |
3148 | } else { | |
3149 | fence_reg = FENCE_REG_965_0; | |
3150 | fence_pitch_shift = I965_FENCE_PITCH_SHIFT; | |
3151 | } | |
3152 | ||
d18b9619 CW |
3153 | fence_reg += reg * 8; |
3154 | ||
3155 | /* To w/a incoherency with non-atomic 64-bit register updates, | |
3156 | * we split the 64-bit update into two 32-bit writes. In order | |
3157 | * for a partial fence not to be evaluated between writes, we | |
3158 | * precede the update with write to turn off the fence register, | |
3159 | * and only enable the fence as the last step. | |
3160 | * | |
3161 | * For extra levels of paranoia, we make sure each step lands | |
3162 | * before applying the next step. | |
3163 | */ | |
3164 | I915_WRITE(fence_reg, 0); | |
3165 | POSTING_READ(fence_reg); | |
3166 | ||
9ce079e4 | 3167 | if (obj) { |
f343c5f6 | 3168 | u32 size = i915_gem_obj_ggtt_size(obj); |
d18b9619 | 3169 | uint64_t val; |
de151cf6 | 3170 | |
af1a7301 BP |
3171 | /* Adjust fence size to match tiled area */ |
3172 | if (obj->tiling_mode != I915_TILING_NONE) { | |
3173 | uint32_t row_size = obj->stride * | |
3174 | (obj->tiling_mode == I915_TILING_Y ? 32 : 8); | |
3175 | size = (size / row_size) * row_size; | |
3176 | } | |
3177 | ||
f343c5f6 | 3178 | val = (uint64_t)((i915_gem_obj_ggtt_offset(obj) + size - 4096) & |
9ce079e4 | 3179 | 0xfffff000) << 32; |
f343c5f6 | 3180 | val |= i915_gem_obj_ggtt_offset(obj) & 0xfffff000; |
56c844e5 | 3181 | val |= (uint64_t)((obj->stride / 128) - 1) << fence_pitch_shift; |
9ce079e4 CW |
3182 | if (obj->tiling_mode == I915_TILING_Y) |
3183 | val |= 1 << I965_FENCE_TILING_Y_SHIFT; | |
3184 | val |= I965_FENCE_REG_VALID; | |
c6642782 | 3185 | |
d18b9619 CW |
3186 | I915_WRITE(fence_reg + 4, val >> 32); |
3187 | POSTING_READ(fence_reg + 4); | |
3188 | ||
3189 | I915_WRITE(fence_reg + 0, val); | |
3190 | POSTING_READ(fence_reg); | |
3191 | } else { | |
3192 | I915_WRITE(fence_reg + 4, 0); | |
3193 | POSTING_READ(fence_reg + 4); | |
3194 | } | |
de151cf6 JB |
3195 | } |
3196 | ||
9ce079e4 CW |
3197 | static void i915_write_fence_reg(struct drm_device *dev, int reg, |
3198 | struct drm_i915_gem_object *obj) | |
de151cf6 | 3199 | { |
3e31c6c0 | 3200 | struct drm_i915_private *dev_priv = dev->dev_private; |
9ce079e4 | 3201 | u32 val; |
de151cf6 | 3202 | |
9ce079e4 | 3203 | if (obj) { |
f343c5f6 | 3204 | u32 size = i915_gem_obj_ggtt_size(obj); |
9ce079e4 CW |
3205 | int pitch_val; |
3206 | int tile_width; | |
c6642782 | 3207 | |
f343c5f6 | 3208 | WARN((i915_gem_obj_ggtt_offset(obj) & ~I915_FENCE_START_MASK) || |
9ce079e4 | 3209 | (size & -size) != size || |
f343c5f6 BW |
3210 | (i915_gem_obj_ggtt_offset(obj) & (size - 1)), |
3211 | "object 0x%08lx [fenceable? %d] not 1M or pot-size (0x%08x) aligned\n", | |
3212 | i915_gem_obj_ggtt_offset(obj), obj->map_and_fenceable, size); | |
c6642782 | 3213 | |
9ce079e4 CW |
3214 | if (obj->tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev)) |
3215 | tile_width = 128; | |
3216 | else | |
3217 | tile_width = 512; | |
3218 | ||
3219 | /* Note: pitch better be a power of two tile widths */ | |
3220 | pitch_val = obj->stride / tile_width; | |
3221 | pitch_val = ffs(pitch_val) - 1; | |
3222 | ||
f343c5f6 | 3223 | val = i915_gem_obj_ggtt_offset(obj); |
9ce079e4 CW |
3224 | if (obj->tiling_mode == I915_TILING_Y) |
3225 | val |= 1 << I830_FENCE_TILING_Y_SHIFT; | |
3226 | val |= I915_FENCE_SIZE_BITS(size); | |
3227 | val |= pitch_val << I830_FENCE_PITCH_SHIFT; | |
3228 | val |= I830_FENCE_REG_VALID; | |
3229 | } else | |
3230 | val = 0; | |
3231 | ||
3232 | if (reg < 8) | |
3233 | reg = FENCE_REG_830_0 + reg * 4; | |
3234 | else | |
3235 | reg = FENCE_REG_945_8 + (reg - 8) * 4; | |
3236 | ||
3237 | I915_WRITE(reg, val); | |
3238 | POSTING_READ(reg); | |
de151cf6 JB |
3239 | } |
3240 | ||
9ce079e4 CW |
3241 | static void i830_write_fence_reg(struct drm_device *dev, int reg, |
3242 | struct drm_i915_gem_object *obj) | |
de151cf6 | 3243 | { |
3e31c6c0 | 3244 | struct drm_i915_private *dev_priv = dev->dev_private; |
de151cf6 | 3245 | uint32_t val; |
de151cf6 | 3246 | |
9ce079e4 | 3247 | if (obj) { |
f343c5f6 | 3248 | u32 size = i915_gem_obj_ggtt_size(obj); |
9ce079e4 | 3249 | uint32_t pitch_val; |
de151cf6 | 3250 | |
f343c5f6 | 3251 | WARN((i915_gem_obj_ggtt_offset(obj) & ~I830_FENCE_START_MASK) || |
9ce079e4 | 3252 | (size & -size) != size || |
f343c5f6 BW |
3253 | (i915_gem_obj_ggtt_offset(obj) & (size - 1)), |
3254 | "object 0x%08lx not 512K or pot-size 0x%08x aligned\n", | |
3255 | i915_gem_obj_ggtt_offset(obj), size); | |
e76a16de | 3256 | |
9ce079e4 CW |
3257 | pitch_val = obj->stride / 128; |
3258 | pitch_val = ffs(pitch_val) - 1; | |
de151cf6 | 3259 | |
f343c5f6 | 3260 | val = i915_gem_obj_ggtt_offset(obj); |
9ce079e4 CW |
3261 | if (obj->tiling_mode == I915_TILING_Y) |
3262 | val |= 1 << I830_FENCE_TILING_Y_SHIFT; | |
3263 | val |= I830_FENCE_SIZE_BITS(size); | |
3264 | val |= pitch_val << I830_FENCE_PITCH_SHIFT; | |
3265 | val |= I830_FENCE_REG_VALID; | |
3266 | } else | |
3267 | val = 0; | |
c6642782 | 3268 | |
9ce079e4 CW |
3269 | I915_WRITE(FENCE_REG_830_0 + reg * 4, val); |
3270 | POSTING_READ(FENCE_REG_830_0 + reg * 4); | |
3271 | } | |
3272 | ||
d0a57789 CW |
3273 | inline static bool i915_gem_object_needs_mb(struct drm_i915_gem_object *obj) |
3274 | { | |
3275 | return obj && obj->base.read_domains & I915_GEM_DOMAIN_GTT; | |
3276 | } | |
3277 | ||
9ce079e4 CW |
3278 | static void i915_gem_write_fence(struct drm_device *dev, int reg, |
3279 | struct drm_i915_gem_object *obj) | |
3280 | { | |
d0a57789 CW |
3281 | struct drm_i915_private *dev_priv = dev->dev_private; |
3282 | ||
3283 | /* Ensure that all CPU reads are completed before installing a fence | |
3284 | * and all writes before removing the fence. | |
3285 | */ | |
3286 | if (i915_gem_object_needs_mb(dev_priv->fence_regs[reg].obj)) | |
3287 | mb(); | |
3288 | ||
94a335db DV |
3289 | WARN(obj && (!obj->stride || !obj->tiling_mode), |
3290 | "bogus fence setup with stride: 0x%x, tiling mode: %i\n", | |
3291 | obj->stride, obj->tiling_mode); | |
3292 | ||
ce38ab05 RV |
3293 | if (IS_GEN2(dev)) |
3294 | i830_write_fence_reg(dev, reg, obj); | |
3295 | else if (IS_GEN3(dev)) | |
3296 | i915_write_fence_reg(dev, reg, obj); | |
3297 | else if (INTEL_INFO(dev)->gen >= 4) | |
3298 | i965_write_fence_reg(dev, reg, obj); | |
d0a57789 CW |
3299 | |
3300 | /* And similarly be paranoid that no direct access to this region | |
3301 | * is reordered to before the fence is installed. | |
3302 | */ | |
3303 | if (i915_gem_object_needs_mb(obj)) | |
3304 | mb(); | |
de151cf6 JB |
3305 | } |
3306 | ||
61050808 CW |
3307 | static inline int fence_number(struct drm_i915_private *dev_priv, |
3308 | struct drm_i915_fence_reg *fence) | |
3309 | { | |
3310 | return fence - dev_priv->fence_regs; | |
3311 | } | |
3312 | ||
3313 | static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj, | |
3314 | struct drm_i915_fence_reg *fence, | |
3315 | bool enable) | |
3316 | { | |
2dc8aae0 | 3317 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
46a0b638 CW |
3318 | int reg = fence_number(dev_priv, fence); |
3319 | ||
3320 | i915_gem_write_fence(obj->base.dev, reg, enable ? obj : NULL); | |
61050808 CW |
3321 | |
3322 | if (enable) { | |
46a0b638 | 3323 | obj->fence_reg = reg; |
61050808 CW |
3324 | fence->obj = obj; |
3325 | list_move_tail(&fence->lru_list, &dev_priv->mm.fence_list); | |
3326 | } else { | |
3327 | obj->fence_reg = I915_FENCE_REG_NONE; | |
3328 | fence->obj = NULL; | |
3329 | list_del_init(&fence->lru_list); | |
3330 | } | |
94a335db | 3331 | obj->fence_dirty = false; |
61050808 CW |
3332 | } |
3333 | ||
d9e86c0e | 3334 | static int |
d0a57789 | 3335 | i915_gem_object_wait_fence(struct drm_i915_gem_object *obj) |
d9e86c0e | 3336 | { |
97b2a6a1 | 3337 | if (obj->last_fenced_req) { |
a4b3a571 | 3338 | int ret = i915_wait_request(obj->last_fenced_req); |
18991845 CW |
3339 | if (ret) |
3340 | return ret; | |
d9e86c0e | 3341 | |
97b2a6a1 | 3342 | i915_gem_request_assign(&obj->last_fenced_req, NULL); |
d9e86c0e CW |
3343 | } |
3344 | ||
3345 | return 0; | |
3346 | } | |
3347 | ||
3348 | int | |
3349 | i915_gem_object_put_fence(struct drm_i915_gem_object *obj) | |
3350 | { | |
61050808 | 3351 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
f9c513e9 | 3352 | struct drm_i915_fence_reg *fence; |
d9e86c0e CW |
3353 | int ret; |
3354 | ||
d0a57789 | 3355 | ret = i915_gem_object_wait_fence(obj); |
d9e86c0e CW |
3356 | if (ret) |
3357 | return ret; | |
3358 | ||
61050808 CW |
3359 | if (obj->fence_reg == I915_FENCE_REG_NONE) |
3360 | return 0; | |
d9e86c0e | 3361 | |
f9c513e9 CW |
3362 | fence = &dev_priv->fence_regs[obj->fence_reg]; |
3363 | ||
aff10b30 DV |
3364 | if (WARN_ON(fence->pin_count)) |
3365 | return -EBUSY; | |
3366 | ||
61050808 | 3367 | i915_gem_object_fence_lost(obj); |
f9c513e9 | 3368 | i915_gem_object_update_fence(obj, fence, false); |
d9e86c0e CW |
3369 | |
3370 | return 0; | |
3371 | } | |
3372 | ||
3373 | static struct drm_i915_fence_reg * | |
a360bb1a | 3374 | i915_find_fence_reg(struct drm_device *dev) |
ae3db24a | 3375 | { |
ae3db24a | 3376 | struct drm_i915_private *dev_priv = dev->dev_private; |
8fe301ad | 3377 | struct drm_i915_fence_reg *reg, *avail; |
d9e86c0e | 3378 | int i; |
ae3db24a DV |
3379 | |
3380 | /* First try to find a free reg */ | |
d9e86c0e | 3381 | avail = NULL; |
ae3db24a DV |
3382 | for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) { |
3383 | reg = &dev_priv->fence_regs[i]; | |
3384 | if (!reg->obj) | |
d9e86c0e | 3385 | return reg; |
ae3db24a | 3386 | |
1690e1eb | 3387 | if (!reg->pin_count) |
d9e86c0e | 3388 | avail = reg; |
ae3db24a DV |
3389 | } |
3390 | ||
d9e86c0e | 3391 | if (avail == NULL) |
5dce5b93 | 3392 | goto deadlock; |
ae3db24a DV |
3393 | |
3394 | /* None available, try to steal one or wait for a user to finish */ | |
d9e86c0e | 3395 | list_for_each_entry(reg, &dev_priv->mm.fence_list, lru_list) { |
1690e1eb | 3396 | if (reg->pin_count) |
ae3db24a DV |
3397 | continue; |
3398 | ||
8fe301ad | 3399 | return reg; |
ae3db24a DV |
3400 | } |
3401 | ||
5dce5b93 CW |
3402 | deadlock: |
3403 | /* Wait for completion of pending flips which consume fences */ | |
3404 | if (intel_has_pending_fb_unpin(dev)) | |
3405 | return ERR_PTR(-EAGAIN); | |
3406 | ||
3407 | return ERR_PTR(-EDEADLK); | |
ae3db24a DV |
3408 | } |
3409 | ||
de151cf6 | 3410 | /** |
9a5a53b3 | 3411 | * i915_gem_object_get_fence - set up fencing for an object |
de151cf6 JB |
3412 | * @obj: object to map through a fence reg |
3413 | * | |
3414 | * When mapping objects through the GTT, userspace wants to be able to write | |
3415 | * to them without having to worry about swizzling if the object is tiled. | |
de151cf6 JB |
3416 | * This function walks the fence regs looking for a free one for @obj, |
3417 | * stealing one if it can't find any. | |
3418 | * | |
3419 | * It then sets up the reg based on the object's properties: address, pitch | |
3420 | * and tiling format. | |
9a5a53b3 CW |
3421 | * |
3422 | * For an untiled surface, this removes any existing fence. | |
de151cf6 | 3423 | */ |
8c4b8c3f | 3424 | int |
06d98131 | 3425 | i915_gem_object_get_fence(struct drm_i915_gem_object *obj) |
de151cf6 | 3426 | { |
05394f39 | 3427 | struct drm_device *dev = obj->base.dev; |
79e53945 | 3428 | struct drm_i915_private *dev_priv = dev->dev_private; |
14415745 | 3429 | bool enable = obj->tiling_mode != I915_TILING_NONE; |
d9e86c0e | 3430 | struct drm_i915_fence_reg *reg; |
ae3db24a | 3431 | int ret; |
de151cf6 | 3432 | |
14415745 CW |
3433 | /* Have we updated the tiling parameters upon the object and so |
3434 | * will need to serialise the write to the associated fence register? | |
3435 | */ | |
5d82e3e6 | 3436 | if (obj->fence_dirty) { |
d0a57789 | 3437 | ret = i915_gem_object_wait_fence(obj); |
14415745 CW |
3438 | if (ret) |
3439 | return ret; | |
3440 | } | |
9a5a53b3 | 3441 | |
d9e86c0e | 3442 | /* Just update our place in the LRU if our fence is getting reused. */ |
05394f39 CW |
3443 | if (obj->fence_reg != I915_FENCE_REG_NONE) { |
3444 | reg = &dev_priv->fence_regs[obj->fence_reg]; | |
5d82e3e6 | 3445 | if (!obj->fence_dirty) { |
14415745 CW |
3446 | list_move_tail(®->lru_list, |
3447 | &dev_priv->mm.fence_list); | |
3448 | return 0; | |
3449 | } | |
3450 | } else if (enable) { | |
e6a84468 CW |
3451 | if (WARN_ON(!obj->map_and_fenceable)) |
3452 | return -EINVAL; | |
3453 | ||
14415745 | 3454 | reg = i915_find_fence_reg(dev); |
5dce5b93 CW |
3455 | if (IS_ERR(reg)) |
3456 | return PTR_ERR(reg); | |
d9e86c0e | 3457 | |
14415745 CW |
3458 | if (reg->obj) { |
3459 | struct drm_i915_gem_object *old = reg->obj; | |
3460 | ||
d0a57789 | 3461 | ret = i915_gem_object_wait_fence(old); |
29c5a587 CW |
3462 | if (ret) |
3463 | return ret; | |
3464 | ||
14415745 | 3465 | i915_gem_object_fence_lost(old); |
29c5a587 | 3466 | } |
14415745 | 3467 | } else |
a09ba7fa | 3468 | return 0; |
a09ba7fa | 3469 | |
14415745 | 3470 | i915_gem_object_update_fence(obj, reg, enable); |
14415745 | 3471 | |
9ce079e4 | 3472 | return 0; |
de151cf6 JB |
3473 | } |
3474 | ||
4144f9b5 | 3475 | static bool i915_gem_valid_gtt_space(struct i915_vma *vma, |
42d6ab48 CW |
3476 | unsigned long cache_level) |
3477 | { | |
4144f9b5 | 3478 | struct drm_mm_node *gtt_space = &vma->node; |
42d6ab48 CW |
3479 | struct drm_mm_node *other; |
3480 | ||
4144f9b5 CW |
3481 | /* |
3482 | * On some machines we have to be careful when putting differing types | |
3483 | * of snoopable memory together to avoid the prefetcher crossing memory | |
3484 | * domains and dying. During vm initialisation, we decide whether or not | |
3485 | * these constraints apply and set the drm_mm.color_adjust | |
3486 | * appropriately. | |
42d6ab48 | 3487 | */ |
4144f9b5 | 3488 | if (vma->vm->mm.color_adjust == NULL) |
42d6ab48 CW |
3489 | return true; |
3490 | ||
c6cfb325 | 3491 | if (!drm_mm_node_allocated(gtt_space)) |
42d6ab48 CW |
3492 | return true; |
3493 | ||
3494 | if (list_empty(>t_space->node_list)) | |
3495 | return true; | |
3496 | ||
3497 | other = list_entry(gtt_space->node_list.prev, struct drm_mm_node, node_list); | |
3498 | if (other->allocated && !other->hole_follows && other->color != cache_level) | |
3499 | return false; | |
3500 | ||
3501 | other = list_entry(gtt_space->node_list.next, struct drm_mm_node, node_list); | |
3502 | if (other->allocated && !gtt_space->hole_follows && other->color != cache_level) | |
3503 | return false; | |
3504 | ||
3505 | return true; | |
3506 | } | |
3507 | ||
673a394b EA |
3508 | /** |
3509 | * Finds free space in the GTT aperture and binds the object there. | |
3510 | */ | |
262de145 | 3511 | static struct i915_vma * |
07fe0b12 BW |
3512 | i915_gem_object_bind_to_vm(struct drm_i915_gem_object *obj, |
3513 | struct i915_address_space *vm, | |
3514 | unsigned alignment, | |
fe14d5f4 TU |
3515 | uint64_t flags, |
3516 | const struct i915_ggtt_view *view) | |
673a394b | 3517 | { |
05394f39 | 3518 | struct drm_device *dev = obj->base.dev; |
3e31c6c0 | 3519 | struct drm_i915_private *dev_priv = dev->dev_private; |
5e783301 | 3520 | u32 size, fence_size, fence_alignment, unfenced_alignment; |
d23db88c CW |
3521 | unsigned long start = |
3522 | flags & PIN_OFFSET_BIAS ? flags & PIN_OFFSET_MASK : 0; | |
3523 | unsigned long end = | |
1ec9e26d | 3524 | flags & PIN_MAPPABLE ? dev_priv->gtt.mappable_end : vm->total; |
2f633156 | 3525 | struct i915_vma *vma; |
07f73f69 | 3526 | int ret; |
673a394b | 3527 | |
e28f8711 CW |
3528 | fence_size = i915_gem_get_gtt_size(dev, |
3529 | obj->base.size, | |
3530 | obj->tiling_mode); | |
3531 | fence_alignment = i915_gem_get_gtt_alignment(dev, | |
3532 | obj->base.size, | |
d865110c | 3533 | obj->tiling_mode, true); |
e28f8711 | 3534 | unfenced_alignment = |
d865110c | 3535 | i915_gem_get_gtt_alignment(dev, |
1ec9e26d DV |
3536 | obj->base.size, |
3537 | obj->tiling_mode, false); | |
a00b10c3 | 3538 | |
673a394b | 3539 | if (alignment == 0) |
1ec9e26d | 3540 | alignment = flags & PIN_MAPPABLE ? fence_alignment : |
5e783301 | 3541 | unfenced_alignment; |
1ec9e26d | 3542 | if (flags & PIN_MAPPABLE && alignment & (fence_alignment - 1)) { |
bd9b6a4e | 3543 | DRM_DEBUG("Invalid object alignment requested %u\n", alignment); |
262de145 | 3544 | return ERR_PTR(-EINVAL); |
673a394b EA |
3545 | } |
3546 | ||
1ec9e26d | 3547 | size = flags & PIN_MAPPABLE ? fence_size : obj->base.size; |
a00b10c3 | 3548 | |
654fc607 CW |
3549 | /* If the object is bigger than the entire aperture, reject it early |
3550 | * before evicting everything in a vain attempt to find space. | |
3551 | */ | |
d23db88c CW |
3552 | if (obj->base.size > end) { |
3553 | DRM_DEBUG("Attempting to bind an object larger than the aperture: object=%zd > %s aperture=%lu\n", | |
a36689cb | 3554 | obj->base.size, |
1ec9e26d | 3555 | flags & PIN_MAPPABLE ? "mappable" : "total", |
d23db88c | 3556 | end); |
262de145 | 3557 | return ERR_PTR(-E2BIG); |
654fc607 CW |
3558 | } |
3559 | ||
37e680a1 | 3560 | ret = i915_gem_object_get_pages(obj); |
6c085a72 | 3561 | if (ret) |
262de145 | 3562 | return ERR_PTR(ret); |
6c085a72 | 3563 | |
fbdda6fb CW |
3564 | i915_gem_object_pin_pages(obj); |
3565 | ||
fe14d5f4 | 3566 | vma = i915_gem_obj_lookup_or_create_vma_view(obj, vm, view); |
262de145 | 3567 | if (IS_ERR(vma)) |
bc6bc15b | 3568 | goto err_unpin; |
2f633156 | 3569 | |
0a9ae0d7 | 3570 | search_free: |
07fe0b12 | 3571 | ret = drm_mm_insert_node_in_range_generic(&vm->mm, &vma->node, |
0a9ae0d7 | 3572 | size, alignment, |
d23db88c CW |
3573 | obj->cache_level, |
3574 | start, end, | |
62347f9e LK |
3575 | DRM_MM_SEARCH_DEFAULT, |
3576 | DRM_MM_CREATE_DEFAULT); | |
dc9dd7a2 | 3577 | if (ret) { |
f6cd1f15 | 3578 | ret = i915_gem_evict_something(dev, vm, size, alignment, |
d23db88c CW |
3579 | obj->cache_level, |
3580 | start, end, | |
3581 | flags); | |
dc9dd7a2 CW |
3582 | if (ret == 0) |
3583 | goto search_free; | |
9731129c | 3584 | |
bc6bc15b | 3585 | goto err_free_vma; |
673a394b | 3586 | } |
4144f9b5 | 3587 | if (WARN_ON(!i915_gem_valid_gtt_space(vma, obj->cache_level))) { |
2f633156 | 3588 | ret = -EINVAL; |
bc6bc15b | 3589 | goto err_remove_node; |
673a394b EA |
3590 | } |
3591 | ||
74163907 | 3592 | ret = i915_gem_gtt_prepare_object(obj); |
2f633156 | 3593 | if (ret) |
bc6bc15b | 3594 | goto err_remove_node; |
673a394b | 3595 | |
fe14d5f4 TU |
3596 | trace_i915_vma_bind(vma, flags); |
3597 | ret = i915_vma_bind(vma, obj->cache_level, | |
3598 | flags & PIN_GLOBAL ? GLOBAL_BIND : 0); | |
3599 | if (ret) | |
3600 | goto err_finish_gtt; | |
3601 | ||
35c20a60 | 3602 | list_move_tail(&obj->global_list, &dev_priv->mm.bound_list); |
ca191b13 | 3603 | list_add_tail(&vma->mm_list, &vm->inactive_list); |
bf1a1092 | 3604 | |
262de145 | 3605 | return vma; |
2f633156 | 3606 | |
fe14d5f4 TU |
3607 | err_finish_gtt: |
3608 | i915_gem_gtt_finish_object(obj); | |
bc6bc15b | 3609 | err_remove_node: |
6286ef9b | 3610 | drm_mm_remove_node(&vma->node); |
bc6bc15b | 3611 | err_free_vma: |
2f633156 | 3612 | i915_gem_vma_destroy(vma); |
262de145 | 3613 | vma = ERR_PTR(ret); |
bc6bc15b | 3614 | err_unpin: |
2f633156 | 3615 | i915_gem_object_unpin_pages(obj); |
262de145 | 3616 | return vma; |
673a394b EA |
3617 | } |
3618 | ||
000433b6 | 3619 | bool |
2c22569b CW |
3620 | i915_gem_clflush_object(struct drm_i915_gem_object *obj, |
3621 | bool force) | |
673a394b | 3622 | { |
673a394b EA |
3623 | /* If we don't have a page list set up, then we're not pinned |
3624 | * to GPU, and we can ignore the cache flush because it'll happen | |
3625 | * again at bind time. | |
3626 | */ | |
05394f39 | 3627 | if (obj->pages == NULL) |
000433b6 | 3628 | return false; |
673a394b | 3629 | |
769ce464 ID |
3630 | /* |
3631 | * Stolen memory is always coherent with the GPU as it is explicitly | |
3632 | * marked as wc by the system, or the system is cache-coherent. | |
3633 | */ | |
6a2c4232 | 3634 | if (obj->stolen || obj->phys_handle) |
000433b6 | 3635 | return false; |
769ce464 | 3636 | |
9c23f7fc CW |
3637 | /* If the GPU is snooping the contents of the CPU cache, |
3638 | * we do not need to manually clear the CPU cache lines. However, | |
3639 | * the caches are only snooped when the render cache is | |
3640 | * flushed/invalidated. As we always have to emit invalidations | |
3641 | * and flushes when moving into and out of the RENDER domain, correct | |
3642 | * snooping behaviour occurs naturally as the result of our domain | |
3643 | * tracking. | |
3644 | */ | |
0f71979a CW |
3645 | if (!force && cpu_cache_is_coherent(obj->base.dev, obj->cache_level)) { |
3646 | obj->cache_dirty = true; | |
000433b6 | 3647 | return false; |
0f71979a | 3648 | } |
9c23f7fc | 3649 | |
1c5d22f7 | 3650 | trace_i915_gem_object_clflush(obj); |
9da3da66 | 3651 | drm_clflush_sg(obj->pages); |
0f71979a | 3652 | obj->cache_dirty = false; |
000433b6 CW |
3653 | |
3654 | return true; | |
e47c68e9 EA |
3655 | } |
3656 | ||
3657 | /** Flushes the GTT write domain for the object if it's dirty. */ | |
3658 | static void | |
05394f39 | 3659 | i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj) |
e47c68e9 | 3660 | { |
1c5d22f7 CW |
3661 | uint32_t old_write_domain; |
3662 | ||
05394f39 | 3663 | if (obj->base.write_domain != I915_GEM_DOMAIN_GTT) |
e47c68e9 EA |
3664 | return; |
3665 | ||
63256ec5 | 3666 | /* No actual flushing is required for the GTT write domain. Writes |
e47c68e9 EA |
3667 | * to it immediately go to main memory as far as we know, so there's |
3668 | * no chipset flush. It also doesn't land in render cache. | |
63256ec5 CW |
3669 | * |
3670 | * However, we do have to enforce the order so that all writes through | |
3671 | * the GTT land before any writes to the device, such as updates to | |
3672 | * the GATT itself. | |
e47c68e9 | 3673 | */ |
63256ec5 CW |
3674 | wmb(); |
3675 | ||
05394f39 CW |
3676 | old_write_domain = obj->base.write_domain; |
3677 | obj->base.write_domain = 0; | |
1c5d22f7 | 3678 | |
f99d7069 DV |
3679 | intel_fb_obj_flush(obj, false); |
3680 | ||
1c5d22f7 | 3681 | trace_i915_gem_object_change_domain(obj, |
05394f39 | 3682 | obj->base.read_domains, |
1c5d22f7 | 3683 | old_write_domain); |
e47c68e9 EA |
3684 | } |
3685 | ||
3686 | /** Flushes the CPU write domain for the object if it's dirty. */ | |
3687 | static void | |
e62b59e4 | 3688 | i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj) |
e47c68e9 | 3689 | { |
1c5d22f7 | 3690 | uint32_t old_write_domain; |
e47c68e9 | 3691 | |
05394f39 | 3692 | if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) |
e47c68e9 EA |
3693 | return; |
3694 | ||
e62b59e4 | 3695 | if (i915_gem_clflush_object(obj, obj->pin_display)) |
000433b6 CW |
3696 | i915_gem_chipset_flush(obj->base.dev); |
3697 | ||
05394f39 CW |
3698 | old_write_domain = obj->base.write_domain; |
3699 | obj->base.write_domain = 0; | |
1c5d22f7 | 3700 | |
f99d7069 DV |
3701 | intel_fb_obj_flush(obj, false); |
3702 | ||
1c5d22f7 | 3703 | trace_i915_gem_object_change_domain(obj, |
05394f39 | 3704 | obj->base.read_domains, |
1c5d22f7 | 3705 | old_write_domain); |
e47c68e9 EA |
3706 | } |
3707 | ||
2ef7eeaa EA |
3708 | /** |
3709 | * Moves a single object to the GTT read, and possibly write domain. | |
3710 | * | |
3711 | * This function returns when the move is complete, including waiting on | |
3712 | * flushes to occur. | |
3713 | */ | |
79e53945 | 3714 | int |
2021746e | 3715 | i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write) |
2ef7eeaa | 3716 | { |
1c5d22f7 | 3717 | uint32_t old_write_domain, old_read_domains; |
43566ded | 3718 | struct i915_vma *vma; |
e47c68e9 | 3719 | int ret; |
2ef7eeaa | 3720 | |
8d7e3de1 CW |
3721 | if (obj->base.write_domain == I915_GEM_DOMAIN_GTT) |
3722 | return 0; | |
3723 | ||
0201f1ec | 3724 | ret = i915_gem_object_wait_rendering(obj, !write); |
88241785 CW |
3725 | if (ret) |
3726 | return ret; | |
3727 | ||
c8725f3d | 3728 | i915_gem_object_retire(obj); |
43566ded CW |
3729 | |
3730 | /* Flush and acquire obj->pages so that we are coherent through | |
3731 | * direct access in memory with previous cached writes through | |
3732 | * shmemfs and that our cache domain tracking remains valid. | |
3733 | * For example, if the obj->filp was moved to swap without us | |
3734 | * being notified and releasing the pages, we would mistakenly | |
3735 | * continue to assume that the obj remained out of the CPU cached | |
3736 | * domain. | |
3737 | */ | |
3738 | ret = i915_gem_object_get_pages(obj); | |
3739 | if (ret) | |
3740 | return ret; | |
3741 | ||
e62b59e4 | 3742 | i915_gem_object_flush_cpu_write_domain(obj); |
1c5d22f7 | 3743 | |
d0a57789 CW |
3744 | /* Serialise direct access to this object with the barriers for |
3745 | * coherent writes from the GPU, by effectively invalidating the | |
3746 | * GTT domain upon first access. | |
3747 | */ | |
3748 | if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0) | |
3749 | mb(); | |
3750 | ||
05394f39 CW |
3751 | old_write_domain = obj->base.write_domain; |
3752 | old_read_domains = obj->base.read_domains; | |
1c5d22f7 | 3753 | |
e47c68e9 EA |
3754 | /* It should now be out of any other write domains, and we can update |
3755 | * the domain values for our changes. | |
3756 | */ | |
05394f39 CW |
3757 | BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) != 0); |
3758 | obj->base.read_domains |= I915_GEM_DOMAIN_GTT; | |
e47c68e9 | 3759 | if (write) { |
05394f39 CW |
3760 | obj->base.read_domains = I915_GEM_DOMAIN_GTT; |
3761 | obj->base.write_domain = I915_GEM_DOMAIN_GTT; | |
3762 | obj->dirty = 1; | |
2ef7eeaa EA |
3763 | } |
3764 | ||
f99d7069 DV |
3765 | if (write) |
3766 | intel_fb_obj_invalidate(obj, NULL); | |
3767 | ||
1c5d22f7 CW |
3768 | trace_i915_gem_object_change_domain(obj, |
3769 | old_read_domains, | |
3770 | old_write_domain); | |
3771 | ||
8325a09d | 3772 | /* And bump the LRU for this access */ |
43566ded CW |
3773 | vma = i915_gem_obj_to_ggtt(obj); |
3774 | if (vma && drm_mm_node_allocated(&vma->node) && !obj->active) | |
dc8cd1e7 | 3775 | list_move_tail(&vma->mm_list, |
43566ded | 3776 | &to_i915(obj->base.dev)->gtt.base.inactive_list); |
8325a09d | 3777 | |
e47c68e9 EA |
3778 | return 0; |
3779 | } | |
3780 | ||
e4ffd173 CW |
3781 | int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj, |
3782 | enum i915_cache_level cache_level) | |
3783 | { | |
7bddb01f | 3784 | struct drm_device *dev = obj->base.dev; |
df6f783a | 3785 | struct i915_vma *vma, *next; |
e4ffd173 CW |
3786 | int ret; |
3787 | ||
3788 | if (obj->cache_level == cache_level) | |
3789 | return 0; | |
3790 | ||
d7f46fc4 | 3791 | if (i915_gem_obj_is_pinned(obj)) { |
e4ffd173 CW |
3792 | DRM_DEBUG("can not change the cache level of pinned objects\n"); |
3793 | return -EBUSY; | |
3794 | } | |
3795 | ||
df6f783a | 3796 | list_for_each_entry_safe(vma, next, &obj->vma_list, vma_link) { |
4144f9b5 | 3797 | if (!i915_gem_valid_gtt_space(vma, cache_level)) { |
07fe0b12 | 3798 | ret = i915_vma_unbind(vma); |
3089c6f2 BW |
3799 | if (ret) |
3800 | return ret; | |
3089c6f2 | 3801 | } |
42d6ab48 CW |
3802 | } |
3803 | ||
3089c6f2 | 3804 | if (i915_gem_obj_bound_any(obj)) { |
e4ffd173 CW |
3805 | ret = i915_gem_object_finish_gpu(obj); |
3806 | if (ret) | |
3807 | return ret; | |
3808 | ||
3809 | i915_gem_object_finish_gtt(obj); | |
3810 | ||
3811 | /* Before SandyBridge, you could not use tiling or fence | |
3812 | * registers with snooped memory, so relinquish any fences | |
3813 | * currently pointing to our region in the aperture. | |
3814 | */ | |
42d6ab48 | 3815 | if (INTEL_INFO(dev)->gen < 6) { |
e4ffd173 CW |
3816 | ret = i915_gem_object_put_fence(obj); |
3817 | if (ret) | |
3818 | return ret; | |
3819 | } | |
3820 | ||
6f65e29a | 3821 | list_for_each_entry(vma, &obj->vma_list, vma_link) |
fe14d5f4 TU |
3822 | if (drm_mm_node_allocated(&vma->node)) { |
3823 | ret = i915_vma_bind(vma, cache_level, | |
3824 | vma->bound & GLOBAL_BIND); | |
3825 | if (ret) | |
3826 | return ret; | |
3827 | } | |
e4ffd173 CW |
3828 | } |
3829 | ||
2c22569b CW |
3830 | list_for_each_entry(vma, &obj->vma_list, vma_link) |
3831 | vma->node.color = cache_level; | |
3832 | obj->cache_level = cache_level; | |
3833 | ||
0f71979a CW |
3834 | if (obj->cache_dirty && |
3835 | obj->base.write_domain != I915_GEM_DOMAIN_CPU && | |
3836 | cpu_write_needs_clflush(obj)) { | |
3837 | if (i915_gem_clflush_object(obj, true)) | |
3838 | i915_gem_chipset_flush(obj->base.dev); | |
e4ffd173 CW |
3839 | } |
3840 | ||
e4ffd173 CW |
3841 | return 0; |
3842 | } | |
3843 | ||
199adf40 BW |
3844 | int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data, |
3845 | struct drm_file *file) | |
e6994aee | 3846 | { |
199adf40 | 3847 | struct drm_i915_gem_caching *args = data; |
e6994aee CW |
3848 | struct drm_i915_gem_object *obj; |
3849 | int ret; | |
3850 | ||
3851 | ret = i915_mutex_lock_interruptible(dev); | |
3852 | if (ret) | |
3853 | return ret; | |
3854 | ||
3855 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); | |
3856 | if (&obj->base == NULL) { | |
3857 | ret = -ENOENT; | |
3858 | goto unlock; | |
3859 | } | |
3860 | ||
651d794f CW |
3861 | switch (obj->cache_level) { |
3862 | case I915_CACHE_LLC: | |
3863 | case I915_CACHE_L3_LLC: | |
3864 | args->caching = I915_CACHING_CACHED; | |
3865 | break; | |
3866 | ||
4257d3ba CW |
3867 | case I915_CACHE_WT: |
3868 | args->caching = I915_CACHING_DISPLAY; | |
3869 | break; | |
3870 | ||
651d794f CW |
3871 | default: |
3872 | args->caching = I915_CACHING_NONE; | |
3873 | break; | |
3874 | } | |
e6994aee CW |
3875 | |
3876 | drm_gem_object_unreference(&obj->base); | |
3877 | unlock: | |
3878 | mutex_unlock(&dev->struct_mutex); | |
3879 | return ret; | |
3880 | } | |
3881 | ||
199adf40 BW |
3882 | int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data, |
3883 | struct drm_file *file) | |
e6994aee | 3884 | { |
199adf40 | 3885 | struct drm_i915_gem_caching *args = data; |
e6994aee CW |
3886 | struct drm_i915_gem_object *obj; |
3887 | enum i915_cache_level level; | |
3888 | int ret; | |
3889 | ||
199adf40 BW |
3890 | switch (args->caching) { |
3891 | case I915_CACHING_NONE: | |
e6994aee CW |
3892 | level = I915_CACHE_NONE; |
3893 | break; | |
199adf40 | 3894 | case I915_CACHING_CACHED: |
e6994aee CW |
3895 | level = I915_CACHE_LLC; |
3896 | break; | |
4257d3ba CW |
3897 | case I915_CACHING_DISPLAY: |
3898 | level = HAS_WT(dev) ? I915_CACHE_WT : I915_CACHE_NONE; | |
3899 | break; | |
e6994aee CW |
3900 | default: |
3901 | return -EINVAL; | |
3902 | } | |
3903 | ||
3bc2913e BW |
3904 | ret = i915_mutex_lock_interruptible(dev); |
3905 | if (ret) | |
3906 | return ret; | |
3907 | ||
e6994aee CW |
3908 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
3909 | if (&obj->base == NULL) { | |
3910 | ret = -ENOENT; | |
3911 | goto unlock; | |
3912 | } | |
3913 | ||
3914 | ret = i915_gem_object_set_cache_level(obj, level); | |
3915 | ||
3916 | drm_gem_object_unreference(&obj->base); | |
3917 | unlock: | |
3918 | mutex_unlock(&dev->struct_mutex); | |
3919 | return ret; | |
3920 | } | |
3921 | ||
cc98b413 CW |
3922 | static bool is_pin_display(struct drm_i915_gem_object *obj) |
3923 | { | |
19656430 OM |
3924 | struct i915_vma *vma; |
3925 | ||
19656430 OM |
3926 | vma = i915_gem_obj_to_ggtt(obj); |
3927 | if (!vma) | |
3928 | return false; | |
3929 | ||
4feb7659 | 3930 | /* There are 2 sources that pin objects: |
cc98b413 CW |
3931 | * 1. The display engine (scanouts, sprites, cursors); |
3932 | * 2. Reservations for execbuffer; | |
cc98b413 CW |
3933 | * |
3934 | * We can ignore reservations as we hold the struct_mutex and | |
4feb7659 | 3935 | * are only called outside of the reservation path. |
cc98b413 | 3936 | */ |
4feb7659 | 3937 | return vma->pin_count; |
cc98b413 CW |
3938 | } |
3939 | ||
b9241ea3 | 3940 | /* |
2da3b9b9 CW |
3941 | * Prepare buffer for display plane (scanout, cursors, etc). |
3942 | * Can be called from an uninterruptible phase (modesetting) and allows | |
3943 | * any flushes to be pipelined (for pageflips). | |
b9241ea3 ZW |
3944 | */ |
3945 | int | |
2da3b9b9 CW |
3946 | i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj, |
3947 | u32 alignment, | |
a4872ba6 | 3948 | struct intel_engine_cs *pipelined) |
b9241ea3 | 3949 | { |
2da3b9b9 | 3950 | u32 old_read_domains, old_write_domain; |
19656430 | 3951 | bool was_pin_display; |
b9241ea3 ZW |
3952 | int ret; |
3953 | ||
41c52415 | 3954 | if (pipelined != i915_gem_request_get_ring(obj->last_read_req)) { |
2911a35b BW |
3955 | ret = i915_gem_object_sync(obj, pipelined); |
3956 | if (ret) | |
b9241ea3 ZW |
3957 | return ret; |
3958 | } | |
3959 | ||
cc98b413 CW |
3960 | /* Mark the pin_display early so that we account for the |
3961 | * display coherency whilst setting up the cache domains. | |
3962 | */ | |
19656430 | 3963 | was_pin_display = obj->pin_display; |
cc98b413 CW |
3964 | obj->pin_display = true; |
3965 | ||
a7ef0640 EA |
3966 | /* The display engine is not coherent with the LLC cache on gen6. As |
3967 | * a result, we make sure that the pinning that is about to occur is | |
3968 | * done with uncached PTEs. This is lowest common denominator for all | |
3969 | * chipsets. | |
3970 | * | |
3971 | * However for gen6+, we could do better by using the GFDT bit instead | |
3972 | * of uncaching, which would allow us to flush all the LLC-cached data | |
3973 | * with that bit in the PTE to main memory with just one PIPE_CONTROL. | |
3974 | */ | |
651d794f CW |
3975 | ret = i915_gem_object_set_cache_level(obj, |
3976 | HAS_WT(obj->base.dev) ? I915_CACHE_WT : I915_CACHE_NONE); | |
a7ef0640 | 3977 | if (ret) |
cc98b413 | 3978 | goto err_unpin_display; |
a7ef0640 | 3979 | |
2da3b9b9 CW |
3980 | /* As the user may map the buffer once pinned in the display plane |
3981 | * (e.g. libkms for the bootup splash), we have to ensure that we | |
3982 | * always use map_and_fenceable for all scanout buffers. | |
3983 | */ | |
1ec9e26d | 3984 | ret = i915_gem_obj_ggtt_pin(obj, alignment, PIN_MAPPABLE); |
2da3b9b9 | 3985 | if (ret) |
cc98b413 | 3986 | goto err_unpin_display; |
2da3b9b9 | 3987 | |
e62b59e4 | 3988 | i915_gem_object_flush_cpu_write_domain(obj); |
b118c1e3 | 3989 | |
2da3b9b9 | 3990 | old_write_domain = obj->base.write_domain; |
05394f39 | 3991 | old_read_domains = obj->base.read_domains; |
2da3b9b9 CW |
3992 | |
3993 | /* It should now be out of any other write domains, and we can update | |
3994 | * the domain values for our changes. | |
3995 | */ | |
e5f1d962 | 3996 | obj->base.write_domain = 0; |
05394f39 | 3997 | obj->base.read_domains |= I915_GEM_DOMAIN_GTT; |
b9241ea3 ZW |
3998 | |
3999 | trace_i915_gem_object_change_domain(obj, | |
4000 | old_read_domains, | |
2da3b9b9 | 4001 | old_write_domain); |
b9241ea3 ZW |
4002 | |
4003 | return 0; | |
cc98b413 CW |
4004 | |
4005 | err_unpin_display: | |
19656430 OM |
4006 | WARN_ON(was_pin_display != is_pin_display(obj)); |
4007 | obj->pin_display = was_pin_display; | |
cc98b413 CW |
4008 | return ret; |
4009 | } | |
4010 | ||
4011 | void | |
4012 | i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object *obj) | |
4013 | { | |
d7f46fc4 | 4014 | i915_gem_object_ggtt_unpin(obj); |
cc98b413 | 4015 | obj->pin_display = is_pin_display(obj); |
b9241ea3 ZW |
4016 | } |
4017 | ||
85345517 | 4018 | int |
a8198eea | 4019 | i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj) |
85345517 | 4020 | { |
88241785 CW |
4021 | int ret; |
4022 | ||
a8198eea | 4023 | if ((obj->base.read_domains & I915_GEM_GPU_DOMAINS) == 0) |
85345517 CW |
4024 | return 0; |
4025 | ||
0201f1ec | 4026 | ret = i915_gem_object_wait_rendering(obj, false); |
c501ae7f CW |
4027 | if (ret) |
4028 | return ret; | |
4029 | ||
a8198eea CW |
4030 | /* Ensure that we invalidate the GPU's caches and TLBs. */ |
4031 | obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS; | |
c501ae7f | 4032 | return 0; |
85345517 CW |
4033 | } |
4034 | ||
e47c68e9 EA |
4035 | /** |
4036 | * Moves a single object to the CPU read, and possibly write domain. | |
4037 | * | |
4038 | * This function returns when the move is complete, including waiting on | |
4039 | * flushes to occur. | |
4040 | */ | |
dabdfe02 | 4041 | int |
919926ae | 4042 | i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write) |
e47c68e9 | 4043 | { |
1c5d22f7 | 4044 | uint32_t old_write_domain, old_read_domains; |
e47c68e9 EA |
4045 | int ret; |
4046 | ||
8d7e3de1 CW |
4047 | if (obj->base.write_domain == I915_GEM_DOMAIN_CPU) |
4048 | return 0; | |
4049 | ||
0201f1ec | 4050 | ret = i915_gem_object_wait_rendering(obj, !write); |
88241785 CW |
4051 | if (ret) |
4052 | return ret; | |
4053 | ||
c8725f3d | 4054 | i915_gem_object_retire(obj); |
e47c68e9 | 4055 | i915_gem_object_flush_gtt_write_domain(obj); |
2ef7eeaa | 4056 | |
05394f39 CW |
4057 | old_write_domain = obj->base.write_domain; |
4058 | old_read_domains = obj->base.read_domains; | |
1c5d22f7 | 4059 | |
e47c68e9 | 4060 | /* Flush the CPU cache if it's still invalid. */ |
05394f39 | 4061 | if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) { |
2c22569b | 4062 | i915_gem_clflush_object(obj, false); |
2ef7eeaa | 4063 | |
05394f39 | 4064 | obj->base.read_domains |= I915_GEM_DOMAIN_CPU; |
2ef7eeaa EA |
4065 | } |
4066 | ||
4067 | /* It should now be out of any other write domains, and we can update | |
4068 | * the domain values for our changes. | |
4069 | */ | |
05394f39 | 4070 | BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) != 0); |
e47c68e9 EA |
4071 | |
4072 | /* If we're writing through the CPU, then the GPU read domains will | |
4073 | * need to be invalidated at next use. | |
4074 | */ | |
4075 | if (write) { | |
05394f39 CW |
4076 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; |
4077 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; | |
e47c68e9 | 4078 | } |
2ef7eeaa | 4079 | |
f99d7069 DV |
4080 | if (write) |
4081 | intel_fb_obj_invalidate(obj, NULL); | |
4082 | ||
1c5d22f7 CW |
4083 | trace_i915_gem_object_change_domain(obj, |
4084 | old_read_domains, | |
4085 | old_write_domain); | |
4086 | ||
2ef7eeaa EA |
4087 | return 0; |
4088 | } | |
4089 | ||
673a394b EA |
4090 | /* Throttle our rendering by waiting until the ring has completed our requests |
4091 | * emitted over 20 msec ago. | |
4092 | * | |
b962442e EA |
4093 | * Note that if we were to use the current jiffies each time around the loop, |
4094 | * we wouldn't escape the function with any frames outstanding if the time to | |
4095 | * render a frame was over 20ms. | |
4096 | * | |
673a394b EA |
4097 | * This should get us reasonable parallelism between CPU and GPU but also |
4098 | * relatively low latency when blocking on a particular request to finish. | |
4099 | */ | |
40a5f0de | 4100 | static int |
f787a5f5 | 4101 | i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file) |
40a5f0de | 4102 | { |
f787a5f5 CW |
4103 | struct drm_i915_private *dev_priv = dev->dev_private; |
4104 | struct drm_i915_file_private *file_priv = file->driver_priv; | |
b962442e | 4105 | unsigned long recent_enough = jiffies - msecs_to_jiffies(20); |
54fb2411 | 4106 | struct drm_i915_gem_request *request, *target = NULL; |
f69061be | 4107 | unsigned reset_counter; |
f787a5f5 | 4108 | int ret; |
93533c29 | 4109 | |
308887aa DV |
4110 | ret = i915_gem_wait_for_error(&dev_priv->gpu_error); |
4111 | if (ret) | |
4112 | return ret; | |
4113 | ||
4114 | ret = i915_gem_check_wedge(&dev_priv->gpu_error, false); | |
4115 | if (ret) | |
4116 | return ret; | |
e110e8d6 | 4117 | |
1c25595f | 4118 | spin_lock(&file_priv->mm.lock); |
f787a5f5 | 4119 | list_for_each_entry(request, &file_priv->mm.request_list, client_list) { |
b962442e EA |
4120 | if (time_after_eq(request->emitted_jiffies, recent_enough)) |
4121 | break; | |
40a5f0de | 4122 | |
54fb2411 | 4123 | target = request; |
b962442e | 4124 | } |
f69061be | 4125 | reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter); |
ff865885 JH |
4126 | if (target) |
4127 | i915_gem_request_reference(target); | |
1c25595f | 4128 | spin_unlock(&file_priv->mm.lock); |
40a5f0de | 4129 | |
54fb2411 | 4130 | if (target == NULL) |
f787a5f5 | 4131 | return 0; |
2bc43b5c | 4132 | |
9c654818 | 4133 | ret = __i915_wait_request(target, reset_counter, true, NULL, NULL); |
f787a5f5 CW |
4134 | if (ret == 0) |
4135 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, 0); | |
40a5f0de | 4136 | |
ff865885 JH |
4137 | mutex_lock(&dev->struct_mutex); |
4138 | i915_gem_request_unreference(target); | |
4139 | mutex_unlock(&dev->struct_mutex); | |
4140 | ||
40a5f0de EA |
4141 | return ret; |
4142 | } | |
4143 | ||
d23db88c CW |
4144 | static bool |
4145 | i915_vma_misplaced(struct i915_vma *vma, uint32_t alignment, uint64_t flags) | |
4146 | { | |
4147 | struct drm_i915_gem_object *obj = vma->obj; | |
4148 | ||
4149 | if (alignment && | |
4150 | vma->node.start & (alignment - 1)) | |
4151 | return true; | |
4152 | ||
4153 | if (flags & PIN_MAPPABLE && !obj->map_and_fenceable) | |
4154 | return true; | |
4155 | ||
4156 | if (flags & PIN_OFFSET_BIAS && | |
4157 | vma->node.start < (flags & PIN_OFFSET_MASK)) | |
4158 | return true; | |
4159 | ||
4160 | return false; | |
4161 | } | |
4162 | ||
673a394b | 4163 | int |
fe14d5f4 TU |
4164 | i915_gem_object_pin_view(struct drm_i915_gem_object *obj, |
4165 | struct i915_address_space *vm, | |
4166 | uint32_t alignment, | |
4167 | uint64_t flags, | |
4168 | const struct i915_ggtt_view *view) | |
673a394b | 4169 | { |
6e7186af | 4170 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
07fe0b12 | 4171 | struct i915_vma *vma; |
ef79e17c | 4172 | unsigned bound; |
673a394b EA |
4173 | int ret; |
4174 | ||
6e7186af BW |
4175 | if (WARN_ON(vm == &dev_priv->mm.aliasing_ppgtt->base)) |
4176 | return -ENODEV; | |
4177 | ||
bf3d149b | 4178 | if (WARN_ON(flags & (PIN_GLOBAL | PIN_MAPPABLE) && !i915_is_ggtt(vm))) |
1ec9e26d | 4179 | return -EINVAL; |
07fe0b12 | 4180 | |
c826c449 CW |
4181 | if (WARN_ON((flags & (PIN_MAPPABLE | PIN_GLOBAL)) == PIN_MAPPABLE)) |
4182 | return -EINVAL; | |
4183 | ||
fe14d5f4 | 4184 | vma = i915_gem_obj_to_vma_view(obj, vm, view); |
07fe0b12 | 4185 | if (vma) { |
d7f46fc4 BW |
4186 | if (WARN_ON(vma->pin_count == DRM_I915_GEM_OBJECT_MAX_PIN_COUNT)) |
4187 | return -EBUSY; | |
4188 | ||
d23db88c | 4189 | if (i915_vma_misplaced(vma, alignment, flags)) { |
d7f46fc4 | 4190 | WARN(vma->pin_count, |
ae7d49d8 | 4191 | "bo is already pinned with incorrect alignment:" |
f343c5f6 | 4192 | " offset=%lx, req.alignment=%x, req.map_and_fenceable=%d," |
75e9e915 | 4193 | " obj->map_and_fenceable=%d\n", |
fe14d5f4 TU |
4194 | i915_gem_obj_offset_view(obj, vm, view->type), |
4195 | alignment, | |
d23db88c | 4196 | !!(flags & PIN_MAPPABLE), |
05394f39 | 4197 | obj->map_and_fenceable); |
07fe0b12 | 4198 | ret = i915_vma_unbind(vma); |
ac0c6b5a CW |
4199 | if (ret) |
4200 | return ret; | |
8ea99c92 DV |
4201 | |
4202 | vma = NULL; | |
ac0c6b5a CW |
4203 | } |
4204 | } | |
4205 | ||
ef79e17c | 4206 | bound = vma ? vma->bound : 0; |
8ea99c92 | 4207 | if (vma == NULL || !drm_mm_node_allocated(&vma->node)) { |
fe14d5f4 TU |
4208 | vma = i915_gem_object_bind_to_vm(obj, vm, alignment, |
4209 | flags, view); | |
262de145 DV |
4210 | if (IS_ERR(vma)) |
4211 | return PTR_ERR(vma); | |
22c344e9 | 4212 | } |
76446cac | 4213 | |
fe14d5f4 TU |
4214 | if (flags & PIN_GLOBAL && !(vma->bound & GLOBAL_BIND)) { |
4215 | ret = i915_vma_bind(vma, obj->cache_level, GLOBAL_BIND); | |
4216 | if (ret) | |
4217 | return ret; | |
4218 | } | |
74898d7e | 4219 | |
ef79e17c CW |
4220 | if ((bound ^ vma->bound) & GLOBAL_BIND) { |
4221 | bool mappable, fenceable; | |
4222 | u32 fence_size, fence_alignment; | |
4223 | ||
4224 | fence_size = i915_gem_get_gtt_size(obj->base.dev, | |
4225 | obj->base.size, | |
4226 | obj->tiling_mode); | |
4227 | fence_alignment = i915_gem_get_gtt_alignment(obj->base.dev, | |
4228 | obj->base.size, | |
4229 | obj->tiling_mode, | |
4230 | true); | |
4231 | ||
4232 | fenceable = (vma->node.size == fence_size && | |
4233 | (vma->node.start & (fence_alignment - 1)) == 0); | |
4234 | ||
4235 | mappable = (vma->node.start + obj->base.size <= | |
4236 | dev_priv->gtt.mappable_end); | |
4237 | ||
4238 | obj->map_and_fenceable = mappable && fenceable; | |
4239 | } | |
4240 | ||
4241 | WARN_ON(flags & PIN_MAPPABLE && !obj->map_and_fenceable); | |
4242 | ||
8ea99c92 | 4243 | vma->pin_count++; |
1ec9e26d DV |
4244 | if (flags & PIN_MAPPABLE) |
4245 | obj->pin_mappable |= true; | |
673a394b EA |
4246 | |
4247 | return 0; | |
4248 | } | |
4249 | ||
4250 | void | |
d7f46fc4 | 4251 | i915_gem_object_ggtt_unpin(struct drm_i915_gem_object *obj) |
673a394b | 4252 | { |
d7f46fc4 | 4253 | struct i915_vma *vma = i915_gem_obj_to_ggtt(obj); |
673a394b | 4254 | |
d7f46fc4 BW |
4255 | BUG_ON(!vma); |
4256 | BUG_ON(vma->pin_count == 0); | |
4257 | BUG_ON(!i915_gem_obj_ggtt_bound(obj)); | |
4258 | ||
4259 | if (--vma->pin_count == 0) | |
6299f992 | 4260 | obj->pin_mappable = false; |
673a394b EA |
4261 | } |
4262 | ||
d8ffa60b DV |
4263 | bool |
4264 | i915_gem_object_pin_fence(struct drm_i915_gem_object *obj) | |
4265 | { | |
4266 | if (obj->fence_reg != I915_FENCE_REG_NONE) { | |
4267 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; | |
4268 | struct i915_vma *ggtt_vma = i915_gem_obj_to_ggtt(obj); | |
4269 | ||
4270 | WARN_ON(!ggtt_vma || | |
4271 | dev_priv->fence_regs[obj->fence_reg].pin_count > | |
4272 | ggtt_vma->pin_count); | |
4273 | dev_priv->fence_regs[obj->fence_reg].pin_count++; | |
4274 | return true; | |
4275 | } else | |
4276 | return false; | |
4277 | } | |
4278 | ||
4279 | void | |
4280 | i915_gem_object_unpin_fence(struct drm_i915_gem_object *obj) | |
4281 | { | |
4282 | if (obj->fence_reg != I915_FENCE_REG_NONE) { | |
4283 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; | |
4284 | WARN_ON(dev_priv->fence_regs[obj->fence_reg].pin_count <= 0); | |
4285 | dev_priv->fence_regs[obj->fence_reg].pin_count--; | |
4286 | } | |
4287 | } | |
4288 | ||
673a394b EA |
4289 | int |
4290 | i915_gem_busy_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 4291 | struct drm_file *file) |
673a394b EA |
4292 | { |
4293 | struct drm_i915_gem_busy *args = data; | |
05394f39 | 4294 | struct drm_i915_gem_object *obj; |
30dbf0c0 CW |
4295 | int ret; |
4296 | ||
76c1dec1 | 4297 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 4298 | if (ret) |
76c1dec1 | 4299 | return ret; |
673a394b | 4300 | |
05394f39 | 4301 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 4302 | if (&obj->base == NULL) { |
1d7cfea1 CW |
4303 | ret = -ENOENT; |
4304 | goto unlock; | |
673a394b | 4305 | } |
d1b851fc | 4306 | |
0be555b6 CW |
4307 | /* Count all active objects as busy, even if they are currently not used |
4308 | * by the gpu. Users of this interface expect objects to eventually | |
4309 | * become non-busy without any further actions, therefore emit any | |
4310 | * necessary flushes here. | |
c4de0a5d | 4311 | */ |
30dfebf3 | 4312 | ret = i915_gem_object_flush_active(obj); |
0be555b6 | 4313 | |
30dfebf3 | 4314 | args->busy = obj->active; |
41c52415 JH |
4315 | if (obj->last_read_req) { |
4316 | struct intel_engine_cs *ring; | |
e9808edd | 4317 | BUILD_BUG_ON(I915_NUM_RINGS > 16); |
41c52415 JH |
4318 | ring = i915_gem_request_get_ring(obj->last_read_req); |
4319 | args->busy |= intel_ring_flag(ring) << 16; | |
e9808edd | 4320 | } |
673a394b | 4321 | |
05394f39 | 4322 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 4323 | unlock: |
673a394b | 4324 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 4325 | return ret; |
673a394b EA |
4326 | } |
4327 | ||
4328 | int | |
4329 | i915_gem_throttle_ioctl(struct drm_device *dev, void *data, | |
4330 | struct drm_file *file_priv) | |
4331 | { | |
0206e353 | 4332 | return i915_gem_ring_throttle(dev, file_priv); |
673a394b EA |
4333 | } |
4334 | ||
3ef94daa CW |
4335 | int |
4336 | i915_gem_madvise_ioctl(struct drm_device *dev, void *data, | |
4337 | struct drm_file *file_priv) | |
4338 | { | |
656bfa3a | 4339 | struct drm_i915_private *dev_priv = dev->dev_private; |
3ef94daa | 4340 | struct drm_i915_gem_madvise *args = data; |
05394f39 | 4341 | struct drm_i915_gem_object *obj; |
76c1dec1 | 4342 | int ret; |
3ef94daa CW |
4343 | |
4344 | switch (args->madv) { | |
4345 | case I915_MADV_DONTNEED: | |
4346 | case I915_MADV_WILLNEED: | |
4347 | break; | |
4348 | default: | |
4349 | return -EINVAL; | |
4350 | } | |
4351 | ||
1d7cfea1 CW |
4352 | ret = i915_mutex_lock_interruptible(dev); |
4353 | if (ret) | |
4354 | return ret; | |
4355 | ||
05394f39 | 4356 | obj = to_intel_bo(drm_gem_object_lookup(dev, file_priv, args->handle)); |
c8725226 | 4357 | if (&obj->base == NULL) { |
1d7cfea1 CW |
4358 | ret = -ENOENT; |
4359 | goto unlock; | |
3ef94daa | 4360 | } |
3ef94daa | 4361 | |
d7f46fc4 | 4362 | if (i915_gem_obj_is_pinned(obj)) { |
1d7cfea1 CW |
4363 | ret = -EINVAL; |
4364 | goto out; | |
3ef94daa CW |
4365 | } |
4366 | ||
656bfa3a DV |
4367 | if (obj->pages && |
4368 | obj->tiling_mode != I915_TILING_NONE && | |
4369 | dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES) { | |
4370 | if (obj->madv == I915_MADV_WILLNEED) | |
4371 | i915_gem_object_unpin_pages(obj); | |
4372 | if (args->madv == I915_MADV_WILLNEED) | |
4373 | i915_gem_object_pin_pages(obj); | |
4374 | } | |
4375 | ||
05394f39 CW |
4376 | if (obj->madv != __I915_MADV_PURGED) |
4377 | obj->madv = args->madv; | |
3ef94daa | 4378 | |
6c085a72 CW |
4379 | /* if the object is no longer attached, discard its backing storage */ |
4380 | if (i915_gem_object_is_purgeable(obj) && obj->pages == NULL) | |
2d7ef395 CW |
4381 | i915_gem_object_truncate(obj); |
4382 | ||
05394f39 | 4383 | args->retained = obj->madv != __I915_MADV_PURGED; |
bb6baf76 | 4384 | |
1d7cfea1 | 4385 | out: |
05394f39 | 4386 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 4387 | unlock: |
3ef94daa | 4388 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 4389 | return ret; |
3ef94daa CW |
4390 | } |
4391 | ||
37e680a1 CW |
4392 | void i915_gem_object_init(struct drm_i915_gem_object *obj, |
4393 | const struct drm_i915_gem_object_ops *ops) | |
0327d6ba | 4394 | { |
35c20a60 | 4395 | INIT_LIST_HEAD(&obj->global_list); |
0327d6ba | 4396 | INIT_LIST_HEAD(&obj->ring_list); |
b25cb2f8 | 4397 | INIT_LIST_HEAD(&obj->obj_exec_link); |
2f633156 | 4398 | INIT_LIST_HEAD(&obj->vma_list); |
493018dc | 4399 | INIT_LIST_HEAD(&obj->batch_pool_list); |
0327d6ba | 4400 | |
37e680a1 CW |
4401 | obj->ops = ops; |
4402 | ||
0327d6ba CW |
4403 | obj->fence_reg = I915_FENCE_REG_NONE; |
4404 | obj->madv = I915_MADV_WILLNEED; | |
0327d6ba CW |
4405 | |
4406 | i915_gem_info_add_obj(obj->base.dev->dev_private, obj->base.size); | |
4407 | } | |
4408 | ||
37e680a1 CW |
4409 | static const struct drm_i915_gem_object_ops i915_gem_object_ops = { |
4410 | .get_pages = i915_gem_object_get_pages_gtt, | |
4411 | .put_pages = i915_gem_object_put_pages_gtt, | |
4412 | }; | |
4413 | ||
05394f39 CW |
4414 | struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev, |
4415 | size_t size) | |
ac52bc56 | 4416 | { |
c397b908 | 4417 | struct drm_i915_gem_object *obj; |
5949eac4 | 4418 | struct address_space *mapping; |
1a240d4d | 4419 | gfp_t mask; |
ac52bc56 | 4420 | |
42dcedd4 | 4421 | obj = i915_gem_object_alloc(dev); |
c397b908 DV |
4422 | if (obj == NULL) |
4423 | return NULL; | |
673a394b | 4424 | |
c397b908 | 4425 | if (drm_gem_object_init(dev, &obj->base, size) != 0) { |
42dcedd4 | 4426 | i915_gem_object_free(obj); |
c397b908 DV |
4427 | return NULL; |
4428 | } | |
673a394b | 4429 | |
bed1ea95 CW |
4430 | mask = GFP_HIGHUSER | __GFP_RECLAIMABLE; |
4431 | if (IS_CRESTLINE(dev) || IS_BROADWATER(dev)) { | |
4432 | /* 965gm cannot relocate objects above 4GiB. */ | |
4433 | mask &= ~__GFP_HIGHMEM; | |
4434 | mask |= __GFP_DMA32; | |
4435 | } | |
4436 | ||
496ad9aa | 4437 | mapping = file_inode(obj->base.filp)->i_mapping; |
bed1ea95 | 4438 | mapping_set_gfp_mask(mapping, mask); |
5949eac4 | 4439 | |
37e680a1 | 4440 | i915_gem_object_init(obj, &i915_gem_object_ops); |
73aa808f | 4441 | |
c397b908 DV |
4442 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; |
4443 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; | |
673a394b | 4444 | |
3d29b842 ED |
4445 | if (HAS_LLC(dev)) { |
4446 | /* On some devices, we can have the GPU use the LLC (the CPU | |
a1871112 EA |
4447 | * cache) for about a 10% performance improvement |
4448 | * compared to uncached. Graphics requests other than | |
4449 | * display scanout are coherent with the CPU in | |
4450 | * accessing this cache. This means in this mode we | |
4451 | * don't need to clflush on the CPU side, and on the | |
4452 | * GPU side we only need to flush internal caches to | |
4453 | * get data visible to the CPU. | |
4454 | * | |
4455 | * However, we maintain the display planes as UC, and so | |
4456 | * need to rebind when first used as such. | |
4457 | */ | |
4458 | obj->cache_level = I915_CACHE_LLC; | |
4459 | } else | |
4460 | obj->cache_level = I915_CACHE_NONE; | |
4461 | ||
d861e338 DV |
4462 | trace_i915_gem_object_create(obj); |
4463 | ||
05394f39 | 4464 | return obj; |
c397b908 DV |
4465 | } |
4466 | ||
340fbd8c CW |
4467 | static bool discard_backing_storage(struct drm_i915_gem_object *obj) |
4468 | { | |
4469 | /* If we are the last user of the backing storage (be it shmemfs | |
4470 | * pages or stolen etc), we know that the pages are going to be | |
4471 | * immediately released. In this case, we can then skip copying | |
4472 | * back the contents from the GPU. | |
4473 | */ | |
4474 | ||
4475 | if (obj->madv != I915_MADV_WILLNEED) | |
4476 | return false; | |
4477 | ||
4478 | if (obj->base.filp == NULL) | |
4479 | return true; | |
4480 | ||
4481 | /* At first glance, this looks racy, but then again so would be | |
4482 | * userspace racing mmap against close. However, the first external | |
4483 | * reference to the filp can only be obtained through the | |
4484 | * i915_gem_mmap_ioctl() which safeguards us against the user | |
4485 | * acquiring such a reference whilst we are in the middle of | |
4486 | * freeing the object. | |
4487 | */ | |
4488 | return atomic_long_read(&obj->base.filp->f_count) == 1; | |
4489 | } | |
4490 | ||
1488fc08 | 4491 | void i915_gem_free_object(struct drm_gem_object *gem_obj) |
673a394b | 4492 | { |
1488fc08 | 4493 | struct drm_i915_gem_object *obj = to_intel_bo(gem_obj); |
05394f39 | 4494 | struct drm_device *dev = obj->base.dev; |
3e31c6c0 | 4495 | struct drm_i915_private *dev_priv = dev->dev_private; |
07fe0b12 | 4496 | struct i915_vma *vma, *next; |
673a394b | 4497 | |
f65c9168 PZ |
4498 | intel_runtime_pm_get(dev_priv); |
4499 | ||
26e12f89 CW |
4500 | trace_i915_gem_object_destroy(obj); |
4501 | ||
07fe0b12 | 4502 | list_for_each_entry_safe(vma, next, &obj->vma_list, vma_link) { |
d7f46fc4 BW |
4503 | int ret; |
4504 | ||
4505 | vma->pin_count = 0; | |
4506 | ret = i915_vma_unbind(vma); | |
07fe0b12 BW |
4507 | if (WARN_ON(ret == -ERESTARTSYS)) { |
4508 | bool was_interruptible; | |
1488fc08 | 4509 | |
07fe0b12 BW |
4510 | was_interruptible = dev_priv->mm.interruptible; |
4511 | dev_priv->mm.interruptible = false; | |
1488fc08 | 4512 | |
07fe0b12 | 4513 | WARN_ON(i915_vma_unbind(vma)); |
1488fc08 | 4514 | |
07fe0b12 BW |
4515 | dev_priv->mm.interruptible = was_interruptible; |
4516 | } | |
1488fc08 CW |
4517 | } |
4518 | ||
1d64ae71 BW |
4519 | /* Stolen objects don't hold a ref, but do hold pin count. Fix that up |
4520 | * before progressing. */ | |
4521 | if (obj->stolen) | |
4522 | i915_gem_object_unpin_pages(obj); | |
4523 | ||
a071fa00 DV |
4524 | WARN_ON(obj->frontbuffer_bits); |
4525 | ||
656bfa3a DV |
4526 | if (obj->pages && obj->madv == I915_MADV_WILLNEED && |
4527 | dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES && | |
4528 | obj->tiling_mode != I915_TILING_NONE) | |
4529 | i915_gem_object_unpin_pages(obj); | |
4530 | ||
401c29f6 BW |
4531 | if (WARN_ON(obj->pages_pin_count)) |
4532 | obj->pages_pin_count = 0; | |
340fbd8c | 4533 | if (discard_backing_storage(obj)) |
5537252b | 4534 | obj->madv = I915_MADV_DONTNEED; |
37e680a1 | 4535 | i915_gem_object_put_pages(obj); |
d8cb5086 | 4536 | i915_gem_object_free_mmap_offset(obj); |
de151cf6 | 4537 | |
9da3da66 CW |
4538 | BUG_ON(obj->pages); |
4539 | ||
2f745ad3 CW |
4540 | if (obj->base.import_attach) |
4541 | drm_prime_gem_destroy(&obj->base, NULL); | |
de151cf6 | 4542 | |
5cc9ed4b CW |
4543 | if (obj->ops->release) |
4544 | obj->ops->release(obj); | |
4545 | ||
05394f39 CW |
4546 | drm_gem_object_release(&obj->base); |
4547 | i915_gem_info_remove_obj(dev_priv, obj->base.size); | |
c397b908 | 4548 | |
05394f39 | 4549 | kfree(obj->bit_17); |
42dcedd4 | 4550 | i915_gem_object_free(obj); |
f65c9168 PZ |
4551 | |
4552 | intel_runtime_pm_put(dev_priv); | |
673a394b EA |
4553 | } |
4554 | ||
fe14d5f4 TU |
4555 | struct i915_vma *i915_gem_obj_to_vma_view(struct drm_i915_gem_object *obj, |
4556 | struct i915_address_space *vm, | |
4557 | const struct i915_ggtt_view *view) | |
e656a6cb DV |
4558 | { |
4559 | struct i915_vma *vma; | |
4560 | list_for_each_entry(vma, &obj->vma_list, vma_link) | |
fe14d5f4 | 4561 | if (vma->vm == vm && vma->ggtt_view.type == view->type) |
e656a6cb DV |
4562 | return vma; |
4563 | ||
4564 | return NULL; | |
4565 | } | |
4566 | ||
2f633156 BW |
4567 | void i915_gem_vma_destroy(struct i915_vma *vma) |
4568 | { | |
b9d06dd9 | 4569 | struct i915_address_space *vm = NULL; |
2f633156 | 4570 | WARN_ON(vma->node.allocated); |
aaa05667 CW |
4571 | |
4572 | /* Keep the vma as a placeholder in the execbuffer reservation lists */ | |
4573 | if (!list_empty(&vma->exec_list)) | |
4574 | return; | |
4575 | ||
b9d06dd9 | 4576 | vm = vma->vm; |
b9d06dd9 | 4577 | |
841cd773 DV |
4578 | if (!i915_is_ggtt(vm)) |
4579 | i915_ppgtt_put(i915_vm_to_ppgtt(vm)); | |
b9d06dd9 | 4580 | |
8b9c2b94 | 4581 | list_del(&vma->vma_link); |
b93dab6e | 4582 | |
2f633156 BW |
4583 | kfree(vma); |
4584 | } | |
4585 | ||
e3efda49 CW |
4586 | static void |
4587 | i915_gem_stop_ringbuffers(struct drm_device *dev) | |
4588 | { | |
4589 | struct drm_i915_private *dev_priv = dev->dev_private; | |
a4872ba6 | 4590 | struct intel_engine_cs *ring; |
e3efda49 CW |
4591 | int i; |
4592 | ||
4593 | for_each_ring(ring, dev_priv, i) | |
a83014d3 | 4594 | dev_priv->gt.stop_ring(ring); |
e3efda49 CW |
4595 | } |
4596 | ||
29105ccc | 4597 | int |
45c5f202 | 4598 | i915_gem_suspend(struct drm_device *dev) |
29105ccc | 4599 | { |
3e31c6c0 | 4600 | struct drm_i915_private *dev_priv = dev->dev_private; |
45c5f202 | 4601 | int ret = 0; |
28dfe52a | 4602 | |
45c5f202 | 4603 | mutex_lock(&dev->struct_mutex); |
b2da9fe5 | 4604 | ret = i915_gpu_idle(dev); |
f7403347 | 4605 | if (ret) |
45c5f202 | 4606 | goto err; |
f7403347 | 4607 | |
b2da9fe5 | 4608 | i915_gem_retire_requests(dev); |
673a394b | 4609 | |
29105ccc | 4610 | /* Under UMS, be paranoid and evict. */ |
a39d7efc | 4611 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) |
6c085a72 | 4612 | i915_gem_evict_everything(dev); |
29105ccc | 4613 | |
e3efda49 | 4614 | i915_gem_stop_ringbuffers(dev); |
45c5f202 CW |
4615 | mutex_unlock(&dev->struct_mutex); |
4616 | ||
737b1506 | 4617 | cancel_delayed_work_sync(&dev_priv->gpu_error.hangcheck_work); |
29105ccc | 4618 | cancel_delayed_work_sync(&dev_priv->mm.retire_work); |
274fa1c1 | 4619 | flush_delayed_work(&dev_priv->mm.idle_work); |
29105ccc | 4620 | |
bdcf120b CW |
4621 | /* Assert that we sucessfully flushed all the work and |
4622 | * reset the GPU back to its idle, low power state. | |
4623 | */ | |
4624 | WARN_ON(dev_priv->mm.busy); | |
4625 | ||
673a394b | 4626 | return 0; |
45c5f202 CW |
4627 | |
4628 | err: | |
4629 | mutex_unlock(&dev->struct_mutex); | |
4630 | return ret; | |
673a394b EA |
4631 | } |
4632 | ||
a4872ba6 | 4633 | int i915_gem_l3_remap(struct intel_engine_cs *ring, int slice) |
b9524a1e | 4634 | { |
c3787e2e | 4635 | struct drm_device *dev = ring->dev; |
3e31c6c0 | 4636 | struct drm_i915_private *dev_priv = dev->dev_private; |
35a85ac6 BW |
4637 | u32 reg_base = GEN7_L3LOG_BASE + (slice * 0x200); |
4638 | u32 *remap_info = dev_priv->l3_parity.remap_info[slice]; | |
c3787e2e | 4639 | int i, ret; |
b9524a1e | 4640 | |
040d2baa | 4641 | if (!HAS_L3_DPF(dev) || !remap_info) |
c3787e2e | 4642 | return 0; |
b9524a1e | 4643 | |
c3787e2e BW |
4644 | ret = intel_ring_begin(ring, GEN7_L3LOG_SIZE / 4 * 3); |
4645 | if (ret) | |
4646 | return ret; | |
b9524a1e | 4647 | |
c3787e2e BW |
4648 | /* |
4649 | * Note: We do not worry about the concurrent register cacheline hang | |
4650 | * here because no other code should access these registers other than | |
4651 | * at initialization time. | |
4652 | */ | |
b9524a1e | 4653 | for (i = 0; i < GEN7_L3LOG_SIZE; i += 4) { |
c3787e2e BW |
4654 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); |
4655 | intel_ring_emit(ring, reg_base + i); | |
4656 | intel_ring_emit(ring, remap_info[i/4]); | |
b9524a1e BW |
4657 | } |
4658 | ||
c3787e2e | 4659 | intel_ring_advance(ring); |
b9524a1e | 4660 | |
c3787e2e | 4661 | return ret; |
b9524a1e BW |
4662 | } |
4663 | ||
f691e2f4 DV |
4664 | void i915_gem_init_swizzling(struct drm_device *dev) |
4665 | { | |
3e31c6c0 | 4666 | struct drm_i915_private *dev_priv = dev->dev_private; |
f691e2f4 | 4667 | |
11782b02 | 4668 | if (INTEL_INFO(dev)->gen < 5 || |
f691e2f4 DV |
4669 | dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE) |
4670 | return; | |
4671 | ||
4672 | I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) | | |
4673 | DISP_TILE_SURFACE_SWIZZLING); | |
4674 | ||
11782b02 DV |
4675 | if (IS_GEN5(dev)) |
4676 | return; | |
4677 | ||
f691e2f4 DV |
4678 | I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_SWZCTL); |
4679 | if (IS_GEN6(dev)) | |
6b26c86d | 4680 | I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB)); |
8782e26c | 4681 | else if (IS_GEN7(dev)) |
6b26c86d | 4682 | I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB)); |
31a5336e BW |
4683 | else if (IS_GEN8(dev)) |
4684 | I915_WRITE(GAMTARBMODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_BDW)); | |
8782e26c BW |
4685 | else |
4686 | BUG(); | |
f691e2f4 | 4687 | } |
e21af88d | 4688 | |
67b1b571 CW |
4689 | static bool |
4690 | intel_enable_blt(struct drm_device *dev) | |
4691 | { | |
4692 | if (!HAS_BLT(dev)) | |
4693 | return false; | |
4694 | ||
4695 | /* The blitter was dysfunctional on early prototypes */ | |
4696 | if (IS_GEN6(dev) && dev->pdev->revision < 8) { | |
4697 | DRM_INFO("BLT not supported on this pre-production hardware;" | |
4698 | " graphics performance will be degraded.\n"); | |
4699 | return false; | |
4700 | } | |
4701 | ||
4702 | return true; | |
4703 | } | |
4704 | ||
81e7f200 VS |
4705 | static void init_unused_ring(struct drm_device *dev, u32 base) |
4706 | { | |
4707 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4708 | ||
4709 | I915_WRITE(RING_CTL(base), 0); | |
4710 | I915_WRITE(RING_HEAD(base), 0); | |
4711 | I915_WRITE(RING_TAIL(base), 0); | |
4712 | I915_WRITE(RING_START(base), 0); | |
4713 | } | |
4714 | ||
4715 | static void init_unused_rings(struct drm_device *dev) | |
4716 | { | |
4717 | if (IS_I830(dev)) { | |
4718 | init_unused_ring(dev, PRB1_BASE); | |
4719 | init_unused_ring(dev, SRB0_BASE); | |
4720 | init_unused_ring(dev, SRB1_BASE); | |
4721 | init_unused_ring(dev, SRB2_BASE); | |
4722 | init_unused_ring(dev, SRB3_BASE); | |
4723 | } else if (IS_GEN2(dev)) { | |
4724 | init_unused_ring(dev, SRB0_BASE); | |
4725 | init_unused_ring(dev, SRB1_BASE); | |
4726 | } else if (IS_GEN3(dev)) { | |
4727 | init_unused_ring(dev, PRB1_BASE); | |
4728 | init_unused_ring(dev, PRB2_BASE); | |
4729 | } | |
4730 | } | |
4731 | ||
a83014d3 | 4732 | int i915_gem_init_rings(struct drm_device *dev) |
8187a2b7 | 4733 | { |
4fc7c971 | 4734 | struct drm_i915_private *dev_priv = dev->dev_private; |
8187a2b7 | 4735 | int ret; |
68f95ba9 | 4736 | |
5c1143bb | 4737 | ret = intel_init_render_ring_buffer(dev); |
68f95ba9 | 4738 | if (ret) |
b6913e4b | 4739 | return ret; |
68f95ba9 CW |
4740 | |
4741 | if (HAS_BSD(dev)) { | |
5c1143bb | 4742 | ret = intel_init_bsd_ring_buffer(dev); |
68f95ba9 CW |
4743 | if (ret) |
4744 | goto cleanup_render_ring; | |
d1b851fc | 4745 | } |
68f95ba9 | 4746 | |
67b1b571 | 4747 | if (intel_enable_blt(dev)) { |
549f7365 CW |
4748 | ret = intel_init_blt_ring_buffer(dev); |
4749 | if (ret) | |
4750 | goto cleanup_bsd_ring; | |
4751 | } | |
4752 | ||
9a8a2213 BW |
4753 | if (HAS_VEBOX(dev)) { |
4754 | ret = intel_init_vebox_ring_buffer(dev); | |
4755 | if (ret) | |
4756 | goto cleanup_blt_ring; | |
4757 | } | |
4758 | ||
845f74a7 ZY |
4759 | if (HAS_BSD2(dev)) { |
4760 | ret = intel_init_bsd2_ring_buffer(dev); | |
4761 | if (ret) | |
4762 | goto cleanup_vebox_ring; | |
4763 | } | |
9a8a2213 | 4764 | |
99433931 | 4765 | ret = i915_gem_set_seqno(dev, ((u32)~0 - 0x1000)); |
4fc7c971 | 4766 | if (ret) |
845f74a7 | 4767 | goto cleanup_bsd2_ring; |
4fc7c971 BW |
4768 | |
4769 | return 0; | |
4770 | ||
845f74a7 ZY |
4771 | cleanup_bsd2_ring: |
4772 | intel_cleanup_ring_buffer(&dev_priv->ring[VCS2]); | |
9a8a2213 BW |
4773 | cleanup_vebox_ring: |
4774 | intel_cleanup_ring_buffer(&dev_priv->ring[VECS]); | |
4fc7c971 BW |
4775 | cleanup_blt_ring: |
4776 | intel_cleanup_ring_buffer(&dev_priv->ring[BCS]); | |
4777 | cleanup_bsd_ring: | |
4778 | intel_cleanup_ring_buffer(&dev_priv->ring[VCS]); | |
4779 | cleanup_render_ring: | |
4780 | intel_cleanup_ring_buffer(&dev_priv->ring[RCS]); | |
4781 | ||
4782 | return ret; | |
4783 | } | |
4784 | ||
4785 | int | |
4786 | i915_gem_init_hw(struct drm_device *dev) | |
4787 | { | |
3e31c6c0 | 4788 | struct drm_i915_private *dev_priv = dev->dev_private; |
35a57ffb | 4789 | struct intel_engine_cs *ring; |
35a85ac6 | 4790 | int ret, i; |
4fc7c971 BW |
4791 | |
4792 | if (INTEL_INFO(dev)->gen < 6 && !intel_enable_gtt()) | |
4793 | return -EIO; | |
4794 | ||
59124506 | 4795 | if (dev_priv->ellc_size) |
05e21cc4 | 4796 | I915_WRITE(HSW_IDICR, I915_READ(HSW_IDICR) | IDIHASHMSK(0xf)); |
4fc7c971 | 4797 | |
0bf21347 VS |
4798 | if (IS_HASWELL(dev)) |
4799 | I915_WRITE(MI_PREDICATE_RESULT_2, IS_HSW_GT3(dev) ? | |
4800 | LOWER_SLICE_ENABLED : LOWER_SLICE_DISABLED); | |
9435373e | 4801 | |
88a2b2a3 | 4802 | if (HAS_PCH_NOP(dev)) { |
6ba844b0 DV |
4803 | if (IS_IVYBRIDGE(dev)) { |
4804 | u32 temp = I915_READ(GEN7_MSG_CTL); | |
4805 | temp &= ~(WAIT_FOR_PCH_FLR_ACK | WAIT_FOR_PCH_RESET_ACK); | |
4806 | I915_WRITE(GEN7_MSG_CTL, temp); | |
4807 | } else if (INTEL_INFO(dev)->gen >= 7) { | |
4808 | u32 temp = I915_READ(HSW_NDE_RSTWRN_OPT); | |
4809 | temp &= ~RESET_PCH_HANDSHAKE_ENABLE; | |
4810 | I915_WRITE(HSW_NDE_RSTWRN_OPT, temp); | |
4811 | } | |
88a2b2a3 BW |
4812 | } |
4813 | ||
4fc7c971 BW |
4814 | i915_gem_init_swizzling(dev); |
4815 | ||
d5abdfda DV |
4816 | /* |
4817 | * At least 830 can leave some of the unused rings | |
4818 | * "active" (ie. head != tail) after resume which | |
4819 | * will prevent c3 entry. Makes sure all unused rings | |
4820 | * are totally idle. | |
4821 | */ | |
4822 | init_unused_rings(dev); | |
4823 | ||
35a57ffb DV |
4824 | for_each_ring(ring, dev_priv, i) { |
4825 | ret = ring->init_hw(ring); | |
4826 | if (ret) | |
4827 | return ret; | |
4828 | } | |
99433931 | 4829 | |
c3787e2e BW |
4830 | for (i = 0; i < NUM_L3_SLICES(dev); i++) |
4831 | i915_gem_l3_remap(&dev_priv->ring[RCS], i); | |
4832 | ||
f48a0165 | 4833 | ret = i915_ppgtt_init_hw(dev); |
60990320 | 4834 | if (ret && ret != -EIO) { |
f48a0165 | 4835 | DRM_ERROR("PPGTT enable failed %d\n", ret); |
60990320 | 4836 | i915_gem_cleanup_ringbuffer(dev); |
82460d97 DV |
4837 | } |
4838 | ||
f48a0165 | 4839 | ret = i915_gem_context_enable(dev_priv); |
82460d97 | 4840 | if (ret && ret != -EIO) { |
f48a0165 | 4841 | DRM_ERROR("Context enable failed %d\n", ret); |
82460d97 | 4842 | i915_gem_cleanup_ringbuffer(dev); |
f48a0165 DW |
4843 | |
4844 | return ret; | |
b7c36d25 | 4845 | } |
e21af88d | 4846 | |
2fa48d8d | 4847 | return ret; |
8187a2b7 ZN |
4848 | } |
4849 | ||
1070a42b CW |
4850 | int i915_gem_init(struct drm_device *dev) |
4851 | { | |
4852 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1070a42b CW |
4853 | int ret; |
4854 | ||
127f1003 OM |
4855 | i915.enable_execlists = intel_sanitize_enable_execlists(dev, |
4856 | i915.enable_execlists); | |
4857 | ||
1070a42b | 4858 | mutex_lock(&dev->struct_mutex); |
d62b4892 JB |
4859 | |
4860 | if (IS_VALLEYVIEW(dev)) { | |
4861 | /* VLVA0 (potential hack), BIOS isn't actually waking us */ | |
981a5aea ID |
4862 | I915_WRITE(VLV_GTLC_WAKE_CTRL, VLV_GTLC_ALLOWWAKEREQ); |
4863 | if (wait_for((I915_READ(VLV_GTLC_PW_STATUS) & | |
4864 | VLV_GTLC_ALLOWWAKEACK), 10)) | |
d62b4892 JB |
4865 | DRM_DEBUG_DRIVER("allow wake ack timed out\n"); |
4866 | } | |
4867 | ||
a83014d3 OM |
4868 | if (!i915.enable_execlists) { |
4869 | dev_priv->gt.do_execbuf = i915_gem_ringbuffer_submission; | |
4870 | dev_priv->gt.init_rings = i915_gem_init_rings; | |
4871 | dev_priv->gt.cleanup_ring = intel_cleanup_ring_buffer; | |
4872 | dev_priv->gt.stop_ring = intel_stop_ring_buffer; | |
454afebd OM |
4873 | } else { |
4874 | dev_priv->gt.do_execbuf = intel_execlists_submission; | |
4875 | dev_priv->gt.init_rings = intel_logical_rings_init; | |
4876 | dev_priv->gt.cleanup_ring = intel_logical_ring_cleanup; | |
4877 | dev_priv->gt.stop_ring = intel_logical_ring_stop; | |
a83014d3 OM |
4878 | } |
4879 | ||
6c5566a8 | 4880 | ret = i915_gem_init_userptr(dev); |
7bcc3777 JN |
4881 | if (ret) |
4882 | goto out_unlock; | |
6c5566a8 | 4883 | |
d7e5008f | 4884 | i915_gem_init_global_gtt(dev); |
d62b4892 | 4885 | |
2fa48d8d | 4886 | ret = i915_gem_context_init(dev); |
7bcc3777 JN |
4887 | if (ret) |
4888 | goto out_unlock; | |
2fa48d8d | 4889 | |
35a57ffb DV |
4890 | ret = dev_priv->gt.init_rings(dev); |
4891 | if (ret) | |
7bcc3777 | 4892 | goto out_unlock; |
2fa48d8d | 4893 | |
1070a42b | 4894 | ret = i915_gem_init_hw(dev); |
60990320 CW |
4895 | if (ret == -EIO) { |
4896 | /* Allow ring initialisation to fail by marking the GPU as | |
4897 | * wedged. But we only want to do this where the GPU is angry, | |
4898 | * for all other failure, such as an allocation failure, bail. | |
4899 | */ | |
4900 | DRM_ERROR("Failed to initialize GPU, declaring it wedged\n"); | |
4901 | atomic_set_mask(I915_WEDGED, &dev_priv->gpu_error.reset_counter); | |
4902 | ret = 0; | |
1070a42b | 4903 | } |
7bcc3777 JN |
4904 | |
4905 | out_unlock: | |
60990320 | 4906 | mutex_unlock(&dev->struct_mutex); |
1070a42b | 4907 | |
60990320 | 4908 | return ret; |
1070a42b CW |
4909 | } |
4910 | ||
8187a2b7 ZN |
4911 | void |
4912 | i915_gem_cleanup_ringbuffer(struct drm_device *dev) | |
4913 | { | |
3e31c6c0 | 4914 | struct drm_i915_private *dev_priv = dev->dev_private; |
a4872ba6 | 4915 | struct intel_engine_cs *ring; |
1ec14ad3 | 4916 | int i; |
8187a2b7 | 4917 | |
b4519513 | 4918 | for_each_ring(ring, dev_priv, i) |
a83014d3 | 4919 | dev_priv->gt.cleanup_ring(ring); |
8187a2b7 ZN |
4920 | } |
4921 | ||
64193406 | 4922 | static void |
a4872ba6 | 4923 | init_ring_lists(struct intel_engine_cs *ring) |
64193406 CW |
4924 | { |
4925 | INIT_LIST_HEAD(&ring->active_list); | |
4926 | INIT_LIST_HEAD(&ring->request_list); | |
64193406 CW |
4927 | } |
4928 | ||
7e0d96bc BW |
4929 | void i915_init_vm(struct drm_i915_private *dev_priv, |
4930 | struct i915_address_space *vm) | |
fc8c067e | 4931 | { |
7e0d96bc BW |
4932 | if (!i915_is_ggtt(vm)) |
4933 | drm_mm_init(&vm->mm, vm->start, vm->total); | |
fc8c067e BW |
4934 | vm->dev = dev_priv->dev; |
4935 | INIT_LIST_HEAD(&vm->active_list); | |
4936 | INIT_LIST_HEAD(&vm->inactive_list); | |
4937 | INIT_LIST_HEAD(&vm->global_link); | |
f72d21ed | 4938 | list_add_tail(&vm->global_link, &dev_priv->vm_list); |
fc8c067e BW |
4939 | } |
4940 | ||
673a394b EA |
4941 | void |
4942 | i915_gem_load(struct drm_device *dev) | |
4943 | { | |
3e31c6c0 | 4944 | struct drm_i915_private *dev_priv = dev->dev_private; |
42dcedd4 CW |
4945 | int i; |
4946 | ||
4947 | dev_priv->slab = | |
4948 | kmem_cache_create("i915_gem_object", | |
4949 | sizeof(struct drm_i915_gem_object), 0, | |
4950 | SLAB_HWCACHE_ALIGN, | |
4951 | NULL); | |
673a394b | 4952 | |
fc8c067e BW |
4953 | INIT_LIST_HEAD(&dev_priv->vm_list); |
4954 | i915_init_vm(dev_priv, &dev_priv->gtt.base); | |
4955 | ||
a33afea5 | 4956 | INIT_LIST_HEAD(&dev_priv->context_list); |
6c085a72 CW |
4957 | INIT_LIST_HEAD(&dev_priv->mm.unbound_list); |
4958 | INIT_LIST_HEAD(&dev_priv->mm.bound_list); | |
a09ba7fa | 4959 | INIT_LIST_HEAD(&dev_priv->mm.fence_list); |
1ec14ad3 CW |
4960 | for (i = 0; i < I915_NUM_RINGS; i++) |
4961 | init_ring_lists(&dev_priv->ring[i]); | |
4b9de737 | 4962 | for (i = 0; i < I915_MAX_NUM_FENCES; i++) |
007cc8ac | 4963 | INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list); |
673a394b EA |
4964 | INIT_DELAYED_WORK(&dev_priv->mm.retire_work, |
4965 | i915_gem_retire_work_handler); | |
b29c19b6 CW |
4966 | INIT_DELAYED_WORK(&dev_priv->mm.idle_work, |
4967 | i915_gem_idle_work_handler); | |
1f83fee0 | 4968 | init_waitqueue_head(&dev_priv->gpu_error.reset_queue); |
31169714 | 4969 | |
94400120 | 4970 | /* On GEN3 we really need to make sure the ARB C3 LP bit is set */ |
dbb42748 | 4971 | if (!drm_core_check_feature(dev, DRIVER_MODESET) && IS_GEN3(dev)) { |
50743298 DV |
4972 | I915_WRITE(MI_ARB_STATE, |
4973 | _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE)); | |
94400120 DA |
4974 | } |
4975 | ||
72bfa19c CW |
4976 | dev_priv->relative_constants_mode = I915_EXEC_CONSTANTS_REL_GENERAL; |
4977 | ||
de151cf6 | 4978 | /* Old X drivers will take 0-2 for front, back, depth buffers */ |
b397c836 EA |
4979 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) |
4980 | dev_priv->fence_reg_start = 3; | |
de151cf6 | 4981 | |
42b5aeab VS |
4982 | if (INTEL_INFO(dev)->gen >= 7 && !IS_VALLEYVIEW(dev)) |
4983 | dev_priv->num_fence_regs = 32; | |
4984 | else if (INTEL_INFO(dev)->gen >= 4 || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) | |
de151cf6 JB |
4985 | dev_priv->num_fence_regs = 16; |
4986 | else | |
4987 | dev_priv->num_fence_regs = 8; | |
4988 | ||
b5aa8a0f | 4989 | /* Initialize fence registers to zero */ |
19b2dbde CW |
4990 | INIT_LIST_HEAD(&dev_priv->mm.fence_list); |
4991 | i915_gem_restore_fences(dev); | |
10ed13e4 | 4992 | |
673a394b | 4993 | i915_gem_detect_bit_6_swizzle(dev); |
6b95a207 | 4994 | init_waitqueue_head(&dev_priv->pending_flip_queue); |
17250b71 | 4995 | |
ce453d81 CW |
4996 | dev_priv->mm.interruptible = true; |
4997 | ||
ceabbba5 CW |
4998 | dev_priv->mm.shrinker.scan_objects = i915_gem_shrinker_scan; |
4999 | dev_priv->mm.shrinker.count_objects = i915_gem_shrinker_count; | |
5000 | dev_priv->mm.shrinker.seeks = DEFAULT_SEEKS; | |
5001 | register_shrinker(&dev_priv->mm.shrinker); | |
2cfcd32a CW |
5002 | |
5003 | dev_priv->mm.oom_notifier.notifier_call = i915_gem_shrinker_oom; | |
5004 | register_oom_notifier(&dev_priv->mm.oom_notifier); | |
f99d7069 | 5005 | |
78a42377 BV |
5006 | i915_gem_batch_pool_init(dev, &dev_priv->mm.batch_pool); |
5007 | ||
f99d7069 | 5008 | mutex_init(&dev_priv->fb_tracking.lock); |
673a394b | 5009 | } |
71acb5eb | 5010 | |
f787a5f5 | 5011 | void i915_gem_release(struct drm_device *dev, struct drm_file *file) |
b962442e | 5012 | { |
f787a5f5 | 5013 | struct drm_i915_file_private *file_priv = file->driver_priv; |
b962442e | 5014 | |
b29c19b6 CW |
5015 | cancel_delayed_work_sync(&file_priv->mm.idle_work); |
5016 | ||
b962442e EA |
5017 | /* Clean up our request list when the client is going away, so that |
5018 | * later retire_requests won't dereference our soon-to-be-gone | |
5019 | * file_priv. | |
5020 | */ | |
1c25595f | 5021 | spin_lock(&file_priv->mm.lock); |
f787a5f5 CW |
5022 | while (!list_empty(&file_priv->mm.request_list)) { |
5023 | struct drm_i915_gem_request *request; | |
5024 | ||
5025 | request = list_first_entry(&file_priv->mm.request_list, | |
5026 | struct drm_i915_gem_request, | |
5027 | client_list); | |
5028 | list_del(&request->client_list); | |
5029 | request->file_priv = NULL; | |
5030 | } | |
1c25595f | 5031 | spin_unlock(&file_priv->mm.lock); |
b962442e | 5032 | } |
31169714 | 5033 | |
b29c19b6 CW |
5034 | static void |
5035 | i915_gem_file_idle_work_handler(struct work_struct *work) | |
5036 | { | |
5037 | struct drm_i915_file_private *file_priv = | |
5038 | container_of(work, typeof(*file_priv), mm.idle_work.work); | |
5039 | ||
5040 | atomic_set(&file_priv->rps_wait_boost, false); | |
5041 | } | |
5042 | ||
5043 | int i915_gem_open(struct drm_device *dev, struct drm_file *file) | |
5044 | { | |
5045 | struct drm_i915_file_private *file_priv; | |
e422b888 | 5046 | int ret; |
b29c19b6 CW |
5047 | |
5048 | DRM_DEBUG_DRIVER("\n"); | |
5049 | ||
5050 | file_priv = kzalloc(sizeof(*file_priv), GFP_KERNEL); | |
5051 | if (!file_priv) | |
5052 | return -ENOMEM; | |
5053 | ||
5054 | file->driver_priv = file_priv; | |
5055 | file_priv->dev_priv = dev->dev_private; | |
ab0e7ff9 | 5056 | file_priv->file = file; |
b29c19b6 CW |
5057 | |
5058 | spin_lock_init(&file_priv->mm.lock); | |
5059 | INIT_LIST_HEAD(&file_priv->mm.request_list); | |
5060 | INIT_DELAYED_WORK(&file_priv->mm.idle_work, | |
5061 | i915_gem_file_idle_work_handler); | |
5062 | ||
e422b888 BW |
5063 | ret = i915_gem_context_open(dev, file); |
5064 | if (ret) | |
5065 | kfree(file_priv); | |
b29c19b6 | 5066 | |
e422b888 | 5067 | return ret; |
b29c19b6 CW |
5068 | } |
5069 | ||
b680c37a DV |
5070 | /** |
5071 | * i915_gem_track_fb - update frontbuffer tracking | |
5072 | * old: current GEM buffer for the frontbuffer slots | |
5073 | * new: new GEM buffer for the frontbuffer slots | |
5074 | * frontbuffer_bits: bitmask of frontbuffer slots | |
5075 | * | |
5076 | * This updates the frontbuffer tracking bits @frontbuffer_bits by clearing them | |
5077 | * from @old and setting them in @new. Both @old and @new can be NULL. | |
5078 | */ | |
a071fa00 DV |
5079 | void i915_gem_track_fb(struct drm_i915_gem_object *old, |
5080 | struct drm_i915_gem_object *new, | |
5081 | unsigned frontbuffer_bits) | |
5082 | { | |
5083 | if (old) { | |
5084 | WARN_ON(!mutex_is_locked(&old->base.dev->struct_mutex)); | |
5085 | WARN_ON(!(old->frontbuffer_bits & frontbuffer_bits)); | |
5086 | old->frontbuffer_bits &= ~frontbuffer_bits; | |
5087 | } | |
5088 | ||
5089 | if (new) { | |
5090 | WARN_ON(!mutex_is_locked(&new->base.dev->struct_mutex)); | |
5091 | WARN_ON(new->frontbuffer_bits & frontbuffer_bits); | |
5092 | new->frontbuffer_bits |= frontbuffer_bits; | |
5093 | } | |
5094 | } | |
5095 | ||
5774506f CW |
5096 | static bool mutex_is_locked_by(struct mutex *mutex, struct task_struct *task) |
5097 | { | |
5098 | if (!mutex_is_locked(mutex)) | |
5099 | return false; | |
5100 | ||
a5094051 | 5101 | #if defined(CONFIG_SMP) || defined(CONFIG_DEBUG_MUTEXES) |
5774506f CW |
5102 | return mutex->owner == task; |
5103 | #else | |
5104 | /* Since UP may be pre-empted, we cannot assume that we own the lock */ | |
5105 | return false; | |
5106 | #endif | |
5107 | } | |
5108 | ||
b453c4db CW |
5109 | static bool i915_gem_shrinker_lock(struct drm_device *dev, bool *unlock) |
5110 | { | |
5111 | if (!mutex_trylock(&dev->struct_mutex)) { | |
5112 | if (!mutex_is_locked_by(&dev->struct_mutex, current)) | |
5113 | return false; | |
5114 | ||
5115 | if (to_i915(dev)->mm.shrinker_no_lock_stealing) | |
5116 | return false; | |
5117 | ||
5118 | *unlock = false; | |
5119 | } else | |
5120 | *unlock = true; | |
5121 | ||
5122 | return true; | |
5123 | } | |
5124 | ||
ceabbba5 CW |
5125 | static int num_vma_bound(struct drm_i915_gem_object *obj) |
5126 | { | |
5127 | struct i915_vma *vma; | |
5128 | int count = 0; | |
5129 | ||
5130 | list_for_each_entry(vma, &obj->vma_list, vma_link) | |
5131 | if (drm_mm_node_allocated(&vma->node)) | |
5132 | count++; | |
5133 | ||
5134 | return count; | |
5135 | } | |
5136 | ||
7dc19d5a | 5137 | static unsigned long |
ceabbba5 | 5138 | i915_gem_shrinker_count(struct shrinker *shrinker, struct shrink_control *sc) |
31169714 | 5139 | { |
17250b71 | 5140 | struct drm_i915_private *dev_priv = |
ceabbba5 | 5141 | container_of(shrinker, struct drm_i915_private, mm.shrinker); |
17250b71 | 5142 | struct drm_device *dev = dev_priv->dev; |
6c085a72 | 5143 | struct drm_i915_gem_object *obj; |
7dc19d5a | 5144 | unsigned long count; |
b453c4db | 5145 | bool unlock; |
17250b71 | 5146 | |
b453c4db CW |
5147 | if (!i915_gem_shrinker_lock(dev, &unlock)) |
5148 | return 0; | |
31169714 | 5149 | |
7dc19d5a | 5150 | count = 0; |
35c20a60 | 5151 | list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) |
a5570178 | 5152 | if (obj->pages_pin_count == 0) |
7dc19d5a | 5153 | count += obj->base.size >> PAGE_SHIFT; |
fcb4a578 BW |
5154 | |
5155 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) { | |
ceabbba5 CW |
5156 | if (!i915_gem_obj_is_pinned(obj) && |
5157 | obj->pages_pin_count == num_vma_bound(obj)) | |
7dc19d5a | 5158 | count += obj->base.size >> PAGE_SHIFT; |
fcb4a578 | 5159 | } |
17250b71 | 5160 | |
5774506f CW |
5161 | if (unlock) |
5162 | mutex_unlock(&dev->struct_mutex); | |
d9973b43 | 5163 | |
7dc19d5a | 5164 | return count; |
31169714 | 5165 | } |
a70a3148 BW |
5166 | |
5167 | /* All the new VM stuff */ | |
fe14d5f4 TU |
5168 | unsigned long i915_gem_obj_offset_view(struct drm_i915_gem_object *o, |
5169 | struct i915_address_space *vm, | |
5170 | enum i915_ggtt_view_type view) | |
a70a3148 BW |
5171 | { |
5172 | struct drm_i915_private *dev_priv = o->base.dev->dev_private; | |
5173 | struct i915_vma *vma; | |
5174 | ||
896ab1a5 | 5175 | WARN_ON(vm == &dev_priv->mm.aliasing_ppgtt->base); |
a70a3148 | 5176 | |
a70a3148 | 5177 | list_for_each_entry(vma, &o->vma_list, vma_link) { |
fe14d5f4 | 5178 | if (vma->vm == vm && vma->ggtt_view.type == view) |
a70a3148 BW |
5179 | return vma->node.start; |
5180 | ||
5181 | } | |
f25748ea DV |
5182 | WARN(1, "%s vma for this object not found.\n", |
5183 | i915_is_ggtt(vm) ? "global" : "ppgtt"); | |
a70a3148 BW |
5184 | return -1; |
5185 | } | |
5186 | ||
fe14d5f4 TU |
5187 | bool i915_gem_obj_bound_view(struct drm_i915_gem_object *o, |
5188 | struct i915_address_space *vm, | |
5189 | enum i915_ggtt_view_type view) | |
a70a3148 BW |
5190 | { |
5191 | struct i915_vma *vma; | |
5192 | ||
5193 | list_for_each_entry(vma, &o->vma_list, vma_link) | |
fe14d5f4 TU |
5194 | if (vma->vm == vm && |
5195 | vma->ggtt_view.type == view && | |
5196 | drm_mm_node_allocated(&vma->node)) | |
a70a3148 BW |
5197 | return true; |
5198 | ||
5199 | return false; | |
5200 | } | |
5201 | ||
5202 | bool i915_gem_obj_bound_any(struct drm_i915_gem_object *o) | |
5203 | { | |
5a1d5eb0 | 5204 | struct i915_vma *vma; |
a70a3148 | 5205 | |
5a1d5eb0 CW |
5206 | list_for_each_entry(vma, &o->vma_list, vma_link) |
5207 | if (drm_mm_node_allocated(&vma->node)) | |
a70a3148 BW |
5208 | return true; |
5209 | ||
5210 | return false; | |
5211 | } | |
5212 | ||
5213 | unsigned long i915_gem_obj_size(struct drm_i915_gem_object *o, | |
5214 | struct i915_address_space *vm) | |
5215 | { | |
5216 | struct drm_i915_private *dev_priv = o->base.dev->dev_private; | |
5217 | struct i915_vma *vma; | |
5218 | ||
896ab1a5 | 5219 | WARN_ON(vm == &dev_priv->mm.aliasing_ppgtt->base); |
a70a3148 BW |
5220 | |
5221 | BUG_ON(list_empty(&o->vma_list)); | |
5222 | ||
5223 | list_for_each_entry(vma, &o->vma_list, vma_link) | |
5224 | if (vma->vm == vm) | |
5225 | return vma->node.size; | |
5226 | ||
5227 | return 0; | |
5228 | } | |
5229 | ||
7dc19d5a | 5230 | static unsigned long |
ceabbba5 | 5231 | i915_gem_shrinker_scan(struct shrinker *shrinker, struct shrink_control *sc) |
7dc19d5a DC |
5232 | { |
5233 | struct drm_i915_private *dev_priv = | |
ceabbba5 | 5234 | container_of(shrinker, struct drm_i915_private, mm.shrinker); |
7dc19d5a | 5235 | struct drm_device *dev = dev_priv->dev; |
7dc19d5a | 5236 | unsigned long freed; |
b453c4db | 5237 | bool unlock; |
7dc19d5a | 5238 | |
b453c4db CW |
5239 | if (!i915_gem_shrinker_lock(dev, &unlock)) |
5240 | return SHRINK_STOP; | |
7dc19d5a | 5241 | |
21ab4e74 CW |
5242 | freed = i915_gem_shrink(dev_priv, |
5243 | sc->nr_to_scan, | |
5244 | I915_SHRINK_BOUND | | |
5245 | I915_SHRINK_UNBOUND | | |
5246 | I915_SHRINK_PURGEABLE); | |
d9973b43 | 5247 | if (freed < sc->nr_to_scan) |
21ab4e74 CW |
5248 | freed += i915_gem_shrink(dev_priv, |
5249 | sc->nr_to_scan - freed, | |
5250 | I915_SHRINK_BOUND | | |
5251 | I915_SHRINK_UNBOUND); | |
7dc19d5a DC |
5252 | if (unlock) |
5253 | mutex_unlock(&dev->struct_mutex); | |
d9973b43 | 5254 | |
7dc19d5a DC |
5255 | return freed; |
5256 | } | |
5c2abbea | 5257 | |
2cfcd32a CW |
5258 | static int |
5259 | i915_gem_shrinker_oom(struct notifier_block *nb, unsigned long event, void *ptr) | |
5260 | { | |
5261 | struct drm_i915_private *dev_priv = | |
5262 | container_of(nb, struct drm_i915_private, mm.oom_notifier); | |
5263 | struct drm_device *dev = dev_priv->dev; | |
5264 | struct drm_i915_gem_object *obj; | |
5265 | unsigned long timeout = msecs_to_jiffies(5000) + 1; | |
005445c5 | 5266 | unsigned long pinned, bound, unbound, freed_pages; |
2cfcd32a CW |
5267 | bool was_interruptible; |
5268 | bool unlock; | |
5269 | ||
a1db2fa7 | 5270 | while (!i915_gem_shrinker_lock(dev, &unlock) && --timeout) { |
2cfcd32a | 5271 | schedule_timeout_killable(1); |
a1db2fa7 CW |
5272 | if (fatal_signal_pending(current)) |
5273 | return NOTIFY_DONE; | |
5274 | } | |
2cfcd32a CW |
5275 | if (timeout == 0) { |
5276 | pr_err("Unable to purge GPU memory due lock contention.\n"); | |
5277 | return NOTIFY_DONE; | |
5278 | } | |
5279 | ||
5280 | was_interruptible = dev_priv->mm.interruptible; | |
5281 | dev_priv->mm.interruptible = false; | |
5282 | ||
005445c5 | 5283 | freed_pages = i915_gem_shrink_all(dev_priv); |
2cfcd32a CW |
5284 | |
5285 | dev_priv->mm.interruptible = was_interruptible; | |
5286 | ||
5287 | /* Because we may be allocating inside our own driver, we cannot | |
5288 | * assert that there are no objects with pinned pages that are not | |
5289 | * being pointed to by hardware. | |
5290 | */ | |
5291 | unbound = bound = pinned = 0; | |
5292 | list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) { | |
5293 | if (!obj->base.filp) /* not backed by a freeable object */ | |
5294 | continue; | |
5295 | ||
5296 | if (obj->pages_pin_count) | |
5297 | pinned += obj->base.size; | |
5298 | else | |
5299 | unbound += obj->base.size; | |
5300 | } | |
5301 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) { | |
5302 | if (!obj->base.filp) | |
5303 | continue; | |
5304 | ||
5305 | if (obj->pages_pin_count) | |
5306 | pinned += obj->base.size; | |
5307 | else | |
5308 | bound += obj->base.size; | |
5309 | } | |
5310 | ||
5311 | if (unlock) | |
5312 | mutex_unlock(&dev->struct_mutex); | |
5313 | ||
bb9059d3 CW |
5314 | if (freed_pages || unbound || bound) |
5315 | pr_info("Purging GPU memory, %lu bytes freed, %lu bytes still pinned.\n", | |
5316 | freed_pages << PAGE_SHIFT, pinned); | |
2cfcd32a CW |
5317 | if (unbound || bound) |
5318 | pr_err("%lu and %lu bytes still available in the " | |
5319 | "bound and unbound GPU page lists.\n", | |
5320 | bound, unbound); | |
5321 | ||
005445c5 | 5322 | *(unsigned long *)ptr += freed_pages; |
2cfcd32a CW |
5323 | return NOTIFY_DONE; |
5324 | } | |
5325 | ||
5c2abbea BW |
5326 | struct i915_vma *i915_gem_obj_to_ggtt(struct drm_i915_gem_object *obj) |
5327 | { | |
f7635669 | 5328 | struct i915_address_space *ggtt = i915_obj_to_ggtt(obj); |
5c2abbea BW |
5329 | struct i915_vma *vma; |
5330 | ||
fe14d5f4 TU |
5331 | list_for_each_entry(vma, &obj->vma_list, vma_link) |
5332 | if (vma->vm == ggtt && | |
5333 | vma->ggtt_view.type == I915_GGTT_VIEW_NORMAL) | |
f7635669 | 5334 | return vma; |
5c2abbea | 5335 | |
f7635669 | 5336 | return NULL; |
5c2abbea | 5337 | } |