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Commit | Line | Data |
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673a394b EA |
1 | /* |
2 | * Copyright © 2008 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | * | |
26 | */ | |
27 | ||
28 | #include "drmP.h" | |
29 | #include "drm.h" | |
30 | #include "i915_drm.h" | |
31 | #include "i915_drv.h" | |
1c5d22f7 | 32 | #include "i915_trace.h" |
652c393a | 33 | #include "intel_drv.h" |
5949eac4 | 34 | #include <linux/shmem_fs.h> |
5a0e3ad6 | 35 | #include <linux/slab.h> |
673a394b | 36 | #include <linux/swap.h> |
79e53945 | 37 | #include <linux/pci.h> |
673a394b | 38 | |
88241785 | 39 | static __must_check int i915_gem_object_flush_gpu_write_domain(struct drm_i915_gem_object *obj); |
05394f39 CW |
40 | static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj); |
41 | static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj); | |
88241785 CW |
42 | static __must_check int i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, |
43 | bool write); | |
44 | static __must_check int i915_gem_object_set_cpu_read_domain_range(struct drm_i915_gem_object *obj, | |
45 | uint64_t offset, | |
46 | uint64_t size); | |
05394f39 | 47 | static void i915_gem_object_set_to_full_cpu_read_domain(struct drm_i915_gem_object *obj); |
88241785 CW |
48 | static __must_check int i915_gem_object_bind_to_gtt(struct drm_i915_gem_object *obj, |
49 | unsigned alignment, | |
50 | bool map_and_fenceable); | |
d9e86c0e CW |
51 | static void i915_gem_clear_fence_reg(struct drm_device *dev, |
52 | struct drm_i915_fence_reg *reg); | |
05394f39 CW |
53 | static int i915_gem_phys_pwrite(struct drm_device *dev, |
54 | struct drm_i915_gem_object *obj, | |
71acb5eb | 55 | struct drm_i915_gem_pwrite *args, |
05394f39 CW |
56 | struct drm_file *file); |
57 | static void i915_gem_free_object_tail(struct drm_i915_gem_object *obj); | |
673a394b | 58 | |
17250b71 | 59 | static int i915_gem_inactive_shrink(struct shrinker *shrinker, |
1495f230 | 60 | struct shrink_control *sc); |
31169714 | 61 | |
73aa808f CW |
62 | /* some bookkeeping */ |
63 | static void i915_gem_info_add_obj(struct drm_i915_private *dev_priv, | |
64 | size_t size) | |
65 | { | |
66 | dev_priv->mm.object_count++; | |
67 | dev_priv->mm.object_memory += size; | |
68 | } | |
69 | ||
70 | static void i915_gem_info_remove_obj(struct drm_i915_private *dev_priv, | |
71 | size_t size) | |
72 | { | |
73 | dev_priv->mm.object_count--; | |
74 | dev_priv->mm.object_memory -= size; | |
75 | } | |
76 | ||
21dd3734 CW |
77 | static int |
78 | i915_gem_wait_for_error(struct drm_device *dev) | |
30dbf0c0 CW |
79 | { |
80 | struct drm_i915_private *dev_priv = dev->dev_private; | |
81 | struct completion *x = &dev_priv->error_completion; | |
82 | unsigned long flags; | |
83 | int ret; | |
84 | ||
85 | if (!atomic_read(&dev_priv->mm.wedged)) | |
86 | return 0; | |
87 | ||
88 | ret = wait_for_completion_interruptible(x); | |
89 | if (ret) | |
90 | return ret; | |
91 | ||
21dd3734 CW |
92 | if (atomic_read(&dev_priv->mm.wedged)) { |
93 | /* GPU is hung, bump the completion count to account for | |
94 | * the token we just consumed so that we never hit zero and | |
95 | * end up waiting upon a subsequent completion event that | |
96 | * will never happen. | |
97 | */ | |
98 | spin_lock_irqsave(&x->wait.lock, flags); | |
99 | x->done++; | |
100 | spin_unlock_irqrestore(&x->wait.lock, flags); | |
101 | } | |
102 | return 0; | |
30dbf0c0 CW |
103 | } |
104 | ||
54cf91dc | 105 | int i915_mutex_lock_interruptible(struct drm_device *dev) |
76c1dec1 | 106 | { |
76c1dec1 CW |
107 | int ret; |
108 | ||
21dd3734 | 109 | ret = i915_gem_wait_for_error(dev); |
76c1dec1 CW |
110 | if (ret) |
111 | return ret; | |
112 | ||
113 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
114 | if (ret) | |
115 | return ret; | |
116 | ||
23bc5982 | 117 | WARN_ON(i915_verify_lists(dev)); |
76c1dec1 CW |
118 | return 0; |
119 | } | |
30dbf0c0 | 120 | |
7d1c4804 | 121 | static inline bool |
05394f39 | 122 | i915_gem_object_is_inactive(struct drm_i915_gem_object *obj) |
7d1c4804 | 123 | { |
05394f39 | 124 | return obj->gtt_space && !obj->active && obj->pin_count == 0; |
7d1c4804 CW |
125 | } |
126 | ||
2021746e CW |
127 | void i915_gem_do_init(struct drm_device *dev, |
128 | unsigned long start, | |
129 | unsigned long mappable_end, | |
130 | unsigned long end) | |
673a394b EA |
131 | { |
132 | drm_i915_private_t *dev_priv = dev->dev_private; | |
673a394b | 133 | |
bee4a186 | 134 | drm_mm_init(&dev_priv->mm.gtt_space, start, end - start); |
673a394b | 135 | |
bee4a186 CW |
136 | dev_priv->mm.gtt_start = start; |
137 | dev_priv->mm.gtt_mappable_end = mappable_end; | |
138 | dev_priv->mm.gtt_end = end; | |
73aa808f | 139 | dev_priv->mm.gtt_total = end - start; |
fb7d516a | 140 | dev_priv->mm.mappable_gtt_total = min(end, mappable_end) - start; |
bee4a186 CW |
141 | |
142 | /* Take over this portion of the GTT */ | |
143 | intel_gtt_clear_range(start / PAGE_SIZE, (end-start) / PAGE_SIZE); | |
79e53945 | 144 | } |
673a394b | 145 | |
79e53945 JB |
146 | int |
147 | i915_gem_init_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 148 | struct drm_file *file) |
79e53945 JB |
149 | { |
150 | struct drm_i915_gem_init *args = data; | |
2021746e CW |
151 | |
152 | if (args->gtt_start >= args->gtt_end || | |
153 | (args->gtt_end | args->gtt_start) & (PAGE_SIZE - 1)) | |
154 | return -EINVAL; | |
79e53945 JB |
155 | |
156 | mutex_lock(&dev->struct_mutex); | |
2021746e | 157 | i915_gem_do_init(dev, args->gtt_start, args->gtt_end, args->gtt_end); |
673a394b EA |
158 | mutex_unlock(&dev->struct_mutex); |
159 | ||
2021746e | 160 | return 0; |
673a394b EA |
161 | } |
162 | ||
5a125c3c EA |
163 | int |
164 | i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 165 | struct drm_file *file) |
5a125c3c | 166 | { |
73aa808f | 167 | struct drm_i915_private *dev_priv = dev->dev_private; |
5a125c3c | 168 | struct drm_i915_gem_get_aperture *args = data; |
6299f992 CW |
169 | struct drm_i915_gem_object *obj; |
170 | size_t pinned; | |
5a125c3c EA |
171 | |
172 | if (!(dev->driver->driver_features & DRIVER_GEM)) | |
173 | return -ENODEV; | |
174 | ||
6299f992 | 175 | pinned = 0; |
73aa808f | 176 | mutex_lock(&dev->struct_mutex); |
6299f992 CW |
177 | list_for_each_entry(obj, &dev_priv->mm.pinned_list, mm_list) |
178 | pinned += obj->gtt_space->size; | |
73aa808f | 179 | mutex_unlock(&dev->struct_mutex); |
5a125c3c | 180 | |
6299f992 | 181 | args->aper_size = dev_priv->mm.gtt_total; |
0206e353 | 182 | args->aper_available_size = args->aper_size - pinned; |
6299f992 | 183 | |
5a125c3c EA |
184 | return 0; |
185 | } | |
186 | ||
ff72145b DA |
187 | static int |
188 | i915_gem_create(struct drm_file *file, | |
189 | struct drm_device *dev, | |
190 | uint64_t size, | |
191 | uint32_t *handle_p) | |
673a394b | 192 | { |
05394f39 | 193 | struct drm_i915_gem_object *obj; |
a1a2d1d3 PP |
194 | int ret; |
195 | u32 handle; | |
673a394b | 196 | |
ff72145b | 197 | size = roundup(size, PAGE_SIZE); |
673a394b EA |
198 | |
199 | /* Allocate the new object */ | |
ff72145b | 200 | obj = i915_gem_alloc_object(dev, size); |
673a394b EA |
201 | if (obj == NULL) |
202 | return -ENOMEM; | |
203 | ||
05394f39 | 204 | ret = drm_gem_handle_create(file, &obj->base, &handle); |
1dfd9754 | 205 | if (ret) { |
05394f39 CW |
206 | drm_gem_object_release(&obj->base); |
207 | i915_gem_info_remove_obj(dev->dev_private, obj->base.size); | |
202f2fef | 208 | kfree(obj); |
673a394b | 209 | return ret; |
1dfd9754 | 210 | } |
673a394b | 211 | |
202f2fef | 212 | /* drop reference from allocate - handle holds it now */ |
05394f39 | 213 | drm_gem_object_unreference(&obj->base); |
202f2fef CW |
214 | trace_i915_gem_object_create(obj); |
215 | ||
ff72145b | 216 | *handle_p = handle; |
673a394b EA |
217 | return 0; |
218 | } | |
219 | ||
ff72145b DA |
220 | int |
221 | i915_gem_dumb_create(struct drm_file *file, | |
222 | struct drm_device *dev, | |
223 | struct drm_mode_create_dumb *args) | |
224 | { | |
225 | /* have to work out size/pitch and return them */ | |
ed0291fd | 226 | args->pitch = ALIGN(args->width * ((args->bpp + 7) / 8), 64); |
ff72145b DA |
227 | args->size = args->pitch * args->height; |
228 | return i915_gem_create(file, dev, | |
229 | args->size, &args->handle); | |
230 | } | |
231 | ||
232 | int i915_gem_dumb_destroy(struct drm_file *file, | |
233 | struct drm_device *dev, | |
234 | uint32_t handle) | |
235 | { | |
236 | return drm_gem_handle_delete(file, handle); | |
237 | } | |
238 | ||
239 | /** | |
240 | * Creates a new mm object and returns a handle to it. | |
241 | */ | |
242 | int | |
243 | i915_gem_create_ioctl(struct drm_device *dev, void *data, | |
244 | struct drm_file *file) | |
245 | { | |
246 | struct drm_i915_gem_create *args = data; | |
247 | return i915_gem_create(file, dev, | |
248 | args->size, &args->handle); | |
249 | } | |
250 | ||
05394f39 | 251 | static int i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj) |
280b713b | 252 | { |
05394f39 | 253 | drm_i915_private_t *dev_priv = obj->base.dev->dev_private; |
280b713b EA |
254 | |
255 | return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 && | |
05394f39 | 256 | obj->tiling_mode != I915_TILING_NONE; |
280b713b EA |
257 | } |
258 | ||
99a03df5 | 259 | static inline void |
40123c1f EA |
260 | slow_shmem_copy(struct page *dst_page, |
261 | int dst_offset, | |
262 | struct page *src_page, | |
263 | int src_offset, | |
264 | int length) | |
265 | { | |
266 | char *dst_vaddr, *src_vaddr; | |
267 | ||
99a03df5 CW |
268 | dst_vaddr = kmap(dst_page); |
269 | src_vaddr = kmap(src_page); | |
40123c1f EA |
270 | |
271 | memcpy(dst_vaddr + dst_offset, src_vaddr + src_offset, length); | |
272 | ||
99a03df5 CW |
273 | kunmap(src_page); |
274 | kunmap(dst_page); | |
40123c1f EA |
275 | } |
276 | ||
99a03df5 | 277 | static inline void |
280b713b EA |
278 | slow_shmem_bit17_copy(struct page *gpu_page, |
279 | int gpu_offset, | |
280 | struct page *cpu_page, | |
281 | int cpu_offset, | |
282 | int length, | |
283 | int is_read) | |
284 | { | |
285 | char *gpu_vaddr, *cpu_vaddr; | |
286 | ||
287 | /* Use the unswizzled path if this page isn't affected. */ | |
288 | if ((page_to_phys(gpu_page) & (1 << 17)) == 0) { | |
289 | if (is_read) | |
290 | return slow_shmem_copy(cpu_page, cpu_offset, | |
291 | gpu_page, gpu_offset, length); | |
292 | else | |
293 | return slow_shmem_copy(gpu_page, gpu_offset, | |
294 | cpu_page, cpu_offset, length); | |
295 | } | |
296 | ||
99a03df5 CW |
297 | gpu_vaddr = kmap(gpu_page); |
298 | cpu_vaddr = kmap(cpu_page); | |
280b713b EA |
299 | |
300 | /* Copy the data, XORing A6 with A17 (1). The user already knows he's | |
301 | * XORing with the other bits (A9 for Y, A9 and A10 for X) | |
302 | */ | |
303 | while (length > 0) { | |
304 | int cacheline_end = ALIGN(gpu_offset + 1, 64); | |
305 | int this_length = min(cacheline_end - gpu_offset, length); | |
306 | int swizzled_gpu_offset = gpu_offset ^ 64; | |
307 | ||
308 | if (is_read) { | |
309 | memcpy(cpu_vaddr + cpu_offset, | |
310 | gpu_vaddr + swizzled_gpu_offset, | |
311 | this_length); | |
312 | } else { | |
313 | memcpy(gpu_vaddr + swizzled_gpu_offset, | |
314 | cpu_vaddr + cpu_offset, | |
315 | this_length); | |
316 | } | |
317 | cpu_offset += this_length; | |
318 | gpu_offset += this_length; | |
319 | length -= this_length; | |
320 | } | |
321 | ||
99a03df5 CW |
322 | kunmap(cpu_page); |
323 | kunmap(gpu_page); | |
280b713b EA |
324 | } |
325 | ||
eb01459f EA |
326 | /** |
327 | * This is the fast shmem pread path, which attempts to copy_from_user directly | |
328 | * from the backing pages of the object to the user's address space. On a | |
329 | * fault, it fails so we can fall back to i915_gem_shmem_pwrite_slow(). | |
330 | */ | |
331 | static int | |
05394f39 CW |
332 | i915_gem_shmem_pread_fast(struct drm_device *dev, |
333 | struct drm_i915_gem_object *obj, | |
eb01459f | 334 | struct drm_i915_gem_pread *args, |
05394f39 | 335 | struct drm_file *file) |
eb01459f | 336 | { |
05394f39 | 337 | struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping; |
eb01459f | 338 | ssize_t remain; |
e5281ccd | 339 | loff_t offset; |
eb01459f EA |
340 | char __user *user_data; |
341 | int page_offset, page_length; | |
eb01459f EA |
342 | |
343 | user_data = (char __user *) (uintptr_t) args->data_ptr; | |
344 | remain = args->size; | |
345 | ||
eb01459f EA |
346 | offset = args->offset; |
347 | ||
348 | while (remain > 0) { | |
e5281ccd CW |
349 | struct page *page; |
350 | char *vaddr; | |
351 | int ret; | |
352 | ||
eb01459f EA |
353 | /* Operation in this page |
354 | * | |
eb01459f EA |
355 | * page_offset = offset within page |
356 | * page_length = bytes to copy for this page | |
357 | */ | |
c8cbbb8b | 358 | page_offset = offset_in_page(offset); |
eb01459f EA |
359 | page_length = remain; |
360 | if ((page_offset + remain) > PAGE_SIZE) | |
361 | page_length = PAGE_SIZE - page_offset; | |
362 | ||
5949eac4 | 363 | page = shmem_read_mapping_page(mapping, offset >> PAGE_SHIFT); |
e5281ccd CW |
364 | if (IS_ERR(page)) |
365 | return PTR_ERR(page); | |
366 | ||
367 | vaddr = kmap_atomic(page); | |
368 | ret = __copy_to_user_inatomic(user_data, | |
369 | vaddr + page_offset, | |
370 | page_length); | |
371 | kunmap_atomic(vaddr); | |
372 | ||
373 | mark_page_accessed(page); | |
374 | page_cache_release(page); | |
375 | if (ret) | |
4f27b75d | 376 | return -EFAULT; |
eb01459f EA |
377 | |
378 | remain -= page_length; | |
379 | user_data += page_length; | |
380 | offset += page_length; | |
381 | } | |
382 | ||
4f27b75d | 383 | return 0; |
eb01459f EA |
384 | } |
385 | ||
386 | /** | |
387 | * This is the fallback shmem pread path, which allocates temporary storage | |
388 | * in kernel space to copy_to_user into outside of the struct_mutex, so we | |
389 | * can copy out of the object's backing pages while holding the struct mutex | |
390 | * and not take page faults. | |
391 | */ | |
392 | static int | |
05394f39 CW |
393 | i915_gem_shmem_pread_slow(struct drm_device *dev, |
394 | struct drm_i915_gem_object *obj, | |
eb01459f | 395 | struct drm_i915_gem_pread *args, |
05394f39 | 396 | struct drm_file *file) |
eb01459f | 397 | { |
05394f39 | 398 | struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping; |
eb01459f EA |
399 | struct mm_struct *mm = current->mm; |
400 | struct page **user_pages; | |
401 | ssize_t remain; | |
402 | loff_t offset, pinned_pages, i; | |
403 | loff_t first_data_page, last_data_page, num_pages; | |
e5281ccd CW |
404 | int shmem_page_offset; |
405 | int data_page_index, data_page_offset; | |
eb01459f EA |
406 | int page_length; |
407 | int ret; | |
408 | uint64_t data_ptr = args->data_ptr; | |
280b713b | 409 | int do_bit17_swizzling; |
eb01459f EA |
410 | |
411 | remain = args->size; | |
412 | ||
413 | /* Pin the user pages containing the data. We can't fault while | |
414 | * holding the struct mutex, yet we want to hold it while | |
415 | * dereferencing the user data. | |
416 | */ | |
417 | first_data_page = data_ptr / PAGE_SIZE; | |
418 | last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE; | |
419 | num_pages = last_data_page - first_data_page + 1; | |
420 | ||
4f27b75d | 421 | user_pages = drm_malloc_ab(num_pages, sizeof(struct page *)); |
eb01459f EA |
422 | if (user_pages == NULL) |
423 | return -ENOMEM; | |
424 | ||
4f27b75d | 425 | mutex_unlock(&dev->struct_mutex); |
eb01459f EA |
426 | down_read(&mm->mmap_sem); |
427 | pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr, | |
e5e9ecde | 428 | num_pages, 1, 0, user_pages, NULL); |
eb01459f | 429 | up_read(&mm->mmap_sem); |
4f27b75d | 430 | mutex_lock(&dev->struct_mutex); |
eb01459f EA |
431 | if (pinned_pages < num_pages) { |
432 | ret = -EFAULT; | |
4f27b75d | 433 | goto out; |
eb01459f EA |
434 | } |
435 | ||
4f27b75d CW |
436 | ret = i915_gem_object_set_cpu_read_domain_range(obj, |
437 | args->offset, | |
438 | args->size); | |
07f73f69 | 439 | if (ret) |
4f27b75d | 440 | goto out; |
eb01459f | 441 | |
4f27b75d | 442 | do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj); |
eb01459f | 443 | |
eb01459f EA |
444 | offset = args->offset; |
445 | ||
446 | while (remain > 0) { | |
e5281ccd CW |
447 | struct page *page; |
448 | ||
eb01459f EA |
449 | /* Operation in this page |
450 | * | |
eb01459f EA |
451 | * shmem_page_offset = offset within page in shmem file |
452 | * data_page_index = page number in get_user_pages return | |
453 | * data_page_offset = offset with data_page_index page. | |
454 | * page_length = bytes to copy for this page | |
455 | */ | |
c8cbbb8b | 456 | shmem_page_offset = offset_in_page(offset); |
eb01459f | 457 | data_page_index = data_ptr / PAGE_SIZE - first_data_page; |
c8cbbb8b | 458 | data_page_offset = offset_in_page(data_ptr); |
eb01459f EA |
459 | |
460 | page_length = remain; | |
461 | if ((shmem_page_offset + page_length) > PAGE_SIZE) | |
462 | page_length = PAGE_SIZE - shmem_page_offset; | |
463 | if ((data_page_offset + page_length) > PAGE_SIZE) | |
464 | page_length = PAGE_SIZE - data_page_offset; | |
465 | ||
5949eac4 | 466 | page = shmem_read_mapping_page(mapping, offset >> PAGE_SHIFT); |
b65552f0 JJ |
467 | if (IS_ERR(page)) { |
468 | ret = PTR_ERR(page); | |
469 | goto out; | |
470 | } | |
e5281ccd | 471 | |
280b713b | 472 | if (do_bit17_swizzling) { |
e5281ccd | 473 | slow_shmem_bit17_copy(page, |
280b713b | 474 | shmem_page_offset, |
99a03df5 CW |
475 | user_pages[data_page_index], |
476 | data_page_offset, | |
477 | page_length, | |
478 | 1); | |
479 | } else { | |
480 | slow_shmem_copy(user_pages[data_page_index], | |
481 | data_page_offset, | |
e5281ccd | 482 | page, |
99a03df5 CW |
483 | shmem_page_offset, |
484 | page_length); | |
280b713b | 485 | } |
eb01459f | 486 | |
e5281ccd CW |
487 | mark_page_accessed(page); |
488 | page_cache_release(page); | |
489 | ||
eb01459f EA |
490 | remain -= page_length; |
491 | data_ptr += page_length; | |
492 | offset += page_length; | |
493 | } | |
494 | ||
4f27b75d | 495 | out: |
eb01459f EA |
496 | for (i = 0; i < pinned_pages; i++) { |
497 | SetPageDirty(user_pages[i]); | |
e5281ccd | 498 | mark_page_accessed(user_pages[i]); |
eb01459f EA |
499 | page_cache_release(user_pages[i]); |
500 | } | |
8e7d2b2c | 501 | drm_free_large(user_pages); |
eb01459f EA |
502 | |
503 | return ret; | |
504 | } | |
505 | ||
673a394b EA |
506 | /** |
507 | * Reads data from the object referenced by handle. | |
508 | * | |
509 | * On error, the contents of *data are undefined. | |
510 | */ | |
511 | int | |
512 | i915_gem_pread_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 513 | struct drm_file *file) |
673a394b EA |
514 | { |
515 | struct drm_i915_gem_pread *args = data; | |
05394f39 | 516 | struct drm_i915_gem_object *obj; |
35b62a89 | 517 | int ret = 0; |
673a394b | 518 | |
51311d0a CW |
519 | if (args->size == 0) |
520 | return 0; | |
521 | ||
522 | if (!access_ok(VERIFY_WRITE, | |
523 | (char __user *)(uintptr_t)args->data_ptr, | |
524 | args->size)) | |
525 | return -EFAULT; | |
526 | ||
527 | ret = fault_in_pages_writeable((char __user *)(uintptr_t)args->data_ptr, | |
528 | args->size); | |
529 | if (ret) | |
530 | return -EFAULT; | |
531 | ||
4f27b75d | 532 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 533 | if (ret) |
4f27b75d | 534 | return ret; |
673a394b | 535 | |
05394f39 | 536 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 537 | if (&obj->base == NULL) { |
1d7cfea1 CW |
538 | ret = -ENOENT; |
539 | goto unlock; | |
4f27b75d | 540 | } |
673a394b | 541 | |
7dcd2499 | 542 | /* Bounds check source. */ |
05394f39 CW |
543 | if (args->offset > obj->base.size || |
544 | args->size > obj->base.size - args->offset) { | |
ce9d419d | 545 | ret = -EINVAL; |
35b62a89 | 546 | goto out; |
ce9d419d CW |
547 | } |
548 | ||
db53a302 CW |
549 | trace_i915_gem_object_pread(obj, args->offset, args->size); |
550 | ||
4f27b75d CW |
551 | ret = i915_gem_object_set_cpu_read_domain_range(obj, |
552 | args->offset, | |
553 | args->size); | |
554 | if (ret) | |
e5281ccd | 555 | goto out; |
4f27b75d CW |
556 | |
557 | ret = -EFAULT; | |
558 | if (!i915_gem_object_needs_bit17_swizzle(obj)) | |
05394f39 | 559 | ret = i915_gem_shmem_pread_fast(dev, obj, args, file); |
4f27b75d | 560 | if (ret == -EFAULT) |
05394f39 | 561 | ret = i915_gem_shmem_pread_slow(dev, obj, args, file); |
673a394b | 562 | |
35b62a89 | 563 | out: |
05394f39 | 564 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 565 | unlock: |
4f27b75d | 566 | mutex_unlock(&dev->struct_mutex); |
eb01459f | 567 | return ret; |
673a394b EA |
568 | } |
569 | ||
0839ccb8 KP |
570 | /* This is the fast write path which cannot handle |
571 | * page faults in the source data | |
9b7530cc | 572 | */ |
0839ccb8 KP |
573 | |
574 | static inline int | |
575 | fast_user_write(struct io_mapping *mapping, | |
576 | loff_t page_base, int page_offset, | |
577 | char __user *user_data, | |
578 | int length) | |
9b7530cc | 579 | { |
9b7530cc | 580 | char *vaddr_atomic; |
0839ccb8 | 581 | unsigned long unwritten; |
9b7530cc | 582 | |
3e4d3af5 | 583 | vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base); |
0839ccb8 KP |
584 | unwritten = __copy_from_user_inatomic_nocache(vaddr_atomic + page_offset, |
585 | user_data, length); | |
3e4d3af5 | 586 | io_mapping_unmap_atomic(vaddr_atomic); |
fbd5a26d | 587 | return unwritten; |
0839ccb8 KP |
588 | } |
589 | ||
590 | /* Here's the write path which can sleep for | |
591 | * page faults | |
592 | */ | |
593 | ||
ab34c226 | 594 | static inline void |
3de09aa3 EA |
595 | slow_kernel_write(struct io_mapping *mapping, |
596 | loff_t gtt_base, int gtt_offset, | |
597 | struct page *user_page, int user_offset, | |
598 | int length) | |
0839ccb8 | 599 | { |
ab34c226 CW |
600 | char __iomem *dst_vaddr; |
601 | char *src_vaddr; | |
0839ccb8 | 602 | |
ab34c226 CW |
603 | dst_vaddr = io_mapping_map_wc(mapping, gtt_base); |
604 | src_vaddr = kmap(user_page); | |
605 | ||
606 | memcpy_toio(dst_vaddr + gtt_offset, | |
607 | src_vaddr + user_offset, | |
608 | length); | |
609 | ||
610 | kunmap(user_page); | |
611 | io_mapping_unmap(dst_vaddr); | |
9b7530cc LT |
612 | } |
613 | ||
3de09aa3 EA |
614 | /** |
615 | * This is the fast pwrite path, where we copy the data directly from the | |
616 | * user into the GTT, uncached. | |
617 | */ | |
673a394b | 618 | static int |
05394f39 CW |
619 | i915_gem_gtt_pwrite_fast(struct drm_device *dev, |
620 | struct drm_i915_gem_object *obj, | |
3de09aa3 | 621 | struct drm_i915_gem_pwrite *args, |
05394f39 | 622 | struct drm_file *file) |
673a394b | 623 | { |
0839ccb8 | 624 | drm_i915_private_t *dev_priv = dev->dev_private; |
673a394b | 625 | ssize_t remain; |
0839ccb8 | 626 | loff_t offset, page_base; |
673a394b | 627 | char __user *user_data; |
0839ccb8 | 628 | int page_offset, page_length; |
673a394b EA |
629 | |
630 | user_data = (char __user *) (uintptr_t) args->data_ptr; | |
631 | remain = args->size; | |
673a394b | 632 | |
05394f39 | 633 | offset = obj->gtt_offset + args->offset; |
673a394b EA |
634 | |
635 | while (remain > 0) { | |
636 | /* Operation in this page | |
637 | * | |
0839ccb8 KP |
638 | * page_base = page offset within aperture |
639 | * page_offset = offset within page | |
640 | * page_length = bytes to copy for this page | |
673a394b | 641 | */ |
c8cbbb8b CW |
642 | page_base = offset & PAGE_MASK; |
643 | page_offset = offset_in_page(offset); | |
0839ccb8 KP |
644 | page_length = remain; |
645 | if ((page_offset + remain) > PAGE_SIZE) | |
646 | page_length = PAGE_SIZE - page_offset; | |
647 | ||
0839ccb8 | 648 | /* If we get a fault while copying data, then (presumably) our |
3de09aa3 EA |
649 | * source page isn't available. Return the error and we'll |
650 | * retry in the slow path. | |
0839ccb8 | 651 | */ |
fbd5a26d CW |
652 | if (fast_user_write(dev_priv->mm.gtt_mapping, page_base, |
653 | page_offset, user_data, page_length)) | |
fbd5a26d | 654 | return -EFAULT; |
673a394b | 655 | |
0839ccb8 KP |
656 | remain -= page_length; |
657 | user_data += page_length; | |
658 | offset += page_length; | |
673a394b | 659 | } |
673a394b | 660 | |
fbd5a26d | 661 | return 0; |
673a394b EA |
662 | } |
663 | ||
3de09aa3 EA |
664 | /** |
665 | * This is the fallback GTT pwrite path, which uses get_user_pages to pin | |
666 | * the memory and maps it using kmap_atomic for copying. | |
667 | * | |
668 | * This code resulted in x11perf -rgb10text consuming about 10% more CPU | |
669 | * than using i915_gem_gtt_pwrite_fast on a G45 (32-bit). | |
670 | */ | |
3043c60c | 671 | static int |
05394f39 CW |
672 | i915_gem_gtt_pwrite_slow(struct drm_device *dev, |
673 | struct drm_i915_gem_object *obj, | |
3de09aa3 | 674 | struct drm_i915_gem_pwrite *args, |
05394f39 | 675 | struct drm_file *file) |
673a394b | 676 | { |
3de09aa3 EA |
677 | drm_i915_private_t *dev_priv = dev->dev_private; |
678 | ssize_t remain; | |
679 | loff_t gtt_page_base, offset; | |
680 | loff_t first_data_page, last_data_page, num_pages; | |
681 | loff_t pinned_pages, i; | |
682 | struct page **user_pages; | |
683 | struct mm_struct *mm = current->mm; | |
684 | int gtt_page_offset, data_page_offset, data_page_index, page_length; | |
673a394b | 685 | int ret; |
3de09aa3 EA |
686 | uint64_t data_ptr = args->data_ptr; |
687 | ||
688 | remain = args->size; | |
689 | ||
690 | /* Pin the user pages containing the data. We can't fault while | |
691 | * holding the struct mutex, and all of the pwrite implementations | |
692 | * want to hold it while dereferencing the user data. | |
693 | */ | |
694 | first_data_page = data_ptr / PAGE_SIZE; | |
695 | last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE; | |
696 | num_pages = last_data_page - first_data_page + 1; | |
697 | ||
fbd5a26d | 698 | user_pages = drm_malloc_ab(num_pages, sizeof(struct page *)); |
3de09aa3 EA |
699 | if (user_pages == NULL) |
700 | return -ENOMEM; | |
701 | ||
fbd5a26d | 702 | mutex_unlock(&dev->struct_mutex); |
3de09aa3 EA |
703 | down_read(&mm->mmap_sem); |
704 | pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr, | |
705 | num_pages, 0, 0, user_pages, NULL); | |
706 | up_read(&mm->mmap_sem); | |
fbd5a26d | 707 | mutex_lock(&dev->struct_mutex); |
3de09aa3 EA |
708 | if (pinned_pages < num_pages) { |
709 | ret = -EFAULT; | |
710 | goto out_unpin_pages; | |
711 | } | |
673a394b | 712 | |
d9e86c0e CW |
713 | ret = i915_gem_object_set_to_gtt_domain(obj, true); |
714 | if (ret) | |
715 | goto out_unpin_pages; | |
716 | ||
717 | ret = i915_gem_object_put_fence(obj); | |
3de09aa3 | 718 | if (ret) |
fbd5a26d | 719 | goto out_unpin_pages; |
3de09aa3 | 720 | |
05394f39 | 721 | offset = obj->gtt_offset + args->offset; |
3de09aa3 EA |
722 | |
723 | while (remain > 0) { | |
724 | /* Operation in this page | |
725 | * | |
726 | * gtt_page_base = page offset within aperture | |
727 | * gtt_page_offset = offset within page in aperture | |
728 | * data_page_index = page number in get_user_pages return | |
729 | * data_page_offset = offset with data_page_index page. | |
730 | * page_length = bytes to copy for this page | |
731 | */ | |
732 | gtt_page_base = offset & PAGE_MASK; | |
c8cbbb8b | 733 | gtt_page_offset = offset_in_page(offset); |
3de09aa3 | 734 | data_page_index = data_ptr / PAGE_SIZE - first_data_page; |
c8cbbb8b | 735 | data_page_offset = offset_in_page(data_ptr); |
3de09aa3 EA |
736 | |
737 | page_length = remain; | |
738 | if ((gtt_page_offset + page_length) > PAGE_SIZE) | |
739 | page_length = PAGE_SIZE - gtt_page_offset; | |
740 | if ((data_page_offset + page_length) > PAGE_SIZE) | |
741 | page_length = PAGE_SIZE - data_page_offset; | |
742 | ||
ab34c226 CW |
743 | slow_kernel_write(dev_priv->mm.gtt_mapping, |
744 | gtt_page_base, gtt_page_offset, | |
745 | user_pages[data_page_index], | |
746 | data_page_offset, | |
747 | page_length); | |
3de09aa3 EA |
748 | |
749 | remain -= page_length; | |
750 | offset += page_length; | |
751 | data_ptr += page_length; | |
752 | } | |
753 | ||
3de09aa3 EA |
754 | out_unpin_pages: |
755 | for (i = 0; i < pinned_pages; i++) | |
756 | page_cache_release(user_pages[i]); | |
8e7d2b2c | 757 | drm_free_large(user_pages); |
3de09aa3 EA |
758 | |
759 | return ret; | |
760 | } | |
761 | ||
40123c1f EA |
762 | /** |
763 | * This is the fast shmem pwrite path, which attempts to directly | |
764 | * copy_from_user into the kmapped pages backing the object. | |
765 | */ | |
3043c60c | 766 | static int |
05394f39 CW |
767 | i915_gem_shmem_pwrite_fast(struct drm_device *dev, |
768 | struct drm_i915_gem_object *obj, | |
40123c1f | 769 | struct drm_i915_gem_pwrite *args, |
05394f39 | 770 | struct drm_file *file) |
673a394b | 771 | { |
05394f39 | 772 | struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping; |
40123c1f | 773 | ssize_t remain; |
e5281ccd | 774 | loff_t offset; |
40123c1f EA |
775 | char __user *user_data; |
776 | int page_offset, page_length; | |
40123c1f EA |
777 | |
778 | user_data = (char __user *) (uintptr_t) args->data_ptr; | |
779 | remain = args->size; | |
673a394b | 780 | |
40123c1f | 781 | offset = args->offset; |
05394f39 | 782 | obj->dirty = 1; |
40123c1f EA |
783 | |
784 | while (remain > 0) { | |
e5281ccd CW |
785 | struct page *page; |
786 | char *vaddr; | |
787 | int ret; | |
788 | ||
40123c1f EA |
789 | /* Operation in this page |
790 | * | |
40123c1f EA |
791 | * page_offset = offset within page |
792 | * page_length = bytes to copy for this page | |
793 | */ | |
c8cbbb8b | 794 | page_offset = offset_in_page(offset); |
40123c1f EA |
795 | page_length = remain; |
796 | if ((page_offset + remain) > PAGE_SIZE) | |
797 | page_length = PAGE_SIZE - page_offset; | |
798 | ||
5949eac4 | 799 | page = shmem_read_mapping_page(mapping, offset >> PAGE_SHIFT); |
e5281ccd CW |
800 | if (IS_ERR(page)) |
801 | return PTR_ERR(page); | |
802 | ||
803 | vaddr = kmap_atomic(page, KM_USER0); | |
804 | ret = __copy_from_user_inatomic(vaddr + page_offset, | |
805 | user_data, | |
806 | page_length); | |
807 | kunmap_atomic(vaddr, KM_USER0); | |
808 | ||
809 | set_page_dirty(page); | |
810 | mark_page_accessed(page); | |
811 | page_cache_release(page); | |
812 | ||
813 | /* If we get a fault while copying data, then (presumably) our | |
814 | * source page isn't available. Return the error and we'll | |
815 | * retry in the slow path. | |
816 | */ | |
817 | if (ret) | |
fbd5a26d | 818 | return -EFAULT; |
40123c1f EA |
819 | |
820 | remain -= page_length; | |
821 | user_data += page_length; | |
822 | offset += page_length; | |
823 | } | |
824 | ||
fbd5a26d | 825 | return 0; |
40123c1f EA |
826 | } |
827 | ||
828 | /** | |
829 | * This is the fallback shmem pwrite path, which uses get_user_pages to pin | |
830 | * the memory and maps it using kmap_atomic for copying. | |
831 | * | |
832 | * This avoids taking mmap_sem for faulting on the user's address while the | |
833 | * struct_mutex is held. | |
834 | */ | |
835 | static int | |
05394f39 CW |
836 | i915_gem_shmem_pwrite_slow(struct drm_device *dev, |
837 | struct drm_i915_gem_object *obj, | |
40123c1f | 838 | struct drm_i915_gem_pwrite *args, |
05394f39 | 839 | struct drm_file *file) |
40123c1f | 840 | { |
05394f39 | 841 | struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping; |
40123c1f EA |
842 | struct mm_struct *mm = current->mm; |
843 | struct page **user_pages; | |
844 | ssize_t remain; | |
845 | loff_t offset, pinned_pages, i; | |
846 | loff_t first_data_page, last_data_page, num_pages; | |
e5281ccd | 847 | int shmem_page_offset; |
40123c1f EA |
848 | int data_page_index, data_page_offset; |
849 | int page_length; | |
850 | int ret; | |
851 | uint64_t data_ptr = args->data_ptr; | |
280b713b | 852 | int do_bit17_swizzling; |
40123c1f EA |
853 | |
854 | remain = args->size; | |
855 | ||
856 | /* Pin the user pages containing the data. We can't fault while | |
857 | * holding the struct mutex, and all of the pwrite implementations | |
858 | * want to hold it while dereferencing the user data. | |
859 | */ | |
860 | first_data_page = data_ptr / PAGE_SIZE; | |
861 | last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE; | |
862 | num_pages = last_data_page - first_data_page + 1; | |
863 | ||
4f27b75d | 864 | user_pages = drm_malloc_ab(num_pages, sizeof(struct page *)); |
40123c1f EA |
865 | if (user_pages == NULL) |
866 | return -ENOMEM; | |
867 | ||
fbd5a26d | 868 | mutex_unlock(&dev->struct_mutex); |
40123c1f EA |
869 | down_read(&mm->mmap_sem); |
870 | pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr, | |
871 | num_pages, 0, 0, user_pages, NULL); | |
872 | up_read(&mm->mmap_sem); | |
fbd5a26d | 873 | mutex_lock(&dev->struct_mutex); |
40123c1f EA |
874 | if (pinned_pages < num_pages) { |
875 | ret = -EFAULT; | |
fbd5a26d | 876 | goto out; |
673a394b EA |
877 | } |
878 | ||
fbd5a26d | 879 | ret = i915_gem_object_set_to_cpu_domain(obj, 1); |
07f73f69 | 880 | if (ret) |
fbd5a26d | 881 | goto out; |
40123c1f | 882 | |
fbd5a26d | 883 | do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj); |
40123c1f | 884 | |
673a394b | 885 | offset = args->offset; |
05394f39 | 886 | obj->dirty = 1; |
673a394b | 887 | |
40123c1f | 888 | while (remain > 0) { |
e5281ccd CW |
889 | struct page *page; |
890 | ||
40123c1f EA |
891 | /* Operation in this page |
892 | * | |
40123c1f EA |
893 | * shmem_page_offset = offset within page in shmem file |
894 | * data_page_index = page number in get_user_pages return | |
895 | * data_page_offset = offset with data_page_index page. | |
896 | * page_length = bytes to copy for this page | |
897 | */ | |
c8cbbb8b | 898 | shmem_page_offset = offset_in_page(offset); |
40123c1f | 899 | data_page_index = data_ptr / PAGE_SIZE - first_data_page; |
c8cbbb8b | 900 | data_page_offset = offset_in_page(data_ptr); |
40123c1f EA |
901 | |
902 | page_length = remain; | |
903 | if ((shmem_page_offset + page_length) > PAGE_SIZE) | |
904 | page_length = PAGE_SIZE - shmem_page_offset; | |
905 | if ((data_page_offset + page_length) > PAGE_SIZE) | |
906 | page_length = PAGE_SIZE - data_page_offset; | |
907 | ||
5949eac4 | 908 | page = shmem_read_mapping_page(mapping, offset >> PAGE_SHIFT); |
e5281ccd CW |
909 | if (IS_ERR(page)) { |
910 | ret = PTR_ERR(page); | |
911 | goto out; | |
912 | } | |
913 | ||
280b713b | 914 | if (do_bit17_swizzling) { |
e5281ccd | 915 | slow_shmem_bit17_copy(page, |
280b713b EA |
916 | shmem_page_offset, |
917 | user_pages[data_page_index], | |
918 | data_page_offset, | |
99a03df5 CW |
919 | page_length, |
920 | 0); | |
921 | } else { | |
e5281ccd | 922 | slow_shmem_copy(page, |
99a03df5 CW |
923 | shmem_page_offset, |
924 | user_pages[data_page_index], | |
925 | data_page_offset, | |
926 | page_length); | |
280b713b | 927 | } |
40123c1f | 928 | |
e5281ccd CW |
929 | set_page_dirty(page); |
930 | mark_page_accessed(page); | |
931 | page_cache_release(page); | |
932 | ||
40123c1f EA |
933 | remain -= page_length; |
934 | data_ptr += page_length; | |
935 | offset += page_length; | |
673a394b EA |
936 | } |
937 | ||
fbd5a26d | 938 | out: |
40123c1f EA |
939 | for (i = 0; i < pinned_pages; i++) |
940 | page_cache_release(user_pages[i]); | |
8e7d2b2c | 941 | drm_free_large(user_pages); |
673a394b | 942 | |
40123c1f | 943 | return ret; |
673a394b EA |
944 | } |
945 | ||
946 | /** | |
947 | * Writes data to the object referenced by handle. | |
948 | * | |
949 | * On error, the contents of the buffer that were to be modified are undefined. | |
950 | */ | |
951 | int | |
952 | i915_gem_pwrite_ioctl(struct drm_device *dev, void *data, | |
fbd5a26d | 953 | struct drm_file *file) |
673a394b EA |
954 | { |
955 | struct drm_i915_gem_pwrite *args = data; | |
05394f39 | 956 | struct drm_i915_gem_object *obj; |
51311d0a CW |
957 | int ret; |
958 | ||
959 | if (args->size == 0) | |
960 | return 0; | |
961 | ||
962 | if (!access_ok(VERIFY_READ, | |
963 | (char __user *)(uintptr_t)args->data_ptr, | |
964 | args->size)) | |
965 | return -EFAULT; | |
966 | ||
967 | ret = fault_in_pages_readable((char __user *)(uintptr_t)args->data_ptr, | |
968 | args->size); | |
969 | if (ret) | |
970 | return -EFAULT; | |
673a394b | 971 | |
fbd5a26d | 972 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 973 | if (ret) |
fbd5a26d | 974 | return ret; |
1d7cfea1 | 975 | |
05394f39 | 976 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 977 | if (&obj->base == NULL) { |
1d7cfea1 CW |
978 | ret = -ENOENT; |
979 | goto unlock; | |
fbd5a26d | 980 | } |
673a394b | 981 | |
7dcd2499 | 982 | /* Bounds check destination. */ |
05394f39 CW |
983 | if (args->offset > obj->base.size || |
984 | args->size > obj->base.size - args->offset) { | |
ce9d419d | 985 | ret = -EINVAL; |
35b62a89 | 986 | goto out; |
ce9d419d CW |
987 | } |
988 | ||
db53a302 CW |
989 | trace_i915_gem_object_pwrite(obj, args->offset, args->size); |
990 | ||
673a394b EA |
991 | /* We can only do the GTT pwrite on untiled buffers, as otherwise |
992 | * it would end up going through the fenced access, and we'll get | |
993 | * different detiling behavior between reading and writing. | |
994 | * pread/pwrite currently are reading and writing from the CPU | |
995 | * perspective, requiring manual detiling by the client. | |
996 | */ | |
05394f39 | 997 | if (obj->phys_obj) |
fbd5a26d | 998 | ret = i915_gem_phys_pwrite(dev, obj, args, file); |
d9e86c0e | 999 | else if (obj->gtt_space && |
05394f39 | 1000 | obj->base.write_domain != I915_GEM_DOMAIN_CPU) { |
75e9e915 | 1001 | ret = i915_gem_object_pin(obj, 0, true); |
fbd5a26d CW |
1002 | if (ret) |
1003 | goto out; | |
1004 | ||
d9e86c0e CW |
1005 | ret = i915_gem_object_set_to_gtt_domain(obj, true); |
1006 | if (ret) | |
1007 | goto out_unpin; | |
1008 | ||
1009 | ret = i915_gem_object_put_fence(obj); | |
fbd5a26d CW |
1010 | if (ret) |
1011 | goto out_unpin; | |
1012 | ||
1013 | ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file); | |
1014 | if (ret == -EFAULT) | |
1015 | ret = i915_gem_gtt_pwrite_slow(dev, obj, args, file); | |
1016 | ||
1017 | out_unpin: | |
1018 | i915_gem_object_unpin(obj); | |
40123c1f | 1019 | } else { |
fbd5a26d CW |
1020 | ret = i915_gem_object_set_to_cpu_domain(obj, 1); |
1021 | if (ret) | |
e5281ccd | 1022 | goto out; |
673a394b | 1023 | |
fbd5a26d CW |
1024 | ret = -EFAULT; |
1025 | if (!i915_gem_object_needs_bit17_swizzle(obj)) | |
1026 | ret = i915_gem_shmem_pwrite_fast(dev, obj, args, file); | |
1027 | if (ret == -EFAULT) | |
1028 | ret = i915_gem_shmem_pwrite_slow(dev, obj, args, file); | |
fbd5a26d | 1029 | } |
673a394b | 1030 | |
35b62a89 | 1031 | out: |
05394f39 | 1032 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 1033 | unlock: |
fbd5a26d | 1034 | mutex_unlock(&dev->struct_mutex); |
673a394b EA |
1035 | return ret; |
1036 | } | |
1037 | ||
1038 | /** | |
2ef7eeaa EA |
1039 | * Called when user space prepares to use an object with the CPU, either |
1040 | * through the mmap ioctl's mapping or a GTT mapping. | |
673a394b EA |
1041 | */ |
1042 | int | |
1043 | i915_gem_set_domain_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 1044 | struct drm_file *file) |
673a394b EA |
1045 | { |
1046 | struct drm_i915_gem_set_domain *args = data; | |
05394f39 | 1047 | struct drm_i915_gem_object *obj; |
2ef7eeaa EA |
1048 | uint32_t read_domains = args->read_domains; |
1049 | uint32_t write_domain = args->write_domain; | |
673a394b EA |
1050 | int ret; |
1051 | ||
1052 | if (!(dev->driver->driver_features & DRIVER_GEM)) | |
1053 | return -ENODEV; | |
1054 | ||
2ef7eeaa | 1055 | /* Only handle setting domains to types used by the CPU. */ |
21d509e3 | 1056 | if (write_domain & I915_GEM_GPU_DOMAINS) |
2ef7eeaa EA |
1057 | return -EINVAL; |
1058 | ||
21d509e3 | 1059 | if (read_domains & I915_GEM_GPU_DOMAINS) |
2ef7eeaa EA |
1060 | return -EINVAL; |
1061 | ||
1062 | /* Having something in the write domain implies it's in the read | |
1063 | * domain, and only that read domain. Enforce that in the request. | |
1064 | */ | |
1065 | if (write_domain != 0 && read_domains != write_domain) | |
1066 | return -EINVAL; | |
1067 | ||
76c1dec1 | 1068 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 1069 | if (ret) |
76c1dec1 | 1070 | return ret; |
1d7cfea1 | 1071 | |
05394f39 | 1072 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 1073 | if (&obj->base == NULL) { |
1d7cfea1 CW |
1074 | ret = -ENOENT; |
1075 | goto unlock; | |
76c1dec1 | 1076 | } |
673a394b | 1077 | |
2ef7eeaa EA |
1078 | if (read_domains & I915_GEM_DOMAIN_GTT) { |
1079 | ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0); | |
02354392 EA |
1080 | |
1081 | /* Silently promote "you're not bound, there was nothing to do" | |
1082 | * to success, since the client was just asking us to | |
1083 | * make sure everything was done. | |
1084 | */ | |
1085 | if (ret == -EINVAL) | |
1086 | ret = 0; | |
2ef7eeaa | 1087 | } else { |
e47c68e9 | 1088 | ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0); |
2ef7eeaa EA |
1089 | } |
1090 | ||
05394f39 | 1091 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 1092 | unlock: |
673a394b EA |
1093 | mutex_unlock(&dev->struct_mutex); |
1094 | return ret; | |
1095 | } | |
1096 | ||
1097 | /** | |
1098 | * Called when user space has done writes to this buffer | |
1099 | */ | |
1100 | int | |
1101 | i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 1102 | struct drm_file *file) |
673a394b EA |
1103 | { |
1104 | struct drm_i915_gem_sw_finish *args = data; | |
05394f39 | 1105 | struct drm_i915_gem_object *obj; |
673a394b EA |
1106 | int ret = 0; |
1107 | ||
1108 | if (!(dev->driver->driver_features & DRIVER_GEM)) | |
1109 | return -ENODEV; | |
1110 | ||
76c1dec1 | 1111 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 1112 | if (ret) |
76c1dec1 | 1113 | return ret; |
1d7cfea1 | 1114 | |
05394f39 | 1115 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 1116 | if (&obj->base == NULL) { |
1d7cfea1 CW |
1117 | ret = -ENOENT; |
1118 | goto unlock; | |
673a394b EA |
1119 | } |
1120 | ||
673a394b | 1121 | /* Pinned buffers may be scanout, so flush the cache */ |
05394f39 | 1122 | if (obj->pin_count) |
e47c68e9 EA |
1123 | i915_gem_object_flush_cpu_write_domain(obj); |
1124 | ||
05394f39 | 1125 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 1126 | unlock: |
673a394b EA |
1127 | mutex_unlock(&dev->struct_mutex); |
1128 | return ret; | |
1129 | } | |
1130 | ||
1131 | /** | |
1132 | * Maps the contents of an object, returning the address it is mapped | |
1133 | * into. | |
1134 | * | |
1135 | * While the mapping holds a reference on the contents of the object, it doesn't | |
1136 | * imply a ref on the object itself. | |
1137 | */ | |
1138 | int | |
1139 | i915_gem_mmap_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 1140 | struct drm_file *file) |
673a394b | 1141 | { |
da761a6e | 1142 | struct drm_i915_private *dev_priv = dev->dev_private; |
673a394b EA |
1143 | struct drm_i915_gem_mmap *args = data; |
1144 | struct drm_gem_object *obj; | |
673a394b EA |
1145 | unsigned long addr; |
1146 | ||
1147 | if (!(dev->driver->driver_features & DRIVER_GEM)) | |
1148 | return -ENODEV; | |
1149 | ||
05394f39 | 1150 | obj = drm_gem_object_lookup(dev, file, args->handle); |
673a394b | 1151 | if (obj == NULL) |
bf79cb91 | 1152 | return -ENOENT; |
673a394b | 1153 | |
da761a6e CW |
1154 | if (obj->size > dev_priv->mm.gtt_mappable_end) { |
1155 | drm_gem_object_unreference_unlocked(obj); | |
1156 | return -E2BIG; | |
1157 | } | |
1158 | ||
673a394b EA |
1159 | down_write(¤t->mm->mmap_sem); |
1160 | addr = do_mmap(obj->filp, 0, args->size, | |
1161 | PROT_READ | PROT_WRITE, MAP_SHARED, | |
1162 | args->offset); | |
1163 | up_write(¤t->mm->mmap_sem); | |
bc9025bd | 1164 | drm_gem_object_unreference_unlocked(obj); |
673a394b EA |
1165 | if (IS_ERR((void *)addr)) |
1166 | return addr; | |
1167 | ||
1168 | args->addr_ptr = (uint64_t) addr; | |
1169 | ||
1170 | return 0; | |
1171 | } | |
1172 | ||
de151cf6 JB |
1173 | /** |
1174 | * i915_gem_fault - fault a page into the GTT | |
1175 | * vma: VMA in question | |
1176 | * vmf: fault info | |
1177 | * | |
1178 | * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped | |
1179 | * from userspace. The fault handler takes care of binding the object to | |
1180 | * the GTT (if needed), allocating and programming a fence register (again, | |
1181 | * only if needed based on whether the old reg is still valid or the object | |
1182 | * is tiled) and inserting a new PTE into the faulting process. | |
1183 | * | |
1184 | * Note that the faulting process may involve evicting existing objects | |
1185 | * from the GTT and/or fence registers to make room. So performance may | |
1186 | * suffer if the GTT working set is large or there are few fence registers | |
1187 | * left. | |
1188 | */ | |
1189 | int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf) | |
1190 | { | |
05394f39 CW |
1191 | struct drm_i915_gem_object *obj = to_intel_bo(vma->vm_private_data); |
1192 | struct drm_device *dev = obj->base.dev; | |
7d1c4804 | 1193 | drm_i915_private_t *dev_priv = dev->dev_private; |
de151cf6 JB |
1194 | pgoff_t page_offset; |
1195 | unsigned long pfn; | |
1196 | int ret = 0; | |
0f973f27 | 1197 | bool write = !!(vmf->flags & FAULT_FLAG_WRITE); |
de151cf6 JB |
1198 | |
1199 | /* We don't use vmf->pgoff since that has the fake offset */ | |
1200 | page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >> | |
1201 | PAGE_SHIFT; | |
1202 | ||
d9bc7e9f CW |
1203 | ret = i915_mutex_lock_interruptible(dev); |
1204 | if (ret) | |
1205 | goto out; | |
a00b10c3 | 1206 | |
db53a302 CW |
1207 | trace_i915_gem_object_fault(obj, page_offset, true, write); |
1208 | ||
d9bc7e9f | 1209 | /* Now bind it into the GTT if needed */ |
919926ae CW |
1210 | if (!obj->map_and_fenceable) { |
1211 | ret = i915_gem_object_unbind(obj); | |
1212 | if (ret) | |
1213 | goto unlock; | |
a00b10c3 | 1214 | } |
05394f39 | 1215 | if (!obj->gtt_space) { |
75e9e915 | 1216 | ret = i915_gem_object_bind_to_gtt(obj, 0, true); |
c715089f CW |
1217 | if (ret) |
1218 | goto unlock; | |
de151cf6 | 1219 | |
e92d03bf EA |
1220 | ret = i915_gem_object_set_to_gtt_domain(obj, write); |
1221 | if (ret) | |
1222 | goto unlock; | |
1223 | } | |
4a684a41 | 1224 | |
d9e86c0e CW |
1225 | if (obj->tiling_mode == I915_TILING_NONE) |
1226 | ret = i915_gem_object_put_fence(obj); | |
1227 | else | |
ce453d81 | 1228 | ret = i915_gem_object_get_fence(obj, NULL); |
d9e86c0e CW |
1229 | if (ret) |
1230 | goto unlock; | |
de151cf6 | 1231 | |
05394f39 CW |
1232 | if (i915_gem_object_is_inactive(obj)) |
1233 | list_move_tail(&obj->mm_list, &dev_priv->mm.inactive_list); | |
7d1c4804 | 1234 | |
6299f992 CW |
1235 | obj->fault_mappable = true; |
1236 | ||
05394f39 | 1237 | pfn = ((dev->agp->base + obj->gtt_offset) >> PAGE_SHIFT) + |
de151cf6 JB |
1238 | page_offset; |
1239 | ||
1240 | /* Finally, remap it using the new GTT offset */ | |
1241 | ret = vm_insert_pfn(vma, (unsigned long)vmf->virtual_address, pfn); | |
c715089f | 1242 | unlock: |
de151cf6 | 1243 | mutex_unlock(&dev->struct_mutex); |
d9bc7e9f | 1244 | out: |
de151cf6 | 1245 | switch (ret) { |
d9bc7e9f | 1246 | case -EIO: |
045e769a | 1247 | case -EAGAIN: |
d9bc7e9f CW |
1248 | /* Give the error handler a chance to run and move the |
1249 | * objects off the GPU active list. Next time we service the | |
1250 | * fault, we should be able to transition the page into the | |
1251 | * GTT without touching the GPU (and so avoid further | |
1252 | * EIO/EGAIN). If the GPU is wedged, then there is no issue | |
1253 | * with coherency, just lost writes. | |
1254 | */ | |
045e769a | 1255 | set_need_resched(); |
c715089f CW |
1256 | case 0: |
1257 | case -ERESTARTSYS: | |
bed636ab | 1258 | case -EINTR: |
c715089f | 1259 | return VM_FAULT_NOPAGE; |
de151cf6 | 1260 | case -ENOMEM: |
de151cf6 | 1261 | return VM_FAULT_OOM; |
de151cf6 | 1262 | default: |
c715089f | 1263 | return VM_FAULT_SIGBUS; |
de151cf6 JB |
1264 | } |
1265 | } | |
1266 | ||
901782b2 CW |
1267 | /** |
1268 | * i915_gem_release_mmap - remove physical page mappings | |
1269 | * @obj: obj in question | |
1270 | * | |
af901ca1 | 1271 | * Preserve the reservation of the mmapping with the DRM core code, but |
901782b2 CW |
1272 | * relinquish ownership of the pages back to the system. |
1273 | * | |
1274 | * It is vital that we remove the page mapping if we have mapped a tiled | |
1275 | * object through the GTT and then lose the fence register due to | |
1276 | * resource pressure. Similarly if the object has been moved out of the | |
1277 | * aperture, than pages mapped into userspace must be revoked. Removing the | |
1278 | * mapping will then trigger a page fault on the next user access, allowing | |
1279 | * fixup by i915_gem_fault(). | |
1280 | */ | |
d05ca301 | 1281 | void |
05394f39 | 1282 | i915_gem_release_mmap(struct drm_i915_gem_object *obj) |
901782b2 | 1283 | { |
6299f992 CW |
1284 | if (!obj->fault_mappable) |
1285 | return; | |
901782b2 | 1286 | |
f6e47884 CW |
1287 | if (obj->base.dev->dev_mapping) |
1288 | unmap_mapping_range(obj->base.dev->dev_mapping, | |
1289 | (loff_t)obj->base.map_list.hash.key<<PAGE_SHIFT, | |
1290 | obj->base.size, 1); | |
fb7d516a | 1291 | |
6299f992 | 1292 | obj->fault_mappable = false; |
901782b2 CW |
1293 | } |
1294 | ||
92b88aeb | 1295 | static uint32_t |
e28f8711 | 1296 | i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode) |
92b88aeb | 1297 | { |
e28f8711 | 1298 | uint32_t gtt_size; |
92b88aeb CW |
1299 | |
1300 | if (INTEL_INFO(dev)->gen >= 4 || | |
e28f8711 CW |
1301 | tiling_mode == I915_TILING_NONE) |
1302 | return size; | |
92b88aeb CW |
1303 | |
1304 | /* Previous chips need a power-of-two fence region when tiling */ | |
1305 | if (INTEL_INFO(dev)->gen == 3) | |
e28f8711 | 1306 | gtt_size = 1024*1024; |
92b88aeb | 1307 | else |
e28f8711 | 1308 | gtt_size = 512*1024; |
92b88aeb | 1309 | |
e28f8711 CW |
1310 | while (gtt_size < size) |
1311 | gtt_size <<= 1; | |
92b88aeb | 1312 | |
e28f8711 | 1313 | return gtt_size; |
92b88aeb CW |
1314 | } |
1315 | ||
de151cf6 JB |
1316 | /** |
1317 | * i915_gem_get_gtt_alignment - return required GTT alignment for an object | |
1318 | * @obj: object to check | |
1319 | * | |
1320 | * Return the required GTT alignment for an object, taking into account | |
5e783301 | 1321 | * potential fence register mapping. |
de151cf6 JB |
1322 | */ |
1323 | static uint32_t | |
e28f8711 CW |
1324 | i915_gem_get_gtt_alignment(struct drm_device *dev, |
1325 | uint32_t size, | |
1326 | int tiling_mode) | |
de151cf6 | 1327 | { |
de151cf6 JB |
1328 | /* |
1329 | * Minimum alignment is 4k (GTT page size), but might be greater | |
1330 | * if a fence register is needed for the object. | |
1331 | */ | |
a00b10c3 | 1332 | if (INTEL_INFO(dev)->gen >= 4 || |
e28f8711 | 1333 | tiling_mode == I915_TILING_NONE) |
de151cf6 JB |
1334 | return 4096; |
1335 | ||
a00b10c3 CW |
1336 | /* |
1337 | * Previous chips need to be aligned to the size of the smallest | |
1338 | * fence register that can contain the object. | |
1339 | */ | |
e28f8711 | 1340 | return i915_gem_get_gtt_size(dev, size, tiling_mode); |
a00b10c3 CW |
1341 | } |
1342 | ||
5e783301 DV |
1343 | /** |
1344 | * i915_gem_get_unfenced_gtt_alignment - return required GTT alignment for an | |
1345 | * unfenced object | |
e28f8711 CW |
1346 | * @dev: the device |
1347 | * @size: size of the object | |
1348 | * @tiling_mode: tiling mode of the object | |
5e783301 DV |
1349 | * |
1350 | * Return the required GTT alignment for an object, only taking into account | |
1351 | * unfenced tiled surface requirements. | |
1352 | */ | |
467cffba | 1353 | uint32_t |
e28f8711 CW |
1354 | i915_gem_get_unfenced_gtt_alignment(struct drm_device *dev, |
1355 | uint32_t size, | |
1356 | int tiling_mode) | |
5e783301 | 1357 | { |
5e783301 DV |
1358 | /* |
1359 | * Minimum alignment is 4k (GTT page size) for sane hw. | |
1360 | */ | |
1361 | if (INTEL_INFO(dev)->gen >= 4 || IS_G33(dev) || | |
e28f8711 | 1362 | tiling_mode == I915_TILING_NONE) |
5e783301 DV |
1363 | return 4096; |
1364 | ||
e28f8711 CW |
1365 | /* Previous hardware however needs to be aligned to a power-of-two |
1366 | * tile height. The simplest method for determining this is to reuse | |
1367 | * the power-of-tile object size. | |
5e783301 | 1368 | */ |
e28f8711 | 1369 | return i915_gem_get_gtt_size(dev, size, tiling_mode); |
5e783301 DV |
1370 | } |
1371 | ||
de151cf6 | 1372 | int |
ff72145b DA |
1373 | i915_gem_mmap_gtt(struct drm_file *file, |
1374 | struct drm_device *dev, | |
1375 | uint32_t handle, | |
1376 | uint64_t *offset) | |
de151cf6 | 1377 | { |
da761a6e | 1378 | struct drm_i915_private *dev_priv = dev->dev_private; |
05394f39 | 1379 | struct drm_i915_gem_object *obj; |
de151cf6 JB |
1380 | int ret; |
1381 | ||
1382 | if (!(dev->driver->driver_features & DRIVER_GEM)) | |
1383 | return -ENODEV; | |
1384 | ||
76c1dec1 | 1385 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 1386 | if (ret) |
76c1dec1 | 1387 | return ret; |
de151cf6 | 1388 | |
ff72145b | 1389 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle)); |
c8725226 | 1390 | if (&obj->base == NULL) { |
1d7cfea1 CW |
1391 | ret = -ENOENT; |
1392 | goto unlock; | |
1393 | } | |
de151cf6 | 1394 | |
05394f39 | 1395 | if (obj->base.size > dev_priv->mm.gtt_mappable_end) { |
da761a6e CW |
1396 | ret = -E2BIG; |
1397 | goto unlock; | |
1398 | } | |
1399 | ||
05394f39 | 1400 | if (obj->madv != I915_MADV_WILLNEED) { |
ab18282d | 1401 | DRM_ERROR("Attempting to mmap a purgeable buffer\n"); |
1d7cfea1 CW |
1402 | ret = -EINVAL; |
1403 | goto out; | |
ab18282d CW |
1404 | } |
1405 | ||
05394f39 | 1406 | if (!obj->base.map_list.map) { |
b464e9a2 | 1407 | ret = drm_gem_create_mmap_offset(&obj->base); |
1d7cfea1 CW |
1408 | if (ret) |
1409 | goto out; | |
de151cf6 JB |
1410 | } |
1411 | ||
ff72145b | 1412 | *offset = (u64)obj->base.map_list.hash.key << PAGE_SHIFT; |
de151cf6 | 1413 | |
1d7cfea1 | 1414 | out: |
05394f39 | 1415 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 1416 | unlock: |
de151cf6 | 1417 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 1418 | return ret; |
de151cf6 JB |
1419 | } |
1420 | ||
ff72145b DA |
1421 | /** |
1422 | * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing | |
1423 | * @dev: DRM device | |
1424 | * @data: GTT mapping ioctl data | |
1425 | * @file: GEM object info | |
1426 | * | |
1427 | * Simply returns the fake offset to userspace so it can mmap it. | |
1428 | * The mmap call will end up in drm_gem_mmap(), which will set things | |
1429 | * up so we can get faults in the handler above. | |
1430 | * | |
1431 | * The fault handler will take care of binding the object into the GTT | |
1432 | * (since it may have been evicted to make room for something), allocating | |
1433 | * a fence register, and mapping the appropriate aperture address into | |
1434 | * userspace. | |
1435 | */ | |
1436 | int | |
1437 | i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data, | |
1438 | struct drm_file *file) | |
1439 | { | |
1440 | struct drm_i915_gem_mmap_gtt *args = data; | |
1441 | ||
1442 | if (!(dev->driver->driver_features & DRIVER_GEM)) | |
1443 | return -ENODEV; | |
1444 | ||
1445 | return i915_gem_mmap_gtt(file, dev, args->handle, &args->offset); | |
1446 | } | |
1447 | ||
1448 | ||
e5281ccd | 1449 | static int |
05394f39 | 1450 | i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj, |
e5281ccd CW |
1451 | gfp_t gfpmask) |
1452 | { | |
e5281ccd CW |
1453 | int page_count, i; |
1454 | struct address_space *mapping; | |
1455 | struct inode *inode; | |
1456 | struct page *page; | |
1457 | ||
1458 | /* Get the list of pages out of our struct file. They'll be pinned | |
1459 | * at this point until we release them. | |
1460 | */ | |
05394f39 CW |
1461 | page_count = obj->base.size / PAGE_SIZE; |
1462 | BUG_ON(obj->pages != NULL); | |
1463 | obj->pages = drm_malloc_ab(page_count, sizeof(struct page *)); | |
1464 | if (obj->pages == NULL) | |
e5281ccd CW |
1465 | return -ENOMEM; |
1466 | ||
05394f39 | 1467 | inode = obj->base.filp->f_path.dentry->d_inode; |
e5281ccd | 1468 | mapping = inode->i_mapping; |
5949eac4 HD |
1469 | gfpmask |= mapping_gfp_mask(mapping); |
1470 | ||
e5281ccd | 1471 | for (i = 0; i < page_count; i++) { |
5949eac4 | 1472 | page = shmem_read_mapping_page_gfp(mapping, i, gfpmask); |
e5281ccd CW |
1473 | if (IS_ERR(page)) |
1474 | goto err_pages; | |
1475 | ||
05394f39 | 1476 | obj->pages[i] = page; |
e5281ccd CW |
1477 | } |
1478 | ||
6dacfd2f | 1479 | if (i915_gem_object_needs_bit17_swizzle(obj)) |
e5281ccd CW |
1480 | i915_gem_object_do_bit_17_swizzle(obj); |
1481 | ||
1482 | return 0; | |
1483 | ||
1484 | err_pages: | |
1485 | while (i--) | |
05394f39 | 1486 | page_cache_release(obj->pages[i]); |
e5281ccd | 1487 | |
05394f39 CW |
1488 | drm_free_large(obj->pages); |
1489 | obj->pages = NULL; | |
e5281ccd CW |
1490 | return PTR_ERR(page); |
1491 | } | |
1492 | ||
5cdf5881 | 1493 | static void |
05394f39 | 1494 | i915_gem_object_put_pages_gtt(struct drm_i915_gem_object *obj) |
673a394b | 1495 | { |
05394f39 | 1496 | int page_count = obj->base.size / PAGE_SIZE; |
673a394b EA |
1497 | int i; |
1498 | ||
05394f39 | 1499 | BUG_ON(obj->madv == __I915_MADV_PURGED); |
673a394b | 1500 | |
6dacfd2f | 1501 | if (i915_gem_object_needs_bit17_swizzle(obj)) |
280b713b EA |
1502 | i915_gem_object_save_bit_17_swizzle(obj); |
1503 | ||
05394f39 CW |
1504 | if (obj->madv == I915_MADV_DONTNEED) |
1505 | obj->dirty = 0; | |
3ef94daa CW |
1506 | |
1507 | for (i = 0; i < page_count; i++) { | |
05394f39 CW |
1508 | if (obj->dirty) |
1509 | set_page_dirty(obj->pages[i]); | |
3ef94daa | 1510 | |
05394f39 CW |
1511 | if (obj->madv == I915_MADV_WILLNEED) |
1512 | mark_page_accessed(obj->pages[i]); | |
3ef94daa | 1513 | |
05394f39 | 1514 | page_cache_release(obj->pages[i]); |
3ef94daa | 1515 | } |
05394f39 | 1516 | obj->dirty = 0; |
673a394b | 1517 | |
05394f39 CW |
1518 | drm_free_large(obj->pages); |
1519 | obj->pages = NULL; | |
673a394b EA |
1520 | } |
1521 | ||
54cf91dc | 1522 | void |
05394f39 | 1523 | i915_gem_object_move_to_active(struct drm_i915_gem_object *obj, |
1ec14ad3 CW |
1524 | struct intel_ring_buffer *ring, |
1525 | u32 seqno) | |
673a394b | 1526 | { |
05394f39 | 1527 | struct drm_device *dev = obj->base.dev; |
69dc4987 | 1528 | struct drm_i915_private *dev_priv = dev->dev_private; |
617dbe27 | 1529 | |
852835f3 | 1530 | BUG_ON(ring == NULL); |
05394f39 | 1531 | obj->ring = ring; |
673a394b EA |
1532 | |
1533 | /* Add a reference if we're newly entering the active list. */ | |
05394f39 CW |
1534 | if (!obj->active) { |
1535 | drm_gem_object_reference(&obj->base); | |
1536 | obj->active = 1; | |
673a394b | 1537 | } |
e35a41de | 1538 | |
673a394b | 1539 | /* Move from whatever list we were on to the tail of execution. */ |
05394f39 CW |
1540 | list_move_tail(&obj->mm_list, &dev_priv->mm.active_list); |
1541 | list_move_tail(&obj->ring_list, &ring->active_list); | |
caea7476 | 1542 | |
05394f39 | 1543 | obj->last_rendering_seqno = seqno; |
caea7476 CW |
1544 | if (obj->fenced_gpu_access) { |
1545 | struct drm_i915_fence_reg *reg; | |
1546 | ||
1547 | BUG_ON(obj->fence_reg == I915_FENCE_REG_NONE); | |
1548 | ||
1549 | obj->last_fenced_seqno = seqno; | |
1550 | obj->last_fenced_ring = ring; | |
1551 | ||
1552 | reg = &dev_priv->fence_regs[obj->fence_reg]; | |
1553 | list_move_tail(®->lru_list, &dev_priv->mm.fence_list); | |
1554 | } | |
1555 | } | |
1556 | ||
1557 | static void | |
1558 | i915_gem_object_move_off_active(struct drm_i915_gem_object *obj) | |
1559 | { | |
1560 | list_del_init(&obj->ring_list); | |
1561 | obj->last_rendering_seqno = 0; | |
673a394b EA |
1562 | } |
1563 | ||
ce44b0ea | 1564 | static void |
05394f39 | 1565 | i915_gem_object_move_to_flushing(struct drm_i915_gem_object *obj) |
ce44b0ea | 1566 | { |
05394f39 | 1567 | struct drm_device *dev = obj->base.dev; |
ce44b0ea | 1568 | drm_i915_private_t *dev_priv = dev->dev_private; |
ce44b0ea | 1569 | |
05394f39 CW |
1570 | BUG_ON(!obj->active); |
1571 | list_move_tail(&obj->mm_list, &dev_priv->mm.flushing_list); | |
caea7476 CW |
1572 | |
1573 | i915_gem_object_move_off_active(obj); | |
1574 | } | |
1575 | ||
1576 | static void | |
1577 | i915_gem_object_move_to_inactive(struct drm_i915_gem_object *obj) | |
1578 | { | |
1579 | struct drm_device *dev = obj->base.dev; | |
1580 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1581 | ||
1582 | if (obj->pin_count != 0) | |
1583 | list_move_tail(&obj->mm_list, &dev_priv->mm.pinned_list); | |
1584 | else | |
1585 | list_move_tail(&obj->mm_list, &dev_priv->mm.inactive_list); | |
1586 | ||
1587 | BUG_ON(!list_empty(&obj->gpu_write_list)); | |
1588 | BUG_ON(!obj->active); | |
1589 | obj->ring = NULL; | |
1590 | ||
1591 | i915_gem_object_move_off_active(obj); | |
1592 | obj->fenced_gpu_access = false; | |
caea7476 CW |
1593 | |
1594 | obj->active = 0; | |
87ca9c8a | 1595 | obj->pending_gpu_write = false; |
caea7476 CW |
1596 | drm_gem_object_unreference(&obj->base); |
1597 | ||
1598 | WARN_ON(i915_verify_lists(dev)); | |
ce44b0ea | 1599 | } |
673a394b | 1600 | |
963b4836 CW |
1601 | /* Immediately discard the backing storage */ |
1602 | static void | |
05394f39 | 1603 | i915_gem_object_truncate(struct drm_i915_gem_object *obj) |
963b4836 | 1604 | { |
bb6baf76 | 1605 | struct inode *inode; |
963b4836 | 1606 | |
ae9fed6b CW |
1607 | /* Our goal here is to return as much of the memory as |
1608 | * is possible back to the system as we are called from OOM. | |
1609 | * To do this we must instruct the shmfs to drop all of its | |
e2377fe0 | 1610 | * backing pages, *now*. |
ae9fed6b | 1611 | */ |
05394f39 | 1612 | inode = obj->base.filp->f_path.dentry->d_inode; |
e2377fe0 | 1613 | shmem_truncate_range(inode, 0, (loff_t)-1); |
bb6baf76 | 1614 | |
05394f39 | 1615 | obj->madv = __I915_MADV_PURGED; |
963b4836 CW |
1616 | } |
1617 | ||
1618 | static inline int | |
05394f39 | 1619 | i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj) |
963b4836 | 1620 | { |
05394f39 | 1621 | return obj->madv == I915_MADV_DONTNEED; |
963b4836 CW |
1622 | } |
1623 | ||
63560396 | 1624 | static void |
db53a302 CW |
1625 | i915_gem_process_flushing_list(struct intel_ring_buffer *ring, |
1626 | uint32_t flush_domains) | |
63560396 | 1627 | { |
05394f39 | 1628 | struct drm_i915_gem_object *obj, *next; |
63560396 | 1629 | |
05394f39 | 1630 | list_for_each_entry_safe(obj, next, |
64193406 | 1631 | &ring->gpu_write_list, |
63560396 | 1632 | gpu_write_list) { |
05394f39 CW |
1633 | if (obj->base.write_domain & flush_domains) { |
1634 | uint32_t old_write_domain = obj->base.write_domain; | |
63560396 | 1635 | |
05394f39 CW |
1636 | obj->base.write_domain = 0; |
1637 | list_del_init(&obj->gpu_write_list); | |
1ec14ad3 | 1638 | i915_gem_object_move_to_active(obj, ring, |
db53a302 | 1639 | i915_gem_next_request_seqno(ring)); |
63560396 | 1640 | |
63560396 | 1641 | trace_i915_gem_object_change_domain(obj, |
05394f39 | 1642 | obj->base.read_domains, |
63560396 DV |
1643 | old_write_domain); |
1644 | } | |
1645 | } | |
1646 | } | |
8187a2b7 | 1647 | |
3cce469c | 1648 | int |
db53a302 | 1649 | i915_add_request(struct intel_ring_buffer *ring, |
f787a5f5 | 1650 | struct drm_file *file, |
db53a302 | 1651 | struct drm_i915_gem_request *request) |
673a394b | 1652 | { |
db53a302 | 1653 | drm_i915_private_t *dev_priv = ring->dev->dev_private; |
673a394b EA |
1654 | uint32_t seqno; |
1655 | int was_empty; | |
3cce469c CW |
1656 | int ret; |
1657 | ||
1658 | BUG_ON(request == NULL); | |
673a394b | 1659 | |
3cce469c CW |
1660 | ret = ring->add_request(ring, &seqno); |
1661 | if (ret) | |
1662 | return ret; | |
673a394b | 1663 | |
db53a302 | 1664 | trace_i915_gem_request_add(ring, seqno); |
673a394b EA |
1665 | |
1666 | request->seqno = seqno; | |
852835f3 | 1667 | request->ring = ring; |
673a394b | 1668 | request->emitted_jiffies = jiffies; |
852835f3 ZN |
1669 | was_empty = list_empty(&ring->request_list); |
1670 | list_add_tail(&request->list, &ring->request_list); | |
1671 | ||
db53a302 CW |
1672 | if (file) { |
1673 | struct drm_i915_file_private *file_priv = file->driver_priv; | |
1674 | ||
1c25595f | 1675 | spin_lock(&file_priv->mm.lock); |
f787a5f5 | 1676 | request->file_priv = file_priv; |
b962442e | 1677 | list_add_tail(&request->client_list, |
f787a5f5 | 1678 | &file_priv->mm.request_list); |
1c25595f | 1679 | spin_unlock(&file_priv->mm.lock); |
b962442e | 1680 | } |
673a394b | 1681 | |
db53a302 CW |
1682 | ring->outstanding_lazy_request = false; |
1683 | ||
f65d9421 | 1684 | if (!dev_priv->mm.suspended) { |
3e0dc6b0 BW |
1685 | if (i915_enable_hangcheck) { |
1686 | mod_timer(&dev_priv->hangcheck_timer, | |
1687 | jiffies + | |
1688 | msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)); | |
1689 | } | |
f65d9421 | 1690 | if (was_empty) |
b3b079db CW |
1691 | queue_delayed_work(dev_priv->wq, |
1692 | &dev_priv->mm.retire_work, HZ); | |
f65d9421 | 1693 | } |
3cce469c | 1694 | return 0; |
673a394b EA |
1695 | } |
1696 | ||
f787a5f5 CW |
1697 | static inline void |
1698 | i915_gem_request_remove_from_client(struct drm_i915_gem_request *request) | |
673a394b | 1699 | { |
1c25595f | 1700 | struct drm_i915_file_private *file_priv = request->file_priv; |
673a394b | 1701 | |
1c25595f CW |
1702 | if (!file_priv) |
1703 | return; | |
1c5d22f7 | 1704 | |
1c25595f | 1705 | spin_lock(&file_priv->mm.lock); |
09bfa517 HRK |
1706 | if (request->file_priv) { |
1707 | list_del(&request->client_list); | |
1708 | request->file_priv = NULL; | |
1709 | } | |
1c25595f | 1710 | spin_unlock(&file_priv->mm.lock); |
673a394b | 1711 | } |
673a394b | 1712 | |
dfaae392 CW |
1713 | static void i915_gem_reset_ring_lists(struct drm_i915_private *dev_priv, |
1714 | struct intel_ring_buffer *ring) | |
9375e446 | 1715 | { |
dfaae392 CW |
1716 | while (!list_empty(&ring->request_list)) { |
1717 | struct drm_i915_gem_request *request; | |
673a394b | 1718 | |
dfaae392 CW |
1719 | request = list_first_entry(&ring->request_list, |
1720 | struct drm_i915_gem_request, | |
1721 | list); | |
de151cf6 | 1722 | |
dfaae392 | 1723 | list_del(&request->list); |
f787a5f5 | 1724 | i915_gem_request_remove_from_client(request); |
dfaae392 CW |
1725 | kfree(request); |
1726 | } | |
673a394b | 1727 | |
dfaae392 | 1728 | while (!list_empty(&ring->active_list)) { |
05394f39 | 1729 | struct drm_i915_gem_object *obj; |
9375e446 | 1730 | |
05394f39 CW |
1731 | obj = list_first_entry(&ring->active_list, |
1732 | struct drm_i915_gem_object, | |
1733 | ring_list); | |
9375e446 | 1734 | |
05394f39 CW |
1735 | obj->base.write_domain = 0; |
1736 | list_del_init(&obj->gpu_write_list); | |
1737 | i915_gem_object_move_to_inactive(obj); | |
673a394b EA |
1738 | } |
1739 | } | |
1740 | ||
312817a3 CW |
1741 | static void i915_gem_reset_fences(struct drm_device *dev) |
1742 | { | |
1743 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1744 | int i; | |
1745 | ||
1746 | for (i = 0; i < 16; i++) { | |
1747 | struct drm_i915_fence_reg *reg = &dev_priv->fence_regs[i]; | |
7d2cb39c CW |
1748 | struct drm_i915_gem_object *obj = reg->obj; |
1749 | ||
1750 | if (!obj) | |
1751 | continue; | |
1752 | ||
1753 | if (obj->tiling_mode) | |
1754 | i915_gem_release_mmap(obj); | |
1755 | ||
d9e86c0e CW |
1756 | reg->obj->fence_reg = I915_FENCE_REG_NONE; |
1757 | reg->obj->fenced_gpu_access = false; | |
1758 | reg->obj->last_fenced_seqno = 0; | |
1759 | reg->obj->last_fenced_ring = NULL; | |
1760 | i915_gem_clear_fence_reg(dev, reg); | |
312817a3 CW |
1761 | } |
1762 | } | |
1763 | ||
069efc1d | 1764 | void i915_gem_reset(struct drm_device *dev) |
673a394b | 1765 | { |
77f01230 | 1766 | struct drm_i915_private *dev_priv = dev->dev_private; |
05394f39 | 1767 | struct drm_i915_gem_object *obj; |
1ec14ad3 | 1768 | int i; |
673a394b | 1769 | |
1ec14ad3 CW |
1770 | for (i = 0; i < I915_NUM_RINGS; i++) |
1771 | i915_gem_reset_ring_lists(dev_priv, &dev_priv->ring[i]); | |
dfaae392 CW |
1772 | |
1773 | /* Remove anything from the flushing lists. The GPU cache is likely | |
1774 | * to be lost on reset along with the data, so simply move the | |
1775 | * lost bo to the inactive list. | |
1776 | */ | |
1777 | while (!list_empty(&dev_priv->mm.flushing_list)) { | |
0206e353 | 1778 | obj = list_first_entry(&dev_priv->mm.flushing_list, |
05394f39 CW |
1779 | struct drm_i915_gem_object, |
1780 | mm_list); | |
dfaae392 | 1781 | |
05394f39 CW |
1782 | obj->base.write_domain = 0; |
1783 | list_del_init(&obj->gpu_write_list); | |
1784 | i915_gem_object_move_to_inactive(obj); | |
dfaae392 CW |
1785 | } |
1786 | ||
1787 | /* Move everything out of the GPU domains to ensure we do any | |
1788 | * necessary invalidation upon reuse. | |
1789 | */ | |
05394f39 | 1790 | list_for_each_entry(obj, |
77f01230 | 1791 | &dev_priv->mm.inactive_list, |
69dc4987 | 1792 | mm_list) |
77f01230 | 1793 | { |
05394f39 | 1794 | obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS; |
77f01230 | 1795 | } |
069efc1d CW |
1796 | |
1797 | /* The fence registers are invalidated so clear them out */ | |
312817a3 | 1798 | i915_gem_reset_fences(dev); |
673a394b EA |
1799 | } |
1800 | ||
1801 | /** | |
1802 | * This function clears the request list as sequence numbers are passed. | |
1803 | */ | |
b09a1fec | 1804 | static void |
db53a302 | 1805 | i915_gem_retire_requests_ring(struct intel_ring_buffer *ring) |
673a394b | 1806 | { |
673a394b | 1807 | uint32_t seqno; |
1ec14ad3 | 1808 | int i; |
673a394b | 1809 | |
db53a302 | 1810 | if (list_empty(&ring->request_list)) |
6c0594a3 KW |
1811 | return; |
1812 | ||
db53a302 | 1813 | WARN_ON(i915_verify_lists(ring->dev)); |
673a394b | 1814 | |
78501eac | 1815 | seqno = ring->get_seqno(ring); |
1ec14ad3 | 1816 | |
076e2c0e | 1817 | for (i = 0; i < ARRAY_SIZE(ring->sync_seqno); i++) |
1ec14ad3 CW |
1818 | if (seqno >= ring->sync_seqno[i]) |
1819 | ring->sync_seqno[i] = 0; | |
1820 | ||
852835f3 | 1821 | while (!list_empty(&ring->request_list)) { |
673a394b | 1822 | struct drm_i915_gem_request *request; |
673a394b | 1823 | |
852835f3 | 1824 | request = list_first_entry(&ring->request_list, |
673a394b EA |
1825 | struct drm_i915_gem_request, |
1826 | list); | |
673a394b | 1827 | |
dfaae392 | 1828 | if (!i915_seqno_passed(seqno, request->seqno)) |
b84d5f0c CW |
1829 | break; |
1830 | ||
db53a302 | 1831 | trace_i915_gem_request_retire(ring, request->seqno); |
b84d5f0c CW |
1832 | |
1833 | list_del(&request->list); | |
f787a5f5 | 1834 | i915_gem_request_remove_from_client(request); |
b84d5f0c CW |
1835 | kfree(request); |
1836 | } | |
673a394b | 1837 | |
b84d5f0c CW |
1838 | /* Move any buffers on the active list that are no longer referenced |
1839 | * by the ringbuffer to the flushing/inactive lists as appropriate. | |
1840 | */ | |
1841 | while (!list_empty(&ring->active_list)) { | |
05394f39 | 1842 | struct drm_i915_gem_object *obj; |
b84d5f0c | 1843 | |
0206e353 | 1844 | obj = list_first_entry(&ring->active_list, |
05394f39 CW |
1845 | struct drm_i915_gem_object, |
1846 | ring_list); | |
673a394b | 1847 | |
05394f39 | 1848 | if (!i915_seqno_passed(seqno, obj->last_rendering_seqno)) |
673a394b | 1849 | break; |
b84d5f0c | 1850 | |
05394f39 | 1851 | if (obj->base.write_domain != 0) |
b84d5f0c CW |
1852 | i915_gem_object_move_to_flushing(obj); |
1853 | else | |
1854 | i915_gem_object_move_to_inactive(obj); | |
673a394b | 1855 | } |
9d34e5db | 1856 | |
db53a302 CW |
1857 | if (unlikely(ring->trace_irq_seqno && |
1858 | i915_seqno_passed(seqno, ring->trace_irq_seqno))) { | |
1ec14ad3 | 1859 | ring->irq_put(ring); |
db53a302 | 1860 | ring->trace_irq_seqno = 0; |
9d34e5db | 1861 | } |
23bc5982 | 1862 | |
db53a302 | 1863 | WARN_ON(i915_verify_lists(ring->dev)); |
673a394b EA |
1864 | } |
1865 | ||
b09a1fec CW |
1866 | void |
1867 | i915_gem_retire_requests(struct drm_device *dev) | |
1868 | { | |
1869 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1ec14ad3 | 1870 | int i; |
b09a1fec | 1871 | |
be72615b | 1872 | if (!list_empty(&dev_priv->mm.deferred_free_list)) { |
05394f39 | 1873 | struct drm_i915_gem_object *obj, *next; |
be72615b CW |
1874 | |
1875 | /* We must be careful that during unbind() we do not | |
1876 | * accidentally infinitely recurse into retire requests. | |
1877 | * Currently: | |
1878 | * retire -> free -> unbind -> wait -> retire_ring | |
1879 | */ | |
05394f39 | 1880 | list_for_each_entry_safe(obj, next, |
be72615b | 1881 | &dev_priv->mm.deferred_free_list, |
69dc4987 | 1882 | mm_list) |
05394f39 | 1883 | i915_gem_free_object_tail(obj); |
be72615b CW |
1884 | } |
1885 | ||
1ec14ad3 | 1886 | for (i = 0; i < I915_NUM_RINGS; i++) |
db53a302 | 1887 | i915_gem_retire_requests_ring(&dev_priv->ring[i]); |
b09a1fec CW |
1888 | } |
1889 | ||
75ef9da2 | 1890 | static void |
673a394b EA |
1891 | i915_gem_retire_work_handler(struct work_struct *work) |
1892 | { | |
1893 | drm_i915_private_t *dev_priv; | |
1894 | struct drm_device *dev; | |
0a58705b CW |
1895 | bool idle; |
1896 | int i; | |
673a394b EA |
1897 | |
1898 | dev_priv = container_of(work, drm_i915_private_t, | |
1899 | mm.retire_work.work); | |
1900 | dev = dev_priv->dev; | |
1901 | ||
891b48cf CW |
1902 | /* Come back later if the device is busy... */ |
1903 | if (!mutex_trylock(&dev->struct_mutex)) { | |
1904 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ); | |
1905 | return; | |
1906 | } | |
1907 | ||
b09a1fec | 1908 | i915_gem_retire_requests(dev); |
d1b851fc | 1909 | |
0a58705b CW |
1910 | /* Send a periodic flush down the ring so we don't hold onto GEM |
1911 | * objects indefinitely. | |
1912 | */ | |
1913 | idle = true; | |
1914 | for (i = 0; i < I915_NUM_RINGS; i++) { | |
1915 | struct intel_ring_buffer *ring = &dev_priv->ring[i]; | |
1916 | ||
1917 | if (!list_empty(&ring->gpu_write_list)) { | |
1918 | struct drm_i915_gem_request *request; | |
1919 | int ret; | |
1920 | ||
db53a302 CW |
1921 | ret = i915_gem_flush_ring(ring, |
1922 | 0, I915_GEM_GPU_DOMAINS); | |
0a58705b CW |
1923 | request = kzalloc(sizeof(*request), GFP_KERNEL); |
1924 | if (ret || request == NULL || | |
db53a302 | 1925 | i915_add_request(ring, NULL, request)) |
0a58705b CW |
1926 | kfree(request); |
1927 | } | |
1928 | ||
1929 | idle &= list_empty(&ring->request_list); | |
1930 | } | |
1931 | ||
1932 | if (!dev_priv->mm.suspended && !idle) | |
9c9fe1f8 | 1933 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ); |
0a58705b | 1934 | |
673a394b EA |
1935 | mutex_unlock(&dev->struct_mutex); |
1936 | } | |
1937 | ||
db53a302 CW |
1938 | /** |
1939 | * Waits for a sequence number to be signaled, and cleans up the | |
1940 | * request and object lists appropriately for that event. | |
1941 | */ | |
5a5a0c64 | 1942 | int |
db53a302 | 1943 | i915_wait_request(struct intel_ring_buffer *ring, |
ce453d81 | 1944 | uint32_t seqno) |
673a394b | 1945 | { |
db53a302 | 1946 | drm_i915_private_t *dev_priv = ring->dev->dev_private; |
802c7eb6 | 1947 | u32 ier; |
673a394b EA |
1948 | int ret = 0; |
1949 | ||
1950 | BUG_ON(seqno == 0); | |
1951 | ||
d9bc7e9f CW |
1952 | if (atomic_read(&dev_priv->mm.wedged)) { |
1953 | struct completion *x = &dev_priv->error_completion; | |
1954 | bool recovery_complete; | |
1955 | unsigned long flags; | |
1956 | ||
1957 | /* Give the error handler a chance to run. */ | |
1958 | spin_lock_irqsave(&x->wait.lock, flags); | |
1959 | recovery_complete = x->done > 0; | |
1960 | spin_unlock_irqrestore(&x->wait.lock, flags); | |
1961 | ||
1962 | return recovery_complete ? -EIO : -EAGAIN; | |
1963 | } | |
30dbf0c0 | 1964 | |
5d97eb69 | 1965 | if (seqno == ring->outstanding_lazy_request) { |
3cce469c CW |
1966 | struct drm_i915_gem_request *request; |
1967 | ||
1968 | request = kzalloc(sizeof(*request), GFP_KERNEL); | |
1969 | if (request == NULL) | |
e35a41de | 1970 | return -ENOMEM; |
3cce469c | 1971 | |
db53a302 | 1972 | ret = i915_add_request(ring, NULL, request); |
3cce469c CW |
1973 | if (ret) { |
1974 | kfree(request); | |
1975 | return ret; | |
1976 | } | |
1977 | ||
1978 | seqno = request->seqno; | |
e35a41de | 1979 | } |
ffed1d09 | 1980 | |
78501eac | 1981 | if (!i915_seqno_passed(ring->get_seqno(ring), seqno)) { |
db53a302 | 1982 | if (HAS_PCH_SPLIT(ring->dev)) |
036a4a7d ZW |
1983 | ier = I915_READ(DEIER) | I915_READ(GTIER); |
1984 | else | |
1985 | ier = I915_READ(IER); | |
802c7eb6 JB |
1986 | if (!ier) { |
1987 | DRM_ERROR("something (likely vbetool) disabled " | |
1988 | "interrupts, re-enabling\n"); | |
f01c22fd CW |
1989 | ring->dev->driver->irq_preinstall(ring->dev); |
1990 | ring->dev->driver->irq_postinstall(ring->dev); | |
802c7eb6 JB |
1991 | } |
1992 | ||
db53a302 | 1993 | trace_i915_gem_request_wait_begin(ring, seqno); |
1c5d22f7 | 1994 | |
b2223497 | 1995 | ring->waiting_seqno = seqno; |
b13c2b96 | 1996 | if (ring->irq_get(ring)) { |
ce453d81 | 1997 | if (dev_priv->mm.interruptible) |
b13c2b96 CW |
1998 | ret = wait_event_interruptible(ring->irq_queue, |
1999 | i915_seqno_passed(ring->get_seqno(ring), seqno) | |
2000 | || atomic_read(&dev_priv->mm.wedged)); | |
2001 | else | |
2002 | wait_event(ring->irq_queue, | |
2003 | i915_seqno_passed(ring->get_seqno(ring), seqno) | |
2004 | || atomic_read(&dev_priv->mm.wedged)); | |
2005 | ||
2006 | ring->irq_put(ring); | |
b5ba177d CW |
2007 | } else if (wait_for(i915_seqno_passed(ring->get_seqno(ring), |
2008 | seqno) || | |
2009 | atomic_read(&dev_priv->mm.wedged), 3000)) | |
2010 | ret = -EBUSY; | |
b2223497 | 2011 | ring->waiting_seqno = 0; |
1c5d22f7 | 2012 | |
db53a302 | 2013 | trace_i915_gem_request_wait_end(ring, seqno); |
673a394b | 2014 | } |
ba1234d1 | 2015 | if (atomic_read(&dev_priv->mm.wedged)) |
30dbf0c0 | 2016 | ret = -EAGAIN; |
673a394b EA |
2017 | |
2018 | if (ret && ret != -ERESTARTSYS) | |
8bff917c | 2019 | DRM_ERROR("%s returns %d (awaiting %d at %d, next %d)\n", |
78501eac | 2020 | __func__, ret, seqno, ring->get_seqno(ring), |
8bff917c | 2021 | dev_priv->next_seqno); |
673a394b EA |
2022 | |
2023 | /* Directly dispatch request retiring. While we have the work queue | |
2024 | * to handle this, the waiter on a request often wants an associated | |
2025 | * buffer to have made it to the inactive list, and we would need | |
2026 | * a separate wait queue to handle that. | |
2027 | */ | |
2028 | if (ret == 0) | |
db53a302 | 2029 | i915_gem_retire_requests_ring(ring); |
673a394b EA |
2030 | |
2031 | return ret; | |
2032 | } | |
2033 | ||
673a394b EA |
2034 | /** |
2035 | * Ensures that all rendering to the object has completed and the object is | |
2036 | * safe to unbind from the GTT or access from the CPU. | |
2037 | */ | |
54cf91dc | 2038 | int |
ce453d81 | 2039 | i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj) |
673a394b | 2040 | { |
673a394b EA |
2041 | int ret; |
2042 | ||
e47c68e9 EA |
2043 | /* This function only exists to support waiting for existing rendering, |
2044 | * not for emitting required flushes. | |
673a394b | 2045 | */ |
05394f39 | 2046 | BUG_ON((obj->base.write_domain & I915_GEM_GPU_DOMAINS) != 0); |
673a394b EA |
2047 | |
2048 | /* If there is rendering queued on the buffer being evicted, wait for | |
2049 | * it. | |
2050 | */ | |
05394f39 | 2051 | if (obj->active) { |
ce453d81 | 2052 | ret = i915_wait_request(obj->ring, obj->last_rendering_seqno); |
2cf34d7b | 2053 | if (ret) |
673a394b EA |
2054 | return ret; |
2055 | } | |
2056 | ||
2057 | return 0; | |
2058 | } | |
2059 | ||
b5ffc9bc CW |
2060 | static void i915_gem_object_finish_gtt(struct drm_i915_gem_object *obj) |
2061 | { | |
2062 | u32 old_write_domain, old_read_domains; | |
2063 | ||
b5ffc9bc CW |
2064 | /* Act a barrier for all accesses through the GTT */ |
2065 | mb(); | |
2066 | ||
2067 | /* Force a pagefault for domain tracking on next user access */ | |
2068 | i915_gem_release_mmap(obj); | |
2069 | ||
b97c3d9c KP |
2070 | if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0) |
2071 | return; | |
2072 | ||
b5ffc9bc CW |
2073 | old_read_domains = obj->base.read_domains; |
2074 | old_write_domain = obj->base.write_domain; | |
2075 | ||
2076 | obj->base.read_domains &= ~I915_GEM_DOMAIN_GTT; | |
2077 | obj->base.write_domain &= ~I915_GEM_DOMAIN_GTT; | |
2078 | ||
2079 | trace_i915_gem_object_change_domain(obj, | |
2080 | old_read_domains, | |
2081 | old_write_domain); | |
2082 | } | |
2083 | ||
673a394b EA |
2084 | /** |
2085 | * Unbinds an object from the GTT aperture. | |
2086 | */ | |
0f973f27 | 2087 | int |
05394f39 | 2088 | i915_gem_object_unbind(struct drm_i915_gem_object *obj) |
673a394b | 2089 | { |
673a394b EA |
2090 | int ret = 0; |
2091 | ||
05394f39 | 2092 | if (obj->gtt_space == NULL) |
673a394b EA |
2093 | return 0; |
2094 | ||
05394f39 | 2095 | if (obj->pin_count != 0) { |
673a394b EA |
2096 | DRM_ERROR("Attempting to unbind pinned buffer\n"); |
2097 | return -EINVAL; | |
2098 | } | |
2099 | ||
a8198eea CW |
2100 | ret = i915_gem_object_finish_gpu(obj); |
2101 | if (ret == -ERESTARTSYS) | |
2102 | return ret; | |
2103 | /* Continue on if we fail due to EIO, the GPU is hung so we | |
2104 | * should be safe and we need to cleanup or else we might | |
2105 | * cause memory corruption through use-after-free. | |
2106 | */ | |
2107 | ||
b5ffc9bc | 2108 | i915_gem_object_finish_gtt(obj); |
5323fd04 | 2109 | |
673a394b EA |
2110 | /* Move the object to the CPU domain to ensure that |
2111 | * any possible CPU writes while it's not in the GTT | |
a8198eea | 2112 | * are flushed when we go to remap it. |
673a394b | 2113 | */ |
a8198eea CW |
2114 | if (ret == 0) |
2115 | ret = i915_gem_object_set_to_cpu_domain(obj, 1); | |
8dc1775d | 2116 | if (ret == -ERESTARTSYS) |
673a394b | 2117 | return ret; |
812ed492 | 2118 | if (ret) { |
a8198eea CW |
2119 | /* In the event of a disaster, abandon all caches and |
2120 | * hope for the best. | |
2121 | */ | |
812ed492 | 2122 | i915_gem_clflush_object(obj); |
05394f39 | 2123 | obj->base.read_domains = obj->base.write_domain = I915_GEM_DOMAIN_CPU; |
812ed492 | 2124 | } |
673a394b | 2125 | |
96b47b65 | 2126 | /* release the fence reg _after_ flushing */ |
d9e86c0e CW |
2127 | ret = i915_gem_object_put_fence(obj); |
2128 | if (ret == -ERESTARTSYS) | |
2129 | return ret; | |
96b47b65 | 2130 | |
db53a302 CW |
2131 | trace_i915_gem_object_unbind(obj); |
2132 | ||
7c2e6fdf | 2133 | i915_gem_gtt_unbind_object(obj); |
e5281ccd | 2134 | i915_gem_object_put_pages_gtt(obj); |
673a394b | 2135 | |
6299f992 | 2136 | list_del_init(&obj->gtt_list); |
05394f39 | 2137 | list_del_init(&obj->mm_list); |
75e9e915 | 2138 | /* Avoid an unnecessary call to unbind on rebind. */ |
05394f39 | 2139 | obj->map_and_fenceable = true; |
673a394b | 2140 | |
05394f39 CW |
2141 | drm_mm_put_block(obj->gtt_space); |
2142 | obj->gtt_space = NULL; | |
2143 | obj->gtt_offset = 0; | |
673a394b | 2144 | |
05394f39 | 2145 | if (i915_gem_object_is_purgeable(obj)) |
963b4836 CW |
2146 | i915_gem_object_truncate(obj); |
2147 | ||
8dc1775d | 2148 | return ret; |
673a394b EA |
2149 | } |
2150 | ||
88241785 | 2151 | int |
db53a302 | 2152 | i915_gem_flush_ring(struct intel_ring_buffer *ring, |
54cf91dc CW |
2153 | uint32_t invalidate_domains, |
2154 | uint32_t flush_domains) | |
2155 | { | |
88241785 CW |
2156 | int ret; |
2157 | ||
36d527de CW |
2158 | if (((invalidate_domains | flush_domains) & I915_GEM_GPU_DOMAINS) == 0) |
2159 | return 0; | |
2160 | ||
db53a302 CW |
2161 | trace_i915_gem_ring_flush(ring, invalidate_domains, flush_domains); |
2162 | ||
88241785 CW |
2163 | ret = ring->flush(ring, invalidate_domains, flush_domains); |
2164 | if (ret) | |
2165 | return ret; | |
2166 | ||
36d527de CW |
2167 | if (flush_domains & I915_GEM_GPU_DOMAINS) |
2168 | i915_gem_process_flushing_list(ring, flush_domains); | |
2169 | ||
88241785 | 2170 | return 0; |
54cf91dc CW |
2171 | } |
2172 | ||
db53a302 | 2173 | static int i915_ring_idle(struct intel_ring_buffer *ring) |
a56ba56c | 2174 | { |
88241785 CW |
2175 | int ret; |
2176 | ||
395b70be | 2177 | if (list_empty(&ring->gpu_write_list) && list_empty(&ring->active_list)) |
64193406 CW |
2178 | return 0; |
2179 | ||
88241785 | 2180 | if (!list_empty(&ring->gpu_write_list)) { |
db53a302 | 2181 | ret = i915_gem_flush_ring(ring, |
0ac74c6b | 2182 | I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS); |
88241785 CW |
2183 | if (ret) |
2184 | return ret; | |
2185 | } | |
2186 | ||
ce453d81 | 2187 | return i915_wait_request(ring, i915_gem_next_request_seqno(ring)); |
a56ba56c CW |
2188 | } |
2189 | ||
b47eb4a2 | 2190 | int |
4df2faf4 DV |
2191 | i915_gpu_idle(struct drm_device *dev) |
2192 | { | |
2193 | drm_i915_private_t *dev_priv = dev->dev_private; | |
2194 | bool lists_empty; | |
1ec14ad3 | 2195 | int ret, i; |
4df2faf4 | 2196 | |
d1b851fc | 2197 | lists_empty = (list_empty(&dev_priv->mm.flushing_list) && |
395b70be | 2198 | list_empty(&dev_priv->mm.active_list)); |
4df2faf4 DV |
2199 | if (lists_empty) |
2200 | return 0; | |
2201 | ||
2202 | /* Flush everything onto the inactive list. */ | |
1ec14ad3 | 2203 | for (i = 0; i < I915_NUM_RINGS; i++) { |
db53a302 | 2204 | ret = i915_ring_idle(&dev_priv->ring[i]); |
1ec14ad3 CW |
2205 | if (ret) |
2206 | return ret; | |
2207 | } | |
4df2faf4 | 2208 | |
8a1a49f9 | 2209 | return 0; |
4df2faf4 DV |
2210 | } |
2211 | ||
c6642782 DV |
2212 | static int sandybridge_write_fence_reg(struct drm_i915_gem_object *obj, |
2213 | struct intel_ring_buffer *pipelined) | |
4e901fdc | 2214 | { |
05394f39 | 2215 | struct drm_device *dev = obj->base.dev; |
4e901fdc | 2216 | drm_i915_private_t *dev_priv = dev->dev_private; |
05394f39 CW |
2217 | u32 size = obj->gtt_space->size; |
2218 | int regnum = obj->fence_reg; | |
4e901fdc EA |
2219 | uint64_t val; |
2220 | ||
05394f39 | 2221 | val = (uint64_t)((obj->gtt_offset + size - 4096) & |
c6642782 | 2222 | 0xfffff000) << 32; |
05394f39 CW |
2223 | val |= obj->gtt_offset & 0xfffff000; |
2224 | val |= (uint64_t)((obj->stride / 128) - 1) << | |
4e901fdc EA |
2225 | SANDYBRIDGE_FENCE_PITCH_SHIFT; |
2226 | ||
05394f39 | 2227 | if (obj->tiling_mode == I915_TILING_Y) |
4e901fdc EA |
2228 | val |= 1 << I965_FENCE_TILING_Y_SHIFT; |
2229 | val |= I965_FENCE_REG_VALID; | |
2230 | ||
c6642782 DV |
2231 | if (pipelined) { |
2232 | int ret = intel_ring_begin(pipelined, 6); | |
2233 | if (ret) | |
2234 | return ret; | |
2235 | ||
2236 | intel_ring_emit(pipelined, MI_NOOP); | |
2237 | intel_ring_emit(pipelined, MI_LOAD_REGISTER_IMM(2)); | |
2238 | intel_ring_emit(pipelined, FENCE_REG_SANDYBRIDGE_0 + regnum*8); | |
2239 | intel_ring_emit(pipelined, (u32)val); | |
2240 | intel_ring_emit(pipelined, FENCE_REG_SANDYBRIDGE_0 + regnum*8 + 4); | |
2241 | intel_ring_emit(pipelined, (u32)(val >> 32)); | |
2242 | intel_ring_advance(pipelined); | |
2243 | } else | |
2244 | I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + regnum * 8, val); | |
2245 | ||
2246 | return 0; | |
4e901fdc EA |
2247 | } |
2248 | ||
c6642782 DV |
2249 | static int i965_write_fence_reg(struct drm_i915_gem_object *obj, |
2250 | struct intel_ring_buffer *pipelined) | |
de151cf6 | 2251 | { |
05394f39 | 2252 | struct drm_device *dev = obj->base.dev; |
de151cf6 | 2253 | drm_i915_private_t *dev_priv = dev->dev_private; |
05394f39 CW |
2254 | u32 size = obj->gtt_space->size; |
2255 | int regnum = obj->fence_reg; | |
de151cf6 JB |
2256 | uint64_t val; |
2257 | ||
05394f39 | 2258 | val = (uint64_t)((obj->gtt_offset + size - 4096) & |
de151cf6 | 2259 | 0xfffff000) << 32; |
05394f39 CW |
2260 | val |= obj->gtt_offset & 0xfffff000; |
2261 | val |= ((obj->stride / 128) - 1) << I965_FENCE_PITCH_SHIFT; | |
2262 | if (obj->tiling_mode == I915_TILING_Y) | |
de151cf6 JB |
2263 | val |= 1 << I965_FENCE_TILING_Y_SHIFT; |
2264 | val |= I965_FENCE_REG_VALID; | |
2265 | ||
c6642782 DV |
2266 | if (pipelined) { |
2267 | int ret = intel_ring_begin(pipelined, 6); | |
2268 | if (ret) | |
2269 | return ret; | |
2270 | ||
2271 | intel_ring_emit(pipelined, MI_NOOP); | |
2272 | intel_ring_emit(pipelined, MI_LOAD_REGISTER_IMM(2)); | |
2273 | intel_ring_emit(pipelined, FENCE_REG_965_0 + regnum*8); | |
2274 | intel_ring_emit(pipelined, (u32)val); | |
2275 | intel_ring_emit(pipelined, FENCE_REG_965_0 + regnum*8 + 4); | |
2276 | intel_ring_emit(pipelined, (u32)(val >> 32)); | |
2277 | intel_ring_advance(pipelined); | |
2278 | } else | |
2279 | I915_WRITE64(FENCE_REG_965_0 + regnum * 8, val); | |
2280 | ||
2281 | return 0; | |
de151cf6 JB |
2282 | } |
2283 | ||
c6642782 DV |
2284 | static int i915_write_fence_reg(struct drm_i915_gem_object *obj, |
2285 | struct intel_ring_buffer *pipelined) | |
de151cf6 | 2286 | { |
05394f39 | 2287 | struct drm_device *dev = obj->base.dev; |
de151cf6 | 2288 | drm_i915_private_t *dev_priv = dev->dev_private; |
05394f39 | 2289 | u32 size = obj->gtt_space->size; |
c6642782 | 2290 | u32 fence_reg, val, pitch_val; |
0f973f27 | 2291 | int tile_width; |
de151cf6 | 2292 | |
c6642782 DV |
2293 | if (WARN((obj->gtt_offset & ~I915_FENCE_START_MASK) || |
2294 | (size & -size) != size || | |
2295 | (obj->gtt_offset & (size - 1)), | |
2296 | "object 0x%08x [fenceable? %d] not 1M or pot-size (0x%08x) aligned\n", | |
2297 | obj->gtt_offset, obj->map_and_fenceable, size)) | |
2298 | return -EINVAL; | |
de151cf6 | 2299 | |
c6642782 | 2300 | if (obj->tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev)) |
0f973f27 | 2301 | tile_width = 128; |
de151cf6 | 2302 | else |
0f973f27 JB |
2303 | tile_width = 512; |
2304 | ||
2305 | /* Note: pitch better be a power of two tile widths */ | |
05394f39 | 2306 | pitch_val = obj->stride / tile_width; |
0f973f27 | 2307 | pitch_val = ffs(pitch_val) - 1; |
de151cf6 | 2308 | |
05394f39 CW |
2309 | val = obj->gtt_offset; |
2310 | if (obj->tiling_mode == I915_TILING_Y) | |
de151cf6 | 2311 | val |= 1 << I830_FENCE_TILING_Y_SHIFT; |
a00b10c3 | 2312 | val |= I915_FENCE_SIZE_BITS(size); |
de151cf6 JB |
2313 | val |= pitch_val << I830_FENCE_PITCH_SHIFT; |
2314 | val |= I830_FENCE_REG_VALID; | |
2315 | ||
05394f39 | 2316 | fence_reg = obj->fence_reg; |
a00b10c3 CW |
2317 | if (fence_reg < 8) |
2318 | fence_reg = FENCE_REG_830_0 + fence_reg * 4; | |
dc529a4f | 2319 | else |
a00b10c3 | 2320 | fence_reg = FENCE_REG_945_8 + (fence_reg - 8) * 4; |
c6642782 DV |
2321 | |
2322 | if (pipelined) { | |
2323 | int ret = intel_ring_begin(pipelined, 4); | |
2324 | if (ret) | |
2325 | return ret; | |
2326 | ||
2327 | intel_ring_emit(pipelined, MI_NOOP); | |
2328 | intel_ring_emit(pipelined, MI_LOAD_REGISTER_IMM(1)); | |
2329 | intel_ring_emit(pipelined, fence_reg); | |
2330 | intel_ring_emit(pipelined, val); | |
2331 | intel_ring_advance(pipelined); | |
2332 | } else | |
2333 | I915_WRITE(fence_reg, val); | |
2334 | ||
2335 | return 0; | |
de151cf6 JB |
2336 | } |
2337 | ||
c6642782 DV |
2338 | static int i830_write_fence_reg(struct drm_i915_gem_object *obj, |
2339 | struct intel_ring_buffer *pipelined) | |
de151cf6 | 2340 | { |
05394f39 | 2341 | struct drm_device *dev = obj->base.dev; |
de151cf6 | 2342 | drm_i915_private_t *dev_priv = dev->dev_private; |
05394f39 CW |
2343 | u32 size = obj->gtt_space->size; |
2344 | int regnum = obj->fence_reg; | |
de151cf6 JB |
2345 | uint32_t val; |
2346 | uint32_t pitch_val; | |
2347 | ||
c6642782 DV |
2348 | if (WARN((obj->gtt_offset & ~I830_FENCE_START_MASK) || |
2349 | (size & -size) != size || | |
2350 | (obj->gtt_offset & (size - 1)), | |
2351 | "object 0x%08x not 512K or pot-size 0x%08x aligned\n", | |
2352 | obj->gtt_offset, size)) | |
2353 | return -EINVAL; | |
de151cf6 | 2354 | |
05394f39 | 2355 | pitch_val = obj->stride / 128; |
e76a16de | 2356 | pitch_val = ffs(pitch_val) - 1; |
e76a16de | 2357 | |
05394f39 CW |
2358 | val = obj->gtt_offset; |
2359 | if (obj->tiling_mode == I915_TILING_Y) | |
de151cf6 | 2360 | val |= 1 << I830_FENCE_TILING_Y_SHIFT; |
c6642782 | 2361 | val |= I830_FENCE_SIZE_BITS(size); |
de151cf6 JB |
2362 | val |= pitch_val << I830_FENCE_PITCH_SHIFT; |
2363 | val |= I830_FENCE_REG_VALID; | |
2364 | ||
c6642782 DV |
2365 | if (pipelined) { |
2366 | int ret = intel_ring_begin(pipelined, 4); | |
2367 | if (ret) | |
2368 | return ret; | |
2369 | ||
2370 | intel_ring_emit(pipelined, MI_NOOP); | |
2371 | intel_ring_emit(pipelined, MI_LOAD_REGISTER_IMM(1)); | |
2372 | intel_ring_emit(pipelined, FENCE_REG_830_0 + regnum*4); | |
2373 | intel_ring_emit(pipelined, val); | |
2374 | intel_ring_advance(pipelined); | |
2375 | } else | |
2376 | I915_WRITE(FENCE_REG_830_0 + regnum * 4, val); | |
2377 | ||
2378 | return 0; | |
de151cf6 JB |
2379 | } |
2380 | ||
d9e86c0e CW |
2381 | static bool ring_passed_seqno(struct intel_ring_buffer *ring, u32 seqno) |
2382 | { | |
2383 | return i915_seqno_passed(ring->get_seqno(ring), seqno); | |
2384 | } | |
2385 | ||
2386 | static int | |
2387 | i915_gem_object_flush_fence(struct drm_i915_gem_object *obj, | |
ce453d81 | 2388 | struct intel_ring_buffer *pipelined) |
d9e86c0e CW |
2389 | { |
2390 | int ret; | |
2391 | ||
2392 | if (obj->fenced_gpu_access) { | |
88241785 | 2393 | if (obj->base.write_domain & I915_GEM_GPU_DOMAINS) { |
db53a302 | 2394 | ret = i915_gem_flush_ring(obj->last_fenced_ring, |
88241785 CW |
2395 | 0, obj->base.write_domain); |
2396 | if (ret) | |
2397 | return ret; | |
2398 | } | |
d9e86c0e CW |
2399 | |
2400 | obj->fenced_gpu_access = false; | |
2401 | } | |
2402 | ||
2403 | if (obj->last_fenced_seqno && pipelined != obj->last_fenced_ring) { | |
2404 | if (!ring_passed_seqno(obj->last_fenced_ring, | |
2405 | obj->last_fenced_seqno)) { | |
db53a302 | 2406 | ret = i915_wait_request(obj->last_fenced_ring, |
ce453d81 | 2407 | obj->last_fenced_seqno); |
d9e86c0e CW |
2408 | if (ret) |
2409 | return ret; | |
2410 | } | |
2411 | ||
2412 | obj->last_fenced_seqno = 0; | |
2413 | obj->last_fenced_ring = NULL; | |
2414 | } | |
2415 | ||
63256ec5 CW |
2416 | /* Ensure that all CPU reads are completed before installing a fence |
2417 | * and all writes before removing the fence. | |
2418 | */ | |
2419 | if (obj->base.read_domains & I915_GEM_DOMAIN_GTT) | |
2420 | mb(); | |
2421 | ||
d9e86c0e CW |
2422 | return 0; |
2423 | } | |
2424 | ||
2425 | int | |
2426 | i915_gem_object_put_fence(struct drm_i915_gem_object *obj) | |
2427 | { | |
2428 | int ret; | |
2429 | ||
2430 | if (obj->tiling_mode) | |
2431 | i915_gem_release_mmap(obj); | |
2432 | ||
ce453d81 | 2433 | ret = i915_gem_object_flush_fence(obj, NULL); |
d9e86c0e CW |
2434 | if (ret) |
2435 | return ret; | |
2436 | ||
2437 | if (obj->fence_reg != I915_FENCE_REG_NONE) { | |
2438 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; | |
2439 | i915_gem_clear_fence_reg(obj->base.dev, | |
2440 | &dev_priv->fence_regs[obj->fence_reg]); | |
2441 | ||
2442 | obj->fence_reg = I915_FENCE_REG_NONE; | |
2443 | } | |
2444 | ||
2445 | return 0; | |
2446 | } | |
2447 | ||
2448 | static struct drm_i915_fence_reg * | |
2449 | i915_find_fence_reg(struct drm_device *dev, | |
2450 | struct intel_ring_buffer *pipelined) | |
ae3db24a | 2451 | { |
ae3db24a | 2452 | struct drm_i915_private *dev_priv = dev->dev_private; |
d9e86c0e CW |
2453 | struct drm_i915_fence_reg *reg, *first, *avail; |
2454 | int i; | |
ae3db24a DV |
2455 | |
2456 | /* First try to find a free reg */ | |
d9e86c0e | 2457 | avail = NULL; |
ae3db24a DV |
2458 | for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) { |
2459 | reg = &dev_priv->fence_regs[i]; | |
2460 | if (!reg->obj) | |
d9e86c0e | 2461 | return reg; |
ae3db24a | 2462 | |
05394f39 | 2463 | if (!reg->obj->pin_count) |
d9e86c0e | 2464 | avail = reg; |
ae3db24a DV |
2465 | } |
2466 | ||
d9e86c0e CW |
2467 | if (avail == NULL) |
2468 | return NULL; | |
ae3db24a DV |
2469 | |
2470 | /* None available, try to steal one or wait for a user to finish */ | |
d9e86c0e CW |
2471 | avail = first = NULL; |
2472 | list_for_each_entry(reg, &dev_priv->mm.fence_list, lru_list) { | |
2473 | if (reg->obj->pin_count) | |
ae3db24a DV |
2474 | continue; |
2475 | ||
d9e86c0e CW |
2476 | if (first == NULL) |
2477 | first = reg; | |
2478 | ||
2479 | if (!pipelined || | |
2480 | !reg->obj->last_fenced_ring || | |
2481 | reg->obj->last_fenced_ring == pipelined) { | |
2482 | avail = reg; | |
2483 | break; | |
2484 | } | |
ae3db24a DV |
2485 | } |
2486 | ||
d9e86c0e CW |
2487 | if (avail == NULL) |
2488 | avail = first; | |
ae3db24a | 2489 | |
a00b10c3 | 2490 | return avail; |
ae3db24a DV |
2491 | } |
2492 | ||
de151cf6 | 2493 | /** |
d9e86c0e | 2494 | * i915_gem_object_get_fence - set up a fence reg for an object |
de151cf6 | 2495 | * @obj: object to map through a fence reg |
d9e86c0e CW |
2496 | * @pipelined: ring on which to queue the change, or NULL for CPU access |
2497 | * @interruptible: must we wait uninterruptibly for the register to retire? | |
de151cf6 JB |
2498 | * |
2499 | * When mapping objects through the GTT, userspace wants to be able to write | |
2500 | * to them without having to worry about swizzling if the object is tiled. | |
2501 | * | |
2502 | * This function walks the fence regs looking for a free one for @obj, | |
2503 | * stealing one if it can't find any. | |
2504 | * | |
2505 | * It then sets up the reg based on the object's properties: address, pitch | |
2506 | * and tiling format. | |
2507 | */ | |
8c4b8c3f | 2508 | int |
d9e86c0e | 2509 | i915_gem_object_get_fence(struct drm_i915_gem_object *obj, |
ce453d81 | 2510 | struct intel_ring_buffer *pipelined) |
de151cf6 | 2511 | { |
05394f39 | 2512 | struct drm_device *dev = obj->base.dev; |
79e53945 | 2513 | struct drm_i915_private *dev_priv = dev->dev_private; |
d9e86c0e | 2514 | struct drm_i915_fence_reg *reg; |
ae3db24a | 2515 | int ret; |
de151cf6 | 2516 | |
6bda10d1 CW |
2517 | /* XXX disable pipelining. There are bugs. Shocking. */ |
2518 | pipelined = NULL; | |
2519 | ||
d9e86c0e | 2520 | /* Just update our place in the LRU if our fence is getting reused. */ |
05394f39 CW |
2521 | if (obj->fence_reg != I915_FENCE_REG_NONE) { |
2522 | reg = &dev_priv->fence_regs[obj->fence_reg]; | |
007cc8ac | 2523 | list_move_tail(®->lru_list, &dev_priv->mm.fence_list); |
d9e86c0e | 2524 | |
29c5a587 CW |
2525 | if (obj->tiling_changed) { |
2526 | ret = i915_gem_object_flush_fence(obj, pipelined); | |
2527 | if (ret) | |
2528 | return ret; | |
2529 | ||
2530 | if (!obj->fenced_gpu_access && !obj->last_fenced_seqno) | |
2531 | pipelined = NULL; | |
2532 | ||
2533 | if (pipelined) { | |
2534 | reg->setup_seqno = | |
2535 | i915_gem_next_request_seqno(pipelined); | |
2536 | obj->last_fenced_seqno = reg->setup_seqno; | |
2537 | obj->last_fenced_ring = pipelined; | |
2538 | } | |
2539 | ||
2540 | goto update; | |
2541 | } | |
d9e86c0e CW |
2542 | |
2543 | if (!pipelined) { | |
2544 | if (reg->setup_seqno) { | |
2545 | if (!ring_passed_seqno(obj->last_fenced_ring, | |
2546 | reg->setup_seqno)) { | |
db53a302 | 2547 | ret = i915_wait_request(obj->last_fenced_ring, |
ce453d81 | 2548 | reg->setup_seqno); |
d9e86c0e CW |
2549 | if (ret) |
2550 | return ret; | |
2551 | } | |
2552 | ||
2553 | reg->setup_seqno = 0; | |
2554 | } | |
2555 | } else if (obj->last_fenced_ring && | |
2556 | obj->last_fenced_ring != pipelined) { | |
ce453d81 | 2557 | ret = i915_gem_object_flush_fence(obj, pipelined); |
d9e86c0e CW |
2558 | if (ret) |
2559 | return ret; | |
d9e86c0e CW |
2560 | } |
2561 | ||
a09ba7fa EA |
2562 | return 0; |
2563 | } | |
2564 | ||
d9e86c0e CW |
2565 | reg = i915_find_fence_reg(dev, pipelined); |
2566 | if (reg == NULL) | |
2567 | return -ENOSPC; | |
de151cf6 | 2568 | |
ce453d81 | 2569 | ret = i915_gem_object_flush_fence(obj, pipelined); |
d9e86c0e | 2570 | if (ret) |
ae3db24a | 2571 | return ret; |
de151cf6 | 2572 | |
d9e86c0e CW |
2573 | if (reg->obj) { |
2574 | struct drm_i915_gem_object *old = reg->obj; | |
2575 | ||
2576 | drm_gem_object_reference(&old->base); | |
2577 | ||
2578 | if (old->tiling_mode) | |
2579 | i915_gem_release_mmap(old); | |
2580 | ||
ce453d81 | 2581 | ret = i915_gem_object_flush_fence(old, pipelined); |
d9e86c0e CW |
2582 | if (ret) { |
2583 | drm_gem_object_unreference(&old->base); | |
2584 | return ret; | |
2585 | } | |
2586 | ||
2587 | if (old->last_fenced_seqno == 0 && obj->last_fenced_seqno == 0) | |
2588 | pipelined = NULL; | |
2589 | ||
2590 | old->fence_reg = I915_FENCE_REG_NONE; | |
2591 | old->last_fenced_ring = pipelined; | |
2592 | old->last_fenced_seqno = | |
db53a302 | 2593 | pipelined ? i915_gem_next_request_seqno(pipelined) : 0; |
d9e86c0e CW |
2594 | |
2595 | drm_gem_object_unreference(&old->base); | |
2596 | } else if (obj->last_fenced_seqno == 0) | |
2597 | pipelined = NULL; | |
a09ba7fa | 2598 | |
de151cf6 | 2599 | reg->obj = obj; |
d9e86c0e CW |
2600 | list_move_tail(®->lru_list, &dev_priv->mm.fence_list); |
2601 | obj->fence_reg = reg - dev_priv->fence_regs; | |
2602 | obj->last_fenced_ring = pipelined; | |
de151cf6 | 2603 | |
d9e86c0e | 2604 | reg->setup_seqno = |
db53a302 | 2605 | pipelined ? i915_gem_next_request_seqno(pipelined) : 0; |
d9e86c0e CW |
2606 | obj->last_fenced_seqno = reg->setup_seqno; |
2607 | ||
2608 | update: | |
2609 | obj->tiling_changed = false; | |
e259befd | 2610 | switch (INTEL_INFO(dev)->gen) { |
25aebfc3 | 2611 | case 7: |
e259befd | 2612 | case 6: |
c6642782 | 2613 | ret = sandybridge_write_fence_reg(obj, pipelined); |
e259befd CW |
2614 | break; |
2615 | case 5: | |
2616 | case 4: | |
c6642782 | 2617 | ret = i965_write_fence_reg(obj, pipelined); |
e259befd CW |
2618 | break; |
2619 | case 3: | |
c6642782 | 2620 | ret = i915_write_fence_reg(obj, pipelined); |
e259befd CW |
2621 | break; |
2622 | case 2: | |
c6642782 | 2623 | ret = i830_write_fence_reg(obj, pipelined); |
e259befd CW |
2624 | break; |
2625 | } | |
d9ddcb96 | 2626 | |
c6642782 | 2627 | return ret; |
de151cf6 JB |
2628 | } |
2629 | ||
2630 | /** | |
2631 | * i915_gem_clear_fence_reg - clear out fence register info | |
2632 | * @obj: object to clear | |
2633 | * | |
2634 | * Zeroes out the fence register itself and clears out the associated | |
05394f39 | 2635 | * data structures in dev_priv and obj. |
de151cf6 JB |
2636 | */ |
2637 | static void | |
d9e86c0e CW |
2638 | i915_gem_clear_fence_reg(struct drm_device *dev, |
2639 | struct drm_i915_fence_reg *reg) | |
de151cf6 | 2640 | { |
79e53945 | 2641 | drm_i915_private_t *dev_priv = dev->dev_private; |
d9e86c0e | 2642 | uint32_t fence_reg = reg - dev_priv->fence_regs; |
de151cf6 | 2643 | |
e259befd | 2644 | switch (INTEL_INFO(dev)->gen) { |
25aebfc3 | 2645 | case 7: |
e259befd | 2646 | case 6: |
d9e86c0e | 2647 | I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + fence_reg*8, 0); |
e259befd CW |
2648 | break; |
2649 | case 5: | |
2650 | case 4: | |
d9e86c0e | 2651 | I915_WRITE64(FENCE_REG_965_0 + fence_reg*8, 0); |
e259befd CW |
2652 | break; |
2653 | case 3: | |
d9e86c0e CW |
2654 | if (fence_reg >= 8) |
2655 | fence_reg = FENCE_REG_945_8 + (fence_reg - 8) * 4; | |
dc529a4f | 2656 | else |
e259befd | 2657 | case 2: |
d9e86c0e | 2658 | fence_reg = FENCE_REG_830_0 + fence_reg * 4; |
dc529a4f EA |
2659 | |
2660 | I915_WRITE(fence_reg, 0); | |
e259befd | 2661 | break; |
dc529a4f | 2662 | } |
de151cf6 | 2663 | |
007cc8ac | 2664 | list_del_init(®->lru_list); |
d9e86c0e CW |
2665 | reg->obj = NULL; |
2666 | reg->setup_seqno = 0; | |
52dc7d32 CW |
2667 | } |
2668 | ||
673a394b EA |
2669 | /** |
2670 | * Finds free space in the GTT aperture and binds the object there. | |
2671 | */ | |
2672 | static int | |
05394f39 | 2673 | i915_gem_object_bind_to_gtt(struct drm_i915_gem_object *obj, |
920afa77 | 2674 | unsigned alignment, |
75e9e915 | 2675 | bool map_and_fenceable) |
673a394b | 2676 | { |
05394f39 | 2677 | struct drm_device *dev = obj->base.dev; |
673a394b | 2678 | drm_i915_private_t *dev_priv = dev->dev_private; |
673a394b | 2679 | struct drm_mm_node *free_space; |
a00b10c3 | 2680 | gfp_t gfpmask = __GFP_NORETRY | __GFP_NOWARN; |
5e783301 | 2681 | u32 size, fence_size, fence_alignment, unfenced_alignment; |
75e9e915 | 2682 | bool mappable, fenceable; |
07f73f69 | 2683 | int ret; |
673a394b | 2684 | |
05394f39 | 2685 | if (obj->madv != I915_MADV_WILLNEED) { |
3ef94daa CW |
2686 | DRM_ERROR("Attempting to bind a purgeable object\n"); |
2687 | return -EINVAL; | |
2688 | } | |
2689 | ||
e28f8711 CW |
2690 | fence_size = i915_gem_get_gtt_size(dev, |
2691 | obj->base.size, | |
2692 | obj->tiling_mode); | |
2693 | fence_alignment = i915_gem_get_gtt_alignment(dev, | |
2694 | obj->base.size, | |
2695 | obj->tiling_mode); | |
2696 | unfenced_alignment = | |
2697 | i915_gem_get_unfenced_gtt_alignment(dev, | |
2698 | obj->base.size, | |
2699 | obj->tiling_mode); | |
a00b10c3 | 2700 | |
673a394b | 2701 | if (alignment == 0) |
5e783301 DV |
2702 | alignment = map_and_fenceable ? fence_alignment : |
2703 | unfenced_alignment; | |
75e9e915 | 2704 | if (map_and_fenceable && alignment & (fence_alignment - 1)) { |
673a394b EA |
2705 | DRM_ERROR("Invalid object alignment requested %u\n", alignment); |
2706 | return -EINVAL; | |
2707 | } | |
2708 | ||
05394f39 | 2709 | size = map_and_fenceable ? fence_size : obj->base.size; |
a00b10c3 | 2710 | |
654fc607 CW |
2711 | /* If the object is bigger than the entire aperture, reject it early |
2712 | * before evicting everything in a vain attempt to find space. | |
2713 | */ | |
05394f39 | 2714 | if (obj->base.size > |
75e9e915 | 2715 | (map_and_fenceable ? dev_priv->mm.gtt_mappable_end : dev_priv->mm.gtt_total)) { |
654fc607 CW |
2716 | DRM_ERROR("Attempting to bind an object larger than the aperture\n"); |
2717 | return -E2BIG; | |
2718 | } | |
2719 | ||
673a394b | 2720 | search_free: |
75e9e915 | 2721 | if (map_and_fenceable) |
920afa77 DV |
2722 | free_space = |
2723 | drm_mm_search_free_in_range(&dev_priv->mm.gtt_space, | |
a00b10c3 | 2724 | size, alignment, 0, |
920afa77 DV |
2725 | dev_priv->mm.gtt_mappable_end, |
2726 | 0); | |
2727 | else | |
2728 | free_space = drm_mm_search_free(&dev_priv->mm.gtt_space, | |
a00b10c3 | 2729 | size, alignment, 0); |
920afa77 DV |
2730 | |
2731 | if (free_space != NULL) { | |
75e9e915 | 2732 | if (map_and_fenceable) |
05394f39 | 2733 | obj->gtt_space = |
920afa77 | 2734 | drm_mm_get_block_range_generic(free_space, |
a00b10c3 | 2735 | size, alignment, 0, |
920afa77 DV |
2736 | dev_priv->mm.gtt_mappable_end, |
2737 | 0); | |
2738 | else | |
05394f39 | 2739 | obj->gtt_space = |
a00b10c3 | 2740 | drm_mm_get_block(free_space, size, alignment); |
920afa77 | 2741 | } |
05394f39 | 2742 | if (obj->gtt_space == NULL) { |
673a394b EA |
2743 | /* If the gtt is empty and we're still having trouble |
2744 | * fitting our object in, we're out of memory. | |
2745 | */ | |
75e9e915 DV |
2746 | ret = i915_gem_evict_something(dev, size, alignment, |
2747 | map_and_fenceable); | |
9731129c | 2748 | if (ret) |
673a394b | 2749 | return ret; |
9731129c | 2750 | |
673a394b EA |
2751 | goto search_free; |
2752 | } | |
2753 | ||
e5281ccd | 2754 | ret = i915_gem_object_get_pages_gtt(obj, gfpmask); |
673a394b | 2755 | if (ret) { |
05394f39 CW |
2756 | drm_mm_put_block(obj->gtt_space); |
2757 | obj->gtt_space = NULL; | |
07f73f69 CW |
2758 | |
2759 | if (ret == -ENOMEM) { | |
809b6334 CW |
2760 | /* first try to reclaim some memory by clearing the GTT */ |
2761 | ret = i915_gem_evict_everything(dev, false); | |
07f73f69 | 2762 | if (ret) { |
07f73f69 | 2763 | /* now try to shrink everyone else */ |
4bdadb97 CW |
2764 | if (gfpmask) { |
2765 | gfpmask = 0; | |
2766 | goto search_free; | |
07f73f69 CW |
2767 | } |
2768 | ||
809b6334 | 2769 | return -ENOMEM; |
07f73f69 CW |
2770 | } |
2771 | ||
2772 | goto search_free; | |
2773 | } | |
2774 | ||
673a394b EA |
2775 | return ret; |
2776 | } | |
2777 | ||
7c2e6fdf DV |
2778 | ret = i915_gem_gtt_bind_object(obj); |
2779 | if (ret) { | |
e5281ccd | 2780 | i915_gem_object_put_pages_gtt(obj); |
05394f39 CW |
2781 | drm_mm_put_block(obj->gtt_space); |
2782 | obj->gtt_space = NULL; | |
07f73f69 | 2783 | |
809b6334 | 2784 | if (i915_gem_evict_everything(dev, false)) |
07f73f69 | 2785 | return ret; |
07f73f69 CW |
2786 | |
2787 | goto search_free; | |
673a394b | 2788 | } |
673a394b | 2789 | |
6299f992 | 2790 | list_add_tail(&obj->gtt_list, &dev_priv->mm.gtt_list); |
05394f39 | 2791 | list_add_tail(&obj->mm_list, &dev_priv->mm.inactive_list); |
bf1a1092 | 2792 | |
673a394b EA |
2793 | /* Assert that the object is not currently in any GPU domain. As it |
2794 | * wasn't in the GTT, there shouldn't be any way it could have been in | |
2795 | * a GPU cache | |
2796 | */ | |
05394f39 CW |
2797 | BUG_ON(obj->base.read_domains & I915_GEM_GPU_DOMAINS); |
2798 | BUG_ON(obj->base.write_domain & I915_GEM_GPU_DOMAINS); | |
673a394b | 2799 | |
6299f992 | 2800 | obj->gtt_offset = obj->gtt_space->start; |
1c5d22f7 | 2801 | |
75e9e915 | 2802 | fenceable = |
05394f39 | 2803 | obj->gtt_space->size == fence_size && |
0206e353 | 2804 | (obj->gtt_space->start & (fence_alignment - 1)) == 0; |
a00b10c3 | 2805 | |
75e9e915 | 2806 | mappable = |
05394f39 | 2807 | obj->gtt_offset + obj->base.size <= dev_priv->mm.gtt_mappable_end; |
a00b10c3 | 2808 | |
05394f39 | 2809 | obj->map_and_fenceable = mappable && fenceable; |
75e9e915 | 2810 | |
db53a302 | 2811 | trace_i915_gem_object_bind(obj, map_and_fenceable); |
673a394b EA |
2812 | return 0; |
2813 | } | |
2814 | ||
2815 | void | |
05394f39 | 2816 | i915_gem_clflush_object(struct drm_i915_gem_object *obj) |
673a394b | 2817 | { |
673a394b EA |
2818 | /* If we don't have a page list set up, then we're not pinned |
2819 | * to GPU, and we can ignore the cache flush because it'll happen | |
2820 | * again at bind time. | |
2821 | */ | |
05394f39 | 2822 | if (obj->pages == NULL) |
673a394b EA |
2823 | return; |
2824 | ||
9c23f7fc CW |
2825 | /* If the GPU is snooping the contents of the CPU cache, |
2826 | * we do not need to manually clear the CPU cache lines. However, | |
2827 | * the caches are only snooped when the render cache is | |
2828 | * flushed/invalidated. As we always have to emit invalidations | |
2829 | * and flushes when moving into and out of the RENDER domain, correct | |
2830 | * snooping behaviour occurs naturally as the result of our domain | |
2831 | * tracking. | |
2832 | */ | |
2833 | if (obj->cache_level != I915_CACHE_NONE) | |
2834 | return; | |
2835 | ||
1c5d22f7 | 2836 | trace_i915_gem_object_clflush(obj); |
cfa16a0d | 2837 | |
05394f39 | 2838 | drm_clflush_pages(obj->pages, obj->base.size / PAGE_SIZE); |
673a394b EA |
2839 | } |
2840 | ||
e47c68e9 | 2841 | /** Flushes any GPU write domain for the object if it's dirty. */ |
88241785 | 2842 | static int |
3619df03 | 2843 | i915_gem_object_flush_gpu_write_domain(struct drm_i915_gem_object *obj) |
e47c68e9 | 2844 | { |
05394f39 | 2845 | if ((obj->base.write_domain & I915_GEM_GPU_DOMAINS) == 0) |
88241785 | 2846 | return 0; |
e47c68e9 EA |
2847 | |
2848 | /* Queue the GPU write cache flushing we need. */ | |
db53a302 | 2849 | return i915_gem_flush_ring(obj->ring, 0, obj->base.write_domain); |
e47c68e9 EA |
2850 | } |
2851 | ||
2852 | /** Flushes the GTT write domain for the object if it's dirty. */ | |
2853 | static void | |
05394f39 | 2854 | i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj) |
e47c68e9 | 2855 | { |
1c5d22f7 CW |
2856 | uint32_t old_write_domain; |
2857 | ||
05394f39 | 2858 | if (obj->base.write_domain != I915_GEM_DOMAIN_GTT) |
e47c68e9 EA |
2859 | return; |
2860 | ||
63256ec5 | 2861 | /* No actual flushing is required for the GTT write domain. Writes |
e47c68e9 EA |
2862 | * to it immediately go to main memory as far as we know, so there's |
2863 | * no chipset flush. It also doesn't land in render cache. | |
63256ec5 CW |
2864 | * |
2865 | * However, we do have to enforce the order so that all writes through | |
2866 | * the GTT land before any writes to the device, such as updates to | |
2867 | * the GATT itself. | |
e47c68e9 | 2868 | */ |
63256ec5 CW |
2869 | wmb(); |
2870 | ||
05394f39 CW |
2871 | old_write_domain = obj->base.write_domain; |
2872 | obj->base.write_domain = 0; | |
1c5d22f7 CW |
2873 | |
2874 | trace_i915_gem_object_change_domain(obj, | |
05394f39 | 2875 | obj->base.read_domains, |
1c5d22f7 | 2876 | old_write_domain); |
e47c68e9 EA |
2877 | } |
2878 | ||
2879 | /** Flushes the CPU write domain for the object if it's dirty. */ | |
2880 | static void | |
05394f39 | 2881 | i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj) |
e47c68e9 | 2882 | { |
1c5d22f7 | 2883 | uint32_t old_write_domain; |
e47c68e9 | 2884 | |
05394f39 | 2885 | if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) |
e47c68e9 EA |
2886 | return; |
2887 | ||
2888 | i915_gem_clflush_object(obj); | |
40ce6575 | 2889 | intel_gtt_chipset_flush(); |
05394f39 CW |
2890 | old_write_domain = obj->base.write_domain; |
2891 | obj->base.write_domain = 0; | |
1c5d22f7 CW |
2892 | |
2893 | trace_i915_gem_object_change_domain(obj, | |
05394f39 | 2894 | obj->base.read_domains, |
1c5d22f7 | 2895 | old_write_domain); |
e47c68e9 EA |
2896 | } |
2897 | ||
2ef7eeaa EA |
2898 | /** |
2899 | * Moves a single object to the GTT read, and possibly write domain. | |
2900 | * | |
2901 | * This function returns when the move is complete, including waiting on | |
2902 | * flushes to occur. | |
2903 | */ | |
79e53945 | 2904 | int |
2021746e | 2905 | i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write) |
2ef7eeaa | 2906 | { |
1c5d22f7 | 2907 | uint32_t old_write_domain, old_read_domains; |
e47c68e9 | 2908 | int ret; |
2ef7eeaa | 2909 | |
02354392 | 2910 | /* Not valid to be called on unbound objects. */ |
05394f39 | 2911 | if (obj->gtt_space == NULL) |
02354392 EA |
2912 | return -EINVAL; |
2913 | ||
8d7e3de1 CW |
2914 | if (obj->base.write_domain == I915_GEM_DOMAIN_GTT) |
2915 | return 0; | |
2916 | ||
88241785 CW |
2917 | ret = i915_gem_object_flush_gpu_write_domain(obj); |
2918 | if (ret) | |
2919 | return ret; | |
2920 | ||
87ca9c8a | 2921 | if (obj->pending_gpu_write || write) { |
ce453d81 | 2922 | ret = i915_gem_object_wait_rendering(obj); |
87ca9c8a CW |
2923 | if (ret) |
2924 | return ret; | |
2925 | } | |
2dafb1e0 | 2926 | |
7213342d | 2927 | i915_gem_object_flush_cpu_write_domain(obj); |
1c5d22f7 | 2928 | |
05394f39 CW |
2929 | old_write_domain = obj->base.write_domain; |
2930 | old_read_domains = obj->base.read_domains; | |
1c5d22f7 | 2931 | |
e47c68e9 EA |
2932 | /* It should now be out of any other write domains, and we can update |
2933 | * the domain values for our changes. | |
2934 | */ | |
05394f39 CW |
2935 | BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) != 0); |
2936 | obj->base.read_domains |= I915_GEM_DOMAIN_GTT; | |
e47c68e9 | 2937 | if (write) { |
05394f39 CW |
2938 | obj->base.read_domains = I915_GEM_DOMAIN_GTT; |
2939 | obj->base.write_domain = I915_GEM_DOMAIN_GTT; | |
2940 | obj->dirty = 1; | |
2ef7eeaa EA |
2941 | } |
2942 | ||
1c5d22f7 CW |
2943 | trace_i915_gem_object_change_domain(obj, |
2944 | old_read_domains, | |
2945 | old_write_domain); | |
2946 | ||
e47c68e9 EA |
2947 | return 0; |
2948 | } | |
2949 | ||
e4ffd173 CW |
2950 | int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj, |
2951 | enum i915_cache_level cache_level) | |
2952 | { | |
2953 | int ret; | |
2954 | ||
2955 | if (obj->cache_level == cache_level) | |
2956 | return 0; | |
2957 | ||
2958 | if (obj->pin_count) { | |
2959 | DRM_DEBUG("can not change the cache level of pinned objects\n"); | |
2960 | return -EBUSY; | |
2961 | } | |
2962 | ||
2963 | if (obj->gtt_space) { | |
2964 | ret = i915_gem_object_finish_gpu(obj); | |
2965 | if (ret) | |
2966 | return ret; | |
2967 | ||
2968 | i915_gem_object_finish_gtt(obj); | |
2969 | ||
2970 | /* Before SandyBridge, you could not use tiling or fence | |
2971 | * registers with snooped memory, so relinquish any fences | |
2972 | * currently pointing to our region in the aperture. | |
2973 | */ | |
2974 | if (INTEL_INFO(obj->base.dev)->gen < 6) { | |
2975 | ret = i915_gem_object_put_fence(obj); | |
2976 | if (ret) | |
2977 | return ret; | |
2978 | } | |
2979 | ||
2980 | i915_gem_gtt_rebind_object(obj, cache_level); | |
2981 | } | |
2982 | ||
2983 | if (cache_level == I915_CACHE_NONE) { | |
2984 | u32 old_read_domains, old_write_domain; | |
2985 | ||
2986 | /* If we're coming from LLC cached, then we haven't | |
2987 | * actually been tracking whether the data is in the | |
2988 | * CPU cache or not, since we only allow one bit set | |
2989 | * in obj->write_domain and have been skipping the clflushes. | |
2990 | * Just set it to the CPU cache for now. | |
2991 | */ | |
2992 | WARN_ON(obj->base.write_domain & ~I915_GEM_DOMAIN_CPU); | |
2993 | WARN_ON(obj->base.read_domains & ~I915_GEM_DOMAIN_CPU); | |
2994 | ||
2995 | old_read_domains = obj->base.read_domains; | |
2996 | old_write_domain = obj->base.write_domain; | |
2997 | ||
2998 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; | |
2999 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; | |
3000 | ||
3001 | trace_i915_gem_object_change_domain(obj, | |
3002 | old_read_domains, | |
3003 | old_write_domain); | |
3004 | } | |
3005 | ||
3006 | obj->cache_level = cache_level; | |
3007 | return 0; | |
3008 | } | |
3009 | ||
b9241ea3 | 3010 | /* |
2da3b9b9 CW |
3011 | * Prepare buffer for display plane (scanout, cursors, etc). |
3012 | * Can be called from an uninterruptible phase (modesetting) and allows | |
3013 | * any flushes to be pipelined (for pageflips). | |
3014 | * | |
3015 | * For the display plane, we want to be in the GTT but out of any write | |
3016 | * domains. So in many ways this looks like set_to_gtt_domain() apart from the | |
3017 | * ability to pipeline the waits, pinning and any additional subtleties | |
3018 | * that may differentiate the display plane from ordinary buffers. | |
b9241ea3 ZW |
3019 | */ |
3020 | int | |
2da3b9b9 CW |
3021 | i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj, |
3022 | u32 alignment, | |
919926ae | 3023 | struct intel_ring_buffer *pipelined) |
b9241ea3 | 3024 | { |
2da3b9b9 | 3025 | u32 old_read_domains, old_write_domain; |
b9241ea3 ZW |
3026 | int ret; |
3027 | ||
88241785 CW |
3028 | ret = i915_gem_object_flush_gpu_write_domain(obj); |
3029 | if (ret) | |
3030 | return ret; | |
3031 | ||
0be73284 | 3032 | if (pipelined != obj->ring) { |
ce453d81 | 3033 | ret = i915_gem_object_wait_rendering(obj); |
f0b69efc | 3034 | if (ret == -ERESTARTSYS) |
b9241ea3 ZW |
3035 | return ret; |
3036 | } | |
3037 | ||
a7ef0640 EA |
3038 | /* The display engine is not coherent with the LLC cache on gen6. As |
3039 | * a result, we make sure that the pinning that is about to occur is | |
3040 | * done with uncached PTEs. This is lowest common denominator for all | |
3041 | * chipsets. | |
3042 | * | |
3043 | * However for gen6+, we could do better by using the GFDT bit instead | |
3044 | * of uncaching, which would allow us to flush all the LLC-cached data | |
3045 | * with that bit in the PTE to main memory with just one PIPE_CONTROL. | |
3046 | */ | |
3047 | ret = i915_gem_object_set_cache_level(obj, I915_CACHE_NONE); | |
3048 | if (ret) | |
3049 | return ret; | |
3050 | ||
2da3b9b9 CW |
3051 | /* As the user may map the buffer once pinned in the display plane |
3052 | * (e.g. libkms for the bootup splash), we have to ensure that we | |
3053 | * always use map_and_fenceable for all scanout buffers. | |
3054 | */ | |
3055 | ret = i915_gem_object_pin(obj, alignment, true); | |
3056 | if (ret) | |
3057 | return ret; | |
3058 | ||
b118c1e3 CW |
3059 | i915_gem_object_flush_cpu_write_domain(obj); |
3060 | ||
2da3b9b9 | 3061 | old_write_domain = obj->base.write_domain; |
05394f39 | 3062 | old_read_domains = obj->base.read_domains; |
2da3b9b9 CW |
3063 | |
3064 | /* It should now be out of any other write domains, and we can update | |
3065 | * the domain values for our changes. | |
3066 | */ | |
3067 | BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) != 0); | |
05394f39 | 3068 | obj->base.read_domains |= I915_GEM_DOMAIN_GTT; |
b9241ea3 ZW |
3069 | |
3070 | trace_i915_gem_object_change_domain(obj, | |
3071 | old_read_domains, | |
2da3b9b9 | 3072 | old_write_domain); |
b9241ea3 ZW |
3073 | |
3074 | return 0; | |
3075 | } | |
3076 | ||
85345517 | 3077 | int |
a8198eea | 3078 | i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj) |
85345517 | 3079 | { |
88241785 CW |
3080 | int ret; |
3081 | ||
a8198eea | 3082 | if ((obj->base.read_domains & I915_GEM_GPU_DOMAINS) == 0) |
85345517 CW |
3083 | return 0; |
3084 | ||
88241785 | 3085 | if (obj->base.write_domain & I915_GEM_GPU_DOMAINS) { |
db53a302 | 3086 | ret = i915_gem_flush_ring(obj->ring, 0, obj->base.write_domain); |
88241785 CW |
3087 | if (ret) |
3088 | return ret; | |
3089 | } | |
85345517 | 3090 | |
a8198eea CW |
3091 | /* Ensure that we invalidate the GPU's caches and TLBs. */ |
3092 | obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS; | |
3093 | ||
ce453d81 | 3094 | return i915_gem_object_wait_rendering(obj); |
85345517 CW |
3095 | } |
3096 | ||
e47c68e9 EA |
3097 | /** |
3098 | * Moves a single object to the CPU read, and possibly write domain. | |
3099 | * | |
3100 | * This function returns when the move is complete, including waiting on | |
3101 | * flushes to occur. | |
3102 | */ | |
3103 | static int | |
919926ae | 3104 | i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write) |
e47c68e9 | 3105 | { |
1c5d22f7 | 3106 | uint32_t old_write_domain, old_read_domains; |
e47c68e9 EA |
3107 | int ret; |
3108 | ||
8d7e3de1 CW |
3109 | if (obj->base.write_domain == I915_GEM_DOMAIN_CPU) |
3110 | return 0; | |
3111 | ||
88241785 CW |
3112 | ret = i915_gem_object_flush_gpu_write_domain(obj); |
3113 | if (ret) | |
3114 | return ret; | |
3115 | ||
ce453d81 | 3116 | ret = i915_gem_object_wait_rendering(obj); |
de18a29e | 3117 | if (ret) |
e47c68e9 | 3118 | return ret; |
2ef7eeaa | 3119 | |
e47c68e9 | 3120 | i915_gem_object_flush_gtt_write_domain(obj); |
2ef7eeaa | 3121 | |
e47c68e9 EA |
3122 | /* If we have a partially-valid cache of the object in the CPU, |
3123 | * finish invalidating it and free the per-page flags. | |
2ef7eeaa | 3124 | */ |
e47c68e9 | 3125 | i915_gem_object_set_to_full_cpu_read_domain(obj); |
2ef7eeaa | 3126 | |
05394f39 CW |
3127 | old_write_domain = obj->base.write_domain; |
3128 | old_read_domains = obj->base.read_domains; | |
1c5d22f7 | 3129 | |
e47c68e9 | 3130 | /* Flush the CPU cache if it's still invalid. */ |
05394f39 | 3131 | if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) { |
2ef7eeaa | 3132 | i915_gem_clflush_object(obj); |
2ef7eeaa | 3133 | |
05394f39 | 3134 | obj->base.read_domains |= I915_GEM_DOMAIN_CPU; |
2ef7eeaa EA |
3135 | } |
3136 | ||
3137 | /* It should now be out of any other write domains, and we can update | |
3138 | * the domain values for our changes. | |
3139 | */ | |
05394f39 | 3140 | BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) != 0); |
e47c68e9 EA |
3141 | |
3142 | /* If we're writing through the CPU, then the GPU read domains will | |
3143 | * need to be invalidated at next use. | |
3144 | */ | |
3145 | if (write) { | |
05394f39 CW |
3146 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; |
3147 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; | |
e47c68e9 | 3148 | } |
2ef7eeaa | 3149 | |
1c5d22f7 CW |
3150 | trace_i915_gem_object_change_domain(obj, |
3151 | old_read_domains, | |
3152 | old_write_domain); | |
3153 | ||
2ef7eeaa EA |
3154 | return 0; |
3155 | } | |
3156 | ||
673a394b | 3157 | /** |
e47c68e9 | 3158 | * Moves the object from a partially CPU read to a full one. |
673a394b | 3159 | * |
e47c68e9 EA |
3160 | * Note that this only resolves i915_gem_object_set_cpu_read_domain_range(), |
3161 | * and doesn't handle transitioning from !(read_domains & I915_GEM_DOMAIN_CPU). | |
673a394b | 3162 | */ |
e47c68e9 | 3163 | static void |
05394f39 | 3164 | i915_gem_object_set_to_full_cpu_read_domain(struct drm_i915_gem_object *obj) |
673a394b | 3165 | { |
05394f39 | 3166 | if (!obj->page_cpu_valid) |
e47c68e9 EA |
3167 | return; |
3168 | ||
3169 | /* If we're partially in the CPU read domain, finish moving it in. | |
3170 | */ | |
05394f39 | 3171 | if (obj->base.read_domains & I915_GEM_DOMAIN_CPU) { |
e47c68e9 EA |
3172 | int i; |
3173 | ||
05394f39 CW |
3174 | for (i = 0; i <= (obj->base.size - 1) / PAGE_SIZE; i++) { |
3175 | if (obj->page_cpu_valid[i]) | |
e47c68e9 | 3176 | continue; |
05394f39 | 3177 | drm_clflush_pages(obj->pages + i, 1); |
e47c68e9 | 3178 | } |
e47c68e9 EA |
3179 | } |
3180 | ||
3181 | /* Free the page_cpu_valid mappings which are now stale, whether | |
3182 | * or not we've got I915_GEM_DOMAIN_CPU. | |
3183 | */ | |
05394f39 CW |
3184 | kfree(obj->page_cpu_valid); |
3185 | obj->page_cpu_valid = NULL; | |
e47c68e9 EA |
3186 | } |
3187 | ||
3188 | /** | |
3189 | * Set the CPU read domain on a range of the object. | |
3190 | * | |
3191 | * The object ends up with I915_GEM_DOMAIN_CPU in its read flags although it's | |
3192 | * not entirely valid. The page_cpu_valid member of the object flags which | |
3193 | * pages have been flushed, and will be respected by | |
3194 | * i915_gem_object_set_to_cpu_domain() if it's called on to get a valid mapping | |
3195 | * of the whole object. | |
3196 | * | |
3197 | * This function returns when the move is complete, including waiting on | |
3198 | * flushes to occur. | |
3199 | */ | |
3200 | static int | |
05394f39 | 3201 | i915_gem_object_set_cpu_read_domain_range(struct drm_i915_gem_object *obj, |
e47c68e9 EA |
3202 | uint64_t offset, uint64_t size) |
3203 | { | |
1c5d22f7 | 3204 | uint32_t old_read_domains; |
e47c68e9 | 3205 | int i, ret; |
673a394b | 3206 | |
05394f39 | 3207 | if (offset == 0 && size == obj->base.size) |
e47c68e9 | 3208 | return i915_gem_object_set_to_cpu_domain(obj, 0); |
673a394b | 3209 | |
88241785 CW |
3210 | ret = i915_gem_object_flush_gpu_write_domain(obj); |
3211 | if (ret) | |
3212 | return ret; | |
3213 | ||
ce453d81 | 3214 | ret = i915_gem_object_wait_rendering(obj); |
de18a29e | 3215 | if (ret) |
6a47baa6 | 3216 | return ret; |
de18a29e | 3217 | |
e47c68e9 EA |
3218 | i915_gem_object_flush_gtt_write_domain(obj); |
3219 | ||
3220 | /* If we're already fully in the CPU read domain, we're done. */ | |
05394f39 CW |
3221 | if (obj->page_cpu_valid == NULL && |
3222 | (obj->base.read_domains & I915_GEM_DOMAIN_CPU) != 0) | |
e47c68e9 | 3223 | return 0; |
673a394b | 3224 | |
e47c68e9 EA |
3225 | /* Otherwise, create/clear the per-page CPU read domain flag if we're |
3226 | * newly adding I915_GEM_DOMAIN_CPU | |
3227 | */ | |
05394f39 CW |
3228 | if (obj->page_cpu_valid == NULL) { |
3229 | obj->page_cpu_valid = kzalloc(obj->base.size / PAGE_SIZE, | |
3230 | GFP_KERNEL); | |
3231 | if (obj->page_cpu_valid == NULL) | |
e47c68e9 | 3232 | return -ENOMEM; |
05394f39 CW |
3233 | } else if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) |
3234 | memset(obj->page_cpu_valid, 0, obj->base.size / PAGE_SIZE); | |
673a394b EA |
3235 | |
3236 | /* Flush the cache on any pages that are still invalid from the CPU's | |
3237 | * perspective. | |
3238 | */ | |
e47c68e9 EA |
3239 | for (i = offset / PAGE_SIZE; i <= (offset + size - 1) / PAGE_SIZE; |
3240 | i++) { | |
05394f39 | 3241 | if (obj->page_cpu_valid[i]) |
673a394b EA |
3242 | continue; |
3243 | ||
05394f39 | 3244 | drm_clflush_pages(obj->pages + i, 1); |
673a394b | 3245 | |
05394f39 | 3246 | obj->page_cpu_valid[i] = 1; |
673a394b EA |
3247 | } |
3248 | ||
e47c68e9 EA |
3249 | /* It should now be out of any other write domains, and we can update |
3250 | * the domain values for our changes. | |
3251 | */ | |
05394f39 | 3252 | BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) != 0); |
e47c68e9 | 3253 | |
05394f39 CW |
3254 | old_read_domains = obj->base.read_domains; |
3255 | obj->base.read_domains |= I915_GEM_DOMAIN_CPU; | |
e47c68e9 | 3256 | |
1c5d22f7 CW |
3257 | trace_i915_gem_object_change_domain(obj, |
3258 | old_read_domains, | |
05394f39 | 3259 | obj->base.write_domain); |
1c5d22f7 | 3260 | |
673a394b EA |
3261 | return 0; |
3262 | } | |
3263 | ||
673a394b EA |
3264 | /* Throttle our rendering by waiting until the ring has completed our requests |
3265 | * emitted over 20 msec ago. | |
3266 | * | |
b962442e EA |
3267 | * Note that if we were to use the current jiffies each time around the loop, |
3268 | * we wouldn't escape the function with any frames outstanding if the time to | |
3269 | * render a frame was over 20ms. | |
3270 | * | |
673a394b EA |
3271 | * This should get us reasonable parallelism between CPU and GPU but also |
3272 | * relatively low latency when blocking on a particular request to finish. | |
3273 | */ | |
40a5f0de | 3274 | static int |
f787a5f5 | 3275 | i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file) |
40a5f0de | 3276 | { |
f787a5f5 CW |
3277 | struct drm_i915_private *dev_priv = dev->dev_private; |
3278 | struct drm_i915_file_private *file_priv = file->driver_priv; | |
b962442e | 3279 | unsigned long recent_enough = jiffies - msecs_to_jiffies(20); |
f787a5f5 CW |
3280 | struct drm_i915_gem_request *request; |
3281 | struct intel_ring_buffer *ring = NULL; | |
3282 | u32 seqno = 0; | |
3283 | int ret; | |
93533c29 | 3284 | |
e110e8d6 CW |
3285 | if (atomic_read(&dev_priv->mm.wedged)) |
3286 | return -EIO; | |
3287 | ||
1c25595f | 3288 | spin_lock(&file_priv->mm.lock); |
f787a5f5 | 3289 | list_for_each_entry(request, &file_priv->mm.request_list, client_list) { |
b962442e EA |
3290 | if (time_after_eq(request->emitted_jiffies, recent_enough)) |
3291 | break; | |
40a5f0de | 3292 | |
f787a5f5 CW |
3293 | ring = request->ring; |
3294 | seqno = request->seqno; | |
b962442e | 3295 | } |
1c25595f | 3296 | spin_unlock(&file_priv->mm.lock); |
40a5f0de | 3297 | |
f787a5f5 CW |
3298 | if (seqno == 0) |
3299 | return 0; | |
2bc43b5c | 3300 | |
f787a5f5 | 3301 | ret = 0; |
78501eac | 3302 | if (!i915_seqno_passed(ring->get_seqno(ring), seqno)) { |
f787a5f5 CW |
3303 | /* And wait for the seqno passing without holding any locks and |
3304 | * causing extra latency for others. This is safe as the irq | |
3305 | * generation is designed to be run atomically and so is | |
3306 | * lockless. | |
3307 | */ | |
b13c2b96 CW |
3308 | if (ring->irq_get(ring)) { |
3309 | ret = wait_event_interruptible(ring->irq_queue, | |
3310 | i915_seqno_passed(ring->get_seqno(ring), seqno) | |
3311 | || atomic_read(&dev_priv->mm.wedged)); | |
3312 | ring->irq_put(ring); | |
40a5f0de | 3313 | |
b13c2b96 CW |
3314 | if (ret == 0 && atomic_read(&dev_priv->mm.wedged)) |
3315 | ret = -EIO; | |
3316 | } | |
40a5f0de EA |
3317 | } |
3318 | ||
f787a5f5 CW |
3319 | if (ret == 0) |
3320 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, 0); | |
40a5f0de EA |
3321 | |
3322 | return ret; | |
3323 | } | |
3324 | ||
673a394b | 3325 | int |
05394f39 CW |
3326 | i915_gem_object_pin(struct drm_i915_gem_object *obj, |
3327 | uint32_t alignment, | |
75e9e915 | 3328 | bool map_and_fenceable) |
673a394b | 3329 | { |
05394f39 | 3330 | struct drm_device *dev = obj->base.dev; |
f13d3f73 | 3331 | struct drm_i915_private *dev_priv = dev->dev_private; |
673a394b EA |
3332 | int ret; |
3333 | ||
05394f39 | 3334 | BUG_ON(obj->pin_count == DRM_I915_GEM_OBJECT_MAX_PIN_COUNT); |
23bc5982 | 3335 | WARN_ON(i915_verify_lists(dev)); |
ac0c6b5a | 3336 | |
05394f39 CW |
3337 | if (obj->gtt_space != NULL) { |
3338 | if ((alignment && obj->gtt_offset & (alignment - 1)) || | |
3339 | (map_and_fenceable && !obj->map_and_fenceable)) { | |
3340 | WARN(obj->pin_count, | |
ae7d49d8 | 3341 | "bo is already pinned with incorrect alignment:" |
75e9e915 DV |
3342 | " offset=%x, req.alignment=%x, req.map_and_fenceable=%d," |
3343 | " obj->map_and_fenceable=%d\n", | |
05394f39 | 3344 | obj->gtt_offset, alignment, |
75e9e915 | 3345 | map_and_fenceable, |
05394f39 | 3346 | obj->map_and_fenceable); |
ac0c6b5a CW |
3347 | ret = i915_gem_object_unbind(obj); |
3348 | if (ret) | |
3349 | return ret; | |
3350 | } | |
3351 | } | |
3352 | ||
05394f39 | 3353 | if (obj->gtt_space == NULL) { |
a00b10c3 | 3354 | ret = i915_gem_object_bind_to_gtt(obj, alignment, |
75e9e915 | 3355 | map_and_fenceable); |
9731129c | 3356 | if (ret) |
673a394b | 3357 | return ret; |
22c344e9 | 3358 | } |
76446cac | 3359 | |
05394f39 | 3360 | if (obj->pin_count++ == 0) { |
05394f39 CW |
3361 | if (!obj->active) |
3362 | list_move_tail(&obj->mm_list, | |
f13d3f73 | 3363 | &dev_priv->mm.pinned_list); |
673a394b | 3364 | } |
6299f992 | 3365 | obj->pin_mappable |= map_and_fenceable; |
673a394b | 3366 | |
23bc5982 | 3367 | WARN_ON(i915_verify_lists(dev)); |
673a394b EA |
3368 | return 0; |
3369 | } | |
3370 | ||
3371 | void | |
05394f39 | 3372 | i915_gem_object_unpin(struct drm_i915_gem_object *obj) |
673a394b | 3373 | { |
05394f39 | 3374 | struct drm_device *dev = obj->base.dev; |
673a394b | 3375 | drm_i915_private_t *dev_priv = dev->dev_private; |
673a394b | 3376 | |
23bc5982 | 3377 | WARN_ON(i915_verify_lists(dev)); |
05394f39 CW |
3378 | BUG_ON(obj->pin_count == 0); |
3379 | BUG_ON(obj->gtt_space == NULL); | |
673a394b | 3380 | |
05394f39 CW |
3381 | if (--obj->pin_count == 0) { |
3382 | if (!obj->active) | |
3383 | list_move_tail(&obj->mm_list, | |
673a394b | 3384 | &dev_priv->mm.inactive_list); |
6299f992 | 3385 | obj->pin_mappable = false; |
673a394b | 3386 | } |
23bc5982 | 3387 | WARN_ON(i915_verify_lists(dev)); |
673a394b EA |
3388 | } |
3389 | ||
3390 | int | |
3391 | i915_gem_pin_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 3392 | struct drm_file *file) |
673a394b EA |
3393 | { |
3394 | struct drm_i915_gem_pin *args = data; | |
05394f39 | 3395 | struct drm_i915_gem_object *obj; |
673a394b EA |
3396 | int ret; |
3397 | ||
1d7cfea1 CW |
3398 | ret = i915_mutex_lock_interruptible(dev); |
3399 | if (ret) | |
3400 | return ret; | |
673a394b | 3401 | |
05394f39 | 3402 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 3403 | if (&obj->base == NULL) { |
1d7cfea1 CW |
3404 | ret = -ENOENT; |
3405 | goto unlock; | |
673a394b | 3406 | } |
673a394b | 3407 | |
05394f39 | 3408 | if (obj->madv != I915_MADV_WILLNEED) { |
bb6baf76 | 3409 | DRM_ERROR("Attempting to pin a purgeable buffer\n"); |
1d7cfea1 CW |
3410 | ret = -EINVAL; |
3411 | goto out; | |
3ef94daa CW |
3412 | } |
3413 | ||
05394f39 | 3414 | if (obj->pin_filp != NULL && obj->pin_filp != file) { |
79e53945 JB |
3415 | DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n", |
3416 | args->handle); | |
1d7cfea1 CW |
3417 | ret = -EINVAL; |
3418 | goto out; | |
79e53945 JB |
3419 | } |
3420 | ||
05394f39 CW |
3421 | obj->user_pin_count++; |
3422 | obj->pin_filp = file; | |
3423 | if (obj->user_pin_count == 1) { | |
75e9e915 | 3424 | ret = i915_gem_object_pin(obj, args->alignment, true); |
1d7cfea1 CW |
3425 | if (ret) |
3426 | goto out; | |
673a394b EA |
3427 | } |
3428 | ||
3429 | /* XXX - flush the CPU caches for pinned objects | |
3430 | * as the X server doesn't manage domains yet | |
3431 | */ | |
e47c68e9 | 3432 | i915_gem_object_flush_cpu_write_domain(obj); |
05394f39 | 3433 | args->offset = obj->gtt_offset; |
1d7cfea1 | 3434 | out: |
05394f39 | 3435 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 3436 | unlock: |
673a394b | 3437 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 3438 | return ret; |
673a394b EA |
3439 | } |
3440 | ||
3441 | int | |
3442 | i915_gem_unpin_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 3443 | struct drm_file *file) |
673a394b EA |
3444 | { |
3445 | struct drm_i915_gem_pin *args = data; | |
05394f39 | 3446 | struct drm_i915_gem_object *obj; |
76c1dec1 | 3447 | int ret; |
673a394b | 3448 | |
1d7cfea1 CW |
3449 | ret = i915_mutex_lock_interruptible(dev); |
3450 | if (ret) | |
3451 | return ret; | |
673a394b | 3452 | |
05394f39 | 3453 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 3454 | if (&obj->base == NULL) { |
1d7cfea1 CW |
3455 | ret = -ENOENT; |
3456 | goto unlock; | |
673a394b | 3457 | } |
76c1dec1 | 3458 | |
05394f39 | 3459 | if (obj->pin_filp != file) { |
79e53945 JB |
3460 | DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n", |
3461 | args->handle); | |
1d7cfea1 CW |
3462 | ret = -EINVAL; |
3463 | goto out; | |
79e53945 | 3464 | } |
05394f39 CW |
3465 | obj->user_pin_count--; |
3466 | if (obj->user_pin_count == 0) { | |
3467 | obj->pin_filp = NULL; | |
79e53945 JB |
3468 | i915_gem_object_unpin(obj); |
3469 | } | |
673a394b | 3470 | |
1d7cfea1 | 3471 | out: |
05394f39 | 3472 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 3473 | unlock: |
673a394b | 3474 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 3475 | return ret; |
673a394b EA |
3476 | } |
3477 | ||
3478 | int | |
3479 | i915_gem_busy_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 3480 | struct drm_file *file) |
673a394b EA |
3481 | { |
3482 | struct drm_i915_gem_busy *args = data; | |
05394f39 | 3483 | struct drm_i915_gem_object *obj; |
30dbf0c0 CW |
3484 | int ret; |
3485 | ||
76c1dec1 | 3486 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 3487 | if (ret) |
76c1dec1 | 3488 | return ret; |
673a394b | 3489 | |
05394f39 | 3490 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 3491 | if (&obj->base == NULL) { |
1d7cfea1 CW |
3492 | ret = -ENOENT; |
3493 | goto unlock; | |
673a394b | 3494 | } |
d1b851fc | 3495 | |
0be555b6 CW |
3496 | /* Count all active objects as busy, even if they are currently not used |
3497 | * by the gpu. Users of this interface expect objects to eventually | |
3498 | * become non-busy without any further actions, therefore emit any | |
3499 | * necessary flushes here. | |
c4de0a5d | 3500 | */ |
05394f39 | 3501 | args->busy = obj->active; |
0be555b6 CW |
3502 | if (args->busy) { |
3503 | /* Unconditionally flush objects, even when the gpu still uses this | |
3504 | * object. Userspace calling this function indicates that it wants to | |
3505 | * use this buffer rather sooner than later, so issuing the required | |
3506 | * flush earlier is beneficial. | |
3507 | */ | |
1a1c6976 | 3508 | if (obj->base.write_domain & I915_GEM_GPU_DOMAINS) { |
db53a302 | 3509 | ret = i915_gem_flush_ring(obj->ring, |
88241785 | 3510 | 0, obj->base.write_domain); |
1a1c6976 CW |
3511 | } else if (obj->ring->outstanding_lazy_request == |
3512 | obj->last_rendering_seqno) { | |
3513 | struct drm_i915_gem_request *request; | |
3514 | ||
7a194876 CW |
3515 | /* This ring is not being cleared by active usage, |
3516 | * so emit a request to do so. | |
3517 | */ | |
1a1c6976 CW |
3518 | request = kzalloc(sizeof(*request), GFP_KERNEL); |
3519 | if (request) | |
0206e353 | 3520 | ret = i915_add_request(obj->ring, NULL, request); |
1a1c6976 | 3521 | else |
7a194876 CW |
3522 | ret = -ENOMEM; |
3523 | } | |
0be555b6 CW |
3524 | |
3525 | /* Update the active list for the hardware's current position. | |
3526 | * Otherwise this only updates on a delayed timer or when irqs | |
3527 | * are actually unmasked, and our working set ends up being | |
3528 | * larger than required. | |
3529 | */ | |
db53a302 | 3530 | i915_gem_retire_requests_ring(obj->ring); |
0be555b6 | 3531 | |
05394f39 | 3532 | args->busy = obj->active; |
0be555b6 | 3533 | } |
673a394b | 3534 | |
05394f39 | 3535 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 3536 | unlock: |
673a394b | 3537 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 3538 | return ret; |
673a394b EA |
3539 | } |
3540 | ||
3541 | int | |
3542 | i915_gem_throttle_ioctl(struct drm_device *dev, void *data, | |
3543 | struct drm_file *file_priv) | |
3544 | { | |
0206e353 | 3545 | return i915_gem_ring_throttle(dev, file_priv); |
673a394b EA |
3546 | } |
3547 | ||
3ef94daa CW |
3548 | int |
3549 | i915_gem_madvise_ioctl(struct drm_device *dev, void *data, | |
3550 | struct drm_file *file_priv) | |
3551 | { | |
3552 | struct drm_i915_gem_madvise *args = data; | |
05394f39 | 3553 | struct drm_i915_gem_object *obj; |
76c1dec1 | 3554 | int ret; |
3ef94daa CW |
3555 | |
3556 | switch (args->madv) { | |
3557 | case I915_MADV_DONTNEED: | |
3558 | case I915_MADV_WILLNEED: | |
3559 | break; | |
3560 | default: | |
3561 | return -EINVAL; | |
3562 | } | |
3563 | ||
1d7cfea1 CW |
3564 | ret = i915_mutex_lock_interruptible(dev); |
3565 | if (ret) | |
3566 | return ret; | |
3567 | ||
05394f39 | 3568 | obj = to_intel_bo(drm_gem_object_lookup(dev, file_priv, args->handle)); |
c8725226 | 3569 | if (&obj->base == NULL) { |
1d7cfea1 CW |
3570 | ret = -ENOENT; |
3571 | goto unlock; | |
3ef94daa | 3572 | } |
3ef94daa | 3573 | |
05394f39 | 3574 | if (obj->pin_count) { |
1d7cfea1 CW |
3575 | ret = -EINVAL; |
3576 | goto out; | |
3ef94daa CW |
3577 | } |
3578 | ||
05394f39 CW |
3579 | if (obj->madv != __I915_MADV_PURGED) |
3580 | obj->madv = args->madv; | |
3ef94daa | 3581 | |
2d7ef395 | 3582 | /* if the object is no longer bound, discard its backing storage */ |
05394f39 CW |
3583 | if (i915_gem_object_is_purgeable(obj) && |
3584 | obj->gtt_space == NULL) | |
2d7ef395 CW |
3585 | i915_gem_object_truncate(obj); |
3586 | ||
05394f39 | 3587 | args->retained = obj->madv != __I915_MADV_PURGED; |
bb6baf76 | 3588 | |
1d7cfea1 | 3589 | out: |
05394f39 | 3590 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 3591 | unlock: |
3ef94daa | 3592 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 3593 | return ret; |
3ef94daa CW |
3594 | } |
3595 | ||
05394f39 CW |
3596 | struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev, |
3597 | size_t size) | |
ac52bc56 | 3598 | { |
73aa808f | 3599 | struct drm_i915_private *dev_priv = dev->dev_private; |
c397b908 | 3600 | struct drm_i915_gem_object *obj; |
5949eac4 | 3601 | struct address_space *mapping; |
ac52bc56 | 3602 | |
c397b908 DV |
3603 | obj = kzalloc(sizeof(*obj), GFP_KERNEL); |
3604 | if (obj == NULL) | |
3605 | return NULL; | |
673a394b | 3606 | |
c397b908 DV |
3607 | if (drm_gem_object_init(dev, &obj->base, size) != 0) { |
3608 | kfree(obj); | |
3609 | return NULL; | |
3610 | } | |
673a394b | 3611 | |
5949eac4 HD |
3612 | mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping; |
3613 | mapping_set_gfp_mask(mapping, GFP_HIGHUSER | __GFP_RECLAIMABLE); | |
3614 | ||
73aa808f CW |
3615 | i915_gem_info_add_obj(dev_priv, size); |
3616 | ||
c397b908 DV |
3617 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; |
3618 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; | |
673a394b | 3619 | |
a1871112 EA |
3620 | if (IS_GEN6(dev)) { |
3621 | /* On Gen6, we can have the GPU use the LLC (the CPU | |
3622 | * cache) for about a 10% performance improvement | |
3623 | * compared to uncached. Graphics requests other than | |
3624 | * display scanout are coherent with the CPU in | |
3625 | * accessing this cache. This means in this mode we | |
3626 | * don't need to clflush on the CPU side, and on the | |
3627 | * GPU side we only need to flush internal caches to | |
3628 | * get data visible to the CPU. | |
3629 | * | |
3630 | * However, we maintain the display planes as UC, and so | |
3631 | * need to rebind when first used as such. | |
3632 | */ | |
3633 | obj->cache_level = I915_CACHE_LLC; | |
3634 | } else | |
3635 | obj->cache_level = I915_CACHE_NONE; | |
3636 | ||
62b8b215 | 3637 | obj->base.driver_private = NULL; |
c397b908 | 3638 | obj->fence_reg = I915_FENCE_REG_NONE; |
69dc4987 | 3639 | INIT_LIST_HEAD(&obj->mm_list); |
93a37f20 | 3640 | INIT_LIST_HEAD(&obj->gtt_list); |
69dc4987 | 3641 | INIT_LIST_HEAD(&obj->ring_list); |
432e58ed | 3642 | INIT_LIST_HEAD(&obj->exec_list); |
c397b908 | 3643 | INIT_LIST_HEAD(&obj->gpu_write_list); |
c397b908 | 3644 | obj->madv = I915_MADV_WILLNEED; |
75e9e915 DV |
3645 | /* Avoid an unnecessary call to unbind on the first bind. */ |
3646 | obj->map_and_fenceable = true; | |
de151cf6 | 3647 | |
05394f39 | 3648 | return obj; |
c397b908 DV |
3649 | } |
3650 | ||
3651 | int i915_gem_init_object(struct drm_gem_object *obj) | |
3652 | { | |
3653 | BUG(); | |
de151cf6 | 3654 | |
673a394b EA |
3655 | return 0; |
3656 | } | |
3657 | ||
05394f39 | 3658 | static void i915_gem_free_object_tail(struct drm_i915_gem_object *obj) |
673a394b | 3659 | { |
05394f39 | 3660 | struct drm_device *dev = obj->base.dev; |
be72615b | 3661 | drm_i915_private_t *dev_priv = dev->dev_private; |
be72615b | 3662 | int ret; |
673a394b | 3663 | |
be72615b CW |
3664 | ret = i915_gem_object_unbind(obj); |
3665 | if (ret == -ERESTARTSYS) { | |
05394f39 | 3666 | list_move(&obj->mm_list, |
be72615b CW |
3667 | &dev_priv->mm.deferred_free_list); |
3668 | return; | |
3669 | } | |
673a394b | 3670 | |
26e12f89 CW |
3671 | trace_i915_gem_object_destroy(obj); |
3672 | ||
05394f39 | 3673 | if (obj->base.map_list.map) |
b464e9a2 | 3674 | drm_gem_free_mmap_offset(&obj->base); |
de151cf6 | 3675 | |
05394f39 CW |
3676 | drm_gem_object_release(&obj->base); |
3677 | i915_gem_info_remove_obj(dev_priv, obj->base.size); | |
c397b908 | 3678 | |
05394f39 CW |
3679 | kfree(obj->page_cpu_valid); |
3680 | kfree(obj->bit_17); | |
3681 | kfree(obj); | |
673a394b EA |
3682 | } |
3683 | ||
05394f39 | 3684 | void i915_gem_free_object(struct drm_gem_object *gem_obj) |
be72615b | 3685 | { |
05394f39 CW |
3686 | struct drm_i915_gem_object *obj = to_intel_bo(gem_obj); |
3687 | struct drm_device *dev = obj->base.dev; | |
be72615b | 3688 | |
05394f39 | 3689 | while (obj->pin_count > 0) |
be72615b CW |
3690 | i915_gem_object_unpin(obj); |
3691 | ||
05394f39 | 3692 | if (obj->phys_obj) |
be72615b CW |
3693 | i915_gem_detach_phys_object(dev, obj); |
3694 | ||
3695 | i915_gem_free_object_tail(obj); | |
3696 | } | |
3697 | ||
29105ccc CW |
3698 | int |
3699 | i915_gem_idle(struct drm_device *dev) | |
3700 | { | |
3701 | drm_i915_private_t *dev_priv = dev->dev_private; | |
3702 | int ret; | |
28dfe52a | 3703 | |
29105ccc | 3704 | mutex_lock(&dev->struct_mutex); |
1c5d22f7 | 3705 | |
87acb0a5 | 3706 | if (dev_priv->mm.suspended) { |
29105ccc CW |
3707 | mutex_unlock(&dev->struct_mutex); |
3708 | return 0; | |
28dfe52a EA |
3709 | } |
3710 | ||
29105ccc | 3711 | ret = i915_gpu_idle(dev); |
6dbe2772 KP |
3712 | if (ret) { |
3713 | mutex_unlock(&dev->struct_mutex); | |
673a394b | 3714 | return ret; |
6dbe2772 | 3715 | } |
673a394b | 3716 | |
29105ccc CW |
3717 | /* Under UMS, be paranoid and evict. */ |
3718 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) { | |
5eac3ab4 | 3719 | ret = i915_gem_evict_inactive(dev, false); |
29105ccc CW |
3720 | if (ret) { |
3721 | mutex_unlock(&dev->struct_mutex); | |
3722 | return ret; | |
3723 | } | |
3724 | } | |
3725 | ||
312817a3 CW |
3726 | i915_gem_reset_fences(dev); |
3727 | ||
29105ccc CW |
3728 | /* Hack! Don't let anybody do execbuf while we don't control the chip. |
3729 | * We need to replace this with a semaphore, or something. | |
3730 | * And not confound mm.suspended! | |
3731 | */ | |
3732 | dev_priv->mm.suspended = 1; | |
bc0c7f14 | 3733 | del_timer_sync(&dev_priv->hangcheck_timer); |
29105ccc CW |
3734 | |
3735 | i915_kernel_lost_context(dev); | |
6dbe2772 | 3736 | i915_gem_cleanup_ringbuffer(dev); |
29105ccc | 3737 | |
6dbe2772 KP |
3738 | mutex_unlock(&dev->struct_mutex); |
3739 | ||
29105ccc CW |
3740 | /* Cancel the retire work handler, which should be idle now. */ |
3741 | cancel_delayed_work_sync(&dev_priv->mm.retire_work); | |
3742 | ||
673a394b EA |
3743 | return 0; |
3744 | } | |
3745 | ||
8187a2b7 ZN |
3746 | int |
3747 | i915_gem_init_ringbuffer(struct drm_device *dev) | |
3748 | { | |
3749 | drm_i915_private_t *dev_priv = dev->dev_private; | |
3750 | int ret; | |
68f95ba9 | 3751 | |
5c1143bb | 3752 | ret = intel_init_render_ring_buffer(dev); |
68f95ba9 | 3753 | if (ret) |
b6913e4b | 3754 | return ret; |
68f95ba9 CW |
3755 | |
3756 | if (HAS_BSD(dev)) { | |
5c1143bb | 3757 | ret = intel_init_bsd_ring_buffer(dev); |
68f95ba9 CW |
3758 | if (ret) |
3759 | goto cleanup_render_ring; | |
d1b851fc | 3760 | } |
68f95ba9 | 3761 | |
549f7365 CW |
3762 | if (HAS_BLT(dev)) { |
3763 | ret = intel_init_blt_ring_buffer(dev); | |
3764 | if (ret) | |
3765 | goto cleanup_bsd_ring; | |
3766 | } | |
3767 | ||
6f392d54 CW |
3768 | dev_priv->next_seqno = 1; |
3769 | ||
68f95ba9 CW |
3770 | return 0; |
3771 | ||
549f7365 | 3772 | cleanup_bsd_ring: |
1ec14ad3 | 3773 | intel_cleanup_ring_buffer(&dev_priv->ring[VCS]); |
68f95ba9 | 3774 | cleanup_render_ring: |
1ec14ad3 | 3775 | intel_cleanup_ring_buffer(&dev_priv->ring[RCS]); |
8187a2b7 ZN |
3776 | return ret; |
3777 | } | |
3778 | ||
3779 | void | |
3780 | i915_gem_cleanup_ringbuffer(struct drm_device *dev) | |
3781 | { | |
3782 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1ec14ad3 | 3783 | int i; |
8187a2b7 | 3784 | |
1ec14ad3 CW |
3785 | for (i = 0; i < I915_NUM_RINGS; i++) |
3786 | intel_cleanup_ring_buffer(&dev_priv->ring[i]); | |
8187a2b7 ZN |
3787 | } |
3788 | ||
673a394b EA |
3789 | int |
3790 | i915_gem_entervt_ioctl(struct drm_device *dev, void *data, | |
3791 | struct drm_file *file_priv) | |
3792 | { | |
3793 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1ec14ad3 | 3794 | int ret, i; |
673a394b | 3795 | |
79e53945 JB |
3796 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
3797 | return 0; | |
3798 | ||
ba1234d1 | 3799 | if (atomic_read(&dev_priv->mm.wedged)) { |
673a394b | 3800 | DRM_ERROR("Reenabling wedged hardware, good luck\n"); |
ba1234d1 | 3801 | atomic_set(&dev_priv->mm.wedged, 0); |
673a394b EA |
3802 | } |
3803 | ||
673a394b | 3804 | mutex_lock(&dev->struct_mutex); |
9bb2d6f9 EA |
3805 | dev_priv->mm.suspended = 0; |
3806 | ||
3807 | ret = i915_gem_init_ringbuffer(dev); | |
d816f6ac WF |
3808 | if (ret != 0) { |
3809 | mutex_unlock(&dev->struct_mutex); | |
9bb2d6f9 | 3810 | return ret; |
d816f6ac | 3811 | } |
9bb2d6f9 | 3812 | |
69dc4987 | 3813 | BUG_ON(!list_empty(&dev_priv->mm.active_list)); |
673a394b EA |
3814 | BUG_ON(!list_empty(&dev_priv->mm.flushing_list)); |
3815 | BUG_ON(!list_empty(&dev_priv->mm.inactive_list)); | |
1ec14ad3 CW |
3816 | for (i = 0; i < I915_NUM_RINGS; i++) { |
3817 | BUG_ON(!list_empty(&dev_priv->ring[i].active_list)); | |
3818 | BUG_ON(!list_empty(&dev_priv->ring[i].request_list)); | |
3819 | } | |
673a394b | 3820 | mutex_unlock(&dev->struct_mutex); |
dbb19d30 | 3821 | |
5f35308b CW |
3822 | ret = drm_irq_install(dev); |
3823 | if (ret) | |
3824 | goto cleanup_ringbuffer; | |
dbb19d30 | 3825 | |
673a394b | 3826 | return 0; |
5f35308b CW |
3827 | |
3828 | cleanup_ringbuffer: | |
3829 | mutex_lock(&dev->struct_mutex); | |
3830 | i915_gem_cleanup_ringbuffer(dev); | |
3831 | dev_priv->mm.suspended = 1; | |
3832 | mutex_unlock(&dev->struct_mutex); | |
3833 | ||
3834 | return ret; | |
673a394b EA |
3835 | } |
3836 | ||
3837 | int | |
3838 | i915_gem_leavevt_ioctl(struct drm_device *dev, void *data, | |
3839 | struct drm_file *file_priv) | |
3840 | { | |
79e53945 JB |
3841 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
3842 | return 0; | |
3843 | ||
dbb19d30 | 3844 | drm_irq_uninstall(dev); |
e6890f6f | 3845 | return i915_gem_idle(dev); |
673a394b EA |
3846 | } |
3847 | ||
3848 | void | |
3849 | i915_gem_lastclose(struct drm_device *dev) | |
3850 | { | |
3851 | int ret; | |
673a394b | 3852 | |
e806b495 EA |
3853 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
3854 | return; | |
3855 | ||
6dbe2772 KP |
3856 | ret = i915_gem_idle(dev); |
3857 | if (ret) | |
3858 | DRM_ERROR("failed to idle hardware: %d\n", ret); | |
673a394b EA |
3859 | } |
3860 | ||
64193406 CW |
3861 | static void |
3862 | init_ring_lists(struct intel_ring_buffer *ring) | |
3863 | { | |
3864 | INIT_LIST_HEAD(&ring->active_list); | |
3865 | INIT_LIST_HEAD(&ring->request_list); | |
3866 | INIT_LIST_HEAD(&ring->gpu_write_list); | |
3867 | } | |
3868 | ||
673a394b EA |
3869 | void |
3870 | i915_gem_load(struct drm_device *dev) | |
3871 | { | |
b5aa8a0f | 3872 | int i; |
673a394b EA |
3873 | drm_i915_private_t *dev_priv = dev->dev_private; |
3874 | ||
69dc4987 | 3875 | INIT_LIST_HEAD(&dev_priv->mm.active_list); |
673a394b EA |
3876 | INIT_LIST_HEAD(&dev_priv->mm.flushing_list); |
3877 | INIT_LIST_HEAD(&dev_priv->mm.inactive_list); | |
f13d3f73 | 3878 | INIT_LIST_HEAD(&dev_priv->mm.pinned_list); |
a09ba7fa | 3879 | INIT_LIST_HEAD(&dev_priv->mm.fence_list); |
be72615b | 3880 | INIT_LIST_HEAD(&dev_priv->mm.deferred_free_list); |
93a37f20 | 3881 | INIT_LIST_HEAD(&dev_priv->mm.gtt_list); |
1ec14ad3 CW |
3882 | for (i = 0; i < I915_NUM_RINGS; i++) |
3883 | init_ring_lists(&dev_priv->ring[i]); | |
007cc8ac DV |
3884 | for (i = 0; i < 16; i++) |
3885 | INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list); | |
673a394b EA |
3886 | INIT_DELAYED_WORK(&dev_priv->mm.retire_work, |
3887 | i915_gem_retire_work_handler); | |
30dbf0c0 | 3888 | init_completion(&dev_priv->error_completion); |
31169714 | 3889 | |
94400120 DA |
3890 | /* On GEN3 we really need to make sure the ARB C3 LP bit is set */ |
3891 | if (IS_GEN3(dev)) { | |
3892 | u32 tmp = I915_READ(MI_ARB_STATE); | |
3893 | if (!(tmp & MI_ARB_C3_LP_WRITE_ENABLE)) { | |
3894 | /* arb state is a masked write, so set bit + bit in mask */ | |
3895 | tmp = MI_ARB_C3_LP_WRITE_ENABLE | (MI_ARB_C3_LP_WRITE_ENABLE << MI_ARB_MASK_SHIFT); | |
3896 | I915_WRITE(MI_ARB_STATE, tmp); | |
3897 | } | |
3898 | } | |
3899 | ||
72bfa19c CW |
3900 | dev_priv->relative_constants_mode = I915_EXEC_CONSTANTS_REL_GENERAL; |
3901 | ||
de151cf6 | 3902 | /* Old X drivers will take 0-2 for front, back, depth buffers */ |
b397c836 EA |
3903 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) |
3904 | dev_priv->fence_reg_start = 3; | |
de151cf6 | 3905 | |
a6c45cf0 | 3906 | if (INTEL_INFO(dev)->gen >= 4 || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) |
de151cf6 JB |
3907 | dev_priv->num_fence_regs = 16; |
3908 | else | |
3909 | dev_priv->num_fence_regs = 8; | |
3910 | ||
b5aa8a0f | 3911 | /* Initialize fence registers to zero */ |
10ed13e4 EA |
3912 | for (i = 0; i < dev_priv->num_fence_regs; i++) { |
3913 | i915_gem_clear_fence_reg(dev, &dev_priv->fence_regs[i]); | |
b5aa8a0f | 3914 | } |
10ed13e4 | 3915 | |
673a394b | 3916 | i915_gem_detect_bit_6_swizzle(dev); |
6b95a207 | 3917 | init_waitqueue_head(&dev_priv->pending_flip_queue); |
17250b71 | 3918 | |
ce453d81 CW |
3919 | dev_priv->mm.interruptible = true; |
3920 | ||
17250b71 CW |
3921 | dev_priv->mm.inactive_shrinker.shrink = i915_gem_inactive_shrink; |
3922 | dev_priv->mm.inactive_shrinker.seeks = DEFAULT_SEEKS; | |
3923 | register_shrinker(&dev_priv->mm.inactive_shrinker); | |
673a394b | 3924 | } |
71acb5eb DA |
3925 | |
3926 | /* | |
3927 | * Create a physically contiguous memory object for this object | |
3928 | * e.g. for cursor + overlay regs | |
3929 | */ | |
995b6762 CW |
3930 | static int i915_gem_init_phys_object(struct drm_device *dev, |
3931 | int id, int size, int align) | |
71acb5eb DA |
3932 | { |
3933 | drm_i915_private_t *dev_priv = dev->dev_private; | |
3934 | struct drm_i915_gem_phys_object *phys_obj; | |
3935 | int ret; | |
3936 | ||
3937 | if (dev_priv->mm.phys_objs[id - 1] || !size) | |
3938 | return 0; | |
3939 | ||
9a298b2a | 3940 | phys_obj = kzalloc(sizeof(struct drm_i915_gem_phys_object), GFP_KERNEL); |
71acb5eb DA |
3941 | if (!phys_obj) |
3942 | return -ENOMEM; | |
3943 | ||
3944 | phys_obj->id = id; | |
3945 | ||
6eeefaf3 | 3946 | phys_obj->handle = drm_pci_alloc(dev, size, align); |
71acb5eb DA |
3947 | if (!phys_obj->handle) { |
3948 | ret = -ENOMEM; | |
3949 | goto kfree_obj; | |
3950 | } | |
3951 | #ifdef CONFIG_X86 | |
3952 | set_memory_wc((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE); | |
3953 | #endif | |
3954 | ||
3955 | dev_priv->mm.phys_objs[id - 1] = phys_obj; | |
3956 | ||
3957 | return 0; | |
3958 | kfree_obj: | |
9a298b2a | 3959 | kfree(phys_obj); |
71acb5eb DA |
3960 | return ret; |
3961 | } | |
3962 | ||
995b6762 | 3963 | static void i915_gem_free_phys_object(struct drm_device *dev, int id) |
71acb5eb DA |
3964 | { |
3965 | drm_i915_private_t *dev_priv = dev->dev_private; | |
3966 | struct drm_i915_gem_phys_object *phys_obj; | |
3967 | ||
3968 | if (!dev_priv->mm.phys_objs[id - 1]) | |
3969 | return; | |
3970 | ||
3971 | phys_obj = dev_priv->mm.phys_objs[id - 1]; | |
3972 | if (phys_obj->cur_obj) { | |
3973 | i915_gem_detach_phys_object(dev, phys_obj->cur_obj); | |
3974 | } | |
3975 | ||
3976 | #ifdef CONFIG_X86 | |
3977 | set_memory_wb((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE); | |
3978 | #endif | |
3979 | drm_pci_free(dev, phys_obj->handle); | |
3980 | kfree(phys_obj); | |
3981 | dev_priv->mm.phys_objs[id - 1] = NULL; | |
3982 | } | |
3983 | ||
3984 | void i915_gem_free_all_phys_object(struct drm_device *dev) | |
3985 | { | |
3986 | int i; | |
3987 | ||
260883c8 | 3988 | for (i = I915_GEM_PHYS_CURSOR_0; i <= I915_MAX_PHYS_OBJECT; i++) |
71acb5eb DA |
3989 | i915_gem_free_phys_object(dev, i); |
3990 | } | |
3991 | ||
3992 | void i915_gem_detach_phys_object(struct drm_device *dev, | |
05394f39 | 3993 | struct drm_i915_gem_object *obj) |
71acb5eb | 3994 | { |
05394f39 | 3995 | struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping; |
e5281ccd | 3996 | char *vaddr; |
71acb5eb | 3997 | int i; |
71acb5eb DA |
3998 | int page_count; |
3999 | ||
05394f39 | 4000 | if (!obj->phys_obj) |
71acb5eb | 4001 | return; |
05394f39 | 4002 | vaddr = obj->phys_obj->handle->vaddr; |
71acb5eb | 4003 | |
05394f39 | 4004 | page_count = obj->base.size / PAGE_SIZE; |
71acb5eb | 4005 | for (i = 0; i < page_count; i++) { |
5949eac4 | 4006 | struct page *page = shmem_read_mapping_page(mapping, i); |
e5281ccd CW |
4007 | if (!IS_ERR(page)) { |
4008 | char *dst = kmap_atomic(page); | |
4009 | memcpy(dst, vaddr + i*PAGE_SIZE, PAGE_SIZE); | |
4010 | kunmap_atomic(dst); | |
4011 | ||
4012 | drm_clflush_pages(&page, 1); | |
4013 | ||
4014 | set_page_dirty(page); | |
4015 | mark_page_accessed(page); | |
4016 | page_cache_release(page); | |
4017 | } | |
71acb5eb | 4018 | } |
40ce6575 | 4019 | intel_gtt_chipset_flush(); |
d78b47b9 | 4020 | |
05394f39 CW |
4021 | obj->phys_obj->cur_obj = NULL; |
4022 | obj->phys_obj = NULL; | |
71acb5eb DA |
4023 | } |
4024 | ||
4025 | int | |
4026 | i915_gem_attach_phys_object(struct drm_device *dev, | |
05394f39 | 4027 | struct drm_i915_gem_object *obj, |
6eeefaf3 CW |
4028 | int id, |
4029 | int align) | |
71acb5eb | 4030 | { |
05394f39 | 4031 | struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping; |
71acb5eb | 4032 | drm_i915_private_t *dev_priv = dev->dev_private; |
71acb5eb DA |
4033 | int ret = 0; |
4034 | int page_count; | |
4035 | int i; | |
4036 | ||
4037 | if (id > I915_MAX_PHYS_OBJECT) | |
4038 | return -EINVAL; | |
4039 | ||
05394f39 CW |
4040 | if (obj->phys_obj) { |
4041 | if (obj->phys_obj->id == id) | |
71acb5eb DA |
4042 | return 0; |
4043 | i915_gem_detach_phys_object(dev, obj); | |
4044 | } | |
4045 | ||
71acb5eb DA |
4046 | /* create a new object */ |
4047 | if (!dev_priv->mm.phys_objs[id - 1]) { | |
4048 | ret = i915_gem_init_phys_object(dev, id, | |
05394f39 | 4049 | obj->base.size, align); |
71acb5eb | 4050 | if (ret) { |
05394f39 CW |
4051 | DRM_ERROR("failed to init phys object %d size: %zu\n", |
4052 | id, obj->base.size); | |
e5281ccd | 4053 | return ret; |
71acb5eb DA |
4054 | } |
4055 | } | |
4056 | ||
4057 | /* bind to the object */ | |
05394f39 CW |
4058 | obj->phys_obj = dev_priv->mm.phys_objs[id - 1]; |
4059 | obj->phys_obj->cur_obj = obj; | |
71acb5eb | 4060 | |
05394f39 | 4061 | page_count = obj->base.size / PAGE_SIZE; |
71acb5eb DA |
4062 | |
4063 | for (i = 0; i < page_count; i++) { | |
e5281ccd CW |
4064 | struct page *page; |
4065 | char *dst, *src; | |
4066 | ||
5949eac4 | 4067 | page = shmem_read_mapping_page(mapping, i); |
e5281ccd CW |
4068 | if (IS_ERR(page)) |
4069 | return PTR_ERR(page); | |
71acb5eb | 4070 | |
ff75b9bc | 4071 | src = kmap_atomic(page); |
05394f39 | 4072 | dst = obj->phys_obj->handle->vaddr + (i * PAGE_SIZE); |
71acb5eb | 4073 | memcpy(dst, src, PAGE_SIZE); |
3e4d3af5 | 4074 | kunmap_atomic(src); |
71acb5eb | 4075 | |
e5281ccd CW |
4076 | mark_page_accessed(page); |
4077 | page_cache_release(page); | |
4078 | } | |
d78b47b9 | 4079 | |
71acb5eb | 4080 | return 0; |
71acb5eb DA |
4081 | } |
4082 | ||
4083 | static int | |
05394f39 CW |
4084 | i915_gem_phys_pwrite(struct drm_device *dev, |
4085 | struct drm_i915_gem_object *obj, | |
71acb5eb DA |
4086 | struct drm_i915_gem_pwrite *args, |
4087 | struct drm_file *file_priv) | |
4088 | { | |
05394f39 | 4089 | void *vaddr = obj->phys_obj->handle->vaddr + args->offset; |
b47b30cc | 4090 | char __user *user_data = (char __user *) (uintptr_t) args->data_ptr; |
71acb5eb | 4091 | |
b47b30cc CW |
4092 | if (__copy_from_user_inatomic_nocache(vaddr, user_data, args->size)) { |
4093 | unsigned long unwritten; | |
4094 | ||
4095 | /* The physical object once assigned is fixed for the lifetime | |
4096 | * of the obj, so we can safely drop the lock and continue | |
4097 | * to access vaddr. | |
4098 | */ | |
4099 | mutex_unlock(&dev->struct_mutex); | |
4100 | unwritten = copy_from_user(vaddr, user_data, args->size); | |
4101 | mutex_lock(&dev->struct_mutex); | |
4102 | if (unwritten) | |
4103 | return -EFAULT; | |
4104 | } | |
71acb5eb | 4105 | |
40ce6575 | 4106 | intel_gtt_chipset_flush(); |
71acb5eb DA |
4107 | return 0; |
4108 | } | |
b962442e | 4109 | |
f787a5f5 | 4110 | void i915_gem_release(struct drm_device *dev, struct drm_file *file) |
b962442e | 4111 | { |
f787a5f5 | 4112 | struct drm_i915_file_private *file_priv = file->driver_priv; |
b962442e EA |
4113 | |
4114 | /* Clean up our request list when the client is going away, so that | |
4115 | * later retire_requests won't dereference our soon-to-be-gone | |
4116 | * file_priv. | |
4117 | */ | |
1c25595f | 4118 | spin_lock(&file_priv->mm.lock); |
f787a5f5 CW |
4119 | while (!list_empty(&file_priv->mm.request_list)) { |
4120 | struct drm_i915_gem_request *request; | |
4121 | ||
4122 | request = list_first_entry(&file_priv->mm.request_list, | |
4123 | struct drm_i915_gem_request, | |
4124 | client_list); | |
4125 | list_del(&request->client_list); | |
4126 | request->file_priv = NULL; | |
4127 | } | |
1c25595f | 4128 | spin_unlock(&file_priv->mm.lock); |
b962442e | 4129 | } |
31169714 | 4130 | |
1637ef41 CW |
4131 | static int |
4132 | i915_gpu_is_active(struct drm_device *dev) | |
4133 | { | |
4134 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4135 | int lists_empty; | |
4136 | ||
1637ef41 | 4137 | lists_empty = list_empty(&dev_priv->mm.flushing_list) && |
17250b71 | 4138 | list_empty(&dev_priv->mm.active_list); |
1637ef41 CW |
4139 | |
4140 | return !lists_empty; | |
4141 | } | |
4142 | ||
31169714 | 4143 | static int |
1495f230 | 4144 | i915_gem_inactive_shrink(struct shrinker *shrinker, struct shrink_control *sc) |
31169714 | 4145 | { |
17250b71 CW |
4146 | struct drm_i915_private *dev_priv = |
4147 | container_of(shrinker, | |
4148 | struct drm_i915_private, | |
4149 | mm.inactive_shrinker); | |
4150 | struct drm_device *dev = dev_priv->dev; | |
4151 | struct drm_i915_gem_object *obj, *next; | |
1495f230 | 4152 | int nr_to_scan = sc->nr_to_scan; |
17250b71 CW |
4153 | int cnt; |
4154 | ||
4155 | if (!mutex_trylock(&dev->struct_mutex)) | |
bbe2e11a | 4156 | return 0; |
31169714 CW |
4157 | |
4158 | /* "fast-path" to count number of available objects */ | |
4159 | if (nr_to_scan == 0) { | |
17250b71 CW |
4160 | cnt = 0; |
4161 | list_for_each_entry(obj, | |
4162 | &dev_priv->mm.inactive_list, | |
4163 | mm_list) | |
4164 | cnt++; | |
4165 | mutex_unlock(&dev->struct_mutex); | |
4166 | return cnt / 100 * sysctl_vfs_cache_pressure; | |
31169714 CW |
4167 | } |
4168 | ||
1637ef41 | 4169 | rescan: |
31169714 | 4170 | /* first scan for clean buffers */ |
17250b71 | 4171 | i915_gem_retire_requests(dev); |
31169714 | 4172 | |
17250b71 CW |
4173 | list_for_each_entry_safe(obj, next, |
4174 | &dev_priv->mm.inactive_list, | |
4175 | mm_list) { | |
4176 | if (i915_gem_object_is_purgeable(obj)) { | |
2021746e CW |
4177 | if (i915_gem_object_unbind(obj) == 0 && |
4178 | --nr_to_scan == 0) | |
17250b71 | 4179 | break; |
31169714 | 4180 | } |
31169714 CW |
4181 | } |
4182 | ||
4183 | /* second pass, evict/count anything still on the inactive list */ | |
17250b71 CW |
4184 | cnt = 0; |
4185 | list_for_each_entry_safe(obj, next, | |
4186 | &dev_priv->mm.inactive_list, | |
4187 | mm_list) { | |
2021746e CW |
4188 | if (nr_to_scan && |
4189 | i915_gem_object_unbind(obj) == 0) | |
17250b71 | 4190 | nr_to_scan--; |
2021746e | 4191 | else |
17250b71 CW |
4192 | cnt++; |
4193 | } | |
4194 | ||
4195 | if (nr_to_scan && i915_gpu_is_active(dev)) { | |
1637ef41 CW |
4196 | /* |
4197 | * We are desperate for pages, so as a last resort, wait | |
4198 | * for the GPU to finish and discard whatever we can. | |
4199 | * This has a dramatic impact to reduce the number of | |
4200 | * OOM-killer events whilst running the GPU aggressively. | |
4201 | */ | |
17250b71 | 4202 | if (i915_gpu_idle(dev) == 0) |
1637ef41 CW |
4203 | goto rescan; |
4204 | } | |
17250b71 CW |
4205 | mutex_unlock(&dev->struct_mutex); |
4206 | return cnt / 100 * sysctl_vfs_cache_pressure; | |
31169714 | 4207 | } |