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673a394b | 1 | /* |
be6a0376 | 2 | * Copyright © 2008-2015 Intel Corporation |
673a394b EA |
3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | * | |
26 | */ | |
27 | ||
760285e7 | 28 | #include <drm/drmP.h> |
0de23977 | 29 | #include <drm/drm_vma_manager.h> |
760285e7 | 30 | #include <drm/i915_drm.h> |
673a394b | 31 | #include "i915_drv.h" |
eb82289a | 32 | #include "i915_vgpu.h" |
1c5d22f7 | 33 | #include "i915_trace.h" |
652c393a | 34 | #include "intel_drv.h" |
5d723d7a | 35 | #include "intel_frontbuffer.h" |
0ccdacf6 | 36 | #include "intel_mocs.h" |
6b5e90f5 | 37 | #include <linux/dma-fence-array.h> |
fe3288b5 | 38 | #include <linux/kthread.h> |
c13d87ea | 39 | #include <linux/reservation.h> |
5949eac4 | 40 | #include <linux/shmem_fs.h> |
5a0e3ad6 | 41 | #include <linux/slab.h> |
20e4933c | 42 | #include <linux/stop_machine.h> |
673a394b | 43 | #include <linux/swap.h> |
79e53945 | 44 | #include <linux/pci.h> |
1286ff73 | 45 | #include <linux/dma-buf.h> |
673a394b | 46 | |
fbbd37b3 | 47 | static void i915_gem_flush_free_objects(struct drm_i915_private *i915); |
05394f39 | 48 | static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj); |
e62b59e4 | 49 | static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj); |
61050808 | 50 | |
c76ce038 CW |
51 | static bool cpu_cache_is_coherent(struct drm_device *dev, |
52 | enum i915_cache_level level) | |
53 | { | |
0031fb96 | 54 | return HAS_LLC(to_i915(dev)) || level != I915_CACHE_NONE; |
c76ce038 CW |
55 | } |
56 | ||
2c22569b CW |
57 | static bool cpu_write_needs_clflush(struct drm_i915_gem_object *obj) |
58 | { | |
b50a5371 AS |
59 | if (obj->base.write_domain == I915_GEM_DOMAIN_CPU) |
60 | return false; | |
61 | ||
2c22569b CW |
62 | if (!cpu_cache_is_coherent(obj->base.dev, obj->cache_level)) |
63 | return true; | |
64 | ||
65 | return obj->pin_display; | |
66 | } | |
67 | ||
4f1959ee | 68 | static int |
bb6dc8d9 | 69 | insert_mappable_node(struct i915_ggtt *ggtt, |
4f1959ee AS |
70 | struct drm_mm_node *node, u32 size) |
71 | { | |
72 | memset(node, 0, sizeof(*node)); | |
4e64e553 CW |
73 | return drm_mm_insert_node_in_range(&ggtt->base.mm, node, |
74 | size, 0, I915_COLOR_UNEVICTABLE, | |
75 | 0, ggtt->mappable_end, | |
76 | DRM_MM_INSERT_LOW); | |
4f1959ee AS |
77 | } |
78 | ||
79 | static void | |
80 | remove_mappable_node(struct drm_mm_node *node) | |
81 | { | |
82 | drm_mm_remove_node(node); | |
83 | } | |
84 | ||
73aa808f CW |
85 | /* some bookkeeping */ |
86 | static void i915_gem_info_add_obj(struct drm_i915_private *dev_priv, | |
3ef7f228 | 87 | u64 size) |
73aa808f | 88 | { |
c20e8355 | 89 | spin_lock(&dev_priv->mm.object_stat_lock); |
73aa808f CW |
90 | dev_priv->mm.object_count++; |
91 | dev_priv->mm.object_memory += size; | |
c20e8355 | 92 | spin_unlock(&dev_priv->mm.object_stat_lock); |
73aa808f CW |
93 | } |
94 | ||
95 | static void i915_gem_info_remove_obj(struct drm_i915_private *dev_priv, | |
3ef7f228 | 96 | u64 size) |
73aa808f | 97 | { |
c20e8355 | 98 | spin_lock(&dev_priv->mm.object_stat_lock); |
73aa808f CW |
99 | dev_priv->mm.object_count--; |
100 | dev_priv->mm.object_memory -= size; | |
c20e8355 | 101 | spin_unlock(&dev_priv->mm.object_stat_lock); |
73aa808f CW |
102 | } |
103 | ||
21dd3734 | 104 | static int |
33196ded | 105 | i915_gem_wait_for_error(struct i915_gpu_error *error) |
30dbf0c0 | 106 | { |
30dbf0c0 CW |
107 | int ret; |
108 | ||
4c7d62c6 CW |
109 | might_sleep(); |
110 | ||
d98c52cf | 111 | if (!i915_reset_in_progress(error)) |
30dbf0c0 CW |
112 | return 0; |
113 | ||
0a6759c6 DV |
114 | /* |
115 | * Only wait 10 seconds for the gpu reset to complete to avoid hanging | |
116 | * userspace. If it takes that long something really bad is going on and | |
117 | * we should simply try to bail out and fail as gracefully as possible. | |
118 | */ | |
1f83fee0 | 119 | ret = wait_event_interruptible_timeout(error->reset_queue, |
d98c52cf | 120 | !i915_reset_in_progress(error), |
b52992c0 | 121 | I915_RESET_TIMEOUT); |
0a6759c6 DV |
122 | if (ret == 0) { |
123 | DRM_ERROR("Timed out waiting for the gpu reset to complete\n"); | |
124 | return -EIO; | |
125 | } else if (ret < 0) { | |
30dbf0c0 | 126 | return ret; |
d98c52cf CW |
127 | } else { |
128 | return 0; | |
0a6759c6 | 129 | } |
30dbf0c0 CW |
130 | } |
131 | ||
54cf91dc | 132 | int i915_mutex_lock_interruptible(struct drm_device *dev) |
76c1dec1 | 133 | { |
fac5e23e | 134 | struct drm_i915_private *dev_priv = to_i915(dev); |
76c1dec1 CW |
135 | int ret; |
136 | ||
33196ded | 137 | ret = i915_gem_wait_for_error(&dev_priv->gpu_error); |
76c1dec1 CW |
138 | if (ret) |
139 | return ret; | |
140 | ||
141 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
142 | if (ret) | |
143 | return ret; | |
144 | ||
76c1dec1 CW |
145 | return 0; |
146 | } | |
30dbf0c0 | 147 | |
5a125c3c EA |
148 | int |
149 | i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 150 | struct drm_file *file) |
5a125c3c | 151 | { |
72e96d64 | 152 | struct drm_i915_private *dev_priv = to_i915(dev); |
62106b4f | 153 | struct i915_ggtt *ggtt = &dev_priv->ggtt; |
72e96d64 | 154 | struct drm_i915_gem_get_aperture *args = data; |
ca1543be | 155 | struct i915_vma *vma; |
6299f992 | 156 | size_t pinned; |
5a125c3c | 157 | |
6299f992 | 158 | pinned = 0; |
73aa808f | 159 | mutex_lock(&dev->struct_mutex); |
1c7f4bca | 160 | list_for_each_entry(vma, &ggtt->base.active_list, vm_link) |
20dfbde4 | 161 | if (i915_vma_is_pinned(vma)) |
ca1543be | 162 | pinned += vma->node.size; |
1c7f4bca | 163 | list_for_each_entry(vma, &ggtt->base.inactive_list, vm_link) |
20dfbde4 | 164 | if (i915_vma_is_pinned(vma)) |
ca1543be | 165 | pinned += vma->node.size; |
73aa808f | 166 | mutex_unlock(&dev->struct_mutex); |
5a125c3c | 167 | |
72e96d64 | 168 | args->aper_size = ggtt->base.total; |
0206e353 | 169 | args->aper_available_size = args->aper_size - pinned; |
6299f992 | 170 | |
5a125c3c EA |
171 | return 0; |
172 | } | |
173 | ||
03ac84f1 | 174 | static struct sg_table * |
6a2c4232 | 175 | i915_gem_object_get_pages_phys(struct drm_i915_gem_object *obj) |
00731155 | 176 | { |
93c76a3d | 177 | struct address_space *mapping = obj->base.filp->f_mapping; |
dbb4351b | 178 | drm_dma_handle_t *phys; |
6a2c4232 CW |
179 | struct sg_table *st; |
180 | struct scatterlist *sg; | |
dbb4351b | 181 | char *vaddr; |
6a2c4232 | 182 | int i; |
00731155 | 183 | |
6a2c4232 | 184 | if (WARN_ON(i915_gem_object_needs_bit17_swizzle(obj))) |
03ac84f1 | 185 | return ERR_PTR(-EINVAL); |
6a2c4232 | 186 | |
dbb4351b CW |
187 | /* Always aligning to the object size, allows a single allocation |
188 | * to handle all possible callers, and given typical object sizes, | |
189 | * the alignment of the buddy allocation will naturally match. | |
190 | */ | |
191 | phys = drm_pci_alloc(obj->base.dev, | |
192 | obj->base.size, | |
193 | roundup_pow_of_two(obj->base.size)); | |
194 | if (!phys) | |
195 | return ERR_PTR(-ENOMEM); | |
196 | ||
197 | vaddr = phys->vaddr; | |
6a2c4232 CW |
198 | for (i = 0; i < obj->base.size / PAGE_SIZE; i++) { |
199 | struct page *page; | |
200 | char *src; | |
201 | ||
202 | page = shmem_read_mapping_page(mapping, i); | |
dbb4351b CW |
203 | if (IS_ERR(page)) { |
204 | st = ERR_CAST(page); | |
205 | goto err_phys; | |
206 | } | |
6a2c4232 CW |
207 | |
208 | src = kmap_atomic(page); | |
209 | memcpy(vaddr, src, PAGE_SIZE); | |
210 | drm_clflush_virt_range(vaddr, PAGE_SIZE); | |
211 | kunmap_atomic(src); | |
212 | ||
09cbfeaf | 213 | put_page(page); |
6a2c4232 CW |
214 | vaddr += PAGE_SIZE; |
215 | } | |
216 | ||
c033666a | 217 | i915_gem_chipset_flush(to_i915(obj->base.dev)); |
6a2c4232 CW |
218 | |
219 | st = kmalloc(sizeof(*st), GFP_KERNEL); | |
dbb4351b CW |
220 | if (!st) { |
221 | st = ERR_PTR(-ENOMEM); | |
222 | goto err_phys; | |
223 | } | |
6a2c4232 CW |
224 | |
225 | if (sg_alloc_table(st, 1, GFP_KERNEL)) { | |
226 | kfree(st); | |
dbb4351b CW |
227 | st = ERR_PTR(-ENOMEM); |
228 | goto err_phys; | |
6a2c4232 CW |
229 | } |
230 | ||
231 | sg = st->sgl; | |
232 | sg->offset = 0; | |
233 | sg->length = obj->base.size; | |
00731155 | 234 | |
dbb4351b | 235 | sg_dma_address(sg) = phys->busaddr; |
6a2c4232 CW |
236 | sg_dma_len(sg) = obj->base.size; |
237 | ||
dbb4351b CW |
238 | obj->phys_handle = phys; |
239 | return st; | |
240 | ||
241 | err_phys: | |
242 | drm_pci_free(obj->base.dev, phys); | |
03ac84f1 | 243 | return st; |
6a2c4232 CW |
244 | } |
245 | ||
246 | static void | |
2b3c8317 | 247 | __i915_gem_object_release_shmem(struct drm_i915_gem_object *obj, |
e5facdf9 CW |
248 | struct sg_table *pages, |
249 | bool needs_clflush) | |
6a2c4232 | 250 | { |
a4f5ea64 | 251 | GEM_BUG_ON(obj->mm.madv == __I915_MADV_PURGED); |
00731155 | 252 | |
a4f5ea64 CW |
253 | if (obj->mm.madv == I915_MADV_DONTNEED) |
254 | obj->mm.dirty = false; | |
6a2c4232 | 255 | |
e5facdf9 CW |
256 | if (needs_clflush && |
257 | (obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0 && | |
05c34837 | 258 | !cpu_cache_is_coherent(obj->base.dev, obj->cache_level)) |
2b3c8317 | 259 | drm_clflush_sg(pages); |
03ac84f1 CW |
260 | |
261 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; | |
262 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; | |
263 | } | |
264 | ||
265 | static void | |
266 | i915_gem_object_put_pages_phys(struct drm_i915_gem_object *obj, | |
267 | struct sg_table *pages) | |
268 | { | |
e5facdf9 | 269 | __i915_gem_object_release_shmem(obj, pages, false); |
03ac84f1 | 270 | |
a4f5ea64 | 271 | if (obj->mm.dirty) { |
93c76a3d | 272 | struct address_space *mapping = obj->base.filp->f_mapping; |
6a2c4232 | 273 | char *vaddr = obj->phys_handle->vaddr; |
00731155 CW |
274 | int i; |
275 | ||
276 | for (i = 0; i < obj->base.size / PAGE_SIZE; i++) { | |
6a2c4232 CW |
277 | struct page *page; |
278 | char *dst; | |
279 | ||
280 | page = shmem_read_mapping_page(mapping, i); | |
281 | if (IS_ERR(page)) | |
282 | continue; | |
283 | ||
284 | dst = kmap_atomic(page); | |
285 | drm_clflush_virt_range(vaddr, PAGE_SIZE); | |
286 | memcpy(dst, vaddr, PAGE_SIZE); | |
287 | kunmap_atomic(dst); | |
288 | ||
289 | set_page_dirty(page); | |
a4f5ea64 | 290 | if (obj->mm.madv == I915_MADV_WILLNEED) |
00731155 | 291 | mark_page_accessed(page); |
09cbfeaf | 292 | put_page(page); |
00731155 CW |
293 | vaddr += PAGE_SIZE; |
294 | } | |
a4f5ea64 | 295 | obj->mm.dirty = false; |
00731155 CW |
296 | } |
297 | ||
03ac84f1 CW |
298 | sg_free_table(pages); |
299 | kfree(pages); | |
dbb4351b CW |
300 | |
301 | drm_pci_free(obj->base.dev, obj->phys_handle); | |
6a2c4232 CW |
302 | } |
303 | ||
304 | static void | |
305 | i915_gem_object_release_phys(struct drm_i915_gem_object *obj) | |
306 | { | |
a4f5ea64 | 307 | i915_gem_object_unpin_pages(obj); |
6a2c4232 CW |
308 | } |
309 | ||
310 | static const struct drm_i915_gem_object_ops i915_gem_phys_ops = { | |
311 | .get_pages = i915_gem_object_get_pages_phys, | |
312 | .put_pages = i915_gem_object_put_pages_phys, | |
313 | .release = i915_gem_object_release_phys, | |
314 | }; | |
315 | ||
581ab1fe CW |
316 | static const struct drm_i915_gem_object_ops i915_gem_object_ops; |
317 | ||
35a9611c | 318 | int i915_gem_object_unbind(struct drm_i915_gem_object *obj) |
aa653a68 CW |
319 | { |
320 | struct i915_vma *vma; | |
321 | LIST_HEAD(still_in_list); | |
02bef8f9 CW |
322 | int ret; |
323 | ||
324 | lockdep_assert_held(&obj->base.dev->struct_mutex); | |
aa653a68 | 325 | |
02bef8f9 CW |
326 | /* Closed vma are removed from the obj->vma_list - but they may |
327 | * still have an active binding on the object. To remove those we | |
328 | * must wait for all rendering to complete to the object (as unbinding | |
329 | * must anyway), and retire the requests. | |
aa653a68 | 330 | */ |
e95433c7 CW |
331 | ret = i915_gem_object_wait(obj, |
332 | I915_WAIT_INTERRUPTIBLE | | |
333 | I915_WAIT_LOCKED | | |
334 | I915_WAIT_ALL, | |
335 | MAX_SCHEDULE_TIMEOUT, | |
336 | NULL); | |
02bef8f9 CW |
337 | if (ret) |
338 | return ret; | |
339 | ||
340 | i915_gem_retire_requests(to_i915(obj->base.dev)); | |
341 | ||
aa653a68 CW |
342 | while ((vma = list_first_entry_or_null(&obj->vma_list, |
343 | struct i915_vma, | |
344 | obj_link))) { | |
345 | list_move_tail(&vma->obj_link, &still_in_list); | |
346 | ret = i915_vma_unbind(vma); | |
347 | if (ret) | |
348 | break; | |
349 | } | |
350 | list_splice(&still_in_list, &obj->vma_list); | |
351 | ||
352 | return ret; | |
353 | } | |
354 | ||
e95433c7 CW |
355 | static long |
356 | i915_gem_object_wait_fence(struct dma_fence *fence, | |
357 | unsigned int flags, | |
358 | long timeout, | |
359 | struct intel_rps_client *rps) | |
00e60f26 | 360 | { |
e95433c7 | 361 | struct drm_i915_gem_request *rq; |
00e60f26 | 362 | |
e95433c7 | 363 | BUILD_BUG_ON(I915_WAIT_INTERRUPTIBLE != 0x1); |
00e60f26 | 364 | |
e95433c7 CW |
365 | if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &fence->flags)) |
366 | return timeout; | |
367 | ||
368 | if (!dma_fence_is_i915(fence)) | |
369 | return dma_fence_wait_timeout(fence, | |
370 | flags & I915_WAIT_INTERRUPTIBLE, | |
371 | timeout); | |
372 | ||
373 | rq = to_request(fence); | |
374 | if (i915_gem_request_completed(rq)) | |
375 | goto out; | |
376 | ||
377 | /* This client is about to stall waiting for the GPU. In many cases | |
378 | * this is undesirable and limits the throughput of the system, as | |
379 | * many clients cannot continue processing user input/output whilst | |
380 | * blocked. RPS autotuning may take tens of milliseconds to respond | |
381 | * to the GPU load and thus incurs additional latency for the client. | |
382 | * We can circumvent that by promoting the GPU frequency to maximum | |
383 | * before we wait. This makes the GPU throttle up much more quickly | |
384 | * (good for benchmarks and user experience, e.g. window animations), | |
385 | * but at a cost of spending more power processing the workload | |
386 | * (bad for battery). Not all clients even want their results | |
387 | * immediately and for them we should just let the GPU select its own | |
388 | * frequency to maximise efficiency. To prevent a single client from | |
389 | * forcing the clocks too high for the whole system, we only allow | |
390 | * each client to waitboost once in a busy period. | |
391 | */ | |
392 | if (rps) { | |
393 | if (INTEL_GEN(rq->i915) >= 6) | |
394 | gen6_rps_boost(rq->i915, rps, rq->emitted_jiffies); | |
395 | else | |
396 | rps = NULL; | |
00e60f26 CW |
397 | } |
398 | ||
e95433c7 CW |
399 | timeout = i915_wait_request(rq, flags, timeout); |
400 | ||
401 | out: | |
402 | if (flags & I915_WAIT_LOCKED && i915_gem_request_completed(rq)) | |
403 | i915_gem_request_retire_upto(rq); | |
404 | ||
cb399eab | 405 | if (rps && rq->global_seqno == intel_engine_last_submit(rq->engine)) { |
e95433c7 CW |
406 | /* The GPU is now idle and this client has stalled. |
407 | * Since no other client has submitted a request in the | |
408 | * meantime, assume that this client is the only one | |
409 | * supplying work to the GPU but is unable to keep that | |
410 | * work supplied because it is waiting. Since the GPU is | |
411 | * then never kept fully busy, RPS autoclocking will | |
412 | * keep the clocks relatively low, causing further delays. | |
413 | * Compensate by giving the synchronous client credit for | |
414 | * a waitboost next time. | |
415 | */ | |
416 | spin_lock(&rq->i915->rps.client_lock); | |
417 | list_del_init(&rps->link); | |
418 | spin_unlock(&rq->i915->rps.client_lock); | |
419 | } | |
420 | ||
421 | return timeout; | |
422 | } | |
423 | ||
424 | static long | |
425 | i915_gem_object_wait_reservation(struct reservation_object *resv, | |
426 | unsigned int flags, | |
427 | long timeout, | |
428 | struct intel_rps_client *rps) | |
429 | { | |
430 | struct dma_fence *excl; | |
431 | ||
432 | if (flags & I915_WAIT_ALL) { | |
433 | struct dma_fence **shared; | |
434 | unsigned int count, i; | |
00e60f26 CW |
435 | int ret; |
436 | ||
e95433c7 CW |
437 | ret = reservation_object_get_fences_rcu(resv, |
438 | &excl, &count, &shared); | |
00e60f26 CW |
439 | if (ret) |
440 | return ret; | |
00e60f26 | 441 | |
e95433c7 CW |
442 | for (i = 0; i < count; i++) { |
443 | timeout = i915_gem_object_wait_fence(shared[i], | |
444 | flags, timeout, | |
445 | rps); | |
d892e939 | 446 | if (timeout < 0) |
e95433c7 | 447 | break; |
00e60f26 | 448 | |
e95433c7 CW |
449 | dma_fence_put(shared[i]); |
450 | } | |
451 | ||
452 | for (; i < count; i++) | |
453 | dma_fence_put(shared[i]); | |
454 | kfree(shared); | |
455 | } else { | |
456 | excl = reservation_object_get_excl_rcu(resv); | |
00e60f26 CW |
457 | } |
458 | ||
d892e939 | 459 | if (excl && timeout >= 0) |
e95433c7 CW |
460 | timeout = i915_gem_object_wait_fence(excl, flags, timeout, rps); |
461 | ||
462 | dma_fence_put(excl); | |
463 | ||
464 | return timeout; | |
00e60f26 CW |
465 | } |
466 | ||
6b5e90f5 CW |
467 | static void __fence_set_priority(struct dma_fence *fence, int prio) |
468 | { | |
469 | struct drm_i915_gem_request *rq; | |
470 | struct intel_engine_cs *engine; | |
471 | ||
472 | if (!dma_fence_is_i915(fence)) | |
473 | return; | |
474 | ||
475 | rq = to_request(fence); | |
476 | engine = rq->engine; | |
477 | if (!engine->schedule) | |
478 | return; | |
479 | ||
480 | engine->schedule(rq, prio); | |
481 | } | |
482 | ||
483 | static void fence_set_priority(struct dma_fence *fence, int prio) | |
484 | { | |
485 | /* Recurse once into a fence-array */ | |
486 | if (dma_fence_is_array(fence)) { | |
487 | struct dma_fence_array *array = to_dma_fence_array(fence); | |
488 | int i; | |
489 | ||
490 | for (i = 0; i < array->num_fences; i++) | |
491 | __fence_set_priority(array->fences[i], prio); | |
492 | } else { | |
493 | __fence_set_priority(fence, prio); | |
494 | } | |
495 | } | |
496 | ||
497 | int | |
498 | i915_gem_object_wait_priority(struct drm_i915_gem_object *obj, | |
499 | unsigned int flags, | |
500 | int prio) | |
501 | { | |
502 | struct dma_fence *excl; | |
503 | ||
504 | if (flags & I915_WAIT_ALL) { | |
505 | struct dma_fence **shared; | |
506 | unsigned int count, i; | |
507 | int ret; | |
508 | ||
509 | ret = reservation_object_get_fences_rcu(obj->resv, | |
510 | &excl, &count, &shared); | |
511 | if (ret) | |
512 | return ret; | |
513 | ||
514 | for (i = 0; i < count; i++) { | |
515 | fence_set_priority(shared[i], prio); | |
516 | dma_fence_put(shared[i]); | |
517 | } | |
518 | ||
519 | kfree(shared); | |
520 | } else { | |
521 | excl = reservation_object_get_excl_rcu(obj->resv); | |
522 | } | |
523 | ||
524 | if (excl) { | |
525 | fence_set_priority(excl, prio); | |
526 | dma_fence_put(excl); | |
527 | } | |
528 | return 0; | |
529 | } | |
530 | ||
e95433c7 CW |
531 | /** |
532 | * Waits for rendering to the object to be completed | |
533 | * @obj: i915 gem object | |
534 | * @flags: how to wait (under a lock, for all rendering or just for writes etc) | |
535 | * @timeout: how long to wait | |
536 | * @rps: client (user process) to charge for any waitboosting | |
00e60f26 | 537 | */ |
e95433c7 CW |
538 | int |
539 | i915_gem_object_wait(struct drm_i915_gem_object *obj, | |
540 | unsigned int flags, | |
541 | long timeout, | |
542 | struct intel_rps_client *rps) | |
00e60f26 | 543 | { |
e95433c7 CW |
544 | might_sleep(); |
545 | #if IS_ENABLED(CONFIG_LOCKDEP) | |
546 | GEM_BUG_ON(debug_locks && | |
547 | !!lockdep_is_held(&obj->base.dev->struct_mutex) != | |
548 | !!(flags & I915_WAIT_LOCKED)); | |
549 | #endif | |
550 | GEM_BUG_ON(timeout < 0); | |
00e60f26 | 551 | |
d07f0e59 CW |
552 | timeout = i915_gem_object_wait_reservation(obj->resv, |
553 | flags, timeout, | |
554 | rps); | |
e95433c7 | 555 | return timeout < 0 ? timeout : 0; |
00e60f26 CW |
556 | } |
557 | ||
558 | static struct intel_rps_client *to_rps_client(struct drm_file *file) | |
559 | { | |
560 | struct drm_i915_file_private *fpriv = file->driver_priv; | |
561 | ||
562 | return &fpriv->rps; | |
563 | } | |
564 | ||
00731155 CW |
565 | int |
566 | i915_gem_object_attach_phys(struct drm_i915_gem_object *obj, | |
567 | int align) | |
568 | { | |
6a2c4232 | 569 | int ret; |
00731155 | 570 | |
dbb4351b CW |
571 | if (align > obj->base.size) |
572 | return -EINVAL; | |
00731155 | 573 | |
dbb4351b | 574 | if (obj->ops == &i915_gem_phys_ops) |
00731155 | 575 | return 0; |
00731155 | 576 | |
a4f5ea64 | 577 | if (obj->mm.madv != I915_MADV_WILLNEED) |
00731155 CW |
578 | return -EFAULT; |
579 | ||
580 | if (obj->base.filp == NULL) | |
581 | return -EINVAL; | |
582 | ||
4717ca9e CW |
583 | ret = i915_gem_object_unbind(obj); |
584 | if (ret) | |
585 | return ret; | |
586 | ||
548625ee | 587 | __i915_gem_object_put_pages(obj, I915_MM_NORMAL); |
03ac84f1 CW |
588 | if (obj->mm.pages) |
589 | return -EBUSY; | |
6a2c4232 | 590 | |
581ab1fe | 591 | GEM_BUG_ON(obj->ops != &i915_gem_object_ops); |
6a2c4232 CW |
592 | obj->ops = &i915_gem_phys_ops; |
593 | ||
581ab1fe CW |
594 | ret = i915_gem_object_pin_pages(obj); |
595 | if (ret) | |
596 | goto err_xfer; | |
597 | ||
598 | return 0; | |
599 | ||
600 | err_xfer: | |
601 | obj->ops = &i915_gem_object_ops; | |
602 | return ret; | |
00731155 CW |
603 | } |
604 | ||
605 | static int | |
606 | i915_gem_phys_pwrite(struct drm_i915_gem_object *obj, | |
607 | struct drm_i915_gem_pwrite *args, | |
03ac84f1 | 608 | struct drm_file *file) |
00731155 | 609 | { |
00731155 | 610 | void *vaddr = obj->phys_handle->vaddr + args->offset; |
3ed605bc | 611 | char __user *user_data = u64_to_user_ptr(args->data_ptr); |
6a2c4232 CW |
612 | |
613 | /* We manually control the domain here and pretend that it | |
614 | * remains coherent i.e. in the GTT domain, like shmem_pwrite. | |
615 | */ | |
77a0d1ca | 616 | intel_fb_obj_invalidate(obj, ORIGIN_CPU); |
10466d2a CW |
617 | if (copy_from_user(vaddr, user_data, args->size)) |
618 | return -EFAULT; | |
00731155 | 619 | |
6a2c4232 | 620 | drm_clflush_virt_range(vaddr, args->size); |
10466d2a | 621 | i915_gem_chipset_flush(to_i915(obj->base.dev)); |
063e4e6b | 622 | |
de152b62 | 623 | intel_fb_obj_flush(obj, false, ORIGIN_CPU); |
10466d2a | 624 | return 0; |
00731155 CW |
625 | } |
626 | ||
187685cb | 627 | void *i915_gem_object_alloc(struct drm_i915_private *dev_priv) |
42dcedd4 | 628 | { |
efab6d8d | 629 | return kmem_cache_zalloc(dev_priv->objects, GFP_KERNEL); |
42dcedd4 CW |
630 | } |
631 | ||
632 | void i915_gem_object_free(struct drm_i915_gem_object *obj) | |
633 | { | |
fac5e23e | 634 | struct drm_i915_private *dev_priv = to_i915(obj->base.dev); |
efab6d8d | 635 | kmem_cache_free(dev_priv->objects, obj); |
42dcedd4 CW |
636 | } |
637 | ||
ff72145b DA |
638 | static int |
639 | i915_gem_create(struct drm_file *file, | |
12d79d78 | 640 | struct drm_i915_private *dev_priv, |
ff72145b DA |
641 | uint64_t size, |
642 | uint32_t *handle_p) | |
673a394b | 643 | { |
05394f39 | 644 | struct drm_i915_gem_object *obj; |
a1a2d1d3 PP |
645 | int ret; |
646 | u32 handle; | |
673a394b | 647 | |
ff72145b | 648 | size = roundup(size, PAGE_SIZE); |
8ffc0246 CW |
649 | if (size == 0) |
650 | return -EINVAL; | |
673a394b EA |
651 | |
652 | /* Allocate the new object */ | |
12d79d78 | 653 | obj = i915_gem_object_create(dev_priv, size); |
fe3db79b CW |
654 | if (IS_ERR(obj)) |
655 | return PTR_ERR(obj); | |
673a394b | 656 | |
05394f39 | 657 | ret = drm_gem_handle_create(file, &obj->base, &handle); |
202f2fef | 658 | /* drop reference from allocate - handle holds it now */ |
f0cd5182 | 659 | i915_gem_object_put(obj); |
d861e338 DV |
660 | if (ret) |
661 | return ret; | |
202f2fef | 662 | |
ff72145b | 663 | *handle_p = handle; |
673a394b EA |
664 | return 0; |
665 | } | |
666 | ||
ff72145b DA |
667 | int |
668 | i915_gem_dumb_create(struct drm_file *file, | |
669 | struct drm_device *dev, | |
670 | struct drm_mode_create_dumb *args) | |
671 | { | |
672 | /* have to work out size/pitch and return them */ | |
de45eaf7 | 673 | args->pitch = ALIGN(args->width * DIV_ROUND_UP(args->bpp, 8), 64); |
ff72145b | 674 | args->size = args->pitch * args->height; |
12d79d78 | 675 | return i915_gem_create(file, to_i915(dev), |
da6b51d0 | 676 | args->size, &args->handle); |
ff72145b DA |
677 | } |
678 | ||
ff72145b DA |
679 | /** |
680 | * Creates a new mm object and returns a handle to it. | |
14bb2c11 TU |
681 | * @dev: drm device pointer |
682 | * @data: ioctl data blob | |
683 | * @file: drm file pointer | |
ff72145b DA |
684 | */ |
685 | int | |
686 | i915_gem_create_ioctl(struct drm_device *dev, void *data, | |
687 | struct drm_file *file) | |
688 | { | |
12d79d78 | 689 | struct drm_i915_private *dev_priv = to_i915(dev); |
ff72145b | 690 | struct drm_i915_gem_create *args = data; |
63ed2cb2 | 691 | |
12d79d78 | 692 | i915_gem_flush_free_objects(dev_priv); |
fbbd37b3 | 693 | |
12d79d78 | 694 | return i915_gem_create(file, dev_priv, |
da6b51d0 | 695 | args->size, &args->handle); |
ff72145b DA |
696 | } |
697 | ||
8461d226 DV |
698 | static inline int |
699 | __copy_to_user_swizzled(char __user *cpu_vaddr, | |
700 | const char *gpu_vaddr, int gpu_offset, | |
701 | int length) | |
702 | { | |
703 | int ret, cpu_offset = 0; | |
704 | ||
705 | while (length > 0) { | |
706 | int cacheline_end = ALIGN(gpu_offset + 1, 64); | |
707 | int this_length = min(cacheline_end - gpu_offset, length); | |
708 | int swizzled_gpu_offset = gpu_offset ^ 64; | |
709 | ||
710 | ret = __copy_to_user(cpu_vaddr + cpu_offset, | |
711 | gpu_vaddr + swizzled_gpu_offset, | |
712 | this_length); | |
713 | if (ret) | |
714 | return ret + length; | |
715 | ||
716 | cpu_offset += this_length; | |
717 | gpu_offset += this_length; | |
718 | length -= this_length; | |
719 | } | |
720 | ||
721 | return 0; | |
722 | } | |
723 | ||
8c59967c | 724 | static inline int |
4f0c7cfb BW |
725 | __copy_from_user_swizzled(char *gpu_vaddr, int gpu_offset, |
726 | const char __user *cpu_vaddr, | |
8c59967c DV |
727 | int length) |
728 | { | |
729 | int ret, cpu_offset = 0; | |
730 | ||
731 | while (length > 0) { | |
732 | int cacheline_end = ALIGN(gpu_offset + 1, 64); | |
733 | int this_length = min(cacheline_end - gpu_offset, length); | |
734 | int swizzled_gpu_offset = gpu_offset ^ 64; | |
735 | ||
736 | ret = __copy_from_user(gpu_vaddr + swizzled_gpu_offset, | |
737 | cpu_vaddr + cpu_offset, | |
738 | this_length); | |
739 | if (ret) | |
740 | return ret + length; | |
741 | ||
742 | cpu_offset += this_length; | |
743 | gpu_offset += this_length; | |
744 | length -= this_length; | |
745 | } | |
746 | ||
747 | return 0; | |
748 | } | |
749 | ||
4c914c0c BV |
750 | /* |
751 | * Pins the specified object's pages and synchronizes the object with | |
752 | * GPU accesses. Sets needs_clflush to non-zero if the caller should | |
753 | * flush the object from the CPU cache. | |
754 | */ | |
755 | int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj, | |
43394c7d | 756 | unsigned int *needs_clflush) |
4c914c0c BV |
757 | { |
758 | int ret; | |
759 | ||
e95433c7 | 760 | lockdep_assert_held(&obj->base.dev->struct_mutex); |
4c914c0c | 761 | |
e95433c7 | 762 | *needs_clflush = 0; |
43394c7d CW |
763 | if (!i915_gem_object_has_struct_page(obj)) |
764 | return -ENODEV; | |
4c914c0c | 765 | |
e95433c7 CW |
766 | ret = i915_gem_object_wait(obj, |
767 | I915_WAIT_INTERRUPTIBLE | | |
768 | I915_WAIT_LOCKED, | |
769 | MAX_SCHEDULE_TIMEOUT, | |
770 | NULL); | |
c13d87ea CW |
771 | if (ret) |
772 | return ret; | |
773 | ||
a4f5ea64 | 774 | ret = i915_gem_object_pin_pages(obj); |
9764951e CW |
775 | if (ret) |
776 | return ret; | |
777 | ||
a314d5cb CW |
778 | i915_gem_object_flush_gtt_write_domain(obj); |
779 | ||
43394c7d CW |
780 | /* If we're not in the cpu read domain, set ourself into the gtt |
781 | * read domain and manually flush cachelines (if required). This | |
782 | * optimizes for the case when the gpu will dirty the data | |
783 | * anyway again before the next pread happens. | |
784 | */ | |
785 | if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU)) | |
4c914c0c BV |
786 | *needs_clflush = !cpu_cache_is_coherent(obj->base.dev, |
787 | obj->cache_level); | |
43394c7d | 788 | |
43394c7d CW |
789 | if (*needs_clflush && !static_cpu_has(X86_FEATURE_CLFLUSH)) { |
790 | ret = i915_gem_object_set_to_cpu_domain(obj, false); | |
9764951e CW |
791 | if (ret) |
792 | goto err_unpin; | |
793 | ||
43394c7d | 794 | *needs_clflush = 0; |
4c914c0c BV |
795 | } |
796 | ||
9764951e | 797 | /* return with the pages pinned */ |
43394c7d | 798 | return 0; |
9764951e CW |
799 | |
800 | err_unpin: | |
801 | i915_gem_object_unpin_pages(obj); | |
802 | return ret; | |
43394c7d CW |
803 | } |
804 | ||
805 | int i915_gem_obj_prepare_shmem_write(struct drm_i915_gem_object *obj, | |
806 | unsigned int *needs_clflush) | |
807 | { | |
808 | int ret; | |
809 | ||
e95433c7 CW |
810 | lockdep_assert_held(&obj->base.dev->struct_mutex); |
811 | ||
43394c7d CW |
812 | *needs_clflush = 0; |
813 | if (!i915_gem_object_has_struct_page(obj)) | |
814 | return -ENODEV; | |
815 | ||
e95433c7 CW |
816 | ret = i915_gem_object_wait(obj, |
817 | I915_WAIT_INTERRUPTIBLE | | |
818 | I915_WAIT_LOCKED | | |
819 | I915_WAIT_ALL, | |
820 | MAX_SCHEDULE_TIMEOUT, | |
821 | NULL); | |
43394c7d CW |
822 | if (ret) |
823 | return ret; | |
824 | ||
a4f5ea64 | 825 | ret = i915_gem_object_pin_pages(obj); |
9764951e CW |
826 | if (ret) |
827 | return ret; | |
828 | ||
a314d5cb CW |
829 | i915_gem_object_flush_gtt_write_domain(obj); |
830 | ||
43394c7d CW |
831 | /* If we're not in the cpu write domain, set ourself into the |
832 | * gtt write domain and manually flush cachelines (as required). | |
833 | * This optimizes for the case when the gpu will use the data | |
834 | * right away and we therefore have to clflush anyway. | |
835 | */ | |
836 | if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) | |
837 | *needs_clflush |= cpu_write_needs_clflush(obj) << 1; | |
838 | ||
839 | /* Same trick applies to invalidate partially written cachelines read | |
840 | * before writing. | |
841 | */ | |
842 | if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU)) | |
843 | *needs_clflush |= !cpu_cache_is_coherent(obj->base.dev, | |
844 | obj->cache_level); | |
845 | ||
43394c7d CW |
846 | if (*needs_clflush && !static_cpu_has(X86_FEATURE_CLFLUSH)) { |
847 | ret = i915_gem_object_set_to_cpu_domain(obj, true); | |
9764951e CW |
848 | if (ret) |
849 | goto err_unpin; | |
850 | ||
43394c7d CW |
851 | *needs_clflush = 0; |
852 | } | |
853 | ||
854 | if ((*needs_clflush & CLFLUSH_AFTER) == 0) | |
855 | obj->cache_dirty = true; | |
856 | ||
857 | intel_fb_obj_invalidate(obj, ORIGIN_CPU); | |
a4f5ea64 | 858 | obj->mm.dirty = true; |
9764951e | 859 | /* return with the pages pinned */ |
43394c7d | 860 | return 0; |
9764951e CW |
861 | |
862 | err_unpin: | |
863 | i915_gem_object_unpin_pages(obj); | |
864 | return ret; | |
4c914c0c BV |
865 | } |
866 | ||
23c18c71 DV |
867 | static void |
868 | shmem_clflush_swizzled_range(char *addr, unsigned long length, | |
869 | bool swizzled) | |
870 | { | |
e7e58eb5 | 871 | if (unlikely(swizzled)) { |
23c18c71 DV |
872 | unsigned long start = (unsigned long) addr; |
873 | unsigned long end = (unsigned long) addr + length; | |
874 | ||
875 | /* For swizzling simply ensure that we always flush both | |
876 | * channels. Lame, but simple and it works. Swizzled | |
877 | * pwrite/pread is far from a hotpath - current userspace | |
878 | * doesn't use it at all. */ | |
879 | start = round_down(start, 128); | |
880 | end = round_up(end, 128); | |
881 | ||
882 | drm_clflush_virt_range((void *)start, end - start); | |
883 | } else { | |
884 | drm_clflush_virt_range(addr, length); | |
885 | } | |
886 | ||
887 | } | |
888 | ||
d174bd64 DV |
889 | /* Only difference to the fast-path function is that this can handle bit17 |
890 | * and uses non-atomic copy and kmap functions. */ | |
891 | static int | |
bb6dc8d9 | 892 | shmem_pread_slow(struct page *page, int offset, int length, |
d174bd64 DV |
893 | char __user *user_data, |
894 | bool page_do_bit17_swizzling, bool needs_clflush) | |
895 | { | |
896 | char *vaddr; | |
897 | int ret; | |
898 | ||
899 | vaddr = kmap(page); | |
900 | if (needs_clflush) | |
bb6dc8d9 | 901 | shmem_clflush_swizzled_range(vaddr + offset, length, |
23c18c71 | 902 | page_do_bit17_swizzling); |
d174bd64 DV |
903 | |
904 | if (page_do_bit17_swizzling) | |
bb6dc8d9 | 905 | ret = __copy_to_user_swizzled(user_data, vaddr, offset, length); |
d174bd64 | 906 | else |
bb6dc8d9 | 907 | ret = __copy_to_user(user_data, vaddr + offset, length); |
d174bd64 DV |
908 | kunmap(page); |
909 | ||
f60d7f0c | 910 | return ret ? - EFAULT : 0; |
d174bd64 DV |
911 | } |
912 | ||
bb6dc8d9 CW |
913 | static int |
914 | shmem_pread(struct page *page, int offset, int length, char __user *user_data, | |
915 | bool page_do_bit17_swizzling, bool needs_clflush) | |
916 | { | |
917 | int ret; | |
918 | ||
919 | ret = -ENODEV; | |
920 | if (!page_do_bit17_swizzling) { | |
921 | char *vaddr = kmap_atomic(page); | |
922 | ||
923 | if (needs_clflush) | |
924 | drm_clflush_virt_range(vaddr + offset, length); | |
925 | ret = __copy_to_user_inatomic(user_data, vaddr + offset, length); | |
926 | kunmap_atomic(vaddr); | |
927 | } | |
928 | if (ret == 0) | |
929 | return 0; | |
930 | ||
931 | return shmem_pread_slow(page, offset, length, user_data, | |
932 | page_do_bit17_swizzling, needs_clflush); | |
933 | } | |
934 | ||
935 | static int | |
936 | i915_gem_shmem_pread(struct drm_i915_gem_object *obj, | |
937 | struct drm_i915_gem_pread *args) | |
938 | { | |
939 | char __user *user_data; | |
940 | u64 remain; | |
941 | unsigned int obj_do_bit17_swizzling; | |
942 | unsigned int needs_clflush; | |
943 | unsigned int idx, offset; | |
944 | int ret; | |
945 | ||
946 | obj_do_bit17_swizzling = 0; | |
947 | if (i915_gem_object_needs_bit17_swizzle(obj)) | |
948 | obj_do_bit17_swizzling = BIT(17); | |
949 | ||
950 | ret = mutex_lock_interruptible(&obj->base.dev->struct_mutex); | |
951 | if (ret) | |
952 | return ret; | |
953 | ||
954 | ret = i915_gem_obj_prepare_shmem_read(obj, &needs_clflush); | |
955 | mutex_unlock(&obj->base.dev->struct_mutex); | |
956 | if (ret) | |
957 | return ret; | |
958 | ||
959 | remain = args->size; | |
960 | user_data = u64_to_user_ptr(args->data_ptr); | |
961 | offset = offset_in_page(args->offset); | |
962 | for (idx = args->offset >> PAGE_SHIFT; remain; idx++) { | |
963 | struct page *page = i915_gem_object_get_page(obj, idx); | |
964 | int length; | |
965 | ||
966 | length = remain; | |
967 | if (offset + length > PAGE_SIZE) | |
968 | length = PAGE_SIZE - offset; | |
969 | ||
970 | ret = shmem_pread(page, offset, length, user_data, | |
971 | page_to_phys(page) & obj_do_bit17_swizzling, | |
972 | needs_clflush); | |
973 | if (ret) | |
974 | break; | |
975 | ||
976 | remain -= length; | |
977 | user_data += length; | |
978 | offset = 0; | |
979 | } | |
980 | ||
981 | i915_gem_obj_finish_shmem_access(obj); | |
982 | return ret; | |
983 | } | |
984 | ||
985 | static inline bool | |
986 | gtt_user_read(struct io_mapping *mapping, | |
987 | loff_t base, int offset, | |
988 | char __user *user_data, int length) | |
b50a5371 | 989 | { |
b50a5371 | 990 | void *vaddr; |
bb6dc8d9 | 991 | unsigned long unwritten; |
b50a5371 | 992 | |
b50a5371 | 993 | /* We can use the cpu mem copy function because this is X86. */ |
bb6dc8d9 CW |
994 | vaddr = (void __force *)io_mapping_map_atomic_wc(mapping, base); |
995 | unwritten = __copy_to_user_inatomic(user_data, vaddr + offset, length); | |
996 | io_mapping_unmap_atomic(vaddr); | |
997 | if (unwritten) { | |
998 | vaddr = (void __force *) | |
999 | io_mapping_map_wc(mapping, base, PAGE_SIZE); | |
1000 | unwritten = copy_to_user(user_data, vaddr + offset, length); | |
1001 | io_mapping_unmap(vaddr); | |
1002 | } | |
b50a5371 AS |
1003 | return unwritten; |
1004 | } | |
1005 | ||
1006 | static int | |
bb6dc8d9 CW |
1007 | i915_gem_gtt_pread(struct drm_i915_gem_object *obj, |
1008 | const struct drm_i915_gem_pread *args) | |
b50a5371 | 1009 | { |
bb6dc8d9 CW |
1010 | struct drm_i915_private *i915 = to_i915(obj->base.dev); |
1011 | struct i915_ggtt *ggtt = &i915->ggtt; | |
b50a5371 | 1012 | struct drm_mm_node node; |
bb6dc8d9 CW |
1013 | struct i915_vma *vma; |
1014 | void __user *user_data; | |
1015 | u64 remain, offset; | |
b50a5371 AS |
1016 | int ret; |
1017 | ||
bb6dc8d9 CW |
1018 | ret = mutex_lock_interruptible(&i915->drm.struct_mutex); |
1019 | if (ret) | |
1020 | return ret; | |
1021 | ||
1022 | intel_runtime_pm_get(i915); | |
1023 | vma = i915_gem_object_ggtt_pin(obj, NULL, 0, 0, | |
1024 | PIN_MAPPABLE | PIN_NONBLOCK); | |
18034584 CW |
1025 | if (!IS_ERR(vma)) { |
1026 | node.start = i915_ggtt_offset(vma); | |
1027 | node.allocated = false; | |
49ef5294 | 1028 | ret = i915_vma_put_fence(vma); |
18034584 CW |
1029 | if (ret) { |
1030 | i915_vma_unpin(vma); | |
1031 | vma = ERR_PTR(ret); | |
1032 | } | |
1033 | } | |
058d88c4 | 1034 | if (IS_ERR(vma)) { |
bb6dc8d9 | 1035 | ret = insert_mappable_node(ggtt, &node, PAGE_SIZE); |
b50a5371 | 1036 | if (ret) |
bb6dc8d9 CW |
1037 | goto out_unlock; |
1038 | GEM_BUG_ON(!node.allocated); | |
b50a5371 AS |
1039 | } |
1040 | ||
1041 | ret = i915_gem_object_set_to_gtt_domain(obj, false); | |
1042 | if (ret) | |
1043 | goto out_unpin; | |
1044 | ||
bb6dc8d9 | 1045 | mutex_unlock(&i915->drm.struct_mutex); |
b50a5371 | 1046 | |
bb6dc8d9 CW |
1047 | user_data = u64_to_user_ptr(args->data_ptr); |
1048 | remain = args->size; | |
1049 | offset = args->offset; | |
b50a5371 AS |
1050 | |
1051 | while (remain > 0) { | |
1052 | /* Operation in this page | |
1053 | * | |
1054 | * page_base = page offset within aperture | |
1055 | * page_offset = offset within page | |
1056 | * page_length = bytes to copy for this page | |
1057 | */ | |
1058 | u32 page_base = node.start; | |
1059 | unsigned page_offset = offset_in_page(offset); | |
1060 | unsigned page_length = PAGE_SIZE - page_offset; | |
1061 | page_length = remain < page_length ? remain : page_length; | |
1062 | if (node.allocated) { | |
1063 | wmb(); | |
1064 | ggtt->base.insert_page(&ggtt->base, | |
1065 | i915_gem_object_get_dma_address(obj, offset >> PAGE_SHIFT), | |
bb6dc8d9 | 1066 | node.start, I915_CACHE_NONE, 0); |
b50a5371 AS |
1067 | wmb(); |
1068 | } else { | |
1069 | page_base += offset & PAGE_MASK; | |
1070 | } | |
bb6dc8d9 CW |
1071 | |
1072 | if (gtt_user_read(&ggtt->mappable, page_base, page_offset, | |
1073 | user_data, page_length)) { | |
b50a5371 AS |
1074 | ret = -EFAULT; |
1075 | break; | |
1076 | } | |
1077 | ||
1078 | remain -= page_length; | |
1079 | user_data += page_length; | |
1080 | offset += page_length; | |
1081 | } | |
1082 | ||
bb6dc8d9 | 1083 | mutex_lock(&i915->drm.struct_mutex); |
b50a5371 AS |
1084 | out_unpin: |
1085 | if (node.allocated) { | |
1086 | wmb(); | |
1087 | ggtt->base.clear_range(&ggtt->base, | |
4fb84d99 | 1088 | node.start, node.size); |
b50a5371 AS |
1089 | remove_mappable_node(&node); |
1090 | } else { | |
058d88c4 | 1091 | i915_vma_unpin(vma); |
b50a5371 | 1092 | } |
bb6dc8d9 CW |
1093 | out_unlock: |
1094 | intel_runtime_pm_put(i915); | |
1095 | mutex_unlock(&i915->drm.struct_mutex); | |
f60d7f0c | 1096 | |
eb01459f EA |
1097 | return ret; |
1098 | } | |
1099 | ||
673a394b EA |
1100 | /** |
1101 | * Reads data from the object referenced by handle. | |
14bb2c11 TU |
1102 | * @dev: drm device pointer |
1103 | * @data: ioctl data blob | |
1104 | * @file: drm file pointer | |
673a394b EA |
1105 | * |
1106 | * On error, the contents of *data are undefined. | |
1107 | */ | |
1108 | int | |
1109 | i915_gem_pread_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 1110 | struct drm_file *file) |
673a394b EA |
1111 | { |
1112 | struct drm_i915_gem_pread *args = data; | |
05394f39 | 1113 | struct drm_i915_gem_object *obj; |
bb6dc8d9 | 1114 | int ret; |
673a394b | 1115 | |
51311d0a CW |
1116 | if (args->size == 0) |
1117 | return 0; | |
1118 | ||
1119 | if (!access_ok(VERIFY_WRITE, | |
3ed605bc | 1120 | u64_to_user_ptr(args->data_ptr), |
51311d0a CW |
1121 | args->size)) |
1122 | return -EFAULT; | |
1123 | ||
03ac0642 | 1124 | obj = i915_gem_object_lookup(file, args->handle); |
258a5ede CW |
1125 | if (!obj) |
1126 | return -ENOENT; | |
673a394b | 1127 | |
7dcd2499 | 1128 | /* Bounds check source. */ |
966d5bf5 | 1129 | if (range_overflows_t(u64, args->offset, args->size, obj->base.size)) { |
ce9d419d | 1130 | ret = -EINVAL; |
bb6dc8d9 | 1131 | goto out; |
ce9d419d CW |
1132 | } |
1133 | ||
db53a302 CW |
1134 | trace_i915_gem_object_pread(obj, args->offset, args->size); |
1135 | ||
e95433c7 CW |
1136 | ret = i915_gem_object_wait(obj, |
1137 | I915_WAIT_INTERRUPTIBLE, | |
1138 | MAX_SCHEDULE_TIMEOUT, | |
1139 | to_rps_client(file)); | |
258a5ede | 1140 | if (ret) |
bb6dc8d9 | 1141 | goto out; |
258a5ede | 1142 | |
bb6dc8d9 | 1143 | ret = i915_gem_object_pin_pages(obj); |
258a5ede | 1144 | if (ret) |
bb6dc8d9 | 1145 | goto out; |
673a394b | 1146 | |
bb6dc8d9 | 1147 | ret = i915_gem_shmem_pread(obj, args); |
9c870d03 | 1148 | if (ret == -EFAULT || ret == -ENODEV) |
bb6dc8d9 | 1149 | ret = i915_gem_gtt_pread(obj, args); |
b50a5371 | 1150 | |
bb6dc8d9 CW |
1151 | i915_gem_object_unpin_pages(obj); |
1152 | out: | |
f0cd5182 | 1153 | i915_gem_object_put(obj); |
eb01459f | 1154 | return ret; |
673a394b EA |
1155 | } |
1156 | ||
0839ccb8 KP |
1157 | /* This is the fast write path which cannot handle |
1158 | * page faults in the source data | |
9b7530cc | 1159 | */ |
0839ccb8 | 1160 | |
fe115628 CW |
1161 | static inline bool |
1162 | ggtt_write(struct io_mapping *mapping, | |
1163 | loff_t base, int offset, | |
1164 | char __user *user_data, int length) | |
9b7530cc | 1165 | { |
4f0c7cfb | 1166 | void *vaddr; |
0839ccb8 | 1167 | unsigned long unwritten; |
9b7530cc | 1168 | |
4f0c7cfb | 1169 | /* We can use the cpu mem copy function because this is X86. */ |
fe115628 CW |
1170 | vaddr = (void __force *)io_mapping_map_atomic_wc(mapping, base); |
1171 | unwritten = __copy_from_user_inatomic_nocache(vaddr + offset, | |
0839ccb8 | 1172 | user_data, length); |
fe115628 CW |
1173 | io_mapping_unmap_atomic(vaddr); |
1174 | if (unwritten) { | |
1175 | vaddr = (void __force *) | |
1176 | io_mapping_map_wc(mapping, base, PAGE_SIZE); | |
1177 | unwritten = copy_from_user(vaddr + offset, user_data, length); | |
1178 | io_mapping_unmap(vaddr); | |
1179 | } | |
bb6dc8d9 | 1180 | |
bb6dc8d9 CW |
1181 | return unwritten; |
1182 | } | |
1183 | ||
3de09aa3 EA |
1184 | /** |
1185 | * This is the fast pwrite path, where we copy the data directly from the | |
1186 | * user into the GTT, uncached. | |
fe115628 | 1187 | * @obj: i915 GEM object |
14bb2c11 | 1188 | * @args: pwrite arguments structure |
3de09aa3 | 1189 | */ |
673a394b | 1190 | static int |
fe115628 CW |
1191 | i915_gem_gtt_pwrite_fast(struct drm_i915_gem_object *obj, |
1192 | const struct drm_i915_gem_pwrite *args) | |
673a394b | 1193 | { |
fe115628 | 1194 | struct drm_i915_private *i915 = to_i915(obj->base.dev); |
4f1959ee AS |
1195 | struct i915_ggtt *ggtt = &i915->ggtt; |
1196 | struct drm_mm_node node; | |
fe115628 CW |
1197 | struct i915_vma *vma; |
1198 | u64 remain, offset; | |
1199 | void __user *user_data; | |
4f1959ee | 1200 | int ret; |
b50a5371 | 1201 | |
fe115628 CW |
1202 | ret = mutex_lock_interruptible(&i915->drm.struct_mutex); |
1203 | if (ret) | |
1204 | return ret; | |
935aaa69 | 1205 | |
9c870d03 | 1206 | intel_runtime_pm_get(i915); |
058d88c4 | 1207 | vma = i915_gem_object_ggtt_pin(obj, NULL, 0, 0, |
de895082 | 1208 | PIN_MAPPABLE | PIN_NONBLOCK); |
18034584 CW |
1209 | if (!IS_ERR(vma)) { |
1210 | node.start = i915_ggtt_offset(vma); | |
1211 | node.allocated = false; | |
49ef5294 | 1212 | ret = i915_vma_put_fence(vma); |
18034584 CW |
1213 | if (ret) { |
1214 | i915_vma_unpin(vma); | |
1215 | vma = ERR_PTR(ret); | |
1216 | } | |
1217 | } | |
058d88c4 | 1218 | if (IS_ERR(vma)) { |
bb6dc8d9 | 1219 | ret = insert_mappable_node(ggtt, &node, PAGE_SIZE); |
4f1959ee | 1220 | if (ret) |
fe115628 CW |
1221 | goto out_unlock; |
1222 | GEM_BUG_ON(!node.allocated); | |
4f1959ee | 1223 | } |
935aaa69 DV |
1224 | |
1225 | ret = i915_gem_object_set_to_gtt_domain(obj, true); | |
1226 | if (ret) | |
1227 | goto out_unpin; | |
1228 | ||
fe115628 CW |
1229 | mutex_unlock(&i915->drm.struct_mutex); |
1230 | ||
b19482d7 | 1231 | intel_fb_obj_invalidate(obj, ORIGIN_CPU); |
063e4e6b | 1232 | |
4f1959ee AS |
1233 | user_data = u64_to_user_ptr(args->data_ptr); |
1234 | offset = args->offset; | |
1235 | remain = args->size; | |
1236 | while (remain) { | |
673a394b EA |
1237 | /* Operation in this page |
1238 | * | |
0839ccb8 KP |
1239 | * page_base = page offset within aperture |
1240 | * page_offset = offset within page | |
1241 | * page_length = bytes to copy for this page | |
673a394b | 1242 | */ |
4f1959ee | 1243 | u32 page_base = node.start; |
bb6dc8d9 CW |
1244 | unsigned int page_offset = offset_in_page(offset); |
1245 | unsigned int page_length = PAGE_SIZE - page_offset; | |
4f1959ee AS |
1246 | page_length = remain < page_length ? remain : page_length; |
1247 | if (node.allocated) { | |
1248 | wmb(); /* flush the write before we modify the GGTT */ | |
1249 | ggtt->base.insert_page(&ggtt->base, | |
1250 | i915_gem_object_get_dma_address(obj, offset >> PAGE_SHIFT), | |
1251 | node.start, I915_CACHE_NONE, 0); | |
1252 | wmb(); /* flush modifications to the GGTT (insert_page) */ | |
1253 | } else { | |
1254 | page_base += offset & PAGE_MASK; | |
1255 | } | |
0839ccb8 | 1256 | /* If we get a fault while copying data, then (presumably) our |
3de09aa3 EA |
1257 | * source page isn't available. Return the error and we'll |
1258 | * retry in the slow path. | |
b50a5371 AS |
1259 | * If the object is non-shmem backed, we retry again with the |
1260 | * path that handles page fault. | |
0839ccb8 | 1261 | */ |
fe115628 CW |
1262 | if (ggtt_write(&ggtt->mappable, page_base, page_offset, |
1263 | user_data, page_length)) { | |
1264 | ret = -EFAULT; | |
1265 | break; | |
935aaa69 | 1266 | } |
673a394b | 1267 | |
0839ccb8 KP |
1268 | remain -= page_length; |
1269 | user_data += page_length; | |
1270 | offset += page_length; | |
673a394b | 1271 | } |
b19482d7 | 1272 | intel_fb_obj_flush(obj, false, ORIGIN_CPU); |
fe115628 CW |
1273 | |
1274 | mutex_lock(&i915->drm.struct_mutex); | |
935aaa69 | 1275 | out_unpin: |
4f1959ee AS |
1276 | if (node.allocated) { |
1277 | wmb(); | |
1278 | ggtt->base.clear_range(&ggtt->base, | |
4fb84d99 | 1279 | node.start, node.size); |
4f1959ee AS |
1280 | remove_mappable_node(&node); |
1281 | } else { | |
058d88c4 | 1282 | i915_vma_unpin(vma); |
4f1959ee | 1283 | } |
fe115628 | 1284 | out_unlock: |
9c870d03 | 1285 | intel_runtime_pm_put(i915); |
fe115628 | 1286 | mutex_unlock(&i915->drm.struct_mutex); |
3de09aa3 | 1287 | return ret; |
673a394b EA |
1288 | } |
1289 | ||
3043c60c | 1290 | static int |
fe115628 | 1291 | shmem_pwrite_slow(struct page *page, int offset, int length, |
d174bd64 DV |
1292 | char __user *user_data, |
1293 | bool page_do_bit17_swizzling, | |
1294 | bool needs_clflush_before, | |
1295 | bool needs_clflush_after) | |
673a394b | 1296 | { |
d174bd64 DV |
1297 | char *vaddr; |
1298 | int ret; | |
e5281ccd | 1299 | |
d174bd64 | 1300 | vaddr = kmap(page); |
e7e58eb5 | 1301 | if (unlikely(needs_clflush_before || page_do_bit17_swizzling)) |
fe115628 | 1302 | shmem_clflush_swizzled_range(vaddr + offset, length, |
23c18c71 | 1303 | page_do_bit17_swizzling); |
d174bd64 | 1304 | if (page_do_bit17_swizzling) |
fe115628 CW |
1305 | ret = __copy_from_user_swizzled(vaddr, offset, user_data, |
1306 | length); | |
d174bd64 | 1307 | else |
fe115628 | 1308 | ret = __copy_from_user(vaddr + offset, user_data, length); |
d174bd64 | 1309 | if (needs_clflush_after) |
fe115628 | 1310 | shmem_clflush_swizzled_range(vaddr + offset, length, |
23c18c71 | 1311 | page_do_bit17_swizzling); |
d174bd64 | 1312 | kunmap(page); |
40123c1f | 1313 | |
755d2218 | 1314 | return ret ? -EFAULT : 0; |
40123c1f EA |
1315 | } |
1316 | ||
fe115628 CW |
1317 | /* Per-page copy function for the shmem pwrite fastpath. |
1318 | * Flushes invalid cachelines before writing to the target if | |
1319 | * needs_clflush_before is set and flushes out any written cachelines after | |
1320 | * writing if needs_clflush is set. | |
1321 | */ | |
40123c1f | 1322 | static int |
fe115628 CW |
1323 | shmem_pwrite(struct page *page, int offset, int len, char __user *user_data, |
1324 | bool page_do_bit17_swizzling, | |
1325 | bool needs_clflush_before, | |
1326 | bool needs_clflush_after) | |
40123c1f | 1327 | { |
fe115628 CW |
1328 | int ret; |
1329 | ||
1330 | ret = -ENODEV; | |
1331 | if (!page_do_bit17_swizzling) { | |
1332 | char *vaddr = kmap_atomic(page); | |
1333 | ||
1334 | if (needs_clflush_before) | |
1335 | drm_clflush_virt_range(vaddr + offset, len); | |
1336 | ret = __copy_from_user_inatomic(vaddr + offset, user_data, len); | |
1337 | if (needs_clflush_after) | |
1338 | drm_clflush_virt_range(vaddr + offset, len); | |
1339 | ||
1340 | kunmap_atomic(vaddr); | |
1341 | } | |
1342 | if (ret == 0) | |
1343 | return ret; | |
1344 | ||
1345 | return shmem_pwrite_slow(page, offset, len, user_data, | |
1346 | page_do_bit17_swizzling, | |
1347 | needs_clflush_before, | |
1348 | needs_clflush_after); | |
1349 | } | |
1350 | ||
1351 | static int | |
1352 | i915_gem_shmem_pwrite(struct drm_i915_gem_object *obj, | |
1353 | const struct drm_i915_gem_pwrite *args) | |
1354 | { | |
1355 | struct drm_i915_private *i915 = to_i915(obj->base.dev); | |
1356 | void __user *user_data; | |
1357 | u64 remain; | |
1358 | unsigned int obj_do_bit17_swizzling; | |
1359 | unsigned int partial_cacheline_write; | |
43394c7d | 1360 | unsigned int needs_clflush; |
fe115628 CW |
1361 | unsigned int offset, idx; |
1362 | int ret; | |
40123c1f | 1363 | |
fe115628 | 1364 | ret = mutex_lock_interruptible(&i915->drm.struct_mutex); |
755d2218 CW |
1365 | if (ret) |
1366 | return ret; | |
1367 | ||
fe115628 CW |
1368 | ret = i915_gem_obj_prepare_shmem_write(obj, &needs_clflush); |
1369 | mutex_unlock(&i915->drm.struct_mutex); | |
1370 | if (ret) | |
1371 | return ret; | |
673a394b | 1372 | |
fe115628 CW |
1373 | obj_do_bit17_swizzling = 0; |
1374 | if (i915_gem_object_needs_bit17_swizzle(obj)) | |
1375 | obj_do_bit17_swizzling = BIT(17); | |
e5281ccd | 1376 | |
fe115628 CW |
1377 | /* If we don't overwrite a cacheline completely we need to be |
1378 | * careful to have up-to-date data by first clflushing. Don't | |
1379 | * overcomplicate things and flush the entire patch. | |
1380 | */ | |
1381 | partial_cacheline_write = 0; | |
1382 | if (needs_clflush & CLFLUSH_BEFORE) | |
1383 | partial_cacheline_write = boot_cpu_data.x86_clflush_size - 1; | |
9da3da66 | 1384 | |
fe115628 CW |
1385 | user_data = u64_to_user_ptr(args->data_ptr); |
1386 | remain = args->size; | |
1387 | offset = offset_in_page(args->offset); | |
1388 | for (idx = args->offset >> PAGE_SHIFT; remain; idx++) { | |
1389 | struct page *page = i915_gem_object_get_page(obj, idx); | |
1390 | int length; | |
40123c1f | 1391 | |
fe115628 CW |
1392 | length = remain; |
1393 | if (offset + length > PAGE_SIZE) | |
1394 | length = PAGE_SIZE - offset; | |
755d2218 | 1395 | |
fe115628 CW |
1396 | ret = shmem_pwrite(page, offset, length, user_data, |
1397 | page_to_phys(page) & obj_do_bit17_swizzling, | |
1398 | (offset | length) & partial_cacheline_write, | |
1399 | needs_clflush & CLFLUSH_AFTER); | |
755d2218 | 1400 | if (ret) |
fe115628 | 1401 | break; |
755d2218 | 1402 | |
fe115628 CW |
1403 | remain -= length; |
1404 | user_data += length; | |
1405 | offset = 0; | |
8c59967c | 1406 | } |
673a394b | 1407 | |
de152b62 | 1408 | intel_fb_obj_flush(obj, false, ORIGIN_CPU); |
fe115628 | 1409 | i915_gem_obj_finish_shmem_access(obj); |
40123c1f | 1410 | return ret; |
673a394b EA |
1411 | } |
1412 | ||
1413 | /** | |
1414 | * Writes data to the object referenced by handle. | |
14bb2c11 TU |
1415 | * @dev: drm device |
1416 | * @data: ioctl data blob | |
1417 | * @file: drm file | |
673a394b EA |
1418 | * |
1419 | * On error, the contents of the buffer that were to be modified are undefined. | |
1420 | */ | |
1421 | int | |
1422 | i915_gem_pwrite_ioctl(struct drm_device *dev, void *data, | |
fbd5a26d | 1423 | struct drm_file *file) |
673a394b EA |
1424 | { |
1425 | struct drm_i915_gem_pwrite *args = data; | |
05394f39 | 1426 | struct drm_i915_gem_object *obj; |
51311d0a CW |
1427 | int ret; |
1428 | ||
1429 | if (args->size == 0) | |
1430 | return 0; | |
1431 | ||
1432 | if (!access_ok(VERIFY_READ, | |
3ed605bc | 1433 | u64_to_user_ptr(args->data_ptr), |
51311d0a CW |
1434 | args->size)) |
1435 | return -EFAULT; | |
1436 | ||
03ac0642 | 1437 | obj = i915_gem_object_lookup(file, args->handle); |
258a5ede CW |
1438 | if (!obj) |
1439 | return -ENOENT; | |
673a394b | 1440 | |
7dcd2499 | 1441 | /* Bounds check destination. */ |
966d5bf5 | 1442 | if (range_overflows_t(u64, args->offset, args->size, obj->base.size)) { |
ce9d419d | 1443 | ret = -EINVAL; |
258a5ede | 1444 | goto err; |
ce9d419d CW |
1445 | } |
1446 | ||
db53a302 CW |
1447 | trace_i915_gem_object_pwrite(obj, args->offset, args->size); |
1448 | ||
e95433c7 CW |
1449 | ret = i915_gem_object_wait(obj, |
1450 | I915_WAIT_INTERRUPTIBLE | | |
1451 | I915_WAIT_ALL, | |
1452 | MAX_SCHEDULE_TIMEOUT, | |
1453 | to_rps_client(file)); | |
258a5ede CW |
1454 | if (ret) |
1455 | goto err; | |
1456 | ||
fe115628 | 1457 | ret = i915_gem_object_pin_pages(obj); |
258a5ede | 1458 | if (ret) |
fe115628 | 1459 | goto err; |
258a5ede | 1460 | |
935aaa69 | 1461 | ret = -EFAULT; |
673a394b EA |
1462 | /* We can only do the GTT pwrite on untiled buffers, as otherwise |
1463 | * it would end up going through the fenced access, and we'll get | |
1464 | * different detiling behavior between reading and writing. | |
1465 | * pread/pwrite currently are reading and writing from the CPU | |
1466 | * perspective, requiring manual detiling by the client. | |
1467 | */ | |
6eae0059 | 1468 | if (!i915_gem_object_has_struct_page(obj) || |
9c870d03 | 1469 | cpu_write_needs_clflush(obj)) |
935aaa69 DV |
1470 | /* Note that the gtt paths might fail with non-page-backed user |
1471 | * pointers (e.g. gtt mappings when moving data between | |
9c870d03 CW |
1472 | * textures). Fallback to the shmem path in that case. |
1473 | */ | |
fe115628 | 1474 | ret = i915_gem_gtt_pwrite_fast(obj, args); |
673a394b | 1475 | |
d1054ee4 | 1476 | if (ret == -EFAULT || ret == -ENOSPC) { |
6a2c4232 CW |
1477 | if (obj->phys_handle) |
1478 | ret = i915_gem_phys_pwrite(obj, args, file); | |
b50a5371 | 1479 | else |
fe115628 | 1480 | ret = i915_gem_shmem_pwrite(obj, args); |
6a2c4232 | 1481 | } |
5c0480f2 | 1482 | |
fe115628 | 1483 | i915_gem_object_unpin_pages(obj); |
258a5ede | 1484 | err: |
f0cd5182 | 1485 | i915_gem_object_put(obj); |
258a5ede | 1486 | return ret; |
673a394b EA |
1487 | } |
1488 | ||
d243ad82 | 1489 | static inline enum fb_op_origin |
aeecc969 CW |
1490 | write_origin(struct drm_i915_gem_object *obj, unsigned domain) |
1491 | { | |
50349247 CW |
1492 | return (domain == I915_GEM_DOMAIN_GTT ? |
1493 | obj->frontbuffer_ggtt_origin : ORIGIN_CPU); | |
aeecc969 CW |
1494 | } |
1495 | ||
40e62d5d CW |
1496 | static void i915_gem_object_bump_inactive_ggtt(struct drm_i915_gem_object *obj) |
1497 | { | |
1498 | struct drm_i915_private *i915; | |
1499 | struct list_head *list; | |
1500 | struct i915_vma *vma; | |
1501 | ||
1502 | list_for_each_entry(vma, &obj->vma_list, obj_link) { | |
1503 | if (!i915_vma_is_ggtt(vma)) | |
28f412e0 | 1504 | break; |
40e62d5d CW |
1505 | |
1506 | if (i915_vma_is_active(vma)) | |
1507 | continue; | |
1508 | ||
1509 | if (!drm_mm_node_allocated(&vma->node)) | |
1510 | continue; | |
1511 | ||
1512 | list_move_tail(&vma->vm_link, &vma->vm->inactive_list); | |
1513 | } | |
1514 | ||
1515 | i915 = to_i915(obj->base.dev); | |
1516 | list = obj->bind_count ? &i915->mm.bound_list : &i915->mm.unbound_list; | |
56cea323 | 1517 | list_move_tail(&obj->global_link, list); |
40e62d5d CW |
1518 | } |
1519 | ||
673a394b | 1520 | /** |
2ef7eeaa EA |
1521 | * Called when user space prepares to use an object with the CPU, either |
1522 | * through the mmap ioctl's mapping or a GTT mapping. | |
14bb2c11 TU |
1523 | * @dev: drm device |
1524 | * @data: ioctl data blob | |
1525 | * @file: drm file | |
673a394b EA |
1526 | */ |
1527 | int | |
1528 | i915_gem_set_domain_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 1529 | struct drm_file *file) |
673a394b EA |
1530 | { |
1531 | struct drm_i915_gem_set_domain *args = data; | |
05394f39 | 1532 | struct drm_i915_gem_object *obj; |
2ef7eeaa EA |
1533 | uint32_t read_domains = args->read_domains; |
1534 | uint32_t write_domain = args->write_domain; | |
40e62d5d | 1535 | int err; |
673a394b | 1536 | |
2ef7eeaa | 1537 | /* Only handle setting domains to types used by the CPU. */ |
b8f9096d | 1538 | if ((write_domain | read_domains) & I915_GEM_GPU_DOMAINS) |
2ef7eeaa EA |
1539 | return -EINVAL; |
1540 | ||
1541 | /* Having something in the write domain implies it's in the read | |
1542 | * domain, and only that read domain. Enforce that in the request. | |
1543 | */ | |
1544 | if (write_domain != 0 && read_domains != write_domain) | |
1545 | return -EINVAL; | |
1546 | ||
03ac0642 | 1547 | obj = i915_gem_object_lookup(file, args->handle); |
b8f9096d CW |
1548 | if (!obj) |
1549 | return -ENOENT; | |
673a394b | 1550 | |
3236f57a CW |
1551 | /* Try to flush the object off the GPU without holding the lock. |
1552 | * We will repeat the flush holding the lock in the normal manner | |
1553 | * to catch cases where we are gazumped. | |
1554 | */ | |
40e62d5d | 1555 | err = i915_gem_object_wait(obj, |
e95433c7 CW |
1556 | I915_WAIT_INTERRUPTIBLE | |
1557 | (write_domain ? I915_WAIT_ALL : 0), | |
1558 | MAX_SCHEDULE_TIMEOUT, | |
1559 | to_rps_client(file)); | |
40e62d5d | 1560 | if (err) |
f0cd5182 | 1561 | goto out; |
b8f9096d | 1562 | |
40e62d5d CW |
1563 | /* Flush and acquire obj->pages so that we are coherent through |
1564 | * direct access in memory with previous cached writes through | |
1565 | * shmemfs and that our cache domain tracking remains valid. | |
1566 | * For example, if the obj->filp was moved to swap without us | |
1567 | * being notified and releasing the pages, we would mistakenly | |
1568 | * continue to assume that the obj remained out of the CPU cached | |
1569 | * domain. | |
1570 | */ | |
1571 | err = i915_gem_object_pin_pages(obj); | |
1572 | if (err) | |
f0cd5182 | 1573 | goto out; |
40e62d5d CW |
1574 | |
1575 | err = i915_mutex_lock_interruptible(dev); | |
1576 | if (err) | |
f0cd5182 | 1577 | goto out_unpin; |
3236f57a | 1578 | |
43566ded | 1579 | if (read_domains & I915_GEM_DOMAIN_GTT) |
40e62d5d | 1580 | err = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0); |
43566ded | 1581 | else |
40e62d5d | 1582 | err = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0); |
2ef7eeaa | 1583 | |
40e62d5d CW |
1584 | /* And bump the LRU for this access */ |
1585 | i915_gem_object_bump_inactive_ggtt(obj); | |
031b698a | 1586 | |
673a394b | 1587 | mutex_unlock(&dev->struct_mutex); |
b8f9096d | 1588 | |
40e62d5d CW |
1589 | if (write_domain != 0) |
1590 | intel_fb_obj_invalidate(obj, write_origin(obj, write_domain)); | |
1591 | ||
f0cd5182 | 1592 | out_unpin: |
40e62d5d | 1593 | i915_gem_object_unpin_pages(obj); |
f0cd5182 CW |
1594 | out: |
1595 | i915_gem_object_put(obj); | |
40e62d5d | 1596 | return err; |
673a394b EA |
1597 | } |
1598 | ||
1599 | /** | |
1600 | * Called when user space has done writes to this buffer | |
14bb2c11 TU |
1601 | * @dev: drm device |
1602 | * @data: ioctl data blob | |
1603 | * @file: drm file | |
673a394b EA |
1604 | */ |
1605 | int | |
1606 | i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 1607 | struct drm_file *file) |
673a394b EA |
1608 | { |
1609 | struct drm_i915_gem_sw_finish *args = data; | |
05394f39 | 1610 | struct drm_i915_gem_object *obj; |
c21724cc | 1611 | int err = 0; |
1d7cfea1 | 1612 | |
03ac0642 | 1613 | obj = i915_gem_object_lookup(file, args->handle); |
c21724cc CW |
1614 | if (!obj) |
1615 | return -ENOENT; | |
673a394b | 1616 | |
673a394b | 1617 | /* Pinned buffers may be scanout, so flush the cache */ |
c21724cc CW |
1618 | if (READ_ONCE(obj->pin_display)) { |
1619 | err = i915_mutex_lock_interruptible(dev); | |
1620 | if (!err) { | |
1621 | i915_gem_object_flush_cpu_write_domain(obj); | |
1622 | mutex_unlock(&dev->struct_mutex); | |
1623 | } | |
1624 | } | |
e47c68e9 | 1625 | |
f0cd5182 | 1626 | i915_gem_object_put(obj); |
c21724cc | 1627 | return err; |
673a394b EA |
1628 | } |
1629 | ||
1630 | /** | |
14bb2c11 TU |
1631 | * i915_gem_mmap_ioctl - Maps the contents of an object, returning the address |
1632 | * it is mapped to. | |
1633 | * @dev: drm device | |
1634 | * @data: ioctl data blob | |
1635 | * @file: drm file | |
673a394b EA |
1636 | * |
1637 | * While the mapping holds a reference on the contents of the object, it doesn't | |
1638 | * imply a ref on the object itself. | |
34367381 DV |
1639 | * |
1640 | * IMPORTANT: | |
1641 | * | |
1642 | * DRM driver writers who look a this function as an example for how to do GEM | |
1643 | * mmap support, please don't implement mmap support like here. The modern way | |
1644 | * to implement DRM mmap support is with an mmap offset ioctl (like | |
1645 | * i915_gem_mmap_gtt) and then using the mmap syscall on the DRM fd directly. | |
1646 | * That way debug tooling like valgrind will understand what's going on, hiding | |
1647 | * the mmap call in a driver private ioctl will break that. The i915 driver only | |
1648 | * does cpu mmaps this way because we didn't know better. | |
673a394b EA |
1649 | */ |
1650 | int | |
1651 | i915_gem_mmap_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 1652 | struct drm_file *file) |
673a394b EA |
1653 | { |
1654 | struct drm_i915_gem_mmap *args = data; | |
03ac0642 | 1655 | struct drm_i915_gem_object *obj; |
673a394b EA |
1656 | unsigned long addr; |
1657 | ||
1816f923 AG |
1658 | if (args->flags & ~(I915_MMAP_WC)) |
1659 | return -EINVAL; | |
1660 | ||
568a58e5 | 1661 | if (args->flags & I915_MMAP_WC && !boot_cpu_has(X86_FEATURE_PAT)) |
1816f923 AG |
1662 | return -ENODEV; |
1663 | ||
03ac0642 CW |
1664 | obj = i915_gem_object_lookup(file, args->handle); |
1665 | if (!obj) | |
bf79cb91 | 1666 | return -ENOENT; |
673a394b | 1667 | |
1286ff73 DV |
1668 | /* prime objects have no backing filp to GEM mmap |
1669 | * pages from. | |
1670 | */ | |
03ac0642 | 1671 | if (!obj->base.filp) { |
f0cd5182 | 1672 | i915_gem_object_put(obj); |
1286ff73 DV |
1673 | return -EINVAL; |
1674 | } | |
1675 | ||
03ac0642 | 1676 | addr = vm_mmap(obj->base.filp, 0, args->size, |
673a394b EA |
1677 | PROT_READ | PROT_WRITE, MAP_SHARED, |
1678 | args->offset); | |
1816f923 AG |
1679 | if (args->flags & I915_MMAP_WC) { |
1680 | struct mm_struct *mm = current->mm; | |
1681 | struct vm_area_struct *vma; | |
1682 | ||
80a89a5e | 1683 | if (down_write_killable(&mm->mmap_sem)) { |
f0cd5182 | 1684 | i915_gem_object_put(obj); |
80a89a5e MH |
1685 | return -EINTR; |
1686 | } | |
1816f923 AG |
1687 | vma = find_vma(mm, addr); |
1688 | if (vma) | |
1689 | vma->vm_page_prot = | |
1690 | pgprot_writecombine(vm_get_page_prot(vma->vm_flags)); | |
1691 | else | |
1692 | addr = -ENOMEM; | |
1693 | up_write(&mm->mmap_sem); | |
aeecc969 CW |
1694 | |
1695 | /* This may race, but that's ok, it only gets set */ | |
50349247 | 1696 | WRITE_ONCE(obj->frontbuffer_ggtt_origin, ORIGIN_CPU); |
1816f923 | 1697 | } |
f0cd5182 | 1698 | i915_gem_object_put(obj); |
673a394b EA |
1699 | if (IS_ERR((void *)addr)) |
1700 | return addr; | |
1701 | ||
1702 | args->addr_ptr = (uint64_t) addr; | |
1703 | ||
1704 | return 0; | |
1705 | } | |
1706 | ||
03af84fe CW |
1707 | static unsigned int tile_row_pages(struct drm_i915_gem_object *obj) |
1708 | { | |
6649a0b6 | 1709 | return i915_gem_object_get_tile_row_size(obj) >> PAGE_SHIFT; |
03af84fe CW |
1710 | } |
1711 | ||
4cc69075 CW |
1712 | /** |
1713 | * i915_gem_mmap_gtt_version - report the current feature set for GTT mmaps | |
1714 | * | |
1715 | * A history of the GTT mmap interface: | |
1716 | * | |
1717 | * 0 - Everything had to fit into the GTT. Both parties of a memcpy had to | |
1718 | * aligned and suitable for fencing, and still fit into the available | |
1719 | * mappable space left by the pinned display objects. A classic problem | |
1720 | * we called the page-fault-of-doom where we would ping-pong between | |
1721 | * two objects that could not fit inside the GTT and so the memcpy | |
1722 | * would page one object in at the expense of the other between every | |
1723 | * single byte. | |
1724 | * | |
1725 | * 1 - Objects can be any size, and have any compatible fencing (X Y, or none | |
1726 | * as set via i915_gem_set_tiling() [DRM_I915_GEM_SET_TILING]). If the | |
1727 | * object is too large for the available space (or simply too large | |
1728 | * for the mappable aperture!), a view is created instead and faulted | |
1729 | * into userspace. (This view is aligned and sized appropriately for | |
1730 | * fenced access.) | |
1731 | * | |
1732 | * Restrictions: | |
1733 | * | |
1734 | * * snoopable objects cannot be accessed via the GTT. It can cause machine | |
1735 | * hangs on some architectures, corruption on others. An attempt to service | |
1736 | * a GTT page fault from a snoopable object will generate a SIGBUS. | |
1737 | * | |
1738 | * * the object must be able to fit into RAM (physical memory, though no | |
1739 | * limited to the mappable aperture). | |
1740 | * | |
1741 | * | |
1742 | * Caveats: | |
1743 | * | |
1744 | * * a new GTT page fault will synchronize rendering from the GPU and flush | |
1745 | * all data to system memory. Subsequent access will not be synchronized. | |
1746 | * | |
1747 | * * all mappings are revoked on runtime device suspend. | |
1748 | * | |
1749 | * * there are only 8, 16 or 32 fence registers to share between all users | |
1750 | * (older machines require fence register for display and blitter access | |
1751 | * as well). Contention of the fence registers will cause the previous users | |
1752 | * to be unmapped and any new access will generate new page faults. | |
1753 | * | |
1754 | * * running out of memory while servicing a fault may generate a SIGBUS, | |
1755 | * rather than the expected SIGSEGV. | |
1756 | */ | |
1757 | int i915_gem_mmap_gtt_version(void) | |
1758 | { | |
1759 | return 1; | |
1760 | } | |
1761 | ||
2d4281bb CW |
1762 | static inline struct i915_ggtt_view |
1763 | compute_partial_view(struct drm_i915_gem_object *obj, | |
2d4281bb CW |
1764 | pgoff_t page_offset, |
1765 | unsigned int chunk) | |
1766 | { | |
1767 | struct i915_ggtt_view view; | |
1768 | ||
1769 | if (i915_gem_object_is_tiled(obj)) | |
1770 | chunk = roundup(chunk, tile_row_pages(obj)); | |
1771 | ||
2d4281bb | 1772 | view.type = I915_GGTT_VIEW_PARTIAL; |
8bab1193 CW |
1773 | view.partial.offset = rounddown(page_offset, chunk); |
1774 | view.partial.size = | |
2d4281bb | 1775 | min_t(unsigned int, chunk, |
8bab1193 | 1776 | (obj->base.size >> PAGE_SHIFT) - view.partial.offset); |
2d4281bb CW |
1777 | |
1778 | /* If the partial covers the entire object, just create a normal VMA. */ | |
1779 | if (chunk >= obj->base.size >> PAGE_SHIFT) | |
1780 | view.type = I915_GGTT_VIEW_NORMAL; | |
1781 | ||
1782 | return view; | |
1783 | } | |
1784 | ||
de151cf6 JB |
1785 | /** |
1786 | * i915_gem_fault - fault a page into the GTT | |
058d88c4 | 1787 | * @area: CPU VMA in question |
d9072a3e | 1788 | * @vmf: fault info |
de151cf6 JB |
1789 | * |
1790 | * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped | |
1791 | * from userspace. The fault handler takes care of binding the object to | |
1792 | * the GTT (if needed), allocating and programming a fence register (again, | |
1793 | * only if needed based on whether the old reg is still valid or the object | |
1794 | * is tiled) and inserting a new PTE into the faulting process. | |
1795 | * | |
1796 | * Note that the faulting process may involve evicting existing objects | |
1797 | * from the GTT and/or fence registers to make room. So performance may | |
1798 | * suffer if the GTT working set is large or there are few fence registers | |
1799 | * left. | |
4cc69075 CW |
1800 | * |
1801 | * The current feature set supported by i915_gem_fault() and thus GTT mmaps | |
1802 | * is exposed via I915_PARAM_MMAP_GTT_VERSION (see i915_gem_mmap_gtt_version). | |
de151cf6 | 1803 | */ |
058d88c4 | 1804 | int i915_gem_fault(struct vm_area_struct *area, struct vm_fault *vmf) |
de151cf6 | 1805 | { |
03af84fe | 1806 | #define MIN_CHUNK_PAGES ((1 << 20) >> PAGE_SHIFT) /* 1 MiB */ |
058d88c4 | 1807 | struct drm_i915_gem_object *obj = to_intel_bo(area->vm_private_data); |
05394f39 | 1808 | struct drm_device *dev = obj->base.dev; |
72e96d64 JL |
1809 | struct drm_i915_private *dev_priv = to_i915(dev); |
1810 | struct i915_ggtt *ggtt = &dev_priv->ggtt; | |
b8f9096d | 1811 | bool write = !!(vmf->flags & FAULT_FLAG_WRITE); |
058d88c4 | 1812 | struct i915_vma *vma; |
de151cf6 | 1813 | pgoff_t page_offset; |
82118877 | 1814 | unsigned int flags; |
b8f9096d | 1815 | int ret; |
f65c9168 | 1816 | |
de151cf6 | 1817 | /* We don't use vmf->pgoff since that has the fake offset */ |
1a29d85e | 1818 | page_offset = (vmf->address - area->vm_start) >> PAGE_SHIFT; |
de151cf6 | 1819 | |
db53a302 CW |
1820 | trace_i915_gem_object_fault(obj, page_offset, true, write); |
1821 | ||
6e4930f6 | 1822 | /* Try to flush the object off the GPU first without holding the lock. |
b8f9096d | 1823 | * Upon acquiring the lock, we will perform our sanity checks and then |
6e4930f6 CW |
1824 | * repeat the flush holding the lock in the normal manner to catch cases |
1825 | * where we are gazumped. | |
1826 | */ | |
e95433c7 CW |
1827 | ret = i915_gem_object_wait(obj, |
1828 | I915_WAIT_INTERRUPTIBLE, | |
1829 | MAX_SCHEDULE_TIMEOUT, | |
1830 | NULL); | |
6e4930f6 | 1831 | if (ret) |
b8f9096d CW |
1832 | goto err; |
1833 | ||
40e62d5d CW |
1834 | ret = i915_gem_object_pin_pages(obj); |
1835 | if (ret) | |
1836 | goto err; | |
1837 | ||
b8f9096d CW |
1838 | intel_runtime_pm_get(dev_priv); |
1839 | ||
1840 | ret = i915_mutex_lock_interruptible(dev); | |
1841 | if (ret) | |
1842 | goto err_rpm; | |
6e4930f6 | 1843 | |
eb119bd6 | 1844 | /* Access to snoopable pages through the GTT is incoherent. */ |
0031fb96 | 1845 | if (obj->cache_level != I915_CACHE_NONE && !HAS_LLC(dev_priv)) { |
ddeff6ee | 1846 | ret = -EFAULT; |
b8f9096d | 1847 | goto err_unlock; |
eb119bd6 CW |
1848 | } |
1849 | ||
82118877 CW |
1850 | /* If the object is smaller than a couple of partial vma, it is |
1851 | * not worth only creating a single partial vma - we may as well | |
1852 | * clear enough space for the full object. | |
1853 | */ | |
1854 | flags = PIN_MAPPABLE; | |
1855 | if (obj->base.size > 2 * MIN_CHUNK_PAGES << PAGE_SHIFT) | |
1856 | flags |= PIN_NONBLOCK | PIN_NONFAULT; | |
1857 | ||
a61007a8 | 1858 | /* Now pin it into the GTT as needed */ |
82118877 | 1859 | vma = i915_gem_object_ggtt_pin(obj, NULL, 0, 0, flags); |
a61007a8 | 1860 | if (IS_ERR(vma)) { |
a61007a8 | 1861 | /* Use a partial view if it is bigger than available space */ |
2d4281bb | 1862 | struct i915_ggtt_view view = |
8201c1fa | 1863 | compute_partial_view(obj, page_offset, MIN_CHUNK_PAGES); |
aa136d9d | 1864 | |
50349247 CW |
1865 | /* Userspace is now writing through an untracked VMA, abandon |
1866 | * all hope that the hardware is able to track future writes. | |
1867 | */ | |
1868 | obj->frontbuffer_ggtt_origin = ORIGIN_CPU; | |
1869 | ||
a61007a8 CW |
1870 | vma = i915_gem_object_ggtt_pin(obj, &view, 0, 0, PIN_MAPPABLE); |
1871 | } | |
058d88c4 CW |
1872 | if (IS_ERR(vma)) { |
1873 | ret = PTR_ERR(vma); | |
b8f9096d | 1874 | goto err_unlock; |
058d88c4 | 1875 | } |
4a684a41 | 1876 | |
c9839303 CW |
1877 | ret = i915_gem_object_set_to_gtt_domain(obj, write); |
1878 | if (ret) | |
b8f9096d | 1879 | goto err_unpin; |
74898d7e | 1880 | |
49ef5294 | 1881 | ret = i915_vma_get_fence(vma); |
d9e86c0e | 1882 | if (ret) |
b8f9096d | 1883 | goto err_unpin; |
7d1c4804 | 1884 | |
275f039d | 1885 | /* Mark as being mmapped into userspace for later revocation */ |
9c870d03 | 1886 | assert_rpm_wakelock_held(dev_priv); |
275f039d CW |
1887 | if (list_empty(&obj->userfault_link)) |
1888 | list_add(&obj->userfault_link, &dev_priv->mm.userfault_list); | |
275f039d | 1889 | |
b90b91d8 | 1890 | /* Finally, remap it using the new GTT offset */ |
c58305af | 1891 | ret = remap_io_mapping(area, |
8bab1193 | 1892 | area->vm_start + (vma->ggtt_view.partial.offset << PAGE_SHIFT), |
c58305af CW |
1893 | (ggtt->mappable_base + vma->node.start) >> PAGE_SHIFT, |
1894 | min_t(u64, vma->size, area->vm_end - area->vm_start), | |
1895 | &ggtt->mappable); | |
a61007a8 | 1896 | |
b8f9096d | 1897 | err_unpin: |
058d88c4 | 1898 | __i915_vma_unpin(vma); |
b8f9096d | 1899 | err_unlock: |
de151cf6 | 1900 | mutex_unlock(&dev->struct_mutex); |
b8f9096d CW |
1901 | err_rpm: |
1902 | intel_runtime_pm_put(dev_priv); | |
40e62d5d | 1903 | i915_gem_object_unpin_pages(obj); |
b8f9096d | 1904 | err: |
de151cf6 | 1905 | switch (ret) { |
d9bc7e9f | 1906 | case -EIO: |
2232f031 DV |
1907 | /* |
1908 | * We eat errors when the gpu is terminally wedged to avoid | |
1909 | * userspace unduly crashing (gl has no provisions for mmaps to | |
1910 | * fail). But any other -EIO isn't ours (e.g. swap in failure) | |
1911 | * and so needs to be reported. | |
1912 | */ | |
1913 | if (!i915_terminally_wedged(&dev_priv->gpu_error)) { | |
f65c9168 PZ |
1914 | ret = VM_FAULT_SIGBUS; |
1915 | break; | |
1916 | } | |
045e769a | 1917 | case -EAGAIN: |
571c608d DV |
1918 | /* |
1919 | * EAGAIN means the gpu is hung and we'll wait for the error | |
1920 | * handler to reset everything when re-faulting in | |
1921 | * i915_mutex_lock_interruptible. | |
d9bc7e9f | 1922 | */ |
c715089f CW |
1923 | case 0: |
1924 | case -ERESTARTSYS: | |
bed636ab | 1925 | case -EINTR: |
e79e0fe3 DR |
1926 | case -EBUSY: |
1927 | /* | |
1928 | * EBUSY is ok: this just means that another thread | |
1929 | * already did the job. | |
1930 | */ | |
f65c9168 PZ |
1931 | ret = VM_FAULT_NOPAGE; |
1932 | break; | |
de151cf6 | 1933 | case -ENOMEM: |
f65c9168 PZ |
1934 | ret = VM_FAULT_OOM; |
1935 | break; | |
a7c2e1aa | 1936 | case -ENOSPC: |
45d67817 | 1937 | case -EFAULT: |
f65c9168 PZ |
1938 | ret = VM_FAULT_SIGBUS; |
1939 | break; | |
de151cf6 | 1940 | default: |
a7c2e1aa | 1941 | WARN_ONCE(ret, "unhandled error in i915_gem_fault: %i\n", ret); |
f65c9168 PZ |
1942 | ret = VM_FAULT_SIGBUS; |
1943 | break; | |
de151cf6 | 1944 | } |
f65c9168 | 1945 | return ret; |
de151cf6 JB |
1946 | } |
1947 | ||
901782b2 CW |
1948 | /** |
1949 | * i915_gem_release_mmap - remove physical page mappings | |
1950 | * @obj: obj in question | |
1951 | * | |
af901ca1 | 1952 | * Preserve the reservation of the mmapping with the DRM core code, but |
901782b2 CW |
1953 | * relinquish ownership of the pages back to the system. |
1954 | * | |
1955 | * It is vital that we remove the page mapping if we have mapped a tiled | |
1956 | * object through the GTT and then lose the fence register due to | |
1957 | * resource pressure. Similarly if the object has been moved out of the | |
1958 | * aperture, than pages mapped into userspace must be revoked. Removing the | |
1959 | * mapping will then trigger a page fault on the next user access, allowing | |
1960 | * fixup by i915_gem_fault(). | |
1961 | */ | |
d05ca301 | 1962 | void |
05394f39 | 1963 | i915_gem_release_mmap(struct drm_i915_gem_object *obj) |
901782b2 | 1964 | { |
275f039d | 1965 | struct drm_i915_private *i915 = to_i915(obj->base.dev); |
275f039d | 1966 | |
349f2ccf CW |
1967 | /* Serialisation between user GTT access and our code depends upon |
1968 | * revoking the CPU's PTE whilst the mutex is held. The next user | |
1969 | * pagefault then has to wait until we release the mutex. | |
9c870d03 CW |
1970 | * |
1971 | * Note that RPM complicates somewhat by adding an additional | |
1972 | * requirement that operations to the GGTT be made holding the RPM | |
1973 | * wakeref. | |
349f2ccf | 1974 | */ |
275f039d | 1975 | lockdep_assert_held(&i915->drm.struct_mutex); |
9c870d03 | 1976 | intel_runtime_pm_get(i915); |
349f2ccf | 1977 | |
3594a3e2 | 1978 | if (list_empty(&obj->userfault_link)) |
9c870d03 | 1979 | goto out; |
901782b2 | 1980 | |
3594a3e2 | 1981 | list_del_init(&obj->userfault_link); |
6796cb16 DH |
1982 | drm_vma_node_unmap(&obj->base.vma_node, |
1983 | obj->base.dev->anon_inode->i_mapping); | |
349f2ccf CW |
1984 | |
1985 | /* Ensure that the CPU's PTE are revoked and there are not outstanding | |
1986 | * memory transactions from userspace before we return. The TLB | |
1987 | * flushing implied above by changing the PTE above *should* be | |
1988 | * sufficient, an extra barrier here just provides us with a bit | |
1989 | * of paranoid documentation about our requirement to serialise | |
1990 | * memory writes before touching registers / GSM. | |
1991 | */ | |
1992 | wmb(); | |
9c870d03 CW |
1993 | |
1994 | out: | |
1995 | intel_runtime_pm_put(i915); | |
901782b2 CW |
1996 | } |
1997 | ||
7c108fd8 | 1998 | void i915_gem_runtime_suspend(struct drm_i915_private *dev_priv) |
eedd10f4 | 1999 | { |
3594a3e2 | 2000 | struct drm_i915_gem_object *obj, *on; |
7c108fd8 | 2001 | int i; |
eedd10f4 | 2002 | |
3594a3e2 CW |
2003 | /* |
2004 | * Only called during RPM suspend. All users of the userfault_list | |
2005 | * must be holding an RPM wakeref to ensure that this can not | |
2006 | * run concurrently with themselves (and use the struct_mutex for | |
2007 | * protection between themselves). | |
2008 | */ | |
275f039d | 2009 | |
3594a3e2 CW |
2010 | list_for_each_entry_safe(obj, on, |
2011 | &dev_priv->mm.userfault_list, userfault_link) { | |
2012 | list_del_init(&obj->userfault_link); | |
275f039d CW |
2013 | drm_vma_node_unmap(&obj->base.vma_node, |
2014 | obj->base.dev->anon_inode->i_mapping); | |
275f039d | 2015 | } |
7c108fd8 CW |
2016 | |
2017 | /* The fence will be lost when the device powers down. If any were | |
2018 | * in use by hardware (i.e. they are pinned), we should not be powering | |
2019 | * down! All other fences will be reacquired by the user upon waking. | |
2020 | */ | |
2021 | for (i = 0; i < dev_priv->num_fence_regs; i++) { | |
2022 | struct drm_i915_fence_reg *reg = &dev_priv->fence_regs[i]; | |
2023 | ||
e0ec3ec6 CW |
2024 | /* Ideally we want to assert that the fence register is not |
2025 | * live at this point (i.e. that no piece of code will be | |
2026 | * trying to write through fence + GTT, as that both violates | |
2027 | * our tracking of activity and associated locking/barriers, | |
2028 | * but also is illegal given that the hw is powered down). | |
2029 | * | |
2030 | * Previously we used reg->pin_count as a "liveness" indicator. | |
2031 | * That is not sufficient, and we need a more fine-grained | |
2032 | * tool if we want to have a sanity check here. | |
2033 | */ | |
7c108fd8 CW |
2034 | |
2035 | if (!reg->vma) | |
2036 | continue; | |
2037 | ||
2038 | GEM_BUG_ON(!list_empty(®->vma->obj->userfault_link)); | |
2039 | reg->dirty = true; | |
2040 | } | |
eedd10f4 CW |
2041 | } |
2042 | ||
d8cb5086 CW |
2043 | static int i915_gem_object_create_mmap_offset(struct drm_i915_gem_object *obj) |
2044 | { | |
fac5e23e | 2045 | struct drm_i915_private *dev_priv = to_i915(obj->base.dev); |
f3f6184c | 2046 | int err; |
da494d7c | 2047 | |
f3f6184c | 2048 | err = drm_gem_create_mmap_offset(&obj->base); |
b42a13d9 | 2049 | if (likely(!err)) |
f3f6184c | 2050 | return 0; |
d8cb5086 | 2051 | |
b42a13d9 CW |
2052 | /* Attempt to reap some mmap space from dead objects */ |
2053 | do { | |
2054 | err = i915_gem_wait_for_idle(dev_priv, I915_WAIT_INTERRUPTIBLE); | |
2055 | if (err) | |
2056 | break; | |
f3f6184c | 2057 | |
b42a13d9 | 2058 | i915_gem_drain_freed_objects(dev_priv); |
f3f6184c | 2059 | err = drm_gem_create_mmap_offset(&obj->base); |
b42a13d9 CW |
2060 | if (!err) |
2061 | break; | |
2062 | ||
2063 | } while (flush_delayed_work(&dev_priv->gt.retire_work)); | |
da494d7c | 2064 | |
f3f6184c | 2065 | return err; |
d8cb5086 CW |
2066 | } |
2067 | ||
2068 | static void i915_gem_object_free_mmap_offset(struct drm_i915_gem_object *obj) | |
2069 | { | |
d8cb5086 CW |
2070 | drm_gem_free_mmap_offset(&obj->base); |
2071 | } | |
2072 | ||
da6b51d0 | 2073 | int |
ff72145b DA |
2074 | i915_gem_mmap_gtt(struct drm_file *file, |
2075 | struct drm_device *dev, | |
da6b51d0 | 2076 | uint32_t handle, |
ff72145b | 2077 | uint64_t *offset) |
de151cf6 | 2078 | { |
05394f39 | 2079 | struct drm_i915_gem_object *obj; |
de151cf6 JB |
2080 | int ret; |
2081 | ||
03ac0642 | 2082 | obj = i915_gem_object_lookup(file, handle); |
f3f6184c CW |
2083 | if (!obj) |
2084 | return -ENOENT; | |
ab18282d | 2085 | |
d8cb5086 | 2086 | ret = i915_gem_object_create_mmap_offset(obj); |
f3f6184c CW |
2087 | if (ret == 0) |
2088 | *offset = drm_vma_node_offset_addr(&obj->base.vma_node); | |
de151cf6 | 2089 | |
f0cd5182 | 2090 | i915_gem_object_put(obj); |
1d7cfea1 | 2091 | return ret; |
de151cf6 JB |
2092 | } |
2093 | ||
ff72145b DA |
2094 | /** |
2095 | * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing | |
2096 | * @dev: DRM device | |
2097 | * @data: GTT mapping ioctl data | |
2098 | * @file: GEM object info | |
2099 | * | |
2100 | * Simply returns the fake offset to userspace so it can mmap it. | |
2101 | * The mmap call will end up in drm_gem_mmap(), which will set things | |
2102 | * up so we can get faults in the handler above. | |
2103 | * | |
2104 | * The fault handler will take care of binding the object into the GTT | |
2105 | * (since it may have been evicted to make room for something), allocating | |
2106 | * a fence register, and mapping the appropriate aperture address into | |
2107 | * userspace. | |
2108 | */ | |
2109 | int | |
2110 | i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data, | |
2111 | struct drm_file *file) | |
2112 | { | |
2113 | struct drm_i915_gem_mmap_gtt *args = data; | |
2114 | ||
da6b51d0 | 2115 | return i915_gem_mmap_gtt(file, dev, args->handle, &args->offset); |
ff72145b DA |
2116 | } |
2117 | ||
225067ee DV |
2118 | /* Immediately discard the backing storage */ |
2119 | static void | |
2120 | i915_gem_object_truncate(struct drm_i915_gem_object *obj) | |
e5281ccd | 2121 | { |
4d6294bf | 2122 | i915_gem_object_free_mmap_offset(obj); |
1286ff73 | 2123 | |
4d6294bf CW |
2124 | if (obj->base.filp == NULL) |
2125 | return; | |
e5281ccd | 2126 | |
225067ee DV |
2127 | /* Our goal here is to return as much of the memory as |
2128 | * is possible back to the system as we are called from OOM. | |
2129 | * To do this we must instruct the shmfs to drop all of its | |
2130 | * backing pages, *now*. | |
2131 | */ | |
5537252b | 2132 | shmem_truncate_range(file_inode(obj->base.filp), 0, (loff_t)-1); |
a4f5ea64 | 2133 | obj->mm.madv = __I915_MADV_PURGED; |
225067ee | 2134 | } |
e5281ccd | 2135 | |
5537252b | 2136 | /* Try to discard unwanted pages */ |
03ac84f1 | 2137 | void __i915_gem_object_invalidate(struct drm_i915_gem_object *obj) |
225067ee | 2138 | { |
5537252b CW |
2139 | struct address_space *mapping; |
2140 | ||
1233e2db CW |
2141 | lockdep_assert_held(&obj->mm.lock); |
2142 | GEM_BUG_ON(obj->mm.pages); | |
2143 | ||
a4f5ea64 | 2144 | switch (obj->mm.madv) { |
5537252b CW |
2145 | case I915_MADV_DONTNEED: |
2146 | i915_gem_object_truncate(obj); | |
2147 | case __I915_MADV_PURGED: | |
2148 | return; | |
2149 | } | |
2150 | ||
2151 | if (obj->base.filp == NULL) | |
2152 | return; | |
2153 | ||
93c76a3d | 2154 | mapping = obj->base.filp->f_mapping, |
5537252b | 2155 | invalidate_mapping_pages(mapping, 0, (loff_t)-1); |
e5281ccd CW |
2156 | } |
2157 | ||
5cdf5881 | 2158 | static void |
03ac84f1 CW |
2159 | i915_gem_object_put_pages_gtt(struct drm_i915_gem_object *obj, |
2160 | struct sg_table *pages) | |
673a394b | 2161 | { |
85d1225e DG |
2162 | struct sgt_iter sgt_iter; |
2163 | struct page *page; | |
1286ff73 | 2164 | |
e5facdf9 | 2165 | __i915_gem_object_release_shmem(obj, pages, true); |
673a394b | 2166 | |
03ac84f1 | 2167 | i915_gem_gtt_finish_pages(obj, pages); |
e2273302 | 2168 | |
6dacfd2f | 2169 | if (i915_gem_object_needs_bit17_swizzle(obj)) |
03ac84f1 | 2170 | i915_gem_object_save_bit_17_swizzle(obj, pages); |
280b713b | 2171 | |
03ac84f1 | 2172 | for_each_sgt_page(page, sgt_iter, pages) { |
a4f5ea64 | 2173 | if (obj->mm.dirty) |
9da3da66 | 2174 | set_page_dirty(page); |
3ef94daa | 2175 | |
a4f5ea64 | 2176 | if (obj->mm.madv == I915_MADV_WILLNEED) |
9da3da66 | 2177 | mark_page_accessed(page); |
3ef94daa | 2178 | |
09cbfeaf | 2179 | put_page(page); |
3ef94daa | 2180 | } |
a4f5ea64 | 2181 | obj->mm.dirty = false; |
673a394b | 2182 | |
03ac84f1 CW |
2183 | sg_free_table(pages); |
2184 | kfree(pages); | |
37e680a1 | 2185 | } |
6c085a72 | 2186 | |
96d77634 CW |
2187 | static void __i915_gem_object_reset_page_iter(struct drm_i915_gem_object *obj) |
2188 | { | |
2189 | struct radix_tree_iter iter; | |
2190 | void **slot; | |
2191 | ||
a4f5ea64 CW |
2192 | radix_tree_for_each_slot(slot, &obj->mm.get_page.radix, &iter, 0) |
2193 | radix_tree_delete(&obj->mm.get_page.radix, iter.index); | |
96d77634 CW |
2194 | } |
2195 | ||
548625ee CW |
2196 | void __i915_gem_object_put_pages(struct drm_i915_gem_object *obj, |
2197 | enum i915_mm_subclass subclass) | |
37e680a1 | 2198 | { |
03ac84f1 | 2199 | struct sg_table *pages; |
37e680a1 | 2200 | |
a4f5ea64 | 2201 | if (i915_gem_object_has_pinned_pages(obj)) |
03ac84f1 | 2202 | return; |
a5570178 | 2203 | |
15717de2 | 2204 | GEM_BUG_ON(obj->bind_count); |
1233e2db CW |
2205 | if (!READ_ONCE(obj->mm.pages)) |
2206 | return; | |
2207 | ||
2208 | /* May be called by shrinker from within get_pages() (on another bo) */ | |
548625ee | 2209 | mutex_lock_nested(&obj->mm.lock, subclass); |
1233e2db CW |
2210 | if (unlikely(atomic_read(&obj->mm.pages_pin_count))) |
2211 | goto unlock; | |
3e123027 | 2212 | |
a2165e31 CW |
2213 | /* ->put_pages might need to allocate memory for the bit17 swizzle |
2214 | * array, hence protect them from being reaped by removing them from gtt | |
2215 | * lists early. */ | |
03ac84f1 CW |
2216 | pages = fetch_and_zero(&obj->mm.pages); |
2217 | GEM_BUG_ON(!pages); | |
a2165e31 | 2218 | |
a4f5ea64 | 2219 | if (obj->mm.mapping) { |
4b30cb23 CW |
2220 | void *ptr; |
2221 | ||
a4f5ea64 | 2222 | ptr = ptr_mask_bits(obj->mm.mapping); |
4b30cb23 CW |
2223 | if (is_vmalloc_addr(ptr)) |
2224 | vunmap(ptr); | |
fb8621d3 | 2225 | else |
4b30cb23 CW |
2226 | kunmap(kmap_to_page(ptr)); |
2227 | ||
a4f5ea64 | 2228 | obj->mm.mapping = NULL; |
0a798eb9 CW |
2229 | } |
2230 | ||
96d77634 CW |
2231 | __i915_gem_object_reset_page_iter(obj); |
2232 | ||
03ac84f1 | 2233 | obj->ops->put_pages(obj, pages); |
1233e2db CW |
2234 | unlock: |
2235 | mutex_unlock(&obj->mm.lock); | |
6c085a72 CW |
2236 | } |
2237 | ||
935a2f77 | 2238 | static bool i915_sg_trim(struct sg_table *orig_st) |
0c40ce13 TU |
2239 | { |
2240 | struct sg_table new_st; | |
2241 | struct scatterlist *sg, *new_sg; | |
2242 | unsigned int i; | |
2243 | ||
2244 | if (orig_st->nents == orig_st->orig_nents) | |
935a2f77 | 2245 | return false; |
0c40ce13 | 2246 | |
8bfc478f | 2247 | if (sg_alloc_table(&new_st, orig_st->nents, GFP_KERNEL | __GFP_NOWARN)) |
935a2f77 | 2248 | return false; |
0c40ce13 TU |
2249 | |
2250 | new_sg = new_st.sgl; | |
2251 | for_each_sg(orig_st->sgl, sg, orig_st->nents, i) { | |
2252 | sg_set_page(new_sg, sg_page(sg), sg->length, 0); | |
2253 | /* called before being DMA mapped, no need to copy sg->dma_* */ | |
2254 | new_sg = sg_next(new_sg); | |
2255 | } | |
c2dc6cc9 | 2256 | GEM_BUG_ON(new_sg); /* Should walk exactly nents and hit the end */ |
0c40ce13 TU |
2257 | |
2258 | sg_free_table(orig_st); | |
2259 | ||
2260 | *orig_st = new_st; | |
935a2f77 | 2261 | return true; |
0c40ce13 TU |
2262 | } |
2263 | ||
03ac84f1 | 2264 | static struct sg_table * |
6c085a72 | 2265 | i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj) |
e5281ccd | 2266 | { |
fac5e23e | 2267 | struct drm_i915_private *dev_priv = to_i915(obj->base.dev); |
d766ef53 CW |
2268 | const unsigned long page_count = obj->base.size / PAGE_SIZE; |
2269 | unsigned long i; | |
e5281ccd | 2270 | struct address_space *mapping; |
9da3da66 CW |
2271 | struct sg_table *st; |
2272 | struct scatterlist *sg; | |
85d1225e | 2273 | struct sgt_iter sgt_iter; |
e5281ccd | 2274 | struct page *page; |
90797e6d | 2275 | unsigned long last_pfn = 0; /* suppress gcc warning */ |
4ff340f0 | 2276 | unsigned int max_segment; |
e2273302 | 2277 | int ret; |
6c085a72 | 2278 | gfp_t gfp; |
e5281ccd | 2279 | |
6c085a72 CW |
2280 | /* Assert that the object is not currently in any GPU domain. As it |
2281 | * wasn't in the GTT, there shouldn't be any way it could have been in | |
2282 | * a GPU cache | |
2283 | */ | |
03ac84f1 CW |
2284 | GEM_BUG_ON(obj->base.read_domains & I915_GEM_GPU_DOMAINS); |
2285 | GEM_BUG_ON(obj->base.write_domain & I915_GEM_GPU_DOMAINS); | |
6c085a72 | 2286 | |
7453c549 | 2287 | max_segment = swiotlb_max_segment(); |
871dfbd6 | 2288 | if (!max_segment) |
4ff340f0 | 2289 | max_segment = rounddown(UINT_MAX, PAGE_SIZE); |
871dfbd6 | 2290 | |
9da3da66 CW |
2291 | st = kmalloc(sizeof(*st), GFP_KERNEL); |
2292 | if (st == NULL) | |
03ac84f1 | 2293 | return ERR_PTR(-ENOMEM); |
9da3da66 | 2294 | |
d766ef53 | 2295 | rebuild_st: |
9da3da66 | 2296 | if (sg_alloc_table(st, page_count, GFP_KERNEL)) { |
9da3da66 | 2297 | kfree(st); |
03ac84f1 | 2298 | return ERR_PTR(-ENOMEM); |
9da3da66 | 2299 | } |
e5281ccd | 2300 | |
9da3da66 CW |
2301 | /* Get the list of pages out of our struct file. They'll be pinned |
2302 | * at this point until we release them. | |
2303 | * | |
2304 | * Fail silently without starting the shrinker | |
2305 | */ | |
93c76a3d | 2306 | mapping = obj->base.filp->f_mapping; |
c62d2555 | 2307 | gfp = mapping_gfp_constraint(mapping, ~(__GFP_IO | __GFP_RECLAIM)); |
d0164adc | 2308 | gfp |= __GFP_NORETRY | __GFP_NOWARN; |
90797e6d ID |
2309 | sg = st->sgl; |
2310 | st->nents = 0; | |
2311 | for (i = 0; i < page_count; i++) { | |
6c085a72 CW |
2312 | page = shmem_read_mapping_page_gfp(mapping, i, gfp); |
2313 | if (IS_ERR(page)) { | |
21ab4e74 CW |
2314 | i915_gem_shrink(dev_priv, |
2315 | page_count, | |
2316 | I915_SHRINK_BOUND | | |
2317 | I915_SHRINK_UNBOUND | | |
2318 | I915_SHRINK_PURGEABLE); | |
6c085a72 CW |
2319 | page = shmem_read_mapping_page_gfp(mapping, i, gfp); |
2320 | } | |
2321 | if (IS_ERR(page)) { | |
2322 | /* We've tried hard to allocate the memory by reaping | |
2323 | * our own buffer, now let the real VM do its job and | |
2324 | * go down in flames if truly OOM. | |
2325 | */ | |
f461d1be | 2326 | page = shmem_read_mapping_page(mapping, i); |
e2273302 ID |
2327 | if (IS_ERR(page)) { |
2328 | ret = PTR_ERR(page); | |
b17993b7 | 2329 | goto err_sg; |
e2273302 | 2330 | } |
6c085a72 | 2331 | } |
871dfbd6 CW |
2332 | if (!i || |
2333 | sg->length >= max_segment || | |
2334 | page_to_pfn(page) != last_pfn + 1) { | |
90797e6d ID |
2335 | if (i) |
2336 | sg = sg_next(sg); | |
2337 | st->nents++; | |
2338 | sg_set_page(sg, page, PAGE_SIZE, 0); | |
2339 | } else { | |
2340 | sg->length += PAGE_SIZE; | |
2341 | } | |
2342 | last_pfn = page_to_pfn(page); | |
3bbbe706 DV |
2343 | |
2344 | /* Check that the i965g/gm workaround works. */ | |
2345 | WARN_ON((gfp & __GFP_DMA32) && (last_pfn >= 0x00100000UL)); | |
e5281ccd | 2346 | } |
871dfbd6 | 2347 | if (sg) /* loop terminated early; short sg table */ |
426729dc | 2348 | sg_mark_end(sg); |
74ce6b6c | 2349 | |
0c40ce13 TU |
2350 | /* Trim unused sg entries to avoid wasting memory. */ |
2351 | i915_sg_trim(st); | |
2352 | ||
03ac84f1 | 2353 | ret = i915_gem_gtt_prepare_pages(obj, st); |
d766ef53 CW |
2354 | if (ret) { |
2355 | /* DMA remapping failed? One possible cause is that | |
2356 | * it could not reserve enough large entries, asking | |
2357 | * for PAGE_SIZE chunks instead may be helpful. | |
2358 | */ | |
2359 | if (max_segment > PAGE_SIZE) { | |
2360 | for_each_sgt_page(page, sgt_iter, st) | |
2361 | put_page(page); | |
2362 | sg_free_table(st); | |
2363 | ||
2364 | max_segment = PAGE_SIZE; | |
2365 | goto rebuild_st; | |
2366 | } else { | |
2367 | dev_warn(&dev_priv->drm.pdev->dev, | |
2368 | "Failed to DMA remap %lu pages\n", | |
2369 | page_count); | |
2370 | goto err_pages; | |
2371 | } | |
2372 | } | |
e2273302 | 2373 | |
6dacfd2f | 2374 | if (i915_gem_object_needs_bit17_swizzle(obj)) |
03ac84f1 | 2375 | i915_gem_object_do_bit_17_swizzle(obj, st); |
e5281ccd | 2376 | |
03ac84f1 | 2377 | return st; |
e5281ccd | 2378 | |
b17993b7 | 2379 | err_sg: |
90797e6d | 2380 | sg_mark_end(sg); |
b17993b7 | 2381 | err_pages: |
85d1225e DG |
2382 | for_each_sgt_page(page, sgt_iter, st) |
2383 | put_page(page); | |
9da3da66 CW |
2384 | sg_free_table(st); |
2385 | kfree(st); | |
0820baf3 CW |
2386 | |
2387 | /* shmemfs first checks if there is enough memory to allocate the page | |
2388 | * and reports ENOSPC should there be insufficient, along with the usual | |
2389 | * ENOMEM for a genuine allocation failure. | |
2390 | * | |
2391 | * We use ENOSPC in our driver to mean that we have run out of aperture | |
2392 | * space and so want to translate the error from shmemfs back to our | |
2393 | * usual understanding of ENOMEM. | |
2394 | */ | |
e2273302 ID |
2395 | if (ret == -ENOSPC) |
2396 | ret = -ENOMEM; | |
2397 | ||
03ac84f1 CW |
2398 | return ERR_PTR(ret); |
2399 | } | |
2400 | ||
2401 | void __i915_gem_object_set_pages(struct drm_i915_gem_object *obj, | |
2402 | struct sg_table *pages) | |
2403 | { | |
1233e2db | 2404 | lockdep_assert_held(&obj->mm.lock); |
03ac84f1 CW |
2405 | |
2406 | obj->mm.get_page.sg_pos = pages->sgl; | |
2407 | obj->mm.get_page.sg_idx = 0; | |
2408 | ||
2409 | obj->mm.pages = pages; | |
2c3a3f44 CW |
2410 | |
2411 | if (i915_gem_object_is_tiled(obj) && | |
2412 | to_i915(obj->base.dev)->quirks & QUIRK_PIN_SWIZZLED_PAGES) { | |
2413 | GEM_BUG_ON(obj->mm.quirked); | |
2414 | __i915_gem_object_pin_pages(obj); | |
2415 | obj->mm.quirked = true; | |
2416 | } | |
03ac84f1 CW |
2417 | } |
2418 | ||
2419 | static int ____i915_gem_object_get_pages(struct drm_i915_gem_object *obj) | |
2420 | { | |
2421 | struct sg_table *pages; | |
2422 | ||
2c3a3f44 CW |
2423 | GEM_BUG_ON(i915_gem_object_has_pinned_pages(obj)); |
2424 | ||
03ac84f1 CW |
2425 | if (unlikely(obj->mm.madv != I915_MADV_WILLNEED)) { |
2426 | DRM_DEBUG("Attempting to obtain a purgeable object\n"); | |
2427 | return -EFAULT; | |
2428 | } | |
2429 | ||
2430 | pages = obj->ops->get_pages(obj); | |
2431 | if (unlikely(IS_ERR(pages))) | |
2432 | return PTR_ERR(pages); | |
2433 | ||
2434 | __i915_gem_object_set_pages(obj, pages); | |
2435 | return 0; | |
673a394b EA |
2436 | } |
2437 | ||
37e680a1 | 2438 | /* Ensure that the associated pages are gathered from the backing storage |
1233e2db | 2439 | * and pinned into our object. i915_gem_object_pin_pages() may be called |
37e680a1 | 2440 | * multiple times before they are released by a single call to |
1233e2db | 2441 | * i915_gem_object_unpin_pages() - once the pages are no longer referenced |
37e680a1 CW |
2442 | * either as a result of memory pressure (reaping pages under the shrinker) |
2443 | * or as the object is itself released. | |
2444 | */ | |
a4f5ea64 | 2445 | int __i915_gem_object_get_pages(struct drm_i915_gem_object *obj) |
37e680a1 | 2446 | { |
03ac84f1 | 2447 | int err; |
37e680a1 | 2448 | |
1233e2db CW |
2449 | err = mutex_lock_interruptible(&obj->mm.lock); |
2450 | if (err) | |
2451 | return err; | |
4c7d62c6 | 2452 | |
2c3a3f44 CW |
2453 | if (unlikely(!obj->mm.pages)) { |
2454 | err = ____i915_gem_object_get_pages(obj); | |
2455 | if (err) | |
2456 | goto unlock; | |
37e680a1 | 2457 | |
2c3a3f44 CW |
2458 | smp_mb__before_atomic(); |
2459 | } | |
2460 | atomic_inc(&obj->mm.pages_pin_count); | |
ee286370 | 2461 | |
1233e2db CW |
2462 | unlock: |
2463 | mutex_unlock(&obj->mm.lock); | |
03ac84f1 | 2464 | return err; |
673a394b EA |
2465 | } |
2466 | ||
dd6034c6 | 2467 | /* The 'mapping' part of i915_gem_object_pin_map() below */ |
d31d7cb1 CW |
2468 | static void *i915_gem_object_map(const struct drm_i915_gem_object *obj, |
2469 | enum i915_map_type type) | |
dd6034c6 DG |
2470 | { |
2471 | unsigned long n_pages = obj->base.size >> PAGE_SHIFT; | |
a4f5ea64 | 2472 | struct sg_table *sgt = obj->mm.pages; |
85d1225e DG |
2473 | struct sgt_iter sgt_iter; |
2474 | struct page *page; | |
b338fa47 DG |
2475 | struct page *stack_pages[32]; |
2476 | struct page **pages = stack_pages; | |
dd6034c6 | 2477 | unsigned long i = 0; |
d31d7cb1 | 2478 | pgprot_t pgprot; |
dd6034c6 DG |
2479 | void *addr; |
2480 | ||
2481 | /* A single page can always be kmapped */ | |
d31d7cb1 | 2482 | if (n_pages == 1 && type == I915_MAP_WB) |
dd6034c6 DG |
2483 | return kmap(sg_page(sgt->sgl)); |
2484 | ||
b338fa47 DG |
2485 | if (n_pages > ARRAY_SIZE(stack_pages)) { |
2486 | /* Too big for stack -- allocate temporary array instead */ | |
2487 | pages = drm_malloc_gfp(n_pages, sizeof(*pages), GFP_TEMPORARY); | |
2488 | if (!pages) | |
2489 | return NULL; | |
2490 | } | |
dd6034c6 | 2491 | |
85d1225e DG |
2492 | for_each_sgt_page(page, sgt_iter, sgt) |
2493 | pages[i++] = page; | |
dd6034c6 DG |
2494 | |
2495 | /* Check that we have the expected number of pages */ | |
2496 | GEM_BUG_ON(i != n_pages); | |
2497 | ||
d31d7cb1 CW |
2498 | switch (type) { |
2499 | case I915_MAP_WB: | |
2500 | pgprot = PAGE_KERNEL; | |
2501 | break; | |
2502 | case I915_MAP_WC: | |
2503 | pgprot = pgprot_writecombine(PAGE_KERNEL_IO); | |
2504 | break; | |
2505 | } | |
2506 | addr = vmap(pages, n_pages, 0, pgprot); | |
dd6034c6 | 2507 | |
b338fa47 DG |
2508 | if (pages != stack_pages) |
2509 | drm_free_large(pages); | |
dd6034c6 DG |
2510 | |
2511 | return addr; | |
2512 | } | |
2513 | ||
2514 | /* get, pin, and map the pages of the object into kernel space */ | |
d31d7cb1 CW |
2515 | void *i915_gem_object_pin_map(struct drm_i915_gem_object *obj, |
2516 | enum i915_map_type type) | |
0a798eb9 | 2517 | { |
d31d7cb1 CW |
2518 | enum i915_map_type has_type; |
2519 | bool pinned; | |
2520 | void *ptr; | |
0a798eb9 CW |
2521 | int ret; |
2522 | ||
d31d7cb1 | 2523 | GEM_BUG_ON(!i915_gem_object_has_struct_page(obj)); |
0a798eb9 | 2524 | |
1233e2db | 2525 | ret = mutex_lock_interruptible(&obj->mm.lock); |
0a798eb9 CW |
2526 | if (ret) |
2527 | return ERR_PTR(ret); | |
2528 | ||
1233e2db CW |
2529 | pinned = true; |
2530 | if (!atomic_inc_not_zero(&obj->mm.pages_pin_count)) { | |
2c3a3f44 CW |
2531 | if (unlikely(!obj->mm.pages)) { |
2532 | ret = ____i915_gem_object_get_pages(obj); | |
2533 | if (ret) | |
2534 | goto err_unlock; | |
1233e2db | 2535 | |
2c3a3f44 CW |
2536 | smp_mb__before_atomic(); |
2537 | } | |
2538 | atomic_inc(&obj->mm.pages_pin_count); | |
1233e2db CW |
2539 | pinned = false; |
2540 | } | |
2541 | GEM_BUG_ON(!obj->mm.pages); | |
0a798eb9 | 2542 | |
a4f5ea64 | 2543 | ptr = ptr_unpack_bits(obj->mm.mapping, has_type); |
d31d7cb1 CW |
2544 | if (ptr && has_type != type) { |
2545 | if (pinned) { | |
2546 | ret = -EBUSY; | |
1233e2db | 2547 | goto err_unpin; |
0a798eb9 | 2548 | } |
d31d7cb1 CW |
2549 | |
2550 | if (is_vmalloc_addr(ptr)) | |
2551 | vunmap(ptr); | |
2552 | else | |
2553 | kunmap(kmap_to_page(ptr)); | |
2554 | ||
a4f5ea64 | 2555 | ptr = obj->mm.mapping = NULL; |
0a798eb9 CW |
2556 | } |
2557 | ||
d31d7cb1 CW |
2558 | if (!ptr) { |
2559 | ptr = i915_gem_object_map(obj, type); | |
2560 | if (!ptr) { | |
2561 | ret = -ENOMEM; | |
1233e2db | 2562 | goto err_unpin; |
d31d7cb1 CW |
2563 | } |
2564 | ||
a4f5ea64 | 2565 | obj->mm.mapping = ptr_pack_bits(ptr, type); |
d31d7cb1 CW |
2566 | } |
2567 | ||
1233e2db CW |
2568 | out_unlock: |
2569 | mutex_unlock(&obj->mm.lock); | |
d31d7cb1 CW |
2570 | return ptr; |
2571 | ||
1233e2db CW |
2572 | err_unpin: |
2573 | atomic_dec(&obj->mm.pages_pin_count); | |
2574 | err_unlock: | |
2575 | ptr = ERR_PTR(ret); | |
2576 | goto out_unlock; | |
0a798eb9 CW |
2577 | } |
2578 | ||
6095868a | 2579 | static bool ban_context(const struct i915_gem_context *ctx) |
be62acb4 | 2580 | { |
6095868a CW |
2581 | return (i915_gem_context_is_bannable(ctx) && |
2582 | ctx->ban_score >= CONTEXT_SCORE_BAN_THRESHOLD); | |
be62acb4 MK |
2583 | } |
2584 | ||
e5e1fc47 | 2585 | static void i915_gem_context_mark_guilty(struct i915_gem_context *ctx) |
aa60c664 | 2586 | { |
bc1d53c6 | 2587 | ctx->guilty_count++; |
6095868a CW |
2588 | ctx->ban_score += CONTEXT_SCORE_GUILTY; |
2589 | if (ban_context(ctx)) | |
2590 | i915_gem_context_set_banned(ctx); | |
b083a087 MK |
2591 | |
2592 | DRM_DEBUG_DRIVER("context %s marked guilty (score %d) banned? %s\n", | |
bc1d53c6 | 2593 | ctx->name, ctx->ban_score, |
6095868a | 2594 | yesno(i915_gem_context_is_banned(ctx))); |
b083a087 | 2595 | |
6095868a | 2596 | if (!i915_gem_context_is_banned(ctx) || IS_ERR_OR_NULL(ctx->file_priv)) |
b083a087 MK |
2597 | return; |
2598 | ||
d9e9da64 CW |
2599 | ctx->file_priv->context_bans++; |
2600 | DRM_DEBUG_DRIVER("client %s has had %d context banned\n", | |
2601 | ctx->name, ctx->file_priv->context_bans); | |
e5e1fc47 MK |
2602 | } |
2603 | ||
2604 | static void i915_gem_context_mark_innocent(struct i915_gem_context *ctx) | |
2605 | { | |
bc1d53c6 | 2606 | ctx->active_count++; |
aa60c664 MK |
2607 | } |
2608 | ||
8d9fc7fd | 2609 | struct drm_i915_gem_request * |
0bc40be8 | 2610 | i915_gem_find_active_request(struct intel_engine_cs *engine) |
9375e446 | 2611 | { |
4db080f9 CW |
2612 | struct drm_i915_gem_request *request; |
2613 | ||
f69a02c9 CW |
2614 | /* We are called by the error capture and reset at a random |
2615 | * point in time. In particular, note that neither is crucially | |
2616 | * ordered with an interrupt. After a hang, the GPU is dead and we | |
2617 | * assume that no more writes can happen (we waited long enough for | |
2618 | * all writes that were in transaction to be flushed) - adding an | |
2619 | * extra delay for a recent interrupt is pointless. Hence, we do | |
2620 | * not need an engine->irq_seqno_barrier() before the seqno reads. | |
2621 | */ | |
73cb9701 | 2622 | list_for_each_entry(request, &engine->timeline->requests, link) { |
80b204bc | 2623 | if (__i915_gem_request_completed(request)) |
4db080f9 | 2624 | continue; |
aa60c664 | 2625 | |
36193acd | 2626 | GEM_BUG_ON(request->engine != engine); |
c00122f3 CW |
2627 | GEM_BUG_ON(test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, |
2628 | &request->fence.flags)); | |
b6b0fac0 | 2629 | return request; |
4db080f9 | 2630 | } |
b6b0fac0 MK |
2631 | |
2632 | return NULL; | |
2633 | } | |
2634 | ||
bf2f0436 MK |
2635 | static bool engine_stalled(struct intel_engine_cs *engine) |
2636 | { | |
2637 | if (!engine->hangcheck.stalled) | |
2638 | return false; | |
2639 | ||
2640 | /* Check for possible seqno movement after hang declaration */ | |
2641 | if (engine->hangcheck.seqno != intel_engine_get_seqno(engine)) { | |
2642 | DRM_DEBUG_DRIVER("%s pardoned\n", engine->name); | |
2643 | return false; | |
2644 | } | |
2645 | ||
2646 | return true; | |
2647 | } | |
2648 | ||
0e178aef | 2649 | int i915_gem_reset_prepare(struct drm_i915_private *dev_priv) |
4c965543 CW |
2650 | { |
2651 | struct intel_engine_cs *engine; | |
2652 | enum intel_engine_id id; | |
0e178aef | 2653 | int err = 0; |
4c965543 CW |
2654 | |
2655 | /* Ensure irq handler finishes, and not run again. */ | |
0e178aef CW |
2656 | for_each_engine(engine, dev_priv, id) { |
2657 | struct drm_i915_gem_request *request; | |
2658 | ||
fe3288b5 CW |
2659 | /* Prevent the signaler thread from updating the request |
2660 | * state (by calling dma_fence_signal) as we are processing | |
2661 | * the reset. The write from the GPU of the seqno is | |
2662 | * asynchronous and the signaler thread may see a different | |
2663 | * value to us and declare the request complete, even though | |
2664 | * the reset routine have picked that request as the active | |
2665 | * (incomplete) request. This conflict is not handled | |
2666 | * gracefully! | |
2667 | */ | |
2668 | kthread_park(engine->breadcrumbs.signaler); | |
2669 | ||
1f7b847d CW |
2670 | /* Prevent request submission to the hardware until we have |
2671 | * completed the reset in i915_gem_reset_finish(). If a request | |
2672 | * is completed by one engine, it may then queue a request | |
2673 | * to a second via its engine->irq_tasklet *just* as we are | |
2674 | * calling engine->init_hw() and also writing the ELSP. | |
2675 | * Turning off the engine->irq_tasklet until the reset is over | |
2676 | * prevents the race. | |
2677 | */ | |
4c965543 | 2678 | tasklet_kill(&engine->irq_tasklet); |
1d309634 | 2679 | tasklet_disable(&engine->irq_tasklet); |
4c965543 | 2680 | |
8c12d121 CW |
2681 | if (engine->irq_seqno_barrier) |
2682 | engine->irq_seqno_barrier(engine); | |
2683 | ||
0e178aef CW |
2684 | if (engine_stalled(engine)) { |
2685 | request = i915_gem_find_active_request(engine); | |
2686 | if (request && request->fence.error == -EIO) | |
2687 | err = -EIO; /* Previous reset failed! */ | |
2688 | } | |
2689 | } | |
2690 | ||
4c965543 | 2691 | i915_gem_revoke_fences(dev_priv); |
0e178aef CW |
2692 | |
2693 | return err; | |
4c965543 CW |
2694 | } |
2695 | ||
36193acd | 2696 | static void skip_request(struct drm_i915_gem_request *request) |
821ed7df CW |
2697 | { |
2698 | void *vaddr = request->ring->vaddr; | |
2699 | u32 head; | |
2700 | ||
2701 | /* As this request likely depends on state from the lost | |
2702 | * context, clear out all the user operations leaving the | |
2703 | * breadcrumb at the end (so we get the fence notifications). | |
2704 | */ | |
2705 | head = request->head; | |
2706 | if (request->postfix < head) { | |
2707 | memset(vaddr + head, 0, request->ring->size - head); | |
2708 | head = 0; | |
2709 | } | |
2710 | memset(vaddr + head, 0, request->postfix - head); | |
c0d5f32c CW |
2711 | |
2712 | dma_fence_set_error(&request->fence, -EIO); | |
821ed7df CW |
2713 | } |
2714 | ||
36193acd MK |
2715 | static void engine_skip_context(struct drm_i915_gem_request *request) |
2716 | { | |
2717 | struct intel_engine_cs *engine = request->engine; | |
2718 | struct i915_gem_context *hung_ctx = request->ctx; | |
2719 | struct intel_timeline *timeline; | |
2720 | unsigned long flags; | |
2721 | ||
2722 | timeline = i915_gem_context_lookup_timeline(hung_ctx, engine); | |
2723 | ||
2724 | spin_lock_irqsave(&engine->timeline->lock, flags); | |
2725 | spin_lock(&timeline->lock); | |
2726 | ||
2727 | list_for_each_entry_continue(request, &engine->timeline->requests, link) | |
2728 | if (request->ctx == hung_ctx) | |
2729 | skip_request(request); | |
2730 | ||
2731 | list_for_each_entry(request, &timeline->requests, link) | |
2732 | skip_request(request); | |
2733 | ||
2734 | spin_unlock(&timeline->lock); | |
2735 | spin_unlock_irqrestore(&engine->timeline->lock, flags); | |
2736 | } | |
2737 | ||
61da5362 MK |
2738 | /* Returns true if the request was guilty of hang */ |
2739 | static bool i915_gem_reset_request(struct drm_i915_gem_request *request) | |
2740 | { | |
2741 | /* Read once and return the resolution */ | |
2742 | const bool guilty = engine_stalled(request->engine); | |
2743 | ||
71895a08 MK |
2744 | /* The guilty request will get skipped on a hung engine. |
2745 | * | |
2746 | * Users of client default contexts do not rely on logical | |
2747 | * state preserved between batches so it is safe to execute | |
2748 | * queued requests following the hang. Non default contexts | |
2749 | * rely on preserved state, so skipping a batch loses the | |
2750 | * evolution of the state and it needs to be considered corrupted. | |
2751 | * Executing more queued batches on top of corrupted state is | |
2752 | * risky. But we take the risk by trying to advance through | |
2753 | * the queued requests in order to make the client behaviour | |
2754 | * more predictable around resets, by not throwing away random | |
2755 | * amount of batches it has prepared for execution. Sophisticated | |
2756 | * clients can use gem_reset_stats_ioctl and dma fence status | |
2757 | * (exported via sync_file info ioctl on explicit fences) to observe | |
2758 | * when it loses the context state and should rebuild accordingly. | |
2759 | * | |
2760 | * The context ban, and ultimately the client ban, mechanism are safety | |
2761 | * valves if client submission ends up resulting in nothing more than | |
2762 | * subsequent hangs. | |
2763 | */ | |
2764 | ||
61da5362 MK |
2765 | if (guilty) { |
2766 | i915_gem_context_mark_guilty(request->ctx); | |
2767 | skip_request(request); | |
2768 | } else { | |
2769 | i915_gem_context_mark_innocent(request->ctx); | |
2770 | dma_fence_set_error(&request->fence, -EAGAIN); | |
2771 | } | |
2772 | ||
2773 | return guilty; | |
2774 | } | |
2775 | ||
821ed7df | 2776 | static void i915_gem_reset_engine(struct intel_engine_cs *engine) |
b6b0fac0 MK |
2777 | { |
2778 | struct drm_i915_gem_request *request; | |
b6b0fac0 | 2779 | |
0bc40be8 | 2780 | request = i915_gem_find_active_request(engine); |
c0dcb203 CW |
2781 | if (request && i915_gem_reset_request(request)) { |
2782 | DRM_DEBUG_DRIVER("resetting %s to restart from tail of request 0x%x\n", | |
2783 | engine->name, request->global_seqno); | |
821ed7df | 2784 | |
c0dcb203 CW |
2785 | /* If this context is now banned, skip all pending requests. */ |
2786 | if (i915_gem_context_is_banned(request->ctx)) | |
2787 | engine_skip_context(request); | |
2788 | } | |
821ed7df CW |
2789 | |
2790 | /* Setup the CS to resume from the breadcrumb of the hung request */ | |
2791 | engine->reset_hw(engine, request); | |
4db080f9 | 2792 | } |
aa60c664 | 2793 | |
d8027093 | 2794 | void i915_gem_reset(struct drm_i915_private *dev_priv) |
4db080f9 | 2795 | { |
821ed7df | 2796 | struct intel_engine_cs *engine; |
3b3f1650 | 2797 | enum intel_engine_id id; |
608c1a52 | 2798 | |
4c7d62c6 CW |
2799 | lockdep_assert_held(&dev_priv->drm.struct_mutex); |
2800 | ||
821ed7df CW |
2801 | i915_gem_retire_requests(dev_priv); |
2802 | ||
2ae55738 CW |
2803 | for_each_engine(engine, dev_priv, id) { |
2804 | struct i915_gem_context *ctx; | |
2805 | ||
821ed7df | 2806 | i915_gem_reset_engine(engine); |
2ae55738 CW |
2807 | ctx = fetch_and_zero(&engine->last_retired_context); |
2808 | if (ctx) | |
2809 | engine->context_unpin(engine, ctx); | |
2810 | } | |
821ed7df | 2811 | |
4362f4f6 | 2812 | i915_gem_restore_fences(dev_priv); |
f2a91d1a CW |
2813 | |
2814 | if (dev_priv->gt.awake) { | |
2815 | intel_sanitize_gt_powersave(dev_priv); | |
2816 | intel_enable_gt_powersave(dev_priv); | |
2817 | if (INTEL_GEN(dev_priv) >= 6) | |
2818 | gen6_rps_busy(dev_priv); | |
2819 | } | |
821ed7df CW |
2820 | } |
2821 | ||
d8027093 CW |
2822 | void i915_gem_reset_finish(struct drm_i915_private *dev_priv) |
2823 | { | |
1f7b847d CW |
2824 | struct intel_engine_cs *engine; |
2825 | enum intel_engine_id id; | |
2826 | ||
d8027093 | 2827 | lockdep_assert_held(&dev_priv->drm.struct_mutex); |
1f7b847d | 2828 | |
fe3288b5 | 2829 | for_each_engine(engine, dev_priv, id) { |
1f7b847d | 2830 | tasklet_enable(&engine->irq_tasklet); |
fe3288b5 CW |
2831 | kthread_unpark(engine->breadcrumbs.signaler); |
2832 | } | |
d8027093 CW |
2833 | } |
2834 | ||
821ed7df CW |
2835 | static void nop_submit_request(struct drm_i915_gem_request *request) |
2836 | { | |
3cd9442f | 2837 | dma_fence_set_error(&request->fence, -EIO); |
3dcf93f7 CW |
2838 | i915_gem_request_submit(request); |
2839 | intel_engine_init_global_seqno(request->engine, request->global_seqno); | |
821ed7df CW |
2840 | } |
2841 | ||
2a20d6f8 | 2842 | static void engine_set_wedged(struct intel_engine_cs *engine) |
821ed7df | 2843 | { |
3cd9442f CW |
2844 | struct drm_i915_gem_request *request; |
2845 | unsigned long flags; | |
2846 | ||
20e4933c CW |
2847 | /* We need to be sure that no thread is running the old callback as |
2848 | * we install the nop handler (otherwise we would submit a request | |
2849 | * to hardware that will never complete). In order to prevent this | |
2850 | * race, we wait until the machine is idle before making the swap | |
2851 | * (using stop_machine()). | |
2852 | */ | |
821ed7df | 2853 | engine->submit_request = nop_submit_request; |
70c2a24d | 2854 | |
3cd9442f CW |
2855 | /* Mark all executing requests as skipped */ |
2856 | spin_lock_irqsave(&engine->timeline->lock, flags); | |
2857 | list_for_each_entry(request, &engine->timeline->requests, link) | |
2858 | dma_fence_set_error(&request->fence, -EIO); | |
2859 | spin_unlock_irqrestore(&engine->timeline->lock, flags); | |
2860 | ||
c4b0930b CW |
2861 | /* Mark all pending requests as complete so that any concurrent |
2862 | * (lockless) lookup doesn't try and wait upon the request as we | |
2863 | * reset it. | |
2864 | */ | |
73cb9701 | 2865 | intel_engine_init_global_seqno(engine, |
cb399eab | 2866 | intel_engine_last_submit(engine)); |
c4b0930b | 2867 | |
dcb4c12a OM |
2868 | /* |
2869 | * Clear the execlists queue up before freeing the requests, as those | |
2870 | * are the ones that keep the context and ringbuffer backing objects | |
2871 | * pinned in place. | |
2872 | */ | |
dcb4c12a | 2873 | |
7de1691a | 2874 | if (i915.enable_execlists) { |
663f71e7 CW |
2875 | unsigned long flags; |
2876 | ||
2877 | spin_lock_irqsave(&engine->timeline->lock, flags); | |
2878 | ||
70c2a24d CW |
2879 | i915_gem_request_put(engine->execlist_port[0].request); |
2880 | i915_gem_request_put(engine->execlist_port[1].request); | |
2881 | memset(engine->execlist_port, 0, sizeof(engine->execlist_port)); | |
20311bd3 CW |
2882 | engine->execlist_queue = RB_ROOT; |
2883 | engine->execlist_first = NULL; | |
663f71e7 CW |
2884 | |
2885 | spin_unlock_irqrestore(&engine->timeline->lock, flags); | |
dcb4c12a | 2886 | } |
673a394b EA |
2887 | } |
2888 | ||
20e4933c | 2889 | static int __i915_gem_set_wedged_BKL(void *data) |
673a394b | 2890 | { |
20e4933c | 2891 | struct drm_i915_private *i915 = data; |
e2f80391 | 2892 | struct intel_engine_cs *engine; |
3b3f1650 | 2893 | enum intel_engine_id id; |
673a394b | 2894 | |
20e4933c | 2895 | for_each_engine(engine, i915, id) |
2a20d6f8 | 2896 | engine_set_wedged(engine); |
20e4933c CW |
2897 | |
2898 | return 0; | |
2899 | } | |
2900 | ||
2901 | void i915_gem_set_wedged(struct drm_i915_private *dev_priv) | |
2902 | { | |
821ed7df CW |
2903 | lockdep_assert_held(&dev_priv->drm.struct_mutex); |
2904 | set_bit(I915_WEDGED, &dev_priv->gpu_error.flags); | |
4db080f9 | 2905 | |
20e4933c | 2906 | stop_machine(__i915_gem_set_wedged_BKL, dev_priv, NULL); |
dfaae392 | 2907 | |
20e4933c | 2908 | i915_gem_context_lost(dev_priv); |
821ed7df | 2909 | i915_gem_retire_requests(dev_priv); |
20e4933c CW |
2910 | |
2911 | mod_delayed_work(dev_priv->wq, &dev_priv->gt.idle_work, 0); | |
673a394b EA |
2912 | } |
2913 | ||
75ef9da2 | 2914 | static void |
673a394b EA |
2915 | i915_gem_retire_work_handler(struct work_struct *work) |
2916 | { | |
b29c19b6 | 2917 | struct drm_i915_private *dev_priv = |
67d97da3 | 2918 | container_of(work, typeof(*dev_priv), gt.retire_work.work); |
91c8a326 | 2919 | struct drm_device *dev = &dev_priv->drm; |
673a394b | 2920 | |
891b48cf | 2921 | /* Come back later if the device is busy... */ |
b29c19b6 | 2922 | if (mutex_trylock(&dev->struct_mutex)) { |
67d97da3 | 2923 | i915_gem_retire_requests(dev_priv); |
b29c19b6 | 2924 | mutex_unlock(&dev->struct_mutex); |
673a394b | 2925 | } |
67d97da3 CW |
2926 | |
2927 | /* Keep the retire handler running until we are finally idle. | |
2928 | * We do not need to do this test under locking as in the worst-case | |
2929 | * we queue the retire worker once too often. | |
2930 | */ | |
c9615613 CW |
2931 | if (READ_ONCE(dev_priv->gt.awake)) { |
2932 | i915_queue_hangcheck(dev_priv); | |
67d97da3 CW |
2933 | queue_delayed_work(dev_priv->wq, |
2934 | &dev_priv->gt.retire_work, | |
bcb45086 | 2935 | round_jiffies_up_relative(HZ)); |
c9615613 | 2936 | } |
b29c19b6 | 2937 | } |
0a58705b | 2938 | |
b29c19b6 CW |
2939 | static void |
2940 | i915_gem_idle_work_handler(struct work_struct *work) | |
2941 | { | |
2942 | struct drm_i915_private *dev_priv = | |
67d97da3 | 2943 | container_of(work, typeof(*dev_priv), gt.idle_work.work); |
91c8a326 | 2944 | struct drm_device *dev = &dev_priv->drm; |
b4ac5afc | 2945 | struct intel_engine_cs *engine; |
3b3f1650 | 2946 | enum intel_engine_id id; |
67d97da3 CW |
2947 | bool rearm_hangcheck; |
2948 | ||
2949 | if (!READ_ONCE(dev_priv->gt.awake)) | |
2950 | return; | |
2951 | ||
0cb5670b ID |
2952 | /* |
2953 | * Wait for last execlists context complete, but bail out in case a | |
2954 | * new request is submitted. | |
2955 | */ | |
2956 | wait_for(READ_ONCE(dev_priv->gt.active_requests) || | |
2957 | intel_execlists_idle(dev_priv), 10); | |
2958 | ||
28176ef4 | 2959 | if (READ_ONCE(dev_priv->gt.active_requests)) |
67d97da3 CW |
2960 | return; |
2961 | ||
2962 | rearm_hangcheck = | |
2963 | cancel_delayed_work_sync(&dev_priv->gpu_error.hangcheck_work); | |
2964 | ||
2965 | if (!mutex_trylock(&dev->struct_mutex)) { | |
2966 | /* Currently busy, come back later */ | |
2967 | mod_delayed_work(dev_priv->wq, | |
2968 | &dev_priv->gt.idle_work, | |
2969 | msecs_to_jiffies(50)); | |
2970 | goto out_rearm; | |
2971 | } | |
2972 | ||
93c97dc1 ID |
2973 | /* |
2974 | * New request retired after this work handler started, extend active | |
2975 | * period until next instance of the work. | |
2976 | */ | |
2977 | if (work_pending(work)) | |
2978 | goto out_unlock; | |
2979 | ||
28176ef4 | 2980 | if (dev_priv->gt.active_requests) |
67d97da3 | 2981 | goto out_unlock; |
b29c19b6 | 2982 | |
0cb5670b ID |
2983 | if (wait_for(intel_execlists_idle(dev_priv), 10)) |
2984 | DRM_ERROR("Timeout waiting for engines to idle\n"); | |
2985 | ||
3b3f1650 | 2986 | for_each_engine(engine, dev_priv, id) |
67d97da3 | 2987 | i915_gem_batch_pool_fini(&engine->batch_pool); |
35c94185 | 2988 | |
67d97da3 CW |
2989 | GEM_BUG_ON(!dev_priv->gt.awake); |
2990 | dev_priv->gt.awake = false; | |
2991 | rearm_hangcheck = false; | |
30ecad77 | 2992 | |
67d97da3 CW |
2993 | if (INTEL_GEN(dev_priv) >= 6) |
2994 | gen6_rps_idle(dev_priv); | |
2995 | intel_runtime_pm_put(dev_priv); | |
2996 | out_unlock: | |
2997 | mutex_unlock(&dev->struct_mutex); | |
b29c19b6 | 2998 | |
67d97da3 CW |
2999 | out_rearm: |
3000 | if (rearm_hangcheck) { | |
3001 | GEM_BUG_ON(!dev_priv->gt.awake); | |
3002 | i915_queue_hangcheck(dev_priv); | |
35c94185 | 3003 | } |
673a394b EA |
3004 | } |
3005 | ||
b1f788c6 CW |
3006 | void i915_gem_close_object(struct drm_gem_object *gem, struct drm_file *file) |
3007 | { | |
3008 | struct drm_i915_gem_object *obj = to_intel_bo(gem); | |
3009 | struct drm_i915_file_private *fpriv = file->driver_priv; | |
3010 | struct i915_vma *vma, *vn; | |
3011 | ||
3012 | mutex_lock(&obj->base.dev->struct_mutex); | |
3013 | list_for_each_entry_safe(vma, vn, &obj->vma_list, obj_link) | |
3014 | if (vma->vm->file == fpriv) | |
3015 | i915_vma_close(vma); | |
f8a7fde4 CW |
3016 | |
3017 | if (i915_gem_object_is_active(obj) && | |
3018 | !i915_gem_object_has_active_reference(obj)) { | |
3019 | i915_gem_object_set_active_reference(obj); | |
3020 | i915_gem_object_get(obj); | |
3021 | } | |
b1f788c6 CW |
3022 | mutex_unlock(&obj->base.dev->struct_mutex); |
3023 | } | |
3024 | ||
e95433c7 CW |
3025 | static unsigned long to_wait_timeout(s64 timeout_ns) |
3026 | { | |
3027 | if (timeout_ns < 0) | |
3028 | return MAX_SCHEDULE_TIMEOUT; | |
3029 | ||
3030 | if (timeout_ns == 0) | |
3031 | return 0; | |
3032 | ||
3033 | return nsecs_to_jiffies_timeout(timeout_ns); | |
3034 | } | |
3035 | ||
23ba4fd0 BW |
3036 | /** |
3037 | * i915_gem_wait_ioctl - implements DRM_IOCTL_I915_GEM_WAIT | |
14bb2c11 TU |
3038 | * @dev: drm device pointer |
3039 | * @data: ioctl data blob | |
3040 | * @file: drm file pointer | |
23ba4fd0 BW |
3041 | * |
3042 | * Returns 0 if successful, else an error is returned with the remaining time in | |
3043 | * the timeout parameter. | |
3044 | * -ETIME: object is still busy after timeout | |
3045 | * -ERESTARTSYS: signal interrupted the wait | |
3046 | * -ENONENT: object doesn't exist | |
3047 | * Also possible, but rare: | |
3048 | * -EAGAIN: GPU wedged | |
3049 | * -ENOMEM: damn | |
3050 | * -ENODEV: Internal IRQ fail | |
3051 | * -E?: The add request failed | |
3052 | * | |
3053 | * The wait ioctl with a timeout of 0 reimplements the busy ioctl. With any | |
3054 | * non-zero timeout parameter the wait ioctl will wait for the given number of | |
3055 | * nanoseconds on an object becoming unbusy. Since the wait itself does so | |
3056 | * without holding struct_mutex the object may become re-busied before this | |
3057 | * function completes. A similar but shorter * race condition exists in the busy | |
3058 | * ioctl | |
3059 | */ | |
3060 | int | |
3061 | i915_gem_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *file) | |
3062 | { | |
3063 | struct drm_i915_gem_wait *args = data; | |
3064 | struct drm_i915_gem_object *obj; | |
e95433c7 CW |
3065 | ktime_t start; |
3066 | long ret; | |
23ba4fd0 | 3067 | |
11b5d511 DV |
3068 | if (args->flags != 0) |
3069 | return -EINVAL; | |
3070 | ||
03ac0642 | 3071 | obj = i915_gem_object_lookup(file, args->bo_handle); |
033d549b | 3072 | if (!obj) |
23ba4fd0 | 3073 | return -ENOENT; |
23ba4fd0 | 3074 | |
e95433c7 CW |
3075 | start = ktime_get(); |
3076 | ||
3077 | ret = i915_gem_object_wait(obj, | |
3078 | I915_WAIT_INTERRUPTIBLE | I915_WAIT_ALL, | |
3079 | to_wait_timeout(args->timeout_ns), | |
3080 | to_rps_client(file)); | |
3081 | ||
3082 | if (args->timeout_ns > 0) { | |
3083 | args->timeout_ns -= ktime_to_ns(ktime_sub(ktime_get(), start)); | |
3084 | if (args->timeout_ns < 0) | |
3085 | args->timeout_ns = 0; | |
c1d2061b CW |
3086 | |
3087 | /* | |
3088 | * Apparently ktime isn't accurate enough and occasionally has a | |
3089 | * bit of mismatch in the jiffies<->nsecs<->ktime loop. So patch | |
3090 | * things up to make the test happy. We allow up to 1 jiffy. | |
3091 | * | |
3092 | * This is a regression from the timespec->ktime conversion. | |
3093 | */ | |
3094 | if (ret == -ETIME && !nsecs_to_jiffies(args->timeout_ns)) | |
3095 | args->timeout_ns = 0; | |
b4716185 CW |
3096 | } |
3097 | ||
f0cd5182 | 3098 | i915_gem_object_put(obj); |
ff865885 | 3099 | return ret; |
23ba4fd0 BW |
3100 | } |
3101 | ||
73cb9701 | 3102 | static int wait_for_timeline(struct i915_gem_timeline *tl, unsigned int flags) |
4df2faf4 | 3103 | { |
73cb9701 | 3104 | int ret, i; |
4df2faf4 | 3105 | |
73cb9701 CW |
3106 | for (i = 0; i < ARRAY_SIZE(tl->engine); i++) { |
3107 | ret = i915_gem_active_wait(&tl->engine[i].last_request, flags); | |
3108 | if (ret) | |
3109 | return ret; | |
3110 | } | |
62e63007 | 3111 | |
73cb9701 CW |
3112 | return 0; |
3113 | } | |
3114 | ||
3115 | int i915_gem_wait_for_idle(struct drm_i915_private *i915, unsigned int flags) | |
3116 | { | |
73cb9701 CW |
3117 | int ret; |
3118 | ||
9caa34aa CW |
3119 | if (flags & I915_WAIT_LOCKED) { |
3120 | struct i915_gem_timeline *tl; | |
3121 | ||
3122 | lockdep_assert_held(&i915->drm.struct_mutex); | |
3123 | ||
3124 | list_for_each_entry(tl, &i915->gt.timelines, link) { | |
3125 | ret = wait_for_timeline(tl, flags); | |
3126 | if (ret) | |
3127 | return ret; | |
3128 | } | |
3129 | } else { | |
3130 | ret = wait_for_timeline(&i915->gt.global_timeline, flags); | |
1ec14ad3 CW |
3131 | if (ret) |
3132 | return ret; | |
3133 | } | |
4df2faf4 | 3134 | |
8a1a49f9 | 3135 | return 0; |
4df2faf4 DV |
3136 | } |
3137 | ||
d0da48cf CW |
3138 | void i915_gem_clflush_object(struct drm_i915_gem_object *obj, |
3139 | bool force) | |
673a394b | 3140 | { |
673a394b EA |
3141 | /* If we don't have a page list set up, then we're not pinned |
3142 | * to GPU, and we can ignore the cache flush because it'll happen | |
3143 | * again at bind time. | |
3144 | */ | |
a4f5ea64 | 3145 | if (!obj->mm.pages) |
d0da48cf | 3146 | return; |
673a394b | 3147 | |
769ce464 ID |
3148 | /* |
3149 | * Stolen memory is always coherent with the GPU as it is explicitly | |
3150 | * marked as wc by the system, or the system is cache-coherent. | |
3151 | */ | |
6a2c4232 | 3152 | if (obj->stolen || obj->phys_handle) |
d0da48cf | 3153 | return; |
769ce464 | 3154 | |
9c23f7fc CW |
3155 | /* If the GPU is snooping the contents of the CPU cache, |
3156 | * we do not need to manually clear the CPU cache lines. However, | |
3157 | * the caches are only snooped when the render cache is | |
3158 | * flushed/invalidated. As we always have to emit invalidations | |
3159 | * and flushes when moving into and out of the RENDER domain, correct | |
3160 | * snooping behaviour occurs naturally as the result of our domain | |
3161 | * tracking. | |
3162 | */ | |
0f71979a CW |
3163 | if (!force && cpu_cache_is_coherent(obj->base.dev, obj->cache_level)) { |
3164 | obj->cache_dirty = true; | |
d0da48cf | 3165 | return; |
0f71979a | 3166 | } |
9c23f7fc | 3167 | |
1c5d22f7 | 3168 | trace_i915_gem_object_clflush(obj); |
a4f5ea64 | 3169 | drm_clflush_sg(obj->mm.pages); |
0f71979a | 3170 | obj->cache_dirty = false; |
e47c68e9 EA |
3171 | } |
3172 | ||
3173 | /** Flushes the GTT write domain for the object if it's dirty. */ | |
3174 | static void | |
05394f39 | 3175 | i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj) |
e47c68e9 | 3176 | { |
3b5724d7 | 3177 | struct drm_i915_private *dev_priv = to_i915(obj->base.dev); |
1c5d22f7 | 3178 | |
05394f39 | 3179 | if (obj->base.write_domain != I915_GEM_DOMAIN_GTT) |
e47c68e9 EA |
3180 | return; |
3181 | ||
63256ec5 | 3182 | /* No actual flushing is required for the GTT write domain. Writes |
3b5724d7 | 3183 | * to it "immediately" go to main memory as far as we know, so there's |
e47c68e9 | 3184 | * no chipset flush. It also doesn't land in render cache. |
63256ec5 CW |
3185 | * |
3186 | * However, we do have to enforce the order so that all writes through | |
3187 | * the GTT land before any writes to the device, such as updates to | |
3188 | * the GATT itself. | |
3b5724d7 CW |
3189 | * |
3190 | * We also have to wait a bit for the writes to land from the GTT. | |
3191 | * An uncached read (i.e. mmio) seems to be ideal for the round-trip | |
3192 | * timing. This issue has only been observed when switching quickly | |
3193 | * between GTT writes and CPU reads from inside the kernel on recent hw, | |
3194 | * and it appears to only affect discrete GTT blocks (i.e. on LLC | |
3195 | * system agents we cannot reproduce this behaviour). | |
e47c68e9 | 3196 | */ |
63256ec5 | 3197 | wmb(); |
3b5724d7 | 3198 | if (INTEL_GEN(dev_priv) >= 6 && !HAS_LLC(dev_priv)) |
3b3f1650 | 3199 | POSTING_READ(RING_ACTHD(dev_priv->engine[RCS]->mmio_base)); |
63256ec5 | 3200 | |
d243ad82 | 3201 | intel_fb_obj_flush(obj, false, write_origin(obj, I915_GEM_DOMAIN_GTT)); |
f99d7069 | 3202 | |
b0dc465f | 3203 | obj->base.write_domain = 0; |
1c5d22f7 | 3204 | trace_i915_gem_object_change_domain(obj, |
05394f39 | 3205 | obj->base.read_domains, |
b0dc465f | 3206 | I915_GEM_DOMAIN_GTT); |
e47c68e9 EA |
3207 | } |
3208 | ||
3209 | /** Flushes the CPU write domain for the object if it's dirty. */ | |
3210 | static void | |
e62b59e4 | 3211 | i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj) |
e47c68e9 | 3212 | { |
05394f39 | 3213 | if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) |
e47c68e9 EA |
3214 | return; |
3215 | ||
d0da48cf | 3216 | i915_gem_clflush_object(obj, obj->pin_display); |
de152b62 | 3217 | intel_fb_obj_flush(obj, false, ORIGIN_CPU); |
f99d7069 | 3218 | |
b0dc465f | 3219 | obj->base.write_domain = 0; |
1c5d22f7 | 3220 | trace_i915_gem_object_change_domain(obj, |
05394f39 | 3221 | obj->base.read_domains, |
b0dc465f | 3222 | I915_GEM_DOMAIN_CPU); |
e47c68e9 EA |
3223 | } |
3224 | ||
2ef7eeaa EA |
3225 | /** |
3226 | * Moves a single object to the GTT read, and possibly write domain. | |
14bb2c11 TU |
3227 | * @obj: object to act on |
3228 | * @write: ask for write access or read only | |
2ef7eeaa EA |
3229 | * |
3230 | * This function returns when the move is complete, including waiting on | |
3231 | * flushes to occur. | |
3232 | */ | |
79e53945 | 3233 | int |
2021746e | 3234 | i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write) |
2ef7eeaa | 3235 | { |
1c5d22f7 | 3236 | uint32_t old_write_domain, old_read_domains; |
e47c68e9 | 3237 | int ret; |
2ef7eeaa | 3238 | |
e95433c7 | 3239 | lockdep_assert_held(&obj->base.dev->struct_mutex); |
4c7d62c6 | 3240 | |
e95433c7 CW |
3241 | ret = i915_gem_object_wait(obj, |
3242 | I915_WAIT_INTERRUPTIBLE | | |
3243 | I915_WAIT_LOCKED | | |
3244 | (write ? I915_WAIT_ALL : 0), | |
3245 | MAX_SCHEDULE_TIMEOUT, | |
3246 | NULL); | |
88241785 CW |
3247 | if (ret) |
3248 | return ret; | |
3249 | ||
c13d87ea CW |
3250 | if (obj->base.write_domain == I915_GEM_DOMAIN_GTT) |
3251 | return 0; | |
3252 | ||
43566ded CW |
3253 | /* Flush and acquire obj->pages so that we are coherent through |
3254 | * direct access in memory with previous cached writes through | |
3255 | * shmemfs and that our cache domain tracking remains valid. | |
3256 | * For example, if the obj->filp was moved to swap without us | |
3257 | * being notified and releasing the pages, we would mistakenly | |
3258 | * continue to assume that the obj remained out of the CPU cached | |
3259 | * domain. | |
3260 | */ | |
a4f5ea64 | 3261 | ret = i915_gem_object_pin_pages(obj); |
43566ded CW |
3262 | if (ret) |
3263 | return ret; | |
3264 | ||
e62b59e4 | 3265 | i915_gem_object_flush_cpu_write_domain(obj); |
1c5d22f7 | 3266 | |
d0a57789 CW |
3267 | /* Serialise direct access to this object with the barriers for |
3268 | * coherent writes from the GPU, by effectively invalidating the | |
3269 | * GTT domain upon first access. | |
3270 | */ | |
3271 | if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0) | |
3272 | mb(); | |
3273 | ||
05394f39 CW |
3274 | old_write_domain = obj->base.write_domain; |
3275 | old_read_domains = obj->base.read_domains; | |
1c5d22f7 | 3276 | |
e47c68e9 EA |
3277 | /* It should now be out of any other write domains, and we can update |
3278 | * the domain values for our changes. | |
3279 | */ | |
40e62d5d | 3280 | GEM_BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) != 0); |
05394f39 | 3281 | obj->base.read_domains |= I915_GEM_DOMAIN_GTT; |
e47c68e9 | 3282 | if (write) { |
05394f39 CW |
3283 | obj->base.read_domains = I915_GEM_DOMAIN_GTT; |
3284 | obj->base.write_domain = I915_GEM_DOMAIN_GTT; | |
a4f5ea64 | 3285 | obj->mm.dirty = true; |
2ef7eeaa EA |
3286 | } |
3287 | ||
1c5d22f7 CW |
3288 | trace_i915_gem_object_change_domain(obj, |
3289 | old_read_domains, | |
3290 | old_write_domain); | |
3291 | ||
a4f5ea64 | 3292 | i915_gem_object_unpin_pages(obj); |
e47c68e9 EA |
3293 | return 0; |
3294 | } | |
3295 | ||
ef55f92a CW |
3296 | /** |
3297 | * Changes the cache-level of an object across all VMA. | |
14bb2c11 TU |
3298 | * @obj: object to act on |
3299 | * @cache_level: new cache level to set for the object | |
ef55f92a CW |
3300 | * |
3301 | * After this function returns, the object will be in the new cache-level | |
3302 | * across all GTT and the contents of the backing storage will be coherent, | |
3303 | * with respect to the new cache-level. In order to keep the backing storage | |
3304 | * coherent for all users, we only allow a single cache level to be set | |
3305 | * globally on the object and prevent it from being changed whilst the | |
3306 | * hardware is reading from the object. That is if the object is currently | |
3307 | * on the scanout it will be set to uncached (or equivalent display | |
3308 | * cache coherency) and all non-MOCS GPU access will also be uncached so | |
3309 | * that all direct access to the scanout remains coherent. | |
3310 | */ | |
e4ffd173 CW |
3311 | int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj, |
3312 | enum i915_cache_level cache_level) | |
3313 | { | |
aa653a68 | 3314 | struct i915_vma *vma; |
a6a7cc4b | 3315 | int ret; |
e4ffd173 | 3316 | |
4c7d62c6 CW |
3317 | lockdep_assert_held(&obj->base.dev->struct_mutex); |
3318 | ||
e4ffd173 | 3319 | if (obj->cache_level == cache_level) |
a6a7cc4b | 3320 | return 0; |
e4ffd173 | 3321 | |
ef55f92a CW |
3322 | /* Inspect the list of currently bound VMA and unbind any that would |
3323 | * be invalid given the new cache-level. This is principally to | |
3324 | * catch the issue of the CS prefetch crossing page boundaries and | |
3325 | * reading an invalid PTE on older architectures. | |
3326 | */ | |
aa653a68 CW |
3327 | restart: |
3328 | list_for_each_entry(vma, &obj->vma_list, obj_link) { | |
ef55f92a CW |
3329 | if (!drm_mm_node_allocated(&vma->node)) |
3330 | continue; | |
3331 | ||
20dfbde4 | 3332 | if (i915_vma_is_pinned(vma)) { |
ef55f92a CW |
3333 | DRM_DEBUG("can not change the cache level of pinned objects\n"); |
3334 | return -EBUSY; | |
3335 | } | |
3336 | ||
aa653a68 CW |
3337 | if (i915_gem_valid_gtt_space(vma, cache_level)) |
3338 | continue; | |
3339 | ||
3340 | ret = i915_vma_unbind(vma); | |
3341 | if (ret) | |
3342 | return ret; | |
3343 | ||
3344 | /* As unbinding may affect other elements in the | |
3345 | * obj->vma_list (due to side-effects from retiring | |
3346 | * an active vma), play safe and restart the iterator. | |
3347 | */ | |
3348 | goto restart; | |
42d6ab48 CW |
3349 | } |
3350 | ||
ef55f92a CW |
3351 | /* We can reuse the existing drm_mm nodes but need to change the |
3352 | * cache-level on the PTE. We could simply unbind them all and | |
3353 | * rebind with the correct cache-level on next use. However since | |
3354 | * we already have a valid slot, dma mapping, pages etc, we may as | |
3355 | * rewrite the PTE in the belief that doing so tramples upon less | |
3356 | * state and so involves less work. | |
3357 | */ | |
15717de2 | 3358 | if (obj->bind_count) { |
ef55f92a CW |
3359 | /* Before we change the PTE, the GPU must not be accessing it. |
3360 | * If we wait upon the object, we know that all the bound | |
3361 | * VMA are no longer active. | |
3362 | */ | |
e95433c7 CW |
3363 | ret = i915_gem_object_wait(obj, |
3364 | I915_WAIT_INTERRUPTIBLE | | |
3365 | I915_WAIT_LOCKED | | |
3366 | I915_WAIT_ALL, | |
3367 | MAX_SCHEDULE_TIMEOUT, | |
3368 | NULL); | |
e4ffd173 CW |
3369 | if (ret) |
3370 | return ret; | |
3371 | ||
0031fb96 TU |
3372 | if (!HAS_LLC(to_i915(obj->base.dev)) && |
3373 | cache_level != I915_CACHE_NONE) { | |
ef55f92a CW |
3374 | /* Access to snoopable pages through the GTT is |
3375 | * incoherent and on some machines causes a hard | |
3376 | * lockup. Relinquish the CPU mmaping to force | |
3377 | * userspace to refault in the pages and we can | |
3378 | * then double check if the GTT mapping is still | |
3379 | * valid for that pointer access. | |
3380 | */ | |
3381 | i915_gem_release_mmap(obj); | |
3382 | ||
3383 | /* As we no longer need a fence for GTT access, | |
3384 | * we can relinquish it now (and so prevent having | |
3385 | * to steal a fence from someone else on the next | |
3386 | * fence request). Note GPU activity would have | |
3387 | * dropped the fence as all snoopable access is | |
3388 | * supposed to be linear. | |
3389 | */ | |
49ef5294 CW |
3390 | list_for_each_entry(vma, &obj->vma_list, obj_link) { |
3391 | ret = i915_vma_put_fence(vma); | |
3392 | if (ret) | |
3393 | return ret; | |
3394 | } | |
ef55f92a CW |
3395 | } else { |
3396 | /* We either have incoherent backing store and | |
3397 | * so no GTT access or the architecture is fully | |
3398 | * coherent. In such cases, existing GTT mmaps | |
3399 | * ignore the cache bit in the PTE and we can | |
3400 | * rewrite it without confusing the GPU or having | |
3401 | * to force userspace to fault back in its mmaps. | |
3402 | */ | |
e4ffd173 CW |
3403 | } |
3404 | ||
1c7f4bca | 3405 | list_for_each_entry(vma, &obj->vma_list, obj_link) { |
ef55f92a CW |
3406 | if (!drm_mm_node_allocated(&vma->node)) |
3407 | continue; | |
3408 | ||
3409 | ret = i915_vma_bind(vma, cache_level, PIN_UPDATE); | |
3410 | if (ret) | |
3411 | return ret; | |
3412 | } | |
e4ffd173 CW |
3413 | } |
3414 | ||
a6a7cc4b CW |
3415 | if (obj->base.write_domain == I915_GEM_DOMAIN_CPU && |
3416 | cpu_cache_is_coherent(obj->base.dev, obj->cache_level)) | |
3417 | obj->cache_dirty = true; | |
3418 | ||
1c7f4bca | 3419 | list_for_each_entry(vma, &obj->vma_list, obj_link) |
2c22569b CW |
3420 | vma->node.color = cache_level; |
3421 | obj->cache_level = cache_level; | |
3422 | ||
e4ffd173 CW |
3423 | return 0; |
3424 | } | |
3425 | ||
199adf40 BW |
3426 | int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data, |
3427 | struct drm_file *file) | |
e6994aee | 3428 | { |
199adf40 | 3429 | struct drm_i915_gem_caching *args = data; |
e6994aee | 3430 | struct drm_i915_gem_object *obj; |
fbbd37b3 | 3431 | int err = 0; |
e6994aee | 3432 | |
fbbd37b3 CW |
3433 | rcu_read_lock(); |
3434 | obj = i915_gem_object_lookup_rcu(file, args->handle); | |
3435 | if (!obj) { | |
3436 | err = -ENOENT; | |
3437 | goto out; | |
3438 | } | |
e6994aee | 3439 | |
651d794f CW |
3440 | switch (obj->cache_level) { |
3441 | case I915_CACHE_LLC: | |
3442 | case I915_CACHE_L3_LLC: | |
3443 | args->caching = I915_CACHING_CACHED; | |
3444 | break; | |
3445 | ||
4257d3ba CW |
3446 | case I915_CACHE_WT: |
3447 | args->caching = I915_CACHING_DISPLAY; | |
3448 | break; | |
3449 | ||
651d794f CW |
3450 | default: |
3451 | args->caching = I915_CACHING_NONE; | |
3452 | break; | |
3453 | } | |
fbbd37b3 CW |
3454 | out: |
3455 | rcu_read_unlock(); | |
3456 | return err; | |
e6994aee CW |
3457 | } |
3458 | ||
199adf40 BW |
3459 | int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data, |
3460 | struct drm_file *file) | |
e6994aee | 3461 | { |
9c870d03 | 3462 | struct drm_i915_private *i915 = to_i915(dev); |
199adf40 | 3463 | struct drm_i915_gem_caching *args = data; |
e6994aee CW |
3464 | struct drm_i915_gem_object *obj; |
3465 | enum i915_cache_level level; | |
d65415df | 3466 | int ret = 0; |
e6994aee | 3467 | |
199adf40 BW |
3468 | switch (args->caching) { |
3469 | case I915_CACHING_NONE: | |
e6994aee CW |
3470 | level = I915_CACHE_NONE; |
3471 | break; | |
199adf40 | 3472 | case I915_CACHING_CACHED: |
e5756c10 ID |
3473 | /* |
3474 | * Due to a HW issue on BXT A stepping, GPU stores via a | |
3475 | * snooped mapping may leave stale data in a corresponding CPU | |
3476 | * cacheline, whereas normally such cachelines would get | |
3477 | * invalidated. | |
3478 | */ | |
9c870d03 | 3479 | if (!HAS_LLC(i915) && !HAS_SNOOP(i915)) |
e5756c10 ID |
3480 | return -ENODEV; |
3481 | ||
e6994aee CW |
3482 | level = I915_CACHE_LLC; |
3483 | break; | |
4257d3ba | 3484 | case I915_CACHING_DISPLAY: |
9c870d03 | 3485 | level = HAS_WT(i915) ? I915_CACHE_WT : I915_CACHE_NONE; |
4257d3ba | 3486 | break; |
e6994aee CW |
3487 | default: |
3488 | return -EINVAL; | |
3489 | } | |
3490 | ||
d65415df CW |
3491 | obj = i915_gem_object_lookup(file, args->handle); |
3492 | if (!obj) | |
3493 | return -ENOENT; | |
3494 | ||
3495 | if (obj->cache_level == level) | |
3496 | goto out; | |
3497 | ||
3498 | ret = i915_gem_object_wait(obj, | |
3499 | I915_WAIT_INTERRUPTIBLE, | |
3500 | MAX_SCHEDULE_TIMEOUT, | |
3501 | to_rps_client(file)); | |
3bc2913e | 3502 | if (ret) |
d65415df | 3503 | goto out; |
3bc2913e | 3504 | |
d65415df CW |
3505 | ret = i915_mutex_lock_interruptible(dev); |
3506 | if (ret) | |
3507 | goto out; | |
e6994aee CW |
3508 | |
3509 | ret = i915_gem_object_set_cache_level(obj, level); | |
e6994aee | 3510 | mutex_unlock(&dev->struct_mutex); |
d65415df CW |
3511 | |
3512 | out: | |
3513 | i915_gem_object_put(obj); | |
e6994aee CW |
3514 | return ret; |
3515 | } | |
3516 | ||
b9241ea3 | 3517 | /* |
2da3b9b9 CW |
3518 | * Prepare buffer for display plane (scanout, cursors, etc). |
3519 | * Can be called from an uninterruptible phase (modesetting) and allows | |
3520 | * any flushes to be pipelined (for pageflips). | |
b9241ea3 | 3521 | */ |
058d88c4 | 3522 | struct i915_vma * |
2da3b9b9 CW |
3523 | i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj, |
3524 | u32 alignment, | |
e6617330 | 3525 | const struct i915_ggtt_view *view) |
b9241ea3 | 3526 | { |
058d88c4 | 3527 | struct i915_vma *vma; |
2da3b9b9 | 3528 | u32 old_read_domains, old_write_domain; |
b9241ea3 ZW |
3529 | int ret; |
3530 | ||
4c7d62c6 CW |
3531 | lockdep_assert_held(&obj->base.dev->struct_mutex); |
3532 | ||
cc98b413 CW |
3533 | /* Mark the pin_display early so that we account for the |
3534 | * display coherency whilst setting up the cache domains. | |
3535 | */ | |
8a0c39b1 | 3536 | obj->pin_display++; |
cc98b413 | 3537 | |
a7ef0640 EA |
3538 | /* The display engine is not coherent with the LLC cache on gen6. As |
3539 | * a result, we make sure that the pinning that is about to occur is | |
3540 | * done with uncached PTEs. This is lowest common denominator for all | |
3541 | * chipsets. | |
3542 | * | |
3543 | * However for gen6+, we could do better by using the GFDT bit instead | |
3544 | * of uncaching, which would allow us to flush all the LLC-cached data | |
3545 | * with that bit in the PTE to main memory with just one PIPE_CONTROL. | |
3546 | */ | |
651d794f | 3547 | ret = i915_gem_object_set_cache_level(obj, |
8652744b TU |
3548 | HAS_WT(to_i915(obj->base.dev)) ? |
3549 | I915_CACHE_WT : I915_CACHE_NONE); | |
058d88c4 CW |
3550 | if (ret) { |
3551 | vma = ERR_PTR(ret); | |
cc98b413 | 3552 | goto err_unpin_display; |
058d88c4 | 3553 | } |
a7ef0640 | 3554 | |
2da3b9b9 CW |
3555 | /* As the user may map the buffer once pinned in the display plane |
3556 | * (e.g. libkms for the bootup splash), we have to ensure that we | |
2efb813d CW |
3557 | * always use map_and_fenceable for all scanout buffers. However, |
3558 | * it may simply be too big to fit into mappable, in which case | |
3559 | * put it anyway and hope that userspace can cope (but always first | |
3560 | * try to preserve the existing ABI). | |
2da3b9b9 | 3561 | */ |
2efb813d | 3562 | vma = ERR_PTR(-ENOSPC); |
47a8e3f6 | 3563 | if (!view || view->type == I915_GGTT_VIEW_NORMAL) |
2efb813d CW |
3564 | vma = i915_gem_object_ggtt_pin(obj, view, 0, alignment, |
3565 | PIN_MAPPABLE | PIN_NONBLOCK); | |
767a222e CW |
3566 | if (IS_ERR(vma)) { |
3567 | struct drm_i915_private *i915 = to_i915(obj->base.dev); | |
3568 | unsigned int flags; | |
3569 | ||
3570 | /* Valleyview is definitely limited to scanning out the first | |
3571 | * 512MiB. Lets presume this behaviour was inherited from the | |
3572 | * g4x display engine and that all earlier gen are similarly | |
3573 | * limited. Testing suggests that it is a little more | |
3574 | * complicated than this. For example, Cherryview appears quite | |
3575 | * happy to scanout from anywhere within its global aperture. | |
3576 | */ | |
3577 | flags = 0; | |
3578 | if (HAS_GMCH_DISPLAY(i915)) | |
3579 | flags = PIN_MAPPABLE; | |
3580 | vma = i915_gem_object_ggtt_pin(obj, view, 0, alignment, flags); | |
3581 | } | |
058d88c4 | 3582 | if (IS_ERR(vma)) |
cc98b413 | 3583 | goto err_unpin_display; |
2da3b9b9 | 3584 | |
d8923dcf CW |
3585 | vma->display_alignment = max_t(u64, vma->display_alignment, alignment); |
3586 | ||
a6a7cc4b | 3587 | /* Treat this as an end-of-frame, like intel_user_framebuffer_dirty() */ |
69aeafea | 3588 | if (obj->cache_dirty || obj->base.write_domain == I915_GEM_DOMAIN_CPU) { |
a6a7cc4b CW |
3589 | i915_gem_clflush_object(obj, true); |
3590 | intel_fb_obj_flush(obj, false, ORIGIN_DIRTYFB); | |
3591 | } | |
b118c1e3 | 3592 | |
2da3b9b9 | 3593 | old_write_domain = obj->base.write_domain; |
05394f39 | 3594 | old_read_domains = obj->base.read_domains; |
2da3b9b9 CW |
3595 | |
3596 | /* It should now be out of any other write domains, and we can update | |
3597 | * the domain values for our changes. | |
3598 | */ | |
e5f1d962 | 3599 | obj->base.write_domain = 0; |
05394f39 | 3600 | obj->base.read_domains |= I915_GEM_DOMAIN_GTT; |
b9241ea3 ZW |
3601 | |
3602 | trace_i915_gem_object_change_domain(obj, | |
3603 | old_read_domains, | |
2da3b9b9 | 3604 | old_write_domain); |
b9241ea3 | 3605 | |
058d88c4 | 3606 | return vma; |
cc98b413 CW |
3607 | |
3608 | err_unpin_display: | |
8a0c39b1 | 3609 | obj->pin_display--; |
058d88c4 | 3610 | return vma; |
cc98b413 CW |
3611 | } |
3612 | ||
3613 | void | |
058d88c4 | 3614 | i915_gem_object_unpin_from_display_plane(struct i915_vma *vma) |
cc98b413 | 3615 | { |
49d73912 | 3616 | lockdep_assert_held(&vma->vm->i915->drm.struct_mutex); |
4c7d62c6 | 3617 | |
058d88c4 | 3618 | if (WARN_ON(vma->obj->pin_display == 0)) |
8a0c39b1 TU |
3619 | return; |
3620 | ||
d8923dcf | 3621 | if (--vma->obj->pin_display == 0) |
f51455d4 | 3622 | vma->display_alignment = I915_GTT_MIN_ALIGNMENT; |
e6617330 | 3623 | |
383d5823 | 3624 | /* Bump the LRU to try and avoid premature eviction whilst flipping */ |
befedbb7 | 3625 | i915_gem_object_bump_inactive_ggtt(vma->obj); |
383d5823 | 3626 | |
058d88c4 | 3627 | i915_vma_unpin(vma); |
b9241ea3 ZW |
3628 | } |
3629 | ||
e47c68e9 EA |
3630 | /** |
3631 | * Moves a single object to the CPU read, and possibly write domain. | |
14bb2c11 TU |
3632 | * @obj: object to act on |
3633 | * @write: requesting write or read-only access | |
e47c68e9 EA |
3634 | * |
3635 | * This function returns when the move is complete, including waiting on | |
3636 | * flushes to occur. | |
3637 | */ | |
dabdfe02 | 3638 | int |
919926ae | 3639 | i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write) |
e47c68e9 | 3640 | { |
1c5d22f7 | 3641 | uint32_t old_write_domain, old_read_domains; |
e47c68e9 EA |
3642 | int ret; |
3643 | ||
e95433c7 | 3644 | lockdep_assert_held(&obj->base.dev->struct_mutex); |
4c7d62c6 | 3645 | |
e95433c7 CW |
3646 | ret = i915_gem_object_wait(obj, |
3647 | I915_WAIT_INTERRUPTIBLE | | |
3648 | I915_WAIT_LOCKED | | |
3649 | (write ? I915_WAIT_ALL : 0), | |
3650 | MAX_SCHEDULE_TIMEOUT, | |
3651 | NULL); | |
88241785 CW |
3652 | if (ret) |
3653 | return ret; | |
3654 | ||
c13d87ea CW |
3655 | if (obj->base.write_domain == I915_GEM_DOMAIN_CPU) |
3656 | return 0; | |
3657 | ||
e47c68e9 | 3658 | i915_gem_object_flush_gtt_write_domain(obj); |
2ef7eeaa | 3659 | |
05394f39 CW |
3660 | old_write_domain = obj->base.write_domain; |
3661 | old_read_domains = obj->base.read_domains; | |
1c5d22f7 | 3662 | |
e47c68e9 | 3663 | /* Flush the CPU cache if it's still invalid. */ |
05394f39 | 3664 | if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) { |
2c22569b | 3665 | i915_gem_clflush_object(obj, false); |
2ef7eeaa | 3666 | |
05394f39 | 3667 | obj->base.read_domains |= I915_GEM_DOMAIN_CPU; |
2ef7eeaa EA |
3668 | } |
3669 | ||
3670 | /* It should now be out of any other write domains, and we can update | |
3671 | * the domain values for our changes. | |
3672 | */ | |
40e62d5d | 3673 | GEM_BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) != 0); |
e47c68e9 EA |
3674 | |
3675 | /* If we're writing through the CPU, then the GPU read domains will | |
3676 | * need to be invalidated at next use. | |
3677 | */ | |
3678 | if (write) { | |
05394f39 CW |
3679 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; |
3680 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; | |
e47c68e9 | 3681 | } |
2ef7eeaa | 3682 | |
1c5d22f7 CW |
3683 | trace_i915_gem_object_change_domain(obj, |
3684 | old_read_domains, | |
3685 | old_write_domain); | |
3686 | ||
2ef7eeaa EA |
3687 | return 0; |
3688 | } | |
3689 | ||
673a394b EA |
3690 | /* Throttle our rendering by waiting until the ring has completed our requests |
3691 | * emitted over 20 msec ago. | |
3692 | * | |
b962442e EA |
3693 | * Note that if we were to use the current jiffies each time around the loop, |
3694 | * we wouldn't escape the function with any frames outstanding if the time to | |
3695 | * render a frame was over 20ms. | |
3696 | * | |
673a394b EA |
3697 | * This should get us reasonable parallelism between CPU and GPU but also |
3698 | * relatively low latency when blocking on a particular request to finish. | |
3699 | */ | |
40a5f0de | 3700 | static int |
f787a5f5 | 3701 | i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file) |
40a5f0de | 3702 | { |
fac5e23e | 3703 | struct drm_i915_private *dev_priv = to_i915(dev); |
f787a5f5 | 3704 | struct drm_i915_file_private *file_priv = file->driver_priv; |
d0bc54f2 | 3705 | unsigned long recent_enough = jiffies - DRM_I915_THROTTLE_JIFFIES; |
54fb2411 | 3706 | struct drm_i915_gem_request *request, *target = NULL; |
e95433c7 | 3707 | long ret; |
93533c29 | 3708 | |
f4457ae7 CW |
3709 | /* ABI: return -EIO if already wedged */ |
3710 | if (i915_terminally_wedged(&dev_priv->gpu_error)) | |
3711 | return -EIO; | |
e110e8d6 | 3712 | |
1c25595f | 3713 | spin_lock(&file_priv->mm.lock); |
f787a5f5 | 3714 | list_for_each_entry(request, &file_priv->mm.request_list, client_list) { |
b962442e EA |
3715 | if (time_after_eq(request->emitted_jiffies, recent_enough)) |
3716 | break; | |
40a5f0de | 3717 | |
fcfa423c JH |
3718 | /* |
3719 | * Note that the request might not have been submitted yet. | |
3720 | * In which case emitted_jiffies will be zero. | |
3721 | */ | |
3722 | if (!request->emitted_jiffies) | |
3723 | continue; | |
3724 | ||
54fb2411 | 3725 | target = request; |
b962442e | 3726 | } |
ff865885 | 3727 | if (target) |
e8a261ea | 3728 | i915_gem_request_get(target); |
1c25595f | 3729 | spin_unlock(&file_priv->mm.lock); |
40a5f0de | 3730 | |
54fb2411 | 3731 | if (target == NULL) |
f787a5f5 | 3732 | return 0; |
2bc43b5c | 3733 | |
e95433c7 CW |
3734 | ret = i915_wait_request(target, |
3735 | I915_WAIT_INTERRUPTIBLE, | |
3736 | MAX_SCHEDULE_TIMEOUT); | |
e8a261ea | 3737 | i915_gem_request_put(target); |
ff865885 | 3738 | |
e95433c7 | 3739 | return ret < 0 ? ret : 0; |
40a5f0de EA |
3740 | } |
3741 | ||
058d88c4 | 3742 | struct i915_vma * |
ec7adb6e JL |
3743 | i915_gem_object_ggtt_pin(struct drm_i915_gem_object *obj, |
3744 | const struct i915_ggtt_view *view, | |
91b2db6f | 3745 | u64 size, |
2ffffd0f CW |
3746 | u64 alignment, |
3747 | u64 flags) | |
ec7adb6e | 3748 | { |
ad16d2ed CW |
3749 | struct drm_i915_private *dev_priv = to_i915(obj->base.dev); |
3750 | struct i915_address_space *vm = &dev_priv->ggtt.base; | |
59bfa124 CW |
3751 | struct i915_vma *vma; |
3752 | int ret; | |
72e96d64 | 3753 | |
4c7d62c6 CW |
3754 | lockdep_assert_held(&obj->base.dev->struct_mutex); |
3755 | ||
718659a6 | 3756 | vma = i915_vma_instance(obj, vm, view); |
e0216b76 | 3757 | if (unlikely(IS_ERR(vma))) |
058d88c4 | 3758 | return vma; |
59bfa124 CW |
3759 | |
3760 | if (i915_vma_misplaced(vma, size, alignment, flags)) { | |
3761 | if (flags & PIN_NONBLOCK && | |
3762 | (i915_vma_is_pinned(vma) || i915_vma_is_active(vma))) | |
058d88c4 | 3763 | return ERR_PTR(-ENOSPC); |
59bfa124 | 3764 | |
ad16d2ed | 3765 | if (flags & PIN_MAPPABLE) { |
ad16d2ed CW |
3766 | /* If the required space is larger than the available |
3767 | * aperture, we will not able to find a slot for the | |
3768 | * object and unbinding the object now will be in | |
3769 | * vain. Worse, doing so may cause us to ping-pong | |
3770 | * the object in and out of the Global GTT and | |
3771 | * waste a lot of cycles under the mutex. | |
3772 | */ | |
944397f0 | 3773 | if (vma->fence_size > dev_priv->ggtt.mappable_end) |
ad16d2ed CW |
3774 | return ERR_PTR(-E2BIG); |
3775 | ||
3776 | /* If NONBLOCK is set the caller is optimistically | |
3777 | * trying to cache the full object within the mappable | |
3778 | * aperture, and *must* have a fallback in place for | |
3779 | * situations where we cannot bind the object. We | |
3780 | * can be a little more lax here and use the fallback | |
3781 | * more often to avoid costly migrations of ourselves | |
3782 | * and other objects within the aperture. | |
3783 | * | |
3784 | * Half-the-aperture is used as a simple heuristic. | |
3785 | * More interesting would to do search for a free | |
3786 | * block prior to making the commitment to unbind. | |
3787 | * That caters for the self-harm case, and with a | |
3788 | * little more heuristics (e.g. NOFAULT, NOEVICT) | |
3789 | * we could try to minimise harm to others. | |
3790 | */ | |
3791 | if (flags & PIN_NONBLOCK && | |
944397f0 | 3792 | vma->fence_size > dev_priv->ggtt.mappable_end / 2) |
ad16d2ed CW |
3793 | return ERR_PTR(-ENOSPC); |
3794 | } | |
3795 | ||
59bfa124 CW |
3796 | WARN(i915_vma_is_pinned(vma), |
3797 | "bo is already pinned in ggtt with incorrect alignment:" | |
05a20d09 CW |
3798 | " offset=%08x, req.alignment=%llx," |
3799 | " req.map_and_fenceable=%d, vma->map_and_fenceable=%d\n", | |
3800 | i915_ggtt_offset(vma), alignment, | |
59bfa124 | 3801 | !!(flags & PIN_MAPPABLE), |
05a20d09 | 3802 | i915_vma_is_map_and_fenceable(vma)); |
59bfa124 CW |
3803 | ret = i915_vma_unbind(vma); |
3804 | if (ret) | |
058d88c4 | 3805 | return ERR_PTR(ret); |
59bfa124 CW |
3806 | } |
3807 | ||
058d88c4 CW |
3808 | ret = i915_vma_pin(vma, size, alignment, flags | PIN_GLOBAL); |
3809 | if (ret) | |
3810 | return ERR_PTR(ret); | |
ec7adb6e | 3811 | |
058d88c4 | 3812 | return vma; |
673a394b EA |
3813 | } |
3814 | ||
edf6b76f | 3815 | static __always_inline unsigned int __busy_read_flag(unsigned int id) |
3fdc13c7 CW |
3816 | { |
3817 | /* Note that we could alias engines in the execbuf API, but | |
3818 | * that would be very unwise as it prevents userspace from | |
3819 | * fine control over engine selection. Ahem. | |
3820 | * | |
3821 | * This should be something like EXEC_MAX_ENGINE instead of | |
3822 | * I915_NUM_ENGINES. | |
3823 | */ | |
3824 | BUILD_BUG_ON(I915_NUM_ENGINES > 16); | |
3825 | return 0x10000 << id; | |
3826 | } | |
3827 | ||
3828 | static __always_inline unsigned int __busy_write_id(unsigned int id) | |
3829 | { | |
70cb472c CW |
3830 | /* The uABI guarantees an active writer is also amongst the read |
3831 | * engines. This would be true if we accessed the activity tracking | |
3832 | * under the lock, but as we perform the lookup of the object and | |
3833 | * its activity locklessly we can not guarantee that the last_write | |
3834 | * being active implies that we have set the same engine flag from | |
3835 | * last_read - hence we always set both read and write busy for | |
3836 | * last_write. | |
3837 | */ | |
3838 | return id | __busy_read_flag(id); | |
3fdc13c7 CW |
3839 | } |
3840 | ||
edf6b76f | 3841 | static __always_inline unsigned int |
d07f0e59 | 3842 | __busy_set_if_active(const struct dma_fence *fence, |
3fdc13c7 CW |
3843 | unsigned int (*flag)(unsigned int id)) |
3844 | { | |
d07f0e59 | 3845 | struct drm_i915_gem_request *rq; |
3fdc13c7 | 3846 | |
d07f0e59 CW |
3847 | /* We have to check the current hw status of the fence as the uABI |
3848 | * guarantees forward progress. We could rely on the idle worker | |
3849 | * to eventually flush us, but to minimise latency just ask the | |
3850 | * hardware. | |
1255501d | 3851 | * |
d07f0e59 | 3852 | * Note we only report on the status of native fences. |
1255501d | 3853 | */ |
d07f0e59 CW |
3854 | if (!dma_fence_is_i915(fence)) |
3855 | return 0; | |
3856 | ||
3857 | /* opencode to_request() in order to avoid const warnings */ | |
3858 | rq = container_of(fence, struct drm_i915_gem_request, fence); | |
3859 | if (i915_gem_request_completed(rq)) | |
3860 | return 0; | |
3861 | ||
3862 | return flag(rq->engine->exec_id); | |
3fdc13c7 CW |
3863 | } |
3864 | ||
edf6b76f | 3865 | static __always_inline unsigned int |
d07f0e59 | 3866 | busy_check_reader(const struct dma_fence *fence) |
3fdc13c7 | 3867 | { |
d07f0e59 | 3868 | return __busy_set_if_active(fence, __busy_read_flag); |
3fdc13c7 CW |
3869 | } |
3870 | ||
edf6b76f | 3871 | static __always_inline unsigned int |
d07f0e59 | 3872 | busy_check_writer(const struct dma_fence *fence) |
3fdc13c7 | 3873 | { |
d07f0e59 CW |
3874 | if (!fence) |
3875 | return 0; | |
3876 | ||
3877 | return __busy_set_if_active(fence, __busy_write_id); | |
3fdc13c7 CW |
3878 | } |
3879 | ||
673a394b EA |
3880 | int |
3881 | i915_gem_busy_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 3882 | struct drm_file *file) |
673a394b EA |
3883 | { |
3884 | struct drm_i915_gem_busy *args = data; | |
05394f39 | 3885 | struct drm_i915_gem_object *obj; |
d07f0e59 CW |
3886 | struct reservation_object_list *list; |
3887 | unsigned int seq; | |
fbbd37b3 | 3888 | int err; |
673a394b | 3889 | |
d07f0e59 | 3890 | err = -ENOENT; |
fbbd37b3 CW |
3891 | rcu_read_lock(); |
3892 | obj = i915_gem_object_lookup_rcu(file, args->handle); | |
d07f0e59 | 3893 | if (!obj) |
fbbd37b3 | 3894 | goto out; |
d1b851fc | 3895 | |
d07f0e59 CW |
3896 | /* A discrepancy here is that we do not report the status of |
3897 | * non-i915 fences, i.e. even though we may report the object as idle, | |
3898 | * a call to set-domain may still stall waiting for foreign rendering. | |
3899 | * This also means that wait-ioctl may report an object as busy, | |
3900 | * where busy-ioctl considers it idle. | |
3901 | * | |
3902 | * We trade the ability to warn of foreign fences to report on which | |
3903 | * i915 engines are active for the object. | |
3904 | * | |
3905 | * Alternatively, we can trade that extra information on read/write | |
3906 | * activity with | |
3907 | * args->busy = | |
3908 | * !reservation_object_test_signaled_rcu(obj->resv, true); | |
3909 | * to report the overall busyness. This is what the wait-ioctl does. | |
3910 | * | |
3911 | */ | |
3912 | retry: | |
3913 | seq = raw_read_seqcount(&obj->resv->seq); | |
426960be | 3914 | |
d07f0e59 CW |
3915 | /* Translate the exclusive fence to the READ *and* WRITE engine */ |
3916 | args->busy = busy_check_writer(rcu_dereference(obj->resv->fence_excl)); | |
3fdc13c7 | 3917 | |
d07f0e59 CW |
3918 | /* Translate shared fences to READ set of engines */ |
3919 | list = rcu_dereference(obj->resv->fence); | |
3920 | if (list) { | |
3921 | unsigned int shared_count = list->shared_count, i; | |
3fdc13c7 | 3922 | |
d07f0e59 CW |
3923 | for (i = 0; i < shared_count; ++i) { |
3924 | struct dma_fence *fence = | |
3925 | rcu_dereference(list->shared[i]); | |
3926 | ||
3927 | args->busy |= busy_check_reader(fence); | |
3928 | } | |
426960be | 3929 | } |
673a394b | 3930 | |
d07f0e59 CW |
3931 | if (args->busy && read_seqcount_retry(&obj->resv->seq, seq)) |
3932 | goto retry; | |
3933 | ||
3934 | err = 0; | |
fbbd37b3 CW |
3935 | out: |
3936 | rcu_read_unlock(); | |
3937 | return err; | |
673a394b EA |
3938 | } |
3939 | ||
3940 | int | |
3941 | i915_gem_throttle_ioctl(struct drm_device *dev, void *data, | |
3942 | struct drm_file *file_priv) | |
3943 | { | |
0206e353 | 3944 | return i915_gem_ring_throttle(dev, file_priv); |
673a394b EA |
3945 | } |
3946 | ||
3ef94daa CW |
3947 | int |
3948 | i915_gem_madvise_ioctl(struct drm_device *dev, void *data, | |
3949 | struct drm_file *file_priv) | |
3950 | { | |
fac5e23e | 3951 | struct drm_i915_private *dev_priv = to_i915(dev); |
3ef94daa | 3952 | struct drm_i915_gem_madvise *args = data; |
05394f39 | 3953 | struct drm_i915_gem_object *obj; |
1233e2db | 3954 | int err; |
3ef94daa CW |
3955 | |
3956 | switch (args->madv) { | |
3957 | case I915_MADV_DONTNEED: | |
3958 | case I915_MADV_WILLNEED: | |
3959 | break; | |
3960 | default: | |
3961 | return -EINVAL; | |
3962 | } | |
3963 | ||
03ac0642 | 3964 | obj = i915_gem_object_lookup(file_priv, args->handle); |
1233e2db CW |
3965 | if (!obj) |
3966 | return -ENOENT; | |
3967 | ||
3968 | err = mutex_lock_interruptible(&obj->mm.lock); | |
3969 | if (err) | |
3970 | goto out; | |
3ef94daa | 3971 | |
a4f5ea64 | 3972 | if (obj->mm.pages && |
3e510a8e | 3973 | i915_gem_object_is_tiled(obj) && |
656bfa3a | 3974 | dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES) { |
bc0629a7 CW |
3975 | if (obj->mm.madv == I915_MADV_WILLNEED) { |
3976 | GEM_BUG_ON(!obj->mm.quirked); | |
a4f5ea64 | 3977 | __i915_gem_object_unpin_pages(obj); |
bc0629a7 CW |
3978 | obj->mm.quirked = false; |
3979 | } | |
3980 | if (args->madv == I915_MADV_WILLNEED) { | |
2c3a3f44 | 3981 | GEM_BUG_ON(obj->mm.quirked); |
a4f5ea64 | 3982 | __i915_gem_object_pin_pages(obj); |
bc0629a7 CW |
3983 | obj->mm.quirked = true; |
3984 | } | |
656bfa3a DV |
3985 | } |
3986 | ||
a4f5ea64 CW |
3987 | if (obj->mm.madv != __I915_MADV_PURGED) |
3988 | obj->mm.madv = args->madv; | |
3ef94daa | 3989 | |
6c085a72 | 3990 | /* if the object is no longer attached, discard its backing storage */ |
a4f5ea64 | 3991 | if (obj->mm.madv == I915_MADV_DONTNEED && !obj->mm.pages) |
2d7ef395 CW |
3992 | i915_gem_object_truncate(obj); |
3993 | ||
a4f5ea64 | 3994 | args->retained = obj->mm.madv != __I915_MADV_PURGED; |
1233e2db | 3995 | mutex_unlock(&obj->mm.lock); |
bb6baf76 | 3996 | |
1233e2db | 3997 | out: |
f8c417cd | 3998 | i915_gem_object_put(obj); |
1233e2db | 3999 | return err; |
3ef94daa CW |
4000 | } |
4001 | ||
5b8c8aec CW |
4002 | static void |
4003 | frontbuffer_retire(struct i915_gem_active *active, | |
4004 | struct drm_i915_gem_request *request) | |
4005 | { | |
4006 | struct drm_i915_gem_object *obj = | |
4007 | container_of(active, typeof(*obj), frontbuffer_write); | |
4008 | ||
4009 | intel_fb_obj_flush(obj, true, ORIGIN_CS); | |
4010 | } | |
4011 | ||
37e680a1 CW |
4012 | void i915_gem_object_init(struct drm_i915_gem_object *obj, |
4013 | const struct drm_i915_gem_object_ops *ops) | |
0327d6ba | 4014 | { |
1233e2db CW |
4015 | mutex_init(&obj->mm.lock); |
4016 | ||
56cea323 | 4017 | INIT_LIST_HEAD(&obj->global_link); |
275f039d | 4018 | INIT_LIST_HEAD(&obj->userfault_link); |
b25cb2f8 | 4019 | INIT_LIST_HEAD(&obj->obj_exec_link); |
2f633156 | 4020 | INIT_LIST_HEAD(&obj->vma_list); |
8d9d5744 | 4021 | INIT_LIST_HEAD(&obj->batch_pool_link); |
0327d6ba | 4022 | |
37e680a1 CW |
4023 | obj->ops = ops; |
4024 | ||
d07f0e59 CW |
4025 | reservation_object_init(&obj->__builtin_resv); |
4026 | obj->resv = &obj->__builtin_resv; | |
4027 | ||
50349247 | 4028 | obj->frontbuffer_ggtt_origin = ORIGIN_GTT; |
5b8c8aec | 4029 | init_request_active(&obj->frontbuffer_write, frontbuffer_retire); |
a4f5ea64 CW |
4030 | |
4031 | obj->mm.madv = I915_MADV_WILLNEED; | |
4032 | INIT_RADIX_TREE(&obj->mm.get_page.radix, GFP_KERNEL | __GFP_NOWARN); | |
4033 | mutex_init(&obj->mm.get_page.lock); | |
0327d6ba | 4034 | |
f19ec8cb | 4035 | i915_gem_info_add_obj(to_i915(obj->base.dev), obj->base.size); |
0327d6ba CW |
4036 | } |
4037 | ||
37e680a1 | 4038 | static const struct drm_i915_gem_object_ops i915_gem_object_ops = { |
3599a91c TU |
4039 | .flags = I915_GEM_OBJECT_HAS_STRUCT_PAGE | |
4040 | I915_GEM_OBJECT_IS_SHRINKABLE, | |
37e680a1 CW |
4041 | .get_pages = i915_gem_object_get_pages_gtt, |
4042 | .put_pages = i915_gem_object_put_pages_gtt, | |
4043 | }; | |
4044 | ||
b4bcbe2a | 4045 | struct drm_i915_gem_object * |
12d79d78 | 4046 | i915_gem_object_create(struct drm_i915_private *dev_priv, u64 size) |
ac52bc56 | 4047 | { |
c397b908 | 4048 | struct drm_i915_gem_object *obj; |
5949eac4 | 4049 | struct address_space *mapping; |
1a240d4d | 4050 | gfp_t mask; |
fe3db79b | 4051 | int ret; |
ac52bc56 | 4052 | |
b4bcbe2a CW |
4053 | /* There is a prevalence of the assumption that we fit the object's |
4054 | * page count inside a 32bit _signed_ variable. Let's document this and | |
4055 | * catch if we ever need to fix it. In the meantime, if you do spot | |
4056 | * such a local variable, please consider fixing! | |
4057 | */ | |
4058 | if (WARN_ON(size >> PAGE_SHIFT > INT_MAX)) | |
4059 | return ERR_PTR(-E2BIG); | |
4060 | ||
4061 | if (overflows_type(size, obj->base.size)) | |
4062 | return ERR_PTR(-E2BIG); | |
4063 | ||
187685cb | 4064 | obj = i915_gem_object_alloc(dev_priv); |
c397b908 | 4065 | if (obj == NULL) |
fe3db79b | 4066 | return ERR_PTR(-ENOMEM); |
673a394b | 4067 | |
12d79d78 | 4068 | ret = drm_gem_object_init(&dev_priv->drm, &obj->base, size); |
fe3db79b CW |
4069 | if (ret) |
4070 | goto fail; | |
673a394b | 4071 | |
bed1ea95 | 4072 | mask = GFP_HIGHUSER | __GFP_RECLAIMABLE; |
c0f86832 | 4073 | if (IS_I965GM(dev_priv) || IS_I965G(dev_priv)) { |
bed1ea95 CW |
4074 | /* 965gm cannot relocate objects above 4GiB. */ |
4075 | mask &= ~__GFP_HIGHMEM; | |
4076 | mask |= __GFP_DMA32; | |
4077 | } | |
4078 | ||
93c76a3d | 4079 | mapping = obj->base.filp->f_mapping; |
bed1ea95 | 4080 | mapping_set_gfp_mask(mapping, mask); |
5949eac4 | 4081 | |
37e680a1 | 4082 | i915_gem_object_init(obj, &i915_gem_object_ops); |
73aa808f | 4083 | |
c397b908 DV |
4084 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; |
4085 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; | |
673a394b | 4086 | |
0031fb96 | 4087 | if (HAS_LLC(dev_priv)) { |
3d29b842 | 4088 | /* On some devices, we can have the GPU use the LLC (the CPU |
a1871112 EA |
4089 | * cache) for about a 10% performance improvement |
4090 | * compared to uncached. Graphics requests other than | |
4091 | * display scanout are coherent with the CPU in | |
4092 | * accessing this cache. This means in this mode we | |
4093 | * don't need to clflush on the CPU side, and on the | |
4094 | * GPU side we only need to flush internal caches to | |
4095 | * get data visible to the CPU. | |
4096 | * | |
4097 | * However, we maintain the display planes as UC, and so | |
4098 | * need to rebind when first used as such. | |
4099 | */ | |
4100 | obj->cache_level = I915_CACHE_LLC; | |
4101 | } else | |
4102 | obj->cache_level = I915_CACHE_NONE; | |
4103 | ||
d861e338 DV |
4104 | trace_i915_gem_object_create(obj); |
4105 | ||
05394f39 | 4106 | return obj; |
fe3db79b CW |
4107 | |
4108 | fail: | |
4109 | i915_gem_object_free(obj); | |
fe3db79b | 4110 | return ERR_PTR(ret); |
c397b908 DV |
4111 | } |
4112 | ||
340fbd8c CW |
4113 | static bool discard_backing_storage(struct drm_i915_gem_object *obj) |
4114 | { | |
4115 | /* If we are the last user of the backing storage (be it shmemfs | |
4116 | * pages or stolen etc), we know that the pages are going to be | |
4117 | * immediately released. In this case, we can then skip copying | |
4118 | * back the contents from the GPU. | |
4119 | */ | |
4120 | ||
a4f5ea64 | 4121 | if (obj->mm.madv != I915_MADV_WILLNEED) |
340fbd8c CW |
4122 | return false; |
4123 | ||
4124 | if (obj->base.filp == NULL) | |
4125 | return true; | |
4126 | ||
4127 | /* At first glance, this looks racy, but then again so would be | |
4128 | * userspace racing mmap against close. However, the first external | |
4129 | * reference to the filp can only be obtained through the | |
4130 | * i915_gem_mmap_ioctl() which safeguards us against the user | |
4131 | * acquiring such a reference whilst we are in the middle of | |
4132 | * freeing the object. | |
4133 | */ | |
4134 | return atomic_long_read(&obj->base.filp->f_count) == 1; | |
4135 | } | |
4136 | ||
fbbd37b3 CW |
4137 | static void __i915_gem_free_objects(struct drm_i915_private *i915, |
4138 | struct llist_node *freed) | |
673a394b | 4139 | { |
fbbd37b3 | 4140 | struct drm_i915_gem_object *obj, *on; |
673a394b | 4141 | |
fbbd37b3 CW |
4142 | mutex_lock(&i915->drm.struct_mutex); |
4143 | intel_runtime_pm_get(i915); | |
4144 | llist_for_each_entry(obj, freed, freed) { | |
4145 | struct i915_vma *vma, *vn; | |
4146 | ||
4147 | trace_i915_gem_object_destroy(obj); | |
4148 | ||
4149 | GEM_BUG_ON(i915_gem_object_is_active(obj)); | |
4150 | list_for_each_entry_safe(vma, vn, | |
4151 | &obj->vma_list, obj_link) { | |
4152 | GEM_BUG_ON(!i915_vma_is_ggtt(vma)); | |
4153 | GEM_BUG_ON(i915_vma_is_active(vma)); | |
4154 | vma->flags &= ~I915_VMA_PIN_MASK; | |
4155 | i915_vma_close(vma); | |
4156 | } | |
db6c2b41 CW |
4157 | GEM_BUG_ON(!list_empty(&obj->vma_list)); |
4158 | GEM_BUG_ON(!RB_EMPTY_ROOT(&obj->vma_tree)); | |
fbbd37b3 | 4159 | |
56cea323 | 4160 | list_del(&obj->global_link); |
fbbd37b3 CW |
4161 | } |
4162 | intel_runtime_pm_put(i915); | |
4163 | mutex_unlock(&i915->drm.struct_mutex); | |
4164 | ||
4165 | llist_for_each_entry_safe(obj, on, freed, freed) { | |
4166 | GEM_BUG_ON(obj->bind_count); | |
4167 | GEM_BUG_ON(atomic_read(&obj->frontbuffer_bits)); | |
4168 | ||
4169 | if (obj->ops->release) | |
4170 | obj->ops->release(obj); | |
f65c9168 | 4171 | |
fbbd37b3 CW |
4172 | if (WARN_ON(i915_gem_object_has_pinned_pages(obj))) |
4173 | atomic_set(&obj->mm.pages_pin_count, 0); | |
548625ee | 4174 | __i915_gem_object_put_pages(obj, I915_MM_NORMAL); |
fbbd37b3 CW |
4175 | GEM_BUG_ON(obj->mm.pages); |
4176 | ||
4177 | if (obj->base.import_attach) | |
4178 | drm_prime_gem_destroy(&obj->base, NULL); | |
4179 | ||
d07f0e59 | 4180 | reservation_object_fini(&obj->__builtin_resv); |
fbbd37b3 CW |
4181 | drm_gem_object_release(&obj->base); |
4182 | i915_gem_info_remove_obj(i915, obj->base.size); | |
4183 | ||
4184 | kfree(obj->bit_17); | |
4185 | i915_gem_object_free(obj); | |
4186 | } | |
4187 | } | |
4188 | ||
4189 | static void i915_gem_flush_free_objects(struct drm_i915_private *i915) | |
4190 | { | |
4191 | struct llist_node *freed; | |
4192 | ||
4193 | freed = llist_del_all(&i915->mm.free_list); | |
4194 | if (unlikely(freed)) | |
4195 | __i915_gem_free_objects(i915, freed); | |
4196 | } | |
4197 | ||
4198 | static void __i915_gem_free_work(struct work_struct *work) | |
4199 | { | |
4200 | struct drm_i915_private *i915 = | |
4201 | container_of(work, struct drm_i915_private, mm.free_work); | |
4202 | struct llist_node *freed; | |
26e12f89 | 4203 | |
b1f788c6 CW |
4204 | /* All file-owned VMA should have been released by this point through |
4205 | * i915_gem_close_object(), or earlier by i915_gem_context_close(). | |
4206 | * However, the object may also be bound into the global GTT (e.g. | |
4207 | * older GPUs without per-process support, or for direct access through | |
4208 | * the GTT either for the user or for scanout). Those VMA still need to | |
4209 | * unbound now. | |
4210 | */ | |
1488fc08 | 4211 | |
fbbd37b3 CW |
4212 | while ((freed = llist_del_all(&i915->mm.free_list))) |
4213 | __i915_gem_free_objects(i915, freed); | |
4214 | } | |
a071fa00 | 4215 | |
fbbd37b3 CW |
4216 | static void __i915_gem_free_object_rcu(struct rcu_head *head) |
4217 | { | |
4218 | struct drm_i915_gem_object *obj = | |
4219 | container_of(head, typeof(*obj), rcu); | |
4220 | struct drm_i915_private *i915 = to_i915(obj->base.dev); | |
4221 | ||
4222 | /* We can't simply use call_rcu() from i915_gem_free_object() | |
4223 | * as we need to block whilst unbinding, and the call_rcu | |
4224 | * task may be called from softirq context. So we take a | |
4225 | * detour through a worker. | |
4226 | */ | |
4227 | if (llist_add(&obj->freed, &i915->mm.free_list)) | |
4228 | schedule_work(&i915->mm.free_work); | |
4229 | } | |
656bfa3a | 4230 | |
fbbd37b3 CW |
4231 | void i915_gem_free_object(struct drm_gem_object *gem_obj) |
4232 | { | |
4233 | struct drm_i915_gem_object *obj = to_intel_bo(gem_obj); | |
a4f5ea64 | 4234 | |
bc0629a7 CW |
4235 | if (obj->mm.quirked) |
4236 | __i915_gem_object_unpin_pages(obj); | |
4237 | ||
340fbd8c | 4238 | if (discard_backing_storage(obj)) |
a4f5ea64 | 4239 | obj->mm.madv = I915_MADV_DONTNEED; |
de151cf6 | 4240 | |
fbbd37b3 CW |
4241 | /* Before we free the object, make sure any pure RCU-only |
4242 | * read-side critical sections are complete, e.g. | |
4243 | * i915_gem_busy_ioctl(). For the corresponding synchronized | |
4244 | * lookup see i915_gem_object_lookup_rcu(). | |
4245 | */ | |
4246 | call_rcu(&obj->rcu, __i915_gem_free_object_rcu); | |
673a394b EA |
4247 | } |
4248 | ||
f8a7fde4 CW |
4249 | void __i915_gem_object_release_unless_active(struct drm_i915_gem_object *obj) |
4250 | { | |
4251 | lockdep_assert_held(&obj->base.dev->struct_mutex); | |
4252 | ||
4253 | GEM_BUG_ON(i915_gem_object_has_active_reference(obj)); | |
4254 | if (i915_gem_object_is_active(obj)) | |
4255 | i915_gem_object_set_active_reference(obj); | |
4256 | else | |
4257 | i915_gem_object_put(obj); | |
4258 | } | |
4259 | ||
3033acab CW |
4260 | static void assert_kernel_context_is_current(struct drm_i915_private *dev_priv) |
4261 | { | |
4262 | struct intel_engine_cs *engine; | |
4263 | enum intel_engine_id id; | |
4264 | ||
4265 | for_each_engine(engine, dev_priv, id) | |
f131e356 CW |
4266 | GEM_BUG_ON(engine->last_retired_context && |
4267 | !i915_gem_context_is_kernel(engine->last_retired_context)); | |
3033acab CW |
4268 | } |
4269 | ||
24145517 CW |
4270 | void i915_gem_sanitize(struct drm_i915_private *i915) |
4271 | { | |
4272 | /* | |
4273 | * If we inherit context state from the BIOS or earlier occupants | |
4274 | * of the GPU, the GPU may be in an inconsistent state when we | |
4275 | * try to take over. The only way to remove the earlier state | |
4276 | * is by resetting. However, resetting on earlier gen is tricky as | |
4277 | * it may impact the display and we are uncertain about the stability | |
4278 | * of the reset, so we only reset recent machines with logical | |
4279 | * context support (that must be reset to remove any stray contexts). | |
4280 | */ | |
4281 | if (HAS_HW_CONTEXTS(i915)) { | |
4282 | int reset = intel_gpu_reset(i915, ALL_ENGINES); | |
4283 | WARN_ON(reset && reset != -ENODEV); | |
4284 | } | |
4285 | } | |
4286 | ||
bf9e8429 | 4287 | int i915_gem_suspend(struct drm_i915_private *dev_priv) |
29105ccc | 4288 | { |
bf9e8429 | 4289 | struct drm_device *dev = &dev_priv->drm; |
dcff85c8 | 4290 | int ret; |
28dfe52a | 4291 | |
54b4f68f CW |
4292 | intel_suspend_gt_powersave(dev_priv); |
4293 | ||
45c5f202 | 4294 | mutex_lock(&dev->struct_mutex); |
5ab57c70 CW |
4295 | |
4296 | /* We have to flush all the executing contexts to main memory so | |
4297 | * that they can saved in the hibernation image. To ensure the last | |
4298 | * context image is coherent, we have to switch away from it. That | |
4299 | * leaves the dev_priv->kernel_context still active when | |
4300 | * we actually suspend, and its image in memory may not match the GPU | |
4301 | * state. Fortunately, the kernel_context is disposable and we do | |
4302 | * not rely on its state. | |
4303 | */ | |
4304 | ret = i915_gem_switch_to_kernel_context(dev_priv); | |
4305 | if (ret) | |
4306 | goto err; | |
4307 | ||
22dd3bb9 CW |
4308 | ret = i915_gem_wait_for_idle(dev_priv, |
4309 | I915_WAIT_INTERRUPTIBLE | | |
4310 | I915_WAIT_LOCKED); | |
f7403347 | 4311 | if (ret) |
45c5f202 | 4312 | goto err; |
f7403347 | 4313 | |
c033666a | 4314 | i915_gem_retire_requests(dev_priv); |
28176ef4 | 4315 | GEM_BUG_ON(dev_priv->gt.active_requests); |
673a394b | 4316 | |
3033acab | 4317 | assert_kernel_context_is_current(dev_priv); |
b2e862d0 | 4318 | i915_gem_context_lost(dev_priv); |
45c5f202 CW |
4319 | mutex_unlock(&dev->struct_mutex); |
4320 | ||
737b1506 | 4321 | cancel_delayed_work_sync(&dev_priv->gpu_error.hangcheck_work); |
67d97da3 | 4322 | cancel_delayed_work_sync(&dev_priv->gt.retire_work); |
bdeb9785 CW |
4323 | |
4324 | /* As the idle_work is rearming if it detects a race, play safe and | |
4325 | * repeat the flush until it is definitely idle. | |
4326 | */ | |
4327 | while (flush_delayed_work(&dev_priv->gt.idle_work)) | |
4328 | ; | |
4329 | ||
4330 | i915_gem_drain_freed_objects(dev_priv); | |
29105ccc | 4331 | |
bdcf120b CW |
4332 | /* Assert that we sucessfully flushed all the work and |
4333 | * reset the GPU back to its idle, low power state. | |
4334 | */ | |
67d97da3 | 4335 | WARN_ON(dev_priv->gt.awake); |
31ab49ab | 4336 | WARN_ON(!intel_execlists_idle(dev_priv)); |
bdcf120b | 4337 | |
1c777c5d ID |
4338 | /* |
4339 | * Neither the BIOS, ourselves or any other kernel | |
4340 | * expects the system to be in execlists mode on startup, | |
4341 | * so we need to reset the GPU back to legacy mode. And the only | |
4342 | * known way to disable logical contexts is through a GPU reset. | |
4343 | * | |
4344 | * So in order to leave the system in a known default configuration, | |
4345 | * always reset the GPU upon unload and suspend. Afterwards we then | |
4346 | * clean up the GEM state tracking, flushing off the requests and | |
4347 | * leaving the system in a known idle state. | |
4348 | * | |
4349 | * Note that is of the upmost importance that the GPU is idle and | |
4350 | * all stray writes are flushed *before* we dismantle the backing | |
4351 | * storage for the pinned objects. | |
4352 | * | |
4353 | * However, since we are uncertain that resetting the GPU on older | |
4354 | * machines is a good idea, we don't - just in case it leaves the | |
4355 | * machine in an unusable condition. | |
4356 | */ | |
24145517 | 4357 | i915_gem_sanitize(dev_priv); |
1c777c5d | 4358 | |
673a394b | 4359 | return 0; |
45c5f202 CW |
4360 | |
4361 | err: | |
4362 | mutex_unlock(&dev->struct_mutex); | |
4363 | return ret; | |
673a394b EA |
4364 | } |
4365 | ||
bf9e8429 | 4366 | void i915_gem_resume(struct drm_i915_private *dev_priv) |
5ab57c70 | 4367 | { |
bf9e8429 | 4368 | struct drm_device *dev = &dev_priv->drm; |
5ab57c70 | 4369 | |
31ab49ab ID |
4370 | WARN_ON(dev_priv->gt.awake); |
4371 | ||
5ab57c70 | 4372 | mutex_lock(&dev->struct_mutex); |
275a991c | 4373 | i915_gem_restore_gtt_mappings(dev_priv); |
5ab57c70 CW |
4374 | |
4375 | /* As we didn't flush the kernel context before suspend, we cannot | |
4376 | * guarantee that the context image is complete. So let's just reset | |
4377 | * it and start again. | |
4378 | */ | |
821ed7df | 4379 | dev_priv->gt.resume(dev_priv); |
5ab57c70 CW |
4380 | |
4381 | mutex_unlock(&dev->struct_mutex); | |
4382 | } | |
4383 | ||
c6be607a | 4384 | void i915_gem_init_swizzling(struct drm_i915_private *dev_priv) |
f691e2f4 | 4385 | { |
c6be607a | 4386 | if (INTEL_GEN(dev_priv) < 5 || |
f691e2f4 DV |
4387 | dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE) |
4388 | return; | |
4389 | ||
4390 | I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) | | |
4391 | DISP_TILE_SURFACE_SWIZZLING); | |
4392 | ||
5db94019 | 4393 | if (IS_GEN5(dev_priv)) |
11782b02 DV |
4394 | return; |
4395 | ||
f691e2f4 | 4396 | I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_SWZCTL); |
5db94019 | 4397 | if (IS_GEN6(dev_priv)) |
6b26c86d | 4398 | I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB)); |
5db94019 | 4399 | else if (IS_GEN7(dev_priv)) |
6b26c86d | 4400 | I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB)); |
5db94019 | 4401 | else if (IS_GEN8(dev_priv)) |
31a5336e | 4402 | I915_WRITE(GAMTARBMODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_BDW)); |
8782e26c BW |
4403 | else |
4404 | BUG(); | |
f691e2f4 | 4405 | } |
e21af88d | 4406 | |
50a0bc90 | 4407 | static void init_unused_ring(struct drm_i915_private *dev_priv, u32 base) |
81e7f200 | 4408 | { |
81e7f200 VS |
4409 | I915_WRITE(RING_CTL(base), 0); |
4410 | I915_WRITE(RING_HEAD(base), 0); | |
4411 | I915_WRITE(RING_TAIL(base), 0); | |
4412 | I915_WRITE(RING_START(base), 0); | |
4413 | } | |
4414 | ||
50a0bc90 | 4415 | static void init_unused_rings(struct drm_i915_private *dev_priv) |
81e7f200 | 4416 | { |
50a0bc90 TU |
4417 | if (IS_I830(dev_priv)) { |
4418 | init_unused_ring(dev_priv, PRB1_BASE); | |
4419 | init_unused_ring(dev_priv, SRB0_BASE); | |
4420 | init_unused_ring(dev_priv, SRB1_BASE); | |
4421 | init_unused_ring(dev_priv, SRB2_BASE); | |
4422 | init_unused_ring(dev_priv, SRB3_BASE); | |
4423 | } else if (IS_GEN2(dev_priv)) { | |
4424 | init_unused_ring(dev_priv, SRB0_BASE); | |
4425 | init_unused_ring(dev_priv, SRB1_BASE); | |
4426 | } else if (IS_GEN3(dev_priv)) { | |
4427 | init_unused_ring(dev_priv, PRB1_BASE); | |
4428 | init_unused_ring(dev_priv, PRB2_BASE); | |
81e7f200 VS |
4429 | } |
4430 | } | |
4431 | ||
20a8a74a | 4432 | static int __i915_gem_restart_engines(void *data) |
4fc7c971 | 4433 | { |
20a8a74a | 4434 | struct drm_i915_private *i915 = data; |
e2f80391 | 4435 | struct intel_engine_cs *engine; |
3b3f1650 | 4436 | enum intel_engine_id id; |
20a8a74a CW |
4437 | int err; |
4438 | ||
4439 | for_each_engine(engine, i915, id) { | |
4440 | err = engine->init_hw(engine); | |
4441 | if (err) | |
4442 | return err; | |
4443 | } | |
4444 | ||
4445 | return 0; | |
4446 | } | |
4447 | ||
4448 | int i915_gem_init_hw(struct drm_i915_private *dev_priv) | |
4449 | { | |
d200cda6 | 4450 | int ret; |
4fc7c971 | 4451 | |
de867c20 CW |
4452 | dev_priv->gt.last_init_time = ktime_get(); |
4453 | ||
5e4f5189 CW |
4454 | /* Double layer security blanket, see i915_gem_init() */ |
4455 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); | |
4456 | ||
0031fb96 | 4457 | if (HAS_EDRAM(dev_priv) && INTEL_GEN(dev_priv) < 9) |
05e21cc4 | 4458 | I915_WRITE(HSW_IDICR, I915_READ(HSW_IDICR) | IDIHASHMSK(0xf)); |
4fc7c971 | 4459 | |
772c2a51 | 4460 | if (IS_HASWELL(dev_priv)) |
50a0bc90 | 4461 | I915_WRITE(MI_PREDICATE_RESULT_2, IS_HSW_GT3(dev_priv) ? |
0bf21347 | 4462 | LOWER_SLICE_ENABLED : LOWER_SLICE_DISABLED); |
9435373e | 4463 | |
6e266956 | 4464 | if (HAS_PCH_NOP(dev_priv)) { |
fd6b8f43 | 4465 | if (IS_IVYBRIDGE(dev_priv)) { |
6ba844b0 DV |
4466 | u32 temp = I915_READ(GEN7_MSG_CTL); |
4467 | temp &= ~(WAIT_FOR_PCH_FLR_ACK | WAIT_FOR_PCH_RESET_ACK); | |
4468 | I915_WRITE(GEN7_MSG_CTL, temp); | |
c6be607a | 4469 | } else if (INTEL_GEN(dev_priv) >= 7) { |
6ba844b0 DV |
4470 | u32 temp = I915_READ(HSW_NDE_RSTWRN_OPT); |
4471 | temp &= ~RESET_PCH_HANDSHAKE_ENABLE; | |
4472 | I915_WRITE(HSW_NDE_RSTWRN_OPT, temp); | |
4473 | } | |
88a2b2a3 BW |
4474 | } |
4475 | ||
c6be607a | 4476 | i915_gem_init_swizzling(dev_priv); |
4fc7c971 | 4477 | |
d5abdfda DV |
4478 | /* |
4479 | * At least 830 can leave some of the unused rings | |
4480 | * "active" (ie. head != tail) after resume which | |
4481 | * will prevent c3 entry. Makes sure all unused rings | |
4482 | * are totally idle. | |
4483 | */ | |
50a0bc90 | 4484 | init_unused_rings(dev_priv); |
d5abdfda | 4485 | |
ed54c1a1 | 4486 | BUG_ON(!dev_priv->kernel_context); |
90638cc1 | 4487 | |
c6be607a | 4488 | ret = i915_ppgtt_init_hw(dev_priv); |
4ad2fd88 JH |
4489 | if (ret) { |
4490 | DRM_ERROR("PPGTT enable HW failed %d\n", ret); | |
4491 | goto out; | |
4492 | } | |
4493 | ||
4494 | /* Need to do basic initialisation of all rings first: */ | |
20a8a74a CW |
4495 | ret = __i915_gem_restart_engines(dev_priv); |
4496 | if (ret) | |
4497 | goto out; | |
99433931 | 4498 | |
bf9e8429 | 4499 | intel_mocs_init_l3cc_table(dev_priv); |
0ccdacf6 | 4500 | |
33a732f4 | 4501 | /* We can't enable contexts until all firmware is loaded */ |
bf9e8429 | 4502 | ret = intel_guc_setup(dev_priv); |
e556f7c1 DG |
4503 | if (ret) |
4504 | goto out; | |
33a732f4 | 4505 | |
5e4f5189 CW |
4506 | out: |
4507 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); | |
2fa48d8d | 4508 | return ret; |
8187a2b7 ZN |
4509 | } |
4510 | ||
39df9190 CW |
4511 | bool intel_sanitize_semaphores(struct drm_i915_private *dev_priv, int value) |
4512 | { | |
4513 | if (INTEL_INFO(dev_priv)->gen < 6) | |
4514 | return false; | |
4515 | ||
4516 | /* TODO: make semaphores and Execlists play nicely together */ | |
4517 | if (i915.enable_execlists) | |
4518 | return false; | |
4519 | ||
4520 | if (value >= 0) | |
4521 | return value; | |
4522 | ||
4523 | #ifdef CONFIG_INTEL_IOMMU | |
4524 | /* Enable semaphores on SNB when IO remapping is off */ | |
4525 | if (INTEL_INFO(dev_priv)->gen == 6 && intel_iommu_gfx_mapped) | |
4526 | return false; | |
4527 | #endif | |
4528 | ||
4529 | return true; | |
4530 | } | |
4531 | ||
bf9e8429 | 4532 | int i915_gem_init(struct drm_i915_private *dev_priv) |
1070a42b | 4533 | { |
1070a42b CW |
4534 | int ret; |
4535 | ||
bf9e8429 | 4536 | mutex_lock(&dev_priv->drm.struct_mutex); |
d62b4892 | 4537 | |
a83014d3 | 4538 | if (!i915.enable_execlists) { |
821ed7df | 4539 | dev_priv->gt.resume = intel_legacy_submission_resume; |
7e37f889 | 4540 | dev_priv->gt.cleanup_engine = intel_engine_cleanup; |
454afebd | 4541 | } else { |
821ed7df | 4542 | dev_priv->gt.resume = intel_lr_context_resume; |
117897f4 | 4543 | dev_priv->gt.cleanup_engine = intel_logical_ring_cleanup; |
a83014d3 OM |
4544 | } |
4545 | ||
5e4f5189 CW |
4546 | /* This is just a security blanket to placate dragons. |
4547 | * On some systems, we very sporadically observe that the first TLBs | |
4548 | * used by the CS may be stale, despite us poking the TLB reset. If | |
4549 | * we hold the forcewake during initialisation these problems | |
4550 | * just magically go away. | |
4551 | */ | |
4552 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); | |
4553 | ||
72778cb2 | 4554 | i915_gem_init_userptr(dev_priv); |
f6b9d5ca CW |
4555 | |
4556 | ret = i915_gem_init_ggtt(dev_priv); | |
4557 | if (ret) | |
4558 | goto out_unlock; | |
d62b4892 | 4559 | |
bf9e8429 | 4560 | ret = i915_gem_context_init(dev_priv); |
7bcc3777 JN |
4561 | if (ret) |
4562 | goto out_unlock; | |
2fa48d8d | 4563 | |
bf9e8429 | 4564 | ret = intel_engines_init(dev_priv); |
35a57ffb | 4565 | if (ret) |
7bcc3777 | 4566 | goto out_unlock; |
2fa48d8d | 4567 | |
bf9e8429 | 4568 | ret = i915_gem_init_hw(dev_priv); |
60990320 | 4569 | if (ret == -EIO) { |
7e21d648 | 4570 | /* Allow engine initialisation to fail by marking the GPU as |
60990320 CW |
4571 | * wedged. But we only want to do this where the GPU is angry, |
4572 | * for all other failure, such as an allocation failure, bail. | |
4573 | */ | |
4574 | DRM_ERROR("Failed to initialize GPU, declaring it wedged\n"); | |
821ed7df | 4575 | i915_gem_set_wedged(dev_priv); |
60990320 | 4576 | ret = 0; |
1070a42b | 4577 | } |
7bcc3777 JN |
4578 | |
4579 | out_unlock: | |
5e4f5189 | 4580 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); |
bf9e8429 | 4581 | mutex_unlock(&dev_priv->drm.struct_mutex); |
1070a42b | 4582 | |
60990320 | 4583 | return ret; |
1070a42b CW |
4584 | } |
4585 | ||
24145517 CW |
4586 | void i915_gem_init_mmio(struct drm_i915_private *i915) |
4587 | { | |
4588 | i915_gem_sanitize(i915); | |
4589 | } | |
4590 | ||
8187a2b7 | 4591 | void |
cb15d9f8 | 4592 | i915_gem_cleanup_engines(struct drm_i915_private *dev_priv) |
8187a2b7 | 4593 | { |
e2f80391 | 4594 | struct intel_engine_cs *engine; |
3b3f1650 | 4595 | enum intel_engine_id id; |
8187a2b7 | 4596 | |
3b3f1650 | 4597 | for_each_engine(engine, dev_priv, id) |
117897f4 | 4598 | dev_priv->gt.cleanup_engine(engine); |
8187a2b7 ZN |
4599 | } |
4600 | ||
40ae4e16 ID |
4601 | void |
4602 | i915_gem_load_init_fences(struct drm_i915_private *dev_priv) | |
4603 | { | |
49ef5294 | 4604 | int i; |
40ae4e16 ID |
4605 | |
4606 | if (INTEL_INFO(dev_priv)->gen >= 7 && !IS_VALLEYVIEW(dev_priv) && | |
4607 | !IS_CHERRYVIEW(dev_priv)) | |
4608 | dev_priv->num_fence_regs = 32; | |
73f67aa8 JN |
4609 | else if (INTEL_INFO(dev_priv)->gen >= 4 || |
4610 | IS_I945G(dev_priv) || IS_I945GM(dev_priv) || | |
4611 | IS_G33(dev_priv) || IS_PINEVIEW(dev_priv)) | |
40ae4e16 ID |
4612 | dev_priv->num_fence_regs = 16; |
4613 | else | |
4614 | dev_priv->num_fence_regs = 8; | |
4615 | ||
c033666a | 4616 | if (intel_vgpu_active(dev_priv)) |
40ae4e16 ID |
4617 | dev_priv->num_fence_regs = |
4618 | I915_READ(vgtif_reg(avail_rs.fence_num)); | |
4619 | ||
4620 | /* Initialize fence registers to zero */ | |
49ef5294 CW |
4621 | for (i = 0; i < dev_priv->num_fence_regs; i++) { |
4622 | struct drm_i915_fence_reg *fence = &dev_priv->fence_regs[i]; | |
4623 | ||
4624 | fence->i915 = dev_priv; | |
4625 | fence->id = i; | |
4626 | list_add_tail(&fence->link, &dev_priv->mm.fence_list); | |
4627 | } | |
4362f4f6 | 4628 | i915_gem_restore_fences(dev_priv); |
40ae4e16 | 4629 | |
4362f4f6 | 4630 | i915_gem_detect_bit_6_swizzle(dev_priv); |
40ae4e16 ID |
4631 | } |
4632 | ||
73cb9701 | 4633 | int |
cb15d9f8 | 4634 | i915_gem_load_init(struct drm_i915_private *dev_priv) |
673a394b | 4635 | { |
a933568e | 4636 | int err = -ENOMEM; |
42dcedd4 | 4637 | |
a933568e TU |
4638 | dev_priv->objects = KMEM_CACHE(drm_i915_gem_object, SLAB_HWCACHE_ALIGN); |
4639 | if (!dev_priv->objects) | |
73cb9701 | 4640 | goto err_out; |
73cb9701 | 4641 | |
a933568e TU |
4642 | dev_priv->vmas = KMEM_CACHE(i915_vma, SLAB_HWCACHE_ALIGN); |
4643 | if (!dev_priv->vmas) | |
73cb9701 | 4644 | goto err_objects; |
73cb9701 | 4645 | |
a933568e TU |
4646 | dev_priv->requests = KMEM_CACHE(drm_i915_gem_request, |
4647 | SLAB_HWCACHE_ALIGN | | |
4648 | SLAB_RECLAIM_ACCOUNT | | |
4649 | SLAB_DESTROY_BY_RCU); | |
4650 | if (!dev_priv->requests) | |
73cb9701 | 4651 | goto err_vmas; |
73cb9701 | 4652 | |
52e54209 CW |
4653 | dev_priv->dependencies = KMEM_CACHE(i915_dependency, |
4654 | SLAB_HWCACHE_ALIGN | | |
4655 | SLAB_RECLAIM_ACCOUNT); | |
4656 | if (!dev_priv->dependencies) | |
4657 | goto err_requests; | |
4658 | ||
73cb9701 CW |
4659 | mutex_lock(&dev_priv->drm.struct_mutex); |
4660 | INIT_LIST_HEAD(&dev_priv->gt.timelines); | |
bb89485e | 4661 | err = i915_gem_timeline_init__global(dev_priv); |
73cb9701 CW |
4662 | mutex_unlock(&dev_priv->drm.struct_mutex); |
4663 | if (err) | |
52e54209 | 4664 | goto err_dependencies; |
673a394b | 4665 | |
a33afea5 | 4666 | INIT_LIST_HEAD(&dev_priv->context_list); |
fbbd37b3 CW |
4667 | INIT_WORK(&dev_priv->mm.free_work, __i915_gem_free_work); |
4668 | init_llist_head(&dev_priv->mm.free_list); | |
6c085a72 CW |
4669 | INIT_LIST_HEAD(&dev_priv->mm.unbound_list); |
4670 | INIT_LIST_HEAD(&dev_priv->mm.bound_list); | |
a09ba7fa | 4671 | INIT_LIST_HEAD(&dev_priv->mm.fence_list); |
275f039d | 4672 | INIT_LIST_HEAD(&dev_priv->mm.userfault_list); |
67d97da3 | 4673 | INIT_DELAYED_WORK(&dev_priv->gt.retire_work, |
673a394b | 4674 | i915_gem_retire_work_handler); |
67d97da3 | 4675 | INIT_DELAYED_WORK(&dev_priv->gt.idle_work, |
b29c19b6 | 4676 | i915_gem_idle_work_handler); |
1f15b76f | 4677 | init_waitqueue_head(&dev_priv->gpu_error.wait_queue); |
1f83fee0 | 4678 | init_waitqueue_head(&dev_priv->gpu_error.reset_queue); |
31169714 | 4679 | |
72bfa19c CW |
4680 | dev_priv->relative_constants_mode = I915_EXEC_CONSTANTS_REL_GENERAL; |
4681 | ||
6b95a207 | 4682 | init_waitqueue_head(&dev_priv->pending_flip_queue); |
17250b71 | 4683 | |
ce453d81 CW |
4684 | dev_priv->mm.interruptible = true; |
4685 | ||
6f633402 JL |
4686 | atomic_set(&dev_priv->mm.bsd_engine_dispatch_index, 0); |
4687 | ||
b5add959 | 4688 | spin_lock_init(&dev_priv->fb_tracking.lock); |
73cb9701 CW |
4689 | |
4690 | return 0; | |
4691 | ||
52e54209 CW |
4692 | err_dependencies: |
4693 | kmem_cache_destroy(dev_priv->dependencies); | |
73cb9701 CW |
4694 | err_requests: |
4695 | kmem_cache_destroy(dev_priv->requests); | |
4696 | err_vmas: | |
4697 | kmem_cache_destroy(dev_priv->vmas); | |
4698 | err_objects: | |
4699 | kmem_cache_destroy(dev_priv->objects); | |
4700 | err_out: | |
4701 | return err; | |
673a394b | 4702 | } |
71acb5eb | 4703 | |
cb15d9f8 | 4704 | void i915_gem_load_cleanup(struct drm_i915_private *dev_priv) |
d64aa096 | 4705 | { |
c4d4c1c6 | 4706 | i915_gem_drain_freed_objects(dev_priv); |
7d5d59e5 | 4707 | WARN_ON(!llist_empty(&dev_priv->mm.free_list)); |
c4d4c1c6 | 4708 | WARN_ON(dev_priv->mm.object_count); |
7d5d59e5 | 4709 | |
ea84aa77 MA |
4710 | mutex_lock(&dev_priv->drm.struct_mutex); |
4711 | i915_gem_timeline_fini(&dev_priv->gt.global_timeline); | |
4712 | WARN_ON(!list_empty(&dev_priv->gt.timelines)); | |
4713 | mutex_unlock(&dev_priv->drm.struct_mutex); | |
4714 | ||
52e54209 | 4715 | kmem_cache_destroy(dev_priv->dependencies); |
d64aa096 ID |
4716 | kmem_cache_destroy(dev_priv->requests); |
4717 | kmem_cache_destroy(dev_priv->vmas); | |
4718 | kmem_cache_destroy(dev_priv->objects); | |
0eafec6d CW |
4719 | |
4720 | /* And ensure that our DESTROY_BY_RCU slabs are truly destroyed */ | |
4721 | rcu_barrier(); | |
d64aa096 ID |
4722 | } |
4723 | ||
6a800eab CW |
4724 | int i915_gem_freeze(struct drm_i915_private *dev_priv) |
4725 | { | |
6a800eab CW |
4726 | mutex_lock(&dev_priv->drm.struct_mutex); |
4727 | i915_gem_shrink_all(dev_priv); | |
4728 | mutex_unlock(&dev_priv->drm.struct_mutex); | |
4729 | ||
6a800eab CW |
4730 | return 0; |
4731 | } | |
4732 | ||
461fb99c CW |
4733 | int i915_gem_freeze_late(struct drm_i915_private *dev_priv) |
4734 | { | |
4735 | struct drm_i915_gem_object *obj; | |
7aab2d53 CW |
4736 | struct list_head *phases[] = { |
4737 | &dev_priv->mm.unbound_list, | |
4738 | &dev_priv->mm.bound_list, | |
4739 | NULL | |
4740 | }, **p; | |
461fb99c CW |
4741 | |
4742 | /* Called just before we write the hibernation image. | |
4743 | * | |
4744 | * We need to update the domain tracking to reflect that the CPU | |
4745 | * will be accessing all the pages to create and restore from the | |
4746 | * hibernation, and so upon restoration those pages will be in the | |
4747 | * CPU domain. | |
4748 | * | |
4749 | * To make sure the hibernation image contains the latest state, | |
4750 | * we update that state just before writing out the image. | |
7aab2d53 CW |
4751 | * |
4752 | * To try and reduce the hibernation image, we manually shrink | |
4753 | * the objects as well. | |
461fb99c CW |
4754 | */ |
4755 | ||
6a800eab CW |
4756 | mutex_lock(&dev_priv->drm.struct_mutex); |
4757 | i915_gem_shrink(dev_priv, -1UL, I915_SHRINK_UNBOUND); | |
461fb99c | 4758 | |
7aab2d53 | 4759 | for (p = phases; *p; p++) { |
56cea323 | 4760 | list_for_each_entry(obj, *p, global_link) { |
7aab2d53 CW |
4761 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; |
4762 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; | |
4763 | } | |
461fb99c | 4764 | } |
6a800eab | 4765 | mutex_unlock(&dev_priv->drm.struct_mutex); |
461fb99c CW |
4766 | |
4767 | return 0; | |
4768 | } | |
4769 | ||
f787a5f5 | 4770 | void i915_gem_release(struct drm_device *dev, struct drm_file *file) |
b962442e | 4771 | { |
f787a5f5 | 4772 | struct drm_i915_file_private *file_priv = file->driver_priv; |
15f7bbc7 | 4773 | struct drm_i915_gem_request *request; |
b962442e EA |
4774 | |
4775 | /* Clean up our request list when the client is going away, so that | |
4776 | * later retire_requests won't dereference our soon-to-be-gone | |
4777 | * file_priv. | |
4778 | */ | |
1c25595f | 4779 | spin_lock(&file_priv->mm.lock); |
15f7bbc7 | 4780 | list_for_each_entry(request, &file_priv->mm.request_list, client_list) |
f787a5f5 | 4781 | request->file_priv = NULL; |
1c25595f | 4782 | spin_unlock(&file_priv->mm.lock); |
b29c19b6 | 4783 | |
2e1b8730 | 4784 | if (!list_empty(&file_priv->rps.link)) { |
8d3afd7d | 4785 | spin_lock(&to_i915(dev)->rps.client_lock); |
2e1b8730 | 4786 | list_del(&file_priv->rps.link); |
8d3afd7d | 4787 | spin_unlock(&to_i915(dev)->rps.client_lock); |
1854d5ca | 4788 | } |
b29c19b6 CW |
4789 | } |
4790 | ||
4791 | int i915_gem_open(struct drm_device *dev, struct drm_file *file) | |
4792 | { | |
4793 | struct drm_i915_file_private *file_priv; | |
e422b888 | 4794 | int ret; |
b29c19b6 | 4795 | |
c4c29d7b | 4796 | DRM_DEBUG("\n"); |
b29c19b6 CW |
4797 | |
4798 | file_priv = kzalloc(sizeof(*file_priv), GFP_KERNEL); | |
4799 | if (!file_priv) | |
4800 | return -ENOMEM; | |
4801 | ||
4802 | file->driver_priv = file_priv; | |
f19ec8cb | 4803 | file_priv->dev_priv = to_i915(dev); |
ab0e7ff9 | 4804 | file_priv->file = file; |
2e1b8730 | 4805 | INIT_LIST_HEAD(&file_priv->rps.link); |
b29c19b6 CW |
4806 | |
4807 | spin_lock_init(&file_priv->mm.lock); | |
4808 | INIT_LIST_HEAD(&file_priv->mm.request_list); | |
b29c19b6 | 4809 | |
c80ff16e | 4810 | file_priv->bsd_engine = -1; |
de1add36 | 4811 | |
e422b888 BW |
4812 | ret = i915_gem_context_open(dev, file); |
4813 | if (ret) | |
4814 | kfree(file_priv); | |
b29c19b6 | 4815 | |
e422b888 | 4816 | return ret; |
b29c19b6 CW |
4817 | } |
4818 | ||
b680c37a DV |
4819 | /** |
4820 | * i915_gem_track_fb - update frontbuffer tracking | |
d9072a3e GT |
4821 | * @old: current GEM buffer for the frontbuffer slots |
4822 | * @new: new GEM buffer for the frontbuffer slots | |
4823 | * @frontbuffer_bits: bitmask of frontbuffer slots | |
b680c37a DV |
4824 | * |
4825 | * This updates the frontbuffer tracking bits @frontbuffer_bits by clearing them | |
4826 | * from @old and setting them in @new. Both @old and @new can be NULL. | |
4827 | */ | |
a071fa00 DV |
4828 | void i915_gem_track_fb(struct drm_i915_gem_object *old, |
4829 | struct drm_i915_gem_object *new, | |
4830 | unsigned frontbuffer_bits) | |
4831 | { | |
faf5bf0a CW |
4832 | /* Control of individual bits within the mask are guarded by |
4833 | * the owning plane->mutex, i.e. we can never see concurrent | |
4834 | * manipulation of individual bits. But since the bitfield as a whole | |
4835 | * is updated using RMW, we need to use atomics in order to update | |
4836 | * the bits. | |
4837 | */ | |
4838 | BUILD_BUG_ON(INTEL_FRONTBUFFER_BITS_PER_PIPE * I915_MAX_PIPES > | |
4839 | sizeof(atomic_t) * BITS_PER_BYTE); | |
4840 | ||
a071fa00 | 4841 | if (old) { |
faf5bf0a CW |
4842 | WARN_ON(!(atomic_read(&old->frontbuffer_bits) & frontbuffer_bits)); |
4843 | atomic_andnot(frontbuffer_bits, &old->frontbuffer_bits); | |
a071fa00 DV |
4844 | } |
4845 | ||
4846 | if (new) { | |
faf5bf0a CW |
4847 | WARN_ON(atomic_read(&new->frontbuffer_bits) & frontbuffer_bits); |
4848 | atomic_or(frontbuffer_bits, &new->frontbuffer_bits); | |
a071fa00 DV |
4849 | } |
4850 | } | |
4851 | ||
ea70299d DG |
4852 | /* Allocate a new GEM object and fill it with the supplied data */ |
4853 | struct drm_i915_gem_object * | |
12d79d78 | 4854 | i915_gem_object_create_from_data(struct drm_i915_private *dev_priv, |
ea70299d DG |
4855 | const void *data, size_t size) |
4856 | { | |
4857 | struct drm_i915_gem_object *obj; | |
4858 | struct sg_table *sg; | |
4859 | size_t bytes; | |
4860 | int ret; | |
4861 | ||
12d79d78 | 4862 | obj = i915_gem_object_create(dev_priv, round_up(size, PAGE_SIZE)); |
fe3db79b | 4863 | if (IS_ERR(obj)) |
ea70299d DG |
4864 | return obj; |
4865 | ||
4866 | ret = i915_gem_object_set_to_cpu_domain(obj, true); | |
4867 | if (ret) | |
4868 | goto fail; | |
4869 | ||
a4f5ea64 | 4870 | ret = i915_gem_object_pin_pages(obj); |
ea70299d DG |
4871 | if (ret) |
4872 | goto fail; | |
4873 | ||
a4f5ea64 | 4874 | sg = obj->mm.pages; |
ea70299d | 4875 | bytes = sg_copy_from_buffer(sg->sgl, sg->nents, (void *)data, size); |
a4f5ea64 | 4876 | obj->mm.dirty = true; /* Backing store is now out of date */ |
ea70299d DG |
4877 | i915_gem_object_unpin_pages(obj); |
4878 | ||
4879 | if (WARN_ON(bytes != size)) { | |
4880 | DRM_ERROR("Incomplete copy, wrote %zu of %zu", bytes, size); | |
4881 | ret = -EFAULT; | |
4882 | goto fail; | |
4883 | } | |
4884 | ||
4885 | return obj; | |
4886 | ||
4887 | fail: | |
f8c417cd | 4888 | i915_gem_object_put(obj); |
ea70299d DG |
4889 | return ERR_PTR(ret); |
4890 | } | |
96d77634 CW |
4891 | |
4892 | struct scatterlist * | |
4893 | i915_gem_object_get_sg(struct drm_i915_gem_object *obj, | |
4894 | unsigned int n, | |
4895 | unsigned int *offset) | |
4896 | { | |
a4f5ea64 | 4897 | struct i915_gem_object_page_iter *iter = &obj->mm.get_page; |
96d77634 CW |
4898 | struct scatterlist *sg; |
4899 | unsigned int idx, count; | |
4900 | ||
4901 | might_sleep(); | |
4902 | GEM_BUG_ON(n >= obj->base.size >> PAGE_SHIFT); | |
a4f5ea64 | 4903 | GEM_BUG_ON(!i915_gem_object_has_pinned_pages(obj)); |
96d77634 CW |
4904 | |
4905 | /* As we iterate forward through the sg, we record each entry in a | |
4906 | * radixtree for quick repeated (backwards) lookups. If we have seen | |
4907 | * this index previously, we will have an entry for it. | |
4908 | * | |
4909 | * Initial lookup is O(N), but this is amortized to O(1) for | |
4910 | * sequential page access (where each new request is consecutive | |
4911 | * to the previous one). Repeated lookups are O(lg(obj->base.size)), | |
4912 | * i.e. O(1) with a large constant! | |
4913 | */ | |
4914 | if (n < READ_ONCE(iter->sg_idx)) | |
4915 | goto lookup; | |
4916 | ||
4917 | mutex_lock(&iter->lock); | |
4918 | ||
4919 | /* We prefer to reuse the last sg so that repeated lookup of this | |
4920 | * (or the subsequent) sg are fast - comparing against the last | |
4921 | * sg is faster than going through the radixtree. | |
4922 | */ | |
4923 | ||
4924 | sg = iter->sg_pos; | |
4925 | idx = iter->sg_idx; | |
4926 | count = __sg_page_count(sg); | |
4927 | ||
4928 | while (idx + count <= n) { | |
4929 | unsigned long exception, i; | |
4930 | int ret; | |
4931 | ||
4932 | /* If we cannot allocate and insert this entry, or the | |
4933 | * individual pages from this range, cancel updating the | |
4934 | * sg_idx so that on this lookup we are forced to linearly | |
4935 | * scan onwards, but on future lookups we will try the | |
4936 | * insertion again (in which case we need to be careful of | |
4937 | * the error return reporting that we have already inserted | |
4938 | * this index). | |
4939 | */ | |
4940 | ret = radix_tree_insert(&iter->radix, idx, sg); | |
4941 | if (ret && ret != -EEXIST) | |
4942 | goto scan; | |
4943 | ||
4944 | exception = | |
4945 | RADIX_TREE_EXCEPTIONAL_ENTRY | | |
4946 | idx << RADIX_TREE_EXCEPTIONAL_SHIFT; | |
4947 | for (i = 1; i < count; i++) { | |
4948 | ret = radix_tree_insert(&iter->radix, idx + i, | |
4949 | (void *)exception); | |
4950 | if (ret && ret != -EEXIST) | |
4951 | goto scan; | |
4952 | } | |
4953 | ||
4954 | idx += count; | |
4955 | sg = ____sg_next(sg); | |
4956 | count = __sg_page_count(sg); | |
4957 | } | |
4958 | ||
4959 | scan: | |
4960 | iter->sg_pos = sg; | |
4961 | iter->sg_idx = idx; | |
4962 | ||
4963 | mutex_unlock(&iter->lock); | |
4964 | ||
4965 | if (unlikely(n < idx)) /* insertion completed by another thread */ | |
4966 | goto lookup; | |
4967 | ||
4968 | /* In case we failed to insert the entry into the radixtree, we need | |
4969 | * to look beyond the current sg. | |
4970 | */ | |
4971 | while (idx + count <= n) { | |
4972 | idx += count; | |
4973 | sg = ____sg_next(sg); | |
4974 | count = __sg_page_count(sg); | |
4975 | } | |
4976 | ||
4977 | *offset = n - idx; | |
4978 | return sg; | |
4979 | ||
4980 | lookup: | |
4981 | rcu_read_lock(); | |
4982 | ||
4983 | sg = radix_tree_lookup(&iter->radix, n); | |
4984 | GEM_BUG_ON(!sg); | |
4985 | ||
4986 | /* If this index is in the middle of multi-page sg entry, | |
4987 | * the radixtree will contain an exceptional entry that points | |
4988 | * to the start of that range. We will return the pointer to | |
4989 | * the base page and the offset of this page within the | |
4990 | * sg entry's range. | |
4991 | */ | |
4992 | *offset = 0; | |
4993 | if (unlikely(radix_tree_exception(sg))) { | |
4994 | unsigned long base = | |
4995 | (unsigned long)sg >> RADIX_TREE_EXCEPTIONAL_SHIFT; | |
4996 | ||
4997 | sg = radix_tree_lookup(&iter->radix, base); | |
4998 | GEM_BUG_ON(!sg); | |
4999 | ||
5000 | *offset = n - base; | |
5001 | } | |
5002 | ||
5003 | rcu_read_unlock(); | |
5004 | ||
5005 | return sg; | |
5006 | } | |
5007 | ||
5008 | struct page * | |
5009 | i915_gem_object_get_page(struct drm_i915_gem_object *obj, unsigned int n) | |
5010 | { | |
5011 | struct scatterlist *sg; | |
5012 | unsigned int offset; | |
5013 | ||
5014 | GEM_BUG_ON(!i915_gem_object_has_struct_page(obj)); | |
5015 | ||
5016 | sg = i915_gem_object_get_sg(obj, n, &offset); | |
5017 | return nth_page(sg_page(sg), offset); | |
5018 | } | |
5019 | ||
5020 | /* Like i915_gem_object_get_page(), but mark the returned page dirty */ | |
5021 | struct page * | |
5022 | i915_gem_object_get_dirty_page(struct drm_i915_gem_object *obj, | |
5023 | unsigned int n) | |
5024 | { | |
5025 | struct page *page; | |
5026 | ||
5027 | page = i915_gem_object_get_page(obj, n); | |
a4f5ea64 | 5028 | if (!obj->mm.dirty) |
96d77634 CW |
5029 | set_page_dirty(page); |
5030 | ||
5031 | return page; | |
5032 | } | |
5033 | ||
5034 | dma_addr_t | |
5035 | i915_gem_object_get_dma_address(struct drm_i915_gem_object *obj, | |
5036 | unsigned long n) | |
5037 | { | |
5038 | struct scatterlist *sg; | |
5039 | unsigned int offset; | |
5040 | ||
5041 | sg = i915_gem_object_get_sg(obj, n, &offset); | |
5042 | return sg_dma_address(sg) + (offset << PAGE_SHIFT); | |
5043 | } | |
935a2f77 CW |
5044 | |
5045 | #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST) | |
5046 | #include "selftests/scatterlist.c" | |
66d9cb5d | 5047 | #include "selftests/mock_gem_device.c" |
44653988 | 5048 | #include "selftests/huge_gem_object.c" |
8335fd65 | 5049 | #include "selftests/i915_gem_object.c" |
17059450 | 5050 | #include "selftests/i915_gem_coherency.c" |
935a2f77 | 5051 | #endif |