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Commit | Line | Data |
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673a394b EA |
1 | /* |
2 | * Copyright © 2008 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | * | |
26 | */ | |
27 | ||
28 | #include "drmP.h" | |
29 | #include "drm.h" | |
30 | #include "i915_drm.h" | |
31 | #include "i915_drv.h" | |
1c5d22f7 | 32 | #include "i915_trace.h" |
652c393a | 33 | #include "intel_drv.h" |
5a0e3ad6 | 34 | #include <linux/slab.h> |
673a394b | 35 | #include <linux/swap.h> |
79e53945 | 36 | #include <linux/pci.h> |
f8f235e5 | 37 | #include <linux/intel-gtt.h> |
673a394b | 38 | |
0108a3ed | 39 | static uint32_t i915_gem_get_gtt_alignment(struct drm_gem_object *obj); |
ba3d8d74 DV |
40 | |
41 | static int i915_gem_object_flush_gpu_write_domain(struct drm_gem_object *obj, | |
42 | bool pipelined); | |
e47c68e9 EA |
43 | static void i915_gem_object_flush_gtt_write_domain(struct drm_gem_object *obj); |
44 | static void i915_gem_object_flush_cpu_write_domain(struct drm_gem_object *obj); | |
e47c68e9 EA |
45 | static int i915_gem_object_set_to_cpu_domain(struct drm_gem_object *obj, |
46 | int write); | |
47 | static int i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object *obj, | |
48 | uint64_t offset, | |
49 | uint64_t size); | |
50 | static void i915_gem_object_set_to_full_cpu_read_domain(struct drm_gem_object *obj); | |
ba3d8d74 | 51 | static int i915_gem_object_wait_rendering(struct drm_gem_object *obj); |
de151cf6 JB |
52 | static int i915_gem_object_bind_to_gtt(struct drm_gem_object *obj, |
53 | unsigned alignment); | |
de151cf6 | 54 | static void i915_gem_clear_fence_reg(struct drm_gem_object *obj); |
71acb5eb DA |
55 | static int i915_gem_phys_pwrite(struct drm_device *dev, struct drm_gem_object *obj, |
56 | struct drm_i915_gem_pwrite *args, | |
57 | struct drm_file *file_priv); | |
be72615b | 58 | static void i915_gem_free_object_tail(struct drm_gem_object *obj); |
673a394b | 59 | |
31169714 CW |
60 | static LIST_HEAD(shrink_list); |
61 | static DEFINE_SPINLOCK(shrink_list_lock); | |
62 | ||
7d1c4804 CW |
63 | static inline bool |
64 | i915_gem_object_is_inactive(struct drm_i915_gem_object *obj_priv) | |
65 | { | |
66 | return obj_priv->gtt_space && | |
67 | !obj_priv->active && | |
68 | obj_priv->pin_count == 0; | |
69 | } | |
70 | ||
79e53945 JB |
71 | int i915_gem_do_init(struct drm_device *dev, unsigned long start, |
72 | unsigned long end) | |
673a394b EA |
73 | { |
74 | drm_i915_private_t *dev_priv = dev->dev_private; | |
673a394b | 75 | |
79e53945 JB |
76 | if (start >= end || |
77 | (start & (PAGE_SIZE - 1)) != 0 || | |
78 | (end & (PAGE_SIZE - 1)) != 0) { | |
673a394b EA |
79 | return -EINVAL; |
80 | } | |
81 | ||
79e53945 JB |
82 | drm_mm_init(&dev_priv->mm.gtt_space, start, |
83 | end - start); | |
673a394b | 84 | |
79e53945 JB |
85 | dev->gtt_total = (uint32_t) (end - start); |
86 | ||
87 | return 0; | |
88 | } | |
673a394b | 89 | |
79e53945 JB |
90 | int |
91 | i915_gem_init_ioctl(struct drm_device *dev, void *data, | |
92 | struct drm_file *file_priv) | |
93 | { | |
94 | struct drm_i915_gem_init *args = data; | |
95 | int ret; | |
96 | ||
97 | mutex_lock(&dev->struct_mutex); | |
98 | ret = i915_gem_do_init(dev, args->gtt_start, args->gtt_end); | |
673a394b EA |
99 | mutex_unlock(&dev->struct_mutex); |
100 | ||
79e53945 | 101 | return ret; |
673a394b EA |
102 | } |
103 | ||
5a125c3c EA |
104 | int |
105 | i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data, | |
106 | struct drm_file *file_priv) | |
107 | { | |
5a125c3c | 108 | struct drm_i915_gem_get_aperture *args = data; |
5a125c3c EA |
109 | |
110 | if (!(dev->driver->driver_features & DRIVER_GEM)) | |
111 | return -ENODEV; | |
112 | ||
113 | args->aper_size = dev->gtt_total; | |
2678d9d6 KP |
114 | args->aper_available_size = (args->aper_size - |
115 | atomic_read(&dev->pin_memory)); | |
5a125c3c EA |
116 | |
117 | return 0; | |
118 | } | |
119 | ||
673a394b EA |
120 | |
121 | /** | |
122 | * Creates a new mm object and returns a handle to it. | |
123 | */ | |
124 | int | |
125 | i915_gem_create_ioctl(struct drm_device *dev, void *data, | |
126 | struct drm_file *file_priv) | |
127 | { | |
128 | struct drm_i915_gem_create *args = data; | |
129 | struct drm_gem_object *obj; | |
a1a2d1d3 PP |
130 | int ret; |
131 | u32 handle; | |
673a394b EA |
132 | |
133 | args->size = roundup(args->size, PAGE_SIZE); | |
134 | ||
135 | /* Allocate the new object */ | |
ac52bc56 | 136 | obj = i915_gem_alloc_object(dev, args->size); |
673a394b EA |
137 | if (obj == NULL) |
138 | return -ENOMEM; | |
139 | ||
140 | ret = drm_gem_handle_create(file_priv, obj, &handle); | |
1dfd9754 CW |
141 | if (ret) { |
142 | drm_gem_object_unreference_unlocked(obj); | |
673a394b | 143 | return ret; |
1dfd9754 | 144 | } |
673a394b | 145 | |
1dfd9754 CW |
146 | /* Sink the floating reference from kref_init(handlecount) */ |
147 | drm_gem_object_handle_unreference_unlocked(obj); | |
673a394b | 148 | |
1dfd9754 | 149 | args->handle = handle; |
673a394b EA |
150 | return 0; |
151 | } | |
152 | ||
eb01459f EA |
153 | static inline int |
154 | fast_shmem_read(struct page **pages, | |
155 | loff_t page_base, int page_offset, | |
156 | char __user *data, | |
157 | int length) | |
158 | { | |
159 | char __iomem *vaddr; | |
2bc43b5c | 160 | int unwritten; |
eb01459f EA |
161 | |
162 | vaddr = kmap_atomic(pages[page_base >> PAGE_SHIFT], KM_USER0); | |
163 | if (vaddr == NULL) | |
164 | return -ENOMEM; | |
2bc43b5c | 165 | unwritten = __copy_to_user_inatomic(data, vaddr + page_offset, length); |
eb01459f EA |
166 | kunmap_atomic(vaddr, KM_USER0); |
167 | ||
2bc43b5c FM |
168 | if (unwritten) |
169 | return -EFAULT; | |
170 | ||
171 | return 0; | |
eb01459f EA |
172 | } |
173 | ||
280b713b EA |
174 | static int i915_gem_object_needs_bit17_swizzle(struct drm_gem_object *obj) |
175 | { | |
176 | drm_i915_private_t *dev_priv = obj->dev->dev_private; | |
23010e43 | 177 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
280b713b EA |
178 | |
179 | return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 && | |
180 | obj_priv->tiling_mode != I915_TILING_NONE; | |
181 | } | |
182 | ||
99a03df5 | 183 | static inline void |
40123c1f EA |
184 | slow_shmem_copy(struct page *dst_page, |
185 | int dst_offset, | |
186 | struct page *src_page, | |
187 | int src_offset, | |
188 | int length) | |
189 | { | |
190 | char *dst_vaddr, *src_vaddr; | |
191 | ||
99a03df5 CW |
192 | dst_vaddr = kmap(dst_page); |
193 | src_vaddr = kmap(src_page); | |
40123c1f EA |
194 | |
195 | memcpy(dst_vaddr + dst_offset, src_vaddr + src_offset, length); | |
196 | ||
99a03df5 CW |
197 | kunmap(src_page); |
198 | kunmap(dst_page); | |
40123c1f EA |
199 | } |
200 | ||
99a03df5 | 201 | static inline void |
280b713b EA |
202 | slow_shmem_bit17_copy(struct page *gpu_page, |
203 | int gpu_offset, | |
204 | struct page *cpu_page, | |
205 | int cpu_offset, | |
206 | int length, | |
207 | int is_read) | |
208 | { | |
209 | char *gpu_vaddr, *cpu_vaddr; | |
210 | ||
211 | /* Use the unswizzled path if this page isn't affected. */ | |
212 | if ((page_to_phys(gpu_page) & (1 << 17)) == 0) { | |
213 | if (is_read) | |
214 | return slow_shmem_copy(cpu_page, cpu_offset, | |
215 | gpu_page, gpu_offset, length); | |
216 | else | |
217 | return slow_shmem_copy(gpu_page, gpu_offset, | |
218 | cpu_page, cpu_offset, length); | |
219 | } | |
220 | ||
99a03df5 CW |
221 | gpu_vaddr = kmap(gpu_page); |
222 | cpu_vaddr = kmap(cpu_page); | |
280b713b EA |
223 | |
224 | /* Copy the data, XORing A6 with A17 (1). The user already knows he's | |
225 | * XORing with the other bits (A9 for Y, A9 and A10 for X) | |
226 | */ | |
227 | while (length > 0) { | |
228 | int cacheline_end = ALIGN(gpu_offset + 1, 64); | |
229 | int this_length = min(cacheline_end - gpu_offset, length); | |
230 | int swizzled_gpu_offset = gpu_offset ^ 64; | |
231 | ||
232 | if (is_read) { | |
233 | memcpy(cpu_vaddr + cpu_offset, | |
234 | gpu_vaddr + swizzled_gpu_offset, | |
235 | this_length); | |
236 | } else { | |
237 | memcpy(gpu_vaddr + swizzled_gpu_offset, | |
238 | cpu_vaddr + cpu_offset, | |
239 | this_length); | |
240 | } | |
241 | cpu_offset += this_length; | |
242 | gpu_offset += this_length; | |
243 | length -= this_length; | |
244 | } | |
245 | ||
99a03df5 CW |
246 | kunmap(cpu_page); |
247 | kunmap(gpu_page); | |
280b713b EA |
248 | } |
249 | ||
eb01459f EA |
250 | /** |
251 | * This is the fast shmem pread path, which attempts to copy_from_user directly | |
252 | * from the backing pages of the object to the user's address space. On a | |
253 | * fault, it fails so we can fall back to i915_gem_shmem_pwrite_slow(). | |
254 | */ | |
255 | static int | |
256 | i915_gem_shmem_pread_fast(struct drm_device *dev, struct drm_gem_object *obj, | |
257 | struct drm_i915_gem_pread *args, | |
258 | struct drm_file *file_priv) | |
259 | { | |
23010e43 | 260 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
eb01459f EA |
261 | ssize_t remain; |
262 | loff_t offset, page_base; | |
263 | char __user *user_data; | |
264 | int page_offset, page_length; | |
265 | int ret; | |
266 | ||
267 | user_data = (char __user *) (uintptr_t) args->data_ptr; | |
268 | remain = args->size; | |
269 | ||
270 | mutex_lock(&dev->struct_mutex); | |
271 | ||
4bdadb97 | 272 | ret = i915_gem_object_get_pages(obj, 0); |
eb01459f EA |
273 | if (ret != 0) |
274 | goto fail_unlock; | |
275 | ||
276 | ret = i915_gem_object_set_cpu_read_domain_range(obj, args->offset, | |
277 | args->size); | |
278 | if (ret != 0) | |
279 | goto fail_put_pages; | |
280 | ||
23010e43 | 281 | obj_priv = to_intel_bo(obj); |
eb01459f EA |
282 | offset = args->offset; |
283 | ||
284 | while (remain > 0) { | |
285 | /* Operation in this page | |
286 | * | |
287 | * page_base = page offset within aperture | |
288 | * page_offset = offset within page | |
289 | * page_length = bytes to copy for this page | |
290 | */ | |
291 | page_base = (offset & ~(PAGE_SIZE-1)); | |
292 | page_offset = offset & (PAGE_SIZE-1); | |
293 | page_length = remain; | |
294 | if ((page_offset + remain) > PAGE_SIZE) | |
295 | page_length = PAGE_SIZE - page_offset; | |
296 | ||
297 | ret = fast_shmem_read(obj_priv->pages, | |
298 | page_base, page_offset, | |
299 | user_data, page_length); | |
300 | if (ret) | |
301 | goto fail_put_pages; | |
302 | ||
303 | remain -= page_length; | |
304 | user_data += page_length; | |
305 | offset += page_length; | |
306 | } | |
307 | ||
308 | fail_put_pages: | |
309 | i915_gem_object_put_pages(obj); | |
310 | fail_unlock: | |
311 | mutex_unlock(&dev->struct_mutex); | |
312 | ||
313 | return ret; | |
314 | } | |
315 | ||
07f73f69 CW |
316 | static int |
317 | i915_gem_object_get_pages_or_evict(struct drm_gem_object *obj) | |
318 | { | |
319 | int ret; | |
320 | ||
4bdadb97 | 321 | ret = i915_gem_object_get_pages(obj, __GFP_NORETRY | __GFP_NOWARN); |
07f73f69 CW |
322 | |
323 | /* If we've insufficient memory to map in the pages, attempt | |
324 | * to make some space by throwing out some old buffers. | |
325 | */ | |
326 | if (ret == -ENOMEM) { | |
327 | struct drm_device *dev = obj->dev; | |
07f73f69 | 328 | |
0108a3ed DV |
329 | ret = i915_gem_evict_something(dev, obj->size, |
330 | i915_gem_get_gtt_alignment(obj)); | |
07f73f69 CW |
331 | if (ret) |
332 | return ret; | |
333 | ||
4bdadb97 | 334 | ret = i915_gem_object_get_pages(obj, 0); |
07f73f69 CW |
335 | } |
336 | ||
337 | return ret; | |
338 | } | |
339 | ||
eb01459f EA |
340 | /** |
341 | * This is the fallback shmem pread path, which allocates temporary storage | |
342 | * in kernel space to copy_to_user into outside of the struct_mutex, so we | |
343 | * can copy out of the object's backing pages while holding the struct mutex | |
344 | * and not take page faults. | |
345 | */ | |
346 | static int | |
347 | i915_gem_shmem_pread_slow(struct drm_device *dev, struct drm_gem_object *obj, | |
348 | struct drm_i915_gem_pread *args, | |
349 | struct drm_file *file_priv) | |
350 | { | |
23010e43 | 351 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
eb01459f EA |
352 | struct mm_struct *mm = current->mm; |
353 | struct page **user_pages; | |
354 | ssize_t remain; | |
355 | loff_t offset, pinned_pages, i; | |
356 | loff_t first_data_page, last_data_page, num_pages; | |
357 | int shmem_page_index, shmem_page_offset; | |
358 | int data_page_index, data_page_offset; | |
359 | int page_length; | |
360 | int ret; | |
361 | uint64_t data_ptr = args->data_ptr; | |
280b713b | 362 | int do_bit17_swizzling; |
eb01459f EA |
363 | |
364 | remain = args->size; | |
365 | ||
366 | /* Pin the user pages containing the data. We can't fault while | |
367 | * holding the struct mutex, yet we want to hold it while | |
368 | * dereferencing the user data. | |
369 | */ | |
370 | first_data_page = data_ptr / PAGE_SIZE; | |
371 | last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE; | |
372 | num_pages = last_data_page - first_data_page + 1; | |
373 | ||
8e7d2b2c | 374 | user_pages = drm_calloc_large(num_pages, sizeof(struct page *)); |
eb01459f EA |
375 | if (user_pages == NULL) |
376 | return -ENOMEM; | |
377 | ||
378 | down_read(&mm->mmap_sem); | |
379 | pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr, | |
e5e9ecde | 380 | num_pages, 1, 0, user_pages, NULL); |
eb01459f EA |
381 | up_read(&mm->mmap_sem); |
382 | if (pinned_pages < num_pages) { | |
383 | ret = -EFAULT; | |
384 | goto fail_put_user_pages; | |
385 | } | |
386 | ||
280b713b EA |
387 | do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj); |
388 | ||
eb01459f EA |
389 | mutex_lock(&dev->struct_mutex); |
390 | ||
07f73f69 CW |
391 | ret = i915_gem_object_get_pages_or_evict(obj); |
392 | if (ret) | |
eb01459f EA |
393 | goto fail_unlock; |
394 | ||
395 | ret = i915_gem_object_set_cpu_read_domain_range(obj, args->offset, | |
396 | args->size); | |
397 | if (ret != 0) | |
398 | goto fail_put_pages; | |
399 | ||
23010e43 | 400 | obj_priv = to_intel_bo(obj); |
eb01459f EA |
401 | offset = args->offset; |
402 | ||
403 | while (remain > 0) { | |
404 | /* Operation in this page | |
405 | * | |
406 | * shmem_page_index = page number within shmem file | |
407 | * shmem_page_offset = offset within page in shmem file | |
408 | * data_page_index = page number in get_user_pages return | |
409 | * data_page_offset = offset with data_page_index page. | |
410 | * page_length = bytes to copy for this page | |
411 | */ | |
412 | shmem_page_index = offset / PAGE_SIZE; | |
413 | shmem_page_offset = offset & ~PAGE_MASK; | |
414 | data_page_index = data_ptr / PAGE_SIZE - first_data_page; | |
415 | data_page_offset = data_ptr & ~PAGE_MASK; | |
416 | ||
417 | page_length = remain; | |
418 | if ((shmem_page_offset + page_length) > PAGE_SIZE) | |
419 | page_length = PAGE_SIZE - shmem_page_offset; | |
420 | if ((data_page_offset + page_length) > PAGE_SIZE) | |
421 | page_length = PAGE_SIZE - data_page_offset; | |
422 | ||
280b713b | 423 | if (do_bit17_swizzling) { |
99a03df5 | 424 | slow_shmem_bit17_copy(obj_priv->pages[shmem_page_index], |
280b713b | 425 | shmem_page_offset, |
99a03df5 CW |
426 | user_pages[data_page_index], |
427 | data_page_offset, | |
428 | page_length, | |
429 | 1); | |
430 | } else { | |
431 | slow_shmem_copy(user_pages[data_page_index], | |
432 | data_page_offset, | |
433 | obj_priv->pages[shmem_page_index], | |
434 | shmem_page_offset, | |
435 | page_length); | |
280b713b | 436 | } |
eb01459f EA |
437 | |
438 | remain -= page_length; | |
439 | data_ptr += page_length; | |
440 | offset += page_length; | |
441 | } | |
442 | ||
443 | fail_put_pages: | |
444 | i915_gem_object_put_pages(obj); | |
445 | fail_unlock: | |
446 | mutex_unlock(&dev->struct_mutex); | |
447 | fail_put_user_pages: | |
448 | for (i = 0; i < pinned_pages; i++) { | |
449 | SetPageDirty(user_pages[i]); | |
450 | page_cache_release(user_pages[i]); | |
451 | } | |
8e7d2b2c | 452 | drm_free_large(user_pages); |
eb01459f EA |
453 | |
454 | return ret; | |
455 | } | |
456 | ||
673a394b EA |
457 | /** |
458 | * Reads data from the object referenced by handle. | |
459 | * | |
460 | * On error, the contents of *data are undefined. | |
461 | */ | |
462 | int | |
463 | i915_gem_pread_ioctl(struct drm_device *dev, void *data, | |
464 | struct drm_file *file_priv) | |
465 | { | |
466 | struct drm_i915_gem_pread *args = data; | |
467 | struct drm_gem_object *obj; | |
468 | struct drm_i915_gem_object *obj_priv; | |
673a394b EA |
469 | int ret; |
470 | ||
471 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); | |
472 | if (obj == NULL) | |
bf79cb91 | 473 | return -ENOENT; |
23010e43 | 474 | obj_priv = to_intel_bo(obj); |
673a394b EA |
475 | |
476 | /* Bounds check source. | |
477 | * | |
478 | * XXX: This could use review for overflow issues... | |
479 | */ | |
480 | if (args->offset > obj->size || args->size > obj->size || | |
481 | args->offset + args->size > obj->size) { | |
bc9025bd | 482 | drm_gem_object_unreference_unlocked(obj); |
673a394b EA |
483 | return -EINVAL; |
484 | } | |
485 | ||
280b713b | 486 | if (i915_gem_object_needs_bit17_swizzle(obj)) { |
eb01459f | 487 | ret = i915_gem_shmem_pread_slow(dev, obj, args, file_priv); |
280b713b EA |
488 | } else { |
489 | ret = i915_gem_shmem_pread_fast(dev, obj, args, file_priv); | |
490 | if (ret != 0) | |
491 | ret = i915_gem_shmem_pread_slow(dev, obj, args, | |
492 | file_priv); | |
493 | } | |
673a394b | 494 | |
bc9025bd | 495 | drm_gem_object_unreference_unlocked(obj); |
673a394b | 496 | |
eb01459f | 497 | return ret; |
673a394b EA |
498 | } |
499 | ||
0839ccb8 KP |
500 | /* This is the fast write path which cannot handle |
501 | * page faults in the source data | |
9b7530cc | 502 | */ |
0839ccb8 KP |
503 | |
504 | static inline int | |
505 | fast_user_write(struct io_mapping *mapping, | |
506 | loff_t page_base, int page_offset, | |
507 | char __user *user_data, | |
508 | int length) | |
9b7530cc | 509 | { |
9b7530cc | 510 | char *vaddr_atomic; |
0839ccb8 | 511 | unsigned long unwritten; |
9b7530cc | 512 | |
fca3ec01 | 513 | vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base, KM_USER0); |
0839ccb8 KP |
514 | unwritten = __copy_from_user_inatomic_nocache(vaddr_atomic + page_offset, |
515 | user_data, length); | |
fca3ec01 | 516 | io_mapping_unmap_atomic(vaddr_atomic, KM_USER0); |
0839ccb8 KP |
517 | if (unwritten) |
518 | return -EFAULT; | |
519 | return 0; | |
520 | } | |
521 | ||
522 | /* Here's the write path which can sleep for | |
523 | * page faults | |
524 | */ | |
525 | ||
ab34c226 | 526 | static inline void |
3de09aa3 EA |
527 | slow_kernel_write(struct io_mapping *mapping, |
528 | loff_t gtt_base, int gtt_offset, | |
529 | struct page *user_page, int user_offset, | |
530 | int length) | |
0839ccb8 | 531 | { |
ab34c226 CW |
532 | char __iomem *dst_vaddr; |
533 | char *src_vaddr; | |
0839ccb8 | 534 | |
ab34c226 CW |
535 | dst_vaddr = io_mapping_map_wc(mapping, gtt_base); |
536 | src_vaddr = kmap(user_page); | |
537 | ||
538 | memcpy_toio(dst_vaddr + gtt_offset, | |
539 | src_vaddr + user_offset, | |
540 | length); | |
541 | ||
542 | kunmap(user_page); | |
543 | io_mapping_unmap(dst_vaddr); | |
9b7530cc LT |
544 | } |
545 | ||
40123c1f EA |
546 | static inline int |
547 | fast_shmem_write(struct page **pages, | |
548 | loff_t page_base, int page_offset, | |
549 | char __user *data, | |
550 | int length) | |
551 | { | |
552 | char __iomem *vaddr; | |
d0088775 | 553 | unsigned long unwritten; |
40123c1f EA |
554 | |
555 | vaddr = kmap_atomic(pages[page_base >> PAGE_SHIFT], KM_USER0); | |
556 | if (vaddr == NULL) | |
557 | return -ENOMEM; | |
d0088775 | 558 | unwritten = __copy_from_user_inatomic(vaddr + page_offset, data, length); |
40123c1f EA |
559 | kunmap_atomic(vaddr, KM_USER0); |
560 | ||
d0088775 DA |
561 | if (unwritten) |
562 | return -EFAULT; | |
40123c1f EA |
563 | return 0; |
564 | } | |
565 | ||
3de09aa3 EA |
566 | /** |
567 | * This is the fast pwrite path, where we copy the data directly from the | |
568 | * user into the GTT, uncached. | |
569 | */ | |
673a394b | 570 | static int |
3de09aa3 EA |
571 | i915_gem_gtt_pwrite_fast(struct drm_device *dev, struct drm_gem_object *obj, |
572 | struct drm_i915_gem_pwrite *args, | |
573 | struct drm_file *file_priv) | |
673a394b | 574 | { |
23010e43 | 575 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
0839ccb8 | 576 | drm_i915_private_t *dev_priv = dev->dev_private; |
673a394b | 577 | ssize_t remain; |
0839ccb8 | 578 | loff_t offset, page_base; |
673a394b | 579 | char __user *user_data; |
0839ccb8 KP |
580 | int page_offset, page_length; |
581 | int ret; | |
673a394b EA |
582 | |
583 | user_data = (char __user *) (uintptr_t) args->data_ptr; | |
584 | remain = args->size; | |
585 | if (!access_ok(VERIFY_READ, user_data, remain)) | |
586 | return -EFAULT; | |
587 | ||
588 | ||
589 | mutex_lock(&dev->struct_mutex); | |
590 | ret = i915_gem_object_pin(obj, 0); | |
591 | if (ret) { | |
592 | mutex_unlock(&dev->struct_mutex); | |
593 | return ret; | |
594 | } | |
2ef7eeaa | 595 | ret = i915_gem_object_set_to_gtt_domain(obj, 1); |
673a394b EA |
596 | if (ret) |
597 | goto fail; | |
598 | ||
23010e43 | 599 | obj_priv = to_intel_bo(obj); |
673a394b | 600 | offset = obj_priv->gtt_offset + args->offset; |
673a394b EA |
601 | |
602 | while (remain > 0) { | |
603 | /* Operation in this page | |
604 | * | |
0839ccb8 KP |
605 | * page_base = page offset within aperture |
606 | * page_offset = offset within page | |
607 | * page_length = bytes to copy for this page | |
673a394b | 608 | */ |
0839ccb8 KP |
609 | page_base = (offset & ~(PAGE_SIZE-1)); |
610 | page_offset = offset & (PAGE_SIZE-1); | |
611 | page_length = remain; | |
612 | if ((page_offset + remain) > PAGE_SIZE) | |
613 | page_length = PAGE_SIZE - page_offset; | |
614 | ||
615 | ret = fast_user_write (dev_priv->mm.gtt_mapping, page_base, | |
616 | page_offset, user_data, page_length); | |
617 | ||
618 | /* If we get a fault while copying data, then (presumably) our | |
3de09aa3 EA |
619 | * source page isn't available. Return the error and we'll |
620 | * retry in the slow path. | |
0839ccb8 | 621 | */ |
3de09aa3 EA |
622 | if (ret) |
623 | goto fail; | |
673a394b | 624 | |
0839ccb8 KP |
625 | remain -= page_length; |
626 | user_data += page_length; | |
627 | offset += page_length; | |
673a394b | 628 | } |
673a394b EA |
629 | |
630 | fail: | |
631 | i915_gem_object_unpin(obj); | |
632 | mutex_unlock(&dev->struct_mutex); | |
633 | ||
634 | return ret; | |
635 | } | |
636 | ||
3de09aa3 EA |
637 | /** |
638 | * This is the fallback GTT pwrite path, which uses get_user_pages to pin | |
639 | * the memory and maps it using kmap_atomic for copying. | |
640 | * | |
641 | * This code resulted in x11perf -rgb10text consuming about 10% more CPU | |
642 | * than using i915_gem_gtt_pwrite_fast on a G45 (32-bit). | |
643 | */ | |
3043c60c | 644 | static int |
3de09aa3 EA |
645 | i915_gem_gtt_pwrite_slow(struct drm_device *dev, struct drm_gem_object *obj, |
646 | struct drm_i915_gem_pwrite *args, | |
647 | struct drm_file *file_priv) | |
673a394b | 648 | { |
23010e43 | 649 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
3de09aa3 EA |
650 | drm_i915_private_t *dev_priv = dev->dev_private; |
651 | ssize_t remain; | |
652 | loff_t gtt_page_base, offset; | |
653 | loff_t first_data_page, last_data_page, num_pages; | |
654 | loff_t pinned_pages, i; | |
655 | struct page **user_pages; | |
656 | struct mm_struct *mm = current->mm; | |
657 | int gtt_page_offset, data_page_offset, data_page_index, page_length; | |
673a394b | 658 | int ret; |
3de09aa3 EA |
659 | uint64_t data_ptr = args->data_ptr; |
660 | ||
661 | remain = args->size; | |
662 | ||
663 | /* Pin the user pages containing the data. We can't fault while | |
664 | * holding the struct mutex, and all of the pwrite implementations | |
665 | * want to hold it while dereferencing the user data. | |
666 | */ | |
667 | first_data_page = data_ptr / PAGE_SIZE; | |
668 | last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE; | |
669 | num_pages = last_data_page - first_data_page + 1; | |
670 | ||
8e7d2b2c | 671 | user_pages = drm_calloc_large(num_pages, sizeof(struct page *)); |
3de09aa3 EA |
672 | if (user_pages == NULL) |
673 | return -ENOMEM; | |
674 | ||
675 | down_read(&mm->mmap_sem); | |
676 | pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr, | |
677 | num_pages, 0, 0, user_pages, NULL); | |
678 | up_read(&mm->mmap_sem); | |
679 | if (pinned_pages < num_pages) { | |
680 | ret = -EFAULT; | |
681 | goto out_unpin_pages; | |
682 | } | |
673a394b EA |
683 | |
684 | mutex_lock(&dev->struct_mutex); | |
3de09aa3 EA |
685 | ret = i915_gem_object_pin(obj, 0); |
686 | if (ret) | |
687 | goto out_unlock; | |
688 | ||
689 | ret = i915_gem_object_set_to_gtt_domain(obj, 1); | |
690 | if (ret) | |
691 | goto out_unpin_object; | |
692 | ||
23010e43 | 693 | obj_priv = to_intel_bo(obj); |
3de09aa3 EA |
694 | offset = obj_priv->gtt_offset + args->offset; |
695 | ||
696 | while (remain > 0) { | |
697 | /* Operation in this page | |
698 | * | |
699 | * gtt_page_base = page offset within aperture | |
700 | * gtt_page_offset = offset within page in aperture | |
701 | * data_page_index = page number in get_user_pages return | |
702 | * data_page_offset = offset with data_page_index page. | |
703 | * page_length = bytes to copy for this page | |
704 | */ | |
705 | gtt_page_base = offset & PAGE_MASK; | |
706 | gtt_page_offset = offset & ~PAGE_MASK; | |
707 | data_page_index = data_ptr / PAGE_SIZE - first_data_page; | |
708 | data_page_offset = data_ptr & ~PAGE_MASK; | |
709 | ||
710 | page_length = remain; | |
711 | if ((gtt_page_offset + page_length) > PAGE_SIZE) | |
712 | page_length = PAGE_SIZE - gtt_page_offset; | |
713 | if ((data_page_offset + page_length) > PAGE_SIZE) | |
714 | page_length = PAGE_SIZE - data_page_offset; | |
715 | ||
ab34c226 CW |
716 | slow_kernel_write(dev_priv->mm.gtt_mapping, |
717 | gtt_page_base, gtt_page_offset, | |
718 | user_pages[data_page_index], | |
719 | data_page_offset, | |
720 | page_length); | |
3de09aa3 EA |
721 | |
722 | remain -= page_length; | |
723 | offset += page_length; | |
724 | data_ptr += page_length; | |
725 | } | |
726 | ||
727 | out_unpin_object: | |
728 | i915_gem_object_unpin(obj); | |
729 | out_unlock: | |
730 | mutex_unlock(&dev->struct_mutex); | |
731 | out_unpin_pages: | |
732 | for (i = 0; i < pinned_pages; i++) | |
733 | page_cache_release(user_pages[i]); | |
8e7d2b2c | 734 | drm_free_large(user_pages); |
3de09aa3 EA |
735 | |
736 | return ret; | |
737 | } | |
738 | ||
40123c1f EA |
739 | /** |
740 | * This is the fast shmem pwrite path, which attempts to directly | |
741 | * copy_from_user into the kmapped pages backing the object. | |
742 | */ | |
3043c60c | 743 | static int |
40123c1f EA |
744 | i915_gem_shmem_pwrite_fast(struct drm_device *dev, struct drm_gem_object *obj, |
745 | struct drm_i915_gem_pwrite *args, | |
746 | struct drm_file *file_priv) | |
673a394b | 747 | { |
23010e43 | 748 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
40123c1f EA |
749 | ssize_t remain; |
750 | loff_t offset, page_base; | |
751 | char __user *user_data; | |
752 | int page_offset, page_length; | |
673a394b | 753 | int ret; |
40123c1f EA |
754 | |
755 | user_data = (char __user *) (uintptr_t) args->data_ptr; | |
756 | remain = args->size; | |
673a394b EA |
757 | |
758 | mutex_lock(&dev->struct_mutex); | |
759 | ||
4bdadb97 | 760 | ret = i915_gem_object_get_pages(obj, 0); |
40123c1f EA |
761 | if (ret != 0) |
762 | goto fail_unlock; | |
673a394b | 763 | |
e47c68e9 | 764 | ret = i915_gem_object_set_to_cpu_domain(obj, 1); |
40123c1f EA |
765 | if (ret != 0) |
766 | goto fail_put_pages; | |
767 | ||
23010e43 | 768 | obj_priv = to_intel_bo(obj); |
40123c1f EA |
769 | offset = args->offset; |
770 | obj_priv->dirty = 1; | |
771 | ||
772 | while (remain > 0) { | |
773 | /* Operation in this page | |
774 | * | |
775 | * page_base = page offset within aperture | |
776 | * page_offset = offset within page | |
777 | * page_length = bytes to copy for this page | |
778 | */ | |
779 | page_base = (offset & ~(PAGE_SIZE-1)); | |
780 | page_offset = offset & (PAGE_SIZE-1); | |
781 | page_length = remain; | |
782 | if ((page_offset + remain) > PAGE_SIZE) | |
783 | page_length = PAGE_SIZE - page_offset; | |
784 | ||
785 | ret = fast_shmem_write(obj_priv->pages, | |
786 | page_base, page_offset, | |
787 | user_data, page_length); | |
788 | if (ret) | |
789 | goto fail_put_pages; | |
790 | ||
791 | remain -= page_length; | |
792 | user_data += page_length; | |
793 | offset += page_length; | |
794 | } | |
795 | ||
796 | fail_put_pages: | |
797 | i915_gem_object_put_pages(obj); | |
798 | fail_unlock: | |
799 | mutex_unlock(&dev->struct_mutex); | |
800 | ||
801 | return ret; | |
802 | } | |
803 | ||
804 | /** | |
805 | * This is the fallback shmem pwrite path, which uses get_user_pages to pin | |
806 | * the memory and maps it using kmap_atomic for copying. | |
807 | * | |
808 | * This avoids taking mmap_sem for faulting on the user's address while the | |
809 | * struct_mutex is held. | |
810 | */ | |
811 | static int | |
812 | i915_gem_shmem_pwrite_slow(struct drm_device *dev, struct drm_gem_object *obj, | |
813 | struct drm_i915_gem_pwrite *args, | |
814 | struct drm_file *file_priv) | |
815 | { | |
23010e43 | 816 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
40123c1f EA |
817 | struct mm_struct *mm = current->mm; |
818 | struct page **user_pages; | |
819 | ssize_t remain; | |
820 | loff_t offset, pinned_pages, i; | |
821 | loff_t first_data_page, last_data_page, num_pages; | |
822 | int shmem_page_index, shmem_page_offset; | |
823 | int data_page_index, data_page_offset; | |
824 | int page_length; | |
825 | int ret; | |
826 | uint64_t data_ptr = args->data_ptr; | |
280b713b | 827 | int do_bit17_swizzling; |
40123c1f EA |
828 | |
829 | remain = args->size; | |
830 | ||
831 | /* Pin the user pages containing the data. We can't fault while | |
832 | * holding the struct mutex, and all of the pwrite implementations | |
833 | * want to hold it while dereferencing the user data. | |
834 | */ | |
835 | first_data_page = data_ptr / PAGE_SIZE; | |
836 | last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE; | |
837 | num_pages = last_data_page - first_data_page + 1; | |
838 | ||
8e7d2b2c | 839 | user_pages = drm_calloc_large(num_pages, sizeof(struct page *)); |
40123c1f EA |
840 | if (user_pages == NULL) |
841 | return -ENOMEM; | |
842 | ||
843 | down_read(&mm->mmap_sem); | |
844 | pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr, | |
845 | num_pages, 0, 0, user_pages, NULL); | |
846 | up_read(&mm->mmap_sem); | |
847 | if (pinned_pages < num_pages) { | |
848 | ret = -EFAULT; | |
849 | goto fail_put_user_pages; | |
673a394b EA |
850 | } |
851 | ||
280b713b EA |
852 | do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj); |
853 | ||
40123c1f EA |
854 | mutex_lock(&dev->struct_mutex); |
855 | ||
07f73f69 CW |
856 | ret = i915_gem_object_get_pages_or_evict(obj); |
857 | if (ret) | |
40123c1f EA |
858 | goto fail_unlock; |
859 | ||
860 | ret = i915_gem_object_set_to_cpu_domain(obj, 1); | |
861 | if (ret != 0) | |
862 | goto fail_put_pages; | |
863 | ||
23010e43 | 864 | obj_priv = to_intel_bo(obj); |
673a394b | 865 | offset = args->offset; |
40123c1f | 866 | obj_priv->dirty = 1; |
673a394b | 867 | |
40123c1f EA |
868 | while (remain > 0) { |
869 | /* Operation in this page | |
870 | * | |
871 | * shmem_page_index = page number within shmem file | |
872 | * shmem_page_offset = offset within page in shmem file | |
873 | * data_page_index = page number in get_user_pages return | |
874 | * data_page_offset = offset with data_page_index page. | |
875 | * page_length = bytes to copy for this page | |
876 | */ | |
877 | shmem_page_index = offset / PAGE_SIZE; | |
878 | shmem_page_offset = offset & ~PAGE_MASK; | |
879 | data_page_index = data_ptr / PAGE_SIZE - first_data_page; | |
880 | data_page_offset = data_ptr & ~PAGE_MASK; | |
881 | ||
882 | page_length = remain; | |
883 | if ((shmem_page_offset + page_length) > PAGE_SIZE) | |
884 | page_length = PAGE_SIZE - shmem_page_offset; | |
885 | if ((data_page_offset + page_length) > PAGE_SIZE) | |
886 | page_length = PAGE_SIZE - data_page_offset; | |
887 | ||
280b713b | 888 | if (do_bit17_swizzling) { |
99a03df5 | 889 | slow_shmem_bit17_copy(obj_priv->pages[shmem_page_index], |
280b713b EA |
890 | shmem_page_offset, |
891 | user_pages[data_page_index], | |
892 | data_page_offset, | |
99a03df5 CW |
893 | page_length, |
894 | 0); | |
895 | } else { | |
896 | slow_shmem_copy(obj_priv->pages[shmem_page_index], | |
897 | shmem_page_offset, | |
898 | user_pages[data_page_index], | |
899 | data_page_offset, | |
900 | page_length); | |
280b713b | 901 | } |
40123c1f EA |
902 | |
903 | remain -= page_length; | |
904 | data_ptr += page_length; | |
905 | offset += page_length; | |
673a394b EA |
906 | } |
907 | ||
40123c1f EA |
908 | fail_put_pages: |
909 | i915_gem_object_put_pages(obj); | |
910 | fail_unlock: | |
673a394b | 911 | mutex_unlock(&dev->struct_mutex); |
40123c1f EA |
912 | fail_put_user_pages: |
913 | for (i = 0; i < pinned_pages; i++) | |
914 | page_cache_release(user_pages[i]); | |
8e7d2b2c | 915 | drm_free_large(user_pages); |
673a394b | 916 | |
40123c1f | 917 | return ret; |
673a394b EA |
918 | } |
919 | ||
920 | /** | |
921 | * Writes data to the object referenced by handle. | |
922 | * | |
923 | * On error, the contents of the buffer that were to be modified are undefined. | |
924 | */ | |
925 | int | |
926 | i915_gem_pwrite_ioctl(struct drm_device *dev, void *data, | |
927 | struct drm_file *file_priv) | |
928 | { | |
929 | struct drm_i915_gem_pwrite *args = data; | |
930 | struct drm_gem_object *obj; | |
931 | struct drm_i915_gem_object *obj_priv; | |
932 | int ret = 0; | |
933 | ||
934 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); | |
935 | if (obj == NULL) | |
bf79cb91 | 936 | return -ENOENT; |
23010e43 | 937 | obj_priv = to_intel_bo(obj); |
673a394b EA |
938 | |
939 | /* Bounds check destination. | |
940 | * | |
941 | * XXX: This could use review for overflow issues... | |
942 | */ | |
943 | if (args->offset > obj->size || args->size > obj->size || | |
944 | args->offset + args->size > obj->size) { | |
bc9025bd | 945 | drm_gem_object_unreference_unlocked(obj); |
673a394b EA |
946 | return -EINVAL; |
947 | } | |
948 | ||
949 | /* We can only do the GTT pwrite on untiled buffers, as otherwise | |
950 | * it would end up going through the fenced access, and we'll get | |
951 | * different detiling behavior between reading and writing. | |
952 | * pread/pwrite currently are reading and writing from the CPU | |
953 | * perspective, requiring manual detiling by the client. | |
954 | */ | |
71acb5eb DA |
955 | if (obj_priv->phys_obj) |
956 | ret = i915_gem_phys_pwrite(dev, obj, args, file_priv); | |
957 | else if (obj_priv->tiling_mode == I915_TILING_NONE && | |
9b8c4a0b CW |
958 | dev->gtt_total != 0 && |
959 | obj->write_domain != I915_GEM_DOMAIN_CPU) { | |
3de09aa3 EA |
960 | ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file_priv); |
961 | if (ret == -EFAULT) { | |
962 | ret = i915_gem_gtt_pwrite_slow(dev, obj, args, | |
963 | file_priv); | |
964 | } | |
280b713b EA |
965 | } else if (i915_gem_object_needs_bit17_swizzle(obj)) { |
966 | ret = i915_gem_shmem_pwrite_slow(dev, obj, args, file_priv); | |
40123c1f EA |
967 | } else { |
968 | ret = i915_gem_shmem_pwrite_fast(dev, obj, args, file_priv); | |
969 | if (ret == -EFAULT) { | |
970 | ret = i915_gem_shmem_pwrite_slow(dev, obj, args, | |
971 | file_priv); | |
972 | } | |
973 | } | |
673a394b EA |
974 | |
975 | #if WATCH_PWRITE | |
976 | if (ret) | |
977 | DRM_INFO("pwrite failed %d\n", ret); | |
978 | #endif | |
979 | ||
bc9025bd | 980 | drm_gem_object_unreference_unlocked(obj); |
673a394b EA |
981 | |
982 | return ret; | |
983 | } | |
984 | ||
985 | /** | |
2ef7eeaa EA |
986 | * Called when user space prepares to use an object with the CPU, either |
987 | * through the mmap ioctl's mapping or a GTT mapping. | |
673a394b EA |
988 | */ |
989 | int | |
990 | i915_gem_set_domain_ioctl(struct drm_device *dev, void *data, | |
991 | struct drm_file *file_priv) | |
992 | { | |
a09ba7fa | 993 | struct drm_i915_private *dev_priv = dev->dev_private; |
673a394b EA |
994 | struct drm_i915_gem_set_domain *args = data; |
995 | struct drm_gem_object *obj; | |
652c393a | 996 | struct drm_i915_gem_object *obj_priv; |
2ef7eeaa EA |
997 | uint32_t read_domains = args->read_domains; |
998 | uint32_t write_domain = args->write_domain; | |
673a394b EA |
999 | int ret; |
1000 | ||
1001 | if (!(dev->driver->driver_features & DRIVER_GEM)) | |
1002 | return -ENODEV; | |
1003 | ||
2ef7eeaa | 1004 | /* Only handle setting domains to types used by the CPU. */ |
21d509e3 | 1005 | if (write_domain & I915_GEM_GPU_DOMAINS) |
2ef7eeaa EA |
1006 | return -EINVAL; |
1007 | ||
21d509e3 | 1008 | if (read_domains & I915_GEM_GPU_DOMAINS) |
2ef7eeaa EA |
1009 | return -EINVAL; |
1010 | ||
1011 | /* Having something in the write domain implies it's in the read | |
1012 | * domain, and only that read domain. Enforce that in the request. | |
1013 | */ | |
1014 | if (write_domain != 0 && read_domains != write_domain) | |
1015 | return -EINVAL; | |
1016 | ||
673a394b EA |
1017 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); |
1018 | if (obj == NULL) | |
bf79cb91 | 1019 | return -ENOENT; |
23010e43 | 1020 | obj_priv = to_intel_bo(obj); |
673a394b EA |
1021 | |
1022 | mutex_lock(&dev->struct_mutex); | |
652c393a JB |
1023 | |
1024 | intel_mark_busy(dev, obj); | |
1025 | ||
673a394b | 1026 | #if WATCH_BUF |
cfd43c02 | 1027 | DRM_INFO("set_domain_ioctl %p(%zd), %08x %08x\n", |
2ef7eeaa | 1028 | obj, obj->size, read_domains, write_domain); |
673a394b | 1029 | #endif |
2ef7eeaa EA |
1030 | if (read_domains & I915_GEM_DOMAIN_GTT) { |
1031 | ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0); | |
02354392 | 1032 | |
a09ba7fa EA |
1033 | /* Update the LRU on the fence for the CPU access that's |
1034 | * about to occur. | |
1035 | */ | |
1036 | if (obj_priv->fence_reg != I915_FENCE_REG_NONE) { | |
007cc8ac DV |
1037 | struct drm_i915_fence_reg *reg = |
1038 | &dev_priv->fence_regs[obj_priv->fence_reg]; | |
1039 | list_move_tail(®->lru_list, | |
a09ba7fa EA |
1040 | &dev_priv->mm.fence_list); |
1041 | } | |
1042 | ||
02354392 EA |
1043 | /* Silently promote "you're not bound, there was nothing to do" |
1044 | * to success, since the client was just asking us to | |
1045 | * make sure everything was done. | |
1046 | */ | |
1047 | if (ret == -EINVAL) | |
1048 | ret = 0; | |
2ef7eeaa | 1049 | } else { |
e47c68e9 | 1050 | ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0); |
2ef7eeaa EA |
1051 | } |
1052 | ||
7d1c4804 CW |
1053 | |
1054 | /* Maintain LRU order of "inactive" objects */ | |
1055 | if (ret == 0 && i915_gem_object_is_inactive(obj_priv)) | |
1056 | list_move_tail(&obj_priv->list, &dev_priv->mm.inactive_list); | |
1057 | ||
673a394b EA |
1058 | drm_gem_object_unreference(obj); |
1059 | mutex_unlock(&dev->struct_mutex); | |
1060 | return ret; | |
1061 | } | |
1062 | ||
1063 | /** | |
1064 | * Called when user space has done writes to this buffer | |
1065 | */ | |
1066 | int | |
1067 | i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data, | |
1068 | struct drm_file *file_priv) | |
1069 | { | |
1070 | struct drm_i915_gem_sw_finish *args = data; | |
1071 | struct drm_gem_object *obj; | |
1072 | struct drm_i915_gem_object *obj_priv; | |
1073 | int ret = 0; | |
1074 | ||
1075 | if (!(dev->driver->driver_features & DRIVER_GEM)) | |
1076 | return -ENODEV; | |
1077 | ||
1078 | mutex_lock(&dev->struct_mutex); | |
1079 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); | |
1080 | if (obj == NULL) { | |
1081 | mutex_unlock(&dev->struct_mutex); | |
bf79cb91 | 1082 | return -ENOENT; |
673a394b EA |
1083 | } |
1084 | ||
1085 | #if WATCH_BUF | |
cfd43c02 | 1086 | DRM_INFO("%s: sw_finish %d (%p %zd)\n", |
673a394b EA |
1087 | __func__, args->handle, obj, obj->size); |
1088 | #endif | |
23010e43 | 1089 | obj_priv = to_intel_bo(obj); |
673a394b EA |
1090 | |
1091 | /* Pinned buffers may be scanout, so flush the cache */ | |
e47c68e9 EA |
1092 | if (obj_priv->pin_count) |
1093 | i915_gem_object_flush_cpu_write_domain(obj); | |
1094 | ||
673a394b EA |
1095 | drm_gem_object_unreference(obj); |
1096 | mutex_unlock(&dev->struct_mutex); | |
1097 | return ret; | |
1098 | } | |
1099 | ||
1100 | /** | |
1101 | * Maps the contents of an object, returning the address it is mapped | |
1102 | * into. | |
1103 | * | |
1104 | * While the mapping holds a reference on the contents of the object, it doesn't | |
1105 | * imply a ref on the object itself. | |
1106 | */ | |
1107 | int | |
1108 | i915_gem_mmap_ioctl(struct drm_device *dev, void *data, | |
1109 | struct drm_file *file_priv) | |
1110 | { | |
1111 | struct drm_i915_gem_mmap *args = data; | |
1112 | struct drm_gem_object *obj; | |
1113 | loff_t offset; | |
1114 | unsigned long addr; | |
1115 | ||
1116 | if (!(dev->driver->driver_features & DRIVER_GEM)) | |
1117 | return -ENODEV; | |
1118 | ||
1119 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); | |
1120 | if (obj == NULL) | |
bf79cb91 | 1121 | return -ENOENT; |
673a394b EA |
1122 | |
1123 | offset = args->offset; | |
1124 | ||
1125 | down_write(¤t->mm->mmap_sem); | |
1126 | addr = do_mmap(obj->filp, 0, args->size, | |
1127 | PROT_READ | PROT_WRITE, MAP_SHARED, | |
1128 | args->offset); | |
1129 | up_write(¤t->mm->mmap_sem); | |
bc9025bd | 1130 | drm_gem_object_unreference_unlocked(obj); |
673a394b EA |
1131 | if (IS_ERR((void *)addr)) |
1132 | return addr; | |
1133 | ||
1134 | args->addr_ptr = (uint64_t) addr; | |
1135 | ||
1136 | return 0; | |
1137 | } | |
1138 | ||
de151cf6 JB |
1139 | /** |
1140 | * i915_gem_fault - fault a page into the GTT | |
1141 | * vma: VMA in question | |
1142 | * vmf: fault info | |
1143 | * | |
1144 | * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped | |
1145 | * from userspace. The fault handler takes care of binding the object to | |
1146 | * the GTT (if needed), allocating and programming a fence register (again, | |
1147 | * only if needed based on whether the old reg is still valid or the object | |
1148 | * is tiled) and inserting a new PTE into the faulting process. | |
1149 | * | |
1150 | * Note that the faulting process may involve evicting existing objects | |
1151 | * from the GTT and/or fence registers to make room. So performance may | |
1152 | * suffer if the GTT working set is large or there are few fence registers | |
1153 | * left. | |
1154 | */ | |
1155 | int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf) | |
1156 | { | |
1157 | struct drm_gem_object *obj = vma->vm_private_data; | |
1158 | struct drm_device *dev = obj->dev; | |
7d1c4804 | 1159 | drm_i915_private_t *dev_priv = dev->dev_private; |
23010e43 | 1160 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
de151cf6 JB |
1161 | pgoff_t page_offset; |
1162 | unsigned long pfn; | |
1163 | int ret = 0; | |
0f973f27 | 1164 | bool write = !!(vmf->flags & FAULT_FLAG_WRITE); |
de151cf6 JB |
1165 | |
1166 | /* We don't use vmf->pgoff since that has the fake offset */ | |
1167 | page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >> | |
1168 | PAGE_SHIFT; | |
1169 | ||
1170 | /* Now bind it into the GTT if needed */ | |
1171 | mutex_lock(&dev->struct_mutex); | |
1172 | if (!obj_priv->gtt_space) { | |
e67b8ce1 | 1173 | ret = i915_gem_object_bind_to_gtt(obj, 0); |
c715089f CW |
1174 | if (ret) |
1175 | goto unlock; | |
07f4f3e8 | 1176 | |
07f4f3e8 | 1177 | ret = i915_gem_object_set_to_gtt_domain(obj, write); |
c715089f CW |
1178 | if (ret) |
1179 | goto unlock; | |
de151cf6 JB |
1180 | } |
1181 | ||
1182 | /* Need a new fence register? */ | |
a09ba7fa | 1183 | if (obj_priv->tiling_mode != I915_TILING_NONE) { |
8c4b8c3f | 1184 | ret = i915_gem_object_get_fence_reg(obj); |
c715089f CW |
1185 | if (ret) |
1186 | goto unlock; | |
d9ddcb96 | 1187 | } |
de151cf6 | 1188 | |
7d1c4804 CW |
1189 | if (i915_gem_object_is_inactive(obj_priv)) |
1190 | list_move_tail(&obj_priv->list, &dev_priv->mm.inactive_list); | |
1191 | ||
de151cf6 JB |
1192 | pfn = ((dev->agp->base + obj_priv->gtt_offset) >> PAGE_SHIFT) + |
1193 | page_offset; | |
1194 | ||
1195 | /* Finally, remap it using the new GTT offset */ | |
1196 | ret = vm_insert_pfn(vma, (unsigned long)vmf->virtual_address, pfn); | |
c715089f | 1197 | unlock: |
de151cf6 JB |
1198 | mutex_unlock(&dev->struct_mutex); |
1199 | ||
1200 | switch (ret) { | |
c715089f CW |
1201 | case 0: |
1202 | case -ERESTARTSYS: | |
1203 | return VM_FAULT_NOPAGE; | |
de151cf6 JB |
1204 | case -ENOMEM: |
1205 | case -EAGAIN: | |
1206 | return VM_FAULT_OOM; | |
de151cf6 | 1207 | default: |
c715089f | 1208 | return VM_FAULT_SIGBUS; |
de151cf6 JB |
1209 | } |
1210 | } | |
1211 | ||
1212 | /** | |
1213 | * i915_gem_create_mmap_offset - create a fake mmap offset for an object | |
1214 | * @obj: obj in question | |
1215 | * | |
1216 | * GEM memory mapping works by handing back to userspace a fake mmap offset | |
1217 | * it can use in a subsequent mmap(2) call. The DRM core code then looks | |
1218 | * up the object based on the offset and sets up the various memory mapping | |
1219 | * structures. | |
1220 | * | |
1221 | * This routine allocates and attaches a fake offset for @obj. | |
1222 | */ | |
1223 | static int | |
1224 | i915_gem_create_mmap_offset(struct drm_gem_object *obj) | |
1225 | { | |
1226 | struct drm_device *dev = obj->dev; | |
1227 | struct drm_gem_mm *mm = dev->mm_private; | |
23010e43 | 1228 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
de151cf6 | 1229 | struct drm_map_list *list; |
f77d390c | 1230 | struct drm_local_map *map; |
de151cf6 JB |
1231 | int ret = 0; |
1232 | ||
1233 | /* Set the object up for mmap'ing */ | |
1234 | list = &obj->map_list; | |
9a298b2a | 1235 | list->map = kzalloc(sizeof(struct drm_map_list), GFP_KERNEL); |
de151cf6 JB |
1236 | if (!list->map) |
1237 | return -ENOMEM; | |
1238 | ||
1239 | map = list->map; | |
1240 | map->type = _DRM_GEM; | |
1241 | map->size = obj->size; | |
1242 | map->handle = obj; | |
1243 | ||
1244 | /* Get a DRM GEM mmap offset allocated... */ | |
1245 | list->file_offset_node = drm_mm_search_free(&mm->offset_manager, | |
1246 | obj->size / PAGE_SIZE, 0, 0); | |
1247 | if (!list->file_offset_node) { | |
1248 | DRM_ERROR("failed to allocate offset for bo %d\n", obj->name); | |
1249 | ret = -ENOMEM; | |
1250 | goto out_free_list; | |
1251 | } | |
1252 | ||
1253 | list->file_offset_node = drm_mm_get_block(list->file_offset_node, | |
1254 | obj->size / PAGE_SIZE, 0); | |
1255 | if (!list->file_offset_node) { | |
1256 | ret = -ENOMEM; | |
1257 | goto out_free_list; | |
1258 | } | |
1259 | ||
1260 | list->hash.key = list->file_offset_node->start; | |
1261 | if (drm_ht_insert_item(&mm->offset_hash, &list->hash)) { | |
1262 | DRM_ERROR("failed to add to map hash\n"); | |
5618ca6a | 1263 | ret = -ENOMEM; |
de151cf6 JB |
1264 | goto out_free_mm; |
1265 | } | |
1266 | ||
1267 | /* By now we should be all set, any drm_mmap request on the offset | |
1268 | * below will get to our mmap & fault handler */ | |
1269 | obj_priv->mmap_offset = ((uint64_t) list->hash.key) << PAGE_SHIFT; | |
1270 | ||
1271 | return 0; | |
1272 | ||
1273 | out_free_mm: | |
1274 | drm_mm_put_block(list->file_offset_node); | |
1275 | out_free_list: | |
9a298b2a | 1276 | kfree(list->map); |
de151cf6 JB |
1277 | |
1278 | return ret; | |
1279 | } | |
1280 | ||
901782b2 CW |
1281 | /** |
1282 | * i915_gem_release_mmap - remove physical page mappings | |
1283 | * @obj: obj in question | |
1284 | * | |
af901ca1 | 1285 | * Preserve the reservation of the mmapping with the DRM core code, but |
901782b2 CW |
1286 | * relinquish ownership of the pages back to the system. |
1287 | * | |
1288 | * It is vital that we remove the page mapping if we have mapped a tiled | |
1289 | * object through the GTT and then lose the fence register due to | |
1290 | * resource pressure. Similarly if the object has been moved out of the | |
1291 | * aperture, than pages mapped into userspace must be revoked. Removing the | |
1292 | * mapping will then trigger a page fault on the next user access, allowing | |
1293 | * fixup by i915_gem_fault(). | |
1294 | */ | |
d05ca301 | 1295 | void |
901782b2 CW |
1296 | i915_gem_release_mmap(struct drm_gem_object *obj) |
1297 | { | |
1298 | struct drm_device *dev = obj->dev; | |
23010e43 | 1299 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
901782b2 CW |
1300 | |
1301 | if (dev->dev_mapping) | |
1302 | unmap_mapping_range(dev->dev_mapping, | |
1303 | obj_priv->mmap_offset, obj->size, 1); | |
1304 | } | |
1305 | ||
ab00b3e5 JB |
1306 | static void |
1307 | i915_gem_free_mmap_offset(struct drm_gem_object *obj) | |
1308 | { | |
1309 | struct drm_device *dev = obj->dev; | |
23010e43 | 1310 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
ab00b3e5 JB |
1311 | struct drm_gem_mm *mm = dev->mm_private; |
1312 | struct drm_map_list *list; | |
1313 | ||
1314 | list = &obj->map_list; | |
1315 | drm_ht_remove_item(&mm->offset_hash, &list->hash); | |
1316 | ||
1317 | if (list->file_offset_node) { | |
1318 | drm_mm_put_block(list->file_offset_node); | |
1319 | list->file_offset_node = NULL; | |
1320 | } | |
1321 | ||
1322 | if (list->map) { | |
9a298b2a | 1323 | kfree(list->map); |
ab00b3e5 JB |
1324 | list->map = NULL; |
1325 | } | |
1326 | ||
1327 | obj_priv->mmap_offset = 0; | |
1328 | } | |
1329 | ||
de151cf6 JB |
1330 | /** |
1331 | * i915_gem_get_gtt_alignment - return required GTT alignment for an object | |
1332 | * @obj: object to check | |
1333 | * | |
1334 | * Return the required GTT alignment for an object, taking into account | |
1335 | * potential fence register mapping if needed. | |
1336 | */ | |
1337 | static uint32_t | |
1338 | i915_gem_get_gtt_alignment(struct drm_gem_object *obj) | |
1339 | { | |
1340 | struct drm_device *dev = obj->dev; | |
23010e43 | 1341 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
de151cf6 JB |
1342 | int start, i; |
1343 | ||
1344 | /* | |
1345 | * Minimum alignment is 4k (GTT page size), but might be greater | |
1346 | * if a fence register is needed for the object. | |
1347 | */ | |
1348 | if (IS_I965G(dev) || obj_priv->tiling_mode == I915_TILING_NONE) | |
1349 | return 4096; | |
1350 | ||
1351 | /* | |
1352 | * Previous chips need to be aligned to the size of the smallest | |
1353 | * fence register that can contain the object. | |
1354 | */ | |
1355 | if (IS_I9XX(dev)) | |
1356 | start = 1024*1024; | |
1357 | else | |
1358 | start = 512*1024; | |
1359 | ||
1360 | for (i = start; i < obj->size; i <<= 1) | |
1361 | ; | |
1362 | ||
1363 | return i; | |
1364 | } | |
1365 | ||
1366 | /** | |
1367 | * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing | |
1368 | * @dev: DRM device | |
1369 | * @data: GTT mapping ioctl data | |
1370 | * @file_priv: GEM object info | |
1371 | * | |
1372 | * Simply returns the fake offset to userspace so it can mmap it. | |
1373 | * The mmap call will end up in drm_gem_mmap(), which will set things | |
1374 | * up so we can get faults in the handler above. | |
1375 | * | |
1376 | * The fault handler will take care of binding the object into the GTT | |
1377 | * (since it may have been evicted to make room for something), allocating | |
1378 | * a fence register, and mapping the appropriate aperture address into | |
1379 | * userspace. | |
1380 | */ | |
1381 | int | |
1382 | i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data, | |
1383 | struct drm_file *file_priv) | |
1384 | { | |
1385 | struct drm_i915_gem_mmap_gtt *args = data; | |
de151cf6 JB |
1386 | struct drm_gem_object *obj; |
1387 | struct drm_i915_gem_object *obj_priv; | |
1388 | int ret; | |
1389 | ||
1390 | if (!(dev->driver->driver_features & DRIVER_GEM)) | |
1391 | return -ENODEV; | |
1392 | ||
1393 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); | |
1394 | if (obj == NULL) | |
bf79cb91 | 1395 | return -ENOENT; |
de151cf6 JB |
1396 | |
1397 | mutex_lock(&dev->struct_mutex); | |
1398 | ||
23010e43 | 1399 | obj_priv = to_intel_bo(obj); |
de151cf6 | 1400 | |
ab18282d CW |
1401 | if (obj_priv->madv != I915_MADV_WILLNEED) { |
1402 | DRM_ERROR("Attempting to mmap a purgeable buffer\n"); | |
1403 | drm_gem_object_unreference(obj); | |
1404 | mutex_unlock(&dev->struct_mutex); | |
1405 | return -EINVAL; | |
1406 | } | |
1407 | ||
1408 | ||
de151cf6 JB |
1409 | if (!obj_priv->mmap_offset) { |
1410 | ret = i915_gem_create_mmap_offset(obj); | |
13af1062 CW |
1411 | if (ret) { |
1412 | drm_gem_object_unreference(obj); | |
1413 | mutex_unlock(&dev->struct_mutex); | |
de151cf6 | 1414 | return ret; |
13af1062 | 1415 | } |
de151cf6 JB |
1416 | } |
1417 | ||
1418 | args->offset = obj_priv->mmap_offset; | |
1419 | ||
de151cf6 JB |
1420 | /* |
1421 | * Pull it into the GTT so that we have a page list (makes the | |
1422 | * initial fault faster and any subsequent flushing possible). | |
1423 | */ | |
1424 | if (!obj_priv->agp_mem) { | |
e67b8ce1 | 1425 | ret = i915_gem_object_bind_to_gtt(obj, 0); |
de151cf6 JB |
1426 | if (ret) { |
1427 | drm_gem_object_unreference(obj); | |
1428 | mutex_unlock(&dev->struct_mutex); | |
1429 | return ret; | |
1430 | } | |
de151cf6 JB |
1431 | } |
1432 | ||
1433 | drm_gem_object_unreference(obj); | |
1434 | mutex_unlock(&dev->struct_mutex); | |
1435 | ||
1436 | return 0; | |
1437 | } | |
1438 | ||
6911a9b8 | 1439 | void |
856fa198 | 1440 | i915_gem_object_put_pages(struct drm_gem_object *obj) |
673a394b | 1441 | { |
23010e43 | 1442 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
673a394b EA |
1443 | int page_count = obj->size / PAGE_SIZE; |
1444 | int i; | |
1445 | ||
856fa198 | 1446 | BUG_ON(obj_priv->pages_refcount == 0); |
bb6baf76 | 1447 | BUG_ON(obj_priv->madv == __I915_MADV_PURGED); |
673a394b | 1448 | |
856fa198 EA |
1449 | if (--obj_priv->pages_refcount != 0) |
1450 | return; | |
673a394b | 1451 | |
280b713b EA |
1452 | if (obj_priv->tiling_mode != I915_TILING_NONE) |
1453 | i915_gem_object_save_bit_17_swizzle(obj); | |
1454 | ||
3ef94daa | 1455 | if (obj_priv->madv == I915_MADV_DONTNEED) |
13a05fd9 | 1456 | obj_priv->dirty = 0; |
3ef94daa CW |
1457 | |
1458 | for (i = 0; i < page_count; i++) { | |
3ef94daa CW |
1459 | if (obj_priv->dirty) |
1460 | set_page_dirty(obj_priv->pages[i]); | |
1461 | ||
1462 | if (obj_priv->madv == I915_MADV_WILLNEED) | |
856fa198 | 1463 | mark_page_accessed(obj_priv->pages[i]); |
3ef94daa CW |
1464 | |
1465 | page_cache_release(obj_priv->pages[i]); | |
1466 | } | |
673a394b EA |
1467 | obj_priv->dirty = 0; |
1468 | ||
8e7d2b2c | 1469 | drm_free_large(obj_priv->pages); |
856fa198 | 1470 | obj_priv->pages = NULL; |
673a394b EA |
1471 | } |
1472 | ||
e35a41de | 1473 | static uint32_t |
a6910434 DV |
1474 | i915_gem_next_request_seqno(struct drm_device *dev, |
1475 | struct intel_ring_buffer *ring) | |
e35a41de DV |
1476 | { |
1477 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1478 | ||
a6910434 DV |
1479 | ring->outstanding_lazy_request = true; |
1480 | ||
e35a41de DV |
1481 | return dev_priv->next_seqno; |
1482 | } | |
1483 | ||
673a394b | 1484 | static void |
617dbe27 | 1485 | i915_gem_object_move_to_active(struct drm_gem_object *obj, |
852835f3 | 1486 | struct intel_ring_buffer *ring) |
673a394b EA |
1487 | { |
1488 | struct drm_device *dev = obj->dev; | |
23010e43 | 1489 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
617dbe27 DV |
1490 | uint32_t seqno = i915_gem_next_request_seqno(dev, ring); |
1491 | ||
852835f3 ZN |
1492 | BUG_ON(ring == NULL); |
1493 | obj_priv->ring = ring; | |
673a394b EA |
1494 | |
1495 | /* Add a reference if we're newly entering the active list. */ | |
1496 | if (!obj_priv->active) { | |
1497 | drm_gem_object_reference(obj); | |
1498 | obj_priv->active = 1; | |
1499 | } | |
e35a41de | 1500 | |
673a394b | 1501 | /* Move from whatever list we were on to the tail of execution. */ |
852835f3 | 1502 | list_move_tail(&obj_priv->list, &ring->active_list); |
ce44b0ea | 1503 | obj_priv->last_rendering_seqno = seqno; |
673a394b EA |
1504 | } |
1505 | ||
ce44b0ea EA |
1506 | static void |
1507 | i915_gem_object_move_to_flushing(struct drm_gem_object *obj) | |
1508 | { | |
1509 | struct drm_device *dev = obj->dev; | |
1510 | drm_i915_private_t *dev_priv = dev->dev_private; | |
23010e43 | 1511 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
ce44b0ea EA |
1512 | |
1513 | BUG_ON(!obj_priv->active); | |
1514 | list_move_tail(&obj_priv->list, &dev_priv->mm.flushing_list); | |
1515 | obj_priv->last_rendering_seqno = 0; | |
1516 | } | |
673a394b | 1517 | |
963b4836 CW |
1518 | /* Immediately discard the backing storage */ |
1519 | static void | |
1520 | i915_gem_object_truncate(struct drm_gem_object *obj) | |
1521 | { | |
23010e43 | 1522 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
bb6baf76 | 1523 | struct inode *inode; |
963b4836 | 1524 | |
ae9fed6b CW |
1525 | /* Our goal here is to return as much of the memory as |
1526 | * is possible back to the system as we are called from OOM. | |
1527 | * To do this we must instruct the shmfs to drop all of its | |
1528 | * backing pages, *now*. Here we mirror the actions taken | |
1529 | * when by shmem_delete_inode() to release the backing store. | |
1530 | */ | |
bb6baf76 | 1531 | inode = obj->filp->f_path.dentry->d_inode; |
ae9fed6b CW |
1532 | truncate_inode_pages(inode->i_mapping, 0); |
1533 | if (inode->i_op->truncate_range) | |
1534 | inode->i_op->truncate_range(inode, 0, (loff_t)-1); | |
bb6baf76 CW |
1535 | |
1536 | obj_priv->madv = __I915_MADV_PURGED; | |
963b4836 CW |
1537 | } |
1538 | ||
1539 | static inline int | |
1540 | i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj_priv) | |
1541 | { | |
1542 | return obj_priv->madv == I915_MADV_DONTNEED; | |
1543 | } | |
1544 | ||
673a394b EA |
1545 | static void |
1546 | i915_gem_object_move_to_inactive(struct drm_gem_object *obj) | |
1547 | { | |
1548 | struct drm_device *dev = obj->dev; | |
1549 | drm_i915_private_t *dev_priv = dev->dev_private; | |
23010e43 | 1550 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
673a394b EA |
1551 | |
1552 | i915_verify_inactive(dev, __FILE__, __LINE__); | |
1553 | if (obj_priv->pin_count != 0) | |
1554 | list_del_init(&obj_priv->list); | |
1555 | else | |
1556 | list_move_tail(&obj_priv->list, &dev_priv->mm.inactive_list); | |
1557 | ||
99fcb766 DV |
1558 | BUG_ON(!list_empty(&obj_priv->gpu_write_list)); |
1559 | ||
ce44b0ea | 1560 | obj_priv->last_rendering_seqno = 0; |
852835f3 | 1561 | obj_priv->ring = NULL; |
673a394b EA |
1562 | if (obj_priv->active) { |
1563 | obj_priv->active = 0; | |
1564 | drm_gem_object_unreference(obj); | |
1565 | } | |
1566 | i915_verify_inactive(dev, __FILE__, __LINE__); | |
1567 | } | |
1568 | ||
8a1a49f9 | 1569 | void |
63560396 | 1570 | i915_gem_process_flushing_list(struct drm_device *dev, |
8a1a49f9 | 1571 | uint32_t flush_domains, |
852835f3 | 1572 | struct intel_ring_buffer *ring) |
63560396 DV |
1573 | { |
1574 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1575 | struct drm_i915_gem_object *obj_priv, *next; | |
1576 | ||
1577 | list_for_each_entry_safe(obj_priv, next, | |
1578 | &dev_priv->mm.gpu_write_list, | |
1579 | gpu_write_list) { | |
a8089e84 | 1580 | struct drm_gem_object *obj = &obj_priv->base; |
63560396 DV |
1581 | |
1582 | if ((obj->write_domain & flush_domains) == | |
852835f3 ZN |
1583 | obj->write_domain && |
1584 | obj_priv->ring->ring_flag == ring->ring_flag) { | |
63560396 DV |
1585 | uint32_t old_write_domain = obj->write_domain; |
1586 | ||
1587 | obj->write_domain = 0; | |
1588 | list_del_init(&obj_priv->gpu_write_list); | |
617dbe27 | 1589 | i915_gem_object_move_to_active(obj, ring); |
63560396 DV |
1590 | |
1591 | /* update the fence lru list */ | |
007cc8ac DV |
1592 | if (obj_priv->fence_reg != I915_FENCE_REG_NONE) { |
1593 | struct drm_i915_fence_reg *reg = | |
1594 | &dev_priv->fence_regs[obj_priv->fence_reg]; | |
1595 | list_move_tail(®->lru_list, | |
63560396 | 1596 | &dev_priv->mm.fence_list); |
007cc8ac | 1597 | } |
63560396 DV |
1598 | |
1599 | trace_i915_gem_object_change_domain(obj, | |
1600 | obj->read_domains, | |
1601 | old_write_domain); | |
1602 | } | |
1603 | } | |
1604 | } | |
8187a2b7 | 1605 | |
5a5a0c64 | 1606 | uint32_t |
8a1a49f9 DV |
1607 | i915_add_request(struct drm_device *dev, |
1608 | struct drm_file *file_priv, | |
8dc5d147 | 1609 | struct drm_i915_gem_request *request, |
8a1a49f9 | 1610 | struct intel_ring_buffer *ring) |
673a394b EA |
1611 | { |
1612 | drm_i915_private_t *dev_priv = dev->dev_private; | |
b962442e | 1613 | struct drm_i915_file_private *i915_file_priv = NULL; |
673a394b EA |
1614 | uint32_t seqno; |
1615 | int was_empty; | |
673a394b | 1616 | |
b962442e EA |
1617 | if (file_priv != NULL) |
1618 | i915_file_priv = file_priv->driver_priv; | |
1619 | ||
8dc5d147 CW |
1620 | if (request == NULL) { |
1621 | request = kzalloc(sizeof(*request), GFP_KERNEL); | |
1622 | if (request == NULL) | |
1623 | return 0; | |
1624 | } | |
673a394b | 1625 | |
8a1a49f9 | 1626 | seqno = ring->add_request(dev, ring, file_priv, 0); |
673a394b EA |
1627 | |
1628 | request->seqno = seqno; | |
852835f3 | 1629 | request->ring = ring; |
673a394b | 1630 | request->emitted_jiffies = jiffies; |
852835f3 ZN |
1631 | was_empty = list_empty(&ring->request_list); |
1632 | list_add_tail(&request->list, &ring->request_list); | |
1633 | ||
b962442e EA |
1634 | if (i915_file_priv) { |
1635 | list_add_tail(&request->client_list, | |
1636 | &i915_file_priv->mm.request_list); | |
1637 | } else { | |
1638 | INIT_LIST_HEAD(&request->client_list); | |
1639 | } | |
673a394b | 1640 | |
f65d9421 | 1641 | if (!dev_priv->mm.suspended) { |
b3b079db CW |
1642 | mod_timer(&dev_priv->hangcheck_timer, |
1643 | jiffies + msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)); | |
f65d9421 | 1644 | if (was_empty) |
b3b079db CW |
1645 | queue_delayed_work(dev_priv->wq, |
1646 | &dev_priv->mm.retire_work, HZ); | |
f65d9421 | 1647 | } |
673a394b EA |
1648 | return seqno; |
1649 | } | |
1650 | ||
1651 | /** | |
1652 | * Command execution barrier | |
1653 | * | |
1654 | * Ensures that all commands in the ring are finished | |
1655 | * before signalling the CPU | |
1656 | */ | |
8a1a49f9 | 1657 | static void |
852835f3 | 1658 | i915_retire_commands(struct drm_device *dev, struct intel_ring_buffer *ring) |
673a394b | 1659 | { |
673a394b | 1660 | uint32_t flush_domains = 0; |
673a394b EA |
1661 | |
1662 | /* The sampler always gets flushed on i965 (sigh) */ | |
1663 | if (IS_I965G(dev)) | |
1664 | flush_domains |= I915_GEM_DOMAIN_SAMPLER; | |
852835f3 ZN |
1665 | |
1666 | ring->flush(dev, ring, | |
1667 | I915_GEM_DOMAIN_COMMAND, flush_domains); | |
673a394b EA |
1668 | } |
1669 | ||
1670 | /** | |
1671 | * Moves buffers associated only with the given active seqno from the active | |
1672 | * to inactive list, potentially freeing them. | |
1673 | */ | |
1674 | static void | |
1675 | i915_gem_retire_request(struct drm_device *dev, | |
1676 | struct drm_i915_gem_request *request) | |
1677 | { | |
1c5d22f7 CW |
1678 | trace_i915_gem_request_retire(dev, request->seqno); |
1679 | ||
673a394b EA |
1680 | /* Move any buffers on the active list that are no longer referenced |
1681 | * by the ringbuffer to the flushing/inactive lists as appropriate. | |
1682 | */ | |
852835f3 | 1683 | while (!list_empty(&request->ring->active_list)) { |
673a394b EA |
1684 | struct drm_gem_object *obj; |
1685 | struct drm_i915_gem_object *obj_priv; | |
1686 | ||
852835f3 | 1687 | obj_priv = list_first_entry(&request->ring->active_list, |
673a394b EA |
1688 | struct drm_i915_gem_object, |
1689 | list); | |
a8089e84 | 1690 | obj = &obj_priv->base; |
673a394b EA |
1691 | |
1692 | /* If the seqno being retired doesn't match the oldest in the | |
1693 | * list, then the oldest in the list must still be newer than | |
1694 | * this seqno. | |
1695 | */ | |
1696 | if (obj_priv->last_rendering_seqno != request->seqno) | |
de227ef0 | 1697 | return; |
de151cf6 | 1698 | |
673a394b EA |
1699 | #if WATCH_LRU |
1700 | DRM_INFO("%s: retire %d moves to inactive list %p\n", | |
1701 | __func__, request->seqno, obj); | |
1702 | #endif | |
1703 | ||
ce44b0ea EA |
1704 | if (obj->write_domain != 0) |
1705 | i915_gem_object_move_to_flushing(obj); | |
de227ef0 | 1706 | else |
673a394b | 1707 | i915_gem_object_move_to_inactive(obj); |
673a394b EA |
1708 | } |
1709 | } | |
1710 | ||
1711 | /** | |
1712 | * Returns true if seq1 is later than seq2. | |
1713 | */ | |
22be1724 | 1714 | bool |
673a394b EA |
1715 | i915_seqno_passed(uint32_t seq1, uint32_t seq2) |
1716 | { | |
1717 | return (int32_t)(seq1 - seq2) >= 0; | |
1718 | } | |
1719 | ||
1720 | uint32_t | |
852835f3 | 1721 | i915_get_gem_seqno(struct drm_device *dev, |
d1b851fc | 1722 | struct intel_ring_buffer *ring) |
673a394b | 1723 | { |
852835f3 | 1724 | return ring->get_gem_seqno(dev, ring); |
673a394b EA |
1725 | } |
1726 | ||
1727 | /** | |
1728 | * This function clears the request list as sequence numbers are passed. | |
1729 | */ | |
b09a1fec CW |
1730 | static void |
1731 | i915_gem_retire_requests_ring(struct drm_device *dev, | |
1732 | struct intel_ring_buffer *ring) | |
673a394b EA |
1733 | { |
1734 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1735 | uint32_t seqno; | |
1736 | ||
8187a2b7 | 1737 | if (!ring->status_page.page_addr |
852835f3 | 1738 | || list_empty(&ring->request_list)) |
6c0594a3 KW |
1739 | return; |
1740 | ||
852835f3 | 1741 | seqno = i915_get_gem_seqno(dev, ring); |
673a394b | 1742 | |
852835f3 | 1743 | while (!list_empty(&ring->request_list)) { |
673a394b EA |
1744 | struct drm_i915_gem_request *request; |
1745 | uint32_t retiring_seqno; | |
1746 | ||
852835f3 | 1747 | request = list_first_entry(&ring->request_list, |
673a394b EA |
1748 | struct drm_i915_gem_request, |
1749 | list); | |
1750 | retiring_seqno = request->seqno; | |
1751 | ||
1752 | if (i915_seqno_passed(seqno, retiring_seqno) || | |
ba1234d1 | 1753 | atomic_read(&dev_priv->mm.wedged)) { |
673a394b EA |
1754 | i915_gem_retire_request(dev, request); |
1755 | ||
1756 | list_del(&request->list); | |
b962442e | 1757 | list_del(&request->client_list); |
9a298b2a | 1758 | kfree(request); |
673a394b EA |
1759 | } else |
1760 | break; | |
1761 | } | |
9d34e5db CW |
1762 | |
1763 | if (unlikely (dev_priv->trace_irq_seqno && | |
1764 | i915_seqno_passed(dev_priv->trace_irq_seqno, seqno))) { | |
8187a2b7 ZN |
1765 | |
1766 | ring->user_irq_put(dev, ring); | |
9d34e5db CW |
1767 | dev_priv->trace_irq_seqno = 0; |
1768 | } | |
673a394b EA |
1769 | } |
1770 | ||
b09a1fec CW |
1771 | void |
1772 | i915_gem_retire_requests(struct drm_device *dev) | |
1773 | { | |
1774 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1775 | ||
be72615b CW |
1776 | if (!list_empty(&dev_priv->mm.deferred_free_list)) { |
1777 | struct drm_i915_gem_object *obj_priv, *tmp; | |
1778 | ||
1779 | /* We must be careful that during unbind() we do not | |
1780 | * accidentally infinitely recurse into retire requests. | |
1781 | * Currently: | |
1782 | * retire -> free -> unbind -> wait -> retire_ring | |
1783 | */ | |
1784 | list_for_each_entry_safe(obj_priv, tmp, | |
1785 | &dev_priv->mm.deferred_free_list, | |
1786 | list) | |
1787 | i915_gem_free_object_tail(&obj_priv->base); | |
1788 | } | |
1789 | ||
b09a1fec CW |
1790 | i915_gem_retire_requests_ring(dev, &dev_priv->render_ring); |
1791 | if (HAS_BSD(dev)) | |
1792 | i915_gem_retire_requests_ring(dev, &dev_priv->bsd_ring); | |
1793 | } | |
1794 | ||
75ef9da2 | 1795 | static void |
673a394b EA |
1796 | i915_gem_retire_work_handler(struct work_struct *work) |
1797 | { | |
1798 | drm_i915_private_t *dev_priv; | |
1799 | struct drm_device *dev; | |
1800 | ||
1801 | dev_priv = container_of(work, drm_i915_private_t, | |
1802 | mm.retire_work.work); | |
1803 | dev = dev_priv->dev; | |
1804 | ||
1805 | mutex_lock(&dev->struct_mutex); | |
b09a1fec | 1806 | i915_gem_retire_requests(dev); |
d1b851fc | 1807 | |
6dbe2772 | 1808 | if (!dev_priv->mm.suspended && |
d1b851fc ZN |
1809 | (!list_empty(&dev_priv->render_ring.request_list) || |
1810 | (HAS_BSD(dev) && | |
1811 | !list_empty(&dev_priv->bsd_ring.request_list)))) | |
9c9fe1f8 | 1812 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ); |
673a394b EA |
1813 | mutex_unlock(&dev->struct_mutex); |
1814 | } | |
1815 | ||
5a5a0c64 | 1816 | int |
852835f3 | 1817 | i915_do_wait_request(struct drm_device *dev, uint32_t seqno, |
8a1a49f9 | 1818 | bool interruptible, struct intel_ring_buffer *ring) |
673a394b EA |
1819 | { |
1820 | drm_i915_private_t *dev_priv = dev->dev_private; | |
802c7eb6 | 1821 | u32 ier; |
673a394b EA |
1822 | int ret = 0; |
1823 | ||
1824 | BUG_ON(seqno == 0); | |
1825 | ||
e35a41de | 1826 | if (seqno == dev_priv->next_seqno) { |
8dc5d147 | 1827 | seqno = i915_add_request(dev, NULL, NULL, ring); |
e35a41de DV |
1828 | if (seqno == 0) |
1829 | return -ENOMEM; | |
1830 | } | |
1831 | ||
ba1234d1 | 1832 | if (atomic_read(&dev_priv->mm.wedged)) |
ffed1d09 BG |
1833 | return -EIO; |
1834 | ||
852835f3 | 1835 | if (!i915_seqno_passed(ring->get_gem_seqno(dev, ring), seqno)) { |
bad720ff | 1836 | if (HAS_PCH_SPLIT(dev)) |
036a4a7d ZW |
1837 | ier = I915_READ(DEIER) | I915_READ(GTIER); |
1838 | else | |
1839 | ier = I915_READ(IER); | |
802c7eb6 JB |
1840 | if (!ier) { |
1841 | DRM_ERROR("something (likely vbetool) disabled " | |
1842 | "interrupts, re-enabling\n"); | |
1843 | i915_driver_irq_preinstall(dev); | |
1844 | i915_driver_irq_postinstall(dev); | |
1845 | } | |
1846 | ||
1c5d22f7 CW |
1847 | trace_i915_gem_request_wait_begin(dev, seqno); |
1848 | ||
852835f3 | 1849 | ring->waiting_gem_seqno = seqno; |
8187a2b7 | 1850 | ring->user_irq_get(dev, ring); |
48764bf4 | 1851 | if (interruptible) |
852835f3 ZN |
1852 | ret = wait_event_interruptible(ring->irq_queue, |
1853 | i915_seqno_passed( | |
1854 | ring->get_gem_seqno(dev, ring), seqno) | |
1855 | || atomic_read(&dev_priv->mm.wedged)); | |
48764bf4 | 1856 | else |
852835f3 ZN |
1857 | wait_event(ring->irq_queue, |
1858 | i915_seqno_passed( | |
1859 | ring->get_gem_seqno(dev, ring), seqno) | |
1860 | || atomic_read(&dev_priv->mm.wedged)); | |
48764bf4 | 1861 | |
8187a2b7 | 1862 | ring->user_irq_put(dev, ring); |
852835f3 | 1863 | ring->waiting_gem_seqno = 0; |
1c5d22f7 CW |
1864 | |
1865 | trace_i915_gem_request_wait_end(dev, seqno); | |
673a394b | 1866 | } |
ba1234d1 | 1867 | if (atomic_read(&dev_priv->mm.wedged)) |
673a394b EA |
1868 | ret = -EIO; |
1869 | ||
1870 | if (ret && ret != -ERESTARTSYS) | |
8bff917c DV |
1871 | DRM_ERROR("%s returns %d (awaiting %d at %d, next %d)\n", |
1872 | __func__, ret, seqno, ring->get_gem_seqno(dev, ring), | |
1873 | dev_priv->next_seqno); | |
673a394b EA |
1874 | |
1875 | /* Directly dispatch request retiring. While we have the work queue | |
1876 | * to handle this, the waiter on a request often wants an associated | |
1877 | * buffer to have made it to the inactive list, and we would need | |
1878 | * a separate wait queue to handle that. | |
1879 | */ | |
1880 | if (ret == 0) | |
b09a1fec | 1881 | i915_gem_retire_requests_ring(dev, ring); |
673a394b EA |
1882 | |
1883 | return ret; | |
1884 | } | |
1885 | ||
48764bf4 DV |
1886 | /** |
1887 | * Waits for a sequence number to be signaled, and cleans up the | |
1888 | * request and object lists appropriately for that event. | |
1889 | */ | |
1890 | static int | |
852835f3 ZN |
1891 | i915_wait_request(struct drm_device *dev, uint32_t seqno, |
1892 | struct intel_ring_buffer *ring) | |
48764bf4 | 1893 | { |
852835f3 | 1894 | return i915_do_wait_request(dev, seqno, 1, ring); |
48764bf4 DV |
1895 | } |
1896 | ||
8187a2b7 ZN |
1897 | static void |
1898 | i915_gem_flush(struct drm_device *dev, | |
1899 | uint32_t invalidate_domains, | |
1900 | uint32_t flush_domains) | |
1901 | { | |
1902 | drm_i915_private_t *dev_priv = dev->dev_private; | |
8bff917c | 1903 | |
8187a2b7 ZN |
1904 | if (flush_domains & I915_GEM_DOMAIN_CPU) |
1905 | drm_agp_chipset_flush(dev); | |
8bff917c | 1906 | |
8187a2b7 ZN |
1907 | dev_priv->render_ring.flush(dev, &dev_priv->render_ring, |
1908 | invalidate_domains, | |
1909 | flush_domains); | |
d1b851fc ZN |
1910 | |
1911 | if (HAS_BSD(dev)) | |
1912 | dev_priv->bsd_ring.flush(dev, &dev_priv->bsd_ring, | |
1913 | invalidate_domains, | |
1914 | flush_domains); | |
8187a2b7 ZN |
1915 | } |
1916 | ||
673a394b EA |
1917 | /** |
1918 | * Ensures that all rendering to the object has completed and the object is | |
1919 | * safe to unbind from the GTT or access from the CPU. | |
1920 | */ | |
1921 | static int | |
ba3d8d74 | 1922 | i915_gem_object_wait_rendering(struct drm_gem_object *obj) |
673a394b EA |
1923 | { |
1924 | struct drm_device *dev = obj->dev; | |
23010e43 | 1925 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
673a394b EA |
1926 | int ret; |
1927 | ||
e47c68e9 EA |
1928 | /* This function only exists to support waiting for existing rendering, |
1929 | * not for emitting required flushes. | |
673a394b | 1930 | */ |
e47c68e9 | 1931 | BUG_ON((obj->write_domain & I915_GEM_GPU_DOMAINS) != 0); |
673a394b EA |
1932 | |
1933 | /* If there is rendering queued on the buffer being evicted, wait for | |
1934 | * it. | |
1935 | */ | |
1936 | if (obj_priv->active) { | |
1937 | #if WATCH_BUF | |
1938 | DRM_INFO("%s: object %p wait for seqno %08x\n", | |
1939 | __func__, obj, obj_priv->last_rendering_seqno); | |
1940 | #endif | |
ba3d8d74 DV |
1941 | ret = i915_wait_request(dev, |
1942 | obj_priv->last_rendering_seqno, | |
1943 | obj_priv->ring); | |
673a394b EA |
1944 | if (ret != 0) |
1945 | return ret; | |
1946 | } | |
1947 | ||
1948 | return 0; | |
1949 | } | |
1950 | ||
1951 | /** | |
1952 | * Unbinds an object from the GTT aperture. | |
1953 | */ | |
0f973f27 | 1954 | int |
673a394b EA |
1955 | i915_gem_object_unbind(struct drm_gem_object *obj) |
1956 | { | |
1957 | struct drm_device *dev = obj->dev; | |
23010e43 | 1958 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
673a394b EA |
1959 | int ret = 0; |
1960 | ||
1961 | #if WATCH_BUF | |
1962 | DRM_INFO("%s:%d %p\n", __func__, __LINE__, obj); | |
1963 | DRM_INFO("gtt_space %p\n", obj_priv->gtt_space); | |
1964 | #endif | |
1965 | if (obj_priv->gtt_space == NULL) | |
1966 | return 0; | |
1967 | ||
1968 | if (obj_priv->pin_count != 0) { | |
1969 | DRM_ERROR("Attempting to unbind pinned buffer\n"); | |
1970 | return -EINVAL; | |
1971 | } | |
1972 | ||
5323fd04 EA |
1973 | /* blow away mappings if mapped through GTT */ |
1974 | i915_gem_release_mmap(obj); | |
1975 | ||
673a394b EA |
1976 | /* Move the object to the CPU domain to ensure that |
1977 | * any possible CPU writes while it's not in the GTT | |
1978 | * are flushed when we go to remap it. This will | |
1979 | * also ensure that all pending GPU writes are finished | |
1980 | * before we unbind. | |
1981 | */ | |
e47c68e9 | 1982 | ret = i915_gem_object_set_to_cpu_domain(obj, 1); |
8dc1775d | 1983 | if (ret == -ERESTARTSYS) |
673a394b | 1984 | return ret; |
8dc1775d CW |
1985 | /* Continue on if we fail due to EIO, the GPU is hung so we |
1986 | * should be safe and we need to cleanup or else we might | |
1987 | * cause memory corruption through use-after-free. | |
1988 | */ | |
673a394b | 1989 | |
96b47b65 DV |
1990 | /* release the fence reg _after_ flushing */ |
1991 | if (obj_priv->fence_reg != I915_FENCE_REG_NONE) | |
1992 | i915_gem_clear_fence_reg(obj); | |
1993 | ||
673a394b EA |
1994 | if (obj_priv->agp_mem != NULL) { |
1995 | drm_unbind_agp(obj_priv->agp_mem); | |
1996 | drm_free_agp(obj_priv->agp_mem, obj->size / PAGE_SIZE); | |
1997 | obj_priv->agp_mem = NULL; | |
1998 | } | |
1999 | ||
856fa198 | 2000 | i915_gem_object_put_pages(obj); |
a32808c0 | 2001 | BUG_ON(obj_priv->pages_refcount); |
673a394b EA |
2002 | |
2003 | if (obj_priv->gtt_space) { | |
2004 | atomic_dec(&dev->gtt_count); | |
2005 | atomic_sub(obj->size, &dev->gtt_memory); | |
2006 | ||
2007 | drm_mm_put_block(obj_priv->gtt_space); | |
2008 | obj_priv->gtt_space = NULL; | |
2009 | } | |
2010 | ||
2011 | /* Remove ourselves from the LRU list if present. */ | |
2012 | if (!list_empty(&obj_priv->list)) | |
2013 | list_del_init(&obj_priv->list); | |
2014 | ||
963b4836 CW |
2015 | if (i915_gem_object_is_purgeable(obj_priv)) |
2016 | i915_gem_object_truncate(obj); | |
2017 | ||
1c5d22f7 CW |
2018 | trace_i915_gem_object_unbind(obj); |
2019 | ||
8dc1775d | 2020 | return ret; |
673a394b EA |
2021 | } |
2022 | ||
b47eb4a2 | 2023 | int |
4df2faf4 DV |
2024 | i915_gpu_idle(struct drm_device *dev) |
2025 | { | |
2026 | drm_i915_private_t *dev_priv = dev->dev_private; | |
2027 | bool lists_empty; | |
852835f3 | 2028 | int ret; |
4df2faf4 | 2029 | |
d1b851fc ZN |
2030 | lists_empty = (list_empty(&dev_priv->mm.flushing_list) && |
2031 | list_empty(&dev_priv->render_ring.active_list) && | |
2032 | (!HAS_BSD(dev) || | |
2033 | list_empty(&dev_priv->bsd_ring.active_list))); | |
4df2faf4 DV |
2034 | if (lists_empty) |
2035 | return 0; | |
2036 | ||
2037 | /* Flush everything onto the inactive list. */ | |
2038 | i915_gem_flush(dev, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS); | |
4fc6ee76 DV |
2039 | |
2040 | ret = i915_wait_request(dev, | |
2041 | i915_gem_next_request_seqno(dev, &dev_priv->render_ring), | |
2042 | &dev_priv->render_ring); | |
8a1a49f9 DV |
2043 | if (ret) |
2044 | return ret; | |
d1b851fc ZN |
2045 | |
2046 | if (HAS_BSD(dev)) { | |
4fc6ee76 DV |
2047 | ret = i915_wait_request(dev, |
2048 | i915_gem_next_request_seqno(dev, &dev_priv->bsd_ring), | |
2049 | &dev_priv->bsd_ring); | |
d1b851fc ZN |
2050 | if (ret) |
2051 | return ret; | |
2052 | } | |
2053 | ||
8a1a49f9 | 2054 | return 0; |
4df2faf4 DV |
2055 | } |
2056 | ||
6911a9b8 | 2057 | int |
4bdadb97 CW |
2058 | i915_gem_object_get_pages(struct drm_gem_object *obj, |
2059 | gfp_t gfpmask) | |
673a394b | 2060 | { |
23010e43 | 2061 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
673a394b EA |
2062 | int page_count, i; |
2063 | struct address_space *mapping; | |
2064 | struct inode *inode; | |
2065 | struct page *page; | |
673a394b | 2066 | |
778c3544 DV |
2067 | BUG_ON(obj_priv->pages_refcount |
2068 | == DRM_I915_GEM_OBJECT_MAX_PAGES_REFCOUNT); | |
2069 | ||
856fa198 | 2070 | if (obj_priv->pages_refcount++ != 0) |
673a394b EA |
2071 | return 0; |
2072 | ||
2073 | /* Get the list of pages out of our struct file. They'll be pinned | |
2074 | * at this point until we release them. | |
2075 | */ | |
2076 | page_count = obj->size / PAGE_SIZE; | |
856fa198 | 2077 | BUG_ON(obj_priv->pages != NULL); |
8e7d2b2c | 2078 | obj_priv->pages = drm_calloc_large(page_count, sizeof(struct page *)); |
856fa198 | 2079 | if (obj_priv->pages == NULL) { |
856fa198 | 2080 | obj_priv->pages_refcount--; |
673a394b EA |
2081 | return -ENOMEM; |
2082 | } | |
2083 | ||
2084 | inode = obj->filp->f_path.dentry->d_inode; | |
2085 | mapping = inode->i_mapping; | |
2086 | for (i = 0; i < page_count; i++) { | |
4bdadb97 | 2087 | page = read_cache_page_gfp(mapping, i, |
985b823b | 2088 | GFP_HIGHUSER | |
4bdadb97 | 2089 | __GFP_COLD | |
cd9f040d | 2090 | __GFP_RECLAIMABLE | |
4bdadb97 | 2091 | gfpmask); |
1f2b1013 CW |
2092 | if (IS_ERR(page)) |
2093 | goto err_pages; | |
2094 | ||
856fa198 | 2095 | obj_priv->pages[i] = page; |
673a394b | 2096 | } |
280b713b EA |
2097 | |
2098 | if (obj_priv->tiling_mode != I915_TILING_NONE) | |
2099 | i915_gem_object_do_bit_17_swizzle(obj); | |
2100 | ||
673a394b | 2101 | return 0; |
1f2b1013 CW |
2102 | |
2103 | err_pages: | |
2104 | while (i--) | |
2105 | page_cache_release(obj_priv->pages[i]); | |
2106 | ||
2107 | drm_free_large(obj_priv->pages); | |
2108 | obj_priv->pages = NULL; | |
2109 | obj_priv->pages_refcount--; | |
2110 | return PTR_ERR(page); | |
673a394b EA |
2111 | } |
2112 | ||
4e901fdc EA |
2113 | static void sandybridge_write_fence_reg(struct drm_i915_fence_reg *reg) |
2114 | { | |
2115 | struct drm_gem_object *obj = reg->obj; | |
2116 | struct drm_device *dev = obj->dev; | |
2117 | drm_i915_private_t *dev_priv = dev->dev_private; | |
23010e43 | 2118 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
4e901fdc EA |
2119 | int regnum = obj_priv->fence_reg; |
2120 | uint64_t val; | |
2121 | ||
2122 | val = (uint64_t)((obj_priv->gtt_offset + obj->size - 4096) & | |
2123 | 0xfffff000) << 32; | |
2124 | val |= obj_priv->gtt_offset & 0xfffff000; | |
2125 | val |= (uint64_t)((obj_priv->stride / 128) - 1) << | |
2126 | SANDYBRIDGE_FENCE_PITCH_SHIFT; | |
2127 | ||
2128 | if (obj_priv->tiling_mode == I915_TILING_Y) | |
2129 | val |= 1 << I965_FENCE_TILING_Y_SHIFT; | |
2130 | val |= I965_FENCE_REG_VALID; | |
2131 | ||
2132 | I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + (regnum * 8), val); | |
2133 | } | |
2134 | ||
de151cf6 JB |
2135 | static void i965_write_fence_reg(struct drm_i915_fence_reg *reg) |
2136 | { | |
2137 | struct drm_gem_object *obj = reg->obj; | |
2138 | struct drm_device *dev = obj->dev; | |
2139 | drm_i915_private_t *dev_priv = dev->dev_private; | |
23010e43 | 2140 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
de151cf6 JB |
2141 | int regnum = obj_priv->fence_reg; |
2142 | uint64_t val; | |
2143 | ||
2144 | val = (uint64_t)((obj_priv->gtt_offset + obj->size - 4096) & | |
2145 | 0xfffff000) << 32; | |
2146 | val |= obj_priv->gtt_offset & 0xfffff000; | |
2147 | val |= ((obj_priv->stride / 128) - 1) << I965_FENCE_PITCH_SHIFT; | |
2148 | if (obj_priv->tiling_mode == I915_TILING_Y) | |
2149 | val |= 1 << I965_FENCE_TILING_Y_SHIFT; | |
2150 | val |= I965_FENCE_REG_VALID; | |
2151 | ||
2152 | I915_WRITE64(FENCE_REG_965_0 + (regnum * 8), val); | |
2153 | } | |
2154 | ||
2155 | static void i915_write_fence_reg(struct drm_i915_fence_reg *reg) | |
2156 | { | |
2157 | struct drm_gem_object *obj = reg->obj; | |
2158 | struct drm_device *dev = obj->dev; | |
2159 | drm_i915_private_t *dev_priv = dev->dev_private; | |
23010e43 | 2160 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
de151cf6 | 2161 | int regnum = obj_priv->fence_reg; |
0f973f27 | 2162 | int tile_width; |
dc529a4f | 2163 | uint32_t fence_reg, val; |
de151cf6 JB |
2164 | uint32_t pitch_val; |
2165 | ||
2166 | if ((obj_priv->gtt_offset & ~I915_FENCE_START_MASK) || | |
2167 | (obj_priv->gtt_offset & (obj->size - 1))) { | |
f06da264 | 2168 | WARN(1, "%s: object 0x%08x not 1M or size (0x%zx) aligned\n", |
0f973f27 | 2169 | __func__, obj_priv->gtt_offset, obj->size); |
de151cf6 JB |
2170 | return; |
2171 | } | |
2172 | ||
0f973f27 JB |
2173 | if (obj_priv->tiling_mode == I915_TILING_Y && |
2174 | HAS_128_BYTE_Y_TILING(dev)) | |
2175 | tile_width = 128; | |
de151cf6 | 2176 | else |
0f973f27 JB |
2177 | tile_width = 512; |
2178 | ||
2179 | /* Note: pitch better be a power of two tile widths */ | |
2180 | pitch_val = obj_priv->stride / tile_width; | |
2181 | pitch_val = ffs(pitch_val) - 1; | |
de151cf6 | 2182 | |
c36a2a6d DV |
2183 | if (obj_priv->tiling_mode == I915_TILING_Y && |
2184 | HAS_128_BYTE_Y_TILING(dev)) | |
2185 | WARN_ON(pitch_val > I830_FENCE_MAX_PITCH_VAL); | |
2186 | else | |
2187 | WARN_ON(pitch_val > I915_FENCE_MAX_PITCH_VAL); | |
2188 | ||
de151cf6 JB |
2189 | val = obj_priv->gtt_offset; |
2190 | if (obj_priv->tiling_mode == I915_TILING_Y) | |
2191 | val |= 1 << I830_FENCE_TILING_Y_SHIFT; | |
2192 | val |= I915_FENCE_SIZE_BITS(obj->size); | |
2193 | val |= pitch_val << I830_FENCE_PITCH_SHIFT; | |
2194 | val |= I830_FENCE_REG_VALID; | |
2195 | ||
dc529a4f EA |
2196 | if (regnum < 8) |
2197 | fence_reg = FENCE_REG_830_0 + (regnum * 4); | |
2198 | else | |
2199 | fence_reg = FENCE_REG_945_8 + ((regnum - 8) * 4); | |
2200 | I915_WRITE(fence_reg, val); | |
de151cf6 JB |
2201 | } |
2202 | ||
2203 | static void i830_write_fence_reg(struct drm_i915_fence_reg *reg) | |
2204 | { | |
2205 | struct drm_gem_object *obj = reg->obj; | |
2206 | struct drm_device *dev = obj->dev; | |
2207 | drm_i915_private_t *dev_priv = dev->dev_private; | |
23010e43 | 2208 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
de151cf6 JB |
2209 | int regnum = obj_priv->fence_reg; |
2210 | uint32_t val; | |
2211 | uint32_t pitch_val; | |
8d7773a3 | 2212 | uint32_t fence_size_bits; |
de151cf6 | 2213 | |
8d7773a3 | 2214 | if ((obj_priv->gtt_offset & ~I830_FENCE_START_MASK) || |
de151cf6 | 2215 | (obj_priv->gtt_offset & (obj->size - 1))) { |
8d7773a3 | 2216 | WARN(1, "%s: object 0x%08x not 512K or size aligned\n", |
0f973f27 | 2217 | __func__, obj_priv->gtt_offset); |
de151cf6 JB |
2218 | return; |
2219 | } | |
2220 | ||
e76a16de EA |
2221 | pitch_val = obj_priv->stride / 128; |
2222 | pitch_val = ffs(pitch_val) - 1; | |
2223 | WARN_ON(pitch_val > I830_FENCE_MAX_PITCH_VAL); | |
2224 | ||
de151cf6 JB |
2225 | val = obj_priv->gtt_offset; |
2226 | if (obj_priv->tiling_mode == I915_TILING_Y) | |
2227 | val |= 1 << I830_FENCE_TILING_Y_SHIFT; | |
8d7773a3 DV |
2228 | fence_size_bits = I830_FENCE_SIZE_BITS(obj->size); |
2229 | WARN_ON(fence_size_bits & ~0x00000f00); | |
2230 | val |= fence_size_bits; | |
de151cf6 JB |
2231 | val |= pitch_val << I830_FENCE_PITCH_SHIFT; |
2232 | val |= I830_FENCE_REG_VALID; | |
2233 | ||
2234 | I915_WRITE(FENCE_REG_830_0 + (regnum * 4), val); | |
de151cf6 JB |
2235 | } |
2236 | ||
ae3db24a DV |
2237 | static int i915_find_fence_reg(struct drm_device *dev) |
2238 | { | |
2239 | struct drm_i915_fence_reg *reg = NULL; | |
2240 | struct drm_i915_gem_object *obj_priv = NULL; | |
2241 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2242 | struct drm_gem_object *obj = NULL; | |
2243 | int i, avail, ret; | |
2244 | ||
2245 | /* First try to find a free reg */ | |
2246 | avail = 0; | |
2247 | for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) { | |
2248 | reg = &dev_priv->fence_regs[i]; | |
2249 | if (!reg->obj) | |
2250 | return i; | |
2251 | ||
23010e43 | 2252 | obj_priv = to_intel_bo(reg->obj); |
ae3db24a DV |
2253 | if (!obj_priv->pin_count) |
2254 | avail++; | |
2255 | } | |
2256 | ||
2257 | if (avail == 0) | |
2258 | return -ENOSPC; | |
2259 | ||
2260 | /* None available, try to steal one or wait for a user to finish */ | |
2261 | i = I915_FENCE_REG_NONE; | |
007cc8ac DV |
2262 | list_for_each_entry(reg, &dev_priv->mm.fence_list, |
2263 | lru_list) { | |
2264 | obj = reg->obj; | |
2265 | obj_priv = to_intel_bo(obj); | |
ae3db24a DV |
2266 | |
2267 | if (obj_priv->pin_count) | |
2268 | continue; | |
2269 | ||
2270 | /* found one! */ | |
2271 | i = obj_priv->fence_reg; | |
2272 | break; | |
2273 | } | |
2274 | ||
2275 | BUG_ON(i == I915_FENCE_REG_NONE); | |
2276 | ||
2277 | /* We only have a reference on obj from the active list. put_fence_reg | |
2278 | * might drop that one, causing a use-after-free in it. So hold a | |
2279 | * private reference to obj like the other callers of put_fence_reg | |
2280 | * (set_tiling ioctl) do. */ | |
2281 | drm_gem_object_reference(obj); | |
2282 | ret = i915_gem_object_put_fence_reg(obj); | |
2283 | drm_gem_object_unreference(obj); | |
2284 | if (ret != 0) | |
2285 | return ret; | |
2286 | ||
2287 | return i; | |
2288 | } | |
2289 | ||
de151cf6 JB |
2290 | /** |
2291 | * i915_gem_object_get_fence_reg - set up a fence reg for an object | |
2292 | * @obj: object to map through a fence reg | |
2293 | * | |
2294 | * When mapping objects through the GTT, userspace wants to be able to write | |
2295 | * to them without having to worry about swizzling if the object is tiled. | |
2296 | * | |
2297 | * This function walks the fence regs looking for a free one for @obj, | |
2298 | * stealing one if it can't find any. | |
2299 | * | |
2300 | * It then sets up the reg based on the object's properties: address, pitch | |
2301 | * and tiling format. | |
2302 | */ | |
8c4b8c3f CW |
2303 | int |
2304 | i915_gem_object_get_fence_reg(struct drm_gem_object *obj) | |
de151cf6 JB |
2305 | { |
2306 | struct drm_device *dev = obj->dev; | |
79e53945 | 2307 | struct drm_i915_private *dev_priv = dev->dev_private; |
23010e43 | 2308 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
de151cf6 | 2309 | struct drm_i915_fence_reg *reg = NULL; |
ae3db24a | 2310 | int ret; |
de151cf6 | 2311 | |
a09ba7fa EA |
2312 | /* Just update our place in the LRU if our fence is getting used. */ |
2313 | if (obj_priv->fence_reg != I915_FENCE_REG_NONE) { | |
007cc8ac DV |
2314 | reg = &dev_priv->fence_regs[obj_priv->fence_reg]; |
2315 | list_move_tail(®->lru_list, &dev_priv->mm.fence_list); | |
a09ba7fa EA |
2316 | return 0; |
2317 | } | |
2318 | ||
de151cf6 JB |
2319 | switch (obj_priv->tiling_mode) { |
2320 | case I915_TILING_NONE: | |
2321 | WARN(1, "allocating a fence for non-tiled object?\n"); | |
2322 | break; | |
2323 | case I915_TILING_X: | |
0f973f27 JB |
2324 | if (!obj_priv->stride) |
2325 | return -EINVAL; | |
2326 | WARN((obj_priv->stride & (512 - 1)), | |
2327 | "object 0x%08x is X tiled but has non-512B pitch\n", | |
2328 | obj_priv->gtt_offset); | |
de151cf6 JB |
2329 | break; |
2330 | case I915_TILING_Y: | |
0f973f27 JB |
2331 | if (!obj_priv->stride) |
2332 | return -EINVAL; | |
2333 | WARN((obj_priv->stride & (128 - 1)), | |
2334 | "object 0x%08x is Y tiled but has non-128B pitch\n", | |
2335 | obj_priv->gtt_offset); | |
de151cf6 JB |
2336 | break; |
2337 | } | |
2338 | ||
ae3db24a DV |
2339 | ret = i915_find_fence_reg(dev); |
2340 | if (ret < 0) | |
2341 | return ret; | |
de151cf6 | 2342 | |
ae3db24a DV |
2343 | obj_priv->fence_reg = ret; |
2344 | reg = &dev_priv->fence_regs[obj_priv->fence_reg]; | |
007cc8ac | 2345 | list_add_tail(®->lru_list, &dev_priv->mm.fence_list); |
a09ba7fa | 2346 | |
de151cf6 JB |
2347 | reg->obj = obj; |
2348 | ||
4e901fdc EA |
2349 | if (IS_GEN6(dev)) |
2350 | sandybridge_write_fence_reg(reg); | |
2351 | else if (IS_I965G(dev)) | |
de151cf6 JB |
2352 | i965_write_fence_reg(reg); |
2353 | else if (IS_I9XX(dev)) | |
2354 | i915_write_fence_reg(reg); | |
2355 | else | |
2356 | i830_write_fence_reg(reg); | |
d9ddcb96 | 2357 | |
ae3db24a DV |
2358 | trace_i915_gem_object_get_fence(obj, obj_priv->fence_reg, |
2359 | obj_priv->tiling_mode); | |
1c5d22f7 | 2360 | |
d9ddcb96 | 2361 | return 0; |
de151cf6 JB |
2362 | } |
2363 | ||
2364 | /** | |
2365 | * i915_gem_clear_fence_reg - clear out fence register info | |
2366 | * @obj: object to clear | |
2367 | * | |
2368 | * Zeroes out the fence register itself and clears out the associated | |
2369 | * data structures in dev_priv and obj_priv. | |
2370 | */ | |
2371 | static void | |
2372 | i915_gem_clear_fence_reg(struct drm_gem_object *obj) | |
2373 | { | |
2374 | struct drm_device *dev = obj->dev; | |
79e53945 | 2375 | drm_i915_private_t *dev_priv = dev->dev_private; |
23010e43 | 2376 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
007cc8ac DV |
2377 | struct drm_i915_fence_reg *reg = |
2378 | &dev_priv->fence_regs[obj_priv->fence_reg]; | |
de151cf6 | 2379 | |
4e901fdc EA |
2380 | if (IS_GEN6(dev)) { |
2381 | I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + | |
2382 | (obj_priv->fence_reg * 8), 0); | |
2383 | } else if (IS_I965G(dev)) { | |
de151cf6 | 2384 | I915_WRITE64(FENCE_REG_965_0 + (obj_priv->fence_reg * 8), 0); |
4e901fdc | 2385 | } else { |
dc529a4f EA |
2386 | uint32_t fence_reg; |
2387 | ||
2388 | if (obj_priv->fence_reg < 8) | |
2389 | fence_reg = FENCE_REG_830_0 + obj_priv->fence_reg * 4; | |
2390 | else | |
2391 | fence_reg = FENCE_REG_945_8 + (obj_priv->fence_reg - | |
2392 | 8) * 4; | |
2393 | ||
2394 | I915_WRITE(fence_reg, 0); | |
2395 | } | |
de151cf6 | 2396 | |
007cc8ac | 2397 | reg->obj = NULL; |
de151cf6 | 2398 | obj_priv->fence_reg = I915_FENCE_REG_NONE; |
007cc8ac | 2399 | list_del_init(®->lru_list); |
de151cf6 JB |
2400 | } |
2401 | ||
52dc7d32 CW |
2402 | /** |
2403 | * i915_gem_object_put_fence_reg - waits on outstanding fenced access | |
2404 | * to the buffer to finish, and then resets the fence register. | |
2405 | * @obj: tiled object holding a fence register. | |
2406 | * | |
2407 | * Zeroes out the fence register itself and clears out the associated | |
2408 | * data structures in dev_priv and obj_priv. | |
2409 | */ | |
2410 | int | |
2411 | i915_gem_object_put_fence_reg(struct drm_gem_object *obj) | |
2412 | { | |
2413 | struct drm_device *dev = obj->dev; | |
23010e43 | 2414 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
52dc7d32 CW |
2415 | |
2416 | if (obj_priv->fence_reg == I915_FENCE_REG_NONE) | |
2417 | return 0; | |
2418 | ||
10ae9bd2 DV |
2419 | /* If we've changed tiling, GTT-mappings of the object |
2420 | * need to re-fault to ensure that the correct fence register | |
2421 | * setup is in place. | |
2422 | */ | |
2423 | i915_gem_release_mmap(obj); | |
2424 | ||
52dc7d32 CW |
2425 | /* On the i915, GPU access to tiled buffers is via a fence, |
2426 | * therefore we must wait for any outstanding access to complete | |
2427 | * before clearing the fence. | |
2428 | */ | |
2429 | if (!IS_I965G(dev)) { | |
2430 | int ret; | |
2431 | ||
ba3d8d74 | 2432 | ret = i915_gem_object_flush_gpu_write_domain(obj, false); |
52dc7d32 CW |
2433 | if (ret != 0) |
2434 | return ret; | |
2435 | } | |
2436 | ||
4a726612 | 2437 | i915_gem_object_flush_gtt_write_domain(obj); |
52dc7d32 CW |
2438 | i915_gem_clear_fence_reg (obj); |
2439 | ||
2440 | return 0; | |
2441 | } | |
2442 | ||
673a394b EA |
2443 | /** |
2444 | * Finds free space in the GTT aperture and binds the object there. | |
2445 | */ | |
2446 | static int | |
2447 | i915_gem_object_bind_to_gtt(struct drm_gem_object *obj, unsigned alignment) | |
2448 | { | |
2449 | struct drm_device *dev = obj->dev; | |
2450 | drm_i915_private_t *dev_priv = dev->dev_private; | |
23010e43 | 2451 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
673a394b | 2452 | struct drm_mm_node *free_space; |
4bdadb97 | 2453 | gfp_t gfpmask = __GFP_NORETRY | __GFP_NOWARN; |
07f73f69 | 2454 | int ret; |
673a394b | 2455 | |
bb6baf76 | 2456 | if (obj_priv->madv != I915_MADV_WILLNEED) { |
3ef94daa CW |
2457 | DRM_ERROR("Attempting to bind a purgeable object\n"); |
2458 | return -EINVAL; | |
2459 | } | |
2460 | ||
673a394b | 2461 | if (alignment == 0) |
0f973f27 | 2462 | alignment = i915_gem_get_gtt_alignment(obj); |
8d7773a3 | 2463 | if (alignment & (i915_gem_get_gtt_alignment(obj) - 1)) { |
673a394b EA |
2464 | DRM_ERROR("Invalid object alignment requested %u\n", alignment); |
2465 | return -EINVAL; | |
2466 | } | |
2467 | ||
654fc607 CW |
2468 | /* If the object is bigger than the entire aperture, reject it early |
2469 | * before evicting everything in a vain attempt to find space. | |
2470 | */ | |
2471 | if (obj->size > dev->gtt_total) { | |
2472 | DRM_ERROR("Attempting to bind an object larger than the aperture\n"); | |
2473 | return -E2BIG; | |
2474 | } | |
2475 | ||
673a394b EA |
2476 | search_free: |
2477 | free_space = drm_mm_search_free(&dev_priv->mm.gtt_space, | |
2478 | obj->size, alignment, 0); | |
2479 | if (free_space != NULL) { | |
2480 | obj_priv->gtt_space = drm_mm_get_block(free_space, obj->size, | |
2481 | alignment); | |
db3307a9 | 2482 | if (obj_priv->gtt_space != NULL) |
673a394b | 2483 | obj_priv->gtt_offset = obj_priv->gtt_space->start; |
673a394b EA |
2484 | } |
2485 | if (obj_priv->gtt_space == NULL) { | |
2486 | /* If the gtt is empty and we're still having trouble | |
2487 | * fitting our object in, we're out of memory. | |
2488 | */ | |
2489 | #if WATCH_LRU | |
2490 | DRM_INFO("%s: GTT full, evicting something\n", __func__); | |
2491 | #endif | |
0108a3ed | 2492 | ret = i915_gem_evict_something(dev, obj->size, alignment); |
9731129c | 2493 | if (ret) |
673a394b | 2494 | return ret; |
9731129c | 2495 | |
673a394b EA |
2496 | goto search_free; |
2497 | } | |
2498 | ||
2499 | #if WATCH_BUF | |
cfd43c02 | 2500 | DRM_INFO("Binding object of size %zd at 0x%08x\n", |
673a394b EA |
2501 | obj->size, obj_priv->gtt_offset); |
2502 | #endif | |
4bdadb97 | 2503 | ret = i915_gem_object_get_pages(obj, gfpmask); |
673a394b EA |
2504 | if (ret) { |
2505 | drm_mm_put_block(obj_priv->gtt_space); | |
2506 | obj_priv->gtt_space = NULL; | |
07f73f69 CW |
2507 | |
2508 | if (ret == -ENOMEM) { | |
2509 | /* first try to clear up some space from the GTT */ | |
0108a3ed DV |
2510 | ret = i915_gem_evict_something(dev, obj->size, |
2511 | alignment); | |
07f73f69 | 2512 | if (ret) { |
07f73f69 | 2513 | /* now try to shrink everyone else */ |
4bdadb97 CW |
2514 | if (gfpmask) { |
2515 | gfpmask = 0; | |
2516 | goto search_free; | |
07f73f69 CW |
2517 | } |
2518 | ||
2519 | return ret; | |
2520 | } | |
2521 | ||
2522 | goto search_free; | |
2523 | } | |
2524 | ||
673a394b EA |
2525 | return ret; |
2526 | } | |
2527 | ||
673a394b EA |
2528 | /* Create an AGP memory structure pointing at our pages, and bind it |
2529 | * into the GTT. | |
2530 | */ | |
2531 | obj_priv->agp_mem = drm_agp_bind_pages(dev, | |
856fa198 | 2532 | obj_priv->pages, |
07f73f69 | 2533 | obj->size >> PAGE_SHIFT, |
ba1eb1d8 KP |
2534 | obj_priv->gtt_offset, |
2535 | obj_priv->agp_type); | |
673a394b | 2536 | if (obj_priv->agp_mem == NULL) { |
856fa198 | 2537 | i915_gem_object_put_pages(obj); |
673a394b EA |
2538 | drm_mm_put_block(obj_priv->gtt_space); |
2539 | obj_priv->gtt_space = NULL; | |
07f73f69 | 2540 | |
0108a3ed | 2541 | ret = i915_gem_evict_something(dev, obj->size, alignment); |
9731129c | 2542 | if (ret) |
07f73f69 | 2543 | return ret; |
07f73f69 CW |
2544 | |
2545 | goto search_free; | |
673a394b EA |
2546 | } |
2547 | atomic_inc(&dev->gtt_count); | |
2548 | atomic_add(obj->size, &dev->gtt_memory); | |
2549 | ||
bf1a1092 CW |
2550 | /* keep track of bounds object by adding it to the inactive list */ |
2551 | list_add_tail(&obj_priv->list, &dev_priv->mm.inactive_list); | |
2552 | ||
673a394b EA |
2553 | /* Assert that the object is not currently in any GPU domain. As it |
2554 | * wasn't in the GTT, there shouldn't be any way it could have been in | |
2555 | * a GPU cache | |
2556 | */ | |
21d509e3 CW |
2557 | BUG_ON(obj->read_domains & I915_GEM_GPU_DOMAINS); |
2558 | BUG_ON(obj->write_domain & I915_GEM_GPU_DOMAINS); | |
673a394b | 2559 | |
1c5d22f7 CW |
2560 | trace_i915_gem_object_bind(obj, obj_priv->gtt_offset); |
2561 | ||
673a394b EA |
2562 | return 0; |
2563 | } | |
2564 | ||
2565 | void | |
2566 | i915_gem_clflush_object(struct drm_gem_object *obj) | |
2567 | { | |
23010e43 | 2568 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
673a394b EA |
2569 | |
2570 | /* If we don't have a page list set up, then we're not pinned | |
2571 | * to GPU, and we can ignore the cache flush because it'll happen | |
2572 | * again at bind time. | |
2573 | */ | |
856fa198 | 2574 | if (obj_priv->pages == NULL) |
673a394b EA |
2575 | return; |
2576 | ||
1c5d22f7 | 2577 | trace_i915_gem_object_clflush(obj); |
cfa16a0d | 2578 | |
856fa198 | 2579 | drm_clflush_pages(obj_priv->pages, obj->size / PAGE_SIZE); |
673a394b EA |
2580 | } |
2581 | ||
e47c68e9 | 2582 | /** Flushes any GPU write domain for the object if it's dirty. */ |
2dafb1e0 | 2583 | static int |
ba3d8d74 DV |
2584 | i915_gem_object_flush_gpu_write_domain(struct drm_gem_object *obj, |
2585 | bool pipelined) | |
e47c68e9 EA |
2586 | { |
2587 | struct drm_device *dev = obj->dev; | |
1c5d22f7 | 2588 | uint32_t old_write_domain; |
e47c68e9 EA |
2589 | |
2590 | if ((obj->write_domain & I915_GEM_GPU_DOMAINS) == 0) | |
2dafb1e0 | 2591 | return 0; |
e47c68e9 EA |
2592 | |
2593 | /* Queue the GPU write cache flushing we need. */ | |
1c5d22f7 | 2594 | old_write_domain = obj->write_domain; |
e47c68e9 | 2595 | i915_gem_flush(dev, 0, obj->write_domain); |
1c5d22f7 CW |
2596 | |
2597 | trace_i915_gem_object_change_domain(obj, | |
2598 | obj->read_domains, | |
2599 | old_write_domain); | |
ba3d8d74 DV |
2600 | |
2601 | if (pipelined) | |
2602 | return 0; | |
2603 | ||
2604 | return i915_gem_object_wait_rendering(obj); | |
e47c68e9 EA |
2605 | } |
2606 | ||
2607 | /** Flushes the GTT write domain for the object if it's dirty. */ | |
2608 | static void | |
2609 | i915_gem_object_flush_gtt_write_domain(struct drm_gem_object *obj) | |
2610 | { | |
1c5d22f7 CW |
2611 | uint32_t old_write_domain; |
2612 | ||
e47c68e9 EA |
2613 | if (obj->write_domain != I915_GEM_DOMAIN_GTT) |
2614 | return; | |
2615 | ||
2616 | /* No actual flushing is required for the GTT write domain. Writes | |
2617 | * to it immediately go to main memory as far as we know, so there's | |
2618 | * no chipset flush. It also doesn't land in render cache. | |
2619 | */ | |
1c5d22f7 | 2620 | old_write_domain = obj->write_domain; |
e47c68e9 | 2621 | obj->write_domain = 0; |
1c5d22f7 CW |
2622 | |
2623 | trace_i915_gem_object_change_domain(obj, | |
2624 | obj->read_domains, | |
2625 | old_write_domain); | |
e47c68e9 EA |
2626 | } |
2627 | ||
2628 | /** Flushes the CPU write domain for the object if it's dirty. */ | |
2629 | static void | |
2630 | i915_gem_object_flush_cpu_write_domain(struct drm_gem_object *obj) | |
2631 | { | |
2632 | struct drm_device *dev = obj->dev; | |
1c5d22f7 | 2633 | uint32_t old_write_domain; |
e47c68e9 EA |
2634 | |
2635 | if (obj->write_domain != I915_GEM_DOMAIN_CPU) | |
2636 | return; | |
2637 | ||
2638 | i915_gem_clflush_object(obj); | |
2639 | drm_agp_chipset_flush(dev); | |
1c5d22f7 | 2640 | old_write_domain = obj->write_domain; |
e47c68e9 | 2641 | obj->write_domain = 0; |
1c5d22f7 CW |
2642 | |
2643 | trace_i915_gem_object_change_domain(obj, | |
2644 | obj->read_domains, | |
2645 | old_write_domain); | |
e47c68e9 EA |
2646 | } |
2647 | ||
2ef7eeaa EA |
2648 | /** |
2649 | * Moves a single object to the GTT read, and possibly write domain. | |
2650 | * | |
2651 | * This function returns when the move is complete, including waiting on | |
2652 | * flushes to occur. | |
2653 | */ | |
79e53945 | 2654 | int |
2ef7eeaa EA |
2655 | i915_gem_object_set_to_gtt_domain(struct drm_gem_object *obj, int write) |
2656 | { | |
23010e43 | 2657 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
1c5d22f7 | 2658 | uint32_t old_write_domain, old_read_domains; |
e47c68e9 | 2659 | int ret; |
2ef7eeaa | 2660 | |
02354392 EA |
2661 | /* Not valid to be called on unbound objects. */ |
2662 | if (obj_priv->gtt_space == NULL) | |
2663 | return -EINVAL; | |
2664 | ||
ba3d8d74 | 2665 | ret = i915_gem_object_flush_gpu_write_domain(obj, false); |
e47c68e9 EA |
2666 | if (ret != 0) |
2667 | return ret; | |
2668 | ||
7213342d | 2669 | i915_gem_object_flush_cpu_write_domain(obj); |
1c5d22f7 | 2670 | |
ba3d8d74 DV |
2671 | if (write) { |
2672 | ret = i915_gem_object_wait_rendering(obj); | |
2673 | if (ret) | |
2674 | return ret; | |
ba3d8d74 | 2675 | } |
2ef7eeaa | 2676 | |
7213342d CW |
2677 | old_write_domain = obj->write_domain; |
2678 | old_read_domains = obj->read_domains; | |
2ef7eeaa | 2679 | |
e47c68e9 EA |
2680 | /* It should now be out of any other write domains, and we can update |
2681 | * the domain values for our changes. | |
2682 | */ | |
2683 | BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_GTT) != 0); | |
2684 | obj->read_domains |= I915_GEM_DOMAIN_GTT; | |
2685 | if (write) { | |
7213342d | 2686 | obj->read_domains = I915_GEM_DOMAIN_GTT; |
e47c68e9 EA |
2687 | obj->write_domain = I915_GEM_DOMAIN_GTT; |
2688 | obj_priv->dirty = 1; | |
2ef7eeaa EA |
2689 | } |
2690 | ||
1c5d22f7 CW |
2691 | trace_i915_gem_object_change_domain(obj, |
2692 | old_read_domains, | |
2693 | old_write_domain); | |
2694 | ||
e47c68e9 EA |
2695 | return 0; |
2696 | } | |
2697 | ||
b9241ea3 ZW |
2698 | /* |
2699 | * Prepare buffer for display plane. Use uninterruptible for possible flush | |
2700 | * wait, as in modesetting process we're not supposed to be interrupted. | |
2701 | */ | |
2702 | int | |
2703 | i915_gem_object_set_to_display_plane(struct drm_gem_object *obj) | |
2704 | { | |
23010e43 | 2705 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
ba3d8d74 | 2706 | uint32_t old_read_domains; |
b9241ea3 ZW |
2707 | int ret; |
2708 | ||
2709 | /* Not valid to be called on unbound objects. */ | |
2710 | if (obj_priv->gtt_space == NULL) | |
2711 | return -EINVAL; | |
2712 | ||
ba3d8d74 | 2713 | ret = i915_gem_object_flush_gpu_write_domain(obj, true); |
e35a41de DV |
2714 | if (ret != 0) |
2715 | return ret; | |
b9241ea3 | 2716 | |
b118c1e3 CW |
2717 | i915_gem_object_flush_cpu_write_domain(obj); |
2718 | ||
b9241ea3 | 2719 | old_read_domains = obj->read_domains; |
b118c1e3 | 2720 | obj->read_domains = I915_GEM_DOMAIN_GTT; |
b9241ea3 ZW |
2721 | |
2722 | trace_i915_gem_object_change_domain(obj, | |
2723 | old_read_domains, | |
ba3d8d74 | 2724 | obj->write_domain); |
b9241ea3 ZW |
2725 | |
2726 | return 0; | |
2727 | } | |
2728 | ||
e47c68e9 EA |
2729 | /** |
2730 | * Moves a single object to the CPU read, and possibly write domain. | |
2731 | * | |
2732 | * This function returns when the move is complete, including waiting on | |
2733 | * flushes to occur. | |
2734 | */ | |
2735 | static int | |
2736 | i915_gem_object_set_to_cpu_domain(struct drm_gem_object *obj, int write) | |
2737 | { | |
1c5d22f7 | 2738 | uint32_t old_write_domain, old_read_domains; |
e47c68e9 EA |
2739 | int ret; |
2740 | ||
ba3d8d74 | 2741 | ret = i915_gem_object_flush_gpu_write_domain(obj, false); |
e47c68e9 EA |
2742 | if (ret != 0) |
2743 | return ret; | |
2ef7eeaa | 2744 | |
e47c68e9 | 2745 | i915_gem_object_flush_gtt_write_domain(obj); |
2ef7eeaa | 2746 | |
e47c68e9 EA |
2747 | /* If we have a partially-valid cache of the object in the CPU, |
2748 | * finish invalidating it and free the per-page flags. | |
2ef7eeaa | 2749 | */ |
e47c68e9 | 2750 | i915_gem_object_set_to_full_cpu_read_domain(obj); |
2ef7eeaa | 2751 | |
7213342d CW |
2752 | if (write) { |
2753 | ret = i915_gem_object_wait_rendering(obj); | |
2754 | if (ret) | |
2755 | return ret; | |
2756 | } | |
2757 | ||
1c5d22f7 CW |
2758 | old_write_domain = obj->write_domain; |
2759 | old_read_domains = obj->read_domains; | |
2760 | ||
e47c68e9 EA |
2761 | /* Flush the CPU cache if it's still invalid. */ |
2762 | if ((obj->read_domains & I915_GEM_DOMAIN_CPU) == 0) { | |
2ef7eeaa | 2763 | i915_gem_clflush_object(obj); |
2ef7eeaa | 2764 | |
e47c68e9 | 2765 | obj->read_domains |= I915_GEM_DOMAIN_CPU; |
2ef7eeaa EA |
2766 | } |
2767 | ||
2768 | /* It should now be out of any other write domains, and we can update | |
2769 | * the domain values for our changes. | |
2770 | */ | |
e47c68e9 EA |
2771 | BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_CPU) != 0); |
2772 | ||
2773 | /* If we're writing through the CPU, then the GPU read domains will | |
2774 | * need to be invalidated at next use. | |
2775 | */ | |
2776 | if (write) { | |
2777 | obj->read_domains &= I915_GEM_DOMAIN_CPU; | |
2778 | obj->write_domain = I915_GEM_DOMAIN_CPU; | |
2779 | } | |
2ef7eeaa | 2780 | |
1c5d22f7 CW |
2781 | trace_i915_gem_object_change_domain(obj, |
2782 | old_read_domains, | |
2783 | old_write_domain); | |
2784 | ||
2ef7eeaa EA |
2785 | return 0; |
2786 | } | |
2787 | ||
673a394b EA |
2788 | /* |
2789 | * Set the next domain for the specified object. This | |
2790 | * may not actually perform the necessary flushing/invaliding though, | |
2791 | * as that may want to be batched with other set_domain operations | |
2792 | * | |
2793 | * This is (we hope) the only really tricky part of gem. The goal | |
2794 | * is fairly simple -- track which caches hold bits of the object | |
2795 | * and make sure they remain coherent. A few concrete examples may | |
2796 | * help to explain how it works. For shorthand, we use the notation | |
2797 | * (read_domains, write_domain), e.g. (CPU, CPU) to indicate the | |
2798 | * a pair of read and write domain masks. | |
2799 | * | |
2800 | * Case 1: the batch buffer | |
2801 | * | |
2802 | * 1. Allocated | |
2803 | * 2. Written by CPU | |
2804 | * 3. Mapped to GTT | |
2805 | * 4. Read by GPU | |
2806 | * 5. Unmapped from GTT | |
2807 | * 6. Freed | |
2808 | * | |
2809 | * Let's take these a step at a time | |
2810 | * | |
2811 | * 1. Allocated | |
2812 | * Pages allocated from the kernel may still have | |
2813 | * cache contents, so we set them to (CPU, CPU) always. | |
2814 | * 2. Written by CPU (using pwrite) | |
2815 | * The pwrite function calls set_domain (CPU, CPU) and | |
2816 | * this function does nothing (as nothing changes) | |
2817 | * 3. Mapped by GTT | |
2818 | * This function asserts that the object is not | |
2819 | * currently in any GPU-based read or write domains | |
2820 | * 4. Read by GPU | |
2821 | * i915_gem_execbuffer calls set_domain (COMMAND, 0). | |
2822 | * As write_domain is zero, this function adds in the | |
2823 | * current read domains (CPU+COMMAND, 0). | |
2824 | * flush_domains is set to CPU. | |
2825 | * invalidate_domains is set to COMMAND | |
2826 | * clflush is run to get data out of the CPU caches | |
2827 | * then i915_dev_set_domain calls i915_gem_flush to | |
2828 | * emit an MI_FLUSH and drm_agp_chipset_flush | |
2829 | * 5. Unmapped from GTT | |
2830 | * i915_gem_object_unbind calls set_domain (CPU, CPU) | |
2831 | * flush_domains and invalidate_domains end up both zero | |
2832 | * so no flushing/invalidating happens | |
2833 | * 6. Freed | |
2834 | * yay, done | |
2835 | * | |
2836 | * Case 2: The shared render buffer | |
2837 | * | |
2838 | * 1. Allocated | |
2839 | * 2. Mapped to GTT | |
2840 | * 3. Read/written by GPU | |
2841 | * 4. set_domain to (CPU,CPU) | |
2842 | * 5. Read/written by CPU | |
2843 | * 6. Read/written by GPU | |
2844 | * | |
2845 | * 1. Allocated | |
2846 | * Same as last example, (CPU, CPU) | |
2847 | * 2. Mapped to GTT | |
2848 | * Nothing changes (assertions find that it is not in the GPU) | |
2849 | * 3. Read/written by GPU | |
2850 | * execbuffer calls set_domain (RENDER, RENDER) | |
2851 | * flush_domains gets CPU | |
2852 | * invalidate_domains gets GPU | |
2853 | * clflush (obj) | |
2854 | * MI_FLUSH and drm_agp_chipset_flush | |
2855 | * 4. set_domain (CPU, CPU) | |
2856 | * flush_domains gets GPU | |
2857 | * invalidate_domains gets CPU | |
2858 | * wait_rendering (obj) to make sure all drawing is complete. | |
2859 | * This will include an MI_FLUSH to get the data from GPU | |
2860 | * to memory | |
2861 | * clflush (obj) to invalidate the CPU cache | |
2862 | * Another MI_FLUSH in i915_gem_flush (eliminate this somehow?) | |
2863 | * 5. Read/written by CPU | |
2864 | * cache lines are loaded and dirtied | |
2865 | * 6. Read written by GPU | |
2866 | * Same as last GPU access | |
2867 | * | |
2868 | * Case 3: The constant buffer | |
2869 | * | |
2870 | * 1. Allocated | |
2871 | * 2. Written by CPU | |
2872 | * 3. Read by GPU | |
2873 | * 4. Updated (written) by CPU again | |
2874 | * 5. Read by GPU | |
2875 | * | |
2876 | * 1. Allocated | |
2877 | * (CPU, CPU) | |
2878 | * 2. Written by CPU | |
2879 | * (CPU, CPU) | |
2880 | * 3. Read by GPU | |
2881 | * (CPU+RENDER, 0) | |
2882 | * flush_domains = CPU | |
2883 | * invalidate_domains = RENDER | |
2884 | * clflush (obj) | |
2885 | * MI_FLUSH | |
2886 | * drm_agp_chipset_flush | |
2887 | * 4. Updated (written) by CPU again | |
2888 | * (CPU, CPU) | |
2889 | * flush_domains = 0 (no previous write domain) | |
2890 | * invalidate_domains = 0 (no new read domains) | |
2891 | * 5. Read by GPU | |
2892 | * (CPU+RENDER, 0) | |
2893 | * flush_domains = CPU | |
2894 | * invalidate_domains = RENDER | |
2895 | * clflush (obj) | |
2896 | * MI_FLUSH | |
2897 | * drm_agp_chipset_flush | |
2898 | */ | |
c0d90829 | 2899 | static void |
8b0e378a | 2900 | i915_gem_object_set_to_gpu_domain(struct drm_gem_object *obj) |
673a394b EA |
2901 | { |
2902 | struct drm_device *dev = obj->dev; | |
23010e43 | 2903 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
673a394b EA |
2904 | uint32_t invalidate_domains = 0; |
2905 | uint32_t flush_domains = 0; | |
1c5d22f7 | 2906 | uint32_t old_read_domains; |
e47c68e9 | 2907 | |
8b0e378a EA |
2908 | BUG_ON(obj->pending_read_domains & I915_GEM_DOMAIN_CPU); |
2909 | BUG_ON(obj->pending_write_domain == I915_GEM_DOMAIN_CPU); | |
673a394b | 2910 | |
652c393a JB |
2911 | intel_mark_busy(dev, obj); |
2912 | ||
673a394b EA |
2913 | #if WATCH_BUF |
2914 | DRM_INFO("%s: object %p read %08x -> %08x write %08x -> %08x\n", | |
2915 | __func__, obj, | |
8b0e378a EA |
2916 | obj->read_domains, obj->pending_read_domains, |
2917 | obj->write_domain, obj->pending_write_domain); | |
673a394b EA |
2918 | #endif |
2919 | /* | |
2920 | * If the object isn't moving to a new write domain, | |
2921 | * let the object stay in multiple read domains | |
2922 | */ | |
8b0e378a EA |
2923 | if (obj->pending_write_domain == 0) |
2924 | obj->pending_read_domains |= obj->read_domains; | |
673a394b EA |
2925 | else |
2926 | obj_priv->dirty = 1; | |
2927 | ||
2928 | /* | |
2929 | * Flush the current write domain if | |
2930 | * the new read domains don't match. Invalidate | |
2931 | * any read domains which differ from the old | |
2932 | * write domain | |
2933 | */ | |
8b0e378a EA |
2934 | if (obj->write_domain && |
2935 | obj->write_domain != obj->pending_read_domains) { | |
673a394b | 2936 | flush_domains |= obj->write_domain; |
8b0e378a EA |
2937 | invalidate_domains |= |
2938 | obj->pending_read_domains & ~obj->write_domain; | |
673a394b EA |
2939 | } |
2940 | /* | |
2941 | * Invalidate any read caches which may have | |
2942 | * stale data. That is, any new read domains. | |
2943 | */ | |
8b0e378a | 2944 | invalidate_domains |= obj->pending_read_domains & ~obj->read_domains; |
673a394b EA |
2945 | if ((flush_domains | invalidate_domains) & I915_GEM_DOMAIN_CPU) { |
2946 | #if WATCH_BUF | |
2947 | DRM_INFO("%s: CPU domain flush %08x invalidate %08x\n", | |
2948 | __func__, flush_domains, invalidate_domains); | |
2949 | #endif | |
673a394b EA |
2950 | i915_gem_clflush_object(obj); |
2951 | } | |
2952 | ||
1c5d22f7 CW |
2953 | old_read_domains = obj->read_domains; |
2954 | ||
efbeed96 EA |
2955 | /* The actual obj->write_domain will be updated with |
2956 | * pending_write_domain after we emit the accumulated flush for all | |
2957 | * of our domain changes in execbuffers (which clears objects' | |
2958 | * write_domains). So if we have a current write domain that we | |
2959 | * aren't changing, set pending_write_domain to that. | |
2960 | */ | |
2961 | if (flush_domains == 0 && obj->pending_write_domain == 0) | |
2962 | obj->pending_write_domain = obj->write_domain; | |
8b0e378a | 2963 | obj->read_domains = obj->pending_read_domains; |
673a394b EA |
2964 | |
2965 | dev->invalidate_domains |= invalidate_domains; | |
2966 | dev->flush_domains |= flush_domains; | |
2967 | #if WATCH_BUF | |
2968 | DRM_INFO("%s: read %08x write %08x invalidate %08x flush %08x\n", | |
2969 | __func__, | |
2970 | obj->read_domains, obj->write_domain, | |
2971 | dev->invalidate_domains, dev->flush_domains); | |
2972 | #endif | |
1c5d22f7 CW |
2973 | |
2974 | trace_i915_gem_object_change_domain(obj, | |
2975 | old_read_domains, | |
2976 | obj->write_domain); | |
673a394b EA |
2977 | } |
2978 | ||
2979 | /** | |
e47c68e9 | 2980 | * Moves the object from a partially CPU read to a full one. |
673a394b | 2981 | * |
e47c68e9 EA |
2982 | * Note that this only resolves i915_gem_object_set_cpu_read_domain_range(), |
2983 | * and doesn't handle transitioning from !(read_domains & I915_GEM_DOMAIN_CPU). | |
673a394b | 2984 | */ |
e47c68e9 EA |
2985 | static void |
2986 | i915_gem_object_set_to_full_cpu_read_domain(struct drm_gem_object *obj) | |
673a394b | 2987 | { |
23010e43 | 2988 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
673a394b | 2989 | |
e47c68e9 EA |
2990 | if (!obj_priv->page_cpu_valid) |
2991 | return; | |
2992 | ||
2993 | /* If we're partially in the CPU read domain, finish moving it in. | |
2994 | */ | |
2995 | if (obj->read_domains & I915_GEM_DOMAIN_CPU) { | |
2996 | int i; | |
2997 | ||
2998 | for (i = 0; i <= (obj->size - 1) / PAGE_SIZE; i++) { | |
2999 | if (obj_priv->page_cpu_valid[i]) | |
3000 | continue; | |
856fa198 | 3001 | drm_clflush_pages(obj_priv->pages + i, 1); |
e47c68e9 | 3002 | } |
e47c68e9 EA |
3003 | } |
3004 | ||
3005 | /* Free the page_cpu_valid mappings which are now stale, whether | |
3006 | * or not we've got I915_GEM_DOMAIN_CPU. | |
3007 | */ | |
9a298b2a | 3008 | kfree(obj_priv->page_cpu_valid); |
e47c68e9 EA |
3009 | obj_priv->page_cpu_valid = NULL; |
3010 | } | |
3011 | ||
3012 | /** | |
3013 | * Set the CPU read domain on a range of the object. | |
3014 | * | |
3015 | * The object ends up with I915_GEM_DOMAIN_CPU in its read flags although it's | |
3016 | * not entirely valid. The page_cpu_valid member of the object flags which | |
3017 | * pages have been flushed, and will be respected by | |
3018 | * i915_gem_object_set_to_cpu_domain() if it's called on to get a valid mapping | |
3019 | * of the whole object. | |
3020 | * | |
3021 | * This function returns when the move is complete, including waiting on | |
3022 | * flushes to occur. | |
3023 | */ | |
3024 | static int | |
3025 | i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object *obj, | |
3026 | uint64_t offset, uint64_t size) | |
3027 | { | |
23010e43 | 3028 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
1c5d22f7 | 3029 | uint32_t old_read_domains; |
e47c68e9 | 3030 | int i, ret; |
673a394b | 3031 | |
e47c68e9 EA |
3032 | if (offset == 0 && size == obj->size) |
3033 | return i915_gem_object_set_to_cpu_domain(obj, 0); | |
673a394b | 3034 | |
ba3d8d74 | 3035 | ret = i915_gem_object_flush_gpu_write_domain(obj, false); |
e47c68e9 | 3036 | if (ret != 0) |
6a47baa6 | 3037 | return ret; |
e47c68e9 EA |
3038 | i915_gem_object_flush_gtt_write_domain(obj); |
3039 | ||
3040 | /* If we're already fully in the CPU read domain, we're done. */ | |
3041 | if (obj_priv->page_cpu_valid == NULL && | |
3042 | (obj->read_domains & I915_GEM_DOMAIN_CPU) != 0) | |
3043 | return 0; | |
673a394b | 3044 | |
e47c68e9 EA |
3045 | /* Otherwise, create/clear the per-page CPU read domain flag if we're |
3046 | * newly adding I915_GEM_DOMAIN_CPU | |
3047 | */ | |
673a394b | 3048 | if (obj_priv->page_cpu_valid == NULL) { |
9a298b2a EA |
3049 | obj_priv->page_cpu_valid = kzalloc(obj->size / PAGE_SIZE, |
3050 | GFP_KERNEL); | |
e47c68e9 EA |
3051 | if (obj_priv->page_cpu_valid == NULL) |
3052 | return -ENOMEM; | |
3053 | } else if ((obj->read_domains & I915_GEM_DOMAIN_CPU) == 0) | |
3054 | memset(obj_priv->page_cpu_valid, 0, obj->size / PAGE_SIZE); | |
673a394b EA |
3055 | |
3056 | /* Flush the cache on any pages that are still invalid from the CPU's | |
3057 | * perspective. | |
3058 | */ | |
e47c68e9 EA |
3059 | for (i = offset / PAGE_SIZE; i <= (offset + size - 1) / PAGE_SIZE; |
3060 | i++) { | |
673a394b EA |
3061 | if (obj_priv->page_cpu_valid[i]) |
3062 | continue; | |
3063 | ||
856fa198 | 3064 | drm_clflush_pages(obj_priv->pages + i, 1); |
673a394b EA |
3065 | |
3066 | obj_priv->page_cpu_valid[i] = 1; | |
3067 | } | |
3068 | ||
e47c68e9 EA |
3069 | /* It should now be out of any other write domains, and we can update |
3070 | * the domain values for our changes. | |
3071 | */ | |
3072 | BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_CPU) != 0); | |
3073 | ||
1c5d22f7 | 3074 | old_read_domains = obj->read_domains; |
e47c68e9 EA |
3075 | obj->read_domains |= I915_GEM_DOMAIN_CPU; |
3076 | ||
1c5d22f7 CW |
3077 | trace_i915_gem_object_change_domain(obj, |
3078 | old_read_domains, | |
3079 | obj->write_domain); | |
3080 | ||
673a394b EA |
3081 | return 0; |
3082 | } | |
3083 | ||
673a394b EA |
3084 | /** |
3085 | * Pin an object to the GTT and evaluate the relocations landing in it. | |
3086 | */ | |
3087 | static int | |
3088 | i915_gem_object_pin_and_relocate(struct drm_gem_object *obj, | |
3089 | struct drm_file *file_priv, | |
76446cac | 3090 | struct drm_i915_gem_exec_object2 *entry, |
40a5f0de | 3091 | struct drm_i915_gem_relocation_entry *relocs) |
673a394b EA |
3092 | { |
3093 | struct drm_device *dev = obj->dev; | |
0839ccb8 | 3094 | drm_i915_private_t *dev_priv = dev->dev_private; |
23010e43 | 3095 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
673a394b | 3096 | int i, ret; |
0839ccb8 | 3097 | void __iomem *reloc_page; |
76446cac JB |
3098 | bool need_fence; |
3099 | ||
3100 | need_fence = entry->flags & EXEC_OBJECT_NEEDS_FENCE && | |
3101 | obj_priv->tiling_mode != I915_TILING_NONE; | |
3102 | ||
3103 | /* Check fence reg constraints and rebind if necessary */ | |
808b24d6 CW |
3104 | if (need_fence && |
3105 | !i915_gem_object_fence_offset_ok(obj, | |
3106 | obj_priv->tiling_mode)) { | |
3107 | ret = i915_gem_object_unbind(obj); | |
3108 | if (ret) | |
3109 | return ret; | |
3110 | } | |
673a394b EA |
3111 | |
3112 | /* Choose the GTT offset for our buffer and put it there. */ | |
3113 | ret = i915_gem_object_pin(obj, (uint32_t) entry->alignment); | |
3114 | if (ret) | |
3115 | return ret; | |
3116 | ||
76446cac JB |
3117 | /* |
3118 | * Pre-965 chips need a fence register set up in order to | |
3119 | * properly handle blits to/from tiled surfaces. | |
3120 | */ | |
3121 | if (need_fence) { | |
3122 | ret = i915_gem_object_get_fence_reg(obj); | |
3123 | if (ret != 0) { | |
76446cac JB |
3124 | i915_gem_object_unpin(obj); |
3125 | return ret; | |
3126 | } | |
3127 | } | |
3128 | ||
673a394b EA |
3129 | entry->offset = obj_priv->gtt_offset; |
3130 | ||
673a394b EA |
3131 | /* Apply the relocations, using the GTT aperture to avoid cache |
3132 | * flushing requirements. | |
3133 | */ | |
3134 | for (i = 0; i < entry->relocation_count; i++) { | |
40a5f0de | 3135 | struct drm_i915_gem_relocation_entry *reloc= &relocs[i]; |
673a394b EA |
3136 | struct drm_gem_object *target_obj; |
3137 | struct drm_i915_gem_object *target_obj_priv; | |
3043c60c EA |
3138 | uint32_t reloc_val, reloc_offset; |
3139 | uint32_t __iomem *reloc_entry; | |
673a394b | 3140 | |
673a394b | 3141 | target_obj = drm_gem_object_lookup(obj->dev, file_priv, |
40a5f0de | 3142 | reloc->target_handle); |
673a394b EA |
3143 | if (target_obj == NULL) { |
3144 | i915_gem_object_unpin(obj); | |
bf79cb91 | 3145 | return -ENOENT; |
673a394b | 3146 | } |
23010e43 | 3147 | target_obj_priv = to_intel_bo(target_obj); |
673a394b | 3148 | |
8542a0bb CW |
3149 | #if WATCH_RELOC |
3150 | DRM_INFO("%s: obj %p offset %08x target %d " | |
3151 | "read %08x write %08x gtt %08x " | |
3152 | "presumed %08x delta %08x\n", | |
3153 | __func__, | |
3154 | obj, | |
3155 | (int) reloc->offset, | |
3156 | (int) reloc->target_handle, | |
3157 | (int) reloc->read_domains, | |
3158 | (int) reloc->write_domain, | |
3159 | (int) target_obj_priv->gtt_offset, | |
3160 | (int) reloc->presumed_offset, | |
3161 | reloc->delta); | |
3162 | #endif | |
3163 | ||
673a394b EA |
3164 | /* The target buffer should have appeared before us in the |
3165 | * exec_object list, so it should have a GTT space bound by now. | |
3166 | */ | |
3167 | if (target_obj_priv->gtt_space == NULL) { | |
3168 | DRM_ERROR("No GTT space found for object %d\n", | |
40a5f0de | 3169 | reloc->target_handle); |
673a394b EA |
3170 | drm_gem_object_unreference(target_obj); |
3171 | i915_gem_object_unpin(obj); | |
3172 | return -EINVAL; | |
3173 | } | |
3174 | ||
8542a0bb | 3175 | /* Validate that the target is in a valid r/w GPU domain */ |
16edd550 DV |
3176 | if (reloc->write_domain & (reloc->write_domain - 1)) { |
3177 | DRM_ERROR("reloc with multiple write domains: " | |
3178 | "obj %p target %d offset %d " | |
3179 | "read %08x write %08x", | |
3180 | obj, reloc->target_handle, | |
3181 | (int) reloc->offset, | |
3182 | reloc->read_domains, | |
3183 | reloc->write_domain); | |
3184 | return -EINVAL; | |
3185 | } | |
40a5f0de EA |
3186 | if (reloc->write_domain & I915_GEM_DOMAIN_CPU || |
3187 | reloc->read_domains & I915_GEM_DOMAIN_CPU) { | |
e47c68e9 EA |
3188 | DRM_ERROR("reloc with read/write CPU domains: " |
3189 | "obj %p target %d offset %d " | |
3190 | "read %08x write %08x", | |
40a5f0de EA |
3191 | obj, reloc->target_handle, |
3192 | (int) reloc->offset, | |
3193 | reloc->read_domains, | |
3194 | reloc->write_domain); | |
491152b8 CW |
3195 | drm_gem_object_unreference(target_obj); |
3196 | i915_gem_object_unpin(obj); | |
e47c68e9 EA |
3197 | return -EINVAL; |
3198 | } | |
40a5f0de EA |
3199 | if (reloc->write_domain && target_obj->pending_write_domain && |
3200 | reloc->write_domain != target_obj->pending_write_domain) { | |
673a394b EA |
3201 | DRM_ERROR("Write domain conflict: " |
3202 | "obj %p target %d offset %d " | |
3203 | "new %08x old %08x\n", | |
40a5f0de EA |
3204 | obj, reloc->target_handle, |
3205 | (int) reloc->offset, | |
3206 | reloc->write_domain, | |
673a394b EA |
3207 | target_obj->pending_write_domain); |
3208 | drm_gem_object_unreference(target_obj); | |
3209 | i915_gem_object_unpin(obj); | |
3210 | return -EINVAL; | |
3211 | } | |
3212 | ||
40a5f0de EA |
3213 | target_obj->pending_read_domains |= reloc->read_domains; |
3214 | target_obj->pending_write_domain |= reloc->write_domain; | |
673a394b EA |
3215 | |
3216 | /* If the relocation already has the right value in it, no | |
3217 | * more work needs to be done. | |
3218 | */ | |
40a5f0de | 3219 | if (target_obj_priv->gtt_offset == reloc->presumed_offset) { |
673a394b EA |
3220 | drm_gem_object_unreference(target_obj); |
3221 | continue; | |
3222 | } | |
3223 | ||
8542a0bb CW |
3224 | /* Check that the relocation address is valid... */ |
3225 | if (reloc->offset > obj->size - 4) { | |
3226 | DRM_ERROR("Relocation beyond object bounds: " | |
3227 | "obj %p target %d offset %d size %d.\n", | |
3228 | obj, reloc->target_handle, | |
3229 | (int) reloc->offset, (int) obj->size); | |
3230 | drm_gem_object_unreference(target_obj); | |
3231 | i915_gem_object_unpin(obj); | |
3232 | return -EINVAL; | |
3233 | } | |
3234 | if (reloc->offset & 3) { | |
3235 | DRM_ERROR("Relocation not 4-byte aligned: " | |
3236 | "obj %p target %d offset %d.\n", | |
3237 | obj, reloc->target_handle, | |
3238 | (int) reloc->offset); | |
3239 | drm_gem_object_unreference(target_obj); | |
3240 | i915_gem_object_unpin(obj); | |
3241 | return -EINVAL; | |
3242 | } | |
3243 | ||
3244 | /* and points to somewhere within the target object. */ | |
3245 | if (reloc->delta >= target_obj->size) { | |
3246 | DRM_ERROR("Relocation beyond target object bounds: " | |
3247 | "obj %p target %d delta %d size %d.\n", | |
3248 | obj, reloc->target_handle, | |
3249 | (int) reloc->delta, (int) target_obj->size); | |
3250 | drm_gem_object_unreference(target_obj); | |
3251 | i915_gem_object_unpin(obj); | |
3252 | return -EINVAL; | |
3253 | } | |
3254 | ||
2ef7eeaa EA |
3255 | ret = i915_gem_object_set_to_gtt_domain(obj, 1); |
3256 | if (ret != 0) { | |
3257 | drm_gem_object_unreference(target_obj); | |
3258 | i915_gem_object_unpin(obj); | |
3259 | return -EINVAL; | |
673a394b EA |
3260 | } |
3261 | ||
3262 | /* Map the page containing the relocation we're going to | |
3263 | * perform. | |
3264 | */ | |
40a5f0de | 3265 | reloc_offset = obj_priv->gtt_offset + reloc->offset; |
0839ccb8 KP |
3266 | reloc_page = io_mapping_map_atomic_wc(dev_priv->mm.gtt_mapping, |
3267 | (reloc_offset & | |
fca3ec01 CW |
3268 | ~(PAGE_SIZE - 1)), |
3269 | KM_USER0); | |
3043c60c | 3270 | reloc_entry = (uint32_t __iomem *)(reloc_page + |
0839ccb8 | 3271 | (reloc_offset & (PAGE_SIZE - 1))); |
40a5f0de | 3272 | reloc_val = target_obj_priv->gtt_offset + reloc->delta; |
673a394b EA |
3273 | |
3274 | #if WATCH_BUF | |
3275 | DRM_INFO("Applied relocation: %p@0x%08x %08x -> %08x\n", | |
40a5f0de | 3276 | obj, (unsigned int) reloc->offset, |
673a394b EA |
3277 | readl(reloc_entry), reloc_val); |
3278 | #endif | |
3279 | writel(reloc_val, reloc_entry); | |
fca3ec01 | 3280 | io_mapping_unmap_atomic(reloc_page, KM_USER0); |
673a394b | 3281 | |
40a5f0de EA |
3282 | /* The updated presumed offset for this entry will be |
3283 | * copied back out to the user. | |
673a394b | 3284 | */ |
40a5f0de | 3285 | reloc->presumed_offset = target_obj_priv->gtt_offset; |
673a394b EA |
3286 | |
3287 | drm_gem_object_unreference(target_obj); | |
3288 | } | |
3289 | ||
673a394b EA |
3290 | #if WATCH_BUF |
3291 | if (0) | |
3292 | i915_gem_dump_object(obj, 128, __func__, ~0); | |
3293 | #endif | |
3294 | return 0; | |
3295 | } | |
3296 | ||
673a394b EA |
3297 | /* Throttle our rendering by waiting until the ring has completed our requests |
3298 | * emitted over 20 msec ago. | |
3299 | * | |
b962442e EA |
3300 | * Note that if we were to use the current jiffies each time around the loop, |
3301 | * we wouldn't escape the function with any frames outstanding if the time to | |
3302 | * render a frame was over 20ms. | |
3303 | * | |
673a394b EA |
3304 | * This should get us reasonable parallelism between CPU and GPU but also |
3305 | * relatively low latency when blocking on a particular request to finish. | |
3306 | */ | |
3307 | static int | |
3308 | i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file_priv) | |
3309 | { | |
3310 | struct drm_i915_file_private *i915_file_priv = file_priv->driver_priv; | |
3311 | int ret = 0; | |
b962442e | 3312 | unsigned long recent_enough = jiffies - msecs_to_jiffies(20); |
673a394b EA |
3313 | |
3314 | mutex_lock(&dev->struct_mutex); | |
b962442e EA |
3315 | while (!list_empty(&i915_file_priv->mm.request_list)) { |
3316 | struct drm_i915_gem_request *request; | |
3317 | ||
3318 | request = list_first_entry(&i915_file_priv->mm.request_list, | |
3319 | struct drm_i915_gem_request, | |
3320 | client_list); | |
3321 | ||
3322 | if (time_after_eq(request->emitted_jiffies, recent_enough)) | |
3323 | break; | |
3324 | ||
852835f3 | 3325 | ret = i915_wait_request(dev, request->seqno, request->ring); |
b962442e EA |
3326 | if (ret != 0) |
3327 | break; | |
3328 | } | |
673a394b | 3329 | mutex_unlock(&dev->struct_mutex); |
b962442e | 3330 | |
673a394b EA |
3331 | return ret; |
3332 | } | |
3333 | ||
40a5f0de | 3334 | static int |
76446cac | 3335 | i915_gem_get_relocs_from_user(struct drm_i915_gem_exec_object2 *exec_list, |
40a5f0de EA |
3336 | uint32_t buffer_count, |
3337 | struct drm_i915_gem_relocation_entry **relocs) | |
3338 | { | |
3339 | uint32_t reloc_count = 0, reloc_index = 0, i; | |
3340 | int ret; | |
3341 | ||
3342 | *relocs = NULL; | |
3343 | for (i = 0; i < buffer_count; i++) { | |
3344 | if (reloc_count + exec_list[i].relocation_count < reloc_count) | |
3345 | return -EINVAL; | |
3346 | reloc_count += exec_list[i].relocation_count; | |
3347 | } | |
3348 | ||
8e7d2b2c | 3349 | *relocs = drm_calloc_large(reloc_count, sizeof(**relocs)); |
76446cac JB |
3350 | if (*relocs == NULL) { |
3351 | DRM_ERROR("failed to alloc relocs, count %d\n", reloc_count); | |
40a5f0de | 3352 | return -ENOMEM; |
76446cac | 3353 | } |
40a5f0de EA |
3354 | |
3355 | for (i = 0; i < buffer_count; i++) { | |
3356 | struct drm_i915_gem_relocation_entry __user *user_relocs; | |
3357 | ||
3358 | user_relocs = (void __user *)(uintptr_t)exec_list[i].relocs_ptr; | |
3359 | ||
3360 | ret = copy_from_user(&(*relocs)[reloc_index], | |
3361 | user_relocs, | |
3362 | exec_list[i].relocation_count * | |
3363 | sizeof(**relocs)); | |
3364 | if (ret != 0) { | |
8e7d2b2c | 3365 | drm_free_large(*relocs); |
40a5f0de | 3366 | *relocs = NULL; |
2bc43b5c | 3367 | return -EFAULT; |
40a5f0de EA |
3368 | } |
3369 | ||
3370 | reloc_index += exec_list[i].relocation_count; | |
3371 | } | |
3372 | ||
2bc43b5c | 3373 | return 0; |
40a5f0de EA |
3374 | } |
3375 | ||
3376 | static int | |
76446cac | 3377 | i915_gem_put_relocs_to_user(struct drm_i915_gem_exec_object2 *exec_list, |
40a5f0de EA |
3378 | uint32_t buffer_count, |
3379 | struct drm_i915_gem_relocation_entry *relocs) | |
3380 | { | |
3381 | uint32_t reloc_count = 0, i; | |
2bc43b5c | 3382 | int ret = 0; |
40a5f0de | 3383 | |
93533c29 CW |
3384 | if (relocs == NULL) |
3385 | return 0; | |
3386 | ||
40a5f0de EA |
3387 | for (i = 0; i < buffer_count; i++) { |
3388 | struct drm_i915_gem_relocation_entry __user *user_relocs; | |
2bc43b5c | 3389 | int unwritten; |
40a5f0de EA |
3390 | |
3391 | user_relocs = (void __user *)(uintptr_t)exec_list[i].relocs_ptr; | |
3392 | ||
2bc43b5c FM |
3393 | unwritten = copy_to_user(user_relocs, |
3394 | &relocs[reloc_count], | |
3395 | exec_list[i].relocation_count * | |
3396 | sizeof(*relocs)); | |
3397 | ||
3398 | if (unwritten) { | |
3399 | ret = -EFAULT; | |
3400 | goto err; | |
40a5f0de EA |
3401 | } |
3402 | ||
3403 | reloc_count += exec_list[i].relocation_count; | |
3404 | } | |
3405 | ||
2bc43b5c | 3406 | err: |
8e7d2b2c | 3407 | drm_free_large(relocs); |
40a5f0de EA |
3408 | |
3409 | return ret; | |
3410 | } | |
3411 | ||
83d60795 | 3412 | static int |
76446cac | 3413 | i915_gem_check_execbuffer (struct drm_i915_gem_execbuffer2 *exec, |
83d60795 CW |
3414 | uint64_t exec_offset) |
3415 | { | |
3416 | uint32_t exec_start, exec_len; | |
3417 | ||
3418 | exec_start = (uint32_t) exec_offset + exec->batch_start_offset; | |
3419 | exec_len = (uint32_t) exec->batch_len; | |
3420 | ||
3421 | if ((exec_start | exec_len) & 0x7) | |
3422 | return -EINVAL; | |
3423 | ||
3424 | if (!exec_start) | |
3425 | return -EINVAL; | |
3426 | ||
3427 | return 0; | |
3428 | } | |
3429 | ||
6b95a207 KH |
3430 | static int |
3431 | i915_gem_wait_for_pending_flip(struct drm_device *dev, | |
3432 | struct drm_gem_object **object_list, | |
3433 | int count) | |
3434 | { | |
3435 | drm_i915_private_t *dev_priv = dev->dev_private; | |
3436 | struct drm_i915_gem_object *obj_priv; | |
3437 | DEFINE_WAIT(wait); | |
3438 | int i, ret = 0; | |
3439 | ||
3440 | for (;;) { | |
3441 | prepare_to_wait(&dev_priv->pending_flip_queue, | |
3442 | &wait, TASK_INTERRUPTIBLE); | |
3443 | for (i = 0; i < count; i++) { | |
23010e43 | 3444 | obj_priv = to_intel_bo(object_list[i]); |
6b95a207 KH |
3445 | if (atomic_read(&obj_priv->pending_flip) > 0) |
3446 | break; | |
3447 | } | |
3448 | if (i == count) | |
3449 | break; | |
3450 | ||
3451 | if (!signal_pending(current)) { | |
3452 | mutex_unlock(&dev->struct_mutex); | |
3453 | schedule(); | |
3454 | mutex_lock(&dev->struct_mutex); | |
3455 | continue; | |
3456 | } | |
3457 | ret = -ERESTARTSYS; | |
3458 | break; | |
3459 | } | |
3460 | finish_wait(&dev_priv->pending_flip_queue, &wait); | |
3461 | ||
3462 | return ret; | |
3463 | } | |
3464 | ||
8dc5d147 | 3465 | static int |
76446cac JB |
3466 | i915_gem_do_execbuffer(struct drm_device *dev, void *data, |
3467 | struct drm_file *file_priv, | |
3468 | struct drm_i915_gem_execbuffer2 *args, | |
3469 | struct drm_i915_gem_exec_object2 *exec_list) | |
673a394b EA |
3470 | { |
3471 | drm_i915_private_t *dev_priv = dev->dev_private; | |
673a394b EA |
3472 | struct drm_gem_object **object_list = NULL; |
3473 | struct drm_gem_object *batch_obj; | |
b70d11da | 3474 | struct drm_i915_gem_object *obj_priv; |
201361a5 | 3475 | struct drm_clip_rect *cliprects = NULL; |
93533c29 | 3476 | struct drm_i915_gem_relocation_entry *relocs = NULL; |
8dc5d147 | 3477 | struct drm_i915_gem_request *request = NULL; |
76446cac | 3478 | int ret = 0, ret2, i, pinned = 0; |
673a394b | 3479 | uint64_t exec_offset; |
8a1a49f9 | 3480 | uint32_t seqno, reloc_index; |
6b95a207 | 3481 | int pin_tries, flips; |
673a394b | 3482 | |
852835f3 ZN |
3483 | struct intel_ring_buffer *ring = NULL; |
3484 | ||
673a394b EA |
3485 | #if WATCH_EXEC |
3486 | DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n", | |
3487 | (int) args->buffers_ptr, args->buffer_count, args->batch_len); | |
3488 | #endif | |
d1b851fc ZN |
3489 | if (args->flags & I915_EXEC_BSD) { |
3490 | if (!HAS_BSD(dev)) { | |
3491 | DRM_ERROR("execbuf with wrong flag\n"); | |
3492 | return -EINVAL; | |
3493 | } | |
3494 | ring = &dev_priv->bsd_ring; | |
3495 | } else { | |
3496 | ring = &dev_priv->render_ring; | |
3497 | } | |
3498 | ||
4f481ed2 EA |
3499 | if (args->buffer_count < 1) { |
3500 | DRM_ERROR("execbuf with %d buffers\n", args->buffer_count); | |
3501 | return -EINVAL; | |
3502 | } | |
c8e0f93a | 3503 | object_list = drm_malloc_ab(sizeof(*object_list), args->buffer_count); |
76446cac JB |
3504 | if (object_list == NULL) { |
3505 | DRM_ERROR("Failed to allocate object list for %d buffers\n", | |
673a394b EA |
3506 | args->buffer_count); |
3507 | ret = -ENOMEM; | |
3508 | goto pre_mutex_err; | |
3509 | } | |
673a394b | 3510 | |
201361a5 | 3511 | if (args->num_cliprects != 0) { |
9a298b2a EA |
3512 | cliprects = kcalloc(args->num_cliprects, sizeof(*cliprects), |
3513 | GFP_KERNEL); | |
a40e8d31 OA |
3514 | if (cliprects == NULL) { |
3515 | ret = -ENOMEM; | |
201361a5 | 3516 | goto pre_mutex_err; |
a40e8d31 | 3517 | } |
201361a5 EA |
3518 | |
3519 | ret = copy_from_user(cliprects, | |
3520 | (struct drm_clip_rect __user *) | |
3521 | (uintptr_t) args->cliprects_ptr, | |
3522 | sizeof(*cliprects) * args->num_cliprects); | |
3523 | if (ret != 0) { | |
3524 | DRM_ERROR("copy %d cliprects failed: %d\n", | |
3525 | args->num_cliprects, ret); | |
c877cdce | 3526 | ret = -EFAULT; |
201361a5 EA |
3527 | goto pre_mutex_err; |
3528 | } | |
3529 | } | |
3530 | ||
8dc5d147 CW |
3531 | request = kzalloc(sizeof(*request), GFP_KERNEL); |
3532 | if (request == NULL) { | |
3533 | ret = -ENOMEM; | |
3534 | goto pre_mutex_err; | |
3535 | } | |
3536 | ||
40a5f0de EA |
3537 | ret = i915_gem_get_relocs_from_user(exec_list, args->buffer_count, |
3538 | &relocs); | |
3539 | if (ret != 0) | |
3540 | goto pre_mutex_err; | |
3541 | ||
673a394b EA |
3542 | mutex_lock(&dev->struct_mutex); |
3543 | ||
3544 | i915_verify_inactive(dev, __FILE__, __LINE__); | |
3545 | ||
ba1234d1 | 3546 | if (atomic_read(&dev_priv->mm.wedged)) { |
673a394b | 3547 | mutex_unlock(&dev->struct_mutex); |
a198bc80 CW |
3548 | ret = -EIO; |
3549 | goto pre_mutex_err; | |
673a394b EA |
3550 | } |
3551 | ||
3552 | if (dev_priv->mm.suspended) { | |
673a394b | 3553 | mutex_unlock(&dev->struct_mutex); |
a198bc80 CW |
3554 | ret = -EBUSY; |
3555 | goto pre_mutex_err; | |
673a394b EA |
3556 | } |
3557 | ||
ac94a962 | 3558 | /* Look up object handles */ |
6b95a207 | 3559 | flips = 0; |
673a394b EA |
3560 | for (i = 0; i < args->buffer_count; i++) { |
3561 | object_list[i] = drm_gem_object_lookup(dev, file_priv, | |
3562 | exec_list[i].handle); | |
3563 | if (object_list[i] == NULL) { | |
3564 | DRM_ERROR("Invalid object handle %d at index %d\n", | |
3565 | exec_list[i].handle, i); | |
0ce907f8 CW |
3566 | /* prevent error path from reading uninitialized data */ |
3567 | args->buffer_count = i + 1; | |
bf79cb91 | 3568 | ret = -ENOENT; |
673a394b EA |
3569 | goto err; |
3570 | } | |
b70d11da | 3571 | |
23010e43 | 3572 | obj_priv = to_intel_bo(object_list[i]); |
b70d11da KH |
3573 | if (obj_priv->in_execbuffer) { |
3574 | DRM_ERROR("Object %p appears more than once in object list\n", | |
3575 | object_list[i]); | |
0ce907f8 CW |
3576 | /* prevent error path from reading uninitialized data */ |
3577 | args->buffer_count = i + 1; | |
bf79cb91 | 3578 | ret = -EINVAL; |
b70d11da KH |
3579 | goto err; |
3580 | } | |
3581 | obj_priv->in_execbuffer = true; | |
6b95a207 KH |
3582 | flips += atomic_read(&obj_priv->pending_flip); |
3583 | } | |
3584 | ||
3585 | if (flips > 0) { | |
3586 | ret = i915_gem_wait_for_pending_flip(dev, object_list, | |
3587 | args->buffer_count); | |
3588 | if (ret) | |
3589 | goto err; | |
ac94a962 | 3590 | } |
673a394b | 3591 | |
ac94a962 KP |
3592 | /* Pin and relocate */ |
3593 | for (pin_tries = 0; ; pin_tries++) { | |
3594 | ret = 0; | |
40a5f0de EA |
3595 | reloc_index = 0; |
3596 | ||
ac94a962 KP |
3597 | for (i = 0; i < args->buffer_count; i++) { |
3598 | object_list[i]->pending_read_domains = 0; | |
3599 | object_list[i]->pending_write_domain = 0; | |
3600 | ret = i915_gem_object_pin_and_relocate(object_list[i], | |
3601 | file_priv, | |
40a5f0de EA |
3602 | &exec_list[i], |
3603 | &relocs[reloc_index]); | |
ac94a962 KP |
3604 | if (ret) |
3605 | break; | |
3606 | pinned = i + 1; | |
40a5f0de | 3607 | reloc_index += exec_list[i].relocation_count; |
ac94a962 KP |
3608 | } |
3609 | /* success */ | |
3610 | if (ret == 0) | |
3611 | break; | |
3612 | ||
3613 | /* error other than GTT full, or we've already tried again */ | |
2939e1f5 | 3614 | if (ret != -ENOSPC || pin_tries >= 1) { |
07f73f69 CW |
3615 | if (ret != -ERESTARTSYS) { |
3616 | unsigned long long total_size = 0; | |
3d1cc470 CW |
3617 | int num_fences = 0; |
3618 | for (i = 0; i < args->buffer_count; i++) { | |
43b27f40 | 3619 | obj_priv = to_intel_bo(object_list[i]); |
3d1cc470 | 3620 | |
07f73f69 | 3621 | total_size += object_list[i]->size; |
3d1cc470 CW |
3622 | num_fences += |
3623 | exec_list[i].flags & EXEC_OBJECT_NEEDS_FENCE && | |
3624 | obj_priv->tiling_mode != I915_TILING_NONE; | |
3625 | } | |
3626 | DRM_ERROR("Failed to pin buffer %d of %d, total %llu bytes, %d fences: %d\n", | |
07f73f69 | 3627 | pinned+1, args->buffer_count, |
3d1cc470 CW |
3628 | total_size, num_fences, |
3629 | ret); | |
07f73f69 CW |
3630 | DRM_ERROR("%d objects [%d pinned], " |
3631 | "%d object bytes [%d pinned], " | |
3632 | "%d/%d gtt bytes\n", | |
3633 | atomic_read(&dev->object_count), | |
3634 | atomic_read(&dev->pin_count), | |
3635 | atomic_read(&dev->object_memory), | |
3636 | atomic_read(&dev->pin_memory), | |
3637 | atomic_read(&dev->gtt_memory), | |
3638 | dev->gtt_total); | |
3639 | } | |
673a394b EA |
3640 | goto err; |
3641 | } | |
ac94a962 KP |
3642 | |
3643 | /* unpin all of our buffers */ | |
3644 | for (i = 0; i < pinned; i++) | |
3645 | i915_gem_object_unpin(object_list[i]); | |
b1177636 | 3646 | pinned = 0; |
ac94a962 KP |
3647 | |
3648 | /* evict everyone we can from the aperture */ | |
3649 | ret = i915_gem_evict_everything(dev); | |
07f73f69 | 3650 | if (ret && ret != -ENOSPC) |
ac94a962 | 3651 | goto err; |
673a394b EA |
3652 | } |
3653 | ||
3654 | /* Set the pending read domains for the batch buffer to COMMAND */ | |
3655 | batch_obj = object_list[args->buffer_count-1]; | |
5f26a2c7 CW |
3656 | if (batch_obj->pending_write_domain) { |
3657 | DRM_ERROR("Attempting to use self-modifying batch buffer\n"); | |
3658 | ret = -EINVAL; | |
3659 | goto err; | |
3660 | } | |
3661 | batch_obj->pending_read_domains |= I915_GEM_DOMAIN_COMMAND; | |
673a394b | 3662 | |
83d60795 CW |
3663 | /* Sanity check the batch buffer, prior to moving objects */ |
3664 | exec_offset = exec_list[args->buffer_count - 1].offset; | |
3665 | ret = i915_gem_check_execbuffer (args, exec_offset); | |
3666 | if (ret != 0) { | |
3667 | DRM_ERROR("execbuf with invalid offset/length\n"); | |
3668 | goto err; | |
3669 | } | |
3670 | ||
673a394b EA |
3671 | i915_verify_inactive(dev, __FILE__, __LINE__); |
3672 | ||
646f0f6e KP |
3673 | /* Zero the global flush/invalidate flags. These |
3674 | * will be modified as new domains are computed | |
3675 | * for each object | |
3676 | */ | |
3677 | dev->invalidate_domains = 0; | |
3678 | dev->flush_domains = 0; | |
3679 | ||
673a394b EA |
3680 | for (i = 0; i < args->buffer_count; i++) { |
3681 | struct drm_gem_object *obj = object_list[i]; | |
673a394b | 3682 | |
646f0f6e | 3683 | /* Compute new gpu domains and update invalidate/flush */ |
8b0e378a | 3684 | i915_gem_object_set_to_gpu_domain(obj); |
673a394b EA |
3685 | } |
3686 | ||
3687 | i915_verify_inactive(dev, __FILE__, __LINE__); | |
3688 | ||
646f0f6e KP |
3689 | if (dev->invalidate_domains | dev->flush_domains) { |
3690 | #if WATCH_EXEC | |
3691 | DRM_INFO("%s: invalidate_domains %08x flush_domains %08x\n", | |
3692 | __func__, | |
3693 | dev->invalidate_domains, | |
3694 | dev->flush_domains); | |
3695 | #endif | |
3696 | i915_gem_flush(dev, | |
3697 | dev->invalidate_domains, | |
3698 | dev->flush_domains); | |
a6910434 DV |
3699 | } |
3700 | ||
3701 | if (dev_priv->render_ring.outstanding_lazy_request) { | |
8dc5d147 | 3702 | (void)i915_add_request(dev, file_priv, NULL, &dev_priv->render_ring); |
a6910434 DV |
3703 | dev_priv->render_ring.outstanding_lazy_request = false; |
3704 | } | |
3705 | if (dev_priv->bsd_ring.outstanding_lazy_request) { | |
8dc5d147 | 3706 | (void)i915_add_request(dev, file_priv, NULL, &dev_priv->bsd_ring); |
a6910434 | 3707 | dev_priv->bsd_ring.outstanding_lazy_request = false; |
646f0f6e | 3708 | } |
673a394b | 3709 | |
efbeed96 EA |
3710 | for (i = 0; i < args->buffer_count; i++) { |
3711 | struct drm_gem_object *obj = object_list[i]; | |
23010e43 | 3712 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
1c5d22f7 | 3713 | uint32_t old_write_domain = obj->write_domain; |
efbeed96 EA |
3714 | |
3715 | obj->write_domain = obj->pending_write_domain; | |
99fcb766 DV |
3716 | if (obj->write_domain) |
3717 | list_move_tail(&obj_priv->gpu_write_list, | |
3718 | &dev_priv->mm.gpu_write_list); | |
3719 | else | |
3720 | list_del_init(&obj_priv->gpu_write_list); | |
3721 | ||
1c5d22f7 CW |
3722 | trace_i915_gem_object_change_domain(obj, |
3723 | obj->read_domains, | |
3724 | old_write_domain); | |
efbeed96 EA |
3725 | } |
3726 | ||
673a394b EA |
3727 | i915_verify_inactive(dev, __FILE__, __LINE__); |
3728 | ||
3729 | #if WATCH_COHERENCY | |
3730 | for (i = 0; i < args->buffer_count; i++) { | |
3731 | i915_gem_object_check_coherency(object_list[i], | |
3732 | exec_list[i].handle); | |
3733 | } | |
3734 | #endif | |
3735 | ||
673a394b | 3736 | #if WATCH_EXEC |
6911a9b8 | 3737 | i915_gem_dump_object(batch_obj, |
673a394b EA |
3738 | args->batch_len, |
3739 | __func__, | |
3740 | ~0); | |
3741 | #endif | |
3742 | ||
673a394b | 3743 | /* Exec the batchbuffer */ |
852835f3 ZN |
3744 | ret = ring->dispatch_gem_execbuffer(dev, ring, args, |
3745 | cliprects, exec_offset); | |
673a394b EA |
3746 | if (ret) { |
3747 | DRM_ERROR("dispatch failed %d\n", ret); | |
3748 | goto err; | |
3749 | } | |
3750 | ||
3751 | /* | |
3752 | * Ensure that the commands in the batch buffer are | |
3753 | * finished before the interrupt fires | |
3754 | */ | |
8a1a49f9 | 3755 | i915_retire_commands(dev, ring); |
673a394b EA |
3756 | |
3757 | i915_verify_inactive(dev, __FILE__, __LINE__); | |
3758 | ||
617dbe27 DV |
3759 | for (i = 0; i < args->buffer_count; i++) { |
3760 | struct drm_gem_object *obj = object_list[i]; | |
3761 | obj_priv = to_intel_bo(obj); | |
3762 | ||
3763 | i915_gem_object_move_to_active(obj, ring); | |
3764 | #if WATCH_LRU | |
3765 | DRM_INFO("%s: move to exec list %p\n", __func__, obj); | |
3766 | #endif | |
3767 | } | |
3768 | ||
673a394b EA |
3769 | /* |
3770 | * Get a seqno representing the execution of the current buffer, | |
3771 | * which we can wait on. We would like to mitigate these interrupts, | |
3772 | * likely by only creating seqnos occasionally (so that we have | |
3773 | * *some* interrupts representing completion of buffers that we can | |
3774 | * wait on when trying to clear up gtt space). | |
3775 | */ | |
8dc5d147 CW |
3776 | seqno = i915_add_request(dev, file_priv, request, ring); |
3777 | request = NULL; | |
673a394b | 3778 | |
673a394b EA |
3779 | #if WATCH_LRU |
3780 | i915_dump_lru(dev, __func__); | |
3781 | #endif | |
3782 | ||
3783 | i915_verify_inactive(dev, __FILE__, __LINE__); | |
3784 | ||
673a394b | 3785 | err: |
aad87dff JL |
3786 | for (i = 0; i < pinned; i++) |
3787 | i915_gem_object_unpin(object_list[i]); | |
3788 | ||
b70d11da KH |
3789 | for (i = 0; i < args->buffer_count; i++) { |
3790 | if (object_list[i]) { | |
23010e43 | 3791 | obj_priv = to_intel_bo(object_list[i]); |
b70d11da KH |
3792 | obj_priv->in_execbuffer = false; |
3793 | } | |
aad87dff | 3794 | drm_gem_object_unreference(object_list[i]); |
b70d11da | 3795 | } |
673a394b | 3796 | |
673a394b EA |
3797 | mutex_unlock(&dev->struct_mutex); |
3798 | ||
93533c29 | 3799 | pre_mutex_err: |
40a5f0de EA |
3800 | /* Copy the updated relocations out regardless of current error |
3801 | * state. Failure to update the relocs would mean that the next | |
3802 | * time userland calls execbuf, it would do so with presumed offset | |
3803 | * state that didn't match the actual object state. | |
3804 | */ | |
3805 | ret2 = i915_gem_put_relocs_to_user(exec_list, args->buffer_count, | |
3806 | relocs); | |
3807 | if (ret2 != 0) { | |
3808 | DRM_ERROR("Failed to copy relocations back out: %d\n", ret2); | |
3809 | ||
3810 | if (ret == 0) | |
3811 | ret = ret2; | |
3812 | } | |
3813 | ||
8e7d2b2c | 3814 | drm_free_large(object_list); |
9a298b2a | 3815 | kfree(cliprects); |
8dc5d147 | 3816 | kfree(request); |
673a394b EA |
3817 | |
3818 | return ret; | |
3819 | } | |
3820 | ||
76446cac JB |
3821 | /* |
3822 | * Legacy execbuffer just creates an exec2 list from the original exec object | |
3823 | * list array and passes it to the real function. | |
3824 | */ | |
3825 | int | |
3826 | i915_gem_execbuffer(struct drm_device *dev, void *data, | |
3827 | struct drm_file *file_priv) | |
3828 | { | |
3829 | struct drm_i915_gem_execbuffer *args = data; | |
3830 | struct drm_i915_gem_execbuffer2 exec2; | |
3831 | struct drm_i915_gem_exec_object *exec_list = NULL; | |
3832 | struct drm_i915_gem_exec_object2 *exec2_list = NULL; | |
3833 | int ret, i; | |
3834 | ||
3835 | #if WATCH_EXEC | |
3836 | DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n", | |
3837 | (int) args->buffers_ptr, args->buffer_count, args->batch_len); | |
3838 | #endif | |
3839 | ||
3840 | if (args->buffer_count < 1) { | |
3841 | DRM_ERROR("execbuf with %d buffers\n", args->buffer_count); | |
3842 | return -EINVAL; | |
3843 | } | |
3844 | ||
3845 | /* Copy in the exec list from userland */ | |
3846 | exec_list = drm_malloc_ab(sizeof(*exec_list), args->buffer_count); | |
3847 | exec2_list = drm_malloc_ab(sizeof(*exec2_list), args->buffer_count); | |
3848 | if (exec_list == NULL || exec2_list == NULL) { | |
3849 | DRM_ERROR("Failed to allocate exec list for %d buffers\n", | |
3850 | args->buffer_count); | |
3851 | drm_free_large(exec_list); | |
3852 | drm_free_large(exec2_list); | |
3853 | return -ENOMEM; | |
3854 | } | |
3855 | ret = copy_from_user(exec_list, | |
3856 | (struct drm_i915_relocation_entry __user *) | |
3857 | (uintptr_t) args->buffers_ptr, | |
3858 | sizeof(*exec_list) * args->buffer_count); | |
3859 | if (ret != 0) { | |
3860 | DRM_ERROR("copy %d exec entries failed %d\n", | |
3861 | args->buffer_count, ret); | |
3862 | drm_free_large(exec_list); | |
3863 | drm_free_large(exec2_list); | |
3864 | return -EFAULT; | |
3865 | } | |
3866 | ||
3867 | for (i = 0; i < args->buffer_count; i++) { | |
3868 | exec2_list[i].handle = exec_list[i].handle; | |
3869 | exec2_list[i].relocation_count = exec_list[i].relocation_count; | |
3870 | exec2_list[i].relocs_ptr = exec_list[i].relocs_ptr; | |
3871 | exec2_list[i].alignment = exec_list[i].alignment; | |
3872 | exec2_list[i].offset = exec_list[i].offset; | |
3873 | if (!IS_I965G(dev)) | |
3874 | exec2_list[i].flags = EXEC_OBJECT_NEEDS_FENCE; | |
3875 | else | |
3876 | exec2_list[i].flags = 0; | |
3877 | } | |
3878 | ||
3879 | exec2.buffers_ptr = args->buffers_ptr; | |
3880 | exec2.buffer_count = args->buffer_count; | |
3881 | exec2.batch_start_offset = args->batch_start_offset; | |
3882 | exec2.batch_len = args->batch_len; | |
3883 | exec2.DR1 = args->DR1; | |
3884 | exec2.DR4 = args->DR4; | |
3885 | exec2.num_cliprects = args->num_cliprects; | |
3886 | exec2.cliprects_ptr = args->cliprects_ptr; | |
852835f3 | 3887 | exec2.flags = I915_EXEC_RENDER; |
76446cac JB |
3888 | |
3889 | ret = i915_gem_do_execbuffer(dev, data, file_priv, &exec2, exec2_list); | |
3890 | if (!ret) { | |
3891 | /* Copy the new buffer offsets back to the user's exec list. */ | |
3892 | for (i = 0; i < args->buffer_count; i++) | |
3893 | exec_list[i].offset = exec2_list[i].offset; | |
3894 | /* ... and back out to userspace */ | |
3895 | ret = copy_to_user((struct drm_i915_relocation_entry __user *) | |
3896 | (uintptr_t) args->buffers_ptr, | |
3897 | exec_list, | |
3898 | sizeof(*exec_list) * args->buffer_count); | |
3899 | if (ret) { | |
3900 | ret = -EFAULT; | |
3901 | DRM_ERROR("failed to copy %d exec entries " | |
3902 | "back to user (%d)\n", | |
3903 | args->buffer_count, ret); | |
3904 | } | |
76446cac JB |
3905 | } |
3906 | ||
3907 | drm_free_large(exec_list); | |
3908 | drm_free_large(exec2_list); | |
3909 | return ret; | |
3910 | } | |
3911 | ||
3912 | int | |
3913 | i915_gem_execbuffer2(struct drm_device *dev, void *data, | |
3914 | struct drm_file *file_priv) | |
3915 | { | |
3916 | struct drm_i915_gem_execbuffer2 *args = data; | |
3917 | struct drm_i915_gem_exec_object2 *exec2_list = NULL; | |
3918 | int ret; | |
3919 | ||
3920 | #if WATCH_EXEC | |
3921 | DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n", | |
3922 | (int) args->buffers_ptr, args->buffer_count, args->batch_len); | |
3923 | #endif | |
3924 | ||
3925 | if (args->buffer_count < 1) { | |
3926 | DRM_ERROR("execbuf2 with %d buffers\n", args->buffer_count); | |
3927 | return -EINVAL; | |
3928 | } | |
3929 | ||
3930 | exec2_list = drm_malloc_ab(sizeof(*exec2_list), args->buffer_count); | |
3931 | if (exec2_list == NULL) { | |
3932 | DRM_ERROR("Failed to allocate exec list for %d buffers\n", | |
3933 | args->buffer_count); | |
3934 | return -ENOMEM; | |
3935 | } | |
3936 | ret = copy_from_user(exec2_list, | |
3937 | (struct drm_i915_relocation_entry __user *) | |
3938 | (uintptr_t) args->buffers_ptr, | |
3939 | sizeof(*exec2_list) * args->buffer_count); | |
3940 | if (ret != 0) { | |
3941 | DRM_ERROR("copy %d exec entries failed %d\n", | |
3942 | args->buffer_count, ret); | |
3943 | drm_free_large(exec2_list); | |
3944 | return -EFAULT; | |
3945 | } | |
3946 | ||
3947 | ret = i915_gem_do_execbuffer(dev, data, file_priv, args, exec2_list); | |
3948 | if (!ret) { | |
3949 | /* Copy the new buffer offsets back to the user's exec list. */ | |
3950 | ret = copy_to_user((struct drm_i915_relocation_entry __user *) | |
3951 | (uintptr_t) args->buffers_ptr, | |
3952 | exec2_list, | |
3953 | sizeof(*exec2_list) * args->buffer_count); | |
3954 | if (ret) { | |
3955 | ret = -EFAULT; | |
3956 | DRM_ERROR("failed to copy %d exec entries " | |
3957 | "back to user (%d)\n", | |
3958 | args->buffer_count, ret); | |
3959 | } | |
3960 | } | |
3961 | ||
3962 | drm_free_large(exec2_list); | |
3963 | return ret; | |
3964 | } | |
3965 | ||
673a394b EA |
3966 | int |
3967 | i915_gem_object_pin(struct drm_gem_object *obj, uint32_t alignment) | |
3968 | { | |
3969 | struct drm_device *dev = obj->dev; | |
23010e43 | 3970 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
673a394b EA |
3971 | int ret; |
3972 | ||
778c3544 DV |
3973 | BUG_ON(obj_priv->pin_count == DRM_I915_GEM_OBJECT_MAX_PIN_COUNT); |
3974 | ||
673a394b | 3975 | i915_verify_inactive(dev, __FILE__, __LINE__); |
ac0c6b5a CW |
3976 | |
3977 | if (obj_priv->gtt_space != NULL) { | |
3978 | if (alignment == 0) | |
3979 | alignment = i915_gem_get_gtt_alignment(obj); | |
3980 | if (obj_priv->gtt_offset & (alignment - 1)) { | |
ae7d49d8 CW |
3981 | WARN(obj_priv->pin_count, |
3982 | "bo is already pinned with incorrect alignment:" | |
3983 | " offset=%x, req.alignment=%x\n", | |
3984 | obj_priv->gtt_offset, alignment); | |
ac0c6b5a CW |
3985 | ret = i915_gem_object_unbind(obj); |
3986 | if (ret) | |
3987 | return ret; | |
3988 | } | |
3989 | } | |
3990 | ||
673a394b EA |
3991 | if (obj_priv->gtt_space == NULL) { |
3992 | ret = i915_gem_object_bind_to_gtt(obj, alignment); | |
9731129c | 3993 | if (ret) |
673a394b | 3994 | return ret; |
22c344e9 | 3995 | } |
76446cac | 3996 | |
673a394b EA |
3997 | obj_priv->pin_count++; |
3998 | ||
3999 | /* If the object is not active and not pending a flush, | |
4000 | * remove it from the inactive list | |
4001 | */ | |
4002 | if (obj_priv->pin_count == 1) { | |
4003 | atomic_inc(&dev->pin_count); | |
4004 | atomic_add(obj->size, &dev->pin_memory); | |
4005 | if (!obj_priv->active && | |
bf1a1092 | 4006 | (obj->write_domain & I915_GEM_GPU_DOMAINS) == 0) |
673a394b EA |
4007 | list_del_init(&obj_priv->list); |
4008 | } | |
4009 | i915_verify_inactive(dev, __FILE__, __LINE__); | |
4010 | ||
4011 | return 0; | |
4012 | } | |
4013 | ||
4014 | void | |
4015 | i915_gem_object_unpin(struct drm_gem_object *obj) | |
4016 | { | |
4017 | struct drm_device *dev = obj->dev; | |
4018 | drm_i915_private_t *dev_priv = dev->dev_private; | |
23010e43 | 4019 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
673a394b EA |
4020 | |
4021 | i915_verify_inactive(dev, __FILE__, __LINE__); | |
4022 | obj_priv->pin_count--; | |
4023 | BUG_ON(obj_priv->pin_count < 0); | |
4024 | BUG_ON(obj_priv->gtt_space == NULL); | |
4025 | ||
4026 | /* If the object is no longer pinned, and is | |
4027 | * neither active nor being flushed, then stick it on | |
4028 | * the inactive list | |
4029 | */ | |
4030 | if (obj_priv->pin_count == 0) { | |
4031 | if (!obj_priv->active && | |
21d509e3 | 4032 | (obj->write_domain & I915_GEM_GPU_DOMAINS) == 0) |
673a394b EA |
4033 | list_move_tail(&obj_priv->list, |
4034 | &dev_priv->mm.inactive_list); | |
4035 | atomic_dec(&dev->pin_count); | |
4036 | atomic_sub(obj->size, &dev->pin_memory); | |
4037 | } | |
4038 | i915_verify_inactive(dev, __FILE__, __LINE__); | |
4039 | } | |
4040 | ||
4041 | int | |
4042 | i915_gem_pin_ioctl(struct drm_device *dev, void *data, | |
4043 | struct drm_file *file_priv) | |
4044 | { | |
4045 | struct drm_i915_gem_pin *args = data; | |
4046 | struct drm_gem_object *obj; | |
4047 | struct drm_i915_gem_object *obj_priv; | |
4048 | int ret; | |
4049 | ||
4050 | mutex_lock(&dev->struct_mutex); | |
4051 | ||
4052 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); | |
4053 | if (obj == NULL) { | |
4054 | DRM_ERROR("Bad handle in i915_gem_pin_ioctl(): %d\n", | |
4055 | args->handle); | |
4056 | mutex_unlock(&dev->struct_mutex); | |
bf79cb91 | 4057 | return -ENOENT; |
673a394b | 4058 | } |
23010e43 | 4059 | obj_priv = to_intel_bo(obj); |
673a394b | 4060 | |
bb6baf76 CW |
4061 | if (obj_priv->madv != I915_MADV_WILLNEED) { |
4062 | DRM_ERROR("Attempting to pin a purgeable buffer\n"); | |
3ef94daa CW |
4063 | drm_gem_object_unreference(obj); |
4064 | mutex_unlock(&dev->struct_mutex); | |
4065 | return -EINVAL; | |
4066 | } | |
4067 | ||
79e53945 JB |
4068 | if (obj_priv->pin_filp != NULL && obj_priv->pin_filp != file_priv) { |
4069 | DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n", | |
4070 | args->handle); | |
96dec61d | 4071 | drm_gem_object_unreference(obj); |
673a394b | 4072 | mutex_unlock(&dev->struct_mutex); |
79e53945 JB |
4073 | return -EINVAL; |
4074 | } | |
4075 | ||
4076 | obj_priv->user_pin_count++; | |
4077 | obj_priv->pin_filp = file_priv; | |
4078 | if (obj_priv->user_pin_count == 1) { | |
4079 | ret = i915_gem_object_pin(obj, args->alignment); | |
4080 | if (ret != 0) { | |
4081 | drm_gem_object_unreference(obj); | |
4082 | mutex_unlock(&dev->struct_mutex); | |
4083 | return ret; | |
4084 | } | |
673a394b EA |
4085 | } |
4086 | ||
4087 | /* XXX - flush the CPU caches for pinned objects | |
4088 | * as the X server doesn't manage domains yet | |
4089 | */ | |
e47c68e9 | 4090 | i915_gem_object_flush_cpu_write_domain(obj); |
673a394b EA |
4091 | args->offset = obj_priv->gtt_offset; |
4092 | drm_gem_object_unreference(obj); | |
4093 | mutex_unlock(&dev->struct_mutex); | |
4094 | ||
4095 | return 0; | |
4096 | } | |
4097 | ||
4098 | int | |
4099 | i915_gem_unpin_ioctl(struct drm_device *dev, void *data, | |
4100 | struct drm_file *file_priv) | |
4101 | { | |
4102 | struct drm_i915_gem_pin *args = data; | |
4103 | struct drm_gem_object *obj; | |
79e53945 | 4104 | struct drm_i915_gem_object *obj_priv; |
673a394b EA |
4105 | |
4106 | mutex_lock(&dev->struct_mutex); | |
4107 | ||
4108 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); | |
4109 | if (obj == NULL) { | |
4110 | DRM_ERROR("Bad handle in i915_gem_unpin_ioctl(): %d\n", | |
4111 | args->handle); | |
4112 | mutex_unlock(&dev->struct_mutex); | |
bf79cb91 | 4113 | return -ENOENT; |
673a394b EA |
4114 | } |
4115 | ||
23010e43 | 4116 | obj_priv = to_intel_bo(obj); |
79e53945 JB |
4117 | if (obj_priv->pin_filp != file_priv) { |
4118 | DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n", | |
4119 | args->handle); | |
4120 | drm_gem_object_unreference(obj); | |
4121 | mutex_unlock(&dev->struct_mutex); | |
4122 | return -EINVAL; | |
4123 | } | |
4124 | obj_priv->user_pin_count--; | |
4125 | if (obj_priv->user_pin_count == 0) { | |
4126 | obj_priv->pin_filp = NULL; | |
4127 | i915_gem_object_unpin(obj); | |
4128 | } | |
673a394b EA |
4129 | |
4130 | drm_gem_object_unreference(obj); | |
4131 | mutex_unlock(&dev->struct_mutex); | |
4132 | return 0; | |
4133 | } | |
4134 | ||
4135 | int | |
4136 | i915_gem_busy_ioctl(struct drm_device *dev, void *data, | |
4137 | struct drm_file *file_priv) | |
4138 | { | |
4139 | struct drm_i915_gem_busy *args = data; | |
4140 | struct drm_gem_object *obj; | |
4141 | struct drm_i915_gem_object *obj_priv; | |
4142 | ||
673a394b EA |
4143 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); |
4144 | if (obj == NULL) { | |
4145 | DRM_ERROR("Bad handle in i915_gem_busy_ioctl(): %d\n", | |
4146 | args->handle); | |
bf79cb91 | 4147 | return -ENOENT; |
673a394b EA |
4148 | } |
4149 | ||
b1ce786c | 4150 | mutex_lock(&dev->struct_mutex); |
d1b851fc | 4151 | |
0be555b6 CW |
4152 | /* Count all active objects as busy, even if they are currently not used |
4153 | * by the gpu. Users of this interface expect objects to eventually | |
4154 | * become non-busy without any further actions, therefore emit any | |
4155 | * necessary flushes here. | |
c4de0a5d | 4156 | */ |
0be555b6 CW |
4157 | obj_priv = to_intel_bo(obj); |
4158 | args->busy = obj_priv->active; | |
4159 | if (args->busy) { | |
4160 | /* Unconditionally flush objects, even when the gpu still uses this | |
4161 | * object. Userspace calling this function indicates that it wants to | |
4162 | * use this buffer rather sooner than later, so issuing the required | |
4163 | * flush earlier is beneficial. | |
4164 | */ | |
4165 | if (obj->write_domain) { | |
4166 | i915_gem_flush(dev, 0, obj->write_domain); | |
8dc5d147 | 4167 | (void)i915_add_request(dev, file_priv, NULL, obj_priv->ring); |
0be555b6 CW |
4168 | } |
4169 | ||
4170 | /* Update the active list for the hardware's current position. | |
4171 | * Otherwise this only updates on a delayed timer or when irqs | |
4172 | * are actually unmasked, and our working set ends up being | |
4173 | * larger than required. | |
4174 | */ | |
4175 | i915_gem_retire_requests_ring(dev, obj_priv->ring); | |
4176 | ||
4177 | args->busy = obj_priv->active; | |
4178 | } | |
673a394b EA |
4179 | |
4180 | drm_gem_object_unreference(obj); | |
4181 | mutex_unlock(&dev->struct_mutex); | |
4182 | return 0; | |
4183 | } | |
4184 | ||
4185 | int | |
4186 | i915_gem_throttle_ioctl(struct drm_device *dev, void *data, | |
4187 | struct drm_file *file_priv) | |
4188 | { | |
4189 | return i915_gem_ring_throttle(dev, file_priv); | |
4190 | } | |
4191 | ||
3ef94daa CW |
4192 | int |
4193 | i915_gem_madvise_ioctl(struct drm_device *dev, void *data, | |
4194 | struct drm_file *file_priv) | |
4195 | { | |
4196 | struct drm_i915_gem_madvise *args = data; | |
4197 | struct drm_gem_object *obj; | |
4198 | struct drm_i915_gem_object *obj_priv; | |
4199 | ||
4200 | switch (args->madv) { | |
4201 | case I915_MADV_DONTNEED: | |
4202 | case I915_MADV_WILLNEED: | |
4203 | break; | |
4204 | default: | |
4205 | return -EINVAL; | |
4206 | } | |
4207 | ||
4208 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); | |
4209 | if (obj == NULL) { | |
4210 | DRM_ERROR("Bad handle in i915_gem_madvise_ioctl(): %d\n", | |
4211 | args->handle); | |
bf79cb91 | 4212 | return -ENOENT; |
3ef94daa CW |
4213 | } |
4214 | ||
4215 | mutex_lock(&dev->struct_mutex); | |
23010e43 | 4216 | obj_priv = to_intel_bo(obj); |
3ef94daa CW |
4217 | |
4218 | if (obj_priv->pin_count) { | |
4219 | drm_gem_object_unreference(obj); | |
4220 | mutex_unlock(&dev->struct_mutex); | |
4221 | ||
4222 | DRM_ERROR("Attempted i915_gem_madvise_ioctl() on a pinned object\n"); | |
4223 | return -EINVAL; | |
4224 | } | |
4225 | ||
bb6baf76 CW |
4226 | if (obj_priv->madv != __I915_MADV_PURGED) |
4227 | obj_priv->madv = args->madv; | |
3ef94daa | 4228 | |
2d7ef395 CW |
4229 | /* if the object is no longer bound, discard its backing storage */ |
4230 | if (i915_gem_object_is_purgeable(obj_priv) && | |
4231 | obj_priv->gtt_space == NULL) | |
4232 | i915_gem_object_truncate(obj); | |
4233 | ||
bb6baf76 CW |
4234 | args->retained = obj_priv->madv != __I915_MADV_PURGED; |
4235 | ||
3ef94daa CW |
4236 | drm_gem_object_unreference(obj); |
4237 | mutex_unlock(&dev->struct_mutex); | |
4238 | ||
4239 | return 0; | |
4240 | } | |
4241 | ||
ac52bc56 DV |
4242 | struct drm_gem_object * i915_gem_alloc_object(struct drm_device *dev, |
4243 | size_t size) | |
4244 | { | |
c397b908 | 4245 | struct drm_i915_gem_object *obj; |
ac52bc56 | 4246 | |
c397b908 DV |
4247 | obj = kzalloc(sizeof(*obj), GFP_KERNEL); |
4248 | if (obj == NULL) | |
4249 | return NULL; | |
673a394b | 4250 | |
c397b908 DV |
4251 | if (drm_gem_object_init(dev, &obj->base, size) != 0) { |
4252 | kfree(obj); | |
4253 | return NULL; | |
4254 | } | |
673a394b | 4255 | |
c397b908 DV |
4256 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; |
4257 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; | |
673a394b | 4258 | |
c397b908 | 4259 | obj->agp_type = AGP_USER_MEMORY; |
62b8b215 | 4260 | obj->base.driver_private = NULL; |
c397b908 DV |
4261 | obj->fence_reg = I915_FENCE_REG_NONE; |
4262 | INIT_LIST_HEAD(&obj->list); | |
4263 | INIT_LIST_HEAD(&obj->gpu_write_list); | |
c397b908 | 4264 | obj->madv = I915_MADV_WILLNEED; |
de151cf6 | 4265 | |
c397b908 DV |
4266 | trace_i915_gem_object_create(&obj->base); |
4267 | ||
4268 | return &obj->base; | |
4269 | } | |
4270 | ||
4271 | int i915_gem_init_object(struct drm_gem_object *obj) | |
4272 | { | |
4273 | BUG(); | |
de151cf6 | 4274 | |
673a394b EA |
4275 | return 0; |
4276 | } | |
4277 | ||
be72615b | 4278 | static void i915_gem_free_object_tail(struct drm_gem_object *obj) |
673a394b | 4279 | { |
de151cf6 | 4280 | struct drm_device *dev = obj->dev; |
be72615b | 4281 | drm_i915_private_t *dev_priv = dev->dev_private; |
23010e43 | 4282 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
be72615b | 4283 | int ret; |
673a394b | 4284 | |
be72615b CW |
4285 | ret = i915_gem_object_unbind(obj); |
4286 | if (ret == -ERESTARTSYS) { | |
4287 | list_move(&obj_priv->list, | |
4288 | &dev_priv->mm.deferred_free_list); | |
4289 | return; | |
4290 | } | |
673a394b | 4291 | |
7e616158 CW |
4292 | if (obj_priv->mmap_offset) |
4293 | i915_gem_free_mmap_offset(obj); | |
de151cf6 | 4294 | |
c397b908 DV |
4295 | drm_gem_object_release(obj); |
4296 | ||
9a298b2a | 4297 | kfree(obj_priv->page_cpu_valid); |
280b713b | 4298 | kfree(obj_priv->bit_17); |
c397b908 | 4299 | kfree(obj_priv); |
673a394b EA |
4300 | } |
4301 | ||
be72615b CW |
4302 | void i915_gem_free_object(struct drm_gem_object *obj) |
4303 | { | |
4304 | struct drm_device *dev = obj->dev; | |
4305 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); | |
4306 | ||
4307 | trace_i915_gem_object_destroy(obj); | |
4308 | ||
4309 | while (obj_priv->pin_count > 0) | |
4310 | i915_gem_object_unpin(obj); | |
4311 | ||
4312 | if (obj_priv->phys_obj) | |
4313 | i915_gem_detach_phys_object(dev, obj); | |
4314 | ||
4315 | i915_gem_free_object_tail(obj); | |
4316 | } | |
4317 | ||
29105ccc CW |
4318 | int |
4319 | i915_gem_idle(struct drm_device *dev) | |
4320 | { | |
4321 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4322 | int ret; | |
28dfe52a | 4323 | |
29105ccc | 4324 | mutex_lock(&dev->struct_mutex); |
1c5d22f7 | 4325 | |
8187a2b7 | 4326 | if (dev_priv->mm.suspended || |
d1b851fc ZN |
4327 | (dev_priv->render_ring.gem_object == NULL) || |
4328 | (HAS_BSD(dev) && | |
4329 | dev_priv->bsd_ring.gem_object == NULL)) { | |
29105ccc CW |
4330 | mutex_unlock(&dev->struct_mutex); |
4331 | return 0; | |
28dfe52a EA |
4332 | } |
4333 | ||
29105ccc | 4334 | ret = i915_gpu_idle(dev); |
6dbe2772 KP |
4335 | if (ret) { |
4336 | mutex_unlock(&dev->struct_mutex); | |
673a394b | 4337 | return ret; |
6dbe2772 | 4338 | } |
673a394b | 4339 | |
29105ccc CW |
4340 | /* Under UMS, be paranoid and evict. */ |
4341 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) { | |
b47eb4a2 | 4342 | ret = i915_gem_evict_inactive(dev); |
29105ccc CW |
4343 | if (ret) { |
4344 | mutex_unlock(&dev->struct_mutex); | |
4345 | return ret; | |
4346 | } | |
4347 | } | |
4348 | ||
4349 | /* Hack! Don't let anybody do execbuf while we don't control the chip. | |
4350 | * We need to replace this with a semaphore, or something. | |
4351 | * And not confound mm.suspended! | |
4352 | */ | |
4353 | dev_priv->mm.suspended = 1; | |
bc0c7f14 | 4354 | del_timer_sync(&dev_priv->hangcheck_timer); |
29105ccc CW |
4355 | |
4356 | i915_kernel_lost_context(dev); | |
6dbe2772 | 4357 | i915_gem_cleanup_ringbuffer(dev); |
29105ccc | 4358 | |
6dbe2772 KP |
4359 | mutex_unlock(&dev->struct_mutex); |
4360 | ||
29105ccc CW |
4361 | /* Cancel the retire work handler, which should be idle now. */ |
4362 | cancel_delayed_work_sync(&dev_priv->mm.retire_work); | |
4363 | ||
673a394b EA |
4364 | return 0; |
4365 | } | |
4366 | ||
e552eb70 JB |
4367 | /* |
4368 | * 965+ support PIPE_CONTROL commands, which provide finer grained control | |
4369 | * over cache flushing. | |
4370 | */ | |
8187a2b7 | 4371 | static int |
e552eb70 JB |
4372 | i915_gem_init_pipe_control(struct drm_device *dev) |
4373 | { | |
4374 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4375 | struct drm_gem_object *obj; | |
4376 | struct drm_i915_gem_object *obj_priv; | |
4377 | int ret; | |
4378 | ||
34dc4d44 | 4379 | obj = i915_gem_alloc_object(dev, 4096); |
e552eb70 JB |
4380 | if (obj == NULL) { |
4381 | DRM_ERROR("Failed to allocate seqno page\n"); | |
4382 | ret = -ENOMEM; | |
4383 | goto err; | |
4384 | } | |
4385 | obj_priv = to_intel_bo(obj); | |
4386 | obj_priv->agp_type = AGP_USER_CACHED_MEMORY; | |
4387 | ||
4388 | ret = i915_gem_object_pin(obj, 4096); | |
4389 | if (ret) | |
4390 | goto err_unref; | |
4391 | ||
4392 | dev_priv->seqno_gfx_addr = obj_priv->gtt_offset; | |
4393 | dev_priv->seqno_page = kmap(obj_priv->pages[0]); | |
4394 | if (dev_priv->seqno_page == NULL) | |
4395 | goto err_unpin; | |
4396 | ||
4397 | dev_priv->seqno_obj = obj; | |
4398 | memset(dev_priv->seqno_page, 0, PAGE_SIZE); | |
4399 | ||
4400 | return 0; | |
4401 | ||
4402 | err_unpin: | |
4403 | i915_gem_object_unpin(obj); | |
4404 | err_unref: | |
4405 | drm_gem_object_unreference(obj); | |
4406 | err: | |
4407 | return ret; | |
4408 | } | |
4409 | ||
8187a2b7 ZN |
4410 | |
4411 | static void | |
e552eb70 JB |
4412 | i915_gem_cleanup_pipe_control(struct drm_device *dev) |
4413 | { | |
4414 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4415 | struct drm_gem_object *obj; | |
4416 | struct drm_i915_gem_object *obj_priv; | |
4417 | ||
4418 | obj = dev_priv->seqno_obj; | |
4419 | obj_priv = to_intel_bo(obj); | |
4420 | kunmap(obj_priv->pages[0]); | |
4421 | i915_gem_object_unpin(obj); | |
4422 | drm_gem_object_unreference(obj); | |
4423 | dev_priv->seqno_obj = NULL; | |
4424 | ||
4425 | dev_priv->seqno_page = NULL; | |
673a394b EA |
4426 | } |
4427 | ||
8187a2b7 ZN |
4428 | int |
4429 | i915_gem_init_ringbuffer(struct drm_device *dev) | |
4430 | { | |
4431 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4432 | int ret; | |
68f95ba9 | 4433 | |
8187a2b7 | 4434 | dev_priv->render_ring = render_ring; |
68f95ba9 | 4435 | |
8187a2b7 ZN |
4436 | if (!I915_NEED_GFX_HWS(dev)) { |
4437 | dev_priv->render_ring.status_page.page_addr | |
4438 | = dev_priv->status_page_dmah->vaddr; | |
4439 | memset(dev_priv->render_ring.status_page.page_addr, | |
4440 | 0, PAGE_SIZE); | |
4441 | } | |
68f95ba9 | 4442 | |
8187a2b7 ZN |
4443 | if (HAS_PIPE_CONTROL(dev)) { |
4444 | ret = i915_gem_init_pipe_control(dev); | |
4445 | if (ret) | |
4446 | return ret; | |
4447 | } | |
68f95ba9 | 4448 | |
8187a2b7 | 4449 | ret = intel_init_ring_buffer(dev, &dev_priv->render_ring); |
68f95ba9 CW |
4450 | if (ret) |
4451 | goto cleanup_pipe_control; | |
4452 | ||
4453 | if (HAS_BSD(dev)) { | |
d1b851fc ZN |
4454 | dev_priv->bsd_ring = bsd_ring; |
4455 | ret = intel_init_ring_buffer(dev, &dev_priv->bsd_ring); | |
68f95ba9 CW |
4456 | if (ret) |
4457 | goto cleanup_render_ring; | |
d1b851fc | 4458 | } |
68f95ba9 | 4459 | |
6f392d54 CW |
4460 | dev_priv->next_seqno = 1; |
4461 | ||
68f95ba9 CW |
4462 | return 0; |
4463 | ||
4464 | cleanup_render_ring: | |
4465 | intel_cleanup_ring_buffer(dev, &dev_priv->render_ring); | |
4466 | cleanup_pipe_control: | |
4467 | if (HAS_PIPE_CONTROL(dev)) | |
4468 | i915_gem_cleanup_pipe_control(dev); | |
8187a2b7 ZN |
4469 | return ret; |
4470 | } | |
4471 | ||
4472 | void | |
4473 | i915_gem_cleanup_ringbuffer(struct drm_device *dev) | |
4474 | { | |
4475 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4476 | ||
4477 | intel_cleanup_ring_buffer(dev, &dev_priv->render_ring); | |
d1b851fc ZN |
4478 | if (HAS_BSD(dev)) |
4479 | intel_cleanup_ring_buffer(dev, &dev_priv->bsd_ring); | |
8187a2b7 ZN |
4480 | if (HAS_PIPE_CONTROL(dev)) |
4481 | i915_gem_cleanup_pipe_control(dev); | |
4482 | } | |
4483 | ||
673a394b EA |
4484 | int |
4485 | i915_gem_entervt_ioctl(struct drm_device *dev, void *data, | |
4486 | struct drm_file *file_priv) | |
4487 | { | |
4488 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4489 | int ret; | |
4490 | ||
79e53945 JB |
4491 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
4492 | return 0; | |
4493 | ||
ba1234d1 | 4494 | if (atomic_read(&dev_priv->mm.wedged)) { |
673a394b | 4495 | DRM_ERROR("Reenabling wedged hardware, good luck\n"); |
ba1234d1 | 4496 | atomic_set(&dev_priv->mm.wedged, 0); |
673a394b EA |
4497 | } |
4498 | ||
673a394b | 4499 | mutex_lock(&dev->struct_mutex); |
9bb2d6f9 EA |
4500 | dev_priv->mm.suspended = 0; |
4501 | ||
4502 | ret = i915_gem_init_ringbuffer(dev); | |
d816f6ac WF |
4503 | if (ret != 0) { |
4504 | mutex_unlock(&dev->struct_mutex); | |
9bb2d6f9 | 4505 | return ret; |
d816f6ac | 4506 | } |
9bb2d6f9 | 4507 | |
852835f3 | 4508 | BUG_ON(!list_empty(&dev_priv->render_ring.active_list)); |
d1b851fc | 4509 | BUG_ON(HAS_BSD(dev) && !list_empty(&dev_priv->bsd_ring.active_list)); |
673a394b EA |
4510 | BUG_ON(!list_empty(&dev_priv->mm.flushing_list)); |
4511 | BUG_ON(!list_empty(&dev_priv->mm.inactive_list)); | |
852835f3 | 4512 | BUG_ON(!list_empty(&dev_priv->render_ring.request_list)); |
d1b851fc | 4513 | BUG_ON(HAS_BSD(dev) && !list_empty(&dev_priv->bsd_ring.request_list)); |
673a394b | 4514 | mutex_unlock(&dev->struct_mutex); |
dbb19d30 | 4515 | |
5f35308b CW |
4516 | ret = drm_irq_install(dev); |
4517 | if (ret) | |
4518 | goto cleanup_ringbuffer; | |
dbb19d30 | 4519 | |
673a394b | 4520 | return 0; |
5f35308b CW |
4521 | |
4522 | cleanup_ringbuffer: | |
4523 | mutex_lock(&dev->struct_mutex); | |
4524 | i915_gem_cleanup_ringbuffer(dev); | |
4525 | dev_priv->mm.suspended = 1; | |
4526 | mutex_unlock(&dev->struct_mutex); | |
4527 | ||
4528 | return ret; | |
673a394b EA |
4529 | } |
4530 | ||
4531 | int | |
4532 | i915_gem_leavevt_ioctl(struct drm_device *dev, void *data, | |
4533 | struct drm_file *file_priv) | |
4534 | { | |
79e53945 JB |
4535 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
4536 | return 0; | |
4537 | ||
dbb19d30 | 4538 | drm_irq_uninstall(dev); |
e6890f6f | 4539 | return i915_gem_idle(dev); |
673a394b EA |
4540 | } |
4541 | ||
4542 | void | |
4543 | i915_gem_lastclose(struct drm_device *dev) | |
4544 | { | |
4545 | int ret; | |
673a394b | 4546 | |
e806b495 EA |
4547 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
4548 | return; | |
4549 | ||
6dbe2772 KP |
4550 | ret = i915_gem_idle(dev); |
4551 | if (ret) | |
4552 | DRM_ERROR("failed to idle hardware: %d\n", ret); | |
673a394b EA |
4553 | } |
4554 | ||
4555 | void | |
4556 | i915_gem_load(struct drm_device *dev) | |
4557 | { | |
b5aa8a0f | 4558 | int i; |
673a394b EA |
4559 | drm_i915_private_t *dev_priv = dev->dev_private; |
4560 | ||
673a394b | 4561 | INIT_LIST_HEAD(&dev_priv->mm.flushing_list); |
99fcb766 | 4562 | INIT_LIST_HEAD(&dev_priv->mm.gpu_write_list); |
673a394b | 4563 | INIT_LIST_HEAD(&dev_priv->mm.inactive_list); |
a09ba7fa | 4564 | INIT_LIST_HEAD(&dev_priv->mm.fence_list); |
be72615b | 4565 | INIT_LIST_HEAD(&dev_priv->mm.deferred_free_list); |
852835f3 ZN |
4566 | INIT_LIST_HEAD(&dev_priv->render_ring.active_list); |
4567 | INIT_LIST_HEAD(&dev_priv->render_ring.request_list); | |
d1b851fc ZN |
4568 | if (HAS_BSD(dev)) { |
4569 | INIT_LIST_HEAD(&dev_priv->bsd_ring.active_list); | |
4570 | INIT_LIST_HEAD(&dev_priv->bsd_ring.request_list); | |
4571 | } | |
007cc8ac DV |
4572 | for (i = 0; i < 16; i++) |
4573 | INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list); | |
673a394b EA |
4574 | INIT_DELAYED_WORK(&dev_priv->mm.retire_work, |
4575 | i915_gem_retire_work_handler); | |
31169714 CW |
4576 | spin_lock(&shrink_list_lock); |
4577 | list_add(&dev_priv->mm.shrink_list, &shrink_list); | |
4578 | spin_unlock(&shrink_list_lock); | |
4579 | ||
94400120 DA |
4580 | /* On GEN3 we really need to make sure the ARB C3 LP bit is set */ |
4581 | if (IS_GEN3(dev)) { | |
4582 | u32 tmp = I915_READ(MI_ARB_STATE); | |
4583 | if (!(tmp & MI_ARB_C3_LP_WRITE_ENABLE)) { | |
4584 | /* arb state is a masked write, so set bit + bit in mask */ | |
4585 | tmp = MI_ARB_C3_LP_WRITE_ENABLE | (MI_ARB_C3_LP_WRITE_ENABLE << MI_ARB_MASK_SHIFT); | |
4586 | I915_WRITE(MI_ARB_STATE, tmp); | |
4587 | } | |
4588 | } | |
4589 | ||
de151cf6 | 4590 | /* Old X drivers will take 0-2 for front, back, depth buffers */ |
b397c836 EA |
4591 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) |
4592 | dev_priv->fence_reg_start = 3; | |
de151cf6 | 4593 | |
0f973f27 | 4594 | if (IS_I965G(dev) || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) |
de151cf6 JB |
4595 | dev_priv->num_fence_regs = 16; |
4596 | else | |
4597 | dev_priv->num_fence_regs = 8; | |
4598 | ||
b5aa8a0f GH |
4599 | /* Initialize fence registers to zero */ |
4600 | if (IS_I965G(dev)) { | |
4601 | for (i = 0; i < 16; i++) | |
4602 | I915_WRITE64(FENCE_REG_965_0 + (i * 8), 0); | |
4603 | } else { | |
4604 | for (i = 0; i < 8; i++) | |
4605 | I915_WRITE(FENCE_REG_830_0 + (i * 4), 0); | |
4606 | if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) | |
4607 | for (i = 0; i < 8; i++) | |
4608 | I915_WRITE(FENCE_REG_945_8 + (i * 4), 0); | |
4609 | } | |
673a394b | 4610 | i915_gem_detect_bit_6_swizzle(dev); |
6b95a207 | 4611 | init_waitqueue_head(&dev_priv->pending_flip_queue); |
673a394b | 4612 | } |
71acb5eb DA |
4613 | |
4614 | /* | |
4615 | * Create a physically contiguous memory object for this object | |
4616 | * e.g. for cursor + overlay regs | |
4617 | */ | |
995b6762 CW |
4618 | static int i915_gem_init_phys_object(struct drm_device *dev, |
4619 | int id, int size, int align) | |
71acb5eb DA |
4620 | { |
4621 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4622 | struct drm_i915_gem_phys_object *phys_obj; | |
4623 | int ret; | |
4624 | ||
4625 | if (dev_priv->mm.phys_objs[id - 1] || !size) | |
4626 | return 0; | |
4627 | ||
9a298b2a | 4628 | phys_obj = kzalloc(sizeof(struct drm_i915_gem_phys_object), GFP_KERNEL); |
71acb5eb DA |
4629 | if (!phys_obj) |
4630 | return -ENOMEM; | |
4631 | ||
4632 | phys_obj->id = id; | |
4633 | ||
6eeefaf3 | 4634 | phys_obj->handle = drm_pci_alloc(dev, size, align); |
71acb5eb DA |
4635 | if (!phys_obj->handle) { |
4636 | ret = -ENOMEM; | |
4637 | goto kfree_obj; | |
4638 | } | |
4639 | #ifdef CONFIG_X86 | |
4640 | set_memory_wc((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE); | |
4641 | #endif | |
4642 | ||
4643 | dev_priv->mm.phys_objs[id - 1] = phys_obj; | |
4644 | ||
4645 | return 0; | |
4646 | kfree_obj: | |
9a298b2a | 4647 | kfree(phys_obj); |
71acb5eb DA |
4648 | return ret; |
4649 | } | |
4650 | ||
995b6762 | 4651 | static void i915_gem_free_phys_object(struct drm_device *dev, int id) |
71acb5eb DA |
4652 | { |
4653 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4654 | struct drm_i915_gem_phys_object *phys_obj; | |
4655 | ||
4656 | if (!dev_priv->mm.phys_objs[id - 1]) | |
4657 | return; | |
4658 | ||
4659 | phys_obj = dev_priv->mm.phys_objs[id - 1]; | |
4660 | if (phys_obj->cur_obj) { | |
4661 | i915_gem_detach_phys_object(dev, phys_obj->cur_obj); | |
4662 | } | |
4663 | ||
4664 | #ifdef CONFIG_X86 | |
4665 | set_memory_wb((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE); | |
4666 | #endif | |
4667 | drm_pci_free(dev, phys_obj->handle); | |
4668 | kfree(phys_obj); | |
4669 | dev_priv->mm.phys_objs[id - 1] = NULL; | |
4670 | } | |
4671 | ||
4672 | void i915_gem_free_all_phys_object(struct drm_device *dev) | |
4673 | { | |
4674 | int i; | |
4675 | ||
260883c8 | 4676 | for (i = I915_GEM_PHYS_CURSOR_0; i <= I915_MAX_PHYS_OBJECT; i++) |
71acb5eb DA |
4677 | i915_gem_free_phys_object(dev, i); |
4678 | } | |
4679 | ||
4680 | void i915_gem_detach_phys_object(struct drm_device *dev, | |
4681 | struct drm_gem_object *obj) | |
4682 | { | |
4683 | struct drm_i915_gem_object *obj_priv; | |
4684 | int i; | |
4685 | int ret; | |
4686 | int page_count; | |
4687 | ||
23010e43 | 4688 | obj_priv = to_intel_bo(obj); |
71acb5eb DA |
4689 | if (!obj_priv->phys_obj) |
4690 | return; | |
4691 | ||
4bdadb97 | 4692 | ret = i915_gem_object_get_pages(obj, 0); |
71acb5eb DA |
4693 | if (ret) |
4694 | goto out; | |
4695 | ||
4696 | page_count = obj->size / PAGE_SIZE; | |
4697 | ||
4698 | for (i = 0; i < page_count; i++) { | |
856fa198 | 4699 | char *dst = kmap_atomic(obj_priv->pages[i], KM_USER0); |
71acb5eb DA |
4700 | char *src = obj_priv->phys_obj->handle->vaddr + (i * PAGE_SIZE); |
4701 | ||
4702 | memcpy(dst, src, PAGE_SIZE); | |
4703 | kunmap_atomic(dst, KM_USER0); | |
4704 | } | |
856fa198 | 4705 | drm_clflush_pages(obj_priv->pages, page_count); |
71acb5eb | 4706 | drm_agp_chipset_flush(dev); |
d78b47b9 CW |
4707 | |
4708 | i915_gem_object_put_pages(obj); | |
71acb5eb DA |
4709 | out: |
4710 | obj_priv->phys_obj->cur_obj = NULL; | |
4711 | obj_priv->phys_obj = NULL; | |
4712 | } | |
4713 | ||
4714 | int | |
4715 | i915_gem_attach_phys_object(struct drm_device *dev, | |
6eeefaf3 CW |
4716 | struct drm_gem_object *obj, |
4717 | int id, | |
4718 | int align) | |
71acb5eb DA |
4719 | { |
4720 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4721 | struct drm_i915_gem_object *obj_priv; | |
4722 | int ret = 0; | |
4723 | int page_count; | |
4724 | int i; | |
4725 | ||
4726 | if (id > I915_MAX_PHYS_OBJECT) | |
4727 | return -EINVAL; | |
4728 | ||
23010e43 | 4729 | obj_priv = to_intel_bo(obj); |
71acb5eb DA |
4730 | |
4731 | if (obj_priv->phys_obj) { | |
4732 | if (obj_priv->phys_obj->id == id) | |
4733 | return 0; | |
4734 | i915_gem_detach_phys_object(dev, obj); | |
4735 | } | |
4736 | ||
71acb5eb DA |
4737 | /* create a new object */ |
4738 | if (!dev_priv->mm.phys_objs[id - 1]) { | |
4739 | ret = i915_gem_init_phys_object(dev, id, | |
6eeefaf3 | 4740 | obj->size, align); |
71acb5eb | 4741 | if (ret) { |
aeb565df | 4742 | DRM_ERROR("failed to init phys object %d size: %zu\n", id, obj->size); |
71acb5eb DA |
4743 | goto out; |
4744 | } | |
4745 | } | |
4746 | ||
4747 | /* bind to the object */ | |
4748 | obj_priv->phys_obj = dev_priv->mm.phys_objs[id - 1]; | |
4749 | obj_priv->phys_obj->cur_obj = obj; | |
4750 | ||
4bdadb97 | 4751 | ret = i915_gem_object_get_pages(obj, 0); |
71acb5eb DA |
4752 | if (ret) { |
4753 | DRM_ERROR("failed to get page list\n"); | |
4754 | goto out; | |
4755 | } | |
4756 | ||
4757 | page_count = obj->size / PAGE_SIZE; | |
4758 | ||
4759 | for (i = 0; i < page_count; i++) { | |
856fa198 | 4760 | char *src = kmap_atomic(obj_priv->pages[i], KM_USER0); |
71acb5eb DA |
4761 | char *dst = obj_priv->phys_obj->handle->vaddr + (i * PAGE_SIZE); |
4762 | ||
4763 | memcpy(dst, src, PAGE_SIZE); | |
4764 | kunmap_atomic(src, KM_USER0); | |
4765 | } | |
4766 | ||
d78b47b9 CW |
4767 | i915_gem_object_put_pages(obj); |
4768 | ||
71acb5eb DA |
4769 | return 0; |
4770 | out: | |
4771 | return ret; | |
4772 | } | |
4773 | ||
4774 | static int | |
4775 | i915_gem_phys_pwrite(struct drm_device *dev, struct drm_gem_object *obj, | |
4776 | struct drm_i915_gem_pwrite *args, | |
4777 | struct drm_file *file_priv) | |
4778 | { | |
23010e43 | 4779 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
71acb5eb DA |
4780 | void *obj_addr; |
4781 | int ret; | |
4782 | char __user *user_data; | |
4783 | ||
4784 | user_data = (char __user *) (uintptr_t) args->data_ptr; | |
4785 | obj_addr = obj_priv->phys_obj->handle->vaddr + args->offset; | |
4786 | ||
44d98a61 | 4787 | DRM_DEBUG_DRIVER("obj_addr %p, %lld\n", obj_addr, args->size); |
71acb5eb DA |
4788 | ret = copy_from_user(obj_addr, user_data, args->size); |
4789 | if (ret) | |
4790 | return -EFAULT; | |
4791 | ||
4792 | drm_agp_chipset_flush(dev); | |
4793 | return 0; | |
4794 | } | |
b962442e EA |
4795 | |
4796 | void i915_gem_release(struct drm_device * dev, struct drm_file *file_priv) | |
4797 | { | |
4798 | struct drm_i915_file_private *i915_file_priv = file_priv->driver_priv; | |
4799 | ||
4800 | /* Clean up our request list when the client is going away, so that | |
4801 | * later retire_requests won't dereference our soon-to-be-gone | |
4802 | * file_priv. | |
4803 | */ | |
4804 | mutex_lock(&dev->struct_mutex); | |
4805 | while (!list_empty(&i915_file_priv->mm.request_list)) | |
4806 | list_del_init(i915_file_priv->mm.request_list.next); | |
4807 | mutex_unlock(&dev->struct_mutex); | |
4808 | } | |
31169714 | 4809 | |
1637ef41 CW |
4810 | static int |
4811 | i915_gpu_is_active(struct drm_device *dev) | |
4812 | { | |
4813 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4814 | int lists_empty; | |
4815 | ||
1637ef41 | 4816 | lists_empty = list_empty(&dev_priv->mm.flushing_list) && |
852835f3 | 4817 | list_empty(&dev_priv->render_ring.active_list); |
d1b851fc ZN |
4818 | if (HAS_BSD(dev)) |
4819 | lists_empty &= list_empty(&dev_priv->bsd_ring.active_list); | |
1637ef41 CW |
4820 | |
4821 | return !lists_empty; | |
4822 | } | |
4823 | ||
31169714 | 4824 | static int |
7f8275d0 | 4825 | i915_gem_shrink(struct shrinker *shrink, int nr_to_scan, gfp_t gfp_mask) |
31169714 CW |
4826 | { |
4827 | drm_i915_private_t *dev_priv, *next_dev; | |
4828 | struct drm_i915_gem_object *obj_priv, *next_obj; | |
4829 | int cnt = 0; | |
4830 | int would_deadlock = 1; | |
4831 | ||
4832 | /* "fast-path" to count number of available objects */ | |
4833 | if (nr_to_scan == 0) { | |
4834 | spin_lock(&shrink_list_lock); | |
4835 | list_for_each_entry(dev_priv, &shrink_list, mm.shrink_list) { | |
4836 | struct drm_device *dev = dev_priv->dev; | |
4837 | ||
4838 | if (mutex_trylock(&dev->struct_mutex)) { | |
4839 | list_for_each_entry(obj_priv, | |
4840 | &dev_priv->mm.inactive_list, | |
4841 | list) | |
4842 | cnt++; | |
4843 | mutex_unlock(&dev->struct_mutex); | |
4844 | } | |
4845 | } | |
4846 | spin_unlock(&shrink_list_lock); | |
4847 | ||
4848 | return (cnt / 100) * sysctl_vfs_cache_pressure; | |
4849 | } | |
4850 | ||
4851 | spin_lock(&shrink_list_lock); | |
4852 | ||
1637ef41 | 4853 | rescan: |
31169714 CW |
4854 | /* first scan for clean buffers */ |
4855 | list_for_each_entry_safe(dev_priv, next_dev, | |
4856 | &shrink_list, mm.shrink_list) { | |
4857 | struct drm_device *dev = dev_priv->dev; | |
4858 | ||
4859 | if (! mutex_trylock(&dev->struct_mutex)) | |
4860 | continue; | |
4861 | ||
4862 | spin_unlock(&shrink_list_lock); | |
b09a1fec | 4863 | i915_gem_retire_requests(dev); |
31169714 CW |
4864 | |
4865 | list_for_each_entry_safe(obj_priv, next_obj, | |
4866 | &dev_priv->mm.inactive_list, | |
4867 | list) { | |
4868 | if (i915_gem_object_is_purgeable(obj_priv)) { | |
a8089e84 | 4869 | i915_gem_object_unbind(&obj_priv->base); |
31169714 CW |
4870 | if (--nr_to_scan <= 0) |
4871 | break; | |
4872 | } | |
4873 | } | |
4874 | ||
4875 | spin_lock(&shrink_list_lock); | |
4876 | mutex_unlock(&dev->struct_mutex); | |
4877 | ||
963b4836 CW |
4878 | would_deadlock = 0; |
4879 | ||
31169714 CW |
4880 | if (nr_to_scan <= 0) |
4881 | break; | |
4882 | } | |
4883 | ||
4884 | /* second pass, evict/count anything still on the inactive list */ | |
4885 | list_for_each_entry_safe(dev_priv, next_dev, | |
4886 | &shrink_list, mm.shrink_list) { | |
4887 | struct drm_device *dev = dev_priv->dev; | |
4888 | ||
4889 | if (! mutex_trylock(&dev->struct_mutex)) | |
4890 | continue; | |
4891 | ||
4892 | spin_unlock(&shrink_list_lock); | |
4893 | ||
4894 | list_for_each_entry_safe(obj_priv, next_obj, | |
4895 | &dev_priv->mm.inactive_list, | |
4896 | list) { | |
4897 | if (nr_to_scan > 0) { | |
a8089e84 | 4898 | i915_gem_object_unbind(&obj_priv->base); |
31169714 CW |
4899 | nr_to_scan--; |
4900 | } else | |
4901 | cnt++; | |
4902 | } | |
4903 | ||
4904 | spin_lock(&shrink_list_lock); | |
4905 | mutex_unlock(&dev->struct_mutex); | |
4906 | ||
4907 | would_deadlock = 0; | |
4908 | } | |
4909 | ||
1637ef41 CW |
4910 | if (nr_to_scan) { |
4911 | int active = 0; | |
4912 | ||
4913 | /* | |
4914 | * We are desperate for pages, so as a last resort, wait | |
4915 | * for the GPU to finish and discard whatever we can. | |
4916 | * This has a dramatic impact to reduce the number of | |
4917 | * OOM-killer events whilst running the GPU aggressively. | |
4918 | */ | |
4919 | list_for_each_entry(dev_priv, &shrink_list, mm.shrink_list) { | |
4920 | struct drm_device *dev = dev_priv->dev; | |
4921 | ||
4922 | if (!mutex_trylock(&dev->struct_mutex)) | |
4923 | continue; | |
4924 | ||
4925 | spin_unlock(&shrink_list_lock); | |
4926 | ||
4927 | if (i915_gpu_is_active(dev)) { | |
4928 | i915_gpu_idle(dev); | |
4929 | active++; | |
4930 | } | |
4931 | ||
4932 | spin_lock(&shrink_list_lock); | |
4933 | mutex_unlock(&dev->struct_mutex); | |
4934 | } | |
4935 | ||
4936 | if (active) | |
4937 | goto rescan; | |
4938 | } | |
4939 | ||
31169714 CW |
4940 | spin_unlock(&shrink_list_lock); |
4941 | ||
4942 | if (would_deadlock) | |
4943 | return -1; | |
4944 | else if (cnt > 0) | |
4945 | return (cnt / 100) * sysctl_vfs_cache_pressure; | |
4946 | else | |
4947 | return 0; | |
4948 | } | |
4949 | ||
4950 | static struct shrinker shrinker = { | |
4951 | .shrink = i915_gem_shrink, | |
4952 | .seeks = DEFAULT_SEEKS, | |
4953 | }; | |
4954 | ||
4955 | __init void | |
4956 | i915_gem_shrinker_init(void) | |
4957 | { | |
4958 | register_shrinker(&shrinker); | |
4959 | } | |
4960 | ||
4961 | __exit void | |
4962 | i915_gem_shrinker_exit(void) | |
4963 | { | |
4964 | unregister_shrinker(&shrinker); | |
4965 | } |