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drm: Move the GTT accounting to i915
[mirror_ubuntu-focal-kernel.git] / drivers / gpu / drm / i915 / i915_gem.c
CommitLineData
673a394b
EA		 1/*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 *
26 */
27
28#include "drmP.h"
29#include "drm.h"
30#include "i915_drm.h"
31#include "i915_drv.h"
1c5d22f7 32#include "i915_trace.h"
652c393a 33#include "intel_drv.h"
5a0e3ad6 34#include <linux/slab.h>
673a394b 35#include <linux/swap.h>
79e53945 36#include <linux/pci.h>
f8f235e5 37#include <linux/intel-gtt.h>
673a394b 38
0108a3ed 39static uint32_t i915_gem_get_gtt_alignment(struct drm_gem_object *obj);
ba3d8d74
DV		 40
41static int i915_gem_object_flush_gpu_write_domain(struct drm_gem_object *obj,
42 bool pipelined);
e47c68e9
EA		 43static void i915_gem_object_flush_gtt_write_domain(struct drm_gem_object *obj);
44static void i915_gem_object_flush_cpu_write_domain(struct drm_gem_object *obj);
e47c68e9
EA		 45static int i915_gem_object_set_to_cpu_domain(struct drm_gem_object *obj,
46 int write);
47static int i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object *obj,
48 uint64_t offset,
49 uint64_t size);
50static void i915_gem_object_set_to_full_cpu_read_domain(struct drm_gem_object *obj);
2cf34d7b
CW		 51static int i915_gem_object_wait_rendering(struct drm_gem_object *obj,
52 bool interruptible);
de151cf6
JB		 53static int i915_gem_object_bind_to_gtt(struct drm_gem_object *obj,
54 unsigned alignment);
de151cf6 55static void i915_gem_clear_fence_reg(struct drm_gem_object *obj);
71acb5eb
DA		 56static int i915_gem_phys_pwrite(struct drm_device *dev, struct drm_gem_object *obj,
57 struct drm_i915_gem_pwrite *args,
58 struct drm_file *file_priv);
be72615b 59static void i915_gem_free_object_tail(struct drm_gem_object *obj);
673a394b 60
5cdf5881
CW		 61static int
62i915_gem_object_get_pages(struct drm_gem_object *obj,
63 gfp_t gfpmask);
64
65static void
66i915_gem_object_put_pages(struct drm_gem_object *obj);
67
31169714
CW		 68static LIST_HEAD(shrink_list);
69static DEFINE_SPINLOCK(shrink_list_lock);
70
73aa808f
CW		 71/* some bookkeeping */
72static void i915_gem_info_add_obj(struct drm_i915_private *dev_priv,
73 size_t size)
74{
75 dev_priv->mm.object_count++;
76 dev_priv->mm.object_memory += size;
77}
78
79static void i915_gem_info_remove_obj(struct drm_i915_private *dev_priv,
80 size_t size)
81{
82 dev_priv->mm.object_count--;
83 dev_priv->mm.object_memory -= size;
84}
85
86static void i915_gem_info_add_gtt(struct drm_i915_private *dev_priv,
87 size_t size)
88{
89 dev_priv->mm.gtt_count++;
90 dev_priv->mm.gtt_memory += size;
91}
92
93static void i915_gem_info_remove_gtt(struct drm_i915_private *dev_priv,
94 size_t size)
95{
96 dev_priv->mm.gtt_count--;
97 dev_priv->mm.gtt_memory -= size;
98}
99
100static void i915_gem_info_add_pin(struct drm_i915_private *dev_priv,
101 size_t size)
102{
103 dev_priv->mm.pin_count++;
104 dev_priv->mm.pin_memory += size;
105}
106
107static void i915_gem_info_remove_pin(struct drm_i915_private *dev_priv,
108 size_t size)
109{
110 dev_priv->mm.pin_count--;
111 dev_priv->mm.pin_memory -= size;
112}
113
30dbf0c0
CW		 114int
115i915_gem_check_is_wedged(struct drm_device *dev)
116{
117 struct drm_i915_private *dev_priv = dev->dev_private;
118 struct completion *x = &dev_priv->error_completion;
119 unsigned long flags;
120 int ret;
121
122 if (!atomic_read(&dev_priv->mm.wedged))
123 return 0;
124
125 ret = wait_for_completion_interruptible(x);
126 if (ret)
127 return ret;
128
129 /* Success, we reset the GPU! */
130 if (!atomic_read(&dev_priv->mm.wedged))
131 return 0;
132
133 /* GPU is hung, bump the completion count to account for
134 * the token we just consumed so that we never hit zero and
135 * end up waiting upon a subsequent completion event that
136 * will never happen.
137 */
138 spin_lock_irqsave(&x->wait.lock, flags);
139 x->done++;
140 spin_unlock_irqrestore(&x->wait.lock, flags);
141 return -EIO;
142}
143
76c1dec1
CW		 144static int i915_mutex_lock_interruptible(struct drm_device *dev)
145{
146 struct drm_i915_private *dev_priv = dev->dev_private;
147 int ret;
148
149 ret = i915_gem_check_is_wedged(dev);
150 if (ret)
151 return ret;
152
153 ret = mutex_lock_interruptible(&dev->struct_mutex);
154 if (ret)
155 return ret;
156
157 if (atomic_read(&dev_priv->mm.wedged)) {
158 mutex_unlock(&dev->struct_mutex);
159 return -EAGAIN;
160 }
161
23bc5982 162 WARN_ON(i915_verify_lists(dev));
76c1dec1
CW		 163 return 0;
164}
30dbf0c0 165
7d1c4804
CW		 166static inline bool
167i915_gem_object_is_inactive(struct drm_i915_gem_object *obj_priv)
168{
169 return obj_priv->gtt_space &&
170 !obj_priv->active &&
171 obj_priv->pin_count == 0;
172}
173
73aa808f
CW		 174int i915_gem_do_init(struct drm_device *dev,
175 unsigned long start,
79e53945 176 unsigned long end)
673a394b
EA		 177{
178 drm_i915_private_t *dev_priv = dev->dev_private;
673a394b 179
79e53945
JB		 180 if (start >= end ||
181 (start & (PAGE_SIZE - 1)) != 0 ||
182 (end & (PAGE_SIZE - 1)) != 0) {
673a394b
EA		 183 return -EINVAL;
184 }
185
79e53945
JB		 186 drm_mm_init(&dev_priv->mm.gtt_space, start,
187 end - start);
673a394b 188
73aa808f 189 dev_priv->mm.gtt_total = end - start;
79e53945
JB		 190
191 return 0;
192}
673a394b 193
79e53945
JB		 194int
195i915_gem_init_ioctl(struct drm_device *dev, void *data,
196 struct drm_file *file_priv)
197{
198 struct drm_i915_gem_init *args = data;
199 int ret;
200
201 mutex_lock(&dev->struct_mutex);
202 ret = i915_gem_do_init(dev, args->gtt_start, args->gtt_end);
673a394b
EA		 203 mutex_unlock(&dev->struct_mutex);
204
79e53945 205 return ret;
673a394b
EA		 206}
207
5a125c3c
EA		 208int
209i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
210 struct drm_file *file_priv)
211{
73aa808f 212 struct drm_i915_private *dev_priv = dev->dev_private;
5a125c3c 213 struct drm_i915_gem_get_aperture *args = data;
5a125c3c
EA		 214
215 if (!(dev->driver->driver_features & DRIVER_GEM))
216 return -ENODEV;
217
73aa808f
CW		 218 mutex_lock(&dev->struct_mutex);
219 args->aper_size = dev_priv->mm.gtt_total;
220 args->aper_available_size = args->aper_size - dev_priv->mm.pin_memory;
221 mutex_unlock(&dev->struct_mutex);
5a125c3c
EA		 222
223 return 0;
224}
225
673a394b
EA		 226
227/**
228 * Creates a new mm object and returns a handle to it.
229 */
230int
231i915_gem_create_ioctl(struct drm_device *dev, void *data,
232 struct drm_file *file_priv)
233{
234 struct drm_i915_gem_create *args = data;
235 struct drm_gem_object *obj;
a1a2d1d3
PP		 236 int ret;
237 u32 handle;
673a394b
EA		 238
239 args->size = roundup(args->size, PAGE_SIZE);
240
241 /* Allocate the new object */
ac52bc56 242 obj = i915_gem_alloc_object(dev, args->size);
673a394b
EA		 243 if (obj == NULL)
244 return -ENOMEM;
245
246 ret = drm_gem_handle_create(file_priv, obj, &handle);
1dfd9754
CW		 247 if (ret) {
248 drm_gem_object_unreference_unlocked(obj);
673a394b 249 return ret;
1dfd9754 250 }
673a394b 251
1dfd9754
CW		 252 /* Sink the floating reference from kref_init(handlecount) */
253 drm_gem_object_handle_unreference_unlocked(obj);
673a394b 254
1dfd9754 255 args->handle = handle;
673a394b
EA		 256 return 0;
257}
258
eb01459f
EA		 259static inline int
260fast_shmem_read(struct page **pages,
261 loff_t page_base, int page_offset,
262 char __user *data,
263 int length)
264{
265 char __iomem *vaddr;
2bc43b5c 266 int unwritten;
eb01459f
EA		 267
268 vaddr = kmap_atomic(pages[page_base >> PAGE_SHIFT], KM_USER0);
269 if (vaddr == NULL)
270 return -ENOMEM;
2bc43b5c 271 unwritten = __copy_to_user_inatomic(data, vaddr + page_offset, length);
eb01459f
EA		 272 kunmap_atomic(vaddr, KM_USER0);
273
2bc43b5c
FM		 274 if (unwritten)
275 return -EFAULT;
276
277 return 0;
eb01459f
EA		 278}
279
280b713b
EA		 280static int i915_gem_object_needs_bit17_swizzle(struct drm_gem_object *obj)
281{
282 drm_i915_private_t *dev_priv = obj->dev->dev_private;
23010e43 283 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
280b713b
EA		 284
285 return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
286 obj_priv->tiling_mode != I915_TILING_NONE;
287}
288
99a03df5 289static inline void
40123c1f
EA		 290slow_shmem_copy(struct page *dst_page,
291 int dst_offset,
292 struct page *src_page,
293 int src_offset,
294 int length)
295{
296 char *dst_vaddr, *src_vaddr;
297
99a03df5
CW		 298 dst_vaddr = kmap(dst_page);
299 src_vaddr = kmap(src_page);
40123c1f
EA		 300
301 memcpy(dst_vaddr + dst_offset, src_vaddr + src_offset, length);
302
99a03df5
CW		 303 kunmap(src_page);
304 kunmap(dst_page);
40123c1f
EA		 305}
306
99a03df5 307static inline void
280b713b
EA		 308slow_shmem_bit17_copy(struct page *gpu_page,
309 int gpu_offset,
310 struct page *cpu_page,
311 int cpu_offset,
312 int length,
313 int is_read)
314{
315 char *gpu_vaddr, *cpu_vaddr;
316
317 /* Use the unswizzled path if this page isn't affected. */
318 if ((page_to_phys(gpu_page) & (1 << 17)) == 0) {
319 if (is_read)
320 return slow_shmem_copy(cpu_page, cpu_offset,
321 gpu_page, gpu_offset, length);
322 else
323 return slow_shmem_copy(gpu_page, gpu_offset,
324 cpu_page, cpu_offset, length);
325 }
326
99a03df5
CW		 327 gpu_vaddr = kmap(gpu_page);
328 cpu_vaddr = kmap(cpu_page);
280b713b
EA		 329
330 /* Copy the data, XORing A6 with A17 (1). The user already knows he's
331 * XORing with the other bits (A9 for Y, A9 and A10 for X)
332 */
333 while (length > 0) {
334 int cacheline_end = ALIGN(gpu_offset + 1, 64);
335 int this_length = min(cacheline_end - gpu_offset, length);
336 int swizzled_gpu_offset = gpu_offset ^ 64;
337
338 if (is_read) {
339 memcpy(cpu_vaddr + cpu_offset,
340 gpu_vaddr + swizzled_gpu_offset,
341 this_length);
342 } else {
343 memcpy(gpu_vaddr + swizzled_gpu_offset,
344 cpu_vaddr + cpu_offset,
345 this_length);
346 }
347 cpu_offset += this_length;
348 gpu_offset += this_length;
349 length -= this_length;
350 }
351
99a03df5
CW		 352 kunmap(cpu_page);
353 kunmap(gpu_page);
280b713b
EA		 354}
355
eb01459f
EA		 356/**
357 * This is the fast shmem pread path, which attempts to copy_from_user directly
358 * from the backing pages of the object to the user's address space. On a
359 * fault, it fails so we can fall back to i915_gem_shmem_pwrite_slow().
360 */
361static int
362i915_gem_shmem_pread_fast(struct drm_device *dev, struct drm_gem_object *obj,
363 struct drm_i915_gem_pread *args,
364 struct drm_file *file_priv)
365{
23010e43 366 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
eb01459f
EA		 367 ssize_t remain;
368 loff_t offset, page_base;
369 char __user *user_data;
370 int page_offset, page_length;
371 int ret;
372
373 user_data = (char __user *) (uintptr_t) args->data_ptr;
374 remain = args->size;
375
76c1dec1
CW		 376 ret = i915_mutex_lock_interruptible(dev);
377 if (ret)
378 return ret;
eb01459f 379
4bdadb97 380 ret = i915_gem_object_get_pages(obj, 0);
eb01459f
EA		 381 if (ret != 0)
382 goto fail_unlock;
383
384 ret = i915_gem_object_set_cpu_read_domain_range(obj, args->offset,
385 args->size);
386 if (ret != 0)
387 goto fail_put_pages;
388
23010e43 389 obj_priv = to_intel_bo(obj);
eb01459f
EA		 390 offset = args->offset;
391
392 while (remain > 0) {
393 /* Operation in this page
394 *
395 * page_base = page offset within aperture
396 * page_offset = offset within page
397 * page_length = bytes to copy for this page
398 */
399 page_base = (offset & ~(PAGE_SIZE-1));
400 page_offset = offset & (PAGE_SIZE-1);
401 page_length = remain;
402 if ((page_offset + remain) > PAGE_SIZE)
403 page_length = PAGE_SIZE - page_offset;
404
405 ret = fast_shmem_read(obj_priv->pages,
406 page_base, page_offset,
407 user_data, page_length);
408 if (ret)
409 goto fail_put_pages;
410
411 remain -= page_length;
412 user_data += page_length;
413 offset += page_length;
414 }
415
416fail_put_pages:
417 i915_gem_object_put_pages(obj);
418fail_unlock:
419 mutex_unlock(&dev->struct_mutex);
420
421 return ret;
422}
423
07f73f69
CW		 424static int
425i915_gem_object_get_pages_or_evict(struct drm_gem_object *obj)
426{
427 int ret;
428
4bdadb97 429 ret = i915_gem_object_get_pages(obj, __GFP_NORETRY | __GFP_NOWARN);
07f73f69
CW		 430
431 /* If we've insufficient memory to map in the pages, attempt
432 * to make some space by throwing out some old buffers.
433 */
434 if (ret == -ENOMEM) {
435 struct drm_device *dev = obj->dev;
07f73f69 436
0108a3ed
DV		 437 ret = i915_gem_evict_something(dev, obj->size,
438 i915_gem_get_gtt_alignment(obj));
07f73f69
CW		 439 if (ret)
440 return ret;
441
4bdadb97 442 ret = i915_gem_object_get_pages(obj, 0);
07f73f69
CW		 443 }
444
445 return ret;
446}
447
eb01459f
EA		 448/**
449 * This is the fallback shmem pread path, which allocates temporary storage
450 * in kernel space to copy_to_user into outside of the struct_mutex, so we
451 * can copy out of the object's backing pages while holding the struct mutex
452 * and not take page faults.
453 */
454static int
455i915_gem_shmem_pread_slow(struct drm_device *dev, struct drm_gem_object *obj,
456 struct drm_i915_gem_pread *args,
457 struct drm_file *file_priv)
458{
23010e43 459 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
eb01459f
EA		 460 struct mm_struct *mm = current->mm;
461 struct page **user_pages;
462 ssize_t remain;
463 loff_t offset, pinned_pages, i;
464 loff_t first_data_page, last_data_page, num_pages;
465 int shmem_page_index, shmem_page_offset;
466 int data_page_index, data_page_offset;
467 int page_length;
468 int ret;
469 uint64_t data_ptr = args->data_ptr;
280b713b 470 int do_bit17_swizzling;
eb01459f
EA		 471
472 remain = args->size;
473
474 /* Pin the user pages containing the data. We can't fault while
475 * holding the struct mutex, yet we want to hold it while
476 * dereferencing the user data.
477 */
478 first_data_page = data_ptr / PAGE_SIZE;
479 last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE;
480 num_pages = last_data_page - first_data_page + 1;
481
8e7d2b2c 482 user_pages = drm_calloc_large(num_pages, sizeof(struct page *));
eb01459f
EA		 483 if (user_pages == NULL)
484 return -ENOMEM;
485
486 down_read(&mm->mmap_sem);
487 pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr,
e5e9ecde 488 num_pages, 1, 0, user_pages, NULL);
eb01459f
EA		 489 up_read(&mm->mmap_sem);
490 if (pinned_pages < num_pages) {
491 ret = -EFAULT;
492 goto fail_put_user_pages;
493 }
494
280b713b
EA		 495 do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
496
76c1dec1
CW		 497 ret = i915_mutex_lock_interruptible(dev);
498 if (ret)
499 goto fail_put_user_pages;
eb01459f 500
07f73f69
CW		 501 ret = i915_gem_object_get_pages_or_evict(obj);
502 if (ret)
eb01459f
EA		 503 goto fail_unlock;
504
505 ret = i915_gem_object_set_cpu_read_domain_range(obj, args->offset,
506 args->size);
507 if (ret != 0)
508 goto fail_put_pages;
509
23010e43 510 obj_priv = to_intel_bo(obj);
eb01459f
EA		 511 offset = args->offset;
512
513 while (remain > 0) {
514 /* Operation in this page
515 *
516 * shmem_page_index = page number within shmem file
517 * shmem_page_offset = offset within page in shmem file
518 * data_page_index = page number in get_user_pages return
519 * data_page_offset = offset with data_page_index page.
520 * page_length = bytes to copy for this page
521 */
522 shmem_page_index = offset / PAGE_SIZE;
523 shmem_page_offset = offset & ~PAGE_MASK;
524 data_page_index = data_ptr / PAGE_SIZE - first_data_page;
525 data_page_offset = data_ptr & ~PAGE_MASK;
526
527 page_length = remain;
528 if ((shmem_page_offset + page_length) > PAGE_SIZE)
529 page_length = PAGE_SIZE - shmem_page_offset;
530 if ((data_page_offset + page_length) > PAGE_SIZE)
531 page_length = PAGE_SIZE - data_page_offset;
532
280b713b 533 if (do_bit17_swizzling) {
99a03df5 534 slow_shmem_bit17_copy(obj_priv->pages[shmem_page_index],
280b713b 535 shmem_page_offset,
99a03df5
CW		 536 user_pages[data_page_index],
537 data_page_offset,
538 page_length,
539 1);
540 } else {
541 slow_shmem_copy(user_pages[data_page_index],
542 data_page_offset,
543 obj_priv->pages[shmem_page_index],
544 shmem_page_offset,
545 page_length);
280b713b 546 }
eb01459f
EA		 547
548 remain -= page_length;
549 data_ptr += page_length;
550 offset += page_length;
551 }
552
553fail_put_pages:
554 i915_gem_object_put_pages(obj);
555fail_unlock:
556 mutex_unlock(&dev->struct_mutex);
557fail_put_user_pages:
558 for (i = 0; i < pinned_pages; i++) {
559 SetPageDirty(user_pages[i]);
560 page_cache_release(user_pages[i]);
561 }
8e7d2b2c 562 drm_free_large(user_pages);
eb01459f
EA		 563
564 return ret;
565}
566
673a394b
EA		 567/**
568 * Reads data from the object referenced by handle.
569 *
570 * On error, the contents of *data are undefined.
571 */
572int
573i915_gem_pread_ioctl(struct drm_device *dev, void *data,
574 struct drm_file *file_priv)
575{
576 struct drm_i915_gem_pread *args = data;
577 struct drm_gem_object *obj;
578 struct drm_i915_gem_object *obj_priv;
673a394b
EA		 579 int ret;
580
581 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
582 if (obj == NULL)
bf79cb91 583 return -ENOENT;
23010e43 584 obj_priv = to_intel_bo(obj);
673a394b
EA		 585
586 /* Bounds check source.
587 *
588 * XXX: This could use review for overflow issues...
589 */
590 if (args->offset > obj->size || args->size > obj->size ||
591 args->offset + args->size > obj->size) {
bc9025bd 592 drm_gem_object_unreference_unlocked(obj);
673a394b
EA		 593 return -EINVAL;
594 }
595
280b713b 596 if (i915_gem_object_needs_bit17_swizzle(obj)) {
eb01459f 597 ret = i915_gem_shmem_pread_slow(dev, obj, args, file_priv);
280b713b
EA		 598 } else {
599 ret = i915_gem_shmem_pread_fast(dev, obj, args, file_priv);
600 if (ret != 0)
601 ret = i915_gem_shmem_pread_slow(dev, obj, args,
602 file_priv);
603 }
673a394b 604
bc9025bd 605 drm_gem_object_unreference_unlocked(obj);
673a394b 606
eb01459f 607 return ret;
673a394b
EA		 608}
609
0839ccb8
KP		 610/* This is the fast write path which cannot handle
611 * page faults in the source data
9b7530cc 612 */
0839ccb8
KP		 613
614static inline int
615fast_user_write(struct io_mapping *mapping,
616 loff_t page_base, int page_offset,
617 char __user *user_data,
618 int length)
9b7530cc 619{
9b7530cc 620 char *vaddr_atomic;
0839ccb8 621 unsigned long unwritten;
9b7530cc 622
fca3ec01 623 vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base, KM_USER0);
0839ccb8
KP		 624 unwritten = __copy_from_user_inatomic_nocache(vaddr_atomic + page_offset,
625 user_data, length);
fca3ec01 626 io_mapping_unmap_atomic(vaddr_atomic, KM_USER0);
0839ccb8
KP		 627 if (unwritten)
628 return -EFAULT;
629 return 0;
630}
631
632/* Here's the write path which can sleep for
633 * page faults
634 */
635
ab34c226 636static inline void
3de09aa3
EA		 637slow_kernel_write(struct io_mapping *mapping,
638 loff_t gtt_base, int gtt_offset,
639 struct page *user_page, int user_offset,
640 int length)
0839ccb8 641{
ab34c226
CW		 642 char __iomem *dst_vaddr;
643 char *src_vaddr;
0839ccb8 644
ab34c226
CW		 645 dst_vaddr = io_mapping_map_wc(mapping, gtt_base);
646 src_vaddr = kmap(user_page);
647
648 memcpy_toio(dst_vaddr + gtt_offset,
649 src_vaddr + user_offset,
650 length);
651
652 kunmap(user_page);
653 io_mapping_unmap(dst_vaddr);
9b7530cc
LT		 654}
655
40123c1f
EA		 656static inline int
657fast_shmem_write(struct page **pages,
658 loff_t page_base, int page_offset,
659 char __user *data,
660 int length)
661{
662 char __iomem *vaddr;
d0088775 663 unsigned long unwritten;
40123c1f
EA		 664
665 vaddr = kmap_atomic(pages[page_base >> PAGE_SHIFT], KM_USER0);
666 if (vaddr == NULL)
667 return -ENOMEM;
d0088775 668 unwritten = __copy_from_user_inatomic(vaddr + page_offset, data, length);
40123c1f
EA		 669 kunmap_atomic(vaddr, KM_USER0);
670
d0088775
DA		 671 if (unwritten)
672 return -EFAULT;
40123c1f
EA		 673 return 0;
674}
675
3de09aa3
EA		 676/**
677 * This is the fast pwrite path, where we copy the data directly from the
678 * user into the GTT, uncached.
679 */
673a394b 680static int
3de09aa3
EA		 681i915_gem_gtt_pwrite_fast(struct drm_device *dev, struct drm_gem_object *obj,
682 struct drm_i915_gem_pwrite *args,
683 struct drm_file *file_priv)
673a394b 684{
23010e43 685 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
0839ccb8 686 drm_i915_private_t *dev_priv = dev->dev_private;
673a394b 687 ssize_t remain;
0839ccb8 688 loff_t offset, page_base;
673a394b 689 char __user *user_data;
0839ccb8
KP		 690 int page_offset, page_length;
691 int ret;
673a394b
EA		 692
693 user_data = (char __user *) (uintptr_t) args->data_ptr;
694 remain = args->size;
695 if (!access_ok(VERIFY_READ, user_data, remain))
696 return -EFAULT;
697
76c1dec1
CW		 698 ret = i915_mutex_lock_interruptible(dev);
699 if (ret)
700 return ret;
673a394b 701
673a394b
EA		 702 ret = i915_gem_object_pin(obj, 0);
703 if (ret) {
704 mutex_unlock(&dev->struct_mutex);
705 return ret;
706 }
2ef7eeaa 707 ret = i915_gem_object_set_to_gtt_domain(obj, 1);
673a394b
EA		 708 if (ret)
709 goto fail;
710
23010e43 711 obj_priv = to_intel_bo(obj);
673a394b 712 offset = obj_priv->gtt_offset + args->offset;
673a394b
EA		 713
714 while (remain > 0) {
715 /* Operation in this page
716 *
0839ccb8
KP		 717 * page_base = page offset within aperture
718 * page_offset = offset within page
719 * page_length = bytes to copy for this page
673a394b 720 */
0839ccb8
KP		 721 page_base = (offset & ~(PAGE_SIZE-1));
722 page_offset = offset & (PAGE_SIZE-1);
723 page_length = remain;
724 if ((page_offset + remain) > PAGE_SIZE)
725 page_length = PAGE_SIZE - page_offset;
726
727 ret = fast_user_write (dev_priv->mm.gtt_mapping, page_base,
728 page_offset, user_data, page_length);
729
730 /* If we get a fault while copying data, then (presumably) our
3de09aa3
EA		 731 * source page isn't available. Return the error and we'll
732 * retry in the slow path.
0839ccb8 733 */
3de09aa3
EA		 734 if (ret)
735 goto fail;
673a394b 736
0839ccb8
KP		 737 remain -= page_length;
738 user_data += page_length;
739 offset += page_length;
673a394b 740 }
673a394b
EA		 741
742fail:
743 i915_gem_object_unpin(obj);
744 mutex_unlock(&dev->struct_mutex);
745
746 return ret;
747}
748
3de09aa3
EA		 749/**
750 * This is the fallback GTT pwrite path, which uses get_user_pages to pin
751 * the memory and maps it using kmap_atomic for copying.
752 *
753 * This code resulted in x11perf -rgb10text consuming about 10% more CPU
754 * than using i915_gem_gtt_pwrite_fast on a G45 (32-bit).
755 */
3043c60c 756static int
3de09aa3
EA		 757i915_gem_gtt_pwrite_slow(struct drm_device *dev, struct drm_gem_object *obj,
758 struct drm_i915_gem_pwrite *args,
759 struct drm_file *file_priv)
673a394b 760{
23010e43 761 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
3de09aa3
EA		 762 drm_i915_private_t *dev_priv = dev->dev_private;
763 ssize_t remain;
764 loff_t gtt_page_base, offset;
765 loff_t first_data_page, last_data_page, num_pages;
766 loff_t pinned_pages, i;
767 struct page **user_pages;
768 struct mm_struct *mm = current->mm;
769 int gtt_page_offset, data_page_offset, data_page_index, page_length;
673a394b 770 int ret;
3de09aa3
EA		 771 uint64_t data_ptr = args->data_ptr;
772
773 remain = args->size;
774
775 /* Pin the user pages containing the data. We can't fault while
776 * holding the struct mutex, and all of the pwrite implementations
777 * want to hold it while dereferencing the user data.
778 */
779 first_data_page = data_ptr / PAGE_SIZE;
780 last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE;
781 num_pages = last_data_page - first_data_page + 1;
782
8e7d2b2c 783 user_pages = drm_calloc_large(num_pages, sizeof(struct page *));
3de09aa3
EA		 784 if (user_pages == NULL)
785 return -ENOMEM;
786
787 down_read(&mm->mmap_sem);
788 pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr,
789 num_pages, 0, 0, user_pages, NULL);
790 up_read(&mm->mmap_sem);
791 if (pinned_pages < num_pages) {
792 ret = -EFAULT;
793 goto out_unpin_pages;
794 }
673a394b 795
76c1dec1
CW		 796 ret = i915_mutex_lock_interruptible(dev);
797 if (ret)
798 goto out_unpin_pages;
799
3de09aa3
EA		 800 ret = i915_gem_object_pin(obj, 0);
801 if (ret)
802 goto out_unlock;
803
804 ret = i915_gem_object_set_to_gtt_domain(obj, 1);
805 if (ret)
806 goto out_unpin_object;
807
23010e43 808 obj_priv = to_intel_bo(obj);
3de09aa3
EA		 809 offset = obj_priv->gtt_offset + args->offset;
810
811 while (remain > 0) {
812 /* Operation in this page
813 *
814 * gtt_page_base = page offset within aperture
815 * gtt_page_offset = offset within page in aperture
816 * data_page_index = page number in get_user_pages return
817 * data_page_offset = offset with data_page_index page.
818 * page_length = bytes to copy for this page
819 */
820 gtt_page_base = offset & PAGE_MASK;
821 gtt_page_offset = offset & ~PAGE_MASK;
822 data_page_index = data_ptr / PAGE_SIZE - first_data_page;
823 data_page_offset = data_ptr & ~PAGE_MASK;
824
825 page_length = remain;
826 if ((gtt_page_offset + page_length) > PAGE_SIZE)
827 page_length = PAGE_SIZE - gtt_page_offset;
828 if ((data_page_offset + page_length) > PAGE_SIZE)
829 page_length = PAGE_SIZE - data_page_offset;
830
ab34c226
CW		 831 slow_kernel_write(dev_priv->mm.gtt_mapping,
832 gtt_page_base, gtt_page_offset,
833 user_pages[data_page_index],
834 data_page_offset,
835 page_length);
3de09aa3
EA		 836
837 remain -= page_length;
838 offset += page_length;
839 data_ptr += page_length;
840 }
841
842out_unpin_object:
843 i915_gem_object_unpin(obj);
844out_unlock:
845 mutex_unlock(&dev->struct_mutex);
846out_unpin_pages:
847 for (i = 0; i < pinned_pages; i++)
848 page_cache_release(user_pages[i]);
8e7d2b2c 849 drm_free_large(user_pages);
3de09aa3
EA		 850
851 return ret;
852}
853
40123c1f
EA		 854/**
855 * This is the fast shmem pwrite path, which attempts to directly
856 * copy_from_user into the kmapped pages backing the object.
857 */
3043c60c 858static int
40123c1f
EA		 859i915_gem_shmem_pwrite_fast(struct drm_device *dev, struct drm_gem_object *obj,
860 struct drm_i915_gem_pwrite *args,
861 struct drm_file *file_priv)
673a394b 862{
23010e43 863 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
40123c1f
EA		 864 ssize_t remain;
865 loff_t offset, page_base;
866 char __user *user_data;
867 int page_offset, page_length;
673a394b 868 int ret;
40123c1f
EA		 869
870 user_data = (char __user *) (uintptr_t) args->data_ptr;
871 remain = args->size;
673a394b 872
76c1dec1
CW		 873 ret = i915_mutex_lock_interruptible(dev);
874 if (ret)
875 return ret;
673a394b 876
4bdadb97 877 ret = i915_gem_object_get_pages(obj, 0);
40123c1f
EA		 878 if (ret != 0)
879 goto fail_unlock;
673a394b 880
e47c68e9 881 ret = i915_gem_object_set_to_cpu_domain(obj, 1);
40123c1f
EA		 882 if (ret != 0)
883 goto fail_put_pages;
884
23010e43 885 obj_priv = to_intel_bo(obj);
40123c1f
EA		 886 offset = args->offset;
887 obj_priv->dirty = 1;
888
889 while (remain > 0) {
890 /* Operation in this page
891 *
892 * page_base = page offset within aperture
893 * page_offset = offset within page
894 * page_length = bytes to copy for this page
895 */
896 page_base = (offset & ~(PAGE_SIZE-1));
897 page_offset = offset & (PAGE_SIZE-1);
898 page_length = remain;
899 if ((page_offset + remain) > PAGE_SIZE)
900 page_length = PAGE_SIZE - page_offset;
901
902 ret = fast_shmem_write(obj_priv->pages,
903 page_base, page_offset,
904 user_data, page_length);
905 if (ret)
906 goto fail_put_pages;
907
908 remain -= page_length;
909 user_data += page_length;
910 offset += page_length;
911 }
912
913fail_put_pages:
914 i915_gem_object_put_pages(obj);
915fail_unlock:
916 mutex_unlock(&dev->struct_mutex);
917
918 return ret;
919}
920
921/**
922 * This is the fallback shmem pwrite path, which uses get_user_pages to pin
923 * the memory and maps it using kmap_atomic for copying.
924 *
925 * This avoids taking mmap_sem for faulting on the user's address while the
926 * struct_mutex is held.
927 */
928static int
929i915_gem_shmem_pwrite_slow(struct drm_device *dev, struct drm_gem_object *obj,
930 struct drm_i915_gem_pwrite *args,
931 struct drm_file *file_priv)
932{
23010e43 933 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
40123c1f
EA		 934 struct mm_struct *mm = current->mm;
935 struct page **user_pages;
936 ssize_t remain;
937 loff_t offset, pinned_pages, i;
938 loff_t first_data_page, last_data_page, num_pages;
939 int shmem_page_index, shmem_page_offset;
940 int data_page_index, data_page_offset;
941 int page_length;
942 int ret;
943 uint64_t data_ptr = args->data_ptr;
280b713b 944 int do_bit17_swizzling;
40123c1f
EA		 945
946 remain = args->size;
947
948 /* Pin the user pages containing the data. We can't fault while
949 * holding the struct mutex, and all of the pwrite implementations
950 * want to hold it while dereferencing the user data.
951 */
952 first_data_page = data_ptr / PAGE_SIZE;
953 last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE;
954 num_pages = last_data_page - first_data_page + 1;
955
8e7d2b2c 956 user_pages = drm_calloc_large(num_pages, sizeof(struct page *));
40123c1f
EA		 957 if (user_pages == NULL)
958 return -ENOMEM;
959
960 down_read(&mm->mmap_sem);
961 pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr,
962 num_pages, 0, 0, user_pages, NULL);
963 up_read(&mm->mmap_sem);
964 if (pinned_pages < num_pages) {
965 ret = -EFAULT;
966 goto fail_put_user_pages;
673a394b
EA		 967 }
968
280b713b
EA		 969 do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
970
76c1dec1
CW		 971 ret = i915_mutex_lock_interruptible(dev);
972 if (ret)
973 goto fail_put_user_pages;
40123c1f 974
07f73f69
CW		 975 ret = i915_gem_object_get_pages_or_evict(obj);
976 if (ret)
40123c1f
EA		 977 goto fail_unlock;
978
979 ret = i915_gem_object_set_to_cpu_domain(obj, 1);
980 if (ret != 0)
981 goto fail_put_pages;
982
23010e43 983 obj_priv = to_intel_bo(obj);
673a394b 984 offset = args->offset;
40123c1f 985 obj_priv->dirty = 1;
673a394b 986
40123c1f
EA		 987 while (remain > 0) {
988 /* Operation in this page
989 *
990 * shmem_page_index = page number within shmem file
991 * shmem_page_offset = offset within page in shmem file
992 * data_page_index = page number in get_user_pages return
993 * data_page_offset = offset with data_page_index page.
994 * page_length = bytes to copy for this page
995 */
996 shmem_page_index = offset / PAGE_SIZE;
997 shmem_page_offset = offset & ~PAGE_MASK;
998 data_page_index = data_ptr / PAGE_SIZE - first_data_page;
999 data_page_offset = data_ptr & ~PAGE_MASK;
1000
1001 page_length = remain;
1002 if ((shmem_page_offset + page_length) > PAGE_SIZE)
1003 page_length = PAGE_SIZE - shmem_page_offset;
1004 if ((data_page_offset + page_length) > PAGE_SIZE)
1005 page_length = PAGE_SIZE - data_page_offset;
1006
280b713b 1007 if (do_bit17_swizzling) {
99a03df5 1008 slow_shmem_bit17_copy(obj_priv->pages[shmem_page_index],
280b713b
EA		 1009 shmem_page_offset,
1010 user_pages[data_page_index],
1011 data_page_offset,
99a03df5
CW		 1012 page_length,
1013 0);
1014 } else {
1015 slow_shmem_copy(obj_priv->pages[shmem_page_index],
1016 shmem_page_offset,
1017 user_pages[data_page_index],
1018 data_page_offset,
1019 page_length);
280b713b 1020 }
40123c1f
EA		 1021
1022 remain -= page_length;
1023 data_ptr += page_length;
1024 offset += page_length;
673a394b
EA		 1025 }
1026
40123c1f
EA		 1027fail_put_pages:
1028 i915_gem_object_put_pages(obj);
1029fail_unlock:
673a394b 1030 mutex_unlock(&dev->struct_mutex);
40123c1f
EA		 1031fail_put_user_pages:
1032 for (i = 0; i < pinned_pages; i++)
1033 page_cache_release(user_pages[i]);
8e7d2b2c 1034 drm_free_large(user_pages);
673a394b 1035
40123c1f 1036 return ret;
673a394b
EA		 1037}
1038
1039/**
1040 * Writes data to the object referenced by handle.
1041 *
1042 * On error, the contents of the buffer that were to be modified are undefined.
1043 */
1044int
1045i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
1046 struct drm_file *file_priv)
1047{
1048 struct drm_i915_gem_pwrite *args = data;
1049 struct drm_gem_object *obj;
1050 struct drm_i915_gem_object *obj_priv;
1051 int ret = 0;
1052
1053 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
1054 if (obj == NULL)
bf79cb91 1055 return -ENOENT;
23010e43 1056 obj_priv = to_intel_bo(obj);
673a394b
EA		 1057
1058 /* Bounds check destination.
1059 *
1060 * XXX: This could use review for overflow issues...
1061 */
1062 if (args->offset > obj->size || args->size > obj->size ||
1063 args->offset + args->size > obj->size) {
bc9025bd 1064 drm_gem_object_unreference_unlocked(obj);
673a394b
EA		 1065 return -EINVAL;
1066 }
1067
1068 /* We can only do the GTT pwrite on untiled buffers, as otherwise
1069 * it would end up going through the fenced access, and we'll get
1070 * different detiling behavior between reading and writing.
1071 * pread/pwrite currently are reading and writing from the CPU
1072 * perspective, requiring manual detiling by the client.
1073 */
71acb5eb
DA		 1074 if (obj_priv->phys_obj)
1075 ret = i915_gem_phys_pwrite(dev, obj, args, file_priv);
1076 else if (obj_priv->tiling_mode == I915_TILING_NONE &&
5cdf5881 1077 obj_priv->gtt_space &&
9b8c4a0b 1078 obj->write_domain != I915_GEM_DOMAIN_CPU) {
3de09aa3
EA		 1079 ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file_priv);
1080 if (ret == -EFAULT) {
1081 ret = i915_gem_gtt_pwrite_slow(dev, obj, args,
1082 file_priv);
1083 }
280b713b
EA		 1084 } else if (i915_gem_object_needs_bit17_swizzle(obj)) {
1085 ret = i915_gem_shmem_pwrite_slow(dev, obj, args, file_priv);
40123c1f
EA		 1086 } else {
1087 ret = i915_gem_shmem_pwrite_fast(dev, obj, args, file_priv);
1088 if (ret == -EFAULT) {
1089 ret = i915_gem_shmem_pwrite_slow(dev, obj, args,
1090 file_priv);
1091 }
1092 }
673a394b
EA		 1093
1094#if WATCH_PWRITE
1095 if (ret)
1096 DRM_INFO("pwrite failed %d\n", ret);
1097#endif
1098
bc9025bd 1099 drm_gem_object_unreference_unlocked(obj);
673a394b
EA		 1100
1101 return ret;
1102}
1103
1104/**
2ef7eeaa
EA		 1105 * Called when user space prepares to use an object with the CPU, either
1106 * through the mmap ioctl's mapping or a GTT mapping.
673a394b
EA		 1107 */
1108int
1109i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1110 struct drm_file *file_priv)
1111{
a09ba7fa 1112 struct drm_i915_private *dev_priv = dev->dev_private;
673a394b
EA		 1113 struct drm_i915_gem_set_domain *args = data;
1114 struct drm_gem_object *obj;
652c393a 1115 struct drm_i915_gem_object *obj_priv;
2ef7eeaa
EA		 1116 uint32_t read_domains = args->read_domains;
1117 uint32_t write_domain = args->write_domain;
673a394b
EA		 1118 int ret;
1119
1120 if (!(dev->driver->driver_features & DRIVER_GEM))
1121 return -ENODEV;
1122
2ef7eeaa 1123 /* Only handle setting domains to types used by the CPU. */
21d509e3 1124 if (write_domain & I915_GEM_GPU_DOMAINS)
2ef7eeaa
EA		 1125 return -EINVAL;
1126
21d509e3 1127 if (read_domains & I915_GEM_GPU_DOMAINS)
2ef7eeaa
EA		 1128 return -EINVAL;
1129
1130 /* Having something in the write domain implies it's in the read
1131 * domain, and only that read domain. Enforce that in the request.
1132 */
1133 if (write_domain != 0 && read_domains != write_domain)
1134 return -EINVAL;
1135
673a394b
EA		 1136 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
1137 if (obj == NULL)
bf79cb91 1138 return -ENOENT;
23010e43 1139 obj_priv = to_intel_bo(obj);
673a394b 1140
76c1dec1
CW		 1141 ret = i915_mutex_lock_interruptible(dev);
1142 if (ret) {
1143 drm_gem_object_unreference_unlocked(obj);
1144 return ret;
1145 }
652c393a
JB		 1146
1147 intel_mark_busy(dev, obj);
1148
2ef7eeaa
EA		 1149 if (read_domains & I915_GEM_DOMAIN_GTT) {
1150 ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0);
02354392 1151
a09ba7fa
EA		 1152 /* Update the LRU on the fence for the CPU access that's
1153 * about to occur.
1154 */
1155 if (obj_priv->fence_reg != I915_FENCE_REG_NONE) {
007cc8ac
DV		 1156 struct drm_i915_fence_reg *reg =
1157 &dev_priv->fence_regs[obj_priv->fence_reg];
1158 list_move_tail(&reg->lru_list,
a09ba7fa
EA		 1159 &dev_priv->mm.fence_list);
1160 }
1161
02354392
EA		 1162 /* Silently promote "you're not bound, there was nothing to do"
1163 * to success, since the client was just asking us to
1164 * make sure everything was done.
1165 */
1166 if (ret == -EINVAL)
1167 ret = 0;
2ef7eeaa 1168 } else {
e47c68e9 1169 ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0);
2ef7eeaa
EA		 1170 }
1171
7d1c4804
CW		 1172 /* Maintain LRU order of "inactive" objects */
1173 if (ret == 0 && i915_gem_object_is_inactive(obj_priv))
1174 list_move_tail(&obj_priv->list, &dev_priv->mm.inactive_list);
1175
673a394b
EA		 1176 drm_gem_object_unreference(obj);
1177 mutex_unlock(&dev->struct_mutex);
1178 return ret;
1179}
1180
1181/**
1182 * Called when user space has done writes to this buffer
1183 */
1184int
1185i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
1186 struct drm_file *file_priv)
1187{
1188 struct drm_i915_gem_sw_finish *args = data;
1189 struct drm_gem_object *obj;
673a394b
EA		 1190 int ret = 0;
1191
1192 if (!(dev->driver->driver_features & DRIVER_GEM))
1193 return -ENODEV;
1194
673a394b 1195 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
76c1dec1 1196 if (obj == NULL)
bf79cb91 1197 return -ENOENT;
76c1dec1
CW		 1198
1199 ret = i915_mutex_lock_interruptible(dev);
1200 if (ret) {
1201 drm_gem_object_unreference_unlocked(obj);
1202 return ret;
673a394b
EA		 1203 }
1204
673a394b 1205 /* Pinned buffers may be scanout, so flush the cache */
3d2a812a 1206 if (to_intel_bo(obj)->pin_count)
e47c68e9
EA		 1207 i915_gem_object_flush_cpu_write_domain(obj);
1208
673a394b
EA		 1209 drm_gem_object_unreference(obj);
1210 mutex_unlock(&dev->struct_mutex);
1211 return ret;
1212}
1213
1214/**
1215 * Maps the contents of an object, returning the address it is mapped
1216 * into.
1217 *
1218 * While the mapping holds a reference on the contents of the object, it doesn't
1219 * imply a ref on the object itself.
1220 */
1221int
1222i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
1223 struct drm_file *file_priv)
1224{
1225 struct drm_i915_gem_mmap *args = data;
1226 struct drm_gem_object *obj;
1227 loff_t offset;
1228 unsigned long addr;
1229
1230 if (!(dev->driver->driver_features & DRIVER_GEM))
1231 return -ENODEV;
1232
1233 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
1234 if (obj == NULL)
bf79cb91 1235 return -ENOENT;
673a394b
EA		 1236
1237 offset = args->offset;
1238
1239 down_write(&current->mm->mmap_sem);
1240 addr = do_mmap(obj->filp, 0, args->size,
1241 PROT_READ | PROT_WRITE, MAP_SHARED,
1242 args->offset);
1243 up_write(&current->mm->mmap_sem);
bc9025bd 1244 drm_gem_object_unreference_unlocked(obj);
673a394b
EA		 1245 if (IS_ERR((void *)addr))
1246 return addr;
1247
1248 args->addr_ptr = (uint64_t) addr;
1249
1250 return 0;
1251}
1252
de151cf6
JB		 1253/**
1254 * i915_gem_fault - fault a page into the GTT
1255 * vma: VMA in question
1256 * vmf: fault info
1257 *
1258 * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
1259 * from userspace. The fault handler takes care of binding the object to
1260 * the GTT (if needed), allocating and programming a fence register (again,
1261 * only if needed based on whether the old reg is still valid or the object
1262 * is tiled) and inserting a new PTE into the faulting process.
1263 *
1264 * Note that the faulting process may involve evicting existing objects
1265 * from the GTT and/or fence registers to make room. So performance may
1266 * suffer if the GTT working set is large or there are few fence registers
1267 * left.
1268 */
1269int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
1270{
1271 struct drm_gem_object *obj = vma->vm_private_data;
1272 struct drm_device *dev = obj->dev;
7d1c4804 1273 drm_i915_private_t *dev_priv = dev->dev_private;
23010e43 1274 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
de151cf6
JB		 1275 pgoff_t page_offset;
1276 unsigned long pfn;
1277 int ret = 0;
0f973f27 1278 bool write = !!(vmf->flags & FAULT_FLAG_WRITE);
de151cf6
JB		 1279
1280 /* We don't use vmf->pgoff since that has the fake offset */
1281 page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >>
1282 PAGE_SHIFT;
1283
1284 /* Now bind it into the GTT if needed */
1285 mutex_lock(&dev->struct_mutex);
1286 if (!obj_priv->gtt_space) {
e67b8ce1 1287 ret = i915_gem_object_bind_to_gtt(obj, 0);
c715089f
CW		 1288 if (ret)
1289 goto unlock;
07f4f3e8 1290
07f4f3e8 1291 ret = i915_gem_object_set_to_gtt_domain(obj, write);
c715089f
CW		 1292 if (ret)
1293 goto unlock;
de151cf6
JB		 1294 }
1295
1296 /* Need a new fence register? */
a09ba7fa 1297 if (obj_priv->tiling_mode != I915_TILING_NONE) {
2cf34d7b 1298 ret = i915_gem_object_get_fence_reg(obj, true);
c715089f
CW		 1299 if (ret)
1300 goto unlock;
d9ddcb96 1301 }
de151cf6 1302
7d1c4804
CW		 1303 if (i915_gem_object_is_inactive(obj_priv))
1304 list_move_tail(&obj_priv->list, &dev_priv->mm.inactive_list);
1305
de151cf6
JB		 1306 pfn = ((dev->agp->base + obj_priv->gtt_offset) >> PAGE_SHIFT) +
1307 page_offset;
1308
1309 /* Finally, remap it using the new GTT offset */
1310 ret = vm_insert_pfn(vma, (unsigned long)vmf->virtual_address, pfn);
c715089f 1311unlock:
de151cf6
JB		 1312 mutex_unlock(&dev->struct_mutex);
1313
1314 switch (ret) {
c715089f
CW		 1315 case 0:
1316 case -ERESTARTSYS:
1317 return VM_FAULT_NOPAGE;
de151cf6
JB		 1318 case -ENOMEM:
1319 case -EAGAIN:
1320 return VM_FAULT_OOM;
de151cf6 1321 default:
c715089f 1322 return VM_FAULT_SIGBUS;
de151cf6
JB		 1323 }
1324}
1325
1326/**
1327 * i915_gem_create_mmap_offset - create a fake mmap offset for an object
1328 * @obj: obj in question
1329 *
1330 * GEM memory mapping works by handing back to userspace a fake mmap offset
1331 * it can use in a subsequent mmap(2) call. The DRM core code then looks
1332 * up the object based on the offset and sets up the various memory mapping
1333 * structures.
1334 *
1335 * This routine allocates and attaches a fake offset for @obj.
1336 */
1337static int
1338i915_gem_create_mmap_offset(struct drm_gem_object *obj)
1339{
1340 struct drm_device *dev = obj->dev;
1341 struct drm_gem_mm *mm = dev->mm_private;
23010e43 1342 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
de151cf6 1343 struct drm_map_list *list;
f77d390c 1344 struct drm_local_map *map;
de151cf6
JB		 1345 int ret = 0;
1346
1347 /* Set the object up for mmap'ing */
1348 list = &obj->map_list;
9a298b2a 1349 list->map = kzalloc(sizeof(struct drm_map_list), GFP_KERNEL);
de151cf6
JB		 1350 if (!list->map)
1351 return -ENOMEM;
1352
1353 map = list->map;
1354 map->type = _DRM_GEM;
1355 map->size = obj->size;
1356 map->handle = obj;
1357
1358 /* Get a DRM GEM mmap offset allocated... */
1359 list->file_offset_node = drm_mm_search_free(&mm->offset_manager,
1360 obj->size / PAGE_SIZE, 0, 0);
1361 if (!list->file_offset_node) {
1362 DRM_ERROR("failed to allocate offset for bo %d\n", obj->name);
9e0ae534 1363 ret = -ENOSPC;
de151cf6
JB		 1364 goto out_free_list;
1365 }
1366
1367 list->file_offset_node = drm_mm_get_block(list->file_offset_node,
1368 obj->size / PAGE_SIZE, 0);
1369 if (!list->file_offset_node) {
1370 ret = -ENOMEM;
1371 goto out_free_list;
1372 }
1373
1374 list->hash.key = list->file_offset_node->start;
9e0ae534
CW		 1375 ret = drm_ht_insert_item(&mm->offset_hash, &list->hash);
1376 if (ret) {
de151cf6
JB		 1377 DRM_ERROR("failed to add to map hash\n");
1378 goto out_free_mm;
1379 }
1380
1381 /* By now we should be all set, any drm_mmap request on the offset
1382 * below will get to our mmap & fault handler */
1383 obj_priv->mmap_offset = ((uint64_t) list->hash.key) << PAGE_SHIFT;
1384
1385 return 0;
1386
1387out_free_mm:
1388 drm_mm_put_block(list->file_offset_node);
1389out_free_list:
9a298b2a 1390 kfree(list->map);
de151cf6
JB		 1391
1392 return ret;
1393}
1394
901782b2
CW		 1395/**
1396 * i915_gem_release_mmap - remove physical page mappings
1397 * @obj: obj in question
1398 *
af901ca1 1399 * Preserve the reservation of the mmapping with the DRM core code, but
901782b2
CW		 1400 * relinquish ownership of the pages back to the system.
1401 *
1402 * It is vital that we remove the page mapping if we have mapped a tiled
1403 * object through the GTT and then lose the fence register due to
1404 * resource pressure. Similarly if the object has been moved out of the
1405 * aperture, than pages mapped into userspace must be revoked. Removing the
1406 * mapping will then trigger a page fault on the next user access, allowing
1407 * fixup by i915_gem_fault().
1408 */
d05ca301 1409void
901782b2
CW		 1410i915_gem_release_mmap(struct drm_gem_object *obj)
1411{
1412 struct drm_device *dev = obj->dev;
23010e43 1413 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
901782b2
CW		 1414
1415 if (dev->dev_mapping)
1416 unmap_mapping_range(dev->dev_mapping,
1417 obj_priv->mmap_offset, obj->size, 1);
1418}
1419
ab00b3e5
JB		 1420static void
1421i915_gem_free_mmap_offset(struct drm_gem_object *obj)
1422{
1423 struct drm_device *dev = obj->dev;
23010e43 1424 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
ab00b3e5
JB		 1425 struct drm_gem_mm *mm = dev->mm_private;
1426 struct drm_map_list *list;
1427
1428 list = &obj->map_list;
1429 drm_ht_remove_item(&mm->offset_hash, &list->hash);
1430
1431 if (list->file_offset_node) {
1432 drm_mm_put_block(list->file_offset_node);
1433 list->file_offset_node = NULL;
1434 }
1435
1436 if (list->map) {
9a298b2a 1437 kfree(list->map);
ab00b3e5
JB		 1438 list->map = NULL;
1439 }
1440
1441 obj_priv->mmap_offset = 0;
1442}
1443
de151cf6
JB		 1444/**
1445 * i915_gem_get_gtt_alignment - return required GTT alignment for an object
1446 * @obj: object to check
1447 *
1448 * Return the required GTT alignment for an object, taking into account
1449 * potential fence register mapping if needed.
1450 */
1451static uint32_t
1452i915_gem_get_gtt_alignment(struct drm_gem_object *obj)
1453{
1454 struct drm_device *dev = obj->dev;
23010e43 1455 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
de151cf6
JB		 1456 int start, i;
1457
1458 /*
1459 * Minimum alignment is 4k (GTT page size), but might be greater
1460 * if a fence register is needed for the object.
1461 */
a6c45cf0 1462 if (INTEL_INFO(dev)->gen >= 4 || obj_priv->tiling_mode == I915_TILING_NONE)
de151cf6
JB		 1463 return 4096;
1464
1465 /*
1466 * Previous chips need to be aligned to the size of the smallest
1467 * fence register that can contain the object.
1468 */
a6c45cf0 1469 if (INTEL_INFO(dev)->gen == 3)
de151cf6
JB		 1470 start = 1024*1024;
1471 else
1472 start = 512*1024;
1473
1474 for (i = start; i < obj->size; i <<= 1)
1475 ;
1476
1477 return i;
1478}
1479
1480/**
1481 * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
1482 * @dev: DRM device
1483 * @data: GTT mapping ioctl data
1484 * @file_priv: GEM object info
1485 *
1486 * Simply returns the fake offset to userspace so it can mmap it.
1487 * The mmap call will end up in drm_gem_mmap(), which will set things
1488 * up so we can get faults in the handler above.
1489 *
1490 * The fault handler will take care of binding the object into the GTT
1491 * (since it may have been evicted to make room for something), allocating
1492 * a fence register, and mapping the appropriate aperture address into
1493 * userspace.
1494 */
1495int
1496i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
1497 struct drm_file *file_priv)
1498{
1499 struct drm_i915_gem_mmap_gtt *args = data;
de151cf6
JB		 1500 struct drm_gem_object *obj;
1501 struct drm_i915_gem_object *obj_priv;
1502 int ret;
1503
1504 if (!(dev->driver->driver_features & DRIVER_GEM))
1505 return -ENODEV;
1506
1507 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
1508 if (obj == NULL)
bf79cb91 1509 return -ENOENT;
de151cf6 1510
76c1dec1
CW		 1511 ret = i915_mutex_lock_interruptible(dev);
1512 if (ret) {
1513 drm_gem_object_unreference_unlocked(obj);
1514 return ret;
1515 }
de151cf6 1516
23010e43 1517 obj_priv = to_intel_bo(obj);
de151cf6 1518
ab18282d
CW		 1519 if (obj_priv->madv != I915_MADV_WILLNEED) {
1520 DRM_ERROR("Attempting to mmap a purgeable buffer\n");
1521 drm_gem_object_unreference(obj);
1522 mutex_unlock(&dev->struct_mutex);
1523 return -EINVAL;
1524 }
1525
1526
de151cf6
JB		 1527 if (!obj_priv->mmap_offset) {
1528 ret = i915_gem_create_mmap_offset(obj);
13af1062
CW		 1529 if (ret) {
1530 drm_gem_object_unreference(obj);
1531 mutex_unlock(&dev->struct_mutex);
de151cf6 1532 return ret;
13af1062 1533 }
de151cf6
JB		 1534 }
1535
1536 args->offset = obj_priv->mmap_offset;
1537
de151cf6
JB		 1538 /*
1539 * Pull it into the GTT so that we have a page list (makes the
1540 * initial fault faster and any subsequent flushing possible).
1541 */
1542 if (!obj_priv->agp_mem) {
e67b8ce1 1543 ret = i915_gem_object_bind_to_gtt(obj, 0);
de151cf6
JB		 1544 if (ret) {
1545 drm_gem_object_unreference(obj);
1546 mutex_unlock(&dev->struct_mutex);
1547 return ret;
1548 }
de151cf6
JB		 1549 }
1550
1551 drm_gem_object_unreference(obj);
1552 mutex_unlock(&dev->struct_mutex);
1553
1554 return 0;
1555}
1556
5cdf5881 1557static void
856fa198 1558i915_gem_object_put_pages(struct drm_gem_object *obj)
673a394b 1559{
23010e43 1560 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
673a394b
EA		 1561 int page_count = obj->size / PAGE_SIZE;
1562 int i;
1563
856fa198 1564 BUG_ON(obj_priv->pages_refcount == 0);
bb6baf76 1565 BUG_ON(obj_priv->madv == __I915_MADV_PURGED);
673a394b 1566
856fa198
EA		 1567 if (--obj_priv->pages_refcount != 0)
1568 return;
673a394b 1569
280b713b
EA		 1570 if (obj_priv->tiling_mode != I915_TILING_NONE)
1571 i915_gem_object_save_bit_17_swizzle(obj);
1572
3ef94daa 1573 if (obj_priv->madv == I915_MADV_DONTNEED)
13a05fd9 1574 obj_priv->dirty = 0;
3ef94daa
CW		 1575
1576 for (i = 0; i < page_count; i++) {
3ef94daa
CW		 1577 if (obj_priv->dirty)
1578 set_page_dirty(obj_priv->pages[i]);
1579
1580 if (obj_priv->madv == I915_MADV_WILLNEED)
856fa198 1581 mark_page_accessed(obj_priv->pages[i]);
3ef94daa
CW		 1582
1583 page_cache_release(obj_priv->pages[i]);
1584 }
673a394b
EA		 1585 obj_priv->dirty = 0;
1586
8e7d2b2c 1587 drm_free_large(obj_priv->pages);
856fa198 1588 obj_priv->pages = NULL;
673a394b
EA		 1589}
1590
a56ba56c
CW		 1591static uint32_t
1592i915_gem_next_request_seqno(struct drm_device *dev,
1593 struct intel_ring_buffer *ring)
1594{
1595 drm_i915_private_t *dev_priv = dev->dev_private;
1596
1597 ring->outstanding_lazy_request = true;
1598 return dev_priv->next_seqno;
1599}
1600
673a394b 1601static void
617dbe27 1602i915_gem_object_move_to_active(struct drm_gem_object *obj,
852835f3 1603 struct intel_ring_buffer *ring)
673a394b 1604{
a56ba56c 1605 struct drm_device *dev = obj->dev;
23010e43 1606 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
a56ba56c 1607 uint32_t seqno = i915_gem_next_request_seqno(dev, ring);
617dbe27 1608
852835f3
ZN		 1609 BUG_ON(ring == NULL);
1610 obj_priv->ring = ring;
673a394b
EA		 1611
1612 /* Add a reference if we're newly entering the active list. */
1613 if (!obj_priv->active) {
1614 drm_gem_object_reference(obj);
1615 obj_priv->active = 1;
1616 }
e35a41de 1617
673a394b 1618 /* Move from whatever list we were on to the tail of execution. */
852835f3 1619 list_move_tail(&obj_priv->list, &ring->active_list);
a56ba56c 1620 obj_priv->last_rendering_seqno = seqno;
673a394b
EA		 1621}
1622
ce44b0ea
EA		 1623static void
1624i915_gem_object_move_to_flushing(struct drm_gem_object *obj)
1625{
1626 struct drm_device *dev = obj->dev;
1627 drm_i915_private_t *dev_priv = dev->dev_private;
23010e43 1628 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
ce44b0ea
EA		 1629
1630 BUG_ON(!obj_priv->active);
1631 list_move_tail(&obj_priv->list, &dev_priv->mm.flushing_list);
1632 obj_priv->last_rendering_seqno = 0;
1633}
673a394b 1634
963b4836
CW		 1635/* Immediately discard the backing storage */
1636static void
1637i915_gem_object_truncate(struct drm_gem_object *obj)
1638{
23010e43 1639 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
bb6baf76 1640 struct inode *inode;
963b4836 1641
ae9fed6b
CW		 1642 /* Our goal here is to return as much of the memory as
1643 * is possible back to the system as we are called from OOM.
1644 * To do this we must instruct the shmfs to drop all of its
1645 * backing pages, *now*. Here we mirror the actions taken
1646 * when by shmem_delete_inode() to release the backing store.
1647 */
bb6baf76 1648 inode = obj->filp->f_path.dentry->d_inode;
ae9fed6b
CW		 1649 truncate_inode_pages(inode->i_mapping, 0);
1650 if (inode->i_op->truncate_range)
1651 inode->i_op->truncate_range(inode, 0, (loff_t)-1);
bb6baf76
CW		 1652
1653 obj_priv->madv = __I915_MADV_PURGED;
963b4836
CW		 1654}
1655
1656static inline int
1657i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj_priv)
1658{
1659 return obj_priv->madv == I915_MADV_DONTNEED;
1660}
1661
673a394b
EA		 1662static void
1663i915_gem_object_move_to_inactive(struct drm_gem_object *obj)
1664{
1665 struct drm_device *dev = obj->dev;
1666 drm_i915_private_t *dev_priv = dev->dev_private;
23010e43 1667 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
673a394b 1668
673a394b 1669 if (obj_priv->pin_count != 0)
f13d3f73 1670 list_move_tail(&obj_priv->list, &dev_priv->mm.pinned_list);
673a394b
EA		 1671 else
1672 list_move_tail(&obj_priv->list, &dev_priv->mm.inactive_list);
1673
99fcb766
DV		 1674 BUG_ON(!list_empty(&obj_priv->gpu_write_list));
1675
ce44b0ea 1676 obj_priv->last_rendering_seqno = 0;
852835f3 1677 obj_priv->ring = NULL;
673a394b
EA		 1678 if (obj_priv->active) {
1679 obj_priv->active = 0;
1680 drm_gem_object_unreference(obj);
1681 }
23bc5982 1682 WARN_ON(i915_verify_lists(dev));
673a394b
EA		 1683}
1684
9220434a 1685static void
63560396 1686i915_gem_process_flushing_list(struct drm_device *dev,
8a1a49f9 1687 uint32_t flush_domains,
852835f3 1688 struct intel_ring_buffer *ring)
63560396
DV		 1689{
1690 drm_i915_private_t *dev_priv = dev->dev_private;
1691 struct drm_i915_gem_object *obj_priv, *next;
1692
1693 list_for_each_entry_safe(obj_priv, next,
1694 &dev_priv->mm.gpu_write_list,
1695 gpu_write_list) {
a8089e84 1696 struct drm_gem_object *obj = &obj_priv->base;
63560396 1697
2b6efaa4
CW		 1698 if (obj->write_domain & flush_domains &&
1699 obj_priv->ring == ring) {
63560396
DV		 1700 uint32_t old_write_domain = obj->write_domain;
1701
1702 obj->write_domain = 0;
1703 list_del_init(&obj_priv->gpu_write_list);
617dbe27 1704 i915_gem_object_move_to_active(obj, ring);
63560396
DV		 1705
1706 /* update the fence lru list */
007cc8ac
DV		 1707 if (obj_priv->fence_reg != I915_FENCE_REG_NONE) {
1708 struct drm_i915_fence_reg *reg =
1709 &dev_priv->fence_regs[obj_priv->fence_reg];
1710 list_move_tail(&reg->lru_list,
63560396 1711 &dev_priv->mm.fence_list);
007cc8ac 1712 }
63560396
DV		 1713
1714 trace_i915_gem_object_change_domain(obj,
1715 obj->read_domains,
1716 old_write_domain);
1717 }
1718 }
1719}
8187a2b7 1720
5a5a0c64 1721uint32_t
8a1a49f9 1722i915_add_request(struct drm_device *dev,
f787a5f5 1723 struct drm_file *file,
8dc5d147 1724 struct drm_i915_gem_request *request,
8a1a49f9 1725 struct intel_ring_buffer *ring)
673a394b
EA		 1726{
1727 drm_i915_private_t *dev_priv = dev->dev_private;
f787a5f5 1728 struct drm_i915_file_private *file_priv = NULL;
673a394b
EA		 1729 uint32_t seqno;
1730 int was_empty;
673a394b 1731
f787a5f5
CW		 1732 if (file != NULL)
1733 file_priv = file->driver_priv;
b962442e 1734
8dc5d147
CW		 1735 if (request == NULL) {
1736 request = kzalloc(sizeof(*request), GFP_KERNEL);
1737 if (request == NULL)
1738 return 0;
1739 }
673a394b 1740
f787a5f5 1741 seqno = ring->add_request(dev, ring, 0);
a56ba56c 1742 ring->outstanding_lazy_request = false;
673a394b
EA		 1743
1744 request->seqno = seqno;
852835f3 1745 request->ring = ring;
673a394b 1746 request->emitted_jiffies = jiffies;
852835f3
ZN		 1747 was_empty = list_empty(&ring->request_list);
1748 list_add_tail(&request->list, &ring->request_list);
1749
f787a5f5 1750 if (file_priv) {
1c25595f 1751 spin_lock(&file_priv->mm.lock);
f787a5f5 1752 request->file_priv = file_priv;
b962442e 1753 list_add_tail(&request->client_list,
f787a5f5 1754 &file_priv->mm.request_list);
1c25595f 1755 spin_unlock(&file_priv->mm.lock);
b962442e 1756 }
673a394b 1757
f65d9421 1758 if (!dev_priv->mm.suspended) {
b3b079db
CW		 1759 mod_timer(&dev_priv->hangcheck_timer,
1760 jiffies + msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD));
f65d9421 1761 if (was_empty)
b3b079db
CW		 1762 queue_delayed_work(dev_priv->wq,
1763 &dev_priv->mm.retire_work, HZ);
f65d9421 1764 }
673a394b
EA		 1765 return seqno;
1766}
1767
1768/**
1769 * Command execution barrier
1770 *
1771 * Ensures that all commands in the ring are finished
1772 * before signalling the CPU
1773 */
8a1a49f9 1774static void
852835f3 1775i915_retire_commands(struct drm_device *dev, struct intel_ring_buffer *ring)
673a394b 1776{
673a394b 1777 uint32_t flush_domains = 0;
673a394b
EA		 1778
1779 /* The sampler always gets flushed on i965 (sigh) */
a6c45cf0 1780 if (INTEL_INFO(dev)->gen >= 4)
673a394b 1781 flush_domains |= I915_GEM_DOMAIN_SAMPLER;
852835f3
ZN		 1782
1783 ring->flush(dev, ring,
1784 I915_GEM_DOMAIN_COMMAND, flush_domains);
673a394b
EA		 1785}
1786
f787a5f5
CW		 1787static inline void
1788i915_gem_request_remove_from_client(struct drm_i915_gem_request *request)
673a394b 1789{
1c25595f
CW		 1790 struct drm_i915_file_private *file_priv = request->file_priv;
1791
1792 if (!file_priv)
1793 return;
1794
1795 spin_lock(&file_priv->mm.lock);
1796 list_del(&request->client_list);
1797 request->file_priv = NULL;
1798 spin_unlock(&file_priv->mm.lock);
673a394b
EA		 1799}
1800
dfaae392
CW		 1801static void i915_gem_reset_ring_lists(struct drm_i915_private *dev_priv,
1802 struct intel_ring_buffer *ring)
9375e446 1803{
dfaae392
CW		 1804 while (!list_empty(&ring->request_list)) {
1805 struct drm_i915_gem_request *request;
9375e446 1806
dfaae392
CW		 1807 request = list_first_entry(&ring->request_list,
1808 struct drm_i915_gem_request,
1809 list);
1810
1811 list_del(&request->list);
f787a5f5 1812 i915_gem_request_remove_from_client(request);
dfaae392
CW		 1813 kfree(request);
1814 }
1815
1816 while (!list_empty(&ring->active_list)) {
9375e446
CW		 1817 struct drm_i915_gem_object *obj_priv;
1818
dfaae392 1819 obj_priv = list_first_entry(&ring->active_list,
9375e446
CW		 1820 struct drm_i915_gem_object,
1821 list);
1822
1823 obj_priv->base.write_domain = 0;
dfaae392 1824 list_del_init(&obj_priv->gpu_write_list);
9375e446
CW		 1825 i915_gem_object_move_to_inactive(&obj_priv->base);
1826 }
1827}
1828
dfaae392 1829void i915_gem_reset_lists(struct drm_device *dev)
77f01230
CW		 1830{
1831 struct drm_i915_private *dev_priv = dev->dev_private;
1832 struct drm_i915_gem_object *obj_priv;
1833
dfaae392
CW		 1834 i915_gem_reset_ring_lists(dev_priv, &dev_priv->render_ring);
1835 if (HAS_BSD(dev))
1836 i915_gem_reset_ring_lists(dev_priv, &dev_priv->bsd_ring);
1837
1838 /* Remove anything from the flushing lists. The GPU cache is likely
1839 * to be lost on reset along with the data, so simply move the
1840 * lost bo to the inactive list.
1841 */
1842 while (!list_empty(&dev_priv->mm.flushing_list)) {
1843 obj_priv = list_first_entry(&dev_priv->mm.flushing_list,
1844 struct drm_i915_gem_object,
1845 list);
1846
1847 obj_priv->base.write_domain = 0;
1848 list_del_init(&obj_priv->gpu_write_list);
1849 i915_gem_object_move_to_inactive(&obj_priv->base);
1850 }
1851
1852 /* Move everything out of the GPU domains to ensure we do any
1853 * necessary invalidation upon reuse.
1854 */
77f01230
CW		 1855 list_for_each_entry(obj_priv,
1856 &dev_priv->mm.inactive_list,
1857 list)
1858 {
1859 obj_priv->base.read_domains &= ~I915_GEM_GPU_DOMAINS;
1860 }
1861}
1862
673a394b
EA		 1863/**
1864 * This function clears the request list as sequence numbers are passed.
1865 */
b09a1fec
CW		 1866static void
1867i915_gem_retire_requests_ring(struct drm_device *dev,
1868 struct intel_ring_buffer *ring)
673a394b
EA		 1869{
1870 drm_i915_private_t *dev_priv = dev->dev_private;
1871 uint32_t seqno;
1872
b84d5f0c
CW		 1873 if (!ring->status_page.page_addr ||
1874 list_empty(&ring->request_list))
6c0594a3
KW		 1875 return;
1876
23bc5982
CW		 1877 WARN_ON(i915_verify_lists(dev));
1878
f787a5f5 1879 seqno = ring->get_seqno(dev, ring);
852835f3 1880 while (!list_empty(&ring->request_list)) {
673a394b 1881 struct drm_i915_gem_request *request;
673a394b 1882
852835f3 1883 request = list_first_entry(&ring->request_list,
673a394b
EA		 1884 struct drm_i915_gem_request,
1885 list);
673a394b 1886
dfaae392 1887 if (!i915_seqno_passed(seqno, request->seqno))
b84d5f0c
CW		 1888 break;
1889
1890 trace_i915_gem_request_retire(dev, request->seqno);
1891
1892 list_del(&request->list);
f787a5f5 1893 i915_gem_request_remove_from_client(request);
b84d5f0c
CW		 1894 kfree(request);
1895 }
1896
1897 /* Move any buffers on the active list that are no longer referenced
1898 * by the ringbuffer to the flushing/inactive lists as appropriate.
1899 */
1900 while (!list_empty(&ring->active_list)) {
1901 struct drm_gem_object *obj;
1902 struct drm_i915_gem_object *obj_priv;
1903
1904 obj_priv = list_first_entry(&ring->active_list,
1905 struct drm_i915_gem_object,
1906 list);
673a394b 1907
dfaae392 1908 if (!i915_seqno_passed(seqno, obj_priv->last_rendering_seqno))
673a394b 1909 break;
b84d5f0c
CW		 1910
1911 obj = &obj_priv->base;
b84d5f0c
CW		 1912 if (obj->write_domain != 0)
1913 i915_gem_object_move_to_flushing(obj);
1914 else
1915 i915_gem_object_move_to_inactive(obj);
673a394b 1916 }
9d34e5db
CW		 1917
1918 if (unlikely (dev_priv->trace_irq_seqno &&
1919 i915_seqno_passed(dev_priv->trace_irq_seqno, seqno))) {
8187a2b7 1920 ring->user_irq_put(dev, ring);
9d34e5db
CW		 1921 dev_priv->trace_irq_seqno = 0;
1922 }
23bc5982
CW		 1923
1924 WARN_ON(i915_verify_lists(dev));
673a394b
EA		 1925}
1926
b09a1fec
CW		 1927void
1928i915_gem_retire_requests(struct drm_device *dev)
1929{
1930 drm_i915_private_t *dev_priv = dev->dev_private;
1931
be72615b
CW		 1932 if (!list_empty(&dev_priv->mm.deferred_free_list)) {
1933 struct drm_i915_gem_object *obj_priv, *tmp;
1934
1935 /* We must be careful that during unbind() we do not
1936 * accidentally infinitely recurse into retire requests.
1937 * Currently:
1938 * retire -> free -> unbind -> wait -> retire_ring
1939 */
1940 list_for_each_entry_safe(obj_priv, tmp,
1941 &dev_priv->mm.deferred_free_list,
1942 list)
1943 i915_gem_free_object_tail(&obj_priv->base);
1944 }
1945
b09a1fec
CW		 1946 i915_gem_retire_requests_ring(dev, &dev_priv->render_ring);
1947 if (HAS_BSD(dev))
1948 i915_gem_retire_requests_ring(dev, &dev_priv->bsd_ring);
1949}
1950
75ef9da2 1951static void
673a394b
EA		 1952i915_gem_retire_work_handler(struct work_struct *work)
1953{
1954 drm_i915_private_t *dev_priv;
1955 struct drm_device *dev;
1956
1957 dev_priv = container_of(work, drm_i915_private_t,
1958 mm.retire_work.work);
1959 dev = dev_priv->dev;
1960
891b48cf
CW		 1961 /* Come back later if the device is busy... */
1962 if (!mutex_trylock(&dev->struct_mutex)) {
1963 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ);
1964 return;
1965 }
1966
b09a1fec 1967 i915_gem_retire_requests(dev);
d1b851fc 1968
6dbe2772 1969 if (!dev_priv->mm.suspended &&
d1b851fc
ZN		 1970 (!list_empty(&dev_priv->render_ring.request_list) ||
1971 (HAS_BSD(dev) &&
1972 !list_empty(&dev_priv->bsd_ring.request_list))))
9c9fe1f8 1973 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ);
673a394b
EA		 1974 mutex_unlock(&dev->struct_mutex);
1975}
1976
5a5a0c64 1977int
852835f3 1978i915_do_wait_request(struct drm_device *dev, uint32_t seqno,
8a1a49f9 1979 bool interruptible, struct intel_ring_buffer *ring)
673a394b
EA		 1980{
1981 drm_i915_private_t *dev_priv = dev->dev_private;
802c7eb6 1982 u32 ier;
673a394b
EA		 1983 int ret = 0;
1984
1985 BUG_ON(seqno == 0);
1986
30dbf0c0
CW		 1987 if (atomic_read(&dev_priv->mm.wedged))
1988 return -EAGAIN;
1989
a56ba56c 1990 if (ring->outstanding_lazy_request) {
8dc5d147 1991 seqno = i915_add_request(dev, NULL, NULL, ring);
e35a41de
DV		 1992 if (seqno == 0)
1993 return -ENOMEM;
1994 }
a56ba56c 1995 BUG_ON(seqno == dev_priv->next_seqno);
e35a41de 1996
f787a5f5 1997 if (!i915_seqno_passed(ring->get_seqno(dev, ring), seqno)) {
bad720ff 1998 if (HAS_PCH_SPLIT(dev))
036a4a7d
ZW		 1999 ier = I915_READ(DEIER) | I915_READ(GTIER);
2000 else
2001 ier = I915_READ(IER);
802c7eb6
JB		 2002 if (!ier) {
2003 DRM_ERROR("something (likely vbetool) disabled "
2004 "interrupts, re-enabling\n");
2005 i915_driver_irq_preinstall(dev);
2006 i915_driver_irq_postinstall(dev);
2007 }
2008
1c5d22f7
CW		 2009 trace_i915_gem_request_wait_begin(dev, seqno);
2010
852835f3 2011 ring->waiting_gem_seqno = seqno;
8187a2b7 2012 ring->user_irq_get(dev, ring);
48764bf4 2013 if (interruptible)
852835f3
ZN		 2014 ret = wait_event_interruptible(ring->irq_queue,
2015 i915_seqno_passed(
f787a5f5 2016 ring->get_seqno(dev, ring), seqno)
852835f3 2017 || atomic_read(&dev_priv->mm.wedged));
48764bf4 2018 else
852835f3
ZN		 2019 wait_event(ring->irq_queue,
2020 i915_seqno_passed(
f787a5f5 2021 ring->get_seqno(dev, ring), seqno)
852835f3 2022 || atomic_read(&dev_priv->mm.wedged));
48764bf4 2023
8187a2b7 2024 ring->user_irq_put(dev, ring);
852835f3 2025 ring->waiting_gem_seqno = 0;
1c5d22f7
CW		 2026
2027 trace_i915_gem_request_wait_end(dev, seqno);
673a394b 2028 }
ba1234d1 2029 if (atomic_read(&dev_priv->mm.wedged))
30dbf0c0 2030 ret = -EAGAIN;
673a394b
EA		 2031
2032 if (ret && ret != -ERESTARTSYS)
8bff917c 2033 DRM_ERROR("%s returns %d (awaiting %d at %d, next %d)\n",
f787a5f5 2034 __func__, ret, seqno, ring->get_seqno(dev, ring),
8bff917c 2035 dev_priv->next_seqno);
673a394b
EA		 2036
2037 /* Directly dispatch request retiring. While we have the work queue
2038 * to handle this, the waiter on a request often wants an associated
2039 * buffer to have made it to the inactive list, and we would need
2040 * a separate wait queue to handle that.
2041 */
2042 if (ret == 0)
b09a1fec 2043 i915_gem_retire_requests_ring(dev, ring);
673a394b
EA		 2044
2045 return ret;
2046}
2047
48764bf4
DV		 2048/**
2049 * Waits for a sequence number to be signaled, and cleans up the
2050 * request and object lists appropriately for that event.
2051 */
2052static int
852835f3 2053i915_wait_request(struct drm_device *dev, uint32_t seqno,
a56ba56c 2054 struct intel_ring_buffer *ring)
48764bf4 2055{
852835f3 2056 return i915_do_wait_request(dev, seqno, 1, ring);
48764bf4
DV		 2057}
2058
20f0cd55 2059static void
9220434a 2060i915_gem_flush_ring(struct drm_device *dev,
c78ec30b 2061 struct drm_file *file_priv,
9220434a
CW		 2062 struct intel_ring_buffer *ring,
2063 uint32_t invalidate_domains,
2064 uint32_t flush_domains)
2065{
2066 ring->flush(dev, ring, invalidate_domains, flush_domains);
2067 i915_gem_process_flushing_list(dev, flush_domains, ring);
2068}
2069
8187a2b7
ZN		 2070static void
2071i915_gem_flush(struct drm_device *dev,
c78ec30b 2072 struct drm_file *file_priv,
8187a2b7 2073 uint32_t invalidate_domains,
9220434a
CW		 2074 uint32_t flush_domains,
2075 uint32_t flush_rings)
8187a2b7
ZN		 2076{
2077 drm_i915_private_t *dev_priv = dev->dev_private;
8bff917c 2078
8187a2b7
ZN		 2079 if (flush_domains & I915_GEM_DOMAIN_CPU)
2080 drm_agp_chipset_flush(dev);
8bff917c 2081
9220434a
CW		 2082 if ((flush_domains | invalidate_domains) & I915_GEM_GPU_DOMAINS) {
2083 if (flush_rings & RING_RENDER)
c78ec30b 2084 i915_gem_flush_ring(dev, file_priv,
9220434a
CW		 2085 &dev_priv->render_ring,
2086 invalidate_domains, flush_domains);
2087 if (flush_rings & RING_BSD)
c78ec30b 2088 i915_gem_flush_ring(dev, file_priv,
9220434a
CW		 2089 &dev_priv->bsd_ring,
2090 invalidate_domains, flush_domains);
2091 }
8187a2b7
ZN		 2092}
2093
673a394b
EA		 2094/**
2095 * Ensures that all rendering to the object has completed and the object is
2096 * safe to unbind from the GTT or access from the CPU.
2097 */
2098static int
2cf34d7b
CW		 2099i915_gem_object_wait_rendering(struct drm_gem_object *obj,
2100 bool interruptible)
673a394b
EA		 2101{
2102 struct drm_device *dev = obj->dev;
23010e43 2103 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
673a394b
EA		 2104 int ret;
2105
e47c68e9
EA		 2106 /* This function only exists to support waiting for existing rendering,
2107 * not for emitting required flushes.
673a394b 2108 */
e47c68e9 2109 BUG_ON((obj->write_domain & I915_GEM_GPU_DOMAINS) != 0);
673a394b
EA		 2110
2111 /* If there is rendering queued on the buffer being evicted, wait for
2112 * it.
2113 */
2114 if (obj_priv->active) {
2cf34d7b
CW		 2115 ret = i915_do_wait_request(dev,
2116 obj_priv->last_rendering_seqno,
2117 interruptible,
2118 obj_priv->ring);
2119 if (ret)
673a394b
EA		 2120 return ret;
2121 }
2122
2123 return 0;
2124}
2125
2126/**
2127 * Unbinds an object from the GTT aperture.
2128 */
0f973f27 2129int
673a394b
EA		 2130i915_gem_object_unbind(struct drm_gem_object *obj)
2131{
2132 struct drm_device *dev = obj->dev;
73aa808f 2133 struct drm_i915_private *dev_priv = dev->dev_private;
23010e43 2134 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
673a394b
EA		 2135 int ret = 0;
2136
673a394b
EA		 2137 if (obj_priv->gtt_space == NULL)
2138 return 0;
2139
2140 if (obj_priv->pin_count != 0) {
2141 DRM_ERROR("Attempting to unbind pinned buffer\n");
2142 return -EINVAL;
2143 }
2144
5323fd04
EA		 2145 /* blow away mappings if mapped through GTT */
2146 i915_gem_release_mmap(obj);
2147
673a394b
EA		 2148 /* Move the object to the CPU domain to ensure that
2149 * any possible CPU writes while it's not in the GTT
2150 * are flushed when we go to remap it. This will
2151 * also ensure that all pending GPU writes are finished
2152 * before we unbind.
2153 */
e47c68e9 2154 ret = i915_gem_object_set_to_cpu_domain(obj, 1);
8dc1775d 2155 if (ret == -ERESTARTSYS)
673a394b 2156 return ret;
8dc1775d
CW		 2157 /* Continue on if we fail due to EIO, the GPU is hung so we
2158 * should be safe and we need to cleanup or else we might
2159 * cause memory corruption through use-after-free.
2160 */
673a394b 2161
96b47b65
DV		 2162 /* release the fence reg _after_ flushing */
2163 if (obj_priv->fence_reg != I915_FENCE_REG_NONE)
2164 i915_gem_clear_fence_reg(obj);
2165
73aa808f
CW		 2166 drm_unbind_agp(obj_priv->agp_mem);
2167 drm_free_agp(obj_priv->agp_mem, obj->size / PAGE_SIZE);
673a394b 2168
856fa198 2169 i915_gem_object_put_pages(obj);
a32808c0 2170 BUG_ON(obj_priv->pages_refcount);
673a394b 2171
73aa808f 2172 i915_gem_info_remove_gtt(dev_priv, obj->size);
f13d3f73 2173 list_del_init(&obj_priv->list);
673a394b 2174
73aa808f
CW		 2175 drm_mm_put_block(obj_priv->gtt_space);
2176 obj_priv->gtt_space = NULL;
2177
963b4836
CW		 2178 if (i915_gem_object_is_purgeable(obj_priv))
2179 i915_gem_object_truncate(obj);
2180
1c5d22f7
CW		 2181 trace_i915_gem_object_unbind(obj);
2182
8dc1775d 2183 return ret;
673a394b
EA		 2184}
2185
a56ba56c
CW		 2186static int i915_ring_idle(struct drm_device *dev,
2187 struct intel_ring_buffer *ring)
2188{
2189 i915_gem_flush_ring(dev, NULL, ring,
2190 I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
2191 return i915_wait_request(dev,
2192 i915_gem_next_request_seqno(dev, ring),
2193 ring);
2194}
2195
b47eb4a2 2196int
4df2faf4
DV		 2197i915_gpu_idle(struct drm_device *dev)
2198{
2199 drm_i915_private_t *dev_priv = dev->dev_private;
2200 bool lists_empty;
852835f3 2201 int ret;
4df2faf4 2202
d1b851fc
ZN		 2203 lists_empty = (list_empty(&dev_priv->mm.flushing_list) &&
2204 list_empty(&dev_priv->render_ring.active_list) &&
2205 (!HAS_BSD(dev) ||
2206 list_empty(&dev_priv->bsd_ring.active_list)));
4df2faf4
DV		 2207 if (lists_empty)
2208 return 0;
2209
2210 /* Flush everything onto the inactive list. */
a56ba56c 2211 ret = i915_ring_idle(dev, &dev_priv->render_ring);
8a1a49f9
DV		 2212 if (ret)
2213 return ret;
d1b851fc
ZN		 2214
2215 if (HAS_BSD(dev)) {
a56ba56c 2216 ret = i915_ring_idle(dev, &dev_priv->bsd_ring);
d1b851fc
ZN		 2217 if (ret)
2218 return ret;
2219 }
2220
8a1a49f9 2221 return 0;
4df2faf4
DV		 2222}
2223
5cdf5881 2224static int
4bdadb97
CW		 2225i915_gem_object_get_pages(struct drm_gem_object *obj,
2226 gfp_t gfpmask)
673a394b 2227{
23010e43 2228 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
673a394b
EA		 2229 int page_count, i;
2230 struct address_space *mapping;
2231 struct inode *inode;
2232 struct page *page;
673a394b 2233
778c3544
DV		 2234 BUG_ON(obj_priv->pages_refcount
2235 == DRM_I915_GEM_OBJECT_MAX_PAGES_REFCOUNT);
2236
856fa198 2237 if (obj_priv->pages_refcount++ != 0)
673a394b
EA		 2238 return 0;
2239
2240 /* Get the list of pages out of our struct file. They'll be pinned
2241 * at this point until we release them.
2242 */
2243 page_count = obj->size / PAGE_SIZE;
856fa198 2244 BUG_ON(obj_priv->pages != NULL);
8e7d2b2c 2245 obj_priv->pages = drm_calloc_large(page_count, sizeof(struct page *));
856fa198 2246 if (obj_priv->pages == NULL) {
856fa198 2247 obj_priv->pages_refcount--;
673a394b
EA		 2248 return -ENOMEM;
2249 }
2250
2251 inode = obj->filp->f_path.dentry->d_inode;
2252 mapping = inode->i_mapping;
2253 for (i = 0; i < page_count; i++) {
4bdadb97 2254 page = read_cache_page_gfp(mapping, i,
985b823b 2255 GFP_HIGHUSER |
4bdadb97 2256 __GFP_COLD |
cd9f040d 2257 __GFP_RECLAIMABLE |
4bdadb97 2258 gfpmask);
1f2b1013
CW		 2259 if (IS_ERR(page))
2260 goto err_pages;
2261
856fa198 2262 obj_priv->pages[i] = page;
673a394b 2263 }
280b713b
EA		 2264
2265 if (obj_priv->tiling_mode != I915_TILING_NONE)
2266 i915_gem_object_do_bit_17_swizzle(obj);
2267
673a394b 2268 return 0;
1f2b1013
CW		 2269
2270err_pages:
2271 while (i--)
2272 page_cache_release(obj_priv->pages[i]);
2273
2274 drm_free_large(obj_priv->pages);
2275 obj_priv->pages = NULL;
2276 obj_priv->pages_refcount--;
2277 return PTR_ERR(page);
673a394b
EA		 2278}
2279
4e901fdc
EA		 2280static void sandybridge_write_fence_reg(struct drm_i915_fence_reg *reg)
2281{
2282 struct drm_gem_object *obj = reg->obj;
2283 struct drm_device *dev = obj->dev;
2284 drm_i915_private_t *dev_priv = dev->dev_private;
23010e43 2285 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
4e901fdc
EA		 2286 int regnum = obj_priv->fence_reg;
2287 uint64_t val;
2288
2289 val = (uint64_t)((obj_priv->gtt_offset + obj->size - 4096) &
2290 0xfffff000) << 32;
2291 val |= obj_priv->gtt_offset & 0xfffff000;
2292 val |= (uint64_t)((obj_priv->stride / 128) - 1) <<
2293 SANDYBRIDGE_FENCE_PITCH_SHIFT;
2294
2295 if (obj_priv->tiling_mode == I915_TILING_Y)
2296 val |= 1 << I965_FENCE_TILING_Y_SHIFT;
2297 val |= I965_FENCE_REG_VALID;
2298
2299 I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + (regnum * 8), val);
2300}
2301
de151cf6
JB		 2302static void i965_write_fence_reg(struct drm_i915_fence_reg *reg)
2303{
2304 struct drm_gem_object *obj = reg->obj;
2305 struct drm_device *dev = obj->dev;
2306 drm_i915_private_t *dev_priv = dev->dev_private;
23010e43 2307 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
de151cf6
JB		 2308 int regnum = obj_priv->fence_reg;
2309 uint64_t val;
2310
2311 val = (uint64_t)((obj_priv->gtt_offset + obj->size - 4096) &
2312 0xfffff000) << 32;
2313 val |= obj_priv->gtt_offset & 0xfffff000;
2314 val |= ((obj_priv->stride / 128) - 1) << I965_FENCE_PITCH_SHIFT;
2315 if (obj_priv->tiling_mode == I915_TILING_Y)
2316 val |= 1 << I965_FENCE_TILING_Y_SHIFT;
2317 val |= I965_FENCE_REG_VALID;
2318
2319 I915_WRITE64(FENCE_REG_965_0 + (regnum * 8), val);
2320}
2321
2322static void i915_write_fence_reg(struct drm_i915_fence_reg *reg)
2323{
2324 struct drm_gem_object *obj = reg->obj;
2325 struct drm_device *dev = obj->dev;
2326 drm_i915_private_t *dev_priv = dev->dev_private;
23010e43 2327 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
de151cf6 2328 int regnum = obj_priv->fence_reg;
0f973f27 2329 int tile_width;
dc529a4f 2330 uint32_t fence_reg, val;
de151cf6
JB		 2331 uint32_t pitch_val;
2332
2333 if ((obj_priv->gtt_offset & ~I915_FENCE_START_MASK) ||
2334 (obj_priv->gtt_offset & (obj->size - 1))) {
f06da264 2335 WARN(1, "%s: object 0x%08x not 1M or size (0x%zx) aligned\n",
0f973f27 2336 __func__, obj_priv->gtt_offset, obj->size);
de151cf6
JB		 2337 return;
2338 }
2339
0f973f27
JB		 2340 if (obj_priv->tiling_mode == I915_TILING_Y &&
2341 HAS_128_BYTE_Y_TILING(dev))
2342 tile_width = 128;
de151cf6 2343 else
0f973f27
JB		 2344 tile_width = 512;
2345
2346 /* Note: pitch better be a power of two tile widths */
2347 pitch_val = obj_priv->stride / tile_width;
2348 pitch_val = ffs(pitch_val) - 1;
de151cf6 2349
c36a2a6d
DV		 2350 if (obj_priv->tiling_mode == I915_TILING_Y &&
2351 HAS_128_BYTE_Y_TILING(dev))
2352 WARN_ON(pitch_val > I830_FENCE_MAX_PITCH_VAL);
2353 else
2354 WARN_ON(pitch_val > I915_FENCE_MAX_PITCH_VAL);
2355
de151cf6
JB		 2356 val = obj_priv->gtt_offset;
2357 if (obj_priv->tiling_mode == I915_TILING_Y)
2358 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
2359 val |= I915_FENCE_SIZE_BITS(obj->size);
2360 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
2361 val |= I830_FENCE_REG_VALID;
2362
dc529a4f
EA		 2363 if (regnum < 8)
2364 fence_reg = FENCE_REG_830_0 + (regnum * 4);
2365 else
2366 fence_reg = FENCE_REG_945_8 + ((regnum - 8) * 4);
2367 I915_WRITE(fence_reg, val);
de151cf6
JB		 2368}
2369
2370static void i830_write_fence_reg(struct drm_i915_fence_reg *reg)
2371{
2372 struct drm_gem_object *obj = reg->obj;
2373 struct drm_device *dev = obj->dev;
2374 drm_i915_private_t *dev_priv = dev->dev_private;
23010e43 2375 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
de151cf6
JB		 2376 int regnum = obj_priv->fence_reg;
2377 uint32_t val;
2378 uint32_t pitch_val;
8d7773a3 2379 uint32_t fence_size_bits;
de151cf6 2380
8d7773a3 2381 if ((obj_priv->gtt_offset & ~I830_FENCE_START_MASK) ||
de151cf6 2382 (obj_priv->gtt_offset & (obj->size - 1))) {
8d7773a3 2383 WARN(1, "%s: object 0x%08x not 512K or size aligned\n",
0f973f27 2384 __func__, obj_priv->gtt_offset);
de151cf6
JB		 2385 return;
2386 }
2387
e76a16de
EA		 2388 pitch_val = obj_priv->stride / 128;
2389 pitch_val = ffs(pitch_val) - 1;
2390 WARN_ON(pitch_val > I830_FENCE_MAX_PITCH_VAL);
2391
de151cf6
JB		 2392 val = obj_priv->gtt_offset;
2393 if (obj_priv->tiling_mode == I915_TILING_Y)
2394 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
8d7773a3
DV		 2395 fence_size_bits = I830_FENCE_SIZE_BITS(obj->size);
2396 WARN_ON(fence_size_bits & ~0x00000f00);
2397 val |= fence_size_bits;
de151cf6
JB		 2398 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
2399 val |= I830_FENCE_REG_VALID;
2400
2401 I915_WRITE(FENCE_REG_830_0 + (regnum * 4), val);
de151cf6
JB		 2402}
2403
2cf34d7b
CW		 2404static int i915_find_fence_reg(struct drm_device *dev,
2405 bool interruptible)
ae3db24a
DV		 2406{
2407 struct drm_i915_fence_reg *reg = NULL;
2408 struct drm_i915_gem_object *obj_priv = NULL;
2409 struct drm_i915_private *dev_priv = dev->dev_private;
2410 struct drm_gem_object *obj = NULL;
2411 int i, avail, ret;
2412
2413 /* First try to find a free reg */
2414 avail = 0;
2415 for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) {
2416 reg = &dev_priv->fence_regs[i];
2417 if (!reg->obj)
2418 return i;
2419
23010e43 2420 obj_priv = to_intel_bo(reg->obj);
ae3db24a
DV		 2421 if (!obj_priv->pin_count)
2422 avail++;
2423 }
2424
2425 if (avail == 0)
2426 return -ENOSPC;
2427
2428 /* None available, try to steal one or wait for a user to finish */
2429 i = I915_FENCE_REG_NONE;
007cc8ac
DV		 2430 list_for_each_entry(reg, &dev_priv->mm.fence_list,
2431 lru_list) {
2432 obj = reg->obj;
2433 obj_priv = to_intel_bo(obj);
ae3db24a
DV		 2434
2435 if (obj_priv->pin_count)
2436 continue;
2437
2438 /* found one! */
2439 i = obj_priv->fence_reg;
2440 break;
2441 }
2442
2443 BUG_ON(i == I915_FENCE_REG_NONE);
2444
2445 /* We only have a reference on obj from the active list. put_fence_reg
2446 * might drop that one, causing a use-after-free in it. So hold a
2447 * private reference to obj like the other callers of put_fence_reg
2448 * (set_tiling ioctl) do. */
2449 drm_gem_object_reference(obj);
2cf34d7b 2450 ret = i915_gem_object_put_fence_reg(obj, interruptible);
ae3db24a
DV		 2451 drm_gem_object_unreference(obj);
2452 if (ret != 0)
2453 return ret;
2454
2455 return i;
2456}
2457
de151cf6
JB		 2458/**
2459 * i915_gem_object_get_fence_reg - set up a fence reg for an object
2460 * @obj: object to map through a fence reg
2461 *
2462 * When mapping objects through the GTT, userspace wants to be able to write
2463 * to them without having to worry about swizzling if the object is tiled.
2464 *
2465 * This function walks the fence regs looking for a free one for @obj,
2466 * stealing one if it can't find any.
2467 *
2468 * It then sets up the reg based on the object's properties: address, pitch
2469 * and tiling format.
2470 */
8c4b8c3f 2471int
2cf34d7b
CW		 2472i915_gem_object_get_fence_reg(struct drm_gem_object *obj,
2473 bool interruptible)
de151cf6
JB		 2474{
2475 struct drm_device *dev = obj->dev;
79e53945 2476 struct drm_i915_private *dev_priv = dev->dev_private;
23010e43 2477 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
de151cf6 2478 struct drm_i915_fence_reg *reg = NULL;
ae3db24a 2479 int ret;
de151cf6 2480
a09ba7fa
EA		 2481 /* Just update our place in the LRU if our fence is getting used. */
2482 if (obj_priv->fence_reg != I915_FENCE_REG_NONE) {
007cc8ac
DV		 2483 reg = &dev_priv->fence_regs[obj_priv->fence_reg];
2484 list_move_tail(&reg->lru_list, &dev_priv->mm.fence_list);
a09ba7fa
EA		 2485 return 0;
2486 }
2487
de151cf6
JB		 2488 switch (obj_priv->tiling_mode) {
2489 case I915_TILING_NONE:
2490 WARN(1, "allocating a fence for non-tiled object?\n");
2491 break;
2492 case I915_TILING_X:
0f973f27
JB		 2493 if (!obj_priv->stride)
2494 return -EINVAL;
2495 WARN((obj_priv->stride & (512 - 1)),
2496 "object 0x%08x is X tiled but has non-512B pitch\n",
2497 obj_priv->gtt_offset);
de151cf6
JB		 2498 break;
2499 case I915_TILING_Y:
0f973f27
JB		 2500 if (!obj_priv->stride)
2501 return -EINVAL;
2502 WARN((obj_priv->stride & (128 - 1)),
2503 "object 0x%08x is Y tiled but has non-128B pitch\n",
2504 obj_priv->gtt_offset);
de151cf6
JB		 2505 break;
2506 }
2507
2cf34d7b 2508 ret = i915_find_fence_reg(dev, interruptible);
ae3db24a
DV		 2509 if (ret < 0)
2510 return ret;
de151cf6 2511
ae3db24a
DV		 2512 obj_priv->fence_reg = ret;
2513 reg = &dev_priv->fence_regs[obj_priv->fence_reg];
007cc8ac 2514 list_add_tail(&reg->lru_list, &dev_priv->mm.fence_list);
a09ba7fa 2515
de151cf6
JB		 2516 reg->obj = obj;
2517
e259befd
CW		 2518 switch (INTEL_INFO(dev)->gen) {
2519 case 6:
4e901fdc 2520 sandybridge_write_fence_reg(reg);
e259befd
CW		 2521 break;
2522 case 5:
2523 case 4:
de151cf6 2524 i965_write_fence_reg(reg);
e259befd
CW		 2525 break;
2526 case 3:
de151cf6 2527 i915_write_fence_reg(reg);
e259befd
CW		 2528 break;
2529 case 2:
de151cf6 2530 i830_write_fence_reg(reg);
e259befd
CW		 2531 break;
2532 }
d9ddcb96 2533
ae3db24a
DV		 2534 trace_i915_gem_object_get_fence(obj, obj_priv->fence_reg,
2535 obj_priv->tiling_mode);
1c5d22f7 2536
d9ddcb96 2537 return 0;
de151cf6
JB		 2538}
2539
2540/**
2541 * i915_gem_clear_fence_reg - clear out fence register info
2542 * @obj: object to clear
2543 *
2544 * Zeroes out the fence register itself and clears out the associated
2545 * data structures in dev_priv and obj_priv.
2546 */
2547static void
2548i915_gem_clear_fence_reg(struct drm_gem_object *obj)
2549{
2550 struct drm_device *dev = obj->dev;
79e53945 2551 drm_i915_private_t *dev_priv = dev->dev_private;
23010e43 2552 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
007cc8ac
DV		 2553 struct drm_i915_fence_reg *reg =
2554 &dev_priv->fence_regs[obj_priv->fence_reg];
e259befd 2555 uint32_t fence_reg;
de151cf6 2556
e259befd
CW		 2557 switch (INTEL_INFO(dev)->gen) {
2558 case 6:
4e901fdc
EA		 2559 I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 +
2560 (obj_priv->fence_reg * 8), 0);
e259befd
CW		 2561 break;
2562 case 5:
2563 case 4:
de151cf6 2564 I915_WRITE64(FENCE_REG_965_0 + (obj_priv->fence_reg * 8), 0);
e259befd
CW		 2565 break;
2566 case 3:
9b74f734 2567 if (obj_priv->fence_reg >= 8)
e259befd 2568 fence_reg = FENCE_REG_945_8 + (obj_priv->fence_reg - 8) * 4;
dc529a4f 2569 else
e259befd
CW		 2570 case 2:
2571 fence_reg = FENCE_REG_830_0 + obj_priv->fence_reg * 4;
dc529a4f
EA		 2572
2573 I915_WRITE(fence_reg, 0);
e259befd 2574 break;
dc529a4f 2575 }
de151cf6 2576
007cc8ac 2577 reg->obj = NULL;
de151cf6 2578 obj_priv->fence_reg = I915_FENCE_REG_NONE;
007cc8ac 2579 list_del_init(&reg->lru_list);
de151cf6
JB		 2580}
2581
52dc7d32
CW		 2582/**
2583 * i915_gem_object_put_fence_reg - waits on outstanding fenced access
2584 * to the buffer to finish, and then resets the fence register.
2585 * @obj: tiled object holding a fence register.
2cf34d7b 2586 * @bool: whether the wait upon the fence is interruptible
52dc7d32
CW		 2587 *
2588 * Zeroes out the fence register itself and clears out the associated
2589 * data structures in dev_priv and obj_priv.
2590 */
2591int
2cf34d7b
CW		 2592i915_gem_object_put_fence_reg(struct drm_gem_object *obj,
2593 bool interruptible)
52dc7d32
CW		 2594{
2595 struct drm_device *dev = obj->dev;
53640e1d 2596 struct drm_i915_private *dev_priv = dev->dev_private;
23010e43 2597 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
53640e1d 2598 struct drm_i915_fence_reg *reg;
52dc7d32
CW		 2599
2600 if (obj_priv->fence_reg == I915_FENCE_REG_NONE)
2601 return 0;
2602
10ae9bd2
DV		 2603 /* If we've changed tiling, GTT-mappings of the object
2604 * need to re-fault to ensure that the correct fence register
2605 * setup is in place.
2606 */
2607 i915_gem_release_mmap(obj);
2608
52dc7d32
CW		 2609 /* On the i915, GPU access to tiled buffers is via a fence,
2610 * therefore we must wait for any outstanding access to complete
2611 * before clearing the fence.
2612 */
53640e1d
CW		 2613 reg = &dev_priv->fence_regs[obj_priv->fence_reg];
2614 if (reg->gpu) {
52dc7d32
CW		 2615 int ret;
2616
2cf34d7b 2617 ret = i915_gem_object_flush_gpu_write_domain(obj, true);
0bc23aad
CW		 2618 if (ret)
2619 return ret;
2620
2cf34d7b 2621 ret = i915_gem_object_wait_rendering(obj, interruptible);
0bc23aad 2622 if (ret)
52dc7d32 2623 return ret;
53640e1d
CW		 2624
2625 reg->gpu = false;
52dc7d32
CW		 2626 }
2627
4a726612 2628 i915_gem_object_flush_gtt_write_domain(obj);
0bc23aad 2629 i915_gem_clear_fence_reg(obj);
52dc7d32
CW		 2630
2631 return 0;
2632}
2633
673a394b
EA		 2634/**
2635 * Finds free space in the GTT aperture and binds the object there.
2636 */
2637static int
2638i915_gem_object_bind_to_gtt(struct drm_gem_object *obj, unsigned alignment)
2639{
2640 struct drm_device *dev = obj->dev;
2641 drm_i915_private_t *dev_priv = dev->dev_private;
23010e43 2642 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
673a394b 2643 struct drm_mm_node *free_space;
4bdadb97 2644 gfp_t gfpmask = __GFP_NORETRY | __GFP_NOWARN;
07f73f69 2645 int ret;
673a394b 2646
bb6baf76 2647 if (obj_priv->madv != I915_MADV_WILLNEED) {
3ef94daa
CW		 2648 DRM_ERROR("Attempting to bind a purgeable object\n");
2649 return -EINVAL;
2650 }
2651
673a394b 2652 if (alignment == 0)
0f973f27 2653 alignment = i915_gem_get_gtt_alignment(obj);
8d7773a3 2654 if (alignment & (i915_gem_get_gtt_alignment(obj) - 1)) {
673a394b
EA		 2655 DRM_ERROR("Invalid object alignment requested %u\n", alignment);
2656 return -EINVAL;
2657 }
2658
654fc607
CW		 2659 /* If the object is bigger than the entire aperture, reject it early
2660 * before evicting everything in a vain attempt to find space.
2661 */
73aa808f 2662 if (obj->size > dev_priv->mm.gtt_total) {
654fc607
CW		 2663 DRM_ERROR("Attempting to bind an object larger than the aperture\n");
2664 return -E2BIG;
2665 }
2666
673a394b
EA		 2667 search_free:
2668 free_space = drm_mm_search_free(&dev_priv->mm.gtt_space,
2669 obj->size, alignment, 0);
2670 if (free_space != NULL) {
2671 obj_priv->gtt_space = drm_mm_get_block(free_space, obj->size,
2672 alignment);
db3307a9 2673 if (obj_priv->gtt_space != NULL)
673a394b 2674 obj_priv->gtt_offset = obj_priv->gtt_space->start;
673a394b
EA		 2675 }
2676 if (obj_priv->gtt_space == NULL) {
2677 /* If the gtt is empty and we're still having trouble
2678 * fitting our object in, we're out of memory.
2679 */
0108a3ed 2680 ret = i915_gem_evict_something(dev, obj->size, alignment);
9731129c 2681 if (ret)
673a394b 2682 return ret;
9731129c 2683
673a394b
EA		 2684 goto search_free;
2685 }
2686
4bdadb97 2687 ret = i915_gem_object_get_pages(obj, gfpmask);
673a394b
EA		 2688 if (ret) {
2689 drm_mm_put_block(obj_priv->gtt_space);
2690 obj_priv->gtt_space = NULL;
07f73f69
CW		 2691
2692 if (ret == -ENOMEM) {
2693 /* first try to clear up some space from the GTT */
0108a3ed
DV		 2694 ret = i915_gem_evict_something(dev, obj->size,
2695 alignment);
07f73f69 2696 if (ret) {
07f73f69 2697 /* now try to shrink everyone else */
4bdadb97
CW		 2698 if (gfpmask) {
2699 gfpmask = 0;
2700 goto search_free;
07f73f69
CW		 2701 }
2702
2703 return ret;
2704 }
2705
2706 goto search_free;
2707 }
2708
673a394b
EA		 2709 return ret;
2710 }
2711
673a394b
EA		 2712 /* Create an AGP memory structure pointing at our pages, and bind it
2713 * into the GTT.
2714 */
2715 obj_priv->agp_mem = drm_agp_bind_pages(dev,
856fa198 2716 obj_priv->pages,
07f73f69 2717 obj->size >> PAGE_SHIFT,
ba1eb1d8
KP		 2718 obj_priv->gtt_offset,
2719 obj_priv->agp_type);
673a394b 2720 if (obj_priv->agp_mem == NULL) {
856fa198 2721 i915_gem_object_put_pages(obj);
673a394b
EA		 2722 drm_mm_put_block(obj_priv->gtt_space);
2723 obj_priv->gtt_space = NULL;
07f73f69 2724
0108a3ed 2725 ret = i915_gem_evict_something(dev, obj->size, alignment);
9731129c 2726 if (ret)
07f73f69 2727 return ret;
07f73f69
CW		 2728
2729 goto search_free;
673a394b 2730 }
673a394b 2731
bf1a1092
CW		 2732 /* keep track of bounds object by adding it to the inactive list */
2733 list_add_tail(&obj_priv->list, &dev_priv->mm.inactive_list);
73aa808f 2734 i915_gem_info_add_gtt(dev_priv, obj->size);
bf1a1092 2735
673a394b
EA		 2736 /* Assert that the object is not currently in any GPU domain. As it
2737 * wasn't in the GTT, there shouldn't be any way it could have been in
2738 * a GPU cache
2739 */
21d509e3
CW		 2740 BUG_ON(obj->read_domains & I915_GEM_GPU_DOMAINS);
2741 BUG_ON(obj->write_domain & I915_GEM_GPU_DOMAINS);
673a394b 2742
1c5d22f7
CW		 2743 trace_i915_gem_object_bind(obj, obj_priv->gtt_offset);
2744
673a394b
EA		 2745 return 0;
2746}
2747
2748void
2749i915_gem_clflush_object(struct drm_gem_object *obj)
2750{
23010e43 2751 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
673a394b
EA		 2752
2753 /* If we don't have a page list set up, then we're not pinned
2754 * to GPU, and we can ignore the cache flush because it'll happen
2755 * again at bind time.
2756 */
856fa198 2757 if (obj_priv->pages == NULL)
673a394b
EA		 2758 return;
2759
1c5d22f7 2760 trace_i915_gem_object_clflush(obj);
cfa16a0d 2761
856fa198 2762 drm_clflush_pages(obj_priv->pages, obj->size / PAGE_SIZE);
673a394b
EA		 2763}
2764
e47c68e9 2765/** Flushes any GPU write domain for the object if it's dirty. */
2dafb1e0 2766static int
ba3d8d74
DV		 2767i915_gem_object_flush_gpu_write_domain(struct drm_gem_object *obj,
2768 bool pipelined)
e47c68e9
EA		 2769{
2770 struct drm_device *dev = obj->dev;
1c5d22f7 2771 uint32_t old_write_domain;
e47c68e9
EA		 2772
2773 if ((obj->write_domain & I915_GEM_GPU_DOMAINS) == 0)
2dafb1e0 2774 return 0;
e47c68e9
EA		 2775
2776 /* Queue the GPU write cache flushing we need. */
1c5d22f7 2777 old_write_domain = obj->write_domain;
c78ec30b 2778 i915_gem_flush_ring(dev, NULL,
9220434a
CW		 2779 to_intel_bo(obj)->ring,
2780 0, obj->write_domain);
48b956c5 2781 BUG_ON(obj->write_domain);
1c5d22f7
CW		 2782
2783 trace_i915_gem_object_change_domain(obj,
2784 obj->read_domains,
2785 old_write_domain);
ba3d8d74
DV		 2786
2787 if (pipelined)
2788 return 0;
2789
2cf34d7b 2790 return i915_gem_object_wait_rendering(obj, true);
e47c68e9
EA		 2791}
2792
2793/** Flushes the GTT write domain for the object if it's dirty. */
2794static void
2795i915_gem_object_flush_gtt_write_domain(struct drm_gem_object *obj)
2796{
1c5d22f7
CW		 2797 uint32_t old_write_domain;
2798
e47c68e9
EA		 2799 if (obj->write_domain != I915_GEM_DOMAIN_GTT)
2800 return;
2801
2802 /* No actual flushing is required for the GTT write domain. Writes
2803 * to it immediately go to main memory as far as we know, so there's
2804 * no chipset flush. It also doesn't land in render cache.
2805 */
1c5d22f7 2806 old_write_domain = obj->write_domain;
e47c68e9 2807 obj->write_domain = 0;
1c5d22f7
CW		 2808
2809 trace_i915_gem_object_change_domain(obj,
2810 obj->read_domains,
2811 old_write_domain);
e47c68e9
EA		 2812}
2813
2814/** Flushes the CPU write domain for the object if it's dirty. */
2815static void
2816i915_gem_object_flush_cpu_write_domain(struct drm_gem_object *obj)
2817{
2818 struct drm_device *dev = obj->dev;
1c5d22f7 2819 uint32_t old_write_domain;
e47c68e9
EA		 2820
2821 if (obj->write_domain != I915_GEM_DOMAIN_CPU)
2822 return;
2823
2824 i915_gem_clflush_object(obj);
2825 drm_agp_chipset_flush(dev);
1c5d22f7 2826 old_write_domain = obj->write_domain;
e47c68e9 2827 obj->write_domain = 0;
1c5d22f7
CW		 2828
2829 trace_i915_gem_object_change_domain(obj,
2830 obj->read_domains,
2831 old_write_domain);
e47c68e9
EA		 2832}
2833
2ef7eeaa
EA		 2834/**
2835 * Moves a single object to the GTT read, and possibly write domain.
2836 *
2837 * This function returns when the move is complete, including waiting on
2838 * flushes to occur.
2839 */
79e53945 2840int
2ef7eeaa
EA		 2841i915_gem_object_set_to_gtt_domain(struct drm_gem_object *obj, int write)
2842{
23010e43 2843 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1c5d22f7 2844 uint32_t old_write_domain, old_read_domains;
e47c68e9 2845 int ret;
2ef7eeaa 2846
02354392
EA		 2847 /* Not valid to be called on unbound objects. */
2848 if (obj_priv->gtt_space == NULL)
2849 return -EINVAL;
2850
ba3d8d74 2851 ret = i915_gem_object_flush_gpu_write_domain(obj, false);
e47c68e9
EA		 2852 if (ret != 0)
2853 return ret;
2854
7213342d 2855 i915_gem_object_flush_cpu_write_domain(obj);
1c5d22f7 2856
ba3d8d74 2857 if (write) {
2cf34d7b 2858 ret = i915_gem_object_wait_rendering(obj, true);
ba3d8d74
DV		 2859 if (ret)
2860 return ret;
ba3d8d74 2861 }
2ef7eeaa 2862
7213342d
CW		 2863 old_write_domain = obj->write_domain;
2864 old_read_domains = obj->read_domains;
2ef7eeaa 2865
e47c68e9
EA		 2866 /* It should now be out of any other write domains, and we can update
2867 * the domain values for our changes.
2868 */
2869 BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_GTT) != 0);
2870 obj->read_domains |= I915_GEM_DOMAIN_GTT;
2871 if (write) {
7213342d 2872 obj->read_domains = I915_GEM_DOMAIN_GTT;
e47c68e9
EA		 2873 obj->write_domain = I915_GEM_DOMAIN_GTT;
2874 obj_priv->dirty = 1;
2ef7eeaa
EA		 2875 }
2876
1c5d22f7
CW		 2877 trace_i915_gem_object_change_domain(obj,
2878 old_read_domains,
2879 old_write_domain);
2880
e47c68e9
EA		 2881 return 0;
2882}
2883
b9241ea3
ZW		 2884/*
2885 * Prepare buffer for display plane. Use uninterruptible for possible flush
2886 * wait, as in modesetting process we're not supposed to be interrupted.
2887 */
2888int
48b956c5
CW		 2889i915_gem_object_set_to_display_plane(struct drm_gem_object *obj,
2890 bool pipelined)
b9241ea3 2891{
23010e43 2892 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
ba3d8d74 2893 uint32_t old_read_domains;
b9241ea3
ZW		 2894 int ret;
2895
2896 /* Not valid to be called on unbound objects. */
2897 if (obj_priv->gtt_space == NULL)
2898 return -EINVAL;
2899
ced270fa 2900 ret = i915_gem_object_flush_gpu_write_domain(obj, true);
48b956c5 2901 if (ret)
e35a41de 2902 return ret;
b9241ea3 2903
ced270fa
CW		 2904 /* Currently, we are always called from an non-interruptible context. */
2905 if (!pipelined) {
2906 ret = i915_gem_object_wait_rendering(obj, false);
2907 if (ret)
2908 return ret;
2909 }
2910
b118c1e3
CW		 2911 i915_gem_object_flush_cpu_write_domain(obj);
2912
b9241ea3 2913 old_read_domains = obj->read_domains;
c78ec30b 2914 obj->read_domains |= I915_GEM_DOMAIN_GTT;
b9241ea3
ZW		 2915
2916 trace_i915_gem_object_change_domain(obj,
2917 old_read_domains,
ba3d8d74 2918 obj->write_domain);
b9241ea3
ZW		 2919
2920 return 0;
2921}
2922
e47c68e9
EA		 2923/**
2924 * Moves a single object to the CPU read, and possibly write domain.
2925 *
2926 * This function returns when the move is complete, including waiting on
2927 * flushes to occur.
2928 */
2929static int
2930i915_gem_object_set_to_cpu_domain(struct drm_gem_object *obj, int write)
2931{
1c5d22f7 2932 uint32_t old_write_domain, old_read_domains;
e47c68e9
EA		 2933 int ret;
2934
ba3d8d74 2935 ret = i915_gem_object_flush_gpu_write_domain(obj, false);
e47c68e9
EA		 2936 if (ret != 0)
2937 return ret;
2ef7eeaa 2938
e47c68e9 2939 i915_gem_object_flush_gtt_write_domain(obj);
2ef7eeaa 2940
e47c68e9
EA		 2941 /* If we have a partially-valid cache of the object in the CPU,
2942 * finish invalidating it and free the per-page flags.
2ef7eeaa 2943 */
e47c68e9 2944 i915_gem_object_set_to_full_cpu_read_domain(obj);
2ef7eeaa 2945
7213342d 2946 if (write) {
2cf34d7b 2947 ret = i915_gem_object_wait_rendering(obj, true);
7213342d
CW		 2948 if (ret)
2949 return ret;
2950 }
2951
1c5d22f7
CW		 2952 old_write_domain = obj->write_domain;
2953 old_read_domains = obj->read_domains;
2954
e47c68e9
EA		 2955 /* Flush the CPU cache if it's still invalid. */
2956 if ((obj->read_domains & I915_GEM_DOMAIN_CPU) == 0) {
2ef7eeaa 2957 i915_gem_clflush_object(obj);
2ef7eeaa 2958
e47c68e9 2959 obj->read_domains |= I915_GEM_DOMAIN_CPU;
2ef7eeaa
EA		 2960 }
2961
2962 /* It should now be out of any other write domains, and we can update
2963 * the domain values for our changes.
2964 */
e47c68e9
EA		 2965 BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
2966
2967 /* If we're writing through the CPU, then the GPU read domains will
2968 * need to be invalidated at next use.
2969 */
2970 if (write) {
c78ec30b 2971 obj->read_domains = I915_GEM_DOMAIN_CPU;
e47c68e9
EA		 2972 obj->write_domain = I915_GEM_DOMAIN_CPU;
2973 }
2ef7eeaa 2974
1c5d22f7
CW		 2975 trace_i915_gem_object_change_domain(obj,
2976 old_read_domains,
2977 old_write_domain);
2978
2ef7eeaa
EA		 2979 return 0;
2980}
2981
673a394b
EA		 2982/*
2983 * Set the next domain for the specified object. This
2984 * may not actually perform the necessary flushing/invaliding though,
2985 * as that may want to be batched with other set_domain operations
2986 *
2987 * This is (we hope) the only really tricky part of gem. The goal
2988 * is fairly simple -- track which caches hold bits of the object
2989 * and make sure they remain coherent. A few concrete examples may
2990 * help to explain how it works. For shorthand, we use the notation
2991 * (read_domains, write_domain), e.g. (CPU, CPU) to indicate the
2992 * a pair of read and write domain masks.
2993 *
2994 * Case 1: the batch buffer
2995 *
2996 * 1. Allocated
2997 * 2. Written by CPU
2998 * 3. Mapped to GTT
2999 * 4. Read by GPU
3000 * 5. Unmapped from GTT
3001 * 6. Freed
3002 *
3003 * Let's take these a step at a time
3004 *
3005 * 1. Allocated
3006 * Pages allocated from the kernel may still have
3007 * cache contents, so we set them to (CPU, CPU) always.
3008 * 2. Written by CPU (using pwrite)
3009 * The pwrite function calls set_domain (CPU, CPU) and
3010 * this function does nothing (as nothing changes)
3011 * 3. Mapped by GTT
3012 * This function asserts that the object is not
3013 * currently in any GPU-based read or write domains
3014 * 4. Read by GPU
3015 * i915_gem_execbuffer calls set_domain (COMMAND, 0).
3016 * As write_domain is zero, this function adds in the
3017 * current read domains (CPU+COMMAND, 0).
3018 * flush_domains is set to CPU.
3019 * invalidate_domains is set to COMMAND
3020 * clflush is run to get data out of the CPU caches
3021 * then i915_dev_set_domain calls i915_gem_flush to
3022 * emit an MI_FLUSH and drm_agp_chipset_flush
3023 * 5. Unmapped from GTT
3024 * i915_gem_object_unbind calls set_domain (CPU, CPU)
3025 * flush_domains and invalidate_domains end up both zero
3026 * so no flushing/invalidating happens
3027 * 6. Freed
3028 * yay, done
3029 *
3030 * Case 2: The shared render buffer
3031 *
3032 * 1. Allocated
3033 * 2. Mapped to GTT
3034 * 3. Read/written by GPU
3035 * 4. set_domain to (CPU,CPU)
3036 * 5. Read/written by CPU
3037 * 6. Read/written by GPU
3038 *
3039 * 1. Allocated
3040 * Same as last example, (CPU, CPU)
3041 * 2. Mapped to GTT
3042 * Nothing changes (assertions find that it is not in the GPU)
3043 * 3. Read/written by GPU
3044 * execbuffer calls set_domain (RENDER, RENDER)
3045 * flush_domains gets CPU
3046 * invalidate_domains gets GPU
3047 * clflush (obj)
3048 * MI_FLUSH and drm_agp_chipset_flush
3049 * 4. set_domain (CPU, CPU)
3050 * flush_domains gets GPU
3051 * invalidate_domains gets CPU
3052 * wait_rendering (obj) to make sure all drawing is complete.
3053 * This will include an MI_FLUSH to get the data from GPU
3054 * to memory
3055 * clflush (obj) to invalidate the CPU cache
3056 * Another MI_FLUSH in i915_gem_flush (eliminate this somehow?)
3057 * 5. Read/written by CPU
3058 * cache lines are loaded and dirtied
3059 * 6. Read written by GPU
3060 * Same as last GPU access
3061 *
3062 * Case 3: The constant buffer
3063 *
3064 * 1. Allocated
3065 * 2. Written by CPU
3066 * 3. Read by GPU
3067 * 4. Updated (written) by CPU again
3068 * 5. Read by GPU
3069 *
3070 * 1. Allocated
3071 * (CPU, CPU)
3072 * 2. Written by CPU
3073 * (CPU, CPU)
3074 * 3. Read by GPU
3075 * (CPU+RENDER, 0)
3076 * flush_domains = CPU
3077 * invalidate_domains = RENDER
3078 * clflush (obj)
3079 * MI_FLUSH
3080 * drm_agp_chipset_flush
3081 * 4. Updated (written) by CPU again
3082 * (CPU, CPU)
3083 * flush_domains = 0 (no previous write domain)
3084 * invalidate_domains = 0 (no new read domains)
3085 * 5. Read by GPU
3086 * (CPU+RENDER, 0)
3087 * flush_domains = CPU
3088 * invalidate_domains = RENDER
3089 * clflush (obj)
3090 * MI_FLUSH
3091 * drm_agp_chipset_flush
3092 */
c0d90829 3093static void
8b0e378a 3094i915_gem_object_set_to_gpu_domain(struct drm_gem_object *obj)
673a394b
EA		 3095{
3096 struct drm_device *dev = obj->dev;
9220434a 3097 struct drm_i915_private *dev_priv = dev->dev_private;
23010e43 3098 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
673a394b
EA		 3099 uint32_t invalidate_domains = 0;
3100 uint32_t flush_domains = 0;
1c5d22f7 3101 uint32_t old_read_domains;
e47c68e9 3102
8b0e378a
EA		 3103 BUG_ON(obj->pending_read_domains & I915_GEM_DOMAIN_CPU);
3104 BUG_ON(obj->pending_write_domain == I915_GEM_DOMAIN_CPU);
673a394b 3105
652c393a
JB		 3106 intel_mark_busy(dev, obj);
3107
673a394b
EA		 3108 /*
3109 * If the object isn't moving to a new write domain,
3110 * let the object stay in multiple read domains
3111 */
8b0e378a
EA		 3112 if (obj->pending_write_domain == 0)
3113 obj->pending_read_domains |= obj->read_domains;
673a394b
EA		 3114 else
3115 obj_priv->dirty = 1;
3116
3117 /*
3118 * Flush the current write domain if
3119 * the new read domains don't match. Invalidate
3120 * any read domains which differ from the old
3121 * write domain
3122 */
8b0e378a
EA		 3123 if (obj->write_domain &&
3124 obj->write_domain != obj->pending_read_domains) {
673a394b 3125 flush_domains |= obj->write_domain;
8b0e378a
EA		 3126 invalidate_domains |=
3127 obj->pending_read_domains & ~obj->write_domain;
673a394b
EA		 3128 }
3129 /*
3130 * Invalidate any read caches which may have
3131 * stale data. That is, any new read domains.
3132 */
8b0e378a 3133 invalidate_domains |= obj->pending_read_domains & ~obj->read_domains;
3d2a812a 3134 if ((flush_domains | invalidate_domains) & I915_GEM_DOMAIN_CPU)
673a394b 3135 i915_gem_clflush_object(obj);
673a394b 3136
1c5d22f7
CW		 3137 old_read_domains = obj->read_domains;
3138
efbeed96
EA		 3139 /* The actual obj->write_domain will be updated with
3140 * pending_write_domain after we emit the accumulated flush for all
3141 * of our domain changes in execbuffers (which clears objects'
3142 * write_domains). So if we have a current write domain that we
3143 * aren't changing, set pending_write_domain to that.
3144 */
3145 if (flush_domains == 0 && obj->pending_write_domain == 0)
3146 obj->pending_write_domain = obj->write_domain;
8b0e378a 3147 obj->read_domains = obj->pending_read_domains;
673a394b
EA		 3148
3149 dev->invalidate_domains |= invalidate_domains;
3150 dev->flush_domains |= flush_domains;
9220434a
CW		 3151 if (obj_priv->ring)
3152 dev_priv->mm.flush_rings |= obj_priv->ring->id;
1c5d22f7
CW		 3153
3154 trace_i915_gem_object_change_domain(obj,
3155 old_read_domains,
3156 obj->write_domain);
673a394b
EA		 3157}
3158
3159/**
e47c68e9 3160 * Moves the object from a partially CPU read to a full one.
673a394b 3161 *
e47c68e9
EA		 3162 * Note that this only resolves i915_gem_object_set_cpu_read_domain_range(),
3163 * and doesn't handle transitioning from !(read_domains & I915_GEM_DOMAIN_CPU).
673a394b 3164 */
e47c68e9
EA		 3165static void
3166i915_gem_object_set_to_full_cpu_read_domain(struct drm_gem_object *obj)
673a394b 3167{
23010e43 3168 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
673a394b 3169
e47c68e9
EA		 3170 if (!obj_priv->page_cpu_valid)
3171 return;
3172
3173 /* If we're partially in the CPU read domain, finish moving it in.
3174 */
3175 if (obj->read_domains & I915_GEM_DOMAIN_CPU) {
3176 int i;
3177
3178 for (i = 0; i <= (obj->size - 1) / PAGE_SIZE; i++) {
3179 if (obj_priv->page_cpu_valid[i])
3180 continue;
856fa198 3181 drm_clflush_pages(obj_priv->pages + i, 1);
e47c68e9 3182 }
e47c68e9
EA		 3183 }
3184
3185 /* Free the page_cpu_valid mappings which are now stale, whether
3186 * or not we've got I915_GEM_DOMAIN_CPU.
3187 */
9a298b2a 3188 kfree(obj_priv->page_cpu_valid);
e47c68e9
EA		 3189 obj_priv->page_cpu_valid = NULL;
3190}
3191
3192/**
3193 * Set the CPU read domain on a range of the object.
3194 *
3195 * The object ends up with I915_GEM_DOMAIN_CPU in its read flags although it's
3196 * not entirely valid. The page_cpu_valid member of the object flags which
3197 * pages have been flushed, and will be respected by
3198 * i915_gem_object_set_to_cpu_domain() if it's called on to get a valid mapping
3199 * of the whole object.
3200 *
3201 * This function returns when the move is complete, including waiting on
3202 * flushes to occur.
3203 */
3204static int
3205i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object *obj,
3206 uint64_t offset, uint64_t size)
3207{
23010e43 3208 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1c5d22f7 3209 uint32_t old_read_domains;
e47c68e9 3210 int i, ret;
673a394b 3211
e47c68e9
EA		 3212 if (offset == 0 && size == obj->size)
3213 return i915_gem_object_set_to_cpu_domain(obj, 0);
673a394b 3214
ba3d8d74 3215 ret = i915_gem_object_flush_gpu_write_domain(obj, false);
e47c68e9 3216 if (ret != 0)
6a47baa6 3217 return ret;
e47c68e9
EA		 3218 i915_gem_object_flush_gtt_write_domain(obj);
3219
3220 /* If we're already fully in the CPU read domain, we're done. */
3221 if (obj_priv->page_cpu_valid == NULL &&
3222 (obj->read_domains & I915_GEM_DOMAIN_CPU) != 0)
3223 return 0;
673a394b 3224
e47c68e9
EA		 3225 /* Otherwise, create/clear the per-page CPU read domain flag if we're
3226 * newly adding I915_GEM_DOMAIN_CPU
3227 */
673a394b 3228 if (obj_priv->page_cpu_valid == NULL) {
9a298b2a
EA		 3229 obj_priv->page_cpu_valid = kzalloc(obj->size / PAGE_SIZE,
3230 GFP_KERNEL);
e47c68e9
EA		 3231 if (obj_priv->page_cpu_valid == NULL)
3232 return -ENOMEM;
3233 } else if ((obj->read_domains & I915_GEM_DOMAIN_CPU) == 0)
3234 memset(obj_priv->page_cpu_valid, 0, obj->size / PAGE_SIZE);
673a394b
EA		 3235
3236 /* Flush the cache on any pages that are still invalid from the CPU's
3237 * perspective.
3238 */
e47c68e9
EA		 3239 for (i = offset / PAGE_SIZE; i <= (offset + size - 1) / PAGE_SIZE;
3240 i++) {
673a394b
EA		 3241 if (obj_priv->page_cpu_valid[i])
3242 continue;
3243
856fa198 3244 drm_clflush_pages(obj_priv->pages + i, 1);
673a394b
EA		 3245
3246 obj_priv->page_cpu_valid[i] = 1;
3247 }
3248
e47c68e9
EA		 3249 /* It should now be out of any other write domains, and we can update
3250 * the domain values for our changes.
3251 */
3252 BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
3253
1c5d22f7 3254 old_read_domains = obj->read_domains;
e47c68e9
EA		 3255 obj->read_domains |= I915_GEM_DOMAIN_CPU;
3256
1c5d22f7
CW		 3257 trace_i915_gem_object_change_domain(obj,
3258 old_read_domains,
3259 obj->write_domain);
3260
673a394b
EA		 3261 return 0;
3262}
3263
673a394b
EA		 3264/**
3265 * Pin an object to the GTT and evaluate the relocations landing in it.
3266 */
3267static int
3268i915_gem_object_pin_and_relocate(struct drm_gem_object *obj,
3269 struct drm_file *file_priv,
76446cac 3270 struct drm_i915_gem_exec_object2 *entry,
40a5f0de 3271 struct drm_i915_gem_relocation_entry *relocs)
673a394b
EA		 3272{
3273 struct drm_device *dev = obj->dev;
0839ccb8 3274 drm_i915_private_t *dev_priv = dev->dev_private;
23010e43 3275 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
673a394b 3276 int i, ret;
0839ccb8 3277 void __iomem *reloc_page;
76446cac
JB		 3278 bool need_fence;
3279
3280 need_fence = entry->flags & EXEC_OBJECT_NEEDS_FENCE &&
3281 obj_priv->tiling_mode != I915_TILING_NONE;
3282
3283 /* Check fence reg constraints and rebind if necessary */
808b24d6
CW		 3284 if (need_fence &&
3285 !i915_gem_object_fence_offset_ok(obj,
3286 obj_priv->tiling_mode)) {
3287 ret = i915_gem_object_unbind(obj);
3288 if (ret)
3289 return ret;
3290 }
673a394b
EA		 3291
3292 /* Choose the GTT offset for our buffer and put it there. */
3293 ret = i915_gem_object_pin(obj, (uint32_t) entry->alignment);
3294 if (ret)
3295 return ret;
3296
76446cac
JB		 3297 /*
3298 * Pre-965 chips need a fence register set up in order to
3299 * properly handle blits to/from tiled surfaces.
3300 */
3301 if (need_fence) {
53640e1d 3302 ret = i915_gem_object_get_fence_reg(obj, true);
76446cac 3303 if (ret != 0) {
76446cac
JB		 3304 i915_gem_object_unpin(obj);
3305 return ret;
3306 }
53640e1d
CW		 3307
3308 dev_priv->fence_regs[obj_priv->fence_reg].gpu = true;
76446cac
JB		 3309 }
3310
673a394b
EA		 3311 entry->offset = obj_priv->gtt_offset;
3312
673a394b
EA		 3313 /* Apply the relocations, using the GTT aperture to avoid cache
3314 * flushing requirements.
3315 */
3316 for (i = 0; i < entry->relocation_count; i++) {
40a5f0de 3317 struct drm_i915_gem_relocation_entry *reloc= &relocs[i];
673a394b
EA		 3318 struct drm_gem_object *target_obj;
3319 struct drm_i915_gem_object *target_obj_priv;
3043c60c
EA		 3320 uint32_t reloc_val, reloc_offset;
3321 uint32_t __iomem *reloc_entry;
673a394b 3322
673a394b 3323 target_obj = drm_gem_object_lookup(obj->dev, file_priv,
40a5f0de 3324 reloc->target_handle);
673a394b
EA		 3325 if (target_obj == NULL) {
3326 i915_gem_object_unpin(obj);
bf79cb91 3327 return -ENOENT;
673a394b 3328 }
23010e43 3329 target_obj_priv = to_intel_bo(target_obj);
673a394b 3330
8542a0bb
CW		 3331#if WATCH_RELOC
3332 DRM_INFO("%s: obj %p offset %08x target %d "
3333 "read %08x write %08x gtt %08x "
3334 "presumed %08x delta %08x\n",
3335 __func__,
3336 obj,
3337 (int) reloc->offset,
3338 (int) reloc->target_handle,
3339 (int) reloc->read_domains,
3340 (int) reloc->write_domain,
3341 (int) target_obj_priv->gtt_offset,
3342 (int) reloc->presumed_offset,
3343 reloc->delta);
3344#endif
3345
673a394b
EA		 3346 /* The target buffer should have appeared before us in the
3347 * exec_object list, so it should have a GTT space bound by now.
3348 */
3349 if (target_obj_priv->gtt_space == NULL) {
3350 DRM_ERROR("No GTT space found for object %d\n",
40a5f0de 3351 reloc->target_handle);
673a394b
EA		 3352 drm_gem_object_unreference(target_obj);
3353 i915_gem_object_unpin(obj);
3354 return -EINVAL;
3355 }
3356
8542a0bb 3357 /* Validate that the target is in a valid r/w GPU domain */
16edd550
DV		 3358 if (reloc->write_domain & (reloc->write_domain - 1)) {
3359 DRM_ERROR("reloc with multiple write domains: "
3360 "obj %p target %d offset %d "
3361 "read %08x write %08x",
3362 obj, reloc->target_handle,
3363 (int) reloc->offset,
3364 reloc->read_domains,
3365 reloc->write_domain);
3366 return -EINVAL;
3367 }
40a5f0de
EA		 3368 if (reloc->write_domain & I915_GEM_DOMAIN_CPU ||
3369 reloc->read_domains & I915_GEM_DOMAIN_CPU) {
e47c68e9
EA		 3370 DRM_ERROR("reloc with read/write CPU domains: "
3371 "obj %p target %d offset %d "
3372 "read %08x write %08x",
40a5f0de
EA		 3373 obj, reloc->target_handle,
3374 (int) reloc->offset,
3375 reloc->read_domains,
3376 reloc->write_domain);
491152b8
CW		 3377 drm_gem_object_unreference(target_obj);
3378 i915_gem_object_unpin(obj);
e47c68e9
EA		 3379 return -EINVAL;
3380 }
40a5f0de
EA		 3381 if (reloc->write_domain && target_obj->pending_write_domain &&
3382 reloc->write_domain != target_obj->pending_write_domain) {
673a394b
EA		 3383 DRM_ERROR("Write domain conflict: "
3384 "obj %p target %d offset %d "
3385 "new %08x old %08x\n",
40a5f0de
EA		 3386 obj, reloc->target_handle,
3387 (int) reloc->offset,
3388 reloc->write_domain,
673a394b
EA		 3389 target_obj->pending_write_domain);
3390 drm_gem_object_unreference(target_obj);
3391 i915_gem_object_unpin(obj);
3392 return -EINVAL;
3393 }
3394
40a5f0de
EA		 3395 target_obj->pending_read_domains |= reloc->read_domains;
3396 target_obj->pending_write_domain |= reloc->write_domain;
673a394b
EA		 3397
3398 /* If the relocation already has the right value in it, no
3399 * more work needs to be done.
3400 */
40a5f0de 3401 if (target_obj_priv->gtt_offset == reloc->presumed_offset) {
673a394b
EA		 3402 drm_gem_object_unreference(target_obj);
3403 continue;
3404 }
3405
8542a0bb
CW		 3406 /* Check that the relocation address is valid... */
3407 if (reloc->offset > obj->size - 4) {
3408 DRM_ERROR("Relocation beyond object bounds: "
3409 "obj %p target %d offset %d size %d.\n",
3410 obj, reloc->target_handle,
3411 (int) reloc->offset, (int) obj->size);
3412 drm_gem_object_unreference(target_obj);
3413 i915_gem_object_unpin(obj);
3414 return -EINVAL;
3415 }
3416 if (reloc->offset & 3) {
3417 DRM_ERROR("Relocation not 4-byte aligned: "
3418 "obj %p target %d offset %d.\n",
3419 obj, reloc->target_handle,
3420 (int) reloc->offset);
3421 drm_gem_object_unreference(target_obj);
3422 i915_gem_object_unpin(obj);
3423 return -EINVAL;
3424 }
3425
3426 /* and points to somewhere within the target object. */
3427 if (reloc->delta >= target_obj->size) {
3428 DRM_ERROR("Relocation beyond target object bounds: "
3429 "obj %p target %d delta %d size %d.\n",
3430 obj, reloc->target_handle,
3431 (int) reloc->delta, (int) target_obj->size);
3432 drm_gem_object_unreference(target_obj);
3433 i915_gem_object_unpin(obj);
3434 return -EINVAL;
3435 }
3436
2ef7eeaa
EA		 3437 ret = i915_gem_object_set_to_gtt_domain(obj, 1);
3438 if (ret != 0) {
3439 drm_gem_object_unreference(target_obj);
3440 i915_gem_object_unpin(obj);
3441 return -EINVAL;
673a394b
EA		 3442 }
3443
3444 /* Map the page containing the relocation we're going to
3445 * perform.
3446 */
40a5f0de 3447 reloc_offset = obj_priv->gtt_offset + reloc->offset;
0839ccb8
KP		 3448 reloc_page = io_mapping_map_atomic_wc(dev_priv->mm.gtt_mapping,
3449 (reloc_offset &
fca3ec01
CW		 3450 ~(PAGE_SIZE - 1)),
3451 KM_USER0);
3043c60c 3452 reloc_entry = (uint32_t __iomem *)(reloc_page +
0839ccb8 3453 (reloc_offset & (PAGE_SIZE - 1)));
40a5f0de 3454 reloc_val = target_obj_priv->gtt_offset + reloc->delta;
673a394b 3455
673a394b 3456 writel(reloc_val, reloc_entry);
fca3ec01 3457 io_mapping_unmap_atomic(reloc_page, KM_USER0);
673a394b 3458
40a5f0de
EA		 3459 /* The updated presumed offset for this entry will be
3460 * copied back out to the user.
673a394b 3461 */
40a5f0de 3462 reloc->presumed_offset = target_obj_priv->gtt_offset;
673a394b
EA		 3463
3464 drm_gem_object_unreference(target_obj);
3465 }
3466
673a394b
EA		 3467 return 0;
3468}
3469
673a394b
EA		 3470/* Throttle our rendering by waiting until the ring has completed our requests
3471 * emitted over 20 msec ago.
3472 *
b962442e
EA		 3473 * Note that if we were to use the current jiffies each time around the loop,
3474 * we wouldn't escape the function with any frames outstanding if the time to
3475 * render a frame was over 20ms.
3476 *
673a394b
EA		 3477 * This should get us reasonable parallelism between CPU and GPU but also
3478 * relatively low latency when blocking on a particular request to finish.
3479 */
3480static int
f787a5f5 3481i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file)
673a394b 3482{
f787a5f5
CW		 3483 struct drm_i915_private *dev_priv = dev->dev_private;
3484 struct drm_i915_file_private *file_priv = file->driver_priv;
b962442e 3485 unsigned long recent_enough = jiffies - msecs_to_jiffies(20);
f787a5f5
CW		 3486 struct drm_i915_gem_request *request;
3487 struct intel_ring_buffer *ring = NULL;
3488 u32 seqno = 0;
3489 int ret;
673a394b 3490
1c25595f 3491 spin_lock(&file_priv->mm.lock);
f787a5f5 3492 list_for_each_entry(request, &file_priv->mm.request_list, client_list) {
b962442e
EA		 3493 if (time_after_eq(request->emitted_jiffies, recent_enough))
3494 break;
3495
f787a5f5
CW		 3496 ring = request->ring;
3497 seqno = request->seqno;
b962442e 3498 }
1c25595f 3499 spin_unlock(&file_priv->mm.lock);
f787a5f5
CW		 3500
3501 if (seqno == 0)
3502 return 0;
3503
3504 ret = 0;
3505 if (!i915_seqno_passed(ring->get_seqno(dev, ring), seqno)) {
3506 /* And wait for the seqno passing without holding any locks and
3507 * causing extra latency for others. This is safe as the irq
3508 * generation is designed to be run atomically and so is
3509 * lockless.
3510 */
3511 ring->user_irq_get(dev, ring);
3512 ret = wait_event_interruptible(ring->irq_queue,
3513 i915_seqno_passed(ring->get_seqno(dev, ring), seqno)
3514 || atomic_read(&dev_priv->mm.wedged));
3515 ring->user_irq_put(dev, ring);
3516
3517 if (ret == 0 && atomic_read(&dev_priv->mm.wedged))
3518 ret = -EIO;
3519 }
3520
3521 if (ret == 0)
3522 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, 0);
b962442e 3523
673a394b
EA		 3524 return ret;
3525}
3526
40a5f0de 3527static int
76446cac 3528i915_gem_get_relocs_from_user(struct drm_i915_gem_exec_object2 *exec_list,
40a5f0de
EA		 3529 uint32_t buffer_count,
3530 struct drm_i915_gem_relocation_entry **relocs)
3531{
3532 uint32_t reloc_count = 0, reloc_index = 0, i;
3533 int ret;
3534
3535 *relocs = NULL;
3536 for (i = 0; i < buffer_count; i++) {
3537 if (reloc_count + exec_list[i].relocation_count < reloc_count)
3538 return -EINVAL;
3539 reloc_count += exec_list[i].relocation_count;
3540 }
3541
8e7d2b2c 3542 *relocs = drm_calloc_large(reloc_count, sizeof(**relocs));
76446cac
JB		 3543 if (*relocs == NULL) {
3544 DRM_ERROR("failed to alloc relocs, count %d\n", reloc_count);
40a5f0de 3545 return -ENOMEM;
76446cac 3546 }
40a5f0de
EA		 3547
3548 for (i = 0; i < buffer_count; i++) {
3549 struct drm_i915_gem_relocation_entry __user *user_relocs;
3550
3551 user_relocs = (void __user *)(uintptr_t)exec_list[i].relocs_ptr;
3552
3553 ret = copy_from_user(&(*relocs)[reloc_index],
3554 user_relocs,
3555 exec_list[i].relocation_count *
3556 sizeof(**relocs));
3557 if (ret != 0) {
8e7d2b2c 3558 drm_free_large(*relocs);
40a5f0de 3559 *relocs = NULL;
2bc43b5c 3560 return -EFAULT;
40a5f0de
EA		 3561 }
3562
3563 reloc_index += exec_list[i].relocation_count;
3564 }
3565
2bc43b5c 3566 return 0;
40a5f0de
EA		 3567}
3568
3569static int
76446cac 3570i915_gem_put_relocs_to_user(struct drm_i915_gem_exec_object2 *exec_list,
40a5f0de
EA		 3571 uint32_t buffer_count,
3572 struct drm_i915_gem_relocation_entry *relocs)
3573{
3574 uint32_t reloc_count = 0, i;
2bc43b5c 3575 int ret = 0;
40a5f0de 3576
93533c29
CW		 3577 if (relocs == NULL)
3578 return 0;
3579
40a5f0de
EA		 3580 for (i = 0; i < buffer_count; i++) {
3581 struct drm_i915_gem_relocation_entry __user *user_relocs;
2bc43b5c 3582 int unwritten;
40a5f0de
EA		 3583
3584 user_relocs = (void __user *)(uintptr_t)exec_list[i].relocs_ptr;
3585
2bc43b5c
FM		 3586 unwritten = copy_to_user(user_relocs,
3587 &relocs[reloc_count],
3588 exec_list[i].relocation_count *
3589 sizeof(*relocs));
3590
3591 if (unwritten) {
3592 ret = -EFAULT;
3593 goto err;
40a5f0de
EA		 3594 }
3595
3596 reloc_count += exec_list[i].relocation_count;
3597 }
3598
2bc43b5c 3599err:
8e7d2b2c 3600 drm_free_large(relocs);
40a5f0de
EA		 3601
3602 return ret;
3603}
3604
83d60795 3605static int
76446cac 3606i915_gem_check_execbuffer (struct drm_i915_gem_execbuffer2 *exec,
83d60795
CW		 3607 uint64_t exec_offset)
3608{
3609 uint32_t exec_start, exec_len;
3610
3611 exec_start = (uint32_t) exec_offset + exec->batch_start_offset;
3612 exec_len = (uint32_t) exec->batch_len;
3613
3614 if ((exec_start | exec_len) & 0x7)
3615 return -EINVAL;
3616
3617 if (!exec_start)
3618 return -EINVAL;
3619
3620 return 0;
3621}
3622
e6c3a2a6 3623static int
6b95a207
KH		 3624i915_gem_wait_for_pending_flip(struct drm_device *dev,
3625 struct drm_gem_object **object_list,
3626 int count)
3627{
3628 drm_i915_private_t *dev_priv = dev->dev_private;
3629 struct drm_i915_gem_object *obj_priv;
3630 DEFINE_WAIT(wait);
3631 int i, ret = 0;
3632
3633 for (;;) {
3634 prepare_to_wait(&dev_priv->pending_flip_queue,
3635 &wait, TASK_INTERRUPTIBLE);
3636 for (i = 0; i < count; i++) {
23010e43 3637 obj_priv = to_intel_bo(object_list[i]);
6b95a207
KH		 3638 if (atomic_read(&obj_priv->pending_flip) > 0)
3639 break;
3640 }
3641 if (i == count)
3642 break;
3643
3644 if (!signal_pending(current)) {
3645 mutex_unlock(&dev->struct_mutex);
3646 schedule();
3647 mutex_lock(&dev->struct_mutex);
3648 continue;
3649 }
3650 ret = -ERESTARTSYS;
3651 break;
3652 }
3653 finish_wait(&dev_priv->pending_flip_queue, &wait);
3654
3655 return ret;
3656}
3657
8dc5d147 3658static int
76446cac
JB		 3659i915_gem_do_execbuffer(struct drm_device *dev, void *data,
3660 struct drm_file *file_priv,
3661 struct drm_i915_gem_execbuffer2 *args,
3662 struct drm_i915_gem_exec_object2 *exec_list)
673a394b
EA		 3663{
3664 drm_i915_private_t *dev_priv = dev->dev_private;
673a394b
EA		 3665 struct drm_gem_object **object_list = NULL;
3666 struct drm_gem_object *batch_obj;
b70d11da 3667 struct drm_i915_gem_object *obj_priv;
201361a5 3668 struct drm_clip_rect *cliprects = NULL;
93533c29 3669 struct drm_i915_gem_relocation_entry *relocs = NULL;
8dc5d147 3670 struct drm_i915_gem_request *request = NULL;
30dbf0c0 3671 int ret, ret2, i, pinned = 0;
673a394b 3672 uint64_t exec_offset;
5c12a07e 3673 uint32_t reloc_index;
6b95a207 3674 int pin_tries, flips;
673a394b 3675
852835f3
ZN		 3676 struct intel_ring_buffer *ring = NULL;
3677
30dbf0c0
CW		 3678 ret = i915_gem_check_is_wedged(dev);
3679 if (ret)
3680 return ret;
3681
673a394b
EA		 3682#if WATCH_EXEC
3683 DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n",
3684 (int) args->buffers_ptr, args->buffer_count, args->batch_len);
3685#endif
d1b851fc
ZN		 3686 if (args->flags & I915_EXEC_BSD) {
3687 if (!HAS_BSD(dev)) {
3688 DRM_ERROR("execbuf with wrong flag\n");
3689 return -EINVAL;
3690 }
3691 ring = &dev_priv->bsd_ring;
3692 } else {
3693 ring = &dev_priv->render_ring;
3694 }
3695
4f481ed2
EA		 3696 if (args->buffer_count < 1) {
3697 DRM_ERROR("execbuf with %d buffers\n", args->buffer_count);
3698 return -EINVAL;
3699 }
c8e0f93a 3700 object_list = drm_malloc_ab(sizeof(*object_list), args->buffer_count);
76446cac
JB		 3701 if (object_list == NULL) {
3702 DRM_ERROR("Failed to allocate object list for %d buffers\n",
673a394b
EA		 3703 args->buffer_count);
3704 ret = -ENOMEM;
3705 goto pre_mutex_err;
3706 }
673a394b 3707
201361a5 3708 if (args->num_cliprects != 0) {
9a298b2a
EA		 3709 cliprects = kcalloc(args->num_cliprects, sizeof(*cliprects),
3710 GFP_KERNEL);
a40e8d31
OA		 3711 if (cliprects == NULL) {
3712 ret = -ENOMEM;
201361a5 3713 goto pre_mutex_err;
a40e8d31 3714 }
201361a5
EA		 3715
3716 ret = copy_from_user(cliprects,
3717 (struct drm_clip_rect __user *)
3718 (uintptr_t) args->cliprects_ptr,
3719 sizeof(*cliprects) * args->num_cliprects);
3720 if (ret != 0) {
3721 DRM_ERROR("copy %d cliprects failed: %d\n",
3722 args->num_cliprects, ret);
c877cdce 3723 ret = -EFAULT;
201361a5
EA		 3724 goto pre_mutex_err;
3725 }
3726 }
3727
8dc5d147
CW		 3728 request = kzalloc(sizeof(*request), GFP_KERNEL);
3729 if (request == NULL) {
3730 ret = -ENOMEM;
3731 goto pre_mutex_err;
3732 }
3733
40a5f0de
EA		 3734 ret = i915_gem_get_relocs_from_user(exec_list, args->buffer_count,
3735 &relocs);
3736 if (ret != 0)
3737 goto pre_mutex_err;
3738
76c1dec1
CW		 3739 ret = i915_mutex_lock_interruptible(dev);
3740 if (ret)
3741 goto pre_mutex_err;
673a394b 3742
673a394b 3743 if (dev_priv->mm.suspended) {
673a394b 3744 mutex_unlock(&dev->struct_mutex);
a198bc80
CW		 3745 ret = -EBUSY;
3746 goto pre_mutex_err;
673a394b
EA		 3747 }
3748
ac94a962 3749 /* Look up object handles */
6b95a207 3750 flips = 0;
673a394b
EA		 3751 for (i = 0; i < args->buffer_count; i++) {
3752 object_list[i] = drm_gem_object_lookup(dev, file_priv,
3753 exec_list[i].handle);
3754 if (object_list[i] == NULL) {
3755 DRM_ERROR("Invalid object handle %d at index %d\n",
3756 exec_list[i].handle, i);
0ce907f8
CW		 3757 /* prevent error path from reading uninitialized data */
3758 args->buffer_count = i + 1;
bf79cb91 3759 ret = -ENOENT;
673a394b
EA		 3760 goto err;
3761 }
b70d11da 3762
23010e43 3763 obj_priv = to_intel_bo(object_list[i]);
b70d11da
KH		 3764 if (obj_priv->in_execbuffer) {
3765 DRM_ERROR("Object %p appears more than once in object list\n",
3766 object_list[i]);
0ce907f8
CW		 3767 /* prevent error path from reading uninitialized data */
3768 args->buffer_count = i + 1;
bf79cb91 3769 ret = -EINVAL;
b70d11da
KH		 3770 goto err;
3771 }
3772 obj_priv->in_execbuffer = true;
6b95a207
KH		 3773 flips += atomic_read(&obj_priv->pending_flip);
3774 }
3775
3776 if (flips > 0) {
3777 ret = i915_gem_wait_for_pending_flip(dev, object_list,
3778 args->buffer_count);
3779 if (ret)
3780 goto err;
ac94a962 3781 }
673a394b 3782
ac94a962
KP		 3783 /* Pin and relocate */
3784 for (pin_tries = 0; ; pin_tries++) {
3785 ret = 0;
40a5f0de
EA		 3786 reloc_index = 0;
3787
ac94a962
KP		 3788 for (i = 0; i < args->buffer_count; i++) {
3789 object_list[i]->pending_read_domains = 0;
3790 object_list[i]->pending_write_domain = 0;
3791 ret = i915_gem_object_pin_and_relocate(object_list[i],
3792 file_priv,
40a5f0de
EA		 3793 &exec_list[i],
3794 &relocs[reloc_index]);
ac94a962
KP		 3795 if (ret)
3796 break;
3797 pinned = i + 1;
40a5f0de 3798 reloc_index += exec_list[i].relocation_count;
ac94a962
KP		 3799 }
3800 /* success */
3801 if (ret == 0)
3802 break;
3803
3804 /* error other than GTT full, or we've already tried again */
2939e1f5 3805 if (ret != -ENOSPC || pin_tries >= 1) {
07f73f69
CW		 3806 if (ret != -ERESTARTSYS) {
3807 unsigned long long total_size = 0;
3d1cc470
CW		 3808 int num_fences = 0;
3809 for (i = 0; i < args->buffer_count; i++) {
43b27f40 3810 obj_priv = to_intel_bo(object_list[i]);
3d1cc470 3811
07f73f69 3812 total_size += object_list[i]->size;
3d1cc470
CW		 3813 num_fences +=
3814 exec_list[i].flags & EXEC_OBJECT_NEEDS_FENCE &&
3815 obj_priv->tiling_mode != I915_TILING_NONE;
3816 }
3817 DRM_ERROR("Failed to pin buffer %d of %d, total %llu bytes, %d fences: %d\n",
07f73f69 3818 pinned+1, args->buffer_count,
3d1cc470
CW		 3819 total_size, num_fences,
3820 ret);
73aa808f
CW		 3821 DRM_ERROR("%u objects [%u pinned, %u GTT], "
3822 "%zu object bytes [%zu pinned], "
3823 "%zu /%zu gtt bytes\n",
3824 dev_priv->mm.object_count,
3825 dev_priv->mm.pin_count,
3826 dev_priv->mm.gtt_count,
3827 dev_priv->mm.object_memory,
3828 dev_priv->mm.pin_memory,
3829 dev_priv->mm.gtt_memory,
3830 dev_priv->mm.gtt_total);
07f73f69 3831 }
673a394b
EA		 3832 goto err;
3833 }
ac94a962
KP		 3834
3835 /* unpin all of our buffers */
3836 for (i = 0; i < pinned; i++)
3837 i915_gem_object_unpin(object_list[i]);
b1177636 3838 pinned = 0;
ac94a962
KP		 3839
3840 /* evict everyone we can from the aperture */
3841 ret = i915_gem_evict_everything(dev);
07f73f69 3842 if (ret && ret != -ENOSPC)
ac94a962 3843 goto err;
673a394b
EA		 3844 }
3845
3846 /* Set the pending read domains for the batch buffer to COMMAND */
3847 batch_obj = object_list[args->buffer_count-1];
5f26a2c7
CW		 3848 if (batch_obj->pending_write_domain) {
3849 DRM_ERROR("Attempting to use self-modifying batch buffer\n");
3850 ret = -EINVAL;
3851 goto err;
3852 }
3853 batch_obj->pending_read_domains |= I915_GEM_DOMAIN_COMMAND;
673a394b 3854
83d60795
CW		 3855 /* Sanity check the batch buffer, prior to moving objects */
3856 exec_offset = exec_list[args->buffer_count - 1].offset;
3857 ret = i915_gem_check_execbuffer (args, exec_offset);
3858 if (ret != 0) {
3859 DRM_ERROR("execbuf with invalid offset/length\n");
3860 goto err;
3861 }
3862
646f0f6e
KP		 3863 /* Zero the global flush/invalidate flags. These
3864 * will be modified as new domains are computed
3865 * for each object
3866 */
3867 dev->invalidate_domains = 0;
3868 dev->flush_domains = 0;
9220434a 3869 dev_priv->mm.flush_rings = 0;
646f0f6e 3870
673a394b
EA		 3871 for (i = 0; i < args->buffer_count; i++) {
3872 struct drm_gem_object *obj = object_list[i];
673a394b 3873
646f0f6e 3874 /* Compute new gpu domains and update invalidate/flush */
8b0e378a 3875 i915_gem_object_set_to_gpu_domain(obj);
673a394b
EA		 3876 }
3877
646f0f6e
KP		 3878 if (dev->invalidate_domains | dev->flush_domains) {
3879#if WATCH_EXEC
3880 DRM_INFO("%s: invalidate_domains %08x flush_domains %08x\n",
3881 __func__,
3882 dev->invalidate_domains,
3883 dev->flush_domains);
3884#endif
c78ec30b 3885 i915_gem_flush(dev, file_priv,
646f0f6e 3886 dev->invalidate_domains,
9220434a
CW		 3887 dev->flush_domains,
3888 dev_priv->mm.flush_rings);
a6910434
DV		 3889 }
3890
efbeed96
EA		 3891 for (i = 0; i < args->buffer_count; i++) {
3892 struct drm_gem_object *obj = object_list[i];
23010e43 3893 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1c5d22f7 3894 uint32_t old_write_domain = obj->write_domain;
efbeed96
EA		 3895
3896 obj->write_domain = obj->pending_write_domain;
99fcb766
DV		 3897 if (obj->write_domain)
3898 list_move_tail(&obj_priv->gpu_write_list,
3899 &dev_priv->mm.gpu_write_list);
99fcb766 3900
1c5d22f7
CW		 3901 trace_i915_gem_object_change_domain(obj,
3902 obj->read_domains,
3903 old_write_domain);
efbeed96
EA		 3904 }
3905
673a394b
EA		 3906#if WATCH_COHERENCY
3907 for (i = 0; i < args->buffer_count; i++) {
3908 i915_gem_object_check_coherency(object_list[i],
3909 exec_list[i].handle);
3910 }
3911#endif
3912
673a394b 3913#if WATCH_EXEC
6911a9b8 3914 i915_gem_dump_object(batch_obj,
673a394b
EA		 3915 args->batch_len,
3916 __func__,
3917 ~0);
3918#endif
3919
673a394b 3920 /* Exec the batchbuffer */
852835f3
ZN		 3921 ret = ring->dispatch_gem_execbuffer(dev, ring, args,
3922 cliprects, exec_offset);
673a394b
EA		 3923 if (ret) {
3924 DRM_ERROR("dispatch failed %d\n", ret);
3925 goto err;
3926 }
3927
3928 /*
3929 * Ensure that the commands in the batch buffer are
3930 * finished before the interrupt fires
3931 */
8a1a49f9 3932 i915_retire_commands(dev, ring);
673a394b 3933
617dbe27
DV		 3934 for (i = 0; i < args->buffer_count; i++) {
3935 struct drm_gem_object *obj = object_list[i];
3936 obj_priv = to_intel_bo(obj);
3937
3938 i915_gem_object_move_to_active(obj, ring);
617dbe27 3939 }
a56ba56c 3940
5c12a07e 3941 i915_add_request(dev, file_priv, request, ring);
8dc5d147 3942 request = NULL;
673a394b 3943
673a394b 3944err:
aad87dff
JL		 3945 for (i = 0; i < pinned; i++)
3946 i915_gem_object_unpin(object_list[i]);
3947
b70d11da
KH		 3948 for (i = 0; i < args->buffer_count; i++) {
3949 if (object_list[i]) {
23010e43 3950 obj_priv = to_intel_bo(object_list[i]);
b70d11da
KH		 3951 obj_priv->in_execbuffer = false;
3952 }
aad87dff 3953 drm_gem_object_unreference(object_list[i]);
b70d11da 3954 }
673a394b 3955
673a394b
EA		 3956 mutex_unlock(&dev->struct_mutex);
3957
93533c29 3958pre_mutex_err:
40a5f0de
EA		 3959 /* Copy the updated relocations out regardless of current error
3960 * state. Failure to update the relocs would mean that the next
3961 * time userland calls execbuf, it would do so with presumed offset
3962 * state that didn't match the actual object state.
3963 */
3964 ret2 = i915_gem_put_relocs_to_user(exec_list, args->buffer_count,
3965 relocs);
3966 if (ret2 != 0) {
3967 DRM_ERROR("Failed to copy relocations back out: %d\n", ret2);
3968
3969 if (ret == 0)
3970 ret = ret2;
3971 }
3972
8e7d2b2c 3973 drm_free_large(object_list);
9a298b2a 3974 kfree(cliprects);
8dc5d147 3975 kfree(request);
673a394b
EA		 3976
3977 return ret;
3978}
3979
76446cac
JB		 3980/*
3981 * Legacy execbuffer just creates an exec2 list from the original exec object
3982 * list array and passes it to the real function.
3983 */
3984int
3985i915_gem_execbuffer(struct drm_device *dev, void *data,
3986 struct drm_file *file_priv)
3987{
3988 struct drm_i915_gem_execbuffer *args = data;
3989 struct drm_i915_gem_execbuffer2 exec2;
3990 struct drm_i915_gem_exec_object *exec_list = NULL;
3991 struct drm_i915_gem_exec_object2 *exec2_list = NULL;
3992 int ret, i;
3993
3994#if WATCH_EXEC
3995 DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n",
3996 (int) args->buffers_ptr, args->buffer_count, args->batch_len);
3997#endif
3998
3999 if (args->buffer_count < 1) {
4000 DRM_ERROR("execbuf with %d buffers\n", args->buffer_count);
4001 return -EINVAL;
4002 }
4003
4004 /* Copy in the exec list from userland */
4005 exec_list = drm_malloc_ab(sizeof(*exec_list), args->buffer_count);
4006 exec2_list = drm_malloc_ab(sizeof(*exec2_list), args->buffer_count);
4007 if (exec_list == NULL || exec2_list == NULL) {
4008 DRM_ERROR("Failed to allocate exec list for %d buffers\n",
4009 args->buffer_count);
4010 drm_free_large(exec_list);
4011 drm_free_large(exec2_list);
4012 return -ENOMEM;
4013 }
4014 ret = copy_from_user(exec_list,
4015 (struct drm_i915_relocation_entry __user *)
4016 (uintptr_t) args->buffers_ptr,
4017 sizeof(*exec_list) * args->buffer_count);
4018 if (ret != 0) {
4019 DRM_ERROR("copy %d exec entries failed %d\n",
4020 args->buffer_count, ret);
4021 drm_free_large(exec_list);
4022 drm_free_large(exec2_list);
4023 return -EFAULT;
4024 }
4025
4026 for (i = 0; i < args->buffer_count; i++) {
4027 exec2_list[i].handle = exec_list[i].handle;
4028 exec2_list[i].relocation_count = exec_list[i].relocation_count;
4029 exec2_list[i].relocs_ptr = exec_list[i].relocs_ptr;
4030 exec2_list[i].alignment = exec_list[i].alignment;
4031 exec2_list[i].offset = exec_list[i].offset;
a6c45cf0 4032 if (INTEL_INFO(dev)->gen < 4)
76446cac
JB		 4033 exec2_list[i].flags = EXEC_OBJECT_NEEDS_FENCE;
4034 else
4035 exec2_list[i].flags = 0;
4036 }
4037
4038 exec2.buffers_ptr = args->buffers_ptr;
4039 exec2.buffer_count = args->buffer_count;
4040 exec2.batch_start_offset = args->batch_start_offset;
4041 exec2.batch_len = args->batch_len;
4042 exec2.DR1 = args->DR1;
4043 exec2.DR4 = args->DR4;
4044 exec2.num_cliprects = args->num_cliprects;
4045 exec2.cliprects_ptr = args->cliprects_ptr;
852835f3 4046 exec2.flags = I915_EXEC_RENDER;
76446cac
JB		 4047
4048 ret = i915_gem_do_execbuffer(dev, data, file_priv, &exec2, exec2_list);
4049 if (!ret) {
4050 /* Copy the new buffer offsets back to the user's exec list. */
4051 for (i = 0; i < args->buffer_count; i++)
4052 exec_list[i].offset = exec2_list[i].offset;
4053 /* ... and back out to userspace */
4054 ret = copy_to_user((struct drm_i915_relocation_entry __user *)
4055 (uintptr_t) args->buffers_ptr,
4056 exec_list,
4057 sizeof(*exec_list) * args->buffer_count);
4058 if (ret) {
4059 ret = -EFAULT;
4060 DRM_ERROR("failed to copy %d exec entries "
4061 "back to user (%d)\n",
4062 args->buffer_count, ret);
4063 }
76446cac
JB		 4064 }
4065
4066 drm_free_large(exec_list);
4067 drm_free_large(exec2_list);
4068 return ret;
4069}
4070
4071int
4072i915_gem_execbuffer2(struct drm_device *dev, void *data,
4073 struct drm_file *file_priv)
4074{
4075 struct drm_i915_gem_execbuffer2 *args = data;
4076 struct drm_i915_gem_exec_object2 *exec2_list = NULL;
4077 int ret;
4078
4079#if WATCH_EXEC
4080 DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n",
4081 (int) args->buffers_ptr, args->buffer_count, args->batch_len);
4082#endif
4083
4084 if (args->buffer_count < 1) {
4085 DRM_ERROR("execbuf2 with %d buffers\n", args->buffer_count);
4086 return -EINVAL;
4087 }
4088
4089 exec2_list = drm_malloc_ab(sizeof(*exec2_list), args->buffer_count);
4090 if (exec2_list == NULL) {
4091 DRM_ERROR("Failed to allocate exec list for %d buffers\n",
4092 args->buffer_count);
4093 return -ENOMEM;
4094 }
4095 ret = copy_from_user(exec2_list,
4096 (struct drm_i915_relocation_entry __user *)
4097 (uintptr_t) args->buffers_ptr,
4098 sizeof(*exec2_list) * args->buffer_count);
4099 if (ret != 0) {
4100 DRM_ERROR("copy %d exec entries failed %d\n",
4101 args->buffer_count, ret);
4102 drm_free_large(exec2_list);
4103 return -EFAULT;
4104 }
4105
4106 ret = i915_gem_do_execbuffer(dev, data, file_priv, args, exec2_list);
4107 if (!ret) {
4108 /* Copy the new buffer offsets back to the user's exec list. */
4109 ret = copy_to_user((struct drm_i915_relocation_entry __user *)
4110 (uintptr_t) args->buffers_ptr,
4111 exec2_list,
4112 sizeof(*exec2_list) * args->buffer_count);
4113 if (ret) {
4114 ret = -EFAULT;
4115 DRM_ERROR("failed to copy %d exec entries "
4116 "back to user (%d)\n",
4117 args->buffer_count, ret);
4118 }
4119 }
4120
4121 drm_free_large(exec2_list);
4122 return ret;
4123}
4124
673a394b
EA		 4125int
4126i915_gem_object_pin(struct drm_gem_object *obj, uint32_t alignment)
4127{
4128 struct drm_device *dev = obj->dev;
f13d3f73 4129 struct drm_i915_private *dev_priv = dev->dev_private;
23010e43 4130 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
673a394b
EA		 4131 int ret;
4132
778c3544 4133 BUG_ON(obj_priv->pin_count == DRM_I915_GEM_OBJECT_MAX_PIN_COUNT);
23bc5982 4134 WARN_ON(i915_verify_lists(dev));
ac0c6b5a
CW		 4135
4136 if (obj_priv->gtt_space != NULL) {
4137 if (alignment == 0)
4138 alignment = i915_gem_get_gtt_alignment(obj);
4139 if (obj_priv->gtt_offset & (alignment - 1)) {
ae7d49d8
CW		 4140 WARN(obj_priv->pin_count,
4141 "bo is already pinned with incorrect alignment:"
4142 " offset=%x, req.alignment=%x\n",
4143 obj_priv->gtt_offset, alignment);
ac0c6b5a
CW		 4144 ret = i915_gem_object_unbind(obj);
4145 if (ret)
4146 return ret;
4147 }
4148 }
4149
673a394b
EA		 4150 if (obj_priv->gtt_space == NULL) {
4151 ret = i915_gem_object_bind_to_gtt(obj, alignment);
9731129c 4152 if (ret)
673a394b 4153 return ret;
22c344e9 4154 }
76446cac 4155
673a394b
EA		 4156 obj_priv->pin_count++;
4157
4158 /* If the object is not active and not pending a flush,
4159 * remove it from the inactive list
4160 */
4161 if (obj_priv->pin_count == 1) {
73aa808f 4162 i915_gem_info_add_pin(dev_priv, obj->size);
f13d3f73
CW		 4163 if (!obj_priv->active)
4164 list_move_tail(&obj_priv->list,
4165 &dev_priv->mm.pinned_list);
673a394b 4166 }
673a394b 4167
23bc5982 4168 WARN_ON(i915_verify_lists(dev));
673a394b
EA		 4169 return 0;
4170}
4171
4172void
4173i915_gem_object_unpin(struct drm_gem_object *obj)
4174{
4175 struct drm_device *dev = obj->dev;
4176 drm_i915_private_t *dev_priv = dev->dev_private;
23010e43 4177 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
673a394b 4178
23bc5982 4179 WARN_ON(i915_verify_lists(dev));
673a394b
EA		 4180 obj_priv->pin_count--;
4181 BUG_ON(obj_priv->pin_count < 0);
4182 BUG_ON(obj_priv->gtt_space == NULL);
4183
4184 /* If the object is no longer pinned, and is
4185 * neither active nor being flushed, then stick it on
4186 * the inactive list
4187 */
4188 if (obj_priv->pin_count == 0) {
f13d3f73 4189 if (!obj_priv->active)
673a394b
EA		 4190 list_move_tail(&obj_priv->list,
4191 &dev_priv->mm.inactive_list);
73aa808f 4192 i915_gem_info_remove_pin(dev_priv, obj->size);
673a394b 4193 }
23bc5982 4194 WARN_ON(i915_verify_lists(dev));
673a394b
EA		 4195}
4196
4197int
4198i915_gem_pin_ioctl(struct drm_device *dev, void *data,
4199 struct drm_file *file_priv)
4200{
4201 struct drm_i915_gem_pin *args = data;
4202 struct drm_gem_object *obj;
4203 struct drm_i915_gem_object *obj_priv;
4204 int ret;
4205
673a394b
EA		 4206 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
4207 if (obj == NULL) {
4208 DRM_ERROR("Bad handle in i915_gem_pin_ioctl(): %d\n",
4209 args->handle);
bf79cb91 4210 return -ENOENT;
673a394b 4211 }
23010e43 4212 obj_priv = to_intel_bo(obj);
673a394b 4213
76c1dec1
CW		 4214 ret = i915_mutex_lock_interruptible(dev);
4215 if (ret) {
4216 drm_gem_object_unreference_unlocked(obj);
4217 return ret;
4218 }
4219
bb6baf76
CW		 4220 if (obj_priv->madv != I915_MADV_WILLNEED) {
4221 DRM_ERROR("Attempting to pin a purgeable buffer\n");
3ef94daa
CW		 4222 drm_gem_object_unreference(obj);
4223 mutex_unlock(&dev->struct_mutex);
4224 return -EINVAL;
4225 }
4226
79e53945
JB		 4227 if (obj_priv->pin_filp != NULL && obj_priv->pin_filp != file_priv) {
4228 DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n",
4229 args->handle);
96dec61d 4230 drm_gem_object_unreference(obj);
673a394b 4231 mutex_unlock(&dev->struct_mutex);
79e53945
JB		 4232 return -EINVAL;
4233 }
4234
4235 obj_priv->user_pin_count++;
4236 obj_priv->pin_filp = file_priv;
4237 if (obj_priv->user_pin_count == 1) {
4238 ret = i915_gem_object_pin(obj, args->alignment);
4239 if (ret != 0) {
4240 drm_gem_object_unreference(obj);
4241 mutex_unlock(&dev->struct_mutex);
4242 return ret;
4243 }
673a394b
EA		 4244 }
4245
4246 /* XXX - flush the CPU caches for pinned objects
4247 * as the X server doesn't manage domains yet
4248 */
e47c68e9 4249 i915_gem_object_flush_cpu_write_domain(obj);
673a394b
EA		 4250 args->offset = obj_priv->gtt_offset;
4251 drm_gem_object_unreference(obj);
4252 mutex_unlock(&dev->struct_mutex);
4253
4254 return 0;
4255}
4256
4257int
4258i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
4259 struct drm_file *file_priv)
4260{
4261 struct drm_i915_gem_pin *args = data;
4262 struct drm_gem_object *obj;
79e53945 4263 struct drm_i915_gem_object *obj_priv;
76c1dec1 4264 int ret;
673a394b
EA		 4265
4266 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
4267 if (obj == NULL) {
4268 DRM_ERROR("Bad handle in i915_gem_unpin_ioctl(): %d\n",
4269 args->handle);
bf79cb91 4270 return -ENOENT;
673a394b
EA		 4271 }
4272
23010e43 4273 obj_priv = to_intel_bo(obj);
76c1dec1
CW		 4274
4275 ret = i915_mutex_lock_interruptible(dev);
4276 if (ret) {
4277 drm_gem_object_unreference_unlocked(obj);
4278 return ret;
4279 }
4280
79e53945
JB		 4281 if (obj_priv->pin_filp != file_priv) {
4282 DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n",
4283 args->handle);
4284 drm_gem_object_unreference(obj);
4285 mutex_unlock(&dev->struct_mutex);
4286 return -EINVAL;
4287 }
4288 obj_priv->user_pin_count--;
4289 if (obj_priv->user_pin_count == 0) {
4290 obj_priv->pin_filp = NULL;
4291 i915_gem_object_unpin(obj);
4292 }
673a394b
EA		 4293
4294 drm_gem_object_unreference(obj);
4295 mutex_unlock(&dev->struct_mutex);
4296 return 0;
4297}
4298
4299int
4300i915_gem_busy_ioctl(struct drm_device *dev, void *data,
4301 struct drm_file *file_priv)
4302{
4303 struct drm_i915_gem_busy *args = data;
4304 struct drm_gem_object *obj;
4305 struct drm_i915_gem_object *obj_priv;
30dbf0c0
CW		 4306 int ret;
4307
673a394b
EA		 4308 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
4309 if (obj == NULL) {
4310 DRM_ERROR("Bad handle in i915_gem_busy_ioctl(): %d\n",
4311 args->handle);
bf79cb91 4312 return -ENOENT;
673a394b
EA		 4313 }
4314
76c1dec1
CW		 4315 ret = i915_mutex_lock_interruptible(dev);
4316 if (ret) {
4317 drm_gem_object_unreference_unlocked(obj);
4318 return ret;
30dbf0c0
CW		 4319 }
4320
0be555b6
CW		 4321 /* Count all active objects as busy, even if they are currently not used
4322 * by the gpu. Users of this interface expect objects to eventually
4323 * become non-busy without any further actions, therefore emit any
4324 * necessary flushes here.
c4de0a5d 4325 */
0be555b6
CW		 4326 obj_priv = to_intel_bo(obj);
4327 args->busy = obj_priv->active;
4328 if (args->busy) {
4329 /* Unconditionally flush objects, even when the gpu still uses this
4330 * object. Userspace calling this function indicates that it wants to
4331 * use this buffer rather sooner than later, so issuing the required
4332 * flush earlier is beneficial.
4333 */
c78ec30b
CW		 4334 if (obj->write_domain & I915_GEM_GPU_DOMAINS)
4335 i915_gem_flush_ring(dev, file_priv,
9220434a
CW		 4336 obj_priv->ring,
4337 0, obj->write_domain);
0be555b6
CW		 4338
4339 /* Update the active list for the hardware's current position.
4340 * Otherwise this only updates on a delayed timer or when irqs
4341 * are actually unmasked, and our working set ends up being
4342 * larger than required.
4343 */
4344 i915_gem_retire_requests_ring(dev, obj_priv->ring);
4345
4346 args->busy = obj_priv->active;
4347 }
673a394b
EA		 4348
4349 drm_gem_object_unreference(obj);
4350 mutex_unlock(&dev->struct_mutex);
76c1dec1 4351 return 0;
673a394b
EA		 4352}
4353
4354int
4355i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
4356 struct drm_file *file_priv)
4357{
4358 return i915_gem_ring_throttle(dev, file_priv);
4359}
4360
3ef94daa
CW		 4361int
4362i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
4363 struct drm_file *file_priv)
4364{
4365 struct drm_i915_gem_madvise *args = data;
4366 struct drm_gem_object *obj;
4367 struct drm_i915_gem_object *obj_priv;
76c1dec1 4368 int ret;
3ef94daa
CW		 4369
4370 switch (args->madv) {
4371 case I915_MADV_DONTNEED:
4372 case I915_MADV_WILLNEED:
4373 break;
4374 default:
4375 return -EINVAL;
4376 }
4377
4378 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
4379 if (obj == NULL) {
4380 DRM_ERROR("Bad handle in i915_gem_madvise_ioctl(): %d\n",
4381 args->handle);
bf79cb91 4382 return -ENOENT;
3ef94daa 4383 }
23010e43 4384 obj_priv = to_intel_bo(obj);
3ef94daa 4385
76c1dec1
CW		 4386 ret = i915_mutex_lock_interruptible(dev);
4387 if (ret) {
4388 drm_gem_object_unreference_unlocked(obj);
4389 return ret;
4390 }
4391
3ef94daa
CW		 4392 if (obj_priv->pin_count) {
4393 drm_gem_object_unreference(obj);
4394 mutex_unlock(&dev->struct_mutex);
4395
4396 DRM_ERROR("Attempted i915_gem_madvise_ioctl() on a pinned object\n");
4397 return -EINVAL;
4398 }
4399
bb6baf76
CW		 4400 if (obj_priv->madv != __I915_MADV_PURGED)
4401 obj_priv->madv = args->madv;
3ef94daa 4402
2d7ef395
CW		 4403 /* if the object is no longer bound, discard its backing storage */
4404 if (i915_gem_object_is_purgeable(obj_priv) &&
4405 obj_priv->gtt_space == NULL)
4406 i915_gem_object_truncate(obj);
4407
bb6baf76
CW		 4408 args->retained = obj_priv->madv != __I915_MADV_PURGED;
4409
3ef94daa
CW		 4410 drm_gem_object_unreference(obj);
4411 mutex_unlock(&dev->struct_mutex);
4412
4413 return 0;
4414}
4415
ac52bc56
DV		 4416struct drm_gem_object * i915_gem_alloc_object(struct drm_device *dev,
4417 size_t size)
4418{
73aa808f 4419 struct drm_i915_private *dev_priv = dev->dev_private;
c397b908 4420 struct drm_i915_gem_object *obj;
ac52bc56 4421
c397b908
DV		 4422 obj = kzalloc(sizeof(*obj), GFP_KERNEL);
4423 if (obj == NULL)
4424 return NULL;
673a394b 4425
c397b908
DV		 4426 if (drm_gem_object_init(dev, &obj->base, size) != 0) {
4427 kfree(obj);
4428 return NULL;
4429 }
673a394b 4430
73aa808f
CW		 4431 i915_gem_info_add_obj(dev_priv, size);
4432
c397b908
DV		 4433 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
4434 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
673a394b 4435
c397b908 4436 obj->agp_type = AGP_USER_MEMORY;
62b8b215 4437 obj->base.driver_private = NULL;
c397b908
DV		 4438 obj->fence_reg = I915_FENCE_REG_NONE;
4439 INIT_LIST_HEAD(&obj->list);
4440 INIT_LIST_HEAD(&obj->gpu_write_list);
c397b908 4441 obj->madv = I915_MADV_WILLNEED;
de151cf6 4442
c397b908
DV		 4443 trace_i915_gem_object_create(&obj->base);
4444
4445 return &obj->base;
4446}
4447
4448int i915_gem_init_object(struct drm_gem_object *obj)
4449{
4450 BUG();
de151cf6 4451
673a394b
EA		 4452 return 0;
4453}
4454
be72615b 4455static void i915_gem_free_object_tail(struct drm_gem_object *obj)
673a394b 4456{
de151cf6 4457 struct drm_device *dev = obj->dev;
be72615b 4458 drm_i915_private_t *dev_priv = dev->dev_private;
23010e43 4459 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
be72615b 4460 int ret;
673a394b 4461
be72615b
CW		 4462 ret = i915_gem_object_unbind(obj);
4463 if (ret == -ERESTARTSYS) {
4464 list_move(&obj_priv->list,
4465 &dev_priv->mm.deferred_free_list);
4466 return;
4467 }
673a394b 4468
7e616158
CW		 4469 if (obj_priv->mmap_offset)
4470 i915_gem_free_mmap_offset(obj);
de151cf6 4471
c397b908 4472 drm_gem_object_release(obj);
73aa808f 4473 i915_gem_info_remove_obj(dev_priv, obj->size);
c397b908 4474
9a298b2a 4475 kfree(obj_priv->page_cpu_valid);
280b713b 4476 kfree(obj_priv->bit_17);
c397b908 4477 kfree(obj_priv);
673a394b
EA		 4478}
4479
be72615b
CW		 4480void i915_gem_free_object(struct drm_gem_object *obj)
4481{
4482 struct drm_device *dev = obj->dev;
4483 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
4484
4485 trace_i915_gem_object_destroy(obj);
4486
4487 while (obj_priv->pin_count > 0)
4488 i915_gem_object_unpin(obj);
4489
4490 if (obj_priv->phys_obj)
4491 i915_gem_detach_phys_object(dev, obj);
4492
4493 i915_gem_free_object_tail(obj);
4494}
4495
29105ccc
CW		 4496int
4497i915_gem_idle(struct drm_device *dev)
4498{
4499 drm_i915_private_t *dev_priv = dev->dev_private;
4500 int ret;
28dfe52a 4501
29105ccc 4502 mutex_lock(&dev->struct_mutex);
1c5d22f7 4503
8187a2b7 4504 if (dev_priv->mm.suspended ||
d1b851fc
ZN		 4505 (dev_priv->render_ring.gem_object == NULL) ||
4506 (HAS_BSD(dev) &&
4507 dev_priv->bsd_ring.gem_object == NULL)) {
29105ccc
CW		 4508 mutex_unlock(&dev->struct_mutex);
4509 return 0;
28dfe52a
EA		 4510 }
4511
29105ccc 4512 ret = i915_gpu_idle(dev);
6dbe2772
KP		 4513 if (ret) {
4514 mutex_unlock(&dev->struct_mutex);
673a394b 4515 return ret;
6dbe2772 4516 }
673a394b 4517
29105ccc
CW		 4518 /* Under UMS, be paranoid and evict. */
4519 if (!drm_core_check_feature(dev, DRIVER_MODESET)) {
b47eb4a2 4520 ret = i915_gem_evict_inactive(dev);
29105ccc
CW		 4521 if (ret) {
4522 mutex_unlock(&dev->struct_mutex);
4523 return ret;
4524 }
4525 }
4526
4527 /* Hack! Don't let anybody do execbuf while we don't control the chip.
4528 * We need to replace this with a semaphore, or something.
4529 * And not confound mm.suspended!
4530 */
4531 dev_priv->mm.suspended = 1;
bc0c7f14 4532 del_timer_sync(&dev_priv->hangcheck_timer);
29105ccc
CW		 4533
4534 i915_kernel_lost_context(dev);
6dbe2772 4535 i915_gem_cleanup_ringbuffer(dev);
29105ccc 4536
6dbe2772
KP		 4537 mutex_unlock(&dev->struct_mutex);
4538
29105ccc
CW		 4539 /* Cancel the retire work handler, which should be idle now. */
4540 cancel_delayed_work_sync(&dev_priv->mm.retire_work);
4541
673a394b
EA		 4542 return 0;
4543}
4544
e552eb70
JB		 4545/*
4546 * 965+ support PIPE_CONTROL commands, which provide finer grained control
4547 * over cache flushing.
4548 */
8187a2b7 4549static int
e552eb70
JB		 4550i915_gem_init_pipe_control(struct drm_device *dev)
4551{
4552 drm_i915_private_t *dev_priv = dev->dev_private;
4553 struct drm_gem_object *obj;
4554 struct drm_i915_gem_object *obj_priv;
4555 int ret;
4556
34dc4d44 4557 obj = i915_gem_alloc_object(dev, 4096);
e552eb70
JB		 4558 if (obj == NULL) {
4559 DRM_ERROR("Failed to allocate seqno page\n");
4560 ret = -ENOMEM;
4561 goto err;
4562 }
4563 obj_priv = to_intel_bo(obj);
4564 obj_priv->agp_type = AGP_USER_CACHED_MEMORY;
4565
4566 ret = i915_gem_object_pin(obj, 4096);
4567 if (ret)
4568 goto err_unref;
4569
4570 dev_priv->seqno_gfx_addr = obj_priv->gtt_offset;
4571 dev_priv->seqno_page = kmap(obj_priv->pages[0]);
4572 if (dev_priv->seqno_page == NULL)
4573 goto err_unpin;
4574
4575 dev_priv->seqno_obj = obj;
4576 memset(dev_priv->seqno_page, 0, PAGE_SIZE);
4577
4578 return 0;
4579
4580err_unpin:
4581 i915_gem_object_unpin(obj);
4582err_unref:
4583 drm_gem_object_unreference(obj);
4584err:
4585 return ret;
4586}
4587
8187a2b7
ZN		 4588
4589static void
e552eb70
JB		 4590i915_gem_cleanup_pipe_control(struct drm_device *dev)
4591{
4592 drm_i915_private_t *dev_priv = dev->dev_private;
4593 struct drm_gem_object *obj;
4594 struct drm_i915_gem_object *obj_priv;
4595
4596 obj = dev_priv->seqno_obj;
4597 obj_priv = to_intel_bo(obj);
4598 kunmap(obj_priv->pages[0]);
4599 i915_gem_object_unpin(obj);
4600 drm_gem_object_unreference(obj);
4601 dev_priv->seqno_obj = NULL;
4602
4603 dev_priv->seqno_page = NULL;
673a394b
EA		 4604}
4605
8187a2b7
ZN		 4606int
4607i915_gem_init_ringbuffer(struct drm_device *dev)
4608{
4609 drm_i915_private_t *dev_priv = dev->dev_private;
4610 int ret;
68f95ba9 4611
8187a2b7
ZN		 4612 if (HAS_PIPE_CONTROL(dev)) {
4613 ret = i915_gem_init_pipe_control(dev);
4614 if (ret)
4615 return ret;
4616 }
68f95ba9 4617
5c1143bb 4618 ret = intel_init_render_ring_buffer(dev);
68f95ba9
CW		 4619 if (ret)
4620 goto cleanup_pipe_control;
4621
4622 if (HAS_BSD(dev)) {
5c1143bb 4623 ret = intel_init_bsd_ring_buffer(dev);
68f95ba9
CW		 4624 if (ret)
4625 goto cleanup_render_ring;
d1b851fc 4626 }
68f95ba9 4627
6f392d54
CW		 4628 dev_priv->next_seqno = 1;
4629
68f95ba9
CW		 4630 return 0;
4631
4632cleanup_render_ring:
4633 intel_cleanup_ring_buffer(dev, &dev_priv->render_ring);
4634cleanup_pipe_control:
4635 if (HAS_PIPE_CONTROL(dev))
4636 i915_gem_cleanup_pipe_control(dev);
8187a2b7
ZN		 4637 return ret;
4638}
4639
4640void
4641i915_gem_cleanup_ringbuffer(struct drm_device *dev)
4642{
4643 drm_i915_private_t *dev_priv = dev->dev_private;
4644
4645 intel_cleanup_ring_buffer(dev, &dev_priv->render_ring);
d1b851fc
ZN		 4646 if (HAS_BSD(dev))
4647 intel_cleanup_ring_buffer(dev, &dev_priv->bsd_ring);
8187a2b7
ZN		 4648 if (HAS_PIPE_CONTROL(dev))
4649 i915_gem_cleanup_pipe_control(dev);
4650}
4651
673a394b
EA		 4652int
4653i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
4654 struct drm_file *file_priv)
4655{
4656 drm_i915_private_t *dev_priv = dev->dev_private;
4657 int ret;
4658
79e53945
JB		 4659 if (drm_core_check_feature(dev, DRIVER_MODESET))
4660 return 0;
4661
ba1234d1 4662 if (atomic_read(&dev_priv->mm.wedged)) {
673a394b 4663 DRM_ERROR("Reenabling wedged hardware, good luck\n");
ba1234d1 4664 atomic_set(&dev_priv->mm.wedged, 0);
673a394b
EA		 4665 }
4666
673a394b 4667 mutex_lock(&dev->struct_mutex);
9bb2d6f9
EA		 4668 dev_priv->mm.suspended = 0;
4669
4670 ret = i915_gem_init_ringbuffer(dev);
d816f6ac
WF		 4671 if (ret != 0) {
4672 mutex_unlock(&dev->struct_mutex);
9bb2d6f9 4673 return ret;
d816f6ac 4674 }
9bb2d6f9 4675
852835f3 4676 BUG_ON(!list_empty(&dev_priv->render_ring.active_list));
d1b851fc 4677 BUG_ON(HAS_BSD(dev) && !list_empty(&dev_priv->bsd_ring.active_list));
673a394b
EA		 4678 BUG_ON(!list_empty(&dev_priv->mm.flushing_list));
4679 BUG_ON(!list_empty(&dev_priv->mm.inactive_list));
852835f3 4680 BUG_ON(!list_empty(&dev_priv->render_ring.request_list));
d1b851fc 4681 BUG_ON(HAS_BSD(dev) && !list_empty(&dev_priv->bsd_ring.request_list));
673a394b 4682 mutex_unlock(&dev->struct_mutex);
dbb19d30 4683
5f35308b
CW		 4684 ret = drm_irq_install(dev);
4685 if (ret)
4686 goto cleanup_ringbuffer;
dbb19d30 4687
673a394b 4688 return 0;
5f35308b
CW		 4689
4690cleanup_ringbuffer:
4691 mutex_lock(&dev->struct_mutex);
4692 i915_gem_cleanup_ringbuffer(dev);
4693 dev_priv->mm.suspended = 1;
4694 mutex_unlock(&dev->struct_mutex);
4695
4696 return ret;
673a394b
EA		 4697}
4698
4699int
4700i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
4701 struct drm_file *file_priv)
4702{
79e53945
JB		 4703 if (drm_core_check_feature(dev, DRIVER_MODESET))
4704 return 0;
4705
dbb19d30 4706 drm_irq_uninstall(dev);
e6890f6f 4707 return i915_gem_idle(dev);
673a394b
EA		 4708}
4709
4710void
4711i915_gem_lastclose(struct drm_device *dev)
4712{
4713 int ret;
673a394b 4714
e806b495
EA		 4715 if (drm_core_check_feature(dev, DRIVER_MODESET))
4716 return;
4717
6dbe2772
KP		 4718 ret = i915_gem_idle(dev);
4719 if (ret)
4720 DRM_ERROR("failed to idle hardware: %d\n", ret);
673a394b
EA		 4721}
4722
4723void
4724i915_gem_load(struct drm_device *dev)
4725{
b5aa8a0f 4726 int i;
673a394b
EA		 4727 drm_i915_private_t *dev_priv = dev->dev_private;
4728
673a394b 4729 INIT_LIST_HEAD(&dev_priv->mm.flushing_list);
99fcb766 4730 INIT_LIST_HEAD(&dev_priv->mm.gpu_write_list);
673a394b 4731 INIT_LIST_HEAD(&dev_priv->mm.inactive_list);
f13d3f73 4732 INIT_LIST_HEAD(&dev_priv->mm.pinned_list);
a09ba7fa 4733 INIT_LIST_HEAD(&dev_priv->mm.fence_list);
be72615b 4734 INIT_LIST_HEAD(&dev_priv->mm.deferred_free_list);
852835f3
ZN		 4735 INIT_LIST_HEAD(&dev_priv->render_ring.active_list);
4736 INIT_LIST_HEAD(&dev_priv->render_ring.request_list);
d1b851fc
ZN		 4737 if (HAS_BSD(dev)) {
4738 INIT_LIST_HEAD(&dev_priv->bsd_ring.active_list);
4739 INIT_LIST_HEAD(&dev_priv->bsd_ring.request_list);
4740 }
007cc8ac
DV		 4741 for (i = 0; i < 16; i++)
4742 INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list);
673a394b
EA		 4743 INIT_DELAYED_WORK(&dev_priv->mm.retire_work,
4744 i915_gem_retire_work_handler);
30dbf0c0 4745 init_completion(&dev_priv->error_completion);
31169714
CW		 4746 spin_lock(&shrink_list_lock);
4747 list_add(&dev_priv->mm.shrink_list, &shrink_list);
4748 spin_unlock(&shrink_list_lock);
4749
94400120
DA		 4750 /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
4751 if (IS_GEN3(dev)) {
4752 u32 tmp = I915_READ(MI_ARB_STATE);
4753 if (!(tmp & MI_ARB_C3_LP_WRITE_ENABLE)) {
4754 /* arb state is a masked write, so set bit + bit in mask */
4755 tmp = MI_ARB_C3_LP_WRITE_ENABLE | (MI_ARB_C3_LP_WRITE_ENABLE << MI_ARB_MASK_SHIFT);
4756 I915_WRITE(MI_ARB_STATE, tmp);
4757 }
4758 }
4759
de151cf6 4760 /* Old X drivers will take 0-2 for front, back, depth buffers */
b397c836
EA		 4761 if (!drm_core_check_feature(dev, DRIVER_MODESET))
4762 dev_priv->fence_reg_start = 3;
de151cf6 4763
a6c45cf0 4764 if (INTEL_INFO(dev)->gen >= 4 || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
de151cf6
JB		 4765 dev_priv->num_fence_regs = 16;
4766 else
4767 dev_priv->num_fence_regs = 8;
4768
b5aa8a0f 4769 /* Initialize fence registers to zero */
a6c45cf0
CW		 4770 switch (INTEL_INFO(dev)->gen) {
4771 case 6:
4772 for (i = 0; i < 16; i++)
4773 I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + (i * 8), 0);
4774 break;
4775 case 5:
4776 case 4:
b5aa8a0f
GH		 4777 for (i = 0; i < 16; i++)
4778 I915_WRITE64(FENCE_REG_965_0 + (i * 8), 0);
a6c45cf0
CW		 4779 break;
4780 case 3:
b5aa8a0f
GH		 4781 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4782 for (i = 0; i < 8; i++)
4783 I915_WRITE(FENCE_REG_945_8 + (i * 4), 0);
a6c45cf0
CW		 4784 case 2:
4785 for (i = 0; i < 8; i++)
4786 I915_WRITE(FENCE_REG_830_0 + (i * 4), 0);
4787 break;
b5aa8a0f 4788 }
673a394b 4789 i915_gem_detect_bit_6_swizzle(dev);
6b95a207 4790 init_waitqueue_head(&dev_priv->pending_flip_queue);
673a394b 4791}
71acb5eb
DA		 4792
4793/*
4794 * Create a physically contiguous memory object for this object
4795 * e.g. for cursor + overlay regs
4796 */
995b6762
CW		 4797static int i915_gem_init_phys_object(struct drm_device *dev,
4798 int id, int size, int align)
71acb5eb
DA		 4799{
4800 drm_i915_private_t *dev_priv = dev->dev_private;
4801 struct drm_i915_gem_phys_object *phys_obj;
4802 int ret;
4803
4804 if (dev_priv->mm.phys_objs[id - 1] || !size)
4805 return 0;
4806
9a298b2a 4807 phys_obj = kzalloc(sizeof(struct drm_i915_gem_phys_object), GFP_KERNEL);
71acb5eb
DA		 4808 if (!phys_obj)
4809 return -ENOMEM;
4810
4811 phys_obj->id = id;
4812
6eeefaf3 4813 phys_obj->handle = drm_pci_alloc(dev, size, align);
71acb5eb
DA		 4814 if (!phys_obj->handle) {
4815 ret = -ENOMEM;
4816 goto kfree_obj;
4817 }
4818#ifdef CONFIG_X86
4819 set_memory_wc((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE);
4820#endif
4821
4822 dev_priv->mm.phys_objs[id - 1] = phys_obj;
4823
4824 return 0;
4825kfree_obj:
9a298b2a 4826 kfree(phys_obj);
71acb5eb
DA		 4827 return ret;
4828}
4829
995b6762 4830static void i915_gem_free_phys_object(struct drm_device *dev, int id)
71acb5eb
DA		 4831{
4832 drm_i915_private_t *dev_priv = dev->dev_private;
4833 struct drm_i915_gem_phys_object *phys_obj;
4834
4835 if (!dev_priv->mm.phys_objs[id - 1])
4836 return;
4837
4838 phys_obj = dev_priv->mm.phys_objs[id - 1];
4839 if (phys_obj->cur_obj) {
4840 i915_gem_detach_phys_object(dev, phys_obj->cur_obj);
4841 }
4842
4843#ifdef CONFIG_X86
4844 set_memory_wb((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE);
4845#endif
4846 drm_pci_free(dev, phys_obj->handle);
4847 kfree(phys_obj);
4848 dev_priv->mm.phys_objs[id - 1] = NULL;
4849}
4850
4851void i915_gem_free_all_phys_object(struct drm_device *dev)
4852{
4853 int i;
4854
260883c8 4855 for (i = I915_GEM_PHYS_CURSOR_0; i <= I915_MAX_PHYS_OBJECT; i++)
71acb5eb
DA		 4856 i915_gem_free_phys_object(dev, i);
4857}
4858
4859void i915_gem_detach_phys_object(struct drm_device *dev,
4860 struct drm_gem_object *obj)
4861{
4862 struct drm_i915_gem_object *obj_priv;
4863 int i;
4864 int ret;
4865 int page_count;
4866
23010e43 4867 obj_priv = to_intel_bo(obj);
71acb5eb
DA		 4868 if (!obj_priv->phys_obj)
4869 return;
4870
4bdadb97 4871 ret = i915_gem_object_get_pages(obj, 0);
71acb5eb
DA		 4872 if (ret)
4873 goto out;
4874
4875 page_count = obj->size / PAGE_SIZE;
4876
4877 for (i = 0; i < page_count; i++) {
856fa198 4878 char *dst = kmap_atomic(obj_priv->pages[i], KM_USER0);
71acb5eb
DA		 4879 char *src = obj_priv->phys_obj->handle->vaddr + (i * PAGE_SIZE);
4880
4881 memcpy(dst, src, PAGE_SIZE);
4882 kunmap_atomic(dst, KM_USER0);
4883 }
856fa198 4884 drm_clflush_pages(obj_priv->pages, page_count);
71acb5eb 4885 drm_agp_chipset_flush(dev);
d78b47b9
CW		 4886
4887 i915_gem_object_put_pages(obj);
71acb5eb
DA		 4888out:
4889 obj_priv->phys_obj->cur_obj = NULL;
4890 obj_priv->phys_obj = NULL;
4891}
4892
4893int
4894i915_gem_attach_phys_object(struct drm_device *dev,
6eeefaf3
CW		 4895 struct drm_gem_object *obj,
4896 int id,
4897 int align)
71acb5eb
DA		 4898{
4899 drm_i915_private_t *dev_priv = dev->dev_private;
4900 struct drm_i915_gem_object *obj_priv;
4901 int ret = 0;
4902 int page_count;
4903 int i;
4904
4905 if (id > I915_MAX_PHYS_OBJECT)
4906 return -EINVAL;
4907
23010e43 4908 obj_priv = to_intel_bo(obj);
71acb5eb
DA		 4909
4910 if (obj_priv->phys_obj) {
4911 if (obj_priv->phys_obj->id == id)
4912 return 0;
4913 i915_gem_detach_phys_object(dev, obj);
4914 }
4915
71acb5eb
DA		 4916 /* create a new object */
4917 if (!dev_priv->mm.phys_objs[id - 1]) {
4918 ret = i915_gem_init_phys_object(dev, id,
6eeefaf3 4919 obj->size, align);
71acb5eb 4920 if (ret) {
aeb565df 4921 DRM_ERROR("failed to init phys object %d size: %zu\n", id, obj->size);
71acb5eb
DA		 4922 goto out;
4923 }
4924 }
4925
4926 /* bind to the object */
4927 obj_priv->phys_obj = dev_priv->mm.phys_objs[id - 1];
4928 obj_priv->phys_obj->cur_obj = obj;
4929
4bdadb97 4930 ret = i915_gem_object_get_pages(obj, 0);
71acb5eb
DA		 4931 if (ret) {
4932 DRM_ERROR("failed to get page list\n");
4933 goto out;
4934 }
4935
4936 page_count = obj->size / PAGE_SIZE;
4937
4938 for (i = 0; i < page_count; i++) {
856fa198 4939 char *src = kmap_atomic(obj_priv->pages[i], KM_USER0);
71acb5eb
DA		 4940 char *dst = obj_priv->phys_obj->handle->vaddr + (i * PAGE_SIZE);
4941
4942 memcpy(dst, src, PAGE_SIZE);
4943 kunmap_atomic(src, KM_USER0);
4944 }
4945
d78b47b9
CW		 4946 i915_gem_object_put_pages(obj);
4947
71acb5eb
DA		 4948 return 0;
4949out:
4950 return ret;
4951}
4952
4953static int
4954i915_gem_phys_pwrite(struct drm_device *dev, struct drm_gem_object *obj,
4955 struct drm_i915_gem_pwrite *args,
4956 struct drm_file *file_priv)
4957{
23010e43 4958 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
71acb5eb
DA		 4959 void *obj_addr;
4960 int ret;
4961 char __user *user_data;
4962
4963 user_data = (char __user *) (uintptr_t) args->data_ptr;
4964 obj_addr = obj_priv->phys_obj->handle->vaddr + args->offset;
4965
44d98a61 4966 DRM_DEBUG_DRIVER("obj_addr %p, %lld\n", obj_addr, args->size);
71acb5eb
DA		 4967 ret = copy_from_user(obj_addr, user_data, args->size);
4968 if (ret)
4969 return -EFAULT;
4970
4971 drm_agp_chipset_flush(dev);
4972 return 0;
4973}
b962442e 4974
f787a5f5 4975void i915_gem_release(struct drm_device *dev, struct drm_file *file)
b962442e 4976{
f787a5f5 4977 struct drm_i915_file_private *file_priv = file->driver_priv;
b962442e
EA		 4978
4979 /* Clean up our request list when the client is going away, so that
4980 * later retire_requests won't dereference our soon-to-be-gone
4981 * file_priv.
4982 */
1c25595f 4983 spin_lock(&file_priv->mm.lock);
f787a5f5
CW		 4984 while (!list_empty(&file_priv->mm.request_list)) {
4985 struct drm_i915_gem_request *request;
4986
4987 request = list_first_entry(&file_priv->mm.request_list,
4988 struct drm_i915_gem_request,
4989 client_list);
4990 list_del(&request->client_list);
4991 request->file_priv = NULL;
4992 }
1c25595f 4993 spin_unlock(&file_priv->mm.lock);
b962442e 4994}
31169714 4995
1637ef41
CW		 4996static int
4997i915_gpu_is_active(struct drm_device *dev)
4998{
4999 drm_i915_private_t *dev_priv = dev->dev_private;
5000 int lists_empty;
5001
1637ef41 5002 lists_empty = list_empty(&dev_priv->mm.flushing_list) &&
852835f3 5003 list_empty(&dev_priv->render_ring.active_list);
d1b851fc
ZN		 5004 if (HAS_BSD(dev))
5005 lists_empty &= list_empty(&dev_priv->bsd_ring.active_list);
1637ef41
CW		 5006
5007 return !lists_empty;
5008}
5009
31169714 5010static int
7f8275d0 5011i915_gem_shrink(struct shrinker *shrink, int nr_to_scan, gfp_t gfp_mask)
31169714
CW		 5012{
5013 drm_i915_private_t *dev_priv, *next_dev;
5014 struct drm_i915_gem_object *obj_priv, *next_obj;
5015 int cnt = 0;
5016 int would_deadlock = 1;
5017
5018 /* "fast-path" to count number of available objects */
5019 if (nr_to_scan == 0) {
5020 spin_lock(&shrink_list_lock);
5021 list_for_each_entry(dev_priv, &shrink_list, mm.shrink_list) {
5022 struct drm_device *dev = dev_priv->dev;
5023
5024 if (mutex_trylock(&dev->struct_mutex)) {
5025 list_for_each_entry(obj_priv,
5026 &dev_priv->mm.inactive_list,
5027 list)
5028 cnt++;
5029 mutex_unlock(&dev->struct_mutex);
5030 }
5031 }
5032 spin_unlock(&shrink_list_lock);
5033
5034 return (cnt / 100) * sysctl_vfs_cache_pressure;
5035 }
5036
5037 spin_lock(&shrink_list_lock);
5038
1637ef41 5039rescan:
31169714
CW		 5040 /* first scan for clean buffers */
5041 list_for_each_entry_safe(dev_priv, next_dev,
5042 &shrink_list, mm.shrink_list) {
5043 struct drm_device *dev = dev_priv->dev;
5044
5045 if (! mutex_trylock(&dev->struct_mutex))
5046 continue;
5047
5048 spin_unlock(&shrink_list_lock);
b09a1fec 5049 i915_gem_retire_requests(dev);
31169714
CW		 5050
5051 list_for_each_entry_safe(obj_priv, next_obj,
5052 &dev_priv->mm.inactive_list,
5053 list) {
5054 if (i915_gem_object_is_purgeable(obj_priv)) {
a8089e84 5055 i915_gem_object_unbind(&obj_priv->base);
31169714
CW		 5056 if (--nr_to_scan <= 0)
5057 break;
5058 }
5059 }
5060
5061 spin_lock(&shrink_list_lock);
5062 mutex_unlock(&dev->struct_mutex);
5063
963b4836
CW		 5064 would_deadlock = 0;
5065
31169714
CW		 5066 if (nr_to_scan <= 0)
5067 break;
5068 }
5069
5070 /* second pass, evict/count anything still on the inactive list */
5071 list_for_each_entry_safe(dev_priv, next_dev,
5072 &shrink_list, mm.shrink_list) {
5073 struct drm_device *dev = dev_priv->dev;
5074
5075 if (! mutex_trylock(&dev->struct_mutex))
5076 continue;
5077
5078 spin_unlock(&shrink_list_lock);
5079
5080 list_for_each_entry_safe(obj_priv, next_obj,
5081 &dev_priv->mm.inactive_list,
5082 list) {
5083 if (nr_to_scan > 0) {
a8089e84 5084 i915_gem_object_unbind(&obj_priv->base);
31169714
CW		 5085 nr_to_scan--;
5086 } else
5087 cnt++;
5088 }
5089
5090 spin_lock(&shrink_list_lock);
5091 mutex_unlock(&dev->struct_mutex);
5092
5093 would_deadlock = 0;
5094 }
5095
1637ef41
CW		 5096 if (nr_to_scan) {
5097 int active = 0;
5098
5099 /*
5100 * We are desperate for pages, so as a last resort, wait
5101 * for the GPU to finish and discard whatever we can.
5102 * This has a dramatic impact to reduce the number of
5103 * OOM-killer events whilst running the GPU aggressively.
5104 */
5105 list_for_each_entry(dev_priv, &shrink_list, mm.shrink_list) {
5106 struct drm_device *dev = dev_priv->dev;
5107
5108 if (!mutex_trylock(&dev->struct_mutex))
5109 continue;
5110
5111 spin_unlock(&shrink_list_lock);
5112
5113 if (i915_gpu_is_active(dev)) {
5114 i915_gpu_idle(dev);
5115 active++;
5116 }
5117
5118 spin_lock(&shrink_list_lock);
5119 mutex_unlock(&dev->struct_mutex);
5120 }
5121
5122 if (active)
5123 goto rescan;
5124 }
5125
31169714
CW		 5126 spin_unlock(&shrink_list_lock);
5127
5128 if (would_deadlock)
5129 return -1;
5130 else if (cnt > 0)
5131 return (cnt / 100) * sysctl_vfs_cache_pressure;
5132 else
5133 return 0;
5134}
5135
5136static struct shrinker shrinker = {
5137 .shrink = i915_gem_shrink,
5138 .seeks = DEFAULT_SEEKS,
5139};
5140
5141__init void
5142i915_gem_shrinker_init(void)
5143{
5144 register_shrinker(&shrinker);
5145}
5146
5147__exit void
5148i915_gem_shrinker_exit(void)
5149{
5150 unregister_shrinker(&shrinker);
5151}
Ubuntu Focal Linux kernel mirror