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Commit | Line | Data |
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673a394b | 1 | /* |
be6a0376 | 2 | * Copyright © 2008-2015 Intel Corporation |
673a394b EA |
3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | * | |
26 | */ | |
27 | ||
760285e7 | 28 | #include <drm/drmP.h> |
0de23977 | 29 | #include <drm/drm_vma_manager.h> |
760285e7 | 30 | #include <drm/i915_drm.h> |
673a394b | 31 | #include "i915_drv.h" |
eb82289a | 32 | #include "i915_vgpu.h" |
1c5d22f7 | 33 | #include "i915_trace.h" |
652c393a | 34 | #include "intel_drv.h" |
5d723d7a | 35 | #include "intel_frontbuffer.h" |
0ccdacf6 | 36 | #include "intel_mocs.h" |
6b5e90f5 | 37 | #include <linux/dma-fence-array.h> |
c13d87ea | 38 | #include <linux/reservation.h> |
5949eac4 | 39 | #include <linux/shmem_fs.h> |
5a0e3ad6 | 40 | #include <linux/slab.h> |
673a394b | 41 | #include <linux/swap.h> |
79e53945 | 42 | #include <linux/pci.h> |
1286ff73 | 43 | #include <linux/dma-buf.h> |
673a394b | 44 | |
fbbd37b3 | 45 | static void i915_gem_flush_free_objects(struct drm_i915_private *i915); |
05394f39 | 46 | static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj); |
e62b59e4 | 47 | static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj); |
61050808 | 48 | |
c76ce038 CW |
49 | static bool cpu_cache_is_coherent(struct drm_device *dev, |
50 | enum i915_cache_level level) | |
51 | { | |
0031fb96 | 52 | return HAS_LLC(to_i915(dev)) || level != I915_CACHE_NONE; |
c76ce038 CW |
53 | } |
54 | ||
2c22569b CW |
55 | static bool cpu_write_needs_clflush(struct drm_i915_gem_object *obj) |
56 | { | |
b50a5371 AS |
57 | if (obj->base.write_domain == I915_GEM_DOMAIN_CPU) |
58 | return false; | |
59 | ||
2c22569b CW |
60 | if (!cpu_cache_is_coherent(obj->base.dev, obj->cache_level)) |
61 | return true; | |
62 | ||
63 | return obj->pin_display; | |
64 | } | |
65 | ||
4f1959ee | 66 | static int |
bb6dc8d9 | 67 | insert_mappable_node(struct i915_ggtt *ggtt, |
4f1959ee AS |
68 | struct drm_mm_node *node, u32 size) |
69 | { | |
70 | memset(node, 0, sizeof(*node)); | |
bb6dc8d9 CW |
71 | return drm_mm_insert_node_in_range_generic(&ggtt->base.mm, node, |
72 | size, 0, -1, | |
73 | 0, ggtt->mappable_end, | |
4f1959ee AS |
74 | DRM_MM_SEARCH_DEFAULT, |
75 | DRM_MM_CREATE_DEFAULT); | |
76 | } | |
77 | ||
78 | static void | |
79 | remove_mappable_node(struct drm_mm_node *node) | |
80 | { | |
81 | drm_mm_remove_node(node); | |
82 | } | |
83 | ||
73aa808f CW |
84 | /* some bookkeeping */ |
85 | static void i915_gem_info_add_obj(struct drm_i915_private *dev_priv, | |
3ef7f228 | 86 | u64 size) |
73aa808f | 87 | { |
c20e8355 | 88 | spin_lock(&dev_priv->mm.object_stat_lock); |
73aa808f CW |
89 | dev_priv->mm.object_count++; |
90 | dev_priv->mm.object_memory += size; | |
c20e8355 | 91 | spin_unlock(&dev_priv->mm.object_stat_lock); |
73aa808f CW |
92 | } |
93 | ||
94 | static void i915_gem_info_remove_obj(struct drm_i915_private *dev_priv, | |
3ef7f228 | 95 | u64 size) |
73aa808f | 96 | { |
c20e8355 | 97 | spin_lock(&dev_priv->mm.object_stat_lock); |
73aa808f CW |
98 | dev_priv->mm.object_count--; |
99 | dev_priv->mm.object_memory -= size; | |
c20e8355 | 100 | spin_unlock(&dev_priv->mm.object_stat_lock); |
73aa808f CW |
101 | } |
102 | ||
21dd3734 | 103 | static int |
33196ded | 104 | i915_gem_wait_for_error(struct i915_gpu_error *error) |
30dbf0c0 | 105 | { |
30dbf0c0 CW |
106 | int ret; |
107 | ||
4c7d62c6 CW |
108 | might_sleep(); |
109 | ||
d98c52cf | 110 | if (!i915_reset_in_progress(error)) |
30dbf0c0 CW |
111 | return 0; |
112 | ||
0a6759c6 DV |
113 | /* |
114 | * Only wait 10 seconds for the gpu reset to complete to avoid hanging | |
115 | * userspace. If it takes that long something really bad is going on and | |
116 | * we should simply try to bail out and fail as gracefully as possible. | |
117 | */ | |
1f83fee0 | 118 | ret = wait_event_interruptible_timeout(error->reset_queue, |
d98c52cf | 119 | !i915_reset_in_progress(error), |
b52992c0 | 120 | I915_RESET_TIMEOUT); |
0a6759c6 DV |
121 | if (ret == 0) { |
122 | DRM_ERROR("Timed out waiting for the gpu reset to complete\n"); | |
123 | return -EIO; | |
124 | } else if (ret < 0) { | |
30dbf0c0 | 125 | return ret; |
d98c52cf CW |
126 | } else { |
127 | return 0; | |
0a6759c6 | 128 | } |
30dbf0c0 CW |
129 | } |
130 | ||
54cf91dc | 131 | int i915_mutex_lock_interruptible(struct drm_device *dev) |
76c1dec1 | 132 | { |
fac5e23e | 133 | struct drm_i915_private *dev_priv = to_i915(dev); |
76c1dec1 CW |
134 | int ret; |
135 | ||
33196ded | 136 | ret = i915_gem_wait_for_error(&dev_priv->gpu_error); |
76c1dec1 CW |
137 | if (ret) |
138 | return ret; | |
139 | ||
140 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
141 | if (ret) | |
142 | return ret; | |
143 | ||
76c1dec1 CW |
144 | return 0; |
145 | } | |
30dbf0c0 | 146 | |
5a125c3c EA |
147 | int |
148 | i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 149 | struct drm_file *file) |
5a125c3c | 150 | { |
72e96d64 | 151 | struct drm_i915_private *dev_priv = to_i915(dev); |
62106b4f | 152 | struct i915_ggtt *ggtt = &dev_priv->ggtt; |
72e96d64 | 153 | struct drm_i915_gem_get_aperture *args = data; |
ca1543be | 154 | struct i915_vma *vma; |
6299f992 | 155 | size_t pinned; |
5a125c3c | 156 | |
6299f992 | 157 | pinned = 0; |
73aa808f | 158 | mutex_lock(&dev->struct_mutex); |
1c7f4bca | 159 | list_for_each_entry(vma, &ggtt->base.active_list, vm_link) |
20dfbde4 | 160 | if (i915_vma_is_pinned(vma)) |
ca1543be | 161 | pinned += vma->node.size; |
1c7f4bca | 162 | list_for_each_entry(vma, &ggtt->base.inactive_list, vm_link) |
20dfbde4 | 163 | if (i915_vma_is_pinned(vma)) |
ca1543be | 164 | pinned += vma->node.size; |
73aa808f | 165 | mutex_unlock(&dev->struct_mutex); |
5a125c3c | 166 | |
72e96d64 | 167 | args->aper_size = ggtt->base.total; |
0206e353 | 168 | args->aper_available_size = args->aper_size - pinned; |
6299f992 | 169 | |
5a125c3c EA |
170 | return 0; |
171 | } | |
172 | ||
03ac84f1 | 173 | static struct sg_table * |
6a2c4232 | 174 | i915_gem_object_get_pages_phys(struct drm_i915_gem_object *obj) |
00731155 | 175 | { |
93c76a3d | 176 | struct address_space *mapping = obj->base.filp->f_mapping; |
6a2c4232 CW |
177 | char *vaddr = obj->phys_handle->vaddr; |
178 | struct sg_table *st; | |
179 | struct scatterlist *sg; | |
180 | int i; | |
00731155 | 181 | |
6a2c4232 | 182 | if (WARN_ON(i915_gem_object_needs_bit17_swizzle(obj))) |
03ac84f1 | 183 | return ERR_PTR(-EINVAL); |
6a2c4232 CW |
184 | |
185 | for (i = 0; i < obj->base.size / PAGE_SIZE; i++) { | |
186 | struct page *page; | |
187 | char *src; | |
188 | ||
189 | page = shmem_read_mapping_page(mapping, i); | |
190 | if (IS_ERR(page)) | |
03ac84f1 | 191 | return ERR_CAST(page); |
6a2c4232 CW |
192 | |
193 | src = kmap_atomic(page); | |
194 | memcpy(vaddr, src, PAGE_SIZE); | |
195 | drm_clflush_virt_range(vaddr, PAGE_SIZE); | |
196 | kunmap_atomic(src); | |
197 | ||
09cbfeaf | 198 | put_page(page); |
6a2c4232 CW |
199 | vaddr += PAGE_SIZE; |
200 | } | |
201 | ||
c033666a | 202 | i915_gem_chipset_flush(to_i915(obj->base.dev)); |
6a2c4232 CW |
203 | |
204 | st = kmalloc(sizeof(*st), GFP_KERNEL); | |
205 | if (st == NULL) | |
03ac84f1 | 206 | return ERR_PTR(-ENOMEM); |
6a2c4232 CW |
207 | |
208 | if (sg_alloc_table(st, 1, GFP_KERNEL)) { | |
209 | kfree(st); | |
03ac84f1 | 210 | return ERR_PTR(-ENOMEM); |
6a2c4232 CW |
211 | } |
212 | ||
213 | sg = st->sgl; | |
214 | sg->offset = 0; | |
215 | sg->length = obj->base.size; | |
00731155 | 216 | |
6a2c4232 CW |
217 | sg_dma_address(sg) = obj->phys_handle->busaddr; |
218 | sg_dma_len(sg) = obj->base.size; | |
219 | ||
03ac84f1 | 220 | return st; |
6a2c4232 CW |
221 | } |
222 | ||
223 | static void | |
2b3c8317 CW |
224 | __i915_gem_object_release_shmem(struct drm_i915_gem_object *obj, |
225 | struct sg_table *pages) | |
6a2c4232 | 226 | { |
a4f5ea64 | 227 | GEM_BUG_ON(obj->mm.madv == __I915_MADV_PURGED); |
00731155 | 228 | |
a4f5ea64 CW |
229 | if (obj->mm.madv == I915_MADV_DONTNEED) |
230 | obj->mm.dirty = false; | |
6a2c4232 | 231 | |
05c34837 CW |
232 | if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0 && |
233 | !cpu_cache_is_coherent(obj->base.dev, obj->cache_level)) | |
2b3c8317 | 234 | drm_clflush_sg(pages); |
03ac84f1 CW |
235 | |
236 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; | |
237 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; | |
238 | } | |
239 | ||
240 | static void | |
241 | i915_gem_object_put_pages_phys(struct drm_i915_gem_object *obj, | |
242 | struct sg_table *pages) | |
243 | { | |
2b3c8317 | 244 | __i915_gem_object_release_shmem(obj, pages); |
03ac84f1 | 245 | |
a4f5ea64 | 246 | if (obj->mm.dirty) { |
93c76a3d | 247 | struct address_space *mapping = obj->base.filp->f_mapping; |
6a2c4232 | 248 | char *vaddr = obj->phys_handle->vaddr; |
00731155 CW |
249 | int i; |
250 | ||
251 | for (i = 0; i < obj->base.size / PAGE_SIZE; i++) { | |
6a2c4232 CW |
252 | struct page *page; |
253 | char *dst; | |
254 | ||
255 | page = shmem_read_mapping_page(mapping, i); | |
256 | if (IS_ERR(page)) | |
257 | continue; | |
258 | ||
259 | dst = kmap_atomic(page); | |
260 | drm_clflush_virt_range(vaddr, PAGE_SIZE); | |
261 | memcpy(dst, vaddr, PAGE_SIZE); | |
262 | kunmap_atomic(dst); | |
263 | ||
264 | set_page_dirty(page); | |
a4f5ea64 | 265 | if (obj->mm.madv == I915_MADV_WILLNEED) |
00731155 | 266 | mark_page_accessed(page); |
09cbfeaf | 267 | put_page(page); |
00731155 CW |
268 | vaddr += PAGE_SIZE; |
269 | } | |
a4f5ea64 | 270 | obj->mm.dirty = false; |
00731155 CW |
271 | } |
272 | ||
03ac84f1 CW |
273 | sg_free_table(pages); |
274 | kfree(pages); | |
6a2c4232 CW |
275 | } |
276 | ||
277 | static void | |
278 | i915_gem_object_release_phys(struct drm_i915_gem_object *obj) | |
279 | { | |
280 | drm_pci_free(obj->base.dev, obj->phys_handle); | |
a4f5ea64 | 281 | i915_gem_object_unpin_pages(obj); |
6a2c4232 CW |
282 | } |
283 | ||
284 | static const struct drm_i915_gem_object_ops i915_gem_phys_ops = { | |
285 | .get_pages = i915_gem_object_get_pages_phys, | |
286 | .put_pages = i915_gem_object_put_pages_phys, | |
287 | .release = i915_gem_object_release_phys, | |
288 | }; | |
289 | ||
35a9611c | 290 | int i915_gem_object_unbind(struct drm_i915_gem_object *obj) |
aa653a68 CW |
291 | { |
292 | struct i915_vma *vma; | |
293 | LIST_HEAD(still_in_list); | |
02bef8f9 CW |
294 | int ret; |
295 | ||
296 | lockdep_assert_held(&obj->base.dev->struct_mutex); | |
aa653a68 | 297 | |
02bef8f9 CW |
298 | /* Closed vma are removed from the obj->vma_list - but they may |
299 | * still have an active binding on the object. To remove those we | |
300 | * must wait for all rendering to complete to the object (as unbinding | |
301 | * must anyway), and retire the requests. | |
aa653a68 | 302 | */ |
e95433c7 CW |
303 | ret = i915_gem_object_wait(obj, |
304 | I915_WAIT_INTERRUPTIBLE | | |
305 | I915_WAIT_LOCKED | | |
306 | I915_WAIT_ALL, | |
307 | MAX_SCHEDULE_TIMEOUT, | |
308 | NULL); | |
02bef8f9 CW |
309 | if (ret) |
310 | return ret; | |
311 | ||
312 | i915_gem_retire_requests(to_i915(obj->base.dev)); | |
313 | ||
aa653a68 CW |
314 | while ((vma = list_first_entry_or_null(&obj->vma_list, |
315 | struct i915_vma, | |
316 | obj_link))) { | |
317 | list_move_tail(&vma->obj_link, &still_in_list); | |
318 | ret = i915_vma_unbind(vma); | |
319 | if (ret) | |
320 | break; | |
321 | } | |
322 | list_splice(&still_in_list, &obj->vma_list); | |
323 | ||
324 | return ret; | |
325 | } | |
326 | ||
e95433c7 CW |
327 | static long |
328 | i915_gem_object_wait_fence(struct dma_fence *fence, | |
329 | unsigned int flags, | |
330 | long timeout, | |
331 | struct intel_rps_client *rps) | |
00e60f26 | 332 | { |
e95433c7 | 333 | struct drm_i915_gem_request *rq; |
00e60f26 | 334 | |
e95433c7 | 335 | BUILD_BUG_ON(I915_WAIT_INTERRUPTIBLE != 0x1); |
00e60f26 | 336 | |
e95433c7 CW |
337 | if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &fence->flags)) |
338 | return timeout; | |
339 | ||
340 | if (!dma_fence_is_i915(fence)) | |
341 | return dma_fence_wait_timeout(fence, | |
342 | flags & I915_WAIT_INTERRUPTIBLE, | |
343 | timeout); | |
344 | ||
345 | rq = to_request(fence); | |
346 | if (i915_gem_request_completed(rq)) | |
347 | goto out; | |
348 | ||
349 | /* This client is about to stall waiting for the GPU. In many cases | |
350 | * this is undesirable and limits the throughput of the system, as | |
351 | * many clients cannot continue processing user input/output whilst | |
352 | * blocked. RPS autotuning may take tens of milliseconds to respond | |
353 | * to the GPU load and thus incurs additional latency for the client. | |
354 | * We can circumvent that by promoting the GPU frequency to maximum | |
355 | * before we wait. This makes the GPU throttle up much more quickly | |
356 | * (good for benchmarks and user experience, e.g. window animations), | |
357 | * but at a cost of spending more power processing the workload | |
358 | * (bad for battery). Not all clients even want their results | |
359 | * immediately and for them we should just let the GPU select its own | |
360 | * frequency to maximise efficiency. To prevent a single client from | |
361 | * forcing the clocks too high for the whole system, we only allow | |
362 | * each client to waitboost once in a busy period. | |
363 | */ | |
364 | if (rps) { | |
365 | if (INTEL_GEN(rq->i915) >= 6) | |
366 | gen6_rps_boost(rq->i915, rps, rq->emitted_jiffies); | |
367 | else | |
368 | rps = NULL; | |
00e60f26 CW |
369 | } |
370 | ||
e95433c7 CW |
371 | timeout = i915_wait_request(rq, flags, timeout); |
372 | ||
373 | out: | |
374 | if (flags & I915_WAIT_LOCKED && i915_gem_request_completed(rq)) | |
375 | i915_gem_request_retire_upto(rq); | |
376 | ||
cb399eab | 377 | if (rps && rq->global_seqno == intel_engine_last_submit(rq->engine)) { |
e95433c7 CW |
378 | /* The GPU is now idle and this client has stalled. |
379 | * Since no other client has submitted a request in the | |
380 | * meantime, assume that this client is the only one | |
381 | * supplying work to the GPU but is unable to keep that | |
382 | * work supplied because it is waiting. Since the GPU is | |
383 | * then never kept fully busy, RPS autoclocking will | |
384 | * keep the clocks relatively low, causing further delays. | |
385 | * Compensate by giving the synchronous client credit for | |
386 | * a waitboost next time. | |
387 | */ | |
388 | spin_lock(&rq->i915->rps.client_lock); | |
389 | list_del_init(&rps->link); | |
390 | spin_unlock(&rq->i915->rps.client_lock); | |
391 | } | |
392 | ||
393 | return timeout; | |
394 | } | |
395 | ||
396 | static long | |
397 | i915_gem_object_wait_reservation(struct reservation_object *resv, | |
398 | unsigned int flags, | |
399 | long timeout, | |
400 | struct intel_rps_client *rps) | |
401 | { | |
402 | struct dma_fence *excl; | |
403 | ||
404 | if (flags & I915_WAIT_ALL) { | |
405 | struct dma_fence **shared; | |
406 | unsigned int count, i; | |
00e60f26 CW |
407 | int ret; |
408 | ||
e95433c7 CW |
409 | ret = reservation_object_get_fences_rcu(resv, |
410 | &excl, &count, &shared); | |
00e60f26 CW |
411 | if (ret) |
412 | return ret; | |
00e60f26 | 413 | |
e95433c7 CW |
414 | for (i = 0; i < count; i++) { |
415 | timeout = i915_gem_object_wait_fence(shared[i], | |
416 | flags, timeout, | |
417 | rps); | |
418 | if (timeout <= 0) | |
419 | break; | |
00e60f26 | 420 | |
e95433c7 CW |
421 | dma_fence_put(shared[i]); |
422 | } | |
423 | ||
424 | for (; i < count; i++) | |
425 | dma_fence_put(shared[i]); | |
426 | kfree(shared); | |
427 | } else { | |
428 | excl = reservation_object_get_excl_rcu(resv); | |
00e60f26 CW |
429 | } |
430 | ||
e95433c7 CW |
431 | if (excl && timeout > 0) |
432 | timeout = i915_gem_object_wait_fence(excl, flags, timeout, rps); | |
433 | ||
434 | dma_fence_put(excl); | |
435 | ||
436 | return timeout; | |
00e60f26 CW |
437 | } |
438 | ||
6b5e90f5 CW |
439 | static void __fence_set_priority(struct dma_fence *fence, int prio) |
440 | { | |
441 | struct drm_i915_gem_request *rq; | |
442 | struct intel_engine_cs *engine; | |
443 | ||
444 | if (!dma_fence_is_i915(fence)) | |
445 | return; | |
446 | ||
447 | rq = to_request(fence); | |
448 | engine = rq->engine; | |
449 | if (!engine->schedule) | |
450 | return; | |
451 | ||
452 | engine->schedule(rq, prio); | |
453 | } | |
454 | ||
455 | static void fence_set_priority(struct dma_fence *fence, int prio) | |
456 | { | |
457 | /* Recurse once into a fence-array */ | |
458 | if (dma_fence_is_array(fence)) { | |
459 | struct dma_fence_array *array = to_dma_fence_array(fence); | |
460 | int i; | |
461 | ||
462 | for (i = 0; i < array->num_fences; i++) | |
463 | __fence_set_priority(array->fences[i], prio); | |
464 | } else { | |
465 | __fence_set_priority(fence, prio); | |
466 | } | |
467 | } | |
468 | ||
469 | int | |
470 | i915_gem_object_wait_priority(struct drm_i915_gem_object *obj, | |
471 | unsigned int flags, | |
472 | int prio) | |
473 | { | |
474 | struct dma_fence *excl; | |
475 | ||
476 | if (flags & I915_WAIT_ALL) { | |
477 | struct dma_fence **shared; | |
478 | unsigned int count, i; | |
479 | int ret; | |
480 | ||
481 | ret = reservation_object_get_fences_rcu(obj->resv, | |
482 | &excl, &count, &shared); | |
483 | if (ret) | |
484 | return ret; | |
485 | ||
486 | for (i = 0; i < count; i++) { | |
487 | fence_set_priority(shared[i], prio); | |
488 | dma_fence_put(shared[i]); | |
489 | } | |
490 | ||
491 | kfree(shared); | |
492 | } else { | |
493 | excl = reservation_object_get_excl_rcu(obj->resv); | |
494 | } | |
495 | ||
496 | if (excl) { | |
497 | fence_set_priority(excl, prio); | |
498 | dma_fence_put(excl); | |
499 | } | |
500 | return 0; | |
501 | } | |
502 | ||
e95433c7 CW |
503 | /** |
504 | * Waits for rendering to the object to be completed | |
505 | * @obj: i915 gem object | |
506 | * @flags: how to wait (under a lock, for all rendering or just for writes etc) | |
507 | * @timeout: how long to wait | |
508 | * @rps: client (user process) to charge for any waitboosting | |
00e60f26 | 509 | */ |
e95433c7 CW |
510 | int |
511 | i915_gem_object_wait(struct drm_i915_gem_object *obj, | |
512 | unsigned int flags, | |
513 | long timeout, | |
514 | struct intel_rps_client *rps) | |
00e60f26 | 515 | { |
e95433c7 CW |
516 | might_sleep(); |
517 | #if IS_ENABLED(CONFIG_LOCKDEP) | |
518 | GEM_BUG_ON(debug_locks && | |
519 | !!lockdep_is_held(&obj->base.dev->struct_mutex) != | |
520 | !!(flags & I915_WAIT_LOCKED)); | |
521 | #endif | |
522 | GEM_BUG_ON(timeout < 0); | |
00e60f26 | 523 | |
d07f0e59 CW |
524 | timeout = i915_gem_object_wait_reservation(obj->resv, |
525 | flags, timeout, | |
526 | rps); | |
e95433c7 | 527 | return timeout < 0 ? timeout : 0; |
00e60f26 CW |
528 | } |
529 | ||
530 | static struct intel_rps_client *to_rps_client(struct drm_file *file) | |
531 | { | |
532 | struct drm_i915_file_private *fpriv = file->driver_priv; | |
533 | ||
534 | return &fpriv->rps; | |
535 | } | |
536 | ||
00731155 CW |
537 | int |
538 | i915_gem_object_attach_phys(struct drm_i915_gem_object *obj, | |
539 | int align) | |
540 | { | |
541 | drm_dma_handle_t *phys; | |
6a2c4232 | 542 | int ret; |
00731155 CW |
543 | |
544 | if (obj->phys_handle) { | |
545 | if ((unsigned long)obj->phys_handle->vaddr & (align -1)) | |
546 | return -EBUSY; | |
547 | ||
548 | return 0; | |
549 | } | |
550 | ||
a4f5ea64 | 551 | if (obj->mm.madv != I915_MADV_WILLNEED) |
00731155 CW |
552 | return -EFAULT; |
553 | ||
554 | if (obj->base.filp == NULL) | |
555 | return -EINVAL; | |
556 | ||
4717ca9e CW |
557 | ret = i915_gem_object_unbind(obj); |
558 | if (ret) | |
559 | return ret; | |
560 | ||
548625ee | 561 | __i915_gem_object_put_pages(obj, I915_MM_NORMAL); |
03ac84f1 CW |
562 | if (obj->mm.pages) |
563 | return -EBUSY; | |
6a2c4232 | 564 | |
00731155 CW |
565 | /* create a new object */ |
566 | phys = drm_pci_alloc(obj->base.dev, obj->base.size, align); | |
567 | if (!phys) | |
568 | return -ENOMEM; | |
569 | ||
00731155 | 570 | obj->phys_handle = phys; |
6a2c4232 CW |
571 | obj->ops = &i915_gem_phys_ops; |
572 | ||
a4f5ea64 | 573 | return i915_gem_object_pin_pages(obj); |
00731155 CW |
574 | } |
575 | ||
576 | static int | |
577 | i915_gem_phys_pwrite(struct drm_i915_gem_object *obj, | |
578 | struct drm_i915_gem_pwrite *args, | |
03ac84f1 | 579 | struct drm_file *file) |
00731155 CW |
580 | { |
581 | struct drm_device *dev = obj->base.dev; | |
582 | void *vaddr = obj->phys_handle->vaddr + args->offset; | |
3ed605bc | 583 | char __user *user_data = u64_to_user_ptr(args->data_ptr); |
e95433c7 | 584 | int ret; |
6a2c4232 CW |
585 | |
586 | /* We manually control the domain here and pretend that it | |
587 | * remains coherent i.e. in the GTT domain, like shmem_pwrite. | |
588 | */ | |
e95433c7 CW |
589 | lockdep_assert_held(&obj->base.dev->struct_mutex); |
590 | ret = i915_gem_object_wait(obj, | |
591 | I915_WAIT_INTERRUPTIBLE | | |
592 | I915_WAIT_LOCKED | | |
593 | I915_WAIT_ALL, | |
594 | MAX_SCHEDULE_TIMEOUT, | |
03ac84f1 | 595 | to_rps_client(file)); |
6a2c4232 CW |
596 | if (ret) |
597 | return ret; | |
00731155 | 598 | |
77a0d1ca | 599 | intel_fb_obj_invalidate(obj, ORIGIN_CPU); |
00731155 CW |
600 | if (__copy_from_user_inatomic_nocache(vaddr, user_data, args->size)) { |
601 | unsigned long unwritten; | |
602 | ||
603 | /* The physical object once assigned is fixed for the lifetime | |
604 | * of the obj, so we can safely drop the lock and continue | |
605 | * to access vaddr. | |
606 | */ | |
607 | mutex_unlock(&dev->struct_mutex); | |
608 | unwritten = copy_from_user(vaddr, user_data, args->size); | |
609 | mutex_lock(&dev->struct_mutex); | |
063e4e6b PZ |
610 | if (unwritten) { |
611 | ret = -EFAULT; | |
612 | goto out; | |
613 | } | |
00731155 CW |
614 | } |
615 | ||
6a2c4232 | 616 | drm_clflush_virt_range(vaddr, args->size); |
c033666a | 617 | i915_gem_chipset_flush(to_i915(dev)); |
063e4e6b PZ |
618 | |
619 | out: | |
de152b62 | 620 | intel_fb_obj_flush(obj, false, ORIGIN_CPU); |
063e4e6b | 621 | return ret; |
00731155 CW |
622 | } |
623 | ||
42dcedd4 CW |
624 | void *i915_gem_object_alloc(struct drm_device *dev) |
625 | { | |
fac5e23e | 626 | struct drm_i915_private *dev_priv = to_i915(dev); |
efab6d8d | 627 | return kmem_cache_zalloc(dev_priv->objects, GFP_KERNEL); |
42dcedd4 CW |
628 | } |
629 | ||
630 | void i915_gem_object_free(struct drm_i915_gem_object *obj) | |
631 | { | |
fac5e23e | 632 | struct drm_i915_private *dev_priv = to_i915(obj->base.dev); |
efab6d8d | 633 | kmem_cache_free(dev_priv->objects, obj); |
42dcedd4 CW |
634 | } |
635 | ||
ff72145b DA |
636 | static int |
637 | i915_gem_create(struct drm_file *file, | |
638 | struct drm_device *dev, | |
639 | uint64_t size, | |
640 | uint32_t *handle_p) | |
673a394b | 641 | { |
05394f39 | 642 | struct drm_i915_gem_object *obj; |
a1a2d1d3 PP |
643 | int ret; |
644 | u32 handle; | |
673a394b | 645 | |
ff72145b | 646 | size = roundup(size, PAGE_SIZE); |
8ffc0246 CW |
647 | if (size == 0) |
648 | return -EINVAL; | |
673a394b EA |
649 | |
650 | /* Allocate the new object */ | |
d37cd8a8 | 651 | obj = i915_gem_object_create(dev, size); |
fe3db79b CW |
652 | if (IS_ERR(obj)) |
653 | return PTR_ERR(obj); | |
673a394b | 654 | |
05394f39 | 655 | ret = drm_gem_handle_create(file, &obj->base, &handle); |
202f2fef | 656 | /* drop reference from allocate - handle holds it now */ |
f0cd5182 | 657 | i915_gem_object_put(obj); |
d861e338 DV |
658 | if (ret) |
659 | return ret; | |
202f2fef | 660 | |
ff72145b | 661 | *handle_p = handle; |
673a394b EA |
662 | return 0; |
663 | } | |
664 | ||
ff72145b DA |
665 | int |
666 | i915_gem_dumb_create(struct drm_file *file, | |
667 | struct drm_device *dev, | |
668 | struct drm_mode_create_dumb *args) | |
669 | { | |
670 | /* have to work out size/pitch and return them */ | |
de45eaf7 | 671 | args->pitch = ALIGN(args->width * DIV_ROUND_UP(args->bpp, 8), 64); |
ff72145b DA |
672 | args->size = args->pitch * args->height; |
673 | return i915_gem_create(file, dev, | |
da6b51d0 | 674 | args->size, &args->handle); |
ff72145b DA |
675 | } |
676 | ||
ff72145b DA |
677 | /** |
678 | * Creates a new mm object and returns a handle to it. | |
14bb2c11 TU |
679 | * @dev: drm device pointer |
680 | * @data: ioctl data blob | |
681 | * @file: drm file pointer | |
ff72145b DA |
682 | */ |
683 | int | |
684 | i915_gem_create_ioctl(struct drm_device *dev, void *data, | |
685 | struct drm_file *file) | |
686 | { | |
687 | struct drm_i915_gem_create *args = data; | |
63ed2cb2 | 688 | |
fbbd37b3 CW |
689 | i915_gem_flush_free_objects(to_i915(dev)); |
690 | ||
ff72145b | 691 | return i915_gem_create(file, dev, |
da6b51d0 | 692 | args->size, &args->handle); |
ff72145b DA |
693 | } |
694 | ||
8461d226 DV |
695 | static inline int |
696 | __copy_to_user_swizzled(char __user *cpu_vaddr, | |
697 | const char *gpu_vaddr, int gpu_offset, | |
698 | int length) | |
699 | { | |
700 | int ret, cpu_offset = 0; | |
701 | ||
702 | while (length > 0) { | |
703 | int cacheline_end = ALIGN(gpu_offset + 1, 64); | |
704 | int this_length = min(cacheline_end - gpu_offset, length); | |
705 | int swizzled_gpu_offset = gpu_offset ^ 64; | |
706 | ||
707 | ret = __copy_to_user(cpu_vaddr + cpu_offset, | |
708 | gpu_vaddr + swizzled_gpu_offset, | |
709 | this_length); | |
710 | if (ret) | |
711 | return ret + length; | |
712 | ||
713 | cpu_offset += this_length; | |
714 | gpu_offset += this_length; | |
715 | length -= this_length; | |
716 | } | |
717 | ||
718 | return 0; | |
719 | } | |
720 | ||
8c59967c | 721 | static inline int |
4f0c7cfb BW |
722 | __copy_from_user_swizzled(char *gpu_vaddr, int gpu_offset, |
723 | const char __user *cpu_vaddr, | |
8c59967c DV |
724 | int length) |
725 | { | |
726 | int ret, cpu_offset = 0; | |
727 | ||
728 | while (length > 0) { | |
729 | int cacheline_end = ALIGN(gpu_offset + 1, 64); | |
730 | int this_length = min(cacheline_end - gpu_offset, length); | |
731 | int swizzled_gpu_offset = gpu_offset ^ 64; | |
732 | ||
733 | ret = __copy_from_user(gpu_vaddr + swizzled_gpu_offset, | |
734 | cpu_vaddr + cpu_offset, | |
735 | this_length); | |
736 | if (ret) | |
737 | return ret + length; | |
738 | ||
739 | cpu_offset += this_length; | |
740 | gpu_offset += this_length; | |
741 | length -= this_length; | |
742 | } | |
743 | ||
744 | return 0; | |
745 | } | |
746 | ||
4c914c0c BV |
747 | /* |
748 | * Pins the specified object's pages and synchronizes the object with | |
749 | * GPU accesses. Sets needs_clflush to non-zero if the caller should | |
750 | * flush the object from the CPU cache. | |
751 | */ | |
752 | int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj, | |
43394c7d | 753 | unsigned int *needs_clflush) |
4c914c0c BV |
754 | { |
755 | int ret; | |
756 | ||
e95433c7 | 757 | lockdep_assert_held(&obj->base.dev->struct_mutex); |
4c914c0c | 758 | |
e95433c7 | 759 | *needs_clflush = 0; |
43394c7d CW |
760 | if (!i915_gem_object_has_struct_page(obj)) |
761 | return -ENODEV; | |
4c914c0c | 762 | |
e95433c7 CW |
763 | ret = i915_gem_object_wait(obj, |
764 | I915_WAIT_INTERRUPTIBLE | | |
765 | I915_WAIT_LOCKED, | |
766 | MAX_SCHEDULE_TIMEOUT, | |
767 | NULL); | |
c13d87ea CW |
768 | if (ret) |
769 | return ret; | |
770 | ||
a4f5ea64 | 771 | ret = i915_gem_object_pin_pages(obj); |
9764951e CW |
772 | if (ret) |
773 | return ret; | |
774 | ||
a314d5cb CW |
775 | i915_gem_object_flush_gtt_write_domain(obj); |
776 | ||
43394c7d CW |
777 | /* If we're not in the cpu read domain, set ourself into the gtt |
778 | * read domain and manually flush cachelines (if required). This | |
779 | * optimizes for the case when the gpu will dirty the data | |
780 | * anyway again before the next pread happens. | |
781 | */ | |
782 | if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU)) | |
4c914c0c BV |
783 | *needs_clflush = !cpu_cache_is_coherent(obj->base.dev, |
784 | obj->cache_level); | |
43394c7d | 785 | |
43394c7d CW |
786 | if (*needs_clflush && !static_cpu_has(X86_FEATURE_CLFLUSH)) { |
787 | ret = i915_gem_object_set_to_cpu_domain(obj, false); | |
9764951e CW |
788 | if (ret) |
789 | goto err_unpin; | |
790 | ||
43394c7d | 791 | *needs_clflush = 0; |
4c914c0c BV |
792 | } |
793 | ||
9764951e | 794 | /* return with the pages pinned */ |
43394c7d | 795 | return 0; |
9764951e CW |
796 | |
797 | err_unpin: | |
798 | i915_gem_object_unpin_pages(obj); | |
799 | return ret; | |
43394c7d CW |
800 | } |
801 | ||
802 | int i915_gem_obj_prepare_shmem_write(struct drm_i915_gem_object *obj, | |
803 | unsigned int *needs_clflush) | |
804 | { | |
805 | int ret; | |
806 | ||
e95433c7 CW |
807 | lockdep_assert_held(&obj->base.dev->struct_mutex); |
808 | ||
43394c7d CW |
809 | *needs_clflush = 0; |
810 | if (!i915_gem_object_has_struct_page(obj)) | |
811 | return -ENODEV; | |
812 | ||
e95433c7 CW |
813 | ret = i915_gem_object_wait(obj, |
814 | I915_WAIT_INTERRUPTIBLE | | |
815 | I915_WAIT_LOCKED | | |
816 | I915_WAIT_ALL, | |
817 | MAX_SCHEDULE_TIMEOUT, | |
818 | NULL); | |
43394c7d CW |
819 | if (ret) |
820 | return ret; | |
821 | ||
a4f5ea64 | 822 | ret = i915_gem_object_pin_pages(obj); |
9764951e CW |
823 | if (ret) |
824 | return ret; | |
825 | ||
a314d5cb CW |
826 | i915_gem_object_flush_gtt_write_domain(obj); |
827 | ||
43394c7d CW |
828 | /* If we're not in the cpu write domain, set ourself into the |
829 | * gtt write domain and manually flush cachelines (as required). | |
830 | * This optimizes for the case when the gpu will use the data | |
831 | * right away and we therefore have to clflush anyway. | |
832 | */ | |
833 | if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) | |
834 | *needs_clflush |= cpu_write_needs_clflush(obj) << 1; | |
835 | ||
836 | /* Same trick applies to invalidate partially written cachelines read | |
837 | * before writing. | |
838 | */ | |
839 | if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU)) | |
840 | *needs_clflush |= !cpu_cache_is_coherent(obj->base.dev, | |
841 | obj->cache_level); | |
842 | ||
43394c7d CW |
843 | if (*needs_clflush && !static_cpu_has(X86_FEATURE_CLFLUSH)) { |
844 | ret = i915_gem_object_set_to_cpu_domain(obj, true); | |
9764951e CW |
845 | if (ret) |
846 | goto err_unpin; | |
847 | ||
43394c7d CW |
848 | *needs_clflush = 0; |
849 | } | |
850 | ||
851 | if ((*needs_clflush & CLFLUSH_AFTER) == 0) | |
852 | obj->cache_dirty = true; | |
853 | ||
854 | intel_fb_obj_invalidate(obj, ORIGIN_CPU); | |
a4f5ea64 | 855 | obj->mm.dirty = true; |
9764951e | 856 | /* return with the pages pinned */ |
43394c7d | 857 | return 0; |
9764951e CW |
858 | |
859 | err_unpin: | |
860 | i915_gem_object_unpin_pages(obj); | |
861 | return ret; | |
4c914c0c BV |
862 | } |
863 | ||
23c18c71 DV |
864 | static void |
865 | shmem_clflush_swizzled_range(char *addr, unsigned long length, | |
866 | bool swizzled) | |
867 | { | |
e7e58eb5 | 868 | if (unlikely(swizzled)) { |
23c18c71 DV |
869 | unsigned long start = (unsigned long) addr; |
870 | unsigned long end = (unsigned long) addr + length; | |
871 | ||
872 | /* For swizzling simply ensure that we always flush both | |
873 | * channels. Lame, but simple and it works. Swizzled | |
874 | * pwrite/pread is far from a hotpath - current userspace | |
875 | * doesn't use it at all. */ | |
876 | start = round_down(start, 128); | |
877 | end = round_up(end, 128); | |
878 | ||
879 | drm_clflush_virt_range((void *)start, end - start); | |
880 | } else { | |
881 | drm_clflush_virt_range(addr, length); | |
882 | } | |
883 | ||
884 | } | |
885 | ||
d174bd64 DV |
886 | /* Only difference to the fast-path function is that this can handle bit17 |
887 | * and uses non-atomic copy and kmap functions. */ | |
888 | static int | |
bb6dc8d9 | 889 | shmem_pread_slow(struct page *page, int offset, int length, |
d174bd64 DV |
890 | char __user *user_data, |
891 | bool page_do_bit17_swizzling, bool needs_clflush) | |
892 | { | |
893 | char *vaddr; | |
894 | int ret; | |
895 | ||
896 | vaddr = kmap(page); | |
897 | if (needs_clflush) | |
bb6dc8d9 | 898 | shmem_clflush_swizzled_range(vaddr + offset, length, |
23c18c71 | 899 | page_do_bit17_swizzling); |
d174bd64 DV |
900 | |
901 | if (page_do_bit17_swizzling) | |
bb6dc8d9 | 902 | ret = __copy_to_user_swizzled(user_data, vaddr, offset, length); |
d174bd64 | 903 | else |
bb6dc8d9 | 904 | ret = __copy_to_user(user_data, vaddr + offset, length); |
d174bd64 DV |
905 | kunmap(page); |
906 | ||
f60d7f0c | 907 | return ret ? - EFAULT : 0; |
d174bd64 DV |
908 | } |
909 | ||
bb6dc8d9 CW |
910 | static int |
911 | shmem_pread(struct page *page, int offset, int length, char __user *user_data, | |
912 | bool page_do_bit17_swizzling, bool needs_clflush) | |
913 | { | |
914 | int ret; | |
915 | ||
916 | ret = -ENODEV; | |
917 | if (!page_do_bit17_swizzling) { | |
918 | char *vaddr = kmap_atomic(page); | |
919 | ||
920 | if (needs_clflush) | |
921 | drm_clflush_virt_range(vaddr + offset, length); | |
922 | ret = __copy_to_user_inatomic(user_data, vaddr + offset, length); | |
923 | kunmap_atomic(vaddr); | |
924 | } | |
925 | if (ret == 0) | |
926 | return 0; | |
927 | ||
928 | return shmem_pread_slow(page, offset, length, user_data, | |
929 | page_do_bit17_swizzling, needs_clflush); | |
930 | } | |
931 | ||
932 | static int | |
933 | i915_gem_shmem_pread(struct drm_i915_gem_object *obj, | |
934 | struct drm_i915_gem_pread *args) | |
935 | { | |
936 | char __user *user_data; | |
937 | u64 remain; | |
938 | unsigned int obj_do_bit17_swizzling; | |
939 | unsigned int needs_clflush; | |
940 | unsigned int idx, offset; | |
941 | int ret; | |
942 | ||
943 | obj_do_bit17_swizzling = 0; | |
944 | if (i915_gem_object_needs_bit17_swizzle(obj)) | |
945 | obj_do_bit17_swizzling = BIT(17); | |
946 | ||
947 | ret = mutex_lock_interruptible(&obj->base.dev->struct_mutex); | |
948 | if (ret) | |
949 | return ret; | |
950 | ||
951 | ret = i915_gem_obj_prepare_shmem_read(obj, &needs_clflush); | |
952 | mutex_unlock(&obj->base.dev->struct_mutex); | |
953 | if (ret) | |
954 | return ret; | |
955 | ||
956 | remain = args->size; | |
957 | user_data = u64_to_user_ptr(args->data_ptr); | |
958 | offset = offset_in_page(args->offset); | |
959 | for (idx = args->offset >> PAGE_SHIFT; remain; idx++) { | |
960 | struct page *page = i915_gem_object_get_page(obj, idx); | |
961 | int length; | |
962 | ||
963 | length = remain; | |
964 | if (offset + length > PAGE_SIZE) | |
965 | length = PAGE_SIZE - offset; | |
966 | ||
967 | ret = shmem_pread(page, offset, length, user_data, | |
968 | page_to_phys(page) & obj_do_bit17_swizzling, | |
969 | needs_clflush); | |
970 | if (ret) | |
971 | break; | |
972 | ||
973 | remain -= length; | |
974 | user_data += length; | |
975 | offset = 0; | |
976 | } | |
977 | ||
978 | i915_gem_obj_finish_shmem_access(obj); | |
979 | return ret; | |
980 | } | |
981 | ||
982 | static inline bool | |
983 | gtt_user_read(struct io_mapping *mapping, | |
984 | loff_t base, int offset, | |
985 | char __user *user_data, int length) | |
b50a5371 | 986 | { |
b50a5371 | 987 | void *vaddr; |
bb6dc8d9 | 988 | unsigned long unwritten; |
b50a5371 | 989 | |
b50a5371 | 990 | /* We can use the cpu mem copy function because this is X86. */ |
bb6dc8d9 CW |
991 | vaddr = (void __force *)io_mapping_map_atomic_wc(mapping, base); |
992 | unwritten = __copy_to_user_inatomic(user_data, vaddr + offset, length); | |
993 | io_mapping_unmap_atomic(vaddr); | |
994 | if (unwritten) { | |
995 | vaddr = (void __force *) | |
996 | io_mapping_map_wc(mapping, base, PAGE_SIZE); | |
997 | unwritten = copy_to_user(user_data, vaddr + offset, length); | |
998 | io_mapping_unmap(vaddr); | |
999 | } | |
b50a5371 AS |
1000 | return unwritten; |
1001 | } | |
1002 | ||
1003 | static int | |
bb6dc8d9 CW |
1004 | i915_gem_gtt_pread(struct drm_i915_gem_object *obj, |
1005 | const struct drm_i915_gem_pread *args) | |
b50a5371 | 1006 | { |
bb6dc8d9 CW |
1007 | struct drm_i915_private *i915 = to_i915(obj->base.dev); |
1008 | struct i915_ggtt *ggtt = &i915->ggtt; | |
b50a5371 | 1009 | struct drm_mm_node node; |
bb6dc8d9 CW |
1010 | struct i915_vma *vma; |
1011 | void __user *user_data; | |
1012 | u64 remain, offset; | |
b50a5371 AS |
1013 | int ret; |
1014 | ||
bb6dc8d9 CW |
1015 | ret = mutex_lock_interruptible(&i915->drm.struct_mutex); |
1016 | if (ret) | |
1017 | return ret; | |
1018 | ||
1019 | intel_runtime_pm_get(i915); | |
1020 | vma = i915_gem_object_ggtt_pin(obj, NULL, 0, 0, | |
1021 | PIN_MAPPABLE | PIN_NONBLOCK); | |
18034584 CW |
1022 | if (!IS_ERR(vma)) { |
1023 | node.start = i915_ggtt_offset(vma); | |
1024 | node.allocated = false; | |
49ef5294 | 1025 | ret = i915_vma_put_fence(vma); |
18034584 CW |
1026 | if (ret) { |
1027 | i915_vma_unpin(vma); | |
1028 | vma = ERR_PTR(ret); | |
1029 | } | |
1030 | } | |
058d88c4 | 1031 | if (IS_ERR(vma)) { |
bb6dc8d9 | 1032 | ret = insert_mappable_node(ggtt, &node, PAGE_SIZE); |
b50a5371 | 1033 | if (ret) |
bb6dc8d9 CW |
1034 | goto out_unlock; |
1035 | GEM_BUG_ON(!node.allocated); | |
b50a5371 AS |
1036 | } |
1037 | ||
1038 | ret = i915_gem_object_set_to_gtt_domain(obj, false); | |
1039 | if (ret) | |
1040 | goto out_unpin; | |
1041 | ||
bb6dc8d9 | 1042 | mutex_unlock(&i915->drm.struct_mutex); |
b50a5371 | 1043 | |
bb6dc8d9 CW |
1044 | user_data = u64_to_user_ptr(args->data_ptr); |
1045 | remain = args->size; | |
1046 | offset = args->offset; | |
b50a5371 AS |
1047 | |
1048 | while (remain > 0) { | |
1049 | /* Operation in this page | |
1050 | * | |
1051 | * page_base = page offset within aperture | |
1052 | * page_offset = offset within page | |
1053 | * page_length = bytes to copy for this page | |
1054 | */ | |
1055 | u32 page_base = node.start; | |
1056 | unsigned page_offset = offset_in_page(offset); | |
1057 | unsigned page_length = PAGE_SIZE - page_offset; | |
1058 | page_length = remain < page_length ? remain : page_length; | |
1059 | if (node.allocated) { | |
1060 | wmb(); | |
1061 | ggtt->base.insert_page(&ggtt->base, | |
1062 | i915_gem_object_get_dma_address(obj, offset >> PAGE_SHIFT), | |
bb6dc8d9 | 1063 | node.start, I915_CACHE_NONE, 0); |
b50a5371 AS |
1064 | wmb(); |
1065 | } else { | |
1066 | page_base += offset & PAGE_MASK; | |
1067 | } | |
bb6dc8d9 CW |
1068 | |
1069 | if (gtt_user_read(&ggtt->mappable, page_base, page_offset, | |
1070 | user_data, page_length)) { | |
b50a5371 AS |
1071 | ret = -EFAULT; |
1072 | break; | |
1073 | } | |
1074 | ||
1075 | remain -= page_length; | |
1076 | user_data += page_length; | |
1077 | offset += page_length; | |
1078 | } | |
1079 | ||
bb6dc8d9 | 1080 | mutex_lock(&i915->drm.struct_mutex); |
b50a5371 AS |
1081 | out_unpin: |
1082 | if (node.allocated) { | |
1083 | wmb(); | |
1084 | ggtt->base.clear_range(&ggtt->base, | |
4fb84d99 | 1085 | node.start, node.size); |
b50a5371 AS |
1086 | remove_mappable_node(&node); |
1087 | } else { | |
058d88c4 | 1088 | i915_vma_unpin(vma); |
b50a5371 | 1089 | } |
bb6dc8d9 CW |
1090 | out_unlock: |
1091 | intel_runtime_pm_put(i915); | |
1092 | mutex_unlock(&i915->drm.struct_mutex); | |
f60d7f0c | 1093 | |
eb01459f EA |
1094 | return ret; |
1095 | } | |
1096 | ||
673a394b EA |
1097 | /** |
1098 | * Reads data from the object referenced by handle. | |
14bb2c11 TU |
1099 | * @dev: drm device pointer |
1100 | * @data: ioctl data blob | |
1101 | * @file: drm file pointer | |
673a394b EA |
1102 | * |
1103 | * On error, the contents of *data are undefined. | |
1104 | */ | |
1105 | int | |
1106 | i915_gem_pread_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 1107 | struct drm_file *file) |
673a394b EA |
1108 | { |
1109 | struct drm_i915_gem_pread *args = data; | |
05394f39 | 1110 | struct drm_i915_gem_object *obj; |
bb6dc8d9 | 1111 | int ret; |
673a394b | 1112 | |
51311d0a CW |
1113 | if (args->size == 0) |
1114 | return 0; | |
1115 | ||
1116 | if (!access_ok(VERIFY_WRITE, | |
3ed605bc | 1117 | u64_to_user_ptr(args->data_ptr), |
51311d0a CW |
1118 | args->size)) |
1119 | return -EFAULT; | |
1120 | ||
03ac0642 | 1121 | obj = i915_gem_object_lookup(file, args->handle); |
258a5ede CW |
1122 | if (!obj) |
1123 | return -ENOENT; | |
673a394b | 1124 | |
7dcd2499 | 1125 | /* Bounds check source. */ |
05394f39 CW |
1126 | if (args->offset > obj->base.size || |
1127 | args->size > obj->base.size - args->offset) { | |
ce9d419d | 1128 | ret = -EINVAL; |
bb6dc8d9 | 1129 | goto out; |
ce9d419d CW |
1130 | } |
1131 | ||
db53a302 CW |
1132 | trace_i915_gem_object_pread(obj, args->offset, args->size); |
1133 | ||
e95433c7 CW |
1134 | ret = i915_gem_object_wait(obj, |
1135 | I915_WAIT_INTERRUPTIBLE, | |
1136 | MAX_SCHEDULE_TIMEOUT, | |
1137 | to_rps_client(file)); | |
258a5ede | 1138 | if (ret) |
bb6dc8d9 | 1139 | goto out; |
258a5ede | 1140 | |
bb6dc8d9 | 1141 | ret = i915_gem_object_pin_pages(obj); |
258a5ede | 1142 | if (ret) |
bb6dc8d9 | 1143 | goto out; |
673a394b | 1144 | |
bb6dc8d9 | 1145 | ret = i915_gem_shmem_pread(obj, args); |
9c870d03 | 1146 | if (ret == -EFAULT || ret == -ENODEV) |
bb6dc8d9 | 1147 | ret = i915_gem_gtt_pread(obj, args); |
b50a5371 | 1148 | |
bb6dc8d9 CW |
1149 | i915_gem_object_unpin_pages(obj); |
1150 | out: | |
f0cd5182 | 1151 | i915_gem_object_put(obj); |
eb01459f | 1152 | return ret; |
673a394b EA |
1153 | } |
1154 | ||
0839ccb8 KP |
1155 | /* This is the fast write path which cannot handle |
1156 | * page faults in the source data | |
9b7530cc | 1157 | */ |
0839ccb8 | 1158 | |
fe115628 CW |
1159 | static inline bool |
1160 | ggtt_write(struct io_mapping *mapping, | |
1161 | loff_t base, int offset, | |
1162 | char __user *user_data, int length) | |
9b7530cc | 1163 | { |
4f0c7cfb | 1164 | void *vaddr; |
0839ccb8 | 1165 | unsigned long unwritten; |
9b7530cc | 1166 | |
4f0c7cfb | 1167 | /* We can use the cpu mem copy function because this is X86. */ |
fe115628 CW |
1168 | vaddr = (void __force *)io_mapping_map_atomic_wc(mapping, base); |
1169 | unwritten = __copy_from_user_inatomic_nocache(vaddr + offset, | |
0839ccb8 | 1170 | user_data, length); |
fe115628 CW |
1171 | io_mapping_unmap_atomic(vaddr); |
1172 | if (unwritten) { | |
1173 | vaddr = (void __force *) | |
1174 | io_mapping_map_wc(mapping, base, PAGE_SIZE); | |
1175 | unwritten = copy_from_user(vaddr + offset, user_data, length); | |
1176 | io_mapping_unmap(vaddr); | |
1177 | } | |
bb6dc8d9 | 1178 | |
bb6dc8d9 CW |
1179 | return unwritten; |
1180 | } | |
1181 | ||
3de09aa3 EA |
1182 | /** |
1183 | * This is the fast pwrite path, where we copy the data directly from the | |
1184 | * user into the GTT, uncached. | |
fe115628 | 1185 | * @obj: i915 GEM object |
14bb2c11 | 1186 | * @args: pwrite arguments structure |
3de09aa3 | 1187 | */ |
673a394b | 1188 | static int |
fe115628 CW |
1189 | i915_gem_gtt_pwrite_fast(struct drm_i915_gem_object *obj, |
1190 | const struct drm_i915_gem_pwrite *args) | |
673a394b | 1191 | { |
fe115628 | 1192 | struct drm_i915_private *i915 = to_i915(obj->base.dev); |
4f1959ee AS |
1193 | struct i915_ggtt *ggtt = &i915->ggtt; |
1194 | struct drm_mm_node node; | |
fe115628 CW |
1195 | struct i915_vma *vma; |
1196 | u64 remain, offset; | |
1197 | void __user *user_data; | |
4f1959ee | 1198 | int ret; |
b50a5371 | 1199 | |
fe115628 CW |
1200 | ret = mutex_lock_interruptible(&i915->drm.struct_mutex); |
1201 | if (ret) | |
1202 | return ret; | |
935aaa69 | 1203 | |
9c870d03 | 1204 | intel_runtime_pm_get(i915); |
058d88c4 | 1205 | vma = i915_gem_object_ggtt_pin(obj, NULL, 0, 0, |
de895082 | 1206 | PIN_MAPPABLE | PIN_NONBLOCK); |
18034584 CW |
1207 | if (!IS_ERR(vma)) { |
1208 | node.start = i915_ggtt_offset(vma); | |
1209 | node.allocated = false; | |
49ef5294 | 1210 | ret = i915_vma_put_fence(vma); |
18034584 CW |
1211 | if (ret) { |
1212 | i915_vma_unpin(vma); | |
1213 | vma = ERR_PTR(ret); | |
1214 | } | |
1215 | } | |
058d88c4 | 1216 | if (IS_ERR(vma)) { |
bb6dc8d9 | 1217 | ret = insert_mappable_node(ggtt, &node, PAGE_SIZE); |
4f1959ee | 1218 | if (ret) |
fe115628 CW |
1219 | goto out_unlock; |
1220 | GEM_BUG_ON(!node.allocated); | |
4f1959ee | 1221 | } |
935aaa69 DV |
1222 | |
1223 | ret = i915_gem_object_set_to_gtt_domain(obj, true); | |
1224 | if (ret) | |
1225 | goto out_unpin; | |
1226 | ||
fe115628 CW |
1227 | mutex_unlock(&i915->drm.struct_mutex); |
1228 | ||
b19482d7 | 1229 | intel_fb_obj_invalidate(obj, ORIGIN_CPU); |
063e4e6b | 1230 | |
4f1959ee AS |
1231 | user_data = u64_to_user_ptr(args->data_ptr); |
1232 | offset = args->offset; | |
1233 | remain = args->size; | |
1234 | while (remain) { | |
673a394b EA |
1235 | /* Operation in this page |
1236 | * | |
0839ccb8 KP |
1237 | * page_base = page offset within aperture |
1238 | * page_offset = offset within page | |
1239 | * page_length = bytes to copy for this page | |
673a394b | 1240 | */ |
4f1959ee | 1241 | u32 page_base = node.start; |
bb6dc8d9 CW |
1242 | unsigned int page_offset = offset_in_page(offset); |
1243 | unsigned int page_length = PAGE_SIZE - page_offset; | |
4f1959ee AS |
1244 | page_length = remain < page_length ? remain : page_length; |
1245 | if (node.allocated) { | |
1246 | wmb(); /* flush the write before we modify the GGTT */ | |
1247 | ggtt->base.insert_page(&ggtt->base, | |
1248 | i915_gem_object_get_dma_address(obj, offset >> PAGE_SHIFT), | |
1249 | node.start, I915_CACHE_NONE, 0); | |
1250 | wmb(); /* flush modifications to the GGTT (insert_page) */ | |
1251 | } else { | |
1252 | page_base += offset & PAGE_MASK; | |
1253 | } | |
0839ccb8 | 1254 | /* If we get a fault while copying data, then (presumably) our |
3de09aa3 EA |
1255 | * source page isn't available. Return the error and we'll |
1256 | * retry in the slow path. | |
b50a5371 AS |
1257 | * If the object is non-shmem backed, we retry again with the |
1258 | * path that handles page fault. | |
0839ccb8 | 1259 | */ |
fe115628 CW |
1260 | if (ggtt_write(&ggtt->mappable, page_base, page_offset, |
1261 | user_data, page_length)) { | |
1262 | ret = -EFAULT; | |
1263 | break; | |
935aaa69 | 1264 | } |
673a394b | 1265 | |
0839ccb8 KP |
1266 | remain -= page_length; |
1267 | user_data += page_length; | |
1268 | offset += page_length; | |
673a394b | 1269 | } |
b19482d7 | 1270 | intel_fb_obj_flush(obj, false, ORIGIN_CPU); |
fe115628 CW |
1271 | |
1272 | mutex_lock(&i915->drm.struct_mutex); | |
935aaa69 | 1273 | out_unpin: |
4f1959ee AS |
1274 | if (node.allocated) { |
1275 | wmb(); | |
1276 | ggtt->base.clear_range(&ggtt->base, | |
4fb84d99 | 1277 | node.start, node.size); |
4f1959ee AS |
1278 | remove_mappable_node(&node); |
1279 | } else { | |
058d88c4 | 1280 | i915_vma_unpin(vma); |
4f1959ee | 1281 | } |
fe115628 | 1282 | out_unlock: |
9c870d03 | 1283 | intel_runtime_pm_put(i915); |
fe115628 | 1284 | mutex_unlock(&i915->drm.struct_mutex); |
3de09aa3 | 1285 | return ret; |
673a394b EA |
1286 | } |
1287 | ||
3043c60c | 1288 | static int |
fe115628 | 1289 | shmem_pwrite_slow(struct page *page, int offset, int length, |
d174bd64 DV |
1290 | char __user *user_data, |
1291 | bool page_do_bit17_swizzling, | |
1292 | bool needs_clflush_before, | |
1293 | bool needs_clflush_after) | |
673a394b | 1294 | { |
d174bd64 DV |
1295 | char *vaddr; |
1296 | int ret; | |
e5281ccd | 1297 | |
d174bd64 | 1298 | vaddr = kmap(page); |
e7e58eb5 | 1299 | if (unlikely(needs_clflush_before || page_do_bit17_swizzling)) |
fe115628 | 1300 | shmem_clflush_swizzled_range(vaddr + offset, length, |
23c18c71 | 1301 | page_do_bit17_swizzling); |
d174bd64 | 1302 | if (page_do_bit17_swizzling) |
fe115628 CW |
1303 | ret = __copy_from_user_swizzled(vaddr, offset, user_data, |
1304 | length); | |
d174bd64 | 1305 | else |
fe115628 | 1306 | ret = __copy_from_user(vaddr + offset, user_data, length); |
d174bd64 | 1307 | if (needs_clflush_after) |
fe115628 | 1308 | shmem_clflush_swizzled_range(vaddr + offset, length, |
23c18c71 | 1309 | page_do_bit17_swizzling); |
d174bd64 | 1310 | kunmap(page); |
40123c1f | 1311 | |
755d2218 | 1312 | return ret ? -EFAULT : 0; |
40123c1f EA |
1313 | } |
1314 | ||
fe115628 CW |
1315 | /* Per-page copy function for the shmem pwrite fastpath. |
1316 | * Flushes invalid cachelines before writing to the target if | |
1317 | * needs_clflush_before is set and flushes out any written cachelines after | |
1318 | * writing if needs_clflush is set. | |
1319 | */ | |
40123c1f | 1320 | static int |
fe115628 CW |
1321 | shmem_pwrite(struct page *page, int offset, int len, char __user *user_data, |
1322 | bool page_do_bit17_swizzling, | |
1323 | bool needs_clflush_before, | |
1324 | bool needs_clflush_after) | |
40123c1f | 1325 | { |
fe115628 CW |
1326 | int ret; |
1327 | ||
1328 | ret = -ENODEV; | |
1329 | if (!page_do_bit17_swizzling) { | |
1330 | char *vaddr = kmap_atomic(page); | |
1331 | ||
1332 | if (needs_clflush_before) | |
1333 | drm_clflush_virt_range(vaddr + offset, len); | |
1334 | ret = __copy_from_user_inatomic(vaddr + offset, user_data, len); | |
1335 | if (needs_clflush_after) | |
1336 | drm_clflush_virt_range(vaddr + offset, len); | |
1337 | ||
1338 | kunmap_atomic(vaddr); | |
1339 | } | |
1340 | if (ret == 0) | |
1341 | return ret; | |
1342 | ||
1343 | return shmem_pwrite_slow(page, offset, len, user_data, | |
1344 | page_do_bit17_swizzling, | |
1345 | needs_clflush_before, | |
1346 | needs_clflush_after); | |
1347 | } | |
1348 | ||
1349 | static int | |
1350 | i915_gem_shmem_pwrite(struct drm_i915_gem_object *obj, | |
1351 | const struct drm_i915_gem_pwrite *args) | |
1352 | { | |
1353 | struct drm_i915_private *i915 = to_i915(obj->base.dev); | |
1354 | void __user *user_data; | |
1355 | u64 remain; | |
1356 | unsigned int obj_do_bit17_swizzling; | |
1357 | unsigned int partial_cacheline_write; | |
43394c7d | 1358 | unsigned int needs_clflush; |
fe115628 CW |
1359 | unsigned int offset, idx; |
1360 | int ret; | |
40123c1f | 1361 | |
fe115628 | 1362 | ret = mutex_lock_interruptible(&i915->drm.struct_mutex); |
755d2218 CW |
1363 | if (ret) |
1364 | return ret; | |
1365 | ||
fe115628 CW |
1366 | ret = i915_gem_obj_prepare_shmem_write(obj, &needs_clflush); |
1367 | mutex_unlock(&i915->drm.struct_mutex); | |
1368 | if (ret) | |
1369 | return ret; | |
673a394b | 1370 | |
fe115628 CW |
1371 | obj_do_bit17_swizzling = 0; |
1372 | if (i915_gem_object_needs_bit17_swizzle(obj)) | |
1373 | obj_do_bit17_swizzling = BIT(17); | |
e5281ccd | 1374 | |
fe115628 CW |
1375 | /* If we don't overwrite a cacheline completely we need to be |
1376 | * careful to have up-to-date data by first clflushing. Don't | |
1377 | * overcomplicate things and flush the entire patch. | |
1378 | */ | |
1379 | partial_cacheline_write = 0; | |
1380 | if (needs_clflush & CLFLUSH_BEFORE) | |
1381 | partial_cacheline_write = boot_cpu_data.x86_clflush_size - 1; | |
9da3da66 | 1382 | |
fe115628 CW |
1383 | user_data = u64_to_user_ptr(args->data_ptr); |
1384 | remain = args->size; | |
1385 | offset = offset_in_page(args->offset); | |
1386 | for (idx = args->offset >> PAGE_SHIFT; remain; idx++) { | |
1387 | struct page *page = i915_gem_object_get_page(obj, idx); | |
1388 | int length; | |
40123c1f | 1389 | |
fe115628 CW |
1390 | length = remain; |
1391 | if (offset + length > PAGE_SIZE) | |
1392 | length = PAGE_SIZE - offset; | |
755d2218 | 1393 | |
fe115628 CW |
1394 | ret = shmem_pwrite(page, offset, length, user_data, |
1395 | page_to_phys(page) & obj_do_bit17_swizzling, | |
1396 | (offset | length) & partial_cacheline_write, | |
1397 | needs_clflush & CLFLUSH_AFTER); | |
755d2218 | 1398 | if (ret) |
fe115628 | 1399 | break; |
755d2218 | 1400 | |
fe115628 CW |
1401 | remain -= length; |
1402 | user_data += length; | |
1403 | offset = 0; | |
8c59967c | 1404 | } |
673a394b | 1405 | |
de152b62 | 1406 | intel_fb_obj_flush(obj, false, ORIGIN_CPU); |
fe115628 | 1407 | i915_gem_obj_finish_shmem_access(obj); |
40123c1f | 1408 | return ret; |
673a394b EA |
1409 | } |
1410 | ||
1411 | /** | |
1412 | * Writes data to the object referenced by handle. | |
14bb2c11 TU |
1413 | * @dev: drm device |
1414 | * @data: ioctl data blob | |
1415 | * @file: drm file | |
673a394b EA |
1416 | * |
1417 | * On error, the contents of the buffer that were to be modified are undefined. | |
1418 | */ | |
1419 | int | |
1420 | i915_gem_pwrite_ioctl(struct drm_device *dev, void *data, | |
fbd5a26d | 1421 | struct drm_file *file) |
673a394b EA |
1422 | { |
1423 | struct drm_i915_gem_pwrite *args = data; | |
05394f39 | 1424 | struct drm_i915_gem_object *obj; |
51311d0a CW |
1425 | int ret; |
1426 | ||
1427 | if (args->size == 0) | |
1428 | return 0; | |
1429 | ||
1430 | if (!access_ok(VERIFY_READ, | |
3ed605bc | 1431 | u64_to_user_ptr(args->data_ptr), |
51311d0a CW |
1432 | args->size)) |
1433 | return -EFAULT; | |
1434 | ||
03ac0642 | 1435 | obj = i915_gem_object_lookup(file, args->handle); |
258a5ede CW |
1436 | if (!obj) |
1437 | return -ENOENT; | |
673a394b | 1438 | |
7dcd2499 | 1439 | /* Bounds check destination. */ |
05394f39 CW |
1440 | if (args->offset > obj->base.size || |
1441 | args->size > obj->base.size - args->offset) { | |
ce9d419d | 1442 | ret = -EINVAL; |
258a5ede | 1443 | goto err; |
ce9d419d CW |
1444 | } |
1445 | ||
db53a302 CW |
1446 | trace_i915_gem_object_pwrite(obj, args->offset, args->size); |
1447 | ||
e95433c7 CW |
1448 | ret = i915_gem_object_wait(obj, |
1449 | I915_WAIT_INTERRUPTIBLE | | |
1450 | I915_WAIT_ALL, | |
1451 | MAX_SCHEDULE_TIMEOUT, | |
1452 | to_rps_client(file)); | |
258a5ede CW |
1453 | if (ret) |
1454 | goto err; | |
1455 | ||
fe115628 | 1456 | ret = i915_gem_object_pin_pages(obj); |
258a5ede | 1457 | if (ret) |
fe115628 | 1458 | goto err; |
258a5ede | 1459 | |
935aaa69 | 1460 | ret = -EFAULT; |
673a394b EA |
1461 | /* We can only do the GTT pwrite on untiled buffers, as otherwise |
1462 | * it would end up going through the fenced access, and we'll get | |
1463 | * different detiling behavior between reading and writing. | |
1464 | * pread/pwrite currently are reading and writing from the CPU | |
1465 | * perspective, requiring manual detiling by the client. | |
1466 | */ | |
6eae0059 | 1467 | if (!i915_gem_object_has_struct_page(obj) || |
9c870d03 | 1468 | cpu_write_needs_clflush(obj)) |
935aaa69 DV |
1469 | /* Note that the gtt paths might fail with non-page-backed user |
1470 | * pointers (e.g. gtt mappings when moving data between | |
9c870d03 CW |
1471 | * textures). Fallback to the shmem path in that case. |
1472 | */ | |
fe115628 | 1473 | ret = i915_gem_gtt_pwrite_fast(obj, args); |
673a394b | 1474 | |
d1054ee4 | 1475 | if (ret == -EFAULT || ret == -ENOSPC) { |
6a2c4232 CW |
1476 | if (obj->phys_handle) |
1477 | ret = i915_gem_phys_pwrite(obj, args, file); | |
b50a5371 | 1478 | else |
fe115628 | 1479 | ret = i915_gem_shmem_pwrite(obj, args); |
6a2c4232 | 1480 | } |
5c0480f2 | 1481 | |
fe115628 | 1482 | i915_gem_object_unpin_pages(obj); |
258a5ede | 1483 | err: |
f0cd5182 | 1484 | i915_gem_object_put(obj); |
258a5ede | 1485 | return ret; |
673a394b EA |
1486 | } |
1487 | ||
d243ad82 | 1488 | static inline enum fb_op_origin |
aeecc969 CW |
1489 | write_origin(struct drm_i915_gem_object *obj, unsigned domain) |
1490 | { | |
50349247 CW |
1491 | return (domain == I915_GEM_DOMAIN_GTT ? |
1492 | obj->frontbuffer_ggtt_origin : ORIGIN_CPU); | |
aeecc969 CW |
1493 | } |
1494 | ||
40e62d5d CW |
1495 | static void i915_gem_object_bump_inactive_ggtt(struct drm_i915_gem_object *obj) |
1496 | { | |
1497 | struct drm_i915_private *i915; | |
1498 | struct list_head *list; | |
1499 | struct i915_vma *vma; | |
1500 | ||
1501 | list_for_each_entry(vma, &obj->vma_list, obj_link) { | |
1502 | if (!i915_vma_is_ggtt(vma)) | |
1503 | continue; | |
1504 | ||
1505 | if (i915_vma_is_active(vma)) | |
1506 | continue; | |
1507 | ||
1508 | if (!drm_mm_node_allocated(&vma->node)) | |
1509 | continue; | |
1510 | ||
1511 | list_move_tail(&vma->vm_link, &vma->vm->inactive_list); | |
1512 | } | |
1513 | ||
1514 | i915 = to_i915(obj->base.dev); | |
1515 | list = obj->bind_count ? &i915->mm.bound_list : &i915->mm.unbound_list; | |
56cea323 | 1516 | list_move_tail(&obj->global_link, list); |
40e62d5d CW |
1517 | } |
1518 | ||
673a394b | 1519 | /** |
2ef7eeaa EA |
1520 | * Called when user space prepares to use an object with the CPU, either |
1521 | * through the mmap ioctl's mapping or a GTT mapping. | |
14bb2c11 TU |
1522 | * @dev: drm device |
1523 | * @data: ioctl data blob | |
1524 | * @file: drm file | |
673a394b EA |
1525 | */ |
1526 | int | |
1527 | i915_gem_set_domain_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 1528 | struct drm_file *file) |
673a394b EA |
1529 | { |
1530 | struct drm_i915_gem_set_domain *args = data; | |
05394f39 | 1531 | struct drm_i915_gem_object *obj; |
2ef7eeaa EA |
1532 | uint32_t read_domains = args->read_domains; |
1533 | uint32_t write_domain = args->write_domain; | |
40e62d5d | 1534 | int err; |
673a394b | 1535 | |
2ef7eeaa | 1536 | /* Only handle setting domains to types used by the CPU. */ |
b8f9096d | 1537 | if ((write_domain | read_domains) & I915_GEM_GPU_DOMAINS) |
2ef7eeaa EA |
1538 | return -EINVAL; |
1539 | ||
1540 | /* Having something in the write domain implies it's in the read | |
1541 | * domain, and only that read domain. Enforce that in the request. | |
1542 | */ | |
1543 | if (write_domain != 0 && read_domains != write_domain) | |
1544 | return -EINVAL; | |
1545 | ||
03ac0642 | 1546 | obj = i915_gem_object_lookup(file, args->handle); |
b8f9096d CW |
1547 | if (!obj) |
1548 | return -ENOENT; | |
673a394b | 1549 | |
3236f57a CW |
1550 | /* Try to flush the object off the GPU without holding the lock. |
1551 | * We will repeat the flush holding the lock in the normal manner | |
1552 | * to catch cases where we are gazumped. | |
1553 | */ | |
40e62d5d | 1554 | err = i915_gem_object_wait(obj, |
e95433c7 CW |
1555 | I915_WAIT_INTERRUPTIBLE | |
1556 | (write_domain ? I915_WAIT_ALL : 0), | |
1557 | MAX_SCHEDULE_TIMEOUT, | |
1558 | to_rps_client(file)); | |
40e62d5d | 1559 | if (err) |
f0cd5182 | 1560 | goto out; |
b8f9096d | 1561 | |
40e62d5d CW |
1562 | /* Flush and acquire obj->pages so that we are coherent through |
1563 | * direct access in memory with previous cached writes through | |
1564 | * shmemfs and that our cache domain tracking remains valid. | |
1565 | * For example, if the obj->filp was moved to swap without us | |
1566 | * being notified and releasing the pages, we would mistakenly | |
1567 | * continue to assume that the obj remained out of the CPU cached | |
1568 | * domain. | |
1569 | */ | |
1570 | err = i915_gem_object_pin_pages(obj); | |
1571 | if (err) | |
f0cd5182 | 1572 | goto out; |
40e62d5d CW |
1573 | |
1574 | err = i915_mutex_lock_interruptible(dev); | |
1575 | if (err) | |
f0cd5182 | 1576 | goto out_unpin; |
3236f57a | 1577 | |
43566ded | 1578 | if (read_domains & I915_GEM_DOMAIN_GTT) |
40e62d5d | 1579 | err = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0); |
43566ded | 1580 | else |
40e62d5d | 1581 | err = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0); |
2ef7eeaa | 1582 | |
40e62d5d CW |
1583 | /* And bump the LRU for this access */ |
1584 | i915_gem_object_bump_inactive_ggtt(obj); | |
031b698a | 1585 | |
673a394b | 1586 | mutex_unlock(&dev->struct_mutex); |
b8f9096d | 1587 | |
40e62d5d CW |
1588 | if (write_domain != 0) |
1589 | intel_fb_obj_invalidate(obj, write_origin(obj, write_domain)); | |
1590 | ||
f0cd5182 | 1591 | out_unpin: |
40e62d5d | 1592 | i915_gem_object_unpin_pages(obj); |
f0cd5182 CW |
1593 | out: |
1594 | i915_gem_object_put(obj); | |
40e62d5d | 1595 | return err; |
673a394b EA |
1596 | } |
1597 | ||
1598 | /** | |
1599 | * Called when user space has done writes to this buffer | |
14bb2c11 TU |
1600 | * @dev: drm device |
1601 | * @data: ioctl data blob | |
1602 | * @file: drm file | |
673a394b EA |
1603 | */ |
1604 | int | |
1605 | i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 1606 | struct drm_file *file) |
673a394b EA |
1607 | { |
1608 | struct drm_i915_gem_sw_finish *args = data; | |
05394f39 | 1609 | struct drm_i915_gem_object *obj; |
c21724cc | 1610 | int err = 0; |
1d7cfea1 | 1611 | |
03ac0642 | 1612 | obj = i915_gem_object_lookup(file, args->handle); |
c21724cc CW |
1613 | if (!obj) |
1614 | return -ENOENT; | |
673a394b | 1615 | |
673a394b | 1616 | /* Pinned buffers may be scanout, so flush the cache */ |
c21724cc CW |
1617 | if (READ_ONCE(obj->pin_display)) { |
1618 | err = i915_mutex_lock_interruptible(dev); | |
1619 | if (!err) { | |
1620 | i915_gem_object_flush_cpu_write_domain(obj); | |
1621 | mutex_unlock(&dev->struct_mutex); | |
1622 | } | |
1623 | } | |
e47c68e9 | 1624 | |
f0cd5182 | 1625 | i915_gem_object_put(obj); |
c21724cc | 1626 | return err; |
673a394b EA |
1627 | } |
1628 | ||
1629 | /** | |
14bb2c11 TU |
1630 | * i915_gem_mmap_ioctl - Maps the contents of an object, returning the address |
1631 | * it is mapped to. | |
1632 | * @dev: drm device | |
1633 | * @data: ioctl data blob | |
1634 | * @file: drm file | |
673a394b EA |
1635 | * |
1636 | * While the mapping holds a reference on the contents of the object, it doesn't | |
1637 | * imply a ref on the object itself. | |
34367381 DV |
1638 | * |
1639 | * IMPORTANT: | |
1640 | * | |
1641 | * DRM driver writers who look a this function as an example for how to do GEM | |
1642 | * mmap support, please don't implement mmap support like here. The modern way | |
1643 | * to implement DRM mmap support is with an mmap offset ioctl (like | |
1644 | * i915_gem_mmap_gtt) and then using the mmap syscall on the DRM fd directly. | |
1645 | * That way debug tooling like valgrind will understand what's going on, hiding | |
1646 | * the mmap call in a driver private ioctl will break that. The i915 driver only | |
1647 | * does cpu mmaps this way because we didn't know better. | |
673a394b EA |
1648 | */ |
1649 | int | |
1650 | i915_gem_mmap_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 1651 | struct drm_file *file) |
673a394b EA |
1652 | { |
1653 | struct drm_i915_gem_mmap *args = data; | |
03ac0642 | 1654 | struct drm_i915_gem_object *obj; |
673a394b EA |
1655 | unsigned long addr; |
1656 | ||
1816f923 AG |
1657 | if (args->flags & ~(I915_MMAP_WC)) |
1658 | return -EINVAL; | |
1659 | ||
568a58e5 | 1660 | if (args->flags & I915_MMAP_WC && !boot_cpu_has(X86_FEATURE_PAT)) |
1816f923 AG |
1661 | return -ENODEV; |
1662 | ||
03ac0642 CW |
1663 | obj = i915_gem_object_lookup(file, args->handle); |
1664 | if (!obj) | |
bf79cb91 | 1665 | return -ENOENT; |
673a394b | 1666 | |
1286ff73 DV |
1667 | /* prime objects have no backing filp to GEM mmap |
1668 | * pages from. | |
1669 | */ | |
03ac0642 | 1670 | if (!obj->base.filp) { |
f0cd5182 | 1671 | i915_gem_object_put(obj); |
1286ff73 DV |
1672 | return -EINVAL; |
1673 | } | |
1674 | ||
03ac0642 | 1675 | addr = vm_mmap(obj->base.filp, 0, args->size, |
673a394b EA |
1676 | PROT_READ | PROT_WRITE, MAP_SHARED, |
1677 | args->offset); | |
1816f923 AG |
1678 | if (args->flags & I915_MMAP_WC) { |
1679 | struct mm_struct *mm = current->mm; | |
1680 | struct vm_area_struct *vma; | |
1681 | ||
80a89a5e | 1682 | if (down_write_killable(&mm->mmap_sem)) { |
f0cd5182 | 1683 | i915_gem_object_put(obj); |
80a89a5e MH |
1684 | return -EINTR; |
1685 | } | |
1816f923 AG |
1686 | vma = find_vma(mm, addr); |
1687 | if (vma) | |
1688 | vma->vm_page_prot = | |
1689 | pgprot_writecombine(vm_get_page_prot(vma->vm_flags)); | |
1690 | else | |
1691 | addr = -ENOMEM; | |
1692 | up_write(&mm->mmap_sem); | |
aeecc969 CW |
1693 | |
1694 | /* This may race, but that's ok, it only gets set */ | |
50349247 | 1695 | WRITE_ONCE(obj->frontbuffer_ggtt_origin, ORIGIN_CPU); |
1816f923 | 1696 | } |
f0cd5182 | 1697 | i915_gem_object_put(obj); |
673a394b EA |
1698 | if (IS_ERR((void *)addr)) |
1699 | return addr; | |
1700 | ||
1701 | args->addr_ptr = (uint64_t) addr; | |
1702 | ||
1703 | return 0; | |
1704 | } | |
1705 | ||
03af84fe CW |
1706 | static unsigned int tile_row_pages(struct drm_i915_gem_object *obj) |
1707 | { | |
1708 | u64 size; | |
1709 | ||
1710 | size = i915_gem_object_get_stride(obj); | |
1711 | size *= i915_gem_object_get_tiling(obj) == I915_TILING_Y ? 32 : 8; | |
1712 | ||
1713 | return size >> PAGE_SHIFT; | |
1714 | } | |
1715 | ||
4cc69075 CW |
1716 | /** |
1717 | * i915_gem_mmap_gtt_version - report the current feature set for GTT mmaps | |
1718 | * | |
1719 | * A history of the GTT mmap interface: | |
1720 | * | |
1721 | * 0 - Everything had to fit into the GTT. Both parties of a memcpy had to | |
1722 | * aligned and suitable for fencing, and still fit into the available | |
1723 | * mappable space left by the pinned display objects. A classic problem | |
1724 | * we called the page-fault-of-doom where we would ping-pong between | |
1725 | * two objects that could not fit inside the GTT and so the memcpy | |
1726 | * would page one object in at the expense of the other between every | |
1727 | * single byte. | |
1728 | * | |
1729 | * 1 - Objects can be any size, and have any compatible fencing (X Y, or none | |
1730 | * as set via i915_gem_set_tiling() [DRM_I915_GEM_SET_TILING]). If the | |
1731 | * object is too large for the available space (or simply too large | |
1732 | * for the mappable aperture!), a view is created instead and faulted | |
1733 | * into userspace. (This view is aligned and sized appropriately for | |
1734 | * fenced access.) | |
1735 | * | |
1736 | * Restrictions: | |
1737 | * | |
1738 | * * snoopable objects cannot be accessed via the GTT. It can cause machine | |
1739 | * hangs on some architectures, corruption on others. An attempt to service | |
1740 | * a GTT page fault from a snoopable object will generate a SIGBUS. | |
1741 | * | |
1742 | * * the object must be able to fit into RAM (physical memory, though no | |
1743 | * limited to the mappable aperture). | |
1744 | * | |
1745 | * | |
1746 | * Caveats: | |
1747 | * | |
1748 | * * a new GTT page fault will synchronize rendering from the GPU and flush | |
1749 | * all data to system memory. Subsequent access will not be synchronized. | |
1750 | * | |
1751 | * * all mappings are revoked on runtime device suspend. | |
1752 | * | |
1753 | * * there are only 8, 16 or 32 fence registers to share between all users | |
1754 | * (older machines require fence register for display and blitter access | |
1755 | * as well). Contention of the fence registers will cause the previous users | |
1756 | * to be unmapped and any new access will generate new page faults. | |
1757 | * | |
1758 | * * running out of memory while servicing a fault may generate a SIGBUS, | |
1759 | * rather than the expected SIGSEGV. | |
1760 | */ | |
1761 | int i915_gem_mmap_gtt_version(void) | |
1762 | { | |
1763 | return 1; | |
1764 | } | |
1765 | ||
de151cf6 JB |
1766 | /** |
1767 | * i915_gem_fault - fault a page into the GTT | |
058d88c4 | 1768 | * @area: CPU VMA in question |
d9072a3e | 1769 | * @vmf: fault info |
de151cf6 JB |
1770 | * |
1771 | * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped | |
1772 | * from userspace. The fault handler takes care of binding the object to | |
1773 | * the GTT (if needed), allocating and programming a fence register (again, | |
1774 | * only if needed based on whether the old reg is still valid or the object | |
1775 | * is tiled) and inserting a new PTE into the faulting process. | |
1776 | * | |
1777 | * Note that the faulting process may involve evicting existing objects | |
1778 | * from the GTT and/or fence registers to make room. So performance may | |
1779 | * suffer if the GTT working set is large or there are few fence registers | |
1780 | * left. | |
4cc69075 CW |
1781 | * |
1782 | * The current feature set supported by i915_gem_fault() and thus GTT mmaps | |
1783 | * is exposed via I915_PARAM_MMAP_GTT_VERSION (see i915_gem_mmap_gtt_version). | |
de151cf6 | 1784 | */ |
058d88c4 | 1785 | int i915_gem_fault(struct vm_area_struct *area, struct vm_fault *vmf) |
de151cf6 | 1786 | { |
03af84fe | 1787 | #define MIN_CHUNK_PAGES ((1 << 20) >> PAGE_SHIFT) /* 1 MiB */ |
058d88c4 | 1788 | struct drm_i915_gem_object *obj = to_intel_bo(area->vm_private_data); |
05394f39 | 1789 | struct drm_device *dev = obj->base.dev; |
72e96d64 JL |
1790 | struct drm_i915_private *dev_priv = to_i915(dev); |
1791 | struct i915_ggtt *ggtt = &dev_priv->ggtt; | |
b8f9096d | 1792 | bool write = !!(vmf->flags & FAULT_FLAG_WRITE); |
058d88c4 | 1793 | struct i915_vma *vma; |
de151cf6 | 1794 | pgoff_t page_offset; |
82118877 | 1795 | unsigned int flags; |
b8f9096d | 1796 | int ret; |
f65c9168 | 1797 | |
de151cf6 | 1798 | /* We don't use vmf->pgoff since that has the fake offset */ |
058d88c4 | 1799 | page_offset = ((unsigned long)vmf->virtual_address - area->vm_start) >> |
de151cf6 JB |
1800 | PAGE_SHIFT; |
1801 | ||
db53a302 CW |
1802 | trace_i915_gem_object_fault(obj, page_offset, true, write); |
1803 | ||
6e4930f6 | 1804 | /* Try to flush the object off the GPU first without holding the lock. |
b8f9096d | 1805 | * Upon acquiring the lock, we will perform our sanity checks and then |
6e4930f6 CW |
1806 | * repeat the flush holding the lock in the normal manner to catch cases |
1807 | * where we are gazumped. | |
1808 | */ | |
e95433c7 CW |
1809 | ret = i915_gem_object_wait(obj, |
1810 | I915_WAIT_INTERRUPTIBLE, | |
1811 | MAX_SCHEDULE_TIMEOUT, | |
1812 | NULL); | |
6e4930f6 | 1813 | if (ret) |
b8f9096d CW |
1814 | goto err; |
1815 | ||
40e62d5d CW |
1816 | ret = i915_gem_object_pin_pages(obj); |
1817 | if (ret) | |
1818 | goto err; | |
1819 | ||
b8f9096d CW |
1820 | intel_runtime_pm_get(dev_priv); |
1821 | ||
1822 | ret = i915_mutex_lock_interruptible(dev); | |
1823 | if (ret) | |
1824 | goto err_rpm; | |
6e4930f6 | 1825 | |
eb119bd6 | 1826 | /* Access to snoopable pages through the GTT is incoherent. */ |
0031fb96 | 1827 | if (obj->cache_level != I915_CACHE_NONE && !HAS_LLC(dev_priv)) { |
ddeff6ee | 1828 | ret = -EFAULT; |
b8f9096d | 1829 | goto err_unlock; |
eb119bd6 CW |
1830 | } |
1831 | ||
82118877 CW |
1832 | /* If the object is smaller than a couple of partial vma, it is |
1833 | * not worth only creating a single partial vma - we may as well | |
1834 | * clear enough space for the full object. | |
1835 | */ | |
1836 | flags = PIN_MAPPABLE; | |
1837 | if (obj->base.size > 2 * MIN_CHUNK_PAGES << PAGE_SHIFT) | |
1838 | flags |= PIN_NONBLOCK | PIN_NONFAULT; | |
1839 | ||
a61007a8 | 1840 | /* Now pin it into the GTT as needed */ |
82118877 | 1841 | vma = i915_gem_object_ggtt_pin(obj, NULL, 0, 0, flags); |
a61007a8 CW |
1842 | if (IS_ERR(vma)) { |
1843 | struct i915_ggtt_view view; | |
03af84fe CW |
1844 | unsigned int chunk_size; |
1845 | ||
a61007a8 | 1846 | /* Use a partial view if it is bigger than available space */ |
03af84fe CW |
1847 | chunk_size = MIN_CHUNK_PAGES; |
1848 | if (i915_gem_object_is_tiled(obj)) | |
0ef723cb | 1849 | chunk_size = roundup(chunk_size, tile_row_pages(obj)); |
e7ded2d7 | 1850 | |
c5ad54cf JL |
1851 | memset(&view, 0, sizeof(view)); |
1852 | view.type = I915_GGTT_VIEW_PARTIAL; | |
1853 | view.params.partial.offset = rounddown(page_offset, chunk_size); | |
1854 | view.params.partial.size = | |
a61007a8 | 1855 | min_t(unsigned int, chunk_size, |
908b1232 | 1856 | vma_pages(area) - view.params.partial.offset); |
c5ad54cf | 1857 | |
aa136d9d CW |
1858 | /* If the partial covers the entire object, just create a |
1859 | * normal VMA. | |
1860 | */ | |
1861 | if (chunk_size >= obj->base.size >> PAGE_SHIFT) | |
1862 | view.type = I915_GGTT_VIEW_NORMAL; | |
1863 | ||
50349247 CW |
1864 | /* Userspace is now writing through an untracked VMA, abandon |
1865 | * all hope that the hardware is able to track future writes. | |
1866 | */ | |
1867 | obj->frontbuffer_ggtt_origin = ORIGIN_CPU; | |
1868 | ||
a61007a8 CW |
1869 | vma = i915_gem_object_ggtt_pin(obj, &view, 0, 0, PIN_MAPPABLE); |
1870 | } | |
058d88c4 CW |
1871 | if (IS_ERR(vma)) { |
1872 | ret = PTR_ERR(vma); | |
b8f9096d | 1873 | goto err_unlock; |
058d88c4 | 1874 | } |
4a684a41 | 1875 | |
c9839303 CW |
1876 | ret = i915_gem_object_set_to_gtt_domain(obj, write); |
1877 | if (ret) | |
b8f9096d | 1878 | goto err_unpin; |
74898d7e | 1879 | |
49ef5294 | 1880 | ret = i915_vma_get_fence(vma); |
d9e86c0e | 1881 | if (ret) |
b8f9096d | 1882 | goto err_unpin; |
7d1c4804 | 1883 | |
275f039d | 1884 | /* Mark as being mmapped into userspace for later revocation */ |
9c870d03 | 1885 | assert_rpm_wakelock_held(dev_priv); |
275f039d CW |
1886 | if (list_empty(&obj->userfault_link)) |
1887 | list_add(&obj->userfault_link, &dev_priv->mm.userfault_list); | |
275f039d | 1888 | |
b90b91d8 | 1889 | /* Finally, remap it using the new GTT offset */ |
c58305af CW |
1890 | ret = remap_io_mapping(area, |
1891 | area->vm_start + (vma->ggtt_view.params.partial.offset << PAGE_SHIFT), | |
1892 | (ggtt->mappable_base + vma->node.start) >> PAGE_SHIFT, | |
1893 | min_t(u64, vma->size, area->vm_end - area->vm_start), | |
1894 | &ggtt->mappable); | |
a61007a8 | 1895 | |
b8f9096d | 1896 | err_unpin: |
058d88c4 | 1897 | __i915_vma_unpin(vma); |
b8f9096d | 1898 | err_unlock: |
de151cf6 | 1899 | mutex_unlock(&dev->struct_mutex); |
b8f9096d CW |
1900 | err_rpm: |
1901 | intel_runtime_pm_put(dev_priv); | |
40e62d5d | 1902 | i915_gem_object_unpin_pages(obj); |
b8f9096d | 1903 | err: |
de151cf6 | 1904 | switch (ret) { |
d9bc7e9f | 1905 | case -EIO: |
2232f031 DV |
1906 | /* |
1907 | * We eat errors when the gpu is terminally wedged to avoid | |
1908 | * userspace unduly crashing (gl has no provisions for mmaps to | |
1909 | * fail). But any other -EIO isn't ours (e.g. swap in failure) | |
1910 | * and so needs to be reported. | |
1911 | */ | |
1912 | if (!i915_terminally_wedged(&dev_priv->gpu_error)) { | |
f65c9168 PZ |
1913 | ret = VM_FAULT_SIGBUS; |
1914 | break; | |
1915 | } | |
045e769a | 1916 | case -EAGAIN: |
571c608d DV |
1917 | /* |
1918 | * EAGAIN means the gpu is hung and we'll wait for the error | |
1919 | * handler to reset everything when re-faulting in | |
1920 | * i915_mutex_lock_interruptible. | |
d9bc7e9f | 1921 | */ |
c715089f CW |
1922 | case 0: |
1923 | case -ERESTARTSYS: | |
bed636ab | 1924 | case -EINTR: |
e79e0fe3 DR |
1925 | case -EBUSY: |
1926 | /* | |
1927 | * EBUSY is ok: this just means that another thread | |
1928 | * already did the job. | |
1929 | */ | |
f65c9168 PZ |
1930 | ret = VM_FAULT_NOPAGE; |
1931 | break; | |
de151cf6 | 1932 | case -ENOMEM: |
f65c9168 PZ |
1933 | ret = VM_FAULT_OOM; |
1934 | break; | |
a7c2e1aa | 1935 | case -ENOSPC: |
45d67817 | 1936 | case -EFAULT: |
f65c9168 PZ |
1937 | ret = VM_FAULT_SIGBUS; |
1938 | break; | |
de151cf6 | 1939 | default: |
a7c2e1aa | 1940 | WARN_ONCE(ret, "unhandled error in i915_gem_fault: %i\n", ret); |
f65c9168 PZ |
1941 | ret = VM_FAULT_SIGBUS; |
1942 | break; | |
de151cf6 | 1943 | } |
f65c9168 | 1944 | return ret; |
de151cf6 JB |
1945 | } |
1946 | ||
901782b2 CW |
1947 | /** |
1948 | * i915_gem_release_mmap - remove physical page mappings | |
1949 | * @obj: obj in question | |
1950 | * | |
af901ca1 | 1951 | * Preserve the reservation of the mmapping with the DRM core code, but |
901782b2 CW |
1952 | * relinquish ownership of the pages back to the system. |
1953 | * | |
1954 | * It is vital that we remove the page mapping if we have mapped a tiled | |
1955 | * object through the GTT and then lose the fence register due to | |
1956 | * resource pressure. Similarly if the object has been moved out of the | |
1957 | * aperture, than pages mapped into userspace must be revoked. Removing the | |
1958 | * mapping will then trigger a page fault on the next user access, allowing | |
1959 | * fixup by i915_gem_fault(). | |
1960 | */ | |
d05ca301 | 1961 | void |
05394f39 | 1962 | i915_gem_release_mmap(struct drm_i915_gem_object *obj) |
901782b2 | 1963 | { |
275f039d | 1964 | struct drm_i915_private *i915 = to_i915(obj->base.dev); |
275f039d | 1965 | |
349f2ccf CW |
1966 | /* Serialisation between user GTT access and our code depends upon |
1967 | * revoking the CPU's PTE whilst the mutex is held. The next user | |
1968 | * pagefault then has to wait until we release the mutex. | |
9c870d03 CW |
1969 | * |
1970 | * Note that RPM complicates somewhat by adding an additional | |
1971 | * requirement that operations to the GGTT be made holding the RPM | |
1972 | * wakeref. | |
349f2ccf | 1973 | */ |
275f039d | 1974 | lockdep_assert_held(&i915->drm.struct_mutex); |
9c870d03 | 1975 | intel_runtime_pm_get(i915); |
349f2ccf | 1976 | |
3594a3e2 | 1977 | if (list_empty(&obj->userfault_link)) |
9c870d03 | 1978 | goto out; |
901782b2 | 1979 | |
3594a3e2 | 1980 | list_del_init(&obj->userfault_link); |
6796cb16 DH |
1981 | drm_vma_node_unmap(&obj->base.vma_node, |
1982 | obj->base.dev->anon_inode->i_mapping); | |
349f2ccf CW |
1983 | |
1984 | /* Ensure that the CPU's PTE are revoked and there are not outstanding | |
1985 | * memory transactions from userspace before we return. The TLB | |
1986 | * flushing implied above by changing the PTE above *should* be | |
1987 | * sufficient, an extra barrier here just provides us with a bit | |
1988 | * of paranoid documentation about our requirement to serialise | |
1989 | * memory writes before touching registers / GSM. | |
1990 | */ | |
1991 | wmb(); | |
9c870d03 CW |
1992 | |
1993 | out: | |
1994 | intel_runtime_pm_put(i915); | |
901782b2 CW |
1995 | } |
1996 | ||
7c108fd8 | 1997 | void i915_gem_runtime_suspend(struct drm_i915_private *dev_priv) |
eedd10f4 | 1998 | { |
3594a3e2 | 1999 | struct drm_i915_gem_object *obj, *on; |
7c108fd8 | 2000 | int i; |
eedd10f4 | 2001 | |
3594a3e2 CW |
2002 | /* |
2003 | * Only called during RPM suspend. All users of the userfault_list | |
2004 | * must be holding an RPM wakeref to ensure that this can not | |
2005 | * run concurrently with themselves (and use the struct_mutex for | |
2006 | * protection between themselves). | |
2007 | */ | |
275f039d | 2008 | |
3594a3e2 CW |
2009 | list_for_each_entry_safe(obj, on, |
2010 | &dev_priv->mm.userfault_list, userfault_link) { | |
2011 | list_del_init(&obj->userfault_link); | |
275f039d CW |
2012 | drm_vma_node_unmap(&obj->base.vma_node, |
2013 | obj->base.dev->anon_inode->i_mapping); | |
275f039d | 2014 | } |
7c108fd8 CW |
2015 | |
2016 | /* The fence will be lost when the device powers down. If any were | |
2017 | * in use by hardware (i.e. they are pinned), we should not be powering | |
2018 | * down! All other fences will be reacquired by the user upon waking. | |
2019 | */ | |
2020 | for (i = 0; i < dev_priv->num_fence_regs; i++) { | |
2021 | struct drm_i915_fence_reg *reg = &dev_priv->fence_regs[i]; | |
2022 | ||
2023 | if (WARN_ON(reg->pin_count)) | |
2024 | continue; | |
2025 | ||
2026 | if (!reg->vma) | |
2027 | continue; | |
2028 | ||
2029 | GEM_BUG_ON(!list_empty(®->vma->obj->userfault_link)); | |
2030 | reg->dirty = true; | |
2031 | } | |
eedd10f4 CW |
2032 | } |
2033 | ||
ad1a7d20 CW |
2034 | /** |
2035 | * i915_gem_get_ggtt_size - return required global GTT size for an object | |
a9f1481f | 2036 | * @dev_priv: i915 device |
ad1a7d20 CW |
2037 | * @size: object size |
2038 | * @tiling_mode: tiling mode | |
2039 | * | |
2040 | * Return the required global GTT size for an object, taking into account | |
2041 | * potential fence register mapping. | |
2042 | */ | |
a9f1481f CW |
2043 | u64 i915_gem_get_ggtt_size(struct drm_i915_private *dev_priv, |
2044 | u64 size, int tiling_mode) | |
92b88aeb | 2045 | { |
ad1a7d20 | 2046 | u64 ggtt_size; |
92b88aeb | 2047 | |
ad1a7d20 CW |
2048 | GEM_BUG_ON(size == 0); |
2049 | ||
a9f1481f | 2050 | if (INTEL_GEN(dev_priv) >= 4 || |
e28f8711 CW |
2051 | tiling_mode == I915_TILING_NONE) |
2052 | return size; | |
92b88aeb CW |
2053 | |
2054 | /* Previous chips need a power-of-two fence region when tiling */ | |
a9f1481f | 2055 | if (IS_GEN3(dev_priv)) |
ad1a7d20 | 2056 | ggtt_size = 1024*1024; |
92b88aeb | 2057 | else |
ad1a7d20 | 2058 | ggtt_size = 512*1024; |
92b88aeb | 2059 | |
ad1a7d20 CW |
2060 | while (ggtt_size < size) |
2061 | ggtt_size <<= 1; | |
92b88aeb | 2062 | |
ad1a7d20 | 2063 | return ggtt_size; |
92b88aeb CW |
2064 | } |
2065 | ||
de151cf6 | 2066 | /** |
ad1a7d20 | 2067 | * i915_gem_get_ggtt_alignment - return required global GTT alignment |
a9f1481f | 2068 | * @dev_priv: i915 device |
14bb2c11 TU |
2069 | * @size: object size |
2070 | * @tiling_mode: tiling mode | |
ad1a7d20 | 2071 | * @fenced: is fenced alignment required or not |
de151cf6 | 2072 | * |
ad1a7d20 | 2073 | * Return the required global GTT alignment for an object, taking into account |
5e783301 | 2074 | * potential fence register mapping. |
de151cf6 | 2075 | */ |
a9f1481f | 2076 | u64 i915_gem_get_ggtt_alignment(struct drm_i915_private *dev_priv, u64 size, |
ad1a7d20 | 2077 | int tiling_mode, bool fenced) |
de151cf6 | 2078 | { |
ad1a7d20 CW |
2079 | GEM_BUG_ON(size == 0); |
2080 | ||
de151cf6 JB |
2081 | /* |
2082 | * Minimum alignment is 4k (GTT page size), but might be greater | |
2083 | * if a fence register is needed for the object. | |
2084 | */ | |
a9f1481f | 2085 | if (INTEL_GEN(dev_priv) >= 4 || (!fenced && IS_G33(dev_priv)) || |
e28f8711 | 2086 | tiling_mode == I915_TILING_NONE) |
de151cf6 JB |
2087 | return 4096; |
2088 | ||
a00b10c3 CW |
2089 | /* |
2090 | * Previous chips need to be aligned to the size of the smallest | |
2091 | * fence register that can contain the object. | |
2092 | */ | |
a9f1481f | 2093 | return i915_gem_get_ggtt_size(dev_priv, size, tiling_mode); |
a00b10c3 CW |
2094 | } |
2095 | ||
d8cb5086 CW |
2096 | static int i915_gem_object_create_mmap_offset(struct drm_i915_gem_object *obj) |
2097 | { | |
fac5e23e | 2098 | struct drm_i915_private *dev_priv = to_i915(obj->base.dev); |
f3f6184c | 2099 | int err; |
da494d7c | 2100 | |
f3f6184c CW |
2101 | err = drm_gem_create_mmap_offset(&obj->base); |
2102 | if (!err) | |
2103 | return 0; | |
d8cb5086 | 2104 | |
f3f6184c CW |
2105 | /* We can idle the GPU locklessly to flush stale objects, but in order |
2106 | * to claim that space for ourselves, we need to take the big | |
2107 | * struct_mutex to free the requests+objects and allocate our slot. | |
d8cb5086 | 2108 | */ |
ea746f36 | 2109 | err = i915_gem_wait_for_idle(dev_priv, I915_WAIT_INTERRUPTIBLE); |
f3f6184c CW |
2110 | if (err) |
2111 | return err; | |
2112 | ||
2113 | err = i915_mutex_lock_interruptible(&dev_priv->drm); | |
2114 | if (!err) { | |
2115 | i915_gem_retire_requests(dev_priv); | |
2116 | err = drm_gem_create_mmap_offset(&obj->base); | |
2117 | mutex_unlock(&dev_priv->drm.struct_mutex); | |
2118 | } | |
da494d7c | 2119 | |
f3f6184c | 2120 | return err; |
d8cb5086 CW |
2121 | } |
2122 | ||
2123 | static void i915_gem_object_free_mmap_offset(struct drm_i915_gem_object *obj) | |
2124 | { | |
d8cb5086 CW |
2125 | drm_gem_free_mmap_offset(&obj->base); |
2126 | } | |
2127 | ||
da6b51d0 | 2128 | int |
ff72145b DA |
2129 | i915_gem_mmap_gtt(struct drm_file *file, |
2130 | struct drm_device *dev, | |
da6b51d0 | 2131 | uint32_t handle, |
ff72145b | 2132 | uint64_t *offset) |
de151cf6 | 2133 | { |
05394f39 | 2134 | struct drm_i915_gem_object *obj; |
de151cf6 JB |
2135 | int ret; |
2136 | ||
03ac0642 | 2137 | obj = i915_gem_object_lookup(file, handle); |
f3f6184c CW |
2138 | if (!obj) |
2139 | return -ENOENT; | |
ab18282d | 2140 | |
d8cb5086 | 2141 | ret = i915_gem_object_create_mmap_offset(obj); |
f3f6184c CW |
2142 | if (ret == 0) |
2143 | *offset = drm_vma_node_offset_addr(&obj->base.vma_node); | |
de151cf6 | 2144 | |
f0cd5182 | 2145 | i915_gem_object_put(obj); |
1d7cfea1 | 2146 | return ret; |
de151cf6 JB |
2147 | } |
2148 | ||
ff72145b DA |
2149 | /** |
2150 | * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing | |
2151 | * @dev: DRM device | |
2152 | * @data: GTT mapping ioctl data | |
2153 | * @file: GEM object info | |
2154 | * | |
2155 | * Simply returns the fake offset to userspace so it can mmap it. | |
2156 | * The mmap call will end up in drm_gem_mmap(), which will set things | |
2157 | * up so we can get faults in the handler above. | |
2158 | * | |
2159 | * The fault handler will take care of binding the object into the GTT | |
2160 | * (since it may have been evicted to make room for something), allocating | |
2161 | * a fence register, and mapping the appropriate aperture address into | |
2162 | * userspace. | |
2163 | */ | |
2164 | int | |
2165 | i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data, | |
2166 | struct drm_file *file) | |
2167 | { | |
2168 | struct drm_i915_gem_mmap_gtt *args = data; | |
2169 | ||
da6b51d0 | 2170 | return i915_gem_mmap_gtt(file, dev, args->handle, &args->offset); |
ff72145b DA |
2171 | } |
2172 | ||
225067ee DV |
2173 | /* Immediately discard the backing storage */ |
2174 | static void | |
2175 | i915_gem_object_truncate(struct drm_i915_gem_object *obj) | |
e5281ccd | 2176 | { |
4d6294bf | 2177 | i915_gem_object_free_mmap_offset(obj); |
1286ff73 | 2178 | |
4d6294bf CW |
2179 | if (obj->base.filp == NULL) |
2180 | return; | |
e5281ccd | 2181 | |
225067ee DV |
2182 | /* Our goal here is to return as much of the memory as |
2183 | * is possible back to the system as we are called from OOM. | |
2184 | * To do this we must instruct the shmfs to drop all of its | |
2185 | * backing pages, *now*. | |
2186 | */ | |
5537252b | 2187 | shmem_truncate_range(file_inode(obj->base.filp), 0, (loff_t)-1); |
a4f5ea64 | 2188 | obj->mm.madv = __I915_MADV_PURGED; |
225067ee | 2189 | } |
e5281ccd | 2190 | |
5537252b | 2191 | /* Try to discard unwanted pages */ |
03ac84f1 | 2192 | void __i915_gem_object_invalidate(struct drm_i915_gem_object *obj) |
225067ee | 2193 | { |
5537252b CW |
2194 | struct address_space *mapping; |
2195 | ||
1233e2db CW |
2196 | lockdep_assert_held(&obj->mm.lock); |
2197 | GEM_BUG_ON(obj->mm.pages); | |
2198 | ||
a4f5ea64 | 2199 | switch (obj->mm.madv) { |
5537252b CW |
2200 | case I915_MADV_DONTNEED: |
2201 | i915_gem_object_truncate(obj); | |
2202 | case __I915_MADV_PURGED: | |
2203 | return; | |
2204 | } | |
2205 | ||
2206 | if (obj->base.filp == NULL) | |
2207 | return; | |
2208 | ||
93c76a3d | 2209 | mapping = obj->base.filp->f_mapping, |
5537252b | 2210 | invalidate_mapping_pages(mapping, 0, (loff_t)-1); |
e5281ccd CW |
2211 | } |
2212 | ||
5cdf5881 | 2213 | static void |
03ac84f1 CW |
2214 | i915_gem_object_put_pages_gtt(struct drm_i915_gem_object *obj, |
2215 | struct sg_table *pages) | |
673a394b | 2216 | { |
85d1225e DG |
2217 | struct sgt_iter sgt_iter; |
2218 | struct page *page; | |
1286ff73 | 2219 | |
2b3c8317 | 2220 | __i915_gem_object_release_shmem(obj, pages); |
673a394b | 2221 | |
03ac84f1 | 2222 | i915_gem_gtt_finish_pages(obj, pages); |
e2273302 | 2223 | |
6dacfd2f | 2224 | if (i915_gem_object_needs_bit17_swizzle(obj)) |
03ac84f1 | 2225 | i915_gem_object_save_bit_17_swizzle(obj, pages); |
280b713b | 2226 | |
03ac84f1 | 2227 | for_each_sgt_page(page, sgt_iter, pages) { |
a4f5ea64 | 2228 | if (obj->mm.dirty) |
9da3da66 | 2229 | set_page_dirty(page); |
3ef94daa | 2230 | |
a4f5ea64 | 2231 | if (obj->mm.madv == I915_MADV_WILLNEED) |
9da3da66 | 2232 | mark_page_accessed(page); |
3ef94daa | 2233 | |
09cbfeaf | 2234 | put_page(page); |
3ef94daa | 2235 | } |
a4f5ea64 | 2236 | obj->mm.dirty = false; |
673a394b | 2237 | |
03ac84f1 CW |
2238 | sg_free_table(pages); |
2239 | kfree(pages); | |
37e680a1 | 2240 | } |
6c085a72 | 2241 | |
96d77634 CW |
2242 | static void __i915_gem_object_reset_page_iter(struct drm_i915_gem_object *obj) |
2243 | { | |
2244 | struct radix_tree_iter iter; | |
2245 | void **slot; | |
2246 | ||
a4f5ea64 CW |
2247 | radix_tree_for_each_slot(slot, &obj->mm.get_page.radix, &iter, 0) |
2248 | radix_tree_delete(&obj->mm.get_page.radix, iter.index); | |
96d77634 CW |
2249 | } |
2250 | ||
548625ee CW |
2251 | void __i915_gem_object_put_pages(struct drm_i915_gem_object *obj, |
2252 | enum i915_mm_subclass subclass) | |
37e680a1 | 2253 | { |
03ac84f1 | 2254 | struct sg_table *pages; |
37e680a1 | 2255 | |
a4f5ea64 | 2256 | if (i915_gem_object_has_pinned_pages(obj)) |
03ac84f1 | 2257 | return; |
a5570178 | 2258 | |
15717de2 | 2259 | GEM_BUG_ON(obj->bind_count); |
1233e2db CW |
2260 | if (!READ_ONCE(obj->mm.pages)) |
2261 | return; | |
2262 | ||
2263 | /* May be called by shrinker from within get_pages() (on another bo) */ | |
548625ee | 2264 | mutex_lock_nested(&obj->mm.lock, subclass); |
1233e2db CW |
2265 | if (unlikely(atomic_read(&obj->mm.pages_pin_count))) |
2266 | goto unlock; | |
3e123027 | 2267 | |
a2165e31 CW |
2268 | /* ->put_pages might need to allocate memory for the bit17 swizzle |
2269 | * array, hence protect them from being reaped by removing them from gtt | |
2270 | * lists early. */ | |
03ac84f1 CW |
2271 | pages = fetch_and_zero(&obj->mm.pages); |
2272 | GEM_BUG_ON(!pages); | |
a2165e31 | 2273 | |
a4f5ea64 | 2274 | if (obj->mm.mapping) { |
4b30cb23 CW |
2275 | void *ptr; |
2276 | ||
a4f5ea64 | 2277 | ptr = ptr_mask_bits(obj->mm.mapping); |
4b30cb23 CW |
2278 | if (is_vmalloc_addr(ptr)) |
2279 | vunmap(ptr); | |
fb8621d3 | 2280 | else |
4b30cb23 CW |
2281 | kunmap(kmap_to_page(ptr)); |
2282 | ||
a4f5ea64 | 2283 | obj->mm.mapping = NULL; |
0a798eb9 CW |
2284 | } |
2285 | ||
96d77634 CW |
2286 | __i915_gem_object_reset_page_iter(obj); |
2287 | ||
03ac84f1 | 2288 | obj->ops->put_pages(obj, pages); |
1233e2db CW |
2289 | unlock: |
2290 | mutex_unlock(&obj->mm.lock); | |
6c085a72 CW |
2291 | } |
2292 | ||
0c40ce13 TU |
2293 | static void i915_sg_trim(struct sg_table *orig_st) |
2294 | { | |
2295 | struct sg_table new_st; | |
2296 | struct scatterlist *sg, *new_sg; | |
2297 | unsigned int i; | |
2298 | ||
2299 | if (orig_st->nents == orig_st->orig_nents) | |
2300 | return; | |
2301 | ||
2302 | if (sg_alloc_table(&new_st, orig_st->nents, GFP_KERNEL)) | |
2303 | return; | |
2304 | ||
2305 | new_sg = new_st.sgl; | |
2306 | for_each_sg(orig_st->sgl, sg, orig_st->nents, i) { | |
2307 | sg_set_page(new_sg, sg_page(sg), sg->length, 0); | |
2308 | /* called before being DMA mapped, no need to copy sg->dma_* */ | |
2309 | new_sg = sg_next(new_sg); | |
2310 | } | |
2311 | ||
2312 | sg_free_table(orig_st); | |
2313 | ||
2314 | *orig_st = new_st; | |
2315 | } | |
2316 | ||
03ac84f1 | 2317 | static struct sg_table * |
6c085a72 | 2318 | i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj) |
e5281ccd | 2319 | { |
fac5e23e | 2320 | struct drm_i915_private *dev_priv = to_i915(obj->base.dev); |
e5281ccd CW |
2321 | int page_count, i; |
2322 | struct address_space *mapping; | |
9da3da66 CW |
2323 | struct sg_table *st; |
2324 | struct scatterlist *sg; | |
85d1225e | 2325 | struct sgt_iter sgt_iter; |
e5281ccd | 2326 | struct page *page; |
90797e6d | 2327 | unsigned long last_pfn = 0; /* suppress gcc warning */ |
4ff340f0 | 2328 | unsigned int max_segment; |
e2273302 | 2329 | int ret; |
6c085a72 | 2330 | gfp_t gfp; |
e5281ccd | 2331 | |
6c085a72 CW |
2332 | /* Assert that the object is not currently in any GPU domain. As it |
2333 | * wasn't in the GTT, there shouldn't be any way it could have been in | |
2334 | * a GPU cache | |
2335 | */ | |
03ac84f1 CW |
2336 | GEM_BUG_ON(obj->base.read_domains & I915_GEM_GPU_DOMAINS); |
2337 | GEM_BUG_ON(obj->base.write_domain & I915_GEM_GPU_DOMAINS); | |
6c085a72 | 2338 | |
7453c549 | 2339 | max_segment = swiotlb_max_segment(); |
871dfbd6 | 2340 | if (!max_segment) |
4ff340f0 | 2341 | max_segment = rounddown(UINT_MAX, PAGE_SIZE); |
871dfbd6 | 2342 | |
9da3da66 CW |
2343 | st = kmalloc(sizeof(*st), GFP_KERNEL); |
2344 | if (st == NULL) | |
03ac84f1 | 2345 | return ERR_PTR(-ENOMEM); |
9da3da66 | 2346 | |
05394f39 | 2347 | page_count = obj->base.size / PAGE_SIZE; |
9da3da66 | 2348 | if (sg_alloc_table(st, page_count, GFP_KERNEL)) { |
9da3da66 | 2349 | kfree(st); |
03ac84f1 | 2350 | return ERR_PTR(-ENOMEM); |
9da3da66 | 2351 | } |
e5281ccd | 2352 | |
9da3da66 CW |
2353 | /* Get the list of pages out of our struct file. They'll be pinned |
2354 | * at this point until we release them. | |
2355 | * | |
2356 | * Fail silently without starting the shrinker | |
2357 | */ | |
93c76a3d | 2358 | mapping = obj->base.filp->f_mapping; |
c62d2555 | 2359 | gfp = mapping_gfp_constraint(mapping, ~(__GFP_IO | __GFP_RECLAIM)); |
d0164adc | 2360 | gfp |= __GFP_NORETRY | __GFP_NOWARN; |
90797e6d ID |
2361 | sg = st->sgl; |
2362 | st->nents = 0; | |
2363 | for (i = 0; i < page_count; i++) { | |
6c085a72 CW |
2364 | page = shmem_read_mapping_page_gfp(mapping, i, gfp); |
2365 | if (IS_ERR(page)) { | |
21ab4e74 CW |
2366 | i915_gem_shrink(dev_priv, |
2367 | page_count, | |
2368 | I915_SHRINK_BOUND | | |
2369 | I915_SHRINK_UNBOUND | | |
2370 | I915_SHRINK_PURGEABLE); | |
6c085a72 CW |
2371 | page = shmem_read_mapping_page_gfp(mapping, i, gfp); |
2372 | } | |
2373 | if (IS_ERR(page)) { | |
2374 | /* We've tried hard to allocate the memory by reaping | |
2375 | * our own buffer, now let the real VM do its job and | |
2376 | * go down in flames if truly OOM. | |
2377 | */ | |
f461d1be | 2378 | page = shmem_read_mapping_page(mapping, i); |
e2273302 ID |
2379 | if (IS_ERR(page)) { |
2380 | ret = PTR_ERR(page); | |
b17993b7 | 2381 | goto err_sg; |
e2273302 | 2382 | } |
6c085a72 | 2383 | } |
871dfbd6 CW |
2384 | if (!i || |
2385 | sg->length >= max_segment || | |
2386 | page_to_pfn(page) != last_pfn + 1) { | |
90797e6d ID |
2387 | if (i) |
2388 | sg = sg_next(sg); | |
2389 | st->nents++; | |
2390 | sg_set_page(sg, page, PAGE_SIZE, 0); | |
2391 | } else { | |
2392 | sg->length += PAGE_SIZE; | |
2393 | } | |
2394 | last_pfn = page_to_pfn(page); | |
3bbbe706 DV |
2395 | |
2396 | /* Check that the i965g/gm workaround works. */ | |
2397 | WARN_ON((gfp & __GFP_DMA32) && (last_pfn >= 0x00100000UL)); | |
e5281ccd | 2398 | } |
871dfbd6 | 2399 | if (sg) /* loop terminated early; short sg table */ |
426729dc | 2400 | sg_mark_end(sg); |
74ce6b6c | 2401 | |
0c40ce13 TU |
2402 | /* Trim unused sg entries to avoid wasting memory. */ |
2403 | i915_sg_trim(st); | |
2404 | ||
03ac84f1 | 2405 | ret = i915_gem_gtt_prepare_pages(obj, st); |
e2273302 ID |
2406 | if (ret) |
2407 | goto err_pages; | |
2408 | ||
6dacfd2f | 2409 | if (i915_gem_object_needs_bit17_swizzle(obj)) |
03ac84f1 | 2410 | i915_gem_object_do_bit_17_swizzle(obj, st); |
e5281ccd | 2411 | |
03ac84f1 | 2412 | return st; |
e5281ccd | 2413 | |
b17993b7 | 2414 | err_sg: |
90797e6d | 2415 | sg_mark_end(sg); |
b17993b7 | 2416 | err_pages: |
85d1225e DG |
2417 | for_each_sgt_page(page, sgt_iter, st) |
2418 | put_page(page); | |
9da3da66 CW |
2419 | sg_free_table(st); |
2420 | kfree(st); | |
0820baf3 CW |
2421 | |
2422 | /* shmemfs first checks if there is enough memory to allocate the page | |
2423 | * and reports ENOSPC should there be insufficient, along with the usual | |
2424 | * ENOMEM for a genuine allocation failure. | |
2425 | * | |
2426 | * We use ENOSPC in our driver to mean that we have run out of aperture | |
2427 | * space and so want to translate the error from shmemfs back to our | |
2428 | * usual understanding of ENOMEM. | |
2429 | */ | |
e2273302 ID |
2430 | if (ret == -ENOSPC) |
2431 | ret = -ENOMEM; | |
2432 | ||
03ac84f1 CW |
2433 | return ERR_PTR(ret); |
2434 | } | |
2435 | ||
2436 | void __i915_gem_object_set_pages(struct drm_i915_gem_object *obj, | |
2437 | struct sg_table *pages) | |
2438 | { | |
1233e2db | 2439 | lockdep_assert_held(&obj->mm.lock); |
03ac84f1 CW |
2440 | |
2441 | obj->mm.get_page.sg_pos = pages->sgl; | |
2442 | obj->mm.get_page.sg_idx = 0; | |
2443 | ||
2444 | obj->mm.pages = pages; | |
2c3a3f44 CW |
2445 | |
2446 | if (i915_gem_object_is_tiled(obj) && | |
2447 | to_i915(obj->base.dev)->quirks & QUIRK_PIN_SWIZZLED_PAGES) { | |
2448 | GEM_BUG_ON(obj->mm.quirked); | |
2449 | __i915_gem_object_pin_pages(obj); | |
2450 | obj->mm.quirked = true; | |
2451 | } | |
03ac84f1 CW |
2452 | } |
2453 | ||
2454 | static int ____i915_gem_object_get_pages(struct drm_i915_gem_object *obj) | |
2455 | { | |
2456 | struct sg_table *pages; | |
2457 | ||
2c3a3f44 CW |
2458 | GEM_BUG_ON(i915_gem_object_has_pinned_pages(obj)); |
2459 | ||
03ac84f1 CW |
2460 | if (unlikely(obj->mm.madv != I915_MADV_WILLNEED)) { |
2461 | DRM_DEBUG("Attempting to obtain a purgeable object\n"); | |
2462 | return -EFAULT; | |
2463 | } | |
2464 | ||
2465 | pages = obj->ops->get_pages(obj); | |
2466 | if (unlikely(IS_ERR(pages))) | |
2467 | return PTR_ERR(pages); | |
2468 | ||
2469 | __i915_gem_object_set_pages(obj, pages); | |
2470 | return 0; | |
673a394b EA |
2471 | } |
2472 | ||
37e680a1 | 2473 | /* Ensure that the associated pages are gathered from the backing storage |
1233e2db | 2474 | * and pinned into our object. i915_gem_object_pin_pages() may be called |
37e680a1 | 2475 | * multiple times before they are released by a single call to |
1233e2db | 2476 | * i915_gem_object_unpin_pages() - once the pages are no longer referenced |
37e680a1 CW |
2477 | * either as a result of memory pressure (reaping pages under the shrinker) |
2478 | * or as the object is itself released. | |
2479 | */ | |
a4f5ea64 | 2480 | int __i915_gem_object_get_pages(struct drm_i915_gem_object *obj) |
37e680a1 | 2481 | { |
03ac84f1 | 2482 | int err; |
37e680a1 | 2483 | |
1233e2db CW |
2484 | err = mutex_lock_interruptible(&obj->mm.lock); |
2485 | if (err) | |
2486 | return err; | |
4c7d62c6 | 2487 | |
2c3a3f44 CW |
2488 | if (unlikely(!obj->mm.pages)) { |
2489 | err = ____i915_gem_object_get_pages(obj); | |
2490 | if (err) | |
2491 | goto unlock; | |
37e680a1 | 2492 | |
2c3a3f44 CW |
2493 | smp_mb__before_atomic(); |
2494 | } | |
2495 | atomic_inc(&obj->mm.pages_pin_count); | |
ee286370 | 2496 | |
1233e2db CW |
2497 | unlock: |
2498 | mutex_unlock(&obj->mm.lock); | |
03ac84f1 | 2499 | return err; |
673a394b EA |
2500 | } |
2501 | ||
dd6034c6 | 2502 | /* The 'mapping' part of i915_gem_object_pin_map() below */ |
d31d7cb1 CW |
2503 | static void *i915_gem_object_map(const struct drm_i915_gem_object *obj, |
2504 | enum i915_map_type type) | |
dd6034c6 DG |
2505 | { |
2506 | unsigned long n_pages = obj->base.size >> PAGE_SHIFT; | |
a4f5ea64 | 2507 | struct sg_table *sgt = obj->mm.pages; |
85d1225e DG |
2508 | struct sgt_iter sgt_iter; |
2509 | struct page *page; | |
b338fa47 DG |
2510 | struct page *stack_pages[32]; |
2511 | struct page **pages = stack_pages; | |
dd6034c6 | 2512 | unsigned long i = 0; |
d31d7cb1 | 2513 | pgprot_t pgprot; |
dd6034c6 DG |
2514 | void *addr; |
2515 | ||
2516 | /* A single page can always be kmapped */ | |
d31d7cb1 | 2517 | if (n_pages == 1 && type == I915_MAP_WB) |
dd6034c6 DG |
2518 | return kmap(sg_page(sgt->sgl)); |
2519 | ||
b338fa47 DG |
2520 | if (n_pages > ARRAY_SIZE(stack_pages)) { |
2521 | /* Too big for stack -- allocate temporary array instead */ | |
2522 | pages = drm_malloc_gfp(n_pages, sizeof(*pages), GFP_TEMPORARY); | |
2523 | if (!pages) | |
2524 | return NULL; | |
2525 | } | |
dd6034c6 | 2526 | |
85d1225e DG |
2527 | for_each_sgt_page(page, sgt_iter, sgt) |
2528 | pages[i++] = page; | |
dd6034c6 DG |
2529 | |
2530 | /* Check that we have the expected number of pages */ | |
2531 | GEM_BUG_ON(i != n_pages); | |
2532 | ||
d31d7cb1 CW |
2533 | switch (type) { |
2534 | case I915_MAP_WB: | |
2535 | pgprot = PAGE_KERNEL; | |
2536 | break; | |
2537 | case I915_MAP_WC: | |
2538 | pgprot = pgprot_writecombine(PAGE_KERNEL_IO); | |
2539 | break; | |
2540 | } | |
2541 | addr = vmap(pages, n_pages, 0, pgprot); | |
dd6034c6 | 2542 | |
b338fa47 DG |
2543 | if (pages != stack_pages) |
2544 | drm_free_large(pages); | |
dd6034c6 DG |
2545 | |
2546 | return addr; | |
2547 | } | |
2548 | ||
2549 | /* get, pin, and map the pages of the object into kernel space */ | |
d31d7cb1 CW |
2550 | void *i915_gem_object_pin_map(struct drm_i915_gem_object *obj, |
2551 | enum i915_map_type type) | |
0a798eb9 | 2552 | { |
d31d7cb1 CW |
2553 | enum i915_map_type has_type; |
2554 | bool pinned; | |
2555 | void *ptr; | |
0a798eb9 CW |
2556 | int ret; |
2557 | ||
d31d7cb1 | 2558 | GEM_BUG_ON(!i915_gem_object_has_struct_page(obj)); |
0a798eb9 | 2559 | |
1233e2db | 2560 | ret = mutex_lock_interruptible(&obj->mm.lock); |
0a798eb9 CW |
2561 | if (ret) |
2562 | return ERR_PTR(ret); | |
2563 | ||
1233e2db CW |
2564 | pinned = true; |
2565 | if (!atomic_inc_not_zero(&obj->mm.pages_pin_count)) { | |
2c3a3f44 CW |
2566 | if (unlikely(!obj->mm.pages)) { |
2567 | ret = ____i915_gem_object_get_pages(obj); | |
2568 | if (ret) | |
2569 | goto err_unlock; | |
1233e2db | 2570 | |
2c3a3f44 CW |
2571 | smp_mb__before_atomic(); |
2572 | } | |
2573 | atomic_inc(&obj->mm.pages_pin_count); | |
1233e2db CW |
2574 | pinned = false; |
2575 | } | |
2576 | GEM_BUG_ON(!obj->mm.pages); | |
0a798eb9 | 2577 | |
a4f5ea64 | 2578 | ptr = ptr_unpack_bits(obj->mm.mapping, has_type); |
d31d7cb1 CW |
2579 | if (ptr && has_type != type) { |
2580 | if (pinned) { | |
2581 | ret = -EBUSY; | |
1233e2db | 2582 | goto err_unpin; |
0a798eb9 | 2583 | } |
d31d7cb1 CW |
2584 | |
2585 | if (is_vmalloc_addr(ptr)) | |
2586 | vunmap(ptr); | |
2587 | else | |
2588 | kunmap(kmap_to_page(ptr)); | |
2589 | ||
a4f5ea64 | 2590 | ptr = obj->mm.mapping = NULL; |
0a798eb9 CW |
2591 | } |
2592 | ||
d31d7cb1 CW |
2593 | if (!ptr) { |
2594 | ptr = i915_gem_object_map(obj, type); | |
2595 | if (!ptr) { | |
2596 | ret = -ENOMEM; | |
1233e2db | 2597 | goto err_unpin; |
d31d7cb1 CW |
2598 | } |
2599 | ||
a4f5ea64 | 2600 | obj->mm.mapping = ptr_pack_bits(ptr, type); |
d31d7cb1 CW |
2601 | } |
2602 | ||
1233e2db CW |
2603 | out_unlock: |
2604 | mutex_unlock(&obj->mm.lock); | |
d31d7cb1 CW |
2605 | return ptr; |
2606 | ||
1233e2db CW |
2607 | err_unpin: |
2608 | atomic_dec(&obj->mm.pages_pin_count); | |
2609 | err_unlock: | |
2610 | ptr = ERR_PTR(ret); | |
2611 | goto out_unlock; | |
0a798eb9 CW |
2612 | } |
2613 | ||
7b4d3a16 | 2614 | static bool i915_context_is_banned(const struct i915_gem_context *ctx) |
be62acb4 | 2615 | { |
44e2c070 | 2616 | unsigned long elapsed; |
be62acb4 | 2617 | |
44e2c070 | 2618 | if (ctx->hang_stats.banned) |
be62acb4 MK |
2619 | return true; |
2620 | ||
7b4d3a16 | 2621 | elapsed = get_seconds() - ctx->hang_stats.guilty_ts; |
676fa572 CW |
2622 | if (ctx->hang_stats.ban_period_seconds && |
2623 | elapsed <= ctx->hang_stats.ban_period_seconds) { | |
7b4d3a16 CW |
2624 | DRM_DEBUG("context hanging too fast, banning!\n"); |
2625 | return true; | |
be62acb4 MK |
2626 | } |
2627 | ||
2628 | return false; | |
2629 | } | |
2630 | ||
7b4d3a16 | 2631 | static void i915_set_reset_status(struct i915_gem_context *ctx, |
b6b0fac0 | 2632 | const bool guilty) |
aa60c664 | 2633 | { |
7b4d3a16 | 2634 | struct i915_ctx_hang_stats *hs = &ctx->hang_stats; |
44e2c070 MK |
2635 | |
2636 | if (guilty) { | |
7b4d3a16 | 2637 | hs->banned = i915_context_is_banned(ctx); |
44e2c070 MK |
2638 | hs->batch_active++; |
2639 | hs->guilty_ts = get_seconds(); | |
2640 | } else { | |
2641 | hs->batch_pending++; | |
aa60c664 MK |
2642 | } |
2643 | } | |
2644 | ||
8d9fc7fd | 2645 | struct drm_i915_gem_request * |
0bc40be8 | 2646 | i915_gem_find_active_request(struct intel_engine_cs *engine) |
9375e446 | 2647 | { |
4db080f9 CW |
2648 | struct drm_i915_gem_request *request; |
2649 | ||
f69a02c9 CW |
2650 | /* We are called by the error capture and reset at a random |
2651 | * point in time. In particular, note that neither is crucially | |
2652 | * ordered with an interrupt. After a hang, the GPU is dead and we | |
2653 | * assume that no more writes can happen (we waited long enough for | |
2654 | * all writes that were in transaction to be flushed) - adding an | |
2655 | * extra delay for a recent interrupt is pointless. Hence, we do | |
2656 | * not need an engine->irq_seqno_barrier() before the seqno reads. | |
2657 | */ | |
73cb9701 | 2658 | list_for_each_entry(request, &engine->timeline->requests, link) { |
80b204bc | 2659 | if (__i915_gem_request_completed(request)) |
4db080f9 | 2660 | continue; |
aa60c664 | 2661 | |
b6b0fac0 | 2662 | return request; |
4db080f9 | 2663 | } |
b6b0fac0 MK |
2664 | |
2665 | return NULL; | |
2666 | } | |
2667 | ||
821ed7df CW |
2668 | static void reset_request(struct drm_i915_gem_request *request) |
2669 | { | |
2670 | void *vaddr = request->ring->vaddr; | |
2671 | u32 head; | |
2672 | ||
2673 | /* As this request likely depends on state from the lost | |
2674 | * context, clear out all the user operations leaving the | |
2675 | * breadcrumb at the end (so we get the fence notifications). | |
2676 | */ | |
2677 | head = request->head; | |
2678 | if (request->postfix < head) { | |
2679 | memset(vaddr + head, 0, request->ring->size - head); | |
2680 | head = 0; | |
2681 | } | |
2682 | memset(vaddr + head, 0, request->postfix - head); | |
2683 | } | |
2684 | ||
2685 | static void i915_gem_reset_engine(struct intel_engine_cs *engine) | |
b6b0fac0 MK |
2686 | { |
2687 | struct drm_i915_gem_request *request; | |
821ed7df | 2688 | struct i915_gem_context *incomplete_ctx; |
80b204bc | 2689 | struct intel_timeline *timeline; |
b6b0fac0 MK |
2690 | bool ring_hung; |
2691 | ||
821ed7df CW |
2692 | if (engine->irq_seqno_barrier) |
2693 | engine->irq_seqno_barrier(engine); | |
2694 | ||
0bc40be8 | 2695 | request = i915_gem_find_active_request(engine); |
821ed7df | 2696 | if (!request) |
b6b0fac0 MK |
2697 | return; |
2698 | ||
0bc40be8 | 2699 | ring_hung = engine->hangcheck.score >= HANGCHECK_SCORE_RING_HUNG; |
77c60701 CW |
2700 | if (engine->hangcheck.seqno != intel_engine_get_seqno(engine)) |
2701 | ring_hung = false; | |
2702 | ||
7b4d3a16 | 2703 | i915_set_reset_status(request->ctx, ring_hung); |
821ed7df CW |
2704 | if (!ring_hung) |
2705 | return; | |
2706 | ||
2707 | DRM_DEBUG_DRIVER("resetting %s to restart from tail of request 0x%x\n", | |
65e4760e | 2708 | engine->name, request->global_seqno); |
821ed7df CW |
2709 | |
2710 | /* Setup the CS to resume from the breadcrumb of the hung request */ | |
2711 | engine->reset_hw(engine, request); | |
2712 | ||
2713 | /* Users of the default context do not rely on logical state | |
2714 | * preserved between batches. They have to emit full state on | |
2715 | * every batch and so it is safe to execute queued requests following | |
2716 | * the hang. | |
2717 | * | |
2718 | * Other contexts preserve state, now corrupt. We want to skip all | |
2719 | * queued requests that reference the corrupt context. | |
2720 | */ | |
2721 | incomplete_ctx = request->ctx; | |
2722 | if (i915_gem_context_is_default(incomplete_ctx)) | |
2723 | return; | |
2724 | ||
73cb9701 | 2725 | list_for_each_entry_continue(request, &engine->timeline->requests, link) |
821ed7df CW |
2726 | if (request->ctx == incomplete_ctx) |
2727 | reset_request(request); | |
80b204bc CW |
2728 | |
2729 | timeline = i915_gem_context_lookup_timeline(incomplete_ctx, engine); | |
2730 | list_for_each_entry(request, &timeline->requests, link) | |
2731 | reset_request(request); | |
4db080f9 | 2732 | } |
aa60c664 | 2733 | |
821ed7df | 2734 | void i915_gem_reset(struct drm_i915_private *dev_priv) |
4db080f9 | 2735 | { |
821ed7df | 2736 | struct intel_engine_cs *engine; |
3b3f1650 | 2737 | enum intel_engine_id id; |
608c1a52 | 2738 | |
4c7d62c6 CW |
2739 | lockdep_assert_held(&dev_priv->drm.struct_mutex); |
2740 | ||
821ed7df CW |
2741 | i915_gem_retire_requests(dev_priv); |
2742 | ||
3b3f1650 | 2743 | for_each_engine(engine, dev_priv, id) |
821ed7df CW |
2744 | i915_gem_reset_engine(engine); |
2745 | ||
4362f4f6 | 2746 | i915_gem_restore_fences(dev_priv); |
f2a91d1a CW |
2747 | |
2748 | if (dev_priv->gt.awake) { | |
2749 | intel_sanitize_gt_powersave(dev_priv); | |
2750 | intel_enable_gt_powersave(dev_priv); | |
2751 | if (INTEL_GEN(dev_priv) >= 6) | |
2752 | gen6_rps_busy(dev_priv); | |
2753 | } | |
821ed7df CW |
2754 | } |
2755 | ||
2756 | static void nop_submit_request(struct drm_i915_gem_request *request) | |
2757 | { | |
ce1135c7 CW |
2758 | i915_gem_request_submit(request); |
2759 | intel_engine_init_global_seqno(request->engine, request->global_seqno); | |
821ed7df CW |
2760 | } |
2761 | ||
2762 | static void i915_gem_cleanup_engine(struct intel_engine_cs *engine) | |
2763 | { | |
2764 | engine->submit_request = nop_submit_request; | |
70c2a24d | 2765 | |
c4b0930b CW |
2766 | /* Mark all pending requests as complete so that any concurrent |
2767 | * (lockless) lookup doesn't try and wait upon the request as we | |
2768 | * reset it. | |
2769 | */ | |
73cb9701 | 2770 | intel_engine_init_global_seqno(engine, |
cb399eab | 2771 | intel_engine_last_submit(engine)); |
c4b0930b | 2772 | |
dcb4c12a OM |
2773 | /* |
2774 | * Clear the execlists queue up before freeing the requests, as those | |
2775 | * are the ones that keep the context and ringbuffer backing objects | |
2776 | * pinned in place. | |
2777 | */ | |
dcb4c12a | 2778 | |
7de1691a | 2779 | if (i915.enable_execlists) { |
663f71e7 CW |
2780 | unsigned long flags; |
2781 | ||
2782 | spin_lock_irqsave(&engine->timeline->lock, flags); | |
2783 | ||
70c2a24d CW |
2784 | i915_gem_request_put(engine->execlist_port[0].request); |
2785 | i915_gem_request_put(engine->execlist_port[1].request); | |
2786 | memset(engine->execlist_port, 0, sizeof(engine->execlist_port)); | |
20311bd3 CW |
2787 | engine->execlist_queue = RB_ROOT; |
2788 | engine->execlist_first = NULL; | |
663f71e7 CW |
2789 | |
2790 | spin_unlock_irqrestore(&engine->timeline->lock, flags); | |
dcb4c12a | 2791 | } |
673a394b EA |
2792 | } |
2793 | ||
821ed7df | 2794 | void i915_gem_set_wedged(struct drm_i915_private *dev_priv) |
673a394b | 2795 | { |
e2f80391 | 2796 | struct intel_engine_cs *engine; |
3b3f1650 | 2797 | enum intel_engine_id id; |
673a394b | 2798 | |
821ed7df CW |
2799 | lockdep_assert_held(&dev_priv->drm.struct_mutex); |
2800 | set_bit(I915_WEDGED, &dev_priv->gpu_error.flags); | |
4db080f9 | 2801 | |
821ed7df | 2802 | i915_gem_context_lost(dev_priv); |
3b3f1650 | 2803 | for_each_engine(engine, dev_priv, id) |
821ed7df | 2804 | i915_gem_cleanup_engine(engine); |
b913b33c | 2805 | mod_delayed_work(dev_priv->wq, &dev_priv->gt.idle_work, 0); |
dfaae392 | 2806 | |
821ed7df | 2807 | i915_gem_retire_requests(dev_priv); |
673a394b EA |
2808 | } |
2809 | ||
75ef9da2 | 2810 | static void |
673a394b EA |
2811 | i915_gem_retire_work_handler(struct work_struct *work) |
2812 | { | |
b29c19b6 | 2813 | struct drm_i915_private *dev_priv = |
67d97da3 | 2814 | container_of(work, typeof(*dev_priv), gt.retire_work.work); |
91c8a326 | 2815 | struct drm_device *dev = &dev_priv->drm; |
673a394b | 2816 | |
891b48cf | 2817 | /* Come back later if the device is busy... */ |
b29c19b6 | 2818 | if (mutex_trylock(&dev->struct_mutex)) { |
67d97da3 | 2819 | i915_gem_retire_requests(dev_priv); |
b29c19b6 | 2820 | mutex_unlock(&dev->struct_mutex); |
673a394b | 2821 | } |
67d97da3 CW |
2822 | |
2823 | /* Keep the retire handler running until we are finally idle. | |
2824 | * We do not need to do this test under locking as in the worst-case | |
2825 | * we queue the retire worker once too often. | |
2826 | */ | |
c9615613 CW |
2827 | if (READ_ONCE(dev_priv->gt.awake)) { |
2828 | i915_queue_hangcheck(dev_priv); | |
67d97da3 CW |
2829 | queue_delayed_work(dev_priv->wq, |
2830 | &dev_priv->gt.retire_work, | |
bcb45086 | 2831 | round_jiffies_up_relative(HZ)); |
c9615613 | 2832 | } |
b29c19b6 | 2833 | } |
0a58705b | 2834 | |
b29c19b6 CW |
2835 | static void |
2836 | i915_gem_idle_work_handler(struct work_struct *work) | |
2837 | { | |
2838 | struct drm_i915_private *dev_priv = | |
67d97da3 | 2839 | container_of(work, typeof(*dev_priv), gt.idle_work.work); |
91c8a326 | 2840 | struct drm_device *dev = &dev_priv->drm; |
b4ac5afc | 2841 | struct intel_engine_cs *engine; |
3b3f1650 | 2842 | enum intel_engine_id id; |
67d97da3 CW |
2843 | bool rearm_hangcheck; |
2844 | ||
2845 | if (!READ_ONCE(dev_priv->gt.awake)) | |
2846 | return; | |
2847 | ||
0cb5670b ID |
2848 | /* |
2849 | * Wait for last execlists context complete, but bail out in case a | |
2850 | * new request is submitted. | |
2851 | */ | |
2852 | wait_for(READ_ONCE(dev_priv->gt.active_requests) || | |
2853 | intel_execlists_idle(dev_priv), 10); | |
2854 | ||
28176ef4 | 2855 | if (READ_ONCE(dev_priv->gt.active_requests)) |
67d97da3 CW |
2856 | return; |
2857 | ||
2858 | rearm_hangcheck = | |
2859 | cancel_delayed_work_sync(&dev_priv->gpu_error.hangcheck_work); | |
2860 | ||
2861 | if (!mutex_trylock(&dev->struct_mutex)) { | |
2862 | /* Currently busy, come back later */ | |
2863 | mod_delayed_work(dev_priv->wq, | |
2864 | &dev_priv->gt.idle_work, | |
2865 | msecs_to_jiffies(50)); | |
2866 | goto out_rearm; | |
2867 | } | |
2868 | ||
93c97dc1 ID |
2869 | /* |
2870 | * New request retired after this work handler started, extend active | |
2871 | * period until next instance of the work. | |
2872 | */ | |
2873 | if (work_pending(work)) | |
2874 | goto out_unlock; | |
2875 | ||
28176ef4 | 2876 | if (dev_priv->gt.active_requests) |
67d97da3 | 2877 | goto out_unlock; |
b29c19b6 | 2878 | |
0cb5670b ID |
2879 | if (wait_for(intel_execlists_idle(dev_priv), 10)) |
2880 | DRM_ERROR("Timeout waiting for engines to idle\n"); | |
2881 | ||
3b3f1650 | 2882 | for_each_engine(engine, dev_priv, id) |
67d97da3 | 2883 | i915_gem_batch_pool_fini(&engine->batch_pool); |
35c94185 | 2884 | |
67d97da3 CW |
2885 | GEM_BUG_ON(!dev_priv->gt.awake); |
2886 | dev_priv->gt.awake = false; | |
2887 | rearm_hangcheck = false; | |
30ecad77 | 2888 | |
67d97da3 CW |
2889 | if (INTEL_GEN(dev_priv) >= 6) |
2890 | gen6_rps_idle(dev_priv); | |
2891 | intel_runtime_pm_put(dev_priv); | |
2892 | out_unlock: | |
2893 | mutex_unlock(&dev->struct_mutex); | |
b29c19b6 | 2894 | |
67d97da3 CW |
2895 | out_rearm: |
2896 | if (rearm_hangcheck) { | |
2897 | GEM_BUG_ON(!dev_priv->gt.awake); | |
2898 | i915_queue_hangcheck(dev_priv); | |
35c94185 | 2899 | } |
673a394b EA |
2900 | } |
2901 | ||
b1f788c6 CW |
2902 | void i915_gem_close_object(struct drm_gem_object *gem, struct drm_file *file) |
2903 | { | |
2904 | struct drm_i915_gem_object *obj = to_intel_bo(gem); | |
2905 | struct drm_i915_file_private *fpriv = file->driver_priv; | |
2906 | struct i915_vma *vma, *vn; | |
2907 | ||
2908 | mutex_lock(&obj->base.dev->struct_mutex); | |
2909 | list_for_each_entry_safe(vma, vn, &obj->vma_list, obj_link) | |
2910 | if (vma->vm->file == fpriv) | |
2911 | i915_vma_close(vma); | |
f8a7fde4 CW |
2912 | |
2913 | if (i915_gem_object_is_active(obj) && | |
2914 | !i915_gem_object_has_active_reference(obj)) { | |
2915 | i915_gem_object_set_active_reference(obj); | |
2916 | i915_gem_object_get(obj); | |
2917 | } | |
b1f788c6 CW |
2918 | mutex_unlock(&obj->base.dev->struct_mutex); |
2919 | } | |
2920 | ||
e95433c7 CW |
2921 | static unsigned long to_wait_timeout(s64 timeout_ns) |
2922 | { | |
2923 | if (timeout_ns < 0) | |
2924 | return MAX_SCHEDULE_TIMEOUT; | |
2925 | ||
2926 | if (timeout_ns == 0) | |
2927 | return 0; | |
2928 | ||
2929 | return nsecs_to_jiffies_timeout(timeout_ns); | |
2930 | } | |
2931 | ||
23ba4fd0 BW |
2932 | /** |
2933 | * i915_gem_wait_ioctl - implements DRM_IOCTL_I915_GEM_WAIT | |
14bb2c11 TU |
2934 | * @dev: drm device pointer |
2935 | * @data: ioctl data blob | |
2936 | * @file: drm file pointer | |
23ba4fd0 BW |
2937 | * |
2938 | * Returns 0 if successful, else an error is returned with the remaining time in | |
2939 | * the timeout parameter. | |
2940 | * -ETIME: object is still busy after timeout | |
2941 | * -ERESTARTSYS: signal interrupted the wait | |
2942 | * -ENONENT: object doesn't exist | |
2943 | * Also possible, but rare: | |
2944 | * -EAGAIN: GPU wedged | |
2945 | * -ENOMEM: damn | |
2946 | * -ENODEV: Internal IRQ fail | |
2947 | * -E?: The add request failed | |
2948 | * | |
2949 | * The wait ioctl with a timeout of 0 reimplements the busy ioctl. With any | |
2950 | * non-zero timeout parameter the wait ioctl will wait for the given number of | |
2951 | * nanoseconds on an object becoming unbusy. Since the wait itself does so | |
2952 | * without holding struct_mutex the object may become re-busied before this | |
2953 | * function completes. A similar but shorter * race condition exists in the busy | |
2954 | * ioctl | |
2955 | */ | |
2956 | int | |
2957 | i915_gem_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *file) | |
2958 | { | |
2959 | struct drm_i915_gem_wait *args = data; | |
2960 | struct drm_i915_gem_object *obj; | |
e95433c7 CW |
2961 | ktime_t start; |
2962 | long ret; | |
23ba4fd0 | 2963 | |
11b5d511 DV |
2964 | if (args->flags != 0) |
2965 | return -EINVAL; | |
2966 | ||
03ac0642 | 2967 | obj = i915_gem_object_lookup(file, args->bo_handle); |
033d549b | 2968 | if (!obj) |
23ba4fd0 | 2969 | return -ENOENT; |
23ba4fd0 | 2970 | |
e95433c7 CW |
2971 | start = ktime_get(); |
2972 | ||
2973 | ret = i915_gem_object_wait(obj, | |
2974 | I915_WAIT_INTERRUPTIBLE | I915_WAIT_ALL, | |
2975 | to_wait_timeout(args->timeout_ns), | |
2976 | to_rps_client(file)); | |
2977 | ||
2978 | if (args->timeout_ns > 0) { | |
2979 | args->timeout_ns -= ktime_to_ns(ktime_sub(ktime_get(), start)); | |
2980 | if (args->timeout_ns < 0) | |
2981 | args->timeout_ns = 0; | |
b4716185 CW |
2982 | } |
2983 | ||
f0cd5182 | 2984 | i915_gem_object_put(obj); |
ff865885 | 2985 | return ret; |
23ba4fd0 BW |
2986 | } |
2987 | ||
73cb9701 | 2988 | static int wait_for_timeline(struct i915_gem_timeline *tl, unsigned int flags) |
4df2faf4 | 2989 | { |
73cb9701 | 2990 | int ret, i; |
4df2faf4 | 2991 | |
73cb9701 CW |
2992 | for (i = 0; i < ARRAY_SIZE(tl->engine); i++) { |
2993 | ret = i915_gem_active_wait(&tl->engine[i].last_request, flags); | |
2994 | if (ret) | |
2995 | return ret; | |
2996 | } | |
62e63007 | 2997 | |
73cb9701 CW |
2998 | return 0; |
2999 | } | |
3000 | ||
3001 | int i915_gem_wait_for_idle(struct drm_i915_private *i915, unsigned int flags) | |
3002 | { | |
73cb9701 CW |
3003 | int ret; |
3004 | ||
9caa34aa CW |
3005 | if (flags & I915_WAIT_LOCKED) { |
3006 | struct i915_gem_timeline *tl; | |
3007 | ||
3008 | lockdep_assert_held(&i915->drm.struct_mutex); | |
3009 | ||
3010 | list_for_each_entry(tl, &i915->gt.timelines, link) { | |
3011 | ret = wait_for_timeline(tl, flags); | |
3012 | if (ret) | |
3013 | return ret; | |
3014 | } | |
3015 | } else { | |
3016 | ret = wait_for_timeline(&i915->gt.global_timeline, flags); | |
1ec14ad3 CW |
3017 | if (ret) |
3018 | return ret; | |
3019 | } | |
4df2faf4 | 3020 | |
8a1a49f9 | 3021 | return 0; |
4df2faf4 DV |
3022 | } |
3023 | ||
d0da48cf CW |
3024 | void i915_gem_clflush_object(struct drm_i915_gem_object *obj, |
3025 | bool force) | |
673a394b | 3026 | { |
673a394b EA |
3027 | /* If we don't have a page list set up, then we're not pinned |
3028 | * to GPU, and we can ignore the cache flush because it'll happen | |
3029 | * again at bind time. | |
3030 | */ | |
a4f5ea64 | 3031 | if (!obj->mm.pages) |
d0da48cf | 3032 | return; |
673a394b | 3033 | |
769ce464 ID |
3034 | /* |
3035 | * Stolen memory is always coherent with the GPU as it is explicitly | |
3036 | * marked as wc by the system, or the system is cache-coherent. | |
3037 | */ | |
6a2c4232 | 3038 | if (obj->stolen || obj->phys_handle) |
d0da48cf | 3039 | return; |
769ce464 | 3040 | |
9c23f7fc CW |
3041 | /* If the GPU is snooping the contents of the CPU cache, |
3042 | * we do not need to manually clear the CPU cache lines. However, | |
3043 | * the caches are only snooped when the render cache is | |
3044 | * flushed/invalidated. As we always have to emit invalidations | |
3045 | * and flushes when moving into and out of the RENDER domain, correct | |
3046 | * snooping behaviour occurs naturally as the result of our domain | |
3047 | * tracking. | |
3048 | */ | |
0f71979a CW |
3049 | if (!force && cpu_cache_is_coherent(obj->base.dev, obj->cache_level)) { |
3050 | obj->cache_dirty = true; | |
d0da48cf | 3051 | return; |
0f71979a | 3052 | } |
9c23f7fc | 3053 | |
1c5d22f7 | 3054 | trace_i915_gem_object_clflush(obj); |
a4f5ea64 | 3055 | drm_clflush_sg(obj->mm.pages); |
0f71979a | 3056 | obj->cache_dirty = false; |
e47c68e9 EA |
3057 | } |
3058 | ||
3059 | /** Flushes the GTT write domain for the object if it's dirty. */ | |
3060 | static void | |
05394f39 | 3061 | i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj) |
e47c68e9 | 3062 | { |
3b5724d7 | 3063 | struct drm_i915_private *dev_priv = to_i915(obj->base.dev); |
1c5d22f7 | 3064 | |
05394f39 | 3065 | if (obj->base.write_domain != I915_GEM_DOMAIN_GTT) |
e47c68e9 EA |
3066 | return; |
3067 | ||
63256ec5 | 3068 | /* No actual flushing is required for the GTT write domain. Writes |
3b5724d7 | 3069 | * to it "immediately" go to main memory as far as we know, so there's |
e47c68e9 | 3070 | * no chipset flush. It also doesn't land in render cache. |
63256ec5 CW |
3071 | * |
3072 | * However, we do have to enforce the order so that all writes through | |
3073 | * the GTT land before any writes to the device, such as updates to | |
3074 | * the GATT itself. | |
3b5724d7 CW |
3075 | * |
3076 | * We also have to wait a bit for the writes to land from the GTT. | |
3077 | * An uncached read (i.e. mmio) seems to be ideal for the round-trip | |
3078 | * timing. This issue has only been observed when switching quickly | |
3079 | * between GTT writes and CPU reads from inside the kernel on recent hw, | |
3080 | * and it appears to only affect discrete GTT blocks (i.e. on LLC | |
3081 | * system agents we cannot reproduce this behaviour). | |
e47c68e9 | 3082 | */ |
63256ec5 | 3083 | wmb(); |
3b5724d7 | 3084 | if (INTEL_GEN(dev_priv) >= 6 && !HAS_LLC(dev_priv)) |
3b3f1650 | 3085 | POSTING_READ(RING_ACTHD(dev_priv->engine[RCS]->mmio_base)); |
63256ec5 | 3086 | |
d243ad82 | 3087 | intel_fb_obj_flush(obj, false, write_origin(obj, I915_GEM_DOMAIN_GTT)); |
f99d7069 | 3088 | |
b0dc465f | 3089 | obj->base.write_domain = 0; |
1c5d22f7 | 3090 | trace_i915_gem_object_change_domain(obj, |
05394f39 | 3091 | obj->base.read_domains, |
b0dc465f | 3092 | I915_GEM_DOMAIN_GTT); |
e47c68e9 EA |
3093 | } |
3094 | ||
3095 | /** Flushes the CPU write domain for the object if it's dirty. */ | |
3096 | static void | |
e62b59e4 | 3097 | i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj) |
e47c68e9 | 3098 | { |
05394f39 | 3099 | if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) |
e47c68e9 EA |
3100 | return; |
3101 | ||
d0da48cf | 3102 | i915_gem_clflush_object(obj, obj->pin_display); |
de152b62 | 3103 | intel_fb_obj_flush(obj, false, ORIGIN_CPU); |
f99d7069 | 3104 | |
b0dc465f | 3105 | obj->base.write_domain = 0; |
1c5d22f7 | 3106 | trace_i915_gem_object_change_domain(obj, |
05394f39 | 3107 | obj->base.read_domains, |
b0dc465f | 3108 | I915_GEM_DOMAIN_CPU); |
e47c68e9 EA |
3109 | } |
3110 | ||
2ef7eeaa EA |
3111 | /** |
3112 | * Moves a single object to the GTT read, and possibly write domain. | |
14bb2c11 TU |
3113 | * @obj: object to act on |
3114 | * @write: ask for write access or read only | |
2ef7eeaa EA |
3115 | * |
3116 | * This function returns when the move is complete, including waiting on | |
3117 | * flushes to occur. | |
3118 | */ | |
79e53945 | 3119 | int |
2021746e | 3120 | i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write) |
2ef7eeaa | 3121 | { |
1c5d22f7 | 3122 | uint32_t old_write_domain, old_read_domains; |
e47c68e9 | 3123 | int ret; |
2ef7eeaa | 3124 | |
e95433c7 | 3125 | lockdep_assert_held(&obj->base.dev->struct_mutex); |
4c7d62c6 | 3126 | |
e95433c7 CW |
3127 | ret = i915_gem_object_wait(obj, |
3128 | I915_WAIT_INTERRUPTIBLE | | |
3129 | I915_WAIT_LOCKED | | |
3130 | (write ? I915_WAIT_ALL : 0), | |
3131 | MAX_SCHEDULE_TIMEOUT, | |
3132 | NULL); | |
88241785 CW |
3133 | if (ret) |
3134 | return ret; | |
3135 | ||
c13d87ea CW |
3136 | if (obj->base.write_domain == I915_GEM_DOMAIN_GTT) |
3137 | return 0; | |
3138 | ||
43566ded CW |
3139 | /* Flush and acquire obj->pages so that we are coherent through |
3140 | * direct access in memory with previous cached writes through | |
3141 | * shmemfs and that our cache domain tracking remains valid. | |
3142 | * For example, if the obj->filp was moved to swap without us | |
3143 | * being notified and releasing the pages, we would mistakenly | |
3144 | * continue to assume that the obj remained out of the CPU cached | |
3145 | * domain. | |
3146 | */ | |
a4f5ea64 | 3147 | ret = i915_gem_object_pin_pages(obj); |
43566ded CW |
3148 | if (ret) |
3149 | return ret; | |
3150 | ||
e62b59e4 | 3151 | i915_gem_object_flush_cpu_write_domain(obj); |
1c5d22f7 | 3152 | |
d0a57789 CW |
3153 | /* Serialise direct access to this object with the barriers for |
3154 | * coherent writes from the GPU, by effectively invalidating the | |
3155 | * GTT domain upon first access. | |
3156 | */ | |
3157 | if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0) | |
3158 | mb(); | |
3159 | ||
05394f39 CW |
3160 | old_write_domain = obj->base.write_domain; |
3161 | old_read_domains = obj->base.read_domains; | |
1c5d22f7 | 3162 | |
e47c68e9 EA |
3163 | /* It should now be out of any other write domains, and we can update |
3164 | * the domain values for our changes. | |
3165 | */ | |
40e62d5d | 3166 | GEM_BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) != 0); |
05394f39 | 3167 | obj->base.read_domains |= I915_GEM_DOMAIN_GTT; |
e47c68e9 | 3168 | if (write) { |
05394f39 CW |
3169 | obj->base.read_domains = I915_GEM_DOMAIN_GTT; |
3170 | obj->base.write_domain = I915_GEM_DOMAIN_GTT; | |
a4f5ea64 | 3171 | obj->mm.dirty = true; |
2ef7eeaa EA |
3172 | } |
3173 | ||
1c5d22f7 CW |
3174 | trace_i915_gem_object_change_domain(obj, |
3175 | old_read_domains, | |
3176 | old_write_domain); | |
3177 | ||
a4f5ea64 | 3178 | i915_gem_object_unpin_pages(obj); |
e47c68e9 EA |
3179 | return 0; |
3180 | } | |
3181 | ||
ef55f92a CW |
3182 | /** |
3183 | * Changes the cache-level of an object across all VMA. | |
14bb2c11 TU |
3184 | * @obj: object to act on |
3185 | * @cache_level: new cache level to set for the object | |
ef55f92a CW |
3186 | * |
3187 | * After this function returns, the object will be in the new cache-level | |
3188 | * across all GTT and the contents of the backing storage will be coherent, | |
3189 | * with respect to the new cache-level. In order to keep the backing storage | |
3190 | * coherent for all users, we only allow a single cache level to be set | |
3191 | * globally on the object and prevent it from being changed whilst the | |
3192 | * hardware is reading from the object. That is if the object is currently | |
3193 | * on the scanout it will be set to uncached (or equivalent display | |
3194 | * cache coherency) and all non-MOCS GPU access will also be uncached so | |
3195 | * that all direct access to the scanout remains coherent. | |
3196 | */ | |
e4ffd173 CW |
3197 | int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj, |
3198 | enum i915_cache_level cache_level) | |
3199 | { | |
aa653a68 | 3200 | struct i915_vma *vma; |
a6a7cc4b | 3201 | int ret; |
e4ffd173 | 3202 | |
4c7d62c6 CW |
3203 | lockdep_assert_held(&obj->base.dev->struct_mutex); |
3204 | ||
e4ffd173 | 3205 | if (obj->cache_level == cache_level) |
a6a7cc4b | 3206 | return 0; |
e4ffd173 | 3207 | |
ef55f92a CW |
3208 | /* Inspect the list of currently bound VMA and unbind any that would |
3209 | * be invalid given the new cache-level. This is principally to | |
3210 | * catch the issue of the CS prefetch crossing page boundaries and | |
3211 | * reading an invalid PTE on older architectures. | |
3212 | */ | |
aa653a68 CW |
3213 | restart: |
3214 | list_for_each_entry(vma, &obj->vma_list, obj_link) { | |
ef55f92a CW |
3215 | if (!drm_mm_node_allocated(&vma->node)) |
3216 | continue; | |
3217 | ||
20dfbde4 | 3218 | if (i915_vma_is_pinned(vma)) { |
ef55f92a CW |
3219 | DRM_DEBUG("can not change the cache level of pinned objects\n"); |
3220 | return -EBUSY; | |
3221 | } | |
3222 | ||
aa653a68 CW |
3223 | if (i915_gem_valid_gtt_space(vma, cache_level)) |
3224 | continue; | |
3225 | ||
3226 | ret = i915_vma_unbind(vma); | |
3227 | if (ret) | |
3228 | return ret; | |
3229 | ||
3230 | /* As unbinding may affect other elements in the | |
3231 | * obj->vma_list (due to side-effects from retiring | |
3232 | * an active vma), play safe and restart the iterator. | |
3233 | */ | |
3234 | goto restart; | |
42d6ab48 CW |
3235 | } |
3236 | ||
ef55f92a CW |
3237 | /* We can reuse the existing drm_mm nodes but need to change the |
3238 | * cache-level on the PTE. We could simply unbind them all and | |
3239 | * rebind with the correct cache-level on next use. However since | |
3240 | * we already have a valid slot, dma mapping, pages etc, we may as | |
3241 | * rewrite the PTE in the belief that doing so tramples upon less | |
3242 | * state and so involves less work. | |
3243 | */ | |
15717de2 | 3244 | if (obj->bind_count) { |
ef55f92a CW |
3245 | /* Before we change the PTE, the GPU must not be accessing it. |
3246 | * If we wait upon the object, we know that all the bound | |
3247 | * VMA are no longer active. | |
3248 | */ | |
e95433c7 CW |
3249 | ret = i915_gem_object_wait(obj, |
3250 | I915_WAIT_INTERRUPTIBLE | | |
3251 | I915_WAIT_LOCKED | | |
3252 | I915_WAIT_ALL, | |
3253 | MAX_SCHEDULE_TIMEOUT, | |
3254 | NULL); | |
e4ffd173 CW |
3255 | if (ret) |
3256 | return ret; | |
3257 | ||
0031fb96 TU |
3258 | if (!HAS_LLC(to_i915(obj->base.dev)) && |
3259 | cache_level != I915_CACHE_NONE) { | |
ef55f92a CW |
3260 | /* Access to snoopable pages through the GTT is |
3261 | * incoherent and on some machines causes a hard | |
3262 | * lockup. Relinquish the CPU mmaping to force | |
3263 | * userspace to refault in the pages and we can | |
3264 | * then double check if the GTT mapping is still | |
3265 | * valid for that pointer access. | |
3266 | */ | |
3267 | i915_gem_release_mmap(obj); | |
3268 | ||
3269 | /* As we no longer need a fence for GTT access, | |
3270 | * we can relinquish it now (and so prevent having | |
3271 | * to steal a fence from someone else on the next | |
3272 | * fence request). Note GPU activity would have | |
3273 | * dropped the fence as all snoopable access is | |
3274 | * supposed to be linear. | |
3275 | */ | |
49ef5294 CW |
3276 | list_for_each_entry(vma, &obj->vma_list, obj_link) { |
3277 | ret = i915_vma_put_fence(vma); | |
3278 | if (ret) | |
3279 | return ret; | |
3280 | } | |
ef55f92a CW |
3281 | } else { |
3282 | /* We either have incoherent backing store and | |
3283 | * so no GTT access or the architecture is fully | |
3284 | * coherent. In such cases, existing GTT mmaps | |
3285 | * ignore the cache bit in the PTE and we can | |
3286 | * rewrite it without confusing the GPU or having | |
3287 | * to force userspace to fault back in its mmaps. | |
3288 | */ | |
e4ffd173 CW |
3289 | } |
3290 | ||
1c7f4bca | 3291 | list_for_each_entry(vma, &obj->vma_list, obj_link) { |
ef55f92a CW |
3292 | if (!drm_mm_node_allocated(&vma->node)) |
3293 | continue; | |
3294 | ||
3295 | ret = i915_vma_bind(vma, cache_level, PIN_UPDATE); | |
3296 | if (ret) | |
3297 | return ret; | |
3298 | } | |
e4ffd173 CW |
3299 | } |
3300 | ||
a6a7cc4b CW |
3301 | if (obj->base.write_domain == I915_GEM_DOMAIN_CPU && |
3302 | cpu_cache_is_coherent(obj->base.dev, obj->cache_level)) | |
3303 | obj->cache_dirty = true; | |
3304 | ||
1c7f4bca | 3305 | list_for_each_entry(vma, &obj->vma_list, obj_link) |
2c22569b CW |
3306 | vma->node.color = cache_level; |
3307 | obj->cache_level = cache_level; | |
3308 | ||
e4ffd173 CW |
3309 | return 0; |
3310 | } | |
3311 | ||
199adf40 BW |
3312 | int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data, |
3313 | struct drm_file *file) | |
e6994aee | 3314 | { |
199adf40 | 3315 | struct drm_i915_gem_caching *args = data; |
e6994aee | 3316 | struct drm_i915_gem_object *obj; |
fbbd37b3 | 3317 | int err = 0; |
e6994aee | 3318 | |
fbbd37b3 CW |
3319 | rcu_read_lock(); |
3320 | obj = i915_gem_object_lookup_rcu(file, args->handle); | |
3321 | if (!obj) { | |
3322 | err = -ENOENT; | |
3323 | goto out; | |
3324 | } | |
e6994aee | 3325 | |
651d794f CW |
3326 | switch (obj->cache_level) { |
3327 | case I915_CACHE_LLC: | |
3328 | case I915_CACHE_L3_LLC: | |
3329 | args->caching = I915_CACHING_CACHED; | |
3330 | break; | |
3331 | ||
4257d3ba CW |
3332 | case I915_CACHE_WT: |
3333 | args->caching = I915_CACHING_DISPLAY; | |
3334 | break; | |
3335 | ||
651d794f CW |
3336 | default: |
3337 | args->caching = I915_CACHING_NONE; | |
3338 | break; | |
3339 | } | |
fbbd37b3 CW |
3340 | out: |
3341 | rcu_read_unlock(); | |
3342 | return err; | |
e6994aee CW |
3343 | } |
3344 | ||
199adf40 BW |
3345 | int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data, |
3346 | struct drm_file *file) | |
e6994aee | 3347 | { |
9c870d03 | 3348 | struct drm_i915_private *i915 = to_i915(dev); |
199adf40 | 3349 | struct drm_i915_gem_caching *args = data; |
e6994aee CW |
3350 | struct drm_i915_gem_object *obj; |
3351 | enum i915_cache_level level; | |
3352 | int ret; | |
3353 | ||
199adf40 BW |
3354 | switch (args->caching) { |
3355 | case I915_CACHING_NONE: | |
e6994aee CW |
3356 | level = I915_CACHE_NONE; |
3357 | break; | |
199adf40 | 3358 | case I915_CACHING_CACHED: |
e5756c10 ID |
3359 | /* |
3360 | * Due to a HW issue on BXT A stepping, GPU stores via a | |
3361 | * snooped mapping may leave stale data in a corresponding CPU | |
3362 | * cacheline, whereas normally such cachelines would get | |
3363 | * invalidated. | |
3364 | */ | |
9c870d03 | 3365 | if (!HAS_LLC(i915) && !HAS_SNOOP(i915)) |
e5756c10 ID |
3366 | return -ENODEV; |
3367 | ||
e6994aee CW |
3368 | level = I915_CACHE_LLC; |
3369 | break; | |
4257d3ba | 3370 | case I915_CACHING_DISPLAY: |
9c870d03 | 3371 | level = HAS_WT(i915) ? I915_CACHE_WT : I915_CACHE_NONE; |
4257d3ba | 3372 | break; |
e6994aee CW |
3373 | default: |
3374 | return -EINVAL; | |
3375 | } | |
3376 | ||
3bc2913e BW |
3377 | ret = i915_mutex_lock_interruptible(dev); |
3378 | if (ret) | |
9c870d03 | 3379 | return ret; |
3bc2913e | 3380 | |
03ac0642 CW |
3381 | obj = i915_gem_object_lookup(file, args->handle); |
3382 | if (!obj) { | |
e6994aee CW |
3383 | ret = -ENOENT; |
3384 | goto unlock; | |
3385 | } | |
3386 | ||
3387 | ret = i915_gem_object_set_cache_level(obj, level); | |
f8c417cd | 3388 | i915_gem_object_put(obj); |
e6994aee CW |
3389 | unlock: |
3390 | mutex_unlock(&dev->struct_mutex); | |
3391 | return ret; | |
3392 | } | |
3393 | ||
b9241ea3 | 3394 | /* |
2da3b9b9 CW |
3395 | * Prepare buffer for display plane (scanout, cursors, etc). |
3396 | * Can be called from an uninterruptible phase (modesetting) and allows | |
3397 | * any flushes to be pipelined (for pageflips). | |
b9241ea3 | 3398 | */ |
058d88c4 | 3399 | struct i915_vma * |
2da3b9b9 CW |
3400 | i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj, |
3401 | u32 alignment, | |
e6617330 | 3402 | const struct i915_ggtt_view *view) |
b9241ea3 | 3403 | { |
058d88c4 | 3404 | struct i915_vma *vma; |
2da3b9b9 | 3405 | u32 old_read_domains, old_write_domain; |
b9241ea3 ZW |
3406 | int ret; |
3407 | ||
4c7d62c6 CW |
3408 | lockdep_assert_held(&obj->base.dev->struct_mutex); |
3409 | ||
cc98b413 CW |
3410 | /* Mark the pin_display early so that we account for the |
3411 | * display coherency whilst setting up the cache domains. | |
3412 | */ | |
8a0c39b1 | 3413 | obj->pin_display++; |
cc98b413 | 3414 | |
a7ef0640 EA |
3415 | /* The display engine is not coherent with the LLC cache on gen6. As |
3416 | * a result, we make sure that the pinning that is about to occur is | |
3417 | * done with uncached PTEs. This is lowest common denominator for all | |
3418 | * chipsets. | |
3419 | * | |
3420 | * However for gen6+, we could do better by using the GFDT bit instead | |
3421 | * of uncaching, which would allow us to flush all the LLC-cached data | |
3422 | * with that bit in the PTE to main memory with just one PIPE_CONTROL. | |
3423 | */ | |
651d794f | 3424 | ret = i915_gem_object_set_cache_level(obj, |
8652744b TU |
3425 | HAS_WT(to_i915(obj->base.dev)) ? |
3426 | I915_CACHE_WT : I915_CACHE_NONE); | |
058d88c4 CW |
3427 | if (ret) { |
3428 | vma = ERR_PTR(ret); | |
cc98b413 | 3429 | goto err_unpin_display; |
058d88c4 | 3430 | } |
a7ef0640 | 3431 | |
2da3b9b9 CW |
3432 | /* As the user may map the buffer once pinned in the display plane |
3433 | * (e.g. libkms for the bootup splash), we have to ensure that we | |
2efb813d CW |
3434 | * always use map_and_fenceable for all scanout buffers. However, |
3435 | * it may simply be too big to fit into mappable, in which case | |
3436 | * put it anyway and hope that userspace can cope (but always first | |
3437 | * try to preserve the existing ABI). | |
2da3b9b9 | 3438 | */ |
2efb813d CW |
3439 | vma = ERR_PTR(-ENOSPC); |
3440 | if (view->type == I915_GGTT_VIEW_NORMAL) | |
3441 | vma = i915_gem_object_ggtt_pin(obj, view, 0, alignment, | |
3442 | PIN_MAPPABLE | PIN_NONBLOCK); | |
767a222e CW |
3443 | if (IS_ERR(vma)) { |
3444 | struct drm_i915_private *i915 = to_i915(obj->base.dev); | |
3445 | unsigned int flags; | |
3446 | ||
3447 | /* Valleyview is definitely limited to scanning out the first | |
3448 | * 512MiB. Lets presume this behaviour was inherited from the | |
3449 | * g4x display engine and that all earlier gen are similarly | |
3450 | * limited. Testing suggests that it is a little more | |
3451 | * complicated than this. For example, Cherryview appears quite | |
3452 | * happy to scanout from anywhere within its global aperture. | |
3453 | */ | |
3454 | flags = 0; | |
3455 | if (HAS_GMCH_DISPLAY(i915)) | |
3456 | flags = PIN_MAPPABLE; | |
3457 | vma = i915_gem_object_ggtt_pin(obj, view, 0, alignment, flags); | |
3458 | } | |
058d88c4 | 3459 | if (IS_ERR(vma)) |
cc98b413 | 3460 | goto err_unpin_display; |
2da3b9b9 | 3461 | |
d8923dcf CW |
3462 | vma->display_alignment = max_t(u64, vma->display_alignment, alignment); |
3463 | ||
a6a7cc4b CW |
3464 | /* Treat this as an end-of-frame, like intel_user_framebuffer_dirty() */ |
3465 | if (obj->cache_dirty) { | |
3466 | i915_gem_clflush_object(obj, true); | |
3467 | intel_fb_obj_flush(obj, false, ORIGIN_DIRTYFB); | |
3468 | } | |
b118c1e3 | 3469 | |
2da3b9b9 | 3470 | old_write_domain = obj->base.write_domain; |
05394f39 | 3471 | old_read_domains = obj->base.read_domains; |
2da3b9b9 CW |
3472 | |
3473 | /* It should now be out of any other write domains, and we can update | |
3474 | * the domain values for our changes. | |
3475 | */ | |
e5f1d962 | 3476 | obj->base.write_domain = 0; |
05394f39 | 3477 | obj->base.read_domains |= I915_GEM_DOMAIN_GTT; |
b9241ea3 ZW |
3478 | |
3479 | trace_i915_gem_object_change_domain(obj, | |
3480 | old_read_domains, | |
2da3b9b9 | 3481 | old_write_domain); |
b9241ea3 | 3482 | |
058d88c4 | 3483 | return vma; |
cc98b413 CW |
3484 | |
3485 | err_unpin_display: | |
8a0c39b1 | 3486 | obj->pin_display--; |
058d88c4 | 3487 | return vma; |
cc98b413 CW |
3488 | } |
3489 | ||
3490 | void | |
058d88c4 | 3491 | i915_gem_object_unpin_from_display_plane(struct i915_vma *vma) |
cc98b413 | 3492 | { |
4c7d62c6 CW |
3493 | lockdep_assert_held(&vma->vm->dev->struct_mutex); |
3494 | ||
058d88c4 | 3495 | if (WARN_ON(vma->obj->pin_display == 0)) |
8a0c39b1 TU |
3496 | return; |
3497 | ||
d8923dcf CW |
3498 | if (--vma->obj->pin_display == 0) |
3499 | vma->display_alignment = 0; | |
e6617330 | 3500 | |
383d5823 CW |
3501 | /* Bump the LRU to try and avoid premature eviction whilst flipping */ |
3502 | if (!i915_vma_is_active(vma)) | |
3503 | list_move_tail(&vma->vm_link, &vma->vm->inactive_list); | |
3504 | ||
058d88c4 | 3505 | i915_vma_unpin(vma); |
b9241ea3 ZW |
3506 | } |
3507 | ||
e47c68e9 EA |
3508 | /** |
3509 | * Moves a single object to the CPU read, and possibly write domain. | |
14bb2c11 TU |
3510 | * @obj: object to act on |
3511 | * @write: requesting write or read-only access | |
e47c68e9 EA |
3512 | * |
3513 | * This function returns when the move is complete, including waiting on | |
3514 | * flushes to occur. | |
3515 | */ | |
dabdfe02 | 3516 | int |
919926ae | 3517 | i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write) |
e47c68e9 | 3518 | { |
1c5d22f7 | 3519 | uint32_t old_write_domain, old_read_domains; |
e47c68e9 EA |
3520 | int ret; |
3521 | ||
e95433c7 | 3522 | lockdep_assert_held(&obj->base.dev->struct_mutex); |
4c7d62c6 | 3523 | |
e95433c7 CW |
3524 | ret = i915_gem_object_wait(obj, |
3525 | I915_WAIT_INTERRUPTIBLE | | |
3526 | I915_WAIT_LOCKED | | |
3527 | (write ? I915_WAIT_ALL : 0), | |
3528 | MAX_SCHEDULE_TIMEOUT, | |
3529 | NULL); | |
88241785 CW |
3530 | if (ret) |
3531 | return ret; | |
3532 | ||
c13d87ea CW |
3533 | if (obj->base.write_domain == I915_GEM_DOMAIN_CPU) |
3534 | return 0; | |
3535 | ||
e47c68e9 | 3536 | i915_gem_object_flush_gtt_write_domain(obj); |
2ef7eeaa | 3537 | |
05394f39 CW |
3538 | old_write_domain = obj->base.write_domain; |
3539 | old_read_domains = obj->base.read_domains; | |
1c5d22f7 | 3540 | |
e47c68e9 | 3541 | /* Flush the CPU cache if it's still invalid. */ |
05394f39 | 3542 | if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) { |
2c22569b | 3543 | i915_gem_clflush_object(obj, false); |
2ef7eeaa | 3544 | |
05394f39 | 3545 | obj->base.read_domains |= I915_GEM_DOMAIN_CPU; |
2ef7eeaa EA |
3546 | } |
3547 | ||
3548 | /* It should now be out of any other write domains, and we can update | |
3549 | * the domain values for our changes. | |
3550 | */ | |
40e62d5d | 3551 | GEM_BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) != 0); |
e47c68e9 EA |
3552 | |
3553 | /* If we're writing through the CPU, then the GPU read domains will | |
3554 | * need to be invalidated at next use. | |
3555 | */ | |
3556 | if (write) { | |
05394f39 CW |
3557 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; |
3558 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; | |
e47c68e9 | 3559 | } |
2ef7eeaa | 3560 | |
1c5d22f7 CW |
3561 | trace_i915_gem_object_change_domain(obj, |
3562 | old_read_domains, | |
3563 | old_write_domain); | |
3564 | ||
2ef7eeaa EA |
3565 | return 0; |
3566 | } | |
3567 | ||
673a394b EA |
3568 | /* Throttle our rendering by waiting until the ring has completed our requests |
3569 | * emitted over 20 msec ago. | |
3570 | * | |
b962442e EA |
3571 | * Note that if we were to use the current jiffies each time around the loop, |
3572 | * we wouldn't escape the function with any frames outstanding if the time to | |
3573 | * render a frame was over 20ms. | |
3574 | * | |
673a394b EA |
3575 | * This should get us reasonable parallelism between CPU and GPU but also |
3576 | * relatively low latency when blocking on a particular request to finish. | |
3577 | */ | |
40a5f0de | 3578 | static int |
f787a5f5 | 3579 | i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file) |
40a5f0de | 3580 | { |
fac5e23e | 3581 | struct drm_i915_private *dev_priv = to_i915(dev); |
f787a5f5 | 3582 | struct drm_i915_file_private *file_priv = file->driver_priv; |
d0bc54f2 | 3583 | unsigned long recent_enough = jiffies - DRM_I915_THROTTLE_JIFFIES; |
54fb2411 | 3584 | struct drm_i915_gem_request *request, *target = NULL; |
e95433c7 | 3585 | long ret; |
93533c29 | 3586 | |
f4457ae7 CW |
3587 | /* ABI: return -EIO if already wedged */ |
3588 | if (i915_terminally_wedged(&dev_priv->gpu_error)) | |
3589 | return -EIO; | |
e110e8d6 | 3590 | |
1c25595f | 3591 | spin_lock(&file_priv->mm.lock); |
f787a5f5 | 3592 | list_for_each_entry(request, &file_priv->mm.request_list, client_list) { |
b962442e EA |
3593 | if (time_after_eq(request->emitted_jiffies, recent_enough)) |
3594 | break; | |
40a5f0de | 3595 | |
fcfa423c JH |
3596 | /* |
3597 | * Note that the request might not have been submitted yet. | |
3598 | * In which case emitted_jiffies will be zero. | |
3599 | */ | |
3600 | if (!request->emitted_jiffies) | |
3601 | continue; | |
3602 | ||
54fb2411 | 3603 | target = request; |
b962442e | 3604 | } |
ff865885 | 3605 | if (target) |
e8a261ea | 3606 | i915_gem_request_get(target); |
1c25595f | 3607 | spin_unlock(&file_priv->mm.lock); |
40a5f0de | 3608 | |
54fb2411 | 3609 | if (target == NULL) |
f787a5f5 | 3610 | return 0; |
2bc43b5c | 3611 | |
e95433c7 CW |
3612 | ret = i915_wait_request(target, |
3613 | I915_WAIT_INTERRUPTIBLE, | |
3614 | MAX_SCHEDULE_TIMEOUT); | |
e8a261ea | 3615 | i915_gem_request_put(target); |
ff865885 | 3616 | |
e95433c7 | 3617 | return ret < 0 ? ret : 0; |
40a5f0de EA |
3618 | } |
3619 | ||
058d88c4 | 3620 | struct i915_vma * |
ec7adb6e JL |
3621 | i915_gem_object_ggtt_pin(struct drm_i915_gem_object *obj, |
3622 | const struct i915_ggtt_view *view, | |
91b2db6f | 3623 | u64 size, |
2ffffd0f CW |
3624 | u64 alignment, |
3625 | u64 flags) | |
ec7adb6e | 3626 | { |
ad16d2ed CW |
3627 | struct drm_i915_private *dev_priv = to_i915(obj->base.dev); |
3628 | struct i915_address_space *vm = &dev_priv->ggtt.base; | |
59bfa124 CW |
3629 | struct i915_vma *vma; |
3630 | int ret; | |
72e96d64 | 3631 | |
4c7d62c6 CW |
3632 | lockdep_assert_held(&obj->base.dev->struct_mutex); |
3633 | ||
058d88c4 | 3634 | vma = i915_gem_obj_lookup_or_create_vma(obj, vm, view); |
59bfa124 | 3635 | if (IS_ERR(vma)) |
058d88c4 | 3636 | return vma; |
59bfa124 CW |
3637 | |
3638 | if (i915_vma_misplaced(vma, size, alignment, flags)) { | |
3639 | if (flags & PIN_NONBLOCK && | |
3640 | (i915_vma_is_pinned(vma) || i915_vma_is_active(vma))) | |
058d88c4 | 3641 | return ERR_PTR(-ENOSPC); |
59bfa124 | 3642 | |
ad16d2ed CW |
3643 | if (flags & PIN_MAPPABLE) { |
3644 | u32 fence_size; | |
3645 | ||
3646 | fence_size = i915_gem_get_ggtt_size(dev_priv, vma->size, | |
3647 | i915_gem_object_get_tiling(obj)); | |
3648 | /* If the required space is larger than the available | |
3649 | * aperture, we will not able to find a slot for the | |
3650 | * object and unbinding the object now will be in | |
3651 | * vain. Worse, doing so may cause us to ping-pong | |
3652 | * the object in and out of the Global GTT and | |
3653 | * waste a lot of cycles under the mutex. | |
3654 | */ | |
3655 | if (fence_size > dev_priv->ggtt.mappable_end) | |
3656 | return ERR_PTR(-E2BIG); | |
3657 | ||
3658 | /* If NONBLOCK is set the caller is optimistically | |
3659 | * trying to cache the full object within the mappable | |
3660 | * aperture, and *must* have a fallback in place for | |
3661 | * situations where we cannot bind the object. We | |
3662 | * can be a little more lax here and use the fallback | |
3663 | * more often to avoid costly migrations of ourselves | |
3664 | * and other objects within the aperture. | |
3665 | * | |
3666 | * Half-the-aperture is used as a simple heuristic. | |
3667 | * More interesting would to do search for a free | |
3668 | * block prior to making the commitment to unbind. | |
3669 | * That caters for the self-harm case, and with a | |
3670 | * little more heuristics (e.g. NOFAULT, NOEVICT) | |
3671 | * we could try to minimise harm to others. | |
3672 | */ | |
3673 | if (flags & PIN_NONBLOCK && | |
3674 | fence_size > dev_priv->ggtt.mappable_end / 2) | |
3675 | return ERR_PTR(-ENOSPC); | |
3676 | } | |
3677 | ||
59bfa124 CW |
3678 | WARN(i915_vma_is_pinned(vma), |
3679 | "bo is already pinned in ggtt with incorrect alignment:" | |
05a20d09 CW |
3680 | " offset=%08x, req.alignment=%llx," |
3681 | " req.map_and_fenceable=%d, vma->map_and_fenceable=%d\n", | |
3682 | i915_ggtt_offset(vma), alignment, | |
59bfa124 | 3683 | !!(flags & PIN_MAPPABLE), |
05a20d09 | 3684 | i915_vma_is_map_and_fenceable(vma)); |
59bfa124 CW |
3685 | ret = i915_vma_unbind(vma); |
3686 | if (ret) | |
058d88c4 | 3687 | return ERR_PTR(ret); |
59bfa124 CW |
3688 | } |
3689 | ||
058d88c4 CW |
3690 | ret = i915_vma_pin(vma, size, alignment, flags | PIN_GLOBAL); |
3691 | if (ret) | |
3692 | return ERR_PTR(ret); | |
ec7adb6e | 3693 | |
058d88c4 | 3694 | return vma; |
673a394b EA |
3695 | } |
3696 | ||
edf6b76f | 3697 | static __always_inline unsigned int __busy_read_flag(unsigned int id) |
3fdc13c7 CW |
3698 | { |
3699 | /* Note that we could alias engines in the execbuf API, but | |
3700 | * that would be very unwise as it prevents userspace from | |
3701 | * fine control over engine selection. Ahem. | |
3702 | * | |
3703 | * This should be something like EXEC_MAX_ENGINE instead of | |
3704 | * I915_NUM_ENGINES. | |
3705 | */ | |
3706 | BUILD_BUG_ON(I915_NUM_ENGINES > 16); | |
3707 | return 0x10000 << id; | |
3708 | } | |
3709 | ||
3710 | static __always_inline unsigned int __busy_write_id(unsigned int id) | |
3711 | { | |
70cb472c CW |
3712 | /* The uABI guarantees an active writer is also amongst the read |
3713 | * engines. This would be true if we accessed the activity tracking | |
3714 | * under the lock, but as we perform the lookup of the object and | |
3715 | * its activity locklessly we can not guarantee that the last_write | |
3716 | * being active implies that we have set the same engine flag from | |
3717 | * last_read - hence we always set both read and write busy for | |
3718 | * last_write. | |
3719 | */ | |
3720 | return id | __busy_read_flag(id); | |
3fdc13c7 CW |
3721 | } |
3722 | ||
edf6b76f | 3723 | static __always_inline unsigned int |
d07f0e59 | 3724 | __busy_set_if_active(const struct dma_fence *fence, |
3fdc13c7 CW |
3725 | unsigned int (*flag)(unsigned int id)) |
3726 | { | |
d07f0e59 | 3727 | struct drm_i915_gem_request *rq; |
3fdc13c7 | 3728 | |
d07f0e59 CW |
3729 | /* We have to check the current hw status of the fence as the uABI |
3730 | * guarantees forward progress. We could rely on the idle worker | |
3731 | * to eventually flush us, but to minimise latency just ask the | |
3732 | * hardware. | |
1255501d | 3733 | * |
d07f0e59 | 3734 | * Note we only report on the status of native fences. |
1255501d | 3735 | */ |
d07f0e59 CW |
3736 | if (!dma_fence_is_i915(fence)) |
3737 | return 0; | |
3738 | ||
3739 | /* opencode to_request() in order to avoid const warnings */ | |
3740 | rq = container_of(fence, struct drm_i915_gem_request, fence); | |
3741 | if (i915_gem_request_completed(rq)) | |
3742 | return 0; | |
3743 | ||
3744 | return flag(rq->engine->exec_id); | |
3fdc13c7 CW |
3745 | } |
3746 | ||
edf6b76f | 3747 | static __always_inline unsigned int |
d07f0e59 | 3748 | busy_check_reader(const struct dma_fence *fence) |
3fdc13c7 | 3749 | { |
d07f0e59 | 3750 | return __busy_set_if_active(fence, __busy_read_flag); |
3fdc13c7 CW |
3751 | } |
3752 | ||
edf6b76f | 3753 | static __always_inline unsigned int |
d07f0e59 | 3754 | busy_check_writer(const struct dma_fence *fence) |
3fdc13c7 | 3755 | { |
d07f0e59 CW |
3756 | if (!fence) |
3757 | return 0; | |
3758 | ||
3759 | return __busy_set_if_active(fence, __busy_write_id); | |
3fdc13c7 CW |
3760 | } |
3761 | ||
673a394b EA |
3762 | int |
3763 | i915_gem_busy_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 3764 | struct drm_file *file) |
673a394b EA |
3765 | { |
3766 | struct drm_i915_gem_busy *args = data; | |
05394f39 | 3767 | struct drm_i915_gem_object *obj; |
d07f0e59 CW |
3768 | struct reservation_object_list *list; |
3769 | unsigned int seq; | |
fbbd37b3 | 3770 | int err; |
673a394b | 3771 | |
d07f0e59 | 3772 | err = -ENOENT; |
fbbd37b3 CW |
3773 | rcu_read_lock(); |
3774 | obj = i915_gem_object_lookup_rcu(file, args->handle); | |
d07f0e59 | 3775 | if (!obj) |
fbbd37b3 | 3776 | goto out; |
d1b851fc | 3777 | |
d07f0e59 CW |
3778 | /* A discrepancy here is that we do not report the status of |
3779 | * non-i915 fences, i.e. even though we may report the object as idle, | |
3780 | * a call to set-domain may still stall waiting for foreign rendering. | |
3781 | * This also means that wait-ioctl may report an object as busy, | |
3782 | * where busy-ioctl considers it idle. | |
3783 | * | |
3784 | * We trade the ability to warn of foreign fences to report on which | |
3785 | * i915 engines are active for the object. | |
3786 | * | |
3787 | * Alternatively, we can trade that extra information on read/write | |
3788 | * activity with | |
3789 | * args->busy = | |
3790 | * !reservation_object_test_signaled_rcu(obj->resv, true); | |
3791 | * to report the overall busyness. This is what the wait-ioctl does. | |
3792 | * | |
3793 | */ | |
3794 | retry: | |
3795 | seq = raw_read_seqcount(&obj->resv->seq); | |
426960be | 3796 | |
d07f0e59 CW |
3797 | /* Translate the exclusive fence to the READ *and* WRITE engine */ |
3798 | args->busy = busy_check_writer(rcu_dereference(obj->resv->fence_excl)); | |
3fdc13c7 | 3799 | |
d07f0e59 CW |
3800 | /* Translate shared fences to READ set of engines */ |
3801 | list = rcu_dereference(obj->resv->fence); | |
3802 | if (list) { | |
3803 | unsigned int shared_count = list->shared_count, i; | |
3fdc13c7 | 3804 | |
d07f0e59 CW |
3805 | for (i = 0; i < shared_count; ++i) { |
3806 | struct dma_fence *fence = | |
3807 | rcu_dereference(list->shared[i]); | |
3808 | ||
3809 | args->busy |= busy_check_reader(fence); | |
3810 | } | |
426960be | 3811 | } |
673a394b | 3812 | |
d07f0e59 CW |
3813 | if (args->busy && read_seqcount_retry(&obj->resv->seq, seq)) |
3814 | goto retry; | |
3815 | ||
3816 | err = 0; | |
fbbd37b3 CW |
3817 | out: |
3818 | rcu_read_unlock(); | |
3819 | return err; | |
673a394b EA |
3820 | } |
3821 | ||
3822 | int | |
3823 | i915_gem_throttle_ioctl(struct drm_device *dev, void *data, | |
3824 | struct drm_file *file_priv) | |
3825 | { | |
0206e353 | 3826 | return i915_gem_ring_throttle(dev, file_priv); |
673a394b EA |
3827 | } |
3828 | ||
3ef94daa CW |
3829 | int |
3830 | i915_gem_madvise_ioctl(struct drm_device *dev, void *data, | |
3831 | struct drm_file *file_priv) | |
3832 | { | |
fac5e23e | 3833 | struct drm_i915_private *dev_priv = to_i915(dev); |
3ef94daa | 3834 | struct drm_i915_gem_madvise *args = data; |
05394f39 | 3835 | struct drm_i915_gem_object *obj; |
1233e2db | 3836 | int err; |
3ef94daa CW |
3837 | |
3838 | switch (args->madv) { | |
3839 | case I915_MADV_DONTNEED: | |
3840 | case I915_MADV_WILLNEED: | |
3841 | break; | |
3842 | default: | |
3843 | return -EINVAL; | |
3844 | } | |
3845 | ||
03ac0642 | 3846 | obj = i915_gem_object_lookup(file_priv, args->handle); |
1233e2db CW |
3847 | if (!obj) |
3848 | return -ENOENT; | |
3849 | ||
3850 | err = mutex_lock_interruptible(&obj->mm.lock); | |
3851 | if (err) | |
3852 | goto out; | |
3ef94daa | 3853 | |
a4f5ea64 | 3854 | if (obj->mm.pages && |
3e510a8e | 3855 | i915_gem_object_is_tiled(obj) && |
656bfa3a | 3856 | dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES) { |
bc0629a7 CW |
3857 | if (obj->mm.madv == I915_MADV_WILLNEED) { |
3858 | GEM_BUG_ON(!obj->mm.quirked); | |
a4f5ea64 | 3859 | __i915_gem_object_unpin_pages(obj); |
bc0629a7 CW |
3860 | obj->mm.quirked = false; |
3861 | } | |
3862 | if (args->madv == I915_MADV_WILLNEED) { | |
2c3a3f44 | 3863 | GEM_BUG_ON(obj->mm.quirked); |
a4f5ea64 | 3864 | __i915_gem_object_pin_pages(obj); |
bc0629a7 CW |
3865 | obj->mm.quirked = true; |
3866 | } | |
656bfa3a DV |
3867 | } |
3868 | ||
a4f5ea64 CW |
3869 | if (obj->mm.madv != __I915_MADV_PURGED) |
3870 | obj->mm.madv = args->madv; | |
3ef94daa | 3871 | |
6c085a72 | 3872 | /* if the object is no longer attached, discard its backing storage */ |
a4f5ea64 | 3873 | if (obj->mm.madv == I915_MADV_DONTNEED && !obj->mm.pages) |
2d7ef395 CW |
3874 | i915_gem_object_truncate(obj); |
3875 | ||
a4f5ea64 | 3876 | args->retained = obj->mm.madv != __I915_MADV_PURGED; |
1233e2db | 3877 | mutex_unlock(&obj->mm.lock); |
bb6baf76 | 3878 | |
1233e2db | 3879 | out: |
f8c417cd | 3880 | i915_gem_object_put(obj); |
1233e2db | 3881 | return err; |
3ef94daa CW |
3882 | } |
3883 | ||
5b8c8aec CW |
3884 | static void |
3885 | frontbuffer_retire(struct i915_gem_active *active, | |
3886 | struct drm_i915_gem_request *request) | |
3887 | { | |
3888 | struct drm_i915_gem_object *obj = | |
3889 | container_of(active, typeof(*obj), frontbuffer_write); | |
3890 | ||
3891 | intel_fb_obj_flush(obj, true, ORIGIN_CS); | |
3892 | } | |
3893 | ||
37e680a1 CW |
3894 | void i915_gem_object_init(struct drm_i915_gem_object *obj, |
3895 | const struct drm_i915_gem_object_ops *ops) | |
0327d6ba | 3896 | { |
1233e2db CW |
3897 | mutex_init(&obj->mm.lock); |
3898 | ||
56cea323 | 3899 | INIT_LIST_HEAD(&obj->global_link); |
275f039d | 3900 | INIT_LIST_HEAD(&obj->userfault_link); |
b25cb2f8 | 3901 | INIT_LIST_HEAD(&obj->obj_exec_link); |
2f633156 | 3902 | INIT_LIST_HEAD(&obj->vma_list); |
8d9d5744 | 3903 | INIT_LIST_HEAD(&obj->batch_pool_link); |
0327d6ba | 3904 | |
37e680a1 CW |
3905 | obj->ops = ops; |
3906 | ||
d07f0e59 CW |
3907 | reservation_object_init(&obj->__builtin_resv); |
3908 | obj->resv = &obj->__builtin_resv; | |
3909 | ||
50349247 | 3910 | obj->frontbuffer_ggtt_origin = ORIGIN_GTT; |
5b8c8aec | 3911 | init_request_active(&obj->frontbuffer_write, frontbuffer_retire); |
a4f5ea64 CW |
3912 | |
3913 | obj->mm.madv = I915_MADV_WILLNEED; | |
3914 | INIT_RADIX_TREE(&obj->mm.get_page.radix, GFP_KERNEL | __GFP_NOWARN); | |
3915 | mutex_init(&obj->mm.get_page.lock); | |
0327d6ba | 3916 | |
f19ec8cb | 3917 | i915_gem_info_add_obj(to_i915(obj->base.dev), obj->base.size); |
0327d6ba CW |
3918 | } |
3919 | ||
37e680a1 | 3920 | static const struct drm_i915_gem_object_ops i915_gem_object_ops = { |
3599a91c TU |
3921 | .flags = I915_GEM_OBJECT_HAS_STRUCT_PAGE | |
3922 | I915_GEM_OBJECT_IS_SHRINKABLE, | |
37e680a1 CW |
3923 | .get_pages = i915_gem_object_get_pages_gtt, |
3924 | .put_pages = i915_gem_object_put_pages_gtt, | |
3925 | }; | |
3926 | ||
b4bcbe2a CW |
3927 | /* Note we don't consider signbits :| */ |
3928 | #define overflows_type(x, T) \ | |
3929 | (sizeof(x) > sizeof(T) && (x) >> (sizeof(T) * BITS_PER_BYTE)) | |
3930 | ||
3931 | struct drm_i915_gem_object * | |
3932 | i915_gem_object_create(struct drm_device *dev, u64 size) | |
ac52bc56 | 3933 | { |
a26e5239 | 3934 | struct drm_i915_private *dev_priv = to_i915(dev); |
c397b908 | 3935 | struct drm_i915_gem_object *obj; |
5949eac4 | 3936 | struct address_space *mapping; |
1a240d4d | 3937 | gfp_t mask; |
fe3db79b | 3938 | int ret; |
ac52bc56 | 3939 | |
b4bcbe2a CW |
3940 | /* There is a prevalence of the assumption that we fit the object's |
3941 | * page count inside a 32bit _signed_ variable. Let's document this and | |
3942 | * catch if we ever need to fix it. In the meantime, if you do spot | |
3943 | * such a local variable, please consider fixing! | |
3944 | */ | |
3945 | if (WARN_ON(size >> PAGE_SHIFT > INT_MAX)) | |
3946 | return ERR_PTR(-E2BIG); | |
3947 | ||
3948 | if (overflows_type(size, obj->base.size)) | |
3949 | return ERR_PTR(-E2BIG); | |
3950 | ||
42dcedd4 | 3951 | obj = i915_gem_object_alloc(dev); |
c397b908 | 3952 | if (obj == NULL) |
fe3db79b | 3953 | return ERR_PTR(-ENOMEM); |
673a394b | 3954 | |
fe3db79b CW |
3955 | ret = drm_gem_object_init(dev, &obj->base, size); |
3956 | if (ret) | |
3957 | goto fail; | |
673a394b | 3958 | |
bed1ea95 | 3959 | mask = GFP_HIGHUSER | __GFP_RECLAIMABLE; |
a26e5239 | 3960 | if (IS_CRESTLINE(dev_priv) || IS_BROADWATER(dev_priv)) { |
bed1ea95 CW |
3961 | /* 965gm cannot relocate objects above 4GiB. */ |
3962 | mask &= ~__GFP_HIGHMEM; | |
3963 | mask |= __GFP_DMA32; | |
3964 | } | |
3965 | ||
93c76a3d | 3966 | mapping = obj->base.filp->f_mapping; |
bed1ea95 | 3967 | mapping_set_gfp_mask(mapping, mask); |
5949eac4 | 3968 | |
37e680a1 | 3969 | i915_gem_object_init(obj, &i915_gem_object_ops); |
73aa808f | 3970 | |
c397b908 DV |
3971 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; |
3972 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; | |
673a394b | 3973 | |
0031fb96 | 3974 | if (HAS_LLC(dev_priv)) { |
3d29b842 | 3975 | /* On some devices, we can have the GPU use the LLC (the CPU |
a1871112 EA |
3976 | * cache) for about a 10% performance improvement |
3977 | * compared to uncached. Graphics requests other than | |
3978 | * display scanout are coherent with the CPU in | |
3979 | * accessing this cache. This means in this mode we | |
3980 | * don't need to clflush on the CPU side, and on the | |
3981 | * GPU side we only need to flush internal caches to | |
3982 | * get data visible to the CPU. | |
3983 | * | |
3984 | * However, we maintain the display planes as UC, and so | |
3985 | * need to rebind when first used as such. | |
3986 | */ | |
3987 | obj->cache_level = I915_CACHE_LLC; | |
3988 | } else | |
3989 | obj->cache_level = I915_CACHE_NONE; | |
3990 | ||
d861e338 DV |
3991 | trace_i915_gem_object_create(obj); |
3992 | ||
05394f39 | 3993 | return obj; |
fe3db79b CW |
3994 | |
3995 | fail: | |
3996 | i915_gem_object_free(obj); | |
fe3db79b | 3997 | return ERR_PTR(ret); |
c397b908 DV |
3998 | } |
3999 | ||
340fbd8c CW |
4000 | static bool discard_backing_storage(struct drm_i915_gem_object *obj) |
4001 | { | |
4002 | /* If we are the last user of the backing storage (be it shmemfs | |
4003 | * pages or stolen etc), we know that the pages are going to be | |
4004 | * immediately released. In this case, we can then skip copying | |
4005 | * back the contents from the GPU. | |
4006 | */ | |
4007 | ||
a4f5ea64 | 4008 | if (obj->mm.madv != I915_MADV_WILLNEED) |
340fbd8c CW |
4009 | return false; |
4010 | ||
4011 | if (obj->base.filp == NULL) | |
4012 | return true; | |
4013 | ||
4014 | /* At first glance, this looks racy, but then again so would be | |
4015 | * userspace racing mmap against close. However, the first external | |
4016 | * reference to the filp can only be obtained through the | |
4017 | * i915_gem_mmap_ioctl() which safeguards us against the user | |
4018 | * acquiring such a reference whilst we are in the middle of | |
4019 | * freeing the object. | |
4020 | */ | |
4021 | return atomic_long_read(&obj->base.filp->f_count) == 1; | |
4022 | } | |
4023 | ||
fbbd37b3 CW |
4024 | static void __i915_gem_free_objects(struct drm_i915_private *i915, |
4025 | struct llist_node *freed) | |
673a394b | 4026 | { |
fbbd37b3 | 4027 | struct drm_i915_gem_object *obj, *on; |
673a394b | 4028 | |
fbbd37b3 CW |
4029 | mutex_lock(&i915->drm.struct_mutex); |
4030 | intel_runtime_pm_get(i915); | |
4031 | llist_for_each_entry(obj, freed, freed) { | |
4032 | struct i915_vma *vma, *vn; | |
4033 | ||
4034 | trace_i915_gem_object_destroy(obj); | |
4035 | ||
4036 | GEM_BUG_ON(i915_gem_object_is_active(obj)); | |
4037 | list_for_each_entry_safe(vma, vn, | |
4038 | &obj->vma_list, obj_link) { | |
4039 | GEM_BUG_ON(!i915_vma_is_ggtt(vma)); | |
4040 | GEM_BUG_ON(i915_vma_is_active(vma)); | |
4041 | vma->flags &= ~I915_VMA_PIN_MASK; | |
4042 | i915_vma_close(vma); | |
4043 | } | |
db6c2b41 CW |
4044 | GEM_BUG_ON(!list_empty(&obj->vma_list)); |
4045 | GEM_BUG_ON(!RB_EMPTY_ROOT(&obj->vma_tree)); | |
fbbd37b3 | 4046 | |
56cea323 | 4047 | list_del(&obj->global_link); |
fbbd37b3 CW |
4048 | } |
4049 | intel_runtime_pm_put(i915); | |
4050 | mutex_unlock(&i915->drm.struct_mutex); | |
4051 | ||
4052 | llist_for_each_entry_safe(obj, on, freed, freed) { | |
4053 | GEM_BUG_ON(obj->bind_count); | |
4054 | GEM_BUG_ON(atomic_read(&obj->frontbuffer_bits)); | |
4055 | ||
4056 | if (obj->ops->release) | |
4057 | obj->ops->release(obj); | |
f65c9168 | 4058 | |
fbbd37b3 CW |
4059 | if (WARN_ON(i915_gem_object_has_pinned_pages(obj))) |
4060 | atomic_set(&obj->mm.pages_pin_count, 0); | |
548625ee | 4061 | __i915_gem_object_put_pages(obj, I915_MM_NORMAL); |
fbbd37b3 CW |
4062 | GEM_BUG_ON(obj->mm.pages); |
4063 | ||
4064 | if (obj->base.import_attach) | |
4065 | drm_prime_gem_destroy(&obj->base, NULL); | |
4066 | ||
d07f0e59 | 4067 | reservation_object_fini(&obj->__builtin_resv); |
fbbd37b3 CW |
4068 | drm_gem_object_release(&obj->base); |
4069 | i915_gem_info_remove_obj(i915, obj->base.size); | |
4070 | ||
4071 | kfree(obj->bit_17); | |
4072 | i915_gem_object_free(obj); | |
4073 | } | |
4074 | } | |
4075 | ||
4076 | static void i915_gem_flush_free_objects(struct drm_i915_private *i915) | |
4077 | { | |
4078 | struct llist_node *freed; | |
4079 | ||
4080 | freed = llist_del_all(&i915->mm.free_list); | |
4081 | if (unlikely(freed)) | |
4082 | __i915_gem_free_objects(i915, freed); | |
4083 | } | |
4084 | ||
4085 | static void __i915_gem_free_work(struct work_struct *work) | |
4086 | { | |
4087 | struct drm_i915_private *i915 = | |
4088 | container_of(work, struct drm_i915_private, mm.free_work); | |
4089 | struct llist_node *freed; | |
26e12f89 | 4090 | |
b1f788c6 CW |
4091 | /* All file-owned VMA should have been released by this point through |
4092 | * i915_gem_close_object(), or earlier by i915_gem_context_close(). | |
4093 | * However, the object may also be bound into the global GTT (e.g. | |
4094 | * older GPUs without per-process support, or for direct access through | |
4095 | * the GTT either for the user or for scanout). Those VMA still need to | |
4096 | * unbound now. | |
4097 | */ | |
1488fc08 | 4098 | |
fbbd37b3 CW |
4099 | while ((freed = llist_del_all(&i915->mm.free_list))) |
4100 | __i915_gem_free_objects(i915, freed); | |
4101 | } | |
a071fa00 | 4102 | |
fbbd37b3 CW |
4103 | static void __i915_gem_free_object_rcu(struct rcu_head *head) |
4104 | { | |
4105 | struct drm_i915_gem_object *obj = | |
4106 | container_of(head, typeof(*obj), rcu); | |
4107 | struct drm_i915_private *i915 = to_i915(obj->base.dev); | |
4108 | ||
4109 | /* We can't simply use call_rcu() from i915_gem_free_object() | |
4110 | * as we need to block whilst unbinding, and the call_rcu | |
4111 | * task may be called from softirq context. So we take a | |
4112 | * detour through a worker. | |
4113 | */ | |
4114 | if (llist_add(&obj->freed, &i915->mm.free_list)) | |
4115 | schedule_work(&i915->mm.free_work); | |
4116 | } | |
656bfa3a | 4117 | |
fbbd37b3 CW |
4118 | void i915_gem_free_object(struct drm_gem_object *gem_obj) |
4119 | { | |
4120 | struct drm_i915_gem_object *obj = to_intel_bo(gem_obj); | |
a4f5ea64 | 4121 | |
bc0629a7 CW |
4122 | if (obj->mm.quirked) |
4123 | __i915_gem_object_unpin_pages(obj); | |
4124 | ||
340fbd8c | 4125 | if (discard_backing_storage(obj)) |
a4f5ea64 | 4126 | obj->mm.madv = I915_MADV_DONTNEED; |
de151cf6 | 4127 | |
fbbd37b3 CW |
4128 | /* Before we free the object, make sure any pure RCU-only |
4129 | * read-side critical sections are complete, e.g. | |
4130 | * i915_gem_busy_ioctl(). For the corresponding synchronized | |
4131 | * lookup see i915_gem_object_lookup_rcu(). | |
4132 | */ | |
4133 | call_rcu(&obj->rcu, __i915_gem_free_object_rcu); | |
673a394b EA |
4134 | } |
4135 | ||
f8a7fde4 CW |
4136 | void __i915_gem_object_release_unless_active(struct drm_i915_gem_object *obj) |
4137 | { | |
4138 | lockdep_assert_held(&obj->base.dev->struct_mutex); | |
4139 | ||
4140 | GEM_BUG_ON(i915_gem_object_has_active_reference(obj)); | |
4141 | if (i915_gem_object_is_active(obj)) | |
4142 | i915_gem_object_set_active_reference(obj); | |
4143 | else | |
4144 | i915_gem_object_put(obj); | |
4145 | } | |
4146 | ||
3033acab CW |
4147 | static void assert_kernel_context_is_current(struct drm_i915_private *dev_priv) |
4148 | { | |
4149 | struct intel_engine_cs *engine; | |
4150 | enum intel_engine_id id; | |
4151 | ||
4152 | for_each_engine(engine, dev_priv, id) | |
4153 | GEM_BUG_ON(engine->last_context != dev_priv->kernel_context); | |
4154 | } | |
4155 | ||
dcff85c8 | 4156 | int i915_gem_suspend(struct drm_device *dev) |
29105ccc | 4157 | { |
fac5e23e | 4158 | struct drm_i915_private *dev_priv = to_i915(dev); |
dcff85c8 | 4159 | int ret; |
28dfe52a | 4160 | |
54b4f68f CW |
4161 | intel_suspend_gt_powersave(dev_priv); |
4162 | ||
45c5f202 | 4163 | mutex_lock(&dev->struct_mutex); |
5ab57c70 CW |
4164 | |
4165 | /* We have to flush all the executing contexts to main memory so | |
4166 | * that they can saved in the hibernation image. To ensure the last | |
4167 | * context image is coherent, we have to switch away from it. That | |
4168 | * leaves the dev_priv->kernel_context still active when | |
4169 | * we actually suspend, and its image in memory may not match the GPU | |
4170 | * state. Fortunately, the kernel_context is disposable and we do | |
4171 | * not rely on its state. | |
4172 | */ | |
4173 | ret = i915_gem_switch_to_kernel_context(dev_priv); | |
4174 | if (ret) | |
4175 | goto err; | |
4176 | ||
22dd3bb9 CW |
4177 | ret = i915_gem_wait_for_idle(dev_priv, |
4178 | I915_WAIT_INTERRUPTIBLE | | |
4179 | I915_WAIT_LOCKED); | |
f7403347 | 4180 | if (ret) |
45c5f202 | 4181 | goto err; |
f7403347 | 4182 | |
c033666a | 4183 | i915_gem_retire_requests(dev_priv); |
28176ef4 | 4184 | GEM_BUG_ON(dev_priv->gt.active_requests); |
673a394b | 4185 | |
3033acab | 4186 | assert_kernel_context_is_current(dev_priv); |
b2e862d0 | 4187 | i915_gem_context_lost(dev_priv); |
45c5f202 CW |
4188 | mutex_unlock(&dev->struct_mutex); |
4189 | ||
737b1506 | 4190 | cancel_delayed_work_sync(&dev_priv->gpu_error.hangcheck_work); |
67d97da3 CW |
4191 | cancel_delayed_work_sync(&dev_priv->gt.retire_work); |
4192 | flush_delayed_work(&dev_priv->gt.idle_work); | |
fbbd37b3 | 4193 | flush_work(&dev_priv->mm.free_work); |
29105ccc | 4194 | |
bdcf120b CW |
4195 | /* Assert that we sucessfully flushed all the work and |
4196 | * reset the GPU back to its idle, low power state. | |
4197 | */ | |
67d97da3 | 4198 | WARN_ON(dev_priv->gt.awake); |
31ab49ab | 4199 | WARN_ON(!intel_execlists_idle(dev_priv)); |
bdcf120b | 4200 | |
1c777c5d ID |
4201 | /* |
4202 | * Neither the BIOS, ourselves or any other kernel | |
4203 | * expects the system to be in execlists mode on startup, | |
4204 | * so we need to reset the GPU back to legacy mode. And the only | |
4205 | * known way to disable logical contexts is through a GPU reset. | |
4206 | * | |
4207 | * So in order to leave the system in a known default configuration, | |
4208 | * always reset the GPU upon unload and suspend. Afterwards we then | |
4209 | * clean up the GEM state tracking, flushing off the requests and | |
4210 | * leaving the system in a known idle state. | |
4211 | * | |
4212 | * Note that is of the upmost importance that the GPU is idle and | |
4213 | * all stray writes are flushed *before* we dismantle the backing | |
4214 | * storage for the pinned objects. | |
4215 | * | |
4216 | * However, since we are uncertain that resetting the GPU on older | |
4217 | * machines is a good idea, we don't - just in case it leaves the | |
4218 | * machine in an unusable condition. | |
4219 | */ | |
0031fb96 | 4220 | if (HAS_HW_CONTEXTS(dev_priv)) { |
1c777c5d ID |
4221 | int reset = intel_gpu_reset(dev_priv, ALL_ENGINES); |
4222 | WARN_ON(reset && reset != -ENODEV); | |
4223 | } | |
4224 | ||
673a394b | 4225 | return 0; |
45c5f202 CW |
4226 | |
4227 | err: | |
4228 | mutex_unlock(&dev->struct_mutex); | |
4229 | return ret; | |
673a394b EA |
4230 | } |
4231 | ||
5ab57c70 CW |
4232 | void i915_gem_resume(struct drm_device *dev) |
4233 | { | |
4234 | struct drm_i915_private *dev_priv = to_i915(dev); | |
4235 | ||
31ab49ab ID |
4236 | WARN_ON(dev_priv->gt.awake); |
4237 | ||
5ab57c70 | 4238 | mutex_lock(&dev->struct_mutex); |
275a991c | 4239 | i915_gem_restore_gtt_mappings(dev_priv); |
5ab57c70 CW |
4240 | |
4241 | /* As we didn't flush the kernel context before suspend, we cannot | |
4242 | * guarantee that the context image is complete. So let's just reset | |
4243 | * it and start again. | |
4244 | */ | |
821ed7df | 4245 | dev_priv->gt.resume(dev_priv); |
5ab57c70 CW |
4246 | |
4247 | mutex_unlock(&dev->struct_mutex); | |
4248 | } | |
4249 | ||
c6be607a | 4250 | void i915_gem_init_swizzling(struct drm_i915_private *dev_priv) |
f691e2f4 | 4251 | { |
c6be607a | 4252 | if (INTEL_GEN(dev_priv) < 5 || |
f691e2f4 DV |
4253 | dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE) |
4254 | return; | |
4255 | ||
4256 | I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) | | |
4257 | DISP_TILE_SURFACE_SWIZZLING); | |
4258 | ||
5db94019 | 4259 | if (IS_GEN5(dev_priv)) |
11782b02 DV |
4260 | return; |
4261 | ||
f691e2f4 | 4262 | I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_SWZCTL); |
5db94019 | 4263 | if (IS_GEN6(dev_priv)) |
6b26c86d | 4264 | I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB)); |
5db94019 | 4265 | else if (IS_GEN7(dev_priv)) |
6b26c86d | 4266 | I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB)); |
5db94019 | 4267 | else if (IS_GEN8(dev_priv)) |
31a5336e | 4268 | I915_WRITE(GAMTARBMODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_BDW)); |
8782e26c BW |
4269 | else |
4270 | BUG(); | |
f691e2f4 | 4271 | } |
e21af88d | 4272 | |
50a0bc90 | 4273 | static void init_unused_ring(struct drm_i915_private *dev_priv, u32 base) |
81e7f200 | 4274 | { |
81e7f200 VS |
4275 | I915_WRITE(RING_CTL(base), 0); |
4276 | I915_WRITE(RING_HEAD(base), 0); | |
4277 | I915_WRITE(RING_TAIL(base), 0); | |
4278 | I915_WRITE(RING_START(base), 0); | |
4279 | } | |
4280 | ||
50a0bc90 | 4281 | static void init_unused_rings(struct drm_i915_private *dev_priv) |
81e7f200 | 4282 | { |
50a0bc90 TU |
4283 | if (IS_I830(dev_priv)) { |
4284 | init_unused_ring(dev_priv, PRB1_BASE); | |
4285 | init_unused_ring(dev_priv, SRB0_BASE); | |
4286 | init_unused_ring(dev_priv, SRB1_BASE); | |
4287 | init_unused_ring(dev_priv, SRB2_BASE); | |
4288 | init_unused_ring(dev_priv, SRB3_BASE); | |
4289 | } else if (IS_GEN2(dev_priv)) { | |
4290 | init_unused_ring(dev_priv, SRB0_BASE); | |
4291 | init_unused_ring(dev_priv, SRB1_BASE); | |
4292 | } else if (IS_GEN3(dev_priv)) { | |
4293 | init_unused_ring(dev_priv, PRB1_BASE); | |
4294 | init_unused_ring(dev_priv, PRB2_BASE); | |
81e7f200 VS |
4295 | } |
4296 | } | |
4297 | ||
4fc7c971 BW |
4298 | int |
4299 | i915_gem_init_hw(struct drm_device *dev) | |
4300 | { | |
fac5e23e | 4301 | struct drm_i915_private *dev_priv = to_i915(dev); |
e2f80391 | 4302 | struct intel_engine_cs *engine; |
3b3f1650 | 4303 | enum intel_engine_id id; |
d200cda6 | 4304 | int ret; |
4fc7c971 | 4305 | |
de867c20 CW |
4306 | dev_priv->gt.last_init_time = ktime_get(); |
4307 | ||
5e4f5189 CW |
4308 | /* Double layer security blanket, see i915_gem_init() */ |
4309 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); | |
4310 | ||
0031fb96 | 4311 | if (HAS_EDRAM(dev_priv) && INTEL_GEN(dev_priv) < 9) |
05e21cc4 | 4312 | I915_WRITE(HSW_IDICR, I915_READ(HSW_IDICR) | IDIHASHMSK(0xf)); |
4fc7c971 | 4313 | |
772c2a51 | 4314 | if (IS_HASWELL(dev_priv)) |
50a0bc90 | 4315 | I915_WRITE(MI_PREDICATE_RESULT_2, IS_HSW_GT3(dev_priv) ? |
0bf21347 | 4316 | LOWER_SLICE_ENABLED : LOWER_SLICE_DISABLED); |
9435373e | 4317 | |
6e266956 | 4318 | if (HAS_PCH_NOP(dev_priv)) { |
fd6b8f43 | 4319 | if (IS_IVYBRIDGE(dev_priv)) { |
6ba844b0 DV |
4320 | u32 temp = I915_READ(GEN7_MSG_CTL); |
4321 | temp &= ~(WAIT_FOR_PCH_FLR_ACK | WAIT_FOR_PCH_RESET_ACK); | |
4322 | I915_WRITE(GEN7_MSG_CTL, temp); | |
c6be607a | 4323 | } else if (INTEL_GEN(dev_priv) >= 7) { |
6ba844b0 DV |
4324 | u32 temp = I915_READ(HSW_NDE_RSTWRN_OPT); |
4325 | temp &= ~RESET_PCH_HANDSHAKE_ENABLE; | |
4326 | I915_WRITE(HSW_NDE_RSTWRN_OPT, temp); | |
4327 | } | |
88a2b2a3 BW |
4328 | } |
4329 | ||
c6be607a | 4330 | i915_gem_init_swizzling(dev_priv); |
4fc7c971 | 4331 | |
d5abdfda DV |
4332 | /* |
4333 | * At least 830 can leave some of the unused rings | |
4334 | * "active" (ie. head != tail) after resume which | |
4335 | * will prevent c3 entry. Makes sure all unused rings | |
4336 | * are totally idle. | |
4337 | */ | |
50a0bc90 | 4338 | init_unused_rings(dev_priv); |
d5abdfda | 4339 | |
ed54c1a1 | 4340 | BUG_ON(!dev_priv->kernel_context); |
90638cc1 | 4341 | |
c6be607a | 4342 | ret = i915_ppgtt_init_hw(dev_priv); |
4ad2fd88 JH |
4343 | if (ret) { |
4344 | DRM_ERROR("PPGTT enable HW failed %d\n", ret); | |
4345 | goto out; | |
4346 | } | |
4347 | ||
4348 | /* Need to do basic initialisation of all rings first: */ | |
3b3f1650 | 4349 | for_each_engine(engine, dev_priv, id) { |
e2f80391 | 4350 | ret = engine->init_hw(engine); |
35a57ffb | 4351 | if (ret) |
5e4f5189 | 4352 | goto out; |
35a57ffb | 4353 | } |
99433931 | 4354 | |
0ccdacf6 PA |
4355 | intel_mocs_init_l3cc_table(dev); |
4356 | ||
33a732f4 | 4357 | /* We can't enable contexts until all firmware is loaded */ |
e556f7c1 DG |
4358 | ret = intel_guc_setup(dev); |
4359 | if (ret) | |
4360 | goto out; | |
33a732f4 | 4361 | |
5e4f5189 CW |
4362 | out: |
4363 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); | |
2fa48d8d | 4364 | return ret; |
8187a2b7 ZN |
4365 | } |
4366 | ||
39df9190 CW |
4367 | bool intel_sanitize_semaphores(struct drm_i915_private *dev_priv, int value) |
4368 | { | |
4369 | if (INTEL_INFO(dev_priv)->gen < 6) | |
4370 | return false; | |
4371 | ||
4372 | /* TODO: make semaphores and Execlists play nicely together */ | |
4373 | if (i915.enable_execlists) | |
4374 | return false; | |
4375 | ||
4376 | if (value >= 0) | |
4377 | return value; | |
4378 | ||
4379 | #ifdef CONFIG_INTEL_IOMMU | |
4380 | /* Enable semaphores on SNB when IO remapping is off */ | |
4381 | if (INTEL_INFO(dev_priv)->gen == 6 && intel_iommu_gfx_mapped) | |
4382 | return false; | |
4383 | #endif | |
4384 | ||
4385 | return true; | |
4386 | } | |
4387 | ||
1070a42b CW |
4388 | int i915_gem_init(struct drm_device *dev) |
4389 | { | |
fac5e23e | 4390 | struct drm_i915_private *dev_priv = to_i915(dev); |
1070a42b CW |
4391 | int ret; |
4392 | ||
1070a42b | 4393 | mutex_lock(&dev->struct_mutex); |
d62b4892 | 4394 | |
a83014d3 | 4395 | if (!i915.enable_execlists) { |
821ed7df | 4396 | dev_priv->gt.resume = intel_legacy_submission_resume; |
7e37f889 | 4397 | dev_priv->gt.cleanup_engine = intel_engine_cleanup; |
454afebd | 4398 | } else { |
821ed7df | 4399 | dev_priv->gt.resume = intel_lr_context_resume; |
117897f4 | 4400 | dev_priv->gt.cleanup_engine = intel_logical_ring_cleanup; |
a83014d3 OM |
4401 | } |
4402 | ||
5e4f5189 CW |
4403 | /* This is just a security blanket to placate dragons. |
4404 | * On some systems, we very sporadically observe that the first TLBs | |
4405 | * used by the CS may be stale, despite us poking the TLB reset. If | |
4406 | * we hold the forcewake during initialisation these problems | |
4407 | * just magically go away. | |
4408 | */ | |
4409 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); | |
4410 | ||
72778cb2 | 4411 | i915_gem_init_userptr(dev_priv); |
f6b9d5ca CW |
4412 | |
4413 | ret = i915_gem_init_ggtt(dev_priv); | |
4414 | if (ret) | |
4415 | goto out_unlock; | |
d62b4892 | 4416 | |
2fa48d8d | 4417 | ret = i915_gem_context_init(dev); |
7bcc3777 JN |
4418 | if (ret) |
4419 | goto out_unlock; | |
2fa48d8d | 4420 | |
8b3e2d36 | 4421 | ret = intel_engines_init(dev); |
35a57ffb | 4422 | if (ret) |
7bcc3777 | 4423 | goto out_unlock; |
2fa48d8d | 4424 | |
1070a42b | 4425 | ret = i915_gem_init_hw(dev); |
60990320 | 4426 | if (ret == -EIO) { |
7e21d648 | 4427 | /* Allow engine initialisation to fail by marking the GPU as |
60990320 CW |
4428 | * wedged. But we only want to do this where the GPU is angry, |
4429 | * for all other failure, such as an allocation failure, bail. | |
4430 | */ | |
4431 | DRM_ERROR("Failed to initialize GPU, declaring it wedged\n"); | |
821ed7df | 4432 | i915_gem_set_wedged(dev_priv); |
60990320 | 4433 | ret = 0; |
1070a42b | 4434 | } |
7bcc3777 JN |
4435 | |
4436 | out_unlock: | |
5e4f5189 | 4437 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); |
60990320 | 4438 | mutex_unlock(&dev->struct_mutex); |
1070a42b | 4439 | |
60990320 | 4440 | return ret; |
1070a42b CW |
4441 | } |
4442 | ||
8187a2b7 | 4443 | void |
117897f4 | 4444 | i915_gem_cleanup_engines(struct drm_device *dev) |
8187a2b7 | 4445 | { |
fac5e23e | 4446 | struct drm_i915_private *dev_priv = to_i915(dev); |
e2f80391 | 4447 | struct intel_engine_cs *engine; |
3b3f1650 | 4448 | enum intel_engine_id id; |
8187a2b7 | 4449 | |
3b3f1650 | 4450 | for_each_engine(engine, dev_priv, id) |
117897f4 | 4451 | dev_priv->gt.cleanup_engine(engine); |
8187a2b7 ZN |
4452 | } |
4453 | ||
40ae4e16 ID |
4454 | void |
4455 | i915_gem_load_init_fences(struct drm_i915_private *dev_priv) | |
4456 | { | |
49ef5294 | 4457 | int i; |
40ae4e16 ID |
4458 | |
4459 | if (INTEL_INFO(dev_priv)->gen >= 7 && !IS_VALLEYVIEW(dev_priv) && | |
4460 | !IS_CHERRYVIEW(dev_priv)) | |
4461 | dev_priv->num_fence_regs = 32; | |
4462 | else if (INTEL_INFO(dev_priv)->gen >= 4 || IS_I945G(dev_priv) || | |
4463 | IS_I945GM(dev_priv) || IS_G33(dev_priv)) | |
4464 | dev_priv->num_fence_regs = 16; | |
4465 | else | |
4466 | dev_priv->num_fence_regs = 8; | |
4467 | ||
c033666a | 4468 | if (intel_vgpu_active(dev_priv)) |
40ae4e16 ID |
4469 | dev_priv->num_fence_regs = |
4470 | I915_READ(vgtif_reg(avail_rs.fence_num)); | |
4471 | ||
4472 | /* Initialize fence registers to zero */ | |
49ef5294 CW |
4473 | for (i = 0; i < dev_priv->num_fence_regs; i++) { |
4474 | struct drm_i915_fence_reg *fence = &dev_priv->fence_regs[i]; | |
4475 | ||
4476 | fence->i915 = dev_priv; | |
4477 | fence->id = i; | |
4478 | list_add_tail(&fence->link, &dev_priv->mm.fence_list); | |
4479 | } | |
4362f4f6 | 4480 | i915_gem_restore_fences(dev_priv); |
40ae4e16 | 4481 | |
4362f4f6 | 4482 | i915_gem_detect_bit_6_swizzle(dev_priv); |
40ae4e16 ID |
4483 | } |
4484 | ||
73cb9701 | 4485 | int |
d64aa096 | 4486 | i915_gem_load_init(struct drm_device *dev) |
673a394b | 4487 | { |
fac5e23e | 4488 | struct drm_i915_private *dev_priv = to_i915(dev); |
a933568e | 4489 | int err = -ENOMEM; |
42dcedd4 | 4490 | |
a933568e TU |
4491 | dev_priv->objects = KMEM_CACHE(drm_i915_gem_object, SLAB_HWCACHE_ALIGN); |
4492 | if (!dev_priv->objects) | |
73cb9701 | 4493 | goto err_out; |
73cb9701 | 4494 | |
a933568e TU |
4495 | dev_priv->vmas = KMEM_CACHE(i915_vma, SLAB_HWCACHE_ALIGN); |
4496 | if (!dev_priv->vmas) | |
73cb9701 | 4497 | goto err_objects; |
73cb9701 | 4498 | |
a933568e TU |
4499 | dev_priv->requests = KMEM_CACHE(drm_i915_gem_request, |
4500 | SLAB_HWCACHE_ALIGN | | |
4501 | SLAB_RECLAIM_ACCOUNT | | |
4502 | SLAB_DESTROY_BY_RCU); | |
4503 | if (!dev_priv->requests) | |
73cb9701 | 4504 | goto err_vmas; |
73cb9701 | 4505 | |
52e54209 CW |
4506 | dev_priv->dependencies = KMEM_CACHE(i915_dependency, |
4507 | SLAB_HWCACHE_ALIGN | | |
4508 | SLAB_RECLAIM_ACCOUNT); | |
4509 | if (!dev_priv->dependencies) | |
4510 | goto err_requests; | |
4511 | ||
73cb9701 CW |
4512 | mutex_lock(&dev_priv->drm.struct_mutex); |
4513 | INIT_LIST_HEAD(&dev_priv->gt.timelines); | |
bb89485e | 4514 | err = i915_gem_timeline_init__global(dev_priv); |
73cb9701 CW |
4515 | mutex_unlock(&dev_priv->drm.struct_mutex); |
4516 | if (err) | |
52e54209 | 4517 | goto err_dependencies; |
673a394b | 4518 | |
a33afea5 | 4519 | INIT_LIST_HEAD(&dev_priv->context_list); |
fbbd37b3 CW |
4520 | INIT_WORK(&dev_priv->mm.free_work, __i915_gem_free_work); |
4521 | init_llist_head(&dev_priv->mm.free_list); | |
6c085a72 CW |
4522 | INIT_LIST_HEAD(&dev_priv->mm.unbound_list); |
4523 | INIT_LIST_HEAD(&dev_priv->mm.bound_list); | |
a09ba7fa | 4524 | INIT_LIST_HEAD(&dev_priv->mm.fence_list); |
275f039d | 4525 | INIT_LIST_HEAD(&dev_priv->mm.userfault_list); |
67d97da3 | 4526 | INIT_DELAYED_WORK(&dev_priv->gt.retire_work, |
673a394b | 4527 | i915_gem_retire_work_handler); |
67d97da3 | 4528 | INIT_DELAYED_WORK(&dev_priv->gt.idle_work, |
b29c19b6 | 4529 | i915_gem_idle_work_handler); |
1f15b76f | 4530 | init_waitqueue_head(&dev_priv->gpu_error.wait_queue); |
1f83fee0 | 4531 | init_waitqueue_head(&dev_priv->gpu_error.reset_queue); |
31169714 | 4532 | |
72bfa19c CW |
4533 | dev_priv->relative_constants_mode = I915_EXEC_CONSTANTS_REL_GENERAL; |
4534 | ||
6b95a207 | 4535 | init_waitqueue_head(&dev_priv->pending_flip_queue); |
17250b71 | 4536 | |
ce453d81 CW |
4537 | dev_priv->mm.interruptible = true; |
4538 | ||
6f633402 JL |
4539 | atomic_set(&dev_priv->mm.bsd_engine_dispatch_index, 0); |
4540 | ||
b5add959 | 4541 | spin_lock_init(&dev_priv->fb_tracking.lock); |
73cb9701 CW |
4542 | |
4543 | return 0; | |
4544 | ||
52e54209 CW |
4545 | err_dependencies: |
4546 | kmem_cache_destroy(dev_priv->dependencies); | |
73cb9701 CW |
4547 | err_requests: |
4548 | kmem_cache_destroy(dev_priv->requests); | |
4549 | err_vmas: | |
4550 | kmem_cache_destroy(dev_priv->vmas); | |
4551 | err_objects: | |
4552 | kmem_cache_destroy(dev_priv->objects); | |
4553 | err_out: | |
4554 | return err; | |
673a394b | 4555 | } |
71acb5eb | 4556 | |
d64aa096 ID |
4557 | void i915_gem_load_cleanup(struct drm_device *dev) |
4558 | { | |
4559 | struct drm_i915_private *dev_priv = to_i915(dev); | |
4560 | ||
7d5d59e5 CW |
4561 | WARN_ON(!llist_empty(&dev_priv->mm.free_list)); |
4562 | ||
ea84aa77 MA |
4563 | mutex_lock(&dev_priv->drm.struct_mutex); |
4564 | i915_gem_timeline_fini(&dev_priv->gt.global_timeline); | |
4565 | WARN_ON(!list_empty(&dev_priv->gt.timelines)); | |
4566 | mutex_unlock(&dev_priv->drm.struct_mutex); | |
4567 | ||
52e54209 | 4568 | kmem_cache_destroy(dev_priv->dependencies); |
d64aa096 ID |
4569 | kmem_cache_destroy(dev_priv->requests); |
4570 | kmem_cache_destroy(dev_priv->vmas); | |
4571 | kmem_cache_destroy(dev_priv->objects); | |
0eafec6d CW |
4572 | |
4573 | /* And ensure that our DESTROY_BY_RCU slabs are truly destroyed */ | |
4574 | rcu_barrier(); | |
d64aa096 ID |
4575 | } |
4576 | ||
6a800eab CW |
4577 | int i915_gem_freeze(struct drm_i915_private *dev_priv) |
4578 | { | |
4579 | intel_runtime_pm_get(dev_priv); | |
4580 | ||
4581 | mutex_lock(&dev_priv->drm.struct_mutex); | |
4582 | i915_gem_shrink_all(dev_priv); | |
4583 | mutex_unlock(&dev_priv->drm.struct_mutex); | |
4584 | ||
4585 | intel_runtime_pm_put(dev_priv); | |
4586 | ||
4587 | return 0; | |
4588 | } | |
4589 | ||
461fb99c CW |
4590 | int i915_gem_freeze_late(struct drm_i915_private *dev_priv) |
4591 | { | |
4592 | struct drm_i915_gem_object *obj; | |
7aab2d53 CW |
4593 | struct list_head *phases[] = { |
4594 | &dev_priv->mm.unbound_list, | |
4595 | &dev_priv->mm.bound_list, | |
4596 | NULL | |
4597 | }, **p; | |
461fb99c CW |
4598 | |
4599 | /* Called just before we write the hibernation image. | |
4600 | * | |
4601 | * We need to update the domain tracking to reflect that the CPU | |
4602 | * will be accessing all the pages to create and restore from the | |
4603 | * hibernation, and so upon restoration those pages will be in the | |
4604 | * CPU domain. | |
4605 | * | |
4606 | * To make sure the hibernation image contains the latest state, | |
4607 | * we update that state just before writing out the image. | |
7aab2d53 CW |
4608 | * |
4609 | * To try and reduce the hibernation image, we manually shrink | |
4610 | * the objects as well. | |
461fb99c CW |
4611 | */ |
4612 | ||
6a800eab CW |
4613 | mutex_lock(&dev_priv->drm.struct_mutex); |
4614 | i915_gem_shrink(dev_priv, -1UL, I915_SHRINK_UNBOUND); | |
461fb99c | 4615 | |
7aab2d53 | 4616 | for (p = phases; *p; p++) { |
56cea323 | 4617 | list_for_each_entry(obj, *p, global_link) { |
7aab2d53 CW |
4618 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; |
4619 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; | |
4620 | } | |
461fb99c | 4621 | } |
6a800eab | 4622 | mutex_unlock(&dev_priv->drm.struct_mutex); |
461fb99c CW |
4623 | |
4624 | return 0; | |
4625 | } | |
4626 | ||
f787a5f5 | 4627 | void i915_gem_release(struct drm_device *dev, struct drm_file *file) |
b962442e | 4628 | { |
f787a5f5 | 4629 | struct drm_i915_file_private *file_priv = file->driver_priv; |
15f7bbc7 | 4630 | struct drm_i915_gem_request *request; |
b962442e EA |
4631 | |
4632 | /* Clean up our request list when the client is going away, so that | |
4633 | * later retire_requests won't dereference our soon-to-be-gone | |
4634 | * file_priv. | |
4635 | */ | |
1c25595f | 4636 | spin_lock(&file_priv->mm.lock); |
15f7bbc7 | 4637 | list_for_each_entry(request, &file_priv->mm.request_list, client_list) |
f787a5f5 | 4638 | request->file_priv = NULL; |
1c25595f | 4639 | spin_unlock(&file_priv->mm.lock); |
b29c19b6 | 4640 | |
2e1b8730 | 4641 | if (!list_empty(&file_priv->rps.link)) { |
8d3afd7d | 4642 | spin_lock(&to_i915(dev)->rps.client_lock); |
2e1b8730 | 4643 | list_del(&file_priv->rps.link); |
8d3afd7d | 4644 | spin_unlock(&to_i915(dev)->rps.client_lock); |
1854d5ca | 4645 | } |
b29c19b6 CW |
4646 | } |
4647 | ||
4648 | int i915_gem_open(struct drm_device *dev, struct drm_file *file) | |
4649 | { | |
4650 | struct drm_i915_file_private *file_priv; | |
e422b888 | 4651 | int ret; |
b29c19b6 | 4652 | |
c4c29d7b | 4653 | DRM_DEBUG("\n"); |
b29c19b6 CW |
4654 | |
4655 | file_priv = kzalloc(sizeof(*file_priv), GFP_KERNEL); | |
4656 | if (!file_priv) | |
4657 | return -ENOMEM; | |
4658 | ||
4659 | file->driver_priv = file_priv; | |
f19ec8cb | 4660 | file_priv->dev_priv = to_i915(dev); |
ab0e7ff9 | 4661 | file_priv->file = file; |
2e1b8730 | 4662 | INIT_LIST_HEAD(&file_priv->rps.link); |
b29c19b6 CW |
4663 | |
4664 | spin_lock_init(&file_priv->mm.lock); | |
4665 | INIT_LIST_HEAD(&file_priv->mm.request_list); | |
b29c19b6 | 4666 | |
c80ff16e | 4667 | file_priv->bsd_engine = -1; |
de1add36 | 4668 | |
e422b888 BW |
4669 | ret = i915_gem_context_open(dev, file); |
4670 | if (ret) | |
4671 | kfree(file_priv); | |
b29c19b6 | 4672 | |
e422b888 | 4673 | return ret; |
b29c19b6 CW |
4674 | } |
4675 | ||
b680c37a DV |
4676 | /** |
4677 | * i915_gem_track_fb - update frontbuffer tracking | |
d9072a3e GT |
4678 | * @old: current GEM buffer for the frontbuffer slots |
4679 | * @new: new GEM buffer for the frontbuffer slots | |
4680 | * @frontbuffer_bits: bitmask of frontbuffer slots | |
b680c37a DV |
4681 | * |
4682 | * This updates the frontbuffer tracking bits @frontbuffer_bits by clearing them | |
4683 | * from @old and setting them in @new. Both @old and @new can be NULL. | |
4684 | */ | |
a071fa00 DV |
4685 | void i915_gem_track_fb(struct drm_i915_gem_object *old, |
4686 | struct drm_i915_gem_object *new, | |
4687 | unsigned frontbuffer_bits) | |
4688 | { | |
faf5bf0a CW |
4689 | /* Control of individual bits within the mask are guarded by |
4690 | * the owning plane->mutex, i.e. we can never see concurrent | |
4691 | * manipulation of individual bits. But since the bitfield as a whole | |
4692 | * is updated using RMW, we need to use atomics in order to update | |
4693 | * the bits. | |
4694 | */ | |
4695 | BUILD_BUG_ON(INTEL_FRONTBUFFER_BITS_PER_PIPE * I915_MAX_PIPES > | |
4696 | sizeof(atomic_t) * BITS_PER_BYTE); | |
4697 | ||
a071fa00 | 4698 | if (old) { |
faf5bf0a CW |
4699 | WARN_ON(!(atomic_read(&old->frontbuffer_bits) & frontbuffer_bits)); |
4700 | atomic_andnot(frontbuffer_bits, &old->frontbuffer_bits); | |
a071fa00 DV |
4701 | } |
4702 | ||
4703 | if (new) { | |
faf5bf0a CW |
4704 | WARN_ON(atomic_read(&new->frontbuffer_bits) & frontbuffer_bits); |
4705 | atomic_or(frontbuffer_bits, &new->frontbuffer_bits); | |
a071fa00 DV |
4706 | } |
4707 | } | |
4708 | ||
ea70299d DG |
4709 | /* Allocate a new GEM object and fill it with the supplied data */ |
4710 | struct drm_i915_gem_object * | |
4711 | i915_gem_object_create_from_data(struct drm_device *dev, | |
4712 | const void *data, size_t size) | |
4713 | { | |
4714 | struct drm_i915_gem_object *obj; | |
4715 | struct sg_table *sg; | |
4716 | size_t bytes; | |
4717 | int ret; | |
4718 | ||
d37cd8a8 | 4719 | obj = i915_gem_object_create(dev, round_up(size, PAGE_SIZE)); |
fe3db79b | 4720 | if (IS_ERR(obj)) |
ea70299d DG |
4721 | return obj; |
4722 | ||
4723 | ret = i915_gem_object_set_to_cpu_domain(obj, true); | |
4724 | if (ret) | |
4725 | goto fail; | |
4726 | ||
a4f5ea64 | 4727 | ret = i915_gem_object_pin_pages(obj); |
ea70299d DG |
4728 | if (ret) |
4729 | goto fail; | |
4730 | ||
a4f5ea64 | 4731 | sg = obj->mm.pages; |
ea70299d | 4732 | bytes = sg_copy_from_buffer(sg->sgl, sg->nents, (void *)data, size); |
a4f5ea64 | 4733 | obj->mm.dirty = true; /* Backing store is now out of date */ |
ea70299d DG |
4734 | i915_gem_object_unpin_pages(obj); |
4735 | ||
4736 | if (WARN_ON(bytes != size)) { | |
4737 | DRM_ERROR("Incomplete copy, wrote %zu of %zu", bytes, size); | |
4738 | ret = -EFAULT; | |
4739 | goto fail; | |
4740 | } | |
4741 | ||
4742 | return obj; | |
4743 | ||
4744 | fail: | |
f8c417cd | 4745 | i915_gem_object_put(obj); |
ea70299d DG |
4746 | return ERR_PTR(ret); |
4747 | } | |
96d77634 CW |
4748 | |
4749 | struct scatterlist * | |
4750 | i915_gem_object_get_sg(struct drm_i915_gem_object *obj, | |
4751 | unsigned int n, | |
4752 | unsigned int *offset) | |
4753 | { | |
a4f5ea64 | 4754 | struct i915_gem_object_page_iter *iter = &obj->mm.get_page; |
96d77634 CW |
4755 | struct scatterlist *sg; |
4756 | unsigned int idx, count; | |
4757 | ||
4758 | might_sleep(); | |
4759 | GEM_BUG_ON(n >= obj->base.size >> PAGE_SHIFT); | |
a4f5ea64 | 4760 | GEM_BUG_ON(!i915_gem_object_has_pinned_pages(obj)); |
96d77634 CW |
4761 | |
4762 | /* As we iterate forward through the sg, we record each entry in a | |
4763 | * radixtree for quick repeated (backwards) lookups. If we have seen | |
4764 | * this index previously, we will have an entry for it. | |
4765 | * | |
4766 | * Initial lookup is O(N), but this is amortized to O(1) for | |
4767 | * sequential page access (where each new request is consecutive | |
4768 | * to the previous one). Repeated lookups are O(lg(obj->base.size)), | |
4769 | * i.e. O(1) with a large constant! | |
4770 | */ | |
4771 | if (n < READ_ONCE(iter->sg_idx)) | |
4772 | goto lookup; | |
4773 | ||
4774 | mutex_lock(&iter->lock); | |
4775 | ||
4776 | /* We prefer to reuse the last sg so that repeated lookup of this | |
4777 | * (or the subsequent) sg are fast - comparing against the last | |
4778 | * sg is faster than going through the radixtree. | |
4779 | */ | |
4780 | ||
4781 | sg = iter->sg_pos; | |
4782 | idx = iter->sg_idx; | |
4783 | count = __sg_page_count(sg); | |
4784 | ||
4785 | while (idx + count <= n) { | |
4786 | unsigned long exception, i; | |
4787 | int ret; | |
4788 | ||
4789 | /* If we cannot allocate and insert this entry, or the | |
4790 | * individual pages from this range, cancel updating the | |
4791 | * sg_idx so that on this lookup we are forced to linearly | |
4792 | * scan onwards, but on future lookups we will try the | |
4793 | * insertion again (in which case we need to be careful of | |
4794 | * the error return reporting that we have already inserted | |
4795 | * this index). | |
4796 | */ | |
4797 | ret = radix_tree_insert(&iter->radix, idx, sg); | |
4798 | if (ret && ret != -EEXIST) | |
4799 | goto scan; | |
4800 | ||
4801 | exception = | |
4802 | RADIX_TREE_EXCEPTIONAL_ENTRY | | |
4803 | idx << RADIX_TREE_EXCEPTIONAL_SHIFT; | |
4804 | for (i = 1; i < count; i++) { | |
4805 | ret = radix_tree_insert(&iter->radix, idx + i, | |
4806 | (void *)exception); | |
4807 | if (ret && ret != -EEXIST) | |
4808 | goto scan; | |
4809 | } | |
4810 | ||
4811 | idx += count; | |
4812 | sg = ____sg_next(sg); | |
4813 | count = __sg_page_count(sg); | |
4814 | } | |
4815 | ||
4816 | scan: | |
4817 | iter->sg_pos = sg; | |
4818 | iter->sg_idx = idx; | |
4819 | ||
4820 | mutex_unlock(&iter->lock); | |
4821 | ||
4822 | if (unlikely(n < idx)) /* insertion completed by another thread */ | |
4823 | goto lookup; | |
4824 | ||
4825 | /* In case we failed to insert the entry into the radixtree, we need | |
4826 | * to look beyond the current sg. | |
4827 | */ | |
4828 | while (idx + count <= n) { | |
4829 | idx += count; | |
4830 | sg = ____sg_next(sg); | |
4831 | count = __sg_page_count(sg); | |
4832 | } | |
4833 | ||
4834 | *offset = n - idx; | |
4835 | return sg; | |
4836 | ||
4837 | lookup: | |
4838 | rcu_read_lock(); | |
4839 | ||
4840 | sg = radix_tree_lookup(&iter->radix, n); | |
4841 | GEM_BUG_ON(!sg); | |
4842 | ||
4843 | /* If this index is in the middle of multi-page sg entry, | |
4844 | * the radixtree will contain an exceptional entry that points | |
4845 | * to the start of that range. We will return the pointer to | |
4846 | * the base page and the offset of this page within the | |
4847 | * sg entry's range. | |
4848 | */ | |
4849 | *offset = 0; | |
4850 | if (unlikely(radix_tree_exception(sg))) { | |
4851 | unsigned long base = | |
4852 | (unsigned long)sg >> RADIX_TREE_EXCEPTIONAL_SHIFT; | |
4853 | ||
4854 | sg = radix_tree_lookup(&iter->radix, base); | |
4855 | GEM_BUG_ON(!sg); | |
4856 | ||
4857 | *offset = n - base; | |
4858 | } | |
4859 | ||
4860 | rcu_read_unlock(); | |
4861 | ||
4862 | return sg; | |
4863 | } | |
4864 | ||
4865 | struct page * | |
4866 | i915_gem_object_get_page(struct drm_i915_gem_object *obj, unsigned int n) | |
4867 | { | |
4868 | struct scatterlist *sg; | |
4869 | unsigned int offset; | |
4870 | ||
4871 | GEM_BUG_ON(!i915_gem_object_has_struct_page(obj)); | |
4872 | ||
4873 | sg = i915_gem_object_get_sg(obj, n, &offset); | |
4874 | return nth_page(sg_page(sg), offset); | |
4875 | } | |
4876 | ||
4877 | /* Like i915_gem_object_get_page(), but mark the returned page dirty */ | |
4878 | struct page * | |
4879 | i915_gem_object_get_dirty_page(struct drm_i915_gem_object *obj, | |
4880 | unsigned int n) | |
4881 | { | |
4882 | struct page *page; | |
4883 | ||
4884 | page = i915_gem_object_get_page(obj, n); | |
a4f5ea64 | 4885 | if (!obj->mm.dirty) |
96d77634 CW |
4886 | set_page_dirty(page); |
4887 | ||
4888 | return page; | |
4889 | } | |
4890 | ||
4891 | dma_addr_t | |
4892 | i915_gem_object_get_dma_address(struct drm_i915_gem_object *obj, | |
4893 | unsigned long n) | |
4894 | { | |
4895 | struct scatterlist *sg; | |
4896 | unsigned int offset; | |
4897 | ||
4898 | sg = i915_gem_object_get_sg(obj, n, &offset); | |
4899 | return sg_dma_address(sg) + (offset << PAGE_SHIFT); | |
4900 | } |