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673a394b EA |
1 | /* |
2 | * Copyright © 2008 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | * | |
26 | */ | |
27 | ||
28 | #include "drmP.h" | |
29 | #include "drm.h" | |
30 | #include "i915_drm.h" | |
31 | #include "i915_drv.h" | |
1c5d22f7 | 32 | #include "i915_trace.h" |
652c393a | 33 | #include "intel_drv.h" |
5a0e3ad6 | 34 | #include <linux/slab.h> |
673a394b | 35 | #include <linux/swap.h> |
79e53945 | 36 | #include <linux/pci.h> |
f8f235e5 | 37 | #include <linux/intel-gtt.h> |
673a394b | 38 | |
0f8c6d7c CW |
39 | struct change_domains { |
40 | uint32_t invalidate_domains; | |
41 | uint32_t flush_domains; | |
42 | uint32_t flush_rings; | |
43 | }; | |
44 | ||
a00b10c3 CW |
45 | static uint32_t i915_gem_get_gtt_alignment(struct drm_i915_gem_object *obj_priv); |
46 | static uint32_t i915_gem_get_gtt_size(struct drm_i915_gem_object *obj_priv); | |
ba3d8d74 DV |
47 | |
48 | static int i915_gem_object_flush_gpu_write_domain(struct drm_gem_object *obj, | |
49 | bool pipelined); | |
e47c68e9 EA |
50 | static void i915_gem_object_flush_gtt_write_domain(struct drm_gem_object *obj); |
51 | static void i915_gem_object_flush_cpu_write_domain(struct drm_gem_object *obj); | |
e47c68e9 EA |
52 | static int i915_gem_object_set_to_cpu_domain(struct drm_gem_object *obj, |
53 | int write); | |
54 | static int i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object *obj, | |
55 | uint64_t offset, | |
56 | uint64_t size); | |
57 | static void i915_gem_object_set_to_full_cpu_read_domain(struct drm_gem_object *obj); | |
2cf34d7b CW |
58 | static int i915_gem_object_wait_rendering(struct drm_gem_object *obj, |
59 | bool interruptible); | |
de151cf6 | 60 | static int i915_gem_object_bind_to_gtt(struct drm_gem_object *obj, |
a00b10c3 | 61 | unsigned alignment, |
75e9e915 | 62 | bool map_and_fenceable); |
de151cf6 | 63 | static void i915_gem_clear_fence_reg(struct drm_gem_object *obj); |
71acb5eb DA |
64 | static int i915_gem_phys_pwrite(struct drm_device *dev, struct drm_gem_object *obj, |
65 | struct drm_i915_gem_pwrite *args, | |
66 | struct drm_file *file_priv); | |
be72615b | 67 | static void i915_gem_free_object_tail(struct drm_gem_object *obj); |
673a394b | 68 | |
17250b71 CW |
69 | static int i915_gem_inactive_shrink(struct shrinker *shrinker, |
70 | int nr_to_scan, | |
71 | gfp_t gfp_mask); | |
72 | ||
31169714 | 73 | |
73aa808f CW |
74 | /* some bookkeeping */ |
75 | static void i915_gem_info_add_obj(struct drm_i915_private *dev_priv, | |
76 | size_t size) | |
77 | { | |
78 | dev_priv->mm.object_count++; | |
79 | dev_priv->mm.object_memory += size; | |
80 | } | |
81 | ||
82 | static void i915_gem_info_remove_obj(struct drm_i915_private *dev_priv, | |
83 | size_t size) | |
84 | { | |
85 | dev_priv->mm.object_count--; | |
86 | dev_priv->mm.object_memory -= size; | |
87 | } | |
88 | ||
89 | static void i915_gem_info_add_gtt(struct drm_i915_private *dev_priv, | |
a00b10c3 | 90 | struct drm_i915_gem_object *obj) |
73aa808f CW |
91 | { |
92 | dev_priv->mm.gtt_count++; | |
a00b10c3 CW |
93 | dev_priv->mm.gtt_memory += obj->gtt_space->size; |
94 | if (obj->gtt_offset < dev_priv->mm.gtt_mappable_end) { | |
fb7d516a | 95 | dev_priv->mm.mappable_gtt_used += |
a00b10c3 CW |
96 | min_t(size_t, obj->gtt_space->size, |
97 | dev_priv->mm.gtt_mappable_end - obj->gtt_offset); | |
fb7d516a | 98 | } |
73aa808f CW |
99 | } |
100 | ||
101 | static void i915_gem_info_remove_gtt(struct drm_i915_private *dev_priv, | |
a00b10c3 | 102 | struct drm_i915_gem_object *obj) |
73aa808f CW |
103 | { |
104 | dev_priv->mm.gtt_count--; | |
a00b10c3 CW |
105 | dev_priv->mm.gtt_memory -= obj->gtt_space->size; |
106 | if (obj->gtt_offset < dev_priv->mm.gtt_mappable_end) { | |
fb7d516a | 107 | dev_priv->mm.mappable_gtt_used -= |
a00b10c3 CW |
108 | min_t(size_t, obj->gtt_space->size, |
109 | dev_priv->mm.gtt_mappable_end - obj->gtt_offset); | |
fb7d516a DV |
110 | } |
111 | } | |
112 | ||
113 | /** | |
114 | * Update the mappable working set counters. Call _only_ when there is a change | |
115 | * in one of (pin|fault)_mappable and update *_mappable _before_ calling. | |
116 | * @mappable: new state the changed mappable flag (either pin_ or fault_). | |
117 | */ | |
118 | static void | |
119 | i915_gem_info_update_mappable(struct drm_i915_private *dev_priv, | |
a00b10c3 | 120 | struct drm_i915_gem_object *obj, |
fb7d516a DV |
121 | bool mappable) |
122 | { | |
fb7d516a | 123 | if (mappable) { |
a00b10c3 | 124 | if (obj->pin_mappable && obj->fault_mappable) |
fb7d516a DV |
125 | /* Combined state was already mappable. */ |
126 | return; | |
127 | dev_priv->mm.gtt_mappable_count++; | |
a00b10c3 | 128 | dev_priv->mm.gtt_mappable_memory += obj->gtt_space->size; |
fb7d516a | 129 | } else { |
a00b10c3 | 130 | if (obj->pin_mappable || obj->fault_mappable) |
fb7d516a DV |
131 | /* Combined state still mappable. */ |
132 | return; | |
133 | dev_priv->mm.gtt_mappable_count--; | |
a00b10c3 | 134 | dev_priv->mm.gtt_mappable_memory -= obj->gtt_space->size; |
fb7d516a | 135 | } |
73aa808f CW |
136 | } |
137 | ||
138 | static void i915_gem_info_add_pin(struct drm_i915_private *dev_priv, | |
a00b10c3 | 139 | struct drm_i915_gem_object *obj, |
fb7d516a | 140 | bool mappable) |
73aa808f CW |
141 | { |
142 | dev_priv->mm.pin_count++; | |
a00b10c3 | 143 | dev_priv->mm.pin_memory += obj->gtt_space->size; |
fb7d516a | 144 | if (mappable) { |
a00b10c3 | 145 | obj->pin_mappable = true; |
fb7d516a DV |
146 | i915_gem_info_update_mappable(dev_priv, obj, true); |
147 | } | |
73aa808f CW |
148 | } |
149 | ||
150 | static void i915_gem_info_remove_pin(struct drm_i915_private *dev_priv, | |
a00b10c3 | 151 | struct drm_i915_gem_object *obj) |
73aa808f CW |
152 | { |
153 | dev_priv->mm.pin_count--; | |
a00b10c3 CW |
154 | dev_priv->mm.pin_memory -= obj->gtt_space->size; |
155 | if (obj->pin_mappable) { | |
156 | obj->pin_mappable = false; | |
fb7d516a DV |
157 | i915_gem_info_update_mappable(dev_priv, obj, false); |
158 | } | |
73aa808f CW |
159 | } |
160 | ||
30dbf0c0 CW |
161 | int |
162 | i915_gem_check_is_wedged(struct drm_device *dev) | |
163 | { | |
164 | struct drm_i915_private *dev_priv = dev->dev_private; | |
165 | struct completion *x = &dev_priv->error_completion; | |
166 | unsigned long flags; | |
167 | int ret; | |
168 | ||
169 | if (!atomic_read(&dev_priv->mm.wedged)) | |
170 | return 0; | |
171 | ||
172 | ret = wait_for_completion_interruptible(x); | |
173 | if (ret) | |
174 | return ret; | |
175 | ||
176 | /* Success, we reset the GPU! */ | |
177 | if (!atomic_read(&dev_priv->mm.wedged)) | |
178 | return 0; | |
179 | ||
180 | /* GPU is hung, bump the completion count to account for | |
181 | * the token we just consumed so that we never hit zero and | |
182 | * end up waiting upon a subsequent completion event that | |
183 | * will never happen. | |
184 | */ | |
185 | spin_lock_irqsave(&x->wait.lock, flags); | |
186 | x->done++; | |
187 | spin_unlock_irqrestore(&x->wait.lock, flags); | |
188 | return -EIO; | |
189 | } | |
190 | ||
76c1dec1 CW |
191 | static int i915_mutex_lock_interruptible(struct drm_device *dev) |
192 | { | |
193 | struct drm_i915_private *dev_priv = dev->dev_private; | |
194 | int ret; | |
195 | ||
196 | ret = i915_gem_check_is_wedged(dev); | |
197 | if (ret) | |
198 | return ret; | |
199 | ||
200 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
201 | if (ret) | |
202 | return ret; | |
203 | ||
204 | if (atomic_read(&dev_priv->mm.wedged)) { | |
205 | mutex_unlock(&dev->struct_mutex); | |
206 | return -EAGAIN; | |
207 | } | |
208 | ||
23bc5982 | 209 | WARN_ON(i915_verify_lists(dev)); |
76c1dec1 CW |
210 | return 0; |
211 | } | |
30dbf0c0 | 212 | |
7d1c4804 CW |
213 | static inline bool |
214 | i915_gem_object_is_inactive(struct drm_i915_gem_object *obj_priv) | |
215 | { | |
216 | return obj_priv->gtt_space && | |
217 | !obj_priv->active && | |
218 | obj_priv->pin_count == 0; | |
219 | } | |
220 | ||
73aa808f CW |
221 | int i915_gem_do_init(struct drm_device *dev, |
222 | unsigned long start, | |
53984635 | 223 | unsigned long mappable_end, |
79e53945 | 224 | unsigned long end) |
673a394b EA |
225 | { |
226 | drm_i915_private_t *dev_priv = dev->dev_private; | |
673a394b | 227 | |
79e53945 JB |
228 | if (start >= end || |
229 | (start & (PAGE_SIZE - 1)) != 0 || | |
230 | (end & (PAGE_SIZE - 1)) != 0) { | |
673a394b EA |
231 | return -EINVAL; |
232 | } | |
233 | ||
79e53945 JB |
234 | drm_mm_init(&dev_priv->mm.gtt_space, start, |
235 | end - start); | |
673a394b | 236 | |
73aa808f | 237 | dev_priv->mm.gtt_total = end - start; |
fb7d516a | 238 | dev_priv->mm.mappable_gtt_total = min(end, mappable_end) - start; |
53984635 | 239 | dev_priv->mm.gtt_mappable_end = mappable_end; |
79e53945 JB |
240 | |
241 | return 0; | |
242 | } | |
673a394b | 243 | |
79e53945 JB |
244 | int |
245 | i915_gem_init_ioctl(struct drm_device *dev, void *data, | |
246 | struct drm_file *file_priv) | |
247 | { | |
248 | struct drm_i915_gem_init *args = data; | |
249 | int ret; | |
250 | ||
251 | mutex_lock(&dev->struct_mutex); | |
53984635 | 252 | ret = i915_gem_do_init(dev, args->gtt_start, args->gtt_end, args->gtt_end); |
673a394b EA |
253 | mutex_unlock(&dev->struct_mutex); |
254 | ||
79e53945 | 255 | return ret; |
673a394b EA |
256 | } |
257 | ||
5a125c3c EA |
258 | int |
259 | i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data, | |
260 | struct drm_file *file_priv) | |
261 | { | |
73aa808f | 262 | struct drm_i915_private *dev_priv = dev->dev_private; |
5a125c3c | 263 | struct drm_i915_gem_get_aperture *args = data; |
5a125c3c EA |
264 | |
265 | if (!(dev->driver->driver_features & DRIVER_GEM)) | |
266 | return -ENODEV; | |
267 | ||
73aa808f CW |
268 | mutex_lock(&dev->struct_mutex); |
269 | args->aper_size = dev_priv->mm.gtt_total; | |
270 | args->aper_available_size = args->aper_size - dev_priv->mm.pin_memory; | |
271 | mutex_unlock(&dev->struct_mutex); | |
5a125c3c EA |
272 | |
273 | return 0; | |
274 | } | |
275 | ||
673a394b EA |
276 | |
277 | /** | |
278 | * Creates a new mm object and returns a handle to it. | |
279 | */ | |
280 | int | |
281 | i915_gem_create_ioctl(struct drm_device *dev, void *data, | |
282 | struct drm_file *file_priv) | |
283 | { | |
284 | struct drm_i915_gem_create *args = data; | |
285 | struct drm_gem_object *obj; | |
a1a2d1d3 PP |
286 | int ret; |
287 | u32 handle; | |
673a394b EA |
288 | |
289 | args->size = roundup(args->size, PAGE_SIZE); | |
290 | ||
291 | /* Allocate the new object */ | |
ac52bc56 | 292 | obj = i915_gem_alloc_object(dev, args->size); |
673a394b EA |
293 | if (obj == NULL) |
294 | return -ENOMEM; | |
295 | ||
296 | ret = drm_gem_handle_create(file_priv, obj, &handle); | |
1dfd9754 | 297 | if (ret) { |
202f2fef CW |
298 | drm_gem_object_release(obj); |
299 | i915_gem_info_remove_obj(dev->dev_private, obj->size); | |
300 | kfree(obj); | |
673a394b | 301 | return ret; |
1dfd9754 | 302 | } |
673a394b | 303 | |
202f2fef CW |
304 | /* drop reference from allocate - handle holds it now */ |
305 | drm_gem_object_unreference(obj); | |
306 | trace_i915_gem_object_create(obj); | |
307 | ||
1dfd9754 | 308 | args->handle = handle; |
673a394b EA |
309 | return 0; |
310 | } | |
311 | ||
280b713b EA |
312 | static int i915_gem_object_needs_bit17_swizzle(struct drm_gem_object *obj) |
313 | { | |
314 | drm_i915_private_t *dev_priv = obj->dev->dev_private; | |
23010e43 | 315 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
280b713b EA |
316 | |
317 | return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 && | |
318 | obj_priv->tiling_mode != I915_TILING_NONE; | |
319 | } | |
320 | ||
99a03df5 | 321 | static inline void |
40123c1f EA |
322 | slow_shmem_copy(struct page *dst_page, |
323 | int dst_offset, | |
324 | struct page *src_page, | |
325 | int src_offset, | |
326 | int length) | |
327 | { | |
328 | char *dst_vaddr, *src_vaddr; | |
329 | ||
99a03df5 CW |
330 | dst_vaddr = kmap(dst_page); |
331 | src_vaddr = kmap(src_page); | |
40123c1f EA |
332 | |
333 | memcpy(dst_vaddr + dst_offset, src_vaddr + src_offset, length); | |
334 | ||
99a03df5 CW |
335 | kunmap(src_page); |
336 | kunmap(dst_page); | |
40123c1f EA |
337 | } |
338 | ||
99a03df5 | 339 | static inline void |
280b713b EA |
340 | slow_shmem_bit17_copy(struct page *gpu_page, |
341 | int gpu_offset, | |
342 | struct page *cpu_page, | |
343 | int cpu_offset, | |
344 | int length, | |
345 | int is_read) | |
346 | { | |
347 | char *gpu_vaddr, *cpu_vaddr; | |
348 | ||
349 | /* Use the unswizzled path if this page isn't affected. */ | |
350 | if ((page_to_phys(gpu_page) & (1 << 17)) == 0) { | |
351 | if (is_read) | |
352 | return slow_shmem_copy(cpu_page, cpu_offset, | |
353 | gpu_page, gpu_offset, length); | |
354 | else | |
355 | return slow_shmem_copy(gpu_page, gpu_offset, | |
356 | cpu_page, cpu_offset, length); | |
357 | } | |
358 | ||
99a03df5 CW |
359 | gpu_vaddr = kmap(gpu_page); |
360 | cpu_vaddr = kmap(cpu_page); | |
280b713b EA |
361 | |
362 | /* Copy the data, XORing A6 with A17 (1). The user already knows he's | |
363 | * XORing with the other bits (A9 for Y, A9 and A10 for X) | |
364 | */ | |
365 | while (length > 0) { | |
366 | int cacheline_end = ALIGN(gpu_offset + 1, 64); | |
367 | int this_length = min(cacheline_end - gpu_offset, length); | |
368 | int swizzled_gpu_offset = gpu_offset ^ 64; | |
369 | ||
370 | if (is_read) { | |
371 | memcpy(cpu_vaddr + cpu_offset, | |
372 | gpu_vaddr + swizzled_gpu_offset, | |
373 | this_length); | |
374 | } else { | |
375 | memcpy(gpu_vaddr + swizzled_gpu_offset, | |
376 | cpu_vaddr + cpu_offset, | |
377 | this_length); | |
378 | } | |
379 | cpu_offset += this_length; | |
380 | gpu_offset += this_length; | |
381 | length -= this_length; | |
382 | } | |
383 | ||
99a03df5 CW |
384 | kunmap(cpu_page); |
385 | kunmap(gpu_page); | |
280b713b EA |
386 | } |
387 | ||
eb01459f EA |
388 | /** |
389 | * This is the fast shmem pread path, which attempts to copy_from_user directly | |
390 | * from the backing pages of the object to the user's address space. On a | |
391 | * fault, it fails so we can fall back to i915_gem_shmem_pwrite_slow(). | |
392 | */ | |
393 | static int | |
394 | i915_gem_shmem_pread_fast(struct drm_device *dev, struct drm_gem_object *obj, | |
395 | struct drm_i915_gem_pread *args, | |
396 | struct drm_file *file_priv) | |
397 | { | |
23010e43 | 398 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
e5281ccd | 399 | struct address_space *mapping = obj->filp->f_path.dentry->d_inode->i_mapping; |
eb01459f | 400 | ssize_t remain; |
e5281ccd | 401 | loff_t offset; |
eb01459f EA |
402 | char __user *user_data; |
403 | int page_offset, page_length; | |
eb01459f EA |
404 | |
405 | user_data = (char __user *) (uintptr_t) args->data_ptr; | |
406 | remain = args->size; | |
407 | ||
23010e43 | 408 | obj_priv = to_intel_bo(obj); |
eb01459f EA |
409 | offset = args->offset; |
410 | ||
411 | while (remain > 0) { | |
e5281ccd CW |
412 | struct page *page; |
413 | char *vaddr; | |
414 | int ret; | |
415 | ||
eb01459f EA |
416 | /* Operation in this page |
417 | * | |
eb01459f EA |
418 | * page_offset = offset within page |
419 | * page_length = bytes to copy for this page | |
420 | */ | |
eb01459f EA |
421 | page_offset = offset & (PAGE_SIZE-1); |
422 | page_length = remain; | |
423 | if ((page_offset + remain) > PAGE_SIZE) | |
424 | page_length = PAGE_SIZE - page_offset; | |
425 | ||
e5281ccd CW |
426 | page = read_cache_page_gfp(mapping, offset >> PAGE_SHIFT, |
427 | GFP_HIGHUSER | __GFP_RECLAIMABLE); | |
428 | if (IS_ERR(page)) | |
429 | return PTR_ERR(page); | |
430 | ||
431 | vaddr = kmap_atomic(page); | |
432 | ret = __copy_to_user_inatomic(user_data, | |
433 | vaddr + page_offset, | |
434 | page_length); | |
435 | kunmap_atomic(vaddr); | |
436 | ||
437 | mark_page_accessed(page); | |
438 | page_cache_release(page); | |
439 | if (ret) | |
4f27b75d | 440 | return -EFAULT; |
eb01459f EA |
441 | |
442 | remain -= page_length; | |
443 | user_data += page_length; | |
444 | offset += page_length; | |
445 | } | |
446 | ||
4f27b75d | 447 | return 0; |
eb01459f EA |
448 | } |
449 | ||
450 | /** | |
451 | * This is the fallback shmem pread path, which allocates temporary storage | |
452 | * in kernel space to copy_to_user into outside of the struct_mutex, so we | |
453 | * can copy out of the object's backing pages while holding the struct mutex | |
454 | * and not take page faults. | |
455 | */ | |
456 | static int | |
457 | i915_gem_shmem_pread_slow(struct drm_device *dev, struct drm_gem_object *obj, | |
458 | struct drm_i915_gem_pread *args, | |
459 | struct drm_file *file_priv) | |
460 | { | |
e5281ccd | 461 | struct address_space *mapping = obj->filp->f_path.dentry->d_inode->i_mapping; |
23010e43 | 462 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
eb01459f EA |
463 | struct mm_struct *mm = current->mm; |
464 | struct page **user_pages; | |
465 | ssize_t remain; | |
466 | loff_t offset, pinned_pages, i; | |
467 | loff_t first_data_page, last_data_page, num_pages; | |
e5281ccd CW |
468 | int shmem_page_offset; |
469 | int data_page_index, data_page_offset; | |
eb01459f EA |
470 | int page_length; |
471 | int ret; | |
472 | uint64_t data_ptr = args->data_ptr; | |
280b713b | 473 | int do_bit17_swizzling; |
eb01459f EA |
474 | |
475 | remain = args->size; | |
476 | ||
477 | /* Pin the user pages containing the data. We can't fault while | |
478 | * holding the struct mutex, yet we want to hold it while | |
479 | * dereferencing the user data. | |
480 | */ | |
481 | first_data_page = data_ptr / PAGE_SIZE; | |
482 | last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE; | |
483 | num_pages = last_data_page - first_data_page + 1; | |
484 | ||
4f27b75d | 485 | user_pages = drm_malloc_ab(num_pages, sizeof(struct page *)); |
eb01459f EA |
486 | if (user_pages == NULL) |
487 | return -ENOMEM; | |
488 | ||
4f27b75d | 489 | mutex_unlock(&dev->struct_mutex); |
eb01459f EA |
490 | down_read(&mm->mmap_sem); |
491 | pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr, | |
e5e9ecde | 492 | num_pages, 1, 0, user_pages, NULL); |
eb01459f | 493 | up_read(&mm->mmap_sem); |
4f27b75d | 494 | mutex_lock(&dev->struct_mutex); |
eb01459f EA |
495 | if (pinned_pages < num_pages) { |
496 | ret = -EFAULT; | |
4f27b75d | 497 | goto out; |
eb01459f EA |
498 | } |
499 | ||
4f27b75d CW |
500 | ret = i915_gem_object_set_cpu_read_domain_range(obj, |
501 | args->offset, | |
502 | args->size); | |
07f73f69 | 503 | if (ret) |
4f27b75d | 504 | goto out; |
eb01459f | 505 | |
4f27b75d | 506 | do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj); |
eb01459f | 507 | |
23010e43 | 508 | obj_priv = to_intel_bo(obj); |
eb01459f EA |
509 | offset = args->offset; |
510 | ||
511 | while (remain > 0) { | |
e5281ccd CW |
512 | struct page *page; |
513 | ||
eb01459f EA |
514 | /* Operation in this page |
515 | * | |
eb01459f EA |
516 | * shmem_page_offset = offset within page in shmem file |
517 | * data_page_index = page number in get_user_pages return | |
518 | * data_page_offset = offset with data_page_index page. | |
519 | * page_length = bytes to copy for this page | |
520 | */ | |
eb01459f EA |
521 | shmem_page_offset = offset & ~PAGE_MASK; |
522 | data_page_index = data_ptr / PAGE_SIZE - first_data_page; | |
523 | data_page_offset = data_ptr & ~PAGE_MASK; | |
524 | ||
525 | page_length = remain; | |
526 | if ((shmem_page_offset + page_length) > PAGE_SIZE) | |
527 | page_length = PAGE_SIZE - shmem_page_offset; | |
528 | if ((data_page_offset + page_length) > PAGE_SIZE) | |
529 | page_length = PAGE_SIZE - data_page_offset; | |
530 | ||
e5281ccd CW |
531 | page = read_cache_page_gfp(mapping, offset >> PAGE_SHIFT, |
532 | GFP_HIGHUSER | __GFP_RECLAIMABLE); | |
533 | if (IS_ERR(page)) | |
534 | return PTR_ERR(page); | |
535 | ||
280b713b | 536 | if (do_bit17_swizzling) { |
e5281ccd | 537 | slow_shmem_bit17_copy(page, |
280b713b | 538 | shmem_page_offset, |
99a03df5 CW |
539 | user_pages[data_page_index], |
540 | data_page_offset, | |
541 | page_length, | |
542 | 1); | |
543 | } else { | |
544 | slow_shmem_copy(user_pages[data_page_index], | |
545 | data_page_offset, | |
e5281ccd | 546 | page, |
99a03df5 CW |
547 | shmem_page_offset, |
548 | page_length); | |
280b713b | 549 | } |
eb01459f | 550 | |
e5281ccd CW |
551 | mark_page_accessed(page); |
552 | page_cache_release(page); | |
553 | ||
eb01459f EA |
554 | remain -= page_length; |
555 | data_ptr += page_length; | |
556 | offset += page_length; | |
557 | } | |
558 | ||
4f27b75d | 559 | out: |
eb01459f EA |
560 | for (i = 0; i < pinned_pages; i++) { |
561 | SetPageDirty(user_pages[i]); | |
e5281ccd | 562 | mark_page_accessed(user_pages[i]); |
eb01459f EA |
563 | page_cache_release(user_pages[i]); |
564 | } | |
8e7d2b2c | 565 | drm_free_large(user_pages); |
eb01459f EA |
566 | |
567 | return ret; | |
568 | } | |
569 | ||
673a394b EA |
570 | /** |
571 | * Reads data from the object referenced by handle. | |
572 | * | |
573 | * On error, the contents of *data are undefined. | |
574 | */ | |
575 | int | |
576 | i915_gem_pread_ioctl(struct drm_device *dev, void *data, | |
577 | struct drm_file *file_priv) | |
578 | { | |
579 | struct drm_i915_gem_pread *args = data; | |
580 | struct drm_gem_object *obj; | |
581 | struct drm_i915_gem_object *obj_priv; | |
35b62a89 | 582 | int ret = 0; |
673a394b | 583 | |
4f27b75d | 584 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 585 | if (ret) |
4f27b75d | 586 | return ret; |
673a394b EA |
587 | |
588 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); | |
1d7cfea1 CW |
589 | if (obj == NULL) { |
590 | ret = -ENOENT; | |
591 | goto unlock; | |
4f27b75d | 592 | } |
23010e43 | 593 | obj_priv = to_intel_bo(obj); |
673a394b | 594 | |
7dcd2499 CW |
595 | /* Bounds check source. */ |
596 | if (args->offset > obj->size || args->size > obj->size - args->offset) { | |
ce9d419d | 597 | ret = -EINVAL; |
35b62a89 | 598 | goto out; |
ce9d419d CW |
599 | } |
600 | ||
35b62a89 CW |
601 | if (args->size == 0) |
602 | goto out; | |
603 | ||
ce9d419d CW |
604 | if (!access_ok(VERIFY_WRITE, |
605 | (char __user *)(uintptr_t)args->data_ptr, | |
606 | args->size)) { | |
607 | ret = -EFAULT; | |
35b62a89 | 608 | goto out; |
673a394b EA |
609 | } |
610 | ||
b5e4feb6 CW |
611 | ret = fault_in_pages_writeable((char __user *)(uintptr_t)args->data_ptr, |
612 | args->size); | |
613 | if (ret) { | |
614 | ret = -EFAULT; | |
615 | goto out; | |
280b713b | 616 | } |
673a394b | 617 | |
4f27b75d CW |
618 | ret = i915_gem_object_set_cpu_read_domain_range(obj, |
619 | args->offset, | |
620 | args->size); | |
621 | if (ret) | |
e5281ccd | 622 | goto out; |
4f27b75d CW |
623 | |
624 | ret = -EFAULT; | |
625 | if (!i915_gem_object_needs_bit17_swizzle(obj)) | |
280b713b | 626 | ret = i915_gem_shmem_pread_fast(dev, obj, args, file_priv); |
4f27b75d CW |
627 | if (ret == -EFAULT) |
628 | ret = i915_gem_shmem_pread_slow(dev, obj, args, file_priv); | |
673a394b | 629 | |
35b62a89 | 630 | out: |
4f27b75d | 631 | drm_gem_object_unreference(obj); |
1d7cfea1 | 632 | unlock: |
4f27b75d | 633 | mutex_unlock(&dev->struct_mutex); |
eb01459f | 634 | return ret; |
673a394b EA |
635 | } |
636 | ||
0839ccb8 KP |
637 | /* This is the fast write path which cannot handle |
638 | * page faults in the source data | |
9b7530cc | 639 | */ |
0839ccb8 KP |
640 | |
641 | static inline int | |
642 | fast_user_write(struct io_mapping *mapping, | |
643 | loff_t page_base, int page_offset, | |
644 | char __user *user_data, | |
645 | int length) | |
9b7530cc | 646 | { |
9b7530cc | 647 | char *vaddr_atomic; |
0839ccb8 | 648 | unsigned long unwritten; |
9b7530cc | 649 | |
3e4d3af5 | 650 | vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base); |
0839ccb8 KP |
651 | unwritten = __copy_from_user_inatomic_nocache(vaddr_atomic + page_offset, |
652 | user_data, length); | |
3e4d3af5 | 653 | io_mapping_unmap_atomic(vaddr_atomic); |
fbd5a26d | 654 | return unwritten; |
0839ccb8 KP |
655 | } |
656 | ||
657 | /* Here's the write path which can sleep for | |
658 | * page faults | |
659 | */ | |
660 | ||
ab34c226 | 661 | static inline void |
3de09aa3 EA |
662 | slow_kernel_write(struct io_mapping *mapping, |
663 | loff_t gtt_base, int gtt_offset, | |
664 | struct page *user_page, int user_offset, | |
665 | int length) | |
0839ccb8 | 666 | { |
ab34c226 CW |
667 | char __iomem *dst_vaddr; |
668 | char *src_vaddr; | |
0839ccb8 | 669 | |
ab34c226 CW |
670 | dst_vaddr = io_mapping_map_wc(mapping, gtt_base); |
671 | src_vaddr = kmap(user_page); | |
672 | ||
673 | memcpy_toio(dst_vaddr + gtt_offset, | |
674 | src_vaddr + user_offset, | |
675 | length); | |
676 | ||
677 | kunmap(user_page); | |
678 | io_mapping_unmap(dst_vaddr); | |
9b7530cc LT |
679 | } |
680 | ||
3de09aa3 EA |
681 | /** |
682 | * This is the fast pwrite path, where we copy the data directly from the | |
683 | * user into the GTT, uncached. | |
684 | */ | |
673a394b | 685 | static int |
3de09aa3 EA |
686 | i915_gem_gtt_pwrite_fast(struct drm_device *dev, struct drm_gem_object *obj, |
687 | struct drm_i915_gem_pwrite *args, | |
688 | struct drm_file *file_priv) | |
673a394b | 689 | { |
23010e43 | 690 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
0839ccb8 | 691 | drm_i915_private_t *dev_priv = dev->dev_private; |
673a394b | 692 | ssize_t remain; |
0839ccb8 | 693 | loff_t offset, page_base; |
673a394b | 694 | char __user *user_data; |
0839ccb8 | 695 | int page_offset, page_length; |
673a394b EA |
696 | |
697 | user_data = (char __user *) (uintptr_t) args->data_ptr; | |
698 | remain = args->size; | |
673a394b | 699 | |
23010e43 | 700 | obj_priv = to_intel_bo(obj); |
673a394b | 701 | offset = obj_priv->gtt_offset + args->offset; |
673a394b EA |
702 | |
703 | while (remain > 0) { | |
704 | /* Operation in this page | |
705 | * | |
0839ccb8 KP |
706 | * page_base = page offset within aperture |
707 | * page_offset = offset within page | |
708 | * page_length = bytes to copy for this page | |
673a394b | 709 | */ |
0839ccb8 KP |
710 | page_base = (offset & ~(PAGE_SIZE-1)); |
711 | page_offset = offset & (PAGE_SIZE-1); | |
712 | page_length = remain; | |
713 | if ((page_offset + remain) > PAGE_SIZE) | |
714 | page_length = PAGE_SIZE - page_offset; | |
715 | ||
0839ccb8 | 716 | /* If we get a fault while copying data, then (presumably) our |
3de09aa3 EA |
717 | * source page isn't available. Return the error and we'll |
718 | * retry in the slow path. | |
0839ccb8 | 719 | */ |
fbd5a26d CW |
720 | if (fast_user_write(dev_priv->mm.gtt_mapping, page_base, |
721 | page_offset, user_data, page_length)) | |
722 | ||
723 | return -EFAULT; | |
673a394b | 724 | |
0839ccb8 KP |
725 | remain -= page_length; |
726 | user_data += page_length; | |
727 | offset += page_length; | |
673a394b | 728 | } |
673a394b | 729 | |
fbd5a26d | 730 | return 0; |
673a394b EA |
731 | } |
732 | ||
3de09aa3 EA |
733 | /** |
734 | * This is the fallback GTT pwrite path, which uses get_user_pages to pin | |
735 | * the memory and maps it using kmap_atomic for copying. | |
736 | * | |
737 | * This code resulted in x11perf -rgb10text consuming about 10% more CPU | |
738 | * than using i915_gem_gtt_pwrite_fast on a G45 (32-bit). | |
739 | */ | |
3043c60c | 740 | static int |
3de09aa3 EA |
741 | i915_gem_gtt_pwrite_slow(struct drm_device *dev, struct drm_gem_object *obj, |
742 | struct drm_i915_gem_pwrite *args, | |
743 | struct drm_file *file_priv) | |
673a394b | 744 | { |
23010e43 | 745 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
3de09aa3 EA |
746 | drm_i915_private_t *dev_priv = dev->dev_private; |
747 | ssize_t remain; | |
748 | loff_t gtt_page_base, offset; | |
749 | loff_t first_data_page, last_data_page, num_pages; | |
750 | loff_t pinned_pages, i; | |
751 | struct page **user_pages; | |
752 | struct mm_struct *mm = current->mm; | |
753 | int gtt_page_offset, data_page_offset, data_page_index, page_length; | |
673a394b | 754 | int ret; |
3de09aa3 EA |
755 | uint64_t data_ptr = args->data_ptr; |
756 | ||
757 | remain = args->size; | |
758 | ||
759 | /* Pin the user pages containing the data. We can't fault while | |
760 | * holding the struct mutex, and all of the pwrite implementations | |
761 | * want to hold it while dereferencing the user data. | |
762 | */ | |
763 | first_data_page = data_ptr / PAGE_SIZE; | |
764 | last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE; | |
765 | num_pages = last_data_page - first_data_page + 1; | |
766 | ||
fbd5a26d | 767 | user_pages = drm_malloc_ab(num_pages, sizeof(struct page *)); |
3de09aa3 EA |
768 | if (user_pages == NULL) |
769 | return -ENOMEM; | |
770 | ||
fbd5a26d | 771 | mutex_unlock(&dev->struct_mutex); |
3de09aa3 EA |
772 | down_read(&mm->mmap_sem); |
773 | pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr, | |
774 | num_pages, 0, 0, user_pages, NULL); | |
775 | up_read(&mm->mmap_sem); | |
fbd5a26d | 776 | mutex_lock(&dev->struct_mutex); |
3de09aa3 EA |
777 | if (pinned_pages < num_pages) { |
778 | ret = -EFAULT; | |
779 | goto out_unpin_pages; | |
780 | } | |
673a394b | 781 | |
3de09aa3 EA |
782 | ret = i915_gem_object_set_to_gtt_domain(obj, 1); |
783 | if (ret) | |
fbd5a26d | 784 | goto out_unpin_pages; |
3de09aa3 | 785 | |
23010e43 | 786 | obj_priv = to_intel_bo(obj); |
3de09aa3 EA |
787 | offset = obj_priv->gtt_offset + args->offset; |
788 | ||
789 | while (remain > 0) { | |
790 | /* Operation in this page | |
791 | * | |
792 | * gtt_page_base = page offset within aperture | |
793 | * gtt_page_offset = offset within page in aperture | |
794 | * data_page_index = page number in get_user_pages return | |
795 | * data_page_offset = offset with data_page_index page. | |
796 | * page_length = bytes to copy for this page | |
797 | */ | |
798 | gtt_page_base = offset & PAGE_MASK; | |
799 | gtt_page_offset = offset & ~PAGE_MASK; | |
800 | data_page_index = data_ptr / PAGE_SIZE - first_data_page; | |
801 | data_page_offset = data_ptr & ~PAGE_MASK; | |
802 | ||
803 | page_length = remain; | |
804 | if ((gtt_page_offset + page_length) > PAGE_SIZE) | |
805 | page_length = PAGE_SIZE - gtt_page_offset; | |
806 | if ((data_page_offset + page_length) > PAGE_SIZE) | |
807 | page_length = PAGE_SIZE - data_page_offset; | |
808 | ||
ab34c226 CW |
809 | slow_kernel_write(dev_priv->mm.gtt_mapping, |
810 | gtt_page_base, gtt_page_offset, | |
811 | user_pages[data_page_index], | |
812 | data_page_offset, | |
813 | page_length); | |
3de09aa3 EA |
814 | |
815 | remain -= page_length; | |
816 | offset += page_length; | |
817 | data_ptr += page_length; | |
818 | } | |
819 | ||
3de09aa3 EA |
820 | out_unpin_pages: |
821 | for (i = 0; i < pinned_pages; i++) | |
822 | page_cache_release(user_pages[i]); | |
8e7d2b2c | 823 | drm_free_large(user_pages); |
3de09aa3 EA |
824 | |
825 | return ret; | |
826 | } | |
827 | ||
40123c1f EA |
828 | /** |
829 | * This is the fast shmem pwrite path, which attempts to directly | |
830 | * copy_from_user into the kmapped pages backing the object. | |
831 | */ | |
3043c60c | 832 | static int |
40123c1f EA |
833 | i915_gem_shmem_pwrite_fast(struct drm_device *dev, struct drm_gem_object *obj, |
834 | struct drm_i915_gem_pwrite *args, | |
835 | struct drm_file *file_priv) | |
673a394b | 836 | { |
e5281ccd | 837 | struct address_space *mapping = obj->filp->f_path.dentry->d_inode->i_mapping; |
23010e43 | 838 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
40123c1f | 839 | ssize_t remain; |
e5281ccd | 840 | loff_t offset; |
40123c1f EA |
841 | char __user *user_data; |
842 | int page_offset, page_length; | |
40123c1f EA |
843 | |
844 | user_data = (char __user *) (uintptr_t) args->data_ptr; | |
845 | remain = args->size; | |
673a394b | 846 | |
23010e43 | 847 | obj_priv = to_intel_bo(obj); |
40123c1f EA |
848 | offset = args->offset; |
849 | obj_priv->dirty = 1; | |
850 | ||
851 | while (remain > 0) { | |
e5281ccd CW |
852 | struct page *page; |
853 | char *vaddr; | |
854 | int ret; | |
855 | ||
40123c1f EA |
856 | /* Operation in this page |
857 | * | |
40123c1f EA |
858 | * page_offset = offset within page |
859 | * page_length = bytes to copy for this page | |
860 | */ | |
40123c1f EA |
861 | page_offset = offset & (PAGE_SIZE-1); |
862 | page_length = remain; | |
863 | if ((page_offset + remain) > PAGE_SIZE) | |
864 | page_length = PAGE_SIZE - page_offset; | |
865 | ||
e5281ccd CW |
866 | page = read_cache_page_gfp(mapping, offset >> PAGE_SHIFT, |
867 | GFP_HIGHUSER | __GFP_RECLAIMABLE); | |
868 | if (IS_ERR(page)) | |
869 | return PTR_ERR(page); | |
870 | ||
871 | vaddr = kmap_atomic(page, KM_USER0); | |
872 | ret = __copy_from_user_inatomic(vaddr + page_offset, | |
873 | user_data, | |
874 | page_length); | |
875 | kunmap_atomic(vaddr, KM_USER0); | |
876 | ||
877 | set_page_dirty(page); | |
878 | mark_page_accessed(page); | |
879 | page_cache_release(page); | |
880 | ||
881 | /* If we get a fault while copying data, then (presumably) our | |
882 | * source page isn't available. Return the error and we'll | |
883 | * retry in the slow path. | |
884 | */ | |
885 | if (ret) | |
fbd5a26d | 886 | return -EFAULT; |
40123c1f EA |
887 | |
888 | remain -= page_length; | |
889 | user_data += page_length; | |
890 | offset += page_length; | |
891 | } | |
892 | ||
fbd5a26d | 893 | return 0; |
40123c1f EA |
894 | } |
895 | ||
896 | /** | |
897 | * This is the fallback shmem pwrite path, which uses get_user_pages to pin | |
898 | * the memory and maps it using kmap_atomic for copying. | |
899 | * | |
900 | * This avoids taking mmap_sem for faulting on the user's address while the | |
901 | * struct_mutex is held. | |
902 | */ | |
903 | static int | |
904 | i915_gem_shmem_pwrite_slow(struct drm_device *dev, struct drm_gem_object *obj, | |
905 | struct drm_i915_gem_pwrite *args, | |
906 | struct drm_file *file_priv) | |
907 | { | |
e5281ccd | 908 | struct address_space *mapping = obj->filp->f_path.dentry->d_inode->i_mapping; |
23010e43 | 909 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
40123c1f EA |
910 | struct mm_struct *mm = current->mm; |
911 | struct page **user_pages; | |
912 | ssize_t remain; | |
913 | loff_t offset, pinned_pages, i; | |
914 | loff_t first_data_page, last_data_page, num_pages; | |
e5281ccd | 915 | int shmem_page_offset; |
40123c1f EA |
916 | int data_page_index, data_page_offset; |
917 | int page_length; | |
918 | int ret; | |
919 | uint64_t data_ptr = args->data_ptr; | |
280b713b | 920 | int do_bit17_swizzling; |
40123c1f EA |
921 | |
922 | remain = args->size; | |
923 | ||
924 | /* Pin the user pages containing the data. We can't fault while | |
925 | * holding the struct mutex, and all of the pwrite implementations | |
926 | * want to hold it while dereferencing the user data. | |
927 | */ | |
928 | first_data_page = data_ptr / PAGE_SIZE; | |
929 | last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE; | |
930 | num_pages = last_data_page - first_data_page + 1; | |
931 | ||
4f27b75d | 932 | user_pages = drm_malloc_ab(num_pages, sizeof(struct page *)); |
40123c1f EA |
933 | if (user_pages == NULL) |
934 | return -ENOMEM; | |
935 | ||
fbd5a26d | 936 | mutex_unlock(&dev->struct_mutex); |
40123c1f EA |
937 | down_read(&mm->mmap_sem); |
938 | pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr, | |
939 | num_pages, 0, 0, user_pages, NULL); | |
940 | up_read(&mm->mmap_sem); | |
fbd5a26d | 941 | mutex_lock(&dev->struct_mutex); |
40123c1f EA |
942 | if (pinned_pages < num_pages) { |
943 | ret = -EFAULT; | |
fbd5a26d | 944 | goto out; |
673a394b EA |
945 | } |
946 | ||
fbd5a26d | 947 | ret = i915_gem_object_set_to_cpu_domain(obj, 1); |
07f73f69 | 948 | if (ret) |
fbd5a26d | 949 | goto out; |
40123c1f | 950 | |
fbd5a26d | 951 | do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj); |
40123c1f | 952 | |
23010e43 | 953 | obj_priv = to_intel_bo(obj); |
673a394b | 954 | offset = args->offset; |
40123c1f | 955 | obj_priv->dirty = 1; |
673a394b | 956 | |
40123c1f | 957 | while (remain > 0) { |
e5281ccd CW |
958 | struct page *page; |
959 | ||
40123c1f EA |
960 | /* Operation in this page |
961 | * | |
40123c1f EA |
962 | * shmem_page_offset = offset within page in shmem file |
963 | * data_page_index = page number in get_user_pages return | |
964 | * data_page_offset = offset with data_page_index page. | |
965 | * page_length = bytes to copy for this page | |
966 | */ | |
40123c1f EA |
967 | shmem_page_offset = offset & ~PAGE_MASK; |
968 | data_page_index = data_ptr / PAGE_SIZE - first_data_page; | |
969 | data_page_offset = data_ptr & ~PAGE_MASK; | |
970 | ||
971 | page_length = remain; | |
972 | if ((shmem_page_offset + page_length) > PAGE_SIZE) | |
973 | page_length = PAGE_SIZE - shmem_page_offset; | |
974 | if ((data_page_offset + page_length) > PAGE_SIZE) | |
975 | page_length = PAGE_SIZE - data_page_offset; | |
976 | ||
e5281ccd CW |
977 | page = read_cache_page_gfp(mapping, offset >> PAGE_SHIFT, |
978 | GFP_HIGHUSER | __GFP_RECLAIMABLE); | |
979 | if (IS_ERR(page)) { | |
980 | ret = PTR_ERR(page); | |
981 | goto out; | |
982 | } | |
983 | ||
280b713b | 984 | if (do_bit17_swizzling) { |
e5281ccd | 985 | slow_shmem_bit17_copy(page, |
280b713b EA |
986 | shmem_page_offset, |
987 | user_pages[data_page_index], | |
988 | data_page_offset, | |
99a03df5 CW |
989 | page_length, |
990 | 0); | |
991 | } else { | |
e5281ccd | 992 | slow_shmem_copy(page, |
99a03df5 CW |
993 | shmem_page_offset, |
994 | user_pages[data_page_index], | |
995 | data_page_offset, | |
996 | page_length); | |
280b713b | 997 | } |
40123c1f | 998 | |
e5281ccd CW |
999 | set_page_dirty(page); |
1000 | mark_page_accessed(page); | |
1001 | page_cache_release(page); | |
1002 | ||
40123c1f EA |
1003 | remain -= page_length; |
1004 | data_ptr += page_length; | |
1005 | offset += page_length; | |
673a394b EA |
1006 | } |
1007 | ||
fbd5a26d | 1008 | out: |
40123c1f EA |
1009 | for (i = 0; i < pinned_pages; i++) |
1010 | page_cache_release(user_pages[i]); | |
8e7d2b2c | 1011 | drm_free_large(user_pages); |
673a394b | 1012 | |
40123c1f | 1013 | return ret; |
673a394b EA |
1014 | } |
1015 | ||
1016 | /** | |
1017 | * Writes data to the object referenced by handle. | |
1018 | * | |
1019 | * On error, the contents of the buffer that were to be modified are undefined. | |
1020 | */ | |
1021 | int | |
1022 | i915_gem_pwrite_ioctl(struct drm_device *dev, void *data, | |
fbd5a26d | 1023 | struct drm_file *file) |
673a394b EA |
1024 | { |
1025 | struct drm_i915_gem_pwrite *args = data; | |
1026 | struct drm_gem_object *obj; | |
1027 | struct drm_i915_gem_object *obj_priv; | |
1028 | int ret = 0; | |
1029 | ||
fbd5a26d | 1030 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 1031 | if (ret) |
fbd5a26d | 1032 | return ret; |
1d7cfea1 CW |
1033 | |
1034 | obj = drm_gem_object_lookup(dev, file, args->handle); | |
1035 | if (obj == NULL) { | |
1036 | ret = -ENOENT; | |
1037 | goto unlock; | |
fbd5a26d | 1038 | } |
23010e43 | 1039 | obj_priv = to_intel_bo(obj); |
673a394b | 1040 | |
fbd5a26d | 1041 | |
7dcd2499 CW |
1042 | /* Bounds check destination. */ |
1043 | if (args->offset > obj->size || args->size > obj->size - args->offset) { | |
ce9d419d | 1044 | ret = -EINVAL; |
35b62a89 | 1045 | goto out; |
ce9d419d CW |
1046 | } |
1047 | ||
35b62a89 CW |
1048 | if (args->size == 0) |
1049 | goto out; | |
1050 | ||
ce9d419d CW |
1051 | if (!access_ok(VERIFY_READ, |
1052 | (char __user *)(uintptr_t)args->data_ptr, | |
1053 | args->size)) { | |
1054 | ret = -EFAULT; | |
35b62a89 | 1055 | goto out; |
673a394b EA |
1056 | } |
1057 | ||
b5e4feb6 CW |
1058 | ret = fault_in_pages_readable((char __user *)(uintptr_t)args->data_ptr, |
1059 | args->size); | |
1060 | if (ret) { | |
1061 | ret = -EFAULT; | |
1062 | goto out; | |
673a394b EA |
1063 | } |
1064 | ||
1065 | /* We can only do the GTT pwrite on untiled buffers, as otherwise | |
1066 | * it would end up going through the fenced access, and we'll get | |
1067 | * different detiling behavior between reading and writing. | |
1068 | * pread/pwrite currently are reading and writing from the CPU | |
1069 | * perspective, requiring manual detiling by the client. | |
1070 | */ | |
71acb5eb | 1071 | if (obj_priv->phys_obj) |
fbd5a26d | 1072 | ret = i915_gem_phys_pwrite(dev, obj, args, file); |
71acb5eb | 1073 | else if (obj_priv->tiling_mode == I915_TILING_NONE && |
5cdf5881 | 1074 | obj_priv->gtt_space && |
9b8c4a0b | 1075 | obj->write_domain != I915_GEM_DOMAIN_CPU) { |
75e9e915 | 1076 | ret = i915_gem_object_pin(obj, 0, true); |
fbd5a26d CW |
1077 | if (ret) |
1078 | goto out; | |
1079 | ||
1080 | ret = i915_gem_object_set_to_gtt_domain(obj, 1); | |
1081 | if (ret) | |
1082 | goto out_unpin; | |
1083 | ||
1084 | ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file); | |
1085 | if (ret == -EFAULT) | |
1086 | ret = i915_gem_gtt_pwrite_slow(dev, obj, args, file); | |
1087 | ||
1088 | out_unpin: | |
1089 | i915_gem_object_unpin(obj); | |
40123c1f | 1090 | } else { |
fbd5a26d CW |
1091 | ret = i915_gem_object_set_to_cpu_domain(obj, 1); |
1092 | if (ret) | |
e5281ccd | 1093 | goto out; |
673a394b | 1094 | |
fbd5a26d CW |
1095 | ret = -EFAULT; |
1096 | if (!i915_gem_object_needs_bit17_swizzle(obj)) | |
1097 | ret = i915_gem_shmem_pwrite_fast(dev, obj, args, file); | |
1098 | if (ret == -EFAULT) | |
1099 | ret = i915_gem_shmem_pwrite_slow(dev, obj, args, file); | |
fbd5a26d | 1100 | } |
673a394b | 1101 | |
35b62a89 | 1102 | out: |
fbd5a26d | 1103 | drm_gem_object_unreference(obj); |
1d7cfea1 | 1104 | unlock: |
fbd5a26d | 1105 | mutex_unlock(&dev->struct_mutex); |
673a394b EA |
1106 | return ret; |
1107 | } | |
1108 | ||
1109 | /** | |
2ef7eeaa EA |
1110 | * Called when user space prepares to use an object with the CPU, either |
1111 | * through the mmap ioctl's mapping or a GTT mapping. | |
673a394b EA |
1112 | */ |
1113 | int | |
1114 | i915_gem_set_domain_ioctl(struct drm_device *dev, void *data, | |
1115 | struct drm_file *file_priv) | |
1116 | { | |
a09ba7fa | 1117 | struct drm_i915_private *dev_priv = dev->dev_private; |
673a394b EA |
1118 | struct drm_i915_gem_set_domain *args = data; |
1119 | struct drm_gem_object *obj; | |
652c393a | 1120 | struct drm_i915_gem_object *obj_priv; |
2ef7eeaa EA |
1121 | uint32_t read_domains = args->read_domains; |
1122 | uint32_t write_domain = args->write_domain; | |
673a394b EA |
1123 | int ret; |
1124 | ||
1125 | if (!(dev->driver->driver_features & DRIVER_GEM)) | |
1126 | return -ENODEV; | |
1127 | ||
2ef7eeaa | 1128 | /* Only handle setting domains to types used by the CPU. */ |
21d509e3 | 1129 | if (write_domain & I915_GEM_GPU_DOMAINS) |
2ef7eeaa EA |
1130 | return -EINVAL; |
1131 | ||
21d509e3 | 1132 | if (read_domains & I915_GEM_GPU_DOMAINS) |
2ef7eeaa EA |
1133 | return -EINVAL; |
1134 | ||
1135 | /* Having something in the write domain implies it's in the read | |
1136 | * domain, and only that read domain. Enforce that in the request. | |
1137 | */ | |
1138 | if (write_domain != 0 && read_domains != write_domain) | |
1139 | return -EINVAL; | |
1140 | ||
76c1dec1 | 1141 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 1142 | if (ret) |
76c1dec1 | 1143 | return ret; |
1d7cfea1 | 1144 | |
673a394b | 1145 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); |
1d7cfea1 CW |
1146 | if (obj == NULL) { |
1147 | ret = -ENOENT; | |
1148 | goto unlock; | |
76c1dec1 | 1149 | } |
23010e43 | 1150 | obj_priv = to_intel_bo(obj); |
673a394b | 1151 | |
652c393a JB |
1152 | intel_mark_busy(dev, obj); |
1153 | ||
2ef7eeaa EA |
1154 | if (read_domains & I915_GEM_DOMAIN_GTT) { |
1155 | ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0); | |
02354392 | 1156 | |
a09ba7fa EA |
1157 | /* Update the LRU on the fence for the CPU access that's |
1158 | * about to occur. | |
1159 | */ | |
1160 | if (obj_priv->fence_reg != I915_FENCE_REG_NONE) { | |
007cc8ac DV |
1161 | struct drm_i915_fence_reg *reg = |
1162 | &dev_priv->fence_regs[obj_priv->fence_reg]; | |
1163 | list_move_tail(®->lru_list, | |
a09ba7fa EA |
1164 | &dev_priv->mm.fence_list); |
1165 | } | |
1166 | ||
02354392 EA |
1167 | /* Silently promote "you're not bound, there was nothing to do" |
1168 | * to success, since the client was just asking us to | |
1169 | * make sure everything was done. | |
1170 | */ | |
1171 | if (ret == -EINVAL) | |
1172 | ret = 0; | |
2ef7eeaa | 1173 | } else { |
e47c68e9 | 1174 | ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0); |
2ef7eeaa EA |
1175 | } |
1176 | ||
7d1c4804 CW |
1177 | /* Maintain LRU order of "inactive" objects */ |
1178 | if (ret == 0 && i915_gem_object_is_inactive(obj_priv)) | |
69dc4987 | 1179 | list_move_tail(&obj_priv->mm_list, &dev_priv->mm.inactive_list); |
7d1c4804 | 1180 | |
673a394b | 1181 | drm_gem_object_unreference(obj); |
1d7cfea1 | 1182 | unlock: |
673a394b EA |
1183 | mutex_unlock(&dev->struct_mutex); |
1184 | return ret; | |
1185 | } | |
1186 | ||
1187 | /** | |
1188 | * Called when user space has done writes to this buffer | |
1189 | */ | |
1190 | int | |
1191 | i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data, | |
1192 | struct drm_file *file_priv) | |
1193 | { | |
1194 | struct drm_i915_gem_sw_finish *args = data; | |
1195 | struct drm_gem_object *obj; | |
673a394b EA |
1196 | int ret = 0; |
1197 | ||
1198 | if (!(dev->driver->driver_features & DRIVER_GEM)) | |
1199 | return -ENODEV; | |
1200 | ||
76c1dec1 | 1201 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 1202 | if (ret) |
76c1dec1 | 1203 | return ret; |
1d7cfea1 | 1204 | |
673a394b EA |
1205 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); |
1206 | if (obj == NULL) { | |
1d7cfea1 CW |
1207 | ret = -ENOENT; |
1208 | goto unlock; | |
673a394b EA |
1209 | } |
1210 | ||
673a394b | 1211 | /* Pinned buffers may be scanout, so flush the cache */ |
3d2a812a | 1212 | if (to_intel_bo(obj)->pin_count) |
e47c68e9 EA |
1213 | i915_gem_object_flush_cpu_write_domain(obj); |
1214 | ||
673a394b | 1215 | drm_gem_object_unreference(obj); |
1d7cfea1 | 1216 | unlock: |
673a394b EA |
1217 | mutex_unlock(&dev->struct_mutex); |
1218 | return ret; | |
1219 | } | |
1220 | ||
1221 | /** | |
1222 | * Maps the contents of an object, returning the address it is mapped | |
1223 | * into. | |
1224 | * | |
1225 | * While the mapping holds a reference on the contents of the object, it doesn't | |
1226 | * imply a ref on the object itself. | |
1227 | */ | |
1228 | int | |
1229 | i915_gem_mmap_ioctl(struct drm_device *dev, void *data, | |
1230 | struct drm_file *file_priv) | |
1231 | { | |
da761a6e | 1232 | struct drm_i915_private *dev_priv = dev->dev_private; |
673a394b EA |
1233 | struct drm_i915_gem_mmap *args = data; |
1234 | struct drm_gem_object *obj; | |
1235 | loff_t offset; | |
1236 | unsigned long addr; | |
1237 | ||
1238 | if (!(dev->driver->driver_features & DRIVER_GEM)) | |
1239 | return -ENODEV; | |
1240 | ||
1241 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); | |
1242 | if (obj == NULL) | |
bf79cb91 | 1243 | return -ENOENT; |
673a394b | 1244 | |
da761a6e CW |
1245 | if (obj->size > dev_priv->mm.gtt_mappable_end) { |
1246 | drm_gem_object_unreference_unlocked(obj); | |
1247 | return -E2BIG; | |
1248 | } | |
1249 | ||
673a394b EA |
1250 | offset = args->offset; |
1251 | ||
1252 | down_write(¤t->mm->mmap_sem); | |
1253 | addr = do_mmap(obj->filp, 0, args->size, | |
1254 | PROT_READ | PROT_WRITE, MAP_SHARED, | |
1255 | args->offset); | |
1256 | up_write(¤t->mm->mmap_sem); | |
bc9025bd | 1257 | drm_gem_object_unreference_unlocked(obj); |
673a394b EA |
1258 | if (IS_ERR((void *)addr)) |
1259 | return addr; | |
1260 | ||
1261 | args->addr_ptr = (uint64_t) addr; | |
1262 | ||
1263 | return 0; | |
1264 | } | |
1265 | ||
de151cf6 JB |
1266 | /** |
1267 | * i915_gem_fault - fault a page into the GTT | |
1268 | * vma: VMA in question | |
1269 | * vmf: fault info | |
1270 | * | |
1271 | * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped | |
1272 | * from userspace. The fault handler takes care of binding the object to | |
1273 | * the GTT (if needed), allocating and programming a fence register (again, | |
1274 | * only if needed based on whether the old reg is still valid or the object | |
1275 | * is tiled) and inserting a new PTE into the faulting process. | |
1276 | * | |
1277 | * Note that the faulting process may involve evicting existing objects | |
1278 | * from the GTT and/or fence registers to make room. So performance may | |
1279 | * suffer if the GTT working set is large or there are few fence registers | |
1280 | * left. | |
1281 | */ | |
1282 | int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf) | |
1283 | { | |
1284 | struct drm_gem_object *obj = vma->vm_private_data; | |
1285 | struct drm_device *dev = obj->dev; | |
7d1c4804 | 1286 | drm_i915_private_t *dev_priv = dev->dev_private; |
23010e43 | 1287 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
de151cf6 JB |
1288 | pgoff_t page_offset; |
1289 | unsigned long pfn; | |
1290 | int ret = 0; | |
0f973f27 | 1291 | bool write = !!(vmf->flags & FAULT_FLAG_WRITE); |
de151cf6 JB |
1292 | |
1293 | /* We don't use vmf->pgoff since that has the fake offset */ | |
1294 | page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >> | |
1295 | PAGE_SHIFT; | |
1296 | ||
1297 | /* Now bind it into the GTT if needed */ | |
1298 | mutex_lock(&dev->struct_mutex); | |
fb7d516a | 1299 | BUG_ON(obj_priv->pin_count && !obj_priv->pin_mappable); |
a00b10c3 CW |
1300 | |
1301 | if (obj_priv->gtt_space) { | |
75e9e915 | 1302 | if (!obj_priv->map_and_fenceable) { |
a00b10c3 CW |
1303 | ret = i915_gem_object_unbind(obj); |
1304 | if (ret) | |
1305 | goto unlock; | |
1306 | } | |
1307 | } | |
16e809ac | 1308 | |
de151cf6 | 1309 | if (!obj_priv->gtt_space) { |
75e9e915 | 1310 | ret = i915_gem_object_bind_to_gtt(obj, 0, true); |
c715089f CW |
1311 | if (ret) |
1312 | goto unlock; | |
de151cf6 JB |
1313 | } |
1314 | ||
4a684a41 CW |
1315 | ret = i915_gem_object_set_to_gtt_domain(obj, write); |
1316 | if (ret) | |
1317 | goto unlock; | |
1318 | ||
fb7d516a DV |
1319 | if (!obj_priv->fault_mappable) { |
1320 | obj_priv->fault_mappable = true; | |
a00b10c3 | 1321 | i915_gem_info_update_mappable(dev_priv, obj_priv, true); |
fb7d516a DV |
1322 | } |
1323 | ||
de151cf6 | 1324 | /* Need a new fence register? */ |
a09ba7fa | 1325 | if (obj_priv->tiling_mode != I915_TILING_NONE) { |
2cf34d7b | 1326 | ret = i915_gem_object_get_fence_reg(obj, true); |
c715089f CW |
1327 | if (ret) |
1328 | goto unlock; | |
d9ddcb96 | 1329 | } |
de151cf6 | 1330 | |
7d1c4804 | 1331 | if (i915_gem_object_is_inactive(obj_priv)) |
69dc4987 | 1332 | list_move_tail(&obj_priv->mm_list, &dev_priv->mm.inactive_list); |
7d1c4804 | 1333 | |
de151cf6 JB |
1334 | pfn = ((dev->agp->base + obj_priv->gtt_offset) >> PAGE_SHIFT) + |
1335 | page_offset; | |
1336 | ||
1337 | /* Finally, remap it using the new GTT offset */ | |
1338 | ret = vm_insert_pfn(vma, (unsigned long)vmf->virtual_address, pfn); | |
c715089f | 1339 | unlock: |
de151cf6 JB |
1340 | mutex_unlock(&dev->struct_mutex); |
1341 | ||
1342 | switch (ret) { | |
c715089f CW |
1343 | case 0: |
1344 | case -ERESTARTSYS: | |
1345 | return VM_FAULT_NOPAGE; | |
de151cf6 JB |
1346 | case -ENOMEM: |
1347 | case -EAGAIN: | |
1348 | return VM_FAULT_OOM; | |
de151cf6 | 1349 | default: |
c715089f | 1350 | return VM_FAULT_SIGBUS; |
de151cf6 JB |
1351 | } |
1352 | } | |
1353 | ||
1354 | /** | |
1355 | * i915_gem_create_mmap_offset - create a fake mmap offset for an object | |
1356 | * @obj: obj in question | |
1357 | * | |
1358 | * GEM memory mapping works by handing back to userspace a fake mmap offset | |
1359 | * it can use in a subsequent mmap(2) call. The DRM core code then looks | |
1360 | * up the object based on the offset and sets up the various memory mapping | |
1361 | * structures. | |
1362 | * | |
1363 | * This routine allocates and attaches a fake offset for @obj. | |
1364 | */ | |
1365 | static int | |
1366 | i915_gem_create_mmap_offset(struct drm_gem_object *obj) | |
1367 | { | |
1368 | struct drm_device *dev = obj->dev; | |
1369 | struct drm_gem_mm *mm = dev->mm_private; | |
de151cf6 | 1370 | struct drm_map_list *list; |
f77d390c | 1371 | struct drm_local_map *map; |
de151cf6 JB |
1372 | int ret = 0; |
1373 | ||
1374 | /* Set the object up for mmap'ing */ | |
1375 | list = &obj->map_list; | |
9a298b2a | 1376 | list->map = kzalloc(sizeof(struct drm_map_list), GFP_KERNEL); |
de151cf6 JB |
1377 | if (!list->map) |
1378 | return -ENOMEM; | |
1379 | ||
1380 | map = list->map; | |
1381 | map->type = _DRM_GEM; | |
1382 | map->size = obj->size; | |
1383 | map->handle = obj; | |
1384 | ||
1385 | /* Get a DRM GEM mmap offset allocated... */ | |
1386 | list->file_offset_node = drm_mm_search_free(&mm->offset_manager, | |
1387 | obj->size / PAGE_SIZE, 0, 0); | |
1388 | if (!list->file_offset_node) { | |
1389 | DRM_ERROR("failed to allocate offset for bo %d\n", obj->name); | |
9e0ae534 | 1390 | ret = -ENOSPC; |
de151cf6 JB |
1391 | goto out_free_list; |
1392 | } | |
1393 | ||
1394 | list->file_offset_node = drm_mm_get_block(list->file_offset_node, | |
1395 | obj->size / PAGE_SIZE, 0); | |
1396 | if (!list->file_offset_node) { | |
1397 | ret = -ENOMEM; | |
1398 | goto out_free_list; | |
1399 | } | |
1400 | ||
1401 | list->hash.key = list->file_offset_node->start; | |
9e0ae534 CW |
1402 | ret = drm_ht_insert_item(&mm->offset_hash, &list->hash); |
1403 | if (ret) { | |
de151cf6 JB |
1404 | DRM_ERROR("failed to add to map hash\n"); |
1405 | goto out_free_mm; | |
1406 | } | |
1407 | ||
de151cf6 JB |
1408 | return 0; |
1409 | ||
1410 | out_free_mm: | |
1411 | drm_mm_put_block(list->file_offset_node); | |
1412 | out_free_list: | |
9a298b2a | 1413 | kfree(list->map); |
39a01d1f | 1414 | list->map = NULL; |
de151cf6 JB |
1415 | |
1416 | return ret; | |
1417 | } | |
1418 | ||
901782b2 CW |
1419 | /** |
1420 | * i915_gem_release_mmap - remove physical page mappings | |
1421 | * @obj: obj in question | |
1422 | * | |
af901ca1 | 1423 | * Preserve the reservation of the mmapping with the DRM core code, but |
901782b2 CW |
1424 | * relinquish ownership of the pages back to the system. |
1425 | * | |
1426 | * It is vital that we remove the page mapping if we have mapped a tiled | |
1427 | * object through the GTT and then lose the fence register due to | |
1428 | * resource pressure. Similarly if the object has been moved out of the | |
1429 | * aperture, than pages mapped into userspace must be revoked. Removing the | |
1430 | * mapping will then trigger a page fault on the next user access, allowing | |
1431 | * fixup by i915_gem_fault(). | |
1432 | */ | |
d05ca301 | 1433 | void |
901782b2 CW |
1434 | i915_gem_release_mmap(struct drm_gem_object *obj) |
1435 | { | |
1436 | struct drm_device *dev = obj->dev; | |
fb7d516a | 1437 | struct drm_i915_private *dev_priv = dev->dev_private; |
23010e43 | 1438 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
901782b2 | 1439 | |
39a01d1f | 1440 | if (unlikely(obj->map_list.map && dev->dev_mapping)) |
901782b2 | 1441 | unmap_mapping_range(dev->dev_mapping, |
39a01d1f CW |
1442 | (loff_t)obj->map_list.hash.key<<PAGE_SHIFT, |
1443 | obj->size, 1); | |
fb7d516a DV |
1444 | |
1445 | if (obj_priv->fault_mappable) { | |
1446 | obj_priv->fault_mappable = false; | |
a00b10c3 | 1447 | i915_gem_info_update_mappable(dev_priv, obj_priv, false); |
fb7d516a | 1448 | } |
901782b2 CW |
1449 | } |
1450 | ||
ab00b3e5 JB |
1451 | static void |
1452 | i915_gem_free_mmap_offset(struct drm_gem_object *obj) | |
1453 | { | |
1454 | struct drm_device *dev = obj->dev; | |
ab00b3e5 | 1455 | struct drm_gem_mm *mm = dev->mm_private; |
39a01d1f | 1456 | struct drm_map_list *list = &obj->map_list; |
ab00b3e5 | 1457 | |
ab00b3e5 | 1458 | drm_ht_remove_item(&mm->offset_hash, &list->hash); |
39a01d1f CW |
1459 | drm_mm_put_block(list->file_offset_node); |
1460 | kfree(list->map); | |
1461 | list->map = NULL; | |
ab00b3e5 JB |
1462 | } |
1463 | ||
de151cf6 JB |
1464 | /** |
1465 | * i915_gem_get_gtt_alignment - return required GTT alignment for an object | |
1466 | * @obj: object to check | |
1467 | * | |
1468 | * Return the required GTT alignment for an object, taking into account | |
1469 | * potential fence register mapping if needed. | |
1470 | */ | |
1471 | static uint32_t | |
a00b10c3 | 1472 | i915_gem_get_gtt_alignment(struct drm_i915_gem_object *obj_priv) |
de151cf6 | 1473 | { |
a00b10c3 | 1474 | struct drm_device *dev = obj_priv->base.dev; |
de151cf6 JB |
1475 | |
1476 | /* | |
1477 | * Minimum alignment is 4k (GTT page size), but might be greater | |
1478 | * if a fence register is needed for the object. | |
1479 | */ | |
a00b10c3 CW |
1480 | if (INTEL_INFO(dev)->gen >= 4 || |
1481 | obj_priv->tiling_mode == I915_TILING_NONE) | |
de151cf6 JB |
1482 | return 4096; |
1483 | ||
a00b10c3 CW |
1484 | /* |
1485 | * Previous chips need to be aligned to the size of the smallest | |
1486 | * fence register that can contain the object. | |
1487 | */ | |
1488 | return i915_gem_get_gtt_size(obj_priv); | |
1489 | } | |
1490 | ||
1491 | static uint32_t | |
1492 | i915_gem_get_gtt_size(struct drm_i915_gem_object *obj_priv) | |
1493 | { | |
1494 | struct drm_device *dev = obj_priv->base.dev; | |
1495 | uint32_t size; | |
1496 | ||
1497 | /* | |
1498 | * Minimum alignment is 4k (GTT page size), but might be greater | |
1499 | * if a fence register is needed for the object. | |
1500 | */ | |
1501 | if (INTEL_INFO(dev)->gen >= 4) | |
1502 | return obj_priv->base.size; | |
1503 | ||
de151cf6 JB |
1504 | /* |
1505 | * Previous chips need to be aligned to the size of the smallest | |
1506 | * fence register that can contain the object. | |
1507 | */ | |
a6c45cf0 | 1508 | if (INTEL_INFO(dev)->gen == 3) |
a00b10c3 | 1509 | size = 1024*1024; |
de151cf6 | 1510 | else |
a00b10c3 | 1511 | size = 512*1024; |
de151cf6 | 1512 | |
a00b10c3 CW |
1513 | while (size < obj_priv->base.size) |
1514 | size <<= 1; | |
de151cf6 | 1515 | |
a00b10c3 | 1516 | return size; |
de151cf6 JB |
1517 | } |
1518 | ||
1519 | /** | |
1520 | * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing | |
1521 | * @dev: DRM device | |
1522 | * @data: GTT mapping ioctl data | |
1523 | * @file_priv: GEM object info | |
1524 | * | |
1525 | * Simply returns the fake offset to userspace so it can mmap it. | |
1526 | * The mmap call will end up in drm_gem_mmap(), which will set things | |
1527 | * up so we can get faults in the handler above. | |
1528 | * | |
1529 | * The fault handler will take care of binding the object into the GTT | |
1530 | * (since it may have been evicted to make room for something), allocating | |
1531 | * a fence register, and mapping the appropriate aperture address into | |
1532 | * userspace. | |
1533 | */ | |
1534 | int | |
1535 | i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data, | |
1536 | struct drm_file *file_priv) | |
1537 | { | |
da761a6e | 1538 | struct drm_i915_private *dev_priv = dev->dev_private; |
de151cf6 | 1539 | struct drm_i915_gem_mmap_gtt *args = data; |
de151cf6 JB |
1540 | struct drm_gem_object *obj; |
1541 | struct drm_i915_gem_object *obj_priv; | |
1542 | int ret; | |
1543 | ||
1544 | if (!(dev->driver->driver_features & DRIVER_GEM)) | |
1545 | return -ENODEV; | |
1546 | ||
76c1dec1 | 1547 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 1548 | if (ret) |
76c1dec1 | 1549 | return ret; |
de151cf6 | 1550 | |
1d7cfea1 CW |
1551 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); |
1552 | if (obj == NULL) { | |
1553 | ret = -ENOENT; | |
1554 | goto unlock; | |
1555 | } | |
23010e43 | 1556 | obj_priv = to_intel_bo(obj); |
de151cf6 | 1557 | |
da761a6e CW |
1558 | if (obj->size > dev_priv->mm.gtt_mappable_end) { |
1559 | ret = -E2BIG; | |
1560 | goto unlock; | |
1561 | } | |
1562 | ||
ab18282d CW |
1563 | if (obj_priv->madv != I915_MADV_WILLNEED) { |
1564 | DRM_ERROR("Attempting to mmap a purgeable buffer\n"); | |
1d7cfea1 CW |
1565 | ret = -EINVAL; |
1566 | goto out; | |
ab18282d CW |
1567 | } |
1568 | ||
39a01d1f | 1569 | if (!obj->map_list.map) { |
de151cf6 | 1570 | ret = i915_gem_create_mmap_offset(obj); |
1d7cfea1 CW |
1571 | if (ret) |
1572 | goto out; | |
de151cf6 JB |
1573 | } |
1574 | ||
39a01d1f | 1575 | args->offset = (u64)obj->map_list.hash.key << PAGE_SHIFT; |
de151cf6 | 1576 | |
1d7cfea1 | 1577 | out: |
de151cf6 | 1578 | drm_gem_object_unreference(obj); |
1d7cfea1 | 1579 | unlock: |
de151cf6 | 1580 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 1581 | return ret; |
de151cf6 JB |
1582 | } |
1583 | ||
e5281ccd CW |
1584 | static int |
1585 | i915_gem_object_get_pages_gtt(struct drm_gem_object *obj, | |
1586 | gfp_t gfpmask) | |
1587 | { | |
1588 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); | |
1589 | int page_count, i; | |
1590 | struct address_space *mapping; | |
1591 | struct inode *inode; | |
1592 | struct page *page; | |
1593 | ||
1594 | /* Get the list of pages out of our struct file. They'll be pinned | |
1595 | * at this point until we release them. | |
1596 | */ | |
1597 | page_count = obj->size / PAGE_SIZE; | |
1598 | BUG_ON(obj_priv->pages != NULL); | |
1599 | obj_priv->pages = drm_malloc_ab(page_count, sizeof(struct page *)); | |
1600 | if (obj_priv->pages == NULL) | |
1601 | return -ENOMEM; | |
1602 | ||
1603 | inode = obj->filp->f_path.dentry->d_inode; | |
1604 | mapping = inode->i_mapping; | |
1605 | for (i = 0; i < page_count; i++) { | |
1606 | page = read_cache_page_gfp(mapping, i, | |
1607 | GFP_HIGHUSER | | |
1608 | __GFP_COLD | | |
1609 | __GFP_RECLAIMABLE | | |
1610 | gfpmask); | |
1611 | if (IS_ERR(page)) | |
1612 | goto err_pages; | |
1613 | ||
1614 | obj_priv->pages[i] = page; | |
1615 | } | |
1616 | ||
1617 | if (obj_priv->tiling_mode != I915_TILING_NONE) | |
1618 | i915_gem_object_do_bit_17_swizzle(obj); | |
1619 | ||
1620 | return 0; | |
1621 | ||
1622 | err_pages: | |
1623 | while (i--) | |
1624 | page_cache_release(obj_priv->pages[i]); | |
1625 | ||
1626 | drm_free_large(obj_priv->pages); | |
1627 | obj_priv->pages = NULL; | |
1628 | return PTR_ERR(page); | |
1629 | } | |
1630 | ||
5cdf5881 | 1631 | static void |
e5281ccd | 1632 | i915_gem_object_put_pages_gtt(struct drm_gem_object *obj) |
673a394b | 1633 | { |
23010e43 | 1634 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
673a394b EA |
1635 | int page_count = obj->size / PAGE_SIZE; |
1636 | int i; | |
1637 | ||
bb6baf76 | 1638 | BUG_ON(obj_priv->madv == __I915_MADV_PURGED); |
673a394b | 1639 | |
280b713b EA |
1640 | if (obj_priv->tiling_mode != I915_TILING_NONE) |
1641 | i915_gem_object_save_bit_17_swizzle(obj); | |
1642 | ||
3ef94daa | 1643 | if (obj_priv->madv == I915_MADV_DONTNEED) |
13a05fd9 | 1644 | obj_priv->dirty = 0; |
3ef94daa CW |
1645 | |
1646 | for (i = 0; i < page_count; i++) { | |
3ef94daa CW |
1647 | if (obj_priv->dirty) |
1648 | set_page_dirty(obj_priv->pages[i]); | |
1649 | ||
1650 | if (obj_priv->madv == I915_MADV_WILLNEED) | |
856fa198 | 1651 | mark_page_accessed(obj_priv->pages[i]); |
3ef94daa CW |
1652 | |
1653 | page_cache_release(obj_priv->pages[i]); | |
1654 | } | |
673a394b EA |
1655 | obj_priv->dirty = 0; |
1656 | ||
8e7d2b2c | 1657 | drm_free_large(obj_priv->pages); |
856fa198 | 1658 | obj_priv->pages = NULL; |
673a394b EA |
1659 | } |
1660 | ||
a56ba56c CW |
1661 | static uint32_t |
1662 | i915_gem_next_request_seqno(struct drm_device *dev, | |
1663 | struct intel_ring_buffer *ring) | |
1664 | { | |
1665 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1666 | ||
1667 | ring->outstanding_lazy_request = true; | |
1668 | return dev_priv->next_seqno; | |
1669 | } | |
1670 | ||
673a394b | 1671 | static void |
617dbe27 | 1672 | i915_gem_object_move_to_active(struct drm_gem_object *obj, |
852835f3 | 1673 | struct intel_ring_buffer *ring) |
673a394b EA |
1674 | { |
1675 | struct drm_device *dev = obj->dev; | |
69dc4987 | 1676 | struct drm_i915_private *dev_priv = dev->dev_private; |
23010e43 | 1677 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
a56ba56c | 1678 | uint32_t seqno = i915_gem_next_request_seqno(dev, ring); |
617dbe27 | 1679 | |
852835f3 ZN |
1680 | BUG_ON(ring == NULL); |
1681 | obj_priv->ring = ring; | |
673a394b EA |
1682 | |
1683 | /* Add a reference if we're newly entering the active list. */ | |
1684 | if (!obj_priv->active) { | |
1685 | drm_gem_object_reference(obj); | |
1686 | obj_priv->active = 1; | |
1687 | } | |
e35a41de | 1688 | |
673a394b | 1689 | /* Move from whatever list we were on to the tail of execution. */ |
69dc4987 CW |
1690 | list_move_tail(&obj_priv->mm_list, &dev_priv->mm.active_list); |
1691 | list_move_tail(&obj_priv->ring_list, &ring->active_list); | |
ce44b0ea | 1692 | obj_priv->last_rendering_seqno = seqno; |
673a394b EA |
1693 | } |
1694 | ||
ce44b0ea EA |
1695 | static void |
1696 | i915_gem_object_move_to_flushing(struct drm_gem_object *obj) | |
1697 | { | |
1698 | struct drm_device *dev = obj->dev; | |
1699 | drm_i915_private_t *dev_priv = dev->dev_private; | |
23010e43 | 1700 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
ce44b0ea EA |
1701 | |
1702 | BUG_ON(!obj_priv->active); | |
69dc4987 CW |
1703 | list_move_tail(&obj_priv->mm_list, &dev_priv->mm.flushing_list); |
1704 | list_del_init(&obj_priv->ring_list); | |
ce44b0ea EA |
1705 | obj_priv->last_rendering_seqno = 0; |
1706 | } | |
673a394b | 1707 | |
963b4836 CW |
1708 | /* Immediately discard the backing storage */ |
1709 | static void | |
1710 | i915_gem_object_truncate(struct drm_gem_object *obj) | |
1711 | { | |
23010e43 | 1712 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
bb6baf76 | 1713 | struct inode *inode; |
963b4836 | 1714 | |
ae9fed6b CW |
1715 | /* Our goal here is to return as much of the memory as |
1716 | * is possible back to the system as we are called from OOM. | |
1717 | * To do this we must instruct the shmfs to drop all of its | |
1718 | * backing pages, *now*. Here we mirror the actions taken | |
1719 | * when by shmem_delete_inode() to release the backing store. | |
1720 | */ | |
bb6baf76 | 1721 | inode = obj->filp->f_path.dentry->d_inode; |
ae9fed6b CW |
1722 | truncate_inode_pages(inode->i_mapping, 0); |
1723 | if (inode->i_op->truncate_range) | |
1724 | inode->i_op->truncate_range(inode, 0, (loff_t)-1); | |
bb6baf76 CW |
1725 | |
1726 | obj_priv->madv = __I915_MADV_PURGED; | |
963b4836 CW |
1727 | } |
1728 | ||
1729 | static inline int | |
1730 | i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj_priv) | |
1731 | { | |
1732 | return obj_priv->madv == I915_MADV_DONTNEED; | |
1733 | } | |
1734 | ||
673a394b EA |
1735 | static void |
1736 | i915_gem_object_move_to_inactive(struct drm_gem_object *obj) | |
1737 | { | |
1738 | struct drm_device *dev = obj->dev; | |
1739 | drm_i915_private_t *dev_priv = dev->dev_private; | |
23010e43 | 1740 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
673a394b | 1741 | |
673a394b | 1742 | if (obj_priv->pin_count != 0) |
69dc4987 | 1743 | list_move_tail(&obj_priv->mm_list, &dev_priv->mm.pinned_list); |
673a394b | 1744 | else |
69dc4987 CW |
1745 | list_move_tail(&obj_priv->mm_list, &dev_priv->mm.inactive_list); |
1746 | list_del_init(&obj_priv->ring_list); | |
673a394b | 1747 | |
99fcb766 DV |
1748 | BUG_ON(!list_empty(&obj_priv->gpu_write_list)); |
1749 | ||
ce44b0ea | 1750 | obj_priv->last_rendering_seqno = 0; |
852835f3 | 1751 | obj_priv->ring = NULL; |
673a394b EA |
1752 | if (obj_priv->active) { |
1753 | obj_priv->active = 0; | |
1754 | drm_gem_object_unreference(obj); | |
1755 | } | |
23bc5982 | 1756 | WARN_ON(i915_verify_lists(dev)); |
673a394b EA |
1757 | } |
1758 | ||
63560396 DV |
1759 | static void |
1760 | i915_gem_process_flushing_list(struct drm_device *dev, | |
8a1a49f9 | 1761 | uint32_t flush_domains, |
852835f3 | 1762 | struct intel_ring_buffer *ring) |
63560396 DV |
1763 | { |
1764 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1765 | struct drm_i915_gem_object *obj_priv, *next; | |
1766 | ||
1767 | list_for_each_entry_safe(obj_priv, next, | |
64193406 | 1768 | &ring->gpu_write_list, |
63560396 | 1769 | gpu_write_list) { |
a8089e84 | 1770 | struct drm_gem_object *obj = &obj_priv->base; |
63560396 | 1771 | |
64193406 | 1772 | if (obj->write_domain & flush_domains) { |
63560396 DV |
1773 | uint32_t old_write_domain = obj->write_domain; |
1774 | ||
1775 | obj->write_domain = 0; | |
1776 | list_del_init(&obj_priv->gpu_write_list); | |
617dbe27 | 1777 | i915_gem_object_move_to_active(obj, ring); |
63560396 DV |
1778 | |
1779 | /* update the fence lru list */ | |
007cc8ac DV |
1780 | if (obj_priv->fence_reg != I915_FENCE_REG_NONE) { |
1781 | struct drm_i915_fence_reg *reg = | |
1782 | &dev_priv->fence_regs[obj_priv->fence_reg]; | |
1783 | list_move_tail(®->lru_list, | |
63560396 | 1784 | &dev_priv->mm.fence_list); |
007cc8ac | 1785 | } |
63560396 DV |
1786 | |
1787 | trace_i915_gem_object_change_domain(obj, | |
1788 | obj->read_domains, | |
1789 | old_write_domain); | |
1790 | } | |
1791 | } | |
1792 | } | |
8187a2b7 | 1793 | |
3cce469c | 1794 | int |
8a1a49f9 | 1795 | i915_add_request(struct drm_device *dev, |
f787a5f5 | 1796 | struct drm_file *file, |
8dc5d147 | 1797 | struct drm_i915_gem_request *request, |
8a1a49f9 | 1798 | struct intel_ring_buffer *ring) |
673a394b EA |
1799 | { |
1800 | drm_i915_private_t *dev_priv = dev->dev_private; | |
f787a5f5 | 1801 | struct drm_i915_file_private *file_priv = NULL; |
673a394b EA |
1802 | uint32_t seqno; |
1803 | int was_empty; | |
3cce469c CW |
1804 | int ret; |
1805 | ||
1806 | BUG_ON(request == NULL); | |
673a394b | 1807 | |
f787a5f5 CW |
1808 | if (file != NULL) |
1809 | file_priv = file->driver_priv; | |
b962442e | 1810 | |
3cce469c CW |
1811 | ret = ring->add_request(ring, &seqno); |
1812 | if (ret) | |
1813 | return ret; | |
673a394b | 1814 | |
a56ba56c | 1815 | ring->outstanding_lazy_request = false; |
673a394b EA |
1816 | |
1817 | request->seqno = seqno; | |
852835f3 | 1818 | request->ring = ring; |
673a394b | 1819 | request->emitted_jiffies = jiffies; |
852835f3 ZN |
1820 | was_empty = list_empty(&ring->request_list); |
1821 | list_add_tail(&request->list, &ring->request_list); | |
1822 | ||
f787a5f5 | 1823 | if (file_priv) { |
1c25595f | 1824 | spin_lock(&file_priv->mm.lock); |
f787a5f5 | 1825 | request->file_priv = file_priv; |
b962442e | 1826 | list_add_tail(&request->client_list, |
f787a5f5 | 1827 | &file_priv->mm.request_list); |
1c25595f | 1828 | spin_unlock(&file_priv->mm.lock); |
b962442e | 1829 | } |
673a394b | 1830 | |
f65d9421 | 1831 | if (!dev_priv->mm.suspended) { |
b3b079db CW |
1832 | mod_timer(&dev_priv->hangcheck_timer, |
1833 | jiffies + msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)); | |
f65d9421 | 1834 | if (was_empty) |
b3b079db CW |
1835 | queue_delayed_work(dev_priv->wq, |
1836 | &dev_priv->mm.retire_work, HZ); | |
f65d9421 | 1837 | } |
3cce469c | 1838 | return 0; |
673a394b EA |
1839 | } |
1840 | ||
1841 | /** | |
1842 | * Command execution barrier | |
1843 | * | |
1844 | * Ensures that all commands in the ring are finished | |
1845 | * before signalling the CPU | |
1846 | */ | |
8a1a49f9 | 1847 | static void |
852835f3 | 1848 | i915_retire_commands(struct drm_device *dev, struct intel_ring_buffer *ring) |
673a394b | 1849 | { |
673a394b | 1850 | uint32_t flush_domains = 0; |
673a394b EA |
1851 | |
1852 | /* The sampler always gets flushed on i965 (sigh) */ | |
a6c45cf0 | 1853 | if (INTEL_INFO(dev)->gen >= 4) |
673a394b | 1854 | flush_domains |= I915_GEM_DOMAIN_SAMPLER; |
852835f3 | 1855 | |
78501eac | 1856 | ring->flush(ring, I915_GEM_DOMAIN_COMMAND, flush_domains); |
673a394b EA |
1857 | } |
1858 | ||
f787a5f5 CW |
1859 | static inline void |
1860 | i915_gem_request_remove_from_client(struct drm_i915_gem_request *request) | |
673a394b | 1861 | { |
1c25595f | 1862 | struct drm_i915_file_private *file_priv = request->file_priv; |
673a394b | 1863 | |
1c25595f CW |
1864 | if (!file_priv) |
1865 | return; | |
1c5d22f7 | 1866 | |
1c25595f CW |
1867 | spin_lock(&file_priv->mm.lock); |
1868 | list_del(&request->client_list); | |
1869 | request->file_priv = NULL; | |
1870 | spin_unlock(&file_priv->mm.lock); | |
673a394b | 1871 | } |
673a394b | 1872 | |
dfaae392 CW |
1873 | static void i915_gem_reset_ring_lists(struct drm_i915_private *dev_priv, |
1874 | struct intel_ring_buffer *ring) | |
9375e446 | 1875 | { |
dfaae392 CW |
1876 | while (!list_empty(&ring->request_list)) { |
1877 | struct drm_i915_gem_request *request; | |
673a394b | 1878 | |
dfaae392 CW |
1879 | request = list_first_entry(&ring->request_list, |
1880 | struct drm_i915_gem_request, | |
1881 | list); | |
de151cf6 | 1882 | |
dfaae392 | 1883 | list_del(&request->list); |
f787a5f5 | 1884 | i915_gem_request_remove_from_client(request); |
dfaae392 CW |
1885 | kfree(request); |
1886 | } | |
673a394b | 1887 | |
dfaae392 | 1888 | while (!list_empty(&ring->active_list)) { |
9375e446 CW |
1889 | struct drm_i915_gem_object *obj_priv; |
1890 | ||
dfaae392 | 1891 | obj_priv = list_first_entry(&ring->active_list, |
9375e446 | 1892 | struct drm_i915_gem_object, |
69dc4987 | 1893 | ring_list); |
9375e446 CW |
1894 | |
1895 | obj_priv->base.write_domain = 0; | |
dfaae392 | 1896 | list_del_init(&obj_priv->gpu_write_list); |
9375e446 | 1897 | i915_gem_object_move_to_inactive(&obj_priv->base); |
673a394b EA |
1898 | } |
1899 | } | |
1900 | ||
069efc1d | 1901 | void i915_gem_reset(struct drm_device *dev) |
673a394b | 1902 | { |
77f01230 CW |
1903 | struct drm_i915_private *dev_priv = dev->dev_private; |
1904 | struct drm_i915_gem_object *obj_priv; | |
069efc1d | 1905 | int i; |
673a394b | 1906 | |
dfaae392 | 1907 | i915_gem_reset_ring_lists(dev_priv, &dev_priv->render_ring); |
87acb0a5 | 1908 | i915_gem_reset_ring_lists(dev_priv, &dev_priv->bsd_ring); |
549f7365 | 1909 | i915_gem_reset_ring_lists(dev_priv, &dev_priv->blt_ring); |
dfaae392 CW |
1910 | |
1911 | /* Remove anything from the flushing lists. The GPU cache is likely | |
1912 | * to be lost on reset along with the data, so simply move the | |
1913 | * lost bo to the inactive list. | |
1914 | */ | |
1915 | while (!list_empty(&dev_priv->mm.flushing_list)) { | |
1916 | obj_priv = list_first_entry(&dev_priv->mm.flushing_list, | |
1917 | struct drm_i915_gem_object, | |
69dc4987 | 1918 | mm_list); |
dfaae392 CW |
1919 | |
1920 | obj_priv->base.write_domain = 0; | |
1921 | list_del_init(&obj_priv->gpu_write_list); | |
1922 | i915_gem_object_move_to_inactive(&obj_priv->base); | |
1923 | } | |
1924 | ||
1925 | /* Move everything out of the GPU domains to ensure we do any | |
1926 | * necessary invalidation upon reuse. | |
1927 | */ | |
77f01230 CW |
1928 | list_for_each_entry(obj_priv, |
1929 | &dev_priv->mm.inactive_list, | |
69dc4987 | 1930 | mm_list) |
77f01230 CW |
1931 | { |
1932 | obj_priv->base.read_domains &= ~I915_GEM_GPU_DOMAINS; | |
1933 | } | |
069efc1d CW |
1934 | |
1935 | /* The fence registers are invalidated so clear them out */ | |
1936 | for (i = 0; i < 16; i++) { | |
1937 | struct drm_i915_fence_reg *reg; | |
1938 | ||
1939 | reg = &dev_priv->fence_regs[i]; | |
1940 | if (!reg->obj) | |
1941 | continue; | |
1942 | ||
1943 | i915_gem_clear_fence_reg(reg->obj); | |
1944 | } | |
673a394b EA |
1945 | } |
1946 | ||
1947 | /** | |
1948 | * This function clears the request list as sequence numbers are passed. | |
1949 | */ | |
b09a1fec CW |
1950 | static void |
1951 | i915_gem_retire_requests_ring(struct drm_device *dev, | |
1952 | struct intel_ring_buffer *ring) | |
673a394b EA |
1953 | { |
1954 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1955 | uint32_t seqno; | |
1956 | ||
b84d5f0c CW |
1957 | if (!ring->status_page.page_addr || |
1958 | list_empty(&ring->request_list)) | |
6c0594a3 KW |
1959 | return; |
1960 | ||
23bc5982 | 1961 | WARN_ON(i915_verify_lists(dev)); |
673a394b | 1962 | |
78501eac | 1963 | seqno = ring->get_seqno(ring); |
852835f3 | 1964 | while (!list_empty(&ring->request_list)) { |
673a394b | 1965 | struct drm_i915_gem_request *request; |
673a394b | 1966 | |
852835f3 | 1967 | request = list_first_entry(&ring->request_list, |
673a394b EA |
1968 | struct drm_i915_gem_request, |
1969 | list); | |
673a394b | 1970 | |
dfaae392 | 1971 | if (!i915_seqno_passed(seqno, request->seqno)) |
b84d5f0c CW |
1972 | break; |
1973 | ||
1974 | trace_i915_gem_request_retire(dev, request->seqno); | |
1975 | ||
1976 | list_del(&request->list); | |
f787a5f5 | 1977 | i915_gem_request_remove_from_client(request); |
b84d5f0c CW |
1978 | kfree(request); |
1979 | } | |
673a394b | 1980 | |
b84d5f0c CW |
1981 | /* Move any buffers on the active list that are no longer referenced |
1982 | * by the ringbuffer to the flushing/inactive lists as appropriate. | |
1983 | */ | |
1984 | while (!list_empty(&ring->active_list)) { | |
1985 | struct drm_gem_object *obj; | |
1986 | struct drm_i915_gem_object *obj_priv; | |
1987 | ||
1988 | obj_priv = list_first_entry(&ring->active_list, | |
1989 | struct drm_i915_gem_object, | |
69dc4987 | 1990 | ring_list); |
673a394b | 1991 | |
dfaae392 | 1992 | if (!i915_seqno_passed(seqno, obj_priv->last_rendering_seqno)) |
673a394b | 1993 | break; |
b84d5f0c CW |
1994 | |
1995 | obj = &obj_priv->base; | |
b84d5f0c CW |
1996 | if (obj->write_domain != 0) |
1997 | i915_gem_object_move_to_flushing(obj); | |
1998 | else | |
1999 | i915_gem_object_move_to_inactive(obj); | |
673a394b | 2000 | } |
9d34e5db CW |
2001 | |
2002 | if (unlikely (dev_priv->trace_irq_seqno && | |
2003 | i915_seqno_passed(dev_priv->trace_irq_seqno, seqno))) { | |
78501eac | 2004 | ring->user_irq_put(ring); |
9d34e5db CW |
2005 | dev_priv->trace_irq_seqno = 0; |
2006 | } | |
23bc5982 CW |
2007 | |
2008 | WARN_ON(i915_verify_lists(dev)); | |
673a394b EA |
2009 | } |
2010 | ||
b09a1fec CW |
2011 | void |
2012 | i915_gem_retire_requests(struct drm_device *dev) | |
2013 | { | |
2014 | drm_i915_private_t *dev_priv = dev->dev_private; | |
2015 | ||
be72615b CW |
2016 | if (!list_empty(&dev_priv->mm.deferred_free_list)) { |
2017 | struct drm_i915_gem_object *obj_priv, *tmp; | |
2018 | ||
2019 | /* We must be careful that during unbind() we do not | |
2020 | * accidentally infinitely recurse into retire requests. | |
2021 | * Currently: | |
2022 | * retire -> free -> unbind -> wait -> retire_ring | |
2023 | */ | |
2024 | list_for_each_entry_safe(obj_priv, tmp, | |
2025 | &dev_priv->mm.deferred_free_list, | |
69dc4987 | 2026 | mm_list) |
be72615b CW |
2027 | i915_gem_free_object_tail(&obj_priv->base); |
2028 | } | |
2029 | ||
b09a1fec | 2030 | i915_gem_retire_requests_ring(dev, &dev_priv->render_ring); |
87acb0a5 | 2031 | i915_gem_retire_requests_ring(dev, &dev_priv->bsd_ring); |
549f7365 | 2032 | i915_gem_retire_requests_ring(dev, &dev_priv->blt_ring); |
b09a1fec CW |
2033 | } |
2034 | ||
75ef9da2 | 2035 | static void |
673a394b EA |
2036 | i915_gem_retire_work_handler(struct work_struct *work) |
2037 | { | |
2038 | drm_i915_private_t *dev_priv; | |
2039 | struct drm_device *dev; | |
2040 | ||
2041 | dev_priv = container_of(work, drm_i915_private_t, | |
2042 | mm.retire_work.work); | |
2043 | dev = dev_priv->dev; | |
2044 | ||
891b48cf CW |
2045 | /* Come back later if the device is busy... */ |
2046 | if (!mutex_trylock(&dev->struct_mutex)) { | |
2047 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ); | |
2048 | return; | |
2049 | } | |
2050 | ||
b09a1fec | 2051 | i915_gem_retire_requests(dev); |
d1b851fc | 2052 | |
6dbe2772 | 2053 | if (!dev_priv->mm.suspended && |
d1b851fc | 2054 | (!list_empty(&dev_priv->render_ring.request_list) || |
549f7365 CW |
2055 | !list_empty(&dev_priv->bsd_ring.request_list) || |
2056 | !list_empty(&dev_priv->blt_ring.request_list))) | |
9c9fe1f8 | 2057 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ); |
673a394b EA |
2058 | mutex_unlock(&dev->struct_mutex); |
2059 | } | |
2060 | ||
5a5a0c64 | 2061 | int |
852835f3 | 2062 | i915_do_wait_request(struct drm_device *dev, uint32_t seqno, |
8a1a49f9 | 2063 | bool interruptible, struct intel_ring_buffer *ring) |
673a394b EA |
2064 | { |
2065 | drm_i915_private_t *dev_priv = dev->dev_private; | |
802c7eb6 | 2066 | u32 ier; |
673a394b EA |
2067 | int ret = 0; |
2068 | ||
2069 | BUG_ON(seqno == 0); | |
2070 | ||
ba1234d1 | 2071 | if (atomic_read(&dev_priv->mm.wedged)) |
30dbf0c0 CW |
2072 | return -EAGAIN; |
2073 | ||
a56ba56c | 2074 | if (ring->outstanding_lazy_request) { |
3cce469c CW |
2075 | struct drm_i915_gem_request *request; |
2076 | ||
2077 | request = kzalloc(sizeof(*request), GFP_KERNEL); | |
2078 | if (request == NULL) | |
e35a41de | 2079 | return -ENOMEM; |
3cce469c CW |
2080 | |
2081 | ret = i915_add_request(dev, NULL, request, ring); | |
2082 | if (ret) { | |
2083 | kfree(request); | |
2084 | return ret; | |
2085 | } | |
2086 | ||
2087 | seqno = request->seqno; | |
e35a41de | 2088 | } |
a56ba56c | 2089 | BUG_ON(seqno == dev_priv->next_seqno); |
ffed1d09 | 2090 | |
78501eac | 2091 | if (!i915_seqno_passed(ring->get_seqno(ring), seqno)) { |
bad720ff | 2092 | if (HAS_PCH_SPLIT(dev)) |
036a4a7d ZW |
2093 | ier = I915_READ(DEIER) | I915_READ(GTIER); |
2094 | else | |
2095 | ier = I915_READ(IER); | |
802c7eb6 JB |
2096 | if (!ier) { |
2097 | DRM_ERROR("something (likely vbetool) disabled " | |
2098 | "interrupts, re-enabling\n"); | |
2099 | i915_driver_irq_preinstall(dev); | |
2100 | i915_driver_irq_postinstall(dev); | |
2101 | } | |
2102 | ||
1c5d22f7 CW |
2103 | trace_i915_gem_request_wait_begin(dev, seqno); |
2104 | ||
b2223497 | 2105 | ring->waiting_seqno = seqno; |
78501eac | 2106 | ring->user_irq_get(ring); |
48764bf4 | 2107 | if (interruptible) |
852835f3 | 2108 | ret = wait_event_interruptible(ring->irq_queue, |
78501eac | 2109 | i915_seqno_passed(ring->get_seqno(ring), seqno) |
852835f3 | 2110 | || atomic_read(&dev_priv->mm.wedged)); |
48764bf4 | 2111 | else |
852835f3 | 2112 | wait_event(ring->irq_queue, |
78501eac | 2113 | i915_seqno_passed(ring->get_seqno(ring), seqno) |
852835f3 | 2114 | || atomic_read(&dev_priv->mm.wedged)); |
48764bf4 | 2115 | |
78501eac | 2116 | ring->user_irq_put(ring); |
b2223497 | 2117 | ring->waiting_seqno = 0; |
1c5d22f7 CW |
2118 | |
2119 | trace_i915_gem_request_wait_end(dev, seqno); | |
673a394b | 2120 | } |
ba1234d1 | 2121 | if (atomic_read(&dev_priv->mm.wedged)) |
30dbf0c0 | 2122 | ret = -EAGAIN; |
673a394b EA |
2123 | |
2124 | if (ret && ret != -ERESTARTSYS) | |
8bff917c | 2125 | DRM_ERROR("%s returns %d (awaiting %d at %d, next %d)\n", |
78501eac | 2126 | __func__, ret, seqno, ring->get_seqno(ring), |
8bff917c | 2127 | dev_priv->next_seqno); |
673a394b EA |
2128 | |
2129 | /* Directly dispatch request retiring. While we have the work queue | |
2130 | * to handle this, the waiter on a request often wants an associated | |
2131 | * buffer to have made it to the inactive list, and we would need | |
2132 | * a separate wait queue to handle that. | |
2133 | */ | |
2134 | if (ret == 0) | |
b09a1fec | 2135 | i915_gem_retire_requests_ring(dev, ring); |
673a394b EA |
2136 | |
2137 | return ret; | |
2138 | } | |
2139 | ||
48764bf4 DV |
2140 | /** |
2141 | * Waits for a sequence number to be signaled, and cleans up the | |
2142 | * request and object lists appropriately for that event. | |
2143 | */ | |
2144 | static int | |
852835f3 | 2145 | i915_wait_request(struct drm_device *dev, uint32_t seqno, |
a56ba56c | 2146 | struct intel_ring_buffer *ring) |
48764bf4 | 2147 | { |
852835f3 | 2148 | return i915_do_wait_request(dev, seqno, 1, ring); |
48764bf4 DV |
2149 | } |
2150 | ||
20f0cd55 | 2151 | static void |
9220434a | 2152 | i915_gem_flush_ring(struct drm_device *dev, |
c78ec30b | 2153 | struct drm_file *file_priv, |
9220434a CW |
2154 | struct intel_ring_buffer *ring, |
2155 | uint32_t invalidate_domains, | |
2156 | uint32_t flush_domains) | |
2157 | { | |
78501eac | 2158 | ring->flush(ring, invalidate_domains, flush_domains); |
9220434a CW |
2159 | i915_gem_process_flushing_list(dev, flush_domains, ring); |
2160 | } | |
2161 | ||
8187a2b7 ZN |
2162 | static void |
2163 | i915_gem_flush(struct drm_device *dev, | |
c78ec30b | 2164 | struct drm_file *file_priv, |
8187a2b7 | 2165 | uint32_t invalidate_domains, |
9220434a CW |
2166 | uint32_t flush_domains, |
2167 | uint32_t flush_rings) | |
8187a2b7 ZN |
2168 | { |
2169 | drm_i915_private_t *dev_priv = dev->dev_private; | |
8bff917c | 2170 | |
8187a2b7 ZN |
2171 | if (flush_domains & I915_GEM_DOMAIN_CPU) |
2172 | drm_agp_chipset_flush(dev); | |
8bff917c | 2173 | |
9220434a CW |
2174 | if ((flush_domains | invalidate_domains) & I915_GEM_GPU_DOMAINS) { |
2175 | if (flush_rings & RING_RENDER) | |
c78ec30b | 2176 | i915_gem_flush_ring(dev, file_priv, |
9220434a CW |
2177 | &dev_priv->render_ring, |
2178 | invalidate_domains, flush_domains); | |
2179 | if (flush_rings & RING_BSD) | |
c78ec30b | 2180 | i915_gem_flush_ring(dev, file_priv, |
9220434a CW |
2181 | &dev_priv->bsd_ring, |
2182 | invalidate_domains, flush_domains); | |
549f7365 CW |
2183 | if (flush_rings & RING_BLT) |
2184 | i915_gem_flush_ring(dev, file_priv, | |
2185 | &dev_priv->blt_ring, | |
2186 | invalidate_domains, flush_domains); | |
9220434a | 2187 | } |
8187a2b7 ZN |
2188 | } |
2189 | ||
673a394b EA |
2190 | /** |
2191 | * Ensures that all rendering to the object has completed and the object is | |
2192 | * safe to unbind from the GTT or access from the CPU. | |
2193 | */ | |
2194 | static int | |
2cf34d7b CW |
2195 | i915_gem_object_wait_rendering(struct drm_gem_object *obj, |
2196 | bool interruptible) | |
673a394b EA |
2197 | { |
2198 | struct drm_device *dev = obj->dev; | |
23010e43 | 2199 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
673a394b EA |
2200 | int ret; |
2201 | ||
e47c68e9 EA |
2202 | /* This function only exists to support waiting for existing rendering, |
2203 | * not for emitting required flushes. | |
673a394b | 2204 | */ |
e47c68e9 | 2205 | BUG_ON((obj->write_domain & I915_GEM_GPU_DOMAINS) != 0); |
673a394b EA |
2206 | |
2207 | /* If there is rendering queued on the buffer being evicted, wait for | |
2208 | * it. | |
2209 | */ | |
2210 | if (obj_priv->active) { | |
2cf34d7b CW |
2211 | ret = i915_do_wait_request(dev, |
2212 | obj_priv->last_rendering_seqno, | |
2213 | interruptible, | |
2214 | obj_priv->ring); | |
2215 | if (ret) | |
673a394b EA |
2216 | return ret; |
2217 | } | |
2218 | ||
2219 | return 0; | |
2220 | } | |
2221 | ||
2222 | /** | |
2223 | * Unbinds an object from the GTT aperture. | |
2224 | */ | |
0f973f27 | 2225 | int |
673a394b EA |
2226 | i915_gem_object_unbind(struct drm_gem_object *obj) |
2227 | { | |
2228 | struct drm_device *dev = obj->dev; | |
73aa808f | 2229 | struct drm_i915_private *dev_priv = dev->dev_private; |
23010e43 | 2230 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
673a394b EA |
2231 | int ret = 0; |
2232 | ||
673a394b EA |
2233 | if (obj_priv->gtt_space == NULL) |
2234 | return 0; | |
2235 | ||
2236 | if (obj_priv->pin_count != 0) { | |
2237 | DRM_ERROR("Attempting to unbind pinned buffer\n"); | |
2238 | return -EINVAL; | |
2239 | } | |
2240 | ||
5323fd04 EA |
2241 | /* blow away mappings if mapped through GTT */ |
2242 | i915_gem_release_mmap(obj); | |
2243 | ||
673a394b EA |
2244 | /* Move the object to the CPU domain to ensure that |
2245 | * any possible CPU writes while it's not in the GTT | |
2246 | * are flushed when we go to remap it. This will | |
2247 | * also ensure that all pending GPU writes are finished | |
2248 | * before we unbind. | |
2249 | */ | |
e47c68e9 | 2250 | ret = i915_gem_object_set_to_cpu_domain(obj, 1); |
8dc1775d | 2251 | if (ret == -ERESTARTSYS) |
673a394b | 2252 | return ret; |
8dc1775d CW |
2253 | /* Continue on if we fail due to EIO, the GPU is hung so we |
2254 | * should be safe and we need to cleanup or else we might | |
2255 | * cause memory corruption through use-after-free. | |
2256 | */ | |
812ed492 CW |
2257 | if (ret) { |
2258 | i915_gem_clflush_object(obj); | |
2259 | obj->read_domains = obj->write_domain = I915_GEM_DOMAIN_CPU; | |
2260 | } | |
673a394b | 2261 | |
96b47b65 DV |
2262 | /* release the fence reg _after_ flushing */ |
2263 | if (obj_priv->fence_reg != I915_FENCE_REG_NONE) | |
2264 | i915_gem_clear_fence_reg(obj); | |
2265 | ||
73aa808f CW |
2266 | drm_unbind_agp(obj_priv->agp_mem); |
2267 | drm_free_agp(obj_priv->agp_mem, obj->size / PAGE_SIZE); | |
673a394b | 2268 | |
e5281ccd | 2269 | i915_gem_object_put_pages_gtt(obj); |
673a394b | 2270 | |
a00b10c3 | 2271 | i915_gem_info_remove_gtt(dev_priv, obj_priv); |
69dc4987 | 2272 | list_del_init(&obj_priv->mm_list); |
75e9e915 DV |
2273 | /* Avoid an unnecessary call to unbind on rebind. */ |
2274 | obj_priv->map_and_fenceable = true; | |
673a394b | 2275 | |
73aa808f CW |
2276 | drm_mm_put_block(obj_priv->gtt_space); |
2277 | obj_priv->gtt_space = NULL; | |
9af90d19 | 2278 | obj_priv->gtt_offset = 0; |
673a394b | 2279 | |
963b4836 CW |
2280 | if (i915_gem_object_is_purgeable(obj_priv)) |
2281 | i915_gem_object_truncate(obj); | |
2282 | ||
1c5d22f7 CW |
2283 | trace_i915_gem_object_unbind(obj); |
2284 | ||
8dc1775d | 2285 | return ret; |
673a394b EA |
2286 | } |
2287 | ||
a56ba56c CW |
2288 | static int i915_ring_idle(struct drm_device *dev, |
2289 | struct intel_ring_buffer *ring) | |
2290 | { | |
395b70be | 2291 | if (list_empty(&ring->gpu_write_list) && list_empty(&ring->active_list)) |
64193406 CW |
2292 | return 0; |
2293 | ||
a56ba56c CW |
2294 | i915_gem_flush_ring(dev, NULL, ring, |
2295 | I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS); | |
2296 | return i915_wait_request(dev, | |
2297 | i915_gem_next_request_seqno(dev, ring), | |
2298 | ring); | |
2299 | } | |
2300 | ||
b47eb4a2 | 2301 | int |
4df2faf4 DV |
2302 | i915_gpu_idle(struct drm_device *dev) |
2303 | { | |
2304 | drm_i915_private_t *dev_priv = dev->dev_private; | |
2305 | bool lists_empty; | |
852835f3 | 2306 | int ret; |
4df2faf4 | 2307 | |
d1b851fc | 2308 | lists_empty = (list_empty(&dev_priv->mm.flushing_list) && |
395b70be | 2309 | list_empty(&dev_priv->mm.active_list)); |
4df2faf4 DV |
2310 | if (lists_empty) |
2311 | return 0; | |
2312 | ||
2313 | /* Flush everything onto the inactive list. */ | |
a56ba56c | 2314 | ret = i915_ring_idle(dev, &dev_priv->render_ring); |
8a1a49f9 DV |
2315 | if (ret) |
2316 | return ret; | |
d1b851fc | 2317 | |
87acb0a5 CW |
2318 | ret = i915_ring_idle(dev, &dev_priv->bsd_ring); |
2319 | if (ret) | |
2320 | return ret; | |
d1b851fc | 2321 | |
549f7365 CW |
2322 | ret = i915_ring_idle(dev, &dev_priv->blt_ring); |
2323 | if (ret) | |
2324 | return ret; | |
4df2faf4 | 2325 | |
8a1a49f9 | 2326 | return 0; |
4df2faf4 DV |
2327 | } |
2328 | ||
a00b10c3 | 2329 | static void sandybridge_write_fence_reg(struct drm_gem_object *obj) |
4e901fdc | 2330 | { |
4e901fdc EA |
2331 | struct drm_device *dev = obj->dev; |
2332 | drm_i915_private_t *dev_priv = dev->dev_private; | |
23010e43 | 2333 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
a00b10c3 | 2334 | u32 size = i915_gem_get_gtt_size(obj_priv); |
4e901fdc EA |
2335 | int regnum = obj_priv->fence_reg; |
2336 | uint64_t val; | |
2337 | ||
a00b10c3 | 2338 | val = (uint64_t)((obj_priv->gtt_offset + size - 4096) & |
4e901fdc EA |
2339 | 0xfffff000) << 32; |
2340 | val |= obj_priv->gtt_offset & 0xfffff000; | |
2341 | val |= (uint64_t)((obj_priv->stride / 128) - 1) << | |
2342 | SANDYBRIDGE_FENCE_PITCH_SHIFT; | |
2343 | ||
2344 | if (obj_priv->tiling_mode == I915_TILING_Y) | |
2345 | val |= 1 << I965_FENCE_TILING_Y_SHIFT; | |
2346 | val |= I965_FENCE_REG_VALID; | |
2347 | ||
2348 | I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + (regnum * 8), val); | |
2349 | } | |
2350 | ||
a00b10c3 | 2351 | static void i965_write_fence_reg(struct drm_gem_object *obj) |
de151cf6 | 2352 | { |
de151cf6 JB |
2353 | struct drm_device *dev = obj->dev; |
2354 | drm_i915_private_t *dev_priv = dev->dev_private; | |
23010e43 | 2355 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
a00b10c3 | 2356 | u32 size = i915_gem_get_gtt_size(obj_priv); |
de151cf6 JB |
2357 | int regnum = obj_priv->fence_reg; |
2358 | uint64_t val; | |
2359 | ||
a00b10c3 | 2360 | val = (uint64_t)((obj_priv->gtt_offset + size - 4096) & |
de151cf6 JB |
2361 | 0xfffff000) << 32; |
2362 | val |= obj_priv->gtt_offset & 0xfffff000; | |
2363 | val |= ((obj_priv->stride / 128) - 1) << I965_FENCE_PITCH_SHIFT; | |
2364 | if (obj_priv->tiling_mode == I915_TILING_Y) | |
2365 | val |= 1 << I965_FENCE_TILING_Y_SHIFT; | |
2366 | val |= I965_FENCE_REG_VALID; | |
2367 | ||
2368 | I915_WRITE64(FENCE_REG_965_0 + (regnum * 8), val); | |
2369 | } | |
2370 | ||
a00b10c3 | 2371 | static void i915_write_fence_reg(struct drm_gem_object *obj) |
de151cf6 | 2372 | { |
de151cf6 JB |
2373 | struct drm_device *dev = obj->dev; |
2374 | drm_i915_private_t *dev_priv = dev->dev_private; | |
23010e43 | 2375 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
a00b10c3 CW |
2376 | u32 size = i915_gem_get_gtt_size(obj_priv); |
2377 | uint32_t fence_reg, val, pitch_val; | |
0f973f27 | 2378 | int tile_width; |
de151cf6 JB |
2379 | |
2380 | if ((obj_priv->gtt_offset & ~I915_FENCE_START_MASK) || | |
a00b10c3 CW |
2381 | (obj_priv->gtt_offset & (size - 1))) { |
2382 | WARN(1, "%s: object 0x%08x [fenceable? %d] not 1M or size (0x%08x) aligned [gtt_space offset=%lx, size=%lx]\n", | |
75e9e915 | 2383 | __func__, obj_priv->gtt_offset, obj_priv->map_and_fenceable, size, |
a00b10c3 | 2384 | obj_priv->gtt_space->start, obj_priv->gtt_space->size); |
de151cf6 JB |
2385 | return; |
2386 | } | |
2387 | ||
0f973f27 JB |
2388 | if (obj_priv->tiling_mode == I915_TILING_Y && |
2389 | HAS_128_BYTE_Y_TILING(dev)) | |
2390 | tile_width = 128; | |
de151cf6 | 2391 | else |
0f973f27 JB |
2392 | tile_width = 512; |
2393 | ||
2394 | /* Note: pitch better be a power of two tile widths */ | |
2395 | pitch_val = obj_priv->stride / tile_width; | |
2396 | pitch_val = ffs(pitch_val) - 1; | |
de151cf6 | 2397 | |
c36a2a6d DV |
2398 | if (obj_priv->tiling_mode == I915_TILING_Y && |
2399 | HAS_128_BYTE_Y_TILING(dev)) | |
2400 | WARN_ON(pitch_val > I830_FENCE_MAX_PITCH_VAL); | |
2401 | else | |
2402 | WARN_ON(pitch_val > I915_FENCE_MAX_PITCH_VAL); | |
2403 | ||
de151cf6 JB |
2404 | val = obj_priv->gtt_offset; |
2405 | if (obj_priv->tiling_mode == I915_TILING_Y) | |
2406 | val |= 1 << I830_FENCE_TILING_Y_SHIFT; | |
a00b10c3 | 2407 | val |= I915_FENCE_SIZE_BITS(size); |
de151cf6 JB |
2408 | val |= pitch_val << I830_FENCE_PITCH_SHIFT; |
2409 | val |= I830_FENCE_REG_VALID; | |
2410 | ||
a00b10c3 CW |
2411 | fence_reg = obj_priv->fence_reg; |
2412 | if (fence_reg < 8) | |
2413 | fence_reg = FENCE_REG_830_0 + fence_reg * 4; | |
dc529a4f | 2414 | else |
a00b10c3 | 2415 | fence_reg = FENCE_REG_945_8 + (fence_reg - 8) * 4; |
dc529a4f | 2416 | I915_WRITE(fence_reg, val); |
de151cf6 JB |
2417 | } |
2418 | ||
a00b10c3 | 2419 | static void i830_write_fence_reg(struct drm_gem_object *obj) |
de151cf6 | 2420 | { |
de151cf6 JB |
2421 | struct drm_device *dev = obj->dev; |
2422 | drm_i915_private_t *dev_priv = dev->dev_private; | |
23010e43 | 2423 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
a00b10c3 | 2424 | u32 size = i915_gem_get_gtt_size(obj_priv); |
de151cf6 JB |
2425 | int regnum = obj_priv->fence_reg; |
2426 | uint32_t val; | |
2427 | uint32_t pitch_val; | |
8d7773a3 | 2428 | uint32_t fence_size_bits; |
de151cf6 | 2429 | |
8d7773a3 | 2430 | if ((obj_priv->gtt_offset & ~I830_FENCE_START_MASK) || |
de151cf6 | 2431 | (obj_priv->gtt_offset & (obj->size - 1))) { |
8d7773a3 | 2432 | WARN(1, "%s: object 0x%08x not 512K or size aligned\n", |
0f973f27 | 2433 | __func__, obj_priv->gtt_offset); |
de151cf6 JB |
2434 | return; |
2435 | } | |
2436 | ||
e76a16de EA |
2437 | pitch_val = obj_priv->stride / 128; |
2438 | pitch_val = ffs(pitch_val) - 1; | |
2439 | WARN_ON(pitch_val > I830_FENCE_MAX_PITCH_VAL); | |
2440 | ||
de151cf6 JB |
2441 | val = obj_priv->gtt_offset; |
2442 | if (obj_priv->tiling_mode == I915_TILING_Y) | |
2443 | val |= 1 << I830_FENCE_TILING_Y_SHIFT; | |
a00b10c3 | 2444 | fence_size_bits = I830_FENCE_SIZE_BITS(size); |
8d7773a3 DV |
2445 | WARN_ON(fence_size_bits & ~0x00000f00); |
2446 | val |= fence_size_bits; | |
de151cf6 JB |
2447 | val |= pitch_val << I830_FENCE_PITCH_SHIFT; |
2448 | val |= I830_FENCE_REG_VALID; | |
2449 | ||
2450 | I915_WRITE(FENCE_REG_830_0 + (regnum * 4), val); | |
de151cf6 JB |
2451 | } |
2452 | ||
2cf34d7b CW |
2453 | static int i915_find_fence_reg(struct drm_device *dev, |
2454 | bool interruptible) | |
ae3db24a | 2455 | { |
ae3db24a | 2456 | struct drm_i915_private *dev_priv = dev->dev_private; |
a00b10c3 CW |
2457 | struct drm_i915_fence_reg *reg; |
2458 | struct drm_i915_gem_object *obj_priv = NULL; | |
ae3db24a DV |
2459 | int i, avail, ret; |
2460 | ||
2461 | /* First try to find a free reg */ | |
2462 | avail = 0; | |
2463 | for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) { | |
2464 | reg = &dev_priv->fence_regs[i]; | |
2465 | if (!reg->obj) | |
2466 | return i; | |
2467 | ||
23010e43 | 2468 | obj_priv = to_intel_bo(reg->obj); |
ae3db24a DV |
2469 | if (!obj_priv->pin_count) |
2470 | avail++; | |
2471 | } | |
2472 | ||
2473 | if (avail == 0) | |
2474 | return -ENOSPC; | |
2475 | ||
2476 | /* None available, try to steal one or wait for a user to finish */ | |
a00b10c3 | 2477 | avail = I915_FENCE_REG_NONE; |
007cc8ac DV |
2478 | list_for_each_entry(reg, &dev_priv->mm.fence_list, |
2479 | lru_list) { | |
a00b10c3 | 2480 | obj_priv = to_intel_bo(reg->obj); |
ae3db24a DV |
2481 | if (obj_priv->pin_count) |
2482 | continue; | |
2483 | ||
2484 | /* found one! */ | |
a00b10c3 | 2485 | avail = obj_priv->fence_reg; |
ae3db24a DV |
2486 | break; |
2487 | } | |
2488 | ||
a00b10c3 | 2489 | BUG_ON(avail == I915_FENCE_REG_NONE); |
ae3db24a DV |
2490 | |
2491 | /* We only have a reference on obj from the active list. put_fence_reg | |
2492 | * might drop that one, causing a use-after-free in it. So hold a | |
2493 | * private reference to obj like the other callers of put_fence_reg | |
2494 | * (set_tiling ioctl) do. */ | |
a00b10c3 CW |
2495 | drm_gem_object_reference(&obj_priv->base); |
2496 | ret = i915_gem_object_put_fence_reg(&obj_priv->base, interruptible); | |
2497 | drm_gem_object_unreference(&obj_priv->base); | |
ae3db24a DV |
2498 | if (ret != 0) |
2499 | return ret; | |
2500 | ||
a00b10c3 | 2501 | return avail; |
ae3db24a DV |
2502 | } |
2503 | ||
de151cf6 JB |
2504 | /** |
2505 | * i915_gem_object_get_fence_reg - set up a fence reg for an object | |
2506 | * @obj: object to map through a fence reg | |
2507 | * | |
2508 | * When mapping objects through the GTT, userspace wants to be able to write | |
2509 | * to them without having to worry about swizzling if the object is tiled. | |
2510 | * | |
2511 | * This function walks the fence regs looking for a free one for @obj, | |
2512 | * stealing one if it can't find any. | |
2513 | * | |
2514 | * It then sets up the reg based on the object's properties: address, pitch | |
2515 | * and tiling format. | |
2516 | */ | |
8c4b8c3f | 2517 | int |
2cf34d7b CW |
2518 | i915_gem_object_get_fence_reg(struct drm_gem_object *obj, |
2519 | bool interruptible) | |
de151cf6 JB |
2520 | { |
2521 | struct drm_device *dev = obj->dev; | |
79e53945 | 2522 | struct drm_i915_private *dev_priv = dev->dev_private; |
23010e43 | 2523 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
de151cf6 | 2524 | struct drm_i915_fence_reg *reg = NULL; |
ae3db24a | 2525 | int ret; |
de151cf6 | 2526 | |
a09ba7fa EA |
2527 | /* Just update our place in the LRU if our fence is getting used. */ |
2528 | if (obj_priv->fence_reg != I915_FENCE_REG_NONE) { | |
007cc8ac DV |
2529 | reg = &dev_priv->fence_regs[obj_priv->fence_reg]; |
2530 | list_move_tail(®->lru_list, &dev_priv->mm.fence_list); | |
a09ba7fa EA |
2531 | return 0; |
2532 | } | |
2533 | ||
de151cf6 JB |
2534 | switch (obj_priv->tiling_mode) { |
2535 | case I915_TILING_NONE: | |
2536 | WARN(1, "allocating a fence for non-tiled object?\n"); | |
2537 | break; | |
2538 | case I915_TILING_X: | |
0f973f27 JB |
2539 | if (!obj_priv->stride) |
2540 | return -EINVAL; | |
2541 | WARN((obj_priv->stride & (512 - 1)), | |
2542 | "object 0x%08x is X tiled but has non-512B pitch\n", | |
2543 | obj_priv->gtt_offset); | |
de151cf6 JB |
2544 | break; |
2545 | case I915_TILING_Y: | |
0f973f27 JB |
2546 | if (!obj_priv->stride) |
2547 | return -EINVAL; | |
2548 | WARN((obj_priv->stride & (128 - 1)), | |
2549 | "object 0x%08x is Y tiled but has non-128B pitch\n", | |
2550 | obj_priv->gtt_offset); | |
de151cf6 JB |
2551 | break; |
2552 | } | |
2553 | ||
2cf34d7b | 2554 | ret = i915_find_fence_reg(dev, interruptible); |
ae3db24a DV |
2555 | if (ret < 0) |
2556 | return ret; | |
de151cf6 | 2557 | |
ae3db24a DV |
2558 | obj_priv->fence_reg = ret; |
2559 | reg = &dev_priv->fence_regs[obj_priv->fence_reg]; | |
007cc8ac | 2560 | list_add_tail(®->lru_list, &dev_priv->mm.fence_list); |
a09ba7fa | 2561 | |
de151cf6 JB |
2562 | reg->obj = obj; |
2563 | ||
e259befd CW |
2564 | switch (INTEL_INFO(dev)->gen) { |
2565 | case 6: | |
a00b10c3 | 2566 | sandybridge_write_fence_reg(obj); |
e259befd CW |
2567 | break; |
2568 | case 5: | |
2569 | case 4: | |
a00b10c3 | 2570 | i965_write_fence_reg(obj); |
e259befd CW |
2571 | break; |
2572 | case 3: | |
a00b10c3 | 2573 | i915_write_fence_reg(obj); |
e259befd CW |
2574 | break; |
2575 | case 2: | |
a00b10c3 | 2576 | i830_write_fence_reg(obj); |
e259befd CW |
2577 | break; |
2578 | } | |
d9ddcb96 | 2579 | |
a00b10c3 CW |
2580 | trace_i915_gem_object_get_fence(obj, |
2581 | obj_priv->fence_reg, | |
2582 | obj_priv->tiling_mode); | |
1c5d22f7 | 2583 | |
d9ddcb96 | 2584 | return 0; |
de151cf6 JB |
2585 | } |
2586 | ||
2587 | /** | |
2588 | * i915_gem_clear_fence_reg - clear out fence register info | |
2589 | * @obj: object to clear | |
2590 | * | |
2591 | * Zeroes out the fence register itself and clears out the associated | |
2592 | * data structures in dev_priv and obj_priv. | |
2593 | */ | |
2594 | static void | |
2595 | i915_gem_clear_fence_reg(struct drm_gem_object *obj) | |
2596 | { | |
2597 | struct drm_device *dev = obj->dev; | |
79e53945 | 2598 | drm_i915_private_t *dev_priv = dev->dev_private; |
23010e43 | 2599 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
007cc8ac DV |
2600 | struct drm_i915_fence_reg *reg = |
2601 | &dev_priv->fence_regs[obj_priv->fence_reg]; | |
e259befd | 2602 | uint32_t fence_reg; |
de151cf6 | 2603 | |
e259befd CW |
2604 | switch (INTEL_INFO(dev)->gen) { |
2605 | case 6: | |
4e901fdc EA |
2606 | I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + |
2607 | (obj_priv->fence_reg * 8), 0); | |
e259befd CW |
2608 | break; |
2609 | case 5: | |
2610 | case 4: | |
de151cf6 | 2611 | I915_WRITE64(FENCE_REG_965_0 + (obj_priv->fence_reg * 8), 0); |
e259befd CW |
2612 | break; |
2613 | case 3: | |
9b74f734 | 2614 | if (obj_priv->fence_reg >= 8) |
e259befd | 2615 | fence_reg = FENCE_REG_945_8 + (obj_priv->fence_reg - 8) * 4; |
dc529a4f | 2616 | else |
e259befd CW |
2617 | case 2: |
2618 | fence_reg = FENCE_REG_830_0 + obj_priv->fence_reg * 4; | |
dc529a4f EA |
2619 | |
2620 | I915_WRITE(fence_reg, 0); | |
e259befd | 2621 | break; |
dc529a4f | 2622 | } |
de151cf6 | 2623 | |
007cc8ac | 2624 | reg->obj = NULL; |
de151cf6 | 2625 | obj_priv->fence_reg = I915_FENCE_REG_NONE; |
007cc8ac | 2626 | list_del_init(®->lru_list); |
de151cf6 JB |
2627 | } |
2628 | ||
52dc7d32 CW |
2629 | /** |
2630 | * i915_gem_object_put_fence_reg - waits on outstanding fenced access | |
2631 | * to the buffer to finish, and then resets the fence register. | |
2632 | * @obj: tiled object holding a fence register. | |
2cf34d7b | 2633 | * @bool: whether the wait upon the fence is interruptible |
52dc7d32 CW |
2634 | * |
2635 | * Zeroes out the fence register itself and clears out the associated | |
2636 | * data structures in dev_priv and obj_priv. | |
2637 | */ | |
2638 | int | |
2cf34d7b CW |
2639 | i915_gem_object_put_fence_reg(struct drm_gem_object *obj, |
2640 | bool interruptible) | |
52dc7d32 CW |
2641 | { |
2642 | struct drm_device *dev = obj->dev; | |
53640e1d | 2643 | struct drm_i915_private *dev_priv = dev->dev_private; |
23010e43 | 2644 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
53640e1d | 2645 | struct drm_i915_fence_reg *reg; |
52dc7d32 CW |
2646 | |
2647 | if (obj_priv->fence_reg == I915_FENCE_REG_NONE) | |
2648 | return 0; | |
2649 | ||
10ae9bd2 DV |
2650 | /* If we've changed tiling, GTT-mappings of the object |
2651 | * need to re-fault to ensure that the correct fence register | |
2652 | * setup is in place. | |
2653 | */ | |
2654 | i915_gem_release_mmap(obj); | |
2655 | ||
52dc7d32 CW |
2656 | /* On the i915, GPU access to tiled buffers is via a fence, |
2657 | * therefore we must wait for any outstanding access to complete | |
2658 | * before clearing the fence. | |
2659 | */ | |
53640e1d CW |
2660 | reg = &dev_priv->fence_regs[obj_priv->fence_reg]; |
2661 | if (reg->gpu) { | |
52dc7d32 CW |
2662 | int ret; |
2663 | ||
2cf34d7b | 2664 | ret = i915_gem_object_flush_gpu_write_domain(obj, true); |
0bc23aad | 2665 | if (ret) |
2dafb1e0 CW |
2666 | return ret; |
2667 | ||
2cf34d7b | 2668 | ret = i915_gem_object_wait_rendering(obj, interruptible); |
0bc23aad | 2669 | if (ret) |
52dc7d32 | 2670 | return ret; |
53640e1d CW |
2671 | |
2672 | reg->gpu = false; | |
52dc7d32 CW |
2673 | } |
2674 | ||
4a726612 | 2675 | i915_gem_object_flush_gtt_write_domain(obj); |
0bc23aad | 2676 | i915_gem_clear_fence_reg(obj); |
52dc7d32 CW |
2677 | |
2678 | return 0; | |
2679 | } | |
2680 | ||
673a394b EA |
2681 | /** |
2682 | * Finds free space in the GTT aperture and binds the object there. | |
2683 | */ | |
2684 | static int | |
920afa77 DV |
2685 | i915_gem_object_bind_to_gtt(struct drm_gem_object *obj, |
2686 | unsigned alignment, | |
75e9e915 | 2687 | bool map_and_fenceable) |
673a394b EA |
2688 | { |
2689 | struct drm_device *dev = obj->dev; | |
2690 | drm_i915_private_t *dev_priv = dev->dev_private; | |
23010e43 | 2691 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
673a394b | 2692 | struct drm_mm_node *free_space; |
a00b10c3 CW |
2693 | gfp_t gfpmask = __GFP_NORETRY | __GFP_NOWARN; |
2694 | u32 size, fence_size, fence_alignment; | |
75e9e915 | 2695 | bool mappable, fenceable; |
07f73f69 | 2696 | int ret; |
673a394b | 2697 | |
bb6baf76 | 2698 | if (obj_priv->madv != I915_MADV_WILLNEED) { |
3ef94daa CW |
2699 | DRM_ERROR("Attempting to bind a purgeable object\n"); |
2700 | return -EINVAL; | |
2701 | } | |
2702 | ||
a00b10c3 CW |
2703 | fence_size = i915_gem_get_gtt_size(obj_priv); |
2704 | fence_alignment = i915_gem_get_gtt_alignment(obj_priv); | |
2705 | ||
673a394b | 2706 | if (alignment == 0) |
75e9e915 DV |
2707 | alignment = map_and_fenceable ? fence_alignment : 4096; |
2708 | if (map_and_fenceable && alignment & (fence_alignment - 1)) { | |
673a394b EA |
2709 | DRM_ERROR("Invalid object alignment requested %u\n", alignment); |
2710 | return -EINVAL; | |
2711 | } | |
2712 | ||
75e9e915 | 2713 | size = map_and_fenceable ? fence_size : obj->size; |
a00b10c3 | 2714 | |
654fc607 CW |
2715 | /* If the object is bigger than the entire aperture, reject it early |
2716 | * before evicting everything in a vain attempt to find space. | |
2717 | */ | |
920afa77 | 2718 | if (obj->size > |
75e9e915 | 2719 | (map_and_fenceable ? dev_priv->mm.gtt_mappable_end : dev_priv->mm.gtt_total)) { |
654fc607 CW |
2720 | DRM_ERROR("Attempting to bind an object larger than the aperture\n"); |
2721 | return -E2BIG; | |
2722 | } | |
2723 | ||
673a394b | 2724 | search_free: |
75e9e915 | 2725 | if (map_and_fenceable) |
920afa77 DV |
2726 | free_space = |
2727 | drm_mm_search_free_in_range(&dev_priv->mm.gtt_space, | |
a00b10c3 | 2728 | size, alignment, 0, |
920afa77 DV |
2729 | dev_priv->mm.gtt_mappable_end, |
2730 | 0); | |
2731 | else | |
2732 | free_space = drm_mm_search_free(&dev_priv->mm.gtt_space, | |
a00b10c3 | 2733 | size, alignment, 0); |
920afa77 DV |
2734 | |
2735 | if (free_space != NULL) { | |
75e9e915 | 2736 | if (map_and_fenceable) |
920afa77 DV |
2737 | obj_priv->gtt_space = |
2738 | drm_mm_get_block_range_generic(free_space, | |
a00b10c3 | 2739 | size, alignment, 0, |
920afa77 DV |
2740 | dev_priv->mm.gtt_mappable_end, |
2741 | 0); | |
2742 | else | |
2743 | obj_priv->gtt_space = | |
a00b10c3 | 2744 | drm_mm_get_block(free_space, size, alignment); |
920afa77 | 2745 | } |
673a394b EA |
2746 | if (obj_priv->gtt_space == NULL) { |
2747 | /* If the gtt is empty and we're still having trouble | |
2748 | * fitting our object in, we're out of memory. | |
2749 | */ | |
75e9e915 DV |
2750 | ret = i915_gem_evict_something(dev, size, alignment, |
2751 | map_and_fenceable); | |
9731129c | 2752 | if (ret) |
673a394b | 2753 | return ret; |
9731129c | 2754 | |
673a394b EA |
2755 | goto search_free; |
2756 | } | |
2757 | ||
e5281ccd | 2758 | ret = i915_gem_object_get_pages_gtt(obj, gfpmask); |
673a394b EA |
2759 | if (ret) { |
2760 | drm_mm_put_block(obj_priv->gtt_space); | |
2761 | obj_priv->gtt_space = NULL; | |
07f73f69 CW |
2762 | |
2763 | if (ret == -ENOMEM) { | |
2764 | /* first try to clear up some space from the GTT */ | |
a00b10c3 | 2765 | ret = i915_gem_evict_something(dev, size, |
75e9e915 DV |
2766 | alignment, |
2767 | map_and_fenceable); | |
07f73f69 | 2768 | if (ret) { |
07f73f69 | 2769 | /* now try to shrink everyone else */ |
4bdadb97 CW |
2770 | if (gfpmask) { |
2771 | gfpmask = 0; | |
2772 | goto search_free; | |
07f73f69 CW |
2773 | } |
2774 | ||
2775 | return ret; | |
2776 | } | |
2777 | ||
2778 | goto search_free; | |
2779 | } | |
2780 | ||
673a394b EA |
2781 | return ret; |
2782 | } | |
2783 | ||
673a394b EA |
2784 | /* Create an AGP memory structure pointing at our pages, and bind it |
2785 | * into the GTT. | |
2786 | */ | |
2787 | obj_priv->agp_mem = drm_agp_bind_pages(dev, | |
856fa198 | 2788 | obj_priv->pages, |
07f73f69 | 2789 | obj->size >> PAGE_SHIFT, |
9af90d19 | 2790 | obj_priv->gtt_space->start, |
ba1eb1d8 | 2791 | obj_priv->agp_type); |
673a394b | 2792 | if (obj_priv->agp_mem == NULL) { |
e5281ccd | 2793 | i915_gem_object_put_pages_gtt(obj); |
673a394b EA |
2794 | drm_mm_put_block(obj_priv->gtt_space); |
2795 | obj_priv->gtt_space = NULL; | |
07f73f69 | 2796 | |
a00b10c3 | 2797 | ret = i915_gem_evict_something(dev, size, |
75e9e915 | 2798 | alignment, map_and_fenceable); |
9731129c | 2799 | if (ret) |
07f73f69 | 2800 | return ret; |
07f73f69 CW |
2801 | |
2802 | goto search_free; | |
673a394b | 2803 | } |
673a394b | 2804 | |
fb7d516a DV |
2805 | obj_priv->gtt_offset = obj_priv->gtt_space->start; |
2806 | ||
bf1a1092 | 2807 | /* keep track of bounds object by adding it to the inactive list */ |
69dc4987 | 2808 | list_add_tail(&obj_priv->mm_list, &dev_priv->mm.inactive_list); |
a00b10c3 | 2809 | i915_gem_info_add_gtt(dev_priv, obj_priv); |
bf1a1092 | 2810 | |
673a394b EA |
2811 | /* Assert that the object is not currently in any GPU domain. As it |
2812 | * wasn't in the GTT, there shouldn't be any way it could have been in | |
2813 | * a GPU cache | |
2814 | */ | |
21d509e3 CW |
2815 | BUG_ON(obj->read_domains & I915_GEM_GPU_DOMAINS); |
2816 | BUG_ON(obj->write_domain & I915_GEM_GPU_DOMAINS); | |
673a394b | 2817 | |
75e9e915 | 2818 | trace_i915_gem_object_bind(obj, obj_priv->gtt_offset, map_and_fenceable); |
1c5d22f7 | 2819 | |
75e9e915 | 2820 | fenceable = |
a00b10c3 CW |
2821 | obj_priv->gtt_space->size == fence_size && |
2822 | (obj_priv->gtt_space->start & (fence_alignment -1)) == 0; | |
2823 | ||
75e9e915 | 2824 | mappable = |
a00b10c3 CW |
2825 | obj_priv->gtt_offset + obj->size <= dev_priv->mm.gtt_mappable_end; |
2826 | ||
75e9e915 DV |
2827 | obj_priv->map_and_fenceable = mappable && fenceable; |
2828 | ||
673a394b EA |
2829 | return 0; |
2830 | } | |
2831 | ||
2832 | void | |
2833 | i915_gem_clflush_object(struct drm_gem_object *obj) | |
2834 | { | |
23010e43 | 2835 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
673a394b EA |
2836 | |
2837 | /* If we don't have a page list set up, then we're not pinned | |
2838 | * to GPU, and we can ignore the cache flush because it'll happen | |
2839 | * again at bind time. | |
2840 | */ | |
856fa198 | 2841 | if (obj_priv->pages == NULL) |
673a394b EA |
2842 | return; |
2843 | ||
1c5d22f7 | 2844 | trace_i915_gem_object_clflush(obj); |
cfa16a0d | 2845 | |
856fa198 | 2846 | drm_clflush_pages(obj_priv->pages, obj->size / PAGE_SIZE); |
673a394b EA |
2847 | } |
2848 | ||
e47c68e9 | 2849 | /** Flushes any GPU write domain for the object if it's dirty. */ |
2dafb1e0 | 2850 | static int |
ba3d8d74 DV |
2851 | i915_gem_object_flush_gpu_write_domain(struct drm_gem_object *obj, |
2852 | bool pipelined) | |
e47c68e9 EA |
2853 | { |
2854 | struct drm_device *dev = obj->dev; | |
e47c68e9 EA |
2855 | |
2856 | if ((obj->write_domain & I915_GEM_GPU_DOMAINS) == 0) | |
2dafb1e0 | 2857 | return 0; |
e47c68e9 EA |
2858 | |
2859 | /* Queue the GPU write cache flushing we need. */ | |
c78ec30b | 2860 | i915_gem_flush_ring(dev, NULL, |
9220434a CW |
2861 | to_intel_bo(obj)->ring, |
2862 | 0, obj->write_domain); | |
48b956c5 | 2863 | BUG_ON(obj->write_domain); |
1c5d22f7 | 2864 | |
ba3d8d74 DV |
2865 | if (pipelined) |
2866 | return 0; | |
2867 | ||
2cf34d7b | 2868 | return i915_gem_object_wait_rendering(obj, true); |
e47c68e9 EA |
2869 | } |
2870 | ||
2871 | /** Flushes the GTT write domain for the object if it's dirty. */ | |
2872 | static void | |
2873 | i915_gem_object_flush_gtt_write_domain(struct drm_gem_object *obj) | |
2874 | { | |
1c5d22f7 CW |
2875 | uint32_t old_write_domain; |
2876 | ||
e47c68e9 EA |
2877 | if (obj->write_domain != I915_GEM_DOMAIN_GTT) |
2878 | return; | |
2879 | ||
2880 | /* No actual flushing is required for the GTT write domain. Writes | |
2881 | * to it immediately go to main memory as far as we know, so there's | |
2882 | * no chipset flush. It also doesn't land in render cache. | |
2883 | */ | |
4a684a41 CW |
2884 | i915_gem_release_mmap(obj); |
2885 | ||
1c5d22f7 | 2886 | old_write_domain = obj->write_domain; |
e47c68e9 | 2887 | obj->write_domain = 0; |
1c5d22f7 CW |
2888 | |
2889 | trace_i915_gem_object_change_domain(obj, | |
2890 | obj->read_domains, | |
2891 | old_write_domain); | |
e47c68e9 EA |
2892 | } |
2893 | ||
2894 | /** Flushes the CPU write domain for the object if it's dirty. */ | |
2895 | static void | |
2896 | i915_gem_object_flush_cpu_write_domain(struct drm_gem_object *obj) | |
2897 | { | |
2898 | struct drm_device *dev = obj->dev; | |
1c5d22f7 | 2899 | uint32_t old_write_domain; |
e47c68e9 EA |
2900 | |
2901 | if (obj->write_domain != I915_GEM_DOMAIN_CPU) | |
2902 | return; | |
2903 | ||
2904 | i915_gem_clflush_object(obj); | |
2905 | drm_agp_chipset_flush(dev); | |
1c5d22f7 | 2906 | old_write_domain = obj->write_domain; |
e47c68e9 | 2907 | obj->write_domain = 0; |
1c5d22f7 CW |
2908 | |
2909 | trace_i915_gem_object_change_domain(obj, | |
2910 | obj->read_domains, | |
2911 | old_write_domain); | |
e47c68e9 EA |
2912 | } |
2913 | ||
2ef7eeaa EA |
2914 | /** |
2915 | * Moves a single object to the GTT read, and possibly write domain. | |
2916 | * | |
2917 | * This function returns when the move is complete, including waiting on | |
2918 | * flushes to occur. | |
2919 | */ | |
79e53945 | 2920 | int |
2ef7eeaa EA |
2921 | i915_gem_object_set_to_gtt_domain(struct drm_gem_object *obj, int write) |
2922 | { | |
23010e43 | 2923 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
1c5d22f7 | 2924 | uint32_t old_write_domain, old_read_domains; |
e47c68e9 | 2925 | int ret; |
2ef7eeaa | 2926 | |
02354392 EA |
2927 | /* Not valid to be called on unbound objects. */ |
2928 | if (obj_priv->gtt_space == NULL) | |
2929 | return -EINVAL; | |
2930 | ||
ba3d8d74 | 2931 | ret = i915_gem_object_flush_gpu_write_domain(obj, false); |
2dafb1e0 CW |
2932 | if (ret != 0) |
2933 | return ret; | |
2934 | ||
7213342d | 2935 | i915_gem_object_flush_cpu_write_domain(obj); |
1c5d22f7 | 2936 | |
ba3d8d74 | 2937 | if (write) { |
2cf34d7b | 2938 | ret = i915_gem_object_wait_rendering(obj, true); |
ba3d8d74 DV |
2939 | if (ret) |
2940 | return ret; | |
ba3d8d74 | 2941 | } |
e47c68e9 | 2942 | |
1c5d22f7 CW |
2943 | old_write_domain = obj->write_domain; |
2944 | old_read_domains = obj->read_domains; | |
2945 | ||
e47c68e9 EA |
2946 | /* It should now be out of any other write domains, and we can update |
2947 | * the domain values for our changes. | |
2948 | */ | |
2949 | BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_GTT) != 0); | |
2950 | obj->read_domains |= I915_GEM_DOMAIN_GTT; | |
2951 | if (write) { | |
7213342d | 2952 | obj->read_domains = I915_GEM_DOMAIN_GTT; |
e47c68e9 EA |
2953 | obj->write_domain = I915_GEM_DOMAIN_GTT; |
2954 | obj_priv->dirty = 1; | |
2ef7eeaa EA |
2955 | } |
2956 | ||
1c5d22f7 CW |
2957 | trace_i915_gem_object_change_domain(obj, |
2958 | old_read_domains, | |
2959 | old_write_domain); | |
2960 | ||
e47c68e9 EA |
2961 | return 0; |
2962 | } | |
2963 | ||
b9241ea3 ZW |
2964 | /* |
2965 | * Prepare buffer for display plane. Use uninterruptible for possible flush | |
2966 | * wait, as in modesetting process we're not supposed to be interrupted. | |
2967 | */ | |
2968 | int | |
48b956c5 CW |
2969 | i915_gem_object_set_to_display_plane(struct drm_gem_object *obj, |
2970 | bool pipelined) | |
b9241ea3 | 2971 | { |
23010e43 | 2972 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
ba3d8d74 | 2973 | uint32_t old_read_domains; |
b9241ea3 ZW |
2974 | int ret; |
2975 | ||
2976 | /* Not valid to be called on unbound objects. */ | |
2977 | if (obj_priv->gtt_space == NULL) | |
2978 | return -EINVAL; | |
2979 | ||
ced270fa | 2980 | ret = i915_gem_object_flush_gpu_write_domain(obj, true); |
2dafb1e0 CW |
2981 | if (ret) |
2982 | return ret; | |
b9241ea3 | 2983 | |
ced270fa CW |
2984 | /* Currently, we are always called from an non-interruptible context. */ |
2985 | if (!pipelined) { | |
2986 | ret = i915_gem_object_wait_rendering(obj, false); | |
2987 | if (ret) | |
b9241ea3 ZW |
2988 | return ret; |
2989 | } | |
2990 | ||
b118c1e3 CW |
2991 | i915_gem_object_flush_cpu_write_domain(obj); |
2992 | ||
b9241ea3 | 2993 | old_read_domains = obj->read_domains; |
c78ec30b | 2994 | obj->read_domains |= I915_GEM_DOMAIN_GTT; |
b9241ea3 ZW |
2995 | |
2996 | trace_i915_gem_object_change_domain(obj, | |
2997 | old_read_domains, | |
ba3d8d74 | 2998 | obj->write_domain); |
b9241ea3 ZW |
2999 | |
3000 | return 0; | |
3001 | } | |
3002 | ||
e47c68e9 EA |
3003 | /** |
3004 | * Moves a single object to the CPU read, and possibly write domain. | |
3005 | * | |
3006 | * This function returns when the move is complete, including waiting on | |
3007 | * flushes to occur. | |
3008 | */ | |
3009 | static int | |
3010 | i915_gem_object_set_to_cpu_domain(struct drm_gem_object *obj, int write) | |
3011 | { | |
1c5d22f7 | 3012 | uint32_t old_write_domain, old_read_domains; |
e47c68e9 EA |
3013 | int ret; |
3014 | ||
ba3d8d74 | 3015 | ret = i915_gem_object_flush_gpu_write_domain(obj, false); |
e47c68e9 EA |
3016 | if (ret != 0) |
3017 | return ret; | |
2ef7eeaa | 3018 | |
e47c68e9 | 3019 | i915_gem_object_flush_gtt_write_domain(obj); |
2ef7eeaa | 3020 | |
e47c68e9 EA |
3021 | /* If we have a partially-valid cache of the object in the CPU, |
3022 | * finish invalidating it and free the per-page flags. | |
2ef7eeaa | 3023 | */ |
e47c68e9 | 3024 | i915_gem_object_set_to_full_cpu_read_domain(obj); |
2ef7eeaa | 3025 | |
7213342d | 3026 | if (write) { |
2cf34d7b | 3027 | ret = i915_gem_object_wait_rendering(obj, true); |
7213342d CW |
3028 | if (ret) |
3029 | return ret; | |
3030 | } | |
3031 | ||
1c5d22f7 CW |
3032 | old_write_domain = obj->write_domain; |
3033 | old_read_domains = obj->read_domains; | |
3034 | ||
e47c68e9 EA |
3035 | /* Flush the CPU cache if it's still invalid. */ |
3036 | if ((obj->read_domains & I915_GEM_DOMAIN_CPU) == 0) { | |
2ef7eeaa | 3037 | i915_gem_clflush_object(obj); |
2ef7eeaa | 3038 | |
e47c68e9 | 3039 | obj->read_domains |= I915_GEM_DOMAIN_CPU; |
2ef7eeaa EA |
3040 | } |
3041 | ||
3042 | /* It should now be out of any other write domains, and we can update | |
3043 | * the domain values for our changes. | |
3044 | */ | |
e47c68e9 EA |
3045 | BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_CPU) != 0); |
3046 | ||
3047 | /* If we're writing through the CPU, then the GPU read domains will | |
3048 | * need to be invalidated at next use. | |
3049 | */ | |
3050 | if (write) { | |
c78ec30b | 3051 | obj->read_domains = I915_GEM_DOMAIN_CPU; |
e47c68e9 EA |
3052 | obj->write_domain = I915_GEM_DOMAIN_CPU; |
3053 | } | |
2ef7eeaa | 3054 | |
1c5d22f7 CW |
3055 | trace_i915_gem_object_change_domain(obj, |
3056 | old_read_domains, | |
3057 | old_write_domain); | |
3058 | ||
2ef7eeaa EA |
3059 | return 0; |
3060 | } | |
3061 | ||
673a394b EA |
3062 | /* |
3063 | * Set the next domain for the specified object. This | |
3064 | * may not actually perform the necessary flushing/invaliding though, | |
3065 | * as that may want to be batched with other set_domain operations | |
3066 | * | |
3067 | * This is (we hope) the only really tricky part of gem. The goal | |
3068 | * is fairly simple -- track which caches hold bits of the object | |
3069 | * and make sure they remain coherent. A few concrete examples may | |
3070 | * help to explain how it works. For shorthand, we use the notation | |
3071 | * (read_domains, write_domain), e.g. (CPU, CPU) to indicate the | |
3072 | * a pair of read and write domain masks. | |
3073 | * | |
3074 | * Case 1: the batch buffer | |
3075 | * | |
3076 | * 1. Allocated | |
3077 | * 2. Written by CPU | |
3078 | * 3. Mapped to GTT | |
3079 | * 4. Read by GPU | |
3080 | * 5. Unmapped from GTT | |
3081 | * 6. Freed | |
3082 | * | |
3083 | * Let's take these a step at a time | |
3084 | * | |
3085 | * 1. Allocated | |
3086 | * Pages allocated from the kernel may still have | |
3087 | * cache contents, so we set them to (CPU, CPU) always. | |
3088 | * 2. Written by CPU (using pwrite) | |
3089 | * The pwrite function calls set_domain (CPU, CPU) and | |
3090 | * this function does nothing (as nothing changes) | |
3091 | * 3. Mapped by GTT | |
3092 | * This function asserts that the object is not | |
3093 | * currently in any GPU-based read or write domains | |
3094 | * 4. Read by GPU | |
3095 | * i915_gem_execbuffer calls set_domain (COMMAND, 0). | |
3096 | * As write_domain is zero, this function adds in the | |
3097 | * current read domains (CPU+COMMAND, 0). | |
3098 | * flush_domains is set to CPU. | |
3099 | * invalidate_domains is set to COMMAND | |
3100 | * clflush is run to get data out of the CPU caches | |
3101 | * then i915_dev_set_domain calls i915_gem_flush to | |
3102 | * emit an MI_FLUSH and drm_agp_chipset_flush | |
3103 | * 5. Unmapped from GTT | |
3104 | * i915_gem_object_unbind calls set_domain (CPU, CPU) | |
3105 | * flush_domains and invalidate_domains end up both zero | |
3106 | * so no flushing/invalidating happens | |
3107 | * 6. Freed | |
3108 | * yay, done | |
3109 | * | |
3110 | * Case 2: The shared render buffer | |
3111 | * | |
3112 | * 1. Allocated | |
3113 | * 2. Mapped to GTT | |
3114 | * 3. Read/written by GPU | |
3115 | * 4. set_domain to (CPU,CPU) | |
3116 | * 5. Read/written by CPU | |
3117 | * 6. Read/written by GPU | |
3118 | * | |
3119 | * 1. Allocated | |
3120 | * Same as last example, (CPU, CPU) | |
3121 | * 2. Mapped to GTT | |
3122 | * Nothing changes (assertions find that it is not in the GPU) | |
3123 | * 3. Read/written by GPU | |
3124 | * execbuffer calls set_domain (RENDER, RENDER) | |
3125 | * flush_domains gets CPU | |
3126 | * invalidate_domains gets GPU | |
3127 | * clflush (obj) | |
3128 | * MI_FLUSH and drm_agp_chipset_flush | |
3129 | * 4. set_domain (CPU, CPU) | |
3130 | * flush_domains gets GPU | |
3131 | * invalidate_domains gets CPU | |
3132 | * wait_rendering (obj) to make sure all drawing is complete. | |
3133 | * This will include an MI_FLUSH to get the data from GPU | |
3134 | * to memory | |
3135 | * clflush (obj) to invalidate the CPU cache | |
3136 | * Another MI_FLUSH in i915_gem_flush (eliminate this somehow?) | |
3137 | * 5. Read/written by CPU | |
3138 | * cache lines are loaded and dirtied | |
3139 | * 6. Read written by GPU | |
3140 | * Same as last GPU access | |
3141 | * | |
3142 | * Case 3: The constant buffer | |
3143 | * | |
3144 | * 1. Allocated | |
3145 | * 2. Written by CPU | |
3146 | * 3. Read by GPU | |
3147 | * 4. Updated (written) by CPU again | |
3148 | * 5. Read by GPU | |
3149 | * | |
3150 | * 1. Allocated | |
3151 | * (CPU, CPU) | |
3152 | * 2. Written by CPU | |
3153 | * (CPU, CPU) | |
3154 | * 3. Read by GPU | |
3155 | * (CPU+RENDER, 0) | |
3156 | * flush_domains = CPU | |
3157 | * invalidate_domains = RENDER | |
3158 | * clflush (obj) | |
3159 | * MI_FLUSH | |
3160 | * drm_agp_chipset_flush | |
3161 | * 4. Updated (written) by CPU again | |
3162 | * (CPU, CPU) | |
3163 | * flush_domains = 0 (no previous write domain) | |
3164 | * invalidate_domains = 0 (no new read domains) | |
3165 | * 5. Read by GPU | |
3166 | * (CPU+RENDER, 0) | |
3167 | * flush_domains = CPU | |
3168 | * invalidate_domains = RENDER | |
3169 | * clflush (obj) | |
3170 | * MI_FLUSH | |
3171 | * drm_agp_chipset_flush | |
3172 | */ | |
c0d90829 | 3173 | static void |
b6651458 | 3174 | i915_gem_object_set_to_gpu_domain(struct drm_gem_object *obj, |
0f8c6d7c CW |
3175 | struct intel_ring_buffer *ring, |
3176 | struct change_domains *cd) | |
673a394b | 3177 | { |
23010e43 | 3178 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
673a394b EA |
3179 | uint32_t invalidate_domains = 0; |
3180 | uint32_t flush_domains = 0; | |
652c393a | 3181 | |
673a394b EA |
3182 | /* |
3183 | * If the object isn't moving to a new write domain, | |
3184 | * let the object stay in multiple read domains | |
3185 | */ | |
8b0e378a EA |
3186 | if (obj->pending_write_domain == 0) |
3187 | obj->pending_read_domains |= obj->read_domains; | |
673a394b EA |
3188 | |
3189 | /* | |
3190 | * Flush the current write domain if | |
3191 | * the new read domains don't match. Invalidate | |
3192 | * any read domains which differ from the old | |
3193 | * write domain | |
3194 | */ | |
8b0e378a | 3195 | if (obj->write_domain && |
13b29289 CW |
3196 | (obj->write_domain != obj->pending_read_domains || |
3197 | obj_priv->ring != ring)) { | |
673a394b | 3198 | flush_domains |= obj->write_domain; |
8b0e378a EA |
3199 | invalidate_domains |= |
3200 | obj->pending_read_domains & ~obj->write_domain; | |
673a394b EA |
3201 | } |
3202 | /* | |
3203 | * Invalidate any read caches which may have | |
3204 | * stale data. That is, any new read domains. | |
3205 | */ | |
8b0e378a | 3206 | invalidate_domains |= obj->pending_read_domains & ~obj->read_domains; |
3d2a812a | 3207 | if ((flush_domains | invalidate_domains) & I915_GEM_DOMAIN_CPU) |
673a394b | 3208 | i915_gem_clflush_object(obj); |
673a394b | 3209 | |
4a684a41 CW |
3210 | /* blow away mappings if mapped through GTT */ |
3211 | if ((flush_domains | invalidate_domains) & I915_GEM_DOMAIN_GTT) | |
3212 | i915_gem_release_mmap(obj); | |
3213 | ||
efbeed96 EA |
3214 | /* The actual obj->write_domain will be updated with |
3215 | * pending_write_domain after we emit the accumulated flush for all | |
3216 | * of our domain changes in execbuffers (which clears objects' | |
3217 | * write_domains). So if we have a current write domain that we | |
3218 | * aren't changing, set pending_write_domain to that. | |
3219 | */ | |
3220 | if (flush_domains == 0 && obj->pending_write_domain == 0) | |
3221 | obj->pending_write_domain = obj->write_domain; | |
673a394b | 3222 | |
0f8c6d7c CW |
3223 | cd->invalidate_domains |= invalidate_domains; |
3224 | cd->flush_domains |= flush_domains; | |
b6651458 | 3225 | if (flush_domains & I915_GEM_GPU_DOMAINS) |
0f8c6d7c | 3226 | cd->flush_rings |= obj_priv->ring->id; |
b6651458 | 3227 | if (invalidate_domains & I915_GEM_GPU_DOMAINS) |
0f8c6d7c | 3228 | cd->flush_rings |= ring->id; |
673a394b EA |
3229 | } |
3230 | ||
3231 | /** | |
e47c68e9 | 3232 | * Moves the object from a partially CPU read to a full one. |
673a394b | 3233 | * |
e47c68e9 EA |
3234 | * Note that this only resolves i915_gem_object_set_cpu_read_domain_range(), |
3235 | * and doesn't handle transitioning from !(read_domains & I915_GEM_DOMAIN_CPU). | |
673a394b | 3236 | */ |
e47c68e9 EA |
3237 | static void |
3238 | i915_gem_object_set_to_full_cpu_read_domain(struct drm_gem_object *obj) | |
673a394b | 3239 | { |
23010e43 | 3240 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
673a394b | 3241 | |
e47c68e9 EA |
3242 | if (!obj_priv->page_cpu_valid) |
3243 | return; | |
3244 | ||
3245 | /* If we're partially in the CPU read domain, finish moving it in. | |
3246 | */ | |
3247 | if (obj->read_domains & I915_GEM_DOMAIN_CPU) { | |
3248 | int i; | |
3249 | ||
3250 | for (i = 0; i <= (obj->size - 1) / PAGE_SIZE; i++) { | |
3251 | if (obj_priv->page_cpu_valid[i]) | |
3252 | continue; | |
856fa198 | 3253 | drm_clflush_pages(obj_priv->pages + i, 1); |
e47c68e9 | 3254 | } |
e47c68e9 EA |
3255 | } |
3256 | ||
3257 | /* Free the page_cpu_valid mappings which are now stale, whether | |
3258 | * or not we've got I915_GEM_DOMAIN_CPU. | |
3259 | */ | |
9a298b2a | 3260 | kfree(obj_priv->page_cpu_valid); |
e47c68e9 EA |
3261 | obj_priv->page_cpu_valid = NULL; |
3262 | } | |
3263 | ||
3264 | /** | |
3265 | * Set the CPU read domain on a range of the object. | |
3266 | * | |
3267 | * The object ends up with I915_GEM_DOMAIN_CPU in its read flags although it's | |
3268 | * not entirely valid. The page_cpu_valid member of the object flags which | |
3269 | * pages have been flushed, and will be respected by | |
3270 | * i915_gem_object_set_to_cpu_domain() if it's called on to get a valid mapping | |
3271 | * of the whole object. | |
3272 | * | |
3273 | * This function returns when the move is complete, including waiting on | |
3274 | * flushes to occur. | |
3275 | */ | |
3276 | static int | |
3277 | i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object *obj, | |
3278 | uint64_t offset, uint64_t size) | |
3279 | { | |
23010e43 | 3280 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
1c5d22f7 | 3281 | uint32_t old_read_domains; |
e47c68e9 | 3282 | int i, ret; |
673a394b | 3283 | |
e47c68e9 EA |
3284 | if (offset == 0 && size == obj->size) |
3285 | return i915_gem_object_set_to_cpu_domain(obj, 0); | |
673a394b | 3286 | |
ba3d8d74 | 3287 | ret = i915_gem_object_flush_gpu_write_domain(obj, false); |
e47c68e9 | 3288 | if (ret != 0) |
6a47baa6 | 3289 | return ret; |
e47c68e9 EA |
3290 | i915_gem_object_flush_gtt_write_domain(obj); |
3291 | ||
3292 | /* If we're already fully in the CPU read domain, we're done. */ | |
3293 | if (obj_priv->page_cpu_valid == NULL && | |
3294 | (obj->read_domains & I915_GEM_DOMAIN_CPU) != 0) | |
3295 | return 0; | |
673a394b | 3296 | |
e47c68e9 EA |
3297 | /* Otherwise, create/clear the per-page CPU read domain flag if we're |
3298 | * newly adding I915_GEM_DOMAIN_CPU | |
3299 | */ | |
673a394b | 3300 | if (obj_priv->page_cpu_valid == NULL) { |
9a298b2a EA |
3301 | obj_priv->page_cpu_valid = kzalloc(obj->size / PAGE_SIZE, |
3302 | GFP_KERNEL); | |
e47c68e9 EA |
3303 | if (obj_priv->page_cpu_valid == NULL) |
3304 | return -ENOMEM; | |
3305 | } else if ((obj->read_domains & I915_GEM_DOMAIN_CPU) == 0) | |
3306 | memset(obj_priv->page_cpu_valid, 0, obj->size / PAGE_SIZE); | |
673a394b EA |
3307 | |
3308 | /* Flush the cache on any pages that are still invalid from the CPU's | |
3309 | * perspective. | |
3310 | */ | |
e47c68e9 EA |
3311 | for (i = offset / PAGE_SIZE; i <= (offset + size - 1) / PAGE_SIZE; |
3312 | i++) { | |
673a394b EA |
3313 | if (obj_priv->page_cpu_valid[i]) |
3314 | continue; | |
3315 | ||
856fa198 | 3316 | drm_clflush_pages(obj_priv->pages + i, 1); |
673a394b EA |
3317 | |
3318 | obj_priv->page_cpu_valid[i] = 1; | |
3319 | } | |
3320 | ||
e47c68e9 EA |
3321 | /* It should now be out of any other write domains, and we can update |
3322 | * the domain values for our changes. | |
3323 | */ | |
3324 | BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_CPU) != 0); | |
3325 | ||
1c5d22f7 | 3326 | old_read_domains = obj->read_domains; |
e47c68e9 EA |
3327 | obj->read_domains |= I915_GEM_DOMAIN_CPU; |
3328 | ||
1c5d22f7 CW |
3329 | trace_i915_gem_object_change_domain(obj, |
3330 | old_read_domains, | |
3331 | obj->write_domain); | |
3332 | ||
673a394b EA |
3333 | return 0; |
3334 | } | |
3335 | ||
673a394b EA |
3336 | /** |
3337 | * Pin an object to the GTT and evaluate the relocations landing in it. | |
3338 | */ | |
3339 | static int | |
9af90d19 CW |
3340 | i915_gem_execbuffer_relocate(struct drm_i915_gem_object *obj, |
3341 | struct drm_file *file_priv, | |
3342 | struct drm_i915_gem_exec_object2 *entry) | |
673a394b | 3343 | { |
9af90d19 | 3344 | struct drm_device *dev = obj->base.dev; |
0839ccb8 | 3345 | drm_i915_private_t *dev_priv = dev->dev_private; |
2549d6c2 | 3346 | struct drm_i915_gem_relocation_entry __user *user_relocs; |
9af90d19 CW |
3347 | struct drm_gem_object *target_obj = NULL; |
3348 | uint32_t target_handle = 0; | |
3349 | int i, ret = 0; | |
673a394b | 3350 | |
2549d6c2 | 3351 | user_relocs = (void __user *)(uintptr_t)entry->relocs_ptr; |
673a394b | 3352 | for (i = 0; i < entry->relocation_count; i++) { |
2549d6c2 | 3353 | struct drm_i915_gem_relocation_entry reloc; |
9af90d19 | 3354 | uint32_t target_offset; |
673a394b | 3355 | |
9af90d19 CW |
3356 | if (__copy_from_user_inatomic(&reloc, |
3357 | user_relocs+i, | |
3358 | sizeof(reloc))) { | |
3359 | ret = -EFAULT; | |
3360 | break; | |
76446cac | 3361 | } |
76446cac | 3362 | |
9af90d19 CW |
3363 | if (reloc.target_handle != target_handle) { |
3364 | drm_gem_object_unreference(target_obj); | |
673a394b | 3365 | |
9af90d19 CW |
3366 | target_obj = drm_gem_object_lookup(dev, file_priv, |
3367 | reloc.target_handle); | |
3368 | if (target_obj == NULL) { | |
3369 | ret = -ENOENT; | |
3370 | break; | |
3371 | } | |
3372 | ||
3373 | target_handle = reloc.target_handle; | |
673a394b | 3374 | } |
9af90d19 | 3375 | target_offset = to_intel_bo(target_obj)->gtt_offset; |
673a394b | 3376 | |
8542a0bb CW |
3377 | #if WATCH_RELOC |
3378 | DRM_INFO("%s: obj %p offset %08x target %d " | |
3379 | "read %08x write %08x gtt %08x " | |
3380 | "presumed %08x delta %08x\n", | |
3381 | __func__, | |
3382 | obj, | |
2549d6c2 CW |
3383 | (int) reloc.offset, |
3384 | (int) reloc.target_handle, | |
3385 | (int) reloc.read_domains, | |
3386 | (int) reloc.write_domain, | |
9af90d19 | 3387 | (int) target_offset, |
2549d6c2 CW |
3388 | (int) reloc.presumed_offset, |
3389 | reloc.delta); | |
8542a0bb CW |
3390 | #endif |
3391 | ||
673a394b EA |
3392 | /* The target buffer should have appeared before us in the |
3393 | * exec_object list, so it should have a GTT space bound by now. | |
3394 | */ | |
9af90d19 | 3395 | if (target_offset == 0) { |
673a394b | 3396 | DRM_ERROR("No GTT space found for object %d\n", |
2549d6c2 | 3397 | reloc.target_handle); |
9af90d19 CW |
3398 | ret = -EINVAL; |
3399 | break; | |
673a394b EA |
3400 | } |
3401 | ||
8542a0bb | 3402 | /* Validate that the target is in a valid r/w GPU domain */ |
2549d6c2 | 3403 | if (reloc.write_domain & (reloc.write_domain - 1)) { |
16edd550 DV |
3404 | DRM_ERROR("reloc with multiple write domains: " |
3405 | "obj %p target %d offset %d " | |
3406 | "read %08x write %08x", | |
2549d6c2 CW |
3407 | obj, reloc.target_handle, |
3408 | (int) reloc.offset, | |
3409 | reloc.read_domains, | |
3410 | reloc.write_domain); | |
9af90d19 CW |
3411 | ret = -EINVAL; |
3412 | break; | |
16edd550 | 3413 | } |
2549d6c2 CW |
3414 | if (reloc.write_domain & I915_GEM_DOMAIN_CPU || |
3415 | reloc.read_domains & I915_GEM_DOMAIN_CPU) { | |
e47c68e9 EA |
3416 | DRM_ERROR("reloc with read/write CPU domains: " |
3417 | "obj %p target %d offset %d " | |
3418 | "read %08x write %08x", | |
2549d6c2 CW |
3419 | obj, reloc.target_handle, |
3420 | (int) reloc.offset, | |
3421 | reloc.read_domains, | |
3422 | reloc.write_domain); | |
9af90d19 CW |
3423 | ret = -EINVAL; |
3424 | break; | |
e47c68e9 | 3425 | } |
2549d6c2 CW |
3426 | if (reloc.write_domain && target_obj->pending_write_domain && |
3427 | reloc.write_domain != target_obj->pending_write_domain) { | |
673a394b EA |
3428 | DRM_ERROR("Write domain conflict: " |
3429 | "obj %p target %d offset %d " | |
3430 | "new %08x old %08x\n", | |
2549d6c2 CW |
3431 | obj, reloc.target_handle, |
3432 | (int) reloc.offset, | |
3433 | reloc.write_domain, | |
673a394b | 3434 | target_obj->pending_write_domain); |
9af90d19 CW |
3435 | ret = -EINVAL; |
3436 | break; | |
673a394b EA |
3437 | } |
3438 | ||
2549d6c2 | 3439 | target_obj->pending_read_domains |= reloc.read_domains; |
878a3c37 | 3440 | target_obj->pending_write_domain |= reloc.write_domain; |
673a394b EA |
3441 | |
3442 | /* If the relocation already has the right value in it, no | |
3443 | * more work needs to be done. | |
3444 | */ | |
9af90d19 | 3445 | if (target_offset == reloc.presumed_offset) |
673a394b | 3446 | continue; |
673a394b | 3447 | |
8542a0bb | 3448 | /* Check that the relocation address is valid... */ |
9af90d19 | 3449 | if (reloc.offset > obj->base.size - 4) { |
8542a0bb CW |
3450 | DRM_ERROR("Relocation beyond object bounds: " |
3451 | "obj %p target %d offset %d size %d.\n", | |
2549d6c2 | 3452 | obj, reloc.target_handle, |
9af90d19 CW |
3453 | (int) reloc.offset, (int) obj->base.size); |
3454 | ret = -EINVAL; | |
3455 | break; | |
8542a0bb | 3456 | } |
2549d6c2 | 3457 | if (reloc.offset & 3) { |
8542a0bb CW |
3458 | DRM_ERROR("Relocation not 4-byte aligned: " |
3459 | "obj %p target %d offset %d.\n", | |
2549d6c2 CW |
3460 | obj, reloc.target_handle, |
3461 | (int) reloc.offset); | |
9af90d19 CW |
3462 | ret = -EINVAL; |
3463 | break; | |
8542a0bb CW |
3464 | } |
3465 | ||
3466 | /* and points to somewhere within the target object. */ | |
2549d6c2 | 3467 | if (reloc.delta >= target_obj->size) { |
8542a0bb CW |
3468 | DRM_ERROR("Relocation beyond target object bounds: " |
3469 | "obj %p target %d delta %d size %d.\n", | |
2549d6c2 CW |
3470 | obj, reloc.target_handle, |
3471 | (int) reloc.delta, (int) target_obj->size); | |
9af90d19 CW |
3472 | ret = -EINVAL; |
3473 | break; | |
673a394b EA |
3474 | } |
3475 | ||
9af90d19 CW |
3476 | reloc.delta += target_offset; |
3477 | if (obj->base.write_domain == I915_GEM_DOMAIN_CPU) { | |
f0c43d9b CW |
3478 | uint32_t page_offset = reloc.offset & ~PAGE_MASK; |
3479 | char *vaddr; | |
673a394b | 3480 | |
c48c43e4 | 3481 | vaddr = kmap_atomic(obj->pages[reloc.offset >> PAGE_SHIFT]); |
f0c43d9b | 3482 | *(uint32_t *)(vaddr + page_offset) = reloc.delta; |
c48c43e4 | 3483 | kunmap_atomic(vaddr); |
f0c43d9b CW |
3484 | } else { |
3485 | uint32_t __iomem *reloc_entry; | |
3486 | void __iomem *reloc_page; | |
b962442e | 3487 | |
9af90d19 CW |
3488 | ret = i915_gem_object_set_to_gtt_domain(&obj->base, 1); |
3489 | if (ret) | |
3490 | break; | |
b962442e | 3491 | |
f0c43d9b | 3492 | /* Map the page containing the relocation we're going to perform. */ |
9af90d19 | 3493 | reloc.offset += obj->gtt_offset; |
f0c43d9b | 3494 | reloc_page = io_mapping_map_atomic_wc(dev_priv->mm.gtt_mapping, |
c48c43e4 | 3495 | reloc.offset & PAGE_MASK); |
f0c43d9b CW |
3496 | reloc_entry = (uint32_t __iomem *) |
3497 | (reloc_page + (reloc.offset & ~PAGE_MASK)); | |
3498 | iowrite32(reloc.delta, reloc_entry); | |
c48c43e4 | 3499 | io_mapping_unmap_atomic(reloc_page); |
f0c43d9b | 3500 | } |
b962442e | 3501 | |
b5dc608c CW |
3502 | /* and update the user's relocation entry */ |
3503 | reloc.presumed_offset = target_offset; | |
3504 | if (__copy_to_user_inatomic(&user_relocs[i].presumed_offset, | |
3505 | &reloc.presumed_offset, | |
3506 | sizeof(reloc.presumed_offset))) { | |
3507 | ret = -EFAULT; | |
3508 | break; | |
3509 | } | |
b962442e | 3510 | } |
b962442e | 3511 | |
9af90d19 | 3512 | drm_gem_object_unreference(target_obj); |
673a394b EA |
3513 | return ret; |
3514 | } | |
3515 | ||
40a5f0de | 3516 | static int |
9af90d19 CW |
3517 | i915_gem_execbuffer_pin(struct drm_device *dev, |
3518 | struct drm_file *file, | |
3519 | struct drm_gem_object **object_list, | |
3520 | struct drm_i915_gem_exec_object2 *exec_list, | |
3521 | int count) | |
40a5f0de | 3522 | { |
9af90d19 CW |
3523 | struct drm_i915_private *dev_priv = dev->dev_private; |
3524 | int ret, i, retry; | |
40a5f0de | 3525 | |
9af90d19 | 3526 | /* attempt to pin all of the buffers into the GTT */ |
5eac3ab4 CW |
3527 | retry = 0; |
3528 | do { | |
9af90d19 CW |
3529 | ret = 0; |
3530 | for (i = 0; i < count; i++) { | |
3531 | struct drm_i915_gem_exec_object2 *entry = &exec_list[i]; | |
16e809ac | 3532 | struct drm_i915_gem_object *obj = to_intel_bo(object_list[i]); |
9af90d19 CW |
3533 | bool need_fence = |
3534 | entry->flags & EXEC_OBJECT_NEEDS_FENCE && | |
3535 | obj->tiling_mode != I915_TILING_NONE; | |
3536 | ||
16e809ac DV |
3537 | /* g33/pnv can't fence buffers in the unmappable part */ |
3538 | bool need_mappable = | |
3539 | entry->relocation_count ? true : need_fence; | |
3540 | ||
9af90d19 | 3541 | /* Check fence reg constraints and rebind if necessary */ |
75e9e915 | 3542 | if (need_mappable && !obj->map_and_fenceable) { |
9af90d19 CW |
3543 | ret = i915_gem_object_unbind(&obj->base); |
3544 | if (ret) | |
3545 | break; | |
3546 | } | |
40a5f0de | 3547 | |
920afa77 | 3548 | ret = i915_gem_object_pin(&obj->base, |
16e809ac | 3549 | entry->alignment, |
75e9e915 | 3550 | need_mappable); |
9af90d19 CW |
3551 | if (ret) |
3552 | break; | |
40a5f0de | 3553 | |
9af90d19 CW |
3554 | /* |
3555 | * Pre-965 chips need a fence register set up in order | |
3556 | * to properly handle blits to/from tiled surfaces. | |
3557 | */ | |
3558 | if (need_fence) { | |
3559 | ret = i915_gem_object_get_fence_reg(&obj->base, true); | |
3560 | if (ret) { | |
3561 | i915_gem_object_unpin(&obj->base); | |
3562 | break; | |
3563 | } | |
40a5f0de | 3564 | |
9af90d19 CW |
3565 | dev_priv->fence_regs[obj->fence_reg].gpu = true; |
3566 | } | |
40a5f0de | 3567 | |
9af90d19 | 3568 | entry->offset = obj->gtt_offset; |
40a5f0de EA |
3569 | } |
3570 | ||
9af90d19 CW |
3571 | while (i--) |
3572 | i915_gem_object_unpin(object_list[i]); | |
3573 | ||
5eac3ab4 | 3574 | if (ret != -ENOSPC || retry > 1) |
9af90d19 CW |
3575 | return ret; |
3576 | ||
5eac3ab4 CW |
3577 | /* First attempt, just clear anything that is purgeable. |
3578 | * Second attempt, clear the entire GTT. | |
3579 | */ | |
3580 | ret = i915_gem_evict_everything(dev, retry == 0); | |
9af90d19 CW |
3581 | if (ret) |
3582 | return ret; | |
40a5f0de | 3583 | |
5eac3ab4 CW |
3584 | retry++; |
3585 | } while (1); | |
40a5f0de EA |
3586 | } |
3587 | ||
13b29289 CW |
3588 | static int |
3589 | i915_gem_execbuffer_move_to_gpu(struct drm_device *dev, | |
3590 | struct drm_file *file, | |
3591 | struct intel_ring_buffer *ring, | |
3592 | struct drm_gem_object **objects, | |
3593 | int count) | |
3594 | { | |
0f8c6d7c | 3595 | struct change_domains cd; |
13b29289 CW |
3596 | int ret, i; |
3597 | ||
0f8c6d7c CW |
3598 | cd.invalidate_domains = 0; |
3599 | cd.flush_domains = 0; | |
3600 | cd.flush_rings = 0; | |
13b29289 | 3601 | for (i = 0; i < count; i++) |
0f8c6d7c | 3602 | i915_gem_object_set_to_gpu_domain(objects[i], ring, &cd); |
13b29289 | 3603 | |
0f8c6d7c | 3604 | if (cd.invalidate_domains | cd.flush_domains) { |
13b29289 CW |
3605 | #if WATCH_EXEC |
3606 | DRM_INFO("%s: invalidate_domains %08x flush_domains %08x\n", | |
3607 | __func__, | |
0f8c6d7c CW |
3608 | cd.invalidate_domains, |
3609 | cd.flush_domains); | |
13b29289 CW |
3610 | #endif |
3611 | i915_gem_flush(dev, file, | |
0f8c6d7c CW |
3612 | cd.invalidate_domains, |
3613 | cd.flush_domains, | |
3614 | cd.flush_rings); | |
13b29289 CW |
3615 | } |
3616 | ||
3617 | for (i = 0; i < count; i++) { | |
3618 | struct drm_i915_gem_object *obj = to_intel_bo(objects[i]); | |
3619 | /* XXX replace with semaphores */ | |
3620 | if (obj->ring && ring != obj->ring) { | |
3621 | ret = i915_gem_object_wait_rendering(&obj->base, true); | |
3622 | if (ret) | |
3623 | return ret; | |
3624 | } | |
3625 | } | |
3626 | ||
3627 | return 0; | |
3628 | } | |
3629 | ||
673a394b EA |
3630 | /* Throttle our rendering by waiting until the ring has completed our requests |
3631 | * emitted over 20 msec ago. | |
3632 | * | |
b962442e EA |
3633 | * Note that if we were to use the current jiffies each time around the loop, |
3634 | * we wouldn't escape the function with any frames outstanding if the time to | |
3635 | * render a frame was over 20ms. | |
3636 | * | |
673a394b EA |
3637 | * This should get us reasonable parallelism between CPU and GPU but also |
3638 | * relatively low latency when blocking on a particular request to finish. | |
3639 | */ | |
40a5f0de | 3640 | static int |
f787a5f5 | 3641 | i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file) |
40a5f0de | 3642 | { |
f787a5f5 CW |
3643 | struct drm_i915_private *dev_priv = dev->dev_private; |
3644 | struct drm_i915_file_private *file_priv = file->driver_priv; | |
b962442e | 3645 | unsigned long recent_enough = jiffies - msecs_to_jiffies(20); |
f787a5f5 CW |
3646 | struct drm_i915_gem_request *request; |
3647 | struct intel_ring_buffer *ring = NULL; | |
3648 | u32 seqno = 0; | |
3649 | int ret; | |
93533c29 | 3650 | |
1c25595f | 3651 | spin_lock(&file_priv->mm.lock); |
f787a5f5 | 3652 | list_for_each_entry(request, &file_priv->mm.request_list, client_list) { |
b962442e EA |
3653 | if (time_after_eq(request->emitted_jiffies, recent_enough)) |
3654 | break; | |
40a5f0de | 3655 | |
f787a5f5 CW |
3656 | ring = request->ring; |
3657 | seqno = request->seqno; | |
b962442e | 3658 | } |
1c25595f | 3659 | spin_unlock(&file_priv->mm.lock); |
40a5f0de | 3660 | |
f787a5f5 CW |
3661 | if (seqno == 0) |
3662 | return 0; | |
2bc43b5c | 3663 | |
f787a5f5 | 3664 | ret = 0; |
78501eac | 3665 | if (!i915_seqno_passed(ring->get_seqno(ring), seqno)) { |
f787a5f5 CW |
3666 | /* And wait for the seqno passing without holding any locks and |
3667 | * causing extra latency for others. This is safe as the irq | |
3668 | * generation is designed to be run atomically and so is | |
3669 | * lockless. | |
3670 | */ | |
78501eac | 3671 | ring->user_irq_get(ring); |
f787a5f5 | 3672 | ret = wait_event_interruptible(ring->irq_queue, |
78501eac | 3673 | i915_seqno_passed(ring->get_seqno(ring), seqno) |
f787a5f5 | 3674 | || atomic_read(&dev_priv->mm.wedged)); |
78501eac | 3675 | ring->user_irq_put(ring); |
40a5f0de | 3676 | |
f787a5f5 CW |
3677 | if (ret == 0 && atomic_read(&dev_priv->mm.wedged)) |
3678 | ret = -EIO; | |
40a5f0de EA |
3679 | } |
3680 | ||
f787a5f5 CW |
3681 | if (ret == 0) |
3682 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, 0); | |
40a5f0de EA |
3683 | |
3684 | return ret; | |
3685 | } | |
3686 | ||
83d60795 | 3687 | static int |
2549d6c2 CW |
3688 | i915_gem_check_execbuffer(struct drm_i915_gem_execbuffer2 *exec, |
3689 | uint64_t exec_offset) | |
83d60795 CW |
3690 | { |
3691 | uint32_t exec_start, exec_len; | |
3692 | ||
3693 | exec_start = (uint32_t) exec_offset + exec->batch_start_offset; | |
3694 | exec_len = (uint32_t) exec->batch_len; | |
3695 | ||
3696 | if ((exec_start | exec_len) & 0x7) | |
3697 | return -EINVAL; | |
3698 | ||
3699 | if (!exec_start) | |
3700 | return -EINVAL; | |
3701 | ||
3702 | return 0; | |
3703 | } | |
3704 | ||
6b95a207 | 3705 | static int |
2549d6c2 CW |
3706 | validate_exec_list(struct drm_i915_gem_exec_object2 *exec, |
3707 | int count) | |
6b95a207 | 3708 | { |
2549d6c2 | 3709 | int i; |
6b95a207 | 3710 | |
2549d6c2 CW |
3711 | for (i = 0; i < count; i++) { |
3712 | char __user *ptr = (char __user *)(uintptr_t)exec[i].relocs_ptr; | |
3713 | size_t length = exec[i].relocation_count * sizeof(struct drm_i915_gem_relocation_entry); | |
6b95a207 | 3714 | |
2549d6c2 CW |
3715 | if (!access_ok(VERIFY_READ, ptr, length)) |
3716 | return -EFAULT; | |
40a5f0de | 3717 | |
b5dc608c CW |
3718 | /* we may also need to update the presumed offsets */ |
3719 | if (!access_ok(VERIFY_WRITE, ptr, length)) | |
3720 | return -EFAULT; | |
3721 | ||
2549d6c2 CW |
3722 | if (fault_in_pages_readable(ptr, length)) |
3723 | return -EFAULT; | |
6b95a207 | 3724 | } |
6b95a207 | 3725 | |
83d60795 | 3726 | return 0; |
6b95a207 KH |
3727 | } |
3728 | ||
8dc5d147 | 3729 | static int |
76446cac | 3730 | i915_gem_do_execbuffer(struct drm_device *dev, void *data, |
9af90d19 | 3731 | struct drm_file *file, |
76446cac JB |
3732 | struct drm_i915_gem_execbuffer2 *args, |
3733 | struct drm_i915_gem_exec_object2 *exec_list) | |
673a394b EA |
3734 | { |
3735 | drm_i915_private_t *dev_priv = dev->dev_private; | |
673a394b EA |
3736 | struct drm_gem_object **object_list = NULL; |
3737 | struct drm_gem_object *batch_obj; | |
201361a5 | 3738 | struct drm_clip_rect *cliprects = NULL; |
8dc5d147 | 3739 | struct drm_i915_gem_request *request = NULL; |
9af90d19 | 3740 | int ret, i, flips; |
673a394b | 3741 | uint64_t exec_offset; |
673a394b | 3742 | |
852835f3 ZN |
3743 | struct intel_ring_buffer *ring = NULL; |
3744 | ||
30dbf0c0 CW |
3745 | ret = i915_gem_check_is_wedged(dev); |
3746 | if (ret) | |
3747 | return ret; | |
3748 | ||
2549d6c2 CW |
3749 | ret = validate_exec_list(exec_list, args->buffer_count); |
3750 | if (ret) | |
3751 | return ret; | |
3752 | ||
673a394b EA |
3753 | #if WATCH_EXEC |
3754 | DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n", | |
3755 | (int) args->buffers_ptr, args->buffer_count, args->batch_len); | |
3756 | #endif | |
549f7365 CW |
3757 | switch (args->flags & I915_EXEC_RING_MASK) { |
3758 | case I915_EXEC_DEFAULT: | |
3759 | case I915_EXEC_RENDER: | |
3760 | ring = &dev_priv->render_ring; | |
3761 | break; | |
3762 | case I915_EXEC_BSD: | |
d1b851fc | 3763 | if (!HAS_BSD(dev)) { |
549f7365 | 3764 | DRM_ERROR("execbuf with invalid ring (BSD)\n"); |
d1b851fc ZN |
3765 | return -EINVAL; |
3766 | } | |
3767 | ring = &dev_priv->bsd_ring; | |
549f7365 CW |
3768 | break; |
3769 | case I915_EXEC_BLT: | |
3770 | if (!HAS_BLT(dev)) { | |
3771 | DRM_ERROR("execbuf with invalid ring (BLT)\n"); | |
3772 | return -EINVAL; | |
3773 | } | |
3774 | ring = &dev_priv->blt_ring; | |
3775 | break; | |
3776 | default: | |
3777 | DRM_ERROR("execbuf with unknown ring: %d\n", | |
3778 | (int)(args->flags & I915_EXEC_RING_MASK)); | |
3779 | return -EINVAL; | |
d1b851fc ZN |
3780 | } |
3781 | ||
4f481ed2 EA |
3782 | if (args->buffer_count < 1) { |
3783 | DRM_ERROR("execbuf with %d buffers\n", args->buffer_count); | |
3784 | return -EINVAL; | |
3785 | } | |
c8e0f93a | 3786 | object_list = drm_malloc_ab(sizeof(*object_list), args->buffer_count); |
76446cac JB |
3787 | if (object_list == NULL) { |
3788 | DRM_ERROR("Failed to allocate object list for %d buffers\n", | |
673a394b EA |
3789 | args->buffer_count); |
3790 | ret = -ENOMEM; | |
3791 | goto pre_mutex_err; | |
3792 | } | |
673a394b | 3793 | |
201361a5 | 3794 | if (args->num_cliprects != 0) { |
9a298b2a EA |
3795 | cliprects = kcalloc(args->num_cliprects, sizeof(*cliprects), |
3796 | GFP_KERNEL); | |
a40e8d31 OA |
3797 | if (cliprects == NULL) { |
3798 | ret = -ENOMEM; | |
201361a5 | 3799 | goto pre_mutex_err; |
a40e8d31 | 3800 | } |
201361a5 EA |
3801 | |
3802 | ret = copy_from_user(cliprects, | |
3803 | (struct drm_clip_rect __user *) | |
3804 | (uintptr_t) args->cliprects_ptr, | |
3805 | sizeof(*cliprects) * args->num_cliprects); | |
3806 | if (ret != 0) { | |
3807 | DRM_ERROR("copy %d cliprects failed: %d\n", | |
3808 | args->num_cliprects, ret); | |
c877cdce | 3809 | ret = -EFAULT; |
201361a5 EA |
3810 | goto pre_mutex_err; |
3811 | } | |
3812 | } | |
3813 | ||
8dc5d147 CW |
3814 | request = kzalloc(sizeof(*request), GFP_KERNEL); |
3815 | if (request == NULL) { | |
3816 | ret = -ENOMEM; | |
40a5f0de | 3817 | goto pre_mutex_err; |
8dc5d147 | 3818 | } |
40a5f0de | 3819 | |
76c1dec1 CW |
3820 | ret = i915_mutex_lock_interruptible(dev); |
3821 | if (ret) | |
a198bc80 | 3822 | goto pre_mutex_err; |
673a394b EA |
3823 | |
3824 | if (dev_priv->mm.suspended) { | |
673a394b | 3825 | mutex_unlock(&dev->struct_mutex); |
a198bc80 CW |
3826 | ret = -EBUSY; |
3827 | goto pre_mutex_err; | |
673a394b EA |
3828 | } |
3829 | ||
ac94a962 | 3830 | /* Look up object handles */ |
673a394b | 3831 | for (i = 0; i < args->buffer_count; i++) { |
7e318e18 CW |
3832 | struct drm_i915_gem_object *obj_priv; |
3833 | ||
9af90d19 | 3834 | object_list[i] = drm_gem_object_lookup(dev, file, |
673a394b EA |
3835 | exec_list[i].handle); |
3836 | if (object_list[i] == NULL) { | |
3837 | DRM_ERROR("Invalid object handle %d at index %d\n", | |
3838 | exec_list[i].handle, i); | |
0ce907f8 CW |
3839 | /* prevent error path from reading uninitialized data */ |
3840 | args->buffer_count = i + 1; | |
bf79cb91 | 3841 | ret = -ENOENT; |
673a394b EA |
3842 | goto err; |
3843 | } | |
b70d11da | 3844 | |
23010e43 | 3845 | obj_priv = to_intel_bo(object_list[i]); |
b70d11da KH |
3846 | if (obj_priv->in_execbuffer) { |
3847 | DRM_ERROR("Object %p appears more than once in object list\n", | |
3848 | object_list[i]); | |
0ce907f8 CW |
3849 | /* prevent error path from reading uninitialized data */ |
3850 | args->buffer_count = i + 1; | |
bf79cb91 | 3851 | ret = -EINVAL; |
b70d11da KH |
3852 | goto err; |
3853 | } | |
3854 | obj_priv->in_execbuffer = true; | |
ac94a962 | 3855 | } |
673a394b | 3856 | |
9af90d19 CW |
3857 | /* Move the objects en-masse into the GTT, evicting if necessary. */ |
3858 | ret = i915_gem_execbuffer_pin(dev, file, | |
3859 | object_list, exec_list, | |
3860 | args->buffer_count); | |
3861 | if (ret) | |
3862 | goto err; | |
ac94a962 | 3863 | |
9af90d19 CW |
3864 | /* The objects are in their final locations, apply the relocations. */ |
3865 | for (i = 0; i < args->buffer_count; i++) { | |
3866 | struct drm_i915_gem_object *obj = to_intel_bo(object_list[i]); | |
3867 | obj->base.pending_read_domains = 0; | |
3868 | obj->base.pending_write_domain = 0; | |
3869 | ret = i915_gem_execbuffer_relocate(obj, file, &exec_list[i]); | |
3870 | if (ret) | |
ac94a962 | 3871 | goto err; |
673a394b EA |
3872 | } |
3873 | ||
3874 | /* Set the pending read domains for the batch buffer to COMMAND */ | |
3875 | batch_obj = object_list[args->buffer_count-1]; | |
5f26a2c7 CW |
3876 | if (batch_obj->pending_write_domain) { |
3877 | DRM_ERROR("Attempting to use self-modifying batch buffer\n"); | |
3878 | ret = -EINVAL; | |
3879 | goto err; | |
3880 | } | |
3881 | batch_obj->pending_read_domains |= I915_GEM_DOMAIN_COMMAND; | |
673a394b | 3882 | |
9af90d19 CW |
3883 | /* Sanity check the batch buffer */ |
3884 | exec_offset = to_intel_bo(batch_obj)->gtt_offset; | |
3885 | ret = i915_gem_check_execbuffer(args, exec_offset); | |
83d60795 CW |
3886 | if (ret != 0) { |
3887 | DRM_ERROR("execbuf with invalid offset/length\n"); | |
3888 | goto err; | |
3889 | } | |
3890 | ||
13b29289 CW |
3891 | ret = i915_gem_execbuffer_move_to_gpu(dev, file, ring, |
3892 | object_list, args->buffer_count); | |
3893 | if (ret) | |
3894 | goto err; | |
673a394b | 3895 | |
673a394b EA |
3896 | #if WATCH_COHERENCY |
3897 | for (i = 0; i < args->buffer_count; i++) { | |
3898 | i915_gem_object_check_coherency(object_list[i], | |
3899 | exec_list[i].handle); | |
3900 | } | |
3901 | #endif | |
3902 | ||
673a394b | 3903 | #if WATCH_EXEC |
6911a9b8 | 3904 | i915_gem_dump_object(batch_obj, |
673a394b EA |
3905 | args->batch_len, |
3906 | __func__, | |
3907 | ~0); | |
3908 | #endif | |
3909 | ||
e59f2bac CW |
3910 | /* Check for any pending flips. As we only maintain a flip queue depth |
3911 | * of 1, we can simply insert a WAIT for the next display flip prior | |
3912 | * to executing the batch and avoid stalling the CPU. | |
3913 | */ | |
3914 | flips = 0; | |
3915 | for (i = 0; i < args->buffer_count; i++) { | |
3916 | if (object_list[i]->write_domain) | |
3917 | flips |= atomic_read(&to_intel_bo(object_list[i])->pending_flip); | |
3918 | } | |
3919 | if (flips) { | |
3920 | int plane, flip_mask; | |
3921 | ||
3922 | for (plane = 0; flips >> plane; plane++) { | |
3923 | if (((flips >> plane) & 1) == 0) | |
3924 | continue; | |
3925 | ||
3926 | if (plane) | |
3927 | flip_mask = MI_WAIT_FOR_PLANE_B_FLIP; | |
3928 | else | |
3929 | flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; | |
3930 | ||
e1f99ce6 CW |
3931 | ret = intel_ring_begin(ring, 2); |
3932 | if (ret) | |
3933 | goto err; | |
3934 | ||
78501eac CW |
3935 | intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask); |
3936 | intel_ring_emit(ring, MI_NOOP); | |
3937 | intel_ring_advance(ring); | |
e59f2bac CW |
3938 | } |
3939 | } | |
3940 | ||
673a394b | 3941 | /* Exec the batchbuffer */ |
78501eac | 3942 | ret = ring->dispatch_execbuffer(ring, args, cliprects, exec_offset); |
673a394b EA |
3943 | if (ret) { |
3944 | DRM_ERROR("dispatch failed %d\n", ret); | |
3945 | goto err; | |
3946 | } | |
3947 | ||
673a394b EA |
3948 | for (i = 0; i < args->buffer_count; i++) { |
3949 | struct drm_gem_object *obj = object_list[i]; | |
673a394b | 3950 | |
7e318e18 CW |
3951 | obj->read_domains = obj->pending_read_domains; |
3952 | obj->write_domain = obj->pending_write_domain; | |
3953 | ||
617dbe27 | 3954 | i915_gem_object_move_to_active(obj, ring); |
7e318e18 CW |
3955 | if (obj->write_domain) { |
3956 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); | |
3957 | obj_priv->dirty = 1; | |
3958 | list_move_tail(&obj_priv->gpu_write_list, | |
64193406 | 3959 | &ring->gpu_write_list); |
7e318e18 CW |
3960 | intel_mark_busy(dev, obj); |
3961 | } | |
3962 | ||
3963 | trace_i915_gem_object_change_domain(obj, | |
3964 | obj->read_domains, | |
3965 | obj->write_domain); | |
673a394b | 3966 | } |
673a394b | 3967 | |
7e318e18 CW |
3968 | /* |
3969 | * Ensure that the commands in the batch buffer are | |
3970 | * finished before the interrupt fires | |
3971 | */ | |
3972 | i915_retire_commands(dev, ring); | |
3973 | ||
3cce469c CW |
3974 | if (i915_add_request(dev, file, request, ring)) |
3975 | ring->outstanding_lazy_request = true; | |
3976 | else | |
3977 | request = NULL; | |
673a394b | 3978 | |
673a394b | 3979 | err: |
b70d11da | 3980 | for (i = 0; i < args->buffer_count; i++) { |
7e318e18 CW |
3981 | if (object_list[i] == NULL) |
3982 | break; | |
3983 | ||
3984 | to_intel_bo(object_list[i])->in_execbuffer = false; | |
aad87dff | 3985 | drm_gem_object_unreference(object_list[i]); |
b70d11da | 3986 | } |
673a394b | 3987 | |
673a394b EA |
3988 | mutex_unlock(&dev->struct_mutex); |
3989 | ||
93533c29 | 3990 | pre_mutex_err: |
8e7d2b2c | 3991 | drm_free_large(object_list); |
9a298b2a | 3992 | kfree(cliprects); |
8dc5d147 | 3993 | kfree(request); |
673a394b EA |
3994 | |
3995 | return ret; | |
3996 | } | |
3997 | ||
76446cac JB |
3998 | /* |
3999 | * Legacy execbuffer just creates an exec2 list from the original exec object | |
4000 | * list array and passes it to the real function. | |
4001 | */ | |
4002 | int | |
4003 | i915_gem_execbuffer(struct drm_device *dev, void *data, | |
4004 | struct drm_file *file_priv) | |
4005 | { | |
4006 | struct drm_i915_gem_execbuffer *args = data; | |
4007 | struct drm_i915_gem_execbuffer2 exec2; | |
4008 | struct drm_i915_gem_exec_object *exec_list = NULL; | |
4009 | struct drm_i915_gem_exec_object2 *exec2_list = NULL; | |
4010 | int ret, i; | |
4011 | ||
4012 | #if WATCH_EXEC | |
4013 | DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n", | |
4014 | (int) args->buffers_ptr, args->buffer_count, args->batch_len); | |
4015 | #endif | |
4016 | ||
4017 | if (args->buffer_count < 1) { | |
4018 | DRM_ERROR("execbuf with %d buffers\n", args->buffer_count); | |
4019 | return -EINVAL; | |
4020 | } | |
4021 | ||
4022 | /* Copy in the exec list from userland */ | |
4023 | exec_list = drm_malloc_ab(sizeof(*exec_list), args->buffer_count); | |
4024 | exec2_list = drm_malloc_ab(sizeof(*exec2_list), args->buffer_count); | |
4025 | if (exec_list == NULL || exec2_list == NULL) { | |
4026 | DRM_ERROR("Failed to allocate exec list for %d buffers\n", | |
4027 | args->buffer_count); | |
4028 | drm_free_large(exec_list); | |
4029 | drm_free_large(exec2_list); | |
4030 | return -ENOMEM; | |
4031 | } | |
4032 | ret = copy_from_user(exec_list, | |
4033 | (struct drm_i915_relocation_entry __user *) | |
4034 | (uintptr_t) args->buffers_ptr, | |
4035 | sizeof(*exec_list) * args->buffer_count); | |
4036 | if (ret != 0) { | |
4037 | DRM_ERROR("copy %d exec entries failed %d\n", | |
4038 | args->buffer_count, ret); | |
4039 | drm_free_large(exec_list); | |
4040 | drm_free_large(exec2_list); | |
4041 | return -EFAULT; | |
4042 | } | |
4043 | ||
4044 | for (i = 0; i < args->buffer_count; i++) { | |
4045 | exec2_list[i].handle = exec_list[i].handle; | |
4046 | exec2_list[i].relocation_count = exec_list[i].relocation_count; | |
4047 | exec2_list[i].relocs_ptr = exec_list[i].relocs_ptr; | |
4048 | exec2_list[i].alignment = exec_list[i].alignment; | |
4049 | exec2_list[i].offset = exec_list[i].offset; | |
a6c45cf0 | 4050 | if (INTEL_INFO(dev)->gen < 4) |
76446cac JB |
4051 | exec2_list[i].flags = EXEC_OBJECT_NEEDS_FENCE; |
4052 | else | |
4053 | exec2_list[i].flags = 0; | |
4054 | } | |
4055 | ||
4056 | exec2.buffers_ptr = args->buffers_ptr; | |
4057 | exec2.buffer_count = args->buffer_count; | |
4058 | exec2.batch_start_offset = args->batch_start_offset; | |
4059 | exec2.batch_len = args->batch_len; | |
4060 | exec2.DR1 = args->DR1; | |
4061 | exec2.DR4 = args->DR4; | |
4062 | exec2.num_cliprects = args->num_cliprects; | |
4063 | exec2.cliprects_ptr = args->cliprects_ptr; | |
852835f3 | 4064 | exec2.flags = I915_EXEC_RENDER; |
76446cac JB |
4065 | |
4066 | ret = i915_gem_do_execbuffer(dev, data, file_priv, &exec2, exec2_list); | |
4067 | if (!ret) { | |
4068 | /* Copy the new buffer offsets back to the user's exec list. */ | |
4069 | for (i = 0; i < args->buffer_count; i++) | |
4070 | exec_list[i].offset = exec2_list[i].offset; | |
4071 | /* ... and back out to userspace */ | |
4072 | ret = copy_to_user((struct drm_i915_relocation_entry __user *) | |
4073 | (uintptr_t) args->buffers_ptr, | |
4074 | exec_list, | |
4075 | sizeof(*exec_list) * args->buffer_count); | |
4076 | if (ret) { | |
4077 | ret = -EFAULT; | |
4078 | DRM_ERROR("failed to copy %d exec entries " | |
4079 | "back to user (%d)\n", | |
4080 | args->buffer_count, ret); | |
4081 | } | |
76446cac JB |
4082 | } |
4083 | ||
4084 | drm_free_large(exec_list); | |
4085 | drm_free_large(exec2_list); | |
4086 | return ret; | |
4087 | } | |
4088 | ||
4089 | int | |
4090 | i915_gem_execbuffer2(struct drm_device *dev, void *data, | |
4091 | struct drm_file *file_priv) | |
4092 | { | |
4093 | struct drm_i915_gem_execbuffer2 *args = data; | |
4094 | struct drm_i915_gem_exec_object2 *exec2_list = NULL; | |
4095 | int ret; | |
4096 | ||
4097 | #if WATCH_EXEC | |
4098 | DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n", | |
4099 | (int) args->buffers_ptr, args->buffer_count, args->batch_len); | |
4100 | #endif | |
4101 | ||
4102 | if (args->buffer_count < 1) { | |
4103 | DRM_ERROR("execbuf2 with %d buffers\n", args->buffer_count); | |
4104 | return -EINVAL; | |
4105 | } | |
4106 | ||
4107 | exec2_list = drm_malloc_ab(sizeof(*exec2_list), args->buffer_count); | |
4108 | if (exec2_list == NULL) { | |
4109 | DRM_ERROR("Failed to allocate exec list for %d buffers\n", | |
4110 | args->buffer_count); | |
4111 | return -ENOMEM; | |
4112 | } | |
4113 | ret = copy_from_user(exec2_list, | |
4114 | (struct drm_i915_relocation_entry __user *) | |
4115 | (uintptr_t) args->buffers_ptr, | |
4116 | sizeof(*exec2_list) * args->buffer_count); | |
4117 | if (ret != 0) { | |
4118 | DRM_ERROR("copy %d exec entries failed %d\n", | |
4119 | args->buffer_count, ret); | |
4120 | drm_free_large(exec2_list); | |
4121 | return -EFAULT; | |
4122 | } | |
4123 | ||
4124 | ret = i915_gem_do_execbuffer(dev, data, file_priv, args, exec2_list); | |
4125 | if (!ret) { | |
4126 | /* Copy the new buffer offsets back to the user's exec list. */ | |
4127 | ret = copy_to_user((struct drm_i915_relocation_entry __user *) | |
4128 | (uintptr_t) args->buffers_ptr, | |
4129 | exec2_list, | |
4130 | sizeof(*exec2_list) * args->buffer_count); | |
4131 | if (ret) { | |
4132 | ret = -EFAULT; | |
4133 | DRM_ERROR("failed to copy %d exec entries " | |
4134 | "back to user (%d)\n", | |
4135 | args->buffer_count, ret); | |
4136 | } | |
4137 | } | |
4138 | ||
4139 | drm_free_large(exec2_list); | |
4140 | return ret; | |
4141 | } | |
4142 | ||
673a394b | 4143 | int |
920afa77 | 4144 | i915_gem_object_pin(struct drm_gem_object *obj, uint32_t alignment, |
75e9e915 | 4145 | bool map_and_fenceable) |
673a394b EA |
4146 | { |
4147 | struct drm_device *dev = obj->dev; | |
f13d3f73 | 4148 | struct drm_i915_private *dev_priv = dev->dev_private; |
23010e43 | 4149 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
673a394b EA |
4150 | int ret; |
4151 | ||
778c3544 | 4152 | BUG_ON(obj_priv->pin_count == DRM_I915_GEM_OBJECT_MAX_PIN_COUNT); |
75e9e915 | 4153 | BUG_ON(map_and_fenceable && !map_and_fenceable); |
23bc5982 | 4154 | WARN_ON(i915_verify_lists(dev)); |
ac0c6b5a CW |
4155 | |
4156 | if (obj_priv->gtt_space != NULL) { | |
a00b10c3 | 4157 | if ((alignment && obj_priv->gtt_offset & (alignment - 1)) || |
75e9e915 | 4158 | (map_and_fenceable && !obj_priv->map_and_fenceable)) { |
ae7d49d8 CW |
4159 | WARN(obj_priv->pin_count, |
4160 | "bo is already pinned with incorrect alignment:" | |
75e9e915 DV |
4161 | " offset=%x, req.alignment=%x, req.map_and_fenceable=%d," |
4162 | " obj->map_and_fenceable=%d\n", | |
a00b10c3 | 4163 | obj_priv->gtt_offset, alignment, |
75e9e915 DV |
4164 | map_and_fenceable, |
4165 | obj_priv->map_and_fenceable); | |
ac0c6b5a CW |
4166 | ret = i915_gem_object_unbind(obj); |
4167 | if (ret) | |
4168 | return ret; | |
4169 | } | |
4170 | } | |
4171 | ||
673a394b | 4172 | if (obj_priv->gtt_space == NULL) { |
a00b10c3 | 4173 | ret = i915_gem_object_bind_to_gtt(obj, alignment, |
75e9e915 | 4174 | map_and_fenceable); |
9731129c | 4175 | if (ret) |
673a394b | 4176 | return ret; |
22c344e9 | 4177 | } |
76446cac | 4178 | |
7465378f | 4179 | if (obj_priv->pin_count++ == 0) { |
75e9e915 | 4180 | i915_gem_info_add_pin(dev_priv, obj_priv, map_and_fenceable); |
f13d3f73 | 4181 | if (!obj_priv->active) |
69dc4987 | 4182 | list_move_tail(&obj_priv->mm_list, |
f13d3f73 | 4183 | &dev_priv->mm.pinned_list); |
673a394b | 4184 | } |
75e9e915 | 4185 | BUG_ON(!obj_priv->pin_mappable && map_and_fenceable); |
673a394b | 4186 | |
23bc5982 | 4187 | WARN_ON(i915_verify_lists(dev)); |
673a394b EA |
4188 | return 0; |
4189 | } | |
4190 | ||
4191 | void | |
4192 | i915_gem_object_unpin(struct drm_gem_object *obj) | |
4193 | { | |
4194 | struct drm_device *dev = obj->dev; | |
4195 | drm_i915_private_t *dev_priv = dev->dev_private; | |
23010e43 | 4196 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
673a394b | 4197 | |
23bc5982 | 4198 | WARN_ON(i915_verify_lists(dev)); |
7465378f | 4199 | BUG_ON(obj_priv->pin_count == 0); |
673a394b EA |
4200 | BUG_ON(obj_priv->gtt_space == NULL); |
4201 | ||
7465378f | 4202 | if (--obj_priv->pin_count == 0) { |
f13d3f73 | 4203 | if (!obj_priv->active) |
69dc4987 | 4204 | list_move_tail(&obj_priv->mm_list, |
673a394b | 4205 | &dev_priv->mm.inactive_list); |
a00b10c3 | 4206 | i915_gem_info_remove_pin(dev_priv, obj_priv); |
673a394b | 4207 | } |
23bc5982 | 4208 | WARN_ON(i915_verify_lists(dev)); |
673a394b EA |
4209 | } |
4210 | ||
4211 | int | |
4212 | i915_gem_pin_ioctl(struct drm_device *dev, void *data, | |
4213 | struct drm_file *file_priv) | |
4214 | { | |
4215 | struct drm_i915_gem_pin *args = data; | |
4216 | struct drm_gem_object *obj; | |
4217 | struct drm_i915_gem_object *obj_priv; | |
4218 | int ret; | |
4219 | ||
1d7cfea1 CW |
4220 | ret = i915_mutex_lock_interruptible(dev); |
4221 | if (ret) | |
4222 | return ret; | |
673a394b EA |
4223 | |
4224 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); | |
4225 | if (obj == NULL) { | |
1d7cfea1 CW |
4226 | ret = -ENOENT; |
4227 | goto unlock; | |
673a394b | 4228 | } |
23010e43 | 4229 | obj_priv = to_intel_bo(obj); |
673a394b | 4230 | |
bb6baf76 CW |
4231 | if (obj_priv->madv != I915_MADV_WILLNEED) { |
4232 | DRM_ERROR("Attempting to pin a purgeable buffer\n"); | |
1d7cfea1 CW |
4233 | ret = -EINVAL; |
4234 | goto out; | |
3ef94daa CW |
4235 | } |
4236 | ||
79e53945 JB |
4237 | if (obj_priv->pin_filp != NULL && obj_priv->pin_filp != file_priv) { |
4238 | DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n", | |
4239 | args->handle); | |
1d7cfea1 CW |
4240 | ret = -EINVAL; |
4241 | goto out; | |
79e53945 JB |
4242 | } |
4243 | ||
4244 | obj_priv->user_pin_count++; | |
4245 | obj_priv->pin_filp = file_priv; | |
4246 | if (obj_priv->user_pin_count == 1) { | |
75e9e915 | 4247 | ret = i915_gem_object_pin(obj, args->alignment, true); |
1d7cfea1 CW |
4248 | if (ret) |
4249 | goto out; | |
673a394b EA |
4250 | } |
4251 | ||
4252 | /* XXX - flush the CPU caches for pinned objects | |
4253 | * as the X server doesn't manage domains yet | |
4254 | */ | |
e47c68e9 | 4255 | i915_gem_object_flush_cpu_write_domain(obj); |
673a394b | 4256 | args->offset = obj_priv->gtt_offset; |
1d7cfea1 | 4257 | out: |
673a394b | 4258 | drm_gem_object_unreference(obj); |
1d7cfea1 | 4259 | unlock: |
673a394b | 4260 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 4261 | return ret; |
673a394b EA |
4262 | } |
4263 | ||
4264 | int | |
4265 | i915_gem_unpin_ioctl(struct drm_device *dev, void *data, | |
4266 | struct drm_file *file_priv) | |
4267 | { | |
4268 | struct drm_i915_gem_pin *args = data; | |
4269 | struct drm_gem_object *obj; | |
79e53945 | 4270 | struct drm_i915_gem_object *obj_priv; |
76c1dec1 | 4271 | int ret; |
673a394b | 4272 | |
1d7cfea1 CW |
4273 | ret = i915_mutex_lock_interruptible(dev); |
4274 | if (ret) | |
4275 | return ret; | |
673a394b EA |
4276 | |
4277 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); | |
4278 | if (obj == NULL) { | |
1d7cfea1 CW |
4279 | ret = -ENOENT; |
4280 | goto unlock; | |
673a394b | 4281 | } |
23010e43 | 4282 | obj_priv = to_intel_bo(obj); |
76c1dec1 | 4283 | |
79e53945 JB |
4284 | if (obj_priv->pin_filp != file_priv) { |
4285 | DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n", | |
4286 | args->handle); | |
1d7cfea1 CW |
4287 | ret = -EINVAL; |
4288 | goto out; | |
79e53945 JB |
4289 | } |
4290 | obj_priv->user_pin_count--; | |
4291 | if (obj_priv->user_pin_count == 0) { | |
4292 | obj_priv->pin_filp = NULL; | |
4293 | i915_gem_object_unpin(obj); | |
4294 | } | |
673a394b | 4295 | |
1d7cfea1 | 4296 | out: |
673a394b | 4297 | drm_gem_object_unreference(obj); |
1d7cfea1 | 4298 | unlock: |
673a394b | 4299 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 4300 | return ret; |
673a394b EA |
4301 | } |
4302 | ||
4303 | int | |
4304 | i915_gem_busy_ioctl(struct drm_device *dev, void *data, | |
4305 | struct drm_file *file_priv) | |
4306 | { | |
4307 | struct drm_i915_gem_busy *args = data; | |
4308 | struct drm_gem_object *obj; | |
4309 | struct drm_i915_gem_object *obj_priv; | |
30dbf0c0 CW |
4310 | int ret; |
4311 | ||
76c1dec1 | 4312 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 4313 | if (ret) |
76c1dec1 | 4314 | return ret; |
673a394b | 4315 | |
673a394b EA |
4316 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); |
4317 | if (obj == NULL) { | |
1d7cfea1 CW |
4318 | ret = -ENOENT; |
4319 | goto unlock; | |
673a394b | 4320 | } |
1d7cfea1 | 4321 | obj_priv = to_intel_bo(obj); |
d1b851fc | 4322 | |
0be555b6 CW |
4323 | /* Count all active objects as busy, even if they are currently not used |
4324 | * by the gpu. Users of this interface expect objects to eventually | |
4325 | * become non-busy without any further actions, therefore emit any | |
4326 | * necessary flushes here. | |
c4de0a5d | 4327 | */ |
0be555b6 CW |
4328 | args->busy = obj_priv->active; |
4329 | if (args->busy) { | |
4330 | /* Unconditionally flush objects, even when the gpu still uses this | |
4331 | * object. Userspace calling this function indicates that it wants to | |
4332 | * use this buffer rather sooner than later, so issuing the required | |
4333 | * flush earlier is beneficial. | |
4334 | */ | |
c78ec30b CW |
4335 | if (obj->write_domain & I915_GEM_GPU_DOMAINS) |
4336 | i915_gem_flush_ring(dev, file_priv, | |
9220434a CW |
4337 | obj_priv->ring, |
4338 | 0, obj->write_domain); | |
0be555b6 CW |
4339 | |
4340 | /* Update the active list for the hardware's current position. | |
4341 | * Otherwise this only updates on a delayed timer or when irqs | |
4342 | * are actually unmasked, and our working set ends up being | |
4343 | * larger than required. | |
4344 | */ | |
4345 | i915_gem_retire_requests_ring(dev, obj_priv->ring); | |
4346 | ||
4347 | args->busy = obj_priv->active; | |
4348 | } | |
673a394b EA |
4349 | |
4350 | drm_gem_object_unreference(obj); | |
1d7cfea1 | 4351 | unlock: |
673a394b | 4352 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 4353 | return ret; |
673a394b EA |
4354 | } |
4355 | ||
4356 | int | |
4357 | i915_gem_throttle_ioctl(struct drm_device *dev, void *data, | |
4358 | struct drm_file *file_priv) | |
4359 | { | |
4360 | return i915_gem_ring_throttle(dev, file_priv); | |
4361 | } | |
4362 | ||
3ef94daa CW |
4363 | int |
4364 | i915_gem_madvise_ioctl(struct drm_device *dev, void *data, | |
4365 | struct drm_file *file_priv) | |
4366 | { | |
4367 | struct drm_i915_gem_madvise *args = data; | |
4368 | struct drm_gem_object *obj; | |
4369 | struct drm_i915_gem_object *obj_priv; | |
76c1dec1 | 4370 | int ret; |
3ef94daa CW |
4371 | |
4372 | switch (args->madv) { | |
4373 | case I915_MADV_DONTNEED: | |
4374 | case I915_MADV_WILLNEED: | |
4375 | break; | |
4376 | default: | |
4377 | return -EINVAL; | |
4378 | } | |
4379 | ||
1d7cfea1 CW |
4380 | ret = i915_mutex_lock_interruptible(dev); |
4381 | if (ret) | |
4382 | return ret; | |
4383 | ||
3ef94daa CW |
4384 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); |
4385 | if (obj == NULL) { | |
1d7cfea1 CW |
4386 | ret = -ENOENT; |
4387 | goto unlock; | |
3ef94daa | 4388 | } |
23010e43 | 4389 | obj_priv = to_intel_bo(obj); |
3ef94daa CW |
4390 | |
4391 | if (obj_priv->pin_count) { | |
1d7cfea1 CW |
4392 | ret = -EINVAL; |
4393 | goto out; | |
3ef94daa CW |
4394 | } |
4395 | ||
bb6baf76 CW |
4396 | if (obj_priv->madv != __I915_MADV_PURGED) |
4397 | obj_priv->madv = args->madv; | |
3ef94daa | 4398 | |
2d7ef395 CW |
4399 | /* if the object is no longer bound, discard its backing storage */ |
4400 | if (i915_gem_object_is_purgeable(obj_priv) && | |
4401 | obj_priv->gtt_space == NULL) | |
4402 | i915_gem_object_truncate(obj); | |
4403 | ||
bb6baf76 CW |
4404 | args->retained = obj_priv->madv != __I915_MADV_PURGED; |
4405 | ||
1d7cfea1 | 4406 | out: |
3ef94daa | 4407 | drm_gem_object_unreference(obj); |
1d7cfea1 | 4408 | unlock: |
3ef94daa | 4409 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 4410 | return ret; |
3ef94daa CW |
4411 | } |
4412 | ||
ac52bc56 DV |
4413 | struct drm_gem_object * i915_gem_alloc_object(struct drm_device *dev, |
4414 | size_t size) | |
4415 | { | |
73aa808f | 4416 | struct drm_i915_private *dev_priv = dev->dev_private; |
c397b908 | 4417 | struct drm_i915_gem_object *obj; |
ac52bc56 | 4418 | |
c397b908 DV |
4419 | obj = kzalloc(sizeof(*obj), GFP_KERNEL); |
4420 | if (obj == NULL) | |
4421 | return NULL; | |
673a394b | 4422 | |
c397b908 DV |
4423 | if (drm_gem_object_init(dev, &obj->base, size) != 0) { |
4424 | kfree(obj); | |
4425 | return NULL; | |
4426 | } | |
673a394b | 4427 | |
73aa808f CW |
4428 | i915_gem_info_add_obj(dev_priv, size); |
4429 | ||
c397b908 DV |
4430 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; |
4431 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; | |
673a394b | 4432 | |
c397b908 | 4433 | obj->agp_type = AGP_USER_MEMORY; |
62b8b215 | 4434 | obj->base.driver_private = NULL; |
c397b908 | 4435 | obj->fence_reg = I915_FENCE_REG_NONE; |
69dc4987 CW |
4436 | INIT_LIST_HEAD(&obj->mm_list); |
4437 | INIT_LIST_HEAD(&obj->ring_list); | |
c397b908 | 4438 | INIT_LIST_HEAD(&obj->gpu_write_list); |
c397b908 | 4439 | obj->madv = I915_MADV_WILLNEED; |
75e9e915 DV |
4440 | /* Avoid an unnecessary call to unbind on the first bind. */ |
4441 | obj->map_and_fenceable = true; | |
de151cf6 | 4442 | |
c397b908 DV |
4443 | return &obj->base; |
4444 | } | |
4445 | ||
4446 | int i915_gem_init_object(struct drm_gem_object *obj) | |
4447 | { | |
4448 | BUG(); | |
de151cf6 | 4449 | |
673a394b EA |
4450 | return 0; |
4451 | } | |
4452 | ||
be72615b | 4453 | static void i915_gem_free_object_tail(struct drm_gem_object *obj) |
673a394b | 4454 | { |
de151cf6 | 4455 | struct drm_device *dev = obj->dev; |
be72615b | 4456 | drm_i915_private_t *dev_priv = dev->dev_private; |
23010e43 | 4457 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
be72615b | 4458 | int ret; |
673a394b | 4459 | |
be72615b CW |
4460 | ret = i915_gem_object_unbind(obj); |
4461 | if (ret == -ERESTARTSYS) { | |
69dc4987 | 4462 | list_move(&obj_priv->mm_list, |
be72615b CW |
4463 | &dev_priv->mm.deferred_free_list); |
4464 | return; | |
4465 | } | |
673a394b | 4466 | |
39a01d1f | 4467 | if (obj->map_list.map) |
7e616158 | 4468 | i915_gem_free_mmap_offset(obj); |
de151cf6 | 4469 | |
c397b908 | 4470 | drm_gem_object_release(obj); |
73aa808f | 4471 | i915_gem_info_remove_obj(dev_priv, obj->size); |
c397b908 | 4472 | |
9a298b2a | 4473 | kfree(obj_priv->page_cpu_valid); |
280b713b | 4474 | kfree(obj_priv->bit_17); |
c397b908 | 4475 | kfree(obj_priv); |
673a394b EA |
4476 | } |
4477 | ||
be72615b CW |
4478 | void i915_gem_free_object(struct drm_gem_object *obj) |
4479 | { | |
4480 | struct drm_device *dev = obj->dev; | |
4481 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); | |
4482 | ||
4483 | trace_i915_gem_object_destroy(obj); | |
4484 | ||
4485 | while (obj_priv->pin_count > 0) | |
4486 | i915_gem_object_unpin(obj); | |
4487 | ||
4488 | if (obj_priv->phys_obj) | |
4489 | i915_gem_detach_phys_object(dev, obj); | |
4490 | ||
4491 | i915_gem_free_object_tail(obj); | |
4492 | } | |
4493 | ||
29105ccc CW |
4494 | int |
4495 | i915_gem_idle(struct drm_device *dev) | |
4496 | { | |
4497 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4498 | int ret; | |
28dfe52a | 4499 | |
29105ccc | 4500 | mutex_lock(&dev->struct_mutex); |
1c5d22f7 | 4501 | |
87acb0a5 | 4502 | if (dev_priv->mm.suspended) { |
29105ccc CW |
4503 | mutex_unlock(&dev->struct_mutex); |
4504 | return 0; | |
28dfe52a EA |
4505 | } |
4506 | ||
29105ccc | 4507 | ret = i915_gpu_idle(dev); |
6dbe2772 KP |
4508 | if (ret) { |
4509 | mutex_unlock(&dev->struct_mutex); | |
673a394b | 4510 | return ret; |
6dbe2772 | 4511 | } |
673a394b | 4512 | |
29105ccc CW |
4513 | /* Under UMS, be paranoid and evict. */ |
4514 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) { | |
5eac3ab4 | 4515 | ret = i915_gem_evict_inactive(dev, false); |
29105ccc CW |
4516 | if (ret) { |
4517 | mutex_unlock(&dev->struct_mutex); | |
4518 | return ret; | |
4519 | } | |
4520 | } | |
4521 | ||
4522 | /* Hack! Don't let anybody do execbuf while we don't control the chip. | |
4523 | * We need to replace this with a semaphore, or something. | |
4524 | * And not confound mm.suspended! | |
4525 | */ | |
4526 | dev_priv->mm.suspended = 1; | |
bc0c7f14 | 4527 | del_timer_sync(&dev_priv->hangcheck_timer); |
29105ccc CW |
4528 | |
4529 | i915_kernel_lost_context(dev); | |
6dbe2772 | 4530 | i915_gem_cleanup_ringbuffer(dev); |
29105ccc | 4531 | |
6dbe2772 KP |
4532 | mutex_unlock(&dev->struct_mutex); |
4533 | ||
29105ccc CW |
4534 | /* Cancel the retire work handler, which should be idle now. */ |
4535 | cancel_delayed_work_sync(&dev_priv->mm.retire_work); | |
4536 | ||
673a394b EA |
4537 | return 0; |
4538 | } | |
4539 | ||
e552eb70 JB |
4540 | /* |
4541 | * 965+ support PIPE_CONTROL commands, which provide finer grained control | |
4542 | * over cache flushing. | |
4543 | */ | |
8187a2b7 | 4544 | static int |
e552eb70 JB |
4545 | i915_gem_init_pipe_control(struct drm_device *dev) |
4546 | { | |
4547 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4548 | struct drm_gem_object *obj; | |
4549 | struct drm_i915_gem_object *obj_priv; | |
4550 | int ret; | |
4551 | ||
34dc4d44 | 4552 | obj = i915_gem_alloc_object(dev, 4096); |
e552eb70 JB |
4553 | if (obj == NULL) { |
4554 | DRM_ERROR("Failed to allocate seqno page\n"); | |
4555 | ret = -ENOMEM; | |
4556 | goto err; | |
4557 | } | |
4558 | obj_priv = to_intel_bo(obj); | |
4559 | obj_priv->agp_type = AGP_USER_CACHED_MEMORY; | |
4560 | ||
75e9e915 | 4561 | ret = i915_gem_object_pin(obj, 4096, true); |
e552eb70 JB |
4562 | if (ret) |
4563 | goto err_unref; | |
4564 | ||
4565 | dev_priv->seqno_gfx_addr = obj_priv->gtt_offset; | |
4566 | dev_priv->seqno_page = kmap(obj_priv->pages[0]); | |
4567 | if (dev_priv->seqno_page == NULL) | |
4568 | goto err_unpin; | |
4569 | ||
4570 | dev_priv->seqno_obj = obj; | |
4571 | memset(dev_priv->seqno_page, 0, PAGE_SIZE); | |
4572 | ||
4573 | return 0; | |
4574 | ||
4575 | err_unpin: | |
4576 | i915_gem_object_unpin(obj); | |
4577 | err_unref: | |
4578 | drm_gem_object_unreference(obj); | |
4579 | err: | |
4580 | return ret; | |
4581 | } | |
4582 | ||
8187a2b7 ZN |
4583 | |
4584 | static void | |
e552eb70 JB |
4585 | i915_gem_cleanup_pipe_control(struct drm_device *dev) |
4586 | { | |
4587 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4588 | struct drm_gem_object *obj; | |
4589 | struct drm_i915_gem_object *obj_priv; | |
4590 | ||
4591 | obj = dev_priv->seqno_obj; | |
4592 | obj_priv = to_intel_bo(obj); | |
4593 | kunmap(obj_priv->pages[0]); | |
4594 | i915_gem_object_unpin(obj); | |
4595 | drm_gem_object_unreference(obj); | |
4596 | dev_priv->seqno_obj = NULL; | |
4597 | ||
4598 | dev_priv->seqno_page = NULL; | |
673a394b EA |
4599 | } |
4600 | ||
8187a2b7 ZN |
4601 | int |
4602 | i915_gem_init_ringbuffer(struct drm_device *dev) | |
4603 | { | |
4604 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4605 | int ret; | |
68f95ba9 | 4606 | |
8187a2b7 ZN |
4607 | if (HAS_PIPE_CONTROL(dev)) { |
4608 | ret = i915_gem_init_pipe_control(dev); | |
4609 | if (ret) | |
4610 | return ret; | |
4611 | } | |
68f95ba9 | 4612 | |
5c1143bb | 4613 | ret = intel_init_render_ring_buffer(dev); |
68f95ba9 CW |
4614 | if (ret) |
4615 | goto cleanup_pipe_control; | |
4616 | ||
4617 | if (HAS_BSD(dev)) { | |
5c1143bb | 4618 | ret = intel_init_bsd_ring_buffer(dev); |
68f95ba9 CW |
4619 | if (ret) |
4620 | goto cleanup_render_ring; | |
d1b851fc | 4621 | } |
68f95ba9 | 4622 | |
549f7365 CW |
4623 | if (HAS_BLT(dev)) { |
4624 | ret = intel_init_blt_ring_buffer(dev); | |
4625 | if (ret) | |
4626 | goto cleanup_bsd_ring; | |
4627 | } | |
4628 | ||
6f392d54 CW |
4629 | dev_priv->next_seqno = 1; |
4630 | ||
68f95ba9 CW |
4631 | return 0; |
4632 | ||
549f7365 | 4633 | cleanup_bsd_ring: |
78501eac | 4634 | intel_cleanup_ring_buffer(&dev_priv->bsd_ring); |
68f95ba9 | 4635 | cleanup_render_ring: |
78501eac | 4636 | intel_cleanup_ring_buffer(&dev_priv->render_ring); |
68f95ba9 CW |
4637 | cleanup_pipe_control: |
4638 | if (HAS_PIPE_CONTROL(dev)) | |
4639 | i915_gem_cleanup_pipe_control(dev); | |
8187a2b7 ZN |
4640 | return ret; |
4641 | } | |
4642 | ||
4643 | void | |
4644 | i915_gem_cleanup_ringbuffer(struct drm_device *dev) | |
4645 | { | |
4646 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4647 | ||
78501eac CW |
4648 | intel_cleanup_ring_buffer(&dev_priv->render_ring); |
4649 | intel_cleanup_ring_buffer(&dev_priv->bsd_ring); | |
4650 | intel_cleanup_ring_buffer(&dev_priv->blt_ring); | |
8187a2b7 ZN |
4651 | if (HAS_PIPE_CONTROL(dev)) |
4652 | i915_gem_cleanup_pipe_control(dev); | |
4653 | } | |
4654 | ||
673a394b EA |
4655 | int |
4656 | i915_gem_entervt_ioctl(struct drm_device *dev, void *data, | |
4657 | struct drm_file *file_priv) | |
4658 | { | |
4659 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4660 | int ret; | |
4661 | ||
79e53945 JB |
4662 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
4663 | return 0; | |
4664 | ||
ba1234d1 | 4665 | if (atomic_read(&dev_priv->mm.wedged)) { |
673a394b | 4666 | DRM_ERROR("Reenabling wedged hardware, good luck\n"); |
ba1234d1 | 4667 | atomic_set(&dev_priv->mm.wedged, 0); |
673a394b EA |
4668 | } |
4669 | ||
673a394b | 4670 | mutex_lock(&dev->struct_mutex); |
9bb2d6f9 EA |
4671 | dev_priv->mm.suspended = 0; |
4672 | ||
4673 | ret = i915_gem_init_ringbuffer(dev); | |
d816f6ac WF |
4674 | if (ret != 0) { |
4675 | mutex_unlock(&dev->struct_mutex); | |
9bb2d6f9 | 4676 | return ret; |
d816f6ac | 4677 | } |
9bb2d6f9 | 4678 | |
69dc4987 | 4679 | BUG_ON(!list_empty(&dev_priv->mm.active_list)); |
852835f3 | 4680 | BUG_ON(!list_empty(&dev_priv->render_ring.active_list)); |
87acb0a5 | 4681 | BUG_ON(!list_empty(&dev_priv->bsd_ring.active_list)); |
549f7365 | 4682 | BUG_ON(!list_empty(&dev_priv->blt_ring.active_list)); |
673a394b EA |
4683 | BUG_ON(!list_empty(&dev_priv->mm.flushing_list)); |
4684 | BUG_ON(!list_empty(&dev_priv->mm.inactive_list)); | |
852835f3 | 4685 | BUG_ON(!list_empty(&dev_priv->render_ring.request_list)); |
87acb0a5 | 4686 | BUG_ON(!list_empty(&dev_priv->bsd_ring.request_list)); |
549f7365 | 4687 | BUG_ON(!list_empty(&dev_priv->blt_ring.request_list)); |
673a394b | 4688 | mutex_unlock(&dev->struct_mutex); |
dbb19d30 | 4689 | |
5f35308b CW |
4690 | ret = drm_irq_install(dev); |
4691 | if (ret) | |
4692 | goto cleanup_ringbuffer; | |
dbb19d30 | 4693 | |
673a394b | 4694 | return 0; |
5f35308b CW |
4695 | |
4696 | cleanup_ringbuffer: | |
4697 | mutex_lock(&dev->struct_mutex); | |
4698 | i915_gem_cleanup_ringbuffer(dev); | |
4699 | dev_priv->mm.suspended = 1; | |
4700 | mutex_unlock(&dev->struct_mutex); | |
4701 | ||
4702 | return ret; | |
673a394b EA |
4703 | } |
4704 | ||
4705 | int | |
4706 | i915_gem_leavevt_ioctl(struct drm_device *dev, void *data, | |
4707 | struct drm_file *file_priv) | |
4708 | { | |
79e53945 JB |
4709 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
4710 | return 0; | |
4711 | ||
dbb19d30 | 4712 | drm_irq_uninstall(dev); |
e6890f6f | 4713 | return i915_gem_idle(dev); |
673a394b EA |
4714 | } |
4715 | ||
4716 | void | |
4717 | i915_gem_lastclose(struct drm_device *dev) | |
4718 | { | |
4719 | int ret; | |
673a394b | 4720 | |
e806b495 EA |
4721 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
4722 | return; | |
4723 | ||
6dbe2772 KP |
4724 | ret = i915_gem_idle(dev); |
4725 | if (ret) | |
4726 | DRM_ERROR("failed to idle hardware: %d\n", ret); | |
673a394b EA |
4727 | } |
4728 | ||
64193406 CW |
4729 | static void |
4730 | init_ring_lists(struct intel_ring_buffer *ring) | |
4731 | { | |
4732 | INIT_LIST_HEAD(&ring->active_list); | |
4733 | INIT_LIST_HEAD(&ring->request_list); | |
4734 | INIT_LIST_HEAD(&ring->gpu_write_list); | |
4735 | } | |
4736 | ||
673a394b EA |
4737 | void |
4738 | i915_gem_load(struct drm_device *dev) | |
4739 | { | |
b5aa8a0f | 4740 | int i; |
673a394b EA |
4741 | drm_i915_private_t *dev_priv = dev->dev_private; |
4742 | ||
69dc4987 | 4743 | INIT_LIST_HEAD(&dev_priv->mm.active_list); |
673a394b EA |
4744 | INIT_LIST_HEAD(&dev_priv->mm.flushing_list); |
4745 | INIT_LIST_HEAD(&dev_priv->mm.inactive_list); | |
f13d3f73 | 4746 | INIT_LIST_HEAD(&dev_priv->mm.pinned_list); |
a09ba7fa | 4747 | INIT_LIST_HEAD(&dev_priv->mm.fence_list); |
be72615b | 4748 | INIT_LIST_HEAD(&dev_priv->mm.deferred_free_list); |
64193406 CW |
4749 | init_ring_lists(&dev_priv->render_ring); |
4750 | init_ring_lists(&dev_priv->bsd_ring); | |
4751 | init_ring_lists(&dev_priv->blt_ring); | |
007cc8ac DV |
4752 | for (i = 0; i < 16; i++) |
4753 | INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list); | |
673a394b EA |
4754 | INIT_DELAYED_WORK(&dev_priv->mm.retire_work, |
4755 | i915_gem_retire_work_handler); | |
30dbf0c0 | 4756 | init_completion(&dev_priv->error_completion); |
31169714 | 4757 | |
94400120 DA |
4758 | /* On GEN3 we really need to make sure the ARB C3 LP bit is set */ |
4759 | if (IS_GEN3(dev)) { | |
4760 | u32 tmp = I915_READ(MI_ARB_STATE); | |
4761 | if (!(tmp & MI_ARB_C3_LP_WRITE_ENABLE)) { | |
4762 | /* arb state is a masked write, so set bit + bit in mask */ | |
4763 | tmp = MI_ARB_C3_LP_WRITE_ENABLE | (MI_ARB_C3_LP_WRITE_ENABLE << MI_ARB_MASK_SHIFT); | |
4764 | I915_WRITE(MI_ARB_STATE, tmp); | |
4765 | } | |
4766 | } | |
4767 | ||
de151cf6 | 4768 | /* Old X drivers will take 0-2 for front, back, depth buffers */ |
b397c836 EA |
4769 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) |
4770 | dev_priv->fence_reg_start = 3; | |
de151cf6 | 4771 | |
a6c45cf0 | 4772 | if (INTEL_INFO(dev)->gen >= 4 || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) |
de151cf6 JB |
4773 | dev_priv->num_fence_regs = 16; |
4774 | else | |
4775 | dev_priv->num_fence_regs = 8; | |
4776 | ||
b5aa8a0f | 4777 | /* Initialize fence registers to zero */ |
a6c45cf0 CW |
4778 | switch (INTEL_INFO(dev)->gen) { |
4779 | case 6: | |
4780 | for (i = 0; i < 16; i++) | |
4781 | I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + (i * 8), 0); | |
4782 | break; | |
4783 | case 5: | |
4784 | case 4: | |
b5aa8a0f GH |
4785 | for (i = 0; i < 16; i++) |
4786 | I915_WRITE64(FENCE_REG_965_0 + (i * 8), 0); | |
a6c45cf0 CW |
4787 | break; |
4788 | case 3: | |
b5aa8a0f GH |
4789 | if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) |
4790 | for (i = 0; i < 8; i++) | |
4791 | I915_WRITE(FENCE_REG_945_8 + (i * 4), 0); | |
a6c45cf0 CW |
4792 | case 2: |
4793 | for (i = 0; i < 8; i++) | |
4794 | I915_WRITE(FENCE_REG_830_0 + (i * 4), 0); | |
4795 | break; | |
b5aa8a0f | 4796 | } |
673a394b | 4797 | i915_gem_detect_bit_6_swizzle(dev); |
6b95a207 | 4798 | init_waitqueue_head(&dev_priv->pending_flip_queue); |
17250b71 CW |
4799 | |
4800 | dev_priv->mm.inactive_shrinker.shrink = i915_gem_inactive_shrink; | |
4801 | dev_priv->mm.inactive_shrinker.seeks = DEFAULT_SEEKS; | |
4802 | register_shrinker(&dev_priv->mm.inactive_shrinker); | |
673a394b | 4803 | } |
71acb5eb DA |
4804 | |
4805 | /* | |
4806 | * Create a physically contiguous memory object for this object | |
4807 | * e.g. for cursor + overlay regs | |
4808 | */ | |
995b6762 CW |
4809 | static int i915_gem_init_phys_object(struct drm_device *dev, |
4810 | int id, int size, int align) | |
71acb5eb DA |
4811 | { |
4812 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4813 | struct drm_i915_gem_phys_object *phys_obj; | |
4814 | int ret; | |
4815 | ||
4816 | if (dev_priv->mm.phys_objs[id - 1] || !size) | |
4817 | return 0; | |
4818 | ||
9a298b2a | 4819 | phys_obj = kzalloc(sizeof(struct drm_i915_gem_phys_object), GFP_KERNEL); |
71acb5eb DA |
4820 | if (!phys_obj) |
4821 | return -ENOMEM; | |
4822 | ||
4823 | phys_obj->id = id; | |
4824 | ||
6eeefaf3 | 4825 | phys_obj->handle = drm_pci_alloc(dev, size, align); |
71acb5eb DA |
4826 | if (!phys_obj->handle) { |
4827 | ret = -ENOMEM; | |
4828 | goto kfree_obj; | |
4829 | } | |
4830 | #ifdef CONFIG_X86 | |
4831 | set_memory_wc((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE); | |
4832 | #endif | |
4833 | ||
4834 | dev_priv->mm.phys_objs[id - 1] = phys_obj; | |
4835 | ||
4836 | return 0; | |
4837 | kfree_obj: | |
9a298b2a | 4838 | kfree(phys_obj); |
71acb5eb DA |
4839 | return ret; |
4840 | } | |
4841 | ||
995b6762 | 4842 | static void i915_gem_free_phys_object(struct drm_device *dev, int id) |
71acb5eb DA |
4843 | { |
4844 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4845 | struct drm_i915_gem_phys_object *phys_obj; | |
4846 | ||
4847 | if (!dev_priv->mm.phys_objs[id - 1]) | |
4848 | return; | |
4849 | ||
4850 | phys_obj = dev_priv->mm.phys_objs[id - 1]; | |
4851 | if (phys_obj->cur_obj) { | |
4852 | i915_gem_detach_phys_object(dev, phys_obj->cur_obj); | |
4853 | } | |
4854 | ||
4855 | #ifdef CONFIG_X86 | |
4856 | set_memory_wb((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE); | |
4857 | #endif | |
4858 | drm_pci_free(dev, phys_obj->handle); | |
4859 | kfree(phys_obj); | |
4860 | dev_priv->mm.phys_objs[id - 1] = NULL; | |
4861 | } | |
4862 | ||
4863 | void i915_gem_free_all_phys_object(struct drm_device *dev) | |
4864 | { | |
4865 | int i; | |
4866 | ||
260883c8 | 4867 | for (i = I915_GEM_PHYS_CURSOR_0; i <= I915_MAX_PHYS_OBJECT; i++) |
71acb5eb DA |
4868 | i915_gem_free_phys_object(dev, i); |
4869 | } | |
4870 | ||
4871 | void i915_gem_detach_phys_object(struct drm_device *dev, | |
4872 | struct drm_gem_object *obj) | |
4873 | { | |
e5281ccd CW |
4874 | struct address_space *mapping = obj->filp->f_path.dentry->d_inode->i_mapping; |
4875 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); | |
4876 | char *vaddr; | |
71acb5eb | 4877 | int i; |
71acb5eb DA |
4878 | int page_count; |
4879 | ||
71acb5eb DA |
4880 | if (!obj_priv->phys_obj) |
4881 | return; | |
e5281ccd | 4882 | vaddr = obj_priv->phys_obj->handle->vaddr; |
71acb5eb DA |
4883 | |
4884 | page_count = obj->size / PAGE_SIZE; | |
4885 | ||
4886 | for (i = 0; i < page_count; i++) { | |
e5281ccd CW |
4887 | struct page *page = read_cache_page_gfp(mapping, i, |
4888 | GFP_HIGHUSER | __GFP_RECLAIMABLE); | |
4889 | if (!IS_ERR(page)) { | |
4890 | char *dst = kmap_atomic(page); | |
4891 | memcpy(dst, vaddr + i*PAGE_SIZE, PAGE_SIZE); | |
4892 | kunmap_atomic(dst); | |
4893 | ||
4894 | drm_clflush_pages(&page, 1); | |
4895 | ||
4896 | set_page_dirty(page); | |
4897 | mark_page_accessed(page); | |
4898 | page_cache_release(page); | |
4899 | } | |
71acb5eb | 4900 | } |
71acb5eb | 4901 | drm_agp_chipset_flush(dev); |
d78b47b9 | 4902 | |
71acb5eb DA |
4903 | obj_priv->phys_obj->cur_obj = NULL; |
4904 | obj_priv->phys_obj = NULL; | |
4905 | } | |
4906 | ||
4907 | int | |
4908 | i915_gem_attach_phys_object(struct drm_device *dev, | |
6eeefaf3 CW |
4909 | struct drm_gem_object *obj, |
4910 | int id, | |
4911 | int align) | |
71acb5eb | 4912 | { |
e5281ccd | 4913 | struct address_space *mapping = obj->filp->f_path.dentry->d_inode->i_mapping; |
71acb5eb DA |
4914 | drm_i915_private_t *dev_priv = dev->dev_private; |
4915 | struct drm_i915_gem_object *obj_priv; | |
4916 | int ret = 0; | |
4917 | int page_count; | |
4918 | int i; | |
4919 | ||
4920 | if (id > I915_MAX_PHYS_OBJECT) | |
4921 | return -EINVAL; | |
4922 | ||
23010e43 | 4923 | obj_priv = to_intel_bo(obj); |
71acb5eb DA |
4924 | |
4925 | if (obj_priv->phys_obj) { | |
4926 | if (obj_priv->phys_obj->id == id) | |
4927 | return 0; | |
4928 | i915_gem_detach_phys_object(dev, obj); | |
4929 | } | |
4930 | ||
71acb5eb DA |
4931 | /* create a new object */ |
4932 | if (!dev_priv->mm.phys_objs[id - 1]) { | |
4933 | ret = i915_gem_init_phys_object(dev, id, | |
6eeefaf3 | 4934 | obj->size, align); |
71acb5eb | 4935 | if (ret) { |
aeb565df | 4936 | DRM_ERROR("failed to init phys object %d size: %zu\n", id, obj->size); |
e5281ccd | 4937 | return ret; |
71acb5eb DA |
4938 | } |
4939 | } | |
4940 | ||
4941 | /* bind to the object */ | |
4942 | obj_priv->phys_obj = dev_priv->mm.phys_objs[id - 1]; | |
4943 | obj_priv->phys_obj->cur_obj = obj; | |
4944 | ||
71acb5eb DA |
4945 | page_count = obj->size / PAGE_SIZE; |
4946 | ||
4947 | for (i = 0; i < page_count; i++) { | |
e5281ccd CW |
4948 | struct page *page; |
4949 | char *dst, *src; | |
4950 | ||
4951 | page = read_cache_page_gfp(mapping, i, | |
4952 | GFP_HIGHUSER | __GFP_RECLAIMABLE); | |
4953 | if (IS_ERR(page)) | |
4954 | return PTR_ERR(page); | |
71acb5eb | 4955 | |
ff75b9bc | 4956 | src = kmap_atomic(page); |
e5281ccd | 4957 | dst = obj_priv->phys_obj->handle->vaddr + (i * PAGE_SIZE); |
71acb5eb | 4958 | memcpy(dst, src, PAGE_SIZE); |
3e4d3af5 | 4959 | kunmap_atomic(src); |
71acb5eb | 4960 | |
e5281ccd CW |
4961 | mark_page_accessed(page); |
4962 | page_cache_release(page); | |
4963 | } | |
d78b47b9 | 4964 | |
71acb5eb | 4965 | return 0; |
71acb5eb DA |
4966 | } |
4967 | ||
4968 | static int | |
4969 | i915_gem_phys_pwrite(struct drm_device *dev, struct drm_gem_object *obj, | |
4970 | struct drm_i915_gem_pwrite *args, | |
4971 | struct drm_file *file_priv) | |
4972 | { | |
23010e43 | 4973 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
71acb5eb DA |
4974 | void *obj_addr; |
4975 | int ret; | |
4976 | char __user *user_data; | |
4977 | ||
4978 | user_data = (char __user *) (uintptr_t) args->data_ptr; | |
4979 | obj_addr = obj_priv->phys_obj->handle->vaddr + args->offset; | |
4980 | ||
44d98a61 | 4981 | DRM_DEBUG_DRIVER("obj_addr %p, %lld\n", obj_addr, args->size); |
71acb5eb DA |
4982 | ret = copy_from_user(obj_addr, user_data, args->size); |
4983 | if (ret) | |
4984 | return -EFAULT; | |
4985 | ||
4986 | drm_agp_chipset_flush(dev); | |
4987 | return 0; | |
4988 | } | |
b962442e | 4989 | |
f787a5f5 | 4990 | void i915_gem_release(struct drm_device *dev, struct drm_file *file) |
b962442e | 4991 | { |
f787a5f5 | 4992 | struct drm_i915_file_private *file_priv = file->driver_priv; |
b962442e EA |
4993 | |
4994 | /* Clean up our request list when the client is going away, so that | |
4995 | * later retire_requests won't dereference our soon-to-be-gone | |
4996 | * file_priv. | |
4997 | */ | |
1c25595f | 4998 | spin_lock(&file_priv->mm.lock); |
f787a5f5 CW |
4999 | while (!list_empty(&file_priv->mm.request_list)) { |
5000 | struct drm_i915_gem_request *request; | |
5001 | ||
5002 | request = list_first_entry(&file_priv->mm.request_list, | |
5003 | struct drm_i915_gem_request, | |
5004 | client_list); | |
5005 | list_del(&request->client_list); | |
5006 | request->file_priv = NULL; | |
5007 | } | |
1c25595f | 5008 | spin_unlock(&file_priv->mm.lock); |
b962442e | 5009 | } |
31169714 | 5010 | |
1637ef41 CW |
5011 | static int |
5012 | i915_gpu_is_active(struct drm_device *dev) | |
5013 | { | |
5014 | drm_i915_private_t *dev_priv = dev->dev_private; | |
5015 | int lists_empty; | |
5016 | ||
1637ef41 | 5017 | lists_empty = list_empty(&dev_priv->mm.flushing_list) && |
17250b71 | 5018 | list_empty(&dev_priv->mm.active_list); |
1637ef41 CW |
5019 | |
5020 | return !lists_empty; | |
5021 | } | |
5022 | ||
31169714 | 5023 | static int |
17250b71 CW |
5024 | i915_gem_inactive_shrink(struct shrinker *shrinker, |
5025 | int nr_to_scan, | |
5026 | gfp_t gfp_mask) | |
31169714 | 5027 | { |
17250b71 CW |
5028 | struct drm_i915_private *dev_priv = |
5029 | container_of(shrinker, | |
5030 | struct drm_i915_private, | |
5031 | mm.inactive_shrinker); | |
5032 | struct drm_device *dev = dev_priv->dev; | |
5033 | struct drm_i915_gem_object *obj, *next; | |
5034 | int cnt; | |
5035 | ||
5036 | if (!mutex_trylock(&dev->struct_mutex)) | |
bbe2e11a | 5037 | return 0; |
31169714 CW |
5038 | |
5039 | /* "fast-path" to count number of available objects */ | |
5040 | if (nr_to_scan == 0) { | |
17250b71 CW |
5041 | cnt = 0; |
5042 | list_for_each_entry(obj, | |
5043 | &dev_priv->mm.inactive_list, | |
5044 | mm_list) | |
5045 | cnt++; | |
5046 | mutex_unlock(&dev->struct_mutex); | |
5047 | return cnt / 100 * sysctl_vfs_cache_pressure; | |
31169714 CW |
5048 | } |
5049 | ||
1637ef41 | 5050 | rescan: |
31169714 | 5051 | /* first scan for clean buffers */ |
17250b71 | 5052 | i915_gem_retire_requests(dev); |
31169714 | 5053 | |
17250b71 CW |
5054 | list_for_each_entry_safe(obj, next, |
5055 | &dev_priv->mm.inactive_list, | |
5056 | mm_list) { | |
5057 | if (i915_gem_object_is_purgeable(obj)) { | |
5058 | i915_gem_object_unbind(&obj->base); | |
5059 | if (--nr_to_scan == 0) | |
5060 | break; | |
31169714 | 5061 | } |
31169714 CW |
5062 | } |
5063 | ||
5064 | /* second pass, evict/count anything still on the inactive list */ | |
17250b71 CW |
5065 | cnt = 0; |
5066 | list_for_each_entry_safe(obj, next, | |
5067 | &dev_priv->mm.inactive_list, | |
5068 | mm_list) { | |
5069 | if (nr_to_scan) { | |
5070 | i915_gem_object_unbind(&obj->base); | |
5071 | nr_to_scan--; | |
5072 | } else | |
5073 | cnt++; | |
5074 | } | |
5075 | ||
5076 | if (nr_to_scan && i915_gpu_is_active(dev)) { | |
1637ef41 CW |
5077 | /* |
5078 | * We are desperate for pages, so as a last resort, wait | |
5079 | * for the GPU to finish and discard whatever we can. | |
5080 | * This has a dramatic impact to reduce the number of | |
5081 | * OOM-killer events whilst running the GPU aggressively. | |
5082 | */ | |
17250b71 | 5083 | if (i915_gpu_idle(dev) == 0) |
1637ef41 CW |
5084 | goto rescan; |
5085 | } | |
17250b71 CW |
5086 | mutex_unlock(&dev->struct_mutex); |
5087 | return cnt / 100 * sysctl_vfs_cache_pressure; | |
31169714 | 5088 | } |