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Commit | Line | Data |
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673a394b | 1 | /* |
be6a0376 | 2 | * Copyright © 2008-2015 Intel Corporation |
673a394b EA |
3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | * | |
26 | */ | |
27 | ||
760285e7 | 28 | #include <drm/drmP.h> |
0de23977 | 29 | #include <drm/drm_vma_manager.h> |
760285e7 | 30 | #include <drm/i915_drm.h> |
673a394b | 31 | #include "i915_drv.h" |
c13d87ea | 32 | #include "i915_gem_dmabuf.h" |
eb82289a | 33 | #include "i915_vgpu.h" |
1c5d22f7 | 34 | #include "i915_trace.h" |
652c393a | 35 | #include "intel_drv.h" |
0ccdacf6 | 36 | #include "intel_mocs.h" |
c13d87ea | 37 | #include <linux/reservation.h> |
5949eac4 | 38 | #include <linux/shmem_fs.h> |
5a0e3ad6 | 39 | #include <linux/slab.h> |
673a394b | 40 | #include <linux/swap.h> |
79e53945 | 41 | #include <linux/pci.h> |
1286ff73 | 42 | #include <linux/dma-buf.h> |
673a394b | 43 | |
05394f39 | 44 | static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj); |
e62b59e4 | 45 | static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj); |
c8725f3d | 46 | static void |
b4716185 CW |
47 | i915_gem_object_retire__write(struct drm_i915_gem_object *obj); |
48 | static void | |
7e21d648 | 49 | i915_gem_object_retire__read(struct drm_i915_gem_object *obj, int engine); |
61050808 | 50 | |
c76ce038 CW |
51 | static bool cpu_cache_is_coherent(struct drm_device *dev, |
52 | enum i915_cache_level level) | |
53 | { | |
54 | return HAS_LLC(dev) || level != I915_CACHE_NONE; | |
55 | } | |
56 | ||
2c22569b CW |
57 | static bool cpu_write_needs_clflush(struct drm_i915_gem_object *obj) |
58 | { | |
b50a5371 AS |
59 | if (obj->base.write_domain == I915_GEM_DOMAIN_CPU) |
60 | return false; | |
61 | ||
2c22569b CW |
62 | if (!cpu_cache_is_coherent(obj->base.dev, obj->cache_level)) |
63 | return true; | |
64 | ||
65 | return obj->pin_display; | |
66 | } | |
67 | ||
4f1959ee AS |
68 | static int |
69 | insert_mappable_node(struct drm_i915_private *i915, | |
70 | struct drm_mm_node *node, u32 size) | |
71 | { | |
72 | memset(node, 0, sizeof(*node)); | |
73 | return drm_mm_insert_node_in_range_generic(&i915->ggtt.base.mm, node, | |
74 | size, 0, 0, 0, | |
75 | i915->ggtt.mappable_end, | |
76 | DRM_MM_SEARCH_DEFAULT, | |
77 | DRM_MM_CREATE_DEFAULT); | |
78 | } | |
79 | ||
80 | static void | |
81 | remove_mappable_node(struct drm_mm_node *node) | |
82 | { | |
83 | drm_mm_remove_node(node); | |
84 | } | |
85 | ||
73aa808f CW |
86 | /* some bookkeeping */ |
87 | static void i915_gem_info_add_obj(struct drm_i915_private *dev_priv, | |
88 | size_t size) | |
89 | { | |
c20e8355 | 90 | spin_lock(&dev_priv->mm.object_stat_lock); |
73aa808f CW |
91 | dev_priv->mm.object_count++; |
92 | dev_priv->mm.object_memory += size; | |
c20e8355 | 93 | spin_unlock(&dev_priv->mm.object_stat_lock); |
73aa808f CW |
94 | } |
95 | ||
96 | static void i915_gem_info_remove_obj(struct drm_i915_private *dev_priv, | |
97 | size_t size) | |
98 | { | |
c20e8355 | 99 | spin_lock(&dev_priv->mm.object_stat_lock); |
73aa808f CW |
100 | dev_priv->mm.object_count--; |
101 | dev_priv->mm.object_memory -= size; | |
c20e8355 | 102 | spin_unlock(&dev_priv->mm.object_stat_lock); |
73aa808f CW |
103 | } |
104 | ||
21dd3734 | 105 | static int |
33196ded | 106 | i915_gem_wait_for_error(struct i915_gpu_error *error) |
30dbf0c0 | 107 | { |
30dbf0c0 CW |
108 | int ret; |
109 | ||
d98c52cf | 110 | if (!i915_reset_in_progress(error)) |
30dbf0c0 CW |
111 | return 0; |
112 | ||
0a6759c6 DV |
113 | /* |
114 | * Only wait 10 seconds for the gpu reset to complete to avoid hanging | |
115 | * userspace. If it takes that long something really bad is going on and | |
116 | * we should simply try to bail out and fail as gracefully as possible. | |
117 | */ | |
1f83fee0 | 118 | ret = wait_event_interruptible_timeout(error->reset_queue, |
d98c52cf | 119 | !i915_reset_in_progress(error), |
1f83fee0 | 120 | 10*HZ); |
0a6759c6 DV |
121 | if (ret == 0) { |
122 | DRM_ERROR("Timed out waiting for the gpu reset to complete\n"); | |
123 | return -EIO; | |
124 | } else if (ret < 0) { | |
30dbf0c0 | 125 | return ret; |
d98c52cf CW |
126 | } else { |
127 | return 0; | |
0a6759c6 | 128 | } |
30dbf0c0 CW |
129 | } |
130 | ||
54cf91dc | 131 | int i915_mutex_lock_interruptible(struct drm_device *dev) |
76c1dec1 | 132 | { |
fac5e23e | 133 | struct drm_i915_private *dev_priv = to_i915(dev); |
76c1dec1 CW |
134 | int ret; |
135 | ||
33196ded | 136 | ret = i915_gem_wait_for_error(&dev_priv->gpu_error); |
76c1dec1 CW |
137 | if (ret) |
138 | return ret; | |
139 | ||
140 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
141 | if (ret) | |
142 | return ret; | |
143 | ||
23bc5982 | 144 | WARN_ON(i915_verify_lists(dev)); |
76c1dec1 CW |
145 | return 0; |
146 | } | |
30dbf0c0 | 147 | |
5a125c3c EA |
148 | int |
149 | i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 150 | struct drm_file *file) |
5a125c3c | 151 | { |
72e96d64 | 152 | struct drm_i915_private *dev_priv = to_i915(dev); |
62106b4f | 153 | struct i915_ggtt *ggtt = &dev_priv->ggtt; |
72e96d64 | 154 | struct drm_i915_gem_get_aperture *args = data; |
ca1543be | 155 | struct i915_vma *vma; |
6299f992 | 156 | size_t pinned; |
5a125c3c | 157 | |
6299f992 | 158 | pinned = 0; |
73aa808f | 159 | mutex_lock(&dev->struct_mutex); |
1c7f4bca | 160 | list_for_each_entry(vma, &ggtt->base.active_list, vm_link) |
ca1543be TU |
161 | if (vma->pin_count) |
162 | pinned += vma->node.size; | |
1c7f4bca | 163 | list_for_each_entry(vma, &ggtt->base.inactive_list, vm_link) |
ca1543be TU |
164 | if (vma->pin_count) |
165 | pinned += vma->node.size; | |
73aa808f | 166 | mutex_unlock(&dev->struct_mutex); |
5a125c3c | 167 | |
72e96d64 | 168 | args->aper_size = ggtt->base.total; |
0206e353 | 169 | args->aper_available_size = args->aper_size - pinned; |
6299f992 | 170 | |
5a125c3c EA |
171 | return 0; |
172 | } | |
173 | ||
6a2c4232 CW |
174 | static int |
175 | i915_gem_object_get_pages_phys(struct drm_i915_gem_object *obj) | |
00731155 | 176 | { |
6a2c4232 CW |
177 | struct address_space *mapping = file_inode(obj->base.filp)->i_mapping; |
178 | char *vaddr = obj->phys_handle->vaddr; | |
179 | struct sg_table *st; | |
180 | struct scatterlist *sg; | |
181 | int i; | |
00731155 | 182 | |
6a2c4232 CW |
183 | if (WARN_ON(i915_gem_object_needs_bit17_swizzle(obj))) |
184 | return -EINVAL; | |
185 | ||
186 | for (i = 0; i < obj->base.size / PAGE_SIZE; i++) { | |
187 | struct page *page; | |
188 | char *src; | |
189 | ||
190 | page = shmem_read_mapping_page(mapping, i); | |
191 | if (IS_ERR(page)) | |
192 | return PTR_ERR(page); | |
193 | ||
194 | src = kmap_atomic(page); | |
195 | memcpy(vaddr, src, PAGE_SIZE); | |
196 | drm_clflush_virt_range(vaddr, PAGE_SIZE); | |
197 | kunmap_atomic(src); | |
198 | ||
09cbfeaf | 199 | put_page(page); |
6a2c4232 CW |
200 | vaddr += PAGE_SIZE; |
201 | } | |
202 | ||
c033666a | 203 | i915_gem_chipset_flush(to_i915(obj->base.dev)); |
6a2c4232 CW |
204 | |
205 | st = kmalloc(sizeof(*st), GFP_KERNEL); | |
206 | if (st == NULL) | |
207 | return -ENOMEM; | |
208 | ||
209 | if (sg_alloc_table(st, 1, GFP_KERNEL)) { | |
210 | kfree(st); | |
211 | return -ENOMEM; | |
212 | } | |
213 | ||
214 | sg = st->sgl; | |
215 | sg->offset = 0; | |
216 | sg->length = obj->base.size; | |
00731155 | 217 | |
6a2c4232 CW |
218 | sg_dma_address(sg) = obj->phys_handle->busaddr; |
219 | sg_dma_len(sg) = obj->base.size; | |
220 | ||
221 | obj->pages = st; | |
6a2c4232 CW |
222 | return 0; |
223 | } | |
224 | ||
225 | static void | |
226 | i915_gem_object_put_pages_phys(struct drm_i915_gem_object *obj) | |
227 | { | |
228 | int ret; | |
229 | ||
230 | BUG_ON(obj->madv == __I915_MADV_PURGED); | |
00731155 | 231 | |
6a2c4232 | 232 | ret = i915_gem_object_set_to_cpu_domain(obj, true); |
f4457ae7 | 233 | if (WARN_ON(ret)) { |
6a2c4232 CW |
234 | /* In the event of a disaster, abandon all caches and |
235 | * hope for the best. | |
236 | */ | |
6a2c4232 CW |
237 | obj->base.read_domains = obj->base.write_domain = I915_GEM_DOMAIN_CPU; |
238 | } | |
239 | ||
240 | if (obj->madv == I915_MADV_DONTNEED) | |
241 | obj->dirty = 0; | |
242 | ||
243 | if (obj->dirty) { | |
00731155 | 244 | struct address_space *mapping = file_inode(obj->base.filp)->i_mapping; |
6a2c4232 | 245 | char *vaddr = obj->phys_handle->vaddr; |
00731155 CW |
246 | int i; |
247 | ||
248 | for (i = 0; i < obj->base.size / PAGE_SIZE; i++) { | |
6a2c4232 CW |
249 | struct page *page; |
250 | char *dst; | |
251 | ||
252 | page = shmem_read_mapping_page(mapping, i); | |
253 | if (IS_ERR(page)) | |
254 | continue; | |
255 | ||
256 | dst = kmap_atomic(page); | |
257 | drm_clflush_virt_range(vaddr, PAGE_SIZE); | |
258 | memcpy(dst, vaddr, PAGE_SIZE); | |
259 | kunmap_atomic(dst); | |
260 | ||
261 | set_page_dirty(page); | |
262 | if (obj->madv == I915_MADV_WILLNEED) | |
00731155 | 263 | mark_page_accessed(page); |
09cbfeaf | 264 | put_page(page); |
00731155 CW |
265 | vaddr += PAGE_SIZE; |
266 | } | |
6a2c4232 | 267 | obj->dirty = 0; |
00731155 CW |
268 | } |
269 | ||
6a2c4232 CW |
270 | sg_free_table(obj->pages); |
271 | kfree(obj->pages); | |
6a2c4232 CW |
272 | } |
273 | ||
274 | static void | |
275 | i915_gem_object_release_phys(struct drm_i915_gem_object *obj) | |
276 | { | |
277 | drm_pci_free(obj->base.dev, obj->phys_handle); | |
278 | } | |
279 | ||
280 | static const struct drm_i915_gem_object_ops i915_gem_phys_ops = { | |
281 | .get_pages = i915_gem_object_get_pages_phys, | |
282 | .put_pages = i915_gem_object_put_pages_phys, | |
283 | .release = i915_gem_object_release_phys, | |
284 | }; | |
285 | ||
286 | static int | |
287 | drop_pages(struct drm_i915_gem_object *obj) | |
288 | { | |
289 | struct i915_vma *vma, *next; | |
290 | int ret; | |
291 | ||
25dc556a | 292 | i915_gem_object_get(obj); |
1c7f4bca | 293 | list_for_each_entry_safe(vma, next, &obj->vma_list, obj_link) |
6a2c4232 CW |
294 | if (i915_vma_unbind(vma)) |
295 | break; | |
296 | ||
297 | ret = i915_gem_object_put_pages(obj); | |
f8c417cd | 298 | i915_gem_object_put(obj); |
6a2c4232 CW |
299 | |
300 | return ret; | |
00731155 CW |
301 | } |
302 | ||
303 | int | |
304 | i915_gem_object_attach_phys(struct drm_i915_gem_object *obj, | |
305 | int align) | |
306 | { | |
307 | drm_dma_handle_t *phys; | |
6a2c4232 | 308 | int ret; |
00731155 CW |
309 | |
310 | if (obj->phys_handle) { | |
311 | if ((unsigned long)obj->phys_handle->vaddr & (align -1)) | |
312 | return -EBUSY; | |
313 | ||
314 | return 0; | |
315 | } | |
316 | ||
317 | if (obj->madv != I915_MADV_WILLNEED) | |
318 | return -EFAULT; | |
319 | ||
320 | if (obj->base.filp == NULL) | |
321 | return -EINVAL; | |
322 | ||
6a2c4232 CW |
323 | ret = drop_pages(obj); |
324 | if (ret) | |
325 | return ret; | |
326 | ||
00731155 CW |
327 | /* create a new object */ |
328 | phys = drm_pci_alloc(obj->base.dev, obj->base.size, align); | |
329 | if (!phys) | |
330 | return -ENOMEM; | |
331 | ||
00731155 | 332 | obj->phys_handle = phys; |
6a2c4232 CW |
333 | obj->ops = &i915_gem_phys_ops; |
334 | ||
335 | return i915_gem_object_get_pages(obj); | |
00731155 CW |
336 | } |
337 | ||
338 | static int | |
339 | i915_gem_phys_pwrite(struct drm_i915_gem_object *obj, | |
340 | struct drm_i915_gem_pwrite *args, | |
341 | struct drm_file *file_priv) | |
342 | { | |
343 | struct drm_device *dev = obj->base.dev; | |
344 | void *vaddr = obj->phys_handle->vaddr + args->offset; | |
3ed605bc | 345 | char __user *user_data = u64_to_user_ptr(args->data_ptr); |
063e4e6b | 346 | int ret = 0; |
6a2c4232 CW |
347 | |
348 | /* We manually control the domain here and pretend that it | |
349 | * remains coherent i.e. in the GTT domain, like shmem_pwrite. | |
350 | */ | |
351 | ret = i915_gem_object_wait_rendering(obj, false); | |
352 | if (ret) | |
353 | return ret; | |
00731155 | 354 | |
77a0d1ca | 355 | intel_fb_obj_invalidate(obj, ORIGIN_CPU); |
00731155 CW |
356 | if (__copy_from_user_inatomic_nocache(vaddr, user_data, args->size)) { |
357 | unsigned long unwritten; | |
358 | ||
359 | /* The physical object once assigned is fixed for the lifetime | |
360 | * of the obj, so we can safely drop the lock and continue | |
361 | * to access vaddr. | |
362 | */ | |
363 | mutex_unlock(&dev->struct_mutex); | |
364 | unwritten = copy_from_user(vaddr, user_data, args->size); | |
365 | mutex_lock(&dev->struct_mutex); | |
063e4e6b PZ |
366 | if (unwritten) { |
367 | ret = -EFAULT; | |
368 | goto out; | |
369 | } | |
00731155 CW |
370 | } |
371 | ||
6a2c4232 | 372 | drm_clflush_virt_range(vaddr, args->size); |
c033666a | 373 | i915_gem_chipset_flush(to_i915(dev)); |
063e4e6b PZ |
374 | |
375 | out: | |
de152b62 | 376 | intel_fb_obj_flush(obj, false, ORIGIN_CPU); |
063e4e6b | 377 | return ret; |
00731155 CW |
378 | } |
379 | ||
42dcedd4 CW |
380 | void *i915_gem_object_alloc(struct drm_device *dev) |
381 | { | |
fac5e23e | 382 | struct drm_i915_private *dev_priv = to_i915(dev); |
efab6d8d | 383 | return kmem_cache_zalloc(dev_priv->objects, GFP_KERNEL); |
42dcedd4 CW |
384 | } |
385 | ||
386 | void i915_gem_object_free(struct drm_i915_gem_object *obj) | |
387 | { | |
fac5e23e | 388 | struct drm_i915_private *dev_priv = to_i915(obj->base.dev); |
efab6d8d | 389 | kmem_cache_free(dev_priv->objects, obj); |
42dcedd4 CW |
390 | } |
391 | ||
ff72145b DA |
392 | static int |
393 | i915_gem_create(struct drm_file *file, | |
394 | struct drm_device *dev, | |
395 | uint64_t size, | |
396 | uint32_t *handle_p) | |
673a394b | 397 | { |
05394f39 | 398 | struct drm_i915_gem_object *obj; |
a1a2d1d3 PP |
399 | int ret; |
400 | u32 handle; | |
673a394b | 401 | |
ff72145b | 402 | size = roundup(size, PAGE_SIZE); |
8ffc0246 CW |
403 | if (size == 0) |
404 | return -EINVAL; | |
673a394b EA |
405 | |
406 | /* Allocate the new object */ | |
d37cd8a8 | 407 | obj = i915_gem_object_create(dev, size); |
fe3db79b CW |
408 | if (IS_ERR(obj)) |
409 | return PTR_ERR(obj); | |
673a394b | 410 | |
05394f39 | 411 | ret = drm_gem_handle_create(file, &obj->base, &handle); |
202f2fef | 412 | /* drop reference from allocate - handle holds it now */ |
34911fd3 | 413 | i915_gem_object_put_unlocked(obj); |
d861e338 DV |
414 | if (ret) |
415 | return ret; | |
202f2fef | 416 | |
ff72145b | 417 | *handle_p = handle; |
673a394b EA |
418 | return 0; |
419 | } | |
420 | ||
ff72145b DA |
421 | int |
422 | i915_gem_dumb_create(struct drm_file *file, | |
423 | struct drm_device *dev, | |
424 | struct drm_mode_create_dumb *args) | |
425 | { | |
426 | /* have to work out size/pitch and return them */ | |
de45eaf7 | 427 | args->pitch = ALIGN(args->width * DIV_ROUND_UP(args->bpp, 8), 64); |
ff72145b DA |
428 | args->size = args->pitch * args->height; |
429 | return i915_gem_create(file, dev, | |
da6b51d0 | 430 | args->size, &args->handle); |
ff72145b DA |
431 | } |
432 | ||
ff72145b DA |
433 | /** |
434 | * Creates a new mm object and returns a handle to it. | |
14bb2c11 TU |
435 | * @dev: drm device pointer |
436 | * @data: ioctl data blob | |
437 | * @file: drm file pointer | |
ff72145b DA |
438 | */ |
439 | int | |
440 | i915_gem_create_ioctl(struct drm_device *dev, void *data, | |
441 | struct drm_file *file) | |
442 | { | |
443 | struct drm_i915_gem_create *args = data; | |
63ed2cb2 | 444 | |
ff72145b | 445 | return i915_gem_create(file, dev, |
da6b51d0 | 446 | args->size, &args->handle); |
ff72145b DA |
447 | } |
448 | ||
8461d226 DV |
449 | static inline int |
450 | __copy_to_user_swizzled(char __user *cpu_vaddr, | |
451 | const char *gpu_vaddr, int gpu_offset, | |
452 | int length) | |
453 | { | |
454 | int ret, cpu_offset = 0; | |
455 | ||
456 | while (length > 0) { | |
457 | int cacheline_end = ALIGN(gpu_offset + 1, 64); | |
458 | int this_length = min(cacheline_end - gpu_offset, length); | |
459 | int swizzled_gpu_offset = gpu_offset ^ 64; | |
460 | ||
461 | ret = __copy_to_user(cpu_vaddr + cpu_offset, | |
462 | gpu_vaddr + swizzled_gpu_offset, | |
463 | this_length); | |
464 | if (ret) | |
465 | return ret + length; | |
466 | ||
467 | cpu_offset += this_length; | |
468 | gpu_offset += this_length; | |
469 | length -= this_length; | |
470 | } | |
471 | ||
472 | return 0; | |
473 | } | |
474 | ||
8c59967c | 475 | static inline int |
4f0c7cfb BW |
476 | __copy_from_user_swizzled(char *gpu_vaddr, int gpu_offset, |
477 | const char __user *cpu_vaddr, | |
8c59967c DV |
478 | int length) |
479 | { | |
480 | int ret, cpu_offset = 0; | |
481 | ||
482 | while (length > 0) { | |
483 | int cacheline_end = ALIGN(gpu_offset + 1, 64); | |
484 | int this_length = min(cacheline_end - gpu_offset, length); | |
485 | int swizzled_gpu_offset = gpu_offset ^ 64; | |
486 | ||
487 | ret = __copy_from_user(gpu_vaddr + swizzled_gpu_offset, | |
488 | cpu_vaddr + cpu_offset, | |
489 | this_length); | |
490 | if (ret) | |
491 | return ret + length; | |
492 | ||
493 | cpu_offset += this_length; | |
494 | gpu_offset += this_length; | |
495 | length -= this_length; | |
496 | } | |
497 | ||
498 | return 0; | |
499 | } | |
500 | ||
4c914c0c BV |
501 | /* |
502 | * Pins the specified object's pages and synchronizes the object with | |
503 | * GPU accesses. Sets needs_clflush to non-zero if the caller should | |
504 | * flush the object from the CPU cache. | |
505 | */ | |
506 | int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj, | |
507 | int *needs_clflush) | |
508 | { | |
509 | int ret; | |
510 | ||
511 | *needs_clflush = 0; | |
512 | ||
b9bcd14a | 513 | if (WARN_ON(!i915_gem_object_has_struct_page(obj))) |
4c914c0c BV |
514 | return -EINVAL; |
515 | ||
c13d87ea CW |
516 | ret = i915_gem_object_wait_rendering(obj, true); |
517 | if (ret) | |
518 | return ret; | |
519 | ||
4c914c0c BV |
520 | if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU)) { |
521 | /* If we're not in the cpu read domain, set ourself into the gtt | |
522 | * read domain and manually flush cachelines (if required). This | |
523 | * optimizes for the case when the gpu will dirty the data | |
524 | * anyway again before the next pread happens. */ | |
525 | *needs_clflush = !cpu_cache_is_coherent(obj->base.dev, | |
526 | obj->cache_level); | |
4c914c0c BV |
527 | } |
528 | ||
529 | ret = i915_gem_object_get_pages(obj); | |
530 | if (ret) | |
531 | return ret; | |
532 | ||
533 | i915_gem_object_pin_pages(obj); | |
534 | ||
535 | return ret; | |
536 | } | |
537 | ||
d174bd64 DV |
538 | /* Per-page copy function for the shmem pread fastpath. |
539 | * Flushes invalid cachelines before reading the target if | |
540 | * needs_clflush is set. */ | |
eb01459f | 541 | static int |
d174bd64 DV |
542 | shmem_pread_fast(struct page *page, int shmem_page_offset, int page_length, |
543 | char __user *user_data, | |
544 | bool page_do_bit17_swizzling, bool needs_clflush) | |
545 | { | |
546 | char *vaddr; | |
547 | int ret; | |
548 | ||
e7e58eb5 | 549 | if (unlikely(page_do_bit17_swizzling)) |
d174bd64 DV |
550 | return -EINVAL; |
551 | ||
552 | vaddr = kmap_atomic(page); | |
553 | if (needs_clflush) | |
554 | drm_clflush_virt_range(vaddr + shmem_page_offset, | |
555 | page_length); | |
556 | ret = __copy_to_user_inatomic(user_data, | |
557 | vaddr + shmem_page_offset, | |
558 | page_length); | |
559 | kunmap_atomic(vaddr); | |
560 | ||
f60d7f0c | 561 | return ret ? -EFAULT : 0; |
d174bd64 DV |
562 | } |
563 | ||
23c18c71 DV |
564 | static void |
565 | shmem_clflush_swizzled_range(char *addr, unsigned long length, | |
566 | bool swizzled) | |
567 | { | |
e7e58eb5 | 568 | if (unlikely(swizzled)) { |
23c18c71 DV |
569 | unsigned long start = (unsigned long) addr; |
570 | unsigned long end = (unsigned long) addr + length; | |
571 | ||
572 | /* For swizzling simply ensure that we always flush both | |
573 | * channels. Lame, but simple and it works. Swizzled | |
574 | * pwrite/pread is far from a hotpath - current userspace | |
575 | * doesn't use it at all. */ | |
576 | start = round_down(start, 128); | |
577 | end = round_up(end, 128); | |
578 | ||
579 | drm_clflush_virt_range((void *)start, end - start); | |
580 | } else { | |
581 | drm_clflush_virt_range(addr, length); | |
582 | } | |
583 | ||
584 | } | |
585 | ||
d174bd64 DV |
586 | /* Only difference to the fast-path function is that this can handle bit17 |
587 | * and uses non-atomic copy and kmap functions. */ | |
588 | static int | |
589 | shmem_pread_slow(struct page *page, int shmem_page_offset, int page_length, | |
590 | char __user *user_data, | |
591 | bool page_do_bit17_swizzling, bool needs_clflush) | |
592 | { | |
593 | char *vaddr; | |
594 | int ret; | |
595 | ||
596 | vaddr = kmap(page); | |
597 | if (needs_clflush) | |
23c18c71 DV |
598 | shmem_clflush_swizzled_range(vaddr + shmem_page_offset, |
599 | page_length, | |
600 | page_do_bit17_swizzling); | |
d174bd64 DV |
601 | |
602 | if (page_do_bit17_swizzling) | |
603 | ret = __copy_to_user_swizzled(user_data, | |
604 | vaddr, shmem_page_offset, | |
605 | page_length); | |
606 | else | |
607 | ret = __copy_to_user(user_data, | |
608 | vaddr + shmem_page_offset, | |
609 | page_length); | |
610 | kunmap(page); | |
611 | ||
f60d7f0c | 612 | return ret ? - EFAULT : 0; |
d174bd64 DV |
613 | } |
614 | ||
b50a5371 AS |
615 | static inline unsigned long |
616 | slow_user_access(struct io_mapping *mapping, | |
617 | uint64_t page_base, int page_offset, | |
618 | char __user *user_data, | |
619 | unsigned long length, bool pwrite) | |
620 | { | |
621 | void __iomem *ioaddr; | |
622 | void *vaddr; | |
623 | uint64_t unwritten; | |
624 | ||
625 | ioaddr = io_mapping_map_wc(mapping, page_base, PAGE_SIZE); | |
626 | /* We can use the cpu mem copy function because this is X86. */ | |
627 | vaddr = (void __force *)ioaddr + page_offset; | |
628 | if (pwrite) | |
629 | unwritten = __copy_from_user(vaddr, user_data, length); | |
630 | else | |
631 | unwritten = __copy_to_user(user_data, vaddr, length); | |
632 | ||
633 | io_mapping_unmap(ioaddr); | |
634 | return unwritten; | |
635 | } | |
636 | ||
637 | static int | |
638 | i915_gem_gtt_pread(struct drm_device *dev, | |
639 | struct drm_i915_gem_object *obj, uint64_t size, | |
640 | uint64_t data_offset, uint64_t data_ptr) | |
641 | { | |
fac5e23e | 642 | struct drm_i915_private *dev_priv = to_i915(dev); |
b50a5371 AS |
643 | struct i915_ggtt *ggtt = &dev_priv->ggtt; |
644 | struct drm_mm_node node; | |
645 | char __user *user_data; | |
646 | uint64_t remain; | |
647 | uint64_t offset; | |
648 | int ret; | |
649 | ||
650 | ret = i915_gem_obj_ggtt_pin(obj, 0, PIN_MAPPABLE); | |
651 | if (ret) { | |
652 | ret = insert_mappable_node(dev_priv, &node, PAGE_SIZE); | |
653 | if (ret) | |
654 | goto out; | |
655 | ||
656 | ret = i915_gem_object_get_pages(obj); | |
657 | if (ret) { | |
658 | remove_mappable_node(&node); | |
659 | goto out; | |
660 | } | |
661 | ||
662 | i915_gem_object_pin_pages(obj); | |
663 | } else { | |
664 | node.start = i915_gem_obj_ggtt_offset(obj); | |
665 | node.allocated = false; | |
666 | ret = i915_gem_object_put_fence(obj); | |
667 | if (ret) | |
668 | goto out_unpin; | |
669 | } | |
670 | ||
671 | ret = i915_gem_object_set_to_gtt_domain(obj, false); | |
672 | if (ret) | |
673 | goto out_unpin; | |
674 | ||
675 | user_data = u64_to_user_ptr(data_ptr); | |
676 | remain = size; | |
677 | offset = data_offset; | |
678 | ||
679 | mutex_unlock(&dev->struct_mutex); | |
680 | if (likely(!i915.prefault_disable)) { | |
681 | ret = fault_in_multipages_writeable(user_data, remain); | |
682 | if (ret) { | |
683 | mutex_lock(&dev->struct_mutex); | |
684 | goto out_unpin; | |
685 | } | |
686 | } | |
687 | ||
688 | while (remain > 0) { | |
689 | /* Operation in this page | |
690 | * | |
691 | * page_base = page offset within aperture | |
692 | * page_offset = offset within page | |
693 | * page_length = bytes to copy for this page | |
694 | */ | |
695 | u32 page_base = node.start; | |
696 | unsigned page_offset = offset_in_page(offset); | |
697 | unsigned page_length = PAGE_SIZE - page_offset; | |
698 | page_length = remain < page_length ? remain : page_length; | |
699 | if (node.allocated) { | |
700 | wmb(); | |
701 | ggtt->base.insert_page(&ggtt->base, | |
702 | i915_gem_object_get_dma_address(obj, offset >> PAGE_SHIFT), | |
703 | node.start, | |
704 | I915_CACHE_NONE, 0); | |
705 | wmb(); | |
706 | } else { | |
707 | page_base += offset & PAGE_MASK; | |
708 | } | |
709 | /* This is a slow read/write as it tries to read from | |
710 | * and write to user memory which may result into page | |
711 | * faults, and so we cannot perform this under struct_mutex. | |
712 | */ | |
713 | if (slow_user_access(ggtt->mappable, page_base, | |
714 | page_offset, user_data, | |
715 | page_length, false)) { | |
716 | ret = -EFAULT; | |
717 | break; | |
718 | } | |
719 | ||
720 | remain -= page_length; | |
721 | user_data += page_length; | |
722 | offset += page_length; | |
723 | } | |
724 | ||
725 | mutex_lock(&dev->struct_mutex); | |
726 | if (ret == 0 && (obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0) { | |
727 | /* The user has modified the object whilst we tried | |
728 | * reading from it, and we now have no idea what domain | |
729 | * the pages should be in. As we have just been touching | |
730 | * them directly, flush everything back to the GTT | |
731 | * domain. | |
732 | */ | |
733 | ret = i915_gem_object_set_to_gtt_domain(obj, false); | |
734 | } | |
735 | ||
736 | out_unpin: | |
737 | if (node.allocated) { | |
738 | wmb(); | |
739 | ggtt->base.clear_range(&ggtt->base, | |
740 | node.start, node.size, | |
741 | true); | |
742 | i915_gem_object_unpin_pages(obj); | |
743 | remove_mappable_node(&node); | |
744 | } else { | |
745 | i915_gem_object_ggtt_unpin(obj); | |
746 | } | |
747 | out: | |
748 | return ret; | |
749 | } | |
750 | ||
eb01459f | 751 | static int |
dbf7bff0 DV |
752 | i915_gem_shmem_pread(struct drm_device *dev, |
753 | struct drm_i915_gem_object *obj, | |
754 | struct drm_i915_gem_pread *args, | |
755 | struct drm_file *file) | |
eb01459f | 756 | { |
8461d226 | 757 | char __user *user_data; |
eb01459f | 758 | ssize_t remain; |
8461d226 | 759 | loff_t offset; |
eb2c0c81 | 760 | int shmem_page_offset, page_length, ret = 0; |
8461d226 | 761 | int obj_do_bit17_swizzling, page_do_bit17_swizzling; |
96d79b52 | 762 | int prefaulted = 0; |
8489731c | 763 | int needs_clflush = 0; |
67d5a50c | 764 | struct sg_page_iter sg_iter; |
eb01459f | 765 | |
6eae0059 | 766 | if (!i915_gem_object_has_struct_page(obj)) |
b50a5371 AS |
767 | return -ENODEV; |
768 | ||
3ed605bc | 769 | user_data = u64_to_user_ptr(args->data_ptr); |
eb01459f EA |
770 | remain = args->size; |
771 | ||
8461d226 | 772 | obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj); |
eb01459f | 773 | |
4c914c0c | 774 | ret = i915_gem_obj_prepare_shmem_read(obj, &needs_clflush); |
f60d7f0c CW |
775 | if (ret) |
776 | return ret; | |
777 | ||
8461d226 | 778 | offset = args->offset; |
eb01459f | 779 | |
67d5a50c ID |
780 | for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, |
781 | offset >> PAGE_SHIFT) { | |
2db76d7c | 782 | struct page *page = sg_page_iter_page(&sg_iter); |
9da3da66 CW |
783 | |
784 | if (remain <= 0) | |
785 | break; | |
786 | ||
eb01459f EA |
787 | /* Operation in this page |
788 | * | |
eb01459f | 789 | * shmem_page_offset = offset within page in shmem file |
eb01459f EA |
790 | * page_length = bytes to copy for this page |
791 | */ | |
c8cbbb8b | 792 | shmem_page_offset = offset_in_page(offset); |
eb01459f EA |
793 | page_length = remain; |
794 | if ((shmem_page_offset + page_length) > PAGE_SIZE) | |
795 | page_length = PAGE_SIZE - shmem_page_offset; | |
eb01459f | 796 | |
8461d226 DV |
797 | page_do_bit17_swizzling = obj_do_bit17_swizzling && |
798 | (page_to_phys(page) & (1 << 17)) != 0; | |
799 | ||
d174bd64 DV |
800 | ret = shmem_pread_fast(page, shmem_page_offset, page_length, |
801 | user_data, page_do_bit17_swizzling, | |
802 | needs_clflush); | |
803 | if (ret == 0) | |
804 | goto next_page; | |
dbf7bff0 | 805 | |
dbf7bff0 DV |
806 | mutex_unlock(&dev->struct_mutex); |
807 | ||
d330a953 | 808 | if (likely(!i915.prefault_disable) && !prefaulted) { |
f56f821f | 809 | ret = fault_in_multipages_writeable(user_data, remain); |
96d79b52 DV |
810 | /* Userspace is tricking us, but we've already clobbered |
811 | * its pages with the prefault and promised to write the | |
812 | * data up to the first fault. Hence ignore any errors | |
813 | * and just continue. */ | |
814 | (void)ret; | |
815 | prefaulted = 1; | |
816 | } | |
eb01459f | 817 | |
d174bd64 DV |
818 | ret = shmem_pread_slow(page, shmem_page_offset, page_length, |
819 | user_data, page_do_bit17_swizzling, | |
820 | needs_clflush); | |
eb01459f | 821 | |
dbf7bff0 | 822 | mutex_lock(&dev->struct_mutex); |
f60d7f0c | 823 | |
f60d7f0c | 824 | if (ret) |
8461d226 | 825 | goto out; |
8461d226 | 826 | |
17793c9a | 827 | next_page: |
eb01459f | 828 | remain -= page_length; |
8461d226 | 829 | user_data += page_length; |
eb01459f EA |
830 | offset += page_length; |
831 | } | |
832 | ||
4f27b75d | 833 | out: |
f60d7f0c CW |
834 | i915_gem_object_unpin_pages(obj); |
835 | ||
eb01459f EA |
836 | return ret; |
837 | } | |
838 | ||
673a394b EA |
839 | /** |
840 | * Reads data from the object referenced by handle. | |
14bb2c11 TU |
841 | * @dev: drm device pointer |
842 | * @data: ioctl data blob | |
843 | * @file: drm file pointer | |
673a394b EA |
844 | * |
845 | * On error, the contents of *data are undefined. | |
846 | */ | |
847 | int | |
848 | i915_gem_pread_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 849 | struct drm_file *file) |
673a394b EA |
850 | { |
851 | struct drm_i915_gem_pread *args = data; | |
05394f39 | 852 | struct drm_i915_gem_object *obj; |
35b62a89 | 853 | int ret = 0; |
673a394b | 854 | |
51311d0a CW |
855 | if (args->size == 0) |
856 | return 0; | |
857 | ||
858 | if (!access_ok(VERIFY_WRITE, | |
3ed605bc | 859 | u64_to_user_ptr(args->data_ptr), |
51311d0a CW |
860 | args->size)) |
861 | return -EFAULT; | |
862 | ||
4f27b75d | 863 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 864 | if (ret) |
4f27b75d | 865 | return ret; |
673a394b | 866 | |
03ac0642 CW |
867 | obj = i915_gem_object_lookup(file, args->handle); |
868 | if (!obj) { | |
1d7cfea1 CW |
869 | ret = -ENOENT; |
870 | goto unlock; | |
4f27b75d | 871 | } |
673a394b | 872 | |
7dcd2499 | 873 | /* Bounds check source. */ |
05394f39 CW |
874 | if (args->offset > obj->base.size || |
875 | args->size > obj->base.size - args->offset) { | |
ce9d419d | 876 | ret = -EINVAL; |
35b62a89 | 877 | goto out; |
ce9d419d CW |
878 | } |
879 | ||
db53a302 CW |
880 | trace_i915_gem_object_pread(obj, args->offset, args->size); |
881 | ||
dbf7bff0 | 882 | ret = i915_gem_shmem_pread(dev, obj, args, file); |
673a394b | 883 | |
b50a5371 AS |
884 | /* pread for non shmem backed objects */ |
885 | if (ret == -EFAULT || ret == -ENODEV) | |
886 | ret = i915_gem_gtt_pread(dev, obj, args->size, | |
887 | args->offset, args->data_ptr); | |
888 | ||
35b62a89 | 889 | out: |
f8c417cd | 890 | i915_gem_object_put(obj); |
1d7cfea1 | 891 | unlock: |
4f27b75d | 892 | mutex_unlock(&dev->struct_mutex); |
eb01459f | 893 | return ret; |
673a394b EA |
894 | } |
895 | ||
0839ccb8 KP |
896 | /* This is the fast write path which cannot handle |
897 | * page faults in the source data | |
9b7530cc | 898 | */ |
0839ccb8 KP |
899 | |
900 | static inline int | |
901 | fast_user_write(struct io_mapping *mapping, | |
902 | loff_t page_base, int page_offset, | |
903 | char __user *user_data, | |
904 | int length) | |
9b7530cc | 905 | { |
4f0c7cfb BW |
906 | void __iomem *vaddr_atomic; |
907 | void *vaddr; | |
0839ccb8 | 908 | unsigned long unwritten; |
9b7530cc | 909 | |
3e4d3af5 | 910 | vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base); |
4f0c7cfb BW |
911 | /* We can use the cpu mem copy function because this is X86. */ |
912 | vaddr = (void __force*)vaddr_atomic + page_offset; | |
913 | unwritten = __copy_from_user_inatomic_nocache(vaddr, | |
0839ccb8 | 914 | user_data, length); |
3e4d3af5 | 915 | io_mapping_unmap_atomic(vaddr_atomic); |
fbd5a26d | 916 | return unwritten; |
0839ccb8 KP |
917 | } |
918 | ||
3de09aa3 EA |
919 | /** |
920 | * This is the fast pwrite path, where we copy the data directly from the | |
921 | * user into the GTT, uncached. | |
62f90b38 | 922 | * @i915: i915 device private data |
14bb2c11 TU |
923 | * @obj: i915 gem object |
924 | * @args: pwrite arguments structure | |
925 | * @file: drm file pointer | |
3de09aa3 | 926 | */ |
673a394b | 927 | static int |
4f1959ee | 928 | i915_gem_gtt_pwrite_fast(struct drm_i915_private *i915, |
05394f39 | 929 | struct drm_i915_gem_object *obj, |
3de09aa3 | 930 | struct drm_i915_gem_pwrite *args, |
05394f39 | 931 | struct drm_file *file) |
673a394b | 932 | { |
4f1959ee | 933 | struct i915_ggtt *ggtt = &i915->ggtt; |
b50a5371 | 934 | struct drm_device *dev = obj->base.dev; |
4f1959ee AS |
935 | struct drm_mm_node node; |
936 | uint64_t remain, offset; | |
673a394b | 937 | char __user *user_data; |
4f1959ee | 938 | int ret; |
b50a5371 AS |
939 | bool hit_slow_path = false; |
940 | ||
941 | if (obj->tiling_mode != I915_TILING_NONE) | |
942 | return -EFAULT; | |
935aaa69 | 943 | |
1ec9e26d | 944 | ret = i915_gem_obj_ggtt_pin(obj, 0, PIN_MAPPABLE | PIN_NONBLOCK); |
4f1959ee AS |
945 | if (ret) { |
946 | ret = insert_mappable_node(i915, &node, PAGE_SIZE); | |
947 | if (ret) | |
948 | goto out; | |
949 | ||
950 | ret = i915_gem_object_get_pages(obj); | |
951 | if (ret) { | |
952 | remove_mappable_node(&node); | |
953 | goto out; | |
954 | } | |
955 | ||
956 | i915_gem_object_pin_pages(obj); | |
957 | } else { | |
958 | node.start = i915_gem_obj_ggtt_offset(obj); | |
959 | node.allocated = false; | |
b50a5371 AS |
960 | ret = i915_gem_object_put_fence(obj); |
961 | if (ret) | |
962 | goto out_unpin; | |
4f1959ee | 963 | } |
935aaa69 DV |
964 | |
965 | ret = i915_gem_object_set_to_gtt_domain(obj, true); | |
966 | if (ret) | |
967 | goto out_unpin; | |
968 | ||
77a0d1ca | 969 | intel_fb_obj_invalidate(obj, ORIGIN_GTT); |
4f1959ee | 970 | obj->dirty = true; |
063e4e6b | 971 | |
4f1959ee AS |
972 | user_data = u64_to_user_ptr(args->data_ptr); |
973 | offset = args->offset; | |
974 | remain = args->size; | |
975 | while (remain) { | |
673a394b EA |
976 | /* Operation in this page |
977 | * | |
0839ccb8 KP |
978 | * page_base = page offset within aperture |
979 | * page_offset = offset within page | |
980 | * page_length = bytes to copy for this page | |
673a394b | 981 | */ |
4f1959ee AS |
982 | u32 page_base = node.start; |
983 | unsigned page_offset = offset_in_page(offset); | |
984 | unsigned page_length = PAGE_SIZE - page_offset; | |
985 | page_length = remain < page_length ? remain : page_length; | |
986 | if (node.allocated) { | |
987 | wmb(); /* flush the write before we modify the GGTT */ | |
988 | ggtt->base.insert_page(&ggtt->base, | |
989 | i915_gem_object_get_dma_address(obj, offset >> PAGE_SHIFT), | |
990 | node.start, I915_CACHE_NONE, 0); | |
991 | wmb(); /* flush modifications to the GGTT (insert_page) */ | |
992 | } else { | |
993 | page_base += offset & PAGE_MASK; | |
994 | } | |
0839ccb8 | 995 | /* If we get a fault while copying data, then (presumably) our |
3de09aa3 EA |
996 | * source page isn't available. Return the error and we'll |
997 | * retry in the slow path. | |
b50a5371 AS |
998 | * If the object is non-shmem backed, we retry again with the |
999 | * path that handles page fault. | |
0839ccb8 | 1000 | */ |
72e96d64 | 1001 | if (fast_user_write(ggtt->mappable, page_base, |
935aaa69 | 1002 | page_offset, user_data, page_length)) { |
b50a5371 AS |
1003 | hit_slow_path = true; |
1004 | mutex_unlock(&dev->struct_mutex); | |
1005 | if (slow_user_access(ggtt->mappable, | |
1006 | page_base, | |
1007 | page_offset, user_data, | |
1008 | page_length, true)) { | |
1009 | ret = -EFAULT; | |
1010 | mutex_lock(&dev->struct_mutex); | |
1011 | goto out_flush; | |
1012 | } | |
1013 | ||
1014 | mutex_lock(&dev->struct_mutex); | |
935aaa69 | 1015 | } |
673a394b | 1016 | |
0839ccb8 KP |
1017 | remain -= page_length; |
1018 | user_data += page_length; | |
1019 | offset += page_length; | |
673a394b | 1020 | } |
673a394b | 1021 | |
063e4e6b | 1022 | out_flush: |
b50a5371 AS |
1023 | if (hit_slow_path) { |
1024 | if (ret == 0 && | |
1025 | (obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0) { | |
1026 | /* The user has modified the object whilst we tried | |
1027 | * reading from it, and we now have no idea what domain | |
1028 | * the pages should be in. As we have just been touching | |
1029 | * them directly, flush everything back to the GTT | |
1030 | * domain. | |
1031 | */ | |
1032 | ret = i915_gem_object_set_to_gtt_domain(obj, false); | |
1033 | } | |
1034 | } | |
1035 | ||
de152b62 | 1036 | intel_fb_obj_flush(obj, false, ORIGIN_GTT); |
935aaa69 | 1037 | out_unpin: |
4f1959ee AS |
1038 | if (node.allocated) { |
1039 | wmb(); | |
1040 | ggtt->base.clear_range(&ggtt->base, | |
1041 | node.start, node.size, | |
1042 | true); | |
1043 | i915_gem_object_unpin_pages(obj); | |
1044 | remove_mappable_node(&node); | |
1045 | } else { | |
1046 | i915_gem_object_ggtt_unpin(obj); | |
1047 | } | |
935aaa69 | 1048 | out: |
3de09aa3 | 1049 | return ret; |
673a394b EA |
1050 | } |
1051 | ||
d174bd64 DV |
1052 | /* Per-page copy function for the shmem pwrite fastpath. |
1053 | * Flushes invalid cachelines before writing to the target if | |
1054 | * needs_clflush_before is set and flushes out any written cachelines after | |
1055 | * writing if needs_clflush is set. */ | |
3043c60c | 1056 | static int |
d174bd64 DV |
1057 | shmem_pwrite_fast(struct page *page, int shmem_page_offset, int page_length, |
1058 | char __user *user_data, | |
1059 | bool page_do_bit17_swizzling, | |
1060 | bool needs_clflush_before, | |
1061 | bool needs_clflush_after) | |
673a394b | 1062 | { |
d174bd64 | 1063 | char *vaddr; |
673a394b | 1064 | int ret; |
3de09aa3 | 1065 | |
e7e58eb5 | 1066 | if (unlikely(page_do_bit17_swizzling)) |
d174bd64 | 1067 | return -EINVAL; |
3de09aa3 | 1068 | |
d174bd64 DV |
1069 | vaddr = kmap_atomic(page); |
1070 | if (needs_clflush_before) | |
1071 | drm_clflush_virt_range(vaddr + shmem_page_offset, | |
1072 | page_length); | |
c2831a94 CW |
1073 | ret = __copy_from_user_inatomic(vaddr + shmem_page_offset, |
1074 | user_data, page_length); | |
d174bd64 DV |
1075 | if (needs_clflush_after) |
1076 | drm_clflush_virt_range(vaddr + shmem_page_offset, | |
1077 | page_length); | |
1078 | kunmap_atomic(vaddr); | |
3de09aa3 | 1079 | |
755d2218 | 1080 | return ret ? -EFAULT : 0; |
3de09aa3 EA |
1081 | } |
1082 | ||
d174bd64 DV |
1083 | /* Only difference to the fast-path function is that this can handle bit17 |
1084 | * and uses non-atomic copy and kmap functions. */ | |
3043c60c | 1085 | static int |
d174bd64 DV |
1086 | shmem_pwrite_slow(struct page *page, int shmem_page_offset, int page_length, |
1087 | char __user *user_data, | |
1088 | bool page_do_bit17_swizzling, | |
1089 | bool needs_clflush_before, | |
1090 | bool needs_clflush_after) | |
673a394b | 1091 | { |
d174bd64 DV |
1092 | char *vaddr; |
1093 | int ret; | |
e5281ccd | 1094 | |
d174bd64 | 1095 | vaddr = kmap(page); |
e7e58eb5 | 1096 | if (unlikely(needs_clflush_before || page_do_bit17_swizzling)) |
23c18c71 DV |
1097 | shmem_clflush_swizzled_range(vaddr + shmem_page_offset, |
1098 | page_length, | |
1099 | page_do_bit17_swizzling); | |
d174bd64 DV |
1100 | if (page_do_bit17_swizzling) |
1101 | ret = __copy_from_user_swizzled(vaddr, shmem_page_offset, | |
e5281ccd CW |
1102 | user_data, |
1103 | page_length); | |
d174bd64 DV |
1104 | else |
1105 | ret = __copy_from_user(vaddr + shmem_page_offset, | |
1106 | user_data, | |
1107 | page_length); | |
1108 | if (needs_clflush_after) | |
23c18c71 DV |
1109 | shmem_clflush_swizzled_range(vaddr + shmem_page_offset, |
1110 | page_length, | |
1111 | page_do_bit17_swizzling); | |
d174bd64 | 1112 | kunmap(page); |
40123c1f | 1113 | |
755d2218 | 1114 | return ret ? -EFAULT : 0; |
40123c1f EA |
1115 | } |
1116 | ||
40123c1f | 1117 | static int |
e244a443 DV |
1118 | i915_gem_shmem_pwrite(struct drm_device *dev, |
1119 | struct drm_i915_gem_object *obj, | |
1120 | struct drm_i915_gem_pwrite *args, | |
1121 | struct drm_file *file) | |
40123c1f | 1122 | { |
40123c1f | 1123 | ssize_t remain; |
8c59967c DV |
1124 | loff_t offset; |
1125 | char __user *user_data; | |
eb2c0c81 | 1126 | int shmem_page_offset, page_length, ret = 0; |
8c59967c | 1127 | int obj_do_bit17_swizzling, page_do_bit17_swizzling; |
e244a443 | 1128 | int hit_slowpath = 0; |
58642885 DV |
1129 | int needs_clflush_after = 0; |
1130 | int needs_clflush_before = 0; | |
67d5a50c | 1131 | struct sg_page_iter sg_iter; |
40123c1f | 1132 | |
3ed605bc | 1133 | user_data = u64_to_user_ptr(args->data_ptr); |
40123c1f EA |
1134 | remain = args->size; |
1135 | ||
8c59967c | 1136 | obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj); |
40123c1f | 1137 | |
c13d87ea CW |
1138 | ret = i915_gem_object_wait_rendering(obj, false); |
1139 | if (ret) | |
1140 | return ret; | |
1141 | ||
58642885 DV |
1142 | if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) { |
1143 | /* If we're not in the cpu write domain, set ourself into the gtt | |
1144 | * write domain and manually flush cachelines (if required). This | |
1145 | * optimizes for the case when the gpu will use the data | |
1146 | * right away and we therefore have to clflush anyway. */ | |
2c22569b | 1147 | needs_clflush_after = cpu_write_needs_clflush(obj); |
58642885 | 1148 | } |
c76ce038 CW |
1149 | /* Same trick applies to invalidate partially written cachelines read |
1150 | * before writing. */ | |
1151 | if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) | |
1152 | needs_clflush_before = | |
1153 | !cpu_cache_is_coherent(dev, obj->cache_level); | |
58642885 | 1154 | |
755d2218 CW |
1155 | ret = i915_gem_object_get_pages(obj); |
1156 | if (ret) | |
1157 | return ret; | |
1158 | ||
77a0d1ca | 1159 | intel_fb_obj_invalidate(obj, ORIGIN_CPU); |
063e4e6b | 1160 | |
755d2218 CW |
1161 | i915_gem_object_pin_pages(obj); |
1162 | ||
673a394b | 1163 | offset = args->offset; |
05394f39 | 1164 | obj->dirty = 1; |
673a394b | 1165 | |
67d5a50c ID |
1166 | for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, |
1167 | offset >> PAGE_SHIFT) { | |
2db76d7c | 1168 | struct page *page = sg_page_iter_page(&sg_iter); |
58642885 | 1169 | int partial_cacheline_write; |
e5281ccd | 1170 | |
9da3da66 CW |
1171 | if (remain <= 0) |
1172 | break; | |
1173 | ||
40123c1f EA |
1174 | /* Operation in this page |
1175 | * | |
40123c1f | 1176 | * shmem_page_offset = offset within page in shmem file |
40123c1f EA |
1177 | * page_length = bytes to copy for this page |
1178 | */ | |
c8cbbb8b | 1179 | shmem_page_offset = offset_in_page(offset); |
40123c1f EA |
1180 | |
1181 | page_length = remain; | |
1182 | if ((shmem_page_offset + page_length) > PAGE_SIZE) | |
1183 | page_length = PAGE_SIZE - shmem_page_offset; | |
40123c1f | 1184 | |
58642885 DV |
1185 | /* If we don't overwrite a cacheline completely we need to be |
1186 | * careful to have up-to-date data by first clflushing. Don't | |
1187 | * overcomplicate things and flush the entire patch. */ | |
1188 | partial_cacheline_write = needs_clflush_before && | |
1189 | ((shmem_page_offset | page_length) | |
1190 | & (boot_cpu_data.x86_clflush_size - 1)); | |
1191 | ||
8c59967c DV |
1192 | page_do_bit17_swizzling = obj_do_bit17_swizzling && |
1193 | (page_to_phys(page) & (1 << 17)) != 0; | |
1194 | ||
d174bd64 DV |
1195 | ret = shmem_pwrite_fast(page, shmem_page_offset, page_length, |
1196 | user_data, page_do_bit17_swizzling, | |
1197 | partial_cacheline_write, | |
1198 | needs_clflush_after); | |
1199 | if (ret == 0) | |
1200 | goto next_page; | |
e244a443 DV |
1201 | |
1202 | hit_slowpath = 1; | |
e244a443 | 1203 | mutex_unlock(&dev->struct_mutex); |
d174bd64 DV |
1204 | ret = shmem_pwrite_slow(page, shmem_page_offset, page_length, |
1205 | user_data, page_do_bit17_swizzling, | |
1206 | partial_cacheline_write, | |
1207 | needs_clflush_after); | |
40123c1f | 1208 | |
e244a443 | 1209 | mutex_lock(&dev->struct_mutex); |
755d2218 | 1210 | |
755d2218 | 1211 | if (ret) |
8c59967c | 1212 | goto out; |
8c59967c | 1213 | |
17793c9a | 1214 | next_page: |
40123c1f | 1215 | remain -= page_length; |
8c59967c | 1216 | user_data += page_length; |
40123c1f | 1217 | offset += page_length; |
673a394b EA |
1218 | } |
1219 | ||
fbd5a26d | 1220 | out: |
755d2218 CW |
1221 | i915_gem_object_unpin_pages(obj); |
1222 | ||
e244a443 | 1223 | if (hit_slowpath) { |
8dcf015e DV |
1224 | /* |
1225 | * Fixup: Flush cpu caches in case we didn't flush the dirty | |
1226 | * cachelines in-line while writing and the object moved | |
1227 | * out of the cpu write domain while we've dropped the lock. | |
1228 | */ | |
1229 | if (!needs_clflush_after && | |
1230 | obj->base.write_domain != I915_GEM_DOMAIN_CPU) { | |
000433b6 | 1231 | if (i915_gem_clflush_object(obj, obj->pin_display)) |
ed75a55b | 1232 | needs_clflush_after = true; |
e244a443 | 1233 | } |
8c59967c | 1234 | } |
673a394b | 1235 | |
58642885 | 1236 | if (needs_clflush_after) |
c033666a | 1237 | i915_gem_chipset_flush(to_i915(dev)); |
ed75a55b VS |
1238 | else |
1239 | obj->cache_dirty = true; | |
58642885 | 1240 | |
de152b62 | 1241 | intel_fb_obj_flush(obj, false, ORIGIN_CPU); |
40123c1f | 1242 | return ret; |
673a394b EA |
1243 | } |
1244 | ||
1245 | /** | |
1246 | * Writes data to the object referenced by handle. | |
14bb2c11 TU |
1247 | * @dev: drm device |
1248 | * @data: ioctl data blob | |
1249 | * @file: drm file | |
673a394b EA |
1250 | * |
1251 | * On error, the contents of the buffer that were to be modified are undefined. | |
1252 | */ | |
1253 | int | |
1254 | i915_gem_pwrite_ioctl(struct drm_device *dev, void *data, | |
fbd5a26d | 1255 | struct drm_file *file) |
673a394b | 1256 | { |
fac5e23e | 1257 | struct drm_i915_private *dev_priv = to_i915(dev); |
673a394b | 1258 | struct drm_i915_gem_pwrite *args = data; |
05394f39 | 1259 | struct drm_i915_gem_object *obj; |
51311d0a CW |
1260 | int ret; |
1261 | ||
1262 | if (args->size == 0) | |
1263 | return 0; | |
1264 | ||
1265 | if (!access_ok(VERIFY_READ, | |
3ed605bc | 1266 | u64_to_user_ptr(args->data_ptr), |
51311d0a CW |
1267 | args->size)) |
1268 | return -EFAULT; | |
1269 | ||
d330a953 | 1270 | if (likely(!i915.prefault_disable)) { |
3ed605bc | 1271 | ret = fault_in_multipages_readable(u64_to_user_ptr(args->data_ptr), |
0b74b508 XZ |
1272 | args->size); |
1273 | if (ret) | |
1274 | return -EFAULT; | |
1275 | } | |
673a394b | 1276 | |
5d77d9c5 ID |
1277 | intel_runtime_pm_get(dev_priv); |
1278 | ||
fbd5a26d | 1279 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 1280 | if (ret) |
5d77d9c5 | 1281 | goto put_rpm; |
1d7cfea1 | 1282 | |
03ac0642 CW |
1283 | obj = i915_gem_object_lookup(file, args->handle); |
1284 | if (!obj) { | |
1d7cfea1 CW |
1285 | ret = -ENOENT; |
1286 | goto unlock; | |
fbd5a26d | 1287 | } |
673a394b | 1288 | |
7dcd2499 | 1289 | /* Bounds check destination. */ |
05394f39 CW |
1290 | if (args->offset > obj->base.size || |
1291 | args->size > obj->base.size - args->offset) { | |
ce9d419d | 1292 | ret = -EINVAL; |
35b62a89 | 1293 | goto out; |
ce9d419d CW |
1294 | } |
1295 | ||
db53a302 CW |
1296 | trace_i915_gem_object_pwrite(obj, args->offset, args->size); |
1297 | ||
935aaa69 | 1298 | ret = -EFAULT; |
673a394b EA |
1299 | /* We can only do the GTT pwrite on untiled buffers, as otherwise |
1300 | * it would end up going through the fenced access, and we'll get | |
1301 | * different detiling behavior between reading and writing. | |
1302 | * pread/pwrite currently are reading and writing from the CPU | |
1303 | * perspective, requiring manual detiling by the client. | |
1304 | */ | |
6eae0059 CW |
1305 | if (!i915_gem_object_has_struct_page(obj) || |
1306 | cpu_write_needs_clflush(obj)) { | |
4f1959ee | 1307 | ret = i915_gem_gtt_pwrite_fast(dev_priv, obj, args, file); |
935aaa69 DV |
1308 | /* Note that the gtt paths might fail with non-page-backed user |
1309 | * pointers (e.g. gtt mappings when moving data between | |
1310 | * textures). Fallback to the shmem path in that case. */ | |
fbd5a26d | 1311 | } |
673a394b | 1312 | |
d1054ee4 | 1313 | if (ret == -EFAULT || ret == -ENOSPC) { |
6a2c4232 CW |
1314 | if (obj->phys_handle) |
1315 | ret = i915_gem_phys_pwrite(obj, args, file); | |
6eae0059 | 1316 | else if (i915_gem_object_has_struct_page(obj)) |
6a2c4232 | 1317 | ret = i915_gem_shmem_pwrite(dev, obj, args, file); |
b50a5371 AS |
1318 | else |
1319 | ret = -ENODEV; | |
6a2c4232 | 1320 | } |
5c0480f2 | 1321 | |
35b62a89 | 1322 | out: |
f8c417cd | 1323 | i915_gem_object_put(obj); |
1d7cfea1 | 1324 | unlock: |
fbd5a26d | 1325 | mutex_unlock(&dev->struct_mutex); |
5d77d9c5 ID |
1326 | put_rpm: |
1327 | intel_runtime_pm_put(dev_priv); | |
1328 | ||
673a394b EA |
1329 | return ret; |
1330 | } | |
1331 | ||
b361237b CW |
1332 | /** |
1333 | * Ensures that all rendering to the object has completed and the object is | |
1334 | * safe to unbind from the GTT or access from the CPU. | |
14bb2c11 TU |
1335 | * @obj: i915 gem object |
1336 | * @readonly: waiting for read access or write | |
b361237b | 1337 | */ |
2e2f351d | 1338 | int |
b361237b CW |
1339 | i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj, |
1340 | bool readonly) | |
1341 | { | |
c13d87ea | 1342 | struct reservation_object *resv; |
b4716185 | 1343 | int ret, i; |
b361237b | 1344 | |
b4716185 CW |
1345 | if (readonly) { |
1346 | if (obj->last_write_req != NULL) { | |
1347 | ret = i915_wait_request(obj->last_write_req); | |
1348 | if (ret) | |
1349 | return ret; | |
b361237b | 1350 | |
4a570db5 | 1351 | i = obj->last_write_req->engine->id; |
b4716185 CW |
1352 | if (obj->last_read_req[i] == obj->last_write_req) |
1353 | i915_gem_object_retire__read(obj, i); | |
1354 | else | |
1355 | i915_gem_object_retire__write(obj); | |
1356 | } | |
1357 | } else { | |
666796da | 1358 | for (i = 0; i < I915_NUM_ENGINES; i++) { |
b4716185 CW |
1359 | if (obj->last_read_req[i] == NULL) |
1360 | continue; | |
1361 | ||
1362 | ret = i915_wait_request(obj->last_read_req[i]); | |
1363 | if (ret) | |
1364 | return ret; | |
1365 | ||
1366 | i915_gem_object_retire__read(obj, i); | |
1367 | } | |
d501b1d2 | 1368 | GEM_BUG_ON(obj->active); |
b4716185 CW |
1369 | } |
1370 | ||
c13d87ea CW |
1371 | resv = i915_gem_object_get_dmabuf_resv(obj); |
1372 | if (resv) { | |
1373 | long err; | |
1374 | ||
1375 | err = reservation_object_wait_timeout_rcu(resv, !readonly, true, | |
1376 | MAX_SCHEDULE_TIMEOUT); | |
1377 | if (err < 0) | |
1378 | return err; | |
1379 | } | |
1380 | ||
b4716185 CW |
1381 | return 0; |
1382 | } | |
1383 | ||
1384 | static void | |
1385 | i915_gem_object_retire_request(struct drm_i915_gem_object *obj, | |
1386 | struct drm_i915_gem_request *req) | |
1387 | { | |
7e21d648 | 1388 | int idx = req->engine->id; |
b4716185 | 1389 | |
7e21d648 CW |
1390 | if (obj->last_read_req[idx] == req) |
1391 | i915_gem_object_retire__read(obj, idx); | |
b4716185 CW |
1392 | else if (obj->last_write_req == req) |
1393 | i915_gem_object_retire__write(obj); | |
1394 | ||
0c5eed65 | 1395 | if (!i915_reset_in_progress(&req->i915->gpu_error)) |
05235c53 | 1396 | i915_gem_request_retire_upto(req); |
b361237b CW |
1397 | } |
1398 | ||
3236f57a CW |
1399 | /* A nonblocking variant of the above wait. This is a highly dangerous routine |
1400 | * as the object state may change during this call. | |
1401 | */ | |
1402 | static __must_check int | |
1403 | i915_gem_object_wait_rendering__nonblocking(struct drm_i915_gem_object *obj, | |
2e1b8730 | 1404 | struct intel_rps_client *rps, |
3236f57a CW |
1405 | bool readonly) |
1406 | { | |
1407 | struct drm_device *dev = obj->base.dev; | |
fac5e23e | 1408 | struct drm_i915_private *dev_priv = to_i915(dev); |
666796da | 1409 | struct drm_i915_gem_request *requests[I915_NUM_ENGINES]; |
b4716185 | 1410 | int ret, i, n = 0; |
3236f57a CW |
1411 | |
1412 | BUG_ON(!mutex_is_locked(&dev->struct_mutex)); | |
1413 | BUG_ON(!dev_priv->mm.interruptible); | |
1414 | ||
b4716185 | 1415 | if (!obj->active) |
3236f57a CW |
1416 | return 0; |
1417 | ||
b4716185 CW |
1418 | if (readonly) { |
1419 | struct drm_i915_gem_request *req; | |
1420 | ||
1421 | req = obj->last_write_req; | |
1422 | if (req == NULL) | |
1423 | return 0; | |
1424 | ||
e8a261ea | 1425 | requests[n++] = i915_gem_request_get(req); |
b4716185 | 1426 | } else { |
666796da | 1427 | for (i = 0; i < I915_NUM_ENGINES; i++) { |
b4716185 CW |
1428 | struct drm_i915_gem_request *req; |
1429 | ||
1430 | req = obj->last_read_req[i]; | |
1431 | if (req == NULL) | |
1432 | continue; | |
1433 | ||
e8a261ea | 1434 | requests[n++] = i915_gem_request_get(req); |
b4716185 CW |
1435 | } |
1436 | } | |
1437 | ||
3236f57a | 1438 | mutex_unlock(&dev->struct_mutex); |
299259a3 | 1439 | ret = 0; |
b4716185 | 1440 | for (i = 0; ret == 0 && i < n; i++) |
299259a3 | 1441 | ret = __i915_wait_request(requests[i], true, NULL, rps); |
3236f57a CW |
1442 | mutex_lock(&dev->struct_mutex); |
1443 | ||
b4716185 CW |
1444 | for (i = 0; i < n; i++) { |
1445 | if (ret == 0) | |
1446 | i915_gem_object_retire_request(obj, requests[i]); | |
e8a261ea | 1447 | i915_gem_request_put(requests[i]); |
b4716185 CW |
1448 | } |
1449 | ||
1450 | return ret; | |
3236f57a CW |
1451 | } |
1452 | ||
2e1b8730 CW |
1453 | static struct intel_rps_client *to_rps_client(struct drm_file *file) |
1454 | { | |
1455 | struct drm_i915_file_private *fpriv = file->driver_priv; | |
1456 | return &fpriv->rps; | |
1457 | } | |
1458 | ||
aeecc969 CW |
1459 | static enum fb_op_origin |
1460 | write_origin(struct drm_i915_gem_object *obj, unsigned domain) | |
1461 | { | |
1462 | return domain == I915_GEM_DOMAIN_GTT && !obj->has_wc_mmap ? | |
1463 | ORIGIN_GTT : ORIGIN_CPU; | |
1464 | } | |
1465 | ||
673a394b | 1466 | /** |
2ef7eeaa EA |
1467 | * Called when user space prepares to use an object with the CPU, either |
1468 | * through the mmap ioctl's mapping or a GTT mapping. | |
14bb2c11 TU |
1469 | * @dev: drm device |
1470 | * @data: ioctl data blob | |
1471 | * @file: drm file | |
673a394b EA |
1472 | */ |
1473 | int | |
1474 | i915_gem_set_domain_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 1475 | struct drm_file *file) |
673a394b EA |
1476 | { |
1477 | struct drm_i915_gem_set_domain *args = data; | |
05394f39 | 1478 | struct drm_i915_gem_object *obj; |
2ef7eeaa EA |
1479 | uint32_t read_domains = args->read_domains; |
1480 | uint32_t write_domain = args->write_domain; | |
673a394b EA |
1481 | int ret; |
1482 | ||
2ef7eeaa | 1483 | /* Only handle setting domains to types used by the CPU. */ |
21d509e3 | 1484 | if (write_domain & I915_GEM_GPU_DOMAINS) |
2ef7eeaa EA |
1485 | return -EINVAL; |
1486 | ||
21d509e3 | 1487 | if (read_domains & I915_GEM_GPU_DOMAINS) |
2ef7eeaa EA |
1488 | return -EINVAL; |
1489 | ||
1490 | /* Having something in the write domain implies it's in the read | |
1491 | * domain, and only that read domain. Enforce that in the request. | |
1492 | */ | |
1493 | if (write_domain != 0 && read_domains != write_domain) | |
1494 | return -EINVAL; | |
1495 | ||
76c1dec1 | 1496 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 1497 | if (ret) |
76c1dec1 | 1498 | return ret; |
1d7cfea1 | 1499 | |
03ac0642 CW |
1500 | obj = i915_gem_object_lookup(file, args->handle); |
1501 | if (!obj) { | |
1d7cfea1 CW |
1502 | ret = -ENOENT; |
1503 | goto unlock; | |
76c1dec1 | 1504 | } |
673a394b | 1505 | |
3236f57a CW |
1506 | /* Try to flush the object off the GPU without holding the lock. |
1507 | * We will repeat the flush holding the lock in the normal manner | |
1508 | * to catch cases where we are gazumped. | |
1509 | */ | |
6e4930f6 | 1510 | ret = i915_gem_object_wait_rendering__nonblocking(obj, |
2e1b8730 | 1511 | to_rps_client(file), |
6e4930f6 | 1512 | !write_domain); |
3236f57a CW |
1513 | if (ret) |
1514 | goto unref; | |
1515 | ||
43566ded | 1516 | if (read_domains & I915_GEM_DOMAIN_GTT) |
2ef7eeaa | 1517 | ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0); |
43566ded | 1518 | else |
e47c68e9 | 1519 | ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0); |
2ef7eeaa | 1520 | |
031b698a | 1521 | if (write_domain != 0) |
aeecc969 | 1522 | intel_fb_obj_invalidate(obj, write_origin(obj, write_domain)); |
031b698a | 1523 | |
3236f57a | 1524 | unref: |
f8c417cd | 1525 | i915_gem_object_put(obj); |
1d7cfea1 | 1526 | unlock: |
673a394b EA |
1527 | mutex_unlock(&dev->struct_mutex); |
1528 | return ret; | |
1529 | } | |
1530 | ||
1531 | /** | |
1532 | * Called when user space has done writes to this buffer | |
14bb2c11 TU |
1533 | * @dev: drm device |
1534 | * @data: ioctl data blob | |
1535 | * @file: drm file | |
673a394b EA |
1536 | */ |
1537 | int | |
1538 | i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 1539 | struct drm_file *file) |
673a394b EA |
1540 | { |
1541 | struct drm_i915_gem_sw_finish *args = data; | |
05394f39 | 1542 | struct drm_i915_gem_object *obj; |
673a394b EA |
1543 | int ret = 0; |
1544 | ||
76c1dec1 | 1545 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 1546 | if (ret) |
76c1dec1 | 1547 | return ret; |
1d7cfea1 | 1548 | |
03ac0642 CW |
1549 | obj = i915_gem_object_lookup(file, args->handle); |
1550 | if (!obj) { | |
1d7cfea1 CW |
1551 | ret = -ENOENT; |
1552 | goto unlock; | |
673a394b EA |
1553 | } |
1554 | ||
673a394b | 1555 | /* Pinned buffers may be scanout, so flush the cache */ |
2c22569b | 1556 | if (obj->pin_display) |
e62b59e4 | 1557 | i915_gem_object_flush_cpu_write_domain(obj); |
e47c68e9 | 1558 | |
f8c417cd | 1559 | i915_gem_object_put(obj); |
1d7cfea1 | 1560 | unlock: |
673a394b EA |
1561 | mutex_unlock(&dev->struct_mutex); |
1562 | return ret; | |
1563 | } | |
1564 | ||
1565 | /** | |
14bb2c11 TU |
1566 | * i915_gem_mmap_ioctl - Maps the contents of an object, returning the address |
1567 | * it is mapped to. | |
1568 | * @dev: drm device | |
1569 | * @data: ioctl data blob | |
1570 | * @file: drm file | |
673a394b EA |
1571 | * |
1572 | * While the mapping holds a reference on the contents of the object, it doesn't | |
1573 | * imply a ref on the object itself. | |
34367381 DV |
1574 | * |
1575 | * IMPORTANT: | |
1576 | * | |
1577 | * DRM driver writers who look a this function as an example for how to do GEM | |
1578 | * mmap support, please don't implement mmap support like here. The modern way | |
1579 | * to implement DRM mmap support is with an mmap offset ioctl (like | |
1580 | * i915_gem_mmap_gtt) and then using the mmap syscall on the DRM fd directly. | |
1581 | * That way debug tooling like valgrind will understand what's going on, hiding | |
1582 | * the mmap call in a driver private ioctl will break that. The i915 driver only | |
1583 | * does cpu mmaps this way because we didn't know better. | |
673a394b EA |
1584 | */ |
1585 | int | |
1586 | i915_gem_mmap_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 1587 | struct drm_file *file) |
673a394b EA |
1588 | { |
1589 | struct drm_i915_gem_mmap *args = data; | |
03ac0642 | 1590 | struct drm_i915_gem_object *obj; |
673a394b EA |
1591 | unsigned long addr; |
1592 | ||
1816f923 AG |
1593 | if (args->flags & ~(I915_MMAP_WC)) |
1594 | return -EINVAL; | |
1595 | ||
568a58e5 | 1596 | if (args->flags & I915_MMAP_WC && !boot_cpu_has(X86_FEATURE_PAT)) |
1816f923 AG |
1597 | return -ENODEV; |
1598 | ||
03ac0642 CW |
1599 | obj = i915_gem_object_lookup(file, args->handle); |
1600 | if (!obj) | |
bf79cb91 | 1601 | return -ENOENT; |
673a394b | 1602 | |
1286ff73 DV |
1603 | /* prime objects have no backing filp to GEM mmap |
1604 | * pages from. | |
1605 | */ | |
03ac0642 | 1606 | if (!obj->base.filp) { |
34911fd3 | 1607 | i915_gem_object_put_unlocked(obj); |
1286ff73 DV |
1608 | return -EINVAL; |
1609 | } | |
1610 | ||
03ac0642 | 1611 | addr = vm_mmap(obj->base.filp, 0, args->size, |
673a394b EA |
1612 | PROT_READ | PROT_WRITE, MAP_SHARED, |
1613 | args->offset); | |
1816f923 AG |
1614 | if (args->flags & I915_MMAP_WC) { |
1615 | struct mm_struct *mm = current->mm; | |
1616 | struct vm_area_struct *vma; | |
1617 | ||
80a89a5e | 1618 | if (down_write_killable(&mm->mmap_sem)) { |
34911fd3 | 1619 | i915_gem_object_put_unlocked(obj); |
80a89a5e MH |
1620 | return -EINTR; |
1621 | } | |
1816f923 AG |
1622 | vma = find_vma(mm, addr); |
1623 | if (vma) | |
1624 | vma->vm_page_prot = | |
1625 | pgprot_writecombine(vm_get_page_prot(vma->vm_flags)); | |
1626 | else | |
1627 | addr = -ENOMEM; | |
1628 | up_write(&mm->mmap_sem); | |
aeecc969 CW |
1629 | |
1630 | /* This may race, but that's ok, it only gets set */ | |
03ac0642 | 1631 | WRITE_ONCE(obj->has_wc_mmap, true); |
1816f923 | 1632 | } |
34911fd3 | 1633 | i915_gem_object_put_unlocked(obj); |
673a394b EA |
1634 | if (IS_ERR((void *)addr)) |
1635 | return addr; | |
1636 | ||
1637 | args->addr_ptr = (uint64_t) addr; | |
1638 | ||
1639 | return 0; | |
1640 | } | |
1641 | ||
de151cf6 JB |
1642 | /** |
1643 | * i915_gem_fault - fault a page into the GTT | |
d9072a3e GT |
1644 | * @vma: VMA in question |
1645 | * @vmf: fault info | |
de151cf6 JB |
1646 | * |
1647 | * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped | |
1648 | * from userspace. The fault handler takes care of binding the object to | |
1649 | * the GTT (if needed), allocating and programming a fence register (again, | |
1650 | * only if needed based on whether the old reg is still valid or the object | |
1651 | * is tiled) and inserting a new PTE into the faulting process. | |
1652 | * | |
1653 | * Note that the faulting process may involve evicting existing objects | |
1654 | * from the GTT and/or fence registers to make room. So performance may | |
1655 | * suffer if the GTT working set is large or there are few fence registers | |
1656 | * left. | |
1657 | */ | |
1658 | int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf) | |
1659 | { | |
05394f39 CW |
1660 | struct drm_i915_gem_object *obj = to_intel_bo(vma->vm_private_data); |
1661 | struct drm_device *dev = obj->base.dev; | |
72e96d64 JL |
1662 | struct drm_i915_private *dev_priv = to_i915(dev); |
1663 | struct i915_ggtt *ggtt = &dev_priv->ggtt; | |
c5ad54cf | 1664 | struct i915_ggtt_view view = i915_ggtt_view_normal; |
de151cf6 JB |
1665 | pgoff_t page_offset; |
1666 | unsigned long pfn; | |
1667 | int ret = 0; | |
0f973f27 | 1668 | bool write = !!(vmf->flags & FAULT_FLAG_WRITE); |
de151cf6 | 1669 | |
f65c9168 PZ |
1670 | intel_runtime_pm_get(dev_priv); |
1671 | ||
de151cf6 JB |
1672 | /* We don't use vmf->pgoff since that has the fake offset */ |
1673 | page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >> | |
1674 | PAGE_SHIFT; | |
1675 | ||
d9bc7e9f CW |
1676 | ret = i915_mutex_lock_interruptible(dev); |
1677 | if (ret) | |
1678 | goto out; | |
a00b10c3 | 1679 | |
db53a302 CW |
1680 | trace_i915_gem_object_fault(obj, page_offset, true, write); |
1681 | ||
6e4930f6 CW |
1682 | /* Try to flush the object off the GPU first without holding the lock. |
1683 | * Upon reacquiring the lock, we will perform our sanity checks and then | |
1684 | * repeat the flush holding the lock in the normal manner to catch cases | |
1685 | * where we are gazumped. | |
1686 | */ | |
1687 | ret = i915_gem_object_wait_rendering__nonblocking(obj, NULL, !write); | |
1688 | if (ret) | |
1689 | goto unlock; | |
1690 | ||
eb119bd6 CW |
1691 | /* Access to snoopable pages through the GTT is incoherent. */ |
1692 | if (obj->cache_level != I915_CACHE_NONE && !HAS_LLC(dev)) { | |
ddeff6ee | 1693 | ret = -EFAULT; |
eb119bd6 CW |
1694 | goto unlock; |
1695 | } | |
1696 | ||
c5ad54cf | 1697 | /* Use a partial view if the object is bigger than the aperture. */ |
72e96d64 | 1698 | if (obj->base.size >= ggtt->mappable_end && |
e7ded2d7 | 1699 | obj->tiling_mode == I915_TILING_NONE) { |
c5ad54cf | 1700 | static const unsigned int chunk_size = 256; // 1 MiB |
e7ded2d7 | 1701 | |
c5ad54cf JL |
1702 | memset(&view, 0, sizeof(view)); |
1703 | view.type = I915_GGTT_VIEW_PARTIAL; | |
1704 | view.params.partial.offset = rounddown(page_offset, chunk_size); | |
1705 | view.params.partial.size = | |
1706 | min_t(unsigned int, | |
1707 | chunk_size, | |
1708 | (vma->vm_end - vma->vm_start)/PAGE_SIZE - | |
1709 | view.params.partial.offset); | |
1710 | } | |
1711 | ||
1712 | /* Now pin it into the GTT if needed */ | |
1713 | ret = i915_gem_object_ggtt_pin(obj, &view, 0, PIN_MAPPABLE); | |
c9839303 CW |
1714 | if (ret) |
1715 | goto unlock; | |
4a684a41 | 1716 | |
c9839303 CW |
1717 | ret = i915_gem_object_set_to_gtt_domain(obj, write); |
1718 | if (ret) | |
1719 | goto unpin; | |
74898d7e | 1720 | |
06d98131 | 1721 | ret = i915_gem_object_get_fence(obj); |
d9e86c0e | 1722 | if (ret) |
c9839303 | 1723 | goto unpin; |
7d1c4804 | 1724 | |
b90b91d8 | 1725 | /* Finally, remap it using the new GTT offset */ |
72e96d64 | 1726 | pfn = ggtt->mappable_base + |
c5ad54cf | 1727 | i915_gem_obj_ggtt_offset_view(obj, &view); |
f343c5f6 | 1728 | pfn >>= PAGE_SHIFT; |
de151cf6 | 1729 | |
c5ad54cf JL |
1730 | if (unlikely(view.type == I915_GGTT_VIEW_PARTIAL)) { |
1731 | /* Overriding existing pages in partial view does not cause | |
1732 | * us any trouble as TLBs are still valid because the fault | |
1733 | * is due to userspace losing part of the mapping or never | |
1734 | * having accessed it before (at this partials' range). | |
1735 | */ | |
1736 | unsigned long base = vma->vm_start + | |
1737 | (view.params.partial.offset << PAGE_SHIFT); | |
1738 | unsigned int i; | |
b90b91d8 | 1739 | |
c5ad54cf JL |
1740 | for (i = 0; i < view.params.partial.size; i++) { |
1741 | ret = vm_insert_pfn(vma, base + i * PAGE_SIZE, pfn + i); | |
b90b91d8 CW |
1742 | if (ret) |
1743 | break; | |
1744 | } | |
1745 | ||
1746 | obj->fault_mappable = true; | |
c5ad54cf JL |
1747 | } else { |
1748 | if (!obj->fault_mappable) { | |
1749 | unsigned long size = min_t(unsigned long, | |
1750 | vma->vm_end - vma->vm_start, | |
1751 | obj->base.size); | |
1752 | int i; | |
1753 | ||
1754 | for (i = 0; i < size >> PAGE_SHIFT; i++) { | |
1755 | ret = vm_insert_pfn(vma, | |
1756 | (unsigned long)vma->vm_start + i * PAGE_SIZE, | |
1757 | pfn + i); | |
1758 | if (ret) | |
1759 | break; | |
1760 | } | |
1761 | ||
1762 | obj->fault_mappable = true; | |
1763 | } else | |
1764 | ret = vm_insert_pfn(vma, | |
1765 | (unsigned long)vmf->virtual_address, | |
1766 | pfn + page_offset); | |
1767 | } | |
c9839303 | 1768 | unpin: |
c5ad54cf | 1769 | i915_gem_object_ggtt_unpin_view(obj, &view); |
c715089f | 1770 | unlock: |
de151cf6 | 1771 | mutex_unlock(&dev->struct_mutex); |
d9bc7e9f | 1772 | out: |
de151cf6 | 1773 | switch (ret) { |
d9bc7e9f | 1774 | case -EIO: |
2232f031 DV |
1775 | /* |
1776 | * We eat errors when the gpu is terminally wedged to avoid | |
1777 | * userspace unduly crashing (gl has no provisions for mmaps to | |
1778 | * fail). But any other -EIO isn't ours (e.g. swap in failure) | |
1779 | * and so needs to be reported. | |
1780 | */ | |
1781 | if (!i915_terminally_wedged(&dev_priv->gpu_error)) { | |
f65c9168 PZ |
1782 | ret = VM_FAULT_SIGBUS; |
1783 | break; | |
1784 | } | |
045e769a | 1785 | case -EAGAIN: |
571c608d DV |
1786 | /* |
1787 | * EAGAIN means the gpu is hung and we'll wait for the error | |
1788 | * handler to reset everything when re-faulting in | |
1789 | * i915_mutex_lock_interruptible. | |
d9bc7e9f | 1790 | */ |
c715089f CW |
1791 | case 0: |
1792 | case -ERESTARTSYS: | |
bed636ab | 1793 | case -EINTR: |
e79e0fe3 DR |
1794 | case -EBUSY: |
1795 | /* | |
1796 | * EBUSY is ok: this just means that another thread | |
1797 | * already did the job. | |
1798 | */ | |
f65c9168 PZ |
1799 | ret = VM_FAULT_NOPAGE; |
1800 | break; | |
de151cf6 | 1801 | case -ENOMEM: |
f65c9168 PZ |
1802 | ret = VM_FAULT_OOM; |
1803 | break; | |
a7c2e1aa | 1804 | case -ENOSPC: |
45d67817 | 1805 | case -EFAULT: |
f65c9168 PZ |
1806 | ret = VM_FAULT_SIGBUS; |
1807 | break; | |
de151cf6 | 1808 | default: |
a7c2e1aa | 1809 | WARN_ONCE(ret, "unhandled error in i915_gem_fault: %i\n", ret); |
f65c9168 PZ |
1810 | ret = VM_FAULT_SIGBUS; |
1811 | break; | |
de151cf6 | 1812 | } |
f65c9168 PZ |
1813 | |
1814 | intel_runtime_pm_put(dev_priv); | |
1815 | return ret; | |
de151cf6 JB |
1816 | } |
1817 | ||
901782b2 CW |
1818 | /** |
1819 | * i915_gem_release_mmap - remove physical page mappings | |
1820 | * @obj: obj in question | |
1821 | * | |
af901ca1 | 1822 | * Preserve the reservation of the mmapping with the DRM core code, but |
901782b2 CW |
1823 | * relinquish ownership of the pages back to the system. |
1824 | * | |
1825 | * It is vital that we remove the page mapping if we have mapped a tiled | |
1826 | * object through the GTT and then lose the fence register due to | |
1827 | * resource pressure. Similarly if the object has been moved out of the | |
1828 | * aperture, than pages mapped into userspace must be revoked. Removing the | |
1829 | * mapping will then trigger a page fault on the next user access, allowing | |
1830 | * fixup by i915_gem_fault(). | |
1831 | */ | |
d05ca301 | 1832 | void |
05394f39 | 1833 | i915_gem_release_mmap(struct drm_i915_gem_object *obj) |
901782b2 | 1834 | { |
349f2ccf CW |
1835 | /* Serialisation between user GTT access and our code depends upon |
1836 | * revoking the CPU's PTE whilst the mutex is held. The next user | |
1837 | * pagefault then has to wait until we release the mutex. | |
1838 | */ | |
1839 | lockdep_assert_held(&obj->base.dev->struct_mutex); | |
1840 | ||
6299f992 CW |
1841 | if (!obj->fault_mappable) |
1842 | return; | |
901782b2 | 1843 | |
6796cb16 DH |
1844 | drm_vma_node_unmap(&obj->base.vma_node, |
1845 | obj->base.dev->anon_inode->i_mapping); | |
349f2ccf CW |
1846 | |
1847 | /* Ensure that the CPU's PTE are revoked and there are not outstanding | |
1848 | * memory transactions from userspace before we return. The TLB | |
1849 | * flushing implied above by changing the PTE above *should* be | |
1850 | * sufficient, an extra barrier here just provides us with a bit | |
1851 | * of paranoid documentation about our requirement to serialise | |
1852 | * memory writes before touching registers / GSM. | |
1853 | */ | |
1854 | wmb(); | |
1855 | ||
6299f992 | 1856 | obj->fault_mappable = false; |
901782b2 CW |
1857 | } |
1858 | ||
eedd10f4 CW |
1859 | void |
1860 | i915_gem_release_all_mmaps(struct drm_i915_private *dev_priv) | |
1861 | { | |
1862 | struct drm_i915_gem_object *obj; | |
1863 | ||
1864 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) | |
1865 | i915_gem_release_mmap(obj); | |
1866 | } | |
1867 | ||
0fa87796 | 1868 | uint32_t |
e28f8711 | 1869 | i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode) |
92b88aeb | 1870 | { |
e28f8711 | 1871 | uint32_t gtt_size; |
92b88aeb CW |
1872 | |
1873 | if (INTEL_INFO(dev)->gen >= 4 || | |
e28f8711 CW |
1874 | tiling_mode == I915_TILING_NONE) |
1875 | return size; | |
92b88aeb CW |
1876 | |
1877 | /* Previous chips need a power-of-two fence region when tiling */ | |
7e22dbbb | 1878 | if (IS_GEN3(dev)) |
e28f8711 | 1879 | gtt_size = 1024*1024; |
92b88aeb | 1880 | else |
e28f8711 | 1881 | gtt_size = 512*1024; |
92b88aeb | 1882 | |
e28f8711 CW |
1883 | while (gtt_size < size) |
1884 | gtt_size <<= 1; | |
92b88aeb | 1885 | |
e28f8711 | 1886 | return gtt_size; |
92b88aeb CW |
1887 | } |
1888 | ||
de151cf6 JB |
1889 | /** |
1890 | * i915_gem_get_gtt_alignment - return required GTT alignment for an object | |
14bb2c11 TU |
1891 | * @dev: drm device |
1892 | * @size: object size | |
1893 | * @tiling_mode: tiling mode | |
1894 | * @fenced: is fenced alignemned required or not | |
de151cf6 JB |
1895 | * |
1896 | * Return the required GTT alignment for an object, taking into account | |
5e783301 | 1897 | * potential fence register mapping. |
de151cf6 | 1898 | */ |
d865110c ID |
1899 | uint32_t |
1900 | i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size, | |
1901 | int tiling_mode, bool fenced) | |
de151cf6 | 1902 | { |
de151cf6 JB |
1903 | /* |
1904 | * Minimum alignment is 4k (GTT page size), but might be greater | |
1905 | * if a fence register is needed for the object. | |
1906 | */ | |
d865110c | 1907 | if (INTEL_INFO(dev)->gen >= 4 || (!fenced && IS_G33(dev)) || |
e28f8711 | 1908 | tiling_mode == I915_TILING_NONE) |
de151cf6 JB |
1909 | return 4096; |
1910 | ||
a00b10c3 CW |
1911 | /* |
1912 | * Previous chips need to be aligned to the size of the smallest | |
1913 | * fence register that can contain the object. | |
1914 | */ | |
e28f8711 | 1915 | return i915_gem_get_gtt_size(dev, size, tiling_mode); |
a00b10c3 CW |
1916 | } |
1917 | ||
d8cb5086 CW |
1918 | static int i915_gem_object_create_mmap_offset(struct drm_i915_gem_object *obj) |
1919 | { | |
fac5e23e | 1920 | struct drm_i915_private *dev_priv = to_i915(obj->base.dev); |
d8cb5086 CW |
1921 | int ret; |
1922 | ||
da494d7c DV |
1923 | dev_priv->mm.shrinker_no_lock_stealing = true; |
1924 | ||
d8cb5086 CW |
1925 | ret = drm_gem_create_mmap_offset(&obj->base); |
1926 | if (ret != -ENOSPC) | |
da494d7c | 1927 | goto out; |
d8cb5086 CW |
1928 | |
1929 | /* Badly fragmented mmap space? The only way we can recover | |
1930 | * space is by destroying unwanted objects. We can't randomly release | |
1931 | * mmap_offsets as userspace expects them to be persistent for the | |
1932 | * lifetime of the objects. The closest we can is to release the | |
1933 | * offsets on purgeable objects by truncating it and marking it purged, | |
1934 | * which prevents userspace from ever using that object again. | |
1935 | */ | |
21ab4e74 CW |
1936 | i915_gem_shrink(dev_priv, |
1937 | obj->base.size >> PAGE_SHIFT, | |
1938 | I915_SHRINK_BOUND | | |
1939 | I915_SHRINK_UNBOUND | | |
1940 | I915_SHRINK_PURGEABLE); | |
d8cb5086 CW |
1941 | ret = drm_gem_create_mmap_offset(&obj->base); |
1942 | if (ret != -ENOSPC) | |
da494d7c | 1943 | goto out; |
d8cb5086 CW |
1944 | |
1945 | i915_gem_shrink_all(dev_priv); | |
da494d7c DV |
1946 | ret = drm_gem_create_mmap_offset(&obj->base); |
1947 | out: | |
1948 | dev_priv->mm.shrinker_no_lock_stealing = false; | |
1949 | ||
1950 | return ret; | |
d8cb5086 CW |
1951 | } |
1952 | ||
1953 | static void i915_gem_object_free_mmap_offset(struct drm_i915_gem_object *obj) | |
1954 | { | |
d8cb5086 CW |
1955 | drm_gem_free_mmap_offset(&obj->base); |
1956 | } | |
1957 | ||
da6b51d0 | 1958 | int |
ff72145b DA |
1959 | i915_gem_mmap_gtt(struct drm_file *file, |
1960 | struct drm_device *dev, | |
da6b51d0 | 1961 | uint32_t handle, |
ff72145b | 1962 | uint64_t *offset) |
de151cf6 | 1963 | { |
05394f39 | 1964 | struct drm_i915_gem_object *obj; |
de151cf6 JB |
1965 | int ret; |
1966 | ||
76c1dec1 | 1967 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 1968 | if (ret) |
76c1dec1 | 1969 | return ret; |
de151cf6 | 1970 | |
03ac0642 CW |
1971 | obj = i915_gem_object_lookup(file, handle); |
1972 | if (!obj) { | |
1d7cfea1 CW |
1973 | ret = -ENOENT; |
1974 | goto unlock; | |
1975 | } | |
de151cf6 | 1976 | |
05394f39 | 1977 | if (obj->madv != I915_MADV_WILLNEED) { |
bd9b6a4e | 1978 | DRM_DEBUG("Attempting to mmap a purgeable buffer\n"); |
8c99e57d | 1979 | ret = -EFAULT; |
1d7cfea1 | 1980 | goto out; |
ab18282d CW |
1981 | } |
1982 | ||
d8cb5086 CW |
1983 | ret = i915_gem_object_create_mmap_offset(obj); |
1984 | if (ret) | |
1985 | goto out; | |
de151cf6 | 1986 | |
0de23977 | 1987 | *offset = drm_vma_node_offset_addr(&obj->base.vma_node); |
de151cf6 | 1988 | |
1d7cfea1 | 1989 | out: |
f8c417cd | 1990 | i915_gem_object_put(obj); |
1d7cfea1 | 1991 | unlock: |
de151cf6 | 1992 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 1993 | return ret; |
de151cf6 JB |
1994 | } |
1995 | ||
ff72145b DA |
1996 | /** |
1997 | * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing | |
1998 | * @dev: DRM device | |
1999 | * @data: GTT mapping ioctl data | |
2000 | * @file: GEM object info | |
2001 | * | |
2002 | * Simply returns the fake offset to userspace so it can mmap it. | |
2003 | * The mmap call will end up in drm_gem_mmap(), which will set things | |
2004 | * up so we can get faults in the handler above. | |
2005 | * | |
2006 | * The fault handler will take care of binding the object into the GTT | |
2007 | * (since it may have been evicted to make room for something), allocating | |
2008 | * a fence register, and mapping the appropriate aperture address into | |
2009 | * userspace. | |
2010 | */ | |
2011 | int | |
2012 | i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data, | |
2013 | struct drm_file *file) | |
2014 | { | |
2015 | struct drm_i915_gem_mmap_gtt *args = data; | |
2016 | ||
da6b51d0 | 2017 | return i915_gem_mmap_gtt(file, dev, args->handle, &args->offset); |
ff72145b DA |
2018 | } |
2019 | ||
225067ee DV |
2020 | /* Immediately discard the backing storage */ |
2021 | static void | |
2022 | i915_gem_object_truncate(struct drm_i915_gem_object *obj) | |
e5281ccd | 2023 | { |
4d6294bf | 2024 | i915_gem_object_free_mmap_offset(obj); |
1286ff73 | 2025 | |
4d6294bf CW |
2026 | if (obj->base.filp == NULL) |
2027 | return; | |
e5281ccd | 2028 | |
225067ee DV |
2029 | /* Our goal here is to return as much of the memory as |
2030 | * is possible back to the system as we are called from OOM. | |
2031 | * To do this we must instruct the shmfs to drop all of its | |
2032 | * backing pages, *now*. | |
2033 | */ | |
5537252b | 2034 | shmem_truncate_range(file_inode(obj->base.filp), 0, (loff_t)-1); |
225067ee DV |
2035 | obj->madv = __I915_MADV_PURGED; |
2036 | } | |
e5281ccd | 2037 | |
5537252b CW |
2038 | /* Try to discard unwanted pages */ |
2039 | static void | |
2040 | i915_gem_object_invalidate(struct drm_i915_gem_object *obj) | |
225067ee | 2041 | { |
5537252b CW |
2042 | struct address_space *mapping; |
2043 | ||
2044 | switch (obj->madv) { | |
2045 | case I915_MADV_DONTNEED: | |
2046 | i915_gem_object_truncate(obj); | |
2047 | case __I915_MADV_PURGED: | |
2048 | return; | |
2049 | } | |
2050 | ||
2051 | if (obj->base.filp == NULL) | |
2052 | return; | |
2053 | ||
2054 | mapping = file_inode(obj->base.filp)->i_mapping, | |
2055 | invalidate_mapping_pages(mapping, 0, (loff_t)-1); | |
e5281ccd CW |
2056 | } |
2057 | ||
5cdf5881 | 2058 | static void |
05394f39 | 2059 | i915_gem_object_put_pages_gtt(struct drm_i915_gem_object *obj) |
673a394b | 2060 | { |
85d1225e DG |
2061 | struct sgt_iter sgt_iter; |
2062 | struct page *page; | |
90797e6d | 2063 | int ret; |
1286ff73 | 2064 | |
05394f39 | 2065 | BUG_ON(obj->madv == __I915_MADV_PURGED); |
673a394b | 2066 | |
6c085a72 | 2067 | ret = i915_gem_object_set_to_cpu_domain(obj, true); |
f4457ae7 | 2068 | if (WARN_ON(ret)) { |
6c085a72 CW |
2069 | /* In the event of a disaster, abandon all caches and |
2070 | * hope for the best. | |
2071 | */ | |
2c22569b | 2072 | i915_gem_clflush_object(obj, true); |
6c085a72 CW |
2073 | obj->base.read_domains = obj->base.write_domain = I915_GEM_DOMAIN_CPU; |
2074 | } | |
2075 | ||
e2273302 ID |
2076 | i915_gem_gtt_finish_object(obj); |
2077 | ||
6dacfd2f | 2078 | if (i915_gem_object_needs_bit17_swizzle(obj)) |
280b713b EA |
2079 | i915_gem_object_save_bit_17_swizzle(obj); |
2080 | ||
05394f39 CW |
2081 | if (obj->madv == I915_MADV_DONTNEED) |
2082 | obj->dirty = 0; | |
3ef94daa | 2083 | |
85d1225e | 2084 | for_each_sgt_page(page, sgt_iter, obj->pages) { |
05394f39 | 2085 | if (obj->dirty) |
9da3da66 | 2086 | set_page_dirty(page); |
3ef94daa | 2087 | |
05394f39 | 2088 | if (obj->madv == I915_MADV_WILLNEED) |
9da3da66 | 2089 | mark_page_accessed(page); |
3ef94daa | 2090 | |
09cbfeaf | 2091 | put_page(page); |
3ef94daa | 2092 | } |
05394f39 | 2093 | obj->dirty = 0; |
673a394b | 2094 | |
9da3da66 CW |
2095 | sg_free_table(obj->pages); |
2096 | kfree(obj->pages); | |
37e680a1 | 2097 | } |
6c085a72 | 2098 | |
dd624afd | 2099 | int |
37e680a1 CW |
2100 | i915_gem_object_put_pages(struct drm_i915_gem_object *obj) |
2101 | { | |
2102 | const struct drm_i915_gem_object_ops *ops = obj->ops; | |
2103 | ||
2f745ad3 | 2104 | if (obj->pages == NULL) |
37e680a1 CW |
2105 | return 0; |
2106 | ||
a5570178 CW |
2107 | if (obj->pages_pin_count) |
2108 | return -EBUSY; | |
2109 | ||
9843877d | 2110 | BUG_ON(i915_gem_obj_bound_any(obj)); |
3e123027 | 2111 | |
a2165e31 CW |
2112 | /* ->put_pages might need to allocate memory for the bit17 swizzle |
2113 | * array, hence protect them from being reaped by removing them from gtt | |
2114 | * lists early. */ | |
35c20a60 | 2115 | list_del(&obj->global_list); |
a2165e31 | 2116 | |
0a798eb9 | 2117 | if (obj->mapping) { |
fb8621d3 CW |
2118 | if (is_vmalloc_addr(obj->mapping)) |
2119 | vunmap(obj->mapping); | |
2120 | else | |
2121 | kunmap(kmap_to_page(obj->mapping)); | |
0a798eb9 CW |
2122 | obj->mapping = NULL; |
2123 | } | |
2124 | ||
37e680a1 | 2125 | ops->put_pages(obj); |
05394f39 | 2126 | obj->pages = NULL; |
37e680a1 | 2127 | |
5537252b | 2128 | i915_gem_object_invalidate(obj); |
6c085a72 CW |
2129 | |
2130 | return 0; | |
2131 | } | |
2132 | ||
37e680a1 | 2133 | static int |
6c085a72 | 2134 | i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj) |
e5281ccd | 2135 | { |
fac5e23e | 2136 | struct drm_i915_private *dev_priv = to_i915(obj->base.dev); |
e5281ccd CW |
2137 | int page_count, i; |
2138 | struct address_space *mapping; | |
9da3da66 CW |
2139 | struct sg_table *st; |
2140 | struct scatterlist *sg; | |
85d1225e | 2141 | struct sgt_iter sgt_iter; |
e5281ccd | 2142 | struct page *page; |
90797e6d | 2143 | unsigned long last_pfn = 0; /* suppress gcc warning */ |
e2273302 | 2144 | int ret; |
6c085a72 | 2145 | gfp_t gfp; |
e5281ccd | 2146 | |
6c085a72 CW |
2147 | /* Assert that the object is not currently in any GPU domain. As it |
2148 | * wasn't in the GTT, there shouldn't be any way it could have been in | |
2149 | * a GPU cache | |
2150 | */ | |
2151 | BUG_ON(obj->base.read_domains & I915_GEM_GPU_DOMAINS); | |
2152 | BUG_ON(obj->base.write_domain & I915_GEM_GPU_DOMAINS); | |
2153 | ||
9da3da66 CW |
2154 | st = kmalloc(sizeof(*st), GFP_KERNEL); |
2155 | if (st == NULL) | |
2156 | return -ENOMEM; | |
2157 | ||
05394f39 | 2158 | page_count = obj->base.size / PAGE_SIZE; |
9da3da66 | 2159 | if (sg_alloc_table(st, page_count, GFP_KERNEL)) { |
9da3da66 | 2160 | kfree(st); |
e5281ccd | 2161 | return -ENOMEM; |
9da3da66 | 2162 | } |
e5281ccd | 2163 | |
9da3da66 CW |
2164 | /* Get the list of pages out of our struct file. They'll be pinned |
2165 | * at this point until we release them. | |
2166 | * | |
2167 | * Fail silently without starting the shrinker | |
2168 | */ | |
496ad9aa | 2169 | mapping = file_inode(obj->base.filp)->i_mapping; |
c62d2555 | 2170 | gfp = mapping_gfp_constraint(mapping, ~(__GFP_IO | __GFP_RECLAIM)); |
d0164adc | 2171 | gfp |= __GFP_NORETRY | __GFP_NOWARN; |
90797e6d ID |
2172 | sg = st->sgl; |
2173 | st->nents = 0; | |
2174 | for (i = 0; i < page_count; i++) { | |
6c085a72 CW |
2175 | page = shmem_read_mapping_page_gfp(mapping, i, gfp); |
2176 | if (IS_ERR(page)) { | |
21ab4e74 CW |
2177 | i915_gem_shrink(dev_priv, |
2178 | page_count, | |
2179 | I915_SHRINK_BOUND | | |
2180 | I915_SHRINK_UNBOUND | | |
2181 | I915_SHRINK_PURGEABLE); | |
6c085a72 CW |
2182 | page = shmem_read_mapping_page_gfp(mapping, i, gfp); |
2183 | } | |
2184 | if (IS_ERR(page)) { | |
2185 | /* We've tried hard to allocate the memory by reaping | |
2186 | * our own buffer, now let the real VM do its job and | |
2187 | * go down in flames if truly OOM. | |
2188 | */ | |
6c085a72 | 2189 | i915_gem_shrink_all(dev_priv); |
f461d1be | 2190 | page = shmem_read_mapping_page(mapping, i); |
e2273302 ID |
2191 | if (IS_ERR(page)) { |
2192 | ret = PTR_ERR(page); | |
6c085a72 | 2193 | goto err_pages; |
e2273302 | 2194 | } |
6c085a72 | 2195 | } |
426729dc KRW |
2196 | #ifdef CONFIG_SWIOTLB |
2197 | if (swiotlb_nr_tbl()) { | |
2198 | st->nents++; | |
2199 | sg_set_page(sg, page, PAGE_SIZE, 0); | |
2200 | sg = sg_next(sg); | |
2201 | continue; | |
2202 | } | |
2203 | #endif | |
90797e6d ID |
2204 | if (!i || page_to_pfn(page) != last_pfn + 1) { |
2205 | if (i) | |
2206 | sg = sg_next(sg); | |
2207 | st->nents++; | |
2208 | sg_set_page(sg, page, PAGE_SIZE, 0); | |
2209 | } else { | |
2210 | sg->length += PAGE_SIZE; | |
2211 | } | |
2212 | last_pfn = page_to_pfn(page); | |
3bbbe706 DV |
2213 | |
2214 | /* Check that the i965g/gm workaround works. */ | |
2215 | WARN_ON((gfp & __GFP_DMA32) && (last_pfn >= 0x00100000UL)); | |
e5281ccd | 2216 | } |
426729dc KRW |
2217 | #ifdef CONFIG_SWIOTLB |
2218 | if (!swiotlb_nr_tbl()) | |
2219 | #endif | |
2220 | sg_mark_end(sg); | |
74ce6b6c CW |
2221 | obj->pages = st; |
2222 | ||
e2273302 ID |
2223 | ret = i915_gem_gtt_prepare_object(obj); |
2224 | if (ret) | |
2225 | goto err_pages; | |
2226 | ||
6dacfd2f | 2227 | if (i915_gem_object_needs_bit17_swizzle(obj)) |
e5281ccd CW |
2228 | i915_gem_object_do_bit_17_swizzle(obj); |
2229 | ||
656bfa3a DV |
2230 | if (obj->tiling_mode != I915_TILING_NONE && |
2231 | dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES) | |
2232 | i915_gem_object_pin_pages(obj); | |
2233 | ||
e5281ccd CW |
2234 | return 0; |
2235 | ||
2236 | err_pages: | |
90797e6d | 2237 | sg_mark_end(sg); |
85d1225e DG |
2238 | for_each_sgt_page(page, sgt_iter, st) |
2239 | put_page(page); | |
9da3da66 CW |
2240 | sg_free_table(st); |
2241 | kfree(st); | |
0820baf3 CW |
2242 | |
2243 | /* shmemfs first checks if there is enough memory to allocate the page | |
2244 | * and reports ENOSPC should there be insufficient, along with the usual | |
2245 | * ENOMEM for a genuine allocation failure. | |
2246 | * | |
2247 | * We use ENOSPC in our driver to mean that we have run out of aperture | |
2248 | * space and so want to translate the error from shmemfs back to our | |
2249 | * usual understanding of ENOMEM. | |
2250 | */ | |
e2273302 ID |
2251 | if (ret == -ENOSPC) |
2252 | ret = -ENOMEM; | |
2253 | ||
2254 | return ret; | |
673a394b EA |
2255 | } |
2256 | ||
37e680a1 CW |
2257 | /* Ensure that the associated pages are gathered from the backing storage |
2258 | * and pinned into our object. i915_gem_object_get_pages() may be called | |
2259 | * multiple times before they are released by a single call to | |
2260 | * i915_gem_object_put_pages() - once the pages are no longer referenced | |
2261 | * either as a result of memory pressure (reaping pages under the shrinker) | |
2262 | * or as the object is itself released. | |
2263 | */ | |
2264 | int | |
2265 | i915_gem_object_get_pages(struct drm_i915_gem_object *obj) | |
2266 | { | |
fac5e23e | 2267 | struct drm_i915_private *dev_priv = to_i915(obj->base.dev); |
37e680a1 CW |
2268 | const struct drm_i915_gem_object_ops *ops = obj->ops; |
2269 | int ret; | |
2270 | ||
2f745ad3 | 2271 | if (obj->pages) |
37e680a1 CW |
2272 | return 0; |
2273 | ||
43e28f09 | 2274 | if (obj->madv != I915_MADV_WILLNEED) { |
bd9b6a4e | 2275 | DRM_DEBUG("Attempting to obtain a purgeable object\n"); |
8c99e57d | 2276 | return -EFAULT; |
43e28f09 CW |
2277 | } |
2278 | ||
a5570178 CW |
2279 | BUG_ON(obj->pages_pin_count); |
2280 | ||
37e680a1 CW |
2281 | ret = ops->get_pages(obj); |
2282 | if (ret) | |
2283 | return ret; | |
2284 | ||
35c20a60 | 2285 | list_add_tail(&obj->global_list, &dev_priv->mm.unbound_list); |
ee286370 CW |
2286 | |
2287 | obj->get_page.sg = obj->pages->sgl; | |
2288 | obj->get_page.last = 0; | |
2289 | ||
37e680a1 | 2290 | return 0; |
673a394b EA |
2291 | } |
2292 | ||
dd6034c6 DG |
2293 | /* The 'mapping' part of i915_gem_object_pin_map() below */ |
2294 | static void *i915_gem_object_map(const struct drm_i915_gem_object *obj) | |
2295 | { | |
2296 | unsigned long n_pages = obj->base.size >> PAGE_SHIFT; | |
2297 | struct sg_table *sgt = obj->pages; | |
85d1225e DG |
2298 | struct sgt_iter sgt_iter; |
2299 | struct page *page; | |
b338fa47 DG |
2300 | struct page *stack_pages[32]; |
2301 | struct page **pages = stack_pages; | |
dd6034c6 DG |
2302 | unsigned long i = 0; |
2303 | void *addr; | |
2304 | ||
2305 | /* A single page can always be kmapped */ | |
2306 | if (n_pages == 1) | |
2307 | return kmap(sg_page(sgt->sgl)); | |
2308 | ||
b338fa47 DG |
2309 | if (n_pages > ARRAY_SIZE(stack_pages)) { |
2310 | /* Too big for stack -- allocate temporary array instead */ | |
2311 | pages = drm_malloc_gfp(n_pages, sizeof(*pages), GFP_TEMPORARY); | |
2312 | if (!pages) | |
2313 | return NULL; | |
2314 | } | |
dd6034c6 | 2315 | |
85d1225e DG |
2316 | for_each_sgt_page(page, sgt_iter, sgt) |
2317 | pages[i++] = page; | |
dd6034c6 DG |
2318 | |
2319 | /* Check that we have the expected number of pages */ | |
2320 | GEM_BUG_ON(i != n_pages); | |
2321 | ||
2322 | addr = vmap(pages, n_pages, 0, PAGE_KERNEL); | |
2323 | ||
b338fa47 DG |
2324 | if (pages != stack_pages) |
2325 | drm_free_large(pages); | |
dd6034c6 DG |
2326 | |
2327 | return addr; | |
2328 | } | |
2329 | ||
2330 | /* get, pin, and map the pages of the object into kernel space */ | |
0a798eb9 CW |
2331 | void *i915_gem_object_pin_map(struct drm_i915_gem_object *obj) |
2332 | { | |
2333 | int ret; | |
2334 | ||
2335 | lockdep_assert_held(&obj->base.dev->struct_mutex); | |
2336 | ||
2337 | ret = i915_gem_object_get_pages(obj); | |
2338 | if (ret) | |
2339 | return ERR_PTR(ret); | |
2340 | ||
2341 | i915_gem_object_pin_pages(obj); | |
2342 | ||
dd6034c6 DG |
2343 | if (!obj->mapping) { |
2344 | obj->mapping = i915_gem_object_map(obj); | |
2345 | if (!obj->mapping) { | |
0a798eb9 CW |
2346 | i915_gem_object_unpin_pages(obj); |
2347 | return ERR_PTR(-ENOMEM); | |
2348 | } | |
2349 | } | |
2350 | ||
2351 | return obj->mapping; | |
2352 | } | |
2353 | ||
b4716185 | 2354 | void i915_vma_move_to_active(struct i915_vma *vma, |
b2af0376 | 2355 | struct drm_i915_gem_request *req) |
673a394b | 2356 | { |
b4716185 | 2357 | struct drm_i915_gem_object *obj = vma->obj; |
e2f80391 | 2358 | struct intel_engine_cs *engine; |
b2af0376 | 2359 | |
666796da | 2360 | engine = i915_gem_request_get_engine(req); |
673a394b EA |
2361 | |
2362 | /* Add a reference if we're newly entering the active list. */ | |
b4716185 | 2363 | if (obj->active == 0) |
25dc556a | 2364 | i915_gem_object_get(obj); |
666796da | 2365 | obj->active |= intel_engine_flag(engine); |
e35a41de | 2366 | |
117897f4 | 2367 | list_move_tail(&obj->engine_list[engine->id], &engine->active_list); |
e2f80391 | 2368 | i915_gem_request_assign(&obj->last_read_req[engine->id], req); |
caea7476 | 2369 | |
1c7f4bca | 2370 | list_move_tail(&vma->vm_link, &vma->vm->active_list); |
caea7476 CW |
2371 | } |
2372 | ||
b4716185 CW |
2373 | static void |
2374 | i915_gem_object_retire__write(struct drm_i915_gem_object *obj) | |
e2d05a8b | 2375 | { |
d501b1d2 CW |
2376 | GEM_BUG_ON(obj->last_write_req == NULL); |
2377 | GEM_BUG_ON(!(obj->active & intel_engine_flag(obj->last_write_req->engine))); | |
b4716185 CW |
2378 | |
2379 | i915_gem_request_assign(&obj->last_write_req, NULL); | |
de152b62 | 2380 | intel_fb_obj_flush(obj, true, ORIGIN_CS); |
e2d05a8b BW |
2381 | } |
2382 | ||
caea7476 | 2383 | static void |
7e21d648 | 2384 | i915_gem_object_retire__read(struct drm_i915_gem_object *obj, int idx) |
ce44b0ea | 2385 | { |
feb822cf | 2386 | struct i915_vma *vma; |
ce44b0ea | 2387 | |
7e21d648 CW |
2388 | GEM_BUG_ON(obj->last_read_req[idx] == NULL); |
2389 | GEM_BUG_ON(!(obj->active & (1 << idx))); | |
b4716185 | 2390 | |
7e21d648 CW |
2391 | list_del_init(&obj->engine_list[idx]); |
2392 | i915_gem_request_assign(&obj->last_read_req[idx], NULL); | |
b4716185 | 2393 | |
7e21d648 | 2394 | if (obj->last_write_req && obj->last_write_req->engine->id == idx) |
b4716185 CW |
2395 | i915_gem_object_retire__write(obj); |
2396 | ||
7e21d648 | 2397 | obj->active &= ~(1 << idx); |
b4716185 CW |
2398 | if (obj->active) |
2399 | return; | |
caea7476 | 2400 | |
6c246959 CW |
2401 | /* Bump our place on the bound list to keep it roughly in LRU order |
2402 | * so that we don't steal from recently used but inactive objects | |
2403 | * (unless we are forced to ofc!) | |
2404 | */ | |
2405 | list_move_tail(&obj->global_list, | |
2406 | &to_i915(obj->base.dev)->mm.bound_list); | |
2407 | ||
1c7f4bca CW |
2408 | list_for_each_entry(vma, &obj->vma_list, obj_link) { |
2409 | if (!list_empty(&vma->vm_link)) | |
2410 | list_move_tail(&vma->vm_link, &vma->vm->inactive_list); | |
feb822cf | 2411 | } |
caea7476 | 2412 | |
97b2a6a1 | 2413 | i915_gem_request_assign(&obj->last_fenced_req, NULL); |
f8c417cd | 2414 | i915_gem_object_put(obj); |
c8725f3d CW |
2415 | } |
2416 | ||
7b4d3a16 | 2417 | static bool i915_context_is_banned(const struct i915_gem_context *ctx) |
be62acb4 | 2418 | { |
44e2c070 | 2419 | unsigned long elapsed; |
be62acb4 | 2420 | |
44e2c070 | 2421 | if (ctx->hang_stats.banned) |
be62acb4 MK |
2422 | return true; |
2423 | ||
7b4d3a16 | 2424 | elapsed = get_seconds() - ctx->hang_stats.guilty_ts; |
676fa572 CW |
2425 | if (ctx->hang_stats.ban_period_seconds && |
2426 | elapsed <= ctx->hang_stats.ban_period_seconds) { | |
7b4d3a16 CW |
2427 | DRM_DEBUG("context hanging too fast, banning!\n"); |
2428 | return true; | |
be62acb4 MK |
2429 | } |
2430 | ||
2431 | return false; | |
2432 | } | |
2433 | ||
7b4d3a16 | 2434 | static void i915_set_reset_status(struct i915_gem_context *ctx, |
b6b0fac0 | 2435 | const bool guilty) |
aa60c664 | 2436 | { |
7b4d3a16 | 2437 | struct i915_ctx_hang_stats *hs = &ctx->hang_stats; |
44e2c070 MK |
2438 | |
2439 | if (guilty) { | |
7b4d3a16 | 2440 | hs->banned = i915_context_is_banned(ctx); |
44e2c070 MK |
2441 | hs->batch_active++; |
2442 | hs->guilty_ts = get_seconds(); | |
2443 | } else { | |
2444 | hs->batch_pending++; | |
aa60c664 MK |
2445 | } |
2446 | } | |
2447 | ||
8d9fc7fd | 2448 | struct drm_i915_gem_request * |
0bc40be8 | 2449 | i915_gem_find_active_request(struct intel_engine_cs *engine) |
9375e446 | 2450 | { |
4db080f9 CW |
2451 | struct drm_i915_gem_request *request; |
2452 | ||
f69a02c9 CW |
2453 | /* We are called by the error capture and reset at a random |
2454 | * point in time. In particular, note that neither is crucially | |
2455 | * ordered with an interrupt. After a hang, the GPU is dead and we | |
2456 | * assume that no more writes can happen (we waited long enough for | |
2457 | * all writes that were in transaction to be flushed) - adding an | |
2458 | * extra delay for a recent interrupt is pointless. Hence, we do | |
2459 | * not need an engine->irq_seqno_barrier() before the seqno reads. | |
2460 | */ | |
0bc40be8 | 2461 | list_for_each_entry(request, &engine->request_list, list) { |
f69a02c9 | 2462 | if (i915_gem_request_completed(request)) |
4db080f9 | 2463 | continue; |
aa60c664 | 2464 | |
b6b0fac0 | 2465 | return request; |
4db080f9 | 2466 | } |
b6b0fac0 MK |
2467 | |
2468 | return NULL; | |
2469 | } | |
2470 | ||
7b4d3a16 | 2471 | static void i915_gem_reset_engine_status(struct intel_engine_cs *engine) |
b6b0fac0 MK |
2472 | { |
2473 | struct drm_i915_gem_request *request; | |
2474 | bool ring_hung; | |
2475 | ||
0bc40be8 | 2476 | request = i915_gem_find_active_request(engine); |
b6b0fac0 MK |
2477 | if (request == NULL) |
2478 | return; | |
2479 | ||
0bc40be8 | 2480 | ring_hung = engine->hangcheck.score >= HANGCHECK_SCORE_RING_HUNG; |
b6b0fac0 | 2481 | |
7b4d3a16 | 2482 | i915_set_reset_status(request->ctx, ring_hung); |
0bc40be8 | 2483 | list_for_each_entry_continue(request, &engine->request_list, list) |
7b4d3a16 | 2484 | i915_set_reset_status(request->ctx, false); |
4db080f9 | 2485 | } |
aa60c664 | 2486 | |
7b4d3a16 | 2487 | static void i915_gem_reset_engine_cleanup(struct intel_engine_cs *engine) |
4db080f9 | 2488 | { |
7e37f889 | 2489 | struct intel_ring *ring; |
608c1a52 | 2490 | |
0bc40be8 | 2491 | while (!list_empty(&engine->active_list)) { |
05394f39 | 2492 | struct drm_i915_gem_object *obj; |
9375e446 | 2493 | |
0bc40be8 | 2494 | obj = list_first_entry(&engine->active_list, |
05394f39 | 2495 | struct drm_i915_gem_object, |
117897f4 | 2496 | engine_list[engine->id]); |
9375e446 | 2497 | |
0bc40be8 | 2498 | i915_gem_object_retire__read(obj, engine->id); |
673a394b | 2499 | } |
1d62beea | 2500 | |
c4b0930b CW |
2501 | /* Mark all pending requests as complete so that any concurrent |
2502 | * (lockless) lookup doesn't try and wait upon the request as we | |
2503 | * reset it. | |
2504 | */ | |
7e37f889 | 2505 | intel_engine_init_seqno(engine, engine->last_submitted_seqno); |
c4b0930b | 2506 | |
dcb4c12a OM |
2507 | /* |
2508 | * Clear the execlists queue up before freeing the requests, as those | |
2509 | * are the ones that keep the context and ringbuffer backing objects | |
2510 | * pinned in place. | |
2511 | */ | |
dcb4c12a | 2512 | |
7de1691a | 2513 | if (i915.enable_execlists) { |
27af5eea TU |
2514 | /* Ensure irq handler finishes or is cancelled. */ |
2515 | tasklet_kill(&engine->irq_tasklet); | |
1197b4f2 | 2516 | |
e39d42fa | 2517 | intel_execlists_cancel_requests(engine); |
dcb4c12a OM |
2518 | } |
2519 | ||
1d62beea BW |
2520 | /* |
2521 | * We must free the requests after all the corresponding objects have | |
2522 | * been moved off active lists. Which is the same order as the normal | |
2523 | * retire_requests function does. This is important if object hold | |
2524 | * implicit references on things like e.g. ppgtt address spaces through | |
2525 | * the request. | |
2526 | */ | |
05235c53 | 2527 | if (!list_empty(&engine->request_list)) { |
1d62beea BW |
2528 | struct drm_i915_gem_request *request; |
2529 | ||
05235c53 CW |
2530 | request = list_last_entry(&engine->request_list, |
2531 | struct drm_i915_gem_request, | |
2532 | list); | |
1d62beea | 2533 | |
05235c53 | 2534 | i915_gem_request_retire_upto(request); |
1d62beea | 2535 | } |
608c1a52 CW |
2536 | |
2537 | /* Having flushed all requests from all queues, we know that all | |
2538 | * ringbuffers must now be empty. However, since we do not reclaim | |
2539 | * all space when retiring the request (to prevent HEADs colliding | |
2540 | * with rapid ringbuffer wraparound) the amount of available space | |
2541 | * upon reset is less than when we start. Do one more pass over | |
2542 | * all the ringbuffers to reset last_retired_head. | |
2543 | */ | |
7e37f889 CW |
2544 | list_for_each_entry(ring, &engine->buffers, link) { |
2545 | ring->last_retired_head = ring->tail; | |
2546 | intel_ring_update_space(ring); | |
608c1a52 | 2547 | } |
2ed53a94 | 2548 | |
b913b33c | 2549 | engine->i915->gt.active_engines &= ~intel_engine_flag(engine); |
673a394b EA |
2550 | } |
2551 | ||
069efc1d | 2552 | void i915_gem_reset(struct drm_device *dev) |
673a394b | 2553 | { |
fac5e23e | 2554 | struct drm_i915_private *dev_priv = to_i915(dev); |
e2f80391 | 2555 | struct intel_engine_cs *engine; |
673a394b | 2556 | |
4db080f9 CW |
2557 | /* |
2558 | * Before we free the objects from the requests, we need to inspect | |
2559 | * them for finding the guilty party. As the requests only borrow | |
2560 | * their reference to the objects, the inspection must be done first. | |
2561 | */ | |
b4ac5afc | 2562 | for_each_engine(engine, dev_priv) |
7b4d3a16 | 2563 | i915_gem_reset_engine_status(engine); |
4db080f9 | 2564 | |
b4ac5afc | 2565 | for_each_engine(engine, dev_priv) |
7b4d3a16 | 2566 | i915_gem_reset_engine_cleanup(engine); |
b913b33c | 2567 | mod_delayed_work(dev_priv->wq, &dev_priv->gt.idle_work, 0); |
dfaae392 | 2568 | |
acce9ffa BW |
2569 | i915_gem_context_reset(dev); |
2570 | ||
19b2dbde | 2571 | i915_gem_restore_fences(dev); |
b4716185 CW |
2572 | |
2573 | WARN_ON(i915_verify_lists(dev)); | |
673a394b EA |
2574 | } |
2575 | ||
2576 | /** | |
2577 | * This function clears the request list as sequence numbers are passed. | |
14bb2c11 | 2578 | * @engine: engine to retire requests on |
673a394b | 2579 | */ |
1cf0ba14 | 2580 | void |
0bc40be8 | 2581 | i915_gem_retire_requests_ring(struct intel_engine_cs *engine) |
673a394b | 2582 | { |
0bc40be8 | 2583 | WARN_ON(i915_verify_lists(engine->dev)); |
673a394b | 2584 | |
832a3aad CW |
2585 | /* Retire requests first as we use it above for the early return. |
2586 | * If we retire requests last, we may use a later seqno and so clear | |
2587 | * the requests lists without clearing the active list, leading to | |
2588 | * confusion. | |
e9103038 | 2589 | */ |
0bc40be8 | 2590 | while (!list_empty(&engine->request_list)) { |
673a394b | 2591 | struct drm_i915_gem_request *request; |
673a394b | 2592 | |
0bc40be8 | 2593 | request = list_first_entry(&engine->request_list, |
673a394b EA |
2594 | struct drm_i915_gem_request, |
2595 | list); | |
673a394b | 2596 | |
f69a02c9 | 2597 | if (!i915_gem_request_completed(request)) |
b84d5f0c CW |
2598 | break; |
2599 | ||
05235c53 | 2600 | i915_gem_request_retire_upto(request); |
b84d5f0c | 2601 | } |
673a394b | 2602 | |
832a3aad CW |
2603 | /* Move any buffers on the active list that are no longer referenced |
2604 | * by the ringbuffer to the flushing/inactive lists as appropriate, | |
2605 | * before we free the context associated with the requests. | |
2606 | */ | |
0bc40be8 | 2607 | while (!list_empty(&engine->active_list)) { |
832a3aad CW |
2608 | struct drm_i915_gem_object *obj; |
2609 | ||
0bc40be8 TU |
2610 | obj = list_first_entry(&engine->active_list, |
2611 | struct drm_i915_gem_object, | |
117897f4 | 2612 | engine_list[engine->id]); |
832a3aad | 2613 | |
0bc40be8 | 2614 | if (!list_empty(&obj->last_read_req[engine->id]->list)) |
832a3aad CW |
2615 | break; |
2616 | ||
0bc40be8 | 2617 | i915_gem_object_retire__read(obj, engine->id); |
832a3aad CW |
2618 | } |
2619 | ||
0bc40be8 | 2620 | WARN_ON(i915_verify_lists(engine->dev)); |
673a394b EA |
2621 | } |
2622 | ||
67d97da3 | 2623 | void i915_gem_retire_requests(struct drm_i915_private *dev_priv) |
b09a1fec | 2624 | { |
e2f80391 | 2625 | struct intel_engine_cs *engine; |
67d97da3 | 2626 | |
91c8a326 | 2627 | lockdep_assert_held(&dev_priv->drm.struct_mutex); |
67d97da3 CW |
2628 | |
2629 | if (dev_priv->gt.active_engines == 0) | |
2630 | return; | |
2631 | ||
2632 | GEM_BUG_ON(!dev_priv->gt.awake); | |
b09a1fec | 2633 | |
b4ac5afc | 2634 | for_each_engine(engine, dev_priv) { |
e2f80391 | 2635 | i915_gem_retire_requests_ring(engine); |
67d97da3 CW |
2636 | if (list_empty(&engine->request_list)) |
2637 | dev_priv->gt.active_engines &= ~intel_engine_flag(engine); | |
b29c19b6 CW |
2638 | } |
2639 | ||
67d97da3 | 2640 | if (dev_priv->gt.active_engines == 0) |
1b51bce2 CW |
2641 | queue_delayed_work(dev_priv->wq, |
2642 | &dev_priv->gt.idle_work, | |
2643 | msecs_to_jiffies(100)); | |
b09a1fec CW |
2644 | } |
2645 | ||
75ef9da2 | 2646 | static void |
673a394b EA |
2647 | i915_gem_retire_work_handler(struct work_struct *work) |
2648 | { | |
b29c19b6 | 2649 | struct drm_i915_private *dev_priv = |
67d97da3 | 2650 | container_of(work, typeof(*dev_priv), gt.retire_work.work); |
91c8a326 | 2651 | struct drm_device *dev = &dev_priv->drm; |
673a394b | 2652 | |
891b48cf | 2653 | /* Come back later if the device is busy... */ |
b29c19b6 | 2654 | if (mutex_trylock(&dev->struct_mutex)) { |
67d97da3 | 2655 | i915_gem_retire_requests(dev_priv); |
b29c19b6 | 2656 | mutex_unlock(&dev->struct_mutex); |
673a394b | 2657 | } |
67d97da3 CW |
2658 | |
2659 | /* Keep the retire handler running until we are finally idle. | |
2660 | * We do not need to do this test under locking as in the worst-case | |
2661 | * we queue the retire worker once too often. | |
2662 | */ | |
c9615613 CW |
2663 | if (READ_ONCE(dev_priv->gt.awake)) { |
2664 | i915_queue_hangcheck(dev_priv); | |
67d97da3 CW |
2665 | queue_delayed_work(dev_priv->wq, |
2666 | &dev_priv->gt.retire_work, | |
bcb45086 | 2667 | round_jiffies_up_relative(HZ)); |
c9615613 | 2668 | } |
b29c19b6 | 2669 | } |
0a58705b | 2670 | |
b29c19b6 CW |
2671 | static void |
2672 | i915_gem_idle_work_handler(struct work_struct *work) | |
2673 | { | |
2674 | struct drm_i915_private *dev_priv = | |
67d97da3 | 2675 | container_of(work, typeof(*dev_priv), gt.idle_work.work); |
91c8a326 | 2676 | struct drm_device *dev = &dev_priv->drm; |
b4ac5afc | 2677 | struct intel_engine_cs *engine; |
67d97da3 CW |
2678 | unsigned int stuck_engines; |
2679 | bool rearm_hangcheck; | |
2680 | ||
2681 | if (!READ_ONCE(dev_priv->gt.awake)) | |
2682 | return; | |
2683 | ||
2684 | if (READ_ONCE(dev_priv->gt.active_engines)) | |
2685 | return; | |
2686 | ||
2687 | rearm_hangcheck = | |
2688 | cancel_delayed_work_sync(&dev_priv->gpu_error.hangcheck_work); | |
2689 | ||
2690 | if (!mutex_trylock(&dev->struct_mutex)) { | |
2691 | /* Currently busy, come back later */ | |
2692 | mod_delayed_work(dev_priv->wq, | |
2693 | &dev_priv->gt.idle_work, | |
2694 | msecs_to_jiffies(50)); | |
2695 | goto out_rearm; | |
2696 | } | |
2697 | ||
2698 | if (dev_priv->gt.active_engines) | |
2699 | goto out_unlock; | |
b29c19b6 | 2700 | |
b4ac5afc | 2701 | for_each_engine(engine, dev_priv) |
67d97da3 | 2702 | i915_gem_batch_pool_fini(&engine->batch_pool); |
35c94185 | 2703 | |
67d97da3 CW |
2704 | GEM_BUG_ON(!dev_priv->gt.awake); |
2705 | dev_priv->gt.awake = false; | |
2706 | rearm_hangcheck = false; | |
30ecad77 | 2707 | |
2529d570 CW |
2708 | /* As we have disabled hangcheck, we need to unstick any waiters still |
2709 | * hanging around. However, as we may be racing against the interrupt | |
2710 | * handler or the waiters themselves, we skip enabling the fake-irq. | |
2711 | */ | |
67d97da3 | 2712 | stuck_engines = intel_kick_waiters(dev_priv); |
2529d570 CW |
2713 | if (unlikely(stuck_engines)) |
2714 | DRM_DEBUG_DRIVER("kicked stuck waiters (%x)...missed irq?\n", | |
2715 | stuck_engines); | |
35c94185 | 2716 | |
67d97da3 CW |
2717 | if (INTEL_GEN(dev_priv) >= 6) |
2718 | gen6_rps_idle(dev_priv); | |
2719 | intel_runtime_pm_put(dev_priv); | |
2720 | out_unlock: | |
2721 | mutex_unlock(&dev->struct_mutex); | |
b29c19b6 | 2722 | |
67d97da3 CW |
2723 | out_rearm: |
2724 | if (rearm_hangcheck) { | |
2725 | GEM_BUG_ON(!dev_priv->gt.awake); | |
2726 | i915_queue_hangcheck(dev_priv); | |
35c94185 | 2727 | } |
673a394b EA |
2728 | } |
2729 | ||
30dfebf3 DV |
2730 | /** |
2731 | * Ensures that an object will eventually get non-busy by flushing any required | |
2732 | * write domains, emitting any outstanding lazy request and retiring and | |
2733 | * completed requests. | |
14bb2c11 | 2734 | * @obj: object to flush |
30dfebf3 DV |
2735 | */ |
2736 | static int | |
2737 | i915_gem_object_flush_active(struct drm_i915_gem_object *obj) | |
2738 | { | |
a5ac0f90 | 2739 | int i; |
b4716185 CW |
2740 | |
2741 | if (!obj->active) | |
2742 | return 0; | |
30dfebf3 | 2743 | |
666796da | 2744 | for (i = 0; i < I915_NUM_ENGINES; i++) { |
b4716185 | 2745 | struct drm_i915_gem_request *req; |
41c52415 | 2746 | |
b4716185 CW |
2747 | req = obj->last_read_req[i]; |
2748 | if (req == NULL) | |
2749 | continue; | |
2750 | ||
f69a02c9 | 2751 | if (i915_gem_request_completed(req)) |
b4716185 | 2752 | i915_gem_object_retire__read(obj, i); |
30dfebf3 DV |
2753 | } |
2754 | ||
2755 | return 0; | |
2756 | } | |
2757 | ||
23ba4fd0 BW |
2758 | /** |
2759 | * i915_gem_wait_ioctl - implements DRM_IOCTL_I915_GEM_WAIT | |
14bb2c11 TU |
2760 | * @dev: drm device pointer |
2761 | * @data: ioctl data blob | |
2762 | * @file: drm file pointer | |
23ba4fd0 BW |
2763 | * |
2764 | * Returns 0 if successful, else an error is returned with the remaining time in | |
2765 | * the timeout parameter. | |
2766 | * -ETIME: object is still busy after timeout | |
2767 | * -ERESTARTSYS: signal interrupted the wait | |
2768 | * -ENONENT: object doesn't exist | |
2769 | * Also possible, but rare: | |
2770 | * -EAGAIN: GPU wedged | |
2771 | * -ENOMEM: damn | |
2772 | * -ENODEV: Internal IRQ fail | |
2773 | * -E?: The add request failed | |
2774 | * | |
2775 | * The wait ioctl with a timeout of 0 reimplements the busy ioctl. With any | |
2776 | * non-zero timeout parameter the wait ioctl will wait for the given number of | |
2777 | * nanoseconds on an object becoming unbusy. Since the wait itself does so | |
2778 | * without holding struct_mutex the object may become re-busied before this | |
2779 | * function completes. A similar but shorter * race condition exists in the busy | |
2780 | * ioctl | |
2781 | */ | |
2782 | int | |
2783 | i915_gem_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *file) | |
2784 | { | |
2785 | struct drm_i915_gem_wait *args = data; | |
2786 | struct drm_i915_gem_object *obj; | |
666796da | 2787 | struct drm_i915_gem_request *req[I915_NUM_ENGINES]; |
b4716185 CW |
2788 | int i, n = 0; |
2789 | int ret; | |
23ba4fd0 | 2790 | |
11b5d511 DV |
2791 | if (args->flags != 0) |
2792 | return -EINVAL; | |
2793 | ||
23ba4fd0 BW |
2794 | ret = i915_mutex_lock_interruptible(dev); |
2795 | if (ret) | |
2796 | return ret; | |
2797 | ||
03ac0642 CW |
2798 | obj = i915_gem_object_lookup(file, args->bo_handle); |
2799 | if (!obj) { | |
23ba4fd0 BW |
2800 | mutex_unlock(&dev->struct_mutex); |
2801 | return -ENOENT; | |
2802 | } | |
2803 | ||
30dfebf3 DV |
2804 | /* Need to make sure the object gets inactive eventually. */ |
2805 | ret = i915_gem_object_flush_active(obj); | |
23ba4fd0 BW |
2806 | if (ret) |
2807 | goto out; | |
2808 | ||
b4716185 | 2809 | if (!obj->active) |
97b2a6a1 | 2810 | goto out; |
23ba4fd0 | 2811 | |
23ba4fd0 | 2812 | /* Do this after OLR check to make sure we make forward progress polling |
762e4583 | 2813 | * on this IOCTL with a timeout == 0 (like busy ioctl) |
23ba4fd0 | 2814 | */ |
762e4583 | 2815 | if (args->timeout_ns == 0) { |
23ba4fd0 BW |
2816 | ret = -ETIME; |
2817 | goto out; | |
2818 | } | |
2819 | ||
f8c417cd | 2820 | i915_gem_object_put(obj); |
b4716185 | 2821 | |
666796da | 2822 | for (i = 0; i < I915_NUM_ENGINES; i++) { |
b4716185 CW |
2823 | if (obj->last_read_req[i] == NULL) |
2824 | continue; | |
2825 | ||
e8a261ea | 2826 | req[n++] = i915_gem_request_get(obj->last_read_req[i]); |
b4716185 CW |
2827 | } |
2828 | ||
23ba4fd0 BW |
2829 | mutex_unlock(&dev->struct_mutex); |
2830 | ||
b4716185 CW |
2831 | for (i = 0; i < n; i++) { |
2832 | if (ret == 0) | |
299259a3 | 2833 | ret = __i915_wait_request(req[i], true, |
b4716185 | 2834 | args->timeout_ns > 0 ? &args->timeout_ns : NULL, |
b6aa0873 | 2835 | to_rps_client(file)); |
e8a261ea | 2836 | i915_gem_request_put(req[i]); |
b4716185 | 2837 | } |
ff865885 | 2838 | return ret; |
23ba4fd0 BW |
2839 | |
2840 | out: | |
f8c417cd | 2841 | i915_gem_object_put(obj); |
23ba4fd0 BW |
2842 | mutex_unlock(&dev->struct_mutex); |
2843 | return ret; | |
2844 | } | |
2845 | ||
b4716185 CW |
2846 | static int |
2847 | __i915_gem_object_sync(struct drm_i915_gem_object *obj, | |
2848 | struct intel_engine_cs *to, | |
91af127f JH |
2849 | struct drm_i915_gem_request *from_req, |
2850 | struct drm_i915_gem_request **to_req) | |
b4716185 CW |
2851 | { |
2852 | struct intel_engine_cs *from; | |
2853 | int ret; | |
2854 | ||
666796da | 2855 | from = i915_gem_request_get_engine(from_req); |
b4716185 CW |
2856 | if (to == from) |
2857 | return 0; | |
2858 | ||
f69a02c9 | 2859 | if (i915_gem_request_completed(from_req)) |
b4716185 CW |
2860 | return 0; |
2861 | ||
39df9190 | 2862 | if (!i915.semaphores) { |
a6f766f3 | 2863 | struct drm_i915_private *i915 = to_i915(obj->base.dev); |
91af127f | 2864 | ret = __i915_wait_request(from_req, |
a6f766f3 CW |
2865 | i915->mm.interruptible, |
2866 | NULL, | |
197be2ae | 2867 | NO_WAITBOOST); |
b4716185 CW |
2868 | if (ret) |
2869 | return ret; | |
2870 | ||
91af127f | 2871 | i915_gem_object_retire_request(obj, from_req); |
b4716185 | 2872 | } else { |
7e37f889 | 2873 | int idx = intel_engine_sync_index(from, to); |
91af127f JH |
2874 | u32 seqno = i915_gem_request_get_seqno(from_req); |
2875 | ||
2876 | WARN_ON(!to_req); | |
b4716185 CW |
2877 | |
2878 | if (seqno <= from->semaphore.sync_seqno[idx]) | |
2879 | return 0; | |
2880 | ||
91af127f | 2881 | if (*to_req == NULL) { |
26827088 DG |
2882 | struct drm_i915_gem_request *req; |
2883 | ||
2884 | req = i915_gem_request_alloc(to, NULL); | |
2885 | if (IS_ERR(req)) | |
2886 | return PTR_ERR(req); | |
2887 | ||
2888 | *to_req = req; | |
91af127f JH |
2889 | } |
2890 | ||
599d924c JH |
2891 | trace_i915_gem_ring_sync_to(*to_req, from, from_req); |
2892 | ret = to->semaphore.sync_to(*to_req, from, seqno); | |
b4716185 CW |
2893 | if (ret) |
2894 | return ret; | |
2895 | ||
2896 | /* We use last_read_req because sync_to() | |
2897 | * might have just caused seqno wrap under | |
2898 | * the radar. | |
2899 | */ | |
2900 | from->semaphore.sync_seqno[idx] = | |
2901 | i915_gem_request_get_seqno(obj->last_read_req[from->id]); | |
2902 | } | |
2903 | ||
2904 | return 0; | |
2905 | } | |
2906 | ||
5816d648 BW |
2907 | /** |
2908 | * i915_gem_object_sync - sync an object to a ring. | |
2909 | * | |
2910 | * @obj: object which may be in use on another ring. | |
2911 | * @to: ring we wish to use the object on. May be NULL. | |
91af127f JH |
2912 | * @to_req: request we wish to use the object for. See below. |
2913 | * This will be allocated and returned if a request is | |
2914 | * required but not passed in. | |
5816d648 BW |
2915 | * |
2916 | * This code is meant to abstract object synchronization with the GPU. | |
2917 | * Calling with NULL implies synchronizing the object with the CPU | |
b4716185 | 2918 | * rather than a particular GPU ring. Conceptually we serialise writes |
91af127f | 2919 | * between engines inside the GPU. We only allow one engine to write |
b4716185 CW |
2920 | * into a buffer at any time, but multiple readers. To ensure each has |
2921 | * a coherent view of memory, we must: | |
2922 | * | |
2923 | * - If there is an outstanding write request to the object, the new | |
2924 | * request must wait for it to complete (either CPU or in hw, requests | |
2925 | * on the same ring will be naturally ordered). | |
2926 | * | |
2927 | * - If we are a write request (pending_write_domain is set), the new | |
2928 | * request must wait for outstanding read requests to complete. | |
5816d648 | 2929 | * |
91af127f JH |
2930 | * For CPU synchronisation (NULL to) no request is required. For syncing with |
2931 | * rings to_req must be non-NULL. However, a request does not have to be | |
2932 | * pre-allocated. If *to_req is NULL and sync commands will be emitted then a | |
2933 | * request will be allocated automatically and returned through *to_req. Note | |
2934 | * that it is not guaranteed that commands will be emitted (because the system | |
2935 | * might already be idle). Hence there is no need to create a request that | |
2936 | * might never have any work submitted. Note further that if a request is | |
2937 | * returned in *to_req, it is the responsibility of the caller to submit | |
2938 | * that request (after potentially adding more work to it). | |
2939 | * | |
5816d648 BW |
2940 | * Returns 0 if successful, else propagates up the lower layer error. |
2941 | */ | |
2911a35b BW |
2942 | int |
2943 | i915_gem_object_sync(struct drm_i915_gem_object *obj, | |
91af127f JH |
2944 | struct intel_engine_cs *to, |
2945 | struct drm_i915_gem_request **to_req) | |
2911a35b | 2946 | { |
b4716185 | 2947 | const bool readonly = obj->base.pending_write_domain == 0; |
666796da | 2948 | struct drm_i915_gem_request *req[I915_NUM_ENGINES]; |
b4716185 | 2949 | int ret, i, n; |
41c52415 | 2950 | |
b4716185 | 2951 | if (!obj->active) |
2911a35b BW |
2952 | return 0; |
2953 | ||
b4716185 CW |
2954 | if (to == NULL) |
2955 | return i915_gem_object_wait_rendering(obj, readonly); | |
2911a35b | 2956 | |
b4716185 CW |
2957 | n = 0; |
2958 | if (readonly) { | |
2959 | if (obj->last_write_req) | |
2960 | req[n++] = obj->last_write_req; | |
2961 | } else { | |
666796da | 2962 | for (i = 0; i < I915_NUM_ENGINES; i++) |
b4716185 CW |
2963 | if (obj->last_read_req[i]) |
2964 | req[n++] = obj->last_read_req[i]; | |
2965 | } | |
2966 | for (i = 0; i < n; i++) { | |
91af127f | 2967 | ret = __i915_gem_object_sync(obj, to, req[i], to_req); |
b4716185 CW |
2968 | if (ret) |
2969 | return ret; | |
2970 | } | |
2911a35b | 2971 | |
b4716185 | 2972 | return 0; |
2911a35b BW |
2973 | } |
2974 | ||
b5ffc9bc CW |
2975 | static void i915_gem_object_finish_gtt(struct drm_i915_gem_object *obj) |
2976 | { | |
2977 | u32 old_write_domain, old_read_domains; | |
2978 | ||
b5ffc9bc CW |
2979 | /* Force a pagefault for domain tracking on next user access */ |
2980 | i915_gem_release_mmap(obj); | |
2981 | ||
b97c3d9c KP |
2982 | if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0) |
2983 | return; | |
2984 | ||
b5ffc9bc CW |
2985 | old_read_domains = obj->base.read_domains; |
2986 | old_write_domain = obj->base.write_domain; | |
2987 | ||
2988 | obj->base.read_domains &= ~I915_GEM_DOMAIN_GTT; | |
2989 | obj->base.write_domain &= ~I915_GEM_DOMAIN_GTT; | |
2990 | ||
2991 | trace_i915_gem_object_change_domain(obj, | |
2992 | old_read_domains, | |
2993 | old_write_domain); | |
2994 | } | |
2995 | ||
8ef8561f CW |
2996 | static void __i915_vma_iounmap(struct i915_vma *vma) |
2997 | { | |
2998 | GEM_BUG_ON(vma->pin_count); | |
2999 | ||
3000 | if (vma->iomap == NULL) | |
3001 | return; | |
3002 | ||
3003 | io_mapping_unmap(vma->iomap); | |
3004 | vma->iomap = NULL; | |
3005 | } | |
3006 | ||
e9f24d5f | 3007 | static int __i915_vma_unbind(struct i915_vma *vma, bool wait) |
673a394b | 3008 | { |
07fe0b12 | 3009 | struct drm_i915_gem_object *obj = vma->obj; |
fac5e23e | 3010 | struct drm_i915_private *dev_priv = to_i915(obj->base.dev); |
43e28f09 | 3011 | int ret; |
673a394b | 3012 | |
1c7f4bca | 3013 | if (list_empty(&vma->obj_link)) |
673a394b EA |
3014 | return 0; |
3015 | ||
0ff501cb DV |
3016 | if (!drm_mm_node_allocated(&vma->node)) { |
3017 | i915_gem_vma_destroy(vma); | |
0ff501cb DV |
3018 | return 0; |
3019 | } | |
433544bd | 3020 | |
d7f46fc4 | 3021 | if (vma->pin_count) |
31d8d651 | 3022 | return -EBUSY; |
673a394b | 3023 | |
c4670ad0 CW |
3024 | BUG_ON(obj->pages == NULL); |
3025 | ||
e9f24d5f TU |
3026 | if (wait) { |
3027 | ret = i915_gem_object_wait_rendering(obj, false); | |
3028 | if (ret) | |
3029 | return ret; | |
3030 | } | |
a8198eea | 3031 | |
596c5923 | 3032 | if (vma->is_ggtt && vma->ggtt_view.type == I915_GGTT_VIEW_NORMAL) { |
8b1bc9b4 | 3033 | i915_gem_object_finish_gtt(obj); |
5323fd04 | 3034 | |
8b1bc9b4 DV |
3035 | /* release the fence reg _after_ flushing */ |
3036 | ret = i915_gem_object_put_fence(obj); | |
3037 | if (ret) | |
3038 | return ret; | |
8ef8561f CW |
3039 | |
3040 | __i915_vma_iounmap(vma); | |
8b1bc9b4 | 3041 | } |
96b47b65 | 3042 | |
07fe0b12 | 3043 | trace_i915_vma_unbind(vma); |
db53a302 | 3044 | |
777dc5bb | 3045 | vma->vm->unbind_vma(vma); |
5e562f1d | 3046 | vma->bound = 0; |
6f65e29a | 3047 | |
1c7f4bca | 3048 | list_del_init(&vma->vm_link); |
596c5923 | 3049 | if (vma->is_ggtt) { |
fe14d5f4 TU |
3050 | if (vma->ggtt_view.type == I915_GGTT_VIEW_NORMAL) { |
3051 | obj->map_and_fenceable = false; | |
3052 | } else if (vma->ggtt_view.pages) { | |
3053 | sg_free_table(vma->ggtt_view.pages); | |
3054 | kfree(vma->ggtt_view.pages); | |
fe14d5f4 | 3055 | } |
016a65a3 | 3056 | vma->ggtt_view.pages = NULL; |
fe14d5f4 | 3057 | } |
673a394b | 3058 | |
2f633156 BW |
3059 | drm_mm_remove_node(&vma->node); |
3060 | i915_gem_vma_destroy(vma); | |
3061 | ||
3062 | /* Since the unbound list is global, only move to that list if | |
b93dab6e | 3063 | * no more VMAs exist. */ |
e2273302 | 3064 | if (list_empty(&obj->vma_list)) |
2f633156 | 3065 | list_move_tail(&obj->global_list, &dev_priv->mm.unbound_list); |
673a394b | 3066 | |
70903c3b CW |
3067 | /* And finally now the object is completely decoupled from this vma, |
3068 | * we can drop its hold on the backing storage and allow it to be | |
3069 | * reaped by the shrinker. | |
3070 | */ | |
3071 | i915_gem_object_unpin_pages(obj); | |
3072 | ||
88241785 | 3073 | return 0; |
54cf91dc CW |
3074 | } |
3075 | ||
e9f24d5f TU |
3076 | int i915_vma_unbind(struct i915_vma *vma) |
3077 | { | |
3078 | return __i915_vma_unbind(vma, true); | |
3079 | } | |
3080 | ||
3081 | int __i915_vma_unbind_no_wait(struct i915_vma *vma) | |
3082 | { | |
3083 | return __i915_vma_unbind(vma, false); | |
3084 | } | |
3085 | ||
6e5a5beb | 3086 | int i915_gem_wait_for_idle(struct drm_i915_private *dev_priv) |
4df2faf4 | 3087 | { |
e2f80391 | 3088 | struct intel_engine_cs *engine; |
b4ac5afc | 3089 | int ret; |
4df2faf4 | 3090 | |
91c8a326 | 3091 | lockdep_assert_held(&dev_priv->drm.struct_mutex); |
6e5a5beb | 3092 | |
b4ac5afc | 3093 | for_each_engine(engine, dev_priv) { |
62e63007 CW |
3094 | if (engine->last_context == NULL) |
3095 | continue; | |
3096 | ||
666796da | 3097 | ret = intel_engine_idle(engine); |
1ec14ad3 CW |
3098 | if (ret) |
3099 | return ret; | |
3100 | } | |
4df2faf4 | 3101 | |
b4716185 | 3102 | WARN_ON(i915_verify_lists(dev)); |
8a1a49f9 | 3103 | return 0; |
4df2faf4 DV |
3104 | } |
3105 | ||
4144f9b5 | 3106 | static bool i915_gem_valid_gtt_space(struct i915_vma *vma, |
42d6ab48 CW |
3107 | unsigned long cache_level) |
3108 | { | |
4144f9b5 | 3109 | struct drm_mm_node *gtt_space = &vma->node; |
42d6ab48 CW |
3110 | struct drm_mm_node *other; |
3111 | ||
4144f9b5 CW |
3112 | /* |
3113 | * On some machines we have to be careful when putting differing types | |
3114 | * of snoopable memory together to avoid the prefetcher crossing memory | |
3115 | * domains and dying. During vm initialisation, we decide whether or not | |
3116 | * these constraints apply and set the drm_mm.color_adjust | |
3117 | * appropriately. | |
42d6ab48 | 3118 | */ |
4144f9b5 | 3119 | if (vma->vm->mm.color_adjust == NULL) |
42d6ab48 CW |
3120 | return true; |
3121 | ||
c6cfb325 | 3122 | if (!drm_mm_node_allocated(gtt_space)) |
42d6ab48 CW |
3123 | return true; |
3124 | ||
3125 | if (list_empty(>t_space->node_list)) | |
3126 | return true; | |
3127 | ||
3128 | other = list_entry(gtt_space->node_list.prev, struct drm_mm_node, node_list); | |
3129 | if (other->allocated && !other->hole_follows && other->color != cache_level) | |
3130 | return false; | |
3131 | ||
3132 | other = list_entry(gtt_space->node_list.next, struct drm_mm_node, node_list); | |
3133 | if (other->allocated && !gtt_space->hole_follows && other->color != cache_level) | |
3134 | return false; | |
3135 | ||
3136 | return true; | |
3137 | } | |
3138 | ||
673a394b | 3139 | /** |
91e6711e JL |
3140 | * Finds free space in the GTT aperture and binds the object or a view of it |
3141 | * there. | |
14bb2c11 TU |
3142 | * @obj: object to bind |
3143 | * @vm: address space to bind into | |
3144 | * @ggtt_view: global gtt view if applicable | |
3145 | * @alignment: requested alignment | |
3146 | * @flags: mask of PIN_* flags to use | |
673a394b | 3147 | */ |
262de145 | 3148 | static struct i915_vma * |
07fe0b12 BW |
3149 | i915_gem_object_bind_to_vm(struct drm_i915_gem_object *obj, |
3150 | struct i915_address_space *vm, | |
ec7adb6e | 3151 | const struct i915_ggtt_view *ggtt_view, |
07fe0b12 | 3152 | unsigned alignment, |
ec7adb6e | 3153 | uint64_t flags) |
673a394b | 3154 | { |
05394f39 | 3155 | struct drm_device *dev = obj->base.dev; |
72e96d64 JL |
3156 | struct drm_i915_private *dev_priv = to_i915(dev); |
3157 | struct i915_ggtt *ggtt = &dev_priv->ggtt; | |
65bd342f | 3158 | u32 fence_alignment, unfenced_alignment; |
101b506a MT |
3159 | u32 search_flag, alloc_flag; |
3160 | u64 start, end; | |
65bd342f | 3161 | u64 size, fence_size; |
2f633156 | 3162 | struct i915_vma *vma; |
07f73f69 | 3163 | int ret; |
673a394b | 3164 | |
91e6711e JL |
3165 | if (i915_is_ggtt(vm)) { |
3166 | u32 view_size; | |
3167 | ||
3168 | if (WARN_ON(!ggtt_view)) | |
3169 | return ERR_PTR(-EINVAL); | |
ec7adb6e | 3170 | |
91e6711e JL |
3171 | view_size = i915_ggtt_view_size(obj, ggtt_view); |
3172 | ||
3173 | fence_size = i915_gem_get_gtt_size(dev, | |
3174 | view_size, | |
3175 | obj->tiling_mode); | |
3176 | fence_alignment = i915_gem_get_gtt_alignment(dev, | |
3177 | view_size, | |
3178 | obj->tiling_mode, | |
3179 | true); | |
3180 | unfenced_alignment = i915_gem_get_gtt_alignment(dev, | |
3181 | view_size, | |
3182 | obj->tiling_mode, | |
3183 | false); | |
3184 | size = flags & PIN_MAPPABLE ? fence_size : view_size; | |
3185 | } else { | |
3186 | fence_size = i915_gem_get_gtt_size(dev, | |
3187 | obj->base.size, | |
3188 | obj->tiling_mode); | |
3189 | fence_alignment = i915_gem_get_gtt_alignment(dev, | |
3190 | obj->base.size, | |
3191 | obj->tiling_mode, | |
3192 | true); | |
3193 | unfenced_alignment = | |
3194 | i915_gem_get_gtt_alignment(dev, | |
3195 | obj->base.size, | |
3196 | obj->tiling_mode, | |
3197 | false); | |
3198 | size = flags & PIN_MAPPABLE ? fence_size : obj->base.size; | |
3199 | } | |
a00b10c3 | 3200 | |
101b506a MT |
3201 | start = flags & PIN_OFFSET_BIAS ? flags & PIN_OFFSET_MASK : 0; |
3202 | end = vm->total; | |
3203 | if (flags & PIN_MAPPABLE) | |
72e96d64 | 3204 | end = min_t(u64, end, ggtt->mappable_end); |
101b506a | 3205 | if (flags & PIN_ZONE_4G) |
48ea1e32 | 3206 | end = min_t(u64, end, (1ULL << 32) - PAGE_SIZE); |
101b506a | 3207 | |
673a394b | 3208 | if (alignment == 0) |
1ec9e26d | 3209 | alignment = flags & PIN_MAPPABLE ? fence_alignment : |
5e783301 | 3210 | unfenced_alignment; |
1ec9e26d | 3211 | if (flags & PIN_MAPPABLE && alignment & (fence_alignment - 1)) { |
91e6711e JL |
3212 | DRM_DEBUG("Invalid object (view type=%u) alignment requested %u\n", |
3213 | ggtt_view ? ggtt_view->type : 0, | |
3214 | alignment); | |
262de145 | 3215 | return ERR_PTR(-EINVAL); |
673a394b EA |
3216 | } |
3217 | ||
91e6711e JL |
3218 | /* If binding the object/GGTT view requires more space than the entire |
3219 | * aperture has, reject it early before evicting everything in a vain | |
3220 | * attempt to find space. | |
654fc607 | 3221 | */ |
91e6711e | 3222 | if (size > end) { |
65bd342f | 3223 | DRM_DEBUG("Attempting to bind an object (view type=%u) larger than the aperture: size=%llu > %s aperture=%llu\n", |
91e6711e JL |
3224 | ggtt_view ? ggtt_view->type : 0, |
3225 | size, | |
1ec9e26d | 3226 | flags & PIN_MAPPABLE ? "mappable" : "total", |
d23db88c | 3227 | end); |
262de145 | 3228 | return ERR_PTR(-E2BIG); |
654fc607 CW |
3229 | } |
3230 | ||
37e680a1 | 3231 | ret = i915_gem_object_get_pages(obj); |
6c085a72 | 3232 | if (ret) |
262de145 | 3233 | return ERR_PTR(ret); |
6c085a72 | 3234 | |
fbdda6fb CW |
3235 | i915_gem_object_pin_pages(obj); |
3236 | ||
ec7adb6e JL |
3237 | vma = ggtt_view ? i915_gem_obj_lookup_or_create_ggtt_vma(obj, ggtt_view) : |
3238 | i915_gem_obj_lookup_or_create_vma(obj, vm); | |
3239 | ||
262de145 | 3240 | if (IS_ERR(vma)) |
bc6bc15b | 3241 | goto err_unpin; |
2f633156 | 3242 | |
506a8e87 CW |
3243 | if (flags & PIN_OFFSET_FIXED) { |
3244 | uint64_t offset = flags & PIN_OFFSET_MASK; | |
3245 | ||
3246 | if (offset & (alignment - 1) || offset + size > end) { | |
3247 | ret = -EINVAL; | |
3248 | goto err_free_vma; | |
3249 | } | |
3250 | vma->node.start = offset; | |
3251 | vma->node.size = size; | |
3252 | vma->node.color = obj->cache_level; | |
3253 | ret = drm_mm_reserve_node(&vm->mm, &vma->node); | |
3254 | if (ret) { | |
3255 | ret = i915_gem_evict_for_vma(vma); | |
3256 | if (ret == 0) | |
3257 | ret = drm_mm_reserve_node(&vm->mm, &vma->node); | |
3258 | } | |
3259 | if (ret) | |
3260 | goto err_free_vma; | |
101b506a | 3261 | } else { |
506a8e87 CW |
3262 | if (flags & PIN_HIGH) { |
3263 | search_flag = DRM_MM_SEARCH_BELOW; | |
3264 | alloc_flag = DRM_MM_CREATE_TOP; | |
3265 | } else { | |
3266 | search_flag = DRM_MM_SEARCH_DEFAULT; | |
3267 | alloc_flag = DRM_MM_CREATE_DEFAULT; | |
3268 | } | |
101b506a | 3269 | |
0a9ae0d7 | 3270 | search_free: |
506a8e87 CW |
3271 | ret = drm_mm_insert_node_in_range_generic(&vm->mm, &vma->node, |
3272 | size, alignment, | |
3273 | obj->cache_level, | |
3274 | start, end, | |
3275 | search_flag, | |
3276 | alloc_flag); | |
3277 | if (ret) { | |
3278 | ret = i915_gem_evict_something(dev, vm, size, alignment, | |
3279 | obj->cache_level, | |
3280 | start, end, | |
3281 | flags); | |
3282 | if (ret == 0) | |
3283 | goto search_free; | |
9731129c | 3284 | |
506a8e87 CW |
3285 | goto err_free_vma; |
3286 | } | |
673a394b | 3287 | } |
4144f9b5 | 3288 | if (WARN_ON(!i915_gem_valid_gtt_space(vma, obj->cache_level))) { |
2f633156 | 3289 | ret = -EINVAL; |
bc6bc15b | 3290 | goto err_remove_node; |
673a394b EA |
3291 | } |
3292 | ||
fe14d5f4 | 3293 | trace_i915_vma_bind(vma, flags); |
0875546c | 3294 | ret = i915_vma_bind(vma, obj->cache_level, flags); |
fe14d5f4 | 3295 | if (ret) |
e2273302 | 3296 | goto err_remove_node; |
fe14d5f4 | 3297 | |
35c20a60 | 3298 | list_move_tail(&obj->global_list, &dev_priv->mm.bound_list); |
1c7f4bca | 3299 | list_add_tail(&vma->vm_link, &vm->inactive_list); |
bf1a1092 | 3300 | |
262de145 | 3301 | return vma; |
2f633156 | 3302 | |
bc6bc15b | 3303 | err_remove_node: |
6286ef9b | 3304 | drm_mm_remove_node(&vma->node); |
bc6bc15b | 3305 | err_free_vma: |
2f633156 | 3306 | i915_gem_vma_destroy(vma); |
262de145 | 3307 | vma = ERR_PTR(ret); |
bc6bc15b | 3308 | err_unpin: |
2f633156 | 3309 | i915_gem_object_unpin_pages(obj); |
262de145 | 3310 | return vma; |
673a394b EA |
3311 | } |
3312 | ||
000433b6 | 3313 | bool |
2c22569b CW |
3314 | i915_gem_clflush_object(struct drm_i915_gem_object *obj, |
3315 | bool force) | |
673a394b | 3316 | { |
673a394b EA |
3317 | /* If we don't have a page list set up, then we're not pinned |
3318 | * to GPU, and we can ignore the cache flush because it'll happen | |
3319 | * again at bind time. | |
3320 | */ | |
05394f39 | 3321 | if (obj->pages == NULL) |
000433b6 | 3322 | return false; |
673a394b | 3323 | |
769ce464 ID |
3324 | /* |
3325 | * Stolen memory is always coherent with the GPU as it is explicitly | |
3326 | * marked as wc by the system, or the system is cache-coherent. | |
3327 | */ | |
6a2c4232 | 3328 | if (obj->stolen || obj->phys_handle) |
000433b6 | 3329 | return false; |
769ce464 | 3330 | |
9c23f7fc CW |
3331 | /* If the GPU is snooping the contents of the CPU cache, |
3332 | * we do not need to manually clear the CPU cache lines. However, | |
3333 | * the caches are only snooped when the render cache is | |
3334 | * flushed/invalidated. As we always have to emit invalidations | |
3335 | * and flushes when moving into and out of the RENDER domain, correct | |
3336 | * snooping behaviour occurs naturally as the result of our domain | |
3337 | * tracking. | |
3338 | */ | |
0f71979a CW |
3339 | if (!force && cpu_cache_is_coherent(obj->base.dev, obj->cache_level)) { |
3340 | obj->cache_dirty = true; | |
000433b6 | 3341 | return false; |
0f71979a | 3342 | } |
9c23f7fc | 3343 | |
1c5d22f7 | 3344 | trace_i915_gem_object_clflush(obj); |
9da3da66 | 3345 | drm_clflush_sg(obj->pages); |
0f71979a | 3346 | obj->cache_dirty = false; |
000433b6 CW |
3347 | |
3348 | return true; | |
e47c68e9 EA |
3349 | } |
3350 | ||
3351 | /** Flushes the GTT write domain for the object if it's dirty. */ | |
3352 | static void | |
05394f39 | 3353 | i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj) |
e47c68e9 | 3354 | { |
1c5d22f7 CW |
3355 | uint32_t old_write_domain; |
3356 | ||
05394f39 | 3357 | if (obj->base.write_domain != I915_GEM_DOMAIN_GTT) |
e47c68e9 EA |
3358 | return; |
3359 | ||
63256ec5 | 3360 | /* No actual flushing is required for the GTT write domain. Writes |
e47c68e9 EA |
3361 | * to it immediately go to main memory as far as we know, so there's |
3362 | * no chipset flush. It also doesn't land in render cache. | |
63256ec5 CW |
3363 | * |
3364 | * However, we do have to enforce the order so that all writes through | |
3365 | * the GTT land before any writes to the device, such as updates to | |
3366 | * the GATT itself. | |
e47c68e9 | 3367 | */ |
63256ec5 CW |
3368 | wmb(); |
3369 | ||
05394f39 CW |
3370 | old_write_domain = obj->base.write_domain; |
3371 | obj->base.write_domain = 0; | |
1c5d22f7 | 3372 | |
de152b62 | 3373 | intel_fb_obj_flush(obj, false, ORIGIN_GTT); |
f99d7069 | 3374 | |
1c5d22f7 | 3375 | trace_i915_gem_object_change_domain(obj, |
05394f39 | 3376 | obj->base.read_domains, |
1c5d22f7 | 3377 | old_write_domain); |
e47c68e9 EA |
3378 | } |
3379 | ||
3380 | /** Flushes the CPU write domain for the object if it's dirty. */ | |
3381 | static void | |
e62b59e4 | 3382 | i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj) |
e47c68e9 | 3383 | { |
1c5d22f7 | 3384 | uint32_t old_write_domain; |
e47c68e9 | 3385 | |
05394f39 | 3386 | if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) |
e47c68e9 EA |
3387 | return; |
3388 | ||
e62b59e4 | 3389 | if (i915_gem_clflush_object(obj, obj->pin_display)) |
c033666a | 3390 | i915_gem_chipset_flush(to_i915(obj->base.dev)); |
000433b6 | 3391 | |
05394f39 CW |
3392 | old_write_domain = obj->base.write_domain; |
3393 | obj->base.write_domain = 0; | |
1c5d22f7 | 3394 | |
de152b62 | 3395 | intel_fb_obj_flush(obj, false, ORIGIN_CPU); |
f99d7069 | 3396 | |
1c5d22f7 | 3397 | trace_i915_gem_object_change_domain(obj, |
05394f39 | 3398 | obj->base.read_domains, |
1c5d22f7 | 3399 | old_write_domain); |
e47c68e9 EA |
3400 | } |
3401 | ||
2ef7eeaa EA |
3402 | /** |
3403 | * Moves a single object to the GTT read, and possibly write domain. | |
14bb2c11 TU |
3404 | * @obj: object to act on |
3405 | * @write: ask for write access or read only | |
2ef7eeaa EA |
3406 | * |
3407 | * This function returns when the move is complete, including waiting on | |
3408 | * flushes to occur. | |
3409 | */ | |
79e53945 | 3410 | int |
2021746e | 3411 | i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write) |
2ef7eeaa | 3412 | { |
72e96d64 JL |
3413 | struct drm_device *dev = obj->base.dev; |
3414 | struct drm_i915_private *dev_priv = to_i915(dev); | |
3415 | struct i915_ggtt *ggtt = &dev_priv->ggtt; | |
1c5d22f7 | 3416 | uint32_t old_write_domain, old_read_domains; |
43566ded | 3417 | struct i915_vma *vma; |
e47c68e9 | 3418 | int ret; |
2ef7eeaa | 3419 | |
0201f1ec | 3420 | ret = i915_gem_object_wait_rendering(obj, !write); |
88241785 CW |
3421 | if (ret) |
3422 | return ret; | |
3423 | ||
c13d87ea CW |
3424 | if (obj->base.write_domain == I915_GEM_DOMAIN_GTT) |
3425 | return 0; | |
3426 | ||
43566ded CW |
3427 | /* Flush and acquire obj->pages so that we are coherent through |
3428 | * direct access in memory with previous cached writes through | |
3429 | * shmemfs and that our cache domain tracking remains valid. | |
3430 | * For example, if the obj->filp was moved to swap without us | |
3431 | * being notified and releasing the pages, we would mistakenly | |
3432 | * continue to assume that the obj remained out of the CPU cached | |
3433 | * domain. | |
3434 | */ | |
3435 | ret = i915_gem_object_get_pages(obj); | |
3436 | if (ret) | |
3437 | return ret; | |
3438 | ||
e62b59e4 | 3439 | i915_gem_object_flush_cpu_write_domain(obj); |
1c5d22f7 | 3440 | |
d0a57789 CW |
3441 | /* Serialise direct access to this object with the barriers for |
3442 | * coherent writes from the GPU, by effectively invalidating the | |
3443 | * GTT domain upon first access. | |
3444 | */ | |
3445 | if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0) | |
3446 | mb(); | |
3447 | ||
05394f39 CW |
3448 | old_write_domain = obj->base.write_domain; |
3449 | old_read_domains = obj->base.read_domains; | |
1c5d22f7 | 3450 | |
e47c68e9 EA |
3451 | /* It should now be out of any other write domains, and we can update |
3452 | * the domain values for our changes. | |
3453 | */ | |
05394f39 CW |
3454 | BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) != 0); |
3455 | obj->base.read_domains |= I915_GEM_DOMAIN_GTT; | |
e47c68e9 | 3456 | if (write) { |
05394f39 CW |
3457 | obj->base.read_domains = I915_GEM_DOMAIN_GTT; |
3458 | obj->base.write_domain = I915_GEM_DOMAIN_GTT; | |
3459 | obj->dirty = 1; | |
2ef7eeaa EA |
3460 | } |
3461 | ||
1c5d22f7 CW |
3462 | trace_i915_gem_object_change_domain(obj, |
3463 | old_read_domains, | |
3464 | old_write_domain); | |
3465 | ||
8325a09d | 3466 | /* And bump the LRU for this access */ |
43566ded CW |
3467 | vma = i915_gem_obj_to_ggtt(obj); |
3468 | if (vma && drm_mm_node_allocated(&vma->node) && !obj->active) | |
1c7f4bca | 3469 | list_move_tail(&vma->vm_link, |
72e96d64 | 3470 | &ggtt->base.inactive_list); |
8325a09d | 3471 | |
e47c68e9 EA |
3472 | return 0; |
3473 | } | |
3474 | ||
ef55f92a CW |
3475 | /** |
3476 | * Changes the cache-level of an object across all VMA. | |
14bb2c11 TU |
3477 | * @obj: object to act on |
3478 | * @cache_level: new cache level to set for the object | |
ef55f92a CW |
3479 | * |
3480 | * After this function returns, the object will be in the new cache-level | |
3481 | * across all GTT and the contents of the backing storage will be coherent, | |
3482 | * with respect to the new cache-level. In order to keep the backing storage | |
3483 | * coherent for all users, we only allow a single cache level to be set | |
3484 | * globally on the object and prevent it from being changed whilst the | |
3485 | * hardware is reading from the object. That is if the object is currently | |
3486 | * on the scanout it will be set to uncached (or equivalent display | |
3487 | * cache coherency) and all non-MOCS GPU access will also be uncached so | |
3488 | * that all direct access to the scanout remains coherent. | |
3489 | */ | |
e4ffd173 CW |
3490 | int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj, |
3491 | enum i915_cache_level cache_level) | |
3492 | { | |
7bddb01f | 3493 | struct drm_device *dev = obj->base.dev; |
df6f783a | 3494 | struct i915_vma *vma, *next; |
ef55f92a | 3495 | bool bound = false; |
ed75a55b | 3496 | int ret = 0; |
e4ffd173 CW |
3497 | |
3498 | if (obj->cache_level == cache_level) | |
ed75a55b | 3499 | goto out; |
e4ffd173 | 3500 | |
ef55f92a CW |
3501 | /* Inspect the list of currently bound VMA and unbind any that would |
3502 | * be invalid given the new cache-level. This is principally to | |
3503 | * catch the issue of the CS prefetch crossing page boundaries and | |
3504 | * reading an invalid PTE on older architectures. | |
3505 | */ | |
1c7f4bca | 3506 | list_for_each_entry_safe(vma, next, &obj->vma_list, obj_link) { |
ef55f92a CW |
3507 | if (!drm_mm_node_allocated(&vma->node)) |
3508 | continue; | |
3509 | ||
3510 | if (vma->pin_count) { | |
3511 | DRM_DEBUG("can not change the cache level of pinned objects\n"); | |
3512 | return -EBUSY; | |
3513 | } | |
3514 | ||
4144f9b5 | 3515 | if (!i915_gem_valid_gtt_space(vma, cache_level)) { |
07fe0b12 | 3516 | ret = i915_vma_unbind(vma); |
3089c6f2 BW |
3517 | if (ret) |
3518 | return ret; | |
ef55f92a CW |
3519 | } else |
3520 | bound = true; | |
42d6ab48 CW |
3521 | } |
3522 | ||
ef55f92a CW |
3523 | /* We can reuse the existing drm_mm nodes but need to change the |
3524 | * cache-level on the PTE. We could simply unbind them all and | |
3525 | * rebind with the correct cache-level on next use. However since | |
3526 | * we already have a valid slot, dma mapping, pages etc, we may as | |
3527 | * rewrite the PTE in the belief that doing so tramples upon less | |
3528 | * state and so involves less work. | |
3529 | */ | |
3530 | if (bound) { | |
3531 | /* Before we change the PTE, the GPU must not be accessing it. | |
3532 | * If we wait upon the object, we know that all the bound | |
3533 | * VMA are no longer active. | |
3534 | */ | |
2e2f351d | 3535 | ret = i915_gem_object_wait_rendering(obj, false); |
e4ffd173 CW |
3536 | if (ret) |
3537 | return ret; | |
3538 | ||
ef55f92a CW |
3539 | if (!HAS_LLC(dev) && cache_level != I915_CACHE_NONE) { |
3540 | /* Access to snoopable pages through the GTT is | |
3541 | * incoherent and on some machines causes a hard | |
3542 | * lockup. Relinquish the CPU mmaping to force | |
3543 | * userspace to refault in the pages and we can | |
3544 | * then double check if the GTT mapping is still | |
3545 | * valid for that pointer access. | |
3546 | */ | |
3547 | i915_gem_release_mmap(obj); | |
3548 | ||
3549 | /* As we no longer need a fence for GTT access, | |
3550 | * we can relinquish it now (and so prevent having | |
3551 | * to steal a fence from someone else on the next | |
3552 | * fence request). Note GPU activity would have | |
3553 | * dropped the fence as all snoopable access is | |
3554 | * supposed to be linear. | |
3555 | */ | |
e4ffd173 CW |
3556 | ret = i915_gem_object_put_fence(obj); |
3557 | if (ret) | |
3558 | return ret; | |
ef55f92a CW |
3559 | } else { |
3560 | /* We either have incoherent backing store and | |
3561 | * so no GTT access or the architecture is fully | |
3562 | * coherent. In such cases, existing GTT mmaps | |
3563 | * ignore the cache bit in the PTE and we can | |
3564 | * rewrite it without confusing the GPU or having | |
3565 | * to force userspace to fault back in its mmaps. | |
3566 | */ | |
e4ffd173 CW |
3567 | } |
3568 | ||
1c7f4bca | 3569 | list_for_each_entry(vma, &obj->vma_list, obj_link) { |
ef55f92a CW |
3570 | if (!drm_mm_node_allocated(&vma->node)) |
3571 | continue; | |
3572 | ||
3573 | ret = i915_vma_bind(vma, cache_level, PIN_UPDATE); | |
3574 | if (ret) | |
3575 | return ret; | |
3576 | } | |
e4ffd173 CW |
3577 | } |
3578 | ||
1c7f4bca | 3579 | list_for_each_entry(vma, &obj->vma_list, obj_link) |
2c22569b CW |
3580 | vma->node.color = cache_level; |
3581 | obj->cache_level = cache_level; | |
3582 | ||
ed75a55b | 3583 | out: |
ef55f92a CW |
3584 | /* Flush the dirty CPU caches to the backing storage so that the |
3585 | * object is now coherent at its new cache level (with respect | |
3586 | * to the access domain). | |
3587 | */ | |
b50a5371 | 3588 | if (obj->cache_dirty && cpu_write_needs_clflush(obj)) { |
0f71979a | 3589 | if (i915_gem_clflush_object(obj, true)) |
c033666a | 3590 | i915_gem_chipset_flush(to_i915(obj->base.dev)); |
e4ffd173 CW |
3591 | } |
3592 | ||
e4ffd173 CW |
3593 | return 0; |
3594 | } | |
3595 | ||
199adf40 BW |
3596 | int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data, |
3597 | struct drm_file *file) | |
e6994aee | 3598 | { |
199adf40 | 3599 | struct drm_i915_gem_caching *args = data; |
e6994aee | 3600 | struct drm_i915_gem_object *obj; |
e6994aee | 3601 | |
03ac0642 CW |
3602 | obj = i915_gem_object_lookup(file, args->handle); |
3603 | if (!obj) | |
432be69d | 3604 | return -ENOENT; |
e6994aee | 3605 | |
651d794f CW |
3606 | switch (obj->cache_level) { |
3607 | case I915_CACHE_LLC: | |
3608 | case I915_CACHE_L3_LLC: | |
3609 | args->caching = I915_CACHING_CACHED; | |
3610 | break; | |
3611 | ||
4257d3ba CW |
3612 | case I915_CACHE_WT: |
3613 | args->caching = I915_CACHING_DISPLAY; | |
3614 | break; | |
3615 | ||
651d794f CW |
3616 | default: |
3617 | args->caching = I915_CACHING_NONE; | |
3618 | break; | |
3619 | } | |
e6994aee | 3620 | |
34911fd3 | 3621 | i915_gem_object_put_unlocked(obj); |
432be69d | 3622 | return 0; |
e6994aee CW |
3623 | } |
3624 | ||
199adf40 BW |
3625 | int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data, |
3626 | struct drm_file *file) | |
e6994aee | 3627 | { |
fac5e23e | 3628 | struct drm_i915_private *dev_priv = to_i915(dev); |
199adf40 | 3629 | struct drm_i915_gem_caching *args = data; |
e6994aee CW |
3630 | struct drm_i915_gem_object *obj; |
3631 | enum i915_cache_level level; | |
3632 | int ret; | |
3633 | ||
199adf40 BW |
3634 | switch (args->caching) { |
3635 | case I915_CACHING_NONE: | |
e6994aee CW |
3636 | level = I915_CACHE_NONE; |
3637 | break; | |
199adf40 | 3638 | case I915_CACHING_CACHED: |
e5756c10 ID |
3639 | /* |
3640 | * Due to a HW issue on BXT A stepping, GPU stores via a | |
3641 | * snooped mapping may leave stale data in a corresponding CPU | |
3642 | * cacheline, whereas normally such cachelines would get | |
3643 | * invalidated. | |
3644 | */ | |
ca377809 | 3645 | if (!HAS_LLC(dev) && !HAS_SNOOP(dev)) |
e5756c10 ID |
3646 | return -ENODEV; |
3647 | ||
e6994aee CW |
3648 | level = I915_CACHE_LLC; |
3649 | break; | |
4257d3ba CW |
3650 | case I915_CACHING_DISPLAY: |
3651 | level = HAS_WT(dev) ? I915_CACHE_WT : I915_CACHE_NONE; | |
3652 | break; | |
e6994aee CW |
3653 | default: |
3654 | return -EINVAL; | |
3655 | } | |
3656 | ||
fd0fe6ac ID |
3657 | intel_runtime_pm_get(dev_priv); |
3658 | ||
3bc2913e BW |
3659 | ret = i915_mutex_lock_interruptible(dev); |
3660 | if (ret) | |
fd0fe6ac | 3661 | goto rpm_put; |
3bc2913e | 3662 | |
03ac0642 CW |
3663 | obj = i915_gem_object_lookup(file, args->handle); |
3664 | if (!obj) { | |
e6994aee CW |
3665 | ret = -ENOENT; |
3666 | goto unlock; | |
3667 | } | |
3668 | ||
3669 | ret = i915_gem_object_set_cache_level(obj, level); | |
3670 | ||
f8c417cd | 3671 | i915_gem_object_put(obj); |
e6994aee CW |
3672 | unlock: |
3673 | mutex_unlock(&dev->struct_mutex); | |
fd0fe6ac ID |
3674 | rpm_put: |
3675 | intel_runtime_pm_put(dev_priv); | |
3676 | ||
e6994aee CW |
3677 | return ret; |
3678 | } | |
3679 | ||
b9241ea3 | 3680 | /* |
2da3b9b9 CW |
3681 | * Prepare buffer for display plane (scanout, cursors, etc). |
3682 | * Can be called from an uninterruptible phase (modesetting) and allows | |
3683 | * any flushes to be pipelined (for pageflips). | |
b9241ea3 ZW |
3684 | */ |
3685 | int | |
2da3b9b9 CW |
3686 | i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj, |
3687 | u32 alignment, | |
e6617330 | 3688 | const struct i915_ggtt_view *view) |
b9241ea3 | 3689 | { |
2da3b9b9 | 3690 | u32 old_read_domains, old_write_domain; |
b9241ea3 ZW |
3691 | int ret; |
3692 | ||
cc98b413 CW |
3693 | /* Mark the pin_display early so that we account for the |
3694 | * display coherency whilst setting up the cache domains. | |
3695 | */ | |
8a0c39b1 | 3696 | obj->pin_display++; |
cc98b413 | 3697 | |
a7ef0640 EA |
3698 | /* The display engine is not coherent with the LLC cache on gen6. As |
3699 | * a result, we make sure that the pinning that is about to occur is | |
3700 | * done with uncached PTEs. This is lowest common denominator for all | |
3701 | * chipsets. | |
3702 | * | |
3703 | * However for gen6+, we could do better by using the GFDT bit instead | |
3704 | * of uncaching, which would allow us to flush all the LLC-cached data | |
3705 | * with that bit in the PTE to main memory with just one PIPE_CONTROL. | |
3706 | */ | |
651d794f CW |
3707 | ret = i915_gem_object_set_cache_level(obj, |
3708 | HAS_WT(obj->base.dev) ? I915_CACHE_WT : I915_CACHE_NONE); | |
a7ef0640 | 3709 | if (ret) |
cc98b413 | 3710 | goto err_unpin_display; |
a7ef0640 | 3711 | |
2da3b9b9 CW |
3712 | /* As the user may map the buffer once pinned in the display plane |
3713 | * (e.g. libkms for the bootup splash), we have to ensure that we | |
3714 | * always use map_and_fenceable for all scanout buffers. | |
3715 | */ | |
50470bb0 TU |
3716 | ret = i915_gem_object_ggtt_pin(obj, view, alignment, |
3717 | view->type == I915_GGTT_VIEW_NORMAL ? | |
3718 | PIN_MAPPABLE : 0); | |
2da3b9b9 | 3719 | if (ret) |
cc98b413 | 3720 | goto err_unpin_display; |
2da3b9b9 | 3721 | |
e62b59e4 | 3722 | i915_gem_object_flush_cpu_write_domain(obj); |
b118c1e3 | 3723 | |
2da3b9b9 | 3724 | old_write_domain = obj->base.write_domain; |
05394f39 | 3725 | old_read_domains = obj->base.read_domains; |
2da3b9b9 CW |
3726 | |
3727 | /* It should now be out of any other write domains, and we can update | |
3728 | * the domain values for our changes. | |
3729 | */ | |
e5f1d962 | 3730 | obj->base.write_domain = 0; |
05394f39 | 3731 | obj->base.read_domains |= I915_GEM_DOMAIN_GTT; |
b9241ea3 ZW |
3732 | |
3733 | trace_i915_gem_object_change_domain(obj, | |
3734 | old_read_domains, | |
2da3b9b9 | 3735 | old_write_domain); |
b9241ea3 ZW |
3736 | |
3737 | return 0; | |
cc98b413 CW |
3738 | |
3739 | err_unpin_display: | |
8a0c39b1 | 3740 | obj->pin_display--; |
cc98b413 CW |
3741 | return ret; |
3742 | } | |
3743 | ||
3744 | void | |
e6617330 TU |
3745 | i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object *obj, |
3746 | const struct i915_ggtt_view *view) | |
cc98b413 | 3747 | { |
8a0c39b1 TU |
3748 | if (WARN_ON(obj->pin_display == 0)) |
3749 | return; | |
3750 | ||
e6617330 TU |
3751 | i915_gem_object_ggtt_unpin_view(obj, view); |
3752 | ||
8a0c39b1 | 3753 | obj->pin_display--; |
b9241ea3 ZW |
3754 | } |
3755 | ||
e47c68e9 EA |
3756 | /** |
3757 | * Moves a single object to the CPU read, and possibly write domain. | |
14bb2c11 TU |
3758 | * @obj: object to act on |
3759 | * @write: requesting write or read-only access | |
e47c68e9 EA |
3760 | * |
3761 | * This function returns when the move is complete, including waiting on | |
3762 | * flushes to occur. | |
3763 | */ | |
dabdfe02 | 3764 | int |
919926ae | 3765 | i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write) |
e47c68e9 | 3766 | { |
1c5d22f7 | 3767 | uint32_t old_write_domain, old_read_domains; |
e47c68e9 EA |
3768 | int ret; |
3769 | ||
0201f1ec | 3770 | ret = i915_gem_object_wait_rendering(obj, !write); |
88241785 CW |
3771 | if (ret) |
3772 | return ret; | |
3773 | ||
c13d87ea CW |
3774 | if (obj->base.write_domain == I915_GEM_DOMAIN_CPU) |
3775 | return 0; | |
3776 | ||
e47c68e9 | 3777 | i915_gem_object_flush_gtt_write_domain(obj); |
2ef7eeaa | 3778 | |
05394f39 CW |
3779 | old_write_domain = obj->base.write_domain; |
3780 | old_read_domains = obj->base.read_domains; | |
1c5d22f7 | 3781 | |
e47c68e9 | 3782 | /* Flush the CPU cache if it's still invalid. */ |
05394f39 | 3783 | if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) { |
2c22569b | 3784 | i915_gem_clflush_object(obj, false); |
2ef7eeaa | 3785 | |
05394f39 | 3786 | obj->base.read_domains |= I915_GEM_DOMAIN_CPU; |
2ef7eeaa EA |
3787 | } |
3788 | ||
3789 | /* It should now be out of any other write domains, and we can update | |
3790 | * the domain values for our changes. | |
3791 | */ | |
05394f39 | 3792 | BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) != 0); |
e47c68e9 EA |
3793 | |
3794 | /* If we're writing through the CPU, then the GPU read domains will | |
3795 | * need to be invalidated at next use. | |
3796 | */ | |
3797 | if (write) { | |
05394f39 CW |
3798 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; |
3799 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; | |
e47c68e9 | 3800 | } |
2ef7eeaa | 3801 | |
1c5d22f7 CW |
3802 | trace_i915_gem_object_change_domain(obj, |
3803 | old_read_domains, | |
3804 | old_write_domain); | |
3805 | ||
2ef7eeaa EA |
3806 | return 0; |
3807 | } | |
3808 | ||
673a394b EA |
3809 | /* Throttle our rendering by waiting until the ring has completed our requests |
3810 | * emitted over 20 msec ago. | |
3811 | * | |
b962442e EA |
3812 | * Note that if we were to use the current jiffies each time around the loop, |
3813 | * we wouldn't escape the function with any frames outstanding if the time to | |
3814 | * render a frame was over 20ms. | |
3815 | * | |
673a394b EA |
3816 | * This should get us reasonable parallelism between CPU and GPU but also |
3817 | * relatively low latency when blocking on a particular request to finish. | |
3818 | */ | |
40a5f0de | 3819 | static int |
f787a5f5 | 3820 | i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file) |
40a5f0de | 3821 | { |
fac5e23e | 3822 | struct drm_i915_private *dev_priv = to_i915(dev); |
f787a5f5 | 3823 | struct drm_i915_file_private *file_priv = file->driver_priv; |
d0bc54f2 | 3824 | unsigned long recent_enough = jiffies - DRM_I915_THROTTLE_JIFFIES; |
54fb2411 | 3825 | struct drm_i915_gem_request *request, *target = NULL; |
f787a5f5 | 3826 | int ret; |
93533c29 | 3827 | |
308887aa DV |
3828 | ret = i915_gem_wait_for_error(&dev_priv->gpu_error); |
3829 | if (ret) | |
3830 | return ret; | |
3831 | ||
f4457ae7 CW |
3832 | /* ABI: return -EIO if already wedged */ |
3833 | if (i915_terminally_wedged(&dev_priv->gpu_error)) | |
3834 | return -EIO; | |
e110e8d6 | 3835 | |
1c25595f | 3836 | spin_lock(&file_priv->mm.lock); |
f787a5f5 | 3837 | list_for_each_entry(request, &file_priv->mm.request_list, client_list) { |
b962442e EA |
3838 | if (time_after_eq(request->emitted_jiffies, recent_enough)) |
3839 | break; | |
40a5f0de | 3840 | |
fcfa423c JH |
3841 | /* |
3842 | * Note that the request might not have been submitted yet. | |
3843 | * In which case emitted_jiffies will be zero. | |
3844 | */ | |
3845 | if (!request->emitted_jiffies) | |
3846 | continue; | |
3847 | ||
54fb2411 | 3848 | target = request; |
b962442e | 3849 | } |
ff865885 | 3850 | if (target) |
e8a261ea | 3851 | i915_gem_request_get(target); |
1c25595f | 3852 | spin_unlock(&file_priv->mm.lock); |
40a5f0de | 3853 | |
54fb2411 | 3854 | if (target == NULL) |
f787a5f5 | 3855 | return 0; |
2bc43b5c | 3856 | |
299259a3 | 3857 | ret = __i915_wait_request(target, true, NULL, NULL); |
e8a261ea | 3858 | i915_gem_request_put(target); |
ff865885 | 3859 | |
40a5f0de EA |
3860 | return ret; |
3861 | } | |
3862 | ||
d23db88c CW |
3863 | static bool |
3864 | i915_vma_misplaced(struct i915_vma *vma, uint32_t alignment, uint64_t flags) | |
3865 | { | |
3866 | struct drm_i915_gem_object *obj = vma->obj; | |
3867 | ||
3868 | if (alignment && | |
3869 | vma->node.start & (alignment - 1)) | |
3870 | return true; | |
3871 | ||
3872 | if (flags & PIN_MAPPABLE && !obj->map_and_fenceable) | |
3873 | return true; | |
3874 | ||
3875 | if (flags & PIN_OFFSET_BIAS && | |
3876 | vma->node.start < (flags & PIN_OFFSET_MASK)) | |
3877 | return true; | |
3878 | ||
506a8e87 CW |
3879 | if (flags & PIN_OFFSET_FIXED && |
3880 | vma->node.start != (flags & PIN_OFFSET_MASK)) | |
3881 | return true; | |
3882 | ||
d23db88c CW |
3883 | return false; |
3884 | } | |
3885 | ||
d0710abb CW |
3886 | void __i915_vma_set_map_and_fenceable(struct i915_vma *vma) |
3887 | { | |
3888 | struct drm_i915_gem_object *obj = vma->obj; | |
3889 | bool mappable, fenceable; | |
3890 | u32 fence_size, fence_alignment; | |
3891 | ||
3892 | fence_size = i915_gem_get_gtt_size(obj->base.dev, | |
3893 | obj->base.size, | |
3894 | obj->tiling_mode); | |
3895 | fence_alignment = i915_gem_get_gtt_alignment(obj->base.dev, | |
3896 | obj->base.size, | |
3897 | obj->tiling_mode, | |
3898 | true); | |
3899 | ||
3900 | fenceable = (vma->node.size == fence_size && | |
3901 | (vma->node.start & (fence_alignment - 1)) == 0); | |
3902 | ||
3903 | mappable = (vma->node.start + fence_size <= | |
62106b4f | 3904 | to_i915(obj->base.dev)->ggtt.mappable_end); |
d0710abb CW |
3905 | |
3906 | obj->map_and_fenceable = mappable && fenceable; | |
3907 | } | |
3908 | ||
ec7adb6e JL |
3909 | static int |
3910 | i915_gem_object_do_pin(struct drm_i915_gem_object *obj, | |
3911 | struct i915_address_space *vm, | |
3912 | const struct i915_ggtt_view *ggtt_view, | |
3913 | uint32_t alignment, | |
3914 | uint64_t flags) | |
673a394b | 3915 | { |
fac5e23e | 3916 | struct drm_i915_private *dev_priv = to_i915(obj->base.dev); |
07fe0b12 | 3917 | struct i915_vma *vma; |
ef79e17c | 3918 | unsigned bound; |
673a394b EA |
3919 | int ret; |
3920 | ||
6e7186af BW |
3921 | if (WARN_ON(vm == &dev_priv->mm.aliasing_ppgtt->base)) |
3922 | return -ENODEV; | |
3923 | ||
bf3d149b | 3924 | if (WARN_ON(flags & (PIN_GLOBAL | PIN_MAPPABLE) && !i915_is_ggtt(vm))) |
1ec9e26d | 3925 | return -EINVAL; |
07fe0b12 | 3926 | |
c826c449 CW |
3927 | if (WARN_ON((flags & (PIN_MAPPABLE | PIN_GLOBAL)) == PIN_MAPPABLE)) |
3928 | return -EINVAL; | |
3929 | ||
ec7adb6e JL |
3930 | if (WARN_ON(i915_is_ggtt(vm) != !!ggtt_view)) |
3931 | return -EINVAL; | |
3932 | ||
3933 | vma = ggtt_view ? i915_gem_obj_to_ggtt_view(obj, ggtt_view) : | |
3934 | i915_gem_obj_to_vma(obj, vm); | |
3935 | ||
07fe0b12 | 3936 | if (vma) { |
d7f46fc4 BW |
3937 | if (WARN_ON(vma->pin_count == DRM_I915_GEM_OBJECT_MAX_PIN_COUNT)) |
3938 | return -EBUSY; | |
3939 | ||
d23db88c | 3940 | if (i915_vma_misplaced(vma, alignment, flags)) { |
d7f46fc4 | 3941 | WARN(vma->pin_count, |
ec7adb6e | 3942 | "bo is already pinned in %s with incorrect alignment:" |
088e0df4 | 3943 | " offset=%08x %08x, req.alignment=%x, req.map_and_fenceable=%d," |
75e9e915 | 3944 | " obj->map_and_fenceable=%d\n", |
ec7adb6e | 3945 | ggtt_view ? "ggtt" : "ppgtt", |
088e0df4 MT |
3946 | upper_32_bits(vma->node.start), |
3947 | lower_32_bits(vma->node.start), | |
fe14d5f4 | 3948 | alignment, |
d23db88c | 3949 | !!(flags & PIN_MAPPABLE), |
05394f39 | 3950 | obj->map_and_fenceable); |
07fe0b12 | 3951 | ret = i915_vma_unbind(vma); |
ac0c6b5a CW |
3952 | if (ret) |
3953 | return ret; | |
8ea99c92 DV |
3954 | |
3955 | vma = NULL; | |
ac0c6b5a CW |
3956 | } |
3957 | } | |
3958 | ||
ef79e17c | 3959 | bound = vma ? vma->bound : 0; |
8ea99c92 | 3960 | if (vma == NULL || !drm_mm_node_allocated(&vma->node)) { |
ec7adb6e JL |
3961 | vma = i915_gem_object_bind_to_vm(obj, vm, ggtt_view, alignment, |
3962 | flags); | |
262de145 DV |
3963 | if (IS_ERR(vma)) |
3964 | return PTR_ERR(vma); | |
0875546c DV |
3965 | } else { |
3966 | ret = i915_vma_bind(vma, obj->cache_level, flags); | |
fe14d5f4 TU |
3967 | if (ret) |
3968 | return ret; | |
3969 | } | |
74898d7e | 3970 | |
91e6711e JL |
3971 | if (ggtt_view && ggtt_view->type == I915_GGTT_VIEW_NORMAL && |
3972 | (bound ^ vma->bound) & GLOBAL_BIND) { | |
d0710abb | 3973 | __i915_vma_set_map_and_fenceable(vma); |
91e6711e JL |
3974 | WARN_ON(flags & PIN_MAPPABLE && !obj->map_and_fenceable); |
3975 | } | |
ef79e17c | 3976 | |
8ea99c92 | 3977 | vma->pin_count++; |
673a394b EA |
3978 | return 0; |
3979 | } | |
3980 | ||
ec7adb6e JL |
3981 | int |
3982 | i915_gem_object_pin(struct drm_i915_gem_object *obj, | |
3983 | struct i915_address_space *vm, | |
3984 | uint32_t alignment, | |
3985 | uint64_t flags) | |
3986 | { | |
3987 | return i915_gem_object_do_pin(obj, vm, | |
3988 | i915_is_ggtt(vm) ? &i915_ggtt_view_normal : NULL, | |
3989 | alignment, flags); | |
3990 | } | |
3991 | ||
3992 | int | |
3993 | i915_gem_object_ggtt_pin(struct drm_i915_gem_object *obj, | |
3994 | const struct i915_ggtt_view *view, | |
3995 | uint32_t alignment, | |
3996 | uint64_t flags) | |
3997 | { | |
72e96d64 JL |
3998 | struct drm_device *dev = obj->base.dev; |
3999 | struct drm_i915_private *dev_priv = to_i915(dev); | |
4000 | struct i915_ggtt *ggtt = &dev_priv->ggtt; | |
4001 | ||
ade7daa1 | 4002 | BUG_ON(!view); |
ec7adb6e | 4003 | |
72e96d64 | 4004 | return i915_gem_object_do_pin(obj, &ggtt->base, view, |
6fafab76 | 4005 | alignment, flags | PIN_GLOBAL); |
ec7adb6e JL |
4006 | } |
4007 | ||
673a394b | 4008 | void |
e6617330 TU |
4009 | i915_gem_object_ggtt_unpin_view(struct drm_i915_gem_object *obj, |
4010 | const struct i915_ggtt_view *view) | |
673a394b | 4011 | { |
e6617330 | 4012 | struct i915_vma *vma = i915_gem_obj_to_ggtt_view(obj, view); |
673a394b | 4013 | |
e6617330 | 4014 | WARN_ON(vma->pin_count == 0); |
9abc4648 | 4015 | WARN_ON(!i915_gem_obj_ggtt_bound_view(obj, view)); |
d7f46fc4 | 4016 | |
30154650 | 4017 | --vma->pin_count; |
673a394b EA |
4018 | } |
4019 | ||
673a394b EA |
4020 | int |
4021 | i915_gem_busy_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 4022 | struct drm_file *file) |
673a394b EA |
4023 | { |
4024 | struct drm_i915_gem_busy *args = data; | |
05394f39 | 4025 | struct drm_i915_gem_object *obj; |
30dbf0c0 CW |
4026 | int ret; |
4027 | ||
76c1dec1 | 4028 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 4029 | if (ret) |
76c1dec1 | 4030 | return ret; |
673a394b | 4031 | |
03ac0642 CW |
4032 | obj = i915_gem_object_lookup(file, args->handle); |
4033 | if (!obj) { | |
1d7cfea1 CW |
4034 | ret = -ENOENT; |
4035 | goto unlock; | |
673a394b | 4036 | } |
d1b851fc | 4037 | |
0be555b6 CW |
4038 | /* Count all active objects as busy, even if they are currently not used |
4039 | * by the gpu. Users of this interface expect objects to eventually | |
4040 | * become non-busy without any further actions, therefore emit any | |
4041 | * necessary flushes here. | |
c4de0a5d | 4042 | */ |
30dfebf3 | 4043 | ret = i915_gem_object_flush_active(obj); |
b4716185 CW |
4044 | if (ret) |
4045 | goto unref; | |
0be555b6 | 4046 | |
426960be CW |
4047 | args->busy = 0; |
4048 | if (obj->active) { | |
4049 | int i; | |
4050 | ||
666796da | 4051 | for (i = 0; i < I915_NUM_ENGINES; i++) { |
426960be CW |
4052 | struct drm_i915_gem_request *req; |
4053 | ||
4054 | req = obj->last_read_req[i]; | |
4055 | if (req) | |
4a570db5 | 4056 | args->busy |= 1 << (16 + req->engine->exec_id); |
426960be CW |
4057 | } |
4058 | if (obj->last_write_req) | |
4a570db5 | 4059 | args->busy |= obj->last_write_req->engine->exec_id; |
426960be | 4060 | } |
673a394b | 4061 | |
b4716185 | 4062 | unref: |
f8c417cd | 4063 | i915_gem_object_put(obj); |
1d7cfea1 | 4064 | unlock: |
673a394b | 4065 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 4066 | return ret; |
673a394b EA |
4067 | } |
4068 | ||
4069 | int | |
4070 | i915_gem_throttle_ioctl(struct drm_device *dev, void *data, | |
4071 | struct drm_file *file_priv) | |
4072 | { | |
0206e353 | 4073 | return i915_gem_ring_throttle(dev, file_priv); |
673a394b EA |
4074 | } |
4075 | ||
3ef94daa CW |
4076 | int |
4077 | i915_gem_madvise_ioctl(struct drm_device *dev, void *data, | |
4078 | struct drm_file *file_priv) | |
4079 | { | |
fac5e23e | 4080 | struct drm_i915_private *dev_priv = to_i915(dev); |
3ef94daa | 4081 | struct drm_i915_gem_madvise *args = data; |
05394f39 | 4082 | struct drm_i915_gem_object *obj; |
76c1dec1 | 4083 | int ret; |
3ef94daa CW |
4084 | |
4085 | switch (args->madv) { | |
4086 | case I915_MADV_DONTNEED: | |
4087 | case I915_MADV_WILLNEED: | |
4088 | break; | |
4089 | default: | |
4090 | return -EINVAL; | |
4091 | } | |
4092 | ||
1d7cfea1 CW |
4093 | ret = i915_mutex_lock_interruptible(dev); |
4094 | if (ret) | |
4095 | return ret; | |
4096 | ||
03ac0642 CW |
4097 | obj = i915_gem_object_lookup(file_priv, args->handle); |
4098 | if (!obj) { | |
1d7cfea1 CW |
4099 | ret = -ENOENT; |
4100 | goto unlock; | |
3ef94daa | 4101 | } |
3ef94daa | 4102 | |
d7f46fc4 | 4103 | if (i915_gem_obj_is_pinned(obj)) { |
1d7cfea1 CW |
4104 | ret = -EINVAL; |
4105 | goto out; | |
3ef94daa CW |
4106 | } |
4107 | ||
656bfa3a DV |
4108 | if (obj->pages && |
4109 | obj->tiling_mode != I915_TILING_NONE && | |
4110 | dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES) { | |
4111 | if (obj->madv == I915_MADV_WILLNEED) | |
4112 | i915_gem_object_unpin_pages(obj); | |
4113 | if (args->madv == I915_MADV_WILLNEED) | |
4114 | i915_gem_object_pin_pages(obj); | |
4115 | } | |
4116 | ||
05394f39 CW |
4117 | if (obj->madv != __I915_MADV_PURGED) |
4118 | obj->madv = args->madv; | |
3ef94daa | 4119 | |
6c085a72 | 4120 | /* if the object is no longer attached, discard its backing storage */ |
be6a0376 | 4121 | if (obj->madv == I915_MADV_DONTNEED && obj->pages == NULL) |
2d7ef395 CW |
4122 | i915_gem_object_truncate(obj); |
4123 | ||
05394f39 | 4124 | args->retained = obj->madv != __I915_MADV_PURGED; |
bb6baf76 | 4125 | |
1d7cfea1 | 4126 | out: |
f8c417cd | 4127 | i915_gem_object_put(obj); |
1d7cfea1 | 4128 | unlock: |
3ef94daa | 4129 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 4130 | return ret; |
3ef94daa CW |
4131 | } |
4132 | ||
37e680a1 CW |
4133 | void i915_gem_object_init(struct drm_i915_gem_object *obj, |
4134 | const struct drm_i915_gem_object_ops *ops) | |
0327d6ba | 4135 | { |
b4716185 CW |
4136 | int i; |
4137 | ||
35c20a60 | 4138 | INIT_LIST_HEAD(&obj->global_list); |
666796da | 4139 | for (i = 0; i < I915_NUM_ENGINES; i++) |
117897f4 | 4140 | INIT_LIST_HEAD(&obj->engine_list[i]); |
b25cb2f8 | 4141 | INIT_LIST_HEAD(&obj->obj_exec_link); |
2f633156 | 4142 | INIT_LIST_HEAD(&obj->vma_list); |
8d9d5744 | 4143 | INIT_LIST_HEAD(&obj->batch_pool_link); |
0327d6ba | 4144 | |
37e680a1 CW |
4145 | obj->ops = ops; |
4146 | ||
0327d6ba CW |
4147 | obj->fence_reg = I915_FENCE_REG_NONE; |
4148 | obj->madv = I915_MADV_WILLNEED; | |
0327d6ba | 4149 | |
f19ec8cb | 4150 | i915_gem_info_add_obj(to_i915(obj->base.dev), obj->base.size); |
0327d6ba CW |
4151 | } |
4152 | ||
37e680a1 | 4153 | static const struct drm_i915_gem_object_ops i915_gem_object_ops = { |
de472664 | 4154 | .flags = I915_GEM_OBJECT_HAS_STRUCT_PAGE, |
37e680a1 CW |
4155 | .get_pages = i915_gem_object_get_pages_gtt, |
4156 | .put_pages = i915_gem_object_put_pages_gtt, | |
4157 | }; | |
4158 | ||
d37cd8a8 | 4159 | struct drm_i915_gem_object *i915_gem_object_create(struct drm_device *dev, |
05394f39 | 4160 | size_t size) |
ac52bc56 | 4161 | { |
c397b908 | 4162 | struct drm_i915_gem_object *obj; |
5949eac4 | 4163 | struct address_space *mapping; |
1a240d4d | 4164 | gfp_t mask; |
fe3db79b | 4165 | int ret; |
ac52bc56 | 4166 | |
42dcedd4 | 4167 | obj = i915_gem_object_alloc(dev); |
c397b908 | 4168 | if (obj == NULL) |
fe3db79b | 4169 | return ERR_PTR(-ENOMEM); |
673a394b | 4170 | |
fe3db79b CW |
4171 | ret = drm_gem_object_init(dev, &obj->base, size); |
4172 | if (ret) | |
4173 | goto fail; | |
673a394b | 4174 | |
bed1ea95 CW |
4175 | mask = GFP_HIGHUSER | __GFP_RECLAIMABLE; |
4176 | if (IS_CRESTLINE(dev) || IS_BROADWATER(dev)) { | |
4177 | /* 965gm cannot relocate objects above 4GiB. */ | |
4178 | mask &= ~__GFP_HIGHMEM; | |
4179 | mask |= __GFP_DMA32; | |
4180 | } | |
4181 | ||
496ad9aa | 4182 | mapping = file_inode(obj->base.filp)->i_mapping; |
bed1ea95 | 4183 | mapping_set_gfp_mask(mapping, mask); |
5949eac4 | 4184 | |
37e680a1 | 4185 | i915_gem_object_init(obj, &i915_gem_object_ops); |
73aa808f | 4186 | |
c397b908 DV |
4187 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; |
4188 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; | |
673a394b | 4189 | |
3d29b842 ED |
4190 | if (HAS_LLC(dev)) { |
4191 | /* On some devices, we can have the GPU use the LLC (the CPU | |
a1871112 EA |
4192 | * cache) for about a 10% performance improvement |
4193 | * compared to uncached. Graphics requests other than | |
4194 | * display scanout are coherent with the CPU in | |
4195 | * accessing this cache. This means in this mode we | |
4196 | * don't need to clflush on the CPU side, and on the | |
4197 | * GPU side we only need to flush internal caches to | |
4198 | * get data visible to the CPU. | |
4199 | * | |
4200 | * However, we maintain the display planes as UC, and so | |
4201 | * need to rebind when first used as such. | |
4202 | */ | |
4203 | obj->cache_level = I915_CACHE_LLC; | |
4204 | } else | |
4205 | obj->cache_level = I915_CACHE_NONE; | |
4206 | ||
d861e338 DV |
4207 | trace_i915_gem_object_create(obj); |
4208 | ||
05394f39 | 4209 | return obj; |
fe3db79b CW |
4210 | |
4211 | fail: | |
4212 | i915_gem_object_free(obj); | |
4213 | ||
4214 | return ERR_PTR(ret); | |
c397b908 DV |
4215 | } |
4216 | ||
340fbd8c CW |
4217 | static bool discard_backing_storage(struct drm_i915_gem_object *obj) |
4218 | { | |
4219 | /* If we are the last user of the backing storage (be it shmemfs | |
4220 | * pages or stolen etc), we know that the pages are going to be | |
4221 | * immediately released. In this case, we can then skip copying | |
4222 | * back the contents from the GPU. | |
4223 | */ | |
4224 | ||
4225 | if (obj->madv != I915_MADV_WILLNEED) | |
4226 | return false; | |
4227 | ||
4228 | if (obj->base.filp == NULL) | |
4229 | return true; | |
4230 | ||
4231 | /* At first glance, this looks racy, but then again so would be | |
4232 | * userspace racing mmap against close. However, the first external | |
4233 | * reference to the filp can only be obtained through the | |
4234 | * i915_gem_mmap_ioctl() which safeguards us against the user | |
4235 | * acquiring such a reference whilst we are in the middle of | |
4236 | * freeing the object. | |
4237 | */ | |
4238 | return atomic_long_read(&obj->base.filp->f_count) == 1; | |
4239 | } | |
4240 | ||
1488fc08 | 4241 | void i915_gem_free_object(struct drm_gem_object *gem_obj) |
673a394b | 4242 | { |
1488fc08 | 4243 | struct drm_i915_gem_object *obj = to_intel_bo(gem_obj); |
05394f39 | 4244 | struct drm_device *dev = obj->base.dev; |
fac5e23e | 4245 | struct drm_i915_private *dev_priv = to_i915(dev); |
07fe0b12 | 4246 | struct i915_vma *vma, *next; |
673a394b | 4247 | |
f65c9168 PZ |
4248 | intel_runtime_pm_get(dev_priv); |
4249 | ||
26e12f89 CW |
4250 | trace_i915_gem_object_destroy(obj); |
4251 | ||
1c7f4bca | 4252 | list_for_each_entry_safe(vma, next, &obj->vma_list, obj_link) { |
d7f46fc4 BW |
4253 | int ret; |
4254 | ||
4255 | vma->pin_count = 0; | |
c13d87ea | 4256 | ret = __i915_vma_unbind_no_wait(vma); |
07fe0b12 BW |
4257 | if (WARN_ON(ret == -ERESTARTSYS)) { |
4258 | bool was_interruptible; | |
1488fc08 | 4259 | |
07fe0b12 BW |
4260 | was_interruptible = dev_priv->mm.interruptible; |
4261 | dev_priv->mm.interruptible = false; | |
1488fc08 | 4262 | |
07fe0b12 | 4263 | WARN_ON(i915_vma_unbind(vma)); |
1488fc08 | 4264 | |
07fe0b12 BW |
4265 | dev_priv->mm.interruptible = was_interruptible; |
4266 | } | |
1488fc08 CW |
4267 | } |
4268 | ||
1d64ae71 BW |
4269 | /* Stolen objects don't hold a ref, but do hold pin count. Fix that up |
4270 | * before progressing. */ | |
4271 | if (obj->stolen) | |
4272 | i915_gem_object_unpin_pages(obj); | |
4273 | ||
a071fa00 DV |
4274 | WARN_ON(obj->frontbuffer_bits); |
4275 | ||
656bfa3a DV |
4276 | if (obj->pages && obj->madv == I915_MADV_WILLNEED && |
4277 | dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES && | |
4278 | obj->tiling_mode != I915_TILING_NONE) | |
4279 | i915_gem_object_unpin_pages(obj); | |
4280 | ||
401c29f6 BW |
4281 | if (WARN_ON(obj->pages_pin_count)) |
4282 | obj->pages_pin_count = 0; | |
340fbd8c | 4283 | if (discard_backing_storage(obj)) |
5537252b | 4284 | obj->madv = I915_MADV_DONTNEED; |
37e680a1 | 4285 | i915_gem_object_put_pages(obj); |
de151cf6 | 4286 | |
9da3da66 CW |
4287 | BUG_ON(obj->pages); |
4288 | ||
2f745ad3 CW |
4289 | if (obj->base.import_attach) |
4290 | drm_prime_gem_destroy(&obj->base, NULL); | |
de151cf6 | 4291 | |
5cc9ed4b CW |
4292 | if (obj->ops->release) |
4293 | obj->ops->release(obj); | |
4294 | ||
05394f39 CW |
4295 | drm_gem_object_release(&obj->base); |
4296 | i915_gem_info_remove_obj(dev_priv, obj->base.size); | |
c397b908 | 4297 | |
05394f39 | 4298 | kfree(obj->bit_17); |
42dcedd4 | 4299 | i915_gem_object_free(obj); |
f65c9168 PZ |
4300 | |
4301 | intel_runtime_pm_put(dev_priv); | |
673a394b EA |
4302 | } |
4303 | ||
ec7adb6e JL |
4304 | struct i915_vma *i915_gem_obj_to_vma(struct drm_i915_gem_object *obj, |
4305 | struct i915_address_space *vm) | |
e656a6cb DV |
4306 | { |
4307 | struct i915_vma *vma; | |
1c7f4bca | 4308 | list_for_each_entry(vma, &obj->vma_list, obj_link) { |
1b683729 TU |
4309 | if (vma->ggtt_view.type == I915_GGTT_VIEW_NORMAL && |
4310 | vma->vm == vm) | |
e656a6cb | 4311 | return vma; |
ec7adb6e JL |
4312 | } |
4313 | return NULL; | |
4314 | } | |
4315 | ||
4316 | struct i915_vma *i915_gem_obj_to_ggtt_view(struct drm_i915_gem_object *obj, | |
4317 | const struct i915_ggtt_view *view) | |
4318 | { | |
ec7adb6e | 4319 | struct i915_vma *vma; |
e656a6cb | 4320 | |
598b9ec8 | 4321 | GEM_BUG_ON(!view); |
ec7adb6e | 4322 | |
1c7f4bca | 4323 | list_for_each_entry(vma, &obj->vma_list, obj_link) |
598b9ec8 | 4324 | if (vma->is_ggtt && i915_ggtt_view_equal(&vma->ggtt_view, view)) |
ec7adb6e | 4325 | return vma; |
e656a6cb DV |
4326 | return NULL; |
4327 | } | |
4328 | ||
2f633156 BW |
4329 | void i915_gem_vma_destroy(struct i915_vma *vma) |
4330 | { | |
4331 | WARN_ON(vma->node.allocated); | |
aaa05667 CW |
4332 | |
4333 | /* Keep the vma as a placeholder in the execbuffer reservation lists */ | |
4334 | if (!list_empty(&vma->exec_list)) | |
4335 | return; | |
4336 | ||
596c5923 CW |
4337 | if (!vma->is_ggtt) |
4338 | i915_ppgtt_put(i915_vm_to_ppgtt(vma->vm)); | |
b9d06dd9 | 4339 | |
1c7f4bca | 4340 | list_del(&vma->obj_link); |
b93dab6e | 4341 | |
e20d2ab7 | 4342 | kmem_cache_free(to_i915(vma->obj->base.dev)->vmas, vma); |
2f633156 BW |
4343 | } |
4344 | ||
e3efda49 | 4345 | static void |
117897f4 | 4346 | i915_gem_stop_engines(struct drm_device *dev) |
e3efda49 | 4347 | { |
fac5e23e | 4348 | struct drm_i915_private *dev_priv = to_i915(dev); |
e2f80391 | 4349 | struct intel_engine_cs *engine; |
e3efda49 | 4350 | |
b4ac5afc | 4351 | for_each_engine(engine, dev_priv) |
117897f4 | 4352 | dev_priv->gt.stop_engine(engine); |
e3efda49 CW |
4353 | } |
4354 | ||
29105ccc | 4355 | int |
45c5f202 | 4356 | i915_gem_suspend(struct drm_device *dev) |
29105ccc | 4357 | { |
fac5e23e | 4358 | struct drm_i915_private *dev_priv = to_i915(dev); |
45c5f202 | 4359 | int ret = 0; |
28dfe52a | 4360 | |
54b4f68f CW |
4361 | intel_suspend_gt_powersave(dev_priv); |
4362 | ||
45c5f202 | 4363 | mutex_lock(&dev->struct_mutex); |
5ab57c70 CW |
4364 | |
4365 | /* We have to flush all the executing contexts to main memory so | |
4366 | * that they can saved in the hibernation image. To ensure the last | |
4367 | * context image is coherent, we have to switch away from it. That | |
4368 | * leaves the dev_priv->kernel_context still active when | |
4369 | * we actually suspend, and its image in memory may not match the GPU | |
4370 | * state. Fortunately, the kernel_context is disposable and we do | |
4371 | * not rely on its state. | |
4372 | */ | |
4373 | ret = i915_gem_switch_to_kernel_context(dev_priv); | |
4374 | if (ret) | |
4375 | goto err; | |
4376 | ||
6e5a5beb | 4377 | ret = i915_gem_wait_for_idle(dev_priv); |
f7403347 | 4378 | if (ret) |
45c5f202 | 4379 | goto err; |
f7403347 | 4380 | |
c033666a | 4381 | i915_gem_retire_requests(dev_priv); |
673a394b | 4382 | |
5ab57c70 CW |
4383 | /* Note that rather than stopping the engines, all we have to do |
4384 | * is assert that every RING_HEAD == RING_TAIL (all execution complete) | |
4385 | * and similar for all logical context images (to ensure they are | |
4386 | * all ready for hibernation). | |
4387 | */ | |
117897f4 | 4388 | i915_gem_stop_engines(dev); |
b2e862d0 | 4389 | i915_gem_context_lost(dev_priv); |
45c5f202 CW |
4390 | mutex_unlock(&dev->struct_mutex); |
4391 | ||
737b1506 | 4392 | cancel_delayed_work_sync(&dev_priv->gpu_error.hangcheck_work); |
67d97da3 CW |
4393 | cancel_delayed_work_sync(&dev_priv->gt.retire_work); |
4394 | flush_delayed_work(&dev_priv->gt.idle_work); | |
29105ccc | 4395 | |
bdcf120b CW |
4396 | /* Assert that we sucessfully flushed all the work and |
4397 | * reset the GPU back to its idle, low power state. | |
4398 | */ | |
67d97da3 | 4399 | WARN_ON(dev_priv->gt.awake); |
bdcf120b | 4400 | |
673a394b | 4401 | return 0; |
45c5f202 CW |
4402 | |
4403 | err: | |
4404 | mutex_unlock(&dev->struct_mutex); | |
4405 | return ret; | |
673a394b EA |
4406 | } |
4407 | ||
5ab57c70 CW |
4408 | void i915_gem_resume(struct drm_device *dev) |
4409 | { | |
4410 | struct drm_i915_private *dev_priv = to_i915(dev); | |
4411 | ||
4412 | mutex_lock(&dev->struct_mutex); | |
4413 | i915_gem_restore_gtt_mappings(dev); | |
4414 | ||
4415 | /* As we didn't flush the kernel context before suspend, we cannot | |
4416 | * guarantee that the context image is complete. So let's just reset | |
4417 | * it and start again. | |
4418 | */ | |
4419 | if (i915.enable_execlists) | |
4420 | intel_lr_context_reset(dev_priv, dev_priv->kernel_context); | |
4421 | ||
4422 | mutex_unlock(&dev->struct_mutex); | |
4423 | } | |
4424 | ||
f691e2f4 DV |
4425 | void i915_gem_init_swizzling(struct drm_device *dev) |
4426 | { | |
fac5e23e | 4427 | struct drm_i915_private *dev_priv = to_i915(dev); |
f691e2f4 | 4428 | |
11782b02 | 4429 | if (INTEL_INFO(dev)->gen < 5 || |
f691e2f4 DV |
4430 | dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE) |
4431 | return; | |
4432 | ||
4433 | I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) | | |
4434 | DISP_TILE_SURFACE_SWIZZLING); | |
4435 | ||
11782b02 DV |
4436 | if (IS_GEN5(dev)) |
4437 | return; | |
4438 | ||
f691e2f4 DV |
4439 | I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_SWZCTL); |
4440 | if (IS_GEN6(dev)) | |
6b26c86d | 4441 | I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB)); |
8782e26c | 4442 | else if (IS_GEN7(dev)) |
6b26c86d | 4443 | I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB)); |
31a5336e BW |
4444 | else if (IS_GEN8(dev)) |
4445 | I915_WRITE(GAMTARBMODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_BDW)); | |
8782e26c BW |
4446 | else |
4447 | BUG(); | |
f691e2f4 | 4448 | } |
e21af88d | 4449 | |
81e7f200 VS |
4450 | static void init_unused_ring(struct drm_device *dev, u32 base) |
4451 | { | |
fac5e23e | 4452 | struct drm_i915_private *dev_priv = to_i915(dev); |
81e7f200 VS |
4453 | |
4454 | I915_WRITE(RING_CTL(base), 0); | |
4455 | I915_WRITE(RING_HEAD(base), 0); | |
4456 | I915_WRITE(RING_TAIL(base), 0); | |
4457 | I915_WRITE(RING_START(base), 0); | |
4458 | } | |
4459 | ||
4460 | static void init_unused_rings(struct drm_device *dev) | |
4461 | { | |
4462 | if (IS_I830(dev)) { | |
4463 | init_unused_ring(dev, PRB1_BASE); | |
4464 | init_unused_ring(dev, SRB0_BASE); | |
4465 | init_unused_ring(dev, SRB1_BASE); | |
4466 | init_unused_ring(dev, SRB2_BASE); | |
4467 | init_unused_ring(dev, SRB3_BASE); | |
4468 | } else if (IS_GEN2(dev)) { | |
4469 | init_unused_ring(dev, SRB0_BASE); | |
4470 | init_unused_ring(dev, SRB1_BASE); | |
4471 | } else if (IS_GEN3(dev)) { | |
4472 | init_unused_ring(dev, PRB1_BASE); | |
4473 | init_unused_ring(dev, PRB2_BASE); | |
4474 | } | |
4475 | } | |
4476 | ||
4fc7c971 BW |
4477 | int |
4478 | i915_gem_init_hw(struct drm_device *dev) | |
4479 | { | |
fac5e23e | 4480 | struct drm_i915_private *dev_priv = to_i915(dev); |
e2f80391 | 4481 | struct intel_engine_cs *engine; |
d200cda6 | 4482 | int ret; |
4fc7c971 | 4483 | |
5e4f5189 CW |
4484 | /* Double layer security blanket, see i915_gem_init() */ |
4485 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); | |
4486 | ||
3accaf7e | 4487 | if (HAS_EDRAM(dev) && INTEL_GEN(dev_priv) < 9) |
05e21cc4 | 4488 | I915_WRITE(HSW_IDICR, I915_READ(HSW_IDICR) | IDIHASHMSK(0xf)); |
4fc7c971 | 4489 | |
0bf21347 VS |
4490 | if (IS_HASWELL(dev)) |
4491 | I915_WRITE(MI_PREDICATE_RESULT_2, IS_HSW_GT3(dev) ? | |
4492 | LOWER_SLICE_ENABLED : LOWER_SLICE_DISABLED); | |
9435373e | 4493 | |
88a2b2a3 | 4494 | if (HAS_PCH_NOP(dev)) { |
6ba844b0 DV |
4495 | if (IS_IVYBRIDGE(dev)) { |
4496 | u32 temp = I915_READ(GEN7_MSG_CTL); | |
4497 | temp &= ~(WAIT_FOR_PCH_FLR_ACK | WAIT_FOR_PCH_RESET_ACK); | |
4498 | I915_WRITE(GEN7_MSG_CTL, temp); | |
4499 | } else if (INTEL_INFO(dev)->gen >= 7) { | |
4500 | u32 temp = I915_READ(HSW_NDE_RSTWRN_OPT); | |
4501 | temp &= ~RESET_PCH_HANDSHAKE_ENABLE; | |
4502 | I915_WRITE(HSW_NDE_RSTWRN_OPT, temp); | |
4503 | } | |
88a2b2a3 BW |
4504 | } |
4505 | ||
4fc7c971 BW |
4506 | i915_gem_init_swizzling(dev); |
4507 | ||
d5abdfda DV |
4508 | /* |
4509 | * At least 830 can leave some of the unused rings | |
4510 | * "active" (ie. head != tail) after resume which | |
4511 | * will prevent c3 entry. Makes sure all unused rings | |
4512 | * are totally idle. | |
4513 | */ | |
4514 | init_unused_rings(dev); | |
4515 | ||
ed54c1a1 | 4516 | BUG_ON(!dev_priv->kernel_context); |
90638cc1 | 4517 | |
4ad2fd88 JH |
4518 | ret = i915_ppgtt_init_hw(dev); |
4519 | if (ret) { | |
4520 | DRM_ERROR("PPGTT enable HW failed %d\n", ret); | |
4521 | goto out; | |
4522 | } | |
4523 | ||
4524 | /* Need to do basic initialisation of all rings first: */ | |
b4ac5afc | 4525 | for_each_engine(engine, dev_priv) { |
e2f80391 | 4526 | ret = engine->init_hw(engine); |
35a57ffb | 4527 | if (ret) |
5e4f5189 | 4528 | goto out; |
35a57ffb | 4529 | } |
99433931 | 4530 | |
0ccdacf6 PA |
4531 | intel_mocs_init_l3cc_table(dev); |
4532 | ||
33a732f4 | 4533 | /* We can't enable contexts until all firmware is loaded */ |
e556f7c1 DG |
4534 | ret = intel_guc_setup(dev); |
4535 | if (ret) | |
4536 | goto out; | |
33a732f4 | 4537 | |
5e4f5189 CW |
4538 | out: |
4539 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); | |
2fa48d8d | 4540 | return ret; |
8187a2b7 ZN |
4541 | } |
4542 | ||
39df9190 CW |
4543 | bool intel_sanitize_semaphores(struct drm_i915_private *dev_priv, int value) |
4544 | { | |
4545 | if (INTEL_INFO(dev_priv)->gen < 6) | |
4546 | return false; | |
4547 | ||
4548 | /* TODO: make semaphores and Execlists play nicely together */ | |
4549 | if (i915.enable_execlists) | |
4550 | return false; | |
4551 | ||
4552 | if (value >= 0) | |
4553 | return value; | |
4554 | ||
4555 | #ifdef CONFIG_INTEL_IOMMU | |
4556 | /* Enable semaphores on SNB when IO remapping is off */ | |
4557 | if (INTEL_INFO(dev_priv)->gen == 6 && intel_iommu_gfx_mapped) | |
4558 | return false; | |
4559 | #endif | |
4560 | ||
4561 | return true; | |
4562 | } | |
4563 | ||
1070a42b CW |
4564 | int i915_gem_init(struct drm_device *dev) |
4565 | { | |
fac5e23e | 4566 | struct drm_i915_private *dev_priv = to_i915(dev); |
1070a42b CW |
4567 | int ret; |
4568 | ||
1070a42b | 4569 | mutex_lock(&dev->struct_mutex); |
d62b4892 | 4570 | |
a83014d3 | 4571 | if (!i915.enable_execlists) { |
f3dc74c0 | 4572 | dev_priv->gt.execbuf_submit = i915_gem_ringbuffer_submission; |
7e37f889 CW |
4573 | dev_priv->gt.cleanup_engine = intel_engine_cleanup; |
4574 | dev_priv->gt.stop_engine = intel_engine_stop; | |
454afebd | 4575 | } else { |
f3dc74c0 | 4576 | dev_priv->gt.execbuf_submit = intel_execlists_submission; |
117897f4 TU |
4577 | dev_priv->gt.cleanup_engine = intel_logical_ring_cleanup; |
4578 | dev_priv->gt.stop_engine = intel_logical_ring_stop; | |
a83014d3 OM |
4579 | } |
4580 | ||
5e4f5189 CW |
4581 | /* This is just a security blanket to placate dragons. |
4582 | * On some systems, we very sporadically observe that the first TLBs | |
4583 | * used by the CS may be stale, despite us poking the TLB reset. If | |
4584 | * we hold the forcewake during initialisation these problems | |
4585 | * just magically go away. | |
4586 | */ | |
4587 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); | |
4588 | ||
72778cb2 | 4589 | i915_gem_init_userptr(dev_priv); |
d85489d3 | 4590 | i915_gem_init_ggtt(dev); |
d62b4892 | 4591 | |
2fa48d8d | 4592 | ret = i915_gem_context_init(dev); |
7bcc3777 JN |
4593 | if (ret) |
4594 | goto out_unlock; | |
2fa48d8d | 4595 | |
8b3e2d36 | 4596 | ret = intel_engines_init(dev); |
35a57ffb | 4597 | if (ret) |
7bcc3777 | 4598 | goto out_unlock; |
2fa48d8d | 4599 | |
1070a42b | 4600 | ret = i915_gem_init_hw(dev); |
60990320 | 4601 | if (ret == -EIO) { |
7e21d648 | 4602 | /* Allow engine initialisation to fail by marking the GPU as |
60990320 CW |
4603 | * wedged. But we only want to do this where the GPU is angry, |
4604 | * for all other failure, such as an allocation failure, bail. | |
4605 | */ | |
4606 | DRM_ERROR("Failed to initialize GPU, declaring it wedged\n"); | |
805de8f4 | 4607 | atomic_or(I915_WEDGED, &dev_priv->gpu_error.reset_counter); |
60990320 | 4608 | ret = 0; |
1070a42b | 4609 | } |
7bcc3777 JN |
4610 | |
4611 | out_unlock: | |
5e4f5189 | 4612 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); |
60990320 | 4613 | mutex_unlock(&dev->struct_mutex); |
1070a42b | 4614 | |
60990320 | 4615 | return ret; |
1070a42b CW |
4616 | } |
4617 | ||
8187a2b7 | 4618 | void |
117897f4 | 4619 | i915_gem_cleanup_engines(struct drm_device *dev) |
8187a2b7 | 4620 | { |
fac5e23e | 4621 | struct drm_i915_private *dev_priv = to_i915(dev); |
e2f80391 | 4622 | struct intel_engine_cs *engine; |
8187a2b7 | 4623 | |
b4ac5afc | 4624 | for_each_engine(engine, dev_priv) |
117897f4 | 4625 | dev_priv->gt.cleanup_engine(engine); |
8187a2b7 ZN |
4626 | } |
4627 | ||
64193406 | 4628 | static void |
666796da | 4629 | init_engine_lists(struct intel_engine_cs *engine) |
64193406 | 4630 | { |
0bc40be8 TU |
4631 | INIT_LIST_HEAD(&engine->active_list); |
4632 | INIT_LIST_HEAD(&engine->request_list); | |
64193406 CW |
4633 | } |
4634 | ||
40ae4e16 ID |
4635 | void |
4636 | i915_gem_load_init_fences(struct drm_i915_private *dev_priv) | |
4637 | { | |
91c8a326 | 4638 | struct drm_device *dev = &dev_priv->drm; |
40ae4e16 ID |
4639 | |
4640 | if (INTEL_INFO(dev_priv)->gen >= 7 && !IS_VALLEYVIEW(dev_priv) && | |
4641 | !IS_CHERRYVIEW(dev_priv)) | |
4642 | dev_priv->num_fence_regs = 32; | |
4643 | else if (INTEL_INFO(dev_priv)->gen >= 4 || IS_I945G(dev_priv) || | |
4644 | IS_I945GM(dev_priv) || IS_G33(dev_priv)) | |
4645 | dev_priv->num_fence_regs = 16; | |
4646 | else | |
4647 | dev_priv->num_fence_regs = 8; | |
4648 | ||
c033666a | 4649 | if (intel_vgpu_active(dev_priv)) |
40ae4e16 ID |
4650 | dev_priv->num_fence_regs = |
4651 | I915_READ(vgtif_reg(avail_rs.fence_num)); | |
4652 | ||
4653 | /* Initialize fence registers to zero */ | |
4654 | i915_gem_restore_fences(dev); | |
4655 | ||
4656 | i915_gem_detect_bit_6_swizzle(dev); | |
4657 | } | |
4658 | ||
673a394b | 4659 | void |
d64aa096 | 4660 | i915_gem_load_init(struct drm_device *dev) |
673a394b | 4661 | { |
fac5e23e | 4662 | struct drm_i915_private *dev_priv = to_i915(dev); |
42dcedd4 CW |
4663 | int i; |
4664 | ||
efab6d8d | 4665 | dev_priv->objects = |
42dcedd4 CW |
4666 | kmem_cache_create("i915_gem_object", |
4667 | sizeof(struct drm_i915_gem_object), 0, | |
4668 | SLAB_HWCACHE_ALIGN, | |
4669 | NULL); | |
e20d2ab7 CW |
4670 | dev_priv->vmas = |
4671 | kmem_cache_create("i915_gem_vma", | |
4672 | sizeof(struct i915_vma), 0, | |
4673 | SLAB_HWCACHE_ALIGN, | |
4674 | NULL); | |
efab6d8d CW |
4675 | dev_priv->requests = |
4676 | kmem_cache_create("i915_gem_request", | |
4677 | sizeof(struct drm_i915_gem_request), 0, | |
4678 | SLAB_HWCACHE_ALIGN, | |
4679 | NULL); | |
673a394b | 4680 | |
fc8c067e | 4681 | INIT_LIST_HEAD(&dev_priv->vm_list); |
a33afea5 | 4682 | INIT_LIST_HEAD(&dev_priv->context_list); |
6c085a72 CW |
4683 | INIT_LIST_HEAD(&dev_priv->mm.unbound_list); |
4684 | INIT_LIST_HEAD(&dev_priv->mm.bound_list); | |
a09ba7fa | 4685 | INIT_LIST_HEAD(&dev_priv->mm.fence_list); |
666796da TU |
4686 | for (i = 0; i < I915_NUM_ENGINES; i++) |
4687 | init_engine_lists(&dev_priv->engine[i]); | |
4b9de737 | 4688 | for (i = 0; i < I915_MAX_NUM_FENCES; i++) |
007cc8ac | 4689 | INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list); |
67d97da3 | 4690 | INIT_DELAYED_WORK(&dev_priv->gt.retire_work, |
673a394b | 4691 | i915_gem_retire_work_handler); |
67d97da3 | 4692 | INIT_DELAYED_WORK(&dev_priv->gt.idle_work, |
b29c19b6 | 4693 | i915_gem_idle_work_handler); |
1f15b76f | 4694 | init_waitqueue_head(&dev_priv->gpu_error.wait_queue); |
1f83fee0 | 4695 | init_waitqueue_head(&dev_priv->gpu_error.reset_queue); |
31169714 | 4696 | |
72bfa19c CW |
4697 | dev_priv->relative_constants_mode = I915_EXEC_CONSTANTS_REL_GENERAL; |
4698 | ||
19b2dbde | 4699 | INIT_LIST_HEAD(&dev_priv->mm.fence_list); |
10ed13e4 | 4700 | |
6b95a207 | 4701 | init_waitqueue_head(&dev_priv->pending_flip_queue); |
17250b71 | 4702 | |
ce453d81 CW |
4703 | dev_priv->mm.interruptible = true; |
4704 | ||
f99d7069 | 4705 | mutex_init(&dev_priv->fb_tracking.lock); |
673a394b | 4706 | } |
71acb5eb | 4707 | |
d64aa096 ID |
4708 | void i915_gem_load_cleanup(struct drm_device *dev) |
4709 | { | |
4710 | struct drm_i915_private *dev_priv = to_i915(dev); | |
4711 | ||
4712 | kmem_cache_destroy(dev_priv->requests); | |
4713 | kmem_cache_destroy(dev_priv->vmas); | |
4714 | kmem_cache_destroy(dev_priv->objects); | |
4715 | } | |
4716 | ||
461fb99c CW |
4717 | int i915_gem_freeze_late(struct drm_i915_private *dev_priv) |
4718 | { | |
4719 | struct drm_i915_gem_object *obj; | |
4720 | ||
4721 | /* Called just before we write the hibernation image. | |
4722 | * | |
4723 | * We need to update the domain tracking to reflect that the CPU | |
4724 | * will be accessing all the pages to create and restore from the | |
4725 | * hibernation, and so upon restoration those pages will be in the | |
4726 | * CPU domain. | |
4727 | * | |
4728 | * To make sure the hibernation image contains the latest state, | |
4729 | * we update that state just before writing out the image. | |
4730 | */ | |
4731 | ||
4732 | list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) { | |
4733 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; | |
4734 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; | |
4735 | } | |
4736 | ||
4737 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) { | |
4738 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; | |
4739 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; | |
4740 | } | |
4741 | ||
4742 | return 0; | |
4743 | } | |
4744 | ||
f787a5f5 | 4745 | void i915_gem_release(struct drm_device *dev, struct drm_file *file) |
b962442e | 4746 | { |
f787a5f5 | 4747 | struct drm_i915_file_private *file_priv = file->driver_priv; |
15f7bbc7 | 4748 | struct drm_i915_gem_request *request; |
b962442e EA |
4749 | |
4750 | /* Clean up our request list when the client is going away, so that | |
4751 | * later retire_requests won't dereference our soon-to-be-gone | |
4752 | * file_priv. | |
4753 | */ | |
1c25595f | 4754 | spin_lock(&file_priv->mm.lock); |
15f7bbc7 | 4755 | list_for_each_entry(request, &file_priv->mm.request_list, client_list) |
f787a5f5 | 4756 | request->file_priv = NULL; |
1c25595f | 4757 | spin_unlock(&file_priv->mm.lock); |
b29c19b6 | 4758 | |
2e1b8730 | 4759 | if (!list_empty(&file_priv->rps.link)) { |
8d3afd7d | 4760 | spin_lock(&to_i915(dev)->rps.client_lock); |
2e1b8730 | 4761 | list_del(&file_priv->rps.link); |
8d3afd7d | 4762 | spin_unlock(&to_i915(dev)->rps.client_lock); |
1854d5ca | 4763 | } |
b29c19b6 CW |
4764 | } |
4765 | ||
4766 | int i915_gem_open(struct drm_device *dev, struct drm_file *file) | |
4767 | { | |
4768 | struct drm_i915_file_private *file_priv; | |
e422b888 | 4769 | int ret; |
b29c19b6 CW |
4770 | |
4771 | DRM_DEBUG_DRIVER("\n"); | |
4772 | ||
4773 | file_priv = kzalloc(sizeof(*file_priv), GFP_KERNEL); | |
4774 | if (!file_priv) | |
4775 | return -ENOMEM; | |
4776 | ||
4777 | file->driver_priv = file_priv; | |
f19ec8cb | 4778 | file_priv->dev_priv = to_i915(dev); |
ab0e7ff9 | 4779 | file_priv->file = file; |
2e1b8730 | 4780 | INIT_LIST_HEAD(&file_priv->rps.link); |
b29c19b6 CW |
4781 | |
4782 | spin_lock_init(&file_priv->mm.lock); | |
4783 | INIT_LIST_HEAD(&file_priv->mm.request_list); | |
b29c19b6 | 4784 | |
c80ff16e | 4785 | file_priv->bsd_engine = -1; |
de1add36 | 4786 | |
e422b888 BW |
4787 | ret = i915_gem_context_open(dev, file); |
4788 | if (ret) | |
4789 | kfree(file_priv); | |
b29c19b6 | 4790 | |
e422b888 | 4791 | return ret; |
b29c19b6 CW |
4792 | } |
4793 | ||
b680c37a DV |
4794 | /** |
4795 | * i915_gem_track_fb - update frontbuffer tracking | |
d9072a3e GT |
4796 | * @old: current GEM buffer for the frontbuffer slots |
4797 | * @new: new GEM buffer for the frontbuffer slots | |
4798 | * @frontbuffer_bits: bitmask of frontbuffer slots | |
b680c37a DV |
4799 | * |
4800 | * This updates the frontbuffer tracking bits @frontbuffer_bits by clearing them | |
4801 | * from @old and setting them in @new. Both @old and @new can be NULL. | |
4802 | */ | |
a071fa00 DV |
4803 | void i915_gem_track_fb(struct drm_i915_gem_object *old, |
4804 | struct drm_i915_gem_object *new, | |
4805 | unsigned frontbuffer_bits) | |
4806 | { | |
4807 | if (old) { | |
4808 | WARN_ON(!mutex_is_locked(&old->base.dev->struct_mutex)); | |
4809 | WARN_ON(!(old->frontbuffer_bits & frontbuffer_bits)); | |
4810 | old->frontbuffer_bits &= ~frontbuffer_bits; | |
4811 | } | |
4812 | ||
4813 | if (new) { | |
4814 | WARN_ON(!mutex_is_locked(&new->base.dev->struct_mutex)); | |
4815 | WARN_ON(new->frontbuffer_bits & frontbuffer_bits); | |
4816 | new->frontbuffer_bits |= frontbuffer_bits; | |
4817 | } | |
4818 | } | |
4819 | ||
a70a3148 | 4820 | /* All the new VM stuff */ |
088e0df4 MT |
4821 | u64 i915_gem_obj_offset(struct drm_i915_gem_object *o, |
4822 | struct i915_address_space *vm) | |
a70a3148 | 4823 | { |
fac5e23e | 4824 | struct drm_i915_private *dev_priv = to_i915(o->base.dev); |
a70a3148 BW |
4825 | struct i915_vma *vma; |
4826 | ||
896ab1a5 | 4827 | WARN_ON(vm == &dev_priv->mm.aliasing_ppgtt->base); |
a70a3148 | 4828 | |
1c7f4bca | 4829 | list_for_each_entry(vma, &o->vma_list, obj_link) { |
596c5923 | 4830 | if (vma->is_ggtt && |
ec7adb6e JL |
4831 | vma->ggtt_view.type != I915_GGTT_VIEW_NORMAL) |
4832 | continue; | |
4833 | if (vma->vm == vm) | |
a70a3148 | 4834 | return vma->node.start; |
a70a3148 | 4835 | } |
ec7adb6e | 4836 | |
f25748ea DV |
4837 | WARN(1, "%s vma for this object not found.\n", |
4838 | i915_is_ggtt(vm) ? "global" : "ppgtt"); | |
a70a3148 BW |
4839 | return -1; |
4840 | } | |
4841 | ||
088e0df4 MT |
4842 | u64 i915_gem_obj_ggtt_offset_view(struct drm_i915_gem_object *o, |
4843 | const struct i915_ggtt_view *view) | |
a70a3148 BW |
4844 | { |
4845 | struct i915_vma *vma; | |
4846 | ||
1c7f4bca | 4847 | list_for_each_entry(vma, &o->vma_list, obj_link) |
8aac2220 | 4848 | if (vma->is_ggtt && i915_ggtt_view_equal(&vma->ggtt_view, view)) |
ec7adb6e JL |
4849 | return vma->node.start; |
4850 | ||
5678ad73 | 4851 | WARN(1, "global vma for this object not found. (view=%u)\n", view->type); |
ec7adb6e JL |
4852 | return -1; |
4853 | } | |
4854 | ||
4855 | bool i915_gem_obj_bound(struct drm_i915_gem_object *o, | |
4856 | struct i915_address_space *vm) | |
4857 | { | |
4858 | struct i915_vma *vma; | |
4859 | ||
1c7f4bca | 4860 | list_for_each_entry(vma, &o->vma_list, obj_link) { |
596c5923 | 4861 | if (vma->is_ggtt && |
ec7adb6e JL |
4862 | vma->ggtt_view.type != I915_GGTT_VIEW_NORMAL) |
4863 | continue; | |
4864 | if (vma->vm == vm && drm_mm_node_allocated(&vma->node)) | |
4865 | return true; | |
4866 | } | |
4867 | ||
4868 | return false; | |
4869 | } | |
4870 | ||
4871 | bool i915_gem_obj_ggtt_bound_view(struct drm_i915_gem_object *o, | |
9abc4648 | 4872 | const struct i915_ggtt_view *view) |
ec7adb6e | 4873 | { |
ec7adb6e JL |
4874 | struct i915_vma *vma; |
4875 | ||
1c7f4bca | 4876 | list_for_each_entry(vma, &o->vma_list, obj_link) |
ff5ec22d | 4877 | if (vma->is_ggtt && |
9abc4648 | 4878 | i915_ggtt_view_equal(&vma->ggtt_view, view) && |
fe14d5f4 | 4879 | drm_mm_node_allocated(&vma->node)) |
a70a3148 BW |
4880 | return true; |
4881 | ||
4882 | return false; | |
4883 | } | |
4884 | ||
4885 | bool i915_gem_obj_bound_any(struct drm_i915_gem_object *o) | |
4886 | { | |
5a1d5eb0 | 4887 | struct i915_vma *vma; |
a70a3148 | 4888 | |
1c7f4bca | 4889 | list_for_each_entry(vma, &o->vma_list, obj_link) |
5a1d5eb0 | 4890 | if (drm_mm_node_allocated(&vma->node)) |
a70a3148 BW |
4891 | return true; |
4892 | ||
4893 | return false; | |
4894 | } | |
4895 | ||
8da32727 | 4896 | unsigned long i915_gem_obj_ggtt_size(struct drm_i915_gem_object *o) |
a70a3148 | 4897 | { |
a70a3148 BW |
4898 | struct i915_vma *vma; |
4899 | ||
8da32727 | 4900 | GEM_BUG_ON(list_empty(&o->vma_list)); |
a70a3148 | 4901 | |
1c7f4bca | 4902 | list_for_each_entry(vma, &o->vma_list, obj_link) { |
596c5923 | 4903 | if (vma->is_ggtt && |
8da32727 | 4904 | vma->ggtt_view.type == I915_GGTT_VIEW_NORMAL) |
a70a3148 | 4905 | return vma->node.size; |
ec7adb6e | 4906 | } |
8da32727 | 4907 | |
a70a3148 BW |
4908 | return 0; |
4909 | } | |
4910 | ||
ec7adb6e | 4911 | bool i915_gem_obj_is_pinned(struct drm_i915_gem_object *obj) |
5c2abbea BW |
4912 | { |
4913 | struct i915_vma *vma; | |
1c7f4bca | 4914 | list_for_each_entry(vma, &obj->vma_list, obj_link) |
ec7adb6e JL |
4915 | if (vma->pin_count > 0) |
4916 | return true; | |
a6631ae1 | 4917 | |
ec7adb6e | 4918 | return false; |
5c2abbea | 4919 | } |
ea70299d | 4920 | |
033908ae DG |
4921 | /* Like i915_gem_object_get_page(), but mark the returned page dirty */ |
4922 | struct page * | |
4923 | i915_gem_object_get_dirty_page(struct drm_i915_gem_object *obj, int n) | |
4924 | { | |
4925 | struct page *page; | |
4926 | ||
4927 | /* Only default objects have per-page dirty tracking */ | |
b9bcd14a | 4928 | if (WARN_ON(!i915_gem_object_has_struct_page(obj))) |
033908ae DG |
4929 | return NULL; |
4930 | ||
4931 | page = i915_gem_object_get_page(obj, n); | |
4932 | set_page_dirty(page); | |
4933 | return page; | |
4934 | } | |
4935 | ||
ea70299d DG |
4936 | /* Allocate a new GEM object and fill it with the supplied data */ |
4937 | struct drm_i915_gem_object * | |
4938 | i915_gem_object_create_from_data(struct drm_device *dev, | |
4939 | const void *data, size_t size) | |
4940 | { | |
4941 | struct drm_i915_gem_object *obj; | |
4942 | struct sg_table *sg; | |
4943 | size_t bytes; | |
4944 | int ret; | |
4945 | ||
d37cd8a8 | 4946 | obj = i915_gem_object_create(dev, round_up(size, PAGE_SIZE)); |
fe3db79b | 4947 | if (IS_ERR(obj)) |
ea70299d DG |
4948 | return obj; |
4949 | ||
4950 | ret = i915_gem_object_set_to_cpu_domain(obj, true); | |
4951 | if (ret) | |
4952 | goto fail; | |
4953 | ||
4954 | ret = i915_gem_object_get_pages(obj); | |
4955 | if (ret) | |
4956 | goto fail; | |
4957 | ||
4958 | i915_gem_object_pin_pages(obj); | |
4959 | sg = obj->pages; | |
4960 | bytes = sg_copy_from_buffer(sg->sgl, sg->nents, (void *)data, size); | |
9e7d18c0 | 4961 | obj->dirty = 1; /* Backing store is now out of date */ |
ea70299d DG |
4962 | i915_gem_object_unpin_pages(obj); |
4963 | ||
4964 | if (WARN_ON(bytes != size)) { | |
4965 | DRM_ERROR("Incomplete copy, wrote %zu of %zu", bytes, size); | |
4966 | ret = -EFAULT; | |
4967 | goto fail; | |
4968 | } | |
4969 | ||
4970 | return obj; | |
4971 | ||
4972 | fail: | |
f8c417cd | 4973 | i915_gem_object_put(obj); |
ea70299d DG |
4974 | return ERR_PTR(ret); |
4975 | } |