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Commit | Line | Data |
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673a394b EA |
1 | /* |
2 | * Copyright © 2008 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | * | |
26 | */ | |
27 | ||
28 | #include "drmP.h" | |
29 | #include "drm.h" | |
30 | #include "i915_drm.h" | |
31 | #include "i915_drv.h" | |
1c5d22f7 | 32 | #include "i915_trace.h" |
652c393a | 33 | #include "intel_drv.h" |
5949eac4 | 34 | #include <linux/shmem_fs.h> |
5a0e3ad6 | 35 | #include <linux/slab.h> |
673a394b | 36 | #include <linux/swap.h> |
79e53945 | 37 | #include <linux/pci.h> |
673a394b | 38 | |
88241785 | 39 | static __must_check int i915_gem_object_flush_gpu_write_domain(struct drm_i915_gem_object *obj); |
05394f39 CW |
40 | static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj); |
41 | static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj); | |
88241785 CW |
42 | static __must_check int i915_gem_object_bind_to_gtt(struct drm_i915_gem_object *obj, |
43 | unsigned alignment, | |
44 | bool map_and_fenceable); | |
05394f39 CW |
45 | static int i915_gem_phys_pwrite(struct drm_device *dev, |
46 | struct drm_i915_gem_object *obj, | |
71acb5eb | 47 | struct drm_i915_gem_pwrite *args, |
05394f39 CW |
48 | struct drm_file *file); |
49 | static void i915_gem_free_object_tail(struct drm_i915_gem_object *obj); | |
673a394b | 50 | |
61050808 CW |
51 | static void i915_gem_write_fence(struct drm_device *dev, int reg, |
52 | struct drm_i915_gem_object *obj); | |
53 | static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj, | |
54 | struct drm_i915_fence_reg *fence, | |
55 | bool enable); | |
56 | ||
17250b71 | 57 | static int i915_gem_inactive_shrink(struct shrinker *shrinker, |
1495f230 | 58 | struct shrink_control *sc); |
8c59967c | 59 | static void i915_gem_object_truncate(struct drm_i915_gem_object *obj); |
31169714 | 60 | |
61050808 CW |
61 | static inline void i915_gem_object_fence_lost(struct drm_i915_gem_object *obj) |
62 | { | |
63 | if (obj->tiling_mode) | |
64 | i915_gem_release_mmap(obj); | |
65 | ||
66 | /* As we do not have an associated fence register, we will force | |
67 | * a tiling change if we ever need to acquire one. | |
68 | */ | |
5d82e3e6 | 69 | obj->fence_dirty = false; |
61050808 CW |
70 | obj->fence_reg = I915_FENCE_REG_NONE; |
71 | } | |
72 | ||
73aa808f CW |
73 | /* some bookkeeping */ |
74 | static void i915_gem_info_add_obj(struct drm_i915_private *dev_priv, | |
75 | size_t size) | |
76 | { | |
77 | dev_priv->mm.object_count++; | |
78 | dev_priv->mm.object_memory += size; | |
79 | } | |
80 | ||
81 | static void i915_gem_info_remove_obj(struct drm_i915_private *dev_priv, | |
82 | size_t size) | |
83 | { | |
84 | dev_priv->mm.object_count--; | |
85 | dev_priv->mm.object_memory -= size; | |
86 | } | |
87 | ||
21dd3734 CW |
88 | static int |
89 | i915_gem_wait_for_error(struct drm_device *dev) | |
30dbf0c0 CW |
90 | { |
91 | struct drm_i915_private *dev_priv = dev->dev_private; | |
92 | struct completion *x = &dev_priv->error_completion; | |
93 | unsigned long flags; | |
94 | int ret; | |
95 | ||
96 | if (!atomic_read(&dev_priv->mm.wedged)) | |
97 | return 0; | |
98 | ||
99 | ret = wait_for_completion_interruptible(x); | |
100 | if (ret) | |
101 | return ret; | |
102 | ||
21dd3734 CW |
103 | if (atomic_read(&dev_priv->mm.wedged)) { |
104 | /* GPU is hung, bump the completion count to account for | |
105 | * the token we just consumed so that we never hit zero and | |
106 | * end up waiting upon a subsequent completion event that | |
107 | * will never happen. | |
108 | */ | |
109 | spin_lock_irqsave(&x->wait.lock, flags); | |
110 | x->done++; | |
111 | spin_unlock_irqrestore(&x->wait.lock, flags); | |
112 | } | |
113 | return 0; | |
30dbf0c0 CW |
114 | } |
115 | ||
54cf91dc | 116 | int i915_mutex_lock_interruptible(struct drm_device *dev) |
76c1dec1 | 117 | { |
76c1dec1 CW |
118 | int ret; |
119 | ||
21dd3734 | 120 | ret = i915_gem_wait_for_error(dev); |
76c1dec1 CW |
121 | if (ret) |
122 | return ret; | |
123 | ||
124 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
125 | if (ret) | |
126 | return ret; | |
127 | ||
23bc5982 | 128 | WARN_ON(i915_verify_lists(dev)); |
76c1dec1 CW |
129 | return 0; |
130 | } | |
30dbf0c0 | 131 | |
7d1c4804 | 132 | static inline bool |
05394f39 | 133 | i915_gem_object_is_inactive(struct drm_i915_gem_object *obj) |
7d1c4804 | 134 | { |
8325a09d | 135 | return !obj->active && obj->pin_count == 0; |
7d1c4804 CW |
136 | } |
137 | ||
79e53945 JB |
138 | int |
139 | i915_gem_init_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 140 | struct drm_file *file) |
79e53945 JB |
141 | { |
142 | struct drm_i915_gem_init *args = data; | |
2021746e CW |
143 | |
144 | if (args->gtt_start >= args->gtt_end || | |
145 | (args->gtt_end | args->gtt_start) & (PAGE_SIZE - 1)) | |
146 | return -EINVAL; | |
79e53945 | 147 | |
f534bc0b DV |
148 | /* GEM with user mode setting was never supported on ilk and later. */ |
149 | if (INTEL_INFO(dev)->gen >= 5) | |
150 | return -ENODEV; | |
151 | ||
79e53945 | 152 | mutex_lock(&dev->struct_mutex); |
644ec02b DV |
153 | i915_gem_init_global_gtt(dev, args->gtt_start, |
154 | args->gtt_end, args->gtt_end); | |
673a394b EA |
155 | mutex_unlock(&dev->struct_mutex); |
156 | ||
2021746e | 157 | return 0; |
673a394b EA |
158 | } |
159 | ||
5a125c3c EA |
160 | int |
161 | i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 162 | struct drm_file *file) |
5a125c3c | 163 | { |
73aa808f | 164 | struct drm_i915_private *dev_priv = dev->dev_private; |
5a125c3c | 165 | struct drm_i915_gem_get_aperture *args = data; |
6299f992 CW |
166 | struct drm_i915_gem_object *obj; |
167 | size_t pinned; | |
5a125c3c EA |
168 | |
169 | if (!(dev->driver->driver_features & DRIVER_GEM)) | |
170 | return -ENODEV; | |
171 | ||
6299f992 | 172 | pinned = 0; |
73aa808f | 173 | mutex_lock(&dev->struct_mutex); |
6299f992 CW |
174 | list_for_each_entry(obj, &dev_priv->mm.pinned_list, mm_list) |
175 | pinned += obj->gtt_space->size; | |
73aa808f | 176 | mutex_unlock(&dev->struct_mutex); |
5a125c3c | 177 | |
6299f992 | 178 | args->aper_size = dev_priv->mm.gtt_total; |
0206e353 | 179 | args->aper_available_size = args->aper_size - pinned; |
6299f992 | 180 | |
5a125c3c EA |
181 | return 0; |
182 | } | |
183 | ||
ff72145b DA |
184 | static int |
185 | i915_gem_create(struct drm_file *file, | |
186 | struct drm_device *dev, | |
187 | uint64_t size, | |
188 | uint32_t *handle_p) | |
673a394b | 189 | { |
05394f39 | 190 | struct drm_i915_gem_object *obj; |
a1a2d1d3 PP |
191 | int ret; |
192 | u32 handle; | |
673a394b | 193 | |
ff72145b | 194 | size = roundup(size, PAGE_SIZE); |
8ffc0246 CW |
195 | if (size == 0) |
196 | return -EINVAL; | |
673a394b EA |
197 | |
198 | /* Allocate the new object */ | |
ff72145b | 199 | obj = i915_gem_alloc_object(dev, size); |
673a394b EA |
200 | if (obj == NULL) |
201 | return -ENOMEM; | |
202 | ||
05394f39 | 203 | ret = drm_gem_handle_create(file, &obj->base, &handle); |
1dfd9754 | 204 | if (ret) { |
05394f39 CW |
205 | drm_gem_object_release(&obj->base); |
206 | i915_gem_info_remove_obj(dev->dev_private, obj->base.size); | |
202f2fef | 207 | kfree(obj); |
673a394b | 208 | return ret; |
1dfd9754 | 209 | } |
673a394b | 210 | |
202f2fef | 211 | /* drop reference from allocate - handle holds it now */ |
05394f39 | 212 | drm_gem_object_unreference(&obj->base); |
202f2fef CW |
213 | trace_i915_gem_object_create(obj); |
214 | ||
ff72145b | 215 | *handle_p = handle; |
673a394b EA |
216 | return 0; |
217 | } | |
218 | ||
ff72145b DA |
219 | int |
220 | i915_gem_dumb_create(struct drm_file *file, | |
221 | struct drm_device *dev, | |
222 | struct drm_mode_create_dumb *args) | |
223 | { | |
224 | /* have to work out size/pitch and return them */ | |
ed0291fd | 225 | args->pitch = ALIGN(args->width * ((args->bpp + 7) / 8), 64); |
ff72145b DA |
226 | args->size = args->pitch * args->height; |
227 | return i915_gem_create(file, dev, | |
228 | args->size, &args->handle); | |
229 | } | |
230 | ||
231 | int i915_gem_dumb_destroy(struct drm_file *file, | |
232 | struct drm_device *dev, | |
233 | uint32_t handle) | |
234 | { | |
235 | return drm_gem_handle_delete(file, handle); | |
236 | } | |
237 | ||
238 | /** | |
239 | * Creates a new mm object and returns a handle to it. | |
240 | */ | |
241 | int | |
242 | i915_gem_create_ioctl(struct drm_device *dev, void *data, | |
243 | struct drm_file *file) | |
244 | { | |
245 | struct drm_i915_gem_create *args = data; | |
246 | return i915_gem_create(file, dev, | |
247 | args->size, &args->handle); | |
248 | } | |
249 | ||
05394f39 | 250 | static int i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj) |
280b713b | 251 | { |
05394f39 | 252 | drm_i915_private_t *dev_priv = obj->base.dev->dev_private; |
280b713b EA |
253 | |
254 | return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 && | |
05394f39 | 255 | obj->tiling_mode != I915_TILING_NONE; |
280b713b EA |
256 | } |
257 | ||
8461d226 DV |
258 | static inline int |
259 | __copy_to_user_swizzled(char __user *cpu_vaddr, | |
260 | const char *gpu_vaddr, int gpu_offset, | |
261 | int length) | |
262 | { | |
263 | int ret, cpu_offset = 0; | |
264 | ||
265 | while (length > 0) { | |
266 | int cacheline_end = ALIGN(gpu_offset + 1, 64); | |
267 | int this_length = min(cacheline_end - gpu_offset, length); | |
268 | int swizzled_gpu_offset = gpu_offset ^ 64; | |
269 | ||
270 | ret = __copy_to_user(cpu_vaddr + cpu_offset, | |
271 | gpu_vaddr + swizzled_gpu_offset, | |
272 | this_length); | |
273 | if (ret) | |
274 | return ret + length; | |
275 | ||
276 | cpu_offset += this_length; | |
277 | gpu_offset += this_length; | |
278 | length -= this_length; | |
279 | } | |
280 | ||
281 | return 0; | |
282 | } | |
283 | ||
8c59967c | 284 | static inline int |
4f0c7cfb BW |
285 | __copy_from_user_swizzled(char *gpu_vaddr, int gpu_offset, |
286 | const char __user *cpu_vaddr, | |
8c59967c DV |
287 | int length) |
288 | { | |
289 | int ret, cpu_offset = 0; | |
290 | ||
291 | while (length > 0) { | |
292 | int cacheline_end = ALIGN(gpu_offset + 1, 64); | |
293 | int this_length = min(cacheline_end - gpu_offset, length); | |
294 | int swizzled_gpu_offset = gpu_offset ^ 64; | |
295 | ||
296 | ret = __copy_from_user(gpu_vaddr + swizzled_gpu_offset, | |
297 | cpu_vaddr + cpu_offset, | |
298 | this_length); | |
299 | if (ret) | |
300 | return ret + length; | |
301 | ||
302 | cpu_offset += this_length; | |
303 | gpu_offset += this_length; | |
304 | length -= this_length; | |
305 | } | |
306 | ||
307 | return 0; | |
308 | } | |
309 | ||
d174bd64 DV |
310 | /* Per-page copy function for the shmem pread fastpath. |
311 | * Flushes invalid cachelines before reading the target if | |
312 | * needs_clflush is set. */ | |
eb01459f | 313 | static int |
d174bd64 DV |
314 | shmem_pread_fast(struct page *page, int shmem_page_offset, int page_length, |
315 | char __user *user_data, | |
316 | bool page_do_bit17_swizzling, bool needs_clflush) | |
317 | { | |
318 | char *vaddr; | |
319 | int ret; | |
320 | ||
e7e58eb5 | 321 | if (unlikely(page_do_bit17_swizzling)) |
d174bd64 DV |
322 | return -EINVAL; |
323 | ||
324 | vaddr = kmap_atomic(page); | |
325 | if (needs_clflush) | |
326 | drm_clflush_virt_range(vaddr + shmem_page_offset, | |
327 | page_length); | |
328 | ret = __copy_to_user_inatomic(user_data, | |
329 | vaddr + shmem_page_offset, | |
330 | page_length); | |
331 | kunmap_atomic(vaddr); | |
332 | ||
333 | return ret; | |
334 | } | |
335 | ||
23c18c71 DV |
336 | static void |
337 | shmem_clflush_swizzled_range(char *addr, unsigned long length, | |
338 | bool swizzled) | |
339 | { | |
e7e58eb5 | 340 | if (unlikely(swizzled)) { |
23c18c71 DV |
341 | unsigned long start = (unsigned long) addr; |
342 | unsigned long end = (unsigned long) addr + length; | |
343 | ||
344 | /* For swizzling simply ensure that we always flush both | |
345 | * channels. Lame, but simple and it works. Swizzled | |
346 | * pwrite/pread is far from a hotpath - current userspace | |
347 | * doesn't use it at all. */ | |
348 | start = round_down(start, 128); | |
349 | end = round_up(end, 128); | |
350 | ||
351 | drm_clflush_virt_range((void *)start, end - start); | |
352 | } else { | |
353 | drm_clflush_virt_range(addr, length); | |
354 | } | |
355 | ||
356 | } | |
357 | ||
d174bd64 DV |
358 | /* Only difference to the fast-path function is that this can handle bit17 |
359 | * and uses non-atomic copy and kmap functions. */ | |
360 | static int | |
361 | shmem_pread_slow(struct page *page, int shmem_page_offset, int page_length, | |
362 | char __user *user_data, | |
363 | bool page_do_bit17_swizzling, bool needs_clflush) | |
364 | { | |
365 | char *vaddr; | |
366 | int ret; | |
367 | ||
368 | vaddr = kmap(page); | |
369 | if (needs_clflush) | |
23c18c71 DV |
370 | shmem_clflush_swizzled_range(vaddr + shmem_page_offset, |
371 | page_length, | |
372 | page_do_bit17_swizzling); | |
d174bd64 DV |
373 | |
374 | if (page_do_bit17_swizzling) | |
375 | ret = __copy_to_user_swizzled(user_data, | |
376 | vaddr, shmem_page_offset, | |
377 | page_length); | |
378 | else | |
379 | ret = __copy_to_user(user_data, | |
380 | vaddr + shmem_page_offset, | |
381 | page_length); | |
382 | kunmap(page); | |
383 | ||
384 | return ret; | |
385 | } | |
386 | ||
eb01459f | 387 | static int |
dbf7bff0 DV |
388 | i915_gem_shmem_pread(struct drm_device *dev, |
389 | struct drm_i915_gem_object *obj, | |
390 | struct drm_i915_gem_pread *args, | |
391 | struct drm_file *file) | |
eb01459f | 392 | { |
05394f39 | 393 | struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping; |
8461d226 | 394 | char __user *user_data; |
eb01459f | 395 | ssize_t remain; |
8461d226 | 396 | loff_t offset; |
eb2c0c81 | 397 | int shmem_page_offset, page_length, ret = 0; |
8461d226 | 398 | int obj_do_bit17_swizzling, page_do_bit17_swizzling; |
dbf7bff0 | 399 | int hit_slowpath = 0; |
96d79b52 | 400 | int prefaulted = 0; |
8489731c | 401 | int needs_clflush = 0; |
692a576b | 402 | int release_page; |
eb01459f | 403 | |
8461d226 | 404 | user_data = (char __user *) (uintptr_t) args->data_ptr; |
eb01459f EA |
405 | remain = args->size; |
406 | ||
8461d226 | 407 | obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj); |
eb01459f | 408 | |
8489731c DV |
409 | if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU)) { |
410 | /* If we're not in the cpu read domain, set ourself into the gtt | |
411 | * read domain and manually flush cachelines (if required). This | |
412 | * optimizes for the case when the gpu will dirty the data | |
413 | * anyway again before the next pread happens. */ | |
414 | if (obj->cache_level == I915_CACHE_NONE) | |
415 | needs_clflush = 1; | |
416 | ret = i915_gem_object_set_to_gtt_domain(obj, false); | |
417 | if (ret) | |
418 | return ret; | |
419 | } | |
eb01459f | 420 | |
8461d226 | 421 | offset = args->offset; |
eb01459f EA |
422 | |
423 | while (remain > 0) { | |
e5281ccd CW |
424 | struct page *page; |
425 | ||
eb01459f EA |
426 | /* Operation in this page |
427 | * | |
eb01459f | 428 | * shmem_page_offset = offset within page in shmem file |
eb01459f EA |
429 | * page_length = bytes to copy for this page |
430 | */ | |
c8cbbb8b | 431 | shmem_page_offset = offset_in_page(offset); |
eb01459f EA |
432 | page_length = remain; |
433 | if ((shmem_page_offset + page_length) > PAGE_SIZE) | |
434 | page_length = PAGE_SIZE - shmem_page_offset; | |
eb01459f | 435 | |
692a576b DV |
436 | if (obj->pages) { |
437 | page = obj->pages[offset >> PAGE_SHIFT]; | |
438 | release_page = 0; | |
439 | } else { | |
440 | page = shmem_read_mapping_page(mapping, offset >> PAGE_SHIFT); | |
441 | if (IS_ERR(page)) { | |
442 | ret = PTR_ERR(page); | |
443 | goto out; | |
444 | } | |
445 | release_page = 1; | |
b65552f0 | 446 | } |
e5281ccd | 447 | |
8461d226 DV |
448 | page_do_bit17_swizzling = obj_do_bit17_swizzling && |
449 | (page_to_phys(page) & (1 << 17)) != 0; | |
450 | ||
d174bd64 DV |
451 | ret = shmem_pread_fast(page, shmem_page_offset, page_length, |
452 | user_data, page_do_bit17_swizzling, | |
453 | needs_clflush); | |
454 | if (ret == 0) | |
455 | goto next_page; | |
dbf7bff0 DV |
456 | |
457 | hit_slowpath = 1; | |
692a576b | 458 | page_cache_get(page); |
dbf7bff0 DV |
459 | mutex_unlock(&dev->struct_mutex); |
460 | ||
96d79b52 | 461 | if (!prefaulted) { |
f56f821f | 462 | ret = fault_in_multipages_writeable(user_data, remain); |
96d79b52 DV |
463 | /* Userspace is tricking us, but we've already clobbered |
464 | * its pages with the prefault and promised to write the | |
465 | * data up to the first fault. Hence ignore any errors | |
466 | * and just continue. */ | |
467 | (void)ret; | |
468 | prefaulted = 1; | |
469 | } | |
eb01459f | 470 | |
d174bd64 DV |
471 | ret = shmem_pread_slow(page, shmem_page_offset, page_length, |
472 | user_data, page_do_bit17_swizzling, | |
473 | needs_clflush); | |
eb01459f | 474 | |
dbf7bff0 | 475 | mutex_lock(&dev->struct_mutex); |
e5281ccd | 476 | page_cache_release(page); |
dbf7bff0 | 477 | next_page: |
e5281ccd | 478 | mark_page_accessed(page); |
692a576b DV |
479 | if (release_page) |
480 | page_cache_release(page); | |
e5281ccd | 481 | |
8461d226 DV |
482 | if (ret) { |
483 | ret = -EFAULT; | |
484 | goto out; | |
485 | } | |
486 | ||
eb01459f | 487 | remain -= page_length; |
8461d226 | 488 | user_data += page_length; |
eb01459f EA |
489 | offset += page_length; |
490 | } | |
491 | ||
4f27b75d | 492 | out: |
dbf7bff0 DV |
493 | if (hit_slowpath) { |
494 | /* Fixup: Kill any reinstated backing storage pages */ | |
495 | if (obj->madv == __I915_MADV_PURGED) | |
496 | i915_gem_object_truncate(obj); | |
497 | } | |
eb01459f EA |
498 | |
499 | return ret; | |
500 | } | |
501 | ||
673a394b EA |
502 | /** |
503 | * Reads data from the object referenced by handle. | |
504 | * | |
505 | * On error, the contents of *data are undefined. | |
506 | */ | |
507 | int | |
508 | i915_gem_pread_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 509 | struct drm_file *file) |
673a394b EA |
510 | { |
511 | struct drm_i915_gem_pread *args = data; | |
05394f39 | 512 | struct drm_i915_gem_object *obj; |
35b62a89 | 513 | int ret = 0; |
673a394b | 514 | |
51311d0a CW |
515 | if (args->size == 0) |
516 | return 0; | |
517 | ||
518 | if (!access_ok(VERIFY_WRITE, | |
519 | (char __user *)(uintptr_t)args->data_ptr, | |
520 | args->size)) | |
521 | return -EFAULT; | |
522 | ||
4f27b75d | 523 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 524 | if (ret) |
4f27b75d | 525 | return ret; |
673a394b | 526 | |
05394f39 | 527 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 528 | if (&obj->base == NULL) { |
1d7cfea1 CW |
529 | ret = -ENOENT; |
530 | goto unlock; | |
4f27b75d | 531 | } |
673a394b | 532 | |
7dcd2499 | 533 | /* Bounds check source. */ |
05394f39 CW |
534 | if (args->offset > obj->base.size || |
535 | args->size > obj->base.size - args->offset) { | |
ce9d419d | 536 | ret = -EINVAL; |
35b62a89 | 537 | goto out; |
ce9d419d CW |
538 | } |
539 | ||
db53a302 CW |
540 | trace_i915_gem_object_pread(obj, args->offset, args->size); |
541 | ||
dbf7bff0 | 542 | ret = i915_gem_shmem_pread(dev, obj, args, file); |
673a394b | 543 | |
35b62a89 | 544 | out: |
05394f39 | 545 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 546 | unlock: |
4f27b75d | 547 | mutex_unlock(&dev->struct_mutex); |
eb01459f | 548 | return ret; |
673a394b EA |
549 | } |
550 | ||
0839ccb8 KP |
551 | /* This is the fast write path which cannot handle |
552 | * page faults in the source data | |
9b7530cc | 553 | */ |
0839ccb8 KP |
554 | |
555 | static inline int | |
556 | fast_user_write(struct io_mapping *mapping, | |
557 | loff_t page_base, int page_offset, | |
558 | char __user *user_data, | |
559 | int length) | |
9b7530cc | 560 | { |
4f0c7cfb BW |
561 | void __iomem *vaddr_atomic; |
562 | void *vaddr; | |
0839ccb8 | 563 | unsigned long unwritten; |
9b7530cc | 564 | |
3e4d3af5 | 565 | vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base); |
4f0c7cfb BW |
566 | /* We can use the cpu mem copy function because this is X86. */ |
567 | vaddr = (void __force*)vaddr_atomic + page_offset; | |
568 | unwritten = __copy_from_user_inatomic_nocache(vaddr, | |
0839ccb8 | 569 | user_data, length); |
3e4d3af5 | 570 | io_mapping_unmap_atomic(vaddr_atomic); |
fbd5a26d | 571 | return unwritten; |
0839ccb8 KP |
572 | } |
573 | ||
3de09aa3 EA |
574 | /** |
575 | * This is the fast pwrite path, where we copy the data directly from the | |
576 | * user into the GTT, uncached. | |
577 | */ | |
673a394b | 578 | static int |
05394f39 CW |
579 | i915_gem_gtt_pwrite_fast(struct drm_device *dev, |
580 | struct drm_i915_gem_object *obj, | |
3de09aa3 | 581 | struct drm_i915_gem_pwrite *args, |
05394f39 | 582 | struct drm_file *file) |
673a394b | 583 | { |
0839ccb8 | 584 | drm_i915_private_t *dev_priv = dev->dev_private; |
673a394b | 585 | ssize_t remain; |
0839ccb8 | 586 | loff_t offset, page_base; |
673a394b | 587 | char __user *user_data; |
935aaa69 DV |
588 | int page_offset, page_length, ret; |
589 | ||
590 | ret = i915_gem_object_pin(obj, 0, true); | |
591 | if (ret) | |
592 | goto out; | |
593 | ||
594 | ret = i915_gem_object_set_to_gtt_domain(obj, true); | |
595 | if (ret) | |
596 | goto out_unpin; | |
597 | ||
598 | ret = i915_gem_object_put_fence(obj); | |
599 | if (ret) | |
600 | goto out_unpin; | |
673a394b EA |
601 | |
602 | user_data = (char __user *) (uintptr_t) args->data_ptr; | |
603 | remain = args->size; | |
673a394b | 604 | |
05394f39 | 605 | offset = obj->gtt_offset + args->offset; |
673a394b EA |
606 | |
607 | while (remain > 0) { | |
608 | /* Operation in this page | |
609 | * | |
0839ccb8 KP |
610 | * page_base = page offset within aperture |
611 | * page_offset = offset within page | |
612 | * page_length = bytes to copy for this page | |
673a394b | 613 | */ |
c8cbbb8b CW |
614 | page_base = offset & PAGE_MASK; |
615 | page_offset = offset_in_page(offset); | |
0839ccb8 KP |
616 | page_length = remain; |
617 | if ((page_offset + remain) > PAGE_SIZE) | |
618 | page_length = PAGE_SIZE - page_offset; | |
619 | ||
0839ccb8 | 620 | /* If we get a fault while copying data, then (presumably) our |
3de09aa3 EA |
621 | * source page isn't available. Return the error and we'll |
622 | * retry in the slow path. | |
0839ccb8 | 623 | */ |
fbd5a26d | 624 | if (fast_user_write(dev_priv->mm.gtt_mapping, page_base, |
935aaa69 DV |
625 | page_offset, user_data, page_length)) { |
626 | ret = -EFAULT; | |
627 | goto out_unpin; | |
628 | } | |
673a394b | 629 | |
0839ccb8 KP |
630 | remain -= page_length; |
631 | user_data += page_length; | |
632 | offset += page_length; | |
673a394b | 633 | } |
673a394b | 634 | |
935aaa69 DV |
635 | out_unpin: |
636 | i915_gem_object_unpin(obj); | |
637 | out: | |
3de09aa3 | 638 | return ret; |
673a394b EA |
639 | } |
640 | ||
d174bd64 DV |
641 | /* Per-page copy function for the shmem pwrite fastpath. |
642 | * Flushes invalid cachelines before writing to the target if | |
643 | * needs_clflush_before is set and flushes out any written cachelines after | |
644 | * writing if needs_clflush is set. */ | |
3043c60c | 645 | static int |
d174bd64 DV |
646 | shmem_pwrite_fast(struct page *page, int shmem_page_offset, int page_length, |
647 | char __user *user_data, | |
648 | bool page_do_bit17_swizzling, | |
649 | bool needs_clflush_before, | |
650 | bool needs_clflush_after) | |
673a394b | 651 | { |
d174bd64 | 652 | char *vaddr; |
673a394b | 653 | int ret; |
3de09aa3 | 654 | |
e7e58eb5 | 655 | if (unlikely(page_do_bit17_swizzling)) |
d174bd64 | 656 | return -EINVAL; |
3de09aa3 | 657 | |
d174bd64 DV |
658 | vaddr = kmap_atomic(page); |
659 | if (needs_clflush_before) | |
660 | drm_clflush_virt_range(vaddr + shmem_page_offset, | |
661 | page_length); | |
662 | ret = __copy_from_user_inatomic_nocache(vaddr + shmem_page_offset, | |
663 | user_data, | |
664 | page_length); | |
665 | if (needs_clflush_after) | |
666 | drm_clflush_virt_range(vaddr + shmem_page_offset, | |
667 | page_length); | |
668 | kunmap_atomic(vaddr); | |
3de09aa3 EA |
669 | |
670 | return ret; | |
671 | } | |
672 | ||
d174bd64 DV |
673 | /* Only difference to the fast-path function is that this can handle bit17 |
674 | * and uses non-atomic copy and kmap functions. */ | |
3043c60c | 675 | static int |
d174bd64 DV |
676 | shmem_pwrite_slow(struct page *page, int shmem_page_offset, int page_length, |
677 | char __user *user_data, | |
678 | bool page_do_bit17_swizzling, | |
679 | bool needs_clflush_before, | |
680 | bool needs_clflush_after) | |
673a394b | 681 | { |
d174bd64 DV |
682 | char *vaddr; |
683 | int ret; | |
e5281ccd | 684 | |
d174bd64 | 685 | vaddr = kmap(page); |
e7e58eb5 | 686 | if (unlikely(needs_clflush_before || page_do_bit17_swizzling)) |
23c18c71 DV |
687 | shmem_clflush_swizzled_range(vaddr + shmem_page_offset, |
688 | page_length, | |
689 | page_do_bit17_swizzling); | |
d174bd64 DV |
690 | if (page_do_bit17_swizzling) |
691 | ret = __copy_from_user_swizzled(vaddr, shmem_page_offset, | |
e5281ccd CW |
692 | user_data, |
693 | page_length); | |
d174bd64 DV |
694 | else |
695 | ret = __copy_from_user(vaddr + shmem_page_offset, | |
696 | user_data, | |
697 | page_length); | |
698 | if (needs_clflush_after) | |
23c18c71 DV |
699 | shmem_clflush_swizzled_range(vaddr + shmem_page_offset, |
700 | page_length, | |
701 | page_do_bit17_swizzling); | |
d174bd64 | 702 | kunmap(page); |
40123c1f | 703 | |
d174bd64 | 704 | return ret; |
40123c1f EA |
705 | } |
706 | ||
40123c1f | 707 | static int |
e244a443 DV |
708 | i915_gem_shmem_pwrite(struct drm_device *dev, |
709 | struct drm_i915_gem_object *obj, | |
710 | struct drm_i915_gem_pwrite *args, | |
711 | struct drm_file *file) | |
40123c1f | 712 | { |
05394f39 | 713 | struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping; |
40123c1f | 714 | ssize_t remain; |
8c59967c DV |
715 | loff_t offset; |
716 | char __user *user_data; | |
eb2c0c81 | 717 | int shmem_page_offset, page_length, ret = 0; |
8c59967c | 718 | int obj_do_bit17_swizzling, page_do_bit17_swizzling; |
e244a443 | 719 | int hit_slowpath = 0; |
58642885 DV |
720 | int needs_clflush_after = 0; |
721 | int needs_clflush_before = 0; | |
692a576b | 722 | int release_page; |
40123c1f | 723 | |
8c59967c | 724 | user_data = (char __user *) (uintptr_t) args->data_ptr; |
40123c1f EA |
725 | remain = args->size; |
726 | ||
8c59967c | 727 | obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj); |
40123c1f | 728 | |
58642885 DV |
729 | if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) { |
730 | /* If we're not in the cpu write domain, set ourself into the gtt | |
731 | * write domain and manually flush cachelines (if required). This | |
732 | * optimizes for the case when the gpu will use the data | |
733 | * right away and we therefore have to clflush anyway. */ | |
734 | if (obj->cache_level == I915_CACHE_NONE) | |
735 | needs_clflush_after = 1; | |
736 | ret = i915_gem_object_set_to_gtt_domain(obj, true); | |
737 | if (ret) | |
738 | return ret; | |
739 | } | |
740 | /* Same trick applies for invalidate partially written cachelines before | |
741 | * writing. */ | |
742 | if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU) | |
743 | && obj->cache_level == I915_CACHE_NONE) | |
744 | needs_clflush_before = 1; | |
745 | ||
673a394b | 746 | offset = args->offset; |
05394f39 | 747 | obj->dirty = 1; |
673a394b | 748 | |
40123c1f | 749 | while (remain > 0) { |
e5281ccd | 750 | struct page *page; |
58642885 | 751 | int partial_cacheline_write; |
e5281ccd | 752 | |
40123c1f EA |
753 | /* Operation in this page |
754 | * | |
40123c1f | 755 | * shmem_page_offset = offset within page in shmem file |
40123c1f EA |
756 | * page_length = bytes to copy for this page |
757 | */ | |
c8cbbb8b | 758 | shmem_page_offset = offset_in_page(offset); |
40123c1f EA |
759 | |
760 | page_length = remain; | |
761 | if ((shmem_page_offset + page_length) > PAGE_SIZE) | |
762 | page_length = PAGE_SIZE - shmem_page_offset; | |
40123c1f | 763 | |
58642885 DV |
764 | /* If we don't overwrite a cacheline completely we need to be |
765 | * careful to have up-to-date data by first clflushing. Don't | |
766 | * overcomplicate things and flush the entire patch. */ | |
767 | partial_cacheline_write = needs_clflush_before && | |
768 | ((shmem_page_offset | page_length) | |
769 | & (boot_cpu_data.x86_clflush_size - 1)); | |
770 | ||
692a576b DV |
771 | if (obj->pages) { |
772 | page = obj->pages[offset >> PAGE_SHIFT]; | |
773 | release_page = 0; | |
774 | } else { | |
775 | page = shmem_read_mapping_page(mapping, offset >> PAGE_SHIFT); | |
776 | if (IS_ERR(page)) { | |
777 | ret = PTR_ERR(page); | |
778 | goto out; | |
779 | } | |
780 | release_page = 1; | |
e5281ccd CW |
781 | } |
782 | ||
8c59967c DV |
783 | page_do_bit17_swizzling = obj_do_bit17_swizzling && |
784 | (page_to_phys(page) & (1 << 17)) != 0; | |
785 | ||
d174bd64 DV |
786 | ret = shmem_pwrite_fast(page, shmem_page_offset, page_length, |
787 | user_data, page_do_bit17_swizzling, | |
788 | partial_cacheline_write, | |
789 | needs_clflush_after); | |
790 | if (ret == 0) | |
791 | goto next_page; | |
e244a443 DV |
792 | |
793 | hit_slowpath = 1; | |
692a576b | 794 | page_cache_get(page); |
e244a443 DV |
795 | mutex_unlock(&dev->struct_mutex); |
796 | ||
d174bd64 DV |
797 | ret = shmem_pwrite_slow(page, shmem_page_offset, page_length, |
798 | user_data, page_do_bit17_swizzling, | |
799 | partial_cacheline_write, | |
800 | needs_clflush_after); | |
40123c1f | 801 | |
e244a443 | 802 | mutex_lock(&dev->struct_mutex); |
692a576b | 803 | page_cache_release(page); |
e244a443 | 804 | next_page: |
e5281ccd CW |
805 | set_page_dirty(page); |
806 | mark_page_accessed(page); | |
692a576b DV |
807 | if (release_page) |
808 | page_cache_release(page); | |
e5281ccd | 809 | |
8c59967c DV |
810 | if (ret) { |
811 | ret = -EFAULT; | |
812 | goto out; | |
813 | } | |
814 | ||
40123c1f | 815 | remain -= page_length; |
8c59967c | 816 | user_data += page_length; |
40123c1f | 817 | offset += page_length; |
673a394b EA |
818 | } |
819 | ||
fbd5a26d | 820 | out: |
e244a443 DV |
821 | if (hit_slowpath) { |
822 | /* Fixup: Kill any reinstated backing storage pages */ | |
823 | if (obj->madv == __I915_MADV_PURGED) | |
824 | i915_gem_object_truncate(obj); | |
825 | /* and flush dirty cachelines in case the object isn't in the cpu write | |
826 | * domain anymore. */ | |
827 | if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) { | |
828 | i915_gem_clflush_object(obj); | |
829 | intel_gtt_chipset_flush(); | |
830 | } | |
8c59967c | 831 | } |
673a394b | 832 | |
58642885 DV |
833 | if (needs_clflush_after) |
834 | intel_gtt_chipset_flush(); | |
835 | ||
40123c1f | 836 | return ret; |
673a394b EA |
837 | } |
838 | ||
839 | /** | |
840 | * Writes data to the object referenced by handle. | |
841 | * | |
842 | * On error, the contents of the buffer that were to be modified are undefined. | |
843 | */ | |
844 | int | |
845 | i915_gem_pwrite_ioctl(struct drm_device *dev, void *data, | |
fbd5a26d | 846 | struct drm_file *file) |
673a394b EA |
847 | { |
848 | struct drm_i915_gem_pwrite *args = data; | |
05394f39 | 849 | struct drm_i915_gem_object *obj; |
51311d0a CW |
850 | int ret; |
851 | ||
852 | if (args->size == 0) | |
853 | return 0; | |
854 | ||
855 | if (!access_ok(VERIFY_READ, | |
856 | (char __user *)(uintptr_t)args->data_ptr, | |
857 | args->size)) | |
858 | return -EFAULT; | |
859 | ||
f56f821f DV |
860 | ret = fault_in_multipages_readable((char __user *)(uintptr_t)args->data_ptr, |
861 | args->size); | |
51311d0a CW |
862 | if (ret) |
863 | return -EFAULT; | |
673a394b | 864 | |
fbd5a26d | 865 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 866 | if (ret) |
fbd5a26d | 867 | return ret; |
1d7cfea1 | 868 | |
05394f39 | 869 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 870 | if (&obj->base == NULL) { |
1d7cfea1 CW |
871 | ret = -ENOENT; |
872 | goto unlock; | |
fbd5a26d | 873 | } |
673a394b | 874 | |
7dcd2499 | 875 | /* Bounds check destination. */ |
05394f39 CW |
876 | if (args->offset > obj->base.size || |
877 | args->size > obj->base.size - args->offset) { | |
ce9d419d | 878 | ret = -EINVAL; |
35b62a89 | 879 | goto out; |
ce9d419d CW |
880 | } |
881 | ||
db53a302 CW |
882 | trace_i915_gem_object_pwrite(obj, args->offset, args->size); |
883 | ||
935aaa69 | 884 | ret = -EFAULT; |
673a394b EA |
885 | /* We can only do the GTT pwrite on untiled buffers, as otherwise |
886 | * it would end up going through the fenced access, and we'll get | |
887 | * different detiling behavior between reading and writing. | |
888 | * pread/pwrite currently are reading and writing from the CPU | |
889 | * perspective, requiring manual detiling by the client. | |
890 | */ | |
5c0480f2 | 891 | if (obj->phys_obj) { |
fbd5a26d | 892 | ret = i915_gem_phys_pwrite(dev, obj, args, file); |
5c0480f2 DV |
893 | goto out; |
894 | } | |
895 | ||
896 | if (obj->gtt_space && | |
3ae53783 | 897 | obj->cache_level == I915_CACHE_NONE && |
c07496fa | 898 | obj->tiling_mode == I915_TILING_NONE && |
ffc62976 | 899 | obj->map_and_fenceable && |
5c0480f2 | 900 | obj->base.write_domain != I915_GEM_DOMAIN_CPU) { |
fbd5a26d | 901 | ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file); |
935aaa69 DV |
902 | /* Note that the gtt paths might fail with non-page-backed user |
903 | * pointers (e.g. gtt mappings when moving data between | |
904 | * textures). Fallback to the shmem path in that case. */ | |
fbd5a26d | 905 | } |
673a394b | 906 | |
5c0480f2 | 907 | if (ret == -EFAULT) |
935aaa69 | 908 | ret = i915_gem_shmem_pwrite(dev, obj, args, file); |
5c0480f2 | 909 | |
35b62a89 | 910 | out: |
05394f39 | 911 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 912 | unlock: |
fbd5a26d | 913 | mutex_unlock(&dev->struct_mutex); |
673a394b EA |
914 | return ret; |
915 | } | |
916 | ||
917 | /** | |
2ef7eeaa EA |
918 | * Called when user space prepares to use an object with the CPU, either |
919 | * through the mmap ioctl's mapping or a GTT mapping. | |
673a394b EA |
920 | */ |
921 | int | |
922 | i915_gem_set_domain_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 923 | struct drm_file *file) |
673a394b EA |
924 | { |
925 | struct drm_i915_gem_set_domain *args = data; | |
05394f39 | 926 | struct drm_i915_gem_object *obj; |
2ef7eeaa EA |
927 | uint32_t read_domains = args->read_domains; |
928 | uint32_t write_domain = args->write_domain; | |
673a394b EA |
929 | int ret; |
930 | ||
931 | if (!(dev->driver->driver_features & DRIVER_GEM)) | |
932 | return -ENODEV; | |
933 | ||
2ef7eeaa | 934 | /* Only handle setting domains to types used by the CPU. */ |
21d509e3 | 935 | if (write_domain & I915_GEM_GPU_DOMAINS) |
2ef7eeaa EA |
936 | return -EINVAL; |
937 | ||
21d509e3 | 938 | if (read_domains & I915_GEM_GPU_DOMAINS) |
2ef7eeaa EA |
939 | return -EINVAL; |
940 | ||
941 | /* Having something in the write domain implies it's in the read | |
942 | * domain, and only that read domain. Enforce that in the request. | |
943 | */ | |
944 | if (write_domain != 0 && read_domains != write_domain) | |
945 | return -EINVAL; | |
946 | ||
76c1dec1 | 947 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 948 | if (ret) |
76c1dec1 | 949 | return ret; |
1d7cfea1 | 950 | |
05394f39 | 951 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 952 | if (&obj->base == NULL) { |
1d7cfea1 CW |
953 | ret = -ENOENT; |
954 | goto unlock; | |
76c1dec1 | 955 | } |
673a394b | 956 | |
2ef7eeaa EA |
957 | if (read_domains & I915_GEM_DOMAIN_GTT) { |
958 | ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0); | |
02354392 EA |
959 | |
960 | /* Silently promote "you're not bound, there was nothing to do" | |
961 | * to success, since the client was just asking us to | |
962 | * make sure everything was done. | |
963 | */ | |
964 | if (ret == -EINVAL) | |
965 | ret = 0; | |
2ef7eeaa | 966 | } else { |
e47c68e9 | 967 | ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0); |
2ef7eeaa EA |
968 | } |
969 | ||
05394f39 | 970 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 971 | unlock: |
673a394b EA |
972 | mutex_unlock(&dev->struct_mutex); |
973 | return ret; | |
974 | } | |
975 | ||
976 | /** | |
977 | * Called when user space has done writes to this buffer | |
978 | */ | |
979 | int | |
980 | i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 981 | struct drm_file *file) |
673a394b EA |
982 | { |
983 | struct drm_i915_gem_sw_finish *args = data; | |
05394f39 | 984 | struct drm_i915_gem_object *obj; |
673a394b EA |
985 | int ret = 0; |
986 | ||
987 | if (!(dev->driver->driver_features & DRIVER_GEM)) | |
988 | return -ENODEV; | |
989 | ||
76c1dec1 | 990 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 991 | if (ret) |
76c1dec1 | 992 | return ret; |
1d7cfea1 | 993 | |
05394f39 | 994 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 995 | if (&obj->base == NULL) { |
1d7cfea1 CW |
996 | ret = -ENOENT; |
997 | goto unlock; | |
673a394b EA |
998 | } |
999 | ||
673a394b | 1000 | /* Pinned buffers may be scanout, so flush the cache */ |
05394f39 | 1001 | if (obj->pin_count) |
e47c68e9 EA |
1002 | i915_gem_object_flush_cpu_write_domain(obj); |
1003 | ||
05394f39 | 1004 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 1005 | unlock: |
673a394b EA |
1006 | mutex_unlock(&dev->struct_mutex); |
1007 | return ret; | |
1008 | } | |
1009 | ||
1010 | /** | |
1011 | * Maps the contents of an object, returning the address it is mapped | |
1012 | * into. | |
1013 | * | |
1014 | * While the mapping holds a reference on the contents of the object, it doesn't | |
1015 | * imply a ref on the object itself. | |
1016 | */ | |
1017 | int | |
1018 | i915_gem_mmap_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 1019 | struct drm_file *file) |
673a394b EA |
1020 | { |
1021 | struct drm_i915_gem_mmap *args = data; | |
1022 | struct drm_gem_object *obj; | |
673a394b EA |
1023 | unsigned long addr; |
1024 | ||
1025 | if (!(dev->driver->driver_features & DRIVER_GEM)) | |
1026 | return -ENODEV; | |
1027 | ||
05394f39 | 1028 | obj = drm_gem_object_lookup(dev, file, args->handle); |
673a394b | 1029 | if (obj == NULL) |
bf79cb91 | 1030 | return -ENOENT; |
673a394b | 1031 | |
673a394b EA |
1032 | down_write(¤t->mm->mmap_sem); |
1033 | addr = do_mmap(obj->filp, 0, args->size, | |
1034 | PROT_READ | PROT_WRITE, MAP_SHARED, | |
1035 | args->offset); | |
1036 | up_write(¤t->mm->mmap_sem); | |
bc9025bd | 1037 | drm_gem_object_unreference_unlocked(obj); |
673a394b EA |
1038 | if (IS_ERR((void *)addr)) |
1039 | return addr; | |
1040 | ||
1041 | args->addr_ptr = (uint64_t) addr; | |
1042 | ||
1043 | return 0; | |
1044 | } | |
1045 | ||
de151cf6 JB |
1046 | /** |
1047 | * i915_gem_fault - fault a page into the GTT | |
1048 | * vma: VMA in question | |
1049 | * vmf: fault info | |
1050 | * | |
1051 | * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped | |
1052 | * from userspace. The fault handler takes care of binding the object to | |
1053 | * the GTT (if needed), allocating and programming a fence register (again, | |
1054 | * only if needed based on whether the old reg is still valid or the object | |
1055 | * is tiled) and inserting a new PTE into the faulting process. | |
1056 | * | |
1057 | * Note that the faulting process may involve evicting existing objects | |
1058 | * from the GTT and/or fence registers to make room. So performance may | |
1059 | * suffer if the GTT working set is large or there are few fence registers | |
1060 | * left. | |
1061 | */ | |
1062 | int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf) | |
1063 | { | |
05394f39 CW |
1064 | struct drm_i915_gem_object *obj = to_intel_bo(vma->vm_private_data); |
1065 | struct drm_device *dev = obj->base.dev; | |
7d1c4804 | 1066 | drm_i915_private_t *dev_priv = dev->dev_private; |
de151cf6 JB |
1067 | pgoff_t page_offset; |
1068 | unsigned long pfn; | |
1069 | int ret = 0; | |
0f973f27 | 1070 | bool write = !!(vmf->flags & FAULT_FLAG_WRITE); |
de151cf6 JB |
1071 | |
1072 | /* We don't use vmf->pgoff since that has the fake offset */ | |
1073 | page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >> | |
1074 | PAGE_SHIFT; | |
1075 | ||
d9bc7e9f CW |
1076 | ret = i915_mutex_lock_interruptible(dev); |
1077 | if (ret) | |
1078 | goto out; | |
a00b10c3 | 1079 | |
db53a302 CW |
1080 | trace_i915_gem_object_fault(obj, page_offset, true, write); |
1081 | ||
d9bc7e9f | 1082 | /* Now bind it into the GTT if needed */ |
919926ae CW |
1083 | if (!obj->map_and_fenceable) { |
1084 | ret = i915_gem_object_unbind(obj); | |
1085 | if (ret) | |
1086 | goto unlock; | |
a00b10c3 | 1087 | } |
05394f39 | 1088 | if (!obj->gtt_space) { |
75e9e915 | 1089 | ret = i915_gem_object_bind_to_gtt(obj, 0, true); |
c715089f CW |
1090 | if (ret) |
1091 | goto unlock; | |
de151cf6 | 1092 | |
e92d03bf EA |
1093 | ret = i915_gem_object_set_to_gtt_domain(obj, write); |
1094 | if (ret) | |
1095 | goto unlock; | |
1096 | } | |
4a684a41 | 1097 | |
74898d7e DV |
1098 | if (!obj->has_global_gtt_mapping) |
1099 | i915_gem_gtt_bind_object(obj, obj->cache_level); | |
1100 | ||
06d98131 | 1101 | ret = i915_gem_object_get_fence(obj); |
d9e86c0e CW |
1102 | if (ret) |
1103 | goto unlock; | |
de151cf6 | 1104 | |
05394f39 CW |
1105 | if (i915_gem_object_is_inactive(obj)) |
1106 | list_move_tail(&obj->mm_list, &dev_priv->mm.inactive_list); | |
7d1c4804 | 1107 | |
6299f992 CW |
1108 | obj->fault_mappable = true; |
1109 | ||
05394f39 | 1110 | pfn = ((dev->agp->base + obj->gtt_offset) >> PAGE_SHIFT) + |
de151cf6 JB |
1111 | page_offset; |
1112 | ||
1113 | /* Finally, remap it using the new GTT offset */ | |
1114 | ret = vm_insert_pfn(vma, (unsigned long)vmf->virtual_address, pfn); | |
c715089f | 1115 | unlock: |
de151cf6 | 1116 | mutex_unlock(&dev->struct_mutex); |
d9bc7e9f | 1117 | out: |
de151cf6 | 1118 | switch (ret) { |
d9bc7e9f | 1119 | case -EIO: |
045e769a | 1120 | case -EAGAIN: |
d9bc7e9f CW |
1121 | /* Give the error handler a chance to run and move the |
1122 | * objects off the GPU active list. Next time we service the | |
1123 | * fault, we should be able to transition the page into the | |
1124 | * GTT without touching the GPU (and so avoid further | |
1125 | * EIO/EGAIN). If the GPU is wedged, then there is no issue | |
1126 | * with coherency, just lost writes. | |
1127 | */ | |
045e769a | 1128 | set_need_resched(); |
c715089f CW |
1129 | case 0: |
1130 | case -ERESTARTSYS: | |
bed636ab | 1131 | case -EINTR: |
c715089f | 1132 | return VM_FAULT_NOPAGE; |
de151cf6 | 1133 | case -ENOMEM: |
de151cf6 | 1134 | return VM_FAULT_OOM; |
de151cf6 | 1135 | default: |
c715089f | 1136 | return VM_FAULT_SIGBUS; |
de151cf6 JB |
1137 | } |
1138 | } | |
1139 | ||
901782b2 CW |
1140 | /** |
1141 | * i915_gem_release_mmap - remove physical page mappings | |
1142 | * @obj: obj in question | |
1143 | * | |
af901ca1 | 1144 | * Preserve the reservation of the mmapping with the DRM core code, but |
901782b2 CW |
1145 | * relinquish ownership of the pages back to the system. |
1146 | * | |
1147 | * It is vital that we remove the page mapping if we have mapped a tiled | |
1148 | * object through the GTT and then lose the fence register due to | |
1149 | * resource pressure. Similarly if the object has been moved out of the | |
1150 | * aperture, than pages mapped into userspace must be revoked. Removing the | |
1151 | * mapping will then trigger a page fault on the next user access, allowing | |
1152 | * fixup by i915_gem_fault(). | |
1153 | */ | |
d05ca301 | 1154 | void |
05394f39 | 1155 | i915_gem_release_mmap(struct drm_i915_gem_object *obj) |
901782b2 | 1156 | { |
6299f992 CW |
1157 | if (!obj->fault_mappable) |
1158 | return; | |
901782b2 | 1159 | |
f6e47884 CW |
1160 | if (obj->base.dev->dev_mapping) |
1161 | unmap_mapping_range(obj->base.dev->dev_mapping, | |
1162 | (loff_t)obj->base.map_list.hash.key<<PAGE_SHIFT, | |
1163 | obj->base.size, 1); | |
fb7d516a | 1164 | |
6299f992 | 1165 | obj->fault_mappable = false; |
901782b2 CW |
1166 | } |
1167 | ||
92b88aeb | 1168 | static uint32_t |
e28f8711 | 1169 | i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode) |
92b88aeb | 1170 | { |
e28f8711 | 1171 | uint32_t gtt_size; |
92b88aeb CW |
1172 | |
1173 | if (INTEL_INFO(dev)->gen >= 4 || | |
e28f8711 CW |
1174 | tiling_mode == I915_TILING_NONE) |
1175 | return size; | |
92b88aeb CW |
1176 | |
1177 | /* Previous chips need a power-of-two fence region when tiling */ | |
1178 | if (INTEL_INFO(dev)->gen == 3) | |
e28f8711 | 1179 | gtt_size = 1024*1024; |
92b88aeb | 1180 | else |
e28f8711 | 1181 | gtt_size = 512*1024; |
92b88aeb | 1182 | |
e28f8711 CW |
1183 | while (gtt_size < size) |
1184 | gtt_size <<= 1; | |
92b88aeb | 1185 | |
e28f8711 | 1186 | return gtt_size; |
92b88aeb CW |
1187 | } |
1188 | ||
de151cf6 JB |
1189 | /** |
1190 | * i915_gem_get_gtt_alignment - return required GTT alignment for an object | |
1191 | * @obj: object to check | |
1192 | * | |
1193 | * Return the required GTT alignment for an object, taking into account | |
5e783301 | 1194 | * potential fence register mapping. |
de151cf6 JB |
1195 | */ |
1196 | static uint32_t | |
e28f8711 CW |
1197 | i915_gem_get_gtt_alignment(struct drm_device *dev, |
1198 | uint32_t size, | |
1199 | int tiling_mode) | |
de151cf6 | 1200 | { |
de151cf6 JB |
1201 | /* |
1202 | * Minimum alignment is 4k (GTT page size), but might be greater | |
1203 | * if a fence register is needed for the object. | |
1204 | */ | |
a00b10c3 | 1205 | if (INTEL_INFO(dev)->gen >= 4 || |
e28f8711 | 1206 | tiling_mode == I915_TILING_NONE) |
de151cf6 JB |
1207 | return 4096; |
1208 | ||
a00b10c3 CW |
1209 | /* |
1210 | * Previous chips need to be aligned to the size of the smallest | |
1211 | * fence register that can contain the object. | |
1212 | */ | |
e28f8711 | 1213 | return i915_gem_get_gtt_size(dev, size, tiling_mode); |
a00b10c3 CW |
1214 | } |
1215 | ||
5e783301 DV |
1216 | /** |
1217 | * i915_gem_get_unfenced_gtt_alignment - return required GTT alignment for an | |
1218 | * unfenced object | |
e28f8711 CW |
1219 | * @dev: the device |
1220 | * @size: size of the object | |
1221 | * @tiling_mode: tiling mode of the object | |
5e783301 DV |
1222 | * |
1223 | * Return the required GTT alignment for an object, only taking into account | |
1224 | * unfenced tiled surface requirements. | |
1225 | */ | |
467cffba | 1226 | uint32_t |
e28f8711 CW |
1227 | i915_gem_get_unfenced_gtt_alignment(struct drm_device *dev, |
1228 | uint32_t size, | |
1229 | int tiling_mode) | |
5e783301 | 1230 | { |
5e783301 DV |
1231 | /* |
1232 | * Minimum alignment is 4k (GTT page size) for sane hw. | |
1233 | */ | |
1234 | if (INTEL_INFO(dev)->gen >= 4 || IS_G33(dev) || | |
e28f8711 | 1235 | tiling_mode == I915_TILING_NONE) |
5e783301 DV |
1236 | return 4096; |
1237 | ||
e28f8711 CW |
1238 | /* Previous hardware however needs to be aligned to a power-of-two |
1239 | * tile height. The simplest method for determining this is to reuse | |
1240 | * the power-of-tile object size. | |
5e783301 | 1241 | */ |
e28f8711 | 1242 | return i915_gem_get_gtt_size(dev, size, tiling_mode); |
5e783301 DV |
1243 | } |
1244 | ||
de151cf6 | 1245 | int |
ff72145b DA |
1246 | i915_gem_mmap_gtt(struct drm_file *file, |
1247 | struct drm_device *dev, | |
1248 | uint32_t handle, | |
1249 | uint64_t *offset) | |
de151cf6 | 1250 | { |
da761a6e | 1251 | struct drm_i915_private *dev_priv = dev->dev_private; |
05394f39 | 1252 | struct drm_i915_gem_object *obj; |
de151cf6 JB |
1253 | int ret; |
1254 | ||
1255 | if (!(dev->driver->driver_features & DRIVER_GEM)) | |
1256 | return -ENODEV; | |
1257 | ||
76c1dec1 | 1258 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 1259 | if (ret) |
76c1dec1 | 1260 | return ret; |
de151cf6 | 1261 | |
ff72145b | 1262 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle)); |
c8725226 | 1263 | if (&obj->base == NULL) { |
1d7cfea1 CW |
1264 | ret = -ENOENT; |
1265 | goto unlock; | |
1266 | } | |
de151cf6 | 1267 | |
05394f39 | 1268 | if (obj->base.size > dev_priv->mm.gtt_mappable_end) { |
da761a6e | 1269 | ret = -E2BIG; |
ff56b0bc | 1270 | goto out; |
da761a6e CW |
1271 | } |
1272 | ||
05394f39 | 1273 | if (obj->madv != I915_MADV_WILLNEED) { |
ab18282d | 1274 | DRM_ERROR("Attempting to mmap a purgeable buffer\n"); |
1d7cfea1 CW |
1275 | ret = -EINVAL; |
1276 | goto out; | |
ab18282d CW |
1277 | } |
1278 | ||
05394f39 | 1279 | if (!obj->base.map_list.map) { |
b464e9a2 | 1280 | ret = drm_gem_create_mmap_offset(&obj->base); |
1d7cfea1 CW |
1281 | if (ret) |
1282 | goto out; | |
de151cf6 JB |
1283 | } |
1284 | ||
ff72145b | 1285 | *offset = (u64)obj->base.map_list.hash.key << PAGE_SHIFT; |
de151cf6 | 1286 | |
1d7cfea1 | 1287 | out: |
05394f39 | 1288 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 1289 | unlock: |
de151cf6 | 1290 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 1291 | return ret; |
de151cf6 JB |
1292 | } |
1293 | ||
ff72145b DA |
1294 | /** |
1295 | * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing | |
1296 | * @dev: DRM device | |
1297 | * @data: GTT mapping ioctl data | |
1298 | * @file: GEM object info | |
1299 | * | |
1300 | * Simply returns the fake offset to userspace so it can mmap it. | |
1301 | * The mmap call will end up in drm_gem_mmap(), which will set things | |
1302 | * up so we can get faults in the handler above. | |
1303 | * | |
1304 | * The fault handler will take care of binding the object into the GTT | |
1305 | * (since it may have been evicted to make room for something), allocating | |
1306 | * a fence register, and mapping the appropriate aperture address into | |
1307 | * userspace. | |
1308 | */ | |
1309 | int | |
1310 | i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data, | |
1311 | struct drm_file *file) | |
1312 | { | |
1313 | struct drm_i915_gem_mmap_gtt *args = data; | |
1314 | ||
1315 | if (!(dev->driver->driver_features & DRIVER_GEM)) | |
1316 | return -ENODEV; | |
1317 | ||
1318 | return i915_gem_mmap_gtt(file, dev, args->handle, &args->offset); | |
1319 | } | |
1320 | ||
1321 | ||
e5281ccd | 1322 | static int |
05394f39 | 1323 | i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj, |
e5281ccd CW |
1324 | gfp_t gfpmask) |
1325 | { | |
e5281ccd CW |
1326 | int page_count, i; |
1327 | struct address_space *mapping; | |
1328 | struct inode *inode; | |
1329 | struct page *page; | |
1330 | ||
1331 | /* Get the list of pages out of our struct file. They'll be pinned | |
1332 | * at this point until we release them. | |
1333 | */ | |
05394f39 CW |
1334 | page_count = obj->base.size / PAGE_SIZE; |
1335 | BUG_ON(obj->pages != NULL); | |
1336 | obj->pages = drm_malloc_ab(page_count, sizeof(struct page *)); | |
1337 | if (obj->pages == NULL) | |
e5281ccd CW |
1338 | return -ENOMEM; |
1339 | ||
05394f39 | 1340 | inode = obj->base.filp->f_path.dentry->d_inode; |
e5281ccd | 1341 | mapping = inode->i_mapping; |
5949eac4 HD |
1342 | gfpmask |= mapping_gfp_mask(mapping); |
1343 | ||
e5281ccd | 1344 | for (i = 0; i < page_count; i++) { |
5949eac4 | 1345 | page = shmem_read_mapping_page_gfp(mapping, i, gfpmask); |
e5281ccd CW |
1346 | if (IS_ERR(page)) |
1347 | goto err_pages; | |
1348 | ||
05394f39 | 1349 | obj->pages[i] = page; |
e5281ccd CW |
1350 | } |
1351 | ||
6dacfd2f | 1352 | if (i915_gem_object_needs_bit17_swizzle(obj)) |
e5281ccd CW |
1353 | i915_gem_object_do_bit_17_swizzle(obj); |
1354 | ||
1355 | return 0; | |
1356 | ||
1357 | err_pages: | |
1358 | while (i--) | |
05394f39 | 1359 | page_cache_release(obj->pages[i]); |
e5281ccd | 1360 | |
05394f39 CW |
1361 | drm_free_large(obj->pages); |
1362 | obj->pages = NULL; | |
e5281ccd CW |
1363 | return PTR_ERR(page); |
1364 | } | |
1365 | ||
5cdf5881 | 1366 | static void |
05394f39 | 1367 | i915_gem_object_put_pages_gtt(struct drm_i915_gem_object *obj) |
673a394b | 1368 | { |
05394f39 | 1369 | int page_count = obj->base.size / PAGE_SIZE; |
673a394b EA |
1370 | int i; |
1371 | ||
05394f39 | 1372 | BUG_ON(obj->madv == __I915_MADV_PURGED); |
673a394b | 1373 | |
6dacfd2f | 1374 | if (i915_gem_object_needs_bit17_swizzle(obj)) |
280b713b EA |
1375 | i915_gem_object_save_bit_17_swizzle(obj); |
1376 | ||
05394f39 CW |
1377 | if (obj->madv == I915_MADV_DONTNEED) |
1378 | obj->dirty = 0; | |
3ef94daa CW |
1379 | |
1380 | for (i = 0; i < page_count; i++) { | |
05394f39 CW |
1381 | if (obj->dirty) |
1382 | set_page_dirty(obj->pages[i]); | |
3ef94daa | 1383 | |
05394f39 CW |
1384 | if (obj->madv == I915_MADV_WILLNEED) |
1385 | mark_page_accessed(obj->pages[i]); | |
3ef94daa | 1386 | |
05394f39 | 1387 | page_cache_release(obj->pages[i]); |
3ef94daa | 1388 | } |
05394f39 | 1389 | obj->dirty = 0; |
673a394b | 1390 | |
05394f39 CW |
1391 | drm_free_large(obj->pages); |
1392 | obj->pages = NULL; | |
673a394b EA |
1393 | } |
1394 | ||
54cf91dc | 1395 | void |
05394f39 | 1396 | i915_gem_object_move_to_active(struct drm_i915_gem_object *obj, |
1ec14ad3 CW |
1397 | struct intel_ring_buffer *ring, |
1398 | u32 seqno) | |
673a394b | 1399 | { |
05394f39 | 1400 | struct drm_device *dev = obj->base.dev; |
69dc4987 | 1401 | struct drm_i915_private *dev_priv = dev->dev_private; |
617dbe27 | 1402 | |
852835f3 | 1403 | BUG_ON(ring == NULL); |
05394f39 | 1404 | obj->ring = ring; |
673a394b EA |
1405 | |
1406 | /* Add a reference if we're newly entering the active list. */ | |
05394f39 CW |
1407 | if (!obj->active) { |
1408 | drm_gem_object_reference(&obj->base); | |
1409 | obj->active = 1; | |
673a394b | 1410 | } |
e35a41de | 1411 | |
673a394b | 1412 | /* Move from whatever list we were on to the tail of execution. */ |
05394f39 CW |
1413 | list_move_tail(&obj->mm_list, &dev_priv->mm.active_list); |
1414 | list_move_tail(&obj->ring_list, &ring->active_list); | |
caea7476 | 1415 | |
05394f39 | 1416 | obj->last_rendering_seqno = seqno; |
caea7476 | 1417 | |
7dd49065 | 1418 | if (obj->fenced_gpu_access) { |
caea7476 | 1419 | obj->last_fenced_seqno = seqno; |
caea7476 | 1420 | |
7dd49065 CW |
1421 | /* Bump MRU to take account of the delayed flush */ |
1422 | if (obj->fence_reg != I915_FENCE_REG_NONE) { | |
1423 | struct drm_i915_fence_reg *reg; | |
1424 | ||
1425 | reg = &dev_priv->fence_regs[obj->fence_reg]; | |
1426 | list_move_tail(®->lru_list, | |
1427 | &dev_priv->mm.fence_list); | |
1428 | } | |
caea7476 CW |
1429 | } |
1430 | } | |
1431 | ||
1432 | static void | |
1433 | i915_gem_object_move_off_active(struct drm_i915_gem_object *obj) | |
1434 | { | |
1435 | list_del_init(&obj->ring_list); | |
1436 | obj->last_rendering_seqno = 0; | |
15a13bbd | 1437 | obj->last_fenced_seqno = 0; |
673a394b EA |
1438 | } |
1439 | ||
ce44b0ea | 1440 | static void |
05394f39 | 1441 | i915_gem_object_move_to_flushing(struct drm_i915_gem_object *obj) |
ce44b0ea | 1442 | { |
05394f39 | 1443 | struct drm_device *dev = obj->base.dev; |
ce44b0ea | 1444 | drm_i915_private_t *dev_priv = dev->dev_private; |
ce44b0ea | 1445 | |
05394f39 CW |
1446 | BUG_ON(!obj->active); |
1447 | list_move_tail(&obj->mm_list, &dev_priv->mm.flushing_list); | |
caea7476 CW |
1448 | |
1449 | i915_gem_object_move_off_active(obj); | |
1450 | } | |
1451 | ||
1452 | static void | |
1453 | i915_gem_object_move_to_inactive(struct drm_i915_gem_object *obj) | |
1454 | { | |
1455 | struct drm_device *dev = obj->base.dev; | |
1456 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1457 | ||
1458 | if (obj->pin_count != 0) | |
1459 | list_move_tail(&obj->mm_list, &dev_priv->mm.pinned_list); | |
1460 | else | |
1461 | list_move_tail(&obj->mm_list, &dev_priv->mm.inactive_list); | |
1462 | ||
1463 | BUG_ON(!list_empty(&obj->gpu_write_list)); | |
1464 | BUG_ON(!obj->active); | |
1465 | obj->ring = NULL; | |
1466 | ||
1467 | i915_gem_object_move_off_active(obj); | |
1468 | obj->fenced_gpu_access = false; | |
caea7476 CW |
1469 | |
1470 | obj->active = 0; | |
87ca9c8a | 1471 | obj->pending_gpu_write = false; |
caea7476 CW |
1472 | drm_gem_object_unreference(&obj->base); |
1473 | ||
1474 | WARN_ON(i915_verify_lists(dev)); | |
ce44b0ea | 1475 | } |
673a394b | 1476 | |
963b4836 CW |
1477 | /* Immediately discard the backing storage */ |
1478 | static void | |
05394f39 | 1479 | i915_gem_object_truncate(struct drm_i915_gem_object *obj) |
963b4836 | 1480 | { |
bb6baf76 | 1481 | struct inode *inode; |
963b4836 | 1482 | |
ae9fed6b CW |
1483 | /* Our goal here is to return as much of the memory as |
1484 | * is possible back to the system as we are called from OOM. | |
1485 | * To do this we must instruct the shmfs to drop all of its | |
e2377fe0 | 1486 | * backing pages, *now*. |
ae9fed6b | 1487 | */ |
05394f39 | 1488 | inode = obj->base.filp->f_path.dentry->d_inode; |
e2377fe0 | 1489 | shmem_truncate_range(inode, 0, (loff_t)-1); |
bb6baf76 | 1490 | |
a14917ee CW |
1491 | if (obj->base.map_list.map) |
1492 | drm_gem_free_mmap_offset(&obj->base); | |
1493 | ||
05394f39 | 1494 | obj->madv = __I915_MADV_PURGED; |
963b4836 CW |
1495 | } |
1496 | ||
1497 | static inline int | |
05394f39 | 1498 | i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj) |
963b4836 | 1499 | { |
05394f39 | 1500 | return obj->madv == I915_MADV_DONTNEED; |
963b4836 CW |
1501 | } |
1502 | ||
63560396 | 1503 | static void |
db53a302 CW |
1504 | i915_gem_process_flushing_list(struct intel_ring_buffer *ring, |
1505 | uint32_t flush_domains) | |
63560396 | 1506 | { |
05394f39 | 1507 | struct drm_i915_gem_object *obj, *next; |
63560396 | 1508 | |
05394f39 | 1509 | list_for_each_entry_safe(obj, next, |
64193406 | 1510 | &ring->gpu_write_list, |
63560396 | 1511 | gpu_write_list) { |
05394f39 CW |
1512 | if (obj->base.write_domain & flush_domains) { |
1513 | uint32_t old_write_domain = obj->base.write_domain; | |
63560396 | 1514 | |
05394f39 CW |
1515 | obj->base.write_domain = 0; |
1516 | list_del_init(&obj->gpu_write_list); | |
1ec14ad3 | 1517 | i915_gem_object_move_to_active(obj, ring, |
db53a302 | 1518 | i915_gem_next_request_seqno(ring)); |
63560396 | 1519 | |
63560396 | 1520 | trace_i915_gem_object_change_domain(obj, |
05394f39 | 1521 | obj->base.read_domains, |
63560396 DV |
1522 | old_write_domain); |
1523 | } | |
1524 | } | |
1525 | } | |
8187a2b7 | 1526 | |
53d227f2 DV |
1527 | static u32 |
1528 | i915_gem_get_seqno(struct drm_device *dev) | |
1529 | { | |
1530 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1531 | u32 seqno = dev_priv->next_seqno; | |
1532 | ||
1533 | /* reserve 0 for non-seqno */ | |
1534 | if (++dev_priv->next_seqno == 0) | |
1535 | dev_priv->next_seqno = 1; | |
1536 | ||
1537 | return seqno; | |
1538 | } | |
1539 | ||
1540 | u32 | |
1541 | i915_gem_next_request_seqno(struct intel_ring_buffer *ring) | |
1542 | { | |
1543 | if (ring->outstanding_lazy_request == 0) | |
1544 | ring->outstanding_lazy_request = i915_gem_get_seqno(ring->dev); | |
1545 | ||
1546 | return ring->outstanding_lazy_request; | |
1547 | } | |
1548 | ||
3cce469c | 1549 | int |
db53a302 | 1550 | i915_add_request(struct intel_ring_buffer *ring, |
f787a5f5 | 1551 | struct drm_file *file, |
db53a302 | 1552 | struct drm_i915_gem_request *request) |
673a394b | 1553 | { |
db53a302 | 1554 | drm_i915_private_t *dev_priv = ring->dev->dev_private; |
673a394b | 1555 | uint32_t seqno; |
a71d8d94 | 1556 | u32 request_ring_position; |
673a394b | 1557 | int was_empty; |
3cce469c CW |
1558 | int ret; |
1559 | ||
1560 | BUG_ON(request == NULL); | |
53d227f2 | 1561 | seqno = i915_gem_next_request_seqno(ring); |
673a394b | 1562 | |
a71d8d94 CW |
1563 | /* Record the position of the start of the request so that |
1564 | * should we detect the updated seqno part-way through the | |
1565 | * GPU processing the request, we never over-estimate the | |
1566 | * position of the head. | |
1567 | */ | |
1568 | request_ring_position = intel_ring_get_tail(ring); | |
1569 | ||
3cce469c CW |
1570 | ret = ring->add_request(ring, &seqno); |
1571 | if (ret) | |
1572 | return ret; | |
673a394b | 1573 | |
db53a302 | 1574 | trace_i915_gem_request_add(ring, seqno); |
673a394b EA |
1575 | |
1576 | request->seqno = seqno; | |
852835f3 | 1577 | request->ring = ring; |
a71d8d94 | 1578 | request->tail = request_ring_position; |
673a394b | 1579 | request->emitted_jiffies = jiffies; |
852835f3 ZN |
1580 | was_empty = list_empty(&ring->request_list); |
1581 | list_add_tail(&request->list, &ring->request_list); | |
1582 | ||
db53a302 CW |
1583 | if (file) { |
1584 | struct drm_i915_file_private *file_priv = file->driver_priv; | |
1585 | ||
1c25595f | 1586 | spin_lock(&file_priv->mm.lock); |
f787a5f5 | 1587 | request->file_priv = file_priv; |
b962442e | 1588 | list_add_tail(&request->client_list, |
f787a5f5 | 1589 | &file_priv->mm.request_list); |
1c25595f | 1590 | spin_unlock(&file_priv->mm.lock); |
b962442e | 1591 | } |
673a394b | 1592 | |
5391d0cf | 1593 | ring->outstanding_lazy_request = 0; |
db53a302 | 1594 | |
f65d9421 | 1595 | if (!dev_priv->mm.suspended) { |
3e0dc6b0 BW |
1596 | if (i915_enable_hangcheck) { |
1597 | mod_timer(&dev_priv->hangcheck_timer, | |
1598 | jiffies + | |
1599 | msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)); | |
1600 | } | |
f65d9421 | 1601 | if (was_empty) |
b3b079db CW |
1602 | queue_delayed_work(dev_priv->wq, |
1603 | &dev_priv->mm.retire_work, HZ); | |
f65d9421 | 1604 | } |
3cce469c | 1605 | return 0; |
673a394b EA |
1606 | } |
1607 | ||
f787a5f5 CW |
1608 | static inline void |
1609 | i915_gem_request_remove_from_client(struct drm_i915_gem_request *request) | |
673a394b | 1610 | { |
1c25595f | 1611 | struct drm_i915_file_private *file_priv = request->file_priv; |
673a394b | 1612 | |
1c25595f CW |
1613 | if (!file_priv) |
1614 | return; | |
1c5d22f7 | 1615 | |
1c25595f | 1616 | spin_lock(&file_priv->mm.lock); |
09bfa517 HRK |
1617 | if (request->file_priv) { |
1618 | list_del(&request->client_list); | |
1619 | request->file_priv = NULL; | |
1620 | } | |
1c25595f | 1621 | spin_unlock(&file_priv->mm.lock); |
673a394b | 1622 | } |
673a394b | 1623 | |
dfaae392 CW |
1624 | static void i915_gem_reset_ring_lists(struct drm_i915_private *dev_priv, |
1625 | struct intel_ring_buffer *ring) | |
9375e446 | 1626 | { |
dfaae392 CW |
1627 | while (!list_empty(&ring->request_list)) { |
1628 | struct drm_i915_gem_request *request; | |
673a394b | 1629 | |
dfaae392 CW |
1630 | request = list_first_entry(&ring->request_list, |
1631 | struct drm_i915_gem_request, | |
1632 | list); | |
de151cf6 | 1633 | |
dfaae392 | 1634 | list_del(&request->list); |
f787a5f5 | 1635 | i915_gem_request_remove_from_client(request); |
dfaae392 CW |
1636 | kfree(request); |
1637 | } | |
673a394b | 1638 | |
dfaae392 | 1639 | while (!list_empty(&ring->active_list)) { |
05394f39 | 1640 | struct drm_i915_gem_object *obj; |
9375e446 | 1641 | |
05394f39 CW |
1642 | obj = list_first_entry(&ring->active_list, |
1643 | struct drm_i915_gem_object, | |
1644 | ring_list); | |
9375e446 | 1645 | |
05394f39 CW |
1646 | obj->base.write_domain = 0; |
1647 | list_del_init(&obj->gpu_write_list); | |
1648 | i915_gem_object_move_to_inactive(obj); | |
673a394b EA |
1649 | } |
1650 | } | |
1651 | ||
312817a3 CW |
1652 | static void i915_gem_reset_fences(struct drm_device *dev) |
1653 | { | |
1654 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1655 | int i; | |
1656 | ||
4b9de737 | 1657 | for (i = 0; i < dev_priv->num_fence_regs; i++) { |
312817a3 | 1658 | struct drm_i915_fence_reg *reg = &dev_priv->fence_regs[i]; |
7d2cb39c | 1659 | |
ada726c7 | 1660 | i915_gem_write_fence(dev, i, NULL); |
7d2cb39c | 1661 | |
ada726c7 CW |
1662 | if (reg->obj) |
1663 | i915_gem_object_fence_lost(reg->obj); | |
7d2cb39c | 1664 | |
ada726c7 CW |
1665 | reg->pin_count = 0; |
1666 | reg->obj = NULL; | |
1667 | INIT_LIST_HEAD(®->lru_list); | |
312817a3 | 1668 | } |
ada726c7 CW |
1669 | |
1670 | INIT_LIST_HEAD(&dev_priv->mm.fence_list); | |
312817a3 CW |
1671 | } |
1672 | ||
069efc1d | 1673 | void i915_gem_reset(struct drm_device *dev) |
673a394b | 1674 | { |
77f01230 | 1675 | struct drm_i915_private *dev_priv = dev->dev_private; |
05394f39 | 1676 | struct drm_i915_gem_object *obj; |
1ec14ad3 | 1677 | int i; |
673a394b | 1678 | |
1ec14ad3 CW |
1679 | for (i = 0; i < I915_NUM_RINGS; i++) |
1680 | i915_gem_reset_ring_lists(dev_priv, &dev_priv->ring[i]); | |
dfaae392 CW |
1681 | |
1682 | /* Remove anything from the flushing lists. The GPU cache is likely | |
1683 | * to be lost on reset along with the data, so simply move the | |
1684 | * lost bo to the inactive list. | |
1685 | */ | |
1686 | while (!list_empty(&dev_priv->mm.flushing_list)) { | |
0206e353 | 1687 | obj = list_first_entry(&dev_priv->mm.flushing_list, |
05394f39 CW |
1688 | struct drm_i915_gem_object, |
1689 | mm_list); | |
dfaae392 | 1690 | |
05394f39 CW |
1691 | obj->base.write_domain = 0; |
1692 | list_del_init(&obj->gpu_write_list); | |
1693 | i915_gem_object_move_to_inactive(obj); | |
dfaae392 CW |
1694 | } |
1695 | ||
1696 | /* Move everything out of the GPU domains to ensure we do any | |
1697 | * necessary invalidation upon reuse. | |
1698 | */ | |
05394f39 | 1699 | list_for_each_entry(obj, |
77f01230 | 1700 | &dev_priv->mm.inactive_list, |
69dc4987 | 1701 | mm_list) |
77f01230 | 1702 | { |
05394f39 | 1703 | obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS; |
77f01230 | 1704 | } |
069efc1d CW |
1705 | |
1706 | /* The fence registers are invalidated so clear them out */ | |
312817a3 | 1707 | i915_gem_reset_fences(dev); |
673a394b EA |
1708 | } |
1709 | ||
1710 | /** | |
1711 | * This function clears the request list as sequence numbers are passed. | |
1712 | */ | |
a71d8d94 | 1713 | void |
db53a302 | 1714 | i915_gem_retire_requests_ring(struct intel_ring_buffer *ring) |
673a394b | 1715 | { |
673a394b | 1716 | uint32_t seqno; |
1ec14ad3 | 1717 | int i; |
673a394b | 1718 | |
db53a302 | 1719 | if (list_empty(&ring->request_list)) |
6c0594a3 KW |
1720 | return; |
1721 | ||
db53a302 | 1722 | WARN_ON(i915_verify_lists(ring->dev)); |
673a394b | 1723 | |
78501eac | 1724 | seqno = ring->get_seqno(ring); |
1ec14ad3 | 1725 | |
076e2c0e | 1726 | for (i = 0; i < ARRAY_SIZE(ring->sync_seqno); i++) |
1ec14ad3 CW |
1727 | if (seqno >= ring->sync_seqno[i]) |
1728 | ring->sync_seqno[i] = 0; | |
1729 | ||
852835f3 | 1730 | while (!list_empty(&ring->request_list)) { |
673a394b | 1731 | struct drm_i915_gem_request *request; |
673a394b | 1732 | |
852835f3 | 1733 | request = list_first_entry(&ring->request_list, |
673a394b EA |
1734 | struct drm_i915_gem_request, |
1735 | list); | |
673a394b | 1736 | |
dfaae392 | 1737 | if (!i915_seqno_passed(seqno, request->seqno)) |
b84d5f0c CW |
1738 | break; |
1739 | ||
db53a302 | 1740 | trace_i915_gem_request_retire(ring, request->seqno); |
a71d8d94 CW |
1741 | /* We know the GPU must have read the request to have |
1742 | * sent us the seqno + interrupt, so use the position | |
1743 | * of tail of the request to update the last known position | |
1744 | * of the GPU head. | |
1745 | */ | |
1746 | ring->last_retired_head = request->tail; | |
b84d5f0c CW |
1747 | |
1748 | list_del(&request->list); | |
f787a5f5 | 1749 | i915_gem_request_remove_from_client(request); |
b84d5f0c CW |
1750 | kfree(request); |
1751 | } | |
673a394b | 1752 | |
b84d5f0c CW |
1753 | /* Move any buffers on the active list that are no longer referenced |
1754 | * by the ringbuffer to the flushing/inactive lists as appropriate. | |
1755 | */ | |
1756 | while (!list_empty(&ring->active_list)) { | |
05394f39 | 1757 | struct drm_i915_gem_object *obj; |
b84d5f0c | 1758 | |
0206e353 | 1759 | obj = list_first_entry(&ring->active_list, |
05394f39 CW |
1760 | struct drm_i915_gem_object, |
1761 | ring_list); | |
673a394b | 1762 | |
05394f39 | 1763 | if (!i915_seqno_passed(seqno, obj->last_rendering_seqno)) |
673a394b | 1764 | break; |
b84d5f0c | 1765 | |
05394f39 | 1766 | if (obj->base.write_domain != 0) |
b84d5f0c CW |
1767 | i915_gem_object_move_to_flushing(obj); |
1768 | else | |
1769 | i915_gem_object_move_to_inactive(obj); | |
673a394b | 1770 | } |
9d34e5db | 1771 | |
db53a302 CW |
1772 | if (unlikely(ring->trace_irq_seqno && |
1773 | i915_seqno_passed(seqno, ring->trace_irq_seqno))) { | |
1ec14ad3 | 1774 | ring->irq_put(ring); |
db53a302 | 1775 | ring->trace_irq_seqno = 0; |
9d34e5db | 1776 | } |
23bc5982 | 1777 | |
db53a302 | 1778 | WARN_ON(i915_verify_lists(ring->dev)); |
673a394b EA |
1779 | } |
1780 | ||
b09a1fec CW |
1781 | void |
1782 | i915_gem_retire_requests(struct drm_device *dev) | |
1783 | { | |
1784 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1ec14ad3 | 1785 | int i; |
b09a1fec | 1786 | |
be72615b | 1787 | if (!list_empty(&dev_priv->mm.deferred_free_list)) { |
05394f39 | 1788 | struct drm_i915_gem_object *obj, *next; |
be72615b CW |
1789 | |
1790 | /* We must be careful that during unbind() we do not | |
1791 | * accidentally infinitely recurse into retire requests. | |
1792 | * Currently: | |
1793 | * retire -> free -> unbind -> wait -> retire_ring | |
1794 | */ | |
05394f39 | 1795 | list_for_each_entry_safe(obj, next, |
be72615b | 1796 | &dev_priv->mm.deferred_free_list, |
69dc4987 | 1797 | mm_list) |
05394f39 | 1798 | i915_gem_free_object_tail(obj); |
be72615b CW |
1799 | } |
1800 | ||
1ec14ad3 | 1801 | for (i = 0; i < I915_NUM_RINGS; i++) |
db53a302 | 1802 | i915_gem_retire_requests_ring(&dev_priv->ring[i]); |
b09a1fec CW |
1803 | } |
1804 | ||
75ef9da2 | 1805 | static void |
673a394b EA |
1806 | i915_gem_retire_work_handler(struct work_struct *work) |
1807 | { | |
1808 | drm_i915_private_t *dev_priv; | |
1809 | struct drm_device *dev; | |
0a58705b CW |
1810 | bool idle; |
1811 | int i; | |
673a394b EA |
1812 | |
1813 | dev_priv = container_of(work, drm_i915_private_t, | |
1814 | mm.retire_work.work); | |
1815 | dev = dev_priv->dev; | |
1816 | ||
891b48cf CW |
1817 | /* Come back later if the device is busy... */ |
1818 | if (!mutex_trylock(&dev->struct_mutex)) { | |
1819 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ); | |
1820 | return; | |
1821 | } | |
1822 | ||
b09a1fec | 1823 | i915_gem_retire_requests(dev); |
d1b851fc | 1824 | |
0a58705b CW |
1825 | /* Send a periodic flush down the ring so we don't hold onto GEM |
1826 | * objects indefinitely. | |
1827 | */ | |
1828 | idle = true; | |
1829 | for (i = 0; i < I915_NUM_RINGS; i++) { | |
1830 | struct intel_ring_buffer *ring = &dev_priv->ring[i]; | |
1831 | ||
1832 | if (!list_empty(&ring->gpu_write_list)) { | |
1833 | struct drm_i915_gem_request *request; | |
1834 | int ret; | |
1835 | ||
db53a302 CW |
1836 | ret = i915_gem_flush_ring(ring, |
1837 | 0, I915_GEM_GPU_DOMAINS); | |
0a58705b CW |
1838 | request = kzalloc(sizeof(*request), GFP_KERNEL); |
1839 | if (ret || request == NULL || | |
db53a302 | 1840 | i915_add_request(ring, NULL, request)) |
0a58705b CW |
1841 | kfree(request); |
1842 | } | |
1843 | ||
1844 | idle &= list_empty(&ring->request_list); | |
1845 | } | |
1846 | ||
1847 | if (!dev_priv->mm.suspended && !idle) | |
9c9fe1f8 | 1848 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ); |
0a58705b | 1849 | |
673a394b EA |
1850 | mutex_unlock(&dev->struct_mutex); |
1851 | } | |
1852 | ||
db53a302 CW |
1853 | /** |
1854 | * Waits for a sequence number to be signaled, and cleans up the | |
1855 | * request and object lists appropriately for that event. | |
1856 | */ | |
5a5a0c64 | 1857 | int |
db53a302 | 1858 | i915_wait_request(struct intel_ring_buffer *ring, |
b93f9cf1 BW |
1859 | uint32_t seqno, |
1860 | bool do_retire) | |
673a394b | 1861 | { |
db53a302 | 1862 | drm_i915_private_t *dev_priv = ring->dev->dev_private; |
802c7eb6 | 1863 | u32 ier; |
673a394b EA |
1864 | int ret = 0; |
1865 | ||
1866 | BUG_ON(seqno == 0); | |
1867 | ||
d9bc7e9f CW |
1868 | if (atomic_read(&dev_priv->mm.wedged)) { |
1869 | struct completion *x = &dev_priv->error_completion; | |
1870 | bool recovery_complete; | |
1871 | unsigned long flags; | |
1872 | ||
1873 | /* Give the error handler a chance to run. */ | |
1874 | spin_lock_irqsave(&x->wait.lock, flags); | |
1875 | recovery_complete = x->done > 0; | |
1876 | spin_unlock_irqrestore(&x->wait.lock, flags); | |
1877 | ||
1878 | return recovery_complete ? -EIO : -EAGAIN; | |
1879 | } | |
30dbf0c0 | 1880 | |
5d97eb69 | 1881 | if (seqno == ring->outstanding_lazy_request) { |
3cce469c CW |
1882 | struct drm_i915_gem_request *request; |
1883 | ||
1884 | request = kzalloc(sizeof(*request), GFP_KERNEL); | |
1885 | if (request == NULL) | |
e35a41de | 1886 | return -ENOMEM; |
3cce469c | 1887 | |
db53a302 | 1888 | ret = i915_add_request(ring, NULL, request); |
3cce469c CW |
1889 | if (ret) { |
1890 | kfree(request); | |
1891 | return ret; | |
1892 | } | |
1893 | ||
1894 | seqno = request->seqno; | |
e35a41de | 1895 | } |
ffed1d09 | 1896 | |
78501eac | 1897 | if (!i915_seqno_passed(ring->get_seqno(ring), seqno)) { |
db53a302 | 1898 | if (HAS_PCH_SPLIT(ring->dev)) |
036a4a7d | 1899 | ier = I915_READ(DEIER) | I915_READ(GTIER); |
23e3f9b3 JB |
1900 | else if (IS_VALLEYVIEW(ring->dev)) |
1901 | ier = I915_READ(GTIER) | I915_READ(VLV_IER); | |
036a4a7d ZW |
1902 | else |
1903 | ier = I915_READ(IER); | |
802c7eb6 JB |
1904 | if (!ier) { |
1905 | DRM_ERROR("something (likely vbetool) disabled " | |
1906 | "interrupts, re-enabling\n"); | |
f01c22fd CW |
1907 | ring->dev->driver->irq_preinstall(ring->dev); |
1908 | ring->dev->driver->irq_postinstall(ring->dev); | |
802c7eb6 JB |
1909 | } |
1910 | ||
db53a302 | 1911 | trace_i915_gem_request_wait_begin(ring, seqno); |
1c5d22f7 | 1912 | |
b2223497 | 1913 | ring->waiting_seqno = seqno; |
b13c2b96 | 1914 | if (ring->irq_get(ring)) { |
ce453d81 | 1915 | if (dev_priv->mm.interruptible) |
b13c2b96 CW |
1916 | ret = wait_event_interruptible(ring->irq_queue, |
1917 | i915_seqno_passed(ring->get_seqno(ring), seqno) | |
1918 | || atomic_read(&dev_priv->mm.wedged)); | |
1919 | else | |
1920 | wait_event(ring->irq_queue, | |
1921 | i915_seqno_passed(ring->get_seqno(ring), seqno) | |
1922 | || atomic_read(&dev_priv->mm.wedged)); | |
1923 | ||
1924 | ring->irq_put(ring); | |
e959b5db EA |
1925 | } else if (wait_for_atomic(i915_seqno_passed(ring->get_seqno(ring), |
1926 | seqno) || | |
1927 | atomic_read(&dev_priv->mm.wedged), 3000)) | |
b5ba177d | 1928 | ret = -EBUSY; |
b2223497 | 1929 | ring->waiting_seqno = 0; |
1c5d22f7 | 1930 | |
db53a302 | 1931 | trace_i915_gem_request_wait_end(ring, seqno); |
673a394b | 1932 | } |
ba1234d1 | 1933 | if (atomic_read(&dev_priv->mm.wedged)) |
30dbf0c0 | 1934 | ret = -EAGAIN; |
673a394b | 1935 | |
673a394b EA |
1936 | /* Directly dispatch request retiring. While we have the work queue |
1937 | * to handle this, the waiter on a request often wants an associated | |
1938 | * buffer to have made it to the inactive list, and we would need | |
1939 | * a separate wait queue to handle that. | |
1940 | */ | |
b93f9cf1 | 1941 | if (ret == 0 && do_retire) |
db53a302 | 1942 | i915_gem_retire_requests_ring(ring); |
673a394b EA |
1943 | |
1944 | return ret; | |
1945 | } | |
1946 | ||
673a394b EA |
1947 | /** |
1948 | * Ensures that all rendering to the object has completed and the object is | |
1949 | * safe to unbind from the GTT or access from the CPU. | |
1950 | */ | |
54cf91dc | 1951 | int |
ce453d81 | 1952 | i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj) |
673a394b | 1953 | { |
673a394b EA |
1954 | int ret; |
1955 | ||
e47c68e9 EA |
1956 | /* This function only exists to support waiting for existing rendering, |
1957 | * not for emitting required flushes. | |
673a394b | 1958 | */ |
05394f39 | 1959 | BUG_ON((obj->base.write_domain & I915_GEM_GPU_DOMAINS) != 0); |
673a394b EA |
1960 | |
1961 | /* If there is rendering queued on the buffer being evicted, wait for | |
1962 | * it. | |
1963 | */ | |
05394f39 | 1964 | if (obj->active) { |
b93f9cf1 BW |
1965 | ret = i915_wait_request(obj->ring, obj->last_rendering_seqno, |
1966 | true); | |
2cf34d7b | 1967 | if (ret) |
673a394b EA |
1968 | return ret; |
1969 | } | |
1970 | ||
1971 | return 0; | |
1972 | } | |
1973 | ||
5816d648 BW |
1974 | /** |
1975 | * i915_gem_object_sync - sync an object to a ring. | |
1976 | * | |
1977 | * @obj: object which may be in use on another ring. | |
1978 | * @to: ring we wish to use the object on. May be NULL. | |
1979 | * | |
1980 | * This code is meant to abstract object synchronization with the GPU. | |
1981 | * Calling with NULL implies synchronizing the object with the CPU | |
1982 | * rather than a particular GPU ring. | |
1983 | * | |
1984 | * Returns 0 if successful, else propagates up the lower layer error. | |
1985 | */ | |
2911a35b BW |
1986 | int |
1987 | i915_gem_object_sync(struct drm_i915_gem_object *obj, | |
1988 | struct intel_ring_buffer *to) | |
1989 | { | |
1990 | struct intel_ring_buffer *from = obj->ring; | |
1991 | u32 seqno; | |
1992 | int ret, idx; | |
1993 | ||
1994 | if (from == NULL || to == from) | |
1995 | return 0; | |
1996 | ||
5816d648 | 1997 | if (to == NULL || !i915_semaphore_is_enabled(obj->base.dev)) |
2911a35b BW |
1998 | return i915_gem_object_wait_rendering(obj); |
1999 | ||
2000 | idx = intel_ring_sync_index(from, to); | |
2001 | ||
2002 | seqno = obj->last_rendering_seqno; | |
2003 | if (seqno <= from->sync_seqno[idx]) | |
2004 | return 0; | |
2005 | ||
2006 | if (seqno == from->outstanding_lazy_request) { | |
2007 | struct drm_i915_gem_request *request; | |
2008 | ||
2009 | request = kzalloc(sizeof(*request), GFP_KERNEL); | |
2010 | if (request == NULL) | |
2011 | return -ENOMEM; | |
2012 | ||
2013 | ret = i915_add_request(from, NULL, request); | |
2014 | if (ret) { | |
2015 | kfree(request); | |
2016 | return ret; | |
2017 | } | |
2018 | ||
2019 | seqno = request->seqno; | |
2020 | } | |
2021 | ||
2911a35b | 2022 | |
1500f7ea | 2023 | ret = to->sync_to(to, from, seqno); |
e3a5a225 BW |
2024 | if (!ret) |
2025 | from->sync_seqno[idx] = seqno; | |
2911a35b | 2026 | |
e3a5a225 | 2027 | return ret; |
2911a35b BW |
2028 | } |
2029 | ||
b5ffc9bc CW |
2030 | static void i915_gem_object_finish_gtt(struct drm_i915_gem_object *obj) |
2031 | { | |
2032 | u32 old_write_domain, old_read_domains; | |
2033 | ||
b5ffc9bc CW |
2034 | /* Act a barrier for all accesses through the GTT */ |
2035 | mb(); | |
2036 | ||
2037 | /* Force a pagefault for domain tracking on next user access */ | |
2038 | i915_gem_release_mmap(obj); | |
2039 | ||
b97c3d9c KP |
2040 | if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0) |
2041 | return; | |
2042 | ||
b5ffc9bc CW |
2043 | old_read_domains = obj->base.read_domains; |
2044 | old_write_domain = obj->base.write_domain; | |
2045 | ||
2046 | obj->base.read_domains &= ~I915_GEM_DOMAIN_GTT; | |
2047 | obj->base.write_domain &= ~I915_GEM_DOMAIN_GTT; | |
2048 | ||
2049 | trace_i915_gem_object_change_domain(obj, | |
2050 | old_read_domains, | |
2051 | old_write_domain); | |
2052 | } | |
2053 | ||
673a394b EA |
2054 | /** |
2055 | * Unbinds an object from the GTT aperture. | |
2056 | */ | |
0f973f27 | 2057 | int |
05394f39 | 2058 | i915_gem_object_unbind(struct drm_i915_gem_object *obj) |
673a394b | 2059 | { |
7bddb01f | 2060 | drm_i915_private_t *dev_priv = obj->base.dev->dev_private; |
673a394b EA |
2061 | int ret = 0; |
2062 | ||
05394f39 | 2063 | if (obj->gtt_space == NULL) |
673a394b EA |
2064 | return 0; |
2065 | ||
05394f39 | 2066 | if (obj->pin_count != 0) { |
673a394b EA |
2067 | DRM_ERROR("Attempting to unbind pinned buffer\n"); |
2068 | return -EINVAL; | |
2069 | } | |
2070 | ||
a8198eea CW |
2071 | ret = i915_gem_object_finish_gpu(obj); |
2072 | if (ret == -ERESTARTSYS) | |
2073 | return ret; | |
2074 | /* Continue on if we fail due to EIO, the GPU is hung so we | |
2075 | * should be safe and we need to cleanup or else we might | |
2076 | * cause memory corruption through use-after-free. | |
2077 | */ | |
2078 | ||
b5ffc9bc | 2079 | i915_gem_object_finish_gtt(obj); |
5323fd04 | 2080 | |
673a394b EA |
2081 | /* Move the object to the CPU domain to ensure that |
2082 | * any possible CPU writes while it's not in the GTT | |
a8198eea | 2083 | * are flushed when we go to remap it. |
673a394b | 2084 | */ |
a8198eea CW |
2085 | if (ret == 0) |
2086 | ret = i915_gem_object_set_to_cpu_domain(obj, 1); | |
8dc1775d | 2087 | if (ret == -ERESTARTSYS) |
673a394b | 2088 | return ret; |
812ed492 | 2089 | if (ret) { |
a8198eea CW |
2090 | /* In the event of a disaster, abandon all caches and |
2091 | * hope for the best. | |
2092 | */ | |
812ed492 | 2093 | i915_gem_clflush_object(obj); |
05394f39 | 2094 | obj->base.read_domains = obj->base.write_domain = I915_GEM_DOMAIN_CPU; |
812ed492 | 2095 | } |
673a394b | 2096 | |
96b47b65 | 2097 | /* release the fence reg _after_ flushing */ |
d9e86c0e CW |
2098 | ret = i915_gem_object_put_fence(obj); |
2099 | if (ret == -ERESTARTSYS) | |
2100 | return ret; | |
96b47b65 | 2101 | |
db53a302 CW |
2102 | trace_i915_gem_object_unbind(obj); |
2103 | ||
74898d7e DV |
2104 | if (obj->has_global_gtt_mapping) |
2105 | i915_gem_gtt_unbind_object(obj); | |
7bddb01f DV |
2106 | if (obj->has_aliasing_ppgtt_mapping) { |
2107 | i915_ppgtt_unbind_object(dev_priv->mm.aliasing_ppgtt, obj); | |
2108 | obj->has_aliasing_ppgtt_mapping = 0; | |
2109 | } | |
74163907 | 2110 | i915_gem_gtt_finish_object(obj); |
7bddb01f | 2111 | |
e5281ccd | 2112 | i915_gem_object_put_pages_gtt(obj); |
673a394b | 2113 | |
6299f992 | 2114 | list_del_init(&obj->gtt_list); |
05394f39 | 2115 | list_del_init(&obj->mm_list); |
75e9e915 | 2116 | /* Avoid an unnecessary call to unbind on rebind. */ |
05394f39 | 2117 | obj->map_and_fenceable = true; |
673a394b | 2118 | |
05394f39 CW |
2119 | drm_mm_put_block(obj->gtt_space); |
2120 | obj->gtt_space = NULL; | |
2121 | obj->gtt_offset = 0; | |
673a394b | 2122 | |
05394f39 | 2123 | if (i915_gem_object_is_purgeable(obj)) |
963b4836 CW |
2124 | i915_gem_object_truncate(obj); |
2125 | ||
8dc1775d | 2126 | return ret; |
673a394b EA |
2127 | } |
2128 | ||
88241785 | 2129 | int |
db53a302 | 2130 | i915_gem_flush_ring(struct intel_ring_buffer *ring, |
54cf91dc CW |
2131 | uint32_t invalidate_domains, |
2132 | uint32_t flush_domains) | |
2133 | { | |
88241785 CW |
2134 | int ret; |
2135 | ||
36d527de CW |
2136 | if (((invalidate_domains | flush_domains) & I915_GEM_GPU_DOMAINS) == 0) |
2137 | return 0; | |
2138 | ||
db53a302 CW |
2139 | trace_i915_gem_ring_flush(ring, invalidate_domains, flush_domains); |
2140 | ||
88241785 CW |
2141 | ret = ring->flush(ring, invalidate_domains, flush_domains); |
2142 | if (ret) | |
2143 | return ret; | |
2144 | ||
36d527de CW |
2145 | if (flush_domains & I915_GEM_GPU_DOMAINS) |
2146 | i915_gem_process_flushing_list(ring, flush_domains); | |
2147 | ||
88241785 | 2148 | return 0; |
54cf91dc CW |
2149 | } |
2150 | ||
b93f9cf1 | 2151 | static int i915_ring_idle(struct intel_ring_buffer *ring, bool do_retire) |
a56ba56c | 2152 | { |
88241785 CW |
2153 | int ret; |
2154 | ||
395b70be | 2155 | if (list_empty(&ring->gpu_write_list) && list_empty(&ring->active_list)) |
64193406 CW |
2156 | return 0; |
2157 | ||
88241785 | 2158 | if (!list_empty(&ring->gpu_write_list)) { |
db53a302 | 2159 | ret = i915_gem_flush_ring(ring, |
0ac74c6b | 2160 | I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS); |
88241785 CW |
2161 | if (ret) |
2162 | return ret; | |
2163 | } | |
2164 | ||
b93f9cf1 BW |
2165 | return i915_wait_request(ring, i915_gem_next_request_seqno(ring), |
2166 | do_retire); | |
a56ba56c CW |
2167 | } |
2168 | ||
b93f9cf1 | 2169 | int i915_gpu_idle(struct drm_device *dev, bool do_retire) |
4df2faf4 DV |
2170 | { |
2171 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1ec14ad3 | 2172 | int ret, i; |
4df2faf4 | 2173 | |
4df2faf4 | 2174 | /* Flush everything onto the inactive list. */ |
1ec14ad3 | 2175 | for (i = 0; i < I915_NUM_RINGS; i++) { |
b93f9cf1 | 2176 | ret = i915_ring_idle(&dev_priv->ring[i], do_retire); |
1ec14ad3 CW |
2177 | if (ret) |
2178 | return ret; | |
2179 | } | |
4df2faf4 | 2180 | |
8a1a49f9 | 2181 | return 0; |
4df2faf4 DV |
2182 | } |
2183 | ||
9ce079e4 CW |
2184 | static void sandybridge_write_fence_reg(struct drm_device *dev, int reg, |
2185 | struct drm_i915_gem_object *obj) | |
4e901fdc | 2186 | { |
4e901fdc | 2187 | drm_i915_private_t *dev_priv = dev->dev_private; |
4e901fdc EA |
2188 | uint64_t val; |
2189 | ||
9ce079e4 CW |
2190 | if (obj) { |
2191 | u32 size = obj->gtt_space->size; | |
4e901fdc | 2192 | |
9ce079e4 CW |
2193 | val = (uint64_t)((obj->gtt_offset + size - 4096) & |
2194 | 0xfffff000) << 32; | |
2195 | val |= obj->gtt_offset & 0xfffff000; | |
2196 | val |= (uint64_t)((obj->stride / 128) - 1) << | |
2197 | SANDYBRIDGE_FENCE_PITCH_SHIFT; | |
4e901fdc | 2198 | |
9ce079e4 CW |
2199 | if (obj->tiling_mode == I915_TILING_Y) |
2200 | val |= 1 << I965_FENCE_TILING_Y_SHIFT; | |
2201 | val |= I965_FENCE_REG_VALID; | |
2202 | } else | |
2203 | val = 0; | |
c6642782 | 2204 | |
9ce079e4 CW |
2205 | I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + reg * 8, val); |
2206 | POSTING_READ(FENCE_REG_SANDYBRIDGE_0 + reg * 8); | |
4e901fdc EA |
2207 | } |
2208 | ||
9ce079e4 CW |
2209 | static void i965_write_fence_reg(struct drm_device *dev, int reg, |
2210 | struct drm_i915_gem_object *obj) | |
de151cf6 | 2211 | { |
de151cf6 | 2212 | drm_i915_private_t *dev_priv = dev->dev_private; |
de151cf6 JB |
2213 | uint64_t val; |
2214 | ||
9ce079e4 CW |
2215 | if (obj) { |
2216 | u32 size = obj->gtt_space->size; | |
de151cf6 | 2217 | |
9ce079e4 CW |
2218 | val = (uint64_t)((obj->gtt_offset + size - 4096) & |
2219 | 0xfffff000) << 32; | |
2220 | val |= obj->gtt_offset & 0xfffff000; | |
2221 | val |= ((obj->stride / 128) - 1) << I965_FENCE_PITCH_SHIFT; | |
2222 | if (obj->tiling_mode == I915_TILING_Y) | |
2223 | val |= 1 << I965_FENCE_TILING_Y_SHIFT; | |
2224 | val |= I965_FENCE_REG_VALID; | |
2225 | } else | |
2226 | val = 0; | |
c6642782 | 2227 | |
9ce079e4 CW |
2228 | I915_WRITE64(FENCE_REG_965_0 + reg * 8, val); |
2229 | POSTING_READ(FENCE_REG_965_0 + reg * 8); | |
de151cf6 JB |
2230 | } |
2231 | ||
9ce079e4 CW |
2232 | static void i915_write_fence_reg(struct drm_device *dev, int reg, |
2233 | struct drm_i915_gem_object *obj) | |
de151cf6 | 2234 | { |
de151cf6 | 2235 | drm_i915_private_t *dev_priv = dev->dev_private; |
9ce079e4 | 2236 | u32 val; |
de151cf6 | 2237 | |
9ce079e4 CW |
2238 | if (obj) { |
2239 | u32 size = obj->gtt_space->size; | |
2240 | int pitch_val; | |
2241 | int tile_width; | |
c6642782 | 2242 | |
9ce079e4 CW |
2243 | WARN((obj->gtt_offset & ~I915_FENCE_START_MASK) || |
2244 | (size & -size) != size || | |
2245 | (obj->gtt_offset & (size - 1)), | |
2246 | "object 0x%08x [fenceable? %d] not 1M or pot-size (0x%08x) aligned\n", | |
2247 | obj->gtt_offset, obj->map_and_fenceable, size); | |
c6642782 | 2248 | |
9ce079e4 CW |
2249 | if (obj->tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev)) |
2250 | tile_width = 128; | |
2251 | else | |
2252 | tile_width = 512; | |
2253 | ||
2254 | /* Note: pitch better be a power of two tile widths */ | |
2255 | pitch_val = obj->stride / tile_width; | |
2256 | pitch_val = ffs(pitch_val) - 1; | |
2257 | ||
2258 | val = obj->gtt_offset; | |
2259 | if (obj->tiling_mode == I915_TILING_Y) | |
2260 | val |= 1 << I830_FENCE_TILING_Y_SHIFT; | |
2261 | val |= I915_FENCE_SIZE_BITS(size); | |
2262 | val |= pitch_val << I830_FENCE_PITCH_SHIFT; | |
2263 | val |= I830_FENCE_REG_VALID; | |
2264 | } else | |
2265 | val = 0; | |
2266 | ||
2267 | if (reg < 8) | |
2268 | reg = FENCE_REG_830_0 + reg * 4; | |
2269 | else | |
2270 | reg = FENCE_REG_945_8 + (reg - 8) * 4; | |
2271 | ||
2272 | I915_WRITE(reg, val); | |
2273 | POSTING_READ(reg); | |
de151cf6 JB |
2274 | } |
2275 | ||
9ce079e4 CW |
2276 | static void i830_write_fence_reg(struct drm_device *dev, int reg, |
2277 | struct drm_i915_gem_object *obj) | |
de151cf6 | 2278 | { |
de151cf6 | 2279 | drm_i915_private_t *dev_priv = dev->dev_private; |
de151cf6 | 2280 | uint32_t val; |
de151cf6 | 2281 | |
9ce079e4 CW |
2282 | if (obj) { |
2283 | u32 size = obj->gtt_space->size; | |
2284 | uint32_t pitch_val; | |
de151cf6 | 2285 | |
9ce079e4 CW |
2286 | WARN((obj->gtt_offset & ~I830_FENCE_START_MASK) || |
2287 | (size & -size) != size || | |
2288 | (obj->gtt_offset & (size - 1)), | |
2289 | "object 0x%08x not 512K or pot-size 0x%08x aligned\n", | |
2290 | obj->gtt_offset, size); | |
e76a16de | 2291 | |
9ce079e4 CW |
2292 | pitch_val = obj->stride / 128; |
2293 | pitch_val = ffs(pitch_val) - 1; | |
de151cf6 | 2294 | |
9ce079e4 CW |
2295 | val = obj->gtt_offset; |
2296 | if (obj->tiling_mode == I915_TILING_Y) | |
2297 | val |= 1 << I830_FENCE_TILING_Y_SHIFT; | |
2298 | val |= I830_FENCE_SIZE_BITS(size); | |
2299 | val |= pitch_val << I830_FENCE_PITCH_SHIFT; | |
2300 | val |= I830_FENCE_REG_VALID; | |
2301 | } else | |
2302 | val = 0; | |
c6642782 | 2303 | |
9ce079e4 CW |
2304 | I915_WRITE(FENCE_REG_830_0 + reg * 4, val); |
2305 | POSTING_READ(FENCE_REG_830_0 + reg * 4); | |
2306 | } | |
2307 | ||
2308 | static void i915_gem_write_fence(struct drm_device *dev, int reg, | |
2309 | struct drm_i915_gem_object *obj) | |
2310 | { | |
2311 | switch (INTEL_INFO(dev)->gen) { | |
2312 | case 7: | |
2313 | case 6: sandybridge_write_fence_reg(dev, reg, obj); break; | |
2314 | case 5: | |
2315 | case 4: i965_write_fence_reg(dev, reg, obj); break; | |
2316 | case 3: i915_write_fence_reg(dev, reg, obj); break; | |
2317 | case 2: i830_write_fence_reg(dev, reg, obj); break; | |
2318 | default: break; | |
2319 | } | |
de151cf6 JB |
2320 | } |
2321 | ||
61050808 CW |
2322 | static inline int fence_number(struct drm_i915_private *dev_priv, |
2323 | struct drm_i915_fence_reg *fence) | |
2324 | { | |
2325 | return fence - dev_priv->fence_regs; | |
2326 | } | |
2327 | ||
2328 | static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj, | |
2329 | struct drm_i915_fence_reg *fence, | |
2330 | bool enable) | |
2331 | { | |
2332 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; | |
2333 | int reg = fence_number(dev_priv, fence); | |
2334 | ||
2335 | i915_gem_write_fence(obj->base.dev, reg, enable ? obj : NULL); | |
2336 | ||
2337 | if (enable) { | |
2338 | obj->fence_reg = reg; | |
2339 | fence->obj = obj; | |
2340 | list_move_tail(&fence->lru_list, &dev_priv->mm.fence_list); | |
2341 | } else { | |
2342 | obj->fence_reg = I915_FENCE_REG_NONE; | |
2343 | fence->obj = NULL; | |
2344 | list_del_init(&fence->lru_list); | |
2345 | } | |
2346 | } | |
2347 | ||
d9e86c0e | 2348 | static int |
a360bb1a | 2349 | i915_gem_object_flush_fence(struct drm_i915_gem_object *obj) |
d9e86c0e CW |
2350 | { |
2351 | int ret; | |
2352 | ||
2353 | if (obj->fenced_gpu_access) { | |
88241785 | 2354 | if (obj->base.write_domain & I915_GEM_GPU_DOMAINS) { |
1c293ea3 | 2355 | ret = i915_gem_flush_ring(obj->ring, |
88241785 CW |
2356 | 0, obj->base.write_domain); |
2357 | if (ret) | |
2358 | return ret; | |
2359 | } | |
d9e86c0e CW |
2360 | |
2361 | obj->fenced_gpu_access = false; | |
2362 | } | |
2363 | ||
1c293ea3 | 2364 | if (obj->last_fenced_seqno) { |
18991845 CW |
2365 | ret = i915_wait_request(obj->ring, |
2366 | obj->last_fenced_seqno, | |
14415745 | 2367 | false); |
18991845 CW |
2368 | if (ret) |
2369 | return ret; | |
d9e86c0e CW |
2370 | |
2371 | obj->last_fenced_seqno = 0; | |
d9e86c0e CW |
2372 | } |
2373 | ||
63256ec5 CW |
2374 | /* Ensure that all CPU reads are completed before installing a fence |
2375 | * and all writes before removing the fence. | |
2376 | */ | |
2377 | if (obj->base.read_domains & I915_GEM_DOMAIN_GTT) | |
2378 | mb(); | |
2379 | ||
d9e86c0e CW |
2380 | return 0; |
2381 | } | |
2382 | ||
2383 | int | |
2384 | i915_gem_object_put_fence(struct drm_i915_gem_object *obj) | |
2385 | { | |
61050808 | 2386 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
d9e86c0e CW |
2387 | int ret; |
2388 | ||
a360bb1a | 2389 | ret = i915_gem_object_flush_fence(obj); |
d9e86c0e CW |
2390 | if (ret) |
2391 | return ret; | |
2392 | ||
61050808 CW |
2393 | if (obj->fence_reg == I915_FENCE_REG_NONE) |
2394 | return 0; | |
d9e86c0e | 2395 | |
61050808 CW |
2396 | i915_gem_object_update_fence(obj, |
2397 | &dev_priv->fence_regs[obj->fence_reg], | |
2398 | false); | |
2399 | i915_gem_object_fence_lost(obj); | |
d9e86c0e CW |
2400 | |
2401 | return 0; | |
2402 | } | |
2403 | ||
2404 | static struct drm_i915_fence_reg * | |
a360bb1a | 2405 | i915_find_fence_reg(struct drm_device *dev) |
ae3db24a | 2406 | { |
ae3db24a | 2407 | struct drm_i915_private *dev_priv = dev->dev_private; |
8fe301ad | 2408 | struct drm_i915_fence_reg *reg, *avail; |
d9e86c0e | 2409 | int i; |
ae3db24a DV |
2410 | |
2411 | /* First try to find a free reg */ | |
d9e86c0e | 2412 | avail = NULL; |
ae3db24a DV |
2413 | for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) { |
2414 | reg = &dev_priv->fence_regs[i]; | |
2415 | if (!reg->obj) | |
d9e86c0e | 2416 | return reg; |
ae3db24a | 2417 | |
1690e1eb | 2418 | if (!reg->pin_count) |
d9e86c0e | 2419 | avail = reg; |
ae3db24a DV |
2420 | } |
2421 | ||
d9e86c0e CW |
2422 | if (avail == NULL) |
2423 | return NULL; | |
ae3db24a DV |
2424 | |
2425 | /* None available, try to steal one or wait for a user to finish */ | |
d9e86c0e | 2426 | list_for_each_entry(reg, &dev_priv->mm.fence_list, lru_list) { |
1690e1eb | 2427 | if (reg->pin_count) |
ae3db24a DV |
2428 | continue; |
2429 | ||
8fe301ad | 2430 | return reg; |
ae3db24a DV |
2431 | } |
2432 | ||
8fe301ad | 2433 | return NULL; |
ae3db24a DV |
2434 | } |
2435 | ||
de151cf6 | 2436 | /** |
9a5a53b3 | 2437 | * i915_gem_object_get_fence - set up fencing for an object |
de151cf6 JB |
2438 | * @obj: object to map through a fence reg |
2439 | * | |
2440 | * When mapping objects through the GTT, userspace wants to be able to write | |
2441 | * to them without having to worry about swizzling if the object is tiled. | |
de151cf6 JB |
2442 | * This function walks the fence regs looking for a free one for @obj, |
2443 | * stealing one if it can't find any. | |
2444 | * | |
2445 | * It then sets up the reg based on the object's properties: address, pitch | |
2446 | * and tiling format. | |
9a5a53b3 CW |
2447 | * |
2448 | * For an untiled surface, this removes any existing fence. | |
de151cf6 | 2449 | */ |
8c4b8c3f | 2450 | int |
06d98131 | 2451 | i915_gem_object_get_fence(struct drm_i915_gem_object *obj) |
de151cf6 | 2452 | { |
05394f39 | 2453 | struct drm_device *dev = obj->base.dev; |
79e53945 | 2454 | struct drm_i915_private *dev_priv = dev->dev_private; |
14415745 | 2455 | bool enable = obj->tiling_mode != I915_TILING_NONE; |
d9e86c0e | 2456 | struct drm_i915_fence_reg *reg; |
ae3db24a | 2457 | int ret; |
de151cf6 | 2458 | |
14415745 CW |
2459 | /* Have we updated the tiling parameters upon the object and so |
2460 | * will need to serialise the write to the associated fence register? | |
2461 | */ | |
5d82e3e6 | 2462 | if (obj->fence_dirty) { |
14415745 CW |
2463 | ret = i915_gem_object_flush_fence(obj); |
2464 | if (ret) | |
2465 | return ret; | |
2466 | } | |
9a5a53b3 | 2467 | |
d9e86c0e | 2468 | /* Just update our place in the LRU if our fence is getting reused. */ |
05394f39 CW |
2469 | if (obj->fence_reg != I915_FENCE_REG_NONE) { |
2470 | reg = &dev_priv->fence_regs[obj->fence_reg]; | |
5d82e3e6 | 2471 | if (!obj->fence_dirty) { |
14415745 CW |
2472 | list_move_tail(®->lru_list, |
2473 | &dev_priv->mm.fence_list); | |
2474 | return 0; | |
2475 | } | |
2476 | } else if (enable) { | |
2477 | reg = i915_find_fence_reg(dev); | |
2478 | if (reg == NULL) | |
2479 | return -EDEADLK; | |
d9e86c0e | 2480 | |
14415745 CW |
2481 | if (reg->obj) { |
2482 | struct drm_i915_gem_object *old = reg->obj; | |
2483 | ||
2484 | ret = i915_gem_object_flush_fence(old); | |
29c5a587 CW |
2485 | if (ret) |
2486 | return ret; | |
2487 | ||
14415745 | 2488 | i915_gem_object_fence_lost(old); |
29c5a587 | 2489 | } |
14415745 | 2490 | } else |
a09ba7fa | 2491 | return 0; |
a09ba7fa | 2492 | |
14415745 | 2493 | i915_gem_object_update_fence(obj, reg, enable); |
5d82e3e6 | 2494 | obj->fence_dirty = false; |
14415745 | 2495 | |
9ce079e4 | 2496 | return 0; |
de151cf6 JB |
2497 | } |
2498 | ||
673a394b EA |
2499 | /** |
2500 | * Finds free space in the GTT aperture and binds the object there. | |
2501 | */ | |
2502 | static int | |
05394f39 | 2503 | i915_gem_object_bind_to_gtt(struct drm_i915_gem_object *obj, |
920afa77 | 2504 | unsigned alignment, |
75e9e915 | 2505 | bool map_and_fenceable) |
673a394b | 2506 | { |
05394f39 | 2507 | struct drm_device *dev = obj->base.dev; |
673a394b | 2508 | drm_i915_private_t *dev_priv = dev->dev_private; |
673a394b | 2509 | struct drm_mm_node *free_space; |
a00b10c3 | 2510 | gfp_t gfpmask = __GFP_NORETRY | __GFP_NOWARN; |
5e783301 | 2511 | u32 size, fence_size, fence_alignment, unfenced_alignment; |
75e9e915 | 2512 | bool mappable, fenceable; |
07f73f69 | 2513 | int ret; |
673a394b | 2514 | |
05394f39 | 2515 | if (obj->madv != I915_MADV_WILLNEED) { |
3ef94daa CW |
2516 | DRM_ERROR("Attempting to bind a purgeable object\n"); |
2517 | return -EINVAL; | |
2518 | } | |
2519 | ||
e28f8711 CW |
2520 | fence_size = i915_gem_get_gtt_size(dev, |
2521 | obj->base.size, | |
2522 | obj->tiling_mode); | |
2523 | fence_alignment = i915_gem_get_gtt_alignment(dev, | |
2524 | obj->base.size, | |
2525 | obj->tiling_mode); | |
2526 | unfenced_alignment = | |
2527 | i915_gem_get_unfenced_gtt_alignment(dev, | |
2528 | obj->base.size, | |
2529 | obj->tiling_mode); | |
a00b10c3 | 2530 | |
673a394b | 2531 | if (alignment == 0) |
5e783301 DV |
2532 | alignment = map_and_fenceable ? fence_alignment : |
2533 | unfenced_alignment; | |
75e9e915 | 2534 | if (map_and_fenceable && alignment & (fence_alignment - 1)) { |
673a394b EA |
2535 | DRM_ERROR("Invalid object alignment requested %u\n", alignment); |
2536 | return -EINVAL; | |
2537 | } | |
2538 | ||
05394f39 | 2539 | size = map_and_fenceable ? fence_size : obj->base.size; |
a00b10c3 | 2540 | |
654fc607 CW |
2541 | /* If the object is bigger than the entire aperture, reject it early |
2542 | * before evicting everything in a vain attempt to find space. | |
2543 | */ | |
05394f39 | 2544 | if (obj->base.size > |
75e9e915 | 2545 | (map_and_fenceable ? dev_priv->mm.gtt_mappable_end : dev_priv->mm.gtt_total)) { |
654fc607 CW |
2546 | DRM_ERROR("Attempting to bind an object larger than the aperture\n"); |
2547 | return -E2BIG; | |
2548 | } | |
2549 | ||
673a394b | 2550 | search_free: |
75e9e915 | 2551 | if (map_and_fenceable) |
920afa77 DV |
2552 | free_space = |
2553 | drm_mm_search_free_in_range(&dev_priv->mm.gtt_space, | |
a00b10c3 | 2554 | size, alignment, 0, |
920afa77 DV |
2555 | dev_priv->mm.gtt_mappable_end, |
2556 | 0); | |
2557 | else | |
2558 | free_space = drm_mm_search_free(&dev_priv->mm.gtt_space, | |
a00b10c3 | 2559 | size, alignment, 0); |
920afa77 DV |
2560 | |
2561 | if (free_space != NULL) { | |
75e9e915 | 2562 | if (map_and_fenceable) |
05394f39 | 2563 | obj->gtt_space = |
920afa77 | 2564 | drm_mm_get_block_range_generic(free_space, |
a00b10c3 | 2565 | size, alignment, 0, |
920afa77 DV |
2566 | dev_priv->mm.gtt_mappable_end, |
2567 | 0); | |
2568 | else | |
05394f39 | 2569 | obj->gtt_space = |
a00b10c3 | 2570 | drm_mm_get_block(free_space, size, alignment); |
920afa77 | 2571 | } |
05394f39 | 2572 | if (obj->gtt_space == NULL) { |
673a394b EA |
2573 | /* If the gtt is empty and we're still having trouble |
2574 | * fitting our object in, we're out of memory. | |
2575 | */ | |
75e9e915 DV |
2576 | ret = i915_gem_evict_something(dev, size, alignment, |
2577 | map_and_fenceable); | |
9731129c | 2578 | if (ret) |
673a394b | 2579 | return ret; |
9731129c | 2580 | |
673a394b EA |
2581 | goto search_free; |
2582 | } | |
2583 | ||
e5281ccd | 2584 | ret = i915_gem_object_get_pages_gtt(obj, gfpmask); |
673a394b | 2585 | if (ret) { |
05394f39 CW |
2586 | drm_mm_put_block(obj->gtt_space); |
2587 | obj->gtt_space = NULL; | |
07f73f69 CW |
2588 | |
2589 | if (ret == -ENOMEM) { | |
809b6334 CW |
2590 | /* first try to reclaim some memory by clearing the GTT */ |
2591 | ret = i915_gem_evict_everything(dev, false); | |
07f73f69 | 2592 | if (ret) { |
07f73f69 | 2593 | /* now try to shrink everyone else */ |
4bdadb97 CW |
2594 | if (gfpmask) { |
2595 | gfpmask = 0; | |
2596 | goto search_free; | |
07f73f69 CW |
2597 | } |
2598 | ||
809b6334 | 2599 | return -ENOMEM; |
07f73f69 CW |
2600 | } |
2601 | ||
2602 | goto search_free; | |
2603 | } | |
2604 | ||
673a394b EA |
2605 | return ret; |
2606 | } | |
2607 | ||
74163907 | 2608 | ret = i915_gem_gtt_prepare_object(obj); |
7c2e6fdf | 2609 | if (ret) { |
e5281ccd | 2610 | i915_gem_object_put_pages_gtt(obj); |
05394f39 CW |
2611 | drm_mm_put_block(obj->gtt_space); |
2612 | obj->gtt_space = NULL; | |
07f73f69 | 2613 | |
809b6334 | 2614 | if (i915_gem_evict_everything(dev, false)) |
07f73f69 | 2615 | return ret; |
07f73f69 CW |
2616 | |
2617 | goto search_free; | |
673a394b | 2618 | } |
673a394b | 2619 | |
0ebb9829 DV |
2620 | if (!dev_priv->mm.aliasing_ppgtt) |
2621 | i915_gem_gtt_bind_object(obj, obj->cache_level); | |
673a394b | 2622 | |
6299f992 | 2623 | list_add_tail(&obj->gtt_list, &dev_priv->mm.gtt_list); |
05394f39 | 2624 | list_add_tail(&obj->mm_list, &dev_priv->mm.inactive_list); |
bf1a1092 | 2625 | |
673a394b EA |
2626 | /* Assert that the object is not currently in any GPU domain. As it |
2627 | * wasn't in the GTT, there shouldn't be any way it could have been in | |
2628 | * a GPU cache | |
2629 | */ | |
05394f39 CW |
2630 | BUG_ON(obj->base.read_domains & I915_GEM_GPU_DOMAINS); |
2631 | BUG_ON(obj->base.write_domain & I915_GEM_GPU_DOMAINS); | |
673a394b | 2632 | |
6299f992 | 2633 | obj->gtt_offset = obj->gtt_space->start; |
1c5d22f7 | 2634 | |
75e9e915 | 2635 | fenceable = |
05394f39 | 2636 | obj->gtt_space->size == fence_size && |
0206e353 | 2637 | (obj->gtt_space->start & (fence_alignment - 1)) == 0; |
a00b10c3 | 2638 | |
75e9e915 | 2639 | mappable = |
05394f39 | 2640 | obj->gtt_offset + obj->base.size <= dev_priv->mm.gtt_mappable_end; |
a00b10c3 | 2641 | |
05394f39 | 2642 | obj->map_and_fenceable = mappable && fenceable; |
75e9e915 | 2643 | |
db53a302 | 2644 | trace_i915_gem_object_bind(obj, map_and_fenceable); |
673a394b EA |
2645 | return 0; |
2646 | } | |
2647 | ||
2648 | void | |
05394f39 | 2649 | i915_gem_clflush_object(struct drm_i915_gem_object *obj) |
673a394b | 2650 | { |
673a394b EA |
2651 | /* If we don't have a page list set up, then we're not pinned |
2652 | * to GPU, and we can ignore the cache flush because it'll happen | |
2653 | * again at bind time. | |
2654 | */ | |
05394f39 | 2655 | if (obj->pages == NULL) |
673a394b EA |
2656 | return; |
2657 | ||
9c23f7fc CW |
2658 | /* If the GPU is snooping the contents of the CPU cache, |
2659 | * we do not need to manually clear the CPU cache lines. However, | |
2660 | * the caches are only snooped when the render cache is | |
2661 | * flushed/invalidated. As we always have to emit invalidations | |
2662 | * and flushes when moving into and out of the RENDER domain, correct | |
2663 | * snooping behaviour occurs naturally as the result of our domain | |
2664 | * tracking. | |
2665 | */ | |
2666 | if (obj->cache_level != I915_CACHE_NONE) | |
2667 | return; | |
2668 | ||
1c5d22f7 | 2669 | trace_i915_gem_object_clflush(obj); |
cfa16a0d | 2670 | |
05394f39 | 2671 | drm_clflush_pages(obj->pages, obj->base.size / PAGE_SIZE); |
673a394b EA |
2672 | } |
2673 | ||
e47c68e9 | 2674 | /** Flushes any GPU write domain for the object if it's dirty. */ |
88241785 | 2675 | static int |
3619df03 | 2676 | i915_gem_object_flush_gpu_write_domain(struct drm_i915_gem_object *obj) |
e47c68e9 | 2677 | { |
05394f39 | 2678 | if ((obj->base.write_domain & I915_GEM_GPU_DOMAINS) == 0) |
88241785 | 2679 | return 0; |
e47c68e9 EA |
2680 | |
2681 | /* Queue the GPU write cache flushing we need. */ | |
db53a302 | 2682 | return i915_gem_flush_ring(obj->ring, 0, obj->base.write_domain); |
e47c68e9 EA |
2683 | } |
2684 | ||
2685 | /** Flushes the GTT write domain for the object if it's dirty. */ | |
2686 | static void | |
05394f39 | 2687 | i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj) |
e47c68e9 | 2688 | { |
1c5d22f7 CW |
2689 | uint32_t old_write_domain; |
2690 | ||
05394f39 | 2691 | if (obj->base.write_domain != I915_GEM_DOMAIN_GTT) |
e47c68e9 EA |
2692 | return; |
2693 | ||
63256ec5 | 2694 | /* No actual flushing is required for the GTT write domain. Writes |
e47c68e9 EA |
2695 | * to it immediately go to main memory as far as we know, so there's |
2696 | * no chipset flush. It also doesn't land in render cache. | |
63256ec5 CW |
2697 | * |
2698 | * However, we do have to enforce the order so that all writes through | |
2699 | * the GTT land before any writes to the device, such as updates to | |
2700 | * the GATT itself. | |
e47c68e9 | 2701 | */ |
63256ec5 CW |
2702 | wmb(); |
2703 | ||
05394f39 CW |
2704 | old_write_domain = obj->base.write_domain; |
2705 | obj->base.write_domain = 0; | |
1c5d22f7 CW |
2706 | |
2707 | trace_i915_gem_object_change_domain(obj, | |
05394f39 | 2708 | obj->base.read_domains, |
1c5d22f7 | 2709 | old_write_domain); |
e47c68e9 EA |
2710 | } |
2711 | ||
2712 | /** Flushes the CPU write domain for the object if it's dirty. */ | |
2713 | static void | |
05394f39 | 2714 | i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj) |
e47c68e9 | 2715 | { |
1c5d22f7 | 2716 | uint32_t old_write_domain; |
e47c68e9 | 2717 | |
05394f39 | 2718 | if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) |
e47c68e9 EA |
2719 | return; |
2720 | ||
2721 | i915_gem_clflush_object(obj); | |
40ce6575 | 2722 | intel_gtt_chipset_flush(); |
05394f39 CW |
2723 | old_write_domain = obj->base.write_domain; |
2724 | obj->base.write_domain = 0; | |
1c5d22f7 CW |
2725 | |
2726 | trace_i915_gem_object_change_domain(obj, | |
05394f39 | 2727 | obj->base.read_domains, |
1c5d22f7 | 2728 | old_write_domain); |
e47c68e9 EA |
2729 | } |
2730 | ||
2ef7eeaa EA |
2731 | /** |
2732 | * Moves a single object to the GTT read, and possibly write domain. | |
2733 | * | |
2734 | * This function returns when the move is complete, including waiting on | |
2735 | * flushes to occur. | |
2736 | */ | |
79e53945 | 2737 | int |
2021746e | 2738 | i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write) |
2ef7eeaa | 2739 | { |
8325a09d | 2740 | drm_i915_private_t *dev_priv = obj->base.dev->dev_private; |
1c5d22f7 | 2741 | uint32_t old_write_domain, old_read_domains; |
e47c68e9 | 2742 | int ret; |
2ef7eeaa | 2743 | |
02354392 | 2744 | /* Not valid to be called on unbound objects. */ |
05394f39 | 2745 | if (obj->gtt_space == NULL) |
02354392 EA |
2746 | return -EINVAL; |
2747 | ||
8d7e3de1 CW |
2748 | if (obj->base.write_domain == I915_GEM_DOMAIN_GTT) |
2749 | return 0; | |
2750 | ||
88241785 CW |
2751 | ret = i915_gem_object_flush_gpu_write_domain(obj); |
2752 | if (ret) | |
2753 | return ret; | |
2754 | ||
87ca9c8a | 2755 | if (obj->pending_gpu_write || write) { |
ce453d81 | 2756 | ret = i915_gem_object_wait_rendering(obj); |
87ca9c8a CW |
2757 | if (ret) |
2758 | return ret; | |
2759 | } | |
2dafb1e0 | 2760 | |
7213342d | 2761 | i915_gem_object_flush_cpu_write_domain(obj); |
1c5d22f7 | 2762 | |
05394f39 CW |
2763 | old_write_domain = obj->base.write_domain; |
2764 | old_read_domains = obj->base.read_domains; | |
1c5d22f7 | 2765 | |
e47c68e9 EA |
2766 | /* It should now be out of any other write domains, and we can update |
2767 | * the domain values for our changes. | |
2768 | */ | |
05394f39 CW |
2769 | BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) != 0); |
2770 | obj->base.read_domains |= I915_GEM_DOMAIN_GTT; | |
e47c68e9 | 2771 | if (write) { |
05394f39 CW |
2772 | obj->base.read_domains = I915_GEM_DOMAIN_GTT; |
2773 | obj->base.write_domain = I915_GEM_DOMAIN_GTT; | |
2774 | obj->dirty = 1; | |
2ef7eeaa EA |
2775 | } |
2776 | ||
1c5d22f7 CW |
2777 | trace_i915_gem_object_change_domain(obj, |
2778 | old_read_domains, | |
2779 | old_write_domain); | |
2780 | ||
8325a09d CW |
2781 | /* And bump the LRU for this access */ |
2782 | if (i915_gem_object_is_inactive(obj)) | |
2783 | list_move_tail(&obj->mm_list, &dev_priv->mm.inactive_list); | |
2784 | ||
e47c68e9 EA |
2785 | return 0; |
2786 | } | |
2787 | ||
e4ffd173 CW |
2788 | int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj, |
2789 | enum i915_cache_level cache_level) | |
2790 | { | |
7bddb01f DV |
2791 | struct drm_device *dev = obj->base.dev; |
2792 | drm_i915_private_t *dev_priv = dev->dev_private; | |
e4ffd173 CW |
2793 | int ret; |
2794 | ||
2795 | if (obj->cache_level == cache_level) | |
2796 | return 0; | |
2797 | ||
2798 | if (obj->pin_count) { | |
2799 | DRM_DEBUG("can not change the cache level of pinned objects\n"); | |
2800 | return -EBUSY; | |
2801 | } | |
2802 | ||
2803 | if (obj->gtt_space) { | |
2804 | ret = i915_gem_object_finish_gpu(obj); | |
2805 | if (ret) | |
2806 | return ret; | |
2807 | ||
2808 | i915_gem_object_finish_gtt(obj); | |
2809 | ||
2810 | /* Before SandyBridge, you could not use tiling or fence | |
2811 | * registers with snooped memory, so relinquish any fences | |
2812 | * currently pointing to our region in the aperture. | |
2813 | */ | |
2814 | if (INTEL_INFO(obj->base.dev)->gen < 6) { | |
2815 | ret = i915_gem_object_put_fence(obj); | |
2816 | if (ret) | |
2817 | return ret; | |
2818 | } | |
2819 | ||
74898d7e DV |
2820 | if (obj->has_global_gtt_mapping) |
2821 | i915_gem_gtt_bind_object(obj, cache_level); | |
7bddb01f DV |
2822 | if (obj->has_aliasing_ppgtt_mapping) |
2823 | i915_ppgtt_bind_object(dev_priv->mm.aliasing_ppgtt, | |
2824 | obj, cache_level); | |
e4ffd173 CW |
2825 | } |
2826 | ||
2827 | if (cache_level == I915_CACHE_NONE) { | |
2828 | u32 old_read_domains, old_write_domain; | |
2829 | ||
2830 | /* If we're coming from LLC cached, then we haven't | |
2831 | * actually been tracking whether the data is in the | |
2832 | * CPU cache or not, since we only allow one bit set | |
2833 | * in obj->write_domain and have been skipping the clflushes. | |
2834 | * Just set it to the CPU cache for now. | |
2835 | */ | |
2836 | WARN_ON(obj->base.write_domain & ~I915_GEM_DOMAIN_CPU); | |
2837 | WARN_ON(obj->base.read_domains & ~I915_GEM_DOMAIN_CPU); | |
2838 | ||
2839 | old_read_domains = obj->base.read_domains; | |
2840 | old_write_domain = obj->base.write_domain; | |
2841 | ||
2842 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; | |
2843 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; | |
2844 | ||
2845 | trace_i915_gem_object_change_domain(obj, | |
2846 | old_read_domains, | |
2847 | old_write_domain); | |
2848 | } | |
2849 | ||
2850 | obj->cache_level = cache_level; | |
2851 | return 0; | |
2852 | } | |
2853 | ||
b9241ea3 | 2854 | /* |
2da3b9b9 CW |
2855 | * Prepare buffer for display plane (scanout, cursors, etc). |
2856 | * Can be called from an uninterruptible phase (modesetting) and allows | |
2857 | * any flushes to be pipelined (for pageflips). | |
b9241ea3 ZW |
2858 | */ |
2859 | int | |
2da3b9b9 CW |
2860 | i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj, |
2861 | u32 alignment, | |
919926ae | 2862 | struct intel_ring_buffer *pipelined) |
b9241ea3 | 2863 | { |
2da3b9b9 | 2864 | u32 old_read_domains, old_write_domain; |
b9241ea3 ZW |
2865 | int ret; |
2866 | ||
88241785 CW |
2867 | ret = i915_gem_object_flush_gpu_write_domain(obj); |
2868 | if (ret) | |
2869 | return ret; | |
2870 | ||
0be73284 | 2871 | if (pipelined != obj->ring) { |
2911a35b BW |
2872 | ret = i915_gem_object_sync(obj, pipelined); |
2873 | if (ret) | |
b9241ea3 ZW |
2874 | return ret; |
2875 | } | |
2876 | ||
a7ef0640 EA |
2877 | /* The display engine is not coherent with the LLC cache on gen6. As |
2878 | * a result, we make sure that the pinning that is about to occur is | |
2879 | * done with uncached PTEs. This is lowest common denominator for all | |
2880 | * chipsets. | |
2881 | * | |
2882 | * However for gen6+, we could do better by using the GFDT bit instead | |
2883 | * of uncaching, which would allow us to flush all the LLC-cached data | |
2884 | * with that bit in the PTE to main memory with just one PIPE_CONTROL. | |
2885 | */ | |
2886 | ret = i915_gem_object_set_cache_level(obj, I915_CACHE_NONE); | |
2887 | if (ret) | |
2888 | return ret; | |
2889 | ||
2da3b9b9 CW |
2890 | /* As the user may map the buffer once pinned in the display plane |
2891 | * (e.g. libkms for the bootup splash), we have to ensure that we | |
2892 | * always use map_and_fenceable for all scanout buffers. | |
2893 | */ | |
2894 | ret = i915_gem_object_pin(obj, alignment, true); | |
2895 | if (ret) | |
2896 | return ret; | |
2897 | ||
b118c1e3 CW |
2898 | i915_gem_object_flush_cpu_write_domain(obj); |
2899 | ||
2da3b9b9 | 2900 | old_write_domain = obj->base.write_domain; |
05394f39 | 2901 | old_read_domains = obj->base.read_domains; |
2da3b9b9 CW |
2902 | |
2903 | /* It should now be out of any other write domains, and we can update | |
2904 | * the domain values for our changes. | |
2905 | */ | |
2906 | BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) != 0); | |
05394f39 | 2907 | obj->base.read_domains |= I915_GEM_DOMAIN_GTT; |
b9241ea3 ZW |
2908 | |
2909 | trace_i915_gem_object_change_domain(obj, | |
2910 | old_read_domains, | |
2da3b9b9 | 2911 | old_write_domain); |
b9241ea3 ZW |
2912 | |
2913 | return 0; | |
2914 | } | |
2915 | ||
85345517 | 2916 | int |
a8198eea | 2917 | i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj) |
85345517 | 2918 | { |
88241785 CW |
2919 | int ret; |
2920 | ||
a8198eea | 2921 | if ((obj->base.read_domains & I915_GEM_GPU_DOMAINS) == 0) |
85345517 CW |
2922 | return 0; |
2923 | ||
88241785 | 2924 | if (obj->base.write_domain & I915_GEM_GPU_DOMAINS) { |
db53a302 | 2925 | ret = i915_gem_flush_ring(obj->ring, 0, obj->base.write_domain); |
88241785 CW |
2926 | if (ret) |
2927 | return ret; | |
2928 | } | |
85345517 | 2929 | |
c501ae7f CW |
2930 | ret = i915_gem_object_wait_rendering(obj); |
2931 | if (ret) | |
2932 | return ret; | |
2933 | ||
a8198eea CW |
2934 | /* Ensure that we invalidate the GPU's caches and TLBs. */ |
2935 | obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS; | |
c501ae7f | 2936 | return 0; |
85345517 CW |
2937 | } |
2938 | ||
e47c68e9 EA |
2939 | /** |
2940 | * Moves a single object to the CPU read, and possibly write domain. | |
2941 | * | |
2942 | * This function returns when the move is complete, including waiting on | |
2943 | * flushes to occur. | |
2944 | */ | |
dabdfe02 | 2945 | int |
919926ae | 2946 | i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write) |
e47c68e9 | 2947 | { |
1c5d22f7 | 2948 | uint32_t old_write_domain, old_read_domains; |
e47c68e9 EA |
2949 | int ret; |
2950 | ||
8d7e3de1 CW |
2951 | if (obj->base.write_domain == I915_GEM_DOMAIN_CPU) |
2952 | return 0; | |
2953 | ||
88241785 CW |
2954 | ret = i915_gem_object_flush_gpu_write_domain(obj); |
2955 | if (ret) | |
2956 | return ret; | |
2957 | ||
f8413190 CW |
2958 | if (write || obj->pending_gpu_write) { |
2959 | ret = i915_gem_object_wait_rendering(obj); | |
2960 | if (ret) | |
2961 | return ret; | |
2962 | } | |
2ef7eeaa | 2963 | |
e47c68e9 | 2964 | i915_gem_object_flush_gtt_write_domain(obj); |
2ef7eeaa | 2965 | |
05394f39 CW |
2966 | old_write_domain = obj->base.write_domain; |
2967 | old_read_domains = obj->base.read_domains; | |
1c5d22f7 | 2968 | |
e47c68e9 | 2969 | /* Flush the CPU cache if it's still invalid. */ |
05394f39 | 2970 | if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) { |
2ef7eeaa | 2971 | i915_gem_clflush_object(obj); |
2ef7eeaa | 2972 | |
05394f39 | 2973 | obj->base.read_domains |= I915_GEM_DOMAIN_CPU; |
2ef7eeaa EA |
2974 | } |
2975 | ||
2976 | /* It should now be out of any other write domains, and we can update | |
2977 | * the domain values for our changes. | |
2978 | */ | |
05394f39 | 2979 | BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) != 0); |
e47c68e9 EA |
2980 | |
2981 | /* If we're writing through the CPU, then the GPU read domains will | |
2982 | * need to be invalidated at next use. | |
2983 | */ | |
2984 | if (write) { | |
05394f39 CW |
2985 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; |
2986 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; | |
e47c68e9 | 2987 | } |
2ef7eeaa | 2988 | |
1c5d22f7 CW |
2989 | trace_i915_gem_object_change_domain(obj, |
2990 | old_read_domains, | |
2991 | old_write_domain); | |
2992 | ||
2ef7eeaa EA |
2993 | return 0; |
2994 | } | |
2995 | ||
673a394b EA |
2996 | /* Throttle our rendering by waiting until the ring has completed our requests |
2997 | * emitted over 20 msec ago. | |
2998 | * | |
b962442e EA |
2999 | * Note that if we were to use the current jiffies each time around the loop, |
3000 | * we wouldn't escape the function with any frames outstanding if the time to | |
3001 | * render a frame was over 20ms. | |
3002 | * | |
673a394b EA |
3003 | * This should get us reasonable parallelism between CPU and GPU but also |
3004 | * relatively low latency when blocking on a particular request to finish. | |
3005 | */ | |
40a5f0de | 3006 | static int |
f787a5f5 | 3007 | i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file) |
40a5f0de | 3008 | { |
f787a5f5 CW |
3009 | struct drm_i915_private *dev_priv = dev->dev_private; |
3010 | struct drm_i915_file_private *file_priv = file->driver_priv; | |
b962442e | 3011 | unsigned long recent_enough = jiffies - msecs_to_jiffies(20); |
f787a5f5 CW |
3012 | struct drm_i915_gem_request *request; |
3013 | struct intel_ring_buffer *ring = NULL; | |
3014 | u32 seqno = 0; | |
3015 | int ret; | |
93533c29 | 3016 | |
e110e8d6 CW |
3017 | if (atomic_read(&dev_priv->mm.wedged)) |
3018 | return -EIO; | |
3019 | ||
1c25595f | 3020 | spin_lock(&file_priv->mm.lock); |
f787a5f5 | 3021 | list_for_each_entry(request, &file_priv->mm.request_list, client_list) { |
b962442e EA |
3022 | if (time_after_eq(request->emitted_jiffies, recent_enough)) |
3023 | break; | |
40a5f0de | 3024 | |
f787a5f5 CW |
3025 | ring = request->ring; |
3026 | seqno = request->seqno; | |
b962442e | 3027 | } |
1c25595f | 3028 | spin_unlock(&file_priv->mm.lock); |
40a5f0de | 3029 | |
f787a5f5 CW |
3030 | if (seqno == 0) |
3031 | return 0; | |
2bc43b5c | 3032 | |
f787a5f5 | 3033 | ret = 0; |
78501eac | 3034 | if (!i915_seqno_passed(ring->get_seqno(ring), seqno)) { |
f787a5f5 CW |
3035 | /* And wait for the seqno passing without holding any locks and |
3036 | * causing extra latency for others. This is safe as the irq | |
3037 | * generation is designed to be run atomically and so is | |
3038 | * lockless. | |
3039 | */ | |
b13c2b96 CW |
3040 | if (ring->irq_get(ring)) { |
3041 | ret = wait_event_interruptible(ring->irq_queue, | |
3042 | i915_seqno_passed(ring->get_seqno(ring), seqno) | |
3043 | || atomic_read(&dev_priv->mm.wedged)); | |
3044 | ring->irq_put(ring); | |
40a5f0de | 3045 | |
b13c2b96 CW |
3046 | if (ret == 0 && atomic_read(&dev_priv->mm.wedged)) |
3047 | ret = -EIO; | |
e959b5db EA |
3048 | } else if (wait_for_atomic(i915_seqno_passed(ring->get_seqno(ring), |
3049 | seqno) || | |
7ea29b13 EA |
3050 | atomic_read(&dev_priv->mm.wedged), 3000)) { |
3051 | ret = -EBUSY; | |
b13c2b96 | 3052 | } |
40a5f0de EA |
3053 | } |
3054 | ||
f787a5f5 CW |
3055 | if (ret == 0) |
3056 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, 0); | |
40a5f0de EA |
3057 | |
3058 | return ret; | |
3059 | } | |
3060 | ||
673a394b | 3061 | int |
05394f39 CW |
3062 | i915_gem_object_pin(struct drm_i915_gem_object *obj, |
3063 | uint32_t alignment, | |
75e9e915 | 3064 | bool map_and_fenceable) |
673a394b | 3065 | { |
05394f39 | 3066 | struct drm_device *dev = obj->base.dev; |
f13d3f73 | 3067 | struct drm_i915_private *dev_priv = dev->dev_private; |
673a394b EA |
3068 | int ret; |
3069 | ||
05394f39 | 3070 | BUG_ON(obj->pin_count == DRM_I915_GEM_OBJECT_MAX_PIN_COUNT); |
23bc5982 | 3071 | WARN_ON(i915_verify_lists(dev)); |
ac0c6b5a | 3072 | |
05394f39 CW |
3073 | if (obj->gtt_space != NULL) { |
3074 | if ((alignment && obj->gtt_offset & (alignment - 1)) || | |
3075 | (map_and_fenceable && !obj->map_and_fenceable)) { | |
3076 | WARN(obj->pin_count, | |
ae7d49d8 | 3077 | "bo is already pinned with incorrect alignment:" |
75e9e915 DV |
3078 | " offset=%x, req.alignment=%x, req.map_and_fenceable=%d," |
3079 | " obj->map_and_fenceable=%d\n", | |
05394f39 | 3080 | obj->gtt_offset, alignment, |
75e9e915 | 3081 | map_and_fenceable, |
05394f39 | 3082 | obj->map_and_fenceable); |
ac0c6b5a CW |
3083 | ret = i915_gem_object_unbind(obj); |
3084 | if (ret) | |
3085 | return ret; | |
3086 | } | |
3087 | } | |
3088 | ||
05394f39 | 3089 | if (obj->gtt_space == NULL) { |
a00b10c3 | 3090 | ret = i915_gem_object_bind_to_gtt(obj, alignment, |
75e9e915 | 3091 | map_and_fenceable); |
9731129c | 3092 | if (ret) |
673a394b | 3093 | return ret; |
22c344e9 | 3094 | } |
76446cac | 3095 | |
74898d7e DV |
3096 | if (!obj->has_global_gtt_mapping && map_and_fenceable) |
3097 | i915_gem_gtt_bind_object(obj, obj->cache_level); | |
3098 | ||
05394f39 | 3099 | if (obj->pin_count++ == 0) { |
05394f39 CW |
3100 | if (!obj->active) |
3101 | list_move_tail(&obj->mm_list, | |
f13d3f73 | 3102 | &dev_priv->mm.pinned_list); |
673a394b | 3103 | } |
6299f992 | 3104 | obj->pin_mappable |= map_and_fenceable; |
673a394b | 3105 | |
23bc5982 | 3106 | WARN_ON(i915_verify_lists(dev)); |
673a394b EA |
3107 | return 0; |
3108 | } | |
3109 | ||
3110 | void | |
05394f39 | 3111 | i915_gem_object_unpin(struct drm_i915_gem_object *obj) |
673a394b | 3112 | { |
05394f39 | 3113 | struct drm_device *dev = obj->base.dev; |
673a394b | 3114 | drm_i915_private_t *dev_priv = dev->dev_private; |
673a394b | 3115 | |
23bc5982 | 3116 | WARN_ON(i915_verify_lists(dev)); |
05394f39 CW |
3117 | BUG_ON(obj->pin_count == 0); |
3118 | BUG_ON(obj->gtt_space == NULL); | |
673a394b | 3119 | |
05394f39 CW |
3120 | if (--obj->pin_count == 0) { |
3121 | if (!obj->active) | |
3122 | list_move_tail(&obj->mm_list, | |
673a394b | 3123 | &dev_priv->mm.inactive_list); |
6299f992 | 3124 | obj->pin_mappable = false; |
673a394b | 3125 | } |
23bc5982 | 3126 | WARN_ON(i915_verify_lists(dev)); |
673a394b EA |
3127 | } |
3128 | ||
3129 | int | |
3130 | i915_gem_pin_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 3131 | struct drm_file *file) |
673a394b EA |
3132 | { |
3133 | struct drm_i915_gem_pin *args = data; | |
05394f39 | 3134 | struct drm_i915_gem_object *obj; |
673a394b EA |
3135 | int ret; |
3136 | ||
1d7cfea1 CW |
3137 | ret = i915_mutex_lock_interruptible(dev); |
3138 | if (ret) | |
3139 | return ret; | |
673a394b | 3140 | |
05394f39 | 3141 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 3142 | if (&obj->base == NULL) { |
1d7cfea1 CW |
3143 | ret = -ENOENT; |
3144 | goto unlock; | |
673a394b | 3145 | } |
673a394b | 3146 | |
05394f39 | 3147 | if (obj->madv != I915_MADV_WILLNEED) { |
bb6baf76 | 3148 | DRM_ERROR("Attempting to pin a purgeable buffer\n"); |
1d7cfea1 CW |
3149 | ret = -EINVAL; |
3150 | goto out; | |
3ef94daa CW |
3151 | } |
3152 | ||
05394f39 | 3153 | if (obj->pin_filp != NULL && obj->pin_filp != file) { |
79e53945 JB |
3154 | DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n", |
3155 | args->handle); | |
1d7cfea1 CW |
3156 | ret = -EINVAL; |
3157 | goto out; | |
79e53945 JB |
3158 | } |
3159 | ||
05394f39 CW |
3160 | obj->user_pin_count++; |
3161 | obj->pin_filp = file; | |
3162 | if (obj->user_pin_count == 1) { | |
75e9e915 | 3163 | ret = i915_gem_object_pin(obj, args->alignment, true); |
1d7cfea1 CW |
3164 | if (ret) |
3165 | goto out; | |
673a394b EA |
3166 | } |
3167 | ||
3168 | /* XXX - flush the CPU caches for pinned objects | |
3169 | * as the X server doesn't manage domains yet | |
3170 | */ | |
e47c68e9 | 3171 | i915_gem_object_flush_cpu_write_domain(obj); |
05394f39 | 3172 | args->offset = obj->gtt_offset; |
1d7cfea1 | 3173 | out: |
05394f39 | 3174 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 3175 | unlock: |
673a394b | 3176 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 3177 | return ret; |
673a394b EA |
3178 | } |
3179 | ||
3180 | int | |
3181 | i915_gem_unpin_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 3182 | struct drm_file *file) |
673a394b EA |
3183 | { |
3184 | struct drm_i915_gem_pin *args = data; | |
05394f39 | 3185 | struct drm_i915_gem_object *obj; |
76c1dec1 | 3186 | int ret; |
673a394b | 3187 | |
1d7cfea1 CW |
3188 | ret = i915_mutex_lock_interruptible(dev); |
3189 | if (ret) | |
3190 | return ret; | |
673a394b | 3191 | |
05394f39 | 3192 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 3193 | if (&obj->base == NULL) { |
1d7cfea1 CW |
3194 | ret = -ENOENT; |
3195 | goto unlock; | |
673a394b | 3196 | } |
76c1dec1 | 3197 | |
05394f39 | 3198 | if (obj->pin_filp != file) { |
79e53945 JB |
3199 | DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n", |
3200 | args->handle); | |
1d7cfea1 CW |
3201 | ret = -EINVAL; |
3202 | goto out; | |
79e53945 | 3203 | } |
05394f39 CW |
3204 | obj->user_pin_count--; |
3205 | if (obj->user_pin_count == 0) { | |
3206 | obj->pin_filp = NULL; | |
79e53945 JB |
3207 | i915_gem_object_unpin(obj); |
3208 | } | |
673a394b | 3209 | |
1d7cfea1 | 3210 | out: |
05394f39 | 3211 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 3212 | unlock: |
673a394b | 3213 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 3214 | return ret; |
673a394b EA |
3215 | } |
3216 | ||
3217 | int | |
3218 | i915_gem_busy_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 3219 | struct drm_file *file) |
673a394b EA |
3220 | { |
3221 | struct drm_i915_gem_busy *args = data; | |
05394f39 | 3222 | struct drm_i915_gem_object *obj; |
30dbf0c0 CW |
3223 | int ret; |
3224 | ||
76c1dec1 | 3225 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 3226 | if (ret) |
76c1dec1 | 3227 | return ret; |
673a394b | 3228 | |
05394f39 | 3229 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 3230 | if (&obj->base == NULL) { |
1d7cfea1 CW |
3231 | ret = -ENOENT; |
3232 | goto unlock; | |
673a394b | 3233 | } |
d1b851fc | 3234 | |
0be555b6 CW |
3235 | /* Count all active objects as busy, even if they are currently not used |
3236 | * by the gpu. Users of this interface expect objects to eventually | |
3237 | * become non-busy without any further actions, therefore emit any | |
3238 | * necessary flushes here. | |
c4de0a5d | 3239 | */ |
05394f39 | 3240 | args->busy = obj->active; |
0be555b6 CW |
3241 | if (args->busy) { |
3242 | /* Unconditionally flush objects, even when the gpu still uses this | |
3243 | * object. Userspace calling this function indicates that it wants to | |
3244 | * use this buffer rather sooner than later, so issuing the required | |
3245 | * flush earlier is beneficial. | |
3246 | */ | |
1a1c6976 | 3247 | if (obj->base.write_domain & I915_GEM_GPU_DOMAINS) { |
db53a302 | 3248 | ret = i915_gem_flush_ring(obj->ring, |
88241785 | 3249 | 0, obj->base.write_domain); |
1a1c6976 CW |
3250 | } else if (obj->ring->outstanding_lazy_request == |
3251 | obj->last_rendering_seqno) { | |
3252 | struct drm_i915_gem_request *request; | |
3253 | ||
7a194876 CW |
3254 | /* This ring is not being cleared by active usage, |
3255 | * so emit a request to do so. | |
3256 | */ | |
1a1c6976 | 3257 | request = kzalloc(sizeof(*request), GFP_KERNEL); |
457eafce | 3258 | if (request) { |
0206e353 | 3259 | ret = i915_add_request(obj->ring, NULL, request); |
457eafce RM |
3260 | if (ret) |
3261 | kfree(request); | |
3262 | } else | |
7a194876 CW |
3263 | ret = -ENOMEM; |
3264 | } | |
0be555b6 CW |
3265 | |
3266 | /* Update the active list for the hardware's current position. | |
3267 | * Otherwise this only updates on a delayed timer or when irqs | |
3268 | * are actually unmasked, and our working set ends up being | |
3269 | * larger than required. | |
3270 | */ | |
db53a302 | 3271 | i915_gem_retire_requests_ring(obj->ring); |
0be555b6 | 3272 | |
05394f39 | 3273 | args->busy = obj->active; |
0be555b6 | 3274 | } |
673a394b | 3275 | |
05394f39 | 3276 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 3277 | unlock: |
673a394b | 3278 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 3279 | return ret; |
673a394b EA |
3280 | } |
3281 | ||
3282 | int | |
3283 | i915_gem_throttle_ioctl(struct drm_device *dev, void *data, | |
3284 | struct drm_file *file_priv) | |
3285 | { | |
0206e353 | 3286 | return i915_gem_ring_throttle(dev, file_priv); |
673a394b EA |
3287 | } |
3288 | ||
3ef94daa CW |
3289 | int |
3290 | i915_gem_madvise_ioctl(struct drm_device *dev, void *data, | |
3291 | struct drm_file *file_priv) | |
3292 | { | |
3293 | struct drm_i915_gem_madvise *args = data; | |
05394f39 | 3294 | struct drm_i915_gem_object *obj; |
76c1dec1 | 3295 | int ret; |
3ef94daa CW |
3296 | |
3297 | switch (args->madv) { | |
3298 | case I915_MADV_DONTNEED: | |
3299 | case I915_MADV_WILLNEED: | |
3300 | break; | |
3301 | default: | |
3302 | return -EINVAL; | |
3303 | } | |
3304 | ||
1d7cfea1 CW |
3305 | ret = i915_mutex_lock_interruptible(dev); |
3306 | if (ret) | |
3307 | return ret; | |
3308 | ||
05394f39 | 3309 | obj = to_intel_bo(drm_gem_object_lookup(dev, file_priv, args->handle)); |
c8725226 | 3310 | if (&obj->base == NULL) { |
1d7cfea1 CW |
3311 | ret = -ENOENT; |
3312 | goto unlock; | |
3ef94daa | 3313 | } |
3ef94daa | 3314 | |
05394f39 | 3315 | if (obj->pin_count) { |
1d7cfea1 CW |
3316 | ret = -EINVAL; |
3317 | goto out; | |
3ef94daa CW |
3318 | } |
3319 | ||
05394f39 CW |
3320 | if (obj->madv != __I915_MADV_PURGED) |
3321 | obj->madv = args->madv; | |
3ef94daa | 3322 | |
2d7ef395 | 3323 | /* if the object is no longer bound, discard its backing storage */ |
05394f39 CW |
3324 | if (i915_gem_object_is_purgeable(obj) && |
3325 | obj->gtt_space == NULL) | |
2d7ef395 CW |
3326 | i915_gem_object_truncate(obj); |
3327 | ||
05394f39 | 3328 | args->retained = obj->madv != __I915_MADV_PURGED; |
bb6baf76 | 3329 | |
1d7cfea1 | 3330 | out: |
05394f39 | 3331 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 3332 | unlock: |
3ef94daa | 3333 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 3334 | return ret; |
3ef94daa CW |
3335 | } |
3336 | ||
05394f39 CW |
3337 | struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev, |
3338 | size_t size) | |
ac52bc56 | 3339 | { |
73aa808f | 3340 | struct drm_i915_private *dev_priv = dev->dev_private; |
c397b908 | 3341 | struct drm_i915_gem_object *obj; |
5949eac4 | 3342 | struct address_space *mapping; |
ac52bc56 | 3343 | |
c397b908 DV |
3344 | obj = kzalloc(sizeof(*obj), GFP_KERNEL); |
3345 | if (obj == NULL) | |
3346 | return NULL; | |
673a394b | 3347 | |
c397b908 DV |
3348 | if (drm_gem_object_init(dev, &obj->base, size) != 0) { |
3349 | kfree(obj); | |
3350 | return NULL; | |
3351 | } | |
673a394b | 3352 | |
5949eac4 HD |
3353 | mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping; |
3354 | mapping_set_gfp_mask(mapping, GFP_HIGHUSER | __GFP_RECLAIMABLE); | |
3355 | ||
73aa808f CW |
3356 | i915_gem_info_add_obj(dev_priv, size); |
3357 | ||
c397b908 DV |
3358 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; |
3359 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; | |
673a394b | 3360 | |
3d29b842 ED |
3361 | if (HAS_LLC(dev)) { |
3362 | /* On some devices, we can have the GPU use the LLC (the CPU | |
a1871112 EA |
3363 | * cache) for about a 10% performance improvement |
3364 | * compared to uncached. Graphics requests other than | |
3365 | * display scanout are coherent with the CPU in | |
3366 | * accessing this cache. This means in this mode we | |
3367 | * don't need to clflush on the CPU side, and on the | |
3368 | * GPU side we only need to flush internal caches to | |
3369 | * get data visible to the CPU. | |
3370 | * | |
3371 | * However, we maintain the display planes as UC, and so | |
3372 | * need to rebind when first used as such. | |
3373 | */ | |
3374 | obj->cache_level = I915_CACHE_LLC; | |
3375 | } else | |
3376 | obj->cache_level = I915_CACHE_NONE; | |
3377 | ||
62b8b215 | 3378 | obj->base.driver_private = NULL; |
c397b908 | 3379 | obj->fence_reg = I915_FENCE_REG_NONE; |
69dc4987 | 3380 | INIT_LIST_HEAD(&obj->mm_list); |
93a37f20 | 3381 | INIT_LIST_HEAD(&obj->gtt_list); |
69dc4987 | 3382 | INIT_LIST_HEAD(&obj->ring_list); |
432e58ed | 3383 | INIT_LIST_HEAD(&obj->exec_list); |
c397b908 | 3384 | INIT_LIST_HEAD(&obj->gpu_write_list); |
c397b908 | 3385 | obj->madv = I915_MADV_WILLNEED; |
75e9e915 DV |
3386 | /* Avoid an unnecessary call to unbind on the first bind. */ |
3387 | obj->map_and_fenceable = true; | |
de151cf6 | 3388 | |
05394f39 | 3389 | return obj; |
c397b908 DV |
3390 | } |
3391 | ||
3392 | int i915_gem_init_object(struct drm_gem_object *obj) | |
3393 | { | |
3394 | BUG(); | |
de151cf6 | 3395 | |
673a394b EA |
3396 | return 0; |
3397 | } | |
3398 | ||
05394f39 | 3399 | static void i915_gem_free_object_tail(struct drm_i915_gem_object *obj) |
673a394b | 3400 | { |
05394f39 | 3401 | struct drm_device *dev = obj->base.dev; |
be72615b | 3402 | drm_i915_private_t *dev_priv = dev->dev_private; |
be72615b | 3403 | int ret; |
673a394b | 3404 | |
be72615b CW |
3405 | ret = i915_gem_object_unbind(obj); |
3406 | if (ret == -ERESTARTSYS) { | |
05394f39 | 3407 | list_move(&obj->mm_list, |
be72615b CW |
3408 | &dev_priv->mm.deferred_free_list); |
3409 | return; | |
3410 | } | |
673a394b | 3411 | |
26e12f89 CW |
3412 | trace_i915_gem_object_destroy(obj); |
3413 | ||
05394f39 | 3414 | if (obj->base.map_list.map) |
b464e9a2 | 3415 | drm_gem_free_mmap_offset(&obj->base); |
de151cf6 | 3416 | |
05394f39 CW |
3417 | drm_gem_object_release(&obj->base); |
3418 | i915_gem_info_remove_obj(dev_priv, obj->base.size); | |
c397b908 | 3419 | |
05394f39 CW |
3420 | kfree(obj->bit_17); |
3421 | kfree(obj); | |
673a394b EA |
3422 | } |
3423 | ||
05394f39 | 3424 | void i915_gem_free_object(struct drm_gem_object *gem_obj) |
be72615b | 3425 | { |
05394f39 CW |
3426 | struct drm_i915_gem_object *obj = to_intel_bo(gem_obj); |
3427 | struct drm_device *dev = obj->base.dev; | |
be72615b | 3428 | |
05394f39 | 3429 | while (obj->pin_count > 0) |
be72615b CW |
3430 | i915_gem_object_unpin(obj); |
3431 | ||
05394f39 | 3432 | if (obj->phys_obj) |
be72615b CW |
3433 | i915_gem_detach_phys_object(dev, obj); |
3434 | ||
3435 | i915_gem_free_object_tail(obj); | |
3436 | } | |
3437 | ||
29105ccc CW |
3438 | int |
3439 | i915_gem_idle(struct drm_device *dev) | |
3440 | { | |
3441 | drm_i915_private_t *dev_priv = dev->dev_private; | |
3442 | int ret; | |
28dfe52a | 3443 | |
29105ccc | 3444 | mutex_lock(&dev->struct_mutex); |
1c5d22f7 | 3445 | |
87acb0a5 | 3446 | if (dev_priv->mm.suspended) { |
29105ccc CW |
3447 | mutex_unlock(&dev->struct_mutex); |
3448 | return 0; | |
28dfe52a EA |
3449 | } |
3450 | ||
b93f9cf1 | 3451 | ret = i915_gpu_idle(dev, true); |
6dbe2772 KP |
3452 | if (ret) { |
3453 | mutex_unlock(&dev->struct_mutex); | |
673a394b | 3454 | return ret; |
6dbe2772 | 3455 | } |
673a394b | 3456 | |
29105ccc CW |
3457 | /* Under UMS, be paranoid and evict. */ |
3458 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) { | |
5eac3ab4 | 3459 | ret = i915_gem_evict_inactive(dev, false); |
29105ccc CW |
3460 | if (ret) { |
3461 | mutex_unlock(&dev->struct_mutex); | |
3462 | return ret; | |
3463 | } | |
3464 | } | |
3465 | ||
312817a3 CW |
3466 | i915_gem_reset_fences(dev); |
3467 | ||
29105ccc CW |
3468 | /* Hack! Don't let anybody do execbuf while we don't control the chip. |
3469 | * We need to replace this with a semaphore, or something. | |
3470 | * And not confound mm.suspended! | |
3471 | */ | |
3472 | dev_priv->mm.suspended = 1; | |
bc0c7f14 | 3473 | del_timer_sync(&dev_priv->hangcheck_timer); |
29105ccc CW |
3474 | |
3475 | i915_kernel_lost_context(dev); | |
6dbe2772 | 3476 | i915_gem_cleanup_ringbuffer(dev); |
29105ccc | 3477 | |
6dbe2772 KP |
3478 | mutex_unlock(&dev->struct_mutex); |
3479 | ||
29105ccc CW |
3480 | /* Cancel the retire work handler, which should be idle now. */ |
3481 | cancel_delayed_work_sync(&dev_priv->mm.retire_work); | |
3482 | ||
673a394b EA |
3483 | return 0; |
3484 | } | |
3485 | ||
f691e2f4 DV |
3486 | void i915_gem_init_swizzling(struct drm_device *dev) |
3487 | { | |
3488 | drm_i915_private_t *dev_priv = dev->dev_private; | |
3489 | ||
11782b02 | 3490 | if (INTEL_INFO(dev)->gen < 5 || |
f691e2f4 DV |
3491 | dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE) |
3492 | return; | |
3493 | ||
3494 | I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) | | |
3495 | DISP_TILE_SURFACE_SWIZZLING); | |
3496 | ||
11782b02 DV |
3497 | if (IS_GEN5(dev)) |
3498 | return; | |
3499 | ||
f691e2f4 DV |
3500 | I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_SWZCTL); |
3501 | if (IS_GEN6(dev)) | |
6b26c86d | 3502 | I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB)); |
f691e2f4 | 3503 | else |
6b26c86d | 3504 | I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB)); |
f691e2f4 | 3505 | } |
e21af88d DV |
3506 | |
3507 | void i915_gem_init_ppgtt(struct drm_device *dev) | |
3508 | { | |
3509 | drm_i915_private_t *dev_priv = dev->dev_private; | |
3510 | uint32_t pd_offset; | |
3511 | struct intel_ring_buffer *ring; | |
55a254ac DV |
3512 | struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt; |
3513 | uint32_t __iomem *pd_addr; | |
3514 | uint32_t pd_entry; | |
e21af88d DV |
3515 | int i; |
3516 | ||
3517 | if (!dev_priv->mm.aliasing_ppgtt) | |
3518 | return; | |
3519 | ||
55a254ac DV |
3520 | |
3521 | pd_addr = dev_priv->mm.gtt->gtt + ppgtt->pd_offset/sizeof(uint32_t); | |
3522 | for (i = 0; i < ppgtt->num_pd_entries; i++) { | |
3523 | dma_addr_t pt_addr; | |
3524 | ||
3525 | if (dev_priv->mm.gtt->needs_dmar) | |
3526 | pt_addr = ppgtt->pt_dma_addr[i]; | |
3527 | else | |
3528 | pt_addr = page_to_phys(ppgtt->pt_pages[i]); | |
3529 | ||
3530 | pd_entry = GEN6_PDE_ADDR_ENCODE(pt_addr); | |
3531 | pd_entry |= GEN6_PDE_VALID; | |
3532 | ||
3533 | writel(pd_entry, pd_addr + i); | |
3534 | } | |
3535 | readl(pd_addr); | |
3536 | ||
3537 | pd_offset = ppgtt->pd_offset; | |
e21af88d DV |
3538 | pd_offset /= 64; /* in cachelines, */ |
3539 | pd_offset <<= 16; | |
3540 | ||
3541 | if (INTEL_INFO(dev)->gen == 6) { | |
48ecfa10 DV |
3542 | uint32_t ecochk, gab_ctl, ecobits; |
3543 | ||
3544 | ecobits = I915_READ(GAC_ECO_BITS); | |
3545 | I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_PPGTT_CACHE64B); | |
be901a5a DV |
3546 | |
3547 | gab_ctl = I915_READ(GAB_CTL); | |
3548 | I915_WRITE(GAB_CTL, gab_ctl | GAB_CTL_CONT_AFTER_PAGEFAULT); | |
3549 | ||
3550 | ecochk = I915_READ(GAM_ECOCHK); | |
e21af88d DV |
3551 | I915_WRITE(GAM_ECOCHK, ecochk | ECOCHK_SNB_BIT | |
3552 | ECOCHK_PPGTT_CACHE64B); | |
6b26c86d | 3553 | I915_WRITE(GFX_MODE, _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE)); |
e21af88d DV |
3554 | } else if (INTEL_INFO(dev)->gen >= 7) { |
3555 | I915_WRITE(GAM_ECOCHK, ECOCHK_PPGTT_CACHE64B); | |
3556 | /* GFX_MODE is per-ring on gen7+ */ | |
3557 | } | |
3558 | ||
3559 | for (i = 0; i < I915_NUM_RINGS; i++) { | |
3560 | ring = &dev_priv->ring[i]; | |
3561 | ||
3562 | if (INTEL_INFO(dev)->gen >= 7) | |
3563 | I915_WRITE(RING_MODE_GEN7(ring), | |
6b26c86d | 3564 | _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE)); |
e21af88d DV |
3565 | |
3566 | I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G); | |
3567 | I915_WRITE(RING_PP_DIR_BASE(ring), pd_offset); | |
3568 | } | |
3569 | } | |
3570 | ||
8187a2b7 | 3571 | int |
f691e2f4 | 3572 | i915_gem_init_hw(struct drm_device *dev) |
8187a2b7 ZN |
3573 | { |
3574 | drm_i915_private_t *dev_priv = dev->dev_private; | |
3575 | int ret; | |
68f95ba9 | 3576 | |
f691e2f4 DV |
3577 | i915_gem_init_swizzling(dev); |
3578 | ||
5c1143bb | 3579 | ret = intel_init_render_ring_buffer(dev); |
68f95ba9 | 3580 | if (ret) |
b6913e4b | 3581 | return ret; |
68f95ba9 CW |
3582 | |
3583 | if (HAS_BSD(dev)) { | |
5c1143bb | 3584 | ret = intel_init_bsd_ring_buffer(dev); |
68f95ba9 CW |
3585 | if (ret) |
3586 | goto cleanup_render_ring; | |
d1b851fc | 3587 | } |
68f95ba9 | 3588 | |
549f7365 CW |
3589 | if (HAS_BLT(dev)) { |
3590 | ret = intel_init_blt_ring_buffer(dev); | |
3591 | if (ret) | |
3592 | goto cleanup_bsd_ring; | |
3593 | } | |
3594 | ||
6f392d54 CW |
3595 | dev_priv->next_seqno = 1; |
3596 | ||
e21af88d DV |
3597 | i915_gem_init_ppgtt(dev); |
3598 | ||
68f95ba9 CW |
3599 | return 0; |
3600 | ||
549f7365 | 3601 | cleanup_bsd_ring: |
1ec14ad3 | 3602 | intel_cleanup_ring_buffer(&dev_priv->ring[VCS]); |
68f95ba9 | 3603 | cleanup_render_ring: |
1ec14ad3 | 3604 | intel_cleanup_ring_buffer(&dev_priv->ring[RCS]); |
8187a2b7 ZN |
3605 | return ret; |
3606 | } | |
3607 | ||
3608 | void | |
3609 | i915_gem_cleanup_ringbuffer(struct drm_device *dev) | |
3610 | { | |
3611 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1ec14ad3 | 3612 | int i; |
8187a2b7 | 3613 | |
1ec14ad3 CW |
3614 | for (i = 0; i < I915_NUM_RINGS; i++) |
3615 | intel_cleanup_ring_buffer(&dev_priv->ring[i]); | |
8187a2b7 ZN |
3616 | } |
3617 | ||
673a394b EA |
3618 | int |
3619 | i915_gem_entervt_ioctl(struct drm_device *dev, void *data, | |
3620 | struct drm_file *file_priv) | |
3621 | { | |
3622 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1ec14ad3 | 3623 | int ret, i; |
673a394b | 3624 | |
79e53945 JB |
3625 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
3626 | return 0; | |
3627 | ||
ba1234d1 | 3628 | if (atomic_read(&dev_priv->mm.wedged)) { |
673a394b | 3629 | DRM_ERROR("Reenabling wedged hardware, good luck\n"); |
ba1234d1 | 3630 | atomic_set(&dev_priv->mm.wedged, 0); |
673a394b EA |
3631 | } |
3632 | ||
673a394b | 3633 | mutex_lock(&dev->struct_mutex); |
9bb2d6f9 EA |
3634 | dev_priv->mm.suspended = 0; |
3635 | ||
f691e2f4 | 3636 | ret = i915_gem_init_hw(dev); |
d816f6ac WF |
3637 | if (ret != 0) { |
3638 | mutex_unlock(&dev->struct_mutex); | |
9bb2d6f9 | 3639 | return ret; |
d816f6ac | 3640 | } |
9bb2d6f9 | 3641 | |
69dc4987 | 3642 | BUG_ON(!list_empty(&dev_priv->mm.active_list)); |
673a394b EA |
3643 | BUG_ON(!list_empty(&dev_priv->mm.flushing_list)); |
3644 | BUG_ON(!list_empty(&dev_priv->mm.inactive_list)); | |
1ec14ad3 CW |
3645 | for (i = 0; i < I915_NUM_RINGS; i++) { |
3646 | BUG_ON(!list_empty(&dev_priv->ring[i].active_list)); | |
3647 | BUG_ON(!list_empty(&dev_priv->ring[i].request_list)); | |
3648 | } | |
673a394b | 3649 | mutex_unlock(&dev->struct_mutex); |
dbb19d30 | 3650 | |
5f35308b CW |
3651 | ret = drm_irq_install(dev); |
3652 | if (ret) | |
3653 | goto cleanup_ringbuffer; | |
dbb19d30 | 3654 | |
673a394b | 3655 | return 0; |
5f35308b CW |
3656 | |
3657 | cleanup_ringbuffer: | |
3658 | mutex_lock(&dev->struct_mutex); | |
3659 | i915_gem_cleanup_ringbuffer(dev); | |
3660 | dev_priv->mm.suspended = 1; | |
3661 | mutex_unlock(&dev->struct_mutex); | |
3662 | ||
3663 | return ret; | |
673a394b EA |
3664 | } |
3665 | ||
3666 | int | |
3667 | i915_gem_leavevt_ioctl(struct drm_device *dev, void *data, | |
3668 | struct drm_file *file_priv) | |
3669 | { | |
79e53945 JB |
3670 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
3671 | return 0; | |
3672 | ||
dbb19d30 | 3673 | drm_irq_uninstall(dev); |
e6890f6f | 3674 | return i915_gem_idle(dev); |
673a394b EA |
3675 | } |
3676 | ||
3677 | void | |
3678 | i915_gem_lastclose(struct drm_device *dev) | |
3679 | { | |
3680 | int ret; | |
673a394b | 3681 | |
e806b495 EA |
3682 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
3683 | return; | |
3684 | ||
6dbe2772 KP |
3685 | ret = i915_gem_idle(dev); |
3686 | if (ret) | |
3687 | DRM_ERROR("failed to idle hardware: %d\n", ret); | |
673a394b EA |
3688 | } |
3689 | ||
64193406 CW |
3690 | static void |
3691 | init_ring_lists(struct intel_ring_buffer *ring) | |
3692 | { | |
3693 | INIT_LIST_HEAD(&ring->active_list); | |
3694 | INIT_LIST_HEAD(&ring->request_list); | |
3695 | INIT_LIST_HEAD(&ring->gpu_write_list); | |
3696 | } | |
3697 | ||
673a394b EA |
3698 | void |
3699 | i915_gem_load(struct drm_device *dev) | |
3700 | { | |
b5aa8a0f | 3701 | int i; |
673a394b EA |
3702 | drm_i915_private_t *dev_priv = dev->dev_private; |
3703 | ||
69dc4987 | 3704 | INIT_LIST_HEAD(&dev_priv->mm.active_list); |
673a394b EA |
3705 | INIT_LIST_HEAD(&dev_priv->mm.flushing_list); |
3706 | INIT_LIST_HEAD(&dev_priv->mm.inactive_list); | |
f13d3f73 | 3707 | INIT_LIST_HEAD(&dev_priv->mm.pinned_list); |
a09ba7fa | 3708 | INIT_LIST_HEAD(&dev_priv->mm.fence_list); |
be72615b | 3709 | INIT_LIST_HEAD(&dev_priv->mm.deferred_free_list); |
93a37f20 | 3710 | INIT_LIST_HEAD(&dev_priv->mm.gtt_list); |
1ec14ad3 CW |
3711 | for (i = 0; i < I915_NUM_RINGS; i++) |
3712 | init_ring_lists(&dev_priv->ring[i]); | |
4b9de737 | 3713 | for (i = 0; i < I915_MAX_NUM_FENCES; i++) |
007cc8ac | 3714 | INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list); |
673a394b EA |
3715 | INIT_DELAYED_WORK(&dev_priv->mm.retire_work, |
3716 | i915_gem_retire_work_handler); | |
30dbf0c0 | 3717 | init_completion(&dev_priv->error_completion); |
31169714 | 3718 | |
94400120 DA |
3719 | /* On GEN3 we really need to make sure the ARB C3 LP bit is set */ |
3720 | if (IS_GEN3(dev)) { | |
3721 | u32 tmp = I915_READ(MI_ARB_STATE); | |
3722 | if (!(tmp & MI_ARB_C3_LP_WRITE_ENABLE)) { | |
3723 | /* arb state is a masked write, so set bit + bit in mask */ | |
3724 | tmp = MI_ARB_C3_LP_WRITE_ENABLE | (MI_ARB_C3_LP_WRITE_ENABLE << MI_ARB_MASK_SHIFT); | |
3725 | I915_WRITE(MI_ARB_STATE, tmp); | |
3726 | } | |
3727 | } | |
3728 | ||
72bfa19c CW |
3729 | dev_priv->relative_constants_mode = I915_EXEC_CONSTANTS_REL_GENERAL; |
3730 | ||
de151cf6 | 3731 | /* Old X drivers will take 0-2 for front, back, depth buffers */ |
b397c836 EA |
3732 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) |
3733 | dev_priv->fence_reg_start = 3; | |
de151cf6 | 3734 | |
a6c45cf0 | 3735 | if (INTEL_INFO(dev)->gen >= 4 || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) |
de151cf6 JB |
3736 | dev_priv->num_fence_regs = 16; |
3737 | else | |
3738 | dev_priv->num_fence_regs = 8; | |
3739 | ||
b5aa8a0f | 3740 | /* Initialize fence registers to zero */ |
ada726c7 | 3741 | i915_gem_reset_fences(dev); |
10ed13e4 | 3742 | |
673a394b | 3743 | i915_gem_detect_bit_6_swizzle(dev); |
6b95a207 | 3744 | init_waitqueue_head(&dev_priv->pending_flip_queue); |
17250b71 | 3745 | |
ce453d81 CW |
3746 | dev_priv->mm.interruptible = true; |
3747 | ||
17250b71 CW |
3748 | dev_priv->mm.inactive_shrinker.shrink = i915_gem_inactive_shrink; |
3749 | dev_priv->mm.inactive_shrinker.seeks = DEFAULT_SEEKS; | |
3750 | register_shrinker(&dev_priv->mm.inactive_shrinker); | |
673a394b | 3751 | } |
71acb5eb DA |
3752 | |
3753 | /* | |
3754 | * Create a physically contiguous memory object for this object | |
3755 | * e.g. for cursor + overlay regs | |
3756 | */ | |
995b6762 CW |
3757 | static int i915_gem_init_phys_object(struct drm_device *dev, |
3758 | int id, int size, int align) | |
71acb5eb DA |
3759 | { |
3760 | drm_i915_private_t *dev_priv = dev->dev_private; | |
3761 | struct drm_i915_gem_phys_object *phys_obj; | |
3762 | int ret; | |
3763 | ||
3764 | if (dev_priv->mm.phys_objs[id - 1] || !size) | |
3765 | return 0; | |
3766 | ||
9a298b2a | 3767 | phys_obj = kzalloc(sizeof(struct drm_i915_gem_phys_object), GFP_KERNEL); |
71acb5eb DA |
3768 | if (!phys_obj) |
3769 | return -ENOMEM; | |
3770 | ||
3771 | phys_obj->id = id; | |
3772 | ||
6eeefaf3 | 3773 | phys_obj->handle = drm_pci_alloc(dev, size, align); |
71acb5eb DA |
3774 | if (!phys_obj->handle) { |
3775 | ret = -ENOMEM; | |
3776 | goto kfree_obj; | |
3777 | } | |
3778 | #ifdef CONFIG_X86 | |
3779 | set_memory_wc((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE); | |
3780 | #endif | |
3781 | ||
3782 | dev_priv->mm.phys_objs[id - 1] = phys_obj; | |
3783 | ||
3784 | return 0; | |
3785 | kfree_obj: | |
9a298b2a | 3786 | kfree(phys_obj); |
71acb5eb DA |
3787 | return ret; |
3788 | } | |
3789 | ||
995b6762 | 3790 | static void i915_gem_free_phys_object(struct drm_device *dev, int id) |
71acb5eb DA |
3791 | { |
3792 | drm_i915_private_t *dev_priv = dev->dev_private; | |
3793 | struct drm_i915_gem_phys_object *phys_obj; | |
3794 | ||
3795 | if (!dev_priv->mm.phys_objs[id - 1]) | |
3796 | return; | |
3797 | ||
3798 | phys_obj = dev_priv->mm.phys_objs[id - 1]; | |
3799 | if (phys_obj->cur_obj) { | |
3800 | i915_gem_detach_phys_object(dev, phys_obj->cur_obj); | |
3801 | } | |
3802 | ||
3803 | #ifdef CONFIG_X86 | |
3804 | set_memory_wb((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE); | |
3805 | #endif | |
3806 | drm_pci_free(dev, phys_obj->handle); | |
3807 | kfree(phys_obj); | |
3808 | dev_priv->mm.phys_objs[id - 1] = NULL; | |
3809 | } | |
3810 | ||
3811 | void i915_gem_free_all_phys_object(struct drm_device *dev) | |
3812 | { | |
3813 | int i; | |
3814 | ||
260883c8 | 3815 | for (i = I915_GEM_PHYS_CURSOR_0; i <= I915_MAX_PHYS_OBJECT; i++) |
71acb5eb DA |
3816 | i915_gem_free_phys_object(dev, i); |
3817 | } | |
3818 | ||
3819 | void i915_gem_detach_phys_object(struct drm_device *dev, | |
05394f39 | 3820 | struct drm_i915_gem_object *obj) |
71acb5eb | 3821 | { |
05394f39 | 3822 | struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping; |
e5281ccd | 3823 | char *vaddr; |
71acb5eb | 3824 | int i; |
71acb5eb DA |
3825 | int page_count; |
3826 | ||
05394f39 | 3827 | if (!obj->phys_obj) |
71acb5eb | 3828 | return; |
05394f39 | 3829 | vaddr = obj->phys_obj->handle->vaddr; |
71acb5eb | 3830 | |
05394f39 | 3831 | page_count = obj->base.size / PAGE_SIZE; |
71acb5eb | 3832 | for (i = 0; i < page_count; i++) { |
5949eac4 | 3833 | struct page *page = shmem_read_mapping_page(mapping, i); |
e5281ccd CW |
3834 | if (!IS_ERR(page)) { |
3835 | char *dst = kmap_atomic(page); | |
3836 | memcpy(dst, vaddr + i*PAGE_SIZE, PAGE_SIZE); | |
3837 | kunmap_atomic(dst); | |
3838 | ||
3839 | drm_clflush_pages(&page, 1); | |
3840 | ||
3841 | set_page_dirty(page); | |
3842 | mark_page_accessed(page); | |
3843 | page_cache_release(page); | |
3844 | } | |
71acb5eb | 3845 | } |
40ce6575 | 3846 | intel_gtt_chipset_flush(); |
d78b47b9 | 3847 | |
05394f39 CW |
3848 | obj->phys_obj->cur_obj = NULL; |
3849 | obj->phys_obj = NULL; | |
71acb5eb DA |
3850 | } |
3851 | ||
3852 | int | |
3853 | i915_gem_attach_phys_object(struct drm_device *dev, | |
05394f39 | 3854 | struct drm_i915_gem_object *obj, |
6eeefaf3 CW |
3855 | int id, |
3856 | int align) | |
71acb5eb | 3857 | { |
05394f39 | 3858 | struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping; |
71acb5eb | 3859 | drm_i915_private_t *dev_priv = dev->dev_private; |
71acb5eb DA |
3860 | int ret = 0; |
3861 | int page_count; | |
3862 | int i; | |
3863 | ||
3864 | if (id > I915_MAX_PHYS_OBJECT) | |
3865 | return -EINVAL; | |
3866 | ||
05394f39 CW |
3867 | if (obj->phys_obj) { |
3868 | if (obj->phys_obj->id == id) | |
71acb5eb DA |
3869 | return 0; |
3870 | i915_gem_detach_phys_object(dev, obj); | |
3871 | } | |
3872 | ||
71acb5eb DA |
3873 | /* create a new object */ |
3874 | if (!dev_priv->mm.phys_objs[id - 1]) { | |
3875 | ret = i915_gem_init_phys_object(dev, id, | |
05394f39 | 3876 | obj->base.size, align); |
71acb5eb | 3877 | if (ret) { |
05394f39 CW |
3878 | DRM_ERROR("failed to init phys object %d size: %zu\n", |
3879 | id, obj->base.size); | |
e5281ccd | 3880 | return ret; |
71acb5eb DA |
3881 | } |
3882 | } | |
3883 | ||
3884 | /* bind to the object */ | |
05394f39 CW |
3885 | obj->phys_obj = dev_priv->mm.phys_objs[id - 1]; |
3886 | obj->phys_obj->cur_obj = obj; | |
71acb5eb | 3887 | |
05394f39 | 3888 | page_count = obj->base.size / PAGE_SIZE; |
71acb5eb DA |
3889 | |
3890 | for (i = 0; i < page_count; i++) { | |
e5281ccd CW |
3891 | struct page *page; |
3892 | char *dst, *src; | |
3893 | ||
5949eac4 | 3894 | page = shmem_read_mapping_page(mapping, i); |
e5281ccd CW |
3895 | if (IS_ERR(page)) |
3896 | return PTR_ERR(page); | |
71acb5eb | 3897 | |
ff75b9bc | 3898 | src = kmap_atomic(page); |
05394f39 | 3899 | dst = obj->phys_obj->handle->vaddr + (i * PAGE_SIZE); |
71acb5eb | 3900 | memcpy(dst, src, PAGE_SIZE); |
3e4d3af5 | 3901 | kunmap_atomic(src); |
71acb5eb | 3902 | |
e5281ccd CW |
3903 | mark_page_accessed(page); |
3904 | page_cache_release(page); | |
3905 | } | |
d78b47b9 | 3906 | |
71acb5eb | 3907 | return 0; |
71acb5eb DA |
3908 | } |
3909 | ||
3910 | static int | |
05394f39 CW |
3911 | i915_gem_phys_pwrite(struct drm_device *dev, |
3912 | struct drm_i915_gem_object *obj, | |
71acb5eb DA |
3913 | struct drm_i915_gem_pwrite *args, |
3914 | struct drm_file *file_priv) | |
3915 | { | |
05394f39 | 3916 | void *vaddr = obj->phys_obj->handle->vaddr + args->offset; |
b47b30cc | 3917 | char __user *user_data = (char __user *) (uintptr_t) args->data_ptr; |
71acb5eb | 3918 | |
b47b30cc CW |
3919 | if (__copy_from_user_inatomic_nocache(vaddr, user_data, args->size)) { |
3920 | unsigned long unwritten; | |
3921 | ||
3922 | /* The physical object once assigned is fixed for the lifetime | |
3923 | * of the obj, so we can safely drop the lock and continue | |
3924 | * to access vaddr. | |
3925 | */ | |
3926 | mutex_unlock(&dev->struct_mutex); | |
3927 | unwritten = copy_from_user(vaddr, user_data, args->size); | |
3928 | mutex_lock(&dev->struct_mutex); | |
3929 | if (unwritten) | |
3930 | return -EFAULT; | |
3931 | } | |
71acb5eb | 3932 | |
40ce6575 | 3933 | intel_gtt_chipset_flush(); |
71acb5eb DA |
3934 | return 0; |
3935 | } | |
b962442e | 3936 | |
f787a5f5 | 3937 | void i915_gem_release(struct drm_device *dev, struct drm_file *file) |
b962442e | 3938 | { |
f787a5f5 | 3939 | struct drm_i915_file_private *file_priv = file->driver_priv; |
b962442e EA |
3940 | |
3941 | /* Clean up our request list when the client is going away, so that | |
3942 | * later retire_requests won't dereference our soon-to-be-gone | |
3943 | * file_priv. | |
3944 | */ | |
1c25595f | 3945 | spin_lock(&file_priv->mm.lock); |
f787a5f5 CW |
3946 | while (!list_empty(&file_priv->mm.request_list)) { |
3947 | struct drm_i915_gem_request *request; | |
3948 | ||
3949 | request = list_first_entry(&file_priv->mm.request_list, | |
3950 | struct drm_i915_gem_request, | |
3951 | client_list); | |
3952 | list_del(&request->client_list); | |
3953 | request->file_priv = NULL; | |
3954 | } | |
1c25595f | 3955 | spin_unlock(&file_priv->mm.lock); |
b962442e | 3956 | } |
31169714 | 3957 | |
1637ef41 CW |
3958 | static int |
3959 | i915_gpu_is_active(struct drm_device *dev) | |
3960 | { | |
3961 | drm_i915_private_t *dev_priv = dev->dev_private; | |
3962 | int lists_empty; | |
3963 | ||
1637ef41 | 3964 | lists_empty = list_empty(&dev_priv->mm.flushing_list) && |
17250b71 | 3965 | list_empty(&dev_priv->mm.active_list); |
1637ef41 CW |
3966 | |
3967 | return !lists_empty; | |
3968 | } | |
3969 | ||
31169714 | 3970 | static int |
1495f230 | 3971 | i915_gem_inactive_shrink(struct shrinker *shrinker, struct shrink_control *sc) |
31169714 | 3972 | { |
17250b71 CW |
3973 | struct drm_i915_private *dev_priv = |
3974 | container_of(shrinker, | |
3975 | struct drm_i915_private, | |
3976 | mm.inactive_shrinker); | |
3977 | struct drm_device *dev = dev_priv->dev; | |
3978 | struct drm_i915_gem_object *obj, *next; | |
1495f230 | 3979 | int nr_to_scan = sc->nr_to_scan; |
17250b71 CW |
3980 | int cnt; |
3981 | ||
3982 | if (!mutex_trylock(&dev->struct_mutex)) | |
bbe2e11a | 3983 | return 0; |
31169714 CW |
3984 | |
3985 | /* "fast-path" to count number of available objects */ | |
3986 | if (nr_to_scan == 0) { | |
17250b71 CW |
3987 | cnt = 0; |
3988 | list_for_each_entry(obj, | |
3989 | &dev_priv->mm.inactive_list, | |
3990 | mm_list) | |
3991 | cnt++; | |
3992 | mutex_unlock(&dev->struct_mutex); | |
3993 | return cnt / 100 * sysctl_vfs_cache_pressure; | |
31169714 CW |
3994 | } |
3995 | ||
1637ef41 | 3996 | rescan: |
31169714 | 3997 | /* first scan for clean buffers */ |
17250b71 | 3998 | i915_gem_retire_requests(dev); |
31169714 | 3999 | |
17250b71 CW |
4000 | list_for_each_entry_safe(obj, next, |
4001 | &dev_priv->mm.inactive_list, | |
4002 | mm_list) { | |
4003 | if (i915_gem_object_is_purgeable(obj)) { | |
2021746e CW |
4004 | if (i915_gem_object_unbind(obj) == 0 && |
4005 | --nr_to_scan == 0) | |
17250b71 | 4006 | break; |
31169714 | 4007 | } |
31169714 CW |
4008 | } |
4009 | ||
4010 | /* second pass, evict/count anything still on the inactive list */ | |
17250b71 CW |
4011 | cnt = 0; |
4012 | list_for_each_entry_safe(obj, next, | |
4013 | &dev_priv->mm.inactive_list, | |
4014 | mm_list) { | |
2021746e CW |
4015 | if (nr_to_scan && |
4016 | i915_gem_object_unbind(obj) == 0) | |
17250b71 | 4017 | nr_to_scan--; |
2021746e | 4018 | else |
17250b71 CW |
4019 | cnt++; |
4020 | } | |
4021 | ||
4022 | if (nr_to_scan && i915_gpu_is_active(dev)) { | |
1637ef41 CW |
4023 | /* |
4024 | * We are desperate for pages, so as a last resort, wait | |
4025 | * for the GPU to finish and discard whatever we can. | |
4026 | * This has a dramatic impact to reduce the number of | |
4027 | * OOM-killer events whilst running the GPU aggressively. | |
4028 | */ | |
b93f9cf1 | 4029 | if (i915_gpu_idle(dev, true) == 0) |
1637ef41 CW |
4030 | goto rescan; |
4031 | } | |
17250b71 CW |
4032 | mutex_unlock(&dev->struct_mutex); |
4033 | return cnt / 100 * sysctl_vfs_cache_pressure; | |
31169714 | 4034 | } |