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Commit | Line | Data |
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673a394b EA |
1 | /* |
2 | * Copyright © 2008 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | * | |
26 | */ | |
27 | ||
28 | #include "drmP.h" | |
29 | #include "drm.h" | |
30 | #include "i915_drm.h" | |
31 | #include "i915_drv.h" | |
1c5d22f7 | 32 | #include "i915_trace.h" |
652c393a | 33 | #include "intel_drv.h" |
5a0e3ad6 | 34 | #include <linux/slab.h> |
673a394b | 35 | #include <linux/swap.h> |
79e53945 | 36 | #include <linux/pci.h> |
673a394b | 37 | |
3619df03 | 38 | static void i915_gem_object_flush_gpu_write_domain(struct drm_i915_gem_object *obj); |
05394f39 CW |
39 | static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj); |
40 | static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj); | |
41 | static int i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, | |
919926ae | 42 | bool write); |
05394f39 | 43 | static int i915_gem_object_set_cpu_read_domain_range(struct drm_i915_gem_object *obj, |
e47c68e9 EA |
44 | uint64_t offset, |
45 | uint64_t size); | |
05394f39 | 46 | static void i915_gem_object_set_to_full_cpu_read_domain(struct drm_i915_gem_object *obj); |
05394f39 | 47 | static int i915_gem_object_bind_to_gtt(struct drm_i915_gem_object *obj, |
a00b10c3 | 48 | unsigned alignment, |
75e9e915 | 49 | bool map_and_fenceable); |
05394f39 CW |
50 | static void i915_gem_clear_fence_reg(struct drm_i915_gem_object *obj); |
51 | static int i915_gem_phys_pwrite(struct drm_device *dev, | |
52 | struct drm_i915_gem_object *obj, | |
71acb5eb | 53 | struct drm_i915_gem_pwrite *args, |
05394f39 CW |
54 | struct drm_file *file); |
55 | static void i915_gem_free_object_tail(struct drm_i915_gem_object *obj); | |
673a394b | 56 | |
17250b71 CW |
57 | static int i915_gem_inactive_shrink(struct shrinker *shrinker, |
58 | int nr_to_scan, | |
59 | gfp_t gfp_mask); | |
60 | ||
31169714 | 61 | |
73aa808f CW |
62 | /* some bookkeeping */ |
63 | static void i915_gem_info_add_obj(struct drm_i915_private *dev_priv, | |
64 | size_t size) | |
65 | { | |
66 | dev_priv->mm.object_count++; | |
67 | dev_priv->mm.object_memory += size; | |
68 | } | |
69 | ||
70 | static void i915_gem_info_remove_obj(struct drm_i915_private *dev_priv, | |
71 | size_t size) | |
72 | { | |
73 | dev_priv->mm.object_count--; | |
74 | dev_priv->mm.object_memory -= size; | |
75 | } | |
76 | ||
30dbf0c0 CW |
77 | int |
78 | i915_gem_check_is_wedged(struct drm_device *dev) | |
79 | { | |
80 | struct drm_i915_private *dev_priv = dev->dev_private; | |
81 | struct completion *x = &dev_priv->error_completion; | |
82 | unsigned long flags; | |
83 | int ret; | |
84 | ||
85 | if (!atomic_read(&dev_priv->mm.wedged)) | |
86 | return 0; | |
87 | ||
88 | ret = wait_for_completion_interruptible(x); | |
89 | if (ret) | |
90 | return ret; | |
91 | ||
92 | /* Success, we reset the GPU! */ | |
93 | if (!atomic_read(&dev_priv->mm.wedged)) | |
94 | return 0; | |
95 | ||
96 | /* GPU is hung, bump the completion count to account for | |
97 | * the token we just consumed so that we never hit zero and | |
98 | * end up waiting upon a subsequent completion event that | |
99 | * will never happen. | |
100 | */ | |
101 | spin_lock_irqsave(&x->wait.lock, flags); | |
102 | x->done++; | |
103 | spin_unlock_irqrestore(&x->wait.lock, flags); | |
104 | return -EIO; | |
105 | } | |
106 | ||
54cf91dc | 107 | int i915_mutex_lock_interruptible(struct drm_device *dev) |
76c1dec1 CW |
108 | { |
109 | struct drm_i915_private *dev_priv = dev->dev_private; | |
110 | int ret; | |
111 | ||
112 | ret = i915_gem_check_is_wedged(dev); | |
113 | if (ret) | |
114 | return ret; | |
115 | ||
116 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
117 | if (ret) | |
118 | return ret; | |
119 | ||
120 | if (atomic_read(&dev_priv->mm.wedged)) { | |
121 | mutex_unlock(&dev->struct_mutex); | |
122 | return -EAGAIN; | |
123 | } | |
124 | ||
23bc5982 | 125 | WARN_ON(i915_verify_lists(dev)); |
76c1dec1 CW |
126 | return 0; |
127 | } | |
30dbf0c0 | 128 | |
7d1c4804 | 129 | static inline bool |
05394f39 | 130 | i915_gem_object_is_inactive(struct drm_i915_gem_object *obj) |
7d1c4804 | 131 | { |
05394f39 | 132 | return obj->gtt_space && !obj->active && obj->pin_count == 0; |
7d1c4804 CW |
133 | } |
134 | ||
2021746e CW |
135 | void i915_gem_do_init(struct drm_device *dev, |
136 | unsigned long start, | |
137 | unsigned long mappable_end, | |
138 | unsigned long end) | |
673a394b EA |
139 | { |
140 | drm_i915_private_t *dev_priv = dev->dev_private; | |
673a394b | 141 | |
79e53945 JB |
142 | drm_mm_init(&dev_priv->mm.gtt_space, start, |
143 | end - start); | |
673a394b | 144 | |
73aa808f | 145 | dev_priv->mm.gtt_total = end - start; |
fb7d516a | 146 | dev_priv->mm.mappable_gtt_total = min(end, mappable_end) - start; |
53984635 | 147 | dev_priv->mm.gtt_mappable_end = mappable_end; |
79e53945 | 148 | } |
673a394b | 149 | |
79e53945 JB |
150 | int |
151 | i915_gem_init_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 152 | struct drm_file *file) |
79e53945 JB |
153 | { |
154 | struct drm_i915_gem_init *args = data; | |
2021746e CW |
155 | |
156 | if (args->gtt_start >= args->gtt_end || | |
157 | (args->gtt_end | args->gtt_start) & (PAGE_SIZE - 1)) | |
158 | return -EINVAL; | |
79e53945 JB |
159 | |
160 | mutex_lock(&dev->struct_mutex); | |
2021746e | 161 | i915_gem_do_init(dev, args->gtt_start, args->gtt_end, args->gtt_end); |
673a394b EA |
162 | mutex_unlock(&dev->struct_mutex); |
163 | ||
2021746e | 164 | return 0; |
673a394b EA |
165 | } |
166 | ||
5a125c3c EA |
167 | int |
168 | i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 169 | struct drm_file *file) |
5a125c3c | 170 | { |
73aa808f | 171 | struct drm_i915_private *dev_priv = dev->dev_private; |
5a125c3c | 172 | struct drm_i915_gem_get_aperture *args = data; |
6299f992 CW |
173 | struct drm_i915_gem_object *obj; |
174 | size_t pinned; | |
5a125c3c EA |
175 | |
176 | if (!(dev->driver->driver_features & DRIVER_GEM)) | |
177 | return -ENODEV; | |
178 | ||
6299f992 | 179 | pinned = 0; |
73aa808f | 180 | mutex_lock(&dev->struct_mutex); |
6299f992 CW |
181 | list_for_each_entry(obj, &dev_priv->mm.pinned_list, mm_list) |
182 | pinned += obj->gtt_space->size; | |
73aa808f | 183 | mutex_unlock(&dev->struct_mutex); |
5a125c3c | 184 | |
6299f992 CW |
185 | args->aper_size = dev_priv->mm.gtt_total; |
186 | args->aper_available_size = args->aper_size -pinned; | |
187 | ||
5a125c3c EA |
188 | return 0; |
189 | } | |
190 | ||
673a394b EA |
191 | /** |
192 | * Creates a new mm object and returns a handle to it. | |
193 | */ | |
194 | int | |
195 | i915_gem_create_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 196 | struct drm_file *file) |
673a394b EA |
197 | { |
198 | struct drm_i915_gem_create *args = data; | |
05394f39 | 199 | struct drm_i915_gem_object *obj; |
a1a2d1d3 PP |
200 | int ret; |
201 | u32 handle; | |
673a394b EA |
202 | |
203 | args->size = roundup(args->size, PAGE_SIZE); | |
204 | ||
205 | /* Allocate the new object */ | |
ac52bc56 | 206 | obj = i915_gem_alloc_object(dev, args->size); |
673a394b EA |
207 | if (obj == NULL) |
208 | return -ENOMEM; | |
209 | ||
05394f39 | 210 | ret = drm_gem_handle_create(file, &obj->base, &handle); |
1dfd9754 | 211 | if (ret) { |
05394f39 CW |
212 | drm_gem_object_release(&obj->base); |
213 | i915_gem_info_remove_obj(dev->dev_private, obj->base.size); | |
202f2fef | 214 | kfree(obj); |
673a394b | 215 | return ret; |
1dfd9754 | 216 | } |
673a394b | 217 | |
202f2fef | 218 | /* drop reference from allocate - handle holds it now */ |
05394f39 | 219 | drm_gem_object_unreference(&obj->base); |
202f2fef CW |
220 | trace_i915_gem_object_create(obj); |
221 | ||
1dfd9754 | 222 | args->handle = handle; |
673a394b EA |
223 | return 0; |
224 | } | |
225 | ||
05394f39 | 226 | static int i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj) |
280b713b | 227 | { |
05394f39 | 228 | drm_i915_private_t *dev_priv = obj->base.dev->dev_private; |
280b713b EA |
229 | |
230 | return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 && | |
05394f39 | 231 | obj->tiling_mode != I915_TILING_NONE; |
280b713b EA |
232 | } |
233 | ||
99a03df5 | 234 | static inline void |
40123c1f EA |
235 | slow_shmem_copy(struct page *dst_page, |
236 | int dst_offset, | |
237 | struct page *src_page, | |
238 | int src_offset, | |
239 | int length) | |
240 | { | |
241 | char *dst_vaddr, *src_vaddr; | |
242 | ||
99a03df5 CW |
243 | dst_vaddr = kmap(dst_page); |
244 | src_vaddr = kmap(src_page); | |
40123c1f EA |
245 | |
246 | memcpy(dst_vaddr + dst_offset, src_vaddr + src_offset, length); | |
247 | ||
99a03df5 CW |
248 | kunmap(src_page); |
249 | kunmap(dst_page); | |
40123c1f EA |
250 | } |
251 | ||
99a03df5 | 252 | static inline void |
280b713b EA |
253 | slow_shmem_bit17_copy(struct page *gpu_page, |
254 | int gpu_offset, | |
255 | struct page *cpu_page, | |
256 | int cpu_offset, | |
257 | int length, | |
258 | int is_read) | |
259 | { | |
260 | char *gpu_vaddr, *cpu_vaddr; | |
261 | ||
262 | /* Use the unswizzled path if this page isn't affected. */ | |
263 | if ((page_to_phys(gpu_page) & (1 << 17)) == 0) { | |
264 | if (is_read) | |
265 | return slow_shmem_copy(cpu_page, cpu_offset, | |
266 | gpu_page, gpu_offset, length); | |
267 | else | |
268 | return slow_shmem_copy(gpu_page, gpu_offset, | |
269 | cpu_page, cpu_offset, length); | |
270 | } | |
271 | ||
99a03df5 CW |
272 | gpu_vaddr = kmap(gpu_page); |
273 | cpu_vaddr = kmap(cpu_page); | |
280b713b EA |
274 | |
275 | /* Copy the data, XORing A6 with A17 (1). The user already knows he's | |
276 | * XORing with the other bits (A9 for Y, A9 and A10 for X) | |
277 | */ | |
278 | while (length > 0) { | |
279 | int cacheline_end = ALIGN(gpu_offset + 1, 64); | |
280 | int this_length = min(cacheline_end - gpu_offset, length); | |
281 | int swizzled_gpu_offset = gpu_offset ^ 64; | |
282 | ||
283 | if (is_read) { | |
284 | memcpy(cpu_vaddr + cpu_offset, | |
285 | gpu_vaddr + swizzled_gpu_offset, | |
286 | this_length); | |
287 | } else { | |
288 | memcpy(gpu_vaddr + swizzled_gpu_offset, | |
289 | cpu_vaddr + cpu_offset, | |
290 | this_length); | |
291 | } | |
292 | cpu_offset += this_length; | |
293 | gpu_offset += this_length; | |
294 | length -= this_length; | |
295 | } | |
296 | ||
99a03df5 CW |
297 | kunmap(cpu_page); |
298 | kunmap(gpu_page); | |
280b713b EA |
299 | } |
300 | ||
eb01459f EA |
301 | /** |
302 | * This is the fast shmem pread path, which attempts to copy_from_user directly | |
303 | * from the backing pages of the object to the user's address space. On a | |
304 | * fault, it fails so we can fall back to i915_gem_shmem_pwrite_slow(). | |
305 | */ | |
306 | static int | |
05394f39 CW |
307 | i915_gem_shmem_pread_fast(struct drm_device *dev, |
308 | struct drm_i915_gem_object *obj, | |
eb01459f | 309 | struct drm_i915_gem_pread *args, |
05394f39 | 310 | struct drm_file *file) |
eb01459f | 311 | { |
05394f39 | 312 | struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping; |
eb01459f | 313 | ssize_t remain; |
e5281ccd | 314 | loff_t offset; |
eb01459f EA |
315 | char __user *user_data; |
316 | int page_offset, page_length; | |
eb01459f EA |
317 | |
318 | user_data = (char __user *) (uintptr_t) args->data_ptr; | |
319 | remain = args->size; | |
320 | ||
eb01459f EA |
321 | offset = args->offset; |
322 | ||
323 | while (remain > 0) { | |
e5281ccd CW |
324 | struct page *page; |
325 | char *vaddr; | |
326 | int ret; | |
327 | ||
eb01459f EA |
328 | /* Operation in this page |
329 | * | |
eb01459f EA |
330 | * page_offset = offset within page |
331 | * page_length = bytes to copy for this page | |
332 | */ | |
eb01459f EA |
333 | page_offset = offset & (PAGE_SIZE-1); |
334 | page_length = remain; | |
335 | if ((page_offset + remain) > PAGE_SIZE) | |
336 | page_length = PAGE_SIZE - page_offset; | |
337 | ||
e5281ccd CW |
338 | page = read_cache_page_gfp(mapping, offset >> PAGE_SHIFT, |
339 | GFP_HIGHUSER | __GFP_RECLAIMABLE); | |
340 | if (IS_ERR(page)) | |
341 | return PTR_ERR(page); | |
342 | ||
343 | vaddr = kmap_atomic(page); | |
344 | ret = __copy_to_user_inatomic(user_data, | |
345 | vaddr + page_offset, | |
346 | page_length); | |
347 | kunmap_atomic(vaddr); | |
348 | ||
349 | mark_page_accessed(page); | |
350 | page_cache_release(page); | |
351 | if (ret) | |
4f27b75d | 352 | return -EFAULT; |
eb01459f EA |
353 | |
354 | remain -= page_length; | |
355 | user_data += page_length; | |
356 | offset += page_length; | |
357 | } | |
358 | ||
4f27b75d | 359 | return 0; |
eb01459f EA |
360 | } |
361 | ||
362 | /** | |
363 | * This is the fallback shmem pread path, which allocates temporary storage | |
364 | * in kernel space to copy_to_user into outside of the struct_mutex, so we | |
365 | * can copy out of the object's backing pages while holding the struct mutex | |
366 | * and not take page faults. | |
367 | */ | |
368 | static int | |
05394f39 CW |
369 | i915_gem_shmem_pread_slow(struct drm_device *dev, |
370 | struct drm_i915_gem_object *obj, | |
eb01459f | 371 | struct drm_i915_gem_pread *args, |
05394f39 | 372 | struct drm_file *file) |
eb01459f | 373 | { |
05394f39 | 374 | struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping; |
eb01459f EA |
375 | struct mm_struct *mm = current->mm; |
376 | struct page **user_pages; | |
377 | ssize_t remain; | |
378 | loff_t offset, pinned_pages, i; | |
379 | loff_t first_data_page, last_data_page, num_pages; | |
e5281ccd CW |
380 | int shmem_page_offset; |
381 | int data_page_index, data_page_offset; | |
eb01459f EA |
382 | int page_length; |
383 | int ret; | |
384 | uint64_t data_ptr = args->data_ptr; | |
280b713b | 385 | int do_bit17_swizzling; |
eb01459f EA |
386 | |
387 | remain = args->size; | |
388 | ||
389 | /* Pin the user pages containing the data. We can't fault while | |
390 | * holding the struct mutex, yet we want to hold it while | |
391 | * dereferencing the user data. | |
392 | */ | |
393 | first_data_page = data_ptr / PAGE_SIZE; | |
394 | last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE; | |
395 | num_pages = last_data_page - first_data_page + 1; | |
396 | ||
4f27b75d | 397 | user_pages = drm_malloc_ab(num_pages, sizeof(struct page *)); |
eb01459f EA |
398 | if (user_pages == NULL) |
399 | return -ENOMEM; | |
400 | ||
4f27b75d | 401 | mutex_unlock(&dev->struct_mutex); |
eb01459f EA |
402 | down_read(&mm->mmap_sem); |
403 | pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr, | |
e5e9ecde | 404 | num_pages, 1, 0, user_pages, NULL); |
eb01459f | 405 | up_read(&mm->mmap_sem); |
4f27b75d | 406 | mutex_lock(&dev->struct_mutex); |
eb01459f EA |
407 | if (pinned_pages < num_pages) { |
408 | ret = -EFAULT; | |
4f27b75d | 409 | goto out; |
eb01459f EA |
410 | } |
411 | ||
4f27b75d CW |
412 | ret = i915_gem_object_set_cpu_read_domain_range(obj, |
413 | args->offset, | |
414 | args->size); | |
07f73f69 | 415 | if (ret) |
4f27b75d | 416 | goto out; |
eb01459f | 417 | |
4f27b75d | 418 | do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj); |
eb01459f | 419 | |
eb01459f EA |
420 | offset = args->offset; |
421 | ||
422 | while (remain > 0) { | |
e5281ccd CW |
423 | struct page *page; |
424 | ||
eb01459f EA |
425 | /* Operation in this page |
426 | * | |
eb01459f EA |
427 | * shmem_page_offset = offset within page in shmem file |
428 | * data_page_index = page number in get_user_pages return | |
429 | * data_page_offset = offset with data_page_index page. | |
430 | * page_length = bytes to copy for this page | |
431 | */ | |
eb01459f EA |
432 | shmem_page_offset = offset & ~PAGE_MASK; |
433 | data_page_index = data_ptr / PAGE_SIZE - first_data_page; | |
434 | data_page_offset = data_ptr & ~PAGE_MASK; | |
435 | ||
436 | page_length = remain; | |
437 | if ((shmem_page_offset + page_length) > PAGE_SIZE) | |
438 | page_length = PAGE_SIZE - shmem_page_offset; | |
439 | if ((data_page_offset + page_length) > PAGE_SIZE) | |
440 | page_length = PAGE_SIZE - data_page_offset; | |
441 | ||
e5281ccd CW |
442 | page = read_cache_page_gfp(mapping, offset >> PAGE_SHIFT, |
443 | GFP_HIGHUSER | __GFP_RECLAIMABLE); | |
444 | if (IS_ERR(page)) | |
445 | return PTR_ERR(page); | |
446 | ||
280b713b | 447 | if (do_bit17_swizzling) { |
e5281ccd | 448 | slow_shmem_bit17_copy(page, |
280b713b | 449 | shmem_page_offset, |
99a03df5 CW |
450 | user_pages[data_page_index], |
451 | data_page_offset, | |
452 | page_length, | |
453 | 1); | |
454 | } else { | |
455 | slow_shmem_copy(user_pages[data_page_index], | |
456 | data_page_offset, | |
e5281ccd | 457 | page, |
99a03df5 CW |
458 | shmem_page_offset, |
459 | page_length); | |
280b713b | 460 | } |
eb01459f | 461 | |
e5281ccd CW |
462 | mark_page_accessed(page); |
463 | page_cache_release(page); | |
464 | ||
eb01459f EA |
465 | remain -= page_length; |
466 | data_ptr += page_length; | |
467 | offset += page_length; | |
468 | } | |
469 | ||
4f27b75d | 470 | out: |
eb01459f EA |
471 | for (i = 0; i < pinned_pages; i++) { |
472 | SetPageDirty(user_pages[i]); | |
e5281ccd | 473 | mark_page_accessed(user_pages[i]); |
eb01459f EA |
474 | page_cache_release(user_pages[i]); |
475 | } | |
8e7d2b2c | 476 | drm_free_large(user_pages); |
eb01459f EA |
477 | |
478 | return ret; | |
479 | } | |
480 | ||
673a394b EA |
481 | /** |
482 | * Reads data from the object referenced by handle. | |
483 | * | |
484 | * On error, the contents of *data are undefined. | |
485 | */ | |
486 | int | |
487 | i915_gem_pread_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 488 | struct drm_file *file) |
673a394b EA |
489 | { |
490 | struct drm_i915_gem_pread *args = data; | |
05394f39 | 491 | struct drm_i915_gem_object *obj; |
35b62a89 | 492 | int ret = 0; |
673a394b | 493 | |
51311d0a CW |
494 | if (args->size == 0) |
495 | return 0; | |
496 | ||
497 | if (!access_ok(VERIFY_WRITE, | |
498 | (char __user *)(uintptr_t)args->data_ptr, | |
499 | args->size)) | |
500 | return -EFAULT; | |
501 | ||
502 | ret = fault_in_pages_writeable((char __user *)(uintptr_t)args->data_ptr, | |
503 | args->size); | |
504 | if (ret) | |
505 | return -EFAULT; | |
506 | ||
4f27b75d | 507 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 508 | if (ret) |
4f27b75d | 509 | return ret; |
673a394b | 510 | |
05394f39 | 511 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
1d7cfea1 CW |
512 | if (obj == NULL) { |
513 | ret = -ENOENT; | |
514 | goto unlock; | |
4f27b75d | 515 | } |
673a394b | 516 | |
7dcd2499 | 517 | /* Bounds check source. */ |
05394f39 CW |
518 | if (args->offset > obj->base.size || |
519 | args->size > obj->base.size - args->offset) { | |
ce9d419d | 520 | ret = -EINVAL; |
35b62a89 | 521 | goto out; |
ce9d419d CW |
522 | } |
523 | ||
4f27b75d CW |
524 | ret = i915_gem_object_set_cpu_read_domain_range(obj, |
525 | args->offset, | |
526 | args->size); | |
527 | if (ret) | |
e5281ccd | 528 | goto out; |
4f27b75d CW |
529 | |
530 | ret = -EFAULT; | |
531 | if (!i915_gem_object_needs_bit17_swizzle(obj)) | |
05394f39 | 532 | ret = i915_gem_shmem_pread_fast(dev, obj, args, file); |
4f27b75d | 533 | if (ret == -EFAULT) |
05394f39 | 534 | ret = i915_gem_shmem_pread_slow(dev, obj, args, file); |
673a394b | 535 | |
35b62a89 | 536 | out: |
05394f39 | 537 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 538 | unlock: |
4f27b75d | 539 | mutex_unlock(&dev->struct_mutex); |
eb01459f | 540 | return ret; |
673a394b EA |
541 | } |
542 | ||
0839ccb8 KP |
543 | /* This is the fast write path which cannot handle |
544 | * page faults in the source data | |
9b7530cc | 545 | */ |
0839ccb8 KP |
546 | |
547 | static inline int | |
548 | fast_user_write(struct io_mapping *mapping, | |
549 | loff_t page_base, int page_offset, | |
550 | char __user *user_data, | |
551 | int length) | |
9b7530cc | 552 | { |
9b7530cc | 553 | char *vaddr_atomic; |
0839ccb8 | 554 | unsigned long unwritten; |
9b7530cc | 555 | |
3e4d3af5 | 556 | vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base); |
0839ccb8 KP |
557 | unwritten = __copy_from_user_inatomic_nocache(vaddr_atomic + page_offset, |
558 | user_data, length); | |
3e4d3af5 | 559 | io_mapping_unmap_atomic(vaddr_atomic); |
fbd5a26d | 560 | return unwritten; |
0839ccb8 KP |
561 | } |
562 | ||
563 | /* Here's the write path which can sleep for | |
564 | * page faults | |
565 | */ | |
566 | ||
ab34c226 | 567 | static inline void |
3de09aa3 EA |
568 | slow_kernel_write(struct io_mapping *mapping, |
569 | loff_t gtt_base, int gtt_offset, | |
570 | struct page *user_page, int user_offset, | |
571 | int length) | |
0839ccb8 | 572 | { |
ab34c226 CW |
573 | char __iomem *dst_vaddr; |
574 | char *src_vaddr; | |
0839ccb8 | 575 | |
ab34c226 CW |
576 | dst_vaddr = io_mapping_map_wc(mapping, gtt_base); |
577 | src_vaddr = kmap(user_page); | |
578 | ||
579 | memcpy_toio(dst_vaddr + gtt_offset, | |
580 | src_vaddr + user_offset, | |
581 | length); | |
582 | ||
583 | kunmap(user_page); | |
584 | io_mapping_unmap(dst_vaddr); | |
9b7530cc LT |
585 | } |
586 | ||
3de09aa3 EA |
587 | /** |
588 | * This is the fast pwrite path, where we copy the data directly from the | |
589 | * user into the GTT, uncached. | |
590 | */ | |
673a394b | 591 | static int |
05394f39 CW |
592 | i915_gem_gtt_pwrite_fast(struct drm_device *dev, |
593 | struct drm_i915_gem_object *obj, | |
3de09aa3 | 594 | struct drm_i915_gem_pwrite *args, |
05394f39 | 595 | struct drm_file *file) |
673a394b | 596 | { |
0839ccb8 | 597 | drm_i915_private_t *dev_priv = dev->dev_private; |
673a394b | 598 | ssize_t remain; |
0839ccb8 | 599 | loff_t offset, page_base; |
673a394b | 600 | char __user *user_data; |
0839ccb8 | 601 | int page_offset, page_length; |
673a394b EA |
602 | |
603 | user_data = (char __user *) (uintptr_t) args->data_ptr; | |
604 | remain = args->size; | |
673a394b | 605 | |
05394f39 | 606 | offset = obj->gtt_offset + args->offset; |
673a394b EA |
607 | |
608 | while (remain > 0) { | |
609 | /* Operation in this page | |
610 | * | |
0839ccb8 KP |
611 | * page_base = page offset within aperture |
612 | * page_offset = offset within page | |
613 | * page_length = bytes to copy for this page | |
673a394b | 614 | */ |
0839ccb8 KP |
615 | page_base = (offset & ~(PAGE_SIZE-1)); |
616 | page_offset = offset & (PAGE_SIZE-1); | |
617 | page_length = remain; | |
618 | if ((page_offset + remain) > PAGE_SIZE) | |
619 | page_length = PAGE_SIZE - page_offset; | |
620 | ||
0839ccb8 | 621 | /* If we get a fault while copying data, then (presumably) our |
3de09aa3 EA |
622 | * source page isn't available. Return the error and we'll |
623 | * retry in the slow path. | |
0839ccb8 | 624 | */ |
fbd5a26d CW |
625 | if (fast_user_write(dev_priv->mm.gtt_mapping, page_base, |
626 | page_offset, user_data, page_length)) | |
627 | ||
628 | return -EFAULT; | |
673a394b | 629 | |
0839ccb8 KP |
630 | remain -= page_length; |
631 | user_data += page_length; | |
632 | offset += page_length; | |
673a394b | 633 | } |
673a394b | 634 | |
fbd5a26d | 635 | return 0; |
673a394b EA |
636 | } |
637 | ||
3de09aa3 EA |
638 | /** |
639 | * This is the fallback GTT pwrite path, which uses get_user_pages to pin | |
640 | * the memory and maps it using kmap_atomic for copying. | |
641 | * | |
642 | * This code resulted in x11perf -rgb10text consuming about 10% more CPU | |
643 | * than using i915_gem_gtt_pwrite_fast on a G45 (32-bit). | |
644 | */ | |
3043c60c | 645 | static int |
05394f39 CW |
646 | i915_gem_gtt_pwrite_slow(struct drm_device *dev, |
647 | struct drm_i915_gem_object *obj, | |
3de09aa3 | 648 | struct drm_i915_gem_pwrite *args, |
05394f39 | 649 | struct drm_file *file) |
673a394b | 650 | { |
3de09aa3 EA |
651 | drm_i915_private_t *dev_priv = dev->dev_private; |
652 | ssize_t remain; | |
653 | loff_t gtt_page_base, offset; | |
654 | loff_t first_data_page, last_data_page, num_pages; | |
655 | loff_t pinned_pages, i; | |
656 | struct page **user_pages; | |
657 | struct mm_struct *mm = current->mm; | |
658 | int gtt_page_offset, data_page_offset, data_page_index, page_length; | |
673a394b | 659 | int ret; |
3de09aa3 EA |
660 | uint64_t data_ptr = args->data_ptr; |
661 | ||
662 | remain = args->size; | |
663 | ||
664 | /* Pin the user pages containing the data. We can't fault while | |
665 | * holding the struct mutex, and all of the pwrite implementations | |
666 | * want to hold it while dereferencing the user data. | |
667 | */ | |
668 | first_data_page = data_ptr / PAGE_SIZE; | |
669 | last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE; | |
670 | num_pages = last_data_page - first_data_page + 1; | |
671 | ||
fbd5a26d | 672 | user_pages = drm_malloc_ab(num_pages, sizeof(struct page *)); |
3de09aa3 EA |
673 | if (user_pages == NULL) |
674 | return -ENOMEM; | |
675 | ||
fbd5a26d | 676 | mutex_unlock(&dev->struct_mutex); |
3de09aa3 EA |
677 | down_read(&mm->mmap_sem); |
678 | pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr, | |
679 | num_pages, 0, 0, user_pages, NULL); | |
680 | up_read(&mm->mmap_sem); | |
fbd5a26d | 681 | mutex_lock(&dev->struct_mutex); |
3de09aa3 EA |
682 | if (pinned_pages < num_pages) { |
683 | ret = -EFAULT; | |
684 | goto out_unpin_pages; | |
685 | } | |
673a394b | 686 | |
3de09aa3 EA |
687 | ret = i915_gem_object_set_to_gtt_domain(obj, 1); |
688 | if (ret) | |
fbd5a26d | 689 | goto out_unpin_pages; |
3de09aa3 | 690 | |
05394f39 | 691 | offset = obj->gtt_offset + args->offset; |
3de09aa3 EA |
692 | |
693 | while (remain > 0) { | |
694 | /* Operation in this page | |
695 | * | |
696 | * gtt_page_base = page offset within aperture | |
697 | * gtt_page_offset = offset within page in aperture | |
698 | * data_page_index = page number in get_user_pages return | |
699 | * data_page_offset = offset with data_page_index page. | |
700 | * page_length = bytes to copy for this page | |
701 | */ | |
702 | gtt_page_base = offset & PAGE_MASK; | |
703 | gtt_page_offset = offset & ~PAGE_MASK; | |
704 | data_page_index = data_ptr / PAGE_SIZE - first_data_page; | |
705 | data_page_offset = data_ptr & ~PAGE_MASK; | |
706 | ||
707 | page_length = remain; | |
708 | if ((gtt_page_offset + page_length) > PAGE_SIZE) | |
709 | page_length = PAGE_SIZE - gtt_page_offset; | |
710 | if ((data_page_offset + page_length) > PAGE_SIZE) | |
711 | page_length = PAGE_SIZE - data_page_offset; | |
712 | ||
ab34c226 CW |
713 | slow_kernel_write(dev_priv->mm.gtt_mapping, |
714 | gtt_page_base, gtt_page_offset, | |
715 | user_pages[data_page_index], | |
716 | data_page_offset, | |
717 | page_length); | |
3de09aa3 EA |
718 | |
719 | remain -= page_length; | |
720 | offset += page_length; | |
721 | data_ptr += page_length; | |
722 | } | |
723 | ||
3de09aa3 EA |
724 | out_unpin_pages: |
725 | for (i = 0; i < pinned_pages; i++) | |
726 | page_cache_release(user_pages[i]); | |
8e7d2b2c | 727 | drm_free_large(user_pages); |
3de09aa3 EA |
728 | |
729 | return ret; | |
730 | } | |
731 | ||
40123c1f EA |
732 | /** |
733 | * This is the fast shmem pwrite path, which attempts to directly | |
734 | * copy_from_user into the kmapped pages backing the object. | |
735 | */ | |
3043c60c | 736 | static int |
05394f39 CW |
737 | i915_gem_shmem_pwrite_fast(struct drm_device *dev, |
738 | struct drm_i915_gem_object *obj, | |
40123c1f | 739 | struct drm_i915_gem_pwrite *args, |
05394f39 | 740 | struct drm_file *file) |
673a394b | 741 | { |
05394f39 | 742 | struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping; |
40123c1f | 743 | ssize_t remain; |
e5281ccd | 744 | loff_t offset; |
40123c1f EA |
745 | char __user *user_data; |
746 | int page_offset, page_length; | |
40123c1f EA |
747 | |
748 | user_data = (char __user *) (uintptr_t) args->data_ptr; | |
749 | remain = args->size; | |
673a394b | 750 | |
40123c1f | 751 | offset = args->offset; |
05394f39 | 752 | obj->dirty = 1; |
40123c1f EA |
753 | |
754 | while (remain > 0) { | |
e5281ccd CW |
755 | struct page *page; |
756 | char *vaddr; | |
757 | int ret; | |
758 | ||
40123c1f EA |
759 | /* Operation in this page |
760 | * | |
40123c1f EA |
761 | * page_offset = offset within page |
762 | * page_length = bytes to copy for this page | |
763 | */ | |
40123c1f EA |
764 | page_offset = offset & (PAGE_SIZE-1); |
765 | page_length = remain; | |
766 | if ((page_offset + remain) > PAGE_SIZE) | |
767 | page_length = PAGE_SIZE - page_offset; | |
768 | ||
e5281ccd CW |
769 | page = read_cache_page_gfp(mapping, offset >> PAGE_SHIFT, |
770 | GFP_HIGHUSER | __GFP_RECLAIMABLE); | |
771 | if (IS_ERR(page)) | |
772 | return PTR_ERR(page); | |
773 | ||
774 | vaddr = kmap_atomic(page, KM_USER0); | |
775 | ret = __copy_from_user_inatomic(vaddr + page_offset, | |
776 | user_data, | |
777 | page_length); | |
778 | kunmap_atomic(vaddr, KM_USER0); | |
779 | ||
780 | set_page_dirty(page); | |
781 | mark_page_accessed(page); | |
782 | page_cache_release(page); | |
783 | ||
784 | /* If we get a fault while copying data, then (presumably) our | |
785 | * source page isn't available. Return the error and we'll | |
786 | * retry in the slow path. | |
787 | */ | |
788 | if (ret) | |
fbd5a26d | 789 | return -EFAULT; |
40123c1f EA |
790 | |
791 | remain -= page_length; | |
792 | user_data += page_length; | |
793 | offset += page_length; | |
794 | } | |
795 | ||
fbd5a26d | 796 | return 0; |
40123c1f EA |
797 | } |
798 | ||
799 | /** | |
800 | * This is the fallback shmem pwrite path, which uses get_user_pages to pin | |
801 | * the memory and maps it using kmap_atomic for copying. | |
802 | * | |
803 | * This avoids taking mmap_sem for faulting on the user's address while the | |
804 | * struct_mutex is held. | |
805 | */ | |
806 | static int | |
05394f39 CW |
807 | i915_gem_shmem_pwrite_slow(struct drm_device *dev, |
808 | struct drm_i915_gem_object *obj, | |
40123c1f | 809 | struct drm_i915_gem_pwrite *args, |
05394f39 | 810 | struct drm_file *file) |
40123c1f | 811 | { |
05394f39 | 812 | struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping; |
40123c1f EA |
813 | struct mm_struct *mm = current->mm; |
814 | struct page **user_pages; | |
815 | ssize_t remain; | |
816 | loff_t offset, pinned_pages, i; | |
817 | loff_t first_data_page, last_data_page, num_pages; | |
e5281ccd | 818 | int shmem_page_offset; |
40123c1f EA |
819 | int data_page_index, data_page_offset; |
820 | int page_length; | |
821 | int ret; | |
822 | uint64_t data_ptr = args->data_ptr; | |
280b713b | 823 | int do_bit17_swizzling; |
40123c1f EA |
824 | |
825 | remain = args->size; | |
826 | ||
827 | /* Pin the user pages containing the data. We can't fault while | |
828 | * holding the struct mutex, and all of the pwrite implementations | |
829 | * want to hold it while dereferencing the user data. | |
830 | */ | |
831 | first_data_page = data_ptr / PAGE_SIZE; | |
832 | last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE; | |
833 | num_pages = last_data_page - first_data_page + 1; | |
834 | ||
4f27b75d | 835 | user_pages = drm_malloc_ab(num_pages, sizeof(struct page *)); |
40123c1f EA |
836 | if (user_pages == NULL) |
837 | return -ENOMEM; | |
838 | ||
fbd5a26d | 839 | mutex_unlock(&dev->struct_mutex); |
40123c1f EA |
840 | down_read(&mm->mmap_sem); |
841 | pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr, | |
842 | num_pages, 0, 0, user_pages, NULL); | |
843 | up_read(&mm->mmap_sem); | |
fbd5a26d | 844 | mutex_lock(&dev->struct_mutex); |
40123c1f EA |
845 | if (pinned_pages < num_pages) { |
846 | ret = -EFAULT; | |
fbd5a26d | 847 | goto out; |
673a394b EA |
848 | } |
849 | ||
fbd5a26d | 850 | ret = i915_gem_object_set_to_cpu_domain(obj, 1); |
07f73f69 | 851 | if (ret) |
fbd5a26d | 852 | goto out; |
40123c1f | 853 | |
fbd5a26d | 854 | do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj); |
40123c1f | 855 | |
673a394b | 856 | offset = args->offset; |
05394f39 | 857 | obj->dirty = 1; |
673a394b | 858 | |
40123c1f | 859 | while (remain > 0) { |
e5281ccd CW |
860 | struct page *page; |
861 | ||
40123c1f EA |
862 | /* Operation in this page |
863 | * | |
40123c1f EA |
864 | * shmem_page_offset = offset within page in shmem file |
865 | * data_page_index = page number in get_user_pages return | |
866 | * data_page_offset = offset with data_page_index page. | |
867 | * page_length = bytes to copy for this page | |
868 | */ | |
40123c1f EA |
869 | shmem_page_offset = offset & ~PAGE_MASK; |
870 | data_page_index = data_ptr / PAGE_SIZE - first_data_page; | |
871 | data_page_offset = data_ptr & ~PAGE_MASK; | |
872 | ||
873 | page_length = remain; | |
874 | if ((shmem_page_offset + page_length) > PAGE_SIZE) | |
875 | page_length = PAGE_SIZE - shmem_page_offset; | |
876 | if ((data_page_offset + page_length) > PAGE_SIZE) | |
877 | page_length = PAGE_SIZE - data_page_offset; | |
878 | ||
e5281ccd CW |
879 | page = read_cache_page_gfp(mapping, offset >> PAGE_SHIFT, |
880 | GFP_HIGHUSER | __GFP_RECLAIMABLE); | |
881 | if (IS_ERR(page)) { | |
882 | ret = PTR_ERR(page); | |
883 | goto out; | |
884 | } | |
885 | ||
280b713b | 886 | if (do_bit17_swizzling) { |
e5281ccd | 887 | slow_shmem_bit17_copy(page, |
280b713b EA |
888 | shmem_page_offset, |
889 | user_pages[data_page_index], | |
890 | data_page_offset, | |
99a03df5 CW |
891 | page_length, |
892 | 0); | |
893 | } else { | |
e5281ccd | 894 | slow_shmem_copy(page, |
99a03df5 CW |
895 | shmem_page_offset, |
896 | user_pages[data_page_index], | |
897 | data_page_offset, | |
898 | page_length); | |
280b713b | 899 | } |
40123c1f | 900 | |
e5281ccd CW |
901 | set_page_dirty(page); |
902 | mark_page_accessed(page); | |
903 | page_cache_release(page); | |
904 | ||
40123c1f EA |
905 | remain -= page_length; |
906 | data_ptr += page_length; | |
907 | offset += page_length; | |
673a394b EA |
908 | } |
909 | ||
fbd5a26d | 910 | out: |
40123c1f EA |
911 | for (i = 0; i < pinned_pages; i++) |
912 | page_cache_release(user_pages[i]); | |
8e7d2b2c | 913 | drm_free_large(user_pages); |
673a394b | 914 | |
40123c1f | 915 | return ret; |
673a394b EA |
916 | } |
917 | ||
918 | /** | |
919 | * Writes data to the object referenced by handle. | |
920 | * | |
921 | * On error, the contents of the buffer that were to be modified are undefined. | |
922 | */ | |
923 | int | |
924 | i915_gem_pwrite_ioctl(struct drm_device *dev, void *data, | |
fbd5a26d | 925 | struct drm_file *file) |
673a394b EA |
926 | { |
927 | struct drm_i915_gem_pwrite *args = data; | |
05394f39 | 928 | struct drm_i915_gem_object *obj; |
51311d0a CW |
929 | int ret; |
930 | ||
931 | if (args->size == 0) | |
932 | return 0; | |
933 | ||
934 | if (!access_ok(VERIFY_READ, | |
935 | (char __user *)(uintptr_t)args->data_ptr, | |
936 | args->size)) | |
937 | return -EFAULT; | |
938 | ||
939 | ret = fault_in_pages_readable((char __user *)(uintptr_t)args->data_ptr, | |
940 | args->size); | |
941 | if (ret) | |
942 | return -EFAULT; | |
673a394b | 943 | |
fbd5a26d | 944 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 945 | if (ret) |
fbd5a26d | 946 | return ret; |
1d7cfea1 | 947 | |
05394f39 | 948 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
1d7cfea1 CW |
949 | if (obj == NULL) { |
950 | ret = -ENOENT; | |
951 | goto unlock; | |
fbd5a26d | 952 | } |
673a394b | 953 | |
7dcd2499 | 954 | /* Bounds check destination. */ |
05394f39 CW |
955 | if (args->offset > obj->base.size || |
956 | args->size > obj->base.size - args->offset) { | |
ce9d419d | 957 | ret = -EINVAL; |
35b62a89 | 958 | goto out; |
ce9d419d CW |
959 | } |
960 | ||
673a394b EA |
961 | /* We can only do the GTT pwrite on untiled buffers, as otherwise |
962 | * it would end up going through the fenced access, and we'll get | |
963 | * different detiling behavior between reading and writing. | |
964 | * pread/pwrite currently are reading and writing from the CPU | |
965 | * perspective, requiring manual detiling by the client. | |
966 | */ | |
05394f39 | 967 | if (obj->phys_obj) |
fbd5a26d | 968 | ret = i915_gem_phys_pwrite(dev, obj, args, file); |
05394f39 CW |
969 | else if (obj->tiling_mode == I915_TILING_NONE && |
970 | obj->gtt_space && | |
971 | obj->base.write_domain != I915_GEM_DOMAIN_CPU) { | |
75e9e915 | 972 | ret = i915_gem_object_pin(obj, 0, true); |
fbd5a26d CW |
973 | if (ret) |
974 | goto out; | |
975 | ||
976 | ret = i915_gem_object_set_to_gtt_domain(obj, 1); | |
977 | if (ret) | |
978 | goto out_unpin; | |
979 | ||
980 | ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file); | |
981 | if (ret == -EFAULT) | |
982 | ret = i915_gem_gtt_pwrite_slow(dev, obj, args, file); | |
983 | ||
984 | out_unpin: | |
985 | i915_gem_object_unpin(obj); | |
40123c1f | 986 | } else { |
fbd5a26d CW |
987 | ret = i915_gem_object_set_to_cpu_domain(obj, 1); |
988 | if (ret) | |
e5281ccd | 989 | goto out; |
673a394b | 990 | |
fbd5a26d CW |
991 | ret = -EFAULT; |
992 | if (!i915_gem_object_needs_bit17_swizzle(obj)) | |
993 | ret = i915_gem_shmem_pwrite_fast(dev, obj, args, file); | |
994 | if (ret == -EFAULT) | |
995 | ret = i915_gem_shmem_pwrite_slow(dev, obj, args, file); | |
fbd5a26d | 996 | } |
673a394b | 997 | |
35b62a89 | 998 | out: |
05394f39 | 999 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 1000 | unlock: |
fbd5a26d | 1001 | mutex_unlock(&dev->struct_mutex); |
673a394b EA |
1002 | return ret; |
1003 | } | |
1004 | ||
1005 | /** | |
2ef7eeaa EA |
1006 | * Called when user space prepares to use an object with the CPU, either |
1007 | * through the mmap ioctl's mapping or a GTT mapping. | |
673a394b EA |
1008 | */ |
1009 | int | |
1010 | i915_gem_set_domain_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 1011 | struct drm_file *file) |
673a394b | 1012 | { |
a09ba7fa | 1013 | struct drm_i915_private *dev_priv = dev->dev_private; |
673a394b | 1014 | struct drm_i915_gem_set_domain *args = data; |
05394f39 | 1015 | struct drm_i915_gem_object *obj; |
2ef7eeaa EA |
1016 | uint32_t read_domains = args->read_domains; |
1017 | uint32_t write_domain = args->write_domain; | |
673a394b EA |
1018 | int ret; |
1019 | ||
1020 | if (!(dev->driver->driver_features & DRIVER_GEM)) | |
1021 | return -ENODEV; | |
1022 | ||
2ef7eeaa | 1023 | /* Only handle setting domains to types used by the CPU. */ |
21d509e3 | 1024 | if (write_domain & I915_GEM_GPU_DOMAINS) |
2ef7eeaa EA |
1025 | return -EINVAL; |
1026 | ||
21d509e3 | 1027 | if (read_domains & I915_GEM_GPU_DOMAINS) |
2ef7eeaa EA |
1028 | return -EINVAL; |
1029 | ||
1030 | /* Having something in the write domain implies it's in the read | |
1031 | * domain, and only that read domain. Enforce that in the request. | |
1032 | */ | |
1033 | if (write_domain != 0 && read_domains != write_domain) | |
1034 | return -EINVAL; | |
1035 | ||
76c1dec1 | 1036 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 1037 | if (ret) |
76c1dec1 | 1038 | return ret; |
1d7cfea1 | 1039 | |
05394f39 | 1040 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
1d7cfea1 CW |
1041 | if (obj == NULL) { |
1042 | ret = -ENOENT; | |
1043 | goto unlock; | |
76c1dec1 | 1044 | } |
673a394b | 1045 | |
652c393a JB |
1046 | intel_mark_busy(dev, obj); |
1047 | ||
2ef7eeaa EA |
1048 | if (read_domains & I915_GEM_DOMAIN_GTT) { |
1049 | ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0); | |
02354392 | 1050 | |
a09ba7fa EA |
1051 | /* Update the LRU on the fence for the CPU access that's |
1052 | * about to occur. | |
1053 | */ | |
05394f39 | 1054 | if (obj->fence_reg != I915_FENCE_REG_NONE) { |
007cc8ac | 1055 | struct drm_i915_fence_reg *reg = |
05394f39 | 1056 | &dev_priv->fence_regs[obj->fence_reg]; |
007cc8ac | 1057 | list_move_tail(®->lru_list, |
a09ba7fa EA |
1058 | &dev_priv->mm.fence_list); |
1059 | } | |
1060 | ||
02354392 EA |
1061 | /* Silently promote "you're not bound, there was nothing to do" |
1062 | * to success, since the client was just asking us to | |
1063 | * make sure everything was done. | |
1064 | */ | |
1065 | if (ret == -EINVAL) | |
1066 | ret = 0; | |
2ef7eeaa | 1067 | } else { |
e47c68e9 | 1068 | ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0); |
2ef7eeaa EA |
1069 | } |
1070 | ||
7d1c4804 | 1071 | /* Maintain LRU order of "inactive" objects */ |
05394f39 CW |
1072 | if (ret == 0 && i915_gem_object_is_inactive(obj)) |
1073 | list_move_tail(&obj->mm_list, &dev_priv->mm.inactive_list); | |
7d1c4804 | 1074 | |
05394f39 | 1075 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 1076 | unlock: |
673a394b EA |
1077 | mutex_unlock(&dev->struct_mutex); |
1078 | return ret; | |
1079 | } | |
1080 | ||
1081 | /** | |
1082 | * Called when user space has done writes to this buffer | |
1083 | */ | |
1084 | int | |
1085 | i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 1086 | struct drm_file *file) |
673a394b EA |
1087 | { |
1088 | struct drm_i915_gem_sw_finish *args = data; | |
05394f39 | 1089 | struct drm_i915_gem_object *obj; |
673a394b EA |
1090 | int ret = 0; |
1091 | ||
1092 | if (!(dev->driver->driver_features & DRIVER_GEM)) | |
1093 | return -ENODEV; | |
1094 | ||
76c1dec1 | 1095 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 1096 | if (ret) |
76c1dec1 | 1097 | return ret; |
1d7cfea1 | 1098 | |
05394f39 | 1099 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
673a394b | 1100 | if (obj == NULL) { |
1d7cfea1 CW |
1101 | ret = -ENOENT; |
1102 | goto unlock; | |
673a394b EA |
1103 | } |
1104 | ||
673a394b | 1105 | /* Pinned buffers may be scanout, so flush the cache */ |
05394f39 | 1106 | if (obj->pin_count) |
e47c68e9 EA |
1107 | i915_gem_object_flush_cpu_write_domain(obj); |
1108 | ||
05394f39 | 1109 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 1110 | unlock: |
673a394b EA |
1111 | mutex_unlock(&dev->struct_mutex); |
1112 | return ret; | |
1113 | } | |
1114 | ||
1115 | /** | |
1116 | * Maps the contents of an object, returning the address it is mapped | |
1117 | * into. | |
1118 | * | |
1119 | * While the mapping holds a reference on the contents of the object, it doesn't | |
1120 | * imply a ref on the object itself. | |
1121 | */ | |
1122 | int | |
1123 | i915_gem_mmap_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 1124 | struct drm_file *file) |
673a394b | 1125 | { |
da761a6e | 1126 | struct drm_i915_private *dev_priv = dev->dev_private; |
673a394b EA |
1127 | struct drm_i915_gem_mmap *args = data; |
1128 | struct drm_gem_object *obj; | |
1129 | loff_t offset; | |
1130 | unsigned long addr; | |
1131 | ||
1132 | if (!(dev->driver->driver_features & DRIVER_GEM)) | |
1133 | return -ENODEV; | |
1134 | ||
05394f39 | 1135 | obj = drm_gem_object_lookup(dev, file, args->handle); |
673a394b | 1136 | if (obj == NULL) |
bf79cb91 | 1137 | return -ENOENT; |
673a394b | 1138 | |
da761a6e CW |
1139 | if (obj->size > dev_priv->mm.gtt_mappable_end) { |
1140 | drm_gem_object_unreference_unlocked(obj); | |
1141 | return -E2BIG; | |
1142 | } | |
1143 | ||
673a394b EA |
1144 | offset = args->offset; |
1145 | ||
1146 | down_write(¤t->mm->mmap_sem); | |
1147 | addr = do_mmap(obj->filp, 0, args->size, | |
1148 | PROT_READ | PROT_WRITE, MAP_SHARED, | |
1149 | args->offset); | |
1150 | up_write(¤t->mm->mmap_sem); | |
bc9025bd | 1151 | drm_gem_object_unreference_unlocked(obj); |
673a394b EA |
1152 | if (IS_ERR((void *)addr)) |
1153 | return addr; | |
1154 | ||
1155 | args->addr_ptr = (uint64_t) addr; | |
1156 | ||
1157 | return 0; | |
1158 | } | |
1159 | ||
de151cf6 JB |
1160 | /** |
1161 | * i915_gem_fault - fault a page into the GTT | |
1162 | * vma: VMA in question | |
1163 | * vmf: fault info | |
1164 | * | |
1165 | * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped | |
1166 | * from userspace. The fault handler takes care of binding the object to | |
1167 | * the GTT (if needed), allocating and programming a fence register (again, | |
1168 | * only if needed based on whether the old reg is still valid or the object | |
1169 | * is tiled) and inserting a new PTE into the faulting process. | |
1170 | * | |
1171 | * Note that the faulting process may involve evicting existing objects | |
1172 | * from the GTT and/or fence registers to make room. So performance may | |
1173 | * suffer if the GTT working set is large or there are few fence registers | |
1174 | * left. | |
1175 | */ | |
1176 | int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf) | |
1177 | { | |
05394f39 CW |
1178 | struct drm_i915_gem_object *obj = to_intel_bo(vma->vm_private_data); |
1179 | struct drm_device *dev = obj->base.dev; | |
7d1c4804 | 1180 | drm_i915_private_t *dev_priv = dev->dev_private; |
de151cf6 JB |
1181 | pgoff_t page_offset; |
1182 | unsigned long pfn; | |
1183 | int ret = 0; | |
0f973f27 | 1184 | bool write = !!(vmf->flags & FAULT_FLAG_WRITE); |
de151cf6 JB |
1185 | |
1186 | /* We don't use vmf->pgoff since that has the fake offset */ | |
1187 | page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >> | |
1188 | PAGE_SHIFT; | |
1189 | ||
1190 | /* Now bind it into the GTT if needed */ | |
1191 | mutex_lock(&dev->struct_mutex); | |
a00b10c3 | 1192 | |
919926ae CW |
1193 | if (!obj->map_and_fenceable) { |
1194 | ret = i915_gem_object_unbind(obj); | |
1195 | if (ret) | |
1196 | goto unlock; | |
a00b10c3 | 1197 | } |
05394f39 | 1198 | if (!obj->gtt_space) { |
75e9e915 | 1199 | ret = i915_gem_object_bind_to_gtt(obj, 0, true); |
c715089f CW |
1200 | if (ret) |
1201 | goto unlock; | |
de151cf6 JB |
1202 | } |
1203 | ||
4a684a41 CW |
1204 | ret = i915_gem_object_set_to_gtt_domain(obj, write); |
1205 | if (ret) | |
1206 | goto unlock; | |
1207 | ||
de151cf6 | 1208 | /* Need a new fence register? */ |
05394f39 | 1209 | if (obj->tiling_mode != I915_TILING_NONE) { |
2cf34d7b | 1210 | ret = i915_gem_object_get_fence_reg(obj, true); |
c715089f CW |
1211 | if (ret) |
1212 | goto unlock; | |
d9ddcb96 | 1213 | } |
de151cf6 | 1214 | |
05394f39 CW |
1215 | if (i915_gem_object_is_inactive(obj)) |
1216 | list_move_tail(&obj->mm_list, &dev_priv->mm.inactive_list); | |
7d1c4804 | 1217 | |
6299f992 CW |
1218 | obj->fault_mappable = true; |
1219 | ||
05394f39 | 1220 | pfn = ((dev->agp->base + obj->gtt_offset) >> PAGE_SHIFT) + |
de151cf6 JB |
1221 | page_offset; |
1222 | ||
1223 | /* Finally, remap it using the new GTT offset */ | |
1224 | ret = vm_insert_pfn(vma, (unsigned long)vmf->virtual_address, pfn); | |
c715089f | 1225 | unlock: |
de151cf6 JB |
1226 | mutex_unlock(&dev->struct_mutex); |
1227 | ||
1228 | switch (ret) { | |
045e769a CW |
1229 | case -EAGAIN: |
1230 | set_need_resched(); | |
c715089f CW |
1231 | case 0: |
1232 | case -ERESTARTSYS: | |
1233 | return VM_FAULT_NOPAGE; | |
de151cf6 | 1234 | case -ENOMEM: |
de151cf6 | 1235 | return VM_FAULT_OOM; |
de151cf6 | 1236 | default: |
c715089f | 1237 | return VM_FAULT_SIGBUS; |
de151cf6 JB |
1238 | } |
1239 | } | |
1240 | ||
1241 | /** | |
1242 | * i915_gem_create_mmap_offset - create a fake mmap offset for an object | |
1243 | * @obj: obj in question | |
1244 | * | |
1245 | * GEM memory mapping works by handing back to userspace a fake mmap offset | |
1246 | * it can use in a subsequent mmap(2) call. The DRM core code then looks | |
1247 | * up the object based on the offset and sets up the various memory mapping | |
1248 | * structures. | |
1249 | * | |
1250 | * This routine allocates and attaches a fake offset for @obj. | |
1251 | */ | |
1252 | static int | |
05394f39 | 1253 | i915_gem_create_mmap_offset(struct drm_i915_gem_object *obj) |
de151cf6 | 1254 | { |
05394f39 | 1255 | struct drm_device *dev = obj->base.dev; |
de151cf6 | 1256 | struct drm_gem_mm *mm = dev->mm_private; |
de151cf6 | 1257 | struct drm_map_list *list; |
f77d390c | 1258 | struct drm_local_map *map; |
de151cf6 JB |
1259 | int ret = 0; |
1260 | ||
1261 | /* Set the object up for mmap'ing */ | |
05394f39 | 1262 | list = &obj->base.map_list; |
9a298b2a | 1263 | list->map = kzalloc(sizeof(struct drm_map_list), GFP_KERNEL); |
de151cf6 JB |
1264 | if (!list->map) |
1265 | return -ENOMEM; | |
1266 | ||
1267 | map = list->map; | |
1268 | map->type = _DRM_GEM; | |
05394f39 | 1269 | map->size = obj->base.size; |
de151cf6 JB |
1270 | map->handle = obj; |
1271 | ||
1272 | /* Get a DRM GEM mmap offset allocated... */ | |
1273 | list->file_offset_node = drm_mm_search_free(&mm->offset_manager, | |
05394f39 CW |
1274 | obj->base.size / PAGE_SIZE, |
1275 | 0, 0); | |
de151cf6 | 1276 | if (!list->file_offset_node) { |
05394f39 CW |
1277 | DRM_ERROR("failed to allocate offset for bo %d\n", |
1278 | obj->base.name); | |
9e0ae534 | 1279 | ret = -ENOSPC; |
de151cf6 JB |
1280 | goto out_free_list; |
1281 | } | |
1282 | ||
1283 | list->file_offset_node = drm_mm_get_block(list->file_offset_node, | |
05394f39 CW |
1284 | obj->base.size / PAGE_SIZE, |
1285 | 0); | |
de151cf6 JB |
1286 | if (!list->file_offset_node) { |
1287 | ret = -ENOMEM; | |
1288 | goto out_free_list; | |
1289 | } | |
1290 | ||
1291 | list->hash.key = list->file_offset_node->start; | |
9e0ae534 CW |
1292 | ret = drm_ht_insert_item(&mm->offset_hash, &list->hash); |
1293 | if (ret) { | |
de151cf6 JB |
1294 | DRM_ERROR("failed to add to map hash\n"); |
1295 | goto out_free_mm; | |
1296 | } | |
1297 | ||
de151cf6 JB |
1298 | return 0; |
1299 | ||
1300 | out_free_mm: | |
1301 | drm_mm_put_block(list->file_offset_node); | |
1302 | out_free_list: | |
9a298b2a | 1303 | kfree(list->map); |
39a01d1f | 1304 | list->map = NULL; |
de151cf6 JB |
1305 | |
1306 | return ret; | |
1307 | } | |
1308 | ||
901782b2 CW |
1309 | /** |
1310 | * i915_gem_release_mmap - remove physical page mappings | |
1311 | * @obj: obj in question | |
1312 | * | |
af901ca1 | 1313 | * Preserve the reservation of the mmapping with the DRM core code, but |
901782b2 CW |
1314 | * relinquish ownership of the pages back to the system. |
1315 | * | |
1316 | * It is vital that we remove the page mapping if we have mapped a tiled | |
1317 | * object through the GTT and then lose the fence register due to | |
1318 | * resource pressure. Similarly if the object has been moved out of the | |
1319 | * aperture, than pages mapped into userspace must be revoked. Removing the | |
1320 | * mapping will then trigger a page fault on the next user access, allowing | |
1321 | * fixup by i915_gem_fault(). | |
1322 | */ | |
d05ca301 | 1323 | void |
05394f39 | 1324 | i915_gem_release_mmap(struct drm_i915_gem_object *obj) |
901782b2 | 1325 | { |
6299f992 CW |
1326 | if (!obj->fault_mappable) |
1327 | return; | |
901782b2 | 1328 | |
6299f992 CW |
1329 | unmap_mapping_range(obj->base.dev->dev_mapping, |
1330 | (loff_t)obj->base.map_list.hash.key<<PAGE_SHIFT, | |
1331 | obj->base.size, 1); | |
fb7d516a | 1332 | |
6299f992 | 1333 | obj->fault_mappable = false; |
901782b2 CW |
1334 | } |
1335 | ||
ab00b3e5 | 1336 | static void |
05394f39 | 1337 | i915_gem_free_mmap_offset(struct drm_i915_gem_object *obj) |
ab00b3e5 | 1338 | { |
05394f39 | 1339 | struct drm_device *dev = obj->base.dev; |
ab00b3e5 | 1340 | struct drm_gem_mm *mm = dev->mm_private; |
05394f39 | 1341 | struct drm_map_list *list = &obj->base.map_list; |
ab00b3e5 | 1342 | |
ab00b3e5 | 1343 | drm_ht_remove_item(&mm->offset_hash, &list->hash); |
39a01d1f CW |
1344 | drm_mm_put_block(list->file_offset_node); |
1345 | kfree(list->map); | |
1346 | list->map = NULL; | |
ab00b3e5 JB |
1347 | } |
1348 | ||
92b88aeb CW |
1349 | static uint32_t |
1350 | i915_gem_get_gtt_size(struct drm_i915_gem_object *obj) | |
1351 | { | |
1352 | struct drm_device *dev = obj->base.dev; | |
1353 | uint32_t size; | |
1354 | ||
1355 | if (INTEL_INFO(dev)->gen >= 4 || | |
1356 | obj->tiling_mode == I915_TILING_NONE) | |
1357 | return obj->base.size; | |
1358 | ||
1359 | /* Previous chips need a power-of-two fence region when tiling */ | |
1360 | if (INTEL_INFO(dev)->gen == 3) | |
1361 | size = 1024*1024; | |
1362 | else | |
1363 | size = 512*1024; | |
1364 | ||
1365 | while (size < obj->base.size) | |
1366 | size <<= 1; | |
1367 | ||
1368 | return size; | |
1369 | } | |
1370 | ||
de151cf6 JB |
1371 | /** |
1372 | * i915_gem_get_gtt_alignment - return required GTT alignment for an object | |
1373 | * @obj: object to check | |
1374 | * | |
1375 | * Return the required GTT alignment for an object, taking into account | |
5e783301 | 1376 | * potential fence register mapping. |
de151cf6 JB |
1377 | */ |
1378 | static uint32_t | |
05394f39 | 1379 | i915_gem_get_gtt_alignment(struct drm_i915_gem_object *obj) |
de151cf6 | 1380 | { |
05394f39 | 1381 | struct drm_device *dev = obj->base.dev; |
de151cf6 JB |
1382 | |
1383 | /* | |
1384 | * Minimum alignment is 4k (GTT page size), but might be greater | |
1385 | * if a fence register is needed for the object. | |
1386 | */ | |
a00b10c3 | 1387 | if (INTEL_INFO(dev)->gen >= 4 || |
05394f39 | 1388 | obj->tiling_mode == I915_TILING_NONE) |
de151cf6 JB |
1389 | return 4096; |
1390 | ||
a00b10c3 CW |
1391 | /* |
1392 | * Previous chips need to be aligned to the size of the smallest | |
1393 | * fence register that can contain the object. | |
1394 | */ | |
05394f39 | 1395 | return i915_gem_get_gtt_size(obj); |
a00b10c3 CW |
1396 | } |
1397 | ||
5e783301 DV |
1398 | /** |
1399 | * i915_gem_get_unfenced_gtt_alignment - return required GTT alignment for an | |
1400 | * unfenced object | |
1401 | * @obj: object to check | |
1402 | * | |
1403 | * Return the required GTT alignment for an object, only taking into account | |
1404 | * unfenced tiled surface requirements. | |
1405 | */ | |
1406 | static uint32_t | |
05394f39 | 1407 | i915_gem_get_unfenced_gtt_alignment(struct drm_i915_gem_object *obj) |
5e783301 | 1408 | { |
05394f39 | 1409 | struct drm_device *dev = obj->base.dev; |
5e783301 DV |
1410 | int tile_height; |
1411 | ||
1412 | /* | |
1413 | * Minimum alignment is 4k (GTT page size) for sane hw. | |
1414 | */ | |
1415 | if (INTEL_INFO(dev)->gen >= 4 || IS_G33(dev) || | |
05394f39 | 1416 | obj->tiling_mode == I915_TILING_NONE) |
5e783301 DV |
1417 | return 4096; |
1418 | ||
1419 | /* | |
1420 | * Older chips need unfenced tiled buffers to be aligned to the left | |
1421 | * edge of an even tile row (where tile rows are counted as if the bo is | |
1422 | * placed in a fenced gtt region). | |
1423 | */ | |
1424 | if (IS_GEN2(dev) || | |
05394f39 | 1425 | (obj->tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev))) |
5e783301 DV |
1426 | tile_height = 32; |
1427 | else | |
1428 | tile_height = 8; | |
1429 | ||
05394f39 | 1430 | return tile_height * obj->stride * 2; |
5e783301 DV |
1431 | } |
1432 | ||
de151cf6 JB |
1433 | /** |
1434 | * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing | |
1435 | * @dev: DRM device | |
1436 | * @data: GTT mapping ioctl data | |
05394f39 | 1437 | * @file: GEM object info |
de151cf6 JB |
1438 | * |
1439 | * Simply returns the fake offset to userspace so it can mmap it. | |
1440 | * The mmap call will end up in drm_gem_mmap(), which will set things | |
1441 | * up so we can get faults in the handler above. | |
1442 | * | |
1443 | * The fault handler will take care of binding the object into the GTT | |
1444 | * (since it may have been evicted to make room for something), allocating | |
1445 | * a fence register, and mapping the appropriate aperture address into | |
1446 | * userspace. | |
1447 | */ | |
1448 | int | |
1449 | i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 1450 | struct drm_file *file) |
de151cf6 | 1451 | { |
da761a6e | 1452 | struct drm_i915_private *dev_priv = dev->dev_private; |
de151cf6 | 1453 | struct drm_i915_gem_mmap_gtt *args = data; |
05394f39 | 1454 | struct drm_i915_gem_object *obj; |
de151cf6 JB |
1455 | int ret; |
1456 | ||
1457 | if (!(dev->driver->driver_features & DRIVER_GEM)) | |
1458 | return -ENODEV; | |
1459 | ||
76c1dec1 | 1460 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 1461 | if (ret) |
76c1dec1 | 1462 | return ret; |
de151cf6 | 1463 | |
05394f39 | 1464 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
1d7cfea1 CW |
1465 | if (obj == NULL) { |
1466 | ret = -ENOENT; | |
1467 | goto unlock; | |
1468 | } | |
de151cf6 | 1469 | |
05394f39 | 1470 | if (obj->base.size > dev_priv->mm.gtt_mappable_end) { |
da761a6e CW |
1471 | ret = -E2BIG; |
1472 | goto unlock; | |
1473 | } | |
1474 | ||
05394f39 | 1475 | if (obj->madv != I915_MADV_WILLNEED) { |
ab18282d | 1476 | DRM_ERROR("Attempting to mmap a purgeable buffer\n"); |
1d7cfea1 CW |
1477 | ret = -EINVAL; |
1478 | goto out; | |
ab18282d CW |
1479 | } |
1480 | ||
05394f39 | 1481 | if (!obj->base.map_list.map) { |
de151cf6 | 1482 | ret = i915_gem_create_mmap_offset(obj); |
1d7cfea1 CW |
1483 | if (ret) |
1484 | goto out; | |
de151cf6 JB |
1485 | } |
1486 | ||
05394f39 | 1487 | args->offset = (u64)obj->base.map_list.hash.key << PAGE_SHIFT; |
de151cf6 | 1488 | |
1d7cfea1 | 1489 | out: |
05394f39 | 1490 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 1491 | unlock: |
de151cf6 | 1492 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 1493 | return ret; |
de151cf6 JB |
1494 | } |
1495 | ||
e5281ccd | 1496 | static int |
05394f39 | 1497 | i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj, |
e5281ccd CW |
1498 | gfp_t gfpmask) |
1499 | { | |
e5281ccd CW |
1500 | int page_count, i; |
1501 | struct address_space *mapping; | |
1502 | struct inode *inode; | |
1503 | struct page *page; | |
1504 | ||
1505 | /* Get the list of pages out of our struct file. They'll be pinned | |
1506 | * at this point until we release them. | |
1507 | */ | |
05394f39 CW |
1508 | page_count = obj->base.size / PAGE_SIZE; |
1509 | BUG_ON(obj->pages != NULL); | |
1510 | obj->pages = drm_malloc_ab(page_count, sizeof(struct page *)); | |
1511 | if (obj->pages == NULL) | |
e5281ccd CW |
1512 | return -ENOMEM; |
1513 | ||
05394f39 | 1514 | inode = obj->base.filp->f_path.dentry->d_inode; |
e5281ccd CW |
1515 | mapping = inode->i_mapping; |
1516 | for (i = 0; i < page_count; i++) { | |
1517 | page = read_cache_page_gfp(mapping, i, | |
1518 | GFP_HIGHUSER | | |
1519 | __GFP_COLD | | |
1520 | __GFP_RECLAIMABLE | | |
1521 | gfpmask); | |
1522 | if (IS_ERR(page)) | |
1523 | goto err_pages; | |
1524 | ||
05394f39 | 1525 | obj->pages[i] = page; |
e5281ccd CW |
1526 | } |
1527 | ||
05394f39 | 1528 | if (obj->tiling_mode != I915_TILING_NONE) |
e5281ccd CW |
1529 | i915_gem_object_do_bit_17_swizzle(obj); |
1530 | ||
1531 | return 0; | |
1532 | ||
1533 | err_pages: | |
1534 | while (i--) | |
05394f39 | 1535 | page_cache_release(obj->pages[i]); |
e5281ccd | 1536 | |
05394f39 CW |
1537 | drm_free_large(obj->pages); |
1538 | obj->pages = NULL; | |
e5281ccd CW |
1539 | return PTR_ERR(page); |
1540 | } | |
1541 | ||
5cdf5881 | 1542 | static void |
05394f39 | 1543 | i915_gem_object_put_pages_gtt(struct drm_i915_gem_object *obj) |
673a394b | 1544 | { |
05394f39 | 1545 | int page_count = obj->base.size / PAGE_SIZE; |
673a394b EA |
1546 | int i; |
1547 | ||
05394f39 | 1548 | BUG_ON(obj->madv == __I915_MADV_PURGED); |
673a394b | 1549 | |
05394f39 | 1550 | if (obj->tiling_mode != I915_TILING_NONE) |
280b713b EA |
1551 | i915_gem_object_save_bit_17_swizzle(obj); |
1552 | ||
05394f39 CW |
1553 | if (obj->madv == I915_MADV_DONTNEED) |
1554 | obj->dirty = 0; | |
3ef94daa CW |
1555 | |
1556 | for (i = 0; i < page_count; i++) { | |
05394f39 CW |
1557 | if (obj->dirty) |
1558 | set_page_dirty(obj->pages[i]); | |
3ef94daa | 1559 | |
05394f39 CW |
1560 | if (obj->madv == I915_MADV_WILLNEED) |
1561 | mark_page_accessed(obj->pages[i]); | |
3ef94daa | 1562 | |
05394f39 | 1563 | page_cache_release(obj->pages[i]); |
3ef94daa | 1564 | } |
05394f39 | 1565 | obj->dirty = 0; |
673a394b | 1566 | |
05394f39 CW |
1567 | drm_free_large(obj->pages); |
1568 | obj->pages = NULL; | |
673a394b EA |
1569 | } |
1570 | ||
54cf91dc | 1571 | void |
05394f39 | 1572 | i915_gem_object_move_to_active(struct drm_i915_gem_object *obj, |
852835f3 | 1573 | struct intel_ring_buffer *ring) |
673a394b | 1574 | { |
05394f39 | 1575 | struct drm_device *dev = obj->base.dev; |
69dc4987 | 1576 | struct drm_i915_private *dev_priv = dev->dev_private; |
a56ba56c | 1577 | uint32_t seqno = i915_gem_next_request_seqno(dev, ring); |
617dbe27 | 1578 | |
852835f3 | 1579 | BUG_ON(ring == NULL); |
05394f39 | 1580 | obj->ring = ring; |
673a394b EA |
1581 | |
1582 | /* Add a reference if we're newly entering the active list. */ | |
05394f39 CW |
1583 | if (!obj->active) { |
1584 | drm_gem_object_reference(&obj->base); | |
1585 | obj->active = 1; | |
673a394b | 1586 | } |
e35a41de | 1587 | |
673a394b | 1588 | /* Move from whatever list we were on to the tail of execution. */ |
05394f39 CW |
1589 | list_move_tail(&obj->mm_list, &dev_priv->mm.active_list); |
1590 | list_move_tail(&obj->ring_list, &ring->active_list); | |
caea7476 | 1591 | |
05394f39 | 1592 | obj->last_rendering_seqno = seqno; |
caea7476 CW |
1593 | if (obj->fenced_gpu_access) { |
1594 | struct drm_i915_fence_reg *reg; | |
1595 | ||
1596 | BUG_ON(obj->fence_reg == I915_FENCE_REG_NONE); | |
1597 | ||
1598 | obj->last_fenced_seqno = seqno; | |
1599 | obj->last_fenced_ring = ring; | |
1600 | ||
1601 | reg = &dev_priv->fence_regs[obj->fence_reg]; | |
1602 | list_move_tail(®->lru_list, &dev_priv->mm.fence_list); | |
1603 | } | |
1604 | } | |
1605 | ||
1606 | static void | |
1607 | i915_gem_object_move_off_active(struct drm_i915_gem_object *obj) | |
1608 | { | |
1609 | list_del_init(&obj->ring_list); | |
1610 | obj->last_rendering_seqno = 0; | |
1611 | obj->last_fenced_seqno = 0; | |
673a394b EA |
1612 | } |
1613 | ||
ce44b0ea | 1614 | static void |
05394f39 | 1615 | i915_gem_object_move_to_flushing(struct drm_i915_gem_object *obj) |
ce44b0ea | 1616 | { |
05394f39 | 1617 | struct drm_device *dev = obj->base.dev; |
ce44b0ea | 1618 | drm_i915_private_t *dev_priv = dev->dev_private; |
ce44b0ea | 1619 | |
05394f39 CW |
1620 | BUG_ON(!obj->active); |
1621 | list_move_tail(&obj->mm_list, &dev_priv->mm.flushing_list); | |
caea7476 CW |
1622 | |
1623 | i915_gem_object_move_off_active(obj); | |
1624 | } | |
1625 | ||
1626 | static void | |
1627 | i915_gem_object_move_to_inactive(struct drm_i915_gem_object *obj) | |
1628 | { | |
1629 | struct drm_device *dev = obj->base.dev; | |
1630 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1631 | ||
1632 | if (obj->pin_count != 0) | |
1633 | list_move_tail(&obj->mm_list, &dev_priv->mm.pinned_list); | |
1634 | else | |
1635 | list_move_tail(&obj->mm_list, &dev_priv->mm.inactive_list); | |
1636 | ||
1637 | BUG_ON(!list_empty(&obj->gpu_write_list)); | |
1638 | BUG_ON(!obj->active); | |
1639 | obj->ring = NULL; | |
1640 | ||
1641 | i915_gem_object_move_off_active(obj); | |
1642 | obj->fenced_gpu_access = false; | |
1643 | obj->last_fenced_ring = NULL; | |
1644 | ||
1645 | obj->active = 0; | |
87ca9c8a | 1646 | obj->pending_gpu_write = false; |
caea7476 CW |
1647 | drm_gem_object_unreference(&obj->base); |
1648 | ||
1649 | WARN_ON(i915_verify_lists(dev)); | |
ce44b0ea | 1650 | } |
673a394b | 1651 | |
963b4836 CW |
1652 | /* Immediately discard the backing storage */ |
1653 | static void | |
05394f39 | 1654 | i915_gem_object_truncate(struct drm_i915_gem_object *obj) |
963b4836 | 1655 | { |
bb6baf76 | 1656 | struct inode *inode; |
963b4836 | 1657 | |
ae9fed6b CW |
1658 | /* Our goal here is to return as much of the memory as |
1659 | * is possible back to the system as we are called from OOM. | |
1660 | * To do this we must instruct the shmfs to drop all of its | |
1661 | * backing pages, *now*. Here we mirror the actions taken | |
1662 | * when by shmem_delete_inode() to release the backing store. | |
1663 | */ | |
05394f39 | 1664 | inode = obj->base.filp->f_path.dentry->d_inode; |
ae9fed6b CW |
1665 | truncate_inode_pages(inode->i_mapping, 0); |
1666 | if (inode->i_op->truncate_range) | |
1667 | inode->i_op->truncate_range(inode, 0, (loff_t)-1); | |
bb6baf76 | 1668 | |
05394f39 | 1669 | obj->madv = __I915_MADV_PURGED; |
963b4836 CW |
1670 | } |
1671 | ||
1672 | static inline int | |
05394f39 | 1673 | i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj) |
963b4836 | 1674 | { |
05394f39 | 1675 | return obj->madv == I915_MADV_DONTNEED; |
963b4836 CW |
1676 | } |
1677 | ||
63560396 DV |
1678 | static void |
1679 | i915_gem_process_flushing_list(struct drm_device *dev, | |
8a1a49f9 | 1680 | uint32_t flush_domains, |
852835f3 | 1681 | struct intel_ring_buffer *ring) |
63560396 | 1682 | { |
05394f39 | 1683 | struct drm_i915_gem_object *obj, *next; |
63560396 | 1684 | |
05394f39 | 1685 | list_for_each_entry_safe(obj, next, |
64193406 | 1686 | &ring->gpu_write_list, |
63560396 | 1687 | gpu_write_list) { |
05394f39 CW |
1688 | if (obj->base.write_domain & flush_domains) { |
1689 | uint32_t old_write_domain = obj->base.write_domain; | |
63560396 | 1690 | |
05394f39 CW |
1691 | obj->base.write_domain = 0; |
1692 | list_del_init(&obj->gpu_write_list); | |
617dbe27 | 1693 | i915_gem_object_move_to_active(obj, ring); |
63560396 | 1694 | |
63560396 | 1695 | trace_i915_gem_object_change_domain(obj, |
05394f39 | 1696 | obj->base.read_domains, |
63560396 DV |
1697 | old_write_domain); |
1698 | } | |
1699 | } | |
1700 | } | |
8187a2b7 | 1701 | |
3cce469c | 1702 | int |
8a1a49f9 | 1703 | i915_add_request(struct drm_device *dev, |
f787a5f5 | 1704 | struct drm_file *file, |
8dc5d147 | 1705 | struct drm_i915_gem_request *request, |
8a1a49f9 | 1706 | struct intel_ring_buffer *ring) |
673a394b EA |
1707 | { |
1708 | drm_i915_private_t *dev_priv = dev->dev_private; | |
f787a5f5 | 1709 | struct drm_i915_file_private *file_priv = NULL; |
673a394b EA |
1710 | uint32_t seqno; |
1711 | int was_empty; | |
3cce469c CW |
1712 | int ret; |
1713 | ||
1714 | BUG_ON(request == NULL); | |
673a394b | 1715 | |
f787a5f5 CW |
1716 | if (file != NULL) |
1717 | file_priv = file->driver_priv; | |
b962442e | 1718 | |
3cce469c CW |
1719 | ret = ring->add_request(ring, &seqno); |
1720 | if (ret) | |
1721 | return ret; | |
673a394b | 1722 | |
a56ba56c | 1723 | ring->outstanding_lazy_request = false; |
673a394b EA |
1724 | |
1725 | request->seqno = seqno; | |
852835f3 | 1726 | request->ring = ring; |
673a394b | 1727 | request->emitted_jiffies = jiffies; |
852835f3 ZN |
1728 | was_empty = list_empty(&ring->request_list); |
1729 | list_add_tail(&request->list, &ring->request_list); | |
1730 | ||
f787a5f5 | 1731 | if (file_priv) { |
1c25595f | 1732 | spin_lock(&file_priv->mm.lock); |
f787a5f5 | 1733 | request->file_priv = file_priv; |
b962442e | 1734 | list_add_tail(&request->client_list, |
f787a5f5 | 1735 | &file_priv->mm.request_list); |
1c25595f | 1736 | spin_unlock(&file_priv->mm.lock); |
b962442e | 1737 | } |
673a394b | 1738 | |
f65d9421 | 1739 | if (!dev_priv->mm.suspended) { |
b3b079db CW |
1740 | mod_timer(&dev_priv->hangcheck_timer, |
1741 | jiffies + msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)); | |
f65d9421 | 1742 | if (was_empty) |
b3b079db CW |
1743 | queue_delayed_work(dev_priv->wq, |
1744 | &dev_priv->mm.retire_work, HZ); | |
f65d9421 | 1745 | } |
3cce469c | 1746 | return 0; |
673a394b EA |
1747 | } |
1748 | ||
f787a5f5 CW |
1749 | static inline void |
1750 | i915_gem_request_remove_from_client(struct drm_i915_gem_request *request) | |
673a394b | 1751 | { |
1c25595f | 1752 | struct drm_i915_file_private *file_priv = request->file_priv; |
673a394b | 1753 | |
1c25595f CW |
1754 | if (!file_priv) |
1755 | return; | |
1c5d22f7 | 1756 | |
1c25595f CW |
1757 | spin_lock(&file_priv->mm.lock); |
1758 | list_del(&request->client_list); | |
1759 | request->file_priv = NULL; | |
1760 | spin_unlock(&file_priv->mm.lock); | |
673a394b | 1761 | } |
673a394b | 1762 | |
dfaae392 CW |
1763 | static void i915_gem_reset_ring_lists(struct drm_i915_private *dev_priv, |
1764 | struct intel_ring_buffer *ring) | |
9375e446 | 1765 | { |
dfaae392 CW |
1766 | while (!list_empty(&ring->request_list)) { |
1767 | struct drm_i915_gem_request *request; | |
673a394b | 1768 | |
dfaae392 CW |
1769 | request = list_first_entry(&ring->request_list, |
1770 | struct drm_i915_gem_request, | |
1771 | list); | |
de151cf6 | 1772 | |
dfaae392 | 1773 | list_del(&request->list); |
f787a5f5 | 1774 | i915_gem_request_remove_from_client(request); |
dfaae392 CW |
1775 | kfree(request); |
1776 | } | |
673a394b | 1777 | |
dfaae392 | 1778 | while (!list_empty(&ring->active_list)) { |
05394f39 | 1779 | struct drm_i915_gem_object *obj; |
9375e446 | 1780 | |
05394f39 CW |
1781 | obj = list_first_entry(&ring->active_list, |
1782 | struct drm_i915_gem_object, | |
1783 | ring_list); | |
9375e446 | 1784 | |
05394f39 CW |
1785 | obj->base.write_domain = 0; |
1786 | list_del_init(&obj->gpu_write_list); | |
1787 | i915_gem_object_move_to_inactive(obj); | |
673a394b EA |
1788 | } |
1789 | } | |
1790 | ||
312817a3 CW |
1791 | static void i915_gem_reset_fences(struct drm_device *dev) |
1792 | { | |
1793 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1794 | int i; | |
1795 | ||
1796 | for (i = 0; i < 16; i++) { | |
1797 | struct drm_i915_fence_reg *reg = &dev_priv->fence_regs[i]; | |
7d2cb39c CW |
1798 | struct drm_i915_gem_object *obj = reg->obj; |
1799 | ||
1800 | if (!obj) | |
1801 | continue; | |
1802 | ||
1803 | if (obj->tiling_mode) | |
1804 | i915_gem_release_mmap(obj); | |
1805 | ||
1806 | i915_gem_clear_fence_reg(obj); | |
312817a3 CW |
1807 | } |
1808 | } | |
1809 | ||
069efc1d | 1810 | void i915_gem_reset(struct drm_device *dev) |
673a394b | 1811 | { |
77f01230 | 1812 | struct drm_i915_private *dev_priv = dev->dev_private; |
05394f39 | 1813 | struct drm_i915_gem_object *obj; |
673a394b | 1814 | |
dfaae392 | 1815 | i915_gem_reset_ring_lists(dev_priv, &dev_priv->render_ring); |
87acb0a5 | 1816 | i915_gem_reset_ring_lists(dev_priv, &dev_priv->bsd_ring); |
549f7365 | 1817 | i915_gem_reset_ring_lists(dev_priv, &dev_priv->blt_ring); |
dfaae392 CW |
1818 | |
1819 | /* Remove anything from the flushing lists. The GPU cache is likely | |
1820 | * to be lost on reset along with the data, so simply move the | |
1821 | * lost bo to the inactive list. | |
1822 | */ | |
1823 | while (!list_empty(&dev_priv->mm.flushing_list)) { | |
05394f39 CW |
1824 | obj= list_first_entry(&dev_priv->mm.flushing_list, |
1825 | struct drm_i915_gem_object, | |
1826 | mm_list); | |
dfaae392 | 1827 | |
05394f39 CW |
1828 | obj->base.write_domain = 0; |
1829 | list_del_init(&obj->gpu_write_list); | |
1830 | i915_gem_object_move_to_inactive(obj); | |
dfaae392 CW |
1831 | } |
1832 | ||
1833 | /* Move everything out of the GPU domains to ensure we do any | |
1834 | * necessary invalidation upon reuse. | |
1835 | */ | |
05394f39 | 1836 | list_for_each_entry(obj, |
77f01230 | 1837 | &dev_priv->mm.inactive_list, |
69dc4987 | 1838 | mm_list) |
77f01230 | 1839 | { |
05394f39 | 1840 | obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS; |
77f01230 | 1841 | } |
069efc1d CW |
1842 | |
1843 | /* The fence registers are invalidated so clear them out */ | |
312817a3 | 1844 | i915_gem_reset_fences(dev); |
673a394b EA |
1845 | } |
1846 | ||
1847 | /** | |
1848 | * This function clears the request list as sequence numbers are passed. | |
1849 | */ | |
b09a1fec CW |
1850 | static void |
1851 | i915_gem_retire_requests_ring(struct drm_device *dev, | |
1852 | struct intel_ring_buffer *ring) | |
673a394b EA |
1853 | { |
1854 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1855 | uint32_t seqno; | |
1856 | ||
b84d5f0c CW |
1857 | if (!ring->status_page.page_addr || |
1858 | list_empty(&ring->request_list)) | |
6c0594a3 KW |
1859 | return; |
1860 | ||
23bc5982 | 1861 | WARN_ON(i915_verify_lists(dev)); |
673a394b | 1862 | |
78501eac | 1863 | seqno = ring->get_seqno(ring); |
852835f3 | 1864 | while (!list_empty(&ring->request_list)) { |
673a394b | 1865 | struct drm_i915_gem_request *request; |
673a394b | 1866 | |
852835f3 | 1867 | request = list_first_entry(&ring->request_list, |
673a394b EA |
1868 | struct drm_i915_gem_request, |
1869 | list); | |
673a394b | 1870 | |
dfaae392 | 1871 | if (!i915_seqno_passed(seqno, request->seqno)) |
b84d5f0c CW |
1872 | break; |
1873 | ||
1874 | trace_i915_gem_request_retire(dev, request->seqno); | |
1875 | ||
1876 | list_del(&request->list); | |
f787a5f5 | 1877 | i915_gem_request_remove_from_client(request); |
b84d5f0c CW |
1878 | kfree(request); |
1879 | } | |
673a394b | 1880 | |
b84d5f0c CW |
1881 | /* Move any buffers on the active list that are no longer referenced |
1882 | * by the ringbuffer to the flushing/inactive lists as appropriate. | |
1883 | */ | |
1884 | while (!list_empty(&ring->active_list)) { | |
05394f39 | 1885 | struct drm_i915_gem_object *obj; |
b84d5f0c | 1886 | |
05394f39 CW |
1887 | obj= list_first_entry(&ring->active_list, |
1888 | struct drm_i915_gem_object, | |
1889 | ring_list); | |
673a394b | 1890 | |
05394f39 | 1891 | if (!i915_seqno_passed(seqno, obj->last_rendering_seqno)) |
673a394b | 1892 | break; |
b84d5f0c | 1893 | |
05394f39 | 1894 | if (obj->base.write_domain != 0) |
b84d5f0c CW |
1895 | i915_gem_object_move_to_flushing(obj); |
1896 | else | |
1897 | i915_gem_object_move_to_inactive(obj); | |
673a394b | 1898 | } |
9d34e5db CW |
1899 | |
1900 | if (unlikely (dev_priv->trace_irq_seqno && | |
1901 | i915_seqno_passed(dev_priv->trace_irq_seqno, seqno))) { | |
78501eac | 1902 | ring->user_irq_put(ring); |
9d34e5db CW |
1903 | dev_priv->trace_irq_seqno = 0; |
1904 | } | |
23bc5982 CW |
1905 | |
1906 | WARN_ON(i915_verify_lists(dev)); | |
673a394b EA |
1907 | } |
1908 | ||
b09a1fec CW |
1909 | void |
1910 | i915_gem_retire_requests(struct drm_device *dev) | |
1911 | { | |
1912 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1913 | ||
be72615b | 1914 | if (!list_empty(&dev_priv->mm.deferred_free_list)) { |
05394f39 | 1915 | struct drm_i915_gem_object *obj, *next; |
be72615b CW |
1916 | |
1917 | /* We must be careful that during unbind() we do not | |
1918 | * accidentally infinitely recurse into retire requests. | |
1919 | * Currently: | |
1920 | * retire -> free -> unbind -> wait -> retire_ring | |
1921 | */ | |
05394f39 | 1922 | list_for_each_entry_safe(obj, next, |
be72615b | 1923 | &dev_priv->mm.deferred_free_list, |
69dc4987 | 1924 | mm_list) |
05394f39 | 1925 | i915_gem_free_object_tail(obj); |
be72615b CW |
1926 | } |
1927 | ||
b09a1fec | 1928 | i915_gem_retire_requests_ring(dev, &dev_priv->render_ring); |
87acb0a5 | 1929 | i915_gem_retire_requests_ring(dev, &dev_priv->bsd_ring); |
549f7365 | 1930 | i915_gem_retire_requests_ring(dev, &dev_priv->blt_ring); |
b09a1fec CW |
1931 | } |
1932 | ||
75ef9da2 | 1933 | static void |
673a394b EA |
1934 | i915_gem_retire_work_handler(struct work_struct *work) |
1935 | { | |
1936 | drm_i915_private_t *dev_priv; | |
1937 | struct drm_device *dev; | |
1938 | ||
1939 | dev_priv = container_of(work, drm_i915_private_t, | |
1940 | mm.retire_work.work); | |
1941 | dev = dev_priv->dev; | |
1942 | ||
891b48cf CW |
1943 | /* Come back later if the device is busy... */ |
1944 | if (!mutex_trylock(&dev->struct_mutex)) { | |
1945 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ); | |
1946 | return; | |
1947 | } | |
1948 | ||
b09a1fec | 1949 | i915_gem_retire_requests(dev); |
d1b851fc | 1950 | |
6dbe2772 | 1951 | if (!dev_priv->mm.suspended && |
d1b851fc | 1952 | (!list_empty(&dev_priv->render_ring.request_list) || |
549f7365 CW |
1953 | !list_empty(&dev_priv->bsd_ring.request_list) || |
1954 | !list_empty(&dev_priv->blt_ring.request_list))) | |
9c9fe1f8 | 1955 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ); |
673a394b EA |
1956 | mutex_unlock(&dev->struct_mutex); |
1957 | } | |
1958 | ||
5a5a0c64 | 1959 | int |
852835f3 | 1960 | i915_do_wait_request(struct drm_device *dev, uint32_t seqno, |
8a1a49f9 | 1961 | bool interruptible, struct intel_ring_buffer *ring) |
673a394b EA |
1962 | { |
1963 | drm_i915_private_t *dev_priv = dev->dev_private; | |
802c7eb6 | 1964 | u32 ier; |
673a394b EA |
1965 | int ret = 0; |
1966 | ||
1967 | BUG_ON(seqno == 0); | |
1968 | ||
ba1234d1 | 1969 | if (atomic_read(&dev_priv->mm.wedged)) |
30dbf0c0 CW |
1970 | return -EAGAIN; |
1971 | ||
5d97eb69 | 1972 | if (seqno == ring->outstanding_lazy_request) { |
3cce469c CW |
1973 | struct drm_i915_gem_request *request; |
1974 | ||
1975 | request = kzalloc(sizeof(*request), GFP_KERNEL); | |
1976 | if (request == NULL) | |
e35a41de | 1977 | return -ENOMEM; |
3cce469c CW |
1978 | |
1979 | ret = i915_add_request(dev, NULL, request, ring); | |
1980 | if (ret) { | |
1981 | kfree(request); | |
1982 | return ret; | |
1983 | } | |
1984 | ||
1985 | seqno = request->seqno; | |
e35a41de | 1986 | } |
ffed1d09 | 1987 | |
78501eac | 1988 | if (!i915_seqno_passed(ring->get_seqno(ring), seqno)) { |
bad720ff | 1989 | if (HAS_PCH_SPLIT(dev)) |
036a4a7d ZW |
1990 | ier = I915_READ(DEIER) | I915_READ(GTIER); |
1991 | else | |
1992 | ier = I915_READ(IER); | |
802c7eb6 JB |
1993 | if (!ier) { |
1994 | DRM_ERROR("something (likely vbetool) disabled " | |
1995 | "interrupts, re-enabling\n"); | |
1996 | i915_driver_irq_preinstall(dev); | |
1997 | i915_driver_irq_postinstall(dev); | |
1998 | } | |
1999 | ||
1c5d22f7 CW |
2000 | trace_i915_gem_request_wait_begin(dev, seqno); |
2001 | ||
b2223497 | 2002 | ring->waiting_seqno = seqno; |
78501eac | 2003 | ring->user_irq_get(ring); |
48764bf4 | 2004 | if (interruptible) |
852835f3 | 2005 | ret = wait_event_interruptible(ring->irq_queue, |
78501eac | 2006 | i915_seqno_passed(ring->get_seqno(ring), seqno) |
852835f3 | 2007 | || atomic_read(&dev_priv->mm.wedged)); |
48764bf4 | 2008 | else |
852835f3 | 2009 | wait_event(ring->irq_queue, |
78501eac | 2010 | i915_seqno_passed(ring->get_seqno(ring), seqno) |
852835f3 | 2011 | || atomic_read(&dev_priv->mm.wedged)); |
48764bf4 | 2012 | |
78501eac | 2013 | ring->user_irq_put(ring); |
b2223497 | 2014 | ring->waiting_seqno = 0; |
1c5d22f7 CW |
2015 | |
2016 | trace_i915_gem_request_wait_end(dev, seqno); | |
673a394b | 2017 | } |
ba1234d1 | 2018 | if (atomic_read(&dev_priv->mm.wedged)) |
30dbf0c0 | 2019 | ret = -EAGAIN; |
673a394b EA |
2020 | |
2021 | if (ret && ret != -ERESTARTSYS) | |
8bff917c | 2022 | DRM_ERROR("%s returns %d (awaiting %d at %d, next %d)\n", |
78501eac | 2023 | __func__, ret, seqno, ring->get_seqno(ring), |
8bff917c | 2024 | dev_priv->next_seqno); |
673a394b EA |
2025 | |
2026 | /* Directly dispatch request retiring. While we have the work queue | |
2027 | * to handle this, the waiter on a request often wants an associated | |
2028 | * buffer to have made it to the inactive list, and we would need | |
2029 | * a separate wait queue to handle that. | |
2030 | */ | |
2031 | if (ret == 0) | |
b09a1fec | 2032 | i915_gem_retire_requests_ring(dev, ring); |
673a394b EA |
2033 | |
2034 | return ret; | |
2035 | } | |
2036 | ||
48764bf4 DV |
2037 | /** |
2038 | * Waits for a sequence number to be signaled, and cleans up the | |
2039 | * request and object lists appropriately for that event. | |
2040 | */ | |
2041 | static int | |
852835f3 | 2042 | i915_wait_request(struct drm_device *dev, uint32_t seqno, |
a56ba56c | 2043 | struct intel_ring_buffer *ring) |
48764bf4 | 2044 | { |
852835f3 | 2045 | return i915_do_wait_request(dev, seqno, 1, ring); |
48764bf4 DV |
2046 | } |
2047 | ||
673a394b EA |
2048 | /** |
2049 | * Ensures that all rendering to the object has completed and the object is | |
2050 | * safe to unbind from the GTT or access from the CPU. | |
2051 | */ | |
54cf91dc | 2052 | int |
05394f39 | 2053 | i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj, |
2cf34d7b | 2054 | bool interruptible) |
673a394b | 2055 | { |
05394f39 | 2056 | struct drm_device *dev = obj->base.dev; |
673a394b EA |
2057 | int ret; |
2058 | ||
e47c68e9 EA |
2059 | /* This function only exists to support waiting for existing rendering, |
2060 | * not for emitting required flushes. | |
673a394b | 2061 | */ |
05394f39 | 2062 | BUG_ON((obj->base.write_domain & I915_GEM_GPU_DOMAINS) != 0); |
673a394b EA |
2063 | |
2064 | /* If there is rendering queued on the buffer being evicted, wait for | |
2065 | * it. | |
2066 | */ | |
05394f39 | 2067 | if (obj->active) { |
2cf34d7b | 2068 | ret = i915_do_wait_request(dev, |
05394f39 | 2069 | obj->last_rendering_seqno, |
2cf34d7b | 2070 | interruptible, |
05394f39 | 2071 | obj->ring); |
2cf34d7b | 2072 | if (ret) |
673a394b EA |
2073 | return ret; |
2074 | } | |
2075 | ||
2076 | return 0; | |
2077 | } | |
2078 | ||
2079 | /** | |
2080 | * Unbinds an object from the GTT aperture. | |
2081 | */ | |
0f973f27 | 2082 | int |
05394f39 | 2083 | i915_gem_object_unbind(struct drm_i915_gem_object *obj) |
673a394b | 2084 | { |
673a394b EA |
2085 | int ret = 0; |
2086 | ||
05394f39 | 2087 | if (obj->gtt_space == NULL) |
673a394b EA |
2088 | return 0; |
2089 | ||
05394f39 | 2090 | if (obj->pin_count != 0) { |
673a394b EA |
2091 | DRM_ERROR("Attempting to unbind pinned buffer\n"); |
2092 | return -EINVAL; | |
2093 | } | |
2094 | ||
5323fd04 EA |
2095 | /* blow away mappings if mapped through GTT */ |
2096 | i915_gem_release_mmap(obj); | |
2097 | ||
673a394b EA |
2098 | /* Move the object to the CPU domain to ensure that |
2099 | * any possible CPU writes while it's not in the GTT | |
2100 | * are flushed when we go to remap it. This will | |
2101 | * also ensure that all pending GPU writes are finished | |
2102 | * before we unbind. | |
2103 | */ | |
e47c68e9 | 2104 | ret = i915_gem_object_set_to_cpu_domain(obj, 1); |
8dc1775d | 2105 | if (ret == -ERESTARTSYS) |
673a394b | 2106 | return ret; |
8dc1775d CW |
2107 | /* Continue on if we fail due to EIO, the GPU is hung so we |
2108 | * should be safe and we need to cleanup or else we might | |
2109 | * cause memory corruption through use-after-free. | |
2110 | */ | |
812ed492 CW |
2111 | if (ret) { |
2112 | i915_gem_clflush_object(obj); | |
05394f39 | 2113 | obj->base.read_domains = obj->base.write_domain = I915_GEM_DOMAIN_CPU; |
812ed492 | 2114 | } |
673a394b | 2115 | |
96b47b65 | 2116 | /* release the fence reg _after_ flushing */ |
05394f39 | 2117 | if (obj->fence_reg != I915_FENCE_REG_NONE) |
96b47b65 DV |
2118 | i915_gem_clear_fence_reg(obj); |
2119 | ||
7c2e6fdf | 2120 | i915_gem_gtt_unbind_object(obj); |
e5281ccd | 2121 | i915_gem_object_put_pages_gtt(obj); |
673a394b | 2122 | |
6299f992 | 2123 | list_del_init(&obj->gtt_list); |
05394f39 | 2124 | list_del_init(&obj->mm_list); |
75e9e915 | 2125 | /* Avoid an unnecessary call to unbind on rebind. */ |
05394f39 | 2126 | obj->map_and_fenceable = true; |
673a394b | 2127 | |
05394f39 CW |
2128 | drm_mm_put_block(obj->gtt_space); |
2129 | obj->gtt_space = NULL; | |
2130 | obj->gtt_offset = 0; | |
673a394b | 2131 | |
05394f39 | 2132 | if (i915_gem_object_is_purgeable(obj)) |
963b4836 CW |
2133 | i915_gem_object_truncate(obj); |
2134 | ||
1c5d22f7 CW |
2135 | trace_i915_gem_object_unbind(obj); |
2136 | ||
8dc1775d | 2137 | return ret; |
673a394b EA |
2138 | } |
2139 | ||
54cf91dc CW |
2140 | void |
2141 | i915_gem_flush_ring(struct drm_device *dev, | |
2142 | struct intel_ring_buffer *ring, | |
2143 | uint32_t invalidate_domains, | |
2144 | uint32_t flush_domains) | |
2145 | { | |
2146 | ring->flush(ring, invalidate_domains, flush_domains); | |
2147 | i915_gem_process_flushing_list(dev, flush_domains, ring); | |
2148 | } | |
2149 | ||
a56ba56c CW |
2150 | static int i915_ring_idle(struct drm_device *dev, |
2151 | struct intel_ring_buffer *ring) | |
2152 | { | |
395b70be | 2153 | if (list_empty(&ring->gpu_write_list) && list_empty(&ring->active_list)) |
64193406 CW |
2154 | return 0; |
2155 | ||
05394f39 | 2156 | i915_gem_flush_ring(dev, ring, |
a56ba56c CW |
2157 | I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS); |
2158 | return i915_wait_request(dev, | |
2159 | i915_gem_next_request_seqno(dev, ring), | |
2160 | ring); | |
2161 | } | |
2162 | ||
b47eb4a2 | 2163 | int |
4df2faf4 DV |
2164 | i915_gpu_idle(struct drm_device *dev) |
2165 | { | |
2166 | drm_i915_private_t *dev_priv = dev->dev_private; | |
2167 | bool lists_empty; | |
852835f3 | 2168 | int ret; |
4df2faf4 | 2169 | |
d1b851fc | 2170 | lists_empty = (list_empty(&dev_priv->mm.flushing_list) && |
395b70be | 2171 | list_empty(&dev_priv->mm.active_list)); |
4df2faf4 DV |
2172 | if (lists_empty) |
2173 | return 0; | |
2174 | ||
2175 | /* Flush everything onto the inactive list. */ | |
a56ba56c | 2176 | ret = i915_ring_idle(dev, &dev_priv->render_ring); |
8a1a49f9 DV |
2177 | if (ret) |
2178 | return ret; | |
d1b851fc | 2179 | |
87acb0a5 CW |
2180 | ret = i915_ring_idle(dev, &dev_priv->bsd_ring); |
2181 | if (ret) | |
2182 | return ret; | |
d1b851fc | 2183 | |
549f7365 CW |
2184 | ret = i915_ring_idle(dev, &dev_priv->blt_ring); |
2185 | if (ret) | |
2186 | return ret; | |
4df2faf4 | 2187 | |
8a1a49f9 | 2188 | return 0; |
4df2faf4 DV |
2189 | } |
2190 | ||
c6642782 DV |
2191 | static int sandybridge_write_fence_reg(struct drm_i915_gem_object *obj, |
2192 | struct intel_ring_buffer *pipelined) | |
4e901fdc | 2193 | { |
05394f39 | 2194 | struct drm_device *dev = obj->base.dev; |
4e901fdc | 2195 | drm_i915_private_t *dev_priv = dev->dev_private; |
05394f39 CW |
2196 | u32 size = obj->gtt_space->size; |
2197 | int regnum = obj->fence_reg; | |
4e901fdc EA |
2198 | uint64_t val; |
2199 | ||
05394f39 | 2200 | val = (uint64_t)((obj->gtt_offset + size - 4096) & |
c6642782 | 2201 | 0xfffff000) << 32; |
05394f39 CW |
2202 | val |= obj->gtt_offset & 0xfffff000; |
2203 | val |= (uint64_t)((obj->stride / 128) - 1) << | |
4e901fdc EA |
2204 | SANDYBRIDGE_FENCE_PITCH_SHIFT; |
2205 | ||
05394f39 | 2206 | if (obj->tiling_mode == I915_TILING_Y) |
4e901fdc EA |
2207 | val |= 1 << I965_FENCE_TILING_Y_SHIFT; |
2208 | val |= I965_FENCE_REG_VALID; | |
2209 | ||
c6642782 DV |
2210 | if (pipelined) { |
2211 | int ret = intel_ring_begin(pipelined, 6); | |
2212 | if (ret) | |
2213 | return ret; | |
2214 | ||
2215 | intel_ring_emit(pipelined, MI_NOOP); | |
2216 | intel_ring_emit(pipelined, MI_LOAD_REGISTER_IMM(2)); | |
2217 | intel_ring_emit(pipelined, FENCE_REG_SANDYBRIDGE_0 + regnum*8); | |
2218 | intel_ring_emit(pipelined, (u32)val); | |
2219 | intel_ring_emit(pipelined, FENCE_REG_SANDYBRIDGE_0 + regnum*8 + 4); | |
2220 | intel_ring_emit(pipelined, (u32)(val >> 32)); | |
2221 | intel_ring_advance(pipelined); | |
2222 | } else | |
2223 | I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + regnum * 8, val); | |
2224 | ||
2225 | return 0; | |
4e901fdc EA |
2226 | } |
2227 | ||
c6642782 DV |
2228 | static int i965_write_fence_reg(struct drm_i915_gem_object *obj, |
2229 | struct intel_ring_buffer *pipelined) | |
de151cf6 | 2230 | { |
05394f39 | 2231 | struct drm_device *dev = obj->base.dev; |
de151cf6 | 2232 | drm_i915_private_t *dev_priv = dev->dev_private; |
05394f39 CW |
2233 | u32 size = obj->gtt_space->size; |
2234 | int regnum = obj->fence_reg; | |
de151cf6 JB |
2235 | uint64_t val; |
2236 | ||
05394f39 | 2237 | val = (uint64_t)((obj->gtt_offset + size - 4096) & |
de151cf6 | 2238 | 0xfffff000) << 32; |
05394f39 CW |
2239 | val |= obj->gtt_offset & 0xfffff000; |
2240 | val |= ((obj->stride / 128) - 1) << I965_FENCE_PITCH_SHIFT; | |
2241 | if (obj->tiling_mode == I915_TILING_Y) | |
de151cf6 JB |
2242 | val |= 1 << I965_FENCE_TILING_Y_SHIFT; |
2243 | val |= I965_FENCE_REG_VALID; | |
2244 | ||
c6642782 DV |
2245 | if (pipelined) { |
2246 | int ret = intel_ring_begin(pipelined, 6); | |
2247 | if (ret) | |
2248 | return ret; | |
2249 | ||
2250 | intel_ring_emit(pipelined, MI_NOOP); | |
2251 | intel_ring_emit(pipelined, MI_LOAD_REGISTER_IMM(2)); | |
2252 | intel_ring_emit(pipelined, FENCE_REG_965_0 + regnum*8); | |
2253 | intel_ring_emit(pipelined, (u32)val); | |
2254 | intel_ring_emit(pipelined, FENCE_REG_965_0 + regnum*8 + 4); | |
2255 | intel_ring_emit(pipelined, (u32)(val >> 32)); | |
2256 | intel_ring_advance(pipelined); | |
2257 | } else | |
2258 | I915_WRITE64(FENCE_REG_965_0 + regnum * 8, val); | |
2259 | ||
2260 | return 0; | |
de151cf6 JB |
2261 | } |
2262 | ||
c6642782 DV |
2263 | static int i915_write_fence_reg(struct drm_i915_gem_object *obj, |
2264 | struct intel_ring_buffer *pipelined) | |
de151cf6 | 2265 | { |
05394f39 | 2266 | struct drm_device *dev = obj->base.dev; |
de151cf6 | 2267 | drm_i915_private_t *dev_priv = dev->dev_private; |
05394f39 | 2268 | u32 size = obj->gtt_space->size; |
c6642782 | 2269 | u32 fence_reg, val, pitch_val; |
0f973f27 | 2270 | int tile_width; |
de151cf6 | 2271 | |
c6642782 DV |
2272 | if (WARN((obj->gtt_offset & ~I915_FENCE_START_MASK) || |
2273 | (size & -size) != size || | |
2274 | (obj->gtt_offset & (size - 1)), | |
2275 | "object 0x%08x [fenceable? %d] not 1M or pot-size (0x%08x) aligned\n", | |
2276 | obj->gtt_offset, obj->map_and_fenceable, size)) | |
2277 | return -EINVAL; | |
de151cf6 | 2278 | |
c6642782 | 2279 | if (obj->tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev)) |
0f973f27 | 2280 | tile_width = 128; |
de151cf6 | 2281 | else |
0f973f27 JB |
2282 | tile_width = 512; |
2283 | ||
2284 | /* Note: pitch better be a power of two tile widths */ | |
05394f39 | 2285 | pitch_val = obj->stride / tile_width; |
0f973f27 | 2286 | pitch_val = ffs(pitch_val) - 1; |
de151cf6 | 2287 | |
05394f39 CW |
2288 | val = obj->gtt_offset; |
2289 | if (obj->tiling_mode == I915_TILING_Y) | |
de151cf6 | 2290 | val |= 1 << I830_FENCE_TILING_Y_SHIFT; |
a00b10c3 | 2291 | val |= I915_FENCE_SIZE_BITS(size); |
de151cf6 JB |
2292 | val |= pitch_val << I830_FENCE_PITCH_SHIFT; |
2293 | val |= I830_FENCE_REG_VALID; | |
2294 | ||
05394f39 | 2295 | fence_reg = obj->fence_reg; |
a00b10c3 CW |
2296 | if (fence_reg < 8) |
2297 | fence_reg = FENCE_REG_830_0 + fence_reg * 4; | |
dc529a4f | 2298 | else |
a00b10c3 | 2299 | fence_reg = FENCE_REG_945_8 + (fence_reg - 8) * 4; |
c6642782 DV |
2300 | |
2301 | if (pipelined) { | |
2302 | int ret = intel_ring_begin(pipelined, 4); | |
2303 | if (ret) | |
2304 | return ret; | |
2305 | ||
2306 | intel_ring_emit(pipelined, MI_NOOP); | |
2307 | intel_ring_emit(pipelined, MI_LOAD_REGISTER_IMM(1)); | |
2308 | intel_ring_emit(pipelined, fence_reg); | |
2309 | intel_ring_emit(pipelined, val); | |
2310 | intel_ring_advance(pipelined); | |
2311 | } else | |
2312 | I915_WRITE(fence_reg, val); | |
2313 | ||
2314 | return 0; | |
de151cf6 JB |
2315 | } |
2316 | ||
c6642782 DV |
2317 | static int i830_write_fence_reg(struct drm_i915_gem_object *obj, |
2318 | struct intel_ring_buffer *pipelined) | |
de151cf6 | 2319 | { |
05394f39 | 2320 | struct drm_device *dev = obj->base.dev; |
de151cf6 | 2321 | drm_i915_private_t *dev_priv = dev->dev_private; |
05394f39 CW |
2322 | u32 size = obj->gtt_space->size; |
2323 | int regnum = obj->fence_reg; | |
de151cf6 JB |
2324 | uint32_t val; |
2325 | uint32_t pitch_val; | |
2326 | ||
c6642782 DV |
2327 | if (WARN((obj->gtt_offset & ~I830_FENCE_START_MASK) || |
2328 | (size & -size) != size || | |
2329 | (obj->gtt_offset & (size - 1)), | |
2330 | "object 0x%08x not 512K or pot-size 0x%08x aligned\n", | |
2331 | obj->gtt_offset, size)) | |
2332 | return -EINVAL; | |
de151cf6 | 2333 | |
05394f39 | 2334 | pitch_val = obj->stride / 128; |
e76a16de | 2335 | pitch_val = ffs(pitch_val) - 1; |
e76a16de | 2336 | |
05394f39 CW |
2337 | val = obj->gtt_offset; |
2338 | if (obj->tiling_mode == I915_TILING_Y) | |
de151cf6 | 2339 | val |= 1 << I830_FENCE_TILING_Y_SHIFT; |
c6642782 | 2340 | val |= I830_FENCE_SIZE_BITS(size); |
de151cf6 JB |
2341 | val |= pitch_val << I830_FENCE_PITCH_SHIFT; |
2342 | val |= I830_FENCE_REG_VALID; | |
2343 | ||
c6642782 DV |
2344 | if (pipelined) { |
2345 | int ret = intel_ring_begin(pipelined, 4); | |
2346 | if (ret) | |
2347 | return ret; | |
2348 | ||
2349 | intel_ring_emit(pipelined, MI_NOOP); | |
2350 | intel_ring_emit(pipelined, MI_LOAD_REGISTER_IMM(1)); | |
2351 | intel_ring_emit(pipelined, FENCE_REG_830_0 + regnum*4); | |
2352 | intel_ring_emit(pipelined, val); | |
2353 | intel_ring_advance(pipelined); | |
2354 | } else | |
2355 | I915_WRITE(FENCE_REG_830_0 + regnum * 4, val); | |
2356 | ||
2357 | return 0; | |
de151cf6 JB |
2358 | } |
2359 | ||
2cf34d7b CW |
2360 | static int i915_find_fence_reg(struct drm_device *dev, |
2361 | bool interruptible) | |
ae3db24a | 2362 | { |
ae3db24a | 2363 | struct drm_i915_private *dev_priv = dev->dev_private; |
a00b10c3 | 2364 | struct drm_i915_fence_reg *reg; |
05394f39 | 2365 | struct drm_i915_gem_object *obj = NULL; |
ae3db24a DV |
2366 | int i, avail, ret; |
2367 | ||
2368 | /* First try to find a free reg */ | |
2369 | avail = 0; | |
2370 | for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) { | |
2371 | reg = &dev_priv->fence_regs[i]; | |
2372 | if (!reg->obj) | |
2373 | return i; | |
2374 | ||
05394f39 CW |
2375 | if (!reg->obj->pin_count) |
2376 | avail++; | |
ae3db24a DV |
2377 | } |
2378 | ||
2379 | if (avail == 0) | |
2380 | return -ENOSPC; | |
2381 | ||
2382 | /* None available, try to steal one or wait for a user to finish */ | |
a00b10c3 | 2383 | avail = I915_FENCE_REG_NONE; |
007cc8ac DV |
2384 | list_for_each_entry(reg, &dev_priv->mm.fence_list, |
2385 | lru_list) { | |
05394f39 CW |
2386 | obj = reg->obj; |
2387 | if (obj->pin_count) | |
ae3db24a DV |
2388 | continue; |
2389 | ||
2390 | /* found one! */ | |
05394f39 | 2391 | avail = obj->fence_reg; |
ae3db24a DV |
2392 | break; |
2393 | } | |
2394 | ||
a00b10c3 | 2395 | BUG_ON(avail == I915_FENCE_REG_NONE); |
ae3db24a DV |
2396 | |
2397 | /* We only have a reference on obj from the active list. put_fence_reg | |
2398 | * might drop that one, causing a use-after-free in it. So hold a | |
2399 | * private reference to obj like the other callers of put_fence_reg | |
2400 | * (set_tiling ioctl) do. */ | |
05394f39 CW |
2401 | drm_gem_object_reference(&obj->base); |
2402 | ret = i915_gem_object_put_fence_reg(obj, interruptible); | |
2403 | drm_gem_object_unreference(&obj->base); | |
ae3db24a DV |
2404 | if (ret != 0) |
2405 | return ret; | |
2406 | ||
a00b10c3 | 2407 | return avail; |
ae3db24a DV |
2408 | } |
2409 | ||
de151cf6 JB |
2410 | /** |
2411 | * i915_gem_object_get_fence_reg - set up a fence reg for an object | |
2412 | * @obj: object to map through a fence reg | |
2413 | * | |
2414 | * When mapping objects through the GTT, userspace wants to be able to write | |
2415 | * to them without having to worry about swizzling if the object is tiled. | |
2416 | * | |
2417 | * This function walks the fence regs looking for a free one for @obj, | |
2418 | * stealing one if it can't find any. | |
2419 | * | |
2420 | * It then sets up the reg based on the object's properties: address, pitch | |
2421 | * and tiling format. | |
2422 | */ | |
8c4b8c3f | 2423 | int |
05394f39 | 2424 | i915_gem_object_get_fence_reg(struct drm_i915_gem_object *obj, |
2cf34d7b | 2425 | bool interruptible) |
de151cf6 | 2426 | { |
05394f39 | 2427 | struct drm_device *dev = obj->base.dev; |
79e53945 | 2428 | struct drm_i915_private *dev_priv = dev->dev_private; |
de151cf6 | 2429 | struct drm_i915_fence_reg *reg = NULL; |
c6642782 | 2430 | struct intel_ring_buffer *pipelined = NULL; |
ae3db24a | 2431 | int ret; |
de151cf6 | 2432 | |
a09ba7fa | 2433 | /* Just update our place in the LRU if our fence is getting used. */ |
05394f39 CW |
2434 | if (obj->fence_reg != I915_FENCE_REG_NONE) { |
2435 | reg = &dev_priv->fence_regs[obj->fence_reg]; | |
007cc8ac | 2436 | list_move_tail(®->lru_list, &dev_priv->mm.fence_list); |
a09ba7fa EA |
2437 | return 0; |
2438 | } | |
2439 | ||
05394f39 | 2440 | switch (obj->tiling_mode) { |
de151cf6 JB |
2441 | case I915_TILING_NONE: |
2442 | WARN(1, "allocating a fence for non-tiled object?\n"); | |
2443 | break; | |
2444 | case I915_TILING_X: | |
05394f39 | 2445 | if (!obj->stride) |
0f973f27 | 2446 | return -EINVAL; |
05394f39 | 2447 | WARN((obj->stride & (512 - 1)), |
0f973f27 | 2448 | "object 0x%08x is X tiled but has non-512B pitch\n", |
05394f39 | 2449 | obj->gtt_offset); |
de151cf6 JB |
2450 | break; |
2451 | case I915_TILING_Y: | |
05394f39 | 2452 | if (!obj->stride) |
0f973f27 | 2453 | return -EINVAL; |
05394f39 | 2454 | WARN((obj->stride & (128 - 1)), |
0f973f27 | 2455 | "object 0x%08x is Y tiled but has non-128B pitch\n", |
05394f39 | 2456 | obj->gtt_offset); |
de151cf6 JB |
2457 | break; |
2458 | } | |
2459 | ||
2cf34d7b | 2460 | ret = i915_find_fence_reg(dev, interruptible); |
ae3db24a DV |
2461 | if (ret < 0) |
2462 | return ret; | |
de151cf6 | 2463 | |
05394f39 CW |
2464 | obj->fence_reg = ret; |
2465 | reg = &dev_priv->fence_regs[obj->fence_reg]; | |
007cc8ac | 2466 | list_add_tail(®->lru_list, &dev_priv->mm.fence_list); |
a09ba7fa | 2467 | |
de151cf6 JB |
2468 | reg->obj = obj; |
2469 | ||
e259befd CW |
2470 | switch (INTEL_INFO(dev)->gen) { |
2471 | case 6: | |
c6642782 | 2472 | ret = sandybridge_write_fence_reg(obj, pipelined); |
e259befd CW |
2473 | break; |
2474 | case 5: | |
2475 | case 4: | |
c6642782 | 2476 | ret = i965_write_fence_reg(obj, pipelined); |
e259befd CW |
2477 | break; |
2478 | case 3: | |
c6642782 | 2479 | ret = i915_write_fence_reg(obj, pipelined); |
e259befd CW |
2480 | break; |
2481 | case 2: | |
c6642782 | 2482 | ret = i830_write_fence_reg(obj, pipelined); |
e259befd CW |
2483 | break; |
2484 | } | |
d9ddcb96 | 2485 | |
a00b10c3 | 2486 | trace_i915_gem_object_get_fence(obj, |
05394f39 CW |
2487 | obj->fence_reg, |
2488 | obj->tiling_mode); | |
c6642782 | 2489 | return ret; |
de151cf6 JB |
2490 | } |
2491 | ||
2492 | /** | |
2493 | * i915_gem_clear_fence_reg - clear out fence register info | |
2494 | * @obj: object to clear | |
2495 | * | |
2496 | * Zeroes out the fence register itself and clears out the associated | |
05394f39 | 2497 | * data structures in dev_priv and obj. |
de151cf6 JB |
2498 | */ |
2499 | static void | |
05394f39 | 2500 | i915_gem_clear_fence_reg(struct drm_i915_gem_object *obj) |
de151cf6 | 2501 | { |
05394f39 | 2502 | struct drm_device *dev = obj->base.dev; |
79e53945 | 2503 | drm_i915_private_t *dev_priv = dev->dev_private; |
05394f39 | 2504 | struct drm_i915_fence_reg *reg = &dev_priv->fence_regs[obj->fence_reg]; |
e259befd | 2505 | uint32_t fence_reg; |
de151cf6 | 2506 | |
e259befd CW |
2507 | switch (INTEL_INFO(dev)->gen) { |
2508 | case 6: | |
4e901fdc | 2509 | I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + |
05394f39 | 2510 | (obj->fence_reg * 8), 0); |
e259befd CW |
2511 | break; |
2512 | case 5: | |
2513 | case 4: | |
05394f39 | 2514 | I915_WRITE64(FENCE_REG_965_0 + (obj->fence_reg * 8), 0); |
e259befd CW |
2515 | break; |
2516 | case 3: | |
05394f39 CW |
2517 | if (obj->fence_reg >= 8) |
2518 | fence_reg = FENCE_REG_945_8 + (obj->fence_reg - 8) * 4; | |
dc529a4f | 2519 | else |
e259befd | 2520 | case 2: |
05394f39 | 2521 | fence_reg = FENCE_REG_830_0 + obj->fence_reg * 4; |
dc529a4f EA |
2522 | |
2523 | I915_WRITE(fence_reg, 0); | |
e259befd | 2524 | break; |
dc529a4f | 2525 | } |
de151cf6 | 2526 | |
007cc8ac | 2527 | reg->obj = NULL; |
05394f39 | 2528 | obj->fence_reg = I915_FENCE_REG_NONE; |
007cc8ac | 2529 | list_del_init(®->lru_list); |
de151cf6 JB |
2530 | } |
2531 | ||
52dc7d32 CW |
2532 | /** |
2533 | * i915_gem_object_put_fence_reg - waits on outstanding fenced access | |
2534 | * to the buffer to finish, and then resets the fence register. | |
2535 | * @obj: tiled object holding a fence register. | |
2cf34d7b | 2536 | * @bool: whether the wait upon the fence is interruptible |
52dc7d32 CW |
2537 | * |
2538 | * Zeroes out the fence register itself and clears out the associated | |
05394f39 | 2539 | * data structures in dev_priv and obj. |
52dc7d32 CW |
2540 | */ |
2541 | int | |
05394f39 | 2542 | i915_gem_object_put_fence_reg(struct drm_i915_gem_object *obj, |
2cf34d7b | 2543 | bool interruptible) |
52dc7d32 | 2544 | { |
05394f39 | 2545 | struct drm_device *dev = obj->base.dev; |
caea7476 | 2546 | int ret; |
52dc7d32 | 2547 | |
05394f39 | 2548 | if (obj->fence_reg == I915_FENCE_REG_NONE) |
52dc7d32 CW |
2549 | return 0; |
2550 | ||
10ae9bd2 DV |
2551 | /* If we've changed tiling, GTT-mappings of the object |
2552 | * need to re-fault to ensure that the correct fence register | |
2553 | * setup is in place. | |
2554 | */ | |
2555 | i915_gem_release_mmap(obj); | |
2556 | ||
52dc7d32 CW |
2557 | /* On the i915, GPU access to tiled buffers is via a fence, |
2558 | * therefore we must wait for any outstanding access to complete | |
2559 | * before clearing the fence. | |
2560 | */ | |
caea7476 | 2561 | if (obj->fenced_gpu_access) { |
3619df03 | 2562 | i915_gem_object_flush_gpu_write_domain(obj); |
caea7476 CW |
2563 | obj->fenced_gpu_access = false; |
2564 | } | |
2565 | ||
2566 | if (obj->last_fenced_seqno) { | |
2567 | ret = i915_do_wait_request(dev, | |
2568 | obj->last_fenced_seqno, | |
2569 | interruptible, | |
2570 | obj->last_fenced_ring); | |
0bc23aad | 2571 | if (ret) |
52dc7d32 | 2572 | return ret; |
53640e1d | 2573 | |
caea7476 | 2574 | obj->last_fenced_seqno = false; |
52dc7d32 CW |
2575 | } |
2576 | ||
4a726612 | 2577 | i915_gem_object_flush_gtt_write_domain(obj); |
0bc23aad | 2578 | i915_gem_clear_fence_reg(obj); |
52dc7d32 CW |
2579 | |
2580 | return 0; | |
2581 | } | |
2582 | ||
673a394b EA |
2583 | /** |
2584 | * Finds free space in the GTT aperture and binds the object there. | |
2585 | */ | |
2586 | static int | |
05394f39 | 2587 | i915_gem_object_bind_to_gtt(struct drm_i915_gem_object *obj, |
920afa77 | 2588 | unsigned alignment, |
75e9e915 | 2589 | bool map_and_fenceable) |
673a394b | 2590 | { |
05394f39 | 2591 | struct drm_device *dev = obj->base.dev; |
673a394b | 2592 | drm_i915_private_t *dev_priv = dev->dev_private; |
673a394b | 2593 | struct drm_mm_node *free_space; |
a00b10c3 | 2594 | gfp_t gfpmask = __GFP_NORETRY | __GFP_NOWARN; |
5e783301 | 2595 | u32 size, fence_size, fence_alignment, unfenced_alignment; |
75e9e915 | 2596 | bool mappable, fenceable; |
07f73f69 | 2597 | int ret; |
673a394b | 2598 | |
05394f39 | 2599 | if (obj->madv != I915_MADV_WILLNEED) { |
3ef94daa CW |
2600 | DRM_ERROR("Attempting to bind a purgeable object\n"); |
2601 | return -EINVAL; | |
2602 | } | |
2603 | ||
05394f39 CW |
2604 | fence_size = i915_gem_get_gtt_size(obj); |
2605 | fence_alignment = i915_gem_get_gtt_alignment(obj); | |
2606 | unfenced_alignment = i915_gem_get_unfenced_gtt_alignment(obj); | |
a00b10c3 | 2607 | |
673a394b | 2608 | if (alignment == 0) |
5e783301 DV |
2609 | alignment = map_and_fenceable ? fence_alignment : |
2610 | unfenced_alignment; | |
75e9e915 | 2611 | if (map_and_fenceable && alignment & (fence_alignment - 1)) { |
673a394b EA |
2612 | DRM_ERROR("Invalid object alignment requested %u\n", alignment); |
2613 | return -EINVAL; | |
2614 | } | |
2615 | ||
05394f39 | 2616 | size = map_and_fenceable ? fence_size : obj->base.size; |
a00b10c3 | 2617 | |
654fc607 CW |
2618 | /* If the object is bigger than the entire aperture, reject it early |
2619 | * before evicting everything in a vain attempt to find space. | |
2620 | */ | |
05394f39 | 2621 | if (obj->base.size > |
75e9e915 | 2622 | (map_and_fenceable ? dev_priv->mm.gtt_mappable_end : dev_priv->mm.gtt_total)) { |
654fc607 CW |
2623 | DRM_ERROR("Attempting to bind an object larger than the aperture\n"); |
2624 | return -E2BIG; | |
2625 | } | |
2626 | ||
673a394b | 2627 | search_free: |
75e9e915 | 2628 | if (map_and_fenceable) |
920afa77 DV |
2629 | free_space = |
2630 | drm_mm_search_free_in_range(&dev_priv->mm.gtt_space, | |
a00b10c3 | 2631 | size, alignment, 0, |
920afa77 DV |
2632 | dev_priv->mm.gtt_mappable_end, |
2633 | 0); | |
2634 | else | |
2635 | free_space = drm_mm_search_free(&dev_priv->mm.gtt_space, | |
a00b10c3 | 2636 | size, alignment, 0); |
920afa77 DV |
2637 | |
2638 | if (free_space != NULL) { | |
75e9e915 | 2639 | if (map_and_fenceable) |
05394f39 | 2640 | obj->gtt_space = |
920afa77 | 2641 | drm_mm_get_block_range_generic(free_space, |
a00b10c3 | 2642 | size, alignment, 0, |
920afa77 DV |
2643 | dev_priv->mm.gtt_mappable_end, |
2644 | 0); | |
2645 | else | |
05394f39 | 2646 | obj->gtt_space = |
a00b10c3 | 2647 | drm_mm_get_block(free_space, size, alignment); |
920afa77 | 2648 | } |
05394f39 | 2649 | if (obj->gtt_space == NULL) { |
673a394b EA |
2650 | /* If the gtt is empty and we're still having trouble |
2651 | * fitting our object in, we're out of memory. | |
2652 | */ | |
75e9e915 DV |
2653 | ret = i915_gem_evict_something(dev, size, alignment, |
2654 | map_and_fenceable); | |
9731129c | 2655 | if (ret) |
673a394b | 2656 | return ret; |
9731129c | 2657 | |
673a394b EA |
2658 | goto search_free; |
2659 | } | |
2660 | ||
e5281ccd | 2661 | ret = i915_gem_object_get_pages_gtt(obj, gfpmask); |
673a394b | 2662 | if (ret) { |
05394f39 CW |
2663 | drm_mm_put_block(obj->gtt_space); |
2664 | obj->gtt_space = NULL; | |
07f73f69 CW |
2665 | |
2666 | if (ret == -ENOMEM) { | |
2667 | /* first try to clear up some space from the GTT */ | |
a00b10c3 | 2668 | ret = i915_gem_evict_something(dev, size, |
75e9e915 DV |
2669 | alignment, |
2670 | map_and_fenceable); | |
07f73f69 | 2671 | if (ret) { |
07f73f69 | 2672 | /* now try to shrink everyone else */ |
4bdadb97 CW |
2673 | if (gfpmask) { |
2674 | gfpmask = 0; | |
2675 | goto search_free; | |
07f73f69 CW |
2676 | } |
2677 | ||
2678 | return ret; | |
2679 | } | |
2680 | ||
2681 | goto search_free; | |
2682 | } | |
2683 | ||
673a394b EA |
2684 | return ret; |
2685 | } | |
2686 | ||
7c2e6fdf DV |
2687 | ret = i915_gem_gtt_bind_object(obj); |
2688 | if (ret) { | |
e5281ccd | 2689 | i915_gem_object_put_pages_gtt(obj); |
05394f39 CW |
2690 | drm_mm_put_block(obj->gtt_space); |
2691 | obj->gtt_space = NULL; | |
07f73f69 | 2692 | |
a00b10c3 | 2693 | ret = i915_gem_evict_something(dev, size, |
75e9e915 | 2694 | alignment, map_and_fenceable); |
9731129c | 2695 | if (ret) |
07f73f69 | 2696 | return ret; |
07f73f69 CW |
2697 | |
2698 | goto search_free; | |
673a394b | 2699 | } |
673a394b | 2700 | |
6299f992 | 2701 | list_add_tail(&obj->gtt_list, &dev_priv->mm.gtt_list); |
05394f39 | 2702 | list_add_tail(&obj->mm_list, &dev_priv->mm.inactive_list); |
bf1a1092 | 2703 | |
673a394b EA |
2704 | /* Assert that the object is not currently in any GPU domain. As it |
2705 | * wasn't in the GTT, there shouldn't be any way it could have been in | |
2706 | * a GPU cache | |
2707 | */ | |
05394f39 CW |
2708 | BUG_ON(obj->base.read_domains & I915_GEM_GPU_DOMAINS); |
2709 | BUG_ON(obj->base.write_domain & I915_GEM_GPU_DOMAINS); | |
673a394b | 2710 | |
6299f992 | 2711 | obj->gtt_offset = obj->gtt_space->start; |
1c5d22f7 | 2712 | |
75e9e915 | 2713 | fenceable = |
05394f39 CW |
2714 | obj->gtt_space->size == fence_size && |
2715 | (obj->gtt_space->start & (fence_alignment -1)) == 0; | |
a00b10c3 | 2716 | |
75e9e915 | 2717 | mappable = |
05394f39 | 2718 | obj->gtt_offset + obj->base.size <= dev_priv->mm.gtt_mappable_end; |
a00b10c3 | 2719 | |
05394f39 | 2720 | obj->map_and_fenceable = mappable && fenceable; |
75e9e915 | 2721 | |
6299f992 | 2722 | trace_i915_gem_object_bind(obj, obj->gtt_offset, map_and_fenceable); |
673a394b EA |
2723 | return 0; |
2724 | } | |
2725 | ||
2726 | void | |
05394f39 | 2727 | i915_gem_clflush_object(struct drm_i915_gem_object *obj) |
673a394b | 2728 | { |
673a394b EA |
2729 | /* If we don't have a page list set up, then we're not pinned |
2730 | * to GPU, and we can ignore the cache flush because it'll happen | |
2731 | * again at bind time. | |
2732 | */ | |
05394f39 | 2733 | if (obj->pages == NULL) |
673a394b EA |
2734 | return; |
2735 | ||
1c5d22f7 | 2736 | trace_i915_gem_object_clflush(obj); |
cfa16a0d | 2737 | |
05394f39 | 2738 | drm_clflush_pages(obj->pages, obj->base.size / PAGE_SIZE); |
673a394b EA |
2739 | } |
2740 | ||
e47c68e9 | 2741 | /** Flushes any GPU write domain for the object if it's dirty. */ |
3619df03 CW |
2742 | static void |
2743 | i915_gem_object_flush_gpu_write_domain(struct drm_i915_gem_object *obj) | |
e47c68e9 | 2744 | { |
05394f39 | 2745 | struct drm_device *dev = obj->base.dev; |
e47c68e9 | 2746 | |
05394f39 | 2747 | if ((obj->base.write_domain & I915_GEM_GPU_DOMAINS) == 0) |
3619df03 | 2748 | return; |
e47c68e9 EA |
2749 | |
2750 | /* Queue the GPU write cache flushing we need. */ | |
05394f39 CW |
2751 | i915_gem_flush_ring(dev, obj->ring, 0, obj->base.write_domain); |
2752 | BUG_ON(obj->base.write_domain); | |
e47c68e9 EA |
2753 | } |
2754 | ||
2755 | /** Flushes the GTT write domain for the object if it's dirty. */ | |
2756 | static void | |
05394f39 | 2757 | i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj) |
e47c68e9 | 2758 | { |
1c5d22f7 CW |
2759 | uint32_t old_write_domain; |
2760 | ||
05394f39 | 2761 | if (obj->base.write_domain != I915_GEM_DOMAIN_GTT) |
e47c68e9 EA |
2762 | return; |
2763 | ||
2764 | /* No actual flushing is required for the GTT write domain. Writes | |
2765 | * to it immediately go to main memory as far as we know, so there's | |
2766 | * no chipset flush. It also doesn't land in render cache. | |
2767 | */ | |
4a684a41 CW |
2768 | i915_gem_release_mmap(obj); |
2769 | ||
05394f39 CW |
2770 | old_write_domain = obj->base.write_domain; |
2771 | obj->base.write_domain = 0; | |
1c5d22f7 CW |
2772 | |
2773 | trace_i915_gem_object_change_domain(obj, | |
05394f39 | 2774 | obj->base.read_domains, |
1c5d22f7 | 2775 | old_write_domain); |
e47c68e9 EA |
2776 | } |
2777 | ||
2778 | /** Flushes the CPU write domain for the object if it's dirty. */ | |
2779 | static void | |
05394f39 | 2780 | i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj) |
e47c68e9 | 2781 | { |
1c5d22f7 | 2782 | uint32_t old_write_domain; |
e47c68e9 | 2783 | |
05394f39 | 2784 | if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) |
e47c68e9 EA |
2785 | return; |
2786 | ||
2787 | i915_gem_clflush_object(obj); | |
40ce6575 | 2788 | intel_gtt_chipset_flush(); |
05394f39 CW |
2789 | old_write_domain = obj->base.write_domain; |
2790 | obj->base.write_domain = 0; | |
1c5d22f7 CW |
2791 | |
2792 | trace_i915_gem_object_change_domain(obj, | |
05394f39 | 2793 | obj->base.read_domains, |
1c5d22f7 | 2794 | old_write_domain); |
e47c68e9 EA |
2795 | } |
2796 | ||
2ef7eeaa EA |
2797 | /** |
2798 | * Moves a single object to the GTT read, and possibly write domain. | |
2799 | * | |
2800 | * This function returns when the move is complete, including waiting on | |
2801 | * flushes to occur. | |
2802 | */ | |
79e53945 | 2803 | int |
2021746e | 2804 | i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write) |
2ef7eeaa | 2805 | { |
1c5d22f7 | 2806 | uint32_t old_write_domain, old_read_domains; |
e47c68e9 | 2807 | int ret; |
2ef7eeaa | 2808 | |
02354392 | 2809 | /* Not valid to be called on unbound objects. */ |
05394f39 | 2810 | if (obj->gtt_space == NULL) |
02354392 EA |
2811 | return -EINVAL; |
2812 | ||
3619df03 | 2813 | i915_gem_object_flush_gpu_write_domain(obj); |
87ca9c8a CW |
2814 | if (obj->pending_gpu_write || write) { |
2815 | ret = i915_gem_object_wait_rendering(obj, true); | |
2816 | if (ret) | |
2817 | return ret; | |
2818 | } | |
2dafb1e0 | 2819 | |
7213342d | 2820 | i915_gem_object_flush_cpu_write_domain(obj); |
1c5d22f7 | 2821 | |
05394f39 CW |
2822 | old_write_domain = obj->base.write_domain; |
2823 | old_read_domains = obj->base.read_domains; | |
1c5d22f7 | 2824 | |
e47c68e9 EA |
2825 | /* It should now be out of any other write domains, and we can update |
2826 | * the domain values for our changes. | |
2827 | */ | |
05394f39 CW |
2828 | BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) != 0); |
2829 | obj->base.read_domains |= I915_GEM_DOMAIN_GTT; | |
e47c68e9 | 2830 | if (write) { |
05394f39 CW |
2831 | obj->base.read_domains = I915_GEM_DOMAIN_GTT; |
2832 | obj->base.write_domain = I915_GEM_DOMAIN_GTT; | |
2833 | obj->dirty = 1; | |
2ef7eeaa EA |
2834 | } |
2835 | ||
1c5d22f7 CW |
2836 | trace_i915_gem_object_change_domain(obj, |
2837 | old_read_domains, | |
2838 | old_write_domain); | |
2839 | ||
e47c68e9 EA |
2840 | return 0; |
2841 | } | |
2842 | ||
b9241ea3 ZW |
2843 | /* |
2844 | * Prepare buffer for display plane. Use uninterruptible for possible flush | |
2845 | * wait, as in modesetting process we're not supposed to be interrupted. | |
2846 | */ | |
2847 | int | |
05394f39 | 2848 | i915_gem_object_set_to_display_plane(struct drm_i915_gem_object *obj, |
919926ae | 2849 | struct intel_ring_buffer *pipelined) |
b9241ea3 | 2850 | { |
ba3d8d74 | 2851 | uint32_t old_read_domains; |
b9241ea3 ZW |
2852 | int ret; |
2853 | ||
2854 | /* Not valid to be called on unbound objects. */ | |
05394f39 | 2855 | if (obj->gtt_space == NULL) |
b9241ea3 ZW |
2856 | return -EINVAL; |
2857 | ||
3619df03 | 2858 | i915_gem_object_flush_gpu_write_domain(obj); |
b9241ea3 | 2859 | |
ced270fa CW |
2860 | /* Currently, we are always called from an non-interruptible context. */ |
2861 | if (!pipelined) { | |
2862 | ret = i915_gem_object_wait_rendering(obj, false); | |
2863 | if (ret) | |
b9241ea3 ZW |
2864 | return ret; |
2865 | } | |
2866 | ||
b118c1e3 CW |
2867 | i915_gem_object_flush_cpu_write_domain(obj); |
2868 | ||
05394f39 CW |
2869 | old_read_domains = obj->base.read_domains; |
2870 | obj->base.read_domains |= I915_GEM_DOMAIN_GTT; | |
b9241ea3 ZW |
2871 | |
2872 | trace_i915_gem_object_change_domain(obj, | |
2873 | old_read_domains, | |
05394f39 | 2874 | obj->base.write_domain); |
b9241ea3 ZW |
2875 | |
2876 | return 0; | |
2877 | } | |
2878 | ||
85345517 CW |
2879 | int |
2880 | i915_gem_object_flush_gpu(struct drm_i915_gem_object *obj, | |
2881 | bool interruptible) | |
2882 | { | |
2883 | if (!obj->active) | |
2884 | return 0; | |
2885 | ||
2886 | if (obj->base.write_domain & I915_GEM_GPU_DOMAINS) | |
05394f39 | 2887 | i915_gem_flush_ring(obj->base.dev, obj->ring, |
85345517 CW |
2888 | 0, obj->base.write_domain); |
2889 | ||
05394f39 | 2890 | return i915_gem_object_wait_rendering(obj, interruptible); |
85345517 CW |
2891 | } |
2892 | ||
e47c68e9 EA |
2893 | /** |
2894 | * Moves a single object to the CPU read, and possibly write domain. | |
2895 | * | |
2896 | * This function returns when the move is complete, including waiting on | |
2897 | * flushes to occur. | |
2898 | */ | |
2899 | static int | |
919926ae | 2900 | i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write) |
e47c68e9 | 2901 | { |
1c5d22f7 | 2902 | uint32_t old_write_domain, old_read_domains; |
e47c68e9 EA |
2903 | int ret; |
2904 | ||
3619df03 | 2905 | i915_gem_object_flush_gpu_write_domain(obj); |
de18a29e DV |
2906 | ret = i915_gem_object_wait_rendering(obj, true); |
2907 | if (ret) | |
e47c68e9 | 2908 | return ret; |
2ef7eeaa | 2909 | |
e47c68e9 | 2910 | i915_gem_object_flush_gtt_write_domain(obj); |
2ef7eeaa | 2911 | |
e47c68e9 EA |
2912 | /* If we have a partially-valid cache of the object in the CPU, |
2913 | * finish invalidating it and free the per-page flags. | |
2ef7eeaa | 2914 | */ |
e47c68e9 | 2915 | i915_gem_object_set_to_full_cpu_read_domain(obj); |
2ef7eeaa | 2916 | |
05394f39 CW |
2917 | old_write_domain = obj->base.write_domain; |
2918 | old_read_domains = obj->base.read_domains; | |
1c5d22f7 | 2919 | |
e47c68e9 | 2920 | /* Flush the CPU cache if it's still invalid. */ |
05394f39 | 2921 | if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) { |
2ef7eeaa | 2922 | i915_gem_clflush_object(obj); |
2ef7eeaa | 2923 | |
05394f39 | 2924 | obj->base.read_domains |= I915_GEM_DOMAIN_CPU; |
2ef7eeaa EA |
2925 | } |
2926 | ||
2927 | /* It should now be out of any other write domains, and we can update | |
2928 | * the domain values for our changes. | |
2929 | */ | |
05394f39 | 2930 | BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) != 0); |
e47c68e9 EA |
2931 | |
2932 | /* If we're writing through the CPU, then the GPU read domains will | |
2933 | * need to be invalidated at next use. | |
2934 | */ | |
2935 | if (write) { | |
05394f39 CW |
2936 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; |
2937 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; | |
e47c68e9 | 2938 | } |
2ef7eeaa | 2939 | |
1c5d22f7 CW |
2940 | trace_i915_gem_object_change_domain(obj, |
2941 | old_read_domains, | |
2942 | old_write_domain); | |
2943 | ||
2ef7eeaa EA |
2944 | return 0; |
2945 | } | |
2946 | ||
673a394b | 2947 | /** |
e47c68e9 | 2948 | * Moves the object from a partially CPU read to a full one. |
673a394b | 2949 | * |
e47c68e9 EA |
2950 | * Note that this only resolves i915_gem_object_set_cpu_read_domain_range(), |
2951 | * and doesn't handle transitioning from !(read_domains & I915_GEM_DOMAIN_CPU). | |
673a394b | 2952 | */ |
e47c68e9 | 2953 | static void |
05394f39 | 2954 | i915_gem_object_set_to_full_cpu_read_domain(struct drm_i915_gem_object *obj) |
673a394b | 2955 | { |
05394f39 | 2956 | if (!obj->page_cpu_valid) |
e47c68e9 EA |
2957 | return; |
2958 | ||
2959 | /* If we're partially in the CPU read domain, finish moving it in. | |
2960 | */ | |
05394f39 | 2961 | if (obj->base.read_domains & I915_GEM_DOMAIN_CPU) { |
e47c68e9 EA |
2962 | int i; |
2963 | ||
05394f39 CW |
2964 | for (i = 0; i <= (obj->base.size - 1) / PAGE_SIZE; i++) { |
2965 | if (obj->page_cpu_valid[i]) | |
e47c68e9 | 2966 | continue; |
05394f39 | 2967 | drm_clflush_pages(obj->pages + i, 1); |
e47c68e9 | 2968 | } |
e47c68e9 EA |
2969 | } |
2970 | ||
2971 | /* Free the page_cpu_valid mappings which are now stale, whether | |
2972 | * or not we've got I915_GEM_DOMAIN_CPU. | |
2973 | */ | |
05394f39 CW |
2974 | kfree(obj->page_cpu_valid); |
2975 | obj->page_cpu_valid = NULL; | |
e47c68e9 EA |
2976 | } |
2977 | ||
2978 | /** | |
2979 | * Set the CPU read domain on a range of the object. | |
2980 | * | |
2981 | * The object ends up with I915_GEM_DOMAIN_CPU in its read flags although it's | |
2982 | * not entirely valid. The page_cpu_valid member of the object flags which | |
2983 | * pages have been flushed, and will be respected by | |
2984 | * i915_gem_object_set_to_cpu_domain() if it's called on to get a valid mapping | |
2985 | * of the whole object. | |
2986 | * | |
2987 | * This function returns when the move is complete, including waiting on | |
2988 | * flushes to occur. | |
2989 | */ | |
2990 | static int | |
05394f39 | 2991 | i915_gem_object_set_cpu_read_domain_range(struct drm_i915_gem_object *obj, |
e47c68e9 EA |
2992 | uint64_t offset, uint64_t size) |
2993 | { | |
1c5d22f7 | 2994 | uint32_t old_read_domains; |
e47c68e9 | 2995 | int i, ret; |
673a394b | 2996 | |
05394f39 | 2997 | if (offset == 0 && size == obj->base.size) |
e47c68e9 | 2998 | return i915_gem_object_set_to_cpu_domain(obj, 0); |
673a394b | 2999 | |
3619df03 | 3000 | i915_gem_object_flush_gpu_write_domain(obj); |
de18a29e DV |
3001 | ret = i915_gem_object_wait_rendering(obj, true); |
3002 | if (ret) | |
6a47baa6 | 3003 | return ret; |
de18a29e | 3004 | |
e47c68e9 EA |
3005 | i915_gem_object_flush_gtt_write_domain(obj); |
3006 | ||
3007 | /* If we're already fully in the CPU read domain, we're done. */ | |
05394f39 CW |
3008 | if (obj->page_cpu_valid == NULL && |
3009 | (obj->base.read_domains & I915_GEM_DOMAIN_CPU) != 0) | |
e47c68e9 | 3010 | return 0; |
673a394b | 3011 | |
e47c68e9 EA |
3012 | /* Otherwise, create/clear the per-page CPU read domain flag if we're |
3013 | * newly adding I915_GEM_DOMAIN_CPU | |
3014 | */ | |
05394f39 CW |
3015 | if (obj->page_cpu_valid == NULL) { |
3016 | obj->page_cpu_valid = kzalloc(obj->base.size / PAGE_SIZE, | |
3017 | GFP_KERNEL); | |
3018 | if (obj->page_cpu_valid == NULL) | |
e47c68e9 | 3019 | return -ENOMEM; |
05394f39 CW |
3020 | } else if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) |
3021 | memset(obj->page_cpu_valid, 0, obj->base.size / PAGE_SIZE); | |
673a394b EA |
3022 | |
3023 | /* Flush the cache on any pages that are still invalid from the CPU's | |
3024 | * perspective. | |
3025 | */ | |
e47c68e9 EA |
3026 | for (i = offset / PAGE_SIZE; i <= (offset + size - 1) / PAGE_SIZE; |
3027 | i++) { | |
05394f39 | 3028 | if (obj->page_cpu_valid[i]) |
673a394b EA |
3029 | continue; |
3030 | ||
05394f39 | 3031 | drm_clflush_pages(obj->pages + i, 1); |
673a394b | 3032 | |
05394f39 | 3033 | obj->page_cpu_valid[i] = 1; |
673a394b EA |
3034 | } |
3035 | ||
e47c68e9 EA |
3036 | /* It should now be out of any other write domains, and we can update |
3037 | * the domain values for our changes. | |
3038 | */ | |
05394f39 | 3039 | BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) != 0); |
e47c68e9 | 3040 | |
05394f39 CW |
3041 | old_read_domains = obj->base.read_domains; |
3042 | obj->base.read_domains |= I915_GEM_DOMAIN_CPU; | |
e47c68e9 | 3043 | |
1c5d22f7 CW |
3044 | trace_i915_gem_object_change_domain(obj, |
3045 | old_read_domains, | |
05394f39 | 3046 | obj->base.write_domain); |
1c5d22f7 | 3047 | |
673a394b EA |
3048 | return 0; |
3049 | } | |
3050 | ||
673a394b EA |
3051 | /* Throttle our rendering by waiting until the ring has completed our requests |
3052 | * emitted over 20 msec ago. | |
3053 | * | |
b962442e EA |
3054 | * Note that if we were to use the current jiffies each time around the loop, |
3055 | * we wouldn't escape the function with any frames outstanding if the time to | |
3056 | * render a frame was over 20ms. | |
3057 | * | |
673a394b EA |
3058 | * This should get us reasonable parallelism between CPU and GPU but also |
3059 | * relatively low latency when blocking on a particular request to finish. | |
3060 | */ | |
40a5f0de | 3061 | static int |
f787a5f5 | 3062 | i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file) |
40a5f0de | 3063 | { |
f787a5f5 CW |
3064 | struct drm_i915_private *dev_priv = dev->dev_private; |
3065 | struct drm_i915_file_private *file_priv = file->driver_priv; | |
b962442e | 3066 | unsigned long recent_enough = jiffies - msecs_to_jiffies(20); |
f787a5f5 CW |
3067 | struct drm_i915_gem_request *request; |
3068 | struct intel_ring_buffer *ring = NULL; | |
3069 | u32 seqno = 0; | |
3070 | int ret; | |
93533c29 | 3071 | |
1c25595f | 3072 | spin_lock(&file_priv->mm.lock); |
f787a5f5 | 3073 | list_for_each_entry(request, &file_priv->mm.request_list, client_list) { |
b962442e EA |
3074 | if (time_after_eq(request->emitted_jiffies, recent_enough)) |
3075 | break; | |
40a5f0de | 3076 | |
f787a5f5 CW |
3077 | ring = request->ring; |
3078 | seqno = request->seqno; | |
b962442e | 3079 | } |
1c25595f | 3080 | spin_unlock(&file_priv->mm.lock); |
40a5f0de | 3081 | |
f787a5f5 CW |
3082 | if (seqno == 0) |
3083 | return 0; | |
2bc43b5c | 3084 | |
f787a5f5 | 3085 | ret = 0; |
78501eac | 3086 | if (!i915_seqno_passed(ring->get_seqno(ring), seqno)) { |
f787a5f5 CW |
3087 | /* And wait for the seqno passing without holding any locks and |
3088 | * causing extra latency for others. This is safe as the irq | |
3089 | * generation is designed to be run atomically and so is | |
3090 | * lockless. | |
3091 | */ | |
78501eac | 3092 | ring->user_irq_get(ring); |
f787a5f5 | 3093 | ret = wait_event_interruptible(ring->irq_queue, |
78501eac | 3094 | i915_seqno_passed(ring->get_seqno(ring), seqno) |
f787a5f5 | 3095 | || atomic_read(&dev_priv->mm.wedged)); |
78501eac | 3096 | ring->user_irq_put(ring); |
40a5f0de | 3097 | |
f787a5f5 CW |
3098 | if (ret == 0 && atomic_read(&dev_priv->mm.wedged)) |
3099 | ret = -EIO; | |
40a5f0de EA |
3100 | } |
3101 | ||
f787a5f5 CW |
3102 | if (ret == 0) |
3103 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, 0); | |
40a5f0de EA |
3104 | |
3105 | return ret; | |
3106 | } | |
3107 | ||
673a394b | 3108 | int |
05394f39 CW |
3109 | i915_gem_object_pin(struct drm_i915_gem_object *obj, |
3110 | uint32_t alignment, | |
75e9e915 | 3111 | bool map_and_fenceable) |
673a394b | 3112 | { |
05394f39 | 3113 | struct drm_device *dev = obj->base.dev; |
f13d3f73 | 3114 | struct drm_i915_private *dev_priv = dev->dev_private; |
673a394b EA |
3115 | int ret; |
3116 | ||
05394f39 | 3117 | BUG_ON(obj->pin_count == DRM_I915_GEM_OBJECT_MAX_PIN_COUNT); |
23bc5982 | 3118 | WARN_ON(i915_verify_lists(dev)); |
ac0c6b5a | 3119 | |
05394f39 CW |
3120 | if (obj->gtt_space != NULL) { |
3121 | if ((alignment && obj->gtt_offset & (alignment - 1)) || | |
3122 | (map_and_fenceable && !obj->map_and_fenceable)) { | |
3123 | WARN(obj->pin_count, | |
ae7d49d8 | 3124 | "bo is already pinned with incorrect alignment:" |
75e9e915 DV |
3125 | " offset=%x, req.alignment=%x, req.map_and_fenceable=%d," |
3126 | " obj->map_and_fenceable=%d\n", | |
05394f39 | 3127 | obj->gtt_offset, alignment, |
75e9e915 | 3128 | map_and_fenceable, |
05394f39 | 3129 | obj->map_and_fenceable); |
ac0c6b5a CW |
3130 | ret = i915_gem_object_unbind(obj); |
3131 | if (ret) | |
3132 | return ret; | |
3133 | } | |
3134 | } | |
3135 | ||
05394f39 | 3136 | if (obj->gtt_space == NULL) { |
a00b10c3 | 3137 | ret = i915_gem_object_bind_to_gtt(obj, alignment, |
75e9e915 | 3138 | map_and_fenceable); |
9731129c | 3139 | if (ret) |
673a394b | 3140 | return ret; |
22c344e9 | 3141 | } |
76446cac | 3142 | |
05394f39 | 3143 | if (obj->pin_count++ == 0) { |
05394f39 CW |
3144 | if (!obj->active) |
3145 | list_move_tail(&obj->mm_list, | |
f13d3f73 | 3146 | &dev_priv->mm.pinned_list); |
673a394b | 3147 | } |
6299f992 | 3148 | obj->pin_mappable |= map_and_fenceable; |
673a394b | 3149 | |
23bc5982 | 3150 | WARN_ON(i915_verify_lists(dev)); |
673a394b EA |
3151 | return 0; |
3152 | } | |
3153 | ||
3154 | void | |
05394f39 | 3155 | i915_gem_object_unpin(struct drm_i915_gem_object *obj) |
673a394b | 3156 | { |
05394f39 | 3157 | struct drm_device *dev = obj->base.dev; |
673a394b | 3158 | drm_i915_private_t *dev_priv = dev->dev_private; |
673a394b | 3159 | |
23bc5982 | 3160 | WARN_ON(i915_verify_lists(dev)); |
05394f39 CW |
3161 | BUG_ON(obj->pin_count == 0); |
3162 | BUG_ON(obj->gtt_space == NULL); | |
673a394b | 3163 | |
05394f39 CW |
3164 | if (--obj->pin_count == 0) { |
3165 | if (!obj->active) | |
3166 | list_move_tail(&obj->mm_list, | |
673a394b | 3167 | &dev_priv->mm.inactive_list); |
6299f992 | 3168 | obj->pin_mappable = false; |
673a394b | 3169 | } |
23bc5982 | 3170 | WARN_ON(i915_verify_lists(dev)); |
673a394b EA |
3171 | } |
3172 | ||
3173 | int | |
3174 | i915_gem_pin_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 3175 | struct drm_file *file) |
673a394b EA |
3176 | { |
3177 | struct drm_i915_gem_pin *args = data; | |
05394f39 | 3178 | struct drm_i915_gem_object *obj; |
673a394b EA |
3179 | int ret; |
3180 | ||
1d7cfea1 CW |
3181 | ret = i915_mutex_lock_interruptible(dev); |
3182 | if (ret) | |
3183 | return ret; | |
673a394b | 3184 | |
05394f39 | 3185 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
673a394b | 3186 | if (obj == NULL) { |
1d7cfea1 CW |
3187 | ret = -ENOENT; |
3188 | goto unlock; | |
673a394b | 3189 | } |
673a394b | 3190 | |
05394f39 | 3191 | if (obj->madv != I915_MADV_WILLNEED) { |
bb6baf76 | 3192 | DRM_ERROR("Attempting to pin a purgeable buffer\n"); |
1d7cfea1 CW |
3193 | ret = -EINVAL; |
3194 | goto out; | |
3ef94daa CW |
3195 | } |
3196 | ||
05394f39 | 3197 | if (obj->pin_filp != NULL && obj->pin_filp != file) { |
79e53945 JB |
3198 | DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n", |
3199 | args->handle); | |
1d7cfea1 CW |
3200 | ret = -EINVAL; |
3201 | goto out; | |
79e53945 JB |
3202 | } |
3203 | ||
05394f39 CW |
3204 | obj->user_pin_count++; |
3205 | obj->pin_filp = file; | |
3206 | if (obj->user_pin_count == 1) { | |
75e9e915 | 3207 | ret = i915_gem_object_pin(obj, args->alignment, true); |
1d7cfea1 CW |
3208 | if (ret) |
3209 | goto out; | |
673a394b EA |
3210 | } |
3211 | ||
3212 | /* XXX - flush the CPU caches for pinned objects | |
3213 | * as the X server doesn't manage domains yet | |
3214 | */ | |
e47c68e9 | 3215 | i915_gem_object_flush_cpu_write_domain(obj); |
05394f39 | 3216 | args->offset = obj->gtt_offset; |
1d7cfea1 | 3217 | out: |
05394f39 | 3218 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 3219 | unlock: |
673a394b | 3220 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 3221 | return ret; |
673a394b EA |
3222 | } |
3223 | ||
3224 | int | |
3225 | i915_gem_unpin_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 3226 | struct drm_file *file) |
673a394b EA |
3227 | { |
3228 | struct drm_i915_gem_pin *args = data; | |
05394f39 | 3229 | struct drm_i915_gem_object *obj; |
76c1dec1 | 3230 | int ret; |
673a394b | 3231 | |
1d7cfea1 CW |
3232 | ret = i915_mutex_lock_interruptible(dev); |
3233 | if (ret) | |
3234 | return ret; | |
673a394b | 3235 | |
05394f39 | 3236 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
673a394b | 3237 | if (obj == NULL) { |
1d7cfea1 CW |
3238 | ret = -ENOENT; |
3239 | goto unlock; | |
673a394b | 3240 | } |
76c1dec1 | 3241 | |
05394f39 | 3242 | if (obj->pin_filp != file) { |
79e53945 JB |
3243 | DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n", |
3244 | args->handle); | |
1d7cfea1 CW |
3245 | ret = -EINVAL; |
3246 | goto out; | |
79e53945 | 3247 | } |
05394f39 CW |
3248 | obj->user_pin_count--; |
3249 | if (obj->user_pin_count == 0) { | |
3250 | obj->pin_filp = NULL; | |
79e53945 JB |
3251 | i915_gem_object_unpin(obj); |
3252 | } | |
673a394b | 3253 | |
1d7cfea1 | 3254 | out: |
05394f39 | 3255 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 3256 | unlock: |
673a394b | 3257 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 3258 | return ret; |
673a394b EA |
3259 | } |
3260 | ||
3261 | int | |
3262 | i915_gem_busy_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 3263 | struct drm_file *file) |
673a394b EA |
3264 | { |
3265 | struct drm_i915_gem_busy *args = data; | |
05394f39 | 3266 | struct drm_i915_gem_object *obj; |
30dbf0c0 CW |
3267 | int ret; |
3268 | ||
76c1dec1 | 3269 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 3270 | if (ret) |
76c1dec1 | 3271 | return ret; |
673a394b | 3272 | |
05394f39 | 3273 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
673a394b | 3274 | if (obj == NULL) { |
1d7cfea1 CW |
3275 | ret = -ENOENT; |
3276 | goto unlock; | |
673a394b | 3277 | } |
d1b851fc | 3278 | |
0be555b6 CW |
3279 | /* Count all active objects as busy, even if they are currently not used |
3280 | * by the gpu. Users of this interface expect objects to eventually | |
3281 | * become non-busy without any further actions, therefore emit any | |
3282 | * necessary flushes here. | |
c4de0a5d | 3283 | */ |
05394f39 | 3284 | args->busy = obj->active; |
0be555b6 CW |
3285 | if (args->busy) { |
3286 | /* Unconditionally flush objects, even when the gpu still uses this | |
3287 | * object. Userspace calling this function indicates that it wants to | |
3288 | * use this buffer rather sooner than later, so issuing the required | |
3289 | * flush earlier is beneficial. | |
3290 | */ | |
05394f39 CW |
3291 | if (obj->base.write_domain & I915_GEM_GPU_DOMAINS) |
3292 | i915_gem_flush_ring(dev, obj->ring, | |
3293 | 0, obj->base.write_domain); | |
0be555b6 CW |
3294 | |
3295 | /* Update the active list for the hardware's current position. | |
3296 | * Otherwise this only updates on a delayed timer or when irqs | |
3297 | * are actually unmasked, and our working set ends up being | |
3298 | * larger than required. | |
3299 | */ | |
05394f39 | 3300 | i915_gem_retire_requests_ring(dev, obj->ring); |
0be555b6 | 3301 | |
05394f39 | 3302 | args->busy = obj->active; |
0be555b6 | 3303 | } |
673a394b | 3304 | |
05394f39 | 3305 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 3306 | unlock: |
673a394b | 3307 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 3308 | return ret; |
673a394b EA |
3309 | } |
3310 | ||
3311 | int | |
3312 | i915_gem_throttle_ioctl(struct drm_device *dev, void *data, | |
3313 | struct drm_file *file_priv) | |
3314 | { | |
3315 | return i915_gem_ring_throttle(dev, file_priv); | |
3316 | } | |
3317 | ||
3ef94daa CW |
3318 | int |
3319 | i915_gem_madvise_ioctl(struct drm_device *dev, void *data, | |
3320 | struct drm_file *file_priv) | |
3321 | { | |
3322 | struct drm_i915_gem_madvise *args = data; | |
05394f39 | 3323 | struct drm_i915_gem_object *obj; |
76c1dec1 | 3324 | int ret; |
3ef94daa CW |
3325 | |
3326 | switch (args->madv) { | |
3327 | case I915_MADV_DONTNEED: | |
3328 | case I915_MADV_WILLNEED: | |
3329 | break; | |
3330 | default: | |
3331 | return -EINVAL; | |
3332 | } | |
3333 | ||
1d7cfea1 CW |
3334 | ret = i915_mutex_lock_interruptible(dev); |
3335 | if (ret) | |
3336 | return ret; | |
3337 | ||
05394f39 | 3338 | obj = to_intel_bo(drm_gem_object_lookup(dev, file_priv, args->handle)); |
3ef94daa | 3339 | if (obj == NULL) { |
1d7cfea1 CW |
3340 | ret = -ENOENT; |
3341 | goto unlock; | |
3ef94daa | 3342 | } |
3ef94daa | 3343 | |
05394f39 | 3344 | if (obj->pin_count) { |
1d7cfea1 CW |
3345 | ret = -EINVAL; |
3346 | goto out; | |
3ef94daa CW |
3347 | } |
3348 | ||
05394f39 CW |
3349 | if (obj->madv != __I915_MADV_PURGED) |
3350 | obj->madv = args->madv; | |
3ef94daa | 3351 | |
2d7ef395 | 3352 | /* if the object is no longer bound, discard its backing storage */ |
05394f39 CW |
3353 | if (i915_gem_object_is_purgeable(obj) && |
3354 | obj->gtt_space == NULL) | |
2d7ef395 CW |
3355 | i915_gem_object_truncate(obj); |
3356 | ||
05394f39 | 3357 | args->retained = obj->madv != __I915_MADV_PURGED; |
bb6baf76 | 3358 | |
1d7cfea1 | 3359 | out: |
05394f39 | 3360 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 3361 | unlock: |
3ef94daa | 3362 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 3363 | return ret; |
3ef94daa CW |
3364 | } |
3365 | ||
05394f39 CW |
3366 | struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev, |
3367 | size_t size) | |
ac52bc56 | 3368 | { |
73aa808f | 3369 | struct drm_i915_private *dev_priv = dev->dev_private; |
c397b908 | 3370 | struct drm_i915_gem_object *obj; |
ac52bc56 | 3371 | |
c397b908 DV |
3372 | obj = kzalloc(sizeof(*obj), GFP_KERNEL); |
3373 | if (obj == NULL) | |
3374 | return NULL; | |
673a394b | 3375 | |
c397b908 DV |
3376 | if (drm_gem_object_init(dev, &obj->base, size) != 0) { |
3377 | kfree(obj); | |
3378 | return NULL; | |
3379 | } | |
673a394b | 3380 | |
73aa808f CW |
3381 | i915_gem_info_add_obj(dev_priv, size); |
3382 | ||
c397b908 DV |
3383 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; |
3384 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; | |
673a394b | 3385 | |
c397b908 | 3386 | obj->agp_type = AGP_USER_MEMORY; |
62b8b215 | 3387 | obj->base.driver_private = NULL; |
c397b908 | 3388 | obj->fence_reg = I915_FENCE_REG_NONE; |
69dc4987 | 3389 | INIT_LIST_HEAD(&obj->mm_list); |
93a37f20 | 3390 | INIT_LIST_HEAD(&obj->gtt_list); |
69dc4987 | 3391 | INIT_LIST_HEAD(&obj->ring_list); |
432e58ed | 3392 | INIT_LIST_HEAD(&obj->exec_list); |
c397b908 | 3393 | INIT_LIST_HEAD(&obj->gpu_write_list); |
c397b908 | 3394 | obj->madv = I915_MADV_WILLNEED; |
75e9e915 DV |
3395 | /* Avoid an unnecessary call to unbind on the first bind. */ |
3396 | obj->map_and_fenceable = true; | |
de151cf6 | 3397 | |
05394f39 | 3398 | return obj; |
c397b908 DV |
3399 | } |
3400 | ||
3401 | int i915_gem_init_object(struct drm_gem_object *obj) | |
3402 | { | |
3403 | BUG(); | |
de151cf6 | 3404 | |
673a394b EA |
3405 | return 0; |
3406 | } | |
3407 | ||
05394f39 | 3408 | static void i915_gem_free_object_tail(struct drm_i915_gem_object *obj) |
673a394b | 3409 | { |
05394f39 | 3410 | struct drm_device *dev = obj->base.dev; |
be72615b | 3411 | drm_i915_private_t *dev_priv = dev->dev_private; |
be72615b | 3412 | int ret; |
673a394b | 3413 | |
be72615b CW |
3414 | ret = i915_gem_object_unbind(obj); |
3415 | if (ret == -ERESTARTSYS) { | |
05394f39 | 3416 | list_move(&obj->mm_list, |
be72615b CW |
3417 | &dev_priv->mm.deferred_free_list); |
3418 | return; | |
3419 | } | |
673a394b | 3420 | |
05394f39 | 3421 | if (obj->base.map_list.map) |
7e616158 | 3422 | i915_gem_free_mmap_offset(obj); |
de151cf6 | 3423 | |
05394f39 CW |
3424 | drm_gem_object_release(&obj->base); |
3425 | i915_gem_info_remove_obj(dev_priv, obj->base.size); | |
c397b908 | 3426 | |
05394f39 CW |
3427 | kfree(obj->page_cpu_valid); |
3428 | kfree(obj->bit_17); | |
3429 | kfree(obj); | |
673a394b EA |
3430 | } |
3431 | ||
05394f39 | 3432 | void i915_gem_free_object(struct drm_gem_object *gem_obj) |
be72615b | 3433 | { |
05394f39 CW |
3434 | struct drm_i915_gem_object *obj = to_intel_bo(gem_obj); |
3435 | struct drm_device *dev = obj->base.dev; | |
be72615b CW |
3436 | |
3437 | trace_i915_gem_object_destroy(obj); | |
3438 | ||
05394f39 | 3439 | while (obj->pin_count > 0) |
be72615b CW |
3440 | i915_gem_object_unpin(obj); |
3441 | ||
05394f39 | 3442 | if (obj->phys_obj) |
be72615b CW |
3443 | i915_gem_detach_phys_object(dev, obj); |
3444 | ||
3445 | i915_gem_free_object_tail(obj); | |
3446 | } | |
3447 | ||
29105ccc CW |
3448 | int |
3449 | i915_gem_idle(struct drm_device *dev) | |
3450 | { | |
3451 | drm_i915_private_t *dev_priv = dev->dev_private; | |
3452 | int ret; | |
28dfe52a | 3453 | |
29105ccc | 3454 | mutex_lock(&dev->struct_mutex); |
1c5d22f7 | 3455 | |
87acb0a5 | 3456 | if (dev_priv->mm.suspended) { |
29105ccc CW |
3457 | mutex_unlock(&dev->struct_mutex); |
3458 | return 0; | |
28dfe52a EA |
3459 | } |
3460 | ||
29105ccc | 3461 | ret = i915_gpu_idle(dev); |
6dbe2772 KP |
3462 | if (ret) { |
3463 | mutex_unlock(&dev->struct_mutex); | |
673a394b | 3464 | return ret; |
6dbe2772 | 3465 | } |
673a394b | 3466 | |
29105ccc CW |
3467 | /* Under UMS, be paranoid and evict. */ |
3468 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) { | |
5eac3ab4 | 3469 | ret = i915_gem_evict_inactive(dev, false); |
29105ccc CW |
3470 | if (ret) { |
3471 | mutex_unlock(&dev->struct_mutex); | |
3472 | return ret; | |
3473 | } | |
3474 | } | |
3475 | ||
312817a3 CW |
3476 | i915_gem_reset_fences(dev); |
3477 | ||
29105ccc CW |
3478 | /* Hack! Don't let anybody do execbuf while we don't control the chip. |
3479 | * We need to replace this with a semaphore, or something. | |
3480 | * And not confound mm.suspended! | |
3481 | */ | |
3482 | dev_priv->mm.suspended = 1; | |
bc0c7f14 | 3483 | del_timer_sync(&dev_priv->hangcheck_timer); |
29105ccc CW |
3484 | |
3485 | i915_kernel_lost_context(dev); | |
6dbe2772 | 3486 | i915_gem_cleanup_ringbuffer(dev); |
29105ccc | 3487 | |
6dbe2772 KP |
3488 | mutex_unlock(&dev->struct_mutex); |
3489 | ||
29105ccc CW |
3490 | /* Cancel the retire work handler, which should be idle now. */ |
3491 | cancel_delayed_work_sync(&dev_priv->mm.retire_work); | |
3492 | ||
673a394b EA |
3493 | return 0; |
3494 | } | |
3495 | ||
8187a2b7 ZN |
3496 | int |
3497 | i915_gem_init_ringbuffer(struct drm_device *dev) | |
3498 | { | |
3499 | drm_i915_private_t *dev_priv = dev->dev_private; | |
3500 | int ret; | |
68f95ba9 | 3501 | |
5c1143bb | 3502 | ret = intel_init_render_ring_buffer(dev); |
68f95ba9 | 3503 | if (ret) |
b6913e4b | 3504 | return ret; |
68f95ba9 CW |
3505 | |
3506 | if (HAS_BSD(dev)) { | |
5c1143bb | 3507 | ret = intel_init_bsd_ring_buffer(dev); |
68f95ba9 CW |
3508 | if (ret) |
3509 | goto cleanup_render_ring; | |
d1b851fc | 3510 | } |
68f95ba9 | 3511 | |
549f7365 CW |
3512 | if (HAS_BLT(dev)) { |
3513 | ret = intel_init_blt_ring_buffer(dev); | |
3514 | if (ret) | |
3515 | goto cleanup_bsd_ring; | |
3516 | } | |
3517 | ||
6f392d54 CW |
3518 | dev_priv->next_seqno = 1; |
3519 | ||
68f95ba9 CW |
3520 | return 0; |
3521 | ||
549f7365 | 3522 | cleanup_bsd_ring: |
78501eac | 3523 | intel_cleanup_ring_buffer(&dev_priv->bsd_ring); |
68f95ba9 | 3524 | cleanup_render_ring: |
78501eac | 3525 | intel_cleanup_ring_buffer(&dev_priv->render_ring); |
8187a2b7 ZN |
3526 | return ret; |
3527 | } | |
3528 | ||
3529 | void | |
3530 | i915_gem_cleanup_ringbuffer(struct drm_device *dev) | |
3531 | { | |
3532 | drm_i915_private_t *dev_priv = dev->dev_private; | |
3533 | ||
78501eac CW |
3534 | intel_cleanup_ring_buffer(&dev_priv->render_ring); |
3535 | intel_cleanup_ring_buffer(&dev_priv->bsd_ring); | |
3536 | intel_cleanup_ring_buffer(&dev_priv->blt_ring); | |
8187a2b7 ZN |
3537 | } |
3538 | ||
673a394b EA |
3539 | int |
3540 | i915_gem_entervt_ioctl(struct drm_device *dev, void *data, | |
3541 | struct drm_file *file_priv) | |
3542 | { | |
3543 | drm_i915_private_t *dev_priv = dev->dev_private; | |
3544 | int ret; | |
3545 | ||
79e53945 JB |
3546 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
3547 | return 0; | |
3548 | ||
ba1234d1 | 3549 | if (atomic_read(&dev_priv->mm.wedged)) { |
673a394b | 3550 | DRM_ERROR("Reenabling wedged hardware, good luck\n"); |
ba1234d1 | 3551 | atomic_set(&dev_priv->mm.wedged, 0); |
673a394b EA |
3552 | } |
3553 | ||
673a394b | 3554 | mutex_lock(&dev->struct_mutex); |
9bb2d6f9 EA |
3555 | dev_priv->mm.suspended = 0; |
3556 | ||
3557 | ret = i915_gem_init_ringbuffer(dev); | |
d816f6ac WF |
3558 | if (ret != 0) { |
3559 | mutex_unlock(&dev->struct_mutex); | |
9bb2d6f9 | 3560 | return ret; |
d816f6ac | 3561 | } |
9bb2d6f9 | 3562 | |
69dc4987 | 3563 | BUG_ON(!list_empty(&dev_priv->mm.active_list)); |
852835f3 | 3564 | BUG_ON(!list_empty(&dev_priv->render_ring.active_list)); |
87acb0a5 | 3565 | BUG_ON(!list_empty(&dev_priv->bsd_ring.active_list)); |
549f7365 | 3566 | BUG_ON(!list_empty(&dev_priv->blt_ring.active_list)); |
673a394b EA |
3567 | BUG_ON(!list_empty(&dev_priv->mm.flushing_list)); |
3568 | BUG_ON(!list_empty(&dev_priv->mm.inactive_list)); | |
852835f3 | 3569 | BUG_ON(!list_empty(&dev_priv->render_ring.request_list)); |
87acb0a5 | 3570 | BUG_ON(!list_empty(&dev_priv->bsd_ring.request_list)); |
549f7365 | 3571 | BUG_ON(!list_empty(&dev_priv->blt_ring.request_list)); |
673a394b | 3572 | mutex_unlock(&dev->struct_mutex); |
dbb19d30 | 3573 | |
5f35308b CW |
3574 | ret = drm_irq_install(dev); |
3575 | if (ret) | |
3576 | goto cleanup_ringbuffer; | |
dbb19d30 | 3577 | |
673a394b | 3578 | return 0; |
5f35308b CW |
3579 | |
3580 | cleanup_ringbuffer: | |
3581 | mutex_lock(&dev->struct_mutex); | |
3582 | i915_gem_cleanup_ringbuffer(dev); | |
3583 | dev_priv->mm.suspended = 1; | |
3584 | mutex_unlock(&dev->struct_mutex); | |
3585 | ||
3586 | return ret; | |
673a394b EA |
3587 | } |
3588 | ||
3589 | int | |
3590 | i915_gem_leavevt_ioctl(struct drm_device *dev, void *data, | |
3591 | struct drm_file *file_priv) | |
3592 | { | |
79e53945 JB |
3593 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
3594 | return 0; | |
3595 | ||
dbb19d30 | 3596 | drm_irq_uninstall(dev); |
e6890f6f | 3597 | return i915_gem_idle(dev); |
673a394b EA |
3598 | } |
3599 | ||
3600 | void | |
3601 | i915_gem_lastclose(struct drm_device *dev) | |
3602 | { | |
3603 | int ret; | |
673a394b | 3604 | |
e806b495 EA |
3605 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
3606 | return; | |
3607 | ||
6dbe2772 KP |
3608 | ret = i915_gem_idle(dev); |
3609 | if (ret) | |
3610 | DRM_ERROR("failed to idle hardware: %d\n", ret); | |
673a394b EA |
3611 | } |
3612 | ||
64193406 CW |
3613 | static void |
3614 | init_ring_lists(struct intel_ring_buffer *ring) | |
3615 | { | |
3616 | INIT_LIST_HEAD(&ring->active_list); | |
3617 | INIT_LIST_HEAD(&ring->request_list); | |
3618 | INIT_LIST_HEAD(&ring->gpu_write_list); | |
3619 | } | |
3620 | ||
673a394b EA |
3621 | void |
3622 | i915_gem_load(struct drm_device *dev) | |
3623 | { | |
b5aa8a0f | 3624 | int i; |
673a394b EA |
3625 | drm_i915_private_t *dev_priv = dev->dev_private; |
3626 | ||
69dc4987 | 3627 | INIT_LIST_HEAD(&dev_priv->mm.active_list); |
673a394b EA |
3628 | INIT_LIST_HEAD(&dev_priv->mm.flushing_list); |
3629 | INIT_LIST_HEAD(&dev_priv->mm.inactive_list); | |
f13d3f73 | 3630 | INIT_LIST_HEAD(&dev_priv->mm.pinned_list); |
a09ba7fa | 3631 | INIT_LIST_HEAD(&dev_priv->mm.fence_list); |
be72615b | 3632 | INIT_LIST_HEAD(&dev_priv->mm.deferred_free_list); |
93a37f20 | 3633 | INIT_LIST_HEAD(&dev_priv->mm.gtt_list); |
64193406 CW |
3634 | init_ring_lists(&dev_priv->render_ring); |
3635 | init_ring_lists(&dev_priv->bsd_ring); | |
3636 | init_ring_lists(&dev_priv->blt_ring); | |
007cc8ac DV |
3637 | for (i = 0; i < 16; i++) |
3638 | INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list); | |
673a394b EA |
3639 | INIT_DELAYED_WORK(&dev_priv->mm.retire_work, |
3640 | i915_gem_retire_work_handler); | |
30dbf0c0 | 3641 | init_completion(&dev_priv->error_completion); |
31169714 | 3642 | |
94400120 DA |
3643 | /* On GEN3 we really need to make sure the ARB C3 LP bit is set */ |
3644 | if (IS_GEN3(dev)) { | |
3645 | u32 tmp = I915_READ(MI_ARB_STATE); | |
3646 | if (!(tmp & MI_ARB_C3_LP_WRITE_ENABLE)) { | |
3647 | /* arb state is a masked write, so set bit + bit in mask */ | |
3648 | tmp = MI_ARB_C3_LP_WRITE_ENABLE | (MI_ARB_C3_LP_WRITE_ENABLE << MI_ARB_MASK_SHIFT); | |
3649 | I915_WRITE(MI_ARB_STATE, tmp); | |
3650 | } | |
3651 | } | |
3652 | ||
de151cf6 | 3653 | /* Old X drivers will take 0-2 for front, back, depth buffers */ |
b397c836 EA |
3654 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) |
3655 | dev_priv->fence_reg_start = 3; | |
de151cf6 | 3656 | |
a6c45cf0 | 3657 | if (INTEL_INFO(dev)->gen >= 4 || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) |
de151cf6 JB |
3658 | dev_priv->num_fence_regs = 16; |
3659 | else | |
3660 | dev_priv->num_fence_regs = 8; | |
3661 | ||
b5aa8a0f | 3662 | /* Initialize fence registers to zero */ |
a6c45cf0 CW |
3663 | switch (INTEL_INFO(dev)->gen) { |
3664 | case 6: | |
3665 | for (i = 0; i < 16; i++) | |
3666 | I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + (i * 8), 0); | |
3667 | break; | |
3668 | case 5: | |
3669 | case 4: | |
b5aa8a0f GH |
3670 | for (i = 0; i < 16; i++) |
3671 | I915_WRITE64(FENCE_REG_965_0 + (i * 8), 0); | |
a6c45cf0 CW |
3672 | break; |
3673 | case 3: | |
b5aa8a0f GH |
3674 | if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) |
3675 | for (i = 0; i < 8; i++) | |
3676 | I915_WRITE(FENCE_REG_945_8 + (i * 4), 0); | |
a6c45cf0 CW |
3677 | case 2: |
3678 | for (i = 0; i < 8; i++) | |
3679 | I915_WRITE(FENCE_REG_830_0 + (i * 4), 0); | |
3680 | break; | |
b5aa8a0f | 3681 | } |
673a394b | 3682 | i915_gem_detect_bit_6_swizzle(dev); |
6b95a207 | 3683 | init_waitqueue_head(&dev_priv->pending_flip_queue); |
17250b71 CW |
3684 | |
3685 | dev_priv->mm.inactive_shrinker.shrink = i915_gem_inactive_shrink; | |
3686 | dev_priv->mm.inactive_shrinker.seeks = DEFAULT_SEEKS; | |
3687 | register_shrinker(&dev_priv->mm.inactive_shrinker); | |
673a394b | 3688 | } |
71acb5eb DA |
3689 | |
3690 | /* | |
3691 | * Create a physically contiguous memory object for this object | |
3692 | * e.g. for cursor + overlay regs | |
3693 | */ | |
995b6762 CW |
3694 | static int i915_gem_init_phys_object(struct drm_device *dev, |
3695 | int id, int size, int align) | |
71acb5eb DA |
3696 | { |
3697 | drm_i915_private_t *dev_priv = dev->dev_private; | |
3698 | struct drm_i915_gem_phys_object *phys_obj; | |
3699 | int ret; | |
3700 | ||
3701 | if (dev_priv->mm.phys_objs[id - 1] || !size) | |
3702 | return 0; | |
3703 | ||
9a298b2a | 3704 | phys_obj = kzalloc(sizeof(struct drm_i915_gem_phys_object), GFP_KERNEL); |
71acb5eb DA |
3705 | if (!phys_obj) |
3706 | return -ENOMEM; | |
3707 | ||
3708 | phys_obj->id = id; | |
3709 | ||
6eeefaf3 | 3710 | phys_obj->handle = drm_pci_alloc(dev, size, align); |
71acb5eb DA |
3711 | if (!phys_obj->handle) { |
3712 | ret = -ENOMEM; | |
3713 | goto kfree_obj; | |
3714 | } | |
3715 | #ifdef CONFIG_X86 | |
3716 | set_memory_wc((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE); | |
3717 | #endif | |
3718 | ||
3719 | dev_priv->mm.phys_objs[id - 1] = phys_obj; | |
3720 | ||
3721 | return 0; | |
3722 | kfree_obj: | |
9a298b2a | 3723 | kfree(phys_obj); |
71acb5eb DA |
3724 | return ret; |
3725 | } | |
3726 | ||
995b6762 | 3727 | static void i915_gem_free_phys_object(struct drm_device *dev, int id) |
71acb5eb DA |
3728 | { |
3729 | drm_i915_private_t *dev_priv = dev->dev_private; | |
3730 | struct drm_i915_gem_phys_object *phys_obj; | |
3731 | ||
3732 | if (!dev_priv->mm.phys_objs[id - 1]) | |
3733 | return; | |
3734 | ||
3735 | phys_obj = dev_priv->mm.phys_objs[id - 1]; | |
3736 | if (phys_obj->cur_obj) { | |
3737 | i915_gem_detach_phys_object(dev, phys_obj->cur_obj); | |
3738 | } | |
3739 | ||
3740 | #ifdef CONFIG_X86 | |
3741 | set_memory_wb((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE); | |
3742 | #endif | |
3743 | drm_pci_free(dev, phys_obj->handle); | |
3744 | kfree(phys_obj); | |
3745 | dev_priv->mm.phys_objs[id - 1] = NULL; | |
3746 | } | |
3747 | ||
3748 | void i915_gem_free_all_phys_object(struct drm_device *dev) | |
3749 | { | |
3750 | int i; | |
3751 | ||
260883c8 | 3752 | for (i = I915_GEM_PHYS_CURSOR_0; i <= I915_MAX_PHYS_OBJECT; i++) |
71acb5eb DA |
3753 | i915_gem_free_phys_object(dev, i); |
3754 | } | |
3755 | ||
3756 | void i915_gem_detach_phys_object(struct drm_device *dev, | |
05394f39 | 3757 | struct drm_i915_gem_object *obj) |
71acb5eb | 3758 | { |
05394f39 | 3759 | struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping; |
e5281ccd | 3760 | char *vaddr; |
71acb5eb | 3761 | int i; |
71acb5eb DA |
3762 | int page_count; |
3763 | ||
05394f39 | 3764 | if (!obj->phys_obj) |
71acb5eb | 3765 | return; |
05394f39 | 3766 | vaddr = obj->phys_obj->handle->vaddr; |
71acb5eb | 3767 | |
05394f39 | 3768 | page_count = obj->base.size / PAGE_SIZE; |
71acb5eb | 3769 | for (i = 0; i < page_count; i++) { |
e5281ccd CW |
3770 | struct page *page = read_cache_page_gfp(mapping, i, |
3771 | GFP_HIGHUSER | __GFP_RECLAIMABLE); | |
3772 | if (!IS_ERR(page)) { | |
3773 | char *dst = kmap_atomic(page); | |
3774 | memcpy(dst, vaddr + i*PAGE_SIZE, PAGE_SIZE); | |
3775 | kunmap_atomic(dst); | |
3776 | ||
3777 | drm_clflush_pages(&page, 1); | |
3778 | ||
3779 | set_page_dirty(page); | |
3780 | mark_page_accessed(page); | |
3781 | page_cache_release(page); | |
3782 | } | |
71acb5eb | 3783 | } |
40ce6575 | 3784 | intel_gtt_chipset_flush(); |
d78b47b9 | 3785 | |
05394f39 CW |
3786 | obj->phys_obj->cur_obj = NULL; |
3787 | obj->phys_obj = NULL; | |
71acb5eb DA |
3788 | } |
3789 | ||
3790 | int | |
3791 | i915_gem_attach_phys_object(struct drm_device *dev, | |
05394f39 | 3792 | struct drm_i915_gem_object *obj, |
6eeefaf3 CW |
3793 | int id, |
3794 | int align) | |
71acb5eb | 3795 | { |
05394f39 | 3796 | struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping; |
71acb5eb | 3797 | drm_i915_private_t *dev_priv = dev->dev_private; |
71acb5eb DA |
3798 | int ret = 0; |
3799 | int page_count; | |
3800 | int i; | |
3801 | ||
3802 | if (id > I915_MAX_PHYS_OBJECT) | |
3803 | return -EINVAL; | |
3804 | ||
05394f39 CW |
3805 | if (obj->phys_obj) { |
3806 | if (obj->phys_obj->id == id) | |
71acb5eb DA |
3807 | return 0; |
3808 | i915_gem_detach_phys_object(dev, obj); | |
3809 | } | |
3810 | ||
71acb5eb DA |
3811 | /* create a new object */ |
3812 | if (!dev_priv->mm.phys_objs[id - 1]) { | |
3813 | ret = i915_gem_init_phys_object(dev, id, | |
05394f39 | 3814 | obj->base.size, align); |
71acb5eb | 3815 | if (ret) { |
05394f39 CW |
3816 | DRM_ERROR("failed to init phys object %d size: %zu\n", |
3817 | id, obj->base.size); | |
e5281ccd | 3818 | return ret; |
71acb5eb DA |
3819 | } |
3820 | } | |
3821 | ||
3822 | /* bind to the object */ | |
05394f39 CW |
3823 | obj->phys_obj = dev_priv->mm.phys_objs[id - 1]; |
3824 | obj->phys_obj->cur_obj = obj; | |
71acb5eb | 3825 | |
05394f39 | 3826 | page_count = obj->base.size / PAGE_SIZE; |
71acb5eb DA |
3827 | |
3828 | for (i = 0; i < page_count; i++) { | |
e5281ccd CW |
3829 | struct page *page; |
3830 | char *dst, *src; | |
3831 | ||
3832 | page = read_cache_page_gfp(mapping, i, | |
3833 | GFP_HIGHUSER | __GFP_RECLAIMABLE); | |
3834 | if (IS_ERR(page)) | |
3835 | return PTR_ERR(page); | |
71acb5eb | 3836 | |
ff75b9bc | 3837 | src = kmap_atomic(page); |
05394f39 | 3838 | dst = obj->phys_obj->handle->vaddr + (i * PAGE_SIZE); |
71acb5eb | 3839 | memcpy(dst, src, PAGE_SIZE); |
3e4d3af5 | 3840 | kunmap_atomic(src); |
71acb5eb | 3841 | |
e5281ccd CW |
3842 | mark_page_accessed(page); |
3843 | page_cache_release(page); | |
3844 | } | |
d78b47b9 | 3845 | |
71acb5eb | 3846 | return 0; |
71acb5eb DA |
3847 | } |
3848 | ||
3849 | static int | |
05394f39 CW |
3850 | i915_gem_phys_pwrite(struct drm_device *dev, |
3851 | struct drm_i915_gem_object *obj, | |
71acb5eb DA |
3852 | struct drm_i915_gem_pwrite *args, |
3853 | struct drm_file *file_priv) | |
3854 | { | |
05394f39 | 3855 | void *vaddr = obj->phys_obj->handle->vaddr + args->offset; |
b47b30cc | 3856 | char __user *user_data = (char __user *) (uintptr_t) args->data_ptr; |
71acb5eb | 3857 | |
b47b30cc CW |
3858 | if (__copy_from_user_inatomic_nocache(vaddr, user_data, args->size)) { |
3859 | unsigned long unwritten; | |
3860 | ||
3861 | /* The physical object once assigned is fixed for the lifetime | |
3862 | * of the obj, so we can safely drop the lock and continue | |
3863 | * to access vaddr. | |
3864 | */ | |
3865 | mutex_unlock(&dev->struct_mutex); | |
3866 | unwritten = copy_from_user(vaddr, user_data, args->size); | |
3867 | mutex_lock(&dev->struct_mutex); | |
3868 | if (unwritten) | |
3869 | return -EFAULT; | |
3870 | } | |
71acb5eb | 3871 | |
40ce6575 | 3872 | intel_gtt_chipset_flush(); |
71acb5eb DA |
3873 | return 0; |
3874 | } | |
b962442e | 3875 | |
f787a5f5 | 3876 | void i915_gem_release(struct drm_device *dev, struct drm_file *file) |
b962442e | 3877 | { |
f787a5f5 | 3878 | struct drm_i915_file_private *file_priv = file->driver_priv; |
b962442e EA |
3879 | |
3880 | /* Clean up our request list when the client is going away, so that | |
3881 | * later retire_requests won't dereference our soon-to-be-gone | |
3882 | * file_priv. | |
3883 | */ | |
1c25595f | 3884 | spin_lock(&file_priv->mm.lock); |
f787a5f5 CW |
3885 | while (!list_empty(&file_priv->mm.request_list)) { |
3886 | struct drm_i915_gem_request *request; | |
3887 | ||
3888 | request = list_first_entry(&file_priv->mm.request_list, | |
3889 | struct drm_i915_gem_request, | |
3890 | client_list); | |
3891 | list_del(&request->client_list); | |
3892 | request->file_priv = NULL; | |
3893 | } | |
1c25595f | 3894 | spin_unlock(&file_priv->mm.lock); |
b962442e | 3895 | } |
31169714 | 3896 | |
1637ef41 CW |
3897 | static int |
3898 | i915_gpu_is_active(struct drm_device *dev) | |
3899 | { | |
3900 | drm_i915_private_t *dev_priv = dev->dev_private; | |
3901 | int lists_empty; | |
3902 | ||
1637ef41 | 3903 | lists_empty = list_empty(&dev_priv->mm.flushing_list) && |
17250b71 | 3904 | list_empty(&dev_priv->mm.active_list); |
1637ef41 CW |
3905 | |
3906 | return !lists_empty; | |
3907 | } | |
3908 | ||
31169714 | 3909 | static int |
17250b71 CW |
3910 | i915_gem_inactive_shrink(struct shrinker *shrinker, |
3911 | int nr_to_scan, | |
3912 | gfp_t gfp_mask) | |
31169714 | 3913 | { |
17250b71 CW |
3914 | struct drm_i915_private *dev_priv = |
3915 | container_of(shrinker, | |
3916 | struct drm_i915_private, | |
3917 | mm.inactive_shrinker); | |
3918 | struct drm_device *dev = dev_priv->dev; | |
3919 | struct drm_i915_gem_object *obj, *next; | |
3920 | int cnt; | |
3921 | ||
3922 | if (!mutex_trylock(&dev->struct_mutex)) | |
bbe2e11a | 3923 | return 0; |
31169714 CW |
3924 | |
3925 | /* "fast-path" to count number of available objects */ | |
3926 | if (nr_to_scan == 0) { | |
17250b71 CW |
3927 | cnt = 0; |
3928 | list_for_each_entry(obj, | |
3929 | &dev_priv->mm.inactive_list, | |
3930 | mm_list) | |
3931 | cnt++; | |
3932 | mutex_unlock(&dev->struct_mutex); | |
3933 | return cnt / 100 * sysctl_vfs_cache_pressure; | |
31169714 CW |
3934 | } |
3935 | ||
1637ef41 | 3936 | rescan: |
31169714 | 3937 | /* first scan for clean buffers */ |
17250b71 | 3938 | i915_gem_retire_requests(dev); |
31169714 | 3939 | |
17250b71 CW |
3940 | list_for_each_entry_safe(obj, next, |
3941 | &dev_priv->mm.inactive_list, | |
3942 | mm_list) { | |
3943 | if (i915_gem_object_is_purgeable(obj)) { | |
2021746e CW |
3944 | if (i915_gem_object_unbind(obj) == 0 && |
3945 | --nr_to_scan == 0) | |
17250b71 | 3946 | break; |
31169714 | 3947 | } |
31169714 CW |
3948 | } |
3949 | ||
3950 | /* second pass, evict/count anything still on the inactive list */ | |
17250b71 CW |
3951 | cnt = 0; |
3952 | list_for_each_entry_safe(obj, next, | |
3953 | &dev_priv->mm.inactive_list, | |
3954 | mm_list) { | |
2021746e CW |
3955 | if (nr_to_scan && |
3956 | i915_gem_object_unbind(obj) == 0) | |
17250b71 | 3957 | nr_to_scan--; |
2021746e | 3958 | else |
17250b71 CW |
3959 | cnt++; |
3960 | } | |
3961 | ||
3962 | if (nr_to_scan && i915_gpu_is_active(dev)) { | |
1637ef41 CW |
3963 | /* |
3964 | * We are desperate for pages, so as a last resort, wait | |
3965 | * for the GPU to finish and discard whatever we can. | |
3966 | * This has a dramatic impact to reduce the number of | |
3967 | * OOM-killer events whilst running the GPU aggressively. | |
3968 | */ | |
17250b71 | 3969 | if (i915_gpu_idle(dev) == 0) |
1637ef41 CW |
3970 | goto rescan; |
3971 | } | |
17250b71 CW |
3972 | mutex_unlock(&dev->struct_mutex); |
3973 | return cnt / 100 * sysctl_vfs_cache_pressure; | |
31169714 | 3974 | } |