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673a394b EA |
1 | /* |
2 | * Copyright © 2008 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | * | |
26 | */ | |
27 | ||
28 | #include "drmP.h" | |
29 | #include "drm.h" | |
30 | #include "i915_drm.h" | |
31 | #include "i915_drv.h" | |
1c5d22f7 | 32 | #include "i915_trace.h" |
652c393a | 33 | #include "intel_drv.h" |
673a394b | 34 | #include <linux/swap.h> |
79e53945 | 35 | #include <linux/pci.h> |
673a394b | 36 | |
28dfe52a EA |
37 | #define I915_GEM_GPU_DOMAINS (~(I915_GEM_DOMAIN_CPU | I915_GEM_DOMAIN_GTT)) |
38 | ||
e47c68e9 EA |
39 | static void i915_gem_object_flush_gpu_write_domain(struct drm_gem_object *obj); |
40 | static void i915_gem_object_flush_gtt_write_domain(struct drm_gem_object *obj); | |
41 | static void i915_gem_object_flush_cpu_write_domain(struct drm_gem_object *obj); | |
e47c68e9 EA |
42 | static int i915_gem_object_set_to_cpu_domain(struct drm_gem_object *obj, |
43 | int write); | |
44 | static int i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object *obj, | |
45 | uint64_t offset, | |
46 | uint64_t size); | |
47 | static void i915_gem_object_set_to_full_cpu_read_domain(struct drm_gem_object *obj); | |
673a394b | 48 | static int i915_gem_object_wait_rendering(struct drm_gem_object *obj); |
de151cf6 JB |
49 | static int i915_gem_object_bind_to_gtt(struct drm_gem_object *obj, |
50 | unsigned alignment); | |
de151cf6 | 51 | static void i915_gem_clear_fence_reg(struct drm_gem_object *obj); |
07f73f69 | 52 | static int i915_gem_evict_something(struct drm_device *dev, int min_size); |
ab5ee576 | 53 | static int i915_gem_evict_from_inactive_list(struct drm_device *dev); |
71acb5eb DA |
54 | static int i915_gem_phys_pwrite(struct drm_device *dev, struct drm_gem_object *obj, |
55 | struct drm_i915_gem_pwrite *args, | |
56 | struct drm_file *file_priv); | |
673a394b | 57 | |
31169714 CW |
58 | static LIST_HEAD(shrink_list); |
59 | static DEFINE_SPINLOCK(shrink_list_lock); | |
60 | ||
79e53945 JB |
61 | int i915_gem_do_init(struct drm_device *dev, unsigned long start, |
62 | unsigned long end) | |
673a394b EA |
63 | { |
64 | drm_i915_private_t *dev_priv = dev->dev_private; | |
673a394b | 65 | |
79e53945 JB |
66 | if (start >= end || |
67 | (start & (PAGE_SIZE - 1)) != 0 || | |
68 | (end & (PAGE_SIZE - 1)) != 0) { | |
673a394b EA |
69 | return -EINVAL; |
70 | } | |
71 | ||
79e53945 JB |
72 | drm_mm_init(&dev_priv->mm.gtt_space, start, |
73 | end - start); | |
673a394b | 74 | |
79e53945 JB |
75 | dev->gtt_total = (uint32_t) (end - start); |
76 | ||
77 | return 0; | |
78 | } | |
673a394b | 79 | |
79e53945 JB |
80 | int |
81 | i915_gem_init_ioctl(struct drm_device *dev, void *data, | |
82 | struct drm_file *file_priv) | |
83 | { | |
84 | struct drm_i915_gem_init *args = data; | |
85 | int ret; | |
86 | ||
87 | mutex_lock(&dev->struct_mutex); | |
88 | ret = i915_gem_do_init(dev, args->gtt_start, args->gtt_end); | |
673a394b EA |
89 | mutex_unlock(&dev->struct_mutex); |
90 | ||
79e53945 | 91 | return ret; |
673a394b EA |
92 | } |
93 | ||
5a125c3c EA |
94 | int |
95 | i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data, | |
96 | struct drm_file *file_priv) | |
97 | { | |
5a125c3c | 98 | struct drm_i915_gem_get_aperture *args = data; |
5a125c3c EA |
99 | |
100 | if (!(dev->driver->driver_features & DRIVER_GEM)) | |
101 | return -ENODEV; | |
102 | ||
103 | args->aper_size = dev->gtt_total; | |
2678d9d6 KP |
104 | args->aper_available_size = (args->aper_size - |
105 | atomic_read(&dev->pin_memory)); | |
5a125c3c EA |
106 | |
107 | return 0; | |
108 | } | |
109 | ||
673a394b EA |
110 | |
111 | /** | |
112 | * Creates a new mm object and returns a handle to it. | |
113 | */ | |
114 | int | |
115 | i915_gem_create_ioctl(struct drm_device *dev, void *data, | |
116 | struct drm_file *file_priv) | |
117 | { | |
118 | struct drm_i915_gem_create *args = data; | |
119 | struct drm_gem_object *obj; | |
a1a2d1d3 PP |
120 | int ret; |
121 | u32 handle; | |
673a394b EA |
122 | |
123 | args->size = roundup(args->size, PAGE_SIZE); | |
124 | ||
125 | /* Allocate the new object */ | |
126 | obj = drm_gem_object_alloc(dev, args->size); | |
127 | if (obj == NULL) | |
128 | return -ENOMEM; | |
129 | ||
130 | ret = drm_gem_handle_create(file_priv, obj, &handle); | |
131 | mutex_lock(&dev->struct_mutex); | |
132 | drm_gem_object_handle_unreference(obj); | |
133 | mutex_unlock(&dev->struct_mutex); | |
134 | ||
135 | if (ret) | |
136 | return ret; | |
137 | ||
138 | args->handle = handle; | |
139 | ||
140 | return 0; | |
141 | } | |
142 | ||
eb01459f EA |
143 | static inline int |
144 | fast_shmem_read(struct page **pages, | |
145 | loff_t page_base, int page_offset, | |
146 | char __user *data, | |
147 | int length) | |
148 | { | |
149 | char __iomem *vaddr; | |
2bc43b5c | 150 | int unwritten; |
eb01459f EA |
151 | |
152 | vaddr = kmap_atomic(pages[page_base >> PAGE_SHIFT], KM_USER0); | |
153 | if (vaddr == NULL) | |
154 | return -ENOMEM; | |
2bc43b5c | 155 | unwritten = __copy_to_user_inatomic(data, vaddr + page_offset, length); |
eb01459f EA |
156 | kunmap_atomic(vaddr, KM_USER0); |
157 | ||
2bc43b5c FM |
158 | if (unwritten) |
159 | return -EFAULT; | |
160 | ||
161 | return 0; | |
eb01459f EA |
162 | } |
163 | ||
280b713b EA |
164 | static int i915_gem_object_needs_bit17_swizzle(struct drm_gem_object *obj) |
165 | { | |
166 | drm_i915_private_t *dev_priv = obj->dev->dev_private; | |
167 | struct drm_i915_gem_object *obj_priv = obj->driver_private; | |
168 | ||
169 | return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 && | |
170 | obj_priv->tiling_mode != I915_TILING_NONE; | |
171 | } | |
172 | ||
40123c1f EA |
173 | static inline int |
174 | slow_shmem_copy(struct page *dst_page, | |
175 | int dst_offset, | |
176 | struct page *src_page, | |
177 | int src_offset, | |
178 | int length) | |
179 | { | |
180 | char *dst_vaddr, *src_vaddr; | |
181 | ||
182 | dst_vaddr = kmap_atomic(dst_page, KM_USER0); | |
183 | if (dst_vaddr == NULL) | |
184 | return -ENOMEM; | |
185 | ||
186 | src_vaddr = kmap_atomic(src_page, KM_USER1); | |
187 | if (src_vaddr == NULL) { | |
188 | kunmap_atomic(dst_vaddr, KM_USER0); | |
189 | return -ENOMEM; | |
190 | } | |
191 | ||
192 | memcpy(dst_vaddr + dst_offset, src_vaddr + src_offset, length); | |
193 | ||
194 | kunmap_atomic(src_vaddr, KM_USER1); | |
195 | kunmap_atomic(dst_vaddr, KM_USER0); | |
196 | ||
197 | return 0; | |
198 | } | |
199 | ||
280b713b EA |
200 | static inline int |
201 | slow_shmem_bit17_copy(struct page *gpu_page, | |
202 | int gpu_offset, | |
203 | struct page *cpu_page, | |
204 | int cpu_offset, | |
205 | int length, | |
206 | int is_read) | |
207 | { | |
208 | char *gpu_vaddr, *cpu_vaddr; | |
209 | ||
210 | /* Use the unswizzled path if this page isn't affected. */ | |
211 | if ((page_to_phys(gpu_page) & (1 << 17)) == 0) { | |
212 | if (is_read) | |
213 | return slow_shmem_copy(cpu_page, cpu_offset, | |
214 | gpu_page, gpu_offset, length); | |
215 | else | |
216 | return slow_shmem_copy(gpu_page, gpu_offset, | |
217 | cpu_page, cpu_offset, length); | |
218 | } | |
219 | ||
220 | gpu_vaddr = kmap_atomic(gpu_page, KM_USER0); | |
221 | if (gpu_vaddr == NULL) | |
222 | return -ENOMEM; | |
223 | ||
224 | cpu_vaddr = kmap_atomic(cpu_page, KM_USER1); | |
225 | if (cpu_vaddr == NULL) { | |
226 | kunmap_atomic(gpu_vaddr, KM_USER0); | |
227 | return -ENOMEM; | |
228 | } | |
229 | ||
230 | /* Copy the data, XORing A6 with A17 (1). The user already knows he's | |
231 | * XORing with the other bits (A9 for Y, A9 and A10 for X) | |
232 | */ | |
233 | while (length > 0) { | |
234 | int cacheline_end = ALIGN(gpu_offset + 1, 64); | |
235 | int this_length = min(cacheline_end - gpu_offset, length); | |
236 | int swizzled_gpu_offset = gpu_offset ^ 64; | |
237 | ||
238 | if (is_read) { | |
239 | memcpy(cpu_vaddr + cpu_offset, | |
240 | gpu_vaddr + swizzled_gpu_offset, | |
241 | this_length); | |
242 | } else { | |
243 | memcpy(gpu_vaddr + swizzled_gpu_offset, | |
244 | cpu_vaddr + cpu_offset, | |
245 | this_length); | |
246 | } | |
247 | cpu_offset += this_length; | |
248 | gpu_offset += this_length; | |
249 | length -= this_length; | |
250 | } | |
251 | ||
252 | kunmap_atomic(cpu_vaddr, KM_USER1); | |
253 | kunmap_atomic(gpu_vaddr, KM_USER0); | |
254 | ||
255 | return 0; | |
256 | } | |
257 | ||
eb01459f EA |
258 | /** |
259 | * This is the fast shmem pread path, which attempts to copy_from_user directly | |
260 | * from the backing pages of the object to the user's address space. On a | |
261 | * fault, it fails so we can fall back to i915_gem_shmem_pwrite_slow(). | |
262 | */ | |
263 | static int | |
264 | i915_gem_shmem_pread_fast(struct drm_device *dev, struct drm_gem_object *obj, | |
265 | struct drm_i915_gem_pread *args, | |
266 | struct drm_file *file_priv) | |
267 | { | |
268 | struct drm_i915_gem_object *obj_priv = obj->driver_private; | |
269 | ssize_t remain; | |
270 | loff_t offset, page_base; | |
271 | char __user *user_data; | |
272 | int page_offset, page_length; | |
273 | int ret; | |
274 | ||
275 | user_data = (char __user *) (uintptr_t) args->data_ptr; | |
276 | remain = args->size; | |
277 | ||
278 | mutex_lock(&dev->struct_mutex); | |
279 | ||
280 | ret = i915_gem_object_get_pages(obj); | |
281 | if (ret != 0) | |
282 | goto fail_unlock; | |
283 | ||
284 | ret = i915_gem_object_set_cpu_read_domain_range(obj, args->offset, | |
285 | args->size); | |
286 | if (ret != 0) | |
287 | goto fail_put_pages; | |
288 | ||
289 | obj_priv = obj->driver_private; | |
290 | offset = args->offset; | |
291 | ||
292 | while (remain > 0) { | |
293 | /* Operation in this page | |
294 | * | |
295 | * page_base = page offset within aperture | |
296 | * page_offset = offset within page | |
297 | * page_length = bytes to copy for this page | |
298 | */ | |
299 | page_base = (offset & ~(PAGE_SIZE-1)); | |
300 | page_offset = offset & (PAGE_SIZE-1); | |
301 | page_length = remain; | |
302 | if ((page_offset + remain) > PAGE_SIZE) | |
303 | page_length = PAGE_SIZE - page_offset; | |
304 | ||
305 | ret = fast_shmem_read(obj_priv->pages, | |
306 | page_base, page_offset, | |
307 | user_data, page_length); | |
308 | if (ret) | |
309 | goto fail_put_pages; | |
310 | ||
311 | remain -= page_length; | |
312 | user_data += page_length; | |
313 | offset += page_length; | |
314 | } | |
315 | ||
316 | fail_put_pages: | |
317 | i915_gem_object_put_pages(obj); | |
318 | fail_unlock: | |
319 | mutex_unlock(&dev->struct_mutex); | |
320 | ||
321 | return ret; | |
322 | } | |
323 | ||
07f73f69 CW |
324 | static inline gfp_t |
325 | i915_gem_object_get_page_gfp_mask (struct drm_gem_object *obj) | |
326 | { | |
327 | return mapping_gfp_mask(obj->filp->f_path.dentry->d_inode->i_mapping); | |
328 | } | |
329 | ||
330 | static inline void | |
331 | i915_gem_object_set_page_gfp_mask (struct drm_gem_object *obj, gfp_t gfp) | |
332 | { | |
333 | mapping_set_gfp_mask(obj->filp->f_path.dentry->d_inode->i_mapping, gfp); | |
334 | } | |
335 | ||
336 | static int | |
337 | i915_gem_object_get_pages_or_evict(struct drm_gem_object *obj) | |
338 | { | |
339 | int ret; | |
340 | ||
341 | ret = i915_gem_object_get_pages(obj); | |
342 | ||
343 | /* If we've insufficient memory to map in the pages, attempt | |
344 | * to make some space by throwing out some old buffers. | |
345 | */ | |
346 | if (ret == -ENOMEM) { | |
347 | struct drm_device *dev = obj->dev; | |
348 | gfp_t gfp; | |
349 | ||
350 | ret = i915_gem_evict_something(dev, obj->size); | |
351 | if (ret) | |
352 | return ret; | |
353 | ||
354 | gfp = i915_gem_object_get_page_gfp_mask(obj); | |
355 | i915_gem_object_set_page_gfp_mask(obj, gfp & ~__GFP_NORETRY); | |
356 | ret = i915_gem_object_get_pages(obj); | |
357 | i915_gem_object_set_page_gfp_mask (obj, gfp); | |
358 | } | |
359 | ||
360 | return ret; | |
361 | } | |
362 | ||
eb01459f EA |
363 | /** |
364 | * This is the fallback shmem pread path, which allocates temporary storage | |
365 | * in kernel space to copy_to_user into outside of the struct_mutex, so we | |
366 | * can copy out of the object's backing pages while holding the struct mutex | |
367 | * and not take page faults. | |
368 | */ | |
369 | static int | |
370 | i915_gem_shmem_pread_slow(struct drm_device *dev, struct drm_gem_object *obj, | |
371 | struct drm_i915_gem_pread *args, | |
372 | struct drm_file *file_priv) | |
373 | { | |
374 | struct drm_i915_gem_object *obj_priv = obj->driver_private; | |
375 | struct mm_struct *mm = current->mm; | |
376 | struct page **user_pages; | |
377 | ssize_t remain; | |
378 | loff_t offset, pinned_pages, i; | |
379 | loff_t first_data_page, last_data_page, num_pages; | |
380 | int shmem_page_index, shmem_page_offset; | |
381 | int data_page_index, data_page_offset; | |
382 | int page_length; | |
383 | int ret; | |
384 | uint64_t data_ptr = args->data_ptr; | |
280b713b | 385 | int do_bit17_swizzling; |
eb01459f EA |
386 | |
387 | remain = args->size; | |
388 | ||
389 | /* Pin the user pages containing the data. We can't fault while | |
390 | * holding the struct mutex, yet we want to hold it while | |
391 | * dereferencing the user data. | |
392 | */ | |
393 | first_data_page = data_ptr / PAGE_SIZE; | |
394 | last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE; | |
395 | num_pages = last_data_page - first_data_page + 1; | |
396 | ||
8e7d2b2c | 397 | user_pages = drm_calloc_large(num_pages, sizeof(struct page *)); |
eb01459f EA |
398 | if (user_pages == NULL) |
399 | return -ENOMEM; | |
400 | ||
401 | down_read(&mm->mmap_sem); | |
402 | pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr, | |
e5e9ecde | 403 | num_pages, 1, 0, user_pages, NULL); |
eb01459f EA |
404 | up_read(&mm->mmap_sem); |
405 | if (pinned_pages < num_pages) { | |
406 | ret = -EFAULT; | |
407 | goto fail_put_user_pages; | |
408 | } | |
409 | ||
280b713b EA |
410 | do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj); |
411 | ||
eb01459f EA |
412 | mutex_lock(&dev->struct_mutex); |
413 | ||
07f73f69 CW |
414 | ret = i915_gem_object_get_pages_or_evict(obj); |
415 | if (ret) | |
eb01459f EA |
416 | goto fail_unlock; |
417 | ||
418 | ret = i915_gem_object_set_cpu_read_domain_range(obj, args->offset, | |
419 | args->size); | |
420 | if (ret != 0) | |
421 | goto fail_put_pages; | |
422 | ||
423 | obj_priv = obj->driver_private; | |
424 | offset = args->offset; | |
425 | ||
426 | while (remain > 0) { | |
427 | /* Operation in this page | |
428 | * | |
429 | * shmem_page_index = page number within shmem file | |
430 | * shmem_page_offset = offset within page in shmem file | |
431 | * data_page_index = page number in get_user_pages return | |
432 | * data_page_offset = offset with data_page_index page. | |
433 | * page_length = bytes to copy for this page | |
434 | */ | |
435 | shmem_page_index = offset / PAGE_SIZE; | |
436 | shmem_page_offset = offset & ~PAGE_MASK; | |
437 | data_page_index = data_ptr / PAGE_SIZE - first_data_page; | |
438 | data_page_offset = data_ptr & ~PAGE_MASK; | |
439 | ||
440 | page_length = remain; | |
441 | if ((shmem_page_offset + page_length) > PAGE_SIZE) | |
442 | page_length = PAGE_SIZE - shmem_page_offset; | |
443 | if ((data_page_offset + page_length) > PAGE_SIZE) | |
444 | page_length = PAGE_SIZE - data_page_offset; | |
445 | ||
280b713b EA |
446 | if (do_bit17_swizzling) { |
447 | ret = slow_shmem_bit17_copy(obj_priv->pages[shmem_page_index], | |
448 | shmem_page_offset, | |
449 | user_pages[data_page_index], | |
450 | data_page_offset, | |
451 | page_length, | |
452 | 1); | |
453 | } else { | |
454 | ret = slow_shmem_copy(user_pages[data_page_index], | |
455 | data_page_offset, | |
456 | obj_priv->pages[shmem_page_index], | |
457 | shmem_page_offset, | |
458 | page_length); | |
459 | } | |
eb01459f EA |
460 | if (ret) |
461 | goto fail_put_pages; | |
462 | ||
463 | remain -= page_length; | |
464 | data_ptr += page_length; | |
465 | offset += page_length; | |
466 | } | |
467 | ||
468 | fail_put_pages: | |
469 | i915_gem_object_put_pages(obj); | |
470 | fail_unlock: | |
471 | mutex_unlock(&dev->struct_mutex); | |
472 | fail_put_user_pages: | |
473 | for (i = 0; i < pinned_pages; i++) { | |
474 | SetPageDirty(user_pages[i]); | |
475 | page_cache_release(user_pages[i]); | |
476 | } | |
8e7d2b2c | 477 | drm_free_large(user_pages); |
eb01459f EA |
478 | |
479 | return ret; | |
480 | } | |
481 | ||
673a394b EA |
482 | /** |
483 | * Reads data from the object referenced by handle. | |
484 | * | |
485 | * On error, the contents of *data are undefined. | |
486 | */ | |
487 | int | |
488 | i915_gem_pread_ioctl(struct drm_device *dev, void *data, | |
489 | struct drm_file *file_priv) | |
490 | { | |
491 | struct drm_i915_gem_pread *args = data; | |
492 | struct drm_gem_object *obj; | |
493 | struct drm_i915_gem_object *obj_priv; | |
673a394b EA |
494 | int ret; |
495 | ||
496 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); | |
497 | if (obj == NULL) | |
498 | return -EBADF; | |
499 | obj_priv = obj->driver_private; | |
500 | ||
501 | /* Bounds check source. | |
502 | * | |
503 | * XXX: This could use review for overflow issues... | |
504 | */ | |
505 | if (args->offset > obj->size || args->size > obj->size || | |
506 | args->offset + args->size > obj->size) { | |
507 | drm_gem_object_unreference(obj); | |
508 | return -EINVAL; | |
509 | } | |
510 | ||
280b713b | 511 | if (i915_gem_object_needs_bit17_swizzle(obj)) { |
eb01459f | 512 | ret = i915_gem_shmem_pread_slow(dev, obj, args, file_priv); |
280b713b EA |
513 | } else { |
514 | ret = i915_gem_shmem_pread_fast(dev, obj, args, file_priv); | |
515 | if (ret != 0) | |
516 | ret = i915_gem_shmem_pread_slow(dev, obj, args, | |
517 | file_priv); | |
518 | } | |
673a394b EA |
519 | |
520 | drm_gem_object_unreference(obj); | |
673a394b | 521 | |
eb01459f | 522 | return ret; |
673a394b EA |
523 | } |
524 | ||
0839ccb8 KP |
525 | /* This is the fast write path which cannot handle |
526 | * page faults in the source data | |
9b7530cc | 527 | */ |
0839ccb8 KP |
528 | |
529 | static inline int | |
530 | fast_user_write(struct io_mapping *mapping, | |
531 | loff_t page_base, int page_offset, | |
532 | char __user *user_data, | |
533 | int length) | |
9b7530cc | 534 | { |
9b7530cc | 535 | char *vaddr_atomic; |
0839ccb8 | 536 | unsigned long unwritten; |
9b7530cc | 537 | |
0839ccb8 KP |
538 | vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base); |
539 | unwritten = __copy_from_user_inatomic_nocache(vaddr_atomic + page_offset, | |
540 | user_data, length); | |
541 | io_mapping_unmap_atomic(vaddr_atomic); | |
542 | if (unwritten) | |
543 | return -EFAULT; | |
544 | return 0; | |
545 | } | |
546 | ||
547 | /* Here's the write path which can sleep for | |
548 | * page faults | |
549 | */ | |
550 | ||
551 | static inline int | |
3de09aa3 EA |
552 | slow_kernel_write(struct io_mapping *mapping, |
553 | loff_t gtt_base, int gtt_offset, | |
554 | struct page *user_page, int user_offset, | |
555 | int length) | |
0839ccb8 | 556 | { |
3de09aa3 | 557 | char *src_vaddr, *dst_vaddr; |
0839ccb8 KP |
558 | unsigned long unwritten; |
559 | ||
3de09aa3 EA |
560 | dst_vaddr = io_mapping_map_atomic_wc(mapping, gtt_base); |
561 | src_vaddr = kmap_atomic(user_page, KM_USER1); | |
562 | unwritten = __copy_from_user_inatomic_nocache(dst_vaddr + gtt_offset, | |
563 | src_vaddr + user_offset, | |
564 | length); | |
565 | kunmap_atomic(src_vaddr, KM_USER1); | |
566 | io_mapping_unmap_atomic(dst_vaddr); | |
0839ccb8 KP |
567 | if (unwritten) |
568 | return -EFAULT; | |
9b7530cc | 569 | return 0; |
9b7530cc LT |
570 | } |
571 | ||
40123c1f EA |
572 | static inline int |
573 | fast_shmem_write(struct page **pages, | |
574 | loff_t page_base, int page_offset, | |
575 | char __user *data, | |
576 | int length) | |
577 | { | |
578 | char __iomem *vaddr; | |
d0088775 | 579 | unsigned long unwritten; |
40123c1f EA |
580 | |
581 | vaddr = kmap_atomic(pages[page_base >> PAGE_SHIFT], KM_USER0); | |
582 | if (vaddr == NULL) | |
583 | return -ENOMEM; | |
d0088775 | 584 | unwritten = __copy_from_user_inatomic(vaddr + page_offset, data, length); |
40123c1f EA |
585 | kunmap_atomic(vaddr, KM_USER0); |
586 | ||
d0088775 DA |
587 | if (unwritten) |
588 | return -EFAULT; | |
40123c1f EA |
589 | return 0; |
590 | } | |
591 | ||
3de09aa3 EA |
592 | /** |
593 | * This is the fast pwrite path, where we copy the data directly from the | |
594 | * user into the GTT, uncached. | |
595 | */ | |
673a394b | 596 | static int |
3de09aa3 EA |
597 | i915_gem_gtt_pwrite_fast(struct drm_device *dev, struct drm_gem_object *obj, |
598 | struct drm_i915_gem_pwrite *args, | |
599 | struct drm_file *file_priv) | |
673a394b EA |
600 | { |
601 | struct drm_i915_gem_object *obj_priv = obj->driver_private; | |
0839ccb8 | 602 | drm_i915_private_t *dev_priv = dev->dev_private; |
673a394b | 603 | ssize_t remain; |
0839ccb8 | 604 | loff_t offset, page_base; |
673a394b | 605 | char __user *user_data; |
0839ccb8 KP |
606 | int page_offset, page_length; |
607 | int ret; | |
673a394b EA |
608 | |
609 | user_data = (char __user *) (uintptr_t) args->data_ptr; | |
610 | remain = args->size; | |
611 | if (!access_ok(VERIFY_READ, user_data, remain)) | |
612 | return -EFAULT; | |
613 | ||
614 | ||
615 | mutex_lock(&dev->struct_mutex); | |
616 | ret = i915_gem_object_pin(obj, 0); | |
617 | if (ret) { | |
618 | mutex_unlock(&dev->struct_mutex); | |
619 | return ret; | |
620 | } | |
2ef7eeaa | 621 | ret = i915_gem_object_set_to_gtt_domain(obj, 1); |
673a394b EA |
622 | if (ret) |
623 | goto fail; | |
624 | ||
625 | obj_priv = obj->driver_private; | |
626 | offset = obj_priv->gtt_offset + args->offset; | |
673a394b EA |
627 | |
628 | while (remain > 0) { | |
629 | /* Operation in this page | |
630 | * | |
0839ccb8 KP |
631 | * page_base = page offset within aperture |
632 | * page_offset = offset within page | |
633 | * page_length = bytes to copy for this page | |
673a394b | 634 | */ |
0839ccb8 KP |
635 | page_base = (offset & ~(PAGE_SIZE-1)); |
636 | page_offset = offset & (PAGE_SIZE-1); | |
637 | page_length = remain; | |
638 | if ((page_offset + remain) > PAGE_SIZE) | |
639 | page_length = PAGE_SIZE - page_offset; | |
640 | ||
641 | ret = fast_user_write (dev_priv->mm.gtt_mapping, page_base, | |
642 | page_offset, user_data, page_length); | |
643 | ||
644 | /* If we get a fault while copying data, then (presumably) our | |
3de09aa3 EA |
645 | * source page isn't available. Return the error and we'll |
646 | * retry in the slow path. | |
0839ccb8 | 647 | */ |
3de09aa3 EA |
648 | if (ret) |
649 | goto fail; | |
673a394b | 650 | |
0839ccb8 KP |
651 | remain -= page_length; |
652 | user_data += page_length; | |
653 | offset += page_length; | |
673a394b | 654 | } |
673a394b EA |
655 | |
656 | fail: | |
657 | i915_gem_object_unpin(obj); | |
658 | mutex_unlock(&dev->struct_mutex); | |
659 | ||
660 | return ret; | |
661 | } | |
662 | ||
3de09aa3 EA |
663 | /** |
664 | * This is the fallback GTT pwrite path, which uses get_user_pages to pin | |
665 | * the memory and maps it using kmap_atomic for copying. | |
666 | * | |
667 | * This code resulted in x11perf -rgb10text consuming about 10% more CPU | |
668 | * than using i915_gem_gtt_pwrite_fast on a G45 (32-bit). | |
669 | */ | |
3043c60c | 670 | static int |
3de09aa3 EA |
671 | i915_gem_gtt_pwrite_slow(struct drm_device *dev, struct drm_gem_object *obj, |
672 | struct drm_i915_gem_pwrite *args, | |
673 | struct drm_file *file_priv) | |
673a394b | 674 | { |
3de09aa3 EA |
675 | struct drm_i915_gem_object *obj_priv = obj->driver_private; |
676 | drm_i915_private_t *dev_priv = dev->dev_private; | |
677 | ssize_t remain; | |
678 | loff_t gtt_page_base, offset; | |
679 | loff_t first_data_page, last_data_page, num_pages; | |
680 | loff_t pinned_pages, i; | |
681 | struct page **user_pages; | |
682 | struct mm_struct *mm = current->mm; | |
683 | int gtt_page_offset, data_page_offset, data_page_index, page_length; | |
673a394b | 684 | int ret; |
3de09aa3 EA |
685 | uint64_t data_ptr = args->data_ptr; |
686 | ||
687 | remain = args->size; | |
688 | ||
689 | /* Pin the user pages containing the data. We can't fault while | |
690 | * holding the struct mutex, and all of the pwrite implementations | |
691 | * want to hold it while dereferencing the user data. | |
692 | */ | |
693 | first_data_page = data_ptr / PAGE_SIZE; | |
694 | last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE; | |
695 | num_pages = last_data_page - first_data_page + 1; | |
696 | ||
8e7d2b2c | 697 | user_pages = drm_calloc_large(num_pages, sizeof(struct page *)); |
3de09aa3 EA |
698 | if (user_pages == NULL) |
699 | return -ENOMEM; | |
700 | ||
701 | down_read(&mm->mmap_sem); | |
702 | pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr, | |
703 | num_pages, 0, 0, user_pages, NULL); | |
704 | up_read(&mm->mmap_sem); | |
705 | if (pinned_pages < num_pages) { | |
706 | ret = -EFAULT; | |
707 | goto out_unpin_pages; | |
708 | } | |
673a394b EA |
709 | |
710 | mutex_lock(&dev->struct_mutex); | |
3de09aa3 EA |
711 | ret = i915_gem_object_pin(obj, 0); |
712 | if (ret) | |
713 | goto out_unlock; | |
714 | ||
715 | ret = i915_gem_object_set_to_gtt_domain(obj, 1); | |
716 | if (ret) | |
717 | goto out_unpin_object; | |
718 | ||
719 | obj_priv = obj->driver_private; | |
720 | offset = obj_priv->gtt_offset + args->offset; | |
721 | ||
722 | while (remain > 0) { | |
723 | /* Operation in this page | |
724 | * | |
725 | * gtt_page_base = page offset within aperture | |
726 | * gtt_page_offset = offset within page in aperture | |
727 | * data_page_index = page number in get_user_pages return | |
728 | * data_page_offset = offset with data_page_index page. | |
729 | * page_length = bytes to copy for this page | |
730 | */ | |
731 | gtt_page_base = offset & PAGE_MASK; | |
732 | gtt_page_offset = offset & ~PAGE_MASK; | |
733 | data_page_index = data_ptr / PAGE_SIZE - first_data_page; | |
734 | data_page_offset = data_ptr & ~PAGE_MASK; | |
735 | ||
736 | page_length = remain; | |
737 | if ((gtt_page_offset + page_length) > PAGE_SIZE) | |
738 | page_length = PAGE_SIZE - gtt_page_offset; | |
739 | if ((data_page_offset + page_length) > PAGE_SIZE) | |
740 | page_length = PAGE_SIZE - data_page_offset; | |
741 | ||
742 | ret = slow_kernel_write(dev_priv->mm.gtt_mapping, | |
743 | gtt_page_base, gtt_page_offset, | |
744 | user_pages[data_page_index], | |
745 | data_page_offset, | |
746 | page_length); | |
747 | ||
748 | /* If we get a fault while copying data, then (presumably) our | |
749 | * source page isn't available. Return the error and we'll | |
750 | * retry in the slow path. | |
751 | */ | |
752 | if (ret) | |
753 | goto out_unpin_object; | |
754 | ||
755 | remain -= page_length; | |
756 | offset += page_length; | |
757 | data_ptr += page_length; | |
758 | } | |
759 | ||
760 | out_unpin_object: | |
761 | i915_gem_object_unpin(obj); | |
762 | out_unlock: | |
763 | mutex_unlock(&dev->struct_mutex); | |
764 | out_unpin_pages: | |
765 | for (i = 0; i < pinned_pages; i++) | |
766 | page_cache_release(user_pages[i]); | |
8e7d2b2c | 767 | drm_free_large(user_pages); |
3de09aa3 EA |
768 | |
769 | return ret; | |
770 | } | |
771 | ||
40123c1f EA |
772 | /** |
773 | * This is the fast shmem pwrite path, which attempts to directly | |
774 | * copy_from_user into the kmapped pages backing the object. | |
775 | */ | |
3043c60c | 776 | static int |
40123c1f EA |
777 | i915_gem_shmem_pwrite_fast(struct drm_device *dev, struct drm_gem_object *obj, |
778 | struct drm_i915_gem_pwrite *args, | |
779 | struct drm_file *file_priv) | |
673a394b | 780 | { |
40123c1f EA |
781 | struct drm_i915_gem_object *obj_priv = obj->driver_private; |
782 | ssize_t remain; | |
783 | loff_t offset, page_base; | |
784 | char __user *user_data; | |
785 | int page_offset, page_length; | |
673a394b | 786 | int ret; |
40123c1f EA |
787 | |
788 | user_data = (char __user *) (uintptr_t) args->data_ptr; | |
789 | remain = args->size; | |
673a394b EA |
790 | |
791 | mutex_lock(&dev->struct_mutex); | |
792 | ||
40123c1f EA |
793 | ret = i915_gem_object_get_pages(obj); |
794 | if (ret != 0) | |
795 | goto fail_unlock; | |
673a394b | 796 | |
e47c68e9 | 797 | ret = i915_gem_object_set_to_cpu_domain(obj, 1); |
40123c1f EA |
798 | if (ret != 0) |
799 | goto fail_put_pages; | |
800 | ||
801 | obj_priv = obj->driver_private; | |
802 | offset = args->offset; | |
803 | obj_priv->dirty = 1; | |
804 | ||
805 | while (remain > 0) { | |
806 | /* Operation in this page | |
807 | * | |
808 | * page_base = page offset within aperture | |
809 | * page_offset = offset within page | |
810 | * page_length = bytes to copy for this page | |
811 | */ | |
812 | page_base = (offset & ~(PAGE_SIZE-1)); | |
813 | page_offset = offset & (PAGE_SIZE-1); | |
814 | page_length = remain; | |
815 | if ((page_offset + remain) > PAGE_SIZE) | |
816 | page_length = PAGE_SIZE - page_offset; | |
817 | ||
818 | ret = fast_shmem_write(obj_priv->pages, | |
819 | page_base, page_offset, | |
820 | user_data, page_length); | |
821 | if (ret) | |
822 | goto fail_put_pages; | |
823 | ||
824 | remain -= page_length; | |
825 | user_data += page_length; | |
826 | offset += page_length; | |
827 | } | |
828 | ||
829 | fail_put_pages: | |
830 | i915_gem_object_put_pages(obj); | |
831 | fail_unlock: | |
832 | mutex_unlock(&dev->struct_mutex); | |
833 | ||
834 | return ret; | |
835 | } | |
836 | ||
837 | /** | |
838 | * This is the fallback shmem pwrite path, which uses get_user_pages to pin | |
839 | * the memory and maps it using kmap_atomic for copying. | |
840 | * | |
841 | * This avoids taking mmap_sem for faulting on the user's address while the | |
842 | * struct_mutex is held. | |
843 | */ | |
844 | static int | |
845 | i915_gem_shmem_pwrite_slow(struct drm_device *dev, struct drm_gem_object *obj, | |
846 | struct drm_i915_gem_pwrite *args, | |
847 | struct drm_file *file_priv) | |
848 | { | |
849 | struct drm_i915_gem_object *obj_priv = obj->driver_private; | |
850 | struct mm_struct *mm = current->mm; | |
851 | struct page **user_pages; | |
852 | ssize_t remain; | |
853 | loff_t offset, pinned_pages, i; | |
854 | loff_t first_data_page, last_data_page, num_pages; | |
855 | int shmem_page_index, shmem_page_offset; | |
856 | int data_page_index, data_page_offset; | |
857 | int page_length; | |
858 | int ret; | |
859 | uint64_t data_ptr = args->data_ptr; | |
280b713b | 860 | int do_bit17_swizzling; |
40123c1f EA |
861 | |
862 | remain = args->size; | |
863 | ||
864 | /* Pin the user pages containing the data. We can't fault while | |
865 | * holding the struct mutex, and all of the pwrite implementations | |
866 | * want to hold it while dereferencing the user data. | |
867 | */ | |
868 | first_data_page = data_ptr / PAGE_SIZE; | |
869 | last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE; | |
870 | num_pages = last_data_page - first_data_page + 1; | |
871 | ||
8e7d2b2c | 872 | user_pages = drm_calloc_large(num_pages, sizeof(struct page *)); |
40123c1f EA |
873 | if (user_pages == NULL) |
874 | return -ENOMEM; | |
875 | ||
876 | down_read(&mm->mmap_sem); | |
877 | pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr, | |
878 | num_pages, 0, 0, user_pages, NULL); | |
879 | up_read(&mm->mmap_sem); | |
880 | if (pinned_pages < num_pages) { | |
881 | ret = -EFAULT; | |
882 | goto fail_put_user_pages; | |
673a394b EA |
883 | } |
884 | ||
280b713b EA |
885 | do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj); |
886 | ||
40123c1f EA |
887 | mutex_lock(&dev->struct_mutex); |
888 | ||
07f73f69 CW |
889 | ret = i915_gem_object_get_pages_or_evict(obj); |
890 | if (ret) | |
40123c1f EA |
891 | goto fail_unlock; |
892 | ||
893 | ret = i915_gem_object_set_to_cpu_domain(obj, 1); | |
894 | if (ret != 0) | |
895 | goto fail_put_pages; | |
896 | ||
897 | obj_priv = obj->driver_private; | |
673a394b | 898 | offset = args->offset; |
40123c1f | 899 | obj_priv->dirty = 1; |
673a394b | 900 | |
40123c1f EA |
901 | while (remain > 0) { |
902 | /* Operation in this page | |
903 | * | |
904 | * shmem_page_index = page number within shmem file | |
905 | * shmem_page_offset = offset within page in shmem file | |
906 | * data_page_index = page number in get_user_pages return | |
907 | * data_page_offset = offset with data_page_index page. | |
908 | * page_length = bytes to copy for this page | |
909 | */ | |
910 | shmem_page_index = offset / PAGE_SIZE; | |
911 | shmem_page_offset = offset & ~PAGE_MASK; | |
912 | data_page_index = data_ptr / PAGE_SIZE - first_data_page; | |
913 | data_page_offset = data_ptr & ~PAGE_MASK; | |
914 | ||
915 | page_length = remain; | |
916 | if ((shmem_page_offset + page_length) > PAGE_SIZE) | |
917 | page_length = PAGE_SIZE - shmem_page_offset; | |
918 | if ((data_page_offset + page_length) > PAGE_SIZE) | |
919 | page_length = PAGE_SIZE - data_page_offset; | |
920 | ||
280b713b EA |
921 | if (do_bit17_swizzling) { |
922 | ret = slow_shmem_bit17_copy(obj_priv->pages[shmem_page_index], | |
923 | shmem_page_offset, | |
924 | user_pages[data_page_index], | |
925 | data_page_offset, | |
926 | page_length, | |
927 | 0); | |
928 | } else { | |
929 | ret = slow_shmem_copy(obj_priv->pages[shmem_page_index], | |
930 | shmem_page_offset, | |
931 | user_pages[data_page_index], | |
932 | data_page_offset, | |
933 | page_length); | |
934 | } | |
40123c1f EA |
935 | if (ret) |
936 | goto fail_put_pages; | |
937 | ||
938 | remain -= page_length; | |
939 | data_ptr += page_length; | |
940 | offset += page_length; | |
673a394b EA |
941 | } |
942 | ||
40123c1f EA |
943 | fail_put_pages: |
944 | i915_gem_object_put_pages(obj); | |
945 | fail_unlock: | |
673a394b | 946 | mutex_unlock(&dev->struct_mutex); |
40123c1f EA |
947 | fail_put_user_pages: |
948 | for (i = 0; i < pinned_pages; i++) | |
949 | page_cache_release(user_pages[i]); | |
8e7d2b2c | 950 | drm_free_large(user_pages); |
673a394b | 951 | |
40123c1f | 952 | return ret; |
673a394b EA |
953 | } |
954 | ||
955 | /** | |
956 | * Writes data to the object referenced by handle. | |
957 | * | |
958 | * On error, the contents of the buffer that were to be modified are undefined. | |
959 | */ | |
960 | int | |
961 | i915_gem_pwrite_ioctl(struct drm_device *dev, void *data, | |
962 | struct drm_file *file_priv) | |
963 | { | |
964 | struct drm_i915_gem_pwrite *args = data; | |
965 | struct drm_gem_object *obj; | |
966 | struct drm_i915_gem_object *obj_priv; | |
967 | int ret = 0; | |
968 | ||
969 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); | |
970 | if (obj == NULL) | |
971 | return -EBADF; | |
972 | obj_priv = obj->driver_private; | |
973 | ||
974 | /* Bounds check destination. | |
975 | * | |
976 | * XXX: This could use review for overflow issues... | |
977 | */ | |
978 | if (args->offset > obj->size || args->size > obj->size || | |
979 | args->offset + args->size > obj->size) { | |
980 | drm_gem_object_unreference(obj); | |
981 | return -EINVAL; | |
982 | } | |
983 | ||
984 | /* We can only do the GTT pwrite on untiled buffers, as otherwise | |
985 | * it would end up going through the fenced access, and we'll get | |
986 | * different detiling behavior between reading and writing. | |
987 | * pread/pwrite currently are reading and writing from the CPU | |
988 | * perspective, requiring manual detiling by the client. | |
989 | */ | |
71acb5eb DA |
990 | if (obj_priv->phys_obj) |
991 | ret = i915_gem_phys_pwrite(dev, obj, args, file_priv); | |
992 | else if (obj_priv->tiling_mode == I915_TILING_NONE && | |
3de09aa3 EA |
993 | dev->gtt_total != 0) { |
994 | ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file_priv); | |
995 | if (ret == -EFAULT) { | |
996 | ret = i915_gem_gtt_pwrite_slow(dev, obj, args, | |
997 | file_priv); | |
998 | } | |
280b713b EA |
999 | } else if (i915_gem_object_needs_bit17_swizzle(obj)) { |
1000 | ret = i915_gem_shmem_pwrite_slow(dev, obj, args, file_priv); | |
40123c1f EA |
1001 | } else { |
1002 | ret = i915_gem_shmem_pwrite_fast(dev, obj, args, file_priv); | |
1003 | if (ret == -EFAULT) { | |
1004 | ret = i915_gem_shmem_pwrite_slow(dev, obj, args, | |
1005 | file_priv); | |
1006 | } | |
1007 | } | |
673a394b EA |
1008 | |
1009 | #if WATCH_PWRITE | |
1010 | if (ret) | |
1011 | DRM_INFO("pwrite failed %d\n", ret); | |
1012 | #endif | |
1013 | ||
1014 | drm_gem_object_unreference(obj); | |
1015 | ||
1016 | return ret; | |
1017 | } | |
1018 | ||
1019 | /** | |
2ef7eeaa EA |
1020 | * Called when user space prepares to use an object with the CPU, either |
1021 | * through the mmap ioctl's mapping or a GTT mapping. | |
673a394b EA |
1022 | */ |
1023 | int | |
1024 | i915_gem_set_domain_ioctl(struct drm_device *dev, void *data, | |
1025 | struct drm_file *file_priv) | |
1026 | { | |
a09ba7fa | 1027 | struct drm_i915_private *dev_priv = dev->dev_private; |
673a394b EA |
1028 | struct drm_i915_gem_set_domain *args = data; |
1029 | struct drm_gem_object *obj; | |
652c393a | 1030 | struct drm_i915_gem_object *obj_priv; |
2ef7eeaa EA |
1031 | uint32_t read_domains = args->read_domains; |
1032 | uint32_t write_domain = args->write_domain; | |
673a394b EA |
1033 | int ret; |
1034 | ||
1035 | if (!(dev->driver->driver_features & DRIVER_GEM)) | |
1036 | return -ENODEV; | |
1037 | ||
2ef7eeaa | 1038 | /* Only handle setting domains to types used by the CPU. */ |
21d509e3 | 1039 | if (write_domain & I915_GEM_GPU_DOMAINS) |
2ef7eeaa EA |
1040 | return -EINVAL; |
1041 | ||
21d509e3 | 1042 | if (read_domains & I915_GEM_GPU_DOMAINS) |
2ef7eeaa EA |
1043 | return -EINVAL; |
1044 | ||
1045 | /* Having something in the write domain implies it's in the read | |
1046 | * domain, and only that read domain. Enforce that in the request. | |
1047 | */ | |
1048 | if (write_domain != 0 && read_domains != write_domain) | |
1049 | return -EINVAL; | |
1050 | ||
673a394b EA |
1051 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); |
1052 | if (obj == NULL) | |
1053 | return -EBADF; | |
652c393a | 1054 | obj_priv = obj->driver_private; |
673a394b EA |
1055 | |
1056 | mutex_lock(&dev->struct_mutex); | |
652c393a JB |
1057 | |
1058 | intel_mark_busy(dev, obj); | |
1059 | ||
673a394b | 1060 | #if WATCH_BUF |
cfd43c02 | 1061 | DRM_INFO("set_domain_ioctl %p(%zd), %08x %08x\n", |
2ef7eeaa | 1062 | obj, obj->size, read_domains, write_domain); |
673a394b | 1063 | #endif |
2ef7eeaa EA |
1064 | if (read_domains & I915_GEM_DOMAIN_GTT) { |
1065 | ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0); | |
02354392 | 1066 | |
a09ba7fa EA |
1067 | /* Update the LRU on the fence for the CPU access that's |
1068 | * about to occur. | |
1069 | */ | |
1070 | if (obj_priv->fence_reg != I915_FENCE_REG_NONE) { | |
1071 | list_move_tail(&obj_priv->fence_list, | |
1072 | &dev_priv->mm.fence_list); | |
1073 | } | |
1074 | ||
02354392 EA |
1075 | /* Silently promote "you're not bound, there was nothing to do" |
1076 | * to success, since the client was just asking us to | |
1077 | * make sure everything was done. | |
1078 | */ | |
1079 | if (ret == -EINVAL) | |
1080 | ret = 0; | |
2ef7eeaa | 1081 | } else { |
e47c68e9 | 1082 | ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0); |
2ef7eeaa EA |
1083 | } |
1084 | ||
673a394b EA |
1085 | drm_gem_object_unreference(obj); |
1086 | mutex_unlock(&dev->struct_mutex); | |
1087 | return ret; | |
1088 | } | |
1089 | ||
1090 | /** | |
1091 | * Called when user space has done writes to this buffer | |
1092 | */ | |
1093 | int | |
1094 | i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data, | |
1095 | struct drm_file *file_priv) | |
1096 | { | |
1097 | struct drm_i915_gem_sw_finish *args = data; | |
1098 | struct drm_gem_object *obj; | |
1099 | struct drm_i915_gem_object *obj_priv; | |
1100 | int ret = 0; | |
1101 | ||
1102 | if (!(dev->driver->driver_features & DRIVER_GEM)) | |
1103 | return -ENODEV; | |
1104 | ||
1105 | mutex_lock(&dev->struct_mutex); | |
1106 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); | |
1107 | if (obj == NULL) { | |
1108 | mutex_unlock(&dev->struct_mutex); | |
1109 | return -EBADF; | |
1110 | } | |
1111 | ||
1112 | #if WATCH_BUF | |
cfd43c02 | 1113 | DRM_INFO("%s: sw_finish %d (%p %zd)\n", |
673a394b EA |
1114 | __func__, args->handle, obj, obj->size); |
1115 | #endif | |
1116 | obj_priv = obj->driver_private; | |
1117 | ||
1118 | /* Pinned buffers may be scanout, so flush the cache */ | |
e47c68e9 EA |
1119 | if (obj_priv->pin_count) |
1120 | i915_gem_object_flush_cpu_write_domain(obj); | |
1121 | ||
673a394b EA |
1122 | drm_gem_object_unreference(obj); |
1123 | mutex_unlock(&dev->struct_mutex); | |
1124 | return ret; | |
1125 | } | |
1126 | ||
1127 | /** | |
1128 | * Maps the contents of an object, returning the address it is mapped | |
1129 | * into. | |
1130 | * | |
1131 | * While the mapping holds a reference on the contents of the object, it doesn't | |
1132 | * imply a ref on the object itself. | |
1133 | */ | |
1134 | int | |
1135 | i915_gem_mmap_ioctl(struct drm_device *dev, void *data, | |
1136 | struct drm_file *file_priv) | |
1137 | { | |
1138 | struct drm_i915_gem_mmap *args = data; | |
1139 | struct drm_gem_object *obj; | |
1140 | loff_t offset; | |
1141 | unsigned long addr; | |
1142 | ||
1143 | if (!(dev->driver->driver_features & DRIVER_GEM)) | |
1144 | return -ENODEV; | |
1145 | ||
1146 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); | |
1147 | if (obj == NULL) | |
1148 | return -EBADF; | |
1149 | ||
1150 | offset = args->offset; | |
1151 | ||
1152 | down_write(¤t->mm->mmap_sem); | |
1153 | addr = do_mmap(obj->filp, 0, args->size, | |
1154 | PROT_READ | PROT_WRITE, MAP_SHARED, | |
1155 | args->offset); | |
1156 | up_write(¤t->mm->mmap_sem); | |
1157 | mutex_lock(&dev->struct_mutex); | |
1158 | drm_gem_object_unreference(obj); | |
1159 | mutex_unlock(&dev->struct_mutex); | |
1160 | if (IS_ERR((void *)addr)) | |
1161 | return addr; | |
1162 | ||
1163 | args->addr_ptr = (uint64_t) addr; | |
1164 | ||
1165 | return 0; | |
1166 | } | |
1167 | ||
de151cf6 JB |
1168 | /** |
1169 | * i915_gem_fault - fault a page into the GTT | |
1170 | * vma: VMA in question | |
1171 | * vmf: fault info | |
1172 | * | |
1173 | * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped | |
1174 | * from userspace. The fault handler takes care of binding the object to | |
1175 | * the GTT (if needed), allocating and programming a fence register (again, | |
1176 | * only if needed based on whether the old reg is still valid or the object | |
1177 | * is tiled) and inserting a new PTE into the faulting process. | |
1178 | * | |
1179 | * Note that the faulting process may involve evicting existing objects | |
1180 | * from the GTT and/or fence registers to make room. So performance may | |
1181 | * suffer if the GTT working set is large or there are few fence registers | |
1182 | * left. | |
1183 | */ | |
1184 | int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf) | |
1185 | { | |
1186 | struct drm_gem_object *obj = vma->vm_private_data; | |
1187 | struct drm_device *dev = obj->dev; | |
1188 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1189 | struct drm_i915_gem_object *obj_priv = obj->driver_private; | |
1190 | pgoff_t page_offset; | |
1191 | unsigned long pfn; | |
1192 | int ret = 0; | |
0f973f27 | 1193 | bool write = !!(vmf->flags & FAULT_FLAG_WRITE); |
de151cf6 JB |
1194 | |
1195 | /* We don't use vmf->pgoff since that has the fake offset */ | |
1196 | page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >> | |
1197 | PAGE_SHIFT; | |
1198 | ||
1199 | /* Now bind it into the GTT if needed */ | |
1200 | mutex_lock(&dev->struct_mutex); | |
1201 | if (!obj_priv->gtt_space) { | |
e67b8ce1 | 1202 | ret = i915_gem_object_bind_to_gtt(obj, 0); |
c715089f CW |
1203 | if (ret) |
1204 | goto unlock; | |
07f4f3e8 | 1205 | |
14b60391 | 1206 | list_add_tail(&obj_priv->list, &dev_priv->mm.inactive_list); |
07f4f3e8 KH |
1207 | |
1208 | ret = i915_gem_object_set_to_gtt_domain(obj, write); | |
c715089f CW |
1209 | if (ret) |
1210 | goto unlock; | |
de151cf6 JB |
1211 | } |
1212 | ||
1213 | /* Need a new fence register? */ | |
a09ba7fa | 1214 | if (obj_priv->tiling_mode != I915_TILING_NONE) { |
8c4b8c3f | 1215 | ret = i915_gem_object_get_fence_reg(obj); |
c715089f CW |
1216 | if (ret) |
1217 | goto unlock; | |
d9ddcb96 | 1218 | } |
de151cf6 JB |
1219 | |
1220 | pfn = ((dev->agp->base + obj_priv->gtt_offset) >> PAGE_SHIFT) + | |
1221 | page_offset; | |
1222 | ||
1223 | /* Finally, remap it using the new GTT offset */ | |
1224 | ret = vm_insert_pfn(vma, (unsigned long)vmf->virtual_address, pfn); | |
c715089f | 1225 | unlock: |
de151cf6 JB |
1226 | mutex_unlock(&dev->struct_mutex); |
1227 | ||
1228 | switch (ret) { | |
c715089f CW |
1229 | case 0: |
1230 | case -ERESTARTSYS: | |
1231 | return VM_FAULT_NOPAGE; | |
de151cf6 JB |
1232 | case -ENOMEM: |
1233 | case -EAGAIN: | |
1234 | return VM_FAULT_OOM; | |
de151cf6 | 1235 | default: |
c715089f | 1236 | return VM_FAULT_SIGBUS; |
de151cf6 JB |
1237 | } |
1238 | } | |
1239 | ||
1240 | /** | |
1241 | * i915_gem_create_mmap_offset - create a fake mmap offset for an object | |
1242 | * @obj: obj in question | |
1243 | * | |
1244 | * GEM memory mapping works by handing back to userspace a fake mmap offset | |
1245 | * it can use in a subsequent mmap(2) call. The DRM core code then looks | |
1246 | * up the object based on the offset and sets up the various memory mapping | |
1247 | * structures. | |
1248 | * | |
1249 | * This routine allocates and attaches a fake offset for @obj. | |
1250 | */ | |
1251 | static int | |
1252 | i915_gem_create_mmap_offset(struct drm_gem_object *obj) | |
1253 | { | |
1254 | struct drm_device *dev = obj->dev; | |
1255 | struct drm_gem_mm *mm = dev->mm_private; | |
1256 | struct drm_i915_gem_object *obj_priv = obj->driver_private; | |
1257 | struct drm_map_list *list; | |
f77d390c | 1258 | struct drm_local_map *map; |
de151cf6 JB |
1259 | int ret = 0; |
1260 | ||
1261 | /* Set the object up for mmap'ing */ | |
1262 | list = &obj->map_list; | |
9a298b2a | 1263 | list->map = kzalloc(sizeof(struct drm_map_list), GFP_KERNEL); |
de151cf6 JB |
1264 | if (!list->map) |
1265 | return -ENOMEM; | |
1266 | ||
1267 | map = list->map; | |
1268 | map->type = _DRM_GEM; | |
1269 | map->size = obj->size; | |
1270 | map->handle = obj; | |
1271 | ||
1272 | /* Get a DRM GEM mmap offset allocated... */ | |
1273 | list->file_offset_node = drm_mm_search_free(&mm->offset_manager, | |
1274 | obj->size / PAGE_SIZE, 0, 0); | |
1275 | if (!list->file_offset_node) { | |
1276 | DRM_ERROR("failed to allocate offset for bo %d\n", obj->name); | |
1277 | ret = -ENOMEM; | |
1278 | goto out_free_list; | |
1279 | } | |
1280 | ||
1281 | list->file_offset_node = drm_mm_get_block(list->file_offset_node, | |
1282 | obj->size / PAGE_SIZE, 0); | |
1283 | if (!list->file_offset_node) { | |
1284 | ret = -ENOMEM; | |
1285 | goto out_free_list; | |
1286 | } | |
1287 | ||
1288 | list->hash.key = list->file_offset_node->start; | |
1289 | if (drm_ht_insert_item(&mm->offset_hash, &list->hash)) { | |
1290 | DRM_ERROR("failed to add to map hash\n"); | |
1291 | goto out_free_mm; | |
1292 | } | |
1293 | ||
1294 | /* By now we should be all set, any drm_mmap request on the offset | |
1295 | * below will get to our mmap & fault handler */ | |
1296 | obj_priv->mmap_offset = ((uint64_t) list->hash.key) << PAGE_SHIFT; | |
1297 | ||
1298 | return 0; | |
1299 | ||
1300 | out_free_mm: | |
1301 | drm_mm_put_block(list->file_offset_node); | |
1302 | out_free_list: | |
9a298b2a | 1303 | kfree(list->map); |
de151cf6 JB |
1304 | |
1305 | return ret; | |
1306 | } | |
1307 | ||
901782b2 CW |
1308 | /** |
1309 | * i915_gem_release_mmap - remove physical page mappings | |
1310 | * @obj: obj in question | |
1311 | * | |
1312 | * Preserve the reservation of the mmaping with the DRM core code, but | |
1313 | * relinquish ownership of the pages back to the system. | |
1314 | * | |
1315 | * It is vital that we remove the page mapping if we have mapped a tiled | |
1316 | * object through the GTT and then lose the fence register due to | |
1317 | * resource pressure. Similarly if the object has been moved out of the | |
1318 | * aperture, than pages mapped into userspace must be revoked. Removing the | |
1319 | * mapping will then trigger a page fault on the next user access, allowing | |
1320 | * fixup by i915_gem_fault(). | |
1321 | */ | |
d05ca301 | 1322 | void |
901782b2 CW |
1323 | i915_gem_release_mmap(struct drm_gem_object *obj) |
1324 | { | |
1325 | struct drm_device *dev = obj->dev; | |
1326 | struct drm_i915_gem_object *obj_priv = obj->driver_private; | |
1327 | ||
1328 | if (dev->dev_mapping) | |
1329 | unmap_mapping_range(dev->dev_mapping, | |
1330 | obj_priv->mmap_offset, obj->size, 1); | |
1331 | } | |
1332 | ||
ab00b3e5 JB |
1333 | static void |
1334 | i915_gem_free_mmap_offset(struct drm_gem_object *obj) | |
1335 | { | |
1336 | struct drm_device *dev = obj->dev; | |
1337 | struct drm_i915_gem_object *obj_priv = obj->driver_private; | |
1338 | struct drm_gem_mm *mm = dev->mm_private; | |
1339 | struct drm_map_list *list; | |
1340 | ||
1341 | list = &obj->map_list; | |
1342 | drm_ht_remove_item(&mm->offset_hash, &list->hash); | |
1343 | ||
1344 | if (list->file_offset_node) { | |
1345 | drm_mm_put_block(list->file_offset_node); | |
1346 | list->file_offset_node = NULL; | |
1347 | } | |
1348 | ||
1349 | if (list->map) { | |
9a298b2a | 1350 | kfree(list->map); |
ab00b3e5 JB |
1351 | list->map = NULL; |
1352 | } | |
1353 | ||
1354 | obj_priv->mmap_offset = 0; | |
1355 | } | |
1356 | ||
de151cf6 JB |
1357 | /** |
1358 | * i915_gem_get_gtt_alignment - return required GTT alignment for an object | |
1359 | * @obj: object to check | |
1360 | * | |
1361 | * Return the required GTT alignment for an object, taking into account | |
1362 | * potential fence register mapping if needed. | |
1363 | */ | |
1364 | static uint32_t | |
1365 | i915_gem_get_gtt_alignment(struct drm_gem_object *obj) | |
1366 | { | |
1367 | struct drm_device *dev = obj->dev; | |
1368 | struct drm_i915_gem_object *obj_priv = obj->driver_private; | |
1369 | int start, i; | |
1370 | ||
1371 | /* | |
1372 | * Minimum alignment is 4k (GTT page size), but might be greater | |
1373 | * if a fence register is needed for the object. | |
1374 | */ | |
1375 | if (IS_I965G(dev) || obj_priv->tiling_mode == I915_TILING_NONE) | |
1376 | return 4096; | |
1377 | ||
1378 | /* | |
1379 | * Previous chips need to be aligned to the size of the smallest | |
1380 | * fence register that can contain the object. | |
1381 | */ | |
1382 | if (IS_I9XX(dev)) | |
1383 | start = 1024*1024; | |
1384 | else | |
1385 | start = 512*1024; | |
1386 | ||
1387 | for (i = start; i < obj->size; i <<= 1) | |
1388 | ; | |
1389 | ||
1390 | return i; | |
1391 | } | |
1392 | ||
1393 | /** | |
1394 | * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing | |
1395 | * @dev: DRM device | |
1396 | * @data: GTT mapping ioctl data | |
1397 | * @file_priv: GEM object info | |
1398 | * | |
1399 | * Simply returns the fake offset to userspace so it can mmap it. | |
1400 | * The mmap call will end up in drm_gem_mmap(), which will set things | |
1401 | * up so we can get faults in the handler above. | |
1402 | * | |
1403 | * The fault handler will take care of binding the object into the GTT | |
1404 | * (since it may have been evicted to make room for something), allocating | |
1405 | * a fence register, and mapping the appropriate aperture address into | |
1406 | * userspace. | |
1407 | */ | |
1408 | int | |
1409 | i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data, | |
1410 | struct drm_file *file_priv) | |
1411 | { | |
1412 | struct drm_i915_gem_mmap_gtt *args = data; | |
1413 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1414 | struct drm_gem_object *obj; | |
1415 | struct drm_i915_gem_object *obj_priv; | |
1416 | int ret; | |
1417 | ||
1418 | if (!(dev->driver->driver_features & DRIVER_GEM)) | |
1419 | return -ENODEV; | |
1420 | ||
1421 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); | |
1422 | if (obj == NULL) | |
1423 | return -EBADF; | |
1424 | ||
1425 | mutex_lock(&dev->struct_mutex); | |
1426 | ||
1427 | obj_priv = obj->driver_private; | |
1428 | ||
ab18282d CW |
1429 | if (obj_priv->madv != I915_MADV_WILLNEED) { |
1430 | DRM_ERROR("Attempting to mmap a purgeable buffer\n"); | |
1431 | drm_gem_object_unreference(obj); | |
1432 | mutex_unlock(&dev->struct_mutex); | |
1433 | return -EINVAL; | |
1434 | } | |
1435 | ||
1436 | ||
de151cf6 JB |
1437 | if (!obj_priv->mmap_offset) { |
1438 | ret = i915_gem_create_mmap_offset(obj); | |
13af1062 CW |
1439 | if (ret) { |
1440 | drm_gem_object_unreference(obj); | |
1441 | mutex_unlock(&dev->struct_mutex); | |
de151cf6 | 1442 | return ret; |
13af1062 | 1443 | } |
de151cf6 JB |
1444 | } |
1445 | ||
1446 | args->offset = obj_priv->mmap_offset; | |
1447 | ||
de151cf6 JB |
1448 | /* |
1449 | * Pull it into the GTT so that we have a page list (makes the | |
1450 | * initial fault faster and any subsequent flushing possible). | |
1451 | */ | |
1452 | if (!obj_priv->agp_mem) { | |
e67b8ce1 | 1453 | ret = i915_gem_object_bind_to_gtt(obj, 0); |
de151cf6 JB |
1454 | if (ret) { |
1455 | drm_gem_object_unreference(obj); | |
1456 | mutex_unlock(&dev->struct_mutex); | |
1457 | return ret; | |
1458 | } | |
14b60391 | 1459 | list_add_tail(&obj_priv->list, &dev_priv->mm.inactive_list); |
de151cf6 JB |
1460 | } |
1461 | ||
1462 | drm_gem_object_unreference(obj); | |
1463 | mutex_unlock(&dev->struct_mutex); | |
1464 | ||
1465 | return 0; | |
1466 | } | |
1467 | ||
6911a9b8 | 1468 | void |
856fa198 | 1469 | i915_gem_object_put_pages(struct drm_gem_object *obj) |
673a394b EA |
1470 | { |
1471 | struct drm_i915_gem_object *obj_priv = obj->driver_private; | |
1472 | int page_count = obj->size / PAGE_SIZE; | |
1473 | int i; | |
1474 | ||
856fa198 | 1475 | BUG_ON(obj_priv->pages_refcount == 0); |
bb6baf76 | 1476 | BUG_ON(obj_priv->madv == __I915_MADV_PURGED); |
673a394b | 1477 | |
856fa198 EA |
1478 | if (--obj_priv->pages_refcount != 0) |
1479 | return; | |
673a394b | 1480 | |
280b713b EA |
1481 | if (obj_priv->tiling_mode != I915_TILING_NONE) |
1482 | i915_gem_object_save_bit_17_swizzle(obj); | |
1483 | ||
3ef94daa | 1484 | if (obj_priv->madv == I915_MADV_DONTNEED) |
13a05fd9 | 1485 | obj_priv->dirty = 0; |
3ef94daa CW |
1486 | |
1487 | for (i = 0; i < page_count; i++) { | |
1488 | if (obj_priv->pages[i] == NULL) | |
1489 | break; | |
1490 | ||
1491 | if (obj_priv->dirty) | |
1492 | set_page_dirty(obj_priv->pages[i]); | |
1493 | ||
1494 | if (obj_priv->madv == I915_MADV_WILLNEED) | |
856fa198 | 1495 | mark_page_accessed(obj_priv->pages[i]); |
3ef94daa CW |
1496 | |
1497 | page_cache_release(obj_priv->pages[i]); | |
1498 | } | |
673a394b EA |
1499 | obj_priv->dirty = 0; |
1500 | ||
8e7d2b2c | 1501 | drm_free_large(obj_priv->pages); |
856fa198 | 1502 | obj_priv->pages = NULL; |
673a394b EA |
1503 | } |
1504 | ||
1505 | static void | |
ce44b0ea | 1506 | i915_gem_object_move_to_active(struct drm_gem_object *obj, uint32_t seqno) |
673a394b EA |
1507 | { |
1508 | struct drm_device *dev = obj->dev; | |
1509 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1510 | struct drm_i915_gem_object *obj_priv = obj->driver_private; | |
1511 | ||
1512 | /* Add a reference if we're newly entering the active list. */ | |
1513 | if (!obj_priv->active) { | |
1514 | drm_gem_object_reference(obj); | |
1515 | obj_priv->active = 1; | |
1516 | } | |
1517 | /* Move from whatever list we were on to the tail of execution. */ | |
5e118f41 | 1518 | spin_lock(&dev_priv->mm.active_list_lock); |
673a394b EA |
1519 | list_move_tail(&obj_priv->list, |
1520 | &dev_priv->mm.active_list); | |
5e118f41 | 1521 | spin_unlock(&dev_priv->mm.active_list_lock); |
ce44b0ea | 1522 | obj_priv->last_rendering_seqno = seqno; |
673a394b EA |
1523 | } |
1524 | ||
ce44b0ea EA |
1525 | static void |
1526 | i915_gem_object_move_to_flushing(struct drm_gem_object *obj) | |
1527 | { | |
1528 | struct drm_device *dev = obj->dev; | |
1529 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1530 | struct drm_i915_gem_object *obj_priv = obj->driver_private; | |
1531 | ||
1532 | BUG_ON(!obj_priv->active); | |
1533 | list_move_tail(&obj_priv->list, &dev_priv->mm.flushing_list); | |
1534 | obj_priv->last_rendering_seqno = 0; | |
1535 | } | |
673a394b | 1536 | |
963b4836 CW |
1537 | /* Immediately discard the backing storage */ |
1538 | static void | |
1539 | i915_gem_object_truncate(struct drm_gem_object *obj) | |
1540 | { | |
bb6baf76 CW |
1541 | struct drm_i915_gem_object *obj_priv = obj->driver_private; |
1542 | struct inode *inode; | |
963b4836 | 1543 | |
bb6baf76 CW |
1544 | inode = obj->filp->f_path.dentry->d_inode; |
1545 | if (inode->i_op->truncate) | |
1546 | inode->i_op->truncate (inode); | |
1547 | ||
1548 | obj_priv->madv = __I915_MADV_PURGED; | |
963b4836 CW |
1549 | } |
1550 | ||
1551 | static inline int | |
1552 | i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj_priv) | |
1553 | { | |
1554 | return obj_priv->madv == I915_MADV_DONTNEED; | |
1555 | } | |
1556 | ||
673a394b EA |
1557 | static void |
1558 | i915_gem_object_move_to_inactive(struct drm_gem_object *obj) | |
1559 | { | |
1560 | struct drm_device *dev = obj->dev; | |
1561 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1562 | struct drm_i915_gem_object *obj_priv = obj->driver_private; | |
1563 | ||
1564 | i915_verify_inactive(dev, __FILE__, __LINE__); | |
1565 | if (obj_priv->pin_count != 0) | |
1566 | list_del_init(&obj_priv->list); | |
1567 | else | |
1568 | list_move_tail(&obj_priv->list, &dev_priv->mm.inactive_list); | |
1569 | ||
ce44b0ea | 1570 | obj_priv->last_rendering_seqno = 0; |
673a394b EA |
1571 | if (obj_priv->active) { |
1572 | obj_priv->active = 0; | |
1573 | drm_gem_object_unreference(obj); | |
1574 | } | |
1575 | i915_verify_inactive(dev, __FILE__, __LINE__); | |
1576 | } | |
1577 | ||
1578 | /** | |
1579 | * Creates a new sequence number, emitting a write of it to the status page | |
1580 | * plus an interrupt, which will trigger i915_user_interrupt_handler. | |
1581 | * | |
1582 | * Must be called with struct_lock held. | |
1583 | * | |
1584 | * Returned sequence numbers are nonzero on success. | |
1585 | */ | |
1586 | static uint32_t | |
b962442e EA |
1587 | i915_add_request(struct drm_device *dev, struct drm_file *file_priv, |
1588 | uint32_t flush_domains) | |
673a394b EA |
1589 | { |
1590 | drm_i915_private_t *dev_priv = dev->dev_private; | |
b962442e | 1591 | struct drm_i915_file_private *i915_file_priv = NULL; |
673a394b EA |
1592 | struct drm_i915_gem_request *request; |
1593 | uint32_t seqno; | |
1594 | int was_empty; | |
1595 | RING_LOCALS; | |
1596 | ||
b962442e EA |
1597 | if (file_priv != NULL) |
1598 | i915_file_priv = file_priv->driver_priv; | |
1599 | ||
9a298b2a | 1600 | request = kzalloc(sizeof(*request), GFP_KERNEL); |
673a394b EA |
1601 | if (request == NULL) |
1602 | return 0; | |
1603 | ||
1604 | /* Grab the seqno we're going to make this request be, and bump the | |
1605 | * next (skipping 0 so it can be the reserved no-seqno value). | |
1606 | */ | |
1607 | seqno = dev_priv->mm.next_gem_seqno; | |
1608 | dev_priv->mm.next_gem_seqno++; | |
1609 | if (dev_priv->mm.next_gem_seqno == 0) | |
1610 | dev_priv->mm.next_gem_seqno++; | |
1611 | ||
1612 | BEGIN_LP_RING(4); | |
1613 | OUT_RING(MI_STORE_DWORD_INDEX); | |
1614 | OUT_RING(I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT); | |
1615 | OUT_RING(seqno); | |
1616 | ||
1617 | OUT_RING(MI_USER_INTERRUPT); | |
1618 | ADVANCE_LP_RING(); | |
1619 | ||
1620 | DRM_DEBUG("%d\n", seqno); | |
1621 | ||
1622 | request->seqno = seqno; | |
1623 | request->emitted_jiffies = jiffies; | |
673a394b EA |
1624 | was_empty = list_empty(&dev_priv->mm.request_list); |
1625 | list_add_tail(&request->list, &dev_priv->mm.request_list); | |
b962442e EA |
1626 | if (i915_file_priv) { |
1627 | list_add_tail(&request->client_list, | |
1628 | &i915_file_priv->mm.request_list); | |
1629 | } else { | |
1630 | INIT_LIST_HEAD(&request->client_list); | |
1631 | } | |
673a394b | 1632 | |
ce44b0ea EA |
1633 | /* Associate any objects on the flushing list matching the write |
1634 | * domain we're flushing with our flush. | |
1635 | */ | |
1636 | if (flush_domains != 0) { | |
1637 | struct drm_i915_gem_object *obj_priv, *next; | |
1638 | ||
1639 | list_for_each_entry_safe(obj_priv, next, | |
1640 | &dev_priv->mm.flushing_list, list) { | |
1641 | struct drm_gem_object *obj = obj_priv->obj; | |
1642 | ||
1643 | if ((obj->write_domain & flush_domains) == | |
1644 | obj->write_domain) { | |
1c5d22f7 CW |
1645 | uint32_t old_write_domain = obj->write_domain; |
1646 | ||
ce44b0ea EA |
1647 | obj->write_domain = 0; |
1648 | i915_gem_object_move_to_active(obj, seqno); | |
1c5d22f7 CW |
1649 | |
1650 | trace_i915_gem_object_change_domain(obj, | |
1651 | obj->read_domains, | |
1652 | old_write_domain); | |
ce44b0ea EA |
1653 | } |
1654 | } | |
1655 | ||
1656 | } | |
1657 | ||
f65d9421 BG |
1658 | if (!dev_priv->mm.suspended) { |
1659 | mod_timer(&dev_priv->hangcheck_timer, jiffies + DRM_I915_HANGCHECK_PERIOD); | |
1660 | if (was_empty) | |
1661 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ); | |
1662 | } | |
673a394b EA |
1663 | return seqno; |
1664 | } | |
1665 | ||
1666 | /** | |
1667 | * Command execution barrier | |
1668 | * | |
1669 | * Ensures that all commands in the ring are finished | |
1670 | * before signalling the CPU | |
1671 | */ | |
3043c60c | 1672 | static uint32_t |
673a394b EA |
1673 | i915_retire_commands(struct drm_device *dev) |
1674 | { | |
1675 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1676 | uint32_t cmd = MI_FLUSH | MI_NO_WRITE_FLUSH; | |
1677 | uint32_t flush_domains = 0; | |
1678 | RING_LOCALS; | |
1679 | ||
1680 | /* The sampler always gets flushed on i965 (sigh) */ | |
1681 | if (IS_I965G(dev)) | |
1682 | flush_domains |= I915_GEM_DOMAIN_SAMPLER; | |
1683 | BEGIN_LP_RING(2); | |
1684 | OUT_RING(cmd); | |
1685 | OUT_RING(0); /* noop */ | |
1686 | ADVANCE_LP_RING(); | |
1687 | return flush_domains; | |
1688 | } | |
1689 | ||
1690 | /** | |
1691 | * Moves buffers associated only with the given active seqno from the active | |
1692 | * to inactive list, potentially freeing them. | |
1693 | */ | |
1694 | static void | |
1695 | i915_gem_retire_request(struct drm_device *dev, | |
1696 | struct drm_i915_gem_request *request) | |
1697 | { | |
1698 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1699 | ||
1c5d22f7 CW |
1700 | trace_i915_gem_request_retire(dev, request->seqno); |
1701 | ||
673a394b EA |
1702 | /* Move any buffers on the active list that are no longer referenced |
1703 | * by the ringbuffer to the flushing/inactive lists as appropriate. | |
1704 | */ | |
5e118f41 | 1705 | spin_lock(&dev_priv->mm.active_list_lock); |
673a394b EA |
1706 | while (!list_empty(&dev_priv->mm.active_list)) { |
1707 | struct drm_gem_object *obj; | |
1708 | struct drm_i915_gem_object *obj_priv; | |
1709 | ||
1710 | obj_priv = list_first_entry(&dev_priv->mm.active_list, | |
1711 | struct drm_i915_gem_object, | |
1712 | list); | |
1713 | obj = obj_priv->obj; | |
1714 | ||
1715 | /* If the seqno being retired doesn't match the oldest in the | |
1716 | * list, then the oldest in the list must still be newer than | |
1717 | * this seqno. | |
1718 | */ | |
1719 | if (obj_priv->last_rendering_seqno != request->seqno) | |
5e118f41 | 1720 | goto out; |
de151cf6 | 1721 | |
673a394b EA |
1722 | #if WATCH_LRU |
1723 | DRM_INFO("%s: retire %d moves to inactive list %p\n", | |
1724 | __func__, request->seqno, obj); | |
1725 | #endif | |
1726 | ||
ce44b0ea EA |
1727 | if (obj->write_domain != 0) |
1728 | i915_gem_object_move_to_flushing(obj); | |
68c84342 SL |
1729 | else { |
1730 | /* Take a reference on the object so it won't be | |
1731 | * freed while the spinlock is held. The list | |
1732 | * protection for this spinlock is safe when breaking | |
1733 | * the lock like this since the next thing we do | |
1734 | * is just get the head of the list again. | |
1735 | */ | |
1736 | drm_gem_object_reference(obj); | |
673a394b | 1737 | i915_gem_object_move_to_inactive(obj); |
68c84342 SL |
1738 | spin_unlock(&dev_priv->mm.active_list_lock); |
1739 | drm_gem_object_unreference(obj); | |
1740 | spin_lock(&dev_priv->mm.active_list_lock); | |
1741 | } | |
673a394b | 1742 | } |
5e118f41 CW |
1743 | out: |
1744 | spin_unlock(&dev_priv->mm.active_list_lock); | |
673a394b EA |
1745 | } |
1746 | ||
1747 | /** | |
1748 | * Returns true if seq1 is later than seq2. | |
1749 | */ | |
22be1724 | 1750 | bool |
673a394b EA |
1751 | i915_seqno_passed(uint32_t seq1, uint32_t seq2) |
1752 | { | |
1753 | return (int32_t)(seq1 - seq2) >= 0; | |
1754 | } | |
1755 | ||
1756 | uint32_t | |
1757 | i915_get_gem_seqno(struct drm_device *dev) | |
1758 | { | |
1759 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1760 | ||
1761 | return READ_HWSP(dev_priv, I915_GEM_HWS_INDEX); | |
1762 | } | |
1763 | ||
1764 | /** | |
1765 | * This function clears the request list as sequence numbers are passed. | |
1766 | */ | |
1767 | void | |
1768 | i915_gem_retire_requests(struct drm_device *dev) | |
1769 | { | |
1770 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1771 | uint32_t seqno; | |
1772 | ||
6c0594a3 KW |
1773 | if (!dev_priv->hw_status_page) |
1774 | return; | |
1775 | ||
673a394b EA |
1776 | seqno = i915_get_gem_seqno(dev); |
1777 | ||
1778 | while (!list_empty(&dev_priv->mm.request_list)) { | |
1779 | struct drm_i915_gem_request *request; | |
1780 | uint32_t retiring_seqno; | |
1781 | ||
1782 | request = list_first_entry(&dev_priv->mm.request_list, | |
1783 | struct drm_i915_gem_request, | |
1784 | list); | |
1785 | retiring_seqno = request->seqno; | |
1786 | ||
1787 | if (i915_seqno_passed(seqno, retiring_seqno) || | |
ba1234d1 | 1788 | atomic_read(&dev_priv->mm.wedged)) { |
673a394b EA |
1789 | i915_gem_retire_request(dev, request); |
1790 | ||
1791 | list_del(&request->list); | |
b962442e | 1792 | list_del(&request->client_list); |
9a298b2a | 1793 | kfree(request); |
673a394b EA |
1794 | } else |
1795 | break; | |
1796 | } | |
1797 | } | |
1798 | ||
1799 | void | |
1800 | i915_gem_retire_work_handler(struct work_struct *work) | |
1801 | { | |
1802 | drm_i915_private_t *dev_priv; | |
1803 | struct drm_device *dev; | |
1804 | ||
1805 | dev_priv = container_of(work, drm_i915_private_t, | |
1806 | mm.retire_work.work); | |
1807 | dev = dev_priv->dev; | |
1808 | ||
1809 | mutex_lock(&dev->struct_mutex); | |
1810 | i915_gem_retire_requests(dev); | |
6dbe2772 KP |
1811 | if (!dev_priv->mm.suspended && |
1812 | !list_empty(&dev_priv->mm.request_list)) | |
9c9fe1f8 | 1813 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ); |
673a394b EA |
1814 | mutex_unlock(&dev->struct_mutex); |
1815 | } | |
1816 | ||
1817 | /** | |
1818 | * Waits for a sequence number to be signaled, and cleans up the | |
1819 | * request and object lists appropriately for that event. | |
1820 | */ | |
3043c60c | 1821 | static int |
673a394b EA |
1822 | i915_wait_request(struct drm_device *dev, uint32_t seqno) |
1823 | { | |
1824 | drm_i915_private_t *dev_priv = dev->dev_private; | |
802c7eb6 | 1825 | u32 ier; |
673a394b EA |
1826 | int ret = 0; |
1827 | ||
1828 | BUG_ON(seqno == 0); | |
1829 | ||
ba1234d1 | 1830 | if (atomic_read(&dev_priv->mm.wedged)) |
ffed1d09 BG |
1831 | return -EIO; |
1832 | ||
673a394b | 1833 | if (!i915_seqno_passed(i915_get_gem_seqno(dev), seqno)) { |
036a4a7d ZW |
1834 | if (IS_IGDNG(dev)) |
1835 | ier = I915_READ(DEIER) | I915_READ(GTIER); | |
1836 | else | |
1837 | ier = I915_READ(IER); | |
802c7eb6 JB |
1838 | if (!ier) { |
1839 | DRM_ERROR("something (likely vbetool) disabled " | |
1840 | "interrupts, re-enabling\n"); | |
1841 | i915_driver_irq_preinstall(dev); | |
1842 | i915_driver_irq_postinstall(dev); | |
1843 | } | |
1844 | ||
1c5d22f7 CW |
1845 | trace_i915_gem_request_wait_begin(dev, seqno); |
1846 | ||
673a394b EA |
1847 | dev_priv->mm.waiting_gem_seqno = seqno; |
1848 | i915_user_irq_get(dev); | |
1849 | ret = wait_event_interruptible(dev_priv->irq_queue, | |
1850 | i915_seqno_passed(i915_get_gem_seqno(dev), | |
1851 | seqno) || | |
ba1234d1 | 1852 | atomic_read(&dev_priv->mm.wedged)); |
673a394b EA |
1853 | i915_user_irq_put(dev); |
1854 | dev_priv->mm.waiting_gem_seqno = 0; | |
1c5d22f7 CW |
1855 | |
1856 | trace_i915_gem_request_wait_end(dev, seqno); | |
673a394b | 1857 | } |
ba1234d1 | 1858 | if (atomic_read(&dev_priv->mm.wedged)) |
673a394b EA |
1859 | ret = -EIO; |
1860 | ||
1861 | if (ret && ret != -ERESTARTSYS) | |
1862 | DRM_ERROR("%s returns %d (awaiting %d at %d)\n", | |
1863 | __func__, ret, seqno, i915_get_gem_seqno(dev)); | |
1864 | ||
1865 | /* Directly dispatch request retiring. While we have the work queue | |
1866 | * to handle this, the waiter on a request often wants an associated | |
1867 | * buffer to have made it to the inactive list, and we would need | |
1868 | * a separate wait queue to handle that. | |
1869 | */ | |
1870 | if (ret == 0) | |
1871 | i915_gem_retire_requests(dev); | |
1872 | ||
1873 | return ret; | |
1874 | } | |
1875 | ||
1876 | static void | |
1877 | i915_gem_flush(struct drm_device *dev, | |
1878 | uint32_t invalidate_domains, | |
1879 | uint32_t flush_domains) | |
1880 | { | |
1881 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1882 | uint32_t cmd; | |
1883 | RING_LOCALS; | |
1884 | ||
1885 | #if WATCH_EXEC | |
1886 | DRM_INFO("%s: invalidate %08x flush %08x\n", __func__, | |
1887 | invalidate_domains, flush_domains); | |
1888 | #endif | |
1c5d22f7 CW |
1889 | trace_i915_gem_request_flush(dev, dev_priv->mm.next_gem_seqno, |
1890 | invalidate_domains, flush_domains); | |
673a394b EA |
1891 | |
1892 | if (flush_domains & I915_GEM_DOMAIN_CPU) | |
1893 | drm_agp_chipset_flush(dev); | |
1894 | ||
21d509e3 | 1895 | if ((invalidate_domains | flush_domains) & I915_GEM_GPU_DOMAINS) { |
673a394b EA |
1896 | /* |
1897 | * read/write caches: | |
1898 | * | |
1899 | * I915_GEM_DOMAIN_RENDER is always invalidated, but is | |
1900 | * only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is | |
1901 | * also flushed at 2d versus 3d pipeline switches. | |
1902 | * | |
1903 | * read-only caches: | |
1904 | * | |
1905 | * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if | |
1906 | * MI_READ_FLUSH is set, and is always flushed on 965. | |
1907 | * | |
1908 | * I915_GEM_DOMAIN_COMMAND may not exist? | |
1909 | * | |
1910 | * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is | |
1911 | * invalidated when MI_EXE_FLUSH is set. | |
1912 | * | |
1913 | * I915_GEM_DOMAIN_VERTEX, which exists on 965, is | |
1914 | * invalidated with every MI_FLUSH. | |
1915 | * | |
1916 | * TLBs: | |
1917 | * | |
1918 | * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND | |
1919 | * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and | |
1920 | * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER | |
1921 | * are flushed at any MI_FLUSH. | |
1922 | */ | |
1923 | ||
1924 | cmd = MI_FLUSH | MI_NO_WRITE_FLUSH; | |
1925 | if ((invalidate_domains|flush_domains) & | |
1926 | I915_GEM_DOMAIN_RENDER) | |
1927 | cmd &= ~MI_NO_WRITE_FLUSH; | |
1928 | if (!IS_I965G(dev)) { | |
1929 | /* | |
1930 | * On the 965, the sampler cache always gets flushed | |
1931 | * and this bit is reserved. | |
1932 | */ | |
1933 | if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER) | |
1934 | cmd |= MI_READ_FLUSH; | |
1935 | } | |
1936 | if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION) | |
1937 | cmd |= MI_EXE_FLUSH; | |
1938 | ||
1939 | #if WATCH_EXEC | |
1940 | DRM_INFO("%s: queue flush %08x to ring\n", __func__, cmd); | |
1941 | #endif | |
1942 | BEGIN_LP_RING(2); | |
1943 | OUT_RING(cmd); | |
1944 | OUT_RING(0); /* noop */ | |
1945 | ADVANCE_LP_RING(); | |
1946 | } | |
1947 | } | |
1948 | ||
1949 | /** | |
1950 | * Ensures that all rendering to the object has completed and the object is | |
1951 | * safe to unbind from the GTT or access from the CPU. | |
1952 | */ | |
1953 | static int | |
1954 | i915_gem_object_wait_rendering(struct drm_gem_object *obj) | |
1955 | { | |
1956 | struct drm_device *dev = obj->dev; | |
1957 | struct drm_i915_gem_object *obj_priv = obj->driver_private; | |
1958 | int ret; | |
1959 | ||
e47c68e9 EA |
1960 | /* This function only exists to support waiting for existing rendering, |
1961 | * not for emitting required flushes. | |
673a394b | 1962 | */ |
e47c68e9 | 1963 | BUG_ON((obj->write_domain & I915_GEM_GPU_DOMAINS) != 0); |
673a394b EA |
1964 | |
1965 | /* If there is rendering queued on the buffer being evicted, wait for | |
1966 | * it. | |
1967 | */ | |
1968 | if (obj_priv->active) { | |
1969 | #if WATCH_BUF | |
1970 | DRM_INFO("%s: object %p wait for seqno %08x\n", | |
1971 | __func__, obj, obj_priv->last_rendering_seqno); | |
1972 | #endif | |
1973 | ret = i915_wait_request(dev, obj_priv->last_rendering_seqno); | |
1974 | if (ret != 0) | |
1975 | return ret; | |
1976 | } | |
1977 | ||
1978 | return 0; | |
1979 | } | |
1980 | ||
1981 | /** | |
1982 | * Unbinds an object from the GTT aperture. | |
1983 | */ | |
0f973f27 | 1984 | int |
673a394b EA |
1985 | i915_gem_object_unbind(struct drm_gem_object *obj) |
1986 | { | |
1987 | struct drm_device *dev = obj->dev; | |
1988 | struct drm_i915_gem_object *obj_priv = obj->driver_private; | |
1989 | int ret = 0; | |
1990 | ||
1991 | #if WATCH_BUF | |
1992 | DRM_INFO("%s:%d %p\n", __func__, __LINE__, obj); | |
1993 | DRM_INFO("gtt_space %p\n", obj_priv->gtt_space); | |
1994 | #endif | |
1995 | if (obj_priv->gtt_space == NULL) | |
1996 | return 0; | |
1997 | ||
1998 | if (obj_priv->pin_count != 0) { | |
1999 | DRM_ERROR("Attempting to unbind pinned buffer\n"); | |
2000 | return -EINVAL; | |
2001 | } | |
2002 | ||
5323fd04 EA |
2003 | /* blow away mappings if mapped through GTT */ |
2004 | i915_gem_release_mmap(obj); | |
2005 | ||
2006 | if (obj_priv->fence_reg != I915_FENCE_REG_NONE) | |
2007 | i915_gem_clear_fence_reg(obj); | |
2008 | ||
673a394b EA |
2009 | /* Move the object to the CPU domain to ensure that |
2010 | * any possible CPU writes while it's not in the GTT | |
2011 | * are flushed when we go to remap it. This will | |
2012 | * also ensure that all pending GPU writes are finished | |
2013 | * before we unbind. | |
2014 | */ | |
e47c68e9 | 2015 | ret = i915_gem_object_set_to_cpu_domain(obj, 1); |
673a394b | 2016 | if (ret) { |
e47c68e9 EA |
2017 | if (ret != -ERESTARTSYS) |
2018 | DRM_ERROR("set_domain failed: %d\n", ret); | |
673a394b EA |
2019 | return ret; |
2020 | } | |
2021 | ||
5323fd04 EA |
2022 | BUG_ON(obj_priv->active); |
2023 | ||
673a394b EA |
2024 | if (obj_priv->agp_mem != NULL) { |
2025 | drm_unbind_agp(obj_priv->agp_mem); | |
2026 | drm_free_agp(obj_priv->agp_mem, obj->size / PAGE_SIZE); | |
2027 | obj_priv->agp_mem = NULL; | |
2028 | } | |
2029 | ||
856fa198 | 2030 | i915_gem_object_put_pages(obj); |
a32808c0 | 2031 | BUG_ON(obj_priv->pages_refcount); |
673a394b EA |
2032 | |
2033 | if (obj_priv->gtt_space) { | |
2034 | atomic_dec(&dev->gtt_count); | |
2035 | atomic_sub(obj->size, &dev->gtt_memory); | |
2036 | ||
2037 | drm_mm_put_block(obj_priv->gtt_space); | |
2038 | obj_priv->gtt_space = NULL; | |
2039 | } | |
2040 | ||
2041 | /* Remove ourselves from the LRU list if present. */ | |
2042 | if (!list_empty(&obj_priv->list)) | |
2043 | list_del_init(&obj_priv->list); | |
2044 | ||
963b4836 CW |
2045 | if (i915_gem_object_is_purgeable(obj_priv)) |
2046 | i915_gem_object_truncate(obj); | |
2047 | ||
1c5d22f7 CW |
2048 | trace_i915_gem_object_unbind(obj); |
2049 | ||
673a394b EA |
2050 | return 0; |
2051 | } | |
2052 | ||
07f73f69 CW |
2053 | static struct drm_gem_object * |
2054 | i915_gem_find_inactive_object(struct drm_device *dev, int min_size) | |
2055 | { | |
2056 | drm_i915_private_t *dev_priv = dev->dev_private; | |
2057 | struct drm_i915_gem_object *obj_priv; | |
2058 | struct drm_gem_object *best = NULL; | |
2059 | struct drm_gem_object *first = NULL; | |
2060 | ||
2061 | /* Try to find the smallest clean object */ | |
2062 | list_for_each_entry(obj_priv, &dev_priv->mm.inactive_list, list) { | |
2063 | struct drm_gem_object *obj = obj_priv->obj; | |
2064 | if (obj->size >= min_size) { | |
963b4836 CW |
2065 | if ((!obj_priv->dirty || |
2066 | i915_gem_object_is_purgeable(obj_priv)) && | |
07f73f69 CW |
2067 | (!best || obj->size < best->size)) { |
2068 | best = obj; | |
2069 | if (best->size == min_size) | |
2070 | return best; | |
2071 | } | |
2072 | if (!first) | |
2073 | first = obj; | |
2074 | } | |
2075 | } | |
2076 | ||
2077 | return best ? best : first; | |
2078 | } | |
2079 | ||
673a394b | 2080 | static int |
07f73f69 CW |
2081 | i915_gem_evict_everything(struct drm_device *dev) |
2082 | { | |
2083 | drm_i915_private_t *dev_priv = dev->dev_private; | |
2084 | uint32_t seqno; | |
2085 | int ret; | |
2086 | bool lists_empty; | |
2087 | ||
07f73f69 CW |
2088 | spin_lock(&dev_priv->mm.active_list_lock); |
2089 | lists_empty = (list_empty(&dev_priv->mm.inactive_list) && | |
2090 | list_empty(&dev_priv->mm.flushing_list) && | |
2091 | list_empty(&dev_priv->mm.active_list)); | |
2092 | spin_unlock(&dev_priv->mm.active_list_lock); | |
2093 | ||
9731129c | 2094 | if (lists_empty) |
07f73f69 | 2095 | return -ENOSPC; |
07f73f69 CW |
2096 | |
2097 | /* Flush everything (on to the inactive lists) and evict */ | |
2098 | i915_gem_flush(dev, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS); | |
2099 | seqno = i915_add_request(dev, NULL, I915_GEM_GPU_DOMAINS); | |
2100 | if (seqno == 0) | |
2101 | return -ENOMEM; | |
2102 | ||
2103 | ret = i915_wait_request(dev, seqno); | |
2104 | if (ret) | |
2105 | return ret; | |
2106 | ||
ab5ee576 | 2107 | ret = i915_gem_evict_from_inactive_list(dev); |
07f73f69 CW |
2108 | if (ret) |
2109 | return ret; | |
2110 | ||
2111 | spin_lock(&dev_priv->mm.active_list_lock); | |
2112 | lists_empty = (list_empty(&dev_priv->mm.inactive_list) && | |
2113 | list_empty(&dev_priv->mm.flushing_list) && | |
2114 | list_empty(&dev_priv->mm.active_list)); | |
2115 | spin_unlock(&dev_priv->mm.active_list_lock); | |
2116 | BUG_ON(!lists_empty); | |
2117 | ||
2118 | return 0; | |
2119 | } | |
2120 | ||
673a394b | 2121 | static int |
07f73f69 | 2122 | i915_gem_evict_something(struct drm_device *dev, int min_size) |
673a394b EA |
2123 | { |
2124 | drm_i915_private_t *dev_priv = dev->dev_private; | |
2125 | struct drm_gem_object *obj; | |
07f73f69 | 2126 | int ret; |
673a394b EA |
2127 | |
2128 | for (;;) { | |
07f73f69 CW |
2129 | i915_gem_retire_requests(dev); |
2130 | ||
673a394b EA |
2131 | /* If there's an inactive buffer available now, grab it |
2132 | * and be done. | |
2133 | */ | |
07f73f69 CW |
2134 | obj = i915_gem_find_inactive_object(dev, min_size); |
2135 | if (obj) { | |
2136 | struct drm_i915_gem_object *obj_priv; | |
2137 | ||
673a394b EA |
2138 | #if WATCH_LRU |
2139 | DRM_INFO("%s: evicting %p\n", __func__, obj); | |
2140 | #endif | |
07f73f69 CW |
2141 | obj_priv = obj->driver_private; |
2142 | BUG_ON(obj_priv->pin_count != 0); | |
673a394b EA |
2143 | BUG_ON(obj_priv->active); |
2144 | ||
2145 | /* Wait on the rendering and unbind the buffer. */ | |
07f73f69 | 2146 | return i915_gem_object_unbind(obj); |
673a394b EA |
2147 | } |
2148 | ||
2149 | /* If we didn't get anything, but the ring is still processing | |
07f73f69 CW |
2150 | * things, wait for the next to finish and hopefully leave us |
2151 | * a buffer to evict. | |
673a394b EA |
2152 | */ |
2153 | if (!list_empty(&dev_priv->mm.request_list)) { | |
2154 | struct drm_i915_gem_request *request; | |
2155 | ||
2156 | request = list_first_entry(&dev_priv->mm.request_list, | |
2157 | struct drm_i915_gem_request, | |
2158 | list); | |
2159 | ||
2160 | ret = i915_wait_request(dev, request->seqno); | |
2161 | if (ret) | |
07f73f69 | 2162 | return ret; |
673a394b | 2163 | |
07f73f69 | 2164 | continue; |
673a394b EA |
2165 | } |
2166 | ||
2167 | /* If we didn't have anything on the request list but there | |
2168 | * are buffers awaiting a flush, emit one and try again. | |
2169 | * When we wait on it, those buffers waiting for that flush | |
2170 | * will get moved to inactive. | |
2171 | */ | |
2172 | if (!list_empty(&dev_priv->mm.flushing_list)) { | |
07f73f69 | 2173 | struct drm_i915_gem_object *obj_priv; |
673a394b | 2174 | |
9a1e2582 CW |
2175 | /* Find an object that we can immediately reuse */ |
2176 | list_for_each_entry(obj_priv, &dev_priv->mm.flushing_list, list) { | |
2177 | obj = obj_priv->obj; | |
2178 | if (obj->size >= min_size) | |
2179 | break; | |
673a394b | 2180 | |
9a1e2582 CW |
2181 | obj = NULL; |
2182 | } | |
673a394b | 2183 | |
9a1e2582 CW |
2184 | if (obj != NULL) { |
2185 | uint32_t seqno; | |
673a394b | 2186 | |
9a1e2582 CW |
2187 | i915_gem_flush(dev, |
2188 | obj->write_domain, | |
2189 | obj->write_domain); | |
2190 | seqno = i915_add_request(dev, NULL, obj->write_domain); | |
2191 | if (seqno == 0) | |
2192 | return -ENOMEM; | |
ac94a962 | 2193 | |
9a1e2582 CW |
2194 | ret = i915_wait_request(dev, seqno); |
2195 | if (ret) | |
2196 | return ret; | |
2197 | ||
2198 | continue; | |
2199 | } | |
673a394b EA |
2200 | } |
2201 | ||
07f73f69 CW |
2202 | /* If we didn't do any of the above, there's no single buffer |
2203 | * large enough to swap out for the new one, so just evict | |
2204 | * everything and start again. (This should be rare.) | |
673a394b | 2205 | */ |
9731129c | 2206 | if (!list_empty (&dev_priv->mm.inactive_list)) |
ab5ee576 | 2207 | return i915_gem_evict_from_inactive_list(dev); |
9731129c | 2208 | else |
07f73f69 | 2209 | return i915_gem_evict_everything(dev); |
ac94a962 | 2210 | } |
ac94a962 KP |
2211 | } |
2212 | ||
6911a9b8 | 2213 | int |
856fa198 | 2214 | i915_gem_object_get_pages(struct drm_gem_object *obj) |
673a394b EA |
2215 | { |
2216 | struct drm_i915_gem_object *obj_priv = obj->driver_private; | |
2217 | int page_count, i; | |
2218 | struct address_space *mapping; | |
2219 | struct inode *inode; | |
2220 | struct page *page; | |
2221 | int ret; | |
2222 | ||
856fa198 | 2223 | if (obj_priv->pages_refcount++ != 0) |
673a394b EA |
2224 | return 0; |
2225 | ||
2226 | /* Get the list of pages out of our struct file. They'll be pinned | |
2227 | * at this point until we release them. | |
2228 | */ | |
2229 | page_count = obj->size / PAGE_SIZE; | |
856fa198 | 2230 | BUG_ON(obj_priv->pages != NULL); |
8e7d2b2c | 2231 | obj_priv->pages = drm_calloc_large(page_count, sizeof(struct page *)); |
856fa198 | 2232 | if (obj_priv->pages == NULL) { |
856fa198 | 2233 | obj_priv->pages_refcount--; |
673a394b EA |
2234 | return -ENOMEM; |
2235 | } | |
2236 | ||
2237 | inode = obj->filp->f_path.dentry->d_inode; | |
2238 | mapping = inode->i_mapping; | |
2239 | for (i = 0; i < page_count; i++) { | |
2240 | page = read_mapping_page(mapping, i, NULL); | |
2241 | if (IS_ERR(page)) { | |
2242 | ret = PTR_ERR(page); | |
856fa198 | 2243 | i915_gem_object_put_pages(obj); |
673a394b EA |
2244 | return ret; |
2245 | } | |
856fa198 | 2246 | obj_priv->pages[i] = page; |
673a394b | 2247 | } |
280b713b EA |
2248 | |
2249 | if (obj_priv->tiling_mode != I915_TILING_NONE) | |
2250 | i915_gem_object_do_bit_17_swizzle(obj); | |
2251 | ||
673a394b EA |
2252 | return 0; |
2253 | } | |
2254 | ||
de151cf6 JB |
2255 | static void i965_write_fence_reg(struct drm_i915_fence_reg *reg) |
2256 | { | |
2257 | struct drm_gem_object *obj = reg->obj; | |
2258 | struct drm_device *dev = obj->dev; | |
2259 | drm_i915_private_t *dev_priv = dev->dev_private; | |
2260 | struct drm_i915_gem_object *obj_priv = obj->driver_private; | |
2261 | int regnum = obj_priv->fence_reg; | |
2262 | uint64_t val; | |
2263 | ||
2264 | val = (uint64_t)((obj_priv->gtt_offset + obj->size - 4096) & | |
2265 | 0xfffff000) << 32; | |
2266 | val |= obj_priv->gtt_offset & 0xfffff000; | |
2267 | val |= ((obj_priv->stride / 128) - 1) << I965_FENCE_PITCH_SHIFT; | |
2268 | if (obj_priv->tiling_mode == I915_TILING_Y) | |
2269 | val |= 1 << I965_FENCE_TILING_Y_SHIFT; | |
2270 | val |= I965_FENCE_REG_VALID; | |
2271 | ||
2272 | I915_WRITE64(FENCE_REG_965_0 + (regnum * 8), val); | |
2273 | } | |
2274 | ||
2275 | static void i915_write_fence_reg(struct drm_i915_fence_reg *reg) | |
2276 | { | |
2277 | struct drm_gem_object *obj = reg->obj; | |
2278 | struct drm_device *dev = obj->dev; | |
2279 | drm_i915_private_t *dev_priv = dev->dev_private; | |
2280 | struct drm_i915_gem_object *obj_priv = obj->driver_private; | |
2281 | int regnum = obj_priv->fence_reg; | |
0f973f27 | 2282 | int tile_width; |
dc529a4f | 2283 | uint32_t fence_reg, val; |
de151cf6 JB |
2284 | uint32_t pitch_val; |
2285 | ||
2286 | if ((obj_priv->gtt_offset & ~I915_FENCE_START_MASK) || | |
2287 | (obj_priv->gtt_offset & (obj->size - 1))) { | |
f06da264 | 2288 | WARN(1, "%s: object 0x%08x not 1M or size (0x%zx) aligned\n", |
0f973f27 | 2289 | __func__, obj_priv->gtt_offset, obj->size); |
de151cf6 JB |
2290 | return; |
2291 | } | |
2292 | ||
0f973f27 JB |
2293 | if (obj_priv->tiling_mode == I915_TILING_Y && |
2294 | HAS_128_BYTE_Y_TILING(dev)) | |
2295 | tile_width = 128; | |
de151cf6 | 2296 | else |
0f973f27 JB |
2297 | tile_width = 512; |
2298 | ||
2299 | /* Note: pitch better be a power of two tile widths */ | |
2300 | pitch_val = obj_priv->stride / tile_width; | |
2301 | pitch_val = ffs(pitch_val) - 1; | |
de151cf6 JB |
2302 | |
2303 | val = obj_priv->gtt_offset; | |
2304 | if (obj_priv->tiling_mode == I915_TILING_Y) | |
2305 | val |= 1 << I830_FENCE_TILING_Y_SHIFT; | |
2306 | val |= I915_FENCE_SIZE_BITS(obj->size); | |
2307 | val |= pitch_val << I830_FENCE_PITCH_SHIFT; | |
2308 | val |= I830_FENCE_REG_VALID; | |
2309 | ||
dc529a4f EA |
2310 | if (regnum < 8) |
2311 | fence_reg = FENCE_REG_830_0 + (regnum * 4); | |
2312 | else | |
2313 | fence_reg = FENCE_REG_945_8 + ((regnum - 8) * 4); | |
2314 | I915_WRITE(fence_reg, val); | |
de151cf6 JB |
2315 | } |
2316 | ||
2317 | static void i830_write_fence_reg(struct drm_i915_fence_reg *reg) | |
2318 | { | |
2319 | struct drm_gem_object *obj = reg->obj; | |
2320 | struct drm_device *dev = obj->dev; | |
2321 | drm_i915_private_t *dev_priv = dev->dev_private; | |
2322 | struct drm_i915_gem_object *obj_priv = obj->driver_private; | |
2323 | int regnum = obj_priv->fence_reg; | |
2324 | uint32_t val; | |
2325 | uint32_t pitch_val; | |
8d7773a3 | 2326 | uint32_t fence_size_bits; |
de151cf6 | 2327 | |
8d7773a3 | 2328 | if ((obj_priv->gtt_offset & ~I830_FENCE_START_MASK) || |
de151cf6 | 2329 | (obj_priv->gtt_offset & (obj->size - 1))) { |
8d7773a3 | 2330 | WARN(1, "%s: object 0x%08x not 512K or size aligned\n", |
0f973f27 | 2331 | __func__, obj_priv->gtt_offset); |
de151cf6 JB |
2332 | return; |
2333 | } | |
2334 | ||
e76a16de EA |
2335 | pitch_val = obj_priv->stride / 128; |
2336 | pitch_val = ffs(pitch_val) - 1; | |
2337 | WARN_ON(pitch_val > I830_FENCE_MAX_PITCH_VAL); | |
2338 | ||
de151cf6 JB |
2339 | val = obj_priv->gtt_offset; |
2340 | if (obj_priv->tiling_mode == I915_TILING_Y) | |
2341 | val |= 1 << I830_FENCE_TILING_Y_SHIFT; | |
8d7773a3 DV |
2342 | fence_size_bits = I830_FENCE_SIZE_BITS(obj->size); |
2343 | WARN_ON(fence_size_bits & ~0x00000f00); | |
2344 | val |= fence_size_bits; | |
de151cf6 JB |
2345 | val |= pitch_val << I830_FENCE_PITCH_SHIFT; |
2346 | val |= I830_FENCE_REG_VALID; | |
2347 | ||
2348 | I915_WRITE(FENCE_REG_830_0 + (regnum * 4), val); | |
de151cf6 JB |
2349 | } |
2350 | ||
2351 | /** | |
2352 | * i915_gem_object_get_fence_reg - set up a fence reg for an object | |
2353 | * @obj: object to map through a fence reg | |
2354 | * | |
2355 | * When mapping objects through the GTT, userspace wants to be able to write | |
2356 | * to them without having to worry about swizzling if the object is tiled. | |
2357 | * | |
2358 | * This function walks the fence regs looking for a free one for @obj, | |
2359 | * stealing one if it can't find any. | |
2360 | * | |
2361 | * It then sets up the reg based on the object's properties: address, pitch | |
2362 | * and tiling format. | |
2363 | */ | |
8c4b8c3f CW |
2364 | int |
2365 | i915_gem_object_get_fence_reg(struct drm_gem_object *obj) | |
de151cf6 JB |
2366 | { |
2367 | struct drm_device *dev = obj->dev; | |
79e53945 | 2368 | struct drm_i915_private *dev_priv = dev->dev_private; |
de151cf6 JB |
2369 | struct drm_i915_gem_object *obj_priv = obj->driver_private; |
2370 | struct drm_i915_fence_reg *reg = NULL; | |
fc7170ba CW |
2371 | struct drm_i915_gem_object *old_obj_priv = NULL; |
2372 | int i, ret, avail; | |
de151cf6 | 2373 | |
a09ba7fa EA |
2374 | /* Just update our place in the LRU if our fence is getting used. */ |
2375 | if (obj_priv->fence_reg != I915_FENCE_REG_NONE) { | |
2376 | list_move_tail(&obj_priv->fence_list, &dev_priv->mm.fence_list); | |
2377 | return 0; | |
2378 | } | |
2379 | ||
de151cf6 JB |
2380 | switch (obj_priv->tiling_mode) { |
2381 | case I915_TILING_NONE: | |
2382 | WARN(1, "allocating a fence for non-tiled object?\n"); | |
2383 | break; | |
2384 | case I915_TILING_X: | |
0f973f27 JB |
2385 | if (!obj_priv->stride) |
2386 | return -EINVAL; | |
2387 | WARN((obj_priv->stride & (512 - 1)), | |
2388 | "object 0x%08x is X tiled but has non-512B pitch\n", | |
2389 | obj_priv->gtt_offset); | |
de151cf6 JB |
2390 | break; |
2391 | case I915_TILING_Y: | |
0f973f27 JB |
2392 | if (!obj_priv->stride) |
2393 | return -EINVAL; | |
2394 | WARN((obj_priv->stride & (128 - 1)), | |
2395 | "object 0x%08x is Y tiled but has non-128B pitch\n", | |
2396 | obj_priv->gtt_offset); | |
de151cf6 JB |
2397 | break; |
2398 | } | |
2399 | ||
2400 | /* First try to find a free reg */ | |
fc7170ba | 2401 | avail = 0; |
de151cf6 JB |
2402 | for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) { |
2403 | reg = &dev_priv->fence_regs[i]; | |
2404 | if (!reg->obj) | |
2405 | break; | |
fc7170ba CW |
2406 | |
2407 | old_obj_priv = reg->obj->driver_private; | |
2408 | if (!old_obj_priv->pin_count) | |
2409 | avail++; | |
de151cf6 JB |
2410 | } |
2411 | ||
2412 | /* None available, try to steal one or wait for a user to finish */ | |
2413 | if (i == dev_priv->num_fence_regs) { | |
a09ba7fa | 2414 | struct drm_gem_object *old_obj = NULL; |
de151cf6 | 2415 | |
fc7170ba | 2416 | if (avail == 0) |
2939e1f5 | 2417 | return -ENOSPC; |
fc7170ba | 2418 | |
a09ba7fa EA |
2419 | list_for_each_entry(old_obj_priv, &dev_priv->mm.fence_list, |
2420 | fence_list) { | |
2421 | old_obj = old_obj_priv->obj; | |
d7619c4b | 2422 | |
d7619c4b CW |
2423 | if (old_obj_priv->pin_count) |
2424 | continue; | |
2425 | ||
a09ba7fa EA |
2426 | /* Take a reference, as otherwise the wait_rendering |
2427 | * below may cause the object to get freed out from | |
2428 | * under us. | |
2429 | */ | |
2430 | drm_gem_object_reference(old_obj); | |
2431 | ||
d7619c4b CW |
2432 | /* i915 uses fences for GPU access to tiled buffers */ |
2433 | if (IS_I965G(dev) || !old_obj_priv->active) | |
de151cf6 | 2434 | break; |
d7619c4b | 2435 | |
a09ba7fa EA |
2436 | /* This brings the object to the head of the LRU if it |
2437 | * had been written to. The only way this should | |
2438 | * result in us waiting longer than the expected | |
2439 | * optimal amount of time is if there was a | |
2440 | * fence-using buffer later that was read-only. | |
2441 | */ | |
2442 | i915_gem_object_flush_gpu_write_domain(old_obj); | |
2443 | ret = i915_gem_object_wait_rendering(old_obj); | |
58c2fb64 CW |
2444 | if (ret != 0) { |
2445 | drm_gem_object_unreference(old_obj); | |
d7619c4b | 2446 | return ret; |
58c2fb64 CW |
2447 | } |
2448 | ||
a09ba7fa | 2449 | break; |
de151cf6 JB |
2450 | } |
2451 | ||
2452 | /* | |
2453 | * Zap this virtual mapping so we can set up a fence again | |
2454 | * for this object next time we need it. | |
2455 | */ | |
58c2fb64 CW |
2456 | i915_gem_release_mmap(old_obj); |
2457 | ||
a09ba7fa | 2458 | i = old_obj_priv->fence_reg; |
58c2fb64 CW |
2459 | reg = &dev_priv->fence_regs[i]; |
2460 | ||
de151cf6 | 2461 | old_obj_priv->fence_reg = I915_FENCE_REG_NONE; |
a09ba7fa | 2462 | list_del_init(&old_obj_priv->fence_list); |
58c2fb64 | 2463 | |
a09ba7fa | 2464 | drm_gem_object_unreference(old_obj); |
de151cf6 JB |
2465 | } |
2466 | ||
2467 | obj_priv->fence_reg = i; | |
a09ba7fa EA |
2468 | list_add_tail(&obj_priv->fence_list, &dev_priv->mm.fence_list); |
2469 | ||
de151cf6 JB |
2470 | reg->obj = obj; |
2471 | ||
2472 | if (IS_I965G(dev)) | |
2473 | i965_write_fence_reg(reg); | |
2474 | else if (IS_I9XX(dev)) | |
2475 | i915_write_fence_reg(reg); | |
2476 | else | |
2477 | i830_write_fence_reg(reg); | |
d9ddcb96 | 2478 | |
1c5d22f7 CW |
2479 | trace_i915_gem_object_get_fence(obj, i, obj_priv->tiling_mode); |
2480 | ||
d9ddcb96 | 2481 | return 0; |
de151cf6 JB |
2482 | } |
2483 | ||
2484 | /** | |
2485 | * i915_gem_clear_fence_reg - clear out fence register info | |
2486 | * @obj: object to clear | |
2487 | * | |
2488 | * Zeroes out the fence register itself and clears out the associated | |
2489 | * data structures in dev_priv and obj_priv. | |
2490 | */ | |
2491 | static void | |
2492 | i915_gem_clear_fence_reg(struct drm_gem_object *obj) | |
2493 | { | |
2494 | struct drm_device *dev = obj->dev; | |
79e53945 | 2495 | drm_i915_private_t *dev_priv = dev->dev_private; |
de151cf6 JB |
2496 | struct drm_i915_gem_object *obj_priv = obj->driver_private; |
2497 | ||
2498 | if (IS_I965G(dev)) | |
2499 | I915_WRITE64(FENCE_REG_965_0 + (obj_priv->fence_reg * 8), 0); | |
dc529a4f EA |
2500 | else { |
2501 | uint32_t fence_reg; | |
2502 | ||
2503 | if (obj_priv->fence_reg < 8) | |
2504 | fence_reg = FENCE_REG_830_0 + obj_priv->fence_reg * 4; | |
2505 | else | |
2506 | fence_reg = FENCE_REG_945_8 + (obj_priv->fence_reg - | |
2507 | 8) * 4; | |
2508 | ||
2509 | I915_WRITE(fence_reg, 0); | |
2510 | } | |
de151cf6 JB |
2511 | |
2512 | dev_priv->fence_regs[obj_priv->fence_reg].obj = NULL; | |
2513 | obj_priv->fence_reg = I915_FENCE_REG_NONE; | |
a09ba7fa | 2514 | list_del_init(&obj_priv->fence_list); |
de151cf6 JB |
2515 | } |
2516 | ||
52dc7d32 CW |
2517 | /** |
2518 | * i915_gem_object_put_fence_reg - waits on outstanding fenced access | |
2519 | * to the buffer to finish, and then resets the fence register. | |
2520 | * @obj: tiled object holding a fence register. | |
2521 | * | |
2522 | * Zeroes out the fence register itself and clears out the associated | |
2523 | * data structures in dev_priv and obj_priv. | |
2524 | */ | |
2525 | int | |
2526 | i915_gem_object_put_fence_reg(struct drm_gem_object *obj) | |
2527 | { | |
2528 | struct drm_device *dev = obj->dev; | |
2529 | struct drm_i915_gem_object *obj_priv = obj->driver_private; | |
2530 | ||
2531 | if (obj_priv->fence_reg == I915_FENCE_REG_NONE) | |
2532 | return 0; | |
2533 | ||
2534 | /* On the i915, GPU access to tiled buffers is via a fence, | |
2535 | * therefore we must wait for any outstanding access to complete | |
2536 | * before clearing the fence. | |
2537 | */ | |
2538 | if (!IS_I965G(dev)) { | |
2539 | int ret; | |
2540 | ||
2541 | i915_gem_object_flush_gpu_write_domain(obj); | |
2542 | i915_gem_object_flush_gtt_write_domain(obj); | |
2543 | ret = i915_gem_object_wait_rendering(obj); | |
2544 | if (ret != 0) | |
2545 | return ret; | |
2546 | } | |
2547 | ||
2548 | i915_gem_clear_fence_reg (obj); | |
2549 | ||
2550 | return 0; | |
2551 | } | |
2552 | ||
673a394b EA |
2553 | /** |
2554 | * Finds free space in the GTT aperture and binds the object there. | |
2555 | */ | |
2556 | static int | |
2557 | i915_gem_object_bind_to_gtt(struct drm_gem_object *obj, unsigned alignment) | |
2558 | { | |
2559 | struct drm_device *dev = obj->dev; | |
2560 | drm_i915_private_t *dev_priv = dev->dev_private; | |
2561 | struct drm_i915_gem_object *obj_priv = obj->driver_private; | |
2562 | struct drm_mm_node *free_space; | |
07f73f69 CW |
2563 | bool retry_alloc = false; |
2564 | int ret; | |
673a394b | 2565 | |
9bb2d6f9 EA |
2566 | if (dev_priv->mm.suspended) |
2567 | return -EBUSY; | |
3ef94daa | 2568 | |
bb6baf76 | 2569 | if (obj_priv->madv != I915_MADV_WILLNEED) { |
3ef94daa CW |
2570 | DRM_ERROR("Attempting to bind a purgeable object\n"); |
2571 | return -EINVAL; | |
2572 | } | |
2573 | ||
673a394b | 2574 | if (alignment == 0) |
0f973f27 | 2575 | alignment = i915_gem_get_gtt_alignment(obj); |
8d7773a3 | 2576 | if (alignment & (i915_gem_get_gtt_alignment(obj) - 1)) { |
673a394b EA |
2577 | DRM_ERROR("Invalid object alignment requested %u\n", alignment); |
2578 | return -EINVAL; | |
2579 | } | |
2580 | ||
2581 | search_free: | |
2582 | free_space = drm_mm_search_free(&dev_priv->mm.gtt_space, | |
2583 | obj->size, alignment, 0); | |
2584 | if (free_space != NULL) { | |
2585 | obj_priv->gtt_space = drm_mm_get_block(free_space, obj->size, | |
2586 | alignment); | |
2587 | if (obj_priv->gtt_space != NULL) { | |
2588 | obj_priv->gtt_space->private = obj; | |
2589 | obj_priv->gtt_offset = obj_priv->gtt_space->start; | |
2590 | } | |
2591 | } | |
2592 | if (obj_priv->gtt_space == NULL) { | |
2593 | /* If the gtt is empty and we're still having trouble | |
2594 | * fitting our object in, we're out of memory. | |
2595 | */ | |
2596 | #if WATCH_LRU | |
2597 | DRM_INFO("%s: GTT full, evicting something\n", __func__); | |
2598 | #endif | |
07f73f69 | 2599 | ret = i915_gem_evict_something(dev, obj->size); |
9731129c | 2600 | if (ret) |
673a394b | 2601 | return ret; |
9731129c | 2602 | |
673a394b EA |
2603 | goto search_free; |
2604 | } | |
2605 | ||
2606 | #if WATCH_BUF | |
cfd43c02 | 2607 | DRM_INFO("Binding object of size %zd at 0x%08x\n", |
673a394b EA |
2608 | obj->size, obj_priv->gtt_offset); |
2609 | #endif | |
07f73f69 CW |
2610 | if (retry_alloc) { |
2611 | i915_gem_object_set_page_gfp_mask (obj, | |
2612 | i915_gem_object_get_page_gfp_mask (obj) & ~__GFP_NORETRY); | |
2613 | } | |
856fa198 | 2614 | ret = i915_gem_object_get_pages(obj); |
07f73f69 CW |
2615 | if (retry_alloc) { |
2616 | i915_gem_object_set_page_gfp_mask (obj, | |
2617 | i915_gem_object_get_page_gfp_mask (obj) | __GFP_NORETRY); | |
2618 | } | |
673a394b EA |
2619 | if (ret) { |
2620 | drm_mm_put_block(obj_priv->gtt_space); | |
2621 | obj_priv->gtt_space = NULL; | |
07f73f69 CW |
2622 | |
2623 | if (ret == -ENOMEM) { | |
2624 | /* first try to clear up some space from the GTT */ | |
2625 | ret = i915_gem_evict_something(dev, obj->size); | |
2626 | if (ret) { | |
07f73f69 CW |
2627 | /* now try to shrink everyone else */ |
2628 | if (! retry_alloc) { | |
2629 | retry_alloc = true; | |
2630 | goto search_free; | |
2631 | } | |
2632 | ||
2633 | return ret; | |
2634 | } | |
2635 | ||
2636 | goto search_free; | |
2637 | } | |
2638 | ||
673a394b EA |
2639 | return ret; |
2640 | } | |
2641 | ||
673a394b EA |
2642 | /* Create an AGP memory structure pointing at our pages, and bind it |
2643 | * into the GTT. | |
2644 | */ | |
2645 | obj_priv->agp_mem = drm_agp_bind_pages(dev, | |
856fa198 | 2646 | obj_priv->pages, |
07f73f69 | 2647 | obj->size >> PAGE_SHIFT, |
ba1eb1d8 KP |
2648 | obj_priv->gtt_offset, |
2649 | obj_priv->agp_type); | |
673a394b | 2650 | if (obj_priv->agp_mem == NULL) { |
856fa198 | 2651 | i915_gem_object_put_pages(obj); |
673a394b EA |
2652 | drm_mm_put_block(obj_priv->gtt_space); |
2653 | obj_priv->gtt_space = NULL; | |
07f73f69 CW |
2654 | |
2655 | ret = i915_gem_evict_something(dev, obj->size); | |
9731129c | 2656 | if (ret) |
07f73f69 | 2657 | return ret; |
07f73f69 CW |
2658 | |
2659 | goto search_free; | |
673a394b EA |
2660 | } |
2661 | atomic_inc(&dev->gtt_count); | |
2662 | atomic_add(obj->size, &dev->gtt_memory); | |
2663 | ||
2664 | /* Assert that the object is not currently in any GPU domain. As it | |
2665 | * wasn't in the GTT, there shouldn't be any way it could have been in | |
2666 | * a GPU cache | |
2667 | */ | |
21d509e3 CW |
2668 | BUG_ON(obj->read_domains & I915_GEM_GPU_DOMAINS); |
2669 | BUG_ON(obj->write_domain & I915_GEM_GPU_DOMAINS); | |
673a394b | 2670 | |
1c5d22f7 CW |
2671 | trace_i915_gem_object_bind(obj, obj_priv->gtt_offset); |
2672 | ||
673a394b EA |
2673 | return 0; |
2674 | } | |
2675 | ||
2676 | void | |
2677 | i915_gem_clflush_object(struct drm_gem_object *obj) | |
2678 | { | |
2679 | struct drm_i915_gem_object *obj_priv = obj->driver_private; | |
2680 | ||
2681 | /* If we don't have a page list set up, then we're not pinned | |
2682 | * to GPU, and we can ignore the cache flush because it'll happen | |
2683 | * again at bind time. | |
2684 | */ | |
856fa198 | 2685 | if (obj_priv->pages == NULL) |
673a394b EA |
2686 | return; |
2687 | ||
1c5d22f7 | 2688 | trace_i915_gem_object_clflush(obj); |
cfa16a0d | 2689 | |
856fa198 | 2690 | drm_clflush_pages(obj_priv->pages, obj->size / PAGE_SIZE); |
673a394b EA |
2691 | } |
2692 | ||
e47c68e9 EA |
2693 | /** Flushes any GPU write domain for the object if it's dirty. */ |
2694 | static void | |
2695 | i915_gem_object_flush_gpu_write_domain(struct drm_gem_object *obj) | |
2696 | { | |
2697 | struct drm_device *dev = obj->dev; | |
2698 | uint32_t seqno; | |
1c5d22f7 | 2699 | uint32_t old_write_domain; |
e47c68e9 EA |
2700 | |
2701 | if ((obj->write_domain & I915_GEM_GPU_DOMAINS) == 0) | |
2702 | return; | |
2703 | ||
2704 | /* Queue the GPU write cache flushing we need. */ | |
1c5d22f7 | 2705 | old_write_domain = obj->write_domain; |
e47c68e9 | 2706 | i915_gem_flush(dev, 0, obj->write_domain); |
b962442e | 2707 | seqno = i915_add_request(dev, NULL, obj->write_domain); |
e47c68e9 EA |
2708 | obj->write_domain = 0; |
2709 | i915_gem_object_move_to_active(obj, seqno); | |
1c5d22f7 CW |
2710 | |
2711 | trace_i915_gem_object_change_domain(obj, | |
2712 | obj->read_domains, | |
2713 | old_write_domain); | |
e47c68e9 EA |
2714 | } |
2715 | ||
2716 | /** Flushes the GTT write domain for the object if it's dirty. */ | |
2717 | static void | |
2718 | i915_gem_object_flush_gtt_write_domain(struct drm_gem_object *obj) | |
2719 | { | |
1c5d22f7 CW |
2720 | uint32_t old_write_domain; |
2721 | ||
e47c68e9 EA |
2722 | if (obj->write_domain != I915_GEM_DOMAIN_GTT) |
2723 | return; | |
2724 | ||
2725 | /* No actual flushing is required for the GTT write domain. Writes | |
2726 | * to it immediately go to main memory as far as we know, so there's | |
2727 | * no chipset flush. It also doesn't land in render cache. | |
2728 | */ | |
1c5d22f7 | 2729 | old_write_domain = obj->write_domain; |
e47c68e9 | 2730 | obj->write_domain = 0; |
1c5d22f7 CW |
2731 | |
2732 | trace_i915_gem_object_change_domain(obj, | |
2733 | obj->read_domains, | |
2734 | old_write_domain); | |
e47c68e9 EA |
2735 | } |
2736 | ||
2737 | /** Flushes the CPU write domain for the object if it's dirty. */ | |
2738 | static void | |
2739 | i915_gem_object_flush_cpu_write_domain(struct drm_gem_object *obj) | |
2740 | { | |
2741 | struct drm_device *dev = obj->dev; | |
1c5d22f7 | 2742 | uint32_t old_write_domain; |
e47c68e9 EA |
2743 | |
2744 | if (obj->write_domain != I915_GEM_DOMAIN_CPU) | |
2745 | return; | |
2746 | ||
2747 | i915_gem_clflush_object(obj); | |
2748 | drm_agp_chipset_flush(dev); | |
1c5d22f7 | 2749 | old_write_domain = obj->write_domain; |
e47c68e9 | 2750 | obj->write_domain = 0; |
1c5d22f7 CW |
2751 | |
2752 | trace_i915_gem_object_change_domain(obj, | |
2753 | obj->read_domains, | |
2754 | old_write_domain); | |
e47c68e9 EA |
2755 | } |
2756 | ||
2ef7eeaa EA |
2757 | /** |
2758 | * Moves a single object to the GTT read, and possibly write domain. | |
2759 | * | |
2760 | * This function returns when the move is complete, including waiting on | |
2761 | * flushes to occur. | |
2762 | */ | |
79e53945 | 2763 | int |
2ef7eeaa EA |
2764 | i915_gem_object_set_to_gtt_domain(struct drm_gem_object *obj, int write) |
2765 | { | |
2ef7eeaa | 2766 | struct drm_i915_gem_object *obj_priv = obj->driver_private; |
1c5d22f7 | 2767 | uint32_t old_write_domain, old_read_domains; |
e47c68e9 | 2768 | int ret; |
2ef7eeaa | 2769 | |
02354392 EA |
2770 | /* Not valid to be called on unbound objects. */ |
2771 | if (obj_priv->gtt_space == NULL) | |
2772 | return -EINVAL; | |
2773 | ||
e47c68e9 EA |
2774 | i915_gem_object_flush_gpu_write_domain(obj); |
2775 | /* Wait on any GPU rendering and flushing to occur. */ | |
2776 | ret = i915_gem_object_wait_rendering(obj); | |
2777 | if (ret != 0) | |
2778 | return ret; | |
2779 | ||
1c5d22f7 CW |
2780 | old_write_domain = obj->write_domain; |
2781 | old_read_domains = obj->read_domains; | |
2782 | ||
e47c68e9 EA |
2783 | /* If we're writing through the GTT domain, then CPU and GPU caches |
2784 | * will need to be invalidated at next use. | |
2ef7eeaa | 2785 | */ |
e47c68e9 EA |
2786 | if (write) |
2787 | obj->read_domains &= I915_GEM_DOMAIN_GTT; | |
2ef7eeaa | 2788 | |
e47c68e9 | 2789 | i915_gem_object_flush_cpu_write_domain(obj); |
2ef7eeaa | 2790 | |
e47c68e9 EA |
2791 | /* It should now be out of any other write domains, and we can update |
2792 | * the domain values for our changes. | |
2793 | */ | |
2794 | BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_GTT) != 0); | |
2795 | obj->read_domains |= I915_GEM_DOMAIN_GTT; | |
2796 | if (write) { | |
2797 | obj->write_domain = I915_GEM_DOMAIN_GTT; | |
2798 | obj_priv->dirty = 1; | |
2ef7eeaa EA |
2799 | } |
2800 | ||
1c5d22f7 CW |
2801 | trace_i915_gem_object_change_domain(obj, |
2802 | old_read_domains, | |
2803 | old_write_domain); | |
2804 | ||
e47c68e9 EA |
2805 | return 0; |
2806 | } | |
2807 | ||
2808 | /** | |
2809 | * Moves a single object to the CPU read, and possibly write domain. | |
2810 | * | |
2811 | * This function returns when the move is complete, including waiting on | |
2812 | * flushes to occur. | |
2813 | */ | |
2814 | static int | |
2815 | i915_gem_object_set_to_cpu_domain(struct drm_gem_object *obj, int write) | |
2816 | { | |
1c5d22f7 | 2817 | uint32_t old_write_domain, old_read_domains; |
e47c68e9 EA |
2818 | int ret; |
2819 | ||
2820 | i915_gem_object_flush_gpu_write_domain(obj); | |
2ef7eeaa | 2821 | /* Wait on any GPU rendering and flushing to occur. */ |
e47c68e9 EA |
2822 | ret = i915_gem_object_wait_rendering(obj); |
2823 | if (ret != 0) | |
2824 | return ret; | |
2ef7eeaa | 2825 | |
e47c68e9 | 2826 | i915_gem_object_flush_gtt_write_domain(obj); |
2ef7eeaa | 2827 | |
e47c68e9 EA |
2828 | /* If we have a partially-valid cache of the object in the CPU, |
2829 | * finish invalidating it and free the per-page flags. | |
2ef7eeaa | 2830 | */ |
e47c68e9 | 2831 | i915_gem_object_set_to_full_cpu_read_domain(obj); |
2ef7eeaa | 2832 | |
1c5d22f7 CW |
2833 | old_write_domain = obj->write_domain; |
2834 | old_read_domains = obj->read_domains; | |
2835 | ||
e47c68e9 EA |
2836 | /* Flush the CPU cache if it's still invalid. */ |
2837 | if ((obj->read_domains & I915_GEM_DOMAIN_CPU) == 0) { | |
2ef7eeaa | 2838 | i915_gem_clflush_object(obj); |
2ef7eeaa | 2839 | |
e47c68e9 | 2840 | obj->read_domains |= I915_GEM_DOMAIN_CPU; |
2ef7eeaa EA |
2841 | } |
2842 | ||
2843 | /* It should now be out of any other write domains, and we can update | |
2844 | * the domain values for our changes. | |
2845 | */ | |
e47c68e9 EA |
2846 | BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_CPU) != 0); |
2847 | ||
2848 | /* If we're writing through the CPU, then the GPU read domains will | |
2849 | * need to be invalidated at next use. | |
2850 | */ | |
2851 | if (write) { | |
2852 | obj->read_domains &= I915_GEM_DOMAIN_CPU; | |
2853 | obj->write_domain = I915_GEM_DOMAIN_CPU; | |
2854 | } | |
2ef7eeaa | 2855 | |
1c5d22f7 CW |
2856 | trace_i915_gem_object_change_domain(obj, |
2857 | old_read_domains, | |
2858 | old_write_domain); | |
2859 | ||
2ef7eeaa EA |
2860 | return 0; |
2861 | } | |
2862 | ||
673a394b EA |
2863 | /* |
2864 | * Set the next domain for the specified object. This | |
2865 | * may not actually perform the necessary flushing/invaliding though, | |
2866 | * as that may want to be batched with other set_domain operations | |
2867 | * | |
2868 | * This is (we hope) the only really tricky part of gem. The goal | |
2869 | * is fairly simple -- track which caches hold bits of the object | |
2870 | * and make sure they remain coherent. A few concrete examples may | |
2871 | * help to explain how it works. For shorthand, we use the notation | |
2872 | * (read_domains, write_domain), e.g. (CPU, CPU) to indicate the | |
2873 | * a pair of read and write domain masks. | |
2874 | * | |
2875 | * Case 1: the batch buffer | |
2876 | * | |
2877 | * 1. Allocated | |
2878 | * 2. Written by CPU | |
2879 | * 3. Mapped to GTT | |
2880 | * 4. Read by GPU | |
2881 | * 5. Unmapped from GTT | |
2882 | * 6. Freed | |
2883 | * | |
2884 | * Let's take these a step at a time | |
2885 | * | |
2886 | * 1. Allocated | |
2887 | * Pages allocated from the kernel may still have | |
2888 | * cache contents, so we set them to (CPU, CPU) always. | |
2889 | * 2. Written by CPU (using pwrite) | |
2890 | * The pwrite function calls set_domain (CPU, CPU) and | |
2891 | * this function does nothing (as nothing changes) | |
2892 | * 3. Mapped by GTT | |
2893 | * This function asserts that the object is not | |
2894 | * currently in any GPU-based read or write domains | |
2895 | * 4. Read by GPU | |
2896 | * i915_gem_execbuffer calls set_domain (COMMAND, 0). | |
2897 | * As write_domain is zero, this function adds in the | |
2898 | * current read domains (CPU+COMMAND, 0). | |
2899 | * flush_domains is set to CPU. | |
2900 | * invalidate_domains is set to COMMAND | |
2901 | * clflush is run to get data out of the CPU caches | |
2902 | * then i915_dev_set_domain calls i915_gem_flush to | |
2903 | * emit an MI_FLUSH and drm_agp_chipset_flush | |
2904 | * 5. Unmapped from GTT | |
2905 | * i915_gem_object_unbind calls set_domain (CPU, CPU) | |
2906 | * flush_domains and invalidate_domains end up both zero | |
2907 | * so no flushing/invalidating happens | |
2908 | * 6. Freed | |
2909 | * yay, done | |
2910 | * | |
2911 | * Case 2: The shared render buffer | |
2912 | * | |
2913 | * 1. Allocated | |
2914 | * 2. Mapped to GTT | |
2915 | * 3. Read/written by GPU | |
2916 | * 4. set_domain to (CPU,CPU) | |
2917 | * 5. Read/written by CPU | |
2918 | * 6. Read/written by GPU | |
2919 | * | |
2920 | * 1. Allocated | |
2921 | * Same as last example, (CPU, CPU) | |
2922 | * 2. Mapped to GTT | |
2923 | * Nothing changes (assertions find that it is not in the GPU) | |
2924 | * 3. Read/written by GPU | |
2925 | * execbuffer calls set_domain (RENDER, RENDER) | |
2926 | * flush_domains gets CPU | |
2927 | * invalidate_domains gets GPU | |
2928 | * clflush (obj) | |
2929 | * MI_FLUSH and drm_agp_chipset_flush | |
2930 | * 4. set_domain (CPU, CPU) | |
2931 | * flush_domains gets GPU | |
2932 | * invalidate_domains gets CPU | |
2933 | * wait_rendering (obj) to make sure all drawing is complete. | |
2934 | * This will include an MI_FLUSH to get the data from GPU | |
2935 | * to memory | |
2936 | * clflush (obj) to invalidate the CPU cache | |
2937 | * Another MI_FLUSH in i915_gem_flush (eliminate this somehow?) | |
2938 | * 5. Read/written by CPU | |
2939 | * cache lines are loaded and dirtied | |
2940 | * 6. Read written by GPU | |
2941 | * Same as last GPU access | |
2942 | * | |
2943 | * Case 3: The constant buffer | |
2944 | * | |
2945 | * 1. Allocated | |
2946 | * 2. Written by CPU | |
2947 | * 3. Read by GPU | |
2948 | * 4. Updated (written) by CPU again | |
2949 | * 5. Read by GPU | |
2950 | * | |
2951 | * 1. Allocated | |
2952 | * (CPU, CPU) | |
2953 | * 2. Written by CPU | |
2954 | * (CPU, CPU) | |
2955 | * 3. Read by GPU | |
2956 | * (CPU+RENDER, 0) | |
2957 | * flush_domains = CPU | |
2958 | * invalidate_domains = RENDER | |
2959 | * clflush (obj) | |
2960 | * MI_FLUSH | |
2961 | * drm_agp_chipset_flush | |
2962 | * 4. Updated (written) by CPU again | |
2963 | * (CPU, CPU) | |
2964 | * flush_domains = 0 (no previous write domain) | |
2965 | * invalidate_domains = 0 (no new read domains) | |
2966 | * 5. Read by GPU | |
2967 | * (CPU+RENDER, 0) | |
2968 | * flush_domains = CPU | |
2969 | * invalidate_domains = RENDER | |
2970 | * clflush (obj) | |
2971 | * MI_FLUSH | |
2972 | * drm_agp_chipset_flush | |
2973 | */ | |
c0d90829 | 2974 | static void |
8b0e378a | 2975 | i915_gem_object_set_to_gpu_domain(struct drm_gem_object *obj) |
673a394b EA |
2976 | { |
2977 | struct drm_device *dev = obj->dev; | |
2978 | struct drm_i915_gem_object *obj_priv = obj->driver_private; | |
2979 | uint32_t invalidate_domains = 0; | |
2980 | uint32_t flush_domains = 0; | |
1c5d22f7 | 2981 | uint32_t old_read_domains; |
e47c68e9 | 2982 | |
8b0e378a EA |
2983 | BUG_ON(obj->pending_read_domains & I915_GEM_DOMAIN_CPU); |
2984 | BUG_ON(obj->pending_write_domain == I915_GEM_DOMAIN_CPU); | |
673a394b | 2985 | |
652c393a JB |
2986 | intel_mark_busy(dev, obj); |
2987 | ||
673a394b EA |
2988 | #if WATCH_BUF |
2989 | DRM_INFO("%s: object %p read %08x -> %08x write %08x -> %08x\n", | |
2990 | __func__, obj, | |
8b0e378a EA |
2991 | obj->read_domains, obj->pending_read_domains, |
2992 | obj->write_domain, obj->pending_write_domain); | |
673a394b EA |
2993 | #endif |
2994 | /* | |
2995 | * If the object isn't moving to a new write domain, | |
2996 | * let the object stay in multiple read domains | |
2997 | */ | |
8b0e378a EA |
2998 | if (obj->pending_write_domain == 0) |
2999 | obj->pending_read_domains |= obj->read_domains; | |
673a394b EA |
3000 | else |
3001 | obj_priv->dirty = 1; | |
3002 | ||
3003 | /* | |
3004 | * Flush the current write domain if | |
3005 | * the new read domains don't match. Invalidate | |
3006 | * any read domains which differ from the old | |
3007 | * write domain | |
3008 | */ | |
8b0e378a EA |
3009 | if (obj->write_domain && |
3010 | obj->write_domain != obj->pending_read_domains) { | |
673a394b | 3011 | flush_domains |= obj->write_domain; |
8b0e378a EA |
3012 | invalidate_domains |= |
3013 | obj->pending_read_domains & ~obj->write_domain; | |
673a394b EA |
3014 | } |
3015 | /* | |
3016 | * Invalidate any read caches which may have | |
3017 | * stale data. That is, any new read domains. | |
3018 | */ | |
8b0e378a | 3019 | invalidate_domains |= obj->pending_read_domains & ~obj->read_domains; |
673a394b EA |
3020 | if ((flush_domains | invalidate_domains) & I915_GEM_DOMAIN_CPU) { |
3021 | #if WATCH_BUF | |
3022 | DRM_INFO("%s: CPU domain flush %08x invalidate %08x\n", | |
3023 | __func__, flush_domains, invalidate_domains); | |
3024 | #endif | |
673a394b EA |
3025 | i915_gem_clflush_object(obj); |
3026 | } | |
3027 | ||
1c5d22f7 CW |
3028 | old_read_domains = obj->read_domains; |
3029 | ||
efbeed96 EA |
3030 | /* The actual obj->write_domain will be updated with |
3031 | * pending_write_domain after we emit the accumulated flush for all | |
3032 | * of our domain changes in execbuffers (which clears objects' | |
3033 | * write_domains). So if we have a current write domain that we | |
3034 | * aren't changing, set pending_write_domain to that. | |
3035 | */ | |
3036 | if (flush_domains == 0 && obj->pending_write_domain == 0) | |
3037 | obj->pending_write_domain = obj->write_domain; | |
8b0e378a | 3038 | obj->read_domains = obj->pending_read_domains; |
673a394b EA |
3039 | |
3040 | dev->invalidate_domains |= invalidate_domains; | |
3041 | dev->flush_domains |= flush_domains; | |
3042 | #if WATCH_BUF | |
3043 | DRM_INFO("%s: read %08x write %08x invalidate %08x flush %08x\n", | |
3044 | __func__, | |
3045 | obj->read_domains, obj->write_domain, | |
3046 | dev->invalidate_domains, dev->flush_domains); | |
3047 | #endif | |
1c5d22f7 CW |
3048 | |
3049 | trace_i915_gem_object_change_domain(obj, | |
3050 | old_read_domains, | |
3051 | obj->write_domain); | |
673a394b EA |
3052 | } |
3053 | ||
3054 | /** | |
e47c68e9 | 3055 | * Moves the object from a partially CPU read to a full one. |
673a394b | 3056 | * |
e47c68e9 EA |
3057 | * Note that this only resolves i915_gem_object_set_cpu_read_domain_range(), |
3058 | * and doesn't handle transitioning from !(read_domains & I915_GEM_DOMAIN_CPU). | |
673a394b | 3059 | */ |
e47c68e9 EA |
3060 | static void |
3061 | i915_gem_object_set_to_full_cpu_read_domain(struct drm_gem_object *obj) | |
673a394b EA |
3062 | { |
3063 | struct drm_i915_gem_object *obj_priv = obj->driver_private; | |
673a394b | 3064 | |
e47c68e9 EA |
3065 | if (!obj_priv->page_cpu_valid) |
3066 | return; | |
3067 | ||
3068 | /* If we're partially in the CPU read domain, finish moving it in. | |
3069 | */ | |
3070 | if (obj->read_domains & I915_GEM_DOMAIN_CPU) { | |
3071 | int i; | |
3072 | ||
3073 | for (i = 0; i <= (obj->size - 1) / PAGE_SIZE; i++) { | |
3074 | if (obj_priv->page_cpu_valid[i]) | |
3075 | continue; | |
856fa198 | 3076 | drm_clflush_pages(obj_priv->pages + i, 1); |
e47c68e9 | 3077 | } |
e47c68e9 EA |
3078 | } |
3079 | ||
3080 | /* Free the page_cpu_valid mappings which are now stale, whether | |
3081 | * or not we've got I915_GEM_DOMAIN_CPU. | |
3082 | */ | |
9a298b2a | 3083 | kfree(obj_priv->page_cpu_valid); |
e47c68e9 EA |
3084 | obj_priv->page_cpu_valid = NULL; |
3085 | } | |
3086 | ||
3087 | /** | |
3088 | * Set the CPU read domain on a range of the object. | |
3089 | * | |
3090 | * The object ends up with I915_GEM_DOMAIN_CPU in its read flags although it's | |
3091 | * not entirely valid. The page_cpu_valid member of the object flags which | |
3092 | * pages have been flushed, and will be respected by | |
3093 | * i915_gem_object_set_to_cpu_domain() if it's called on to get a valid mapping | |
3094 | * of the whole object. | |
3095 | * | |
3096 | * This function returns when the move is complete, including waiting on | |
3097 | * flushes to occur. | |
3098 | */ | |
3099 | static int | |
3100 | i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object *obj, | |
3101 | uint64_t offset, uint64_t size) | |
3102 | { | |
3103 | struct drm_i915_gem_object *obj_priv = obj->driver_private; | |
1c5d22f7 | 3104 | uint32_t old_read_domains; |
e47c68e9 | 3105 | int i, ret; |
673a394b | 3106 | |
e47c68e9 EA |
3107 | if (offset == 0 && size == obj->size) |
3108 | return i915_gem_object_set_to_cpu_domain(obj, 0); | |
673a394b | 3109 | |
e47c68e9 EA |
3110 | i915_gem_object_flush_gpu_write_domain(obj); |
3111 | /* Wait on any GPU rendering and flushing to occur. */ | |
6a47baa6 | 3112 | ret = i915_gem_object_wait_rendering(obj); |
e47c68e9 | 3113 | if (ret != 0) |
6a47baa6 | 3114 | return ret; |
e47c68e9 EA |
3115 | i915_gem_object_flush_gtt_write_domain(obj); |
3116 | ||
3117 | /* If we're already fully in the CPU read domain, we're done. */ | |
3118 | if (obj_priv->page_cpu_valid == NULL && | |
3119 | (obj->read_domains & I915_GEM_DOMAIN_CPU) != 0) | |
3120 | return 0; | |
673a394b | 3121 | |
e47c68e9 EA |
3122 | /* Otherwise, create/clear the per-page CPU read domain flag if we're |
3123 | * newly adding I915_GEM_DOMAIN_CPU | |
3124 | */ | |
673a394b | 3125 | if (obj_priv->page_cpu_valid == NULL) { |
9a298b2a EA |
3126 | obj_priv->page_cpu_valid = kzalloc(obj->size / PAGE_SIZE, |
3127 | GFP_KERNEL); | |
e47c68e9 EA |
3128 | if (obj_priv->page_cpu_valid == NULL) |
3129 | return -ENOMEM; | |
3130 | } else if ((obj->read_domains & I915_GEM_DOMAIN_CPU) == 0) | |
3131 | memset(obj_priv->page_cpu_valid, 0, obj->size / PAGE_SIZE); | |
673a394b EA |
3132 | |
3133 | /* Flush the cache on any pages that are still invalid from the CPU's | |
3134 | * perspective. | |
3135 | */ | |
e47c68e9 EA |
3136 | for (i = offset / PAGE_SIZE; i <= (offset + size - 1) / PAGE_SIZE; |
3137 | i++) { | |
673a394b EA |
3138 | if (obj_priv->page_cpu_valid[i]) |
3139 | continue; | |
3140 | ||
856fa198 | 3141 | drm_clflush_pages(obj_priv->pages + i, 1); |
673a394b EA |
3142 | |
3143 | obj_priv->page_cpu_valid[i] = 1; | |
3144 | } | |
3145 | ||
e47c68e9 EA |
3146 | /* It should now be out of any other write domains, and we can update |
3147 | * the domain values for our changes. | |
3148 | */ | |
3149 | BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_CPU) != 0); | |
3150 | ||
1c5d22f7 | 3151 | old_read_domains = obj->read_domains; |
e47c68e9 EA |
3152 | obj->read_domains |= I915_GEM_DOMAIN_CPU; |
3153 | ||
1c5d22f7 CW |
3154 | trace_i915_gem_object_change_domain(obj, |
3155 | old_read_domains, | |
3156 | obj->write_domain); | |
3157 | ||
673a394b EA |
3158 | return 0; |
3159 | } | |
3160 | ||
673a394b EA |
3161 | /** |
3162 | * Pin an object to the GTT and evaluate the relocations landing in it. | |
3163 | */ | |
3164 | static int | |
3165 | i915_gem_object_pin_and_relocate(struct drm_gem_object *obj, | |
3166 | struct drm_file *file_priv, | |
40a5f0de EA |
3167 | struct drm_i915_gem_exec_object *entry, |
3168 | struct drm_i915_gem_relocation_entry *relocs) | |
673a394b EA |
3169 | { |
3170 | struct drm_device *dev = obj->dev; | |
0839ccb8 | 3171 | drm_i915_private_t *dev_priv = dev->dev_private; |
673a394b EA |
3172 | struct drm_i915_gem_object *obj_priv = obj->driver_private; |
3173 | int i, ret; | |
0839ccb8 | 3174 | void __iomem *reloc_page; |
673a394b EA |
3175 | |
3176 | /* Choose the GTT offset for our buffer and put it there. */ | |
3177 | ret = i915_gem_object_pin(obj, (uint32_t) entry->alignment); | |
3178 | if (ret) | |
3179 | return ret; | |
3180 | ||
3181 | entry->offset = obj_priv->gtt_offset; | |
3182 | ||
673a394b EA |
3183 | /* Apply the relocations, using the GTT aperture to avoid cache |
3184 | * flushing requirements. | |
3185 | */ | |
3186 | for (i = 0; i < entry->relocation_count; i++) { | |
40a5f0de | 3187 | struct drm_i915_gem_relocation_entry *reloc= &relocs[i]; |
673a394b EA |
3188 | struct drm_gem_object *target_obj; |
3189 | struct drm_i915_gem_object *target_obj_priv; | |
3043c60c EA |
3190 | uint32_t reloc_val, reloc_offset; |
3191 | uint32_t __iomem *reloc_entry; | |
673a394b | 3192 | |
673a394b | 3193 | target_obj = drm_gem_object_lookup(obj->dev, file_priv, |
40a5f0de | 3194 | reloc->target_handle); |
673a394b EA |
3195 | if (target_obj == NULL) { |
3196 | i915_gem_object_unpin(obj); | |
3197 | return -EBADF; | |
3198 | } | |
3199 | target_obj_priv = target_obj->driver_private; | |
3200 | ||
8542a0bb CW |
3201 | #if WATCH_RELOC |
3202 | DRM_INFO("%s: obj %p offset %08x target %d " | |
3203 | "read %08x write %08x gtt %08x " | |
3204 | "presumed %08x delta %08x\n", | |
3205 | __func__, | |
3206 | obj, | |
3207 | (int) reloc->offset, | |
3208 | (int) reloc->target_handle, | |
3209 | (int) reloc->read_domains, | |
3210 | (int) reloc->write_domain, | |
3211 | (int) target_obj_priv->gtt_offset, | |
3212 | (int) reloc->presumed_offset, | |
3213 | reloc->delta); | |
3214 | #endif | |
3215 | ||
673a394b EA |
3216 | /* The target buffer should have appeared before us in the |
3217 | * exec_object list, so it should have a GTT space bound by now. | |
3218 | */ | |
3219 | if (target_obj_priv->gtt_space == NULL) { | |
3220 | DRM_ERROR("No GTT space found for object %d\n", | |
40a5f0de | 3221 | reloc->target_handle); |
673a394b EA |
3222 | drm_gem_object_unreference(target_obj); |
3223 | i915_gem_object_unpin(obj); | |
3224 | return -EINVAL; | |
3225 | } | |
3226 | ||
8542a0bb | 3227 | /* Validate that the target is in a valid r/w GPU domain */ |
40a5f0de EA |
3228 | if (reloc->write_domain & I915_GEM_DOMAIN_CPU || |
3229 | reloc->read_domains & I915_GEM_DOMAIN_CPU) { | |
e47c68e9 EA |
3230 | DRM_ERROR("reloc with read/write CPU domains: " |
3231 | "obj %p target %d offset %d " | |
3232 | "read %08x write %08x", | |
40a5f0de EA |
3233 | obj, reloc->target_handle, |
3234 | (int) reloc->offset, | |
3235 | reloc->read_domains, | |
3236 | reloc->write_domain); | |
491152b8 CW |
3237 | drm_gem_object_unreference(target_obj); |
3238 | i915_gem_object_unpin(obj); | |
e47c68e9 EA |
3239 | return -EINVAL; |
3240 | } | |
40a5f0de EA |
3241 | if (reloc->write_domain && target_obj->pending_write_domain && |
3242 | reloc->write_domain != target_obj->pending_write_domain) { | |
673a394b EA |
3243 | DRM_ERROR("Write domain conflict: " |
3244 | "obj %p target %d offset %d " | |
3245 | "new %08x old %08x\n", | |
40a5f0de EA |
3246 | obj, reloc->target_handle, |
3247 | (int) reloc->offset, | |
3248 | reloc->write_domain, | |
673a394b EA |
3249 | target_obj->pending_write_domain); |
3250 | drm_gem_object_unreference(target_obj); | |
3251 | i915_gem_object_unpin(obj); | |
3252 | return -EINVAL; | |
3253 | } | |
3254 | ||
40a5f0de EA |
3255 | target_obj->pending_read_domains |= reloc->read_domains; |
3256 | target_obj->pending_write_domain |= reloc->write_domain; | |
673a394b EA |
3257 | |
3258 | /* If the relocation already has the right value in it, no | |
3259 | * more work needs to be done. | |
3260 | */ | |
40a5f0de | 3261 | if (target_obj_priv->gtt_offset == reloc->presumed_offset) { |
673a394b EA |
3262 | drm_gem_object_unreference(target_obj); |
3263 | continue; | |
3264 | } | |
3265 | ||
8542a0bb CW |
3266 | /* Check that the relocation address is valid... */ |
3267 | if (reloc->offset > obj->size - 4) { | |
3268 | DRM_ERROR("Relocation beyond object bounds: " | |
3269 | "obj %p target %d offset %d size %d.\n", | |
3270 | obj, reloc->target_handle, | |
3271 | (int) reloc->offset, (int) obj->size); | |
3272 | drm_gem_object_unreference(target_obj); | |
3273 | i915_gem_object_unpin(obj); | |
3274 | return -EINVAL; | |
3275 | } | |
3276 | if (reloc->offset & 3) { | |
3277 | DRM_ERROR("Relocation not 4-byte aligned: " | |
3278 | "obj %p target %d offset %d.\n", | |
3279 | obj, reloc->target_handle, | |
3280 | (int) reloc->offset); | |
3281 | drm_gem_object_unreference(target_obj); | |
3282 | i915_gem_object_unpin(obj); | |
3283 | return -EINVAL; | |
3284 | } | |
3285 | ||
3286 | /* and points to somewhere within the target object. */ | |
3287 | if (reloc->delta >= target_obj->size) { | |
3288 | DRM_ERROR("Relocation beyond target object bounds: " | |
3289 | "obj %p target %d delta %d size %d.\n", | |
3290 | obj, reloc->target_handle, | |
3291 | (int) reloc->delta, (int) target_obj->size); | |
3292 | drm_gem_object_unreference(target_obj); | |
3293 | i915_gem_object_unpin(obj); | |
3294 | return -EINVAL; | |
3295 | } | |
3296 | ||
2ef7eeaa EA |
3297 | ret = i915_gem_object_set_to_gtt_domain(obj, 1); |
3298 | if (ret != 0) { | |
3299 | drm_gem_object_unreference(target_obj); | |
3300 | i915_gem_object_unpin(obj); | |
3301 | return -EINVAL; | |
673a394b EA |
3302 | } |
3303 | ||
3304 | /* Map the page containing the relocation we're going to | |
3305 | * perform. | |
3306 | */ | |
40a5f0de | 3307 | reloc_offset = obj_priv->gtt_offset + reloc->offset; |
0839ccb8 KP |
3308 | reloc_page = io_mapping_map_atomic_wc(dev_priv->mm.gtt_mapping, |
3309 | (reloc_offset & | |
3310 | ~(PAGE_SIZE - 1))); | |
3043c60c | 3311 | reloc_entry = (uint32_t __iomem *)(reloc_page + |
0839ccb8 | 3312 | (reloc_offset & (PAGE_SIZE - 1))); |
40a5f0de | 3313 | reloc_val = target_obj_priv->gtt_offset + reloc->delta; |
673a394b EA |
3314 | |
3315 | #if WATCH_BUF | |
3316 | DRM_INFO("Applied relocation: %p@0x%08x %08x -> %08x\n", | |
40a5f0de | 3317 | obj, (unsigned int) reloc->offset, |
673a394b EA |
3318 | readl(reloc_entry), reloc_val); |
3319 | #endif | |
3320 | writel(reloc_val, reloc_entry); | |
0839ccb8 | 3321 | io_mapping_unmap_atomic(reloc_page); |
673a394b | 3322 | |
40a5f0de EA |
3323 | /* The updated presumed offset for this entry will be |
3324 | * copied back out to the user. | |
673a394b | 3325 | */ |
40a5f0de | 3326 | reloc->presumed_offset = target_obj_priv->gtt_offset; |
673a394b EA |
3327 | |
3328 | drm_gem_object_unreference(target_obj); | |
3329 | } | |
3330 | ||
673a394b EA |
3331 | #if WATCH_BUF |
3332 | if (0) | |
3333 | i915_gem_dump_object(obj, 128, __func__, ~0); | |
3334 | #endif | |
3335 | return 0; | |
3336 | } | |
3337 | ||
3338 | /** Dispatch a batchbuffer to the ring | |
3339 | */ | |
3340 | static int | |
3341 | i915_dispatch_gem_execbuffer(struct drm_device *dev, | |
3342 | struct drm_i915_gem_execbuffer *exec, | |
201361a5 | 3343 | struct drm_clip_rect *cliprects, |
673a394b EA |
3344 | uint64_t exec_offset) |
3345 | { | |
3346 | drm_i915_private_t *dev_priv = dev->dev_private; | |
673a394b EA |
3347 | int nbox = exec->num_cliprects; |
3348 | int i = 0, count; | |
83d60795 | 3349 | uint32_t exec_start, exec_len; |
673a394b EA |
3350 | RING_LOCALS; |
3351 | ||
3352 | exec_start = (uint32_t) exec_offset + exec->batch_start_offset; | |
3353 | exec_len = (uint32_t) exec->batch_len; | |
3354 | ||
8f0dc5bf | 3355 | trace_i915_gem_request_submit(dev, dev_priv->mm.next_gem_seqno + 1); |
1c5d22f7 | 3356 | |
673a394b EA |
3357 | count = nbox ? nbox : 1; |
3358 | ||
3359 | for (i = 0; i < count; i++) { | |
3360 | if (i < nbox) { | |
201361a5 | 3361 | int ret = i915_emit_box(dev, cliprects, i, |
673a394b EA |
3362 | exec->DR1, exec->DR4); |
3363 | if (ret) | |
3364 | return ret; | |
3365 | } | |
3366 | ||
3367 | if (IS_I830(dev) || IS_845G(dev)) { | |
3368 | BEGIN_LP_RING(4); | |
3369 | OUT_RING(MI_BATCH_BUFFER); | |
3370 | OUT_RING(exec_start | MI_BATCH_NON_SECURE); | |
3371 | OUT_RING(exec_start + exec_len - 4); | |
3372 | OUT_RING(0); | |
3373 | ADVANCE_LP_RING(); | |
3374 | } else { | |
3375 | BEGIN_LP_RING(2); | |
3376 | if (IS_I965G(dev)) { | |
3377 | OUT_RING(MI_BATCH_BUFFER_START | | |
3378 | (2 << 6) | | |
3379 | MI_BATCH_NON_SECURE_I965); | |
3380 | OUT_RING(exec_start); | |
3381 | } else { | |
3382 | OUT_RING(MI_BATCH_BUFFER_START | | |
3383 | (2 << 6)); | |
3384 | OUT_RING(exec_start | MI_BATCH_NON_SECURE); | |
3385 | } | |
3386 | ADVANCE_LP_RING(); | |
3387 | } | |
3388 | } | |
3389 | ||
3390 | /* XXX breadcrumb */ | |
3391 | return 0; | |
3392 | } | |
3393 | ||
3394 | /* Throttle our rendering by waiting until the ring has completed our requests | |
3395 | * emitted over 20 msec ago. | |
3396 | * | |
b962442e EA |
3397 | * Note that if we were to use the current jiffies each time around the loop, |
3398 | * we wouldn't escape the function with any frames outstanding if the time to | |
3399 | * render a frame was over 20ms. | |
3400 | * | |
673a394b EA |
3401 | * This should get us reasonable parallelism between CPU and GPU but also |
3402 | * relatively low latency when blocking on a particular request to finish. | |
3403 | */ | |
3404 | static int | |
3405 | i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file_priv) | |
3406 | { | |
3407 | struct drm_i915_file_private *i915_file_priv = file_priv->driver_priv; | |
3408 | int ret = 0; | |
b962442e | 3409 | unsigned long recent_enough = jiffies - msecs_to_jiffies(20); |
673a394b EA |
3410 | |
3411 | mutex_lock(&dev->struct_mutex); | |
b962442e EA |
3412 | while (!list_empty(&i915_file_priv->mm.request_list)) { |
3413 | struct drm_i915_gem_request *request; | |
3414 | ||
3415 | request = list_first_entry(&i915_file_priv->mm.request_list, | |
3416 | struct drm_i915_gem_request, | |
3417 | client_list); | |
3418 | ||
3419 | if (time_after_eq(request->emitted_jiffies, recent_enough)) | |
3420 | break; | |
3421 | ||
3422 | ret = i915_wait_request(dev, request->seqno); | |
3423 | if (ret != 0) | |
3424 | break; | |
3425 | } | |
673a394b | 3426 | mutex_unlock(&dev->struct_mutex); |
b962442e | 3427 | |
673a394b EA |
3428 | return ret; |
3429 | } | |
3430 | ||
40a5f0de EA |
3431 | static int |
3432 | i915_gem_get_relocs_from_user(struct drm_i915_gem_exec_object *exec_list, | |
3433 | uint32_t buffer_count, | |
3434 | struct drm_i915_gem_relocation_entry **relocs) | |
3435 | { | |
3436 | uint32_t reloc_count = 0, reloc_index = 0, i; | |
3437 | int ret; | |
3438 | ||
3439 | *relocs = NULL; | |
3440 | for (i = 0; i < buffer_count; i++) { | |
3441 | if (reloc_count + exec_list[i].relocation_count < reloc_count) | |
3442 | return -EINVAL; | |
3443 | reloc_count += exec_list[i].relocation_count; | |
3444 | } | |
3445 | ||
8e7d2b2c | 3446 | *relocs = drm_calloc_large(reloc_count, sizeof(**relocs)); |
40a5f0de EA |
3447 | if (*relocs == NULL) |
3448 | return -ENOMEM; | |
3449 | ||
3450 | for (i = 0; i < buffer_count; i++) { | |
3451 | struct drm_i915_gem_relocation_entry __user *user_relocs; | |
3452 | ||
3453 | user_relocs = (void __user *)(uintptr_t)exec_list[i].relocs_ptr; | |
3454 | ||
3455 | ret = copy_from_user(&(*relocs)[reloc_index], | |
3456 | user_relocs, | |
3457 | exec_list[i].relocation_count * | |
3458 | sizeof(**relocs)); | |
3459 | if (ret != 0) { | |
8e7d2b2c | 3460 | drm_free_large(*relocs); |
40a5f0de | 3461 | *relocs = NULL; |
2bc43b5c | 3462 | return -EFAULT; |
40a5f0de EA |
3463 | } |
3464 | ||
3465 | reloc_index += exec_list[i].relocation_count; | |
3466 | } | |
3467 | ||
2bc43b5c | 3468 | return 0; |
40a5f0de EA |
3469 | } |
3470 | ||
3471 | static int | |
3472 | i915_gem_put_relocs_to_user(struct drm_i915_gem_exec_object *exec_list, | |
3473 | uint32_t buffer_count, | |
3474 | struct drm_i915_gem_relocation_entry *relocs) | |
3475 | { | |
3476 | uint32_t reloc_count = 0, i; | |
2bc43b5c | 3477 | int ret = 0; |
40a5f0de EA |
3478 | |
3479 | for (i = 0; i < buffer_count; i++) { | |
3480 | struct drm_i915_gem_relocation_entry __user *user_relocs; | |
2bc43b5c | 3481 | int unwritten; |
40a5f0de EA |
3482 | |
3483 | user_relocs = (void __user *)(uintptr_t)exec_list[i].relocs_ptr; | |
3484 | ||
2bc43b5c FM |
3485 | unwritten = copy_to_user(user_relocs, |
3486 | &relocs[reloc_count], | |
3487 | exec_list[i].relocation_count * | |
3488 | sizeof(*relocs)); | |
3489 | ||
3490 | if (unwritten) { | |
3491 | ret = -EFAULT; | |
3492 | goto err; | |
40a5f0de EA |
3493 | } |
3494 | ||
3495 | reloc_count += exec_list[i].relocation_count; | |
3496 | } | |
3497 | ||
2bc43b5c | 3498 | err: |
8e7d2b2c | 3499 | drm_free_large(relocs); |
40a5f0de EA |
3500 | |
3501 | return ret; | |
3502 | } | |
3503 | ||
83d60795 CW |
3504 | static int |
3505 | i915_gem_check_execbuffer (struct drm_i915_gem_execbuffer *exec, | |
3506 | uint64_t exec_offset) | |
3507 | { | |
3508 | uint32_t exec_start, exec_len; | |
3509 | ||
3510 | exec_start = (uint32_t) exec_offset + exec->batch_start_offset; | |
3511 | exec_len = (uint32_t) exec->batch_len; | |
3512 | ||
3513 | if ((exec_start | exec_len) & 0x7) | |
3514 | return -EINVAL; | |
3515 | ||
3516 | if (!exec_start) | |
3517 | return -EINVAL; | |
3518 | ||
3519 | return 0; | |
3520 | } | |
3521 | ||
673a394b EA |
3522 | int |
3523 | i915_gem_execbuffer(struct drm_device *dev, void *data, | |
3524 | struct drm_file *file_priv) | |
3525 | { | |
3526 | drm_i915_private_t *dev_priv = dev->dev_private; | |
673a394b EA |
3527 | struct drm_i915_gem_execbuffer *args = data; |
3528 | struct drm_i915_gem_exec_object *exec_list = NULL; | |
3529 | struct drm_gem_object **object_list = NULL; | |
3530 | struct drm_gem_object *batch_obj; | |
b70d11da | 3531 | struct drm_i915_gem_object *obj_priv; |
201361a5 | 3532 | struct drm_clip_rect *cliprects = NULL; |
40a5f0de EA |
3533 | struct drm_i915_gem_relocation_entry *relocs; |
3534 | int ret, ret2, i, pinned = 0; | |
673a394b | 3535 | uint64_t exec_offset; |
40a5f0de | 3536 | uint32_t seqno, flush_domains, reloc_index; |
ac94a962 | 3537 | int pin_tries; |
673a394b EA |
3538 | |
3539 | #if WATCH_EXEC | |
3540 | DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n", | |
3541 | (int) args->buffers_ptr, args->buffer_count, args->batch_len); | |
3542 | #endif | |
3543 | ||
4f481ed2 EA |
3544 | if (args->buffer_count < 1) { |
3545 | DRM_ERROR("execbuf with %d buffers\n", args->buffer_count); | |
3546 | return -EINVAL; | |
3547 | } | |
673a394b | 3548 | /* Copy in the exec list from userland */ |
8e7d2b2c JB |
3549 | exec_list = drm_calloc_large(sizeof(*exec_list), args->buffer_count); |
3550 | object_list = drm_calloc_large(sizeof(*object_list), args->buffer_count); | |
673a394b EA |
3551 | if (exec_list == NULL || object_list == NULL) { |
3552 | DRM_ERROR("Failed to allocate exec or object list " | |
3553 | "for %d buffers\n", | |
3554 | args->buffer_count); | |
3555 | ret = -ENOMEM; | |
3556 | goto pre_mutex_err; | |
3557 | } | |
3558 | ret = copy_from_user(exec_list, | |
3559 | (struct drm_i915_relocation_entry __user *) | |
3560 | (uintptr_t) args->buffers_ptr, | |
3561 | sizeof(*exec_list) * args->buffer_count); | |
3562 | if (ret != 0) { | |
3563 | DRM_ERROR("copy %d exec entries failed %d\n", | |
3564 | args->buffer_count, ret); | |
3565 | goto pre_mutex_err; | |
3566 | } | |
3567 | ||
201361a5 | 3568 | if (args->num_cliprects != 0) { |
9a298b2a EA |
3569 | cliprects = kcalloc(args->num_cliprects, sizeof(*cliprects), |
3570 | GFP_KERNEL); | |
201361a5 EA |
3571 | if (cliprects == NULL) |
3572 | goto pre_mutex_err; | |
3573 | ||
3574 | ret = copy_from_user(cliprects, | |
3575 | (struct drm_clip_rect __user *) | |
3576 | (uintptr_t) args->cliprects_ptr, | |
3577 | sizeof(*cliprects) * args->num_cliprects); | |
3578 | if (ret != 0) { | |
3579 | DRM_ERROR("copy %d cliprects failed: %d\n", | |
3580 | args->num_cliprects, ret); | |
3581 | goto pre_mutex_err; | |
3582 | } | |
3583 | } | |
3584 | ||
40a5f0de EA |
3585 | ret = i915_gem_get_relocs_from_user(exec_list, args->buffer_count, |
3586 | &relocs); | |
3587 | if (ret != 0) | |
3588 | goto pre_mutex_err; | |
3589 | ||
673a394b EA |
3590 | mutex_lock(&dev->struct_mutex); |
3591 | ||
3592 | i915_verify_inactive(dev, __FILE__, __LINE__); | |
3593 | ||
ba1234d1 | 3594 | if (atomic_read(&dev_priv->mm.wedged)) { |
673a394b EA |
3595 | DRM_ERROR("Execbuf while wedged\n"); |
3596 | mutex_unlock(&dev->struct_mutex); | |
a198bc80 CW |
3597 | ret = -EIO; |
3598 | goto pre_mutex_err; | |
673a394b EA |
3599 | } |
3600 | ||
3601 | if (dev_priv->mm.suspended) { | |
3602 | DRM_ERROR("Execbuf while VT-switched.\n"); | |
3603 | mutex_unlock(&dev->struct_mutex); | |
a198bc80 CW |
3604 | ret = -EBUSY; |
3605 | goto pre_mutex_err; | |
673a394b EA |
3606 | } |
3607 | ||
ac94a962 | 3608 | /* Look up object handles */ |
673a394b EA |
3609 | for (i = 0; i < args->buffer_count; i++) { |
3610 | object_list[i] = drm_gem_object_lookup(dev, file_priv, | |
3611 | exec_list[i].handle); | |
3612 | if (object_list[i] == NULL) { | |
3613 | DRM_ERROR("Invalid object handle %d at index %d\n", | |
3614 | exec_list[i].handle, i); | |
3615 | ret = -EBADF; | |
3616 | goto err; | |
3617 | } | |
b70d11da KH |
3618 | |
3619 | obj_priv = object_list[i]->driver_private; | |
3620 | if (obj_priv->in_execbuffer) { | |
3621 | DRM_ERROR("Object %p appears more than once in object list\n", | |
3622 | object_list[i]); | |
3623 | ret = -EBADF; | |
3624 | goto err; | |
3625 | } | |
3626 | obj_priv->in_execbuffer = true; | |
ac94a962 | 3627 | } |
673a394b | 3628 | |
ac94a962 KP |
3629 | /* Pin and relocate */ |
3630 | for (pin_tries = 0; ; pin_tries++) { | |
3631 | ret = 0; | |
40a5f0de EA |
3632 | reloc_index = 0; |
3633 | ||
ac94a962 KP |
3634 | for (i = 0; i < args->buffer_count; i++) { |
3635 | object_list[i]->pending_read_domains = 0; | |
3636 | object_list[i]->pending_write_domain = 0; | |
3637 | ret = i915_gem_object_pin_and_relocate(object_list[i], | |
3638 | file_priv, | |
40a5f0de EA |
3639 | &exec_list[i], |
3640 | &relocs[reloc_index]); | |
ac94a962 KP |
3641 | if (ret) |
3642 | break; | |
3643 | pinned = i + 1; | |
40a5f0de | 3644 | reloc_index += exec_list[i].relocation_count; |
ac94a962 KP |
3645 | } |
3646 | /* success */ | |
3647 | if (ret == 0) | |
3648 | break; | |
3649 | ||
3650 | /* error other than GTT full, or we've already tried again */ | |
2939e1f5 | 3651 | if (ret != -ENOSPC || pin_tries >= 1) { |
07f73f69 CW |
3652 | if (ret != -ERESTARTSYS) { |
3653 | unsigned long long total_size = 0; | |
3654 | for (i = 0; i < args->buffer_count; i++) | |
3655 | total_size += object_list[i]->size; | |
3656 | DRM_ERROR("Failed to pin buffer %d of %d, total %llu bytes: %d\n", | |
3657 | pinned+1, args->buffer_count, | |
3658 | total_size, ret); | |
3659 | DRM_ERROR("%d objects [%d pinned], " | |
3660 | "%d object bytes [%d pinned], " | |
3661 | "%d/%d gtt bytes\n", | |
3662 | atomic_read(&dev->object_count), | |
3663 | atomic_read(&dev->pin_count), | |
3664 | atomic_read(&dev->object_memory), | |
3665 | atomic_read(&dev->pin_memory), | |
3666 | atomic_read(&dev->gtt_memory), | |
3667 | dev->gtt_total); | |
3668 | } | |
673a394b EA |
3669 | goto err; |
3670 | } | |
ac94a962 KP |
3671 | |
3672 | /* unpin all of our buffers */ | |
3673 | for (i = 0; i < pinned; i++) | |
3674 | i915_gem_object_unpin(object_list[i]); | |
b1177636 | 3675 | pinned = 0; |
ac94a962 KP |
3676 | |
3677 | /* evict everyone we can from the aperture */ | |
3678 | ret = i915_gem_evict_everything(dev); | |
07f73f69 | 3679 | if (ret && ret != -ENOSPC) |
ac94a962 | 3680 | goto err; |
673a394b EA |
3681 | } |
3682 | ||
3683 | /* Set the pending read domains for the batch buffer to COMMAND */ | |
3684 | batch_obj = object_list[args->buffer_count-1]; | |
5f26a2c7 CW |
3685 | if (batch_obj->pending_write_domain) { |
3686 | DRM_ERROR("Attempting to use self-modifying batch buffer\n"); | |
3687 | ret = -EINVAL; | |
3688 | goto err; | |
3689 | } | |
3690 | batch_obj->pending_read_domains |= I915_GEM_DOMAIN_COMMAND; | |
673a394b | 3691 | |
83d60795 CW |
3692 | /* Sanity check the batch buffer, prior to moving objects */ |
3693 | exec_offset = exec_list[args->buffer_count - 1].offset; | |
3694 | ret = i915_gem_check_execbuffer (args, exec_offset); | |
3695 | if (ret != 0) { | |
3696 | DRM_ERROR("execbuf with invalid offset/length\n"); | |
3697 | goto err; | |
3698 | } | |
3699 | ||
673a394b EA |
3700 | i915_verify_inactive(dev, __FILE__, __LINE__); |
3701 | ||
646f0f6e KP |
3702 | /* Zero the global flush/invalidate flags. These |
3703 | * will be modified as new domains are computed | |
3704 | * for each object | |
3705 | */ | |
3706 | dev->invalidate_domains = 0; | |
3707 | dev->flush_domains = 0; | |
3708 | ||
673a394b EA |
3709 | for (i = 0; i < args->buffer_count; i++) { |
3710 | struct drm_gem_object *obj = object_list[i]; | |
673a394b | 3711 | |
646f0f6e | 3712 | /* Compute new gpu domains and update invalidate/flush */ |
8b0e378a | 3713 | i915_gem_object_set_to_gpu_domain(obj); |
673a394b EA |
3714 | } |
3715 | ||
3716 | i915_verify_inactive(dev, __FILE__, __LINE__); | |
3717 | ||
646f0f6e KP |
3718 | if (dev->invalidate_domains | dev->flush_domains) { |
3719 | #if WATCH_EXEC | |
3720 | DRM_INFO("%s: invalidate_domains %08x flush_domains %08x\n", | |
3721 | __func__, | |
3722 | dev->invalidate_domains, | |
3723 | dev->flush_domains); | |
3724 | #endif | |
3725 | i915_gem_flush(dev, | |
3726 | dev->invalidate_domains, | |
3727 | dev->flush_domains); | |
3728 | if (dev->flush_domains) | |
b962442e EA |
3729 | (void)i915_add_request(dev, file_priv, |
3730 | dev->flush_domains); | |
646f0f6e | 3731 | } |
673a394b | 3732 | |
efbeed96 EA |
3733 | for (i = 0; i < args->buffer_count; i++) { |
3734 | struct drm_gem_object *obj = object_list[i]; | |
1c5d22f7 | 3735 | uint32_t old_write_domain = obj->write_domain; |
efbeed96 EA |
3736 | |
3737 | obj->write_domain = obj->pending_write_domain; | |
1c5d22f7 CW |
3738 | trace_i915_gem_object_change_domain(obj, |
3739 | obj->read_domains, | |
3740 | old_write_domain); | |
efbeed96 EA |
3741 | } |
3742 | ||
673a394b EA |
3743 | i915_verify_inactive(dev, __FILE__, __LINE__); |
3744 | ||
3745 | #if WATCH_COHERENCY | |
3746 | for (i = 0; i < args->buffer_count; i++) { | |
3747 | i915_gem_object_check_coherency(object_list[i], | |
3748 | exec_list[i].handle); | |
3749 | } | |
3750 | #endif | |
3751 | ||
673a394b | 3752 | #if WATCH_EXEC |
6911a9b8 | 3753 | i915_gem_dump_object(batch_obj, |
673a394b EA |
3754 | args->batch_len, |
3755 | __func__, | |
3756 | ~0); | |
3757 | #endif | |
3758 | ||
673a394b | 3759 | /* Exec the batchbuffer */ |
201361a5 | 3760 | ret = i915_dispatch_gem_execbuffer(dev, args, cliprects, exec_offset); |
673a394b EA |
3761 | if (ret) { |
3762 | DRM_ERROR("dispatch failed %d\n", ret); | |
3763 | goto err; | |
3764 | } | |
3765 | ||
3766 | /* | |
3767 | * Ensure that the commands in the batch buffer are | |
3768 | * finished before the interrupt fires | |
3769 | */ | |
3770 | flush_domains = i915_retire_commands(dev); | |
3771 | ||
3772 | i915_verify_inactive(dev, __FILE__, __LINE__); | |
3773 | ||
3774 | /* | |
3775 | * Get a seqno representing the execution of the current buffer, | |
3776 | * which we can wait on. We would like to mitigate these interrupts, | |
3777 | * likely by only creating seqnos occasionally (so that we have | |
3778 | * *some* interrupts representing completion of buffers that we can | |
3779 | * wait on when trying to clear up gtt space). | |
3780 | */ | |
b962442e | 3781 | seqno = i915_add_request(dev, file_priv, flush_domains); |
673a394b | 3782 | BUG_ON(seqno == 0); |
673a394b EA |
3783 | for (i = 0; i < args->buffer_count; i++) { |
3784 | struct drm_gem_object *obj = object_list[i]; | |
673a394b | 3785 | |
ce44b0ea | 3786 | i915_gem_object_move_to_active(obj, seqno); |
673a394b EA |
3787 | #if WATCH_LRU |
3788 | DRM_INFO("%s: move to exec list %p\n", __func__, obj); | |
3789 | #endif | |
3790 | } | |
3791 | #if WATCH_LRU | |
3792 | i915_dump_lru(dev, __func__); | |
3793 | #endif | |
3794 | ||
3795 | i915_verify_inactive(dev, __FILE__, __LINE__); | |
3796 | ||
673a394b | 3797 | err: |
aad87dff JL |
3798 | for (i = 0; i < pinned; i++) |
3799 | i915_gem_object_unpin(object_list[i]); | |
3800 | ||
b70d11da KH |
3801 | for (i = 0; i < args->buffer_count; i++) { |
3802 | if (object_list[i]) { | |
3803 | obj_priv = object_list[i]->driver_private; | |
3804 | obj_priv->in_execbuffer = false; | |
3805 | } | |
aad87dff | 3806 | drm_gem_object_unreference(object_list[i]); |
b70d11da | 3807 | } |
673a394b | 3808 | |
673a394b EA |
3809 | mutex_unlock(&dev->struct_mutex); |
3810 | ||
a35f2e2b RD |
3811 | if (!ret) { |
3812 | /* Copy the new buffer offsets back to the user's exec list. */ | |
3813 | ret = copy_to_user((struct drm_i915_relocation_entry __user *) | |
3814 | (uintptr_t) args->buffers_ptr, | |
3815 | exec_list, | |
3816 | sizeof(*exec_list) * args->buffer_count); | |
2bc43b5c FM |
3817 | if (ret) { |
3818 | ret = -EFAULT; | |
a35f2e2b RD |
3819 | DRM_ERROR("failed to copy %d exec entries " |
3820 | "back to user (%d)\n", | |
3821 | args->buffer_count, ret); | |
2bc43b5c | 3822 | } |
a35f2e2b RD |
3823 | } |
3824 | ||
40a5f0de EA |
3825 | /* Copy the updated relocations out regardless of current error |
3826 | * state. Failure to update the relocs would mean that the next | |
3827 | * time userland calls execbuf, it would do so with presumed offset | |
3828 | * state that didn't match the actual object state. | |
3829 | */ | |
3830 | ret2 = i915_gem_put_relocs_to_user(exec_list, args->buffer_count, | |
3831 | relocs); | |
3832 | if (ret2 != 0) { | |
3833 | DRM_ERROR("Failed to copy relocations back out: %d\n", ret2); | |
3834 | ||
3835 | if (ret == 0) | |
3836 | ret = ret2; | |
3837 | } | |
3838 | ||
673a394b | 3839 | pre_mutex_err: |
8e7d2b2c JB |
3840 | drm_free_large(object_list); |
3841 | drm_free_large(exec_list); | |
9a298b2a | 3842 | kfree(cliprects); |
673a394b EA |
3843 | |
3844 | return ret; | |
3845 | } | |
3846 | ||
3847 | int | |
3848 | i915_gem_object_pin(struct drm_gem_object *obj, uint32_t alignment) | |
3849 | { | |
3850 | struct drm_device *dev = obj->dev; | |
3851 | struct drm_i915_gem_object *obj_priv = obj->driver_private; | |
3852 | int ret; | |
3853 | ||
3854 | i915_verify_inactive(dev, __FILE__, __LINE__); | |
3855 | if (obj_priv->gtt_space == NULL) { | |
3856 | ret = i915_gem_object_bind_to_gtt(obj, alignment); | |
9731129c | 3857 | if (ret) |
673a394b | 3858 | return ret; |
22c344e9 CW |
3859 | } |
3860 | /* | |
3861 | * Pre-965 chips need a fence register set up in order to | |
3862 | * properly handle tiled surfaces. | |
3863 | */ | |
a09ba7fa | 3864 | if (!IS_I965G(dev) && obj_priv->tiling_mode != I915_TILING_NONE) { |
8c4b8c3f | 3865 | ret = i915_gem_object_get_fence_reg(obj); |
22c344e9 CW |
3866 | if (ret != 0) { |
3867 | if (ret != -EBUSY && ret != -ERESTARTSYS) | |
3868 | DRM_ERROR("Failure to install fence: %d\n", | |
3869 | ret); | |
3870 | return ret; | |
3871 | } | |
673a394b EA |
3872 | } |
3873 | obj_priv->pin_count++; | |
3874 | ||
3875 | /* If the object is not active and not pending a flush, | |
3876 | * remove it from the inactive list | |
3877 | */ | |
3878 | if (obj_priv->pin_count == 1) { | |
3879 | atomic_inc(&dev->pin_count); | |
3880 | atomic_add(obj->size, &dev->pin_memory); | |
3881 | if (!obj_priv->active && | |
21d509e3 | 3882 | (obj->write_domain & I915_GEM_GPU_DOMAINS) == 0 && |
673a394b EA |
3883 | !list_empty(&obj_priv->list)) |
3884 | list_del_init(&obj_priv->list); | |
3885 | } | |
3886 | i915_verify_inactive(dev, __FILE__, __LINE__); | |
3887 | ||
3888 | return 0; | |
3889 | } | |
3890 | ||
3891 | void | |
3892 | i915_gem_object_unpin(struct drm_gem_object *obj) | |
3893 | { | |
3894 | struct drm_device *dev = obj->dev; | |
3895 | drm_i915_private_t *dev_priv = dev->dev_private; | |
3896 | struct drm_i915_gem_object *obj_priv = obj->driver_private; | |
3897 | ||
3898 | i915_verify_inactive(dev, __FILE__, __LINE__); | |
3899 | obj_priv->pin_count--; | |
3900 | BUG_ON(obj_priv->pin_count < 0); | |
3901 | BUG_ON(obj_priv->gtt_space == NULL); | |
3902 | ||
3903 | /* If the object is no longer pinned, and is | |
3904 | * neither active nor being flushed, then stick it on | |
3905 | * the inactive list | |
3906 | */ | |
3907 | if (obj_priv->pin_count == 0) { | |
3908 | if (!obj_priv->active && | |
21d509e3 | 3909 | (obj->write_domain & I915_GEM_GPU_DOMAINS) == 0) |
673a394b EA |
3910 | list_move_tail(&obj_priv->list, |
3911 | &dev_priv->mm.inactive_list); | |
3912 | atomic_dec(&dev->pin_count); | |
3913 | atomic_sub(obj->size, &dev->pin_memory); | |
3914 | } | |
3915 | i915_verify_inactive(dev, __FILE__, __LINE__); | |
3916 | } | |
3917 | ||
3918 | int | |
3919 | i915_gem_pin_ioctl(struct drm_device *dev, void *data, | |
3920 | struct drm_file *file_priv) | |
3921 | { | |
3922 | struct drm_i915_gem_pin *args = data; | |
3923 | struct drm_gem_object *obj; | |
3924 | struct drm_i915_gem_object *obj_priv; | |
3925 | int ret; | |
3926 | ||
3927 | mutex_lock(&dev->struct_mutex); | |
3928 | ||
3929 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); | |
3930 | if (obj == NULL) { | |
3931 | DRM_ERROR("Bad handle in i915_gem_pin_ioctl(): %d\n", | |
3932 | args->handle); | |
3933 | mutex_unlock(&dev->struct_mutex); | |
3934 | return -EBADF; | |
3935 | } | |
3936 | obj_priv = obj->driver_private; | |
3937 | ||
bb6baf76 CW |
3938 | if (obj_priv->madv != I915_MADV_WILLNEED) { |
3939 | DRM_ERROR("Attempting to pin a purgeable buffer\n"); | |
3ef94daa CW |
3940 | drm_gem_object_unreference(obj); |
3941 | mutex_unlock(&dev->struct_mutex); | |
3942 | return -EINVAL; | |
3943 | } | |
3944 | ||
79e53945 JB |
3945 | if (obj_priv->pin_filp != NULL && obj_priv->pin_filp != file_priv) { |
3946 | DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n", | |
3947 | args->handle); | |
96dec61d | 3948 | drm_gem_object_unreference(obj); |
673a394b | 3949 | mutex_unlock(&dev->struct_mutex); |
79e53945 JB |
3950 | return -EINVAL; |
3951 | } | |
3952 | ||
3953 | obj_priv->user_pin_count++; | |
3954 | obj_priv->pin_filp = file_priv; | |
3955 | if (obj_priv->user_pin_count == 1) { | |
3956 | ret = i915_gem_object_pin(obj, args->alignment); | |
3957 | if (ret != 0) { | |
3958 | drm_gem_object_unreference(obj); | |
3959 | mutex_unlock(&dev->struct_mutex); | |
3960 | return ret; | |
3961 | } | |
673a394b EA |
3962 | } |
3963 | ||
3964 | /* XXX - flush the CPU caches for pinned objects | |
3965 | * as the X server doesn't manage domains yet | |
3966 | */ | |
e47c68e9 | 3967 | i915_gem_object_flush_cpu_write_domain(obj); |
673a394b EA |
3968 | args->offset = obj_priv->gtt_offset; |
3969 | drm_gem_object_unreference(obj); | |
3970 | mutex_unlock(&dev->struct_mutex); | |
3971 | ||
3972 | return 0; | |
3973 | } | |
3974 | ||
3975 | int | |
3976 | i915_gem_unpin_ioctl(struct drm_device *dev, void *data, | |
3977 | struct drm_file *file_priv) | |
3978 | { | |
3979 | struct drm_i915_gem_pin *args = data; | |
3980 | struct drm_gem_object *obj; | |
79e53945 | 3981 | struct drm_i915_gem_object *obj_priv; |
673a394b EA |
3982 | |
3983 | mutex_lock(&dev->struct_mutex); | |
3984 | ||
3985 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); | |
3986 | if (obj == NULL) { | |
3987 | DRM_ERROR("Bad handle in i915_gem_unpin_ioctl(): %d\n", | |
3988 | args->handle); | |
3989 | mutex_unlock(&dev->struct_mutex); | |
3990 | return -EBADF; | |
3991 | } | |
3992 | ||
79e53945 JB |
3993 | obj_priv = obj->driver_private; |
3994 | if (obj_priv->pin_filp != file_priv) { | |
3995 | DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n", | |
3996 | args->handle); | |
3997 | drm_gem_object_unreference(obj); | |
3998 | mutex_unlock(&dev->struct_mutex); | |
3999 | return -EINVAL; | |
4000 | } | |
4001 | obj_priv->user_pin_count--; | |
4002 | if (obj_priv->user_pin_count == 0) { | |
4003 | obj_priv->pin_filp = NULL; | |
4004 | i915_gem_object_unpin(obj); | |
4005 | } | |
673a394b EA |
4006 | |
4007 | drm_gem_object_unreference(obj); | |
4008 | mutex_unlock(&dev->struct_mutex); | |
4009 | return 0; | |
4010 | } | |
4011 | ||
4012 | int | |
4013 | i915_gem_busy_ioctl(struct drm_device *dev, void *data, | |
4014 | struct drm_file *file_priv) | |
4015 | { | |
4016 | struct drm_i915_gem_busy *args = data; | |
4017 | struct drm_gem_object *obj; | |
4018 | struct drm_i915_gem_object *obj_priv; | |
4019 | ||
673a394b EA |
4020 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); |
4021 | if (obj == NULL) { | |
4022 | DRM_ERROR("Bad handle in i915_gem_busy_ioctl(): %d\n", | |
4023 | args->handle); | |
673a394b EA |
4024 | return -EBADF; |
4025 | } | |
4026 | ||
b1ce786c | 4027 | mutex_lock(&dev->struct_mutex); |
f21289b3 EA |
4028 | /* Update the active list for the hardware's current position. |
4029 | * Otherwise this only updates on a delayed timer or when irqs are | |
4030 | * actually unmasked, and our working set ends up being larger than | |
4031 | * required. | |
4032 | */ | |
4033 | i915_gem_retire_requests(dev); | |
4034 | ||
673a394b | 4035 | obj_priv = obj->driver_private; |
c4de0a5d EA |
4036 | /* Don't count being on the flushing list against the object being |
4037 | * done. Otherwise, a buffer left on the flushing list but not getting | |
4038 | * flushed (because nobody's flushing that domain) won't ever return | |
4039 | * unbusy and get reused by libdrm's bo cache. The other expected | |
4040 | * consumer of this interface, OpenGL's occlusion queries, also specs | |
4041 | * that the objects get unbusy "eventually" without any interference. | |
4042 | */ | |
4043 | args->busy = obj_priv->active && obj_priv->last_rendering_seqno != 0; | |
673a394b EA |
4044 | |
4045 | drm_gem_object_unreference(obj); | |
4046 | mutex_unlock(&dev->struct_mutex); | |
4047 | return 0; | |
4048 | } | |
4049 | ||
4050 | int | |
4051 | i915_gem_throttle_ioctl(struct drm_device *dev, void *data, | |
4052 | struct drm_file *file_priv) | |
4053 | { | |
4054 | return i915_gem_ring_throttle(dev, file_priv); | |
4055 | } | |
4056 | ||
3ef94daa CW |
4057 | int |
4058 | i915_gem_madvise_ioctl(struct drm_device *dev, void *data, | |
4059 | struct drm_file *file_priv) | |
4060 | { | |
4061 | struct drm_i915_gem_madvise *args = data; | |
4062 | struct drm_gem_object *obj; | |
4063 | struct drm_i915_gem_object *obj_priv; | |
4064 | ||
4065 | switch (args->madv) { | |
4066 | case I915_MADV_DONTNEED: | |
4067 | case I915_MADV_WILLNEED: | |
4068 | break; | |
4069 | default: | |
4070 | return -EINVAL; | |
4071 | } | |
4072 | ||
4073 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); | |
4074 | if (obj == NULL) { | |
4075 | DRM_ERROR("Bad handle in i915_gem_madvise_ioctl(): %d\n", | |
4076 | args->handle); | |
4077 | return -EBADF; | |
4078 | } | |
4079 | ||
4080 | mutex_lock(&dev->struct_mutex); | |
4081 | obj_priv = obj->driver_private; | |
4082 | ||
4083 | if (obj_priv->pin_count) { | |
4084 | drm_gem_object_unreference(obj); | |
4085 | mutex_unlock(&dev->struct_mutex); | |
4086 | ||
4087 | DRM_ERROR("Attempted i915_gem_madvise_ioctl() on a pinned object\n"); | |
4088 | return -EINVAL; | |
4089 | } | |
4090 | ||
bb6baf76 CW |
4091 | if (obj_priv->madv != __I915_MADV_PURGED) |
4092 | obj_priv->madv = args->madv; | |
3ef94daa | 4093 | |
2d7ef395 CW |
4094 | /* if the object is no longer bound, discard its backing storage */ |
4095 | if (i915_gem_object_is_purgeable(obj_priv) && | |
4096 | obj_priv->gtt_space == NULL) | |
4097 | i915_gem_object_truncate(obj); | |
4098 | ||
bb6baf76 CW |
4099 | args->retained = obj_priv->madv != __I915_MADV_PURGED; |
4100 | ||
3ef94daa CW |
4101 | drm_gem_object_unreference(obj); |
4102 | mutex_unlock(&dev->struct_mutex); | |
4103 | ||
4104 | return 0; | |
4105 | } | |
4106 | ||
673a394b EA |
4107 | int i915_gem_init_object(struct drm_gem_object *obj) |
4108 | { | |
4109 | struct drm_i915_gem_object *obj_priv; | |
4110 | ||
9a298b2a | 4111 | obj_priv = kzalloc(sizeof(*obj_priv), GFP_KERNEL); |
673a394b EA |
4112 | if (obj_priv == NULL) |
4113 | return -ENOMEM; | |
4114 | ||
4115 | /* | |
4116 | * We've just allocated pages from the kernel, | |
4117 | * so they've just been written by the CPU with | |
4118 | * zeros. They'll need to be clflushed before we | |
4119 | * use them with the GPU. | |
4120 | */ | |
4121 | obj->write_domain = I915_GEM_DOMAIN_CPU; | |
4122 | obj->read_domains = I915_GEM_DOMAIN_CPU; | |
4123 | ||
ba1eb1d8 KP |
4124 | obj_priv->agp_type = AGP_USER_MEMORY; |
4125 | ||
673a394b EA |
4126 | obj->driver_private = obj_priv; |
4127 | obj_priv->obj = obj; | |
de151cf6 | 4128 | obj_priv->fence_reg = I915_FENCE_REG_NONE; |
673a394b | 4129 | INIT_LIST_HEAD(&obj_priv->list); |
a09ba7fa | 4130 | INIT_LIST_HEAD(&obj_priv->fence_list); |
3ef94daa | 4131 | obj_priv->madv = I915_MADV_WILLNEED; |
de151cf6 | 4132 | |
1c5d22f7 | 4133 | trace_i915_gem_object_create(obj); |
de151cf6 | 4134 | |
673a394b EA |
4135 | return 0; |
4136 | } | |
4137 | ||
4138 | void i915_gem_free_object(struct drm_gem_object *obj) | |
4139 | { | |
de151cf6 | 4140 | struct drm_device *dev = obj->dev; |
673a394b EA |
4141 | struct drm_i915_gem_object *obj_priv = obj->driver_private; |
4142 | ||
1c5d22f7 CW |
4143 | trace_i915_gem_object_destroy(obj); |
4144 | ||
673a394b EA |
4145 | while (obj_priv->pin_count > 0) |
4146 | i915_gem_object_unpin(obj); | |
4147 | ||
71acb5eb DA |
4148 | if (obj_priv->phys_obj) |
4149 | i915_gem_detach_phys_object(dev, obj); | |
4150 | ||
673a394b EA |
4151 | i915_gem_object_unbind(obj); |
4152 | ||
7e616158 CW |
4153 | if (obj_priv->mmap_offset) |
4154 | i915_gem_free_mmap_offset(obj); | |
de151cf6 | 4155 | |
9a298b2a | 4156 | kfree(obj_priv->page_cpu_valid); |
280b713b | 4157 | kfree(obj_priv->bit_17); |
9a298b2a | 4158 | kfree(obj->driver_private); |
673a394b EA |
4159 | } |
4160 | ||
ab5ee576 | 4161 | /** Unbinds all inactive objects. */ |
673a394b | 4162 | static int |
ab5ee576 | 4163 | i915_gem_evict_from_inactive_list(struct drm_device *dev) |
673a394b | 4164 | { |
ab5ee576 | 4165 | drm_i915_private_t *dev_priv = dev->dev_private; |
673a394b | 4166 | |
ab5ee576 CW |
4167 | while (!list_empty(&dev_priv->mm.inactive_list)) { |
4168 | struct drm_gem_object *obj; | |
4169 | int ret; | |
673a394b | 4170 | |
ab5ee576 CW |
4171 | obj = list_first_entry(&dev_priv->mm.inactive_list, |
4172 | struct drm_i915_gem_object, | |
4173 | list)->obj; | |
673a394b EA |
4174 | |
4175 | ret = i915_gem_object_unbind(obj); | |
4176 | if (ret != 0) { | |
ab5ee576 | 4177 | DRM_ERROR("Error unbinding object: %d\n", ret); |
673a394b EA |
4178 | return ret; |
4179 | } | |
4180 | } | |
4181 | ||
673a394b EA |
4182 | return 0; |
4183 | } | |
4184 | ||
5669fcac | 4185 | int |
673a394b EA |
4186 | i915_gem_idle(struct drm_device *dev) |
4187 | { | |
4188 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4189 | uint32_t seqno, cur_seqno, last_seqno; | |
4190 | int stuck, ret; | |
4191 | ||
6dbe2772 KP |
4192 | mutex_lock(&dev->struct_mutex); |
4193 | ||
4194 | if (dev_priv->mm.suspended || dev_priv->ring.ring_obj == NULL) { | |
4195 | mutex_unlock(&dev->struct_mutex); | |
673a394b | 4196 | return 0; |
6dbe2772 | 4197 | } |
673a394b EA |
4198 | |
4199 | /* Hack! Don't let anybody do execbuf while we don't control the chip. | |
4200 | * We need to replace this with a semaphore, or something. | |
4201 | */ | |
4202 | dev_priv->mm.suspended = 1; | |
f65d9421 | 4203 | del_timer(&dev_priv->hangcheck_timer); |
673a394b | 4204 | |
6dbe2772 KP |
4205 | /* Cancel the retire work handler, wait for it to finish if running |
4206 | */ | |
4207 | mutex_unlock(&dev->struct_mutex); | |
4208 | cancel_delayed_work_sync(&dev_priv->mm.retire_work); | |
4209 | mutex_lock(&dev->struct_mutex); | |
4210 | ||
673a394b EA |
4211 | i915_kernel_lost_context(dev); |
4212 | ||
4213 | /* Flush the GPU along with all non-CPU write domains | |
4214 | */ | |
21d509e3 CW |
4215 | i915_gem_flush(dev, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS); |
4216 | seqno = i915_add_request(dev, NULL, I915_GEM_GPU_DOMAINS); | |
673a394b EA |
4217 | |
4218 | if (seqno == 0) { | |
4219 | mutex_unlock(&dev->struct_mutex); | |
4220 | return -ENOMEM; | |
4221 | } | |
4222 | ||
4223 | dev_priv->mm.waiting_gem_seqno = seqno; | |
4224 | last_seqno = 0; | |
4225 | stuck = 0; | |
4226 | for (;;) { | |
4227 | cur_seqno = i915_get_gem_seqno(dev); | |
4228 | if (i915_seqno_passed(cur_seqno, seqno)) | |
4229 | break; | |
4230 | if (last_seqno == cur_seqno) { | |
4231 | if (stuck++ > 100) { | |
4232 | DRM_ERROR("hardware wedged\n"); | |
ba1234d1 | 4233 | atomic_set(&dev_priv->mm.wedged, 1); |
673a394b EA |
4234 | DRM_WAKEUP(&dev_priv->irq_queue); |
4235 | break; | |
4236 | } | |
4237 | } | |
4238 | msleep(10); | |
4239 | last_seqno = cur_seqno; | |
4240 | } | |
4241 | dev_priv->mm.waiting_gem_seqno = 0; | |
4242 | ||
4243 | i915_gem_retire_requests(dev); | |
4244 | ||
5e118f41 | 4245 | spin_lock(&dev_priv->mm.active_list_lock); |
ba1234d1 | 4246 | if (!atomic_read(&dev_priv->mm.wedged)) { |
28dfe52a EA |
4247 | /* Active and flushing should now be empty as we've |
4248 | * waited for a sequence higher than any pending execbuffer | |
4249 | */ | |
4250 | WARN_ON(!list_empty(&dev_priv->mm.active_list)); | |
4251 | WARN_ON(!list_empty(&dev_priv->mm.flushing_list)); | |
4252 | /* Request should now be empty as we've also waited | |
4253 | * for the last request in the list | |
4254 | */ | |
4255 | WARN_ON(!list_empty(&dev_priv->mm.request_list)); | |
4256 | } | |
673a394b | 4257 | |
28dfe52a EA |
4258 | /* Empty the active and flushing lists to inactive. If there's |
4259 | * anything left at this point, it means that we're wedged and | |
4260 | * nothing good's going to happen by leaving them there. So strip | |
4261 | * the GPU domains and just stuff them onto inactive. | |
673a394b | 4262 | */ |
28dfe52a | 4263 | while (!list_empty(&dev_priv->mm.active_list)) { |
1c5d22f7 CW |
4264 | struct drm_gem_object *obj; |
4265 | uint32_t old_write_domain; | |
673a394b | 4266 | |
1c5d22f7 CW |
4267 | obj = list_first_entry(&dev_priv->mm.active_list, |
4268 | struct drm_i915_gem_object, | |
4269 | list)->obj; | |
4270 | old_write_domain = obj->write_domain; | |
4271 | obj->write_domain &= ~I915_GEM_GPU_DOMAINS; | |
4272 | i915_gem_object_move_to_inactive(obj); | |
4273 | ||
4274 | trace_i915_gem_object_change_domain(obj, | |
4275 | obj->read_domains, | |
4276 | old_write_domain); | |
28dfe52a | 4277 | } |
5e118f41 | 4278 | spin_unlock(&dev_priv->mm.active_list_lock); |
28dfe52a EA |
4279 | |
4280 | while (!list_empty(&dev_priv->mm.flushing_list)) { | |
1c5d22f7 CW |
4281 | struct drm_gem_object *obj; |
4282 | uint32_t old_write_domain; | |
28dfe52a | 4283 | |
1c5d22f7 CW |
4284 | obj = list_first_entry(&dev_priv->mm.flushing_list, |
4285 | struct drm_i915_gem_object, | |
4286 | list)->obj; | |
4287 | old_write_domain = obj->write_domain; | |
4288 | obj->write_domain &= ~I915_GEM_GPU_DOMAINS; | |
4289 | i915_gem_object_move_to_inactive(obj); | |
4290 | ||
4291 | trace_i915_gem_object_change_domain(obj, | |
4292 | obj->read_domains, | |
4293 | old_write_domain); | |
28dfe52a EA |
4294 | } |
4295 | ||
4296 | ||
4297 | /* Move all inactive buffers out of the GTT. */ | |
ab5ee576 | 4298 | ret = i915_gem_evict_from_inactive_list(dev); |
28dfe52a | 4299 | WARN_ON(!list_empty(&dev_priv->mm.inactive_list)); |
6dbe2772 KP |
4300 | if (ret) { |
4301 | mutex_unlock(&dev->struct_mutex); | |
673a394b | 4302 | return ret; |
6dbe2772 | 4303 | } |
673a394b | 4304 | |
6dbe2772 KP |
4305 | i915_gem_cleanup_ringbuffer(dev); |
4306 | mutex_unlock(&dev->struct_mutex); | |
4307 | ||
673a394b EA |
4308 | return 0; |
4309 | } | |
4310 | ||
4311 | static int | |
4312 | i915_gem_init_hws(struct drm_device *dev) | |
4313 | { | |
4314 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4315 | struct drm_gem_object *obj; | |
4316 | struct drm_i915_gem_object *obj_priv; | |
4317 | int ret; | |
4318 | ||
4319 | /* If we need a physical address for the status page, it's already | |
4320 | * initialized at driver load time. | |
4321 | */ | |
4322 | if (!I915_NEED_GFX_HWS(dev)) | |
4323 | return 0; | |
4324 | ||
4325 | obj = drm_gem_object_alloc(dev, 4096); | |
4326 | if (obj == NULL) { | |
4327 | DRM_ERROR("Failed to allocate status page\n"); | |
4328 | return -ENOMEM; | |
4329 | } | |
4330 | obj_priv = obj->driver_private; | |
ba1eb1d8 | 4331 | obj_priv->agp_type = AGP_USER_CACHED_MEMORY; |
673a394b EA |
4332 | |
4333 | ret = i915_gem_object_pin(obj, 4096); | |
4334 | if (ret != 0) { | |
4335 | drm_gem_object_unreference(obj); | |
4336 | return ret; | |
4337 | } | |
4338 | ||
4339 | dev_priv->status_gfx_addr = obj_priv->gtt_offset; | |
673a394b | 4340 | |
856fa198 | 4341 | dev_priv->hw_status_page = kmap(obj_priv->pages[0]); |
ba1eb1d8 | 4342 | if (dev_priv->hw_status_page == NULL) { |
673a394b EA |
4343 | DRM_ERROR("Failed to map status page.\n"); |
4344 | memset(&dev_priv->hws_map, 0, sizeof(dev_priv->hws_map)); | |
3eb2ee77 | 4345 | i915_gem_object_unpin(obj); |
673a394b EA |
4346 | drm_gem_object_unreference(obj); |
4347 | return -EINVAL; | |
4348 | } | |
4349 | dev_priv->hws_obj = obj; | |
673a394b EA |
4350 | memset(dev_priv->hw_status_page, 0, PAGE_SIZE); |
4351 | I915_WRITE(HWS_PGA, dev_priv->status_gfx_addr); | |
ba1eb1d8 | 4352 | I915_READ(HWS_PGA); /* posting read */ |
673a394b EA |
4353 | DRM_DEBUG("hws offset: 0x%08x\n", dev_priv->status_gfx_addr); |
4354 | ||
4355 | return 0; | |
4356 | } | |
4357 | ||
85a7bb98 CW |
4358 | static void |
4359 | i915_gem_cleanup_hws(struct drm_device *dev) | |
4360 | { | |
4361 | drm_i915_private_t *dev_priv = dev->dev_private; | |
bab2d1f6 CW |
4362 | struct drm_gem_object *obj; |
4363 | struct drm_i915_gem_object *obj_priv; | |
85a7bb98 CW |
4364 | |
4365 | if (dev_priv->hws_obj == NULL) | |
4366 | return; | |
4367 | ||
bab2d1f6 CW |
4368 | obj = dev_priv->hws_obj; |
4369 | obj_priv = obj->driver_private; | |
4370 | ||
856fa198 | 4371 | kunmap(obj_priv->pages[0]); |
85a7bb98 CW |
4372 | i915_gem_object_unpin(obj); |
4373 | drm_gem_object_unreference(obj); | |
4374 | dev_priv->hws_obj = NULL; | |
bab2d1f6 | 4375 | |
85a7bb98 CW |
4376 | memset(&dev_priv->hws_map, 0, sizeof(dev_priv->hws_map)); |
4377 | dev_priv->hw_status_page = NULL; | |
4378 | ||
4379 | /* Write high address into HWS_PGA when disabling. */ | |
4380 | I915_WRITE(HWS_PGA, 0x1ffff000); | |
4381 | } | |
4382 | ||
79e53945 | 4383 | int |
673a394b EA |
4384 | i915_gem_init_ringbuffer(struct drm_device *dev) |
4385 | { | |
4386 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4387 | struct drm_gem_object *obj; | |
4388 | struct drm_i915_gem_object *obj_priv; | |
79e53945 | 4389 | drm_i915_ring_buffer_t *ring = &dev_priv->ring; |
673a394b | 4390 | int ret; |
50aa253d | 4391 | u32 head; |
673a394b EA |
4392 | |
4393 | ret = i915_gem_init_hws(dev); | |
4394 | if (ret != 0) | |
4395 | return ret; | |
4396 | ||
4397 | obj = drm_gem_object_alloc(dev, 128 * 1024); | |
4398 | if (obj == NULL) { | |
4399 | DRM_ERROR("Failed to allocate ringbuffer\n"); | |
85a7bb98 | 4400 | i915_gem_cleanup_hws(dev); |
673a394b EA |
4401 | return -ENOMEM; |
4402 | } | |
4403 | obj_priv = obj->driver_private; | |
4404 | ||
4405 | ret = i915_gem_object_pin(obj, 4096); | |
4406 | if (ret != 0) { | |
4407 | drm_gem_object_unreference(obj); | |
85a7bb98 | 4408 | i915_gem_cleanup_hws(dev); |
673a394b EA |
4409 | return ret; |
4410 | } | |
4411 | ||
4412 | /* Set up the kernel mapping for the ring. */ | |
79e53945 | 4413 | ring->Size = obj->size; |
673a394b | 4414 | |
79e53945 JB |
4415 | ring->map.offset = dev->agp->base + obj_priv->gtt_offset; |
4416 | ring->map.size = obj->size; | |
4417 | ring->map.type = 0; | |
4418 | ring->map.flags = 0; | |
4419 | ring->map.mtrr = 0; | |
673a394b | 4420 | |
79e53945 JB |
4421 | drm_core_ioremap_wc(&ring->map, dev); |
4422 | if (ring->map.handle == NULL) { | |
673a394b EA |
4423 | DRM_ERROR("Failed to map ringbuffer.\n"); |
4424 | memset(&dev_priv->ring, 0, sizeof(dev_priv->ring)); | |
47ed185a | 4425 | i915_gem_object_unpin(obj); |
673a394b | 4426 | drm_gem_object_unreference(obj); |
85a7bb98 | 4427 | i915_gem_cleanup_hws(dev); |
673a394b EA |
4428 | return -EINVAL; |
4429 | } | |
79e53945 JB |
4430 | ring->ring_obj = obj; |
4431 | ring->virtual_start = ring->map.handle; | |
673a394b EA |
4432 | |
4433 | /* Stop the ring if it's running. */ | |
4434 | I915_WRITE(PRB0_CTL, 0); | |
673a394b | 4435 | I915_WRITE(PRB0_TAIL, 0); |
50aa253d | 4436 | I915_WRITE(PRB0_HEAD, 0); |
673a394b EA |
4437 | |
4438 | /* Initialize the ring. */ | |
4439 | I915_WRITE(PRB0_START, obj_priv->gtt_offset); | |
50aa253d KP |
4440 | head = I915_READ(PRB0_HEAD) & HEAD_ADDR; |
4441 | ||
4442 | /* G45 ring initialization fails to reset head to zero */ | |
4443 | if (head != 0) { | |
4444 | DRM_ERROR("Ring head not reset to zero " | |
4445 | "ctl %08x head %08x tail %08x start %08x\n", | |
4446 | I915_READ(PRB0_CTL), | |
4447 | I915_READ(PRB0_HEAD), | |
4448 | I915_READ(PRB0_TAIL), | |
4449 | I915_READ(PRB0_START)); | |
4450 | I915_WRITE(PRB0_HEAD, 0); | |
4451 | ||
4452 | DRM_ERROR("Ring head forced to zero " | |
4453 | "ctl %08x head %08x tail %08x start %08x\n", | |
4454 | I915_READ(PRB0_CTL), | |
4455 | I915_READ(PRB0_HEAD), | |
4456 | I915_READ(PRB0_TAIL), | |
4457 | I915_READ(PRB0_START)); | |
4458 | } | |
4459 | ||
673a394b EA |
4460 | I915_WRITE(PRB0_CTL, |
4461 | ((obj->size - 4096) & RING_NR_PAGES) | | |
4462 | RING_NO_REPORT | | |
4463 | RING_VALID); | |
4464 | ||
50aa253d KP |
4465 | head = I915_READ(PRB0_HEAD) & HEAD_ADDR; |
4466 | ||
4467 | /* If the head is still not zero, the ring is dead */ | |
4468 | if (head != 0) { | |
4469 | DRM_ERROR("Ring initialization failed " | |
4470 | "ctl %08x head %08x tail %08x start %08x\n", | |
4471 | I915_READ(PRB0_CTL), | |
4472 | I915_READ(PRB0_HEAD), | |
4473 | I915_READ(PRB0_TAIL), | |
4474 | I915_READ(PRB0_START)); | |
4475 | return -EIO; | |
4476 | } | |
4477 | ||
673a394b | 4478 | /* Update our cache of the ring state */ |
79e53945 JB |
4479 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) |
4480 | i915_kernel_lost_context(dev); | |
4481 | else { | |
4482 | ring->head = I915_READ(PRB0_HEAD) & HEAD_ADDR; | |
4483 | ring->tail = I915_READ(PRB0_TAIL) & TAIL_ADDR; | |
4484 | ring->space = ring->head - (ring->tail + 8); | |
4485 | if (ring->space < 0) | |
4486 | ring->space += ring->Size; | |
4487 | } | |
673a394b EA |
4488 | |
4489 | return 0; | |
4490 | } | |
4491 | ||
79e53945 | 4492 | void |
673a394b EA |
4493 | i915_gem_cleanup_ringbuffer(struct drm_device *dev) |
4494 | { | |
4495 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4496 | ||
4497 | if (dev_priv->ring.ring_obj == NULL) | |
4498 | return; | |
4499 | ||
4500 | drm_core_ioremapfree(&dev_priv->ring.map, dev); | |
4501 | ||
4502 | i915_gem_object_unpin(dev_priv->ring.ring_obj); | |
4503 | drm_gem_object_unreference(dev_priv->ring.ring_obj); | |
4504 | dev_priv->ring.ring_obj = NULL; | |
4505 | memset(&dev_priv->ring, 0, sizeof(dev_priv->ring)); | |
4506 | ||
85a7bb98 | 4507 | i915_gem_cleanup_hws(dev); |
673a394b EA |
4508 | } |
4509 | ||
4510 | int | |
4511 | i915_gem_entervt_ioctl(struct drm_device *dev, void *data, | |
4512 | struct drm_file *file_priv) | |
4513 | { | |
4514 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4515 | int ret; | |
4516 | ||
79e53945 JB |
4517 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
4518 | return 0; | |
4519 | ||
ba1234d1 | 4520 | if (atomic_read(&dev_priv->mm.wedged)) { |
673a394b | 4521 | DRM_ERROR("Reenabling wedged hardware, good luck\n"); |
ba1234d1 | 4522 | atomic_set(&dev_priv->mm.wedged, 0); |
673a394b EA |
4523 | } |
4524 | ||
673a394b | 4525 | mutex_lock(&dev->struct_mutex); |
9bb2d6f9 EA |
4526 | dev_priv->mm.suspended = 0; |
4527 | ||
4528 | ret = i915_gem_init_ringbuffer(dev); | |
d816f6ac WF |
4529 | if (ret != 0) { |
4530 | mutex_unlock(&dev->struct_mutex); | |
9bb2d6f9 | 4531 | return ret; |
d816f6ac | 4532 | } |
9bb2d6f9 | 4533 | |
5e118f41 | 4534 | spin_lock(&dev_priv->mm.active_list_lock); |
673a394b | 4535 | BUG_ON(!list_empty(&dev_priv->mm.active_list)); |
5e118f41 CW |
4536 | spin_unlock(&dev_priv->mm.active_list_lock); |
4537 | ||
673a394b EA |
4538 | BUG_ON(!list_empty(&dev_priv->mm.flushing_list)); |
4539 | BUG_ON(!list_empty(&dev_priv->mm.inactive_list)); | |
4540 | BUG_ON(!list_empty(&dev_priv->mm.request_list)); | |
673a394b | 4541 | mutex_unlock(&dev->struct_mutex); |
dbb19d30 KH |
4542 | |
4543 | drm_irq_install(dev); | |
4544 | ||
673a394b EA |
4545 | return 0; |
4546 | } | |
4547 | ||
4548 | int | |
4549 | i915_gem_leavevt_ioctl(struct drm_device *dev, void *data, | |
4550 | struct drm_file *file_priv) | |
4551 | { | |
79e53945 JB |
4552 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
4553 | return 0; | |
4554 | ||
dbb19d30 | 4555 | drm_irq_uninstall(dev); |
e6890f6f | 4556 | return i915_gem_idle(dev); |
673a394b EA |
4557 | } |
4558 | ||
4559 | void | |
4560 | i915_gem_lastclose(struct drm_device *dev) | |
4561 | { | |
4562 | int ret; | |
673a394b | 4563 | |
e806b495 EA |
4564 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
4565 | return; | |
4566 | ||
6dbe2772 KP |
4567 | ret = i915_gem_idle(dev); |
4568 | if (ret) | |
4569 | DRM_ERROR("failed to idle hardware: %d\n", ret); | |
673a394b EA |
4570 | } |
4571 | ||
4572 | void | |
4573 | i915_gem_load(struct drm_device *dev) | |
4574 | { | |
b5aa8a0f | 4575 | int i; |
673a394b EA |
4576 | drm_i915_private_t *dev_priv = dev->dev_private; |
4577 | ||
5e118f41 | 4578 | spin_lock_init(&dev_priv->mm.active_list_lock); |
673a394b EA |
4579 | INIT_LIST_HEAD(&dev_priv->mm.active_list); |
4580 | INIT_LIST_HEAD(&dev_priv->mm.flushing_list); | |
4581 | INIT_LIST_HEAD(&dev_priv->mm.inactive_list); | |
4582 | INIT_LIST_HEAD(&dev_priv->mm.request_list); | |
a09ba7fa | 4583 | INIT_LIST_HEAD(&dev_priv->mm.fence_list); |
673a394b EA |
4584 | INIT_DELAYED_WORK(&dev_priv->mm.retire_work, |
4585 | i915_gem_retire_work_handler); | |
4586 | dev_priv->mm.next_gem_seqno = 1; | |
4587 | ||
31169714 CW |
4588 | spin_lock(&shrink_list_lock); |
4589 | list_add(&dev_priv->mm.shrink_list, &shrink_list); | |
4590 | spin_unlock(&shrink_list_lock); | |
4591 | ||
de151cf6 JB |
4592 | /* Old X drivers will take 0-2 for front, back, depth buffers */ |
4593 | dev_priv->fence_reg_start = 3; | |
4594 | ||
0f973f27 | 4595 | if (IS_I965G(dev) || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) |
de151cf6 JB |
4596 | dev_priv->num_fence_regs = 16; |
4597 | else | |
4598 | dev_priv->num_fence_regs = 8; | |
4599 | ||
b5aa8a0f GH |
4600 | /* Initialize fence registers to zero */ |
4601 | if (IS_I965G(dev)) { | |
4602 | for (i = 0; i < 16; i++) | |
4603 | I915_WRITE64(FENCE_REG_965_0 + (i * 8), 0); | |
4604 | } else { | |
4605 | for (i = 0; i < 8; i++) | |
4606 | I915_WRITE(FENCE_REG_830_0 + (i * 4), 0); | |
4607 | if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) | |
4608 | for (i = 0; i < 8; i++) | |
4609 | I915_WRITE(FENCE_REG_945_8 + (i * 4), 0); | |
4610 | } | |
4611 | ||
673a394b EA |
4612 | i915_gem_detect_bit_6_swizzle(dev); |
4613 | } | |
71acb5eb DA |
4614 | |
4615 | /* | |
4616 | * Create a physically contiguous memory object for this object | |
4617 | * e.g. for cursor + overlay regs | |
4618 | */ | |
4619 | int i915_gem_init_phys_object(struct drm_device *dev, | |
4620 | int id, int size) | |
4621 | { | |
4622 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4623 | struct drm_i915_gem_phys_object *phys_obj; | |
4624 | int ret; | |
4625 | ||
4626 | if (dev_priv->mm.phys_objs[id - 1] || !size) | |
4627 | return 0; | |
4628 | ||
9a298b2a | 4629 | phys_obj = kzalloc(sizeof(struct drm_i915_gem_phys_object), GFP_KERNEL); |
71acb5eb DA |
4630 | if (!phys_obj) |
4631 | return -ENOMEM; | |
4632 | ||
4633 | phys_obj->id = id; | |
4634 | ||
4635 | phys_obj->handle = drm_pci_alloc(dev, size, 0, 0xffffffff); | |
4636 | if (!phys_obj->handle) { | |
4637 | ret = -ENOMEM; | |
4638 | goto kfree_obj; | |
4639 | } | |
4640 | #ifdef CONFIG_X86 | |
4641 | set_memory_wc((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE); | |
4642 | #endif | |
4643 | ||
4644 | dev_priv->mm.phys_objs[id - 1] = phys_obj; | |
4645 | ||
4646 | return 0; | |
4647 | kfree_obj: | |
9a298b2a | 4648 | kfree(phys_obj); |
71acb5eb DA |
4649 | return ret; |
4650 | } | |
4651 | ||
4652 | void i915_gem_free_phys_object(struct drm_device *dev, int id) | |
4653 | { | |
4654 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4655 | struct drm_i915_gem_phys_object *phys_obj; | |
4656 | ||
4657 | if (!dev_priv->mm.phys_objs[id - 1]) | |
4658 | return; | |
4659 | ||
4660 | phys_obj = dev_priv->mm.phys_objs[id - 1]; | |
4661 | if (phys_obj->cur_obj) { | |
4662 | i915_gem_detach_phys_object(dev, phys_obj->cur_obj); | |
4663 | } | |
4664 | ||
4665 | #ifdef CONFIG_X86 | |
4666 | set_memory_wb((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE); | |
4667 | #endif | |
4668 | drm_pci_free(dev, phys_obj->handle); | |
4669 | kfree(phys_obj); | |
4670 | dev_priv->mm.phys_objs[id - 1] = NULL; | |
4671 | } | |
4672 | ||
4673 | void i915_gem_free_all_phys_object(struct drm_device *dev) | |
4674 | { | |
4675 | int i; | |
4676 | ||
260883c8 | 4677 | for (i = I915_GEM_PHYS_CURSOR_0; i <= I915_MAX_PHYS_OBJECT; i++) |
71acb5eb DA |
4678 | i915_gem_free_phys_object(dev, i); |
4679 | } | |
4680 | ||
4681 | void i915_gem_detach_phys_object(struct drm_device *dev, | |
4682 | struct drm_gem_object *obj) | |
4683 | { | |
4684 | struct drm_i915_gem_object *obj_priv; | |
4685 | int i; | |
4686 | int ret; | |
4687 | int page_count; | |
4688 | ||
4689 | obj_priv = obj->driver_private; | |
4690 | if (!obj_priv->phys_obj) | |
4691 | return; | |
4692 | ||
856fa198 | 4693 | ret = i915_gem_object_get_pages(obj); |
71acb5eb DA |
4694 | if (ret) |
4695 | goto out; | |
4696 | ||
4697 | page_count = obj->size / PAGE_SIZE; | |
4698 | ||
4699 | for (i = 0; i < page_count; i++) { | |
856fa198 | 4700 | char *dst = kmap_atomic(obj_priv->pages[i], KM_USER0); |
71acb5eb DA |
4701 | char *src = obj_priv->phys_obj->handle->vaddr + (i * PAGE_SIZE); |
4702 | ||
4703 | memcpy(dst, src, PAGE_SIZE); | |
4704 | kunmap_atomic(dst, KM_USER0); | |
4705 | } | |
856fa198 | 4706 | drm_clflush_pages(obj_priv->pages, page_count); |
71acb5eb | 4707 | drm_agp_chipset_flush(dev); |
d78b47b9 CW |
4708 | |
4709 | i915_gem_object_put_pages(obj); | |
71acb5eb DA |
4710 | out: |
4711 | obj_priv->phys_obj->cur_obj = NULL; | |
4712 | obj_priv->phys_obj = NULL; | |
4713 | } | |
4714 | ||
4715 | int | |
4716 | i915_gem_attach_phys_object(struct drm_device *dev, | |
4717 | struct drm_gem_object *obj, int id) | |
4718 | { | |
4719 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4720 | struct drm_i915_gem_object *obj_priv; | |
4721 | int ret = 0; | |
4722 | int page_count; | |
4723 | int i; | |
4724 | ||
4725 | if (id > I915_MAX_PHYS_OBJECT) | |
4726 | return -EINVAL; | |
4727 | ||
4728 | obj_priv = obj->driver_private; | |
4729 | ||
4730 | if (obj_priv->phys_obj) { | |
4731 | if (obj_priv->phys_obj->id == id) | |
4732 | return 0; | |
4733 | i915_gem_detach_phys_object(dev, obj); | |
4734 | } | |
4735 | ||
4736 | ||
4737 | /* create a new object */ | |
4738 | if (!dev_priv->mm.phys_objs[id - 1]) { | |
4739 | ret = i915_gem_init_phys_object(dev, id, | |
4740 | obj->size); | |
4741 | if (ret) { | |
aeb565df | 4742 | DRM_ERROR("failed to init phys object %d size: %zu\n", id, obj->size); |
71acb5eb DA |
4743 | goto out; |
4744 | } | |
4745 | } | |
4746 | ||
4747 | /* bind to the object */ | |
4748 | obj_priv->phys_obj = dev_priv->mm.phys_objs[id - 1]; | |
4749 | obj_priv->phys_obj->cur_obj = obj; | |
4750 | ||
856fa198 | 4751 | ret = i915_gem_object_get_pages(obj); |
71acb5eb DA |
4752 | if (ret) { |
4753 | DRM_ERROR("failed to get page list\n"); | |
4754 | goto out; | |
4755 | } | |
4756 | ||
4757 | page_count = obj->size / PAGE_SIZE; | |
4758 | ||
4759 | for (i = 0; i < page_count; i++) { | |
856fa198 | 4760 | char *src = kmap_atomic(obj_priv->pages[i], KM_USER0); |
71acb5eb DA |
4761 | char *dst = obj_priv->phys_obj->handle->vaddr + (i * PAGE_SIZE); |
4762 | ||
4763 | memcpy(dst, src, PAGE_SIZE); | |
4764 | kunmap_atomic(src, KM_USER0); | |
4765 | } | |
4766 | ||
d78b47b9 CW |
4767 | i915_gem_object_put_pages(obj); |
4768 | ||
71acb5eb DA |
4769 | return 0; |
4770 | out: | |
4771 | return ret; | |
4772 | } | |
4773 | ||
4774 | static int | |
4775 | i915_gem_phys_pwrite(struct drm_device *dev, struct drm_gem_object *obj, | |
4776 | struct drm_i915_gem_pwrite *args, | |
4777 | struct drm_file *file_priv) | |
4778 | { | |
4779 | struct drm_i915_gem_object *obj_priv = obj->driver_private; | |
4780 | void *obj_addr; | |
4781 | int ret; | |
4782 | char __user *user_data; | |
4783 | ||
4784 | user_data = (char __user *) (uintptr_t) args->data_ptr; | |
4785 | obj_addr = obj_priv->phys_obj->handle->vaddr + args->offset; | |
4786 | ||
e08fb4f6 | 4787 | DRM_DEBUG("obj_addr %p, %lld\n", obj_addr, args->size); |
71acb5eb DA |
4788 | ret = copy_from_user(obj_addr, user_data, args->size); |
4789 | if (ret) | |
4790 | return -EFAULT; | |
4791 | ||
4792 | drm_agp_chipset_flush(dev); | |
4793 | return 0; | |
4794 | } | |
b962442e EA |
4795 | |
4796 | void i915_gem_release(struct drm_device * dev, struct drm_file *file_priv) | |
4797 | { | |
4798 | struct drm_i915_file_private *i915_file_priv = file_priv->driver_priv; | |
4799 | ||
4800 | /* Clean up our request list when the client is going away, so that | |
4801 | * later retire_requests won't dereference our soon-to-be-gone | |
4802 | * file_priv. | |
4803 | */ | |
4804 | mutex_lock(&dev->struct_mutex); | |
4805 | while (!list_empty(&i915_file_priv->mm.request_list)) | |
4806 | list_del_init(i915_file_priv->mm.request_list.next); | |
4807 | mutex_unlock(&dev->struct_mutex); | |
4808 | } | |
31169714 | 4809 | |
31169714 CW |
4810 | static int |
4811 | i915_gem_shrink(int nr_to_scan, gfp_t gfp_mask) | |
4812 | { | |
4813 | drm_i915_private_t *dev_priv, *next_dev; | |
4814 | struct drm_i915_gem_object *obj_priv, *next_obj; | |
4815 | int cnt = 0; | |
4816 | int would_deadlock = 1; | |
4817 | ||
4818 | /* "fast-path" to count number of available objects */ | |
4819 | if (nr_to_scan == 0) { | |
4820 | spin_lock(&shrink_list_lock); | |
4821 | list_for_each_entry(dev_priv, &shrink_list, mm.shrink_list) { | |
4822 | struct drm_device *dev = dev_priv->dev; | |
4823 | ||
4824 | if (mutex_trylock(&dev->struct_mutex)) { | |
4825 | list_for_each_entry(obj_priv, | |
4826 | &dev_priv->mm.inactive_list, | |
4827 | list) | |
4828 | cnt++; | |
4829 | mutex_unlock(&dev->struct_mutex); | |
4830 | } | |
4831 | } | |
4832 | spin_unlock(&shrink_list_lock); | |
4833 | ||
4834 | return (cnt / 100) * sysctl_vfs_cache_pressure; | |
4835 | } | |
4836 | ||
4837 | spin_lock(&shrink_list_lock); | |
4838 | ||
4839 | /* first scan for clean buffers */ | |
4840 | list_for_each_entry_safe(dev_priv, next_dev, | |
4841 | &shrink_list, mm.shrink_list) { | |
4842 | struct drm_device *dev = dev_priv->dev; | |
4843 | ||
4844 | if (! mutex_trylock(&dev->struct_mutex)) | |
4845 | continue; | |
4846 | ||
4847 | spin_unlock(&shrink_list_lock); | |
4848 | ||
4849 | i915_gem_retire_requests(dev); | |
4850 | ||
4851 | list_for_each_entry_safe(obj_priv, next_obj, | |
4852 | &dev_priv->mm.inactive_list, | |
4853 | list) { | |
4854 | if (i915_gem_object_is_purgeable(obj_priv)) { | |
963b4836 | 4855 | i915_gem_object_unbind(obj_priv->obj); |
31169714 CW |
4856 | if (--nr_to_scan <= 0) |
4857 | break; | |
4858 | } | |
4859 | } | |
4860 | ||
4861 | spin_lock(&shrink_list_lock); | |
4862 | mutex_unlock(&dev->struct_mutex); | |
4863 | ||
963b4836 CW |
4864 | would_deadlock = 0; |
4865 | ||
31169714 CW |
4866 | if (nr_to_scan <= 0) |
4867 | break; | |
4868 | } | |
4869 | ||
4870 | /* second pass, evict/count anything still on the inactive list */ | |
4871 | list_for_each_entry_safe(dev_priv, next_dev, | |
4872 | &shrink_list, mm.shrink_list) { | |
4873 | struct drm_device *dev = dev_priv->dev; | |
4874 | ||
4875 | if (! mutex_trylock(&dev->struct_mutex)) | |
4876 | continue; | |
4877 | ||
4878 | spin_unlock(&shrink_list_lock); | |
4879 | ||
4880 | list_for_each_entry_safe(obj_priv, next_obj, | |
4881 | &dev_priv->mm.inactive_list, | |
4882 | list) { | |
4883 | if (nr_to_scan > 0) { | |
963b4836 | 4884 | i915_gem_object_unbind(obj_priv->obj); |
31169714 CW |
4885 | nr_to_scan--; |
4886 | } else | |
4887 | cnt++; | |
4888 | } | |
4889 | ||
4890 | spin_lock(&shrink_list_lock); | |
4891 | mutex_unlock(&dev->struct_mutex); | |
4892 | ||
4893 | would_deadlock = 0; | |
4894 | } | |
4895 | ||
4896 | spin_unlock(&shrink_list_lock); | |
4897 | ||
4898 | if (would_deadlock) | |
4899 | return -1; | |
4900 | else if (cnt > 0) | |
4901 | return (cnt / 100) * sysctl_vfs_cache_pressure; | |
4902 | else | |
4903 | return 0; | |
4904 | } | |
4905 | ||
4906 | static struct shrinker shrinker = { | |
4907 | .shrink = i915_gem_shrink, | |
4908 | .seeks = DEFAULT_SEEKS, | |
4909 | }; | |
4910 | ||
4911 | __init void | |
4912 | i915_gem_shrinker_init(void) | |
4913 | { | |
4914 | register_shrinker(&shrinker); | |
4915 | } | |
4916 | ||
4917 | __exit void | |
4918 | i915_gem_shrinker_exit(void) | |
4919 | { | |
4920 | unregister_shrinker(&shrinker); | |
4921 | } |