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Commit | Line | Data |
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673a394b | 1 | /* |
be6a0376 | 2 | * Copyright © 2008-2015 Intel Corporation |
673a394b EA |
3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | * | |
26 | */ | |
27 | ||
760285e7 | 28 | #include <drm/drmP.h> |
0de23977 | 29 | #include <drm/drm_vma_manager.h> |
760285e7 | 30 | #include <drm/i915_drm.h> |
673a394b | 31 | #include "i915_drv.h" |
eb82289a | 32 | #include "i915_vgpu.h" |
1c5d22f7 | 33 | #include "i915_trace.h" |
652c393a | 34 | #include "intel_drv.h" |
0ccdacf6 | 35 | #include "intel_mocs.h" |
5949eac4 | 36 | #include <linux/shmem_fs.h> |
5a0e3ad6 | 37 | #include <linux/slab.h> |
673a394b | 38 | #include <linux/swap.h> |
79e53945 | 39 | #include <linux/pci.h> |
1286ff73 | 40 | #include <linux/dma-buf.h> |
673a394b | 41 | |
05394f39 | 42 | static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj); |
e62b59e4 | 43 | static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj); |
c8725f3d | 44 | static void |
b4716185 CW |
45 | i915_gem_object_retire__write(struct drm_i915_gem_object *obj); |
46 | static void | |
47 | i915_gem_object_retire__read(struct drm_i915_gem_object *obj, int ring); | |
61050808 | 48 | |
c76ce038 CW |
49 | static bool cpu_cache_is_coherent(struct drm_device *dev, |
50 | enum i915_cache_level level) | |
51 | { | |
52 | return HAS_LLC(dev) || level != I915_CACHE_NONE; | |
53 | } | |
54 | ||
2c22569b CW |
55 | static bool cpu_write_needs_clflush(struct drm_i915_gem_object *obj) |
56 | { | |
b50a5371 AS |
57 | if (obj->base.write_domain == I915_GEM_DOMAIN_CPU) |
58 | return false; | |
59 | ||
2c22569b CW |
60 | if (!cpu_cache_is_coherent(obj->base.dev, obj->cache_level)) |
61 | return true; | |
62 | ||
63 | return obj->pin_display; | |
64 | } | |
65 | ||
4f1959ee AS |
66 | static int |
67 | insert_mappable_node(struct drm_i915_private *i915, | |
68 | struct drm_mm_node *node, u32 size) | |
69 | { | |
70 | memset(node, 0, sizeof(*node)); | |
71 | return drm_mm_insert_node_in_range_generic(&i915->ggtt.base.mm, node, | |
72 | size, 0, 0, 0, | |
73 | i915->ggtt.mappable_end, | |
74 | DRM_MM_SEARCH_DEFAULT, | |
75 | DRM_MM_CREATE_DEFAULT); | |
76 | } | |
77 | ||
78 | static void | |
79 | remove_mappable_node(struct drm_mm_node *node) | |
80 | { | |
81 | drm_mm_remove_node(node); | |
82 | } | |
83 | ||
73aa808f CW |
84 | /* some bookkeeping */ |
85 | static void i915_gem_info_add_obj(struct drm_i915_private *dev_priv, | |
86 | size_t size) | |
87 | { | |
c20e8355 | 88 | spin_lock(&dev_priv->mm.object_stat_lock); |
73aa808f CW |
89 | dev_priv->mm.object_count++; |
90 | dev_priv->mm.object_memory += size; | |
c20e8355 | 91 | spin_unlock(&dev_priv->mm.object_stat_lock); |
73aa808f CW |
92 | } |
93 | ||
94 | static void i915_gem_info_remove_obj(struct drm_i915_private *dev_priv, | |
95 | size_t size) | |
96 | { | |
c20e8355 | 97 | spin_lock(&dev_priv->mm.object_stat_lock); |
73aa808f CW |
98 | dev_priv->mm.object_count--; |
99 | dev_priv->mm.object_memory -= size; | |
c20e8355 | 100 | spin_unlock(&dev_priv->mm.object_stat_lock); |
73aa808f CW |
101 | } |
102 | ||
21dd3734 | 103 | static int |
33196ded | 104 | i915_gem_wait_for_error(struct i915_gpu_error *error) |
30dbf0c0 | 105 | { |
30dbf0c0 CW |
106 | int ret; |
107 | ||
d98c52cf | 108 | if (!i915_reset_in_progress(error)) |
30dbf0c0 CW |
109 | return 0; |
110 | ||
0a6759c6 DV |
111 | /* |
112 | * Only wait 10 seconds for the gpu reset to complete to avoid hanging | |
113 | * userspace. If it takes that long something really bad is going on and | |
114 | * we should simply try to bail out and fail as gracefully as possible. | |
115 | */ | |
1f83fee0 | 116 | ret = wait_event_interruptible_timeout(error->reset_queue, |
d98c52cf | 117 | !i915_reset_in_progress(error), |
1f83fee0 | 118 | 10*HZ); |
0a6759c6 DV |
119 | if (ret == 0) { |
120 | DRM_ERROR("Timed out waiting for the gpu reset to complete\n"); | |
121 | return -EIO; | |
122 | } else if (ret < 0) { | |
30dbf0c0 | 123 | return ret; |
d98c52cf CW |
124 | } else { |
125 | return 0; | |
0a6759c6 | 126 | } |
30dbf0c0 CW |
127 | } |
128 | ||
54cf91dc | 129 | int i915_mutex_lock_interruptible(struct drm_device *dev) |
76c1dec1 | 130 | { |
fac5e23e | 131 | struct drm_i915_private *dev_priv = to_i915(dev); |
76c1dec1 CW |
132 | int ret; |
133 | ||
33196ded | 134 | ret = i915_gem_wait_for_error(&dev_priv->gpu_error); |
76c1dec1 CW |
135 | if (ret) |
136 | return ret; | |
137 | ||
138 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
139 | if (ret) | |
140 | return ret; | |
141 | ||
23bc5982 | 142 | WARN_ON(i915_verify_lists(dev)); |
76c1dec1 CW |
143 | return 0; |
144 | } | |
30dbf0c0 | 145 | |
5a125c3c EA |
146 | int |
147 | i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 148 | struct drm_file *file) |
5a125c3c | 149 | { |
72e96d64 | 150 | struct drm_i915_private *dev_priv = to_i915(dev); |
62106b4f | 151 | struct i915_ggtt *ggtt = &dev_priv->ggtt; |
72e96d64 | 152 | struct drm_i915_gem_get_aperture *args = data; |
ca1543be | 153 | struct i915_vma *vma; |
6299f992 | 154 | size_t pinned; |
5a125c3c | 155 | |
6299f992 | 156 | pinned = 0; |
73aa808f | 157 | mutex_lock(&dev->struct_mutex); |
1c7f4bca | 158 | list_for_each_entry(vma, &ggtt->base.active_list, vm_link) |
ca1543be TU |
159 | if (vma->pin_count) |
160 | pinned += vma->node.size; | |
1c7f4bca | 161 | list_for_each_entry(vma, &ggtt->base.inactive_list, vm_link) |
ca1543be TU |
162 | if (vma->pin_count) |
163 | pinned += vma->node.size; | |
73aa808f | 164 | mutex_unlock(&dev->struct_mutex); |
5a125c3c | 165 | |
72e96d64 | 166 | args->aper_size = ggtt->base.total; |
0206e353 | 167 | args->aper_available_size = args->aper_size - pinned; |
6299f992 | 168 | |
5a125c3c EA |
169 | return 0; |
170 | } | |
171 | ||
6a2c4232 CW |
172 | static int |
173 | i915_gem_object_get_pages_phys(struct drm_i915_gem_object *obj) | |
00731155 | 174 | { |
6a2c4232 CW |
175 | struct address_space *mapping = file_inode(obj->base.filp)->i_mapping; |
176 | char *vaddr = obj->phys_handle->vaddr; | |
177 | struct sg_table *st; | |
178 | struct scatterlist *sg; | |
179 | int i; | |
00731155 | 180 | |
6a2c4232 CW |
181 | if (WARN_ON(i915_gem_object_needs_bit17_swizzle(obj))) |
182 | return -EINVAL; | |
183 | ||
184 | for (i = 0; i < obj->base.size / PAGE_SIZE; i++) { | |
185 | struct page *page; | |
186 | char *src; | |
187 | ||
188 | page = shmem_read_mapping_page(mapping, i); | |
189 | if (IS_ERR(page)) | |
190 | return PTR_ERR(page); | |
191 | ||
192 | src = kmap_atomic(page); | |
193 | memcpy(vaddr, src, PAGE_SIZE); | |
194 | drm_clflush_virt_range(vaddr, PAGE_SIZE); | |
195 | kunmap_atomic(src); | |
196 | ||
09cbfeaf | 197 | put_page(page); |
6a2c4232 CW |
198 | vaddr += PAGE_SIZE; |
199 | } | |
200 | ||
c033666a | 201 | i915_gem_chipset_flush(to_i915(obj->base.dev)); |
6a2c4232 CW |
202 | |
203 | st = kmalloc(sizeof(*st), GFP_KERNEL); | |
204 | if (st == NULL) | |
205 | return -ENOMEM; | |
206 | ||
207 | if (sg_alloc_table(st, 1, GFP_KERNEL)) { | |
208 | kfree(st); | |
209 | return -ENOMEM; | |
210 | } | |
211 | ||
212 | sg = st->sgl; | |
213 | sg->offset = 0; | |
214 | sg->length = obj->base.size; | |
00731155 | 215 | |
6a2c4232 CW |
216 | sg_dma_address(sg) = obj->phys_handle->busaddr; |
217 | sg_dma_len(sg) = obj->base.size; | |
218 | ||
219 | obj->pages = st; | |
6a2c4232 CW |
220 | return 0; |
221 | } | |
222 | ||
223 | static void | |
224 | i915_gem_object_put_pages_phys(struct drm_i915_gem_object *obj) | |
225 | { | |
226 | int ret; | |
227 | ||
228 | BUG_ON(obj->madv == __I915_MADV_PURGED); | |
00731155 | 229 | |
6a2c4232 | 230 | ret = i915_gem_object_set_to_cpu_domain(obj, true); |
f4457ae7 | 231 | if (WARN_ON(ret)) { |
6a2c4232 CW |
232 | /* In the event of a disaster, abandon all caches and |
233 | * hope for the best. | |
234 | */ | |
6a2c4232 CW |
235 | obj->base.read_domains = obj->base.write_domain = I915_GEM_DOMAIN_CPU; |
236 | } | |
237 | ||
238 | if (obj->madv == I915_MADV_DONTNEED) | |
239 | obj->dirty = 0; | |
240 | ||
241 | if (obj->dirty) { | |
00731155 | 242 | struct address_space *mapping = file_inode(obj->base.filp)->i_mapping; |
6a2c4232 | 243 | char *vaddr = obj->phys_handle->vaddr; |
00731155 CW |
244 | int i; |
245 | ||
246 | for (i = 0; i < obj->base.size / PAGE_SIZE; i++) { | |
6a2c4232 CW |
247 | struct page *page; |
248 | char *dst; | |
249 | ||
250 | page = shmem_read_mapping_page(mapping, i); | |
251 | if (IS_ERR(page)) | |
252 | continue; | |
253 | ||
254 | dst = kmap_atomic(page); | |
255 | drm_clflush_virt_range(vaddr, PAGE_SIZE); | |
256 | memcpy(dst, vaddr, PAGE_SIZE); | |
257 | kunmap_atomic(dst); | |
258 | ||
259 | set_page_dirty(page); | |
260 | if (obj->madv == I915_MADV_WILLNEED) | |
00731155 | 261 | mark_page_accessed(page); |
09cbfeaf | 262 | put_page(page); |
00731155 CW |
263 | vaddr += PAGE_SIZE; |
264 | } | |
6a2c4232 | 265 | obj->dirty = 0; |
00731155 CW |
266 | } |
267 | ||
6a2c4232 CW |
268 | sg_free_table(obj->pages); |
269 | kfree(obj->pages); | |
6a2c4232 CW |
270 | } |
271 | ||
272 | static void | |
273 | i915_gem_object_release_phys(struct drm_i915_gem_object *obj) | |
274 | { | |
275 | drm_pci_free(obj->base.dev, obj->phys_handle); | |
276 | } | |
277 | ||
278 | static const struct drm_i915_gem_object_ops i915_gem_phys_ops = { | |
279 | .get_pages = i915_gem_object_get_pages_phys, | |
280 | .put_pages = i915_gem_object_put_pages_phys, | |
281 | .release = i915_gem_object_release_phys, | |
282 | }; | |
283 | ||
284 | static int | |
285 | drop_pages(struct drm_i915_gem_object *obj) | |
286 | { | |
287 | struct i915_vma *vma, *next; | |
288 | int ret; | |
289 | ||
290 | drm_gem_object_reference(&obj->base); | |
1c7f4bca | 291 | list_for_each_entry_safe(vma, next, &obj->vma_list, obj_link) |
6a2c4232 CW |
292 | if (i915_vma_unbind(vma)) |
293 | break; | |
294 | ||
295 | ret = i915_gem_object_put_pages(obj); | |
296 | drm_gem_object_unreference(&obj->base); | |
297 | ||
298 | return ret; | |
00731155 CW |
299 | } |
300 | ||
301 | int | |
302 | i915_gem_object_attach_phys(struct drm_i915_gem_object *obj, | |
303 | int align) | |
304 | { | |
305 | drm_dma_handle_t *phys; | |
6a2c4232 | 306 | int ret; |
00731155 CW |
307 | |
308 | if (obj->phys_handle) { | |
309 | if ((unsigned long)obj->phys_handle->vaddr & (align -1)) | |
310 | return -EBUSY; | |
311 | ||
312 | return 0; | |
313 | } | |
314 | ||
315 | if (obj->madv != I915_MADV_WILLNEED) | |
316 | return -EFAULT; | |
317 | ||
318 | if (obj->base.filp == NULL) | |
319 | return -EINVAL; | |
320 | ||
6a2c4232 CW |
321 | ret = drop_pages(obj); |
322 | if (ret) | |
323 | return ret; | |
324 | ||
00731155 CW |
325 | /* create a new object */ |
326 | phys = drm_pci_alloc(obj->base.dev, obj->base.size, align); | |
327 | if (!phys) | |
328 | return -ENOMEM; | |
329 | ||
00731155 | 330 | obj->phys_handle = phys; |
6a2c4232 CW |
331 | obj->ops = &i915_gem_phys_ops; |
332 | ||
333 | return i915_gem_object_get_pages(obj); | |
00731155 CW |
334 | } |
335 | ||
336 | static int | |
337 | i915_gem_phys_pwrite(struct drm_i915_gem_object *obj, | |
338 | struct drm_i915_gem_pwrite *args, | |
339 | struct drm_file *file_priv) | |
340 | { | |
341 | struct drm_device *dev = obj->base.dev; | |
342 | void *vaddr = obj->phys_handle->vaddr + args->offset; | |
3ed605bc | 343 | char __user *user_data = u64_to_user_ptr(args->data_ptr); |
063e4e6b | 344 | int ret = 0; |
6a2c4232 CW |
345 | |
346 | /* We manually control the domain here and pretend that it | |
347 | * remains coherent i.e. in the GTT domain, like shmem_pwrite. | |
348 | */ | |
349 | ret = i915_gem_object_wait_rendering(obj, false); | |
350 | if (ret) | |
351 | return ret; | |
00731155 | 352 | |
77a0d1ca | 353 | intel_fb_obj_invalidate(obj, ORIGIN_CPU); |
00731155 CW |
354 | if (__copy_from_user_inatomic_nocache(vaddr, user_data, args->size)) { |
355 | unsigned long unwritten; | |
356 | ||
357 | /* The physical object once assigned is fixed for the lifetime | |
358 | * of the obj, so we can safely drop the lock and continue | |
359 | * to access vaddr. | |
360 | */ | |
361 | mutex_unlock(&dev->struct_mutex); | |
362 | unwritten = copy_from_user(vaddr, user_data, args->size); | |
363 | mutex_lock(&dev->struct_mutex); | |
063e4e6b PZ |
364 | if (unwritten) { |
365 | ret = -EFAULT; | |
366 | goto out; | |
367 | } | |
00731155 CW |
368 | } |
369 | ||
6a2c4232 | 370 | drm_clflush_virt_range(vaddr, args->size); |
c033666a | 371 | i915_gem_chipset_flush(to_i915(dev)); |
063e4e6b PZ |
372 | |
373 | out: | |
de152b62 | 374 | intel_fb_obj_flush(obj, false, ORIGIN_CPU); |
063e4e6b | 375 | return ret; |
00731155 CW |
376 | } |
377 | ||
42dcedd4 CW |
378 | void *i915_gem_object_alloc(struct drm_device *dev) |
379 | { | |
fac5e23e | 380 | struct drm_i915_private *dev_priv = to_i915(dev); |
efab6d8d | 381 | return kmem_cache_zalloc(dev_priv->objects, GFP_KERNEL); |
42dcedd4 CW |
382 | } |
383 | ||
384 | void i915_gem_object_free(struct drm_i915_gem_object *obj) | |
385 | { | |
fac5e23e | 386 | struct drm_i915_private *dev_priv = to_i915(obj->base.dev); |
efab6d8d | 387 | kmem_cache_free(dev_priv->objects, obj); |
42dcedd4 CW |
388 | } |
389 | ||
ff72145b DA |
390 | static int |
391 | i915_gem_create(struct drm_file *file, | |
392 | struct drm_device *dev, | |
393 | uint64_t size, | |
394 | uint32_t *handle_p) | |
673a394b | 395 | { |
05394f39 | 396 | struct drm_i915_gem_object *obj; |
a1a2d1d3 PP |
397 | int ret; |
398 | u32 handle; | |
673a394b | 399 | |
ff72145b | 400 | size = roundup(size, PAGE_SIZE); |
8ffc0246 CW |
401 | if (size == 0) |
402 | return -EINVAL; | |
673a394b EA |
403 | |
404 | /* Allocate the new object */ | |
d37cd8a8 | 405 | obj = i915_gem_object_create(dev, size); |
fe3db79b CW |
406 | if (IS_ERR(obj)) |
407 | return PTR_ERR(obj); | |
673a394b | 408 | |
05394f39 | 409 | ret = drm_gem_handle_create(file, &obj->base, &handle); |
202f2fef | 410 | /* drop reference from allocate - handle holds it now */ |
d861e338 DV |
411 | drm_gem_object_unreference_unlocked(&obj->base); |
412 | if (ret) | |
413 | return ret; | |
202f2fef | 414 | |
ff72145b | 415 | *handle_p = handle; |
673a394b EA |
416 | return 0; |
417 | } | |
418 | ||
ff72145b DA |
419 | int |
420 | i915_gem_dumb_create(struct drm_file *file, | |
421 | struct drm_device *dev, | |
422 | struct drm_mode_create_dumb *args) | |
423 | { | |
424 | /* have to work out size/pitch and return them */ | |
de45eaf7 | 425 | args->pitch = ALIGN(args->width * DIV_ROUND_UP(args->bpp, 8), 64); |
ff72145b DA |
426 | args->size = args->pitch * args->height; |
427 | return i915_gem_create(file, dev, | |
da6b51d0 | 428 | args->size, &args->handle); |
ff72145b DA |
429 | } |
430 | ||
ff72145b DA |
431 | /** |
432 | * Creates a new mm object and returns a handle to it. | |
14bb2c11 TU |
433 | * @dev: drm device pointer |
434 | * @data: ioctl data blob | |
435 | * @file: drm file pointer | |
ff72145b DA |
436 | */ |
437 | int | |
438 | i915_gem_create_ioctl(struct drm_device *dev, void *data, | |
439 | struct drm_file *file) | |
440 | { | |
441 | struct drm_i915_gem_create *args = data; | |
63ed2cb2 | 442 | |
ff72145b | 443 | return i915_gem_create(file, dev, |
da6b51d0 | 444 | args->size, &args->handle); |
ff72145b DA |
445 | } |
446 | ||
8461d226 DV |
447 | static inline int |
448 | __copy_to_user_swizzled(char __user *cpu_vaddr, | |
449 | const char *gpu_vaddr, int gpu_offset, | |
450 | int length) | |
451 | { | |
452 | int ret, cpu_offset = 0; | |
453 | ||
454 | while (length > 0) { | |
455 | int cacheline_end = ALIGN(gpu_offset + 1, 64); | |
456 | int this_length = min(cacheline_end - gpu_offset, length); | |
457 | int swizzled_gpu_offset = gpu_offset ^ 64; | |
458 | ||
459 | ret = __copy_to_user(cpu_vaddr + cpu_offset, | |
460 | gpu_vaddr + swizzled_gpu_offset, | |
461 | this_length); | |
462 | if (ret) | |
463 | return ret + length; | |
464 | ||
465 | cpu_offset += this_length; | |
466 | gpu_offset += this_length; | |
467 | length -= this_length; | |
468 | } | |
469 | ||
470 | return 0; | |
471 | } | |
472 | ||
8c59967c | 473 | static inline int |
4f0c7cfb BW |
474 | __copy_from_user_swizzled(char *gpu_vaddr, int gpu_offset, |
475 | const char __user *cpu_vaddr, | |
8c59967c DV |
476 | int length) |
477 | { | |
478 | int ret, cpu_offset = 0; | |
479 | ||
480 | while (length > 0) { | |
481 | int cacheline_end = ALIGN(gpu_offset + 1, 64); | |
482 | int this_length = min(cacheline_end - gpu_offset, length); | |
483 | int swizzled_gpu_offset = gpu_offset ^ 64; | |
484 | ||
485 | ret = __copy_from_user(gpu_vaddr + swizzled_gpu_offset, | |
486 | cpu_vaddr + cpu_offset, | |
487 | this_length); | |
488 | if (ret) | |
489 | return ret + length; | |
490 | ||
491 | cpu_offset += this_length; | |
492 | gpu_offset += this_length; | |
493 | length -= this_length; | |
494 | } | |
495 | ||
496 | return 0; | |
497 | } | |
498 | ||
4c914c0c BV |
499 | /* |
500 | * Pins the specified object's pages and synchronizes the object with | |
501 | * GPU accesses. Sets needs_clflush to non-zero if the caller should | |
502 | * flush the object from the CPU cache. | |
503 | */ | |
504 | int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj, | |
505 | int *needs_clflush) | |
506 | { | |
507 | int ret; | |
508 | ||
509 | *needs_clflush = 0; | |
510 | ||
b9bcd14a | 511 | if (WARN_ON(!i915_gem_object_has_struct_page(obj))) |
4c914c0c BV |
512 | return -EINVAL; |
513 | ||
514 | if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU)) { | |
515 | /* If we're not in the cpu read domain, set ourself into the gtt | |
516 | * read domain and manually flush cachelines (if required). This | |
517 | * optimizes for the case when the gpu will dirty the data | |
518 | * anyway again before the next pread happens. */ | |
519 | *needs_clflush = !cpu_cache_is_coherent(obj->base.dev, | |
520 | obj->cache_level); | |
521 | ret = i915_gem_object_wait_rendering(obj, true); | |
522 | if (ret) | |
523 | return ret; | |
524 | } | |
525 | ||
526 | ret = i915_gem_object_get_pages(obj); | |
527 | if (ret) | |
528 | return ret; | |
529 | ||
530 | i915_gem_object_pin_pages(obj); | |
531 | ||
532 | return ret; | |
533 | } | |
534 | ||
d174bd64 DV |
535 | /* Per-page copy function for the shmem pread fastpath. |
536 | * Flushes invalid cachelines before reading the target if | |
537 | * needs_clflush is set. */ | |
eb01459f | 538 | static int |
d174bd64 DV |
539 | shmem_pread_fast(struct page *page, int shmem_page_offset, int page_length, |
540 | char __user *user_data, | |
541 | bool page_do_bit17_swizzling, bool needs_clflush) | |
542 | { | |
543 | char *vaddr; | |
544 | int ret; | |
545 | ||
e7e58eb5 | 546 | if (unlikely(page_do_bit17_swizzling)) |
d174bd64 DV |
547 | return -EINVAL; |
548 | ||
549 | vaddr = kmap_atomic(page); | |
550 | if (needs_clflush) | |
551 | drm_clflush_virt_range(vaddr + shmem_page_offset, | |
552 | page_length); | |
553 | ret = __copy_to_user_inatomic(user_data, | |
554 | vaddr + shmem_page_offset, | |
555 | page_length); | |
556 | kunmap_atomic(vaddr); | |
557 | ||
f60d7f0c | 558 | return ret ? -EFAULT : 0; |
d174bd64 DV |
559 | } |
560 | ||
23c18c71 DV |
561 | static void |
562 | shmem_clflush_swizzled_range(char *addr, unsigned long length, | |
563 | bool swizzled) | |
564 | { | |
e7e58eb5 | 565 | if (unlikely(swizzled)) { |
23c18c71 DV |
566 | unsigned long start = (unsigned long) addr; |
567 | unsigned long end = (unsigned long) addr + length; | |
568 | ||
569 | /* For swizzling simply ensure that we always flush both | |
570 | * channels. Lame, but simple and it works. Swizzled | |
571 | * pwrite/pread is far from a hotpath - current userspace | |
572 | * doesn't use it at all. */ | |
573 | start = round_down(start, 128); | |
574 | end = round_up(end, 128); | |
575 | ||
576 | drm_clflush_virt_range((void *)start, end - start); | |
577 | } else { | |
578 | drm_clflush_virt_range(addr, length); | |
579 | } | |
580 | ||
581 | } | |
582 | ||
d174bd64 DV |
583 | /* Only difference to the fast-path function is that this can handle bit17 |
584 | * and uses non-atomic copy and kmap functions. */ | |
585 | static int | |
586 | shmem_pread_slow(struct page *page, int shmem_page_offset, int page_length, | |
587 | char __user *user_data, | |
588 | bool page_do_bit17_swizzling, bool needs_clflush) | |
589 | { | |
590 | char *vaddr; | |
591 | int ret; | |
592 | ||
593 | vaddr = kmap(page); | |
594 | if (needs_clflush) | |
23c18c71 DV |
595 | shmem_clflush_swizzled_range(vaddr + shmem_page_offset, |
596 | page_length, | |
597 | page_do_bit17_swizzling); | |
d174bd64 DV |
598 | |
599 | if (page_do_bit17_swizzling) | |
600 | ret = __copy_to_user_swizzled(user_data, | |
601 | vaddr, shmem_page_offset, | |
602 | page_length); | |
603 | else | |
604 | ret = __copy_to_user(user_data, | |
605 | vaddr + shmem_page_offset, | |
606 | page_length); | |
607 | kunmap(page); | |
608 | ||
f60d7f0c | 609 | return ret ? - EFAULT : 0; |
d174bd64 DV |
610 | } |
611 | ||
b50a5371 AS |
612 | static inline unsigned long |
613 | slow_user_access(struct io_mapping *mapping, | |
614 | uint64_t page_base, int page_offset, | |
615 | char __user *user_data, | |
616 | unsigned long length, bool pwrite) | |
617 | { | |
618 | void __iomem *ioaddr; | |
619 | void *vaddr; | |
620 | uint64_t unwritten; | |
621 | ||
622 | ioaddr = io_mapping_map_wc(mapping, page_base, PAGE_SIZE); | |
623 | /* We can use the cpu mem copy function because this is X86. */ | |
624 | vaddr = (void __force *)ioaddr + page_offset; | |
625 | if (pwrite) | |
626 | unwritten = __copy_from_user(vaddr, user_data, length); | |
627 | else | |
628 | unwritten = __copy_to_user(user_data, vaddr, length); | |
629 | ||
630 | io_mapping_unmap(ioaddr); | |
631 | return unwritten; | |
632 | } | |
633 | ||
634 | static int | |
635 | i915_gem_gtt_pread(struct drm_device *dev, | |
636 | struct drm_i915_gem_object *obj, uint64_t size, | |
637 | uint64_t data_offset, uint64_t data_ptr) | |
638 | { | |
fac5e23e | 639 | struct drm_i915_private *dev_priv = to_i915(dev); |
b50a5371 AS |
640 | struct i915_ggtt *ggtt = &dev_priv->ggtt; |
641 | struct drm_mm_node node; | |
642 | char __user *user_data; | |
643 | uint64_t remain; | |
644 | uint64_t offset; | |
645 | int ret; | |
646 | ||
647 | ret = i915_gem_obj_ggtt_pin(obj, 0, PIN_MAPPABLE); | |
648 | if (ret) { | |
649 | ret = insert_mappable_node(dev_priv, &node, PAGE_SIZE); | |
650 | if (ret) | |
651 | goto out; | |
652 | ||
653 | ret = i915_gem_object_get_pages(obj); | |
654 | if (ret) { | |
655 | remove_mappable_node(&node); | |
656 | goto out; | |
657 | } | |
658 | ||
659 | i915_gem_object_pin_pages(obj); | |
660 | } else { | |
661 | node.start = i915_gem_obj_ggtt_offset(obj); | |
662 | node.allocated = false; | |
663 | ret = i915_gem_object_put_fence(obj); | |
664 | if (ret) | |
665 | goto out_unpin; | |
666 | } | |
667 | ||
668 | ret = i915_gem_object_set_to_gtt_domain(obj, false); | |
669 | if (ret) | |
670 | goto out_unpin; | |
671 | ||
672 | user_data = u64_to_user_ptr(data_ptr); | |
673 | remain = size; | |
674 | offset = data_offset; | |
675 | ||
676 | mutex_unlock(&dev->struct_mutex); | |
677 | if (likely(!i915.prefault_disable)) { | |
678 | ret = fault_in_multipages_writeable(user_data, remain); | |
679 | if (ret) { | |
680 | mutex_lock(&dev->struct_mutex); | |
681 | goto out_unpin; | |
682 | } | |
683 | } | |
684 | ||
685 | while (remain > 0) { | |
686 | /* Operation in this page | |
687 | * | |
688 | * page_base = page offset within aperture | |
689 | * page_offset = offset within page | |
690 | * page_length = bytes to copy for this page | |
691 | */ | |
692 | u32 page_base = node.start; | |
693 | unsigned page_offset = offset_in_page(offset); | |
694 | unsigned page_length = PAGE_SIZE - page_offset; | |
695 | page_length = remain < page_length ? remain : page_length; | |
696 | if (node.allocated) { | |
697 | wmb(); | |
698 | ggtt->base.insert_page(&ggtt->base, | |
699 | i915_gem_object_get_dma_address(obj, offset >> PAGE_SHIFT), | |
700 | node.start, | |
701 | I915_CACHE_NONE, 0); | |
702 | wmb(); | |
703 | } else { | |
704 | page_base += offset & PAGE_MASK; | |
705 | } | |
706 | /* This is a slow read/write as it tries to read from | |
707 | * and write to user memory which may result into page | |
708 | * faults, and so we cannot perform this under struct_mutex. | |
709 | */ | |
710 | if (slow_user_access(ggtt->mappable, page_base, | |
711 | page_offset, user_data, | |
712 | page_length, false)) { | |
713 | ret = -EFAULT; | |
714 | break; | |
715 | } | |
716 | ||
717 | remain -= page_length; | |
718 | user_data += page_length; | |
719 | offset += page_length; | |
720 | } | |
721 | ||
722 | mutex_lock(&dev->struct_mutex); | |
723 | if (ret == 0 && (obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0) { | |
724 | /* The user has modified the object whilst we tried | |
725 | * reading from it, and we now have no idea what domain | |
726 | * the pages should be in. As we have just been touching | |
727 | * them directly, flush everything back to the GTT | |
728 | * domain. | |
729 | */ | |
730 | ret = i915_gem_object_set_to_gtt_domain(obj, false); | |
731 | } | |
732 | ||
733 | out_unpin: | |
734 | if (node.allocated) { | |
735 | wmb(); | |
736 | ggtt->base.clear_range(&ggtt->base, | |
737 | node.start, node.size, | |
738 | true); | |
739 | i915_gem_object_unpin_pages(obj); | |
740 | remove_mappable_node(&node); | |
741 | } else { | |
742 | i915_gem_object_ggtt_unpin(obj); | |
743 | } | |
744 | out: | |
745 | return ret; | |
746 | } | |
747 | ||
eb01459f | 748 | static int |
dbf7bff0 DV |
749 | i915_gem_shmem_pread(struct drm_device *dev, |
750 | struct drm_i915_gem_object *obj, | |
751 | struct drm_i915_gem_pread *args, | |
752 | struct drm_file *file) | |
eb01459f | 753 | { |
8461d226 | 754 | char __user *user_data; |
eb01459f | 755 | ssize_t remain; |
8461d226 | 756 | loff_t offset; |
eb2c0c81 | 757 | int shmem_page_offset, page_length, ret = 0; |
8461d226 | 758 | int obj_do_bit17_swizzling, page_do_bit17_swizzling; |
96d79b52 | 759 | int prefaulted = 0; |
8489731c | 760 | int needs_clflush = 0; |
67d5a50c | 761 | struct sg_page_iter sg_iter; |
eb01459f | 762 | |
6eae0059 | 763 | if (!i915_gem_object_has_struct_page(obj)) |
b50a5371 AS |
764 | return -ENODEV; |
765 | ||
3ed605bc | 766 | user_data = u64_to_user_ptr(args->data_ptr); |
eb01459f EA |
767 | remain = args->size; |
768 | ||
8461d226 | 769 | obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj); |
eb01459f | 770 | |
4c914c0c | 771 | ret = i915_gem_obj_prepare_shmem_read(obj, &needs_clflush); |
f60d7f0c CW |
772 | if (ret) |
773 | return ret; | |
774 | ||
8461d226 | 775 | offset = args->offset; |
eb01459f | 776 | |
67d5a50c ID |
777 | for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, |
778 | offset >> PAGE_SHIFT) { | |
2db76d7c | 779 | struct page *page = sg_page_iter_page(&sg_iter); |
9da3da66 CW |
780 | |
781 | if (remain <= 0) | |
782 | break; | |
783 | ||
eb01459f EA |
784 | /* Operation in this page |
785 | * | |
eb01459f | 786 | * shmem_page_offset = offset within page in shmem file |
eb01459f EA |
787 | * page_length = bytes to copy for this page |
788 | */ | |
c8cbbb8b | 789 | shmem_page_offset = offset_in_page(offset); |
eb01459f EA |
790 | page_length = remain; |
791 | if ((shmem_page_offset + page_length) > PAGE_SIZE) | |
792 | page_length = PAGE_SIZE - shmem_page_offset; | |
eb01459f | 793 | |
8461d226 DV |
794 | page_do_bit17_swizzling = obj_do_bit17_swizzling && |
795 | (page_to_phys(page) & (1 << 17)) != 0; | |
796 | ||
d174bd64 DV |
797 | ret = shmem_pread_fast(page, shmem_page_offset, page_length, |
798 | user_data, page_do_bit17_swizzling, | |
799 | needs_clflush); | |
800 | if (ret == 0) | |
801 | goto next_page; | |
dbf7bff0 | 802 | |
dbf7bff0 DV |
803 | mutex_unlock(&dev->struct_mutex); |
804 | ||
d330a953 | 805 | if (likely(!i915.prefault_disable) && !prefaulted) { |
f56f821f | 806 | ret = fault_in_multipages_writeable(user_data, remain); |
96d79b52 DV |
807 | /* Userspace is tricking us, but we've already clobbered |
808 | * its pages with the prefault and promised to write the | |
809 | * data up to the first fault. Hence ignore any errors | |
810 | * and just continue. */ | |
811 | (void)ret; | |
812 | prefaulted = 1; | |
813 | } | |
eb01459f | 814 | |
d174bd64 DV |
815 | ret = shmem_pread_slow(page, shmem_page_offset, page_length, |
816 | user_data, page_do_bit17_swizzling, | |
817 | needs_clflush); | |
eb01459f | 818 | |
dbf7bff0 | 819 | mutex_lock(&dev->struct_mutex); |
f60d7f0c | 820 | |
f60d7f0c | 821 | if (ret) |
8461d226 | 822 | goto out; |
8461d226 | 823 | |
17793c9a | 824 | next_page: |
eb01459f | 825 | remain -= page_length; |
8461d226 | 826 | user_data += page_length; |
eb01459f EA |
827 | offset += page_length; |
828 | } | |
829 | ||
4f27b75d | 830 | out: |
f60d7f0c CW |
831 | i915_gem_object_unpin_pages(obj); |
832 | ||
eb01459f EA |
833 | return ret; |
834 | } | |
835 | ||
673a394b EA |
836 | /** |
837 | * Reads data from the object referenced by handle. | |
14bb2c11 TU |
838 | * @dev: drm device pointer |
839 | * @data: ioctl data blob | |
840 | * @file: drm file pointer | |
673a394b EA |
841 | * |
842 | * On error, the contents of *data are undefined. | |
843 | */ | |
844 | int | |
845 | i915_gem_pread_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 846 | struct drm_file *file) |
673a394b EA |
847 | { |
848 | struct drm_i915_gem_pread *args = data; | |
05394f39 | 849 | struct drm_i915_gem_object *obj; |
35b62a89 | 850 | int ret = 0; |
673a394b | 851 | |
51311d0a CW |
852 | if (args->size == 0) |
853 | return 0; | |
854 | ||
855 | if (!access_ok(VERIFY_WRITE, | |
3ed605bc | 856 | u64_to_user_ptr(args->data_ptr), |
51311d0a CW |
857 | args->size)) |
858 | return -EFAULT; | |
859 | ||
4f27b75d | 860 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 861 | if (ret) |
4f27b75d | 862 | return ret; |
673a394b | 863 | |
a8ad0bd8 | 864 | obj = to_intel_bo(drm_gem_object_lookup(file, args->handle)); |
c8725226 | 865 | if (&obj->base == NULL) { |
1d7cfea1 CW |
866 | ret = -ENOENT; |
867 | goto unlock; | |
4f27b75d | 868 | } |
673a394b | 869 | |
7dcd2499 | 870 | /* Bounds check source. */ |
05394f39 CW |
871 | if (args->offset > obj->base.size || |
872 | args->size > obj->base.size - args->offset) { | |
ce9d419d | 873 | ret = -EINVAL; |
35b62a89 | 874 | goto out; |
ce9d419d CW |
875 | } |
876 | ||
db53a302 CW |
877 | trace_i915_gem_object_pread(obj, args->offset, args->size); |
878 | ||
dbf7bff0 | 879 | ret = i915_gem_shmem_pread(dev, obj, args, file); |
673a394b | 880 | |
b50a5371 AS |
881 | /* pread for non shmem backed objects */ |
882 | if (ret == -EFAULT || ret == -ENODEV) | |
883 | ret = i915_gem_gtt_pread(dev, obj, args->size, | |
884 | args->offset, args->data_ptr); | |
885 | ||
35b62a89 | 886 | out: |
05394f39 | 887 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 888 | unlock: |
4f27b75d | 889 | mutex_unlock(&dev->struct_mutex); |
eb01459f | 890 | return ret; |
673a394b EA |
891 | } |
892 | ||
0839ccb8 KP |
893 | /* This is the fast write path which cannot handle |
894 | * page faults in the source data | |
9b7530cc | 895 | */ |
0839ccb8 KP |
896 | |
897 | static inline int | |
898 | fast_user_write(struct io_mapping *mapping, | |
899 | loff_t page_base, int page_offset, | |
900 | char __user *user_data, | |
901 | int length) | |
9b7530cc | 902 | { |
4f0c7cfb BW |
903 | void __iomem *vaddr_atomic; |
904 | void *vaddr; | |
0839ccb8 | 905 | unsigned long unwritten; |
9b7530cc | 906 | |
3e4d3af5 | 907 | vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base); |
4f0c7cfb BW |
908 | /* We can use the cpu mem copy function because this is X86. */ |
909 | vaddr = (void __force*)vaddr_atomic + page_offset; | |
910 | unwritten = __copy_from_user_inatomic_nocache(vaddr, | |
0839ccb8 | 911 | user_data, length); |
3e4d3af5 | 912 | io_mapping_unmap_atomic(vaddr_atomic); |
fbd5a26d | 913 | return unwritten; |
0839ccb8 KP |
914 | } |
915 | ||
3de09aa3 EA |
916 | /** |
917 | * This is the fast pwrite path, where we copy the data directly from the | |
918 | * user into the GTT, uncached. | |
14bb2c11 TU |
919 | * @dev: drm device pointer |
920 | * @obj: i915 gem object | |
921 | * @args: pwrite arguments structure | |
922 | * @file: drm file pointer | |
3de09aa3 | 923 | */ |
673a394b | 924 | static int |
4f1959ee | 925 | i915_gem_gtt_pwrite_fast(struct drm_i915_private *i915, |
05394f39 | 926 | struct drm_i915_gem_object *obj, |
3de09aa3 | 927 | struct drm_i915_gem_pwrite *args, |
05394f39 | 928 | struct drm_file *file) |
673a394b | 929 | { |
4f1959ee | 930 | struct i915_ggtt *ggtt = &i915->ggtt; |
b50a5371 | 931 | struct drm_device *dev = obj->base.dev; |
4f1959ee AS |
932 | struct drm_mm_node node; |
933 | uint64_t remain, offset; | |
673a394b | 934 | char __user *user_data; |
4f1959ee | 935 | int ret; |
b50a5371 AS |
936 | bool hit_slow_path = false; |
937 | ||
938 | if (obj->tiling_mode != I915_TILING_NONE) | |
939 | return -EFAULT; | |
935aaa69 | 940 | |
1ec9e26d | 941 | ret = i915_gem_obj_ggtt_pin(obj, 0, PIN_MAPPABLE | PIN_NONBLOCK); |
4f1959ee AS |
942 | if (ret) { |
943 | ret = insert_mappable_node(i915, &node, PAGE_SIZE); | |
944 | if (ret) | |
945 | goto out; | |
946 | ||
947 | ret = i915_gem_object_get_pages(obj); | |
948 | if (ret) { | |
949 | remove_mappable_node(&node); | |
950 | goto out; | |
951 | } | |
952 | ||
953 | i915_gem_object_pin_pages(obj); | |
954 | } else { | |
955 | node.start = i915_gem_obj_ggtt_offset(obj); | |
956 | node.allocated = false; | |
b50a5371 AS |
957 | ret = i915_gem_object_put_fence(obj); |
958 | if (ret) | |
959 | goto out_unpin; | |
4f1959ee | 960 | } |
935aaa69 DV |
961 | |
962 | ret = i915_gem_object_set_to_gtt_domain(obj, true); | |
963 | if (ret) | |
964 | goto out_unpin; | |
965 | ||
77a0d1ca | 966 | intel_fb_obj_invalidate(obj, ORIGIN_GTT); |
4f1959ee | 967 | obj->dirty = true; |
063e4e6b | 968 | |
4f1959ee AS |
969 | user_data = u64_to_user_ptr(args->data_ptr); |
970 | offset = args->offset; | |
971 | remain = args->size; | |
972 | while (remain) { | |
673a394b EA |
973 | /* Operation in this page |
974 | * | |
0839ccb8 KP |
975 | * page_base = page offset within aperture |
976 | * page_offset = offset within page | |
977 | * page_length = bytes to copy for this page | |
673a394b | 978 | */ |
4f1959ee AS |
979 | u32 page_base = node.start; |
980 | unsigned page_offset = offset_in_page(offset); | |
981 | unsigned page_length = PAGE_SIZE - page_offset; | |
982 | page_length = remain < page_length ? remain : page_length; | |
983 | if (node.allocated) { | |
984 | wmb(); /* flush the write before we modify the GGTT */ | |
985 | ggtt->base.insert_page(&ggtt->base, | |
986 | i915_gem_object_get_dma_address(obj, offset >> PAGE_SHIFT), | |
987 | node.start, I915_CACHE_NONE, 0); | |
988 | wmb(); /* flush modifications to the GGTT (insert_page) */ | |
989 | } else { | |
990 | page_base += offset & PAGE_MASK; | |
991 | } | |
0839ccb8 | 992 | /* If we get a fault while copying data, then (presumably) our |
3de09aa3 EA |
993 | * source page isn't available. Return the error and we'll |
994 | * retry in the slow path. | |
b50a5371 AS |
995 | * If the object is non-shmem backed, we retry again with the |
996 | * path that handles page fault. | |
0839ccb8 | 997 | */ |
72e96d64 | 998 | if (fast_user_write(ggtt->mappable, page_base, |
935aaa69 | 999 | page_offset, user_data, page_length)) { |
b50a5371 AS |
1000 | hit_slow_path = true; |
1001 | mutex_unlock(&dev->struct_mutex); | |
1002 | if (slow_user_access(ggtt->mappable, | |
1003 | page_base, | |
1004 | page_offset, user_data, | |
1005 | page_length, true)) { | |
1006 | ret = -EFAULT; | |
1007 | mutex_lock(&dev->struct_mutex); | |
1008 | goto out_flush; | |
1009 | } | |
1010 | ||
1011 | mutex_lock(&dev->struct_mutex); | |
935aaa69 | 1012 | } |
673a394b | 1013 | |
0839ccb8 KP |
1014 | remain -= page_length; |
1015 | user_data += page_length; | |
1016 | offset += page_length; | |
673a394b | 1017 | } |
673a394b | 1018 | |
063e4e6b | 1019 | out_flush: |
b50a5371 AS |
1020 | if (hit_slow_path) { |
1021 | if (ret == 0 && | |
1022 | (obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0) { | |
1023 | /* The user has modified the object whilst we tried | |
1024 | * reading from it, and we now have no idea what domain | |
1025 | * the pages should be in. As we have just been touching | |
1026 | * them directly, flush everything back to the GTT | |
1027 | * domain. | |
1028 | */ | |
1029 | ret = i915_gem_object_set_to_gtt_domain(obj, false); | |
1030 | } | |
1031 | } | |
1032 | ||
de152b62 | 1033 | intel_fb_obj_flush(obj, false, ORIGIN_GTT); |
935aaa69 | 1034 | out_unpin: |
4f1959ee AS |
1035 | if (node.allocated) { |
1036 | wmb(); | |
1037 | ggtt->base.clear_range(&ggtt->base, | |
1038 | node.start, node.size, | |
1039 | true); | |
1040 | i915_gem_object_unpin_pages(obj); | |
1041 | remove_mappable_node(&node); | |
1042 | } else { | |
1043 | i915_gem_object_ggtt_unpin(obj); | |
1044 | } | |
935aaa69 | 1045 | out: |
3de09aa3 | 1046 | return ret; |
673a394b EA |
1047 | } |
1048 | ||
d174bd64 DV |
1049 | /* Per-page copy function for the shmem pwrite fastpath. |
1050 | * Flushes invalid cachelines before writing to the target if | |
1051 | * needs_clflush_before is set and flushes out any written cachelines after | |
1052 | * writing if needs_clflush is set. */ | |
3043c60c | 1053 | static int |
d174bd64 DV |
1054 | shmem_pwrite_fast(struct page *page, int shmem_page_offset, int page_length, |
1055 | char __user *user_data, | |
1056 | bool page_do_bit17_swizzling, | |
1057 | bool needs_clflush_before, | |
1058 | bool needs_clflush_after) | |
673a394b | 1059 | { |
d174bd64 | 1060 | char *vaddr; |
673a394b | 1061 | int ret; |
3de09aa3 | 1062 | |
e7e58eb5 | 1063 | if (unlikely(page_do_bit17_swizzling)) |
d174bd64 | 1064 | return -EINVAL; |
3de09aa3 | 1065 | |
d174bd64 DV |
1066 | vaddr = kmap_atomic(page); |
1067 | if (needs_clflush_before) | |
1068 | drm_clflush_virt_range(vaddr + shmem_page_offset, | |
1069 | page_length); | |
c2831a94 CW |
1070 | ret = __copy_from_user_inatomic(vaddr + shmem_page_offset, |
1071 | user_data, page_length); | |
d174bd64 DV |
1072 | if (needs_clflush_after) |
1073 | drm_clflush_virt_range(vaddr + shmem_page_offset, | |
1074 | page_length); | |
1075 | kunmap_atomic(vaddr); | |
3de09aa3 | 1076 | |
755d2218 | 1077 | return ret ? -EFAULT : 0; |
3de09aa3 EA |
1078 | } |
1079 | ||
d174bd64 DV |
1080 | /* Only difference to the fast-path function is that this can handle bit17 |
1081 | * and uses non-atomic copy and kmap functions. */ | |
3043c60c | 1082 | static int |
d174bd64 DV |
1083 | shmem_pwrite_slow(struct page *page, int shmem_page_offset, int page_length, |
1084 | char __user *user_data, | |
1085 | bool page_do_bit17_swizzling, | |
1086 | bool needs_clflush_before, | |
1087 | bool needs_clflush_after) | |
673a394b | 1088 | { |
d174bd64 DV |
1089 | char *vaddr; |
1090 | int ret; | |
e5281ccd | 1091 | |
d174bd64 | 1092 | vaddr = kmap(page); |
e7e58eb5 | 1093 | if (unlikely(needs_clflush_before || page_do_bit17_swizzling)) |
23c18c71 DV |
1094 | shmem_clflush_swizzled_range(vaddr + shmem_page_offset, |
1095 | page_length, | |
1096 | page_do_bit17_swizzling); | |
d174bd64 DV |
1097 | if (page_do_bit17_swizzling) |
1098 | ret = __copy_from_user_swizzled(vaddr, shmem_page_offset, | |
e5281ccd CW |
1099 | user_data, |
1100 | page_length); | |
d174bd64 DV |
1101 | else |
1102 | ret = __copy_from_user(vaddr + shmem_page_offset, | |
1103 | user_data, | |
1104 | page_length); | |
1105 | if (needs_clflush_after) | |
23c18c71 DV |
1106 | shmem_clflush_swizzled_range(vaddr + shmem_page_offset, |
1107 | page_length, | |
1108 | page_do_bit17_swizzling); | |
d174bd64 | 1109 | kunmap(page); |
40123c1f | 1110 | |
755d2218 | 1111 | return ret ? -EFAULT : 0; |
40123c1f EA |
1112 | } |
1113 | ||
40123c1f | 1114 | static int |
e244a443 DV |
1115 | i915_gem_shmem_pwrite(struct drm_device *dev, |
1116 | struct drm_i915_gem_object *obj, | |
1117 | struct drm_i915_gem_pwrite *args, | |
1118 | struct drm_file *file) | |
40123c1f | 1119 | { |
40123c1f | 1120 | ssize_t remain; |
8c59967c DV |
1121 | loff_t offset; |
1122 | char __user *user_data; | |
eb2c0c81 | 1123 | int shmem_page_offset, page_length, ret = 0; |
8c59967c | 1124 | int obj_do_bit17_swizzling, page_do_bit17_swizzling; |
e244a443 | 1125 | int hit_slowpath = 0; |
58642885 DV |
1126 | int needs_clflush_after = 0; |
1127 | int needs_clflush_before = 0; | |
67d5a50c | 1128 | struct sg_page_iter sg_iter; |
40123c1f | 1129 | |
3ed605bc | 1130 | user_data = u64_to_user_ptr(args->data_ptr); |
40123c1f EA |
1131 | remain = args->size; |
1132 | ||
8c59967c | 1133 | obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj); |
40123c1f | 1134 | |
58642885 DV |
1135 | if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) { |
1136 | /* If we're not in the cpu write domain, set ourself into the gtt | |
1137 | * write domain and manually flush cachelines (if required). This | |
1138 | * optimizes for the case when the gpu will use the data | |
1139 | * right away and we therefore have to clflush anyway. */ | |
2c22569b | 1140 | needs_clflush_after = cpu_write_needs_clflush(obj); |
23f54483 BW |
1141 | ret = i915_gem_object_wait_rendering(obj, false); |
1142 | if (ret) | |
1143 | return ret; | |
58642885 | 1144 | } |
c76ce038 CW |
1145 | /* Same trick applies to invalidate partially written cachelines read |
1146 | * before writing. */ | |
1147 | if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) | |
1148 | needs_clflush_before = | |
1149 | !cpu_cache_is_coherent(dev, obj->cache_level); | |
58642885 | 1150 | |
755d2218 CW |
1151 | ret = i915_gem_object_get_pages(obj); |
1152 | if (ret) | |
1153 | return ret; | |
1154 | ||
77a0d1ca | 1155 | intel_fb_obj_invalidate(obj, ORIGIN_CPU); |
063e4e6b | 1156 | |
755d2218 CW |
1157 | i915_gem_object_pin_pages(obj); |
1158 | ||
673a394b | 1159 | offset = args->offset; |
05394f39 | 1160 | obj->dirty = 1; |
673a394b | 1161 | |
67d5a50c ID |
1162 | for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, |
1163 | offset >> PAGE_SHIFT) { | |
2db76d7c | 1164 | struct page *page = sg_page_iter_page(&sg_iter); |
58642885 | 1165 | int partial_cacheline_write; |
e5281ccd | 1166 | |
9da3da66 CW |
1167 | if (remain <= 0) |
1168 | break; | |
1169 | ||
40123c1f EA |
1170 | /* Operation in this page |
1171 | * | |
40123c1f | 1172 | * shmem_page_offset = offset within page in shmem file |
40123c1f EA |
1173 | * page_length = bytes to copy for this page |
1174 | */ | |
c8cbbb8b | 1175 | shmem_page_offset = offset_in_page(offset); |
40123c1f EA |
1176 | |
1177 | page_length = remain; | |
1178 | if ((shmem_page_offset + page_length) > PAGE_SIZE) | |
1179 | page_length = PAGE_SIZE - shmem_page_offset; | |
40123c1f | 1180 | |
58642885 DV |
1181 | /* If we don't overwrite a cacheline completely we need to be |
1182 | * careful to have up-to-date data by first clflushing. Don't | |
1183 | * overcomplicate things and flush the entire patch. */ | |
1184 | partial_cacheline_write = needs_clflush_before && | |
1185 | ((shmem_page_offset | page_length) | |
1186 | & (boot_cpu_data.x86_clflush_size - 1)); | |
1187 | ||
8c59967c DV |
1188 | page_do_bit17_swizzling = obj_do_bit17_swizzling && |
1189 | (page_to_phys(page) & (1 << 17)) != 0; | |
1190 | ||
d174bd64 DV |
1191 | ret = shmem_pwrite_fast(page, shmem_page_offset, page_length, |
1192 | user_data, page_do_bit17_swizzling, | |
1193 | partial_cacheline_write, | |
1194 | needs_clflush_after); | |
1195 | if (ret == 0) | |
1196 | goto next_page; | |
e244a443 DV |
1197 | |
1198 | hit_slowpath = 1; | |
e244a443 | 1199 | mutex_unlock(&dev->struct_mutex); |
d174bd64 DV |
1200 | ret = shmem_pwrite_slow(page, shmem_page_offset, page_length, |
1201 | user_data, page_do_bit17_swizzling, | |
1202 | partial_cacheline_write, | |
1203 | needs_clflush_after); | |
40123c1f | 1204 | |
e244a443 | 1205 | mutex_lock(&dev->struct_mutex); |
755d2218 | 1206 | |
755d2218 | 1207 | if (ret) |
8c59967c | 1208 | goto out; |
8c59967c | 1209 | |
17793c9a | 1210 | next_page: |
40123c1f | 1211 | remain -= page_length; |
8c59967c | 1212 | user_data += page_length; |
40123c1f | 1213 | offset += page_length; |
673a394b EA |
1214 | } |
1215 | ||
fbd5a26d | 1216 | out: |
755d2218 CW |
1217 | i915_gem_object_unpin_pages(obj); |
1218 | ||
e244a443 | 1219 | if (hit_slowpath) { |
8dcf015e DV |
1220 | /* |
1221 | * Fixup: Flush cpu caches in case we didn't flush the dirty | |
1222 | * cachelines in-line while writing and the object moved | |
1223 | * out of the cpu write domain while we've dropped the lock. | |
1224 | */ | |
1225 | if (!needs_clflush_after && | |
1226 | obj->base.write_domain != I915_GEM_DOMAIN_CPU) { | |
000433b6 | 1227 | if (i915_gem_clflush_object(obj, obj->pin_display)) |
ed75a55b | 1228 | needs_clflush_after = true; |
e244a443 | 1229 | } |
8c59967c | 1230 | } |
673a394b | 1231 | |
58642885 | 1232 | if (needs_clflush_after) |
c033666a | 1233 | i915_gem_chipset_flush(to_i915(dev)); |
ed75a55b VS |
1234 | else |
1235 | obj->cache_dirty = true; | |
58642885 | 1236 | |
de152b62 | 1237 | intel_fb_obj_flush(obj, false, ORIGIN_CPU); |
40123c1f | 1238 | return ret; |
673a394b EA |
1239 | } |
1240 | ||
1241 | /** | |
1242 | * Writes data to the object referenced by handle. | |
14bb2c11 TU |
1243 | * @dev: drm device |
1244 | * @data: ioctl data blob | |
1245 | * @file: drm file | |
673a394b EA |
1246 | * |
1247 | * On error, the contents of the buffer that were to be modified are undefined. | |
1248 | */ | |
1249 | int | |
1250 | i915_gem_pwrite_ioctl(struct drm_device *dev, void *data, | |
fbd5a26d | 1251 | struct drm_file *file) |
673a394b | 1252 | { |
fac5e23e | 1253 | struct drm_i915_private *dev_priv = to_i915(dev); |
673a394b | 1254 | struct drm_i915_gem_pwrite *args = data; |
05394f39 | 1255 | struct drm_i915_gem_object *obj; |
51311d0a CW |
1256 | int ret; |
1257 | ||
1258 | if (args->size == 0) | |
1259 | return 0; | |
1260 | ||
1261 | if (!access_ok(VERIFY_READ, | |
3ed605bc | 1262 | u64_to_user_ptr(args->data_ptr), |
51311d0a CW |
1263 | args->size)) |
1264 | return -EFAULT; | |
1265 | ||
d330a953 | 1266 | if (likely(!i915.prefault_disable)) { |
3ed605bc | 1267 | ret = fault_in_multipages_readable(u64_to_user_ptr(args->data_ptr), |
0b74b508 XZ |
1268 | args->size); |
1269 | if (ret) | |
1270 | return -EFAULT; | |
1271 | } | |
673a394b | 1272 | |
5d77d9c5 ID |
1273 | intel_runtime_pm_get(dev_priv); |
1274 | ||
fbd5a26d | 1275 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 1276 | if (ret) |
5d77d9c5 | 1277 | goto put_rpm; |
1d7cfea1 | 1278 | |
a8ad0bd8 | 1279 | obj = to_intel_bo(drm_gem_object_lookup(file, args->handle)); |
c8725226 | 1280 | if (&obj->base == NULL) { |
1d7cfea1 CW |
1281 | ret = -ENOENT; |
1282 | goto unlock; | |
fbd5a26d | 1283 | } |
673a394b | 1284 | |
7dcd2499 | 1285 | /* Bounds check destination. */ |
05394f39 CW |
1286 | if (args->offset > obj->base.size || |
1287 | args->size > obj->base.size - args->offset) { | |
ce9d419d | 1288 | ret = -EINVAL; |
35b62a89 | 1289 | goto out; |
ce9d419d CW |
1290 | } |
1291 | ||
db53a302 CW |
1292 | trace_i915_gem_object_pwrite(obj, args->offset, args->size); |
1293 | ||
935aaa69 | 1294 | ret = -EFAULT; |
673a394b EA |
1295 | /* We can only do the GTT pwrite on untiled buffers, as otherwise |
1296 | * it would end up going through the fenced access, and we'll get | |
1297 | * different detiling behavior between reading and writing. | |
1298 | * pread/pwrite currently are reading and writing from the CPU | |
1299 | * perspective, requiring manual detiling by the client. | |
1300 | */ | |
6eae0059 CW |
1301 | if (!i915_gem_object_has_struct_page(obj) || |
1302 | cpu_write_needs_clflush(obj)) { | |
4f1959ee | 1303 | ret = i915_gem_gtt_pwrite_fast(dev_priv, obj, args, file); |
935aaa69 DV |
1304 | /* Note that the gtt paths might fail with non-page-backed user |
1305 | * pointers (e.g. gtt mappings when moving data between | |
1306 | * textures). Fallback to the shmem path in that case. */ | |
fbd5a26d | 1307 | } |
673a394b | 1308 | |
b50a5371 | 1309 | if (ret == -EFAULT) { |
6a2c4232 CW |
1310 | if (obj->phys_handle) |
1311 | ret = i915_gem_phys_pwrite(obj, args, file); | |
6eae0059 | 1312 | else if (i915_gem_object_has_struct_page(obj)) |
6a2c4232 | 1313 | ret = i915_gem_shmem_pwrite(dev, obj, args, file); |
b50a5371 AS |
1314 | else |
1315 | ret = -ENODEV; | |
6a2c4232 | 1316 | } |
5c0480f2 | 1317 | |
35b62a89 | 1318 | out: |
05394f39 | 1319 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 1320 | unlock: |
fbd5a26d | 1321 | mutex_unlock(&dev->struct_mutex); |
5d77d9c5 ID |
1322 | put_rpm: |
1323 | intel_runtime_pm_put(dev_priv); | |
1324 | ||
673a394b EA |
1325 | return ret; |
1326 | } | |
1327 | ||
f4457ae7 CW |
1328 | static int |
1329 | i915_gem_check_wedge(unsigned reset_counter, bool interruptible) | |
b361237b | 1330 | { |
f4457ae7 CW |
1331 | if (__i915_terminally_wedged(reset_counter)) |
1332 | return -EIO; | |
d98c52cf | 1333 | |
f4457ae7 | 1334 | if (__i915_reset_in_progress(reset_counter)) { |
b361237b CW |
1335 | /* Non-interruptible callers can't handle -EAGAIN, hence return |
1336 | * -EIO unconditionally for these. */ | |
1337 | if (!interruptible) | |
1338 | return -EIO; | |
1339 | ||
d98c52cf | 1340 | return -EAGAIN; |
b361237b CW |
1341 | } |
1342 | ||
1343 | return 0; | |
1344 | } | |
1345 | ||
ca5b721e CW |
1346 | static unsigned long local_clock_us(unsigned *cpu) |
1347 | { | |
1348 | unsigned long t; | |
1349 | ||
1350 | /* Cheaply and approximately convert from nanoseconds to microseconds. | |
1351 | * The result and subsequent calculations are also defined in the same | |
1352 | * approximate microseconds units. The principal source of timing | |
1353 | * error here is from the simple truncation. | |
1354 | * | |
1355 | * Note that local_clock() is only defined wrt to the current CPU; | |
1356 | * the comparisons are no longer valid if we switch CPUs. Instead of | |
1357 | * blocking preemption for the entire busywait, we can detect the CPU | |
1358 | * switch and use that as indicator of system load and a reason to | |
1359 | * stop busywaiting, see busywait_stop(). | |
1360 | */ | |
1361 | *cpu = get_cpu(); | |
1362 | t = local_clock() >> 10; | |
1363 | put_cpu(); | |
1364 | ||
1365 | return t; | |
1366 | } | |
1367 | ||
1368 | static bool busywait_stop(unsigned long timeout, unsigned cpu) | |
1369 | { | |
1370 | unsigned this_cpu; | |
1371 | ||
1372 | if (time_after(local_clock_us(&this_cpu), timeout)) | |
1373 | return true; | |
1374 | ||
1375 | return this_cpu != cpu; | |
1376 | } | |
1377 | ||
f69a02c9 CW |
1378 | bool __i915_spin_request(const struct drm_i915_gem_request *req, |
1379 | int state, unsigned long timeout_us) | |
b29c19b6 | 1380 | { |
ca5b721e CW |
1381 | unsigned cpu; |
1382 | ||
1383 | /* When waiting for high frequency requests, e.g. during synchronous | |
1384 | * rendering split between the CPU and GPU, the finite amount of time | |
1385 | * required to set up the irq and wait upon it limits the response | |
1386 | * rate. By busywaiting on the request completion for a short while we | |
1387 | * can service the high frequency waits as quick as possible. However, | |
1388 | * if it is a slow request, we want to sleep as quickly as possible. | |
1389 | * The tradeoff between waiting and sleeping is roughly the time it | |
1390 | * takes to sleep on a request, on the order of a microsecond. | |
1391 | */ | |
2def4ad9 | 1392 | |
f69a02c9 | 1393 | timeout_us += local_clock_us(&cpu); |
688e6c72 | 1394 | do { |
f69a02c9 | 1395 | if (i915_gem_request_completed(req)) |
688e6c72 | 1396 | return true; |
2def4ad9 | 1397 | |
91b0c352 CW |
1398 | if (signal_pending_state(state, current)) |
1399 | break; | |
1400 | ||
f69a02c9 | 1401 | if (busywait_stop(timeout_us, cpu)) |
2def4ad9 | 1402 | break; |
b29c19b6 | 1403 | |
2def4ad9 | 1404 | cpu_relax_lowlatency(); |
688e6c72 | 1405 | } while (!need_resched()); |
2def4ad9 | 1406 | |
688e6c72 | 1407 | return false; |
b29c19b6 CW |
1408 | } |
1409 | ||
b361237b | 1410 | /** |
9c654818 JH |
1411 | * __i915_wait_request - wait until execution of request has finished |
1412 | * @req: duh! | |
b361237b CW |
1413 | * @interruptible: do an interruptible wait (normally yes) |
1414 | * @timeout: in - how long to wait (NULL forever); out - how much time remaining | |
14bb2c11 | 1415 | * @rps: RPS client |
b361237b | 1416 | * |
f69061be DV |
1417 | * Note: It is of utmost importance that the passed in seqno and reset_counter |
1418 | * values have been read by the caller in an smp safe manner. Where read-side | |
1419 | * locks are involved, it is sufficient to read the reset_counter before | |
1420 | * unlocking the lock that protects the seqno. For lockless tricks, the | |
1421 | * reset_counter _must_ be read before, and an appropriate smp_rmb must be | |
1422 | * inserted. | |
1423 | * | |
9c654818 | 1424 | * Returns 0 if the request was found within the alloted time. Else returns the |
b361237b CW |
1425 | * errno with remaining time filled in timeout argument. |
1426 | */ | |
9c654818 | 1427 | int __i915_wait_request(struct drm_i915_gem_request *req, |
b29c19b6 | 1428 | bool interruptible, |
5ed0bdf2 | 1429 | s64 *timeout, |
2e1b8730 | 1430 | struct intel_rps_client *rps) |
b361237b | 1431 | { |
91b0c352 | 1432 | int state = interruptible ? TASK_INTERRUPTIBLE : TASK_UNINTERRUPTIBLE; |
1f15b76f | 1433 | DEFINE_WAIT(reset); |
688e6c72 CW |
1434 | struct intel_wait wait; |
1435 | unsigned long timeout_remain; | |
e0313db0 | 1436 | s64 before = 0; /* Only to silence a compiler warning. */ |
688e6c72 | 1437 | int ret = 0; |
b361237b | 1438 | |
688e6c72 | 1439 | might_sleep(); |
c67a470b | 1440 | |
b4716185 CW |
1441 | if (list_empty(&req->list)) |
1442 | return 0; | |
1443 | ||
f69a02c9 | 1444 | if (i915_gem_request_completed(req)) |
b361237b CW |
1445 | return 0; |
1446 | ||
688e6c72 | 1447 | timeout_remain = MAX_SCHEDULE_TIMEOUT; |
bb6d1984 CW |
1448 | if (timeout) { |
1449 | if (WARN_ON(*timeout < 0)) | |
1450 | return -EINVAL; | |
1451 | ||
1452 | if (*timeout == 0) | |
1453 | return -ETIME; | |
1454 | ||
688e6c72 | 1455 | timeout_remain = nsecs_to_jiffies_timeout(*timeout); |
e0313db0 TU |
1456 | |
1457 | /* | |
1458 | * Record current time in case interrupted by signal, or wedged. | |
1459 | */ | |
1460 | before = ktime_get_raw_ns(); | |
bb6d1984 | 1461 | } |
b361237b | 1462 | |
74328ee5 | 1463 | trace_i915_gem_request_wait_begin(req); |
2def4ad9 | 1464 | |
df4ba509 CW |
1465 | /* This client is about to stall waiting for the GPU. In many cases |
1466 | * this is undesirable and limits the throughput of the system, as | |
1467 | * many clients cannot continue processing user input/output whilst | |
1468 | * blocked. RPS autotuning may take tens of milliseconds to respond | |
1469 | * to the GPU load and thus incurs additional latency for the client. | |
1470 | * We can circumvent that by promoting the GPU frequency to maximum | |
1471 | * before we wait. This makes the GPU throttle up much more quickly | |
1472 | * (good for benchmarks and user experience, e.g. window animations), | |
1473 | * but at a cost of spending more power processing the workload | |
1474 | * (bad for battery). Not all clients even want their results | |
1475 | * immediately and for them we should just let the GPU select its own | |
1476 | * frequency to maximise efficiency. To prevent a single client from | |
1477 | * forcing the clocks too high for the whole system, we only allow | |
1478 | * each client to waitboost once in a busy period. | |
1479 | */ | |
688e6c72 CW |
1480 | if (INTEL_INFO(req->i915)->gen >= 6) |
1481 | gen6_rps_boost(req->i915, rps, req->emitted_jiffies); | |
2def4ad9 | 1482 | |
688e6c72 | 1483 | /* Optimistic spin for the next ~jiffie before touching IRQs */ |
f69a02c9 | 1484 | if (i915_spin_request(req, state, 5)) |
688e6c72 | 1485 | goto complete; |
b361237b | 1486 | |
688e6c72 CW |
1487 | set_current_state(state); |
1488 | add_wait_queue(&req->i915->gpu_error.wait_queue, &reset); | |
b361237b | 1489 | |
688e6c72 CW |
1490 | intel_wait_init(&wait, req->seqno); |
1491 | if (intel_engine_add_wait(req->engine, &wait)) | |
1492 | /* In order to check that we haven't missed the interrupt | |
1493 | * as we enabled it, we need to kick ourselves to do a | |
1494 | * coherent check on the seqno before we sleep. | |
f4457ae7 | 1495 | */ |
688e6c72 | 1496 | goto wakeup; |
b361237b | 1497 | |
688e6c72 | 1498 | for (;;) { |
91b0c352 | 1499 | if (signal_pending_state(state, current)) { |
094f9a54 CW |
1500 | ret = -ERESTARTSYS; |
1501 | break; | |
1502 | } | |
1503 | ||
05535726 CW |
1504 | /* Ensure that even if the GPU hangs, we get woken up. |
1505 | * | |
1506 | * However, note that if no one is waiting, we never notice | |
1507 | * a gpu hang. Eventually, we will have to wait for a resource | |
1508 | * held by the GPU and so trigger a hangcheck. In the most | |
1509 | * pathological case, this will be upon memory starvation! | |
1510 | */ | |
688e6c72 | 1511 | i915_queue_hangcheck(req->i915); |
47e9766d | 1512 | |
688e6c72 CW |
1513 | timeout_remain = io_schedule_timeout(timeout_remain); |
1514 | if (timeout_remain == 0) { | |
1515 | ret = -ETIME; | |
1516 | break; | |
094f9a54 CW |
1517 | } |
1518 | ||
688e6c72 CW |
1519 | if (intel_wait_complete(&wait)) |
1520 | break; | |
1f15b76f | 1521 | |
688e6c72 | 1522 | set_current_state(state); |
094f9a54 | 1523 | |
688e6c72 CW |
1524 | wakeup: |
1525 | /* Carefully check if the request is complete, giving time | |
1526 | * for the seqno to be visible following the interrupt. | |
1527 | * We also have to check in case we are kicked by the GPU | |
1528 | * reset in order to drop the struct_mutex. | |
1529 | */ | |
1530 | if (__i915_request_irq_complete(req)) | |
1531 | break; | |
f69a02c9 CW |
1532 | |
1533 | /* Only spin if we know the GPU is processing this request */ | |
1534 | if (i915_spin_request(req, state, 2)) | |
1535 | break; | |
688e6c72 CW |
1536 | } |
1537 | remove_wait_queue(&req->i915->gpu_error.wait_queue, &reset); | |
b361237b | 1538 | |
688e6c72 CW |
1539 | intel_engine_remove_wait(req->engine, &wait); |
1540 | __set_current_state(TASK_RUNNING); | |
1541 | complete: | |
2def4ad9 CW |
1542 | trace_i915_gem_request_wait_end(req); |
1543 | ||
b361237b | 1544 | if (timeout) { |
e0313db0 | 1545 | s64 tres = *timeout - (ktime_get_raw_ns() - before); |
5ed0bdf2 TG |
1546 | |
1547 | *timeout = tres < 0 ? 0 : tres; | |
9cca3068 DV |
1548 | |
1549 | /* | |
1550 | * Apparently ktime isn't accurate enough and occasionally has a | |
1551 | * bit of mismatch in the jiffies<->nsecs<->ktime loop. So patch | |
1552 | * things up to make the test happy. We allow up to 1 jiffy. | |
1553 | * | |
1554 | * This is a regrssion from the timespec->ktime conversion. | |
1555 | */ | |
1556 | if (ret == -ETIME && *timeout < jiffies_to_usecs(1)*1000) | |
1557 | *timeout = 0; | |
b361237b CW |
1558 | } |
1559 | ||
0e6883b0 CW |
1560 | if (rps && req->seqno == req->engine->last_submitted_seqno) { |
1561 | /* The GPU is now idle and this client has stalled. | |
1562 | * Since no other client has submitted a request in the | |
1563 | * meantime, assume that this client is the only one | |
1564 | * supplying work to the GPU but is unable to keep that | |
1565 | * work supplied because it is waiting. Since the GPU is | |
1566 | * then never kept fully busy, RPS autoclocking will | |
1567 | * keep the clocks relatively low, causing further delays. | |
1568 | * Compensate by giving the synchronous client credit for | |
1569 | * a waitboost next time. | |
1570 | */ | |
1571 | spin_lock(&req->i915->rps.client_lock); | |
1572 | list_del_init(&rps->link); | |
1573 | spin_unlock(&req->i915->rps.client_lock); | |
1574 | } | |
1575 | ||
094f9a54 | 1576 | return ret; |
b361237b CW |
1577 | } |
1578 | ||
fcfa423c JH |
1579 | int i915_gem_request_add_to_client(struct drm_i915_gem_request *req, |
1580 | struct drm_file *file) | |
1581 | { | |
fcfa423c JH |
1582 | struct drm_i915_file_private *file_priv; |
1583 | ||
1584 | WARN_ON(!req || !file || req->file_priv); | |
1585 | ||
1586 | if (!req || !file) | |
1587 | return -EINVAL; | |
1588 | ||
1589 | if (req->file_priv) | |
1590 | return -EINVAL; | |
1591 | ||
fcfa423c JH |
1592 | file_priv = file->driver_priv; |
1593 | ||
1594 | spin_lock(&file_priv->mm.lock); | |
1595 | req->file_priv = file_priv; | |
1596 | list_add_tail(&req->client_list, &file_priv->mm.request_list); | |
1597 | spin_unlock(&file_priv->mm.lock); | |
1598 | ||
1599 | req->pid = get_pid(task_pid(current)); | |
1600 | ||
1601 | return 0; | |
1602 | } | |
1603 | ||
b4716185 CW |
1604 | static inline void |
1605 | i915_gem_request_remove_from_client(struct drm_i915_gem_request *request) | |
1606 | { | |
1607 | struct drm_i915_file_private *file_priv = request->file_priv; | |
1608 | ||
1609 | if (!file_priv) | |
1610 | return; | |
1611 | ||
1612 | spin_lock(&file_priv->mm.lock); | |
1613 | list_del(&request->client_list); | |
1614 | request->file_priv = NULL; | |
1615 | spin_unlock(&file_priv->mm.lock); | |
fcfa423c JH |
1616 | |
1617 | put_pid(request->pid); | |
1618 | request->pid = NULL; | |
b4716185 CW |
1619 | } |
1620 | ||
1621 | static void i915_gem_request_retire(struct drm_i915_gem_request *request) | |
1622 | { | |
1623 | trace_i915_gem_request_retire(request); | |
1624 | ||
1625 | /* We know the GPU must have read the request to have | |
1626 | * sent us the seqno + interrupt, so use the position | |
1627 | * of tail of the request to update the last known position | |
1628 | * of the GPU head. | |
1629 | * | |
1630 | * Note this requires that we are always called in request | |
1631 | * completion order. | |
1632 | */ | |
1633 | request->ringbuf->last_retired_head = request->postfix; | |
1634 | ||
1635 | list_del_init(&request->list); | |
1636 | i915_gem_request_remove_from_client(request); | |
1637 | ||
a16a4052 | 1638 | if (request->previous_context) { |
73db04cf | 1639 | if (i915.enable_execlists) |
a16a4052 CW |
1640 | intel_lr_context_unpin(request->previous_context, |
1641 | request->engine); | |
73db04cf CW |
1642 | } |
1643 | ||
a16a4052 | 1644 | i915_gem_context_unreference(request->ctx); |
b4716185 CW |
1645 | i915_gem_request_unreference(request); |
1646 | } | |
1647 | ||
1648 | static void | |
1649 | __i915_gem_request_retire__upto(struct drm_i915_gem_request *req) | |
1650 | { | |
4a570db5 | 1651 | struct intel_engine_cs *engine = req->engine; |
b4716185 CW |
1652 | struct drm_i915_gem_request *tmp; |
1653 | ||
91c8a326 | 1654 | lockdep_assert_held(&engine->i915->drm.struct_mutex); |
b4716185 CW |
1655 | |
1656 | if (list_empty(&req->list)) | |
1657 | return; | |
1658 | ||
1659 | do { | |
1660 | tmp = list_first_entry(&engine->request_list, | |
1661 | typeof(*tmp), list); | |
1662 | ||
1663 | i915_gem_request_retire(tmp); | |
1664 | } while (tmp != req); | |
1665 | ||
1666 | WARN_ON(i915_verify_lists(engine->dev)); | |
1667 | } | |
1668 | ||
b361237b | 1669 | /** |
a4b3a571 | 1670 | * Waits for a request to be signaled, and cleans up the |
b361237b | 1671 | * request and object lists appropriately for that event. |
14bb2c11 | 1672 | * @req: request to wait on |
b361237b CW |
1673 | */ |
1674 | int | |
a4b3a571 | 1675 | i915_wait_request(struct drm_i915_gem_request *req) |
b361237b | 1676 | { |
791bee12 | 1677 | struct drm_i915_private *dev_priv = req->i915; |
a4b3a571 | 1678 | bool interruptible; |
b361237b CW |
1679 | int ret; |
1680 | ||
a4b3a571 DV |
1681 | interruptible = dev_priv->mm.interruptible; |
1682 | ||
91c8a326 | 1683 | BUG_ON(!mutex_is_locked(&dev_priv->drm.struct_mutex)); |
b361237b | 1684 | |
299259a3 | 1685 | ret = __i915_wait_request(req, interruptible, NULL, NULL); |
b4716185 CW |
1686 | if (ret) |
1687 | return ret; | |
d26e3af8 | 1688 | |
e075a32f | 1689 | /* If the GPU hung, we want to keep the requests to find the guilty. */ |
0c5eed65 | 1690 | if (!i915_reset_in_progress(&dev_priv->gpu_error)) |
e075a32f CW |
1691 | __i915_gem_request_retire__upto(req); |
1692 | ||
d26e3af8 CW |
1693 | return 0; |
1694 | } | |
1695 | ||
b361237b CW |
1696 | /** |
1697 | * Ensures that all rendering to the object has completed and the object is | |
1698 | * safe to unbind from the GTT or access from the CPU. | |
14bb2c11 TU |
1699 | * @obj: i915 gem object |
1700 | * @readonly: waiting for read access or write | |
b361237b | 1701 | */ |
2e2f351d | 1702 | int |
b361237b CW |
1703 | i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj, |
1704 | bool readonly) | |
1705 | { | |
b4716185 | 1706 | int ret, i; |
b361237b | 1707 | |
b4716185 | 1708 | if (!obj->active) |
b361237b CW |
1709 | return 0; |
1710 | ||
b4716185 CW |
1711 | if (readonly) { |
1712 | if (obj->last_write_req != NULL) { | |
1713 | ret = i915_wait_request(obj->last_write_req); | |
1714 | if (ret) | |
1715 | return ret; | |
b361237b | 1716 | |
4a570db5 | 1717 | i = obj->last_write_req->engine->id; |
b4716185 CW |
1718 | if (obj->last_read_req[i] == obj->last_write_req) |
1719 | i915_gem_object_retire__read(obj, i); | |
1720 | else | |
1721 | i915_gem_object_retire__write(obj); | |
1722 | } | |
1723 | } else { | |
666796da | 1724 | for (i = 0; i < I915_NUM_ENGINES; i++) { |
b4716185 CW |
1725 | if (obj->last_read_req[i] == NULL) |
1726 | continue; | |
1727 | ||
1728 | ret = i915_wait_request(obj->last_read_req[i]); | |
1729 | if (ret) | |
1730 | return ret; | |
1731 | ||
1732 | i915_gem_object_retire__read(obj, i); | |
1733 | } | |
d501b1d2 | 1734 | GEM_BUG_ON(obj->active); |
b4716185 CW |
1735 | } |
1736 | ||
1737 | return 0; | |
1738 | } | |
1739 | ||
1740 | static void | |
1741 | i915_gem_object_retire_request(struct drm_i915_gem_object *obj, | |
1742 | struct drm_i915_gem_request *req) | |
1743 | { | |
4a570db5 | 1744 | int ring = req->engine->id; |
b4716185 CW |
1745 | |
1746 | if (obj->last_read_req[ring] == req) | |
1747 | i915_gem_object_retire__read(obj, ring); | |
1748 | else if (obj->last_write_req == req) | |
1749 | i915_gem_object_retire__write(obj); | |
1750 | ||
0c5eed65 | 1751 | if (!i915_reset_in_progress(&req->i915->gpu_error)) |
e075a32f | 1752 | __i915_gem_request_retire__upto(req); |
b361237b CW |
1753 | } |
1754 | ||
3236f57a CW |
1755 | /* A nonblocking variant of the above wait. This is a highly dangerous routine |
1756 | * as the object state may change during this call. | |
1757 | */ | |
1758 | static __must_check int | |
1759 | i915_gem_object_wait_rendering__nonblocking(struct drm_i915_gem_object *obj, | |
2e1b8730 | 1760 | struct intel_rps_client *rps, |
3236f57a CW |
1761 | bool readonly) |
1762 | { | |
1763 | struct drm_device *dev = obj->base.dev; | |
fac5e23e | 1764 | struct drm_i915_private *dev_priv = to_i915(dev); |
666796da | 1765 | struct drm_i915_gem_request *requests[I915_NUM_ENGINES]; |
b4716185 | 1766 | int ret, i, n = 0; |
3236f57a CW |
1767 | |
1768 | BUG_ON(!mutex_is_locked(&dev->struct_mutex)); | |
1769 | BUG_ON(!dev_priv->mm.interruptible); | |
1770 | ||
b4716185 | 1771 | if (!obj->active) |
3236f57a CW |
1772 | return 0; |
1773 | ||
b4716185 CW |
1774 | if (readonly) { |
1775 | struct drm_i915_gem_request *req; | |
1776 | ||
1777 | req = obj->last_write_req; | |
1778 | if (req == NULL) | |
1779 | return 0; | |
1780 | ||
b4716185 CW |
1781 | requests[n++] = i915_gem_request_reference(req); |
1782 | } else { | |
666796da | 1783 | for (i = 0; i < I915_NUM_ENGINES; i++) { |
b4716185 CW |
1784 | struct drm_i915_gem_request *req; |
1785 | ||
1786 | req = obj->last_read_req[i]; | |
1787 | if (req == NULL) | |
1788 | continue; | |
1789 | ||
b4716185 CW |
1790 | requests[n++] = i915_gem_request_reference(req); |
1791 | } | |
1792 | } | |
1793 | ||
3236f57a | 1794 | mutex_unlock(&dev->struct_mutex); |
299259a3 | 1795 | ret = 0; |
b4716185 | 1796 | for (i = 0; ret == 0 && i < n; i++) |
299259a3 | 1797 | ret = __i915_wait_request(requests[i], true, NULL, rps); |
3236f57a CW |
1798 | mutex_lock(&dev->struct_mutex); |
1799 | ||
b4716185 CW |
1800 | for (i = 0; i < n; i++) { |
1801 | if (ret == 0) | |
1802 | i915_gem_object_retire_request(obj, requests[i]); | |
1803 | i915_gem_request_unreference(requests[i]); | |
1804 | } | |
1805 | ||
1806 | return ret; | |
3236f57a CW |
1807 | } |
1808 | ||
2e1b8730 CW |
1809 | static struct intel_rps_client *to_rps_client(struct drm_file *file) |
1810 | { | |
1811 | struct drm_i915_file_private *fpriv = file->driver_priv; | |
1812 | return &fpriv->rps; | |
1813 | } | |
1814 | ||
aeecc969 CW |
1815 | static enum fb_op_origin |
1816 | write_origin(struct drm_i915_gem_object *obj, unsigned domain) | |
1817 | { | |
1818 | return domain == I915_GEM_DOMAIN_GTT && !obj->has_wc_mmap ? | |
1819 | ORIGIN_GTT : ORIGIN_CPU; | |
1820 | } | |
1821 | ||
673a394b | 1822 | /** |
2ef7eeaa EA |
1823 | * Called when user space prepares to use an object with the CPU, either |
1824 | * through the mmap ioctl's mapping or a GTT mapping. | |
14bb2c11 TU |
1825 | * @dev: drm device |
1826 | * @data: ioctl data blob | |
1827 | * @file: drm file | |
673a394b EA |
1828 | */ |
1829 | int | |
1830 | i915_gem_set_domain_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 1831 | struct drm_file *file) |
673a394b EA |
1832 | { |
1833 | struct drm_i915_gem_set_domain *args = data; | |
05394f39 | 1834 | struct drm_i915_gem_object *obj; |
2ef7eeaa EA |
1835 | uint32_t read_domains = args->read_domains; |
1836 | uint32_t write_domain = args->write_domain; | |
673a394b EA |
1837 | int ret; |
1838 | ||
2ef7eeaa | 1839 | /* Only handle setting domains to types used by the CPU. */ |
21d509e3 | 1840 | if (write_domain & I915_GEM_GPU_DOMAINS) |
2ef7eeaa EA |
1841 | return -EINVAL; |
1842 | ||
21d509e3 | 1843 | if (read_domains & I915_GEM_GPU_DOMAINS) |
2ef7eeaa EA |
1844 | return -EINVAL; |
1845 | ||
1846 | /* Having something in the write domain implies it's in the read | |
1847 | * domain, and only that read domain. Enforce that in the request. | |
1848 | */ | |
1849 | if (write_domain != 0 && read_domains != write_domain) | |
1850 | return -EINVAL; | |
1851 | ||
76c1dec1 | 1852 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 1853 | if (ret) |
76c1dec1 | 1854 | return ret; |
1d7cfea1 | 1855 | |
a8ad0bd8 | 1856 | obj = to_intel_bo(drm_gem_object_lookup(file, args->handle)); |
c8725226 | 1857 | if (&obj->base == NULL) { |
1d7cfea1 CW |
1858 | ret = -ENOENT; |
1859 | goto unlock; | |
76c1dec1 | 1860 | } |
673a394b | 1861 | |
3236f57a CW |
1862 | /* Try to flush the object off the GPU without holding the lock. |
1863 | * We will repeat the flush holding the lock in the normal manner | |
1864 | * to catch cases where we are gazumped. | |
1865 | */ | |
6e4930f6 | 1866 | ret = i915_gem_object_wait_rendering__nonblocking(obj, |
2e1b8730 | 1867 | to_rps_client(file), |
6e4930f6 | 1868 | !write_domain); |
3236f57a CW |
1869 | if (ret) |
1870 | goto unref; | |
1871 | ||
43566ded | 1872 | if (read_domains & I915_GEM_DOMAIN_GTT) |
2ef7eeaa | 1873 | ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0); |
43566ded | 1874 | else |
e47c68e9 | 1875 | ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0); |
2ef7eeaa | 1876 | |
031b698a | 1877 | if (write_domain != 0) |
aeecc969 | 1878 | intel_fb_obj_invalidate(obj, write_origin(obj, write_domain)); |
031b698a | 1879 | |
3236f57a | 1880 | unref: |
05394f39 | 1881 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 1882 | unlock: |
673a394b EA |
1883 | mutex_unlock(&dev->struct_mutex); |
1884 | return ret; | |
1885 | } | |
1886 | ||
1887 | /** | |
1888 | * Called when user space has done writes to this buffer | |
14bb2c11 TU |
1889 | * @dev: drm device |
1890 | * @data: ioctl data blob | |
1891 | * @file: drm file | |
673a394b EA |
1892 | */ |
1893 | int | |
1894 | i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 1895 | struct drm_file *file) |
673a394b EA |
1896 | { |
1897 | struct drm_i915_gem_sw_finish *args = data; | |
05394f39 | 1898 | struct drm_i915_gem_object *obj; |
673a394b EA |
1899 | int ret = 0; |
1900 | ||
76c1dec1 | 1901 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 1902 | if (ret) |
76c1dec1 | 1903 | return ret; |
1d7cfea1 | 1904 | |
a8ad0bd8 | 1905 | obj = to_intel_bo(drm_gem_object_lookup(file, args->handle)); |
c8725226 | 1906 | if (&obj->base == NULL) { |
1d7cfea1 CW |
1907 | ret = -ENOENT; |
1908 | goto unlock; | |
673a394b EA |
1909 | } |
1910 | ||
673a394b | 1911 | /* Pinned buffers may be scanout, so flush the cache */ |
2c22569b | 1912 | if (obj->pin_display) |
e62b59e4 | 1913 | i915_gem_object_flush_cpu_write_domain(obj); |
e47c68e9 | 1914 | |
05394f39 | 1915 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 1916 | unlock: |
673a394b EA |
1917 | mutex_unlock(&dev->struct_mutex); |
1918 | return ret; | |
1919 | } | |
1920 | ||
1921 | /** | |
14bb2c11 TU |
1922 | * i915_gem_mmap_ioctl - Maps the contents of an object, returning the address |
1923 | * it is mapped to. | |
1924 | * @dev: drm device | |
1925 | * @data: ioctl data blob | |
1926 | * @file: drm file | |
673a394b EA |
1927 | * |
1928 | * While the mapping holds a reference on the contents of the object, it doesn't | |
1929 | * imply a ref on the object itself. | |
34367381 DV |
1930 | * |
1931 | * IMPORTANT: | |
1932 | * | |
1933 | * DRM driver writers who look a this function as an example for how to do GEM | |
1934 | * mmap support, please don't implement mmap support like here. The modern way | |
1935 | * to implement DRM mmap support is with an mmap offset ioctl (like | |
1936 | * i915_gem_mmap_gtt) and then using the mmap syscall on the DRM fd directly. | |
1937 | * That way debug tooling like valgrind will understand what's going on, hiding | |
1938 | * the mmap call in a driver private ioctl will break that. The i915 driver only | |
1939 | * does cpu mmaps this way because we didn't know better. | |
673a394b EA |
1940 | */ |
1941 | int | |
1942 | i915_gem_mmap_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 1943 | struct drm_file *file) |
673a394b EA |
1944 | { |
1945 | struct drm_i915_gem_mmap *args = data; | |
1946 | struct drm_gem_object *obj; | |
673a394b EA |
1947 | unsigned long addr; |
1948 | ||
1816f923 AG |
1949 | if (args->flags & ~(I915_MMAP_WC)) |
1950 | return -EINVAL; | |
1951 | ||
568a58e5 | 1952 | if (args->flags & I915_MMAP_WC && !boot_cpu_has(X86_FEATURE_PAT)) |
1816f923 AG |
1953 | return -ENODEV; |
1954 | ||
a8ad0bd8 | 1955 | obj = drm_gem_object_lookup(file, args->handle); |
673a394b | 1956 | if (obj == NULL) |
bf79cb91 | 1957 | return -ENOENT; |
673a394b | 1958 | |
1286ff73 DV |
1959 | /* prime objects have no backing filp to GEM mmap |
1960 | * pages from. | |
1961 | */ | |
1962 | if (!obj->filp) { | |
1963 | drm_gem_object_unreference_unlocked(obj); | |
1964 | return -EINVAL; | |
1965 | } | |
1966 | ||
6be5ceb0 | 1967 | addr = vm_mmap(obj->filp, 0, args->size, |
673a394b EA |
1968 | PROT_READ | PROT_WRITE, MAP_SHARED, |
1969 | args->offset); | |
1816f923 AG |
1970 | if (args->flags & I915_MMAP_WC) { |
1971 | struct mm_struct *mm = current->mm; | |
1972 | struct vm_area_struct *vma; | |
1973 | ||
80a89a5e MH |
1974 | if (down_write_killable(&mm->mmap_sem)) { |
1975 | drm_gem_object_unreference_unlocked(obj); | |
1976 | return -EINTR; | |
1977 | } | |
1816f923 AG |
1978 | vma = find_vma(mm, addr); |
1979 | if (vma) | |
1980 | vma->vm_page_prot = | |
1981 | pgprot_writecombine(vm_get_page_prot(vma->vm_flags)); | |
1982 | else | |
1983 | addr = -ENOMEM; | |
1984 | up_write(&mm->mmap_sem); | |
aeecc969 CW |
1985 | |
1986 | /* This may race, but that's ok, it only gets set */ | |
1987 | WRITE_ONCE(to_intel_bo(obj)->has_wc_mmap, true); | |
1816f923 | 1988 | } |
bc9025bd | 1989 | drm_gem_object_unreference_unlocked(obj); |
673a394b EA |
1990 | if (IS_ERR((void *)addr)) |
1991 | return addr; | |
1992 | ||
1993 | args->addr_ptr = (uint64_t) addr; | |
1994 | ||
1995 | return 0; | |
1996 | } | |
1997 | ||
de151cf6 JB |
1998 | /** |
1999 | * i915_gem_fault - fault a page into the GTT | |
d9072a3e GT |
2000 | * @vma: VMA in question |
2001 | * @vmf: fault info | |
de151cf6 JB |
2002 | * |
2003 | * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped | |
2004 | * from userspace. The fault handler takes care of binding the object to | |
2005 | * the GTT (if needed), allocating and programming a fence register (again, | |
2006 | * only if needed based on whether the old reg is still valid or the object | |
2007 | * is tiled) and inserting a new PTE into the faulting process. | |
2008 | * | |
2009 | * Note that the faulting process may involve evicting existing objects | |
2010 | * from the GTT and/or fence registers to make room. So performance may | |
2011 | * suffer if the GTT working set is large or there are few fence registers | |
2012 | * left. | |
2013 | */ | |
2014 | int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf) | |
2015 | { | |
05394f39 CW |
2016 | struct drm_i915_gem_object *obj = to_intel_bo(vma->vm_private_data); |
2017 | struct drm_device *dev = obj->base.dev; | |
72e96d64 JL |
2018 | struct drm_i915_private *dev_priv = to_i915(dev); |
2019 | struct i915_ggtt *ggtt = &dev_priv->ggtt; | |
c5ad54cf | 2020 | struct i915_ggtt_view view = i915_ggtt_view_normal; |
de151cf6 JB |
2021 | pgoff_t page_offset; |
2022 | unsigned long pfn; | |
2023 | int ret = 0; | |
0f973f27 | 2024 | bool write = !!(vmf->flags & FAULT_FLAG_WRITE); |
de151cf6 | 2025 | |
f65c9168 PZ |
2026 | intel_runtime_pm_get(dev_priv); |
2027 | ||
de151cf6 JB |
2028 | /* We don't use vmf->pgoff since that has the fake offset */ |
2029 | page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >> | |
2030 | PAGE_SHIFT; | |
2031 | ||
d9bc7e9f CW |
2032 | ret = i915_mutex_lock_interruptible(dev); |
2033 | if (ret) | |
2034 | goto out; | |
a00b10c3 | 2035 | |
db53a302 CW |
2036 | trace_i915_gem_object_fault(obj, page_offset, true, write); |
2037 | ||
6e4930f6 CW |
2038 | /* Try to flush the object off the GPU first without holding the lock. |
2039 | * Upon reacquiring the lock, we will perform our sanity checks and then | |
2040 | * repeat the flush holding the lock in the normal manner to catch cases | |
2041 | * where we are gazumped. | |
2042 | */ | |
2043 | ret = i915_gem_object_wait_rendering__nonblocking(obj, NULL, !write); | |
2044 | if (ret) | |
2045 | goto unlock; | |
2046 | ||
eb119bd6 CW |
2047 | /* Access to snoopable pages through the GTT is incoherent. */ |
2048 | if (obj->cache_level != I915_CACHE_NONE && !HAS_LLC(dev)) { | |
ddeff6ee | 2049 | ret = -EFAULT; |
eb119bd6 CW |
2050 | goto unlock; |
2051 | } | |
2052 | ||
c5ad54cf | 2053 | /* Use a partial view if the object is bigger than the aperture. */ |
72e96d64 | 2054 | if (obj->base.size >= ggtt->mappable_end && |
e7ded2d7 | 2055 | obj->tiling_mode == I915_TILING_NONE) { |
c5ad54cf | 2056 | static const unsigned int chunk_size = 256; // 1 MiB |
e7ded2d7 | 2057 | |
c5ad54cf JL |
2058 | memset(&view, 0, sizeof(view)); |
2059 | view.type = I915_GGTT_VIEW_PARTIAL; | |
2060 | view.params.partial.offset = rounddown(page_offset, chunk_size); | |
2061 | view.params.partial.size = | |
2062 | min_t(unsigned int, | |
2063 | chunk_size, | |
2064 | (vma->vm_end - vma->vm_start)/PAGE_SIZE - | |
2065 | view.params.partial.offset); | |
2066 | } | |
2067 | ||
2068 | /* Now pin it into the GTT if needed */ | |
2069 | ret = i915_gem_object_ggtt_pin(obj, &view, 0, PIN_MAPPABLE); | |
c9839303 CW |
2070 | if (ret) |
2071 | goto unlock; | |
4a684a41 | 2072 | |
c9839303 CW |
2073 | ret = i915_gem_object_set_to_gtt_domain(obj, write); |
2074 | if (ret) | |
2075 | goto unpin; | |
74898d7e | 2076 | |
06d98131 | 2077 | ret = i915_gem_object_get_fence(obj); |
d9e86c0e | 2078 | if (ret) |
c9839303 | 2079 | goto unpin; |
7d1c4804 | 2080 | |
b90b91d8 | 2081 | /* Finally, remap it using the new GTT offset */ |
72e96d64 | 2082 | pfn = ggtt->mappable_base + |
c5ad54cf | 2083 | i915_gem_obj_ggtt_offset_view(obj, &view); |
f343c5f6 | 2084 | pfn >>= PAGE_SHIFT; |
de151cf6 | 2085 | |
c5ad54cf JL |
2086 | if (unlikely(view.type == I915_GGTT_VIEW_PARTIAL)) { |
2087 | /* Overriding existing pages in partial view does not cause | |
2088 | * us any trouble as TLBs are still valid because the fault | |
2089 | * is due to userspace losing part of the mapping or never | |
2090 | * having accessed it before (at this partials' range). | |
2091 | */ | |
2092 | unsigned long base = vma->vm_start + | |
2093 | (view.params.partial.offset << PAGE_SHIFT); | |
2094 | unsigned int i; | |
b90b91d8 | 2095 | |
c5ad54cf JL |
2096 | for (i = 0; i < view.params.partial.size; i++) { |
2097 | ret = vm_insert_pfn(vma, base + i * PAGE_SIZE, pfn + i); | |
b90b91d8 CW |
2098 | if (ret) |
2099 | break; | |
2100 | } | |
2101 | ||
2102 | obj->fault_mappable = true; | |
c5ad54cf JL |
2103 | } else { |
2104 | if (!obj->fault_mappable) { | |
2105 | unsigned long size = min_t(unsigned long, | |
2106 | vma->vm_end - vma->vm_start, | |
2107 | obj->base.size); | |
2108 | int i; | |
2109 | ||
2110 | for (i = 0; i < size >> PAGE_SHIFT; i++) { | |
2111 | ret = vm_insert_pfn(vma, | |
2112 | (unsigned long)vma->vm_start + i * PAGE_SIZE, | |
2113 | pfn + i); | |
2114 | if (ret) | |
2115 | break; | |
2116 | } | |
2117 | ||
2118 | obj->fault_mappable = true; | |
2119 | } else | |
2120 | ret = vm_insert_pfn(vma, | |
2121 | (unsigned long)vmf->virtual_address, | |
2122 | pfn + page_offset); | |
2123 | } | |
c9839303 | 2124 | unpin: |
c5ad54cf | 2125 | i915_gem_object_ggtt_unpin_view(obj, &view); |
c715089f | 2126 | unlock: |
de151cf6 | 2127 | mutex_unlock(&dev->struct_mutex); |
d9bc7e9f | 2128 | out: |
de151cf6 | 2129 | switch (ret) { |
d9bc7e9f | 2130 | case -EIO: |
2232f031 DV |
2131 | /* |
2132 | * We eat errors when the gpu is terminally wedged to avoid | |
2133 | * userspace unduly crashing (gl has no provisions for mmaps to | |
2134 | * fail). But any other -EIO isn't ours (e.g. swap in failure) | |
2135 | * and so needs to be reported. | |
2136 | */ | |
2137 | if (!i915_terminally_wedged(&dev_priv->gpu_error)) { | |
f65c9168 PZ |
2138 | ret = VM_FAULT_SIGBUS; |
2139 | break; | |
2140 | } | |
045e769a | 2141 | case -EAGAIN: |
571c608d DV |
2142 | /* |
2143 | * EAGAIN means the gpu is hung and we'll wait for the error | |
2144 | * handler to reset everything when re-faulting in | |
2145 | * i915_mutex_lock_interruptible. | |
d9bc7e9f | 2146 | */ |
c715089f CW |
2147 | case 0: |
2148 | case -ERESTARTSYS: | |
bed636ab | 2149 | case -EINTR: |
e79e0fe3 DR |
2150 | case -EBUSY: |
2151 | /* | |
2152 | * EBUSY is ok: this just means that another thread | |
2153 | * already did the job. | |
2154 | */ | |
f65c9168 PZ |
2155 | ret = VM_FAULT_NOPAGE; |
2156 | break; | |
de151cf6 | 2157 | case -ENOMEM: |
f65c9168 PZ |
2158 | ret = VM_FAULT_OOM; |
2159 | break; | |
a7c2e1aa | 2160 | case -ENOSPC: |
45d67817 | 2161 | case -EFAULT: |
f65c9168 PZ |
2162 | ret = VM_FAULT_SIGBUS; |
2163 | break; | |
de151cf6 | 2164 | default: |
a7c2e1aa | 2165 | WARN_ONCE(ret, "unhandled error in i915_gem_fault: %i\n", ret); |
f65c9168 PZ |
2166 | ret = VM_FAULT_SIGBUS; |
2167 | break; | |
de151cf6 | 2168 | } |
f65c9168 PZ |
2169 | |
2170 | intel_runtime_pm_put(dev_priv); | |
2171 | return ret; | |
de151cf6 JB |
2172 | } |
2173 | ||
901782b2 CW |
2174 | /** |
2175 | * i915_gem_release_mmap - remove physical page mappings | |
2176 | * @obj: obj in question | |
2177 | * | |
af901ca1 | 2178 | * Preserve the reservation of the mmapping with the DRM core code, but |
901782b2 CW |
2179 | * relinquish ownership of the pages back to the system. |
2180 | * | |
2181 | * It is vital that we remove the page mapping if we have mapped a tiled | |
2182 | * object through the GTT and then lose the fence register due to | |
2183 | * resource pressure. Similarly if the object has been moved out of the | |
2184 | * aperture, than pages mapped into userspace must be revoked. Removing the | |
2185 | * mapping will then trigger a page fault on the next user access, allowing | |
2186 | * fixup by i915_gem_fault(). | |
2187 | */ | |
d05ca301 | 2188 | void |
05394f39 | 2189 | i915_gem_release_mmap(struct drm_i915_gem_object *obj) |
901782b2 | 2190 | { |
349f2ccf CW |
2191 | /* Serialisation between user GTT access and our code depends upon |
2192 | * revoking the CPU's PTE whilst the mutex is held. The next user | |
2193 | * pagefault then has to wait until we release the mutex. | |
2194 | */ | |
2195 | lockdep_assert_held(&obj->base.dev->struct_mutex); | |
2196 | ||
6299f992 CW |
2197 | if (!obj->fault_mappable) |
2198 | return; | |
901782b2 | 2199 | |
6796cb16 DH |
2200 | drm_vma_node_unmap(&obj->base.vma_node, |
2201 | obj->base.dev->anon_inode->i_mapping); | |
349f2ccf CW |
2202 | |
2203 | /* Ensure that the CPU's PTE are revoked and there are not outstanding | |
2204 | * memory transactions from userspace before we return. The TLB | |
2205 | * flushing implied above by changing the PTE above *should* be | |
2206 | * sufficient, an extra barrier here just provides us with a bit | |
2207 | * of paranoid documentation about our requirement to serialise | |
2208 | * memory writes before touching registers / GSM. | |
2209 | */ | |
2210 | wmb(); | |
2211 | ||
6299f992 | 2212 | obj->fault_mappable = false; |
901782b2 CW |
2213 | } |
2214 | ||
eedd10f4 CW |
2215 | void |
2216 | i915_gem_release_all_mmaps(struct drm_i915_private *dev_priv) | |
2217 | { | |
2218 | struct drm_i915_gem_object *obj; | |
2219 | ||
2220 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) | |
2221 | i915_gem_release_mmap(obj); | |
2222 | } | |
2223 | ||
0fa87796 | 2224 | uint32_t |
e28f8711 | 2225 | i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode) |
92b88aeb | 2226 | { |
e28f8711 | 2227 | uint32_t gtt_size; |
92b88aeb CW |
2228 | |
2229 | if (INTEL_INFO(dev)->gen >= 4 || | |
e28f8711 CW |
2230 | tiling_mode == I915_TILING_NONE) |
2231 | return size; | |
92b88aeb CW |
2232 | |
2233 | /* Previous chips need a power-of-two fence region when tiling */ | |
7e22dbbb | 2234 | if (IS_GEN3(dev)) |
e28f8711 | 2235 | gtt_size = 1024*1024; |
92b88aeb | 2236 | else |
e28f8711 | 2237 | gtt_size = 512*1024; |
92b88aeb | 2238 | |
e28f8711 CW |
2239 | while (gtt_size < size) |
2240 | gtt_size <<= 1; | |
92b88aeb | 2241 | |
e28f8711 | 2242 | return gtt_size; |
92b88aeb CW |
2243 | } |
2244 | ||
de151cf6 JB |
2245 | /** |
2246 | * i915_gem_get_gtt_alignment - return required GTT alignment for an object | |
14bb2c11 TU |
2247 | * @dev: drm device |
2248 | * @size: object size | |
2249 | * @tiling_mode: tiling mode | |
2250 | * @fenced: is fenced alignemned required or not | |
de151cf6 JB |
2251 | * |
2252 | * Return the required GTT alignment for an object, taking into account | |
5e783301 | 2253 | * potential fence register mapping. |
de151cf6 | 2254 | */ |
d865110c ID |
2255 | uint32_t |
2256 | i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size, | |
2257 | int tiling_mode, bool fenced) | |
de151cf6 | 2258 | { |
de151cf6 JB |
2259 | /* |
2260 | * Minimum alignment is 4k (GTT page size), but might be greater | |
2261 | * if a fence register is needed for the object. | |
2262 | */ | |
d865110c | 2263 | if (INTEL_INFO(dev)->gen >= 4 || (!fenced && IS_G33(dev)) || |
e28f8711 | 2264 | tiling_mode == I915_TILING_NONE) |
de151cf6 JB |
2265 | return 4096; |
2266 | ||
a00b10c3 CW |
2267 | /* |
2268 | * Previous chips need to be aligned to the size of the smallest | |
2269 | * fence register that can contain the object. | |
2270 | */ | |
e28f8711 | 2271 | return i915_gem_get_gtt_size(dev, size, tiling_mode); |
a00b10c3 CW |
2272 | } |
2273 | ||
d8cb5086 CW |
2274 | static int i915_gem_object_create_mmap_offset(struct drm_i915_gem_object *obj) |
2275 | { | |
fac5e23e | 2276 | struct drm_i915_private *dev_priv = to_i915(obj->base.dev); |
d8cb5086 CW |
2277 | int ret; |
2278 | ||
da494d7c DV |
2279 | dev_priv->mm.shrinker_no_lock_stealing = true; |
2280 | ||
d8cb5086 CW |
2281 | ret = drm_gem_create_mmap_offset(&obj->base); |
2282 | if (ret != -ENOSPC) | |
da494d7c | 2283 | goto out; |
d8cb5086 CW |
2284 | |
2285 | /* Badly fragmented mmap space? The only way we can recover | |
2286 | * space is by destroying unwanted objects. We can't randomly release | |
2287 | * mmap_offsets as userspace expects them to be persistent for the | |
2288 | * lifetime of the objects. The closest we can is to release the | |
2289 | * offsets on purgeable objects by truncating it and marking it purged, | |
2290 | * which prevents userspace from ever using that object again. | |
2291 | */ | |
21ab4e74 CW |
2292 | i915_gem_shrink(dev_priv, |
2293 | obj->base.size >> PAGE_SHIFT, | |
2294 | I915_SHRINK_BOUND | | |
2295 | I915_SHRINK_UNBOUND | | |
2296 | I915_SHRINK_PURGEABLE); | |
d8cb5086 CW |
2297 | ret = drm_gem_create_mmap_offset(&obj->base); |
2298 | if (ret != -ENOSPC) | |
da494d7c | 2299 | goto out; |
d8cb5086 CW |
2300 | |
2301 | i915_gem_shrink_all(dev_priv); | |
da494d7c DV |
2302 | ret = drm_gem_create_mmap_offset(&obj->base); |
2303 | out: | |
2304 | dev_priv->mm.shrinker_no_lock_stealing = false; | |
2305 | ||
2306 | return ret; | |
d8cb5086 CW |
2307 | } |
2308 | ||
2309 | static void i915_gem_object_free_mmap_offset(struct drm_i915_gem_object *obj) | |
2310 | { | |
d8cb5086 CW |
2311 | drm_gem_free_mmap_offset(&obj->base); |
2312 | } | |
2313 | ||
da6b51d0 | 2314 | int |
ff72145b DA |
2315 | i915_gem_mmap_gtt(struct drm_file *file, |
2316 | struct drm_device *dev, | |
da6b51d0 | 2317 | uint32_t handle, |
ff72145b | 2318 | uint64_t *offset) |
de151cf6 | 2319 | { |
05394f39 | 2320 | struct drm_i915_gem_object *obj; |
de151cf6 JB |
2321 | int ret; |
2322 | ||
76c1dec1 | 2323 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 2324 | if (ret) |
76c1dec1 | 2325 | return ret; |
de151cf6 | 2326 | |
a8ad0bd8 | 2327 | obj = to_intel_bo(drm_gem_object_lookup(file, handle)); |
c8725226 | 2328 | if (&obj->base == NULL) { |
1d7cfea1 CW |
2329 | ret = -ENOENT; |
2330 | goto unlock; | |
2331 | } | |
de151cf6 | 2332 | |
05394f39 | 2333 | if (obj->madv != I915_MADV_WILLNEED) { |
bd9b6a4e | 2334 | DRM_DEBUG("Attempting to mmap a purgeable buffer\n"); |
8c99e57d | 2335 | ret = -EFAULT; |
1d7cfea1 | 2336 | goto out; |
ab18282d CW |
2337 | } |
2338 | ||
d8cb5086 CW |
2339 | ret = i915_gem_object_create_mmap_offset(obj); |
2340 | if (ret) | |
2341 | goto out; | |
de151cf6 | 2342 | |
0de23977 | 2343 | *offset = drm_vma_node_offset_addr(&obj->base.vma_node); |
de151cf6 | 2344 | |
1d7cfea1 | 2345 | out: |
05394f39 | 2346 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 2347 | unlock: |
de151cf6 | 2348 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 2349 | return ret; |
de151cf6 JB |
2350 | } |
2351 | ||
ff72145b DA |
2352 | /** |
2353 | * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing | |
2354 | * @dev: DRM device | |
2355 | * @data: GTT mapping ioctl data | |
2356 | * @file: GEM object info | |
2357 | * | |
2358 | * Simply returns the fake offset to userspace so it can mmap it. | |
2359 | * The mmap call will end up in drm_gem_mmap(), which will set things | |
2360 | * up so we can get faults in the handler above. | |
2361 | * | |
2362 | * The fault handler will take care of binding the object into the GTT | |
2363 | * (since it may have been evicted to make room for something), allocating | |
2364 | * a fence register, and mapping the appropriate aperture address into | |
2365 | * userspace. | |
2366 | */ | |
2367 | int | |
2368 | i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data, | |
2369 | struct drm_file *file) | |
2370 | { | |
2371 | struct drm_i915_gem_mmap_gtt *args = data; | |
2372 | ||
da6b51d0 | 2373 | return i915_gem_mmap_gtt(file, dev, args->handle, &args->offset); |
ff72145b DA |
2374 | } |
2375 | ||
225067ee DV |
2376 | /* Immediately discard the backing storage */ |
2377 | static void | |
2378 | i915_gem_object_truncate(struct drm_i915_gem_object *obj) | |
e5281ccd | 2379 | { |
4d6294bf | 2380 | i915_gem_object_free_mmap_offset(obj); |
1286ff73 | 2381 | |
4d6294bf CW |
2382 | if (obj->base.filp == NULL) |
2383 | return; | |
e5281ccd | 2384 | |
225067ee DV |
2385 | /* Our goal here is to return as much of the memory as |
2386 | * is possible back to the system as we are called from OOM. | |
2387 | * To do this we must instruct the shmfs to drop all of its | |
2388 | * backing pages, *now*. | |
2389 | */ | |
5537252b | 2390 | shmem_truncate_range(file_inode(obj->base.filp), 0, (loff_t)-1); |
225067ee DV |
2391 | obj->madv = __I915_MADV_PURGED; |
2392 | } | |
e5281ccd | 2393 | |
5537252b CW |
2394 | /* Try to discard unwanted pages */ |
2395 | static void | |
2396 | i915_gem_object_invalidate(struct drm_i915_gem_object *obj) | |
225067ee | 2397 | { |
5537252b CW |
2398 | struct address_space *mapping; |
2399 | ||
2400 | switch (obj->madv) { | |
2401 | case I915_MADV_DONTNEED: | |
2402 | i915_gem_object_truncate(obj); | |
2403 | case __I915_MADV_PURGED: | |
2404 | return; | |
2405 | } | |
2406 | ||
2407 | if (obj->base.filp == NULL) | |
2408 | return; | |
2409 | ||
2410 | mapping = file_inode(obj->base.filp)->i_mapping, | |
2411 | invalidate_mapping_pages(mapping, 0, (loff_t)-1); | |
e5281ccd CW |
2412 | } |
2413 | ||
5cdf5881 | 2414 | static void |
05394f39 | 2415 | i915_gem_object_put_pages_gtt(struct drm_i915_gem_object *obj) |
673a394b | 2416 | { |
85d1225e DG |
2417 | struct sgt_iter sgt_iter; |
2418 | struct page *page; | |
90797e6d | 2419 | int ret; |
1286ff73 | 2420 | |
05394f39 | 2421 | BUG_ON(obj->madv == __I915_MADV_PURGED); |
673a394b | 2422 | |
6c085a72 | 2423 | ret = i915_gem_object_set_to_cpu_domain(obj, true); |
f4457ae7 | 2424 | if (WARN_ON(ret)) { |
6c085a72 CW |
2425 | /* In the event of a disaster, abandon all caches and |
2426 | * hope for the best. | |
2427 | */ | |
2c22569b | 2428 | i915_gem_clflush_object(obj, true); |
6c085a72 CW |
2429 | obj->base.read_domains = obj->base.write_domain = I915_GEM_DOMAIN_CPU; |
2430 | } | |
2431 | ||
e2273302 ID |
2432 | i915_gem_gtt_finish_object(obj); |
2433 | ||
6dacfd2f | 2434 | if (i915_gem_object_needs_bit17_swizzle(obj)) |
280b713b EA |
2435 | i915_gem_object_save_bit_17_swizzle(obj); |
2436 | ||
05394f39 CW |
2437 | if (obj->madv == I915_MADV_DONTNEED) |
2438 | obj->dirty = 0; | |
3ef94daa | 2439 | |
85d1225e | 2440 | for_each_sgt_page(page, sgt_iter, obj->pages) { |
05394f39 | 2441 | if (obj->dirty) |
9da3da66 | 2442 | set_page_dirty(page); |
3ef94daa | 2443 | |
05394f39 | 2444 | if (obj->madv == I915_MADV_WILLNEED) |
9da3da66 | 2445 | mark_page_accessed(page); |
3ef94daa | 2446 | |
09cbfeaf | 2447 | put_page(page); |
3ef94daa | 2448 | } |
05394f39 | 2449 | obj->dirty = 0; |
673a394b | 2450 | |
9da3da66 CW |
2451 | sg_free_table(obj->pages); |
2452 | kfree(obj->pages); | |
37e680a1 | 2453 | } |
6c085a72 | 2454 | |
dd624afd | 2455 | int |
37e680a1 CW |
2456 | i915_gem_object_put_pages(struct drm_i915_gem_object *obj) |
2457 | { | |
2458 | const struct drm_i915_gem_object_ops *ops = obj->ops; | |
2459 | ||
2f745ad3 | 2460 | if (obj->pages == NULL) |
37e680a1 CW |
2461 | return 0; |
2462 | ||
a5570178 CW |
2463 | if (obj->pages_pin_count) |
2464 | return -EBUSY; | |
2465 | ||
9843877d | 2466 | BUG_ON(i915_gem_obj_bound_any(obj)); |
3e123027 | 2467 | |
a2165e31 CW |
2468 | /* ->put_pages might need to allocate memory for the bit17 swizzle |
2469 | * array, hence protect them from being reaped by removing them from gtt | |
2470 | * lists early. */ | |
35c20a60 | 2471 | list_del(&obj->global_list); |
a2165e31 | 2472 | |
0a798eb9 | 2473 | if (obj->mapping) { |
fb8621d3 CW |
2474 | if (is_vmalloc_addr(obj->mapping)) |
2475 | vunmap(obj->mapping); | |
2476 | else | |
2477 | kunmap(kmap_to_page(obj->mapping)); | |
0a798eb9 CW |
2478 | obj->mapping = NULL; |
2479 | } | |
2480 | ||
37e680a1 | 2481 | ops->put_pages(obj); |
05394f39 | 2482 | obj->pages = NULL; |
37e680a1 | 2483 | |
5537252b | 2484 | i915_gem_object_invalidate(obj); |
6c085a72 CW |
2485 | |
2486 | return 0; | |
2487 | } | |
2488 | ||
37e680a1 | 2489 | static int |
6c085a72 | 2490 | i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj) |
e5281ccd | 2491 | { |
fac5e23e | 2492 | struct drm_i915_private *dev_priv = to_i915(obj->base.dev); |
e5281ccd CW |
2493 | int page_count, i; |
2494 | struct address_space *mapping; | |
9da3da66 CW |
2495 | struct sg_table *st; |
2496 | struct scatterlist *sg; | |
85d1225e | 2497 | struct sgt_iter sgt_iter; |
e5281ccd | 2498 | struct page *page; |
90797e6d | 2499 | unsigned long last_pfn = 0; /* suppress gcc warning */ |
e2273302 | 2500 | int ret; |
6c085a72 | 2501 | gfp_t gfp; |
e5281ccd | 2502 | |
6c085a72 CW |
2503 | /* Assert that the object is not currently in any GPU domain. As it |
2504 | * wasn't in the GTT, there shouldn't be any way it could have been in | |
2505 | * a GPU cache | |
2506 | */ | |
2507 | BUG_ON(obj->base.read_domains & I915_GEM_GPU_DOMAINS); | |
2508 | BUG_ON(obj->base.write_domain & I915_GEM_GPU_DOMAINS); | |
2509 | ||
9da3da66 CW |
2510 | st = kmalloc(sizeof(*st), GFP_KERNEL); |
2511 | if (st == NULL) | |
2512 | return -ENOMEM; | |
2513 | ||
05394f39 | 2514 | page_count = obj->base.size / PAGE_SIZE; |
9da3da66 | 2515 | if (sg_alloc_table(st, page_count, GFP_KERNEL)) { |
9da3da66 | 2516 | kfree(st); |
e5281ccd | 2517 | return -ENOMEM; |
9da3da66 | 2518 | } |
e5281ccd | 2519 | |
9da3da66 CW |
2520 | /* Get the list of pages out of our struct file. They'll be pinned |
2521 | * at this point until we release them. | |
2522 | * | |
2523 | * Fail silently without starting the shrinker | |
2524 | */ | |
496ad9aa | 2525 | mapping = file_inode(obj->base.filp)->i_mapping; |
c62d2555 | 2526 | gfp = mapping_gfp_constraint(mapping, ~(__GFP_IO | __GFP_RECLAIM)); |
d0164adc | 2527 | gfp |= __GFP_NORETRY | __GFP_NOWARN; |
90797e6d ID |
2528 | sg = st->sgl; |
2529 | st->nents = 0; | |
2530 | for (i = 0; i < page_count; i++) { | |
6c085a72 CW |
2531 | page = shmem_read_mapping_page_gfp(mapping, i, gfp); |
2532 | if (IS_ERR(page)) { | |
21ab4e74 CW |
2533 | i915_gem_shrink(dev_priv, |
2534 | page_count, | |
2535 | I915_SHRINK_BOUND | | |
2536 | I915_SHRINK_UNBOUND | | |
2537 | I915_SHRINK_PURGEABLE); | |
6c085a72 CW |
2538 | page = shmem_read_mapping_page_gfp(mapping, i, gfp); |
2539 | } | |
2540 | if (IS_ERR(page)) { | |
2541 | /* We've tried hard to allocate the memory by reaping | |
2542 | * our own buffer, now let the real VM do its job and | |
2543 | * go down in flames if truly OOM. | |
2544 | */ | |
6c085a72 | 2545 | i915_gem_shrink_all(dev_priv); |
f461d1be | 2546 | page = shmem_read_mapping_page(mapping, i); |
e2273302 ID |
2547 | if (IS_ERR(page)) { |
2548 | ret = PTR_ERR(page); | |
6c085a72 | 2549 | goto err_pages; |
e2273302 | 2550 | } |
6c085a72 | 2551 | } |
426729dc KRW |
2552 | #ifdef CONFIG_SWIOTLB |
2553 | if (swiotlb_nr_tbl()) { | |
2554 | st->nents++; | |
2555 | sg_set_page(sg, page, PAGE_SIZE, 0); | |
2556 | sg = sg_next(sg); | |
2557 | continue; | |
2558 | } | |
2559 | #endif | |
90797e6d ID |
2560 | if (!i || page_to_pfn(page) != last_pfn + 1) { |
2561 | if (i) | |
2562 | sg = sg_next(sg); | |
2563 | st->nents++; | |
2564 | sg_set_page(sg, page, PAGE_SIZE, 0); | |
2565 | } else { | |
2566 | sg->length += PAGE_SIZE; | |
2567 | } | |
2568 | last_pfn = page_to_pfn(page); | |
3bbbe706 DV |
2569 | |
2570 | /* Check that the i965g/gm workaround works. */ | |
2571 | WARN_ON((gfp & __GFP_DMA32) && (last_pfn >= 0x00100000UL)); | |
e5281ccd | 2572 | } |
426729dc KRW |
2573 | #ifdef CONFIG_SWIOTLB |
2574 | if (!swiotlb_nr_tbl()) | |
2575 | #endif | |
2576 | sg_mark_end(sg); | |
74ce6b6c CW |
2577 | obj->pages = st; |
2578 | ||
e2273302 ID |
2579 | ret = i915_gem_gtt_prepare_object(obj); |
2580 | if (ret) | |
2581 | goto err_pages; | |
2582 | ||
6dacfd2f | 2583 | if (i915_gem_object_needs_bit17_swizzle(obj)) |
e5281ccd CW |
2584 | i915_gem_object_do_bit_17_swizzle(obj); |
2585 | ||
656bfa3a DV |
2586 | if (obj->tiling_mode != I915_TILING_NONE && |
2587 | dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES) | |
2588 | i915_gem_object_pin_pages(obj); | |
2589 | ||
e5281ccd CW |
2590 | return 0; |
2591 | ||
2592 | err_pages: | |
90797e6d | 2593 | sg_mark_end(sg); |
85d1225e DG |
2594 | for_each_sgt_page(page, sgt_iter, st) |
2595 | put_page(page); | |
9da3da66 CW |
2596 | sg_free_table(st); |
2597 | kfree(st); | |
0820baf3 CW |
2598 | |
2599 | /* shmemfs first checks if there is enough memory to allocate the page | |
2600 | * and reports ENOSPC should there be insufficient, along with the usual | |
2601 | * ENOMEM for a genuine allocation failure. | |
2602 | * | |
2603 | * We use ENOSPC in our driver to mean that we have run out of aperture | |
2604 | * space and so want to translate the error from shmemfs back to our | |
2605 | * usual understanding of ENOMEM. | |
2606 | */ | |
e2273302 ID |
2607 | if (ret == -ENOSPC) |
2608 | ret = -ENOMEM; | |
2609 | ||
2610 | return ret; | |
673a394b EA |
2611 | } |
2612 | ||
37e680a1 CW |
2613 | /* Ensure that the associated pages are gathered from the backing storage |
2614 | * and pinned into our object. i915_gem_object_get_pages() may be called | |
2615 | * multiple times before they are released by a single call to | |
2616 | * i915_gem_object_put_pages() - once the pages are no longer referenced | |
2617 | * either as a result of memory pressure (reaping pages under the shrinker) | |
2618 | * or as the object is itself released. | |
2619 | */ | |
2620 | int | |
2621 | i915_gem_object_get_pages(struct drm_i915_gem_object *obj) | |
2622 | { | |
fac5e23e | 2623 | struct drm_i915_private *dev_priv = to_i915(obj->base.dev); |
37e680a1 CW |
2624 | const struct drm_i915_gem_object_ops *ops = obj->ops; |
2625 | int ret; | |
2626 | ||
2f745ad3 | 2627 | if (obj->pages) |
37e680a1 CW |
2628 | return 0; |
2629 | ||
43e28f09 | 2630 | if (obj->madv != I915_MADV_WILLNEED) { |
bd9b6a4e | 2631 | DRM_DEBUG("Attempting to obtain a purgeable object\n"); |
8c99e57d | 2632 | return -EFAULT; |
43e28f09 CW |
2633 | } |
2634 | ||
a5570178 CW |
2635 | BUG_ON(obj->pages_pin_count); |
2636 | ||
37e680a1 CW |
2637 | ret = ops->get_pages(obj); |
2638 | if (ret) | |
2639 | return ret; | |
2640 | ||
35c20a60 | 2641 | list_add_tail(&obj->global_list, &dev_priv->mm.unbound_list); |
ee286370 CW |
2642 | |
2643 | obj->get_page.sg = obj->pages->sgl; | |
2644 | obj->get_page.last = 0; | |
2645 | ||
37e680a1 | 2646 | return 0; |
673a394b EA |
2647 | } |
2648 | ||
dd6034c6 DG |
2649 | /* The 'mapping' part of i915_gem_object_pin_map() below */ |
2650 | static void *i915_gem_object_map(const struct drm_i915_gem_object *obj) | |
2651 | { | |
2652 | unsigned long n_pages = obj->base.size >> PAGE_SHIFT; | |
2653 | struct sg_table *sgt = obj->pages; | |
85d1225e DG |
2654 | struct sgt_iter sgt_iter; |
2655 | struct page *page; | |
b338fa47 DG |
2656 | struct page *stack_pages[32]; |
2657 | struct page **pages = stack_pages; | |
dd6034c6 DG |
2658 | unsigned long i = 0; |
2659 | void *addr; | |
2660 | ||
2661 | /* A single page can always be kmapped */ | |
2662 | if (n_pages == 1) | |
2663 | return kmap(sg_page(sgt->sgl)); | |
2664 | ||
b338fa47 DG |
2665 | if (n_pages > ARRAY_SIZE(stack_pages)) { |
2666 | /* Too big for stack -- allocate temporary array instead */ | |
2667 | pages = drm_malloc_gfp(n_pages, sizeof(*pages), GFP_TEMPORARY); | |
2668 | if (!pages) | |
2669 | return NULL; | |
2670 | } | |
dd6034c6 | 2671 | |
85d1225e DG |
2672 | for_each_sgt_page(page, sgt_iter, sgt) |
2673 | pages[i++] = page; | |
dd6034c6 DG |
2674 | |
2675 | /* Check that we have the expected number of pages */ | |
2676 | GEM_BUG_ON(i != n_pages); | |
2677 | ||
2678 | addr = vmap(pages, n_pages, 0, PAGE_KERNEL); | |
2679 | ||
b338fa47 DG |
2680 | if (pages != stack_pages) |
2681 | drm_free_large(pages); | |
dd6034c6 DG |
2682 | |
2683 | return addr; | |
2684 | } | |
2685 | ||
2686 | /* get, pin, and map the pages of the object into kernel space */ | |
0a798eb9 CW |
2687 | void *i915_gem_object_pin_map(struct drm_i915_gem_object *obj) |
2688 | { | |
2689 | int ret; | |
2690 | ||
2691 | lockdep_assert_held(&obj->base.dev->struct_mutex); | |
2692 | ||
2693 | ret = i915_gem_object_get_pages(obj); | |
2694 | if (ret) | |
2695 | return ERR_PTR(ret); | |
2696 | ||
2697 | i915_gem_object_pin_pages(obj); | |
2698 | ||
dd6034c6 DG |
2699 | if (!obj->mapping) { |
2700 | obj->mapping = i915_gem_object_map(obj); | |
2701 | if (!obj->mapping) { | |
0a798eb9 CW |
2702 | i915_gem_object_unpin_pages(obj); |
2703 | return ERR_PTR(-ENOMEM); | |
2704 | } | |
2705 | } | |
2706 | ||
2707 | return obj->mapping; | |
2708 | } | |
2709 | ||
b4716185 | 2710 | void i915_vma_move_to_active(struct i915_vma *vma, |
b2af0376 | 2711 | struct drm_i915_gem_request *req) |
673a394b | 2712 | { |
b4716185 | 2713 | struct drm_i915_gem_object *obj = vma->obj; |
e2f80391 | 2714 | struct intel_engine_cs *engine; |
b2af0376 | 2715 | |
666796da | 2716 | engine = i915_gem_request_get_engine(req); |
673a394b EA |
2717 | |
2718 | /* Add a reference if we're newly entering the active list. */ | |
b4716185 | 2719 | if (obj->active == 0) |
05394f39 | 2720 | drm_gem_object_reference(&obj->base); |
666796da | 2721 | obj->active |= intel_engine_flag(engine); |
e35a41de | 2722 | |
117897f4 | 2723 | list_move_tail(&obj->engine_list[engine->id], &engine->active_list); |
e2f80391 | 2724 | i915_gem_request_assign(&obj->last_read_req[engine->id], req); |
caea7476 | 2725 | |
1c7f4bca | 2726 | list_move_tail(&vma->vm_link, &vma->vm->active_list); |
caea7476 CW |
2727 | } |
2728 | ||
b4716185 CW |
2729 | static void |
2730 | i915_gem_object_retire__write(struct drm_i915_gem_object *obj) | |
e2d05a8b | 2731 | { |
d501b1d2 CW |
2732 | GEM_BUG_ON(obj->last_write_req == NULL); |
2733 | GEM_BUG_ON(!(obj->active & intel_engine_flag(obj->last_write_req->engine))); | |
b4716185 CW |
2734 | |
2735 | i915_gem_request_assign(&obj->last_write_req, NULL); | |
de152b62 | 2736 | intel_fb_obj_flush(obj, true, ORIGIN_CS); |
e2d05a8b BW |
2737 | } |
2738 | ||
caea7476 | 2739 | static void |
b4716185 | 2740 | i915_gem_object_retire__read(struct drm_i915_gem_object *obj, int ring) |
ce44b0ea | 2741 | { |
feb822cf | 2742 | struct i915_vma *vma; |
ce44b0ea | 2743 | |
d501b1d2 CW |
2744 | GEM_BUG_ON(obj->last_read_req[ring] == NULL); |
2745 | GEM_BUG_ON(!(obj->active & (1 << ring))); | |
b4716185 | 2746 | |
117897f4 | 2747 | list_del_init(&obj->engine_list[ring]); |
b4716185 CW |
2748 | i915_gem_request_assign(&obj->last_read_req[ring], NULL); |
2749 | ||
4a570db5 | 2750 | if (obj->last_write_req && obj->last_write_req->engine->id == ring) |
b4716185 CW |
2751 | i915_gem_object_retire__write(obj); |
2752 | ||
2753 | obj->active &= ~(1 << ring); | |
2754 | if (obj->active) | |
2755 | return; | |
caea7476 | 2756 | |
6c246959 CW |
2757 | /* Bump our place on the bound list to keep it roughly in LRU order |
2758 | * so that we don't steal from recently used but inactive objects | |
2759 | * (unless we are forced to ofc!) | |
2760 | */ | |
2761 | list_move_tail(&obj->global_list, | |
2762 | &to_i915(obj->base.dev)->mm.bound_list); | |
2763 | ||
1c7f4bca CW |
2764 | list_for_each_entry(vma, &obj->vma_list, obj_link) { |
2765 | if (!list_empty(&vma->vm_link)) | |
2766 | list_move_tail(&vma->vm_link, &vma->vm->inactive_list); | |
feb822cf | 2767 | } |
caea7476 | 2768 | |
97b2a6a1 | 2769 | i915_gem_request_assign(&obj->last_fenced_req, NULL); |
caea7476 | 2770 | drm_gem_object_unreference(&obj->base); |
c8725f3d CW |
2771 | } |
2772 | ||
9d773091 | 2773 | static int |
c033666a | 2774 | i915_gem_init_seqno(struct drm_i915_private *dev_priv, u32 seqno) |
53d227f2 | 2775 | { |
e2f80391 | 2776 | struct intel_engine_cs *engine; |
29dcb570 | 2777 | int ret; |
53d227f2 | 2778 | |
107f27a5 | 2779 | /* Carefully retire all requests without writing to the rings */ |
b4ac5afc | 2780 | for_each_engine(engine, dev_priv) { |
666796da | 2781 | ret = intel_engine_idle(engine); |
107f27a5 CW |
2782 | if (ret) |
2783 | return ret; | |
9d773091 | 2784 | } |
c033666a | 2785 | i915_gem_retire_requests(dev_priv); |
107f27a5 | 2786 | |
688e6c72 CW |
2787 | /* If the seqno wraps around, we need to clear the breadcrumb rbtree */ |
2788 | if (!i915_seqno_passed(seqno, dev_priv->next_seqno)) { | |
c81d4613 CW |
2789 | while (intel_kick_waiters(dev_priv) || |
2790 | intel_kick_signalers(dev_priv)) | |
688e6c72 CW |
2791 | yield(); |
2792 | } | |
2793 | ||
107f27a5 | 2794 | /* Finally reset hw state */ |
29dcb570 | 2795 | for_each_engine(engine, dev_priv) |
e2f80391 | 2796 | intel_ring_init_seqno(engine, seqno); |
498d2ac1 | 2797 | |
9d773091 | 2798 | return 0; |
53d227f2 DV |
2799 | } |
2800 | ||
fca26bb4 MK |
2801 | int i915_gem_set_seqno(struct drm_device *dev, u32 seqno) |
2802 | { | |
fac5e23e | 2803 | struct drm_i915_private *dev_priv = to_i915(dev); |
fca26bb4 MK |
2804 | int ret; |
2805 | ||
2806 | if (seqno == 0) | |
2807 | return -EINVAL; | |
2808 | ||
2809 | /* HWS page needs to be set less than what we | |
2810 | * will inject to ring | |
2811 | */ | |
c033666a | 2812 | ret = i915_gem_init_seqno(dev_priv, seqno - 1); |
fca26bb4 MK |
2813 | if (ret) |
2814 | return ret; | |
2815 | ||
2816 | /* Carefully set the last_seqno value so that wrap | |
2817 | * detection still works | |
2818 | */ | |
2819 | dev_priv->next_seqno = seqno; | |
2820 | dev_priv->last_seqno = seqno - 1; | |
2821 | if (dev_priv->last_seqno == 0) | |
2822 | dev_priv->last_seqno--; | |
2823 | ||
2824 | return 0; | |
2825 | } | |
2826 | ||
9d773091 | 2827 | int |
c033666a | 2828 | i915_gem_get_seqno(struct drm_i915_private *dev_priv, u32 *seqno) |
53d227f2 | 2829 | { |
9d773091 CW |
2830 | /* reserve 0 for non-seqno */ |
2831 | if (dev_priv->next_seqno == 0) { | |
c033666a | 2832 | int ret = i915_gem_init_seqno(dev_priv, 0); |
9d773091 CW |
2833 | if (ret) |
2834 | return ret; | |
53d227f2 | 2835 | |
9d773091 CW |
2836 | dev_priv->next_seqno = 1; |
2837 | } | |
53d227f2 | 2838 | |
f72b3435 | 2839 | *seqno = dev_priv->last_seqno = dev_priv->next_seqno++; |
9d773091 | 2840 | return 0; |
53d227f2 DV |
2841 | } |
2842 | ||
67d97da3 CW |
2843 | static void i915_gem_mark_busy(const struct intel_engine_cs *engine) |
2844 | { | |
2845 | struct drm_i915_private *dev_priv = engine->i915; | |
2846 | ||
2847 | dev_priv->gt.active_engines |= intel_engine_flag(engine); | |
2848 | if (dev_priv->gt.awake) | |
2849 | return; | |
2850 | ||
2851 | intel_runtime_pm_get_noresume(dev_priv); | |
2852 | dev_priv->gt.awake = true; | |
2853 | ||
2854 | i915_update_gfx_val(dev_priv); | |
2855 | if (INTEL_GEN(dev_priv) >= 6) | |
2856 | gen6_rps_busy(dev_priv); | |
2857 | ||
2858 | queue_delayed_work(dev_priv->wq, | |
2859 | &dev_priv->gt.retire_work, | |
2860 | round_jiffies_up_relative(HZ)); | |
2861 | } | |
2862 | ||
bf7dc5b7 JH |
2863 | /* |
2864 | * NB: This function is not allowed to fail. Doing so would mean the the | |
2865 | * request is not being tracked for completion but the work itself is | |
2866 | * going to happen on the hardware. This would be a Bad Thing(tm). | |
2867 | */ | |
75289874 | 2868 | void __i915_add_request(struct drm_i915_gem_request *request, |
5b4a60c2 JH |
2869 | struct drm_i915_gem_object *obj, |
2870 | bool flush_caches) | |
673a394b | 2871 | { |
e2f80391 | 2872 | struct intel_engine_cs *engine; |
48e29f55 | 2873 | struct intel_ringbuffer *ringbuf; |
6d3d8274 | 2874 | u32 request_start; |
0251a963 | 2875 | u32 reserved_tail; |
3cce469c CW |
2876 | int ret; |
2877 | ||
48e29f55 | 2878 | if (WARN_ON(request == NULL)) |
bf7dc5b7 | 2879 | return; |
48e29f55 | 2880 | |
4a570db5 | 2881 | engine = request->engine; |
75289874 JH |
2882 | ringbuf = request->ringbuf; |
2883 | ||
29b1b415 JH |
2884 | /* |
2885 | * To ensure that this call will not fail, space for its emissions | |
2886 | * should already have been reserved in the ring buffer. Let the ring | |
2887 | * know that it is time to use that space up. | |
2888 | */ | |
48e29f55 | 2889 | request_start = intel_ring_get_tail(ringbuf); |
0251a963 CW |
2890 | reserved_tail = request->reserved_space; |
2891 | request->reserved_space = 0; | |
2892 | ||
cc889e0f DV |
2893 | /* |
2894 | * Emit any outstanding flushes - execbuf can fail to emit the flush | |
2895 | * after having emitted the batchbuffer command. Hence we need to fix | |
2896 | * things up similar to emitting the lazy request. The difference here | |
2897 | * is that the flush _must_ happen before the next request, no matter | |
2898 | * what. | |
2899 | */ | |
5b4a60c2 JH |
2900 | if (flush_caches) { |
2901 | if (i915.enable_execlists) | |
4866d729 | 2902 | ret = logical_ring_flush_all_caches(request); |
5b4a60c2 | 2903 | else |
4866d729 | 2904 | ret = intel_ring_flush_all_caches(request); |
5b4a60c2 JH |
2905 | /* Not allowed to fail! */ |
2906 | WARN(ret, "*_ring_flush_all_caches failed: %d!\n", ret); | |
2907 | } | |
cc889e0f | 2908 | |
7c90b7de CW |
2909 | trace_i915_gem_request_add(request); |
2910 | ||
2911 | request->head = request_start; | |
2912 | ||
2913 | /* Whilst this request exists, batch_obj will be on the | |
2914 | * active_list, and so will hold the active reference. Only when this | |
2915 | * request is retired will the the batch_obj be moved onto the | |
2916 | * inactive_list and lose its active reference. Hence we do not need | |
2917 | * to explicitly hold another reference here. | |
2918 | */ | |
2919 | request->batch_obj = obj; | |
2920 | ||
2921 | /* Seal the request and mark it as pending execution. Note that | |
2922 | * we may inspect this state, without holding any locks, during | |
2923 | * hangcheck. Hence we apply the barrier to ensure that we do not | |
2924 | * see a more recent value in the hws than we are tracking. | |
2925 | */ | |
2926 | request->emitted_jiffies = jiffies; | |
2927 | request->previous_seqno = engine->last_submitted_seqno; | |
2928 | smp_store_mb(engine->last_submitted_seqno, request->seqno); | |
2929 | list_add_tail(&request->list, &engine->request_list); | |
2930 | ||
a71d8d94 CW |
2931 | /* Record the position of the start of the request so that |
2932 | * should we detect the updated seqno part-way through the | |
2933 | * GPU processing the request, we never over-estimate the | |
2934 | * position of the head. | |
2935 | */ | |
6d3d8274 | 2936 | request->postfix = intel_ring_get_tail(ringbuf); |
a71d8d94 | 2937 | |
bf7dc5b7 | 2938 | if (i915.enable_execlists) |
e2f80391 | 2939 | ret = engine->emit_request(request); |
bf7dc5b7 | 2940 | else { |
e2f80391 | 2941 | ret = engine->add_request(request); |
53292cdb MT |
2942 | |
2943 | request->tail = intel_ring_get_tail(ringbuf); | |
48e29f55 | 2944 | } |
bf7dc5b7 JH |
2945 | /* Not allowed to fail! */ |
2946 | WARN(ret, "emit|add_request failed: %d!\n", ret); | |
29b1b415 | 2947 | /* Sanity check that the reserved size was large enough. */ |
0251a963 CW |
2948 | ret = intel_ring_get_tail(ringbuf) - request_start; |
2949 | if (ret < 0) | |
2950 | ret += ringbuf->size; | |
2951 | WARN_ONCE(ret > reserved_tail, | |
2952 | "Not enough space reserved (%d bytes) " | |
2953 | "for adding the request (%d bytes)\n", | |
2954 | reserved_tail, ret); | |
67d97da3 CW |
2955 | |
2956 | i915_gem_mark_busy(engine); | |
673a394b EA |
2957 | } |
2958 | ||
7b4d3a16 | 2959 | static bool i915_context_is_banned(const struct i915_gem_context *ctx) |
be62acb4 | 2960 | { |
44e2c070 | 2961 | unsigned long elapsed; |
be62acb4 | 2962 | |
44e2c070 | 2963 | if (ctx->hang_stats.banned) |
be62acb4 MK |
2964 | return true; |
2965 | ||
7b4d3a16 | 2966 | elapsed = get_seconds() - ctx->hang_stats.guilty_ts; |
676fa572 CW |
2967 | if (ctx->hang_stats.ban_period_seconds && |
2968 | elapsed <= ctx->hang_stats.ban_period_seconds) { | |
7b4d3a16 CW |
2969 | DRM_DEBUG("context hanging too fast, banning!\n"); |
2970 | return true; | |
be62acb4 MK |
2971 | } |
2972 | ||
2973 | return false; | |
2974 | } | |
2975 | ||
7b4d3a16 | 2976 | static void i915_set_reset_status(struct i915_gem_context *ctx, |
b6b0fac0 | 2977 | const bool guilty) |
aa60c664 | 2978 | { |
7b4d3a16 | 2979 | struct i915_ctx_hang_stats *hs = &ctx->hang_stats; |
44e2c070 MK |
2980 | |
2981 | if (guilty) { | |
7b4d3a16 | 2982 | hs->banned = i915_context_is_banned(ctx); |
44e2c070 MK |
2983 | hs->batch_active++; |
2984 | hs->guilty_ts = get_seconds(); | |
2985 | } else { | |
2986 | hs->batch_pending++; | |
aa60c664 MK |
2987 | } |
2988 | } | |
2989 | ||
abfe262a JH |
2990 | void i915_gem_request_free(struct kref *req_ref) |
2991 | { | |
2992 | struct drm_i915_gem_request *req = container_of(req_ref, | |
2993 | typeof(*req), ref); | |
efab6d8d | 2994 | kmem_cache_free(req->i915->requests, req); |
0e50e96b MK |
2995 | } |
2996 | ||
26827088 | 2997 | static inline int |
0bc40be8 | 2998 | __i915_gem_request_alloc(struct intel_engine_cs *engine, |
e2efd130 | 2999 | struct i915_gem_context *ctx, |
26827088 | 3000 | struct drm_i915_gem_request **req_out) |
6689cb2b | 3001 | { |
c033666a | 3002 | struct drm_i915_private *dev_priv = engine->i915; |
299259a3 | 3003 | unsigned reset_counter = i915_reset_counter(&dev_priv->gpu_error); |
eed29a5b | 3004 | struct drm_i915_gem_request *req; |
6689cb2b | 3005 | int ret; |
6689cb2b | 3006 | |
217e46b5 JH |
3007 | if (!req_out) |
3008 | return -EINVAL; | |
3009 | ||
bccca494 | 3010 | *req_out = NULL; |
6689cb2b | 3011 | |
f4457ae7 CW |
3012 | /* ABI: Before userspace accesses the GPU (e.g. execbuffer), report |
3013 | * EIO if the GPU is already wedged, or EAGAIN to drop the struct_mutex | |
3014 | * and restart. | |
3015 | */ | |
3016 | ret = i915_gem_check_wedge(reset_counter, dev_priv->mm.interruptible); | |
299259a3 CW |
3017 | if (ret) |
3018 | return ret; | |
3019 | ||
eed29a5b DV |
3020 | req = kmem_cache_zalloc(dev_priv->requests, GFP_KERNEL); |
3021 | if (req == NULL) | |
6689cb2b JH |
3022 | return -ENOMEM; |
3023 | ||
c033666a | 3024 | ret = i915_gem_get_seqno(engine->i915, &req->seqno); |
9a0c1e27 CW |
3025 | if (ret) |
3026 | goto err; | |
6689cb2b | 3027 | |
40e895ce JH |
3028 | kref_init(&req->ref); |
3029 | req->i915 = dev_priv; | |
4a570db5 | 3030 | req->engine = engine; |
40e895ce JH |
3031 | req->ctx = ctx; |
3032 | i915_gem_context_reference(req->ctx); | |
6689cb2b | 3033 | |
29b1b415 JH |
3034 | /* |
3035 | * Reserve space in the ring buffer for all the commands required to | |
3036 | * eventually emit this request. This is to guarantee that the | |
3037 | * i915_add_request() call can't fail. Note that the reserve may need | |
3038 | * to be redone if the request is not actually submitted straight | |
3039 | * away, e.g. because a GPU scheduler has deferred it. | |
29b1b415 | 3040 | */ |
0251a963 | 3041 | req->reserved_space = MIN_SPACE_FOR_ADD_REQUEST; |
bfa01200 CW |
3042 | |
3043 | if (i915.enable_execlists) | |
3044 | ret = intel_logical_ring_alloc_request_extras(req); | |
3045 | else | |
3046 | ret = intel_ring_alloc_request_extras(req); | |
3047 | if (ret) | |
3048 | goto err_ctx; | |
29b1b415 | 3049 | |
bccca494 | 3050 | *req_out = req; |
6689cb2b | 3051 | return 0; |
9a0c1e27 | 3052 | |
bfa01200 CW |
3053 | err_ctx: |
3054 | i915_gem_context_unreference(ctx); | |
9a0c1e27 CW |
3055 | err: |
3056 | kmem_cache_free(dev_priv->requests, req); | |
3057 | return ret; | |
0e50e96b MK |
3058 | } |
3059 | ||
26827088 DG |
3060 | /** |
3061 | * i915_gem_request_alloc - allocate a request structure | |
3062 | * | |
3063 | * @engine: engine that we wish to issue the request on. | |
3064 | * @ctx: context that the request will be associated with. | |
3065 | * This can be NULL if the request is not directly related to | |
3066 | * any specific user context, in which case this function will | |
3067 | * choose an appropriate context to use. | |
3068 | * | |
3069 | * Returns a pointer to the allocated request if successful, | |
3070 | * or an error code if not. | |
3071 | */ | |
3072 | struct drm_i915_gem_request * | |
3073 | i915_gem_request_alloc(struct intel_engine_cs *engine, | |
e2efd130 | 3074 | struct i915_gem_context *ctx) |
26827088 DG |
3075 | { |
3076 | struct drm_i915_gem_request *req; | |
3077 | int err; | |
3078 | ||
3079 | if (ctx == NULL) | |
c033666a | 3080 | ctx = engine->i915->kernel_context; |
26827088 DG |
3081 | err = __i915_gem_request_alloc(engine, ctx, &req); |
3082 | return err ? ERR_PTR(err) : req; | |
3083 | } | |
3084 | ||
8d9fc7fd | 3085 | struct drm_i915_gem_request * |
0bc40be8 | 3086 | i915_gem_find_active_request(struct intel_engine_cs *engine) |
9375e446 | 3087 | { |
4db080f9 CW |
3088 | struct drm_i915_gem_request *request; |
3089 | ||
f69a02c9 CW |
3090 | /* We are called by the error capture and reset at a random |
3091 | * point in time. In particular, note that neither is crucially | |
3092 | * ordered with an interrupt. After a hang, the GPU is dead and we | |
3093 | * assume that no more writes can happen (we waited long enough for | |
3094 | * all writes that were in transaction to be flushed) - adding an | |
3095 | * extra delay for a recent interrupt is pointless. Hence, we do | |
3096 | * not need an engine->irq_seqno_barrier() before the seqno reads. | |
3097 | */ | |
0bc40be8 | 3098 | list_for_each_entry(request, &engine->request_list, list) { |
f69a02c9 | 3099 | if (i915_gem_request_completed(request)) |
4db080f9 | 3100 | continue; |
aa60c664 | 3101 | |
b6b0fac0 | 3102 | return request; |
4db080f9 | 3103 | } |
b6b0fac0 MK |
3104 | |
3105 | return NULL; | |
3106 | } | |
3107 | ||
7b4d3a16 | 3108 | static void i915_gem_reset_engine_status(struct intel_engine_cs *engine) |
b6b0fac0 MK |
3109 | { |
3110 | struct drm_i915_gem_request *request; | |
3111 | bool ring_hung; | |
3112 | ||
0bc40be8 | 3113 | request = i915_gem_find_active_request(engine); |
b6b0fac0 MK |
3114 | if (request == NULL) |
3115 | return; | |
3116 | ||
0bc40be8 | 3117 | ring_hung = engine->hangcheck.score >= HANGCHECK_SCORE_RING_HUNG; |
b6b0fac0 | 3118 | |
7b4d3a16 | 3119 | i915_set_reset_status(request->ctx, ring_hung); |
0bc40be8 | 3120 | list_for_each_entry_continue(request, &engine->request_list, list) |
7b4d3a16 | 3121 | i915_set_reset_status(request->ctx, false); |
4db080f9 | 3122 | } |
aa60c664 | 3123 | |
7b4d3a16 | 3124 | static void i915_gem_reset_engine_cleanup(struct intel_engine_cs *engine) |
4db080f9 | 3125 | { |
608c1a52 CW |
3126 | struct intel_ringbuffer *buffer; |
3127 | ||
0bc40be8 | 3128 | while (!list_empty(&engine->active_list)) { |
05394f39 | 3129 | struct drm_i915_gem_object *obj; |
9375e446 | 3130 | |
0bc40be8 | 3131 | obj = list_first_entry(&engine->active_list, |
05394f39 | 3132 | struct drm_i915_gem_object, |
117897f4 | 3133 | engine_list[engine->id]); |
9375e446 | 3134 | |
0bc40be8 | 3135 | i915_gem_object_retire__read(obj, engine->id); |
673a394b | 3136 | } |
1d62beea | 3137 | |
dcb4c12a OM |
3138 | /* |
3139 | * Clear the execlists queue up before freeing the requests, as those | |
3140 | * are the ones that keep the context and ringbuffer backing objects | |
3141 | * pinned in place. | |
3142 | */ | |
dcb4c12a | 3143 | |
7de1691a | 3144 | if (i915.enable_execlists) { |
27af5eea TU |
3145 | /* Ensure irq handler finishes or is cancelled. */ |
3146 | tasklet_kill(&engine->irq_tasklet); | |
1197b4f2 | 3147 | |
e39d42fa | 3148 | intel_execlists_cancel_requests(engine); |
dcb4c12a OM |
3149 | } |
3150 | ||
1d62beea BW |
3151 | /* |
3152 | * We must free the requests after all the corresponding objects have | |
3153 | * been moved off active lists. Which is the same order as the normal | |
3154 | * retire_requests function does. This is important if object hold | |
3155 | * implicit references on things like e.g. ppgtt address spaces through | |
3156 | * the request. | |
3157 | */ | |
0bc40be8 | 3158 | while (!list_empty(&engine->request_list)) { |
1d62beea BW |
3159 | struct drm_i915_gem_request *request; |
3160 | ||
0bc40be8 | 3161 | request = list_first_entry(&engine->request_list, |
1d62beea BW |
3162 | struct drm_i915_gem_request, |
3163 | list); | |
3164 | ||
b4716185 | 3165 | i915_gem_request_retire(request); |
1d62beea | 3166 | } |
608c1a52 CW |
3167 | |
3168 | /* Having flushed all requests from all queues, we know that all | |
3169 | * ringbuffers must now be empty. However, since we do not reclaim | |
3170 | * all space when retiring the request (to prevent HEADs colliding | |
3171 | * with rapid ringbuffer wraparound) the amount of available space | |
3172 | * upon reset is less than when we start. Do one more pass over | |
3173 | * all the ringbuffers to reset last_retired_head. | |
3174 | */ | |
0bc40be8 | 3175 | list_for_each_entry(buffer, &engine->buffers, link) { |
608c1a52 CW |
3176 | buffer->last_retired_head = buffer->tail; |
3177 | intel_ring_update_space(buffer); | |
3178 | } | |
2ed53a94 CW |
3179 | |
3180 | intel_ring_init_seqno(engine, engine->last_submitted_seqno); | |
673a394b EA |
3181 | } |
3182 | ||
069efc1d | 3183 | void i915_gem_reset(struct drm_device *dev) |
673a394b | 3184 | { |
fac5e23e | 3185 | struct drm_i915_private *dev_priv = to_i915(dev); |
e2f80391 | 3186 | struct intel_engine_cs *engine; |
673a394b | 3187 | |
4db080f9 CW |
3188 | /* |
3189 | * Before we free the objects from the requests, we need to inspect | |
3190 | * them for finding the guilty party. As the requests only borrow | |
3191 | * their reference to the objects, the inspection must be done first. | |
3192 | */ | |
b4ac5afc | 3193 | for_each_engine(engine, dev_priv) |
7b4d3a16 | 3194 | i915_gem_reset_engine_status(engine); |
4db080f9 | 3195 | |
b4ac5afc | 3196 | for_each_engine(engine, dev_priv) |
7b4d3a16 | 3197 | i915_gem_reset_engine_cleanup(engine); |
dfaae392 | 3198 | |
acce9ffa BW |
3199 | i915_gem_context_reset(dev); |
3200 | ||
19b2dbde | 3201 | i915_gem_restore_fences(dev); |
b4716185 CW |
3202 | |
3203 | WARN_ON(i915_verify_lists(dev)); | |
673a394b EA |
3204 | } |
3205 | ||
3206 | /** | |
3207 | * This function clears the request list as sequence numbers are passed. | |
14bb2c11 | 3208 | * @engine: engine to retire requests on |
673a394b | 3209 | */ |
1cf0ba14 | 3210 | void |
0bc40be8 | 3211 | i915_gem_retire_requests_ring(struct intel_engine_cs *engine) |
673a394b | 3212 | { |
0bc40be8 | 3213 | WARN_ON(i915_verify_lists(engine->dev)); |
673a394b | 3214 | |
832a3aad CW |
3215 | /* Retire requests first as we use it above for the early return. |
3216 | * If we retire requests last, we may use a later seqno and so clear | |
3217 | * the requests lists without clearing the active list, leading to | |
3218 | * confusion. | |
e9103038 | 3219 | */ |
0bc40be8 | 3220 | while (!list_empty(&engine->request_list)) { |
673a394b | 3221 | struct drm_i915_gem_request *request; |
673a394b | 3222 | |
0bc40be8 | 3223 | request = list_first_entry(&engine->request_list, |
673a394b EA |
3224 | struct drm_i915_gem_request, |
3225 | list); | |
673a394b | 3226 | |
f69a02c9 | 3227 | if (!i915_gem_request_completed(request)) |
b84d5f0c CW |
3228 | break; |
3229 | ||
b4716185 | 3230 | i915_gem_request_retire(request); |
b84d5f0c | 3231 | } |
673a394b | 3232 | |
832a3aad CW |
3233 | /* Move any buffers on the active list that are no longer referenced |
3234 | * by the ringbuffer to the flushing/inactive lists as appropriate, | |
3235 | * before we free the context associated with the requests. | |
3236 | */ | |
0bc40be8 | 3237 | while (!list_empty(&engine->active_list)) { |
832a3aad CW |
3238 | struct drm_i915_gem_object *obj; |
3239 | ||
0bc40be8 TU |
3240 | obj = list_first_entry(&engine->active_list, |
3241 | struct drm_i915_gem_object, | |
117897f4 | 3242 | engine_list[engine->id]); |
832a3aad | 3243 | |
0bc40be8 | 3244 | if (!list_empty(&obj->last_read_req[engine->id]->list)) |
832a3aad CW |
3245 | break; |
3246 | ||
0bc40be8 | 3247 | i915_gem_object_retire__read(obj, engine->id); |
832a3aad CW |
3248 | } |
3249 | ||
0bc40be8 | 3250 | WARN_ON(i915_verify_lists(engine->dev)); |
673a394b EA |
3251 | } |
3252 | ||
67d97da3 | 3253 | void i915_gem_retire_requests(struct drm_i915_private *dev_priv) |
b09a1fec | 3254 | { |
e2f80391 | 3255 | struct intel_engine_cs *engine; |
67d97da3 | 3256 | |
91c8a326 | 3257 | lockdep_assert_held(&dev_priv->drm.struct_mutex); |
67d97da3 CW |
3258 | |
3259 | if (dev_priv->gt.active_engines == 0) | |
3260 | return; | |
3261 | ||
3262 | GEM_BUG_ON(!dev_priv->gt.awake); | |
b09a1fec | 3263 | |
b4ac5afc | 3264 | for_each_engine(engine, dev_priv) { |
e2f80391 | 3265 | i915_gem_retire_requests_ring(engine); |
67d97da3 CW |
3266 | if (list_empty(&engine->request_list)) |
3267 | dev_priv->gt.active_engines &= ~intel_engine_flag(engine); | |
b29c19b6 CW |
3268 | } |
3269 | ||
67d97da3 | 3270 | if (dev_priv->gt.active_engines == 0) |
1b51bce2 CW |
3271 | queue_delayed_work(dev_priv->wq, |
3272 | &dev_priv->gt.idle_work, | |
3273 | msecs_to_jiffies(100)); | |
b09a1fec CW |
3274 | } |
3275 | ||
75ef9da2 | 3276 | static void |
673a394b EA |
3277 | i915_gem_retire_work_handler(struct work_struct *work) |
3278 | { | |
b29c19b6 | 3279 | struct drm_i915_private *dev_priv = |
67d97da3 | 3280 | container_of(work, typeof(*dev_priv), gt.retire_work.work); |
91c8a326 | 3281 | struct drm_device *dev = &dev_priv->drm; |
673a394b | 3282 | |
891b48cf | 3283 | /* Come back later if the device is busy... */ |
b29c19b6 | 3284 | if (mutex_trylock(&dev->struct_mutex)) { |
67d97da3 | 3285 | i915_gem_retire_requests(dev_priv); |
b29c19b6 | 3286 | mutex_unlock(&dev->struct_mutex); |
673a394b | 3287 | } |
67d97da3 CW |
3288 | |
3289 | /* Keep the retire handler running until we are finally idle. | |
3290 | * We do not need to do this test under locking as in the worst-case | |
3291 | * we queue the retire worker once too often. | |
3292 | */ | |
b1379d49 | 3293 | if (READ_ONCE(dev_priv->gt.awake)) |
67d97da3 CW |
3294 | queue_delayed_work(dev_priv->wq, |
3295 | &dev_priv->gt.retire_work, | |
bcb45086 | 3296 | round_jiffies_up_relative(HZ)); |
b29c19b6 | 3297 | } |
0a58705b | 3298 | |
b29c19b6 CW |
3299 | static void |
3300 | i915_gem_idle_work_handler(struct work_struct *work) | |
3301 | { | |
3302 | struct drm_i915_private *dev_priv = | |
67d97da3 | 3303 | container_of(work, typeof(*dev_priv), gt.idle_work.work); |
91c8a326 | 3304 | struct drm_device *dev = &dev_priv->drm; |
b4ac5afc | 3305 | struct intel_engine_cs *engine; |
67d97da3 CW |
3306 | unsigned int stuck_engines; |
3307 | bool rearm_hangcheck; | |
3308 | ||
3309 | if (!READ_ONCE(dev_priv->gt.awake)) | |
3310 | return; | |
3311 | ||
3312 | if (READ_ONCE(dev_priv->gt.active_engines)) | |
3313 | return; | |
3314 | ||
3315 | rearm_hangcheck = | |
3316 | cancel_delayed_work_sync(&dev_priv->gpu_error.hangcheck_work); | |
3317 | ||
3318 | if (!mutex_trylock(&dev->struct_mutex)) { | |
3319 | /* Currently busy, come back later */ | |
3320 | mod_delayed_work(dev_priv->wq, | |
3321 | &dev_priv->gt.idle_work, | |
3322 | msecs_to_jiffies(50)); | |
3323 | goto out_rearm; | |
3324 | } | |
3325 | ||
3326 | if (dev_priv->gt.active_engines) | |
3327 | goto out_unlock; | |
b29c19b6 | 3328 | |
b4ac5afc | 3329 | for_each_engine(engine, dev_priv) |
67d97da3 | 3330 | i915_gem_batch_pool_fini(&engine->batch_pool); |
35c94185 | 3331 | |
67d97da3 CW |
3332 | GEM_BUG_ON(!dev_priv->gt.awake); |
3333 | dev_priv->gt.awake = false; | |
3334 | rearm_hangcheck = false; | |
30ecad77 | 3335 | |
67d97da3 CW |
3336 | stuck_engines = intel_kick_waiters(dev_priv); |
3337 | if (unlikely(stuck_engines)) { | |
3338 | DRM_DEBUG_DRIVER("kicked stuck waiters...missed irq\n"); | |
3339 | dev_priv->gpu_error.missed_irq_rings |= stuck_engines; | |
3340 | } | |
35c94185 | 3341 | |
67d97da3 CW |
3342 | if (INTEL_GEN(dev_priv) >= 6) |
3343 | gen6_rps_idle(dev_priv); | |
3344 | intel_runtime_pm_put(dev_priv); | |
3345 | out_unlock: | |
3346 | mutex_unlock(&dev->struct_mutex); | |
b29c19b6 | 3347 | |
67d97da3 CW |
3348 | out_rearm: |
3349 | if (rearm_hangcheck) { | |
3350 | GEM_BUG_ON(!dev_priv->gt.awake); | |
3351 | i915_queue_hangcheck(dev_priv); | |
35c94185 | 3352 | } |
673a394b EA |
3353 | } |
3354 | ||
30dfebf3 DV |
3355 | /** |
3356 | * Ensures that an object will eventually get non-busy by flushing any required | |
3357 | * write domains, emitting any outstanding lazy request and retiring and | |
3358 | * completed requests. | |
14bb2c11 | 3359 | * @obj: object to flush |
30dfebf3 DV |
3360 | */ |
3361 | static int | |
3362 | i915_gem_object_flush_active(struct drm_i915_gem_object *obj) | |
3363 | { | |
a5ac0f90 | 3364 | int i; |
b4716185 CW |
3365 | |
3366 | if (!obj->active) | |
3367 | return 0; | |
30dfebf3 | 3368 | |
666796da | 3369 | for (i = 0; i < I915_NUM_ENGINES; i++) { |
b4716185 | 3370 | struct drm_i915_gem_request *req; |
41c52415 | 3371 | |
b4716185 CW |
3372 | req = obj->last_read_req[i]; |
3373 | if (req == NULL) | |
3374 | continue; | |
3375 | ||
f69a02c9 | 3376 | if (i915_gem_request_completed(req)) |
b4716185 | 3377 | i915_gem_object_retire__read(obj, i); |
30dfebf3 DV |
3378 | } |
3379 | ||
3380 | return 0; | |
3381 | } | |
3382 | ||
23ba4fd0 BW |
3383 | /** |
3384 | * i915_gem_wait_ioctl - implements DRM_IOCTL_I915_GEM_WAIT | |
14bb2c11 TU |
3385 | * @dev: drm device pointer |
3386 | * @data: ioctl data blob | |
3387 | * @file: drm file pointer | |
23ba4fd0 BW |
3388 | * |
3389 | * Returns 0 if successful, else an error is returned with the remaining time in | |
3390 | * the timeout parameter. | |
3391 | * -ETIME: object is still busy after timeout | |
3392 | * -ERESTARTSYS: signal interrupted the wait | |
3393 | * -ENONENT: object doesn't exist | |
3394 | * Also possible, but rare: | |
3395 | * -EAGAIN: GPU wedged | |
3396 | * -ENOMEM: damn | |
3397 | * -ENODEV: Internal IRQ fail | |
3398 | * -E?: The add request failed | |
3399 | * | |
3400 | * The wait ioctl with a timeout of 0 reimplements the busy ioctl. With any | |
3401 | * non-zero timeout parameter the wait ioctl will wait for the given number of | |
3402 | * nanoseconds on an object becoming unbusy. Since the wait itself does so | |
3403 | * without holding struct_mutex the object may become re-busied before this | |
3404 | * function completes. A similar but shorter * race condition exists in the busy | |
3405 | * ioctl | |
3406 | */ | |
3407 | int | |
3408 | i915_gem_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *file) | |
3409 | { | |
3410 | struct drm_i915_gem_wait *args = data; | |
3411 | struct drm_i915_gem_object *obj; | |
666796da | 3412 | struct drm_i915_gem_request *req[I915_NUM_ENGINES]; |
b4716185 CW |
3413 | int i, n = 0; |
3414 | int ret; | |
23ba4fd0 | 3415 | |
11b5d511 DV |
3416 | if (args->flags != 0) |
3417 | return -EINVAL; | |
3418 | ||
23ba4fd0 BW |
3419 | ret = i915_mutex_lock_interruptible(dev); |
3420 | if (ret) | |
3421 | return ret; | |
3422 | ||
a8ad0bd8 | 3423 | obj = to_intel_bo(drm_gem_object_lookup(file, args->bo_handle)); |
23ba4fd0 BW |
3424 | if (&obj->base == NULL) { |
3425 | mutex_unlock(&dev->struct_mutex); | |
3426 | return -ENOENT; | |
3427 | } | |
3428 | ||
30dfebf3 DV |
3429 | /* Need to make sure the object gets inactive eventually. */ |
3430 | ret = i915_gem_object_flush_active(obj); | |
23ba4fd0 BW |
3431 | if (ret) |
3432 | goto out; | |
3433 | ||
b4716185 | 3434 | if (!obj->active) |
97b2a6a1 | 3435 | goto out; |
23ba4fd0 | 3436 | |
23ba4fd0 | 3437 | /* Do this after OLR check to make sure we make forward progress polling |
762e4583 | 3438 | * on this IOCTL with a timeout == 0 (like busy ioctl) |
23ba4fd0 | 3439 | */ |
762e4583 | 3440 | if (args->timeout_ns == 0) { |
23ba4fd0 BW |
3441 | ret = -ETIME; |
3442 | goto out; | |
3443 | } | |
3444 | ||
3445 | drm_gem_object_unreference(&obj->base); | |
b4716185 | 3446 | |
666796da | 3447 | for (i = 0; i < I915_NUM_ENGINES; i++) { |
b4716185 CW |
3448 | if (obj->last_read_req[i] == NULL) |
3449 | continue; | |
3450 | ||
3451 | req[n++] = i915_gem_request_reference(obj->last_read_req[i]); | |
3452 | } | |
3453 | ||
23ba4fd0 BW |
3454 | mutex_unlock(&dev->struct_mutex); |
3455 | ||
b4716185 CW |
3456 | for (i = 0; i < n; i++) { |
3457 | if (ret == 0) | |
299259a3 | 3458 | ret = __i915_wait_request(req[i], true, |
b4716185 | 3459 | args->timeout_ns > 0 ? &args->timeout_ns : NULL, |
b6aa0873 | 3460 | to_rps_client(file)); |
73db04cf | 3461 | i915_gem_request_unreference(req[i]); |
b4716185 | 3462 | } |
ff865885 | 3463 | return ret; |
23ba4fd0 BW |
3464 | |
3465 | out: | |
3466 | drm_gem_object_unreference(&obj->base); | |
3467 | mutex_unlock(&dev->struct_mutex); | |
3468 | return ret; | |
3469 | } | |
3470 | ||
b4716185 CW |
3471 | static int |
3472 | __i915_gem_object_sync(struct drm_i915_gem_object *obj, | |
3473 | struct intel_engine_cs *to, | |
91af127f JH |
3474 | struct drm_i915_gem_request *from_req, |
3475 | struct drm_i915_gem_request **to_req) | |
b4716185 CW |
3476 | { |
3477 | struct intel_engine_cs *from; | |
3478 | int ret; | |
3479 | ||
666796da | 3480 | from = i915_gem_request_get_engine(from_req); |
b4716185 CW |
3481 | if (to == from) |
3482 | return 0; | |
3483 | ||
f69a02c9 | 3484 | if (i915_gem_request_completed(from_req)) |
b4716185 CW |
3485 | return 0; |
3486 | ||
c033666a | 3487 | if (!i915_semaphore_is_enabled(to_i915(obj->base.dev))) { |
a6f766f3 | 3488 | struct drm_i915_private *i915 = to_i915(obj->base.dev); |
91af127f | 3489 | ret = __i915_wait_request(from_req, |
a6f766f3 CW |
3490 | i915->mm.interruptible, |
3491 | NULL, | |
3492 | &i915->rps.semaphores); | |
b4716185 CW |
3493 | if (ret) |
3494 | return ret; | |
3495 | ||
91af127f | 3496 | i915_gem_object_retire_request(obj, from_req); |
b4716185 CW |
3497 | } else { |
3498 | int idx = intel_ring_sync_index(from, to); | |
91af127f JH |
3499 | u32 seqno = i915_gem_request_get_seqno(from_req); |
3500 | ||
3501 | WARN_ON(!to_req); | |
b4716185 CW |
3502 | |
3503 | if (seqno <= from->semaphore.sync_seqno[idx]) | |
3504 | return 0; | |
3505 | ||
91af127f | 3506 | if (*to_req == NULL) { |
26827088 DG |
3507 | struct drm_i915_gem_request *req; |
3508 | ||
3509 | req = i915_gem_request_alloc(to, NULL); | |
3510 | if (IS_ERR(req)) | |
3511 | return PTR_ERR(req); | |
3512 | ||
3513 | *to_req = req; | |
91af127f JH |
3514 | } |
3515 | ||
599d924c JH |
3516 | trace_i915_gem_ring_sync_to(*to_req, from, from_req); |
3517 | ret = to->semaphore.sync_to(*to_req, from, seqno); | |
b4716185 CW |
3518 | if (ret) |
3519 | return ret; | |
3520 | ||
3521 | /* We use last_read_req because sync_to() | |
3522 | * might have just caused seqno wrap under | |
3523 | * the radar. | |
3524 | */ | |
3525 | from->semaphore.sync_seqno[idx] = | |
3526 | i915_gem_request_get_seqno(obj->last_read_req[from->id]); | |
3527 | } | |
3528 | ||
3529 | return 0; | |
3530 | } | |
3531 | ||
5816d648 BW |
3532 | /** |
3533 | * i915_gem_object_sync - sync an object to a ring. | |
3534 | * | |
3535 | * @obj: object which may be in use on another ring. | |
3536 | * @to: ring we wish to use the object on. May be NULL. | |
91af127f JH |
3537 | * @to_req: request we wish to use the object for. See below. |
3538 | * This will be allocated and returned if a request is | |
3539 | * required but not passed in. | |
5816d648 BW |
3540 | * |
3541 | * This code is meant to abstract object synchronization with the GPU. | |
3542 | * Calling with NULL implies synchronizing the object with the CPU | |
b4716185 | 3543 | * rather than a particular GPU ring. Conceptually we serialise writes |
91af127f | 3544 | * between engines inside the GPU. We only allow one engine to write |
b4716185 CW |
3545 | * into a buffer at any time, but multiple readers. To ensure each has |
3546 | * a coherent view of memory, we must: | |
3547 | * | |
3548 | * - If there is an outstanding write request to the object, the new | |
3549 | * request must wait for it to complete (either CPU or in hw, requests | |
3550 | * on the same ring will be naturally ordered). | |
3551 | * | |
3552 | * - If we are a write request (pending_write_domain is set), the new | |
3553 | * request must wait for outstanding read requests to complete. | |
5816d648 | 3554 | * |
91af127f JH |
3555 | * For CPU synchronisation (NULL to) no request is required. For syncing with |
3556 | * rings to_req must be non-NULL. However, a request does not have to be | |
3557 | * pre-allocated. If *to_req is NULL and sync commands will be emitted then a | |
3558 | * request will be allocated automatically and returned through *to_req. Note | |
3559 | * that it is not guaranteed that commands will be emitted (because the system | |
3560 | * might already be idle). Hence there is no need to create a request that | |
3561 | * might never have any work submitted. Note further that if a request is | |
3562 | * returned in *to_req, it is the responsibility of the caller to submit | |
3563 | * that request (after potentially adding more work to it). | |
3564 | * | |
5816d648 BW |
3565 | * Returns 0 if successful, else propagates up the lower layer error. |
3566 | */ | |
2911a35b BW |
3567 | int |
3568 | i915_gem_object_sync(struct drm_i915_gem_object *obj, | |
91af127f JH |
3569 | struct intel_engine_cs *to, |
3570 | struct drm_i915_gem_request **to_req) | |
2911a35b | 3571 | { |
b4716185 | 3572 | const bool readonly = obj->base.pending_write_domain == 0; |
666796da | 3573 | struct drm_i915_gem_request *req[I915_NUM_ENGINES]; |
b4716185 | 3574 | int ret, i, n; |
41c52415 | 3575 | |
b4716185 | 3576 | if (!obj->active) |
2911a35b BW |
3577 | return 0; |
3578 | ||
b4716185 CW |
3579 | if (to == NULL) |
3580 | return i915_gem_object_wait_rendering(obj, readonly); | |
2911a35b | 3581 | |
b4716185 CW |
3582 | n = 0; |
3583 | if (readonly) { | |
3584 | if (obj->last_write_req) | |
3585 | req[n++] = obj->last_write_req; | |
3586 | } else { | |
666796da | 3587 | for (i = 0; i < I915_NUM_ENGINES; i++) |
b4716185 CW |
3588 | if (obj->last_read_req[i]) |
3589 | req[n++] = obj->last_read_req[i]; | |
3590 | } | |
3591 | for (i = 0; i < n; i++) { | |
91af127f | 3592 | ret = __i915_gem_object_sync(obj, to, req[i], to_req); |
b4716185 CW |
3593 | if (ret) |
3594 | return ret; | |
3595 | } | |
2911a35b | 3596 | |
b4716185 | 3597 | return 0; |
2911a35b BW |
3598 | } |
3599 | ||
b5ffc9bc CW |
3600 | static void i915_gem_object_finish_gtt(struct drm_i915_gem_object *obj) |
3601 | { | |
3602 | u32 old_write_domain, old_read_domains; | |
3603 | ||
b5ffc9bc CW |
3604 | /* Force a pagefault for domain tracking on next user access */ |
3605 | i915_gem_release_mmap(obj); | |
3606 | ||
b97c3d9c KP |
3607 | if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0) |
3608 | return; | |
3609 | ||
b5ffc9bc CW |
3610 | old_read_domains = obj->base.read_domains; |
3611 | old_write_domain = obj->base.write_domain; | |
3612 | ||
3613 | obj->base.read_domains &= ~I915_GEM_DOMAIN_GTT; | |
3614 | obj->base.write_domain &= ~I915_GEM_DOMAIN_GTT; | |
3615 | ||
3616 | trace_i915_gem_object_change_domain(obj, | |
3617 | old_read_domains, | |
3618 | old_write_domain); | |
3619 | } | |
3620 | ||
8ef8561f CW |
3621 | static void __i915_vma_iounmap(struct i915_vma *vma) |
3622 | { | |
3623 | GEM_BUG_ON(vma->pin_count); | |
3624 | ||
3625 | if (vma->iomap == NULL) | |
3626 | return; | |
3627 | ||
3628 | io_mapping_unmap(vma->iomap); | |
3629 | vma->iomap = NULL; | |
3630 | } | |
3631 | ||
e9f24d5f | 3632 | static int __i915_vma_unbind(struct i915_vma *vma, bool wait) |
673a394b | 3633 | { |
07fe0b12 | 3634 | struct drm_i915_gem_object *obj = vma->obj; |
fac5e23e | 3635 | struct drm_i915_private *dev_priv = to_i915(obj->base.dev); |
43e28f09 | 3636 | int ret; |
673a394b | 3637 | |
1c7f4bca | 3638 | if (list_empty(&vma->obj_link)) |
673a394b EA |
3639 | return 0; |
3640 | ||
0ff501cb DV |
3641 | if (!drm_mm_node_allocated(&vma->node)) { |
3642 | i915_gem_vma_destroy(vma); | |
0ff501cb DV |
3643 | return 0; |
3644 | } | |
433544bd | 3645 | |
d7f46fc4 | 3646 | if (vma->pin_count) |
31d8d651 | 3647 | return -EBUSY; |
673a394b | 3648 | |
c4670ad0 CW |
3649 | BUG_ON(obj->pages == NULL); |
3650 | ||
e9f24d5f TU |
3651 | if (wait) { |
3652 | ret = i915_gem_object_wait_rendering(obj, false); | |
3653 | if (ret) | |
3654 | return ret; | |
3655 | } | |
a8198eea | 3656 | |
596c5923 | 3657 | if (vma->is_ggtt && vma->ggtt_view.type == I915_GGTT_VIEW_NORMAL) { |
8b1bc9b4 | 3658 | i915_gem_object_finish_gtt(obj); |
5323fd04 | 3659 | |
8b1bc9b4 DV |
3660 | /* release the fence reg _after_ flushing */ |
3661 | ret = i915_gem_object_put_fence(obj); | |
3662 | if (ret) | |
3663 | return ret; | |
8ef8561f CW |
3664 | |
3665 | __i915_vma_iounmap(vma); | |
8b1bc9b4 | 3666 | } |
96b47b65 | 3667 | |
07fe0b12 | 3668 | trace_i915_vma_unbind(vma); |
db53a302 | 3669 | |
777dc5bb | 3670 | vma->vm->unbind_vma(vma); |
5e562f1d | 3671 | vma->bound = 0; |
6f65e29a | 3672 | |
1c7f4bca | 3673 | list_del_init(&vma->vm_link); |
596c5923 | 3674 | if (vma->is_ggtt) { |
fe14d5f4 TU |
3675 | if (vma->ggtt_view.type == I915_GGTT_VIEW_NORMAL) { |
3676 | obj->map_and_fenceable = false; | |
3677 | } else if (vma->ggtt_view.pages) { | |
3678 | sg_free_table(vma->ggtt_view.pages); | |
3679 | kfree(vma->ggtt_view.pages); | |
fe14d5f4 | 3680 | } |
016a65a3 | 3681 | vma->ggtt_view.pages = NULL; |
fe14d5f4 | 3682 | } |
673a394b | 3683 | |
2f633156 BW |
3684 | drm_mm_remove_node(&vma->node); |
3685 | i915_gem_vma_destroy(vma); | |
3686 | ||
3687 | /* Since the unbound list is global, only move to that list if | |
b93dab6e | 3688 | * no more VMAs exist. */ |
e2273302 | 3689 | if (list_empty(&obj->vma_list)) |
2f633156 | 3690 | list_move_tail(&obj->global_list, &dev_priv->mm.unbound_list); |
673a394b | 3691 | |
70903c3b CW |
3692 | /* And finally now the object is completely decoupled from this vma, |
3693 | * we can drop its hold on the backing storage and allow it to be | |
3694 | * reaped by the shrinker. | |
3695 | */ | |
3696 | i915_gem_object_unpin_pages(obj); | |
3697 | ||
88241785 | 3698 | return 0; |
54cf91dc CW |
3699 | } |
3700 | ||
e9f24d5f TU |
3701 | int i915_vma_unbind(struct i915_vma *vma) |
3702 | { | |
3703 | return __i915_vma_unbind(vma, true); | |
3704 | } | |
3705 | ||
3706 | int __i915_vma_unbind_no_wait(struct i915_vma *vma) | |
3707 | { | |
3708 | return __i915_vma_unbind(vma, false); | |
3709 | } | |
3710 | ||
6e5a5beb | 3711 | int i915_gem_wait_for_idle(struct drm_i915_private *dev_priv) |
4df2faf4 | 3712 | { |
e2f80391 | 3713 | struct intel_engine_cs *engine; |
b4ac5afc | 3714 | int ret; |
4df2faf4 | 3715 | |
91c8a326 | 3716 | lockdep_assert_held(&dev_priv->drm.struct_mutex); |
6e5a5beb | 3717 | |
b4ac5afc | 3718 | for_each_engine(engine, dev_priv) { |
62e63007 CW |
3719 | if (engine->last_context == NULL) |
3720 | continue; | |
3721 | ||
666796da | 3722 | ret = intel_engine_idle(engine); |
1ec14ad3 CW |
3723 | if (ret) |
3724 | return ret; | |
3725 | } | |
4df2faf4 | 3726 | |
b4716185 | 3727 | WARN_ON(i915_verify_lists(dev)); |
8a1a49f9 | 3728 | return 0; |
4df2faf4 DV |
3729 | } |
3730 | ||
4144f9b5 | 3731 | static bool i915_gem_valid_gtt_space(struct i915_vma *vma, |
42d6ab48 CW |
3732 | unsigned long cache_level) |
3733 | { | |
4144f9b5 | 3734 | struct drm_mm_node *gtt_space = &vma->node; |
42d6ab48 CW |
3735 | struct drm_mm_node *other; |
3736 | ||
4144f9b5 CW |
3737 | /* |
3738 | * On some machines we have to be careful when putting differing types | |
3739 | * of snoopable memory together to avoid the prefetcher crossing memory | |
3740 | * domains and dying. During vm initialisation, we decide whether or not | |
3741 | * these constraints apply and set the drm_mm.color_adjust | |
3742 | * appropriately. | |
42d6ab48 | 3743 | */ |
4144f9b5 | 3744 | if (vma->vm->mm.color_adjust == NULL) |
42d6ab48 CW |
3745 | return true; |
3746 | ||
c6cfb325 | 3747 | if (!drm_mm_node_allocated(gtt_space)) |
42d6ab48 CW |
3748 | return true; |
3749 | ||
3750 | if (list_empty(>t_space->node_list)) | |
3751 | return true; | |
3752 | ||
3753 | other = list_entry(gtt_space->node_list.prev, struct drm_mm_node, node_list); | |
3754 | if (other->allocated && !other->hole_follows && other->color != cache_level) | |
3755 | return false; | |
3756 | ||
3757 | other = list_entry(gtt_space->node_list.next, struct drm_mm_node, node_list); | |
3758 | if (other->allocated && !gtt_space->hole_follows && other->color != cache_level) | |
3759 | return false; | |
3760 | ||
3761 | return true; | |
3762 | } | |
3763 | ||
673a394b | 3764 | /** |
91e6711e JL |
3765 | * Finds free space in the GTT aperture and binds the object or a view of it |
3766 | * there. | |
14bb2c11 TU |
3767 | * @obj: object to bind |
3768 | * @vm: address space to bind into | |
3769 | * @ggtt_view: global gtt view if applicable | |
3770 | * @alignment: requested alignment | |
3771 | * @flags: mask of PIN_* flags to use | |
673a394b | 3772 | */ |
262de145 | 3773 | static struct i915_vma * |
07fe0b12 BW |
3774 | i915_gem_object_bind_to_vm(struct drm_i915_gem_object *obj, |
3775 | struct i915_address_space *vm, | |
ec7adb6e | 3776 | const struct i915_ggtt_view *ggtt_view, |
07fe0b12 | 3777 | unsigned alignment, |
ec7adb6e | 3778 | uint64_t flags) |
673a394b | 3779 | { |
05394f39 | 3780 | struct drm_device *dev = obj->base.dev; |
72e96d64 JL |
3781 | struct drm_i915_private *dev_priv = to_i915(dev); |
3782 | struct i915_ggtt *ggtt = &dev_priv->ggtt; | |
65bd342f | 3783 | u32 fence_alignment, unfenced_alignment; |
101b506a MT |
3784 | u32 search_flag, alloc_flag; |
3785 | u64 start, end; | |
65bd342f | 3786 | u64 size, fence_size; |
2f633156 | 3787 | struct i915_vma *vma; |
07f73f69 | 3788 | int ret; |
673a394b | 3789 | |
91e6711e JL |
3790 | if (i915_is_ggtt(vm)) { |
3791 | u32 view_size; | |
3792 | ||
3793 | if (WARN_ON(!ggtt_view)) | |
3794 | return ERR_PTR(-EINVAL); | |
ec7adb6e | 3795 | |
91e6711e JL |
3796 | view_size = i915_ggtt_view_size(obj, ggtt_view); |
3797 | ||
3798 | fence_size = i915_gem_get_gtt_size(dev, | |
3799 | view_size, | |
3800 | obj->tiling_mode); | |
3801 | fence_alignment = i915_gem_get_gtt_alignment(dev, | |
3802 | view_size, | |
3803 | obj->tiling_mode, | |
3804 | true); | |
3805 | unfenced_alignment = i915_gem_get_gtt_alignment(dev, | |
3806 | view_size, | |
3807 | obj->tiling_mode, | |
3808 | false); | |
3809 | size = flags & PIN_MAPPABLE ? fence_size : view_size; | |
3810 | } else { | |
3811 | fence_size = i915_gem_get_gtt_size(dev, | |
3812 | obj->base.size, | |
3813 | obj->tiling_mode); | |
3814 | fence_alignment = i915_gem_get_gtt_alignment(dev, | |
3815 | obj->base.size, | |
3816 | obj->tiling_mode, | |
3817 | true); | |
3818 | unfenced_alignment = | |
3819 | i915_gem_get_gtt_alignment(dev, | |
3820 | obj->base.size, | |
3821 | obj->tiling_mode, | |
3822 | false); | |
3823 | size = flags & PIN_MAPPABLE ? fence_size : obj->base.size; | |
3824 | } | |
a00b10c3 | 3825 | |
101b506a MT |
3826 | start = flags & PIN_OFFSET_BIAS ? flags & PIN_OFFSET_MASK : 0; |
3827 | end = vm->total; | |
3828 | if (flags & PIN_MAPPABLE) | |
72e96d64 | 3829 | end = min_t(u64, end, ggtt->mappable_end); |
101b506a | 3830 | if (flags & PIN_ZONE_4G) |
48ea1e32 | 3831 | end = min_t(u64, end, (1ULL << 32) - PAGE_SIZE); |
101b506a | 3832 | |
673a394b | 3833 | if (alignment == 0) |
1ec9e26d | 3834 | alignment = flags & PIN_MAPPABLE ? fence_alignment : |
5e783301 | 3835 | unfenced_alignment; |
1ec9e26d | 3836 | if (flags & PIN_MAPPABLE && alignment & (fence_alignment - 1)) { |
91e6711e JL |
3837 | DRM_DEBUG("Invalid object (view type=%u) alignment requested %u\n", |
3838 | ggtt_view ? ggtt_view->type : 0, | |
3839 | alignment); | |
262de145 | 3840 | return ERR_PTR(-EINVAL); |
673a394b EA |
3841 | } |
3842 | ||
91e6711e JL |
3843 | /* If binding the object/GGTT view requires more space than the entire |
3844 | * aperture has, reject it early before evicting everything in a vain | |
3845 | * attempt to find space. | |
654fc607 | 3846 | */ |
91e6711e | 3847 | if (size > end) { |
65bd342f | 3848 | DRM_DEBUG("Attempting to bind an object (view type=%u) larger than the aperture: size=%llu > %s aperture=%llu\n", |
91e6711e JL |
3849 | ggtt_view ? ggtt_view->type : 0, |
3850 | size, | |
1ec9e26d | 3851 | flags & PIN_MAPPABLE ? "mappable" : "total", |
d23db88c | 3852 | end); |
262de145 | 3853 | return ERR_PTR(-E2BIG); |
654fc607 CW |
3854 | } |
3855 | ||
37e680a1 | 3856 | ret = i915_gem_object_get_pages(obj); |
6c085a72 | 3857 | if (ret) |
262de145 | 3858 | return ERR_PTR(ret); |
6c085a72 | 3859 | |
fbdda6fb CW |
3860 | i915_gem_object_pin_pages(obj); |
3861 | ||
ec7adb6e JL |
3862 | vma = ggtt_view ? i915_gem_obj_lookup_or_create_ggtt_vma(obj, ggtt_view) : |
3863 | i915_gem_obj_lookup_or_create_vma(obj, vm); | |
3864 | ||
262de145 | 3865 | if (IS_ERR(vma)) |
bc6bc15b | 3866 | goto err_unpin; |
2f633156 | 3867 | |
506a8e87 CW |
3868 | if (flags & PIN_OFFSET_FIXED) { |
3869 | uint64_t offset = flags & PIN_OFFSET_MASK; | |
3870 | ||
3871 | if (offset & (alignment - 1) || offset + size > end) { | |
3872 | ret = -EINVAL; | |
3873 | goto err_free_vma; | |
3874 | } | |
3875 | vma->node.start = offset; | |
3876 | vma->node.size = size; | |
3877 | vma->node.color = obj->cache_level; | |
3878 | ret = drm_mm_reserve_node(&vm->mm, &vma->node); | |
3879 | if (ret) { | |
3880 | ret = i915_gem_evict_for_vma(vma); | |
3881 | if (ret == 0) | |
3882 | ret = drm_mm_reserve_node(&vm->mm, &vma->node); | |
3883 | } | |
3884 | if (ret) | |
3885 | goto err_free_vma; | |
101b506a | 3886 | } else { |
506a8e87 CW |
3887 | if (flags & PIN_HIGH) { |
3888 | search_flag = DRM_MM_SEARCH_BELOW; | |
3889 | alloc_flag = DRM_MM_CREATE_TOP; | |
3890 | } else { | |
3891 | search_flag = DRM_MM_SEARCH_DEFAULT; | |
3892 | alloc_flag = DRM_MM_CREATE_DEFAULT; | |
3893 | } | |
101b506a | 3894 | |
0a9ae0d7 | 3895 | search_free: |
506a8e87 CW |
3896 | ret = drm_mm_insert_node_in_range_generic(&vm->mm, &vma->node, |
3897 | size, alignment, | |
3898 | obj->cache_level, | |
3899 | start, end, | |
3900 | search_flag, | |
3901 | alloc_flag); | |
3902 | if (ret) { | |
3903 | ret = i915_gem_evict_something(dev, vm, size, alignment, | |
3904 | obj->cache_level, | |
3905 | start, end, | |
3906 | flags); | |
3907 | if (ret == 0) | |
3908 | goto search_free; | |
9731129c | 3909 | |
506a8e87 CW |
3910 | goto err_free_vma; |
3911 | } | |
673a394b | 3912 | } |
4144f9b5 | 3913 | if (WARN_ON(!i915_gem_valid_gtt_space(vma, obj->cache_level))) { |
2f633156 | 3914 | ret = -EINVAL; |
bc6bc15b | 3915 | goto err_remove_node; |
673a394b EA |
3916 | } |
3917 | ||
fe14d5f4 | 3918 | trace_i915_vma_bind(vma, flags); |
0875546c | 3919 | ret = i915_vma_bind(vma, obj->cache_level, flags); |
fe14d5f4 | 3920 | if (ret) |
e2273302 | 3921 | goto err_remove_node; |
fe14d5f4 | 3922 | |
35c20a60 | 3923 | list_move_tail(&obj->global_list, &dev_priv->mm.bound_list); |
1c7f4bca | 3924 | list_add_tail(&vma->vm_link, &vm->inactive_list); |
bf1a1092 | 3925 | |
262de145 | 3926 | return vma; |
2f633156 | 3927 | |
bc6bc15b | 3928 | err_remove_node: |
6286ef9b | 3929 | drm_mm_remove_node(&vma->node); |
bc6bc15b | 3930 | err_free_vma: |
2f633156 | 3931 | i915_gem_vma_destroy(vma); |
262de145 | 3932 | vma = ERR_PTR(ret); |
bc6bc15b | 3933 | err_unpin: |
2f633156 | 3934 | i915_gem_object_unpin_pages(obj); |
262de145 | 3935 | return vma; |
673a394b EA |
3936 | } |
3937 | ||
000433b6 | 3938 | bool |
2c22569b CW |
3939 | i915_gem_clflush_object(struct drm_i915_gem_object *obj, |
3940 | bool force) | |
673a394b | 3941 | { |
673a394b EA |
3942 | /* If we don't have a page list set up, then we're not pinned |
3943 | * to GPU, and we can ignore the cache flush because it'll happen | |
3944 | * again at bind time. | |
3945 | */ | |
05394f39 | 3946 | if (obj->pages == NULL) |
000433b6 | 3947 | return false; |
673a394b | 3948 | |
769ce464 ID |
3949 | /* |
3950 | * Stolen memory is always coherent with the GPU as it is explicitly | |
3951 | * marked as wc by the system, or the system is cache-coherent. | |
3952 | */ | |
6a2c4232 | 3953 | if (obj->stolen || obj->phys_handle) |
000433b6 | 3954 | return false; |
769ce464 | 3955 | |
9c23f7fc CW |
3956 | /* If the GPU is snooping the contents of the CPU cache, |
3957 | * we do not need to manually clear the CPU cache lines. However, | |
3958 | * the caches are only snooped when the render cache is | |
3959 | * flushed/invalidated. As we always have to emit invalidations | |
3960 | * and flushes when moving into and out of the RENDER domain, correct | |
3961 | * snooping behaviour occurs naturally as the result of our domain | |
3962 | * tracking. | |
3963 | */ | |
0f71979a CW |
3964 | if (!force && cpu_cache_is_coherent(obj->base.dev, obj->cache_level)) { |
3965 | obj->cache_dirty = true; | |
000433b6 | 3966 | return false; |
0f71979a | 3967 | } |
9c23f7fc | 3968 | |
1c5d22f7 | 3969 | trace_i915_gem_object_clflush(obj); |
9da3da66 | 3970 | drm_clflush_sg(obj->pages); |
0f71979a | 3971 | obj->cache_dirty = false; |
000433b6 CW |
3972 | |
3973 | return true; | |
e47c68e9 EA |
3974 | } |
3975 | ||
3976 | /** Flushes the GTT write domain for the object if it's dirty. */ | |
3977 | static void | |
05394f39 | 3978 | i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj) |
e47c68e9 | 3979 | { |
1c5d22f7 CW |
3980 | uint32_t old_write_domain; |
3981 | ||
05394f39 | 3982 | if (obj->base.write_domain != I915_GEM_DOMAIN_GTT) |
e47c68e9 EA |
3983 | return; |
3984 | ||
63256ec5 | 3985 | /* No actual flushing is required for the GTT write domain. Writes |
e47c68e9 EA |
3986 | * to it immediately go to main memory as far as we know, so there's |
3987 | * no chipset flush. It also doesn't land in render cache. | |
63256ec5 CW |
3988 | * |
3989 | * However, we do have to enforce the order so that all writes through | |
3990 | * the GTT land before any writes to the device, such as updates to | |
3991 | * the GATT itself. | |
e47c68e9 | 3992 | */ |
63256ec5 CW |
3993 | wmb(); |
3994 | ||
05394f39 CW |
3995 | old_write_domain = obj->base.write_domain; |
3996 | obj->base.write_domain = 0; | |
1c5d22f7 | 3997 | |
de152b62 | 3998 | intel_fb_obj_flush(obj, false, ORIGIN_GTT); |
f99d7069 | 3999 | |
1c5d22f7 | 4000 | trace_i915_gem_object_change_domain(obj, |
05394f39 | 4001 | obj->base.read_domains, |
1c5d22f7 | 4002 | old_write_domain); |
e47c68e9 EA |
4003 | } |
4004 | ||
4005 | /** Flushes the CPU write domain for the object if it's dirty. */ | |
4006 | static void | |
e62b59e4 | 4007 | i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj) |
e47c68e9 | 4008 | { |
1c5d22f7 | 4009 | uint32_t old_write_domain; |
e47c68e9 | 4010 | |
05394f39 | 4011 | if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) |
e47c68e9 EA |
4012 | return; |
4013 | ||
e62b59e4 | 4014 | if (i915_gem_clflush_object(obj, obj->pin_display)) |
c033666a | 4015 | i915_gem_chipset_flush(to_i915(obj->base.dev)); |
000433b6 | 4016 | |
05394f39 CW |
4017 | old_write_domain = obj->base.write_domain; |
4018 | obj->base.write_domain = 0; | |
1c5d22f7 | 4019 | |
de152b62 | 4020 | intel_fb_obj_flush(obj, false, ORIGIN_CPU); |
f99d7069 | 4021 | |
1c5d22f7 | 4022 | trace_i915_gem_object_change_domain(obj, |
05394f39 | 4023 | obj->base.read_domains, |
1c5d22f7 | 4024 | old_write_domain); |
e47c68e9 EA |
4025 | } |
4026 | ||
2ef7eeaa EA |
4027 | /** |
4028 | * Moves a single object to the GTT read, and possibly write domain. | |
14bb2c11 TU |
4029 | * @obj: object to act on |
4030 | * @write: ask for write access or read only | |
2ef7eeaa EA |
4031 | * |
4032 | * This function returns when the move is complete, including waiting on | |
4033 | * flushes to occur. | |
4034 | */ | |
79e53945 | 4035 | int |
2021746e | 4036 | i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write) |
2ef7eeaa | 4037 | { |
72e96d64 JL |
4038 | struct drm_device *dev = obj->base.dev; |
4039 | struct drm_i915_private *dev_priv = to_i915(dev); | |
4040 | struct i915_ggtt *ggtt = &dev_priv->ggtt; | |
1c5d22f7 | 4041 | uint32_t old_write_domain, old_read_domains; |
43566ded | 4042 | struct i915_vma *vma; |
e47c68e9 | 4043 | int ret; |
2ef7eeaa | 4044 | |
8d7e3de1 CW |
4045 | if (obj->base.write_domain == I915_GEM_DOMAIN_GTT) |
4046 | return 0; | |
4047 | ||
0201f1ec | 4048 | ret = i915_gem_object_wait_rendering(obj, !write); |
88241785 CW |
4049 | if (ret) |
4050 | return ret; | |
4051 | ||
43566ded CW |
4052 | /* Flush and acquire obj->pages so that we are coherent through |
4053 | * direct access in memory with previous cached writes through | |
4054 | * shmemfs and that our cache domain tracking remains valid. | |
4055 | * For example, if the obj->filp was moved to swap without us | |
4056 | * being notified and releasing the pages, we would mistakenly | |
4057 | * continue to assume that the obj remained out of the CPU cached | |
4058 | * domain. | |
4059 | */ | |
4060 | ret = i915_gem_object_get_pages(obj); | |
4061 | if (ret) | |
4062 | return ret; | |
4063 | ||
e62b59e4 | 4064 | i915_gem_object_flush_cpu_write_domain(obj); |
1c5d22f7 | 4065 | |
d0a57789 CW |
4066 | /* Serialise direct access to this object with the barriers for |
4067 | * coherent writes from the GPU, by effectively invalidating the | |
4068 | * GTT domain upon first access. | |
4069 | */ | |
4070 | if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0) | |
4071 | mb(); | |
4072 | ||
05394f39 CW |
4073 | old_write_domain = obj->base.write_domain; |
4074 | old_read_domains = obj->base.read_domains; | |
1c5d22f7 | 4075 | |
e47c68e9 EA |
4076 | /* It should now be out of any other write domains, and we can update |
4077 | * the domain values for our changes. | |
4078 | */ | |
05394f39 CW |
4079 | BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) != 0); |
4080 | obj->base.read_domains |= I915_GEM_DOMAIN_GTT; | |
e47c68e9 | 4081 | if (write) { |
05394f39 CW |
4082 | obj->base.read_domains = I915_GEM_DOMAIN_GTT; |
4083 | obj->base.write_domain = I915_GEM_DOMAIN_GTT; | |
4084 | obj->dirty = 1; | |
2ef7eeaa EA |
4085 | } |
4086 | ||
1c5d22f7 CW |
4087 | trace_i915_gem_object_change_domain(obj, |
4088 | old_read_domains, | |
4089 | old_write_domain); | |
4090 | ||
8325a09d | 4091 | /* And bump the LRU for this access */ |
43566ded CW |
4092 | vma = i915_gem_obj_to_ggtt(obj); |
4093 | if (vma && drm_mm_node_allocated(&vma->node) && !obj->active) | |
1c7f4bca | 4094 | list_move_tail(&vma->vm_link, |
72e96d64 | 4095 | &ggtt->base.inactive_list); |
8325a09d | 4096 | |
e47c68e9 EA |
4097 | return 0; |
4098 | } | |
4099 | ||
ef55f92a CW |
4100 | /** |
4101 | * Changes the cache-level of an object across all VMA. | |
14bb2c11 TU |
4102 | * @obj: object to act on |
4103 | * @cache_level: new cache level to set for the object | |
ef55f92a CW |
4104 | * |
4105 | * After this function returns, the object will be in the new cache-level | |
4106 | * across all GTT and the contents of the backing storage will be coherent, | |
4107 | * with respect to the new cache-level. In order to keep the backing storage | |
4108 | * coherent for all users, we only allow a single cache level to be set | |
4109 | * globally on the object and prevent it from being changed whilst the | |
4110 | * hardware is reading from the object. That is if the object is currently | |
4111 | * on the scanout it will be set to uncached (or equivalent display | |
4112 | * cache coherency) and all non-MOCS GPU access will also be uncached so | |
4113 | * that all direct access to the scanout remains coherent. | |
4114 | */ | |
e4ffd173 CW |
4115 | int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj, |
4116 | enum i915_cache_level cache_level) | |
4117 | { | |
7bddb01f | 4118 | struct drm_device *dev = obj->base.dev; |
df6f783a | 4119 | struct i915_vma *vma, *next; |
ef55f92a | 4120 | bool bound = false; |
ed75a55b | 4121 | int ret = 0; |
e4ffd173 CW |
4122 | |
4123 | if (obj->cache_level == cache_level) | |
ed75a55b | 4124 | goto out; |
e4ffd173 | 4125 | |
ef55f92a CW |
4126 | /* Inspect the list of currently bound VMA and unbind any that would |
4127 | * be invalid given the new cache-level. This is principally to | |
4128 | * catch the issue of the CS prefetch crossing page boundaries and | |
4129 | * reading an invalid PTE on older architectures. | |
4130 | */ | |
1c7f4bca | 4131 | list_for_each_entry_safe(vma, next, &obj->vma_list, obj_link) { |
ef55f92a CW |
4132 | if (!drm_mm_node_allocated(&vma->node)) |
4133 | continue; | |
4134 | ||
4135 | if (vma->pin_count) { | |
4136 | DRM_DEBUG("can not change the cache level of pinned objects\n"); | |
4137 | return -EBUSY; | |
4138 | } | |
4139 | ||
4144f9b5 | 4140 | if (!i915_gem_valid_gtt_space(vma, cache_level)) { |
07fe0b12 | 4141 | ret = i915_vma_unbind(vma); |
3089c6f2 BW |
4142 | if (ret) |
4143 | return ret; | |
ef55f92a CW |
4144 | } else |
4145 | bound = true; | |
42d6ab48 CW |
4146 | } |
4147 | ||
ef55f92a CW |
4148 | /* We can reuse the existing drm_mm nodes but need to change the |
4149 | * cache-level on the PTE. We could simply unbind them all and | |
4150 | * rebind with the correct cache-level on next use. However since | |
4151 | * we already have a valid slot, dma mapping, pages etc, we may as | |
4152 | * rewrite the PTE in the belief that doing so tramples upon less | |
4153 | * state and so involves less work. | |
4154 | */ | |
4155 | if (bound) { | |
4156 | /* Before we change the PTE, the GPU must not be accessing it. | |
4157 | * If we wait upon the object, we know that all the bound | |
4158 | * VMA are no longer active. | |
4159 | */ | |
2e2f351d | 4160 | ret = i915_gem_object_wait_rendering(obj, false); |
e4ffd173 CW |
4161 | if (ret) |
4162 | return ret; | |
4163 | ||
ef55f92a CW |
4164 | if (!HAS_LLC(dev) && cache_level != I915_CACHE_NONE) { |
4165 | /* Access to snoopable pages through the GTT is | |
4166 | * incoherent and on some machines causes a hard | |
4167 | * lockup. Relinquish the CPU mmaping to force | |
4168 | * userspace to refault in the pages and we can | |
4169 | * then double check if the GTT mapping is still | |
4170 | * valid for that pointer access. | |
4171 | */ | |
4172 | i915_gem_release_mmap(obj); | |
4173 | ||
4174 | /* As we no longer need a fence for GTT access, | |
4175 | * we can relinquish it now (and so prevent having | |
4176 | * to steal a fence from someone else on the next | |
4177 | * fence request). Note GPU activity would have | |
4178 | * dropped the fence as all snoopable access is | |
4179 | * supposed to be linear. | |
4180 | */ | |
e4ffd173 CW |
4181 | ret = i915_gem_object_put_fence(obj); |
4182 | if (ret) | |
4183 | return ret; | |
ef55f92a CW |
4184 | } else { |
4185 | /* We either have incoherent backing store and | |
4186 | * so no GTT access or the architecture is fully | |
4187 | * coherent. In such cases, existing GTT mmaps | |
4188 | * ignore the cache bit in the PTE and we can | |
4189 | * rewrite it without confusing the GPU or having | |
4190 | * to force userspace to fault back in its mmaps. | |
4191 | */ | |
e4ffd173 CW |
4192 | } |
4193 | ||
1c7f4bca | 4194 | list_for_each_entry(vma, &obj->vma_list, obj_link) { |
ef55f92a CW |
4195 | if (!drm_mm_node_allocated(&vma->node)) |
4196 | continue; | |
4197 | ||
4198 | ret = i915_vma_bind(vma, cache_level, PIN_UPDATE); | |
4199 | if (ret) | |
4200 | return ret; | |
4201 | } | |
e4ffd173 CW |
4202 | } |
4203 | ||
1c7f4bca | 4204 | list_for_each_entry(vma, &obj->vma_list, obj_link) |
2c22569b CW |
4205 | vma->node.color = cache_level; |
4206 | obj->cache_level = cache_level; | |
4207 | ||
ed75a55b | 4208 | out: |
ef55f92a CW |
4209 | /* Flush the dirty CPU caches to the backing storage so that the |
4210 | * object is now coherent at its new cache level (with respect | |
4211 | * to the access domain). | |
4212 | */ | |
b50a5371 | 4213 | if (obj->cache_dirty && cpu_write_needs_clflush(obj)) { |
0f71979a | 4214 | if (i915_gem_clflush_object(obj, true)) |
c033666a | 4215 | i915_gem_chipset_flush(to_i915(obj->base.dev)); |
e4ffd173 CW |
4216 | } |
4217 | ||
e4ffd173 CW |
4218 | return 0; |
4219 | } | |
4220 | ||
199adf40 BW |
4221 | int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data, |
4222 | struct drm_file *file) | |
e6994aee | 4223 | { |
199adf40 | 4224 | struct drm_i915_gem_caching *args = data; |
e6994aee | 4225 | struct drm_i915_gem_object *obj; |
e6994aee | 4226 | |
a8ad0bd8 | 4227 | obj = to_intel_bo(drm_gem_object_lookup(file, args->handle)); |
432be69d CW |
4228 | if (&obj->base == NULL) |
4229 | return -ENOENT; | |
e6994aee | 4230 | |
651d794f CW |
4231 | switch (obj->cache_level) { |
4232 | case I915_CACHE_LLC: | |
4233 | case I915_CACHE_L3_LLC: | |
4234 | args->caching = I915_CACHING_CACHED; | |
4235 | break; | |
4236 | ||
4257d3ba CW |
4237 | case I915_CACHE_WT: |
4238 | args->caching = I915_CACHING_DISPLAY; | |
4239 | break; | |
4240 | ||
651d794f CW |
4241 | default: |
4242 | args->caching = I915_CACHING_NONE; | |
4243 | break; | |
4244 | } | |
e6994aee | 4245 | |
432be69d CW |
4246 | drm_gem_object_unreference_unlocked(&obj->base); |
4247 | return 0; | |
e6994aee CW |
4248 | } |
4249 | ||
199adf40 BW |
4250 | int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data, |
4251 | struct drm_file *file) | |
e6994aee | 4252 | { |
fac5e23e | 4253 | struct drm_i915_private *dev_priv = to_i915(dev); |
199adf40 | 4254 | struct drm_i915_gem_caching *args = data; |
e6994aee CW |
4255 | struct drm_i915_gem_object *obj; |
4256 | enum i915_cache_level level; | |
4257 | int ret; | |
4258 | ||
199adf40 BW |
4259 | switch (args->caching) { |
4260 | case I915_CACHING_NONE: | |
e6994aee CW |
4261 | level = I915_CACHE_NONE; |
4262 | break; | |
199adf40 | 4263 | case I915_CACHING_CACHED: |
e5756c10 ID |
4264 | /* |
4265 | * Due to a HW issue on BXT A stepping, GPU stores via a | |
4266 | * snooped mapping may leave stale data in a corresponding CPU | |
4267 | * cacheline, whereas normally such cachelines would get | |
4268 | * invalidated. | |
4269 | */ | |
ca377809 | 4270 | if (!HAS_LLC(dev) && !HAS_SNOOP(dev)) |
e5756c10 ID |
4271 | return -ENODEV; |
4272 | ||
e6994aee CW |
4273 | level = I915_CACHE_LLC; |
4274 | break; | |
4257d3ba CW |
4275 | case I915_CACHING_DISPLAY: |
4276 | level = HAS_WT(dev) ? I915_CACHE_WT : I915_CACHE_NONE; | |
4277 | break; | |
e6994aee CW |
4278 | default: |
4279 | return -EINVAL; | |
4280 | } | |
4281 | ||
fd0fe6ac ID |
4282 | intel_runtime_pm_get(dev_priv); |
4283 | ||
3bc2913e BW |
4284 | ret = i915_mutex_lock_interruptible(dev); |
4285 | if (ret) | |
fd0fe6ac | 4286 | goto rpm_put; |
3bc2913e | 4287 | |
a8ad0bd8 | 4288 | obj = to_intel_bo(drm_gem_object_lookup(file, args->handle)); |
e6994aee CW |
4289 | if (&obj->base == NULL) { |
4290 | ret = -ENOENT; | |
4291 | goto unlock; | |
4292 | } | |
4293 | ||
4294 | ret = i915_gem_object_set_cache_level(obj, level); | |
4295 | ||
4296 | drm_gem_object_unreference(&obj->base); | |
4297 | unlock: | |
4298 | mutex_unlock(&dev->struct_mutex); | |
fd0fe6ac ID |
4299 | rpm_put: |
4300 | intel_runtime_pm_put(dev_priv); | |
4301 | ||
e6994aee CW |
4302 | return ret; |
4303 | } | |
4304 | ||
b9241ea3 | 4305 | /* |
2da3b9b9 CW |
4306 | * Prepare buffer for display plane (scanout, cursors, etc). |
4307 | * Can be called from an uninterruptible phase (modesetting) and allows | |
4308 | * any flushes to be pipelined (for pageflips). | |
b9241ea3 ZW |
4309 | */ |
4310 | int | |
2da3b9b9 CW |
4311 | i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj, |
4312 | u32 alignment, | |
e6617330 | 4313 | const struct i915_ggtt_view *view) |
b9241ea3 | 4314 | { |
2da3b9b9 | 4315 | u32 old_read_domains, old_write_domain; |
b9241ea3 ZW |
4316 | int ret; |
4317 | ||
cc98b413 CW |
4318 | /* Mark the pin_display early so that we account for the |
4319 | * display coherency whilst setting up the cache domains. | |
4320 | */ | |
8a0c39b1 | 4321 | obj->pin_display++; |
cc98b413 | 4322 | |
a7ef0640 EA |
4323 | /* The display engine is not coherent with the LLC cache on gen6. As |
4324 | * a result, we make sure that the pinning that is about to occur is | |
4325 | * done with uncached PTEs. This is lowest common denominator for all | |
4326 | * chipsets. | |
4327 | * | |
4328 | * However for gen6+, we could do better by using the GFDT bit instead | |
4329 | * of uncaching, which would allow us to flush all the LLC-cached data | |
4330 | * with that bit in the PTE to main memory with just one PIPE_CONTROL. | |
4331 | */ | |
651d794f CW |
4332 | ret = i915_gem_object_set_cache_level(obj, |
4333 | HAS_WT(obj->base.dev) ? I915_CACHE_WT : I915_CACHE_NONE); | |
a7ef0640 | 4334 | if (ret) |
cc98b413 | 4335 | goto err_unpin_display; |
a7ef0640 | 4336 | |
2da3b9b9 CW |
4337 | /* As the user may map the buffer once pinned in the display plane |
4338 | * (e.g. libkms for the bootup splash), we have to ensure that we | |
4339 | * always use map_and_fenceable for all scanout buffers. | |
4340 | */ | |
50470bb0 TU |
4341 | ret = i915_gem_object_ggtt_pin(obj, view, alignment, |
4342 | view->type == I915_GGTT_VIEW_NORMAL ? | |
4343 | PIN_MAPPABLE : 0); | |
2da3b9b9 | 4344 | if (ret) |
cc98b413 | 4345 | goto err_unpin_display; |
2da3b9b9 | 4346 | |
e62b59e4 | 4347 | i915_gem_object_flush_cpu_write_domain(obj); |
b118c1e3 | 4348 | |
2da3b9b9 | 4349 | old_write_domain = obj->base.write_domain; |
05394f39 | 4350 | old_read_domains = obj->base.read_domains; |
2da3b9b9 CW |
4351 | |
4352 | /* It should now be out of any other write domains, and we can update | |
4353 | * the domain values for our changes. | |
4354 | */ | |
e5f1d962 | 4355 | obj->base.write_domain = 0; |
05394f39 | 4356 | obj->base.read_domains |= I915_GEM_DOMAIN_GTT; |
b9241ea3 ZW |
4357 | |
4358 | trace_i915_gem_object_change_domain(obj, | |
4359 | old_read_domains, | |
2da3b9b9 | 4360 | old_write_domain); |
b9241ea3 ZW |
4361 | |
4362 | return 0; | |
cc98b413 CW |
4363 | |
4364 | err_unpin_display: | |
8a0c39b1 | 4365 | obj->pin_display--; |
cc98b413 CW |
4366 | return ret; |
4367 | } | |
4368 | ||
4369 | void | |
e6617330 TU |
4370 | i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object *obj, |
4371 | const struct i915_ggtt_view *view) | |
cc98b413 | 4372 | { |
8a0c39b1 TU |
4373 | if (WARN_ON(obj->pin_display == 0)) |
4374 | return; | |
4375 | ||
e6617330 TU |
4376 | i915_gem_object_ggtt_unpin_view(obj, view); |
4377 | ||
8a0c39b1 | 4378 | obj->pin_display--; |
b9241ea3 ZW |
4379 | } |
4380 | ||
e47c68e9 EA |
4381 | /** |
4382 | * Moves a single object to the CPU read, and possibly write domain. | |
14bb2c11 TU |
4383 | * @obj: object to act on |
4384 | * @write: requesting write or read-only access | |
e47c68e9 EA |
4385 | * |
4386 | * This function returns when the move is complete, including waiting on | |
4387 | * flushes to occur. | |
4388 | */ | |
dabdfe02 | 4389 | int |
919926ae | 4390 | i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write) |
e47c68e9 | 4391 | { |
1c5d22f7 | 4392 | uint32_t old_write_domain, old_read_domains; |
e47c68e9 EA |
4393 | int ret; |
4394 | ||
8d7e3de1 CW |
4395 | if (obj->base.write_domain == I915_GEM_DOMAIN_CPU) |
4396 | return 0; | |
4397 | ||
0201f1ec | 4398 | ret = i915_gem_object_wait_rendering(obj, !write); |
88241785 CW |
4399 | if (ret) |
4400 | return ret; | |
4401 | ||
e47c68e9 | 4402 | i915_gem_object_flush_gtt_write_domain(obj); |
2ef7eeaa | 4403 | |
05394f39 CW |
4404 | old_write_domain = obj->base.write_domain; |
4405 | old_read_domains = obj->base.read_domains; | |
1c5d22f7 | 4406 | |
e47c68e9 | 4407 | /* Flush the CPU cache if it's still invalid. */ |
05394f39 | 4408 | if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) { |
2c22569b | 4409 | i915_gem_clflush_object(obj, false); |
2ef7eeaa | 4410 | |
05394f39 | 4411 | obj->base.read_domains |= I915_GEM_DOMAIN_CPU; |
2ef7eeaa EA |
4412 | } |
4413 | ||
4414 | /* It should now be out of any other write domains, and we can update | |
4415 | * the domain values for our changes. | |
4416 | */ | |
05394f39 | 4417 | BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) != 0); |
e47c68e9 EA |
4418 | |
4419 | /* If we're writing through the CPU, then the GPU read domains will | |
4420 | * need to be invalidated at next use. | |
4421 | */ | |
4422 | if (write) { | |
05394f39 CW |
4423 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; |
4424 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; | |
e47c68e9 | 4425 | } |
2ef7eeaa | 4426 | |
1c5d22f7 CW |
4427 | trace_i915_gem_object_change_domain(obj, |
4428 | old_read_domains, | |
4429 | old_write_domain); | |
4430 | ||
2ef7eeaa EA |
4431 | return 0; |
4432 | } | |
4433 | ||
673a394b EA |
4434 | /* Throttle our rendering by waiting until the ring has completed our requests |
4435 | * emitted over 20 msec ago. | |
4436 | * | |
b962442e EA |
4437 | * Note that if we were to use the current jiffies each time around the loop, |
4438 | * we wouldn't escape the function with any frames outstanding if the time to | |
4439 | * render a frame was over 20ms. | |
4440 | * | |
673a394b EA |
4441 | * This should get us reasonable parallelism between CPU and GPU but also |
4442 | * relatively low latency when blocking on a particular request to finish. | |
4443 | */ | |
40a5f0de | 4444 | static int |
f787a5f5 | 4445 | i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file) |
40a5f0de | 4446 | { |
fac5e23e | 4447 | struct drm_i915_private *dev_priv = to_i915(dev); |
f787a5f5 | 4448 | struct drm_i915_file_private *file_priv = file->driver_priv; |
d0bc54f2 | 4449 | unsigned long recent_enough = jiffies - DRM_I915_THROTTLE_JIFFIES; |
54fb2411 | 4450 | struct drm_i915_gem_request *request, *target = NULL; |
f787a5f5 | 4451 | int ret; |
93533c29 | 4452 | |
308887aa DV |
4453 | ret = i915_gem_wait_for_error(&dev_priv->gpu_error); |
4454 | if (ret) | |
4455 | return ret; | |
4456 | ||
f4457ae7 CW |
4457 | /* ABI: return -EIO if already wedged */ |
4458 | if (i915_terminally_wedged(&dev_priv->gpu_error)) | |
4459 | return -EIO; | |
e110e8d6 | 4460 | |
1c25595f | 4461 | spin_lock(&file_priv->mm.lock); |
f787a5f5 | 4462 | list_for_each_entry(request, &file_priv->mm.request_list, client_list) { |
b962442e EA |
4463 | if (time_after_eq(request->emitted_jiffies, recent_enough)) |
4464 | break; | |
40a5f0de | 4465 | |
fcfa423c JH |
4466 | /* |
4467 | * Note that the request might not have been submitted yet. | |
4468 | * In which case emitted_jiffies will be zero. | |
4469 | */ | |
4470 | if (!request->emitted_jiffies) | |
4471 | continue; | |
4472 | ||
54fb2411 | 4473 | target = request; |
b962442e | 4474 | } |
ff865885 JH |
4475 | if (target) |
4476 | i915_gem_request_reference(target); | |
1c25595f | 4477 | spin_unlock(&file_priv->mm.lock); |
40a5f0de | 4478 | |
54fb2411 | 4479 | if (target == NULL) |
f787a5f5 | 4480 | return 0; |
2bc43b5c | 4481 | |
299259a3 | 4482 | ret = __i915_wait_request(target, true, NULL, NULL); |
73db04cf | 4483 | i915_gem_request_unreference(target); |
ff865885 | 4484 | |
40a5f0de EA |
4485 | return ret; |
4486 | } | |
4487 | ||
d23db88c CW |
4488 | static bool |
4489 | i915_vma_misplaced(struct i915_vma *vma, uint32_t alignment, uint64_t flags) | |
4490 | { | |
4491 | struct drm_i915_gem_object *obj = vma->obj; | |
4492 | ||
4493 | if (alignment && | |
4494 | vma->node.start & (alignment - 1)) | |
4495 | return true; | |
4496 | ||
4497 | if (flags & PIN_MAPPABLE && !obj->map_and_fenceable) | |
4498 | return true; | |
4499 | ||
4500 | if (flags & PIN_OFFSET_BIAS && | |
4501 | vma->node.start < (flags & PIN_OFFSET_MASK)) | |
4502 | return true; | |
4503 | ||
506a8e87 CW |
4504 | if (flags & PIN_OFFSET_FIXED && |
4505 | vma->node.start != (flags & PIN_OFFSET_MASK)) | |
4506 | return true; | |
4507 | ||
d23db88c CW |
4508 | return false; |
4509 | } | |
4510 | ||
d0710abb CW |
4511 | void __i915_vma_set_map_and_fenceable(struct i915_vma *vma) |
4512 | { | |
4513 | struct drm_i915_gem_object *obj = vma->obj; | |
4514 | bool mappable, fenceable; | |
4515 | u32 fence_size, fence_alignment; | |
4516 | ||
4517 | fence_size = i915_gem_get_gtt_size(obj->base.dev, | |
4518 | obj->base.size, | |
4519 | obj->tiling_mode); | |
4520 | fence_alignment = i915_gem_get_gtt_alignment(obj->base.dev, | |
4521 | obj->base.size, | |
4522 | obj->tiling_mode, | |
4523 | true); | |
4524 | ||
4525 | fenceable = (vma->node.size == fence_size && | |
4526 | (vma->node.start & (fence_alignment - 1)) == 0); | |
4527 | ||
4528 | mappable = (vma->node.start + fence_size <= | |
62106b4f | 4529 | to_i915(obj->base.dev)->ggtt.mappable_end); |
d0710abb CW |
4530 | |
4531 | obj->map_and_fenceable = mappable && fenceable; | |
4532 | } | |
4533 | ||
ec7adb6e JL |
4534 | static int |
4535 | i915_gem_object_do_pin(struct drm_i915_gem_object *obj, | |
4536 | struct i915_address_space *vm, | |
4537 | const struct i915_ggtt_view *ggtt_view, | |
4538 | uint32_t alignment, | |
4539 | uint64_t flags) | |
673a394b | 4540 | { |
fac5e23e | 4541 | struct drm_i915_private *dev_priv = to_i915(obj->base.dev); |
07fe0b12 | 4542 | struct i915_vma *vma; |
ef79e17c | 4543 | unsigned bound; |
673a394b EA |
4544 | int ret; |
4545 | ||
6e7186af BW |
4546 | if (WARN_ON(vm == &dev_priv->mm.aliasing_ppgtt->base)) |
4547 | return -ENODEV; | |
4548 | ||
bf3d149b | 4549 | if (WARN_ON(flags & (PIN_GLOBAL | PIN_MAPPABLE) && !i915_is_ggtt(vm))) |
1ec9e26d | 4550 | return -EINVAL; |
07fe0b12 | 4551 | |
c826c449 CW |
4552 | if (WARN_ON((flags & (PIN_MAPPABLE | PIN_GLOBAL)) == PIN_MAPPABLE)) |
4553 | return -EINVAL; | |
4554 | ||
ec7adb6e JL |
4555 | if (WARN_ON(i915_is_ggtt(vm) != !!ggtt_view)) |
4556 | return -EINVAL; | |
4557 | ||
4558 | vma = ggtt_view ? i915_gem_obj_to_ggtt_view(obj, ggtt_view) : | |
4559 | i915_gem_obj_to_vma(obj, vm); | |
4560 | ||
07fe0b12 | 4561 | if (vma) { |
d7f46fc4 BW |
4562 | if (WARN_ON(vma->pin_count == DRM_I915_GEM_OBJECT_MAX_PIN_COUNT)) |
4563 | return -EBUSY; | |
4564 | ||
d23db88c | 4565 | if (i915_vma_misplaced(vma, alignment, flags)) { |
d7f46fc4 | 4566 | WARN(vma->pin_count, |
ec7adb6e | 4567 | "bo is already pinned in %s with incorrect alignment:" |
088e0df4 | 4568 | " offset=%08x %08x, req.alignment=%x, req.map_and_fenceable=%d," |
75e9e915 | 4569 | " obj->map_and_fenceable=%d\n", |
ec7adb6e | 4570 | ggtt_view ? "ggtt" : "ppgtt", |
088e0df4 MT |
4571 | upper_32_bits(vma->node.start), |
4572 | lower_32_bits(vma->node.start), | |
fe14d5f4 | 4573 | alignment, |
d23db88c | 4574 | !!(flags & PIN_MAPPABLE), |
05394f39 | 4575 | obj->map_and_fenceable); |
07fe0b12 | 4576 | ret = i915_vma_unbind(vma); |
ac0c6b5a CW |
4577 | if (ret) |
4578 | return ret; | |
8ea99c92 DV |
4579 | |
4580 | vma = NULL; | |
ac0c6b5a CW |
4581 | } |
4582 | } | |
4583 | ||
ef79e17c | 4584 | bound = vma ? vma->bound : 0; |
8ea99c92 | 4585 | if (vma == NULL || !drm_mm_node_allocated(&vma->node)) { |
ec7adb6e JL |
4586 | vma = i915_gem_object_bind_to_vm(obj, vm, ggtt_view, alignment, |
4587 | flags); | |
262de145 DV |
4588 | if (IS_ERR(vma)) |
4589 | return PTR_ERR(vma); | |
0875546c DV |
4590 | } else { |
4591 | ret = i915_vma_bind(vma, obj->cache_level, flags); | |
fe14d5f4 TU |
4592 | if (ret) |
4593 | return ret; | |
4594 | } | |
74898d7e | 4595 | |
91e6711e JL |
4596 | if (ggtt_view && ggtt_view->type == I915_GGTT_VIEW_NORMAL && |
4597 | (bound ^ vma->bound) & GLOBAL_BIND) { | |
d0710abb | 4598 | __i915_vma_set_map_and_fenceable(vma); |
91e6711e JL |
4599 | WARN_ON(flags & PIN_MAPPABLE && !obj->map_and_fenceable); |
4600 | } | |
ef79e17c | 4601 | |
8ea99c92 | 4602 | vma->pin_count++; |
673a394b EA |
4603 | return 0; |
4604 | } | |
4605 | ||
ec7adb6e JL |
4606 | int |
4607 | i915_gem_object_pin(struct drm_i915_gem_object *obj, | |
4608 | struct i915_address_space *vm, | |
4609 | uint32_t alignment, | |
4610 | uint64_t flags) | |
4611 | { | |
4612 | return i915_gem_object_do_pin(obj, vm, | |
4613 | i915_is_ggtt(vm) ? &i915_ggtt_view_normal : NULL, | |
4614 | alignment, flags); | |
4615 | } | |
4616 | ||
4617 | int | |
4618 | i915_gem_object_ggtt_pin(struct drm_i915_gem_object *obj, | |
4619 | const struct i915_ggtt_view *view, | |
4620 | uint32_t alignment, | |
4621 | uint64_t flags) | |
4622 | { | |
72e96d64 JL |
4623 | struct drm_device *dev = obj->base.dev; |
4624 | struct drm_i915_private *dev_priv = to_i915(dev); | |
4625 | struct i915_ggtt *ggtt = &dev_priv->ggtt; | |
4626 | ||
ade7daa1 | 4627 | BUG_ON(!view); |
ec7adb6e | 4628 | |
72e96d64 | 4629 | return i915_gem_object_do_pin(obj, &ggtt->base, view, |
6fafab76 | 4630 | alignment, flags | PIN_GLOBAL); |
ec7adb6e JL |
4631 | } |
4632 | ||
673a394b | 4633 | void |
e6617330 TU |
4634 | i915_gem_object_ggtt_unpin_view(struct drm_i915_gem_object *obj, |
4635 | const struct i915_ggtt_view *view) | |
673a394b | 4636 | { |
e6617330 | 4637 | struct i915_vma *vma = i915_gem_obj_to_ggtt_view(obj, view); |
673a394b | 4638 | |
e6617330 | 4639 | WARN_ON(vma->pin_count == 0); |
9abc4648 | 4640 | WARN_ON(!i915_gem_obj_ggtt_bound_view(obj, view)); |
d7f46fc4 | 4641 | |
30154650 | 4642 | --vma->pin_count; |
673a394b EA |
4643 | } |
4644 | ||
673a394b EA |
4645 | int |
4646 | i915_gem_busy_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 4647 | struct drm_file *file) |
673a394b EA |
4648 | { |
4649 | struct drm_i915_gem_busy *args = data; | |
05394f39 | 4650 | struct drm_i915_gem_object *obj; |
30dbf0c0 CW |
4651 | int ret; |
4652 | ||
76c1dec1 | 4653 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 4654 | if (ret) |
76c1dec1 | 4655 | return ret; |
673a394b | 4656 | |
a8ad0bd8 | 4657 | obj = to_intel_bo(drm_gem_object_lookup(file, args->handle)); |
c8725226 | 4658 | if (&obj->base == NULL) { |
1d7cfea1 CW |
4659 | ret = -ENOENT; |
4660 | goto unlock; | |
673a394b | 4661 | } |
d1b851fc | 4662 | |
0be555b6 CW |
4663 | /* Count all active objects as busy, even if they are currently not used |
4664 | * by the gpu. Users of this interface expect objects to eventually | |
4665 | * become non-busy without any further actions, therefore emit any | |
4666 | * necessary flushes here. | |
c4de0a5d | 4667 | */ |
30dfebf3 | 4668 | ret = i915_gem_object_flush_active(obj); |
b4716185 CW |
4669 | if (ret) |
4670 | goto unref; | |
0be555b6 | 4671 | |
426960be CW |
4672 | args->busy = 0; |
4673 | if (obj->active) { | |
4674 | int i; | |
4675 | ||
666796da | 4676 | for (i = 0; i < I915_NUM_ENGINES; i++) { |
426960be CW |
4677 | struct drm_i915_gem_request *req; |
4678 | ||
4679 | req = obj->last_read_req[i]; | |
4680 | if (req) | |
4a570db5 | 4681 | args->busy |= 1 << (16 + req->engine->exec_id); |
426960be CW |
4682 | } |
4683 | if (obj->last_write_req) | |
4a570db5 | 4684 | args->busy |= obj->last_write_req->engine->exec_id; |
426960be | 4685 | } |
673a394b | 4686 | |
b4716185 | 4687 | unref: |
05394f39 | 4688 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 4689 | unlock: |
673a394b | 4690 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 4691 | return ret; |
673a394b EA |
4692 | } |
4693 | ||
4694 | int | |
4695 | i915_gem_throttle_ioctl(struct drm_device *dev, void *data, | |
4696 | struct drm_file *file_priv) | |
4697 | { | |
0206e353 | 4698 | return i915_gem_ring_throttle(dev, file_priv); |
673a394b EA |
4699 | } |
4700 | ||
3ef94daa CW |
4701 | int |
4702 | i915_gem_madvise_ioctl(struct drm_device *dev, void *data, | |
4703 | struct drm_file *file_priv) | |
4704 | { | |
fac5e23e | 4705 | struct drm_i915_private *dev_priv = to_i915(dev); |
3ef94daa | 4706 | struct drm_i915_gem_madvise *args = data; |
05394f39 | 4707 | struct drm_i915_gem_object *obj; |
76c1dec1 | 4708 | int ret; |
3ef94daa CW |
4709 | |
4710 | switch (args->madv) { | |
4711 | case I915_MADV_DONTNEED: | |
4712 | case I915_MADV_WILLNEED: | |
4713 | break; | |
4714 | default: | |
4715 | return -EINVAL; | |
4716 | } | |
4717 | ||
1d7cfea1 CW |
4718 | ret = i915_mutex_lock_interruptible(dev); |
4719 | if (ret) | |
4720 | return ret; | |
4721 | ||
a8ad0bd8 | 4722 | obj = to_intel_bo(drm_gem_object_lookup(file_priv, args->handle)); |
c8725226 | 4723 | if (&obj->base == NULL) { |
1d7cfea1 CW |
4724 | ret = -ENOENT; |
4725 | goto unlock; | |
3ef94daa | 4726 | } |
3ef94daa | 4727 | |
d7f46fc4 | 4728 | if (i915_gem_obj_is_pinned(obj)) { |
1d7cfea1 CW |
4729 | ret = -EINVAL; |
4730 | goto out; | |
3ef94daa CW |
4731 | } |
4732 | ||
656bfa3a DV |
4733 | if (obj->pages && |
4734 | obj->tiling_mode != I915_TILING_NONE && | |
4735 | dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES) { | |
4736 | if (obj->madv == I915_MADV_WILLNEED) | |
4737 | i915_gem_object_unpin_pages(obj); | |
4738 | if (args->madv == I915_MADV_WILLNEED) | |
4739 | i915_gem_object_pin_pages(obj); | |
4740 | } | |
4741 | ||
05394f39 CW |
4742 | if (obj->madv != __I915_MADV_PURGED) |
4743 | obj->madv = args->madv; | |
3ef94daa | 4744 | |
6c085a72 | 4745 | /* if the object is no longer attached, discard its backing storage */ |
be6a0376 | 4746 | if (obj->madv == I915_MADV_DONTNEED && obj->pages == NULL) |
2d7ef395 CW |
4747 | i915_gem_object_truncate(obj); |
4748 | ||
05394f39 | 4749 | args->retained = obj->madv != __I915_MADV_PURGED; |
bb6baf76 | 4750 | |
1d7cfea1 | 4751 | out: |
05394f39 | 4752 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 4753 | unlock: |
3ef94daa | 4754 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 4755 | return ret; |
3ef94daa CW |
4756 | } |
4757 | ||
37e680a1 CW |
4758 | void i915_gem_object_init(struct drm_i915_gem_object *obj, |
4759 | const struct drm_i915_gem_object_ops *ops) | |
0327d6ba | 4760 | { |
b4716185 CW |
4761 | int i; |
4762 | ||
35c20a60 | 4763 | INIT_LIST_HEAD(&obj->global_list); |
666796da | 4764 | for (i = 0; i < I915_NUM_ENGINES; i++) |
117897f4 | 4765 | INIT_LIST_HEAD(&obj->engine_list[i]); |
b25cb2f8 | 4766 | INIT_LIST_HEAD(&obj->obj_exec_link); |
2f633156 | 4767 | INIT_LIST_HEAD(&obj->vma_list); |
8d9d5744 | 4768 | INIT_LIST_HEAD(&obj->batch_pool_link); |
0327d6ba | 4769 | |
37e680a1 CW |
4770 | obj->ops = ops; |
4771 | ||
0327d6ba CW |
4772 | obj->fence_reg = I915_FENCE_REG_NONE; |
4773 | obj->madv = I915_MADV_WILLNEED; | |
0327d6ba | 4774 | |
f19ec8cb | 4775 | i915_gem_info_add_obj(to_i915(obj->base.dev), obj->base.size); |
0327d6ba CW |
4776 | } |
4777 | ||
37e680a1 | 4778 | static const struct drm_i915_gem_object_ops i915_gem_object_ops = { |
de472664 | 4779 | .flags = I915_GEM_OBJECT_HAS_STRUCT_PAGE, |
37e680a1 CW |
4780 | .get_pages = i915_gem_object_get_pages_gtt, |
4781 | .put_pages = i915_gem_object_put_pages_gtt, | |
4782 | }; | |
4783 | ||
d37cd8a8 | 4784 | struct drm_i915_gem_object *i915_gem_object_create(struct drm_device *dev, |
05394f39 | 4785 | size_t size) |
ac52bc56 | 4786 | { |
c397b908 | 4787 | struct drm_i915_gem_object *obj; |
5949eac4 | 4788 | struct address_space *mapping; |
1a240d4d | 4789 | gfp_t mask; |
fe3db79b | 4790 | int ret; |
ac52bc56 | 4791 | |
42dcedd4 | 4792 | obj = i915_gem_object_alloc(dev); |
c397b908 | 4793 | if (obj == NULL) |
fe3db79b | 4794 | return ERR_PTR(-ENOMEM); |
673a394b | 4795 | |
fe3db79b CW |
4796 | ret = drm_gem_object_init(dev, &obj->base, size); |
4797 | if (ret) | |
4798 | goto fail; | |
673a394b | 4799 | |
bed1ea95 CW |
4800 | mask = GFP_HIGHUSER | __GFP_RECLAIMABLE; |
4801 | if (IS_CRESTLINE(dev) || IS_BROADWATER(dev)) { | |
4802 | /* 965gm cannot relocate objects above 4GiB. */ | |
4803 | mask &= ~__GFP_HIGHMEM; | |
4804 | mask |= __GFP_DMA32; | |
4805 | } | |
4806 | ||
496ad9aa | 4807 | mapping = file_inode(obj->base.filp)->i_mapping; |
bed1ea95 | 4808 | mapping_set_gfp_mask(mapping, mask); |
5949eac4 | 4809 | |
37e680a1 | 4810 | i915_gem_object_init(obj, &i915_gem_object_ops); |
73aa808f | 4811 | |
c397b908 DV |
4812 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; |
4813 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; | |
673a394b | 4814 | |
3d29b842 ED |
4815 | if (HAS_LLC(dev)) { |
4816 | /* On some devices, we can have the GPU use the LLC (the CPU | |
a1871112 EA |
4817 | * cache) for about a 10% performance improvement |
4818 | * compared to uncached. Graphics requests other than | |
4819 | * display scanout are coherent with the CPU in | |
4820 | * accessing this cache. This means in this mode we | |
4821 | * don't need to clflush on the CPU side, and on the | |
4822 | * GPU side we only need to flush internal caches to | |
4823 | * get data visible to the CPU. | |
4824 | * | |
4825 | * However, we maintain the display planes as UC, and so | |
4826 | * need to rebind when first used as such. | |
4827 | */ | |
4828 | obj->cache_level = I915_CACHE_LLC; | |
4829 | } else | |
4830 | obj->cache_level = I915_CACHE_NONE; | |
4831 | ||
d861e338 DV |
4832 | trace_i915_gem_object_create(obj); |
4833 | ||
05394f39 | 4834 | return obj; |
fe3db79b CW |
4835 | |
4836 | fail: | |
4837 | i915_gem_object_free(obj); | |
4838 | ||
4839 | return ERR_PTR(ret); | |
c397b908 DV |
4840 | } |
4841 | ||
340fbd8c CW |
4842 | static bool discard_backing_storage(struct drm_i915_gem_object *obj) |
4843 | { | |
4844 | /* If we are the last user of the backing storage (be it shmemfs | |
4845 | * pages or stolen etc), we know that the pages are going to be | |
4846 | * immediately released. In this case, we can then skip copying | |
4847 | * back the contents from the GPU. | |
4848 | */ | |
4849 | ||
4850 | if (obj->madv != I915_MADV_WILLNEED) | |
4851 | return false; | |
4852 | ||
4853 | if (obj->base.filp == NULL) | |
4854 | return true; | |
4855 | ||
4856 | /* At first glance, this looks racy, but then again so would be | |
4857 | * userspace racing mmap against close. However, the first external | |
4858 | * reference to the filp can only be obtained through the | |
4859 | * i915_gem_mmap_ioctl() which safeguards us against the user | |
4860 | * acquiring such a reference whilst we are in the middle of | |
4861 | * freeing the object. | |
4862 | */ | |
4863 | return atomic_long_read(&obj->base.filp->f_count) == 1; | |
4864 | } | |
4865 | ||
1488fc08 | 4866 | void i915_gem_free_object(struct drm_gem_object *gem_obj) |
673a394b | 4867 | { |
1488fc08 | 4868 | struct drm_i915_gem_object *obj = to_intel_bo(gem_obj); |
05394f39 | 4869 | struct drm_device *dev = obj->base.dev; |
fac5e23e | 4870 | struct drm_i915_private *dev_priv = to_i915(dev); |
07fe0b12 | 4871 | struct i915_vma *vma, *next; |
673a394b | 4872 | |
f65c9168 PZ |
4873 | intel_runtime_pm_get(dev_priv); |
4874 | ||
26e12f89 CW |
4875 | trace_i915_gem_object_destroy(obj); |
4876 | ||
1c7f4bca | 4877 | list_for_each_entry_safe(vma, next, &obj->vma_list, obj_link) { |
d7f46fc4 BW |
4878 | int ret; |
4879 | ||
4880 | vma->pin_count = 0; | |
4881 | ret = i915_vma_unbind(vma); | |
07fe0b12 BW |
4882 | if (WARN_ON(ret == -ERESTARTSYS)) { |
4883 | bool was_interruptible; | |
1488fc08 | 4884 | |
07fe0b12 BW |
4885 | was_interruptible = dev_priv->mm.interruptible; |
4886 | dev_priv->mm.interruptible = false; | |
1488fc08 | 4887 | |
07fe0b12 | 4888 | WARN_ON(i915_vma_unbind(vma)); |
1488fc08 | 4889 | |
07fe0b12 BW |
4890 | dev_priv->mm.interruptible = was_interruptible; |
4891 | } | |
1488fc08 CW |
4892 | } |
4893 | ||
1d64ae71 BW |
4894 | /* Stolen objects don't hold a ref, but do hold pin count. Fix that up |
4895 | * before progressing. */ | |
4896 | if (obj->stolen) | |
4897 | i915_gem_object_unpin_pages(obj); | |
4898 | ||
a071fa00 DV |
4899 | WARN_ON(obj->frontbuffer_bits); |
4900 | ||
656bfa3a DV |
4901 | if (obj->pages && obj->madv == I915_MADV_WILLNEED && |
4902 | dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES && | |
4903 | obj->tiling_mode != I915_TILING_NONE) | |
4904 | i915_gem_object_unpin_pages(obj); | |
4905 | ||
401c29f6 BW |
4906 | if (WARN_ON(obj->pages_pin_count)) |
4907 | obj->pages_pin_count = 0; | |
340fbd8c | 4908 | if (discard_backing_storage(obj)) |
5537252b | 4909 | obj->madv = I915_MADV_DONTNEED; |
37e680a1 | 4910 | i915_gem_object_put_pages(obj); |
d8cb5086 | 4911 | i915_gem_object_free_mmap_offset(obj); |
de151cf6 | 4912 | |
9da3da66 CW |
4913 | BUG_ON(obj->pages); |
4914 | ||
2f745ad3 CW |
4915 | if (obj->base.import_attach) |
4916 | drm_prime_gem_destroy(&obj->base, NULL); | |
de151cf6 | 4917 | |
5cc9ed4b CW |
4918 | if (obj->ops->release) |
4919 | obj->ops->release(obj); | |
4920 | ||
05394f39 CW |
4921 | drm_gem_object_release(&obj->base); |
4922 | i915_gem_info_remove_obj(dev_priv, obj->base.size); | |
c397b908 | 4923 | |
05394f39 | 4924 | kfree(obj->bit_17); |
42dcedd4 | 4925 | i915_gem_object_free(obj); |
f65c9168 PZ |
4926 | |
4927 | intel_runtime_pm_put(dev_priv); | |
673a394b EA |
4928 | } |
4929 | ||
ec7adb6e JL |
4930 | struct i915_vma *i915_gem_obj_to_vma(struct drm_i915_gem_object *obj, |
4931 | struct i915_address_space *vm) | |
e656a6cb DV |
4932 | { |
4933 | struct i915_vma *vma; | |
1c7f4bca | 4934 | list_for_each_entry(vma, &obj->vma_list, obj_link) { |
1b683729 TU |
4935 | if (vma->ggtt_view.type == I915_GGTT_VIEW_NORMAL && |
4936 | vma->vm == vm) | |
e656a6cb | 4937 | return vma; |
ec7adb6e JL |
4938 | } |
4939 | return NULL; | |
4940 | } | |
4941 | ||
4942 | struct i915_vma *i915_gem_obj_to_ggtt_view(struct drm_i915_gem_object *obj, | |
4943 | const struct i915_ggtt_view *view) | |
4944 | { | |
ec7adb6e | 4945 | struct i915_vma *vma; |
e656a6cb | 4946 | |
598b9ec8 | 4947 | GEM_BUG_ON(!view); |
ec7adb6e | 4948 | |
1c7f4bca | 4949 | list_for_each_entry(vma, &obj->vma_list, obj_link) |
598b9ec8 | 4950 | if (vma->is_ggtt && i915_ggtt_view_equal(&vma->ggtt_view, view)) |
ec7adb6e | 4951 | return vma; |
e656a6cb DV |
4952 | return NULL; |
4953 | } | |
4954 | ||
2f633156 BW |
4955 | void i915_gem_vma_destroy(struct i915_vma *vma) |
4956 | { | |
4957 | WARN_ON(vma->node.allocated); | |
aaa05667 CW |
4958 | |
4959 | /* Keep the vma as a placeholder in the execbuffer reservation lists */ | |
4960 | if (!list_empty(&vma->exec_list)) | |
4961 | return; | |
4962 | ||
596c5923 CW |
4963 | if (!vma->is_ggtt) |
4964 | i915_ppgtt_put(i915_vm_to_ppgtt(vma->vm)); | |
b9d06dd9 | 4965 | |
1c7f4bca | 4966 | list_del(&vma->obj_link); |
b93dab6e | 4967 | |
e20d2ab7 | 4968 | kmem_cache_free(to_i915(vma->obj->base.dev)->vmas, vma); |
2f633156 BW |
4969 | } |
4970 | ||
e3efda49 | 4971 | static void |
117897f4 | 4972 | i915_gem_stop_engines(struct drm_device *dev) |
e3efda49 | 4973 | { |
fac5e23e | 4974 | struct drm_i915_private *dev_priv = to_i915(dev); |
e2f80391 | 4975 | struct intel_engine_cs *engine; |
e3efda49 | 4976 | |
b4ac5afc | 4977 | for_each_engine(engine, dev_priv) |
117897f4 | 4978 | dev_priv->gt.stop_engine(engine); |
e3efda49 CW |
4979 | } |
4980 | ||
29105ccc | 4981 | int |
45c5f202 | 4982 | i915_gem_suspend(struct drm_device *dev) |
29105ccc | 4983 | { |
fac5e23e | 4984 | struct drm_i915_private *dev_priv = to_i915(dev); |
45c5f202 | 4985 | int ret = 0; |
28dfe52a | 4986 | |
45c5f202 | 4987 | mutex_lock(&dev->struct_mutex); |
6e5a5beb | 4988 | ret = i915_gem_wait_for_idle(dev_priv); |
f7403347 | 4989 | if (ret) |
45c5f202 | 4990 | goto err; |
f7403347 | 4991 | |
c033666a | 4992 | i915_gem_retire_requests(dev_priv); |
673a394b | 4993 | |
117897f4 | 4994 | i915_gem_stop_engines(dev); |
b2e862d0 | 4995 | i915_gem_context_lost(dev_priv); |
45c5f202 CW |
4996 | mutex_unlock(&dev->struct_mutex); |
4997 | ||
737b1506 | 4998 | cancel_delayed_work_sync(&dev_priv->gpu_error.hangcheck_work); |
67d97da3 CW |
4999 | cancel_delayed_work_sync(&dev_priv->gt.retire_work); |
5000 | flush_delayed_work(&dev_priv->gt.idle_work); | |
29105ccc | 5001 | |
bdcf120b CW |
5002 | /* Assert that we sucessfully flushed all the work and |
5003 | * reset the GPU back to its idle, low power state. | |
5004 | */ | |
67d97da3 | 5005 | WARN_ON(dev_priv->gt.awake); |
bdcf120b | 5006 | |
673a394b | 5007 | return 0; |
45c5f202 CW |
5008 | |
5009 | err: | |
5010 | mutex_unlock(&dev->struct_mutex); | |
5011 | return ret; | |
673a394b EA |
5012 | } |
5013 | ||
f691e2f4 DV |
5014 | void i915_gem_init_swizzling(struct drm_device *dev) |
5015 | { | |
fac5e23e | 5016 | struct drm_i915_private *dev_priv = to_i915(dev); |
f691e2f4 | 5017 | |
11782b02 | 5018 | if (INTEL_INFO(dev)->gen < 5 || |
f691e2f4 DV |
5019 | dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE) |
5020 | return; | |
5021 | ||
5022 | I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) | | |
5023 | DISP_TILE_SURFACE_SWIZZLING); | |
5024 | ||
11782b02 DV |
5025 | if (IS_GEN5(dev)) |
5026 | return; | |
5027 | ||
f691e2f4 DV |
5028 | I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_SWZCTL); |
5029 | if (IS_GEN6(dev)) | |
6b26c86d | 5030 | I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB)); |
8782e26c | 5031 | else if (IS_GEN7(dev)) |
6b26c86d | 5032 | I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB)); |
31a5336e BW |
5033 | else if (IS_GEN8(dev)) |
5034 | I915_WRITE(GAMTARBMODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_BDW)); | |
8782e26c BW |
5035 | else |
5036 | BUG(); | |
f691e2f4 | 5037 | } |
e21af88d | 5038 | |
81e7f200 VS |
5039 | static void init_unused_ring(struct drm_device *dev, u32 base) |
5040 | { | |
fac5e23e | 5041 | struct drm_i915_private *dev_priv = to_i915(dev); |
81e7f200 VS |
5042 | |
5043 | I915_WRITE(RING_CTL(base), 0); | |
5044 | I915_WRITE(RING_HEAD(base), 0); | |
5045 | I915_WRITE(RING_TAIL(base), 0); | |
5046 | I915_WRITE(RING_START(base), 0); | |
5047 | } | |
5048 | ||
5049 | static void init_unused_rings(struct drm_device *dev) | |
5050 | { | |
5051 | if (IS_I830(dev)) { | |
5052 | init_unused_ring(dev, PRB1_BASE); | |
5053 | init_unused_ring(dev, SRB0_BASE); | |
5054 | init_unused_ring(dev, SRB1_BASE); | |
5055 | init_unused_ring(dev, SRB2_BASE); | |
5056 | init_unused_ring(dev, SRB3_BASE); | |
5057 | } else if (IS_GEN2(dev)) { | |
5058 | init_unused_ring(dev, SRB0_BASE); | |
5059 | init_unused_ring(dev, SRB1_BASE); | |
5060 | } else if (IS_GEN3(dev)) { | |
5061 | init_unused_ring(dev, PRB1_BASE); | |
5062 | init_unused_ring(dev, PRB2_BASE); | |
5063 | } | |
5064 | } | |
5065 | ||
117897f4 | 5066 | int i915_gem_init_engines(struct drm_device *dev) |
8187a2b7 | 5067 | { |
fac5e23e | 5068 | struct drm_i915_private *dev_priv = to_i915(dev); |
8187a2b7 | 5069 | int ret; |
68f95ba9 | 5070 | |
5c1143bb | 5071 | ret = intel_init_render_ring_buffer(dev); |
68f95ba9 | 5072 | if (ret) |
b6913e4b | 5073 | return ret; |
68f95ba9 CW |
5074 | |
5075 | if (HAS_BSD(dev)) { | |
5c1143bb | 5076 | ret = intel_init_bsd_ring_buffer(dev); |
68f95ba9 CW |
5077 | if (ret) |
5078 | goto cleanup_render_ring; | |
d1b851fc | 5079 | } |
68f95ba9 | 5080 | |
d39398f5 | 5081 | if (HAS_BLT(dev)) { |
549f7365 CW |
5082 | ret = intel_init_blt_ring_buffer(dev); |
5083 | if (ret) | |
5084 | goto cleanup_bsd_ring; | |
5085 | } | |
5086 | ||
9a8a2213 BW |
5087 | if (HAS_VEBOX(dev)) { |
5088 | ret = intel_init_vebox_ring_buffer(dev); | |
5089 | if (ret) | |
5090 | goto cleanup_blt_ring; | |
5091 | } | |
5092 | ||
845f74a7 ZY |
5093 | if (HAS_BSD2(dev)) { |
5094 | ret = intel_init_bsd2_ring_buffer(dev); | |
5095 | if (ret) | |
5096 | goto cleanup_vebox_ring; | |
5097 | } | |
9a8a2213 | 5098 | |
4fc7c971 BW |
5099 | return 0; |
5100 | ||
9a8a2213 | 5101 | cleanup_vebox_ring: |
117897f4 | 5102 | intel_cleanup_engine(&dev_priv->engine[VECS]); |
4fc7c971 | 5103 | cleanup_blt_ring: |
117897f4 | 5104 | intel_cleanup_engine(&dev_priv->engine[BCS]); |
4fc7c971 | 5105 | cleanup_bsd_ring: |
117897f4 | 5106 | intel_cleanup_engine(&dev_priv->engine[VCS]); |
4fc7c971 | 5107 | cleanup_render_ring: |
117897f4 | 5108 | intel_cleanup_engine(&dev_priv->engine[RCS]); |
4fc7c971 BW |
5109 | |
5110 | return ret; | |
5111 | } | |
5112 | ||
5113 | int | |
5114 | i915_gem_init_hw(struct drm_device *dev) | |
5115 | { | |
fac5e23e | 5116 | struct drm_i915_private *dev_priv = to_i915(dev); |
e2f80391 | 5117 | struct intel_engine_cs *engine; |
d200cda6 | 5118 | int ret; |
4fc7c971 | 5119 | |
5e4f5189 CW |
5120 | /* Double layer security blanket, see i915_gem_init() */ |
5121 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); | |
5122 | ||
3accaf7e | 5123 | if (HAS_EDRAM(dev) && INTEL_GEN(dev_priv) < 9) |
05e21cc4 | 5124 | I915_WRITE(HSW_IDICR, I915_READ(HSW_IDICR) | IDIHASHMSK(0xf)); |
4fc7c971 | 5125 | |
0bf21347 VS |
5126 | if (IS_HASWELL(dev)) |
5127 | I915_WRITE(MI_PREDICATE_RESULT_2, IS_HSW_GT3(dev) ? | |
5128 | LOWER_SLICE_ENABLED : LOWER_SLICE_DISABLED); | |
9435373e | 5129 | |
88a2b2a3 | 5130 | if (HAS_PCH_NOP(dev)) { |
6ba844b0 DV |
5131 | if (IS_IVYBRIDGE(dev)) { |
5132 | u32 temp = I915_READ(GEN7_MSG_CTL); | |
5133 | temp &= ~(WAIT_FOR_PCH_FLR_ACK | WAIT_FOR_PCH_RESET_ACK); | |
5134 | I915_WRITE(GEN7_MSG_CTL, temp); | |
5135 | } else if (INTEL_INFO(dev)->gen >= 7) { | |
5136 | u32 temp = I915_READ(HSW_NDE_RSTWRN_OPT); | |
5137 | temp &= ~RESET_PCH_HANDSHAKE_ENABLE; | |
5138 | I915_WRITE(HSW_NDE_RSTWRN_OPT, temp); | |
5139 | } | |
88a2b2a3 BW |
5140 | } |
5141 | ||
4fc7c971 BW |
5142 | i915_gem_init_swizzling(dev); |
5143 | ||
d5abdfda DV |
5144 | /* |
5145 | * At least 830 can leave some of the unused rings | |
5146 | * "active" (ie. head != tail) after resume which | |
5147 | * will prevent c3 entry. Makes sure all unused rings | |
5148 | * are totally idle. | |
5149 | */ | |
5150 | init_unused_rings(dev); | |
5151 | ||
ed54c1a1 | 5152 | BUG_ON(!dev_priv->kernel_context); |
90638cc1 | 5153 | |
4ad2fd88 JH |
5154 | ret = i915_ppgtt_init_hw(dev); |
5155 | if (ret) { | |
5156 | DRM_ERROR("PPGTT enable HW failed %d\n", ret); | |
5157 | goto out; | |
5158 | } | |
5159 | ||
5160 | /* Need to do basic initialisation of all rings first: */ | |
b4ac5afc | 5161 | for_each_engine(engine, dev_priv) { |
e2f80391 | 5162 | ret = engine->init_hw(engine); |
35a57ffb | 5163 | if (ret) |
5e4f5189 | 5164 | goto out; |
35a57ffb | 5165 | } |
99433931 | 5166 | |
0ccdacf6 PA |
5167 | intel_mocs_init_l3cc_table(dev); |
5168 | ||
33a732f4 | 5169 | /* We can't enable contexts until all firmware is loaded */ |
e556f7c1 DG |
5170 | ret = intel_guc_setup(dev); |
5171 | if (ret) | |
5172 | goto out; | |
33a732f4 | 5173 | |
5e4f5189 CW |
5174 | out: |
5175 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); | |
2fa48d8d | 5176 | return ret; |
8187a2b7 ZN |
5177 | } |
5178 | ||
1070a42b CW |
5179 | int i915_gem_init(struct drm_device *dev) |
5180 | { | |
fac5e23e | 5181 | struct drm_i915_private *dev_priv = to_i915(dev); |
1070a42b CW |
5182 | int ret; |
5183 | ||
1070a42b | 5184 | mutex_lock(&dev->struct_mutex); |
d62b4892 | 5185 | |
a83014d3 | 5186 | if (!i915.enable_execlists) { |
f3dc74c0 | 5187 | dev_priv->gt.execbuf_submit = i915_gem_ringbuffer_submission; |
117897f4 TU |
5188 | dev_priv->gt.init_engines = i915_gem_init_engines; |
5189 | dev_priv->gt.cleanup_engine = intel_cleanup_engine; | |
5190 | dev_priv->gt.stop_engine = intel_stop_engine; | |
454afebd | 5191 | } else { |
f3dc74c0 | 5192 | dev_priv->gt.execbuf_submit = intel_execlists_submission; |
117897f4 TU |
5193 | dev_priv->gt.init_engines = intel_logical_rings_init; |
5194 | dev_priv->gt.cleanup_engine = intel_logical_ring_cleanup; | |
5195 | dev_priv->gt.stop_engine = intel_logical_ring_stop; | |
a83014d3 OM |
5196 | } |
5197 | ||
5e4f5189 CW |
5198 | /* This is just a security blanket to placate dragons. |
5199 | * On some systems, we very sporadically observe that the first TLBs | |
5200 | * used by the CS may be stale, despite us poking the TLB reset. If | |
5201 | * we hold the forcewake during initialisation these problems | |
5202 | * just magically go away. | |
5203 | */ | |
5204 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); | |
5205 | ||
72778cb2 | 5206 | i915_gem_init_userptr(dev_priv); |
d85489d3 | 5207 | i915_gem_init_ggtt(dev); |
d62b4892 | 5208 | |
2fa48d8d | 5209 | ret = i915_gem_context_init(dev); |
7bcc3777 JN |
5210 | if (ret) |
5211 | goto out_unlock; | |
2fa48d8d | 5212 | |
117897f4 | 5213 | ret = dev_priv->gt.init_engines(dev); |
35a57ffb | 5214 | if (ret) |
7bcc3777 | 5215 | goto out_unlock; |
2fa48d8d | 5216 | |
1070a42b | 5217 | ret = i915_gem_init_hw(dev); |
60990320 CW |
5218 | if (ret == -EIO) { |
5219 | /* Allow ring initialisation to fail by marking the GPU as | |
5220 | * wedged. But we only want to do this where the GPU is angry, | |
5221 | * for all other failure, such as an allocation failure, bail. | |
5222 | */ | |
5223 | DRM_ERROR("Failed to initialize GPU, declaring it wedged\n"); | |
805de8f4 | 5224 | atomic_or(I915_WEDGED, &dev_priv->gpu_error.reset_counter); |
60990320 | 5225 | ret = 0; |
1070a42b | 5226 | } |
7bcc3777 JN |
5227 | |
5228 | out_unlock: | |
5e4f5189 | 5229 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); |
60990320 | 5230 | mutex_unlock(&dev->struct_mutex); |
1070a42b | 5231 | |
60990320 | 5232 | return ret; |
1070a42b CW |
5233 | } |
5234 | ||
8187a2b7 | 5235 | void |
117897f4 | 5236 | i915_gem_cleanup_engines(struct drm_device *dev) |
8187a2b7 | 5237 | { |
fac5e23e | 5238 | struct drm_i915_private *dev_priv = to_i915(dev); |
e2f80391 | 5239 | struct intel_engine_cs *engine; |
8187a2b7 | 5240 | |
b4ac5afc | 5241 | for_each_engine(engine, dev_priv) |
117897f4 | 5242 | dev_priv->gt.cleanup_engine(engine); |
8187a2b7 ZN |
5243 | } |
5244 | ||
64193406 | 5245 | static void |
666796da | 5246 | init_engine_lists(struct intel_engine_cs *engine) |
64193406 | 5247 | { |
0bc40be8 TU |
5248 | INIT_LIST_HEAD(&engine->active_list); |
5249 | INIT_LIST_HEAD(&engine->request_list); | |
64193406 CW |
5250 | } |
5251 | ||
40ae4e16 ID |
5252 | void |
5253 | i915_gem_load_init_fences(struct drm_i915_private *dev_priv) | |
5254 | { | |
91c8a326 | 5255 | struct drm_device *dev = &dev_priv->drm; |
40ae4e16 ID |
5256 | |
5257 | if (INTEL_INFO(dev_priv)->gen >= 7 && !IS_VALLEYVIEW(dev_priv) && | |
5258 | !IS_CHERRYVIEW(dev_priv)) | |
5259 | dev_priv->num_fence_regs = 32; | |
5260 | else if (INTEL_INFO(dev_priv)->gen >= 4 || IS_I945G(dev_priv) || | |
5261 | IS_I945GM(dev_priv) || IS_G33(dev_priv)) | |
5262 | dev_priv->num_fence_regs = 16; | |
5263 | else | |
5264 | dev_priv->num_fence_regs = 8; | |
5265 | ||
c033666a | 5266 | if (intel_vgpu_active(dev_priv)) |
40ae4e16 ID |
5267 | dev_priv->num_fence_regs = |
5268 | I915_READ(vgtif_reg(avail_rs.fence_num)); | |
5269 | ||
5270 | /* Initialize fence registers to zero */ | |
5271 | i915_gem_restore_fences(dev); | |
5272 | ||
5273 | i915_gem_detect_bit_6_swizzle(dev); | |
5274 | } | |
5275 | ||
673a394b | 5276 | void |
d64aa096 | 5277 | i915_gem_load_init(struct drm_device *dev) |
673a394b | 5278 | { |
fac5e23e | 5279 | struct drm_i915_private *dev_priv = to_i915(dev); |
42dcedd4 CW |
5280 | int i; |
5281 | ||
efab6d8d | 5282 | dev_priv->objects = |
42dcedd4 CW |
5283 | kmem_cache_create("i915_gem_object", |
5284 | sizeof(struct drm_i915_gem_object), 0, | |
5285 | SLAB_HWCACHE_ALIGN, | |
5286 | NULL); | |
e20d2ab7 CW |
5287 | dev_priv->vmas = |
5288 | kmem_cache_create("i915_gem_vma", | |
5289 | sizeof(struct i915_vma), 0, | |
5290 | SLAB_HWCACHE_ALIGN, | |
5291 | NULL); | |
efab6d8d CW |
5292 | dev_priv->requests = |
5293 | kmem_cache_create("i915_gem_request", | |
5294 | sizeof(struct drm_i915_gem_request), 0, | |
5295 | SLAB_HWCACHE_ALIGN, | |
5296 | NULL); | |
673a394b | 5297 | |
fc8c067e | 5298 | INIT_LIST_HEAD(&dev_priv->vm_list); |
a33afea5 | 5299 | INIT_LIST_HEAD(&dev_priv->context_list); |
6c085a72 CW |
5300 | INIT_LIST_HEAD(&dev_priv->mm.unbound_list); |
5301 | INIT_LIST_HEAD(&dev_priv->mm.bound_list); | |
a09ba7fa | 5302 | INIT_LIST_HEAD(&dev_priv->mm.fence_list); |
666796da TU |
5303 | for (i = 0; i < I915_NUM_ENGINES; i++) |
5304 | init_engine_lists(&dev_priv->engine[i]); | |
4b9de737 | 5305 | for (i = 0; i < I915_MAX_NUM_FENCES; i++) |
007cc8ac | 5306 | INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list); |
67d97da3 | 5307 | INIT_DELAYED_WORK(&dev_priv->gt.retire_work, |
673a394b | 5308 | i915_gem_retire_work_handler); |
67d97da3 | 5309 | INIT_DELAYED_WORK(&dev_priv->gt.idle_work, |
b29c19b6 | 5310 | i915_gem_idle_work_handler); |
1f15b76f | 5311 | init_waitqueue_head(&dev_priv->gpu_error.wait_queue); |
1f83fee0 | 5312 | init_waitqueue_head(&dev_priv->gpu_error.reset_queue); |
31169714 | 5313 | |
72bfa19c CW |
5314 | dev_priv->relative_constants_mode = I915_EXEC_CONSTANTS_REL_GENERAL; |
5315 | ||
19b2dbde | 5316 | INIT_LIST_HEAD(&dev_priv->mm.fence_list); |
10ed13e4 | 5317 | |
6b95a207 | 5318 | init_waitqueue_head(&dev_priv->pending_flip_queue); |
17250b71 | 5319 | |
ce453d81 CW |
5320 | dev_priv->mm.interruptible = true; |
5321 | ||
f99d7069 | 5322 | mutex_init(&dev_priv->fb_tracking.lock); |
673a394b | 5323 | } |
71acb5eb | 5324 | |
d64aa096 ID |
5325 | void i915_gem_load_cleanup(struct drm_device *dev) |
5326 | { | |
5327 | struct drm_i915_private *dev_priv = to_i915(dev); | |
5328 | ||
5329 | kmem_cache_destroy(dev_priv->requests); | |
5330 | kmem_cache_destroy(dev_priv->vmas); | |
5331 | kmem_cache_destroy(dev_priv->objects); | |
5332 | } | |
5333 | ||
461fb99c CW |
5334 | int i915_gem_freeze_late(struct drm_i915_private *dev_priv) |
5335 | { | |
5336 | struct drm_i915_gem_object *obj; | |
5337 | ||
5338 | /* Called just before we write the hibernation image. | |
5339 | * | |
5340 | * We need to update the domain tracking to reflect that the CPU | |
5341 | * will be accessing all the pages to create and restore from the | |
5342 | * hibernation, and so upon restoration those pages will be in the | |
5343 | * CPU domain. | |
5344 | * | |
5345 | * To make sure the hibernation image contains the latest state, | |
5346 | * we update that state just before writing out the image. | |
5347 | */ | |
5348 | ||
5349 | list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) { | |
5350 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; | |
5351 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; | |
5352 | } | |
5353 | ||
5354 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) { | |
5355 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; | |
5356 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; | |
5357 | } | |
5358 | ||
5359 | return 0; | |
5360 | } | |
5361 | ||
f787a5f5 | 5362 | void i915_gem_release(struct drm_device *dev, struct drm_file *file) |
b962442e | 5363 | { |
f787a5f5 | 5364 | struct drm_i915_file_private *file_priv = file->driver_priv; |
b962442e EA |
5365 | |
5366 | /* Clean up our request list when the client is going away, so that | |
5367 | * later retire_requests won't dereference our soon-to-be-gone | |
5368 | * file_priv. | |
5369 | */ | |
1c25595f | 5370 | spin_lock(&file_priv->mm.lock); |
f787a5f5 CW |
5371 | while (!list_empty(&file_priv->mm.request_list)) { |
5372 | struct drm_i915_gem_request *request; | |
5373 | ||
5374 | request = list_first_entry(&file_priv->mm.request_list, | |
5375 | struct drm_i915_gem_request, | |
5376 | client_list); | |
5377 | list_del(&request->client_list); | |
5378 | request->file_priv = NULL; | |
5379 | } | |
1c25595f | 5380 | spin_unlock(&file_priv->mm.lock); |
b29c19b6 | 5381 | |
2e1b8730 | 5382 | if (!list_empty(&file_priv->rps.link)) { |
8d3afd7d | 5383 | spin_lock(&to_i915(dev)->rps.client_lock); |
2e1b8730 | 5384 | list_del(&file_priv->rps.link); |
8d3afd7d | 5385 | spin_unlock(&to_i915(dev)->rps.client_lock); |
1854d5ca | 5386 | } |
b29c19b6 CW |
5387 | } |
5388 | ||
5389 | int i915_gem_open(struct drm_device *dev, struct drm_file *file) | |
5390 | { | |
5391 | struct drm_i915_file_private *file_priv; | |
e422b888 | 5392 | int ret; |
b29c19b6 CW |
5393 | |
5394 | DRM_DEBUG_DRIVER("\n"); | |
5395 | ||
5396 | file_priv = kzalloc(sizeof(*file_priv), GFP_KERNEL); | |
5397 | if (!file_priv) | |
5398 | return -ENOMEM; | |
5399 | ||
5400 | file->driver_priv = file_priv; | |
f19ec8cb | 5401 | file_priv->dev_priv = to_i915(dev); |
ab0e7ff9 | 5402 | file_priv->file = file; |
2e1b8730 | 5403 | INIT_LIST_HEAD(&file_priv->rps.link); |
b29c19b6 CW |
5404 | |
5405 | spin_lock_init(&file_priv->mm.lock); | |
5406 | INIT_LIST_HEAD(&file_priv->mm.request_list); | |
b29c19b6 | 5407 | |
de1add36 TU |
5408 | file_priv->bsd_ring = -1; |
5409 | ||
e422b888 BW |
5410 | ret = i915_gem_context_open(dev, file); |
5411 | if (ret) | |
5412 | kfree(file_priv); | |
b29c19b6 | 5413 | |
e422b888 | 5414 | return ret; |
b29c19b6 CW |
5415 | } |
5416 | ||
b680c37a DV |
5417 | /** |
5418 | * i915_gem_track_fb - update frontbuffer tracking | |
d9072a3e GT |
5419 | * @old: current GEM buffer for the frontbuffer slots |
5420 | * @new: new GEM buffer for the frontbuffer slots | |
5421 | * @frontbuffer_bits: bitmask of frontbuffer slots | |
b680c37a DV |
5422 | * |
5423 | * This updates the frontbuffer tracking bits @frontbuffer_bits by clearing them | |
5424 | * from @old and setting them in @new. Both @old and @new can be NULL. | |
5425 | */ | |
a071fa00 DV |
5426 | void i915_gem_track_fb(struct drm_i915_gem_object *old, |
5427 | struct drm_i915_gem_object *new, | |
5428 | unsigned frontbuffer_bits) | |
5429 | { | |
5430 | if (old) { | |
5431 | WARN_ON(!mutex_is_locked(&old->base.dev->struct_mutex)); | |
5432 | WARN_ON(!(old->frontbuffer_bits & frontbuffer_bits)); | |
5433 | old->frontbuffer_bits &= ~frontbuffer_bits; | |
5434 | } | |
5435 | ||
5436 | if (new) { | |
5437 | WARN_ON(!mutex_is_locked(&new->base.dev->struct_mutex)); | |
5438 | WARN_ON(new->frontbuffer_bits & frontbuffer_bits); | |
5439 | new->frontbuffer_bits |= frontbuffer_bits; | |
5440 | } | |
5441 | } | |
5442 | ||
a70a3148 | 5443 | /* All the new VM stuff */ |
088e0df4 MT |
5444 | u64 i915_gem_obj_offset(struct drm_i915_gem_object *o, |
5445 | struct i915_address_space *vm) | |
a70a3148 | 5446 | { |
fac5e23e | 5447 | struct drm_i915_private *dev_priv = to_i915(o->base.dev); |
a70a3148 BW |
5448 | struct i915_vma *vma; |
5449 | ||
896ab1a5 | 5450 | WARN_ON(vm == &dev_priv->mm.aliasing_ppgtt->base); |
a70a3148 | 5451 | |
1c7f4bca | 5452 | list_for_each_entry(vma, &o->vma_list, obj_link) { |
596c5923 | 5453 | if (vma->is_ggtt && |
ec7adb6e JL |
5454 | vma->ggtt_view.type != I915_GGTT_VIEW_NORMAL) |
5455 | continue; | |
5456 | if (vma->vm == vm) | |
a70a3148 | 5457 | return vma->node.start; |
a70a3148 | 5458 | } |
ec7adb6e | 5459 | |
f25748ea DV |
5460 | WARN(1, "%s vma for this object not found.\n", |
5461 | i915_is_ggtt(vm) ? "global" : "ppgtt"); | |
a70a3148 BW |
5462 | return -1; |
5463 | } | |
5464 | ||
088e0df4 MT |
5465 | u64 i915_gem_obj_ggtt_offset_view(struct drm_i915_gem_object *o, |
5466 | const struct i915_ggtt_view *view) | |
a70a3148 BW |
5467 | { |
5468 | struct i915_vma *vma; | |
5469 | ||
1c7f4bca | 5470 | list_for_each_entry(vma, &o->vma_list, obj_link) |
8aac2220 | 5471 | if (vma->is_ggtt && i915_ggtt_view_equal(&vma->ggtt_view, view)) |
ec7adb6e JL |
5472 | return vma->node.start; |
5473 | ||
5678ad73 | 5474 | WARN(1, "global vma for this object not found. (view=%u)\n", view->type); |
ec7adb6e JL |
5475 | return -1; |
5476 | } | |
5477 | ||
5478 | bool i915_gem_obj_bound(struct drm_i915_gem_object *o, | |
5479 | struct i915_address_space *vm) | |
5480 | { | |
5481 | struct i915_vma *vma; | |
5482 | ||
1c7f4bca | 5483 | list_for_each_entry(vma, &o->vma_list, obj_link) { |
596c5923 | 5484 | if (vma->is_ggtt && |
ec7adb6e JL |
5485 | vma->ggtt_view.type != I915_GGTT_VIEW_NORMAL) |
5486 | continue; | |
5487 | if (vma->vm == vm && drm_mm_node_allocated(&vma->node)) | |
5488 | return true; | |
5489 | } | |
5490 | ||
5491 | return false; | |
5492 | } | |
5493 | ||
5494 | bool i915_gem_obj_ggtt_bound_view(struct drm_i915_gem_object *o, | |
9abc4648 | 5495 | const struct i915_ggtt_view *view) |
ec7adb6e | 5496 | { |
ec7adb6e JL |
5497 | struct i915_vma *vma; |
5498 | ||
1c7f4bca | 5499 | list_for_each_entry(vma, &o->vma_list, obj_link) |
ff5ec22d | 5500 | if (vma->is_ggtt && |
9abc4648 | 5501 | i915_ggtt_view_equal(&vma->ggtt_view, view) && |
fe14d5f4 | 5502 | drm_mm_node_allocated(&vma->node)) |
a70a3148 BW |
5503 | return true; |
5504 | ||
5505 | return false; | |
5506 | } | |
5507 | ||
5508 | bool i915_gem_obj_bound_any(struct drm_i915_gem_object *o) | |
5509 | { | |
5a1d5eb0 | 5510 | struct i915_vma *vma; |
a70a3148 | 5511 | |
1c7f4bca | 5512 | list_for_each_entry(vma, &o->vma_list, obj_link) |
5a1d5eb0 | 5513 | if (drm_mm_node_allocated(&vma->node)) |
a70a3148 BW |
5514 | return true; |
5515 | ||
5516 | return false; | |
5517 | } | |
5518 | ||
8da32727 | 5519 | unsigned long i915_gem_obj_ggtt_size(struct drm_i915_gem_object *o) |
a70a3148 | 5520 | { |
a70a3148 BW |
5521 | struct i915_vma *vma; |
5522 | ||
8da32727 | 5523 | GEM_BUG_ON(list_empty(&o->vma_list)); |
a70a3148 | 5524 | |
1c7f4bca | 5525 | list_for_each_entry(vma, &o->vma_list, obj_link) { |
596c5923 | 5526 | if (vma->is_ggtt && |
8da32727 | 5527 | vma->ggtt_view.type == I915_GGTT_VIEW_NORMAL) |
a70a3148 | 5528 | return vma->node.size; |
ec7adb6e | 5529 | } |
8da32727 | 5530 | |
a70a3148 BW |
5531 | return 0; |
5532 | } | |
5533 | ||
ec7adb6e | 5534 | bool i915_gem_obj_is_pinned(struct drm_i915_gem_object *obj) |
5c2abbea BW |
5535 | { |
5536 | struct i915_vma *vma; | |
1c7f4bca | 5537 | list_for_each_entry(vma, &obj->vma_list, obj_link) |
ec7adb6e JL |
5538 | if (vma->pin_count > 0) |
5539 | return true; | |
a6631ae1 | 5540 | |
ec7adb6e | 5541 | return false; |
5c2abbea | 5542 | } |
ea70299d | 5543 | |
033908ae DG |
5544 | /* Like i915_gem_object_get_page(), but mark the returned page dirty */ |
5545 | struct page * | |
5546 | i915_gem_object_get_dirty_page(struct drm_i915_gem_object *obj, int n) | |
5547 | { | |
5548 | struct page *page; | |
5549 | ||
5550 | /* Only default objects have per-page dirty tracking */ | |
b9bcd14a | 5551 | if (WARN_ON(!i915_gem_object_has_struct_page(obj))) |
033908ae DG |
5552 | return NULL; |
5553 | ||
5554 | page = i915_gem_object_get_page(obj, n); | |
5555 | set_page_dirty(page); | |
5556 | return page; | |
5557 | } | |
5558 | ||
ea70299d DG |
5559 | /* Allocate a new GEM object and fill it with the supplied data */ |
5560 | struct drm_i915_gem_object * | |
5561 | i915_gem_object_create_from_data(struct drm_device *dev, | |
5562 | const void *data, size_t size) | |
5563 | { | |
5564 | struct drm_i915_gem_object *obj; | |
5565 | struct sg_table *sg; | |
5566 | size_t bytes; | |
5567 | int ret; | |
5568 | ||
d37cd8a8 | 5569 | obj = i915_gem_object_create(dev, round_up(size, PAGE_SIZE)); |
fe3db79b | 5570 | if (IS_ERR(obj)) |
ea70299d DG |
5571 | return obj; |
5572 | ||
5573 | ret = i915_gem_object_set_to_cpu_domain(obj, true); | |
5574 | if (ret) | |
5575 | goto fail; | |
5576 | ||
5577 | ret = i915_gem_object_get_pages(obj); | |
5578 | if (ret) | |
5579 | goto fail; | |
5580 | ||
5581 | i915_gem_object_pin_pages(obj); | |
5582 | sg = obj->pages; | |
5583 | bytes = sg_copy_from_buffer(sg->sgl, sg->nents, (void *)data, size); | |
9e7d18c0 | 5584 | obj->dirty = 1; /* Backing store is now out of date */ |
ea70299d DG |
5585 | i915_gem_object_unpin_pages(obj); |
5586 | ||
5587 | if (WARN_ON(bytes != size)) { | |
5588 | DRM_ERROR("Incomplete copy, wrote %zu of %zu", bytes, size); | |
5589 | ret = -EFAULT; | |
5590 | goto fail; | |
5591 | } | |
5592 | ||
5593 | return obj; | |
5594 | ||
5595 | fail: | |
5596 | drm_gem_object_unreference(&obj->base); | |
5597 | return ERR_PTR(ret); | |
5598 | } |