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Commit | Line | Data |
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673a394b | 1 | /* |
be6a0376 | 2 | * Copyright © 2008-2015 Intel Corporation |
673a394b EA |
3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | * | |
26 | */ | |
27 | ||
760285e7 | 28 | #include <drm/drmP.h> |
0de23977 | 29 | #include <drm/drm_vma_manager.h> |
760285e7 | 30 | #include <drm/i915_drm.h> |
673a394b | 31 | #include "i915_drv.h" |
eb82289a | 32 | #include "i915_vgpu.h" |
1c5d22f7 | 33 | #include "i915_trace.h" |
652c393a | 34 | #include "intel_drv.h" |
5d723d7a | 35 | #include "intel_frontbuffer.h" |
0ccdacf6 | 36 | #include "intel_mocs.h" |
6b5e90f5 | 37 | #include <linux/dma-fence-array.h> |
c13d87ea | 38 | #include <linux/reservation.h> |
5949eac4 | 39 | #include <linux/shmem_fs.h> |
5a0e3ad6 | 40 | #include <linux/slab.h> |
20e4933c | 41 | #include <linux/stop_machine.h> |
673a394b | 42 | #include <linux/swap.h> |
79e53945 | 43 | #include <linux/pci.h> |
1286ff73 | 44 | #include <linux/dma-buf.h> |
673a394b | 45 | |
fbbd37b3 | 46 | static void i915_gem_flush_free_objects(struct drm_i915_private *i915); |
05394f39 | 47 | static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj); |
e62b59e4 | 48 | static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj); |
61050808 | 49 | |
c76ce038 CW |
50 | static bool cpu_cache_is_coherent(struct drm_device *dev, |
51 | enum i915_cache_level level) | |
52 | { | |
0031fb96 | 53 | return HAS_LLC(to_i915(dev)) || level != I915_CACHE_NONE; |
c76ce038 CW |
54 | } |
55 | ||
2c22569b CW |
56 | static bool cpu_write_needs_clflush(struct drm_i915_gem_object *obj) |
57 | { | |
b50a5371 AS |
58 | if (obj->base.write_domain == I915_GEM_DOMAIN_CPU) |
59 | return false; | |
60 | ||
2c22569b CW |
61 | if (!cpu_cache_is_coherent(obj->base.dev, obj->cache_level)) |
62 | return true; | |
63 | ||
64 | return obj->pin_display; | |
65 | } | |
66 | ||
4f1959ee | 67 | static int |
bb6dc8d9 | 68 | insert_mappable_node(struct i915_ggtt *ggtt, |
4f1959ee AS |
69 | struct drm_mm_node *node, u32 size) |
70 | { | |
71 | memset(node, 0, sizeof(*node)); | |
bb6dc8d9 | 72 | return drm_mm_insert_node_in_range_generic(&ggtt->base.mm, node, |
85fd4f58 CW |
73 | size, 0, |
74 | I915_COLOR_UNEVICTABLE, | |
bb6dc8d9 | 75 | 0, ggtt->mappable_end, |
4f1959ee AS |
76 | DRM_MM_SEARCH_DEFAULT, |
77 | DRM_MM_CREATE_DEFAULT); | |
78 | } | |
79 | ||
80 | static void | |
81 | remove_mappable_node(struct drm_mm_node *node) | |
82 | { | |
83 | drm_mm_remove_node(node); | |
84 | } | |
85 | ||
73aa808f CW |
86 | /* some bookkeeping */ |
87 | static void i915_gem_info_add_obj(struct drm_i915_private *dev_priv, | |
3ef7f228 | 88 | u64 size) |
73aa808f | 89 | { |
c20e8355 | 90 | spin_lock(&dev_priv->mm.object_stat_lock); |
73aa808f CW |
91 | dev_priv->mm.object_count++; |
92 | dev_priv->mm.object_memory += size; | |
c20e8355 | 93 | spin_unlock(&dev_priv->mm.object_stat_lock); |
73aa808f CW |
94 | } |
95 | ||
96 | static void i915_gem_info_remove_obj(struct drm_i915_private *dev_priv, | |
3ef7f228 | 97 | u64 size) |
73aa808f | 98 | { |
c20e8355 | 99 | spin_lock(&dev_priv->mm.object_stat_lock); |
73aa808f CW |
100 | dev_priv->mm.object_count--; |
101 | dev_priv->mm.object_memory -= size; | |
c20e8355 | 102 | spin_unlock(&dev_priv->mm.object_stat_lock); |
73aa808f CW |
103 | } |
104 | ||
21dd3734 | 105 | static int |
33196ded | 106 | i915_gem_wait_for_error(struct i915_gpu_error *error) |
30dbf0c0 | 107 | { |
30dbf0c0 CW |
108 | int ret; |
109 | ||
4c7d62c6 CW |
110 | might_sleep(); |
111 | ||
d98c52cf | 112 | if (!i915_reset_in_progress(error)) |
30dbf0c0 CW |
113 | return 0; |
114 | ||
0a6759c6 DV |
115 | /* |
116 | * Only wait 10 seconds for the gpu reset to complete to avoid hanging | |
117 | * userspace. If it takes that long something really bad is going on and | |
118 | * we should simply try to bail out and fail as gracefully as possible. | |
119 | */ | |
1f83fee0 | 120 | ret = wait_event_interruptible_timeout(error->reset_queue, |
d98c52cf | 121 | !i915_reset_in_progress(error), |
b52992c0 | 122 | I915_RESET_TIMEOUT); |
0a6759c6 DV |
123 | if (ret == 0) { |
124 | DRM_ERROR("Timed out waiting for the gpu reset to complete\n"); | |
125 | return -EIO; | |
126 | } else if (ret < 0) { | |
30dbf0c0 | 127 | return ret; |
d98c52cf CW |
128 | } else { |
129 | return 0; | |
0a6759c6 | 130 | } |
30dbf0c0 CW |
131 | } |
132 | ||
54cf91dc | 133 | int i915_mutex_lock_interruptible(struct drm_device *dev) |
76c1dec1 | 134 | { |
fac5e23e | 135 | struct drm_i915_private *dev_priv = to_i915(dev); |
76c1dec1 CW |
136 | int ret; |
137 | ||
33196ded | 138 | ret = i915_gem_wait_for_error(&dev_priv->gpu_error); |
76c1dec1 CW |
139 | if (ret) |
140 | return ret; | |
141 | ||
142 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
143 | if (ret) | |
144 | return ret; | |
145 | ||
76c1dec1 CW |
146 | return 0; |
147 | } | |
30dbf0c0 | 148 | |
5a125c3c EA |
149 | int |
150 | i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 151 | struct drm_file *file) |
5a125c3c | 152 | { |
72e96d64 | 153 | struct drm_i915_private *dev_priv = to_i915(dev); |
62106b4f | 154 | struct i915_ggtt *ggtt = &dev_priv->ggtt; |
72e96d64 | 155 | struct drm_i915_gem_get_aperture *args = data; |
ca1543be | 156 | struct i915_vma *vma; |
6299f992 | 157 | size_t pinned; |
5a125c3c | 158 | |
6299f992 | 159 | pinned = 0; |
73aa808f | 160 | mutex_lock(&dev->struct_mutex); |
1c7f4bca | 161 | list_for_each_entry(vma, &ggtt->base.active_list, vm_link) |
20dfbde4 | 162 | if (i915_vma_is_pinned(vma)) |
ca1543be | 163 | pinned += vma->node.size; |
1c7f4bca | 164 | list_for_each_entry(vma, &ggtt->base.inactive_list, vm_link) |
20dfbde4 | 165 | if (i915_vma_is_pinned(vma)) |
ca1543be | 166 | pinned += vma->node.size; |
73aa808f | 167 | mutex_unlock(&dev->struct_mutex); |
5a125c3c | 168 | |
72e96d64 | 169 | args->aper_size = ggtt->base.total; |
0206e353 | 170 | args->aper_available_size = args->aper_size - pinned; |
6299f992 | 171 | |
5a125c3c EA |
172 | return 0; |
173 | } | |
174 | ||
03ac84f1 | 175 | static struct sg_table * |
6a2c4232 | 176 | i915_gem_object_get_pages_phys(struct drm_i915_gem_object *obj) |
00731155 | 177 | { |
93c76a3d | 178 | struct address_space *mapping = obj->base.filp->f_mapping; |
6a2c4232 CW |
179 | char *vaddr = obj->phys_handle->vaddr; |
180 | struct sg_table *st; | |
181 | struct scatterlist *sg; | |
182 | int i; | |
00731155 | 183 | |
6a2c4232 | 184 | if (WARN_ON(i915_gem_object_needs_bit17_swizzle(obj))) |
03ac84f1 | 185 | return ERR_PTR(-EINVAL); |
6a2c4232 CW |
186 | |
187 | for (i = 0; i < obj->base.size / PAGE_SIZE; i++) { | |
188 | struct page *page; | |
189 | char *src; | |
190 | ||
191 | page = shmem_read_mapping_page(mapping, i); | |
192 | if (IS_ERR(page)) | |
03ac84f1 | 193 | return ERR_CAST(page); |
6a2c4232 CW |
194 | |
195 | src = kmap_atomic(page); | |
196 | memcpy(vaddr, src, PAGE_SIZE); | |
197 | drm_clflush_virt_range(vaddr, PAGE_SIZE); | |
198 | kunmap_atomic(src); | |
199 | ||
09cbfeaf | 200 | put_page(page); |
6a2c4232 CW |
201 | vaddr += PAGE_SIZE; |
202 | } | |
203 | ||
c033666a | 204 | i915_gem_chipset_flush(to_i915(obj->base.dev)); |
6a2c4232 CW |
205 | |
206 | st = kmalloc(sizeof(*st), GFP_KERNEL); | |
207 | if (st == NULL) | |
03ac84f1 | 208 | return ERR_PTR(-ENOMEM); |
6a2c4232 CW |
209 | |
210 | if (sg_alloc_table(st, 1, GFP_KERNEL)) { | |
211 | kfree(st); | |
03ac84f1 | 212 | return ERR_PTR(-ENOMEM); |
6a2c4232 CW |
213 | } |
214 | ||
215 | sg = st->sgl; | |
216 | sg->offset = 0; | |
217 | sg->length = obj->base.size; | |
00731155 | 218 | |
6a2c4232 CW |
219 | sg_dma_address(sg) = obj->phys_handle->busaddr; |
220 | sg_dma_len(sg) = obj->base.size; | |
221 | ||
03ac84f1 | 222 | return st; |
6a2c4232 CW |
223 | } |
224 | ||
225 | static void | |
2b3c8317 CW |
226 | __i915_gem_object_release_shmem(struct drm_i915_gem_object *obj, |
227 | struct sg_table *pages) | |
6a2c4232 | 228 | { |
a4f5ea64 | 229 | GEM_BUG_ON(obj->mm.madv == __I915_MADV_PURGED); |
00731155 | 230 | |
a4f5ea64 CW |
231 | if (obj->mm.madv == I915_MADV_DONTNEED) |
232 | obj->mm.dirty = false; | |
6a2c4232 | 233 | |
05c34837 CW |
234 | if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0 && |
235 | !cpu_cache_is_coherent(obj->base.dev, obj->cache_level)) | |
2b3c8317 | 236 | drm_clflush_sg(pages); |
03ac84f1 CW |
237 | |
238 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; | |
239 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; | |
240 | } | |
241 | ||
242 | static void | |
243 | i915_gem_object_put_pages_phys(struct drm_i915_gem_object *obj, | |
244 | struct sg_table *pages) | |
245 | { | |
2b3c8317 | 246 | __i915_gem_object_release_shmem(obj, pages); |
03ac84f1 | 247 | |
a4f5ea64 | 248 | if (obj->mm.dirty) { |
93c76a3d | 249 | struct address_space *mapping = obj->base.filp->f_mapping; |
6a2c4232 | 250 | char *vaddr = obj->phys_handle->vaddr; |
00731155 CW |
251 | int i; |
252 | ||
253 | for (i = 0; i < obj->base.size / PAGE_SIZE; i++) { | |
6a2c4232 CW |
254 | struct page *page; |
255 | char *dst; | |
256 | ||
257 | page = shmem_read_mapping_page(mapping, i); | |
258 | if (IS_ERR(page)) | |
259 | continue; | |
260 | ||
261 | dst = kmap_atomic(page); | |
262 | drm_clflush_virt_range(vaddr, PAGE_SIZE); | |
263 | memcpy(dst, vaddr, PAGE_SIZE); | |
264 | kunmap_atomic(dst); | |
265 | ||
266 | set_page_dirty(page); | |
a4f5ea64 | 267 | if (obj->mm.madv == I915_MADV_WILLNEED) |
00731155 | 268 | mark_page_accessed(page); |
09cbfeaf | 269 | put_page(page); |
00731155 CW |
270 | vaddr += PAGE_SIZE; |
271 | } | |
a4f5ea64 | 272 | obj->mm.dirty = false; |
00731155 CW |
273 | } |
274 | ||
03ac84f1 CW |
275 | sg_free_table(pages); |
276 | kfree(pages); | |
6a2c4232 CW |
277 | } |
278 | ||
279 | static void | |
280 | i915_gem_object_release_phys(struct drm_i915_gem_object *obj) | |
281 | { | |
282 | drm_pci_free(obj->base.dev, obj->phys_handle); | |
a4f5ea64 | 283 | i915_gem_object_unpin_pages(obj); |
6a2c4232 CW |
284 | } |
285 | ||
286 | static const struct drm_i915_gem_object_ops i915_gem_phys_ops = { | |
287 | .get_pages = i915_gem_object_get_pages_phys, | |
288 | .put_pages = i915_gem_object_put_pages_phys, | |
289 | .release = i915_gem_object_release_phys, | |
290 | }; | |
291 | ||
35a9611c | 292 | int i915_gem_object_unbind(struct drm_i915_gem_object *obj) |
aa653a68 CW |
293 | { |
294 | struct i915_vma *vma; | |
295 | LIST_HEAD(still_in_list); | |
02bef8f9 CW |
296 | int ret; |
297 | ||
298 | lockdep_assert_held(&obj->base.dev->struct_mutex); | |
aa653a68 | 299 | |
02bef8f9 CW |
300 | /* Closed vma are removed from the obj->vma_list - but they may |
301 | * still have an active binding on the object. To remove those we | |
302 | * must wait for all rendering to complete to the object (as unbinding | |
303 | * must anyway), and retire the requests. | |
aa653a68 | 304 | */ |
e95433c7 CW |
305 | ret = i915_gem_object_wait(obj, |
306 | I915_WAIT_INTERRUPTIBLE | | |
307 | I915_WAIT_LOCKED | | |
308 | I915_WAIT_ALL, | |
309 | MAX_SCHEDULE_TIMEOUT, | |
310 | NULL); | |
02bef8f9 CW |
311 | if (ret) |
312 | return ret; | |
313 | ||
314 | i915_gem_retire_requests(to_i915(obj->base.dev)); | |
315 | ||
aa653a68 CW |
316 | while ((vma = list_first_entry_or_null(&obj->vma_list, |
317 | struct i915_vma, | |
318 | obj_link))) { | |
319 | list_move_tail(&vma->obj_link, &still_in_list); | |
320 | ret = i915_vma_unbind(vma); | |
321 | if (ret) | |
322 | break; | |
323 | } | |
324 | list_splice(&still_in_list, &obj->vma_list); | |
325 | ||
326 | return ret; | |
327 | } | |
328 | ||
e95433c7 CW |
329 | static long |
330 | i915_gem_object_wait_fence(struct dma_fence *fence, | |
331 | unsigned int flags, | |
332 | long timeout, | |
333 | struct intel_rps_client *rps) | |
00e60f26 | 334 | { |
e95433c7 | 335 | struct drm_i915_gem_request *rq; |
00e60f26 | 336 | |
e95433c7 | 337 | BUILD_BUG_ON(I915_WAIT_INTERRUPTIBLE != 0x1); |
00e60f26 | 338 | |
e95433c7 CW |
339 | if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &fence->flags)) |
340 | return timeout; | |
341 | ||
342 | if (!dma_fence_is_i915(fence)) | |
343 | return dma_fence_wait_timeout(fence, | |
344 | flags & I915_WAIT_INTERRUPTIBLE, | |
345 | timeout); | |
346 | ||
347 | rq = to_request(fence); | |
348 | if (i915_gem_request_completed(rq)) | |
349 | goto out; | |
350 | ||
351 | /* This client is about to stall waiting for the GPU. In many cases | |
352 | * this is undesirable and limits the throughput of the system, as | |
353 | * many clients cannot continue processing user input/output whilst | |
354 | * blocked. RPS autotuning may take tens of milliseconds to respond | |
355 | * to the GPU load and thus incurs additional latency for the client. | |
356 | * We can circumvent that by promoting the GPU frequency to maximum | |
357 | * before we wait. This makes the GPU throttle up much more quickly | |
358 | * (good for benchmarks and user experience, e.g. window animations), | |
359 | * but at a cost of spending more power processing the workload | |
360 | * (bad for battery). Not all clients even want their results | |
361 | * immediately and for them we should just let the GPU select its own | |
362 | * frequency to maximise efficiency. To prevent a single client from | |
363 | * forcing the clocks too high for the whole system, we only allow | |
364 | * each client to waitboost once in a busy period. | |
365 | */ | |
366 | if (rps) { | |
367 | if (INTEL_GEN(rq->i915) >= 6) | |
368 | gen6_rps_boost(rq->i915, rps, rq->emitted_jiffies); | |
369 | else | |
370 | rps = NULL; | |
00e60f26 CW |
371 | } |
372 | ||
e95433c7 CW |
373 | timeout = i915_wait_request(rq, flags, timeout); |
374 | ||
375 | out: | |
376 | if (flags & I915_WAIT_LOCKED && i915_gem_request_completed(rq)) | |
377 | i915_gem_request_retire_upto(rq); | |
378 | ||
cb399eab | 379 | if (rps && rq->global_seqno == intel_engine_last_submit(rq->engine)) { |
e95433c7 CW |
380 | /* The GPU is now idle and this client has stalled. |
381 | * Since no other client has submitted a request in the | |
382 | * meantime, assume that this client is the only one | |
383 | * supplying work to the GPU but is unable to keep that | |
384 | * work supplied because it is waiting. Since the GPU is | |
385 | * then never kept fully busy, RPS autoclocking will | |
386 | * keep the clocks relatively low, causing further delays. | |
387 | * Compensate by giving the synchronous client credit for | |
388 | * a waitboost next time. | |
389 | */ | |
390 | spin_lock(&rq->i915->rps.client_lock); | |
391 | list_del_init(&rps->link); | |
392 | spin_unlock(&rq->i915->rps.client_lock); | |
393 | } | |
394 | ||
395 | return timeout; | |
396 | } | |
397 | ||
398 | static long | |
399 | i915_gem_object_wait_reservation(struct reservation_object *resv, | |
400 | unsigned int flags, | |
401 | long timeout, | |
402 | struct intel_rps_client *rps) | |
403 | { | |
404 | struct dma_fence *excl; | |
405 | ||
406 | if (flags & I915_WAIT_ALL) { | |
407 | struct dma_fence **shared; | |
408 | unsigned int count, i; | |
00e60f26 CW |
409 | int ret; |
410 | ||
e95433c7 CW |
411 | ret = reservation_object_get_fences_rcu(resv, |
412 | &excl, &count, &shared); | |
00e60f26 CW |
413 | if (ret) |
414 | return ret; | |
00e60f26 | 415 | |
e95433c7 CW |
416 | for (i = 0; i < count; i++) { |
417 | timeout = i915_gem_object_wait_fence(shared[i], | |
418 | flags, timeout, | |
419 | rps); | |
420 | if (timeout <= 0) | |
421 | break; | |
00e60f26 | 422 | |
e95433c7 CW |
423 | dma_fence_put(shared[i]); |
424 | } | |
425 | ||
426 | for (; i < count; i++) | |
427 | dma_fence_put(shared[i]); | |
428 | kfree(shared); | |
429 | } else { | |
430 | excl = reservation_object_get_excl_rcu(resv); | |
00e60f26 CW |
431 | } |
432 | ||
e95433c7 CW |
433 | if (excl && timeout > 0) |
434 | timeout = i915_gem_object_wait_fence(excl, flags, timeout, rps); | |
435 | ||
436 | dma_fence_put(excl); | |
437 | ||
438 | return timeout; | |
00e60f26 CW |
439 | } |
440 | ||
6b5e90f5 CW |
441 | static void __fence_set_priority(struct dma_fence *fence, int prio) |
442 | { | |
443 | struct drm_i915_gem_request *rq; | |
444 | struct intel_engine_cs *engine; | |
445 | ||
446 | if (!dma_fence_is_i915(fence)) | |
447 | return; | |
448 | ||
449 | rq = to_request(fence); | |
450 | engine = rq->engine; | |
451 | if (!engine->schedule) | |
452 | return; | |
453 | ||
454 | engine->schedule(rq, prio); | |
455 | } | |
456 | ||
457 | static void fence_set_priority(struct dma_fence *fence, int prio) | |
458 | { | |
459 | /* Recurse once into a fence-array */ | |
460 | if (dma_fence_is_array(fence)) { | |
461 | struct dma_fence_array *array = to_dma_fence_array(fence); | |
462 | int i; | |
463 | ||
464 | for (i = 0; i < array->num_fences; i++) | |
465 | __fence_set_priority(array->fences[i], prio); | |
466 | } else { | |
467 | __fence_set_priority(fence, prio); | |
468 | } | |
469 | } | |
470 | ||
471 | int | |
472 | i915_gem_object_wait_priority(struct drm_i915_gem_object *obj, | |
473 | unsigned int flags, | |
474 | int prio) | |
475 | { | |
476 | struct dma_fence *excl; | |
477 | ||
478 | if (flags & I915_WAIT_ALL) { | |
479 | struct dma_fence **shared; | |
480 | unsigned int count, i; | |
481 | int ret; | |
482 | ||
483 | ret = reservation_object_get_fences_rcu(obj->resv, | |
484 | &excl, &count, &shared); | |
485 | if (ret) | |
486 | return ret; | |
487 | ||
488 | for (i = 0; i < count; i++) { | |
489 | fence_set_priority(shared[i], prio); | |
490 | dma_fence_put(shared[i]); | |
491 | } | |
492 | ||
493 | kfree(shared); | |
494 | } else { | |
495 | excl = reservation_object_get_excl_rcu(obj->resv); | |
496 | } | |
497 | ||
498 | if (excl) { | |
499 | fence_set_priority(excl, prio); | |
500 | dma_fence_put(excl); | |
501 | } | |
502 | return 0; | |
503 | } | |
504 | ||
e95433c7 CW |
505 | /** |
506 | * Waits for rendering to the object to be completed | |
507 | * @obj: i915 gem object | |
508 | * @flags: how to wait (under a lock, for all rendering or just for writes etc) | |
509 | * @timeout: how long to wait | |
510 | * @rps: client (user process) to charge for any waitboosting | |
00e60f26 | 511 | */ |
e95433c7 CW |
512 | int |
513 | i915_gem_object_wait(struct drm_i915_gem_object *obj, | |
514 | unsigned int flags, | |
515 | long timeout, | |
516 | struct intel_rps_client *rps) | |
00e60f26 | 517 | { |
e95433c7 CW |
518 | might_sleep(); |
519 | #if IS_ENABLED(CONFIG_LOCKDEP) | |
520 | GEM_BUG_ON(debug_locks && | |
521 | !!lockdep_is_held(&obj->base.dev->struct_mutex) != | |
522 | !!(flags & I915_WAIT_LOCKED)); | |
523 | #endif | |
524 | GEM_BUG_ON(timeout < 0); | |
00e60f26 | 525 | |
d07f0e59 CW |
526 | timeout = i915_gem_object_wait_reservation(obj->resv, |
527 | flags, timeout, | |
528 | rps); | |
e95433c7 | 529 | return timeout < 0 ? timeout : 0; |
00e60f26 CW |
530 | } |
531 | ||
532 | static struct intel_rps_client *to_rps_client(struct drm_file *file) | |
533 | { | |
534 | struct drm_i915_file_private *fpriv = file->driver_priv; | |
535 | ||
536 | return &fpriv->rps; | |
537 | } | |
538 | ||
00731155 CW |
539 | int |
540 | i915_gem_object_attach_phys(struct drm_i915_gem_object *obj, | |
541 | int align) | |
542 | { | |
543 | drm_dma_handle_t *phys; | |
6a2c4232 | 544 | int ret; |
00731155 CW |
545 | |
546 | if (obj->phys_handle) { | |
547 | if ((unsigned long)obj->phys_handle->vaddr & (align -1)) | |
548 | return -EBUSY; | |
549 | ||
550 | return 0; | |
551 | } | |
552 | ||
a4f5ea64 | 553 | if (obj->mm.madv != I915_MADV_WILLNEED) |
00731155 CW |
554 | return -EFAULT; |
555 | ||
556 | if (obj->base.filp == NULL) | |
557 | return -EINVAL; | |
558 | ||
4717ca9e CW |
559 | ret = i915_gem_object_unbind(obj); |
560 | if (ret) | |
561 | return ret; | |
562 | ||
548625ee | 563 | __i915_gem_object_put_pages(obj, I915_MM_NORMAL); |
03ac84f1 CW |
564 | if (obj->mm.pages) |
565 | return -EBUSY; | |
6a2c4232 | 566 | |
00731155 CW |
567 | /* create a new object */ |
568 | phys = drm_pci_alloc(obj->base.dev, obj->base.size, align); | |
569 | if (!phys) | |
570 | return -ENOMEM; | |
571 | ||
00731155 | 572 | obj->phys_handle = phys; |
6a2c4232 CW |
573 | obj->ops = &i915_gem_phys_ops; |
574 | ||
a4f5ea64 | 575 | return i915_gem_object_pin_pages(obj); |
00731155 CW |
576 | } |
577 | ||
578 | static int | |
579 | i915_gem_phys_pwrite(struct drm_i915_gem_object *obj, | |
580 | struct drm_i915_gem_pwrite *args, | |
03ac84f1 | 581 | struct drm_file *file) |
00731155 CW |
582 | { |
583 | struct drm_device *dev = obj->base.dev; | |
584 | void *vaddr = obj->phys_handle->vaddr + args->offset; | |
3ed605bc | 585 | char __user *user_data = u64_to_user_ptr(args->data_ptr); |
e95433c7 | 586 | int ret; |
6a2c4232 CW |
587 | |
588 | /* We manually control the domain here and pretend that it | |
589 | * remains coherent i.e. in the GTT domain, like shmem_pwrite. | |
590 | */ | |
e95433c7 CW |
591 | lockdep_assert_held(&obj->base.dev->struct_mutex); |
592 | ret = i915_gem_object_wait(obj, | |
593 | I915_WAIT_INTERRUPTIBLE | | |
594 | I915_WAIT_LOCKED | | |
595 | I915_WAIT_ALL, | |
596 | MAX_SCHEDULE_TIMEOUT, | |
03ac84f1 | 597 | to_rps_client(file)); |
6a2c4232 CW |
598 | if (ret) |
599 | return ret; | |
00731155 | 600 | |
77a0d1ca | 601 | intel_fb_obj_invalidate(obj, ORIGIN_CPU); |
00731155 CW |
602 | if (__copy_from_user_inatomic_nocache(vaddr, user_data, args->size)) { |
603 | unsigned long unwritten; | |
604 | ||
605 | /* The physical object once assigned is fixed for the lifetime | |
606 | * of the obj, so we can safely drop the lock and continue | |
607 | * to access vaddr. | |
608 | */ | |
609 | mutex_unlock(&dev->struct_mutex); | |
610 | unwritten = copy_from_user(vaddr, user_data, args->size); | |
611 | mutex_lock(&dev->struct_mutex); | |
063e4e6b PZ |
612 | if (unwritten) { |
613 | ret = -EFAULT; | |
614 | goto out; | |
615 | } | |
00731155 CW |
616 | } |
617 | ||
6a2c4232 | 618 | drm_clflush_virt_range(vaddr, args->size); |
c033666a | 619 | i915_gem_chipset_flush(to_i915(dev)); |
063e4e6b PZ |
620 | |
621 | out: | |
de152b62 | 622 | intel_fb_obj_flush(obj, false, ORIGIN_CPU); |
063e4e6b | 623 | return ret; |
00731155 CW |
624 | } |
625 | ||
187685cb | 626 | void *i915_gem_object_alloc(struct drm_i915_private *dev_priv) |
42dcedd4 | 627 | { |
efab6d8d | 628 | return kmem_cache_zalloc(dev_priv->objects, GFP_KERNEL); |
42dcedd4 CW |
629 | } |
630 | ||
631 | void i915_gem_object_free(struct drm_i915_gem_object *obj) | |
632 | { | |
fac5e23e | 633 | struct drm_i915_private *dev_priv = to_i915(obj->base.dev); |
efab6d8d | 634 | kmem_cache_free(dev_priv->objects, obj); |
42dcedd4 CW |
635 | } |
636 | ||
ff72145b DA |
637 | static int |
638 | i915_gem_create(struct drm_file *file, | |
12d79d78 | 639 | struct drm_i915_private *dev_priv, |
ff72145b DA |
640 | uint64_t size, |
641 | uint32_t *handle_p) | |
673a394b | 642 | { |
05394f39 | 643 | struct drm_i915_gem_object *obj; |
a1a2d1d3 PP |
644 | int ret; |
645 | u32 handle; | |
673a394b | 646 | |
ff72145b | 647 | size = roundup(size, PAGE_SIZE); |
8ffc0246 CW |
648 | if (size == 0) |
649 | return -EINVAL; | |
673a394b EA |
650 | |
651 | /* Allocate the new object */ | |
12d79d78 | 652 | obj = i915_gem_object_create(dev_priv, size); |
fe3db79b CW |
653 | if (IS_ERR(obj)) |
654 | return PTR_ERR(obj); | |
673a394b | 655 | |
05394f39 | 656 | ret = drm_gem_handle_create(file, &obj->base, &handle); |
202f2fef | 657 | /* drop reference from allocate - handle holds it now */ |
f0cd5182 | 658 | i915_gem_object_put(obj); |
d861e338 DV |
659 | if (ret) |
660 | return ret; | |
202f2fef | 661 | |
ff72145b | 662 | *handle_p = handle; |
673a394b EA |
663 | return 0; |
664 | } | |
665 | ||
ff72145b DA |
666 | int |
667 | i915_gem_dumb_create(struct drm_file *file, | |
668 | struct drm_device *dev, | |
669 | struct drm_mode_create_dumb *args) | |
670 | { | |
671 | /* have to work out size/pitch and return them */ | |
de45eaf7 | 672 | args->pitch = ALIGN(args->width * DIV_ROUND_UP(args->bpp, 8), 64); |
ff72145b | 673 | args->size = args->pitch * args->height; |
12d79d78 | 674 | return i915_gem_create(file, to_i915(dev), |
da6b51d0 | 675 | args->size, &args->handle); |
ff72145b DA |
676 | } |
677 | ||
ff72145b DA |
678 | /** |
679 | * Creates a new mm object and returns a handle to it. | |
14bb2c11 TU |
680 | * @dev: drm device pointer |
681 | * @data: ioctl data blob | |
682 | * @file: drm file pointer | |
ff72145b DA |
683 | */ |
684 | int | |
685 | i915_gem_create_ioctl(struct drm_device *dev, void *data, | |
686 | struct drm_file *file) | |
687 | { | |
12d79d78 | 688 | struct drm_i915_private *dev_priv = to_i915(dev); |
ff72145b | 689 | struct drm_i915_gem_create *args = data; |
63ed2cb2 | 690 | |
12d79d78 | 691 | i915_gem_flush_free_objects(dev_priv); |
fbbd37b3 | 692 | |
12d79d78 | 693 | return i915_gem_create(file, dev_priv, |
da6b51d0 | 694 | args->size, &args->handle); |
ff72145b DA |
695 | } |
696 | ||
8461d226 DV |
697 | static inline int |
698 | __copy_to_user_swizzled(char __user *cpu_vaddr, | |
699 | const char *gpu_vaddr, int gpu_offset, | |
700 | int length) | |
701 | { | |
702 | int ret, cpu_offset = 0; | |
703 | ||
704 | while (length > 0) { | |
705 | int cacheline_end = ALIGN(gpu_offset + 1, 64); | |
706 | int this_length = min(cacheline_end - gpu_offset, length); | |
707 | int swizzled_gpu_offset = gpu_offset ^ 64; | |
708 | ||
709 | ret = __copy_to_user(cpu_vaddr + cpu_offset, | |
710 | gpu_vaddr + swizzled_gpu_offset, | |
711 | this_length); | |
712 | if (ret) | |
713 | return ret + length; | |
714 | ||
715 | cpu_offset += this_length; | |
716 | gpu_offset += this_length; | |
717 | length -= this_length; | |
718 | } | |
719 | ||
720 | return 0; | |
721 | } | |
722 | ||
8c59967c | 723 | static inline int |
4f0c7cfb BW |
724 | __copy_from_user_swizzled(char *gpu_vaddr, int gpu_offset, |
725 | const char __user *cpu_vaddr, | |
8c59967c DV |
726 | int length) |
727 | { | |
728 | int ret, cpu_offset = 0; | |
729 | ||
730 | while (length > 0) { | |
731 | int cacheline_end = ALIGN(gpu_offset + 1, 64); | |
732 | int this_length = min(cacheline_end - gpu_offset, length); | |
733 | int swizzled_gpu_offset = gpu_offset ^ 64; | |
734 | ||
735 | ret = __copy_from_user(gpu_vaddr + swizzled_gpu_offset, | |
736 | cpu_vaddr + cpu_offset, | |
737 | this_length); | |
738 | if (ret) | |
739 | return ret + length; | |
740 | ||
741 | cpu_offset += this_length; | |
742 | gpu_offset += this_length; | |
743 | length -= this_length; | |
744 | } | |
745 | ||
746 | return 0; | |
747 | } | |
748 | ||
4c914c0c BV |
749 | /* |
750 | * Pins the specified object's pages and synchronizes the object with | |
751 | * GPU accesses. Sets needs_clflush to non-zero if the caller should | |
752 | * flush the object from the CPU cache. | |
753 | */ | |
754 | int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj, | |
43394c7d | 755 | unsigned int *needs_clflush) |
4c914c0c BV |
756 | { |
757 | int ret; | |
758 | ||
e95433c7 | 759 | lockdep_assert_held(&obj->base.dev->struct_mutex); |
4c914c0c | 760 | |
e95433c7 | 761 | *needs_clflush = 0; |
43394c7d CW |
762 | if (!i915_gem_object_has_struct_page(obj)) |
763 | return -ENODEV; | |
4c914c0c | 764 | |
e95433c7 CW |
765 | ret = i915_gem_object_wait(obj, |
766 | I915_WAIT_INTERRUPTIBLE | | |
767 | I915_WAIT_LOCKED, | |
768 | MAX_SCHEDULE_TIMEOUT, | |
769 | NULL); | |
c13d87ea CW |
770 | if (ret) |
771 | return ret; | |
772 | ||
a4f5ea64 | 773 | ret = i915_gem_object_pin_pages(obj); |
9764951e CW |
774 | if (ret) |
775 | return ret; | |
776 | ||
a314d5cb CW |
777 | i915_gem_object_flush_gtt_write_domain(obj); |
778 | ||
43394c7d CW |
779 | /* If we're not in the cpu read domain, set ourself into the gtt |
780 | * read domain and manually flush cachelines (if required). This | |
781 | * optimizes for the case when the gpu will dirty the data | |
782 | * anyway again before the next pread happens. | |
783 | */ | |
784 | if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU)) | |
4c914c0c BV |
785 | *needs_clflush = !cpu_cache_is_coherent(obj->base.dev, |
786 | obj->cache_level); | |
43394c7d | 787 | |
43394c7d CW |
788 | if (*needs_clflush && !static_cpu_has(X86_FEATURE_CLFLUSH)) { |
789 | ret = i915_gem_object_set_to_cpu_domain(obj, false); | |
9764951e CW |
790 | if (ret) |
791 | goto err_unpin; | |
792 | ||
43394c7d | 793 | *needs_clflush = 0; |
4c914c0c BV |
794 | } |
795 | ||
9764951e | 796 | /* return with the pages pinned */ |
43394c7d | 797 | return 0; |
9764951e CW |
798 | |
799 | err_unpin: | |
800 | i915_gem_object_unpin_pages(obj); | |
801 | return ret; | |
43394c7d CW |
802 | } |
803 | ||
804 | int i915_gem_obj_prepare_shmem_write(struct drm_i915_gem_object *obj, | |
805 | unsigned int *needs_clflush) | |
806 | { | |
807 | int ret; | |
808 | ||
e95433c7 CW |
809 | lockdep_assert_held(&obj->base.dev->struct_mutex); |
810 | ||
43394c7d CW |
811 | *needs_clflush = 0; |
812 | if (!i915_gem_object_has_struct_page(obj)) | |
813 | return -ENODEV; | |
814 | ||
e95433c7 CW |
815 | ret = i915_gem_object_wait(obj, |
816 | I915_WAIT_INTERRUPTIBLE | | |
817 | I915_WAIT_LOCKED | | |
818 | I915_WAIT_ALL, | |
819 | MAX_SCHEDULE_TIMEOUT, | |
820 | NULL); | |
43394c7d CW |
821 | if (ret) |
822 | return ret; | |
823 | ||
a4f5ea64 | 824 | ret = i915_gem_object_pin_pages(obj); |
9764951e CW |
825 | if (ret) |
826 | return ret; | |
827 | ||
a314d5cb CW |
828 | i915_gem_object_flush_gtt_write_domain(obj); |
829 | ||
43394c7d CW |
830 | /* If we're not in the cpu write domain, set ourself into the |
831 | * gtt write domain and manually flush cachelines (as required). | |
832 | * This optimizes for the case when the gpu will use the data | |
833 | * right away and we therefore have to clflush anyway. | |
834 | */ | |
835 | if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) | |
836 | *needs_clflush |= cpu_write_needs_clflush(obj) << 1; | |
837 | ||
838 | /* Same trick applies to invalidate partially written cachelines read | |
839 | * before writing. | |
840 | */ | |
841 | if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU)) | |
842 | *needs_clflush |= !cpu_cache_is_coherent(obj->base.dev, | |
843 | obj->cache_level); | |
844 | ||
43394c7d CW |
845 | if (*needs_clflush && !static_cpu_has(X86_FEATURE_CLFLUSH)) { |
846 | ret = i915_gem_object_set_to_cpu_domain(obj, true); | |
9764951e CW |
847 | if (ret) |
848 | goto err_unpin; | |
849 | ||
43394c7d CW |
850 | *needs_clflush = 0; |
851 | } | |
852 | ||
853 | if ((*needs_clflush & CLFLUSH_AFTER) == 0) | |
854 | obj->cache_dirty = true; | |
855 | ||
856 | intel_fb_obj_invalidate(obj, ORIGIN_CPU); | |
a4f5ea64 | 857 | obj->mm.dirty = true; |
9764951e | 858 | /* return with the pages pinned */ |
43394c7d | 859 | return 0; |
9764951e CW |
860 | |
861 | err_unpin: | |
862 | i915_gem_object_unpin_pages(obj); | |
863 | return ret; | |
4c914c0c BV |
864 | } |
865 | ||
23c18c71 DV |
866 | static void |
867 | shmem_clflush_swizzled_range(char *addr, unsigned long length, | |
868 | bool swizzled) | |
869 | { | |
e7e58eb5 | 870 | if (unlikely(swizzled)) { |
23c18c71 DV |
871 | unsigned long start = (unsigned long) addr; |
872 | unsigned long end = (unsigned long) addr + length; | |
873 | ||
874 | /* For swizzling simply ensure that we always flush both | |
875 | * channels. Lame, but simple and it works. Swizzled | |
876 | * pwrite/pread is far from a hotpath - current userspace | |
877 | * doesn't use it at all. */ | |
878 | start = round_down(start, 128); | |
879 | end = round_up(end, 128); | |
880 | ||
881 | drm_clflush_virt_range((void *)start, end - start); | |
882 | } else { | |
883 | drm_clflush_virt_range(addr, length); | |
884 | } | |
885 | ||
886 | } | |
887 | ||
d174bd64 DV |
888 | /* Only difference to the fast-path function is that this can handle bit17 |
889 | * and uses non-atomic copy and kmap functions. */ | |
890 | static int | |
bb6dc8d9 | 891 | shmem_pread_slow(struct page *page, int offset, int length, |
d174bd64 DV |
892 | char __user *user_data, |
893 | bool page_do_bit17_swizzling, bool needs_clflush) | |
894 | { | |
895 | char *vaddr; | |
896 | int ret; | |
897 | ||
898 | vaddr = kmap(page); | |
899 | if (needs_clflush) | |
bb6dc8d9 | 900 | shmem_clflush_swizzled_range(vaddr + offset, length, |
23c18c71 | 901 | page_do_bit17_swizzling); |
d174bd64 DV |
902 | |
903 | if (page_do_bit17_swizzling) | |
bb6dc8d9 | 904 | ret = __copy_to_user_swizzled(user_data, vaddr, offset, length); |
d174bd64 | 905 | else |
bb6dc8d9 | 906 | ret = __copy_to_user(user_data, vaddr + offset, length); |
d174bd64 DV |
907 | kunmap(page); |
908 | ||
f60d7f0c | 909 | return ret ? - EFAULT : 0; |
d174bd64 DV |
910 | } |
911 | ||
bb6dc8d9 CW |
912 | static int |
913 | shmem_pread(struct page *page, int offset, int length, char __user *user_data, | |
914 | bool page_do_bit17_swizzling, bool needs_clflush) | |
915 | { | |
916 | int ret; | |
917 | ||
918 | ret = -ENODEV; | |
919 | if (!page_do_bit17_swizzling) { | |
920 | char *vaddr = kmap_atomic(page); | |
921 | ||
922 | if (needs_clflush) | |
923 | drm_clflush_virt_range(vaddr + offset, length); | |
924 | ret = __copy_to_user_inatomic(user_data, vaddr + offset, length); | |
925 | kunmap_atomic(vaddr); | |
926 | } | |
927 | if (ret == 0) | |
928 | return 0; | |
929 | ||
930 | return shmem_pread_slow(page, offset, length, user_data, | |
931 | page_do_bit17_swizzling, needs_clflush); | |
932 | } | |
933 | ||
934 | static int | |
935 | i915_gem_shmem_pread(struct drm_i915_gem_object *obj, | |
936 | struct drm_i915_gem_pread *args) | |
937 | { | |
938 | char __user *user_data; | |
939 | u64 remain; | |
940 | unsigned int obj_do_bit17_swizzling; | |
941 | unsigned int needs_clflush; | |
942 | unsigned int idx, offset; | |
943 | int ret; | |
944 | ||
945 | obj_do_bit17_swizzling = 0; | |
946 | if (i915_gem_object_needs_bit17_swizzle(obj)) | |
947 | obj_do_bit17_swizzling = BIT(17); | |
948 | ||
949 | ret = mutex_lock_interruptible(&obj->base.dev->struct_mutex); | |
950 | if (ret) | |
951 | return ret; | |
952 | ||
953 | ret = i915_gem_obj_prepare_shmem_read(obj, &needs_clflush); | |
954 | mutex_unlock(&obj->base.dev->struct_mutex); | |
955 | if (ret) | |
956 | return ret; | |
957 | ||
958 | remain = args->size; | |
959 | user_data = u64_to_user_ptr(args->data_ptr); | |
960 | offset = offset_in_page(args->offset); | |
961 | for (idx = args->offset >> PAGE_SHIFT; remain; idx++) { | |
962 | struct page *page = i915_gem_object_get_page(obj, idx); | |
963 | int length; | |
964 | ||
965 | length = remain; | |
966 | if (offset + length > PAGE_SIZE) | |
967 | length = PAGE_SIZE - offset; | |
968 | ||
969 | ret = shmem_pread(page, offset, length, user_data, | |
970 | page_to_phys(page) & obj_do_bit17_swizzling, | |
971 | needs_clflush); | |
972 | if (ret) | |
973 | break; | |
974 | ||
975 | remain -= length; | |
976 | user_data += length; | |
977 | offset = 0; | |
978 | } | |
979 | ||
980 | i915_gem_obj_finish_shmem_access(obj); | |
981 | return ret; | |
982 | } | |
983 | ||
984 | static inline bool | |
985 | gtt_user_read(struct io_mapping *mapping, | |
986 | loff_t base, int offset, | |
987 | char __user *user_data, int length) | |
b50a5371 | 988 | { |
b50a5371 | 989 | void *vaddr; |
bb6dc8d9 | 990 | unsigned long unwritten; |
b50a5371 | 991 | |
b50a5371 | 992 | /* We can use the cpu mem copy function because this is X86. */ |
bb6dc8d9 CW |
993 | vaddr = (void __force *)io_mapping_map_atomic_wc(mapping, base); |
994 | unwritten = __copy_to_user_inatomic(user_data, vaddr + offset, length); | |
995 | io_mapping_unmap_atomic(vaddr); | |
996 | if (unwritten) { | |
997 | vaddr = (void __force *) | |
998 | io_mapping_map_wc(mapping, base, PAGE_SIZE); | |
999 | unwritten = copy_to_user(user_data, vaddr + offset, length); | |
1000 | io_mapping_unmap(vaddr); | |
1001 | } | |
b50a5371 AS |
1002 | return unwritten; |
1003 | } | |
1004 | ||
1005 | static int | |
bb6dc8d9 CW |
1006 | i915_gem_gtt_pread(struct drm_i915_gem_object *obj, |
1007 | const struct drm_i915_gem_pread *args) | |
b50a5371 | 1008 | { |
bb6dc8d9 CW |
1009 | struct drm_i915_private *i915 = to_i915(obj->base.dev); |
1010 | struct i915_ggtt *ggtt = &i915->ggtt; | |
b50a5371 | 1011 | struct drm_mm_node node; |
bb6dc8d9 CW |
1012 | struct i915_vma *vma; |
1013 | void __user *user_data; | |
1014 | u64 remain, offset; | |
b50a5371 AS |
1015 | int ret; |
1016 | ||
bb6dc8d9 CW |
1017 | ret = mutex_lock_interruptible(&i915->drm.struct_mutex); |
1018 | if (ret) | |
1019 | return ret; | |
1020 | ||
1021 | intel_runtime_pm_get(i915); | |
1022 | vma = i915_gem_object_ggtt_pin(obj, NULL, 0, 0, | |
1023 | PIN_MAPPABLE | PIN_NONBLOCK); | |
18034584 CW |
1024 | if (!IS_ERR(vma)) { |
1025 | node.start = i915_ggtt_offset(vma); | |
1026 | node.allocated = false; | |
49ef5294 | 1027 | ret = i915_vma_put_fence(vma); |
18034584 CW |
1028 | if (ret) { |
1029 | i915_vma_unpin(vma); | |
1030 | vma = ERR_PTR(ret); | |
1031 | } | |
1032 | } | |
058d88c4 | 1033 | if (IS_ERR(vma)) { |
bb6dc8d9 | 1034 | ret = insert_mappable_node(ggtt, &node, PAGE_SIZE); |
b50a5371 | 1035 | if (ret) |
bb6dc8d9 CW |
1036 | goto out_unlock; |
1037 | GEM_BUG_ON(!node.allocated); | |
b50a5371 AS |
1038 | } |
1039 | ||
1040 | ret = i915_gem_object_set_to_gtt_domain(obj, false); | |
1041 | if (ret) | |
1042 | goto out_unpin; | |
1043 | ||
bb6dc8d9 | 1044 | mutex_unlock(&i915->drm.struct_mutex); |
b50a5371 | 1045 | |
bb6dc8d9 CW |
1046 | user_data = u64_to_user_ptr(args->data_ptr); |
1047 | remain = args->size; | |
1048 | offset = args->offset; | |
b50a5371 AS |
1049 | |
1050 | while (remain > 0) { | |
1051 | /* Operation in this page | |
1052 | * | |
1053 | * page_base = page offset within aperture | |
1054 | * page_offset = offset within page | |
1055 | * page_length = bytes to copy for this page | |
1056 | */ | |
1057 | u32 page_base = node.start; | |
1058 | unsigned page_offset = offset_in_page(offset); | |
1059 | unsigned page_length = PAGE_SIZE - page_offset; | |
1060 | page_length = remain < page_length ? remain : page_length; | |
1061 | if (node.allocated) { | |
1062 | wmb(); | |
1063 | ggtt->base.insert_page(&ggtt->base, | |
1064 | i915_gem_object_get_dma_address(obj, offset >> PAGE_SHIFT), | |
bb6dc8d9 | 1065 | node.start, I915_CACHE_NONE, 0); |
b50a5371 AS |
1066 | wmb(); |
1067 | } else { | |
1068 | page_base += offset & PAGE_MASK; | |
1069 | } | |
bb6dc8d9 CW |
1070 | |
1071 | if (gtt_user_read(&ggtt->mappable, page_base, page_offset, | |
1072 | user_data, page_length)) { | |
b50a5371 AS |
1073 | ret = -EFAULT; |
1074 | break; | |
1075 | } | |
1076 | ||
1077 | remain -= page_length; | |
1078 | user_data += page_length; | |
1079 | offset += page_length; | |
1080 | } | |
1081 | ||
bb6dc8d9 | 1082 | mutex_lock(&i915->drm.struct_mutex); |
b50a5371 AS |
1083 | out_unpin: |
1084 | if (node.allocated) { | |
1085 | wmb(); | |
1086 | ggtt->base.clear_range(&ggtt->base, | |
4fb84d99 | 1087 | node.start, node.size); |
b50a5371 AS |
1088 | remove_mappable_node(&node); |
1089 | } else { | |
058d88c4 | 1090 | i915_vma_unpin(vma); |
b50a5371 | 1091 | } |
bb6dc8d9 CW |
1092 | out_unlock: |
1093 | intel_runtime_pm_put(i915); | |
1094 | mutex_unlock(&i915->drm.struct_mutex); | |
f60d7f0c | 1095 | |
eb01459f EA |
1096 | return ret; |
1097 | } | |
1098 | ||
673a394b EA |
1099 | /** |
1100 | * Reads data from the object referenced by handle. | |
14bb2c11 TU |
1101 | * @dev: drm device pointer |
1102 | * @data: ioctl data blob | |
1103 | * @file: drm file pointer | |
673a394b EA |
1104 | * |
1105 | * On error, the contents of *data are undefined. | |
1106 | */ | |
1107 | int | |
1108 | i915_gem_pread_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 1109 | struct drm_file *file) |
673a394b EA |
1110 | { |
1111 | struct drm_i915_gem_pread *args = data; | |
05394f39 | 1112 | struct drm_i915_gem_object *obj; |
bb6dc8d9 | 1113 | int ret; |
673a394b | 1114 | |
51311d0a CW |
1115 | if (args->size == 0) |
1116 | return 0; | |
1117 | ||
1118 | if (!access_ok(VERIFY_WRITE, | |
3ed605bc | 1119 | u64_to_user_ptr(args->data_ptr), |
51311d0a CW |
1120 | args->size)) |
1121 | return -EFAULT; | |
1122 | ||
03ac0642 | 1123 | obj = i915_gem_object_lookup(file, args->handle); |
258a5ede CW |
1124 | if (!obj) |
1125 | return -ENOENT; | |
673a394b | 1126 | |
7dcd2499 | 1127 | /* Bounds check source. */ |
05394f39 CW |
1128 | if (args->offset > obj->base.size || |
1129 | args->size > obj->base.size - args->offset) { | |
ce9d419d | 1130 | ret = -EINVAL; |
bb6dc8d9 | 1131 | goto out; |
ce9d419d CW |
1132 | } |
1133 | ||
db53a302 CW |
1134 | trace_i915_gem_object_pread(obj, args->offset, args->size); |
1135 | ||
e95433c7 CW |
1136 | ret = i915_gem_object_wait(obj, |
1137 | I915_WAIT_INTERRUPTIBLE, | |
1138 | MAX_SCHEDULE_TIMEOUT, | |
1139 | to_rps_client(file)); | |
258a5ede | 1140 | if (ret) |
bb6dc8d9 | 1141 | goto out; |
258a5ede | 1142 | |
bb6dc8d9 | 1143 | ret = i915_gem_object_pin_pages(obj); |
258a5ede | 1144 | if (ret) |
bb6dc8d9 | 1145 | goto out; |
673a394b | 1146 | |
bb6dc8d9 | 1147 | ret = i915_gem_shmem_pread(obj, args); |
9c870d03 | 1148 | if (ret == -EFAULT || ret == -ENODEV) |
bb6dc8d9 | 1149 | ret = i915_gem_gtt_pread(obj, args); |
b50a5371 | 1150 | |
bb6dc8d9 CW |
1151 | i915_gem_object_unpin_pages(obj); |
1152 | out: | |
f0cd5182 | 1153 | i915_gem_object_put(obj); |
eb01459f | 1154 | return ret; |
673a394b EA |
1155 | } |
1156 | ||
0839ccb8 KP |
1157 | /* This is the fast write path which cannot handle |
1158 | * page faults in the source data | |
9b7530cc | 1159 | */ |
0839ccb8 | 1160 | |
fe115628 CW |
1161 | static inline bool |
1162 | ggtt_write(struct io_mapping *mapping, | |
1163 | loff_t base, int offset, | |
1164 | char __user *user_data, int length) | |
9b7530cc | 1165 | { |
4f0c7cfb | 1166 | void *vaddr; |
0839ccb8 | 1167 | unsigned long unwritten; |
9b7530cc | 1168 | |
4f0c7cfb | 1169 | /* We can use the cpu mem copy function because this is X86. */ |
fe115628 CW |
1170 | vaddr = (void __force *)io_mapping_map_atomic_wc(mapping, base); |
1171 | unwritten = __copy_from_user_inatomic_nocache(vaddr + offset, | |
0839ccb8 | 1172 | user_data, length); |
fe115628 CW |
1173 | io_mapping_unmap_atomic(vaddr); |
1174 | if (unwritten) { | |
1175 | vaddr = (void __force *) | |
1176 | io_mapping_map_wc(mapping, base, PAGE_SIZE); | |
1177 | unwritten = copy_from_user(vaddr + offset, user_data, length); | |
1178 | io_mapping_unmap(vaddr); | |
1179 | } | |
bb6dc8d9 | 1180 | |
bb6dc8d9 CW |
1181 | return unwritten; |
1182 | } | |
1183 | ||
3de09aa3 EA |
1184 | /** |
1185 | * This is the fast pwrite path, where we copy the data directly from the | |
1186 | * user into the GTT, uncached. | |
fe115628 | 1187 | * @obj: i915 GEM object |
14bb2c11 | 1188 | * @args: pwrite arguments structure |
3de09aa3 | 1189 | */ |
673a394b | 1190 | static int |
fe115628 CW |
1191 | i915_gem_gtt_pwrite_fast(struct drm_i915_gem_object *obj, |
1192 | const struct drm_i915_gem_pwrite *args) | |
673a394b | 1193 | { |
fe115628 | 1194 | struct drm_i915_private *i915 = to_i915(obj->base.dev); |
4f1959ee AS |
1195 | struct i915_ggtt *ggtt = &i915->ggtt; |
1196 | struct drm_mm_node node; | |
fe115628 CW |
1197 | struct i915_vma *vma; |
1198 | u64 remain, offset; | |
1199 | void __user *user_data; | |
4f1959ee | 1200 | int ret; |
b50a5371 | 1201 | |
fe115628 CW |
1202 | ret = mutex_lock_interruptible(&i915->drm.struct_mutex); |
1203 | if (ret) | |
1204 | return ret; | |
935aaa69 | 1205 | |
9c870d03 | 1206 | intel_runtime_pm_get(i915); |
058d88c4 | 1207 | vma = i915_gem_object_ggtt_pin(obj, NULL, 0, 0, |
de895082 | 1208 | PIN_MAPPABLE | PIN_NONBLOCK); |
18034584 CW |
1209 | if (!IS_ERR(vma)) { |
1210 | node.start = i915_ggtt_offset(vma); | |
1211 | node.allocated = false; | |
49ef5294 | 1212 | ret = i915_vma_put_fence(vma); |
18034584 CW |
1213 | if (ret) { |
1214 | i915_vma_unpin(vma); | |
1215 | vma = ERR_PTR(ret); | |
1216 | } | |
1217 | } | |
058d88c4 | 1218 | if (IS_ERR(vma)) { |
bb6dc8d9 | 1219 | ret = insert_mappable_node(ggtt, &node, PAGE_SIZE); |
4f1959ee | 1220 | if (ret) |
fe115628 CW |
1221 | goto out_unlock; |
1222 | GEM_BUG_ON(!node.allocated); | |
4f1959ee | 1223 | } |
935aaa69 DV |
1224 | |
1225 | ret = i915_gem_object_set_to_gtt_domain(obj, true); | |
1226 | if (ret) | |
1227 | goto out_unpin; | |
1228 | ||
fe115628 CW |
1229 | mutex_unlock(&i915->drm.struct_mutex); |
1230 | ||
b19482d7 | 1231 | intel_fb_obj_invalidate(obj, ORIGIN_CPU); |
063e4e6b | 1232 | |
4f1959ee AS |
1233 | user_data = u64_to_user_ptr(args->data_ptr); |
1234 | offset = args->offset; | |
1235 | remain = args->size; | |
1236 | while (remain) { | |
673a394b EA |
1237 | /* Operation in this page |
1238 | * | |
0839ccb8 KP |
1239 | * page_base = page offset within aperture |
1240 | * page_offset = offset within page | |
1241 | * page_length = bytes to copy for this page | |
673a394b | 1242 | */ |
4f1959ee | 1243 | u32 page_base = node.start; |
bb6dc8d9 CW |
1244 | unsigned int page_offset = offset_in_page(offset); |
1245 | unsigned int page_length = PAGE_SIZE - page_offset; | |
4f1959ee AS |
1246 | page_length = remain < page_length ? remain : page_length; |
1247 | if (node.allocated) { | |
1248 | wmb(); /* flush the write before we modify the GGTT */ | |
1249 | ggtt->base.insert_page(&ggtt->base, | |
1250 | i915_gem_object_get_dma_address(obj, offset >> PAGE_SHIFT), | |
1251 | node.start, I915_CACHE_NONE, 0); | |
1252 | wmb(); /* flush modifications to the GGTT (insert_page) */ | |
1253 | } else { | |
1254 | page_base += offset & PAGE_MASK; | |
1255 | } | |
0839ccb8 | 1256 | /* If we get a fault while copying data, then (presumably) our |
3de09aa3 EA |
1257 | * source page isn't available. Return the error and we'll |
1258 | * retry in the slow path. | |
b50a5371 AS |
1259 | * If the object is non-shmem backed, we retry again with the |
1260 | * path that handles page fault. | |
0839ccb8 | 1261 | */ |
fe115628 CW |
1262 | if (ggtt_write(&ggtt->mappable, page_base, page_offset, |
1263 | user_data, page_length)) { | |
1264 | ret = -EFAULT; | |
1265 | break; | |
935aaa69 | 1266 | } |
673a394b | 1267 | |
0839ccb8 KP |
1268 | remain -= page_length; |
1269 | user_data += page_length; | |
1270 | offset += page_length; | |
673a394b | 1271 | } |
b19482d7 | 1272 | intel_fb_obj_flush(obj, false, ORIGIN_CPU); |
fe115628 CW |
1273 | |
1274 | mutex_lock(&i915->drm.struct_mutex); | |
935aaa69 | 1275 | out_unpin: |
4f1959ee AS |
1276 | if (node.allocated) { |
1277 | wmb(); | |
1278 | ggtt->base.clear_range(&ggtt->base, | |
4fb84d99 | 1279 | node.start, node.size); |
4f1959ee AS |
1280 | remove_mappable_node(&node); |
1281 | } else { | |
058d88c4 | 1282 | i915_vma_unpin(vma); |
4f1959ee | 1283 | } |
fe115628 | 1284 | out_unlock: |
9c870d03 | 1285 | intel_runtime_pm_put(i915); |
fe115628 | 1286 | mutex_unlock(&i915->drm.struct_mutex); |
3de09aa3 | 1287 | return ret; |
673a394b EA |
1288 | } |
1289 | ||
3043c60c | 1290 | static int |
fe115628 | 1291 | shmem_pwrite_slow(struct page *page, int offset, int length, |
d174bd64 DV |
1292 | char __user *user_data, |
1293 | bool page_do_bit17_swizzling, | |
1294 | bool needs_clflush_before, | |
1295 | bool needs_clflush_after) | |
673a394b | 1296 | { |
d174bd64 DV |
1297 | char *vaddr; |
1298 | int ret; | |
e5281ccd | 1299 | |
d174bd64 | 1300 | vaddr = kmap(page); |
e7e58eb5 | 1301 | if (unlikely(needs_clflush_before || page_do_bit17_swizzling)) |
fe115628 | 1302 | shmem_clflush_swizzled_range(vaddr + offset, length, |
23c18c71 | 1303 | page_do_bit17_swizzling); |
d174bd64 | 1304 | if (page_do_bit17_swizzling) |
fe115628 CW |
1305 | ret = __copy_from_user_swizzled(vaddr, offset, user_data, |
1306 | length); | |
d174bd64 | 1307 | else |
fe115628 | 1308 | ret = __copy_from_user(vaddr + offset, user_data, length); |
d174bd64 | 1309 | if (needs_clflush_after) |
fe115628 | 1310 | shmem_clflush_swizzled_range(vaddr + offset, length, |
23c18c71 | 1311 | page_do_bit17_swizzling); |
d174bd64 | 1312 | kunmap(page); |
40123c1f | 1313 | |
755d2218 | 1314 | return ret ? -EFAULT : 0; |
40123c1f EA |
1315 | } |
1316 | ||
fe115628 CW |
1317 | /* Per-page copy function for the shmem pwrite fastpath. |
1318 | * Flushes invalid cachelines before writing to the target if | |
1319 | * needs_clflush_before is set and flushes out any written cachelines after | |
1320 | * writing if needs_clflush is set. | |
1321 | */ | |
40123c1f | 1322 | static int |
fe115628 CW |
1323 | shmem_pwrite(struct page *page, int offset, int len, char __user *user_data, |
1324 | bool page_do_bit17_swizzling, | |
1325 | bool needs_clflush_before, | |
1326 | bool needs_clflush_after) | |
40123c1f | 1327 | { |
fe115628 CW |
1328 | int ret; |
1329 | ||
1330 | ret = -ENODEV; | |
1331 | if (!page_do_bit17_swizzling) { | |
1332 | char *vaddr = kmap_atomic(page); | |
1333 | ||
1334 | if (needs_clflush_before) | |
1335 | drm_clflush_virt_range(vaddr + offset, len); | |
1336 | ret = __copy_from_user_inatomic(vaddr + offset, user_data, len); | |
1337 | if (needs_clflush_after) | |
1338 | drm_clflush_virt_range(vaddr + offset, len); | |
1339 | ||
1340 | kunmap_atomic(vaddr); | |
1341 | } | |
1342 | if (ret == 0) | |
1343 | return ret; | |
1344 | ||
1345 | return shmem_pwrite_slow(page, offset, len, user_data, | |
1346 | page_do_bit17_swizzling, | |
1347 | needs_clflush_before, | |
1348 | needs_clflush_after); | |
1349 | } | |
1350 | ||
1351 | static int | |
1352 | i915_gem_shmem_pwrite(struct drm_i915_gem_object *obj, | |
1353 | const struct drm_i915_gem_pwrite *args) | |
1354 | { | |
1355 | struct drm_i915_private *i915 = to_i915(obj->base.dev); | |
1356 | void __user *user_data; | |
1357 | u64 remain; | |
1358 | unsigned int obj_do_bit17_swizzling; | |
1359 | unsigned int partial_cacheline_write; | |
43394c7d | 1360 | unsigned int needs_clflush; |
fe115628 CW |
1361 | unsigned int offset, idx; |
1362 | int ret; | |
40123c1f | 1363 | |
fe115628 | 1364 | ret = mutex_lock_interruptible(&i915->drm.struct_mutex); |
755d2218 CW |
1365 | if (ret) |
1366 | return ret; | |
1367 | ||
fe115628 CW |
1368 | ret = i915_gem_obj_prepare_shmem_write(obj, &needs_clflush); |
1369 | mutex_unlock(&i915->drm.struct_mutex); | |
1370 | if (ret) | |
1371 | return ret; | |
673a394b | 1372 | |
fe115628 CW |
1373 | obj_do_bit17_swizzling = 0; |
1374 | if (i915_gem_object_needs_bit17_swizzle(obj)) | |
1375 | obj_do_bit17_swizzling = BIT(17); | |
e5281ccd | 1376 | |
fe115628 CW |
1377 | /* If we don't overwrite a cacheline completely we need to be |
1378 | * careful to have up-to-date data by first clflushing. Don't | |
1379 | * overcomplicate things and flush the entire patch. | |
1380 | */ | |
1381 | partial_cacheline_write = 0; | |
1382 | if (needs_clflush & CLFLUSH_BEFORE) | |
1383 | partial_cacheline_write = boot_cpu_data.x86_clflush_size - 1; | |
9da3da66 | 1384 | |
fe115628 CW |
1385 | user_data = u64_to_user_ptr(args->data_ptr); |
1386 | remain = args->size; | |
1387 | offset = offset_in_page(args->offset); | |
1388 | for (idx = args->offset >> PAGE_SHIFT; remain; idx++) { | |
1389 | struct page *page = i915_gem_object_get_page(obj, idx); | |
1390 | int length; | |
40123c1f | 1391 | |
fe115628 CW |
1392 | length = remain; |
1393 | if (offset + length > PAGE_SIZE) | |
1394 | length = PAGE_SIZE - offset; | |
755d2218 | 1395 | |
fe115628 CW |
1396 | ret = shmem_pwrite(page, offset, length, user_data, |
1397 | page_to_phys(page) & obj_do_bit17_swizzling, | |
1398 | (offset | length) & partial_cacheline_write, | |
1399 | needs_clflush & CLFLUSH_AFTER); | |
755d2218 | 1400 | if (ret) |
fe115628 | 1401 | break; |
755d2218 | 1402 | |
fe115628 CW |
1403 | remain -= length; |
1404 | user_data += length; | |
1405 | offset = 0; | |
8c59967c | 1406 | } |
673a394b | 1407 | |
de152b62 | 1408 | intel_fb_obj_flush(obj, false, ORIGIN_CPU); |
fe115628 | 1409 | i915_gem_obj_finish_shmem_access(obj); |
40123c1f | 1410 | return ret; |
673a394b EA |
1411 | } |
1412 | ||
1413 | /** | |
1414 | * Writes data to the object referenced by handle. | |
14bb2c11 TU |
1415 | * @dev: drm device |
1416 | * @data: ioctl data blob | |
1417 | * @file: drm file | |
673a394b EA |
1418 | * |
1419 | * On error, the contents of the buffer that were to be modified are undefined. | |
1420 | */ | |
1421 | int | |
1422 | i915_gem_pwrite_ioctl(struct drm_device *dev, void *data, | |
fbd5a26d | 1423 | struct drm_file *file) |
673a394b EA |
1424 | { |
1425 | struct drm_i915_gem_pwrite *args = data; | |
05394f39 | 1426 | struct drm_i915_gem_object *obj; |
51311d0a CW |
1427 | int ret; |
1428 | ||
1429 | if (args->size == 0) | |
1430 | return 0; | |
1431 | ||
1432 | if (!access_ok(VERIFY_READ, | |
3ed605bc | 1433 | u64_to_user_ptr(args->data_ptr), |
51311d0a CW |
1434 | args->size)) |
1435 | return -EFAULT; | |
1436 | ||
03ac0642 | 1437 | obj = i915_gem_object_lookup(file, args->handle); |
258a5ede CW |
1438 | if (!obj) |
1439 | return -ENOENT; | |
673a394b | 1440 | |
7dcd2499 | 1441 | /* Bounds check destination. */ |
05394f39 CW |
1442 | if (args->offset > obj->base.size || |
1443 | args->size > obj->base.size - args->offset) { | |
ce9d419d | 1444 | ret = -EINVAL; |
258a5ede | 1445 | goto err; |
ce9d419d CW |
1446 | } |
1447 | ||
db53a302 CW |
1448 | trace_i915_gem_object_pwrite(obj, args->offset, args->size); |
1449 | ||
e95433c7 CW |
1450 | ret = i915_gem_object_wait(obj, |
1451 | I915_WAIT_INTERRUPTIBLE | | |
1452 | I915_WAIT_ALL, | |
1453 | MAX_SCHEDULE_TIMEOUT, | |
1454 | to_rps_client(file)); | |
258a5ede CW |
1455 | if (ret) |
1456 | goto err; | |
1457 | ||
fe115628 | 1458 | ret = i915_gem_object_pin_pages(obj); |
258a5ede | 1459 | if (ret) |
fe115628 | 1460 | goto err; |
258a5ede | 1461 | |
935aaa69 | 1462 | ret = -EFAULT; |
673a394b EA |
1463 | /* We can only do the GTT pwrite on untiled buffers, as otherwise |
1464 | * it would end up going through the fenced access, and we'll get | |
1465 | * different detiling behavior between reading and writing. | |
1466 | * pread/pwrite currently are reading and writing from the CPU | |
1467 | * perspective, requiring manual detiling by the client. | |
1468 | */ | |
6eae0059 | 1469 | if (!i915_gem_object_has_struct_page(obj) || |
9c870d03 | 1470 | cpu_write_needs_clflush(obj)) |
935aaa69 DV |
1471 | /* Note that the gtt paths might fail with non-page-backed user |
1472 | * pointers (e.g. gtt mappings when moving data between | |
9c870d03 CW |
1473 | * textures). Fallback to the shmem path in that case. |
1474 | */ | |
fe115628 | 1475 | ret = i915_gem_gtt_pwrite_fast(obj, args); |
673a394b | 1476 | |
d1054ee4 | 1477 | if (ret == -EFAULT || ret == -ENOSPC) { |
6a2c4232 CW |
1478 | if (obj->phys_handle) |
1479 | ret = i915_gem_phys_pwrite(obj, args, file); | |
b50a5371 | 1480 | else |
fe115628 | 1481 | ret = i915_gem_shmem_pwrite(obj, args); |
6a2c4232 | 1482 | } |
5c0480f2 | 1483 | |
fe115628 | 1484 | i915_gem_object_unpin_pages(obj); |
258a5ede | 1485 | err: |
f0cd5182 | 1486 | i915_gem_object_put(obj); |
258a5ede | 1487 | return ret; |
673a394b EA |
1488 | } |
1489 | ||
d243ad82 | 1490 | static inline enum fb_op_origin |
aeecc969 CW |
1491 | write_origin(struct drm_i915_gem_object *obj, unsigned domain) |
1492 | { | |
50349247 CW |
1493 | return (domain == I915_GEM_DOMAIN_GTT ? |
1494 | obj->frontbuffer_ggtt_origin : ORIGIN_CPU); | |
aeecc969 CW |
1495 | } |
1496 | ||
40e62d5d CW |
1497 | static void i915_gem_object_bump_inactive_ggtt(struct drm_i915_gem_object *obj) |
1498 | { | |
1499 | struct drm_i915_private *i915; | |
1500 | struct list_head *list; | |
1501 | struct i915_vma *vma; | |
1502 | ||
1503 | list_for_each_entry(vma, &obj->vma_list, obj_link) { | |
1504 | if (!i915_vma_is_ggtt(vma)) | |
1505 | continue; | |
1506 | ||
1507 | if (i915_vma_is_active(vma)) | |
1508 | continue; | |
1509 | ||
1510 | if (!drm_mm_node_allocated(&vma->node)) | |
1511 | continue; | |
1512 | ||
1513 | list_move_tail(&vma->vm_link, &vma->vm->inactive_list); | |
1514 | } | |
1515 | ||
1516 | i915 = to_i915(obj->base.dev); | |
1517 | list = obj->bind_count ? &i915->mm.bound_list : &i915->mm.unbound_list; | |
56cea323 | 1518 | list_move_tail(&obj->global_link, list); |
40e62d5d CW |
1519 | } |
1520 | ||
673a394b | 1521 | /** |
2ef7eeaa EA |
1522 | * Called when user space prepares to use an object with the CPU, either |
1523 | * through the mmap ioctl's mapping or a GTT mapping. | |
14bb2c11 TU |
1524 | * @dev: drm device |
1525 | * @data: ioctl data blob | |
1526 | * @file: drm file | |
673a394b EA |
1527 | */ |
1528 | int | |
1529 | i915_gem_set_domain_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 1530 | struct drm_file *file) |
673a394b EA |
1531 | { |
1532 | struct drm_i915_gem_set_domain *args = data; | |
05394f39 | 1533 | struct drm_i915_gem_object *obj; |
2ef7eeaa EA |
1534 | uint32_t read_domains = args->read_domains; |
1535 | uint32_t write_domain = args->write_domain; | |
40e62d5d | 1536 | int err; |
673a394b | 1537 | |
2ef7eeaa | 1538 | /* Only handle setting domains to types used by the CPU. */ |
b8f9096d | 1539 | if ((write_domain | read_domains) & I915_GEM_GPU_DOMAINS) |
2ef7eeaa EA |
1540 | return -EINVAL; |
1541 | ||
1542 | /* Having something in the write domain implies it's in the read | |
1543 | * domain, and only that read domain. Enforce that in the request. | |
1544 | */ | |
1545 | if (write_domain != 0 && read_domains != write_domain) | |
1546 | return -EINVAL; | |
1547 | ||
03ac0642 | 1548 | obj = i915_gem_object_lookup(file, args->handle); |
b8f9096d CW |
1549 | if (!obj) |
1550 | return -ENOENT; | |
673a394b | 1551 | |
3236f57a CW |
1552 | /* Try to flush the object off the GPU without holding the lock. |
1553 | * We will repeat the flush holding the lock in the normal manner | |
1554 | * to catch cases where we are gazumped. | |
1555 | */ | |
40e62d5d | 1556 | err = i915_gem_object_wait(obj, |
e95433c7 CW |
1557 | I915_WAIT_INTERRUPTIBLE | |
1558 | (write_domain ? I915_WAIT_ALL : 0), | |
1559 | MAX_SCHEDULE_TIMEOUT, | |
1560 | to_rps_client(file)); | |
40e62d5d | 1561 | if (err) |
f0cd5182 | 1562 | goto out; |
b8f9096d | 1563 | |
40e62d5d CW |
1564 | /* Flush and acquire obj->pages so that we are coherent through |
1565 | * direct access in memory with previous cached writes through | |
1566 | * shmemfs and that our cache domain tracking remains valid. | |
1567 | * For example, if the obj->filp was moved to swap without us | |
1568 | * being notified and releasing the pages, we would mistakenly | |
1569 | * continue to assume that the obj remained out of the CPU cached | |
1570 | * domain. | |
1571 | */ | |
1572 | err = i915_gem_object_pin_pages(obj); | |
1573 | if (err) | |
f0cd5182 | 1574 | goto out; |
40e62d5d CW |
1575 | |
1576 | err = i915_mutex_lock_interruptible(dev); | |
1577 | if (err) | |
f0cd5182 | 1578 | goto out_unpin; |
3236f57a | 1579 | |
43566ded | 1580 | if (read_domains & I915_GEM_DOMAIN_GTT) |
40e62d5d | 1581 | err = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0); |
43566ded | 1582 | else |
40e62d5d | 1583 | err = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0); |
2ef7eeaa | 1584 | |
40e62d5d CW |
1585 | /* And bump the LRU for this access */ |
1586 | i915_gem_object_bump_inactive_ggtt(obj); | |
031b698a | 1587 | |
673a394b | 1588 | mutex_unlock(&dev->struct_mutex); |
b8f9096d | 1589 | |
40e62d5d CW |
1590 | if (write_domain != 0) |
1591 | intel_fb_obj_invalidate(obj, write_origin(obj, write_domain)); | |
1592 | ||
f0cd5182 | 1593 | out_unpin: |
40e62d5d | 1594 | i915_gem_object_unpin_pages(obj); |
f0cd5182 CW |
1595 | out: |
1596 | i915_gem_object_put(obj); | |
40e62d5d | 1597 | return err; |
673a394b EA |
1598 | } |
1599 | ||
1600 | /** | |
1601 | * Called when user space has done writes to this buffer | |
14bb2c11 TU |
1602 | * @dev: drm device |
1603 | * @data: ioctl data blob | |
1604 | * @file: drm file | |
673a394b EA |
1605 | */ |
1606 | int | |
1607 | i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 1608 | struct drm_file *file) |
673a394b EA |
1609 | { |
1610 | struct drm_i915_gem_sw_finish *args = data; | |
05394f39 | 1611 | struct drm_i915_gem_object *obj; |
c21724cc | 1612 | int err = 0; |
1d7cfea1 | 1613 | |
03ac0642 | 1614 | obj = i915_gem_object_lookup(file, args->handle); |
c21724cc CW |
1615 | if (!obj) |
1616 | return -ENOENT; | |
673a394b | 1617 | |
673a394b | 1618 | /* Pinned buffers may be scanout, so flush the cache */ |
c21724cc CW |
1619 | if (READ_ONCE(obj->pin_display)) { |
1620 | err = i915_mutex_lock_interruptible(dev); | |
1621 | if (!err) { | |
1622 | i915_gem_object_flush_cpu_write_domain(obj); | |
1623 | mutex_unlock(&dev->struct_mutex); | |
1624 | } | |
1625 | } | |
e47c68e9 | 1626 | |
f0cd5182 | 1627 | i915_gem_object_put(obj); |
c21724cc | 1628 | return err; |
673a394b EA |
1629 | } |
1630 | ||
1631 | /** | |
14bb2c11 TU |
1632 | * i915_gem_mmap_ioctl - Maps the contents of an object, returning the address |
1633 | * it is mapped to. | |
1634 | * @dev: drm device | |
1635 | * @data: ioctl data blob | |
1636 | * @file: drm file | |
673a394b EA |
1637 | * |
1638 | * While the mapping holds a reference on the contents of the object, it doesn't | |
1639 | * imply a ref on the object itself. | |
34367381 DV |
1640 | * |
1641 | * IMPORTANT: | |
1642 | * | |
1643 | * DRM driver writers who look a this function as an example for how to do GEM | |
1644 | * mmap support, please don't implement mmap support like here. The modern way | |
1645 | * to implement DRM mmap support is with an mmap offset ioctl (like | |
1646 | * i915_gem_mmap_gtt) and then using the mmap syscall on the DRM fd directly. | |
1647 | * That way debug tooling like valgrind will understand what's going on, hiding | |
1648 | * the mmap call in a driver private ioctl will break that. The i915 driver only | |
1649 | * does cpu mmaps this way because we didn't know better. | |
673a394b EA |
1650 | */ |
1651 | int | |
1652 | i915_gem_mmap_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 1653 | struct drm_file *file) |
673a394b EA |
1654 | { |
1655 | struct drm_i915_gem_mmap *args = data; | |
03ac0642 | 1656 | struct drm_i915_gem_object *obj; |
673a394b EA |
1657 | unsigned long addr; |
1658 | ||
1816f923 AG |
1659 | if (args->flags & ~(I915_MMAP_WC)) |
1660 | return -EINVAL; | |
1661 | ||
568a58e5 | 1662 | if (args->flags & I915_MMAP_WC && !boot_cpu_has(X86_FEATURE_PAT)) |
1816f923 AG |
1663 | return -ENODEV; |
1664 | ||
03ac0642 CW |
1665 | obj = i915_gem_object_lookup(file, args->handle); |
1666 | if (!obj) | |
bf79cb91 | 1667 | return -ENOENT; |
673a394b | 1668 | |
1286ff73 DV |
1669 | /* prime objects have no backing filp to GEM mmap |
1670 | * pages from. | |
1671 | */ | |
03ac0642 | 1672 | if (!obj->base.filp) { |
f0cd5182 | 1673 | i915_gem_object_put(obj); |
1286ff73 DV |
1674 | return -EINVAL; |
1675 | } | |
1676 | ||
03ac0642 | 1677 | addr = vm_mmap(obj->base.filp, 0, args->size, |
673a394b EA |
1678 | PROT_READ | PROT_WRITE, MAP_SHARED, |
1679 | args->offset); | |
1816f923 AG |
1680 | if (args->flags & I915_MMAP_WC) { |
1681 | struct mm_struct *mm = current->mm; | |
1682 | struct vm_area_struct *vma; | |
1683 | ||
80a89a5e | 1684 | if (down_write_killable(&mm->mmap_sem)) { |
f0cd5182 | 1685 | i915_gem_object_put(obj); |
80a89a5e MH |
1686 | return -EINTR; |
1687 | } | |
1816f923 AG |
1688 | vma = find_vma(mm, addr); |
1689 | if (vma) | |
1690 | vma->vm_page_prot = | |
1691 | pgprot_writecombine(vm_get_page_prot(vma->vm_flags)); | |
1692 | else | |
1693 | addr = -ENOMEM; | |
1694 | up_write(&mm->mmap_sem); | |
aeecc969 CW |
1695 | |
1696 | /* This may race, but that's ok, it only gets set */ | |
50349247 | 1697 | WRITE_ONCE(obj->frontbuffer_ggtt_origin, ORIGIN_CPU); |
1816f923 | 1698 | } |
f0cd5182 | 1699 | i915_gem_object_put(obj); |
673a394b EA |
1700 | if (IS_ERR((void *)addr)) |
1701 | return addr; | |
1702 | ||
1703 | args->addr_ptr = (uint64_t) addr; | |
1704 | ||
1705 | return 0; | |
1706 | } | |
1707 | ||
03af84fe CW |
1708 | static unsigned int tile_row_pages(struct drm_i915_gem_object *obj) |
1709 | { | |
1710 | u64 size; | |
1711 | ||
1712 | size = i915_gem_object_get_stride(obj); | |
1713 | size *= i915_gem_object_get_tiling(obj) == I915_TILING_Y ? 32 : 8; | |
1714 | ||
1715 | return size >> PAGE_SHIFT; | |
1716 | } | |
1717 | ||
4cc69075 CW |
1718 | /** |
1719 | * i915_gem_mmap_gtt_version - report the current feature set for GTT mmaps | |
1720 | * | |
1721 | * A history of the GTT mmap interface: | |
1722 | * | |
1723 | * 0 - Everything had to fit into the GTT. Both parties of a memcpy had to | |
1724 | * aligned and suitable for fencing, and still fit into the available | |
1725 | * mappable space left by the pinned display objects. A classic problem | |
1726 | * we called the page-fault-of-doom where we would ping-pong between | |
1727 | * two objects that could not fit inside the GTT and so the memcpy | |
1728 | * would page one object in at the expense of the other between every | |
1729 | * single byte. | |
1730 | * | |
1731 | * 1 - Objects can be any size, and have any compatible fencing (X Y, or none | |
1732 | * as set via i915_gem_set_tiling() [DRM_I915_GEM_SET_TILING]). If the | |
1733 | * object is too large for the available space (or simply too large | |
1734 | * for the mappable aperture!), a view is created instead and faulted | |
1735 | * into userspace. (This view is aligned and sized appropriately for | |
1736 | * fenced access.) | |
1737 | * | |
1738 | * Restrictions: | |
1739 | * | |
1740 | * * snoopable objects cannot be accessed via the GTT. It can cause machine | |
1741 | * hangs on some architectures, corruption on others. An attempt to service | |
1742 | * a GTT page fault from a snoopable object will generate a SIGBUS. | |
1743 | * | |
1744 | * * the object must be able to fit into RAM (physical memory, though no | |
1745 | * limited to the mappable aperture). | |
1746 | * | |
1747 | * | |
1748 | * Caveats: | |
1749 | * | |
1750 | * * a new GTT page fault will synchronize rendering from the GPU and flush | |
1751 | * all data to system memory. Subsequent access will not be synchronized. | |
1752 | * | |
1753 | * * all mappings are revoked on runtime device suspend. | |
1754 | * | |
1755 | * * there are only 8, 16 or 32 fence registers to share between all users | |
1756 | * (older machines require fence register for display and blitter access | |
1757 | * as well). Contention of the fence registers will cause the previous users | |
1758 | * to be unmapped and any new access will generate new page faults. | |
1759 | * | |
1760 | * * running out of memory while servicing a fault may generate a SIGBUS, | |
1761 | * rather than the expected SIGSEGV. | |
1762 | */ | |
1763 | int i915_gem_mmap_gtt_version(void) | |
1764 | { | |
1765 | return 1; | |
1766 | } | |
1767 | ||
de151cf6 JB |
1768 | /** |
1769 | * i915_gem_fault - fault a page into the GTT | |
058d88c4 | 1770 | * @area: CPU VMA in question |
d9072a3e | 1771 | * @vmf: fault info |
de151cf6 JB |
1772 | * |
1773 | * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped | |
1774 | * from userspace. The fault handler takes care of binding the object to | |
1775 | * the GTT (if needed), allocating and programming a fence register (again, | |
1776 | * only if needed based on whether the old reg is still valid or the object | |
1777 | * is tiled) and inserting a new PTE into the faulting process. | |
1778 | * | |
1779 | * Note that the faulting process may involve evicting existing objects | |
1780 | * from the GTT and/or fence registers to make room. So performance may | |
1781 | * suffer if the GTT working set is large or there are few fence registers | |
1782 | * left. | |
4cc69075 CW |
1783 | * |
1784 | * The current feature set supported by i915_gem_fault() and thus GTT mmaps | |
1785 | * is exposed via I915_PARAM_MMAP_GTT_VERSION (see i915_gem_mmap_gtt_version). | |
de151cf6 | 1786 | */ |
058d88c4 | 1787 | int i915_gem_fault(struct vm_area_struct *area, struct vm_fault *vmf) |
de151cf6 | 1788 | { |
03af84fe | 1789 | #define MIN_CHUNK_PAGES ((1 << 20) >> PAGE_SHIFT) /* 1 MiB */ |
058d88c4 | 1790 | struct drm_i915_gem_object *obj = to_intel_bo(area->vm_private_data); |
05394f39 | 1791 | struct drm_device *dev = obj->base.dev; |
72e96d64 JL |
1792 | struct drm_i915_private *dev_priv = to_i915(dev); |
1793 | struct i915_ggtt *ggtt = &dev_priv->ggtt; | |
b8f9096d | 1794 | bool write = !!(vmf->flags & FAULT_FLAG_WRITE); |
058d88c4 | 1795 | struct i915_vma *vma; |
de151cf6 | 1796 | pgoff_t page_offset; |
82118877 | 1797 | unsigned int flags; |
b8f9096d | 1798 | int ret; |
f65c9168 | 1799 | |
de151cf6 | 1800 | /* We don't use vmf->pgoff since that has the fake offset */ |
058d88c4 | 1801 | page_offset = ((unsigned long)vmf->virtual_address - area->vm_start) >> |
de151cf6 JB |
1802 | PAGE_SHIFT; |
1803 | ||
db53a302 CW |
1804 | trace_i915_gem_object_fault(obj, page_offset, true, write); |
1805 | ||
6e4930f6 | 1806 | /* Try to flush the object off the GPU first without holding the lock. |
b8f9096d | 1807 | * Upon acquiring the lock, we will perform our sanity checks and then |
6e4930f6 CW |
1808 | * repeat the flush holding the lock in the normal manner to catch cases |
1809 | * where we are gazumped. | |
1810 | */ | |
e95433c7 CW |
1811 | ret = i915_gem_object_wait(obj, |
1812 | I915_WAIT_INTERRUPTIBLE, | |
1813 | MAX_SCHEDULE_TIMEOUT, | |
1814 | NULL); | |
6e4930f6 | 1815 | if (ret) |
b8f9096d CW |
1816 | goto err; |
1817 | ||
40e62d5d CW |
1818 | ret = i915_gem_object_pin_pages(obj); |
1819 | if (ret) | |
1820 | goto err; | |
1821 | ||
b8f9096d CW |
1822 | intel_runtime_pm_get(dev_priv); |
1823 | ||
1824 | ret = i915_mutex_lock_interruptible(dev); | |
1825 | if (ret) | |
1826 | goto err_rpm; | |
6e4930f6 | 1827 | |
eb119bd6 | 1828 | /* Access to snoopable pages through the GTT is incoherent. */ |
0031fb96 | 1829 | if (obj->cache_level != I915_CACHE_NONE && !HAS_LLC(dev_priv)) { |
ddeff6ee | 1830 | ret = -EFAULT; |
b8f9096d | 1831 | goto err_unlock; |
eb119bd6 CW |
1832 | } |
1833 | ||
82118877 CW |
1834 | /* If the object is smaller than a couple of partial vma, it is |
1835 | * not worth only creating a single partial vma - we may as well | |
1836 | * clear enough space for the full object. | |
1837 | */ | |
1838 | flags = PIN_MAPPABLE; | |
1839 | if (obj->base.size > 2 * MIN_CHUNK_PAGES << PAGE_SHIFT) | |
1840 | flags |= PIN_NONBLOCK | PIN_NONFAULT; | |
1841 | ||
a61007a8 | 1842 | /* Now pin it into the GTT as needed */ |
82118877 | 1843 | vma = i915_gem_object_ggtt_pin(obj, NULL, 0, 0, flags); |
a61007a8 CW |
1844 | if (IS_ERR(vma)) { |
1845 | struct i915_ggtt_view view; | |
03af84fe CW |
1846 | unsigned int chunk_size; |
1847 | ||
a61007a8 | 1848 | /* Use a partial view if it is bigger than available space */ |
03af84fe CW |
1849 | chunk_size = MIN_CHUNK_PAGES; |
1850 | if (i915_gem_object_is_tiled(obj)) | |
0ef723cb | 1851 | chunk_size = roundup(chunk_size, tile_row_pages(obj)); |
e7ded2d7 | 1852 | |
c5ad54cf JL |
1853 | memset(&view, 0, sizeof(view)); |
1854 | view.type = I915_GGTT_VIEW_PARTIAL; | |
1855 | view.params.partial.offset = rounddown(page_offset, chunk_size); | |
1856 | view.params.partial.size = | |
a61007a8 | 1857 | min_t(unsigned int, chunk_size, |
908b1232 | 1858 | vma_pages(area) - view.params.partial.offset); |
c5ad54cf | 1859 | |
aa136d9d CW |
1860 | /* If the partial covers the entire object, just create a |
1861 | * normal VMA. | |
1862 | */ | |
1863 | if (chunk_size >= obj->base.size >> PAGE_SHIFT) | |
1864 | view.type = I915_GGTT_VIEW_NORMAL; | |
1865 | ||
50349247 CW |
1866 | /* Userspace is now writing through an untracked VMA, abandon |
1867 | * all hope that the hardware is able to track future writes. | |
1868 | */ | |
1869 | obj->frontbuffer_ggtt_origin = ORIGIN_CPU; | |
1870 | ||
a61007a8 CW |
1871 | vma = i915_gem_object_ggtt_pin(obj, &view, 0, 0, PIN_MAPPABLE); |
1872 | } | |
058d88c4 CW |
1873 | if (IS_ERR(vma)) { |
1874 | ret = PTR_ERR(vma); | |
b8f9096d | 1875 | goto err_unlock; |
058d88c4 | 1876 | } |
4a684a41 | 1877 | |
c9839303 CW |
1878 | ret = i915_gem_object_set_to_gtt_domain(obj, write); |
1879 | if (ret) | |
b8f9096d | 1880 | goto err_unpin; |
74898d7e | 1881 | |
49ef5294 | 1882 | ret = i915_vma_get_fence(vma); |
d9e86c0e | 1883 | if (ret) |
b8f9096d | 1884 | goto err_unpin; |
7d1c4804 | 1885 | |
275f039d | 1886 | /* Mark as being mmapped into userspace for later revocation */ |
9c870d03 | 1887 | assert_rpm_wakelock_held(dev_priv); |
275f039d CW |
1888 | if (list_empty(&obj->userfault_link)) |
1889 | list_add(&obj->userfault_link, &dev_priv->mm.userfault_list); | |
275f039d | 1890 | |
b90b91d8 | 1891 | /* Finally, remap it using the new GTT offset */ |
c58305af CW |
1892 | ret = remap_io_mapping(area, |
1893 | area->vm_start + (vma->ggtt_view.params.partial.offset << PAGE_SHIFT), | |
1894 | (ggtt->mappable_base + vma->node.start) >> PAGE_SHIFT, | |
1895 | min_t(u64, vma->size, area->vm_end - area->vm_start), | |
1896 | &ggtt->mappable); | |
a61007a8 | 1897 | |
b8f9096d | 1898 | err_unpin: |
058d88c4 | 1899 | __i915_vma_unpin(vma); |
b8f9096d | 1900 | err_unlock: |
de151cf6 | 1901 | mutex_unlock(&dev->struct_mutex); |
b8f9096d CW |
1902 | err_rpm: |
1903 | intel_runtime_pm_put(dev_priv); | |
40e62d5d | 1904 | i915_gem_object_unpin_pages(obj); |
b8f9096d | 1905 | err: |
de151cf6 | 1906 | switch (ret) { |
d9bc7e9f | 1907 | case -EIO: |
2232f031 DV |
1908 | /* |
1909 | * We eat errors when the gpu is terminally wedged to avoid | |
1910 | * userspace unduly crashing (gl has no provisions for mmaps to | |
1911 | * fail). But any other -EIO isn't ours (e.g. swap in failure) | |
1912 | * and so needs to be reported. | |
1913 | */ | |
1914 | if (!i915_terminally_wedged(&dev_priv->gpu_error)) { | |
f65c9168 PZ |
1915 | ret = VM_FAULT_SIGBUS; |
1916 | break; | |
1917 | } | |
045e769a | 1918 | case -EAGAIN: |
571c608d DV |
1919 | /* |
1920 | * EAGAIN means the gpu is hung and we'll wait for the error | |
1921 | * handler to reset everything when re-faulting in | |
1922 | * i915_mutex_lock_interruptible. | |
d9bc7e9f | 1923 | */ |
c715089f CW |
1924 | case 0: |
1925 | case -ERESTARTSYS: | |
bed636ab | 1926 | case -EINTR: |
e79e0fe3 DR |
1927 | case -EBUSY: |
1928 | /* | |
1929 | * EBUSY is ok: this just means that another thread | |
1930 | * already did the job. | |
1931 | */ | |
f65c9168 PZ |
1932 | ret = VM_FAULT_NOPAGE; |
1933 | break; | |
de151cf6 | 1934 | case -ENOMEM: |
f65c9168 PZ |
1935 | ret = VM_FAULT_OOM; |
1936 | break; | |
a7c2e1aa | 1937 | case -ENOSPC: |
45d67817 | 1938 | case -EFAULT: |
f65c9168 PZ |
1939 | ret = VM_FAULT_SIGBUS; |
1940 | break; | |
de151cf6 | 1941 | default: |
a7c2e1aa | 1942 | WARN_ONCE(ret, "unhandled error in i915_gem_fault: %i\n", ret); |
f65c9168 PZ |
1943 | ret = VM_FAULT_SIGBUS; |
1944 | break; | |
de151cf6 | 1945 | } |
f65c9168 | 1946 | return ret; |
de151cf6 JB |
1947 | } |
1948 | ||
901782b2 CW |
1949 | /** |
1950 | * i915_gem_release_mmap - remove physical page mappings | |
1951 | * @obj: obj in question | |
1952 | * | |
af901ca1 | 1953 | * Preserve the reservation of the mmapping with the DRM core code, but |
901782b2 CW |
1954 | * relinquish ownership of the pages back to the system. |
1955 | * | |
1956 | * It is vital that we remove the page mapping if we have mapped a tiled | |
1957 | * object through the GTT and then lose the fence register due to | |
1958 | * resource pressure. Similarly if the object has been moved out of the | |
1959 | * aperture, than pages mapped into userspace must be revoked. Removing the | |
1960 | * mapping will then trigger a page fault on the next user access, allowing | |
1961 | * fixup by i915_gem_fault(). | |
1962 | */ | |
d05ca301 | 1963 | void |
05394f39 | 1964 | i915_gem_release_mmap(struct drm_i915_gem_object *obj) |
901782b2 | 1965 | { |
275f039d | 1966 | struct drm_i915_private *i915 = to_i915(obj->base.dev); |
275f039d | 1967 | |
349f2ccf CW |
1968 | /* Serialisation between user GTT access and our code depends upon |
1969 | * revoking the CPU's PTE whilst the mutex is held. The next user | |
1970 | * pagefault then has to wait until we release the mutex. | |
9c870d03 CW |
1971 | * |
1972 | * Note that RPM complicates somewhat by adding an additional | |
1973 | * requirement that operations to the GGTT be made holding the RPM | |
1974 | * wakeref. | |
349f2ccf | 1975 | */ |
275f039d | 1976 | lockdep_assert_held(&i915->drm.struct_mutex); |
9c870d03 | 1977 | intel_runtime_pm_get(i915); |
349f2ccf | 1978 | |
3594a3e2 | 1979 | if (list_empty(&obj->userfault_link)) |
9c870d03 | 1980 | goto out; |
901782b2 | 1981 | |
3594a3e2 | 1982 | list_del_init(&obj->userfault_link); |
6796cb16 DH |
1983 | drm_vma_node_unmap(&obj->base.vma_node, |
1984 | obj->base.dev->anon_inode->i_mapping); | |
349f2ccf CW |
1985 | |
1986 | /* Ensure that the CPU's PTE are revoked and there are not outstanding | |
1987 | * memory transactions from userspace before we return. The TLB | |
1988 | * flushing implied above by changing the PTE above *should* be | |
1989 | * sufficient, an extra barrier here just provides us with a bit | |
1990 | * of paranoid documentation about our requirement to serialise | |
1991 | * memory writes before touching registers / GSM. | |
1992 | */ | |
1993 | wmb(); | |
9c870d03 CW |
1994 | |
1995 | out: | |
1996 | intel_runtime_pm_put(i915); | |
901782b2 CW |
1997 | } |
1998 | ||
7c108fd8 | 1999 | void i915_gem_runtime_suspend(struct drm_i915_private *dev_priv) |
eedd10f4 | 2000 | { |
3594a3e2 | 2001 | struct drm_i915_gem_object *obj, *on; |
7c108fd8 | 2002 | int i; |
eedd10f4 | 2003 | |
3594a3e2 CW |
2004 | /* |
2005 | * Only called during RPM suspend. All users of the userfault_list | |
2006 | * must be holding an RPM wakeref to ensure that this can not | |
2007 | * run concurrently with themselves (and use the struct_mutex for | |
2008 | * protection between themselves). | |
2009 | */ | |
275f039d | 2010 | |
3594a3e2 CW |
2011 | list_for_each_entry_safe(obj, on, |
2012 | &dev_priv->mm.userfault_list, userfault_link) { | |
2013 | list_del_init(&obj->userfault_link); | |
275f039d CW |
2014 | drm_vma_node_unmap(&obj->base.vma_node, |
2015 | obj->base.dev->anon_inode->i_mapping); | |
275f039d | 2016 | } |
7c108fd8 CW |
2017 | |
2018 | /* The fence will be lost when the device powers down. If any were | |
2019 | * in use by hardware (i.e. they are pinned), we should not be powering | |
2020 | * down! All other fences will be reacquired by the user upon waking. | |
2021 | */ | |
2022 | for (i = 0; i < dev_priv->num_fence_regs; i++) { | |
2023 | struct drm_i915_fence_reg *reg = &dev_priv->fence_regs[i]; | |
2024 | ||
2025 | if (WARN_ON(reg->pin_count)) | |
2026 | continue; | |
2027 | ||
2028 | if (!reg->vma) | |
2029 | continue; | |
2030 | ||
2031 | GEM_BUG_ON(!list_empty(®->vma->obj->userfault_link)); | |
2032 | reg->dirty = true; | |
2033 | } | |
eedd10f4 CW |
2034 | } |
2035 | ||
ad1a7d20 CW |
2036 | /** |
2037 | * i915_gem_get_ggtt_size - return required global GTT size for an object | |
a9f1481f | 2038 | * @dev_priv: i915 device |
ad1a7d20 CW |
2039 | * @size: object size |
2040 | * @tiling_mode: tiling mode | |
2041 | * | |
2042 | * Return the required global GTT size for an object, taking into account | |
2043 | * potential fence register mapping. | |
2044 | */ | |
a9f1481f CW |
2045 | u64 i915_gem_get_ggtt_size(struct drm_i915_private *dev_priv, |
2046 | u64 size, int tiling_mode) | |
92b88aeb | 2047 | { |
ad1a7d20 | 2048 | u64 ggtt_size; |
92b88aeb | 2049 | |
ad1a7d20 CW |
2050 | GEM_BUG_ON(size == 0); |
2051 | ||
a9f1481f | 2052 | if (INTEL_GEN(dev_priv) >= 4 || |
e28f8711 CW |
2053 | tiling_mode == I915_TILING_NONE) |
2054 | return size; | |
92b88aeb CW |
2055 | |
2056 | /* Previous chips need a power-of-two fence region when tiling */ | |
a9f1481f | 2057 | if (IS_GEN3(dev_priv)) |
ad1a7d20 | 2058 | ggtt_size = 1024*1024; |
92b88aeb | 2059 | else |
ad1a7d20 | 2060 | ggtt_size = 512*1024; |
92b88aeb | 2061 | |
ad1a7d20 CW |
2062 | while (ggtt_size < size) |
2063 | ggtt_size <<= 1; | |
92b88aeb | 2064 | |
ad1a7d20 | 2065 | return ggtt_size; |
92b88aeb CW |
2066 | } |
2067 | ||
de151cf6 | 2068 | /** |
ad1a7d20 | 2069 | * i915_gem_get_ggtt_alignment - return required global GTT alignment |
a9f1481f | 2070 | * @dev_priv: i915 device |
14bb2c11 TU |
2071 | * @size: object size |
2072 | * @tiling_mode: tiling mode | |
ad1a7d20 | 2073 | * @fenced: is fenced alignment required or not |
de151cf6 | 2074 | * |
ad1a7d20 | 2075 | * Return the required global GTT alignment for an object, taking into account |
5e783301 | 2076 | * potential fence register mapping. |
de151cf6 | 2077 | */ |
a9f1481f | 2078 | u64 i915_gem_get_ggtt_alignment(struct drm_i915_private *dev_priv, u64 size, |
ad1a7d20 | 2079 | int tiling_mode, bool fenced) |
de151cf6 | 2080 | { |
ad1a7d20 CW |
2081 | GEM_BUG_ON(size == 0); |
2082 | ||
de151cf6 JB |
2083 | /* |
2084 | * Minimum alignment is 4k (GTT page size), but might be greater | |
2085 | * if a fence register is needed for the object. | |
2086 | */ | |
a9f1481f | 2087 | if (INTEL_GEN(dev_priv) >= 4 || (!fenced && IS_G33(dev_priv)) || |
e28f8711 | 2088 | tiling_mode == I915_TILING_NONE) |
de151cf6 JB |
2089 | return 4096; |
2090 | ||
a00b10c3 CW |
2091 | /* |
2092 | * Previous chips need to be aligned to the size of the smallest | |
2093 | * fence register that can contain the object. | |
2094 | */ | |
a9f1481f | 2095 | return i915_gem_get_ggtt_size(dev_priv, size, tiling_mode); |
a00b10c3 CW |
2096 | } |
2097 | ||
d8cb5086 CW |
2098 | static int i915_gem_object_create_mmap_offset(struct drm_i915_gem_object *obj) |
2099 | { | |
fac5e23e | 2100 | struct drm_i915_private *dev_priv = to_i915(obj->base.dev); |
f3f6184c | 2101 | int err; |
da494d7c | 2102 | |
f3f6184c CW |
2103 | err = drm_gem_create_mmap_offset(&obj->base); |
2104 | if (!err) | |
2105 | return 0; | |
d8cb5086 | 2106 | |
f3f6184c CW |
2107 | /* We can idle the GPU locklessly to flush stale objects, but in order |
2108 | * to claim that space for ourselves, we need to take the big | |
2109 | * struct_mutex to free the requests+objects and allocate our slot. | |
d8cb5086 | 2110 | */ |
ea746f36 | 2111 | err = i915_gem_wait_for_idle(dev_priv, I915_WAIT_INTERRUPTIBLE); |
f3f6184c CW |
2112 | if (err) |
2113 | return err; | |
2114 | ||
2115 | err = i915_mutex_lock_interruptible(&dev_priv->drm); | |
2116 | if (!err) { | |
2117 | i915_gem_retire_requests(dev_priv); | |
2118 | err = drm_gem_create_mmap_offset(&obj->base); | |
2119 | mutex_unlock(&dev_priv->drm.struct_mutex); | |
2120 | } | |
da494d7c | 2121 | |
f3f6184c | 2122 | return err; |
d8cb5086 CW |
2123 | } |
2124 | ||
2125 | static void i915_gem_object_free_mmap_offset(struct drm_i915_gem_object *obj) | |
2126 | { | |
d8cb5086 CW |
2127 | drm_gem_free_mmap_offset(&obj->base); |
2128 | } | |
2129 | ||
da6b51d0 | 2130 | int |
ff72145b DA |
2131 | i915_gem_mmap_gtt(struct drm_file *file, |
2132 | struct drm_device *dev, | |
da6b51d0 | 2133 | uint32_t handle, |
ff72145b | 2134 | uint64_t *offset) |
de151cf6 | 2135 | { |
05394f39 | 2136 | struct drm_i915_gem_object *obj; |
de151cf6 JB |
2137 | int ret; |
2138 | ||
03ac0642 | 2139 | obj = i915_gem_object_lookup(file, handle); |
f3f6184c CW |
2140 | if (!obj) |
2141 | return -ENOENT; | |
ab18282d | 2142 | |
d8cb5086 | 2143 | ret = i915_gem_object_create_mmap_offset(obj); |
f3f6184c CW |
2144 | if (ret == 0) |
2145 | *offset = drm_vma_node_offset_addr(&obj->base.vma_node); | |
de151cf6 | 2146 | |
f0cd5182 | 2147 | i915_gem_object_put(obj); |
1d7cfea1 | 2148 | return ret; |
de151cf6 JB |
2149 | } |
2150 | ||
ff72145b DA |
2151 | /** |
2152 | * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing | |
2153 | * @dev: DRM device | |
2154 | * @data: GTT mapping ioctl data | |
2155 | * @file: GEM object info | |
2156 | * | |
2157 | * Simply returns the fake offset to userspace so it can mmap it. | |
2158 | * The mmap call will end up in drm_gem_mmap(), which will set things | |
2159 | * up so we can get faults in the handler above. | |
2160 | * | |
2161 | * The fault handler will take care of binding the object into the GTT | |
2162 | * (since it may have been evicted to make room for something), allocating | |
2163 | * a fence register, and mapping the appropriate aperture address into | |
2164 | * userspace. | |
2165 | */ | |
2166 | int | |
2167 | i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data, | |
2168 | struct drm_file *file) | |
2169 | { | |
2170 | struct drm_i915_gem_mmap_gtt *args = data; | |
2171 | ||
da6b51d0 | 2172 | return i915_gem_mmap_gtt(file, dev, args->handle, &args->offset); |
ff72145b DA |
2173 | } |
2174 | ||
225067ee DV |
2175 | /* Immediately discard the backing storage */ |
2176 | static void | |
2177 | i915_gem_object_truncate(struct drm_i915_gem_object *obj) | |
e5281ccd | 2178 | { |
4d6294bf | 2179 | i915_gem_object_free_mmap_offset(obj); |
1286ff73 | 2180 | |
4d6294bf CW |
2181 | if (obj->base.filp == NULL) |
2182 | return; | |
e5281ccd | 2183 | |
225067ee DV |
2184 | /* Our goal here is to return as much of the memory as |
2185 | * is possible back to the system as we are called from OOM. | |
2186 | * To do this we must instruct the shmfs to drop all of its | |
2187 | * backing pages, *now*. | |
2188 | */ | |
5537252b | 2189 | shmem_truncate_range(file_inode(obj->base.filp), 0, (loff_t)-1); |
a4f5ea64 | 2190 | obj->mm.madv = __I915_MADV_PURGED; |
225067ee | 2191 | } |
e5281ccd | 2192 | |
5537252b | 2193 | /* Try to discard unwanted pages */ |
03ac84f1 | 2194 | void __i915_gem_object_invalidate(struct drm_i915_gem_object *obj) |
225067ee | 2195 | { |
5537252b CW |
2196 | struct address_space *mapping; |
2197 | ||
1233e2db CW |
2198 | lockdep_assert_held(&obj->mm.lock); |
2199 | GEM_BUG_ON(obj->mm.pages); | |
2200 | ||
a4f5ea64 | 2201 | switch (obj->mm.madv) { |
5537252b CW |
2202 | case I915_MADV_DONTNEED: |
2203 | i915_gem_object_truncate(obj); | |
2204 | case __I915_MADV_PURGED: | |
2205 | return; | |
2206 | } | |
2207 | ||
2208 | if (obj->base.filp == NULL) | |
2209 | return; | |
2210 | ||
93c76a3d | 2211 | mapping = obj->base.filp->f_mapping, |
5537252b | 2212 | invalidate_mapping_pages(mapping, 0, (loff_t)-1); |
e5281ccd CW |
2213 | } |
2214 | ||
5cdf5881 | 2215 | static void |
03ac84f1 CW |
2216 | i915_gem_object_put_pages_gtt(struct drm_i915_gem_object *obj, |
2217 | struct sg_table *pages) | |
673a394b | 2218 | { |
85d1225e DG |
2219 | struct sgt_iter sgt_iter; |
2220 | struct page *page; | |
1286ff73 | 2221 | |
2b3c8317 | 2222 | __i915_gem_object_release_shmem(obj, pages); |
673a394b | 2223 | |
03ac84f1 | 2224 | i915_gem_gtt_finish_pages(obj, pages); |
e2273302 | 2225 | |
6dacfd2f | 2226 | if (i915_gem_object_needs_bit17_swizzle(obj)) |
03ac84f1 | 2227 | i915_gem_object_save_bit_17_swizzle(obj, pages); |
280b713b | 2228 | |
03ac84f1 | 2229 | for_each_sgt_page(page, sgt_iter, pages) { |
a4f5ea64 | 2230 | if (obj->mm.dirty) |
9da3da66 | 2231 | set_page_dirty(page); |
3ef94daa | 2232 | |
a4f5ea64 | 2233 | if (obj->mm.madv == I915_MADV_WILLNEED) |
9da3da66 | 2234 | mark_page_accessed(page); |
3ef94daa | 2235 | |
09cbfeaf | 2236 | put_page(page); |
3ef94daa | 2237 | } |
a4f5ea64 | 2238 | obj->mm.dirty = false; |
673a394b | 2239 | |
03ac84f1 CW |
2240 | sg_free_table(pages); |
2241 | kfree(pages); | |
37e680a1 | 2242 | } |
6c085a72 | 2243 | |
96d77634 CW |
2244 | static void __i915_gem_object_reset_page_iter(struct drm_i915_gem_object *obj) |
2245 | { | |
2246 | struct radix_tree_iter iter; | |
2247 | void **slot; | |
2248 | ||
a4f5ea64 CW |
2249 | radix_tree_for_each_slot(slot, &obj->mm.get_page.radix, &iter, 0) |
2250 | radix_tree_delete(&obj->mm.get_page.radix, iter.index); | |
96d77634 CW |
2251 | } |
2252 | ||
548625ee CW |
2253 | void __i915_gem_object_put_pages(struct drm_i915_gem_object *obj, |
2254 | enum i915_mm_subclass subclass) | |
37e680a1 | 2255 | { |
03ac84f1 | 2256 | struct sg_table *pages; |
37e680a1 | 2257 | |
a4f5ea64 | 2258 | if (i915_gem_object_has_pinned_pages(obj)) |
03ac84f1 | 2259 | return; |
a5570178 | 2260 | |
15717de2 | 2261 | GEM_BUG_ON(obj->bind_count); |
1233e2db CW |
2262 | if (!READ_ONCE(obj->mm.pages)) |
2263 | return; | |
2264 | ||
2265 | /* May be called by shrinker from within get_pages() (on another bo) */ | |
548625ee | 2266 | mutex_lock_nested(&obj->mm.lock, subclass); |
1233e2db CW |
2267 | if (unlikely(atomic_read(&obj->mm.pages_pin_count))) |
2268 | goto unlock; | |
3e123027 | 2269 | |
a2165e31 CW |
2270 | /* ->put_pages might need to allocate memory for the bit17 swizzle |
2271 | * array, hence protect them from being reaped by removing them from gtt | |
2272 | * lists early. */ | |
03ac84f1 CW |
2273 | pages = fetch_and_zero(&obj->mm.pages); |
2274 | GEM_BUG_ON(!pages); | |
a2165e31 | 2275 | |
a4f5ea64 | 2276 | if (obj->mm.mapping) { |
4b30cb23 CW |
2277 | void *ptr; |
2278 | ||
a4f5ea64 | 2279 | ptr = ptr_mask_bits(obj->mm.mapping); |
4b30cb23 CW |
2280 | if (is_vmalloc_addr(ptr)) |
2281 | vunmap(ptr); | |
fb8621d3 | 2282 | else |
4b30cb23 CW |
2283 | kunmap(kmap_to_page(ptr)); |
2284 | ||
a4f5ea64 | 2285 | obj->mm.mapping = NULL; |
0a798eb9 CW |
2286 | } |
2287 | ||
96d77634 CW |
2288 | __i915_gem_object_reset_page_iter(obj); |
2289 | ||
03ac84f1 | 2290 | obj->ops->put_pages(obj, pages); |
1233e2db CW |
2291 | unlock: |
2292 | mutex_unlock(&obj->mm.lock); | |
6c085a72 CW |
2293 | } |
2294 | ||
4ff340f0 | 2295 | static unsigned int swiotlb_max_size(void) |
871dfbd6 CW |
2296 | { |
2297 | #if IS_ENABLED(CONFIG_SWIOTLB) | |
2298 | return rounddown(swiotlb_nr_tbl() << IO_TLB_SHIFT, PAGE_SIZE); | |
2299 | #else | |
2300 | return 0; | |
2301 | #endif | |
2302 | } | |
2303 | ||
0c40ce13 TU |
2304 | static void i915_sg_trim(struct sg_table *orig_st) |
2305 | { | |
2306 | struct sg_table new_st; | |
2307 | struct scatterlist *sg, *new_sg; | |
2308 | unsigned int i; | |
2309 | ||
2310 | if (orig_st->nents == orig_st->orig_nents) | |
2311 | return; | |
2312 | ||
2313 | if (sg_alloc_table(&new_st, orig_st->nents, GFP_KERNEL)) | |
2314 | return; | |
2315 | ||
2316 | new_sg = new_st.sgl; | |
2317 | for_each_sg(orig_st->sgl, sg, orig_st->nents, i) { | |
2318 | sg_set_page(new_sg, sg_page(sg), sg->length, 0); | |
2319 | /* called before being DMA mapped, no need to copy sg->dma_* */ | |
2320 | new_sg = sg_next(new_sg); | |
2321 | } | |
2322 | ||
2323 | sg_free_table(orig_st); | |
2324 | ||
2325 | *orig_st = new_st; | |
2326 | } | |
2327 | ||
03ac84f1 | 2328 | static struct sg_table * |
6c085a72 | 2329 | i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj) |
e5281ccd | 2330 | { |
fac5e23e | 2331 | struct drm_i915_private *dev_priv = to_i915(obj->base.dev); |
e5281ccd CW |
2332 | int page_count, i; |
2333 | struct address_space *mapping; | |
9da3da66 CW |
2334 | struct sg_table *st; |
2335 | struct scatterlist *sg; | |
85d1225e | 2336 | struct sgt_iter sgt_iter; |
e5281ccd | 2337 | struct page *page; |
90797e6d | 2338 | unsigned long last_pfn = 0; /* suppress gcc warning */ |
4ff340f0 | 2339 | unsigned int max_segment; |
e2273302 | 2340 | int ret; |
6c085a72 | 2341 | gfp_t gfp; |
e5281ccd | 2342 | |
6c085a72 CW |
2343 | /* Assert that the object is not currently in any GPU domain. As it |
2344 | * wasn't in the GTT, there shouldn't be any way it could have been in | |
2345 | * a GPU cache | |
2346 | */ | |
03ac84f1 CW |
2347 | GEM_BUG_ON(obj->base.read_domains & I915_GEM_GPU_DOMAINS); |
2348 | GEM_BUG_ON(obj->base.write_domain & I915_GEM_GPU_DOMAINS); | |
6c085a72 | 2349 | |
871dfbd6 CW |
2350 | max_segment = swiotlb_max_size(); |
2351 | if (!max_segment) | |
4ff340f0 | 2352 | max_segment = rounddown(UINT_MAX, PAGE_SIZE); |
871dfbd6 | 2353 | |
9da3da66 CW |
2354 | st = kmalloc(sizeof(*st), GFP_KERNEL); |
2355 | if (st == NULL) | |
03ac84f1 | 2356 | return ERR_PTR(-ENOMEM); |
9da3da66 | 2357 | |
05394f39 | 2358 | page_count = obj->base.size / PAGE_SIZE; |
9da3da66 | 2359 | if (sg_alloc_table(st, page_count, GFP_KERNEL)) { |
9da3da66 | 2360 | kfree(st); |
03ac84f1 | 2361 | return ERR_PTR(-ENOMEM); |
9da3da66 | 2362 | } |
e5281ccd | 2363 | |
9da3da66 CW |
2364 | /* Get the list of pages out of our struct file. They'll be pinned |
2365 | * at this point until we release them. | |
2366 | * | |
2367 | * Fail silently without starting the shrinker | |
2368 | */ | |
93c76a3d | 2369 | mapping = obj->base.filp->f_mapping; |
c62d2555 | 2370 | gfp = mapping_gfp_constraint(mapping, ~(__GFP_IO | __GFP_RECLAIM)); |
d0164adc | 2371 | gfp |= __GFP_NORETRY | __GFP_NOWARN; |
90797e6d ID |
2372 | sg = st->sgl; |
2373 | st->nents = 0; | |
2374 | for (i = 0; i < page_count; i++) { | |
6c085a72 CW |
2375 | page = shmem_read_mapping_page_gfp(mapping, i, gfp); |
2376 | if (IS_ERR(page)) { | |
21ab4e74 CW |
2377 | i915_gem_shrink(dev_priv, |
2378 | page_count, | |
2379 | I915_SHRINK_BOUND | | |
2380 | I915_SHRINK_UNBOUND | | |
2381 | I915_SHRINK_PURGEABLE); | |
6c085a72 CW |
2382 | page = shmem_read_mapping_page_gfp(mapping, i, gfp); |
2383 | } | |
2384 | if (IS_ERR(page)) { | |
2385 | /* We've tried hard to allocate the memory by reaping | |
2386 | * our own buffer, now let the real VM do its job and | |
2387 | * go down in flames if truly OOM. | |
2388 | */ | |
f461d1be | 2389 | page = shmem_read_mapping_page(mapping, i); |
e2273302 ID |
2390 | if (IS_ERR(page)) { |
2391 | ret = PTR_ERR(page); | |
b17993b7 | 2392 | goto err_sg; |
e2273302 | 2393 | } |
6c085a72 | 2394 | } |
871dfbd6 CW |
2395 | if (!i || |
2396 | sg->length >= max_segment || | |
2397 | page_to_pfn(page) != last_pfn + 1) { | |
90797e6d ID |
2398 | if (i) |
2399 | sg = sg_next(sg); | |
2400 | st->nents++; | |
2401 | sg_set_page(sg, page, PAGE_SIZE, 0); | |
2402 | } else { | |
2403 | sg->length += PAGE_SIZE; | |
2404 | } | |
2405 | last_pfn = page_to_pfn(page); | |
3bbbe706 DV |
2406 | |
2407 | /* Check that the i965g/gm workaround works. */ | |
2408 | WARN_ON((gfp & __GFP_DMA32) && (last_pfn >= 0x00100000UL)); | |
e5281ccd | 2409 | } |
871dfbd6 | 2410 | if (sg) /* loop terminated early; short sg table */ |
426729dc | 2411 | sg_mark_end(sg); |
74ce6b6c | 2412 | |
0c40ce13 TU |
2413 | /* Trim unused sg entries to avoid wasting memory. */ |
2414 | i915_sg_trim(st); | |
2415 | ||
03ac84f1 | 2416 | ret = i915_gem_gtt_prepare_pages(obj, st); |
e2273302 ID |
2417 | if (ret) |
2418 | goto err_pages; | |
2419 | ||
6dacfd2f | 2420 | if (i915_gem_object_needs_bit17_swizzle(obj)) |
03ac84f1 | 2421 | i915_gem_object_do_bit_17_swizzle(obj, st); |
e5281ccd | 2422 | |
03ac84f1 | 2423 | return st; |
e5281ccd | 2424 | |
b17993b7 | 2425 | err_sg: |
90797e6d | 2426 | sg_mark_end(sg); |
b17993b7 | 2427 | err_pages: |
85d1225e DG |
2428 | for_each_sgt_page(page, sgt_iter, st) |
2429 | put_page(page); | |
9da3da66 CW |
2430 | sg_free_table(st); |
2431 | kfree(st); | |
0820baf3 CW |
2432 | |
2433 | /* shmemfs first checks if there is enough memory to allocate the page | |
2434 | * and reports ENOSPC should there be insufficient, along with the usual | |
2435 | * ENOMEM for a genuine allocation failure. | |
2436 | * | |
2437 | * We use ENOSPC in our driver to mean that we have run out of aperture | |
2438 | * space and so want to translate the error from shmemfs back to our | |
2439 | * usual understanding of ENOMEM. | |
2440 | */ | |
e2273302 ID |
2441 | if (ret == -ENOSPC) |
2442 | ret = -ENOMEM; | |
2443 | ||
03ac84f1 CW |
2444 | return ERR_PTR(ret); |
2445 | } | |
2446 | ||
2447 | void __i915_gem_object_set_pages(struct drm_i915_gem_object *obj, | |
2448 | struct sg_table *pages) | |
2449 | { | |
1233e2db | 2450 | lockdep_assert_held(&obj->mm.lock); |
03ac84f1 CW |
2451 | |
2452 | obj->mm.get_page.sg_pos = pages->sgl; | |
2453 | obj->mm.get_page.sg_idx = 0; | |
2454 | ||
2455 | obj->mm.pages = pages; | |
2c3a3f44 CW |
2456 | |
2457 | if (i915_gem_object_is_tiled(obj) && | |
2458 | to_i915(obj->base.dev)->quirks & QUIRK_PIN_SWIZZLED_PAGES) { | |
2459 | GEM_BUG_ON(obj->mm.quirked); | |
2460 | __i915_gem_object_pin_pages(obj); | |
2461 | obj->mm.quirked = true; | |
2462 | } | |
03ac84f1 CW |
2463 | } |
2464 | ||
2465 | static int ____i915_gem_object_get_pages(struct drm_i915_gem_object *obj) | |
2466 | { | |
2467 | struct sg_table *pages; | |
2468 | ||
2c3a3f44 CW |
2469 | GEM_BUG_ON(i915_gem_object_has_pinned_pages(obj)); |
2470 | ||
03ac84f1 CW |
2471 | if (unlikely(obj->mm.madv != I915_MADV_WILLNEED)) { |
2472 | DRM_DEBUG("Attempting to obtain a purgeable object\n"); | |
2473 | return -EFAULT; | |
2474 | } | |
2475 | ||
2476 | pages = obj->ops->get_pages(obj); | |
2477 | if (unlikely(IS_ERR(pages))) | |
2478 | return PTR_ERR(pages); | |
2479 | ||
2480 | __i915_gem_object_set_pages(obj, pages); | |
2481 | return 0; | |
673a394b EA |
2482 | } |
2483 | ||
37e680a1 | 2484 | /* Ensure that the associated pages are gathered from the backing storage |
1233e2db | 2485 | * and pinned into our object. i915_gem_object_pin_pages() may be called |
37e680a1 | 2486 | * multiple times before they are released by a single call to |
1233e2db | 2487 | * i915_gem_object_unpin_pages() - once the pages are no longer referenced |
37e680a1 CW |
2488 | * either as a result of memory pressure (reaping pages under the shrinker) |
2489 | * or as the object is itself released. | |
2490 | */ | |
a4f5ea64 | 2491 | int __i915_gem_object_get_pages(struct drm_i915_gem_object *obj) |
37e680a1 | 2492 | { |
03ac84f1 | 2493 | int err; |
37e680a1 | 2494 | |
1233e2db CW |
2495 | err = mutex_lock_interruptible(&obj->mm.lock); |
2496 | if (err) | |
2497 | return err; | |
4c7d62c6 | 2498 | |
2c3a3f44 CW |
2499 | if (unlikely(!obj->mm.pages)) { |
2500 | err = ____i915_gem_object_get_pages(obj); | |
2501 | if (err) | |
2502 | goto unlock; | |
37e680a1 | 2503 | |
2c3a3f44 CW |
2504 | smp_mb__before_atomic(); |
2505 | } | |
2506 | atomic_inc(&obj->mm.pages_pin_count); | |
ee286370 | 2507 | |
1233e2db CW |
2508 | unlock: |
2509 | mutex_unlock(&obj->mm.lock); | |
03ac84f1 | 2510 | return err; |
673a394b EA |
2511 | } |
2512 | ||
dd6034c6 | 2513 | /* The 'mapping' part of i915_gem_object_pin_map() below */ |
d31d7cb1 CW |
2514 | static void *i915_gem_object_map(const struct drm_i915_gem_object *obj, |
2515 | enum i915_map_type type) | |
dd6034c6 DG |
2516 | { |
2517 | unsigned long n_pages = obj->base.size >> PAGE_SHIFT; | |
a4f5ea64 | 2518 | struct sg_table *sgt = obj->mm.pages; |
85d1225e DG |
2519 | struct sgt_iter sgt_iter; |
2520 | struct page *page; | |
b338fa47 DG |
2521 | struct page *stack_pages[32]; |
2522 | struct page **pages = stack_pages; | |
dd6034c6 | 2523 | unsigned long i = 0; |
d31d7cb1 | 2524 | pgprot_t pgprot; |
dd6034c6 DG |
2525 | void *addr; |
2526 | ||
2527 | /* A single page can always be kmapped */ | |
d31d7cb1 | 2528 | if (n_pages == 1 && type == I915_MAP_WB) |
dd6034c6 DG |
2529 | return kmap(sg_page(sgt->sgl)); |
2530 | ||
b338fa47 DG |
2531 | if (n_pages > ARRAY_SIZE(stack_pages)) { |
2532 | /* Too big for stack -- allocate temporary array instead */ | |
2533 | pages = drm_malloc_gfp(n_pages, sizeof(*pages), GFP_TEMPORARY); | |
2534 | if (!pages) | |
2535 | return NULL; | |
2536 | } | |
dd6034c6 | 2537 | |
85d1225e DG |
2538 | for_each_sgt_page(page, sgt_iter, sgt) |
2539 | pages[i++] = page; | |
dd6034c6 DG |
2540 | |
2541 | /* Check that we have the expected number of pages */ | |
2542 | GEM_BUG_ON(i != n_pages); | |
2543 | ||
d31d7cb1 CW |
2544 | switch (type) { |
2545 | case I915_MAP_WB: | |
2546 | pgprot = PAGE_KERNEL; | |
2547 | break; | |
2548 | case I915_MAP_WC: | |
2549 | pgprot = pgprot_writecombine(PAGE_KERNEL_IO); | |
2550 | break; | |
2551 | } | |
2552 | addr = vmap(pages, n_pages, 0, pgprot); | |
dd6034c6 | 2553 | |
b338fa47 DG |
2554 | if (pages != stack_pages) |
2555 | drm_free_large(pages); | |
dd6034c6 DG |
2556 | |
2557 | return addr; | |
2558 | } | |
2559 | ||
2560 | /* get, pin, and map the pages of the object into kernel space */ | |
d31d7cb1 CW |
2561 | void *i915_gem_object_pin_map(struct drm_i915_gem_object *obj, |
2562 | enum i915_map_type type) | |
0a798eb9 | 2563 | { |
d31d7cb1 CW |
2564 | enum i915_map_type has_type; |
2565 | bool pinned; | |
2566 | void *ptr; | |
0a798eb9 CW |
2567 | int ret; |
2568 | ||
d31d7cb1 | 2569 | GEM_BUG_ON(!i915_gem_object_has_struct_page(obj)); |
0a798eb9 | 2570 | |
1233e2db | 2571 | ret = mutex_lock_interruptible(&obj->mm.lock); |
0a798eb9 CW |
2572 | if (ret) |
2573 | return ERR_PTR(ret); | |
2574 | ||
1233e2db CW |
2575 | pinned = true; |
2576 | if (!atomic_inc_not_zero(&obj->mm.pages_pin_count)) { | |
2c3a3f44 CW |
2577 | if (unlikely(!obj->mm.pages)) { |
2578 | ret = ____i915_gem_object_get_pages(obj); | |
2579 | if (ret) | |
2580 | goto err_unlock; | |
1233e2db | 2581 | |
2c3a3f44 CW |
2582 | smp_mb__before_atomic(); |
2583 | } | |
2584 | atomic_inc(&obj->mm.pages_pin_count); | |
1233e2db CW |
2585 | pinned = false; |
2586 | } | |
2587 | GEM_BUG_ON(!obj->mm.pages); | |
0a798eb9 | 2588 | |
a4f5ea64 | 2589 | ptr = ptr_unpack_bits(obj->mm.mapping, has_type); |
d31d7cb1 CW |
2590 | if (ptr && has_type != type) { |
2591 | if (pinned) { | |
2592 | ret = -EBUSY; | |
1233e2db | 2593 | goto err_unpin; |
0a798eb9 | 2594 | } |
d31d7cb1 CW |
2595 | |
2596 | if (is_vmalloc_addr(ptr)) | |
2597 | vunmap(ptr); | |
2598 | else | |
2599 | kunmap(kmap_to_page(ptr)); | |
2600 | ||
a4f5ea64 | 2601 | ptr = obj->mm.mapping = NULL; |
0a798eb9 CW |
2602 | } |
2603 | ||
d31d7cb1 CW |
2604 | if (!ptr) { |
2605 | ptr = i915_gem_object_map(obj, type); | |
2606 | if (!ptr) { | |
2607 | ret = -ENOMEM; | |
1233e2db | 2608 | goto err_unpin; |
d31d7cb1 CW |
2609 | } |
2610 | ||
a4f5ea64 | 2611 | obj->mm.mapping = ptr_pack_bits(ptr, type); |
d31d7cb1 CW |
2612 | } |
2613 | ||
1233e2db CW |
2614 | out_unlock: |
2615 | mutex_unlock(&obj->mm.lock); | |
d31d7cb1 CW |
2616 | return ptr; |
2617 | ||
1233e2db CW |
2618 | err_unpin: |
2619 | atomic_dec(&obj->mm.pages_pin_count); | |
2620 | err_unlock: | |
2621 | ptr = ERR_PTR(ret); | |
2622 | goto out_unlock; | |
0a798eb9 CW |
2623 | } |
2624 | ||
7b4d3a16 | 2625 | static bool i915_context_is_banned(const struct i915_gem_context *ctx) |
be62acb4 | 2626 | { |
bc1d53c6 | 2627 | if (ctx->banned) |
be62acb4 MK |
2628 | return true; |
2629 | ||
bc1d53c6 | 2630 | if (!ctx->bannable) |
e5e1fc47 MK |
2631 | return false; |
2632 | ||
bc1d53c6 | 2633 | if (ctx->ban_score >= CONTEXT_SCORE_BAN_THRESHOLD) { |
e5e1fc47 MK |
2634 | DRM_DEBUG("context hanging too often, banning!\n"); |
2635 | return true; | |
2636 | } | |
2637 | ||
be62acb4 MK |
2638 | return false; |
2639 | } | |
2640 | ||
e5e1fc47 | 2641 | static void i915_gem_context_mark_guilty(struct i915_gem_context *ctx) |
aa60c664 | 2642 | { |
bc1d53c6 | 2643 | ctx->ban_score += CONTEXT_SCORE_GUILTY; |
e5e1fc47 | 2644 | |
bc1d53c6 MK |
2645 | ctx->banned = i915_context_is_banned(ctx); |
2646 | ctx->guilty_count++; | |
b083a087 MK |
2647 | |
2648 | DRM_DEBUG_DRIVER("context %s marked guilty (score %d) banned? %s\n", | |
bc1d53c6 MK |
2649 | ctx->name, ctx->ban_score, |
2650 | yesno(ctx->banned)); | |
b083a087 | 2651 | |
d9e9da64 | 2652 | if (!ctx->banned || IS_ERR_OR_NULL(ctx->file_priv)) |
b083a087 MK |
2653 | return; |
2654 | ||
d9e9da64 CW |
2655 | ctx->file_priv->context_bans++; |
2656 | DRM_DEBUG_DRIVER("client %s has had %d context banned\n", | |
2657 | ctx->name, ctx->file_priv->context_bans); | |
e5e1fc47 MK |
2658 | } |
2659 | ||
2660 | static void i915_gem_context_mark_innocent(struct i915_gem_context *ctx) | |
2661 | { | |
bc1d53c6 | 2662 | ctx->active_count++; |
aa60c664 MK |
2663 | } |
2664 | ||
8d9fc7fd | 2665 | struct drm_i915_gem_request * |
0bc40be8 | 2666 | i915_gem_find_active_request(struct intel_engine_cs *engine) |
9375e446 | 2667 | { |
4db080f9 CW |
2668 | struct drm_i915_gem_request *request; |
2669 | ||
f69a02c9 CW |
2670 | /* We are called by the error capture and reset at a random |
2671 | * point in time. In particular, note that neither is crucially | |
2672 | * ordered with an interrupt. After a hang, the GPU is dead and we | |
2673 | * assume that no more writes can happen (we waited long enough for | |
2674 | * all writes that were in transaction to be flushed) - adding an | |
2675 | * extra delay for a recent interrupt is pointless. Hence, we do | |
2676 | * not need an engine->irq_seqno_barrier() before the seqno reads. | |
2677 | */ | |
73cb9701 | 2678 | list_for_each_entry(request, &engine->timeline->requests, link) { |
80b204bc | 2679 | if (__i915_gem_request_completed(request)) |
4db080f9 | 2680 | continue; |
aa60c664 | 2681 | |
b6b0fac0 | 2682 | return request; |
4db080f9 | 2683 | } |
b6b0fac0 MK |
2684 | |
2685 | return NULL; | |
2686 | } | |
2687 | ||
821ed7df CW |
2688 | static void reset_request(struct drm_i915_gem_request *request) |
2689 | { | |
2690 | void *vaddr = request->ring->vaddr; | |
2691 | u32 head; | |
2692 | ||
2693 | /* As this request likely depends on state from the lost | |
2694 | * context, clear out all the user operations leaving the | |
2695 | * breadcrumb at the end (so we get the fence notifications). | |
2696 | */ | |
2697 | head = request->head; | |
2698 | if (request->postfix < head) { | |
2699 | memset(vaddr + head, 0, request->ring->size - head); | |
2700 | head = 0; | |
2701 | } | |
2702 | memset(vaddr + head, 0, request->postfix - head); | |
2703 | } | |
2704 | ||
2705 | static void i915_gem_reset_engine(struct intel_engine_cs *engine) | |
b6b0fac0 MK |
2706 | { |
2707 | struct drm_i915_gem_request *request; | |
821ed7df | 2708 | struct i915_gem_context *incomplete_ctx; |
80b204bc | 2709 | struct intel_timeline *timeline; |
b6b0fac0 MK |
2710 | bool ring_hung; |
2711 | ||
821ed7df CW |
2712 | if (engine->irq_seqno_barrier) |
2713 | engine->irq_seqno_barrier(engine); | |
2714 | ||
0bc40be8 | 2715 | request = i915_gem_find_active_request(engine); |
821ed7df | 2716 | if (!request) |
b6b0fac0 MK |
2717 | return; |
2718 | ||
3fe3b030 MK |
2719 | ring_hung = engine->hangcheck.stalled; |
2720 | if (engine->hangcheck.seqno != intel_engine_get_seqno(engine)) { | |
2721 | DRM_DEBUG_DRIVER("%s pardoned, was guilty? %s\n", | |
2722 | engine->name, | |
2723 | yesno(ring_hung)); | |
77c60701 | 2724 | ring_hung = false; |
3fe3b030 | 2725 | } |
77c60701 | 2726 | |
e5e1fc47 MK |
2727 | if (ring_hung) |
2728 | i915_gem_context_mark_guilty(request->ctx); | |
2729 | else | |
2730 | i915_gem_context_mark_innocent(request->ctx); | |
2731 | ||
821ed7df CW |
2732 | if (!ring_hung) |
2733 | return; | |
2734 | ||
2735 | DRM_DEBUG_DRIVER("resetting %s to restart from tail of request 0x%x\n", | |
65e4760e | 2736 | engine->name, request->global_seqno); |
821ed7df CW |
2737 | |
2738 | /* Setup the CS to resume from the breadcrumb of the hung request */ | |
2739 | engine->reset_hw(engine, request); | |
2740 | ||
2741 | /* Users of the default context do not rely on logical state | |
2742 | * preserved between batches. They have to emit full state on | |
2743 | * every batch and so it is safe to execute queued requests following | |
2744 | * the hang. | |
2745 | * | |
2746 | * Other contexts preserve state, now corrupt. We want to skip all | |
2747 | * queued requests that reference the corrupt context. | |
2748 | */ | |
2749 | incomplete_ctx = request->ctx; | |
2750 | if (i915_gem_context_is_default(incomplete_ctx)) | |
2751 | return; | |
2752 | ||
73cb9701 | 2753 | list_for_each_entry_continue(request, &engine->timeline->requests, link) |
821ed7df CW |
2754 | if (request->ctx == incomplete_ctx) |
2755 | reset_request(request); | |
80b204bc CW |
2756 | |
2757 | timeline = i915_gem_context_lookup_timeline(incomplete_ctx, engine); | |
2758 | list_for_each_entry(request, &timeline->requests, link) | |
2759 | reset_request(request); | |
4db080f9 | 2760 | } |
aa60c664 | 2761 | |
821ed7df | 2762 | void i915_gem_reset(struct drm_i915_private *dev_priv) |
4db080f9 | 2763 | { |
821ed7df | 2764 | struct intel_engine_cs *engine; |
3b3f1650 | 2765 | enum intel_engine_id id; |
608c1a52 | 2766 | |
4c7d62c6 CW |
2767 | lockdep_assert_held(&dev_priv->drm.struct_mutex); |
2768 | ||
821ed7df CW |
2769 | i915_gem_retire_requests(dev_priv); |
2770 | ||
3b3f1650 | 2771 | for_each_engine(engine, dev_priv, id) |
821ed7df CW |
2772 | i915_gem_reset_engine(engine); |
2773 | ||
4362f4f6 | 2774 | i915_gem_restore_fences(dev_priv); |
f2a91d1a CW |
2775 | |
2776 | if (dev_priv->gt.awake) { | |
2777 | intel_sanitize_gt_powersave(dev_priv); | |
2778 | intel_enable_gt_powersave(dev_priv); | |
2779 | if (INTEL_GEN(dev_priv) >= 6) | |
2780 | gen6_rps_busy(dev_priv); | |
2781 | } | |
821ed7df CW |
2782 | } |
2783 | ||
2784 | static void nop_submit_request(struct drm_i915_gem_request *request) | |
2785 | { | |
3dcf93f7 CW |
2786 | i915_gem_request_submit(request); |
2787 | intel_engine_init_global_seqno(request->engine, request->global_seqno); | |
821ed7df CW |
2788 | } |
2789 | ||
2790 | static void i915_gem_cleanup_engine(struct intel_engine_cs *engine) | |
2791 | { | |
20e4933c CW |
2792 | /* We need to be sure that no thread is running the old callback as |
2793 | * we install the nop handler (otherwise we would submit a request | |
2794 | * to hardware that will never complete). In order to prevent this | |
2795 | * race, we wait until the machine is idle before making the swap | |
2796 | * (using stop_machine()). | |
2797 | */ | |
821ed7df | 2798 | engine->submit_request = nop_submit_request; |
70c2a24d | 2799 | |
c4b0930b CW |
2800 | /* Mark all pending requests as complete so that any concurrent |
2801 | * (lockless) lookup doesn't try and wait upon the request as we | |
2802 | * reset it. | |
2803 | */ | |
73cb9701 | 2804 | intel_engine_init_global_seqno(engine, |
cb399eab | 2805 | intel_engine_last_submit(engine)); |
c4b0930b | 2806 | |
dcb4c12a OM |
2807 | /* |
2808 | * Clear the execlists queue up before freeing the requests, as those | |
2809 | * are the ones that keep the context and ringbuffer backing objects | |
2810 | * pinned in place. | |
2811 | */ | |
dcb4c12a | 2812 | |
7de1691a | 2813 | if (i915.enable_execlists) { |
663f71e7 CW |
2814 | unsigned long flags; |
2815 | ||
2816 | spin_lock_irqsave(&engine->timeline->lock, flags); | |
2817 | ||
70c2a24d CW |
2818 | i915_gem_request_put(engine->execlist_port[0].request); |
2819 | i915_gem_request_put(engine->execlist_port[1].request); | |
2820 | memset(engine->execlist_port, 0, sizeof(engine->execlist_port)); | |
20311bd3 CW |
2821 | engine->execlist_queue = RB_ROOT; |
2822 | engine->execlist_first = NULL; | |
663f71e7 CW |
2823 | |
2824 | spin_unlock_irqrestore(&engine->timeline->lock, flags); | |
dcb4c12a | 2825 | } |
673a394b EA |
2826 | } |
2827 | ||
20e4933c | 2828 | static int __i915_gem_set_wedged_BKL(void *data) |
673a394b | 2829 | { |
20e4933c | 2830 | struct drm_i915_private *i915 = data; |
e2f80391 | 2831 | struct intel_engine_cs *engine; |
3b3f1650 | 2832 | enum intel_engine_id id; |
673a394b | 2833 | |
20e4933c CW |
2834 | for_each_engine(engine, i915, id) |
2835 | i915_gem_cleanup_engine(engine); | |
2836 | ||
2837 | return 0; | |
2838 | } | |
2839 | ||
2840 | void i915_gem_set_wedged(struct drm_i915_private *dev_priv) | |
2841 | { | |
821ed7df CW |
2842 | lockdep_assert_held(&dev_priv->drm.struct_mutex); |
2843 | set_bit(I915_WEDGED, &dev_priv->gpu_error.flags); | |
4db080f9 | 2844 | |
20e4933c | 2845 | stop_machine(__i915_gem_set_wedged_BKL, dev_priv, NULL); |
dfaae392 | 2846 | |
20e4933c | 2847 | i915_gem_context_lost(dev_priv); |
821ed7df | 2848 | i915_gem_retire_requests(dev_priv); |
20e4933c CW |
2849 | |
2850 | mod_delayed_work(dev_priv->wq, &dev_priv->gt.idle_work, 0); | |
673a394b EA |
2851 | } |
2852 | ||
75ef9da2 | 2853 | static void |
673a394b EA |
2854 | i915_gem_retire_work_handler(struct work_struct *work) |
2855 | { | |
b29c19b6 | 2856 | struct drm_i915_private *dev_priv = |
67d97da3 | 2857 | container_of(work, typeof(*dev_priv), gt.retire_work.work); |
91c8a326 | 2858 | struct drm_device *dev = &dev_priv->drm; |
673a394b | 2859 | |
891b48cf | 2860 | /* Come back later if the device is busy... */ |
b29c19b6 | 2861 | if (mutex_trylock(&dev->struct_mutex)) { |
67d97da3 | 2862 | i915_gem_retire_requests(dev_priv); |
b29c19b6 | 2863 | mutex_unlock(&dev->struct_mutex); |
673a394b | 2864 | } |
67d97da3 CW |
2865 | |
2866 | /* Keep the retire handler running until we are finally idle. | |
2867 | * We do not need to do this test under locking as in the worst-case | |
2868 | * we queue the retire worker once too often. | |
2869 | */ | |
c9615613 CW |
2870 | if (READ_ONCE(dev_priv->gt.awake)) { |
2871 | i915_queue_hangcheck(dev_priv); | |
67d97da3 CW |
2872 | queue_delayed_work(dev_priv->wq, |
2873 | &dev_priv->gt.retire_work, | |
bcb45086 | 2874 | round_jiffies_up_relative(HZ)); |
c9615613 | 2875 | } |
b29c19b6 | 2876 | } |
0a58705b | 2877 | |
b29c19b6 CW |
2878 | static void |
2879 | i915_gem_idle_work_handler(struct work_struct *work) | |
2880 | { | |
2881 | struct drm_i915_private *dev_priv = | |
67d97da3 | 2882 | container_of(work, typeof(*dev_priv), gt.idle_work.work); |
91c8a326 | 2883 | struct drm_device *dev = &dev_priv->drm; |
b4ac5afc | 2884 | struct intel_engine_cs *engine; |
3b3f1650 | 2885 | enum intel_engine_id id; |
67d97da3 CW |
2886 | bool rearm_hangcheck; |
2887 | ||
2888 | if (!READ_ONCE(dev_priv->gt.awake)) | |
2889 | return; | |
2890 | ||
0cb5670b ID |
2891 | /* |
2892 | * Wait for last execlists context complete, but bail out in case a | |
2893 | * new request is submitted. | |
2894 | */ | |
2895 | wait_for(READ_ONCE(dev_priv->gt.active_requests) || | |
2896 | intel_execlists_idle(dev_priv), 10); | |
2897 | ||
28176ef4 | 2898 | if (READ_ONCE(dev_priv->gt.active_requests)) |
67d97da3 CW |
2899 | return; |
2900 | ||
2901 | rearm_hangcheck = | |
2902 | cancel_delayed_work_sync(&dev_priv->gpu_error.hangcheck_work); | |
2903 | ||
2904 | if (!mutex_trylock(&dev->struct_mutex)) { | |
2905 | /* Currently busy, come back later */ | |
2906 | mod_delayed_work(dev_priv->wq, | |
2907 | &dev_priv->gt.idle_work, | |
2908 | msecs_to_jiffies(50)); | |
2909 | goto out_rearm; | |
2910 | } | |
2911 | ||
93c97dc1 ID |
2912 | /* |
2913 | * New request retired after this work handler started, extend active | |
2914 | * period until next instance of the work. | |
2915 | */ | |
2916 | if (work_pending(work)) | |
2917 | goto out_unlock; | |
2918 | ||
28176ef4 | 2919 | if (dev_priv->gt.active_requests) |
67d97da3 | 2920 | goto out_unlock; |
b29c19b6 | 2921 | |
0cb5670b ID |
2922 | if (wait_for(intel_execlists_idle(dev_priv), 10)) |
2923 | DRM_ERROR("Timeout waiting for engines to idle\n"); | |
2924 | ||
3b3f1650 | 2925 | for_each_engine(engine, dev_priv, id) |
67d97da3 | 2926 | i915_gem_batch_pool_fini(&engine->batch_pool); |
35c94185 | 2927 | |
67d97da3 CW |
2928 | GEM_BUG_ON(!dev_priv->gt.awake); |
2929 | dev_priv->gt.awake = false; | |
2930 | rearm_hangcheck = false; | |
30ecad77 | 2931 | |
67d97da3 CW |
2932 | if (INTEL_GEN(dev_priv) >= 6) |
2933 | gen6_rps_idle(dev_priv); | |
2934 | intel_runtime_pm_put(dev_priv); | |
2935 | out_unlock: | |
2936 | mutex_unlock(&dev->struct_mutex); | |
b29c19b6 | 2937 | |
67d97da3 CW |
2938 | out_rearm: |
2939 | if (rearm_hangcheck) { | |
2940 | GEM_BUG_ON(!dev_priv->gt.awake); | |
2941 | i915_queue_hangcheck(dev_priv); | |
35c94185 | 2942 | } |
673a394b EA |
2943 | } |
2944 | ||
b1f788c6 CW |
2945 | void i915_gem_close_object(struct drm_gem_object *gem, struct drm_file *file) |
2946 | { | |
2947 | struct drm_i915_gem_object *obj = to_intel_bo(gem); | |
2948 | struct drm_i915_file_private *fpriv = file->driver_priv; | |
2949 | struct i915_vma *vma, *vn; | |
2950 | ||
2951 | mutex_lock(&obj->base.dev->struct_mutex); | |
2952 | list_for_each_entry_safe(vma, vn, &obj->vma_list, obj_link) | |
2953 | if (vma->vm->file == fpriv) | |
2954 | i915_vma_close(vma); | |
f8a7fde4 CW |
2955 | |
2956 | if (i915_gem_object_is_active(obj) && | |
2957 | !i915_gem_object_has_active_reference(obj)) { | |
2958 | i915_gem_object_set_active_reference(obj); | |
2959 | i915_gem_object_get(obj); | |
2960 | } | |
b1f788c6 CW |
2961 | mutex_unlock(&obj->base.dev->struct_mutex); |
2962 | } | |
2963 | ||
e95433c7 CW |
2964 | static unsigned long to_wait_timeout(s64 timeout_ns) |
2965 | { | |
2966 | if (timeout_ns < 0) | |
2967 | return MAX_SCHEDULE_TIMEOUT; | |
2968 | ||
2969 | if (timeout_ns == 0) | |
2970 | return 0; | |
2971 | ||
2972 | return nsecs_to_jiffies_timeout(timeout_ns); | |
2973 | } | |
2974 | ||
23ba4fd0 BW |
2975 | /** |
2976 | * i915_gem_wait_ioctl - implements DRM_IOCTL_I915_GEM_WAIT | |
14bb2c11 TU |
2977 | * @dev: drm device pointer |
2978 | * @data: ioctl data blob | |
2979 | * @file: drm file pointer | |
23ba4fd0 BW |
2980 | * |
2981 | * Returns 0 if successful, else an error is returned with the remaining time in | |
2982 | * the timeout parameter. | |
2983 | * -ETIME: object is still busy after timeout | |
2984 | * -ERESTARTSYS: signal interrupted the wait | |
2985 | * -ENONENT: object doesn't exist | |
2986 | * Also possible, but rare: | |
2987 | * -EAGAIN: GPU wedged | |
2988 | * -ENOMEM: damn | |
2989 | * -ENODEV: Internal IRQ fail | |
2990 | * -E?: The add request failed | |
2991 | * | |
2992 | * The wait ioctl with a timeout of 0 reimplements the busy ioctl. With any | |
2993 | * non-zero timeout parameter the wait ioctl will wait for the given number of | |
2994 | * nanoseconds on an object becoming unbusy. Since the wait itself does so | |
2995 | * without holding struct_mutex the object may become re-busied before this | |
2996 | * function completes. A similar but shorter * race condition exists in the busy | |
2997 | * ioctl | |
2998 | */ | |
2999 | int | |
3000 | i915_gem_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *file) | |
3001 | { | |
3002 | struct drm_i915_gem_wait *args = data; | |
3003 | struct drm_i915_gem_object *obj; | |
e95433c7 CW |
3004 | ktime_t start; |
3005 | long ret; | |
23ba4fd0 | 3006 | |
11b5d511 DV |
3007 | if (args->flags != 0) |
3008 | return -EINVAL; | |
3009 | ||
03ac0642 | 3010 | obj = i915_gem_object_lookup(file, args->bo_handle); |
033d549b | 3011 | if (!obj) |
23ba4fd0 | 3012 | return -ENOENT; |
23ba4fd0 | 3013 | |
e95433c7 CW |
3014 | start = ktime_get(); |
3015 | ||
3016 | ret = i915_gem_object_wait(obj, | |
3017 | I915_WAIT_INTERRUPTIBLE | I915_WAIT_ALL, | |
3018 | to_wait_timeout(args->timeout_ns), | |
3019 | to_rps_client(file)); | |
3020 | ||
3021 | if (args->timeout_ns > 0) { | |
3022 | args->timeout_ns -= ktime_to_ns(ktime_sub(ktime_get(), start)); | |
3023 | if (args->timeout_ns < 0) | |
3024 | args->timeout_ns = 0; | |
b4716185 CW |
3025 | } |
3026 | ||
f0cd5182 | 3027 | i915_gem_object_put(obj); |
ff865885 | 3028 | return ret; |
23ba4fd0 BW |
3029 | } |
3030 | ||
73cb9701 | 3031 | static int wait_for_timeline(struct i915_gem_timeline *tl, unsigned int flags) |
4df2faf4 | 3032 | { |
73cb9701 | 3033 | int ret, i; |
4df2faf4 | 3034 | |
73cb9701 CW |
3035 | for (i = 0; i < ARRAY_SIZE(tl->engine); i++) { |
3036 | ret = i915_gem_active_wait(&tl->engine[i].last_request, flags); | |
3037 | if (ret) | |
3038 | return ret; | |
3039 | } | |
62e63007 | 3040 | |
73cb9701 CW |
3041 | return 0; |
3042 | } | |
3043 | ||
3044 | int i915_gem_wait_for_idle(struct drm_i915_private *i915, unsigned int flags) | |
3045 | { | |
73cb9701 CW |
3046 | int ret; |
3047 | ||
9caa34aa CW |
3048 | if (flags & I915_WAIT_LOCKED) { |
3049 | struct i915_gem_timeline *tl; | |
3050 | ||
3051 | lockdep_assert_held(&i915->drm.struct_mutex); | |
3052 | ||
3053 | list_for_each_entry(tl, &i915->gt.timelines, link) { | |
3054 | ret = wait_for_timeline(tl, flags); | |
3055 | if (ret) | |
3056 | return ret; | |
3057 | } | |
3058 | } else { | |
3059 | ret = wait_for_timeline(&i915->gt.global_timeline, flags); | |
1ec14ad3 CW |
3060 | if (ret) |
3061 | return ret; | |
3062 | } | |
4df2faf4 | 3063 | |
8a1a49f9 | 3064 | return 0; |
4df2faf4 DV |
3065 | } |
3066 | ||
d0da48cf CW |
3067 | void i915_gem_clflush_object(struct drm_i915_gem_object *obj, |
3068 | bool force) | |
673a394b | 3069 | { |
673a394b EA |
3070 | /* If we don't have a page list set up, then we're not pinned |
3071 | * to GPU, and we can ignore the cache flush because it'll happen | |
3072 | * again at bind time. | |
3073 | */ | |
a4f5ea64 | 3074 | if (!obj->mm.pages) |
d0da48cf | 3075 | return; |
673a394b | 3076 | |
769ce464 ID |
3077 | /* |
3078 | * Stolen memory is always coherent with the GPU as it is explicitly | |
3079 | * marked as wc by the system, or the system is cache-coherent. | |
3080 | */ | |
6a2c4232 | 3081 | if (obj->stolen || obj->phys_handle) |
d0da48cf | 3082 | return; |
769ce464 | 3083 | |
9c23f7fc CW |
3084 | /* If the GPU is snooping the contents of the CPU cache, |
3085 | * we do not need to manually clear the CPU cache lines. However, | |
3086 | * the caches are only snooped when the render cache is | |
3087 | * flushed/invalidated. As we always have to emit invalidations | |
3088 | * and flushes when moving into and out of the RENDER domain, correct | |
3089 | * snooping behaviour occurs naturally as the result of our domain | |
3090 | * tracking. | |
3091 | */ | |
0f71979a CW |
3092 | if (!force && cpu_cache_is_coherent(obj->base.dev, obj->cache_level)) { |
3093 | obj->cache_dirty = true; | |
d0da48cf | 3094 | return; |
0f71979a | 3095 | } |
9c23f7fc | 3096 | |
1c5d22f7 | 3097 | trace_i915_gem_object_clflush(obj); |
a4f5ea64 | 3098 | drm_clflush_sg(obj->mm.pages); |
0f71979a | 3099 | obj->cache_dirty = false; |
e47c68e9 EA |
3100 | } |
3101 | ||
3102 | /** Flushes the GTT write domain for the object if it's dirty. */ | |
3103 | static void | |
05394f39 | 3104 | i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj) |
e47c68e9 | 3105 | { |
3b5724d7 | 3106 | struct drm_i915_private *dev_priv = to_i915(obj->base.dev); |
1c5d22f7 | 3107 | |
05394f39 | 3108 | if (obj->base.write_domain != I915_GEM_DOMAIN_GTT) |
e47c68e9 EA |
3109 | return; |
3110 | ||
63256ec5 | 3111 | /* No actual flushing is required for the GTT write domain. Writes |
3b5724d7 | 3112 | * to it "immediately" go to main memory as far as we know, so there's |
e47c68e9 | 3113 | * no chipset flush. It also doesn't land in render cache. |
63256ec5 CW |
3114 | * |
3115 | * However, we do have to enforce the order so that all writes through | |
3116 | * the GTT land before any writes to the device, such as updates to | |
3117 | * the GATT itself. | |
3b5724d7 CW |
3118 | * |
3119 | * We also have to wait a bit for the writes to land from the GTT. | |
3120 | * An uncached read (i.e. mmio) seems to be ideal for the round-trip | |
3121 | * timing. This issue has only been observed when switching quickly | |
3122 | * between GTT writes and CPU reads from inside the kernel on recent hw, | |
3123 | * and it appears to only affect discrete GTT blocks (i.e. on LLC | |
3124 | * system agents we cannot reproduce this behaviour). | |
e47c68e9 | 3125 | */ |
63256ec5 | 3126 | wmb(); |
3b5724d7 | 3127 | if (INTEL_GEN(dev_priv) >= 6 && !HAS_LLC(dev_priv)) |
3b3f1650 | 3128 | POSTING_READ(RING_ACTHD(dev_priv->engine[RCS]->mmio_base)); |
63256ec5 | 3129 | |
d243ad82 | 3130 | intel_fb_obj_flush(obj, false, write_origin(obj, I915_GEM_DOMAIN_GTT)); |
f99d7069 | 3131 | |
b0dc465f | 3132 | obj->base.write_domain = 0; |
1c5d22f7 | 3133 | trace_i915_gem_object_change_domain(obj, |
05394f39 | 3134 | obj->base.read_domains, |
b0dc465f | 3135 | I915_GEM_DOMAIN_GTT); |
e47c68e9 EA |
3136 | } |
3137 | ||
3138 | /** Flushes the CPU write domain for the object if it's dirty. */ | |
3139 | static void | |
e62b59e4 | 3140 | i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj) |
e47c68e9 | 3141 | { |
05394f39 | 3142 | if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) |
e47c68e9 EA |
3143 | return; |
3144 | ||
d0da48cf | 3145 | i915_gem_clflush_object(obj, obj->pin_display); |
de152b62 | 3146 | intel_fb_obj_flush(obj, false, ORIGIN_CPU); |
f99d7069 | 3147 | |
b0dc465f | 3148 | obj->base.write_domain = 0; |
1c5d22f7 | 3149 | trace_i915_gem_object_change_domain(obj, |
05394f39 | 3150 | obj->base.read_domains, |
b0dc465f | 3151 | I915_GEM_DOMAIN_CPU); |
e47c68e9 EA |
3152 | } |
3153 | ||
2ef7eeaa EA |
3154 | /** |
3155 | * Moves a single object to the GTT read, and possibly write domain. | |
14bb2c11 TU |
3156 | * @obj: object to act on |
3157 | * @write: ask for write access or read only | |
2ef7eeaa EA |
3158 | * |
3159 | * This function returns when the move is complete, including waiting on | |
3160 | * flushes to occur. | |
3161 | */ | |
79e53945 | 3162 | int |
2021746e | 3163 | i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write) |
2ef7eeaa | 3164 | { |
1c5d22f7 | 3165 | uint32_t old_write_domain, old_read_domains; |
e47c68e9 | 3166 | int ret; |
2ef7eeaa | 3167 | |
e95433c7 | 3168 | lockdep_assert_held(&obj->base.dev->struct_mutex); |
4c7d62c6 | 3169 | |
e95433c7 CW |
3170 | ret = i915_gem_object_wait(obj, |
3171 | I915_WAIT_INTERRUPTIBLE | | |
3172 | I915_WAIT_LOCKED | | |
3173 | (write ? I915_WAIT_ALL : 0), | |
3174 | MAX_SCHEDULE_TIMEOUT, | |
3175 | NULL); | |
88241785 CW |
3176 | if (ret) |
3177 | return ret; | |
3178 | ||
c13d87ea CW |
3179 | if (obj->base.write_domain == I915_GEM_DOMAIN_GTT) |
3180 | return 0; | |
3181 | ||
43566ded CW |
3182 | /* Flush and acquire obj->pages so that we are coherent through |
3183 | * direct access in memory with previous cached writes through | |
3184 | * shmemfs and that our cache domain tracking remains valid. | |
3185 | * For example, if the obj->filp was moved to swap without us | |
3186 | * being notified and releasing the pages, we would mistakenly | |
3187 | * continue to assume that the obj remained out of the CPU cached | |
3188 | * domain. | |
3189 | */ | |
a4f5ea64 | 3190 | ret = i915_gem_object_pin_pages(obj); |
43566ded CW |
3191 | if (ret) |
3192 | return ret; | |
3193 | ||
e62b59e4 | 3194 | i915_gem_object_flush_cpu_write_domain(obj); |
1c5d22f7 | 3195 | |
d0a57789 CW |
3196 | /* Serialise direct access to this object with the barriers for |
3197 | * coherent writes from the GPU, by effectively invalidating the | |
3198 | * GTT domain upon first access. | |
3199 | */ | |
3200 | if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0) | |
3201 | mb(); | |
3202 | ||
05394f39 CW |
3203 | old_write_domain = obj->base.write_domain; |
3204 | old_read_domains = obj->base.read_domains; | |
1c5d22f7 | 3205 | |
e47c68e9 EA |
3206 | /* It should now be out of any other write domains, and we can update |
3207 | * the domain values for our changes. | |
3208 | */ | |
40e62d5d | 3209 | GEM_BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) != 0); |
05394f39 | 3210 | obj->base.read_domains |= I915_GEM_DOMAIN_GTT; |
e47c68e9 | 3211 | if (write) { |
05394f39 CW |
3212 | obj->base.read_domains = I915_GEM_DOMAIN_GTT; |
3213 | obj->base.write_domain = I915_GEM_DOMAIN_GTT; | |
a4f5ea64 | 3214 | obj->mm.dirty = true; |
2ef7eeaa EA |
3215 | } |
3216 | ||
1c5d22f7 CW |
3217 | trace_i915_gem_object_change_domain(obj, |
3218 | old_read_domains, | |
3219 | old_write_domain); | |
3220 | ||
a4f5ea64 | 3221 | i915_gem_object_unpin_pages(obj); |
e47c68e9 EA |
3222 | return 0; |
3223 | } | |
3224 | ||
ef55f92a CW |
3225 | /** |
3226 | * Changes the cache-level of an object across all VMA. | |
14bb2c11 TU |
3227 | * @obj: object to act on |
3228 | * @cache_level: new cache level to set for the object | |
ef55f92a CW |
3229 | * |
3230 | * After this function returns, the object will be in the new cache-level | |
3231 | * across all GTT and the contents of the backing storage will be coherent, | |
3232 | * with respect to the new cache-level. In order to keep the backing storage | |
3233 | * coherent for all users, we only allow a single cache level to be set | |
3234 | * globally on the object and prevent it from being changed whilst the | |
3235 | * hardware is reading from the object. That is if the object is currently | |
3236 | * on the scanout it will be set to uncached (or equivalent display | |
3237 | * cache coherency) and all non-MOCS GPU access will also be uncached so | |
3238 | * that all direct access to the scanout remains coherent. | |
3239 | */ | |
e4ffd173 CW |
3240 | int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj, |
3241 | enum i915_cache_level cache_level) | |
3242 | { | |
aa653a68 | 3243 | struct i915_vma *vma; |
a6a7cc4b | 3244 | int ret; |
e4ffd173 | 3245 | |
4c7d62c6 CW |
3246 | lockdep_assert_held(&obj->base.dev->struct_mutex); |
3247 | ||
e4ffd173 | 3248 | if (obj->cache_level == cache_level) |
a6a7cc4b | 3249 | return 0; |
e4ffd173 | 3250 | |
ef55f92a CW |
3251 | /* Inspect the list of currently bound VMA and unbind any that would |
3252 | * be invalid given the new cache-level. This is principally to | |
3253 | * catch the issue of the CS prefetch crossing page boundaries and | |
3254 | * reading an invalid PTE on older architectures. | |
3255 | */ | |
aa653a68 CW |
3256 | restart: |
3257 | list_for_each_entry(vma, &obj->vma_list, obj_link) { | |
ef55f92a CW |
3258 | if (!drm_mm_node_allocated(&vma->node)) |
3259 | continue; | |
3260 | ||
20dfbde4 | 3261 | if (i915_vma_is_pinned(vma)) { |
ef55f92a CW |
3262 | DRM_DEBUG("can not change the cache level of pinned objects\n"); |
3263 | return -EBUSY; | |
3264 | } | |
3265 | ||
aa653a68 CW |
3266 | if (i915_gem_valid_gtt_space(vma, cache_level)) |
3267 | continue; | |
3268 | ||
3269 | ret = i915_vma_unbind(vma); | |
3270 | if (ret) | |
3271 | return ret; | |
3272 | ||
3273 | /* As unbinding may affect other elements in the | |
3274 | * obj->vma_list (due to side-effects from retiring | |
3275 | * an active vma), play safe and restart the iterator. | |
3276 | */ | |
3277 | goto restart; | |
42d6ab48 CW |
3278 | } |
3279 | ||
ef55f92a CW |
3280 | /* We can reuse the existing drm_mm nodes but need to change the |
3281 | * cache-level on the PTE. We could simply unbind them all and | |
3282 | * rebind with the correct cache-level on next use. However since | |
3283 | * we already have a valid slot, dma mapping, pages etc, we may as | |
3284 | * rewrite the PTE in the belief that doing so tramples upon less | |
3285 | * state and so involves less work. | |
3286 | */ | |
15717de2 | 3287 | if (obj->bind_count) { |
ef55f92a CW |
3288 | /* Before we change the PTE, the GPU must not be accessing it. |
3289 | * If we wait upon the object, we know that all the bound | |
3290 | * VMA are no longer active. | |
3291 | */ | |
e95433c7 CW |
3292 | ret = i915_gem_object_wait(obj, |
3293 | I915_WAIT_INTERRUPTIBLE | | |
3294 | I915_WAIT_LOCKED | | |
3295 | I915_WAIT_ALL, | |
3296 | MAX_SCHEDULE_TIMEOUT, | |
3297 | NULL); | |
e4ffd173 CW |
3298 | if (ret) |
3299 | return ret; | |
3300 | ||
0031fb96 TU |
3301 | if (!HAS_LLC(to_i915(obj->base.dev)) && |
3302 | cache_level != I915_CACHE_NONE) { | |
ef55f92a CW |
3303 | /* Access to snoopable pages through the GTT is |
3304 | * incoherent and on some machines causes a hard | |
3305 | * lockup. Relinquish the CPU mmaping to force | |
3306 | * userspace to refault in the pages and we can | |
3307 | * then double check if the GTT mapping is still | |
3308 | * valid for that pointer access. | |
3309 | */ | |
3310 | i915_gem_release_mmap(obj); | |
3311 | ||
3312 | /* As we no longer need a fence for GTT access, | |
3313 | * we can relinquish it now (and so prevent having | |
3314 | * to steal a fence from someone else on the next | |
3315 | * fence request). Note GPU activity would have | |
3316 | * dropped the fence as all snoopable access is | |
3317 | * supposed to be linear. | |
3318 | */ | |
49ef5294 CW |
3319 | list_for_each_entry(vma, &obj->vma_list, obj_link) { |
3320 | ret = i915_vma_put_fence(vma); | |
3321 | if (ret) | |
3322 | return ret; | |
3323 | } | |
ef55f92a CW |
3324 | } else { |
3325 | /* We either have incoherent backing store and | |
3326 | * so no GTT access or the architecture is fully | |
3327 | * coherent. In such cases, existing GTT mmaps | |
3328 | * ignore the cache bit in the PTE and we can | |
3329 | * rewrite it without confusing the GPU or having | |
3330 | * to force userspace to fault back in its mmaps. | |
3331 | */ | |
e4ffd173 CW |
3332 | } |
3333 | ||
1c7f4bca | 3334 | list_for_each_entry(vma, &obj->vma_list, obj_link) { |
ef55f92a CW |
3335 | if (!drm_mm_node_allocated(&vma->node)) |
3336 | continue; | |
3337 | ||
3338 | ret = i915_vma_bind(vma, cache_level, PIN_UPDATE); | |
3339 | if (ret) | |
3340 | return ret; | |
3341 | } | |
e4ffd173 CW |
3342 | } |
3343 | ||
a6a7cc4b CW |
3344 | if (obj->base.write_domain == I915_GEM_DOMAIN_CPU && |
3345 | cpu_cache_is_coherent(obj->base.dev, obj->cache_level)) | |
3346 | obj->cache_dirty = true; | |
3347 | ||
1c7f4bca | 3348 | list_for_each_entry(vma, &obj->vma_list, obj_link) |
2c22569b CW |
3349 | vma->node.color = cache_level; |
3350 | obj->cache_level = cache_level; | |
3351 | ||
e4ffd173 CW |
3352 | return 0; |
3353 | } | |
3354 | ||
199adf40 BW |
3355 | int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data, |
3356 | struct drm_file *file) | |
e6994aee | 3357 | { |
199adf40 | 3358 | struct drm_i915_gem_caching *args = data; |
e6994aee | 3359 | struct drm_i915_gem_object *obj; |
fbbd37b3 | 3360 | int err = 0; |
e6994aee | 3361 | |
fbbd37b3 CW |
3362 | rcu_read_lock(); |
3363 | obj = i915_gem_object_lookup_rcu(file, args->handle); | |
3364 | if (!obj) { | |
3365 | err = -ENOENT; | |
3366 | goto out; | |
3367 | } | |
e6994aee | 3368 | |
651d794f CW |
3369 | switch (obj->cache_level) { |
3370 | case I915_CACHE_LLC: | |
3371 | case I915_CACHE_L3_LLC: | |
3372 | args->caching = I915_CACHING_CACHED; | |
3373 | break; | |
3374 | ||
4257d3ba CW |
3375 | case I915_CACHE_WT: |
3376 | args->caching = I915_CACHING_DISPLAY; | |
3377 | break; | |
3378 | ||
651d794f CW |
3379 | default: |
3380 | args->caching = I915_CACHING_NONE; | |
3381 | break; | |
3382 | } | |
fbbd37b3 CW |
3383 | out: |
3384 | rcu_read_unlock(); | |
3385 | return err; | |
e6994aee CW |
3386 | } |
3387 | ||
199adf40 BW |
3388 | int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data, |
3389 | struct drm_file *file) | |
e6994aee | 3390 | { |
9c870d03 | 3391 | struct drm_i915_private *i915 = to_i915(dev); |
199adf40 | 3392 | struct drm_i915_gem_caching *args = data; |
e6994aee CW |
3393 | struct drm_i915_gem_object *obj; |
3394 | enum i915_cache_level level; | |
3395 | int ret; | |
3396 | ||
199adf40 BW |
3397 | switch (args->caching) { |
3398 | case I915_CACHING_NONE: | |
e6994aee CW |
3399 | level = I915_CACHE_NONE; |
3400 | break; | |
199adf40 | 3401 | case I915_CACHING_CACHED: |
e5756c10 ID |
3402 | /* |
3403 | * Due to a HW issue on BXT A stepping, GPU stores via a | |
3404 | * snooped mapping may leave stale data in a corresponding CPU | |
3405 | * cacheline, whereas normally such cachelines would get | |
3406 | * invalidated. | |
3407 | */ | |
9c870d03 | 3408 | if (!HAS_LLC(i915) && !HAS_SNOOP(i915)) |
e5756c10 ID |
3409 | return -ENODEV; |
3410 | ||
e6994aee CW |
3411 | level = I915_CACHE_LLC; |
3412 | break; | |
4257d3ba | 3413 | case I915_CACHING_DISPLAY: |
9c870d03 | 3414 | level = HAS_WT(i915) ? I915_CACHE_WT : I915_CACHE_NONE; |
4257d3ba | 3415 | break; |
e6994aee CW |
3416 | default: |
3417 | return -EINVAL; | |
3418 | } | |
3419 | ||
3bc2913e BW |
3420 | ret = i915_mutex_lock_interruptible(dev); |
3421 | if (ret) | |
9c870d03 | 3422 | return ret; |
3bc2913e | 3423 | |
03ac0642 CW |
3424 | obj = i915_gem_object_lookup(file, args->handle); |
3425 | if (!obj) { | |
e6994aee CW |
3426 | ret = -ENOENT; |
3427 | goto unlock; | |
3428 | } | |
3429 | ||
3430 | ret = i915_gem_object_set_cache_level(obj, level); | |
f8c417cd | 3431 | i915_gem_object_put(obj); |
e6994aee CW |
3432 | unlock: |
3433 | mutex_unlock(&dev->struct_mutex); | |
3434 | return ret; | |
3435 | } | |
3436 | ||
b9241ea3 | 3437 | /* |
2da3b9b9 CW |
3438 | * Prepare buffer for display plane (scanout, cursors, etc). |
3439 | * Can be called from an uninterruptible phase (modesetting) and allows | |
3440 | * any flushes to be pipelined (for pageflips). | |
b9241ea3 | 3441 | */ |
058d88c4 | 3442 | struct i915_vma * |
2da3b9b9 CW |
3443 | i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj, |
3444 | u32 alignment, | |
e6617330 | 3445 | const struct i915_ggtt_view *view) |
b9241ea3 | 3446 | { |
058d88c4 | 3447 | struct i915_vma *vma; |
2da3b9b9 | 3448 | u32 old_read_domains, old_write_domain; |
b9241ea3 ZW |
3449 | int ret; |
3450 | ||
4c7d62c6 CW |
3451 | lockdep_assert_held(&obj->base.dev->struct_mutex); |
3452 | ||
cc98b413 CW |
3453 | /* Mark the pin_display early so that we account for the |
3454 | * display coherency whilst setting up the cache domains. | |
3455 | */ | |
8a0c39b1 | 3456 | obj->pin_display++; |
cc98b413 | 3457 | |
a7ef0640 EA |
3458 | /* The display engine is not coherent with the LLC cache on gen6. As |
3459 | * a result, we make sure that the pinning that is about to occur is | |
3460 | * done with uncached PTEs. This is lowest common denominator for all | |
3461 | * chipsets. | |
3462 | * | |
3463 | * However for gen6+, we could do better by using the GFDT bit instead | |
3464 | * of uncaching, which would allow us to flush all the LLC-cached data | |
3465 | * with that bit in the PTE to main memory with just one PIPE_CONTROL. | |
3466 | */ | |
651d794f | 3467 | ret = i915_gem_object_set_cache_level(obj, |
8652744b TU |
3468 | HAS_WT(to_i915(obj->base.dev)) ? |
3469 | I915_CACHE_WT : I915_CACHE_NONE); | |
058d88c4 CW |
3470 | if (ret) { |
3471 | vma = ERR_PTR(ret); | |
cc98b413 | 3472 | goto err_unpin_display; |
058d88c4 | 3473 | } |
a7ef0640 | 3474 | |
2da3b9b9 CW |
3475 | /* As the user may map the buffer once pinned in the display plane |
3476 | * (e.g. libkms for the bootup splash), we have to ensure that we | |
2efb813d CW |
3477 | * always use map_and_fenceable for all scanout buffers. However, |
3478 | * it may simply be too big to fit into mappable, in which case | |
3479 | * put it anyway and hope that userspace can cope (but always first | |
3480 | * try to preserve the existing ABI). | |
2da3b9b9 | 3481 | */ |
2efb813d CW |
3482 | vma = ERR_PTR(-ENOSPC); |
3483 | if (view->type == I915_GGTT_VIEW_NORMAL) | |
3484 | vma = i915_gem_object_ggtt_pin(obj, view, 0, alignment, | |
3485 | PIN_MAPPABLE | PIN_NONBLOCK); | |
767a222e CW |
3486 | if (IS_ERR(vma)) { |
3487 | struct drm_i915_private *i915 = to_i915(obj->base.dev); | |
3488 | unsigned int flags; | |
3489 | ||
3490 | /* Valleyview is definitely limited to scanning out the first | |
3491 | * 512MiB. Lets presume this behaviour was inherited from the | |
3492 | * g4x display engine and that all earlier gen are similarly | |
3493 | * limited. Testing suggests that it is a little more | |
3494 | * complicated than this. For example, Cherryview appears quite | |
3495 | * happy to scanout from anywhere within its global aperture. | |
3496 | */ | |
3497 | flags = 0; | |
3498 | if (HAS_GMCH_DISPLAY(i915)) | |
3499 | flags = PIN_MAPPABLE; | |
3500 | vma = i915_gem_object_ggtt_pin(obj, view, 0, alignment, flags); | |
3501 | } | |
058d88c4 | 3502 | if (IS_ERR(vma)) |
cc98b413 | 3503 | goto err_unpin_display; |
2da3b9b9 | 3504 | |
d8923dcf CW |
3505 | vma->display_alignment = max_t(u64, vma->display_alignment, alignment); |
3506 | ||
a6a7cc4b CW |
3507 | /* Treat this as an end-of-frame, like intel_user_framebuffer_dirty() */ |
3508 | if (obj->cache_dirty) { | |
3509 | i915_gem_clflush_object(obj, true); | |
3510 | intel_fb_obj_flush(obj, false, ORIGIN_DIRTYFB); | |
3511 | } | |
b118c1e3 | 3512 | |
2da3b9b9 | 3513 | old_write_domain = obj->base.write_domain; |
05394f39 | 3514 | old_read_domains = obj->base.read_domains; |
2da3b9b9 CW |
3515 | |
3516 | /* It should now be out of any other write domains, and we can update | |
3517 | * the domain values for our changes. | |
3518 | */ | |
e5f1d962 | 3519 | obj->base.write_domain = 0; |
05394f39 | 3520 | obj->base.read_domains |= I915_GEM_DOMAIN_GTT; |
b9241ea3 ZW |
3521 | |
3522 | trace_i915_gem_object_change_domain(obj, | |
3523 | old_read_domains, | |
2da3b9b9 | 3524 | old_write_domain); |
b9241ea3 | 3525 | |
058d88c4 | 3526 | return vma; |
cc98b413 CW |
3527 | |
3528 | err_unpin_display: | |
8a0c39b1 | 3529 | obj->pin_display--; |
058d88c4 | 3530 | return vma; |
cc98b413 CW |
3531 | } |
3532 | ||
3533 | void | |
058d88c4 | 3534 | i915_gem_object_unpin_from_display_plane(struct i915_vma *vma) |
cc98b413 | 3535 | { |
49d73912 | 3536 | lockdep_assert_held(&vma->vm->i915->drm.struct_mutex); |
4c7d62c6 | 3537 | |
058d88c4 | 3538 | if (WARN_ON(vma->obj->pin_display == 0)) |
8a0c39b1 TU |
3539 | return; |
3540 | ||
d8923dcf CW |
3541 | if (--vma->obj->pin_display == 0) |
3542 | vma->display_alignment = 0; | |
e6617330 | 3543 | |
383d5823 CW |
3544 | /* Bump the LRU to try and avoid premature eviction whilst flipping */ |
3545 | if (!i915_vma_is_active(vma)) | |
3546 | list_move_tail(&vma->vm_link, &vma->vm->inactive_list); | |
3547 | ||
058d88c4 | 3548 | i915_vma_unpin(vma); |
b9241ea3 ZW |
3549 | } |
3550 | ||
e47c68e9 EA |
3551 | /** |
3552 | * Moves a single object to the CPU read, and possibly write domain. | |
14bb2c11 TU |
3553 | * @obj: object to act on |
3554 | * @write: requesting write or read-only access | |
e47c68e9 EA |
3555 | * |
3556 | * This function returns when the move is complete, including waiting on | |
3557 | * flushes to occur. | |
3558 | */ | |
dabdfe02 | 3559 | int |
919926ae | 3560 | i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write) |
e47c68e9 | 3561 | { |
1c5d22f7 | 3562 | uint32_t old_write_domain, old_read_domains; |
e47c68e9 EA |
3563 | int ret; |
3564 | ||
e95433c7 | 3565 | lockdep_assert_held(&obj->base.dev->struct_mutex); |
4c7d62c6 | 3566 | |
e95433c7 CW |
3567 | ret = i915_gem_object_wait(obj, |
3568 | I915_WAIT_INTERRUPTIBLE | | |
3569 | I915_WAIT_LOCKED | | |
3570 | (write ? I915_WAIT_ALL : 0), | |
3571 | MAX_SCHEDULE_TIMEOUT, | |
3572 | NULL); | |
88241785 CW |
3573 | if (ret) |
3574 | return ret; | |
3575 | ||
c13d87ea CW |
3576 | if (obj->base.write_domain == I915_GEM_DOMAIN_CPU) |
3577 | return 0; | |
3578 | ||
e47c68e9 | 3579 | i915_gem_object_flush_gtt_write_domain(obj); |
2ef7eeaa | 3580 | |
05394f39 CW |
3581 | old_write_domain = obj->base.write_domain; |
3582 | old_read_domains = obj->base.read_domains; | |
1c5d22f7 | 3583 | |
e47c68e9 | 3584 | /* Flush the CPU cache if it's still invalid. */ |
05394f39 | 3585 | if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) { |
2c22569b | 3586 | i915_gem_clflush_object(obj, false); |
2ef7eeaa | 3587 | |
05394f39 | 3588 | obj->base.read_domains |= I915_GEM_DOMAIN_CPU; |
2ef7eeaa EA |
3589 | } |
3590 | ||
3591 | /* It should now be out of any other write domains, and we can update | |
3592 | * the domain values for our changes. | |
3593 | */ | |
40e62d5d | 3594 | GEM_BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) != 0); |
e47c68e9 EA |
3595 | |
3596 | /* If we're writing through the CPU, then the GPU read domains will | |
3597 | * need to be invalidated at next use. | |
3598 | */ | |
3599 | if (write) { | |
05394f39 CW |
3600 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; |
3601 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; | |
e47c68e9 | 3602 | } |
2ef7eeaa | 3603 | |
1c5d22f7 CW |
3604 | trace_i915_gem_object_change_domain(obj, |
3605 | old_read_domains, | |
3606 | old_write_domain); | |
3607 | ||
2ef7eeaa EA |
3608 | return 0; |
3609 | } | |
3610 | ||
673a394b EA |
3611 | /* Throttle our rendering by waiting until the ring has completed our requests |
3612 | * emitted over 20 msec ago. | |
3613 | * | |
b962442e EA |
3614 | * Note that if we were to use the current jiffies each time around the loop, |
3615 | * we wouldn't escape the function with any frames outstanding if the time to | |
3616 | * render a frame was over 20ms. | |
3617 | * | |
673a394b EA |
3618 | * This should get us reasonable parallelism between CPU and GPU but also |
3619 | * relatively low latency when blocking on a particular request to finish. | |
3620 | */ | |
40a5f0de | 3621 | static int |
f787a5f5 | 3622 | i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file) |
40a5f0de | 3623 | { |
fac5e23e | 3624 | struct drm_i915_private *dev_priv = to_i915(dev); |
f787a5f5 | 3625 | struct drm_i915_file_private *file_priv = file->driver_priv; |
d0bc54f2 | 3626 | unsigned long recent_enough = jiffies - DRM_I915_THROTTLE_JIFFIES; |
54fb2411 | 3627 | struct drm_i915_gem_request *request, *target = NULL; |
e95433c7 | 3628 | long ret; |
93533c29 | 3629 | |
f4457ae7 CW |
3630 | /* ABI: return -EIO if already wedged */ |
3631 | if (i915_terminally_wedged(&dev_priv->gpu_error)) | |
3632 | return -EIO; | |
e110e8d6 | 3633 | |
1c25595f | 3634 | spin_lock(&file_priv->mm.lock); |
f787a5f5 | 3635 | list_for_each_entry(request, &file_priv->mm.request_list, client_list) { |
b962442e EA |
3636 | if (time_after_eq(request->emitted_jiffies, recent_enough)) |
3637 | break; | |
40a5f0de | 3638 | |
fcfa423c JH |
3639 | /* |
3640 | * Note that the request might not have been submitted yet. | |
3641 | * In which case emitted_jiffies will be zero. | |
3642 | */ | |
3643 | if (!request->emitted_jiffies) | |
3644 | continue; | |
3645 | ||
54fb2411 | 3646 | target = request; |
b962442e | 3647 | } |
ff865885 | 3648 | if (target) |
e8a261ea | 3649 | i915_gem_request_get(target); |
1c25595f | 3650 | spin_unlock(&file_priv->mm.lock); |
40a5f0de | 3651 | |
54fb2411 | 3652 | if (target == NULL) |
f787a5f5 | 3653 | return 0; |
2bc43b5c | 3654 | |
e95433c7 CW |
3655 | ret = i915_wait_request(target, |
3656 | I915_WAIT_INTERRUPTIBLE, | |
3657 | MAX_SCHEDULE_TIMEOUT); | |
e8a261ea | 3658 | i915_gem_request_put(target); |
ff865885 | 3659 | |
e95433c7 | 3660 | return ret < 0 ? ret : 0; |
40a5f0de EA |
3661 | } |
3662 | ||
058d88c4 | 3663 | struct i915_vma * |
ec7adb6e JL |
3664 | i915_gem_object_ggtt_pin(struct drm_i915_gem_object *obj, |
3665 | const struct i915_ggtt_view *view, | |
91b2db6f | 3666 | u64 size, |
2ffffd0f CW |
3667 | u64 alignment, |
3668 | u64 flags) | |
ec7adb6e | 3669 | { |
ad16d2ed CW |
3670 | struct drm_i915_private *dev_priv = to_i915(obj->base.dev); |
3671 | struct i915_address_space *vm = &dev_priv->ggtt.base; | |
59bfa124 CW |
3672 | struct i915_vma *vma; |
3673 | int ret; | |
72e96d64 | 3674 | |
4c7d62c6 CW |
3675 | lockdep_assert_held(&obj->base.dev->struct_mutex); |
3676 | ||
058d88c4 | 3677 | vma = i915_gem_obj_lookup_or_create_vma(obj, vm, view); |
59bfa124 | 3678 | if (IS_ERR(vma)) |
058d88c4 | 3679 | return vma; |
59bfa124 CW |
3680 | |
3681 | if (i915_vma_misplaced(vma, size, alignment, flags)) { | |
3682 | if (flags & PIN_NONBLOCK && | |
3683 | (i915_vma_is_pinned(vma) || i915_vma_is_active(vma))) | |
058d88c4 | 3684 | return ERR_PTR(-ENOSPC); |
59bfa124 | 3685 | |
ad16d2ed CW |
3686 | if (flags & PIN_MAPPABLE) { |
3687 | u32 fence_size; | |
3688 | ||
3689 | fence_size = i915_gem_get_ggtt_size(dev_priv, vma->size, | |
3690 | i915_gem_object_get_tiling(obj)); | |
3691 | /* If the required space is larger than the available | |
3692 | * aperture, we will not able to find a slot for the | |
3693 | * object and unbinding the object now will be in | |
3694 | * vain. Worse, doing so may cause us to ping-pong | |
3695 | * the object in and out of the Global GTT and | |
3696 | * waste a lot of cycles under the mutex. | |
3697 | */ | |
3698 | if (fence_size > dev_priv->ggtt.mappable_end) | |
3699 | return ERR_PTR(-E2BIG); | |
3700 | ||
3701 | /* If NONBLOCK is set the caller is optimistically | |
3702 | * trying to cache the full object within the mappable | |
3703 | * aperture, and *must* have a fallback in place for | |
3704 | * situations where we cannot bind the object. We | |
3705 | * can be a little more lax here and use the fallback | |
3706 | * more often to avoid costly migrations of ourselves | |
3707 | * and other objects within the aperture. | |
3708 | * | |
3709 | * Half-the-aperture is used as a simple heuristic. | |
3710 | * More interesting would to do search for a free | |
3711 | * block prior to making the commitment to unbind. | |
3712 | * That caters for the self-harm case, and with a | |
3713 | * little more heuristics (e.g. NOFAULT, NOEVICT) | |
3714 | * we could try to minimise harm to others. | |
3715 | */ | |
3716 | if (flags & PIN_NONBLOCK && | |
3717 | fence_size > dev_priv->ggtt.mappable_end / 2) | |
3718 | return ERR_PTR(-ENOSPC); | |
3719 | } | |
3720 | ||
59bfa124 CW |
3721 | WARN(i915_vma_is_pinned(vma), |
3722 | "bo is already pinned in ggtt with incorrect alignment:" | |
05a20d09 CW |
3723 | " offset=%08x, req.alignment=%llx," |
3724 | " req.map_and_fenceable=%d, vma->map_and_fenceable=%d\n", | |
3725 | i915_ggtt_offset(vma), alignment, | |
59bfa124 | 3726 | !!(flags & PIN_MAPPABLE), |
05a20d09 | 3727 | i915_vma_is_map_and_fenceable(vma)); |
59bfa124 CW |
3728 | ret = i915_vma_unbind(vma); |
3729 | if (ret) | |
058d88c4 | 3730 | return ERR_PTR(ret); |
59bfa124 CW |
3731 | } |
3732 | ||
058d88c4 CW |
3733 | ret = i915_vma_pin(vma, size, alignment, flags | PIN_GLOBAL); |
3734 | if (ret) | |
3735 | return ERR_PTR(ret); | |
ec7adb6e | 3736 | |
058d88c4 | 3737 | return vma; |
673a394b EA |
3738 | } |
3739 | ||
edf6b76f | 3740 | static __always_inline unsigned int __busy_read_flag(unsigned int id) |
3fdc13c7 CW |
3741 | { |
3742 | /* Note that we could alias engines in the execbuf API, but | |
3743 | * that would be very unwise as it prevents userspace from | |
3744 | * fine control over engine selection. Ahem. | |
3745 | * | |
3746 | * This should be something like EXEC_MAX_ENGINE instead of | |
3747 | * I915_NUM_ENGINES. | |
3748 | */ | |
3749 | BUILD_BUG_ON(I915_NUM_ENGINES > 16); | |
3750 | return 0x10000 << id; | |
3751 | } | |
3752 | ||
3753 | static __always_inline unsigned int __busy_write_id(unsigned int id) | |
3754 | { | |
70cb472c CW |
3755 | /* The uABI guarantees an active writer is also amongst the read |
3756 | * engines. This would be true if we accessed the activity tracking | |
3757 | * under the lock, but as we perform the lookup of the object and | |
3758 | * its activity locklessly we can not guarantee that the last_write | |
3759 | * being active implies that we have set the same engine flag from | |
3760 | * last_read - hence we always set both read and write busy for | |
3761 | * last_write. | |
3762 | */ | |
3763 | return id | __busy_read_flag(id); | |
3fdc13c7 CW |
3764 | } |
3765 | ||
edf6b76f | 3766 | static __always_inline unsigned int |
d07f0e59 | 3767 | __busy_set_if_active(const struct dma_fence *fence, |
3fdc13c7 CW |
3768 | unsigned int (*flag)(unsigned int id)) |
3769 | { | |
d07f0e59 | 3770 | struct drm_i915_gem_request *rq; |
3fdc13c7 | 3771 | |
d07f0e59 CW |
3772 | /* We have to check the current hw status of the fence as the uABI |
3773 | * guarantees forward progress. We could rely on the idle worker | |
3774 | * to eventually flush us, but to minimise latency just ask the | |
3775 | * hardware. | |
1255501d | 3776 | * |
d07f0e59 | 3777 | * Note we only report on the status of native fences. |
1255501d | 3778 | */ |
d07f0e59 CW |
3779 | if (!dma_fence_is_i915(fence)) |
3780 | return 0; | |
3781 | ||
3782 | /* opencode to_request() in order to avoid const warnings */ | |
3783 | rq = container_of(fence, struct drm_i915_gem_request, fence); | |
3784 | if (i915_gem_request_completed(rq)) | |
3785 | return 0; | |
3786 | ||
3787 | return flag(rq->engine->exec_id); | |
3fdc13c7 CW |
3788 | } |
3789 | ||
edf6b76f | 3790 | static __always_inline unsigned int |
d07f0e59 | 3791 | busy_check_reader(const struct dma_fence *fence) |
3fdc13c7 | 3792 | { |
d07f0e59 | 3793 | return __busy_set_if_active(fence, __busy_read_flag); |
3fdc13c7 CW |
3794 | } |
3795 | ||
edf6b76f | 3796 | static __always_inline unsigned int |
d07f0e59 | 3797 | busy_check_writer(const struct dma_fence *fence) |
3fdc13c7 | 3798 | { |
d07f0e59 CW |
3799 | if (!fence) |
3800 | return 0; | |
3801 | ||
3802 | return __busy_set_if_active(fence, __busy_write_id); | |
3fdc13c7 CW |
3803 | } |
3804 | ||
673a394b EA |
3805 | int |
3806 | i915_gem_busy_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 3807 | struct drm_file *file) |
673a394b EA |
3808 | { |
3809 | struct drm_i915_gem_busy *args = data; | |
05394f39 | 3810 | struct drm_i915_gem_object *obj; |
d07f0e59 CW |
3811 | struct reservation_object_list *list; |
3812 | unsigned int seq; | |
fbbd37b3 | 3813 | int err; |
673a394b | 3814 | |
d07f0e59 | 3815 | err = -ENOENT; |
fbbd37b3 CW |
3816 | rcu_read_lock(); |
3817 | obj = i915_gem_object_lookup_rcu(file, args->handle); | |
d07f0e59 | 3818 | if (!obj) |
fbbd37b3 | 3819 | goto out; |
d1b851fc | 3820 | |
d07f0e59 CW |
3821 | /* A discrepancy here is that we do not report the status of |
3822 | * non-i915 fences, i.e. even though we may report the object as idle, | |
3823 | * a call to set-domain may still stall waiting for foreign rendering. | |
3824 | * This also means that wait-ioctl may report an object as busy, | |
3825 | * where busy-ioctl considers it idle. | |
3826 | * | |
3827 | * We trade the ability to warn of foreign fences to report on which | |
3828 | * i915 engines are active for the object. | |
3829 | * | |
3830 | * Alternatively, we can trade that extra information on read/write | |
3831 | * activity with | |
3832 | * args->busy = | |
3833 | * !reservation_object_test_signaled_rcu(obj->resv, true); | |
3834 | * to report the overall busyness. This is what the wait-ioctl does. | |
3835 | * | |
3836 | */ | |
3837 | retry: | |
3838 | seq = raw_read_seqcount(&obj->resv->seq); | |
426960be | 3839 | |
d07f0e59 CW |
3840 | /* Translate the exclusive fence to the READ *and* WRITE engine */ |
3841 | args->busy = busy_check_writer(rcu_dereference(obj->resv->fence_excl)); | |
3fdc13c7 | 3842 | |
d07f0e59 CW |
3843 | /* Translate shared fences to READ set of engines */ |
3844 | list = rcu_dereference(obj->resv->fence); | |
3845 | if (list) { | |
3846 | unsigned int shared_count = list->shared_count, i; | |
3fdc13c7 | 3847 | |
d07f0e59 CW |
3848 | for (i = 0; i < shared_count; ++i) { |
3849 | struct dma_fence *fence = | |
3850 | rcu_dereference(list->shared[i]); | |
3851 | ||
3852 | args->busy |= busy_check_reader(fence); | |
3853 | } | |
426960be | 3854 | } |
673a394b | 3855 | |
d07f0e59 CW |
3856 | if (args->busy && read_seqcount_retry(&obj->resv->seq, seq)) |
3857 | goto retry; | |
3858 | ||
3859 | err = 0; | |
fbbd37b3 CW |
3860 | out: |
3861 | rcu_read_unlock(); | |
3862 | return err; | |
673a394b EA |
3863 | } |
3864 | ||
3865 | int | |
3866 | i915_gem_throttle_ioctl(struct drm_device *dev, void *data, | |
3867 | struct drm_file *file_priv) | |
3868 | { | |
0206e353 | 3869 | return i915_gem_ring_throttle(dev, file_priv); |
673a394b EA |
3870 | } |
3871 | ||
3ef94daa CW |
3872 | int |
3873 | i915_gem_madvise_ioctl(struct drm_device *dev, void *data, | |
3874 | struct drm_file *file_priv) | |
3875 | { | |
fac5e23e | 3876 | struct drm_i915_private *dev_priv = to_i915(dev); |
3ef94daa | 3877 | struct drm_i915_gem_madvise *args = data; |
05394f39 | 3878 | struct drm_i915_gem_object *obj; |
1233e2db | 3879 | int err; |
3ef94daa CW |
3880 | |
3881 | switch (args->madv) { | |
3882 | case I915_MADV_DONTNEED: | |
3883 | case I915_MADV_WILLNEED: | |
3884 | break; | |
3885 | default: | |
3886 | return -EINVAL; | |
3887 | } | |
3888 | ||
03ac0642 | 3889 | obj = i915_gem_object_lookup(file_priv, args->handle); |
1233e2db CW |
3890 | if (!obj) |
3891 | return -ENOENT; | |
3892 | ||
3893 | err = mutex_lock_interruptible(&obj->mm.lock); | |
3894 | if (err) | |
3895 | goto out; | |
3ef94daa | 3896 | |
a4f5ea64 | 3897 | if (obj->mm.pages && |
3e510a8e | 3898 | i915_gem_object_is_tiled(obj) && |
656bfa3a | 3899 | dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES) { |
bc0629a7 CW |
3900 | if (obj->mm.madv == I915_MADV_WILLNEED) { |
3901 | GEM_BUG_ON(!obj->mm.quirked); | |
a4f5ea64 | 3902 | __i915_gem_object_unpin_pages(obj); |
bc0629a7 CW |
3903 | obj->mm.quirked = false; |
3904 | } | |
3905 | if (args->madv == I915_MADV_WILLNEED) { | |
2c3a3f44 | 3906 | GEM_BUG_ON(obj->mm.quirked); |
a4f5ea64 | 3907 | __i915_gem_object_pin_pages(obj); |
bc0629a7 CW |
3908 | obj->mm.quirked = true; |
3909 | } | |
656bfa3a DV |
3910 | } |
3911 | ||
a4f5ea64 CW |
3912 | if (obj->mm.madv != __I915_MADV_PURGED) |
3913 | obj->mm.madv = args->madv; | |
3ef94daa | 3914 | |
6c085a72 | 3915 | /* if the object is no longer attached, discard its backing storage */ |
a4f5ea64 | 3916 | if (obj->mm.madv == I915_MADV_DONTNEED && !obj->mm.pages) |
2d7ef395 CW |
3917 | i915_gem_object_truncate(obj); |
3918 | ||
a4f5ea64 | 3919 | args->retained = obj->mm.madv != __I915_MADV_PURGED; |
1233e2db | 3920 | mutex_unlock(&obj->mm.lock); |
bb6baf76 | 3921 | |
1233e2db | 3922 | out: |
f8c417cd | 3923 | i915_gem_object_put(obj); |
1233e2db | 3924 | return err; |
3ef94daa CW |
3925 | } |
3926 | ||
5b8c8aec CW |
3927 | static void |
3928 | frontbuffer_retire(struct i915_gem_active *active, | |
3929 | struct drm_i915_gem_request *request) | |
3930 | { | |
3931 | struct drm_i915_gem_object *obj = | |
3932 | container_of(active, typeof(*obj), frontbuffer_write); | |
3933 | ||
3934 | intel_fb_obj_flush(obj, true, ORIGIN_CS); | |
3935 | } | |
3936 | ||
37e680a1 CW |
3937 | void i915_gem_object_init(struct drm_i915_gem_object *obj, |
3938 | const struct drm_i915_gem_object_ops *ops) | |
0327d6ba | 3939 | { |
1233e2db CW |
3940 | mutex_init(&obj->mm.lock); |
3941 | ||
56cea323 | 3942 | INIT_LIST_HEAD(&obj->global_link); |
275f039d | 3943 | INIT_LIST_HEAD(&obj->userfault_link); |
b25cb2f8 | 3944 | INIT_LIST_HEAD(&obj->obj_exec_link); |
2f633156 | 3945 | INIT_LIST_HEAD(&obj->vma_list); |
8d9d5744 | 3946 | INIT_LIST_HEAD(&obj->batch_pool_link); |
0327d6ba | 3947 | |
37e680a1 CW |
3948 | obj->ops = ops; |
3949 | ||
d07f0e59 CW |
3950 | reservation_object_init(&obj->__builtin_resv); |
3951 | obj->resv = &obj->__builtin_resv; | |
3952 | ||
50349247 | 3953 | obj->frontbuffer_ggtt_origin = ORIGIN_GTT; |
5b8c8aec | 3954 | init_request_active(&obj->frontbuffer_write, frontbuffer_retire); |
a4f5ea64 CW |
3955 | |
3956 | obj->mm.madv = I915_MADV_WILLNEED; | |
3957 | INIT_RADIX_TREE(&obj->mm.get_page.radix, GFP_KERNEL | __GFP_NOWARN); | |
3958 | mutex_init(&obj->mm.get_page.lock); | |
0327d6ba | 3959 | |
f19ec8cb | 3960 | i915_gem_info_add_obj(to_i915(obj->base.dev), obj->base.size); |
0327d6ba CW |
3961 | } |
3962 | ||
37e680a1 | 3963 | static const struct drm_i915_gem_object_ops i915_gem_object_ops = { |
3599a91c TU |
3964 | .flags = I915_GEM_OBJECT_HAS_STRUCT_PAGE | |
3965 | I915_GEM_OBJECT_IS_SHRINKABLE, | |
37e680a1 CW |
3966 | .get_pages = i915_gem_object_get_pages_gtt, |
3967 | .put_pages = i915_gem_object_put_pages_gtt, | |
3968 | }; | |
3969 | ||
b4bcbe2a CW |
3970 | /* Note we don't consider signbits :| */ |
3971 | #define overflows_type(x, T) \ | |
3972 | (sizeof(x) > sizeof(T) && (x) >> (sizeof(T) * BITS_PER_BYTE)) | |
3973 | ||
3974 | struct drm_i915_gem_object * | |
12d79d78 | 3975 | i915_gem_object_create(struct drm_i915_private *dev_priv, u64 size) |
ac52bc56 | 3976 | { |
c397b908 | 3977 | struct drm_i915_gem_object *obj; |
5949eac4 | 3978 | struct address_space *mapping; |
1a240d4d | 3979 | gfp_t mask; |
fe3db79b | 3980 | int ret; |
ac52bc56 | 3981 | |
b4bcbe2a CW |
3982 | /* There is a prevalence of the assumption that we fit the object's |
3983 | * page count inside a 32bit _signed_ variable. Let's document this and | |
3984 | * catch if we ever need to fix it. In the meantime, if you do spot | |
3985 | * such a local variable, please consider fixing! | |
3986 | */ | |
3987 | if (WARN_ON(size >> PAGE_SHIFT > INT_MAX)) | |
3988 | return ERR_PTR(-E2BIG); | |
3989 | ||
3990 | if (overflows_type(size, obj->base.size)) | |
3991 | return ERR_PTR(-E2BIG); | |
3992 | ||
187685cb | 3993 | obj = i915_gem_object_alloc(dev_priv); |
c397b908 | 3994 | if (obj == NULL) |
fe3db79b | 3995 | return ERR_PTR(-ENOMEM); |
673a394b | 3996 | |
12d79d78 | 3997 | ret = drm_gem_object_init(&dev_priv->drm, &obj->base, size); |
fe3db79b CW |
3998 | if (ret) |
3999 | goto fail; | |
673a394b | 4000 | |
bed1ea95 | 4001 | mask = GFP_HIGHUSER | __GFP_RECLAIMABLE; |
a26e5239 | 4002 | if (IS_CRESTLINE(dev_priv) || IS_BROADWATER(dev_priv)) { |
bed1ea95 CW |
4003 | /* 965gm cannot relocate objects above 4GiB. */ |
4004 | mask &= ~__GFP_HIGHMEM; | |
4005 | mask |= __GFP_DMA32; | |
4006 | } | |
4007 | ||
93c76a3d | 4008 | mapping = obj->base.filp->f_mapping; |
bed1ea95 | 4009 | mapping_set_gfp_mask(mapping, mask); |
5949eac4 | 4010 | |
37e680a1 | 4011 | i915_gem_object_init(obj, &i915_gem_object_ops); |
73aa808f | 4012 | |
c397b908 DV |
4013 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; |
4014 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; | |
673a394b | 4015 | |
0031fb96 | 4016 | if (HAS_LLC(dev_priv)) { |
3d29b842 | 4017 | /* On some devices, we can have the GPU use the LLC (the CPU |
a1871112 EA |
4018 | * cache) for about a 10% performance improvement |
4019 | * compared to uncached. Graphics requests other than | |
4020 | * display scanout are coherent with the CPU in | |
4021 | * accessing this cache. This means in this mode we | |
4022 | * don't need to clflush on the CPU side, and on the | |
4023 | * GPU side we only need to flush internal caches to | |
4024 | * get data visible to the CPU. | |
4025 | * | |
4026 | * However, we maintain the display planes as UC, and so | |
4027 | * need to rebind when first used as such. | |
4028 | */ | |
4029 | obj->cache_level = I915_CACHE_LLC; | |
4030 | } else | |
4031 | obj->cache_level = I915_CACHE_NONE; | |
4032 | ||
d861e338 DV |
4033 | trace_i915_gem_object_create(obj); |
4034 | ||
05394f39 | 4035 | return obj; |
fe3db79b CW |
4036 | |
4037 | fail: | |
4038 | i915_gem_object_free(obj); | |
fe3db79b | 4039 | return ERR_PTR(ret); |
c397b908 DV |
4040 | } |
4041 | ||
340fbd8c CW |
4042 | static bool discard_backing_storage(struct drm_i915_gem_object *obj) |
4043 | { | |
4044 | /* If we are the last user of the backing storage (be it shmemfs | |
4045 | * pages or stolen etc), we know that the pages are going to be | |
4046 | * immediately released. In this case, we can then skip copying | |
4047 | * back the contents from the GPU. | |
4048 | */ | |
4049 | ||
a4f5ea64 | 4050 | if (obj->mm.madv != I915_MADV_WILLNEED) |
340fbd8c CW |
4051 | return false; |
4052 | ||
4053 | if (obj->base.filp == NULL) | |
4054 | return true; | |
4055 | ||
4056 | /* At first glance, this looks racy, but then again so would be | |
4057 | * userspace racing mmap against close. However, the first external | |
4058 | * reference to the filp can only be obtained through the | |
4059 | * i915_gem_mmap_ioctl() which safeguards us against the user | |
4060 | * acquiring such a reference whilst we are in the middle of | |
4061 | * freeing the object. | |
4062 | */ | |
4063 | return atomic_long_read(&obj->base.filp->f_count) == 1; | |
4064 | } | |
4065 | ||
fbbd37b3 CW |
4066 | static void __i915_gem_free_objects(struct drm_i915_private *i915, |
4067 | struct llist_node *freed) | |
673a394b | 4068 | { |
fbbd37b3 | 4069 | struct drm_i915_gem_object *obj, *on; |
673a394b | 4070 | |
fbbd37b3 CW |
4071 | mutex_lock(&i915->drm.struct_mutex); |
4072 | intel_runtime_pm_get(i915); | |
4073 | llist_for_each_entry(obj, freed, freed) { | |
4074 | struct i915_vma *vma, *vn; | |
4075 | ||
4076 | trace_i915_gem_object_destroy(obj); | |
4077 | ||
4078 | GEM_BUG_ON(i915_gem_object_is_active(obj)); | |
4079 | list_for_each_entry_safe(vma, vn, | |
4080 | &obj->vma_list, obj_link) { | |
4081 | GEM_BUG_ON(!i915_vma_is_ggtt(vma)); | |
4082 | GEM_BUG_ON(i915_vma_is_active(vma)); | |
4083 | vma->flags &= ~I915_VMA_PIN_MASK; | |
4084 | i915_vma_close(vma); | |
4085 | } | |
db6c2b41 CW |
4086 | GEM_BUG_ON(!list_empty(&obj->vma_list)); |
4087 | GEM_BUG_ON(!RB_EMPTY_ROOT(&obj->vma_tree)); | |
fbbd37b3 | 4088 | |
56cea323 | 4089 | list_del(&obj->global_link); |
fbbd37b3 CW |
4090 | } |
4091 | intel_runtime_pm_put(i915); | |
4092 | mutex_unlock(&i915->drm.struct_mutex); | |
4093 | ||
4094 | llist_for_each_entry_safe(obj, on, freed, freed) { | |
4095 | GEM_BUG_ON(obj->bind_count); | |
4096 | GEM_BUG_ON(atomic_read(&obj->frontbuffer_bits)); | |
4097 | ||
4098 | if (obj->ops->release) | |
4099 | obj->ops->release(obj); | |
f65c9168 | 4100 | |
fbbd37b3 CW |
4101 | if (WARN_ON(i915_gem_object_has_pinned_pages(obj))) |
4102 | atomic_set(&obj->mm.pages_pin_count, 0); | |
548625ee | 4103 | __i915_gem_object_put_pages(obj, I915_MM_NORMAL); |
fbbd37b3 CW |
4104 | GEM_BUG_ON(obj->mm.pages); |
4105 | ||
4106 | if (obj->base.import_attach) | |
4107 | drm_prime_gem_destroy(&obj->base, NULL); | |
4108 | ||
d07f0e59 | 4109 | reservation_object_fini(&obj->__builtin_resv); |
fbbd37b3 CW |
4110 | drm_gem_object_release(&obj->base); |
4111 | i915_gem_info_remove_obj(i915, obj->base.size); | |
4112 | ||
4113 | kfree(obj->bit_17); | |
4114 | i915_gem_object_free(obj); | |
4115 | } | |
4116 | } | |
4117 | ||
4118 | static void i915_gem_flush_free_objects(struct drm_i915_private *i915) | |
4119 | { | |
4120 | struct llist_node *freed; | |
4121 | ||
4122 | freed = llist_del_all(&i915->mm.free_list); | |
4123 | if (unlikely(freed)) | |
4124 | __i915_gem_free_objects(i915, freed); | |
4125 | } | |
4126 | ||
4127 | static void __i915_gem_free_work(struct work_struct *work) | |
4128 | { | |
4129 | struct drm_i915_private *i915 = | |
4130 | container_of(work, struct drm_i915_private, mm.free_work); | |
4131 | struct llist_node *freed; | |
26e12f89 | 4132 | |
b1f788c6 CW |
4133 | /* All file-owned VMA should have been released by this point through |
4134 | * i915_gem_close_object(), or earlier by i915_gem_context_close(). | |
4135 | * However, the object may also be bound into the global GTT (e.g. | |
4136 | * older GPUs without per-process support, or for direct access through | |
4137 | * the GTT either for the user or for scanout). Those VMA still need to | |
4138 | * unbound now. | |
4139 | */ | |
1488fc08 | 4140 | |
fbbd37b3 CW |
4141 | while ((freed = llist_del_all(&i915->mm.free_list))) |
4142 | __i915_gem_free_objects(i915, freed); | |
4143 | } | |
a071fa00 | 4144 | |
fbbd37b3 CW |
4145 | static void __i915_gem_free_object_rcu(struct rcu_head *head) |
4146 | { | |
4147 | struct drm_i915_gem_object *obj = | |
4148 | container_of(head, typeof(*obj), rcu); | |
4149 | struct drm_i915_private *i915 = to_i915(obj->base.dev); | |
4150 | ||
4151 | /* We can't simply use call_rcu() from i915_gem_free_object() | |
4152 | * as we need to block whilst unbinding, and the call_rcu | |
4153 | * task may be called from softirq context. So we take a | |
4154 | * detour through a worker. | |
4155 | */ | |
4156 | if (llist_add(&obj->freed, &i915->mm.free_list)) | |
4157 | schedule_work(&i915->mm.free_work); | |
4158 | } | |
656bfa3a | 4159 | |
fbbd37b3 CW |
4160 | void i915_gem_free_object(struct drm_gem_object *gem_obj) |
4161 | { | |
4162 | struct drm_i915_gem_object *obj = to_intel_bo(gem_obj); | |
a4f5ea64 | 4163 | |
bc0629a7 CW |
4164 | if (obj->mm.quirked) |
4165 | __i915_gem_object_unpin_pages(obj); | |
4166 | ||
340fbd8c | 4167 | if (discard_backing_storage(obj)) |
a4f5ea64 | 4168 | obj->mm.madv = I915_MADV_DONTNEED; |
de151cf6 | 4169 | |
fbbd37b3 CW |
4170 | /* Before we free the object, make sure any pure RCU-only |
4171 | * read-side critical sections are complete, e.g. | |
4172 | * i915_gem_busy_ioctl(). For the corresponding synchronized | |
4173 | * lookup see i915_gem_object_lookup_rcu(). | |
4174 | */ | |
4175 | call_rcu(&obj->rcu, __i915_gem_free_object_rcu); | |
673a394b EA |
4176 | } |
4177 | ||
f8a7fde4 CW |
4178 | void __i915_gem_object_release_unless_active(struct drm_i915_gem_object *obj) |
4179 | { | |
4180 | lockdep_assert_held(&obj->base.dev->struct_mutex); | |
4181 | ||
4182 | GEM_BUG_ON(i915_gem_object_has_active_reference(obj)); | |
4183 | if (i915_gem_object_is_active(obj)) | |
4184 | i915_gem_object_set_active_reference(obj); | |
4185 | else | |
4186 | i915_gem_object_put(obj); | |
4187 | } | |
4188 | ||
3033acab CW |
4189 | static void assert_kernel_context_is_current(struct drm_i915_private *dev_priv) |
4190 | { | |
4191 | struct intel_engine_cs *engine; | |
4192 | enum intel_engine_id id; | |
4193 | ||
4194 | for_each_engine(engine, dev_priv, id) | |
4195 | GEM_BUG_ON(engine->last_context != dev_priv->kernel_context); | |
4196 | } | |
4197 | ||
bf9e8429 | 4198 | int i915_gem_suspend(struct drm_i915_private *dev_priv) |
29105ccc | 4199 | { |
bf9e8429 | 4200 | struct drm_device *dev = &dev_priv->drm; |
dcff85c8 | 4201 | int ret; |
28dfe52a | 4202 | |
54b4f68f CW |
4203 | intel_suspend_gt_powersave(dev_priv); |
4204 | ||
45c5f202 | 4205 | mutex_lock(&dev->struct_mutex); |
5ab57c70 CW |
4206 | |
4207 | /* We have to flush all the executing contexts to main memory so | |
4208 | * that they can saved in the hibernation image. To ensure the last | |
4209 | * context image is coherent, we have to switch away from it. That | |
4210 | * leaves the dev_priv->kernel_context still active when | |
4211 | * we actually suspend, and its image in memory may not match the GPU | |
4212 | * state. Fortunately, the kernel_context is disposable and we do | |
4213 | * not rely on its state. | |
4214 | */ | |
4215 | ret = i915_gem_switch_to_kernel_context(dev_priv); | |
4216 | if (ret) | |
4217 | goto err; | |
4218 | ||
22dd3bb9 CW |
4219 | ret = i915_gem_wait_for_idle(dev_priv, |
4220 | I915_WAIT_INTERRUPTIBLE | | |
4221 | I915_WAIT_LOCKED); | |
f7403347 | 4222 | if (ret) |
45c5f202 | 4223 | goto err; |
f7403347 | 4224 | |
c033666a | 4225 | i915_gem_retire_requests(dev_priv); |
28176ef4 | 4226 | GEM_BUG_ON(dev_priv->gt.active_requests); |
673a394b | 4227 | |
3033acab | 4228 | assert_kernel_context_is_current(dev_priv); |
b2e862d0 | 4229 | i915_gem_context_lost(dev_priv); |
45c5f202 CW |
4230 | mutex_unlock(&dev->struct_mutex); |
4231 | ||
737b1506 | 4232 | cancel_delayed_work_sync(&dev_priv->gpu_error.hangcheck_work); |
67d97da3 CW |
4233 | cancel_delayed_work_sync(&dev_priv->gt.retire_work); |
4234 | flush_delayed_work(&dev_priv->gt.idle_work); | |
fbbd37b3 | 4235 | flush_work(&dev_priv->mm.free_work); |
29105ccc | 4236 | |
bdcf120b CW |
4237 | /* Assert that we sucessfully flushed all the work and |
4238 | * reset the GPU back to its idle, low power state. | |
4239 | */ | |
67d97da3 | 4240 | WARN_ON(dev_priv->gt.awake); |
31ab49ab | 4241 | WARN_ON(!intel_execlists_idle(dev_priv)); |
bdcf120b | 4242 | |
1c777c5d ID |
4243 | /* |
4244 | * Neither the BIOS, ourselves or any other kernel | |
4245 | * expects the system to be in execlists mode on startup, | |
4246 | * so we need to reset the GPU back to legacy mode. And the only | |
4247 | * known way to disable logical contexts is through a GPU reset. | |
4248 | * | |
4249 | * So in order to leave the system in a known default configuration, | |
4250 | * always reset the GPU upon unload and suspend. Afterwards we then | |
4251 | * clean up the GEM state tracking, flushing off the requests and | |
4252 | * leaving the system in a known idle state. | |
4253 | * | |
4254 | * Note that is of the upmost importance that the GPU is idle and | |
4255 | * all stray writes are flushed *before* we dismantle the backing | |
4256 | * storage for the pinned objects. | |
4257 | * | |
4258 | * However, since we are uncertain that resetting the GPU on older | |
4259 | * machines is a good idea, we don't - just in case it leaves the | |
4260 | * machine in an unusable condition. | |
4261 | */ | |
0031fb96 | 4262 | if (HAS_HW_CONTEXTS(dev_priv)) { |
1c777c5d ID |
4263 | int reset = intel_gpu_reset(dev_priv, ALL_ENGINES); |
4264 | WARN_ON(reset && reset != -ENODEV); | |
4265 | } | |
4266 | ||
673a394b | 4267 | return 0; |
45c5f202 CW |
4268 | |
4269 | err: | |
4270 | mutex_unlock(&dev->struct_mutex); | |
4271 | return ret; | |
673a394b EA |
4272 | } |
4273 | ||
bf9e8429 | 4274 | void i915_gem_resume(struct drm_i915_private *dev_priv) |
5ab57c70 | 4275 | { |
bf9e8429 | 4276 | struct drm_device *dev = &dev_priv->drm; |
5ab57c70 | 4277 | |
31ab49ab ID |
4278 | WARN_ON(dev_priv->gt.awake); |
4279 | ||
5ab57c70 | 4280 | mutex_lock(&dev->struct_mutex); |
275a991c | 4281 | i915_gem_restore_gtt_mappings(dev_priv); |
5ab57c70 CW |
4282 | |
4283 | /* As we didn't flush the kernel context before suspend, we cannot | |
4284 | * guarantee that the context image is complete. So let's just reset | |
4285 | * it and start again. | |
4286 | */ | |
821ed7df | 4287 | dev_priv->gt.resume(dev_priv); |
5ab57c70 CW |
4288 | |
4289 | mutex_unlock(&dev->struct_mutex); | |
4290 | } | |
4291 | ||
c6be607a | 4292 | void i915_gem_init_swizzling(struct drm_i915_private *dev_priv) |
f691e2f4 | 4293 | { |
c6be607a | 4294 | if (INTEL_GEN(dev_priv) < 5 || |
f691e2f4 DV |
4295 | dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE) |
4296 | return; | |
4297 | ||
4298 | I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) | | |
4299 | DISP_TILE_SURFACE_SWIZZLING); | |
4300 | ||
5db94019 | 4301 | if (IS_GEN5(dev_priv)) |
11782b02 DV |
4302 | return; |
4303 | ||
f691e2f4 | 4304 | I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_SWZCTL); |
5db94019 | 4305 | if (IS_GEN6(dev_priv)) |
6b26c86d | 4306 | I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB)); |
5db94019 | 4307 | else if (IS_GEN7(dev_priv)) |
6b26c86d | 4308 | I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB)); |
5db94019 | 4309 | else if (IS_GEN8(dev_priv)) |
31a5336e | 4310 | I915_WRITE(GAMTARBMODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_BDW)); |
8782e26c BW |
4311 | else |
4312 | BUG(); | |
f691e2f4 | 4313 | } |
e21af88d | 4314 | |
50a0bc90 | 4315 | static void init_unused_ring(struct drm_i915_private *dev_priv, u32 base) |
81e7f200 | 4316 | { |
81e7f200 VS |
4317 | I915_WRITE(RING_CTL(base), 0); |
4318 | I915_WRITE(RING_HEAD(base), 0); | |
4319 | I915_WRITE(RING_TAIL(base), 0); | |
4320 | I915_WRITE(RING_START(base), 0); | |
4321 | } | |
4322 | ||
50a0bc90 | 4323 | static void init_unused_rings(struct drm_i915_private *dev_priv) |
81e7f200 | 4324 | { |
50a0bc90 TU |
4325 | if (IS_I830(dev_priv)) { |
4326 | init_unused_ring(dev_priv, PRB1_BASE); | |
4327 | init_unused_ring(dev_priv, SRB0_BASE); | |
4328 | init_unused_ring(dev_priv, SRB1_BASE); | |
4329 | init_unused_ring(dev_priv, SRB2_BASE); | |
4330 | init_unused_ring(dev_priv, SRB3_BASE); | |
4331 | } else if (IS_GEN2(dev_priv)) { | |
4332 | init_unused_ring(dev_priv, SRB0_BASE); | |
4333 | init_unused_ring(dev_priv, SRB1_BASE); | |
4334 | } else if (IS_GEN3(dev_priv)) { | |
4335 | init_unused_ring(dev_priv, PRB1_BASE); | |
4336 | init_unused_ring(dev_priv, PRB2_BASE); | |
81e7f200 VS |
4337 | } |
4338 | } | |
4339 | ||
4fc7c971 | 4340 | int |
bf9e8429 | 4341 | i915_gem_init_hw(struct drm_i915_private *dev_priv) |
4fc7c971 | 4342 | { |
e2f80391 | 4343 | struct intel_engine_cs *engine; |
3b3f1650 | 4344 | enum intel_engine_id id; |
d200cda6 | 4345 | int ret; |
4fc7c971 | 4346 | |
de867c20 CW |
4347 | dev_priv->gt.last_init_time = ktime_get(); |
4348 | ||
5e4f5189 CW |
4349 | /* Double layer security blanket, see i915_gem_init() */ |
4350 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); | |
4351 | ||
0031fb96 | 4352 | if (HAS_EDRAM(dev_priv) && INTEL_GEN(dev_priv) < 9) |
05e21cc4 | 4353 | I915_WRITE(HSW_IDICR, I915_READ(HSW_IDICR) | IDIHASHMSK(0xf)); |
4fc7c971 | 4354 | |
772c2a51 | 4355 | if (IS_HASWELL(dev_priv)) |
50a0bc90 | 4356 | I915_WRITE(MI_PREDICATE_RESULT_2, IS_HSW_GT3(dev_priv) ? |
0bf21347 | 4357 | LOWER_SLICE_ENABLED : LOWER_SLICE_DISABLED); |
9435373e | 4358 | |
6e266956 | 4359 | if (HAS_PCH_NOP(dev_priv)) { |
fd6b8f43 | 4360 | if (IS_IVYBRIDGE(dev_priv)) { |
6ba844b0 DV |
4361 | u32 temp = I915_READ(GEN7_MSG_CTL); |
4362 | temp &= ~(WAIT_FOR_PCH_FLR_ACK | WAIT_FOR_PCH_RESET_ACK); | |
4363 | I915_WRITE(GEN7_MSG_CTL, temp); | |
c6be607a | 4364 | } else if (INTEL_GEN(dev_priv) >= 7) { |
6ba844b0 DV |
4365 | u32 temp = I915_READ(HSW_NDE_RSTWRN_OPT); |
4366 | temp &= ~RESET_PCH_HANDSHAKE_ENABLE; | |
4367 | I915_WRITE(HSW_NDE_RSTWRN_OPT, temp); | |
4368 | } | |
88a2b2a3 BW |
4369 | } |
4370 | ||
c6be607a | 4371 | i915_gem_init_swizzling(dev_priv); |
4fc7c971 | 4372 | |
d5abdfda DV |
4373 | /* |
4374 | * At least 830 can leave some of the unused rings | |
4375 | * "active" (ie. head != tail) after resume which | |
4376 | * will prevent c3 entry. Makes sure all unused rings | |
4377 | * are totally idle. | |
4378 | */ | |
50a0bc90 | 4379 | init_unused_rings(dev_priv); |
d5abdfda | 4380 | |
ed54c1a1 | 4381 | BUG_ON(!dev_priv->kernel_context); |
90638cc1 | 4382 | |
c6be607a | 4383 | ret = i915_ppgtt_init_hw(dev_priv); |
4ad2fd88 JH |
4384 | if (ret) { |
4385 | DRM_ERROR("PPGTT enable HW failed %d\n", ret); | |
4386 | goto out; | |
4387 | } | |
4388 | ||
4389 | /* Need to do basic initialisation of all rings first: */ | |
3b3f1650 | 4390 | for_each_engine(engine, dev_priv, id) { |
e2f80391 | 4391 | ret = engine->init_hw(engine); |
35a57ffb | 4392 | if (ret) |
5e4f5189 | 4393 | goto out; |
35a57ffb | 4394 | } |
99433931 | 4395 | |
bf9e8429 | 4396 | intel_mocs_init_l3cc_table(dev_priv); |
0ccdacf6 | 4397 | |
33a732f4 | 4398 | /* We can't enable contexts until all firmware is loaded */ |
bf9e8429 | 4399 | ret = intel_guc_setup(dev_priv); |
e556f7c1 DG |
4400 | if (ret) |
4401 | goto out; | |
33a732f4 | 4402 | |
5e4f5189 CW |
4403 | out: |
4404 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); | |
2fa48d8d | 4405 | return ret; |
8187a2b7 ZN |
4406 | } |
4407 | ||
39df9190 CW |
4408 | bool intel_sanitize_semaphores(struct drm_i915_private *dev_priv, int value) |
4409 | { | |
4410 | if (INTEL_INFO(dev_priv)->gen < 6) | |
4411 | return false; | |
4412 | ||
4413 | /* TODO: make semaphores and Execlists play nicely together */ | |
4414 | if (i915.enable_execlists) | |
4415 | return false; | |
4416 | ||
4417 | if (value >= 0) | |
4418 | return value; | |
4419 | ||
4420 | #ifdef CONFIG_INTEL_IOMMU | |
4421 | /* Enable semaphores on SNB when IO remapping is off */ | |
4422 | if (INTEL_INFO(dev_priv)->gen == 6 && intel_iommu_gfx_mapped) | |
4423 | return false; | |
4424 | #endif | |
4425 | ||
4426 | return true; | |
4427 | } | |
4428 | ||
bf9e8429 | 4429 | int i915_gem_init(struct drm_i915_private *dev_priv) |
1070a42b | 4430 | { |
1070a42b CW |
4431 | int ret; |
4432 | ||
bf9e8429 | 4433 | mutex_lock(&dev_priv->drm.struct_mutex); |
d62b4892 | 4434 | |
a83014d3 | 4435 | if (!i915.enable_execlists) { |
821ed7df | 4436 | dev_priv->gt.resume = intel_legacy_submission_resume; |
7e37f889 | 4437 | dev_priv->gt.cleanup_engine = intel_engine_cleanup; |
454afebd | 4438 | } else { |
821ed7df | 4439 | dev_priv->gt.resume = intel_lr_context_resume; |
117897f4 | 4440 | dev_priv->gt.cleanup_engine = intel_logical_ring_cleanup; |
a83014d3 OM |
4441 | } |
4442 | ||
5e4f5189 CW |
4443 | /* This is just a security blanket to placate dragons. |
4444 | * On some systems, we very sporadically observe that the first TLBs | |
4445 | * used by the CS may be stale, despite us poking the TLB reset. If | |
4446 | * we hold the forcewake during initialisation these problems | |
4447 | * just magically go away. | |
4448 | */ | |
4449 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); | |
4450 | ||
72778cb2 | 4451 | i915_gem_init_userptr(dev_priv); |
f6b9d5ca CW |
4452 | |
4453 | ret = i915_gem_init_ggtt(dev_priv); | |
4454 | if (ret) | |
4455 | goto out_unlock; | |
d62b4892 | 4456 | |
bf9e8429 | 4457 | ret = i915_gem_context_init(dev_priv); |
7bcc3777 JN |
4458 | if (ret) |
4459 | goto out_unlock; | |
2fa48d8d | 4460 | |
bf9e8429 | 4461 | ret = intel_engines_init(dev_priv); |
35a57ffb | 4462 | if (ret) |
7bcc3777 | 4463 | goto out_unlock; |
2fa48d8d | 4464 | |
bf9e8429 | 4465 | ret = i915_gem_init_hw(dev_priv); |
60990320 | 4466 | if (ret == -EIO) { |
7e21d648 | 4467 | /* Allow engine initialisation to fail by marking the GPU as |
60990320 CW |
4468 | * wedged. But we only want to do this where the GPU is angry, |
4469 | * for all other failure, such as an allocation failure, bail. | |
4470 | */ | |
4471 | DRM_ERROR("Failed to initialize GPU, declaring it wedged\n"); | |
821ed7df | 4472 | i915_gem_set_wedged(dev_priv); |
60990320 | 4473 | ret = 0; |
1070a42b | 4474 | } |
7bcc3777 JN |
4475 | |
4476 | out_unlock: | |
5e4f5189 | 4477 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); |
bf9e8429 | 4478 | mutex_unlock(&dev_priv->drm.struct_mutex); |
1070a42b | 4479 | |
60990320 | 4480 | return ret; |
1070a42b CW |
4481 | } |
4482 | ||
8187a2b7 | 4483 | void |
cb15d9f8 | 4484 | i915_gem_cleanup_engines(struct drm_i915_private *dev_priv) |
8187a2b7 | 4485 | { |
e2f80391 | 4486 | struct intel_engine_cs *engine; |
3b3f1650 | 4487 | enum intel_engine_id id; |
8187a2b7 | 4488 | |
3b3f1650 | 4489 | for_each_engine(engine, dev_priv, id) |
117897f4 | 4490 | dev_priv->gt.cleanup_engine(engine); |
8187a2b7 ZN |
4491 | } |
4492 | ||
40ae4e16 ID |
4493 | void |
4494 | i915_gem_load_init_fences(struct drm_i915_private *dev_priv) | |
4495 | { | |
49ef5294 | 4496 | int i; |
40ae4e16 ID |
4497 | |
4498 | if (INTEL_INFO(dev_priv)->gen >= 7 && !IS_VALLEYVIEW(dev_priv) && | |
4499 | !IS_CHERRYVIEW(dev_priv)) | |
4500 | dev_priv->num_fence_regs = 32; | |
4501 | else if (INTEL_INFO(dev_priv)->gen >= 4 || IS_I945G(dev_priv) || | |
4502 | IS_I945GM(dev_priv) || IS_G33(dev_priv)) | |
4503 | dev_priv->num_fence_regs = 16; | |
4504 | else | |
4505 | dev_priv->num_fence_regs = 8; | |
4506 | ||
c033666a | 4507 | if (intel_vgpu_active(dev_priv)) |
40ae4e16 ID |
4508 | dev_priv->num_fence_regs = |
4509 | I915_READ(vgtif_reg(avail_rs.fence_num)); | |
4510 | ||
4511 | /* Initialize fence registers to zero */ | |
49ef5294 CW |
4512 | for (i = 0; i < dev_priv->num_fence_regs; i++) { |
4513 | struct drm_i915_fence_reg *fence = &dev_priv->fence_regs[i]; | |
4514 | ||
4515 | fence->i915 = dev_priv; | |
4516 | fence->id = i; | |
4517 | list_add_tail(&fence->link, &dev_priv->mm.fence_list); | |
4518 | } | |
4362f4f6 | 4519 | i915_gem_restore_fences(dev_priv); |
40ae4e16 | 4520 | |
4362f4f6 | 4521 | i915_gem_detect_bit_6_swizzle(dev_priv); |
40ae4e16 ID |
4522 | } |
4523 | ||
73cb9701 | 4524 | int |
cb15d9f8 | 4525 | i915_gem_load_init(struct drm_i915_private *dev_priv) |
673a394b | 4526 | { |
a933568e | 4527 | int err = -ENOMEM; |
42dcedd4 | 4528 | |
a933568e TU |
4529 | dev_priv->objects = KMEM_CACHE(drm_i915_gem_object, SLAB_HWCACHE_ALIGN); |
4530 | if (!dev_priv->objects) | |
73cb9701 | 4531 | goto err_out; |
73cb9701 | 4532 | |
a933568e TU |
4533 | dev_priv->vmas = KMEM_CACHE(i915_vma, SLAB_HWCACHE_ALIGN); |
4534 | if (!dev_priv->vmas) | |
73cb9701 | 4535 | goto err_objects; |
73cb9701 | 4536 | |
a933568e TU |
4537 | dev_priv->requests = KMEM_CACHE(drm_i915_gem_request, |
4538 | SLAB_HWCACHE_ALIGN | | |
4539 | SLAB_RECLAIM_ACCOUNT | | |
4540 | SLAB_DESTROY_BY_RCU); | |
4541 | if (!dev_priv->requests) | |
73cb9701 | 4542 | goto err_vmas; |
73cb9701 | 4543 | |
52e54209 CW |
4544 | dev_priv->dependencies = KMEM_CACHE(i915_dependency, |
4545 | SLAB_HWCACHE_ALIGN | | |
4546 | SLAB_RECLAIM_ACCOUNT); | |
4547 | if (!dev_priv->dependencies) | |
4548 | goto err_requests; | |
4549 | ||
73cb9701 CW |
4550 | mutex_lock(&dev_priv->drm.struct_mutex); |
4551 | INIT_LIST_HEAD(&dev_priv->gt.timelines); | |
bb89485e | 4552 | err = i915_gem_timeline_init__global(dev_priv); |
73cb9701 CW |
4553 | mutex_unlock(&dev_priv->drm.struct_mutex); |
4554 | if (err) | |
52e54209 | 4555 | goto err_dependencies; |
673a394b | 4556 | |
a33afea5 | 4557 | INIT_LIST_HEAD(&dev_priv->context_list); |
fbbd37b3 CW |
4558 | INIT_WORK(&dev_priv->mm.free_work, __i915_gem_free_work); |
4559 | init_llist_head(&dev_priv->mm.free_list); | |
6c085a72 CW |
4560 | INIT_LIST_HEAD(&dev_priv->mm.unbound_list); |
4561 | INIT_LIST_HEAD(&dev_priv->mm.bound_list); | |
a09ba7fa | 4562 | INIT_LIST_HEAD(&dev_priv->mm.fence_list); |
275f039d | 4563 | INIT_LIST_HEAD(&dev_priv->mm.userfault_list); |
67d97da3 | 4564 | INIT_DELAYED_WORK(&dev_priv->gt.retire_work, |
673a394b | 4565 | i915_gem_retire_work_handler); |
67d97da3 | 4566 | INIT_DELAYED_WORK(&dev_priv->gt.idle_work, |
b29c19b6 | 4567 | i915_gem_idle_work_handler); |
1f15b76f | 4568 | init_waitqueue_head(&dev_priv->gpu_error.wait_queue); |
1f83fee0 | 4569 | init_waitqueue_head(&dev_priv->gpu_error.reset_queue); |
31169714 | 4570 | |
72bfa19c CW |
4571 | dev_priv->relative_constants_mode = I915_EXEC_CONSTANTS_REL_GENERAL; |
4572 | ||
6b95a207 | 4573 | init_waitqueue_head(&dev_priv->pending_flip_queue); |
17250b71 | 4574 | |
ce453d81 CW |
4575 | dev_priv->mm.interruptible = true; |
4576 | ||
6f633402 JL |
4577 | atomic_set(&dev_priv->mm.bsd_engine_dispatch_index, 0); |
4578 | ||
b5add959 | 4579 | spin_lock_init(&dev_priv->fb_tracking.lock); |
73cb9701 CW |
4580 | |
4581 | return 0; | |
4582 | ||
52e54209 CW |
4583 | err_dependencies: |
4584 | kmem_cache_destroy(dev_priv->dependencies); | |
73cb9701 CW |
4585 | err_requests: |
4586 | kmem_cache_destroy(dev_priv->requests); | |
4587 | err_vmas: | |
4588 | kmem_cache_destroy(dev_priv->vmas); | |
4589 | err_objects: | |
4590 | kmem_cache_destroy(dev_priv->objects); | |
4591 | err_out: | |
4592 | return err; | |
673a394b | 4593 | } |
71acb5eb | 4594 | |
cb15d9f8 | 4595 | void i915_gem_load_cleanup(struct drm_i915_private *dev_priv) |
d64aa096 | 4596 | { |
7d5d59e5 CW |
4597 | WARN_ON(!llist_empty(&dev_priv->mm.free_list)); |
4598 | ||
ea84aa77 MA |
4599 | mutex_lock(&dev_priv->drm.struct_mutex); |
4600 | i915_gem_timeline_fini(&dev_priv->gt.global_timeline); | |
4601 | WARN_ON(!list_empty(&dev_priv->gt.timelines)); | |
4602 | mutex_unlock(&dev_priv->drm.struct_mutex); | |
4603 | ||
52e54209 | 4604 | kmem_cache_destroy(dev_priv->dependencies); |
d64aa096 ID |
4605 | kmem_cache_destroy(dev_priv->requests); |
4606 | kmem_cache_destroy(dev_priv->vmas); | |
4607 | kmem_cache_destroy(dev_priv->objects); | |
0eafec6d CW |
4608 | |
4609 | /* And ensure that our DESTROY_BY_RCU slabs are truly destroyed */ | |
4610 | rcu_barrier(); | |
d64aa096 ID |
4611 | } |
4612 | ||
6a800eab CW |
4613 | int i915_gem_freeze(struct drm_i915_private *dev_priv) |
4614 | { | |
4615 | intel_runtime_pm_get(dev_priv); | |
4616 | ||
4617 | mutex_lock(&dev_priv->drm.struct_mutex); | |
4618 | i915_gem_shrink_all(dev_priv); | |
4619 | mutex_unlock(&dev_priv->drm.struct_mutex); | |
4620 | ||
4621 | intel_runtime_pm_put(dev_priv); | |
4622 | ||
4623 | return 0; | |
4624 | } | |
4625 | ||
461fb99c CW |
4626 | int i915_gem_freeze_late(struct drm_i915_private *dev_priv) |
4627 | { | |
4628 | struct drm_i915_gem_object *obj; | |
7aab2d53 CW |
4629 | struct list_head *phases[] = { |
4630 | &dev_priv->mm.unbound_list, | |
4631 | &dev_priv->mm.bound_list, | |
4632 | NULL | |
4633 | }, **p; | |
461fb99c CW |
4634 | |
4635 | /* Called just before we write the hibernation image. | |
4636 | * | |
4637 | * We need to update the domain tracking to reflect that the CPU | |
4638 | * will be accessing all the pages to create and restore from the | |
4639 | * hibernation, and so upon restoration those pages will be in the | |
4640 | * CPU domain. | |
4641 | * | |
4642 | * To make sure the hibernation image contains the latest state, | |
4643 | * we update that state just before writing out the image. | |
7aab2d53 CW |
4644 | * |
4645 | * To try and reduce the hibernation image, we manually shrink | |
4646 | * the objects as well. | |
461fb99c CW |
4647 | */ |
4648 | ||
6a800eab CW |
4649 | mutex_lock(&dev_priv->drm.struct_mutex); |
4650 | i915_gem_shrink(dev_priv, -1UL, I915_SHRINK_UNBOUND); | |
461fb99c | 4651 | |
7aab2d53 | 4652 | for (p = phases; *p; p++) { |
56cea323 | 4653 | list_for_each_entry(obj, *p, global_link) { |
7aab2d53 CW |
4654 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; |
4655 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; | |
4656 | } | |
461fb99c | 4657 | } |
6a800eab | 4658 | mutex_unlock(&dev_priv->drm.struct_mutex); |
461fb99c CW |
4659 | |
4660 | return 0; | |
4661 | } | |
4662 | ||
f787a5f5 | 4663 | void i915_gem_release(struct drm_device *dev, struct drm_file *file) |
b962442e | 4664 | { |
f787a5f5 | 4665 | struct drm_i915_file_private *file_priv = file->driver_priv; |
15f7bbc7 | 4666 | struct drm_i915_gem_request *request; |
b962442e EA |
4667 | |
4668 | /* Clean up our request list when the client is going away, so that | |
4669 | * later retire_requests won't dereference our soon-to-be-gone | |
4670 | * file_priv. | |
4671 | */ | |
1c25595f | 4672 | spin_lock(&file_priv->mm.lock); |
15f7bbc7 | 4673 | list_for_each_entry(request, &file_priv->mm.request_list, client_list) |
f787a5f5 | 4674 | request->file_priv = NULL; |
1c25595f | 4675 | spin_unlock(&file_priv->mm.lock); |
b29c19b6 | 4676 | |
2e1b8730 | 4677 | if (!list_empty(&file_priv->rps.link)) { |
8d3afd7d | 4678 | spin_lock(&to_i915(dev)->rps.client_lock); |
2e1b8730 | 4679 | list_del(&file_priv->rps.link); |
8d3afd7d | 4680 | spin_unlock(&to_i915(dev)->rps.client_lock); |
1854d5ca | 4681 | } |
b29c19b6 CW |
4682 | } |
4683 | ||
4684 | int i915_gem_open(struct drm_device *dev, struct drm_file *file) | |
4685 | { | |
4686 | struct drm_i915_file_private *file_priv; | |
e422b888 | 4687 | int ret; |
b29c19b6 | 4688 | |
c4c29d7b | 4689 | DRM_DEBUG("\n"); |
b29c19b6 CW |
4690 | |
4691 | file_priv = kzalloc(sizeof(*file_priv), GFP_KERNEL); | |
4692 | if (!file_priv) | |
4693 | return -ENOMEM; | |
4694 | ||
4695 | file->driver_priv = file_priv; | |
f19ec8cb | 4696 | file_priv->dev_priv = to_i915(dev); |
ab0e7ff9 | 4697 | file_priv->file = file; |
2e1b8730 | 4698 | INIT_LIST_HEAD(&file_priv->rps.link); |
b29c19b6 CW |
4699 | |
4700 | spin_lock_init(&file_priv->mm.lock); | |
4701 | INIT_LIST_HEAD(&file_priv->mm.request_list); | |
b29c19b6 | 4702 | |
c80ff16e | 4703 | file_priv->bsd_engine = -1; |
de1add36 | 4704 | |
e422b888 BW |
4705 | ret = i915_gem_context_open(dev, file); |
4706 | if (ret) | |
4707 | kfree(file_priv); | |
b29c19b6 | 4708 | |
e422b888 | 4709 | return ret; |
b29c19b6 CW |
4710 | } |
4711 | ||
b680c37a DV |
4712 | /** |
4713 | * i915_gem_track_fb - update frontbuffer tracking | |
d9072a3e GT |
4714 | * @old: current GEM buffer for the frontbuffer slots |
4715 | * @new: new GEM buffer for the frontbuffer slots | |
4716 | * @frontbuffer_bits: bitmask of frontbuffer slots | |
b680c37a DV |
4717 | * |
4718 | * This updates the frontbuffer tracking bits @frontbuffer_bits by clearing them | |
4719 | * from @old and setting them in @new. Both @old and @new can be NULL. | |
4720 | */ | |
a071fa00 DV |
4721 | void i915_gem_track_fb(struct drm_i915_gem_object *old, |
4722 | struct drm_i915_gem_object *new, | |
4723 | unsigned frontbuffer_bits) | |
4724 | { | |
faf5bf0a CW |
4725 | /* Control of individual bits within the mask are guarded by |
4726 | * the owning plane->mutex, i.e. we can never see concurrent | |
4727 | * manipulation of individual bits. But since the bitfield as a whole | |
4728 | * is updated using RMW, we need to use atomics in order to update | |
4729 | * the bits. | |
4730 | */ | |
4731 | BUILD_BUG_ON(INTEL_FRONTBUFFER_BITS_PER_PIPE * I915_MAX_PIPES > | |
4732 | sizeof(atomic_t) * BITS_PER_BYTE); | |
4733 | ||
a071fa00 | 4734 | if (old) { |
faf5bf0a CW |
4735 | WARN_ON(!(atomic_read(&old->frontbuffer_bits) & frontbuffer_bits)); |
4736 | atomic_andnot(frontbuffer_bits, &old->frontbuffer_bits); | |
a071fa00 DV |
4737 | } |
4738 | ||
4739 | if (new) { | |
faf5bf0a CW |
4740 | WARN_ON(atomic_read(&new->frontbuffer_bits) & frontbuffer_bits); |
4741 | atomic_or(frontbuffer_bits, &new->frontbuffer_bits); | |
a071fa00 DV |
4742 | } |
4743 | } | |
4744 | ||
ea70299d DG |
4745 | /* Allocate a new GEM object and fill it with the supplied data */ |
4746 | struct drm_i915_gem_object * | |
12d79d78 | 4747 | i915_gem_object_create_from_data(struct drm_i915_private *dev_priv, |
ea70299d DG |
4748 | const void *data, size_t size) |
4749 | { | |
4750 | struct drm_i915_gem_object *obj; | |
4751 | struct sg_table *sg; | |
4752 | size_t bytes; | |
4753 | int ret; | |
4754 | ||
12d79d78 | 4755 | obj = i915_gem_object_create(dev_priv, round_up(size, PAGE_SIZE)); |
fe3db79b | 4756 | if (IS_ERR(obj)) |
ea70299d DG |
4757 | return obj; |
4758 | ||
4759 | ret = i915_gem_object_set_to_cpu_domain(obj, true); | |
4760 | if (ret) | |
4761 | goto fail; | |
4762 | ||
a4f5ea64 | 4763 | ret = i915_gem_object_pin_pages(obj); |
ea70299d DG |
4764 | if (ret) |
4765 | goto fail; | |
4766 | ||
a4f5ea64 | 4767 | sg = obj->mm.pages; |
ea70299d | 4768 | bytes = sg_copy_from_buffer(sg->sgl, sg->nents, (void *)data, size); |
a4f5ea64 | 4769 | obj->mm.dirty = true; /* Backing store is now out of date */ |
ea70299d DG |
4770 | i915_gem_object_unpin_pages(obj); |
4771 | ||
4772 | if (WARN_ON(bytes != size)) { | |
4773 | DRM_ERROR("Incomplete copy, wrote %zu of %zu", bytes, size); | |
4774 | ret = -EFAULT; | |
4775 | goto fail; | |
4776 | } | |
4777 | ||
4778 | return obj; | |
4779 | ||
4780 | fail: | |
f8c417cd | 4781 | i915_gem_object_put(obj); |
ea70299d DG |
4782 | return ERR_PTR(ret); |
4783 | } | |
96d77634 CW |
4784 | |
4785 | struct scatterlist * | |
4786 | i915_gem_object_get_sg(struct drm_i915_gem_object *obj, | |
4787 | unsigned int n, | |
4788 | unsigned int *offset) | |
4789 | { | |
a4f5ea64 | 4790 | struct i915_gem_object_page_iter *iter = &obj->mm.get_page; |
96d77634 CW |
4791 | struct scatterlist *sg; |
4792 | unsigned int idx, count; | |
4793 | ||
4794 | might_sleep(); | |
4795 | GEM_BUG_ON(n >= obj->base.size >> PAGE_SHIFT); | |
a4f5ea64 | 4796 | GEM_BUG_ON(!i915_gem_object_has_pinned_pages(obj)); |
96d77634 CW |
4797 | |
4798 | /* As we iterate forward through the sg, we record each entry in a | |
4799 | * radixtree for quick repeated (backwards) lookups. If we have seen | |
4800 | * this index previously, we will have an entry for it. | |
4801 | * | |
4802 | * Initial lookup is O(N), but this is amortized to O(1) for | |
4803 | * sequential page access (where each new request is consecutive | |
4804 | * to the previous one). Repeated lookups are O(lg(obj->base.size)), | |
4805 | * i.e. O(1) with a large constant! | |
4806 | */ | |
4807 | if (n < READ_ONCE(iter->sg_idx)) | |
4808 | goto lookup; | |
4809 | ||
4810 | mutex_lock(&iter->lock); | |
4811 | ||
4812 | /* We prefer to reuse the last sg so that repeated lookup of this | |
4813 | * (or the subsequent) sg are fast - comparing against the last | |
4814 | * sg is faster than going through the radixtree. | |
4815 | */ | |
4816 | ||
4817 | sg = iter->sg_pos; | |
4818 | idx = iter->sg_idx; | |
4819 | count = __sg_page_count(sg); | |
4820 | ||
4821 | while (idx + count <= n) { | |
4822 | unsigned long exception, i; | |
4823 | int ret; | |
4824 | ||
4825 | /* If we cannot allocate and insert this entry, or the | |
4826 | * individual pages from this range, cancel updating the | |
4827 | * sg_idx so that on this lookup we are forced to linearly | |
4828 | * scan onwards, but on future lookups we will try the | |
4829 | * insertion again (in which case we need to be careful of | |
4830 | * the error return reporting that we have already inserted | |
4831 | * this index). | |
4832 | */ | |
4833 | ret = radix_tree_insert(&iter->radix, idx, sg); | |
4834 | if (ret && ret != -EEXIST) | |
4835 | goto scan; | |
4836 | ||
4837 | exception = | |
4838 | RADIX_TREE_EXCEPTIONAL_ENTRY | | |
4839 | idx << RADIX_TREE_EXCEPTIONAL_SHIFT; | |
4840 | for (i = 1; i < count; i++) { | |
4841 | ret = radix_tree_insert(&iter->radix, idx + i, | |
4842 | (void *)exception); | |
4843 | if (ret && ret != -EEXIST) | |
4844 | goto scan; | |
4845 | } | |
4846 | ||
4847 | idx += count; | |
4848 | sg = ____sg_next(sg); | |
4849 | count = __sg_page_count(sg); | |
4850 | } | |
4851 | ||
4852 | scan: | |
4853 | iter->sg_pos = sg; | |
4854 | iter->sg_idx = idx; | |
4855 | ||
4856 | mutex_unlock(&iter->lock); | |
4857 | ||
4858 | if (unlikely(n < idx)) /* insertion completed by another thread */ | |
4859 | goto lookup; | |
4860 | ||
4861 | /* In case we failed to insert the entry into the radixtree, we need | |
4862 | * to look beyond the current sg. | |
4863 | */ | |
4864 | while (idx + count <= n) { | |
4865 | idx += count; | |
4866 | sg = ____sg_next(sg); | |
4867 | count = __sg_page_count(sg); | |
4868 | } | |
4869 | ||
4870 | *offset = n - idx; | |
4871 | return sg; | |
4872 | ||
4873 | lookup: | |
4874 | rcu_read_lock(); | |
4875 | ||
4876 | sg = radix_tree_lookup(&iter->radix, n); | |
4877 | GEM_BUG_ON(!sg); | |
4878 | ||
4879 | /* If this index is in the middle of multi-page sg entry, | |
4880 | * the radixtree will contain an exceptional entry that points | |
4881 | * to the start of that range. We will return the pointer to | |
4882 | * the base page and the offset of this page within the | |
4883 | * sg entry's range. | |
4884 | */ | |
4885 | *offset = 0; | |
4886 | if (unlikely(radix_tree_exception(sg))) { | |
4887 | unsigned long base = | |
4888 | (unsigned long)sg >> RADIX_TREE_EXCEPTIONAL_SHIFT; | |
4889 | ||
4890 | sg = radix_tree_lookup(&iter->radix, base); | |
4891 | GEM_BUG_ON(!sg); | |
4892 | ||
4893 | *offset = n - base; | |
4894 | } | |
4895 | ||
4896 | rcu_read_unlock(); | |
4897 | ||
4898 | return sg; | |
4899 | } | |
4900 | ||
4901 | struct page * | |
4902 | i915_gem_object_get_page(struct drm_i915_gem_object *obj, unsigned int n) | |
4903 | { | |
4904 | struct scatterlist *sg; | |
4905 | unsigned int offset; | |
4906 | ||
4907 | GEM_BUG_ON(!i915_gem_object_has_struct_page(obj)); | |
4908 | ||
4909 | sg = i915_gem_object_get_sg(obj, n, &offset); | |
4910 | return nth_page(sg_page(sg), offset); | |
4911 | } | |
4912 | ||
4913 | /* Like i915_gem_object_get_page(), but mark the returned page dirty */ | |
4914 | struct page * | |
4915 | i915_gem_object_get_dirty_page(struct drm_i915_gem_object *obj, | |
4916 | unsigned int n) | |
4917 | { | |
4918 | struct page *page; | |
4919 | ||
4920 | page = i915_gem_object_get_page(obj, n); | |
a4f5ea64 | 4921 | if (!obj->mm.dirty) |
96d77634 CW |
4922 | set_page_dirty(page); |
4923 | ||
4924 | return page; | |
4925 | } | |
4926 | ||
4927 | dma_addr_t | |
4928 | i915_gem_object_get_dma_address(struct drm_i915_gem_object *obj, | |
4929 | unsigned long n) | |
4930 | { | |
4931 | struct scatterlist *sg; | |
4932 | unsigned int offset; | |
4933 | ||
4934 | sg = i915_gem_object_get_sg(obj, n, &offset); | |
4935 | return sg_dma_address(sg) + (offset << PAGE_SHIFT); | |
4936 | } |