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drm/i915/dp: Add DPCD data to debug output
[mirror_ubuntu-focal-kernel.git] / drivers / gpu / drm / i915 / i915_gem.c
CommitLineData
673a394b
EA		 1/*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 *
26 */
27
28#include "drmP.h"
29#include "drm.h"
30#include "i915_drm.h"
31#include "i915_drv.h"
1c5d22f7 32#include "i915_trace.h"
652c393a 33#include "intel_drv.h"
5a0e3ad6 34#include <linux/slab.h>
673a394b 35#include <linux/swap.h>
79e53945 36#include <linux/pci.h>
673a394b 37
e47c68e9
EA		 38static void i915_gem_object_flush_gpu_write_domain(struct drm_gem_object *obj);
39static void i915_gem_object_flush_gtt_write_domain(struct drm_gem_object *obj);
40static void i915_gem_object_flush_cpu_write_domain(struct drm_gem_object *obj);
e47c68e9
EA		 41static int i915_gem_object_set_to_cpu_domain(struct drm_gem_object *obj,
42 int write);
43static int i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object *obj,
44 uint64_t offset,
45 uint64_t size);
46static void i915_gem_object_set_to_full_cpu_read_domain(struct drm_gem_object *obj);
673a394b 47static int i915_gem_object_wait_rendering(struct drm_gem_object *obj);
de151cf6
JB		 48static int i915_gem_object_bind_to_gtt(struct drm_gem_object *obj,
49 unsigned alignment);
de151cf6 50static void i915_gem_clear_fence_reg(struct drm_gem_object *obj);
07f73f69 51static int i915_gem_evict_something(struct drm_device *dev, int min_size);
ab5ee576 52static int i915_gem_evict_from_inactive_list(struct drm_device *dev);
71acb5eb
DA		 53static int i915_gem_phys_pwrite(struct drm_device *dev, struct drm_gem_object *obj,
54 struct drm_i915_gem_pwrite *args,
55 struct drm_file *file_priv);
673a394b 56
31169714
CW		 57static LIST_HEAD(shrink_list);
58static DEFINE_SPINLOCK(shrink_list_lock);
59
79e53945
JB		 60int i915_gem_do_init(struct drm_device *dev, unsigned long start,
61 unsigned long end)
673a394b
EA		 62{
63 drm_i915_private_t *dev_priv = dev->dev_private;
673a394b 64
79e53945
JB		 65 if (start >= end ||
66 (start & (PAGE_SIZE - 1)) != 0 ||
67 (end & (PAGE_SIZE - 1)) != 0) {
673a394b
EA		 68 return -EINVAL;
69 }
70
79e53945
JB		 71 drm_mm_init(&dev_priv->mm.gtt_space, start,
72 end - start);
673a394b 73
79e53945
JB		 74 dev->gtt_total = (uint32_t) (end - start);
75
76 return 0;
77}
673a394b 78
79e53945
JB		 79int
80i915_gem_init_ioctl(struct drm_device *dev, void *data,
81 struct drm_file *file_priv)
82{
83 struct drm_i915_gem_init *args = data;
84 int ret;
85
86 mutex_lock(&dev->struct_mutex);
87 ret = i915_gem_do_init(dev, args->gtt_start, args->gtt_end);
673a394b
EA		 88 mutex_unlock(&dev->struct_mutex);
89
79e53945 90 return ret;
673a394b
EA		 91}
92
5a125c3c
EA		 93int
94i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
95 struct drm_file *file_priv)
96{
5a125c3c 97 struct drm_i915_gem_get_aperture *args = data;
5a125c3c
EA		 98
99 if (!(dev->driver->driver_features & DRIVER_GEM))
100 return -ENODEV;
101
102 args->aper_size = dev->gtt_total;
2678d9d6
KP		 103 args->aper_available_size = (args->aper_size -
104 atomic_read(&dev->pin_memory));
5a125c3c
EA		 105
106 return 0;
107}
108
673a394b
EA		 109
110/**
111 * Creates a new mm object and returns a handle to it.
112 */
113int
114i915_gem_create_ioctl(struct drm_device *dev, void *data,
115 struct drm_file *file_priv)
116{
117 struct drm_i915_gem_create *args = data;
118 struct drm_gem_object *obj;
a1a2d1d3
PP		 119 int ret;
120 u32 handle;
673a394b
EA		 121
122 args->size = roundup(args->size, PAGE_SIZE);
123
124 /* Allocate the new object */
ac52bc56 125 obj = i915_gem_alloc_object(dev, args->size);
673a394b
EA		 126 if (obj == NULL)
127 return -ENOMEM;
128
129 ret = drm_gem_handle_create(file_priv, obj, &handle);
bc9025bd 130 drm_gem_object_handle_unreference_unlocked(obj);
673a394b
EA		 131
132 if (ret)
133 return ret;
134
135 args->handle = handle;
136
137 return 0;
138}
139
eb01459f
EA		 140static inline int
141fast_shmem_read(struct page **pages,
142 loff_t page_base, int page_offset,
143 char __user *data,
144 int length)
145{
146 char __iomem *vaddr;
2bc43b5c 147 int unwritten;
eb01459f
EA		 148
149 vaddr = kmap_atomic(pages[page_base >> PAGE_SHIFT], KM_USER0);
150 if (vaddr == NULL)
151 return -ENOMEM;
2bc43b5c 152 unwritten = __copy_to_user_inatomic(data, vaddr + page_offset, length);
eb01459f
EA		 153 kunmap_atomic(vaddr, KM_USER0);
154
2bc43b5c
FM		 155 if (unwritten)
156 return -EFAULT;
157
158 return 0;
eb01459f
EA		 159}
160
280b713b
EA		 161static int i915_gem_object_needs_bit17_swizzle(struct drm_gem_object *obj)
162{
163 drm_i915_private_t *dev_priv = obj->dev->dev_private;
23010e43 164 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
280b713b
EA		 165
166 return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
167 obj_priv->tiling_mode != I915_TILING_NONE;
168}
169
40123c1f
EA		 170static inline int
171slow_shmem_copy(struct page *dst_page,
172 int dst_offset,
173 struct page *src_page,
174 int src_offset,
175 int length)
176{
177 char *dst_vaddr, *src_vaddr;
178
179 dst_vaddr = kmap_atomic(dst_page, KM_USER0);
180 if (dst_vaddr == NULL)
181 return -ENOMEM;
182
183 src_vaddr = kmap_atomic(src_page, KM_USER1);
184 if (src_vaddr == NULL) {
185 kunmap_atomic(dst_vaddr, KM_USER0);
186 return -ENOMEM;
187 }
188
189 memcpy(dst_vaddr + dst_offset, src_vaddr + src_offset, length);
190
191 kunmap_atomic(src_vaddr, KM_USER1);
192 kunmap_atomic(dst_vaddr, KM_USER0);
193
194 return 0;
195}
196
280b713b
EA		 197static inline int
198slow_shmem_bit17_copy(struct page *gpu_page,
199 int gpu_offset,
200 struct page *cpu_page,
201 int cpu_offset,
202 int length,
203 int is_read)
204{
205 char *gpu_vaddr, *cpu_vaddr;
206
207 /* Use the unswizzled path if this page isn't affected. */
208 if ((page_to_phys(gpu_page) & (1 << 17)) == 0) {
209 if (is_read)
210 return slow_shmem_copy(cpu_page, cpu_offset,
211 gpu_page, gpu_offset, length);
212 else
213 return slow_shmem_copy(gpu_page, gpu_offset,
214 cpu_page, cpu_offset, length);
215 }
216
217 gpu_vaddr = kmap_atomic(gpu_page, KM_USER0);
218 if (gpu_vaddr == NULL)
219 return -ENOMEM;
220
221 cpu_vaddr = kmap_atomic(cpu_page, KM_USER1);
222 if (cpu_vaddr == NULL) {
223 kunmap_atomic(gpu_vaddr, KM_USER0);
224 return -ENOMEM;
225 }
226
227 /* Copy the data, XORing A6 with A17 (1). The user already knows he's
228 * XORing with the other bits (A9 for Y, A9 and A10 for X)
229 */
230 while (length > 0) {
231 int cacheline_end = ALIGN(gpu_offset + 1, 64);
232 int this_length = min(cacheline_end - gpu_offset, length);
233 int swizzled_gpu_offset = gpu_offset ^ 64;
234
235 if (is_read) {
236 memcpy(cpu_vaddr + cpu_offset,
237 gpu_vaddr + swizzled_gpu_offset,
238 this_length);
239 } else {
240 memcpy(gpu_vaddr + swizzled_gpu_offset,
241 cpu_vaddr + cpu_offset,
242 this_length);
243 }
244 cpu_offset += this_length;
245 gpu_offset += this_length;
246 length -= this_length;
247 }
248
249 kunmap_atomic(cpu_vaddr, KM_USER1);
250 kunmap_atomic(gpu_vaddr, KM_USER0);
251
252 return 0;
253}
254
eb01459f
EA		 255/**
256 * This is the fast shmem pread path, which attempts to copy_from_user directly
257 * from the backing pages of the object to the user's address space. On a
258 * fault, it fails so we can fall back to i915_gem_shmem_pwrite_slow().
259 */
260static int
261i915_gem_shmem_pread_fast(struct drm_device *dev, struct drm_gem_object *obj,
262 struct drm_i915_gem_pread *args,
263 struct drm_file *file_priv)
264{
23010e43 265 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
eb01459f
EA		 266 ssize_t remain;
267 loff_t offset, page_base;
268 char __user *user_data;
269 int page_offset, page_length;
270 int ret;
271
272 user_data = (char __user *) (uintptr_t) args->data_ptr;
273 remain = args->size;
274
275 mutex_lock(&dev->struct_mutex);
276
4bdadb97 277 ret = i915_gem_object_get_pages(obj, 0);
eb01459f
EA		 278 if (ret != 0)
279 goto fail_unlock;
280
281 ret = i915_gem_object_set_cpu_read_domain_range(obj, args->offset,
282 args->size);
283 if (ret != 0)
284 goto fail_put_pages;
285
23010e43 286 obj_priv = to_intel_bo(obj);
eb01459f
EA		 287 offset = args->offset;
288
289 while (remain > 0) {
290 /* Operation in this page
291 *
292 * page_base = page offset within aperture
293 * page_offset = offset within page
294 * page_length = bytes to copy for this page
295 */
296 page_base = (offset & ~(PAGE_SIZE-1));
297 page_offset = offset & (PAGE_SIZE-1);
298 page_length = remain;
299 if ((page_offset + remain) > PAGE_SIZE)
300 page_length = PAGE_SIZE - page_offset;
301
302 ret = fast_shmem_read(obj_priv->pages,
303 page_base, page_offset,
304 user_data, page_length);
305 if (ret)
306 goto fail_put_pages;
307
308 remain -= page_length;
309 user_data += page_length;
310 offset += page_length;
311 }
312
313fail_put_pages:
314 i915_gem_object_put_pages(obj);
315fail_unlock:
316 mutex_unlock(&dev->struct_mutex);
317
318 return ret;
319}
320
07f73f69
CW		 321static int
322i915_gem_object_get_pages_or_evict(struct drm_gem_object *obj)
323{
324 int ret;
325
4bdadb97 326 ret = i915_gem_object_get_pages(obj, __GFP_NORETRY | __GFP_NOWARN);
07f73f69
CW		 327
328 /* If we've insufficient memory to map in the pages, attempt
329 * to make some space by throwing out some old buffers.
330 */
331 if (ret == -ENOMEM) {
332 struct drm_device *dev = obj->dev;
07f73f69
CW		 333
334 ret = i915_gem_evict_something(dev, obj->size);
335 if (ret)
336 return ret;
337
4bdadb97 338 ret = i915_gem_object_get_pages(obj, 0);
07f73f69
CW		 339 }
340
341 return ret;
342}
343
eb01459f
EA		 344/**
345 * This is the fallback shmem pread path, which allocates temporary storage
346 * in kernel space to copy_to_user into outside of the struct_mutex, so we
347 * can copy out of the object's backing pages while holding the struct mutex
348 * and not take page faults.
349 */
350static int
351i915_gem_shmem_pread_slow(struct drm_device *dev, struct drm_gem_object *obj,
352 struct drm_i915_gem_pread *args,
353 struct drm_file *file_priv)
354{
23010e43 355 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
eb01459f
EA		 356 struct mm_struct *mm = current->mm;
357 struct page **user_pages;
358 ssize_t remain;
359 loff_t offset, pinned_pages, i;
360 loff_t first_data_page, last_data_page, num_pages;
361 int shmem_page_index, shmem_page_offset;
362 int data_page_index, data_page_offset;
363 int page_length;
364 int ret;
365 uint64_t data_ptr = args->data_ptr;
280b713b 366 int do_bit17_swizzling;
eb01459f
EA		 367
368 remain = args->size;
369
370 /* Pin the user pages containing the data. We can't fault while
371 * holding the struct mutex, yet we want to hold it while
372 * dereferencing the user data.
373 */
374 first_data_page = data_ptr / PAGE_SIZE;
375 last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE;
376 num_pages = last_data_page - first_data_page + 1;
377
8e7d2b2c 378 user_pages = drm_calloc_large(num_pages, sizeof(struct page *));
eb01459f
EA		 379 if (user_pages == NULL)
380 return -ENOMEM;
381
382 down_read(&mm->mmap_sem);
383 pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr,
e5e9ecde 384 num_pages, 1, 0, user_pages, NULL);
eb01459f
EA		 385 up_read(&mm->mmap_sem);
386 if (pinned_pages < num_pages) {
387 ret = -EFAULT;
388 goto fail_put_user_pages;
389 }
390
280b713b
EA		 391 do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
392
eb01459f
EA		 393 mutex_lock(&dev->struct_mutex);
394
07f73f69
CW		 395 ret = i915_gem_object_get_pages_or_evict(obj);
396 if (ret)
eb01459f
EA		 397 goto fail_unlock;
398
399 ret = i915_gem_object_set_cpu_read_domain_range(obj, args->offset,
400 args->size);
401 if (ret != 0)
402 goto fail_put_pages;
403
23010e43 404 obj_priv = to_intel_bo(obj);
eb01459f
EA		 405 offset = args->offset;
406
407 while (remain > 0) {
408 /* Operation in this page
409 *
410 * shmem_page_index = page number within shmem file
411 * shmem_page_offset = offset within page in shmem file
412 * data_page_index = page number in get_user_pages return
413 * data_page_offset = offset with data_page_index page.
414 * page_length = bytes to copy for this page
415 */
416 shmem_page_index = offset / PAGE_SIZE;
417 shmem_page_offset = offset & ~PAGE_MASK;
418 data_page_index = data_ptr / PAGE_SIZE - first_data_page;
419 data_page_offset = data_ptr & ~PAGE_MASK;
420
421 page_length = remain;
422 if ((shmem_page_offset + page_length) > PAGE_SIZE)
423 page_length = PAGE_SIZE - shmem_page_offset;
424 if ((data_page_offset + page_length) > PAGE_SIZE)
425 page_length = PAGE_SIZE - data_page_offset;
426
280b713b
EA		 427 if (do_bit17_swizzling) {
428 ret = slow_shmem_bit17_copy(obj_priv->pages[shmem_page_index],
429 shmem_page_offset,
430 user_pages[data_page_index],
431 data_page_offset,
432 page_length,
433 1);
434 } else {
435 ret = slow_shmem_copy(user_pages[data_page_index],
436 data_page_offset,
437 obj_priv->pages[shmem_page_index],
438 shmem_page_offset,
439 page_length);
440 }
eb01459f
EA		 441 if (ret)
442 goto fail_put_pages;
443
444 remain -= page_length;
445 data_ptr += page_length;
446 offset += page_length;
447 }
448
449fail_put_pages:
450 i915_gem_object_put_pages(obj);
451fail_unlock:
452 mutex_unlock(&dev->struct_mutex);
453fail_put_user_pages:
454 for (i = 0; i < pinned_pages; i++) {
455 SetPageDirty(user_pages[i]);
456 page_cache_release(user_pages[i]);
457 }
8e7d2b2c 458 drm_free_large(user_pages);
eb01459f
EA		 459
460 return ret;
461}
462
673a394b
EA		 463/**
464 * Reads data from the object referenced by handle.
465 *
466 * On error, the contents of *data are undefined.
467 */
468int
469i915_gem_pread_ioctl(struct drm_device *dev, void *data,
470 struct drm_file *file_priv)
471{
472 struct drm_i915_gem_pread *args = data;
473 struct drm_gem_object *obj;
474 struct drm_i915_gem_object *obj_priv;
673a394b
EA		 475 int ret;
476
477 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
478 if (obj == NULL)
479 return -EBADF;
23010e43 480 obj_priv = to_intel_bo(obj);
673a394b
EA		 481
482 /* Bounds check source.
483 *
484 * XXX: This could use review for overflow issues...
485 */
486 if (args->offset > obj->size || args->size > obj->size ||
487 args->offset + args->size > obj->size) {
bc9025bd 488 drm_gem_object_unreference_unlocked(obj);
673a394b
EA		 489 return -EINVAL;
490 }
491
280b713b 492 if (i915_gem_object_needs_bit17_swizzle(obj)) {
eb01459f 493 ret = i915_gem_shmem_pread_slow(dev, obj, args, file_priv);
280b713b
EA		 494 } else {
495 ret = i915_gem_shmem_pread_fast(dev, obj, args, file_priv);
496 if (ret != 0)
497 ret = i915_gem_shmem_pread_slow(dev, obj, args,
498 file_priv);
499 }
673a394b 500
bc9025bd 501 drm_gem_object_unreference_unlocked(obj);
673a394b 502
eb01459f 503 return ret;
673a394b
EA		 504}
505
0839ccb8
KP		 506/* This is the fast write path which cannot handle
507 * page faults in the source data
9b7530cc 508 */
0839ccb8
KP		 509
510static inline int
511fast_user_write(struct io_mapping *mapping,
512 loff_t page_base, int page_offset,
513 char __user *user_data,
514 int length)
9b7530cc 515{
9b7530cc 516 char *vaddr_atomic;
0839ccb8 517 unsigned long unwritten;
9b7530cc 518
0839ccb8
KP		 519 vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base);
520 unwritten = __copy_from_user_inatomic_nocache(vaddr_atomic + page_offset,
521 user_data, length);
522 io_mapping_unmap_atomic(vaddr_atomic);
523 if (unwritten)
524 return -EFAULT;
525 return 0;
526}
527
528/* Here's the write path which can sleep for
529 * page faults
530 */
531
532static inline int
3de09aa3
EA		 533slow_kernel_write(struct io_mapping *mapping,
534 loff_t gtt_base, int gtt_offset,
535 struct page *user_page, int user_offset,
536 int length)
0839ccb8 537{
3de09aa3 538 char *src_vaddr, *dst_vaddr;
0839ccb8
KP		 539 unsigned long unwritten;
540
3de09aa3
EA		 541 dst_vaddr = io_mapping_map_atomic_wc(mapping, gtt_base);
542 src_vaddr = kmap_atomic(user_page, KM_USER1);
543 unwritten = __copy_from_user_inatomic_nocache(dst_vaddr + gtt_offset,
544 src_vaddr + user_offset,
545 length);
546 kunmap_atomic(src_vaddr, KM_USER1);
547 io_mapping_unmap_atomic(dst_vaddr);
0839ccb8
KP		 548 if (unwritten)
549 return -EFAULT;
9b7530cc 550 return 0;
9b7530cc
LT		 551}
552
40123c1f
EA		 553static inline int
554fast_shmem_write(struct page **pages,
555 loff_t page_base, int page_offset,
556 char __user *data,
557 int length)
558{
559 char __iomem *vaddr;
d0088775 560 unsigned long unwritten;
40123c1f
EA		 561
562 vaddr = kmap_atomic(pages[page_base >> PAGE_SHIFT], KM_USER0);
563 if (vaddr == NULL)
564 return -ENOMEM;
d0088775 565 unwritten = __copy_from_user_inatomic(vaddr + page_offset, data, length);
40123c1f
EA		 566 kunmap_atomic(vaddr, KM_USER0);
567
d0088775
DA		 568 if (unwritten)
569 return -EFAULT;
40123c1f
EA		 570 return 0;
571}
572
3de09aa3
EA		 573/**
574 * This is the fast pwrite path, where we copy the data directly from the
575 * user into the GTT, uncached.
576 */
673a394b 577static int
3de09aa3
EA		 578i915_gem_gtt_pwrite_fast(struct drm_device *dev, struct drm_gem_object *obj,
579 struct drm_i915_gem_pwrite *args,
580 struct drm_file *file_priv)
673a394b 581{
23010e43 582 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
0839ccb8 583 drm_i915_private_t *dev_priv = dev->dev_private;
673a394b 584 ssize_t remain;
0839ccb8 585 loff_t offset, page_base;
673a394b 586 char __user *user_data;
0839ccb8
KP		 587 int page_offset, page_length;
588 int ret;
673a394b
EA		 589
590 user_data = (char __user *) (uintptr_t) args->data_ptr;
591 remain = args->size;
592 if (!access_ok(VERIFY_READ, user_data, remain))
593 return -EFAULT;
594
595
596 mutex_lock(&dev->struct_mutex);
597 ret = i915_gem_object_pin(obj, 0);
598 if (ret) {
599 mutex_unlock(&dev->struct_mutex);
600 return ret;
601 }
2ef7eeaa 602 ret = i915_gem_object_set_to_gtt_domain(obj, 1);
673a394b
EA		 603 if (ret)
604 goto fail;
605
23010e43 606 obj_priv = to_intel_bo(obj);
673a394b 607 offset = obj_priv->gtt_offset + args->offset;
673a394b
EA		 608
609 while (remain > 0) {
610 /* Operation in this page
611 *
0839ccb8
KP		 612 * page_base = page offset within aperture
613 * page_offset = offset within page
614 * page_length = bytes to copy for this page
673a394b 615 */
0839ccb8
KP		 616 page_base = (offset & ~(PAGE_SIZE-1));
617 page_offset = offset & (PAGE_SIZE-1);
618 page_length = remain;
619 if ((page_offset + remain) > PAGE_SIZE)
620 page_length = PAGE_SIZE - page_offset;
621
622 ret = fast_user_write (dev_priv->mm.gtt_mapping, page_base,
623 page_offset, user_data, page_length);
624
625 /* If we get a fault while copying data, then (presumably) our
3de09aa3
EA		 626 * source page isn't available. Return the error and we'll
627 * retry in the slow path.
0839ccb8 628 */
3de09aa3
EA		 629 if (ret)
630 goto fail;
673a394b 631
0839ccb8
KP		 632 remain -= page_length;
633 user_data += page_length;
634 offset += page_length;
673a394b 635 }
673a394b
EA		 636
637fail:
638 i915_gem_object_unpin(obj);
639 mutex_unlock(&dev->struct_mutex);
640
641 return ret;
642}
643
3de09aa3
EA		 644/**
645 * This is the fallback GTT pwrite path, which uses get_user_pages to pin
646 * the memory and maps it using kmap_atomic for copying.
647 *
648 * This code resulted in x11perf -rgb10text consuming about 10% more CPU
649 * than using i915_gem_gtt_pwrite_fast on a G45 (32-bit).
650 */
3043c60c 651static int
3de09aa3
EA		 652i915_gem_gtt_pwrite_slow(struct drm_device *dev, struct drm_gem_object *obj,
653 struct drm_i915_gem_pwrite *args,
654 struct drm_file *file_priv)
673a394b 655{
23010e43 656 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
3de09aa3
EA		 657 drm_i915_private_t *dev_priv = dev->dev_private;
658 ssize_t remain;
659 loff_t gtt_page_base, offset;
660 loff_t first_data_page, last_data_page, num_pages;
661 loff_t pinned_pages, i;
662 struct page **user_pages;
663 struct mm_struct *mm = current->mm;
664 int gtt_page_offset, data_page_offset, data_page_index, page_length;
673a394b 665 int ret;
3de09aa3
EA		 666 uint64_t data_ptr = args->data_ptr;
667
668 remain = args->size;
669
670 /* Pin the user pages containing the data. We can't fault while
671 * holding the struct mutex, and all of the pwrite implementations
672 * want to hold it while dereferencing the user data.
673 */
674 first_data_page = data_ptr / PAGE_SIZE;
675 last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE;
676 num_pages = last_data_page - first_data_page + 1;
677
8e7d2b2c 678 user_pages = drm_calloc_large(num_pages, sizeof(struct page *));
3de09aa3
EA		 679 if (user_pages == NULL)
680 return -ENOMEM;
681
682 down_read(&mm->mmap_sem);
683 pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr,
684 num_pages, 0, 0, user_pages, NULL);
685 up_read(&mm->mmap_sem);
686 if (pinned_pages < num_pages) {
687 ret = -EFAULT;
688 goto out_unpin_pages;
689 }
673a394b
EA		 690
691 mutex_lock(&dev->struct_mutex);
3de09aa3
EA		 692 ret = i915_gem_object_pin(obj, 0);
693 if (ret)
694 goto out_unlock;
695
696 ret = i915_gem_object_set_to_gtt_domain(obj, 1);
697 if (ret)
698 goto out_unpin_object;
699
23010e43 700 obj_priv = to_intel_bo(obj);
3de09aa3
EA		 701 offset = obj_priv->gtt_offset + args->offset;
702
703 while (remain > 0) {
704 /* Operation in this page
705 *
706 * gtt_page_base = page offset within aperture
707 * gtt_page_offset = offset within page in aperture
708 * data_page_index = page number in get_user_pages return
709 * data_page_offset = offset with data_page_index page.
710 * page_length = bytes to copy for this page
711 */
712 gtt_page_base = offset & PAGE_MASK;
713 gtt_page_offset = offset & ~PAGE_MASK;
714 data_page_index = data_ptr / PAGE_SIZE - first_data_page;
715 data_page_offset = data_ptr & ~PAGE_MASK;
716
717 page_length = remain;
718 if ((gtt_page_offset + page_length) > PAGE_SIZE)
719 page_length = PAGE_SIZE - gtt_page_offset;
720 if ((data_page_offset + page_length) > PAGE_SIZE)
721 page_length = PAGE_SIZE - data_page_offset;
722
723 ret = slow_kernel_write(dev_priv->mm.gtt_mapping,
724 gtt_page_base, gtt_page_offset,
725 user_pages[data_page_index],
726 data_page_offset,
727 page_length);
728
729 /* If we get a fault while copying data, then (presumably) our
730 * source page isn't available. Return the error and we'll
731 * retry in the slow path.
732 */
733 if (ret)
734 goto out_unpin_object;
735
736 remain -= page_length;
737 offset += page_length;
738 data_ptr += page_length;
739 }
740
741out_unpin_object:
742 i915_gem_object_unpin(obj);
743out_unlock:
744 mutex_unlock(&dev->struct_mutex);
745out_unpin_pages:
746 for (i = 0; i < pinned_pages; i++)
747 page_cache_release(user_pages[i]);
8e7d2b2c 748 drm_free_large(user_pages);
3de09aa3
EA		 749
750 return ret;
751}
752
40123c1f
EA		 753/**
754 * This is the fast shmem pwrite path, which attempts to directly
755 * copy_from_user into the kmapped pages backing the object.
756 */
3043c60c 757static int
40123c1f
EA		 758i915_gem_shmem_pwrite_fast(struct drm_device *dev, struct drm_gem_object *obj,
759 struct drm_i915_gem_pwrite *args,
760 struct drm_file *file_priv)
673a394b 761{
23010e43 762 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
40123c1f
EA		 763 ssize_t remain;
764 loff_t offset, page_base;
765 char __user *user_data;
766 int page_offset, page_length;
673a394b 767 int ret;
40123c1f
EA		 768
769 user_data = (char __user *) (uintptr_t) args->data_ptr;
770 remain = args->size;
673a394b
EA		 771
772 mutex_lock(&dev->struct_mutex);
773
4bdadb97 774 ret = i915_gem_object_get_pages(obj, 0);
40123c1f
EA		 775 if (ret != 0)
776 goto fail_unlock;
673a394b 777
e47c68e9 778 ret = i915_gem_object_set_to_cpu_domain(obj, 1);
40123c1f
EA		 779 if (ret != 0)
780 goto fail_put_pages;
781
23010e43 782 obj_priv = to_intel_bo(obj);
40123c1f
EA		 783 offset = args->offset;
784 obj_priv->dirty = 1;
785
786 while (remain > 0) {
787 /* Operation in this page
788 *
789 * page_base = page offset within aperture
790 * page_offset = offset within page
791 * page_length = bytes to copy for this page
792 */
793 page_base = (offset & ~(PAGE_SIZE-1));
794 page_offset = offset & (PAGE_SIZE-1);
795 page_length = remain;
796 if ((page_offset + remain) > PAGE_SIZE)
797 page_length = PAGE_SIZE - page_offset;
798
799 ret = fast_shmem_write(obj_priv->pages,
800 page_base, page_offset,
801 user_data, page_length);
802 if (ret)
803 goto fail_put_pages;
804
805 remain -= page_length;
806 user_data += page_length;
807 offset += page_length;
808 }
809
810fail_put_pages:
811 i915_gem_object_put_pages(obj);
812fail_unlock:
813 mutex_unlock(&dev->struct_mutex);
814
815 return ret;
816}
817
818/**
819 * This is the fallback shmem pwrite path, which uses get_user_pages to pin
820 * the memory and maps it using kmap_atomic for copying.
821 *
822 * This avoids taking mmap_sem for faulting on the user's address while the
823 * struct_mutex is held.
824 */
825static int
826i915_gem_shmem_pwrite_slow(struct drm_device *dev, struct drm_gem_object *obj,
827 struct drm_i915_gem_pwrite *args,
828 struct drm_file *file_priv)
829{
23010e43 830 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
40123c1f
EA		 831 struct mm_struct *mm = current->mm;
832 struct page **user_pages;
833 ssize_t remain;
834 loff_t offset, pinned_pages, i;
835 loff_t first_data_page, last_data_page, num_pages;
836 int shmem_page_index, shmem_page_offset;
837 int data_page_index, data_page_offset;
838 int page_length;
839 int ret;
840 uint64_t data_ptr = args->data_ptr;
280b713b 841 int do_bit17_swizzling;
40123c1f
EA		 842
843 remain = args->size;
844
845 /* Pin the user pages containing the data. We can't fault while
846 * holding the struct mutex, and all of the pwrite implementations
847 * want to hold it while dereferencing the user data.
848 */
849 first_data_page = data_ptr / PAGE_SIZE;
850 last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE;
851 num_pages = last_data_page - first_data_page + 1;
852
8e7d2b2c 853 user_pages = drm_calloc_large(num_pages, sizeof(struct page *));
40123c1f
EA		 854 if (user_pages == NULL)
855 return -ENOMEM;
856
857 down_read(&mm->mmap_sem);
858 pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr,
859 num_pages, 0, 0, user_pages, NULL);
860 up_read(&mm->mmap_sem);
861 if (pinned_pages < num_pages) {
862 ret = -EFAULT;
863 goto fail_put_user_pages;
673a394b
EA		 864 }
865
280b713b
EA		 866 do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
867
40123c1f
EA		 868 mutex_lock(&dev->struct_mutex);
869
07f73f69
CW		 870 ret = i915_gem_object_get_pages_or_evict(obj);
871 if (ret)
40123c1f
EA		 872 goto fail_unlock;
873
874 ret = i915_gem_object_set_to_cpu_domain(obj, 1);
875 if (ret != 0)
876 goto fail_put_pages;
877
23010e43 878 obj_priv = to_intel_bo(obj);
673a394b 879 offset = args->offset;
40123c1f 880 obj_priv->dirty = 1;
673a394b 881
40123c1f
EA		 882 while (remain > 0) {
883 /* Operation in this page
884 *
885 * shmem_page_index = page number within shmem file
886 * shmem_page_offset = offset within page in shmem file
887 * data_page_index = page number in get_user_pages return
888 * data_page_offset = offset with data_page_index page.
889 * page_length = bytes to copy for this page
890 */
891 shmem_page_index = offset / PAGE_SIZE;
892 shmem_page_offset = offset & ~PAGE_MASK;
893 data_page_index = data_ptr / PAGE_SIZE - first_data_page;
894 data_page_offset = data_ptr & ~PAGE_MASK;
895
896 page_length = remain;
897 if ((shmem_page_offset + page_length) > PAGE_SIZE)
898 page_length = PAGE_SIZE - shmem_page_offset;
899 if ((data_page_offset + page_length) > PAGE_SIZE)
900 page_length = PAGE_SIZE - data_page_offset;
901
280b713b
EA		 902 if (do_bit17_swizzling) {
903 ret = slow_shmem_bit17_copy(obj_priv->pages[shmem_page_index],
904 shmem_page_offset,
905 user_pages[data_page_index],
906 data_page_offset,
907 page_length,
908 0);
909 } else {
910 ret = slow_shmem_copy(obj_priv->pages[shmem_page_index],
911 shmem_page_offset,
912 user_pages[data_page_index],
913 data_page_offset,
914 page_length);
915 }
40123c1f
EA		 916 if (ret)
917 goto fail_put_pages;
918
919 remain -= page_length;
920 data_ptr += page_length;
921 offset += page_length;
673a394b
EA		 922 }
923
40123c1f
EA		 924fail_put_pages:
925 i915_gem_object_put_pages(obj);
926fail_unlock:
673a394b 927 mutex_unlock(&dev->struct_mutex);
40123c1f
EA		 928fail_put_user_pages:
929 for (i = 0; i < pinned_pages; i++)
930 page_cache_release(user_pages[i]);
8e7d2b2c 931 drm_free_large(user_pages);
673a394b 932
40123c1f 933 return ret;
673a394b
EA		 934}
935
936/**
937 * Writes data to the object referenced by handle.
938 *
939 * On error, the contents of the buffer that were to be modified are undefined.
940 */
941int
942i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
943 struct drm_file *file_priv)
944{
945 struct drm_i915_gem_pwrite *args = data;
946 struct drm_gem_object *obj;
947 struct drm_i915_gem_object *obj_priv;
948 int ret = 0;
949
950 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
951 if (obj == NULL)
952 return -EBADF;
23010e43 953 obj_priv = to_intel_bo(obj);
673a394b
EA		 954
955 /* Bounds check destination.
956 *
957 * XXX: This could use review for overflow issues...
958 */
959 if (args->offset > obj->size || args->size > obj->size ||
960 args->offset + args->size > obj->size) {
bc9025bd 961 drm_gem_object_unreference_unlocked(obj);
673a394b
EA		 962 return -EINVAL;
963 }
964
965 /* We can only do the GTT pwrite on untiled buffers, as otherwise
966 * it would end up going through the fenced access, and we'll get
967 * different detiling behavior between reading and writing.
968 * pread/pwrite currently are reading and writing from the CPU
969 * perspective, requiring manual detiling by the client.
970 */
71acb5eb
DA		 971 if (obj_priv->phys_obj)
972 ret = i915_gem_phys_pwrite(dev, obj, args, file_priv);
973 else if (obj_priv->tiling_mode == I915_TILING_NONE &&
3de09aa3
EA		 974 dev->gtt_total != 0) {
975 ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file_priv);
976 if (ret == -EFAULT) {
977 ret = i915_gem_gtt_pwrite_slow(dev, obj, args,
978 file_priv);
979 }
280b713b
EA		 980 } else if (i915_gem_object_needs_bit17_swizzle(obj)) {
981 ret = i915_gem_shmem_pwrite_slow(dev, obj, args, file_priv);
40123c1f
EA		 982 } else {
983 ret = i915_gem_shmem_pwrite_fast(dev, obj, args, file_priv);
984 if (ret == -EFAULT) {
985 ret = i915_gem_shmem_pwrite_slow(dev, obj, args,
986 file_priv);
987 }
988 }
673a394b
EA		 989
990#if WATCH_PWRITE
991 if (ret)
992 DRM_INFO("pwrite failed %d\n", ret);
993#endif
994
bc9025bd 995 drm_gem_object_unreference_unlocked(obj);
673a394b
EA		 996
997 return ret;
998}
999
1000/**
2ef7eeaa
EA		 1001 * Called when user space prepares to use an object with the CPU, either
1002 * through the mmap ioctl's mapping or a GTT mapping.
673a394b
EA		 1003 */
1004int
1005i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1006 struct drm_file *file_priv)
1007{
a09ba7fa 1008 struct drm_i915_private *dev_priv = dev->dev_private;
673a394b
EA		 1009 struct drm_i915_gem_set_domain *args = data;
1010 struct drm_gem_object *obj;
652c393a 1011 struct drm_i915_gem_object *obj_priv;
2ef7eeaa
EA		 1012 uint32_t read_domains = args->read_domains;
1013 uint32_t write_domain = args->write_domain;
673a394b
EA		 1014 int ret;
1015
1016 if (!(dev->driver->driver_features & DRIVER_GEM))
1017 return -ENODEV;
1018
2ef7eeaa 1019 /* Only handle setting domains to types used by the CPU. */
21d509e3 1020 if (write_domain & I915_GEM_GPU_DOMAINS)
2ef7eeaa
EA		 1021 return -EINVAL;
1022
21d509e3 1023 if (read_domains & I915_GEM_GPU_DOMAINS)
2ef7eeaa
EA		 1024 return -EINVAL;
1025
1026 /* Having something in the write domain implies it's in the read
1027 * domain, and only that read domain. Enforce that in the request.
1028 */
1029 if (write_domain != 0 && read_domains != write_domain)
1030 return -EINVAL;
1031
673a394b
EA		 1032 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
1033 if (obj == NULL)
1034 return -EBADF;
23010e43 1035 obj_priv = to_intel_bo(obj);
673a394b
EA		 1036
1037 mutex_lock(&dev->struct_mutex);
652c393a
JB		 1038
1039 intel_mark_busy(dev, obj);
1040
673a394b 1041#if WATCH_BUF
cfd43c02 1042 DRM_INFO("set_domain_ioctl %p(%zd), %08x %08x\n",
2ef7eeaa 1043 obj, obj->size, read_domains, write_domain);
673a394b 1044#endif
2ef7eeaa
EA		 1045 if (read_domains & I915_GEM_DOMAIN_GTT) {
1046 ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0);
02354392 1047
a09ba7fa
EA		 1048 /* Update the LRU on the fence for the CPU access that's
1049 * about to occur.
1050 */
1051 if (obj_priv->fence_reg != I915_FENCE_REG_NONE) {
007cc8ac
DV		 1052 struct drm_i915_fence_reg *reg =
1053 &dev_priv->fence_regs[obj_priv->fence_reg];
1054 list_move_tail(&reg->lru_list,
a09ba7fa
EA		 1055 &dev_priv->mm.fence_list);
1056 }
1057
02354392
EA		 1058 /* Silently promote "you're not bound, there was nothing to do"
1059 * to success, since the client was just asking us to
1060 * make sure everything was done.
1061 */
1062 if (ret == -EINVAL)
1063 ret = 0;
2ef7eeaa 1064 } else {
e47c68e9 1065 ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0);
2ef7eeaa
EA		 1066 }
1067
673a394b
EA		 1068 drm_gem_object_unreference(obj);
1069 mutex_unlock(&dev->struct_mutex);
1070 return ret;
1071}
1072
1073/**
1074 * Called when user space has done writes to this buffer
1075 */
1076int
1077i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
1078 struct drm_file *file_priv)
1079{
1080 struct drm_i915_gem_sw_finish *args = data;
1081 struct drm_gem_object *obj;
1082 struct drm_i915_gem_object *obj_priv;
1083 int ret = 0;
1084
1085 if (!(dev->driver->driver_features & DRIVER_GEM))
1086 return -ENODEV;
1087
1088 mutex_lock(&dev->struct_mutex);
1089 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
1090 if (obj == NULL) {
1091 mutex_unlock(&dev->struct_mutex);
1092 return -EBADF;
1093 }
1094
1095#if WATCH_BUF
cfd43c02 1096 DRM_INFO("%s: sw_finish %d (%p %zd)\n",
673a394b
EA		 1097 __func__, args->handle, obj, obj->size);
1098#endif
23010e43 1099 obj_priv = to_intel_bo(obj);
673a394b
EA		 1100
1101 /* Pinned buffers may be scanout, so flush the cache */
e47c68e9
EA		 1102 if (obj_priv->pin_count)
1103 i915_gem_object_flush_cpu_write_domain(obj);
1104
673a394b
EA		 1105 drm_gem_object_unreference(obj);
1106 mutex_unlock(&dev->struct_mutex);
1107 return ret;
1108}
1109
1110/**
1111 * Maps the contents of an object, returning the address it is mapped
1112 * into.
1113 *
1114 * While the mapping holds a reference on the contents of the object, it doesn't
1115 * imply a ref on the object itself.
1116 */
1117int
1118i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
1119 struct drm_file *file_priv)
1120{
1121 struct drm_i915_gem_mmap *args = data;
1122 struct drm_gem_object *obj;
1123 loff_t offset;
1124 unsigned long addr;
1125
1126 if (!(dev->driver->driver_features & DRIVER_GEM))
1127 return -ENODEV;
1128
1129 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
1130 if (obj == NULL)
1131 return -EBADF;
1132
1133 offset = args->offset;
1134
1135 down_write(&current->mm->mmap_sem);
1136 addr = do_mmap(obj->filp, 0, args->size,
1137 PROT_READ | PROT_WRITE, MAP_SHARED,
1138 args->offset);
1139 up_write(&current->mm->mmap_sem);
bc9025bd 1140 drm_gem_object_unreference_unlocked(obj);
673a394b
EA		 1141 if (IS_ERR((void *)addr))
1142 return addr;
1143
1144 args->addr_ptr = (uint64_t) addr;
1145
1146 return 0;
1147}
1148
de151cf6
JB		 1149/**
1150 * i915_gem_fault - fault a page into the GTT
1151 * vma: VMA in question
1152 * vmf: fault info
1153 *
1154 * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
1155 * from userspace. The fault handler takes care of binding the object to
1156 * the GTT (if needed), allocating and programming a fence register (again,
1157 * only if needed based on whether the old reg is still valid or the object
1158 * is tiled) and inserting a new PTE into the faulting process.
1159 *
1160 * Note that the faulting process may involve evicting existing objects
1161 * from the GTT and/or fence registers to make room. So performance may
1162 * suffer if the GTT working set is large or there are few fence registers
1163 * left.
1164 */
1165int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
1166{
1167 struct drm_gem_object *obj = vma->vm_private_data;
1168 struct drm_device *dev = obj->dev;
1169 struct drm_i915_private *dev_priv = dev->dev_private;
23010e43 1170 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
de151cf6
JB		 1171 pgoff_t page_offset;
1172 unsigned long pfn;
1173 int ret = 0;
0f973f27 1174 bool write = !!(vmf->flags & FAULT_FLAG_WRITE);
de151cf6
JB		 1175
1176 /* We don't use vmf->pgoff since that has the fake offset */
1177 page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >>
1178 PAGE_SHIFT;
1179
1180 /* Now bind it into the GTT if needed */
1181 mutex_lock(&dev->struct_mutex);
1182 if (!obj_priv->gtt_space) {
e67b8ce1 1183 ret = i915_gem_object_bind_to_gtt(obj, 0);
c715089f
CW		 1184 if (ret)
1185 goto unlock;
07f4f3e8 1186
14b60391 1187 list_add_tail(&obj_priv->list, &dev_priv->mm.inactive_list);
07f4f3e8
KH		 1188
1189 ret = i915_gem_object_set_to_gtt_domain(obj, write);
c715089f
CW		 1190 if (ret)
1191 goto unlock;
de151cf6
JB		 1192 }
1193
1194 /* Need a new fence register? */
a09ba7fa 1195 if (obj_priv->tiling_mode != I915_TILING_NONE) {
8c4b8c3f 1196 ret = i915_gem_object_get_fence_reg(obj);
c715089f
CW		 1197 if (ret)
1198 goto unlock;
d9ddcb96 1199 }
de151cf6
JB		 1200
1201 pfn = ((dev->agp->base + obj_priv->gtt_offset) >> PAGE_SHIFT) +
1202 page_offset;
1203
1204 /* Finally, remap it using the new GTT offset */
1205 ret = vm_insert_pfn(vma, (unsigned long)vmf->virtual_address, pfn);
c715089f 1206unlock:
de151cf6
JB		 1207 mutex_unlock(&dev->struct_mutex);
1208
1209 switch (ret) {
c715089f
CW		 1210 case 0:
1211 case -ERESTARTSYS:
1212 return VM_FAULT_NOPAGE;
de151cf6
JB		 1213 case -ENOMEM:
1214 case -EAGAIN:
1215 return VM_FAULT_OOM;
de151cf6 1216 default:
c715089f 1217 return VM_FAULT_SIGBUS;
de151cf6
JB		 1218 }
1219}
1220
1221/**
1222 * i915_gem_create_mmap_offset - create a fake mmap offset for an object
1223 * @obj: obj in question
1224 *
1225 * GEM memory mapping works by handing back to userspace a fake mmap offset
1226 * it can use in a subsequent mmap(2) call. The DRM core code then looks
1227 * up the object based on the offset and sets up the various memory mapping
1228 * structures.
1229 *
1230 * This routine allocates and attaches a fake offset for @obj.
1231 */
1232static int
1233i915_gem_create_mmap_offset(struct drm_gem_object *obj)
1234{
1235 struct drm_device *dev = obj->dev;
1236 struct drm_gem_mm *mm = dev->mm_private;
23010e43 1237 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
de151cf6 1238 struct drm_map_list *list;
f77d390c 1239 struct drm_local_map *map;
de151cf6
JB		 1240 int ret = 0;
1241
1242 /* Set the object up for mmap'ing */
1243 list = &obj->map_list;
9a298b2a 1244 list->map = kzalloc(sizeof(struct drm_map_list), GFP_KERNEL);
de151cf6
JB		 1245 if (!list->map)
1246 return -ENOMEM;
1247
1248 map = list->map;
1249 map->type = _DRM_GEM;
1250 map->size = obj->size;
1251 map->handle = obj;
1252
1253 /* Get a DRM GEM mmap offset allocated... */
1254 list->file_offset_node = drm_mm_search_free(&mm->offset_manager,
1255 obj->size / PAGE_SIZE, 0, 0);
1256 if (!list->file_offset_node) {
1257 DRM_ERROR("failed to allocate offset for bo %d\n", obj->name);
1258 ret = -ENOMEM;
1259 goto out_free_list;
1260 }
1261
1262 list->file_offset_node = drm_mm_get_block(list->file_offset_node,
1263 obj->size / PAGE_SIZE, 0);
1264 if (!list->file_offset_node) {
1265 ret = -ENOMEM;
1266 goto out_free_list;
1267 }
1268
1269 list->hash.key = list->file_offset_node->start;
1270 if (drm_ht_insert_item(&mm->offset_hash, &list->hash)) {
1271 DRM_ERROR("failed to add to map hash\n");
5618ca6a 1272 ret = -ENOMEM;
de151cf6
JB		 1273 goto out_free_mm;
1274 }
1275
1276 /* By now we should be all set, any drm_mmap request on the offset
1277 * below will get to our mmap & fault handler */
1278 obj_priv->mmap_offset = ((uint64_t) list->hash.key) << PAGE_SHIFT;
1279
1280 return 0;
1281
1282out_free_mm:
1283 drm_mm_put_block(list->file_offset_node);
1284out_free_list:
9a298b2a 1285 kfree(list->map);
de151cf6
JB		 1286
1287 return ret;
1288}
1289
901782b2
CW		 1290/**
1291 * i915_gem_release_mmap - remove physical page mappings
1292 * @obj: obj in question
1293 *
af901ca1 1294 * Preserve the reservation of the mmapping with the DRM core code, but
901782b2
CW		 1295 * relinquish ownership of the pages back to the system.
1296 *
1297 * It is vital that we remove the page mapping if we have mapped a tiled
1298 * object through the GTT and then lose the fence register due to
1299 * resource pressure. Similarly if the object has been moved out of the
1300 * aperture, than pages mapped into userspace must be revoked. Removing the
1301 * mapping will then trigger a page fault on the next user access, allowing
1302 * fixup by i915_gem_fault().
1303 */
d05ca301 1304void
901782b2
CW		 1305i915_gem_release_mmap(struct drm_gem_object *obj)
1306{
1307 struct drm_device *dev = obj->dev;
23010e43 1308 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
901782b2
CW		 1309
1310 if (dev->dev_mapping)
1311 unmap_mapping_range(dev->dev_mapping,
1312 obj_priv->mmap_offset, obj->size, 1);
1313}
1314
ab00b3e5
JB		 1315static void
1316i915_gem_free_mmap_offset(struct drm_gem_object *obj)
1317{
1318 struct drm_device *dev = obj->dev;
23010e43 1319 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
ab00b3e5
JB		 1320 struct drm_gem_mm *mm = dev->mm_private;
1321 struct drm_map_list *list;
1322
1323 list = &obj->map_list;
1324 drm_ht_remove_item(&mm->offset_hash, &list->hash);
1325
1326 if (list->file_offset_node) {
1327 drm_mm_put_block(list->file_offset_node);
1328 list->file_offset_node = NULL;
1329 }
1330
1331 if (list->map) {
9a298b2a 1332 kfree(list->map);
ab00b3e5
JB		 1333 list->map = NULL;
1334 }
1335
1336 obj_priv->mmap_offset = 0;
1337}
1338
de151cf6
JB		 1339/**
1340 * i915_gem_get_gtt_alignment - return required GTT alignment for an object
1341 * @obj: object to check
1342 *
1343 * Return the required GTT alignment for an object, taking into account
1344 * potential fence register mapping if needed.
1345 */
1346static uint32_t
1347i915_gem_get_gtt_alignment(struct drm_gem_object *obj)
1348{
1349 struct drm_device *dev = obj->dev;
23010e43 1350 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
de151cf6
JB		 1351 int start, i;
1352
1353 /*
1354 * Minimum alignment is 4k (GTT page size), but might be greater
1355 * if a fence register is needed for the object.
1356 */
1357 if (IS_I965G(dev) || obj_priv->tiling_mode == I915_TILING_NONE)
1358 return 4096;
1359
1360 /*
1361 * Previous chips need to be aligned to the size of the smallest
1362 * fence register that can contain the object.
1363 */
1364 if (IS_I9XX(dev))
1365 start = 1024*1024;
1366 else
1367 start = 512*1024;
1368
1369 for (i = start; i < obj->size; i <<= 1)
1370 ;
1371
1372 return i;
1373}
1374
1375/**
1376 * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
1377 * @dev: DRM device
1378 * @data: GTT mapping ioctl data
1379 * @file_priv: GEM object info
1380 *
1381 * Simply returns the fake offset to userspace so it can mmap it.
1382 * The mmap call will end up in drm_gem_mmap(), which will set things
1383 * up so we can get faults in the handler above.
1384 *
1385 * The fault handler will take care of binding the object into the GTT
1386 * (since it may have been evicted to make room for something), allocating
1387 * a fence register, and mapping the appropriate aperture address into
1388 * userspace.
1389 */
1390int
1391i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
1392 struct drm_file *file_priv)
1393{
1394 struct drm_i915_gem_mmap_gtt *args = data;
1395 struct drm_i915_private *dev_priv = dev->dev_private;
1396 struct drm_gem_object *obj;
1397 struct drm_i915_gem_object *obj_priv;
1398 int ret;
1399
1400 if (!(dev->driver->driver_features & DRIVER_GEM))
1401 return -ENODEV;
1402
1403 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
1404 if (obj == NULL)
1405 return -EBADF;
1406
1407 mutex_lock(&dev->struct_mutex);
1408
23010e43 1409 obj_priv = to_intel_bo(obj);
de151cf6 1410
ab18282d
CW		 1411 if (obj_priv->madv != I915_MADV_WILLNEED) {
1412 DRM_ERROR("Attempting to mmap a purgeable buffer\n");
1413 drm_gem_object_unreference(obj);
1414 mutex_unlock(&dev->struct_mutex);
1415 return -EINVAL;
1416 }
1417
1418
de151cf6
JB		 1419 if (!obj_priv->mmap_offset) {
1420 ret = i915_gem_create_mmap_offset(obj);
13af1062
CW		 1421 if (ret) {
1422 drm_gem_object_unreference(obj);
1423 mutex_unlock(&dev->struct_mutex);
de151cf6 1424 return ret;
13af1062 1425 }
de151cf6
JB		 1426 }
1427
1428 args->offset = obj_priv->mmap_offset;
1429
de151cf6
JB		 1430 /*
1431 * Pull it into the GTT so that we have a page list (makes the
1432 * initial fault faster and any subsequent flushing possible).
1433 */
1434 if (!obj_priv->agp_mem) {
e67b8ce1 1435 ret = i915_gem_object_bind_to_gtt(obj, 0);
de151cf6
JB		 1436 if (ret) {
1437 drm_gem_object_unreference(obj);
1438 mutex_unlock(&dev->struct_mutex);
1439 return ret;
1440 }
14b60391 1441 list_add_tail(&obj_priv->list, &dev_priv->mm.inactive_list);
de151cf6
JB		 1442 }
1443
1444 drm_gem_object_unreference(obj);
1445 mutex_unlock(&dev->struct_mutex);
1446
1447 return 0;
1448}
1449
6911a9b8 1450void
856fa198 1451i915_gem_object_put_pages(struct drm_gem_object *obj)
673a394b 1452{
23010e43 1453 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
673a394b
EA		 1454 int page_count = obj->size / PAGE_SIZE;
1455 int i;
1456
856fa198 1457 BUG_ON(obj_priv->pages_refcount == 0);
bb6baf76 1458 BUG_ON(obj_priv->madv == __I915_MADV_PURGED);
673a394b 1459
856fa198
EA		 1460 if (--obj_priv->pages_refcount != 0)
1461 return;
673a394b 1462
280b713b
EA		 1463 if (obj_priv->tiling_mode != I915_TILING_NONE)
1464 i915_gem_object_save_bit_17_swizzle(obj);
1465
3ef94daa 1466 if (obj_priv->madv == I915_MADV_DONTNEED)
13a05fd9 1467 obj_priv->dirty = 0;
3ef94daa
CW		 1468
1469 for (i = 0; i < page_count; i++) {
3ef94daa
CW		 1470 if (obj_priv->dirty)
1471 set_page_dirty(obj_priv->pages[i]);
1472
1473 if (obj_priv->madv == I915_MADV_WILLNEED)
856fa198 1474 mark_page_accessed(obj_priv->pages[i]);
3ef94daa
CW		 1475
1476 page_cache_release(obj_priv->pages[i]);
1477 }
673a394b
EA		 1478 obj_priv->dirty = 0;
1479
8e7d2b2c 1480 drm_free_large(obj_priv->pages);
856fa198 1481 obj_priv->pages = NULL;
673a394b
EA		 1482}
1483
1484static void
852835f3
ZN		 1485i915_gem_object_move_to_active(struct drm_gem_object *obj, uint32_t seqno,
1486 struct intel_ring_buffer *ring)
673a394b
EA		 1487{
1488 struct drm_device *dev = obj->dev;
1489 drm_i915_private_t *dev_priv = dev->dev_private;
23010e43 1490 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
852835f3
ZN		 1491 BUG_ON(ring == NULL);
1492 obj_priv->ring = ring;
673a394b
EA		 1493
1494 /* Add a reference if we're newly entering the active list. */
1495 if (!obj_priv->active) {
1496 drm_gem_object_reference(obj);
1497 obj_priv->active = 1;
1498 }
1499 /* Move from whatever list we were on to the tail of execution. */
5e118f41 1500 spin_lock(&dev_priv->mm.active_list_lock);
852835f3 1501 list_move_tail(&obj_priv->list, &ring->active_list);
5e118f41 1502 spin_unlock(&dev_priv->mm.active_list_lock);
ce44b0ea 1503 obj_priv->last_rendering_seqno = seqno;
673a394b
EA		 1504}
1505
ce44b0ea
EA		 1506static void
1507i915_gem_object_move_to_flushing(struct drm_gem_object *obj)
1508{
1509 struct drm_device *dev = obj->dev;
1510 drm_i915_private_t *dev_priv = dev->dev_private;
23010e43 1511 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
ce44b0ea
EA		 1512
1513 BUG_ON(!obj_priv->active);
1514 list_move_tail(&obj_priv->list, &dev_priv->mm.flushing_list);
1515 obj_priv->last_rendering_seqno = 0;
1516}
673a394b 1517
963b4836
CW		 1518/* Immediately discard the backing storage */
1519static void
1520i915_gem_object_truncate(struct drm_gem_object *obj)
1521{
23010e43 1522 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
bb6baf76 1523 struct inode *inode;
963b4836 1524
bb6baf76
CW		 1525 inode = obj->filp->f_path.dentry->d_inode;
1526 if (inode->i_op->truncate)
1527 inode->i_op->truncate (inode);
1528
1529 obj_priv->madv = __I915_MADV_PURGED;
963b4836
CW		 1530}
1531
1532static inline int
1533i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj_priv)
1534{
1535 return obj_priv->madv == I915_MADV_DONTNEED;
1536}
1537
673a394b
EA		 1538static void
1539i915_gem_object_move_to_inactive(struct drm_gem_object *obj)
1540{
1541 struct drm_device *dev = obj->dev;
1542 drm_i915_private_t *dev_priv = dev->dev_private;
23010e43 1543 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
673a394b
EA		 1544
1545 i915_verify_inactive(dev, __FILE__, __LINE__);
1546 if (obj_priv->pin_count != 0)
1547 list_del_init(&obj_priv->list);
1548 else
1549 list_move_tail(&obj_priv->list, &dev_priv->mm.inactive_list);
1550
99fcb766
DV		 1551 BUG_ON(!list_empty(&obj_priv->gpu_write_list));
1552
ce44b0ea 1553 obj_priv->last_rendering_seqno = 0;
852835f3 1554 obj_priv->ring = NULL;
673a394b
EA		 1555 if (obj_priv->active) {
1556 obj_priv->active = 0;
1557 drm_gem_object_unreference(obj);
1558 }
1559 i915_verify_inactive(dev, __FILE__, __LINE__);
1560}
1561
63560396
DV		 1562static void
1563i915_gem_process_flushing_list(struct drm_device *dev,
852835f3
ZN		 1564 uint32_t flush_domains, uint32_t seqno,
1565 struct intel_ring_buffer *ring)
63560396
DV		 1566{
1567 drm_i915_private_t *dev_priv = dev->dev_private;
1568 struct drm_i915_gem_object *obj_priv, *next;
1569
1570 list_for_each_entry_safe(obj_priv, next,
1571 &dev_priv->mm.gpu_write_list,
1572 gpu_write_list) {
a8089e84 1573 struct drm_gem_object *obj = &obj_priv->base;
63560396
DV		 1574
1575 if ((obj->write_domain & flush_domains) ==
852835f3
ZN		 1576 obj->write_domain &&
1577 obj_priv->ring->ring_flag == ring->ring_flag) {
63560396
DV		 1578 uint32_t old_write_domain = obj->write_domain;
1579
1580 obj->write_domain = 0;
1581 list_del_init(&obj_priv->gpu_write_list);
852835f3 1582 i915_gem_object_move_to_active(obj, seqno, ring);
63560396
DV		 1583
1584 /* update the fence lru list */
007cc8ac
DV		 1585 if (obj_priv->fence_reg != I915_FENCE_REG_NONE) {
1586 struct drm_i915_fence_reg *reg =
1587 &dev_priv->fence_regs[obj_priv->fence_reg];
1588 list_move_tail(&reg->lru_list,
63560396 1589 &dev_priv->mm.fence_list);
007cc8ac 1590 }
63560396
DV		 1591
1592 trace_i915_gem_object_change_domain(obj,
1593 obj->read_domains,
1594 old_write_domain);
1595 }
1596 }
1597}
8187a2b7 1598
5a5a0c64 1599uint32_t
b962442e 1600i915_add_request(struct drm_device *dev, struct drm_file *file_priv,
852835f3 1601 uint32_t flush_domains, struct intel_ring_buffer *ring)
673a394b
EA		 1602{
1603 drm_i915_private_t *dev_priv = dev->dev_private;
b962442e 1604 struct drm_i915_file_private *i915_file_priv = NULL;
673a394b
EA		 1605 struct drm_i915_gem_request *request;
1606 uint32_t seqno;
1607 int was_empty;
673a394b 1608
b962442e
EA		 1609 if (file_priv != NULL)
1610 i915_file_priv = file_priv->driver_priv;
1611
9a298b2a 1612 request = kzalloc(sizeof(*request), GFP_KERNEL);
673a394b
EA		 1613 if (request == NULL)
1614 return 0;
1615
852835f3 1616 seqno = ring->add_request(dev, ring, file_priv, flush_domains);
673a394b
EA		 1617
1618 request->seqno = seqno;
852835f3 1619 request->ring = ring;
673a394b 1620 request->emitted_jiffies = jiffies;
852835f3
ZN		 1621 was_empty = list_empty(&ring->request_list);
1622 list_add_tail(&request->list, &ring->request_list);
1623
b962442e
EA		 1624 if (i915_file_priv) {
1625 list_add_tail(&request->client_list,
1626 &i915_file_priv->mm.request_list);
1627 } else {
1628 INIT_LIST_HEAD(&request->client_list);
1629 }
673a394b 1630
ce44b0ea
EA		 1631 /* Associate any objects on the flushing list matching the write
1632 * domain we're flushing with our flush.
1633 */
63560396 1634 if (flush_domains != 0)
852835f3 1635 i915_gem_process_flushing_list(dev, flush_domains, seqno, ring);
ce44b0ea 1636
f65d9421
BG		 1637 if (!dev_priv->mm.suspended) {
1638 mod_timer(&dev_priv->hangcheck_timer, jiffies + DRM_I915_HANGCHECK_PERIOD);
1639 if (was_empty)
1640 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ);
1641 }
673a394b
EA		 1642 return seqno;
1643}
1644
1645/**
1646 * Command execution barrier
1647 *
1648 * Ensures that all commands in the ring are finished
1649 * before signalling the CPU
1650 */
3043c60c 1651static uint32_t
852835f3 1652i915_retire_commands(struct drm_device *dev, struct intel_ring_buffer *ring)
673a394b 1653{
673a394b 1654 uint32_t flush_domains = 0;
673a394b
EA		 1655
1656 /* The sampler always gets flushed on i965 (sigh) */
1657 if (IS_I965G(dev))
1658 flush_domains |= I915_GEM_DOMAIN_SAMPLER;
852835f3
ZN		 1659
1660 ring->flush(dev, ring,
1661 I915_GEM_DOMAIN_COMMAND, flush_domains);
673a394b
EA		 1662 return flush_domains;
1663}
1664
1665/**
1666 * Moves buffers associated only with the given active seqno from the active
1667 * to inactive list, potentially freeing them.
1668 */
1669static void
1670i915_gem_retire_request(struct drm_device *dev,
1671 struct drm_i915_gem_request *request)
1672{
1673 drm_i915_private_t *dev_priv = dev->dev_private;
1674
1c5d22f7
CW		 1675 trace_i915_gem_request_retire(dev, request->seqno);
1676
673a394b
EA		 1677 /* Move any buffers on the active list that are no longer referenced
1678 * by the ringbuffer to the flushing/inactive lists as appropriate.
1679 */
5e118f41 1680 spin_lock(&dev_priv->mm.active_list_lock);
852835f3 1681 while (!list_empty(&request->ring->active_list)) {
673a394b
EA		 1682 struct drm_gem_object *obj;
1683 struct drm_i915_gem_object *obj_priv;
1684
852835f3 1685 obj_priv = list_first_entry(&request->ring->active_list,
673a394b
EA		 1686 struct drm_i915_gem_object,
1687 list);
a8089e84 1688 obj = &obj_priv->base;
673a394b
EA		 1689
1690 /* If the seqno being retired doesn't match the oldest in the
1691 * list, then the oldest in the list must still be newer than
1692 * this seqno.
1693 */
1694 if (obj_priv->last_rendering_seqno != request->seqno)
5e118f41 1695 goto out;
de151cf6 1696
673a394b
EA		 1697#if WATCH_LRU
1698 DRM_INFO("%s: retire %d moves to inactive list %p\n",
1699 __func__, request->seqno, obj);
1700#endif
1701
ce44b0ea
EA		 1702 if (obj->write_domain != 0)
1703 i915_gem_object_move_to_flushing(obj);
68c84342
SL		 1704 else {
1705 /* Take a reference on the object so it won't be
1706 * freed while the spinlock is held. The list
1707 * protection for this spinlock is safe when breaking
1708 * the lock like this since the next thing we do
1709 * is just get the head of the list again.
1710 */
1711 drm_gem_object_reference(obj);
673a394b 1712 i915_gem_object_move_to_inactive(obj);
68c84342
SL		 1713 spin_unlock(&dev_priv->mm.active_list_lock);
1714 drm_gem_object_unreference(obj);
1715 spin_lock(&dev_priv->mm.active_list_lock);
1716 }
673a394b 1717 }
5e118f41
CW		 1718out:
1719 spin_unlock(&dev_priv->mm.active_list_lock);
673a394b
EA		 1720}
1721
1722/**
1723 * Returns true if seq1 is later than seq2.
1724 */
22be1724 1725bool
673a394b
EA		 1726i915_seqno_passed(uint32_t seq1, uint32_t seq2)
1727{
1728 return (int32_t)(seq1 - seq2) >= 0;
1729}
1730
1731uint32_t
852835f3 1732i915_get_gem_seqno(struct drm_device *dev,
d1b851fc 1733 struct intel_ring_buffer *ring)
673a394b 1734{
852835f3 1735 return ring->get_gem_seqno(dev, ring);
673a394b
EA		 1736}
1737
1738/**
1739 * This function clears the request list as sequence numbers are passed.
1740 */
1741void
852835f3
ZN		 1742i915_gem_retire_requests(struct drm_device *dev,
1743 struct intel_ring_buffer *ring)
673a394b
EA		 1744{
1745 drm_i915_private_t *dev_priv = dev->dev_private;
1746 uint32_t seqno;
1747
8187a2b7 1748 if (!ring->status_page.page_addr
852835f3 1749 || list_empty(&ring->request_list))
6c0594a3
KW		 1750 return;
1751
852835f3 1752 seqno = i915_get_gem_seqno(dev, ring);
673a394b 1753
852835f3 1754 while (!list_empty(&ring->request_list)) {
673a394b
EA		 1755 struct drm_i915_gem_request *request;
1756 uint32_t retiring_seqno;
1757
852835f3 1758 request = list_first_entry(&ring->request_list,
673a394b
EA		 1759 struct drm_i915_gem_request,
1760 list);
1761 retiring_seqno = request->seqno;
1762
1763 if (i915_seqno_passed(seqno, retiring_seqno) ||
ba1234d1 1764 atomic_read(&dev_priv->mm.wedged)) {
673a394b
EA		 1765 i915_gem_retire_request(dev, request);
1766
1767 list_del(&request->list);
b962442e 1768 list_del(&request->client_list);
9a298b2a 1769 kfree(request);
673a394b
EA		 1770 } else
1771 break;
1772 }
9d34e5db
CW		 1773
1774 if (unlikely (dev_priv->trace_irq_seqno &&
1775 i915_seqno_passed(dev_priv->trace_irq_seqno, seqno))) {
8187a2b7
ZN		 1776
1777 ring->user_irq_put(dev, ring);
9d34e5db
CW		 1778 dev_priv->trace_irq_seqno = 0;
1779 }
673a394b
EA		 1780}
1781
1782void
1783i915_gem_retire_work_handler(struct work_struct *work)
1784{
1785 drm_i915_private_t *dev_priv;
1786 struct drm_device *dev;
1787
1788 dev_priv = container_of(work, drm_i915_private_t,
1789 mm.retire_work.work);
1790 dev = dev_priv->dev;
1791
1792 mutex_lock(&dev->struct_mutex);
852835f3
ZN		 1793 i915_gem_retire_requests(dev, &dev_priv->render_ring);
1794
d1b851fc
ZN		 1795 if (HAS_BSD(dev))
1796 i915_gem_retire_requests(dev, &dev_priv->bsd_ring);
1797
6dbe2772 1798 if (!dev_priv->mm.suspended &&
d1b851fc
ZN		 1799 (!list_empty(&dev_priv->render_ring.request_list) ||
1800 (HAS_BSD(dev) &&
1801 !list_empty(&dev_priv->bsd_ring.request_list))))
9c9fe1f8 1802 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ);
673a394b
EA		 1803 mutex_unlock(&dev->struct_mutex);
1804}
1805
5a5a0c64 1806int
852835f3
ZN		 1807i915_do_wait_request(struct drm_device *dev, uint32_t seqno,
1808 int interruptible, struct intel_ring_buffer *ring)
673a394b
EA		 1809{
1810 drm_i915_private_t *dev_priv = dev->dev_private;
802c7eb6 1811 u32 ier;
673a394b
EA		 1812 int ret = 0;
1813
1814 BUG_ON(seqno == 0);
1815
ba1234d1 1816 if (atomic_read(&dev_priv->mm.wedged))
ffed1d09
BG		 1817 return -EIO;
1818
852835f3 1819 if (!i915_seqno_passed(ring->get_gem_seqno(dev, ring), seqno)) {
bad720ff 1820 if (HAS_PCH_SPLIT(dev))
036a4a7d
ZW		 1821 ier = I915_READ(DEIER) | I915_READ(GTIER);
1822 else
1823 ier = I915_READ(IER);
802c7eb6
JB		 1824 if (!ier) {
1825 DRM_ERROR("something (likely vbetool) disabled "
1826 "interrupts, re-enabling\n");
1827 i915_driver_irq_preinstall(dev);
1828 i915_driver_irq_postinstall(dev);
1829 }
1830
1c5d22f7
CW		 1831 trace_i915_gem_request_wait_begin(dev, seqno);
1832
852835f3 1833 ring->waiting_gem_seqno = seqno;
8187a2b7 1834 ring->user_irq_get(dev, ring);
48764bf4 1835 if (interruptible)
852835f3
ZN		 1836 ret = wait_event_interruptible(ring->irq_queue,
1837 i915_seqno_passed(
1838 ring->get_gem_seqno(dev, ring), seqno)
1839 || atomic_read(&dev_priv->mm.wedged));
48764bf4 1840 else
852835f3
ZN		 1841 wait_event(ring->irq_queue,
1842 i915_seqno_passed(
1843 ring->get_gem_seqno(dev, ring), seqno)
1844 || atomic_read(&dev_priv->mm.wedged));
48764bf4 1845
8187a2b7 1846 ring->user_irq_put(dev, ring);
852835f3 1847 ring->waiting_gem_seqno = 0;
1c5d22f7
CW		 1848
1849 trace_i915_gem_request_wait_end(dev, seqno);
673a394b 1850 }
ba1234d1 1851 if (atomic_read(&dev_priv->mm.wedged))
673a394b
EA		 1852 ret = -EIO;
1853
1854 if (ret && ret != -ERESTARTSYS)
1855 DRM_ERROR("%s returns %d (awaiting %d at %d)\n",
852835f3 1856 __func__, ret, seqno, ring->get_gem_seqno(dev, ring));
673a394b
EA		 1857
1858 /* Directly dispatch request retiring. While we have the work queue
1859 * to handle this, the waiter on a request often wants an associated
1860 * buffer to have made it to the inactive list, and we would need
1861 * a separate wait queue to handle that.
1862 */
1863 if (ret == 0)
852835f3 1864 i915_gem_retire_requests(dev, ring);
673a394b
EA		 1865
1866 return ret;
1867}
1868
48764bf4
DV		 1869/**
1870 * Waits for a sequence number to be signaled, and cleans up the
1871 * request and object lists appropriately for that event.
1872 */
1873static int
852835f3
ZN		 1874i915_wait_request(struct drm_device *dev, uint32_t seqno,
1875 struct intel_ring_buffer *ring)
48764bf4 1876{
852835f3 1877 return i915_do_wait_request(dev, seqno, 1, ring);
48764bf4
DV		 1878}
1879
8187a2b7
ZN		 1880static void
1881i915_gem_flush(struct drm_device *dev,
1882 uint32_t invalidate_domains,
1883 uint32_t flush_domains)
1884{
1885 drm_i915_private_t *dev_priv = dev->dev_private;
1886 if (flush_domains & I915_GEM_DOMAIN_CPU)
1887 drm_agp_chipset_flush(dev);
1888 dev_priv->render_ring.flush(dev, &dev_priv->render_ring,
1889 invalidate_domains,
1890 flush_domains);
d1b851fc
ZN		 1891
1892 if (HAS_BSD(dev))
1893 dev_priv->bsd_ring.flush(dev, &dev_priv->bsd_ring,
1894 invalidate_domains,
1895 flush_domains);
8187a2b7
ZN		 1896}
1897
852835f3
ZN		 1898static void
1899i915_gem_flush_ring(struct drm_device *dev,
1900 uint32_t invalidate_domains,
1901 uint32_t flush_domains,
1902 struct intel_ring_buffer *ring)
1903{
1904 if (flush_domains & I915_GEM_DOMAIN_CPU)
1905 drm_agp_chipset_flush(dev);
1906 ring->flush(dev, ring,
1907 invalidate_domains,
1908 flush_domains);
1909}
1910
673a394b
EA		 1911/**
1912 * Ensures that all rendering to the object has completed and the object is
1913 * safe to unbind from the GTT or access from the CPU.
1914 */
1915static int
1916i915_gem_object_wait_rendering(struct drm_gem_object *obj)
1917{
1918 struct drm_device *dev = obj->dev;
23010e43 1919 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
673a394b
EA		 1920 int ret;
1921
e47c68e9
EA		 1922 /* This function only exists to support waiting for existing rendering,
1923 * not for emitting required flushes.
673a394b 1924 */
e47c68e9 1925 BUG_ON((obj->write_domain & I915_GEM_GPU_DOMAINS) != 0);
673a394b
EA		 1926
1927 /* If there is rendering queued on the buffer being evicted, wait for
1928 * it.
1929 */
1930 if (obj_priv->active) {
1931#if WATCH_BUF
1932 DRM_INFO("%s: object %p wait for seqno %08x\n",
1933 __func__, obj, obj_priv->last_rendering_seqno);
1934#endif
852835f3
ZN		 1935 ret = i915_wait_request(dev,
1936 obj_priv->last_rendering_seqno, obj_priv->ring);
673a394b
EA		 1937 if (ret != 0)
1938 return ret;
1939 }
1940
1941 return 0;
1942}
1943
1944/**
1945 * Unbinds an object from the GTT aperture.
1946 */
0f973f27 1947int
673a394b
EA		 1948i915_gem_object_unbind(struct drm_gem_object *obj)
1949{
1950 struct drm_device *dev = obj->dev;
4a87b8ca 1951 drm_i915_private_t *dev_priv = dev->dev_private;
23010e43 1952 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
673a394b
EA		 1953 int ret = 0;
1954
1955#if WATCH_BUF
1956 DRM_INFO("%s:%d %p\n", __func__, __LINE__, obj);
1957 DRM_INFO("gtt_space %p\n", obj_priv->gtt_space);
1958#endif
1959 if (obj_priv->gtt_space == NULL)
1960 return 0;
1961
1962 if (obj_priv->pin_count != 0) {
1963 DRM_ERROR("Attempting to unbind pinned buffer\n");
1964 return -EINVAL;
1965 }
1966
5323fd04
EA		 1967 /* blow away mappings if mapped through GTT */
1968 i915_gem_release_mmap(obj);
1969
673a394b
EA		 1970 /* Move the object to the CPU domain to ensure that
1971 * any possible CPU writes while it's not in the GTT
1972 * are flushed when we go to remap it. This will
1973 * also ensure that all pending GPU writes are finished
1974 * before we unbind.
1975 */
e47c68e9 1976 ret = i915_gem_object_set_to_cpu_domain(obj, 1);
673a394b 1977 if (ret) {
e47c68e9
EA		 1978 if (ret != -ERESTARTSYS)
1979 DRM_ERROR("set_domain failed: %d\n", ret);
673a394b
EA		 1980 return ret;
1981 }
1982
5323fd04
EA		 1983 BUG_ON(obj_priv->active);
1984
96b47b65
DV		 1985 /* release the fence reg _after_ flushing */
1986 if (obj_priv->fence_reg != I915_FENCE_REG_NONE)
1987 i915_gem_clear_fence_reg(obj);
1988
673a394b
EA		 1989 if (obj_priv->agp_mem != NULL) {
1990 drm_unbind_agp(obj_priv->agp_mem);
1991 drm_free_agp(obj_priv->agp_mem, obj->size / PAGE_SIZE);
1992 obj_priv->agp_mem = NULL;
1993 }
1994
856fa198 1995 i915_gem_object_put_pages(obj);
a32808c0 1996 BUG_ON(obj_priv->pages_refcount);
673a394b
EA		 1997
1998 if (obj_priv->gtt_space) {
1999 atomic_dec(&dev->gtt_count);
2000 atomic_sub(obj->size, &dev->gtt_memory);
2001
2002 drm_mm_put_block(obj_priv->gtt_space);
2003 obj_priv->gtt_space = NULL;
2004 }
2005
2006 /* Remove ourselves from the LRU list if present. */
4a87b8ca 2007 spin_lock(&dev_priv->mm.active_list_lock);
673a394b
EA		 2008 if (!list_empty(&obj_priv->list))
2009 list_del_init(&obj_priv->list);
4a87b8ca 2010 spin_unlock(&dev_priv->mm.active_list_lock);
673a394b 2011
963b4836
CW		 2012 if (i915_gem_object_is_purgeable(obj_priv))
2013 i915_gem_object_truncate(obj);
2014
1c5d22f7
CW		 2015 trace_i915_gem_object_unbind(obj);
2016
673a394b
EA		 2017 return 0;
2018}
2019
07f73f69
CW		 2020static struct drm_gem_object *
2021i915_gem_find_inactive_object(struct drm_device *dev, int min_size)
2022{
2023 drm_i915_private_t *dev_priv = dev->dev_private;
2024 struct drm_i915_gem_object *obj_priv;
2025 struct drm_gem_object *best = NULL;
2026 struct drm_gem_object *first = NULL;
2027
2028 /* Try to find the smallest clean object */
2029 list_for_each_entry(obj_priv, &dev_priv->mm.inactive_list, list) {
a8089e84 2030 struct drm_gem_object *obj = &obj_priv->base;
07f73f69 2031 if (obj->size >= min_size) {
963b4836
CW		 2032 if ((!obj_priv->dirty ||
2033 i915_gem_object_is_purgeable(obj_priv)) &&
07f73f69
CW		 2034 (!best || obj->size < best->size)) {
2035 best = obj;
2036 if (best->size == min_size)
2037 return best;
2038 }
2039 if (!first)
2040 first = obj;
2041 }
2042 }
2043
2044 return best ? best : first;
2045}
2046
4df2faf4
DV		 2047static int
2048i915_gpu_idle(struct drm_device *dev)
2049{
2050 drm_i915_private_t *dev_priv = dev->dev_private;
2051 bool lists_empty;
d1b851fc 2052 uint32_t seqno1, seqno2;
852835f3 2053 int ret;
4df2faf4
DV		 2054
2055 spin_lock(&dev_priv->mm.active_list_lock);
d1b851fc
ZN		 2056 lists_empty = (list_empty(&dev_priv->mm.flushing_list) &&
2057 list_empty(&dev_priv->render_ring.active_list) &&
2058 (!HAS_BSD(dev) ||
2059 list_empty(&dev_priv->bsd_ring.active_list)));
4df2faf4
DV		 2060 spin_unlock(&dev_priv->mm.active_list_lock);
2061
2062 if (lists_empty)
2063 return 0;
2064
2065 /* Flush everything onto the inactive list. */
2066 i915_gem_flush(dev, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
d1b851fc 2067 seqno1 = i915_add_request(dev, NULL, I915_GEM_GPU_DOMAINS,
852835f3 2068 &dev_priv->render_ring);
d1b851fc 2069 if (seqno1 == 0)
4df2faf4 2070 return -ENOMEM;
d1b851fc
ZN		 2071 ret = i915_wait_request(dev, seqno1, &dev_priv->render_ring);
2072
2073 if (HAS_BSD(dev)) {
2074 seqno2 = i915_add_request(dev, NULL, I915_GEM_GPU_DOMAINS,
2075 &dev_priv->bsd_ring);
2076 if (seqno2 == 0)
2077 return -ENOMEM;
2078
2079 ret = i915_wait_request(dev, seqno2, &dev_priv->bsd_ring);
2080 if (ret)
2081 return ret;
2082 }
2083
4df2faf4 2084
852835f3 2085 return ret;
4df2faf4
DV		 2086}
2087
673a394b 2088static int
07f73f69
CW		 2089i915_gem_evict_everything(struct drm_device *dev)
2090{
2091 drm_i915_private_t *dev_priv = dev->dev_private;
07f73f69
CW		 2092 int ret;
2093 bool lists_empty;
2094
07f73f69
CW		 2095 spin_lock(&dev_priv->mm.active_list_lock);
2096 lists_empty = (list_empty(&dev_priv->mm.inactive_list) &&
2097 list_empty(&dev_priv->mm.flushing_list) &&
d1b851fc
ZN		 2098 list_empty(&dev_priv->render_ring.active_list) &&
2099 (!HAS_BSD(dev)
2100 || list_empty(&dev_priv->bsd_ring.active_list)));
07f73f69
CW		 2101 spin_unlock(&dev_priv->mm.active_list_lock);
2102
9731129c 2103 if (lists_empty)
07f73f69 2104 return -ENOSPC;
07f73f69
CW		 2105
2106 /* Flush everything (on to the inactive lists) and evict */
4df2faf4 2107 ret = i915_gpu_idle(dev);
07f73f69
CW		 2108 if (ret)
2109 return ret;
2110
99fcb766
DV		 2111 BUG_ON(!list_empty(&dev_priv->mm.flushing_list));
2112
ab5ee576 2113 ret = i915_gem_evict_from_inactive_list(dev);
07f73f69
CW		 2114 if (ret)
2115 return ret;
2116
2117 spin_lock(&dev_priv->mm.active_list_lock);
2118 lists_empty = (list_empty(&dev_priv->mm.inactive_list) &&
2119 list_empty(&dev_priv->mm.flushing_list) &&
d1b851fc
ZN		 2120 list_empty(&dev_priv->render_ring.active_list) &&
2121 (!HAS_BSD(dev)
2122 || list_empty(&dev_priv->bsd_ring.active_list)));
07f73f69
CW		 2123 spin_unlock(&dev_priv->mm.active_list_lock);
2124 BUG_ON(!lists_empty);
2125
2126 return 0;
2127}
2128
673a394b 2129static int
07f73f69 2130i915_gem_evict_something(struct drm_device *dev, int min_size)
673a394b
EA		 2131{
2132 drm_i915_private_t *dev_priv = dev->dev_private;
2133 struct drm_gem_object *obj;
07f73f69 2134 int ret;
673a394b 2135
852835f3 2136 struct intel_ring_buffer *render_ring = &dev_priv->render_ring;
d1b851fc 2137 struct intel_ring_buffer *bsd_ring = &dev_priv->bsd_ring;
673a394b 2138 for (;;) {
852835f3 2139 i915_gem_retire_requests(dev, render_ring);
07f73f69 2140
d1b851fc
ZN		 2141 if (HAS_BSD(dev))
2142 i915_gem_retire_requests(dev, bsd_ring);
2143
673a394b
EA		 2144 /* If there's an inactive buffer available now, grab it
2145 * and be done.
2146 */
07f73f69
CW		 2147 obj = i915_gem_find_inactive_object(dev, min_size);
2148 if (obj) {
2149 struct drm_i915_gem_object *obj_priv;
2150
673a394b
EA		 2151#if WATCH_LRU
2152 DRM_INFO("%s: evicting %p\n", __func__, obj);
2153#endif
23010e43 2154 obj_priv = to_intel_bo(obj);
07f73f69 2155 BUG_ON(obj_priv->pin_count != 0);
673a394b
EA		 2156 BUG_ON(obj_priv->active);
2157
2158 /* Wait on the rendering and unbind the buffer. */
07f73f69 2159 return i915_gem_object_unbind(obj);
673a394b
EA		 2160 }
2161
2162 /* If we didn't get anything, but the ring is still processing
07f73f69
CW		 2163 * things, wait for the next to finish and hopefully leave us
2164 * a buffer to evict.
673a394b 2165 */
852835f3 2166 if (!list_empty(&render_ring->request_list)) {
673a394b
EA		 2167 struct drm_i915_gem_request *request;
2168
852835f3 2169 request = list_first_entry(&render_ring->request_list,
673a394b
EA		 2170 struct drm_i915_gem_request,
2171 list);
2172
852835f3
ZN		 2173 ret = i915_wait_request(dev,
2174 request->seqno, request->ring);
673a394b 2175 if (ret)
07f73f69 2176 return ret;
673a394b 2177
07f73f69 2178 continue;
673a394b
EA		 2179 }
2180
d1b851fc
ZN		 2181 if (HAS_BSD(dev) && !list_empty(&bsd_ring->request_list)) {
2182 struct drm_i915_gem_request *request;
2183
2184 request = list_first_entry(&bsd_ring->request_list,
2185 struct drm_i915_gem_request,
2186 list);
2187
2188 ret = i915_wait_request(dev,
2189 request->seqno, request->ring);
2190 if (ret)
2191 return ret;
2192
2193 continue;
2194 }
2195
673a394b
EA		 2196 /* If we didn't have anything on the request list but there
2197 * are buffers awaiting a flush, emit one and try again.
2198 * When we wait on it, those buffers waiting for that flush
2199 * will get moved to inactive.
2200 */
2201 if (!list_empty(&dev_priv->mm.flushing_list)) {
07f73f69 2202 struct drm_i915_gem_object *obj_priv;
673a394b 2203
9a1e2582
CW		 2204 /* Find an object that we can immediately reuse */
2205 list_for_each_entry(obj_priv, &dev_priv->mm.flushing_list, list) {
a8089e84 2206 obj = &obj_priv->base;
9a1e2582
CW		 2207 if (obj->size >= min_size)
2208 break;
673a394b 2209
9a1e2582
CW		 2210 obj = NULL;
2211 }
673a394b 2212
9a1e2582
CW		 2213 if (obj != NULL) {
2214 uint32_t seqno;
673a394b 2215
852835f3
ZN		 2216 i915_gem_flush_ring(dev,
2217 obj->write_domain,
9a1e2582 2218 obj->write_domain,
852835f3
ZN		 2219 obj_priv->ring);
2220 seqno = i915_add_request(dev, NULL,
2221 obj->write_domain,
2222 obj_priv->ring);
9a1e2582
CW		 2223 if (seqno == 0)
2224 return -ENOMEM;
9a1e2582
CW		 2225 continue;
2226 }
673a394b
EA		 2227 }
2228
07f73f69
CW		 2229 /* If we didn't do any of the above, there's no single buffer
2230 * large enough to swap out for the new one, so just evict
2231 * everything and start again. (This should be rare.)
673a394b 2232 */
9731129c 2233 if (!list_empty (&dev_priv->mm.inactive_list))
ab5ee576 2234 return i915_gem_evict_from_inactive_list(dev);
9731129c 2235 else
07f73f69 2236 return i915_gem_evict_everything(dev);
ac94a962 2237 }
ac94a962
KP		 2238}
2239
6911a9b8 2240int
4bdadb97
CW		 2241i915_gem_object_get_pages(struct drm_gem_object *obj,
2242 gfp_t gfpmask)
673a394b 2243{
23010e43 2244 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
673a394b
EA		 2245 int page_count, i;
2246 struct address_space *mapping;
2247 struct inode *inode;
2248 struct page *page;
673a394b 2249
856fa198 2250 if (obj_priv->pages_refcount++ != 0)
673a394b
EA		 2251 return 0;
2252
2253 /* Get the list of pages out of our struct file. They'll be pinned
2254 * at this point until we release them.
2255 */
2256 page_count = obj->size / PAGE_SIZE;
856fa198 2257 BUG_ON(obj_priv->pages != NULL);
8e7d2b2c 2258 obj_priv->pages = drm_calloc_large(page_count, sizeof(struct page *));
856fa198 2259 if (obj_priv->pages == NULL) {
856fa198 2260 obj_priv->pages_refcount--;
673a394b
EA		 2261 return -ENOMEM;
2262 }
2263
2264 inode = obj->filp->f_path.dentry->d_inode;
2265 mapping = inode->i_mapping;
2266 for (i = 0; i < page_count; i++) {
4bdadb97
CW		 2267 page = read_cache_page_gfp(mapping, i,
2268 mapping_gfp_mask (mapping) |
2269 __GFP_COLD |
2270 gfpmask);
1f2b1013
CW		 2271 if (IS_ERR(page))
2272 goto err_pages;
2273
856fa198 2274 obj_priv->pages[i] = page;
673a394b 2275 }
280b713b
EA		 2276
2277 if (obj_priv->tiling_mode != I915_TILING_NONE)
2278 i915_gem_object_do_bit_17_swizzle(obj);
2279
673a394b 2280 return 0;
1f2b1013
CW		 2281
2282err_pages:
2283 while (i--)
2284 page_cache_release(obj_priv->pages[i]);
2285
2286 drm_free_large(obj_priv->pages);
2287 obj_priv->pages = NULL;
2288 obj_priv->pages_refcount--;
2289 return PTR_ERR(page);
673a394b
EA		 2290}
2291
4e901fdc
EA		 2292static void sandybridge_write_fence_reg(struct drm_i915_fence_reg *reg)
2293{
2294 struct drm_gem_object *obj = reg->obj;
2295 struct drm_device *dev = obj->dev;
2296 drm_i915_private_t *dev_priv = dev->dev_private;
23010e43 2297 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
4e901fdc
EA		 2298 int regnum = obj_priv->fence_reg;
2299 uint64_t val;
2300
2301 val = (uint64_t)((obj_priv->gtt_offset + obj->size - 4096) &
2302 0xfffff000) << 32;
2303 val |= obj_priv->gtt_offset & 0xfffff000;
2304 val |= (uint64_t)((obj_priv->stride / 128) - 1) <<
2305 SANDYBRIDGE_FENCE_PITCH_SHIFT;
2306
2307 if (obj_priv->tiling_mode == I915_TILING_Y)
2308 val |= 1 << I965_FENCE_TILING_Y_SHIFT;
2309 val |= I965_FENCE_REG_VALID;
2310
2311 I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + (regnum * 8), val);
2312}
2313
de151cf6
JB		 2314static void i965_write_fence_reg(struct drm_i915_fence_reg *reg)
2315{
2316 struct drm_gem_object *obj = reg->obj;
2317 struct drm_device *dev = obj->dev;
2318 drm_i915_private_t *dev_priv = dev->dev_private;
23010e43 2319 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
de151cf6
JB		 2320 int regnum = obj_priv->fence_reg;
2321 uint64_t val;
2322
2323 val = (uint64_t)((obj_priv->gtt_offset + obj->size - 4096) &
2324 0xfffff000) << 32;
2325 val |= obj_priv->gtt_offset & 0xfffff000;
2326 val |= ((obj_priv->stride / 128) - 1) << I965_FENCE_PITCH_SHIFT;
2327 if (obj_priv->tiling_mode == I915_TILING_Y)
2328 val |= 1 << I965_FENCE_TILING_Y_SHIFT;
2329 val |= I965_FENCE_REG_VALID;
2330
2331 I915_WRITE64(FENCE_REG_965_0 + (regnum * 8), val);
2332}
2333
2334static void i915_write_fence_reg(struct drm_i915_fence_reg *reg)
2335{
2336 struct drm_gem_object *obj = reg->obj;
2337 struct drm_device *dev = obj->dev;
2338 drm_i915_private_t *dev_priv = dev->dev_private;
23010e43 2339 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
de151cf6 2340 int regnum = obj_priv->fence_reg;
0f973f27 2341 int tile_width;
dc529a4f 2342 uint32_t fence_reg, val;
de151cf6
JB		 2343 uint32_t pitch_val;
2344
2345 if ((obj_priv->gtt_offset & ~I915_FENCE_START_MASK) ||
2346 (obj_priv->gtt_offset & (obj->size - 1))) {
f06da264 2347 WARN(1, "%s: object 0x%08x not 1M or size (0x%zx) aligned\n",
0f973f27 2348 __func__, obj_priv->gtt_offset, obj->size);
de151cf6
JB		 2349 return;
2350 }
2351
0f973f27
JB		 2352 if (obj_priv->tiling_mode == I915_TILING_Y &&
2353 HAS_128_BYTE_Y_TILING(dev))
2354 tile_width = 128;
de151cf6 2355 else
0f973f27
JB		 2356 tile_width = 512;
2357
2358 /* Note: pitch better be a power of two tile widths */
2359 pitch_val = obj_priv->stride / tile_width;
2360 pitch_val = ffs(pitch_val) - 1;
de151cf6 2361
c36a2a6d
DV		 2362 if (obj_priv->tiling_mode == I915_TILING_Y &&
2363 HAS_128_BYTE_Y_TILING(dev))
2364 WARN_ON(pitch_val > I830_FENCE_MAX_PITCH_VAL);
2365 else
2366 WARN_ON(pitch_val > I915_FENCE_MAX_PITCH_VAL);
2367
de151cf6
JB		 2368 val = obj_priv->gtt_offset;
2369 if (obj_priv->tiling_mode == I915_TILING_Y)
2370 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
2371 val |= I915_FENCE_SIZE_BITS(obj->size);
2372 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
2373 val |= I830_FENCE_REG_VALID;
2374
dc529a4f
EA		 2375 if (regnum < 8)
2376 fence_reg = FENCE_REG_830_0 + (regnum * 4);
2377 else
2378 fence_reg = FENCE_REG_945_8 + ((regnum - 8) * 4);
2379 I915_WRITE(fence_reg, val);
de151cf6
JB		 2380}
2381
2382static void i830_write_fence_reg(struct drm_i915_fence_reg *reg)
2383{
2384 struct drm_gem_object *obj = reg->obj;
2385 struct drm_device *dev = obj->dev;
2386 drm_i915_private_t *dev_priv = dev->dev_private;
23010e43 2387 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
de151cf6
JB		 2388 int regnum = obj_priv->fence_reg;
2389 uint32_t val;
2390 uint32_t pitch_val;
8d7773a3 2391 uint32_t fence_size_bits;
de151cf6 2392
8d7773a3 2393 if ((obj_priv->gtt_offset & ~I830_FENCE_START_MASK) ||
de151cf6 2394 (obj_priv->gtt_offset & (obj->size - 1))) {
8d7773a3 2395 WARN(1, "%s: object 0x%08x not 512K or size aligned\n",
0f973f27 2396 __func__, obj_priv->gtt_offset);
de151cf6
JB		 2397 return;
2398 }
2399
e76a16de
EA		 2400 pitch_val = obj_priv->stride / 128;
2401 pitch_val = ffs(pitch_val) - 1;
2402 WARN_ON(pitch_val > I830_FENCE_MAX_PITCH_VAL);
2403
de151cf6
JB		 2404 val = obj_priv->gtt_offset;
2405 if (obj_priv->tiling_mode == I915_TILING_Y)
2406 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
8d7773a3
DV		 2407 fence_size_bits = I830_FENCE_SIZE_BITS(obj->size);
2408 WARN_ON(fence_size_bits & ~0x00000f00);
2409 val |= fence_size_bits;
de151cf6
JB		 2410 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
2411 val |= I830_FENCE_REG_VALID;
2412
2413 I915_WRITE(FENCE_REG_830_0 + (regnum * 4), val);
de151cf6
JB		 2414}
2415
ae3db24a
DV		 2416static int i915_find_fence_reg(struct drm_device *dev)
2417{
2418 struct drm_i915_fence_reg *reg = NULL;
2419 struct drm_i915_gem_object *obj_priv = NULL;
2420 struct drm_i915_private *dev_priv = dev->dev_private;
2421 struct drm_gem_object *obj = NULL;
2422 int i, avail, ret;
2423
2424 /* First try to find a free reg */
2425 avail = 0;
2426 for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) {
2427 reg = &dev_priv->fence_regs[i];
2428 if (!reg->obj)
2429 return i;
2430
23010e43 2431 obj_priv = to_intel_bo(reg->obj);
ae3db24a
DV		 2432 if (!obj_priv->pin_count)
2433 avail++;
2434 }
2435
2436 if (avail == 0)
2437 return -ENOSPC;
2438
2439 /* None available, try to steal one or wait for a user to finish */
2440 i = I915_FENCE_REG_NONE;
007cc8ac
DV		 2441 list_for_each_entry(reg, &dev_priv->mm.fence_list,
2442 lru_list) {
2443 obj = reg->obj;
2444 obj_priv = to_intel_bo(obj);
ae3db24a
DV		 2445
2446 if (obj_priv->pin_count)
2447 continue;
2448
2449 /* found one! */
2450 i = obj_priv->fence_reg;
2451 break;
2452 }
2453
2454 BUG_ON(i == I915_FENCE_REG_NONE);
2455
2456 /* We only have a reference on obj from the active list. put_fence_reg
2457 * might drop that one, causing a use-after-free in it. So hold a
2458 * private reference to obj like the other callers of put_fence_reg
2459 * (set_tiling ioctl) do. */
2460 drm_gem_object_reference(obj);
2461 ret = i915_gem_object_put_fence_reg(obj);
2462 drm_gem_object_unreference(obj);
2463 if (ret != 0)
2464 return ret;
2465
2466 return i;
2467}
2468
de151cf6
JB		 2469/**
2470 * i915_gem_object_get_fence_reg - set up a fence reg for an object
2471 * @obj: object to map through a fence reg
2472 *
2473 * When mapping objects through the GTT, userspace wants to be able to write
2474 * to them without having to worry about swizzling if the object is tiled.
2475 *
2476 * This function walks the fence regs looking for a free one for @obj,
2477 * stealing one if it can't find any.
2478 *
2479 * It then sets up the reg based on the object's properties: address, pitch
2480 * and tiling format.
2481 */
8c4b8c3f
CW		 2482int
2483i915_gem_object_get_fence_reg(struct drm_gem_object *obj)
de151cf6
JB		 2484{
2485 struct drm_device *dev = obj->dev;
79e53945 2486 struct drm_i915_private *dev_priv = dev->dev_private;
23010e43 2487 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
de151cf6 2488 struct drm_i915_fence_reg *reg = NULL;
ae3db24a 2489 int ret;
de151cf6 2490
a09ba7fa
EA		 2491 /* Just update our place in the LRU if our fence is getting used. */
2492 if (obj_priv->fence_reg != I915_FENCE_REG_NONE) {
007cc8ac
DV		 2493 reg = &dev_priv->fence_regs[obj_priv->fence_reg];
2494 list_move_tail(&reg->lru_list, &dev_priv->mm.fence_list);
a09ba7fa
EA		 2495 return 0;
2496 }
2497
de151cf6
JB		 2498 switch (obj_priv->tiling_mode) {
2499 case I915_TILING_NONE:
2500 WARN(1, "allocating a fence for non-tiled object?\n");
2501 break;
2502 case I915_TILING_X:
0f973f27
JB		 2503 if (!obj_priv->stride)
2504 return -EINVAL;
2505 WARN((obj_priv->stride & (512 - 1)),
2506 "object 0x%08x is X tiled but has non-512B pitch\n",
2507 obj_priv->gtt_offset);
de151cf6
JB		 2508 break;
2509 case I915_TILING_Y:
0f973f27
JB		 2510 if (!obj_priv->stride)
2511 return -EINVAL;
2512 WARN((obj_priv->stride & (128 - 1)),
2513 "object 0x%08x is Y tiled but has non-128B pitch\n",
2514 obj_priv->gtt_offset);
de151cf6
JB		 2515 break;
2516 }
2517
ae3db24a
DV		 2518 ret = i915_find_fence_reg(dev);
2519 if (ret < 0)
2520 return ret;
de151cf6 2521
ae3db24a
DV		 2522 obj_priv->fence_reg = ret;
2523 reg = &dev_priv->fence_regs[obj_priv->fence_reg];
007cc8ac 2524 list_add_tail(&reg->lru_list, &dev_priv->mm.fence_list);
a09ba7fa 2525
de151cf6
JB		 2526 reg->obj = obj;
2527
4e901fdc
EA		 2528 if (IS_GEN6(dev))
2529 sandybridge_write_fence_reg(reg);
2530 else if (IS_I965G(dev))
de151cf6
JB		 2531 i965_write_fence_reg(reg);
2532 else if (IS_I9XX(dev))
2533 i915_write_fence_reg(reg);
2534 else
2535 i830_write_fence_reg(reg);
d9ddcb96 2536
ae3db24a
DV		 2537 trace_i915_gem_object_get_fence(obj, obj_priv->fence_reg,
2538 obj_priv->tiling_mode);
1c5d22f7 2539
d9ddcb96 2540 return 0;
de151cf6
JB		 2541}
2542
2543/**
2544 * i915_gem_clear_fence_reg - clear out fence register info
2545 * @obj: object to clear
2546 *
2547 * Zeroes out the fence register itself and clears out the associated
2548 * data structures in dev_priv and obj_priv.
2549 */
2550static void
2551i915_gem_clear_fence_reg(struct drm_gem_object *obj)
2552{
2553 struct drm_device *dev = obj->dev;
79e53945 2554 drm_i915_private_t *dev_priv = dev->dev_private;
23010e43 2555 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
007cc8ac
DV		 2556 struct drm_i915_fence_reg *reg =
2557 &dev_priv->fence_regs[obj_priv->fence_reg];
de151cf6 2558
4e901fdc
EA		 2559 if (IS_GEN6(dev)) {
2560 I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 +
2561 (obj_priv->fence_reg * 8), 0);
2562 } else if (IS_I965G(dev)) {
de151cf6 2563 I915_WRITE64(FENCE_REG_965_0 + (obj_priv->fence_reg * 8), 0);
4e901fdc 2564 } else {
dc529a4f
EA		 2565 uint32_t fence_reg;
2566
2567 if (obj_priv->fence_reg < 8)
2568 fence_reg = FENCE_REG_830_0 + obj_priv->fence_reg * 4;
2569 else
2570 fence_reg = FENCE_REG_945_8 + (obj_priv->fence_reg -
2571 8) * 4;
2572
2573 I915_WRITE(fence_reg, 0);
2574 }
de151cf6 2575
007cc8ac 2576 reg->obj = NULL;
de151cf6 2577 obj_priv->fence_reg = I915_FENCE_REG_NONE;
007cc8ac 2578 list_del_init(&reg->lru_list);
de151cf6
JB		 2579}
2580
52dc7d32
CW		 2581/**
2582 * i915_gem_object_put_fence_reg - waits on outstanding fenced access
2583 * to the buffer to finish, and then resets the fence register.
2584 * @obj: tiled object holding a fence register.
2585 *
2586 * Zeroes out the fence register itself and clears out the associated
2587 * data structures in dev_priv and obj_priv.
2588 */
2589int
2590i915_gem_object_put_fence_reg(struct drm_gem_object *obj)
2591{
2592 struct drm_device *dev = obj->dev;
23010e43 2593 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
52dc7d32
CW		 2594
2595 if (obj_priv->fence_reg == I915_FENCE_REG_NONE)
2596 return 0;
2597
10ae9bd2
DV		 2598 /* If we've changed tiling, GTT-mappings of the object
2599 * need to re-fault to ensure that the correct fence register
2600 * setup is in place.
2601 */
2602 i915_gem_release_mmap(obj);
2603
52dc7d32
CW		 2604 /* On the i915, GPU access to tiled buffers is via a fence,
2605 * therefore we must wait for any outstanding access to complete
2606 * before clearing the fence.
2607 */
2608 if (!IS_I965G(dev)) {
2609 int ret;
2610
2611 i915_gem_object_flush_gpu_write_domain(obj);
52dc7d32
CW		 2612 ret = i915_gem_object_wait_rendering(obj);
2613 if (ret != 0)
2614 return ret;
2615 }
2616
4a726612 2617 i915_gem_object_flush_gtt_write_domain(obj);
52dc7d32
CW		 2618 i915_gem_clear_fence_reg (obj);
2619
2620 return 0;
2621}
2622
673a394b
EA		 2623/**
2624 * Finds free space in the GTT aperture and binds the object there.
2625 */
2626static int
2627i915_gem_object_bind_to_gtt(struct drm_gem_object *obj, unsigned alignment)
2628{
2629 struct drm_device *dev = obj->dev;
2630 drm_i915_private_t *dev_priv = dev->dev_private;
23010e43 2631 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
673a394b 2632 struct drm_mm_node *free_space;
4bdadb97 2633 gfp_t gfpmask = __GFP_NORETRY | __GFP_NOWARN;
07f73f69 2634 int ret;
673a394b 2635
bb6baf76 2636 if (obj_priv->madv != I915_MADV_WILLNEED) {
3ef94daa
CW		 2637 DRM_ERROR("Attempting to bind a purgeable object\n");
2638 return -EINVAL;
2639 }
2640
673a394b 2641 if (alignment == 0)
0f973f27 2642 alignment = i915_gem_get_gtt_alignment(obj);
8d7773a3 2643 if (alignment & (i915_gem_get_gtt_alignment(obj) - 1)) {
673a394b
EA		 2644 DRM_ERROR("Invalid object alignment requested %u\n", alignment);
2645 return -EINVAL;
2646 }
2647
2648 search_free:
2649 free_space = drm_mm_search_free(&dev_priv->mm.gtt_space,
2650 obj->size, alignment, 0);
2651 if (free_space != NULL) {
2652 obj_priv->gtt_space = drm_mm_get_block(free_space, obj->size,
2653 alignment);
2654 if (obj_priv->gtt_space != NULL) {
2655 obj_priv->gtt_space->private = obj;
2656 obj_priv->gtt_offset = obj_priv->gtt_space->start;
2657 }
2658 }
2659 if (obj_priv->gtt_space == NULL) {
2660 /* If the gtt is empty and we're still having trouble
2661 * fitting our object in, we're out of memory.
2662 */
2663#if WATCH_LRU
2664 DRM_INFO("%s: GTT full, evicting something\n", __func__);
2665#endif
07f73f69 2666 ret = i915_gem_evict_something(dev, obj->size);
9731129c 2667 if (ret)
673a394b 2668 return ret;
9731129c 2669
673a394b
EA		 2670 goto search_free;
2671 }
2672
2673#if WATCH_BUF
cfd43c02 2674 DRM_INFO("Binding object of size %zd at 0x%08x\n",
673a394b
EA		 2675 obj->size, obj_priv->gtt_offset);
2676#endif
4bdadb97 2677 ret = i915_gem_object_get_pages(obj, gfpmask);
673a394b
EA		 2678 if (ret) {
2679 drm_mm_put_block(obj_priv->gtt_space);
2680 obj_priv->gtt_space = NULL;
07f73f69
CW		 2681
2682 if (ret == -ENOMEM) {
2683 /* first try to clear up some space from the GTT */
2684 ret = i915_gem_evict_something(dev, obj->size);
2685 if (ret) {
07f73f69 2686 /* now try to shrink everyone else */
4bdadb97
CW		 2687 if (gfpmask) {
2688 gfpmask = 0;
2689 goto search_free;
07f73f69
CW		 2690 }
2691
2692 return ret;
2693 }
2694
2695 goto search_free;
2696 }
2697
673a394b
EA		 2698 return ret;
2699 }
2700
673a394b
EA		 2701 /* Create an AGP memory structure pointing at our pages, and bind it
2702 * into the GTT.
2703 */
2704 obj_priv->agp_mem = drm_agp_bind_pages(dev,
856fa198 2705 obj_priv->pages,
07f73f69 2706 obj->size >> PAGE_SHIFT,
ba1eb1d8
KP		 2707 obj_priv->gtt_offset,
2708 obj_priv->agp_type);
673a394b 2709 if (obj_priv->agp_mem == NULL) {
856fa198 2710 i915_gem_object_put_pages(obj);
673a394b
EA		 2711 drm_mm_put_block(obj_priv->gtt_space);
2712 obj_priv->gtt_space = NULL;
07f73f69
CW		 2713
2714 ret = i915_gem_evict_something(dev, obj->size);
9731129c 2715 if (ret)
07f73f69 2716 return ret;
07f73f69
CW		 2717
2718 goto search_free;
673a394b
EA		 2719 }
2720 atomic_inc(&dev->gtt_count);
2721 atomic_add(obj->size, &dev->gtt_memory);
2722
2723 /* Assert that the object is not currently in any GPU domain. As it
2724 * wasn't in the GTT, there shouldn't be any way it could have been in
2725 * a GPU cache
2726 */
21d509e3
CW		 2727 BUG_ON(obj->read_domains & I915_GEM_GPU_DOMAINS);
2728 BUG_ON(obj->write_domain & I915_GEM_GPU_DOMAINS);
673a394b 2729
1c5d22f7
CW		 2730 trace_i915_gem_object_bind(obj, obj_priv->gtt_offset);
2731
673a394b
EA		 2732 return 0;
2733}
2734
2735void
2736i915_gem_clflush_object(struct drm_gem_object *obj)
2737{
23010e43 2738 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
673a394b
EA		 2739
2740 /* If we don't have a page list set up, then we're not pinned
2741 * to GPU, and we can ignore the cache flush because it'll happen
2742 * again at bind time.
2743 */
856fa198 2744 if (obj_priv->pages == NULL)
673a394b
EA		 2745 return;
2746
1c5d22f7 2747 trace_i915_gem_object_clflush(obj);
cfa16a0d 2748
856fa198 2749 drm_clflush_pages(obj_priv->pages, obj->size / PAGE_SIZE);
673a394b
EA		 2750}
2751
e47c68e9
EA		 2752/** Flushes any GPU write domain for the object if it's dirty. */
2753static void
2754i915_gem_object_flush_gpu_write_domain(struct drm_gem_object *obj)
2755{
2756 struct drm_device *dev = obj->dev;
1c5d22f7 2757 uint32_t old_write_domain;
852835f3 2758 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
e47c68e9
EA		 2759
2760 if ((obj->write_domain & I915_GEM_GPU_DOMAINS) == 0)
2761 return;
2762
2763 /* Queue the GPU write cache flushing we need. */
1c5d22f7 2764 old_write_domain = obj->write_domain;
e47c68e9 2765 i915_gem_flush(dev, 0, obj->write_domain);
852835f3 2766 (void) i915_add_request(dev, NULL, obj->write_domain, obj_priv->ring);
99fcb766 2767 BUG_ON(obj->write_domain);
1c5d22f7
CW		 2768
2769 trace_i915_gem_object_change_domain(obj,
2770 obj->read_domains,
2771 old_write_domain);
e47c68e9
EA		 2772}
2773
2774/** Flushes the GTT write domain for the object if it's dirty. */
2775static void
2776i915_gem_object_flush_gtt_write_domain(struct drm_gem_object *obj)
2777{
1c5d22f7
CW		 2778 uint32_t old_write_domain;
2779
e47c68e9
EA		 2780 if (obj->write_domain != I915_GEM_DOMAIN_GTT)
2781 return;
2782
2783 /* No actual flushing is required for the GTT write domain. Writes
2784 * to it immediately go to main memory as far as we know, so there's
2785 * no chipset flush. It also doesn't land in render cache.
2786 */
1c5d22f7 2787 old_write_domain = obj->write_domain;
e47c68e9 2788 obj->write_domain = 0;
1c5d22f7
CW		 2789
2790 trace_i915_gem_object_change_domain(obj,
2791 obj->read_domains,
2792 old_write_domain);
e47c68e9
EA		 2793}
2794
2795/** Flushes the CPU write domain for the object if it's dirty. */
2796static void
2797i915_gem_object_flush_cpu_write_domain(struct drm_gem_object *obj)
2798{
2799 struct drm_device *dev = obj->dev;
1c5d22f7 2800 uint32_t old_write_domain;
e47c68e9
EA		 2801
2802 if (obj->write_domain != I915_GEM_DOMAIN_CPU)
2803 return;
2804
2805 i915_gem_clflush_object(obj);
2806 drm_agp_chipset_flush(dev);
1c5d22f7 2807 old_write_domain = obj->write_domain;
e47c68e9 2808 obj->write_domain = 0;
1c5d22f7
CW		 2809
2810 trace_i915_gem_object_change_domain(obj,
2811 obj->read_domains,
2812 old_write_domain);
e47c68e9
EA		 2813}
2814
6b95a207
KH		 2815void
2816i915_gem_object_flush_write_domain(struct drm_gem_object *obj)
2817{
2818 switch (obj->write_domain) {
2819 case I915_GEM_DOMAIN_GTT:
2820 i915_gem_object_flush_gtt_write_domain(obj);
2821 break;
2822 case I915_GEM_DOMAIN_CPU:
2823 i915_gem_object_flush_cpu_write_domain(obj);
2824 break;
2825 default:
2826 i915_gem_object_flush_gpu_write_domain(obj);
2827 break;
2828 }
2829}
2830
2ef7eeaa
EA		 2831/**
2832 * Moves a single object to the GTT read, and possibly write domain.
2833 *
2834 * This function returns when the move is complete, including waiting on
2835 * flushes to occur.
2836 */
79e53945 2837int
2ef7eeaa
EA		 2838i915_gem_object_set_to_gtt_domain(struct drm_gem_object *obj, int write)
2839{
23010e43 2840 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1c5d22f7 2841 uint32_t old_write_domain, old_read_domains;
e47c68e9 2842 int ret;
2ef7eeaa 2843
02354392
EA		 2844 /* Not valid to be called on unbound objects. */
2845 if (obj_priv->gtt_space == NULL)
2846 return -EINVAL;
2847
e47c68e9
EA		 2848 i915_gem_object_flush_gpu_write_domain(obj);
2849 /* Wait on any GPU rendering and flushing to occur. */
2850 ret = i915_gem_object_wait_rendering(obj);
2851 if (ret != 0)
2852 return ret;
2853
1c5d22f7
CW		 2854 old_write_domain = obj->write_domain;
2855 old_read_domains = obj->read_domains;
2856
e47c68e9
EA		 2857 /* If we're writing through the GTT domain, then CPU and GPU caches
2858 * will need to be invalidated at next use.
2ef7eeaa 2859 */
e47c68e9
EA		 2860 if (write)
2861 obj->read_domains &= I915_GEM_DOMAIN_GTT;
2ef7eeaa 2862
e47c68e9 2863 i915_gem_object_flush_cpu_write_domain(obj);
2ef7eeaa 2864
e47c68e9
EA		 2865 /* It should now be out of any other write domains, and we can update
2866 * the domain values for our changes.
2867 */
2868 BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_GTT) != 0);
2869 obj->read_domains |= I915_GEM_DOMAIN_GTT;
2870 if (write) {
2871 obj->write_domain = I915_GEM_DOMAIN_GTT;
2872 obj_priv->dirty = 1;
2ef7eeaa
EA		 2873 }
2874
1c5d22f7
CW		 2875 trace_i915_gem_object_change_domain(obj,
2876 old_read_domains,
2877 old_write_domain);
2878
e47c68e9
EA		 2879 return 0;
2880}
2881
b9241ea3
ZW		 2882/*
2883 * Prepare buffer for display plane. Use uninterruptible for possible flush
2884 * wait, as in modesetting process we're not supposed to be interrupted.
2885 */
2886int
2887i915_gem_object_set_to_display_plane(struct drm_gem_object *obj)
2888{
2889 struct drm_device *dev = obj->dev;
23010e43 2890 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
b9241ea3
ZW		 2891 uint32_t old_write_domain, old_read_domains;
2892 int ret;
2893
2894 /* Not valid to be called on unbound objects. */
2895 if (obj_priv->gtt_space == NULL)
2896 return -EINVAL;
2897
2898 i915_gem_object_flush_gpu_write_domain(obj);
2899
2900 /* Wait on any GPU rendering and flushing to occur. */
2901 if (obj_priv->active) {
2902#if WATCH_BUF
2903 DRM_INFO("%s: object %p wait for seqno %08x\n",
2904 __func__, obj, obj_priv->last_rendering_seqno);
2905#endif
852835f3
ZN		 2906 ret = i915_do_wait_request(dev,
2907 obj_priv->last_rendering_seqno,
2908 0,
2909 obj_priv->ring);
b9241ea3
ZW		 2910 if (ret != 0)
2911 return ret;
2912 }
2913
2914 old_write_domain = obj->write_domain;
2915 old_read_domains = obj->read_domains;
2916
2917 obj->read_domains &= I915_GEM_DOMAIN_GTT;
2918
2919 i915_gem_object_flush_cpu_write_domain(obj);
2920
2921 /* It should now be out of any other write domains, and we can update
2922 * the domain values for our changes.
2923 */
2924 BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_GTT) != 0);
2925 obj->read_domains |= I915_GEM_DOMAIN_GTT;
2926 obj->write_domain = I915_GEM_DOMAIN_GTT;
2927 obj_priv->dirty = 1;
2928
2929 trace_i915_gem_object_change_domain(obj,
2930 old_read_domains,
2931 old_write_domain);
2932
2933 return 0;
2934}
2935
e47c68e9
EA		 2936/**
2937 * Moves a single object to the CPU read, and possibly write domain.
2938 *
2939 * This function returns when the move is complete, including waiting on
2940 * flushes to occur.
2941 */
2942static int
2943i915_gem_object_set_to_cpu_domain(struct drm_gem_object *obj, int write)
2944{
1c5d22f7 2945 uint32_t old_write_domain, old_read_domains;
e47c68e9
EA		 2946 int ret;
2947
2948 i915_gem_object_flush_gpu_write_domain(obj);
2ef7eeaa 2949 /* Wait on any GPU rendering and flushing to occur. */
e47c68e9
EA		 2950 ret = i915_gem_object_wait_rendering(obj);
2951 if (ret != 0)
2952 return ret;
2ef7eeaa 2953
e47c68e9 2954 i915_gem_object_flush_gtt_write_domain(obj);
2ef7eeaa 2955
e47c68e9
EA		 2956 /* If we have a partially-valid cache of the object in the CPU,
2957 * finish invalidating it and free the per-page flags.
2ef7eeaa 2958 */
e47c68e9 2959 i915_gem_object_set_to_full_cpu_read_domain(obj);
2ef7eeaa 2960
1c5d22f7
CW		 2961 old_write_domain = obj->write_domain;
2962 old_read_domains = obj->read_domains;
2963
e47c68e9
EA		 2964 /* Flush the CPU cache if it's still invalid. */
2965 if ((obj->read_domains & I915_GEM_DOMAIN_CPU) == 0) {
2ef7eeaa 2966 i915_gem_clflush_object(obj);
2ef7eeaa 2967
e47c68e9 2968 obj->read_domains |= I915_GEM_DOMAIN_CPU;
2ef7eeaa
EA		 2969 }
2970
2971 /* It should now be out of any other write domains, and we can update
2972 * the domain values for our changes.
2973 */
e47c68e9
EA		 2974 BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
2975
2976 /* If we're writing through the CPU, then the GPU read domains will
2977 * need to be invalidated at next use.
2978 */
2979 if (write) {
2980 obj->read_domains &= I915_GEM_DOMAIN_CPU;
2981 obj->write_domain = I915_GEM_DOMAIN_CPU;
2982 }
2ef7eeaa 2983
1c5d22f7
CW		 2984 trace_i915_gem_object_change_domain(obj,
2985 old_read_domains,
2986 old_write_domain);
2987
2ef7eeaa
EA		 2988 return 0;
2989}
2990
673a394b
EA		 2991/*
2992 * Set the next domain for the specified object. This
2993 * may not actually perform the necessary flushing/invaliding though,
2994 * as that may want to be batched with other set_domain operations
2995 *
2996 * This is (we hope) the only really tricky part of gem. The goal
2997 * is fairly simple -- track which caches hold bits of the object
2998 * and make sure they remain coherent. A few concrete examples may
2999 * help to explain how it works. For shorthand, we use the notation
3000 * (read_domains, write_domain), e.g. (CPU, CPU) to indicate the
3001 * a pair of read and write domain masks.
3002 *
3003 * Case 1: the batch buffer
3004 *
3005 * 1. Allocated
3006 * 2. Written by CPU
3007 * 3. Mapped to GTT
3008 * 4. Read by GPU
3009 * 5. Unmapped from GTT
3010 * 6. Freed
3011 *
3012 * Let's take these a step at a time
3013 *
3014 * 1. Allocated
3015 * Pages allocated from the kernel may still have
3016 * cache contents, so we set them to (CPU, CPU) always.
3017 * 2. Written by CPU (using pwrite)
3018 * The pwrite function calls set_domain (CPU, CPU) and
3019 * this function does nothing (as nothing changes)
3020 * 3. Mapped by GTT
3021 * This function asserts that the object is not
3022 * currently in any GPU-based read or write domains
3023 * 4. Read by GPU
3024 * i915_gem_execbuffer calls set_domain (COMMAND, 0).
3025 * As write_domain is zero, this function adds in the
3026 * current read domains (CPU+COMMAND, 0).
3027 * flush_domains is set to CPU.
3028 * invalidate_domains is set to COMMAND
3029 * clflush is run to get data out of the CPU caches
3030 * then i915_dev_set_domain calls i915_gem_flush to
3031 * emit an MI_FLUSH and drm_agp_chipset_flush
3032 * 5. Unmapped from GTT
3033 * i915_gem_object_unbind calls set_domain (CPU, CPU)
3034 * flush_domains and invalidate_domains end up both zero
3035 * so no flushing/invalidating happens
3036 * 6. Freed
3037 * yay, done
3038 *
3039 * Case 2: The shared render buffer
3040 *
3041 * 1. Allocated
3042 * 2. Mapped to GTT
3043 * 3. Read/written by GPU
3044 * 4. set_domain to (CPU,CPU)
3045 * 5. Read/written by CPU
3046 * 6. Read/written by GPU
3047 *
3048 * 1. Allocated
3049 * Same as last example, (CPU, CPU)
3050 * 2. Mapped to GTT
3051 * Nothing changes (assertions find that it is not in the GPU)
3052 * 3. Read/written by GPU
3053 * execbuffer calls set_domain (RENDER, RENDER)
3054 * flush_domains gets CPU
3055 * invalidate_domains gets GPU
3056 * clflush (obj)
3057 * MI_FLUSH and drm_agp_chipset_flush
3058 * 4. set_domain (CPU, CPU)
3059 * flush_domains gets GPU
3060 * invalidate_domains gets CPU
3061 * wait_rendering (obj) to make sure all drawing is complete.
3062 * This will include an MI_FLUSH to get the data from GPU
3063 * to memory
3064 * clflush (obj) to invalidate the CPU cache
3065 * Another MI_FLUSH in i915_gem_flush (eliminate this somehow?)
3066 * 5. Read/written by CPU
3067 * cache lines are loaded and dirtied
3068 * 6. Read written by GPU
3069 * Same as last GPU access
3070 *
3071 * Case 3: The constant buffer
3072 *
3073 * 1. Allocated
3074 * 2. Written by CPU
3075 * 3. Read by GPU
3076 * 4. Updated (written) by CPU again
3077 * 5. Read by GPU
3078 *
3079 * 1. Allocated
3080 * (CPU, CPU)
3081 * 2. Written by CPU
3082 * (CPU, CPU)
3083 * 3. Read by GPU
3084 * (CPU+RENDER, 0)
3085 * flush_domains = CPU
3086 * invalidate_domains = RENDER
3087 * clflush (obj)
3088 * MI_FLUSH
3089 * drm_agp_chipset_flush
3090 * 4. Updated (written) by CPU again
3091 * (CPU, CPU)
3092 * flush_domains = 0 (no previous write domain)
3093 * invalidate_domains = 0 (no new read domains)
3094 * 5. Read by GPU
3095 * (CPU+RENDER, 0)
3096 * flush_domains = CPU
3097 * invalidate_domains = RENDER
3098 * clflush (obj)
3099 * MI_FLUSH
3100 * drm_agp_chipset_flush
3101 */
c0d90829 3102static void
8b0e378a 3103i915_gem_object_set_to_gpu_domain(struct drm_gem_object *obj)
673a394b
EA		 3104{
3105 struct drm_device *dev = obj->dev;
23010e43 3106 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
673a394b
EA		 3107 uint32_t invalidate_domains = 0;
3108 uint32_t flush_domains = 0;
1c5d22f7 3109 uint32_t old_read_domains;
e47c68e9 3110
8b0e378a
EA		 3111 BUG_ON(obj->pending_read_domains & I915_GEM_DOMAIN_CPU);
3112 BUG_ON(obj->pending_write_domain == I915_GEM_DOMAIN_CPU);
673a394b 3113
652c393a
JB		 3114 intel_mark_busy(dev, obj);
3115
673a394b
EA		 3116#if WATCH_BUF
3117 DRM_INFO("%s: object %p read %08x -> %08x write %08x -> %08x\n",
3118 __func__, obj,
8b0e378a
EA		 3119 obj->read_domains, obj->pending_read_domains,
3120 obj->write_domain, obj->pending_write_domain);
673a394b
EA		 3121#endif
3122 /*
3123 * If the object isn't moving to a new write domain,
3124 * let the object stay in multiple read domains
3125 */
8b0e378a
EA		 3126 if (obj->pending_write_domain == 0)
3127 obj->pending_read_domains |= obj->read_domains;
673a394b
EA		 3128 else
3129 obj_priv->dirty = 1;
3130
3131 /*
3132 * Flush the current write domain if
3133 * the new read domains don't match. Invalidate
3134 * any read domains which differ from the old
3135 * write domain
3136 */
8b0e378a
EA		 3137 if (obj->write_domain &&
3138 obj->write_domain != obj->pending_read_domains) {
673a394b 3139 flush_domains |= obj->write_domain;
8b0e378a
EA		 3140 invalidate_domains |=
3141 obj->pending_read_domains & ~obj->write_domain;
673a394b
EA		 3142 }
3143 /*
3144 * Invalidate any read caches which may have
3145 * stale data. That is, any new read domains.
3146 */
8b0e378a 3147 invalidate_domains |= obj->pending_read_domains & ~obj->read_domains;
673a394b
EA		 3148 if ((flush_domains | invalidate_domains) & I915_GEM_DOMAIN_CPU) {
3149#if WATCH_BUF
3150 DRM_INFO("%s: CPU domain flush %08x invalidate %08x\n",
3151 __func__, flush_domains, invalidate_domains);
3152#endif
673a394b
EA		 3153 i915_gem_clflush_object(obj);
3154 }
3155
1c5d22f7
CW		 3156 old_read_domains = obj->read_domains;
3157
efbeed96
EA		 3158 /* The actual obj->write_domain will be updated with
3159 * pending_write_domain after we emit the accumulated flush for all
3160 * of our domain changes in execbuffers (which clears objects'
3161 * write_domains). So if we have a current write domain that we
3162 * aren't changing, set pending_write_domain to that.
3163 */
3164 if (flush_domains == 0 && obj->pending_write_domain == 0)
3165 obj->pending_write_domain = obj->write_domain;
8b0e378a 3166 obj->read_domains = obj->pending_read_domains;
673a394b
EA		 3167
3168 dev->invalidate_domains |= invalidate_domains;
3169 dev->flush_domains |= flush_domains;
3170#if WATCH_BUF
3171 DRM_INFO("%s: read %08x write %08x invalidate %08x flush %08x\n",
3172 __func__,
3173 obj->read_domains, obj->write_domain,
3174 dev->invalidate_domains, dev->flush_domains);
3175#endif
1c5d22f7
CW		 3176
3177 trace_i915_gem_object_change_domain(obj,
3178 old_read_domains,
3179 obj->write_domain);
673a394b
EA		 3180}
3181
3182/**
e47c68e9 3183 * Moves the object from a partially CPU read to a full one.
673a394b 3184 *
e47c68e9
EA		 3185 * Note that this only resolves i915_gem_object_set_cpu_read_domain_range(),
3186 * and doesn't handle transitioning from !(read_domains & I915_GEM_DOMAIN_CPU).
673a394b 3187 */
e47c68e9
EA		 3188static void
3189i915_gem_object_set_to_full_cpu_read_domain(struct drm_gem_object *obj)
673a394b 3190{
23010e43 3191 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
673a394b 3192
e47c68e9
EA		 3193 if (!obj_priv->page_cpu_valid)
3194 return;
3195
3196 /* If we're partially in the CPU read domain, finish moving it in.
3197 */
3198 if (obj->read_domains & I915_GEM_DOMAIN_CPU) {
3199 int i;
3200
3201 for (i = 0; i <= (obj->size - 1) / PAGE_SIZE; i++) {
3202 if (obj_priv->page_cpu_valid[i])
3203 continue;
856fa198 3204 drm_clflush_pages(obj_priv->pages + i, 1);
e47c68e9 3205 }
e47c68e9
EA		 3206 }
3207
3208 /* Free the page_cpu_valid mappings which are now stale, whether
3209 * or not we've got I915_GEM_DOMAIN_CPU.
3210 */
9a298b2a 3211 kfree(obj_priv->page_cpu_valid);
e47c68e9
EA		 3212 obj_priv->page_cpu_valid = NULL;
3213}
3214
3215/**
3216 * Set the CPU read domain on a range of the object.
3217 *
3218 * The object ends up with I915_GEM_DOMAIN_CPU in its read flags although it's
3219 * not entirely valid. The page_cpu_valid member of the object flags which
3220 * pages have been flushed, and will be respected by
3221 * i915_gem_object_set_to_cpu_domain() if it's called on to get a valid mapping
3222 * of the whole object.
3223 *
3224 * This function returns when the move is complete, including waiting on
3225 * flushes to occur.
3226 */
3227static int
3228i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object *obj,
3229 uint64_t offset, uint64_t size)
3230{
23010e43 3231 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1c5d22f7 3232 uint32_t old_read_domains;
e47c68e9 3233 int i, ret;
673a394b 3234
e47c68e9
EA		 3235 if (offset == 0 && size == obj->size)
3236 return i915_gem_object_set_to_cpu_domain(obj, 0);
673a394b 3237
e47c68e9
EA		 3238 i915_gem_object_flush_gpu_write_domain(obj);
3239 /* Wait on any GPU rendering and flushing to occur. */
6a47baa6 3240 ret = i915_gem_object_wait_rendering(obj);
e47c68e9 3241 if (ret != 0)
6a47baa6 3242 return ret;
e47c68e9
EA		 3243 i915_gem_object_flush_gtt_write_domain(obj);
3244
3245 /* If we're already fully in the CPU read domain, we're done. */
3246 if (obj_priv->page_cpu_valid == NULL &&
3247 (obj->read_domains & I915_GEM_DOMAIN_CPU) != 0)
3248 return 0;
673a394b 3249
e47c68e9
EA		 3250 /* Otherwise, create/clear the per-page CPU read domain flag if we're
3251 * newly adding I915_GEM_DOMAIN_CPU
3252 */
673a394b 3253 if (obj_priv->page_cpu_valid == NULL) {
9a298b2a
EA		 3254 obj_priv->page_cpu_valid = kzalloc(obj->size / PAGE_SIZE,
3255 GFP_KERNEL);
e47c68e9
EA		 3256 if (obj_priv->page_cpu_valid == NULL)
3257 return -ENOMEM;
3258 } else if ((obj->read_domains & I915_GEM_DOMAIN_CPU) == 0)
3259 memset(obj_priv->page_cpu_valid, 0, obj->size / PAGE_SIZE);
673a394b
EA		 3260
3261 /* Flush the cache on any pages that are still invalid from the CPU's
3262 * perspective.
3263 */
e47c68e9
EA		 3264 for (i = offset / PAGE_SIZE; i <= (offset + size - 1) / PAGE_SIZE;
3265 i++) {
673a394b
EA		 3266 if (obj_priv->page_cpu_valid[i])
3267 continue;
3268
856fa198 3269 drm_clflush_pages(obj_priv->pages + i, 1);
673a394b
EA		 3270
3271 obj_priv->page_cpu_valid[i] = 1;
3272 }
3273
e47c68e9
EA		 3274 /* It should now be out of any other write domains, and we can update
3275 * the domain values for our changes.
3276 */
3277 BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
3278
1c5d22f7 3279 old_read_domains = obj->read_domains;
e47c68e9
EA		 3280 obj->read_domains |= I915_GEM_DOMAIN_CPU;
3281
1c5d22f7
CW		 3282 trace_i915_gem_object_change_domain(obj,
3283 old_read_domains,
3284 obj->write_domain);
3285
673a394b
EA		 3286 return 0;
3287}
3288
673a394b
EA		 3289/**
3290 * Pin an object to the GTT and evaluate the relocations landing in it.
3291 */
3292static int
3293i915_gem_object_pin_and_relocate(struct drm_gem_object *obj,
3294 struct drm_file *file_priv,
76446cac 3295 struct drm_i915_gem_exec_object2 *entry,
40a5f0de 3296 struct drm_i915_gem_relocation_entry *relocs)
673a394b
EA		 3297{
3298 struct drm_device *dev = obj->dev;
0839ccb8 3299 drm_i915_private_t *dev_priv = dev->dev_private;
23010e43 3300 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
673a394b 3301 int i, ret;
0839ccb8 3302 void __iomem *reloc_page;
76446cac
JB		 3303 bool need_fence;
3304
3305 need_fence = entry->flags & EXEC_OBJECT_NEEDS_FENCE &&
3306 obj_priv->tiling_mode != I915_TILING_NONE;
3307
3308 /* Check fence reg constraints and rebind if necessary */
f590d279
OA		 3309 if (need_fence && !i915_gem_object_fence_offset_ok(obj,
3310 obj_priv->tiling_mode))
76446cac 3311 i915_gem_object_unbind(obj);
673a394b
EA		 3312
3313 /* Choose the GTT offset for our buffer and put it there. */
3314 ret = i915_gem_object_pin(obj, (uint32_t) entry->alignment);
3315 if (ret)
3316 return ret;
3317
76446cac
JB		 3318 /*
3319 * Pre-965 chips need a fence register set up in order to
3320 * properly handle blits to/from tiled surfaces.
3321 */
3322 if (need_fence) {
3323 ret = i915_gem_object_get_fence_reg(obj);
3324 if (ret != 0) {
3325 if (ret != -EBUSY && ret != -ERESTARTSYS)
3326 DRM_ERROR("Failure to install fence: %d\n",
3327 ret);
3328 i915_gem_object_unpin(obj);
3329 return ret;
3330 }
3331 }
3332
673a394b
EA		 3333 entry->offset = obj_priv->gtt_offset;
3334
673a394b
EA		 3335 /* Apply the relocations, using the GTT aperture to avoid cache
3336 * flushing requirements.
3337 */
3338 for (i = 0; i < entry->relocation_count; i++) {
40a5f0de 3339 struct drm_i915_gem_relocation_entry *reloc= &relocs[i];
673a394b
EA		 3340 struct drm_gem_object *target_obj;
3341 struct drm_i915_gem_object *target_obj_priv;
3043c60c
EA		 3342 uint32_t reloc_val, reloc_offset;
3343 uint32_t __iomem *reloc_entry;
673a394b 3344
673a394b 3345 target_obj = drm_gem_object_lookup(obj->dev, file_priv,
40a5f0de 3346 reloc->target_handle);
673a394b
EA		 3347 if (target_obj == NULL) {
3348 i915_gem_object_unpin(obj);
3349 return -EBADF;
3350 }
23010e43 3351 target_obj_priv = to_intel_bo(target_obj);
673a394b 3352
8542a0bb
CW		 3353#if WATCH_RELOC
3354 DRM_INFO("%s: obj %p offset %08x target %d "
3355 "read %08x write %08x gtt %08x "
3356 "presumed %08x delta %08x\n",
3357 __func__,
3358 obj,
3359 (int) reloc->offset,
3360 (int) reloc->target_handle,
3361 (int) reloc->read_domains,
3362 (int) reloc->write_domain,
3363 (int) target_obj_priv->gtt_offset,
3364 (int) reloc->presumed_offset,
3365 reloc->delta);
3366#endif
3367
673a394b
EA		 3368 /* The target buffer should have appeared before us in the
3369 * exec_object list, so it should have a GTT space bound by now.
3370 */
3371 if (target_obj_priv->gtt_space == NULL) {
3372 DRM_ERROR("No GTT space found for object %d\n",
40a5f0de 3373 reloc->target_handle);
673a394b
EA		 3374 drm_gem_object_unreference(target_obj);
3375 i915_gem_object_unpin(obj);
3376 return -EINVAL;
3377 }
3378
8542a0bb 3379 /* Validate that the target is in a valid r/w GPU domain */
16edd550
DV		 3380 if (reloc->write_domain & (reloc->write_domain - 1)) {
3381 DRM_ERROR("reloc with multiple write domains: "
3382 "obj %p target %d offset %d "
3383 "read %08x write %08x",
3384 obj, reloc->target_handle,
3385 (int) reloc->offset,
3386 reloc->read_domains,
3387 reloc->write_domain);
3388 return -EINVAL;
3389 }
40a5f0de
EA		 3390 if (reloc->write_domain & I915_GEM_DOMAIN_CPU ||
3391 reloc->read_domains & I915_GEM_DOMAIN_CPU) {
e47c68e9
EA		 3392 DRM_ERROR("reloc with read/write CPU domains: "
3393 "obj %p target %d offset %d "
3394 "read %08x write %08x",
40a5f0de
EA		 3395 obj, reloc->target_handle,
3396 (int) reloc->offset,
3397 reloc->read_domains,
3398 reloc->write_domain);
491152b8
CW		 3399 drm_gem_object_unreference(target_obj);
3400 i915_gem_object_unpin(obj);
e47c68e9
EA		 3401 return -EINVAL;
3402 }
40a5f0de
EA		 3403 if (reloc->write_domain && target_obj->pending_write_domain &&
3404 reloc->write_domain != target_obj->pending_write_domain) {
673a394b
EA		 3405 DRM_ERROR("Write domain conflict: "
3406 "obj %p target %d offset %d "
3407 "new %08x old %08x\n",
40a5f0de
EA		 3408 obj, reloc->target_handle,
3409 (int) reloc->offset,
3410 reloc->write_domain,
673a394b
EA		 3411 target_obj->pending_write_domain);
3412 drm_gem_object_unreference(target_obj);
3413 i915_gem_object_unpin(obj);
3414 return -EINVAL;
3415 }
3416
40a5f0de
EA		 3417 target_obj->pending_read_domains |= reloc->read_domains;
3418 target_obj->pending_write_domain |= reloc->write_domain;
673a394b
EA		 3419
3420 /* If the relocation already has the right value in it, no
3421 * more work needs to be done.
3422 */
40a5f0de 3423 if (target_obj_priv->gtt_offset == reloc->presumed_offset) {
673a394b
EA		 3424 drm_gem_object_unreference(target_obj);
3425 continue;
3426 }
3427
8542a0bb
CW		 3428 /* Check that the relocation address is valid... */
3429 if (reloc->offset > obj->size - 4) {
3430 DRM_ERROR("Relocation beyond object bounds: "
3431 "obj %p target %d offset %d size %d.\n",
3432 obj, reloc->target_handle,
3433 (int) reloc->offset, (int) obj->size);
3434 drm_gem_object_unreference(target_obj);
3435 i915_gem_object_unpin(obj);
3436 return -EINVAL;
3437 }
3438 if (reloc->offset & 3) {
3439 DRM_ERROR("Relocation not 4-byte aligned: "
3440 "obj %p target %d offset %d.\n",
3441 obj, reloc->target_handle,
3442 (int) reloc->offset);
3443 drm_gem_object_unreference(target_obj);
3444 i915_gem_object_unpin(obj);
3445 return -EINVAL;
3446 }
3447
3448 /* and points to somewhere within the target object. */
3449 if (reloc->delta >= target_obj->size) {
3450 DRM_ERROR("Relocation beyond target object bounds: "
3451 "obj %p target %d delta %d size %d.\n",
3452 obj, reloc->target_handle,
3453 (int) reloc->delta, (int) target_obj->size);
3454 drm_gem_object_unreference(target_obj);
3455 i915_gem_object_unpin(obj);
3456 return -EINVAL;
3457 }
3458
2ef7eeaa
EA		 3459 ret = i915_gem_object_set_to_gtt_domain(obj, 1);
3460 if (ret != 0) {
3461 drm_gem_object_unreference(target_obj);
3462 i915_gem_object_unpin(obj);
3463 return -EINVAL;
673a394b
EA		 3464 }
3465
3466 /* Map the page containing the relocation we're going to
3467 * perform.
3468 */
40a5f0de 3469 reloc_offset = obj_priv->gtt_offset + reloc->offset;
0839ccb8
KP		 3470 reloc_page = io_mapping_map_atomic_wc(dev_priv->mm.gtt_mapping,
3471 (reloc_offset &
3472 ~(PAGE_SIZE - 1)));
3043c60c 3473 reloc_entry = (uint32_t __iomem *)(reloc_page +
0839ccb8 3474 (reloc_offset & (PAGE_SIZE - 1)));
40a5f0de 3475 reloc_val = target_obj_priv->gtt_offset + reloc->delta;
673a394b
EA		 3476
3477#if WATCH_BUF
3478 DRM_INFO("Applied relocation: %p@0x%08x %08x -> %08x\n",
40a5f0de 3479 obj, (unsigned int) reloc->offset,
673a394b
EA		 3480 readl(reloc_entry), reloc_val);
3481#endif
3482 writel(reloc_val, reloc_entry);
0839ccb8 3483 io_mapping_unmap_atomic(reloc_page);
673a394b 3484
40a5f0de
EA		 3485 /* The updated presumed offset for this entry will be
3486 * copied back out to the user.
673a394b 3487 */
40a5f0de 3488 reloc->presumed_offset = target_obj_priv->gtt_offset;
673a394b
EA		 3489
3490 drm_gem_object_unreference(target_obj);
3491 }
3492
673a394b
EA		 3493#if WATCH_BUF
3494 if (0)
3495 i915_gem_dump_object(obj, 128, __func__, ~0);
3496#endif
3497 return 0;
3498}
3499
673a394b
EA		 3500/* Throttle our rendering by waiting until the ring has completed our requests
3501 * emitted over 20 msec ago.
3502 *
b962442e
EA		 3503 * Note that if we were to use the current jiffies each time around the loop,
3504 * we wouldn't escape the function with any frames outstanding if the time to
3505 * render a frame was over 20ms.
3506 *
673a394b
EA		 3507 * This should get us reasonable parallelism between CPU and GPU but also
3508 * relatively low latency when blocking on a particular request to finish.
3509 */
3510static int
3511i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file_priv)
3512{
3513 struct drm_i915_file_private *i915_file_priv = file_priv->driver_priv;
3514 int ret = 0;
b962442e 3515 unsigned long recent_enough = jiffies - msecs_to_jiffies(20);
673a394b
EA		 3516
3517 mutex_lock(&dev->struct_mutex);
b962442e
EA		 3518 while (!list_empty(&i915_file_priv->mm.request_list)) {
3519 struct drm_i915_gem_request *request;
3520
3521 request = list_first_entry(&i915_file_priv->mm.request_list,
3522 struct drm_i915_gem_request,
3523 client_list);
3524
3525 if (time_after_eq(request->emitted_jiffies, recent_enough))
3526 break;
3527
852835f3 3528 ret = i915_wait_request(dev, request->seqno, request->ring);
b962442e
EA		 3529 if (ret != 0)
3530 break;
3531 }
673a394b 3532 mutex_unlock(&dev->struct_mutex);
b962442e 3533
673a394b
EA		 3534 return ret;
3535}
3536
40a5f0de 3537static int
76446cac 3538i915_gem_get_relocs_from_user(struct drm_i915_gem_exec_object2 *exec_list,
40a5f0de
EA		 3539 uint32_t buffer_count,
3540 struct drm_i915_gem_relocation_entry **relocs)
3541{
3542 uint32_t reloc_count = 0, reloc_index = 0, i;
3543 int ret;
3544
3545 *relocs = NULL;
3546 for (i = 0; i < buffer_count; i++) {
3547 if (reloc_count + exec_list[i].relocation_count < reloc_count)
3548 return -EINVAL;
3549 reloc_count += exec_list[i].relocation_count;
3550 }
3551
8e7d2b2c 3552 *relocs = drm_calloc_large(reloc_count, sizeof(**relocs));
76446cac
JB		 3553 if (*relocs == NULL) {
3554 DRM_ERROR("failed to alloc relocs, count %d\n", reloc_count);
40a5f0de 3555 return -ENOMEM;
76446cac 3556 }
40a5f0de
EA		 3557
3558 for (i = 0; i < buffer_count; i++) {
3559 struct drm_i915_gem_relocation_entry __user *user_relocs;
3560
3561 user_relocs = (void __user *)(uintptr_t)exec_list[i].relocs_ptr;
3562
3563 ret = copy_from_user(&(*relocs)[reloc_index],
3564 user_relocs,
3565 exec_list[i].relocation_count *
3566 sizeof(**relocs));
3567 if (ret != 0) {
8e7d2b2c 3568 drm_free_large(*relocs);
40a5f0de 3569 *relocs = NULL;
2bc43b5c 3570 return -EFAULT;
40a5f0de
EA		 3571 }
3572
3573 reloc_index += exec_list[i].relocation_count;
3574 }
3575
2bc43b5c 3576 return 0;
40a5f0de
EA		 3577}
3578
3579static int
76446cac 3580i915_gem_put_relocs_to_user(struct drm_i915_gem_exec_object2 *exec_list,
40a5f0de
EA		 3581 uint32_t buffer_count,
3582 struct drm_i915_gem_relocation_entry *relocs)
3583{
3584 uint32_t reloc_count = 0, i;
2bc43b5c 3585 int ret = 0;
40a5f0de 3586
93533c29
CW		 3587 if (relocs == NULL)
3588 return 0;
3589
40a5f0de
EA		 3590 for (i = 0; i < buffer_count; i++) {
3591 struct drm_i915_gem_relocation_entry __user *user_relocs;
2bc43b5c 3592 int unwritten;
40a5f0de
EA		 3593
3594 user_relocs = (void __user *)(uintptr_t)exec_list[i].relocs_ptr;
3595
2bc43b5c
FM		 3596 unwritten = copy_to_user(user_relocs,
3597 &relocs[reloc_count],
3598 exec_list[i].relocation_count *
3599 sizeof(*relocs));
3600
3601 if (unwritten) {
3602 ret = -EFAULT;
3603 goto err;
40a5f0de
EA		 3604 }
3605
3606 reloc_count += exec_list[i].relocation_count;
3607 }
3608
2bc43b5c 3609err:
8e7d2b2c 3610 drm_free_large(relocs);
40a5f0de
EA		 3611
3612 return ret;
3613}
3614
83d60795 3615static int
76446cac 3616i915_gem_check_execbuffer (struct drm_i915_gem_execbuffer2 *exec,
83d60795
CW		 3617 uint64_t exec_offset)
3618{
3619 uint32_t exec_start, exec_len;
3620
3621 exec_start = (uint32_t) exec_offset + exec->batch_start_offset;
3622 exec_len = (uint32_t) exec->batch_len;
3623
3624 if ((exec_start | exec_len) & 0x7)
3625 return -EINVAL;
3626
3627 if (!exec_start)
3628 return -EINVAL;
3629
3630 return 0;
3631}
3632
6b95a207
KH		 3633static int
3634i915_gem_wait_for_pending_flip(struct drm_device *dev,
3635 struct drm_gem_object **object_list,
3636 int count)
3637{
3638 drm_i915_private_t *dev_priv = dev->dev_private;
3639 struct drm_i915_gem_object *obj_priv;
3640 DEFINE_WAIT(wait);
3641 int i, ret = 0;
3642
3643 for (;;) {
3644 prepare_to_wait(&dev_priv->pending_flip_queue,
3645 &wait, TASK_INTERRUPTIBLE);
3646 for (i = 0; i < count; i++) {
23010e43 3647 obj_priv = to_intel_bo(object_list[i]);
6b95a207
KH		 3648 if (atomic_read(&obj_priv->pending_flip) > 0)
3649 break;
3650 }
3651 if (i == count)
3652 break;
3653
3654 if (!signal_pending(current)) {
3655 mutex_unlock(&dev->struct_mutex);
3656 schedule();
3657 mutex_lock(&dev->struct_mutex);
3658 continue;
3659 }
3660 ret = -ERESTARTSYS;
3661 break;
3662 }
3663 finish_wait(&dev_priv->pending_flip_queue, &wait);
3664
3665 return ret;
3666}
3667
673a394b 3668int
76446cac
JB		 3669i915_gem_do_execbuffer(struct drm_device *dev, void *data,
3670 struct drm_file *file_priv,
3671 struct drm_i915_gem_execbuffer2 *args,
3672 struct drm_i915_gem_exec_object2 *exec_list)
673a394b
EA		 3673{
3674 drm_i915_private_t *dev_priv = dev->dev_private;
673a394b
EA		 3675 struct drm_gem_object **object_list = NULL;
3676 struct drm_gem_object *batch_obj;
b70d11da 3677 struct drm_i915_gem_object *obj_priv;
201361a5 3678 struct drm_clip_rect *cliprects = NULL;
93533c29 3679 struct drm_i915_gem_relocation_entry *relocs = NULL;
76446cac 3680 int ret = 0, ret2, i, pinned = 0;
673a394b 3681 uint64_t exec_offset;
40a5f0de 3682 uint32_t seqno, flush_domains, reloc_index;
6b95a207 3683 int pin_tries, flips;
673a394b 3684
852835f3
ZN		 3685 struct intel_ring_buffer *ring = NULL;
3686
673a394b
EA		 3687#if WATCH_EXEC
3688 DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n",
3689 (int) args->buffers_ptr, args->buffer_count, args->batch_len);
3690#endif
d1b851fc
ZN		 3691 if (args->flags & I915_EXEC_BSD) {
3692 if (!HAS_BSD(dev)) {
3693 DRM_ERROR("execbuf with wrong flag\n");
3694 return -EINVAL;
3695 }
3696 ring = &dev_priv->bsd_ring;
3697 } else {
3698 ring = &dev_priv->render_ring;
3699 }
3700
673a394b 3701
4f481ed2
EA		 3702 if (args->buffer_count < 1) {
3703 DRM_ERROR("execbuf with %d buffers\n", args->buffer_count);
3704 return -EINVAL;
3705 }
c8e0f93a 3706 object_list = drm_malloc_ab(sizeof(*object_list), args->buffer_count);
76446cac
JB		 3707 if (object_list == NULL) {
3708 DRM_ERROR("Failed to allocate object list for %d buffers\n",
673a394b
EA		 3709 args->buffer_count);
3710 ret = -ENOMEM;
3711 goto pre_mutex_err;
3712 }
673a394b 3713
201361a5 3714 if (args->num_cliprects != 0) {
9a298b2a
EA		 3715 cliprects = kcalloc(args->num_cliprects, sizeof(*cliprects),
3716 GFP_KERNEL);
a40e8d31
OA		 3717 if (cliprects == NULL) {
3718 ret = -ENOMEM;
201361a5 3719 goto pre_mutex_err;
a40e8d31 3720 }
201361a5
EA		 3721
3722 ret = copy_from_user(cliprects,
3723 (struct drm_clip_rect __user *)
3724 (uintptr_t) args->cliprects_ptr,
3725 sizeof(*cliprects) * args->num_cliprects);
3726 if (ret != 0) {
3727 DRM_ERROR("copy %d cliprects failed: %d\n",
3728 args->num_cliprects, ret);
3729 goto pre_mutex_err;
3730 }
3731 }
3732
40a5f0de
EA		 3733 ret = i915_gem_get_relocs_from_user(exec_list, args->buffer_count,
3734 &relocs);
3735 if (ret != 0)
3736 goto pre_mutex_err;
3737
673a394b
EA		 3738 mutex_lock(&dev->struct_mutex);
3739
3740 i915_verify_inactive(dev, __FILE__, __LINE__);
3741
ba1234d1 3742 if (atomic_read(&dev_priv->mm.wedged)) {
673a394b 3743 mutex_unlock(&dev->struct_mutex);
a198bc80
CW		 3744 ret = -EIO;
3745 goto pre_mutex_err;
673a394b
EA		 3746 }
3747
3748 if (dev_priv->mm.suspended) {
673a394b 3749 mutex_unlock(&dev->struct_mutex);
a198bc80
CW		 3750 ret = -EBUSY;
3751 goto pre_mutex_err;
673a394b
EA		 3752 }
3753
ac94a962 3754 /* Look up object handles */
6b95a207 3755 flips = 0;
673a394b
EA		 3756 for (i = 0; i < args->buffer_count; i++) {
3757 object_list[i] = drm_gem_object_lookup(dev, file_priv,
3758 exec_list[i].handle);
3759 if (object_list[i] == NULL) {
3760 DRM_ERROR("Invalid object handle %d at index %d\n",
3761 exec_list[i].handle, i);
0ce907f8
CW		 3762 /* prevent error path from reading uninitialized data */
3763 args->buffer_count = i + 1;
673a394b
EA		 3764 ret = -EBADF;
3765 goto err;
3766 }
b70d11da 3767
23010e43 3768 obj_priv = to_intel_bo(object_list[i]);
b70d11da
KH		 3769 if (obj_priv->in_execbuffer) {
3770 DRM_ERROR("Object %p appears more than once in object list\n",
3771 object_list[i]);
0ce907f8
CW		 3772 /* prevent error path from reading uninitialized data */
3773 args->buffer_count = i + 1;
b70d11da
KH		 3774 ret = -EBADF;
3775 goto err;
3776 }
3777 obj_priv->in_execbuffer = true;
6b95a207
KH		 3778 flips += atomic_read(&obj_priv->pending_flip);
3779 }
3780
3781 if (flips > 0) {
3782 ret = i915_gem_wait_for_pending_flip(dev, object_list,
3783 args->buffer_count);
3784 if (ret)
3785 goto err;
ac94a962 3786 }
673a394b 3787
ac94a962
KP		 3788 /* Pin and relocate */
3789 for (pin_tries = 0; ; pin_tries++) {
3790 ret = 0;
40a5f0de
EA		 3791 reloc_index = 0;
3792
ac94a962
KP		 3793 for (i = 0; i < args->buffer_count; i++) {
3794 object_list[i]->pending_read_domains = 0;
3795 object_list[i]->pending_write_domain = 0;
3796 ret = i915_gem_object_pin_and_relocate(object_list[i],
3797 file_priv,
40a5f0de
EA		 3798 &exec_list[i],
3799 &relocs[reloc_index]);
ac94a962
KP		 3800 if (ret)
3801 break;
3802 pinned = i + 1;
40a5f0de 3803 reloc_index += exec_list[i].relocation_count;
ac94a962
KP		 3804 }
3805 /* success */
3806 if (ret == 0)
3807 break;
3808
3809 /* error other than GTT full, or we've already tried again */
2939e1f5 3810 if (ret != -ENOSPC || pin_tries >= 1) {
07f73f69
CW		 3811 if (ret != -ERESTARTSYS) {
3812 unsigned long long total_size = 0;
3813 for (i = 0; i < args->buffer_count; i++)
3814 total_size += object_list[i]->size;
3815 DRM_ERROR("Failed to pin buffer %d of %d, total %llu bytes: %d\n",
3816 pinned+1, args->buffer_count,
3817 total_size, ret);
3818 DRM_ERROR("%d objects [%d pinned], "
3819 "%d object bytes [%d pinned], "
3820 "%d/%d gtt bytes\n",
3821 atomic_read(&dev->object_count),
3822 atomic_read(&dev->pin_count),
3823 atomic_read(&dev->object_memory),
3824 atomic_read(&dev->pin_memory),
3825 atomic_read(&dev->gtt_memory),
3826 dev->gtt_total);
3827 }
673a394b
EA		 3828 goto err;
3829 }
ac94a962
KP		 3830
3831 /* unpin all of our buffers */
3832 for (i = 0; i < pinned; i++)
3833 i915_gem_object_unpin(object_list[i]);
b1177636 3834 pinned = 0;
ac94a962
KP		 3835
3836 /* evict everyone we can from the aperture */
3837 ret = i915_gem_evict_everything(dev);
07f73f69 3838 if (ret && ret != -ENOSPC)
ac94a962 3839 goto err;
673a394b
EA		 3840 }
3841
3842 /* Set the pending read domains for the batch buffer to COMMAND */
3843 batch_obj = object_list[args->buffer_count-1];
5f26a2c7
CW		 3844 if (batch_obj->pending_write_domain) {
3845 DRM_ERROR("Attempting to use self-modifying batch buffer\n");
3846 ret = -EINVAL;
3847 goto err;
3848 }
3849 batch_obj->pending_read_domains |= I915_GEM_DOMAIN_COMMAND;
673a394b 3850
83d60795
CW		 3851 /* Sanity check the batch buffer, prior to moving objects */
3852 exec_offset = exec_list[args->buffer_count - 1].offset;
3853 ret = i915_gem_check_execbuffer (args, exec_offset);
3854 if (ret != 0) {
3855 DRM_ERROR("execbuf with invalid offset/length\n");
3856 goto err;
3857 }
3858
673a394b
EA		 3859 i915_verify_inactive(dev, __FILE__, __LINE__);
3860
646f0f6e
KP		 3861 /* Zero the global flush/invalidate flags. These
3862 * will be modified as new domains are computed
3863 * for each object
3864 */
3865 dev->invalidate_domains = 0;
3866 dev->flush_domains = 0;
3867
673a394b
EA		 3868 for (i = 0; i < args->buffer_count; i++) {
3869 struct drm_gem_object *obj = object_list[i];
673a394b 3870
646f0f6e 3871 /* Compute new gpu domains and update invalidate/flush */
8b0e378a 3872 i915_gem_object_set_to_gpu_domain(obj);
673a394b
EA		 3873 }
3874
3875 i915_verify_inactive(dev, __FILE__, __LINE__);
3876
646f0f6e
KP		 3877 if (dev->invalidate_domains | dev->flush_domains) {
3878#if WATCH_EXEC
3879 DRM_INFO("%s: invalidate_domains %08x flush_domains %08x\n",
3880 __func__,
3881 dev->invalidate_domains,
3882 dev->flush_domains);
3883#endif
3884 i915_gem_flush(dev,
3885 dev->invalidate_domains,
3886 dev->flush_domains);
852835f3 3887 if (dev->flush_domains & I915_GEM_GPU_DOMAINS) {
b962442e 3888 (void)i915_add_request(dev, file_priv,
852835f3
ZN		 3889 dev->flush_domains,
3890 &dev_priv->render_ring);
3891
d1b851fc
ZN		 3892 if (HAS_BSD(dev))
3893 (void)i915_add_request(dev, file_priv,
3894 dev->flush_domains,
3895 &dev_priv->bsd_ring);
852835f3 3896 }
646f0f6e 3897 }
673a394b 3898
efbeed96
EA		 3899 for (i = 0; i < args->buffer_count; i++) {
3900 struct drm_gem_object *obj = object_list[i];
23010e43 3901 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1c5d22f7 3902 uint32_t old_write_domain = obj->write_domain;
efbeed96
EA		 3903
3904 obj->write_domain = obj->pending_write_domain;
99fcb766
DV		 3905 if (obj->write_domain)
3906 list_move_tail(&obj_priv->gpu_write_list,
3907 &dev_priv->mm.gpu_write_list);
3908 else
3909 list_del_init(&obj_priv->gpu_write_list);
3910
1c5d22f7
CW		 3911 trace_i915_gem_object_change_domain(obj,
3912 obj->read_domains,
3913 old_write_domain);
efbeed96
EA		 3914 }
3915
673a394b
EA		 3916 i915_verify_inactive(dev, __FILE__, __LINE__);
3917
3918#if WATCH_COHERENCY
3919 for (i = 0; i < args->buffer_count; i++) {
3920 i915_gem_object_check_coherency(object_list[i],
3921 exec_list[i].handle);
3922 }
3923#endif
3924
673a394b 3925#if WATCH_EXEC
6911a9b8 3926 i915_gem_dump_object(batch_obj,
673a394b
EA		 3927 args->batch_len,
3928 __func__,
3929 ~0);
3930#endif
3931
673a394b 3932 /* Exec the batchbuffer */
852835f3
ZN		 3933 ret = ring->dispatch_gem_execbuffer(dev, ring, args,
3934 cliprects, exec_offset);
673a394b
EA		 3935 if (ret) {
3936 DRM_ERROR("dispatch failed %d\n", ret);
3937 goto err;
3938 }
3939
3940 /*
3941 * Ensure that the commands in the batch buffer are
3942 * finished before the interrupt fires
3943 */
852835f3 3944 flush_domains = i915_retire_commands(dev, ring);
673a394b
EA		 3945
3946 i915_verify_inactive(dev, __FILE__, __LINE__);
3947
3948 /*
3949 * Get a seqno representing the execution of the current buffer,
3950 * which we can wait on. We would like to mitigate these interrupts,
3951 * likely by only creating seqnos occasionally (so that we have
3952 * *some* interrupts representing completion of buffers that we can
3953 * wait on when trying to clear up gtt space).
3954 */
852835f3 3955 seqno = i915_add_request(dev, file_priv, flush_domains, ring);
673a394b 3956 BUG_ON(seqno == 0);
673a394b
EA		 3957 for (i = 0; i < args->buffer_count; i++) {
3958 struct drm_gem_object *obj = object_list[i];
852835f3 3959 obj_priv = to_intel_bo(obj);
673a394b 3960
852835f3 3961 i915_gem_object_move_to_active(obj, seqno, ring);
673a394b
EA		 3962#if WATCH_LRU
3963 DRM_INFO("%s: move to exec list %p\n", __func__, obj);
3964#endif
3965 }
3966#if WATCH_LRU
3967 i915_dump_lru(dev, __func__);
3968#endif
3969
3970 i915_verify_inactive(dev, __FILE__, __LINE__);
3971
673a394b 3972err:
aad87dff
JL		 3973 for (i = 0; i < pinned; i++)
3974 i915_gem_object_unpin(object_list[i]);
3975
b70d11da
KH		 3976 for (i = 0; i < args->buffer_count; i++) {
3977 if (object_list[i]) {
23010e43 3978 obj_priv = to_intel_bo(object_list[i]);
b70d11da
KH		 3979 obj_priv->in_execbuffer = false;
3980 }
aad87dff 3981 drm_gem_object_unreference(object_list[i]);
b70d11da 3982 }
673a394b 3983
673a394b
EA		 3984 mutex_unlock(&dev->struct_mutex);
3985
93533c29 3986pre_mutex_err:
40a5f0de
EA		 3987 /* Copy the updated relocations out regardless of current error
3988 * state. Failure to update the relocs would mean that the next
3989 * time userland calls execbuf, it would do so with presumed offset
3990 * state that didn't match the actual object state.
3991 */
3992 ret2 = i915_gem_put_relocs_to_user(exec_list, args->buffer_count,
3993 relocs);
3994 if (ret2 != 0) {
3995 DRM_ERROR("Failed to copy relocations back out: %d\n", ret2);
3996
3997 if (ret == 0)
3998 ret = ret2;
3999 }
4000
8e7d2b2c 4001 drm_free_large(object_list);
9a298b2a 4002 kfree(cliprects);
673a394b
EA		 4003
4004 return ret;
4005}
4006
76446cac
JB		 4007/*
4008 * Legacy execbuffer just creates an exec2 list from the original exec object
4009 * list array and passes it to the real function.
4010 */
4011int
4012i915_gem_execbuffer(struct drm_device *dev, void *data,
4013 struct drm_file *file_priv)
4014{
4015 struct drm_i915_gem_execbuffer *args = data;
4016 struct drm_i915_gem_execbuffer2 exec2;
4017 struct drm_i915_gem_exec_object *exec_list = NULL;
4018 struct drm_i915_gem_exec_object2 *exec2_list = NULL;
4019 int ret, i;
4020
4021#if WATCH_EXEC
4022 DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n",
4023 (int) args->buffers_ptr, args->buffer_count, args->batch_len);
4024#endif
4025
4026 if (args->buffer_count < 1) {
4027 DRM_ERROR("execbuf with %d buffers\n", args->buffer_count);
4028 return -EINVAL;
4029 }
4030
4031 /* Copy in the exec list from userland */
4032 exec_list = drm_malloc_ab(sizeof(*exec_list), args->buffer_count);
4033 exec2_list = drm_malloc_ab(sizeof(*exec2_list), args->buffer_count);
4034 if (exec_list == NULL || exec2_list == NULL) {
4035 DRM_ERROR("Failed to allocate exec list for %d buffers\n",
4036 args->buffer_count);
4037 drm_free_large(exec_list);
4038 drm_free_large(exec2_list);
4039 return -ENOMEM;
4040 }
4041 ret = copy_from_user(exec_list,
4042 (struct drm_i915_relocation_entry __user *)
4043 (uintptr_t) args->buffers_ptr,
4044 sizeof(*exec_list) * args->buffer_count);
4045 if (ret != 0) {
4046 DRM_ERROR("copy %d exec entries failed %d\n",
4047 args->buffer_count, ret);
4048 drm_free_large(exec_list);
4049 drm_free_large(exec2_list);
4050 return -EFAULT;
4051 }
4052
4053 for (i = 0; i < args->buffer_count; i++) {
4054 exec2_list[i].handle = exec_list[i].handle;
4055 exec2_list[i].relocation_count = exec_list[i].relocation_count;
4056 exec2_list[i].relocs_ptr = exec_list[i].relocs_ptr;
4057 exec2_list[i].alignment = exec_list[i].alignment;
4058 exec2_list[i].offset = exec_list[i].offset;
4059 if (!IS_I965G(dev))
4060 exec2_list[i].flags = EXEC_OBJECT_NEEDS_FENCE;
4061 else
4062 exec2_list[i].flags = 0;
4063 }
4064
4065 exec2.buffers_ptr = args->buffers_ptr;
4066 exec2.buffer_count = args->buffer_count;
4067 exec2.batch_start_offset = args->batch_start_offset;
4068 exec2.batch_len = args->batch_len;
4069 exec2.DR1 = args->DR1;
4070 exec2.DR4 = args->DR4;
4071 exec2.num_cliprects = args->num_cliprects;
4072 exec2.cliprects_ptr = args->cliprects_ptr;
852835f3 4073 exec2.flags = I915_EXEC_RENDER;
76446cac
JB		 4074
4075 ret = i915_gem_do_execbuffer(dev, data, file_priv, &exec2, exec2_list);
4076 if (!ret) {
4077 /* Copy the new buffer offsets back to the user's exec list. */
4078 for (i = 0; i < args->buffer_count; i++)
4079 exec_list[i].offset = exec2_list[i].offset;
4080 /* ... and back out to userspace */
4081 ret = copy_to_user((struct drm_i915_relocation_entry __user *)
4082 (uintptr_t) args->buffers_ptr,
4083 exec_list,
4084 sizeof(*exec_list) * args->buffer_count);
4085 if (ret) {
4086 ret = -EFAULT;
4087 DRM_ERROR("failed to copy %d exec entries "
4088 "back to user (%d)\n",
4089 args->buffer_count, ret);
4090 }
76446cac
JB		 4091 }
4092
4093 drm_free_large(exec_list);
4094 drm_free_large(exec2_list);
4095 return ret;
4096}
4097
4098int
4099i915_gem_execbuffer2(struct drm_device *dev, void *data,
4100 struct drm_file *file_priv)
4101{
4102 struct drm_i915_gem_execbuffer2 *args = data;
4103 struct drm_i915_gem_exec_object2 *exec2_list = NULL;
4104 int ret;
4105
4106#if WATCH_EXEC
4107 DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n",
4108 (int) args->buffers_ptr, args->buffer_count, args->batch_len);
4109#endif
4110
4111 if (args->buffer_count < 1) {
4112 DRM_ERROR("execbuf2 with %d buffers\n", args->buffer_count);
4113 return -EINVAL;
4114 }
4115
4116 exec2_list = drm_malloc_ab(sizeof(*exec2_list), args->buffer_count);
4117 if (exec2_list == NULL) {
4118 DRM_ERROR("Failed to allocate exec list for %d buffers\n",
4119 args->buffer_count);
4120 return -ENOMEM;
4121 }
4122 ret = copy_from_user(exec2_list,
4123 (struct drm_i915_relocation_entry __user *)
4124 (uintptr_t) args->buffers_ptr,
4125 sizeof(*exec2_list) * args->buffer_count);
4126 if (ret != 0) {
4127 DRM_ERROR("copy %d exec entries failed %d\n",
4128 args->buffer_count, ret);
4129 drm_free_large(exec2_list);
4130 return -EFAULT;
4131 }
4132
4133 ret = i915_gem_do_execbuffer(dev, data, file_priv, args, exec2_list);
4134 if (!ret) {
4135 /* Copy the new buffer offsets back to the user's exec list. */
4136 ret = copy_to_user((struct drm_i915_relocation_entry __user *)
4137 (uintptr_t) args->buffers_ptr,
4138 exec2_list,
4139 sizeof(*exec2_list) * args->buffer_count);
4140 if (ret) {
4141 ret = -EFAULT;
4142 DRM_ERROR("failed to copy %d exec entries "
4143 "back to user (%d)\n",
4144 args->buffer_count, ret);
4145 }
4146 }
4147
4148 drm_free_large(exec2_list);
4149 return ret;
4150}
4151
673a394b
EA		 4152int
4153i915_gem_object_pin(struct drm_gem_object *obj, uint32_t alignment)
4154{
4155 struct drm_device *dev = obj->dev;
23010e43 4156 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
673a394b
EA		 4157 int ret;
4158
4159 i915_verify_inactive(dev, __FILE__, __LINE__);
4160 if (obj_priv->gtt_space == NULL) {
4161 ret = i915_gem_object_bind_to_gtt(obj, alignment);
9731129c 4162 if (ret)
673a394b 4163 return ret;
22c344e9 4164 }
76446cac 4165
673a394b
EA		 4166 obj_priv->pin_count++;
4167
4168 /* If the object is not active and not pending a flush,
4169 * remove it from the inactive list
4170 */
4171 if (obj_priv->pin_count == 1) {
4172 atomic_inc(&dev->pin_count);
4173 atomic_add(obj->size, &dev->pin_memory);
4174 if (!obj_priv->active &&
21d509e3 4175 (obj->write_domain & I915_GEM_GPU_DOMAINS) == 0 &&
673a394b
EA		 4176 !list_empty(&obj_priv->list))
4177 list_del_init(&obj_priv->list);
4178 }
4179 i915_verify_inactive(dev, __FILE__, __LINE__);
4180
4181 return 0;
4182}
4183
4184void
4185i915_gem_object_unpin(struct drm_gem_object *obj)
4186{
4187 struct drm_device *dev = obj->dev;
4188 drm_i915_private_t *dev_priv = dev->dev_private;
23010e43 4189 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
673a394b
EA		 4190
4191 i915_verify_inactive(dev, __FILE__, __LINE__);
4192 obj_priv->pin_count--;
4193 BUG_ON(obj_priv->pin_count < 0);
4194 BUG_ON(obj_priv->gtt_space == NULL);
4195
4196 /* If the object is no longer pinned, and is
4197 * neither active nor being flushed, then stick it on
4198 * the inactive list
4199 */
4200 if (obj_priv->pin_count == 0) {
4201 if (!obj_priv->active &&
21d509e3 4202 (obj->write_domain & I915_GEM_GPU_DOMAINS) == 0)
673a394b
EA		 4203 list_move_tail(&obj_priv->list,
4204 &dev_priv->mm.inactive_list);
4205 atomic_dec(&dev->pin_count);
4206 atomic_sub(obj->size, &dev->pin_memory);
4207 }
4208 i915_verify_inactive(dev, __FILE__, __LINE__);
4209}
4210
4211int
4212i915_gem_pin_ioctl(struct drm_device *dev, void *data,
4213 struct drm_file *file_priv)
4214{
4215 struct drm_i915_gem_pin *args = data;
4216 struct drm_gem_object *obj;
4217 struct drm_i915_gem_object *obj_priv;
4218 int ret;
4219
4220 mutex_lock(&dev->struct_mutex);
4221
4222 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
4223 if (obj == NULL) {
4224 DRM_ERROR("Bad handle in i915_gem_pin_ioctl(): %d\n",
4225 args->handle);
4226 mutex_unlock(&dev->struct_mutex);
4227 return -EBADF;
4228 }
23010e43 4229 obj_priv = to_intel_bo(obj);
673a394b 4230
bb6baf76
CW		 4231 if (obj_priv->madv != I915_MADV_WILLNEED) {
4232 DRM_ERROR("Attempting to pin a purgeable buffer\n");
3ef94daa
CW		 4233 drm_gem_object_unreference(obj);
4234 mutex_unlock(&dev->struct_mutex);
4235 return -EINVAL;
4236 }
4237
79e53945
JB		 4238 if (obj_priv->pin_filp != NULL && obj_priv->pin_filp != file_priv) {
4239 DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n",
4240 args->handle);
96dec61d 4241 drm_gem_object_unreference(obj);
673a394b 4242 mutex_unlock(&dev->struct_mutex);
79e53945
JB		 4243 return -EINVAL;
4244 }
4245
4246 obj_priv->user_pin_count++;
4247 obj_priv->pin_filp = file_priv;
4248 if (obj_priv->user_pin_count == 1) {
4249 ret = i915_gem_object_pin(obj, args->alignment);
4250 if (ret != 0) {
4251 drm_gem_object_unreference(obj);
4252 mutex_unlock(&dev->struct_mutex);
4253 return ret;
4254 }
673a394b
EA		 4255 }
4256
4257 /* XXX - flush the CPU caches for pinned objects
4258 * as the X server doesn't manage domains yet
4259 */
e47c68e9 4260 i915_gem_object_flush_cpu_write_domain(obj);
673a394b
EA		 4261 args->offset = obj_priv->gtt_offset;
4262 drm_gem_object_unreference(obj);
4263 mutex_unlock(&dev->struct_mutex);
4264
4265 return 0;
4266}
4267
4268int
4269i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
4270 struct drm_file *file_priv)
4271{
4272 struct drm_i915_gem_pin *args = data;
4273 struct drm_gem_object *obj;
79e53945 4274 struct drm_i915_gem_object *obj_priv;
673a394b
EA		 4275
4276 mutex_lock(&dev->struct_mutex);
4277
4278 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
4279 if (obj == NULL) {
4280 DRM_ERROR("Bad handle in i915_gem_unpin_ioctl(): %d\n",
4281 args->handle);
4282 mutex_unlock(&dev->struct_mutex);
4283 return -EBADF;
4284 }
4285
23010e43 4286 obj_priv = to_intel_bo(obj);
79e53945
JB		 4287 if (obj_priv->pin_filp != file_priv) {
4288 DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n",
4289 args->handle);
4290 drm_gem_object_unreference(obj);
4291 mutex_unlock(&dev->struct_mutex);
4292 return -EINVAL;
4293 }
4294 obj_priv->user_pin_count--;
4295 if (obj_priv->user_pin_count == 0) {
4296 obj_priv->pin_filp = NULL;
4297 i915_gem_object_unpin(obj);
4298 }
673a394b
EA		 4299
4300 drm_gem_object_unreference(obj);
4301 mutex_unlock(&dev->struct_mutex);
4302 return 0;
4303}
4304
4305int
4306i915_gem_busy_ioctl(struct drm_device *dev, void *data,
4307 struct drm_file *file_priv)
4308{
4309 struct drm_i915_gem_busy *args = data;
4310 struct drm_gem_object *obj;
4311 struct drm_i915_gem_object *obj_priv;
852835f3 4312 drm_i915_private_t *dev_priv = dev->dev_private;
673a394b 4313
673a394b
EA		 4314 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
4315 if (obj == NULL) {
4316 DRM_ERROR("Bad handle in i915_gem_busy_ioctl(): %d\n",
4317 args->handle);
673a394b
EA		 4318 return -EBADF;
4319 }
4320
b1ce786c 4321 mutex_lock(&dev->struct_mutex);
f21289b3
EA		 4322 /* Update the active list for the hardware's current position.
4323 * Otherwise this only updates on a delayed timer or when irqs are
4324 * actually unmasked, and our working set ends up being larger than
4325 * required.
4326 */
852835f3 4327 i915_gem_retire_requests(dev, &dev_priv->render_ring);
f21289b3 4328
d1b851fc
ZN		 4329 if (HAS_BSD(dev))
4330 i915_gem_retire_requests(dev, &dev_priv->bsd_ring);
4331
23010e43 4332 obj_priv = to_intel_bo(obj);
c4de0a5d
EA		 4333 /* Don't count being on the flushing list against the object being
4334 * done. Otherwise, a buffer left on the flushing list but not getting
4335 * flushed (because nobody's flushing that domain) won't ever return
4336 * unbusy and get reused by libdrm's bo cache. The other expected
4337 * consumer of this interface, OpenGL's occlusion queries, also specs
4338 * that the objects get unbusy "eventually" without any interference.
4339 */
4340 args->busy = obj_priv->active && obj_priv->last_rendering_seqno != 0;
673a394b
EA		 4341
4342 drm_gem_object_unreference(obj);
4343 mutex_unlock(&dev->struct_mutex);
4344 return 0;
4345}
4346
4347int
4348i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
4349 struct drm_file *file_priv)
4350{
4351 return i915_gem_ring_throttle(dev, file_priv);
4352}
4353
3ef94daa
CW		 4354int
4355i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
4356 struct drm_file *file_priv)
4357{
4358 struct drm_i915_gem_madvise *args = data;
4359 struct drm_gem_object *obj;
4360 struct drm_i915_gem_object *obj_priv;
4361
4362 switch (args->madv) {
4363 case I915_MADV_DONTNEED:
4364 case I915_MADV_WILLNEED:
4365 break;
4366 default:
4367 return -EINVAL;
4368 }
4369
4370 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
4371 if (obj == NULL) {
4372 DRM_ERROR("Bad handle in i915_gem_madvise_ioctl(): %d\n",
4373 args->handle);
4374 return -EBADF;
4375 }
4376
4377 mutex_lock(&dev->struct_mutex);
23010e43 4378 obj_priv = to_intel_bo(obj);
3ef94daa
CW		 4379
4380 if (obj_priv->pin_count) {
4381 drm_gem_object_unreference(obj);
4382 mutex_unlock(&dev->struct_mutex);
4383
4384 DRM_ERROR("Attempted i915_gem_madvise_ioctl() on a pinned object\n");
4385 return -EINVAL;
4386 }
4387
bb6baf76
CW		 4388 if (obj_priv->madv != __I915_MADV_PURGED)
4389 obj_priv->madv = args->madv;
3ef94daa 4390
2d7ef395
CW		 4391 /* if the object is no longer bound, discard its backing storage */
4392 if (i915_gem_object_is_purgeable(obj_priv) &&
4393 obj_priv->gtt_space == NULL)
4394 i915_gem_object_truncate(obj);
4395
bb6baf76
CW		 4396 args->retained = obj_priv->madv != __I915_MADV_PURGED;
4397
3ef94daa
CW		 4398 drm_gem_object_unreference(obj);
4399 mutex_unlock(&dev->struct_mutex);
4400
4401 return 0;
4402}
4403
ac52bc56
DV		 4404struct drm_gem_object * i915_gem_alloc_object(struct drm_device *dev,
4405 size_t size)
4406{
c397b908 4407 struct drm_i915_gem_object *obj;
ac52bc56 4408
c397b908
DV		 4409 obj = kzalloc(sizeof(*obj), GFP_KERNEL);
4410 if (obj == NULL)
4411 return NULL;
673a394b 4412
c397b908
DV		 4413 if (drm_gem_object_init(dev, &obj->base, size) != 0) {
4414 kfree(obj);
4415 return NULL;
4416 }
673a394b 4417
c397b908
DV		 4418 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
4419 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
673a394b 4420
c397b908 4421 obj->agp_type = AGP_USER_MEMORY;
62b8b215 4422 obj->base.driver_private = NULL;
c397b908
DV		 4423 obj->fence_reg = I915_FENCE_REG_NONE;
4424 INIT_LIST_HEAD(&obj->list);
4425 INIT_LIST_HEAD(&obj->gpu_write_list);
c397b908 4426 obj->madv = I915_MADV_WILLNEED;
de151cf6 4427
c397b908
DV		 4428 trace_i915_gem_object_create(&obj->base);
4429
4430 return &obj->base;
4431}
4432
4433int i915_gem_init_object(struct drm_gem_object *obj)
4434{
4435 BUG();
de151cf6 4436
673a394b
EA		 4437 return 0;
4438}
4439
4440void i915_gem_free_object(struct drm_gem_object *obj)
4441{
de151cf6 4442 struct drm_device *dev = obj->dev;
23010e43 4443 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
673a394b 4444
1c5d22f7
CW		 4445 trace_i915_gem_object_destroy(obj);
4446
673a394b
EA		 4447 while (obj_priv->pin_count > 0)
4448 i915_gem_object_unpin(obj);
4449
71acb5eb
DA		 4450 if (obj_priv->phys_obj)
4451 i915_gem_detach_phys_object(dev, obj);
4452
673a394b
EA		 4453 i915_gem_object_unbind(obj);
4454
7e616158
CW		 4455 if (obj_priv->mmap_offset)
4456 i915_gem_free_mmap_offset(obj);
de151cf6 4457
c397b908
DV		 4458 drm_gem_object_release(obj);
4459
9a298b2a 4460 kfree(obj_priv->page_cpu_valid);
280b713b 4461 kfree(obj_priv->bit_17);
c397b908 4462 kfree(obj_priv);
673a394b
EA		 4463}
4464
ab5ee576 4465/** Unbinds all inactive objects. */
673a394b 4466static int
ab5ee576 4467i915_gem_evict_from_inactive_list(struct drm_device *dev)
673a394b 4468{
ab5ee576 4469 drm_i915_private_t *dev_priv = dev->dev_private;
673a394b 4470
ab5ee576
CW		 4471 while (!list_empty(&dev_priv->mm.inactive_list)) {
4472 struct drm_gem_object *obj;
4473 int ret;
673a394b 4474
a8089e84
DV		 4475 obj = &list_first_entry(&dev_priv->mm.inactive_list,
4476 struct drm_i915_gem_object,
4477 list)->base;
673a394b
EA		 4478
4479 ret = i915_gem_object_unbind(obj);
4480 if (ret != 0) {
ab5ee576 4481 DRM_ERROR("Error unbinding object: %d\n", ret);
673a394b
EA		 4482 return ret;
4483 }
4484 }
4485
673a394b
EA		 4486 return 0;
4487}
4488
29105ccc
CW		 4489int
4490i915_gem_idle(struct drm_device *dev)
4491{
4492 drm_i915_private_t *dev_priv = dev->dev_private;
4493 int ret;
28dfe52a 4494
29105ccc 4495 mutex_lock(&dev->struct_mutex);
1c5d22f7 4496
8187a2b7 4497 if (dev_priv->mm.suspended ||
d1b851fc
ZN		 4498 (dev_priv->render_ring.gem_object == NULL) ||
4499 (HAS_BSD(dev) &&
4500 dev_priv->bsd_ring.gem_object == NULL)) {
29105ccc
CW		 4501 mutex_unlock(&dev->struct_mutex);
4502 return 0;
28dfe52a
EA		 4503 }
4504
29105ccc 4505 ret = i915_gpu_idle(dev);
6dbe2772
KP		 4506 if (ret) {
4507 mutex_unlock(&dev->struct_mutex);
673a394b 4508 return ret;
6dbe2772 4509 }
673a394b 4510
29105ccc
CW		 4511 /* Under UMS, be paranoid and evict. */
4512 if (!drm_core_check_feature(dev, DRIVER_MODESET)) {
4513 ret = i915_gem_evict_from_inactive_list(dev);
4514 if (ret) {
4515 mutex_unlock(&dev->struct_mutex);
4516 return ret;
4517 }
4518 }
4519
4520 /* Hack! Don't let anybody do execbuf while we don't control the chip.
4521 * We need to replace this with a semaphore, or something.
4522 * And not confound mm.suspended!
4523 */
4524 dev_priv->mm.suspended = 1;
4525 del_timer(&dev_priv->hangcheck_timer);
4526
4527 i915_kernel_lost_context(dev);
6dbe2772 4528 i915_gem_cleanup_ringbuffer(dev);
29105ccc 4529
6dbe2772
KP		 4530 mutex_unlock(&dev->struct_mutex);
4531
29105ccc
CW		 4532 /* Cancel the retire work handler, which should be idle now. */
4533 cancel_delayed_work_sync(&dev_priv->mm.retire_work);
4534
673a394b
EA		 4535 return 0;
4536}
4537
e552eb70
JB		 4538/*
4539 * 965+ support PIPE_CONTROL commands, which provide finer grained control
4540 * over cache flushing.
4541 */
8187a2b7 4542static int
e552eb70
JB		 4543i915_gem_init_pipe_control(struct drm_device *dev)
4544{
4545 drm_i915_private_t *dev_priv = dev->dev_private;
4546 struct drm_gem_object *obj;
4547 struct drm_i915_gem_object *obj_priv;
4548 int ret;
4549
34dc4d44 4550 obj = i915_gem_alloc_object(dev, 4096);
e552eb70
JB		 4551 if (obj == NULL) {
4552 DRM_ERROR("Failed to allocate seqno page\n");
4553 ret = -ENOMEM;
4554 goto err;
4555 }
4556 obj_priv = to_intel_bo(obj);
4557 obj_priv->agp_type = AGP_USER_CACHED_MEMORY;
4558
4559 ret = i915_gem_object_pin(obj, 4096);
4560 if (ret)
4561 goto err_unref;
4562
4563 dev_priv->seqno_gfx_addr = obj_priv->gtt_offset;
4564 dev_priv->seqno_page = kmap(obj_priv->pages[0]);
4565 if (dev_priv->seqno_page == NULL)
4566 goto err_unpin;
4567
4568 dev_priv->seqno_obj = obj;
4569 memset(dev_priv->seqno_page, 0, PAGE_SIZE);
4570
4571 return 0;
4572
4573err_unpin:
4574 i915_gem_object_unpin(obj);
4575err_unref:
4576 drm_gem_object_unreference(obj);
4577err:
4578 return ret;
4579}
4580
8187a2b7
ZN		 4581
4582static void
e552eb70
JB		 4583i915_gem_cleanup_pipe_control(struct drm_device *dev)
4584{
4585 drm_i915_private_t *dev_priv = dev->dev_private;
4586 struct drm_gem_object *obj;
4587 struct drm_i915_gem_object *obj_priv;
4588
4589 obj = dev_priv->seqno_obj;
4590 obj_priv = to_intel_bo(obj);
4591 kunmap(obj_priv->pages[0]);
4592 i915_gem_object_unpin(obj);
4593 drm_gem_object_unreference(obj);
4594 dev_priv->seqno_obj = NULL;
4595
4596 dev_priv->seqno_page = NULL;
673a394b
EA		 4597}
4598
8187a2b7
ZN		 4599int
4600i915_gem_init_ringbuffer(struct drm_device *dev)
4601{
4602 drm_i915_private_t *dev_priv = dev->dev_private;
4603 int ret;
4604 dev_priv->render_ring = render_ring;
4605 if (!I915_NEED_GFX_HWS(dev)) {
4606 dev_priv->render_ring.status_page.page_addr
4607 = dev_priv->status_page_dmah->vaddr;
4608 memset(dev_priv->render_ring.status_page.page_addr,
4609 0, PAGE_SIZE);
4610 }
4611 if (HAS_PIPE_CONTROL(dev)) {
4612 ret = i915_gem_init_pipe_control(dev);
4613 if (ret)
4614 return ret;
4615 }
4616 ret = intel_init_ring_buffer(dev, &dev_priv->render_ring);
d1b851fc
ZN		 4617 if (!ret && HAS_BSD(dev)) {
4618 dev_priv->bsd_ring = bsd_ring;
4619 ret = intel_init_ring_buffer(dev, &dev_priv->bsd_ring);
4620 }
8187a2b7
ZN		 4621 return ret;
4622}
4623
4624void
4625i915_gem_cleanup_ringbuffer(struct drm_device *dev)
4626{
4627 drm_i915_private_t *dev_priv = dev->dev_private;
4628
4629 intel_cleanup_ring_buffer(dev, &dev_priv->render_ring);
d1b851fc
ZN		 4630 if (HAS_BSD(dev))
4631 intel_cleanup_ring_buffer(dev, &dev_priv->bsd_ring);
8187a2b7
ZN		 4632 if (HAS_PIPE_CONTROL(dev))
4633 i915_gem_cleanup_pipe_control(dev);
4634}
4635
673a394b
EA		 4636int
4637i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
4638 struct drm_file *file_priv)
4639{
4640 drm_i915_private_t *dev_priv = dev->dev_private;
4641 int ret;
4642
79e53945
JB		 4643 if (drm_core_check_feature(dev, DRIVER_MODESET))
4644 return 0;
4645
ba1234d1 4646 if (atomic_read(&dev_priv->mm.wedged)) {
673a394b 4647 DRM_ERROR("Reenabling wedged hardware, good luck\n");
ba1234d1 4648 atomic_set(&dev_priv->mm.wedged, 0);
673a394b
EA		 4649 }
4650
673a394b 4651 mutex_lock(&dev->struct_mutex);
9bb2d6f9
EA		 4652 dev_priv->mm.suspended = 0;
4653
4654 ret = i915_gem_init_ringbuffer(dev);
d816f6ac
WF		 4655 if (ret != 0) {
4656 mutex_unlock(&dev->struct_mutex);
9bb2d6f9 4657 return ret;
d816f6ac 4658 }
9bb2d6f9 4659
5e118f41 4660 spin_lock(&dev_priv->mm.active_list_lock);
852835f3 4661 BUG_ON(!list_empty(&dev_priv->render_ring.active_list));
d1b851fc 4662 BUG_ON(HAS_BSD(dev) && !list_empty(&dev_priv->bsd_ring.active_list));
5e118f41
CW		 4663 spin_unlock(&dev_priv->mm.active_list_lock);
4664
673a394b
EA		 4665 BUG_ON(!list_empty(&dev_priv->mm.flushing_list));
4666 BUG_ON(!list_empty(&dev_priv->mm.inactive_list));
852835f3 4667 BUG_ON(!list_empty(&dev_priv->render_ring.request_list));
d1b851fc 4668 BUG_ON(HAS_BSD(dev) && !list_empty(&dev_priv->bsd_ring.request_list));
673a394b 4669 mutex_unlock(&dev->struct_mutex);
dbb19d30
KH		 4670
4671 drm_irq_install(dev);
4672
673a394b
EA		 4673 return 0;
4674}
4675
4676int
4677i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
4678 struct drm_file *file_priv)
4679{
79e53945
JB		 4680 if (drm_core_check_feature(dev, DRIVER_MODESET))
4681 return 0;
4682
dbb19d30 4683 drm_irq_uninstall(dev);
e6890f6f 4684 return i915_gem_idle(dev);
673a394b
EA		 4685}
4686
4687void
4688i915_gem_lastclose(struct drm_device *dev)
4689{
4690 int ret;
673a394b 4691
e806b495
EA		 4692 if (drm_core_check_feature(dev, DRIVER_MODESET))
4693 return;
4694
6dbe2772
KP		 4695 ret = i915_gem_idle(dev);
4696 if (ret)
4697 DRM_ERROR("failed to idle hardware: %d\n", ret);
673a394b
EA		 4698}
4699
4700void
4701i915_gem_load(struct drm_device *dev)
4702{
b5aa8a0f 4703 int i;
673a394b
EA		 4704 drm_i915_private_t *dev_priv = dev->dev_private;
4705
5e118f41 4706 spin_lock_init(&dev_priv->mm.active_list_lock);
673a394b 4707 INIT_LIST_HEAD(&dev_priv->mm.flushing_list);
99fcb766 4708 INIT_LIST_HEAD(&dev_priv->mm.gpu_write_list);
673a394b 4709 INIT_LIST_HEAD(&dev_priv->mm.inactive_list);
a09ba7fa 4710 INIT_LIST_HEAD(&dev_priv->mm.fence_list);
852835f3
ZN		 4711 INIT_LIST_HEAD(&dev_priv->render_ring.active_list);
4712 INIT_LIST_HEAD(&dev_priv->render_ring.request_list);
d1b851fc
ZN		 4713 if (HAS_BSD(dev)) {
4714 INIT_LIST_HEAD(&dev_priv->bsd_ring.active_list);
4715 INIT_LIST_HEAD(&dev_priv->bsd_ring.request_list);
4716 }
007cc8ac
DV		 4717 for (i = 0; i < 16; i++)
4718 INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list);
673a394b
EA		 4719 INIT_DELAYED_WORK(&dev_priv->mm.retire_work,
4720 i915_gem_retire_work_handler);
31169714
CW		 4721 spin_lock(&shrink_list_lock);
4722 list_add(&dev_priv->mm.shrink_list, &shrink_list);
4723 spin_unlock(&shrink_list_lock);
4724
de151cf6 4725 /* Old X drivers will take 0-2 for front, back, depth buffers */
b397c836
EA		 4726 if (!drm_core_check_feature(dev, DRIVER_MODESET))
4727 dev_priv->fence_reg_start = 3;
de151cf6 4728
0f973f27 4729 if (IS_I965G(dev) || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
de151cf6
JB		 4730 dev_priv->num_fence_regs = 16;
4731 else
4732 dev_priv->num_fence_regs = 8;
4733
b5aa8a0f
GH		 4734 /* Initialize fence registers to zero */
4735 if (IS_I965G(dev)) {
4736 for (i = 0; i < 16; i++)
4737 I915_WRITE64(FENCE_REG_965_0 + (i * 8), 0);
4738 } else {
4739 for (i = 0; i < 8; i++)
4740 I915_WRITE(FENCE_REG_830_0 + (i * 4), 0);
4741 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4742 for (i = 0; i < 8; i++)
4743 I915_WRITE(FENCE_REG_945_8 + (i * 4), 0);
4744 }
673a394b 4745 i915_gem_detect_bit_6_swizzle(dev);
6b95a207 4746 init_waitqueue_head(&dev_priv->pending_flip_queue);
673a394b 4747}
71acb5eb
DA		 4748
4749/*
4750 * Create a physically contiguous memory object for this object
4751 * e.g. for cursor + overlay regs
4752 */
4753int i915_gem_init_phys_object(struct drm_device *dev,
4754 int id, int size)
4755{
4756 drm_i915_private_t *dev_priv = dev->dev_private;
4757 struct drm_i915_gem_phys_object *phys_obj;
4758 int ret;
4759
4760 if (dev_priv->mm.phys_objs[id - 1] || !size)
4761 return 0;
4762
9a298b2a 4763 phys_obj = kzalloc(sizeof(struct drm_i915_gem_phys_object), GFP_KERNEL);
71acb5eb
DA		 4764 if (!phys_obj)
4765 return -ENOMEM;
4766
4767 phys_obj->id = id;
4768
e6be8d9d 4769 phys_obj->handle = drm_pci_alloc(dev, size, 0);
71acb5eb
DA		 4770 if (!phys_obj->handle) {
4771 ret = -ENOMEM;
4772 goto kfree_obj;
4773 }
4774#ifdef CONFIG_X86
4775 set_memory_wc((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE);
4776#endif
4777
4778 dev_priv->mm.phys_objs[id - 1] = phys_obj;
4779
4780 return 0;
4781kfree_obj:
9a298b2a 4782 kfree(phys_obj);
71acb5eb
DA		 4783 return ret;
4784}
4785
4786void i915_gem_free_phys_object(struct drm_device *dev, int id)
4787{
4788 drm_i915_private_t *dev_priv = dev->dev_private;
4789 struct drm_i915_gem_phys_object *phys_obj;
4790
4791 if (!dev_priv->mm.phys_objs[id - 1])
4792 return;
4793
4794 phys_obj = dev_priv->mm.phys_objs[id - 1];
4795 if (phys_obj->cur_obj) {
4796 i915_gem_detach_phys_object(dev, phys_obj->cur_obj);
4797 }
4798
4799#ifdef CONFIG_X86
4800 set_memory_wb((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE);
4801#endif
4802 drm_pci_free(dev, phys_obj->handle);
4803 kfree(phys_obj);
4804 dev_priv->mm.phys_objs[id - 1] = NULL;
4805}
4806
4807void i915_gem_free_all_phys_object(struct drm_device *dev)
4808{
4809 int i;
4810
260883c8 4811 for (i = I915_GEM_PHYS_CURSOR_0; i <= I915_MAX_PHYS_OBJECT; i++)
71acb5eb
DA		 4812 i915_gem_free_phys_object(dev, i);
4813}
4814
4815void i915_gem_detach_phys_object(struct drm_device *dev,
4816 struct drm_gem_object *obj)
4817{
4818 struct drm_i915_gem_object *obj_priv;
4819 int i;
4820 int ret;
4821 int page_count;
4822
23010e43 4823 obj_priv = to_intel_bo(obj);
71acb5eb
DA		 4824 if (!obj_priv->phys_obj)
4825 return;
4826
4bdadb97 4827 ret = i915_gem_object_get_pages(obj, 0);
71acb5eb
DA		 4828 if (ret)
4829 goto out;
4830
4831 page_count = obj->size / PAGE_SIZE;
4832
4833 for (i = 0; i < page_count; i++) {
856fa198 4834 char *dst = kmap_atomic(obj_priv->pages[i], KM_USER0);
71acb5eb
DA		 4835 char *src = obj_priv->phys_obj->handle->vaddr + (i * PAGE_SIZE);
4836
4837 memcpy(dst, src, PAGE_SIZE);
4838 kunmap_atomic(dst, KM_USER0);
4839 }
856fa198 4840 drm_clflush_pages(obj_priv->pages, page_count);
71acb5eb 4841 drm_agp_chipset_flush(dev);
d78b47b9
CW		 4842
4843 i915_gem_object_put_pages(obj);
71acb5eb
DA		 4844out:
4845 obj_priv->phys_obj->cur_obj = NULL;
4846 obj_priv->phys_obj = NULL;
4847}
4848
4849int
4850i915_gem_attach_phys_object(struct drm_device *dev,
4851 struct drm_gem_object *obj, int id)
4852{
4853 drm_i915_private_t *dev_priv = dev->dev_private;
4854 struct drm_i915_gem_object *obj_priv;
4855 int ret = 0;
4856 int page_count;
4857 int i;
4858
4859 if (id > I915_MAX_PHYS_OBJECT)
4860 return -EINVAL;
4861
23010e43 4862 obj_priv = to_intel_bo(obj);
71acb5eb
DA		 4863
4864 if (obj_priv->phys_obj) {
4865 if (obj_priv->phys_obj->id == id)
4866 return 0;
4867 i915_gem_detach_phys_object(dev, obj);
4868 }
4869
4870
4871 /* create a new object */
4872 if (!dev_priv->mm.phys_objs[id - 1]) {
4873 ret = i915_gem_init_phys_object(dev, id,
4874 obj->size);
4875 if (ret) {
aeb565df 4876 DRM_ERROR("failed to init phys object %d size: %zu\n", id, obj->size);
71acb5eb
DA		 4877 goto out;
4878 }
4879 }
4880
4881 /* bind to the object */
4882 obj_priv->phys_obj = dev_priv->mm.phys_objs[id - 1];
4883 obj_priv->phys_obj->cur_obj = obj;
4884
4bdadb97 4885 ret = i915_gem_object_get_pages(obj, 0);
71acb5eb
DA		 4886 if (ret) {
4887 DRM_ERROR("failed to get page list\n");
4888 goto out;
4889 }
4890
4891 page_count = obj->size / PAGE_SIZE;
4892
4893 for (i = 0; i < page_count; i++) {
856fa198 4894 char *src = kmap_atomic(obj_priv->pages[i], KM_USER0);
71acb5eb
DA		 4895 char *dst = obj_priv->phys_obj->handle->vaddr + (i * PAGE_SIZE);
4896
4897 memcpy(dst, src, PAGE_SIZE);
4898 kunmap_atomic(src, KM_USER0);
4899 }
4900
d78b47b9
CW		 4901 i915_gem_object_put_pages(obj);
4902
71acb5eb
DA		 4903 return 0;
4904out:
4905 return ret;
4906}
4907
4908static int
4909i915_gem_phys_pwrite(struct drm_device *dev, struct drm_gem_object *obj,
4910 struct drm_i915_gem_pwrite *args,
4911 struct drm_file *file_priv)
4912{
23010e43 4913 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
71acb5eb
DA		 4914 void *obj_addr;
4915 int ret;
4916 char __user *user_data;
4917
4918 user_data = (char __user *) (uintptr_t) args->data_ptr;
4919 obj_addr = obj_priv->phys_obj->handle->vaddr + args->offset;
4920
44d98a61 4921 DRM_DEBUG_DRIVER("obj_addr %p, %lld\n", obj_addr, args->size);
71acb5eb
DA		 4922 ret = copy_from_user(obj_addr, user_data, args->size);
4923 if (ret)
4924 return -EFAULT;
4925
4926 drm_agp_chipset_flush(dev);
4927 return 0;
4928}
b962442e
EA		 4929
4930void i915_gem_release(struct drm_device * dev, struct drm_file *file_priv)
4931{
4932 struct drm_i915_file_private *i915_file_priv = file_priv->driver_priv;
4933
4934 /* Clean up our request list when the client is going away, so that
4935 * later retire_requests won't dereference our soon-to-be-gone
4936 * file_priv.
4937 */
4938 mutex_lock(&dev->struct_mutex);
4939 while (!list_empty(&i915_file_priv->mm.request_list))
4940 list_del_init(i915_file_priv->mm.request_list.next);
4941 mutex_unlock(&dev->struct_mutex);
4942}
31169714 4943
1637ef41
CW		 4944static int
4945i915_gpu_is_active(struct drm_device *dev)
4946{
4947 drm_i915_private_t *dev_priv = dev->dev_private;
4948 int lists_empty;
4949
4950 spin_lock(&dev_priv->mm.active_list_lock);
4951 lists_empty = list_empty(&dev_priv->mm.flushing_list) &&
852835f3 4952 list_empty(&dev_priv->render_ring.active_list);
d1b851fc
ZN		 4953 if (HAS_BSD(dev))
4954 lists_empty &= list_empty(&dev_priv->bsd_ring.active_list);
1637ef41
CW		 4955 spin_unlock(&dev_priv->mm.active_list_lock);
4956
4957 return !lists_empty;
4958}
4959
31169714
CW		 4960static int
4961i915_gem_shrink(int nr_to_scan, gfp_t gfp_mask)
4962{
4963 drm_i915_private_t *dev_priv, *next_dev;
4964 struct drm_i915_gem_object *obj_priv, *next_obj;
4965 int cnt = 0;
4966 int would_deadlock = 1;
4967
4968 /* "fast-path" to count number of available objects */
4969 if (nr_to_scan == 0) {
4970 spin_lock(&shrink_list_lock);
4971 list_for_each_entry(dev_priv, &shrink_list, mm.shrink_list) {
4972 struct drm_device *dev = dev_priv->dev;
4973
4974 if (mutex_trylock(&dev->struct_mutex)) {
4975 list_for_each_entry(obj_priv,
4976 &dev_priv->mm.inactive_list,
4977 list)
4978 cnt++;
4979 mutex_unlock(&dev->struct_mutex);
4980 }
4981 }
4982 spin_unlock(&shrink_list_lock);
4983
4984 return (cnt / 100) * sysctl_vfs_cache_pressure;
4985 }
4986
4987 spin_lock(&shrink_list_lock);
4988
1637ef41 4989rescan:
31169714
CW		 4990 /* first scan for clean buffers */
4991 list_for_each_entry_safe(dev_priv, next_dev,
4992 &shrink_list, mm.shrink_list) {
4993 struct drm_device *dev = dev_priv->dev;
4994
4995 if (! mutex_trylock(&dev->struct_mutex))
4996 continue;
4997
4998 spin_unlock(&shrink_list_lock);
852835f3 4999 i915_gem_retire_requests(dev, &dev_priv->render_ring);
d1b851fc
ZN		 5000
5001 if (HAS_BSD(dev))
5002 i915_gem_retire_requests(dev, &dev_priv->bsd_ring);
31169714
CW		 5003
5004 list_for_each_entry_safe(obj_priv, next_obj,
5005 &dev_priv->mm.inactive_list,
5006 list) {
5007 if (i915_gem_object_is_purgeable(obj_priv)) {
a8089e84 5008 i915_gem_object_unbind(&obj_priv->base);
31169714
CW		 5009 if (--nr_to_scan <= 0)
5010 break;
5011 }
5012 }
5013
5014 spin_lock(&shrink_list_lock);
5015 mutex_unlock(&dev->struct_mutex);
5016
963b4836
CW		 5017 would_deadlock = 0;
5018
31169714
CW		 5019 if (nr_to_scan <= 0)
5020 break;
5021 }
5022
5023 /* second pass, evict/count anything still on the inactive list */
5024 list_for_each_entry_safe(dev_priv, next_dev,
5025 &shrink_list, mm.shrink_list) {
5026 struct drm_device *dev = dev_priv->dev;
5027
5028 if (! mutex_trylock(&dev->struct_mutex))
5029 continue;
5030
5031 spin_unlock(&shrink_list_lock);
5032
5033 list_for_each_entry_safe(obj_priv, next_obj,
5034 &dev_priv->mm.inactive_list,
5035 list) {
5036 if (nr_to_scan > 0) {
a8089e84 5037 i915_gem_object_unbind(&obj_priv->base);
31169714
CW		 5038 nr_to_scan--;
5039 } else
5040 cnt++;
5041 }
5042
5043 spin_lock(&shrink_list_lock);
5044 mutex_unlock(&dev->struct_mutex);
5045
5046 would_deadlock = 0;
5047 }
5048
1637ef41
CW		 5049 if (nr_to_scan) {
5050 int active = 0;
5051
5052 /*
5053 * We are desperate for pages, so as a last resort, wait
5054 * for the GPU to finish and discard whatever we can.
5055 * This has a dramatic impact to reduce the number of
5056 * OOM-killer events whilst running the GPU aggressively.
5057 */
5058 list_for_each_entry(dev_priv, &shrink_list, mm.shrink_list) {
5059 struct drm_device *dev = dev_priv->dev;
5060
5061 if (!mutex_trylock(&dev->struct_mutex))
5062 continue;
5063
5064 spin_unlock(&shrink_list_lock);
5065
5066 if (i915_gpu_is_active(dev)) {
5067 i915_gpu_idle(dev);
5068 active++;
5069 }
5070
5071 spin_lock(&shrink_list_lock);
5072 mutex_unlock(&dev->struct_mutex);
5073 }
5074
5075 if (active)
5076 goto rescan;
5077 }
5078
31169714
CW		 5079 spin_unlock(&shrink_list_lock);
5080
5081 if (would_deadlock)
5082 return -1;
5083 else if (cnt > 0)
5084 return (cnt / 100) * sysctl_vfs_cache_pressure;
5085 else
5086 return 0;
5087}
5088
5089static struct shrinker shrinker = {
5090 .shrink = i915_gem_shrink,
5091 .seeks = DEFAULT_SEEKS,
5092};
5093
5094__init void
5095i915_gem_shrinker_init(void)
5096{
5097 register_shrinker(&shrinker);
5098}
5099
5100__exit void
5101i915_gem_shrinker_exit(void)
5102{
5103 unregister_shrinker(&shrinker);
5104}
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