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drm/i915: Warn before mmaping a purgeable buffer.
[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / i915 / i915_gem.c
CommitLineData
673a394b
EA		 1/*
2 * Copyright © 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 *
26 */
27
28#include "drmP.h"
29#include "drm.h"
30#include "i915_drm.h"
31#include "i915_drv.h"
1c5d22f7 32#include "i915_trace.h"
652c393a 33#include "intel_drv.h"
673a394b 34#include <linux/swap.h>
79e53945 35#include <linux/pci.h>
673a394b 36
28dfe52a
EA		 37#define I915_GEM_GPU_DOMAINS (~(I915_GEM_DOMAIN_CPU | I915_GEM_DOMAIN_GTT))
38
e47c68e9
EA		 39static void i915_gem_object_flush_gpu_write_domain(struct drm_gem_object *obj);
40static void i915_gem_object_flush_gtt_write_domain(struct drm_gem_object *obj);
41static void i915_gem_object_flush_cpu_write_domain(struct drm_gem_object *obj);
e47c68e9
EA		 42static int i915_gem_object_set_to_cpu_domain(struct drm_gem_object *obj,
43 int write);
44static int i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object *obj,
45 uint64_t offset,
46 uint64_t size);
47static void i915_gem_object_set_to_full_cpu_read_domain(struct drm_gem_object *obj);
673a394b 48static int i915_gem_object_wait_rendering(struct drm_gem_object *obj);
de151cf6
JB		 49static int i915_gem_object_bind_to_gtt(struct drm_gem_object *obj,
50 unsigned alignment);
de151cf6 51static void i915_gem_clear_fence_reg(struct drm_gem_object *obj);
07f73f69 52static int i915_gem_evict_something(struct drm_device *dev, int min_size);
ab5ee576 53static int i915_gem_evict_from_inactive_list(struct drm_device *dev);
71acb5eb
DA		 54static int i915_gem_phys_pwrite(struct drm_device *dev, struct drm_gem_object *obj,
55 struct drm_i915_gem_pwrite *args,
56 struct drm_file *file_priv);
673a394b 57
31169714
CW		 58static LIST_HEAD(shrink_list);
59static DEFINE_SPINLOCK(shrink_list_lock);
60
79e53945
JB		 61int i915_gem_do_init(struct drm_device *dev, unsigned long start,
62 unsigned long end)
673a394b
EA		 63{
64 drm_i915_private_t *dev_priv = dev->dev_private;
673a394b 65
79e53945
JB		 66 if (start >= end ||
67 (start & (PAGE_SIZE - 1)) != 0 ||
68 (end & (PAGE_SIZE - 1)) != 0) {
673a394b
EA		 69 return -EINVAL;
70 }
71
79e53945
JB		 72 drm_mm_init(&dev_priv->mm.gtt_space, start,
73 end - start);
673a394b 74
79e53945
JB		 75 dev->gtt_total = (uint32_t) (end - start);
76
77 return 0;
78}
673a394b 79
79e53945
JB		 80int
81i915_gem_init_ioctl(struct drm_device *dev, void *data,
82 struct drm_file *file_priv)
83{
84 struct drm_i915_gem_init *args = data;
85 int ret;
86
87 mutex_lock(&dev->struct_mutex);
88 ret = i915_gem_do_init(dev, args->gtt_start, args->gtt_end);
673a394b
EA		 89 mutex_unlock(&dev->struct_mutex);
90
79e53945 91 return ret;
673a394b
EA		 92}
93
5a125c3c
EA		 94int
95i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
96 struct drm_file *file_priv)
97{
5a125c3c 98 struct drm_i915_gem_get_aperture *args = data;
5a125c3c
EA		 99
100 if (!(dev->driver->driver_features & DRIVER_GEM))
101 return -ENODEV;
102
103 args->aper_size = dev->gtt_total;
2678d9d6
KP		 104 args->aper_available_size = (args->aper_size -
105 atomic_read(&dev->pin_memory));
5a125c3c
EA		 106
107 return 0;
108}
109
673a394b
EA		 110
111/**
112 * Creates a new mm object and returns a handle to it.
113 */
114int
115i915_gem_create_ioctl(struct drm_device *dev, void *data,
116 struct drm_file *file_priv)
117{
118 struct drm_i915_gem_create *args = data;
119 struct drm_gem_object *obj;
a1a2d1d3
PP		 120 int ret;
121 u32 handle;
673a394b
EA		 122
123 args->size = roundup(args->size, PAGE_SIZE);
124
125 /* Allocate the new object */
126 obj = drm_gem_object_alloc(dev, args->size);
127 if (obj == NULL)
128 return -ENOMEM;
129
130 ret = drm_gem_handle_create(file_priv, obj, &handle);
131 mutex_lock(&dev->struct_mutex);
132 drm_gem_object_handle_unreference(obj);
133 mutex_unlock(&dev->struct_mutex);
134
135 if (ret)
136 return ret;
137
138 args->handle = handle;
139
140 return 0;
141}
142
eb01459f
EA		 143static inline int
144fast_shmem_read(struct page **pages,
145 loff_t page_base, int page_offset,
146 char __user *data,
147 int length)
148{
149 char __iomem *vaddr;
2bc43b5c 150 int unwritten;
eb01459f
EA		 151
152 vaddr = kmap_atomic(pages[page_base >> PAGE_SHIFT], KM_USER0);
153 if (vaddr == NULL)
154 return -ENOMEM;
2bc43b5c 155 unwritten = __copy_to_user_inatomic(data, vaddr + page_offset, length);
eb01459f
EA		 156 kunmap_atomic(vaddr, KM_USER0);
157
2bc43b5c
FM		 158 if (unwritten)
159 return -EFAULT;
160
161 return 0;
eb01459f
EA		 162}
163
280b713b
EA		 164static int i915_gem_object_needs_bit17_swizzle(struct drm_gem_object *obj)
165{
166 drm_i915_private_t *dev_priv = obj->dev->dev_private;
167 struct drm_i915_gem_object *obj_priv = obj->driver_private;
168
169 return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
170 obj_priv->tiling_mode != I915_TILING_NONE;
171}
172
40123c1f
EA		 173static inline int
174slow_shmem_copy(struct page *dst_page,
175 int dst_offset,
176 struct page *src_page,
177 int src_offset,
178 int length)
179{
180 char *dst_vaddr, *src_vaddr;
181
182 dst_vaddr = kmap_atomic(dst_page, KM_USER0);
183 if (dst_vaddr == NULL)
184 return -ENOMEM;
185
186 src_vaddr = kmap_atomic(src_page, KM_USER1);
187 if (src_vaddr == NULL) {
188 kunmap_atomic(dst_vaddr, KM_USER0);
189 return -ENOMEM;
190 }
191
192 memcpy(dst_vaddr + dst_offset, src_vaddr + src_offset, length);
193
194 kunmap_atomic(src_vaddr, KM_USER1);
195 kunmap_atomic(dst_vaddr, KM_USER0);
196
197 return 0;
198}
199
280b713b
EA		 200static inline int
201slow_shmem_bit17_copy(struct page *gpu_page,
202 int gpu_offset,
203 struct page *cpu_page,
204 int cpu_offset,
205 int length,
206 int is_read)
207{
208 char *gpu_vaddr, *cpu_vaddr;
209
210 /* Use the unswizzled path if this page isn't affected. */
211 if ((page_to_phys(gpu_page) & (1 << 17)) == 0) {
212 if (is_read)
213 return slow_shmem_copy(cpu_page, cpu_offset,
214 gpu_page, gpu_offset, length);
215 else
216 return slow_shmem_copy(gpu_page, gpu_offset,
217 cpu_page, cpu_offset, length);
218 }
219
220 gpu_vaddr = kmap_atomic(gpu_page, KM_USER0);
221 if (gpu_vaddr == NULL)
222 return -ENOMEM;
223
224 cpu_vaddr = kmap_atomic(cpu_page, KM_USER1);
225 if (cpu_vaddr == NULL) {
226 kunmap_atomic(gpu_vaddr, KM_USER0);
227 return -ENOMEM;
228 }
229
230 /* Copy the data, XORing A6 with A17 (1). The user already knows he's
231 * XORing with the other bits (A9 for Y, A9 and A10 for X)
232 */
233 while (length > 0) {
234 int cacheline_end = ALIGN(gpu_offset + 1, 64);
235 int this_length = min(cacheline_end - gpu_offset, length);
236 int swizzled_gpu_offset = gpu_offset ^ 64;
237
238 if (is_read) {
239 memcpy(cpu_vaddr + cpu_offset,
240 gpu_vaddr + swizzled_gpu_offset,
241 this_length);
242 } else {
243 memcpy(gpu_vaddr + swizzled_gpu_offset,
244 cpu_vaddr + cpu_offset,
245 this_length);
246 }
247 cpu_offset += this_length;
248 gpu_offset += this_length;
249 length -= this_length;
250 }
251
252 kunmap_atomic(cpu_vaddr, KM_USER1);
253 kunmap_atomic(gpu_vaddr, KM_USER0);
254
255 return 0;
256}
257
eb01459f
EA		 258/**
259 * This is the fast shmem pread path, which attempts to copy_from_user directly
260 * from the backing pages of the object to the user's address space. On a
261 * fault, it fails so we can fall back to i915_gem_shmem_pwrite_slow().
262 */
263static int
264i915_gem_shmem_pread_fast(struct drm_device *dev, struct drm_gem_object *obj,
265 struct drm_i915_gem_pread *args,
266 struct drm_file *file_priv)
267{
268 struct drm_i915_gem_object *obj_priv = obj->driver_private;
269 ssize_t remain;
270 loff_t offset, page_base;
271 char __user *user_data;
272 int page_offset, page_length;
273 int ret;
274
275 user_data = (char __user *) (uintptr_t) args->data_ptr;
276 remain = args->size;
277
278 mutex_lock(&dev->struct_mutex);
279
280 ret = i915_gem_object_get_pages(obj);
281 if (ret != 0)
282 goto fail_unlock;
283
284 ret = i915_gem_object_set_cpu_read_domain_range(obj, args->offset,
285 args->size);
286 if (ret != 0)
287 goto fail_put_pages;
288
289 obj_priv = obj->driver_private;
290 offset = args->offset;
291
292 while (remain > 0) {
293 /* Operation in this page
294 *
295 * page_base = page offset within aperture
296 * page_offset = offset within page
297 * page_length = bytes to copy for this page
298 */
299 page_base = (offset & ~(PAGE_SIZE-1));
300 page_offset = offset & (PAGE_SIZE-1);
301 page_length = remain;
302 if ((page_offset + remain) > PAGE_SIZE)
303 page_length = PAGE_SIZE - page_offset;
304
305 ret = fast_shmem_read(obj_priv->pages,
306 page_base, page_offset,
307 user_data, page_length);
308 if (ret)
309 goto fail_put_pages;
310
311 remain -= page_length;
312 user_data += page_length;
313 offset += page_length;
314 }
315
316fail_put_pages:
317 i915_gem_object_put_pages(obj);
318fail_unlock:
319 mutex_unlock(&dev->struct_mutex);
320
321 return ret;
322}
323
07f73f69
CW		 324static inline gfp_t
325i915_gem_object_get_page_gfp_mask (struct drm_gem_object *obj)
326{
327 return mapping_gfp_mask(obj->filp->f_path.dentry->d_inode->i_mapping);
328}
329
330static inline void
331i915_gem_object_set_page_gfp_mask (struct drm_gem_object *obj, gfp_t gfp)
332{
333 mapping_set_gfp_mask(obj->filp->f_path.dentry->d_inode->i_mapping, gfp);
334}
335
336static int
337i915_gem_object_get_pages_or_evict(struct drm_gem_object *obj)
338{
339 int ret;
340
341 ret = i915_gem_object_get_pages(obj);
342
343 /* If we've insufficient memory to map in the pages, attempt
344 * to make some space by throwing out some old buffers.
345 */
346 if (ret == -ENOMEM) {
347 struct drm_device *dev = obj->dev;
348 gfp_t gfp;
349
350 ret = i915_gem_evict_something(dev, obj->size);
351 if (ret)
352 return ret;
353
354 gfp = i915_gem_object_get_page_gfp_mask(obj);
355 i915_gem_object_set_page_gfp_mask(obj, gfp & ~__GFP_NORETRY);
356 ret = i915_gem_object_get_pages(obj);
357 i915_gem_object_set_page_gfp_mask (obj, gfp);
358 }
359
360 return ret;
361}
362
eb01459f
EA		 363/**
364 * This is the fallback shmem pread path, which allocates temporary storage
365 * in kernel space to copy_to_user into outside of the struct_mutex, so we
366 * can copy out of the object's backing pages while holding the struct mutex
367 * and not take page faults.
368 */
369static int
370i915_gem_shmem_pread_slow(struct drm_device *dev, struct drm_gem_object *obj,
371 struct drm_i915_gem_pread *args,
372 struct drm_file *file_priv)
373{
374 struct drm_i915_gem_object *obj_priv = obj->driver_private;
375 struct mm_struct *mm = current->mm;
376 struct page **user_pages;
377 ssize_t remain;
378 loff_t offset, pinned_pages, i;
379 loff_t first_data_page, last_data_page, num_pages;
380 int shmem_page_index, shmem_page_offset;
381 int data_page_index, data_page_offset;
382 int page_length;
383 int ret;
384 uint64_t data_ptr = args->data_ptr;
280b713b 385 int do_bit17_swizzling;
eb01459f
EA		 386
387 remain = args->size;
388
389 /* Pin the user pages containing the data. We can't fault while
390 * holding the struct mutex, yet we want to hold it while
391 * dereferencing the user data.
392 */
393 first_data_page = data_ptr / PAGE_SIZE;
394 last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE;
395 num_pages = last_data_page - first_data_page + 1;
396
8e7d2b2c 397 user_pages = drm_calloc_large(num_pages, sizeof(struct page *));
eb01459f
EA		 398 if (user_pages == NULL)
399 return -ENOMEM;
400
401 down_read(&mm->mmap_sem);
402 pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr,
e5e9ecde 403 num_pages, 1, 0, user_pages, NULL);
eb01459f
EA		 404 up_read(&mm->mmap_sem);
405 if (pinned_pages < num_pages) {
406 ret = -EFAULT;
407 goto fail_put_user_pages;
408 }
409
280b713b
EA		 410 do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
411
eb01459f
EA		 412 mutex_lock(&dev->struct_mutex);
413
07f73f69
CW		 414 ret = i915_gem_object_get_pages_or_evict(obj);
415 if (ret)
eb01459f
EA		 416 goto fail_unlock;
417
418 ret = i915_gem_object_set_cpu_read_domain_range(obj, args->offset,
419 args->size);
420 if (ret != 0)
421 goto fail_put_pages;
422
423 obj_priv = obj->driver_private;
424 offset = args->offset;
425
426 while (remain > 0) {
427 /* Operation in this page
428 *
429 * shmem_page_index = page number within shmem file
430 * shmem_page_offset = offset within page in shmem file
431 * data_page_index = page number in get_user_pages return
432 * data_page_offset = offset with data_page_index page.
433 * page_length = bytes to copy for this page
434 */
435 shmem_page_index = offset / PAGE_SIZE;
436 shmem_page_offset = offset & ~PAGE_MASK;
437 data_page_index = data_ptr / PAGE_SIZE - first_data_page;
438 data_page_offset = data_ptr & ~PAGE_MASK;
439
440 page_length = remain;
441 if ((shmem_page_offset + page_length) > PAGE_SIZE)
442 page_length = PAGE_SIZE - shmem_page_offset;
443 if ((data_page_offset + page_length) > PAGE_SIZE)
444 page_length = PAGE_SIZE - data_page_offset;
445
280b713b
EA		 446 if (do_bit17_swizzling) {
447 ret = slow_shmem_bit17_copy(obj_priv->pages[shmem_page_index],
448 shmem_page_offset,
449 user_pages[data_page_index],
450 data_page_offset,
451 page_length,
452 1);
453 } else {
454 ret = slow_shmem_copy(user_pages[data_page_index],
455 data_page_offset,
456 obj_priv->pages[shmem_page_index],
457 shmem_page_offset,
458 page_length);
459 }
eb01459f
EA		 460 if (ret)
461 goto fail_put_pages;
462
463 remain -= page_length;
464 data_ptr += page_length;
465 offset += page_length;
466 }
467
468fail_put_pages:
469 i915_gem_object_put_pages(obj);
470fail_unlock:
471 mutex_unlock(&dev->struct_mutex);
472fail_put_user_pages:
473 for (i = 0; i < pinned_pages; i++) {
474 SetPageDirty(user_pages[i]);
475 page_cache_release(user_pages[i]);
476 }
8e7d2b2c 477 drm_free_large(user_pages);
eb01459f
EA		 478
479 return ret;
480}
481
673a394b
EA		 482/**
483 * Reads data from the object referenced by handle.
484 *
485 * On error, the contents of *data are undefined.
486 */
487int
488i915_gem_pread_ioctl(struct drm_device *dev, void *data,
489 struct drm_file *file_priv)
490{
491 struct drm_i915_gem_pread *args = data;
492 struct drm_gem_object *obj;
493 struct drm_i915_gem_object *obj_priv;
673a394b
EA		 494 int ret;
495
496 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
497 if (obj == NULL)
498 return -EBADF;
499 obj_priv = obj->driver_private;
500
501 /* Bounds check source.
502 *
503 * XXX: This could use review for overflow issues...
504 */
505 if (args->offset > obj->size || args->size > obj->size ||
506 args->offset + args->size > obj->size) {
507 drm_gem_object_unreference(obj);
508 return -EINVAL;
509 }
510
280b713b 511 if (i915_gem_object_needs_bit17_swizzle(obj)) {
eb01459f 512 ret = i915_gem_shmem_pread_slow(dev, obj, args, file_priv);
280b713b
EA		 513 } else {
514 ret = i915_gem_shmem_pread_fast(dev, obj, args, file_priv);
515 if (ret != 0)
516 ret = i915_gem_shmem_pread_slow(dev, obj, args,
517 file_priv);
518 }
673a394b
EA		 519
520 drm_gem_object_unreference(obj);
673a394b 521
eb01459f 522 return ret;
673a394b
EA		 523}
524
0839ccb8
KP		 525/* This is the fast write path which cannot handle
526 * page faults in the source data
9b7530cc 527 */
0839ccb8
KP		 528
529static inline int
530fast_user_write(struct io_mapping *mapping,
531 loff_t page_base, int page_offset,
532 char __user *user_data,
533 int length)
9b7530cc 534{
9b7530cc 535 char *vaddr_atomic;
0839ccb8 536 unsigned long unwritten;
9b7530cc 537
0839ccb8
KP		 538 vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base);
539 unwritten = __copy_from_user_inatomic_nocache(vaddr_atomic + page_offset,
540 user_data, length);
541 io_mapping_unmap_atomic(vaddr_atomic);
542 if (unwritten)
543 return -EFAULT;
544 return 0;
545}
546
547/* Here's the write path which can sleep for
548 * page faults
549 */
550
551static inline int
3de09aa3
EA		 552slow_kernel_write(struct io_mapping *mapping,
553 loff_t gtt_base, int gtt_offset,
554 struct page *user_page, int user_offset,
555 int length)
0839ccb8 556{
3de09aa3 557 char *src_vaddr, *dst_vaddr;
0839ccb8
KP		 558 unsigned long unwritten;
559
3de09aa3
EA		 560 dst_vaddr = io_mapping_map_atomic_wc(mapping, gtt_base);
561 src_vaddr = kmap_atomic(user_page, KM_USER1);
562 unwritten = __copy_from_user_inatomic_nocache(dst_vaddr + gtt_offset,
563 src_vaddr + user_offset,
564 length);
565 kunmap_atomic(src_vaddr, KM_USER1);
566 io_mapping_unmap_atomic(dst_vaddr);
0839ccb8
KP		 567 if (unwritten)
568 return -EFAULT;
9b7530cc 569 return 0;
9b7530cc
LT		 570}
571
40123c1f
EA		 572static inline int
573fast_shmem_write(struct page **pages,
574 loff_t page_base, int page_offset,
575 char __user *data,
576 int length)
577{
578 char __iomem *vaddr;
d0088775 579 unsigned long unwritten;
40123c1f
EA		 580
581 vaddr = kmap_atomic(pages[page_base >> PAGE_SHIFT], KM_USER0);
582 if (vaddr == NULL)
583 return -ENOMEM;
d0088775 584 unwritten = __copy_from_user_inatomic(vaddr + page_offset, data, length);
40123c1f
EA		 585 kunmap_atomic(vaddr, KM_USER0);
586
d0088775
DA		 587 if (unwritten)
588 return -EFAULT;
40123c1f
EA		 589 return 0;
590}
591
3de09aa3
EA		 592/**
593 * This is the fast pwrite path, where we copy the data directly from the
594 * user into the GTT, uncached.
595 */
673a394b 596static int
3de09aa3
EA		 597i915_gem_gtt_pwrite_fast(struct drm_device *dev, struct drm_gem_object *obj,
598 struct drm_i915_gem_pwrite *args,
599 struct drm_file *file_priv)
673a394b
EA		 600{
601 struct drm_i915_gem_object *obj_priv = obj->driver_private;
0839ccb8 602 drm_i915_private_t *dev_priv = dev->dev_private;
673a394b 603 ssize_t remain;
0839ccb8 604 loff_t offset, page_base;
673a394b 605 char __user *user_data;
0839ccb8
KP		 606 int page_offset, page_length;
607 int ret;
673a394b
EA		 608
609 user_data = (char __user *) (uintptr_t) args->data_ptr;
610 remain = args->size;
611 if (!access_ok(VERIFY_READ, user_data, remain))
612 return -EFAULT;
613
614
615 mutex_lock(&dev->struct_mutex);
616 ret = i915_gem_object_pin(obj, 0);
617 if (ret) {
618 mutex_unlock(&dev->struct_mutex);
619 return ret;
620 }
2ef7eeaa 621 ret = i915_gem_object_set_to_gtt_domain(obj, 1);
673a394b
EA		 622 if (ret)
623 goto fail;
624
625 obj_priv = obj->driver_private;
626 offset = obj_priv->gtt_offset + args->offset;
673a394b
EA		 627
628 while (remain > 0) {
629 /* Operation in this page
630 *
0839ccb8
KP		 631 * page_base = page offset within aperture
632 * page_offset = offset within page
633 * page_length = bytes to copy for this page
673a394b 634 */
0839ccb8
KP		 635 page_base = (offset & ~(PAGE_SIZE-1));
636 page_offset = offset & (PAGE_SIZE-1);
637 page_length = remain;
638 if ((page_offset + remain) > PAGE_SIZE)
639 page_length = PAGE_SIZE - page_offset;
640
641 ret = fast_user_write (dev_priv->mm.gtt_mapping, page_base,
642 page_offset, user_data, page_length);
643
644 /* If we get a fault while copying data, then (presumably) our
3de09aa3
EA		 645 * source page isn't available. Return the error and we'll
646 * retry in the slow path.
0839ccb8 647 */
3de09aa3
EA		 648 if (ret)
649 goto fail;
673a394b 650
0839ccb8
KP		 651 remain -= page_length;
652 user_data += page_length;
653 offset += page_length;
673a394b 654 }
673a394b
EA		 655
656fail:
657 i915_gem_object_unpin(obj);
658 mutex_unlock(&dev->struct_mutex);
659
660 return ret;
661}
662
3de09aa3
EA		 663/**
664 * This is the fallback GTT pwrite path, which uses get_user_pages to pin
665 * the memory and maps it using kmap_atomic for copying.
666 *
667 * This code resulted in x11perf -rgb10text consuming about 10% more CPU
668 * than using i915_gem_gtt_pwrite_fast on a G45 (32-bit).
669 */
3043c60c 670static int
3de09aa3
EA		 671i915_gem_gtt_pwrite_slow(struct drm_device *dev, struct drm_gem_object *obj,
672 struct drm_i915_gem_pwrite *args,
673 struct drm_file *file_priv)
673a394b 674{
3de09aa3
EA		 675 struct drm_i915_gem_object *obj_priv = obj->driver_private;
676 drm_i915_private_t *dev_priv = dev->dev_private;
677 ssize_t remain;
678 loff_t gtt_page_base, offset;
679 loff_t first_data_page, last_data_page, num_pages;
680 loff_t pinned_pages, i;
681 struct page **user_pages;
682 struct mm_struct *mm = current->mm;
683 int gtt_page_offset, data_page_offset, data_page_index, page_length;
673a394b 684 int ret;
3de09aa3
EA		 685 uint64_t data_ptr = args->data_ptr;
686
687 remain = args->size;
688
689 /* Pin the user pages containing the data. We can't fault while
690 * holding the struct mutex, and all of the pwrite implementations
691 * want to hold it while dereferencing the user data.
692 */
693 first_data_page = data_ptr / PAGE_SIZE;
694 last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE;
695 num_pages = last_data_page - first_data_page + 1;
696
8e7d2b2c 697 user_pages = drm_calloc_large(num_pages, sizeof(struct page *));
3de09aa3
EA		 698 if (user_pages == NULL)
699 return -ENOMEM;
700
701 down_read(&mm->mmap_sem);
702 pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr,
703 num_pages, 0, 0, user_pages, NULL);
704 up_read(&mm->mmap_sem);
705 if (pinned_pages < num_pages) {
706 ret = -EFAULT;
707 goto out_unpin_pages;
708 }
673a394b
EA		 709
710 mutex_lock(&dev->struct_mutex);
3de09aa3
EA		 711 ret = i915_gem_object_pin(obj, 0);
712 if (ret)
713 goto out_unlock;
714
715 ret = i915_gem_object_set_to_gtt_domain(obj, 1);
716 if (ret)
717 goto out_unpin_object;
718
719 obj_priv = obj->driver_private;
720 offset = obj_priv->gtt_offset + args->offset;
721
722 while (remain > 0) {
723 /* Operation in this page
724 *
725 * gtt_page_base = page offset within aperture
726 * gtt_page_offset = offset within page in aperture
727 * data_page_index = page number in get_user_pages return
728 * data_page_offset = offset with data_page_index page.
729 * page_length = bytes to copy for this page
730 */
731 gtt_page_base = offset & PAGE_MASK;
732 gtt_page_offset = offset & ~PAGE_MASK;
733 data_page_index = data_ptr / PAGE_SIZE - first_data_page;
734 data_page_offset = data_ptr & ~PAGE_MASK;
735
736 page_length = remain;
737 if ((gtt_page_offset + page_length) > PAGE_SIZE)
738 page_length = PAGE_SIZE - gtt_page_offset;
739 if ((data_page_offset + page_length) > PAGE_SIZE)
740 page_length = PAGE_SIZE - data_page_offset;
741
742 ret = slow_kernel_write(dev_priv->mm.gtt_mapping,
743 gtt_page_base, gtt_page_offset,
744 user_pages[data_page_index],
745 data_page_offset,
746 page_length);
747
748 /* If we get a fault while copying data, then (presumably) our
749 * source page isn't available. Return the error and we'll
750 * retry in the slow path.
751 */
752 if (ret)
753 goto out_unpin_object;
754
755 remain -= page_length;
756 offset += page_length;
757 data_ptr += page_length;
758 }
759
760out_unpin_object:
761 i915_gem_object_unpin(obj);
762out_unlock:
763 mutex_unlock(&dev->struct_mutex);
764out_unpin_pages:
765 for (i = 0; i < pinned_pages; i++)
766 page_cache_release(user_pages[i]);
8e7d2b2c 767 drm_free_large(user_pages);
3de09aa3
EA		 768
769 return ret;
770}
771
40123c1f
EA		 772/**
773 * This is the fast shmem pwrite path, which attempts to directly
774 * copy_from_user into the kmapped pages backing the object.
775 */
3043c60c 776static int
40123c1f
EA		 777i915_gem_shmem_pwrite_fast(struct drm_device *dev, struct drm_gem_object *obj,
778 struct drm_i915_gem_pwrite *args,
779 struct drm_file *file_priv)
673a394b 780{
40123c1f
EA		 781 struct drm_i915_gem_object *obj_priv = obj->driver_private;
782 ssize_t remain;
783 loff_t offset, page_base;
784 char __user *user_data;
785 int page_offset, page_length;
673a394b 786 int ret;
40123c1f
EA		 787
788 user_data = (char __user *) (uintptr_t) args->data_ptr;
789 remain = args->size;
673a394b
EA		 790
791 mutex_lock(&dev->struct_mutex);
792
40123c1f
EA		 793 ret = i915_gem_object_get_pages(obj);
794 if (ret != 0)
795 goto fail_unlock;
673a394b 796
e47c68e9 797 ret = i915_gem_object_set_to_cpu_domain(obj, 1);
40123c1f
EA		 798 if (ret != 0)
799 goto fail_put_pages;
800
801 obj_priv = obj->driver_private;
802 offset = args->offset;
803 obj_priv->dirty = 1;
804
805 while (remain > 0) {
806 /* Operation in this page
807 *
808 * page_base = page offset within aperture
809 * page_offset = offset within page
810 * page_length = bytes to copy for this page
811 */
812 page_base = (offset & ~(PAGE_SIZE-1));
813 page_offset = offset & (PAGE_SIZE-1);
814 page_length = remain;
815 if ((page_offset + remain) > PAGE_SIZE)
816 page_length = PAGE_SIZE - page_offset;
817
818 ret = fast_shmem_write(obj_priv->pages,
819 page_base, page_offset,
820 user_data, page_length);
821 if (ret)
822 goto fail_put_pages;
823
824 remain -= page_length;
825 user_data += page_length;
826 offset += page_length;
827 }
828
829fail_put_pages:
830 i915_gem_object_put_pages(obj);
831fail_unlock:
832 mutex_unlock(&dev->struct_mutex);
833
834 return ret;
835}
836
837/**
838 * This is the fallback shmem pwrite path, which uses get_user_pages to pin
839 * the memory and maps it using kmap_atomic for copying.
840 *
841 * This avoids taking mmap_sem for faulting on the user's address while the
842 * struct_mutex is held.
843 */
844static int
845i915_gem_shmem_pwrite_slow(struct drm_device *dev, struct drm_gem_object *obj,
846 struct drm_i915_gem_pwrite *args,
847 struct drm_file *file_priv)
848{
849 struct drm_i915_gem_object *obj_priv = obj->driver_private;
850 struct mm_struct *mm = current->mm;
851 struct page **user_pages;
852 ssize_t remain;
853 loff_t offset, pinned_pages, i;
854 loff_t first_data_page, last_data_page, num_pages;
855 int shmem_page_index, shmem_page_offset;
856 int data_page_index, data_page_offset;
857 int page_length;
858 int ret;
859 uint64_t data_ptr = args->data_ptr;
280b713b 860 int do_bit17_swizzling;
40123c1f
EA		 861
862 remain = args->size;
863
864 /* Pin the user pages containing the data. We can't fault while
865 * holding the struct mutex, and all of the pwrite implementations
866 * want to hold it while dereferencing the user data.
867 */
868 first_data_page = data_ptr / PAGE_SIZE;
869 last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE;
870 num_pages = last_data_page - first_data_page + 1;
871
8e7d2b2c 872 user_pages = drm_calloc_large(num_pages, sizeof(struct page *));
40123c1f
EA		 873 if (user_pages == NULL)
874 return -ENOMEM;
875
876 down_read(&mm->mmap_sem);
877 pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr,
878 num_pages, 0, 0, user_pages, NULL);
879 up_read(&mm->mmap_sem);
880 if (pinned_pages < num_pages) {
881 ret = -EFAULT;
882 goto fail_put_user_pages;
673a394b
EA		 883 }
884
280b713b
EA		 885 do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
886
40123c1f
EA		 887 mutex_lock(&dev->struct_mutex);
888
07f73f69
CW		 889 ret = i915_gem_object_get_pages_or_evict(obj);
890 if (ret)
40123c1f
EA		 891 goto fail_unlock;
892
893 ret = i915_gem_object_set_to_cpu_domain(obj, 1);
894 if (ret != 0)
895 goto fail_put_pages;
896
897 obj_priv = obj->driver_private;
673a394b 898 offset = args->offset;
40123c1f 899 obj_priv->dirty = 1;
673a394b 900
40123c1f
EA		 901 while (remain > 0) {
902 /* Operation in this page
903 *
904 * shmem_page_index = page number within shmem file
905 * shmem_page_offset = offset within page in shmem file
906 * data_page_index = page number in get_user_pages return
907 * data_page_offset = offset with data_page_index page.
908 * page_length = bytes to copy for this page
909 */
910 shmem_page_index = offset / PAGE_SIZE;
911 shmem_page_offset = offset & ~PAGE_MASK;
912 data_page_index = data_ptr / PAGE_SIZE - first_data_page;
913 data_page_offset = data_ptr & ~PAGE_MASK;
914
915 page_length = remain;
916 if ((shmem_page_offset + page_length) > PAGE_SIZE)
917 page_length = PAGE_SIZE - shmem_page_offset;
918 if ((data_page_offset + page_length) > PAGE_SIZE)
919 page_length = PAGE_SIZE - data_page_offset;
920
280b713b
EA		 921 if (do_bit17_swizzling) {
922 ret = slow_shmem_bit17_copy(obj_priv->pages[shmem_page_index],
923 shmem_page_offset,
924 user_pages[data_page_index],
925 data_page_offset,
926 page_length,
927 0);
928 } else {
929 ret = slow_shmem_copy(obj_priv->pages[shmem_page_index],
930 shmem_page_offset,
931 user_pages[data_page_index],
932 data_page_offset,
933 page_length);
934 }
40123c1f
EA		 935 if (ret)
936 goto fail_put_pages;
937
938 remain -= page_length;
939 data_ptr += page_length;
940 offset += page_length;
673a394b
EA		 941 }
942
40123c1f
EA		 943fail_put_pages:
944 i915_gem_object_put_pages(obj);
945fail_unlock:
673a394b 946 mutex_unlock(&dev->struct_mutex);
40123c1f
EA		 947fail_put_user_pages:
948 for (i = 0; i < pinned_pages; i++)
949 page_cache_release(user_pages[i]);
8e7d2b2c 950 drm_free_large(user_pages);
673a394b 951
40123c1f 952 return ret;
673a394b
EA		 953}
954
955/**
956 * Writes data to the object referenced by handle.
957 *
958 * On error, the contents of the buffer that were to be modified are undefined.
959 */
960int
961i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
962 struct drm_file *file_priv)
963{
964 struct drm_i915_gem_pwrite *args = data;
965 struct drm_gem_object *obj;
966 struct drm_i915_gem_object *obj_priv;
967 int ret = 0;
968
969 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
970 if (obj == NULL)
971 return -EBADF;
972 obj_priv = obj->driver_private;
973
974 /* Bounds check destination.
975 *
976 * XXX: This could use review for overflow issues...
977 */
978 if (args->offset > obj->size || args->size > obj->size ||
979 args->offset + args->size > obj->size) {
980 drm_gem_object_unreference(obj);
981 return -EINVAL;
982 }
983
984 /* We can only do the GTT pwrite on untiled buffers, as otherwise
985 * it would end up going through the fenced access, and we'll get
986 * different detiling behavior between reading and writing.
987 * pread/pwrite currently are reading and writing from the CPU
988 * perspective, requiring manual detiling by the client.
989 */
71acb5eb
DA		 990 if (obj_priv->phys_obj)
991 ret = i915_gem_phys_pwrite(dev, obj, args, file_priv);
992 else if (obj_priv->tiling_mode == I915_TILING_NONE &&
3de09aa3
EA		 993 dev->gtt_total != 0) {
994 ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file_priv);
995 if (ret == -EFAULT) {
996 ret = i915_gem_gtt_pwrite_slow(dev, obj, args,
997 file_priv);
998 }
280b713b
EA		 999 } else if (i915_gem_object_needs_bit17_swizzle(obj)) {
1000 ret = i915_gem_shmem_pwrite_slow(dev, obj, args, file_priv);
40123c1f
EA		 1001 } else {
1002 ret = i915_gem_shmem_pwrite_fast(dev, obj, args, file_priv);
1003 if (ret == -EFAULT) {
1004 ret = i915_gem_shmem_pwrite_slow(dev, obj, args,
1005 file_priv);
1006 }
1007 }
673a394b
EA		 1008
1009#if WATCH_PWRITE
1010 if (ret)
1011 DRM_INFO("pwrite failed %d\n", ret);
1012#endif
1013
1014 drm_gem_object_unreference(obj);
1015
1016 return ret;
1017}
1018
1019/**
2ef7eeaa
EA		 1020 * Called when user space prepares to use an object with the CPU, either
1021 * through the mmap ioctl's mapping or a GTT mapping.
673a394b
EA		 1022 */
1023int
1024i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1025 struct drm_file *file_priv)
1026{
a09ba7fa 1027 struct drm_i915_private *dev_priv = dev->dev_private;
673a394b
EA		 1028 struct drm_i915_gem_set_domain *args = data;
1029 struct drm_gem_object *obj;
652c393a 1030 struct drm_i915_gem_object *obj_priv;
2ef7eeaa
EA		 1031 uint32_t read_domains = args->read_domains;
1032 uint32_t write_domain = args->write_domain;
673a394b
EA		 1033 int ret;
1034
1035 if (!(dev->driver->driver_features & DRIVER_GEM))
1036 return -ENODEV;
1037
2ef7eeaa 1038 /* Only handle setting domains to types used by the CPU. */
21d509e3 1039 if (write_domain & I915_GEM_GPU_DOMAINS)
2ef7eeaa
EA		 1040 return -EINVAL;
1041
21d509e3 1042 if (read_domains & I915_GEM_GPU_DOMAINS)
2ef7eeaa
EA		 1043 return -EINVAL;
1044
1045 /* Having something in the write domain implies it's in the read
1046 * domain, and only that read domain. Enforce that in the request.
1047 */
1048 if (write_domain != 0 && read_domains != write_domain)
1049 return -EINVAL;
1050
673a394b
EA		 1051 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
1052 if (obj == NULL)
1053 return -EBADF;
652c393a 1054 obj_priv = obj->driver_private;
673a394b
EA		 1055
1056 mutex_lock(&dev->struct_mutex);
652c393a
JB		 1057
1058 intel_mark_busy(dev, obj);
1059
673a394b 1060#if WATCH_BUF
cfd43c02 1061 DRM_INFO("set_domain_ioctl %p(%zd), %08x %08x\n",
2ef7eeaa 1062 obj, obj->size, read_domains, write_domain);
673a394b 1063#endif
2ef7eeaa
EA		 1064 if (read_domains & I915_GEM_DOMAIN_GTT) {
1065 ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0);
02354392 1066
a09ba7fa
EA		 1067 /* Update the LRU on the fence for the CPU access that's
1068 * about to occur.
1069 */
1070 if (obj_priv->fence_reg != I915_FENCE_REG_NONE) {
1071 list_move_tail(&obj_priv->fence_list,
1072 &dev_priv->mm.fence_list);
1073 }
1074
02354392
EA		 1075 /* Silently promote "you're not bound, there was nothing to do"
1076 * to success, since the client was just asking us to
1077 * make sure everything was done.
1078 */
1079 if (ret == -EINVAL)
1080 ret = 0;
2ef7eeaa 1081 } else {
e47c68e9 1082 ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0);
2ef7eeaa
EA		 1083 }
1084
673a394b
EA		 1085 drm_gem_object_unreference(obj);
1086 mutex_unlock(&dev->struct_mutex);
1087 return ret;
1088}
1089
1090/**
1091 * Called when user space has done writes to this buffer
1092 */
1093int
1094i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
1095 struct drm_file *file_priv)
1096{
1097 struct drm_i915_gem_sw_finish *args = data;
1098 struct drm_gem_object *obj;
1099 struct drm_i915_gem_object *obj_priv;
1100 int ret = 0;
1101
1102 if (!(dev->driver->driver_features & DRIVER_GEM))
1103 return -ENODEV;
1104
1105 mutex_lock(&dev->struct_mutex);
1106 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
1107 if (obj == NULL) {
1108 mutex_unlock(&dev->struct_mutex);
1109 return -EBADF;
1110 }
1111
1112#if WATCH_BUF
cfd43c02 1113 DRM_INFO("%s: sw_finish %d (%p %zd)\n",
673a394b
EA		 1114 __func__, args->handle, obj, obj->size);
1115#endif
1116 obj_priv = obj->driver_private;
1117
1118 /* Pinned buffers may be scanout, so flush the cache */
e47c68e9
EA		 1119 if (obj_priv->pin_count)
1120 i915_gem_object_flush_cpu_write_domain(obj);
1121
673a394b
EA		 1122 drm_gem_object_unreference(obj);
1123 mutex_unlock(&dev->struct_mutex);
1124 return ret;
1125}
1126
1127/**
1128 * Maps the contents of an object, returning the address it is mapped
1129 * into.
1130 *
1131 * While the mapping holds a reference on the contents of the object, it doesn't
1132 * imply a ref on the object itself.
1133 */
1134int
1135i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
1136 struct drm_file *file_priv)
1137{
1138 struct drm_i915_gem_mmap *args = data;
1139 struct drm_gem_object *obj;
1140 loff_t offset;
1141 unsigned long addr;
1142
1143 if (!(dev->driver->driver_features & DRIVER_GEM))
1144 return -ENODEV;
1145
1146 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
1147 if (obj == NULL)
1148 return -EBADF;
1149
1150 offset = args->offset;
1151
1152 down_write(&current->mm->mmap_sem);
1153 addr = do_mmap(obj->filp, 0, args->size,
1154 PROT_READ | PROT_WRITE, MAP_SHARED,
1155 args->offset);
1156 up_write(&current->mm->mmap_sem);
1157 mutex_lock(&dev->struct_mutex);
1158 drm_gem_object_unreference(obj);
1159 mutex_unlock(&dev->struct_mutex);
1160 if (IS_ERR((void *)addr))
1161 return addr;
1162
1163 args->addr_ptr = (uint64_t) addr;
1164
1165 return 0;
1166}
1167
de151cf6
JB		 1168/**
1169 * i915_gem_fault - fault a page into the GTT
1170 * vma: VMA in question
1171 * vmf: fault info
1172 *
1173 * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
1174 * from userspace. The fault handler takes care of binding the object to
1175 * the GTT (if needed), allocating and programming a fence register (again,
1176 * only if needed based on whether the old reg is still valid or the object
1177 * is tiled) and inserting a new PTE into the faulting process.
1178 *
1179 * Note that the faulting process may involve evicting existing objects
1180 * from the GTT and/or fence registers to make room. So performance may
1181 * suffer if the GTT working set is large or there are few fence registers
1182 * left.
1183 */
1184int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
1185{
1186 struct drm_gem_object *obj = vma->vm_private_data;
1187 struct drm_device *dev = obj->dev;
1188 struct drm_i915_private *dev_priv = dev->dev_private;
1189 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1190 pgoff_t page_offset;
1191 unsigned long pfn;
1192 int ret = 0;
0f973f27 1193 bool write = !!(vmf->flags & FAULT_FLAG_WRITE);
de151cf6
JB		 1194
1195 /* We don't use vmf->pgoff since that has the fake offset */
1196 page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >>
1197 PAGE_SHIFT;
1198
1199 /* Now bind it into the GTT if needed */
1200 mutex_lock(&dev->struct_mutex);
1201 if (!obj_priv->gtt_space) {
e67b8ce1 1202 ret = i915_gem_object_bind_to_gtt(obj, 0);
de151cf6
JB		 1203 if (ret) {
1204 mutex_unlock(&dev->struct_mutex);
1205 return VM_FAULT_SIGBUS;
1206 }
4960aaca 1207 list_add_tail(&obj_priv->list, &dev_priv->mm.inactive_list);
07f4f3e8
KH		 1208
1209 ret = i915_gem_object_set_to_gtt_domain(obj, write);
1210 if (ret) {
1211 mutex_unlock(&dev->struct_mutex);
1212 return VM_FAULT_SIGBUS;
1213 }
de151cf6
JB		 1214 }
1215
1216 /* Need a new fence register? */
a09ba7fa 1217 if (obj_priv->tiling_mode != I915_TILING_NONE) {
8c4b8c3f 1218 ret = i915_gem_object_get_fence_reg(obj);
7d8d58b2
CW		 1219 if (ret) {
1220 mutex_unlock(&dev->struct_mutex);
d9ddcb96 1221 return VM_FAULT_SIGBUS;
7d8d58b2 1222 }
d9ddcb96 1223 }
de151cf6
JB		 1224
1225 pfn = ((dev->agp->base + obj_priv->gtt_offset) >> PAGE_SHIFT) +
1226 page_offset;
1227
1228 /* Finally, remap it using the new GTT offset */
1229 ret = vm_insert_pfn(vma, (unsigned long)vmf->virtual_address, pfn);
1230
1231 mutex_unlock(&dev->struct_mutex);
1232
1233 switch (ret) {
1234 case -ENOMEM:
1235 case -EAGAIN:
1236 return VM_FAULT_OOM;
1237 case -EFAULT:
959b887c 1238 case -EINVAL:
de151cf6
JB		 1239 return VM_FAULT_SIGBUS;
1240 default:
1241 return VM_FAULT_NOPAGE;
1242 }
1243}
1244
1245/**
1246 * i915_gem_create_mmap_offset - create a fake mmap offset for an object
1247 * @obj: obj in question
1248 *
1249 * GEM memory mapping works by handing back to userspace a fake mmap offset
1250 * it can use in a subsequent mmap(2) call. The DRM core code then looks
1251 * up the object based on the offset and sets up the various memory mapping
1252 * structures.
1253 *
1254 * This routine allocates and attaches a fake offset for @obj.
1255 */
1256static int
1257i915_gem_create_mmap_offset(struct drm_gem_object *obj)
1258{
1259 struct drm_device *dev = obj->dev;
1260 struct drm_gem_mm *mm = dev->mm_private;
1261 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1262 struct drm_map_list *list;
f77d390c 1263 struct drm_local_map *map;
de151cf6
JB		 1264 int ret = 0;
1265
1266 /* Set the object up for mmap'ing */
1267 list = &obj->map_list;
9a298b2a 1268 list->map = kzalloc(sizeof(struct drm_map_list), GFP_KERNEL);
de151cf6
JB		 1269 if (!list->map)
1270 return -ENOMEM;
1271
1272 map = list->map;
1273 map->type = _DRM_GEM;
1274 map->size = obj->size;
1275 map->handle = obj;
1276
1277 /* Get a DRM GEM mmap offset allocated... */
1278 list->file_offset_node = drm_mm_search_free(&mm->offset_manager,
1279 obj->size / PAGE_SIZE, 0, 0);
1280 if (!list->file_offset_node) {
1281 DRM_ERROR("failed to allocate offset for bo %d\n", obj->name);
1282 ret = -ENOMEM;
1283 goto out_free_list;
1284 }
1285
1286 list->file_offset_node = drm_mm_get_block(list->file_offset_node,
1287 obj->size / PAGE_SIZE, 0);
1288 if (!list->file_offset_node) {
1289 ret = -ENOMEM;
1290 goto out_free_list;
1291 }
1292
1293 list->hash.key = list->file_offset_node->start;
1294 if (drm_ht_insert_item(&mm->offset_hash, &list->hash)) {
1295 DRM_ERROR("failed to add to map hash\n");
1296 goto out_free_mm;
1297 }
1298
1299 /* By now we should be all set, any drm_mmap request on the offset
1300 * below will get to our mmap & fault handler */
1301 obj_priv->mmap_offset = ((uint64_t) list->hash.key) << PAGE_SHIFT;
1302
1303 return 0;
1304
1305out_free_mm:
1306 drm_mm_put_block(list->file_offset_node);
1307out_free_list:
9a298b2a 1308 kfree(list->map);
de151cf6
JB		 1309
1310 return ret;
1311}
1312
901782b2
CW		 1313/**
1314 * i915_gem_release_mmap - remove physical page mappings
1315 * @obj: obj in question
1316 *
1317 * Preserve the reservation of the mmaping with the DRM core code, but
1318 * relinquish ownership of the pages back to the system.
1319 *
1320 * It is vital that we remove the page mapping if we have mapped a tiled
1321 * object through the GTT and then lose the fence register due to
1322 * resource pressure. Similarly if the object has been moved out of the
1323 * aperture, than pages mapped into userspace must be revoked. Removing the
1324 * mapping will then trigger a page fault on the next user access, allowing
1325 * fixup by i915_gem_fault().
1326 */
d05ca301 1327void
901782b2
CW		 1328i915_gem_release_mmap(struct drm_gem_object *obj)
1329{
1330 struct drm_device *dev = obj->dev;
1331 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1332
1333 if (dev->dev_mapping)
1334 unmap_mapping_range(dev->dev_mapping,
1335 obj_priv->mmap_offset, obj->size, 1);
1336}
1337
ab00b3e5
JB		 1338static void
1339i915_gem_free_mmap_offset(struct drm_gem_object *obj)
1340{
1341 struct drm_device *dev = obj->dev;
1342 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1343 struct drm_gem_mm *mm = dev->mm_private;
1344 struct drm_map_list *list;
1345
1346 list = &obj->map_list;
1347 drm_ht_remove_item(&mm->offset_hash, &list->hash);
1348
1349 if (list->file_offset_node) {
1350 drm_mm_put_block(list->file_offset_node);
1351 list->file_offset_node = NULL;
1352 }
1353
1354 if (list->map) {
9a298b2a 1355 kfree(list->map);
ab00b3e5
JB		 1356 list->map = NULL;
1357 }
1358
1359 obj_priv->mmap_offset = 0;
1360}
1361
de151cf6
JB		 1362/**
1363 * i915_gem_get_gtt_alignment - return required GTT alignment for an object
1364 * @obj: object to check
1365 *
1366 * Return the required GTT alignment for an object, taking into account
1367 * potential fence register mapping if needed.
1368 */
1369static uint32_t
1370i915_gem_get_gtt_alignment(struct drm_gem_object *obj)
1371{
1372 struct drm_device *dev = obj->dev;
1373 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1374 int start, i;
1375
1376 /*
1377 * Minimum alignment is 4k (GTT page size), but might be greater
1378 * if a fence register is needed for the object.
1379 */
1380 if (IS_I965G(dev) || obj_priv->tiling_mode == I915_TILING_NONE)
1381 return 4096;
1382
1383 /*
1384 * Previous chips need to be aligned to the size of the smallest
1385 * fence register that can contain the object.
1386 */
1387 if (IS_I9XX(dev))
1388 start = 1024*1024;
1389 else
1390 start = 512*1024;
1391
1392 for (i = start; i < obj->size; i <<= 1)
1393 ;
1394
1395 return i;
1396}
1397
1398/**
1399 * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
1400 * @dev: DRM device
1401 * @data: GTT mapping ioctl data
1402 * @file_priv: GEM object info
1403 *
1404 * Simply returns the fake offset to userspace so it can mmap it.
1405 * The mmap call will end up in drm_gem_mmap(), which will set things
1406 * up so we can get faults in the handler above.
1407 *
1408 * The fault handler will take care of binding the object into the GTT
1409 * (since it may have been evicted to make room for something), allocating
1410 * a fence register, and mapping the appropriate aperture address into
1411 * userspace.
1412 */
1413int
1414i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
1415 struct drm_file *file_priv)
1416{
1417 struct drm_i915_gem_mmap_gtt *args = data;
1418 struct drm_i915_private *dev_priv = dev->dev_private;
1419 struct drm_gem_object *obj;
1420 struct drm_i915_gem_object *obj_priv;
1421 int ret;
1422
1423 if (!(dev->driver->driver_features & DRIVER_GEM))
1424 return -ENODEV;
1425
1426 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
1427 if (obj == NULL)
1428 return -EBADF;
1429
1430 mutex_lock(&dev->struct_mutex);
1431
1432 obj_priv = obj->driver_private;
1433
ab18282d
CW		 1434 if (obj_priv->madv != I915_MADV_WILLNEED) {
1435 DRM_ERROR("Attempting to mmap a purgeable buffer\n");
1436 drm_gem_object_unreference(obj);
1437 mutex_unlock(&dev->struct_mutex);
1438 return -EINVAL;
1439 }
1440
1441
de151cf6
JB		 1442 if (!obj_priv->mmap_offset) {
1443 ret = i915_gem_create_mmap_offset(obj);
13af1062
CW		 1444 if (ret) {
1445 drm_gem_object_unreference(obj);
1446 mutex_unlock(&dev->struct_mutex);
de151cf6 1447 return ret;
13af1062 1448 }
de151cf6
JB		 1449 }
1450
1451 args->offset = obj_priv->mmap_offset;
1452
de151cf6
JB		 1453 /*
1454 * Pull it into the GTT so that we have a page list (makes the
1455 * initial fault faster and any subsequent flushing possible).
1456 */
1457 if (!obj_priv->agp_mem) {
e67b8ce1 1458 ret = i915_gem_object_bind_to_gtt(obj, 0);
de151cf6
JB		 1459 if (ret) {
1460 drm_gem_object_unreference(obj);
1461 mutex_unlock(&dev->struct_mutex);
1462 return ret;
1463 }
14b60391 1464 list_add_tail(&obj_priv->list, &dev_priv->mm.inactive_list);
de151cf6
JB		 1465 }
1466
1467 drm_gem_object_unreference(obj);
1468 mutex_unlock(&dev->struct_mutex);
1469
1470 return 0;
1471}
1472
6911a9b8 1473void
856fa198 1474i915_gem_object_put_pages(struct drm_gem_object *obj)
673a394b
EA		 1475{
1476 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1477 int page_count = obj->size / PAGE_SIZE;
1478 int i;
1479
856fa198 1480 BUG_ON(obj_priv->pages_refcount == 0);
bb6baf76 1481 BUG_ON(obj_priv->madv == __I915_MADV_PURGED);
673a394b 1482
856fa198
EA		 1483 if (--obj_priv->pages_refcount != 0)
1484 return;
673a394b 1485
280b713b
EA		 1486 if (obj_priv->tiling_mode != I915_TILING_NONE)
1487 i915_gem_object_save_bit_17_swizzle(obj);
1488
3ef94daa 1489 if (obj_priv->madv == I915_MADV_DONTNEED)
13a05fd9 1490 obj_priv->dirty = 0;
3ef94daa
CW		 1491
1492 for (i = 0; i < page_count; i++) {
1493 if (obj_priv->pages[i] == NULL)
1494 break;
1495
1496 if (obj_priv->dirty)
1497 set_page_dirty(obj_priv->pages[i]);
1498
1499 if (obj_priv->madv == I915_MADV_WILLNEED)
13a05fd9 1500 mark_page_accessed(obj_priv->pages[i]);
3ef94daa
CW		 1501
1502 page_cache_release(obj_priv->pages[i]);
1503 }
673a394b
EA		 1504 obj_priv->dirty = 0;
1505
8e7d2b2c 1506 drm_free_large(obj_priv->pages);
856fa198 1507 obj_priv->pages = NULL;
673a394b
EA		 1508}
1509
1510static void
ce44b0ea 1511i915_gem_object_move_to_active(struct drm_gem_object *obj, uint32_t seqno)
673a394b
EA		 1512{
1513 struct drm_device *dev = obj->dev;
1514 drm_i915_private_t *dev_priv = dev->dev_private;
1515 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1516
1517 /* Add a reference if we're newly entering the active list. */
1518 if (!obj_priv->active) {
1519 drm_gem_object_reference(obj);
1520 obj_priv->active = 1;
1521 }
1522 /* Move from whatever list we were on to the tail of execution. */
5e118f41 1523 spin_lock(&dev_priv->mm.active_list_lock);
673a394b
EA		 1524 list_move_tail(&obj_priv->list,
1525 &dev_priv->mm.active_list);
5e118f41 1526 spin_unlock(&dev_priv->mm.active_list_lock);
ce44b0ea 1527 obj_priv->last_rendering_seqno = seqno;
673a394b
EA		 1528}
1529
ce44b0ea
EA		 1530static void
1531i915_gem_object_move_to_flushing(struct drm_gem_object *obj)
1532{
1533 struct drm_device *dev = obj->dev;
1534 drm_i915_private_t *dev_priv = dev->dev_private;
1535 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1536
1537 BUG_ON(!obj_priv->active);
1538 list_move_tail(&obj_priv->list, &dev_priv->mm.flushing_list);
1539 obj_priv->last_rendering_seqno = 0;
1540}
673a394b 1541
963b4836
CW		 1542/* Immediately discard the backing storage */
1543static void
1544i915_gem_object_truncate(struct drm_gem_object *obj)
1545{
bb6baf76
CW		 1546 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1547 struct inode *inode;
963b4836 1548
bb6baf76
CW		 1549 inode = obj->filp->f_path.dentry->d_inode;
1550 if (inode->i_op->truncate)
1551 inode->i_op->truncate (inode);
1552
1553 obj_priv->madv = __I915_MADV_PURGED;
963b4836
CW		 1554}
1555
1556static inline int
1557i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj_priv)
1558{
1559 return obj_priv->madv == I915_MADV_DONTNEED;
1560}
1561
673a394b
EA		 1562static void
1563i915_gem_object_move_to_inactive(struct drm_gem_object *obj)
1564{
1565 struct drm_device *dev = obj->dev;
1566 drm_i915_private_t *dev_priv = dev->dev_private;
1567 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1568
1569 i915_verify_inactive(dev, __FILE__, __LINE__);
1570 if (obj_priv->pin_count != 0)
1571 list_del_init(&obj_priv->list);
1572 else
1573 list_move_tail(&obj_priv->list, &dev_priv->mm.inactive_list);
1574
ce44b0ea 1575 obj_priv->last_rendering_seqno = 0;
673a394b
EA		 1576 if (obj_priv->active) {
1577 obj_priv->active = 0;
1578 drm_gem_object_unreference(obj);
1579 }
1580 i915_verify_inactive(dev, __FILE__, __LINE__);
1581}
1582
1583/**
1584 * Creates a new sequence number, emitting a write of it to the status page
1585 * plus an interrupt, which will trigger i915_user_interrupt_handler.
1586 *
1587 * Must be called with struct_lock held.
1588 *
1589 * Returned sequence numbers are nonzero on success.
1590 */
1591static uint32_t
b962442e
EA		 1592i915_add_request(struct drm_device *dev, struct drm_file *file_priv,
1593 uint32_t flush_domains)
673a394b
EA		 1594{
1595 drm_i915_private_t *dev_priv = dev->dev_private;
b962442e 1596 struct drm_i915_file_private *i915_file_priv = NULL;
673a394b
EA		 1597 struct drm_i915_gem_request *request;
1598 uint32_t seqno;
1599 int was_empty;
1600 RING_LOCALS;
1601
b962442e
EA		 1602 if (file_priv != NULL)
1603 i915_file_priv = file_priv->driver_priv;
1604
9a298b2a 1605 request = kzalloc(sizeof(*request), GFP_KERNEL);
673a394b
EA		 1606 if (request == NULL)
1607 return 0;
1608
1609 /* Grab the seqno we're going to make this request be, and bump the
1610 * next (skipping 0 so it can be the reserved no-seqno value).
1611 */
1612 seqno = dev_priv->mm.next_gem_seqno;
1613 dev_priv->mm.next_gem_seqno++;
1614 if (dev_priv->mm.next_gem_seqno == 0)
1615 dev_priv->mm.next_gem_seqno++;
1616
1617 BEGIN_LP_RING(4);
1618 OUT_RING(MI_STORE_DWORD_INDEX);
1619 OUT_RING(I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
1620 OUT_RING(seqno);
1621
1622 OUT_RING(MI_USER_INTERRUPT);
1623 ADVANCE_LP_RING();
1624
1625 DRM_DEBUG("%d\n", seqno);
1626
1627 request->seqno = seqno;
1628 request->emitted_jiffies = jiffies;
673a394b
EA		 1629 was_empty = list_empty(&dev_priv->mm.request_list);
1630 list_add_tail(&request->list, &dev_priv->mm.request_list);
b962442e
EA		 1631 if (i915_file_priv) {
1632 list_add_tail(&request->client_list,
1633 &i915_file_priv->mm.request_list);
1634 } else {
1635 INIT_LIST_HEAD(&request->client_list);
1636 }
673a394b 1637
ce44b0ea
EA		 1638 /* Associate any objects on the flushing list matching the write
1639 * domain we're flushing with our flush.
1640 */
1641 if (flush_domains != 0) {
1642 struct drm_i915_gem_object *obj_priv, *next;
1643
1644 list_for_each_entry_safe(obj_priv, next,
1645 &dev_priv->mm.flushing_list, list) {
1646 struct drm_gem_object *obj = obj_priv->obj;
1647
1648 if ((obj->write_domain & flush_domains) ==
1649 obj->write_domain) {
1c5d22f7
CW		 1650 uint32_t old_write_domain = obj->write_domain;
1651
ce44b0ea
EA		 1652 obj->write_domain = 0;
1653 i915_gem_object_move_to_active(obj, seqno);
1c5d22f7
CW		 1654
1655 trace_i915_gem_object_change_domain(obj,
1656 obj->read_domains,
1657 old_write_domain);
ce44b0ea
EA		 1658 }
1659 }
1660
1661 }
1662
f65d9421
BG		 1663 if (!dev_priv->mm.suspended) {
1664 mod_timer(&dev_priv->hangcheck_timer, jiffies + DRM_I915_HANGCHECK_PERIOD);
1665 if (was_empty)
1666 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ);
1667 }
673a394b
EA		 1668 return seqno;
1669}
1670
1671/**
1672 * Command execution barrier
1673 *
1674 * Ensures that all commands in the ring are finished
1675 * before signalling the CPU
1676 */
3043c60c 1677static uint32_t
673a394b
EA		 1678i915_retire_commands(struct drm_device *dev)
1679{
1680 drm_i915_private_t *dev_priv = dev->dev_private;
1681 uint32_t cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
1682 uint32_t flush_domains = 0;
1683 RING_LOCALS;
1684
1685 /* The sampler always gets flushed on i965 (sigh) */
1686 if (IS_I965G(dev))
1687 flush_domains |= I915_GEM_DOMAIN_SAMPLER;
1688 BEGIN_LP_RING(2);
1689 OUT_RING(cmd);
1690 OUT_RING(0); /* noop */
1691 ADVANCE_LP_RING();
1692 return flush_domains;
1693}
1694
1695/**
1696 * Moves buffers associated only with the given active seqno from the active
1697 * to inactive list, potentially freeing them.
1698 */
1699static void
1700i915_gem_retire_request(struct drm_device *dev,
1701 struct drm_i915_gem_request *request)
1702{
1703 drm_i915_private_t *dev_priv = dev->dev_private;
1704
1c5d22f7
CW		 1705 trace_i915_gem_request_retire(dev, request->seqno);
1706
673a394b
EA		 1707 /* Move any buffers on the active list that are no longer referenced
1708 * by the ringbuffer to the flushing/inactive lists as appropriate.
1709 */
5e118f41 1710 spin_lock(&dev_priv->mm.active_list_lock);
673a394b
EA		 1711 while (!list_empty(&dev_priv->mm.active_list)) {
1712 struct drm_gem_object *obj;
1713 struct drm_i915_gem_object *obj_priv;
1714
1715 obj_priv = list_first_entry(&dev_priv->mm.active_list,
1716 struct drm_i915_gem_object,
1717 list);
1718 obj = obj_priv->obj;
1719
1720 /* If the seqno being retired doesn't match the oldest in the
1721 * list, then the oldest in the list must still be newer than
1722 * this seqno.
1723 */
1724 if (obj_priv->last_rendering_seqno != request->seqno)
5e118f41 1725 goto out;
de151cf6 1726
673a394b
EA		 1727#if WATCH_LRU
1728 DRM_INFO("%s: retire %d moves to inactive list %p\n",
1729 __func__, request->seqno, obj);
1730#endif
1731
ce44b0ea
EA		 1732 if (obj->write_domain != 0)
1733 i915_gem_object_move_to_flushing(obj);
68c84342
SL		 1734 else {
1735 /* Take a reference on the object so it won't be
1736 * freed while the spinlock is held. The list
1737 * protection for this spinlock is safe when breaking
1738 * the lock like this since the next thing we do
1739 * is just get the head of the list again.
1740 */
1741 drm_gem_object_reference(obj);
673a394b 1742 i915_gem_object_move_to_inactive(obj);
68c84342
SL		 1743 spin_unlock(&dev_priv->mm.active_list_lock);
1744 drm_gem_object_unreference(obj);
1745 spin_lock(&dev_priv->mm.active_list_lock);
1746 }
673a394b 1747 }
5e118f41
CW		 1748out:
1749 spin_unlock(&dev_priv->mm.active_list_lock);
673a394b
EA		 1750}
1751
1752/**
1753 * Returns true if seq1 is later than seq2.
1754 */
22be1724 1755bool
673a394b
EA		 1756i915_seqno_passed(uint32_t seq1, uint32_t seq2)
1757{
1758 return (int32_t)(seq1 - seq2) >= 0;
1759}
1760
1761uint32_t
1762i915_get_gem_seqno(struct drm_device *dev)
1763{
1764 drm_i915_private_t *dev_priv = dev->dev_private;
1765
1766 return READ_HWSP(dev_priv, I915_GEM_HWS_INDEX);
1767}
1768
1769/**
1770 * This function clears the request list as sequence numbers are passed.
1771 */
1772void
1773i915_gem_retire_requests(struct drm_device *dev)
1774{
1775 drm_i915_private_t *dev_priv = dev->dev_private;
1776 uint32_t seqno;
1777
6c0594a3
KW		 1778 if (!dev_priv->hw_status_page)
1779 return;
1780
673a394b
EA		 1781 seqno = i915_get_gem_seqno(dev);
1782
1783 while (!list_empty(&dev_priv->mm.request_list)) {
1784 struct drm_i915_gem_request *request;
1785 uint32_t retiring_seqno;
1786
1787 request = list_first_entry(&dev_priv->mm.request_list,
1788 struct drm_i915_gem_request,
1789 list);
1790 retiring_seqno = request->seqno;
1791
1792 if (i915_seqno_passed(seqno, retiring_seqno) ||
ba1234d1 1793 atomic_read(&dev_priv->mm.wedged)) {
673a394b
EA		 1794 i915_gem_retire_request(dev, request);
1795
1796 list_del(&request->list);
b962442e 1797 list_del(&request->client_list);
9a298b2a 1798 kfree(request);
673a394b
EA		 1799 } else
1800 break;
1801 }
1802}
1803
1804void
1805i915_gem_retire_work_handler(struct work_struct *work)
1806{
1807 drm_i915_private_t *dev_priv;
1808 struct drm_device *dev;
1809
1810 dev_priv = container_of(work, drm_i915_private_t,
1811 mm.retire_work.work);
1812 dev = dev_priv->dev;
1813
1814 mutex_lock(&dev->struct_mutex);
1815 i915_gem_retire_requests(dev);
6dbe2772
KP		 1816 if (!dev_priv->mm.suspended &&
1817 !list_empty(&dev_priv->mm.request_list))
9c9fe1f8 1818 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ);
673a394b
EA		 1819 mutex_unlock(&dev->struct_mutex);
1820}
1821
1822/**
1823 * Waits for a sequence number to be signaled, and cleans up the
1824 * request and object lists appropriately for that event.
1825 */
3043c60c 1826static int
673a394b
EA		 1827i915_wait_request(struct drm_device *dev, uint32_t seqno)
1828{
1829 drm_i915_private_t *dev_priv = dev->dev_private;
802c7eb6 1830 u32 ier;
673a394b
EA		 1831 int ret = 0;
1832
1833 BUG_ON(seqno == 0);
1834
ba1234d1 1835 if (atomic_read(&dev_priv->mm.wedged))
ffed1d09
BG		 1836 return -EIO;
1837
673a394b 1838 if (!i915_seqno_passed(i915_get_gem_seqno(dev), seqno)) {
036a4a7d
ZW		 1839 if (IS_IGDNG(dev))
1840 ier = I915_READ(DEIER) | I915_READ(GTIER);
1841 else
1842 ier = I915_READ(IER);
802c7eb6
JB		 1843 if (!ier) {
1844 DRM_ERROR("something (likely vbetool) disabled "
1845 "interrupts, re-enabling\n");
1846 i915_driver_irq_preinstall(dev);
1847 i915_driver_irq_postinstall(dev);
1848 }
1849
1c5d22f7
CW		 1850 trace_i915_gem_request_wait_begin(dev, seqno);
1851
673a394b
EA		 1852 dev_priv->mm.waiting_gem_seqno = seqno;
1853 i915_user_irq_get(dev);
1854 ret = wait_event_interruptible(dev_priv->irq_queue,
1855 i915_seqno_passed(i915_get_gem_seqno(dev),
1856 seqno) ||
ba1234d1 1857 atomic_read(&dev_priv->mm.wedged));
673a394b
EA		 1858 i915_user_irq_put(dev);
1859 dev_priv->mm.waiting_gem_seqno = 0;
1c5d22f7
CW		 1860
1861 trace_i915_gem_request_wait_end(dev, seqno);
673a394b 1862 }
ba1234d1 1863 if (atomic_read(&dev_priv->mm.wedged))
673a394b
EA		 1864 ret = -EIO;
1865
1866 if (ret && ret != -ERESTARTSYS)
1867 DRM_ERROR("%s returns %d (awaiting %d at %d)\n",
1868 __func__, ret, seqno, i915_get_gem_seqno(dev));
1869
1870 /* Directly dispatch request retiring. While we have the work queue
1871 * to handle this, the waiter on a request often wants an associated
1872 * buffer to have made it to the inactive list, and we would need
1873 * a separate wait queue to handle that.
1874 */
1875 if (ret == 0)
1876 i915_gem_retire_requests(dev);
1877
1878 return ret;
1879}
1880
1881static void
1882i915_gem_flush(struct drm_device *dev,
1883 uint32_t invalidate_domains,
1884 uint32_t flush_domains)
1885{
1886 drm_i915_private_t *dev_priv = dev->dev_private;
1887 uint32_t cmd;
1888 RING_LOCALS;
1889
1890#if WATCH_EXEC
1891 DRM_INFO("%s: invalidate %08x flush %08x\n", __func__,
1892 invalidate_domains, flush_domains);
1893#endif
1c5d22f7
CW		 1894 trace_i915_gem_request_flush(dev, dev_priv->mm.next_gem_seqno,
1895 invalidate_domains, flush_domains);
673a394b
EA		 1896
1897 if (flush_domains & I915_GEM_DOMAIN_CPU)
1898 drm_agp_chipset_flush(dev);
1899
21d509e3 1900 if ((invalidate_domains | flush_domains) & I915_GEM_GPU_DOMAINS) {
673a394b
EA		 1901 /*
1902 * read/write caches:
1903 *
1904 * I915_GEM_DOMAIN_RENDER is always invalidated, but is
1905 * only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is
1906 * also flushed at 2d versus 3d pipeline switches.
1907 *
1908 * read-only caches:
1909 *
1910 * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if
1911 * MI_READ_FLUSH is set, and is always flushed on 965.
1912 *
1913 * I915_GEM_DOMAIN_COMMAND may not exist?
1914 *
1915 * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is
1916 * invalidated when MI_EXE_FLUSH is set.
1917 *
1918 * I915_GEM_DOMAIN_VERTEX, which exists on 965, is
1919 * invalidated with every MI_FLUSH.
1920 *
1921 * TLBs:
1922 *
1923 * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND
1924 * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and
1925 * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
1926 * are flushed at any MI_FLUSH.
1927 */
1928
1929 cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
1930 if ((invalidate_domains|flush_domains) &
1931 I915_GEM_DOMAIN_RENDER)
1932 cmd &= ~MI_NO_WRITE_FLUSH;
1933 if (!IS_I965G(dev)) {
1934 /*
1935 * On the 965, the sampler cache always gets flushed
1936 * and this bit is reserved.
1937 */
1938 if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER)
1939 cmd |= MI_READ_FLUSH;
1940 }
1941 if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION)
1942 cmd |= MI_EXE_FLUSH;
1943
1944#if WATCH_EXEC
1945 DRM_INFO("%s: queue flush %08x to ring\n", __func__, cmd);
1946#endif
1947 BEGIN_LP_RING(2);
1948 OUT_RING(cmd);
1949 OUT_RING(0); /* noop */
1950 ADVANCE_LP_RING();
1951 }
1952}
1953
1954/**
1955 * Ensures that all rendering to the object has completed and the object is
1956 * safe to unbind from the GTT or access from the CPU.
1957 */
1958static int
1959i915_gem_object_wait_rendering(struct drm_gem_object *obj)
1960{
1961 struct drm_device *dev = obj->dev;
1962 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1963 int ret;
1964
e47c68e9
EA		 1965 /* This function only exists to support waiting for existing rendering,
1966 * not for emitting required flushes.
673a394b 1967 */
e47c68e9 1968 BUG_ON((obj->write_domain & I915_GEM_GPU_DOMAINS) != 0);
673a394b
EA		 1969
1970 /* If there is rendering queued on the buffer being evicted, wait for
1971 * it.
1972 */
1973 if (obj_priv->active) {
1974#if WATCH_BUF
1975 DRM_INFO("%s: object %p wait for seqno %08x\n",
1976 __func__, obj, obj_priv->last_rendering_seqno);
1977#endif
1978 ret = i915_wait_request(dev, obj_priv->last_rendering_seqno);
1979 if (ret != 0)
1980 return ret;
1981 }
1982
1983 return 0;
1984}
1985
1986/**
1987 * Unbinds an object from the GTT aperture.
1988 */
0f973f27 1989int
673a394b
EA		 1990i915_gem_object_unbind(struct drm_gem_object *obj)
1991{
1992 struct drm_device *dev = obj->dev;
1993 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1994 int ret = 0;
1995
1996#if WATCH_BUF
1997 DRM_INFO("%s:%d %p\n", __func__, __LINE__, obj);
1998 DRM_INFO("gtt_space %p\n", obj_priv->gtt_space);
1999#endif
2000 if (obj_priv->gtt_space == NULL)
2001 return 0;
2002
2003 if (obj_priv->pin_count != 0) {
2004 DRM_ERROR("Attempting to unbind pinned buffer\n");
2005 return -EINVAL;
2006 }
2007
5323fd04
EA		 2008 /* blow away mappings if mapped through GTT */
2009 i915_gem_release_mmap(obj);
2010
2011 if (obj_priv->fence_reg != I915_FENCE_REG_NONE)
2012 i915_gem_clear_fence_reg(obj);
2013
673a394b
EA		 2014 /* Move the object to the CPU domain to ensure that
2015 * any possible CPU writes while it's not in the GTT
2016 * are flushed when we go to remap it. This will
2017 * also ensure that all pending GPU writes are finished
2018 * before we unbind.
2019 */
e47c68e9 2020 ret = i915_gem_object_set_to_cpu_domain(obj, 1);
673a394b 2021 if (ret) {
e47c68e9
EA		 2022 if (ret != -ERESTARTSYS)
2023 DRM_ERROR("set_domain failed: %d\n", ret);
673a394b
EA		 2024 return ret;
2025 }
2026
5323fd04
EA		 2027 BUG_ON(obj_priv->active);
2028
673a394b
EA		 2029 if (obj_priv->agp_mem != NULL) {
2030 drm_unbind_agp(obj_priv->agp_mem);
2031 drm_free_agp(obj_priv->agp_mem, obj->size / PAGE_SIZE);
2032 obj_priv->agp_mem = NULL;
2033 }
2034
856fa198 2035 i915_gem_object_put_pages(obj);
a32808c0 2036 BUG_ON(obj_priv->pages_refcount);
673a394b
EA		 2037
2038 if (obj_priv->gtt_space) {
2039 atomic_dec(&dev->gtt_count);
2040 atomic_sub(obj->size, &dev->gtt_memory);
2041
2042 drm_mm_put_block(obj_priv->gtt_space);
2043 obj_priv->gtt_space = NULL;
2044 }
2045
2046 /* Remove ourselves from the LRU list if present. */
2047 if (!list_empty(&obj_priv->list))
2048 list_del_init(&obj_priv->list);
2049
963b4836
CW		 2050 if (i915_gem_object_is_purgeable(obj_priv))
2051 i915_gem_object_truncate(obj);
2052
1c5d22f7
CW		 2053 trace_i915_gem_object_unbind(obj);
2054
673a394b
EA		 2055 return 0;
2056}
2057
07f73f69
CW		 2058static struct drm_gem_object *
2059i915_gem_find_inactive_object(struct drm_device *dev, int min_size)
2060{
2061 drm_i915_private_t *dev_priv = dev->dev_private;
2062 struct drm_i915_gem_object *obj_priv;
2063 struct drm_gem_object *best = NULL;
2064 struct drm_gem_object *first = NULL;
2065
2066 /* Try to find the smallest clean object */
2067 list_for_each_entry(obj_priv, &dev_priv->mm.inactive_list, list) {
2068 struct drm_gem_object *obj = obj_priv->obj;
2069 if (obj->size >= min_size) {
963b4836
CW		 2070 if ((!obj_priv->dirty ||
2071 i915_gem_object_is_purgeable(obj_priv)) &&
07f73f69
CW		 2072 (!best || obj->size < best->size)) {
2073 best = obj;
2074 if (best->size == min_size)
2075 return best;
2076 }
2077 if (!first)
2078 first = obj;
2079 }
2080 }
2081
2082 return best ? best : first;
2083}
2084
2085static int
2086i915_gem_evict_everything(struct drm_device *dev)
2087{
2088 drm_i915_private_t *dev_priv = dev->dev_private;
2089 uint32_t seqno;
2090 int ret;
2091 bool lists_empty;
2092
07f73f69
CW		 2093 spin_lock(&dev_priv->mm.active_list_lock);
2094 lists_empty = (list_empty(&dev_priv->mm.inactive_list) &&
2095 list_empty(&dev_priv->mm.flushing_list) &&
2096 list_empty(&dev_priv->mm.active_list));
2097 spin_unlock(&dev_priv->mm.active_list_lock);
2098
9731129c 2099 if (lists_empty)
07f73f69 2100 return -ENOSPC;
07f73f69
CW		 2101
2102 /* Flush everything (on to the inactive lists) and evict */
2103 i915_gem_flush(dev, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
2104 seqno = i915_add_request(dev, NULL, I915_GEM_GPU_DOMAINS);
2105 if (seqno == 0)
2106 return -ENOMEM;
2107
2108 ret = i915_wait_request(dev, seqno);
2109 if (ret)
2110 return ret;
2111
ab5ee576 2112 ret = i915_gem_evict_from_inactive_list(dev);
07f73f69
CW		 2113 if (ret)
2114 return ret;
2115
2116 spin_lock(&dev_priv->mm.active_list_lock);
2117 lists_empty = (list_empty(&dev_priv->mm.inactive_list) &&
2118 list_empty(&dev_priv->mm.flushing_list) &&
2119 list_empty(&dev_priv->mm.active_list));
2120 spin_unlock(&dev_priv->mm.active_list_lock);
2121 BUG_ON(!lists_empty);
2122
2123 return 0;
2124}
2125
673a394b 2126static int
07f73f69 2127i915_gem_evict_something(struct drm_device *dev, int min_size)
673a394b
EA		 2128{
2129 drm_i915_private_t *dev_priv = dev->dev_private;
2130 struct drm_gem_object *obj;
07f73f69 2131 int ret;
673a394b
EA		 2132
2133 for (;;) {
07f73f69
CW		 2134 i915_gem_retire_requests(dev);
2135
673a394b
EA		 2136 /* If there's an inactive buffer available now, grab it
2137 * and be done.
2138 */
07f73f69
CW		 2139 obj = i915_gem_find_inactive_object(dev, min_size);
2140 if (obj) {
2141 struct drm_i915_gem_object *obj_priv;
2142
673a394b
EA		 2143#if WATCH_LRU
2144 DRM_INFO("%s: evicting %p\n", __func__, obj);
2145#endif
07f73f69
CW		 2146 obj_priv = obj->driver_private;
2147 BUG_ON(obj_priv->pin_count != 0);
673a394b
EA		 2148 BUG_ON(obj_priv->active);
2149
2150 /* Wait on the rendering and unbind the buffer. */
07f73f69 2151 return i915_gem_object_unbind(obj);
673a394b
EA		 2152 }
2153
2154 /* If we didn't get anything, but the ring is still processing
07f73f69
CW		 2155 * things, wait for the next to finish and hopefully leave us
2156 * a buffer to evict.
673a394b
EA		 2157 */
2158 if (!list_empty(&dev_priv->mm.request_list)) {
2159 struct drm_i915_gem_request *request;
2160
2161 request = list_first_entry(&dev_priv->mm.request_list,
2162 struct drm_i915_gem_request,
2163 list);
2164
2165 ret = i915_wait_request(dev, request->seqno);
2166 if (ret)
07f73f69 2167 return ret;
673a394b 2168
07f73f69 2169 continue;
673a394b
EA		 2170 }
2171
2172 /* If we didn't have anything on the request list but there
2173 * are buffers awaiting a flush, emit one and try again.
2174 * When we wait on it, those buffers waiting for that flush
2175 * will get moved to inactive.
2176 */
2177 if (!list_empty(&dev_priv->mm.flushing_list)) {
07f73f69 2178 struct drm_i915_gem_object *obj_priv;
07f73f69 2179
9a1e2582
CW		 2180 /* Find an object that we can immediately reuse */
2181 list_for_each_entry(obj_priv, &dev_priv->mm.flushing_list, list) {
2182 obj = obj_priv->obj;
2183 if (obj->size >= min_size)
2184 break;
673a394b 2185
9a1e2582
CW		 2186 obj = NULL;
2187 }
07f73f69 2188
9a1e2582
CW		 2189 if (obj != NULL) {
2190 uint32_t seqno;
673a394b 2191
9a1e2582
CW		 2192 i915_gem_flush(dev,
2193 obj->write_domain,
2194 obj->write_domain);
2195 seqno = i915_add_request(dev, NULL, obj->write_domain);
2196 if (seqno == 0)
2197 return -ENOMEM;
2198
2199 ret = i915_wait_request(dev, seqno);
2200 if (ret)
2201 return ret;
2202
2203 continue;
2204 }
673a394b
EA		 2205 }
2206
07f73f69
CW		 2207 /* If we didn't do any of the above, there's no single buffer
2208 * large enough to swap out for the new one, so just evict
2209 * everything and start again. (This should be rare.)
673a394b 2210 */
9731129c 2211 if (!list_empty (&dev_priv->mm.inactive_list))
ab5ee576 2212 return i915_gem_evict_from_inactive_list(dev);
9731129c 2213 else
07f73f69 2214 return i915_gem_evict_everything(dev);
ac94a962 2215 }
ac94a962
KP		 2216}
2217
6911a9b8 2218int
856fa198 2219i915_gem_object_get_pages(struct drm_gem_object *obj)
673a394b
EA		 2220{
2221 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2222 int page_count, i;
2223 struct address_space *mapping;
2224 struct inode *inode;
2225 struct page *page;
2226 int ret;
2227
856fa198 2228 if (obj_priv->pages_refcount++ != 0)
673a394b
EA		 2229 return 0;
2230
2231 /* Get the list of pages out of our struct file. They'll be pinned
2232 * at this point until we release them.
2233 */
2234 page_count = obj->size / PAGE_SIZE;
856fa198 2235 BUG_ON(obj_priv->pages != NULL);
8e7d2b2c 2236 obj_priv->pages = drm_calloc_large(page_count, sizeof(struct page *));
856fa198 2237 if (obj_priv->pages == NULL) {
856fa198 2238 obj_priv->pages_refcount--;
673a394b
EA		 2239 return -ENOMEM;
2240 }
2241
2242 inode = obj->filp->f_path.dentry->d_inode;
2243 mapping = inode->i_mapping;
2244 for (i = 0; i < page_count; i++) {
2245 page = read_mapping_page(mapping, i, NULL);
2246 if (IS_ERR(page)) {
2247 ret = PTR_ERR(page);
856fa198 2248 i915_gem_object_put_pages(obj);
673a394b
EA		 2249 return ret;
2250 }
856fa198 2251 obj_priv->pages[i] = page;
673a394b 2252 }
280b713b
EA		 2253
2254 if (obj_priv->tiling_mode != I915_TILING_NONE)
2255 i915_gem_object_do_bit_17_swizzle(obj);
2256
673a394b
EA		 2257 return 0;
2258}
2259
de151cf6
JB		 2260static void i965_write_fence_reg(struct drm_i915_fence_reg *reg)
2261{
2262 struct drm_gem_object *obj = reg->obj;
2263 struct drm_device *dev = obj->dev;
2264 drm_i915_private_t *dev_priv = dev->dev_private;
2265 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2266 int regnum = obj_priv->fence_reg;
2267 uint64_t val;
2268
2269 val = (uint64_t)((obj_priv->gtt_offset + obj->size - 4096) &
2270 0xfffff000) << 32;
2271 val |= obj_priv->gtt_offset & 0xfffff000;
2272 val |= ((obj_priv->stride / 128) - 1) << I965_FENCE_PITCH_SHIFT;
2273 if (obj_priv->tiling_mode == I915_TILING_Y)
2274 val |= 1 << I965_FENCE_TILING_Y_SHIFT;
2275 val |= I965_FENCE_REG_VALID;
2276
2277 I915_WRITE64(FENCE_REG_965_0 + (regnum * 8), val);
2278}
2279
2280static void i915_write_fence_reg(struct drm_i915_fence_reg *reg)
2281{
2282 struct drm_gem_object *obj = reg->obj;
2283 struct drm_device *dev = obj->dev;
2284 drm_i915_private_t *dev_priv = dev->dev_private;
2285 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2286 int regnum = obj_priv->fence_reg;
0f973f27 2287 int tile_width;
dc529a4f 2288 uint32_t fence_reg, val;
de151cf6
JB		 2289 uint32_t pitch_val;
2290
2291 if ((obj_priv->gtt_offset & ~I915_FENCE_START_MASK) ||
2292 (obj_priv->gtt_offset & (obj->size - 1))) {
f06da264 2293 WARN(1, "%s: object 0x%08x not 1M or size (0x%zx) aligned\n",
0f973f27 2294 __func__, obj_priv->gtt_offset, obj->size);
de151cf6
JB		 2295 return;
2296 }
2297
0f973f27
JB		 2298 if (obj_priv->tiling_mode == I915_TILING_Y &&
2299 HAS_128_BYTE_Y_TILING(dev))
2300 tile_width = 128;
de151cf6 2301 else
0f973f27
JB		 2302 tile_width = 512;
2303
2304 /* Note: pitch better be a power of two tile widths */
2305 pitch_val = obj_priv->stride / tile_width;
2306 pitch_val = ffs(pitch_val) - 1;
de151cf6
JB		 2307
2308 val = obj_priv->gtt_offset;
2309 if (obj_priv->tiling_mode == I915_TILING_Y)
2310 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
2311 val |= I915_FENCE_SIZE_BITS(obj->size);
2312 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
2313 val |= I830_FENCE_REG_VALID;
2314
dc529a4f
EA		 2315 if (regnum < 8)
2316 fence_reg = FENCE_REG_830_0 + (regnum * 4);
2317 else
2318 fence_reg = FENCE_REG_945_8 + ((regnum - 8) * 4);
2319 I915_WRITE(fence_reg, val);
de151cf6
JB		 2320}
2321
2322static void i830_write_fence_reg(struct drm_i915_fence_reg *reg)
2323{
2324 struct drm_gem_object *obj = reg->obj;
2325 struct drm_device *dev = obj->dev;
2326 drm_i915_private_t *dev_priv = dev->dev_private;
2327 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2328 int regnum = obj_priv->fence_reg;
2329 uint32_t val;
2330 uint32_t pitch_val;
8d7773a3 2331 uint32_t fence_size_bits;
de151cf6 2332
8d7773a3 2333 if ((obj_priv->gtt_offset & ~I830_FENCE_START_MASK) ||
de151cf6 2334 (obj_priv->gtt_offset & (obj->size - 1))) {
8d7773a3 2335 WARN(1, "%s: object 0x%08x not 512K or size aligned\n",
0f973f27 2336 __func__, obj_priv->gtt_offset);
de151cf6
JB		 2337 return;
2338 }
2339
e76a16de
EA		 2340 pitch_val = obj_priv->stride / 128;
2341 pitch_val = ffs(pitch_val) - 1;
2342 WARN_ON(pitch_val > I830_FENCE_MAX_PITCH_VAL);
2343
de151cf6
JB		 2344 val = obj_priv->gtt_offset;
2345 if (obj_priv->tiling_mode == I915_TILING_Y)
2346 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
8d7773a3
DV		 2347 fence_size_bits = I830_FENCE_SIZE_BITS(obj->size);
2348 WARN_ON(fence_size_bits & ~0x00000f00);
2349 val |= fence_size_bits;
de151cf6
JB		 2350 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
2351 val |= I830_FENCE_REG_VALID;
2352
2353 I915_WRITE(FENCE_REG_830_0 + (regnum * 4), val);
de151cf6
JB		 2354}
2355
2356/**
2357 * i915_gem_object_get_fence_reg - set up a fence reg for an object
2358 * @obj: object to map through a fence reg
2359 *
2360 * When mapping objects through the GTT, userspace wants to be able to write
2361 * to them without having to worry about swizzling if the object is tiled.
2362 *
2363 * This function walks the fence regs looking for a free one for @obj,
2364 * stealing one if it can't find any.
2365 *
2366 * It then sets up the reg based on the object's properties: address, pitch
2367 * and tiling format.
2368 */
8c4b8c3f
CW		 2369int
2370i915_gem_object_get_fence_reg(struct drm_gem_object *obj)
de151cf6
JB		 2371{
2372 struct drm_device *dev = obj->dev;
79e53945 2373 struct drm_i915_private *dev_priv = dev->dev_private;
de151cf6
JB		 2374 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2375 struct drm_i915_fence_reg *reg = NULL;
fc7170ba
CW		 2376 struct drm_i915_gem_object *old_obj_priv = NULL;
2377 int i, ret, avail;
de151cf6 2378
a09ba7fa
EA		 2379 /* Just update our place in the LRU if our fence is getting used. */
2380 if (obj_priv->fence_reg != I915_FENCE_REG_NONE) {
2381 list_move_tail(&obj_priv->fence_list, &dev_priv->mm.fence_list);
2382 return 0;
2383 }
2384
de151cf6
JB		 2385 switch (obj_priv->tiling_mode) {
2386 case I915_TILING_NONE:
2387 WARN(1, "allocating a fence for non-tiled object?\n");
2388 break;
2389 case I915_TILING_X:
0f973f27
JB		 2390 if (!obj_priv->stride)
2391 return -EINVAL;
2392 WARN((obj_priv->stride & (512 - 1)),
2393 "object 0x%08x is X tiled but has non-512B pitch\n",
2394 obj_priv->gtt_offset);
de151cf6
JB		 2395 break;
2396 case I915_TILING_Y:
0f973f27
JB		 2397 if (!obj_priv->stride)
2398 return -EINVAL;
2399 WARN((obj_priv->stride & (128 - 1)),
2400 "object 0x%08x is Y tiled but has non-128B pitch\n",
2401 obj_priv->gtt_offset);
de151cf6
JB		 2402 break;
2403 }
2404
2405 /* First try to find a free reg */
fc7170ba 2406 avail = 0;
de151cf6
JB		 2407 for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) {
2408 reg = &dev_priv->fence_regs[i];
2409 if (!reg->obj)
2410 break;
fc7170ba
CW		 2411
2412 old_obj_priv = reg->obj->driver_private;
2413 if (!old_obj_priv->pin_count)
2414 avail++;
de151cf6
JB		 2415 }
2416
2417 /* None available, try to steal one or wait for a user to finish */
2418 if (i == dev_priv->num_fence_regs) {
a09ba7fa 2419 struct drm_gem_object *old_obj = NULL;
de151cf6 2420
fc7170ba 2421 if (avail == 0)
2939e1f5 2422 return -ENOSPC;
fc7170ba 2423
a09ba7fa
EA		 2424 list_for_each_entry(old_obj_priv, &dev_priv->mm.fence_list,
2425 fence_list) {
2426 old_obj = old_obj_priv->obj;
d7619c4b
CW		 2427
2428 if (old_obj_priv->pin_count)
2429 continue;
2430
a09ba7fa
EA		 2431 /* Take a reference, as otherwise the wait_rendering
2432 * below may cause the object to get freed out from
2433 * under us.
2434 */
2435 drm_gem_object_reference(old_obj);
2436
d7619c4b
CW		 2437 /* i915 uses fences for GPU access to tiled buffers */
2438 if (IS_I965G(dev) || !old_obj_priv->active)
de151cf6 2439 break;
d7619c4b 2440
a09ba7fa
EA		 2441 /* This brings the object to the head of the LRU if it
2442 * had been written to. The only way this should
2443 * result in us waiting longer than the expected
2444 * optimal amount of time is if there was a
2445 * fence-using buffer later that was read-only.
2446 */
2447 i915_gem_object_flush_gpu_write_domain(old_obj);
2448 ret = i915_gem_object_wait_rendering(old_obj);
58c2fb64
CW		 2449 if (ret != 0) {
2450 drm_gem_object_unreference(old_obj);
d7619c4b 2451 return ret;
de151cf6 2452 }
d7619c4b 2453
a09ba7fa 2454 break;
de151cf6
JB		 2455 }
2456
2457 /*
2458 * Zap this virtual mapping so we can set up a fence again
2459 * for this object next time we need it.
2460 */
58c2fb64
CW		 2461 i915_gem_release_mmap(old_obj);
2462
a09ba7fa 2463 i = old_obj_priv->fence_reg;
58c2fb64
CW		 2464 reg = &dev_priv->fence_regs[i];
2465
de151cf6 2466 old_obj_priv->fence_reg = I915_FENCE_REG_NONE;
a09ba7fa 2467 list_del_init(&old_obj_priv->fence_list);
58c2fb64 2468
a09ba7fa 2469 drm_gem_object_unreference(old_obj);
de151cf6
JB		 2470 }
2471
2472 obj_priv->fence_reg = i;
a09ba7fa
EA		 2473 list_add_tail(&obj_priv->fence_list, &dev_priv->mm.fence_list);
2474
de151cf6
JB		 2475 reg->obj = obj;
2476
2477 if (IS_I965G(dev))
2478 i965_write_fence_reg(reg);
2479 else if (IS_I9XX(dev))
2480 i915_write_fence_reg(reg);
2481 else
2482 i830_write_fence_reg(reg);
d9ddcb96 2483
1c5d22f7
CW		 2484 trace_i915_gem_object_get_fence(obj, i, obj_priv->tiling_mode);
2485
d9ddcb96 2486 return 0;
de151cf6
JB		 2487}
2488
2489/**
2490 * i915_gem_clear_fence_reg - clear out fence register info
2491 * @obj: object to clear
2492 *
2493 * Zeroes out the fence register itself and clears out the associated
2494 * data structures in dev_priv and obj_priv.
2495 */
2496static void
2497i915_gem_clear_fence_reg(struct drm_gem_object *obj)
2498{
2499 struct drm_device *dev = obj->dev;
79e53945 2500 drm_i915_private_t *dev_priv = dev->dev_private;
de151cf6
JB		 2501 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2502
2503 if (IS_I965G(dev))
2504 I915_WRITE64(FENCE_REG_965_0 + (obj_priv->fence_reg * 8), 0);
dc529a4f
EA		 2505 else {
2506 uint32_t fence_reg;
2507
2508 if (obj_priv->fence_reg < 8)
2509 fence_reg = FENCE_REG_830_0 + obj_priv->fence_reg * 4;
2510 else
2511 fence_reg = FENCE_REG_945_8 + (obj_priv->fence_reg -
2512 8) * 4;
2513
2514 I915_WRITE(fence_reg, 0);
2515 }
de151cf6
JB		 2516
2517 dev_priv->fence_regs[obj_priv->fence_reg].obj = NULL;
2518 obj_priv->fence_reg = I915_FENCE_REG_NONE;
a09ba7fa 2519 list_del_init(&obj_priv->fence_list);
de151cf6
JB		 2520}
2521
52dc7d32
CW		 2522/**
2523 * i915_gem_object_put_fence_reg - waits on outstanding fenced access
2524 * to the buffer to finish, and then resets the fence register.
2525 * @obj: tiled object holding a fence register.
2526 *
2527 * Zeroes out the fence register itself and clears out the associated
2528 * data structures in dev_priv and obj_priv.
2529 */
2530int
2531i915_gem_object_put_fence_reg(struct drm_gem_object *obj)
2532{
2533 struct drm_device *dev = obj->dev;
2534 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2535
2536 if (obj_priv->fence_reg == I915_FENCE_REG_NONE)
2537 return 0;
2538
2539 /* On the i915, GPU access to tiled buffers is via a fence,
2540 * therefore we must wait for any outstanding access to complete
2541 * before clearing the fence.
2542 */
2543 if (!IS_I965G(dev)) {
2544 int ret;
2545
2546 i915_gem_object_flush_gpu_write_domain(obj);
2547 i915_gem_object_flush_gtt_write_domain(obj);
2548 ret = i915_gem_object_wait_rendering(obj);
2549 if (ret != 0)
2550 return ret;
2551 }
2552
2553 i915_gem_clear_fence_reg (obj);
2554
2555 return 0;
2556}
2557
673a394b
EA		 2558/**
2559 * Finds free space in the GTT aperture and binds the object there.
2560 */
2561static int
2562i915_gem_object_bind_to_gtt(struct drm_gem_object *obj, unsigned alignment)
2563{
2564 struct drm_device *dev = obj->dev;
2565 drm_i915_private_t *dev_priv = dev->dev_private;
2566 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2567 struct drm_mm_node *free_space;
07f73f69
CW		 2568 bool retry_alloc = false;
2569 int ret;
673a394b 2570
9bb2d6f9
EA		 2571 if (dev_priv->mm.suspended)
2572 return -EBUSY;
3ef94daa 2573
bb6baf76 2574 if (obj_priv->madv != I915_MADV_WILLNEED) {
3ef94daa
CW		 2575 DRM_ERROR("Attempting to bind a purgeable object\n");
2576 return -EINVAL;
2577 }
2578
673a394b 2579 if (alignment == 0)
0f973f27 2580 alignment = i915_gem_get_gtt_alignment(obj);
8d7773a3 2581 if (alignment & (i915_gem_get_gtt_alignment(obj) - 1)) {
673a394b
EA		 2582 DRM_ERROR("Invalid object alignment requested %u\n", alignment);
2583 return -EINVAL;
2584 }
2585
2586 search_free:
2587 free_space = drm_mm_search_free(&dev_priv->mm.gtt_space,
2588 obj->size, alignment, 0);
2589 if (free_space != NULL) {
2590 obj_priv->gtt_space = drm_mm_get_block(free_space, obj->size,
2591 alignment);
2592 if (obj_priv->gtt_space != NULL) {
2593 obj_priv->gtt_space->private = obj;
2594 obj_priv->gtt_offset = obj_priv->gtt_space->start;
2595 }
2596 }
2597 if (obj_priv->gtt_space == NULL) {
2598 /* If the gtt is empty and we're still having trouble
2599 * fitting our object in, we're out of memory.
2600 */
2601#if WATCH_LRU
2602 DRM_INFO("%s: GTT full, evicting something\n", __func__);
2603#endif
07f73f69 2604 ret = i915_gem_evict_something(dev, obj->size);
9731129c 2605 if (ret)
673a394b 2606 return ret;
9731129c 2607
673a394b
EA		 2608 goto search_free;
2609 }
2610
2611#if WATCH_BUF
cfd43c02 2612 DRM_INFO("Binding object of size %zd at 0x%08x\n",
673a394b
EA		 2613 obj->size, obj_priv->gtt_offset);
2614#endif
07f73f69
CW		 2615 if (retry_alloc) {
2616 i915_gem_object_set_page_gfp_mask (obj,
2617 i915_gem_object_get_page_gfp_mask (obj) & ~__GFP_NORETRY);
2618 }
856fa198 2619 ret = i915_gem_object_get_pages(obj);
07f73f69
CW		 2620 if (retry_alloc) {
2621 i915_gem_object_set_page_gfp_mask (obj,
2622 i915_gem_object_get_page_gfp_mask (obj) | __GFP_NORETRY);
2623 }
673a394b
EA		 2624 if (ret) {
2625 drm_mm_put_block(obj_priv->gtt_space);
2626 obj_priv->gtt_space = NULL;
07f73f69
CW		 2627
2628 if (ret == -ENOMEM) {
2629 /* first try to clear up some space from the GTT */
2630 ret = i915_gem_evict_something(dev, obj->size);
2631 if (ret) {
07f73f69
CW		 2632 /* now try to shrink everyone else */
2633 if (! retry_alloc) {
2634 retry_alloc = true;
2635 goto search_free;
2636 }
2637
2638 return ret;
2639 }
2640
2641 goto search_free;
2642 }
2643
673a394b
EA		 2644 return ret;
2645 }
2646
673a394b
EA		 2647 /* Create an AGP memory structure pointing at our pages, and bind it
2648 * into the GTT.
2649 */
2650 obj_priv->agp_mem = drm_agp_bind_pages(dev,
856fa198 2651 obj_priv->pages,
07f73f69 2652 obj->size >> PAGE_SHIFT,
ba1eb1d8
KP		 2653 obj_priv->gtt_offset,
2654 obj_priv->agp_type);
673a394b 2655 if (obj_priv->agp_mem == NULL) {
856fa198 2656 i915_gem_object_put_pages(obj);
673a394b
EA		 2657 drm_mm_put_block(obj_priv->gtt_space);
2658 obj_priv->gtt_space = NULL;
07f73f69
CW		 2659
2660 ret = i915_gem_evict_something(dev, obj->size);
9731129c 2661 if (ret)
07f73f69 2662 return ret;
07f73f69
CW		 2663
2664 goto search_free;
673a394b
EA		 2665 }
2666 atomic_inc(&dev->gtt_count);
2667 atomic_add(obj->size, &dev->gtt_memory);
2668
2669 /* Assert that the object is not currently in any GPU domain. As it
2670 * wasn't in the GTT, there shouldn't be any way it could have been in
2671 * a GPU cache
2672 */
21d509e3
CW		 2673 BUG_ON(obj->read_domains & I915_GEM_GPU_DOMAINS);
2674 BUG_ON(obj->write_domain & I915_GEM_GPU_DOMAINS);
673a394b 2675
1c5d22f7
CW		 2676 trace_i915_gem_object_bind(obj, obj_priv->gtt_offset);
2677
673a394b
EA		 2678 return 0;
2679}
2680
2681void
2682i915_gem_clflush_object(struct drm_gem_object *obj)
2683{
2684 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2685
2686 /* If we don't have a page list set up, then we're not pinned
2687 * to GPU, and we can ignore the cache flush because it'll happen
2688 * again at bind time.
2689 */
856fa198 2690 if (obj_priv->pages == NULL)
673a394b
EA		 2691 return;
2692
1c5d22f7
CW		 2693 trace_i915_gem_object_clflush(obj);
2694
856fa198 2695 drm_clflush_pages(obj_priv->pages, obj->size / PAGE_SIZE);
673a394b
EA		 2696}
2697
e47c68e9
EA		 2698/** Flushes any GPU write domain for the object if it's dirty. */
2699static void
2700i915_gem_object_flush_gpu_write_domain(struct drm_gem_object *obj)
2701{
2702 struct drm_device *dev = obj->dev;
2703 uint32_t seqno;
1c5d22f7 2704 uint32_t old_write_domain;
e47c68e9
EA		 2705
2706 if ((obj->write_domain & I915_GEM_GPU_DOMAINS) == 0)
2707 return;
2708
2709 /* Queue the GPU write cache flushing we need. */
1c5d22f7 2710 old_write_domain = obj->write_domain;
e47c68e9 2711 i915_gem_flush(dev, 0, obj->write_domain);
b962442e 2712 seqno = i915_add_request(dev, NULL, obj->write_domain);
e47c68e9
EA		 2713 obj->write_domain = 0;
2714 i915_gem_object_move_to_active(obj, seqno);
1c5d22f7
CW		 2715
2716 trace_i915_gem_object_change_domain(obj,
2717 obj->read_domains,
2718 old_write_domain);
e47c68e9
EA		 2719}
2720
2721/** Flushes the GTT write domain for the object if it's dirty. */
2722static void
2723i915_gem_object_flush_gtt_write_domain(struct drm_gem_object *obj)
2724{
1c5d22f7
CW		 2725 uint32_t old_write_domain;
2726
e47c68e9
EA		 2727 if (obj->write_domain != I915_GEM_DOMAIN_GTT)
2728 return;
2729
2730 /* No actual flushing is required for the GTT write domain. Writes
2731 * to it immediately go to main memory as far as we know, so there's
2732 * no chipset flush. It also doesn't land in render cache.
2733 */
1c5d22f7 2734 old_write_domain = obj->write_domain;
e47c68e9 2735 obj->write_domain = 0;
1c5d22f7
CW		 2736
2737 trace_i915_gem_object_change_domain(obj,
2738 obj->read_domains,
2739 old_write_domain);
e47c68e9
EA		 2740}
2741
2742/** Flushes the CPU write domain for the object if it's dirty. */
2743static void
2744i915_gem_object_flush_cpu_write_domain(struct drm_gem_object *obj)
2745{
2746 struct drm_device *dev = obj->dev;
1c5d22f7 2747 uint32_t old_write_domain;
e47c68e9
EA		 2748
2749 if (obj->write_domain != I915_GEM_DOMAIN_CPU)
2750 return;
2751
2752 i915_gem_clflush_object(obj);
2753 drm_agp_chipset_flush(dev);
1c5d22f7 2754 old_write_domain = obj->write_domain;
e47c68e9 2755 obj->write_domain = 0;
1c5d22f7
CW		 2756
2757 trace_i915_gem_object_change_domain(obj,
2758 obj->read_domains,
2759 old_write_domain);
e47c68e9
EA		 2760}
2761
2ef7eeaa
EA		 2762/**
2763 * Moves a single object to the GTT read, and possibly write domain.
2764 *
2765 * This function returns when the move is complete, including waiting on
2766 * flushes to occur.
2767 */
79e53945 2768int
2ef7eeaa
EA		 2769i915_gem_object_set_to_gtt_domain(struct drm_gem_object *obj, int write)
2770{
2ef7eeaa 2771 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1c5d22f7 2772 uint32_t old_write_domain, old_read_domains;
e47c68e9 2773 int ret;
2ef7eeaa 2774
02354392
EA		 2775 /* Not valid to be called on unbound objects. */
2776 if (obj_priv->gtt_space == NULL)
2777 return -EINVAL;
2778
e47c68e9
EA		 2779 i915_gem_object_flush_gpu_write_domain(obj);
2780 /* Wait on any GPU rendering and flushing to occur. */
2781 ret = i915_gem_object_wait_rendering(obj);
2782 if (ret != 0)
2783 return ret;
2784
1c5d22f7
CW		 2785 old_write_domain = obj->write_domain;
2786 old_read_domains = obj->read_domains;
2787
e47c68e9
EA		 2788 /* If we're writing through the GTT domain, then CPU and GPU caches
2789 * will need to be invalidated at next use.
2ef7eeaa 2790 */
e47c68e9
EA		 2791 if (write)
2792 obj->read_domains &= I915_GEM_DOMAIN_GTT;
2ef7eeaa 2793
e47c68e9 2794 i915_gem_object_flush_cpu_write_domain(obj);
2ef7eeaa 2795
e47c68e9
EA		 2796 /* It should now be out of any other write domains, and we can update
2797 * the domain values for our changes.
2798 */
2799 BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_GTT) != 0);
2800 obj->read_domains |= I915_GEM_DOMAIN_GTT;
2801 if (write) {
2802 obj->write_domain = I915_GEM_DOMAIN_GTT;
2803 obj_priv->dirty = 1;
2ef7eeaa
EA		 2804 }
2805
1c5d22f7
CW		 2806 trace_i915_gem_object_change_domain(obj,
2807 old_read_domains,
2808 old_write_domain);
2809
e47c68e9
EA		 2810 return 0;
2811}
2812
2813/**
2814 * Moves a single object to the CPU read, and possibly write domain.
2815 *
2816 * This function returns when the move is complete, including waiting on
2817 * flushes to occur.
2818 */
2819static int
2820i915_gem_object_set_to_cpu_domain(struct drm_gem_object *obj, int write)
2821{
1c5d22f7 2822 uint32_t old_write_domain, old_read_domains;
e47c68e9
EA		 2823 int ret;
2824
2825 i915_gem_object_flush_gpu_write_domain(obj);
2ef7eeaa 2826 /* Wait on any GPU rendering and flushing to occur. */
e47c68e9
EA		 2827 ret = i915_gem_object_wait_rendering(obj);
2828 if (ret != 0)
2829 return ret;
2ef7eeaa 2830
e47c68e9 2831 i915_gem_object_flush_gtt_write_domain(obj);
2ef7eeaa 2832
e47c68e9
EA		 2833 /* If we have a partially-valid cache of the object in the CPU,
2834 * finish invalidating it and free the per-page flags.
2ef7eeaa 2835 */
e47c68e9 2836 i915_gem_object_set_to_full_cpu_read_domain(obj);
2ef7eeaa 2837
1c5d22f7
CW		 2838 old_write_domain = obj->write_domain;
2839 old_read_domains = obj->read_domains;
2840
e47c68e9
EA		 2841 /* Flush the CPU cache if it's still invalid. */
2842 if ((obj->read_domains & I915_GEM_DOMAIN_CPU) == 0) {
2ef7eeaa 2843 i915_gem_clflush_object(obj);
2ef7eeaa 2844
e47c68e9 2845 obj->read_domains |= I915_GEM_DOMAIN_CPU;
2ef7eeaa
EA		 2846 }
2847
2848 /* It should now be out of any other write domains, and we can update
2849 * the domain values for our changes.
2850 */
e47c68e9
EA		 2851 BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
2852
2853 /* If we're writing through the CPU, then the GPU read domains will
2854 * need to be invalidated at next use.
2855 */
2856 if (write) {
2857 obj->read_domains &= I915_GEM_DOMAIN_CPU;
2858 obj->write_domain = I915_GEM_DOMAIN_CPU;
2859 }
2ef7eeaa 2860
1c5d22f7
CW		 2861 trace_i915_gem_object_change_domain(obj,
2862 old_read_domains,
2863 old_write_domain);
2864
2ef7eeaa
EA		 2865 return 0;
2866}
2867
673a394b
EA		 2868/*
2869 * Set the next domain for the specified object. This
2870 * may not actually perform the necessary flushing/invaliding though,
2871 * as that may want to be batched with other set_domain operations
2872 *
2873 * This is (we hope) the only really tricky part of gem. The goal
2874 * is fairly simple -- track which caches hold bits of the object
2875 * and make sure they remain coherent. A few concrete examples may
2876 * help to explain how it works. For shorthand, we use the notation
2877 * (read_domains, write_domain), e.g. (CPU, CPU) to indicate the
2878 * a pair of read and write domain masks.
2879 *
2880 * Case 1: the batch buffer
2881 *
2882 * 1. Allocated
2883 * 2. Written by CPU
2884 * 3. Mapped to GTT
2885 * 4. Read by GPU
2886 * 5. Unmapped from GTT
2887 * 6. Freed
2888 *
2889 * Let's take these a step at a time
2890 *
2891 * 1. Allocated
2892 * Pages allocated from the kernel may still have
2893 * cache contents, so we set them to (CPU, CPU) always.
2894 * 2. Written by CPU (using pwrite)
2895 * The pwrite function calls set_domain (CPU, CPU) and
2896 * this function does nothing (as nothing changes)
2897 * 3. Mapped by GTT
2898 * This function asserts that the object is not
2899 * currently in any GPU-based read or write domains
2900 * 4. Read by GPU
2901 * i915_gem_execbuffer calls set_domain (COMMAND, 0).
2902 * As write_domain is zero, this function adds in the
2903 * current read domains (CPU+COMMAND, 0).
2904 * flush_domains is set to CPU.
2905 * invalidate_domains is set to COMMAND
2906 * clflush is run to get data out of the CPU caches
2907 * then i915_dev_set_domain calls i915_gem_flush to
2908 * emit an MI_FLUSH and drm_agp_chipset_flush
2909 * 5. Unmapped from GTT
2910 * i915_gem_object_unbind calls set_domain (CPU, CPU)
2911 * flush_domains and invalidate_domains end up both zero
2912 * so no flushing/invalidating happens
2913 * 6. Freed
2914 * yay, done
2915 *
2916 * Case 2: The shared render buffer
2917 *
2918 * 1. Allocated
2919 * 2. Mapped to GTT
2920 * 3. Read/written by GPU
2921 * 4. set_domain to (CPU,CPU)
2922 * 5. Read/written by CPU
2923 * 6. Read/written by GPU
2924 *
2925 * 1. Allocated
2926 * Same as last example, (CPU, CPU)
2927 * 2. Mapped to GTT
2928 * Nothing changes (assertions find that it is not in the GPU)
2929 * 3. Read/written by GPU
2930 * execbuffer calls set_domain (RENDER, RENDER)
2931 * flush_domains gets CPU
2932 * invalidate_domains gets GPU
2933 * clflush (obj)
2934 * MI_FLUSH and drm_agp_chipset_flush
2935 * 4. set_domain (CPU, CPU)
2936 * flush_domains gets GPU
2937 * invalidate_domains gets CPU
2938 * wait_rendering (obj) to make sure all drawing is complete.
2939 * This will include an MI_FLUSH to get the data from GPU
2940 * to memory
2941 * clflush (obj) to invalidate the CPU cache
2942 * Another MI_FLUSH in i915_gem_flush (eliminate this somehow?)
2943 * 5. Read/written by CPU
2944 * cache lines are loaded and dirtied
2945 * 6. Read written by GPU
2946 * Same as last GPU access
2947 *
2948 * Case 3: The constant buffer
2949 *
2950 * 1. Allocated
2951 * 2. Written by CPU
2952 * 3. Read by GPU
2953 * 4. Updated (written) by CPU again
2954 * 5. Read by GPU
2955 *
2956 * 1. Allocated
2957 * (CPU, CPU)
2958 * 2. Written by CPU
2959 * (CPU, CPU)
2960 * 3. Read by GPU
2961 * (CPU+RENDER, 0)
2962 * flush_domains = CPU
2963 * invalidate_domains = RENDER
2964 * clflush (obj)
2965 * MI_FLUSH
2966 * drm_agp_chipset_flush
2967 * 4. Updated (written) by CPU again
2968 * (CPU, CPU)
2969 * flush_domains = 0 (no previous write domain)
2970 * invalidate_domains = 0 (no new read domains)
2971 * 5. Read by GPU
2972 * (CPU+RENDER, 0)
2973 * flush_domains = CPU
2974 * invalidate_domains = RENDER
2975 * clflush (obj)
2976 * MI_FLUSH
2977 * drm_agp_chipset_flush
2978 */
c0d90829 2979static void
8b0e378a 2980i915_gem_object_set_to_gpu_domain(struct drm_gem_object *obj)
673a394b
EA		 2981{
2982 struct drm_device *dev = obj->dev;
2983 struct drm_i915_gem_object *obj_priv = obj->driver_private;
2984 uint32_t invalidate_domains = 0;
2985 uint32_t flush_domains = 0;
1c5d22f7 2986 uint32_t old_read_domains;
e47c68e9 2987
8b0e378a
EA		 2988 BUG_ON(obj->pending_read_domains & I915_GEM_DOMAIN_CPU);
2989 BUG_ON(obj->pending_write_domain == I915_GEM_DOMAIN_CPU);
673a394b 2990
652c393a
JB		 2991 intel_mark_busy(dev, obj);
2992
673a394b
EA		 2993#if WATCH_BUF
2994 DRM_INFO("%s: object %p read %08x -> %08x write %08x -> %08x\n",
2995 __func__, obj,
8b0e378a
EA		 2996 obj->read_domains, obj->pending_read_domains,
2997 obj->write_domain, obj->pending_write_domain);
673a394b
EA		 2998#endif
2999 /*
3000 * If the object isn't moving to a new write domain,
3001 * let the object stay in multiple read domains
3002 */
8b0e378a
EA		 3003 if (obj->pending_write_domain == 0)
3004 obj->pending_read_domains |= obj->read_domains;
673a394b
EA		 3005 else
3006 obj_priv->dirty = 1;
3007
3008 /*
3009 * Flush the current write domain if
3010 * the new read domains don't match. Invalidate
3011 * any read domains which differ from the old
3012 * write domain
3013 */
8b0e378a
EA		 3014 if (obj->write_domain &&
3015 obj->write_domain != obj->pending_read_domains) {
673a394b 3016 flush_domains |= obj->write_domain;
8b0e378a
EA		 3017 invalidate_domains |=
3018 obj->pending_read_domains & ~obj->write_domain;
673a394b
EA		 3019 }
3020 /*
3021 * Invalidate any read caches which may have
3022 * stale data. That is, any new read domains.
3023 */
8b0e378a 3024 invalidate_domains |= obj->pending_read_domains & ~obj->read_domains;
673a394b
EA		 3025 if ((flush_domains | invalidate_domains) & I915_GEM_DOMAIN_CPU) {
3026#if WATCH_BUF
3027 DRM_INFO("%s: CPU domain flush %08x invalidate %08x\n",
3028 __func__, flush_domains, invalidate_domains);
3029#endif
673a394b
EA		 3030 i915_gem_clflush_object(obj);
3031 }
3032
1c5d22f7
CW		 3033 old_read_domains = obj->read_domains;
3034
efbeed96
EA		 3035 /* The actual obj->write_domain will be updated with
3036 * pending_write_domain after we emit the accumulated flush for all
3037 * of our domain changes in execbuffers (which clears objects'
3038 * write_domains). So if we have a current write domain that we
3039 * aren't changing, set pending_write_domain to that.
3040 */
3041 if (flush_domains == 0 && obj->pending_write_domain == 0)
3042 obj->pending_write_domain = obj->write_domain;
8b0e378a 3043 obj->read_domains = obj->pending_read_domains;
673a394b
EA		 3044
3045 dev->invalidate_domains |= invalidate_domains;
3046 dev->flush_domains |= flush_domains;
3047#if WATCH_BUF
3048 DRM_INFO("%s: read %08x write %08x invalidate %08x flush %08x\n",
3049 __func__,
3050 obj->read_domains, obj->write_domain,
3051 dev->invalidate_domains, dev->flush_domains);
3052#endif
1c5d22f7
CW		 3053
3054 trace_i915_gem_object_change_domain(obj,
3055 old_read_domains,
3056 obj->write_domain);
673a394b
EA		 3057}
3058
3059/**
e47c68e9 3060 * Moves the object from a partially CPU read to a full one.
673a394b 3061 *
e47c68e9
EA		 3062 * Note that this only resolves i915_gem_object_set_cpu_read_domain_range(),
3063 * and doesn't handle transitioning from !(read_domains & I915_GEM_DOMAIN_CPU).
673a394b 3064 */
e47c68e9
EA		 3065static void
3066i915_gem_object_set_to_full_cpu_read_domain(struct drm_gem_object *obj)
673a394b
EA		 3067{
3068 struct drm_i915_gem_object *obj_priv = obj->driver_private;
673a394b 3069
e47c68e9
EA		 3070 if (!obj_priv->page_cpu_valid)
3071 return;
3072
3073 /* If we're partially in the CPU read domain, finish moving it in.
3074 */
3075 if (obj->read_domains & I915_GEM_DOMAIN_CPU) {
3076 int i;
3077
3078 for (i = 0; i <= (obj->size - 1) / PAGE_SIZE; i++) {
3079 if (obj_priv->page_cpu_valid[i])
3080 continue;
856fa198 3081 drm_clflush_pages(obj_priv->pages + i, 1);
e47c68e9 3082 }
e47c68e9
EA		 3083 }
3084
3085 /* Free the page_cpu_valid mappings which are now stale, whether
3086 * or not we've got I915_GEM_DOMAIN_CPU.
3087 */
9a298b2a 3088 kfree(obj_priv->page_cpu_valid);
e47c68e9
EA		 3089 obj_priv->page_cpu_valid = NULL;
3090}
3091
3092/**
3093 * Set the CPU read domain on a range of the object.
3094 *
3095 * The object ends up with I915_GEM_DOMAIN_CPU in its read flags although it's
3096 * not entirely valid. The page_cpu_valid member of the object flags which
3097 * pages have been flushed, and will be respected by
3098 * i915_gem_object_set_to_cpu_domain() if it's called on to get a valid mapping
3099 * of the whole object.
3100 *
3101 * This function returns when the move is complete, including waiting on
3102 * flushes to occur.
3103 */
3104static int
3105i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object *obj,
3106 uint64_t offset, uint64_t size)
3107{
3108 struct drm_i915_gem_object *obj_priv = obj->driver_private;
1c5d22f7 3109 uint32_t old_read_domains;
e47c68e9 3110 int i, ret;
673a394b 3111
e47c68e9
EA		 3112 if (offset == 0 && size == obj->size)
3113 return i915_gem_object_set_to_cpu_domain(obj, 0);
673a394b 3114
e47c68e9
EA		 3115 i915_gem_object_flush_gpu_write_domain(obj);
3116 /* Wait on any GPU rendering and flushing to occur. */
6a47baa6 3117 ret = i915_gem_object_wait_rendering(obj);
e47c68e9 3118 if (ret != 0)
6a47baa6 3119 return ret;
e47c68e9
EA		 3120 i915_gem_object_flush_gtt_write_domain(obj);
3121
3122 /* If we're already fully in the CPU read domain, we're done. */
3123 if (obj_priv->page_cpu_valid == NULL &&
3124 (obj->read_domains & I915_GEM_DOMAIN_CPU) != 0)
3125 return 0;
673a394b 3126
e47c68e9
EA		 3127 /* Otherwise, create/clear the per-page CPU read domain flag if we're
3128 * newly adding I915_GEM_DOMAIN_CPU
3129 */
673a394b 3130 if (obj_priv->page_cpu_valid == NULL) {
9a298b2a
EA		 3131 obj_priv->page_cpu_valid = kzalloc(obj->size / PAGE_SIZE,
3132 GFP_KERNEL);
e47c68e9
EA		 3133 if (obj_priv->page_cpu_valid == NULL)
3134 return -ENOMEM;
3135 } else if ((obj->read_domains & I915_GEM_DOMAIN_CPU) == 0)
3136 memset(obj_priv->page_cpu_valid, 0, obj->size / PAGE_SIZE);
673a394b
EA		 3137
3138 /* Flush the cache on any pages that are still invalid from the CPU's
3139 * perspective.
3140 */
e47c68e9
EA		 3141 for (i = offset / PAGE_SIZE; i <= (offset + size - 1) / PAGE_SIZE;
3142 i++) {
673a394b
EA		 3143 if (obj_priv->page_cpu_valid[i])
3144 continue;
3145
856fa198 3146 drm_clflush_pages(obj_priv->pages + i, 1);
673a394b
EA		 3147
3148 obj_priv->page_cpu_valid[i] = 1;
3149 }
3150
e47c68e9
EA		 3151 /* It should now be out of any other write domains, and we can update
3152 * the domain values for our changes.
3153 */
3154 BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
3155
1c5d22f7 3156 old_read_domains = obj->read_domains;
e47c68e9
EA		 3157 obj->read_domains |= I915_GEM_DOMAIN_CPU;
3158
1c5d22f7
CW		 3159 trace_i915_gem_object_change_domain(obj,
3160 old_read_domains,
3161 obj->write_domain);
3162
673a394b
EA		 3163 return 0;
3164}
3165
673a394b
EA		 3166/**
3167 * Pin an object to the GTT and evaluate the relocations landing in it.
3168 */
3169static int
3170i915_gem_object_pin_and_relocate(struct drm_gem_object *obj,
3171 struct drm_file *file_priv,
40a5f0de
EA		 3172 struct drm_i915_gem_exec_object *entry,
3173 struct drm_i915_gem_relocation_entry *relocs)
673a394b
EA		 3174{
3175 struct drm_device *dev = obj->dev;
0839ccb8 3176 drm_i915_private_t *dev_priv = dev->dev_private;
673a394b
EA		 3177 struct drm_i915_gem_object *obj_priv = obj->driver_private;
3178 int i, ret;
0839ccb8 3179 void __iomem *reloc_page;
673a394b
EA		 3180
3181 /* Choose the GTT offset for our buffer and put it there. */
3182 ret = i915_gem_object_pin(obj, (uint32_t) entry->alignment);
3183 if (ret)
3184 return ret;
3185
3186 entry->offset = obj_priv->gtt_offset;
3187
673a394b
EA		 3188 /* Apply the relocations, using the GTT aperture to avoid cache
3189 * flushing requirements.
3190 */
3191 for (i = 0; i < entry->relocation_count; i++) {
40a5f0de 3192 struct drm_i915_gem_relocation_entry *reloc= &relocs[i];
673a394b
EA		 3193 struct drm_gem_object *target_obj;
3194 struct drm_i915_gem_object *target_obj_priv;
3043c60c
EA		 3195 uint32_t reloc_val, reloc_offset;
3196 uint32_t __iomem *reloc_entry;
673a394b 3197
673a394b 3198 target_obj = drm_gem_object_lookup(obj->dev, file_priv,
40a5f0de 3199 reloc->target_handle);
673a394b
EA		 3200 if (target_obj == NULL) {
3201 i915_gem_object_unpin(obj);
3202 return -EBADF;
3203 }
3204 target_obj_priv = target_obj->driver_private;
3205
8542a0bb
CW		 3206#if WATCH_RELOC
3207 DRM_INFO("%s: obj %p offset %08x target %d "
3208 "read %08x write %08x gtt %08x "
3209 "presumed %08x delta %08x\n",
3210 __func__,
3211 obj,
3212 (int) reloc->offset,
3213 (int) reloc->target_handle,
3214 (int) reloc->read_domains,
3215 (int) reloc->write_domain,
3216 (int) target_obj_priv->gtt_offset,
3217 (int) reloc->presumed_offset,
3218 reloc->delta);
3219#endif
3220
673a394b
EA		 3221 /* The target buffer should have appeared before us in the
3222 * exec_object list, so it should have a GTT space bound by now.
3223 */
3224 if (target_obj_priv->gtt_space == NULL) {
3225 DRM_ERROR("No GTT space found for object %d\n",
40a5f0de 3226 reloc->target_handle);
673a394b
EA		 3227 drm_gem_object_unreference(target_obj);
3228 i915_gem_object_unpin(obj);
3229 return -EINVAL;
3230 }
3231
8542a0bb 3232 /* Validate that the target is in a valid r/w GPU domain */
40a5f0de
EA		 3233 if (reloc->write_domain & I915_GEM_DOMAIN_CPU ||
3234 reloc->read_domains & I915_GEM_DOMAIN_CPU) {
e47c68e9
EA		 3235 DRM_ERROR("reloc with read/write CPU domains: "
3236 "obj %p target %d offset %d "
3237 "read %08x write %08x",
40a5f0de
EA		 3238 obj, reloc->target_handle,
3239 (int) reloc->offset,
3240 reloc->read_domains,
3241 reloc->write_domain);
491152b8
CW		 3242 drm_gem_object_unreference(target_obj);
3243 i915_gem_object_unpin(obj);
e47c68e9
EA		 3244 return -EINVAL;
3245 }
40a5f0de
EA		 3246 if (reloc->write_domain && target_obj->pending_write_domain &&
3247 reloc->write_domain != target_obj->pending_write_domain) {
673a394b
EA		 3248 DRM_ERROR("Write domain conflict: "
3249 "obj %p target %d offset %d "
3250 "new %08x old %08x\n",
40a5f0de
EA		 3251 obj, reloc->target_handle,
3252 (int) reloc->offset,
3253 reloc->write_domain,
673a394b
EA		 3254 target_obj->pending_write_domain);
3255 drm_gem_object_unreference(target_obj);
3256 i915_gem_object_unpin(obj);
3257 return -EINVAL;
3258 }
3259
40a5f0de
EA		 3260 target_obj->pending_read_domains |= reloc->read_domains;
3261 target_obj->pending_write_domain |= reloc->write_domain;
673a394b
EA		 3262
3263 /* If the relocation already has the right value in it, no
3264 * more work needs to be done.
3265 */
40a5f0de 3266 if (target_obj_priv->gtt_offset == reloc->presumed_offset) {
673a394b
EA		 3267 drm_gem_object_unreference(target_obj);
3268 continue;
3269 }
3270
8542a0bb
CW		 3271 /* Check that the relocation address is valid... */
3272 if (reloc->offset > obj->size - 4) {
3273 DRM_ERROR("Relocation beyond object bounds: "
3274 "obj %p target %d offset %d size %d.\n",
3275 obj, reloc->target_handle,
3276 (int) reloc->offset, (int) obj->size);
3277 drm_gem_object_unreference(target_obj);
3278 i915_gem_object_unpin(obj);
3279 return -EINVAL;
3280 }
3281 if (reloc->offset & 3) {
3282 DRM_ERROR("Relocation not 4-byte aligned: "
3283 "obj %p target %d offset %d.\n",
3284 obj, reloc->target_handle,
3285 (int) reloc->offset);
3286 drm_gem_object_unreference(target_obj);
3287 i915_gem_object_unpin(obj);
3288 return -EINVAL;
3289 }
3290
3291 /* and points to somewhere within the target object. */
3292 if (reloc->delta >= target_obj->size) {
3293 DRM_ERROR("Relocation beyond target object bounds: "
3294 "obj %p target %d delta %d size %d.\n",
3295 obj, reloc->target_handle,
3296 (int) reloc->delta, (int) target_obj->size);
3297 drm_gem_object_unreference(target_obj);
3298 i915_gem_object_unpin(obj);
3299 return -EINVAL;
3300 }
3301
2ef7eeaa
EA		 3302 ret = i915_gem_object_set_to_gtt_domain(obj, 1);
3303 if (ret != 0) {
3304 drm_gem_object_unreference(target_obj);
3305 i915_gem_object_unpin(obj);
3306 return -EINVAL;
673a394b
EA		 3307 }
3308
3309 /* Map the page containing the relocation we're going to
3310 * perform.
3311 */
40a5f0de 3312 reloc_offset = obj_priv->gtt_offset + reloc->offset;
0839ccb8
KP		 3313 reloc_page = io_mapping_map_atomic_wc(dev_priv->mm.gtt_mapping,
3314 (reloc_offset &
3315 ~(PAGE_SIZE - 1)));
3043c60c 3316 reloc_entry = (uint32_t __iomem *)(reloc_page +
0839ccb8 3317 (reloc_offset & (PAGE_SIZE - 1)));
40a5f0de 3318 reloc_val = target_obj_priv->gtt_offset + reloc->delta;
673a394b
EA		 3319
3320#if WATCH_BUF
3321 DRM_INFO("Applied relocation: %p@0x%08x %08x -> %08x\n",
40a5f0de 3322 obj, (unsigned int) reloc->offset,
673a394b
EA		 3323 readl(reloc_entry), reloc_val);
3324#endif
3325 writel(reloc_val, reloc_entry);
0839ccb8 3326 io_mapping_unmap_atomic(reloc_page);
673a394b 3327
40a5f0de
EA		 3328 /* The updated presumed offset for this entry will be
3329 * copied back out to the user.
673a394b 3330 */
40a5f0de 3331 reloc->presumed_offset = target_obj_priv->gtt_offset;
673a394b
EA		 3332
3333 drm_gem_object_unreference(target_obj);
3334 }
3335
673a394b
EA		 3336#if WATCH_BUF
3337 if (0)
3338 i915_gem_dump_object(obj, 128, __func__, ~0);
3339#endif
3340 return 0;
3341}
3342
3343/** Dispatch a batchbuffer to the ring
3344 */
3345static int
3346i915_dispatch_gem_execbuffer(struct drm_device *dev,
3347 struct drm_i915_gem_execbuffer *exec,
201361a5 3348 struct drm_clip_rect *cliprects,
673a394b
EA		 3349 uint64_t exec_offset)
3350{
3351 drm_i915_private_t *dev_priv = dev->dev_private;
673a394b
EA		 3352 int nbox = exec->num_cliprects;
3353 int i = 0, count;
83d60795 3354 uint32_t exec_start, exec_len;
673a394b
EA		 3355 RING_LOCALS;
3356
3357 exec_start = (uint32_t) exec_offset + exec->batch_start_offset;
3358 exec_len = (uint32_t) exec->batch_len;
3359
1c5d22f7
CW		 3360 trace_i915_gem_request_submit(dev, dev_priv->mm.next_gem_seqno);
3361
673a394b
EA		 3362 count = nbox ? nbox : 1;
3363
3364 for (i = 0; i < count; i++) {
3365 if (i < nbox) {
201361a5 3366 int ret = i915_emit_box(dev, cliprects, i,
673a394b
EA		 3367 exec->DR1, exec->DR4);
3368 if (ret)
3369 return ret;
3370 }
3371
3372 if (IS_I830(dev) || IS_845G(dev)) {
3373 BEGIN_LP_RING(4);
3374 OUT_RING(MI_BATCH_BUFFER);
3375 OUT_RING(exec_start | MI_BATCH_NON_SECURE);
3376 OUT_RING(exec_start + exec_len - 4);
3377 OUT_RING(0);
3378 ADVANCE_LP_RING();
3379 } else {
3380 BEGIN_LP_RING(2);
3381 if (IS_I965G(dev)) {
3382 OUT_RING(MI_BATCH_BUFFER_START |
3383 (2 << 6) |
3384 MI_BATCH_NON_SECURE_I965);
3385 OUT_RING(exec_start);
3386 } else {
3387 OUT_RING(MI_BATCH_BUFFER_START |
3388 (2 << 6));
3389 OUT_RING(exec_start | MI_BATCH_NON_SECURE);
3390 }
3391 ADVANCE_LP_RING();
3392 }
3393 }
3394
3395 /* XXX breadcrumb */
3396 return 0;
3397}
3398
3399/* Throttle our rendering by waiting until the ring has completed our requests
3400 * emitted over 20 msec ago.
3401 *
b962442e
EA		 3402 * Note that if we were to use the current jiffies each time around the loop,
3403 * we wouldn't escape the function with any frames outstanding if the time to
3404 * render a frame was over 20ms.
3405 *
673a394b
EA		 3406 * This should get us reasonable parallelism between CPU and GPU but also
3407 * relatively low latency when blocking on a particular request to finish.
3408 */
3409static int
3410i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file_priv)
3411{
3412 struct drm_i915_file_private *i915_file_priv = file_priv->driver_priv;
3413 int ret = 0;
b962442e 3414 unsigned long recent_enough = jiffies - msecs_to_jiffies(20);
673a394b
EA		 3415
3416 mutex_lock(&dev->struct_mutex);
b962442e
EA		 3417 while (!list_empty(&i915_file_priv->mm.request_list)) {
3418 struct drm_i915_gem_request *request;
3419
3420 request = list_first_entry(&i915_file_priv->mm.request_list,
3421 struct drm_i915_gem_request,
3422 client_list);
3423
3424 if (time_after_eq(request->emitted_jiffies, recent_enough))
3425 break;
3426
3427 ret = i915_wait_request(dev, request->seqno);
3428 if (ret != 0)
3429 break;
3430 }
673a394b 3431 mutex_unlock(&dev->struct_mutex);
b962442e 3432
673a394b
EA		 3433 return ret;
3434}
3435
40a5f0de
EA		 3436static int
3437i915_gem_get_relocs_from_user(struct drm_i915_gem_exec_object *exec_list,
3438 uint32_t buffer_count,
3439 struct drm_i915_gem_relocation_entry **relocs)
3440{
3441 uint32_t reloc_count = 0, reloc_index = 0, i;
3442 int ret;
3443
3444 *relocs = NULL;
3445 for (i = 0; i < buffer_count; i++) {
3446 if (reloc_count + exec_list[i].relocation_count < reloc_count)
3447 return -EINVAL;
3448 reloc_count += exec_list[i].relocation_count;
3449 }
3450
8e7d2b2c 3451 *relocs = drm_calloc_large(reloc_count, sizeof(**relocs));
40a5f0de
EA		 3452 if (*relocs == NULL)
3453 return -ENOMEM;
3454
3455 for (i = 0; i < buffer_count; i++) {
3456 struct drm_i915_gem_relocation_entry __user *user_relocs;
3457
3458 user_relocs = (void __user *)(uintptr_t)exec_list[i].relocs_ptr;
3459
3460 ret = copy_from_user(&(*relocs)[reloc_index],
3461 user_relocs,
3462 exec_list[i].relocation_count *
3463 sizeof(**relocs));
3464 if (ret != 0) {
8e7d2b2c 3465 drm_free_large(*relocs);
40a5f0de 3466 *relocs = NULL;
2bc43b5c 3467 return -EFAULT;
40a5f0de
EA		 3468 }
3469
3470 reloc_index += exec_list[i].relocation_count;
3471 }
3472
2bc43b5c 3473 return 0;
40a5f0de
EA		 3474}
3475
3476static int
3477i915_gem_put_relocs_to_user(struct drm_i915_gem_exec_object *exec_list,
3478 uint32_t buffer_count,
3479 struct drm_i915_gem_relocation_entry *relocs)
3480{
3481 uint32_t reloc_count = 0, i;
2bc43b5c 3482 int ret = 0;
40a5f0de
EA		 3483
3484 for (i = 0; i < buffer_count; i++) {
3485 struct drm_i915_gem_relocation_entry __user *user_relocs;
2bc43b5c 3486 int unwritten;
40a5f0de
EA		 3487
3488 user_relocs = (void __user *)(uintptr_t)exec_list[i].relocs_ptr;
3489
2bc43b5c
FM		 3490 unwritten = copy_to_user(user_relocs,
3491 &relocs[reloc_count],
3492 exec_list[i].relocation_count *
3493 sizeof(*relocs));
3494
3495 if (unwritten) {
3496 ret = -EFAULT;
3497 goto err;
40a5f0de
EA		 3498 }
3499
3500 reloc_count += exec_list[i].relocation_count;
3501 }
3502
2bc43b5c 3503err:
8e7d2b2c 3504 drm_free_large(relocs);
40a5f0de
EA		 3505
3506 return ret;
3507}
3508
83d60795
CW		 3509static int
3510i915_gem_check_execbuffer (struct drm_i915_gem_execbuffer *exec,
3511 uint64_t exec_offset)
3512{
3513 uint32_t exec_start, exec_len;
3514
3515 exec_start = (uint32_t) exec_offset + exec->batch_start_offset;
3516 exec_len = (uint32_t) exec->batch_len;
3517
3518 if ((exec_start | exec_len) & 0x7)
3519 return -EINVAL;
3520
3521 if (!exec_start)
3522 return -EINVAL;
3523
3524 return 0;
3525}
3526
673a394b
EA		 3527int
3528i915_gem_execbuffer(struct drm_device *dev, void *data,
3529 struct drm_file *file_priv)
3530{
3531 drm_i915_private_t *dev_priv = dev->dev_private;
673a394b
EA		 3532 struct drm_i915_gem_execbuffer *args = data;
3533 struct drm_i915_gem_exec_object *exec_list = NULL;
3534 struct drm_gem_object **object_list = NULL;
3535 struct drm_gem_object *batch_obj;
b70d11da 3536 struct drm_i915_gem_object *obj_priv;
201361a5 3537 struct drm_clip_rect *cliprects = NULL;
40a5f0de
EA		 3538 struct drm_i915_gem_relocation_entry *relocs;
3539 int ret, ret2, i, pinned = 0;
673a394b 3540 uint64_t exec_offset;
40a5f0de 3541 uint32_t seqno, flush_domains, reloc_index;
ac94a962 3542 int pin_tries;
673a394b
EA		 3543
3544#if WATCH_EXEC
3545 DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n",
3546 (int) args->buffers_ptr, args->buffer_count, args->batch_len);
3547#endif
3548
4f481ed2
EA		 3549 if (args->buffer_count < 1) {
3550 DRM_ERROR("execbuf with %d buffers\n", args->buffer_count);
3551 return -EINVAL;
3552 }
673a394b 3553 /* Copy in the exec list from userland */
8e7d2b2c
JB		 3554 exec_list = drm_calloc_large(sizeof(*exec_list), args->buffer_count);
3555 object_list = drm_calloc_large(sizeof(*object_list), args->buffer_count);
673a394b
EA		 3556 if (exec_list == NULL || object_list == NULL) {
3557 DRM_ERROR("Failed to allocate exec or object list "
3558 "for %d buffers\n",
3559 args->buffer_count);
3560 ret = -ENOMEM;
3561 goto pre_mutex_err;
3562 }
3563 ret = copy_from_user(exec_list,
3564 (struct drm_i915_relocation_entry __user *)
3565 (uintptr_t) args->buffers_ptr,
3566 sizeof(*exec_list) * args->buffer_count);
3567 if (ret != 0) {
3568 DRM_ERROR("copy %d exec entries failed %d\n",
3569 args->buffer_count, ret);
3570 goto pre_mutex_err;
3571 }
3572
201361a5 3573 if (args->num_cliprects != 0) {
9a298b2a
EA		 3574 cliprects = kcalloc(args->num_cliprects, sizeof(*cliprects),
3575 GFP_KERNEL);
201361a5
EA		 3576 if (cliprects == NULL)
3577 goto pre_mutex_err;
3578
3579 ret = copy_from_user(cliprects,
3580 (struct drm_clip_rect __user *)
3581 (uintptr_t) args->cliprects_ptr,
3582 sizeof(*cliprects) * args->num_cliprects);
3583 if (ret != 0) {
3584 DRM_ERROR("copy %d cliprects failed: %d\n",
3585 args->num_cliprects, ret);
3586 goto pre_mutex_err;
3587 }
3588 }
3589
40a5f0de
EA		 3590 ret = i915_gem_get_relocs_from_user(exec_list, args->buffer_count,
3591 &relocs);
3592 if (ret != 0)
3593 goto pre_mutex_err;
3594
673a394b
EA		 3595 mutex_lock(&dev->struct_mutex);
3596
3597 i915_verify_inactive(dev, __FILE__, __LINE__);
3598
ba1234d1 3599 if (atomic_read(&dev_priv->mm.wedged)) {
673a394b
EA		 3600 DRM_ERROR("Execbuf while wedged\n");
3601 mutex_unlock(&dev->struct_mutex);
a198bc80
CW		 3602 ret = -EIO;
3603 goto pre_mutex_err;
673a394b
EA		 3604 }
3605
3606 if (dev_priv->mm.suspended) {
3607 DRM_ERROR("Execbuf while VT-switched.\n");
3608 mutex_unlock(&dev->struct_mutex);
a198bc80
CW		 3609 ret = -EBUSY;
3610 goto pre_mutex_err;
673a394b
EA		 3611 }
3612
ac94a962 3613 /* Look up object handles */
673a394b
EA		 3614 for (i = 0; i < args->buffer_count; i++) {
3615 object_list[i] = drm_gem_object_lookup(dev, file_priv,
3616 exec_list[i].handle);
3617 if (object_list[i] == NULL) {
3618 DRM_ERROR("Invalid object handle %d at index %d\n",
3619 exec_list[i].handle, i);
3620 ret = -EBADF;
3621 goto err;
3622 }
b70d11da
KH		 3623
3624 obj_priv = object_list[i]->driver_private;
3625 if (obj_priv->in_execbuffer) {
3626 DRM_ERROR("Object %p appears more than once in object list\n",
3627 object_list[i]);
3628 ret = -EBADF;
3629 goto err;
3630 }
3631 obj_priv->in_execbuffer = true;
ac94a962 3632 }
673a394b 3633
ac94a962
KP		 3634 /* Pin and relocate */
3635 for (pin_tries = 0; ; pin_tries++) {
3636 ret = 0;
40a5f0de
EA		 3637 reloc_index = 0;
3638
ac94a962
KP		 3639 for (i = 0; i < args->buffer_count; i++) {
3640 object_list[i]->pending_read_domains = 0;
3641 object_list[i]->pending_write_domain = 0;
3642 ret = i915_gem_object_pin_and_relocate(object_list[i],
3643 file_priv,
40a5f0de
EA		 3644 &exec_list[i],
3645 &relocs[reloc_index]);
ac94a962
KP		 3646 if (ret)
3647 break;
3648 pinned = i + 1;
40a5f0de 3649 reloc_index += exec_list[i].relocation_count;
ac94a962
KP		 3650 }
3651 /* success */
3652 if (ret == 0)
3653 break;
3654
3655 /* error other than GTT full, or we've already tried again */
2939e1f5 3656 if (ret != -ENOSPC || pin_tries >= 1) {
07f73f69
CW		 3657 if (ret != -ERESTARTSYS) {
3658 unsigned long long total_size = 0;
3659 for (i = 0; i < args->buffer_count; i++)
3660 total_size += object_list[i]->size;
3661 DRM_ERROR("Failed to pin buffer %d of %d, total %llu bytes: %d\n",
3662 pinned+1, args->buffer_count,
3663 total_size, ret);
3664 DRM_ERROR("%d objects [%d pinned], "
3665 "%d object bytes [%d pinned], "
3666 "%d/%d gtt bytes\n",
3667 atomic_read(&dev->object_count),
3668 atomic_read(&dev->pin_count),
3669 atomic_read(&dev->object_memory),
3670 atomic_read(&dev->pin_memory),
3671 atomic_read(&dev->gtt_memory),
3672 dev->gtt_total);
3673 }
673a394b
EA		 3674 goto err;
3675 }
ac94a962
KP		 3676
3677 /* unpin all of our buffers */
3678 for (i = 0; i < pinned; i++)
3679 i915_gem_object_unpin(object_list[i]);
b1177636 3680 pinned = 0;
ac94a962
KP		 3681
3682 /* evict everyone we can from the aperture */
3683 ret = i915_gem_evict_everything(dev);
07f73f69 3684 if (ret && ret != -ENOSPC)
ac94a962 3685 goto err;
673a394b
EA		 3686 }
3687
3688 /* Set the pending read domains for the batch buffer to COMMAND */
3689 batch_obj = object_list[args->buffer_count-1];
5f26a2c7
CW		 3690 if (batch_obj->pending_write_domain) {
3691 DRM_ERROR("Attempting to use self-modifying batch buffer\n");
3692 ret = -EINVAL;
3693 goto err;
3694 }
3695 batch_obj->pending_read_domains |= I915_GEM_DOMAIN_COMMAND;
673a394b 3696
83d60795
CW		 3697 /* Sanity check the batch buffer, prior to moving objects */
3698 exec_offset = exec_list[args->buffer_count - 1].offset;
3699 ret = i915_gem_check_execbuffer (args, exec_offset);
3700 if (ret != 0) {
3701 DRM_ERROR("execbuf with invalid offset/length\n");
3702 goto err;
3703 }
3704
673a394b
EA		 3705 i915_verify_inactive(dev, __FILE__, __LINE__);
3706
646f0f6e
KP		 3707 /* Zero the global flush/invalidate flags. These
3708 * will be modified as new domains are computed
3709 * for each object
3710 */
3711 dev->invalidate_domains = 0;
3712 dev->flush_domains = 0;
3713
673a394b
EA		 3714 for (i = 0; i < args->buffer_count; i++) {
3715 struct drm_gem_object *obj = object_list[i];
673a394b 3716
646f0f6e 3717 /* Compute new gpu domains and update invalidate/flush */
8b0e378a 3718 i915_gem_object_set_to_gpu_domain(obj);
673a394b
EA		 3719 }
3720
3721 i915_verify_inactive(dev, __FILE__, __LINE__);
3722
646f0f6e
KP		 3723 if (dev->invalidate_domains | dev->flush_domains) {
3724#if WATCH_EXEC
3725 DRM_INFO("%s: invalidate_domains %08x flush_domains %08x\n",
3726 __func__,
3727 dev->invalidate_domains,
3728 dev->flush_domains);
3729#endif
3730 i915_gem_flush(dev,
3731 dev->invalidate_domains,
3732 dev->flush_domains);
3733 if (dev->flush_domains)
b962442e
EA		 3734 (void)i915_add_request(dev, file_priv,
3735 dev->flush_domains);
646f0f6e 3736 }
673a394b 3737
efbeed96
EA		 3738 for (i = 0; i < args->buffer_count; i++) {
3739 struct drm_gem_object *obj = object_list[i];
1c5d22f7 3740 uint32_t old_write_domain = obj->write_domain;
efbeed96
EA		 3741
3742 obj->write_domain = obj->pending_write_domain;
1c5d22f7
CW		 3743 trace_i915_gem_object_change_domain(obj,
3744 obj->read_domains,
3745 old_write_domain);
efbeed96
EA		 3746 }
3747
673a394b
EA		 3748 i915_verify_inactive(dev, __FILE__, __LINE__);
3749
3750#if WATCH_COHERENCY
3751 for (i = 0; i < args->buffer_count; i++) {
3752 i915_gem_object_check_coherency(object_list[i],
3753 exec_list[i].handle);
3754 }
3755#endif
3756
673a394b 3757#if WATCH_EXEC
6911a9b8 3758 i915_gem_dump_object(batch_obj,
673a394b
EA		 3759 args->batch_len,
3760 __func__,
3761 ~0);
3762#endif
3763
673a394b 3764 /* Exec the batchbuffer */
201361a5 3765 ret = i915_dispatch_gem_execbuffer(dev, args, cliprects, exec_offset);
673a394b
EA		 3766 if (ret) {
3767 DRM_ERROR("dispatch failed %d\n", ret);
3768 goto err;
3769 }
3770
3771 /*
3772 * Ensure that the commands in the batch buffer are
3773 * finished before the interrupt fires
3774 */
3775 flush_domains = i915_retire_commands(dev);
3776
3777 i915_verify_inactive(dev, __FILE__, __LINE__);
3778
3779 /*
3780 * Get a seqno representing the execution of the current buffer,
3781 * which we can wait on. We would like to mitigate these interrupts,
3782 * likely by only creating seqnos occasionally (so that we have
3783 * *some* interrupts representing completion of buffers that we can
3784 * wait on when trying to clear up gtt space).
3785 */
b962442e 3786 seqno = i915_add_request(dev, file_priv, flush_domains);
673a394b 3787 BUG_ON(seqno == 0);
673a394b
EA		 3788 for (i = 0; i < args->buffer_count; i++) {
3789 struct drm_gem_object *obj = object_list[i];
673a394b 3790
ce44b0ea 3791 i915_gem_object_move_to_active(obj, seqno);
673a394b
EA		 3792#if WATCH_LRU
3793 DRM_INFO("%s: move to exec list %p\n", __func__, obj);
3794#endif
3795 }
3796#if WATCH_LRU
3797 i915_dump_lru(dev, __func__);
3798#endif
3799
3800 i915_verify_inactive(dev, __FILE__, __LINE__);
3801
673a394b 3802err:
aad87dff
JL		 3803 for (i = 0; i < pinned; i++)
3804 i915_gem_object_unpin(object_list[i]);
3805
b70d11da
KH		 3806 for (i = 0; i < args->buffer_count; i++) {
3807 if (object_list[i]) {
3808 obj_priv = object_list[i]->driver_private;
3809 obj_priv->in_execbuffer = false;
3810 }
aad87dff 3811 drm_gem_object_unreference(object_list[i]);
b70d11da 3812 }
673a394b 3813
673a394b
EA		 3814 mutex_unlock(&dev->struct_mutex);
3815
a35f2e2b
RD		 3816 if (!ret) {
3817 /* Copy the new buffer offsets back to the user's exec list. */
3818 ret = copy_to_user((struct drm_i915_relocation_entry __user *)
3819 (uintptr_t) args->buffers_ptr,
3820 exec_list,
3821 sizeof(*exec_list) * args->buffer_count);
2bc43b5c
FM		 3822 if (ret) {
3823 ret = -EFAULT;
a35f2e2b
RD		 3824 DRM_ERROR("failed to copy %d exec entries "
3825 "back to user (%d)\n",
3826 args->buffer_count, ret);
2bc43b5c 3827 }
a35f2e2b
RD		 3828 }
3829
40a5f0de
EA		 3830 /* Copy the updated relocations out regardless of current error
3831 * state. Failure to update the relocs would mean that the next
3832 * time userland calls execbuf, it would do so with presumed offset
3833 * state that didn't match the actual object state.
3834 */
3835 ret2 = i915_gem_put_relocs_to_user(exec_list, args->buffer_count,
3836 relocs);
3837 if (ret2 != 0) {
3838 DRM_ERROR("Failed to copy relocations back out: %d\n", ret2);
3839
3840 if (ret == 0)
3841 ret = ret2;
3842 }
3843
673a394b 3844pre_mutex_err:
8e7d2b2c
JB		 3845 drm_free_large(object_list);
3846 drm_free_large(exec_list);
9a298b2a 3847 kfree(cliprects);
673a394b
EA		 3848
3849 return ret;
3850}
3851
3852int
3853i915_gem_object_pin(struct drm_gem_object *obj, uint32_t alignment)
3854{
3855 struct drm_device *dev = obj->dev;
3856 struct drm_i915_gem_object *obj_priv = obj->driver_private;
3857 int ret;
3858
3859 i915_verify_inactive(dev, __FILE__, __LINE__);
3860 if (obj_priv->gtt_space == NULL) {
3861 ret = i915_gem_object_bind_to_gtt(obj, alignment);
9731129c 3862 if (ret)
673a394b 3863 return ret;
22c344e9
CW		 3864 }
3865 /*
3866 * Pre-965 chips need a fence register set up in order to
3867 * properly handle tiled surfaces.
3868 */
a09ba7fa 3869 if (!IS_I965G(dev) && obj_priv->tiling_mode != I915_TILING_NONE) {
8c4b8c3f 3870 ret = i915_gem_object_get_fence_reg(obj);
22c344e9
CW		 3871 if (ret != 0) {
3872 if (ret != -EBUSY && ret != -ERESTARTSYS)
3873 DRM_ERROR("Failure to install fence: %d\n",
3874 ret);
3875 return ret;
3876 }
673a394b
EA		 3877 }
3878 obj_priv->pin_count++;
3879
3880 /* If the object is not active and not pending a flush,
3881 * remove it from the inactive list
3882 */
3883 if (obj_priv->pin_count == 1) {
3884 atomic_inc(&dev->pin_count);
3885 atomic_add(obj->size, &dev->pin_memory);
3886 if (!obj_priv->active &&
21d509e3 3887 (obj->write_domain & I915_GEM_GPU_DOMAINS) == 0 &&
673a394b
EA		 3888 !list_empty(&obj_priv->list))
3889 list_del_init(&obj_priv->list);
3890 }
3891 i915_verify_inactive(dev, __FILE__, __LINE__);
3892
3893 return 0;
3894}
3895
3896void
3897i915_gem_object_unpin(struct drm_gem_object *obj)
3898{
3899 struct drm_device *dev = obj->dev;
3900 drm_i915_private_t *dev_priv = dev->dev_private;
3901 struct drm_i915_gem_object *obj_priv = obj->driver_private;
3902
3903 i915_verify_inactive(dev, __FILE__, __LINE__);
3904 obj_priv->pin_count--;
3905 BUG_ON(obj_priv->pin_count < 0);
3906 BUG_ON(obj_priv->gtt_space == NULL);
3907
3908 /* If the object is no longer pinned, and is
3909 * neither active nor being flushed, then stick it on
3910 * the inactive list
3911 */
3912 if (obj_priv->pin_count == 0) {
3913 if (!obj_priv->active &&
21d509e3 3914 (obj->write_domain & I915_GEM_GPU_DOMAINS) == 0)
673a394b
EA		 3915 list_move_tail(&obj_priv->list,
3916 &dev_priv->mm.inactive_list);
3917 atomic_dec(&dev->pin_count);
3918 atomic_sub(obj->size, &dev->pin_memory);
3919 }
3920 i915_verify_inactive(dev, __FILE__, __LINE__);
3921}
3922
3923int
3924i915_gem_pin_ioctl(struct drm_device *dev, void *data,
3925 struct drm_file *file_priv)
3926{
3927 struct drm_i915_gem_pin *args = data;
3928 struct drm_gem_object *obj;
3929 struct drm_i915_gem_object *obj_priv;
3930 int ret;
3931
3932 mutex_lock(&dev->struct_mutex);
3933
3934 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
3935 if (obj == NULL) {
3936 DRM_ERROR("Bad handle in i915_gem_pin_ioctl(): %d\n",
3937 args->handle);
3938 mutex_unlock(&dev->struct_mutex);
3939 return -EBADF;
3940 }
3941 obj_priv = obj->driver_private;
3942
bb6baf76
CW		 3943 if (obj_priv->madv != I915_MADV_WILLNEED) {
3944 DRM_ERROR("Attempting to pin a purgeable buffer\n");
3ef94daa
CW		 3945 drm_gem_object_unreference(obj);
3946 mutex_unlock(&dev->struct_mutex);
3947 return -EINVAL;
3948 }
3949
79e53945
JB		 3950 if (obj_priv->pin_filp != NULL && obj_priv->pin_filp != file_priv) {
3951 DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n",
3952 args->handle);
96dec61d 3953 drm_gem_object_unreference(obj);
673a394b 3954 mutex_unlock(&dev->struct_mutex);
79e53945
JB		 3955 return -EINVAL;
3956 }
3957
3958 obj_priv->user_pin_count++;
3959 obj_priv->pin_filp = file_priv;
3960 if (obj_priv->user_pin_count == 1) {
3961 ret = i915_gem_object_pin(obj, args->alignment);
3962 if (ret != 0) {
3963 drm_gem_object_unreference(obj);
3964 mutex_unlock(&dev->struct_mutex);
3965 return ret;
3966 }
673a394b
EA		 3967 }
3968
3969 /* XXX - flush the CPU caches for pinned objects
3970 * as the X server doesn't manage domains yet
3971 */
e47c68e9 3972 i915_gem_object_flush_cpu_write_domain(obj);
673a394b
EA		 3973 args->offset = obj_priv->gtt_offset;
3974 drm_gem_object_unreference(obj);
3975 mutex_unlock(&dev->struct_mutex);
3976
3977 return 0;
3978}
3979
3980int
3981i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
3982 struct drm_file *file_priv)
3983{
3984 struct drm_i915_gem_pin *args = data;
3985 struct drm_gem_object *obj;
79e53945 3986 struct drm_i915_gem_object *obj_priv;
673a394b
EA		 3987
3988 mutex_lock(&dev->struct_mutex);
3989
3990 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
3991 if (obj == NULL) {
3992 DRM_ERROR("Bad handle in i915_gem_unpin_ioctl(): %d\n",
3993 args->handle);
3994 mutex_unlock(&dev->struct_mutex);
3995 return -EBADF;
3996 }
3997
79e53945
JB		 3998 obj_priv = obj->driver_private;
3999 if (obj_priv->pin_filp != file_priv) {
4000 DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n",
4001 args->handle);
4002 drm_gem_object_unreference(obj);
4003 mutex_unlock(&dev->struct_mutex);
4004 return -EINVAL;
4005 }
4006 obj_priv->user_pin_count--;
4007 if (obj_priv->user_pin_count == 0) {
4008 obj_priv->pin_filp = NULL;
4009 i915_gem_object_unpin(obj);
4010 }
673a394b
EA		 4011
4012 drm_gem_object_unreference(obj);
4013 mutex_unlock(&dev->struct_mutex);
4014 return 0;
4015}
4016
4017int
4018i915_gem_busy_ioctl(struct drm_device *dev, void *data,
4019 struct drm_file *file_priv)
4020{
4021 struct drm_i915_gem_busy *args = data;
4022 struct drm_gem_object *obj;
4023 struct drm_i915_gem_object *obj_priv;
4024
673a394b
EA		 4025 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
4026 if (obj == NULL) {
4027 DRM_ERROR("Bad handle in i915_gem_busy_ioctl(): %d\n",
4028 args->handle);
673a394b
EA		 4029 return -EBADF;
4030 }
4031
b1ce786c 4032 mutex_lock(&dev->struct_mutex);
f21289b3
EA		 4033 /* Update the active list for the hardware's current position.
4034 * Otherwise this only updates on a delayed timer or when irqs are
4035 * actually unmasked, and our working set ends up being larger than
4036 * required.
4037 */
4038 i915_gem_retire_requests(dev);
4039
673a394b 4040 obj_priv = obj->driver_private;
c4de0a5d
EA		 4041 /* Don't count being on the flushing list against the object being
4042 * done. Otherwise, a buffer left on the flushing list but not getting
4043 * flushed (because nobody's flushing that domain) won't ever return
4044 * unbusy and get reused by libdrm's bo cache. The other expected
4045 * consumer of this interface, OpenGL's occlusion queries, also specs
4046 * that the objects get unbusy "eventually" without any interference.
4047 */
4048 args->busy = obj_priv->active && obj_priv->last_rendering_seqno != 0;
673a394b
EA		 4049
4050 drm_gem_object_unreference(obj);
4051 mutex_unlock(&dev->struct_mutex);
4052 return 0;
4053}
4054
4055int
4056i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
4057 struct drm_file *file_priv)
4058{
4059 return i915_gem_ring_throttle(dev, file_priv);
4060}
4061
3ef94daa
CW		 4062int
4063i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
4064 struct drm_file *file_priv)
4065{
4066 struct drm_i915_gem_madvise *args = data;
4067 struct drm_gem_object *obj;
4068 struct drm_i915_gem_object *obj_priv;
4069
4070 switch (args->madv) {
4071 case I915_MADV_DONTNEED:
4072 case I915_MADV_WILLNEED:
4073 break;
4074 default:
4075 return -EINVAL;
4076 }
4077
4078 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
4079 if (obj == NULL) {
4080 DRM_ERROR("Bad handle in i915_gem_madvise_ioctl(): %d\n",
4081 args->handle);
4082 return -EBADF;
4083 }
4084
4085 mutex_lock(&dev->struct_mutex);
4086 obj_priv = obj->driver_private;
4087
4088 if (obj_priv->pin_count) {
4089 drm_gem_object_unreference(obj);
4090 mutex_unlock(&dev->struct_mutex);
4091
4092 DRM_ERROR("Attempted i915_gem_madvise_ioctl() on a pinned object\n");
4093 return -EINVAL;
4094 }
4095
bb6baf76
CW		 4096 if (obj_priv->madv != __I915_MADV_PURGED)
4097 obj_priv->madv = args->madv;
3ef94daa 4098
2d7ef395
CW		 4099 /* if the object is no longer bound, discard its backing storage */
4100 if (i915_gem_object_is_purgeable(obj_priv) &&
4101 obj_priv->gtt_space == NULL)
4102 i915_gem_object_truncate(obj);
4103
bb6baf76
CW		 4104 args->retained = obj_priv->madv != __I915_MADV_PURGED;
4105
3ef94daa
CW		 4106 drm_gem_object_unreference(obj);
4107 mutex_unlock(&dev->struct_mutex);
4108
4109 return 0;
4110}
4111
673a394b
EA		 4112int i915_gem_init_object(struct drm_gem_object *obj)
4113{
4114 struct drm_i915_gem_object *obj_priv;
4115
9a298b2a 4116 obj_priv = kzalloc(sizeof(*obj_priv), GFP_KERNEL);
673a394b
EA		 4117 if (obj_priv == NULL)
4118 return -ENOMEM;
4119
4120 /*
4121 * We've just allocated pages from the kernel,
4122 * so they've just been written by the CPU with
4123 * zeros. They'll need to be clflushed before we
4124 * use them with the GPU.
4125 */
4126 obj->write_domain = I915_GEM_DOMAIN_CPU;
4127 obj->read_domains = I915_GEM_DOMAIN_CPU;
4128
ba1eb1d8
KP		 4129 obj_priv->agp_type = AGP_USER_MEMORY;
4130
673a394b
EA		 4131 obj->driver_private = obj_priv;
4132 obj_priv->obj = obj;
de151cf6 4133 obj_priv->fence_reg = I915_FENCE_REG_NONE;
673a394b 4134 INIT_LIST_HEAD(&obj_priv->list);
a09ba7fa 4135 INIT_LIST_HEAD(&obj_priv->fence_list);
3ef94daa 4136 obj_priv->madv = I915_MADV_WILLNEED;
de151cf6 4137
1c5d22f7
CW		 4138 trace_i915_gem_object_create(obj);
4139
673a394b
EA		 4140 return 0;
4141}
4142
4143void i915_gem_free_object(struct drm_gem_object *obj)
4144{
de151cf6 4145 struct drm_device *dev = obj->dev;
673a394b
EA		 4146 struct drm_i915_gem_object *obj_priv = obj->driver_private;
4147
1c5d22f7
CW		 4148 trace_i915_gem_object_destroy(obj);
4149
673a394b
EA		 4150 while (obj_priv->pin_count > 0)
4151 i915_gem_object_unpin(obj);
4152
71acb5eb
DA		 4153 if (obj_priv->phys_obj)
4154 i915_gem_detach_phys_object(dev, obj);
4155
673a394b
EA		 4156 i915_gem_object_unbind(obj);
4157
7e616158
CW		 4158 if (obj_priv->mmap_offset)
4159 i915_gem_free_mmap_offset(obj);
de151cf6 4160
9a298b2a 4161 kfree(obj_priv->page_cpu_valid);
280b713b 4162 kfree(obj_priv->bit_17);
9a298b2a 4163 kfree(obj->driver_private);
673a394b
EA		 4164}
4165
ab5ee576 4166/** Unbinds all inactive objects. */
673a394b 4167static int
ab5ee576 4168i915_gem_evict_from_inactive_list(struct drm_device *dev)
673a394b 4169{
ab5ee576 4170 drm_i915_private_t *dev_priv = dev->dev_private;
673a394b 4171
ab5ee576
CW		 4172 while (!list_empty(&dev_priv->mm.inactive_list)) {
4173 struct drm_gem_object *obj;
4174 int ret;
673a394b 4175
ab5ee576
CW		 4176 obj = list_first_entry(&dev_priv->mm.inactive_list,
4177 struct drm_i915_gem_object,
4178 list)->obj;
673a394b
EA		 4179
4180 ret = i915_gem_object_unbind(obj);
4181 if (ret != 0) {
ab5ee576 4182 DRM_ERROR("Error unbinding object: %d\n", ret);
673a394b
EA		 4183 return ret;
4184 }
4185 }
4186
673a394b
EA		 4187 return 0;
4188}
4189
5669fcac 4190int
673a394b
EA		 4191i915_gem_idle(struct drm_device *dev)
4192{
4193 drm_i915_private_t *dev_priv = dev->dev_private;
4194 uint32_t seqno, cur_seqno, last_seqno;
4195 int stuck, ret;
4196
6dbe2772
KP		 4197 mutex_lock(&dev->struct_mutex);
4198
4199 if (dev_priv->mm.suspended || dev_priv->ring.ring_obj == NULL) {
4200 mutex_unlock(&dev->struct_mutex);
673a394b 4201 return 0;
6dbe2772 4202 }
673a394b
EA		 4203
4204 /* Hack! Don't let anybody do execbuf while we don't control the chip.
4205 * We need to replace this with a semaphore, or something.
4206 */
4207 dev_priv->mm.suspended = 1;
f65d9421 4208 del_timer(&dev_priv->hangcheck_timer);
673a394b 4209
6dbe2772
KP		 4210 /* Cancel the retire work handler, wait for it to finish if running
4211 */
4212 mutex_unlock(&dev->struct_mutex);
4213 cancel_delayed_work_sync(&dev_priv->mm.retire_work);
4214 mutex_lock(&dev->struct_mutex);
4215
673a394b
EA		 4216 i915_kernel_lost_context(dev);
4217
4218 /* Flush the GPU along with all non-CPU write domains
4219 */
21d509e3
CW		 4220 i915_gem_flush(dev, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
4221 seqno = i915_add_request(dev, NULL, I915_GEM_GPU_DOMAINS);
673a394b
EA		 4222
4223 if (seqno == 0) {
4224 mutex_unlock(&dev->struct_mutex);
4225 return -ENOMEM;
4226 }
4227
4228 dev_priv->mm.waiting_gem_seqno = seqno;
4229 last_seqno = 0;
4230 stuck = 0;
4231 for (;;) {
4232 cur_seqno = i915_get_gem_seqno(dev);
4233 if (i915_seqno_passed(cur_seqno, seqno))
4234 break;
4235 if (last_seqno == cur_seqno) {
4236 if (stuck++ > 100) {
4237 DRM_ERROR("hardware wedged\n");
ba1234d1 4238 atomic_set(&dev_priv->mm.wedged, 1);
673a394b
EA		 4239 DRM_WAKEUP(&dev_priv->irq_queue);
4240 break;
4241 }
4242 }
4243 msleep(10);
4244 last_seqno = cur_seqno;
4245 }
4246 dev_priv->mm.waiting_gem_seqno = 0;
4247
4248 i915_gem_retire_requests(dev);
4249
5e118f41 4250 spin_lock(&dev_priv->mm.active_list_lock);
ba1234d1 4251 if (!atomic_read(&dev_priv->mm.wedged)) {
28dfe52a
EA		 4252 /* Active and flushing should now be empty as we've
4253 * waited for a sequence higher than any pending execbuffer
4254 */
4255 WARN_ON(!list_empty(&dev_priv->mm.active_list));
4256 WARN_ON(!list_empty(&dev_priv->mm.flushing_list));
4257 /* Request should now be empty as we've also waited
4258 * for the last request in the list
4259 */
4260 WARN_ON(!list_empty(&dev_priv->mm.request_list));
4261 }
673a394b 4262
28dfe52a
EA		 4263 /* Empty the active and flushing lists to inactive. If there's
4264 * anything left at this point, it means that we're wedged and
4265 * nothing good's going to happen by leaving them there. So strip
4266 * the GPU domains and just stuff them onto inactive.
673a394b 4267 */
28dfe52a 4268 while (!list_empty(&dev_priv->mm.active_list)) {
1c5d22f7
CW		 4269 struct drm_gem_object *obj;
4270 uint32_t old_write_domain;
4271
4272 obj = list_first_entry(&dev_priv->mm.active_list,
4273 struct drm_i915_gem_object,
4274 list)->obj;
4275 old_write_domain = obj->write_domain;
4276 obj->write_domain &= ~I915_GEM_GPU_DOMAINS;
4277 i915_gem_object_move_to_inactive(obj);
4278
4279 trace_i915_gem_object_change_domain(obj,
4280 obj->read_domains,
4281 old_write_domain);
28dfe52a 4282 }
5e118f41 4283 spin_unlock(&dev_priv->mm.active_list_lock);
28dfe52a
EA		 4284
4285 while (!list_empty(&dev_priv->mm.flushing_list)) {
1c5d22f7
CW		 4286 struct drm_gem_object *obj;
4287 uint32_t old_write_domain;
4288
4289 obj = list_first_entry(&dev_priv->mm.flushing_list,
4290 struct drm_i915_gem_object,
4291 list)->obj;
4292 old_write_domain = obj->write_domain;
4293 obj->write_domain &= ~I915_GEM_GPU_DOMAINS;
4294 i915_gem_object_move_to_inactive(obj);
4295
4296 trace_i915_gem_object_change_domain(obj,
4297 obj->read_domains,
4298 old_write_domain);
28dfe52a
EA		 4299 }
4300
4301
4302 /* Move all inactive buffers out of the GTT. */
ab5ee576 4303 ret = i915_gem_evict_from_inactive_list(dev);
28dfe52a 4304 WARN_ON(!list_empty(&dev_priv->mm.inactive_list));
6dbe2772
KP		 4305 if (ret) {
4306 mutex_unlock(&dev->struct_mutex);
673a394b 4307 return ret;
6dbe2772 4308 }
673a394b 4309
6dbe2772
KP		 4310 i915_gem_cleanup_ringbuffer(dev);
4311 mutex_unlock(&dev->struct_mutex);
4312
673a394b
EA		 4313 return 0;
4314}
4315
4316static int
4317i915_gem_init_hws(struct drm_device *dev)
4318{
4319 drm_i915_private_t *dev_priv = dev->dev_private;
4320 struct drm_gem_object *obj;
4321 struct drm_i915_gem_object *obj_priv;
4322 int ret;
4323
4324 /* If we need a physical address for the status page, it's already
4325 * initialized at driver load time.
4326 */
4327 if (!I915_NEED_GFX_HWS(dev))
4328 return 0;
4329
4330 obj = drm_gem_object_alloc(dev, 4096);
4331 if (obj == NULL) {
4332 DRM_ERROR("Failed to allocate status page\n");
4333 return -ENOMEM;
4334 }
4335 obj_priv = obj->driver_private;
ba1eb1d8 4336 obj_priv->agp_type = AGP_USER_CACHED_MEMORY;
673a394b
EA		 4337
4338 ret = i915_gem_object_pin(obj, 4096);
4339 if (ret != 0) {
4340 drm_gem_object_unreference(obj);
4341 return ret;
4342 }
4343
4344 dev_priv->status_gfx_addr = obj_priv->gtt_offset;
673a394b 4345
856fa198 4346 dev_priv->hw_status_page = kmap(obj_priv->pages[0]);
ba1eb1d8 4347 if (dev_priv->hw_status_page == NULL) {
673a394b
EA		 4348 DRM_ERROR("Failed to map status page.\n");
4349 memset(&dev_priv->hws_map, 0, sizeof(dev_priv->hws_map));
3eb2ee77 4350 i915_gem_object_unpin(obj);
673a394b
EA		 4351 drm_gem_object_unreference(obj);
4352 return -EINVAL;
4353 }
4354 dev_priv->hws_obj = obj;
673a394b
EA		 4355 memset(dev_priv->hw_status_page, 0, PAGE_SIZE);
4356 I915_WRITE(HWS_PGA, dev_priv->status_gfx_addr);
ba1eb1d8 4357 I915_READ(HWS_PGA); /* posting read */
673a394b
EA		 4358 DRM_DEBUG("hws offset: 0x%08x\n", dev_priv->status_gfx_addr);
4359
4360 return 0;
4361}
4362
85a7bb98
CW		 4363static void
4364i915_gem_cleanup_hws(struct drm_device *dev)
4365{
4366 drm_i915_private_t *dev_priv = dev->dev_private;
bab2d1f6
CW		 4367 struct drm_gem_object *obj;
4368 struct drm_i915_gem_object *obj_priv;
85a7bb98
CW		 4369
4370 if (dev_priv->hws_obj == NULL)
4371 return;
4372
bab2d1f6
CW		 4373 obj = dev_priv->hws_obj;
4374 obj_priv = obj->driver_private;
4375
856fa198 4376 kunmap(obj_priv->pages[0]);
85a7bb98
CW		 4377 i915_gem_object_unpin(obj);
4378 drm_gem_object_unreference(obj);
4379 dev_priv->hws_obj = NULL;
bab2d1f6 4380
85a7bb98
CW		 4381 memset(&dev_priv->hws_map, 0, sizeof(dev_priv->hws_map));
4382 dev_priv->hw_status_page = NULL;
4383
4384 /* Write high address into HWS_PGA when disabling. */
4385 I915_WRITE(HWS_PGA, 0x1ffff000);
4386}
4387
79e53945 4388int
673a394b
EA		 4389i915_gem_init_ringbuffer(struct drm_device *dev)
4390{
4391 drm_i915_private_t *dev_priv = dev->dev_private;
4392 struct drm_gem_object *obj;
4393 struct drm_i915_gem_object *obj_priv;
79e53945 4394 drm_i915_ring_buffer_t *ring = &dev_priv->ring;
673a394b 4395 int ret;
50aa253d 4396 u32 head;
673a394b
EA		 4397
4398 ret = i915_gem_init_hws(dev);
4399 if (ret != 0)
4400 return ret;
4401
4402 obj = drm_gem_object_alloc(dev, 128 * 1024);
4403 if (obj == NULL) {
4404 DRM_ERROR("Failed to allocate ringbuffer\n");
85a7bb98 4405 i915_gem_cleanup_hws(dev);
673a394b
EA		 4406 return -ENOMEM;
4407 }
4408 obj_priv = obj->driver_private;
4409
4410 ret = i915_gem_object_pin(obj, 4096);
4411 if (ret != 0) {
4412 drm_gem_object_unreference(obj);
85a7bb98 4413 i915_gem_cleanup_hws(dev);
673a394b
EA		 4414 return ret;
4415 }
4416
4417 /* Set up the kernel mapping for the ring. */
79e53945 4418 ring->Size = obj->size;
673a394b 4419
79e53945
JB		 4420 ring->map.offset = dev->agp->base + obj_priv->gtt_offset;
4421 ring->map.size = obj->size;
4422 ring->map.type = 0;
4423 ring->map.flags = 0;
4424 ring->map.mtrr = 0;
673a394b 4425
79e53945
JB		 4426 drm_core_ioremap_wc(&ring->map, dev);
4427 if (ring->map.handle == NULL) {
673a394b
EA		 4428 DRM_ERROR("Failed to map ringbuffer.\n");
4429 memset(&dev_priv->ring, 0, sizeof(dev_priv->ring));
47ed185a 4430 i915_gem_object_unpin(obj);
673a394b 4431 drm_gem_object_unreference(obj);
85a7bb98 4432 i915_gem_cleanup_hws(dev);
673a394b
EA		 4433 return -EINVAL;
4434 }
79e53945
JB		 4435 ring->ring_obj = obj;
4436 ring->virtual_start = ring->map.handle;
673a394b
EA		 4437
4438 /* Stop the ring if it's running. */
4439 I915_WRITE(PRB0_CTL, 0);
673a394b 4440 I915_WRITE(PRB0_TAIL, 0);
50aa253d 4441 I915_WRITE(PRB0_HEAD, 0);
673a394b
EA		 4442
4443 /* Initialize the ring. */
4444 I915_WRITE(PRB0_START, obj_priv->gtt_offset);
50aa253d
KP		 4445 head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
4446
4447 /* G45 ring initialization fails to reset head to zero */
4448 if (head != 0) {
4449 DRM_ERROR("Ring head not reset to zero "
4450 "ctl %08x head %08x tail %08x start %08x\n",
4451 I915_READ(PRB0_CTL),
4452 I915_READ(PRB0_HEAD),
4453 I915_READ(PRB0_TAIL),
4454 I915_READ(PRB0_START));
4455 I915_WRITE(PRB0_HEAD, 0);
4456
4457 DRM_ERROR("Ring head forced to zero "
4458 "ctl %08x head %08x tail %08x start %08x\n",
4459 I915_READ(PRB0_CTL),
4460 I915_READ(PRB0_HEAD),
4461 I915_READ(PRB0_TAIL),
4462 I915_READ(PRB0_START));
4463 }
4464
673a394b
EA		 4465 I915_WRITE(PRB0_CTL,
4466 ((obj->size - 4096) & RING_NR_PAGES) |
4467 RING_NO_REPORT |
4468 RING_VALID);
4469
50aa253d
KP		 4470 head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
4471
4472 /* If the head is still not zero, the ring is dead */
4473 if (head != 0) {
4474 DRM_ERROR("Ring initialization failed "
4475 "ctl %08x head %08x tail %08x start %08x\n",
4476 I915_READ(PRB0_CTL),
4477 I915_READ(PRB0_HEAD),
4478 I915_READ(PRB0_TAIL),
4479 I915_READ(PRB0_START));
4480 return -EIO;
4481 }
4482
673a394b 4483 /* Update our cache of the ring state */
79e53945
JB		 4484 if (!drm_core_check_feature(dev, DRIVER_MODESET))
4485 i915_kernel_lost_context(dev);
4486 else {
4487 ring->head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
4488 ring->tail = I915_READ(PRB0_TAIL) & TAIL_ADDR;
4489 ring->space = ring->head - (ring->tail + 8);
4490 if (ring->space < 0)
4491 ring->space += ring->Size;
4492 }
673a394b
EA		 4493
4494 return 0;
4495}
4496
79e53945 4497void
673a394b
EA		 4498i915_gem_cleanup_ringbuffer(struct drm_device *dev)
4499{
4500 drm_i915_private_t *dev_priv = dev->dev_private;
4501
4502 if (dev_priv->ring.ring_obj == NULL)
4503 return;
4504
4505 drm_core_ioremapfree(&dev_priv->ring.map, dev);
4506
4507 i915_gem_object_unpin(dev_priv->ring.ring_obj);
4508 drm_gem_object_unreference(dev_priv->ring.ring_obj);
4509 dev_priv->ring.ring_obj = NULL;
4510 memset(&dev_priv->ring, 0, sizeof(dev_priv->ring));
4511
85a7bb98 4512 i915_gem_cleanup_hws(dev);
673a394b
EA		 4513}
4514
4515int
4516i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
4517 struct drm_file *file_priv)
4518{
4519 drm_i915_private_t *dev_priv = dev->dev_private;
4520 int ret;
4521
79e53945
JB		 4522 if (drm_core_check_feature(dev, DRIVER_MODESET))
4523 return 0;
4524
ba1234d1 4525 if (atomic_read(&dev_priv->mm.wedged)) {
673a394b 4526 DRM_ERROR("Reenabling wedged hardware, good luck\n");
ba1234d1 4527 atomic_set(&dev_priv->mm.wedged, 0);
673a394b
EA		 4528 }
4529
673a394b 4530 mutex_lock(&dev->struct_mutex);
9bb2d6f9
EA		 4531 dev_priv->mm.suspended = 0;
4532
4533 ret = i915_gem_init_ringbuffer(dev);
d816f6ac
WF		 4534 if (ret != 0) {
4535 mutex_unlock(&dev->struct_mutex);
9bb2d6f9 4536 return ret;
d816f6ac 4537 }
9bb2d6f9 4538
5e118f41 4539 spin_lock(&dev_priv->mm.active_list_lock);
673a394b 4540 BUG_ON(!list_empty(&dev_priv->mm.active_list));
5e118f41
CW		 4541 spin_unlock(&dev_priv->mm.active_list_lock);
4542
673a394b
EA		 4543 BUG_ON(!list_empty(&dev_priv->mm.flushing_list));
4544 BUG_ON(!list_empty(&dev_priv->mm.inactive_list));
4545 BUG_ON(!list_empty(&dev_priv->mm.request_list));
673a394b 4546 mutex_unlock(&dev->struct_mutex);
dbb19d30
KH		 4547
4548 drm_irq_install(dev);
4549
673a394b
EA		 4550 return 0;
4551}
4552
4553int
4554i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
4555 struct drm_file *file_priv)
4556{
4557 int ret;
4558
79e53945
JB		 4559 if (drm_core_check_feature(dev, DRIVER_MODESET))
4560 return 0;
4561
673a394b 4562 ret = i915_gem_idle(dev);
dbb19d30
KH		 4563 drm_irq_uninstall(dev);
4564
6dbe2772 4565 return ret;
673a394b
EA		 4566}
4567
4568void
4569i915_gem_lastclose(struct drm_device *dev)
4570{
4571 int ret;
673a394b 4572
e806b495
EA		 4573 if (drm_core_check_feature(dev, DRIVER_MODESET))
4574 return;
4575
6dbe2772
KP		 4576 ret = i915_gem_idle(dev);
4577 if (ret)
4578 DRM_ERROR("failed to idle hardware: %d\n", ret);
673a394b
EA		 4579}
4580
4581void
4582i915_gem_load(struct drm_device *dev)
4583{
b5aa8a0f 4584 int i;
673a394b
EA		 4585 drm_i915_private_t *dev_priv = dev->dev_private;
4586
5e118f41 4587 spin_lock_init(&dev_priv->mm.active_list_lock);
673a394b
EA		 4588 INIT_LIST_HEAD(&dev_priv->mm.active_list);
4589 INIT_LIST_HEAD(&dev_priv->mm.flushing_list);
4590 INIT_LIST_HEAD(&dev_priv->mm.inactive_list);
4591 INIT_LIST_HEAD(&dev_priv->mm.request_list);
a09ba7fa 4592 INIT_LIST_HEAD(&dev_priv->mm.fence_list);
673a394b
EA		 4593 INIT_DELAYED_WORK(&dev_priv->mm.retire_work,
4594 i915_gem_retire_work_handler);
4595 dev_priv->mm.next_gem_seqno = 1;
4596
31169714
CW		 4597 spin_lock(&shrink_list_lock);
4598 list_add(&dev_priv->mm.shrink_list, &shrink_list);
4599 spin_unlock(&shrink_list_lock);
4600
de151cf6
JB		 4601 /* Old X drivers will take 0-2 for front, back, depth buffers */
4602 dev_priv->fence_reg_start = 3;
4603
0f973f27 4604 if (IS_I965G(dev) || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
de151cf6
JB		 4605 dev_priv->num_fence_regs = 16;
4606 else
4607 dev_priv->num_fence_regs = 8;
4608
b5aa8a0f
GH		 4609 /* Initialize fence registers to zero */
4610 if (IS_I965G(dev)) {
4611 for (i = 0; i < 16; i++)
4612 I915_WRITE64(FENCE_REG_965_0 + (i * 8), 0);
4613 } else {
4614 for (i = 0; i < 8; i++)
4615 I915_WRITE(FENCE_REG_830_0 + (i * 4), 0);
4616 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4617 for (i = 0; i < 8; i++)
4618 I915_WRITE(FENCE_REG_945_8 + (i * 4), 0);
4619 }
4620
673a394b
EA		 4621 i915_gem_detect_bit_6_swizzle(dev);
4622}
71acb5eb
DA		 4623
4624/*
4625 * Create a physically contiguous memory object for this object
4626 * e.g. for cursor + overlay regs
4627 */
4628int i915_gem_init_phys_object(struct drm_device *dev,
4629 int id, int size)
4630{
4631 drm_i915_private_t *dev_priv = dev->dev_private;
4632 struct drm_i915_gem_phys_object *phys_obj;
4633 int ret;
4634
4635 if (dev_priv->mm.phys_objs[id - 1] || !size)
4636 return 0;
4637
9a298b2a 4638 phys_obj = kzalloc(sizeof(struct drm_i915_gem_phys_object), GFP_KERNEL);
71acb5eb
DA		 4639 if (!phys_obj)
4640 return -ENOMEM;
4641
4642 phys_obj->id = id;
4643
4644 phys_obj->handle = drm_pci_alloc(dev, size, 0, 0xffffffff);
4645 if (!phys_obj->handle) {
4646 ret = -ENOMEM;
4647 goto kfree_obj;
4648 }
4649#ifdef CONFIG_X86
4650 set_memory_wc((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE);
4651#endif
4652
4653 dev_priv->mm.phys_objs[id - 1] = phys_obj;
4654
4655 return 0;
4656kfree_obj:
9a298b2a 4657 kfree(phys_obj);
71acb5eb
DA		 4658 return ret;
4659}
4660
4661void i915_gem_free_phys_object(struct drm_device *dev, int id)
4662{
4663 drm_i915_private_t *dev_priv = dev->dev_private;
4664 struct drm_i915_gem_phys_object *phys_obj;
4665
4666 if (!dev_priv->mm.phys_objs[id - 1])
4667 return;
4668
4669 phys_obj = dev_priv->mm.phys_objs[id - 1];
4670 if (phys_obj->cur_obj) {
4671 i915_gem_detach_phys_object(dev, phys_obj->cur_obj);
4672 }
4673
4674#ifdef CONFIG_X86
4675 set_memory_wb((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE);
4676#endif
4677 drm_pci_free(dev, phys_obj->handle);
4678 kfree(phys_obj);
4679 dev_priv->mm.phys_objs[id - 1] = NULL;
4680}
4681
4682void i915_gem_free_all_phys_object(struct drm_device *dev)
4683{
4684 int i;
4685
260883c8 4686 for (i = I915_GEM_PHYS_CURSOR_0; i <= I915_MAX_PHYS_OBJECT; i++)
71acb5eb
DA		 4687 i915_gem_free_phys_object(dev, i);
4688}
4689
4690void i915_gem_detach_phys_object(struct drm_device *dev,
4691 struct drm_gem_object *obj)
4692{
4693 struct drm_i915_gem_object *obj_priv;
4694 int i;
4695 int ret;
4696 int page_count;
4697
4698 obj_priv = obj->driver_private;
4699 if (!obj_priv->phys_obj)
4700 return;
4701
856fa198 4702 ret = i915_gem_object_get_pages(obj);
71acb5eb
DA		 4703 if (ret)
4704 goto out;
4705
4706 page_count = obj->size / PAGE_SIZE;
4707
4708 for (i = 0; i < page_count; i++) {
856fa198 4709 char *dst = kmap_atomic(obj_priv->pages[i], KM_USER0);
71acb5eb
DA		 4710 char *src = obj_priv->phys_obj->handle->vaddr + (i * PAGE_SIZE);
4711
4712 memcpy(dst, src, PAGE_SIZE);
4713 kunmap_atomic(dst, KM_USER0);
4714 }
856fa198 4715 drm_clflush_pages(obj_priv->pages, page_count);
71acb5eb 4716 drm_agp_chipset_flush(dev);
d78b47b9
CW		 4717
4718 i915_gem_object_put_pages(obj);
71acb5eb
DA		 4719out:
4720 obj_priv->phys_obj->cur_obj = NULL;
4721 obj_priv->phys_obj = NULL;
4722}
4723
4724int
4725i915_gem_attach_phys_object(struct drm_device *dev,
4726 struct drm_gem_object *obj, int id)
4727{
4728 drm_i915_private_t *dev_priv = dev->dev_private;
4729 struct drm_i915_gem_object *obj_priv;
4730 int ret = 0;
4731 int page_count;
4732 int i;
4733
4734 if (id > I915_MAX_PHYS_OBJECT)
4735 return -EINVAL;
4736
4737 obj_priv = obj->driver_private;
4738
4739 if (obj_priv->phys_obj) {
4740 if (obj_priv->phys_obj->id == id)
4741 return 0;
4742 i915_gem_detach_phys_object(dev, obj);
4743 }
4744
4745
4746 /* create a new object */
4747 if (!dev_priv->mm.phys_objs[id - 1]) {
4748 ret = i915_gem_init_phys_object(dev, id,
4749 obj->size);
4750 if (ret) {
aeb565df 4751 DRM_ERROR("failed to init phys object %d size: %zu\n", id, obj->size);
71acb5eb
DA		 4752 goto out;
4753 }
4754 }
4755
4756 /* bind to the object */
4757 obj_priv->phys_obj = dev_priv->mm.phys_objs[id - 1];
4758 obj_priv->phys_obj->cur_obj = obj;
4759
856fa198 4760 ret = i915_gem_object_get_pages(obj);
71acb5eb
DA		 4761 if (ret) {
4762 DRM_ERROR("failed to get page list\n");
4763 goto out;
4764 }
4765
4766 page_count = obj->size / PAGE_SIZE;
4767
4768 for (i = 0; i < page_count; i++) {
856fa198 4769 char *src = kmap_atomic(obj_priv->pages[i], KM_USER0);
71acb5eb
DA		 4770 char *dst = obj_priv->phys_obj->handle->vaddr + (i * PAGE_SIZE);
4771
4772 memcpy(dst, src, PAGE_SIZE);
4773 kunmap_atomic(src, KM_USER0);
4774 }
4775
d78b47b9
CW		 4776 i915_gem_object_put_pages(obj);
4777
71acb5eb
DA		 4778 return 0;
4779out:
4780 return ret;
4781}
4782
4783static int
4784i915_gem_phys_pwrite(struct drm_device *dev, struct drm_gem_object *obj,
4785 struct drm_i915_gem_pwrite *args,
4786 struct drm_file *file_priv)
4787{
4788 struct drm_i915_gem_object *obj_priv = obj->driver_private;
4789 void *obj_addr;
4790 int ret;
4791 char __user *user_data;
4792
4793 user_data = (char __user *) (uintptr_t) args->data_ptr;
4794 obj_addr = obj_priv->phys_obj->handle->vaddr + args->offset;
4795
e08fb4f6 4796 DRM_DEBUG("obj_addr %p, %lld\n", obj_addr, args->size);
71acb5eb
DA		 4797 ret = copy_from_user(obj_addr, user_data, args->size);
4798 if (ret)
4799 return -EFAULT;
4800
4801 drm_agp_chipset_flush(dev);
4802 return 0;
4803}
b962442e
EA		 4804
4805void i915_gem_release(struct drm_device * dev, struct drm_file *file_priv)
4806{
4807 struct drm_i915_file_private *i915_file_priv = file_priv->driver_priv;
4808
4809 /* Clean up our request list when the client is going away, so that
4810 * later retire_requests won't dereference our soon-to-be-gone
4811 * file_priv.
4812 */
4813 mutex_lock(&dev->struct_mutex);
4814 while (!list_empty(&i915_file_priv->mm.request_list))
4815 list_del_init(i915_file_priv->mm.request_list.next);
4816 mutex_unlock(&dev->struct_mutex);
4817}
31169714 4818
31169714
CW		 4819static int
4820i915_gem_shrink(int nr_to_scan, gfp_t gfp_mask)
4821{
4822 drm_i915_private_t *dev_priv, *next_dev;
4823 struct drm_i915_gem_object *obj_priv, *next_obj;
4824 int cnt = 0;
4825 int would_deadlock = 1;
4826
4827 /* "fast-path" to count number of available objects */
4828 if (nr_to_scan == 0) {
4829 spin_lock(&shrink_list_lock);
4830 list_for_each_entry(dev_priv, &shrink_list, mm.shrink_list) {
4831 struct drm_device *dev = dev_priv->dev;
4832
4833 if (mutex_trylock(&dev->struct_mutex)) {
4834 list_for_each_entry(obj_priv,
4835 &dev_priv->mm.inactive_list,
4836 list)
4837 cnt++;
4838 mutex_unlock(&dev->struct_mutex);
4839 }
4840 }
4841 spin_unlock(&shrink_list_lock);
4842
4843 return (cnt / 100) * sysctl_vfs_cache_pressure;
4844 }
4845
4846 spin_lock(&shrink_list_lock);
4847
4848 /* first scan for clean buffers */
4849 list_for_each_entry_safe(dev_priv, next_dev,
4850 &shrink_list, mm.shrink_list) {
4851 struct drm_device *dev = dev_priv->dev;
4852
4853 if (! mutex_trylock(&dev->struct_mutex))
4854 continue;
4855
4856 spin_unlock(&shrink_list_lock);
4857
4858 i915_gem_retire_requests(dev);
4859
4860 list_for_each_entry_safe(obj_priv, next_obj,
4861 &dev_priv->mm.inactive_list,
4862 list) {
4863 if (i915_gem_object_is_purgeable(obj_priv)) {
963b4836 4864 i915_gem_object_unbind(obj_priv->obj);
31169714
CW		 4865 if (--nr_to_scan <= 0)
4866 break;
4867 }
4868 }
4869
4870 spin_lock(&shrink_list_lock);
4871 mutex_unlock(&dev->struct_mutex);
4872
963b4836
CW		 4873 would_deadlock = 0;
4874
31169714
CW		 4875 if (nr_to_scan <= 0)
4876 break;
4877 }
4878
4879 /* second pass, evict/count anything still on the inactive list */
4880 list_for_each_entry_safe(dev_priv, next_dev,
4881 &shrink_list, mm.shrink_list) {
4882 struct drm_device *dev = dev_priv->dev;
4883
4884 if (! mutex_trylock(&dev->struct_mutex))
4885 continue;
4886
4887 spin_unlock(&shrink_list_lock);
4888
4889 list_for_each_entry_safe(obj_priv, next_obj,
4890 &dev_priv->mm.inactive_list,
4891 list) {
4892 if (nr_to_scan > 0) {
963b4836 4893 i915_gem_object_unbind(obj_priv->obj);
31169714
CW		 4894 nr_to_scan--;
4895 } else
4896 cnt++;
4897 }
4898
4899 spin_lock(&shrink_list_lock);
4900 mutex_unlock(&dev->struct_mutex);
4901
4902 would_deadlock = 0;
4903 }
4904
4905 spin_unlock(&shrink_list_lock);
4906
4907 if (would_deadlock)
4908 return -1;
4909 else if (cnt > 0)
4910 return (cnt / 100) * sysctl_vfs_cache_pressure;
4911 else
4912 return 0;
4913}
4914
4915static struct shrinker shrinker = {
4916 .shrink = i915_gem_shrink,
4917 .seeks = DEFAULT_SEEKS,
4918};
4919
4920__init void
4921i915_gem_shrinker_init(void)
4922{
4923 register_shrinker(&shrinker);
4924}
4925
4926__exit void
4927i915_gem_shrinker_exit(void)
4928{
4929 unregister_shrinker(&shrinker);
4930}
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