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673a394b EA |
1 | /* |
2 | * Copyright © 2008 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | * | |
26 | */ | |
27 | ||
28 | #include "drmP.h" | |
29 | #include "drm.h" | |
30 | #include "i915_drm.h" | |
31 | #include "i915_drv.h" | |
1c5d22f7 | 32 | #include "i915_trace.h" |
652c393a | 33 | #include "intel_drv.h" |
5a0e3ad6 | 34 | #include <linux/slab.h> |
673a394b | 35 | #include <linux/swap.h> |
79e53945 | 36 | #include <linux/pci.h> |
673a394b | 37 | |
0f8c6d7c CW |
38 | struct change_domains { |
39 | uint32_t invalidate_domains; | |
40 | uint32_t flush_domains; | |
41 | uint32_t flush_rings; | |
42 | }; | |
43 | ||
05394f39 | 44 | static int i915_gem_object_flush_gpu_write_domain(struct drm_i915_gem_object *obj, |
919926ae | 45 | struct intel_ring_buffer *pipelined); |
05394f39 CW |
46 | static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj); |
47 | static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj); | |
48 | static int i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, | |
919926ae | 49 | bool write); |
05394f39 | 50 | static int i915_gem_object_set_cpu_read_domain_range(struct drm_i915_gem_object *obj, |
e47c68e9 EA |
51 | uint64_t offset, |
52 | uint64_t size); | |
05394f39 CW |
53 | static void i915_gem_object_set_to_full_cpu_read_domain(struct drm_i915_gem_object *obj); |
54 | static int i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj, | |
2cf34d7b | 55 | bool interruptible); |
05394f39 | 56 | static int i915_gem_object_bind_to_gtt(struct drm_i915_gem_object *obj, |
a00b10c3 | 57 | unsigned alignment, |
75e9e915 | 58 | bool map_and_fenceable); |
05394f39 CW |
59 | static void i915_gem_clear_fence_reg(struct drm_i915_gem_object *obj); |
60 | static int i915_gem_phys_pwrite(struct drm_device *dev, | |
61 | struct drm_i915_gem_object *obj, | |
71acb5eb | 62 | struct drm_i915_gem_pwrite *args, |
05394f39 CW |
63 | struct drm_file *file); |
64 | static void i915_gem_free_object_tail(struct drm_i915_gem_object *obj); | |
673a394b | 65 | |
17250b71 CW |
66 | static int i915_gem_inactive_shrink(struct shrinker *shrinker, |
67 | int nr_to_scan, | |
68 | gfp_t gfp_mask); | |
69 | ||
31169714 | 70 | |
73aa808f CW |
71 | /* some bookkeeping */ |
72 | static void i915_gem_info_add_obj(struct drm_i915_private *dev_priv, | |
73 | size_t size) | |
74 | { | |
75 | dev_priv->mm.object_count++; | |
76 | dev_priv->mm.object_memory += size; | |
77 | } | |
78 | ||
79 | static void i915_gem_info_remove_obj(struct drm_i915_private *dev_priv, | |
80 | size_t size) | |
81 | { | |
82 | dev_priv->mm.object_count--; | |
83 | dev_priv->mm.object_memory -= size; | |
84 | } | |
85 | ||
86 | static void i915_gem_info_add_gtt(struct drm_i915_private *dev_priv, | |
a00b10c3 | 87 | struct drm_i915_gem_object *obj) |
73aa808f CW |
88 | { |
89 | dev_priv->mm.gtt_count++; | |
a00b10c3 CW |
90 | dev_priv->mm.gtt_memory += obj->gtt_space->size; |
91 | if (obj->gtt_offset < dev_priv->mm.gtt_mappable_end) { | |
fb7d516a | 92 | dev_priv->mm.mappable_gtt_used += |
a00b10c3 CW |
93 | min_t(size_t, obj->gtt_space->size, |
94 | dev_priv->mm.gtt_mappable_end - obj->gtt_offset); | |
fb7d516a | 95 | } |
93a37f20 | 96 | list_add_tail(&obj->gtt_list, &dev_priv->mm.gtt_list); |
73aa808f CW |
97 | } |
98 | ||
99 | static void i915_gem_info_remove_gtt(struct drm_i915_private *dev_priv, | |
a00b10c3 | 100 | struct drm_i915_gem_object *obj) |
73aa808f CW |
101 | { |
102 | dev_priv->mm.gtt_count--; | |
a00b10c3 CW |
103 | dev_priv->mm.gtt_memory -= obj->gtt_space->size; |
104 | if (obj->gtt_offset < dev_priv->mm.gtt_mappable_end) { | |
fb7d516a | 105 | dev_priv->mm.mappable_gtt_used -= |
a00b10c3 CW |
106 | min_t(size_t, obj->gtt_space->size, |
107 | dev_priv->mm.gtt_mappable_end - obj->gtt_offset); | |
fb7d516a | 108 | } |
93a37f20 | 109 | list_del_init(&obj->gtt_list); |
fb7d516a DV |
110 | } |
111 | ||
112 | /** | |
113 | * Update the mappable working set counters. Call _only_ when there is a change | |
114 | * in one of (pin|fault)_mappable and update *_mappable _before_ calling. | |
115 | * @mappable: new state the changed mappable flag (either pin_ or fault_). | |
116 | */ | |
117 | static void | |
118 | i915_gem_info_update_mappable(struct drm_i915_private *dev_priv, | |
a00b10c3 | 119 | struct drm_i915_gem_object *obj, |
fb7d516a DV |
120 | bool mappable) |
121 | { | |
fb7d516a | 122 | if (mappable) { |
a00b10c3 | 123 | if (obj->pin_mappable && obj->fault_mappable) |
fb7d516a DV |
124 | /* Combined state was already mappable. */ |
125 | return; | |
126 | dev_priv->mm.gtt_mappable_count++; | |
a00b10c3 | 127 | dev_priv->mm.gtt_mappable_memory += obj->gtt_space->size; |
fb7d516a | 128 | } else { |
a00b10c3 | 129 | if (obj->pin_mappable || obj->fault_mappable) |
fb7d516a DV |
130 | /* Combined state still mappable. */ |
131 | return; | |
132 | dev_priv->mm.gtt_mappable_count--; | |
a00b10c3 | 133 | dev_priv->mm.gtt_mappable_memory -= obj->gtt_space->size; |
fb7d516a | 134 | } |
73aa808f CW |
135 | } |
136 | ||
137 | static void i915_gem_info_add_pin(struct drm_i915_private *dev_priv, | |
a00b10c3 | 138 | struct drm_i915_gem_object *obj, |
fb7d516a | 139 | bool mappable) |
73aa808f CW |
140 | { |
141 | dev_priv->mm.pin_count++; | |
a00b10c3 | 142 | dev_priv->mm.pin_memory += obj->gtt_space->size; |
fb7d516a | 143 | if (mappable) { |
a00b10c3 | 144 | obj->pin_mappable = true; |
fb7d516a DV |
145 | i915_gem_info_update_mappable(dev_priv, obj, true); |
146 | } | |
73aa808f CW |
147 | } |
148 | ||
149 | static void i915_gem_info_remove_pin(struct drm_i915_private *dev_priv, | |
a00b10c3 | 150 | struct drm_i915_gem_object *obj) |
73aa808f CW |
151 | { |
152 | dev_priv->mm.pin_count--; | |
a00b10c3 CW |
153 | dev_priv->mm.pin_memory -= obj->gtt_space->size; |
154 | if (obj->pin_mappable) { | |
155 | obj->pin_mappable = false; | |
fb7d516a DV |
156 | i915_gem_info_update_mappable(dev_priv, obj, false); |
157 | } | |
73aa808f CW |
158 | } |
159 | ||
30dbf0c0 CW |
160 | int |
161 | i915_gem_check_is_wedged(struct drm_device *dev) | |
162 | { | |
163 | struct drm_i915_private *dev_priv = dev->dev_private; | |
164 | struct completion *x = &dev_priv->error_completion; | |
165 | unsigned long flags; | |
166 | int ret; | |
167 | ||
168 | if (!atomic_read(&dev_priv->mm.wedged)) | |
169 | return 0; | |
170 | ||
171 | ret = wait_for_completion_interruptible(x); | |
172 | if (ret) | |
173 | return ret; | |
174 | ||
175 | /* Success, we reset the GPU! */ | |
176 | if (!atomic_read(&dev_priv->mm.wedged)) | |
177 | return 0; | |
178 | ||
179 | /* GPU is hung, bump the completion count to account for | |
180 | * the token we just consumed so that we never hit zero and | |
181 | * end up waiting upon a subsequent completion event that | |
182 | * will never happen. | |
183 | */ | |
184 | spin_lock_irqsave(&x->wait.lock, flags); | |
185 | x->done++; | |
186 | spin_unlock_irqrestore(&x->wait.lock, flags); | |
187 | return -EIO; | |
188 | } | |
189 | ||
76c1dec1 CW |
190 | static int i915_mutex_lock_interruptible(struct drm_device *dev) |
191 | { | |
192 | struct drm_i915_private *dev_priv = dev->dev_private; | |
193 | int ret; | |
194 | ||
195 | ret = i915_gem_check_is_wedged(dev); | |
196 | if (ret) | |
197 | return ret; | |
198 | ||
199 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
200 | if (ret) | |
201 | return ret; | |
202 | ||
203 | if (atomic_read(&dev_priv->mm.wedged)) { | |
204 | mutex_unlock(&dev->struct_mutex); | |
205 | return -EAGAIN; | |
206 | } | |
207 | ||
23bc5982 | 208 | WARN_ON(i915_verify_lists(dev)); |
76c1dec1 CW |
209 | return 0; |
210 | } | |
30dbf0c0 | 211 | |
7d1c4804 | 212 | static inline bool |
05394f39 | 213 | i915_gem_object_is_inactive(struct drm_i915_gem_object *obj) |
7d1c4804 | 214 | { |
05394f39 | 215 | return obj->gtt_space && !obj->active && obj->pin_count == 0; |
7d1c4804 CW |
216 | } |
217 | ||
73aa808f CW |
218 | int i915_gem_do_init(struct drm_device *dev, |
219 | unsigned long start, | |
53984635 | 220 | unsigned long mappable_end, |
79e53945 | 221 | unsigned long end) |
673a394b EA |
222 | { |
223 | drm_i915_private_t *dev_priv = dev->dev_private; | |
673a394b | 224 | |
79e53945 JB |
225 | if (start >= end || |
226 | (start & (PAGE_SIZE - 1)) != 0 || | |
227 | (end & (PAGE_SIZE - 1)) != 0) { | |
673a394b EA |
228 | return -EINVAL; |
229 | } | |
230 | ||
79e53945 JB |
231 | drm_mm_init(&dev_priv->mm.gtt_space, start, |
232 | end - start); | |
673a394b | 233 | |
73aa808f | 234 | dev_priv->mm.gtt_total = end - start; |
fb7d516a | 235 | dev_priv->mm.mappable_gtt_total = min(end, mappable_end) - start; |
53984635 | 236 | dev_priv->mm.gtt_mappable_end = mappable_end; |
79e53945 JB |
237 | |
238 | return 0; | |
239 | } | |
673a394b | 240 | |
79e53945 JB |
241 | int |
242 | i915_gem_init_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 243 | struct drm_file *file) |
79e53945 JB |
244 | { |
245 | struct drm_i915_gem_init *args = data; | |
246 | int ret; | |
247 | ||
248 | mutex_lock(&dev->struct_mutex); | |
53984635 | 249 | ret = i915_gem_do_init(dev, args->gtt_start, args->gtt_end, args->gtt_end); |
673a394b EA |
250 | mutex_unlock(&dev->struct_mutex); |
251 | ||
79e53945 | 252 | return ret; |
673a394b EA |
253 | } |
254 | ||
5a125c3c EA |
255 | int |
256 | i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 257 | struct drm_file *file) |
5a125c3c | 258 | { |
73aa808f | 259 | struct drm_i915_private *dev_priv = dev->dev_private; |
5a125c3c | 260 | struct drm_i915_gem_get_aperture *args = data; |
5a125c3c EA |
261 | |
262 | if (!(dev->driver->driver_features & DRIVER_GEM)) | |
263 | return -ENODEV; | |
264 | ||
73aa808f CW |
265 | mutex_lock(&dev->struct_mutex); |
266 | args->aper_size = dev_priv->mm.gtt_total; | |
267 | args->aper_available_size = args->aper_size - dev_priv->mm.pin_memory; | |
268 | mutex_unlock(&dev->struct_mutex); | |
5a125c3c EA |
269 | |
270 | return 0; | |
271 | } | |
272 | ||
673a394b EA |
273 | |
274 | /** | |
275 | * Creates a new mm object and returns a handle to it. | |
276 | */ | |
277 | int | |
278 | i915_gem_create_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 279 | struct drm_file *file) |
673a394b EA |
280 | { |
281 | struct drm_i915_gem_create *args = data; | |
05394f39 | 282 | struct drm_i915_gem_object *obj; |
a1a2d1d3 PP |
283 | int ret; |
284 | u32 handle; | |
673a394b EA |
285 | |
286 | args->size = roundup(args->size, PAGE_SIZE); | |
287 | ||
288 | /* Allocate the new object */ | |
ac52bc56 | 289 | obj = i915_gem_alloc_object(dev, args->size); |
673a394b EA |
290 | if (obj == NULL) |
291 | return -ENOMEM; | |
292 | ||
05394f39 | 293 | ret = drm_gem_handle_create(file, &obj->base, &handle); |
1dfd9754 | 294 | if (ret) { |
05394f39 CW |
295 | drm_gem_object_release(&obj->base); |
296 | i915_gem_info_remove_obj(dev->dev_private, obj->base.size); | |
202f2fef | 297 | kfree(obj); |
673a394b | 298 | return ret; |
1dfd9754 | 299 | } |
673a394b | 300 | |
202f2fef | 301 | /* drop reference from allocate - handle holds it now */ |
05394f39 | 302 | drm_gem_object_unreference(&obj->base); |
202f2fef CW |
303 | trace_i915_gem_object_create(obj); |
304 | ||
1dfd9754 | 305 | args->handle = handle; |
673a394b EA |
306 | return 0; |
307 | } | |
308 | ||
05394f39 | 309 | static int i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj) |
280b713b | 310 | { |
05394f39 | 311 | drm_i915_private_t *dev_priv = obj->base.dev->dev_private; |
280b713b EA |
312 | |
313 | return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 && | |
05394f39 | 314 | obj->tiling_mode != I915_TILING_NONE; |
280b713b EA |
315 | } |
316 | ||
99a03df5 | 317 | static inline void |
40123c1f EA |
318 | slow_shmem_copy(struct page *dst_page, |
319 | int dst_offset, | |
320 | struct page *src_page, | |
321 | int src_offset, | |
322 | int length) | |
323 | { | |
324 | char *dst_vaddr, *src_vaddr; | |
325 | ||
99a03df5 CW |
326 | dst_vaddr = kmap(dst_page); |
327 | src_vaddr = kmap(src_page); | |
40123c1f EA |
328 | |
329 | memcpy(dst_vaddr + dst_offset, src_vaddr + src_offset, length); | |
330 | ||
99a03df5 CW |
331 | kunmap(src_page); |
332 | kunmap(dst_page); | |
40123c1f EA |
333 | } |
334 | ||
99a03df5 | 335 | static inline void |
280b713b EA |
336 | slow_shmem_bit17_copy(struct page *gpu_page, |
337 | int gpu_offset, | |
338 | struct page *cpu_page, | |
339 | int cpu_offset, | |
340 | int length, | |
341 | int is_read) | |
342 | { | |
343 | char *gpu_vaddr, *cpu_vaddr; | |
344 | ||
345 | /* Use the unswizzled path if this page isn't affected. */ | |
346 | if ((page_to_phys(gpu_page) & (1 << 17)) == 0) { | |
347 | if (is_read) | |
348 | return slow_shmem_copy(cpu_page, cpu_offset, | |
349 | gpu_page, gpu_offset, length); | |
350 | else | |
351 | return slow_shmem_copy(gpu_page, gpu_offset, | |
352 | cpu_page, cpu_offset, length); | |
353 | } | |
354 | ||
99a03df5 CW |
355 | gpu_vaddr = kmap(gpu_page); |
356 | cpu_vaddr = kmap(cpu_page); | |
280b713b EA |
357 | |
358 | /* Copy the data, XORing A6 with A17 (1). The user already knows he's | |
359 | * XORing with the other bits (A9 for Y, A9 and A10 for X) | |
360 | */ | |
361 | while (length > 0) { | |
362 | int cacheline_end = ALIGN(gpu_offset + 1, 64); | |
363 | int this_length = min(cacheline_end - gpu_offset, length); | |
364 | int swizzled_gpu_offset = gpu_offset ^ 64; | |
365 | ||
366 | if (is_read) { | |
367 | memcpy(cpu_vaddr + cpu_offset, | |
368 | gpu_vaddr + swizzled_gpu_offset, | |
369 | this_length); | |
370 | } else { | |
371 | memcpy(gpu_vaddr + swizzled_gpu_offset, | |
372 | cpu_vaddr + cpu_offset, | |
373 | this_length); | |
374 | } | |
375 | cpu_offset += this_length; | |
376 | gpu_offset += this_length; | |
377 | length -= this_length; | |
378 | } | |
379 | ||
99a03df5 CW |
380 | kunmap(cpu_page); |
381 | kunmap(gpu_page); | |
280b713b EA |
382 | } |
383 | ||
eb01459f EA |
384 | /** |
385 | * This is the fast shmem pread path, which attempts to copy_from_user directly | |
386 | * from the backing pages of the object to the user's address space. On a | |
387 | * fault, it fails so we can fall back to i915_gem_shmem_pwrite_slow(). | |
388 | */ | |
389 | static int | |
05394f39 CW |
390 | i915_gem_shmem_pread_fast(struct drm_device *dev, |
391 | struct drm_i915_gem_object *obj, | |
eb01459f | 392 | struct drm_i915_gem_pread *args, |
05394f39 | 393 | struct drm_file *file) |
eb01459f | 394 | { |
05394f39 | 395 | struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping; |
eb01459f | 396 | ssize_t remain; |
e5281ccd | 397 | loff_t offset; |
eb01459f EA |
398 | char __user *user_data; |
399 | int page_offset, page_length; | |
eb01459f EA |
400 | |
401 | user_data = (char __user *) (uintptr_t) args->data_ptr; | |
402 | remain = args->size; | |
403 | ||
eb01459f EA |
404 | offset = args->offset; |
405 | ||
406 | while (remain > 0) { | |
e5281ccd CW |
407 | struct page *page; |
408 | char *vaddr; | |
409 | int ret; | |
410 | ||
eb01459f EA |
411 | /* Operation in this page |
412 | * | |
eb01459f EA |
413 | * page_offset = offset within page |
414 | * page_length = bytes to copy for this page | |
415 | */ | |
eb01459f EA |
416 | page_offset = offset & (PAGE_SIZE-1); |
417 | page_length = remain; | |
418 | if ((page_offset + remain) > PAGE_SIZE) | |
419 | page_length = PAGE_SIZE - page_offset; | |
420 | ||
e5281ccd CW |
421 | page = read_cache_page_gfp(mapping, offset >> PAGE_SHIFT, |
422 | GFP_HIGHUSER | __GFP_RECLAIMABLE); | |
423 | if (IS_ERR(page)) | |
424 | return PTR_ERR(page); | |
425 | ||
426 | vaddr = kmap_atomic(page); | |
427 | ret = __copy_to_user_inatomic(user_data, | |
428 | vaddr + page_offset, | |
429 | page_length); | |
430 | kunmap_atomic(vaddr); | |
431 | ||
432 | mark_page_accessed(page); | |
433 | page_cache_release(page); | |
434 | if (ret) | |
4f27b75d | 435 | return -EFAULT; |
eb01459f EA |
436 | |
437 | remain -= page_length; | |
438 | user_data += page_length; | |
439 | offset += page_length; | |
440 | } | |
441 | ||
4f27b75d | 442 | return 0; |
eb01459f EA |
443 | } |
444 | ||
445 | /** | |
446 | * This is the fallback shmem pread path, which allocates temporary storage | |
447 | * in kernel space to copy_to_user into outside of the struct_mutex, so we | |
448 | * can copy out of the object's backing pages while holding the struct mutex | |
449 | * and not take page faults. | |
450 | */ | |
451 | static int | |
05394f39 CW |
452 | i915_gem_shmem_pread_slow(struct drm_device *dev, |
453 | struct drm_i915_gem_object *obj, | |
eb01459f | 454 | struct drm_i915_gem_pread *args, |
05394f39 | 455 | struct drm_file *file) |
eb01459f | 456 | { |
05394f39 | 457 | struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping; |
eb01459f EA |
458 | struct mm_struct *mm = current->mm; |
459 | struct page **user_pages; | |
460 | ssize_t remain; | |
461 | loff_t offset, pinned_pages, i; | |
462 | loff_t first_data_page, last_data_page, num_pages; | |
e5281ccd CW |
463 | int shmem_page_offset; |
464 | int data_page_index, data_page_offset; | |
eb01459f EA |
465 | int page_length; |
466 | int ret; | |
467 | uint64_t data_ptr = args->data_ptr; | |
280b713b | 468 | int do_bit17_swizzling; |
eb01459f EA |
469 | |
470 | remain = args->size; | |
471 | ||
472 | /* Pin the user pages containing the data. We can't fault while | |
473 | * holding the struct mutex, yet we want to hold it while | |
474 | * dereferencing the user data. | |
475 | */ | |
476 | first_data_page = data_ptr / PAGE_SIZE; | |
477 | last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE; | |
478 | num_pages = last_data_page - first_data_page + 1; | |
479 | ||
4f27b75d | 480 | user_pages = drm_malloc_ab(num_pages, sizeof(struct page *)); |
eb01459f EA |
481 | if (user_pages == NULL) |
482 | return -ENOMEM; | |
483 | ||
4f27b75d | 484 | mutex_unlock(&dev->struct_mutex); |
eb01459f EA |
485 | down_read(&mm->mmap_sem); |
486 | pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr, | |
e5e9ecde | 487 | num_pages, 1, 0, user_pages, NULL); |
eb01459f | 488 | up_read(&mm->mmap_sem); |
4f27b75d | 489 | mutex_lock(&dev->struct_mutex); |
eb01459f EA |
490 | if (pinned_pages < num_pages) { |
491 | ret = -EFAULT; | |
4f27b75d | 492 | goto out; |
eb01459f EA |
493 | } |
494 | ||
4f27b75d CW |
495 | ret = i915_gem_object_set_cpu_read_domain_range(obj, |
496 | args->offset, | |
497 | args->size); | |
07f73f69 | 498 | if (ret) |
4f27b75d | 499 | goto out; |
eb01459f | 500 | |
4f27b75d | 501 | do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj); |
eb01459f | 502 | |
eb01459f EA |
503 | offset = args->offset; |
504 | ||
505 | while (remain > 0) { | |
e5281ccd CW |
506 | struct page *page; |
507 | ||
eb01459f EA |
508 | /* Operation in this page |
509 | * | |
eb01459f EA |
510 | * shmem_page_offset = offset within page in shmem file |
511 | * data_page_index = page number in get_user_pages return | |
512 | * data_page_offset = offset with data_page_index page. | |
513 | * page_length = bytes to copy for this page | |
514 | */ | |
eb01459f EA |
515 | shmem_page_offset = offset & ~PAGE_MASK; |
516 | data_page_index = data_ptr / PAGE_SIZE - first_data_page; | |
517 | data_page_offset = data_ptr & ~PAGE_MASK; | |
518 | ||
519 | page_length = remain; | |
520 | if ((shmem_page_offset + page_length) > PAGE_SIZE) | |
521 | page_length = PAGE_SIZE - shmem_page_offset; | |
522 | if ((data_page_offset + page_length) > PAGE_SIZE) | |
523 | page_length = PAGE_SIZE - data_page_offset; | |
524 | ||
e5281ccd CW |
525 | page = read_cache_page_gfp(mapping, offset >> PAGE_SHIFT, |
526 | GFP_HIGHUSER | __GFP_RECLAIMABLE); | |
527 | if (IS_ERR(page)) | |
528 | return PTR_ERR(page); | |
529 | ||
280b713b | 530 | if (do_bit17_swizzling) { |
e5281ccd | 531 | slow_shmem_bit17_copy(page, |
280b713b | 532 | shmem_page_offset, |
99a03df5 CW |
533 | user_pages[data_page_index], |
534 | data_page_offset, | |
535 | page_length, | |
536 | 1); | |
537 | } else { | |
538 | slow_shmem_copy(user_pages[data_page_index], | |
539 | data_page_offset, | |
e5281ccd | 540 | page, |
99a03df5 CW |
541 | shmem_page_offset, |
542 | page_length); | |
280b713b | 543 | } |
eb01459f | 544 | |
e5281ccd CW |
545 | mark_page_accessed(page); |
546 | page_cache_release(page); | |
547 | ||
eb01459f EA |
548 | remain -= page_length; |
549 | data_ptr += page_length; | |
550 | offset += page_length; | |
551 | } | |
552 | ||
4f27b75d | 553 | out: |
eb01459f EA |
554 | for (i = 0; i < pinned_pages; i++) { |
555 | SetPageDirty(user_pages[i]); | |
e5281ccd | 556 | mark_page_accessed(user_pages[i]); |
eb01459f EA |
557 | page_cache_release(user_pages[i]); |
558 | } | |
8e7d2b2c | 559 | drm_free_large(user_pages); |
eb01459f EA |
560 | |
561 | return ret; | |
562 | } | |
563 | ||
673a394b EA |
564 | /** |
565 | * Reads data from the object referenced by handle. | |
566 | * | |
567 | * On error, the contents of *data are undefined. | |
568 | */ | |
569 | int | |
570 | i915_gem_pread_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 571 | struct drm_file *file) |
673a394b EA |
572 | { |
573 | struct drm_i915_gem_pread *args = data; | |
05394f39 | 574 | struct drm_i915_gem_object *obj; |
35b62a89 | 575 | int ret = 0; |
673a394b | 576 | |
51311d0a CW |
577 | if (args->size == 0) |
578 | return 0; | |
579 | ||
580 | if (!access_ok(VERIFY_WRITE, | |
581 | (char __user *)(uintptr_t)args->data_ptr, | |
582 | args->size)) | |
583 | return -EFAULT; | |
584 | ||
585 | ret = fault_in_pages_writeable((char __user *)(uintptr_t)args->data_ptr, | |
586 | args->size); | |
587 | if (ret) | |
588 | return -EFAULT; | |
589 | ||
4f27b75d | 590 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 591 | if (ret) |
4f27b75d | 592 | return ret; |
673a394b | 593 | |
05394f39 | 594 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
1d7cfea1 CW |
595 | if (obj == NULL) { |
596 | ret = -ENOENT; | |
597 | goto unlock; | |
4f27b75d | 598 | } |
673a394b | 599 | |
7dcd2499 | 600 | /* Bounds check source. */ |
05394f39 CW |
601 | if (args->offset > obj->base.size || |
602 | args->size > obj->base.size - args->offset) { | |
ce9d419d | 603 | ret = -EINVAL; |
35b62a89 | 604 | goto out; |
ce9d419d CW |
605 | } |
606 | ||
4f27b75d CW |
607 | ret = i915_gem_object_set_cpu_read_domain_range(obj, |
608 | args->offset, | |
609 | args->size); | |
610 | if (ret) | |
e5281ccd | 611 | goto out; |
4f27b75d CW |
612 | |
613 | ret = -EFAULT; | |
614 | if (!i915_gem_object_needs_bit17_swizzle(obj)) | |
05394f39 | 615 | ret = i915_gem_shmem_pread_fast(dev, obj, args, file); |
4f27b75d | 616 | if (ret == -EFAULT) |
05394f39 | 617 | ret = i915_gem_shmem_pread_slow(dev, obj, args, file); |
673a394b | 618 | |
35b62a89 | 619 | out: |
05394f39 | 620 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 621 | unlock: |
4f27b75d | 622 | mutex_unlock(&dev->struct_mutex); |
eb01459f | 623 | return ret; |
673a394b EA |
624 | } |
625 | ||
0839ccb8 KP |
626 | /* This is the fast write path which cannot handle |
627 | * page faults in the source data | |
9b7530cc | 628 | */ |
0839ccb8 KP |
629 | |
630 | static inline int | |
631 | fast_user_write(struct io_mapping *mapping, | |
632 | loff_t page_base, int page_offset, | |
633 | char __user *user_data, | |
634 | int length) | |
9b7530cc | 635 | { |
9b7530cc | 636 | char *vaddr_atomic; |
0839ccb8 | 637 | unsigned long unwritten; |
9b7530cc | 638 | |
3e4d3af5 | 639 | vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base); |
0839ccb8 KP |
640 | unwritten = __copy_from_user_inatomic_nocache(vaddr_atomic + page_offset, |
641 | user_data, length); | |
3e4d3af5 | 642 | io_mapping_unmap_atomic(vaddr_atomic); |
fbd5a26d | 643 | return unwritten; |
0839ccb8 KP |
644 | } |
645 | ||
646 | /* Here's the write path which can sleep for | |
647 | * page faults | |
648 | */ | |
649 | ||
ab34c226 | 650 | static inline void |
3de09aa3 EA |
651 | slow_kernel_write(struct io_mapping *mapping, |
652 | loff_t gtt_base, int gtt_offset, | |
653 | struct page *user_page, int user_offset, | |
654 | int length) | |
0839ccb8 | 655 | { |
ab34c226 CW |
656 | char __iomem *dst_vaddr; |
657 | char *src_vaddr; | |
0839ccb8 | 658 | |
ab34c226 CW |
659 | dst_vaddr = io_mapping_map_wc(mapping, gtt_base); |
660 | src_vaddr = kmap(user_page); | |
661 | ||
662 | memcpy_toio(dst_vaddr + gtt_offset, | |
663 | src_vaddr + user_offset, | |
664 | length); | |
665 | ||
666 | kunmap(user_page); | |
667 | io_mapping_unmap(dst_vaddr); | |
9b7530cc LT |
668 | } |
669 | ||
3de09aa3 EA |
670 | /** |
671 | * This is the fast pwrite path, where we copy the data directly from the | |
672 | * user into the GTT, uncached. | |
673 | */ | |
673a394b | 674 | static int |
05394f39 CW |
675 | i915_gem_gtt_pwrite_fast(struct drm_device *dev, |
676 | struct drm_i915_gem_object *obj, | |
3de09aa3 | 677 | struct drm_i915_gem_pwrite *args, |
05394f39 | 678 | struct drm_file *file) |
673a394b | 679 | { |
0839ccb8 | 680 | drm_i915_private_t *dev_priv = dev->dev_private; |
673a394b | 681 | ssize_t remain; |
0839ccb8 | 682 | loff_t offset, page_base; |
673a394b | 683 | char __user *user_data; |
0839ccb8 | 684 | int page_offset, page_length; |
673a394b EA |
685 | |
686 | user_data = (char __user *) (uintptr_t) args->data_ptr; | |
687 | remain = args->size; | |
673a394b | 688 | |
05394f39 | 689 | offset = obj->gtt_offset + args->offset; |
673a394b EA |
690 | |
691 | while (remain > 0) { | |
692 | /* Operation in this page | |
693 | * | |
0839ccb8 KP |
694 | * page_base = page offset within aperture |
695 | * page_offset = offset within page | |
696 | * page_length = bytes to copy for this page | |
673a394b | 697 | */ |
0839ccb8 KP |
698 | page_base = (offset & ~(PAGE_SIZE-1)); |
699 | page_offset = offset & (PAGE_SIZE-1); | |
700 | page_length = remain; | |
701 | if ((page_offset + remain) > PAGE_SIZE) | |
702 | page_length = PAGE_SIZE - page_offset; | |
703 | ||
0839ccb8 | 704 | /* If we get a fault while copying data, then (presumably) our |
3de09aa3 EA |
705 | * source page isn't available. Return the error and we'll |
706 | * retry in the slow path. | |
0839ccb8 | 707 | */ |
fbd5a26d CW |
708 | if (fast_user_write(dev_priv->mm.gtt_mapping, page_base, |
709 | page_offset, user_data, page_length)) | |
710 | ||
711 | return -EFAULT; | |
673a394b | 712 | |
0839ccb8 KP |
713 | remain -= page_length; |
714 | user_data += page_length; | |
715 | offset += page_length; | |
673a394b | 716 | } |
673a394b | 717 | |
fbd5a26d | 718 | return 0; |
673a394b EA |
719 | } |
720 | ||
3de09aa3 EA |
721 | /** |
722 | * This is the fallback GTT pwrite path, which uses get_user_pages to pin | |
723 | * the memory and maps it using kmap_atomic for copying. | |
724 | * | |
725 | * This code resulted in x11perf -rgb10text consuming about 10% more CPU | |
726 | * than using i915_gem_gtt_pwrite_fast on a G45 (32-bit). | |
727 | */ | |
3043c60c | 728 | static int |
05394f39 CW |
729 | i915_gem_gtt_pwrite_slow(struct drm_device *dev, |
730 | struct drm_i915_gem_object *obj, | |
3de09aa3 | 731 | struct drm_i915_gem_pwrite *args, |
05394f39 | 732 | struct drm_file *file) |
673a394b | 733 | { |
3de09aa3 EA |
734 | drm_i915_private_t *dev_priv = dev->dev_private; |
735 | ssize_t remain; | |
736 | loff_t gtt_page_base, offset; | |
737 | loff_t first_data_page, last_data_page, num_pages; | |
738 | loff_t pinned_pages, i; | |
739 | struct page **user_pages; | |
740 | struct mm_struct *mm = current->mm; | |
741 | int gtt_page_offset, data_page_offset, data_page_index, page_length; | |
673a394b | 742 | int ret; |
3de09aa3 EA |
743 | uint64_t data_ptr = args->data_ptr; |
744 | ||
745 | remain = args->size; | |
746 | ||
747 | /* Pin the user pages containing the data. We can't fault while | |
748 | * holding the struct mutex, and all of the pwrite implementations | |
749 | * want to hold it while dereferencing the user data. | |
750 | */ | |
751 | first_data_page = data_ptr / PAGE_SIZE; | |
752 | last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE; | |
753 | num_pages = last_data_page - first_data_page + 1; | |
754 | ||
fbd5a26d | 755 | user_pages = drm_malloc_ab(num_pages, sizeof(struct page *)); |
3de09aa3 EA |
756 | if (user_pages == NULL) |
757 | return -ENOMEM; | |
758 | ||
fbd5a26d | 759 | mutex_unlock(&dev->struct_mutex); |
3de09aa3 EA |
760 | down_read(&mm->mmap_sem); |
761 | pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr, | |
762 | num_pages, 0, 0, user_pages, NULL); | |
763 | up_read(&mm->mmap_sem); | |
fbd5a26d | 764 | mutex_lock(&dev->struct_mutex); |
3de09aa3 EA |
765 | if (pinned_pages < num_pages) { |
766 | ret = -EFAULT; | |
767 | goto out_unpin_pages; | |
768 | } | |
673a394b | 769 | |
3de09aa3 EA |
770 | ret = i915_gem_object_set_to_gtt_domain(obj, 1); |
771 | if (ret) | |
fbd5a26d | 772 | goto out_unpin_pages; |
3de09aa3 | 773 | |
05394f39 | 774 | offset = obj->gtt_offset + args->offset; |
3de09aa3 EA |
775 | |
776 | while (remain > 0) { | |
777 | /* Operation in this page | |
778 | * | |
779 | * gtt_page_base = page offset within aperture | |
780 | * gtt_page_offset = offset within page in aperture | |
781 | * data_page_index = page number in get_user_pages return | |
782 | * data_page_offset = offset with data_page_index page. | |
783 | * page_length = bytes to copy for this page | |
784 | */ | |
785 | gtt_page_base = offset & PAGE_MASK; | |
786 | gtt_page_offset = offset & ~PAGE_MASK; | |
787 | data_page_index = data_ptr / PAGE_SIZE - first_data_page; | |
788 | data_page_offset = data_ptr & ~PAGE_MASK; | |
789 | ||
790 | page_length = remain; | |
791 | if ((gtt_page_offset + page_length) > PAGE_SIZE) | |
792 | page_length = PAGE_SIZE - gtt_page_offset; | |
793 | if ((data_page_offset + page_length) > PAGE_SIZE) | |
794 | page_length = PAGE_SIZE - data_page_offset; | |
795 | ||
ab34c226 CW |
796 | slow_kernel_write(dev_priv->mm.gtt_mapping, |
797 | gtt_page_base, gtt_page_offset, | |
798 | user_pages[data_page_index], | |
799 | data_page_offset, | |
800 | page_length); | |
3de09aa3 EA |
801 | |
802 | remain -= page_length; | |
803 | offset += page_length; | |
804 | data_ptr += page_length; | |
805 | } | |
806 | ||
3de09aa3 EA |
807 | out_unpin_pages: |
808 | for (i = 0; i < pinned_pages; i++) | |
809 | page_cache_release(user_pages[i]); | |
8e7d2b2c | 810 | drm_free_large(user_pages); |
3de09aa3 EA |
811 | |
812 | return ret; | |
813 | } | |
814 | ||
40123c1f EA |
815 | /** |
816 | * This is the fast shmem pwrite path, which attempts to directly | |
817 | * copy_from_user into the kmapped pages backing the object. | |
818 | */ | |
3043c60c | 819 | static int |
05394f39 CW |
820 | i915_gem_shmem_pwrite_fast(struct drm_device *dev, |
821 | struct drm_i915_gem_object *obj, | |
40123c1f | 822 | struct drm_i915_gem_pwrite *args, |
05394f39 | 823 | struct drm_file *file) |
673a394b | 824 | { |
05394f39 | 825 | struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping; |
40123c1f | 826 | ssize_t remain; |
e5281ccd | 827 | loff_t offset; |
40123c1f EA |
828 | char __user *user_data; |
829 | int page_offset, page_length; | |
40123c1f EA |
830 | |
831 | user_data = (char __user *) (uintptr_t) args->data_ptr; | |
832 | remain = args->size; | |
673a394b | 833 | |
40123c1f | 834 | offset = args->offset; |
05394f39 | 835 | obj->dirty = 1; |
40123c1f EA |
836 | |
837 | while (remain > 0) { | |
e5281ccd CW |
838 | struct page *page; |
839 | char *vaddr; | |
840 | int ret; | |
841 | ||
40123c1f EA |
842 | /* Operation in this page |
843 | * | |
40123c1f EA |
844 | * page_offset = offset within page |
845 | * page_length = bytes to copy for this page | |
846 | */ | |
40123c1f EA |
847 | page_offset = offset & (PAGE_SIZE-1); |
848 | page_length = remain; | |
849 | if ((page_offset + remain) > PAGE_SIZE) | |
850 | page_length = PAGE_SIZE - page_offset; | |
851 | ||
e5281ccd CW |
852 | page = read_cache_page_gfp(mapping, offset >> PAGE_SHIFT, |
853 | GFP_HIGHUSER | __GFP_RECLAIMABLE); | |
854 | if (IS_ERR(page)) | |
855 | return PTR_ERR(page); | |
856 | ||
857 | vaddr = kmap_atomic(page, KM_USER0); | |
858 | ret = __copy_from_user_inatomic(vaddr + page_offset, | |
859 | user_data, | |
860 | page_length); | |
861 | kunmap_atomic(vaddr, KM_USER0); | |
862 | ||
863 | set_page_dirty(page); | |
864 | mark_page_accessed(page); | |
865 | page_cache_release(page); | |
866 | ||
867 | /* If we get a fault while copying data, then (presumably) our | |
868 | * source page isn't available. Return the error and we'll | |
869 | * retry in the slow path. | |
870 | */ | |
871 | if (ret) | |
fbd5a26d | 872 | return -EFAULT; |
40123c1f EA |
873 | |
874 | remain -= page_length; | |
875 | user_data += page_length; | |
876 | offset += page_length; | |
877 | } | |
878 | ||
fbd5a26d | 879 | return 0; |
40123c1f EA |
880 | } |
881 | ||
882 | /** | |
883 | * This is the fallback shmem pwrite path, which uses get_user_pages to pin | |
884 | * the memory and maps it using kmap_atomic for copying. | |
885 | * | |
886 | * This avoids taking mmap_sem for faulting on the user's address while the | |
887 | * struct_mutex is held. | |
888 | */ | |
889 | static int | |
05394f39 CW |
890 | i915_gem_shmem_pwrite_slow(struct drm_device *dev, |
891 | struct drm_i915_gem_object *obj, | |
40123c1f | 892 | struct drm_i915_gem_pwrite *args, |
05394f39 | 893 | struct drm_file *file) |
40123c1f | 894 | { |
05394f39 | 895 | struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping; |
40123c1f EA |
896 | struct mm_struct *mm = current->mm; |
897 | struct page **user_pages; | |
898 | ssize_t remain; | |
899 | loff_t offset, pinned_pages, i; | |
900 | loff_t first_data_page, last_data_page, num_pages; | |
e5281ccd | 901 | int shmem_page_offset; |
40123c1f EA |
902 | int data_page_index, data_page_offset; |
903 | int page_length; | |
904 | int ret; | |
905 | uint64_t data_ptr = args->data_ptr; | |
280b713b | 906 | int do_bit17_swizzling; |
40123c1f EA |
907 | |
908 | remain = args->size; | |
909 | ||
910 | /* Pin the user pages containing the data. We can't fault while | |
911 | * holding the struct mutex, and all of the pwrite implementations | |
912 | * want to hold it while dereferencing the user data. | |
913 | */ | |
914 | first_data_page = data_ptr / PAGE_SIZE; | |
915 | last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE; | |
916 | num_pages = last_data_page - first_data_page + 1; | |
917 | ||
4f27b75d | 918 | user_pages = drm_malloc_ab(num_pages, sizeof(struct page *)); |
40123c1f EA |
919 | if (user_pages == NULL) |
920 | return -ENOMEM; | |
921 | ||
fbd5a26d | 922 | mutex_unlock(&dev->struct_mutex); |
40123c1f EA |
923 | down_read(&mm->mmap_sem); |
924 | pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr, | |
925 | num_pages, 0, 0, user_pages, NULL); | |
926 | up_read(&mm->mmap_sem); | |
fbd5a26d | 927 | mutex_lock(&dev->struct_mutex); |
40123c1f EA |
928 | if (pinned_pages < num_pages) { |
929 | ret = -EFAULT; | |
fbd5a26d | 930 | goto out; |
673a394b EA |
931 | } |
932 | ||
fbd5a26d | 933 | ret = i915_gem_object_set_to_cpu_domain(obj, 1); |
07f73f69 | 934 | if (ret) |
fbd5a26d | 935 | goto out; |
40123c1f | 936 | |
fbd5a26d | 937 | do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj); |
40123c1f | 938 | |
673a394b | 939 | offset = args->offset; |
05394f39 | 940 | obj->dirty = 1; |
673a394b | 941 | |
40123c1f | 942 | while (remain > 0) { |
e5281ccd CW |
943 | struct page *page; |
944 | ||
40123c1f EA |
945 | /* Operation in this page |
946 | * | |
40123c1f EA |
947 | * shmem_page_offset = offset within page in shmem file |
948 | * data_page_index = page number in get_user_pages return | |
949 | * data_page_offset = offset with data_page_index page. | |
950 | * page_length = bytes to copy for this page | |
951 | */ | |
40123c1f EA |
952 | shmem_page_offset = offset & ~PAGE_MASK; |
953 | data_page_index = data_ptr / PAGE_SIZE - first_data_page; | |
954 | data_page_offset = data_ptr & ~PAGE_MASK; | |
955 | ||
956 | page_length = remain; | |
957 | if ((shmem_page_offset + page_length) > PAGE_SIZE) | |
958 | page_length = PAGE_SIZE - shmem_page_offset; | |
959 | if ((data_page_offset + page_length) > PAGE_SIZE) | |
960 | page_length = PAGE_SIZE - data_page_offset; | |
961 | ||
e5281ccd CW |
962 | page = read_cache_page_gfp(mapping, offset >> PAGE_SHIFT, |
963 | GFP_HIGHUSER | __GFP_RECLAIMABLE); | |
964 | if (IS_ERR(page)) { | |
965 | ret = PTR_ERR(page); | |
966 | goto out; | |
967 | } | |
968 | ||
280b713b | 969 | if (do_bit17_swizzling) { |
e5281ccd | 970 | slow_shmem_bit17_copy(page, |
280b713b EA |
971 | shmem_page_offset, |
972 | user_pages[data_page_index], | |
973 | data_page_offset, | |
99a03df5 CW |
974 | page_length, |
975 | 0); | |
976 | } else { | |
e5281ccd | 977 | slow_shmem_copy(page, |
99a03df5 CW |
978 | shmem_page_offset, |
979 | user_pages[data_page_index], | |
980 | data_page_offset, | |
981 | page_length); | |
280b713b | 982 | } |
40123c1f | 983 | |
e5281ccd CW |
984 | set_page_dirty(page); |
985 | mark_page_accessed(page); | |
986 | page_cache_release(page); | |
987 | ||
40123c1f EA |
988 | remain -= page_length; |
989 | data_ptr += page_length; | |
990 | offset += page_length; | |
673a394b EA |
991 | } |
992 | ||
fbd5a26d | 993 | out: |
40123c1f EA |
994 | for (i = 0; i < pinned_pages; i++) |
995 | page_cache_release(user_pages[i]); | |
8e7d2b2c | 996 | drm_free_large(user_pages); |
673a394b | 997 | |
40123c1f | 998 | return ret; |
673a394b EA |
999 | } |
1000 | ||
1001 | /** | |
1002 | * Writes data to the object referenced by handle. | |
1003 | * | |
1004 | * On error, the contents of the buffer that were to be modified are undefined. | |
1005 | */ | |
1006 | int | |
1007 | i915_gem_pwrite_ioctl(struct drm_device *dev, void *data, | |
fbd5a26d | 1008 | struct drm_file *file) |
673a394b EA |
1009 | { |
1010 | struct drm_i915_gem_pwrite *args = data; | |
05394f39 | 1011 | struct drm_i915_gem_object *obj; |
51311d0a CW |
1012 | int ret; |
1013 | ||
1014 | if (args->size == 0) | |
1015 | return 0; | |
1016 | ||
1017 | if (!access_ok(VERIFY_READ, | |
1018 | (char __user *)(uintptr_t)args->data_ptr, | |
1019 | args->size)) | |
1020 | return -EFAULT; | |
1021 | ||
1022 | ret = fault_in_pages_readable((char __user *)(uintptr_t)args->data_ptr, | |
1023 | args->size); | |
1024 | if (ret) | |
1025 | return -EFAULT; | |
673a394b | 1026 | |
fbd5a26d | 1027 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 1028 | if (ret) |
fbd5a26d | 1029 | return ret; |
1d7cfea1 | 1030 | |
05394f39 | 1031 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
1d7cfea1 CW |
1032 | if (obj == NULL) { |
1033 | ret = -ENOENT; | |
1034 | goto unlock; | |
fbd5a26d | 1035 | } |
673a394b | 1036 | |
7dcd2499 | 1037 | /* Bounds check destination. */ |
05394f39 CW |
1038 | if (args->offset > obj->base.size || |
1039 | args->size > obj->base.size - args->offset) { | |
ce9d419d | 1040 | ret = -EINVAL; |
35b62a89 | 1041 | goto out; |
ce9d419d CW |
1042 | } |
1043 | ||
673a394b EA |
1044 | /* We can only do the GTT pwrite on untiled buffers, as otherwise |
1045 | * it would end up going through the fenced access, and we'll get | |
1046 | * different detiling behavior between reading and writing. | |
1047 | * pread/pwrite currently are reading and writing from the CPU | |
1048 | * perspective, requiring manual detiling by the client. | |
1049 | */ | |
05394f39 | 1050 | if (obj->phys_obj) |
fbd5a26d | 1051 | ret = i915_gem_phys_pwrite(dev, obj, args, file); |
05394f39 CW |
1052 | else if (obj->tiling_mode == I915_TILING_NONE && |
1053 | obj->gtt_space && | |
1054 | obj->base.write_domain != I915_GEM_DOMAIN_CPU) { | |
75e9e915 | 1055 | ret = i915_gem_object_pin(obj, 0, true); |
fbd5a26d CW |
1056 | if (ret) |
1057 | goto out; | |
1058 | ||
1059 | ret = i915_gem_object_set_to_gtt_domain(obj, 1); | |
1060 | if (ret) | |
1061 | goto out_unpin; | |
1062 | ||
1063 | ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file); | |
1064 | if (ret == -EFAULT) | |
1065 | ret = i915_gem_gtt_pwrite_slow(dev, obj, args, file); | |
1066 | ||
1067 | out_unpin: | |
1068 | i915_gem_object_unpin(obj); | |
40123c1f | 1069 | } else { |
fbd5a26d CW |
1070 | ret = i915_gem_object_set_to_cpu_domain(obj, 1); |
1071 | if (ret) | |
e5281ccd | 1072 | goto out; |
673a394b | 1073 | |
fbd5a26d CW |
1074 | ret = -EFAULT; |
1075 | if (!i915_gem_object_needs_bit17_swizzle(obj)) | |
1076 | ret = i915_gem_shmem_pwrite_fast(dev, obj, args, file); | |
1077 | if (ret == -EFAULT) | |
1078 | ret = i915_gem_shmem_pwrite_slow(dev, obj, args, file); | |
fbd5a26d | 1079 | } |
673a394b | 1080 | |
35b62a89 | 1081 | out: |
05394f39 | 1082 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 1083 | unlock: |
fbd5a26d | 1084 | mutex_unlock(&dev->struct_mutex); |
673a394b EA |
1085 | return ret; |
1086 | } | |
1087 | ||
1088 | /** | |
2ef7eeaa EA |
1089 | * Called when user space prepares to use an object with the CPU, either |
1090 | * through the mmap ioctl's mapping or a GTT mapping. | |
673a394b EA |
1091 | */ |
1092 | int | |
1093 | i915_gem_set_domain_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 1094 | struct drm_file *file) |
673a394b | 1095 | { |
a09ba7fa | 1096 | struct drm_i915_private *dev_priv = dev->dev_private; |
673a394b | 1097 | struct drm_i915_gem_set_domain *args = data; |
05394f39 | 1098 | struct drm_i915_gem_object *obj; |
2ef7eeaa EA |
1099 | uint32_t read_domains = args->read_domains; |
1100 | uint32_t write_domain = args->write_domain; | |
673a394b EA |
1101 | int ret; |
1102 | ||
1103 | if (!(dev->driver->driver_features & DRIVER_GEM)) | |
1104 | return -ENODEV; | |
1105 | ||
2ef7eeaa | 1106 | /* Only handle setting domains to types used by the CPU. */ |
21d509e3 | 1107 | if (write_domain & I915_GEM_GPU_DOMAINS) |
2ef7eeaa EA |
1108 | return -EINVAL; |
1109 | ||
21d509e3 | 1110 | if (read_domains & I915_GEM_GPU_DOMAINS) |
2ef7eeaa EA |
1111 | return -EINVAL; |
1112 | ||
1113 | /* Having something in the write domain implies it's in the read | |
1114 | * domain, and only that read domain. Enforce that in the request. | |
1115 | */ | |
1116 | if (write_domain != 0 && read_domains != write_domain) | |
1117 | return -EINVAL; | |
1118 | ||
76c1dec1 | 1119 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 1120 | if (ret) |
76c1dec1 | 1121 | return ret; |
1d7cfea1 | 1122 | |
05394f39 | 1123 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
1d7cfea1 CW |
1124 | if (obj == NULL) { |
1125 | ret = -ENOENT; | |
1126 | goto unlock; | |
76c1dec1 | 1127 | } |
673a394b | 1128 | |
652c393a JB |
1129 | intel_mark_busy(dev, obj); |
1130 | ||
2ef7eeaa EA |
1131 | if (read_domains & I915_GEM_DOMAIN_GTT) { |
1132 | ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0); | |
02354392 | 1133 | |
a09ba7fa EA |
1134 | /* Update the LRU on the fence for the CPU access that's |
1135 | * about to occur. | |
1136 | */ | |
05394f39 | 1137 | if (obj->fence_reg != I915_FENCE_REG_NONE) { |
007cc8ac | 1138 | struct drm_i915_fence_reg *reg = |
05394f39 | 1139 | &dev_priv->fence_regs[obj->fence_reg]; |
007cc8ac | 1140 | list_move_tail(®->lru_list, |
a09ba7fa EA |
1141 | &dev_priv->mm.fence_list); |
1142 | } | |
1143 | ||
02354392 EA |
1144 | /* Silently promote "you're not bound, there was nothing to do" |
1145 | * to success, since the client was just asking us to | |
1146 | * make sure everything was done. | |
1147 | */ | |
1148 | if (ret == -EINVAL) | |
1149 | ret = 0; | |
2ef7eeaa | 1150 | } else { |
e47c68e9 | 1151 | ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0); |
2ef7eeaa EA |
1152 | } |
1153 | ||
7d1c4804 | 1154 | /* Maintain LRU order of "inactive" objects */ |
05394f39 CW |
1155 | if (ret == 0 && i915_gem_object_is_inactive(obj)) |
1156 | list_move_tail(&obj->mm_list, &dev_priv->mm.inactive_list); | |
7d1c4804 | 1157 | |
05394f39 | 1158 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 1159 | unlock: |
673a394b EA |
1160 | mutex_unlock(&dev->struct_mutex); |
1161 | return ret; | |
1162 | } | |
1163 | ||
1164 | /** | |
1165 | * Called when user space has done writes to this buffer | |
1166 | */ | |
1167 | int | |
1168 | i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 1169 | struct drm_file *file) |
673a394b EA |
1170 | { |
1171 | struct drm_i915_gem_sw_finish *args = data; | |
05394f39 | 1172 | struct drm_i915_gem_object *obj; |
673a394b EA |
1173 | int ret = 0; |
1174 | ||
1175 | if (!(dev->driver->driver_features & DRIVER_GEM)) | |
1176 | return -ENODEV; | |
1177 | ||
76c1dec1 | 1178 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 1179 | if (ret) |
76c1dec1 | 1180 | return ret; |
1d7cfea1 | 1181 | |
05394f39 | 1182 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
673a394b | 1183 | if (obj == NULL) { |
1d7cfea1 CW |
1184 | ret = -ENOENT; |
1185 | goto unlock; | |
673a394b EA |
1186 | } |
1187 | ||
673a394b | 1188 | /* Pinned buffers may be scanout, so flush the cache */ |
05394f39 | 1189 | if (obj->pin_count) |
e47c68e9 EA |
1190 | i915_gem_object_flush_cpu_write_domain(obj); |
1191 | ||
05394f39 | 1192 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 1193 | unlock: |
673a394b EA |
1194 | mutex_unlock(&dev->struct_mutex); |
1195 | return ret; | |
1196 | } | |
1197 | ||
1198 | /** | |
1199 | * Maps the contents of an object, returning the address it is mapped | |
1200 | * into. | |
1201 | * | |
1202 | * While the mapping holds a reference on the contents of the object, it doesn't | |
1203 | * imply a ref on the object itself. | |
1204 | */ | |
1205 | int | |
1206 | i915_gem_mmap_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 1207 | struct drm_file *file) |
673a394b | 1208 | { |
da761a6e | 1209 | struct drm_i915_private *dev_priv = dev->dev_private; |
673a394b EA |
1210 | struct drm_i915_gem_mmap *args = data; |
1211 | struct drm_gem_object *obj; | |
1212 | loff_t offset; | |
1213 | unsigned long addr; | |
1214 | ||
1215 | if (!(dev->driver->driver_features & DRIVER_GEM)) | |
1216 | return -ENODEV; | |
1217 | ||
05394f39 | 1218 | obj = drm_gem_object_lookup(dev, file, args->handle); |
673a394b | 1219 | if (obj == NULL) |
bf79cb91 | 1220 | return -ENOENT; |
673a394b | 1221 | |
da761a6e CW |
1222 | if (obj->size > dev_priv->mm.gtt_mappable_end) { |
1223 | drm_gem_object_unreference_unlocked(obj); | |
1224 | return -E2BIG; | |
1225 | } | |
1226 | ||
673a394b EA |
1227 | offset = args->offset; |
1228 | ||
1229 | down_write(¤t->mm->mmap_sem); | |
1230 | addr = do_mmap(obj->filp, 0, args->size, | |
1231 | PROT_READ | PROT_WRITE, MAP_SHARED, | |
1232 | args->offset); | |
1233 | up_write(¤t->mm->mmap_sem); | |
bc9025bd | 1234 | drm_gem_object_unreference_unlocked(obj); |
673a394b EA |
1235 | if (IS_ERR((void *)addr)) |
1236 | return addr; | |
1237 | ||
1238 | args->addr_ptr = (uint64_t) addr; | |
1239 | ||
1240 | return 0; | |
1241 | } | |
1242 | ||
de151cf6 JB |
1243 | /** |
1244 | * i915_gem_fault - fault a page into the GTT | |
1245 | * vma: VMA in question | |
1246 | * vmf: fault info | |
1247 | * | |
1248 | * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped | |
1249 | * from userspace. The fault handler takes care of binding the object to | |
1250 | * the GTT (if needed), allocating and programming a fence register (again, | |
1251 | * only if needed based on whether the old reg is still valid or the object | |
1252 | * is tiled) and inserting a new PTE into the faulting process. | |
1253 | * | |
1254 | * Note that the faulting process may involve evicting existing objects | |
1255 | * from the GTT and/or fence registers to make room. So performance may | |
1256 | * suffer if the GTT working set is large or there are few fence registers | |
1257 | * left. | |
1258 | */ | |
1259 | int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf) | |
1260 | { | |
05394f39 CW |
1261 | struct drm_i915_gem_object *obj = to_intel_bo(vma->vm_private_data); |
1262 | struct drm_device *dev = obj->base.dev; | |
7d1c4804 | 1263 | drm_i915_private_t *dev_priv = dev->dev_private; |
de151cf6 JB |
1264 | pgoff_t page_offset; |
1265 | unsigned long pfn; | |
1266 | int ret = 0; | |
0f973f27 | 1267 | bool write = !!(vmf->flags & FAULT_FLAG_WRITE); |
de151cf6 JB |
1268 | |
1269 | /* We don't use vmf->pgoff since that has the fake offset */ | |
1270 | page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >> | |
1271 | PAGE_SHIFT; | |
1272 | ||
1273 | /* Now bind it into the GTT if needed */ | |
1274 | mutex_lock(&dev->struct_mutex); | |
05394f39 | 1275 | BUG_ON(obj->pin_count && !obj->pin_mappable); |
a00b10c3 | 1276 | |
919926ae CW |
1277 | if (!obj->map_and_fenceable) { |
1278 | ret = i915_gem_object_unbind(obj); | |
1279 | if (ret) | |
1280 | goto unlock; | |
a00b10c3 | 1281 | } |
16e809ac | 1282 | |
05394f39 | 1283 | if (!obj->gtt_space) { |
75e9e915 | 1284 | ret = i915_gem_object_bind_to_gtt(obj, 0, true); |
c715089f CW |
1285 | if (ret) |
1286 | goto unlock; | |
de151cf6 JB |
1287 | } |
1288 | ||
4a684a41 CW |
1289 | ret = i915_gem_object_set_to_gtt_domain(obj, write); |
1290 | if (ret) | |
1291 | goto unlock; | |
1292 | ||
05394f39 CW |
1293 | if (!obj->fault_mappable) { |
1294 | obj->fault_mappable = true; | |
1295 | i915_gem_info_update_mappable(dev_priv, obj, true); | |
fb7d516a DV |
1296 | } |
1297 | ||
de151cf6 | 1298 | /* Need a new fence register? */ |
05394f39 | 1299 | if (obj->tiling_mode != I915_TILING_NONE) { |
2cf34d7b | 1300 | ret = i915_gem_object_get_fence_reg(obj, true); |
c715089f CW |
1301 | if (ret) |
1302 | goto unlock; | |
d9ddcb96 | 1303 | } |
de151cf6 | 1304 | |
05394f39 CW |
1305 | if (i915_gem_object_is_inactive(obj)) |
1306 | list_move_tail(&obj->mm_list, &dev_priv->mm.inactive_list); | |
7d1c4804 | 1307 | |
05394f39 | 1308 | pfn = ((dev->agp->base + obj->gtt_offset) >> PAGE_SHIFT) + |
de151cf6 JB |
1309 | page_offset; |
1310 | ||
1311 | /* Finally, remap it using the new GTT offset */ | |
1312 | ret = vm_insert_pfn(vma, (unsigned long)vmf->virtual_address, pfn); | |
c715089f | 1313 | unlock: |
de151cf6 JB |
1314 | mutex_unlock(&dev->struct_mutex); |
1315 | ||
1316 | switch (ret) { | |
045e769a CW |
1317 | case -EAGAIN: |
1318 | set_need_resched(); | |
c715089f CW |
1319 | case 0: |
1320 | case -ERESTARTSYS: | |
1321 | return VM_FAULT_NOPAGE; | |
de151cf6 | 1322 | case -ENOMEM: |
de151cf6 | 1323 | return VM_FAULT_OOM; |
de151cf6 | 1324 | default: |
c715089f | 1325 | return VM_FAULT_SIGBUS; |
de151cf6 JB |
1326 | } |
1327 | } | |
1328 | ||
1329 | /** | |
1330 | * i915_gem_create_mmap_offset - create a fake mmap offset for an object | |
1331 | * @obj: obj in question | |
1332 | * | |
1333 | * GEM memory mapping works by handing back to userspace a fake mmap offset | |
1334 | * it can use in a subsequent mmap(2) call. The DRM core code then looks | |
1335 | * up the object based on the offset and sets up the various memory mapping | |
1336 | * structures. | |
1337 | * | |
1338 | * This routine allocates and attaches a fake offset for @obj. | |
1339 | */ | |
1340 | static int | |
05394f39 | 1341 | i915_gem_create_mmap_offset(struct drm_i915_gem_object *obj) |
de151cf6 | 1342 | { |
05394f39 | 1343 | struct drm_device *dev = obj->base.dev; |
de151cf6 | 1344 | struct drm_gem_mm *mm = dev->mm_private; |
de151cf6 | 1345 | struct drm_map_list *list; |
f77d390c | 1346 | struct drm_local_map *map; |
de151cf6 JB |
1347 | int ret = 0; |
1348 | ||
1349 | /* Set the object up for mmap'ing */ | |
05394f39 | 1350 | list = &obj->base.map_list; |
9a298b2a | 1351 | list->map = kzalloc(sizeof(struct drm_map_list), GFP_KERNEL); |
de151cf6 JB |
1352 | if (!list->map) |
1353 | return -ENOMEM; | |
1354 | ||
1355 | map = list->map; | |
1356 | map->type = _DRM_GEM; | |
05394f39 | 1357 | map->size = obj->base.size; |
de151cf6 JB |
1358 | map->handle = obj; |
1359 | ||
1360 | /* Get a DRM GEM mmap offset allocated... */ | |
1361 | list->file_offset_node = drm_mm_search_free(&mm->offset_manager, | |
05394f39 CW |
1362 | obj->base.size / PAGE_SIZE, |
1363 | 0, 0); | |
de151cf6 | 1364 | if (!list->file_offset_node) { |
05394f39 CW |
1365 | DRM_ERROR("failed to allocate offset for bo %d\n", |
1366 | obj->base.name); | |
9e0ae534 | 1367 | ret = -ENOSPC; |
de151cf6 JB |
1368 | goto out_free_list; |
1369 | } | |
1370 | ||
1371 | list->file_offset_node = drm_mm_get_block(list->file_offset_node, | |
05394f39 CW |
1372 | obj->base.size / PAGE_SIZE, |
1373 | 0); | |
de151cf6 JB |
1374 | if (!list->file_offset_node) { |
1375 | ret = -ENOMEM; | |
1376 | goto out_free_list; | |
1377 | } | |
1378 | ||
1379 | list->hash.key = list->file_offset_node->start; | |
9e0ae534 CW |
1380 | ret = drm_ht_insert_item(&mm->offset_hash, &list->hash); |
1381 | if (ret) { | |
de151cf6 JB |
1382 | DRM_ERROR("failed to add to map hash\n"); |
1383 | goto out_free_mm; | |
1384 | } | |
1385 | ||
de151cf6 JB |
1386 | return 0; |
1387 | ||
1388 | out_free_mm: | |
1389 | drm_mm_put_block(list->file_offset_node); | |
1390 | out_free_list: | |
9a298b2a | 1391 | kfree(list->map); |
39a01d1f | 1392 | list->map = NULL; |
de151cf6 JB |
1393 | |
1394 | return ret; | |
1395 | } | |
1396 | ||
901782b2 CW |
1397 | /** |
1398 | * i915_gem_release_mmap - remove physical page mappings | |
1399 | * @obj: obj in question | |
1400 | * | |
af901ca1 | 1401 | * Preserve the reservation of the mmapping with the DRM core code, but |
901782b2 CW |
1402 | * relinquish ownership of the pages back to the system. |
1403 | * | |
1404 | * It is vital that we remove the page mapping if we have mapped a tiled | |
1405 | * object through the GTT and then lose the fence register due to | |
1406 | * resource pressure. Similarly if the object has been moved out of the | |
1407 | * aperture, than pages mapped into userspace must be revoked. Removing the | |
1408 | * mapping will then trigger a page fault on the next user access, allowing | |
1409 | * fixup by i915_gem_fault(). | |
1410 | */ | |
d05ca301 | 1411 | void |
05394f39 | 1412 | i915_gem_release_mmap(struct drm_i915_gem_object *obj) |
901782b2 | 1413 | { |
05394f39 | 1414 | struct drm_device *dev = obj->base.dev; |
fb7d516a | 1415 | struct drm_i915_private *dev_priv = dev->dev_private; |
901782b2 | 1416 | |
05394f39 | 1417 | if (unlikely(obj->base.map_list.map && dev->dev_mapping)) |
901782b2 | 1418 | unmap_mapping_range(dev->dev_mapping, |
05394f39 CW |
1419 | (loff_t)obj->base.map_list.hash.key<<PAGE_SHIFT, |
1420 | obj->base.size, 1); | |
fb7d516a | 1421 | |
05394f39 CW |
1422 | if (obj->fault_mappable) { |
1423 | obj->fault_mappable = false; | |
1424 | i915_gem_info_update_mappable(dev_priv, obj, false); | |
fb7d516a | 1425 | } |
901782b2 CW |
1426 | } |
1427 | ||
ab00b3e5 | 1428 | static void |
05394f39 | 1429 | i915_gem_free_mmap_offset(struct drm_i915_gem_object *obj) |
ab00b3e5 | 1430 | { |
05394f39 | 1431 | struct drm_device *dev = obj->base.dev; |
ab00b3e5 | 1432 | struct drm_gem_mm *mm = dev->mm_private; |
05394f39 | 1433 | struct drm_map_list *list = &obj->base.map_list; |
ab00b3e5 | 1434 | |
ab00b3e5 | 1435 | drm_ht_remove_item(&mm->offset_hash, &list->hash); |
39a01d1f CW |
1436 | drm_mm_put_block(list->file_offset_node); |
1437 | kfree(list->map); | |
1438 | list->map = NULL; | |
ab00b3e5 JB |
1439 | } |
1440 | ||
92b88aeb CW |
1441 | static uint32_t |
1442 | i915_gem_get_gtt_size(struct drm_i915_gem_object *obj) | |
1443 | { | |
1444 | struct drm_device *dev = obj->base.dev; | |
1445 | uint32_t size; | |
1446 | ||
1447 | if (INTEL_INFO(dev)->gen >= 4 || | |
1448 | obj->tiling_mode == I915_TILING_NONE) | |
1449 | return obj->base.size; | |
1450 | ||
1451 | /* Previous chips need a power-of-two fence region when tiling */ | |
1452 | if (INTEL_INFO(dev)->gen == 3) | |
1453 | size = 1024*1024; | |
1454 | else | |
1455 | size = 512*1024; | |
1456 | ||
1457 | while (size < obj->base.size) | |
1458 | size <<= 1; | |
1459 | ||
1460 | return size; | |
1461 | } | |
1462 | ||
de151cf6 JB |
1463 | /** |
1464 | * i915_gem_get_gtt_alignment - return required GTT alignment for an object | |
1465 | * @obj: object to check | |
1466 | * | |
1467 | * Return the required GTT alignment for an object, taking into account | |
5e783301 | 1468 | * potential fence register mapping. |
de151cf6 JB |
1469 | */ |
1470 | static uint32_t | |
05394f39 | 1471 | i915_gem_get_gtt_alignment(struct drm_i915_gem_object *obj) |
de151cf6 | 1472 | { |
05394f39 | 1473 | struct drm_device *dev = obj->base.dev; |
de151cf6 JB |
1474 | |
1475 | /* | |
1476 | * Minimum alignment is 4k (GTT page size), but might be greater | |
1477 | * if a fence register is needed for the object. | |
1478 | */ | |
a00b10c3 | 1479 | if (INTEL_INFO(dev)->gen >= 4 || |
05394f39 | 1480 | obj->tiling_mode == I915_TILING_NONE) |
de151cf6 JB |
1481 | return 4096; |
1482 | ||
a00b10c3 CW |
1483 | /* |
1484 | * Previous chips need to be aligned to the size of the smallest | |
1485 | * fence register that can contain the object. | |
1486 | */ | |
05394f39 | 1487 | return i915_gem_get_gtt_size(obj); |
a00b10c3 CW |
1488 | } |
1489 | ||
5e783301 DV |
1490 | /** |
1491 | * i915_gem_get_unfenced_gtt_alignment - return required GTT alignment for an | |
1492 | * unfenced object | |
1493 | * @obj: object to check | |
1494 | * | |
1495 | * Return the required GTT alignment for an object, only taking into account | |
1496 | * unfenced tiled surface requirements. | |
1497 | */ | |
1498 | static uint32_t | |
05394f39 | 1499 | i915_gem_get_unfenced_gtt_alignment(struct drm_i915_gem_object *obj) |
5e783301 | 1500 | { |
05394f39 | 1501 | struct drm_device *dev = obj->base.dev; |
5e783301 DV |
1502 | int tile_height; |
1503 | ||
1504 | /* | |
1505 | * Minimum alignment is 4k (GTT page size) for sane hw. | |
1506 | */ | |
1507 | if (INTEL_INFO(dev)->gen >= 4 || IS_G33(dev) || | |
05394f39 | 1508 | obj->tiling_mode == I915_TILING_NONE) |
5e783301 DV |
1509 | return 4096; |
1510 | ||
1511 | /* | |
1512 | * Older chips need unfenced tiled buffers to be aligned to the left | |
1513 | * edge of an even tile row (where tile rows are counted as if the bo is | |
1514 | * placed in a fenced gtt region). | |
1515 | */ | |
1516 | if (IS_GEN2(dev) || | |
05394f39 | 1517 | (obj->tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev))) |
5e783301 DV |
1518 | tile_height = 32; |
1519 | else | |
1520 | tile_height = 8; | |
1521 | ||
05394f39 | 1522 | return tile_height * obj->stride * 2; |
5e783301 DV |
1523 | } |
1524 | ||
de151cf6 JB |
1525 | /** |
1526 | * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing | |
1527 | * @dev: DRM device | |
1528 | * @data: GTT mapping ioctl data | |
05394f39 | 1529 | * @file: GEM object info |
de151cf6 JB |
1530 | * |
1531 | * Simply returns the fake offset to userspace so it can mmap it. | |
1532 | * The mmap call will end up in drm_gem_mmap(), which will set things | |
1533 | * up so we can get faults in the handler above. | |
1534 | * | |
1535 | * The fault handler will take care of binding the object into the GTT | |
1536 | * (since it may have been evicted to make room for something), allocating | |
1537 | * a fence register, and mapping the appropriate aperture address into | |
1538 | * userspace. | |
1539 | */ | |
1540 | int | |
1541 | i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 1542 | struct drm_file *file) |
de151cf6 | 1543 | { |
da761a6e | 1544 | struct drm_i915_private *dev_priv = dev->dev_private; |
de151cf6 | 1545 | struct drm_i915_gem_mmap_gtt *args = data; |
05394f39 | 1546 | struct drm_i915_gem_object *obj; |
de151cf6 JB |
1547 | int ret; |
1548 | ||
1549 | if (!(dev->driver->driver_features & DRIVER_GEM)) | |
1550 | return -ENODEV; | |
1551 | ||
76c1dec1 | 1552 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 1553 | if (ret) |
76c1dec1 | 1554 | return ret; |
de151cf6 | 1555 | |
05394f39 | 1556 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
1d7cfea1 CW |
1557 | if (obj == NULL) { |
1558 | ret = -ENOENT; | |
1559 | goto unlock; | |
1560 | } | |
de151cf6 | 1561 | |
05394f39 | 1562 | if (obj->base.size > dev_priv->mm.gtt_mappable_end) { |
da761a6e CW |
1563 | ret = -E2BIG; |
1564 | goto unlock; | |
1565 | } | |
1566 | ||
05394f39 | 1567 | if (obj->madv != I915_MADV_WILLNEED) { |
ab18282d | 1568 | DRM_ERROR("Attempting to mmap a purgeable buffer\n"); |
1d7cfea1 CW |
1569 | ret = -EINVAL; |
1570 | goto out; | |
ab18282d CW |
1571 | } |
1572 | ||
05394f39 | 1573 | if (!obj->base.map_list.map) { |
de151cf6 | 1574 | ret = i915_gem_create_mmap_offset(obj); |
1d7cfea1 CW |
1575 | if (ret) |
1576 | goto out; | |
de151cf6 JB |
1577 | } |
1578 | ||
05394f39 | 1579 | args->offset = (u64)obj->base.map_list.hash.key << PAGE_SHIFT; |
de151cf6 | 1580 | |
1d7cfea1 | 1581 | out: |
05394f39 | 1582 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 1583 | unlock: |
de151cf6 | 1584 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 1585 | return ret; |
de151cf6 JB |
1586 | } |
1587 | ||
e5281ccd | 1588 | static int |
05394f39 | 1589 | i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj, |
e5281ccd CW |
1590 | gfp_t gfpmask) |
1591 | { | |
e5281ccd CW |
1592 | int page_count, i; |
1593 | struct address_space *mapping; | |
1594 | struct inode *inode; | |
1595 | struct page *page; | |
1596 | ||
1597 | /* Get the list of pages out of our struct file. They'll be pinned | |
1598 | * at this point until we release them. | |
1599 | */ | |
05394f39 CW |
1600 | page_count = obj->base.size / PAGE_SIZE; |
1601 | BUG_ON(obj->pages != NULL); | |
1602 | obj->pages = drm_malloc_ab(page_count, sizeof(struct page *)); | |
1603 | if (obj->pages == NULL) | |
e5281ccd CW |
1604 | return -ENOMEM; |
1605 | ||
05394f39 | 1606 | inode = obj->base.filp->f_path.dentry->d_inode; |
e5281ccd CW |
1607 | mapping = inode->i_mapping; |
1608 | for (i = 0; i < page_count; i++) { | |
1609 | page = read_cache_page_gfp(mapping, i, | |
1610 | GFP_HIGHUSER | | |
1611 | __GFP_COLD | | |
1612 | __GFP_RECLAIMABLE | | |
1613 | gfpmask); | |
1614 | if (IS_ERR(page)) | |
1615 | goto err_pages; | |
1616 | ||
05394f39 | 1617 | obj->pages[i] = page; |
e5281ccd CW |
1618 | } |
1619 | ||
05394f39 | 1620 | if (obj->tiling_mode != I915_TILING_NONE) |
e5281ccd CW |
1621 | i915_gem_object_do_bit_17_swizzle(obj); |
1622 | ||
1623 | return 0; | |
1624 | ||
1625 | err_pages: | |
1626 | while (i--) | |
05394f39 | 1627 | page_cache_release(obj->pages[i]); |
e5281ccd | 1628 | |
05394f39 CW |
1629 | drm_free_large(obj->pages); |
1630 | obj->pages = NULL; | |
e5281ccd CW |
1631 | return PTR_ERR(page); |
1632 | } | |
1633 | ||
5cdf5881 | 1634 | static void |
05394f39 | 1635 | i915_gem_object_put_pages_gtt(struct drm_i915_gem_object *obj) |
673a394b | 1636 | { |
05394f39 | 1637 | int page_count = obj->base.size / PAGE_SIZE; |
673a394b EA |
1638 | int i; |
1639 | ||
05394f39 | 1640 | BUG_ON(obj->madv == __I915_MADV_PURGED); |
673a394b | 1641 | |
05394f39 | 1642 | if (obj->tiling_mode != I915_TILING_NONE) |
280b713b EA |
1643 | i915_gem_object_save_bit_17_swizzle(obj); |
1644 | ||
05394f39 CW |
1645 | if (obj->madv == I915_MADV_DONTNEED) |
1646 | obj->dirty = 0; | |
3ef94daa CW |
1647 | |
1648 | for (i = 0; i < page_count; i++) { | |
05394f39 CW |
1649 | if (obj->dirty) |
1650 | set_page_dirty(obj->pages[i]); | |
3ef94daa | 1651 | |
05394f39 CW |
1652 | if (obj->madv == I915_MADV_WILLNEED) |
1653 | mark_page_accessed(obj->pages[i]); | |
3ef94daa | 1654 | |
05394f39 | 1655 | page_cache_release(obj->pages[i]); |
3ef94daa | 1656 | } |
05394f39 | 1657 | obj->dirty = 0; |
673a394b | 1658 | |
05394f39 CW |
1659 | drm_free_large(obj->pages); |
1660 | obj->pages = NULL; | |
673a394b EA |
1661 | } |
1662 | ||
a56ba56c CW |
1663 | static uint32_t |
1664 | i915_gem_next_request_seqno(struct drm_device *dev, | |
1665 | struct intel_ring_buffer *ring) | |
1666 | { | |
1667 | drm_i915_private_t *dev_priv = dev->dev_private; | |
5d97eb69 | 1668 | return ring->outstanding_lazy_request = dev_priv->next_seqno; |
a56ba56c CW |
1669 | } |
1670 | ||
673a394b | 1671 | static void |
05394f39 | 1672 | i915_gem_object_move_to_active(struct drm_i915_gem_object *obj, |
852835f3 | 1673 | struct intel_ring_buffer *ring) |
673a394b | 1674 | { |
05394f39 | 1675 | struct drm_device *dev = obj->base.dev; |
69dc4987 | 1676 | struct drm_i915_private *dev_priv = dev->dev_private; |
a56ba56c | 1677 | uint32_t seqno = i915_gem_next_request_seqno(dev, ring); |
617dbe27 | 1678 | |
852835f3 | 1679 | BUG_ON(ring == NULL); |
05394f39 | 1680 | obj->ring = ring; |
673a394b EA |
1681 | |
1682 | /* Add a reference if we're newly entering the active list. */ | |
05394f39 CW |
1683 | if (!obj->active) { |
1684 | drm_gem_object_reference(&obj->base); | |
1685 | obj->active = 1; | |
673a394b | 1686 | } |
e35a41de | 1687 | |
673a394b | 1688 | /* Move from whatever list we were on to the tail of execution. */ |
05394f39 CW |
1689 | list_move_tail(&obj->mm_list, &dev_priv->mm.active_list); |
1690 | list_move_tail(&obj->ring_list, &ring->active_list); | |
caea7476 | 1691 | |
05394f39 | 1692 | obj->last_rendering_seqno = seqno; |
caea7476 CW |
1693 | if (obj->fenced_gpu_access) { |
1694 | struct drm_i915_fence_reg *reg; | |
1695 | ||
1696 | BUG_ON(obj->fence_reg == I915_FENCE_REG_NONE); | |
1697 | ||
1698 | obj->last_fenced_seqno = seqno; | |
1699 | obj->last_fenced_ring = ring; | |
1700 | ||
1701 | reg = &dev_priv->fence_regs[obj->fence_reg]; | |
1702 | list_move_tail(®->lru_list, &dev_priv->mm.fence_list); | |
1703 | } | |
1704 | } | |
1705 | ||
1706 | static void | |
1707 | i915_gem_object_move_off_active(struct drm_i915_gem_object *obj) | |
1708 | { | |
1709 | list_del_init(&obj->ring_list); | |
1710 | obj->last_rendering_seqno = 0; | |
1711 | obj->last_fenced_seqno = 0; | |
673a394b EA |
1712 | } |
1713 | ||
ce44b0ea | 1714 | static void |
05394f39 | 1715 | i915_gem_object_move_to_flushing(struct drm_i915_gem_object *obj) |
ce44b0ea | 1716 | { |
05394f39 | 1717 | struct drm_device *dev = obj->base.dev; |
ce44b0ea | 1718 | drm_i915_private_t *dev_priv = dev->dev_private; |
ce44b0ea | 1719 | |
05394f39 CW |
1720 | BUG_ON(!obj->active); |
1721 | list_move_tail(&obj->mm_list, &dev_priv->mm.flushing_list); | |
caea7476 CW |
1722 | |
1723 | i915_gem_object_move_off_active(obj); | |
1724 | } | |
1725 | ||
1726 | static void | |
1727 | i915_gem_object_move_to_inactive(struct drm_i915_gem_object *obj) | |
1728 | { | |
1729 | struct drm_device *dev = obj->base.dev; | |
1730 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1731 | ||
1732 | if (obj->pin_count != 0) | |
1733 | list_move_tail(&obj->mm_list, &dev_priv->mm.pinned_list); | |
1734 | else | |
1735 | list_move_tail(&obj->mm_list, &dev_priv->mm.inactive_list); | |
1736 | ||
1737 | BUG_ON(!list_empty(&obj->gpu_write_list)); | |
1738 | BUG_ON(!obj->active); | |
1739 | obj->ring = NULL; | |
1740 | ||
1741 | i915_gem_object_move_off_active(obj); | |
1742 | obj->fenced_gpu_access = false; | |
1743 | obj->last_fenced_ring = NULL; | |
1744 | ||
1745 | obj->active = 0; | |
1746 | drm_gem_object_unreference(&obj->base); | |
1747 | ||
1748 | WARN_ON(i915_verify_lists(dev)); | |
ce44b0ea | 1749 | } |
673a394b | 1750 | |
963b4836 CW |
1751 | /* Immediately discard the backing storage */ |
1752 | static void | |
05394f39 | 1753 | i915_gem_object_truncate(struct drm_i915_gem_object *obj) |
963b4836 | 1754 | { |
bb6baf76 | 1755 | struct inode *inode; |
963b4836 | 1756 | |
ae9fed6b CW |
1757 | /* Our goal here is to return as much of the memory as |
1758 | * is possible back to the system as we are called from OOM. | |
1759 | * To do this we must instruct the shmfs to drop all of its | |
1760 | * backing pages, *now*. Here we mirror the actions taken | |
1761 | * when by shmem_delete_inode() to release the backing store. | |
1762 | */ | |
05394f39 | 1763 | inode = obj->base.filp->f_path.dentry->d_inode; |
ae9fed6b CW |
1764 | truncate_inode_pages(inode->i_mapping, 0); |
1765 | if (inode->i_op->truncate_range) | |
1766 | inode->i_op->truncate_range(inode, 0, (loff_t)-1); | |
bb6baf76 | 1767 | |
05394f39 | 1768 | obj->madv = __I915_MADV_PURGED; |
963b4836 CW |
1769 | } |
1770 | ||
1771 | static inline int | |
05394f39 | 1772 | i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj) |
963b4836 | 1773 | { |
05394f39 | 1774 | return obj->madv == I915_MADV_DONTNEED; |
963b4836 CW |
1775 | } |
1776 | ||
63560396 DV |
1777 | static void |
1778 | i915_gem_process_flushing_list(struct drm_device *dev, | |
8a1a49f9 | 1779 | uint32_t flush_domains, |
852835f3 | 1780 | struct intel_ring_buffer *ring) |
63560396 | 1781 | { |
05394f39 | 1782 | struct drm_i915_gem_object *obj, *next; |
63560396 | 1783 | |
05394f39 | 1784 | list_for_each_entry_safe(obj, next, |
64193406 | 1785 | &ring->gpu_write_list, |
63560396 | 1786 | gpu_write_list) { |
05394f39 CW |
1787 | if (obj->base.write_domain & flush_domains) { |
1788 | uint32_t old_write_domain = obj->base.write_domain; | |
63560396 | 1789 | |
05394f39 CW |
1790 | obj->base.write_domain = 0; |
1791 | list_del_init(&obj->gpu_write_list); | |
617dbe27 | 1792 | i915_gem_object_move_to_active(obj, ring); |
63560396 | 1793 | |
63560396 | 1794 | trace_i915_gem_object_change_domain(obj, |
05394f39 | 1795 | obj->base.read_domains, |
63560396 DV |
1796 | old_write_domain); |
1797 | } | |
1798 | } | |
1799 | } | |
8187a2b7 | 1800 | |
3cce469c | 1801 | int |
8a1a49f9 | 1802 | i915_add_request(struct drm_device *dev, |
f787a5f5 | 1803 | struct drm_file *file, |
8dc5d147 | 1804 | struct drm_i915_gem_request *request, |
8a1a49f9 | 1805 | struct intel_ring_buffer *ring) |
673a394b EA |
1806 | { |
1807 | drm_i915_private_t *dev_priv = dev->dev_private; | |
f787a5f5 | 1808 | struct drm_i915_file_private *file_priv = NULL; |
673a394b EA |
1809 | uint32_t seqno; |
1810 | int was_empty; | |
3cce469c CW |
1811 | int ret; |
1812 | ||
1813 | BUG_ON(request == NULL); | |
673a394b | 1814 | |
f787a5f5 CW |
1815 | if (file != NULL) |
1816 | file_priv = file->driver_priv; | |
b962442e | 1817 | |
3cce469c CW |
1818 | ret = ring->add_request(ring, &seqno); |
1819 | if (ret) | |
1820 | return ret; | |
673a394b | 1821 | |
a56ba56c | 1822 | ring->outstanding_lazy_request = false; |
673a394b EA |
1823 | |
1824 | request->seqno = seqno; | |
852835f3 | 1825 | request->ring = ring; |
673a394b | 1826 | request->emitted_jiffies = jiffies; |
852835f3 ZN |
1827 | was_empty = list_empty(&ring->request_list); |
1828 | list_add_tail(&request->list, &ring->request_list); | |
1829 | ||
f787a5f5 | 1830 | if (file_priv) { |
1c25595f | 1831 | spin_lock(&file_priv->mm.lock); |
f787a5f5 | 1832 | request->file_priv = file_priv; |
b962442e | 1833 | list_add_tail(&request->client_list, |
f787a5f5 | 1834 | &file_priv->mm.request_list); |
1c25595f | 1835 | spin_unlock(&file_priv->mm.lock); |
b962442e | 1836 | } |
673a394b | 1837 | |
f65d9421 | 1838 | if (!dev_priv->mm.suspended) { |
b3b079db CW |
1839 | mod_timer(&dev_priv->hangcheck_timer, |
1840 | jiffies + msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)); | |
f65d9421 | 1841 | if (was_empty) |
b3b079db CW |
1842 | queue_delayed_work(dev_priv->wq, |
1843 | &dev_priv->mm.retire_work, HZ); | |
f65d9421 | 1844 | } |
3cce469c | 1845 | return 0; |
673a394b EA |
1846 | } |
1847 | ||
1848 | /** | |
1849 | * Command execution barrier | |
1850 | * | |
1851 | * Ensures that all commands in the ring are finished | |
1852 | * before signalling the CPU | |
1853 | */ | |
8a1a49f9 | 1854 | static void |
852835f3 | 1855 | i915_retire_commands(struct drm_device *dev, struct intel_ring_buffer *ring) |
673a394b | 1856 | { |
673a394b | 1857 | uint32_t flush_domains = 0; |
673a394b EA |
1858 | |
1859 | /* The sampler always gets flushed on i965 (sigh) */ | |
a6c45cf0 | 1860 | if (INTEL_INFO(dev)->gen >= 4) |
673a394b | 1861 | flush_domains |= I915_GEM_DOMAIN_SAMPLER; |
852835f3 | 1862 | |
78501eac | 1863 | ring->flush(ring, I915_GEM_DOMAIN_COMMAND, flush_domains); |
673a394b EA |
1864 | } |
1865 | ||
f787a5f5 CW |
1866 | static inline void |
1867 | i915_gem_request_remove_from_client(struct drm_i915_gem_request *request) | |
673a394b | 1868 | { |
1c25595f | 1869 | struct drm_i915_file_private *file_priv = request->file_priv; |
673a394b | 1870 | |
1c25595f CW |
1871 | if (!file_priv) |
1872 | return; | |
1c5d22f7 | 1873 | |
1c25595f CW |
1874 | spin_lock(&file_priv->mm.lock); |
1875 | list_del(&request->client_list); | |
1876 | request->file_priv = NULL; | |
1877 | spin_unlock(&file_priv->mm.lock); | |
673a394b | 1878 | } |
673a394b | 1879 | |
dfaae392 CW |
1880 | static void i915_gem_reset_ring_lists(struct drm_i915_private *dev_priv, |
1881 | struct intel_ring_buffer *ring) | |
9375e446 | 1882 | { |
dfaae392 CW |
1883 | while (!list_empty(&ring->request_list)) { |
1884 | struct drm_i915_gem_request *request; | |
673a394b | 1885 | |
dfaae392 CW |
1886 | request = list_first_entry(&ring->request_list, |
1887 | struct drm_i915_gem_request, | |
1888 | list); | |
de151cf6 | 1889 | |
dfaae392 | 1890 | list_del(&request->list); |
f787a5f5 | 1891 | i915_gem_request_remove_from_client(request); |
dfaae392 CW |
1892 | kfree(request); |
1893 | } | |
673a394b | 1894 | |
dfaae392 | 1895 | while (!list_empty(&ring->active_list)) { |
05394f39 | 1896 | struct drm_i915_gem_object *obj; |
9375e446 | 1897 | |
05394f39 CW |
1898 | obj = list_first_entry(&ring->active_list, |
1899 | struct drm_i915_gem_object, | |
1900 | ring_list); | |
9375e446 | 1901 | |
05394f39 CW |
1902 | obj->base.write_domain = 0; |
1903 | list_del_init(&obj->gpu_write_list); | |
1904 | i915_gem_object_move_to_inactive(obj); | |
673a394b EA |
1905 | } |
1906 | } | |
1907 | ||
312817a3 CW |
1908 | static void i915_gem_reset_fences(struct drm_device *dev) |
1909 | { | |
1910 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1911 | int i; | |
1912 | ||
1913 | for (i = 0; i < 16; i++) { | |
1914 | struct drm_i915_fence_reg *reg = &dev_priv->fence_regs[i]; | |
1915 | if (reg->obj) | |
1916 | i915_gem_clear_fence_reg(reg->obj); | |
1917 | } | |
1918 | } | |
1919 | ||
069efc1d | 1920 | void i915_gem_reset(struct drm_device *dev) |
673a394b | 1921 | { |
77f01230 | 1922 | struct drm_i915_private *dev_priv = dev->dev_private; |
05394f39 | 1923 | struct drm_i915_gem_object *obj; |
673a394b | 1924 | |
dfaae392 | 1925 | i915_gem_reset_ring_lists(dev_priv, &dev_priv->render_ring); |
87acb0a5 | 1926 | i915_gem_reset_ring_lists(dev_priv, &dev_priv->bsd_ring); |
549f7365 | 1927 | i915_gem_reset_ring_lists(dev_priv, &dev_priv->blt_ring); |
dfaae392 CW |
1928 | |
1929 | /* Remove anything from the flushing lists. The GPU cache is likely | |
1930 | * to be lost on reset along with the data, so simply move the | |
1931 | * lost bo to the inactive list. | |
1932 | */ | |
1933 | while (!list_empty(&dev_priv->mm.flushing_list)) { | |
05394f39 CW |
1934 | obj= list_first_entry(&dev_priv->mm.flushing_list, |
1935 | struct drm_i915_gem_object, | |
1936 | mm_list); | |
dfaae392 | 1937 | |
05394f39 CW |
1938 | obj->base.write_domain = 0; |
1939 | list_del_init(&obj->gpu_write_list); | |
1940 | i915_gem_object_move_to_inactive(obj); | |
dfaae392 CW |
1941 | } |
1942 | ||
1943 | /* Move everything out of the GPU domains to ensure we do any | |
1944 | * necessary invalidation upon reuse. | |
1945 | */ | |
05394f39 | 1946 | list_for_each_entry(obj, |
77f01230 | 1947 | &dev_priv->mm.inactive_list, |
69dc4987 | 1948 | mm_list) |
77f01230 | 1949 | { |
05394f39 | 1950 | obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS; |
77f01230 | 1951 | } |
069efc1d CW |
1952 | |
1953 | /* The fence registers are invalidated so clear them out */ | |
312817a3 | 1954 | i915_gem_reset_fences(dev); |
673a394b EA |
1955 | } |
1956 | ||
1957 | /** | |
1958 | * This function clears the request list as sequence numbers are passed. | |
1959 | */ | |
b09a1fec CW |
1960 | static void |
1961 | i915_gem_retire_requests_ring(struct drm_device *dev, | |
1962 | struct intel_ring_buffer *ring) | |
673a394b EA |
1963 | { |
1964 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1965 | uint32_t seqno; | |
1966 | ||
b84d5f0c CW |
1967 | if (!ring->status_page.page_addr || |
1968 | list_empty(&ring->request_list)) | |
6c0594a3 KW |
1969 | return; |
1970 | ||
23bc5982 | 1971 | WARN_ON(i915_verify_lists(dev)); |
673a394b | 1972 | |
78501eac | 1973 | seqno = ring->get_seqno(ring); |
852835f3 | 1974 | while (!list_empty(&ring->request_list)) { |
673a394b | 1975 | struct drm_i915_gem_request *request; |
673a394b | 1976 | |
852835f3 | 1977 | request = list_first_entry(&ring->request_list, |
673a394b EA |
1978 | struct drm_i915_gem_request, |
1979 | list); | |
673a394b | 1980 | |
dfaae392 | 1981 | if (!i915_seqno_passed(seqno, request->seqno)) |
b84d5f0c CW |
1982 | break; |
1983 | ||
1984 | trace_i915_gem_request_retire(dev, request->seqno); | |
1985 | ||
1986 | list_del(&request->list); | |
f787a5f5 | 1987 | i915_gem_request_remove_from_client(request); |
b84d5f0c CW |
1988 | kfree(request); |
1989 | } | |
673a394b | 1990 | |
b84d5f0c CW |
1991 | /* Move any buffers on the active list that are no longer referenced |
1992 | * by the ringbuffer to the flushing/inactive lists as appropriate. | |
1993 | */ | |
1994 | while (!list_empty(&ring->active_list)) { | |
05394f39 | 1995 | struct drm_i915_gem_object *obj; |
b84d5f0c | 1996 | |
05394f39 CW |
1997 | obj= list_first_entry(&ring->active_list, |
1998 | struct drm_i915_gem_object, | |
1999 | ring_list); | |
673a394b | 2000 | |
05394f39 | 2001 | if (!i915_seqno_passed(seqno, obj->last_rendering_seqno)) |
673a394b | 2002 | break; |
b84d5f0c | 2003 | |
05394f39 | 2004 | if (obj->base.write_domain != 0) |
b84d5f0c CW |
2005 | i915_gem_object_move_to_flushing(obj); |
2006 | else | |
2007 | i915_gem_object_move_to_inactive(obj); | |
673a394b | 2008 | } |
9d34e5db CW |
2009 | |
2010 | if (unlikely (dev_priv->trace_irq_seqno && | |
2011 | i915_seqno_passed(dev_priv->trace_irq_seqno, seqno))) { | |
78501eac | 2012 | ring->user_irq_put(ring); |
9d34e5db CW |
2013 | dev_priv->trace_irq_seqno = 0; |
2014 | } | |
23bc5982 CW |
2015 | |
2016 | WARN_ON(i915_verify_lists(dev)); | |
673a394b EA |
2017 | } |
2018 | ||
b09a1fec CW |
2019 | void |
2020 | i915_gem_retire_requests(struct drm_device *dev) | |
2021 | { | |
2022 | drm_i915_private_t *dev_priv = dev->dev_private; | |
2023 | ||
be72615b | 2024 | if (!list_empty(&dev_priv->mm.deferred_free_list)) { |
05394f39 | 2025 | struct drm_i915_gem_object *obj, *next; |
be72615b CW |
2026 | |
2027 | /* We must be careful that during unbind() we do not | |
2028 | * accidentally infinitely recurse into retire requests. | |
2029 | * Currently: | |
2030 | * retire -> free -> unbind -> wait -> retire_ring | |
2031 | */ | |
05394f39 | 2032 | list_for_each_entry_safe(obj, next, |
be72615b | 2033 | &dev_priv->mm.deferred_free_list, |
69dc4987 | 2034 | mm_list) |
05394f39 | 2035 | i915_gem_free_object_tail(obj); |
be72615b CW |
2036 | } |
2037 | ||
b09a1fec | 2038 | i915_gem_retire_requests_ring(dev, &dev_priv->render_ring); |
87acb0a5 | 2039 | i915_gem_retire_requests_ring(dev, &dev_priv->bsd_ring); |
549f7365 | 2040 | i915_gem_retire_requests_ring(dev, &dev_priv->blt_ring); |
b09a1fec CW |
2041 | } |
2042 | ||
75ef9da2 | 2043 | static void |
673a394b EA |
2044 | i915_gem_retire_work_handler(struct work_struct *work) |
2045 | { | |
2046 | drm_i915_private_t *dev_priv; | |
2047 | struct drm_device *dev; | |
2048 | ||
2049 | dev_priv = container_of(work, drm_i915_private_t, | |
2050 | mm.retire_work.work); | |
2051 | dev = dev_priv->dev; | |
2052 | ||
891b48cf CW |
2053 | /* Come back later if the device is busy... */ |
2054 | if (!mutex_trylock(&dev->struct_mutex)) { | |
2055 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ); | |
2056 | return; | |
2057 | } | |
2058 | ||
b09a1fec | 2059 | i915_gem_retire_requests(dev); |
d1b851fc | 2060 | |
6dbe2772 | 2061 | if (!dev_priv->mm.suspended && |
d1b851fc | 2062 | (!list_empty(&dev_priv->render_ring.request_list) || |
549f7365 CW |
2063 | !list_empty(&dev_priv->bsd_ring.request_list) || |
2064 | !list_empty(&dev_priv->blt_ring.request_list))) | |
9c9fe1f8 | 2065 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ); |
673a394b EA |
2066 | mutex_unlock(&dev->struct_mutex); |
2067 | } | |
2068 | ||
5a5a0c64 | 2069 | int |
852835f3 | 2070 | i915_do_wait_request(struct drm_device *dev, uint32_t seqno, |
8a1a49f9 | 2071 | bool interruptible, struct intel_ring_buffer *ring) |
673a394b EA |
2072 | { |
2073 | drm_i915_private_t *dev_priv = dev->dev_private; | |
802c7eb6 | 2074 | u32 ier; |
673a394b EA |
2075 | int ret = 0; |
2076 | ||
2077 | BUG_ON(seqno == 0); | |
2078 | ||
ba1234d1 | 2079 | if (atomic_read(&dev_priv->mm.wedged)) |
30dbf0c0 CW |
2080 | return -EAGAIN; |
2081 | ||
5d97eb69 | 2082 | if (seqno == ring->outstanding_lazy_request) { |
3cce469c CW |
2083 | struct drm_i915_gem_request *request; |
2084 | ||
2085 | request = kzalloc(sizeof(*request), GFP_KERNEL); | |
2086 | if (request == NULL) | |
e35a41de | 2087 | return -ENOMEM; |
3cce469c CW |
2088 | |
2089 | ret = i915_add_request(dev, NULL, request, ring); | |
2090 | if (ret) { | |
2091 | kfree(request); | |
2092 | return ret; | |
2093 | } | |
2094 | ||
2095 | seqno = request->seqno; | |
e35a41de | 2096 | } |
ffed1d09 | 2097 | |
78501eac | 2098 | if (!i915_seqno_passed(ring->get_seqno(ring), seqno)) { |
bad720ff | 2099 | if (HAS_PCH_SPLIT(dev)) |
036a4a7d ZW |
2100 | ier = I915_READ(DEIER) | I915_READ(GTIER); |
2101 | else | |
2102 | ier = I915_READ(IER); | |
802c7eb6 JB |
2103 | if (!ier) { |
2104 | DRM_ERROR("something (likely vbetool) disabled " | |
2105 | "interrupts, re-enabling\n"); | |
2106 | i915_driver_irq_preinstall(dev); | |
2107 | i915_driver_irq_postinstall(dev); | |
2108 | } | |
2109 | ||
1c5d22f7 CW |
2110 | trace_i915_gem_request_wait_begin(dev, seqno); |
2111 | ||
b2223497 | 2112 | ring->waiting_seqno = seqno; |
78501eac | 2113 | ring->user_irq_get(ring); |
48764bf4 | 2114 | if (interruptible) |
852835f3 | 2115 | ret = wait_event_interruptible(ring->irq_queue, |
78501eac | 2116 | i915_seqno_passed(ring->get_seqno(ring), seqno) |
852835f3 | 2117 | || atomic_read(&dev_priv->mm.wedged)); |
48764bf4 | 2118 | else |
852835f3 | 2119 | wait_event(ring->irq_queue, |
78501eac | 2120 | i915_seqno_passed(ring->get_seqno(ring), seqno) |
852835f3 | 2121 | || atomic_read(&dev_priv->mm.wedged)); |
48764bf4 | 2122 | |
78501eac | 2123 | ring->user_irq_put(ring); |
b2223497 | 2124 | ring->waiting_seqno = 0; |
1c5d22f7 CW |
2125 | |
2126 | trace_i915_gem_request_wait_end(dev, seqno); | |
673a394b | 2127 | } |
ba1234d1 | 2128 | if (atomic_read(&dev_priv->mm.wedged)) |
30dbf0c0 | 2129 | ret = -EAGAIN; |
673a394b EA |
2130 | |
2131 | if (ret && ret != -ERESTARTSYS) | |
8bff917c | 2132 | DRM_ERROR("%s returns %d (awaiting %d at %d, next %d)\n", |
78501eac | 2133 | __func__, ret, seqno, ring->get_seqno(ring), |
8bff917c | 2134 | dev_priv->next_seqno); |
673a394b EA |
2135 | |
2136 | /* Directly dispatch request retiring. While we have the work queue | |
2137 | * to handle this, the waiter on a request often wants an associated | |
2138 | * buffer to have made it to the inactive list, and we would need | |
2139 | * a separate wait queue to handle that. | |
2140 | */ | |
2141 | if (ret == 0) | |
b09a1fec | 2142 | i915_gem_retire_requests_ring(dev, ring); |
673a394b EA |
2143 | |
2144 | return ret; | |
2145 | } | |
2146 | ||
48764bf4 DV |
2147 | /** |
2148 | * Waits for a sequence number to be signaled, and cleans up the | |
2149 | * request and object lists appropriately for that event. | |
2150 | */ | |
2151 | static int | |
852835f3 | 2152 | i915_wait_request(struct drm_device *dev, uint32_t seqno, |
a56ba56c | 2153 | struct intel_ring_buffer *ring) |
48764bf4 | 2154 | { |
852835f3 | 2155 | return i915_do_wait_request(dev, seqno, 1, ring); |
48764bf4 DV |
2156 | } |
2157 | ||
20f0cd55 | 2158 | static void |
9220434a CW |
2159 | i915_gem_flush_ring(struct drm_device *dev, |
2160 | struct intel_ring_buffer *ring, | |
2161 | uint32_t invalidate_domains, | |
2162 | uint32_t flush_domains) | |
2163 | { | |
78501eac | 2164 | ring->flush(ring, invalidate_domains, flush_domains); |
9220434a CW |
2165 | i915_gem_process_flushing_list(dev, flush_domains, ring); |
2166 | } | |
2167 | ||
8187a2b7 ZN |
2168 | static void |
2169 | i915_gem_flush(struct drm_device *dev, | |
2170 | uint32_t invalidate_domains, | |
9220434a CW |
2171 | uint32_t flush_domains, |
2172 | uint32_t flush_rings) | |
8187a2b7 ZN |
2173 | { |
2174 | drm_i915_private_t *dev_priv = dev->dev_private; | |
8bff917c | 2175 | |
8187a2b7 | 2176 | if (flush_domains & I915_GEM_DOMAIN_CPU) |
40ce6575 | 2177 | intel_gtt_chipset_flush(); |
8bff917c | 2178 | |
9220434a CW |
2179 | if ((flush_domains | invalidate_domains) & I915_GEM_GPU_DOMAINS) { |
2180 | if (flush_rings & RING_RENDER) | |
05394f39 | 2181 | i915_gem_flush_ring(dev, &dev_priv->render_ring, |
9220434a CW |
2182 | invalidate_domains, flush_domains); |
2183 | if (flush_rings & RING_BSD) | |
05394f39 | 2184 | i915_gem_flush_ring(dev, &dev_priv->bsd_ring, |
9220434a | 2185 | invalidate_domains, flush_domains); |
549f7365 | 2186 | if (flush_rings & RING_BLT) |
05394f39 | 2187 | i915_gem_flush_ring(dev, &dev_priv->blt_ring, |
549f7365 | 2188 | invalidate_domains, flush_domains); |
9220434a | 2189 | } |
8187a2b7 ZN |
2190 | } |
2191 | ||
673a394b EA |
2192 | /** |
2193 | * Ensures that all rendering to the object has completed and the object is | |
2194 | * safe to unbind from the GTT or access from the CPU. | |
2195 | */ | |
2196 | static int | |
05394f39 | 2197 | i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj, |
2cf34d7b | 2198 | bool interruptible) |
673a394b | 2199 | { |
05394f39 | 2200 | struct drm_device *dev = obj->base.dev; |
673a394b EA |
2201 | int ret; |
2202 | ||
e47c68e9 EA |
2203 | /* This function only exists to support waiting for existing rendering, |
2204 | * not for emitting required flushes. | |
673a394b | 2205 | */ |
05394f39 | 2206 | BUG_ON((obj->base.write_domain & I915_GEM_GPU_DOMAINS) != 0); |
673a394b EA |
2207 | |
2208 | /* If there is rendering queued on the buffer being evicted, wait for | |
2209 | * it. | |
2210 | */ | |
05394f39 | 2211 | if (obj->active) { |
2cf34d7b | 2212 | ret = i915_do_wait_request(dev, |
05394f39 | 2213 | obj->last_rendering_seqno, |
2cf34d7b | 2214 | interruptible, |
05394f39 | 2215 | obj->ring); |
2cf34d7b | 2216 | if (ret) |
673a394b EA |
2217 | return ret; |
2218 | } | |
2219 | ||
2220 | return 0; | |
2221 | } | |
2222 | ||
2223 | /** | |
2224 | * Unbinds an object from the GTT aperture. | |
2225 | */ | |
0f973f27 | 2226 | int |
05394f39 | 2227 | i915_gem_object_unbind(struct drm_i915_gem_object *obj) |
673a394b | 2228 | { |
05394f39 | 2229 | struct drm_device *dev = obj->base.dev; |
73aa808f | 2230 | struct drm_i915_private *dev_priv = dev->dev_private; |
673a394b EA |
2231 | int ret = 0; |
2232 | ||
05394f39 | 2233 | if (obj->gtt_space == NULL) |
673a394b EA |
2234 | return 0; |
2235 | ||
05394f39 | 2236 | if (obj->pin_count != 0) { |
673a394b EA |
2237 | DRM_ERROR("Attempting to unbind pinned buffer\n"); |
2238 | return -EINVAL; | |
2239 | } | |
2240 | ||
5323fd04 EA |
2241 | /* blow away mappings if mapped through GTT */ |
2242 | i915_gem_release_mmap(obj); | |
2243 | ||
673a394b EA |
2244 | /* Move the object to the CPU domain to ensure that |
2245 | * any possible CPU writes while it's not in the GTT | |
2246 | * are flushed when we go to remap it. This will | |
2247 | * also ensure that all pending GPU writes are finished | |
2248 | * before we unbind. | |
2249 | */ | |
e47c68e9 | 2250 | ret = i915_gem_object_set_to_cpu_domain(obj, 1); |
8dc1775d | 2251 | if (ret == -ERESTARTSYS) |
673a394b | 2252 | return ret; |
8dc1775d CW |
2253 | /* Continue on if we fail due to EIO, the GPU is hung so we |
2254 | * should be safe and we need to cleanup or else we might | |
2255 | * cause memory corruption through use-after-free. | |
2256 | */ | |
812ed492 CW |
2257 | if (ret) { |
2258 | i915_gem_clflush_object(obj); | |
05394f39 | 2259 | obj->base.read_domains = obj->base.write_domain = I915_GEM_DOMAIN_CPU; |
812ed492 | 2260 | } |
673a394b | 2261 | |
96b47b65 | 2262 | /* release the fence reg _after_ flushing */ |
05394f39 | 2263 | if (obj->fence_reg != I915_FENCE_REG_NONE) |
96b47b65 DV |
2264 | i915_gem_clear_fence_reg(obj); |
2265 | ||
7c2e6fdf | 2266 | i915_gem_gtt_unbind_object(obj); |
673a394b | 2267 | |
e5281ccd | 2268 | i915_gem_object_put_pages_gtt(obj); |
673a394b | 2269 | |
05394f39 CW |
2270 | i915_gem_info_remove_gtt(dev_priv, obj); |
2271 | list_del_init(&obj->mm_list); | |
75e9e915 | 2272 | /* Avoid an unnecessary call to unbind on rebind. */ |
05394f39 | 2273 | obj->map_and_fenceable = true; |
673a394b | 2274 | |
05394f39 CW |
2275 | drm_mm_put_block(obj->gtt_space); |
2276 | obj->gtt_space = NULL; | |
2277 | obj->gtt_offset = 0; | |
673a394b | 2278 | |
05394f39 | 2279 | if (i915_gem_object_is_purgeable(obj)) |
963b4836 CW |
2280 | i915_gem_object_truncate(obj); |
2281 | ||
1c5d22f7 CW |
2282 | trace_i915_gem_object_unbind(obj); |
2283 | ||
8dc1775d | 2284 | return ret; |
673a394b EA |
2285 | } |
2286 | ||
a56ba56c CW |
2287 | static int i915_ring_idle(struct drm_device *dev, |
2288 | struct intel_ring_buffer *ring) | |
2289 | { | |
395b70be | 2290 | if (list_empty(&ring->gpu_write_list) && list_empty(&ring->active_list)) |
64193406 CW |
2291 | return 0; |
2292 | ||
05394f39 | 2293 | i915_gem_flush_ring(dev, ring, |
a56ba56c CW |
2294 | I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS); |
2295 | return i915_wait_request(dev, | |
2296 | i915_gem_next_request_seqno(dev, ring), | |
2297 | ring); | |
2298 | } | |
2299 | ||
b47eb4a2 | 2300 | int |
4df2faf4 DV |
2301 | i915_gpu_idle(struct drm_device *dev) |
2302 | { | |
2303 | drm_i915_private_t *dev_priv = dev->dev_private; | |
2304 | bool lists_empty; | |
852835f3 | 2305 | int ret; |
4df2faf4 | 2306 | |
d1b851fc | 2307 | lists_empty = (list_empty(&dev_priv->mm.flushing_list) && |
395b70be | 2308 | list_empty(&dev_priv->mm.active_list)); |
4df2faf4 DV |
2309 | if (lists_empty) |
2310 | return 0; | |
2311 | ||
2312 | /* Flush everything onto the inactive list. */ | |
a56ba56c | 2313 | ret = i915_ring_idle(dev, &dev_priv->render_ring); |
8a1a49f9 DV |
2314 | if (ret) |
2315 | return ret; | |
d1b851fc | 2316 | |
87acb0a5 CW |
2317 | ret = i915_ring_idle(dev, &dev_priv->bsd_ring); |
2318 | if (ret) | |
2319 | return ret; | |
d1b851fc | 2320 | |
549f7365 CW |
2321 | ret = i915_ring_idle(dev, &dev_priv->blt_ring); |
2322 | if (ret) | |
2323 | return ret; | |
4df2faf4 | 2324 | |
8a1a49f9 | 2325 | return 0; |
4df2faf4 DV |
2326 | } |
2327 | ||
c6642782 DV |
2328 | static int sandybridge_write_fence_reg(struct drm_i915_gem_object *obj, |
2329 | struct intel_ring_buffer *pipelined) | |
4e901fdc | 2330 | { |
05394f39 | 2331 | struct drm_device *dev = obj->base.dev; |
4e901fdc | 2332 | drm_i915_private_t *dev_priv = dev->dev_private; |
05394f39 CW |
2333 | u32 size = obj->gtt_space->size; |
2334 | int regnum = obj->fence_reg; | |
4e901fdc EA |
2335 | uint64_t val; |
2336 | ||
05394f39 | 2337 | val = (uint64_t)((obj->gtt_offset + size - 4096) & |
c6642782 | 2338 | 0xfffff000) << 32; |
05394f39 CW |
2339 | val |= obj->gtt_offset & 0xfffff000; |
2340 | val |= (uint64_t)((obj->stride / 128) - 1) << | |
4e901fdc EA |
2341 | SANDYBRIDGE_FENCE_PITCH_SHIFT; |
2342 | ||
05394f39 | 2343 | if (obj->tiling_mode == I915_TILING_Y) |
4e901fdc EA |
2344 | val |= 1 << I965_FENCE_TILING_Y_SHIFT; |
2345 | val |= I965_FENCE_REG_VALID; | |
2346 | ||
c6642782 DV |
2347 | if (pipelined) { |
2348 | int ret = intel_ring_begin(pipelined, 6); | |
2349 | if (ret) | |
2350 | return ret; | |
2351 | ||
2352 | intel_ring_emit(pipelined, MI_NOOP); | |
2353 | intel_ring_emit(pipelined, MI_LOAD_REGISTER_IMM(2)); | |
2354 | intel_ring_emit(pipelined, FENCE_REG_SANDYBRIDGE_0 + regnum*8); | |
2355 | intel_ring_emit(pipelined, (u32)val); | |
2356 | intel_ring_emit(pipelined, FENCE_REG_SANDYBRIDGE_0 + regnum*8 + 4); | |
2357 | intel_ring_emit(pipelined, (u32)(val >> 32)); | |
2358 | intel_ring_advance(pipelined); | |
2359 | } else | |
2360 | I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + regnum * 8, val); | |
2361 | ||
2362 | return 0; | |
4e901fdc EA |
2363 | } |
2364 | ||
c6642782 DV |
2365 | static int i965_write_fence_reg(struct drm_i915_gem_object *obj, |
2366 | struct intel_ring_buffer *pipelined) | |
de151cf6 | 2367 | { |
05394f39 | 2368 | struct drm_device *dev = obj->base.dev; |
de151cf6 | 2369 | drm_i915_private_t *dev_priv = dev->dev_private; |
05394f39 CW |
2370 | u32 size = obj->gtt_space->size; |
2371 | int regnum = obj->fence_reg; | |
de151cf6 JB |
2372 | uint64_t val; |
2373 | ||
05394f39 | 2374 | val = (uint64_t)((obj->gtt_offset + size - 4096) & |
de151cf6 | 2375 | 0xfffff000) << 32; |
05394f39 CW |
2376 | val |= obj->gtt_offset & 0xfffff000; |
2377 | val |= ((obj->stride / 128) - 1) << I965_FENCE_PITCH_SHIFT; | |
2378 | if (obj->tiling_mode == I915_TILING_Y) | |
de151cf6 JB |
2379 | val |= 1 << I965_FENCE_TILING_Y_SHIFT; |
2380 | val |= I965_FENCE_REG_VALID; | |
2381 | ||
c6642782 DV |
2382 | if (pipelined) { |
2383 | int ret = intel_ring_begin(pipelined, 6); | |
2384 | if (ret) | |
2385 | return ret; | |
2386 | ||
2387 | intel_ring_emit(pipelined, MI_NOOP); | |
2388 | intel_ring_emit(pipelined, MI_LOAD_REGISTER_IMM(2)); | |
2389 | intel_ring_emit(pipelined, FENCE_REG_965_0 + regnum*8); | |
2390 | intel_ring_emit(pipelined, (u32)val); | |
2391 | intel_ring_emit(pipelined, FENCE_REG_965_0 + regnum*8 + 4); | |
2392 | intel_ring_emit(pipelined, (u32)(val >> 32)); | |
2393 | intel_ring_advance(pipelined); | |
2394 | } else | |
2395 | I915_WRITE64(FENCE_REG_965_0 + regnum * 8, val); | |
2396 | ||
2397 | return 0; | |
de151cf6 JB |
2398 | } |
2399 | ||
c6642782 DV |
2400 | static int i915_write_fence_reg(struct drm_i915_gem_object *obj, |
2401 | struct intel_ring_buffer *pipelined) | |
de151cf6 | 2402 | { |
05394f39 | 2403 | struct drm_device *dev = obj->base.dev; |
de151cf6 | 2404 | drm_i915_private_t *dev_priv = dev->dev_private; |
05394f39 | 2405 | u32 size = obj->gtt_space->size; |
c6642782 | 2406 | u32 fence_reg, val, pitch_val; |
0f973f27 | 2407 | int tile_width; |
de151cf6 | 2408 | |
c6642782 DV |
2409 | if (WARN((obj->gtt_offset & ~I915_FENCE_START_MASK) || |
2410 | (size & -size) != size || | |
2411 | (obj->gtt_offset & (size - 1)), | |
2412 | "object 0x%08x [fenceable? %d] not 1M or pot-size (0x%08x) aligned\n", | |
2413 | obj->gtt_offset, obj->map_and_fenceable, size)) | |
2414 | return -EINVAL; | |
de151cf6 | 2415 | |
c6642782 | 2416 | if (obj->tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev)) |
0f973f27 | 2417 | tile_width = 128; |
de151cf6 | 2418 | else |
0f973f27 JB |
2419 | tile_width = 512; |
2420 | ||
2421 | /* Note: pitch better be a power of two tile widths */ | |
05394f39 | 2422 | pitch_val = obj->stride / tile_width; |
0f973f27 | 2423 | pitch_val = ffs(pitch_val) - 1; |
de151cf6 | 2424 | |
05394f39 CW |
2425 | val = obj->gtt_offset; |
2426 | if (obj->tiling_mode == I915_TILING_Y) | |
de151cf6 | 2427 | val |= 1 << I830_FENCE_TILING_Y_SHIFT; |
a00b10c3 | 2428 | val |= I915_FENCE_SIZE_BITS(size); |
de151cf6 JB |
2429 | val |= pitch_val << I830_FENCE_PITCH_SHIFT; |
2430 | val |= I830_FENCE_REG_VALID; | |
2431 | ||
05394f39 | 2432 | fence_reg = obj->fence_reg; |
a00b10c3 CW |
2433 | if (fence_reg < 8) |
2434 | fence_reg = FENCE_REG_830_0 + fence_reg * 4; | |
dc529a4f | 2435 | else |
a00b10c3 | 2436 | fence_reg = FENCE_REG_945_8 + (fence_reg - 8) * 4; |
c6642782 DV |
2437 | |
2438 | if (pipelined) { | |
2439 | int ret = intel_ring_begin(pipelined, 4); | |
2440 | if (ret) | |
2441 | return ret; | |
2442 | ||
2443 | intel_ring_emit(pipelined, MI_NOOP); | |
2444 | intel_ring_emit(pipelined, MI_LOAD_REGISTER_IMM(1)); | |
2445 | intel_ring_emit(pipelined, fence_reg); | |
2446 | intel_ring_emit(pipelined, val); | |
2447 | intel_ring_advance(pipelined); | |
2448 | } else | |
2449 | I915_WRITE(fence_reg, val); | |
2450 | ||
2451 | return 0; | |
de151cf6 JB |
2452 | } |
2453 | ||
c6642782 DV |
2454 | static int i830_write_fence_reg(struct drm_i915_gem_object *obj, |
2455 | struct intel_ring_buffer *pipelined) | |
de151cf6 | 2456 | { |
05394f39 | 2457 | struct drm_device *dev = obj->base.dev; |
de151cf6 | 2458 | drm_i915_private_t *dev_priv = dev->dev_private; |
05394f39 CW |
2459 | u32 size = obj->gtt_space->size; |
2460 | int regnum = obj->fence_reg; | |
de151cf6 JB |
2461 | uint32_t val; |
2462 | uint32_t pitch_val; | |
2463 | ||
c6642782 DV |
2464 | if (WARN((obj->gtt_offset & ~I830_FENCE_START_MASK) || |
2465 | (size & -size) != size || | |
2466 | (obj->gtt_offset & (size - 1)), | |
2467 | "object 0x%08x not 512K or pot-size 0x%08x aligned\n", | |
2468 | obj->gtt_offset, size)) | |
2469 | return -EINVAL; | |
de151cf6 | 2470 | |
05394f39 | 2471 | pitch_val = obj->stride / 128; |
e76a16de | 2472 | pitch_val = ffs(pitch_val) - 1; |
e76a16de | 2473 | |
05394f39 CW |
2474 | val = obj->gtt_offset; |
2475 | if (obj->tiling_mode == I915_TILING_Y) | |
de151cf6 | 2476 | val |= 1 << I830_FENCE_TILING_Y_SHIFT; |
c6642782 | 2477 | val |= I830_FENCE_SIZE_BITS(size); |
de151cf6 JB |
2478 | val |= pitch_val << I830_FENCE_PITCH_SHIFT; |
2479 | val |= I830_FENCE_REG_VALID; | |
2480 | ||
c6642782 DV |
2481 | if (pipelined) { |
2482 | int ret = intel_ring_begin(pipelined, 4); | |
2483 | if (ret) | |
2484 | return ret; | |
2485 | ||
2486 | intel_ring_emit(pipelined, MI_NOOP); | |
2487 | intel_ring_emit(pipelined, MI_LOAD_REGISTER_IMM(1)); | |
2488 | intel_ring_emit(pipelined, FENCE_REG_830_0 + regnum*4); | |
2489 | intel_ring_emit(pipelined, val); | |
2490 | intel_ring_advance(pipelined); | |
2491 | } else | |
2492 | I915_WRITE(FENCE_REG_830_0 + regnum * 4, val); | |
2493 | ||
2494 | return 0; | |
de151cf6 JB |
2495 | } |
2496 | ||
2cf34d7b CW |
2497 | static int i915_find_fence_reg(struct drm_device *dev, |
2498 | bool interruptible) | |
ae3db24a | 2499 | { |
ae3db24a | 2500 | struct drm_i915_private *dev_priv = dev->dev_private; |
a00b10c3 | 2501 | struct drm_i915_fence_reg *reg; |
05394f39 | 2502 | struct drm_i915_gem_object *obj = NULL; |
ae3db24a DV |
2503 | int i, avail, ret; |
2504 | ||
2505 | /* First try to find a free reg */ | |
2506 | avail = 0; | |
2507 | for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) { | |
2508 | reg = &dev_priv->fence_regs[i]; | |
2509 | if (!reg->obj) | |
2510 | return i; | |
2511 | ||
05394f39 CW |
2512 | if (!reg->obj->pin_count) |
2513 | avail++; | |
ae3db24a DV |
2514 | } |
2515 | ||
2516 | if (avail == 0) | |
2517 | return -ENOSPC; | |
2518 | ||
2519 | /* None available, try to steal one or wait for a user to finish */ | |
a00b10c3 | 2520 | avail = I915_FENCE_REG_NONE; |
007cc8ac DV |
2521 | list_for_each_entry(reg, &dev_priv->mm.fence_list, |
2522 | lru_list) { | |
05394f39 CW |
2523 | obj = reg->obj; |
2524 | if (obj->pin_count) | |
ae3db24a DV |
2525 | continue; |
2526 | ||
2527 | /* found one! */ | |
05394f39 | 2528 | avail = obj->fence_reg; |
ae3db24a DV |
2529 | break; |
2530 | } | |
2531 | ||
a00b10c3 | 2532 | BUG_ON(avail == I915_FENCE_REG_NONE); |
ae3db24a DV |
2533 | |
2534 | /* We only have a reference on obj from the active list. put_fence_reg | |
2535 | * might drop that one, causing a use-after-free in it. So hold a | |
2536 | * private reference to obj like the other callers of put_fence_reg | |
2537 | * (set_tiling ioctl) do. */ | |
05394f39 CW |
2538 | drm_gem_object_reference(&obj->base); |
2539 | ret = i915_gem_object_put_fence_reg(obj, interruptible); | |
2540 | drm_gem_object_unreference(&obj->base); | |
ae3db24a DV |
2541 | if (ret != 0) |
2542 | return ret; | |
2543 | ||
a00b10c3 | 2544 | return avail; |
ae3db24a DV |
2545 | } |
2546 | ||
de151cf6 JB |
2547 | /** |
2548 | * i915_gem_object_get_fence_reg - set up a fence reg for an object | |
2549 | * @obj: object to map through a fence reg | |
2550 | * | |
2551 | * When mapping objects through the GTT, userspace wants to be able to write | |
2552 | * to them without having to worry about swizzling if the object is tiled. | |
2553 | * | |
2554 | * This function walks the fence regs looking for a free one for @obj, | |
2555 | * stealing one if it can't find any. | |
2556 | * | |
2557 | * It then sets up the reg based on the object's properties: address, pitch | |
2558 | * and tiling format. | |
2559 | */ | |
8c4b8c3f | 2560 | int |
05394f39 | 2561 | i915_gem_object_get_fence_reg(struct drm_i915_gem_object *obj, |
2cf34d7b | 2562 | bool interruptible) |
de151cf6 | 2563 | { |
05394f39 | 2564 | struct drm_device *dev = obj->base.dev; |
79e53945 | 2565 | struct drm_i915_private *dev_priv = dev->dev_private; |
de151cf6 | 2566 | struct drm_i915_fence_reg *reg = NULL; |
c6642782 | 2567 | struct intel_ring_buffer *pipelined = NULL; |
ae3db24a | 2568 | int ret; |
de151cf6 | 2569 | |
a09ba7fa | 2570 | /* Just update our place in the LRU if our fence is getting used. */ |
05394f39 CW |
2571 | if (obj->fence_reg != I915_FENCE_REG_NONE) { |
2572 | reg = &dev_priv->fence_regs[obj->fence_reg]; | |
007cc8ac | 2573 | list_move_tail(®->lru_list, &dev_priv->mm.fence_list); |
a09ba7fa EA |
2574 | return 0; |
2575 | } | |
2576 | ||
05394f39 | 2577 | switch (obj->tiling_mode) { |
de151cf6 JB |
2578 | case I915_TILING_NONE: |
2579 | WARN(1, "allocating a fence for non-tiled object?\n"); | |
2580 | break; | |
2581 | case I915_TILING_X: | |
05394f39 | 2582 | if (!obj->stride) |
0f973f27 | 2583 | return -EINVAL; |
05394f39 | 2584 | WARN((obj->stride & (512 - 1)), |
0f973f27 | 2585 | "object 0x%08x is X tiled but has non-512B pitch\n", |
05394f39 | 2586 | obj->gtt_offset); |
de151cf6 JB |
2587 | break; |
2588 | case I915_TILING_Y: | |
05394f39 | 2589 | if (!obj->stride) |
0f973f27 | 2590 | return -EINVAL; |
05394f39 | 2591 | WARN((obj->stride & (128 - 1)), |
0f973f27 | 2592 | "object 0x%08x is Y tiled but has non-128B pitch\n", |
05394f39 | 2593 | obj->gtt_offset); |
de151cf6 JB |
2594 | break; |
2595 | } | |
2596 | ||
2cf34d7b | 2597 | ret = i915_find_fence_reg(dev, interruptible); |
ae3db24a DV |
2598 | if (ret < 0) |
2599 | return ret; | |
de151cf6 | 2600 | |
05394f39 CW |
2601 | obj->fence_reg = ret; |
2602 | reg = &dev_priv->fence_regs[obj->fence_reg]; | |
007cc8ac | 2603 | list_add_tail(®->lru_list, &dev_priv->mm.fence_list); |
a09ba7fa | 2604 | |
de151cf6 JB |
2605 | reg->obj = obj; |
2606 | ||
e259befd CW |
2607 | switch (INTEL_INFO(dev)->gen) { |
2608 | case 6: | |
c6642782 | 2609 | ret = sandybridge_write_fence_reg(obj, pipelined); |
e259befd CW |
2610 | break; |
2611 | case 5: | |
2612 | case 4: | |
c6642782 | 2613 | ret = i965_write_fence_reg(obj, pipelined); |
e259befd CW |
2614 | break; |
2615 | case 3: | |
c6642782 | 2616 | ret = i915_write_fence_reg(obj, pipelined); |
e259befd CW |
2617 | break; |
2618 | case 2: | |
c6642782 | 2619 | ret = i830_write_fence_reg(obj, pipelined); |
e259befd CW |
2620 | break; |
2621 | } | |
d9ddcb96 | 2622 | |
a00b10c3 | 2623 | trace_i915_gem_object_get_fence(obj, |
05394f39 CW |
2624 | obj->fence_reg, |
2625 | obj->tiling_mode); | |
c6642782 | 2626 | return ret; |
de151cf6 JB |
2627 | } |
2628 | ||
2629 | /** | |
2630 | * i915_gem_clear_fence_reg - clear out fence register info | |
2631 | * @obj: object to clear | |
2632 | * | |
2633 | * Zeroes out the fence register itself and clears out the associated | |
05394f39 | 2634 | * data structures in dev_priv and obj. |
de151cf6 JB |
2635 | */ |
2636 | static void | |
05394f39 | 2637 | i915_gem_clear_fence_reg(struct drm_i915_gem_object *obj) |
de151cf6 | 2638 | { |
05394f39 | 2639 | struct drm_device *dev = obj->base.dev; |
79e53945 | 2640 | drm_i915_private_t *dev_priv = dev->dev_private; |
05394f39 | 2641 | struct drm_i915_fence_reg *reg = &dev_priv->fence_regs[obj->fence_reg]; |
e259befd | 2642 | uint32_t fence_reg; |
de151cf6 | 2643 | |
e259befd CW |
2644 | switch (INTEL_INFO(dev)->gen) { |
2645 | case 6: | |
4e901fdc | 2646 | I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + |
05394f39 | 2647 | (obj->fence_reg * 8), 0); |
e259befd CW |
2648 | break; |
2649 | case 5: | |
2650 | case 4: | |
05394f39 | 2651 | I915_WRITE64(FENCE_REG_965_0 + (obj->fence_reg * 8), 0); |
e259befd CW |
2652 | break; |
2653 | case 3: | |
05394f39 CW |
2654 | if (obj->fence_reg >= 8) |
2655 | fence_reg = FENCE_REG_945_8 + (obj->fence_reg - 8) * 4; | |
dc529a4f | 2656 | else |
e259befd | 2657 | case 2: |
05394f39 | 2658 | fence_reg = FENCE_REG_830_0 + obj->fence_reg * 4; |
dc529a4f EA |
2659 | |
2660 | I915_WRITE(fence_reg, 0); | |
e259befd | 2661 | break; |
dc529a4f | 2662 | } |
de151cf6 | 2663 | |
007cc8ac | 2664 | reg->obj = NULL; |
05394f39 | 2665 | obj->fence_reg = I915_FENCE_REG_NONE; |
007cc8ac | 2666 | list_del_init(®->lru_list); |
de151cf6 JB |
2667 | } |
2668 | ||
52dc7d32 CW |
2669 | /** |
2670 | * i915_gem_object_put_fence_reg - waits on outstanding fenced access | |
2671 | * to the buffer to finish, and then resets the fence register. | |
2672 | * @obj: tiled object holding a fence register. | |
2cf34d7b | 2673 | * @bool: whether the wait upon the fence is interruptible |
52dc7d32 CW |
2674 | * |
2675 | * Zeroes out the fence register itself and clears out the associated | |
05394f39 | 2676 | * data structures in dev_priv and obj. |
52dc7d32 CW |
2677 | */ |
2678 | int | |
05394f39 | 2679 | i915_gem_object_put_fence_reg(struct drm_i915_gem_object *obj, |
2cf34d7b | 2680 | bool interruptible) |
52dc7d32 | 2681 | { |
05394f39 | 2682 | struct drm_device *dev = obj->base.dev; |
caea7476 | 2683 | int ret; |
52dc7d32 | 2684 | |
05394f39 | 2685 | if (obj->fence_reg == I915_FENCE_REG_NONE) |
52dc7d32 CW |
2686 | return 0; |
2687 | ||
10ae9bd2 DV |
2688 | /* If we've changed tiling, GTT-mappings of the object |
2689 | * need to re-fault to ensure that the correct fence register | |
2690 | * setup is in place. | |
2691 | */ | |
2692 | i915_gem_release_mmap(obj); | |
2693 | ||
52dc7d32 CW |
2694 | /* On the i915, GPU access to tiled buffers is via a fence, |
2695 | * therefore we must wait for any outstanding access to complete | |
2696 | * before clearing the fence. | |
2697 | */ | |
caea7476 | 2698 | if (obj->fenced_gpu_access) { |
919926ae | 2699 | ret = i915_gem_object_flush_gpu_write_domain(obj, NULL); |
0bc23aad | 2700 | if (ret) |
2dafb1e0 CW |
2701 | return ret; |
2702 | ||
caea7476 CW |
2703 | obj->fenced_gpu_access = false; |
2704 | } | |
2705 | ||
2706 | if (obj->last_fenced_seqno) { | |
2707 | ret = i915_do_wait_request(dev, | |
2708 | obj->last_fenced_seqno, | |
2709 | interruptible, | |
2710 | obj->last_fenced_ring); | |
0bc23aad | 2711 | if (ret) |
52dc7d32 | 2712 | return ret; |
53640e1d | 2713 | |
caea7476 | 2714 | obj->last_fenced_seqno = false; |
52dc7d32 CW |
2715 | } |
2716 | ||
4a726612 | 2717 | i915_gem_object_flush_gtt_write_domain(obj); |
0bc23aad | 2718 | i915_gem_clear_fence_reg(obj); |
52dc7d32 CW |
2719 | |
2720 | return 0; | |
2721 | } | |
2722 | ||
673a394b EA |
2723 | /** |
2724 | * Finds free space in the GTT aperture and binds the object there. | |
2725 | */ | |
2726 | static int | |
05394f39 | 2727 | i915_gem_object_bind_to_gtt(struct drm_i915_gem_object *obj, |
920afa77 | 2728 | unsigned alignment, |
75e9e915 | 2729 | bool map_and_fenceable) |
673a394b | 2730 | { |
05394f39 | 2731 | struct drm_device *dev = obj->base.dev; |
673a394b | 2732 | drm_i915_private_t *dev_priv = dev->dev_private; |
673a394b | 2733 | struct drm_mm_node *free_space; |
a00b10c3 | 2734 | gfp_t gfpmask = __GFP_NORETRY | __GFP_NOWARN; |
5e783301 | 2735 | u32 size, fence_size, fence_alignment, unfenced_alignment; |
75e9e915 | 2736 | bool mappable, fenceable; |
07f73f69 | 2737 | int ret; |
673a394b | 2738 | |
05394f39 | 2739 | if (obj->madv != I915_MADV_WILLNEED) { |
3ef94daa CW |
2740 | DRM_ERROR("Attempting to bind a purgeable object\n"); |
2741 | return -EINVAL; | |
2742 | } | |
2743 | ||
05394f39 CW |
2744 | fence_size = i915_gem_get_gtt_size(obj); |
2745 | fence_alignment = i915_gem_get_gtt_alignment(obj); | |
2746 | unfenced_alignment = i915_gem_get_unfenced_gtt_alignment(obj); | |
a00b10c3 | 2747 | |
673a394b | 2748 | if (alignment == 0) |
5e783301 DV |
2749 | alignment = map_and_fenceable ? fence_alignment : |
2750 | unfenced_alignment; | |
75e9e915 | 2751 | if (map_and_fenceable && alignment & (fence_alignment - 1)) { |
673a394b EA |
2752 | DRM_ERROR("Invalid object alignment requested %u\n", alignment); |
2753 | return -EINVAL; | |
2754 | } | |
2755 | ||
05394f39 | 2756 | size = map_and_fenceable ? fence_size : obj->base.size; |
a00b10c3 | 2757 | |
654fc607 CW |
2758 | /* If the object is bigger than the entire aperture, reject it early |
2759 | * before evicting everything in a vain attempt to find space. | |
2760 | */ | |
05394f39 | 2761 | if (obj->base.size > |
75e9e915 | 2762 | (map_and_fenceable ? dev_priv->mm.gtt_mappable_end : dev_priv->mm.gtt_total)) { |
654fc607 CW |
2763 | DRM_ERROR("Attempting to bind an object larger than the aperture\n"); |
2764 | return -E2BIG; | |
2765 | } | |
2766 | ||
673a394b | 2767 | search_free: |
75e9e915 | 2768 | if (map_and_fenceable) |
920afa77 DV |
2769 | free_space = |
2770 | drm_mm_search_free_in_range(&dev_priv->mm.gtt_space, | |
a00b10c3 | 2771 | size, alignment, 0, |
920afa77 DV |
2772 | dev_priv->mm.gtt_mappable_end, |
2773 | 0); | |
2774 | else | |
2775 | free_space = drm_mm_search_free(&dev_priv->mm.gtt_space, | |
a00b10c3 | 2776 | size, alignment, 0); |
920afa77 DV |
2777 | |
2778 | if (free_space != NULL) { | |
75e9e915 | 2779 | if (map_and_fenceable) |
05394f39 | 2780 | obj->gtt_space = |
920afa77 | 2781 | drm_mm_get_block_range_generic(free_space, |
a00b10c3 | 2782 | size, alignment, 0, |
920afa77 DV |
2783 | dev_priv->mm.gtt_mappable_end, |
2784 | 0); | |
2785 | else | |
05394f39 | 2786 | obj->gtt_space = |
a00b10c3 | 2787 | drm_mm_get_block(free_space, size, alignment); |
920afa77 | 2788 | } |
05394f39 | 2789 | if (obj->gtt_space == NULL) { |
673a394b EA |
2790 | /* If the gtt is empty and we're still having trouble |
2791 | * fitting our object in, we're out of memory. | |
2792 | */ | |
75e9e915 DV |
2793 | ret = i915_gem_evict_something(dev, size, alignment, |
2794 | map_and_fenceable); | |
9731129c | 2795 | if (ret) |
673a394b | 2796 | return ret; |
9731129c | 2797 | |
673a394b EA |
2798 | goto search_free; |
2799 | } | |
2800 | ||
e5281ccd | 2801 | ret = i915_gem_object_get_pages_gtt(obj, gfpmask); |
673a394b | 2802 | if (ret) { |
05394f39 CW |
2803 | drm_mm_put_block(obj->gtt_space); |
2804 | obj->gtt_space = NULL; | |
07f73f69 CW |
2805 | |
2806 | if (ret == -ENOMEM) { | |
2807 | /* first try to clear up some space from the GTT */ | |
a00b10c3 | 2808 | ret = i915_gem_evict_something(dev, size, |
75e9e915 DV |
2809 | alignment, |
2810 | map_and_fenceable); | |
07f73f69 | 2811 | if (ret) { |
07f73f69 | 2812 | /* now try to shrink everyone else */ |
4bdadb97 CW |
2813 | if (gfpmask) { |
2814 | gfpmask = 0; | |
2815 | goto search_free; | |
07f73f69 CW |
2816 | } |
2817 | ||
2818 | return ret; | |
2819 | } | |
2820 | ||
2821 | goto search_free; | |
2822 | } | |
2823 | ||
673a394b EA |
2824 | return ret; |
2825 | } | |
2826 | ||
7c2e6fdf DV |
2827 | ret = i915_gem_gtt_bind_object(obj); |
2828 | if (ret) { | |
e5281ccd | 2829 | i915_gem_object_put_pages_gtt(obj); |
05394f39 CW |
2830 | drm_mm_put_block(obj->gtt_space); |
2831 | obj->gtt_space = NULL; | |
07f73f69 | 2832 | |
a00b10c3 | 2833 | ret = i915_gem_evict_something(dev, size, |
75e9e915 | 2834 | alignment, map_and_fenceable); |
9731129c | 2835 | if (ret) |
07f73f69 | 2836 | return ret; |
07f73f69 CW |
2837 | |
2838 | goto search_free; | |
673a394b | 2839 | } |
673a394b | 2840 | |
05394f39 | 2841 | obj->gtt_offset = obj->gtt_space->start; |
fb7d516a | 2842 | |
bf1a1092 | 2843 | /* keep track of bounds object by adding it to the inactive list */ |
05394f39 CW |
2844 | list_add_tail(&obj->mm_list, &dev_priv->mm.inactive_list); |
2845 | i915_gem_info_add_gtt(dev_priv, obj); | |
bf1a1092 | 2846 | |
673a394b EA |
2847 | /* Assert that the object is not currently in any GPU domain. As it |
2848 | * wasn't in the GTT, there shouldn't be any way it could have been in | |
2849 | * a GPU cache | |
2850 | */ | |
05394f39 CW |
2851 | BUG_ON(obj->base.read_domains & I915_GEM_GPU_DOMAINS); |
2852 | BUG_ON(obj->base.write_domain & I915_GEM_GPU_DOMAINS); | |
673a394b | 2853 | |
05394f39 | 2854 | trace_i915_gem_object_bind(obj, obj->gtt_offset, map_and_fenceable); |
1c5d22f7 | 2855 | |
75e9e915 | 2856 | fenceable = |
05394f39 CW |
2857 | obj->gtt_space->size == fence_size && |
2858 | (obj->gtt_space->start & (fence_alignment -1)) == 0; | |
a00b10c3 | 2859 | |
75e9e915 | 2860 | mappable = |
05394f39 | 2861 | obj->gtt_offset + obj->base.size <= dev_priv->mm.gtt_mappable_end; |
a00b10c3 | 2862 | |
05394f39 | 2863 | obj->map_and_fenceable = mappable && fenceable; |
75e9e915 | 2864 | |
673a394b EA |
2865 | return 0; |
2866 | } | |
2867 | ||
2868 | void | |
05394f39 | 2869 | i915_gem_clflush_object(struct drm_i915_gem_object *obj) |
673a394b | 2870 | { |
673a394b EA |
2871 | /* If we don't have a page list set up, then we're not pinned |
2872 | * to GPU, and we can ignore the cache flush because it'll happen | |
2873 | * again at bind time. | |
2874 | */ | |
05394f39 | 2875 | if (obj->pages == NULL) |
673a394b EA |
2876 | return; |
2877 | ||
1c5d22f7 | 2878 | trace_i915_gem_object_clflush(obj); |
cfa16a0d | 2879 | |
05394f39 | 2880 | drm_clflush_pages(obj->pages, obj->base.size / PAGE_SIZE); |
673a394b EA |
2881 | } |
2882 | ||
e47c68e9 | 2883 | /** Flushes any GPU write domain for the object if it's dirty. */ |
2dafb1e0 | 2884 | static int |
05394f39 | 2885 | i915_gem_object_flush_gpu_write_domain(struct drm_i915_gem_object *obj, |
919926ae | 2886 | struct intel_ring_buffer *pipelined) |
e47c68e9 | 2887 | { |
05394f39 | 2888 | struct drm_device *dev = obj->base.dev; |
e47c68e9 | 2889 | |
05394f39 | 2890 | if ((obj->base.write_domain & I915_GEM_GPU_DOMAINS) == 0) |
2dafb1e0 | 2891 | return 0; |
e47c68e9 EA |
2892 | |
2893 | /* Queue the GPU write cache flushing we need. */ | |
05394f39 CW |
2894 | i915_gem_flush_ring(dev, obj->ring, 0, obj->base.write_domain); |
2895 | BUG_ON(obj->base.write_domain); | |
1c5d22f7 | 2896 | |
919926ae | 2897 | if (pipelined && pipelined == obj->ring) |
ba3d8d74 DV |
2898 | return 0; |
2899 | ||
2cf34d7b | 2900 | return i915_gem_object_wait_rendering(obj, true); |
e47c68e9 EA |
2901 | } |
2902 | ||
2903 | /** Flushes the GTT write domain for the object if it's dirty. */ | |
2904 | static void | |
05394f39 | 2905 | i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj) |
e47c68e9 | 2906 | { |
1c5d22f7 CW |
2907 | uint32_t old_write_domain; |
2908 | ||
05394f39 | 2909 | if (obj->base.write_domain != I915_GEM_DOMAIN_GTT) |
e47c68e9 EA |
2910 | return; |
2911 | ||
2912 | /* No actual flushing is required for the GTT write domain. Writes | |
2913 | * to it immediately go to main memory as far as we know, so there's | |
2914 | * no chipset flush. It also doesn't land in render cache. | |
2915 | */ | |
4a684a41 CW |
2916 | i915_gem_release_mmap(obj); |
2917 | ||
05394f39 CW |
2918 | old_write_domain = obj->base.write_domain; |
2919 | obj->base.write_domain = 0; | |
1c5d22f7 CW |
2920 | |
2921 | trace_i915_gem_object_change_domain(obj, | |
05394f39 | 2922 | obj->base.read_domains, |
1c5d22f7 | 2923 | old_write_domain); |
e47c68e9 EA |
2924 | } |
2925 | ||
2926 | /** Flushes the CPU write domain for the object if it's dirty. */ | |
2927 | static void | |
05394f39 | 2928 | i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj) |
e47c68e9 | 2929 | { |
1c5d22f7 | 2930 | uint32_t old_write_domain; |
e47c68e9 | 2931 | |
05394f39 | 2932 | if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) |
e47c68e9 EA |
2933 | return; |
2934 | ||
2935 | i915_gem_clflush_object(obj); | |
40ce6575 | 2936 | intel_gtt_chipset_flush(); |
05394f39 CW |
2937 | old_write_domain = obj->base.write_domain; |
2938 | obj->base.write_domain = 0; | |
1c5d22f7 CW |
2939 | |
2940 | trace_i915_gem_object_change_domain(obj, | |
05394f39 | 2941 | obj->base.read_domains, |
1c5d22f7 | 2942 | old_write_domain); |
e47c68e9 EA |
2943 | } |
2944 | ||
2ef7eeaa EA |
2945 | /** |
2946 | * Moves a single object to the GTT read, and possibly write domain. | |
2947 | * | |
2948 | * This function returns when the move is complete, including waiting on | |
2949 | * flushes to occur. | |
2950 | */ | |
79e53945 | 2951 | int |
05394f39 | 2952 | i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, int write) |
2ef7eeaa | 2953 | { |
1c5d22f7 | 2954 | uint32_t old_write_domain, old_read_domains; |
e47c68e9 | 2955 | int ret; |
2ef7eeaa | 2956 | |
02354392 | 2957 | /* Not valid to be called on unbound objects. */ |
05394f39 | 2958 | if (obj->gtt_space == NULL) |
02354392 EA |
2959 | return -EINVAL; |
2960 | ||
919926ae | 2961 | ret = i915_gem_object_flush_gpu_write_domain(obj, NULL); |
2dafb1e0 CW |
2962 | if (ret != 0) |
2963 | return ret; | |
2964 | ||
7213342d | 2965 | i915_gem_object_flush_cpu_write_domain(obj); |
1c5d22f7 | 2966 | |
ba3d8d74 | 2967 | if (write) { |
2cf34d7b | 2968 | ret = i915_gem_object_wait_rendering(obj, true); |
ba3d8d74 DV |
2969 | if (ret) |
2970 | return ret; | |
ba3d8d74 | 2971 | } |
e47c68e9 | 2972 | |
05394f39 CW |
2973 | old_write_domain = obj->base.write_domain; |
2974 | old_read_domains = obj->base.read_domains; | |
1c5d22f7 | 2975 | |
e47c68e9 EA |
2976 | /* It should now be out of any other write domains, and we can update |
2977 | * the domain values for our changes. | |
2978 | */ | |
05394f39 CW |
2979 | BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) != 0); |
2980 | obj->base.read_domains |= I915_GEM_DOMAIN_GTT; | |
e47c68e9 | 2981 | if (write) { |
05394f39 CW |
2982 | obj->base.read_domains = I915_GEM_DOMAIN_GTT; |
2983 | obj->base.write_domain = I915_GEM_DOMAIN_GTT; | |
2984 | obj->dirty = 1; | |
2ef7eeaa EA |
2985 | } |
2986 | ||
1c5d22f7 CW |
2987 | trace_i915_gem_object_change_domain(obj, |
2988 | old_read_domains, | |
2989 | old_write_domain); | |
2990 | ||
e47c68e9 EA |
2991 | return 0; |
2992 | } | |
2993 | ||
b9241ea3 ZW |
2994 | /* |
2995 | * Prepare buffer for display plane. Use uninterruptible for possible flush | |
2996 | * wait, as in modesetting process we're not supposed to be interrupted. | |
2997 | */ | |
2998 | int | |
05394f39 | 2999 | i915_gem_object_set_to_display_plane(struct drm_i915_gem_object *obj, |
919926ae | 3000 | struct intel_ring_buffer *pipelined) |
b9241ea3 | 3001 | { |
ba3d8d74 | 3002 | uint32_t old_read_domains; |
b9241ea3 ZW |
3003 | int ret; |
3004 | ||
3005 | /* Not valid to be called on unbound objects. */ | |
05394f39 | 3006 | if (obj->gtt_space == NULL) |
b9241ea3 ZW |
3007 | return -EINVAL; |
3008 | ||
919926ae | 3009 | ret = i915_gem_object_flush_gpu_write_domain(obj, pipelined); |
2dafb1e0 CW |
3010 | if (ret) |
3011 | return ret; | |
b9241ea3 | 3012 | |
ced270fa CW |
3013 | /* Currently, we are always called from an non-interruptible context. */ |
3014 | if (!pipelined) { | |
3015 | ret = i915_gem_object_wait_rendering(obj, false); | |
3016 | if (ret) | |
b9241ea3 ZW |
3017 | return ret; |
3018 | } | |
3019 | ||
b118c1e3 CW |
3020 | i915_gem_object_flush_cpu_write_domain(obj); |
3021 | ||
05394f39 CW |
3022 | old_read_domains = obj->base.read_domains; |
3023 | obj->base.read_domains |= I915_GEM_DOMAIN_GTT; | |
b9241ea3 ZW |
3024 | |
3025 | trace_i915_gem_object_change_domain(obj, | |
3026 | old_read_domains, | |
05394f39 | 3027 | obj->base.write_domain); |
b9241ea3 ZW |
3028 | |
3029 | return 0; | |
3030 | } | |
3031 | ||
85345517 CW |
3032 | int |
3033 | i915_gem_object_flush_gpu(struct drm_i915_gem_object *obj, | |
3034 | bool interruptible) | |
3035 | { | |
3036 | if (!obj->active) | |
3037 | return 0; | |
3038 | ||
3039 | if (obj->base.write_domain & I915_GEM_GPU_DOMAINS) | |
05394f39 | 3040 | i915_gem_flush_ring(obj->base.dev, obj->ring, |
85345517 CW |
3041 | 0, obj->base.write_domain); |
3042 | ||
05394f39 | 3043 | return i915_gem_object_wait_rendering(obj, interruptible); |
85345517 CW |
3044 | } |
3045 | ||
e47c68e9 EA |
3046 | /** |
3047 | * Moves a single object to the CPU read, and possibly write domain. | |
3048 | * | |
3049 | * This function returns when the move is complete, including waiting on | |
3050 | * flushes to occur. | |
3051 | */ | |
3052 | static int | |
919926ae | 3053 | i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write) |
e47c68e9 | 3054 | { |
1c5d22f7 | 3055 | uint32_t old_write_domain, old_read_domains; |
e47c68e9 EA |
3056 | int ret; |
3057 | ||
ba3d8d74 | 3058 | ret = i915_gem_object_flush_gpu_write_domain(obj, false); |
e47c68e9 EA |
3059 | if (ret != 0) |
3060 | return ret; | |
2ef7eeaa | 3061 | |
e47c68e9 | 3062 | i915_gem_object_flush_gtt_write_domain(obj); |
2ef7eeaa | 3063 | |
e47c68e9 EA |
3064 | /* If we have a partially-valid cache of the object in the CPU, |
3065 | * finish invalidating it and free the per-page flags. | |
2ef7eeaa | 3066 | */ |
e47c68e9 | 3067 | i915_gem_object_set_to_full_cpu_read_domain(obj); |
2ef7eeaa | 3068 | |
7213342d | 3069 | if (write) { |
2cf34d7b | 3070 | ret = i915_gem_object_wait_rendering(obj, true); |
7213342d CW |
3071 | if (ret) |
3072 | return ret; | |
3073 | } | |
3074 | ||
05394f39 CW |
3075 | old_write_domain = obj->base.write_domain; |
3076 | old_read_domains = obj->base.read_domains; | |
1c5d22f7 | 3077 | |
e47c68e9 | 3078 | /* Flush the CPU cache if it's still invalid. */ |
05394f39 | 3079 | if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) { |
2ef7eeaa | 3080 | i915_gem_clflush_object(obj); |
2ef7eeaa | 3081 | |
05394f39 | 3082 | obj->base.read_domains |= I915_GEM_DOMAIN_CPU; |
2ef7eeaa EA |
3083 | } |
3084 | ||
3085 | /* It should now be out of any other write domains, and we can update | |
3086 | * the domain values for our changes. | |
3087 | */ | |
05394f39 | 3088 | BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) != 0); |
e47c68e9 EA |
3089 | |
3090 | /* If we're writing through the CPU, then the GPU read domains will | |
3091 | * need to be invalidated at next use. | |
3092 | */ | |
3093 | if (write) { | |
05394f39 CW |
3094 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; |
3095 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; | |
e47c68e9 | 3096 | } |
2ef7eeaa | 3097 | |
1c5d22f7 CW |
3098 | trace_i915_gem_object_change_domain(obj, |
3099 | old_read_domains, | |
3100 | old_write_domain); | |
3101 | ||
2ef7eeaa EA |
3102 | return 0; |
3103 | } | |
3104 | ||
673a394b EA |
3105 | /* |
3106 | * Set the next domain for the specified object. This | |
3107 | * may not actually perform the necessary flushing/invaliding though, | |
3108 | * as that may want to be batched with other set_domain operations | |
3109 | * | |
3110 | * This is (we hope) the only really tricky part of gem. The goal | |
3111 | * is fairly simple -- track which caches hold bits of the object | |
3112 | * and make sure they remain coherent. A few concrete examples may | |
3113 | * help to explain how it works. For shorthand, we use the notation | |
3114 | * (read_domains, write_domain), e.g. (CPU, CPU) to indicate the | |
3115 | * a pair of read and write domain masks. | |
3116 | * | |
3117 | * Case 1: the batch buffer | |
3118 | * | |
3119 | * 1. Allocated | |
3120 | * 2. Written by CPU | |
3121 | * 3. Mapped to GTT | |
3122 | * 4. Read by GPU | |
3123 | * 5. Unmapped from GTT | |
3124 | * 6. Freed | |
3125 | * | |
3126 | * Let's take these a step at a time | |
3127 | * | |
3128 | * 1. Allocated | |
3129 | * Pages allocated from the kernel may still have | |
3130 | * cache contents, so we set them to (CPU, CPU) always. | |
3131 | * 2. Written by CPU (using pwrite) | |
3132 | * The pwrite function calls set_domain (CPU, CPU) and | |
3133 | * this function does nothing (as nothing changes) | |
3134 | * 3. Mapped by GTT | |
3135 | * This function asserts that the object is not | |
3136 | * currently in any GPU-based read or write domains | |
3137 | * 4. Read by GPU | |
3138 | * i915_gem_execbuffer calls set_domain (COMMAND, 0). | |
3139 | * As write_domain is zero, this function adds in the | |
3140 | * current read domains (CPU+COMMAND, 0). | |
3141 | * flush_domains is set to CPU. | |
3142 | * invalidate_domains is set to COMMAND | |
3143 | * clflush is run to get data out of the CPU caches | |
3144 | * then i915_dev_set_domain calls i915_gem_flush to | |
3145 | * emit an MI_FLUSH and drm_agp_chipset_flush | |
3146 | * 5. Unmapped from GTT | |
3147 | * i915_gem_object_unbind calls set_domain (CPU, CPU) | |
3148 | * flush_domains and invalidate_domains end up both zero | |
3149 | * so no flushing/invalidating happens | |
3150 | * 6. Freed | |
3151 | * yay, done | |
3152 | * | |
3153 | * Case 2: The shared render buffer | |
3154 | * | |
3155 | * 1. Allocated | |
3156 | * 2. Mapped to GTT | |
3157 | * 3. Read/written by GPU | |
3158 | * 4. set_domain to (CPU,CPU) | |
3159 | * 5. Read/written by CPU | |
3160 | * 6. Read/written by GPU | |
3161 | * | |
3162 | * 1. Allocated | |
3163 | * Same as last example, (CPU, CPU) | |
3164 | * 2. Mapped to GTT | |
3165 | * Nothing changes (assertions find that it is not in the GPU) | |
3166 | * 3. Read/written by GPU | |
3167 | * execbuffer calls set_domain (RENDER, RENDER) | |
3168 | * flush_domains gets CPU | |
3169 | * invalidate_domains gets GPU | |
3170 | * clflush (obj) | |
3171 | * MI_FLUSH and drm_agp_chipset_flush | |
3172 | * 4. set_domain (CPU, CPU) | |
3173 | * flush_domains gets GPU | |
3174 | * invalidate_domains gets CPU | |
3175 | * wait_rendering (obj) to make sure all drawing is complete. | |
3176 | * This will include an MI_FLUSH to get the data from GPU | |
3177 | * to memory | |
3178 | * clflush (obj) to invalidate the CPU cache | |
3179 | * Another MI_FLUSH in i915_gem_flush (eliminate this somehow?) | |
3180 | * 5. Read/written by CPU | |
3181 | * cache lines are loaded and dirtied | |
3182 | * 6. Read written by GPU | |
3183 | * Same as last GPU access | |
3184 | * | |
3185 | * Case 3: The constant buffer | |
3186 | * | |
3187 | * 1. Allocated | |
3188 | * 2. Written by CPU | |
3189 | * 3. Read by GPU | |
3190 | * 4. Updated (written) by CPU again | |
3191 | * 5. Read by GPU | |
3192 | * | |
3193 | * 1. Allocated | |
3194 | * (CPU, CPU) | |
3195 | * 2. Written by CPU | |
3196 | * (CPU, CPU) | |
3197 | * 3. Read by GPU | |
3198 | * (CPU+RENDER, 0) | |
3199 | * flush_domains = CPU | |
3200 | * invalidate_domains = RENDER | |
3201 | * clflush (obj) | |
3202 | * MI_FLUSH | |
3203 | * drm_agp_chipset_flush | |
3204 | * 4. Updated (written) by CPU again | |
3205 | * (CPU, CPU) | |
3206 | * flush_domains = 0 (no previous write domain) | |
3207 | * invalidate_domains = 0 (no new read domains) | |
3208 | * 5. Read by GPU | |
3209 | * (CPU+RENDER, 0) | |
3210 | * flush_domains = CPU | |
3211 | * invalidate_domains = RENDER | |
3212 | * clflush (obj) | |
3213 | * MI_FLUSH | |
3214 | * drm_agp_chipset_flush | |
3215 | */ | |
c0d90829 | 3216 | static void |
05394f39 | 3217 | i915_gem_object_set_to_gpu_domain(struct drm_i915_gem_object *obj, |
0f8c6d7c CW |
3218 | struct intel_ring_buffer *ring, |
3219 | struct change_domains *cd) | |
673a394b | 3220 | { |
05394f39 | 3221 | uint32_t invalidate_domains = 0, flush_domains = 0; |
652c393a | 3222 | |
673a394b EA |
3223 | /* |
3224 | * If the object isn't moving to a new write domain, | |
3225 | * let the object stay in multiple read domains | |
3226 | */ | |
05394f39 CW |
3227 | if (obj->base.pending_write_domain == 0) |
3228 | obj->base.pending_read_domains |= obj->base.read_domains; | |
673a394b EA |
3229 | |
3230 | /* | |
3231 | * Flush the current write domain if | |
3232 | * the new read domains don't match. Invalidate | |
3233 | * any read domains which differ from the old | |
3234 | * write domain | |
3235 | */ | |
05394f39 | 3236 | if (obj->base.write_domain && |
caea7476 CW |
3237 | (((obj->base.write_domain != obj->base.pending_read_domains || |
3238 | obj->ring != ring)) || | |
3239 | (obj->fenced_gpu_access && !obj->pending_fenced_gpu_access))) { | |
05394f39 | 3240 | flush_domains |= obj->base.write_domain; |
8b0e378a | 3241 | invalidate_domains |= |
05394f39 | 3242 | obj->base.pending_read_domains & ~obj->base.write_domain; |
673a394b EA |
3243 | } |
3244 | /* | |
3245 | * Invalidate any read caches which may have | |
3246 | * stale data. That is, any new read domains. | |
3247 | */ | |
05394f39 | 3248 | invalidate_domains |= obj->base.pending_read_domains & ~obj->base.read_domains; |
3d2a812a | 3249 | if ((flush_domains | invalidate_domains) & I915_GEM_DOMAIN_CPU) |
673a394b | 3250 | i915_gem_clflush_object(obj); |
673a394b | 3251 | |
4a684a41 CW |
3252 | /* blow away mappings if mapped through GTT */ |
3253 | if ((flush_domains | invalidate_domains) & I915_GEM_DOMAIN_GTT) | |
3254 | i915_gem_release_mmap(obj); | |
3255 | ||
efbeed96 EA |
3256 | /* The actual obj->write_domain will be updated with |
3257 | * pending_write_domain after we emit the accumulated flush for all | |
3258 | * of our domain changes in execbuffers (which clears objects' | |
3259 | * write_domains). So if we have a current write domain that we | |
3260 | * aren't changing, set pending_write_domain to that. | |
3261 | */ | |
05394f39 CW |
3262 | if (flush_domains == 0 && obj->base.pending_write_domain == 0) |
3263 | obj->base.pending_write_domain = obj->base.write_domain; | |
673a394b | 3264 | |
0f8c6d7c CW |
3265 | cd->invalidate_domains |= invalidate_domains; |
3266 | cd->flush_domains |= flush_domains; | |
b6651458 | 3267 | if (flush_domains & I915_GEM_GPU_DOMAINS) |
05394f39 | 3268 | cd->flush_rings |= obj->ring->id; |
b6651458 | 3269 | if (invalidate_domains & I915_GEM_GPU_DOMAINS) |
0f8c6d7c | 3270 | cd->flush_rings |= ring->id; |
673a394b EA |
3271 | } |
3272 | ||
3273 | /** | |
e47c68e9 | 3274 | * Moves the object from a partially CPU read to a full one. |
673a394b | 3275 | * |
e47c68e9 EA |
3276 | * Note that this only resolves i915_gem_object_set_cpu_read_domain_range(), |
3277 | * and doesn't handle transitioning from !(read_domains & I915_GEM_DOMAIN_CPU). | |
673a394b | 3278 | */ |
e47c68e9 | 3279 | static void |
05394f39 | 3280 | i915_gem_object_set_to_full_cpu_read_domain(struct drm_i915_gem_object *obj) |
673a394b | 3281 | { |
05394f39 | 3282 | if (!obj->page_cpu_valid) |
e47c68e9 EA |
3283 | return; |
3284 | ||
3285 | /* If we're partially in the CPU read domain, finish moving it in. | |
3286 | */ | |
05394f39 | 3287 | if (obj->base.read_domains & I915_GEM_DOMAIN_CPU) { |
e47c68e9 EA |
3288 | int i; |
3289 | ||
05394f39 CW |
3290 | for (i = 0; i <= (obj->base.size - 1) / PAGE_SIZE; i++) { |
3291 | if (obj->page_cpu_valid[i]) | |
e47c68e9 | 3292 | continue; |
05394f39 | 3293 | drm_clflush_pages(obj->pages + i, 1); |
e47c68e9 | 3294 | } |
e47c68e9 EA |
3295 | } |
3296 | ||
3297 | /* Free the page_cpu_valid mappings which are now stale, whether | |
3298 | * or not we've got I915_GEM_DOMAIN_CPU. | |
3299 | */ | |
05394f39 CW |
3300 | kfree(obj->page_cpu_valid); |
3301 | obj->page_cpu_valid = NULL; | |
e47c68e9 EA |
3302 | } |
3303 | ||
3304 | /** | |
3305 | * Set the CPU read domain on a range of the object. | |
3306 | * | |
3307 | * The object ends up with I915_GEM_DOMAIN_CPU in its read flags although it's | |
3308 | * not entirely valid. The page_cpu_valid member of the object flags which | |
3309 | * pages have been flushed, and will be respected by | |
3310 | * i915_gem_object_set_to_cpu_domain() if it's called on to get a valid mapping | |
3311 | * of the whole object. | |
3312 | * | |
3313 | * This function returns when the move is complete, including waiting on | |
3314 | * flushes to occur. | |
3315 | */ | |
3316 | static int | |
05394f39 | 3317 | i915_gem_object_set_cpu_read_domain_range(struct drm_i915_gem_object *obj, |
e47c68e9 EA |
3318 | uint64_t offset, uint64_t size) |
3319 | { | |
1c5d22f7 | 3320 | uint32_t old_read_domains; |
e47c68e9 | 3321 | int i, ret; |
673a394b | 3322 | |
05394f39 | 3323 | if (offset == 0 && size == obj->base.size) |
e47c68e9 | 3324 | return i915_gem_object_set_to_cpu_domain(obj, 0); |
673a394b | 3325 | |
ba3d8d74 | 3326 | ret = i915_gem_object_flush_gpu_write_domain(obj, false); |
e47c68e9 | 3327 | if (ret != 0) |
6a47baa6 | 3328 | return ret; |
e47c68e9 EA |
3329 | i915_gem_object_flush_gtt_write_domain(obj); |
3330 | ||
3331 | /* If we're already fully in the CPU read domain, we're done. */ | |
05394f39 CW |
3332 | if (obj->page_cpu_valid == NULL && |
3333 | (obj->base.read_domains & I915_GEM_DOMAIN_CPU) != 0) | |
e47c68e9 | 3334 | return 0; |
673a394b | 3335 | |
e47c68e9 EA |
3336 | /* Otherwise, create/clear the per-page CPU read domain flag if we're |
3337 | * newly adding I915_GEM_DOMAIN_CPU | |
3338 | */ | |
05394f39 CW |
3339 | if (obj->page_cpu_valid == NULL) { |
3340 | obj->page_cpu_valid = kzalloc(obj->base.size / PAGE_SIZE, | |
3341 | GFP_KERNEL); | |
3342 | if (obj->page_cpu_valid == NULL) | |
e47c68e9 | 3343 | return -ENOMEM; |
05394f39 CW |
3344 | } else if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) |
3345 | memset(obj->page_cpu_valid, 0, obj->base.size / PAGE_SIZE); | |
673a394b EA |
3346 | |
3347 | /* Flush the cache on any pages that are still invalid from the CPU's | |
3348 | * perspective. | |
3349 | */ | |
e47c68e9 EA |
3350 | for (i = offset / PAGE_SIZE; i <= (offset + size - 1) / PAGE_SIZE; |
3351 | i++) { | |
05394f39 | 3352 | if (obj->page_cpu_valid[i]) |
673a394b EA |
3353 | continue; |
3354 | ||
05394f39 | 3355 | drm_clflush_pages(obj->pages + i, 1); |
673a394b | 3356 | |
05394f39 | 3357 | obj->page_cpu_valid[i] = 1; |
673a394b EA |
3358 | } |
3359 | ||
e47c68e9 EA |
3360 | /* It should now be out of any other write domains, and we can update |
3361 | * the domain values for our changes. | |
3362 | */ | |
05394f39 | 3363 | BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) != 0); |
e47c68e9 | 3364 | |
05394f39 CW |
3365 | old_read_domains = obj->base.read_domains; |
3366 | obj->base.read_domains |= I915_GEM_DOMAIN_CPU; | |
e47c68e9 | 3367 | |
1c5d22f7 CW |
3368 | trace_i915_gem_object_change_domain(obj, |
3369 | old_read_domains, | |
05394f39 | 3370 | obj->base.write_domain); |
1c5d22f7 | 3371 | |
673a394b EA |
3372 | return 0; |
3373 | } | |
3374 | ||
673a394b | 3375 | static int |
bcf50e27 CW |
3376 | i915_gem_execbuffer_relocate_entry(struct drm_i915_gem_object *obj, |
3377 | struct drm_file *file_priv, | |
3378 | struct drm_i915_gem_exec_object2 *entry, | |
3379 | struct drm_i915_gem_relocation_entry *reloc) | |
673a394b | 3380 | { |
9af90d19 | 3381 | struct drm_device *dev = obj->base.dev; |
bcf50e27 CW |
3382 | struct drm_gem_object *target_obj; |
3383 | uint32_t target_offset; | |
3384 | int ret = -EINVAL; | |
673a394b | 3385 | |
bcf50e27 CW |
3386 | target_obj = drm_gem_object_lookup(dev, file_priv, |
3387 | reloc->target_handle); | |
3388 | if (target_obj == NULL) | |
3389 | return -ENOENT; | |
673a394b | 3390 | |
bcf50e27 | 3391 | target_offset = to_intel_bo(target_obj)->gtt_offset; |
76446cac | 3392 | |
bcf50e27 CW |
3393 | #if WATCH_RELOC |
3394 | DRM_INFO("%s: obj %p offset %08x target %d " | |
3395 | "read %08x write %08x gtt %08x " | |
3396 | "presumed %08x delta %08x\n", | |
3397 | __func__, | |
3398 | obj, | |
3399 | (int) reloc->offset, | |
3400 | (int) reloc->target_handle, | |
3401 | (int) reloc->read_domains, | |
3402 | (int) reloc->write_domain, | |
3403 | (int) target_offset, | |
3404 | (int) reloc->presumed_offset, | |
3405 | reloc->delta); | |
3406 | #endif | |
673a394b | 3407 | |
bcf50e27 CW |
3408 | /* The target buffer should have appeared before us in the |
3409 | * exec_object list, so it should have a GTT space bound by now. | |
3410 | */ | |
3411 | if (target_offset == 0) { | |
3412 | DRM_ERROR("No GTT space found for object %d\n", | |
3413 | reloc->target_handle); | |
3414 | goto err; | |
3415 | } | |
9af90d19 | 3416 | |
bcf50e27 CW |
3417 | /* Validate that the target is in a valid r/w GPU domain */ |
3418 | if (reloc->write_domain & (reloc->write_domain - 1)) { | |
3419 | DRM_ERROR("reloc with multiple write domains: " | |
3420 | "obj %p target %d offset %d " | |
3421 | "read %08x write %08x", | |
3422 | obj, reloc->target_handle, | |
3423 | (int) reloc->offset, | |
3424 | reloc->read_domains, | |
3425 | reloc->write_domain); | |
3426 | goto err; | |
3427 | } | |
3428 | if (reloc->write_domain & I915_GEM_DOMAIN_CPU || | |
3429 | reloc->read_domains & I915_GEM_DOMAIN_CPU) { | |
3430 | DRM_ERROR("reloc with read/write CPU domains: " | |
3431 | "obj %p target %d offset %d " | |
3432 | "read %08x write %08x", | |
3433 | obj, reloc->target_handle, | |
3434 | (int) reloc->offset, | |
3435 | reloc->read_domains, | |
3436 | reloc->write_domain); | |
3437 | goto err; | |
3438 | } | |
3439 | if (reloc->write_domain && target_obj->pending_write_domain && | |
3440 | reloc->write_domain != target_obj->pending_write_domain) { | |
3441 | DRM_ERROR("Write domain conflict: " | |
3442 | "obj %p target %d offset %d " | |
3443 | "new %08x old %08x\n", | |
3444 | obj, reloc->target_handle, | |
3445 | (int) reloc->offset, | |
3446 | reloc->write_domain, | |
3447 | target_obj->pending_write_domain); | |
3448 | goto err; | |
3449 | } | |
673a394b | 3450 | |
bcf50e27 CW |
3451 | target_obj->pending_read_domains |= reloc->read_domains; |
3452 | target_obj->pending_write_domain |= reloc->write_domain; | |
8542a0bb | 3453 | |
bcf50e27 CW |
3454 | /* If the relocation already has the right value in it, no |
3455 | * more work needs to be done. | |
3456 | */ | |
3457 | if (target_offset == reloc->presumed_offset) | |
3458 | goto out; | |
673a394b | 3459 | |
bcf50e27 CW |
3460 | /* Check that the relocation address is valid... */ |
3461 | if (reloc->offset > obj->base.size - 4) { | |
3462 | DRM_ERROR("Relocation beyond object bounds: " | |
3463 | "obj %p target %d offset %d size %d.\n", | |
3464 | obj, reloc->target_handle, | |
3465 | (int) reloc->offset, | |
3466 | (int) obj->base.size); | |
3467 | goto err; | |
3468 | } | |
3469 | if (reloc->offset & 3) { | |
3470 | DRM_ERROR("Relocation not 4-byte aligned: " | |
3471 | "obj %p target %d offset %d.\n", | |
3472 | obj, reloc->target_handle, | |
3473 | (int) reloc->offset); | |
3474 | goto err; | |
3475 | } | |
673a394b | 3476 | |
bcf50e27 CW |
3477 | /* and points to somewhere within the target object. */ |
3478 | if (reloc->delta >= target_obj->size) { | |
3479 | DRM_ERROR("Relocation beyond target object bounds: " | |
3480 | "obj %p target %d delta %d size %d.\n", | |
3481 | obj, reloc->target_handle, | |
3482 | (int) reloc->delta, | |
3483 | (int) target_obj->size); | |
3484 | goto err; | |
3485 | } | |
673a394b | 3486 | |
bcf50e27 CW |
3487 | reloc->delta += target_offset; |
3488 | if (obj->base.write_domain == I915_GEM_DOMAIN_CPU) { | |
3489 | uint32_t page_offset = reloc->offset & ~PAGE_MASK; | |
3490 | char *vaddr; | |
673a394b | 3491 | |
bcf50e27 CW |
3492 | vaddr = kmap_atomic(obj->pages[reloc->offset >> PAGE_SHIFT]); |
3493 | *(uint32_t *)(vaddr + page_offset) = reloc->delta; | |
3494 | kunmap_atomic(vaddr); | |
3495 | } else { | |
3496 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3497 | uint32_t __iomem *reloc_entry; | |
3498 | void __iomem *reloc_page; | |
8542a0bb | 3499 | |
05394f39 | 3500 | ret = i915_gem_object_set_to_gtt_domain(obj, 1); |
bcf50e27 CW |
3501 | if (ret) |
3502 | goto err; | |
673a394b | 3503 | |
bcf50e27 CW |
3504 | /* Map the page containing the relocation we're going to perform. */ |
3505 | reloc->offset += obj->gtt_offset; | |
3506 | reloc_page = io_mapping_map_atomic_wc(dev_priv->mm.gtt_mapping, | |
3507 | reloc->offset & PAGE_MASK); | |
3508 | reloc_entry = (uint32_t __iomem *) | |
3509 | (reloc_page + (reloc->offset & ~PAGE_MASK)); | |
3510 | iowrite32(reloc->delta, reloc_entry); | |
3511 | io_mapping_unmap_atomic(reloc_page); | |
3512 | } | |
673a394b | 3513 | |
bcf50e27 CW |
3514 | /* and update the user's relocation entry */ |
3515 | reloc->presumed_offset = target_offset; | |
b962442e | 3516 | |
bcf50e27 CW |
3517 | out: |
3518 | ret = 0; | |
3519 | err: | |
3520 | drm_gem_object_unreference(target_obj); | |
3521 | return ret; | |
3522 | } | |
b962442e | 3523 | |
bcf50e27 CW |
3524 | static int |
3525 | i915_gem_execbuffer_relocate_object(struct drm_i915_gem_object *obj, | |
3526 | struct drm_file *file_priv, | |
3527 | struct drm_i915_gem_exec_object2 *entry) | |
3528 | { | |
3529 | struct drm_i915_gem_relocation_entry __user *user_relocs; | |
3530 | int i, ret; | |
3531 | ||
3532 | user_relocs = (void __user *)(uintptr_t)entry->relocs_ptr; | |
3533 | for (i = 0; i < entry->relocation_count; i++) { | |
3534 | struct drm_i915_gem_relocation_entry reloc; | |
3535 | ||
3536 | if (__copy_from_user_inatomic(&reloc, | |
3537 | user_relocs+i, | |
3538 | sizeof(reloc))) | |
3539 | return -EFAULT; | |
3540 | ||
3541 | ret = i915_gem_execbuffer_relocate_entry(obj, file_priv, entry, &reloc); | |
3542 | if (ret) | |
3543 | return ret; | |
b962442e | 3544 | |
b5dc608c | 3545 | if (__copy_to_user_inatomic(&user_relocs[i].presumed_offset, |
bcf50e27 CW |
3546 | &reloc.presumed_offset, |
3547 | sizeof(reloc.presumed_offset))) | |
3548 | return -EFAULT; | |
b962442e | 3549 | } |
b962442e | 3550 | |
bcf50e27 CW |
3551 | return 0; |
3552 | } | |
3553 | ||
3554 | static int | |
3555 | i915_gem_execbuffer_relocate_object_slow(struct drm_i915_gem_object *obj, | |
3556 | struct drm_file *file_priv, | |
3557 | struct drm_i915_gem_exec_object2 *entry, | |
3558 | struct drm_i915_gem_relocation_entry *relocs) | |
3559 | { | |
3560 | int i, ret; | |
3561 | ||
3562 | for (i = 0; i < entry->relocation_count; i++) { | |
3563 | ret = i915_gem_execbuffer_relocate_entry(obj, file_priv, entry, &relocs[i]); | |
3564 | if (ret) | |
3565 | return ret; | |
3566 | } | |
3567 | ||
3568 | return 0; | |
673a394b EA |
3569 | } |
3570 | ||
40a5f0de | 3571 | static int |
bcf50e27 CW |
3572 | i915_gem_execbuffer_relocate(struct drm_device *dev, |
3573 | struct drm_file *file, | |
05394f39 | 3574 | struct drm_i915_gem_object **object_list, |
bcf50e27 CW |
3575 | struct drm_i915_gem_exec_object2 *exec_list, |
3576 | int count) | |
3577 | { | |
3578 | int i, ret; | |
3579 | ||
3580 | for (i = 0; i < count; i++) { | |
05394f39 | 3581 | struct drm_i915_gem_object *obj = object_list[i]; |
bcf50e27 CW |
3582 | obj->base.pending_read_domains = 0; |
3583 | obj->base.pending_write_domain = 0; | |
3584 | ret = i915_gem_execbuffer_relocate_object(obj, file, | |
3585 | &exec_list[i]); | |
3586 | if (ret) | |
3587 | return ret; | |
3588 | } | |
3589 | ||
3590 | return 0; | |
673a394b EA |
3591 | } |
3592 | ||
40a5f0de | 3593 | static int |
bcf50e27 CW |
3594 | i915_gem_execbuffer_reserve(struct drm_device *dev, |
3595 | struct drm_file *file, | |
05394f39 | 3596 | struct drm_i915_gem_object **object_list, |
bcf50e27 CW |
3597 | struct drm_i915_gem_exec_object2 *exec_list, |
3598 | int count) | |
40a5f0de | 3599 | { |
9af90d19 | 3600 | int ret, i, retry; |
40a5f0de | 3601 | |
a7a09aeb CW |
3602 | /* Attempt to pin all of the buffers into the GTT. |
3603 | * This is done in 3 phases: | |
3604 | * | |
3605 | * 1a. Unbind all objects that do not match the GTT constraints for | |
3606 | * the execbuffer (fenceable, mappable, alignment etc). | |
3607 | * 1b. Increment pin count for already bound objects. | |
3608 | * 2. Bind new objects. | |
3609 | * 3. Decrement pin count. | |
3610 | * | |
3611 | * This avoid unnecessary unbinding of later objects in order to makr | |
3612 | * room for the earlier objects *unless* we need to defragment. | |
3613 | */ | |
5eac3ab4 CW |
3614 | retry = 0; |
3615 | do { | |
9af90d19 | 3616 | ret = 0; |
a7a09aeb CW |
3617 | |
3618 | /* Unbind any ill-fitting objects or pin. */ | |
9af90d19 | 3619 | for (i = 0; i < count; i++) { |
05394f39 | 3620 | struct drm_i915_gem_object *obj = object_list[i]; |
a7a09aeb CW |
3621 | struct drm_i915_gem_exec_object2 *entry = &exec_list[i]; |
3622 | bool need_fence, need_mappable; | |
3623 | ||
3624 | if (!obj->gtt_space) | |
3625 | continue; | |
3626 | ||
3627 | need_fence = | |
9af90d19 CW |
3628 | entry->flags & EXEC_OBJECT_NEEDS_FENCE && |
3629 | obj->tiling_mode != I915_TILING_NONE; | |
a7a09aeb | 3630 | need_mappable = |
16e809ac DV |
3631 | entry->relocation_count ? true : need_fence; |
3632 | ||
a7a09aeb CW |
3633 | if ((entry->alignment && obj->gtt_offset & (entry->alignment - 1)) || |
3634 | (need_mappable && !obj->map_and_fenceable)) | |
05394f39 | 3635 | ret = i915_gem_object_unbind(obj); |
a7a09aeb CW |
3636 | else |
3637 | ret = i915_gem_object_pin(obj, | |
3638 | entry->alignment, | |
3639 | need_mappable); | |
3640 | if (ret) { | |
3641 | count = i; | |
3642 | goto err; | |
3643 | } | |
3644 | } | |
3645 | ||
3646 | /* Bind fresh objects */ | |
3647 | for (i = 0; i < count; i++) { | |
3648 | struct drm_i915_gem_exec_object2 *entry = &exec_list[i]; | |
3649 | struct drm_i915_gem_object *obj = object_list[i]; | |
3650 | bool need_fence; | |
3651 | ||
3652 | need_fence = | |
3653 | entry->flags & EXEC_OBJECT_NEEDS_FENCE && | |
3654 | obj->tiling_mode != I915_TILING_NONE; | |
3655 | ||
3656 | if (!obj->gtt_space) { | |
3657 | bool need_mappable = | |
3658 | entry->relocation_count ? true : need_fence; | |
3659 | ||
3660 | ret = i915_gem_object_pin(obj, | |
3661 | entry->alignment, | |
3662 | need_mappable); | |
9af90d19 CW |
3663 | if (ret) |
3664 | break; | |
3665 | } | |
40a5f0de | 3666 | |
9af90d19 | 3667 | if (need_fence) { |
05394f39 | 3668 | ret = i915_gem_object_get_fence_reg(obj, true); |
a7a09aeb | 3669 | if (ret) |
9af90d19 | 3670 | break; |
40a5f0de | 3671 | |
caea7476 | 3672 | obj->pending_fenced_gpu_access = true; |
9af90d19 | 3673 | } |
40a5f0de | 3674 | |
9af90d19 | 3675 | entry->offset = obj->gtt_offset; |
40a5f0de EA |
3676 | } |
3677 | ||
a7a09aeb CW |
3678 | err: /* Decrement pin count for bound objects */ |
3679 | for (i = 0; i < count; i++) { | |
3680 | struct drm_i915_gem_object *obj = object_list[i]; | |
3681 | if (obj->gtt_space) | |
3682 | i915_gem_object_unpin(obj); | |
3683 | } | |
9af90d19 | 3684 | |
5eac3ab4 | 3685 | if (ret != -ENOSPC || retry > 1) |
9af90d19 CW |
3686 | return ret; |
3687 | ||
5eac3ab4 CW |
3688 | /* First attempt, just clear anything that is purgeable. |
3689 | * Second attempt, clear the entire GTT. | |
3690 | */ | |
3691 | ret = i915_gem_evict_everything(dev, retry == 0); | |
9af90d19 CW |
3692 | if (ret) |
3693 | return ret; | |
40a5f0de | 3694 | |
5eac3ab4 CW |
3695 | retry++; |
3696 | } while (1); | |
40a5f0de EA |
3697 | } |
3698 | ||
bcf50e27 CW |
3699 | static int |
3700 | i915_gem_execbuffer_relocate_slow(struct drm_device *dev, | |
3701 | struct drm_file *file, | |
05394f39 | 3702 | struct drm_i915_gem_object **object_list, |
bcf50e27 CW |
3703 | struct drm_i915_gem_exec_object2 *exec_list, |
3704 | int count) | |
3705 | { | |
3706 | struct drm_i915_gem_relocation_entry *reloc; | |
3707 | int i, total, ret; | |
3708 | ||
05394f39 CW |
3709 | for (i = 0; i < count; i++) |
3710 | object_list[i]->in_execbuffer = false; | |
bcf50e27 CW |
3711 | |
3712 | mutex_unlock(&dev->struct_mutex); | |
3713 | ||
3714 | total = 0; | |
3715 | for (i = 0; i < count; i++) | |
3716 | total += exec_list[i].relocation_count; | |
3717 | ||
3718 | reloc = drm_malloc_ab(total, sizeof(*reloc)); | |
3719 | if (reloc == NULL) { | |
3720 | mutex_lock(&dev->struct_mutex); | |
3721 | return -ENOMEM; | |
3722 | } | |
3723 | ||
3724 | total = 0; | |
3725 | for (i = 0; i < count; i++) { | |
3726 | struct drm_i915_gem_relocation_entry __user *user_relocs; | |
3727 | ||
3728 | user_relocs = (void __user *)(uintptr_t)exec_list[i].relocs_ptr; | |
3729 | ||
3730 | if (copy_from_user(reloc+total, user_relocs, | |
3731 | exec_list[i].relocation_count * | |
3732 | sizeof(*reloc))) { | |
3733 | ret = -EFAULT; | |
3734 | mutex_lock(&dev->struct_mutex); | |
3735 | goto err; | |
3736 | } | |
3737 | ||
3738 | total += exec_list[i].relocation_count; | |
3739 | } | |
3740 | ||
3741 | ret = i915_mutex_lock_interruptible(dev); | |
3742 | if (ret) { | |
3743 | mutex_lock(&dev->struct_mutex); | |
3744 | goto err; | |
3745 | } | |
3746 | ||
3747 | ret = i915_gem_execbuffer_reserve(dev, file, | |
3748 | object_list, exec_list, | |
3749 | count); | |
3750 | if (ret) | |
3751 | goto err; | |
3752 | ||
3753 | total = 0; | |
3754 | for (i = 0; i < count; i++) { | |
05394f39 | 3755 | struct drm_i915_gem_object *obj = object_list[i]; |
bcf50e27 CW |
3756 | obj->base.pending_read_domains = 0; |
3757 | obj->base.pending_write_domain = 0; | |
3758 | ret = i915_gem_execbuffer_relocate_object_slow(obj, file, | |
3759 | &exec_list[i], | |
3760 | reloc + total); | |
3761 | if (ret) | |
3762 | goto err; | |
3763 | ||
3764 | total += exec_list[i].relocation_count; | |
3765 | } | |
3766 | ||
3767 | /* Leave the user relocations as are, this is the painfully slow path, | |
3768 | * and we want to avoid the complication of dropping the lock whilst | |
3769 | * having buffers reserved in the aperture and so causing spurious | |
3770 | * ENOSPC for random operations. | |
3771 | */ | |
3772 | ||
3773 | err: | |
3774 | drm_free_large(reloc); | |
3775 | return ret; | |
3776 | } | |
3777 | ||
13b29289 CW |
3778 | static int |
3779 | i915_gem_execbuffer_move_to_gpu(struct drm_device *dev, | |
3780 | struct drm_file *file, | |
3781 | struct intel_ring_buffer *ring, | |
05394f39 | 3782 | struct drm_i915_gem_object **objects, |
13b29289 CW |
3783 | int count) |
3784 | { | |
0f8c6d7c | 3785 | struct change_domains cd; |
13b29289 CW |
3786 | int ret, i; |
3787 | ||
0f8c6d7c CW |
3788 | cd.invalidate_domains = 0; |
3789 | cd.flush_domains = 0; | |
3790 | cd.flush_rings = 0; | |
13b29289 | 3791 | for (i = 0; i < count; i++) |
0f8c6d7c | 3792 | i915_gem_object_set_to_gpu_domain(objects[i], ring, &cd); |
13b29289 | 3793 | |
0f8c6d7c | 3794 | if (cd.invalidate_domains | cd.flush_domains) { |
13b29289 CW |
3795 | #if WATCH_EXEC |
3796 | DRM_INFO("%s: invalidate_domains %08x flush_domains %08x\n", | |
3797 | __func__, | |
0f8c6d7c CW |
3798 | cd.invalidate_domains, |
3799 | cd.flush_domains); | |
13b29289 | 3800 | #endif |
05394f39 | 3801 | i915_gem_flush(dev, |
0f8c6d7c CW |
3802 | cd.invalidate_domains, |
3803 | cd.flush_domains, | |
3804 | cd.flush_rings); | |
13b29289 CW |
3805 | } |
3806 | ||
3807 | for (i = 0; i < count; i++) { | |
05394f39 | 3808 | struct drm_i915_gem_object *obj = objects[i]; |
13b29289 CW |
3809 | /* XXX replace with semaphores */ |
3810 | if (obj->ring && ring != obj->ring) { | |
05394f39 | 3811 | ret = i915_gem_object_wait_rendering(obj, true); |
13b29289 CW |
3812 | if (ret) |
3813 | return ret; | |
3814 | } | |
3815 | } | |
3816 | ||
3817 | return 0; | |
3818 | } | |
3819 | ||
673a394b EA |
3820 | /* Throttle our rendering by waiting until the ring has completed our requests |
3821 | * emitted over 20 msec ago. | |
3822 | * | |
b962442e EA |
3823 | * Note that if we were to use the current jiffies each time around the loop, |
3824 | * we wouldn't escape the function with any frames outstanding if the time to | |
3825 | * render a frame was over 20ms. | |
3826 | * | |
673a394b EA |
3827 | * This should get us reasonable parallelism between CPU and GPU but also |
3828 | * relatively low latency when blocking on a particular request to finish. | |
3829 | */ | |
40a5f0de | 3830 | static int |
f787a5f5 | 3831 | i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file) |
40a5f0de | 3832 | { |
f787a5f5 CW |
3833 | struct drm_i915_private *dev_priv = dev->dev_private; |
3834 | struct drm_i915_file_private *file_priv = file->driver_priv; | |
b962442e | 3835 | unsigned long recent_enough = jiffies - msecs_to_jiffies(20); |
f787a5f5 CW |
3836 | struct drm_i915_gem_request *request; |
3837 | struct intel_ring_buffer *ring = NULL; | |
3838 | u32 seqno = 0; | |
3839 | int ret; | |
93533c29 | 3840 | |
1c25595f | 3841 | spin_lock(&file_priv->mm.lock); |
f787a5f5 | 3842 | list_for_each_entry(request, &file_priv->mm.request_list, client_list) { |
b962442e EA |
3843 | if (time_after_eq(request->emitted_jiffies, recent_enough)) |
3844 | break; | |
40a5f0de | 3845 | |
f787a5f5 CW |
3846 | ring = request->ring; |
3847 | seqno = request->seqno; | |
b962442e | 3848 | } |
1c25595f | 3849 | spin_unlock(&file_priv->mm.lock); |
40a5f0de | 3850 | |
f787a5f5 CW |
3851 | if (seqno == 0) |
3852 | return 0; | |
2bc43b5c | 3853 | |
f787a5f5 | 3854 | ret = 0; |
78501eac | 3855 | if (!i915_seqno_passed(ring->get_seqno(ring), seqno)) { |
f787a5f5 CW |
3856 | /* And wait for the seqno passing without holding any locks and |
3857 | * causing extra latency for others. This is safe as the irq | |
3858 | * generation is designed to be run atomically and so is | |
3859 | * lockless. | |
3860 | */ | |
78501eac | 3861 | ring->user_irq_get(ring); |
f787a5f5 | 3862 | ret = wait_event_interruptible(ring->irq_queue, |
78501eac | 3863 | i915_seqno_passed(ring->get_seqno(ring), seqno) |
f787a5f5 | 3864 | || atomic_read(&dev_priv->mm.wedged)); |
78501eac | 3865 | ring->user_irq_put(ring); |
40a5f0de | 3866 | |
f787a5f5 CW |
3867 | if (ret == 0 && atomic_read(&dev_priv->mm.wedged)) |
3868 | ret = -EIO; | |
40a5f0de EA |
3869 | } |
3870 | ||
f787a5f5 CW |
3871 | if (ret == 0) |
3872 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, 0); | |
40a5f0de EA |
3873 | |
3874 | return ret; | |
3875 | } | |
3876 | ||
83d60795 | 3877 | static int |
2549d6c2 CW |
3878 | i915_gem_check_execbuffer(struct drm_i915_gem_execbuffer2 *exec, |
3879 | uint64_t exec_offset) | |
83d60795 CW |
3880 | { |
3881 | uint32_t exec_start, exec_len; | |
3882 | ||
3883 | exec_start = (uint32_t) exec_offset + exec->batch_start_offset; | |
3884 | exec_len = (uint32_t) exec->batch_len; | |
3885 | ||
3886 | if ((exec_start | exec_len) & 0x7) | |
3887 | return -EINVAL; | |
3888 | ||
3889 | if (!exec_start) | |
3890 | return -EINVAL; | |
3891 | ||
3892 | return 0; | |
3893 | } | |
3894 | ||
6b95a207 | 3895 | static int |
2549d6c2 CW |
3896 | validate_exec_list(struct drm_i915_gem_exec_object2 *exec, |
3897 | int count) | |
6b95a207 | 3898 | { |
2549d6c2 | 3899 | int i; |
6b95a207 | 3900 | |
2549d6c2 CW |
3901 | for (i = 0; i < count; i++) { |
3902 | char __user *ptr = (char __user *)(uintptr_t)exec[i].relocs_ptr; | |
d1d78830 | 3903 | int length; /* limited by fault_in_pages_readable() */ |
6b95a207 | 3904 | |
d1d78830 CW |
3905 | /* First check for malicious input causing overflow */ |
3906 | if (exec[i].relocation_count > | |
3907 | INT_MAX / sizeof(struct drm_i915_gem_relocation_entry)) | |
3908 | return -EINVAL; | |
6b95a207 | 3909 | |
d1d78830 CW |
3910 | length = exec[i].relocation_count * |
3911 | sizeof(struct drm_i915_gem_relocation_entry); | |
2549d6c2 CW |
3912 | if (!access_ok(VERIFY_READ, ptr, length)) |
3913 | return -EFAULT; | |
40a5f0de | 3914 | |
b5dc608c CW |
3915 | /* we may also need to update the presumed offsets */ |
3916 | if (!access_ok(VERIFY_WRITE, ptr, length)) | |
3917 | return -EFAULT; | |
3918 | ||
2549d6c2 CW |
3919 | if (fault_in_pages_readable(ptr, length)) |
3920 | return -EFAULT; | |
6b95a207 | 3921 | } |
6b95a207 | 3922 | |
83d60795 | 3923 | return 0; |
6b95a207 KH |
3924 | } |
3925 | ||
8dc5d147 | 3926 | static int |
76446cac | 3927 | i915_gem_do_execbuffer(struct drm_device *dev, void *data, |
9af90d19 | 3928 | struct drm_file *file, |
76446cac JB |
3929 | struct drm_i915_gem_execbuffer2 *args, |
3930 | struct drm_i915_gem_exec_object2 *exec_list) | |
673a394b EA |
3931 | { |
3932 | drm_i915_private_t *dev_priv = dev->dev_private; | |
05394f39 CW |
3933 | struct drm_i915_gem_object **object_list = NULL; |
3934 | struct drm_i915_gem_object *batch_obj; | |
201361a5 | 3935 | struct drm_clip_rect *cliprects = NULL; |
8dc5d147 | 3936 | struct drm_i915_gem_request *request = NULL; |
9af90d19 | 3937 | int ret, i, flips; |
673a394b | 3938 | uint64_t exec_offset; |
673a394b | 3939 | |
852835f3 ZN |
3940 | struct intel_ring_buffer *ring = NULL; |
3941 | ||
30dbf0c0 CW |
3942 | ret = i915_gem_check_is_wedged(dev); |
3943 | if (ret) | |
3944 | return ret; | |
3945 | ||
2549d6c2 CW |
3946 | ret = validate_exec_list(exec_list, args->buffer_count); |
3947 | if (ret) | |
3948 | return ret; | |
3949 | ||
673a394b EA |
3950 | #if WATCH_EXEC |
3951 | DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n", | |
3952 | (int) args->buffers_ptr, args->buffer_count, args->batch_len); | |
3953 | #endif | |
549f7365 CW |
3954 | switch (args->flags & I915_EXEC_RING_MASK) { |
3955 | case I915_EXEC_DEFAULT: | |
3956 | case I915_EXEC_RENDER: | |
3957 | ring = &dev_priv->render_ring; | |
3958 | break; | |
3959 | case I915_EXEC_BSD: | |
d1b851fc | 3960 | if (!HAS_BSD(dev)) { |
549f7365 | 3961 | DRM_ERROR("execbuf with invalid ring (BSD)\n"); |
d1b851fc ZN |
3962 | return -EINVAL; |
3963 | } | |
3964 | ring = &dev_priv->bsd_ring; | |
549f7365 CW |
3965 | break; |
3966 | case I915_EXEC_BLT: | |
3967 | if (!HAS_BLT(dev)) { | |
3968 | DRM_ERROR("execbuf with invalid ring (BLT)\n"); | |
3969 | return -EINVAL; | |
3970 | } | |
3971 | ring = &dev_priv->blt_ring; | |
3972 | break; | |
3973 | default: | |
3974 | DRM_ERROR("execbuf with unknown ring: %d\n", | |
3975 | (int)(args->flags & I915_EXEC_RING_MASK)); | |
3976 | return -EINVAL; | |
d1b851fc ZN |
3977 | } |
3978 | ||
4f481ed2 EA |
3979 | if (args->buffer_count < 1) { |
3980 | DRM_ERROR("execbuf with %d buffers\n", args->buffer_count); | |
3981 | return -EINVAL; | |
3982 | } | |
c8e0f93a | 3983 | object_list = drm_malloc_ab(sizeof(*object_list), args->buffer_count); |
76446cac JB |
3984 | if (object_list == NULL) { |
3985 | DRM_ERROR("Failed to allocate object list for %d buffers\n", | |
673a394b EA |
3986 | args->buffer_count); |
3987 | ret = -ENOMEM; | |
3988 | goto pre_mutex_err; | |
3989 | } | |
673a394b | 3990 | |
201361a5 | 3991 | if (args->num_cliprects != 0) { |
9a298b2a EA |
3992 | cliprects = kcalloc(args->num_cliprects, sizeof(*cliprects), |
3993 | GFP_KERNEL); | |
a40e8d31 OA |
3994 | if (cliprects == NULL) { |
3995 | ret = -ENOMEM; | |
201361a5 | 3996 | goto pre_mutex_err; |
a40e8d31 | 3997 | } |
201361a5 EA |
3998 | |
3999 | ret = copy_from_user(cliprects, | |
4000 | (struct drm_clip_rect __user *) | |
4001 | (uintptr_t) args->cliprects_ptr, | |
4002 | sizeof(*cliprects) * args->num_cliprects); | |
4003 | if (ret != 0) { | |
4004 | DRM_ERROR("copy %d cliprects failed: %d\n", | |
4005 | args->num_cliprects, ret); | |
c877cdce | 4006 | ret = -EFAULT; |
201361a5 EA |
4007 | goto pre_mutex_err; |
4008 | } | |
4009 | } | |
4010 | ||
8dc5d147 CW |
4011 | request = kzalloc(sizeof(*request), GFP_KERNEL); |
4012 | if (request == NULL) { | |
4013 | ret = -ENOMEM; | |
40a5f0de | 4014 | goto pre_mutex_err; |
8dc5d147 | 4015 | } |
40a5f0de | 4016 | |
76c1dec1 CW |
4017 | ret = i915_mutex_lock_interruptible(dev); |
4018 | if (ret) | |
a198bc80 | 4019 | goto pre_mutex_err; |
673a394b EA |
4020 | |
4021 | if (dev_priv->mm.suspended) { | |
673a394b | 4022 | mutex_unlock(&dev->struct_mutex); |
a198bc80 CW |
4023 | ret = -EBUSY; |
4024 | goto pre_mutex_err; | |
673a394b EA |
4025 | } |
4026 | ||
ac94a962 | 4027 | /* Look up object handles */ |
673a394b | 4028 | for (i = 0; i < args->buffer_count; i++) { |
05394f39 | 4029 | struct drm_i915_gem_object *obj; |
7e318e18 | 4030 | |
05394f39 CW |
4031 | obj = to_intel_bo (drm_gem_object_lookup(dev, file, |
4032 | exec_list[i].handle)); | |
4033 | if (obj == NULL) { | |
673a394b EA |
4034 | DRM_ERROR("Invalid object handle %d at index %d\n", |
4035 | exec_list[i].handle, i); | |
0ce907f8 | 4036 | /* prevent error path from reading uninitialized data */ |
05394f39 | 4037 | args->buffer_count = i; |
bf79cb91 | 4038 | ret = -ENOENT; |
673a394b EA |
4039 | goto err; |
4040 | } | |
05394f39 | 4041 | object_list[i] = obj; |
b70d11da | 4042 | |
05394f39 | 4043 | if (obj->in_execbuffer) { |
b70d11da | 4044 | DRM_ERROR("Object %p appears more than once in object list\n", |
05394f39 | 4045 | obj); |
0ce907f8 CW |
4046 | /* prevent error path from reading uninitialized data */ |
4047 | args->buffer_count = i + 1; | |
bf79cb91 | 4048 | ret = -EINVAL; |
b70d11da KH |
4049 | goto err; |
4050 | } | |
05394f39 | 4051 | obj->in_execbuffer = true; |
caea7476 | 4052 | obj->pending_fenced_gpu_access = false; |
ac94a962 | 4053 | } |
673a394b | 4054 | |
9af90d19 | 4055 | /* Move the objects en-masse into the GTT, evicting if necessary. */ |
bcf50e27 CW |
4056 | ret = i915_gem_execbuffer_reserve(dev, file, |
4057 | object_list, exec_list, | |
4058 | args->buffer_count); | |
9af90d19 CW |
4059 | if (ret) |
4060 | goto err; | |
ac94a962 | 4061 | |
9af90d19 | 4062 | /* The objects are in their final locations, apply the relocations. */ |
bcf50e27 CW |
4063 | ret = i915_gem_execbuffer_relocate(dev, file, |
4064 | object_list, exec_list, | |
4065 | args->buffer_count); | |
4066 | if (ret) { | |
4067 | if (ret == -EFAULT) { | |
4068 | ret = i915_gem_execbuffer_relocate_slow(dev, file, | |
4069 | object_list, | |
4070 | exec_list, | |
4071 | args->buffer_count); | |
4072 | BUG_ON(!mutex_is_locked(&dev->struct_mutex)); | |
4073 | } | |
9af90d19 | 4074 | if (ret) |
ac94a962 | 4075 | goto err; |
673a394b EA |
4076 | } |
4077 | ||
4078 | /* Set the pending read domains for the batch buffer to COMMAND */ | |
4079 | batch_obj = object_list[args->buffer_count-1]; | |
05394f39 | 4080 | if (batch_obj->base.pending_write_domain) { |
5f26a2c7 CW |
4081 | DRM_ERROR("Attempting to use self-modifying batch buffer\n"); |
4082 | ret = -EINVAL; | |
4083 | goto err; | |
4084 | } | |
05394f39 | 4085 | batch_obj->base.pending_read_domains |= I915_GEM_DOMAIN_COMMAND; |
673a394b | 4086 | |
9af90d19 | 4087 | /* Sanity check the batch buffer */ |
05394f39 | 4088 | exec_offset = batch_obj->gtt_offset; |
9af90d19 | 4089 | ret = i915_gem_check_execbuffer(args, exec_offset); |
83d60795 CW |
4090 | if (ret != 0) { |
4091 | DRM_ERROR("execbuf with invalid offset/length\n"); | |
4092 | goto err; | |
4093 | } | |
4094 | ||
13b29289 CW |
4095 | ret = i915_gem_execbuffer_move_to_gpu(dev, file, ring, |
4096 | object_list, args->buffer_count); | |
4097 | if (ret) | |
4098 | goto err; | |
673a394b | 4099 | |
673a394b EA |
4100 | #if WATCH_COHERENCY |
4101 | for (i = 0; i < args->buffer_count; i++) { | |
4102 | i915_gem_object_check_coherency(object_list[i], | |
4103 | exec_list[i].handle); | |
4104 | } | |
4105 | #endif | |
4106 | ||
673a394b | 4107 | #if WATCH_EXEC |
6911a9b8 | 4108 | i915_gem_dump_object(batch_obj, |
673a394b EA |
4109 | args->batch_len, |
4110 | __func__, | |
4111 | ~0); | |
4112 | #endif | |
4113 | ||
e59f2bac CW |
4114 | /* Check for any pending flips. As we only maintain a flip queue depth |
4115 | * of 1, we can simply insert a WAIT for the next display flip prior | |
4116 | * to executing the batch and avoid stalling the CPU. | |
4117 | */ | |
4118 | flips = 0; | |
4119 | for (i = 0; i < args->buffer_count; i++) { | |
05394f39 CW |
4120 | if (object_list[i]->base.write_domain) |
4121 | flips |= atomic_read(&object_list[i]->pending_flip); | |
e59f2bac CW |
4122 | } |
4123 | if (flips) { | |
4124 | int plane, flip_mask; | |
4125 | ||
4126 | for (plane = 0; flips >> plane; plane++) { | |
4127 | if (((flips >> plane) & 1) == 0) | |
4128 | continue; | |
4129 | ||
4130 | if (plane) | |
4131 | flip_mask = MI_WAIT_FOR_PLANE_B_FLIP; | |
4132 | else | |
4133 | flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; | |
4134 | ||
e1f99ce6 CW |
4135 | ret = intel_ring_begin(ring, 2); |
4136 | if (ret) | |
4137 | goto err; | |
4138 | ||
78501eac CW |
4139 | intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask); |
4140 | intel_ring_emit(ring, MI_NOOP); | |
4141 | intel_ring_advance(ring); | |
e59f2bac CW |
4142 | } |
4143 | } | |
4144 | ||
673a394b | 4145 | /* Exec the batchbuffer */ |
78501eac | 4146 | ret = ring->dispatch_execbuffer(ring, args, cliprects, exec_offset); |
673a394b EA |
4147 | if (ret) { |
4148 | DRM_ERROR("dispatch failed %d\n", ret); | |
4149 | goto err; | |
4150 | } | |
4151 | ||
673a394b | 4152 | for (i = 0; i < args->buffer_count; i++) { |
05394f39 | 4153 | struct drm_i915_gem_object *obj = object_list[i]; |
673a394b | 4154 | |
05394f39 CW |
4155 | obj->base.read_domains = obj->base.pending_read_domains; |
4156 | obj->base.write_domain = obj->base.pending_write_domain; | |
caea7476 | 4157 | obj->fenced_gpu_access = obj->pending_fenced_gpu_access; |
7e318e18 | 4158 | |
617dbe27 | 4159 | i915_gem_object_move_to_active(obj, ring); |
05394f39 CW |
4160 | if (obj->base.write_domain) { |
4161 | obj->dirty = 1; | |
4162 | list_move_tail(&obj->gpu_write_list, | |
64193406 | 4163 | &ring->gpu_write_list); |
7e318e18 CW |
4164 | intel_mark_busy(dev, obj); |
4165 | } | |
4166 | ||
4167 | trace_i915_gem_object_change_domain(obj, | |
05394f39 CW |
4168 | obj->base.read_domains, |
4169 | obj->base.write_domain); | |
673a394b | 4170 | } |
673a394b | 4171 | |
7e318e18 CW |
4172 | /* |
4173 | * Ensure that the commands in the batch buffer are | |
4174 | * finished before the interrupt fires | |
4175 | */ | |
4176 | i915_retire_commands(dev, ring); | |
4177 | ||
3cce469c | 4178 | if (i915_add_request(dev, file, request, ring)) |
5d97eb69 | 4179 | i915_gem_next_request_seqno(dev, ring); |
3cce469c CW |
4180 | else |
4181 | request = NULL; | |
673a394b | 4182 | |
673a394b | 4183 | err: |
b70d11da | 4184 | for (i = 0; i < args->buffer_count; i++) { |
05394f39 CW |
4185 | object_list[i]->in_execbuffer = false; |
4186 | drm_gem_object_unreference(&object_list[i]->base); | |
b70d11da | 4187 | } |
673a394b | 4188 | |
673a394b EA |
4189 | mutex_unlock(&dev->struct_mutex); |
4190 | ||
93533c29 | 4191 | pre_mutex_err: |
8e7d2b2c | 4192 | drm_free_large(object_list); |
9a298b2a | 4193 | kfree(cliprects); |
8dc5d147 | 4194 | kfree(request); |
673a394b EA |
4195 | |
4196 | return ret; | |
4197 | } | |
4198 | ||
76446cac JB |
4199 | /* |
4200 | * Legacy execbuffer just creates an exec2 list from the original exec object | |
4201 | * list array and passes it to the real function. | |
4202 | */ | |
4203 | int | |
4204 | i915_gem_execbuffer(struct drm_device *dev, void *data, | |
05394f39 | 4205 | struct drm_file *file) |
76446cac JB |
4206 | { |
4207 | struct drm_i915_gem_execbuffer *args = data; | |
4208 | struct drm_i915_gem_execbuffer2 exec2; | |
4209 | struct drm_i915_gem_exec_object *exec_list = NULL; | |
4210 | struct drm_i915_gem_exec_object2 *exec2_list = NULL; | |
4211 | int ret, i; | |
4212 | ||
4213 | #if WATCH_EXEC | |
4214 | DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n", | |
4215 | (int) args->buffers_ptr, args->buffer_count, args->batch_len); | |
4216 | #endif | |
4217 | ||
4218 | if (args->buffer_count < 1) { | |
4219 | DRM_ERROR("execbuf with %d buffers\n", args->buffer_count); | |
4220 | return -EINVAL; | |
4221 | } | |
4222 | ||
4223 | /* Copy in the exec list from userland */ | |
4224 | exec_list = drm_malloc_ab(sizeof(*exec_list), args->buffer_count); | |
4225 | exec2_list = drm_malloc_ab(sizeof(*exec2_list), args->buffer_count); | |
4226 | if (exec_list == NULL || exec2_list == NULL) { | |
4227 | DRM_ERROR("Failed to allocate exec list for %d buffers\n", | |
4228 | args->buffer_count); | |
4229 | drm_free_large(exec_list); | |
4230 | drm_free_large(exec2_list); | |
4231 | return -ENOMEM; | |
4232 | } | |
4233 | ret = copy_from_user(exec_list, | |
4234 | (struct drm_i915_relocation_entry __user *) | |
4235 | (uintptr_t) args->buffers_ptr, | |
4236 | sizeof(*exec_list) * args->buffer_count); | |
4237 | if (ret != 0) { | |
4238 | DRM_ERROR("copy %d exec entries failed %d\n", | |
4239 | args->buffer_count, ret); | |
4240 | drm_free_large(exec_list); | |
4241 | drm_free_large(exec2_list); | |
4242 | return -EFAULT; | |
4243 | } | |
4244 | ||
4245 | for (i = 0; i < args->buffer_count; i++) { | |
4246 | exec2_list[i].handle = exec_list[i].handle; | |
4247 | exec2_list[i].relocation_count = exec_list[i].relocation_count; | |
4248 | exec2_list[i].relocs_ptr = exec_list[i].relocs_ptr; | |
4249 | exec2_list[i].alignment = exec_list[i].alignment; | |
4250 | exec2_list[i].offset = exec_list[i].offset; | |
a6c45cf0 | 4251 | if (INTEL_INFO(dev)->gen < 4) |
76446cac JB |
4252 | exec2_list[i].flags = EXEC_OBJECT_NEEDS_FENCE; |
4253 | else | |
4254 | exec2_list[i].flags = 0; | |
4255 | } | |
4256 | ||
4257 | exec2.buffers_ptr = args->buffers_ptr; | |
4258 | exec2.buffer_count = args->buffer_count; | |
4259 | exec2.batch_start_offset = args->batch_start_offset; | |
4260 | exec2.batch_len = args->batch_len; | |
4261 | exec2.DR1 = args->DR1; | |
4262 | exec2.DR4 = args->DR4; | |
4263 | exec2.num_cliprects = args->num_cliprects; | |
4264 | exec2.cliprects_ptr = args->cliprects_ptr; | |
852835f3 | 4265 | exec2.flags = I915_EXEC_RENDER; |
76446cac | 4266 | |
05394f39 | 4267 | ret = i915_gem_do_execbuffer(dev, data, file, &exec2, exec2_list); |
76446cac JB |
4268 | if (!ret) { |
4269 | /* Copy the new buffer offsets back to the user's exec list. */ | |
4270 | for (i = 0; i < args->buffer_count; i++) | |
4271 | exec_list[i].offset = exec2_list[i].offset; | |
4272 | /* ... and back out to userspace */ | |
4273 | ret = copy_to_user((struct drm_i915_relocation_entry __user *) | |
4274 | (uintptr_t) args->buffers_ptr, | |
4275 | exec_list, | |
4276 | sizeof(*exec_list) * args->buffer_count); | |
4277 | if (ret) { | |
4278 | ret = -EFAULT; | |
4279 | DRM_ERROR("failed to copy %d exec entries " | |
4280 | "back to user (%d)\n", | |
4281 | args->buffer_count, ret); | |
4282 | } | |
76446cac JB |
4283 | } |
4284 | ||
4285 | drm_free_large(exec_list); | |
4286 | drm_free_large(exec2_list); | |
4287 | return ret; | |
4288 | } | |
4289 | ||
4290 | int | |
4291 | i915_gem_execbuffer2(struct drm_device *dev, void *data, | |
05394f39 | 4292 | struct drm_file *file) |
76446cac JB |
4293 | { |
4294 | struct drm_i915_gem_execbuffer2 *args = data; | |
4295 | struct drm_i915_gem_exec_object2 *exec2_list = NULL; | |
4296 | int ret; | |
4297 | ||
4298 | #if WATCH_EXEC | |
4299 | DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n", | |
4300 | (int) args->buffers_ptr, args->buffer_count, args->batch_len); | |
4301 | #endif | |
4302 | ||
4303 | if (args->buffer_count < 1) { | |
4304 | DRM_ERROR("execbuf2 with %d buffers\n", args->buffer_count); | |
4305 | return -EINVAL; | |
4306 | } | |
4307 | ||
4308 | exec2_list = drm_malloc_ab(sizeof(*exec2_list), args->buffer_count); | |
4309 | if (exec2_list == NULL) { | |
4310 | DRM_ERROR("Failed to allocate exec list for %d buffers\n", | |
4311 | args->buffer_count); | |
4312 | return -ENOMEM; | |
4313 | } | |
4314 | ret = copy_from_user(exec2_list, | |
4315 | (struct drm_i915_relocation_entry __user *) | |
4316 | (uintptr_t) args->buffers_ptr, | |
4317 | sizeof(*exec2_list) * args->buffer_count); | |
4318 | if (ret != 0) { | |
4319 | DRM_ERROR("copy %d exec entries failed %d\n", | |
4320 | args->buffer_count, ret); | |
4321 | drm_free_large(exec2_list); | |
4322 | return -EFAULT; | |
4323 | } | |
4324 | ||
05394f39 | 4325 | ret = i915_gem_do_execbuffer(dev, data, file, args, exec2_list); |
76446cac JB |
4326 | if (!ret) { |
4327 | /* Copy the new buffer offsets back to the user's exec list. */ | |
4328 | ret = copy_to_user((struct drm_i915_relocation_entry __user *) | |
4329 | (uintptr_t) args->buffers_ptr, | |
4330 | exec2_list, | |
4331 | sizeof(*exec2_list) * args->buffer_count); | |
4332 | if (ret) { | |
4333 | ret = -EFAULT; | |
4334 | DRM_ERROR("failed to copy %d exec entries " | |
4335 | "back to user (%d)\n", | |
4336 | args->buffer_count, ret); | |
4337 | } | |
4338 | } | |
4339 | ||
4340 | drm_free_large(exec2_list); | |
4341 | return ret; | |
4342 | } | |
4343 | ||
673a394b | 4344 | int |
05394f39 CW |
4345 | i915_gem_object_pin(struct drm_i915_gem_object *obj, |
4346 | uint32_t alignment, | |
75e9e915 | 4347 | bool map_and_fenceable) |
673a394b | 4348 | { |
05394f39 | 4349 | struct drm_device *dev = obj->base.dev; |
f13d3f73 | 4350 | struct drm_i915_private *dev_priv = dev->dev_private; |
673a394b EA |
4351 | int ret; |
4352 | ||
05394f39 | 4353 | BUG_ON(obj->pin_count == DRM_I915_GEM_OBJECT_MAX_PIN_COUNT); |
23bc5982 | 4354 | WARN_ON(i915_verify_lists(dev)); |
ac0c6b5a | 4355 | |
05394f39 CW |
4356 | if (obj->gtt_space != NULL) { |
4357 | if ((alignment && obj->gtt_offset & (alignment - 1)) || | |
4358 | (map_and_fenceable && !obj->map_and_fenceable)) { | |
4359 | WARN(obj->pin_count, | |
ae7d49d8 | 4360 | "bo is already pinned with incorrect alignment:" |
75e9e915 DV |
4361 | " offset=%x, req.alignment=%x, req.map_and_fenceable=%d," |
4362 | " obj->map_and_fenceable=%d\n", | |
05394f39 | 4363 | obj->gtt_offset, alignment, |
75e9e915 | 4364 | map_and_fenceable, |
05394f39 | 4365 | obj->map_and_fenceable); |
ac0c6b5a CW |
4366 | ret = i915_gem_object_unbind(obj); |
4367 | if (ret) | |
4368 | return ret; | |
4369 | } | |
4370 | } | |
4371 | ||
05394f39 | 4372 | if (obj->gtt_space == NULL) { |
a00b10c3 | 4373 | ret = i915_gem_object_bind_to_gtt(obj, alignment, |
75e9e915 | 4374 | map_and_fenceable); |
9731129c | 4375 | if (ret) |
673a394b | 4376 | return ret; |
22c344e9 | 4377 | } |
76446cac | 4378 | |
05394f39 CW |
4379 | if (obj->pin_count++ == 0) { |
4380 | i915_gem_info_add_pin(dev_priv, obj, map_and_fenceable); | |
4381 | if (!obj->active) | |
4382 | list_move_tail(&obj->mm_list, | |
f13d3f73 | 4383 | &dev_priv->mm.pinned_list); |
673a394b | 4384 | } |
05394f39 | 4385 | BUG_ON(!obj->pin_mappable && map_and_fenceable); |
673a394b | 4386 | |
23bc5982 | 4387 | WARN_ON(i915_verify_lists(dev)); |
673a394b EA |
4388 | return 0; |
4389 | } | |
4390 | ||
4391 | void | |
05394f39 | 4392 | i915_gem_object_unpin(struct drm_i915_gem_object *obj) |
673a394b | 4393 | { |
05394f39 | 4394 | struct drm_device *dev = obj->base.dev; |
673a394b | 4395 | drm_i915_private_t *dev_priv = dev->dev_private; |
673a394b | 4396 | |
23bc5982 | 4397 | WARN_ON(i915_verify_lists(dev)); |
05394f39 CW |
4398 | BUG_ON(obj->pin_count == 0); |
4399 | BUG_ON(obj->gtt_space == NULL); | |
673a394b | 4400 | |
05394f39 CW |
4401 | if (--obj->pin_count == 0) { |
4402 | if (!obj->active) | |
4403 | list_move_tail(&obj->mm_list, | |
673a394b | 4404 | &dev_priv->mm.inactive_list); |
05394f39 | 4405 | i915_gem_info_remove_pin(dev_priv, obj); |
673a394b | 4406 | } |
23bc5982 | 4407 | WARN_ON(i915_verify_lists(dev)); |
673a394b EA |
4408 | } |
4409 | ||
4410 | int | |
4411 | i915_gem_pin_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 4412 | struct drm_file *file) |
673a394b EA |
4413 | { |
4414 | struct drm_i915_gem_pin *args = data; | |
05394f39 | 4415 | struct drm_i915_gem_object *obj; |
673a394b EA |
4416 | int ret; |
4417 | ||
1d7cfea1 CW |
4418 | ret = i915_mutex_lock_interruptible(dev); |
4419 | if (ret) | |
4420 | return ret; | |
673a394b | 4421 | |
05394f39 | 4422 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
673a394b | 4423 | if (obj == NULL) { |
1d7cfea1 CW |
4424 | ret = -ENOENT; |
4425 | goto unlock; | |
673a394b | 4426 | } |
673a394b | 4427 | |
05394f39 | 4428 | if (obj->madv != I915_MADV_WILLNEED) { |
bb6baf76 | 4429 | DRM_ERROR("Attempting to pin a purgeable buffer\n"); |
1d7cfea1 CW |
4430 | ret = -EINVAL; |
4431 | goto out; | |
3ef94daa CW |
4432 | } |
4433 | ||
05394f39 | 4434 | if (obj->pin_filp != NULL && obj->pin_filp != file) { |
79e53945 JB |
4435 | DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n", |
4436 | args->handle); | |
1d7cfea1 CW |
4437 | ret = -EINVAL; |
4438 | goto out; | |
79e53945 JB |
4439 | } |
4440 | ||
05394f39 CW |
4441 | obj->user_pin_count++; |
4442 | obj->pin_filp = file; | |
4443 | if (obj->user_pin_count == 1) { | |
75e9e915 | 4444 | ret = i915_gem_object_pin(obj, args->alignment, true); |
1d7cfea1 CW |
4445 | if (ret) |
4446 | goto out; | |
673a394b EA |
4447 | } |
4448 | ||
4449 | /* XXX - flush the CPU caches for pinned objects | |
4450 | * as the X server doesn't manage domains yet | |
4451 | */ | |
e47c68e9 | 4452 | i915_gem_object_flush_cpu_write_domain(obj); |
05394f39 | 4453 | args->offset = obj->gtt_offset; |
1d7cfea1 | 4454 | out: |
05394f39 | 4455 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 4456 | unlock: |
673a394b | 4457 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 4458 | return ret; |
673a394b EA |
4459 | } |
4460 | ||
4461 | int | |
4462 | i915_gem_unpin_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 4463 | struct drm_file *file) |
673a394b EA |
4464 | { |
4465 | struct drm_i915_gem_pin *args = data; | |
05394f39 | 4466 | struct drm_i915_gem_object *obj; |
76c1dec1 | 4467 | int ret; |
673a394b | 4468 | |
1d7cfea1 CW |
4469 | ret = i915_mutex_lock_interruptible(dev); |
4470 | if (ret) | |
4471 | return ret; | |
673a394b | 4472 | |
05394f39 | 4473 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
673a394b | 4474 | if (obj == NULL) { |
1d7cfea1 CW |
4475 | ret = -ENOENT; |
4476 | goto unlock; | |
673a394b | 4477 | } |
76c1dec1 | 4478 | |
05394f39 | 4479 | if (obj->pin_filp != file) { |
79e53945 JB |
4480 | DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n", |
4481 | args->handle); | |
1d7cfea1 CW |
4482 | ret = -EINVAL; |
4483 | goto out; | |
79e53945 | 4484 | } |
05394f39 CW |
4485 | obj->user_pin_count--; |
4486 | if (obj->user_pin_count == 0) { | |
4487 | obj->pin_filp = NULL; | |
79e53945 JB |
4488 | i915_gem_object_unpin(obj); |
4489 | } | |
673a394b | 4490 | |
1d7cfea1 | 4491 | out: |
05394f39 | 4492 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 4493 | unlock: |
673a394b | 4494 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 4495 | return ret; |
673a394b EA |
4496 | } |
4497 | ||
4498 | int | |
4499 | i915_gem_busy_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 4500 | struct drm_file *file) |
673a394b EA |
4501 | { |
4502 | struct drm_i915_gem_busy *args = data; | |
05394f39 | 4503 | struct drm_i915_gem_object *obj; |
30dbf0c0 CW |
4504 | int ret; |
4505 | ||
76c1dec1 | 4506 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 4507 | if (ret) |
76c1dec1 | 4508 | return ret; |
673a394b | 4509 | |
05394f39 | 4510 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
673a394b | 4511 | if (obj == NULL) { |
1d7cfea1 CW |
4512 | ret = -ENOENT; |
4513 | goto unlock; | |
673a394b | 4514 | } |
d1b851fc | 4515 | |
0be555b6 CW |
4516 | /* Count all active objects as busy, even if they are currently not used |
4517 | * by the gpu. Users of this interface expect objects to eventually | |
4518 | * become non-busy without any further actions, therefore emit any | |
4519 | * necessary flushes here. | |
c4de0a5d | 4520 | */ |
05394f39 | 4521 | args->busy = obj->active; |
0be555b6 CW |
4522 | if (args->busy) { |
4523 | /* Unconditionally flush objects, even when the gpu still uses this | |
4524 | * object. Userspace calling this function indicates that it wants to | |
4525 | * use this buffer rather sooner than later, so issuing the required | |
4526 | * flush earlier is beneficial. | |
4527 | */ | |
05394f39 CW |
4528 | if (obj->base.write_domain & I915_GEM_GPU_DOMAINS) |
4529 | i915_gem_flush_ring(dev, obj->ring, | |
4530 | 0, obj->base.write_domain); | |
0be555b6 CW |
4531 | |
4532 | /* Update the active list for the hardware's current position. | |
4533 | * Otherwise this only updates on a delayed timer or when irqs | |
4534 | * are actually unmasked, and our working set ends up being | |
4535 | * larger than required. | |
4536 | */ | |
05394f39 | 4537 | i915_gem_retire_requests_ring(dev, obj->ring); |
0be555b6 | 4538 | |
05394f39 | 4539 | args->busy = obj->active; |
0be555b6 | 4540 | } |
673a394b | 4541 | |
05394f39 | 4542 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 4543 | unlock: |
673a394b | 4544 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 4545 | return ret; |
673a394b EA |
4546 | } |
4547 | ||
4548 | int | |
4549 | i915_gem_throttle_ioctl(struct drm_device *dev, void *data, | |
4550 | struct drm_file *file_priv) | |
4551 | { | |
4552 | return i915_gem_ring_throttle(dev, file_priv); | |
4553 | } | |
4554 | ||
3ef94daa CW |
4555 | int |
4556 | i915_gem_madvise_ioctl(struct drm_device *dev, void *data, | |
4557 | struct drm_file *file_priv) | |
4558 | { | |
4559 | struct drm_i915_gem_madvise *args = data; | |
05394f39 | 4560 | struct drm_i915_gem_object *obj; |
76c1dec1 | 4561 | int ret; |
3ef94daa CW |
4562 | |
4563 | switch (args->madv) { | |
4564 | case I915_MADV_DONTNEED: | |
4565 | case I915_MADV_WILLNEED: | |
4566 | break; | |
4567 | default: | |
4568 | return -EINVAL; | |
4569 | } | |
4570 | ||
1d7cfea1 CW |
4571 | ret = i915_mutex_lock_interruptible(dev); |
4572 | if (ret) | |
4573 | return ret; | |
4574 | ||
05394f39 | 4575 | obj = to_intel_bo(drm_gem_object_lookup(dev, file_priv, args->handle)); |
3ef94daa | 4576 | if (obj == NULL) { |
1d7cfea1 CW |
4577 | ret = -ENOENT; |
4578 | goto unlock; | |
3ef94daa | 4579 | } |
3ef94daa | 4580 | |
05394f39 | 4581 | if (obj->pin_count) { |
1d7cfea1 CW |
4582 | ret = -EINVAL; |
4583 | goto out; | |
3ef94daa CW |
4584 | } |
4585 | ||
05394f39 CW |
4586 | if (obj->madv != __I915_MADV_PURGED) |
4587 | obj->madv = args->madv; | |
3ef94daa | 4588 | |
2d7ef395 | 4589 | /* if the object is no longer bound, discard its backing storage */ |
05394f39 CW |
4590 | if (i915_gem_object_is_purgeable(obj) && |
4591 | obj->gtt_space == NULL) | |
2d7ef395 CW |
4592 | i915_gem_object_truncate(obj); |
4593 | ||
05394f39 | 4594 | args->retained = obj->madv != __I915_MADV_PURGED; |
bb6baf76 | 4595 | |
1d7cfea1 | 4596 | out: |
05394f39 | 4597 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 4598 | unlock: |
3ef94daa | 4599 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 4600 | return ret; |
3ef94daa CW |
4601 | } |
4602 | ||
05394f39 CW |
4603 | struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev, |
4604 | size_t size) | |
ac52bc56 | 4605 | { |
73aa808f | 4606 | struct drm_i915_private *dev_priv = dev->dev_private; |
c397b908 | 4607 | struct drm_i915_gem_object *obj; |
ac52bc56 | 4608 | |
c397b908 DV |
4609 | obj = kzalloc(sizeof(*obj), GFP_KERNEL); |
4610 | if (obj == NULL) | |
4611 | return NULL; | |
673a394b | 4612 | |
c397b908 DV |
4613 | if (drm_gem_object_init(dev, &obj->base, size) != 0) { |
4614 | kfree(obj); | |
4615 | return NULL; | |
4616 | } | |
673a394b | 4617 | |
73aa808f CW |
4618 | i915_gem_info_add_obj(dev_priv, size); |
4619 | ||
c397b908 DV |
4620 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; |
4621 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; | |
673a394b | 4622 | |
c397b908 | 4623 | obj->agp_type = AGP_USER_MEMORY; |
62b8b215 | 4624 | obj->base.driver_private = NULL; |
c397b908 | 4625 | obj->fence_reg = I915_FENCE_REG_NONE; |
69dc4987 | 4626 | INIT_LIST_HEAD(&obj->mm_list); |
93a37f20 | 4627 | INIT_LIST_HEAD(&obj->gtt_list); |
69dc4987 | 4628 | INIT_LIST_HEAD(&obj->ring_list); |
c397b908 | 4629 | INIT_LIST_HEAD(&obj->gpu_write_list); |
c397b908 | 4630 | obj->madv = I915_MADV_WILLNEED; |
75e9e915 DV |
4631 | /* Avoid an unnecessary call to unbind on the first bind. */ |
4632 | obj->map_and_fenceable = true; | |
de151cf6 | 4633 | |
05394f39 | 4634 | return obj; |
c397b908 DV |
4635 | } |
4636 | ||
4637 | int i915_gem_init_object(struct drm_gem_object *obj) | |
4638 | { | |
4639 | BUG(); | |
de151cf6 | 4640 | |
673a394b EA |
4641 | return 0; |
4642 | } | |
4643 | ||
05394f39 | 4644 | static void i915_gem_free_object_tail(struct drm_i915_gem_object *obj) |
673a394b | 4645 | { |
05394f39 | 4646 | struct drm_device *dev = obj->base.dev; |
be72615b | 4647 | drm_i915_private_t *dev_priv = dev->dev_private; |
be72615b | 4648 | int ret; |
673a394b | 4649 | |
be72615b CW |
4650 | ret = i915_gem_object_unbind(obj); |
4651 | if (ret == -ERESTARTSYS) { | |
05394f39 | 4652 | list_move(&obj->mm_list, |
be72615b CW |
4653 | &dev_priv->mm.deferred_free_list); |
4654 | return; | |
4655 | } | |
673a394b | 4656 | |
05394f39 | 4657 | if (obj->base.map_list.map) |
7e616158 | 4658 | i915_gem_free_mmap_offset(obj); |
de151cf6 | 4659 | |
05394f39 CW |
4660 | drm_gem_object_release(&obj->base); |
4661 | i915_gem_info_remove_obj(dev_priv, obj->base.size); | |
c397b908 | 4662 | |
05394f39 CW |
4663 | kfree(obj->page_cpu_valid); |
4664 | kfree(obj->bit_17); | |
4665 | kfree(obj); | |
673a394b EA |
4666 | } |
4667 | ||
05394f39 | 4668 | void i915_gem_free_object(struct drm_gem_object *gem_obj) |
be72615b | 4669 | { |
05394f39 CW |
4670 | struct drm_i915_gem_object *obj = to_intel_bo(gem_obj); |
4671 | struct drm_device *dev = obj->base.dev; | |
be72615b CW |
4672 | |
4673 | trace_i915_gem_object_destroy(obj); | |
4674 | ||
05394f39 | 4675 | while (obj->pin_count > 0) |
be72615b CW |
4676 | i915_gem_object_unpin(obj); |
4677 | ||
05394f39 | 4678 | if (obj->phys_obj) |
be72615b CW |
4679 | i915_gem_detach_phys_object(dev, obj); |
4680 | ||
4681 | i915_gem_free_object_tail(obj); | |
4682 | } | |
4683 | ||
29105ccc CW |
4684 | int |
4685 | i915_gem_idle(struct drm_device *dev) | |
4686 | { | |
4687 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4688 | int ret; | |
28dfe52a | 4689 | |
29105ccc | 4690 | mutex_lock(&dev->struct_mutex); |
1c5d22f7 | 4691 | |
87acb0a5 | 4692 | if (dev_priv->mm.suspended) { |
29105ccc CW |
4693 | mutex_unlock(&dev->struct_mutex); |
4694 | return 0; | |
28dfe52a EA |
4695 | } |
4696 | ||
29105ccc | 4697 | ret = i915_gpu_idle(dev); |
6dbe2772 KP |
4698 | if (ret) { |
4699 | mutex_unlock(&dev->struct_mutex); | |
673a394b | 4700 | return ret; |
6dbe2772 | 4701 | } |
673a394b | 4702 | |
29105ccc CW |
4703 | /* Under UMS, be paranoid and evict. */ |
4704 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) { | |
5eac3ab4 | 4705 | ret = i915_gem_evict_inactive(dev, false); |
29105ccc CW |
4706 | if (ret) { |
4707 | mutex_unlock(&dev->struct_mutex); | |
4708 | return ret; | |
4709 | } | |
4710 | } | |
4711 | ||
312817a3 CW |
4712 | i915_gem_reset_fences(dev); |
4713 | ||
29105ccc CW |
4714 | /* Hack! Don't let anybody do execbuf while we don't control the chip. |
4715 | * We need to replace this with a semaphore, or something. | |
4716 | * And not confound mm.suspended! | |
4717 | */ | |
4718 | dev_priv->mm.suspended = 1; | |
bc0c7f14 | 4719 | del_timer_sync(&dev_priv->hangcheck_timer); |
29105ccc CW |
4720 | |
4721 | i915_kernel_lost_context(dev); | |
6dbe2772 | 4722 | i915_gem_cleanup_ringbuffer(dev); |
29105ccc | 4723 | |
6dbe2772 KP |
4724 | mutex_unlock(&dev->struct_mutex); |
4725 | ||
29105ccc CW |
4726 | /* Cancel the retire work handler, which should be idle now. */ |
4727 | cancel_delayed_work_sync(&dev_priv->mm.retire_work); | |
4728 | ||
673a394b EA |
4729 | return 0; |
4730 | } | |
4731 | ||
8187a2b7 ZN |
4732 | int |
4733 | i915_gem_init_ringbuffer(struct drm_device *dev) | |
4734 | { | |
4735 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4736 | int ret; | |
68f95ba9 | 4737 | |
5c1143bb | 4738 | ret = intel_init_render_ring_buffer(dev); |
68f95ba9 | 4739 | if (ret) |
b6913e4b | 4740 | return ret; |
68f95ba9 CW |
4741 | |
4742 | if (HAS_BSD(dev)) { | |
5c1143bb | 4743 | ret = intel_init_bsd_ring_buffer(dev); |
68f95ba9 CW |
4744 | if (ret) |
4745 | goto cleanup_render_ring; | |
d1b851fc | 4746 | } |
68f95ba9 | 4747 | |
549f7365 CW |
4748 | if (HAS_BLT(dev)) { |
4749 | ret = intel_init_blt_ring_buffer(dev); | |
4750 | if (ret) | |
4751 | goto cleanup_bsd_ring; | |
4752 | } | |
4753 | ||
6f392d54 CW |
4754 | dev_priv->next_seqno = 1; |
4755 | ||
68f95ba9 CW |
4756 | return 0; |
4757 | ||
549f7365 | 4758 | cleanup_bsd_ring: |
78501eac | 4759 | intel_cleanup_ring_buffer(&dev_priv->bsd_ring); |
68f95ba9 | 4760 | cleanup_render_ring: |
78501eac | 4761 | intel_cleanup_ring_buffer(&dev_priv->render_ring); |
8187a2b7 ZN |
4762 | return ret; |
4763 | } | |
4764 | ||
4765 | void | |
4766 | i915_gem_cleanup_ringbuffer(struct drm_device *dev) | |
4767 | { | |
4768 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4769 | ||
78501eac CW |
4770 | intel_cleanup_ring_buffer(&dev_priv->render_ring); |
4771 | intel_cleanup_ring_buffer(&dev_priv->bsd_ring); | |
4772 | intel_cleanup_ring_buffer(&dev_priv->blt_ring); | |
8187a2b7 ZN |
4773 | } |
4774 | ||
673a394b EA |
4775 | int |
4776 | i915_gem_entervt_ioctl(struct drm_device *dev, void *data, | |
4777 | struct drm_file *file_priv) | |
4778 | { | |
4779 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4780 | int ret; | |
4781 | ||
79e53945 JB |
4782 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
4783 | return 0; | |
4784 | ||
ba1234d1 | 4785 | if (atomic_read(&dev_priv->mm.wedged)) { |
673a394b | 4786 | DRM_ERROR("Reenabling wedged hardware, good luck\n"); |
ba1234d1 | 4787 | atomic_set(&dev_priv->mm.wedged, 0); |
673a394b EA |
4788 | } |
4789 | ||
673a394b | 4790 | mutex_lock(&dev->struct_mutex); |
9bb2d6f9 EA |
4791 | dev_priv->mm.suspended = 0; |
4792 | ||
4793 | ret = i915_gem_init_ringbuffer(dev); | |
d816f6ac WF |
4794 | if (ret != 0) { |
4795 | mutex_unlock(&dev->struct_mutex); | |
9bb2d6f9 | 4796 | return ret; |
d816f6ac | 4797 | } |
9bb2d6f9 | 4798 | |
69dc4987 | 4799 | BUG_ON(!list_empty(&dev_priv->mm.active_list)); |
852835f3 | 4800 | BUG_ON(!list_empty(&dev_priv->render_ring.active_list)); |
87acb0a5 | 4801 | BUG_ON(!list_empty(&dev_priv->bsd_ring.active_list)); |
549f7365 | 4802 | BUG_ON(!list_empty(&dev_priv->blt_ring.active_list)); |
673a394b EA |
4803 | BUG_ON(!list_empty(&dev_priv->mm.flushing_list)); |
4804 | BUG_ON(!list_empty(&dev_priv->mm.inactive_list)); | |
852835f3 | 4805 | BUG_ON(!list_empty(&dev_priv->render_ring.request_list)); |
87acb0a5 | 4806 | BUG_ON(!list_empty(&dev_priv->bsd_ring.request_list)); |
549f7365 | 4807 | BUG_ON(!list_empty(&dev_priv->blt_ring.request_list)); |
673a394b | 4808 | mutex_unlock(&dev->struct_mutex); |
dbb19d30 | 4809 | |
5f35308b CW |
4810 | ret = drm_irq_install(dev); |
4811 | if (ret) | |
4812 | goto cleanup_ringbuffer; | |
dbb19d30 | 4813 | |
673a394b | 4814 | return 0; |
5f35308b CW |
4815 | |
4816 | cleanup_ringbuffer: | |
4817 | mutex_lock(&dev->struct_mutex); | |
4818 | i915_gem_cleanup_ringbuffer(dev); | |
4819 | dev_priv->mm.suspended = 1; | |
4820 | mutex_unlock(&dev->struct_mutex); | |
4821 | ||
4822 | return ret; | |
673a394b EA |
4823 | } |
4824 | ||
4825 | int | |
4826 | i915_gem_leavevt_ioctl(struct drm_device *dev, void *data, | |
4827 | struct drm_file *file_priv) | |
4828 | { | |
79e53945 JB |
4829 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
4830 | return 0; | |
4831 | ||
dbb19d30 | 4832 | drm_irq_uninstall(dev); |
e6890f6f | 4833 | return i915_gem_idle(dev); |
673a394b EA |
4834 | } |
4835 | ||
4836 | void | |
4837 | i915_gem_lastclose(struct drm_device *dev) | |
4838 | { | |
4839 | int ret; | |
673a394b | 4840 | |
e806b495 EA |
4841 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
4842 | return; | |
4843 | ||
6dbe2772 KP |
4844 | ret = i915_gem_idle(dev); |
4845 | if (ret) | |
4846 | DRM_ERROR("failed to idle hardware: %d\n", ret); | |
673a394b EA |
4847 | } |
4848 | ||
64193406 CW |
4849 | static void |
4850 | init_ring_lists(struct intel_ring_buffer *ring) | |
4851 | { | |
4852 | INIT_LIST_HEAD(&ring->active_list); | |
4853 | INIT_LIST_HEAD(&ring->request_list); | |
4854 | INIT_LIST_HEAD(&ring->gpu_write_list); | |
4855 | } | |
4856 | ||
673a394b EA |
4857 | void |
4858 | i915_gem_load(struct drm_device *dev) | |
4859 | { | |
b5aa8a0f | 4860 | int i; |
673a394b EA |
4861 | drm_i915_private_t *dev_priv = dev->dev_private; |
4862 | ||
69dc4987 | 4863 | INIT_LIST_HEAD(&dev_priv->mm.active_list); |
673a394b EA |
4864 | INIT_LIST_HEAD(&dev_priv->mm.flushing_list); |
4865 | INIT_LIST_HEAD(&dev_priv->mm.inactive_list); | |
f13d3f73 | 4866 | INIT_LIST_HEAD(&dev_priv->mm.pinned_list); |
a09ba7fa | 4867 | INIT_LIST_HEAD(&dev_priv->mm.fence_list); |
be72615b | 4868 | INIT_LIST_HEAD(&dev_priv->mm.deferred_free_list); |
93a37f20 | 4869 | INIT_LIST_HEAD(&dev_priv->mm.gtt_list); |
64193406 CW |
4870 | init_ring_lists(&dev_priv->render_ring); |
4871 | init_ring_lists(&dev_priv->bsd_ring); | |
4872 | init_ring_lists(&dev_priv->blt_ring); | |
007cc8ac DV |
4873 | for (i = 0; i < 16; i++) |
4874 | INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list); | |
673a394b EA |
4875 | INIT_DELAYED_WORK(&dev_priv->mm.retire_work, |
4876 | i915_gem_retire_work_handler); | |
30dbf0c0 | 4877 | init_completion(&dev_priv->error_completion); |
31169714 | 4878 | |
94400120 DA |
4879 | /* On GEN3 we really need to make sure the ARB C3 LP bit is set */ |
4880 | if (IS_GEN3(dev)) { | |
4881 | u32 tmp = I915_READ(MI_ARB_STATE); | |
4882 | if (!(tmp & MI_ARB_C3_LP_WRITE_ENABLE)) { | |
4883 | /* arb state is a masked write, so set bit + bit in mask */ | |
4884 | tmp = MI_ARB_C3_LP_WRITE_ENABLE | (MI_ARB_C3_LP_WRITE_ENABLE << MI_ARB_MASK_SHIFT); | |
4885 | I915_WRITE(MI_ARB_STATE, tmp); | |
4886 | } | |
4887 | } | |
4888 | ||
de151cf6 | 4889 | /* Old X drivers will take 0-2 for front, back, depth buffers */ |
b397c836 EA |
4890 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) |
4891 | dev_priv->fence_reg_start = 3; | |
de151cf6 | 4892 | |
a6c45cf0 | 4893 | if (INTEL_INFO(dev)->gen >= 4 || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) |
de151cf6 JB |
4894 | dev_priv->num_fence_regs = 16; |
4895 | else | |
4896 | dev_priv->num_fence_regs = 8; | |
4897 | ||
b5aa8a0f | 4898 | /* Initialize fence registers to zero */ |
a6c45cf0 CW |
4899 | switch (INTEL_INFO(dev)->gen) { |
4900 | case 6: | |
4901 | for (i = 0; i < 16; i++) | |
4902 | I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + (i * 8), 0); | |
4903 | break; | |
4904 | case 5: | |
4905 | case 4: | |
b5aa8a0f GH |
4906 | for (i = 0; i < 16; i++) |
4907 | I915_WRITE64(FENCE_REG_965_0 + (i * 8), 0); | |
a6c45cf0 CW |
4908 | break; |
4909 | case 3: | |
b5aa8a0f GH |
4910 | if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) |
4911 | for (i = 0; i < 8; i++) | |
4912 | I915_WRITE(FENCE_REG_945_8 + (i * 4), 0); | |
a6c45cf0 CW |
4913 | case 2: |
4914 | for (i = 0; i < 8; i++) | |
4915 | I915_WRITE(FENCE_REG_830_0 + (i * 4), 0); | |
4916 | break; | |
b5aa8a0f | 4917 | } |
673a394b | 4918 | i915_gem_detect_bit_6_swizzle(dev); |
6b95a207 | 4919 | init_waitqueue_head(&dev_priv->pending_flip_queue); |
17250b71 CW |
4920 | |
4921 | dev_priv->mm.inactive_shrinker.shrink = i915_gem_inactive_shrink; | |
4922 | dev_priv->mm.inactive_shrinker.seeks = DEFAULT_SEEKS; | |
4923 | register_shrinker(&dev_priv->mm.inactive_shrinker); | |
673a394b | 4924 | } |
71acb5eb DA |
4925 | |
4926 | /* | |
4927 | * Create a physically contiguous memory object for this object | |
4928 | * e.g. for cursor + overlay regs | |
4929 | */ | |
995b6762 CW |
4930 | static int i915_gem_init_phys_object(struct drm_device *dev, |
4931 | int id, int size, int align) | |
71acb5eb DA |
4932 | { |
4933 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4934 | struct drm_i915_gem_phys_object *phys_obj; | |
4935 | int ret; | |
4936 | ||
4937 | if (dev_priv->mm.phys_objs[id - 1] || !size) | |
4938 | return 0; | |
4939 | ||
9a298b2a | 4940 | phys_obj = kzalloc(sizeof(struct drm_i915_gem_phys_object), GFP_KERNEL); |
71acb5eb DA |
4941 | if (!phys_obj) |
4942 | return -ENOMEM; | |
4943 | ||
4944 | phys_obj->id = id; | |
4945 | ||
6eeefaf3 | 4946 | phys_obj->handle = drm_pci_alloc(dev, size, align); |
71acb5eb DA |
4947 | if (!phys_obj->handle) { |
4948 | ret = -ENOMEM; | |
4949 | goto kfree_obj; | |
4950 | } | |
4951 | #ifdef CONFIG_X86 | |
4952 | set_memory_wc((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE); | |
4953 | #endif | |
4954 | ||
4955 | dev_priv->mm.phys_objs[id - 1] = phys_obj; | |
4956 | ||
4957 | return 0; | |
4958 | kfree_obj: | |
9a298b2a | 4959 | kfree(phys_obj); |
71acb5eb DA |
4960 | return ret; |
4961 | } | |
4962 | ||
995b6762 | 4963 | static void i915_gem_free_phys_object(struct drm_device *dev, int id) |
71acb5eb DA |
4964 | { |
4965 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4966 | struct drm_i915_gem_phys_object *phys_obj; | |
4967 | ||
4968 | if (!dev_priv->mm.phys_objs[id - 1]) | |
4969 | return; | |
4970 | ||
4971 | phys_obj = dev_priv->mm.phys_objs[id - 1]; | |
4972 | if (phys_obj->cur_obj) { | |
4973 | i915_gem_detach_phys_object(dev, phys_obj->cur_obj); | |
4974 | } | |
4975 | ||
4976 | #ifdef CONFIG_X86 | |
4977 | set_memory_wb((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE); | |
4978 | #endif | |
4979 | drm_pci_free(dev, phys_obj->handle); | |
4980 | kfree(phys_obj); | |
4981 | dev_priv->mm.phys_objs[id - 1] = NULL; | |
4982 | } | |
4983 | ||
4984 | void i915_gem_free_all_phys_object(struct drm_device *dev) | |
4985 | { | |
4986 | int i; | |
4987 | ||
260883c8 | 4988 | for (i = I915_GEM_PHYS_CURSOR_0; i <= I915_MAX_PHYS_OBJECT; i++) |
71acb5eb DA |
4989 | i915_gem_free_phys_object(dev, i); |
4990 | } | |
4991 | ||
4992 | void i915_gem_detach_phys_object(struct drm_device *dev, | |
05394f39 | 4993 | struct drm_i915_gem_object *obj) |
71acb5eb | 4994 | { |
05394f39 | 4995 | struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping; |
e5281ccd | 4996 | char *vaddr; |
71acb5eb | 4997 | int i; |
71acb5eb DA |
4998 | int page_count; |
4999 | ||
05394f39 | 5000 | if (!obj->phys_obj) |
71acb5eb | 5001 | return; |
05394f39 | 5002 | vaddr = obj->phys_obj->handle->vaddr; |
71acb5eb | 5003 | |
05394f39 | 5004 | page_count = obj->base.size / PAGE_SIZE; |
71acb5eb | 5005 | for (i = 0; i < page_count; i++) { |
e5281ccd CW |
5006 | struct page *page = read_cache_page_gfp(mapping, i, |
5007 | GFP_HIGHUSER | __GFP_RECLAIMABLE); | |
5008 | if (!IS_ERR(page)) { | |
5009 | char *dst = kmap_atomic(page); | |
5010 | memcpy(dst, vaddr + i*PAGE_SIZE, PAGE_SIZE); | |
5011 | kunmap_atomic(dst); | |
5012 | ||
5013 | drm_clflush_pages(&page, 1); | |
5014 | ||
5015 | set_page_dirty(page); | |
5016 | mark_page_accessed(page); | |
5017 | page_cache_release(page); | |
5018 | } | |
71acb5eb | 5019 | } |
40ce6575 | 5020 | intel_gtt_chipset_flush(); |
d78b47b9 | 5021 | |
05394f39 CW |
5022 | obj->phys_obj->cur_obj = NULL; |
5023 | obj->phys_obj = NULL; | |
71acb5eb DA |
5024 | } |
5025 | ||
5026 | int | |
5027 | i915_gem_attach_phys_object(struct drm_device *dev, | |
05394f39 | 5028 | struct drm_i915_gem_object *obj, |
6eeefaf3 CW |
5029 | int id, |
5030 | int align) | |
71acb5eb | 5031 | { |
05394f39 | 5032 | struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping; |
71acb5eb | 5033 | drm_i915_private_t *dev_priv = dev->dev_private; |
71acb5eb DA |
5034 | int ret = 0; |
5035 | int page_count; | |
5036 | int i; | |
5037 | ||
5038 | if (id > I915_MAX_PHYS_OBJECT) | |
5039 | return -EINVAL; | |
5040 | ||
05394f39 CW |
5041 | if (obj->phys_obj) { |
5042 | if (obj->phys_obj->id == id) | |
71acb5eb DA |
5043 | return 0; |
5044 | i915_gem_detach_phys_object(dev, obj); | |
5045 | } | |
5046 | ||
71acb5eb DA |
5047 | /* create a new object */ |
5048 | if (!dev_priv->mm.phys_objs[id - 1]) { | |
5049 | ret = i915_gem_init_phys_object(dev, id, | |
05394f39 | 5050 | obj->base.size, align); |
71acb5eb | 5051 | if (ret) { |
05394f39 CW |
5052 | DRM_ERROR("failed to init phys object %d size: %zu\n", |
5053 | id, obj->base.size); | |
e5281ccd | 5054 | return ret; |
71acb5eb DA |
5055 | } |
5056 | } | |
5057 | ||
5058 | /* bind to the object */ | |
05394f39 CW |
5059 | obj->phys_obj = dev_priv->mm.phys_objs[id - 1]; |
5060 | obj->phys_obj->cur_obj = obj; | |
71acb5eb | 5061 | |
05394f39 | 5062 | page_count = obj->base.size / PAGE_SIZE; |
71acb5eb DA |
5063 | |
5064 | for (i = 0; i < page_count; i++) { | |
e5281ccd CW |
5065 | struct page *page; |
5066 | char *dst, *src; | |
5067 | ||
5068 | page = read_cache_page_gfp(mapping, i, | |
5069 | GFP_HIGHUSER | __GFP_RECLAIMABLE); | |
5070 | if (IS_ERR(page)) | |
5071 | return PTR_ERR(page); | |
71acb5eb | 5072 | |
ff75b9bc | 5073 | src = kmap_atomic(page); |
05394f39 | 5074 | dst = obj->phys_obj->handle->vaddr + (i * PAGE_SIZE); |
71acb5eb | 5075 | memcpy(dst, src, PAGE_SIZE); |
3e4d3af5 | 5076 | kunmap_atomic(src); |
71acb5eb | 5077 | |
e5281ccd CW |
5078 | mark_page_accessed(page); |
5079 | page_cache_release(page); | |
5080 | } | |
d78b47b9 | 5081 | |
71acb5eb | 5082 | return 0; |
71acb5eb DA |
5083 | } |
5084 | ||
5085 | static int | |
05394f39 CW |
5086 | i915_gem_phys_pwrite(struct drm_device *dev, |
5087 | struct drm_i915_gem_object *obj, | |
71acb5eb DA |
5088 | struct drm_i915_gem_pwrite *args, |
5089 | struct drm_file *file_priv) | |
5090 | { | |
05394f39 | 5091 | void *vaddr = obj->phys_obj->handle->vaddr + args->offset; |
b47b30cc | 5092 | char __user *user_data = (char __user *) (uintptr_t) args->data_ptr; |
71acb5eb | 5093 | |
b47b30cc CW |
5094 | if (__copy_from_user_inatomic_nocache(vaddr, user_data, args->size)) { |
5095 | unsigned long unwritten; | |
5096 | ||
5097 | /* The physical object once assigned is fixed for the lifetime | |
5098 | * of the obj, so we can safely drop the lock and continue | |
5099 | * to access vaddr. | |
5100 | */ | |
5101 | mutex_unlock(&dev->struct_mutex); | |
5102 | unwritten = copy_from_user(vaddr, user_data, args->size); | |
5103 | mutex_lock(&dev->struct_mutex); | |
5104 | if (unwritten) | |
5105 | return -EFAULT; | |
5106 | } | |
71acb5eb | 5107 | |
40ce6575 | 5108 | intel_gtt_chipset_flush(); |
71acb5eb DA |
5109 | return 0; |
5110 | } | |
b962442e | 5111 | |
f787a5f5 | 5112 | void i915_gem_release(struct drm_device *dev, struct drm_file *file) |
b962442e | 5113 | { |
f787a5f5 | 5114 | struct drm_i915_file_private *file_priv = file->driver_priv; |
b962442e EA |
5115 | |
5116 | /* Clean up our request list when the client is going away, so that | |
5117 | * later retire_requests won't dereference our soon-to-be-gone | |
5118 | * file_priv. | |
5119 | */ | |
1c25595f | 5120 | spin_lock(&file_priv->mm.lock); |
f787a5f5 CW |
5121 | while (!list_empty(&file_priv->mm.request_list)) { |
5122 | struct drm_i915_gem_request *request; | |
5123 | ||
5124 | request = list_first_entry(&file_priv->mm.request_list, | |
5125 | struct drm_i915_gem_request, | |
5126 | client_list); | |
5127 | list_del(&request->client_list); | |
5128 | request->file_priv = NULL; | |
5129 | } | |
1c25595f | 5130 | spin_unlock(&file_priv->mm.lock); |
b962442e | 5131 | } |
31169714 | 5132 | |
1637ef41 CW |
5133 | static int |
5134 | i915_gpu_is_active(struct drm_device *dev) | |
5135 | { | |
5136 | drm_i915_private_t *dev_priv = dev->dev_private; | |
5137 | int lists_empty; | |
5138 | ||
1637ef41 | 5139 | lists_empty = list_empty(&dev_priv->mm.flushing_list) && |
17250b71 | 5140 | list_empty(&dev_priv->mm.active_list); |
1637ef41 CW |
5141 | |
5142 | return !lists_empty; | |
5143 | } | |
5144 | ||
31169714 | 5145 | static int |
17250b71 CW |
5146 | i915_gem_inactive_shrink(struct shrinker *shrinker, |
5147 | int nr_to_scan, | |
5148 | gfp_t gfp_mask) | |
31169714 | 5149 | { |
17250b71 CW |
5150 | struct drm_i915_private *dev_priv = |
5151 | container_of(shrinker, | |
5152 | struct drm_i915_private, | |
5153 | mm.inactive_shrinker); | |
5154 | struct drm_device *dev = dev_priv->dev; | |
5155 | struct drm_i915_gem_object *obj, *next; | |
5156 | int cnt; | |
5157 | ||
5158 | if (!mutex_trylock(&dev->struct_mutex)) | |
bbe2e11a | 5159 | return 0; |
31169714 CW |
5160 | |
5161 | /* "fast-path" to count number of available objects */ | |
5162 | if (nr_to_scan == 0) { | |
17250b71 CW |
5163 | cnt = 0; |
5164 | list_for_each_entry(obj, | |
5165 | &dev_priv->mm.inactive_list, | |
5166 | mm_list) | |
5167 | cnt++; | |
5168 | mutex_unlock(&dev->struct_mutex); | |
5169 | return cnt / 100 * sysctl_vfs_cache_pressure; | |
31169714 CW |
5170 | } |
5171 | ||
1637ef41 | 5172 | rescan: |
31169714 | 5173 | /* first scan for clean buffers */ |
17250b71 | 5174 | i915_gem_retire_requests(dev); |
31169714 | 5175 | |
17250b71 CW |
5176 | list_for_each_entry_safe(obj, next, |
5177 | &dev_priv->mm.inactive_list, | |
5178 | mm_list) { | |
5179 | if (i915_gem_object_is_purgeable(obj)) { | |
05394f39 | 5180 | i915_gem_object_unbind(obj); |
17250b71 CW |
5181 | if (--nr_to_scan == 0) |
5182 | break; | |
31169714 | 5183 | } |
31169714 CW |
5184 | } |
5185 | ||
5186 | /* second pass, evict/count anything still on the inactive list */ | |
17250b71 CW |
5187 | cnt = 0; |
5188 | list_for_each_entry_safe(obj, next, | |
5189 | &dev_priv->mm.inactive_list, | |
5190 | mm_list) { | |
5191 | if (nr_to_scan) { | |
05394f39 | 5192 | i915_gem_object_unbind(obj); |
17250b71 CW |
5193 | nr_to_scan--; |
5194 | } else | |
5195 | cnt++; | |
5196 | } | |
5197 | ||
5198 | if (nr_to_scan && i915_gpu_is_active(dev)) { | |
1637ef41 CW |
5199 | /* |
5200 | * We are desperate for pages, so as a last resort, wait | |
5201 | * for the GPU to finish and discard whatever we can. | |
5202 | * This has a dramatic impact to reduce the number of | |
5203 | * OOM-killer events whilst running the GPU aggressively. | |
5204 | */ | |
17250b71 | 5205 | if (i915_gpu_idle(dev) == 0) |
1637ef41 CW |
5206 | goto rescan; |
5207 | } | |
17250b71 CW |
5208 | mutex_unlock(&dev->struct_mutex); |
5209 | return cnt / 100 * sysctl_vfs_cache_pressure; | |
31169714 | 5210 | } |