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Commit | Line | Data |
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673a394b EA |
1 | /* |
2 | * Copyright © 2008 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | * | |
26 | */ | |
27 | ||
760285e7 DH |
28 | #include <drm/drmP.h> |
29 | #include <drm/i915_drm.h> | |
673a394b | 30 | #include "i915_drv.h" |
1c5d22f7 | 31 | #include "i915_trace.h" |
652c393a | 32 | #include "intel_drv.h" |
5949eac4 | 33 | #include <linux/shmem_fs.h> |
5a0e3ad6 | 34 | #include <linux/slab.h> |
673a394b | 35 | #include <linux/swap.h> |
79e53945 | 36 | #include <linux/pci.h> |
1286ff73 | 37 | #include <linux/dma-buf.h> |
673a394b | 38 | |
05394f39 CW |
39 | static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj); |
40 | static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj); | |
88241785 CW |
41 | static __must_check int i915_gem_object_bind_to_gtt(struct drm_i915_gem_object *obj, |
42 | unsigned alignment, | |
86a1ee26 CW |
43 | bool map_and_fenceable, |
44 | bool nonblocking); | |
05394f39 CW |
45 | static int i915_gem_phys_pwrite(struct drm_device *dev, |
46 | struct drm_i915_gem_object *obj, | |
71acb5eb | 47 | struct drm_i915_gem_pwrite *args, |
05394f39 | 48 | struct drm_file *file); |
673a394b | 49 | |
61050808 CW |
50 | static void i915_gem_write_fence(struct drm_device *dev, int reg, |
51 | struct drm_i915_gem_object *obj); | |
52 | static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj, | |
53 | struct drm_i915_fence_reg *fence, | |
54 | bool enable); | |
55 | ||
17250b71 | 56 | static int i915_gem_inactive_shrink(struct shrinker *shrinker, |
1495f230 | 57 | struct shrink_control *sc); |
6c085a72 CW |
58 | static long i915_gem_purge(struct drm_i915_private *dev_priv, long target); |
59 | static void i915_gem_shrink_all(struct drm_i915_private *dev_priv); | |
8c59967c | 60 | static void i915_gem_object_truncate(struct drm_i915_gem_object *obj); |
31169714 | 61 | |
61050808 CW |
62 | static inline void i915_gem_object_fence_lost(struct drm_i915_gem_object *obj) |
63 | { | |
64 | if (obj->tiling_mode) | |
65 | i915_gem_release_mmap(obj); | |
66 | ||
67 | /* As we do not have an associated fence register, we will force | |
68 | * a tiling change if we ever need to acquire one. | |
69 | */ | |
5d82e3e6 | 70 | obj->fence_dirty = false; |
61050808 CW |
71 | obj->fence_reg = I915_FENCE_REG_NONE; |
72 | } | |
73 | ||
73aa808f CW |
74 | /* some bookkeeping */ |
75 | static void i915_gem_info_add_obj(struct drm_i915_private *dev_priv, | |
76 | size_t size) | |
77 | { | |
78 | dev_priv->mm.object_count++; | |
79 | dev_priv->mm.object_memory += size; | |
80 | } | |
81 | ||
82 | static void i915_gem_info_remove_obj(struct drm_i915_private *dev_priv, | |
83 | size_t size) | |
84 | { | |
85 | dev_priv->mm.object_count--; | |
86 | dev_priv->mm.object_memory -= size; | |
87 | } | |
88 | ||
21dd3734 | 89 | static int |
33196ded | 90 | i915_gem_wait_for_error(struct i915_gpu_error *error) |
30dbf0c0 | 91 | { |
30dbf0c0 CW |
92 | int ret; |
93 | ||
1f83fee0 DV |
94 | #define EXIT_COND (!i915_reset_in_progress(error)) |
95 | if (EXIT_COND) | |
30dbf0c0 CW |
96 | return 0; |
97 | ||
1f83fee0 DV |
98 | /* GPU is already declared terminally dead, give up. */ |
99 | if (i915_terminally_wedged(error)) | |
100 | return -EIO; | |
101 | ||
0a6759c6 DV |
102 | /* |
103 | * Only wait 10 seconds for the gpu reset to complete to avoid hanging | |
104 | * userspace. If it takes that long something really bad is going on and | |
105 | * we should simply try to bail out and fail as gracefully as possible. | |
106 | */ | |
1f83fee0 DV |
107 | ret = wait_event_interruptible_timeout(error->reset_queue, |
108 | EXIT_COND, | |
109 | 10*HZ); | |
0a6759c6 DV |
110 | if (ret == 0) { |
111 | DRM_ERROR("Timed out waiting for the gpu reset to complete\n"); | |
112 | return -EIO; | |
113 | } else if (ret < 0) { | |
30dbf0c0 | 114 | return ret; |
0a6759c6 | 115 | } |
1f83fee0 | 116 | #undef EXIT_COND |
30dbf0c0 | 117 | |
21dd3734 | 118 | return 0; |
30dbf0c0 CW |
119 | } |
120 | ||
54cf91dc | 121 | int i915_mutex_lock_interruptible(struct drm_device *dev) |
76c1dec1 | 122 | { |
33196ded | 123 | struct drm_i915_private *dev_priv = dev->dev_private; |
76c1dec1 CW |
124 | int ret; |
125 | ||
33196ded | 126 | ret = i915_gem_wait_for_error(&dev_priv->gpu_error); |
76c1dec1 CW |
127 | if (ret) |
128 | return ret; | |
129 | ||
130 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
131 | if (ret) | |
132 | return ret; | |
133 | ||
23bc5982 | 134 | WARN_ON(i915_verify_lists(dev)); |
76c1dec1 CW |
135 | return 0; |
136 | } | |
30dbf0c0 | 137 | |
7d1c4804 | 138 | static inline bool |
05394f39 | 139 | i915_gem_object_is_inactive(struct drm_i915_gem_object *obj) |
7d1c4804 | 140 | { |
6c085a72 | 141 | return obj->gtt_space && !obj->active; |
7d1c4804 CW |
142 | } |
143 | ||
79e53945 JB |
144 | int |
145 | i915_gem_init_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 146 | struct drm_file *file) |
79e53945 | 147 | { |
93d18799 | 148 | struct drm_i915_private *dev_priv = dev->dev_private; |
79e53945 | 149 | struct drm_i915_gem_init *args = data; |
2021746e | 150 | |
7bb6fb8d DV |
151 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
152 | return -ENODEV; | |
153 | ||
2021746e CW |
154 | if (args->gtt_start >= args->gtt_end || |
155 | (args->gtt_end | args->gtt_start) & (PAGE_SIZE - 1)) | |
156 | return -EINVAL; | |
79e53945 | 157 | |
f534bc0b DV |
158 | /* GEM with user mode setting was never supported on ilk and later. */ |
159 | if (INTEL_INFO(dev)->gen >= 5) | |
160 | return -ENODEV; | |
161 | ||
79e53945 | 162 | mutex_lock(&dev->struct_mutex); |
d7e5008f BW |
163 | i915_gem_setup_global_gtt(dev, args->gtt_start, args->gtt_end, |
164 | args->gtt_end); | |
93d18799 | 165 | dev_priv->gtt.mappable_end = args->gtt_end; |
673a394b EA |
166 | mutex_unlock(&dev->struct_mutex); |
167 | ||
2021746e | 168 | return 0; |
673a394b EA |
169 | } |
170 | ||
5a125c3c EA |
171 | int |
172 | i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 173 | struct drm_file *file) |
5a125c3c | 174 | { |
73aa808f | 175 | struct drm_i915_private *dev_priv = dev->dev_private; |
5a125c3c | 176 | struct drm_i915_gem_get_aperture *args = data; |
6299f992 CW |
177 | struct drm_i915_gem_object *obj; |
178 | size_t pinned; | |
5a125c3c | 179 | |
6299f992 | 180 | pinned = 0; |
73aa808f | 181 | mutex_lock(&dev->struct_mutex); |
6c085a72 | 182 | list_for_each_entry(obj, &dev_priv->mm.bound_list, gtt_list) |
1b50247a CW |
183 | if (obj->pin_count) |
184 | pinned += obj->gtt_space->size; | |
73aa808f | 185 | mutex_unlock(&dev->struct_mutex); |
5a125c3c | 186 | |
5d4545ae | 187 | args->aper_size = dev_priv->gtt.total; |
0206e353 | 188 | args->aper_available_size = args->aper_size - pinned; |
6299f992 | 189 | |
5a125c3c EA |
190 | return 0; |
191 | } | |
192 | ||
42dcedd4 CW |
193 | void *i915_gem_object_alloc(struct drm_device *dev) |
194 | { | |
195 | struct drm_i915_private *dev_priv = dev->dev_private; | |
196 | return kmem_cache_alloc(dev_priv->slab, GFP_KERNEL | __GFP_ZERO); | |
197 | } | |
198 | ||
199 | void i915_gem_object_free(struct drm_i915_gem_object *obj) | |
200 | { | |
201 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; | |
202 | kmem_cache_free(dev_priv->slab, obj); | |
203 | } | |
204 | ||
ff72145b DA |
205 | static int |
206 | i915_gem_create(struct drm_file *file, | |
207 | struct drm_device *dev, | |
208 | uint64_t size, | |
209 | uint32_t *handle_p) | |
673a394b | 210 | { |
05394f39 | 211 | struct drm_i915_gem_object *obj; |
a1a2d1d3 PP |
212 | int ret; |
213 | u32 handle; | |
673a394b | 214 | |
ff72145b | 215 | size = roundup(size, PAGE_SIZE); |
8ffc0246 CW |
216 | if (size == 0) |
217 | return -EINVAL; | |
673a394b EA |
218 | |
219 | /* Allocate the new object */ | |
ff72145b | 220 | obj = i915_gem_alloc_object(dev, size); |
673a394b EA |
221 | if (obj == NULL) |
222 | return -ENOMEM; | |
223 | ||
05394f39 | 224 | ret = drm_gem_handle_create(file, &obj->base, &handle); |
1dfd9754 | 225 | if (ret) { |
05394f39 CW |
226 | drm_gem_object_release(&obj->base); |
227 | i915_gem_info_remove_obj(dev->dev_private, obj->base.size); | |
42dcedd4 | 228 | i915_gem_object_free(obj); |
673a394b | 229 | return ret; |
1dfd9754 | 230 | } |
673a394b | 231 | |
202f2fef | 232 | /* drop reference from allocate - handle holds it now */ |
05394f39 | 233 | drm_gem_object_unreference(&obj->base); |
202f2fef CW |
234 | trace_i915_gem_object_create(obj); |
235 | ||
ff72145b | 236 | *handle_p = handle; |
673a394b EA |
237 | return 0; |
238 | } | |
239 | ||
ff72145b DA |
240 | int |
241 | i915_gem_dumb_create(struct drm_file *file, | |
242 | struct drm_device *dev, | |
243 | struct drm_mode_create_dumb *args) | |
244 | { | |
245 | /* have to work out size/pitch and return them */ | |
ed0291fd | 246 | args->pitch = ALIGN(args->width * ((args->bpp + 7) / 8), 64); |
ff72145b DA |
247 | args->size = args->pitch * args->height; |
248 | return i915_gem_create(file, dev, | |
249 | args->size, &args->handle); | |
250 | } | |
251 | ||
252 | int i915_gem_dumb_destroy(struct drm_file *file, | |
253 | struct drm_device *dev, | |
254 | uint32_t handle) | |
255 | { | |
256 | return drm_gem_handle_delete(file, handle); | |
257 | } | |
258 | ||
259 | /** | |
260 | * Creates a new mm object and returns a handle to it. | |
261 | */ | |
262 | int | |
263 | i915_gem_create_ioctl(struct drm_device *dev, void *data, | |
264 | struct drm_file *file) | |
265 | { | |
266 | struct drm_i915_gem_create *args = data; | |
63ed2cb2 | 267 | |
ff72145b DA |
268 | return i915_gem_create(file, dev, |
269 | args->size, &args->handle); | |
270 | } | |
271 | ||
8461d226 DV |
272 | static inline int |
273 | __copy_to_user_swizzled(char __user *cpu_vaddr, | |
274 | const char *gpu_vaddr, int gpu_offset, | |
275 | int length) | |
276 | { | |
277 | int ret, cpu_offset = 0; | |
278 | ||
279 | while (length > 0) { | |
280 | int cacheline_end = ALIGN(gpu_offset + 1, 64); | |
281 | int this_length = min(cacheline_end - gpu_offset, length); | |
282 | int swizzled_gpu_offset = gpu_offset ^ 64; | |
283 | ||
284 | ret = __copy_to_user(cpu_vaddr + cpu_offset, | |
285 | gpu_vaddr + swizzled_gpu_offset, | |
286 | this_length); | |
287 | if (ret) | |
288 | return ret + length; | |
289 | ||
290 | cpu_offset += this_length; | |
291 | gpu_offset += this_length; | |
292 | length -= this_length; | |
293 | } | |
294 | ||
295 | return 0; | |
296 | } | |
297 | ||
8c59967c | 298 | static inline int |
4f0c7cfb BW |
299 | __copy_from_user_swizzled(char *gpu_vaddr, int gpu_offset, |
300 | const char __user *cpu_vaddr, | |
8c59967c DV |
301 | int length) |
302 | { | |
303 | int ret, cpu_offset = 0; | |
304 | ||
305 | while (length > 0) { | |
306 | int cacheline_end = ALIGN(gpu_offset + 1, 64); | |
307 | int this_length = min(cacheline_end - gpu_offset, length); | |
308 | int swizzled_gpu_offset = gpu_offset ^ 64; | |
309 | ||
310 | ret = __copy_from_user(gpu_vaddr + swizzled_gpu_offset, | |
311 | cpu_vaddr + cpu_offset, | |
312 | this_length); | |
313 | if (ret) | |
314 | return ret + length; | |
315 | ||
316 | cpu_offset += this_length; | |
317 | gpu_offset += this_length; | |
318 | length -= this_length; | |
319 | } | |
320 | ||
321 | return 0; | |
322 | } | |
323 | ||
d174bd64 DV |
324 | /* Per-page copy function for the shmem pread fastpath. |
325 | * Flushes invalid cachelines before reading the target if | |
326 | * needs_clflush is set. */ | |
eb01459f | 327 | static int |
d174bd64 DV |
328 | shmem_pread_fast(struct page *page, int shmem_page_offset, int page_length, |
329 | char __user *user_data, | |
330 | bool page_do_bit17_swizzling, bool needs_clflush) | |
331 | { | |
332 | char *vaddr; | |
333 | int ret; | |
334 | ||
e7e58eb5 | 335 | if (unlikely(page_do_bit17_swizzling)) |
d174bd64 DV |
336 | return -EINVAL; |
337 | ||
338 | vaddr = kmap_atomic(page); | |
339 | if (needs_clflush) | |
340 | drm_clflush_virt_range(vaddr + shmem_page_offset, | |
341 | page_length); | |
342 | ret = __copy_to_user_inatomic(user_data, | |
343 | vaddr + shmem_page_offset, | |
344 | page_length); | |
345 | kunmap_atomic(vaddr); | |
346 | ||
f60d7f0c | 347 | return ret ? -EFAULT : 0; |
d174bd64 DV |
348 | } |
349 | ||
23c18c71 DV |
350 | static void |
351 | shmem_clflush_swizzled_range(char *addr, unsigned long length, | |
352 | bool swizzled) | |
353 | { | |
e7e58eb5 | 354 | if (unlikely(swizzled)) { |
23c18c71 DV |
355 | unsigned long start = (unsigned long) addr; |
356 | unsigned long end = (unsigned long) addr + length; | |
357 | ||
358 | /* For swizzling simply ensure that we always flush both | |
359 | * channels. Lame, but simple and it works. Swizzled | |
360 | * pwrite/pread is far from a hotpath - current userspace | |
361 | * doesn't use it at all. */ | |
362 | start = round_down(start, 128); | |
363 | end = round_up(end, 128); | |
364 | ||
365 | drm_clflush_virt_range((void *)start, end - start); | |
366 | } else { | |
367 | drm_clflush_virt_range(addr, length); | |
368 | } | |
369 | ||
370 | } | |
371 | ||
d174bd64 DV |
372 | /* Only difference to the fast-path function is that this can handle bit17 |
373 | * and uses non-atomic copy and kmap functions. */ | |
374 | static int | |
375 | shmem_pread_slow(struct page *page, int shmem_page_offset, int page_length, | |
376 | char __user *user_data, | |
377 | bool page_do_bit17_swizzling, bool needs_clflush) | |
378 | { | |
379 | char *vaddr; | |
380 | int ret; | |
381 | ||
382 | vaddr = kmap(page); | |
383 | if (needs_clflush) | |
23c18c71 DV |
384 | shmem_clflush_swizzled_range(vaddr + shmem_page_offset, |
385 | page_length, | |
386 | page_do_bit17_swizzling); | |
d174bd64 DV |
387 | |
388 | if (page_do_bit17_swizzling) | |
389 | ret = __copy_to_user_swizzled(user_data, | |
390 | vaddr, shmem_page_offset, | |
391 | page_length); | |
392 | else | |
393 | ret = __copy_to_user(user_data, | |
394 | vaddr + shmem_page_offset, | |
395 | page_length); | |
396 | kunmap(page); | |
397 | ||
f60d7f0c | 398 | return ret ? - EFAULT : 0; |
d174bd64 DV |
399 | } |
400 | ||
eb01459f | 401 | static int |
dbf7bff0 DV |
402 | i915_gem_shmem_pread(struct drm_device *dev, |
403 | struct drm_i915_gem_object *obj, | |
404 | struct drm_i915_gem_pread *args, | |
405 | struct drm_file *file) | |
eb01459f | 406 | { |
8461d226 | 407 | char __user *user_data; |
eb01459f | 408 | ssize_t remain; |
8461d226 | 409 | loff_t offset; |
eb2c0c81 | 410 | int shmem_page_offset, page_length, ret = 0; |
8461d226 | 411 | int obj_do_bit17_swizzling, page_do_bit17_swizzling; |
96d79b52 | 412 | int prefaulted = 0; |
8489731c | 413 | int needs_clflush = 0; |
9da3da66 CW |
414 | struct scatterlist *sg; |
415 | int i; | |
eb01459f | 416 | |
8461d226 | 417 | user_data = (char __user *) (uintptr_t) args->data_ptr; |
eb01459f EA |
418 | remain = args->size; |
419 | ||
8461d226 | 420 | obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj); |
eb01459f | 421 | |
8489731c DV |
422 | if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU)) { |
423 | /* If we're not in the cpu read domain, set ourself into the gtt | |
424 | * read domain and manually flush cachelines (if required). This | |
425 | * optimizes for the case when the gpu will dirty the data | |
426 | * anyway again before the next pread happens. */ | |
427 | if (obj->cache_level == I915_CACHE_NONE) | |
428 | needs_clflush = 1; | |
6c085a72 CW |
429 | if (obj->gtt_space) { |
430 | ret = i915_gem_object_set_to_gtt_domain(obj, false); | |
431 | if (ret) | |
432 | return ret; | |
433 | } | |
8489731c | 434 | } |
eb01459f | 435 | |
f60d7f0c CW |
436 | ret = i915_gem_object_get_pages(obj); |
437 | if (ret) | |
438 | return ret; | |
439 | ||
440 | i915_gem_object_pin_pages(obj); | |
441 | ||
8461d226 | 442 | offset = args->offset; |
eb01459f | 443 | |
9da3da66 | 444 | for_each_sg(obj->pages->sgl, sg, obj->pages->nents, i) { |
e5281ccd CW |
445 | struct page *page; |
446 | ||
9da3da66 CW |
447 | if (i < offset >> PAGE_SHIFT) |
448 | continue; | |
449 | ||
450 | if (remain <= 0) | |
451 | break; | |
452 | ||
eb01459f EA |
453 | /* Operation in this page |
454 | * | |
eb01459f | 455 | * shmem_page_offset = offset within page in shmem file |
eb01459f EA |
456 | * page_length = bytes to copy for this page |
457 | */ | |
c8cbbb8b | 458 | shmem_page_offset = offset_in_page(offset); |
eb01459f EA |
459 | page_length = remain; |
460 | if ((shmem_page_offset + page_length) > PAGE_SIZE) | |
461 | page_length = PAGE_SIZE - shmem_page_offset; | |
eb01459f | 462 | |
9da3da66 | 463 | page = sg_page(sg); |
8461d226 DV |
464 | page_do_bit17_swizzling = obj_do_bit17_swizzling && |
465 | (page_to_phys(page) & (1 << 17)) != 0; | |
466 | ||
d174bd64 DV |
467 | ret = shmem_pread_fast(page, shmem_page_offset, page_length, |
468 | user_data, page_do_bit17_swizzling, | |
469 | needs_clflush); | |
470 | if (ret == 0) | |
471 | goto next_page; | |
dbf7bff0 | 472 | |
dbf7bff0 DV |
473 | mutex_unlock(&dev->struct_mutex); |
474 | ||
96d79b52 | 475 | if (!prefaulted) { |
f56f821f | 476 | ret = fault_in_multipages_writeable(user_data, remain); |
96d79b52 DV |
477 | /* Userspace is tricking us, but we've already clobbered |
478 | * its pages with the prefault and promised to write the | |
479 | * data up to the first fault. Hence ignore any errors | |
480 | * and just continue. */ | |
481 | (void)ret; | |
482 | prefaulted = 1; | |
483 | } | |
eb01459f | 484 | |
d174bd64 DV |
485 | ret = shmem_pread_slow(page, shmem_page_offset, page_length, |
486 | user_data, page_do_bit17_swizzling, | |
487 | needs_clflush); | |
eb01459f | 488 | |
dbf7bff0 | 489 | mutex_lock(&dev->struct_mutex); |
f60d7f0c | 490 | |
dbf7bff0 | 491 | next_page: |
e5281ccd | 492 | mark_page_accessed(page); |
e5281ccd | 493 | |
f60d7f0c | 494 | if (ret) |
8461d226 | 495 | goto out; |
8461d226 | 496 | |
eb01459f | 497 | remain -= page_length; |
8461d226 | 498 | user_data += page_length; |
eb01459f EA |
499 | offset += page_length; |
500 | } | |
501 | ||
4f27b75d | 502 | out: |
f60d7f0c CW |
503 | i915_gem_object_unpin_pages(obj); |
504 | ||
eb01459f EA |
505 | return ret; |
506 | } | |
507 | ||
673a394b EA |
508 | /** |
509 | * Reads data from the object referenced by handle. | |
510 | * | |
511 | * On error, the contents of *data are undefined. | |
512 | */ | |
513 | int | |
514 | i915_gem_pread_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 515 | struct drm_file *file) |
673a394b EA |
516 | { |
517 | struct drm_i915_gem_pread *args = data; | |
05394f39 | 518 | struct drm_i915_gem_object *obj; |
35b62a89 | 519 | int ret = 0; |
673a394b | 520 | |
51311d0a CW |
521 | if (args->size == 0) |
522 | return 0; | |
523 | ||
524 | if (!access_ok(VERIFY_WRITE, | |
525 | (char __user *)(uintptr_t)args->data_ptr, | |
526 | args->size)) | |
527 | return -EFAULT; | |
528 | ||
4f27b75d | 529 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 530 | if (ret) |
4f27b75d | 531 | return ret; |
673a394b | 532 | |
05394f39 | 533 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 534 | if (&obj->base == NULL) { |
1d7cfea1 CW |
535 | ret = -ENOENT; |
536 | goto unlock; | |
4f27b75d | 537 | } |
673a394b | 538 | |
7dcd2499 | 539 | /* Bounds check source. */ |
05394f39 CW |
540 | if (args->offset > obj->base.size || |
541 | args->size > obj->base.size - args->offset) { | |
ce9d419d | 542 | ret = -EINVAL; |
35b62a89 | 543 | goto out; |
ce9d419d CW |
544 | } |
545 | ||
1286ff73 DV |
546 | /* prime objects have no backing filp to GEM pread/pwrite |
547 | * pages from. | |
548 | */ | |
549 | if (!obj->base.filp) { | |
550 | ret = -EINVAL; | |
551 | goto out; | |
552 | } | |
553 | ||
db53a302 CW |
554 | trace_i915_gem_object_pread(obj, args->offset, args->size); |
555 | ||
dbf7bff0 | 556 | ret = i915_gem_shmem_pread(dev, obj, args, file); |
673a394b | 557 | |
35b62a89 | 558 | out: |
05394f39 | 559 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 560 | unlock: |
4f27b75d | 561 | mutex_unlock(&dev->struct_mutex); |
eb01459f | 562 | return ret; |
673a394b EA |
563 | } |
564 | ||
0839ccb8 KP |
565 | /* This is the fast write path which cannot handle |
566 | * page faults in the source data | |
9b7530cc | 567 | */ |
0839ccb8 KP |
568 | |
569 | static inline int | |
570 | fast_user_write(struct io_mapping *mapping, | |
571 | loff_t page_base, int page_offset, | |
572 | char __user *user_data, | |
573 | int length) | |
9b7530cc | 574 | { |
4f0c7cfb BW |
575 | void __iomem *vaddr_atomic; |
576 | void *vaddr; | |
0839ccb8 | 577 | unsigned long unwritten; |
9b7530cc | 578 | |
3e4d3af5 | 579 | vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base); |
4f0c7cfb BW |
580 | /* We can use the cpu mem copy function because this is X86. */ |
581 | vaddr = (void __force*)vaddr_atomic + page_offset; | |
582 | unwritten = __copy_from_user_inatomic_nocache(vaddr, | |
0839ccb8 | 583 | user_data, length); |
3e4d3af5 | 584 | io_mapping_unmap_atomic(vaddr_atomic); |
fbd5a26d | 585 | return unwritten; |
0839ccb8 KP |
586 | } |
587 | ||
3de09aa3 EA |
588 | /** |
589 | * This is the fast pwrite path, where we copy the data directly from the | |
590 | * user into the GTT, uncached. | |
591 | */ | |
673a394b | 592 | static int |
05394f39 CW |
593 | i915_gem_gtt_pwrite_fast(struct drm_device *dev, |
594 | struct drm_i915_gem_object *obj, | |
3de09aa3 | 595 | struct drm_i915_gem_pwrite *args, |
05394f39 | 596 | struct drm_file *file) |
673a394b | 597 | { |
0839ccb8 | 598 | drm_i915_private_t *dev_priv = dev->dev_private; |
673a394b | 599 | ssize_t remain; |
0839ccb8 | 600 | loff_t offset, page_base; |
673a394b | 601 | char __user *user_data; |
935aaa69 DV |
602 | int page_offset, page_length, ret; |
603 | ||
86a1ee26 | 604 | ret = i915_gem_object_pin(obj, 0, true, true); |
935aaa69 DV |
605 | if (ret) |
606 | goto out; | |
607 | ||
608 | ret = i915_gem_object_set_to_gtt_domain(obj, true); | |
609 | if (ret) | |
610 | goto out_unpin; | |
611 | ||
612 | ret = i915_gem_object_put_fence(obj); | |
613 | if (ret) | |
614 | goto out_unpin; | |
673a394b EA |
615 | |
616 | user_data = (char __user *) (uintptr_t) args->data_ptr; | |
617 | remain = args->size; | |
673a394b | 618 | |
05394f39 | 619 | offset = obj->gtt_offset + args->offset; |
673a394b EA |
620 | |
621 | while (remain > 0) { | |
622 | /* Operation in this page | |
623 | * | |
0839ccb8 KP |
624 | * page_base = page offset within aperture |
625 | * page_offset = offset within page | |
626 | * page_length = bytes to copy for this page | |
673a394b | 627 | */ |
c8cbbb8b CW |
628 | page_base = offset & PAGE_MASK; |
629 | page_offset = offset_in_page(offset); | |
0839ccb8 KP |
630 | page_length = remain; |
631 | if ((page_offset + remain) > PAGE_SIZE) | |
632 | page_length = PAGE_SIZE - page_offset; | |
633 | ||
0839ccb8 | 634 | /* If we get a fault while copying data, then (presumably) our |
3de09aa3 EA |
635 | * source page isn't available. Return the error and we'll |
636 | * retry in the slow path. | |
0839ccb8 | 637 | */ |
5d4545ae | 638 | if (fast_user_write(dev_priv->gtt.mappable, page_base, |
935aaa69 DV |
639 | page_offset, user_data, page_length)) { |
640 | ret = -EFAULT; | |
641 | goto out_unpin; | |
642 | } | |
673a394b | 643 | |
0839ccb8 KP |
644 | remain -= page_length; |
645 | user_data += page_length; | |
646 | offset += page_length; | |
673a394b | 647 | } |
673a394b | 648 | |
935aaa69 DV |
649 | out_unpin: |
650 | i915_gem_object_unpin(obj); | |
651 | out: | |
3de09aa3 | 652 | return ret; |
673a394b EA |
653 | } |
654 | ||
d174bd64 DV |
655 | /* Per-page copy function for the shmem pwrite fastpath. |
656 | * Flushes invalid cachelines before writing to the target if | |
657 | * needs_clflush_before is set and flushes out any written cachelines after | |
658 | * writing if needs_clflush is set. */ | |
3043c60c | 659 | static int |
d174bd64 DV |
660 | shmem_pwrite_fast(struct page *page, int shmem_page_offset, int page_length, |
661 | char __user *user_data, | |
662 | bool page_do_bit17_swizzling, | |
663 | bool needs_clflush_before, | |
664 | bool needs_clflush_after) | |
673a394b | 665 | { |
d174bd64 | 666 | char *vaddr; |
673a394b | 667 | int ret; |
3de09aa3 | 668 | |
e7e58eb5 | 669 | if (unlikely(page_do_bit17_swizzling)) |
d174bd64 | 670 | return -EINVAL; |
3de09aa3 | 671 | |
d174bd64 DV |
672 | vaddr = kmap_atomic(page); |
673 | if (needs_clflush_before) | |
674 | drm_clflush_virt_range(vaddr + shmem_page_offset, | |
675 | page_length); | |
676 | ret = __copy_from_user_inatomic_nocache(vaddr + shmem_page_offset, | |
677 | user_data, | |
678 | page_length); | |
679 | if (needs_clflush_after) | |
680 | drm_clflush_virt_range(vaddr + shmem_page_offset, | |
681 | page_length); | |
682 | kunmap_atomic(vaddr); | |
3de09aa3 | 683 | |
755d2218 | 684 | return ret ? -EFAULT : 0; |
3de09aa3 EA |
685 | } |
686 | ||
d174bd64 DV |
687 | /* Only difference to the fast-path function is that this can handle bit17 |
688 | * and uses non-atomic copy and kmap functions. */ | |
3043c60c | 689 | static int |
d174bd64 DV |
690 | shmem_pwrite_slow(struct page *page, int shmem_page_offset, int page_length, |
691 | char __user *user_data, | |
692 | bool page_do_bit17_swizzling, | |
693 | bool needs_clflush_before, | |
694 | bool needs_clflush_after) | |
673a394b | 695 | { |
d174bd64 DV |
696 | char *vaddr; |
697 | int ret; | |
e5281ccd | 698 | |
d174bd64 | 699 | vaddr = kmap(page); |
e7e58eb5 | 700 | if (unlikely(needs_clflush_before || page_do_bit17_swizzling)) |
23c18c71 DV |
701 | shmem_clflush_swizzled_range(vaddr + shmem_page_offset, |
702 | page_length, | |
703 | page_do_bit17_swizzling); | |
d174bd64 DV |
704 | if (page_do_bit17_swizzling) |
705 | ret = __copy_from_user_swizzled(vaddr, shmem_page_offset, | |
e5281ccd CW |
706 | user_data, |
707 | page_length); | |
d174bd64 DV |
708 | else |
709 | ret = __copy_from_user(vaddr + shmem_page_offset, | |
710 | user_data, | |
711 | page_length); | |
712 | if (needs_clflush_after) | |
23c18c71 DV |
713 | shmem_clflush_swizzled_range(vaddr + shmem_page_offset, |
714 | page_length, | |
715 | page_do_bit17_swizzling); | |
d174bd64 | 716 | kunmap(page); |
40123c1f | 717 | |
755d2218 | 718 | return ret ? -EFAULT : 0; |
40123c1f EA |
719 | } |
720 | ||
40123c1f | 721 | static int |
e244a443 DV |
722 | i915_gem_shmem_pwrite(struct drm_device *dev, |
723 | struct drm_i915_gem_object *obj, | |
724 | struct drm_i915_gem_pwrite *args, | |
725 | struct drm_file *file) | |
40123c1f | 726 | { |
40123c1f | 727 | ssize_t remain; |
8c59967c DV |
728 | loff_t offset; |
729 | char __user *user_data; | |
eb2c0c81 | 730 | int shmem_page_offset, page_length, ret = 0; |
8c59967c | 731 | int obj_do_bit17_swizzling, page_do_bit17_swizzling; |
e244a443 | 732 | int hit_slowpath = 0; |
58642885 DV |
733 | int needs_clflush_after = 0; |
734 | int needs_clflush_before = 0; | |
9da3da66 CW |
735 | int i; |
736 | struct scatterlist *sg; | |
40123c1f | 737 | |
8c59967c | 738 | user_data = (char __user *) (uintptr_t) args->data_ptr; |
40123c1f EA |
739 | remain = args->size; |
740 | ||
8c59967c | 741 | obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj); |
40123c1f | 742 | |
58642885 DV |
743 | if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) { |
744 | /* If we're not in the cpu write domain, set ourself into the gtt | |
745 | * write domain and manually flush cachelines (if required). This | |
746 | * optimizes for the case when the gpu will use the data | |
747 | * right away and we therefore have to clflush anyway. */ | |
748 | if (obj->cache_level == I915_CACHE_NONE) | |
749 | needs_clflush_after = 1; | |
6c085a72 CW |
750 | if (obj->gtt_space) { |
751 | ret = i915_gem_object_set_to_gtt_domain(obj, true); | |
752 | if (ret) | |
753 | return ret; | |
754 | } | |
58642885 DV |
755 | } |
756 | /* Same trick applies for invalidate partially written cachelines before | |
757 | * writing. */ | |
758 | if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU) | |
759 | && obj->cache_level == I915_CACHE_NONE) | |
760 | needs_clflush_before = 1; | |
761 | ||
755d2218 CW |
762 | ret = i915_gem_object_get_pages(obj); |
763 | if (ret) | |
764 | return ret; | |
765 | ||
766 | i915_gem_object_pin_pages(obj); | |
767 | ||
673a394b | 768 | offset = args->offset; |
05394f39 | 769 | obj->dirty = 1; |
673a394b | 770 | |
9da3da66 | 771 | for_each_sg(obj->pages->sgl, sg, obj->pages->nents, i) { |
e5281ccd | 772 | struct page *page; |
58642885 | 773 | int partial_cacheline_write; |
e5281ccd | 774 | |
9da3da66 CW |
775 | if (i < offset >> PAGE_SHIFT) |
776 | continue; | |
777 | ||
778 | if (remain <= 0) | |
779 | break; | |
780 | ||
40123c1f EA |
781 | /* Operation in this page |
782 | * | |
40123c1f | 783 | * shmem_page_offset = offset within page in shmem file |
40123c1f EA |
784 | * page_length = bytes to copy for this page |
785 | */ | |
c8cbbb8b | 786 | shmem_page_offset = offset_in_page(offset); |
40123c1f EA |
787 | |
788 | page_length = remain; | |
789 | if ((shmem_page_offset + page_length) > PAGE_SIZE) | |
790 | page_length = PAGE_SIZE - shmem_page_offset; | |
40123c1f | 791 | |
58642885 DV |
792 | /* If we don't overwrite a cacheline completely we need to be |
793 | * careful to have up-to-date data by first clflushing. Don't | |
794 | * overcomplicate things and flush the entire patch. */ | |
795 | partial_cacheline_write = needs_clflush_before && | |
796 | ((shmem_page_offset | page_length) | |
797 | & (boot_cpu_data.x86_clflush_size - 1)); | |
798 | ||
9da3da66 | 799 | page = sg_page(sg); |
8c59967c DV |
800 | page_do_bit17_swizzling = obj_do_bit17_swizzling && |
801 | (page_to_phys(page) & (1 << 17)) != 0; | |
802 | ||
d174bd64 DV |
803 | ret = shmem_pwrite_fast(page, shmem_page_offset, page_length, |
804 | user_data, page_do_bit17_swizzling, | |
805 | partial_cacheline_write, | |
806 | needs_clflush_after); | |
807 | if (ret == 0) | |
808 | goto next_page; | |
e244a443 DV |
809 | |
810 | hit_slowpath = 1; | |
e244a443 | 811 | mutex_unlock(&dev->struct_mutex); |
d174bd64 DV |
812 | ret = shmem_pwrite_slow(page, shmem_page_offset, page_length, |
813 | user_data, page_do_bit17_swizzling, | |
814 | partial_cacheline_write, | |
815 | needs_clflush_after); | |
40123c1f | 816 | |
e244a443 | 817 | mutex_lock(&dev->struct_mutex); |
755d2218 | 818 | |
e244a443 | 819 | next_page: |
e5281ccd CW |
820 | set_page_dirty(page); |
821 | mark_page_accessed(page); | |
e5281ccd | 822 | |
755d2218 | 823 | if (ret) |
8c59967c | 824 | goto out; |
8c59967c | 825 | |
40123c1f | 826 | remain -= page_length; |
8c59967c | 827 | user_data += page_length; |
40123c1f | 828 | offset += page_length; |
673a394b EA |
829 | } |
830 | ||
fbd5a26d | 831 | out: |
755d2218 CW |
832 | i915_gem_object_unpin_pages(obj); |
833 | ||
e244a443 | 834 | if (hit_slowpath) { |
8dcf015e DV |
835 | /* |
836 | * Fixup: Flush cpu caches in case we didn't flush the dirty | |
837 | * cachelines in-line while writing and the object moved | |
838 | * out of the cpu write domain while we've dropped the lock. | |
839 | */ | |
840 | if (!needs_clflush_after && | |
841 | obj->base.write_domain != I915_GEM_DOMAIN_CPU) { | |
e244a443 | 842 | i915_gem_clflush_object(obj); |
e76e9aeb | 843 | i915_gem_chipset_flush(dev); |
e244a443 | 844 | } |
8c59967c | 845 | } |
673a394b | 846 | |
58642885 | 847 | if (needs_clflush_after) |
e76e9aeb | 848 | i915_gem_chipset_flush(dev); |
58642885 | 849 | |
40123c1f | 850 | return ret; |
673a394b EA |
851 | } |
852 | ||
853 | /** | |
854 | * Writes data to the object referenced by handle. | |
855 | * | |
856 | * On error, the contents of the buffer that were to be modified are undefined. | |
857 | */ | |
858 | int | |
859 | i915_gem_pwrite_ioctl(struct drm_device *dev, void *data, | |
fbd5a26d | 860 | struct drm_file *file) |
673a394b EA |
861 | { |
862 | struct drm_i915_gem_pwrite *args = data; | |
05394f39 | 863 | struct drm_i915_gem_object *obj; |
51311d0a CW |
864 | int ret; |
865 | ||
866 | if (args->size == 0) | |
867 | return 0; | |
868 | ||
869 | if (!access_ok(VERIFY_READ, | |
870 | (char __user *)(uintptr_t)args->data_ptr, | |
871 | args->size)) | |
872 | return -EFAULT; | |
873 | ||
f56f821f DV |
874 | ret = fault_in_multipages_readable((char __user *)(uintptr_t)args->data_ptr, |
875 | args->size); | |
51311d0a CW |
876 | if (ret) |
877 | return -EFAULT; | |
673a394b | 878 | |
fbd5a26d | 879 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 880 | if (ret) |
fbd5a26d | 881 | return ret; |
1d7cfea1 | 882 | |
05394f39 | 883 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 884 | if (&obj->base == NULL) { |
1d7cfea1 CW |
885 | ret = -ENOENT; |
886 | goto unlock; | |
fbd5a26d | 887 | } |
673a394b | 888 | |
7dcd2499 | 889 | /* Bounds check destination. */ |
05394f39 CW |
890 | if (args->offset > obj->base.size || |
891 | args->size > obj->base.size - args->offset) { | |
ce9d419d | 892 | ret = -EINVAL; |
35b62a89 | 893 | goto out; |
ce9d419d CW |
894 | } |
895 | ||
1286ff73 DV |
896 | /* prime objects have no backing filp to GEM pread/pwrite |
897 | * pages from. | |
898 | */ | |
899 | if (!obj->base.filp) { | |
900 | ret = -EINVAL; | |
901 | goto out; | |
902 | } | |
903 | ||
db53a302 CW |
904 | trace_i915_gem_object_pwrite(obj, args->offset, args->size); |
905 | ||
935aaa69 | 906 | ret = -EFAULT; |
673a394b EA |
907 | /* We can only do the GTT pwrite on untiled buffers, as otherwise |
908 | * it would end up going through the fenced access, and we'll get | |
909 | * different detiling behavior between reading and writing. | |
910 | * pread/pwrite currently are reading and writing from the CPU | |
911 | * perspective, requiring manual detiling by the client. | |
912 | */ | |
5c0480f2 | 913 | if (obj->phys_obj) { |
fbd5a26d | 914 | ret = i915_gem_phys_pwrite(dev, obj, args, file); |
5c0480f2 DV |
915 | goto out; |
916 | } | |
917 | ||
86a1ee26 | 918 | if (obj->cache_level == I915_CACHE_NONE && |
c07496fa | 919 | obj->tiling_mode == I915_TILING_NONE && |
5c0480f2 | 920 | obj->base.write_domain != I915_GEM_DOMAIN_CPU) { |
fbd5a26d | 921 | ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file); |
935aaa69 DV |
922 | /* Note that the gtt paths might fail with non-page-backed user |
923 | * pointers (e.g. gtt mappings when moving data between | |
924 | * textures). Fallback to the shmem path in that case. */ | |
fbd5a26d | 925 | } |
673a394b | 926 | |
86a1ee26 | 927 | if (ret == -EFAULT || ret == -ENOSPC) |
935aaa69 | 928 | ret = i915_gem_shmem_pwrite(dev, obj, args, file); |
5c0480f2 | 929 | |
35b62a89 | 930 | out: |
05394f39 | 931 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 932 | unlock: |
fbd5a26d | 933 | mutex_unlock(&dev->struct_mutex); |
673a394b EA |
934 | return ret; |
935 | } | |
936 | ||
b361237b | 937 | int |
33196ded | 938 | i915_gem_check_wedge(struct i915_gpu_error *error, |
b361237b CW |
939 | bool interruptible) |
940 | { | |
1f83fee0 | 941 | if (i915_reset_in_progress(error)) { |
b361237b CW |
942 | /* Non-interruptible callers can't handle -EAGAIN, hence return |
943 | * -EIO unconditionally for these. */ | |
944 | if (!interruptible) | |
945 | return -EIO; | |
946 | ||
1f83fee0 DV |
947 | /* Recovery complete, but the reset failed ... */ |
948 | if (i915_terminally_wedged(error)) | |
b361237b CW |
949 | return -EIO; |
950 | ||
951 | return -EAGAIN; | |
952 | } | |
953 | ||
954 | return 0; | |
955 | } | |
956 | ||
957 | /* | |
958 | * Compare seqno against outstanding lazy request. Emit a request if they are | |
959 | * equal. | |
960 | */ | |
961 | static int | |
962 | i915_gem_check_olr(struct intel_ring_buffer *ring, u32 seqno) | |
963 | { | |
964 | int ret; | |
965 | ||
966 | BUG_ON(!mutex_is_locked(&ring->dev->struct_mutex)); | |
967 | ||
968 | ret = 0; | |
969 | if (seqno == ring->outstanding_lazy_request) | |
970 | ret = i915_add_request(ring, NULL, NULL); | |
971 | ||
972 | return ret; | |
973 | } | |
974 | ||
975 | /** | |
976 | * __wait_seqno - wait until execution of seqno has finished | |
977 | * @ring: the ring expected to report seqno | |
978 | * @seqno: duh! | |
979 | * @interruptible: do an interruptible wait (normally yes) | |
980 | * @timeout: in - how long to wait (NULL forever); out - how much time remaining | |
981 | * | |
982 | * Returns 0 if the seqno was found within the alloted time. Else returns the | |
983 | * errno with remaining time filled in timeout argument. | |
984 | */ | |
985 | static int __wait_seqno(struct intel_ring_buffer *ring, u32 seqno, | |
986 | bool interruptible, struct timespec *timeout) | |
987 | { | |
988 | drm_i915_private_t *dev_priv = ring->dev->dev_private; | |
989 | struct timespec before, now, wait_time={1,0}; | |
990 | unsigned long timeout_jiffies; | |
991 | long end; | |
992 | bool wait_forever = true; | |
993 | int ret; | |
994 | ||
995 | if (i915_seqno_passed(ring->get_seqno(ring, true), seqno)) | |
996 | return 0; | |
997 | ||
998 | trace_i915_gem_request_wait_begin(ring, seqno); | |
999 | ||
1000 | if (timeout != NULL) { | |
1001 | wait_time = *timeout; | |
1002 | wait_forever = false; | |
1003 | } | |
1004 | ||
1005 | timeout_jiffies = timespec_to_jiffies(&wait_time); | |
1006 | ||
1007 | if (WARN_ON(!ring->irq_get(ring))) | |
1008 | return -ENODEV; | |
1009 | ||
1010 | /* Record current time in case interrupted by signal, or wedged * */ | |
1011 | getrawmonotonic(&before); | |
1012 | ||
1013 | #define EXIT_COND \ | |
1014 | (i915_seqno_passed(ring->get_seqno(ring, false), seqno) || \ | |
1f83fee0 | 1015 | i915_reset_in_progress(&dev_priv->gpu_error)) |
b361237b CW |
1016 | do { |
1017 | if (interruptible) | |
1018 | end = wait_event_interruptible_timeout(ring->irq_queue, | |
1019 | EXIT_COND, | |
1020 | timeout_jiffies); | |
1021 | else | |
1022 | end = wait_event_timeout(ring->irq_queue, EXIT_COND, | |
1023 | timeout_jiffies); | |
1024 | ||
33196ded | 1025 | ret = i915_gem_check_wedge(&dev_priv->gpu_error, interruptible); |
b361237b CW |
1026 | if (ret) |
1027 | end = ret; | |
1028 | } while (end == 0 && wait_forever); | |
1029 | ||
1030 | getrawmonotonic(&now); | |
1031 | ||
1032 | ring->irq_put(ring); | |
1033 | trace_i915_gem_request_wait_end(ring, seqno); | |
1034 | #undef EXIT_COND | |
1035 | ||
1036 | if (timeout) { | |
1037 | struct timespec sleep_time = timespec_sub(now, before); | |
1038 | *timeout = timespec_sub(*timeout, sleep_time); | |
1039 | } | |
1040 | ||
1041 | switch (end) { | |
1042 | case -EIO: | |
1043 | case -EAGAIN: /* Wedged */ | |
1044 | case -ERESTARTSYS: /* Signal */ | |
1045 | return (int)end; | |
1046 | case 0: /* Timeout */ | |
1047 | if (timeout) | |
1048 | set_normalized_timespec(timeout, 0, 0); | |
1049 | return -ETIME; | |
1050 | default: /* Completed */ | |
1051 | WARN_ON(end < 0); /* We're not aware of other errors */ | |
1052 | return 0; | |
1053 | } | |
1054 | } | |
1055 | ||
1056 | /** | |
1057 | * Waits for a sequence number to be signaled, and cleans up the | |
1058 | * request and object lists appropriately for that event. | |
1059 | */ | |
1060 | int | |
1061 | i915_wait_seqno(struct intel_ring_buffer *ring, uint32_t seqno) | |
1062 | { | |
1063 | struct drm_device *dev = ring->dev; | |
1064 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1065 | bool interruptible = dev_priv->mm.interruptible; | |
1066 | int ret; | |
1067 | ||
1068 | BUG_ON(!mutex_is_locked(&dev->struct_mutex)); | |
1069 | BUG_ON(seqno == 0); | |
1070 | ||
33196ded | 1071 | ret = i915_gem_check_wedge(&dev_priv->gpu_error, interruptible); |
b361237b CW |
1072 | if (ret) |
1073 | return ret; | |
1074 | ||
1075 | ret = i915_gem_check_olr(ring, seqno); | |
1076 | if (ret) | |
1077 | return ret; | |
1078 | ||
1079 | return __wait_seqno(ring, seqno, interruptible, NULL); | |
1080 | } | |
1081 | ||
1082 | /** | |
1083 | * Ensures that all rendering to the object has completed and the object is | |
1084 | * safe to unbind from the GTT or access from the CPU. | |
1085 | */ | |
1086 | static __must_check int | |
1087 | i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj, | |
1088 | bool readonly) | |
1089 | { | |
1090 | struct intel_ring_buffer *ring = obj->ring; | |
1091 | u32 seqno; | |
1092 | int ret; | |
1093 | ||
1094 | seqno = readonly ? obj->last_write_seqno : obj->last_read_seqno; | |
1095 | if (seqno == 0) | |
1096 | return 0; | |
1097 | ||
1098 | ret = i915_wait_seqno(ring, seqno); | |
1099 | if (ret) | |
1100 | return ret; | |
1101 | ||
1102 | i915_gem_retire_requests_ring(ring); | |
1103 | ||
1104 | /* Manually manage the write flush as we may have not yet | |
1105 | * retired the buffer. | |
1106 | */ | |
1107 | if (obj->last_write_seqno && | |
1108 | i915_seqno_passed(seqno, obj->last_write_seqno)) { | |
1109 | obj->last_write_seqno = 0; | |
1110 | obj->base.write_domain &= ~I915_GEM_GPU_DOMAINS; | |
1111 | } | |
1112 | ||
1113 | return 0; | |
1114 | } | |
1115 | ||
3236f57a CW |
1116 | /* A nonblocking variant of the above wait. This is a highly dangerous routine |
1117 | * as the object state may change during this call. | |
1118 | */ | |
1119 | static __must_check int | |
1120 | i915_gem_object_wait_rendering__nonblocking(struct drm_i915_gem_object *obj, | |
1121 | bool readonly) | |
1122 | { | |
1123 | struct drm_device *dev = obj->base.dev; | |
1124 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1125 | struct intel_ring_buffer *ring = obj->ring; | |
1126 | u32 seqno; | |
1127 | int ret; | |
1128 | ||
1129 | BUG_ON(!mutex_is_locked(&dev->struct_mutex)); | |
1130 | BUG_ON(!dev_priv->mm.interruptible); | |
1131 | ||
1132 | seqno = readonly ? obj->last_write_seqno : obj->last_read_seqno; | |
1133 | if (seqno == 0) | |
1134 | return 0; | |
1135 | ||
33196ded | 1136 | ret = i915_gem_check_wedge(&dev_priv->gpu_error, true); |
3236f57a CW |
1137 | if (ret) |
1138 | return ret; | |
1139 | ||
1140 | ret = i915_gem_check_olr(ring, seqno); | |
1141 | if (ret) | |
1142 | return ret; | |
1143 | ||
1144 | mutex_unlock(&dev->struct_mutex); | |
1145 | ret = __wait_seqno(ring, seqno, true, NULL); | |
1146 | mutex_lock(&dev->struct_mutex); | |
1147 | ||
1148 | i915_gem_retire_requests_ring(ring); | |
1149 | ||
1150 | /* Manually manage the write flush as we may have not yet | |
1151 | * retired the buffer. | |
1152 | */ | |
1153 | if (obj->last_write_seqno && | |
1154 | i915_seqno_passed(seqno, obj->last_write_seqno)) { | |
1155 | obj->last_write_seqno = 0; | |
1156 | obj->base.write_domain &= ~I915_GEM_GPU_DOMAINS; | |
1157 | } | |
1158 | ||
1159 | return ret; | |
1160 | } | |
1161 | ||
673a394b | 1162 | /** |
2ef7eeaa EA |
1163 | * Called when user space prepares to use an object with the CPU, either |
1164 | * through the mmap ioctl's mapping or a GTT mapping. | |
673a394b EA |
1165 | */ |
1166 | int | |
1167 | i915_gem_set_domain_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 1168 | struct drm_file *file) |
673a394b EA |
1169 | { |
1170 | struct drm_i915_gem_set_domain *args = data; | |
05394f39 | 1171 | struct drm_i915_gem_object *obj; |
2ef7eeaa EA |
1172 | uint32_t read_domains = args->read_domains; |
1173 | uint32_t write_domain = args->write_domain; | |
673a394b EA |
1174 | int ret; |
1175 | ||
2ef7eeaa | 1176 | /* Only handle setting domains to types used by the CPU. */ |
21d509e3 | 1177 | if (write_domain & I915_GEM_GPU_DOMAINS) |
2ef7eeaa EA |
1178 | return -EINVAL; |
1179 | ||
21d509e3 | 1180 | if (read_domains & I915_GEM_GPU_DOMAINS) |
2ef7eeaa EA |
1181 | return -EINVAL; |
1182 | ||
1183 | /* Having something in the write domain implies it's in the read | |
1184 | * domain, and only that read domain. Enforce that in the request. | |
1185 | */ | |
1186 | if (write_domain != 0 && read_domains != write_domain) | |
1187 | return -EINVAL; | |
1188 | ||
76c1dec1 | 1189 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 1190 | if (ret) |
76c1dec1 | 1191 | return ret; |
1d7cfea1 | 1192 | |
05394f39 | 1193 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 1194 | if (&obj->base == NULL) { |
1d7cfea1 CW |
1195 | ret = -ENOENT; |
1196 | goto unlock; | |
76c1dec1 | 1197 | } |
673a394b | 1198 | |
3236f57a CW |
1199 | /* Try to flush the object off the GPU without holding the lock. |
1200 | * We will repeat the flush holding the lock in the normal manner | |
1201 | * to catch cases where we are gazumped. | |
1202 | */ | |
1203 | ret = i915_gem_object_wait_rendering__nonblocking(obj, !write_domain); | |
1204 | if (ret) | |
1205 | goto unref; | |
1206 | ||
2ef7eeaa EA |
1207 | if (read_domains & I915_GEM_DOMAIN_GTT) { |
1208 | ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0); | |
02354392 EA |
1209 | |
1210 | /* Silently promote "you're not bound, there was nothing to do" | |
1211 | * to success, since the client was just asking us to | |
1212 | * make sure everything was done. | |
1213 | */ | |
1214 | if (ret == -EINVAL) | |
1215 | ret = 0; | |
2ef7eeaa | 1216 | } else { |
e47c68e9 | 1217 | ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0); |
2ef7eeaa EA |
1218 | } |
1219 | ||
3236f57a | 1220 | unref: |
05394f39 | 1221 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 1222 | unlock: |
673a394b EA |
1223 | mutex_unlock(&dev->struct_mutex); |
1224 | return ret; | |
1225 | } | |
1226 | ||
1227 | /** | |
1228 | * Called when user space has done writes to this buffer | |
1229 | */ | |
1230 | int | |
1231 | i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 1232 | struct drm_file *file) |
673a394b EA |
1233 | { |
1234 | struct drm_i915_gem_sw_finish *args = data; | |
05394f39 | 1235 | struct drm_i915_gem_object *obj; |
673a394b EA |
1236 | int ret = 0; |
1237 | ||
76c1dec1 | 1238 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 1239 | if (ret) |
76c1dec1 | 1240 | return ret; |
1d7cfea1 | 1241 | |
05394f39 | 1242 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 1243 | if (&obj->base == NULL) { |
1d7cfea1 CW |
1244 | ret = -ENOENT; |
1245 | goto unlock; | |
673a394b EA |
1246 | } |
1247 | ||
673a394b | 1248 | /* Pinned buffers may be scanout, so flush the cache */ |
05394f39 | 1249 | if (obj->pin_count) |
e47c68e9 EA |
1250 | i915_gem_object_flush_cpu_write_domain(obj); |
1251 | ||
05394f39 | 1252 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 1253 | unlock: |
673a394b EA |
1254 | mutex_unlock(&dev->struct_mutex); |
1255 | return ret; | |
1256 | } | |
1257 | ||
1258 | /** | |
1259 | * Maps the contents of an object, returning the address it is mapped | |
1260 | * into. | |
1261 | * | |
1262 | * While the mapping holds a reference on the contents of the object, it doesn't | |
1263 | * imply a ref on the object itself. | |
1264 | */ | |
1265 | int | |
1266 | i915_gem_mmap_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 1267 | struct drm_file *file) |
673a394b EA |
1268 | { |
1269 | struct drm_i915_gem_mmap *args = data; | |
1270 | struct drm_gem_object *obj; | |
673a394b EA |
1271 | unsigned long addr; |
1272 | ||
05394f39 | 1273 | obj = drm_gem_object_lookup(dev, file, args->handle); |
673a394b | 1274 | if (obj == NULL) |
bf79cb91 | 1275 | return -ENOENT; |
673a394b | 1276 | |
1286ff73 DV |
1277 | /* prime objects have no backing filp to GEM mmap |
1278 | * pages from. | |
1279 | */ | |
1280 | if (!obj->filp) { | |
1281 | drm_gem_object_unreference_unlocked(obj); | |
1282 | return -EINVAL; | |
1283 | } | |
1284 | ||
6be5ceb0 | 1285 | addr = vm_mmap(obj->filp, 0, args->size, |
673a394b EA |
1286 | PROT_READ | PROT_WRITE, MAP_SHARED, |
1287 | args->offset); | |
bc9025bd | 1288 | drm_gem_object_unreference_unlocked(obj); |
673a394b EA |
1289 | if (IS_ERR((void *)addr)) |
1290 | return addr; | |
1291 | ||
1292 | args->addr_ptr = (uint64_t) addr; | |
1293 | ||
1294 | return 0; | |
1295 | } | |
1296 | ||
de151cf6 JB |
1297 | /** |
1298 | * i915_gem_fault - fault a page into the GTT | |
1299 | * vma: VMA in question | |
1300 | * vmf: fault info | |
1301 | * | |
1302 | * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped | |
1303 | * from userspace. The fault handler takes care of binding the object to | |
1304 | * the GTT (if needed), allocating and programming a fence register (again, | |
1305 | * only if needed based on whether the old reg is still valid or the object | |
1306 | * is tiled) and inserting a new PTE into the faulting process. | |
1307 | * | |
1308 | * Note that the faulting process may involve evicting existing objects | |
1309 | * from the GTT and/or fence registers to make room. So performance may | |
1310 | * suffer if the GTT working set is large or there are few fence registers | |
1311 | * left. | |
1312 | */ | |
1313 | int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf) | |
1314 | { | |
05394f39 CW |
1315 | struct drm_i915_gem_object *obj = to_intel_bo(vma->vm_private_data); |
1316 | struct drm_device *dev = obj->base.dev; | |
7d1c4804 | 1317 | drm_i915_private_t *dev_priv = dev->dev_private; |
de151cf6 JB |
1318 | pgoff_t page_offset; |
1319 | unsigned long pfn; | |
1320 | int ret = 0; | |
0f973f27 | 1321 | bool write = !!(vmf->flags & FAULT_FLAG_WRITE); |
de151cf6 JB |
1322 | |
1323 | /* We don't use vmf->pgoff since that has the fake offset */ | |
1324 | page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >> | |
1325 | PAGE_SHIFT; | |
1326 | ||
d9bc7e9f CW |
1327 | ret = i915_mutex_lock_interruptible(dev); |
1328 | if (ret) | |
1329 | goto out; | |
a00b10c3 | 1330 | |
db53a302 CW |
1331 | trace_i915_gem_object_fault(obj, page_offset, true, write); |
1332 | ||
eb119bd6 CW |
1333 | /* Access to snoopable pages through the GTT is incoherent. */ |
1334 | if (obj->cache_level != I915_CACHE_NONE && !HAS_LLC(dev)) { | |
1335 | ret = -EINVAL; | |
1336 | goto unlock; | |
1337 | } | |
1338 | ||
d9bc7e9f | 1339 | /* Now bind it into the GTT if needed */ |
c9839303 CW |
1340 | ret = i915_gem_object_pin(obj, 0, true, false); |
1341 | if (ret) | |
1342 | goto unlock; | |
4a684a41 | 1343 | |
c9839303 CW |
1344 | ret = i915_gem_object_set_to_gtt_domain(obj, write); |
1345 | if (ret) | |
1346 | goto unpin; | |
74898d7e | 1347 | |
06d98131 | 1348 | ret = i915_gem_object_get_fence(obj); |
d9e86c0e | 1349 | if (ret) |
c9839303 | 1350 | goto unpin; |
7d1c4804 | 1351 | |
6299f992 CW |
1352 | obj->fault_mappable = true; |
1353 | ||
5d4545ae | 1354 | pfn = ((dev_priv->gtt.mappable_base + obj->gtt_offset) >> PAGE_SHIFT) + |
de151cf6 JB |
1355 | page_offset; |
1356 | ||
1357 | /* Finally, remap it using the new GTT offset */ | |
1358 | ret = vm_insert_pfn(vma, (unsigned long)vmf->virtual_address, pfn); | |
c9839303 CW |
1359 | unpin: |
1360 | i915_gem_object_unpin(obj); | |
c715089f | 1361 | unlock: |
de151cf6 | 1362 | mutex_unlock(&dev->struct_mutex); |
d9bc7e9f | 1363 | out: |
de151cf6 | 1364 | switch (ret) { |
d9bc7e9f | 1365 | case -EIO: |
a9340cca DV |
1366 | /* If this -EIO is due to a gpu hang, give the reset code a |
1367 | * chance to clean up the mess. Otherwise return the proper | |
1368 | * SIGBUS. */ | |
1f83fee0 | 1369 | if (i915_terminally_wedged(&dev_priv->gpu_error)) |
a9340cca | 1370 | return VM_FAULT_SIGBUS; |
045e769a | 1371 | case -EAGAIN: |
d9bc7e9f CW |
1372 | /* Give the error handler a chance to run and move the |
1373 | * objects off the GPU active list. Next time we service the | |
1374 | * fault, we should be able to transition the page into the | |
1375 | * GTT without touching the GPU (and so avoid further | |
1376 | * EIO/EGAIN). If the GPU is wedged, then there is no issue | |
1377 | * with coherency, just lost writes. | |
1378 | */ | |
045e769a | 1379 | set_need_resched(); |
c715089f CW |
1380 | case 0: |
1381 | case -ERESTARTSYS: | |
bed636ab | 1382 | case -EINTR: |
e79e0fe3 DR |
1383 | case -EBUSY: |
1384 | /* | |
1385 | * EBUSY is ok: this just means that another thread | |
1386 | * already did the job. | |
1387 | */ | |
c715089f | 1388 | return VM_FAULT_NOPAGE; |
de151cf6 | 1389 | case -ENOMEM: |
de151cf6 | 1390 | return VM_FAULT_OOM; |
a7c2e1aa DV |
1391 | case -ENOSPC: |
1392 | return VM_FAULT_SIGBUS; | |
de151cf6 | 1393 | default: |
a7c2e1aa | 1394 | WARN_ONCE(ret, "unhandled error in i915_gem_fault: %i\n", ret); |
c715089f | 1395 | return VM_FAULT_SIGBUS; |
de151cf6 JB |
1396 | } |
1397 | } | |
1398 | ||
901782b2 CW |
1399 | /** |
1400 | * i915_gem_release_mmap - remove physical page mappings | |
1401 | * @obj: obj in question | |
1402 | * | |
af901ca1 | 1403 | * Preserve the reservation of the mmapping with the DRM core code, but |
901782b2 CW |
1404 | * relinquish ownership of the pages back to the system. |
1405 | * | |
1406 | * It is vital that we remove the page mapping if we have mapped a tiled | |
1407 | * object through the GTT and then lose the fence register due to | |
1408 | * resource pressure. Similarly if the object has been moved out of the | |
1409 | * aperture, than pages mapped into userspace must be revoked. Removing the | |
1410 | * mapping will then trigger a page fault on the next user access, allowing | |
1411 | * fixup by i915_gem_fault(). | |
1412 | */ | |
d05ca301 | 1413 | void |
05394f39 | 1414 | i915_gem_release_mmap(struct drm_i915_gem_object *obj) |
901782b2 | 1415 | { |
6299f992 CW |
1416 | if (!obj->fault_mappable) |
1417 | return; | |
901782b2 | 1418 | |
f6e47884 CW |
1419 | if (obj->base.dev->dev_mapping) |
1420 | unmap_mapping_range(obj->base.dev->dev_mapping, | |
1421 | (loff_t)obj->base.map_list.hash.key<<PAGE_SHIFT, | |
1422 | obj->base.size, 1); | |
fb7d516a | 1423 | |
6299f992 | 1424 | obj->fault_mappable = false; |
901782b2 CW |
1425 | } |
1426 | ||
0fa87796 | 1427 | uint32_t |
e28f8711 | 1428 | i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode) |
92b88aeb | 1429 | { |
e28f8711 | 1430 | uint32_t gtt_size; |
92b88aeb CW |
1431 | |
1432 | if (INTEL_INFO(dev)->gen >= 4 || | |
e28f8711 CW |
1433 | tiling_mode == I915_TILING_NONE) |
1434 | return size; | |
92b88aeb CW |
1435 | |
1436 | /* Previous chips need a power-of-two fence region when tiling */ | |
1437 | if (INTEL_INFO(dev)->gen == 3) | |
e28f8711 | 1438 | gtt_size = 1024*1024; |
92b88aeb | 1439 | else |
e28f8711 | 1440 | gtt_size = 512*1024; |
92b88aeb | 1441 | |
e28f8711 CW |
1442 | while (gtt_size < size) |
1443 | gtt_size <<= 1; | |
92b88aeb | 1444 | |
e28f8711 | 1445 | return gtt_size; |
92b88aeb CW |
1446 | } |
1447 | ||
de151cf6 JB |
1448 | /** |
1449 | * i915_gem_get_gtt_alignment - return required GTT alignment for an object | |
1450 | * @obj: object to check | |
1451 | * | |
1452 | * Return the required GTT alignment for an object, taking into account | |
5e783301 | 1453 | * potential fence register mapping. |
de151cf6 | 1454 | */ |
d865110c ID |
1455 | uint32_t |
1456 | i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size, | |
1457 | int tiling_mode, bool fenced) | |
de151cf6 | 1458 | { |
de151cf6 JB |
1459 | /* |
1460 | * Minimum alignment is 4k (GTT page size), but might be greater | |
1461 | * if a fence register is needed for the object. | |
1462 | */ | |
d865110c | 1463 | if (INTEL_INFO(dev)->gen >= 4 || (!fenced && IS_G33(dev)) || |
e28f8711 | 1464 | tiling_mode == I915_TILING_NONE) |
de151cf6 JB |
1465 | return 4096; |
1466 | ||
a00b10c3 CW |
1467 | /* |
1468 | * Previous chips need to be aligned to the size of the smallest | |
1469 | * fence register that can contain the object. | |
1470 | */ | |
e28f8711 | 1471 | return i915_gem_get_gtt_size(dev, size, tiling_mode); |
a00b10c3 CW |
1472 | } |
1473 | ||
d8cb5086 CW |
1474 | static int i915_gem_object_create_mmap_offset(struct drm_i915_gem_object *obj) |
1475 | { | |
1476 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; | |
1477 | int ret; | |
1478 | ||
1479 | if (obj->base.map_list.map) | |
1480 | return 0; | |
1481 | ||
da494d7c DV |
1482 | dev_priv->mm.shrinker_no_lock_stealing = true; |
1483 | ||
d8cb5086 CW |
1484 | ret = drm_gem_create_mmap_offset(&obj->base); |
1485 | if (ret != -ENOSPC) | |
da494d7c | 1486 | goto out; |
d8cb5086 CW |
1487 | |
1488 | /* Badly fragmented mmap space? The only way we can recover | |
1489 | * space is by destroying unwanted objects. We can't randomly release | |
1490 | * mmap_offsets as userspace expects them to be persistent for the | |
1491 | * lifetime of the objects. The closest we can is to release the | |
1492 | * offsets on purgeable objects by truncating it and marking it purged, | |
1493 | * which prevents userspace from ever using that object again. | |
1494 | */ | |
1495 | i915_gem_purge(dev_priv, obj->base.size >> PAGE_SHIFT); | |
1496 | ret = drm_gem_create_mmap_offset(&obj->base); | |
1497 | if (ret != -ENOSPC) | |
da494d7c | 1498 | goto out; |
d8cb5086 CW |
1499 | |
1500 | i915_gem_shrink_all(dev_priv); | |
da494d7c DV |
1501 | ret = drm_gem_create_mmap_offset(&obj->base); |
1502 | out: | |
1503 | dev_priv->mm.shrinker_no_lock_stealing = false; | |
1504 | ||
1505 | return ret; | |
d8cb5086 CW |
1506 | } |
1507 | ||
1508 | static void i915_gem_object_free_mmap_offset(struct drm_i915_gem_object *obj) | |
1509 | { | |
1510 | if (!obj->base.map_list.map) | |
1511 | return; | |
1512 | ||
1513 | drm_gem_free_mmap_offset(&obj->base); | |
1514 | } | |
1515 | ||
de151cf6 | 1516 | int |
ff72145b DA |
1517 | i915_gem_mmap_gtt(struct drm_file *file, |
1518 | struct drm_device *dev, | |
1519 | uint32_t handle, | |
1520 | uint64_t *offset) | |
de151cf6 | 1521 | { |
da761a6e | 1522 | struct drm_i915_private *dev_priv = dev->dev_private; |
05394f39 | 1523 | struct drm_i915_gem_object *obj; |
de151cf6 JB |
1524 | int ret; |
1525 | ||
76c1dec1 | 1526 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 1527 | if (ret) |
76c1dec1 | 1528 | return ret; |
de151cf6 | 1529 | |
ff72145b | 1530 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle)); |
c8725226 | 1531 | if (&obj->base == NULL) { |
1d7cfea1 CW |
1532 | ret = -ENOENT; |
1533 | goto unlock; | |
1534 | } | |
de151cf6 | 1535 | |
5d4545ae | 1536 | if (obj->base.size > dev_priv->gtt.mappable_end) { |
da761a6e | 1537 | ret = -E2BIG; |
ff56b0bc | 1538 | goto out; |
da761a6e CW |
1539 | } |
1540 | ||
05394f39 | 1541 | if (obj->madv != I915_MADV_WILLNEED) { |
ab18282d | 1542 | DRM_ERROR("Attempting to mmap a purgeable buffer\n"); |
1d7cfea1 CW |
1543 | ret = -EINVAL; |
1544 | goto out; | |
ab18282d CW |
1545 | } |
1546 | ||
d8cb5086 CW |
1547 | ret = i915_gem_object_create_mmap_offset(obj); |
1548 | if (ret) | |
1549 | goto out; | |
de151cf6 | 1550 | |
ff72145b | 1551 | *offset = (u64)obj->base.map_list.hash.key << PAGE_SHIFT; |
de151cf6 | 1552 | |
1d7cfea1 | 1553 | out: |
05394f39 | 1554 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 1555 | unlock: |
de151cf6 | 1556 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 1557 | return ret; |
de151cf6 JB |
1558 | } |
1559 | ||
ff72145b DA |
1560 | /** |
1561 | * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing | |
1562 | * @dev: DRM device | |
1563 | * @data: GTT mapping ioctl data | |
1564 | * @file: GEM object info | |
1565 | * | |
1566 | * Simply returns the fake offset to userspace so it can mmap it. | |
1567 | * The mmap call will end up in drm_gem_mmap(), which will set things | |
1568 | * up so we can get faults in the handler above. | |
1569 | * | |
1570 | * The fault handler will take care of binding the object into the GTT | |
1571 | * (since it may have been evicted to make room for something), allocating | |
1572 | * a fence register, and mapping the appropriate aperture address into | |
1573 | * userspace. | |
1574 | */ | |
1575 | int | |
1576 | i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data, | |
1577 | struct drm_file *file) | |
1578 | { | |
1579 | struct drm_i915_gem_mmap_gtt *args = data; | |
1580 | ||
ff72145b DA |
1581 | return i915_gem_mmap_gtt(file, dev, args->handle, &args->offset); |
1582 | } | |
1583 | ||
225067ee DV |
1584 | /* Immediately discard the backing storage */ |
1585 | static void | |
1586 | i915_gem_object_truncate(struct drm_i915_gem_object *obj) | |
e5281ccd | 1587 | { |
e5281ccd | 1588 | struct inode *inode; |
e5281ccd | 1589 | |
4d6294bf | 1590 | i915_gem_object_free_mmap_offset(obj); |
1286ff73 | 1591 | |
4d6294bf CW |
1592 | if (obj->base.filp == NULL) |
1593 | return; | |
e5281ccd | 1594 | |
225067ee DV |
1595 | /* Our goal here is to return as much of the memory as |
1596 | * is possible back to the system as we are called from OOM. | |
1597 | * To do this we must instruct the shmfs to drop all of its | |
1598 | * backing pages, *now*. | |
1599 | */ | |
05394f39 | 1600 | inode = obj->base.filp->f_path.dentry->d_inode; |
225067ee | 1601 | shmem_truncate_range(inode, 0, (loff_t)-1); |
e5281ccd | 1602 | |
225067ee DV |
1603 | obj->madv = __I915_MADV_PURGED; |
1604 | } | |
e5281ccd | 1605 | |
225067ee DV |
1606 | static inline int |
1607 | i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj) | |
1608 | { | |
1609 | return obj->madv == I915_MADV_DONTNEED; | |
e5281ccd CW |
1610 | } |
1611 | ||
5cdf5881 | 1612 | static void |
05394f39 | 1613 | i915_gem_object_put_pages_gtt(struct drm_i915_gem_object *obj) |
673a394b | 1614 | { |
05394f39 | 1615 | int page_count = obj->base.size / PAGE_SIZE; |
9da3da66 | 1616 | struct scatterlist *sg; |
6c085a72 | 1617 | int ret, i; |
1286ff73 | 1618 | |
05394f39 | 1619 | BUG_ON(obj->madv == __I915_MADV_PURGED); |
673a394b | 1620 | |
6c085a72 CW |
1621 | ret = i915_gem_object_set_to_cpu_domain(obj, true); |
1622 | if (ret) { | |
1623 | /* In the event of a disaster, abandon all caches and | |
1624 | * hope for the best. | |
1625 | */ | |
1626 | WARN_ON(ret != -EIO); | |
1627 | i915_gem_clflush_object(obj); | |
1628 | obj->base.read_domains = obj->base.write_domain = I915_GEM_DOMAIN_CPU; | |
1629 | } | |
1630 | ||
6dacfd2f | 1631 | if (i915_gem_object_needs_bit17_swizzle(obj)) |
280b713b EA |
1632 | i915_gem_object_save_bit_17_swizzle(obj); |
1633 | ||
05394f39 CW |
1634 | if (obj->madv == I915_MADV_DONTNEED) |
1635 | obj->dirty = 0; | |
3ef94daa | 1636 | |
9da3da66 CW |
1637 | for_each_sg(obj->pages->sgl, sg, page_count, i) { |
1638 | struct page *page = sg_page(sg); | |
1639 | ||
05394f39 | 1640 | if (obj->dirty) |
9da3da66 | 1641 | set_page_dirty(page); |
3ef94daa | 1642 | |
05394f39 | 1643 | if (obj->madv == I915_MADV_WILLNEED) |
9da3da66 | 1644 | mark_page_accessed(page); |
3ef94daa | 1645 | |
9da3da66 | 1646 | page_cache_release(page); |
3ef94daa | 1647 | } |
05394f39 | 1648 | obj->dirty = 0; |
673a394b | 1649 | |
9da3da66 CW |
1650 | sg_free_table(obj->pages); |
1651 | kfree(obj->pages); | |
37e680a1 | 1652 | } |
6c085a72 | 1653 | |
dd624afd | 1654 | int |
37e680a1 CW |
1655 | i915_gem_object_put_pages(struct drm_i915_gem_object *obj) |
1656 | { | |
1657 | const struct drm_i915_gem_object_ops *ops = obj->ops; | |
1658 | ||
2f745ad3 | 1659 | if (obj->pages == NULL) |
37e680a1 CW |
1660 | return 0; |
1661 | ||
1662 | BUG_ON(obj->gtt_space); | |
6c085a72 | 1663 | |
a5570178 CW |
1664 | if (obj->pages_pin_count) |
1665 | return -EBUSY; | |
1666 | ||
a2165e31 CW |
1667 | /* ->put_pages might need to allocate memory for the bit17 swizzle |
1668 | * array, hence protect them from being reaped by removing them from gtt | |
1669 | * lists early. */ | |
1670 | list_del(&obj->gtt_list); | |
1671 | ||
37e680a1 | 1672 | ops->put_pages(obj); |
05394f39 | 1673 | obj->pages = NULL; |
37e680a1 | 1674 | |
6c085a72 CW |
1675 | if (i915_gem_object_is_purgeable(obj)) |
1676 | i915_gem_object_truncate(obj); | |
1677 | ||
1678 | return 0; | |
1679 | } | |
1680 | ||
1681 | static long | |
1682 | i915_gem_purge(struct drm_i915_private *dev_priv, long target) | |
1683 | { | |
1684 | struct drm_i915_gem_object *obj, *next; | |
1685 | long count = 0; | |
1686 | ||
1687 | list_for_each_entry_safe(obj, next, | |
1688 | &dev_priv->mm.unbound_list, | |
1689 | gtt_list) { | |
1690 | if (i915_gem_object_is_purgeable(obj) && | |
37e680a1 | 1691 | i915_gem_object_put_pages(obj) == 0) { |
6c085a72 CW |
1692 | count += obj->base.size >> PAGE_SHIFT; |
1693 | if (count >= target) | |
1694 | return count; | |
1695 | } | |
1696 | } | |
1697 | ||
1698 | list_for_each_entry_safe(obj, next, | |
1699 | &dev_priv->mm.inactive_list, | |
1700 | mm_list) { | |
1701 | if (i915_gem_object_is_purgeable(obj) && | |
1702 | i915_gem_object_unbind(obj) == 0 && | |
37e680a1 | 1703 | i915_gem_object_put_pages(obj) == 0) { |
6c085a72 CW |
1704 | count += obj->base.size >> PAGE_SHIFT; |
1705 | if (count >= target) | |
1706 | return count; | |
1707 | } | |
1708 | } | |
1709 | ||
1710 | return count; | |
1711 | } | |
1712 | ||
1713 | static void | |
1714 | i915_gem_shrink_all(struct drm_i915_private *dev_priv) | |
1715 | { | |
1716 | struct drm_i915_gem_object *obj, *next; | |
1717 | ||
1718 | i915_gem_evict_everything(dev_priv->dev); | |
1719 | ||
1720 | list_for_each_entry_safe(obj, next, &dev_priv->mm.unbound_list, gtt_list) | |
37e680a1 | 1721 | i915_gem_object_put_pages(obj); |
225067ee DV |
1722 | } |
1723 | ||
37e680a1 | 1724 | static int |
6c085a72 | 1725 | i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj) |
e5281ccd | 1726 | { |
6c085a72 | 1727 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
e5281ccd CW |
1728 | int page_count, i; |
1729 | struct address_space *mapping; | |
9da3da66 CW |
1730 | struct sg_table *st; |
1731 | struct scatterlist *sg; | |
e5281ccd | 1732 | struct page *page; |
6c085a72 | 1733 | gfp_t gfp; |
e5281ccd | 1734 | |
6c085a72 CW |
1735 | /* Assert that the object is not currently in any GPU domain. As it |
1736 | * wasn't in the GTT, there shouldn't be any way it could have been in | |
1737 | * a GPU cache | |
1738 | */ | |
1739 | BUG_ON(obj->base.read_domains & I915_GEM_GPU_DOMAINS); | |
1740 | BUG_ON(obj->base.write_domain & I915_GEM_GPU_DOMAINS); | |
1741 | ||
9da3da66 CW |
1742 | st = kmalloc(sizeof(*st), GFP_KERNEL); |
1743 | if (st == NULL) | |
1744 | return -ENOMEM; | |
1745 | ||
05394f39 | 1746 | page_count = obj->base.size / PAGE_SIZE; |
9da3da66 CW |
1747 | if (sg_alloc_table(st, page_count, GFP_KERNEL)) { |
1748 | sg_free_table(st); | |
1749 | kfree(st); | |
e5281ccd | 1750 | return -ENOMEM; |
9da3da66 | 1751 | } |
e5281ccd | 1752 | |
9da3da66 CW |
1753 | /* Get the list of pages out of our struct file. They'll be pinned |
1754 | * at this point until we release them. | |
1755 | * | |
1756 | * Fail silently without starting the shrinker | |
1757 | */ | |
6c085a72 CW |
1758 | mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping; |
1759 | gfp = mapping_gfp_mask(mapping); | |
caf49191 | 1760 | gfp |= __GFP_NORETRY | __GFP_NOWARN | __GFP_NO_KSWAPD; |
6c085a72 | 1761 | gfp &= ~(__GFP_IO | __GFP_WAIT); |
9da3da66 | 1762 | for_each_sg(st->sgl, sg, page_count, i) { |
6c085a72 CW |
1763 | page = shmem_read_mapping_page_gfp(mapping, i, gfp); |
1764 | if (IS_ERR(page)) { | |
1765 | i915_gem_purge(dev_priv, page_count); | |
1766 | page = shmem_read_mapping_page_gfp(mapping, i, gfp); | |
1767 | } | |
1768 | if (IS_ERR(page)) { | |
1769 | /* We've tried hard to allocate the memory by reaping | |
1770 | * our own buffer, now let the real VM do its job and | |
1771 | * go down in flames if truly OOM. | |
1772 | */ | |
caf49191 | 1773 | gfp &= ~(__GFP_NORETRY | __GFP_NOWARN | __GFP_NO_KSWAPD); |
6c085a72 CW |
1774 | gfp |= __GFP_IO | __GFP_WAIT; |
1775 | ||
1776 | i915_gem_shrink_all(dev_priv); | |
1777 | page = shmem_read_mapping_page_gfp(mapping, i, gfp); | |
1778 | if (IS_ERR(page)) | |
1779 | goto err_pages; | |
1780 | ||
caf49191 | 1781 | gfp |= __GFP_NORETRY | __GFP_NOWARN | __GFP_NO_KSWAPD; |
6c085a72 CW |
1782 | gfp &= ~(__GFP_IO | __GFP_WAIT); |
1783 | } | |
e5281ccd | 1784 | |
9da3da66 | 1785 | sg_set_page(sg, page, PAGE_SIZE, 0); |
e5281ccd CW |
1786 | } |
1787 | ||
74ce6b6c CW |
1788 | obj->pages = st; |
1789 | ||
6dacfd2f | 1790 | if (i915_gem_object_needs_bit17_swizzle(obj)) |
e5281ccd CW |
1791 | i915_gem_object_do_bit_17_swizzle(obj); |
1792 | ||
1793 | return 0; | |
1794 | ||
1795 | err_pages: | |
9da3da66 CW |
1796 | for_each_sg(st->sgl, sg, i, page_count) |
1797 | page_cache_release(sg_page(sg)); | |
1798 | sg_free_table(st); | |
1799 | kfree(st); | |
e5281ccd | 1800 | return PTR_ERR(page); |
673a394b EA |
1801 | } |
1802 | ||
37e680a1 CW |
1803 | /* Ensure that the associated pages are gathered from the backing storage |
1804 | * and pinned into our object. i915_gem_object_get_pages() may be called | |
1805 | * multiple times before they are released by a single call to | |
1806 | * i915_gem_object_put_pages() - once the pages are no longer referenced | |
1807 | * either as a result of memory pressure (reaping pages under the shrinker) | |
1808 | * or as the object is itself released. | |
1809 | */ | |
1810 | int | |
1811 | i915_gem_object_get_pages(struct drm_i915_gem_object *obj) | |
1812 | { | |
1813 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; | |
1814 | const struct drm_i915_gem_object_ops *ops = obj->ops; | |
1815 | int ret; | |
1816 | ||
2f745ad3 | 1817 | if (obj->pages) |
37e680a1 CW |
1818 | return 0; |
1819 | ||
43e28f09 CW |
1820 | if (obj->madv != I915_MADV_WILLNEED) { |
1821 | DRM_ERROR("Attempting to obtain a purgeable object\n"); | |
1822 | return -EINVAL; | |
1823 | } | |
1824 | ||
a5570178 CW |
1825 | BUG_ON(obj->pages_pin_count); |
1826 | ||
37e680a1 CW |
1827 | ret = ops->get_pages(obj); |
1828 | if (ret) | |
1829 | return ret; | |
1830 | ||
1831 | list_add_tail(&obj->gtt_list, &dev_priv->mm.unbound_list); | |
1832 | return 0; | |
673a394b EA |
1833 | } |
1834 | ||
54cf91dc | 1835 | void |
05394f39 | 1836 | i915_gem_object_move_to_active(struct drm_i915_gem_object *obj, |
9d773091 | 1837 | struct intel_ring_buffer *ring) |
673a394b | 1838 | { |
05394f39 | 1839 | struct drm_device *dev = obj->base.dev; |
69dc4987 | 1840 | struct drm_i915_private *dev_priv = dev->dev_private; |
9d773091 | 1841 | u32 seqno = intel_ring_get_seqno(ring); |
617dbe27 | 1842 | |
852835f3 | 1843 | BUG_ON(ring == NULL); |
05394f39 | 1844 | obj->ring = ring; |
673a394b EA |
1845 | |
1846 | /* Add a reference if we're newly entering the active list. */ | |
05394f39 CW |
1847 | if (!obj->active) { |
1848 | drm_gem_object_reference(&obj->base); | |
1849 | obj->active = 1; | |
673a394b | 1850 | } |
e35a41de | 1851 | |
673a394b | 1852 | /* Move from whatever list we were on to the tail of execution. */ |
05394f39 CW |
1853 | list_move_tail(&obj->mm_list, &dev_priv->mm.active_list); |
1854 | list_move_tail(&obj->ring_list, &ring->active_list); | |
caea7476 | 1855 | |
0201f1ec | 1856 | obj->last_read_seqno = seqno; |
caea7476 | 1857 | |
7dd49065 | 1858 | if (obj->fenced_gpu_access) { |
caea7476 | 1859 | obj->last_fenced_seqno = seqno; |
caea7476 | 1860 | |
7dd49065 CW |
1861 | /* Bump MRU to take account of the delayed flush */ |
1862 | if (obj->fence_reg != I915_FENCE_REG_NONE) { | |
1863 | struct drm_i915_fence_reg *reg; | |
1864 | ||
1865 | reg = &dev_priv->fence_regs[obj->fence_reg]; | |
1866 | list_move_tail(®->lru_list, | |
1867 | &dev_priv->mm.fence_list); | |
1868 | } | |
caea7476 CW |
1869 | } |
1870 | } | |
1871 | ||
1872 | static void | |
caea7476 | 1873 | i915_gem_object_move_to_inactive(struct drm_i915_gem_object *obj) |
ce44b0ea | 1874 | { |
05394f39 | 1875 | struct drm_device *dev = obj->base.dev; |
caea7476 | 1876 | struct drm_i915_private *dev_priv = dev->dev_private; |
ce44b0ea | 1877 | |
65ce3027 | 1878 | BUG_ON(obj->base.write_domain & ~I915_GEM_GPU_DOMAINS); |
05394f39 | 1879 | BUG_ON(!obj->active); |
caea7476 | 1880 | |
f047e395 CW |
1881 | if (obj->pin_count) /* are we a framebuffer? */ |
1882 | intel_mark_fb_idle(obj); | |
caea7476 | 1883 | |
1b50247a | 1884 | list_move_tail(&obj->mm_list, &dev_priv->mm.inactive_list); |
caea7476 | 1885 | |
65ce3027 | 1886 | list_del_init(&obj->ring_list); |
caea7476 CW |
1887 | obj->ring = NULL; |
1888 | ||
65ce3027 CW |
1889 | obj->last_read_seqno = 0; |
1890 | obj->last_write_seqno = 0; | |
1891 | obj->base.write_domain = 0; | |
1892 | ||
1893 | obj->last_fenced_seqno = 0; | |
caea7476 | 1894 | obj->fenced_gpu_access = false; |
caea7476 CW |
1895 | |
1896 | obj->active = 0; | |
1897 | drm_gem_object_unreference(&obj->base); | |
1898 | ||
1899 | WARN_ON(i915_verify_lists(dev)); | |
ce44b0ea | 1900 | } |
673a394b | 1901 | |
9d773091 | 1902 | static int |
fca26bb4 | 1903 | i915_gem_init_seqno(struct drm_device *dev, u32 seqno) |
53d227f2 | 1904 | { |
9d773091 CW |
1905 | struct drm_i915_private *dev_priv = dev->dev_private; |
1906 | struct intel_ring_buffer *ring; | |
1907 | int ret, i, j; | |
53d227f2 | 1908 | |
107f27a5 | 1909 | /* Carefully retire all requests without writing to the rings */ |
9d773091 | 1910 | for_each_ring(ring, dev_priv, i) { |
107f27a5 CW |
1911 | ret = intel_ring_idle(ring); |
1912 | if (ret) | |
1913 | return ret; | |
9d773091 | 1914 | } |
9d773091 | 1915 | i915_gem_retire_requests(dev); |
107f27a5 CW |
1916 | |
1917 | /* Finally reset hw state */ | |
9d773091 | 1918 | for_each_ring(ring, dev_priv, i) { |
fca26bb4 | 1919 | intel_ring_init_seqno(ring, seqno); |
498d2ac1 | 1920 | |
9d773091 CW |
1921 | for (j = 0; j < ARRAY_SIZE(ring->sync_seqno); j++) |
1922 | ring->sync_seqno[j] = 0; | |
1923 | } | |
53d227f2 | 1924 | |
9d773091 | 1925 | return 0; |
53d227f2 DV |
1926 | } |
1927 | ||
fca26bb4 MK |
1928 | int i915_gem_set_seqno(struct drm_device *dev, u32 seqno) |
1929 | { | |
1930 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1931 | int ret; | |
1932 | ||
1933 | if (seqno == 0) | |
1934 | return -EINVAL; | |
1935 | ||
1936 | /* HWS page needs to be set less than what we | |
1937 | * will inject to ring | |
1938 | */ | |
1939 | ret = i915_gem_init_seqno(dev, seqno - 1); | |
1940 | if (ret) | |
1941 | return ret; | |
1942 | ||
1943 | /* Carefully set the last_seqno value so that wrap | |
1944 | * detection still works | |
1945 | */ | |
1946 | dev_priv->next_seqno = seqno; | |
1947 | dev_priv->last_seqno = seqno - 1; | |
1948 | if (dev_priv->last_seqno == 0) | |
1949 | dev_priv->last_seqno--; | |
1950 | ||
1951 | return 0; | |
1952 | } | |
1953 | ||
9d773091 CW |
1954 | int |
1955 | i915_gem_get_seqno(struct drm_device *dev, u32 *seqno) | |
53d227f2 | 1956 | { |
9d773091 CW |
1957 | struct drm_i915_private *dev_priv = dev->dev_private; |
1958 | ||
1959 | /* reserve 0 for non-seqno */ | |
1960 | if (dev_priv->next_seqno == 0) { | |
fca26bb4 | 1961 | int ret = i915_gem_init_seqno(dev, 0); |
9d773091 CW |
1962 | if (ret) |
1963 | return ret; | |
53d227f2 | 1964 | |
9d773091 CW |
1965 | dev_priv->next_seqno = 1; |
1966 | } | |
53d227f2 | 1967 | |
f72b3435 | 1968 | *seqno = dev_priv->last_seqno = dev_priv->next_seqno++; |
9d773091 | 1969 | return 0; |
53d227f2 DV |
1970 | } |
1971 | ||
3cce469c | 1972 | int |
db53a302 | 1973 | i915_add_request(struct intel_ring_buffer *ring, |
f787a5f5 | 1974 | struct drm_file *file, |
acb868d3 | 1975 | u32 *out_seqno) |
673a394b | 1976 | { |
db53a302 | 1977 | drm_i915_private_t *dev_priv = ring->dev->dev_private; |
acb868d3 | 1978 | struct drm_i915_gem_request *request; |
a71d8d94 | 1979 | u32 request_ring_position; |
673a394b | 1980 | int was_empty; |
3cce469c CW |
1981 | int ret; |
1982 | ||
cc889e0f DV |
1983 | /* |
1984 | * Emit any outstanding flushes - execbuf can fail to emit the flush | |
1985 | * after having emitted the batchbuffer command. Hence we need to fix | |
1986 | * things up similar to emitting the lazy request. The difference here | |
1987 | * is that the flush _must_ happen before the next request, no matter | |
1988 | * what. | |
1989 | */ | |
a7b9761d CW |
1990 | ret = intel_ring_flush_all_caches(ring); |
1991 | if (ret) | |
1992 | return ret; | |
cc889e0f | 1993 | |
acb868d3 CW |
1994 | request = kmalloc(sizeof(*request), GFP_KERNEL); |
1995 | if (request == NULL) | |
1996 | return -ENOMEM; | |
cc889e0f | 1997 | |
673a394b | 1998 | |
a71d8d94 CW |
1999 | /* Record the position of the start of the request so that |
2000 | * should we detect the updated seqno part-way through the | |
2001 | * GPU processing the request, we never over-estimate the | |
2002 | * position of the head. | |
2003 | */ | |
2004 | request_ring_position = intel_ring_get_tail(ring); | |
2005 | ||
9d773091 | 2006 | ret = ring->add_request(ring); |
3bb73aba CW |
2007 | if (ret) { |
2008 | kfree(request); | |
2009 | return ret; | |
2010 | } | |
673a394b | 2011 | |
9d773091 | 2012 | request->seqno = intel_ring_get_seqno(ring); |
852835f3 | 2013 | request->ring = ring; |
a71d8d94 | 2014 | request->tail = request_ring_position; |
673a394b | 2015 | request->emitted_jiffies = jiffies; |
852835f3 ZN |
2016 | was_empty = list_empty(&ring->request_list); |
2017 | list_add_tail(&request->list, &ring->request_list); | |
3bb73aba | 2018 | request->file_priv = NULL; |
852835f3 | 2019 | |
db53a302 CW |
2020 | if (file) { |
2021 | struct drm_i915_file_private *file_priv = file->driver_priv; | |
2022 | ||
1c25595f | 2023 | spin_lock(&file_priv->mm.lock); |
f787a5f5 | 2024 | request->file_priv = file_priv; |
b962442e | 2025 | list_add_tail(&request->client_list, |
f787a5f5 | 2026 | &file_priv->mm.request_list); |
1c25595f | 2027 | spin_unlock(&file_priv->mm.lock); |
b962442e | 2028 | } |
673a394b | 2029 | |
9d773091 | 2030 | trace_i915_gem_request_add(ring, request->seqno); |
5391d0cf | 2031 | ring->outstanding_lazy_request = 0; |
db53a302 | 2032 | |
f65d9421 | 2033 | if (!dev_priv->mm.suspended) { |
3e0dc6b0 | 2034 | if (i915_enable_hangcheck) { |
99584db3 | 2035 | mod_timer(&dev_priv->gpu_error.hangcheck_timer, |
cecc21fe | 2036 | round_jiffies_up(jiffies + DRM_I915_HANGCHECK_JIFFIES)); |
3e0dc6b0 | 2037 | } |
f047e395 | 2038 | if (was_empty) { |
b3b079db | 2039 | queue_delayed_work(dev_priv->wq, |
bcb45086 CW |
2040 | &dev_priv->mm.retire_work, |
2041 | round_jiffies_up_relative(HZ)); | |
f047e395 CW |
2042 | intel_mark_busy(dev_priv->dev); |
2043 | } | |
f65d9421 | 2044 | } |
cc889e0f | 2045 | |
acb868d3 | 2046 | if (out_seqno) |
9d773091 | 2047 | *out_seqno = request->seqno; |
3cce469c | 2048 | return 0; |
673a394b EA |
2049 | } |
2050 | ||
f787a5f5 CW |
2051 | static inline void |
2052 | i915_gem_request_remove_from_client(struct drm_i915_gem_request *request) | |
673a394b | 2053 | { |
1c25595f | 2054 | struct drm_i915_file_private *file_priv = request->file_priv; |
673a394b | 2055 | |
1c25595f CW |
2056 | if (!file_priv) |
2057 | return; | |
1c5d22f7 | 2058 | |
1c25595f | 2059 | spin_lock(&file_priv->mm.lock); |
09bfa517 HRK |
2060 | if (request->file_priv) { |
2061 | list_del(&request->client_list); | |
2062 | request->file_priv = NULL; | |
2063 | } | |
1c25595f | 2064 | spin_unlock(&file_priv->mm.lock); |
673a394b | 2065 | } |
673a394b | 2066 | |
dfaae392 CW |
2067 | static void i915_gem_reset_ring_lists(struct drm_i915_private *dev_priv, |
2068 | struct intel_ring_buffer *ring) | |
9375e446 | 2069 | { |
dfaae392 CW |
2070 | while (!list_empty(&ring->request_list)) { |
2071 | struct drm_i915_gem_request *request; | |
673a394b | 2072 | |
dfaae392 CW |
2073 | request = list_first_entry(&ring->request_list, |
2074 | struct drm_i915_gem_request, | |
2075 | list); | |
de151cf6 | 2076 | |
dfaae392 | 2077 | list_del(&request->list); |
f787a5f5 | 2078 | i915_gem_request_remove_from_client(request); |
dfaae392 CW |
2079 | kfree(request); |
2080 | } | |
673a394b | 2081 | |
dfaae392 | 2082 | while (!list_empty(&ring->active_list)) { |
05394f39 | 2083 | struct drm_i915_gem_object *obj; |
9375e446 | 2084 | |
05394f39 CW |
2085 | obj = list_first_entry(&ring->active_list, |
2086 | struct drm_i915_gem_object, | |
2087 | ring_list); | |
9375e446 | 2088 | |
05394f39 | 2089 | i915_gem_object_move_to_inactive(obj); |
673a394b EA |
2090 | } |
2091 | } | |
2092 | ||
312817a3 CW |
2093 | static void i915_gem_reset_fences(struct drm_device *dev) |
2094 | { | |
2095 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2096 | int i; | |
2097 | ||
4b9de737 | 2098 | for (i = 0; i < dev_priv->num_fence_regs; i++) { |
312817a3 | 2099 | struct drm_i915_fence_reg *reg = &dev_priv->fence_regs[i]; |
7d2cb39c | 2100 | |
ada726c7 | 2101 | i915_gem_write_fence(dev, i, NULL); |
7d2cb39c | 2102 | |
ada726c7 CW |
2103 | if (reg->obj) |
2104 | i915_gem_object_fence_lost(reg->obj); | |
7d2cb39c | 2105 | |
ada726c7 CW |
2106 | reg->pin_count = 0; |
2107 | reg->obj = NULL; | |
2108 | INIT_LIST_HEAD(®->lru_list); | |
312817a3 | 2109 | } |
ada726c7 CW |
2110 | |
2111 | INIT_LIST_HEAD(&dev_priv->mm.fence_list); | |
312817a3 CW |
2112 | } |
2113 | ||
069efc1d | 2114 | void i915_gem_reset(struct drm_device *dev) |
673a394b | 2115 | { |
77f01230 | 2116 | struct drm_i915_private *dev_priv = dev->dev_private; |
05394f39 | 2117 | struct drm_i915_gem_object *obj; |
b4519513 | 2118 | struct intel_ring_buffer *ring; |
1ec14ad3 | 2119 | int i; |
673a394b | 2120 | |
b4519513 CW |
2121 | for_each_ring(ring, dev_priv, i) |
2122 | i915_gem_reset_ring_lists(dev_priv, ring); | |
dfaae392 | 2123 | |
dfaae392 CW |
2124 | /* Move everything out of the GPU domains to ensure we do any |
2125 | * necessary invalidation upon reuse. | |
2126 | */ | |
05394f39 | 2127 | list_for_each_entry(obj, |
77f01230 | 2128 | &dev_priv->mm.inactive_list, |
69dc4987 | 2129 | mm_list) |
77f01230 | 2130 | { |
05394f39 | 2131 | obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS; |
77f01230 | 2132 | } |
069efc1d CW |
2133 | |
2134 | /* The fence registers are invalidated so clear them out */ | |
312817a3 | 2135 | i915_gem_reset_fences(dev); |
673a394b EA |
2136 | } |
2137 | ||
2138 | /** | |
2139 | * This function clears the request list as sequence numbers are passed. | |
2140 | */ | |
a71d8d94 | 2141 | void |
db53a302 | 2142 | i915_gem_retire_requests_ring(struct intel_ring_buffer *ring) |
673a394b | 2143 | { |
673a394b EA |
2144 | uint32_t seqno; |
2145 | ||
db53a302 | 2146 | if (list_empty(&ring->request_list)) |
6c0594a3 KW |
2147 | return; |
2148 | ||
db53a302 | 2149 | WARN_ON(i915_verify_lists(ring->dev)); |
673a394b | 2150 | |
b2eadbc8 | 2151 | seqno = ring->get_seqno(ring, true); |
1ec14ad3 | 2152 | |
852835f3 | 2153 | while (!list_empty(&ring->request_list)) { |
673a394b | 2154 | struct drm_i915_gem_request *request; |
673a394b | 2155 | |
852835f3 | 2156 | request = list_first_entry(&ring->request_list, |
673a394b EA |
2157 | struct drm_i915_gem_request, |
2158 | list); | |
673a394b | 2159 | |
dfaae392 | 2160 | if (!i915_seqno_passed(seqno, request->seqno)) |
b84d5f0c CW |
2161 | break; |
2162 | ||
db53a302 | 2163 | trace_i915_gem_request_retire(ring, request->seqno); |
a71d8d94 CW |
2164 | /* We know the GPU must have read the request to have |
2165 | * sent us the seqno + interrupt, so use the position | |
2166 | * of tail of the request to update the last known position | |
2167 | * of the GPU head. | |
2168 | */ | |
2169 | ring->last_retired_head = request->tail; | |
b84d5f0c CW |
2170 | |
2171 | list_del(&request->list); | |
f787a5f5 | 2172 | i915_gem_request_remove_from_client(request); |
b84d5f0c CW |
2173 | kfree(request); |
2174 | } | |
673a394b | 2175 | |
b84d5f0c CW |
2176 | /* Move any buffers on the active list that are no longer referenced |
2177 | * by the ringbuffer to the flushing/inactive lists as appropriate. | |
2178 | */ | |
2179 | while (!list_empty(&ring->active_list)) { | |
05394f39 | 2180 | struct drm_i915_gem_object *obj; |
b84d5f0c | 2181 | |
0206e353 | 2182 | obj = list_first_entry(&ring->active_list, |
05394f39 CW |
2183 | struct drm_i915_gem_object, |
2184 | ring_list); | |
673a394b | 2185 | |
0201f1ec | 2186 | if (!i915_seqno_passed(seqno, obj->last_read_seqno)) |
673a394b | 2187 | break; |
b84d5f0c | 2188 | |
65ce3027 | 2189 | i915_gem_object_move_to_inactive(obj); |
673a394b | 2190 | } |
9d34e5db | 2191 | |
db53a302 CW |
2192 | if (unlikely(ring->trace_irq_seqno && |
2193 | i915_seqno_passed(seqno, ring->trace_irq_seqno))) { | |
1ec14ad3 | 2194 | ring->irq_put(ring); |
db53a302 | 2195 | ring->trace_irq_seqno = 0; |
9d34e5db | 2196 | } |
23bc5982 | 2197 | |
db53a302 | 2198 | WARN_ON(i915_verify_lists(ring->dev)); |
673a394b EA |
2199 | } |
2200 | ||
b09a1fec CW |
2201 | void |
2202 | i915_gem_retire_requests(struct drm_device *dev) | |
2203 | { | |
2204 | drm_i915_private_t *dev_priv = dev->dev_private; | |
b4519513 | 2205 | struct intel_ring_buffer *ring; |
1ec14ad3 | 2206 | int i; |
b09a1fec | 2207 | |
b4519513 CW |
2208 | for_each_ring(ring, dev_priv, i) |
2209 | i915_gem_retire_requests_ring(ring); | |
b09a1fec CW |
2210 | } |
2211 | ||
75ef9da2 | 2212 | static void |
673a394b EA |
2213 | i915_gem_retire_work_handler(struct work_struct *work) |
2214 | { | |
2215 | drm_i915_private_t *dev_priv; | |
2216 | struct drm_device *dev; | |
b4519513 | 2217 | struct intel_ring_buffer *ring; |
0a58705b CW |
2218 | bool idle; |
2219 | int i; | |
673a394b EA |
2220 | |
2221 | dev_priv = container_of(work, drm_i915_private_t, | |
2222 | mm.retire_work.work); | |
2223 | dev = dev_priv->dev; | |
2224 | ||
891b48cf CW |
2225 | /* Come back later if the device is busy... */ |
2226 | if (!mutex_trylock(&dev->struct_mutex)) { | |
bcb45086 CW |
2227 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, |
2228 | round_jiffies_up_relative(HZ)); | |
891b48cf CW |
2229 | return; |
2230 | } | |
673a394b | 2231 | |
b09a1fec | 2232 | i915_gem_retire_requests(dev); |
673a394b | 2233 | |
0a58705b CW |
2234 | /* Send a periodic flush down the ring so we don't hold onto GEM |
2235 | * objects indefinitely. | |
673a394b | 2236 | */ |
0a58705b | 2237 | idle = true; |
b4519513 | 2238 | for_each_ring(ring, dev_priv, i) { |
3bb73aba CW |
2239 | if (ring->gpu_caches_dirty) |
2240 | i915_add_request(ring, NULL, NULL); | |
0a58705b CW |
2241 | |
2242 | idle &= list_empty(&ring->request_list); | |
673a394b EA |
2243 | } |
2244 | ||
0a58705b | 2245 | if (!dev_priv->mm.suspended && !idle) |
bcb45086 CW |
2246 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, |
2247 | round_jiffies_up_relative(HZ)); | |
f047e395 CW |
2248 | if (idle) |
2249 | intel_mark_idle(dev); | |
0a58705b | 2250 | |
673a394b | 2251 | mutex_unlock(&dev->struct_mutex); |
673a394b EA |
2252 | } |
2253 | ||
30dfebf3 DV |
2254 | /** |
2255 | * Ensures that an object will eventually get non-busy by flushing any required | |
2256 | * write domains, emitting any outstanding lazy request and retiring and | |
2257 | * completed requests. | |
2258 | */ | |
2259 | static int | |
2260 | i915_gem_object_flush_active(struct drm_i915_gem_object *obj) | |
2261 | { | |
2262 | int ret; | |
2263 | ||
2264 | if (obj->active) { | |
0201f1ec | 2265 | ret = i915_gem_check_olr(obj->ring, obj->last_read_seqno); |
30dfebf3 DV |
2266 | if (ret) |
2267 | return ret; | |
2268 | ||
30dfebf3 DV |
2269 | i915_gem_retire_requests_ring(obj->ring); |
2270 | } | |
2271 | ||
2272 | return 0; | |
2273 | } | |
2274 | ||
23ba4fd0 BW |
2275 | /** |
2276 | * i915_gem_wait_ioctl - implements DRM_IOCTL_I915_GEM_WAIT | |
2277 | * @DRM_IOCTL_ARGS: standard ioctl arguments | |
2278 | * | |
2279 | * Returns 0 if successful, else an error is returned with the remaining time in | |
2280 | * the timeout parameter. | |
2281 | * -ETIME: object is still busy after timeout | |
2282 | * -ERESTARTSYS: signal interrupted the wait | |
2283 | * -ENONENT: object doesn't exist | |
2284 | * Also possible, but rare: | |
2285 | * -EAGAIN: GPU wedged | |
2286 | * -ENOMEM: damn | |
2287 | * -ENODEV: Internal IRQ fail | |
2288 | * -E?: The add request failed | |
2289 | * | |
2290 | * The wait ioctl with a timeout of 0 reimplements the busy ioctl. With any | |
2291 | * non-zero timeout parameter the wait ioctl will wait for the given number of | |
2292 | * nanoseconds on an object becoming unbusy. Since the wait itself does so | |
2293 | * without holding struct_mutex the object may become re-busied before this | |
2294 | * function completes. A similar but shorter * race condition exists in the busy | |
2295 | * ioctl | |
2296 | */ | |
2297 | int | |
2298 | i915_gem_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *file) | |
2299 | { | |
2300 | struct drm_i915_gem_wait *args = data; | |
2301 | struct drm_i915_gem_object *obj; | |
2302 | struct intel_ring_buffer *ring = NULL; | |
eac1f14f | 2303 | struct timespec timeout_stack, *timeout = NULL; |
23ba4fd0 BW |
2304 | u32 seqno = 0; |
2305 | int ret = 0; | |
2306 | ||
eac1f14f BW |
2307 | if (args->timeout_ns >= 0) { |
2308 | timeout_stack = ns_to_timespec(args->timeout_ns); | |
2309 | timeout = &timeout_stack; | |
2310 | } | |
23ba4fd0 BW |
2311 | |
2312 | ret = i915_mutex_lock_interruptible(dev); | |
2313 | if (ret) | |
2314 | return ret; | |
2315 | ||
2316 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->bo_handle)); | |
2317 | if (&obj->base == NULL) { | |
2318 | mutex_unlock(&dev->struct_mutex); | |
2319 | return -ENOENT; | |
2320 | } | |
2321 | ||
30dfebf3 DV |
2322 | /* Need to make sure the object gets inactive eventually. */ |
2323 | ret = i915_gem_object_flush_active(obj); | |
23ba4fd0 BW |
2324 | if (ret) |
2325 | goto out; | |
2326 | ||
2327 | if (obj->active) { | |
0201f1ec | 2328 | seqno = obj->last_read_seqno; |
23ba4fd0 BW |
2329 | ring = obj->ring; |
2330 | } | |
2331 | ||
2332 | if (seqno == 0) | |
2333 | goto out; | |
2334 | ||
23ba4fd0 BW |
2335 | /* Do this after OLR check to make sure we make forward progress polling |
2336 | * on this IOCTL with a 0 timeout (like busy ioctl) | |
2337 | */ | |
2338 | if (!args->timeout_ns) { | |
2339 | ret = -ETIME; | |
2340 | goto out; | |
2341 | } | |
2342 | ||
2343 | drm_gem_object_unreference(&obj->base); | |
2344 | mutex_unlock(&dev->struct_mutex); | |
2345 | ||
eac1f14f BW |
2346 | ret = __wait_seqno(ring, seqno, true, timeout); |
2347 | if (timeout) { | |
2348 | WARN_ON(!timespec_valid(timeout)); | |
2349 | args->timeout_ns = timespec_to_ns(timeout); | |
2350 | } | |
23ba4fd0 BW |
2351 | return ret; |
2352 | ||
2353 | out: | |
2354 | drm_gem_object_unreference(&obj->base); | |
2355 | mutex_unlock(&dev->struct_mutex); | |
2356 | return ret; | |
2357 | } | |
2358 | ||
5816d648 BW |
2359 | /** |
2360 | * i915_gem_object_sync - sync an object to a ring. | |
2361 | * | |
2362 | * @obj: object which may be in use on another ring. | |
2363 | * @to: ring we wish to use the object on. May be NULL. | |
2364 | * | |
2365 | * This code is meant to abstract object synchronization with the GPU. | |
2366 | * Calling with NULL implies synchronizing the object with the CPU | |
2367 | * rather than a particular GPU ring. | |
2368 | * | |
2369 | * Returns 0 if successful, else propagates up the lower layer error. | |
2370 | */ | |
2911a35b BW |
2371 | int |
2372 | i915_gem_object_sync(struct drm_i915_gem_object *obj, | |
2373 | struct intel_ring_buffer *to) | |
2374 | { | |
2375 | struct intel_ring_buffer *from = obj->ring; | |
2376 | u32 seqno; | |
2377 | int ret, idx; | |
2378 | ||
2379 | if (from == NULL || to == from) | |
2380 | return 0; | |
2381 | ||
5816d648 | 2382 | if (to == NULL || !i915_semaphore_is_enabled(obj->base.dev)) |
0201f1ec | 2383 | return i915_gem_object_wait_rendering(obj, false); |
2911a35b BW |
2384 | |
2385 | idx = intel_ring_sync_index(from, to); | |
2386 | ||
0201f1ec | 2387 | seqno = obj->last_read_seqno; |
2911a35b BW |
2388 | if (seqno <= from->sync_seqno[idx]) |
2389 | return 0; | |
2390 | ||
b4aca010 BW |
2391 | ret = i915_gem_check_olr(obj->ring, seqno); |
2392 | if (ret) | |
2393 | return ret; | |
2911a35b | 2394 | |
1500f7ea | 2395 | ret = to->sync_to(to, from, seqno); |
e3a5a225 | 2396 | if (!ret) |
7b01e260 MK |
2397 | /* We use last_read_seqno because sync_to() |
2398 | * might have just caused seqno wrap under | |
2399 | * the radar. | |
2400 | */ | |
2401 | from->sync_seqno[idx] = obj->last_read_seqno; | |
2911a35b | 2402 | |
e3a5a225 | 2403 | return ret; |
2911a35b BW |
2404 | } |
2405 | ||
b5ffc9bc CW |
2406 | static void i915_gem_object_finish_gtt(struct drm_i915_gem_object *obj) |
2407 | { | |
2408 | u32 old_write_domain, old_read_domains; | |
2409 | ||
b5ffc9bc CW |
2410 | /* Act a barrier for all accesses through the GTT */ |
2411 | mb(); | |
2412 | ||
2413 | /* Force a pagefault for domain tracking on next user access */ | |
2414 | i915_gem_release_mmap(obj); | |
2415 | ||
b97c3d9c KP |
2416 | if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0) |
2417 | return; | |
2418 | ||
b5ffc9bc CW |
2419 | old_read_domains = obj->base.read_domains; |
2420 | old_write_domain = obj->base.write_domain; | |
2421 | ||
2422 | obj->base.read_domains &= ~I915_GEM_DOMAIN_GTT; | |
2423 | obj->base.write_domain &= ~I915_GEM_DOMAIN_GTT; | |
2424 | ||
2425 | trace_i915_gem_object_change_domain(obj, | |
2426 | old_read_domains, | |
2427 | old_write_domain); | |
2428 | } | |
2429 | ||
673a394b EA |
2430 | /** |
2431 | * Unbinds an object from the GTT aperture. | |
2432 | */ | |
0f973f27 | 2433 | int |
05394f39 | 2434 | i915_gem_object_unbind(struct drm_i915_gem_object *obj) |
673a394b | 2435 | { |
7bddb01f | 2436 | drm_i915_private_t *dev_priv = obj->base.dev->dev_private; |
43e28f09 | 2437 | int ret; |
673a394b | 2438 | |
05394f39 | 2439 | if (obj->gtt_space == NULL) |
673a394b EA |
2440 | return 0; |
2441 | ||
31d8d651 CW |
2442 | if (obj->pin_count) |
2443 | return -EBUSY; | |
673a394b | 2444 | |
c4670ad0 CW |
2445 | BUG_ON(obj->pages == NULL); |
2446 | ||
a8198eea | 2447 | ret = i915_gem_object_finish_gpu(obj); |
1488fc08 | 2448 | if (ret) |
a8198eea CW |
2449 | return ret; |
2450 | /* Continue on if we fail due to EIO, the GPU is hung so we | |
2451 | * should be safe and we need to cleanup or else we might | |
2452 | * cause memory corruption through use-after-free. | |
2453 | */ | |
2454 | ||
b5ffc9bc | 2455 | i915_gem_object_finish_gtt(obj); |
5323fd04 | 2456 | |
96b47b65 | 2457 | /* release the fence reg _after_ flushing */ |
d9e86c0e | 2458 | ret = i915_gem_object_put_fence(obj); |
1488fc08 | 2459 | if (ret) |
d9e86c0e | 2460 | return ret; |
96b47b65 | 2461 | |
db53a302 CW |
2462 | trace_i915_gem_object_unbind(obj); |
2463 | ||
74898d7e DV |
2464 | if (obj->has_global_gtt_mapping) |
2465 | i915_gem_gtt_unbind_object(obj); | |
7bddb01f DV |
2466 | if (obj->has_aliasing_ppgtt_mapping) { |
2467 | i915_ppgtt_unbind_object(dev_priv->mm.aliasing_ppgtt, obj); | |
2468 | obj->has_aliasing_ppgtt_mapping = 0; | |
2469 | } | |
74163907 | 2470 | i915_gem_gtt_finish_object(obj); |
7bddb01f | 2471 | |
6c085a72 CW |
2472 | list_del(&obj->mm_list); |
2473 | list_move_tail(&obj->gtt_list, &dev_priv->mm.unbound_list); | |
75e9e915 | 2474 | /* Avoid an unnecessary call to unbind on rebind. */ |
05394f39 | 2475 | obj->map_and_fenceable = true; |
673a394b | 2476 | |
05394f39 CW |
2477 | drm_mm_put_block(obj->gtt_space); |
2478 | obj->gtt_space = NULL; | |
2479 | obj->gtt_offset = 0; | |
673a394b | 2480 | |
88241785 | 2481 | return 0; |
54cf91dc CW |
2482 | } |
2483 | ||
b2da9fe5 | 2484 | int i915_gpu_idle(struct drm_device *dev) |
4df2faf4 DV |
2485 | { |
2486 | drm_i915_private_t *dev_priv = dev->dev_private; | |
b4519513 | 2487 | struct intel_ring_buffer *ring; |
1ec14ad3 | 2488 | int ret, i; |
4df2faf4 | 2489 | |
4df2faf4 | 2490 | /* Flush everything onto the inactive list. */ |
b4519513 | 2491 | for_each_ring(ring, dev_priv, i) { |
b6c7488d BW |
2492 | ret = i915_switch_context(ring, NULL, DEFAULT_CONTEXT_ID); |
2493 | if (ret) | |
2494 | return ret; | |
2495 | ||
3e960501 | 2496 | ret = intel_ring_idle(ring); |
1ec14ad3 CW |
2497 | if (ret) |
2498 | return ret; | |
2499 | } | |
4df2faf4 | 2500 | |
8a1a49f9 | 2501 | return 0; |
4df2faf4 DV |
2502 | } |
2503 | ||
9ce079e4 CW |
2504 | static void i965_write_fence_reg(struct drm_device *dev, int reg, |
2505 | struct drm_i915_gem_object *obj) | |
de151cf6 | 2506 | { |
de151cf6 | 2507 | drm_i915_private_t *dev_priv = dev->dev_private; |
56c844e5 ID |
2508 | int fence_reg; |
2509 | int fence_pitch_shift; | |
de151cf6 JB |
2510 | uint64_t val; |
2511 | ||
56c844e5 ID |
2512 | if (INTEL_INFO(dev)->gen >= 6) { |
2513 | fence_reg = FENCE_REG_SANDYBRIDGE_0; | |
2514 | fence_pitch_shift = SANDYBRIDGE_FENCE_PITCH_SHIFT; | |
2515 | } else { | |
2516 | fence_reg = FENCE_REG_965_0; | |
2517 | fence_pitch_shift = I965_FENCE_PITCH_SHIFT; | |
2518 | } | |
2519 | ||
9ce079e4 CW |
2520 | if (obj) { |
2521 | u32 size = obj->gtt_space->size; | |
de151cf6 | 2522 | |
9ce079e4 CW |
2523 | val = (uint64_t)((obj->gtt_offset + size - 4096) & |
2524 | 0xfffff000) << 32; | |
2525 | val |= obj->gtt_offset & 0xfffff000; | |
56c844e5 | 2526 | val |= (uint64_t)((obj->stride / 128) - 1) << fence_pitch_shift; |
9ce079e4 CW |
2527 | if (obj->tiling_mode == I915_TILING_Y) |
2528 | val |= 1 << I965_FENCE_TILING_Y_SHIFT; | |
2529 | val |= I965_FENCE_REG_VALID; | |
2530 | } else | |
2531 | val = 0; | |
c6642782 | 2532 | |
56c844e5 ID |
2533 | fence_reg += reg * 8; |
2534 | I915_WRITE64(fence_reg, val); | |
2535 | POSTING_READ(fence_reg); | |
de151cf6 JB |
2536 | } |
2537 | ||
9ce079e4 CW |
2538 | static void i915_write_fence_reg(struct drm_device *dev, int reg, |
2539 | struct drm_i915_gem_object *obj) | |
de151cf6 | 2540 | { |
de151cf6 | 2541 | drm_i915_private_t *dev_priv = dev->dev_private; |
9ce079e4 | 2542 | u32 val; |
de151cf6 | 2543 | |
9ce079e4 CW |
2544 | if (obj) { |
2545 | u32 size = obj->gtt_space->size; | |
2546 | int pitch_val; | |
2547 | int tile_width; | |
c6642782 | 2548 | |
9ce079e4 CW |
2549 | WARN((obj->gtt_offset & ~I915_FENCE_START_MASK) || |
2550 | (size & -size) != size || | |
2551 | (obj->gtt_offset & (size - 1)), | |
2552 | "object 0x%08x [fenceable? %d] not 1M or pot-size (0x%08x) aligned\n", | |
2553 | obj->gtt_offset, obj->map_and_fenceable, size); | |
c6642782 | 2554 | |
9ce079e4 CW |
2555 | if (obj->tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev)) |
2556 | tile_width = 128; | |
2557 | else | |
2558 | tile_width = 512; | |
2559 | ||
2560 | /* Note: pitch better be a power of two tile widths */ | |
2561 | pitch_val = obj->stride / tile_width; | |
2562 | pitch_val = ffs(pitch_val) - 1; | |
2563 | ||
2564 | val = obj->gtt_offset; | |
2565 | if (obj->tiling_mode == I915_TILING_Y) | |
2566 | val |= 1 << I830_FENCE_TILING_Y_SHIFT; | |
2567 | val |= I915_FENCE_SIZE_BITS(size); | |
2568 | val |= pitch_val << I830_FENCE_PITCH_SHIFT; | |
2569 | val |= I830_FENCE_REG_VALID; | |
2570 | } else | |
2571 | val = 0; | |
2572 | ||
2573 | if (reg < 8) | |
2574 | reg = FENCE_REG_830_0 + reg * 4; | |
2575 | else | |
2576 | reg = FENCE_REG_945_8 + (reg - 8) * 4; | |
2577 | ||
2578 | I915_WRITE(reg, val); | |
2579 | POSTING_READ(reg); | |
de151cf6 JB |
2580 | } |
2581 | ||
9ce079e4 CW |
2582 | static void i830_write_fence_reg(struct drm_device *dev, int reg, |
2583 | struct drm_i915_gem_object *obj) | |
de151cf6 | 2584 | { |
de151cf6 | 2585 | drm_i915_private_t *dev_priv = dev->dev_private; |
de151cf6 | 2586 | uint32_t val; |
de151cf6 | 2587 | |
9ce079e4 CW |
2588 | if (obj) { |
2589 | u32 size = obj->gtt_space->size; | |
2590 | uint32_t pitch_val; | |
de151cf6 | 2591 | |
9ce079e4 CW |
2592 | WARN((obj->gtt_offset & ~I830_FENCE_START_MASK) || |
2593 | (size & -size) != size || | |
2594 | (obj->gtt_offset & (size - 1)), | |
2595 | "object 0x%08x not 512K or pot-size 0x%08x aligned\n", | |
2596 | obj->gtt_offset, size); | |
e76a16de | 2597 | |
9ce079e4 CW |
2598 | pitch_val = obj->stride / 128; |
2599 | pitch_val = ffs(pitch_val) - 1; | |
de151cf6 | 2600 | |
9ce079e4 CW |
2601 | val = obj->gtt_offset; |
2602 | if (obj->tiling_mode == I915_TILING_Y) | |
2603 | val |= 1 << I830_FENCE_TILING_Y_SHIFT; | |
2604 | val |= I830_FENCE_SIZE_BITS(size); | |
2605 | val |= pitch_val << I830_FENCE_PITCH_SHIFT; | |
2606 | val |= I830_FENCE_REG_VALID; | |
2607 | } else | |
2608 | val = 0; | |
c6642782 | 2609 | |
9ce079e4 CW |
2610 | I915_WRITE(FENCE_REG_830_0 + reg * 4, val); |
2611 | POSTING_READ(FENCE_REG_830_0 + reg * 4); | |
2612 | } | |
2613 | ||
d0a57789 CW |
2614 | inline static bool i915_gem_object_needs_mb(struct drm_i915_gem_object *obj) |
2615 | { | |
2616 | return obj && obj->base.read_domains & I915_GEM_DOMAIN_GTT; | |
2617 | } | |
2618 | ||
9ce079e4 CW |
2619 | static void i915_gem_write_fence(struct drm_device *dev, int reg, |
2620 | struct drm_i915_gem_object *obj) | |
2621 | { | |
d0a57789 CW |
2622 | struct drm_i915_private *dev_priv = dev->dev_private; |
2623 | ||
2624 | /* Ensure that all CPU reads are completed before installing a fence | |
2625 | * and all writes before removing the fence. | |
2626 | */ | |
2627 | if (i915_gem_object_needs_mb(dev_priv->fence_regs[reg].obj)) | |
2628 | mb(); | |
2629 | ||
9ce079e4 CW |
2630 | switch (INTEL_INFO(dev)->gen) { |
2631 | case 7: | |
56c844e5 | 2632 | case 6: |
9ce079e4 CW |
2633 | case 5: |
2634 | case 4: i965_write_fence_reg(dev, reg, obj); break; | |
2635 | case 3: i915_write_fence_reg(dev, reg, obj); break; | |
2636 | case 2: i830_write_fence_reg(dev, reg, obj); break; | |
7dbf9d6e | 2637 | default: BUG(); |
9ce079e4 | 2638 | } |
d0a57789 CW |
2639 | |
2640 | /* And similarly be paranoid that no direct access to this region | |
2641 | * is reordered to before the fence is installed. | |
2642 | */ | |
2643 | if (i915_gem_object_needs_mb(obj)) | |
2644 | mb(); | |
de151cf6 JB |
2645 | } |
2646 | ||
61050808 CW |
2647 | static inline int fence_number(struct drm_i915_private *dev_priv, |
2648 | struct drm_i915_fence_reg *fence) | |
2649 | { | |
2650 | return fence - dev_priv->fence_regs; | |
2651 | } | |
2652 | ||
2653 | static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj, | |
2654 | struct drm_i915_fence_reg *fence, | |
2655 | bool enable) | |
2656 | { | |
2657 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; | |
2658 | int reg = fence_number(dev_priv, fence); | |
2659 | ||
2660 | i915_gem_write_fence(obj->base.dev, reg, enable ? obj : NULL); | |
2661 | ||
2662 | if (enable) { | |
2663 | obj->fence_reg = reg; | |
2664 | fence->obj = obj; | |
2665 | list_move_tail(&fence->lru_list, &dev_priv->mm.fence_list); | |
2666 | } else { | |
2667 | obj->fence_reg = I915_FENCE_REG_NONE; | |
2668 | fence->obj = NULL; | |
2669 | list_del_init(&fence->lru_list); | |
2670 | } | |
2671 | } | |
2672 | ||
d9e86c0e | 2673 | static int |
d0a57789 | 2674 | i915_gem_object_wait_fence(struct drm_i915_gem_object *obj) |
d9e86c0e | 2675 | { |
1c293ea3 | 2676 | if (obj->last_fenced_seqno) { |
86d5bc37 | 2677 | int ret = i915_wait_seqno(obj->ring, obj->last_fenced_seqno); |
18991845 CW |
2678 | if (ret) |
2679 | return ret; | |
d9e86c0e CW |
2680 | |
2681 | obj->last_fenced_seqno = 0; | |
d9e86c0e CW |
2682 | } |
2683 | ||
86d5bc37 | 2684 | obj->fenced_gpu_access = false; |
d9e86c0e CW |
2685 | return 0; |
2686 | } | |
2687 | ||
2688 | int | |
2689 | i915_gem_object_put_fence(struct drm_i915_gem_object *obj) | |
2690 | { | |
61050808 | 2691 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
d9e86c0e CW |
2692 | int ret; |
2693 | ||
d0a57789 | 2694 | ret = i915_gem_object_wait_fence(obj); |
d9e86c0e CW |
2695 | if (ret) |
2696 | return ret; | |
2697 | ||
61050808 CW |
2698 | if (obj->fence_reg == I915_FENCE_REG_NONE) |
2699 | return 0; | |
d9e86c0e | 2700 | |
61050808 CW |
2701 | i915_gem_object_update_fence(obj, |
2702 | &dev_priv->fence_regs[obj->fence_reg], | |
2703 | false); | |
2704 | i915_gem_object_fence_lost(obj); | |
d9e86c0e CW |
2705 | |
2706 | return 0; | |
2707 | } | |
2708 | ||
2709 | static struct drm_i915_fence_reg * | |
a360bb1a | 2710 | i915_find_fence_reg(struct drm_device *dev) |
ae3db24a | 2711 | { |
ae3db24a | 2712 | struct drm_i915_private *dev_priv = dev->dev_private; |
8fe301ad | 2713 | struct drm_i915_fence_reg *reg, *avail; |
d9e86c0e | 2714 | int i; |
ae3db24a DV |
2715 | |
2716 | /* First try to find a free reg */ | |
d9e86c0e | 2717 | avail = NULL; |
ae3db24a DV |
2718 | for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) { |
2719 | reg = &dev_priv->fence_regs[i]; | |
2720 | if (!reg->obj) | |
d9e86c0e | 2721 | return reg; |
ae3db24a | 2722 | |
1690e1eb | 2723 | if (!reg->pin_count) |
d9e86c0e | 2724 | avail = reg; |
ae3db24a DV |
2725 | } |
2726 | ||
d9e86c0e CW |
2727 | if (avail == NULL) |
2728 | return NULL; | |
ae3db24a DV |
2729 | |
2730 | /* None available, try to steal one or wait for a user to finish */ | |
d9e86c0e | 2731 | list_for_each_entry(reg, &dev_priv->mm.fence_list, lru_list) { |
1690e1eb | 2732 | if (reg->pin_count) |
ae3db24a DV |
2733 | continue; |
2734 | ||
8fe301ad | 2735 | return reg; |
ae3db24a DV |
2736 | } |
2737 | ||
8fe301ad | 2738 | return NULL; |
ae3db24a DV |
2739 | } |
2740 | ||
de151cf6 | 2741 | /** |
9a5a53b3 | 2742 | * i915_gem_object_get_fence - set up fencing for an object |
de151cf6 JB |
2743 | * @obj: object to map through a fence reg |
2744 | * | |
2745 | * When mapping objects through the GTT, userspace wants to be able to write | |
2746 | * to them without having to worry about swizzling if the object is tiled. | |
de151cf6 JB |
2747 | * This function walks the fence regs looking for a free one for @obj, |
2748 | * stealing one if it can't find any. | |
2749 | * | |
2750 | * It then sets up the reg based on the object's properties: address, pitch | |
2751 | * and tiling format. | |
9a5a53b3 CW |
2752 | * |
2753 | * For an untiled surface, this removes any existing fence. | |
de151cf6 | 2754 | */ |
8c4b8c3f | 2755 | int |
06d98131 | 2756 | i915_gem_object_get_fence(struct drm_i915_gem_object *obj) |
de151cf6 | 2757 | { |
05394f39 | 2758 | struct drm_device *dev = obj->base.dev; |
79e53945 | 2759 | struct drm_i915_private *dev_priv = dev->dev_private; |
14415745 | 2760 | bool enable = obj->tiling_mode != I915_TILING_NONE; |
d9e86c0e | 2761 | struct drm_i915_fence_reg *reg; |
ae3db24a | 2762 | int ret; |
de151cf6 | 2763 | |
14415745 CW |
2764 | /* Have we updated the tiling parameters upon the object and so |
2765 | * will need to serialise the write to the associated fence register? | |
2766 | */ | |
5d82e3e6 | 2767 | if (obj->fence_dirty) { |
d0a57789 | 2768 | ret = i915_gem_object_wait_fence(obj); |
14415745 CW |
2769 | if (ret) |
2770 | return ret; | |
2771 | } | |
9a5a53b3 | 2772 | |
d9e86c0e | 2773 | /* Just update our place in the LRU if our fence is getting reused. */ |
05394f39 CW |
2774 | if (obj->fence_reg != I915_FENCE_REG_NONE) { |
2775 | reg = &dev_priv->fence_regs[obj->fence_reg]; | |
5d82e3e6 | 2776 | if (!obj->fence_dirty) { |
14415745 CW |
2777 | list_move_tail(®->lru_list, |
2778 | &dev_priv->mm.fence_list); | |
2779 | return 0; | |
2780 | } | |
2781 | } else if (enable) { | |
2782 | reg = i915_find_fence_reg(dev); | |
2783 | if (reg == NULL) | |
2784 | return -EDEADLK; | |
d9e86c0e | 2785 | |
14415745 CW |
2786 | if (reg->obj) { |
2787 | struct drm_i915_gem_object *old = reg->obj; | |
2788 | ||
d0a57789 | 2789 | ret = i915_gem_object_wait_fence(old); |
29c5a587 CW |
2790 | if (ret) |
2791 | return ret; | |
2792 | ||
14415745 | 2793 | i915_gem_object_fence_lost(old); |
29c5a587 | 2794 | } |
14415745 | 2795 | } else |
a09ba7fa | 2796 | return 0; |
a09ba7fa | 2797 | |
14415745 | 2798 | i915_gem_object_update_fence(obj, reg, enable); |
5d82e3e6 | 2799 | obj->fence_dirty = false; |
14415745 | 2800 | |
9ce079e4 | 2801 | return 0; |
de151cf6 JB |
2802 | } |
2803 | ||
42d6ab48 CW |
2804 | static bool i915_gem_valid_gtt_space(struct drm_device *dev, |
2805 | struct drm_mm_node *gtt_space, | |
2806 | unsigned long cache_level) | |
2807 | { | |
2808 | struct drm_mm_node *other; | |
2809 | ||
2810 | /* On non-LLC machines we have to be careful when putting differing | |
2811 | * types of snoopable memory together to avoid the prefetcher | |
4239ca77 | 2812 | * crossing memory domains and dying. |
42d6ab48 CW |
2813 | */ |
2814 | if (HAS_LLC(dev)) | |
2815 | return true; | |
2816 | ||
2817 | if (gtt_space == NULL) | |
2818 | return true; | |
2819 | ||
2820 | if (list_empty(>t_space->node_list)) | |
2821 | return true; | |
2822 | ||
2823 | other = list_entry(gtt_space->node_list.prev, struct drm_mm_node, node_list); | |
2824 | if (other->allocated && !other->hole_follows && other->color != cache_level) | |
2825 | return false; | |
2826 | ||
2827 | other = list_entry(gtt_space->node_list.next, struct drm_mm_node, node_list); | |
2828 | if (other->allocated && !gtt_space->hole_follows && other->color != cache_level) | |
2829 | return false; | |
2830 | ||
2831 | return true; | |
2832 | } | |
2833 | ||
2834 | static void i915_gem_verify_gtt(struct drm_device *dev) | |
2835 | { | |
2836 | #if WATCH_GTT | |
2837 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2838 | struct drm_i915_gem_object *obj; | |
2839 | int err = 0; | |
2840 | ||
2841 | list_for_each_entry(obj, &dev_priv->mm.gtt_list, gtt_list) { | |
2842 | if (obj->gtt_space == NULL) { | |
2843 | printk(KERN_ERR "object found on GTT list with no space reserved\n"); | |
2844 | err++; | |
2845 | continue; | |
2846 | } | |
2847 | ||
2848 | if (obj->cache_level != obj->gtt_space->color) { | |
2849 | printk(KERN_ERR "object reserved space [%08lx, %08lx] with wrong color, cache_level=%x, color=%lx\n", | |
2850 | obj->gtt_space->start, | |
2851 | obj->gtt_space->start + obj->gtt_space->size, | |
2852 | obj->cache_level, | |
2853 | obj->gtt_space->color); | |
2854 | err++; | |
2855 | continue; | |
2856 | } | |
2857 | ||
2858 | if (!i915_gem_valid_gtt_space(dev, | |
2859 | obj->gtt_space, | |
2860 | obj->cache_level)) { | |
2861 | printk(KERN_ERR "invalid GTT space found at [%08lx, %08lx] - color=%x\n", | |
2862 | obj->gtt_space->start, | |
2863 | obj->gtt_space->start + obj->gtt_space->size, | |
2864 | obj->cache_level); | |
2865 | err++; | |
2866 | continue; | |
2867 | } | |
2868 | } | |
2869 | ||
2870 | WARN_ON(err); | |
2871 | #endif | |
2872 | } | |
2873 | ||
673a394b EA |
2874 | /** |
2875 | * Finds free space in the GTT aperture and binds the object there. | |
2876 | */ | |
2877 | static int | |
05394f39 | 2878 | i915_gem_object_bind_to_gtt(struct drm_i915_gem_object *obj, |
920afa77 | 2879 | unsigned alignment, |
86a1ee26 CW |
2880 | bool map_and_fenceable, |
2881 | bool nonblocking) | |
673a394b | 2882 | { |
05394f39 | 2883 | struct drm_device *dev = obj->base.dev; |
673a394b | 2884 | drm_i915_private_t *dev_priv = dev->dev_private; |
dc9dd7a2 | 2885 | struct drm_mm_node *node; |
5e783301 | 2886 | u32 size, fence_size, fence_alignment, unfenced_alignment; |
75e9e915 | 2887 | bool mappable, fenceable; |
07f73f69 | 2888 | int ret; |
673a394b | 2889 | |
e28f8711 CW |
2890 | fence_size = i915_gem_get_gtt_size(dev, |
2891 | obj->base.size, | |
2892 | obj->tiling_mode); | |
2893 | fence_alignment = i915_gem_get_gtt_alignment(dev, | |
2894 | obj->base.size, | |
d865110c | 2895 | obj->tiling_mode, true); |
e28f8711 | 2896 | unfenced_alignment = |
d865110c | 2897 | i915_gem_get_gtt_alignment(dev, |
e28f8711 | 2898 | obj->base.size, |
d865110c | 2899 | obj->tiling_mode, false); |
a00b10c3 | 2900 | |
673a394b | 2901 | if (alignment == 0) |
5e783301 DV |
2902 | alignment = map_and_fenceable ? fence_alignment : |
2903 | unfenced_alignment; | |
75e9e915 | 2904 | if (map_and_fenceable && alignment & (fence_alignment - 1)) { |
673a394b EA |
2905 | DRM_ERROR("Invalid object alignment requested %u\n", alignment); |
2906 | return -EINVAL; | |
2907 | } | |
2908 | ||
05394f39 | 2909 | size = map_and_fenceable ? fence_size : obj->base.size; |
a00b10c3 | 2910 | |
654fc607 CW |
2911 | /* If the object is bigger than the entire aperture, reject it early |
2912 | * before evicting everything in a vain attempt to find space. | |
2913 | */ | |
05394f39 | 2914 | if (obj->base.size > |
5d4545ae | 2915 | (map_and_fenceable ? dev_priv->gtt.mappable_end : dev_priv->gtt.total)) { |
654fc607 CW |
2916 | DRM_ERROR("Attempting to bind an object larger than the aperture\n"); |
2917 | return -E2BIG; | |
2918 | } | |
2919 | ||
37e680a1 | 2920 | ret = i915_gem_object_get_pages(obj); |
6c085a72 CW |
2921 | if (ret) |
2922 | return ret; | |
2923 | ||
fbdda6fb CW |
2924 | i915_gem_object_pin_pages(obj); |
2925 | ||
dc9dd7a2 CW |
2926 | node = kzalloc(sizeof(*node), GFP_KERNEL); |
2927 | if (node == NULL) { | |
2928 | i915_gem_object_unpin_pages(obj); | |
2929 | return -ENOMEM; | |
2930 | } | |
2931 | ||
673a394b | 2932 | search_free: |
75e9e915 | 2933 | if (map_and_fenceable) |
dc9dd7a2 CW |
2934 | ret = drm_mm_insert_node_in_range_generic(&dev_priv->mm.gtt_space, node, |
2935 | size, alignment, obj->cache_level, | |
5d4545ae | 2936 | 0, dev_priv->gtt.mappable_end); |
920afa77 | 2937 | else |
dc9dd7a2 CW |
2938 | ret = drm_mm_insert_node_generic(&dev_priv->mm.gtt_space, node, |
2939 | size, alignment, obj->cache_level); | |
2940 | if (ret) { | |
75e9e915 | 2941 | ret = i915_gem_evict_something(dev, size, alignment, |
42d6ab48 | 2942 | obj->cache_level, |
86a1ee26 CW |
2943 | map_and_fenceable, |
2944 | nonblocking); | |
dc9dd7a2 CW |
2945 | if (ret == 0) |
2946 | goto search_free; | |
9731129c | 2947 | |
dc9dd7a2 CW |
2948 | i915_gem_object_unpin_pages(obj); |
2949 | kfree(node); | |
2950 | return ret; | |
673a394b | 2951 | } |
dc9dd7a2 | 2952 | if (WARN_ON(!i915_gem_valid_gtt_space(dev, node, obj->cache_level))) { |
fbdda6fb | 2953 | i915_gem_object_unpin_pages(obj); |
dc9dd7a2 | 2954 | drm_mm_put_block(node); |
42d6ab48 | 2955 | return -EINVAL; |
673a394b EA |
2956 | } |
2957 | ||
74163907 | 2958 | ret = i915_gem_gtt_prepare_object(obj); |
7c2e6fdf | 2959 | if (ret) { |
fbdda6fb | 2960 | i915_gem_object_unpin_pages(obj); |
dc9dd7a2 | 2961 | drm_mm_put_block(node); |
6c085a72 | 2962 | return ret; |
673a394b | 2963 | } |
673a394b | 2964 | |
6c085a72 | 2965 | list_move_tail(&obj->gtt_list, &dev_priv->mm.bound_list); |
05394f39 | 2966 | list_add_tail(&obj->mm_list, &dev_priv->mm.inactive_list); |
bf1a1092 | 2967 | |
dc9dd7a2 CW |
2968 | obj->gtt_space = node; |
2969 | obj->gtt_offset = node->start; | |
1c5d22f7 | 2970 | |
75e9e915 | 2971 | fenceable = |
dc9dd7a2 CW |
2972 | node->size == fence_size && |
2973 | (node->start & (fence_alignment - 1)) == 0; | |
a00b10c3 | 2974 | |
75e9e915 | 2975 | mappable = |
5d4545ae | 2976 | obj->gtt_offset + obj->base.size <= dev_priv->gtt.mappable_end; |
a00b10c3 | 2977 | |
05394f39 | 2978 | obj->map_and_fenceable = mappable && fenceable; |
75e9e915 | 2979 | |
fbdda6fb | 2980 | i915_gem_object_unpin_pages(obj); |
db53a302 | 2981 | trace_i915_gem_object_bind(obj, map_and_fenceable); |
42d6ab48 | 2982 | i915_gem_verify_gtt(dev); |
673a394b EA |
2983 | return 0; |
2984 | } | |
2985 | ||
2986 | void | |
05394f39 | 2987 | i915_gem_clflush_object(struct drm_i915_gem_object *obj) |
673a394b | 2988 | { |
673a394b EA |
2989 | /* If we don't have a page list set up, then we're not pinned |
2990 | * to GPU, and we can ignore the cache flush because it'll happen | |
2991 | * again at bind time. | |
2992 | */ | |
05394f39 | 2993 | if (obj->pages == NULL) |
673a394b EA |
2994 | return; |
2995 | ||
9c23f7fc CW |
2996 | /* If the GPU is snooping the contents of the CPU cache, |
2997 | * we do not need to manually clear the CPU cache lines. However, | |
2998 | * the caches are only snooped when the render cache is | |
2999 | * flushed/invalidated. As we always have to emit invalidations | |
3000 | * and flushes when moving into and out of the RENDER domain, correct | |
3001 | * snooping behaviour occurs naturally as the result of our domain | |
3002 | * tracking. | |
3003 | */ | |
3004 | if (obj->cache_level != I915_CACHE_NONE) | |
3005 | return; | |
3006 | ||
1c5d22f7 | 3007 | trace_i915_gem_object_clflush(obj); |
cfa16a0d | 3008 | |
9da3da66 | 3009 | drm_clflush_sg(obj->pages); |
e47c68e9 EA |
3010 | } |
3011 | ||
3012 | /** Flushes the GTT write domain for the object if it's dirty. */ | |
3013 | static void | |
05394f39 | 3014 | i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj) |
e47c68e9 | 3015 | { |
1c5d22f7 CW |
3016 | uint32_t old_write_domain; |
3017 | ||
05394f39 | 3018 | if (obj->base.write_domain != I915_GEM_DOMAIN_GTT) |
e47c68e9 EA |
3019 | return; |
3020 | ||
63256ec5 | 3021 | /* No actual flushing is required for the GTT write domain. Writes |
e47c68e9 EA |
3022 | * to it immediately go to main memory as far as we know, so there's |
3023 | * no chipset flush. It also doesn't land in render cache. | |
63256ec5 CW |
3024 | * |
3025 | * However, we do have to enforce the order so that all writes through | |
3026 | * the GTT land before any writes to the device, such as updates to | |
3027 | * the GATT itself. | |
e47c68e9 | 3028 | */ |
63256ec5 CW |
3029 | wmb(); |
3030 | ||
05394f39 CW |
3031 | old_write_domain = obj->base.write_domain; |
3032 | obj->base.write_domain = 0; | |
1c5d22f7 CW |
3033 | |
3034 | trace_i915_gem_object_change_domain(obj, | |
05394f39 | 3035 | obj->base.read_domains, |
1c5d22f7 | 3036 | old_write_domain); |
e47c68e9 EA |
3037 | } |
3038 | ||
3039 | /** Flushes the CPU write domain for the object if it's dirty. */ | |
3040 | static void | |
05394f39 | 3041 | i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj) |
e47c68e9 | 3042 | { |
1c5d22f7 | 3043 | uint32_t old_write_domain; |
e47c68e9 | 3044 | |
05394f39 | 3045 | if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) |
e47c68e9 EA |
3046 | return; |
3047 | ||
3048 | i915_gem_clflush_object(obj); | |
e76e9aeb | 3049 | i915_gem_chipset_flush(obj->base.dev); |
05394f39 CW |
3050 | old_write_domain = obj->base.write_domain; |
3051 | obj->base.write_domain = 0; | |
1c5d22f7 CW |
3052 | |
3053 | trace_i915_gem_object_change_domain(obj, | |
05394f39 | 3054 | obj->base.read_domains, |
1c5d22f7 | 3055 | old_write_domain); |
e47c68e9 EA |
3056 | } |
3057 | ||
2ef7eeaa EA |
3058 | /** |
3059 | * Moves a single object to the GTT read, and possibly write domain. | |
3060 | * | |
3061 | * This function returns when the move is complete, including waiting on | |
3062 | * flushes to occur. | |
3063 | */ | |
79e53945 | 3064 | int |
2021746e | 3065 | i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write) |
2ef7eeaa | 3066 | { |
8325a09d | 3067 | drm_i915_private_t *dev_priv = obj->base.dev->dev_private; |
1c5d22f7 | 3068 | uint32_t old_write_domain, old_read_domains; |
e47c68e9 | 3069 | int ret; |
2ef7eeaa | 3070 | |
02354392 | 3071 | /* Not valid to be called on unbound objects. */ |
05394f39 | 3072 | if (obj->gtt_space == NULL) |
02354392 EA |
3073 | return -EINVAL; |
3074 | ||
8d7e3de1 CW |
3075 | if (obj->base.write_domain == I915_GEM_DOMAIN_GTT) |
3076 | return 0; | |
3077 | ||
0201f1ec | 3078 | ret = i915_gem_object_wait_rendering(obj, !write); |
88241785 CW |
3079 | if (ret) |
3080 | return ret; | |
3081 | ||
7213342d | 3082 | i915_gem_object_flush_cpu_write_domain(obj); |
1c5d22f7 | 3083 | |
d0a57789 CW |
3084 | /* Serialise direct access to this object with the barriers for |
3085 | * coherent writes from the GPU, by effectively invalidating the | |
3086 | * GTT domain upon first access. | |
3087 | */ | |
3088 | if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0) | |
3089 | mb(); | |
3090 | ||
05394f39 CW |
3091 | old_write_domain = obj->base.write_domain; |
3092 | old_read_domains = obj->base.read_domains; | |
1c5d22f7 | 3093 | |
e47c68e9 EA |
3094 | /* It should now be out of any other write domains, and we can update |
3095 | * the domain values for our changes. | |
3096 | */ | |
05394f39 CW |
3097 | BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) != 0); |
3098 | obj->base.read_domains |= I915_GEM_DOMAIN_GTT; | |
e47c68e9 | 3099 | if (write) { |
05394f39 CW |
3100 | obj->base.read_domains = I915_GEM_DOMAIN_GTT; |
3101 | obj->base.write_domain = I915_GEM_DOMAIN_GTT; | |
3102 | obj->dirty = 1; | |
2ef7eeaa EA |
3103 | } |
3104 | ||
1c5d22f7 CW |
3105 | trace_i915_gem_object_change_domain(obj, |
3106 | old_read_domains, | |
3107 | old_write_domain); | |
3108 | ||
8325a09d CW |
3109 | /* And bump the LRU for this access */ |
3110 | if (i915_gem_object_is_inactive(obj)) | |
3111 | list_move_tail(&obj->mm_list, &dev_priv->mm.inactive_list); | |
3112 | ||
e47c68e9 EA |
3113 | return 0; |
3114 | } | |
3115 | ||
e4ffd173 CW |
3116 | int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj, |
3117 | enum i915_cache_level cache_level) | |
3118 | { | |
7bddb01f DV |
3119 | struct drm_device *dev = obj->base.dev; |
3120 | drm_i915_private_t *dev_priv = dev->dev_private; | |
e4ffd173 CW |
3121 | int ret; |
3122 | ||
3123 | if (obj->cache_level == cache_level) | |
3124 | return 0; | |
3125 | ||
3126 | if (obj->pin_count) { | |
3127 | DRM_DEBUG("can not change the cache level of pinned objects\n"); | |
3128 | return -EBUSY; | |
3129 | } | |
3130 | ||
42d6ab48 CW |
3131 | if (!i915_gem_valid_gtt_space(dev, obj->gtt_space, cache_level)) { |
3132 | ret = i915_gem_object_unbind(obj); | |
3133 | if (ret) | |
3134 | return ret; | |
3135 | } | |
3136 | ||
e4ffd173 CW |
3137 | if (obj->gtt_space) { |
3138 | ret = i915_gem_object_finish_gpu(obj); | |
3139 | if (ret) | |
3140 | return ret; | |
3141 | ||
3142 | i915_gem_object_finish_gtt(obj); | |
3143 | ||
3144 | /* Before SandyBridge, you could not use tiling or fence | |
3145 | * registers with snooped memory, so relinquish any fences | |
3146 | * currently pointing to our region in the aperture. | |
3147 | */ | |
42d6ab48 | 3148 | if (INTEL_INFO(dev)->gen < 6) { |
e4ffd173 CW |
3149 | ret = i915_gem_object_put_fence(obj); |
3150 | if (ret) | |
3151 | return ret; | |
3152 | } | |
3153 | ||
74898d7e DV |
3154 | if (obj->has_global_gtt_mapping) |
3155 | i915_gem_gtt_bind_object(obj, cache_level); | |
7bddb01f DV |
3156 | if (obj->has_aliasing_ppgtt_mapping) |
3157 | i915_ppgtt_bind_object(dev_priv->mm.aliasing_ppgtt, | |
3158 | obj, cache_level); | |
42d6ab48 CW |
3159 | |
3160 | obj->gtt_space->color = cache_level; | |
e4ffd173 CW |
3161 | } |
3162 | ||
3163 | if (cache_level == I915_CACHE_NONE) { | |
3164 | u32 old_read_domains, old_write_domain; | |
3165 | ||
3166 | /* If we're coming from LLC cached, then we haven't | |
3167 | * actually been tracking whether the data is in the | |
3168 | * CPU cache or not, since we only allow one bit set | |
3169 | * in obj->write_domain and have been skipping the clflushes. | |
3170 | * Just set it to the CPU cache for now. | |
3171 | */ | |
3172 | WARN_ON(obj->base.write_domain & ~I915_GEM_DOMAIN_CPU); | |
3173 | WARN_ON(obj->base.read_domains & ~I915_GEM_DOMAIN_CPU); | |
3174 | ||
3175 | old_read_domains = obj->base.read_domains; | |
3176 | old_write_domain = obj->base.write_domain; | |
3177 | ||
3178 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; | |
3179 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; | |
3180 | ||
3181 | trace_i915_gem_object_change_domain(obj, | |
3182 | old_read_domains, | |
3183 | old_write_domain); | |
3184 | } | |
3185 | ||
3186 | obj->cache_level = cache_level; | |
42d6ab48 | 3187 | i915_gem_verify_gtt(dev); |
e4ffd173 CW |
3188 | return 0; |
3189 | } | |
3190 | ||
199adf40 BW |
3191 | int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data, |
3192 | struct drm_file *file) | |
e6994aee | 3193 | { |
199adf40 | 3194 | struct drm_i915_gem_caching *args = data; |
e6994aee CW |
3195 | struct drm_i915_gem_object *obj; |
3196 | int ret; | |
3197 | ||
3198 | ret = i915_mutex_lock_interruptible(dev); | |
3199 | if (ret) | |
3200 | return ret; | |
3201 | ||
3202 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); | |
3203 | if (&obj->base == NULL) { | |
3204 | ret = -ENOENT; | |
3205 | goto unlock; | |
3206 | } | |
3207 | ||
199adf40 | 3208 | args->caching = obj->cache_level != I915_CACHE_NONE; |
e6994aee CW |
3209 | |
3210 | drm_gem_object_unreference(&obj->base); | |
3211 | unlock: | |
3212 | mutex_unlock(&dev->struct_mutex); | |
3213 | return ret; | |
3214 | } | |
3215 | ||
199adf40 BW |
3216 | int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data, |
3217 | struct drm_file *file) | |
e6994aee | 3218 | { |
199adf40 | 3219 | struct drm_i915_gem_caching *args = data; |
e6994aee CW |
3220 | struct drm_i915_gem_object *obj; |
3221 | enum i915_cache_level level; | |
3222 | int ret; | |
3223 | ||
199adf40 BW |
3224 | switch (args->caching) { |
3225 | case I915_CACHING_NONE: | |
e6994aee CW |
3226 | level = I915_CACHE_NONE; |
3227 | break; | |
199adf40 | 3228 | case I915_CACHING_CACHED: |
e6994aee CW |
3229 | level = I915_CACHE_LLC; |
3230 | break; | |
3231 | default: | |
3232 | return -EINVAL; | |
3233 | } | |
3234 | ||
3bc2913e BW |
3235 | ret = i915_mutex_lock_interruptible(dev); |
3236 | if (ret) | |
3237 | return ret; | |
3238 | ||
e6994aee CW |
3239 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
3240 | if (&obj->base == NULL) { | |
3241 | ret = -ENOENT; | |
3242 | goto unlock; | |
3243 | } | |
3244 | ||
3245 | ret = i915_gem_object_set_cache_level(obj, level); | |
3246 | ||
3247 | drm_gem_object_unreference(&obj->base); | |
3248 | unlock: | |
3249 | mutex_unlock(&dev->struct_mutex); | |
3250 | return ret; | |
3251 | } | |
3252 | ||
b9241ea3 | 3253 | /* |
2da3b9b9 CW |
3254 | * Prepare buffer for display plane (scanout, cursors, etc). |
3255 | * Can be called from an uninterruptible phase (modesetting) and allows | |
3256 | * any flushes to be pipelined (for pageflips). | |
b9241ea3 ZW |
3257 | */ |
3258 | int | |
2da3b9b9 CW |
3259 | i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj, |
3260 | u32 alignment, | |
919926ae | 3261 | struct intel_ring_buffer *pipelined) |
b9241ea3 | 3262 | { |
2da3b9b9 | 3263 | u32 old_read_domains, old_write_domain; |
b9241ea3 ZW |
3264 | int ret; |
3265 | ||
0be73284 | 3266 | if (pipelined != obj->ring) { |
2911a35b BW |
3267 | ret = i915_gem_object_sync(obj, pipelined); |
3268 | if (ret) | |
b9241ea3 ZW |
3269 | return ret; |
3270 | } | |
3271 | ||
a7ef0640 EA |
3272 | /* The display engine is not coherent with the LLC cache on gen6. As |
3273 | * a result, we make sure that the pinning that is about to occur is | |
3274 | * done with uncached PTEs. This is lowest common denominator for all | |
3275 | * chipsets. | |
3276 | * | |
3277 | * However for gen6+, we could do better by using the GFDT bit instead | |
3278 | * of uncaching, which would allow us to flush all the LLC-cached data | |
3279 | * with that bit in the PTE to main memory with just one PIPE_CONTROL. | |
3280 | */ | |
3281 | ret = i915_gem_object_set_cache_level(obj, I915_CACHE_NONE); | |
3282 | if (ret) | |
3283 | return ret; | |
3284 | ||
2da3b9b9 CW |
3285 | /* As the user may map the buffer once pinned in the display plane |
3286 | * (e.g. libkms for the bootup splash), we have to ensure that we | |
3287 | * always use map_and_fenceable for all scanout buffers. | |
3288 | */ | |
86a1ee26 | 3289 | ret = i915_gem_object_pin(obj, alignment, true, false); |
2da3b9b9 CW |
3290 | if (ret) |
3291 | return ret; | |
3292 | ||
b118c1e3 CW |
3293 | i915_gem_object_flush_cpu_write_domain(obj); |
3294 | ||
2da3b9b9 | 3295 | old_write_domain = obj->base.write_domain; |
05394f39 | 3296 | old_read_domains = obj->base.read_domains; |
2da3b9b9 CW |
3297 | |
3298 | /* It should now be out of any other write domains, and we can update | |
3299 | * the domain values for our changes. | |
3300 | */ | |
e5f1d962 | 3301 | obj->base.write_domain = 0; |
05394f39 | 3302 | obj->base.read_domains |= I915_GEM_DOMAIN_GTT; |
b9241ea3 ZW |
3303 | |
3304 | trace_i915_gem_object_change_domain(obj, | |
3305 | old_read_domains, | |
2da3b9b9 | 3306 | old_write_domain); |
b9241ea3 ZW |
3307 | |
3308 | return 0; | |
3309 | } | |
3310 | ||
85345517 | 3311 | int |
a8198eea | 3312 | i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj) |
85345517 | 3313 | { |
88241785 CW |
3314 | int ret; |
3315 | ||
a8198eea | 3316 | if ((obj->base.read_domains & I915_GEM_GPU_DOMAINS) == 0) |
85345517 CW |
3317 | return 0; |
3318 | ||
0201f1ec | 3319 | ret = i915_gem_object_wait_rendering(obj, false); |
c501ae7f CW |
3320 | if (ret) |
3321 | return ret; | |
3322 | ||
a8198eea CW |
3323 | /* Ensure that we invalidate the GPU's caches and TLBs. */ |
3324 | obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS; | |
c501ae7f | 3325 | return 0; |
85345517 CW |
3326 | } |
3327 | ||
e47c68e9 EA |
3328 | /** |
3329 | * Moves a single object to the CPU read, and possibly write domain. | |
3330 | * | |
3331 | * This function returns when the move is complete, including waiting on | |
3332 | * flushes to occur. | |
3333 | */ | |
dabdfe02 | 3334 | int |
919926ae | 3335 | i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write) |
e47c68e9 | 3336 | { |
1c5d22f7 | 3337 | uint32_t old_write_domain, old_read_domains; |
e47c68e9 EA |
3338 | int ret; |
3339 | ||
8d7e3de1 CW |
3340 | if (obj->base.write_domain == I915_GEM_DOMAIN_CPU) |
3341 | return 0; | |
3342 | ||
0201f1ec | 3343 | ret = i915_gem_object_wait_rendering(obj, !write); |
88241785 CW |
3344 | if (ret) |
3345 | return ret; | |
3346 | ||
e47c68e9 | 3347 | i915_gem_object_flush_gtt_write_domain(obj); |
2ef7eeaa | 3348 | |
05394f39 CW |
3349 | old_write_domain = obj->base.write_domain; |
3350 | old_read_domains = obj->base.read_domains; | |
1c5d22f7 | 3351 | |
e47c68e9 | 3352 | /* Flush the CPU cache if it's still invalid. */ |
05394f39 | 3353 | if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) { |
2ef7eeaa | 3354 | i915_gem_clflush_object(obj); |
2ef7eeaa | 3355 | |
05394f39 | 3356 | obj->base.read_domains |= I915_GEM_DOMAIN_CPU; |
2ef7eeaa EA |
3357 | } |
3358 | ||
3359 | /* It should now be out of any other write domains, and we can update | |
3360 | * the domain values for our changes. | |
3361 | */ | |
05394f39 | 3362 | BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) != 0); |
e47c68e9 EA |
3363 | |
3364 | /* If we're writing through the CPU, then the GPU read domains will | |
3365 | * need to be invalidated at next use. | |
3366 | */ | |
3367 | if (write) { | |
05394f39 CW |
3368 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; |
3369 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; | |
e47c68e9 | 3370 | } |
2ef7eeaa | 3371 | |
1c5d22f7 CW |
3372 | trace_i915_gem_object_change_domain(obj, |
3373 | old_read_domains, | |
3374 | old_write_domain); | |
3375 | ||
2ef7eeaa EA |
3376 | return 0; |
3377 | } | |
3378 | ||
673a394b EA |
3379 | /* Throttle our rendering by waiting until the ring has completed our requests |
3380 | * emitted over 20 msec ago. | |
3381 | * | |
b962442e EA |
3382 | * Note that if we were to use the current jiffies each time around the loop, |
3383 | * we wouldn't escape the function with any frames outstanding if the time to | |
3384 | * render a frame was over 20ms. | |
3385 | * | |
673a394b EA |
3386 | * This should get us reasonable parallelism between CPU and GPU but also |
3387 | * relatively low latency when blocking on a particular request to finish. | |
3388 | */ | |
40a5f0de | 3389 | static int |
f787a5f5 | 3390 | i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file) |
40a5f0de | 3391 | { |
f787a5f5 CW |
3392 | struct drm_i915_private *dev_priv = dev->dev_private; |
3393 | struct drm_i915_file_private *file_priv = file->driver_priv; | |
b962442e | 3394 | unsigned long recent_enough = jiffies - msecs_to_jiffies(20); |
f787a5f5 CW |
3395 | struct drm_i915_gem_request *request; |
3396 | struct intel_ring_buffer *ring = NULL; | |
3397 | u32 seqno = 0; | |
3398 | int ret; | |
93533c29 | 3399 | |
308887aa DV |
3400 | ret = i915_gem_wait_for_error(&dev_priv->gpu_error); |
3401 | if (ret) | |
3402 | return ret; | |
3403 | ||
3404 | ret = i915_gem_check_wedge(&dev_priv->gpu_error, false); | |
3405 | if (ret) | |
3406 | return ret; | |
e110e8d6 | 3407 | |
1c25595f | 3408 | spin_lock(&file_priv->mm.lock); |
f787a5f5 | 3409 | list_for_each_entry(request, &file_priv->mm.request_list, client_list) { |
b962442e EA |
3410 | if (time_after_eq(request->emitted_jiffies, recent_enough)) |
3411 | break; | |
40a5f0de | 3412 | |
f787a5f5 CW |
3413 | ring = request->ring; |
3414 | seqno = request->seqno; | |
b962442e | 3415 | } |
1c25595f | 3416 | spin_unlock(&file_priv->mm.lock); |
40a5f0de | 3417 | |
f787a5f5 CW |
3418 | if (seqno == 0) |
3419 | return 0; | |
2bc43b5c | 3420 | |
5c81fe85 | 3421 | ret = __wait_seqno(ring, seqno, true, NULL); |
f787a5f5 CW |
3422 | if (ret == 0) |
3423 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, 0); | |
40a5f0de EA |
3424 | |
3425 | return ret; | |
3426 | } | |
3427 | ||
673a394b | 3428 | int |
05394f39 CW |
3429 | i915_gem_object_pin(struct drm_i915_gem_object *obj, |
3430 | uint32_t alignment, | |
86a1ee26 CW |
3431 | bool map_and_fenceable, |
3432 | bool nonblocking) | |
673a394b | 3433 | { |
673a394b EA |
3434 | int ret; |
3435 | ||
7e81a42e CW |
3436 | if (WARN_ON(obj->pin_count == DRM_I915_GEM_OBJECT_MAX_PIN_COUNT)) |
3437 | return -EBUSY; | |
ac0c6b5a | 3438 | |
05394f39 CW |
3439 | if (obj->gtt_space != NULL) { |
3440 | if ((alignment && obj->gtt_offset & (alignment - 1)) || | |
3441 | (map_and_fenceable && !obj->map_and_fenceable)) { | |
3442 | WARN(obj->pin_count, | |
ae7d49d8 | 3443 | "bo is already pinned with incorrect alignment:" |
75e9e915 DV |
3444 | " offset=%x, req.alignment=%x, req.map_and_fenceable=%d," |
3445 | " obj->map_and_fenceable=%d\n", | |
05394f39 | 3446 | obj->gtt_offset, alignment, |
75e9e915 | 3447 | map_and_fenceable, |
05394f39 | 3448 | obj->map_and_fenceable); |
ac0c6b5a CW |
3449 | ret = i915_gem_object_unbind(obj); |
3450 | if (ret) | |
3451 | return ret; | |
3452 | } | |
3453 | } | |
3454 | ||
05394f39 | 3455 | if (obj->gtt_space == NULL) { |
8742267a CW |
3456 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
3457 | ||
a00b10c3 | 3458 | ret = i915_gem_object_bind_to_gtt(obj, alignment, |
86a1ee26 CW |
3459 | map_and_fenceable, |
3460 | nonblocking); | |
9731129c | 3461 | if (ret) |
673a394b | 3462 | return ret; |
8742267a CW |
3463 | |
3464 | if (!dev_priv->mm.aliasing_ppgtt) | |
3465 | i915_gem_gtt_bind_object(obj, obj->cache_level); | |
22c344e9 | 3466 | } |
76446cac | 3467 | |
74898d7e DV |
3468 | if (!obj->has_global_gtt_mapping && map_and_fenceable) |
3469 | i915_gem_gtt_bind_object(obj, obj->cache_level); | |
3470 | ||
1b50247a | 3471 | obj->pin_count++; |
6299f992 | 3472 | obj->pin_mappable |= map_and_fenceable; |
673a394b EA |
3473 | |
3474 | return 0; | |
3475 | } | |
3476 | ||
3477 | void | |
05394f39 | 3478 | i915_gem_object_unpin(struct drm_i915_gem_object *obj) |
673a394b | 3479 | { |
05394f39 CW |
3480 | BUG_ON(obj->pin_count == 0); |
3481 | BUG_ON(obj->gtt_space == NULL); | |
673a394b | 3482 | |
1b50247a | 3483 | if (--obj->pin_count == 0) |
6299f992 | 3484 | obj->pin_mappable = false; |
673a394b EA |
3485 | } |
3486 | ||
3487 | int | |
3488 | i915_gem_pin_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 3489 | struct drm_file *file) |
673a394b EA |
3490 | { |
3491 | struct drm_i915_gem_pin *args = data; | |
05394f39 | 3492 | struct drm_i915_gem_object *obj; |
673a394b EA |
3493 | int ret; |
3494 | ||
1d7cfea1 CW |
3495 | ret = i915_mutex_lock_interruptible(dev); |
3496 | if (ret) | |
3497 | return ret; | |
673a394b | 3498 | |
05394f39 | 3499 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 3500 | if (&obj->base == NULL) { |
1d7cfea1 CW |
3501 | ret = -ENOENT; |
3502 | goto unlock; | |
673a394b | 3503 | } |
673a394b | 3504 | |
05394f39 | 3505 | if (obj->madv != I915_MADV_WILLNEED) { |
bb6baf76 | 3506 | DRM_ERROR("Attempting to pin a purgeable buffer\n"); |
1d7cfea1 CW |
3507 | ret = -EINVAL; |
3508 | goto out; | |
3ef94daa CW |
3509 | } |
3510 | ||
05394f39 | 3511 | if (obj->pin_filp != NULL && obj->pin_filp != file) { |
79e53945 JB |
3512 | DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n", |
3513 | args->handle); | |
1d7cfea1 CW |
3514 | ret = -EINVAL; |
3515 | goto out; | |
79e53945 JB |
3516 | } |
3517 | ||
05394f39 CW |
3518 | obj->user_pin_count++; |
3519 | obj->pin_filp = file; | |
3520 | if (obj->user_pin_count == 1) { | |
86a1ee26 | 3521 | ret = i915_gem_object_pin(obj, args->alignment, true, false); |
1d7cfea1 CW |
3522 | if (ret) |
3523 | goto out; | |
673a394b EA |
3524 | } |
3525 | ||
3526 | /* XXX - flush the CPU caches for pinned objects | |
3527 | * as the X server doesn't manage domains yet | |
3528 | */ | |
e47c68e9 | 3529 | i915_gem_object_flush_cpu_write_domain(obj); |
05394f39 | 3530 | args->offset = obj->gtt_offset; |
1d7cfea1 | 3531 | out: |
05394f39 | 3532 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 3533 | unlock: |
673a394b | 3534 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 3535 | return ret; |
673a394b EA |
3536 | } |
3537 | ||
3538 | int | |
3539 | i915_gem_unpin_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 3540 | struct drm_file *file) |
673a394b EA |
3541 | { |
3542 | struct drm_i915_gem_pin *args = data; | |
05394f39 | 3543 | struct drm_i915_gem_object *obj; |
76c1dec1 | 3544 | int ret; |
673a394b | 3545 | |
1d7cfea1 CW |
3546 | ret = i915_mutex_lock_interruptible(dev); |
3547 | if (ret) | |
3548 | return ret; | |
673a394b | 3549 | |
05394f39 | 3550 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 3551 | if (&obj->base == NULL) { |
1d7cfea1 CW |
3552 | ret = -ENOENT; |
3553 | goto unlock; | |
673a394b | 3554 | } |
76c1dec1 | 3555 | |
05394f39 | 3556 | if (obj->pin_filp != file) { |
79e53945 JB |
3557 | DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n", |
3558 | args->handle); | |
1d7cfea1 CW |
3559 | ret = -EINVAL; |
3560 | goto out; | |
79e53945 | 3561 | } |
05394f39 CW |
3562 | obj->user_pin_count--; |
3563 | if (obj->user_pin_count == 0) { | |
3564 | obj->pin_filp = NULL; | |
79e53945 JB |
3565 | i915_gem_object_unpin(obj); |
3566 | } | |
673a394b | 3567 | |
1d7cfea1 | 3568 | out: |
05394f39 | 3569 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 3570 | unlock: |
673a394b | 3571 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 3572 | return ret; |
673a394b EA |
3573 | } |
3574 | ||
3575 | int | |
3576 | i915_gem_busy_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 3577 | struct drm_file *file) |
673a394b EA |
3578 | { |
3579 | struct drm_i915_gem_busy *args = data; | |
05394f39 | 3580 | struct drm_i915_gem_object *obj; |
30dbf0c0 CW |
3581 | int ret; |
3582 | ||
76c1dec1 | 3583 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 3584 | if (ret) |
76c1dec1 | 3585 | return ret; |
673a394b | 3586 | |
05394f39 | 3587 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 3588 | if (&obj->base == NULL) { |
1d7cfea1 CW |
3589 | ret = -ENOENT; |
3590 | goto unlock; | |
673a394b | 3591 | } |
d1b851fc | 3592 | |
0be555b6 CW |
3593 | /* Count all active objects as busy, even if they are currently not used |
3594 | * by the gpu. Users of this interface expect objects to eventually | |
3595 | * become non-busy without any further actions, therefore emit any | |
3596 | * necessary flushes here. | |
c4de0a5d | 3597 | */ |
30dfebf3 | 3598 | ret = i915_gem_object_flush_active(obj); |
0be555b6 | 3599 | |
30dfebf3 | 3600 | args->busy = obj->active; |
e9808edd CW |
3601 | if (obj->ring) { |
3602 | BUILD_BUG_ON(I915_NUM_RINGS > 16); | |
3603 | args->busy |= intel_ring_flag(obj->ring) << 16; | |
3604 | } | |
673a394b | 3605 | |
05394f39 | 3606 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 3607 | unlock: |
673a394b | 3608 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 3609 | return ret; |
673a394b EA |
3610 | } |
3611 | ||
3612 | int | |
3613 | i915_gem_throttle_ioctl(struct drm_device *dev, void *data, | |
3614 | struct drm_file *file_priv) | |
3615 | { | |
0206e353 | 3616 | return i915_gem_ring_throttle(dev, file_priv); |
673a394b EA |
3617 | } |
3618 | ||
3ef94daa CW |
3619 | int |
3620 | i915_gem_madvise_ioctl(struct drm_device *dev, void *data, | |
3621 | struct drm_file *file_priv) | |
3622 | { | |
3623 | struct drm_i915_gem_madvise *args = data; | |
05394f39 | 3624 | struct drm_i915_gem_object *obj; |
76c1dec1 | 3625 | int ret; |
3ef94daa CW |
3626 | |
3627 | switch (args->madv) { | |
3628 | case I915_MADV_DONTNEED: | |
3629 | case I915_MADV_WILLNEED: | |
3630 | break; | |
3631 | default: | |
3632 | return -EINVAL; | |
3633 | } | |
3634 | ||
1d7cfea1 CW |
3635 | ret = i915_mutex_lock_interruptible(dev); |
3636 | if (ret) | |
3637 | return ret; | |
3638 | ||
05394f39 | 3639 | obj = to_intel_bo(drm_gem_object_lookup(dev, file_priv, args->handle)); |
c8725226 | 3640 | if (&obj->base == NULL) { |
1d7cfea1 CW |
3641 | ret = -ENOENT; |
3642 | goto unlock; | |
3ef94daa | 3643 | } |
3ef94daa | 3644 | |
05394f39 | 3645 | if (obj->pin_count) { |
1d7cfea1 CW |
3646 | ret = -EINVAL; |
3647 | goto out; | |
3ef94daa CW |
3648 | } |
3649 | ||
05394f39 CW |
3650 | if (obj->madv != __I915_MADV_PURGED) |
3651 | obj->madv = args->madv; | |
3ef94daa | 3652 | |
6c085a72 CW |
3653 | /* if the object is no longer attached, discard its backing storage */ |
3654 | if (i915_gem_object_is_purgeable(obj) && obj->pages == NULL) | |
2d7ef395 CW |
3655 | i915_gem_object_truncate(obj); |
3656 | ||
05394f39 | 3657 | args->retained = obj->madv != __I915_MADV_PURGED; |
bb6baf76 | 3658 | |
1d7cfea1 | 3659 | out: |
05394f39 | 3660 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 3661 | unlock: |
3ef94daa | 3662 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 3663 | return ret; |
3ef94daa CW |
3664 | } |
3665 | ||
37e680a1 CW |
3666 | void i915_gem_object_init(struct drm_i915_gem_object *obj, |
3667 | const struct drm_i915_gem_object_ops *ops) | |
0327d6ba | 3668 | { |
0327d6ba CW |
3669 | INIT_LIST_HEAD(&obj->mm_list); |
3670 | INIT_LIST_HEAD(&obj->gtt_list); | |
3671 | INIT_LIST_HEAD(&obj->ring_list); | |
3672 | INIT_LIST_HEAD(&obj->exec_list); | |
3673 | ||
37e680a1 CW |
3674 | obj->ops = ops; |
3675 | ||
0327d6ba CW |
3676 | obj->fence_reg = I915_FENCE_REG_NONE; |
3677 | obj->madv = I915_MADV_WILLNEED; | |
3678 | /* Avoid an unnecessary call to unbind on the first bind. */ | |
3679 | obj->map_and_fenceable = true; | |
3680 | ||
3681 | i915_gem_info_add_obj(obj->base.dev->dev_private, obj->base.size); | |
3682 | } | |
3683 | ||
37e680a1 CW |
3684 | static const struct drm_i915_gem_object_ops i915_gem_object_ops = { |
3685 | .get_pages = i915_gem_object_get_pages_gtt, | |
3686 | .put_pages = i915_gem_object_put_pages_gtt, | |
3687 | }; | |
3688 | ||
05394f39 CW |
3689 | struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev, |
3690 | size_t size) | |
ac52bc56 | 3691 | { |
c397b908 | 3692 | struct drm_i915_gem_object *obj; |
5949eac4 | 3693 | struct address_space *mapping; |
1a240d4d | 3694 | gfp_t mask; |
ac52bc56 | 3695 | |
42dcedd4 | 3696 | obj = i915_gem_object_alloc(dev); |
c397b908 DV |
3697 | if (obj == NULL) |
3698 | return NULL; | |
673a394b | 3699 | |
c397b908 | 3700 | if (drm_gem_object_init(dev, &obj->base, size) != 0) { |
42dcedd4 | 3701 | i915_gem_object_free(obj); |
c397b908 DV |
3702 | return NULL; |
3703 | } | |
673a394b | 3704 | |
bed1ea95 CW |
3705 | mask = GFP_HIGHUSER | __GFP_RECLAIMABLE; |
3706 | if (IS_CRESTLINE(dev) || IS_BROADWATER(dev)) { | |
3707 | /* 965gm cannot relocate objects above 4GiB. */ | |
3708 | mask &= ~__GFP_HIGHMEM; | |
3709 | mask |= __GFP_DMA32; | |
3710 | } | |
3711 | ||
5949eac4 | 3712 | mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping; |
bed1ea95 | 3713 | mapping_set_gfp_mask(mapping, mask); |
5949eac4 | 3714 | |
37e680a1 | 3715 | i915_gem_object_init(obj, &i915_gem_object_ops); |
73aa808f | 3716 | |
c397b908 DV |
3717 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; |
3718 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; | |
673a394b | 3719 | |
3d29b842 ED |
3720 | if (HAS_LLC(dev)) { |
3721 | /* On some devices, we can have the GPU use the LLC (the CPU | |
a1871112 EA |
3722 | * cache) for about a 10% performance improvement |
3723 | * compared to uncached. Graphics requests other than | |
3724 | * display scanout are coherent with the CPU in | |
3725 | * accessing this cache. This means in this mode we | |
3726 | * don't need to clflush on the CPU side, and on the | |
3727 | * GPU side we only need to flush internal caches to | |
3728 | * get data visible to the CPU. | |
3729 | * | |
3730 | * However, we maintain the display planes as UC, and so | |
3731 | * need to rebind when first used as such. | |
3732 | */ | |
3733 | obj->cache_level = I915_CACHE_LLC; | |
3734 | } else | |
3735 | obj->cache_level = I915_CACHE_NONE; | |
3736 | ||
05394f39 | 3737 | return obj; |
c397b908 DV |
3738 | } |
3739 | ||
3740 | int i915_gem_init_object(struct drm_gem_object *obj) | |
3741 | { | |
3742 | BUG(); | |
de151cf6 | 3743 | |
673a394b EA |
3744 | return 0; |
3745 | } | |
3746 | ||
1488fc08 | 3747 | void i915_gem_free_object(struct drm_gem_object *gem_obj) |
673a394b | 3748 | { |
1488fc08 | 3749 | struct drm_i915_gem_object *obj = to_intel_bo(gem_obj); |
05394f39 | 3750 | struct drm_device *dev = obj->base.dev; |
be72615b | 3751 | drm_i915_private_t *dev_priv = dev->dev_private; |
673a394b | 3752 | |
26e12f89 CW |
3753 | trace_i915_gem_object_destroy(obj); |
3754 | ||
1488fc08 CW |
3755 | if (obj->phys_obj) |
3756 | i915_gem_detach_phys_object(dev, obj); | |
3757 | ||
3758 | obj->pin_count = 0; | |
3759 | if (WARN_ON(i915_gem_object_unbind(obj) == -ERESTARTSYS)) { | |
3760 | bool was_interruptible; | |
3761 | ||
3762 | was_interruptible = dev_priv->mm.interruptible; | |
3763 | dev_priv->mm.interruptible = false; | |
3764 | ||
3765 | WARN_ON(i915_gem_object_unbind(obj)); | |
3766 | ||
3767 | dev_priv->mm.interruptible = was_interruptible; | |
3768 | } | |
3769 | ||
a5570178 | 3770 | obj->pages_pin_count = 0; |
37e680a1 | 3771 | i915_gem_object_put_pages(obj); |
d8cb5086 | 3772 | i915_gem_object_free_mmap_offset(obj); |
0104fdbb | 3773 | i915_gem_object_release_stolen(obj); |
de151cf6 | 3774 | |
9da3da66 CW |
3775 | BUG_ON(obj->pages); |
3776 | ||
2f745ad3 CW |
3777 | if (obj->base.import_attach) |
3778 | drm_prime_gem_destroy(&obj->base, NULL); | |
de151cf6 | 3779 | |
05394f39 CW |
3780 | drm_gem_object_release(&obj->base); |
3781 | i915_gem_info_remove_obj(dev_priv, obj->base.size); | |
c397b908 | 3782 | |
05394f39 | 3783 | kfree(obj->bit_17); |
42dcedd4 | 3784 | i915_gem_object_free(obj); |
673a394b EA |
3785 | } |
3786 | ||
29105ccc CW |
3787 | int |
3788 | i915_gem_idle(struct drm_device *dev) | |
3789 | { | |
3790 | drm_i915_private_t *dev_priv = dev->dev_private; | |
3791 | int ret; | |
28dfe52a | 3792 | |
29105ccc | 3793 | mutex_lock(&dev->struct_mutex); |
1c5d22f7 | 3794 | |
87acb0a5 | 3795 | if (dev_priv->mm.suspended) { |
29105ccc CW |
3796 | mutex_unlock(&dev->struct_mutex); |
3797 | return 0; | |
28dfe52a EA |
3798 | } |
3799 | ||
b2da9fe5 | 3800 | ret = i915_gpu_idle(dev); |
6dbe2772 KP |
3801 | if (ret) { |
3802 | mutex_unlock(&dev->struct_mutex); | |
673a394b | 3803 | return ret; |
6dbe2772 | 3804 | } |
b2da9fe5 | 3805 | i915_gem_retire_requests(dev); |
673a394b | 3806 | |
29105ccc | 3807 | /* Under UMS, be paranoid and evict. */ |
a39d7efc | 3808 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) |
6c085a72 | 3809 | i915_gem_evict_everything(dev); |
29105ccc | 3810 | |
312817a3 CW |
3811 | i915_gem_reset_fences(dev); |
3812 | ||
29105ccc CW |
3813 | /* Hack! Don't let anybody do execbuf while we don't control the chip. |
3814 | * We need to replace this with a semaphore, or something. | |
3815 | * And not confound mm.suspended! | |
3816 | */ | |
3817 | dev_priv->mm.suspended = 1; | |
99584db3 | 3818 | del_timer_sync(&dev_priv->gpu_error.hangcheck_timer); |
29105ccc CW |
3819 | |
3820 | i915_kernel_lost_context(dev); | |
6dbe2772 | 3821 | i915_gem_cleanup_ringbuffer(dev); |
29105ccc | 3822 | |
6dbe2772 KP |
3823 | mutex_unlock(&dev->struct_mutex); |
3824 | ||
29105ccc CW |
3825 | /* Cancel the retire work handler, which should be idle now. */ |
3826 | cancel_delayed_work_sync(&dev_priv->mm.retire_work); | |
3827 | ||
673a394b EA |
3828 | return 0; |
3829 | } | |
3830 | ||
b9524a1e BW |
3831 | void i915_gem_l3_remap(struct drm_device *dev) |
3832 | { | |
3833 | drm_i915_private_t *dev_priv = dev->dev_private; | |
3834 | u32 misccpctl; | |
3835 | int i; | |
3836 | ||
3837 | if (!IS_IVYBRIDGE(dev)) | |
3838 | return; | |
3839 | ||
a4da4fa4 | 3840 | if (!dev_priv->l3_parity.remap_info) |
b9524a1e BW |
3841 | return; |
3842 | ||
3843 | misccpctl = I915_READ(GEN7_MISCCPCTL); | |
3844 | I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE); | |
3845 | POSTING_READ(GEN7_MISCCPCTL); | |
3846 | ||
3847 | for (i = 0; i < GEN7_L3LOG_SIZE; i += 4) { | |
3848 | u32 remap = I915_READ(GEN7_L3LOG_BASE + i); | |
a4da4fa4 | 3849 | if (remap && remap != dev_priv->l3_parity.remap_info[i/4]) |
b9524a1e BW |
3850 | DRM_DEBUG("0x%x was already programmed to %x\n", |
3851 | GEN7_L3LOG_BASE + i, remap); | |
a4da4fa4 | 3852 | if (remap && !dev_priv->l3_parity.remap_info[i/4]) |
b9524a1e | 3853 | DRM_DEBUG_DRIVER("Clearing remapped register\n"); |
a4da4fa4 | 3854 | I915_WRITE(GEN7_L3LOG_BASE + i, dev_priv->l3_parity.remap_info[i/4]); |
b9524a1e BW |
3855 | } |
3856 | ||
3857 | /* Make sure all the writes land before disabling dop clock gating */ | |
3858 | POSTING_READ(GEN7_L3LOG_BASE); | |
3859 | ||
3860 | I915_WRITE(GEN7_MISCCPCTL, misccpctl); | |
3861 | } | |
3862 | ||
f691e2f4 DV |
3863 | void i915_gem_init_swizzling(struct drm_device *dev) |
3864 | { | |
3865 | drm_i915_private_t *dev_priv = dev->dev_private; | |
3866 | ||
11782b02 | 3867 | if (INTEL_INFO(dev)->gen < 5 || |
f691e2f4 DV |
3868 | dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE) |
3869 | return; | |
3870 | ||
3871 | I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) | | |
3872 | DISP_TILE_SURFACE_SWIZZLING); | |
3873 | ||
11782b02 DV |
3874 | if (IS_GEN5(dev)) |
3875 | return; | |
3876 | ||
f691e2f4 DV |
3877 | I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_SWZCTL); |
3878 | if (IS_GEN6(dev)) | |
6b26c86d | 3879 | I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB)); |
8782e26c | 3880 | else if (IS_GEN7(dev)) |
6b26c86d | 3881 | I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB)); |
8782e26c BW |
3882 | else |
3883 | BUG(); | |
f691e2f4 | 3884 | } |
e21af88d | 3885 | |
67b1b571 CW |
3886 | static bool |
3887 | intel_enable_blt(struct drm_device *dev) | |
3888 | { | |
3889 | if (!HAS_BLT(dev)) | |
3890 | return false; | |
3891 | ||
3892 | /* The blitter was dysfunctional on early prototypes */ | |
3893 | if (IS_GEN6(dev) && dev->pdev->revision < 8) { | |
3894 | DRM_INFO("BLT not supported on this pre-production hardware;" | |
3895 | " graphics performance will be degraded.\n"); | |
3896 | return false; | |
3897 | } | |
3898 | ||
3899 | return true; | |
3900 | } | |
3901 | ||
8187a2b7 | 3902 | int |
f691e2f4 | 3903 | i915_gem_init_hw(struct drm_device *dev) |
8187a2b7 ZN |
3904 | { |
3905 | drm_i915_private_t *dev_priv = dev->dev_private; | |
3906 | int ret; | |
68f95ba9 | 3907 | |
e76e9aeb | 3908 | if (INTEL_INFO(dev)->gen < 6 && !intel_enable_gtt()) |
8ecd1a66 DV |
3909 | return -EIO; |
3910 | ||
eda2d7f5 RV |
3911 | if (IS_HASWELL(dev) && (I915_READ(0x120010) == 1)) |
3912 | I915_WRITE(0x9008, I915_READ(0x9008) | 0xf0000); | |
3913 | ||
b9524a1e BW |
3914 | i915_gem_l3_remap(dev); |
3915 | ||
f691e2f4 DV |
3916 | i915_gem_init_swizzling(dev); |
3917 | ||
f7e98ad4 MK |
3918 | dev_priv->next_seqno = dev_priv->last_seqno = (u32)~0 - 0x1000; |
3919 | ||
5c1143bb | 3920 | ret = intel_init_render_ring_buffer(dev); |
68f95ba9 | 3921 | if (ret) |
b6913e4b | 3922 | return ret; |
68f95ba9 CW |
3923 | |
3924 | if (HAS_BSD(dev)) { | |
5c1143bb | 3925 | ret = intel_init_bsd_ring_buffer(dev); |
68f95ba9 CW |
3926 | if (ret) |
3927 | goto cleanup_render_ring; | |
d1b851fc | 3928 | } |
68f95ba9 | 3929 | |
67b1b571 | 3930 | if (intel_enable_blt(dev)) { |
549f7365 CW |
3931 | ret = intel_init_blt_ring_buffer(dev); |
3932 | if (ret) | |
3933 | goto cleanup_bsd_ring; | |
3934 | } | |
3935 | ||
254f965c BW |
3936 | /* |
3937 | * XXX: There was some w/a described somewhere suggesting loading | |
3938 | * contexts before PPGTT. | |
3939 | */ | |
3940 | i915_gem_context_init(dev); | |
e21af88d DV |
3941 | i915_gem_init_ppgtt(dev); |
3942 | ||
68f95ba9 CW |
3943 | return 0; |
3944 | ||
549f7365 | 3945 | cleanup_bsd_ring: |
1ec14ad3 | 3946 | intel_cleanup_ring_buffer(&dev_priv->ring[VCS]); |
68f95ba9 | 3947 | cleanup_render_ring: |
1ec14ad3 | 3948 | intel_cleanup_ring_buffer(&dev_priv->ring[RCS]); |
8187a2b7 ZN |
3949 | return ret; |
3950 | } | |
3951 | ||
1070a42b CW |
3952 | int i915_gem_init(struct drm_device *dev) |
3953 | { | |
3954 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1070a42b CW |
3955 | int ret; |
3956 | ||
1070a42b | 3957 | mutex_lock(&dev->struct_mutex); |
d7e5008f | 3958 | i915_gem_init_global_gtt(dev); |
1070a42b CW |
3959 | ret = i915_gem_init_hw(dev); |
3960 | mutex_unlock(&dev->struct_mutex); | |
3961 | if (ret) { | |
3962 | i915_gem_cleanup_aliasing_ppgtt(dev); | |
3963 | return ret; | |
3964 | } | |
3965 | ||
53ca26ca DV |
3966 | /* Allow hardware batchbuffers unless told otherwise, but not for KMS. */ |
3967 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) | |
3968 | dev_priv->dri1.allow_batchbuffer = 1; | |
1070a42b CW |
3969 | return 0; |
3970 | } | |
3971 | ||
8187a2b7 ZN |
3972 | void |
3973 | i915_gem_cleanup_ringbuffer(struct drm_device *dev) | |
3974 | { | |
3975 | drm_i915_private_t *dev_priv = dev->dev_private; | |
b4519513 | 3976 | struct intel_ring_buffer *ring; |
1ec14ad3 | 3977 | int i; |
8187a2b7 | 3978 | |
b4519513 CW |
3979 | for_each_ring(ring, dev_priv, i) |
3980 | intel_cleanup_ring_buffer(ring); | |
8187a2b7 ZN |
3981 | } |
3982 | ||
673a394b EA |
3983 | int |
3984 | i915_gem_entervt_ioctl(struct drm_device *dev, void *data, | |
3985 | struct drm_file *file_priv) | |
3986 | { | |
3987 | drm_i915_private_t *dev_priv = dev->dev_private; | |
b4519513 | 3988 | int ret; |
673a394b | 3989 | |
79e53945 JB |
3990 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
3991 | return 0; | |
3992 | ||
1f83fee0 | 3993 | if (i915_reset_in_progress(&dev_priv->gpu_error)) { |
673a394b | 3994 | DRM_ERROR("Reenabling wedged hardware, good luck\n"); |
1f83fee0 | 3995 | atomic_set(&dev_priv->gpu_error.reset_counter, 0); |
673a394b EA |
3996 | } |
3997 | ||
673a394b | 3998 | mutex_lock(&dev->struct_mutex); |
9bb2d6f9 EA |
3999 | dev_priv->mm.suspended = 0; |
4000 | ||
f691e2f4 | 4001 | ret = i915_gem_init_hw(dev); |
d816f6ac WF |
4002 | if (ret != 0) { |
4003 | mutex_unlock(&dev->struct_mutex); | |
9bb2d6f9 | 4004 | return ret; |
d816f6ac | 4005 | } |
9bb2d6f9 | 4006 | |
69dc4987 | 4007 | BUG_ON(!list_empty(&dev_priv->mm.active_list)); |
673a394b | 4008 | mutex_unlock(&dev->struct_mutex); |
dbb19d30 | 4009 | |
5f35308b CW |
4010 | ret = drm_irq_install(dev); |
4011 | if (ret) | |
4012 | goto cleanup_ringbuffer; | |
dbb19d30 | 4013 | |
673a394b | 4014 | return 0; |
5f35308b CW |
4015 | |
4016 | cleanup_ringbuffer: | |
4017 | mutex_lock(&dev->struct_mutex); | |
4018 | i915_gem_cleanup_ringbuffer(dev); | |
4019 | dev_priv->mm.suspended = 1; | |
4020 | mutex_unlock(&dev->struct_mutex); | |
4021 | ||
4022 | return ret; | |
673a394b EA |
4023 | } |
4024 | ||
4025 | int | |
4026 | i915_gem_leavevt_ioctl(struct drm_device *dev, void *data, | |
4027 | struct drm_file *file_priv) | |
4028 | { | |
79e53945 JB |
4029 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
4030 | return 0; | |
4031 | ||
dbb19d30 | 4032 | drm_irq_uninstall(dev); |
e6890f6f | 4033 | return i915_gem_idle(dev); |
673a394b EA |
4034 | } |
4035 | ||
4036 | void | |
4037 | i915_gem_lastclose(struct drm_device *dev) | |
4038 | { | |
4039 | int ret; | |
673a394b | 4040 | |
e806b495 EA |
4041 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
4042 | return; | |
4043 | ||
6dbe2772 KP |
4044 | ret = i915_gem_idle(dev); |
4045 | if (ret) | |
4046 | DRM_ERROR("failed to idle hardware: %d\n", ret); | |
673a394b EA |
4047 | } |
4048 | ||
64193406 CW |
4049 | static void |
4050 | init_ring_lists(struct intel_ring_buffer *ring) | |
4051 | { | |
4052 | INIT_LIST_HEAD(&ring->active_list); | |
4053 | INIT_LIST_HEAD(&ring->request_list); | |
64193406 CW |
4054 | } |
4055 | ||
673a394b EA |
4056 | void |
4057 | i915_gem_load(struct drm_device *dev) | |
4058 | { | |
4059 | drm_i915_private_t *dev_priv = dev->dev_private; | |
42dcedd4 CW |
4060 | int i; |
4061 | ||
4062 | dev_priv->slab = | |
4063 | kmem_cache_create("i915_gem_object", | |
4064 | sizeof(struct drm_i915_gem_object), 0, | |
4065 | SLAB_HWCACHE_ALIGN, | |
4066 | NULL); | |
673a394b | 4067 | |
69dc4987 | 4068 | INIT_LIST_HEAD(&dev_priv->mm.active_list); |
673a394b | 4069 | INIT_LIST_HEAD(&dev_priv->mm.inactive_list); |
6c085a72 CW |
4070 | INIT_LIST_HEAD(&dev_priv->mm.unbound_list); |
4071 | INIT_LIST_HEAD(&dev_priv->mm.bound_list); | |
a09ba7fa | 4072 | INIT_LIST_HEAD(&dev_priv->mm.fence_list); |
1ec14ad3 CW |
4073 | for (i = 0; i < I915_NUM_RINGS; i++) |
4074 | init_ring_lists(&dev_priv->ring[i]); | |
4b9de737 | 4075 | for (i = 0; i < I915_MAX_NUM_FENCES; i++) |
007cc8ac | 4076 | INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list); |
673a394b EA |
4077 | INIT_DELAYED_WORK(&dev_priv->mm.retire_work, |
4078 | i915_gem_retire_work_handler); | |
1f83fee0 | 4079 | init_waitqueue_head(&dev_priv->gpu_error.reset_queue); |
31169714 | 4080 | |
94400120 DA |
4081 | /* On GEN3 we really need to make sure the ARB C3 LP bit is set */ |
4082 | if (IS_GEN3(dev)) { | |
50743298 DV |
4083 | I915_WRITE(MI_ARB_STATE, |
4084 | _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE)); | |
94400120 DA |
4085 | } |
4086 | ||
72bfa19c CW |
4087 | dev_priv->relative_constants_mode = I915_EXEC_CONSTANTS_REL_GENERAL; |
4088 | ||
de151cf6 | 4089 | /* Old X drivers will take 0-2 for front, back, depth buffers */ |
b397c836 EA |
4090 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) |
4091 | dev_priv->fence_reg_start = 3; | |
de151cf6 | 4092 | |
a6c45cf0 | 4093 | if (INTEL_INFO(dev)->gen >= 4 || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) |
de151cf6 JB |
4094 | dev_priv->num_fence_regs = 16; |
4095 | else | |
4096 | dev_priv->num_fence_regs = 8; | |
4097 | ||
b5aa8a0f | 4098 | /* Initialize fence registers to zero */ |
ada726c7 | 4099 | i915_gem_reset_fences(dev); |
10ed13e4 | 4100 | |
673a394b | 4101 | i915_gem_detect_bit_6_swizzle(dev); |
6b95a207 | 4102 | init_waitqueue_head(&dev_priv->pending_flip_queue); |
17250b71 | 4103 | |
ce453d81 CW |
4104 | dev_priv->mm.interruptible = true; |
4105 | ||
17250b71 CW |
4106 | dev_priv->mm.inactive_shrinker.shrink = i915_gem_inactive_shrink; |
4107 | dev_priv->mm.inactive_shrinker.seeks = DEFAULT_SEEKS; | |
4108 | register_shrinker(&dev_priv->mm.inactive_shrinker); | |
673a394b | 4109 | } |
71acb5eb DA |
4110 | |
4111 | /* | |
4112 | * Create a physically contiguous memory object for this object | |
4113 | * e.g. for cursor + overlay regs | |
4114 | */ | |
995b6762 CW |
4115 | static int i915_gem_init_phys_object(struct drm_device *dev, |
4116 | int id, int size, int align) | |
71acb5eb DA |
4117 | { |
4118 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4119 | struct drm_i915_gem_phys_object *phys_obj; | |
4120 | int ret; | |
4121 | ||
4122 | if (dev_priv->mm.phys_objs[id - 1] || !size) | |
4123 | return 0; | |
4124 | ||
9a298b2a | 4125 | phys_obj = kzalloc(sizeof(struct drm_i915_gem_phys_object), GFP_KERNEL); |
71acb5eb DA |
4126 | if (!phys_obj) |
4127 | return -ENOMEM; | |
4128 | ||
4129 | phys_obj->id = id; | |
4130 | ||
6eeefaf3 | 4131 | phys_obj->handle = drm_pci_alloc(dev, size, align); |
71acb5eb DA |
4132 | if (!phys_obj->handle) { |
4133 | ret = -ENOMEM; | |
4134 | goto kfree_obj; | |
4135 | } | |
4136 | #ifdef CONFIG_X86 | |
4137 | set_memory_wc((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE); | |
4138 | #endif | |
4139 | ||
4140 | dev_priv->mm.phys_objs[id - 1] = phys_obj; | |
4141 | ||
4142 | return 0; | |
4143 | kfree_obj: | |
9a298b2a | 4144 | kfree(phys_obj); |
71acb5eb DA |
4145 | return ret; |
4146 | } | |
4147 | ||
995b6762 | 4148 | static void i915_gem_free_phys_object(struct drm_device *dev, int id) |
71acb5eb DA |
4149 | { |
4150 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4151 | struct drm_i915_gem_phys_object *phys_obj; | |
4152 | ||
4153 | if (!dev_priv->mm.phys_objs[id - 1]) | |
4154 | return; | |
4155 | ||
4156 | phys_obj = dev_priv->mm.phys_objs[id - 1]; | |
4157 | if (phys_obj->cur_obj) { | |
4158 | i915_gem_detach_phys_object(dev, phys_obj->cur_obj); | |
4159 | } | |
4160 | ||
4161 | #ifdef CONFIG_X86 | |
4162 | set_memory_wb((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE); | |
4163 | #endif | |
4164 | drm_pci_free(dev, phys_obj->handle); | |
4165 | kfree(phys_obj); | |
4166 | dev_priv->mm.phys_objs[id - 1] = NULL; | |
4167 | } | |
4168 | ||
4169 | void i915_gem_free_all_phys_object(struct drm_device *dev) | |
4170 | { | |
4171 | int i; | |
4172 | ||
260883c8 | 4173 | for (i = I915_GEM_PHYS_CURSOR_0; i <= I915_MAX_PHYS_OBJECT; i++) |
71acb5eb DA |
4174 | i915_gem_free_phys_object(dev, i); |
4175 | } | |
4176 | ||
4177 | void i915_gem_detach_phys_object(struct drm_device *dev, | |
05394f39 | 4178 | struct drm_i915_gem_object *obj) |
71acb5eb | 4179 | { |
05394f39 | 4180 | struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping; |
e5281ccd | 4181 | char *vaddr; |
71acb5eb | 4182 | int i; |
71acb5eb DA |
4183 | int page_count; |
4184 | ||
05394f39 | 4185 | if (!obj->phys_obj) |
71acb5eb | 4186 | return; |
05394f39 | 4187 | vaddr = obj->phys_obj->handle->vaddr; |
71acb5eb | 4188 | |
05394f39 | 4189 | page_count = obj->base.size / PAGE_SIZE; |
71acb5eb | 4190 | for (i = 0; i < page_count; i++) { |
5949eac4 | 4191 | struct page *page = shmem_read_mapping_page(mapping, i); |
e5281ccd CW |
4192 | if (!IS_ERR(page)) { |
4193 | char *dst = kmap_atomic(page); | |
4194 | memcpy(dst, vaddr + i*PAGE_SIZE, PAGE_SIZE); | |
4195 | kunmap_atomic(dst); | |
4196 | ||
4197 | drm_clflush_pages(&page, 1); | |
4198 | ||
4199 | set_page_dirty(page); | |
4200 | mark_page_accessed(page); | |
4201 | page_cache_release(page); | |
4202 | } | |
71acb5eb | 4203 | } |
e76e9aeb | 4204 | i915_gem_chipset_flush(dev); |
d78b47b9 | 4205 | |
05394f39 CW |
4206 | obj->phys_obj->cur_obj = NULL; |
4207 | obj->phys_obj = NULL; | |
71acb5eb DA |
4208 | } |
4209 | ||
4210 | int | |
4211 | i915_gem_attach_phys_object(struct drm_device *dev, | |
05394f39 | 4212 | struct drm_i915_gem_object *obj, |
6eeefaf3 CW |
4213 | int id, |
4214 | int align) | |
71acb5eb | 4215 | { |
05394f39 | 4216 | struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping; |
71acb5eb | 4217 | drm_i915_private_t *dev_priv = dev->dev_private; |
71acb5eb DA |
4218 | int ret = 0; |
4219 | int page_count; | |
4220 | int i; | |
4221 | ||
4222 | if (id > I915_MAX_PHYS_OBJECT) | |
4223 | return -EINVAL; | |
4224 | ||
05394f39 CW |
4225 | if (obj->phys_obj) { |
4226 | if (obj->phys_obj->id == id) | |
71acb5eb DA |
4227 | return 0; |
4228 | i915_gem_detach_phys_object(dev, obj); | |
4229 | } | |
4230 | ||
71acb5eb DA |
4231 | /* create a new object */ |
4232 | if (!dev_priv->mm.phys_objs[id - 1]) { | |
4233 | ret = i915_gem_init_phys_object(dev, id, | |
05394f39 | 4234 | obj->base.size, align); |
71acb5eb | 4235 | if (ret) { |
05394f39 CW |
4236 | DRM_ERROR("failed to init phys object %d size: %zu\n", |
4237 | id, obj->base.size); | |
e5281ccd | 4238 | return ret; |
71acb5eb DA |
4239 | } |
4240 | } | |
4241 | ||
4242 | /* bind to the object */ | |
05394f39 CW |
4243 | obj->phys_obj = dev_priv->mm.phys_objs[id - 1]; |
4244 | obj->phys_obj->cur_obj = obj; | |
71acb5eb | 4245 | |
05394f39 | 4246 | page_count = obj->base.size / PAGE_SIZE; |
71acb5eb DA |
4247 | |
4248 | for (i = 0; i < page_count; i++) { | |
e5281ccd CW |
4249 | struct page *page; |
4250 | char *dst, *src; | |
4251 | ||
5949eac4 | 4252 | page = shmem_read_mapping_page(mapping, i); |
e5281ccd CW |
4253 | if (IS_ERR(page)) |
4254 | return PTR_ERR(page); | |
71acb5eb | 4255 | |
ff75b9bc | 4256 | src = kmap_atomic(page); |
05394f39 | 4257 | dst = obj->phys_obj->handle->vaddr + (i * PAGE_SIZE); |
71acb5eb | 4258 | memcpy(dst, src, PAGE_SIZE); |
3e4d3af5 | 4259 | kunmap_atomic(src); |
71acb5eb | 4260 | |
e5281ccd CW |
4261 | mark_page_accessed(page); |
4262 | page_cache_release(page); | |
4263 | } | |
d78b47b9 | 4264 | |
71acb5eb | 4265 | return 0; |
71acb5eb DA |
4266 | } |
4267 | ||
4268 | static int | |
05394f39 CW |
4269 | i915_gem_phys_pwrite(struct drm_device *dev, |
4270 | struct drm_i915_gem_object *obj, | |
71acb5eb DA |
4271 | struct drm_i915_gem_pwrite *args, |
4272 | struct drm_file *file_priv) | |
4273 | { | |
05394f39 | 4274 | void *vaddr = obj->phys_obj->handle->vaddr + args->offset; |
b47b30cc | 4275 | char __user *user_data = (char __user *) (uintptr_t) args->data_ptr; |
71acb5eb | 4276 | |
b47b30cc CW |
4277 | if (__copy_from_user_inatomic_nocache(vaddr, user_data, args->size)) { |
4278 | unsigned long unwritten; | |
4279 | ||
4280 | /* The physical object once assigned is fixed for the lifetime | |
4281 | * of the obj, so we can safely drop the lock and continue | |
4282 | * to access vaddr. | |
4283 | */ | |
4284 | mutex_unlock(&dev->struct_mutex); | |
4285 | unwritten = copy_from_user(vaddr, user_data, args->size); | |
4286 | mutex_lock(&dev->struct_mutex); | |
4287 | if (unwritten) | |
4288 | return -EFAULT; | |
4289 | } | |
71acb5eb | 4290 | |
e76e9aeb | 4291 | i915_gem_chipset_flush(dev); |
71acb5eb DA |
4292 | return 0; |
4293 | } | |
b962442e | 4294 | |
f787a5f5 | 4295 | void i915_gem_release(struct drm_device *dev, struct drm_file *file) |
b962442e | 4296 | { |
f787a5f5 | 4297 | struct drm_i915_file_private *file_priv = file->driver_priv; |
b962442e EA |
4298 | |
4299 | /* Clean up our request list when the client is going away, so that | |
4300 | * later retire_requests won't dereference our soon-to-be-gone | |
4301 | * file_priv. | |
4302 | */ | |
1c25595f | 4303 | spin_lock(&file_priv->mm.lock); |
f787a5f5 CW |
4304 | while (!list_empty(&file_priv->mm.request_list)) { |
4305 | struct drm_i915_gem_request *request; | |
4306 | ||
4307 | request = list_first_entry(&file_priv->mm.request_list, | |
4308 | struct drm_i915_gem_request, | |
4309 | client_list); | |
4310 | list_del(&request->client_list); | |
4311 | request->file_priv = NULL; | |
4312 | } | |
1c25595f | 4313 | spin_unlock(&file_priv->mm.lock); |
b962442e | 4314 | } |
31169714 | 4315 | |
5774506f CW |
4316 | static bool mutex_is_locked_by(struct mutex *mutex, struct task_struct *task) |
4317 | { | |
4318 | if (!mutex_is_locked(mutex)) | |
4319 | return false; | |
4320 | ||
4321 | #if defined(CONFIG_SMP) || defined(CONFIG_DEBUG_MUTEXES) | |
4322 | return mutex->owner == task; | |
4323 | #else | |
4324 | /* Since UP may be pre-empted, we cannot assume that we own the lock */ | |
4325 | return false; | |
4326 | #endif | |
4327 | } | |
4328 | ||
31169714 | 4329 | static int |
1495f230 | 4330 | i915_gem_inactive_shrink(struct shrinker *shrinker, struct shrink_control *sc) |
31169714 | 4331 | { |
17250b71 CW |
4332 | struct drm_i915_private *dev_priv = |
4333 | container_of(shrinker, | |
4334 | struct drm_i915_private, | |
4335 | mm.inactive_shrinker); | |
4336 | struct drm_device *dev = dev_priv->dev; | |
6c085a72 | 4337 | struct drm_i915_gem_object *obj; |
1495f230 | 4338 | int nr_to_scan = sc->nr_to_scan; |
5774506f | 4339 | bool unlock = true; |
17250b71 CW |
4340 | int cnt; |
4341 | ||
5774506f CW |
4342 | if (!mutex_trylock(&dev->struct_mutex)) { |
4343 | if (!mutex_is_locked_by(&dev->struct_mutex, current)) | |
4344 | return 0; | |
4345 | ||
677feac2 DV |
4346 | if (dev_priv->mm.shrinker_no_lock_stealing) |
4347 | return 0; | |
4348 | ||
5774506f CW |
4349 | unlock = false; |
4350 | } | |
31169714 | 4351 | |
6c085a72 CW |
4352 | if (nr_to_scan) { |
4353 | nr_to_scan -= i915_gem_purge(dev_priv, nr_to_scan); | |
4354 | if (nr_to_scan > 0) | |
4355 | i915_gem_shrink_all(dev_priv); | |
31169714 CW |
4356 | } |
4357 | ||
17250b71 | 4358 | cnt = 0; |
6c085a72 | 4359 | list_for_each_entry(obj, &dev_priv->mm.unbound_list, gtt_list) |
a5570178 CW |
4360 | if (obj->pages_pin_count == 0) |
4361 | cnt += obj->base.size >> PAGE_SHIFT; | |
6c085a72 | 4362 | list_for_each_entry(obj, &dev_priv->mm.bound_list, gtt_list) |
a5570178 | 4363 | if (obj->pin_count == 0 && obj->pages_pin_count == 0) |
6c085a72 | 4364 | cnt += obj->base.size >> PAGE_SHIFT; |
17250b71 | 4365 | |
5774506f CW |
4366 | if (unlock) |
4367 | mutex_unlock(&dev->struct_mutex); | |
6c085a72 | 4368 | return cnt; |
31169714 | 4369 | } |