]>
Commit | Line | Data |
---|---|---|
673a394b EA |
1 | /* |
2 | * Copyright © 2008 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | * | |
26 | */ | |
27 | ||
28 | #include "drmP.h" | |
29 | #include "drm.h" | |
30 | #include "i915_drm.h" | |
31 | #include "i915_drv.h" | |
1c5d22f7 | 32 | #include "i915_trace.h" |
652c393a | 33 | #include "intel_drv.h" |
5949eac4 | 34 | #include <linux/shmem_fs.h> |
5a0e3ad6 | 35 | #include <linux/slab.h> |
673a394b | 36 | #include <linux/swap.h> |
79e53945 | 37 | #include <linux/pci.h> |
1286ff73 | 38 | #include <linux/dma-buf.h> |
673a394b | 39 | |
88241785 | 40 | static __must_check int i915_gem_object_flush_gpu_write_domain(struct drm_i915_gem_object *obj); |
05394f39 CW |
41 | static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj); |
42 | static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj); | |
88241785 CW |
43 | static __must_check int i915_gem_object_bind_to_gtt(struct drm_i915_gem_object *obj, |
44 | unsigned alignment, | |
45 | bool map_and_fenceable); | |
05394f39 CW |
46 | static int i915_gem_phys_pwrite(struct drm_device *dev, |
47 | struct drm_i915_gem_object *obj, | |
71acb5eb | 48 | struct drm_i915_gem_pwrite *args, |
05394f39 | 49 | struct drm_file *file); |
673a394b | 50 | |
61050808 CW |
51 | static void i915_gem_write_fence(struct drm_device *dev, int reg, |
52 | struct drm_i915_gem_object *obj); | |
53 | static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj, | |
54 | struct drm_i915_fence_reg *fence, | |
55 | bool enable); | |
56 | ||
17250b71 | 57 | static int i915_gem_inactive_shrink(struct shrinker *shrinker, |
1495f230 | 58 | struct shrink_control *sc); |
8c59967c | 59 | static void i915_gem_object_truncate(struct drm_i915_gem_object *obj); |
31169714 | 60 | |
61050808 CW |
61 | static inline void i915_gem_object_fence_lost(struct drm_i915_gem_object *obj) |
62 | { | |
63 | if (obj->tiling_mode) | |
64 | i915_gem_release_mmap(obj); | |
65 | ||
66 | /* As we do not have an associated fence register, we will force | |
67 | * a tiling change if we ever need to acquire one. | |
68 | */ | |
5d82e3e6 | 69 | obj->fence_dirty = false; |
61050808 CW |
70 | obj->fence_reg = I915_FENCE_REG_NONE; |
71 | } | |
72 | ||
73aa808f CW |
73 | /* some bookkeeping */ |
74 | static void i915_gem_info_add_obj(struct drm_i915_private *dev_priv, | |
75 | size_t size) | |
76 | { | |
77 | dev_priv->mm.object_count++; | |
78 | dev_priv->mm.object_memory += size; | |
79 | } | |
80 | ||
81 | static void i915_gem_info_remove_obj(struct drm_i915_private *dev_priv, | |
82 | size_t size) | |
83 | { | |
84 | dev_priv->mm.object_count--; | |
85 | dev_priv->mm.object_memory -= size; | |
86 | } | |
87 | ||
21dd3734 CW |
88 | static int |
89 | i915_gem_wait_for_error(struct drm_device *dev) | |
30dbf0c0 CW |
90 | { |
91 | struct drm_i915_private *dev_priv = dev->dev_private; | |
92 | struct completion *x = &dev_priv->error_completion; | |
93 | unsigned long flags; | |
94 | int ret; | |
95 | ||
96 | if (!atomic_read(&dev_priv->mm.wedged)) | |
97 | return 0; | |
98 | ||
99 | ret = wait_for_completion_interruptible(x); | |
100 | if (ret) | |
101 | return ret; | |
102 | ||
21dd3734 CW |
103 | if (atomic_read(&dev_priv->mm.wedged)) { |
104 | /* GPU is hung, bump the completion count to account for | |
105 | * the token we just consumed so that we never hit zero and | |
106 | * end up waiting upon a subsequent completion event that | |
107 | * will never happen. | |
108 | */ | |
109 | spin_lock_irqsave(&x->wait.lock, flags); | |
110 | x->done++; | |
111 | spin_unlock_irqrestore(&x->wait.lock, flags); | |
112 | } | |
113 | return 0; | |
30dbf0c0 CW |
114 | } |
115 | ||
54cf91dc | 116 | int i915_mutex_lock_interruptible(struct drm_device *dev) |
76c1dec1 | 117 | { |
76c1dec1 CW |
118 | int ret; |
119 | ||
21dd3734 | 120 | ret = i915_gem_wait_for_error(dev); |
76c1dec1 CW |
121 | if (ret) |
122 | return ret; | |
123 | ||
124 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
125 | if (ret) | |
126 | return ret; | |
127 | ||
23bc5982 | 128 | WARN_ON(i915_verify_lists(dev)); |
76c1dec1 CW |
129 | return 0; |
130 | } | |
30dbf0c0 | 131 | |
7d1c4804 | 132 | static inline bool |
05394f39 | 133 | i915_gem_object_is_inactive(struct drm_i915_gem_object *obj) |
7d1c4804 | 134 | { |
1b50247a | 135 | return !obj->active; |
7d1c4804 CW |
136 | } |
137 | ||
79e53945 JB |
138 | int |
139 | i915_gem_init_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 140 | struct drm_file *file) |
79e53945 JB |
141 | { |
142 | struct drm_i915_gem_init *args = data; | |
2021746e | 143 | |
7bb6fb8d DV |
144 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
145 | return -ENODEV; | |
146 | ||
2021746e CW |
147 | if (args->gtt_start >= args->gtt_end || |
148 | (args->gtt_end | args->gtt_start) & (PAGE_SIZE - 1)) | |
149 | return -EINVAL; | |
79e53945 | 150 | |
f534bc0b DV |
151 | /* GEM with user mode setting was never supported on ilk and later. */ |
152 | if (INTEL_INFO(dev)->gen >= 5) | |
153 | return -ENODEV; | |
154 | ||
79e53945 | 155 | mutex_lock(&dev->struct_mutex); |
644ec02b DV |
156 | i915_gem_init_global_gtt(dev, args->gtt_start, |
157 | args->gtt_end, args->gtt_end); | |
673a394b EA |
158 | mutex_unlock(&dev->struct_mutex); |
159 | ||
2021746e | 160 | return 0; |
673a394b EA |
161 | } |
162 | ||
5a125c3c EA |
163 | int |
164 | i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 165 | struct drm_file *file) |
5a125c3c | 166 | { |
73aa808f | 167 | struct drm_i915_private *dev_priv = dev->dev_private; |
5a125c3c | 168 | struct drm_i915_gem_get_aperture *args = data; |
6299f992 CW |
169 | struct drm_i915_gem_object *obj; |
170 | size_t pinned; | |
5a125c3c | 171 | |
6299f992 | 172 | pinned = 0; |
73aa808f | 173 | mutex_lock(&dev->struct_mutex); |
1b50247a CW |
174 | list_for_each_entry(obj, &dev_priv->mm.gtt_list, gtt_list) |
175 | if (obj->pin_count) | |
176 | pinned += obj->gtt_space->size; | |
73aa808f | 177 | mutex_unlock(&dev->struct_mutex); |
5a125c3c | 178 | |
6299f992 | 179 | args->aper_size = dev_priv->mm.gtt_total; |
0206e353 | 180 | args->aper_available_size = args->aper_size - pinned; |
6299f992 | 181 | |
5a125c3c EA |
182 | return 0; |
183 | } | |
184 | ||
ff72145b DA |
185 | static int |
186 | i915_gem_create(struct drm_file *file, | |
187 | struct drm_device *dev, | |
188 | uint64_t size, | |
189 | uint32_t *handle_p) | |
673a394b | 190 | { |
05394f39 | 191 | struct drm_i915_gem_object *obj; |
a1a2d1d3 PP |
192 | int ret; |
193 | u32 handle; | |
673a394b | 194 | |
ff72145b | 195 | size = roundup(size, PAGE_SIZE); |
8ffc0246 CW |
196 | if (size == 0) |
197 | return -EINVAL; | |
673a394b EA |
198 | |
199 | /* Allocate the new object */ | |
ff72145b | 200 | obj = i915_gem_alloc_object(dev, size); |
673a394b EA |
201 | if (obj == NULL) |
202 | return -ENOMEM; | |
203 | ||
05394f39 | 204 | ret = drm_gem_handle_create(file, &obj->base, &handle); |
1dfd9754 | 205 | if (ret) { |
05394f39 CW |
206 | drm_gem_object_release(&obj->base); |
207 | i915_gem_info_remove_obj(dev->dev_private, obj->base.size); | |
202f2fef | 208 | kfree(obj); |
673a394b | 209 | return ret; |
1dfd9754 | 210 | } |
673a394b | 211 | |
202f2fef | 212 | /* drop reference from allocate - handle holds it now */ |
05394f39 | 213 | drm_gem_object_unreference(&obj->base); |
202f2fef CW |
214 | trace_i915_gem_object_create(obj); |
215 | ||
ff72145b | 216 | *handle_p = handle; |
673a394b EA |
217 | return 0; |
218 | } | |
219 | ||
ff72145b DA |
220 | int |
221 | i915_gem_dumb_create(struct drm_file *file, | |
222 | struct drm_device *dev, | |
223 | struct drm_mode_create_dumb *args) | |
224 | { | |
225 | /* have to work out size/pitch and return them */ | |
ed0291fd | 226 | args->pitch = ALIGN(args->width * ((args->bpp + 7) / 8), 64); |
ff72145b DA |
227 | args->size = args->pitch * args->height; |
228 | return i915_gem_create(file, dev, | |
229 | args->size, &args->handle); | |
230 | } | |
231 | ||
232 | int i915_gem_dumb_destroy(struct drm_file *file, | |
233 | struct drm_device *dev, | |
234 | uint32_t handle) | |
235 | { | |
236 | return drm_gem_handle_delete(file, handle); | |
237 | } | |
238 | ||
239 | /** | |
240 | * Creates a new mm object and returns a handle to it. | |
241 | */ | |
242 | int | |
243 | i915_gem_create_ioctl(struct drm_device *dev, void *data, | |
244 | struct drm_file *file) | |
245 | { | |
246 | struct drm_i915_gem_create *args = data; | |
63ed2cb2 | 247 | |
ff72145b DA |
248 | return i915_gem_create(file, dev, |
249 | args->size, &args->handle); | |
250 | } | |
251 | ||
05394f39 | 252 | static int i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj) |
280b713b | 253 | { |
05394f39 | 254 | drm_i915_private_t *dev_priv = obj->base.dev->dev_private; |
280b713b EA |
255 | |
256 | return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 && | |
05394f39 | 257 | obj->tiling_mode != I915_TILING_NONE; |
280b713b EA |
258 | } |
259 | ||
8461d226 DV |
260 | static inline int |
261 | __copy_to_user_swizzled(char __user *cpu_vaddr, | |
262 | const char *gpu_vaddr, int gpu_offset, | |
263 | int length) | |
264 | { | |
265 | int ret, cpu_offset = 0; | |
266 | ||
267 | while (length > 0) { | |
268 | int cacheline_end = ALIGN(gpu_offset + 1, 64); | |
269 | int this_length = min(cacheline_end - gpu_offset, length); | |
270 | int swizzled_gpu_offset = gpu_offset ^ 64; | |
271 | ||
272 | ret = __copy_to_user(cpu_vaddr + cpu_offset, | |
273 | gpu_vaddr + swizzled_gpu_offset, | |
274 | this_length); | |
275 | if (ret) | |
276 | return ret + length; | |
277 | ||
278 | cpu_offset += this_length; | |
279 | gpu_offset += this_length; | |
280 | length -= this_length; | |
281 | } | |
282 | ||
283 | return 0; | |
284 | } | |
285 | ||
8c59967c | 286 | static inline int |
4f0c7cfb BW |
287 | __copy_from_user_swizzled(char *gpu_vaddr, int gpu_offset, |
288 | const char __user *cpu_vaddr, | |
8c59967c DV |
289 | int length) |
290 | { | |
291 | int ret, cpu_offset = 0; | |
292 | ||
293 | while (length > 0) { | |
294 | int cacheline_end = ALIGN(gpu_offset + 1, 64); | |
295 | int this_length = min(cacheline_end - gpu_offset, length); | |
296 | int swizzled_gpu_offset = gpu_offset ^ 64; | |
297 | ||
298 | ret = __copy_from_user(gpu_vaddr + swizzled_gpu_offset, | |
299 | cpu_vaddr + cpu_offset, | |
300 | this_length); | |
301 | if (ret) | |
302 | return ret + length; | |
303 | ||
304 | cpu_offset += this_length; | |
305 | gpu_offset += this_length; | |
306 | length -= this_length; | |
307 | } | |
308 | ||
309 | return 0; | |
310 | } | |
311 | ||
d174bd64 DV |
312 | /* Per-page copy function for the shmem pread fastpath. |
313 | * Flushes invalid cachelines before reading the target if | |
314 | * needs_clflush is set. */ | |
eb01459f | 315 | static int |
d174bd64 DV |
316 | shmem_pread_fast(struct page *page, int shmem_page_offset, int page_length, |
317 | char __user *user_data, | |
318 | bool page_do_bit17_swizzling, bool needs_clflush) | |
319 | { | |
320 | char *vaddr; | |
321 | int ret; | |
322 | ||
e7e58eb5 | 323 | if (unlikely(page_do_bit17_swizzling)) |
d174bd64 DV |
324 | return -EINVAL; |
325 | ||
326 | vaddr = kmap_atomic(page); | |
327 | if (needs_clflush) | |
328 | drm_clflush_virt_range(vaddr + shmem_page_offset, | |
329 | page_length); | |
330 | ret = __copy_to_user_inatomic(user_data, | |
331 | vaddr + shmem_page_offset, | |
332 | page_length); | |
333 | kunmap_atomic(vaddr); | |
334 | ||
335 | return ret; | |
336 | } | |
337 | ||
23c18c71 DV |
338 | static void |
339 | shmem_clflush_swizzled_range(char *addr, unsigned long length, | |
340 | bool swizzled) | |
341 | { | |
e7e58eb5 | 342 | if (unlikely(swizzled)) { |
23c18c71 DV |
343 | unsigned long start = (unsigned long) addr; |
344 | unsigned long end = (unsigned long) addr + length; | |
345 | ||
346 | /* For swizzling simply ensure that we always flush both | |
347 | * channels. Lame, but simple and it works. Swizzled | |
348 | * pwrite/pread is far from a hotpath - current userspace | |
349 | * doesn't use it at all. */ | |
350 | start = round_down(start, 128); | |
351 | end = round_up(end, 128); | |
352 | ||
353 | drm_clflush_virt_range((void *)start, end - start); | |
354 | } else { | |
355 | drm_clflush_virt_range(addr, length); | |
356 | } | |
357 | ||
358 | } | |
359 | ||
d174bd64 DV |
360 | /* Only difference to the fast-path function is that this can handle bit17 |
361 | * and uses non-atomic copy and kmap functions. */ | |
362 | static int | |
363 | shmem_pread_slow(struct page *page, int shmem_page_offset, int page_length, | |
364 | char __user *user_data, | |
365 | bool page_do_bit17_swizzling, bool needs_clflush) | |
366 | { | |
367 | char *vaddr; | |
368 | int ret; | |
369 | ||
370 | vaddr = kmap(page); | |
371 | if (needs_clflush) | |
23c18c71 DV |
372 | shmem_clflush_swizzled_range(vaddr + shmem_page_offset, |
373 | page_length, | |
374 | page_do_bit17_swizzling); | |
d174bd64 DV |
375 | |
376 | if (page_do_bit17_swizzling) | |
377 | ret = __copy_to_user_swizzled(user_data, | |
378 | vaddr, shmem_page_offset, | |
379 | page_length); | |
380 | else | |
381 | ret = __copy_to_user(user_data, | |
382 | vaddr + shmem_page_offset, | |
383 | page_length); | |
384 | kunmap(page); | |
385 | ||
386 | return ret; | |
387 | } | |
388 | ||
eb01459f | 389 | static int |
dbf7bff0 DV |
390 | i915_gem_shmem_pread(struct drm_device *dev, |
391 | struct drm_i915_gem_object *obj, | |
392 | struct drm_i915_gem_pread *args, | |
393 | struct drm_file *file) | |
eb01459f | 394 | { |
05394f39 | 395 | struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping; |
8461d226 | 396 | char __user *user_data; |
eb01459f | 397 | ssize_t remain; |
8461d226 | 398 | loff_t offset; |
eb2c0c81 | 399 | int shmem_page_offset, page_length, ret = 0; |
8461d226 | 400 | int obj_do_bit17_swizzling, page_do_bit17_swizzling; |
dbf7bff0 | 401 | int hit_slowpath = 0; |
96d79b52 | 402 | int prefaulted = 0; |
8489731c | 403 | int needs_clflush = 0; |
692a576b | 404 | int release_page; |
eb01459f | 405 | |
8461d226 | 406 | user_data = (char __user *) (uintptr_t) args->data_ptr; |
eb01459f EA |
407 | remain = args->size; |
408 | ||
8461d226 | 409 | obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj); |
eb01459f | 410 | |
8489731c DV |
411 | if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU)) { |
412 | /* If we're not in the cpu read domain, set ourself into the gtt | |
413 | * read domain and manually flush cachelines (if required). This | |
414 | * optimizes for the case when the gpu will dirty the data | |
415 | * anyway again before the next pread happens. */ | |
416 | if (obj->cache_level == I915_CACHE_NONE) | |
417 | needs_clflush = 1; | |
418 | ret = i915_gem_object_set_to_gtt_domain(obj, false); | |
419 | if (ret) | |
420 | return ret; | |
421 | } | |
eb01459f | 422 | |
8461d226 | 423 | offset = args->offset; |
eb01459f EA |
424 | |
425 | while (remain > 0) { | |
e5281ccd CW |
426 | struct page *page; |
427 | ||
eb01459f EA |
428 | /* Operation in this page |
429 | * | |
eb01459f | 430 | * shmem_page_offset = offset within page in shmem file |
eb01459f EA |
431 | * page_length = bytes to copy for this page |
432 | */ | |
c8cbbb8b | 433 | shmem_page_offset = offset_in_page(offset); |
eb01459f EA |
434 | page_length = remain; |
435 | if ((shmem_page_offset + page_length) > PAGE_SIZE) | |
436 | page_length = PAGE_SIZE - shmem_page_offset; | |
eb01459f | 437 | |
692a576b DV |
438 | if (obj->pages) { |
439 | page = obj->pages[offset >> PAGE_SHIFT]; | |
440 | release_page = 0; | |
441 | } else { | |
442 | page = shmem_read_mapping_page(mapping, offset >> PAGE_SHIFT); | |
443 | if (IS_ERR(page)) { | |
444 | ret = PTR_ERR(page); | |
445 | goto out; | |
446 | } | |
447 | release_page = 1; | |
b65552f0 | 448 | } |
e5281ccd | 449 | |
8461d226 DV |
450 | page_do_bit17_swizzling = obj_do_bit17_swizzling && |
451 | (page_to_phys(page) & (1 << 17)) != 0; | |
452 | ||
d174bd64 DV |
453 | ret = shmem_pread_fast(page, shmem_page_offset, page_length, |
454 | user_data, page_do_bit17_swizzling, | |
455 | needs_clflush); | |
456 | if (ret == 0) | |
457 | goto next_page; | |
dbf7bff0 DV |
458 | |
459 | hit_slowpath = 1; | |
692a576b | 460 | page_cache_get(page); |
dbf7bff0 DV |
461 | mutex_unlock(&dev->struct_mutex); |
462 | ||
96d79b52 | 463 | if (!prefaulted) { |
f56f821f | 464 | ret = fault_in_multipages_writeable(user_data, remain); |
96d79b52 DV |
465 | /* Userspace is tricking us, but we've already clobbered |
466 | * its pages with the prefault and promised to write the | |
467 | * data up to the first fault. Hence ignore any errors | |
468 | * and just continue. */ | |
469 | (void)ret; | |
470 | prefaulted = 1; | |
471 | } | |
eb01459f | 472 | |
d174bd64 DV |
473 | ret = shmem_pread_slow(page, shmem_page_offset, page_length, |
474 | user_data, page_do_bit17_swizzling, | |
475 | needs_clflush); | |
eb01459f | 476 | |
dbf7bff0 | 477 | mutex_lock(&dev->struct_mutex); |
e5281ccd | 478 | page_cache_release(page); |
dbf7bff0 | 479 | next_page: |
e5281ccd | 480 | mark_page_accessed(page); |
692a576b DV |
481 | if (release_page) |
482 | page_cache_release(page); | |
e5281ccd | 483 | |
8461d226 DV |
484 | if (ret) { |
485 | ret = -EFAULT; | |
486 | goto out; | |
487 | } | |
488 | ||
eb01459f | 489 | remain -= page_length; |
8461d226 | 490 | user_data += page_length; |
eb01459f EA |
491 | offset += page_length; |
492 | } | |
493 | ||
4f27b75d | 494 | out: |
dbf7bff0 DV |
495 | if (hit_slowpath) { |
496 | /* Fixup: Kill any reinstated backing storage pages */ | |
497 | if (obj->madv == __I915_MADV_PURGED) | |
498 | i915_gem_object_truncate(obj); | |
499 | } | |
eb01459f EA |
500 | |
501 | return ret; | |
502 | } | |
503 | ||
673a394b EA |
504 | /** |
505 | * Reads data from the object referenced by handle. | |
506 | * | |
507 | * On error, the contents of *data are undefined. | |
508 | */ | |
509 | int | |
510 | i915_gem_pread_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 511 | struct drm_file *file) |
673a394b EA |
512 | { |
513 | struct drm_i915_gem_pread *args = data; | |
05394f39 | 514 | struct drm_i915_gem_object *obj; |
35b62a89 | 515 | int ret = 0; |
673a394b | 516 | |
51311d0a CW |
517 | if (args->size == 0) |
518 | return 0; | |
519 | ||
520 | if (!access_ok(VERIFY_WRITE, | |
521 | (char __user *)(uintptr_t)args->data_ptr, | |
522 | args->size)) | |
523 | return -EFAULT; | |
524 | ||
4f27b75d | 525 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 526 | if (ret) |
4f27b75d | 527 | return ret; |
673a394b | 528 | |
05394f39 | 529 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 530 | if (&obj->base == NULL) { |
1d7cfea1 CW |
531 | ret = -ENOENT; |
532 | goto unlock; | |
4f27b75d | 533 | } |
673a394b | 534 | |
7dcd2499 | 535 | /* Bounds check source. */ |
05394f39 CW |
536 | if (args->offset > obj->base.size || |
537 | args->size > obj->base.size - args->offset) { | |
ce9d419d | 538 | ret = -EINVAL; |
35b62a89 | 539 | goto out; |
ce9d419d CW |
540 | } |
541 | ||
1286ff73 DV |
542 | /* prime objects have no backing filp to GEM pread/pwrite |
543 | * pages from. | |
544 | */ | |
545 | if (!obj->base.filp) { | |
546 | ret = -EINVAL; | |
547 | goto out; | |
548 | } | |
549 | ||
db53a302 CW |
550 | trace_i915_gem_object_pread(obj, args->offset, args->size); |
551 | ||
dbf7bff0 | 552 | ret = i915_gem_shmem_pread(dev, obj, args, file); |
673a394b | 553 | |
35b62a89 | 554 | out: |
05394f39 | 555 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 556 | unlock: |
4f27b75d | 557 | mutex_unlock(&dev->struct_mutex); |
eb01459f | 558 | return ret; |
673a394b EA |
559 | } |
560 | ||
0839ccb8 KP |
561 | /* This is the fast write path which cannot handle |
562 | * page faults in the source data | |
9b7530cc | 563 | */ |
0839ccb8 KP |
564 | |
565 | static inline int | |
566 | fast_user_write(struct io_mapping *mapping, | |
567 | loff_t page_base, int page_offset, | |
568 | char __user *user_data, | |
569 | int length) | |
9b7530cc | 570 | { |
4f0c7cfb BW |
571 | void __iomem *vaddr_atomic; |
572 | void *vaddr; | |
0839ccb8 | 573 | unsigned long unwritten; |
9b7530cc | 574 | |
3e4d3af5 | 575 | vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base); |
4f0c7cfb BW |
576 | /* We can use the cpu mem copy function because this is X86. */ |
577 | vaddr = (void __force*)vaddr_atomic + page_offset; | |
578 | unwritten = __copy_from_user_inatomic_nocache(vaddr, | |
0839ccb8 | 579 | user_data, length); |
3e4d3af5 | 580 | io_mapping_unmap_atomic(vaddr_atomic); |
fbd5a26d | 581 | return unwritten; |
0839ccb8 KP |
582 | } |
583 | ||
3de09aa3 EA |
584 | /** |
585 | * This is the fast pwrite path, where we copy the data directly from the | |
586 | * user into the GTT, uncached. | |
587 | */ | |
673a394b | 588 | static int |
05394f39 CW |
589 | i915_gem_gtt_pwrite_fast(struct drm_device *dev, |
590 | struct drm_i915_gem_object *obj, | |
3de09aa3 | 591 | struct drm_i915_gem_pwrite *args, |
05394f39 | 592 | struct drm_file *file) |
673a394b | 593 | { |
0839ccb8 | 594 | drm_i915_private_t *dev_priv = dev->dev_private; |
673a394b | 595 | ssize_t remain; |
0839ccb8 | 596 | loff_t offset, page_base; |
673a394b | 597 | char __user *user_data; |
935aaa69 DV |
598 | int page_offset, page_length, ret; |
599 | ||
600 | ret = i915_gem_object_pin(obj, 0, true); | |
601 | if (ret) | |
602 | goto out; | |
603 | ||
604 | ret = i915_gem_object_set_to_gtt_domain(obj, true); | |
605 | if (ret) | |
606 | goto out_unpin; | |
607 | ||
608 | ret = i915_gem_object_put_fence(obj); | |
609 | if (ret) | |
610 | goto out_unpin; | |
673a394b EA |
611 | |
612 | user_data = (char __user *) (uintptr_t) args->data_ptr; | |
613 | remain = args->size; | |
673a394b | 614 | |
05394f39 | 615 | offset = obj->gtt_offset + args->offset; |
673a394b EA |
616 | |
617 | while (remain > 0) { | |
618 | /* Operation in this page | |
619 | * | |
0839ccb8 KP |
620 | * page_base = page offset within aperture |
621 | * page_offset = offset within page | |
622 | * page_length = bytes to copy for this page | |
673a394b | 623 | */ |
c8cbbb8b CW |
624 | page_base = offset & PAGE_MASK; |
625 | page_offset = offset_in_page(offset); | |
0839ccb8 KP |
626 | page_length = remain; |
627 | if ((page_offset + remain) > PAGE_SIZE) | |
628 | page_length = PAGE_SIZE - page_offset; | |
629 | ||
0839ccb8 | 630 | /* If we get a fault while copying data, then (presumably) our |
3de09aa3 EA |
631 | * source page isn't available. Return the error and we'll |
632 | * retry in the slow path. | |
0839ccb8 | 633 | */ |
fbd5a26d | 634 | if (fast_user_write(dev_priv->mm.gtt_mapping, page_base, |
935aaa69 DV |
635 | page_offset, user_data, page_length)) { |
636 | ret = -EFAULT; | |
637 | goto out_unpin; | |
638 | } | |
673a394b | 639 | |
0839ccb8 KP |
640 | remain -= page_length; |
641 | user_data += page_length; | |
642 | offset += page_length; | |
673a394b | 643 | } |
673a394b | 644 | |
935aaa69 DV |
645 | out_unpin: |
646 | i915_gem_object_unpin(obj); | |
647 | out: | |
3de09aa3 | 648 | return ret; |
673a394b EA |
649 | } |
650 | ||
d174bd64 DV |
651 | /* Per-page copy function for the shmem pwrite fastpath. |
652 | * Flushes invalid cachelines before writing to the target if | |
653 | * needs_clflush_before is set and flushes out any written cachelines after | |
654 | * writing if needs_clflush is set. */ | |
3043c60c | 655 | static int |
d174bd64 DV |
656 | shmem_pwrite_fast(struct page *page, int shmem_page_offset, int page_length, |
657 | char __user *user_data, | |
658 | bool page_do_bit17_swizzling, | |
659 | bool needs_clflush_before, | |
660 | bool needs_clflush_after) | |
673a394b | 661 | { |
d174bd64 | 662 | char *vaddr; |
673a394b | 663 | int ret; |
3de09aa3 | 664 | |
e7e58eb5 | 665 | if (unlikely(page_do_bit17_swizzling)) |
d174bd64 | 666 | return -EINVAL; |
3de09aa3 | 667 | |
d174bd64 DV |
668 | vaddr = kmap_atomic(page); |
669 | if (needs_clflush_before) | |
670 | drm_clflush_virt_range(vaddr + shmem_page_offset, | |
671 | page_length); | |
672 | ret = __copy_from_user_inatomic_nocache(vaddr + shmem_page_offset, | |
673 | user_data, | |
674 | page_length); | |
675 | if (needs_clflush_after) | |
676 | drm_clflush_virt_range(vaddr + shmem_page_offset, | |
677 | page_length); | |
678 | kunmap_atomic(vaddr); | |
3de09aa3 EA |
679 | |
680 | return ret; | |
681 | } | |
682 | ||
d174bd64 DV |
683 | /* Only difference to the fast-path function is that this can handle bit17 |
684 | * and uses non-atomic copy and kmap functions. */ | |
3043c60c | 685 | static int |
d174bd64 DV |
686 | shmem_pwrite_slow(struct page *page, int shmem_page_offset, int page_length, |
687 | char __user *user_data, | |
688 | bool page_do_bit17_swizzling, | |
689 | bool needs_clflush_before, | |
690 | bool needs_clflush_after) | |
673a394b | 691 | { |
d174bd64 DV |
692 | char *vaddr; |
693 | int ret; | |
e5281ccd | 694 | |
d174bd64 | 695 | vaddr = kmap(page); |
e7e58eb5 | 696 | if (unlikely(needs_clflush_before || page_do_bit17_swizzling)) |
23c18c71 DV |
697 | shmem_clflush_swizzled_range(vaddr + shmem_page_offset, |
698 | page_length, | |
699 | page_do_bit17_swizzling); | |
d174bd64 DV |
700 | if (page_do_bit17_swizzling) |
701 | ret = __copy_from_user_swizzled(vaddr, shmem_page_offset, | |
e5281ccd CW |
702 | user_data, |
703 | page_length); | |
d174bd64 DV |
704 | else |
705 | ret = __copy_from_user(vaddr + shmem_page_offset, | |
706 | user_data, | |
707 | page_length); | |
708 | if (needs_clflush_after) | |
23c18c71 DV |
709 | shmem_clflush_swizzled_range(vaddr + shmem_page_offset, |
710 | page_length, | |
711 | page_do_bit17_swizzling); | |
d174bd64 | 712 | kunmap(page); |
40123c1f | 713 | |
d174bd64 | 714 | return ret; |
40123c1f EA |
715 | } |
716 | ||
40123c1f | 717 | static int |
e244a443 DV |
718 | i915_gem_shmem_pwrite(struct drm_device *dev, |
719 | struct drm_i915_gem_object *obj, | |
720 | struct drm_i915_gem_pwrite *args, | |
721 | struct drm_file *file) | |
40123c1f | 722 | { |
05394f39 | 723 | struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping; |
40123c1f | 724 | ssize_t remain; |
8c59967c DV |
725 | loff_t offset; |
726 | char __user *user_data; | |
eb2c0c81 | 727 | int shmem_page_offset, page_length, ret = 0; |
8c59967c | 728 | int obj_do_bit17_swizzling, page_do_bit17_swizzling; |
e244a443 | 729 | int hit_slowpath = 0; |
58642885 DV |
730 | int needs_clflush_after = 0; |
731 | int needs_clflush_before = 0; | |
692a576b | 732 | int release_page; |
40123c1f | 733 | |
8c59967c | 734 | user_data = (char __user *) (uintptr_t) args->data_ptr; |
40123c1f EA |
735 | remain = args->size; |
736 | ||
8c59967c | 737 | obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj); |
40123c1f | 738 | |
58642885 DV |
739 | if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) { |
740 | /* If we're not in the cpu write domain, set ourself into the gtt | |
741 | * write domain and manually flush cachelines (if required). This | |
742 | * optimizes for the case when the gpu will use the data | |
743 | * right away and we therefore have to clflush anyway. */ | |
744 | if (obj->cache_level == I915_CACHE_NONE) | |
745 | needs_clflush_after = 1; | |
746 | ret = i915_gem_object_set_to_gtt_domain(obj, true); | |
747 | if (ret) | |
748 | return ret; | |
749 | } | |
750 | /* Same trick applies for invalidate partially written cachelines before | |
751 | * writing. */ | |
752 | if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU) | |
753 | && obj->cache_level == I915_CACHE_NONE) | |
754 | needs_clflush_before = 1; | |
755 | ||
673a394b | 756 | offset = args->offset; |
05394f39 | 757 | obj->dirty = 1; |
673a394b | 758 | |
40123c1f | 759 | while (remain > 0) { |
e5281ccd | 760 | struct page *page; |
58642885 | 761 | int partial_cacheline_write; |
e5281ccd | 762 | |
40123c1f EA |
763 | /* Operation in this page |
764 | * | |
40123c1f | 765 | * shmem_page_offset = offset within page in shmem file |
40123c1f EA |
766 | * page_length = bytes to copy for this page |
767 | */ | |
c8cbbb8b | 768 | shmem_page_offset = offset_in_page(offset); |
40123c1f EA |
769 | |
770 | page_length = remain; | |
771 | if ((shmem_page_offset + page_length) > PAGE_SIZE) | |
772 | page_length = PAGE_SIZE - shmem_page_offset; | |
40123c1f | 773 | |
58642885 DV |
774 | /* If we don't overwrite a cacheline completely we need to be |
775 | * careful to have up-to-date data by first clflushing. Don't | |
776 | * overcomplicate things and flush the entire patch. */ | |
777 | partial_cacheline_write = needs_clflush_before && | |
778 | ((shmem_page_offset | page_length) | |
779 | & (boot_cpu_data.x86_clflush_size - 1)); | |
780 | ||
692a576b DV |
781 | if (obj->pages) { |
782 | page = obj->pages[offset >> PAGE_SHIFT]; | |
783 | release_page = 0; | |
784 | } else { | |
785 | page = shmem_read_mapping_page(mapping, offset >> PAGE_SHIFT); | |
786 | if (IS_ERR(page)) { | |
787 | ret = PTR_ERR(page); | |
788 | goto out; | |
789 | } | |
790 | release_page = 1; | |
e5281ccd CW |
791 | } |
792 | ||
8c59967c DV |
793 | page_do_bit17_swizzling = obj_do_bit17_swizzling && |
794 | (page_to_phys(page) & (1 << 17)) != 0; | |
795 | ||
d174bd64 DV |
796 | ret = shmem_pwrite_fast(page, shmem_page_offset, page_length, |
797 | user_data, page_do_bit17_swizzling, | |
798 | partial_cacheline_write, | |
799 | needs_clflush_after); | |
800 | if (ret == 0) | |
801 | goto next_page; | |
e244a443 DV |
802 | |
803 | hit_slowpath = 1; | |
692a576b | 804 | page_cache_get(page); |
e244a443 DV |
805 | mutex_unlock(&dev->struct_mutex); |
806 | ||
d174bd64 DV |
807 | ret = shmem_pwrite_slow(page, shmem_page_offset, page_length, |
808 | user_data, page_do_bit17_swizzling, | |
809 | partial_cacheline_write, | |
810 | needs_clflush_after); | |
40123c1f | 811 | |
e244a443 | 812 | mutex_lock(&dev->struct_mutex); |
692a576b | 813 | page_cache_release(page); |
e244a443 | 814 | next_page: |
e5281ccd CW |
815 | set_page_dirty(page); |
816 | mark_page_accessed(page); | |
692a576b DV |
817 | if (release_page) |
818 | page_cache_release(page); | |
e5281ccd | 819 | |
8c59967c DV |
820 | if (ret) { |
821 | ret = -EFAULT; | |
822 | goto out; | |
823 | } | |
824 | ||
40123c1f | 825 | remain -= page_length; |
8c59967c | 826 | user_data += page_length; |
40123c1f | 827 | offset += page_length; |
673a394b EA |
828 | } |
829 | ||
fbd5a26d | 830 | out: |
e244a443 DV |
831 | if (hit_slowpath) { |
832 | /* Fixup: Kill any reinstated backing storage pages */ | |
833 | if (obj->madv == __I915_MADV_PURGED) | |
834 | i915_gem_object_truncate(obj); | |
835 | /* and flush dirty cachelines in case the object isn't in the cpu write | |
836 | * domain anymore. */ | |
837 | if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) { | |
838 | i915_gem_clflush_object(obj); | |
839 | intel_gtt_chipset_flush(); | |
840 | } | |
8c59967c | 841 | } |
673a394b | 842 | |
58642885 DV |
843 | if (needs_clflush_after) |
844 | intel_gtt_chipset_flush(); | |
845 | ||
40123c1f | 846 | return ret; |
673a394b EA |
847 | } |
848 | ||
849 | /** | |
850 | * Writes data to the object referenced by handle. | |
851 | * | |
852 | * On error, the contents of the buffer that were to be modified are undefined. | |
853 | */ | |
854 | int | |
855 | i915_gem_pwrite_ioctl(struct drm_device *dev, void *data, | |
fbd5a26d | 856 | struct drm_file *file) |
673a394b EA |
857 | { |
858 | struct drm_i915_gem_pwrite *args = data; | |
05394f39 | 859 | struct drm_i915_gem_object *obj; |
51311d0a CW |
860 | int ret; |
861 | ||
862 | if (args->size == 0) | |
863 | return 0; | |
864 | ||
865 | if (!access_ok(VERIFY_READ, | |
866 | (char __user *)(uintptr_t)args->data_ptr, | |
867 | args->size)) | |
868 | return -EFAULT; | |
869 | ||
f56f821f DV |
870 | ret = fault_in_multipages_readable((char __user *)(uintptr_t)args->data_ptr, |
871 | args->size); | |
51311d0a CW |
872 | if (ret) |
873 | return -EFAULT; | |
673a394b | 874 | |
fbd5a26d | 875 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 876 | if (ret) |
fbd5a26d | 877 | return ret; |
1d7cfea1 | 878 | |
05394f39 | 879 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 880 | if (&obj->base == NULL) { |
1d7cfea1 CW |
881 | ret = -ENOENT; |
882 | goto unlock; | |
fbd5a26d | 883 | } |
673a394b | 884 | |
7dcd2499 | 885 | /* Bounds check destination. */ |
05394f39 CW |
886 | if (args->offset > obj->base.size || |
887 | args->size > obj->base.size - args->offset) { | |
ce9d419d | 888 | ret = -EINVAL; |
35b62a89 | 889 | goto out; |
ce9d419d CW |
890 | } |
891 | ||
1286ff73 DV |
892 | /* prime objects have no backing filp to GEM pread/pwrite |
893 | * pages from. | |
894 | */ | |
895 | if (!obj->base.filp) { | |
896 | ret = -EINVAL; | |
897 | goto out; | |
898 | } | |
899 | ||
db53a302 CW |
900 | trace_i915_gem_object_pwrite(obj, args->offset, args->size); |
901 | ||
935aaa69 | 902 | ret = -EFAULT; |
673a394b EA |
903 | /* We can only do the GTT pwrite on untiled buffers, as otherwise |
904 | * it would end up going through the fenced access, and we'll get | |
905 | * different detiling behavior between reading and writing. | |
906 | * pread/pwrite currently are reading and writing from the CPU | |
907 | * perspective, requiring manual detiling by the client. | |
908 | */ | |
5c0480f2 | 909 | if (obj->phys_obj) { |
fbd5a26d | 910 | ret = i915_gem_phys_pwrite(dev, obj, args, file); |
5c0480f2 DV |
911 | goto out; |
912 | } | |
913 | ||
914 | if (obj->gtt_space && | |
3ae53783 | 915 | obj->cache_level == I915_CACHE_NONE && |
c07496fa | 916 | obj->tiling_mode == I915_TILING_NONE && |
ffc62976 | 917 | obj->map_and_fenceable && |
5c0480f2 | 918 | obj->base.write_domain != I915_GEM_DOMAIN_CPU) { |
fbd5a26d | 919 | ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file); |
935aaa69 DV |
920 | /* Note that the gtt paths might fail with non-page-backed user |
921 | * pointers (e.g. gtt mappings when moving data between | |
922 | * textures). Fallback to the shmem path in that case. */ | |
fbd5a26d | 923 | } |
673a394b | 924 | |
5c0480f2 | 925 | if (ret == -EFAULT) |
935aaa69 | 926 | ret = i915_gem_shmem_pwrite(dev, obj, args, file); |
5c0480f2 | 927 | |
35b62a89 | 928 | out: |
05394f39 | 929 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 930 | unlock: |
fbd5a26d | 931 | mutex_unlock(&dev->struct_mutex); |
673a394b EA |
932 | return ret; |
933 | } | |
934 | ||
935 | /** | |
2ef7eeaa EA |
936 | * Called when user space prepares to use an object with the CPU, either |
937 | * through the mmap ioctl's mapping or a GTT mapping. | |
673a394b EA |
938 | */ |
939 | int | |
940 | i915_gem_set_domain_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 941 | struct drm_file *file) |
673a394b EA |
942 | { |
943 | struct drm_i915_gem_set_domain *args = data; | |
05394f39 | 944 | struct drm_i915_gem_object *obj; |
2ef7eeaa EA |
945 | uint32_t read_domains = args->read_domains; |
946 | uint32_t write_domain = args->write_domain; | |
673a394b EA |
947 | int ret; |
948 | ||
2ef7eeaa | 949 | /* Only handle setting domains to types used by the CPU. */ |
21d509e3 | 950 | if (write_domain & I915_GEM_GPU_DOMAINS) |
2ef7eeaa EA |
951 | return -EINVAL; |
952 | ||
21d509e3 | 953 | if (read_domains & I915_GEM_GPU_DOMAINS) |
2ef7eeaa EA |
954 | return -EINVAL; |
955 | ||
956 | /* Having something in the write domain implies it's in the read | |
957 | * domain, and only that read domain. Enforce that in the request. | |
958 | */ | |
959 | if (write_domain != 0 && read_domains != write_domain) | |
960 | return -EINVAL; | |
961 | ||
76c1dec1 | 962 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 963 | if (ret) |
76c1dec1 | 964 | return ret; |
1d7cfea1 | 965 | |
05394f39 | 966 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 967 | if (&obj->base == NULL) { |
1d7cfea1 CW |
968 | ret = -ENOENT; |
969 | goto unlock; | |
76c1dec1 | 970 | } |
673a394b | 971 | |
2ef7eeaa EA |
972 | if (read_domains & I915_GEM_DOMAIN_GTT) { |
973 | ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0); | |
02354392 EA |
974 | |
975 | /* Silently promote "you're not bound, there was nothing to do" | |
976 | * to success, since the client was just asking us to | |
977 | * make sure everything was done. | |
978 | */ | |
979 | if (ret == -EINVAL) | |
980 | ret = 0; | |
2ef7eeaa | 981 | } else { |
e47c68e9 | 982 | ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0); |
2ef7eeaa EA |
983 | } |
984 | ||
05394f39 | 985 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 986 | unlock: |
673a394b EA |
987 | mutex_unlock(&dev->struct_mutex); |
988 | return ret; | |
989 | } | |
990 | ||
991 | /** | |
992 | * Called when user space has done writes to this buffer | |
993 | */ | |
994 | int | |
995 | i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 996 | struct drm_file *file) |
673a394b EA |
997 | { |
998 | struct drm_i915_gem_sw_finish *args = data; | |
05394f39 | 999 | struct drm_i915_gem_object *obj; |
673a394b EA |
1000 | int ret = 0; |
1001 | ||
76c1dec1 | 1002 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 1003 | if (ret) |
76c1dec1 | 1004 | return ret; |
1d7cfea1 | 1005 | |
05394f39 | 1006 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 1007 | if (&obj->base == NULL) { |
1d7cfea1 CW |
1008 | ret = -ENOENT; |
1009 | goto unlock; | |
673a394b EA |
1010 | } |
1011 | ||
673a394b | 1012 | /* Pinned buffers may be scanout, so flush the cache */ |
05394f39 | 1013 | if (obj->pin_count) |
e47c68e9 EA |
1014 | i915_gem_object_flush_cpu_write_domain(obj); |
1015 | ||
05394f39 | 1016 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 1017 | unlock: |
673a394b EA |
1018 | mutex_unlock(&dev->struct_mutex); |
1019 | return ret; | |
1020 | } | |
1021 | ||
1022 | /** | |
1023 | * Maps the contents of an object, returning the address it is mapped | |
1024 | * into. | |
1025 | * | |
1026 | * While the mapping holds a reference on the contents of the object, it doesn't | |
1027 | * imply a ref on the object itself. | |
1028 | */ | |
1029 | int | |
1030 | i915_gem_mmap_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 1031 | struct drm_file *file) |
673a394b EA |
1032 | { |
1033 | struct drm_i915_gem_mmap *args = data; | |
1034 | struct drm_gem_object *obj; | |
673a394b EA |
1035 | unsigned long addr; |
1036 | ||
05394f39 | 1037 | obj = drm_gem_object_lookup(dev, file, args->handle); |
673a394b | 1038 | if (obj == NULL) |
bf79cb91 | 1039 | return -ENOENT; |
673a394b | 1040 | |
1286ff73 DV |
1041 | /* prime objects have no backing filp to GEM mmap |
1042 | * pages from. | |
1043 | */ | |
1044 | if (!obj->filp) { | |
1045 | drm_gem_object_unreference_unlocked(obj); | |
1046 | return -EINVAL; | |
1047 | } | |
1048 | ||
6be5ceb0 | 1049 | addr = vm_mmap(obj->filp, 0, args->size, |
673a394b EA |
1050 | PROT_READ | PROT_WRITE, MAP_SHARED, |
1051 | args->offset); | |
bc9025bd | 1052 | drm_gem_object_unreference_unlocked(obj); |
673a394b EA |
1053 | if (IS_ERR((void *)addr)) |
1054 | return addr; | |
1055 | ||
1056 | args->addr_ptr = (uint64_t) addr; | |
1057 | ||
1058 | return 0; | |
1059 | } | |
1060 | ||
de151cf6 JB |
1061 | /** |
1062 | * i915_gem_fault - fault a page into the GTT | |
1063 | * vma: VMA in question | |
1064 | * vmf: fault info | |
1065 | * | |
1066 | * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped | |
1067 | * from userspace. The fault handler takes care of binding the object to | |
1068 | * the GTT (if needed), allocating and programming a fence register (again, | |
1069 | * only if needed based on whether the old reg is still valid or the object | |
1070 | * is tiled) and inserting a new PTE into the faulting process. | |
1071 | * | |
1072 | * Note that the faulting process may involve evicting existing objects | |
1073 | * from the GTT and/or fence registers to make room. So performance may | |
1074 | * suffer if the GTT working set is large or there are few fence registers | |
1075 | * left. | |
1076 | */ | |
1077 | int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf) | |
1078 | { | |
05394f39 CW |
1079 | struct drm_i915_gem_object *obj = to_intel_bo(vma->vm_private_data); |
1080 | struct drm_device *dev = obj->base.dev; | |
7d1c4804 | 1081 | drm_i915_private_t *dev_priv = dev->dev_private; |
de151cf6 JB |
1082 | pgoff_t page_offset; |
1083 | unsigned long pfn; | |
1084 | int ret = 0; | |
0f973f27 | 1085 | bool write = !!(vmf->flags & FAULT_FLAG_WRITE); |
de151cf6 JB |
1086 | |
1087 | /* We don't use vmf->pgoff since that has the fake offset */ | |
1088 | page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >> | |
1089 | PAGE_SHIFT; | |
1090 | ||
d9bc7e9f CW |
1091 | ret = i915_mutex_lock_interruptible(dev); |
1092 | if (ret) | |
1093 | goto out; | |
a00b10c3 | 1094 | |
db53a302 CW |
1095 | trace_i915_gem_object_fault(obj, page_offset, true, write); |
1096 | ||
d9bc7e9f | 1097 | /* Now bind it into the GTT if needed */ |
919926ae CW |
1098 | if (!obj->map_and_fenceable) { |
1099 | ret = i915_gem_object_unbind(obj); | |
1100 | if (ret) | |
1101 | goto unlock; | |
a00b10c3 | 1102 | } |
05394f39 | 1103 | if (!obj->gtt_space) { |
75e9e915 | 1104 | ret = i915_gem_object_bind_to_gtt(obj, 0, true); |
c715089f CW |
1105 | if (ret) |
1106 | goto unlock; | |
de151cf6 | 1107 | |
e92d03bf EA |
1108 | ret = i915_gem_object_set_to_gtt_domain(obj, write); |
1109 | if (ret) | |
1110 | goto unlock; | |
1111 | } | |
4a684a41 | 1112 | |
74898d7e DV |
1113 | if (!obj->has_global_gtt_mapping) |
1114 | i915_gem_gtt_bind_object(obj, obj->cache_level); | |
1115 | ||
06d98131 | 1116 | ret = i915_gem_object_get_fence(obj); |
d9e86c0e CW |
1117 | if (ret) |
1118 | goto unlock; | |
de151cf6 | 1119 | |
05394f39 CW |
1120 | if (i915_gem_object_is_inactive(obj)) |
1121 | list_move_tail(&obj->mm_list, &dev_priv->mm.inactive_list); | |
7d1c4804 | 1122 | |
6299f992 CW |
1123 | obj->fault_mappable = true; |
1124 | ||
dd2757f8 | 1125 | pfn = ((dev_priv->mm.gtt_base_addr + obj->gtt_offset) >> PAGE_SHIFT) + |
de151cf6 JB |
1126 | page_offset; |
1127 | ||
1128 | /* Finally, remap it using the new GTT offset */ | |
1129 | ret = vm_insert_pfn(vma, (unsigned long)vmf->virtual_address, pfn); | |
c715089f | 1130 | unlock: |
de151cf6 | 1131 | mutex_unlock(&dev->struct_mutex); |
d9bc7e9f | 1132 | out: |
de151cf6 | 1133 | switch (ret) { |
d9bc7e9f | 1134 | case -EIO: |
045e769a | 1135 | case -EAGAIN: |
d9bc7e9f CW |
1136 | /* Give the error handler a chance to run and move the |
1137 | * objects off the GPU active list. Next time we service the | |
1138 | * fault, we should be able to transition the page into the | |
1139 | * GTT without touching the GPU (and so avoid further | |
1140 | * EIO/EGAIN). If the GPU is wedged, then there is no issue | |
1141 | * with coherency, just lost writes. | |
1142 | */ | |
045e769a | 1143 | set_need_resched(); |
c715089f CW |
1144 | case 0: |
1145 | case -ERESTARTSYS: | |
bed636ab | 1146 | case -EINTR: |
c715089f | 1147 | return VM_FAULT_NOPAGE; |
de151cf6 | 1148 | case -ENOMEM: |
de151cf6 | 1149 | return VM_FAULT_OOM; |
de151cf6 | 1150 | default: |
c715089f | 1151 | return VM_FAULT_SIGBUS; |
de151cf6 JB |
1152 | } |
1153 | } | |
1154 | ||
901782b2 CW |
1155 | /** |
1156 | * i915_gem_release_mmap - remove physical page mappings | |
1157 | * @obj: obj in question | |
1158 | * | |
af901ca1 | 1159 | * Preserve the reservation of the mmapping with the DRM core code, but |
901782b2 CW |
1160 | * relinquish ownership of the pages back to the system. |
1161 | * | |
1162 | * It is vital that we remove the page mapping if we have mapped a tiled | |
1163 | * object through the GTT and then lose the fence register due to | |
1164 | * resource pressure. Similarly if the object has been moved out of the | |
1165 | * aperture, than pages mapped into userspace must be revoked. Removing the | |
1166 | * mapping will then trigger a page fault on the next user access, allowing | |
1167 | * fixup by i915_gem_fault(). | |
1168 | */ | |
d05ca301 | 1169 | void |
05394f39 | 1170 | i915_gem_release_mmap(struct drm_i915_gem_object *obj) |
901782b2 | 1171 | { |
6299f992 CW |
1172 | if (!obj->fault_mappable) |
1173 | return; | |
901782b2 | 1174 | |
f6e47884 CW |
1175 | if (obj->base.dev->dev_mapping) |
1176 | unmap_mapping_range(obj->base.dev->dev_mapping, | |
1177 | (loff_t)obj->base.map_list.hash.key<<PAGE_SHIFT, | |
1178 | obj->base.size, 1); | |
fb7d516a | 1179 | |
6299f992 | 1180 | obj->fault_mappable = false; |
901782b2 CW |
1181 | } |
1182 | ||
92b88aeb | 1183 | static uint32_t |
e28f8711 | 1184 | i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode) |
92b88aeb | 1185 | { |
e28f8711 | 1186 | uint32_t gtt_size; |
92b88aeb CW |
1187 | |
1188 | if (INTEL_INFO(dev)->gen >= 4 || | |
e28f8711 CW |
1189 | tiling_mode == I915_TILING_NONE) |
1190 | return size; | |
92b88aeb CW |
1191 | |
1192 | /* Previous chips need a power-of-two fence region when tiling */ | |
1193 | if (INTEL_INFO(dev)->gen == 3) | |
e28f8711 | 1194 | gtt_size = 1024*1024; |
92b88aeb | 1195 | else |
e28f8711 | 1196 | gtt_size = 512*1024; |
92b88aeb | 1197 | |
e28f8711 CW |
1198 | while (gtt_size < size) |
1199 | gtt_size <<= 1; | |
92b88aeb | 1200 | |
e28f8711 | 1201 | return gtt_size; |
92b88aeb CW |
1202 | } |
1203 | ||
de151cf6 JB |
1204 | /** |
1205 | * i915_gem_get_gtt_alignment - return required GTT alignment for an object | |
1206 | * @obj: object to check | |
1207 | * | |
1208 | * Return the required GTT alignment for an object, taking into account | |
5e783301 | 1209 | * potential fence register mapping. |
de151cf6 JB |
1210 | */ |
1211 | static uint32_t | |
e28f8711 CW |
1212 | i915_gem_get_gtt_alignment(struct drm_device *dev, |
1213 | uint32_t size, | |
1214 | int tiling_mode) | |
de151cf6 | 1215 | { |
de151cf6 JB |
1216 | /* |
1217 | * Minimum alignment is 4k (GTT page size), but might be greater | |
1218 | * if a fence register is needed for the object. | |
1219 | */ | |
a00b10c3 | 1220 | if (INTEL_INFO(dev)->gen >= 4 || |
e28f8711 | 1221 | tiling_mode == I915_TILING_NONE) |
de151cf6 JB |
1222 | return 4096; |
1223 | ||
a00b10c3 CW |
1224 | /* |
1225 | * Previous chips need to be aligned to the size of the smallest | |
1226 | * fence register that can contain the object. | |
1227 | */ | |
e28f8711 | 1228 | return i915_gem_get_gtt_size(dev, size, tiling_mode); |
a00b10c3 CW |
1229 | } |
1230 | ||
5e783301 DV |
1231 | /** |
1232 | * i915_gem_get_unfenced_gtt_alignment - return required GTT alignment for an | |
1233 | * unfenced object | |
e28f8711 CW |
1234 | * @dev: the device |
1235 | * @size: size of the object | |
1236 | * @tiling_mode: tiling mode of the object | |
5e783301 DV |
1237 | * |
1238 | * Return the required GTT alignment for an object, only taking into account | |
1239 | * unfenced tiled surface requirements. | |
1240 | */ | |
467cffba | 1241 | uint32_t |
e28f8711 CW |
1242 | i915_gem_get_unfenced_gtt_alignment(struct drm_device *dev, |
1243 | uint32_t size, | |
1244 | int tiling_mode) | |
5e783301 | 1245 | { |
5e783301 DV |
1246 | /* |
1247 | * Minimum alignment is 4k (GTT page size) for sane hw. | |
1248 | */ | |
1249 | if (INTEL_INFO(dev)->gen >= 4 || IS_G33(dev) || | |
e28f8711 | 1250 | tiling_mode == I915_TILING_NONE) |
5e783301 DV |
1251 | return 4096; |
1252 | ||
e28f8711 CW |
1253 | /* Previous hardware however needs to be aligned to a power-of-two |
1254 | * tile height. The simplest method for determining this is to reuse | |
1255 | * the power-of-tile object size. | |
5e783301 | 1256 | */ |
e28f8711 | 1257 | return i915_gem_get_gtt_size(dev, size, tiling_mode); |
5e783301 DV |
1258 | } |
1259 | ||
de151cf6 | 1260 | int |
ff72145b DA |
1261 | i915_gem_mmap_gtt(struct drm_file *file, |
1262 | struct drm_device *dev, | |
1263 | uint32_t handle, | |
1264 | uint64_t *offset) | |
de151cf6 | 1265 | { |
da761a6e | 1266 | struct drm_i915_private *dev_priv = dev->dev_private; |
05394f39 | 1267 | struct drm_i915_gem_object *obj; |
de151cf6 JB |
1268 | int ret; |
1269 | ||
76c1dec1 | 1270 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 1271 | if (ret) |
76c1dec1 | 1272 | return ret; |
de151cf6 | 1273 | |
ff72145b | 1274 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle)); |
c8725226 | 1275 | if (&obj->base == NULL) { |
1d7cfea1 CW |
1276 | ret = -ENOENT; |
1277 | goto unlock; | |
1278 | } | |
de151cf6 | 1279 | |
05394f39 | 1280 | if (obj->base.size > dev_priv->mm.gtt_mappable_end) { |
da761a6e | 1281 | ret = -E2BIG; |
ff56b0bc | 1282 | goto out; |
da761a6e CW |
1283 | } |
1284 | ||
05394f39 | 1285 | if (obj->madv != I915_MADV_WILLNEED) { |
ab18282d | 1286 | DRM_ERROR("Attempting to mmap a purgeable buffer\n"); |
1d7cfea1 CW |
1287 | ret = -EINVAL; |
1288 | goto out; | |
ab18282d CW |
1289 | } |
1290 | ||
05394f39 | 1291 | if (!obj->base.map_list.map) { |
b464e9a2 | 1292 | ret = drm_gem_create_mmap_offset(&obj->base); |
1d7cfea1 CW |
1293 | if (ret) |
1294 | goto out; | |
de151cf6 JB |
1295 | } |
1296 | ||
ff72145b | 1297 | *offset = (u64)obj->base.map_list.hash.key << PAGE_SHIFT; |
de151cf6 | 1298 | |
1d7cfea1 | 1299 | out: |
05394f39 | 1300 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 1301 | unlock: |
de151cf6 | 1302 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 1303 | return ret; |
de151cf6 JB |
1304 | } |
1305 | ||
ff72145b DA |
1306 | /** |
1307 | * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing | |
1308 | * @dev: DRM device | |
1309 | * @data: GTT mapping ioctl data | |
1310 | * @file: GEM object info | |
1311 | * | |
1312 | * Simply returns the fake offset to userspace so it can mmap it. | |
1313 | * The mmap call will end up in drm_gem_mmap(), which will set things | |
1314 | * up so we can get faults in the handler above. | |
1315 | * | |
1316 | * The fault handler will take care of binding the object into the GTT | |
1317 | * (since it may have been evicted to make room for something), allocating | |
1318 | * a fence register, and mapping the appropriate aperture address into | |
1319 | * userspace. | |
1320 | */ | |
1321 | int | |
1322 | i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data, | |
1323 | struct drm_file *file) | |
1324 | { | |
1325 | struct drm_i915_gem_mmap_gtt *args = data; | |
1326 | ||
ff72145b DA |
1327 | return i915_gem_mmap_gtt(file, dev, args->handle, &args->offset); |
1328 | } | |
1329 | ||
1286ff73 | 1330 | int |
05394f39 | 1331 | i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj, |
e5281ccd CW |
1332 | gfp_t gfpmask) |
1333 | { | |
e5281ccd CW |
1334 | int page_count, i; |
1335 | struct address_space *mapping; | |
1336 | struct inode *inode; | |
1337 | struct page *page; | |
1338 | ||
1286ff73 DV |
1339 | if (obj->pages || obj->sg_table) |
1340 | return 0; | |
1341 | ||
e5281ccd CW |
1342 | /* Get the list of pages out of our struct file. They'll be pinned |
1343 | * at this point until we release them. | |
1344 | */ | |
05394f39 CW |
1345 | page_count = obj->base.size / PAGE_SIZE; |
1346 | BUG_ON(obj->pages != NULL); | |
1347 | obj->pages = drm_malloc_ab(page_count, sizeof(struct page *)); | |
1348 | if (obj->pages == NULL) | |
e5281ccd CW |
1349 | return -ENOMEM; |
1350 | ||
05394f39 | 1351 | inode = obj->base.filp->f_path.dentry->d_inode; |
e5281ccd | 1352 | mapping = inode->i_mapping; |
5949eac4 HD |
1353 | gfpmask |= mapping_gfp_mask(mapping); |
1354 | ||
e5281ccd | 1355 | for (i = 0; i < page_count; i++) { |
5949eac4 | 1356 | page = shmem_read_mapping_page_gfp(mapping, i, gfpmask); |
e5281ccd CW |
1357 | if (IS_ERR(page)) |
1358 | goto err_pages; | |
1359 | ||
05394f39 | 1360 | obj->pages[i] = page; |
e5281ccd CW |
1361 | } |
1362 | ||
6dacfd2f | 1363 | if (i915_gem_object_needs_bit17_swizzle(obj)) |
e5281ccd CW |
1364 | i915_gem_object_do_bit_17_swizzle(obj); |
1365 | ||
1366 | return 0; | |
1367 | ||
1368 | err_pages: | |
1369 | while (i--) | |
05394f39 | 1370 | page_cache_release(obj->pages[i]); |
e5281ccd | 1371 | |
05394f39 CW |
1372 | drm_free_large(obj->pages); |
1373 | obj->pages = NULL; | |
e5281ccd CW |
1374 | return PTR_ERR(page); |
1375 | } | |
1376 | ||
5cdf5881 | 1377 | static void |
05394f39 | 1378 | i915_gem_object_put_pages_gtt(struct drm_i915_gem_object *obj) |
673a394b | 1379 | { |
05394f39 | 1380 | int page_count = obj->base.size / PAGE_SIZE; |
673a394b EA |
1381 | int i; |
1382 | ||
1286ff73 DV |
1383 | if (!obj->pages) |
1384 | return; | |
1385 | ||
05394f39 | 1386 | BUG_ON(obj->madv == __I915_MADV_PURGED); |
673a394b | 1387 | |
6dacfd2f | 1388 | if (i915_gem_object_needs_bit17_swizzle(obj)) |
280b713b EA |
1389 | i915_gem_object_save_bit_17_swizzle(obj); |
1390 | ||
05394f39 CW |
1391 | if (obj->madv == I915_MADV_DONTNEED) |
1392 | obj->dirty = 0; | |
3ef94daa CW |
1393 | |
1394 | for (i = 0; i < page_count; i++) { | |
05394f39 CW |
1395 | if (obj->dirty) |
1396 | set_page_dirty(obj->pages[i]); | |
3ef94daa | 1397 | |
05394f39 CW |
1398 | if (obj->madv == I915_MADV_WILLNEED) |
1399 | mark_page_accessed(obj->pages[i]); | |
3ef94daa | 1400 | |
05394f39 | 1401 | page_cache_release(obj->pages[i]); |
3ef94daa | 1402 | } |
05394f39 | 1403 | obj->dirty = 0; |
673a394b | 1404 | |
05394f39 CW |
1405 | drm_free_large(obj->pages); |
1406 | obj->pages = NULL; | |
673a394b EA |
1407 | } |
1408 | ||
54cf91dc | 1409 | void |
05394f39 | 1410 | i915_gem_object_move_to_active(struct drm_i915_gem_object *obj, |
1ec14ad3 CW |
1411 | struct intel_ring_buffer *ring, |
1412 | u32 seqno) | |
673a394b | 1413 | { |
05394f39 | 1414 | struct drm_device *dev = obj->base.dev; |
69dc4987 | 1415 | struct drm_i915_private *dev_priv = dev->dev_private; |
617dbe27 | 1416 | |
852835f3 | 1417 | BUG_ON(ring == NULL); |
05394f39 | 1418 | obj->ring = ring; |
673a394b EA |
1419 | |
1420 | /* Add a reference if we're newly entering the active list. */ | |
05394f39 CW |
1421 | if (!obj->active) { |
1422 | drm_gem_object_reference(&obj->base); | |
1423 | obj->active = 1; | |
673a394b | 1424 | } |
e35a41de | 1425 | |
673a394b | 1426 | /* Move from whatever list we were on to the tail of execution. */ |
05394f39 CW |
1427 | list_move_tail(&obj->mm_list, &dev_priv->mm.active_list); |
1428 | list_move_tail(&obj->ring_list, &ring->active_list); | |
caea7476 | 1429 | |
05394f39 | 1430 | obj->last_rendering_seqno = seqno; |
caea7476 | 1431 | |
7dd49065 | 1432 | if (obj->fenced_gpu_access) { |
caea7476 | 1433 | obj->last_fenced_seqno = seqno; |
caea7476 | 1434 | |
7dd49065 CW |
1435 | /* Bump MRU to take account of the delayed flush */ |
1436 | if (obj->fence_reg != I915_FENCE_REG_NONE) { | |
1437 | struct drm_i915_fence_reg *reg; | |
1438 | ||
1439 | reg = &dev_priv->fence_regs[obj->fence_reg]; | |
1440 | list_move_tail(®->lru_list, | |
1441 | &dev_priv->mm.fence_list); | |
1442 | } | |
caea7476 CW |
1443 | } |
1444 | } | |
1445 | ||
1446 | static void | |
1447 | i915_gem_object_move_off_active(struct drm_i915_gem_object *obj) | |
1448 | { | |
1449 | list_del_init(&obj->ring_list); | |
1450 | obj->last_rendering_seqno = 0; | |
15a13bbd | 1451 | obj->last_fenced_seqno = 0; |
673a394b EA |
1452 | } |
1453 | ||
ce44b0ea | 1454 | static void |
05394f39 | 1455 | i915_gem_object_move_to_flushing(struct drm_i915_gem_object *obj) |
ce44b0ea | 1456 | { |
05394f39 | 1457 | struct drm_device *dev = obj->base.dev; |
ce44b0ea | 1458 | drm_i915_private_t *dev_priv = dev->dev_private; |
ce44b0ea | 1459 | |
05394f39 CW |
1460 | BUG_ON(!obj->active); |
1461 | list_move_tail(&obj->mm_list, &dev_priv->mm.flushing_list); | |
caea7476 CW |
1462 | |
1463 | i915_gem_object_move_off_active(obj); | |
1464 | } | |
1465 | ||
1466 | static void | |
1467 | i915_gem_object_move_to_inactive(struct drm_i915_gem_object *obj) | |
1468 | { | |
1469 | struct drm_device *dev = obj->base.dev; | |
1470 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1471 | ||
1b50247a | 1472 | list_move_tail(&obj->mm_list, &dev_priv->mm.inactive_list); |
caea7476 CW |
1473 | |
1474 | BUG_ON(!list_empty(&obj->gpu_write_list)); | |
1475 | BUG_ON(!obj->active); | |
1476 | obj->ring = NULL; | |
1477 | ||
1478 | i915_gem_object_move_off_active(obj); | |
1479 | obj->fenced_gpu_access = false; | |
caea7476 CW |
1480 | |
1481 | obj->active = 0; | |
87ca9c8a | 1482 | obj->pending_gpu_write = false; |
caea7476 CW |
1483 | drm_gem_object_unreference(&obj->base); |
1484 | ||
1485 | WARN_ON(i915_verify_lists(dev)); | |
ce44b0ea | 1486 | } |
673a394b | 1487 | |
963b4836 CW |
1488 | /* Immediately discard the backing storage */ |
1489 | static void | |
05394f39 | 1490 | i915_gem_object_truncate(struct drm_i915_gem_object *obj) |
963b4836 | 1491 | { |
bb6baf76 | 1492 | struct inode *inode; |
963b4836 | 1493 | |
ae9fed6b CW |
1494 | /* Our goal here is to return as much of the memory as |
1495 | * is possible back to the system as we are called from OOM. | |
1496 | * To do this we must instruct the shmfs to drop all of its | |
e2377fe0 | 1497 | * backing pages, *now*. |
ae9fed6b | 1498 | */ |
05394f39 | 1499 | inode = obj->base.filp->f_path.dentry->d_inode; |
e2377fe0 | 1500 | shmem_truncate_range(inode, 0, (loff_t)-1); |
bb6baf76 | 1501 | |
a14917ee CW |
1502 | if (obj->base.map_list.map) |
1503 | drm_gem_free_mmap_offset(&obj->base); | |
1504 | ||
05394f39 | 1505 | obj->madv = __I915_MADV_PURGED; |
963b4836 CW |
1506 | } |
1507 | ||
1508 | static inline int | |
05394f39 | 1509 | i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj) |
963b4836 | 1510 | { |
05394f39 | 1511 | return obj->madv == I915_MADV_DONTNEED; |
963b4836 CW |
1512 | } |
1513 | ||
63560396 | 1514 | static void |
db53a302 CW |
1515 | i915_gem_process_flushing_list(struct intel_ring_buffer *ring, |
1516 | uint32_t flush_domains) | |
63560396 | 1517 | { |
05394f39 | 1518 | struct drm_i915_gem_object *obj, *next; |
63560396 | 1519 | |
05394f39 | 1520 | list_for_each_entry_safe(obj, next, |
64193406 | 1521 | &ring->gpu_write_list, |
63560396 | 1522 | gpu_write_list) { |
05394f39 CW |
1523 | if (obj->base.write_domain & flush_domains) { |
1524 | uint32_t old_write_domain = obj->base.write_domain; | |
63560396 | 1525 | |
05394f39 CW |
1526 | obj->base.write_domain = 0; |
1527 | list_del_init(&obj->gpu_write_list); | |
1ec14ad3 | 1528 | i915_gem_object_move_to_active(obj, ring, |
db53a302 | 1529 | i915_gem_next_request_seqno(ring)); |
63560396 | 1530 | |
63560396 | 1531 | trace_i915_gem_object_change_domain(obj, |
05394f39 | 1532 | obj->base.read_domains, |
63560396 DV |
1533 | old_write_domain); |
1534 | } | |
1535 | } | |
1536 | } | |
8187a2b7 | 1537 | |
53d227f2 DV |
1538 | static u32 |
1539 | i915_gem_get_seqno(struct drm_device *dev) | |
1540 | { | |
1541 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1542 | u32 seqno = dev_priv->next_seqno; | |
1543 | ||
1544 | /* reserve 0 for non-seqno */ | |
1545 | if (++dev_priv->next_seqno == 0) | |
1546 | dev_priv->next_seqno = 1; | |
1547 | ||
1548 | return seqno; | |
1549 | } | |
1550 | ||
1551 | u32 | |
1552 | i915_gem_next_request_seqno(struct intel_ring_buffer *ring) | |
1553 | { | |
1554 | if (ring->outstanding_lazy_request == 0) | |
1555 | ring->outstanding_lazy_request = i915_gem_get_seqno(ring->dev); | |
1556 | ||
1557 | return ring->outstanding_lazy_request; | |
1558 | } | |
1559 | ||
3cce469c | 1560 | int |
db53a302 | 1561 | i915_add_request(struct intel_ring_buffer *ring, |
f787a5f5 | 1562 | struct drm_file *file, |
db53a302 | 1563 | struct drm_i915_gem_request *request) |
673a394b | 1564 | { |
db53a302 | 1565 | drm_i915_private_t *dev_priv = ring->dev->dev_private; |
673a394b | 1566 | uint32_t seqno; |
a71d8d94 | 1567 | u32 request_ring_position; |
673a394b | 1568 | int was_empty; |
3cce469c CW |
1569 | int ret; |
1570 | ||
cc889e0f DV |
1571 | /* |
1572 | * Emit any outstanding flushes - execbuf can fail to emit the flush | |
1573 | * after having emitted the batchbuffer command. Hence we need to fix | |
1574 | * things up similar to emitting the lazy request. The difference here | |
1575 | * is that the flush _must_ happen before the next request, no matter | |
1576 | * what. | |
1577 | */ | |
1578 | if (ring->gpu_caches_dirty) { | |
1579 | ret = i915_gem_flush_ring(ring, 0, I915_GEM_GPU_DOMAINS); | |
1580 | if (ret) | |
1581 | return ret; | |
1582 | ||
1583 | ring->gpu_caches_dirty = false; | |
1584 | } | |
1585 | ||
3cce469c | 1586 | BUG_ON(request == NULL); |
53d227f2 | 1587 | seqno = i915_gem_next_request_seqno(ring); |
673a394b | 1588 | |
a71d8d94 CW |
1589 | /* Record the position of the start of the request so that |
1590 | * should we detect the updated seqno part-way through the | |
1591 | * GPU processing the request, we never over-estimate the | |
1592 | * position of the head. | |
1593 | */ | |
1594 | request_ring_position = intel_ring_get_tail(ring); | |
1595 | ||
3cce469c CW |
1596 | ret = ring->add_request(ring, &seqno); |
1597 | if (ret) | |
1598 | return ret; | |
673a394b | 1599 | |
db53a302 | 1600 | trace_i915_gem_request_add(ring, seqno); |
673a394b EA |
1601 | |
1602 | request->seqno = seqno; | |
852835f3 | 1603 | request->ring = ring; |
a71d8d94 | 1604 | request->tail = request_ring_position; |
673a394b | 1605 | request->emitted_jiffies = jiffies; |
852835f3 ZN |
1606 | was_empty = list_empty(&ring->request_list); |
1607 | list_add_tail(&request->list, &ring->request_list); | |
1608 | ||
db53a302 CW |
1609 | if (file) { |
1610 | struct drm_i915_file_private *file_priv = file->driver_priv; | |
1611 | ||
1c25595f | 1612 | spin_lock(&file_priv->mm.lock); |
f787a5f5 | 1613 | request->file_priv = file_priv; |
b962442e | 1614 | list_add_tail(&request->client_list, |
f787a5f5 | 1615 | &file_priv->mm.request_list); |
1c25595f | 1616 | spin_unlock(&file_priv->mm.lock); |
b962442e | 1617 | } |
673a394b | 1618 | |
5391d0cf | 1619 | ring->outstanding_lazy_request = 0; |
db53a302 | 1620 | |
f65d9421 | 1621 | if (!dev_priv->mm.suspended) { |
3e0dc6b0 BW |
1622 | if (i915_enable_hangcheck) { |
1623 | mod_timer(&dev_priv->hangcheck_timer, | |
1624 | jiffies + | |
1625 | msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)); | |
1626 | } | |
f65d9421 | 1627 | if (was_empty) |
b3b079db CW |
1628 | queue_delayed_work(dev_priv->wq, |
1629 | &dev_priv->mm.retire_work, HZ); | |
f65d9421 | 1630 | } |
cc889e0f DV |
1631 | |
1632 | WARN_ON(!list_empty(&ring->gpu_write_list)); | |
1633 | ||
3cce469c | 1634 | return 0; |
673a394b EA |
1635 | } |
1636 | ||
f787a5f5 CW |
1637 | static inline void |
1638 | i915_gem_request_remove_from_client(struct drm_i915_gem_request *request) | |
673a394b | 1639 | { |
1c25595f | 1640 | struct drm_i915_file_private *file_priv = request->file_priv; |
673a394b | 1641 | |
1c25595f CW |
1642 | if (!file_priv) |
1643 | return; | |
1c5d22f7 | 1644 | |
1c25595f | 1645 | spin_lock(&file_priv->mm.lock); |
09bfa517 HRK |
1646 | if (request->file_priv) { |
1647 | list_del(&request->client_list); | |
1648 | request->file_priv = NULL; | |
1649 | } | |
1c25595f | 1650 | spin_unlock(&file_priv->mm.lock); |
673a394b | 1651 | } |
673a394b | 1652 | |
dfaae392 CW |
1653 | static void i915_gem_reset_ring_lists(struct drm_i915_private *dev_priv, |
1654 | struct intel_ring_buffer *ring) | |
9375e446 | 1655 | { |
dfaae392 CW |
1656 | while (!list_empty(&ring->request_list)) { |
1657 | struct drm_i915_gem_request *request; | |
673a394b | 1658 | |
dfaae392 CW |
1659 | request = list_first_entry(&ring->request_list, |
1660 | struct drm_i915_gem_request, | |
1661 | list); | |
de151cf6 | 1662 | |
dfaae392 | 1663 | list_del(&request->list); |
f787a5f5 | 1664 | i915_gem_request_remove_from_client(request); |
dfaae392 CW |
1665 | kfree(request); |
1666 | } | |
673a394b | 1667 | |
dfaae392 | 1668 | while (!list_empty(&ring->active_list)) { |
05394f39 | 1669 | struct drm_i915_gem_object *obj; |
9375e446 | 1670 | |
05394f39 CW |
1671 | obj = list_first_entry(&ring->active_list, |
1672 | struct drm_i915_gem_object, | |
1673 | ring_list); | |
9375e446 | 1674 | |
05394f39 CW |
1675 | obj->base.write_domain = 0; |
1676 | list_del_init(&obj->gpu_write_list); | |
1677 | i915_gem_object_move_to_inactive(obj); | |
673a394b EA |
1678 | } |
1679 | } | |
1680 | ||
312817a3 CW |
1681 | static void i915_gem_reset_fences(struct drm_device *dev) |
1682 | { | |
1683 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1684 | int i; | |
1685 | ||
4b9de737 | 1686 | for (i = 0; i < dev_priv->num_fence_regs; i++) { |
312817a3 | 1687 | struct drm_i915_fence_reg *reg = &dev_priv->fence_regs[i]; |
7d2cb39c | 1688 | |
ada726c7 | 1689 | i915_gem_write_fence(dev, i, NULL); |
7d2cb39c | 1690 | |
ada726c7 CW |
1691 | if (reg->obj) |
1692 | i915_gem_object_fence_lost(reg->obj); | |
7d2cb39c | 1693 | |
ada726c7 CW |
1694 | reg->pin_count = 0; |
1695 | reg->obj = NULL; | |
1696 | INIT_LIST_HEAD(®->lru_list); | |
312817a3 | 1697 | } |
ada726c7 CW |
1698 | |
1699 | INIT_LIST_HEAD(&dev_priv->mm.fence_list); | |
312817a3 CW |
1700 | } |
1701 | ||
069efc1d | 1702 | void i915_gem_reset(struct drm_device *dev) |
673a394b | 1703 | { |
77f01230 | 1704 | struct drm_i915_private *dev_priv = dev->dev_private; |
05394f39 | 1705 | struct drm_i915_gem_object *obj; |
b4519513 | 1706 | struct intel_ring_buffer *ring; |
1ec14ad3 | 1707 | int i; |
673a394b | 1708 | |
b4519513 CW |
1709 | for_each_ring(ring, dev_priv, i) |
1710 | i915_gem_reset_ring_lists(dev_priv, ring); | |
dfaae392 CW |
1711 | |
1712 | /* Remove anything from the flushing lists. The GPU cache is likely | |
1713 | * to be lost on reset along with the data, so simply move the | |
1714 | * lost bo to the inactive list. | |
1715 | */ | |
1716 | while (!list_empty(&dev_priv->mm.flushing_list)) { | |
0206e353 | 1717 | obj = list_first_entry(&dev_priv->mm.flushing_list, |
05394f39 CW |
1718 | struct drm_i915_gem_object, |
1719 | mm_list); | |
dfaae392 | 1720 | |
05394f39 CW |
1721 | obj->base.write_domain = 0; |
1722 | list_del_init(&obj->gpu_write_list); | |
1723 | i915_gem_object_move_to_inactive(obj); | |
dfaae392 CW |
1724 | } |
1725 | ||
1726 | /* Move everything out of the GPU domains to ensure we do any | |
1727 | * necessary invalidation upon reuse. | |
1728 | */ | |
05394f39 | 1729 | list_for_each_entry(obj, |
77f01230 | 1730 | &dev_priv->mm.inactive_list, |
69dc4987 | 1731 | mm_list) |
77f01230 | 1732 | { |
05394f39 | 1733 | obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS; |
77f01230 | 1734 | } |
069efc1d CW |
1735 | |
1736 | /* The fence registers are invalidated so clear them out */ | |
312817a3 | 1737 | i915_gem_reset_fences(dev); |
673a394b EA |
1738 | } |
1739 | ||
1740 | /** | |
1741 | * This function clears the request list as sequence numbers are passed. | |
1742 | */ | |
a71d8d94 | 1743 | void |
db53a302 | 1744 | i915_gem_retire_requests_ring(struct intel_ring_buffer *ring) |
673a394b | 1745 | { |
673a394b | 1746 | uint32_t seqno; |
1ec14ad3 | 1747 | int i; |
673a394b | 1748 | |
db53a302 | 1749 | if (list_empty(&ring->request_list)) |
6c0594a3 KW |
1750 | return; |
1751 | ||
db53a302 | 1752 | WARN_ON(i915_verify_lists(ring->dev)); |
673a394b | 1753 | |
78501eac | 1754 | seqno = ring->get_seqno(ring); |
1ec14ad3 | 1755 | |
076e2c0e | 1756 | for (i = 0; i < ARRAY_SIZE(ring->sync_seqno); i++) |
1ec14ad3 CW |
1757 | if (seqno >= ring->sync_seqno[i]) |
1758 | ring->sync_seqno[i] = 0; | |
1759 | ||
852835f3 | 1760 | while (!list_empty(&ring->request_list)) { |
673a394b | 1761 | struct drm_i915_gem_request *request; |
673a394b | 1762 | |
852835f3 | 1763 | request = list_first_entry(&ring->request_list, |
673a394b EA |
1764 | struct drm_i915_gem_request, |
1765 | list); | |
673a394b | 1766 | |
dfaae392 | 1767 | if (!i915_seqno_passed(seqno, request->seqno)) |
b84d5f0c CW |
1768 | break; |
1769 | ||
db53a302 | 1770 | trace_i915_gem_request_retire(ring, request->seqno); |
a71d8d94 CW |
1771 | /* We know the GPU must have read the request to have |
1772 | * sent us the seqno + interrupt, so use the position | |
1773 | * of tail of the request to update the last known position | |
1774 | * of the GPU head. | |
1775 | */ | |
1776 | ring->last_retired_head = request->tail; | |
b84d5f0c CW |
1777 | |
1778 | list_del(&request->list); | |
f787a5f5 | 1779 | i915_gem_request_remove_from_client(request); |
b84d5f0c CW |
1780 | kfree(request); |
1781 | } | |
673a394b | 1782 | |
b84d5f0c CW |
1783 | /* Move any buffers on the active list that are no longer referenced |
1784 | * by the ringbuffer to the flushing/inactive lists as appropriate. | |
1785 | */ | |
1786 | while (!list_empty(&ring->active_list)) { | |
05394f39 | 1787 | struct drm_i915_gem_object *obj; |
b84d5f0c | 1788 | |
0206e353 | 1789 | obj = list_first_entry(&ring->active_list, |
05394f39 CW |
1790 | struct drm_i915_gem_object, |
1791 | ring_list); | |
673a394b | 1792 | |
05394f39 | 1793 | if (!i915_seqno_passed(seqno, obj->last_rendering_seqno)) |
673a394b | 1794 | break; |
b84d5f0c | 1795 | |
05394f39 | 1796 | if (obj->base.write_domain != 0) |
b84d5f0c CW |
1797 | i915_gem_object_move_to_flushing(obj); |
1798 | else | |
1799 | i915_gem_object_move_to_inactive(obj); | |
673a394b | 1800 | } |
9d34e5db | 1801 | |
db53a302 CW |
1802 | if (unlikely(ring->trace_irq_seqno && |
1803 | i915_seqno_passed(seqno, ring->trace_irq_seqno))) { | |
1ec14ad3 | 1804 | ring->irq_put(ring); |
db53a302 | 1805 | ring->trace_irq_seqno = 0; |
9d34e5db | 1806 | } |
23bc5982 | 1807 | |
db53a302 | 1808 | WARN_ON(i915_verify_lists(ring->dev)); |
673a394b EA |
1809 | } |
1810 | ||
b09a1fec CW |
1811 | void |
1812 | i915_gem_retire_requests(struct drm_device *dev) | |
1813 | { | |
1814 | drm_i915_private_t *dev_priv = dev->dev_private; | |
b4519513 | 1815 | struct intel_ring_buffer *ring; |
1ec14ad3 | 1816 | int i; |
b09a1fec | 1817 | |
b4519513 CW |
1818 | for_each_ring(ring, dev_priv, i) |
1819 | i915_gem_retire_requests_ring(ring); | |
b09a1fec CW |
1820 | } |
1821 | ||
75ef9da2 | 1822 | static void |
673a394b EA |
1823 | i915_gem_retire_work_handler(struct work_struct *work) |
1824 | { | |
1825 | drm_i915_private_t *dev_priv; | |
1826 | struct drm_device *dev; | |
b4519513 | 1827 | struct intel_ring_buffer *ring; |
0a58705b CW |
1828 | bool idle; |
1829 | int i; | |
673a394b EA |
1830 | |
1831 | dev_priv = container_of(work, drm_i915_private_t, | |
1832 | mm.retire_work.work); | |
1833 | dev = dev_priv->dev; | |
1834 | ||
891b48cf CW |
1835 | /* Come back later if the device is busy... */ |
1836 | if (!mutex_trylock(&dev->struct_mutex)) { | |
1837 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ); | |
1838 | return; | |
1839 | } | |
1840 | ||
b09a1fec | 1841 | i915_gem_retire_requests(dev); |
d1b851fc | 1842 | |
0a58705b CW |
1843 | /* Send a periodic flush down the ring so we don't hold onto GEM |
1844 | * objects indefinitely. | |
1845 | */ | |
1846 | idle = true; | |
b4519513 | 1847 | for_each_ring(ring, dev_priv, i) { |
cc889e0f | 1848 | if (ring->gpu_caches_dirty) { |
0a58705b | 1849 | struct drm_i915_gem_request *request; |
0a58705b | 1850 | |
0a58705b | 1851 | request = kzalloc(sizeof(*request), GFP_KERNEL); |
cc889e0f | 1852 | if (request == NULL || |
db53a302 | 1853 | i915_add_request(ring, NULL, request)) |
0a58705b CW |
1854 | kfree(request); |
1855 | } | |
1856 | ||
1857 | idle &= list_empty(&ring->request_list); | |
1858 | } | |
1859 | ||
1860 | if (!dev_priv->mm.suspended && !idle) | |
9c9fe1f8 | 1861 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ); |
0a58705b | 1862 | |
673a394b EA |
1863 | mutex_unlock(&dev->struct_mutex); |
1864 | } | |
1865 | ||
d6b2c790 DV |
1866 | int |
1867 | i915_gem_check_wedge(struct drm_i915_private *dev_priv, | |
1868 | bool interruptible) | |
b4aca010 | 1869 | { |
b4aca010 BW |
1870 | if (atomic_read(&dev_priv->mm.wedged)) { |
1871 | struct completion *x = &dev_priv->error_completion; | |
1872 | bool recovery_complete; | |
1873 | unsigned long flags; | |
1874 | ||
1875 | /* Give the error handler a chance to run. */ | |
1876 | spin_lock_irqsave(&x->wait.lock, flags); | |
1877 | recovery_complete = x->done > 0; | |
1878 | spin_unlock_irqrestore(&x->wait.lock, flags); | |
1879 | ||
d6b2c790 DV |
1880 | /* Non-interruptible callers can't handle -EAGAIN, hence return |
1881 | * -EIO unconditionally for these. */ | |
1882 | if (!interruptible) | |
1883 | return -EIO; | |
1884 | ||
1885 | /* Recovery complete, but still wedged means reset failure. */ | |
1886 | if (recovery_complete) | |
1887 | return -EIO; | |
1888 | ||
1889 | return -EAGAIN; | |
b4aca010 BW |
1890 | } |
1891 | ||
1892 | return 0; | |
1893 | } | |
1894 | ||
1895 | /* | |
1896 | * Compare seqno against outstanding lazy request. Emit a request if they are | |
1897 | * equal. | |
1898 | */ | |
1899 | static int | |
1900 | i915_gem_check_olr(struct intel_ring_buffer *ring, u32 seqno) | |
1901 | { | |
1902 | int ret = 0; | |
1903 | ||
1904 | BUG_ON(!mutex_is_locked(&ring->dev->struct_mutex)); | |
1905 | ||
1906 | if (seqno == ring->outstanding_lazy_request) { | |
1907 | struct drm_i915_gem_request *request; | |
1908 | ||
1909 | request = kzalloc(sizeof(*request), GFP_KERNEL); | |
1910 | if (request == NULL) | |
1911 | return -ENOMEM; | |
1912 | ||
1913 | ret = i915_add_request(ring, NULL, request); | |
1914 | if (ret) { | |
1915 | kfree(request); | |
1916 | return ret; | |
1917 | } | |
1918 | ||
1919 | BUG_ON(seqno != request->seqno); | |
1920 | } | |
1921 | ||
1922 | return ret; | |
1923 | } | |
1924 | ||
5c81fe85 BW |
1925 | /** |
1926 | * __wait_seqno - wait until execution of seqno has finished | |
1927 | * @ring: the ring expected to report seqno | |
1928 | * @seqno: duh! | |
1929 | * @interruptible: do an interruptible wait (normally yes) | |
1930 | * @timeout: in - how long to wait (NULL forever); out - how much time remaining | |
1931 | * | |
1932 | * Returns 0 if the seqno was found within the alloted time. Else returns the | |
1933 | * errno with remaining time filled in timeout argument. | |
1934 | */ | |
604dd3ec | 1935 | static int __wait_seqno(struct intel_ring_buffer *ring, u32 seqno, |
5c81fe85 | 1936 | bool interruptible, struct timespec *timeout) |
604dd3ec BW |
1937 | { |
1938 | drm_i915_private_t *dev_priv = ring->dev->dev_private; | |
5c81fe85 BW |
1939 | struct timespec before, now, wait_time={1,0}; |
1940 | unsigned long timeout_jiffies; | |
1941 | long end; | |
1942 | bool wait_forever = true; | |
d6b2c790 | 1943 | int ret; |
604dd3ec BW |
1944 | |
1945 | if (i915_seqno_passed(ring->get_seqno(ring), seqno)) | |
1946 | return 0; | |
1947 | ||
1948 | trace_i915_gem_request_wait_begin(ring, seqno); | |
5c81fe85 BW |
1949 | |
1950 | if (timeout != NULL) { | |
1951 | wait_time = *timeout; | |
1952 | wait_forever = false; | |
1953 | } | |
1954 | ||
1955 | timeout_jiffies = timespec_to_jiffies(&wait_time); | |
1956 | ||
604dd3ec BW |
1957 | if (WARN_ON(!ring->irq_get(ring))) |
1958 | return -ENODEV; | |
1959 | ||
5c81fe85 BW |
1960 | /* Record current time in case interrupted by signal, or wedged * */ |
1961 | getrawmonotonic(&before); | |
1962 | ||
604dd3ec BW |
1963 | #define EXIT_COND \ |
1964 | (i915_seqno_passed(ring->get_seqno(ring), seqno) || \ | |
1965 | atomic_read(&dev_priv->mm.wedged)) | |
5c81fe85 BW |
1966 | do { |
1967 | if (interruptible) | |
1968 | end = wait_event_interruptible_timeout(ring->irq_queue, | |
1969 | EXIT_COND, | |
1970 | timeout_jiffies); | |
1971 | else | |
1972 | end = wait_event_timeout(ring->irq_queue, EXIT_COND, | |
1973 | timeout_jiffies); | |
604dd3ec | 1974 | |
d6b2c790 DV |
1975 | ret = i915_gem_check_wedge(dev_priv, interruptible); |
1976 | if (ret) | |
1977 | end = ret; | |
5c81fe85 BW |
1978 | } while (end == 0 && wait_forever); |
1979 | ||
1980 | getrawmonotonic(&now); | |
604dd3ec BW |
1981 | |
1982 | ring->irq_put(ring); | |
1983 | trace_i915_gem_request_wait_end(ring, seqno); | |
1984 | #undef EXIT_COND | |
1985 | ||
5c81fe85 BW |
1986 | if (timeout) { |
1987 | struct timespec sleep_time = timespec_sub(now, before); | |
1988 | *timeout = timespec_sub(*timeout, sleep_time); | |
1989 | } | |
1990 | ||
1991 | switch (end) { | |
1992 | case -EAGAIN: /* Wedged */ | |
1993 | case -ERESTARTSYS: /* Signal */ | |
1994 | return (int)end; | |
1995 | case 0: /* Timeout */ | |
1996 | if (timeout) | |
1997 | set_normalized_timespec(timeout, 0, 0); | |
1998 | return -ETIME; | |
1999 | default: /* Completed */ | |
2000 | WARN_ON(end < 0); /* We're not aware of other errors */ | |
2001 | return 0; | |
2002 | } | |
604dd3ec BW |
2003 | } |
2004 | ||
db53a302 CW |
2005 | /** |
2006 | * Waits for a sequence number to be signaled, and cleans up the | |
2007 | * request and object lists appropriately for that event. | |
2008 | */ | |
5a5a0c64 | 2009 | int |
199b2bc2 | 2010 | i915_wait_seqno(struct intel_ring_buffer *ring, uint32_t seqno) |
673a394b | 2011 | { |
db53a302 | 2012 | drm_i915_private_t *dev_priv = ring->dev->dev_private; |
673a394b EA |
2013 | int ret = 0; |
2014 | ||
2015 | BUG_ON(seqno == 0); | |
2016 | ||
d6b2c790 | 2017 | ret = i915_gem_check_wedge(dev_priv, dev_priv->mm.interruptible); |
b4aca010 BW |
2018 | if (ret) |
2019 | return ret; | |
3cce469c | 2020 | |
b4aca010 BW |
2021 | ret = i915_gem_check_olr(ring, seqno); |
2022 | if (ret) | |
2023 | return ret; | |
ffed1d09 | 2024 | |
5c81fe85 | 2025 | ret = __wait_seqno(ring, seqno, dev_priv->mm.interruptible, NULL); |
673a394b | 2026 | |
673a394b EA |
2027 | return ret; |
2028 | } | |
2029 | ||
673a394b EA |
2030 | /** |
2031 | * Ensures that all rendering to the object has completed and the object is | |
2032 | * safe to unbind from the GTT or access from the CPU. | |
2033 | */ | |
54cf91dc | 2034 | int |
ce453d81 | 2035 | i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj) |
673a394b | 2036 | { |
673a394b EA |
2037 | int ret; |
2038 | ||
e47c68e9 EA |
2039 | /* This function only exists to support waiting for existing rendering, |
2040 | * not for emitting required flushes. | |
673a394b | 2041 | */ |
05394f39 | 2042 | BUG_ON((obj->base.write_domain & I915_GEM_GPU_DOMAINS) != 0); |
673a394b EA |
2043 | |
2044 | /* If there is rendering queued on the buffer being evicted, wait for | |
2045 | * it. | |
2046 | */ | |
05394f39 | 2047 | if (obj->active) { |
199b2bc2 | 2048 | ret = i915_wait_seqno(obj->ring, obj->last_rendering_seqno); |
2cf34d7b | 2049 | if (ret) |
673a394b | 2050 | return ret; |
b2da9fe5 | 2051 | i915_gem_retire_requests_ring(obj->ring); |
673a394b EA |
2052 | } |
2053 | ||
2054 | return 0; | |
2055 | } | |
2056 | ||
30dfebf3 DV |
2057 | /** |
2058 | * Ensures that an object will eventually get non-busy by flushing any required | |
2059 | * write domains, emitting any outstanding lazy request and retiring and | |
2060 | * completed requests. | |
2061 | */ | |
2062 | static int | |
2063 | i915_gem_object_flush_active(struct drm_i915_gem_object *obj) | |
2064 | { | |
2065 | int ret; | |
2066 | ||
2067 | if (obj->active) { | |
2068 | ret = i915_gem_object_flush_gpu_write_domain(obj); | |
2069 | if (ret) | |
2070 | return ret; | |
2071 | ||
2072 | ret = i915_gem_check_olr(obj->ring, | |
2073 | obj->last_rendering_seqno); | |
2074 | if (ret) | |
2075 | return ret; | |
2076 | i915_gem_retire_requests_ring(obj->ring); | |
2077 | } | |
2078 | ||
2079 | return 0; | |
2080 | } | |
2081 | ||
23ba4fd0 BW |
2082 | /** |
2083 | * i915_gem_wait_ioctl - implements DRM_IOCTL_I915_GEM_WAIT | |
2084 | * @DRM_IOCTL_ARGS: standard ioctl arguments | |
2085 | * | |
2086 | * Returns 0 if successful, else an error is returned with the remaining time in | |
2087 | * the timeout parameter. | |
2088 | * -ETIME: object is still busy after timeout | |
2089 | * -ERESTARTSYS: signal interrupted the wait | |
2090 | * -ENONENT: object doesn't exist | |
2091 | * Also possible, but rare: | |
2092 | * -EAGAIN: GPU wedged | |
2093 | * -ENOMEM: damn | |
2094 | * -ENODEV: Internal IRQ fail | |
2095 | * -E?: The add request failed | |
2096 | * | |
2097 | * The wait ioctl with a timeout of 0 reimplements the busy ioctl. With any | |
2098 | * non-zero timeout parameter the wait ioctl will wait for the given number of | |
2099 | * nanoseconds on an object becoming unbusy. Since the wait itself does so | |
2100 | * without holding struct_mutex the object may become re-busied before this | |
2101 | * function completes. A similar but shorter * race condition exists in the busy | |
2102 | * ioctl | |
2103 | */ | |
2104 | int | |
2105 | i915_gem_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *file) | |
2106 | { | |
2107 | struct drm_i915_gem_wait *args = data; | |
2108 | struct drm_i915_gem_object *obj; | |
2109 | struct intel_ring_buffer *ring = NULL; | |
eac1f14f | 2110 | struct timespec timeout_stack, *timeout = NULL; |
23ba4fd0 BW |
2111 | u32 seqno = 0; |
2112 | int ret = 0; | |
2113 | ||
eac1f14f BW |
2114 | if (args->timeout_ns >= 0) { |
2115 | timeout_stack = ns_to_timespec(args->timeout_ns); | |
2116 | timeout = &timeout_stack; | |
2117 | } | |
23ba4fd0 BW |
2118 | |
2119 | ret = i915_mutex_lock_interruptible(dev); | |
2120 | if (ret) | |
2121 | return ret; | |
2122 | ||
2123 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->bo_handle)); | |
2124 | if (&obj->base == NULL) { | |
2125 | mutex_unlock(&dev->struct_mutex); | |
2126 | return -ENOENT; | |
2127 | } | |
2128 | ||
30dfebf3 DV |
2129 | /* Need to make sure the object gets inactive eventually. */ |
2130 | ret = i915_gem_object_flush_active(obj); | |
23ba4fd0 BW |
2131 | if (ret) |
2132 | goto out; | |
2133 | ||
2134 | if (obj->active) { | |
2135 | seqno = obj->last_rendering_seqno; | |
2136 | ring = obj->ring; | |
2137 | } | |
2138 | ||
2139 | if (seqno == 0) | |
2140 | goto out; | |
2141 | ||
23ba4fd0 BW |
2142 | /* Do this after OLR check to make sure we make forward progress polling |
2143 | * on this IOCTL with a 0 timeout (like busy ioctl) | |
2144 | */ | |
2145 | if (!args->timeout_ns) { | |
2146 | ret = -ETIME; | |
2147 | goto out; | |
2148 | } | |
2149 | ||
2150 | drm_gem_object_unreference(&obj->base); | |
2151 | mutex_unlock(&dev->struct_mutex); | |
2152 | ||
eac1f14f BW |
2153 | ret = __wait_seqno(ring, seqno, true, timeout); |
2154 | if (timeout) { | |
2155 | WARN_ON(!timespec_valid(timeout)); | |
2156 | args->timeout_ns = timespec_to_ns(timeout); | |
2157 | } | |
23ba4fd0 BW |
2158 | return ret; |
2159 | ||
2160 | out: | |
2161 | drm_gem_object_unreference(&obj->base); | |
2162 | mutex_unlock(&dev->struct_mutex); | |
2163 | return ret; | |
2164 | } | |
2165 | ||
5816d648 BW |
2166 | /** |
2167 | * i915_gem_object_sync - sync an object to a ring. | |
2168 | * | |
2169 | * @obj: object which may be in use on another ring. | |
2170 | * @to: ring we wish to use the object on. May be NULL. | |
2171 | * | |
2172 | * This code is meant to abstract object synchronization with the GPU. | |
2173 | * Calling with NULL implies synchronizing the object with the CPU | |
2174 | * rather than a particular GPU ring. | |
2175 | * | |
2176 | * Returns 0 if successful, else propagates up the lower layer error. | |
2177 | */ | |
2911a35b BW |
2178 | int |
2179 | i915_gem_object_sync(struct drm_i915_gem_object *obj, | |
2180 | struct intel_ring_buffer *to) | |
2181 | { | |
2182 | struct intel_ring_buffer *from = obj->ring; | |
2183 | u32 seqno; | |
2184 | int ret, idx; | |
2185 | ||
2186 | if (from == NULL || to == from) | |
2187 | return 0; | |
2188 | ||
5816d648 | 2189 | if (to == NULL || !i915_semaphore_is_enabled(obj->base.dev)) |
2911a35b BW |
2190 | return i915_gem_object_wait_rendering(obj); |
2191 | ||
2192 | idx = intel_ring_sync_index(from, to); | |
2193 | ||
2194 | seqno = obj->last_rendering_seqno; | |
2195 | if (seqno <= from->sync_seqno[idx]) | |
2196 | return 0; | |
2197 | ||
b4aca010 BW |
2198 | ret = i915_gem_check_olr(obj->ring, seqno); |
2199 | if (ret) | |
2200 | return ret; | |
2911a35b | 2201 | |
1500f7ea | 2202 | ret = to->sync_to(to, from, seqno); |
e3a5a225 BW |
2203 | if (!ret) |
2204 | from->sync_seqno[idx] = seqno; | |
2911a35b | 2205 | |
e3a5a225 | 2206 | return ret; |
2911a35b BW |
2207 | } |
2208 | ||
b5ffc9bc CW |
2209 | static void i915_gem_object_finish_gtt(struct drm_i915_gem_object *obj) |
2210 | { | |
2211 | u32 old_write_domain, old_read_domains; | |
2212 | ||
b5ffc9bc CW |
2213 | /* Act a barrier for all accesses through the GTT */ |
2214 | mb(); | |
2215 | ||
2216 | /* Force a pagefault for domain tracking on next user access */ | |
2217 | i915_gem_release_mmap(obj); | |
2218 | ||
b97c3d9c KP |
2219 | if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0) |
2220 | return; | |
2221 | ||
b5ffc9bc CW |
2222 | old_read_domains = obj->base.read_domains; |
2223 | old_write_domain = obj->base.write_domain; | |
2224 | ||
2225 | obj->base.read_domains &= ~I915_GEM_DOMAIN_GTT; | |
2226 | obj->base.write_domain &= ~I915_GEM_DOMAIN_GTT; | |
2227 | ||
2228 | trace_i915_gem_object_change_domain(obj, | |
2229 | old_read_domains, | |
2230 | old_write_domain); | |
2231 | } | |
2232 | ||
673a394b EA |
2233 | /** |
2234 | * Unbinds an object from the GTT aperture. | |
2235 | */ | |
0f973f27 | 2236 | int |
05394f39 | 2237 | i915_gem_object_unbind(struct drm_i915_gem_object *obj) |
673a394b | 2238 | { |
7bddb01f | 2239 | drm_i915_private_t *dev_priv = obj->base.dev->dev_private; |
673a394b EA |
2240 | int ret = 0; |
2241 | ||
05394f39 | 2242 | if (obj->gtt_space == NULL) |
673a394b EA |
2243 | return 0; |
2244 | ||
31d8d651 CW |
2245 | if (obj->pin_count) |
2246 | return -EBUSY; | |
673a394b | 2247 | |
a8198eea | 2248 | ret = i915_gem_object_finish_gpu(obj); |
1488fc08 | 2249 | if (ret) |
a8198eea CW |
2250 | return ret; |
2251 | /* Continue on if we fail due to EIO, the GPU is hung so we | |
2252 | * should be safe and we need to cleanup or else we might | |
2253 | * cause memory corruption through use-after-free. | |
2254 | */ | |
2255 | ||
b5ffc9bc | 2256 | i915_gem_object_finish_gtt(obj); |
5323fd04 | 2257 | |
673a394b EA |
2258 | /* Move the object to the CPU domain to ensure that |
2259 | * any possible CPU writes while it's not in the GTT | |
a8198eea | 2260 | * are flushed when we go to remap it. |
673a394b | 2261 | */ |
a8198eea CW |
2262 | if (ret == 0) |
2263 | ret = i915_gem_object_set_to_cpu_domain(obj, 1); | |
8dc1775d | 2264 | if (ret == -ERESTARTSYS) |
673a394b | 2265 | return ret; |
812ed492 | 2266 | if (ret) { |
a8198eea CW |
2267 | /* In the event of a disaster, abandon all caches and |
2268 | * hope for the best. | |
2269 | */ | |
812ed492 | 2270 | i915_gem_clflush_object(obj); |
05394f39 | 2271 | obj->base.read_domains = obj->base.write_domain = I915_GEM_DOMAIN_CPU; |
812ed492 | 2272 | } |
673a394b | 2273 | |
96b47b65 | 2274 | /* release the fence reg _after_ flushing */ |
d9e86c0e | 2275 | ret = i915_gem_object_put_fence(obj); |
1488fc08 | 2276 | if (ret) |
d9e86c0e | 2277 | return ret; |
96b47b65 | 2278 | |
db53a302 CW |
2279 | trace_i915_gem_object_unbind(obj); |
2280 | ||
74898d7e DV |
2281 | if (obj->has_global_gtt_mapping) |
2282 | i915_gem_gtt_unbind_object(obj); | |
7bddb01f DV |
2283 | if (obj->has_aliasing_ppgtt_mapping) { |
2284 | i915_ppgtt_unbind_object(dev_priv->mm.aliasing_ppgtt, obj); | |
2285 | obj->has_aliasing_ppgtt_mapping = 0; | |
2286 | } | |
74163907 | 2287 | i915_gem_gtt_finish_object(obj); |
7bddb01f | 2288 | |
e5281ccd | 2289 | i915_gem_object_put_pages_gtt(obj); |
673a394b | 2290 | |
6299f992 | 2291 | list_del_init(&obj->gtt_list); |
05394f39 | 2292 | list_del_init(&obj->mm_list); |
75e9e915 | 2293 | /* Avoid an unnecessary call to unbind on rebind. */ |
05394f39 | 2294 | obj->map_and_fenceable = true; |
673a394b | 2295 | |
05394f39 CW |
2296 | drm_mm_put_block(obj->gtt_space); |
2297 | obj->gtt_space = NULL; | |
2298 | obj->gtt_offset = 0; | |
673a394b | 2299 | |
05394f39 | 2300 | if (i915_gem_object_is_purgeable(obj)) |
963b4836 CW |
2301 | i915_gem_object_truncate(obj); |
2302 | ||
8dc1775d | 2303 | return ret; |
673a394b EA |
2304 | } |
2305 | ||
88241785 | 2306 | int |
db53a302 | 2307 | i915_gem_flush_ring(struct intel_ring_buffer *ring, |
54cf91dc CW |
2308 | uint32_t invalidate_domains, |
2309 | uint32_t flush_domains) | |
2310 | { | |
88241785 CW |
2311 | int ret; |
2312 | ||
36d527de CW |
2313 | if (((invalidate_domains | flush_domains) & I915_GEM_GPU_DOMAINS) == 0) |
2314 | return 0; | |
2315 | ||
db53a302 CW |
2316 | trace_i915_gem_ring_flush(ring, invalidate_domains, flush_domains); |
2317 | ||
88241785 CW |
2318 | ret = ring->flush(ring, invalidate_domains, flush_domains); |
2319 | if (ret) | |
2320 | return ret; | |
2321 | ||
36d527de CW |
2322 | if (flush_domains & I915_GEM_GPU_DOMAINS) |
2323 | i915_gem_process_flushing_list(ring, flush_domains); | |
2324 | ||
88241785 | 2325 | return 0; |
54cf91dc CW |
2326 | } |
2327 | ||
b2da9fe5 | 2328 | static int i915_ring_idle(struct intel_ring_buffer *ring) |
a56ba56c | 2329 | { |
88241785 CW |
2330 | int ret; |
2331 | ||
395b70be | 2332 | if (list_empty(&ring->gpu_write_list) && list_empty(&ring->active_list)) |
64193406 CW |
2333 | return 0; |
2334 | ||
88241785 | 2335 | if (!list_empty(&ring->gpu_write_list)) { |
db53a302 | 2336 | ret = i915_gem_flush_ring(ring, |
0ac74c6b | 2337 | I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS); |
88241785 CW |
2338 | if (ret) |
2339 | return ret; | |
2340 | } | |
2341 | ||
199b2bc2 | 2342 | return i915_wait_seqno(ring, i915_gem_next_request_seqno(ring)); |
a56ba56c CW |
2343 | } |
2344 | ||
b2da9fe5 | 2345 | int i915_gpu_idle(struct drm_device *dev) |
4df2faf4 DV |
2346 | { |
2347 | drm_i915_private_t *dev_priv = dev->dev_private; | |
b4519513 | 2348 | struct intel_ring_buffer *ring; |
1ec14ad3 | 2349 | int ret, i; |
4df2faf4 | 2350 | |
4df2faf4 | 2351 | /* Flush everything onto the inactive list. */ |
b4519513 CW |
2352 | for_each_ring(ring, dev_priv, i) { |
2353 | ret = i915_ring_idle(ring); | |
1ec14ad3 CW |
2354 | if (ret) |
2355 | return ret; | |
b4519513 CW |
2356 | |
2357 | /* Is the device fubar? */ | |
2358 | if (WARN_ON(!list_empty(&ring->gpu_write_list))) | |
2359 | return -EBUSY; | |
f2ef6eb1 BW |
2360 | |
2361 | ret = i915_switch_context(ring, NULL, DEFAULT_CONTEXT_ID); | |
2362 | if (ret) | |
2363 | return ret; | |
1ec14ad3 | 2364 | } |
4df2faf4 | 2365 | |
8a1a49f9 | 2366 | return 0; |
4df2faf4 DV |
2367 | } |
2368 | ||
9ce079e4 CW |
2369 | static void sandybridge_write_fence_reg(struct drm_device *dev, int reg, |
2370 | struct drm_i915_gem_object *obj) | |
4e901fdc | 2371 | { |
4e901fdc | 2372 | drm_i915_private_t *dev_priv = dev->dev_private; |
4e901fdc EA |
2373 | uint64_t val; |
2374 | ||
9ce079e4 CW |
2375 | if (obj) { |
2376 | u32 size = obj->gtt_space->size; | |
4e901fdc | 2377 | |
9ce079e4 CW |
2378 | val = (uint64_t)((obj->gtt_offset + size - 4096) & |
2379 | 0xfffff000) << 32; | |
2380 | val |= obj->gtt_offset & 0xfffff000; | |
2381 | val |= (uint64_t)((obj->stride / 128) - 1) << | |
2382 | SANDYBRIDGE_FENCE_PITCH_SHIFT; | |
4e901fdc | 2383 | |
9ce079e4 CW |
2384 | if (obj->tiling_mode == I915_TILING_Y) |
2385 | val |= 1 << I965_FENCE_TILING_Y_SHIFT; | |
2386 | val |= I965_FENCE_REG_VALID; | |
2387 | } else | |
2388 | val = 0; | |
c6642782 | 2389 | |
9ce079e4 CW |
2390 | I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + reg * 8, val); |
2391 | POSTING_READ(FENCE_REG_SANDYBRIDGE_0 + reg * 8); | |
4e901fdc EA |
2392 | } |
2393 | ||
9ce079e4 CW |
2394 | static void i965_write_fence_reg(struct drm_device *dev, int reg, |
2395 | struct drm_i915_gem_object *obj) | |
de151cf6 | 2396 | { |
de151cf6 | 2397 | drm_i915_private_t *dev_priv = dev->dev_private; |
de151cf6 JB |
2398 | uint64_t val; |
2399 | ||
9ce079e4 CW |
2400 | if (obj) { |
2401 | u32 size = obj->gtt_space->size; | |
de151cf6 | 2402 | |
9ce079e4 CW |
2403 | val = (uint64_t)((obj->gtt_offset + size - 4096) & |
2404 | 0xfffff000) << 32; | |
2405 | val |= obj->gtt_offset & 0xfffff000; | |
2406 | val |= ((obj->stride / 128) - 1) << I965_FENCE_PITCH_SHIFT; | |
2407 | if (obj->tiling_mode == I915_TILING_Y) | |
2408 | val |= 1 << I965_FENCE_TILING_Y_SHIFT; | |
2409 | val |= I965_FENCE_REG_VALID; | |
2410 | } else | |
2411 | val = 0; | |
c6642782 | 2412 | |
9ce079e4 CW |
2413 | I915_WRITE64(FENCE_REG_965_0 + reg * 8, val); |
2414 | POSTING_READ(FENCE_REG_965_0 + reg * 8); | |
de151cf6 JB |
2415 | } |
2416 | ||
9ce079e4 CW |
2417 | static void i915_write_fence_reg(struct drm_device *dev, int reg, |
2418 | struct drm_i915_gem_object *obj) | |
de151cf6 | 2419 | { |
de151cf6 | 2420 | drm_i915_private_t *dev_priv = dev->dev_private; |
9ce079e4 | 2421 | u32 val; |
de151cf6 | 2422 | |
9ce079e4 CW |
2423 | if (obj) { |
2424 | u32 size = obj->gtt_space->size; | |
2425 | int pitch_val; | |
2426 | int tile_width; | |
c6642782 | 2427 | |
9ce079e4 CW |
2428 | WARN((obj->gtt_offset & ~I915_FENCE_START_MASK) || |
2429 | (size & -size) != size || | |
2430 | (obj->gtt_offset & (size - 1)), | |
2431 | "object 0x%08x [fenceable? %d] not 1M or pot-size (0x%08x) aligned\n", | |
2432 | obj->gtt_offset, obj->map_and_fenceable, size); | |
c6642782 | 2433 | |
9ce079e4 CW |
2434 | if (obj->tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev)) |
2435 | tile_width = 128; | |
2436 | else | |
2437 | tile_width = 512; | |
2438 | ||
2439 | /* Note: pitch better be a power of two tile widths */ | |
2440 | pitch_val = obj->stride / tile_width; | |
2441 | pitch_val = ffs(pitch_val) - 1; | |
2442 | ||
2443 | val = obj->gtt_offset; | |
2444 | if (obj->tiling_mode == I915_TILING_Y) | |
2445 | val |= 1 << I830_FENCE_TILING_Y_SHIFT; | |
2446 | val |= I915_FENCE_SIZE_BITS(size); | |
2447 | val |= pitch_val << I830_FENCE_PITCH_SHIFT; | |
2448 | val |= I830_FENCE_REG_VALID; | |
2449 | } else | |
2450 | val = 0; | |
2451 | ||
2452 | if (reg < 8) | |
2453 | reg = FENCE_REG_830_0 + reg * 4; | |
2454 | else | |
2455 | reg = FENCE_REG_945_8 + (reg - 8) * 4; | |
2456 | ||
2457 | I915_WRITE(reg, val); | |
2458 | POSTING_READ(reg); | |
de151cf6 JB |
2459 | } |
2460 | ||
9ce079e4 CW |
2461 | static void i830_write_fence_reg(struct drm_device *dev, int reg, |
2462 | struct drm_i915_gem_object *obj) | |
de151cf6 | 2463 | { |
de151cf6 | 2464 | drm_i915_private_t *dev_priv = dev->dev_private; |
de151cf6 | 2465 | uint32_t val; |
de151cf6 | 2466 | |
9ce079e4 CW |
2467 | if (obj) { |
2468 | u32 size = obj->gtt_space->size; | |
2469 | uint32_t pitch_val; | |
de151cf6 | 2470 | |
9ce079e4 CW |
2471 | WARN((obj->gtt_offset & ~I830_FENCE_START_MASK) || |
2472 | (size & -size) != size || | |
2473 | (obj->gtt_offset & (size - 1)), | |
2474 | "object 0x%08x not 512K or pot-size 0x%08x aligned\n", | |
2475 | obj->gtt_offset, size); | |
e76a16de | 2476 | |
9ce079e4 CW |
2477 | pitch_val = obj->stride / 128; |
2478 | pitch_val = ffs(pitch_val) - 1; | |
de151cf6 | 2479 | |
9ce079e4 CW |
2480 | val = obj->gtt_offset; |
2481 | if (obj->tiling_mode == I915_TILING_Y) | |
2482 | val |= 1 << I830_FENCE_TILING_Y_SHIFT; | |
2483 | val |= I830_FENCE_SIZE_BITS(size); | |
2484 | val |= pitch_val << I830_FENCE_PITCH_SHIFT; | |
2485 | val |= I830_FENCE_REG_VALID; | |
2486 | } else | |
2487 | val = 0; | |
c6642782 | 2488 | |
9ce079e4 CW |
2489 | I915_WRITE(FENCE_REG_830_0 + reg * 4, val); |
2490 | POSTING_READ(FENCE_REG_830_0 + reg * 4); | |
2491 | } | |
2492 | ||
2493 | static void i915_gem_write_fence(struct drm_device *dev, int reg, | |
2494 | struct drm_i915_gem_object *obj) | |
2495 | { | |
2496 | switch (INTEL_INFO(dev)->gen) { | |
2497 | case 7: | |
2498 | case 6: sandybridge_write_fence_reg(dev, reg, obj); break; | |
2499 | case 5: | |
2500 | case 4: i965_write_fence_reg(dev, reg, obj); break; | |
2501 | case 3: i915_write_fence_reg(dev, reg, obj); break; | |
2502 | case 2: i830_write_fence_reg(dev, reg, obj); break; | |
2503 | default: break; | |
2504 | } | |
de151cf6 JB |
2505 | } |
2506 | ||
61050808 CW |
2507 | static inline int fence_number(struct drm_i915_private *dev_priv, |
2508 | struct drm_i915_fence_reg *fence) | |
2509 | { | |
2510 | return fence - dev_priv->fence_regs; | |
2511 | } | |
2512 | ||
2513 | static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj, | |
2514 | struct drm_i915_fence_reg *fence, | |
2515 | bool enable) | |
2516 | { | |
2517 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; | |
2518 | int reg = fence_number(dev_priv, fence); | |
2519 | ||
2520 | i915_gem_write_fence(obj->base.dev, reg, enable ? obj : NULL); | |
2521 | ||
2522 | if (enable) { | |
2523 | obj->fence_reg = reg; | |
2524 | fence->obj = obj; | |
2525 | list_move_tail(&fence->lru_list, &dev_priv->mm.fence_list); | |
2526 | } else { | |
2527 | obj->fence_reg = I915_FENCE_REG_NONE; | |
2528 | fence->obj = NULL; | |
2529 | list_del_init(&fence->lru_list); | |
2530 | } | |
2531 | } | |
2532 | ||
d9e86c0e | 2533 | static int |
a360bb1a | 2534 | i915_gem_object_flush_fence(struct drm_i915_gem_object *obj) |
d9e86c0e CW |
2535 | { |
2536 | int ret; | |
2537 | ||
2538 | if (obj->fenced_gpu_access) { | |
88241785 | 2539 | if (obj->base.write_domain & I915_GEM_GPU_DOMAINS) { |
1c293ea3 | 2540 | ret = i915_gem_flush_ring(obj->ring, |
88241785 CW |
2541 | 0, obj->base.write_domain); |
2542 | if (ret) | |
2543 | return ret; | |
2544 | } | |
d9e86c0e CW |
2545 | |
2546 | obj->fenced_gpu_access = false; | |
2547 | } | |
2548 | ||
1c293ea3 | 2549 | if (obj->last_fenced_seqno) { |
199b2bc2 | 2550 | ret = i915_wait_seqno(obj->ring, obj->last_fenced_seqno); |
18991845 CW |
2551 | if (ret) |
2552 | return ret; | |
d9e86c0e CW |
2553 | |
2554 | obj->last_fenced_seqno = 0; | |
d9e86c0e CW |
2555 | } |
2556 | ||
63256ec5 CW |
2557 | /* Ensure that all CPU reads are completed before installing a fence |
2558 | * and all writes before removing the fence. | |
2559 | */ | |
2560 | if (obj->base.read_domains & I915_GEM_DOMAIN_GTT) | |
2561 | mb(); | |
2562 | ||
d9e86c0e CW |
2563 | return 0; |
2564 | } | |
2565 | ||
2566 | int | |
2567 | i915_gem_object_put_fence(struct drm_i915_gem_object *obj) | |
2568 | { | |
61050808 | 2569 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
d9e86c0e CW |
2570 | int ret; |
2571 | ||
a360bb1a | 2572 | ret = i915_gem_object_flush_fence(obj); |
d9e86c0e CW |
2573 | if (ret) |
2574 | return ret; | |
2575 | ||
61050808 CW |
2576 | if (obj->fence_reg == I915_FENCE_REG_NONE) |
2577 | return 0; | |
d9e86c0e | 2578 | |
61050808 CW |
2579 | i915_gem_object_update_fence(obj, |
2580 | &dev_priv->fence_regs[obj->fence_reg], | |
2581 | false); | |
2582 | i915_gem_object_fence_lost(obj); | |
d9e86c0e CW |
2583 | |
2584 | return 0; | |
2585 | } | |
2586 | ||
2587 | static struct drm_i915_fence_reg * | |
a360bb1a | 2588 | i915_find_fence_reg(struct drm_device *dev) |
ae3db24a | 2589 | { |
ae3db24a | 2590 | struct drm_i915_private *dev_priv = dev->dev_private; |
8fe301ad | 2591 | struct drm_i915_fence_reg *reg, *avail; |
d9e86c0e | 2592 | int i; |
ae3db24a DV |
2593 | |
2594 | /* First try to find a free reg */ | |
d9e86c0e | 2595 | avail = NULL; |
ae3db24a DV |
2596 | for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) { |
2597 | reg = &dev_priv->fence_regs[i]; | |
2598 | if (!reg->obj) | |
d9e86c0e | 2599 | return reg; |
ae3db24a | 2600 | |
1690e1eb | 2601 | if (!reg->pin_count) |
d9e86c0e | 2602 | avail = reg; |
ae3db24a DV |
2603 | } |
2604 | ||
d9e86c0e CW |
2605 | if (avail == NULL) |
2606 | return NULL; | |
ae3db24a DV |
2607 | |
2608 | /* None available, try to steal one or wait for a user to finish */ | |
d9e86c0e | 2609 | list_for_each_entry(reg, &dev_priv->mm.fence_list, lru_list) { |
1690e1eb | 2610 | if (reg->pin_count) |
ae3db24a DV |
2611 | continue; |
2612 | ||
8fe301ad | 2613 | return reg; |
ae3db24a DV |
2614 | } |
2615 | ||
8fe301ad | 2616 | return NULL; |
ae3db24a DV |
2617 | } |
2618 | ||
de151cf6 | 2619 | /** |
9a5a53b3 | 2620 | * i915_gem_object_get_fence - set up fencing for an object |
de151cf6 JB |
2621 | * @obj: object to map through a fence reg |
2622 | * | |
2623 | * When mapping objects through the GTT, userspace wants to be able to write | |
2624 | * to them without having to worry about swizzling if the object is tiled. | |
de151cf6 JB |
2625 | * This function walks the fence regs looking for a free one for @obj, |
2626 | * stealing one if it can't find any. | |
2627 | * | |
2628 | * It then sets up the reg based on the object's properties: address, pitch | |
2629 | * and tiling format. | |
9a5a53b3 CW |
2630 | * |
2631 | * For an untiled surface, this removes any existing fence. | |
de151cf6 | 2632 | */ |
8c4b8c3f | 2633 | int |
06d98131 | 2634 | i915_gem_object_get_fence(struct drm_i915_gem_object *obj) |
de151cf6 | 2635 | { |
05394f39 | 2636 | struct drm_device *dev = obj->base.dev; |
79e53945 | 2637 | struct drm_i915_private *dev_priv = dev->dev_private; |
14415745 | 2638 | bool enable = obj->tiling_mode != I915_TILING_NONE; |
d9e86c0e | 2639 | struct drm_i915_fence_reg *reg; |
ae3db24a | 2640 | int ret; |
de151cf6 | 2641 | |
14415745 CW |
2642 | /* Have we updated the tiling parameters upon the object and so |
2643 | * will need to serialise the write to the associated fence register? | |
2644 | */ | |
5d82e3e6 | 2645 | if (obj->fence_dirty) { |
14415745 CW |
2646 | ret = i915_gem_object_flush_fence(obj); |
2647 | if (ret) | |
2648 | return ret; | |
2649 | } | |
9a5a53b3 | 2650 | |
d9e86c0e | 2651 | /* Just update our place in the LRU if our fence is getting reused. */ |
05394f39 CW |
2652 | if (obj->fence_reg != I915_FENCE_REG_NONE) { |
2653 | reg = &dev_priv->fence_regs[obj->fence_reg]; | |
5d82e3e6 | 2654 | if (!obj->fence_dirty) { |
14415745 CW |
2655 | list_move_tail(®->lru_list, |
2656 | &dev_priv->mm.fence_list); | |
2657 | return 0; | |
2658 | } | |
2659 | } else if (enable) { | |
2660 | reg = i915_find_fence_reg(dev); | |
2661 | if (reg == NULL) | |
2662 | return -EDEADLK; | |
d9e86c0e | 2663 | |
14415745 CW |
2664 | if (reg->obj) { |
2665 | struct drm_i915_gem_object *old = reg->obj; | |
2666 | ||
2667 | ret = i915_gem_object_flush_fence(old); | |
29c5a587 CW |
2668 | if (ret) |
2669 | return ret; | |
2670 | ||
14415745 | 2671 | i915_gem_object_fence_lost(old); |
29c5a587 | 2672 | } |
14415745 | 2673 | } else |
a09ba7fa | 2674 | return 0; |
a09ba7fa | 2675 | |
14415745 | 2676 | i915_gem_object_update_fence(obj, reg, enable); |
5d82e3e6 | 2677 | obj->fence_dirty = false; |
14415745 | 2678 | |
9ce079e4 | 2679 | return 0; |
de151cf6 JB |
2680 | } |
2681 | ||
673a394b EA |
2682 | /** |
2683 | * Finds free space in the GTT aperture and binds the object there. | |
2684 | */ | |
2685 | static int | |
05394f39 | 2686 | i915_gem_object_bind_to_gtt(struct drm_i915_gem_object *obj, |
920afa77 | 2687 | unsigned alignment, |
75e9e915 | 2688 | bool map_and_fenceable) |
673a394b | 2689 | { |
05394f39 | 2690 | struct drm_device *dev = obj->base.dev; |
673a394b | 2691 | drm_i915_private_t *dev_priv = dev->dev_private; |
673a394b | 2692 | struct drm_mm_node *free_space; |
a00b10c3 | 2693 | gfp_t gfpmask = __GFP_NORETRY | __GFP_NOWARN; |
5e783301 | 2694 | u32 size, fence_size, fence_alignment, unfenced_alignment; |
75e9e915 | 2695 | bool mappable, fenceable; |
07f73f69 | 2696 | int ret; |
673a394b | 2697 | |
05394f39 | 2698 | if (obj->madv != I915_MADV_WILLNEED) { |
3ef94daa CW |
2699 | DRM_ERROR("Attempting to bind a purgeable object\n"); |
2700 | return -EINVAL; | |
2701 | } | |
2702 | ||
e28f8711 CW |
2703 | fence_size = i915_gem_get_gtt_size(dev, |
2704 | obj->base.size, | |
2705 | obj->tiling_mode); | |
2706 | fence_alignment = i915_gem_get_gtt_alignment(dev, | |
2707 | obj->base.size, | |
2708 | obj->tiling_mode); | |
2709 | unfenced_alignment = | |
2710 | i915_gem_get_unfenced_gtt_alignment(dev, | |
2711 | obj->base.size, | |
2712 | obj->tiling_mode); | |
a00b10c3 | 2713 | |
673a394b | 2714 | if (alignment == 0) |
5e783301 DV |
2715 | alignment = map_and_fenceable ? fence_alignment : |
2716 | unfenced_alignment; | |
75e9e915 | 2717 | if (map_and_fenceable && alignment & (fence_alignment - 1)) { |
673a394b EA |
2718 | DRM_ERROR("Invalid object alignment requested %u\n", alignment); |
2719 | return -EINVAL; | |
2720 | } | |
2721 | ||
05394f39 | 2722 | size = map_and_fenceable ? fence_size : obj->base.size; |
a00b10c3 | 2723 | |
654fc607 CW |
2724 | /* If the object is bigger than the entire aperture, reject it early |
2725 | * before evicting everything in a vain attempt to find space. | |
2726 | */ | |
05394f39 | 2727 | if (obj->base.size > |
75e9e915 | 2728 | (map_and_fenceable ? dev_priv->mm.gtt_mappable_end : dev_priv->mm.gtt_total)) { |
654fc607 CW |
2729 | DRM_ERROR("Attempting to bind an object larger than the aperture\n"); |
2730 | return -E2BIG; | |
2731 | } | |
2732 | ||
673a394b | 2733 | search_free: |
75e9e915 | 2734 | if (map_and_fenceable) |
920afa77 DV |
2735 | free_space = |
2736 | drm_mm_search_free_in_range(&dev_priv->mm.gtt_space, | |
a00b10c3 | 2737 | size, alignment, 0, |
920afa77 DV |
2738 | dev_priv->mm.gtt_mappable_end, |
2739 | 0); | |
2740 | else | |
2741 | free_space = drm_mm_search_free(&dev_priv->mm.gtt_space, | |
a00b10c3 | 2742 | size, alignment, 0); |
920afa77 DV |
2743 | |
2744 | if (free_space != NULL) { | |
75e9e915 | 2745 | if (map_and_fenceable) |
05394f39 | 2746 | obj->gtt_space = |
920afa77 | 2747 | drm_mm_get_block_range_generic(free_space, |
a00b10c3 | 2748 | size, alignment, 0, |
920afa77 DV |
2749 | dev_priv->mm.gtt_mappable_end, |
2750 | 0); | |
2751 | else | |
05394f39 | 2752 | obj->gtt_space = |
a00b10c3 | 2753 | drm_mm_get_block(free_space, size, alignment); |
920afa77 | 2754 | } |
05394f39 | 2755 | if (obj->gtt_space == NULL) { |
673a394b EA |
2756 | /* If the gtt is empty and we're still having trouble |
2757 | * fitting our object in, we're out of memory. | |
2758 | */ | |
75e9e915 DV |
2759 | ret = i915_gem_evict_something(dev, size, alignment, |
2760 | map_and_fenceable); | |
9731129c | 2761 | if (ret) |
673a394b | 2762 | return ret; |
9731129c | 2763 | |
673a394b EA |
2764 | goto search_free; |
2765 | } | |
2766 | ||
e5281ccd | 2767 | ret = i915_gem_object_get_pages_gtt(obj, gfpmask); |
673a394b | 2768 | if (ret) { |
05394f39 CW |
2769 | drm_mm_put_block(obj->gtt_space); |
2770 | obj->gtt_space = NULL; | |
07f73f69 CW |
2771 | |
2772 | if (ret == -ENOMEM) { | |
809b6334 CW |
2773 | /* first try to reclaim some memory by clearing the GTT */ |
2774 | ret = i915_gem_evict_everything(dev, false); | |
07f73f69 | 2775 | if (ret) { |
07f73f69 | 2776 | /* now try to shrink everyone else */ |
4bdadb97 CW |
2777 | if (gfpmask) { |
2778 | gfpmask = 0; | |
2779 | goto search_free; | |
07f73f69 CW |
2780 | } |
2781 | ||
809b6334 | 2782 | return -ENOMEM; |
07f73f69 CW |
2783 | } |
2784 | ||
2785 | goto search_free; | |
2786 | } | |
2787 | ||
673a394b EA |
2788 | return ret; |
2789 | } | |
2790 | ||
74163907 | 2791 | ret = i915_gem_gtt_prepare_object(obj); |
7c2e6fdf | 2792 | if (ret) { |
e5281ccd | 2793 | i915_gem_object_put_pages_gtt(obj); |
05394f39 CW |
2794 | drm_mm_put_block(obj->gtt_space); |
2795 | obj->gtt_space = NULL; | |
07f73f69 | 2796 | |
809b6334 | 2797 | if (i915_gem_evict_everything(dev, false)) |
07f73f69 | 2798 | return ret; |
07f73f69 CW |
2799 | |
2800 | goto search_free; | |
673a394b | 2801 | } |
673a394b | 2802 | |
0ebb9829 DV |
2803 | if (!dev_priv->mm.aliasing_ppgtt) |
2804 | i915_gem_gtt_bind_object(obj, obj->cache_level); | |
673a394b | 2805 | |
6299f992 | 2806 | list_add_tail(&obj->gtt_list, &dev_priv->mm.gtt_list); |
05394f39 | 2807 | list_add_tail(&obj->mm_list, &dev_priv->mm.inactive_list); |
bf1a1092 | 2808 | |
673a394b EA |
2809 | /* Assert that the object is not currently in any GPU domain. As it |
2810 | * wasn't in the GTT, there shouldn't be any way it could have been in | |
2811 | * a GPU cache | |
2812 | */ | |
05394f39 CW |
2813 | BUG_ON(obj->base.read_domains & I915_GEM_GPU_DOMAINS); |
2814 | BUG_ON(obj->base.write_domain & I915_GEM_GPU_DOMAINS); | |
673a394b | 2815 | |
6299f992 | 2816 | obj->gtt_offset = obj->gtt_space->start; |
1c5d22f7 | 2817 | |
75e9e915 | 2818 | fenceable = |
05394f39 | 2819 | obj->gtt_space->size == fence_size && |
0206e353 | 2820 | (obj->gtt_space->start & (fence_alignment - 1)) == 0; |
a00b10c3 | 2821 | |
75e9e915 | 2822 | mappable = |
05394f39 | 2823 | obj->gtt_offset + obj->base.size <= dev_priv->mm.gtt_mappable_end; |
a00b10c3 | 2824 | |
05394f39 | 2825 | obj->map_and_fenceable = mappable && fenceable; |
75e9e915 | 2826 | |
db53a302 | 2827 | trace_i915_gem_object_bind(obj, map_and_fenceable); |
673a394b EA |
2828 | return 0; |
2829 | } | |
2830 | ||
2831 | void | |
05394f39 | 2832 | i915_gem_clflush_object(struct drm_i915_gem_object *obj) |
673a394b | 2833 | { |
673a394b EA |
2834 | /* If we don't have a page list set up, then we're not pinned |
2835 | * to GPU, and we can ignore the cache flush because it'll happen | |
2836 | * again at bind time. | |
2837 | */ | |
05394f39 | 2838 | if (obj->pages == NULL) |
673a394b EA |
2839 | return; |
2840 | ||
9c23f7fc CW |
2841 | /* If the GPU is snooping the contents of the CPU cache, |
2842 | * we do not need to manually clear the CPU cache lines. However, | |
2843 | * the caches are only snooped when the render cache is | |
2844 | * flushed/invalidated. As we always have to emit invalidations | |
2845 | * and flushes when moving into and out of the RENDER domain, correct | |
2846 | * snooping behaviour occurs naturally as the result of our domain | |
2847 | * tracking. | |
2848 | */ | |
2849 | if (obj->cache_level != I915_CACHE_NONE) | |
2850 | return; | |
2851 | ||
1c5d22f7 | 2852 | trace_i915_gem_object_clflush(obj); |
cfa16a0d | 2853 | |
05394f39 | 2854 | drm_clflush_pages(obj->pages, obj->base.size / PAGE_SIZE); |
673a394b EA |
2855 | } |
2856 | ||
e47c68e9 | 2857 | /** Flushes any GPU write domain for the object if it's dirty. */ |
88241785 | 2858 | static int |
3619df03 | 2859 | i915_gem_object_flush_gpu_write_domain(struct drm_i915_gem_object *obj) |
e47c68e9 | 2860 | { |
05394f39 | 2861 | if ((obj->base.write_domain & I915_GEM_GPU_DOMAINS) == 0) |
88241785 | 2862 | return 0; |
e47c68e9 EA |
2863 | |
2864 | /* Queue the GPU write cache flushing we need. */ | |
db53a302 | 2865 | return i915_gem_flush_ring(obj->ring, 0, obj->base.write_domain); |
e47c68e9 EA |
2866 | } |
2867 | ||
2868 | /** Flushes the GTT write domain for the object if it's dirty. */ | |
2869 | static void | |
05394f39 | 2870 | i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj) |
e47c68e9 | 2871 | { |
1c5d22f7 CW |
2872 | uint32_t old_write_domain; |
2873 | ||
05394f39 | 2874 | if (obj->base.write_domain != I915_GEM_DOMAIN_GTT) |
e47c68e9 EA |
2875 | return; |
2876 | ||
63256ec5 | 2877 | /* No actual flushing is required for the GTT write domain. Writes |
e47c68e9 EA |
2878 | * to it immediately go to main memory as far as we know, so there's |
2879 | * no chipset flush. It also doesn't land in render cache. | |
63256ec5 CW |
2880 | * |
2881 | * However, we do have to enforce the order so that all writes through | |
2882 | * the GTT land before any writes to the device, such as updates to | |
2883 | * the GATT itself. | |
e47c68e9 | 2884 | */ |
63256ec5 CW |
2885 | wmb(); |
2886 | ||
05394f39 CW |
2887 | old_write_domain = obj->base.write_domain; |
2888 | obj->base.write_domain = 0; | |
1c5d22f7 CW |
2889 | |
2890 | trace_i915_gem_object_change_domain(obj, | |
05394f39 | 2891 | obj->base.read_domains, |
1c5d22f7 | 2892 | old_write_domain); |
e47c68e9 EA |
2893 | } |
2894 | ||
2895 | /** Flushes the CPU write domain for the object if it's dirty. */ | |
2896 | static void | |
05394f39 | 2897 | i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj) |
e47c68e9 | 2898 | { |
1c5d22f7 | 2899 | uint32_t old_write_domain; |
e47c68e9 | 2900 | |
05394f39 | 2901 | if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) |
e47c68e9 EA |
2902 | return; |
2903 | ||
2904 | i915_gem_clflush_object(obj); | |
40ce6575 | 2905 | intel_gtt_chipset_flush(); |
05394f39 CW |
2906 | old_write_domain = obj->base.write_domain; |
2907 | obj->base.write_domain = 0; | |
1c5d22f7 CW |
2908 | |
2909 | trace_i915_gem_object_change_domain(obj, | |
05394f39 | 2910 | obj->base.read_domains, |
1c5d22f7 | 2911 | old_write_domain); |
e47c68e9 EA |
2912 | } |
2913 | ||
2ef7eeaa EA |
2914 | /** |
2915 | * Moves a single object to the GTT read, and possibly write domain. | |
2916 | * | |
2917 | * This function returns when the move is complete, including waiting on | |
2918 | * flushes to occur. | |
2919 | */ | |
79e53945 | 2920 | int |
2021746e | 2921 | i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write) |
2ef7eeaa | 2922 | { |
8325a09d | 2923 | drm_i915_private_t *dev_priv = obj->base.dev->dev_private; |
1c5d22f7 | 2924 | uint32_t old_write_domain, old_read_domains; |
e47c68e9 | 2925 | int ret; |
2ef7eeaa | 2926 | |
02354392 | 2927 | /* Not valid to be called on unbound objects. */ |
05394f39 | 2928 | if (obj->gtt_space == NULL) |
02354392 EA |
2929 | return -EINVAL; |
2930 | ||
8d7e3de1 CW |
2931 | if (obj->base.write_domain == I915_GEM_DOMAIN_GTT) |
2932 | return 0; | |
2933 | ||
88241785 CW |
2934 | ret = i915_gem_object_flush_gpu_write_domain(obj); |
2935 | if (ret) | |
2936 | return ret; | |
2937 | ||
87ca9c8a | 2938 | if (obj->pending_gpu_write || write) { |
ce453d81 | 2939 | ret = i915_gem_object_wait_rendering(obj); |
87ca9c8a CW |
2940 | if (ret) |
2941 | return ret; | |
2942 | } | |
2dafb1e0 | 2943 | |
7213342d | 2944 | i915_gem_object_flush_cpu_write_domain(obj); |
1c5d22f7 | 2945 | |
05394f39 CW |
2946 | old_write_domain = obj->base.write_domain; |
2947 | old_read_domains = obj->base.read_domains; | |
1c5d22f7 | 2948 | |
e47c68e9 EA |
2949 | /* It should now be out of any other write domains, and we can update |
2950 | * the domain values for our changes. | |
2951 | */ | |
05394f39 CW |
2952 | BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) != 0); |
2953 | obj->base.read_domains |= I915_GEM_DOMAIN_GTT; | |
e47c68e9 | 2954 | if (write) { |
05394f39 CW |
2955 | obj->base.read_domains = I915_GEM_DOMAIN_GTT; |
2956 | obj->base.write_domain = I915_GEM_DOMAIN_GTT; | |
2957 | obj->dirty = 1; | |
2ef7eeaa EA |
2958 | } |
2959 | ||
1c5d22f7 CW |
2960 | trace_i915_gem_object_change_domain(obj, |
2961 | old_read_domains, | |
2962 | old_write_domain); | |
2963 | ||
8325a09d CW |
2964 | /* And bump the LRU for this access */ |
2965 | if (i915_gem_object_is_inactive(obj)) | |
2966 | list_move_tail(&obj->mm_list, &dev_priv->mm.inactive_list); | |
2967 | ||
e47c68e9 EA |
2968 | return 0; |
2969 | } | |
2970 | ||
e4ffd173 CW |
2971 | int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj, |
2972 | enum i915_cache_level cache_level) | |
2973 | { | |
7bddb01f DV |
2974 | struct drm_device *dev = obj->base.dev; |
2975 | drm_i915_private_t *dev_priv = dev->dev_private; | |
e4ffd173 CW |
2976 | int ret; |
2977 | ||
2978 | if (obj->cache_level == cache_level) | |
2979 | return 0; | |
2980 | ||
2981 | if (obj->pin_count) { | |
2982 | DRM_DEBUG("can not change the cache level of pinned objects\n"); | |
2983 | return -EBUSY; | |
2984 | } | |
2985 | ||
2986 | if (obj->gtt_space) { | |
2987 | ret = i915_gem_object_finish_gpu(obj); | |
2988 | if (ret) | |
2989 | return ret; | |
2990 | ||
2991 | i915_gem_object_finish_gtt(obj); | |
2992 | ||
2993 | /* Before SandyBridge, you could not use tiling or fence | |
2994 | * registers with snooped memory, so relinquish any fences | |
2995 | * currently pointing to our region in the aperture. | |
2996 | */ | |
2997 | if (INTEL_INFO(obj->base.dev)->gen < 6) { | |
2998 | ret = i915_gem_object_put_fence(obj); | |
2999 | if (ret) | |
3000 | return ret; | |
3001 | } | |
3002 | ||
74898d7e DV |
3003 | if (obj->has_global_gtt_mapping) |
3004 | i915_gem_gtt_bind_object(obj, cache_level); | |
7bddb01f DV |
3005 | if (obj->has_aliasing_ppgtt_mapping) |
3006 | i915_ppgtt_bind_object(dev_priv->mm.aliasing_ppgtt, | |
3007 | obj, cache_level); | |
e4ffd173 CW |
3008 | } |
3009 | ||
3010 | if (cache_level == I915_CACHE_NONE) { | |
3011 | u32 old_read_domains, old_write_domain; | |
3012 | ||
3013 | /* If we're coming from LLC cached, then we haven't | |
3014 | * actually been tracking whether the data is in the | |
3015 | * CPU cache or not, since we only allow one bit set | |
3016 | * in obj->write_domain and have been skipping the clflushes. | |
3017 | * Just set it to the CPU cache for now. | |
3018 | */ | |
3019 | WARN_ON(obj->base.write_domain & ~I915_GEM_DOMAIN_CPU); | |
3020 | WARN_ON(obj->base.read_domains & ~I915_GEM_DOMAIN_CPU); | |
3021 | ||
3022 | old_read_domains = obj->base.read_domains; | |
3023 | old_write_domain = obj->base.write_domain; | |
3024 | ||
3025 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; | |
3026 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; | |
3027 | ||
3028 | trace_i915_gem_object_change_domain(obj, | |
3029 | old_read_domains, | |
3030 | old_write_domain); | |
3031 | } | |
3032 | ||
3033 | obj->cache_level = cache_level; | |
3034 | return 0; | |
3035 | } | |
3036 | ||
b9241ea3 | 3037 | /* |
2da3b9b9 CW |
3038 | * Prepare buffer for display plane (scanout, cursors, etc). |
3039 | * Can be called from an uninterruptible phase (modesetting) and allows | |
3040 | * any flushes to be pipelined (for pageflips). | |
b9241ea3 ZW |
3041 | */ |
3042 | int | |
2da3b9b9 CW |
3043 | i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj, |
3044 | u32 alignment, | |
919926ae | 3045 | struct intel_ring_buffer *pipelined) |
b9241ea3 | 3046 | { |
2da3b9b9 | 3047 | u32 old_read_domains, old_write_domain; |
b9241ea3 ZW |
3048 | int ret; |
3049 | ||
88241785 CW |
3050 | ret = i915_gem_object_flush_gpu_write_domain(obj); |
3051 | if (ret) | |
3052 | return ret; | |
3053 | ||
0be73284 | 3054 | if (pipelined != obj->ring) { |
2911a35b BW |
3055 | ret = i915_gem_object_sync(obj, pipelined); |
3056 | if (ret) | |
b9241ea3 ZW |
3057 | return ret; |
3058 | } | |
3059 | ||
a7ef0640 EA |
3060 | /* The display engine is not coherent with the LLC cache on gen6. As |
3061 | * a result, we make sure that the pinning that is about to occur is | |
3062 | * done with uncached PTEs. This is lowest common denominator for all | |
3063 | * chipsets. | |
3064 | * | |
3065 | * However for gen6+, we could do better by using the GFDT bit instead | |
3066 | * of uncaching, which would allow us to flush all the LLC-cached data | |
3067 | * with that bit in the PTE to main memory with just one PIPE_CONTROL. | |
3068 | */ | |
3069 | ret = i915_gem_object_set_cache_level(obj, I915_CACHE_NONE); | |
3070 | if (ret) | |
3071 | return ret; | |
3072 | ||
2da3b9b9 CW |
3073 | /* As the user may map the buffer once pinned in the display plane |
3074 | * (e.g. libkms for the bootup splash), we have to ensure that we | |
3075 | * always use map_and_fenceable for all scanout buffers. | |
3076 | */ | |
3077 | ret = i915_gem_object_pin(obj, alignment, true); | |
3078 | if (ret) | |
3079 | return ret; | |
3080 | ||
b118c1e3 CW |
3081 | i915_gem_object_flush_cpu_write_domain(obj); |
3082 | ||
2da3b9b9 | 3083 | old_write_domain = obj->base.write_domain; |
05394f39 | 3084 | old_read_domains = obj->base.read_domains; |
2da3b9b9 CW |
3085 | |
3086 | /* It should now be out of any other write domains, and we can update | |
3087 | * the domain values for our changes. | |
3088 | */ | |
3089 | BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) != 0); | |
05394f39 | 3090 | obj->base.read_domains |= I915_GEM_DOMAIN_GTT; |
b9241ea3 ZW |
3091 | |
3092 | trace_i915_gem_object_change_domain(obj, | |
3093 | old_read_domains, | |
2da3b9b9 | 3094 | old_write_domain); |
b9241ea3 ZW |
3095 | |
3096 | return 0; | |
3097 | } | |
3098 | ||
85345517 | 3099 | int |
a8198eea | 3100 | i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj) |
85345517 | 3101 | { |
88241785 CW |
3102 | int ret; |
3103 | ||
a8198eea | 3104 | if ((obj->base.read_domains & I915_GEM_GPU_DOMAINS) == 0) |
85345517 CW |
3105 | return 0; |
3106 | ||
88241785 | 3107 | if (obj->base.write_domain & I915_GEM_GPU_DOMAINS) { |
db53a302 | 3108 | ret = i915_gem_flush_ring(obj->ring, 0, obj->base.write_domain); |
88241785 CW |
3109 | if (ret) |
3110 | return ret; | |
3111 | } | |
85345517 | 3112 | |
c501ae7f CW |
3113 | ret = i915_gem_object_wait_rendering(obj); |
3114 | if (ret) | |
3115 | return ret; | |
3116 | ||
a8198eea CW |
3117 | /* Ensure that we invalidate the GPU's caches and TLBs. */ |
3118 | obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS; | |
c501ae7f | 3119 | return 0; |
85345517 CW |
3120 | } |
3121 | ||
e47c68e9 EA |
3122 | /** |
3123 | * Moves a single object to the CPU read, and possibly write domain. | |
3124 | * | |
3125 | * This function returns when the move is complete, including waiting on | |
3126 | * flushes to occur. | |
3127 | */ | |
dabdfe02 | 3128 | int |
919926ae | 3129 | i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write) |
e47c68e9 | 3130 | { |
1c5d22f7 | 3131 | uint32_t old_write_domain, old_read_domains; |
e47c68e9 EA |
3132 | int ret; |
3133 | ||
8d7e3de1 CW |
3134 | if (obj->base.write_domain == I915_GEM_DOMAIN_CPU) |
3135 | return 0; | |
3136 | ||
88241785 CW |
3137 | ret = i915_gem_object_flush_gpu_write_domain(obj); |
3138 | if (ret) | |
3139 | return ret; | |
3140 | ||
f8413190 CW |
3141 | if (write || obj->pending_gpu_write) { |
3142 | ret = i915_gem_object_wait_rendering(obj); | |
3143 | if (ret) | |
3144 | return ret; | |
3145 | } | |
2ef7eeaa | 3146 | |
e47c68e9 | 3147 | i915_gem_object_flush_gtt_write_domain(obj); |
2ef7eeaa | 3148 | |
05394f39 CW |
3149 | old_write_domain = obj->base.write_domain; |
3150 | old_read_domains = obj->base.read_domains; | |
1c5d22f7 | 3151 | |
e47c68e9 | 3152 | /* Flush the CPU cache if it's still invalid. */ |
05394f39 | 3153 | if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) { |
2ef7eeaa | 3154 | i915_gem_clflush_object(obj); |
2ef7eeaa | 3155 | |
05394f39 | 3156 | obj->base.read_domains |= I915_GEM_DOMAIN_CPU; |
2ef7eeaa EA |
3157 | } |
3158 | ||
3159 | /* It should now be out of any other write domains, and we can update | |
3160 | * the domain values for our changes. | |
3161 | */ | |
05394f39 | 3162 | BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) != 0); |
e47c68e9 EA |
3163 | |
3164 | /* If we're writing through the CPU, then the GPU read domains will | |
3165 | * need to be invalidated at next use. | |
3166 | */ | |
3167 | if (write) { | |
05394f39 CW |
3168 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; |
3169 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; | |
e47c68e9 | 3170 | } |
2ef7eeaa | 3171 | |
1c5d22f7 CW |
3172 | trace_i915_gem_object_change_domain(obj, |
3173 | old_read_domains, | |
3174 | old_write_domain); | |
3175 | ||
2ef7eeaa EA |
3176 | return 0; |
3177 | } | |
3178 | ||
673a394b EA |
3179 | /* Throttle our rendering by waiting until the ring has completed our requests |
3180 | * emitted over 20 msec ago. | |
3181 | * | |
b962442e EA |
3182 | * Note that if we were to use the current jiffies each time around the loop, |
3183 | * we wouldn't escape the function with any frames outstanding if the time to | |
3184 | * render a frame was over 20ms. | |
3185 | * | |
673a394b EA |
3186 | * This should get us reasonable parallelism between CPU and GPU but also |
3187 | * relatively low latency when blocking on a particular request to finish. | |
3188 | */ | |
40a5f0de | 3189 | static int |
f787a5f5 | 3190 | i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file) |
40a5f0de | 3191 | { |
f787a5f5 CW |
3192 | struct drm_i915_private *dev_priv = dev->dev_private; |
3193 | struct drm_i915_file_private *file_priv = file->driver_priv; | |
b962442e | 3194 | unsigned long recent_enough = jiffies - msecs_to_jiffies(20); |
f787a5f5 CW |
3195 | struct drm_i915_gem_request *request; |
3196 | struct intel_ring_buffer *ring = NULL; | |
3197 | u32 seqno = 0; | |
3198 | int ret; | |
93533c29 | 3199 | |
e110e8d6 CW |
3200 | if (atomic_read(&dev_priv->mm.wedged)) |
3201 | return -EIO; | |
3202 | ||
1c25595f | 3203 | spin_lock(&file_priv->mm.lock); |
f787a5f5 | 3204 | list_for_each_entry(request, &file_priv->mm.request_list, client_list) { |
b962442e EA |
3205 | if (time_after_eq(request->emitted_jiffies, recent_enough)) |
3206 | break; | |
40a5f0de | 3207 | |
f787a5f5 CW |
3208 | ring = request->ring; |
3209 | seqno = request->seqno; | |
b962442e | 3210 | } |
1c25595f | 3211 | spin_unlock(&file_priv->mm.lock); |
40a5f0de | 3212 | |
f787a5f5 CW |
3213 | if (seqno == 0) |
3214 | return 0; | |
2bc43b5c | 3215 | |
5c81fe85 | 3216 | ret = __wait_seqno(ring, seqno, true, NULL); |
f787a5f5 CW |
3217 | if (ret == 0) |
3218 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, 0); | |
40a5f0de EA |
3219 | |
3220 | return ret; | |
3221 | } | |
3222 | ||
673a394b | 3223 | int |
05394f39 CW |
3224 | i915_gem_object_pin(struct drm_i915_gem_object *obj, |
3225 | uint32_t alignment, | |
75e9e915 | 3226 | bool map_and_fenceable) |
673a394b | 3227 | { |
673a394b EA |
3228 | int ret; |
3229 | ||
05394f39 | 3230 | BUG_ON(obj->pin_count == DRM_I915_GEM_OBJECT_MAX_PIN_COUNT); |
ac0c6b5a | 3231 | |
05394f39 CW |
3232 | if (obj->gtt_space != NULL) { |
3233 | if ((alignment && obj->gtt_offset & (alignment - 1)) || | |
3234 | (map_and_fenceable && !obj->map_and_fenceable)) { | |
3235 | WARN(obj->pin_count, | |
ae7d49d8 | 3236 | "bo is already pinned with incorrect alignment:" |
75e9e915 DV |
3237 | " offset=%x, req.alignment=%x, req.map_and_fenceable=%d," |
3238 | " obj->map_and_fenceable=%d\n", | |
05394f39 | 3239 | obj->gtt_offset, alignment, |
75e9e915 | 3240 | map_and_fenceable, |
05394f39 | 3241 | obj->map_and_fenceable); |
ac0c6b5a CW |
3242 | ret = i915_gem_object_unbind(obj); |
3243 | if (ret) | |
3244 | return ret; | |
3245 | } | |
3246 | } | |
3247 | ||
05394f39 | 3248 | if (obj->gtt_space == NULL) { |
a00b10c3 | 3249 | ret = i915_gem_object_bind_to_gtt(obj, alignment, |
75e9e915 | 3250 | map_and_fenceable); |
9731129c | 3251 | if (ret) |
673a394b | 3252 | return ret; |
22c344e9 | 3253 | } |
76446cac | 3254 | |
74898d7e DV |
3255 | if (!obj->has_global_gtt_mapping && map_and_fenceable) |
3256 | i915_gem_gtt_bind_object(obj, obj->cache_level); | |
3257 | ||
1b50247a | 3258 | obj->pin_count++; |
6299f992 | 3259 | obj->pin_mappable |= map_and_fenceable; |
673a394b EA |
3260 | |
3261 | return 0; | |
3262 | } | |
3263 | ||
3264 | void | |
05394f39 | 3265 | i915_gem_object_unpin(struct drm_i915_gem_object *obj) |
673a394b | 3266 | { |
05394f39 CW |
3267 | BUG_ON(obj->pin_count == 0); |
3268 | BUG_ON(obj->gtt_space == NULL); | |
673a394b | 3269 | |
1b50247a | 3270 | if (--obj->pin_count == 0) |
6299f992 | 3271 | obj->pin_mappable = false; |
673a394b EA |
3272 | } |
3273 | ||
3274 | int | |
3275 | i915_gem_pin_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 3276 | struct drm_file *file) |
673a394b EA |
3277 | { |
3278 | struct drm_i915_gem_pin *args = data; | |
05394f39 | 3279 | struct drm_i915_gem_object *obj; |
673a394b EA |
3280 | int ret; |
3281 | ||
1d7cfea1 CW |
3282 | ret = i915_mutex_lock_interruptible(dev); |
3283 | if (ret) | |
3284 | return ret; | |
673a394b | 3285 | |
05394f39 | 3286 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 3287 | if (&obj->base == NULL) { |
1d7cfea1 CW |
3288 | ret = -ENOENT; |
3289 | goto unlock; | |
673a394b | 3290 | } |
673a394b | 3291 | |
05394f39 | 3292 | if (obj->madv != I915_MADV_WILLNEED) { |
bb6baf76 | 3293 | DRM_ERROR("Attempting to pin a purgeable buffer\n"); |
1d7cfea1 CW |
3294 | ret = -EINVAL; |
3295 | goto out; | |
3ef94daa CW |
3296 | } |
3297 | ||
05394f39 | 3298 | if (obj->pin_filp != NULL && obj->pin_filp != file) { |
79e53945 JB |
3299 | DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n", |
3300 | args->handle); | |
1d7cfea1 CW |
3301 | ret = -EINVAL; |
3302 | goto out; | |
79e53945 JB |
3303 | } |
3304 | ||
05394f39 CW |
3305 | obj->user_pin_count++; |
3306 | obj->pin_filp = file; | |
3307 | if (obj->user_pin_count == 1) { | |
75e9e915 | 3308 | ret = i915_gem_object_pin(obj, args->alignment, true); |
1d7cfea1 CW |
3309 | if (ret) |
3310 | goto out; | |
673a394b EA |
3311 | } |
3312 | ||
3313 | /* XXX - flush the CPU caches for pinned objects | |
3314 | * as the X server doesn't manage domains yet | |
3315 | */ | |
e47c68e9 | 3316 | i915_gem_object_flush_cpu_write_domain(obj); |
05394f39 | 3317 | args->offset = obj->gtt_offset; |
1d7cfea1 | 3318 | out: |
05394f39 | 3319 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 3320 | unlock: |
673a394b | 3321 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 3322 | return ret; |
673a394b EA |
3323 | } |
3324 | ||
3325 | int | |
3326 | i915_gem_unpin_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 3327 | struct drm_file *file) |
673a394b EA |
3328 | { |
3329 | struct drm_i915_gem_pin *args = data; | |
05394f39 | 3330 | struct drm_i915_gem_object *obj; |
76c1dec1 | 3331 | int ret; |
673a394b | 3332 | |
1d7cfea1 CW |
3333 | ret = i915_mutex_lock_interruptible(dev); |
3334 | if (ret) | |
3335 | return ret; | |
673a394b | 3336 | |
05394f39 | 3337 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 3338 | if (&obj->base == NULL) { |
1d7cfea1 CW |
3339 | ret = -ENOENT; |
3340 | goto unlock; | |
673a394b | 3341 | } |
76c1dec1 | 3342 | |
05394f39 | 3343 | if (obj->pin_filp != file) { |
79e53945 JB |
3344 | DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n", |
3345 | args->handle); | |
1d7cfea1 CW |
3346 | ret = -EINVAL; |
3347 | goto out; | |
79e53945 | 3348 | } |
05394f39 CW |
3349 | obj->user_pin_count--; |
3350 | if (obj->user_pin_count == 0) { | |
3351 | obj->pin_filp = NULL; | |
79e53945 JB |
3352 | i915_gem_object_unpin(obj); |
3353 | } | |
673a394b | 3354 | |
1d7cfea1 | 3355 | out: |
05394f39 | 3356 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 3357 | unlock: |
673a394b | 3358 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 3359 | return ret; |
673a394b EA |
3360 | } |
3361 | ||
3362 | int | |
3363 | i915_gem_busy_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 3364 | struct drm_file *file) |
673a394b EA |
3365 | { |
3366 | struct drm_i915_gem_busy *args = data; | |
05394f39 | 3367 | struct drm_i915_gem_object *obj; |
30dbf0c0 CW |
3368 | int ret; |
3369 | ||
76c1dec1 | 3370 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 3371 | if (ret) |
76c1dec1 | 3372 | return ret; |
673a394b | 3373 | |
05394f39 | 3374 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 3375 | if (&obj->base == NULL) { |
1d7cfea1 CW |
3376 | ret = -ENOENT; |
3377 | goto unlock; | |
673a394b | 3378 | } |
d1b851fc | 3379 | |
0be555b6 CW |
3380 | /* Count all active objects as busy, even if they are currently not used |
3381 | * by the gpu. Users of this interface expect objects to eventually | |
3382 | * become non-busy without any further actions, therefore emit any | |
3383 | * necessary flushes here. | |
c4de0a5d | 3384 | */ |
30dfebf3 | 3385 | ret = i915_gem_object_flush_active(obj); |
0be555b6 | 3386 | |
30dfebf3 | 3387 | args->busy = obj->active; |
673a394b | 3388 | |
05394f39 | 3389 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 3390 | unlock: |
673a394b | 3391 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 3392 | return ret; |
673a394b EA |
3393 | } |
3394 | ||
3395 | int | |
3396 | i915_gem_throttle_ioctl(struct drm_device *dev, void *data, | |
3397 | struct drm_file *file_priv) | |
3398 | { | |
0206e353 | 3399 | return i915_gem_ring_throttle(dev, file_priv); |
673a394b EA |
3400 | } |
3401 | ||
3ef94daa CW |
3402 | int |
3403 | i915_gem_madvise_ioctl(struct drm_device *dev, void *data, | |
3404 | struct drm_file *file_priv) | |
3405 | { | |
3406 | struct drm_i915_gem_madvise *args = data; | |
05394f39 | 3407 | struct drm_i915_gem_object *obj; |
76c1dec1 | 3408 | int ret; |
3ef94daa CW |
3409 | |
3410 | switch (args->madv) { | |
3411 | case I915_MADV_DONTNEED: | |
3412 | case I915_MADV_WILLNEED: | |
3413 | break; | |
3414 | default: | |
3415 | return -EINVAL; | |
3416 | } | |
3417 | ||
1d7cfea1 CW |
3418 | ret = i915_mutex_lock_interruptible(dev); |
3419 | if (ret) | |
3420 | return ret; | |
3421 | ||
05394f39 | 3422 | obj = to_intel_bo(drm_gem_object_lookup(dev, file_priv, args->handle)); |
c8725226 | 3423 | if (&obj->base == NULL) { |
1d7cfea1 CW |
3424 | ret = -ENOENT; |
3425 | goto unlock; | |
3ef94daa | 3426 | } |
3ef94daa | 3427 | |
05394f39 | 3428 | if (obj->pin_count) { |
1d7cfea1 CW |
3429 | ret = -EINVAL; |
3430 | goto out; | |
3ef94daa CW |
3431 | } |
3432 | ||
05394f39 CW |
3433 | if (obj->madv != __I915_MADV_PURGED) |
3434 | obj->madv = args->madv; | |
3ef94daa | 3435 | |
2d7ef395 | 3436 | /* if the object is no longer bound, discard its backing storage */ |
05394f39 CW |
3437 | if (i915_gem_object_is_purgeable(obj) && |
3438 | obj->gtt_space == NULL) | |
2d7ef395 CW |
3439 | i915_gem_object_truncate(obj); |
3440 | ||
05394f39 | 3441 | args->retained = obj->madv != __I915_MADV_PURGED; |
bb6baf76 | 3442 | |
1d7cfea1 | 3443 | out: |
05394f39 | 3444 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 3445 | unlock: |
3ef94daa | 3446 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 3447 | return ret; |
3ef94daa CW |
3448 | } |
3449 | ||
05394f39 CW |
3450 | struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev, |
3451 | size_t size) | |
ac52bc56 | 3452 | { |
73aa808f | 3453 | struct drm_i915_private *dev_priv = dev->dev_private; |
c397b908 | 3454 | struct drm_i915_gem_object *obj; |
5949eac4 | 3455 | struct address_space *mapping; |
bed1ea95 | 3456 | u32 mask; |
ac52bc56 | 3457 | |
c397b908 DV |
3458 | obj = kzalloc(sizeof(*obj), GFP_KERNEL); |
3459 | if (obj == NULL) | |
3460 | return NULL; | |
673a394b | 3461 | |
c397b908 DV |
3462 | if (drm_gem_object_init(dev, &obj->base, size) != 0) { |
3463 | kfree(obj); | |
3464 | return NULL; | |
3465 | } | |
673a394b | 3466 | |
bed1ea95 CW |
3467 | mask = GFP_HIGHUSER | __GFP_RECLAIMABLE; |
3468 | if (IS_CRESTLINE(dev) || IS_BROADWATER(dev)) { | |
3469 | /* 965gm cannot relocate objects above 4GiB. */ | |
3470 | mask &= ~__GFP_HIGHMEM; | |
3471 | mask |= __GFP_DMA32; | |
3472 | } | |
3473 | ||
5949eac4 | 3474 | mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping; |
bed1ea95 | 3475 | mapping_set_gfp_mask(mapping, mask); |
5949eac4 | 3476 | |
73aa808f CW |
3477 | i915_gem_info_add_obj(dev_priv, size); |
3478 | ||
c397b908 DV |
3479 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; |
3480 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; | |
673a394b | 3481 | |
3d29b842 ED |
3482 | if (HAS_LLC(dev)) { |
3483 | /* On some devices, we can have the GPU use the LLC (the CPU | |
a1871112 EA |
3484 | * cache) for about a 10% performance improvement |
3485 | * compared to uncached. Graphics requests other than | |
3486 | * display scanout are coherent with the CPU in | |
3487 | * accessing this cache. This means in this mode we | |
3488 | * don't need to clflush on the CPU side, and on the | |
3489 | * GPU side we only need to flush internal caches to | |
3490 | * get data visible to the CPU. | |
3491 | * | |
3492 | * However, we maintain the display planes as UC, and so | |
3493 | * need to rebind when first used as such. | |
3494 | */ | |
3495 | obj->cache_level = I915_CACHE_LLC; | |
3496 | } else | |
3497 | obj->cache_level = I915_CACHE_NONE; | |
3498 | ||
62b8b215 | 3499 | obj->base.driver_private = NULL; |
c397b908 | 3500 | obj->fence_reg = I915_FENCE_REG_NONE; |
69dc4987 | 3501 | INIT_LIST_HEAD(&obj->mm_list); |
93a37f20 | 3502 | INIT_LIST_HEAD(&obj->gtt_list); |
69dc4987 | 3503 | INIT_LIST_HEAD(&obj->ring_list); |
432e58ed | 3504 | INIT_LIST_HEAD(&obj->exec_list); |
c397b908 | 3505 | INIT_LIST_HEAD(&obj->gpu_write_list); |
c397b908 | 3506 | obj->madv = I915_MADV_WILLNEED; |
75e9e915 DV |
3507 | /* Avoid an unnecessary call to unbind on the first bind. */ |
3508 | obj->map_and_fenceable = true; | |
de151cf6 | 3509 | |
05394f39 | 3510 | return obj; |
c397b908 DV |
3511 | } |
3512 | ||
3513 | int i915_gem_init_object(struct drm_gem_object *obj) | |
3514 | { | |
3515 | BUG(); | |
de151cf6 | 3516 | |
673a394b EA |
3517 | return 0; |
3518 | } | |
3519 | ||
1488fc08 | 3520 | void i915_gem_free_object(struct drm_gem_object *gem_obj) |
673a394b | 3521 | { |
1488fc08 | 3522 | struct drm_i915_gem_object *obj = to_intel_bo(gem_obj); |
05394f39 | 3523 | struct drm_device *dev = obj->base.dev; |
be72615b | 3524 | drm_i915_private_t *dev_priv = dev->dev_private; |
673a394b | 3525 | |
26e12f89 CW |
3526 | trace_i915_gem_object_destroy(obj); |
3527 | ||
1286ff73 DV |
3528 | if (gem_obj->import_attach) |
3529 | drm_prime_gem_destroy(gem_obj, obj->sg_table); | |
3530 | ||
1488fc08 CW |
3531 | if (obj->phys_obj) |
3532 | i915_gem_detach_phys_object(dev, obj); | |
3533 | ||
3534 | obj->pin_count = 0; | |
3535 | if (WARN_ON(i915_gem_object_unbind(obj) == -ERESTARTSYS)) { | |
3536 | bool was_interruptible; | |
3537 | ||
3538 | was_interruptible = dev_priv->mm.interruptible; | |
3539 | dev_priv->mm.interruptible = false; | |
3540 | ||
3541 | WARN_ON(i915_gem_object_unbind(obj)); | |
3542 | ||
3543 | dev_priv->mm.interruptible = was_interruptible; | |
3544 | } | |
3545 | ||
05394f39 | 3546 | if (obj->base.map_list.map) |
b464e9a2 | 3547 | drm_gem_free_mmap_offset(&obj->base); |
de151cf6 | 3548 | |
05394f39 CW |
3549 | drm_gem_object_release(&obj->base); |
3550 | i915_gem_info_remove_obj(dev_priv, obj->base.size); | |
c397b908 | 3551 | |
05394f39 CW |
3552 | kfree(obj->bit_17); |
3553 | kfree(obj); | |
673a394b EA |
3554 | } |
3555 | ||
29105ccc CW |
3556 | int |
3557 | i915_gem_idle(struct drm_device *dev) | |
3558 | { | |
3559 | drm_i915_private_t *dev_priv = dev->dev_private; | |
3560 | int ret; | |
28dfe52a | 3561 | |
29105ccc | 3562 | mutex_lock(&dev->struct_mutex); |
1c5d22f7 | 3563 | |
87acb0a5 | 3564 | if (dev_priv->mm.suspended) { |
29105ccc CW |
3565 | mutex_unlock(&dev->struct_mutex); |
3566 | return 0; | |
28dfe52a EA |
3567 | } |
3568 | ||
b2da9fe5 | 3569 | ret = i915_gpu_idle(dev); |
6dbe2772 KP |
3570 | if (ret) { |
3571 | mutex_unlock(&dev->struct_mutex); | |
673a394b | 3572 | return ret; |
6dbe2772 | 3573 | } |
b2da9fe5 | 3574 | i915_gem_retire_requests(dev); |
673a394b | 3575 | |
29105ccc | 3576 | /* Under UMS, be paranoid and evict. */ |
a39d7efc CW |
3577 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) |
3578 | i915_gem_evict_everything(dev, false); | |
29105ccc | 3579 | |
312817a3 CW |
3580 | i915_gem_reset_fences(dev); |
3581 | ||
29105ccc CW |
3582 | /* Hack! Don't let anybody do execbuf while we don't control the chip. |
3583 | * We need to replace this with a semaphore, or something. | |
3584 | * And not confound mm.suspended! | |
3585 | */ | |
3586 | dev_priv->mm.suspended = 1; | |
bc0c7f14 | 3587 | del_timer_sync(&dev_priv->hangcheck_timer); |
29105ccc CW |
3588 | |
3589 | i915_kernel_lost_context(dev); | |
6dbe2772 | 3590 | i915_gem_cleanup_ringbuffer(dev); |
29105ccc | 3591 | |
6dbe2772 KP |
3592 | mutex_unlock(&dev->struct_mutex); |
3593 | ||
29105ccc CW |
3594 | /* Cancel the retire work handler, which should be idle now. */ |
3595 | cancel_delayed_work_sync(&dev_priv->mm.retire_work); | |
3596 | ||
673a394b EA |
3597 | return 0; |
3598 | } | |
3599 | ||
b9524a1e BW |
3600 | void i915_gem_l3_remap(struct drm_device *dev) |
3601 | { | |
3602 | drm_i915_private_t *dev_priv = dev->dev_private; | |
3603 | u32 misccpctl; | |
3604 | int i; | |
3605 | ||
3606 | if (!IS_IVYBRIDGE(dev)) | |
3607 | return; | |
3608 | ||
3609 | if (!dev_priv->mm.l3_remap_info) | |
3610 | return; | |
3611 | ||
3612 | misccpctl = I915_READ(GEN7_MISCCPCTL); | |
3613 | I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE); | |
3614 | POSTING_READ(GEN7_MISCCPCTL); | |
3615 | ||
3616 | for (i = 0; i < GEN7_L3LOG_SIZE; i += 4) { | |
3617 | u32 remap = I915_READ(GEN7_L3LOG_BASE + i); | |
3618 | if (remap && remap != dev_priv->mm.l3_remap_info[i/4]) | |
3619 | DRM_DEBUG("0x%x was already programmed to %x\n", | |
3620 | GEN7_L3LOG_BASE + i, remap); | |
3621 | if (remap && !dev_priv->mm.l3_remap_info[i/4]) | |
3622 | DRM_DEBUG_DRIVER("Clearing remapped register\n"); | |
3623 | I915_WRITE(GEN7_L3LOG_BASE + i, dev_priv->mm.l3_remap_info[i/4]); | |
3624 | } | |
3625 | ||
3626 | /* Make sure all the writes land before disabling dop clock gating */ | |
3627 | POSTING_READ(GEN7_L3LOG_BASE); | |
3628 | ||
3629 | I915_WRITE(GEN7_MISCCPCTL, misccpctl); | |
3630 | } | |
3631 | ||
f691e2f4 DV |
3632 | void i915_gem_init_swizzling(struct drm_device *dev) |
3633 | { | |
3634 | drm_i915_private_t *dev_priv = dev->dev_private; | |
3635 | ||
11782b02 | 3636 | if (INTEL_INFO(dev)->gen < 5 || |
f691e2f4 DV |
3637 | dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE) |
3638 | return; | |
3639 | ||
3640 | I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) | | |
3641 | DISP_TILE_SURFACE_SWIZZLING); | |
3642 | ||
11782b02 DV |
3643 | if (IS_GEN5(dev)) |
3644 | return; | |
3645 | ||
f691e2f4 DV |
3646 | I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_SWZCTL); |
3647 | if (IS_GEN6(dev)) | |
6b26c86d | 3648 | I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB)); |
f691e2f4 | 3649 | else |
6b26c86d | 3650 | I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB)); |
f691e2f4 | 3651 | } |
e21af88d DV |
3652 | |
3653 | void i915_gem_init_ppgtt(struct drm_device *dev) | |
3654 | { | |
3655 | drm_i915_private_t *dev_priv = dev->dev_private; | |
3656 | uint32_t pd_offset; | |
3657 | struct intel_ring_buffer *ring; | |
55a254ac DV |
3658 | struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt; |
3659 | uint32_t __iomem *pd_addr; | |
3660 | uint32_t pd_entry; | |
e21af88d DV |
3661 | int i; |
3662 | ||
3663 | if (!dev_priv->mm.aliasing_ppgtt) | |
3664 | return; | |
3665 | ||
55a254ac DV |
3666 | |
3667 | pd_addr = dev_priv->mm.gtt->gtt + ppgtt->pd_offset/sizeof(uint32_t); | |
3668 | for (i = 0; i < ppgtt->num_pd_entries; i++) { | |
3669 | dma_addr_t pt_addr; | |
3670 | ||
3671 | if (dev_priv->mm.gtt->needs_dmar) | |
3672 | pt_addr = ppgtt->pt_dma_addr[i]; | |
3673 | else | |
3674 | pt_addr = page_to_phys(ppgtt->pt_pages[i]); | |
3675 | ||
3676 | pd_entry = GEN6_PDE_ADDR_ENCODE(pt_addr); | |
3677 | pd_entry |= GEN6_PDE_VALID; | |
3678 | ||
3679 | writel(pd_entry, pd_addr + i); | |
3680 | } | |
3681 | readl(pd_addr); | |
3682 | ||
3683 | pd_offset = ppgtt->pd_offset; | |
e21af88d DV |
3684 | pd_offset /= 64; /* in cachelines, */ |
3685 | pd_offset <<= 16; | |
3686 | ||
3687 | if (INTEL_INFO(dev)->gen == 6) { | |
48ecfa10 DV |
3688 | uint32_t ecochk, gab_ctl, ecobits; |
3689 | ||
3690 | ecobits = I915_READ(GAC_ECO_BITS); | |
3691 | I915_WRITE(GAC_ECO_BITS, ecobits | ECOBITS_PPGTT_CACHE64B); | |
be901a5a DV |
3692 | |
3693 | gab_ctl = I915_READ(GAB_CTL); | |
3694 | I915_WRITE(GAB_CTL, gab_ctl | GAB_CTL_CONT_AFTER_PAGEFAULT); | |
3695 | ||
3696 | ecochk = I915_READ(GAM_ECOCHK); | |
e21af88d DV |
3697 | I915_WRITE(GAM_ECOCHK, ecochk | ECOCHK_SNB_BIT | |
3698 | ECOCHK_PPGTT_CACHE64B); | |
6b26c86d | 3699 | I915_WRITE(GFX_MODE, _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE)); |
e21af88d DV |
3700 | } else if (INTEL_INFO(dev)->gen >= 7) { |
3701 | I915_WRITE(GAM_ECOCHK, ECOCHK_PPGTT_CACHE64B); | |
3702 | /* GFX_MODE is per-ring on gen7+ */ | |
3703 | } | |
3704 | ||
b4519513 | 3705 | for_each_ring(ring, dev_priv, i) { |
e21af88d DV |
3706 | if (INTEL_INFO(dev)->gen >= 7) |
3707 | I915_WRITE(RING_MODE_GEN7(ring), | |
6b26c86d | 3708 | _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE)); |
e21af88d DV |
3709 | |
3710 | I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G); | |
3711 | I915_WRITE(RING_PP_DIR_BASE(ring), pd_offset); | |
3712 | } | |
3713 | } | |
3714 | ||
8187a2b7 | 3715 | int |
f691e2f4 | 3716 | i915_gem_init_hw(struct drm_device *dev) |
8187a2b7 ZN |
3717 | { |
3718 | drm_i915_private_t *dev_priv = dev->dev_private; | |
3719 | int ret; | |
68f95ba9 | 3720 | |
8ecd1a66 DV |
3721 | if (!intel_enable_gtt()) |
3722 | return -EIO; | |
3723 | ||
b9524a1e BW |
3724 | i915_gem_l3_remap(dev); |
3725 | ||
f691e2f4 DV |
3726 | i915_gem_init_swizzling(dev); |
3727 | ||
5c1143bb | 3728 | ret = intel_init_render_ring_buffer(dev); |
68f95ba9 | 3729 | if (ret) |
b6913e4b | 3730 | return ret; |
68f95ba9 CW |
3731 | |
3732 | if (HAS_BSD(dev)) { | |
5c1143bb | 3733 | ret = intel_init_bsd_ring_buffer(dev); |
68f95ba9 CW |
3734 | if (ret) |
3735 | goto cleanup_render_ring; | |
d1b851fc | 3736 | } |
68f95ba9 | 3737 | |
549f7365 CW |
3738 | if (HAS_BLT(dev)) { |
3739 | ret = intel_init_blt_ring_buffer(dev); | |
3740 | if (ret) | |
3741 | goto cleanup_bsd_ring; | |
3742 | } | |
3743 | ||
6f392d54 CW |
3744 | dev_priv->next_seqno = 1; |
3745 | ||
254f965c BW |
3746 | /* |
3747 | * XXX: There was some w/a described somewhere suggesting loading | |
3748 | * contexts before PPGTT. | |
3749 | */ | |
3750 | i915_gem_context_init(dev); | |
e21af88d DV |
3751 | i915_gem_init_ppgtt(dev); |
3752 | ||
68f95ba9 CW |
3753 | return 0; |
3754 | ||
549f7365 | 3755 | cleanup_bsd_ring: |
1ec14ad3 | 3756 | intel_cleanup_ring_buffer(&dev_priv->ring[VCS]); |
68f95ba9 | 3757 | cleanup_render_ring: |
1ec14ad3 | 3758 | intel_cleanup_ring_buffer(&dev_priv->ring[RCS]); |
8187a2b7 ZN |
3759 | return ret; |
3760 | } | |
3761 | ||
1070a42b CW |
3762 | static bool |
3763 | intel_enable_ppgtt(struct drm_device *dev) | |
3764 | { | |
3765 | if (i915_enable_ppgtt >= 0) | |
3766 | return i915_enable_ppgtt; | |
3767 | ||
3768 | #ifdef CONFIG_INTEL_IOMMU | |
3769 | /* Disable ppgtt on SNB if VT-d is on. */ | |
3770 | if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped) | |
3771 | return false; | |
3772 | #endif | |
3773 | ||
3774 | return true; | |
3775 | } | |
3776 | ||
3777 | int i915_gem_init(struct drm_device *dev) | |
3778 | { | |
3779 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3780 | unsigned long gtt_size, mappable_size; | |
3781 | int ret; | |
3782 | ||
3783 | gtt_size = dev_priv->mm.gtt->gtt_total_entries << PAGE_SHIFT; | |
3784 | mappable_size = dev_priv->mm.gtt->gtt_mappable_entries << PAGE_SHIFT; | |
3785 | ||
3786 | mutex_lock(&dev->struct_mutex); | |
3787 | if (intel_enable_ppgtt(dev) && HAS_ALIASING_PPGTT(dev)) { | |
3788 | /* PPGTT pdes are stolen from global gtt ptes, so shrink the | |
3789 | * aperture accordingly when using aliasing ppgtt. */ | |
3790 | gtt_size -= I915_PPGTT_PD_ENTRIES*PAGE_SIZE; | |
3791 | ||
3792 | i915_gem_init_global_gtt(dev, 0, mappable_size, gtt_size); | |
3793 | ||
3794 | ret = i915_gem_init_aliasing_ppgtt(dev); | |
3795 | if (ret) { | |
3796 | mutex_unlock(&dev->struct_mutex); | |
3797 | return ret; | |
3798 | } | |
3799 | } else { | |
3800 | /* Let GEM Manage all of the aperture. | |
3801 | * | |
3802 | * However, leave one page at the end still bound to the scratch | |
3803 | * page. There are a number of places where the hardware | |
3804 | * apparently prefetches past the end of the object, and we've | |
3805 | * seen multiple hangs with the GPU head pointer stuck in a | |
3806 | * batchbuffer bound at the last page of the aperture. One page | |
3807 | * should be enough to keep any prefetching inside of the | |
3808 | * aperture. | |
3809 | */ | |
3810 | i915_gem_init_global_gtt(dev, 0, mappable_size, | |
3811 | gtt_size); | |
3812 | } | |
3813 | ||
3814 | ret = i915_gem_init_hw(dev); | |
3815 | mutex_unlock(&dev->struct_mutex); | |
3816 | if (ret) { | |
3817 | i915_gem_cleanup_aliasing_ppgtt(dev); | |
3818 | return ret; | |
3819 | } | |
3820 | ||
53ca26ca DV |
3821 | /* Allow hardware batchbuffers unless told otherwise, but not for KMS. */ |
3822 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) | |
3823 | dev_priv->dri1.allow_batchbuffer = 1; | |
1070a42b CW |
3824 | return 0; |
3825 | } | |
3826 | ||
8187a2b7 ZN |
3827 | void |
3828 | i915_gem_cleanup_ringbuffer(struct drm_device *dev) | |
3829 | { | |
3830 | drm_i915_private_t *dev_priv = dev->dev_private; | |
b4519513 | 3831 | struct intel_ring_buffer *ring; |
1ec14ad3 | 3832 | int i; |
8187a2b7 | 3833 | |
b4519513 CW |
3834 | for_each_ring(ring, dev_priv, i) |
3835 | intel_cleanup_ring_buffer(ring); | |
8187a2b7 ZN |
3836 | } |
3837 | ||
673a394b EA |
3838 | int |
3839 | i915_gem_entervt_ioctl(struct drm_device *dev, void *data, | |
3840 | struct drm_file *file_priv) | |
3841 | { | |
3842 | drm_i915_private_t *dev_priv = dev->dev_private; | |
b4519513 | 3843 | int ret; |
673a394b | 3844 | |
79e53945 JB |
3845 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
3846 | return 0; | |
3847 | ||
ba1234d1 | 3848 | if (atomic_read(&dev_priv->mm.wedged)) { |
673a394b | 3849 | DRM_ERROR("Reenabling wedged hardware, good luck\n"); |
ba1234d1 | 3850 | atomic_set(&dev_priv->mm.wedged, 0); |
673a394b EA |
3851 | } |
3852 | ||
673a394b | 3853 | mutex_lock(&dev->struct_mutex); |
9bb2d6f9 EA |
3854 | dev_priv->mm.suspended = 0; |
3855 | ||
f691e2f4 | 3856 | ret = i915_gem_init_hw(dev); |
d816f6ac WF |
3857 | if (ret != 0) { |
3858 | mutex_unlock(&dev->struct_mutex); | |
9bb2d6f9 | 3859 | return ret; |
d816f6ac | 3860 | } |
9bb2d6f9 | 3861 | |
69dc4987 | 3862 | BUG_ON(!list_empty(&dev_priv->mm.active_list)); |
673a394b EA |
3863 | BUG_ON(!list_empty(&dev_priv->mm.flushing_list)); |
3864 | BUG_ON(!list_empty(&dev_priv->mm.inactive_list)); | |
673a394b | 3865 | mutex_unlock(&dev->struct_mutex); |
dbb19d30 | 3866 | |
5f35308b CW |
3867 | ret = drm_irq_install(dev); |
3868 | if (ret) | |
3869 | goto cleanup_ringbuffer; | |
dbb19d30 | 3870 | |
673a394b | 3871 | return 0; |
5f35308b CW |
3872 | |
3873 | cleanup_ringbuffer: | |
3874 | mutex_lock(&dev->struct_mutex); | |
3875 | i915_gem_cleanup_ringbuffer(dev); | |
3876 | dev_priv->mm.suspended = 1; | |
3877 | mutex_unlock(&dev->struct_mutex); | |
3878 | ||
3879 | return ret; | |
673a394b EA |
3880 | } |
3881 | ||
3882 | int | |
3883 | i915_gem_leavevt_ioctl(struct drm_device *dev, void *data, | |
3884 | struct drm_file *file_priv) | |
3885 | { | |
79e53945 JB |
3886 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
3887 | return 0; | |
3888 | ||
dbb19d30 | 3889 | drm_irq_uninstall(dev); |
e6890f6f | 3890 | return i915_gem_idle(dev); |
673a394b EA |
3891 | } |
3892 | ||
3893 | void | |
3894 | i915_gem_lastclose(struct drm_device *dev) | |
3895 | { | |
3896 | int ret; | |
673a394b | 3897 | |
e806b495 EA |
3898 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
3899 | return; | |
3900 | ||
6dbe2772 KP |
3901 | ret = i915_gem_idle(dev); |
3902 | if (ret) | |
3903 | DRM_ERROR("failed to idle hardware: %d\n", ret); | |
673a394b EA |
3904 | } |
3905 | ||
64193406 CW |
3906 | static void |
3907 | init_ring_lists(struct intel_ring_buffer *ring) | |
3908 | { | |
3909 | INIT_LIST_HEAD(&ring->active_list); | |
3910 | INIT_LIST_HEAD(&ring->request_list); | |
3911 | INIT_LIST_HEAD(&ring->gpu_write_list); | |
3912 | } | |
3913 | ||
673a394b EA |
3914 | void |
3915 | i915_gem_load(struct drm_device *dev) | |
3916 | { | |
b5aa8a0f | 3917 | int i; |
673a394b EA |
3918 | drm_i915_private_t *dev_priv = dev->dev_private; |
3919 | ||
69dc4987 | 3920 | INIT_LIST_HEAD(&dev_priv->mm.active_list); |
673a394b EA |
3921 | INIT_LIST_HEAD(&dev_priv->mm.flushing_list); |
3922 | INIT_LIST_HEAD(&dev_priv->mm.inactive_list); | |
a09ba7fa | 3923 | INIT_LIST_HEAD(&dev_priv->mm.fence_list); |
93a37f20 | 3924 | INIT_LIST_HEAD(&dev_priv->mm.gtt_list); |
1ec14ad3 CW |
3925 | for (i = 0; i < I915_NUM_RINGS; i++) |
3926 | init_ring_lists(&dev_priv->ring[i]); | |
4b9de737 | 3927 | for (i = 0; i < I915_MAX_NUM_FENCES; i++) |
007cc8ac | 3928 | INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list); |
673a394b EA |
3929 | INIT_DELAYED_WORK(&dev_priv->mm.retire_work, |
3930 | i915_gem_retire_work_handler); | |
30dbf0c0 | 3931 | init_completion(&dev_priv->error_completion); |
31169714 | 3932 | |
94400120 DA |
3933 | /* On GEN3 we really need to make sure the ARB C3 LP bit is set */ |
3934 | if (IS_GEN3(dev)) { | |
50743298 DV |
3935 | I915_WRITE(MI_ARB_STATE, |
3936 | _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE)); | |
94400120 DA |
3937 | } |
3938 | ||
72bfa19c CW |
3939 | dev_priv->relative_constants_mode = I915_EXEC_CONSTANTS_REL_GENERAL; |
3940 | ||
de151cf6 | 3941 | /* Old X drivers will take 0-2 for front, back, depth buffers */ |
b397c836 EA |
3942 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) |
3943 | dev_priv->fence_reg_start = 3; | |
de151cf6 | 3944 | |
a6c45cf0 | 3945 | if (INTEL_INFO(dev)->gen >= 4 || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) |
de151cf6 JB |
3946 | dev_priv->num_fence_regs = 16; |
3947 | else | |
3948 | dev_priv->num_fence_regs = 8; | |
3949 | ||
b5aa8a0f | 3950 | /* Initialize fence registers to zero */ |
ada726c7 | 3951 | i915_gem_reset_fences(dev); |
10ed13e4 | 3952 | |
673a394b | 3953 | i915_gem_detect_bit_6_swizzle(dev); |
6b95a207 | 3954 | init_waitqueue_head(&dev_priv->pending_flip_queue); |
17250b71 | 3955 | |
ce453d81 CW |
3956 | dev_priv->mm.interruptible = true; |
3957 | ||
17250b71 CW |
3958 | dev_priv->mm.inactive_shrinker.shrink = i915_gem_inactive_shrink; |
3959 | dev_priv->mm.inactive_shrinker.seeks = DEFAULT_SEEKS; | |
3960 | register_shrinker(&dev_priv->mm.inactive_shrinker); | |
673a394b | 3961 | } |
71acb5eb DA |
3962 | |
3963 | /* | |
3964 | * Create a physically contiguous memory object for this object | |
3965 | * e.g. for cursor + overlay regs | |
3966 | */ | |
995b6762 CW |
3967 | static int i915_gem_init_phys_object(struct drm_device *dev, |
3968 | int id, int size, int align) | |
71acb5eb DA |
3969 | { |
3970 | drm_i915_private_t *dev_priv = dev->dev_private; | |
3971 | struct drm_i915_gem_phys_object *phys_obj; | |
3972 | int ret; | |
3973 | ||
3974 | if (dev_priv->mm.phys_objs[id - 1] || !size) | |
3975 | return 0; | |
3976 | ||
9a298b2a | 3977 | phys_obj = kzalloc(sizeof(struct drm_i915_gem_phys_object), GFP_KERNEL); |
71acb5eb DA |
3978 | if (!phys_obj) |
3979 | return -ENOMEM; | |
3980 | ||
3981 | phys_obj->id = id; | |
3982 | ||
6eeefaf3 | 3983 | phys_obj->handle = drm_pci_alloc(dev, size, align); |
71acb5eb DA |
3984 | if (!phys_obj->handle) { |
3985 | ret = -ENOMEM; | |
3986 | goto kfree_obj; | |
3987 | } | |
3988 | #ifdef CONFIG_X86 | |
3989 | set_memory_wc((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE); | |
3990 | #endif | |
3991 | ||
3992 | dev_priv->mm.phys_objs[id - 1] = phys_obj; | |
3993 | ||
3994 | return 0; | |
3995 | kfree_obj: | |
9a298b2a | 3996 | kfree(phys_obj); |
71acb5eb DA |
3997 | return ret; |
3998 | } | |
3999 | ||
995b6762 | 4000 | static void i915_gem_free_phys_object(struct drm_device *dev, int id) |
71acb5eb DA |
4001 | { |
4002 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4003 | struct drm_i915_gem_phys_object *phys_obj; | |
4004 | ||
4005 | if (!dev_priv->mm.phys_objs[id - 1]) | |
4006 | return; | |
4007 | ||
4008 | phys_obj = dev_priv->mm.phys_objs[id - 1]; | |
4009 | if (phys_obj->cur_obj) { | |
4010 | i915_gem_detach_phys_object(dev, phys_obj->cur_obj); | |
4011 | } | |
4012 | ||
4013 | #ifdef CONFIG_X86 | |
4014 | set_memory_wb((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE); | |
4015 | #endif | |
4016 | drm_pci_free(dev, phys_obj->handle); | |
4017 | kfree(phys_obj); | |
4018 | dev_priv->mm.phys_objs[id - 1] = NULL; | |
4019 | } | |
4020 | ||
4021 | void i915_gem_free_all_phys_object(struct drm_device *dev) | |
4022 | { | |
4023 | int i; | |
4024 | ||
260883c8 | 4025 | for (i = I915_GEM_PHYS_CURSOR_0; i <= I915_MAX_PHYS_OBJECT; i++) |
71acb5eb DA |
4026 | i915_gem_free_phys_object(dev, i); |
4027 | } | |
4028 | ||
4029 | void i915_gem_detach_phys_object(struct drm_device *dev, | |
05394f39 | 4030 | struct drm_i915_gem_object *obj) |
71acb5eb | 4031 | { |
05394f39 | 4032 | struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping; |
e5281ccd | 4033 | char *vaddr; |
71acb5eb | 4034 | int i; |
71acb5eb DA |
4035 | int page_count; |
4036 | ||
05394f39 | 4037 | if (!obj->phys_obj) |
71acb5eb | 4038 | return; |
05394f39 | 4039 | vaddr = obj->phys_obj->handle->vaddr; |
71acb5eb | 4040 | |
05394f39 | 4041 | page_count = obj->base.size / PAGE_SIZE; |
71acb5eb | 4042 | for (i = 0; i < page_count; i++) { |
5949eac4 | 4043 | struct page *page = shmem_read_mapping_page(mapping, i); |
e5281ccd CW |
4044 | if (!IS_ERR(page)) { |
4045 | char *dst = kmap_atomic(page); | |
4046 | memcpy(dst, vaddr + i*PAGE_SIZE, PAGE_SIZE); | |
4047 | kunmap_atomic(dst); | |
4048 | ||
4049 | drm_clflush_pages(&page, 1); | |
4050 | ||
4051 | set_page_dirty(page); | |
4052 | mark_page_accessed(page); | |
4053 | page_cache_release(page); | |
4054 | } | |
71acb5eb | 4055 | } |
40ce6575 | 4056 | intel_gtt_chipset_flush(); |
d78b47b9 | 4057 | |
05394f39 CW |
4058 | obj->phys_obj->cur_obj = NULL; |
4059 | obj->phys_obj = NULL; | |
71acb5eb DA |
4060 | } |
4061 | ||
4062 | int | |
4063 | i915_gem_attach_phys_object(struct drm_device *dev, | |
05394f39 | 4064 | struct drm_i915_gem_object *obj, |
6eeefaf3 CW |
4065 | int id, |
4066 | int align) | |
71acb5eb | 4067 | { |
05394f39 | 4068 | struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping; |
71acb5eb | 4069 | drm_i915_private_t *dev_priv = dev->dev_private; |
71acb5eb DA |
4070 | int ret = 0; |
4071 | int page_count; | |
4072 | int i; | |
4073 | ||
4074 | if (id > I915_MAX_PHYS_OBJECT) | |
4075 | return -EINVAL; | |
4076 | ||
05394f39 CW |
4077 | if (obj->phys_obj) { |
4078 | if (obj->phys_obj->id == id) | |
71acb5eb DA |
4079 | return 0; |
4080 | i915_gem_detach_phys_object(dev, obj); | |
4081 | } | |
4082 | ||
71acb5eb DA |
4083 | /* create a new object */ |
4084 | if (!dev_priv->mm.phys_objs[id - 1]) { | |
4085 | ret = i915_gem_init_phys_object(dev, id, | |
05394f39 | 4086 | obj->base.size, align); |
71acb5eb | 4087 | if (ret) { |
05394f39 CW |
4088 | DRM_ERROR("failed to init phys object %d size: %zu\n", |
4089 | id, obj->base.size); | |
e5281ccd | 4090 | return ret; |
71acb5eb DA |
4091 | } |
4092 | } | |
4093 | ||
4094 | /* bind to the object */ | |
05394f39 CW |
4095 | obj->phys_obj = dev_priv->mm.phys_objs[id - 1]; |
4096 | obj->phys_obj->cur_obj = obj; | |
71acb5eb | 4097 | |
05394f39 | 4098 | page_count = obj->base.size / PAGE_SIZE; |
71acb5eb DA |
4099 | |
4100 | for (i = 0; i < page_count; i++) { | |
e5281ccd CW |
4101 | struct page *page; |
4102 | char *dst, *src; | |
4103 | ||
5949eac4 | 4104 | page = shmem_read_mapping_page(mapping, i); |
e5281ccd CW |
4105 | if (IS_ERR(page)) |
4106 | return PTR_ERR(page); | |
71acb5eb | 4107 | |
ff75b9bc | 4108 | src = kmap_atomic(page); |
05394f39 | 4109 | dst = obj->phys_obj->handle->vaddr + (i * PAGE_SIZE); |
71acb5eb | 4110 | memcpy(dst, src, PAGE_SIZE); |
3e4d3af5 | 4111 | kunmap_atomic(src); |
71acb5eb | 4112 | |
e5281ccd CW |
4113 | mark_page_accessed(page); |
4114 | page_cache_release(page); | |
4115 | } | |
d78b47b9 | 4116 | |
71acb5eb | 4117 | return 0; |
71acb5eb DA |
4118 | } |
4119 | ||
4120 | static int | |
05394f39 CW |
4121 | i915_gem_phys_pwrite(struct drm_device *dev, |
4122 | struct drm_i915_gem_object *obj, | |
71acb5eb DA |
4123 | struct drm_i915_gem_pwrite *args, |
4124 | struct drm_file *file_priv) | |
4125 | { | |
05394f39 | 4126 | void *vaddr = obj->phys_obj->handle->vaddr + args->offset; |
b47b30cc | 4127 | char __user *user_data = (char __user *) (uintptr_t) args->data_ptr; |
71acb5eb | 4128 | |
b47b30cc CW |
4129 | if (__copy_from_user_inatomic_nocache(vaddr, user_data, args->size)) { |
4130 | unsigned long unwritten; | |
4131 | ||
4132 | /* The physical object once assigned is fixed for the lifetime | |
4133 | * of the obj, so we can safely drop the lock and continue | |
4134 | * to access vaddr. | |
4135 | */ | |
4136 | mutex_unlock(&dev->struct_mutex); | |
4137 | unwritten = copy_from_user(vaddr, user_data, args->size); | |
4138 | mutex_lock(&dev->struct_mutex); | |
4139 | if (unwritten) | |
4140 | return -EFAULT; | |
4141 | } | |
71acb5eb | 4142 | |
40ce6575 | 4143 | intel_gtt_chipset_flush(); |
71acb5eb DA |
4144 | return 0; |
4145 | } | |
b962442e | 4146 | |
f787a5f5 | 4147 | void i915_gem_release(struct drm_device *dev, struct drm_file *file) |
b962442e | 4148 | { |
f787a5f5 | 4149 | struct drm_i915_file_private *file_priv = file->driver_priv; |
b962442e EA |
4150 | |
4151 | /* Clean up our request list when the client is going away, so that | |
4152 | * later retire_requests won't dereference our soon-to-be-gone | |
4153 | * file_priv. | |
4154 | */ | |
1c25595f | 4155 | spin_lock(&file_priv->mm.lock); |
f787a5f5 CW |
4156 | while (!list_empty(&file_priv->mm.request_list)) { |
4157 | struct drm_i915_gem_request *request; | |
4158 | ||
4159 | request = list_first_entry(&file_priv->mm.request_list, | |
4160 | struct drm_i915_gem_request, | |
4161 | client_list); | |
4162 | list_del(&request->client_list); | |
4163 | request->file_priv = NULL; | |
4164 | } | |
1c25595f | 4165 | spin_unlock(&file_priv->mm.lock); |
b962442e | 4166 | } |
31169714 | 4167 | |
1637ef41 CW |
4168 | static int |
4169 | i915_gpu_is_active(struct drm_device *dev) | |
4170 | { | |
4171 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4172 | int lists_empty; | |
4173 | ||
1637ef41 | 4174 | lists_empty = list_empty(&dev_priv->mm.flushing_list) && |
17250b71 | 4175 | list_empty(&dev_priv->mm.active_list); |
1637ef41 CW |
4176 | |
4177 | return !lists_empty; | |
4178 | } | |
4179 | ||
31169714 | 4180 | static int |
1495f230 | 4181 | i915_gem_inactive_shrink(struct shrinker *shrinker, struct shrink_control *sc) |
31169714 | 4182 | { |
17250b71 CW |
4183 | struct drm_i915_private *dev_priv = |
4184 | container_of(shrinker, | |
4185 | struct drm_i915_private, | |
4186 | mm.inactive_shrinker); | |
4187 | struct drm_device *dev = dev_priv->dev; | |
4188 | struct drm_i915_gem_object *obj, *next; | |
1495f230 | 4189 | int nr_to_scan = sc->nr_to_scan; |
17250b71 CW |
4190 | int cnt; |
4191 | ||
4192 | if (!mutex_trylock(&dev->struct_mutex)) | |
bbe2e11a | 4193 | return 0; |
31169714 CW |
4194 | |
4195 | /* "fast-path" to count number of available objects */ | |
4196 | if (nr_to_scan == 0) { | |
17250b71 CW |
4197 | cnt = 0; |
4198 | list_for_each_entry(obj, | |
4199 | &dev_priv->mm.inactive_list, | |
4200 | mm_list) | |
4201 | cnt++; | |
4202 | mutex_unlock(&dev->struct_mutex); | |
4203 | return cnt / 100 * sysctl_vfs_cache_pressure; | |
31169714 CW |
4204 | } |
4205 | ||
1637ef41 | 4206 | rescan: |
31169714 | 4207 | /* first scan for clean buffers */ |
17250b71 | 4208 | i915_gem_retire_requests(dev); |
31169714 | 4209 | |
17250b71 CW |
4210 | list_for_each_entry_safe(obj, next, |
4211 | &dev_priv->mm.inactive_list, | |
4212 | mm_list) { | |
4213 | if (i915_gem_object_is_purgeable(obj)) { | |
2021746e CW |
4214 | if (i915_gem_object_unbind(obj) == 0 && |
4215 | --nr_to_scan == 0) | |
17250b71 | 4216 | break; |
31169714 | 4217 | } |
31169714 CW |
4218 | } |
4219 | ||
4220 | /* second pass, evict/count anything still on the inactive list */ | |
17250b71 CW |
4221 | cnt = 0; |
4222 | list_for_each_entry_safe(obj, next, | |
4223 | &dev_priv->mm.inactive_list, | |
4224 | mm_list) { | |
2021746e CW |
4225 | if (nr_to_scan && |
4226 | i915_gem_object_unbind(obj) == 0) | |
17250b71 | 4227 | nr_to_scan--; |
2021746e | 4228 | else |
17250b71 CW |
4229 | cnt++; |
4230 | } | |
4231 | ||
4232 | if (nr_to_scan && i915_gpu_is_active(dev)) { | |
1637ef41 CW |
4233 | /* |
4234 | * We are desperate for pages, so as a last resort, wait | |
4235 | * for the GPU to finish and discard whatever we can. | |
4236 | * This has a dramatic impact to reduce the number of | |
4237 | * OOM-killer events whilst running the GPU aggressively. | |
4238 | */ | |
b2da9fe5 | 4239 | if (i915_gpu_idle(dev) == 0) |
1637ef41 CW |
4240 | goto rescan; |
4241 | } | |
17250b71 CW |
4242 | mutex_unlock(&dev->struct_mutex); |
4243 | return cnt / 100 * sysctl_vfs_cache_pressure; | |
31169714 | 4244 | } |