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Commit | Line | Data |
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673a394b EA |
1 | /* |
2 | * Copyright © 2008 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | * | |
26 | */ | |
27 | ||
760285e7 | 28 | #include <drm/drmP.h> |
0de23977 | 29 | #include <drm/drm_vma_manager.h> |
760285e7 | 30 | #include <drm/i915_drm.h> |
673a394b | 31 | #include "i915_drv.h" |
1c5d22f7 | 32 | #include "i915_trace.h" |
652c393a | 33 | #include "intel_drv.h" |
5949eac4 | 34 | #include <linux/shmem_fs.h> |
5a0e3ad6 | 35 | #include <linux/slab.h> |
673a394b | 36 | #include <linux/swap.h> |
79e53945 | 37 | #include <linux/pci.h> |
1286ff73 | 38 | #include <linux/dma-buf.h> |
673a394b | 39 | |
05394f39 | 40 | static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj); |
2c22569b CW |
41 | static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj, |
42 | bool force); | |
07fe0b12 | 43 | static __must_check int |
23f54483 BW |
44 | i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj, |
45 | bool readonly); | |
46 | static __must_check int | |
07fe0b12 BW |
47 | i915_gem_object_bind_to_vm(struct drm_i915_gem_object *obj, |
48 | struct i915_address_space *vm, | |
49 | unsigned alignment, | |
50 | bool map_and_fenceable, | |
51 | bool nonblocking); | |
05394f39 CW |
52 | static int i915_gem_phys_pwrite(struct drm_device *dev, |
53 | struct drm_i915_gem_object *obj, | |
71acb5eb | 54 | struct drm_i915_gem_pwrite *args, |
05394f39 | 55 | struct drm_file *file); |
673a394b | 56 | |
61050808 CW |
57 | static void i915_gem_write_fence(struct drm_device *dev, int reg, |
58 | struct drm_i915_gem_object *obj); | |
59 | static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj, | |
60 | struct drm_i915_fence_reg *fence, | |
61 | bool enable); | |
62 | ||
7dc19d5a DC |
63 | static unsigned long i915_gem_inactive_count(struct shrinker *shrinker, |
64 | struct shrink_control *sc); | |
65 | static unsigned long i915_gem_inactive_scan(struct shrinker *shrinker, | |
66 | struct shrink_control *sc); | |
d9973b43 CW |
67 | static unsigned long i915_gem_purge(struct drm_i915_private *dev_priv, long target); |
68 | static unsigned long i915_gem_shrink_all(struct drm_i915_private *dev_priv); | |
8c59967c | 69 | static void i915_gem_object_truncate(struct drm_i915_gem_object *obj); |
31169714 | 70 | |
c76ce038 CW |
71 | static bool cpu_cache_is_coherent(struct drm_device *dev, |
72 | enum i915_cache_level level) | |
73 | { | |
74 | return HAS_LLC(dev) || level != I915_CACHE_NONE; | |
75 | } | |
76 | ||
2c22569b CW |
77 | static bool cpu_write_needs_clflush(struct drm_i915_gem_object *obj) |
78 | { | |
79 | if (!cpu_cache_is_coherent(obj->base.dev, obj->cache_level)) | |
80 | return true; | |
81 | ||
82 | return obj->pin_display; | |
83 | } | |
84 | ||
61050808 CW |
85 | static inline void i915_gem_object_fence_lost(struct drm_i915_gem_object *obj) |
86 | { | |
87 | if (obj->tiling_mode) | |
88 | i915_gem_release_mmap(obj); | |
89 | ||
90 | /* As we do not have an associated fence register, we will force | |
91 | * a tiling change if we ever need to acquire one. | |
92 | */ | |
5d82e3e6 | 93 | obj->fence_dirty = false; |
61050808 CW |
94 | obj->fence_reg = I915_FENCE_REG_NONE; |
95 | } | |
96 | ||
73aa808f CW |
97 | /* some bookkeeping */ |
98 | static void i915_gem_info_add_obj(struct drm_i915_private *dev_priv, | |
99 | size_t size) | |
100 | { | |
c20e8355 | 101 | spin_lock(&dev_priv->mm.object_stat_lock); |
73aa808f CW |
102 | dev_priv->mm.object_count++; |
103 | dev_priv->mm.object_memory += size; | |
c20e8355 | 104 | spin_unlock(&dev_priv->mm.object_stat_lock); |
73aa808f CW |
105 | } |
106 | ||
107 | static void i915_gem_info_remove_obj(struct drm_i915_private *dev_priv, | |
108 | size_t size) | |
109 | { | |
c20e8355 | 110 | spin_lock(&dev_priv->mm.object_stat_lock); |
73aa808f CW |
111 | dev_priv->mm.object_count--; |
112 | dev_priv->mm.object_memory -= size; | |
c20e8355 | 113 | spin_unlock(&dev_priv->mm.object_stat_lock); |
73aa808f CW |
114 | } |
115 | ||
21dd3734 | 116 | static int |
33196ded | 117 | i915_gem_wait_for_error(struct i915_gpu_error *error) |
30dbf0c0 | 118 | { |
30dbf0c0 CW |
119 | int ret; |
120 | ||
7abb690a DV |
121 | #define EXIT_COND (!i915_reset_in_progress(error) || \ |
122 | i915_terminally_wedged(error)) | |
1f83fee0 | 123 | if (EXIT_COND) |
30dbf0c0 CW |
124 | return 0; |
125 | ||
0a6759c6 DV |
126 | /* |
127 | * Only wait 10 seconds for the gpu reset to complete to avoid hanging | |
128 | * userspace. If it takes that long something really bad is going on and | |
129 | * we should simply try to bail out and fail as gracefully as possible. | |
130 | */ | |
1f83fee0 DV |
131 | ret = wait_event_interruptible_timeout(error->reset_queue, |
132 | EXIT_COND, | |
133 | 10*HZ); | |
0a6759c6 DV |
134 | if (ret == 0) { |
135 | DRM_ERROR("Timed out waiting for the gpu reset to complete\n"); | |
136 | return -EIO; | |
137 | } else if (ret < 0) { | |
30dbf0c0 | 138 | return ret; |
0a6759c6 | 139 | } |
1f83fee0 | 140 | #undef EXIT_COND |
30dbf0c0 | 141 | |
21dd3734 | 142 | return 0; |
30dbf0c0 CW |
143 | } |
144 | ||
54cf91dc | 145 | int i915_mutex_lock_interruptible(struct drm_device *dev) |
76c1dec1 | 146 | { |
33196ded | 147 | struct drm_i915_private *dev_priv = dev->dev_private; |
76c1dec1 CW |
148 | int ret; |
149 | ||
33196ded | 150 | ret = i915_gem_wait_for_error(&dev_priv->gpu_error); |
76c1dec1 CW |
151 | if (ret) |
152 | return ret; | |
153 | ||
154 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
155 | if (ret) | |
156 | return ret; | |
157 | ||
23bc5982 | 158 | WARN_ON(i915_verify_lists(dev)); |
76c1dec1 CW |
159 | return 0; |
160 | } | |
30dbf0c0 | 161 | |
7d1c4804 | 162 | static inline bool |
05394f39 | 163 | i915_gem_object_is_inactive(struct drm_i915_gem_object *obj) |
7d1c4804 | 164 | { |
9843877d | 165 | return i915_gem_obj_bound_any(obj) && !obj->active; |
7d1c4804 CW |
166 | } |
167 | ||
79e53945 JB |
168 | int |
169 | i915_gem_init_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 170 | struct drm_file *file) |
79e53945 | 171 | { |
93d18799 | 172 | struct drm_i915_private *dev_priv = dev->dev_private; |
79e53945 | 173 | struct drm_i915_gem_init *args = data; |
2021746e | 174 | |
7bb6fb8d DV |
175 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
176 | return -ENODEV; | |
177 | ||
2021746e CW |
178 | if (args->gtt_start >= args->gtt_end || |
179 | (args->gtt_end | args->gtt_start) & (PAGE_SIZE - 1)) | |
180 | return -EINVAL; | |
79e53945 | 181 | |
f534bc0b DV |
182 | /* GEM with user mode setting was never supported on ilk and later. */ |
183 | if (INTEL_INFO(dev)->gen >= 5) | |
184 | return -ENODEV; | |
185 | ||
79e53945 | 186 | mutex_lock(&dev->struct_mutex); |
d7e5008f BW |
187 | i915_gem_setup_global_gtt(dev, args->gtt_start, args->gtt_end, |
188 | args->gtt_end); | |
93d18799 | 189 | dev_priv->gtt.mappable_end = args->gtt_end; |
673a394b EA |
190 | mutex_unlock(&dev->struct_mutex); |
191 | ||
2021746e | 192 | return 0; |
673a394b EA |
193 | } |
194 | ||
5a125c3c EA |
195 | int |
196 | i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 197 | struct drm_file *file) |
5a125c3c | 198 | { |
73aa808f | 199 | struct drm_i915_private *dev_priv = dev->dev_private; |
5a125c3c | 200 | struct drm_i915_gem_get_aperture *args = data; |
6299f992 CW |
201 | struct drm_i915_gem_object *obj; |
202 | size_t pinned; | |
5a125c3c | 203 | |
6299f992 | 204 | pinned = 0; |
73aa808f | 205 | mutex_lock(&dev->struct_mutex); |
35c20a60 | 206 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) |
d7f46fc4 | 207 | if (i915_gem_obj_is_pinned(obj)) |
f343c5f6 | 208 | pinned += i915_gem_obj_ggtt_size(obj); |
73aa808f | 209 | mutex_unlock(&dev->struct_mutex); |
5a125c3c | 210 | |
853ba5d2 | 211 | args->aper_size = dev_priv->gtt.base.total; |
0206e353 | 212 | args->aper_available_size = args->aper_size - pinned; |
6299f992 | 213 | |
5a125c3c EA |
214 | return 0; |
215 | } | |
216 | ||
42dcedd4 CW |
217 | void *i915_gem_object_alloc(struct drm_device *dev) |
218 | { | |
219 | struct drm_i915_private *dev_priv = dev->dev_private; | |
fac15c10 | 220 | return kmem_cache_zalloc(dev_priv->slab, GFP_KERNEL); |
42dcedd4 CW |
221 | } |
222 | ||
223 | void i915_gem_object_free(struct drm_i915_gem_object *obj) | |
224 | { | |
225 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; | |
226 | kmem_cache_free(dev_priv->slab, obj); | |
227 | } | |
228 | ||
ff72145b DA |
229 | static int |
230 | i915_gem_create(struct drm_file *file, | |
231 | struct drm_device *dev, | |
232 | uint64_t size, | |
233 | uint32_t *handle_p) | |
673a394b | 234 | { |
05394f39 | 235 | struct drm_i915_gem_object *obj; |
a1a2d1d3 PP |
236 | int ret; |
237 | u32 handle; | |
673a394b | 238 | |
ff72145b | 239 | size = roundup(size, PAGE_SIZE); |
8ffc0246 CW |
240 | if (size == 0) |
241 | return -EINVAL; | |
673a394b EA |
242 | |
243 | /* Allocate the new object */ | |
ff72145b | 244 | obj = i915_gem_alloc_object(dev, size); |
673a394b EA |
245 | if (obj == NULL) |
246 | return -ENOMEM; | |
247 | ||
05394f39 | 248 | ret = drm_gem_handle_create(file, &obj->base, &handle); |
202f2fef | 249 | /* drop reference from allocate - handle holds it now */ |
d861e338 DV |
250 | drm_gem_object_unreference_unlocked(&obj->base); |
251 | if (ret) | |
252 | return ret; | |
202f2fef | 253 | |
ff72145b | 254 | *handle_p = handle; |
673a394b EA |
255 | return 0; |
256 | } | |
257 | ||
ff72145b DA |
258 | int |
259 | i915_gem_dumb_create(struct drm_file *file, | |
260 | struct drm_device *dev, | |
261 | struct drm_mode_create_dumb *args) | |
262 | { | |
263 | /* have to work out size/pitch and return them */ | |
de45eaf7 | 264 | args->pitch = ALIGN(args->width * DIV_ROUND_UP(args->bpp, 8), 64); |
ff72145b DA |
265 | args->size = args->pitch * args->height; |
266 | return i915_gem_create(file, dev, | |
267 | args->size, &args->handle); | |
268 | } | |
269 | ||
ff72145b DA |
270 | /** |
271 | * Creates a new mm object and returns a handle to it. | |
272 | */ | |
273 | int | |
274 | i915_gem_create_ioctl(struct drm_device *dev, void *data, | |
275 | struct drm_file *file) | |
276 | { | |
277 | struct drm_i915_gem_create *args = data; | |
63ed2cb2 | 278 | |
ff72145b DA |
279 | return i915_gem_create(file, dev, |
280 | args->size, &args->handle); | |
281 | } | |
282 | ||
8461d226 DV |
283 | static inline int |
284 | __copy_to_user_swizzled(char __user *cpu_vaddr, | |
285 | const char *gpu_vaddr, int gpu_offset, | |
286 | int length) | |
287 | { | |
288 | int ret, cpu_offset = 0; | |
289 | ||
290 | while (length > 0) { | |
291 | int cacheline_end = ALIGN(gpu_offset + 1, 64); | |
292 | int this_length = min(cacheline_end - gpu_offset, length); | |
293 | int swizzled_gpu_offset = gpu_offset ^ 64; | |
294 | ||
295 | ret = __copy_to_user(cpu_vaddr + cpu_offset, | |
296 | gpu_vaddr + swizzled_gpu_offset, | |
297 | this_length); | |
298 | if (ret) | |
299 | return ret + length; | |
300 | ||
301 | cpu_offset += this_length; | |
302 | gpu_offset += this_length; | |
303 | length -= this_length; | |
304 | } | |
305 | ||
306 | return 0; | |
307 | } | |
308 | ||
8c59967c | 309 | static inline int |
4f0c7cfb BW |
310 | __copy_from_user_swizzled(char *gpu_vaddr, int gpu_offset, |
311 | const char __user *cpu_vaddr, | |
8c59967c DV |
312 | int length) |
313 | { | |
314 | int ret, cpu_offset = 0; | |
315 | ||
316 | while (length > 0) { | |
317 | int cacheline_end = ALIGN(gpu_offset + 1, 64); | |
318 | int this_length = min(cacheline_end - gpu_offset, length); | |
319 | int swizzled_gpu_offset = gpu_offset ^ 64; | |
320 | ||
321 | ret = __copy_from_user(gpu_vaddr + swizzled_gpu_offset, | |
322 | cpu_vaddr + cpu_offset, | |
323 | this_length); | |
324 | if (ret) | |
325 | return ret + length; | |
326 | ||
327 | cpu_offset += this_length; | |
328 | gpu_offset += this_length; | |
329 | length -= this_length; | |
330 | } | |
331 | ||
332 | return 0; | |
333 | } | |
334 | ||
d174bd64 DV |
335 | /* Per-page copy function for the shmem pread fastpath. |
336 | * Flushes invalid cachelines before reading the target if | |
337 | * needs_clflush is set. */ | |
eb01459f | 338 | static int |
d174bd64 DV |
339 | shmem_pread_fast(struct page *page, int shmem_page_offset, int page_length, |
340 | char __user *user_data, | |
341 | bool page_do_bit17_swizzling, bool needs_clflush) | |
342 | { | |
343 | char *vaddr; | |
344 | int ret; | |
345 | ||
e7e58eb5 | 346 | if (unlikely(page_do_bit17_swizzling)) |
d174bd64 DV |
347 | return -EINVAL; |
348 | ||
349 | vaddr = kmap_atomic(page); | |
350 | if (needs_clflush) | |
351 | drm_clflush_virt_range(vaddr + shmem_page_offset, | |
352 | page_length); | |
353 | ret = __copy_to_user_inatomic(user_data, | |
354 | vaddr + shmem_page_offset, | |
355 | page_length); | |
356 | kunmap_atomic(vaddr); | |
357 | ||
f60d7f0c | 358 | return ret ? -EFAULT : 0; |
d174bd64 DV |
359 | } |
360 | ||
23c18c71 DV |
361 | static void |
362 | shmem_clflush_swizzled_range(char *addr, unsigned long length, | |
363 | bool swizzled) | |
364 | { | |
e7e58eb5 | 365 | if (unlikely(swizzled)) { |
23c18c71 DV |
366 | unsigned long start = (unsigned long) addr; |
367 | unsigned long end = (unsigned long) addr + length; | |
368 | ||
369 | /* For swizzling simply ensure that we always flush both | |
370 | * channels. Lame, but simple and it works. Swizzled | |
371 | * pwrite/pread is far from a hotpath - current userspace | |
372 | * doesn't use it at all. */ | |
373 | start = round_down(start, 128); | |
374 | end = round_up(end, 128); | |
375 | ||
376 | drm_clflush_virt_range((void *)start, end - start); | |
377 | } else { | |
378 | drm_clflush_virt_range(addr, length); | |
379 | } | |
380 | ||
381 | } | |
382 | ||
d174bd64 DV |
383 | /* Only difference to the fast-path function is that this can handle bit17 |
384 | * and uses non-atomic copy and kmap functions. */ | |
385 | static int | |
386 | shmem_pread_slow(struct page *page, int shmem_page_offset, int page_length, | |
387 | char __user *user_data, | |
388 | bool page_do_bit17_swizzling, bool needs_clflush) | |
389 | { | |
390 | char *vaddr; | |
391 | int ret; | |
392 | ||
393 | vaddr = kmap(page); | |
394 | if (needs_clflush) | |
23c18c71 DV |
395 | shmem_clflush_swizzled_range(vaddr + shmem_page_offset, |
396 | page_length, | |
397 | page_do_bit17_swizzling); | |
d174bd64 DV |
398 | |
399 | if (page_do_bit17_swizzling) | |
400 | ret = __copy_to_user_swizzled(user_data, | |
401 | vaddr, shmem_page_offset, | |
402 | page_length); | |
403 | else | |
404 | ret = __copy_to_user(user_data, | |
405 | vaddr + shmem_page_offset, | |
406 | page_length); | |
407 | kunmap(page); | |
408 | ||
f60d7f0c | 409 | return ret ? - EFAULT : 0; |
d174bd64 DV |
410 | } |
411 | ||
eb01459f | 412 | static int |
dbf7bff0 DV |
413 | i915_gem_shmem_pread(struct drm_device *dev, |
414 | struct drm_i915_gem_object *obj, | |
415 | struct drm_i915_gem_pread *args, | |
416 | struct drm_file *file) | |
eb01459f | 417 | { |
8461d226 | 418 | char __user *user_data; |
eb01459f | 419 | ssize_t remain; |
8461d226 | 420 | loff_t offset; |
eb2c0c81 | 421 | int shmem_page_offset, page_length, ret = 0; |
8461d226 | 422 | int obj_do_bit17_swizzling, page_do_bit17_swizzling; |
96d79b52 | 423 | int prefaulted = 0; |
8489731c | 424 | int needs_clflush = 0; |
67d5a50c | 425 | struct sg_page_iter sg_iter; |
eb01459f | 426 | |
2bb4629a | 427 | user_data = to_user_ptr(args->data_ptr); |
eb01459f EA |
428 | remain = args->size; |
429 | ||
8461d226 | 430 | obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj); |
eb01459f | 431 | |
8489731c DV |
432 | if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU)) { |
433 | /* If we're not in the cpu read domain, set ourself into the gtt | |
434 | * read domain and manually flush cachelines (if required). This | |
435 | * optimizes for the case when the gpu will dirty the data | |
436 | * anyway again before the next pread happens. */ | |
c76ce038 | 437 | needs_clflush = !cpu_cache_is_coherent(dev, obj->cache_level); |
23f54483 BW |
438 | ret = i915_gem_object_wait_rendering(obj, true); |
439 | if (ret) | |
440 | return ret; | |
8489731c | 441 | } |
eb01459f | 442 | |
f60d7f0c CW |
443 | ret = i915_gem_object_get_pages(obj); |
444 | if (ret) | |
445 | return ret; | |
446 | ||
447 | i915_gem_object_pin_pages(obj); | |
448 | ||
8461d226 | 449 | offset = args->offset; |
eb01459f | 450 | |
67d5a50c ID |
451 | for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, |
452 | offset >> PAGE_SHIFT) { | |
2db76d7c | 453 | struct page *page = sg_page_iter_page(&sg_iter); |
9da3da66 CW |
454 | |
455 | if (remain <= 0) | |
456 | break; | |
457 | ||
eb01459f EA |
458 | /* Operation in this page |
459 | * | |
eb01459f | 460 | * shmem_page_offset = offset within page in shmem file |
eb01459f EA |
461 | * page_length = bytes to copy for this page |
462 | */ | |
c8cbbb8b | 463 | shmem_page_offset = offset_in_page(offset); |
eb01459f EA |
464 | page_length = remain; |
465 | if ((shmem_page_offset + page_length) > PAGE_SIZE) | |
466 | page_length = PAGE_SIZE - shmem_page_offset; | |
eb01459f | 467 | |
8461d226 DV |
468 | page_do_bit17_swizzling = obj_do_bit17_swizzling && |
469 | (page_to_phys(page) & (1 << 17)) != 0; | |
470 | ||
d174bd64 DV |
471 | ret = shmem_pread_fast(page, shmem_page_offset, page_length, |
472 | user_data, page_do_bit17_swizzling, | |
473 | needs_clflush); | |
474 | if (ret == 0) | |
475 | goto next_page; | |
dbf7bff0 | 476 | |
dbf7bff0 DV |
477 | mutex_unlock(&dev->struct_mutex); |
478 | ||
0b74b508 | 479 | if (likely(!i915_prefault_disable) && !prefaulted) { |
f56f821f | 480 | ret = fault_in_multipages_writeable(user_data, remain); |
96d79b52 DV |
481 | /* Userspace is tricking us, but we've already clobbered |
482 | * its pages with the prefault and promised to write the | |
483 | * data up to the first fault. Hence ignore any errors | |
484 | * and just continue. */ | |
485 | (void)ret; | |
486 | prefaulted = 1; | |
487 | } | |
eb01459f | 488 | |
d174bd64 DV |
489 | ret = shmem_pread_slow(page, shmem_page_offset, page_length, |
490 | user_data, page_do_bit17_swizzling, | |
491 | needs_clflush); | |
eb01459f | 492 | |
dbf7bff0 | 493 | mutex_lock(&dev->struct_mutex); |
f60d7f0c | 494 | |
dbf7bff0 | 495 | next_page: |
e5281ccd | 496 | mark_page_accessed(page); |
e5281ccd | 497 | |
f60d7f0c | 498 | if (ret) |
8461d226 | 499 | goto out; |
8461d226 | 500 | |
eb01459f | 501 | remain -= page_length; |
8461d226 | 502 | user_data += page_length; |
eb01459f EA |
503 | offset += page_length; |
504 | } | |
505 | ||
4f27b75d | 506 | out: |
f60d7f0c CW |
507 | i915_gem_object_unpin_pages(obj); |
508 | ||
eb01459f EA |
509 | return ret; |
510 | } | |
511 | ||
673a394b EA |
512 | /** |
513 | * Reads data from the object referenced by handle. | |
514 | * | |
515 | * On error, the contents of *data are undefined. | |
516 | */ | |
517 | int | |
518 | i915_gem_pread_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 519 | struct drm_file *file) |
673a394b EA |
520 | { |
521 | struct drm_i915_gem_pread *args = data; | |
05394f39 | 522 | struct drm_i915_gem_object *obj; |
35b62a89 | 523 | int ret = 0; |
673a394b | 524 | |
51311d0a CW |
525 | if (args->size == 0) |
526 | return 0; | |
527 | ||
528 | if (!access_ok(VERIFY_WRITE, | |
2bb4629a | 529 | to_user_ptr(args->data_ptr), |
51311d0a CW |
530 | args->size)) |
531 | return -EFAULT; | |
532 | ||
4f27b75d | 533 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 534 | if (ret) |
4f27b75d | 535 | return ret; |
673a394b | 536 | |
05394f39 | 537 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 538 | if (&obj->base == NULL) { |
1d7cfea1 CW |
539 | ret = -ENOENT; |
540 | goto unlock; | |
4f27b75d | 541 | } |
673a394b | 542 | |
7dcd2499 | 543 | /* Bounds check source. */ |
05394f39 CW |
544 | if (args->offset > obj->base.size || |
545 | args->size > obj->base.size - args->offset) { | |
ce9d419d | 546 | ret = -EINVAL; |
35b62a89 | 547 | goto out; |
ce9d419d CW |
548 | } |
549 | ||
1286ff73 DV |
550 | /* prime objects have no backing filp to GEM pread/pwrite |
551 | * pages from. | |
552 | */ | |
553 | if (!obj->base.filp) { | |
554 | ret = -EINVAL; | |
555 | goto out; | |
556 | } | |
557 | ||
db53a302 CW |
558 | trace_i915_gem_object_pread(obj, args->offset, args->size); |
559 | ||
dbf7bff0 | 560 | ret = i915_gem_shmem_pread(dev, obj, args, file); |
673a394b | 561 | |
35b62a89 | 562 | out: |
05394f39 | 563 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 564 | unlock: |
4f27b75d | 565 | mutex_unlock(&dev->struct_mutex); |
eb01459f | 566 | return ret; |
673a394b EA |
567 | } |
568 | ||
0839ccb8 KP |
569 | /* This is the fast write path which cannot handle |
570 | * page faults in the source data | |
9b7530cc | 571 | */ |
0839ccb8 KP |
572 | |
573 | static inline int | |
574 | fast_user_write(struct io_mapping *mapping, | |
575 | loff_t page_base, int page_offset, | |
576 | char __user *user_data, | |
577 | int length) | |
9b7530cc | 578 | { |
4f0c7cfb BW |
579 | void __iomem *vaddr_atomic; |
580 | void *vaddr; | |
0839ccb8 | 581 | unsigned long unwritten; |
9b7530cc | 582 | |
3e4d3af5 | 583 | vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base); |
4f0c7cfb BW |
584 | /* We can use the cpu mem copy function because this is X86. */ |
585 | vaddr = (void __force*)vaddr_atomic + page_offset; | |
586 | unwritten = __copy_from_user_inatomic_nocache(vaddr, | |
0839ccb8 | 587 | user_data, length); |
3e4d3af5 | 588 | io_mapping_unmap_atomic(vaddr_atomic); |
fbd5a26d | 589 | return unwritten; |
0839ccb8 KP |
590 | } |
591 | ||
3de09aa3 EA |
592 | /** |
593 | * This is the fast pwrite path, where we copy the data directly from the | |
594 | * user into the GTT, uncached. | |
595 | */ | |
673a394b | 596 | static int |
05394f39 CW |
597 | i915_gem_gtt_pwrite_fast(struct drm_device *dev, |
598 | struct drm_i915_gem_object *obj, | |
3de09aa3 | 599 | struct drm_i915_gem_pwrite *args, |
05394f39 | 600 | struct drm_file *file) |
673a394b | 601 | { |
0839ccb8 | 602 | drm_i915_private_t *dev_priv = dev->dev_private; |
673a394b | 603 | ssize_t remain; |
0839ccb8 | 604 | loff_t offset, page_base; |
673a394b | 605 | char __user *user_data; |
935aaa69 DV |
606 | int page_offset, page_length, ret; |
607 | ||
c37e2204 | 608 | ret = i915_gem_obj_ggtt_pin(obj, 0, true, true); |
935aaa69 DV |
609 | if (ret) |
610 | goto out; | |
611 | ||
612 | ret = i915_gem_object_set_to_gtt_domain(obj, true); | |
613 | if (ret) | |
614 | goto out_unpin; | |
615 | ||
616 | ret = i915_gem_object_put_fence(obj); | |
617 | if (ret) | |
618 | goto out_unpin; | |
673a394b | 619 | |
2bb4629a | 620 | user_data = to_user_ptr(args->data_ptr); |
673a394b | 621 | remain = args->size; |
673a394b | 622 | |
f343c5f6 | 623 | offset = i915_gem_obj_ggtt_offset(obj) + args->offset; |
673a394b EA |
624 | |
625 | while (remain > 0) { | |
626 | /* Operation in this page | |
627 | * | |
0839ccb8 KP |
628 | * page_base = page offset within aperture |
629 | * page_offset = offset within page | |
630 | * page_length = bytes to copy for this page | |
673a394b | 631 | */ |
c8cbbb8b CW |
632 | page_base = offset & PAGE_MASK; |
633 | page_offset = offset_in_page(offset); | |
0839ccb8 KP |
634 | page_length = remain; |
635 | if ((page_offset + remain) > PAGE_SIZE) | |
636 | page_length = PAGE_SIZE - page_offset; | |
637 | ||
0839ccb8 | 638 | /* If we get a fault while copying data, then (presumably) our |
3de09aa3 EA |
639 | * source page isn't available. Return the error and we'll |
640 | * retry in the slow path. | |
0839ccb8 | 641 | */ |
5d4545ae | 642 | if (fast_user_write(dev_priv->gtt.mappable, page_base, |
935aaa69 DV |
643 | page_offset, user_data, page_length)) { |
644 | ret = -EFAULT; | |
645 | goto out_unpin; | |
646 | } | |
673a394b | 647 | |
0839ccb8 KP |
648 | remain -= page_length; |
649 | user_data += page_length; | |
650 | offset += page_length; | |
673a394b | 651 | } |
673a394b | 652 | |
935aaa69 | 653 | out_unpin: |
d7f46fc4 | 654 | i915_gem_object_ggtt_unpin(obj); |
935aaa69 | 655 | out: |
3de09aa3 | 656 | return ret; |
673a394b EA |
657 | } |
658 | ||
d174bd64 DV |
659 | /* Per-page copy function for the shmem pwrite fastpath. |
660 | * Flushes invalid cachelines before writing to the target if | |
661 | * needs_clflush_before is set and flushes out any written cachelines after | |
662 | * writing if needs_clflush is set. */ | |
3043c60c | 663 | static int |
d174bd64 DV |
664 | shmem_pwrite_fast(struct page *page, int shmem_page_offset, int page_length, |
665 | char __user *user_data, | |
666 | bool page_do_bit17_swizzling, | |
667 | bool needs_clflush_before, | |
668 | bool needs_clflush_after) | |
673a394b | 669 | { |
d174bd64 | 670 | char *vaddr; |
673a394b | 671 | int ret; |
3de09aa3 | 672 | |
e7e58eb5 | 673 | if (unlikely(page_do_bit17_swizzling)) |
d174bd64 | 674 | return -EINVAL; |
3de09aa3 | 675 | |
d174bd64 DV |
676 | vaddr = kmap_atomic(page); |
677 | if (needs_clflush_before) | |
678 | drm_clflush_virt_range(vaddr + shmem_page_offset, | |
679 | page_length); | |
680 | ret = __copy_from_user_inatomic_nocache(vaddr + shmem_page_offset, | |
681 | user_data, | |
682 | page_length); | |
683 | if (needs_clflush_after) | |
684 | drm_clflush_virt_range(vaddr + shmem_page_offset, | |
685 | page_length); | |
686 | kunmap_atomic(vaddr); | |
3de09aa3 | 687 | |
755d2218 | 688 | return ret ? -EFAULT : 0; |
3de09aa3 EA |
689 | } |
690 | ||
d174bd64 DV |
691 | /* Only difference to the fast-path function is that this can handle bit17 |
692 | * and uses non-atomic copy and kmap functions. */ | |
3043c60c | 693 | static int |
d174bd64 DV |
694 | shmem_pwrite_slow(struct page *page, int shmem_page_offset, int page_length, |
695 | char __user *user_data, | |
696 | bool page_do_bit17_swizzling, | |
697 | bool needs_clflush_before, | |
698 | bool needs_clflush_after) | |
673a394b | 699 | { |
d174bd64 DV |
700 | char *vaddr; |
701 | int ret; | |
e5281ccd | 702 | |
d174bd64 | 703 | vaddr = kmap(page); |
e7e58eb5 | 704 | if (unlikely(needs_clflush_before || page_do_bit17_swizzling)) |
23c18c71 DV |
705 | shmem_clflush_swizzled_range(vaddr + shmem_page_offset, |
706 | page_length, | |
707 | page_do_bit17_swizzling); | |
d174bd64 DV |
708 | if (page_do_bit17_swizzling) |
709 | ret = __copy_from_user_swizzled(vaddr, shmem_page_offset, | |
e5281ccd CW |
710 | user_data, |
711 | page_length); | |
d174bd64 DV |
712 | else |
713 | ret = __copy_from_user(vaddr + shmem_page_offset, | |
714 | user_data, | |
715 | page_length); | |
716 | if (needs_clflush_after) | |
23c18c71 DV |
717 | shmem_clflush_swizzled_range(vaddr + shmem_page_offset, |
718 | page_length, | |
719 | page_do_bit17_swizzling); | |
d174bd64 | 720 | kunmap(page); |
40123c1f | 721 | |
755d2218 | 722 | return ret ? -EFAULT : 0; |
40123c1f EA |
723 | } |
724 | ||
40123c1f | 725 | static int |
e244a443 DV |
726 | i915_gem_shmem_pwrite(struct drm_device *dev, |
727 | struct drm_i915_gem_object *obj, | |
728 | struct drm_i915_gem_pwrite *args, | |
729 | struct drm_file *file) | |
40123c1f | 730 | { |
40123c1f | 731 | ssize_t remain; |
8c59967c DV |
732 | loff_t offset; |
733 | char __user *user_data; | |
eb2c0c81 | 734 | int shmem_page_offset, page_length, ret = 0; |
8c59967c | 735 | int obj_do_bit17_swizzling, page_do_bit17_swizzling; |
e244a443 | 736 | int hit_slowpath = 0; |
58642885 DV |
737 | int needs_clflush_after = 0; |
738 | int needs_clflush_before = 0; | |
67d5a50c | 739 | struct sg_page_iter sg_iter; |
40123c1f | 740 | |
2bb4629a | 741 | user_data = to_user_ptr(args->data_ptr); |
40123c1f EA |
742 | remain = args->size; |
743 | ||
8c59967c | 744 | obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj); |
40123c1f | 745 | |
58642885 DV |
746 | if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) { |
747 | /* If we're not in the cpu write domain, set ourself into the gtt | |
748 | * write domain and manually flush cachelines (if required). This | |
749 | * optimizes for the case when the gpu will use the data | |
750 | * right away and we therefore have to clflush anyway. */ | |
2c22569b | 751 | needs_clflush_after = cpu_write_needs_clflush(obj); |
23f54483 BW |
752 | ret = i915_gem_object_wait_rendering(obj, false); |
753 | if (ret) | |
754 | return ret; | |
58642885 | 755 | } |
c76ce038 CW |
756 | /* Same trick applies to invalidate partially written cachelines read |
757 | * before writing. */ | |
758 | if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) | |
759 | needs_clflush_before = | |
760 | !cpu_cache_is_coherent(dev, obj->cache_level); | |
58642885 | 761 | |
755d2218 CW |
762 | ret = i915_gem_object_get_pages(obj); |
763 | if (ret) | |
764 | return ret; | |
765 | ||
766 | i915_gem_object_pin_pages(obj); | |
767 | ||
673a394b | 768 | offset = args->offset; |
05394f39 | 769 | obj->dirty = 1; |
673a394b | 770 | |
67d5a50c ID |
771 | for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, |
772 | offset >> PAGE_SHIFT) { | |
2db76d7c | 773 | struct page *page = sg_page_iter_page(&sg_iter); |
58642885 | 774 | int partial_cacheline_write; |
e5281ccd | 775 | |
9da3da66 CW |
776 | if (remain <= 0) |
777 | break; | |
778 | ||
40123c1f EA |
779 | /* Operation in this page |
780 | * | |
40123c1f | 781 | * shmem_page_offset = offset within page in shmem file |
40123c1f EA |
782 | * page_length = bytes to copy for this page |
783 | */ | |
c8cbbb8b | 784 | shmem_page_offset = offset_in_page(offset); |
40123c1f EA |
785 | |
786 | page_length = remain; | |
787 | if ((shmem_page_offset + page_length) > PAGE_SIZE) | |
788 | page_length = PAGE_SIZE - shmem_page_offset; | |
40123c1f | 789 | |
58642885 DV |
790 | /* If we don't overwrite a cacheline completely we need to be |
791 | * careful to have up-to-date data by first clflushing. Don't | |
792 | * overcomplicate things and flush the entire patch. */ | |
793 | partial_cacheline_write = needs_clflush_before && | |
794 | ((shmem_page_offset | page_length) | |
795 | & (boot_cpu_data.x86_clflush_size - 1)); | |
796 | ||
8c59967c DV |
797 | page_do_bit17_swizzling = obj_do_bit17_swizzling && |
798 | (page_to_phys(page) & (1 << 17)) != 0; | |
799 | ||
d174bd64 DV |
800 | ret = shmem_pwrite_fast(page, shmem_page_offset, page_length, |
801 | user_data, page_do_bit17_swizzling, | |
802 | partial_cacheline_write, | |
803 | needs_clflush_after); | |
804 | if (ret == 0) | |
805 | goto next_page; | |
e244a443 DV |
806 | |
807 | hit_slowpath = 1; | |
e244a443 | 808 | mutex_unlock(&dev->struct_mutex); |
d174bd64 DV |
809 | ret = shmem_pwrite_slow(page, shmem_page_offset, page_length, |
810 | user_data, page_do_bit17_swizzling, | |
811 | partial_cacheline_write, | |
812 | needs_clflush_after); | |
40123c1f | 813 | |
e244a443 | 814 | mutex_lock(&dev->struct_mutex); |
755d2218 | 815 | |
e244a443 | 816 | next_page: |
e5281ccd CW |
817 | set_page_dirty(page); |
818 | mark_page_accessed(page); | |
e5281ccd | 819 | |
755d2218 | 820 | if (ret) |
8c59967c | 821 | goto out; |
8c59967c | 822 | |
40123c1f | 823 | remain -= page_length; |
8c59967c | 824 | user_data += page_length; |
40123c1f | 825 | offset += page_length; |
673a394b EA |
826 | } |
827 | ||
fbd5a26d | 828 | out: |
755d2218 CW |
829 | i915_gem_object_unpin_pages(obj); |
830 | ||
e244a443 | 831 | if (hit_slowpath) { |
8dcf015e DV |
832 | /* |
833 | * Fixup: Flush cpu caches in case we didn't flush the dirty | |
834 | * cachelines in-line while writing and the object moved | |
835 | * out of the cpu write domain while we've dropped the lock. | |
836 | */ | |
837 | if (!needs_clflush_after && | |
838 | obj->base.write_domain != I915_GEM_DOMAIN_CPU) { | |
000433b6 CW |
839 | if (i915_gem_clflush_object(obj, obj->pin_display)) |
840 | i915_gem_chipset_flush(dev); | |
e244a443 | 841 | } |
8c59967c | 842 | } |
673a394b | 843 | |
58642885 | 844 | if (needs_clflush_after) |
e76e9aeb | 845 | i915_gem_chipset_flush(dev); |
58642885 | 846 | |
40123c1f | 847 | return ret; |
673a394b EA |
848 | } |
849 | ||
850 | /** | |
851 | * Writes data to the object referenced by handle. | |
852 | * | |
853 | * On error, the contents of the buffer that were to be modified are undefined. | |
854 | */ | |
855 | int | |
856 | i915_gem_pwrite_ioctl(struct drm_device *dev, void *data, | |
fbd5a26d | 857 | struct drm_file *file) |
673a394b EA |
858 | { |
859 | struct drm_i915_gem_pwrite *args = data; | |
05394f39 | 860 | struct drm_i915_gem_object *obj; |
51311d0a CW |
861 | int ret; |
862 | ||
863 | if (args->size == 0) | |
864 | return 0; | |
865 | ||
866 | if (!access_ok(VERIFY_READ, | |
2bb4629a | 867 | to_user_ptr(args->data_ptr), |
51311d0a CW |
868 | args->size)) |
869 | return -EFAULT; | |
870 | ||
0b74b508 XZ |
871 | if (likely(!i915_prefault_disable)) { |
872 | ret = fault_in_multipages_readable(to_user_ptr(args->data_ptr), | |
873 | args->size); | |
874 | if (ret) | |
875 | return -EFAULT; | |
876 | } | |
673a394b | 877 | |
fbd5a26d | 878 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 879 | if (ret) |
fbd5a26d | 880 | return ret; |
1d7cfea1 | 881 | |
05394f39 | 882 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 883 | if (&obj->base == NULL) { |
1d7cfea1 CW |
884 | ret = -ENOENT; |
885 | goto unlock; | |
fbd5a26d | 886 | } |
673a394b | 887 | |
7dcd2499 | 888 | /* Bounds check destination. */ |
05394f39 CW |
889 | if (args->offset > obj->base.size || |
890 | args->size > obj->base.size - args->offset) { | |
ce9d419d | 891 | ret = -EINVAL; |
35b62a89 | 892 | goto out; |
ce9d419d CW |
893 | } |
894 | ||
1286ff73 DV |
895 | /* prime objects have no backing filp to GEM pread/pwrite |
896 | * pages from. | |
897 | */ | |
898 | if (!obj->base.filp) { | |
899 | ret = -EINVAL; | |
900 | goto out; | |
901 | } | |
902 | ||
db53a302 CW |
903 | trace_i915_gem_object_pwrite(obj, args->offset, args->size); |
904 | ||
935aaa69 | 905 | ret = -EFAULT; |
673a394b EA |
906 | /* We can only do the GTT pwrite on untiled buffers, as otherwise |
907 | * it would end up going through the fenced access, and we'll get | |
908 | * different detiling behavior between reading and writing. | |
909 | * pread/pwrite currently are reading and writing from the CPU | |
910 | * perspective, requiring manual detiling by the client. | |
911 | */ | |
5c0480f2 | 912 | if (obj->phys_obj) { |
fbd5a26d | 913 | ret = i915_gem_phys_pwrite(dev, obj, args, file); |
5c0480f2 DV |
914 | goto out; |
915 | } | |
916 | ||
2c22569b CW |
917 | if (obj->tiling_mode == I915_TILING_NONE && |
918 | obj->base.write_domain != I915_GEM_DOMAIN_CPU && | |
919 | cpu_write_needs_clflush(obj)) { | |
fbd5a26d | 920 | ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file); |
935aaa69 DV |
921 | /* Note that the gtt paths might fail with non-page-backed user |
922 | * pointers (e.g. gtt mappings when moving data between | |
923 | * textures). Fallback to the shmem path in that case. */ | |
fbd5a26d | 924 | } |
673a394b | 925 | |
86a1ee26 | 926 | if (ret == -EFAULT || ret == -ENOSPC) |
935aaa69 | 927 | ret = i915_gem_shmem_pwrite(dev, obj, args, file); |
5c0480f2 | 928 | |
35b62a89 | 929 | out: |
05394f39 | 930 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 931 | unlock: |
fbd5a26d | 932 | mutex_unlock(&dev->struct_mutex); |
673a394b EA |
933 | return ret; |
934 | } | |
935 | ||
b361237b | 936 | int |
33196ded | 937 | i915_gem_check_wedge(struct i915_gpu_error *error, |
b361237b CW |
938 | bool interruptible) |
939 | { | |
1f83fee0 | 940 | if (i915_reset_in_progress(error)) { |
b361237b CW |
941 | /* Non-interruptible callers can't handle -EAGAIN, hence return |
942 | * -EIO unconditionally for these. */ | |
943 | if (!interruptible) | |
944 | return -EIO; | |
945 | ||
1f83fee0 DV |
946 | /* Recovery complete, but the reset failed ... */ |
947 | if (i915_terminally_wedged(error)) | |
b361237b CW |
948 | return -EIO; |
949 | ||
950 | return -EAGAIN; | |
951 | } | |
952 | ||
953 | return 0; | |
954 | } | |
955 | ||
956 | /* | |
957 | * Compare seqno against outstanding lazy request. Emit a request if they are | |
958 | * equal. | |
959 | */ | |
960 | static int | |
961 | i915_gem_check_olr(struct intel_ring_buffer *ring, u32 seqno) | |
962 | { | |
963 | int ret; | |
964 | ||
965 | BUG_ON(!mutex_is_locked(&ring->dev->struct_mutex)); | |
966 | ||
967 | ret = 0; | |
1823521d | 968 | if (seqno == ring->outstanding_lazy_seqno) |
0025c077 | 969 | ret = i915_add_request(ring, NULL); |
b361237b CW |
970 | |
971 | return ret; | |
972 | } | |
973 | ||
094f9a54 CW |
974 | static void fake_irq(unsigned long data) |
975 | { | |
976 | wake_up_process((struct task_struct *)data); | |
977 | } | |
978 | ||
979 | static bool missed_irq(struct drm_i915_private *dev_priv, | |
980 | struct intel_ring_buffer *ring) | |
981 | { | |
982 | return test_bit(ring->id, &dev_priv->gpu_error.missed_irq_rings); | |
983 | } | |
984 | ||
b29c19b6 CW |
985 | static bool can_wait_boost(struct drm_i915_file_private *file_priv) |
986 | { | |
987 | if (file_priv == NULL) | |
988 | return true; | |
989 | ||
990 | return !atomic_xchg(&file_priv->rps_wait_boost, true); | |
991 | } | |
992 | ||
b361237b CW |
993 | /** |
994 | * __wait_seqno - wait until execution of seqno has finished | |
995 | * @ring: the ring expected to report seqno | |
996 | * @seqno: duh! | |
f69061be | 997 | * @reset_counter: reset sequence associated with the given seqno |
b361237b CW |
998 | * @interruptible: do an interruptible wait (normally yes) |
999 | * @timeout: in - how long to wait (NULL forever); out - how much time remaining | |
1000 | * | |
f69061be DV |
1001 | * Note: It is of utmost importance that the passed in seqno and reset_counter |
1002 | * values have been read by the caller in an smp safe manner. Where read-side | |
1003 | * locks are involved, it is sufficient to read the reset_counter before | |
1004 | * unlocking the lock that protects the seqno. For lockless tricks, the | |
1005 | * reset_counter _must_ be read before, and an appropriate smp_rmb must be | |
1006 | * inserted. | |
1007 | * | |
b361237b CW |
1008 | * Returns 0 if the seqno was found within the alloted time. Else returns the |
1009 | * errno with remaining time filled in timeout argument. | |
1010 | */ | |
1011 | static int __wait_seqno(struct intel_ring_buffer *ring, u32 seqno, | |
f69061be | 1012 | unsigned reset_counter, |
b29c19b6 CW |
1013 | bool interruptible, |
1014 | struct timespec *timeout, | |
1015 | struct drm_i915_file_private *file_priv) | |
b361237b CW |
1016 | { |
1017 | drm_i915_private_t *dev_priv = ring->dev->dev_private; | |
094f9a54 CW |
1018 | struct timespec before, now; |
1019 | DEFINE_WAIT(wait); | |
1020 | long timeout_jiffies; | |
b361237b CW |
1021 | int ret; |
1022 | ||
c67a470b PZ |
1023 | WARN(dev_priv->pc8.irqs_disabled, "IRQs disabled\n"); |
1024 | ||
b361237b CW |
1025 | if (i915_seqno_passed(ring->get_seqno(ring, true), seqno)) |
1026 | return 0; | |
1027 | ||
094f9a54 | 1028 | timeout_jiffies = timeout ? timespec_to_jiffies_timeout(timeout) : 1; |
b361237b | 1029 | |
b29c19b6 CW |
1030 | if (dev_priv->info->gen >= 6 && can_wait_boost(file_priv)) { |
1031 | gen6_rps_boost(dev_priv); | |
1032 | if (file_priv) | |
1033 | mod_delayed_work(dev_priv->wq, | |
1034 | &file_priv->mm.idle_work, | |
1035 | msecs_to_jiffies(100)); | |
1036 | } | |
1037 | ||
094f9a54 CW |
1038 | if (!(dev_priv->gpu_error.test_irq_rings & intel_ring_flag(ring)) && |
1039 | WARN_ON(!ring->irq_get(ring))) | |
b361237b CW |
1040 | return -ENODEV; |
1041 | ||
094f9a54 CW |
1042 | /* Record current time in case interrupted by signal, or wedged */ |
1043 | trace_i915_gem_request_wait_begin(ring, seqno); | |
b361237b | 1044 | getrawmonotonic(&before); |
094f9a54 CW |
1045 | for (;;) { |
1046 | struct timer_list timer; | |
1047 | unsigned long expire; | |
b361237b | 1048 | |
094f9a54 CW |
1049 | prepare_to_wait(&ring->irq_queue, &wait, |
1050 | interruptible ? TASK_INTERRUPTIBLE : TASK_UNINTERRUPTIBLE); | |
b361237b | 1051 | |
f69061be DV |
1052 | /* We need to check whether any gpu reset happened in between |
1053 | * the caller grabbing the seqno and now ... */ | |
094f9a54 CW |
1054 | if (reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter)) { |
1055 | /* ... but upgrade the -EAGAIN to an -EIO if the gpu | |
1056 | * is truely gone. */ | |
1057 | ret = i915_gem_check_wedge(&dev_priv->gpu_error, interruptible); | |
1058 | if (ret == 0) | |
1059 | ret = -EAGAIN; | |
1060 | break; | |
1061 | } | |
f69061be | 1062 | |
094f9a54 CW |
1063 | if (i915_seqno_passed(ring->get_seqno(ring, false), seqno)) { |
1064 | ret = 0; | |
1065 | break; | |
1066 | } | |
b361237b | 1067 | |
094f9a54 CW |
1068 | if (interruptible && signal_pending(current)) { |
1069 | ret = -ERESTARTSYS; | |
1070 | break; | |
1071 | } | |
1072 | ||
1073 | if (timeout_jiffies <= 0) { | |
1074 | ret = -ETIME; | |
1075 | break; | |
1076 | } | |
1077 | ||
1078 | timer.function = NULL; | |
1079 | if (timeout || missed_irq(dev_priv, ring)) { | |
1080 | setup_timer_on_stack(&timer, fake_irq, (unsigned long)current); | |
1081 | expire = jiffies + (missed_irq(dev_priv, ring) ? 1: timeout_jiffies); | |
1082 | mod_timer(&timer, expire); | |
1083 | } | |
1084 | ||
5035c275 | 1085 | io_schedule(); |
094f9a54 CW |
1086 | |
1087 | if (timeout) | |
1088 | timeout_jiffies = expire - jiffies; | |
1089 | ||
1090 | if (timer.function) { | |
1091 | del_singleshot_timer_sync(&timer); | |
1092 | destroy_timer_on_stack(&timer); | |
1093 | } | |
1094 | } | |
b361237b | 1095 | getrawmonotonic(&now); |
094f9a54 | 1096 | trace_i915_gem_request_wait_end(ring, seqno); |
b361237b CW |
1097 | |
1098 | ring->irq_put(ring); | |
094f9a54 CW |
1099 | |
1100 | finish_wait(&ring->irq_queue, &wait); | |
b361237b CW |
1101 | |
1102 | if (timeout) { | |
1103 | struct timespec sleep_time = timespec_sub(now, before); | |
1104 | *timeout = timespec_sub(*timeout, sleep_time); | |
4f42f4ef CW |
1105 | if (!timespec_valid(timeout)) /* i.e. negative time remains */ |
1106 | set_normalized_timespec(timeout, 0, 0); | |
b361237b CW |
1107 | } |
1108 | ||
094f9a54 | 1109 | return ret; |
b361237b CW |
1110 | } |
1111 | ||
1112 | /** | |
1113 | * Waits for a sequence number to be signaled, and cleans up the | |
1114 | * request and object lists appropriately for that event. | |
1115 | */ | |
1116 | int | |
1117 | i915_wait_seqno(struct intel_ring_buffer *ring, uint32_t seqno) | |
1118 | { | |
1119 | struct drm_device *dev = ring->dev; | |
1120 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1121 | bool interruptible = dev_priv->mm.interruptible; | |
1122 | int ret; | |
1123 | ||
1124 | BUG_ON(!mutex_is_locked(&dev->struct_mutex)); | |
1125 | BUG_ON(seqno == 0); | |
1126 | ||
33196ded | 1127 | ret = i915_gem_check_wedge(&dev_priv->gpu_error, interruptible); |
b361237b CW |
1128 | if (ret) |
1129 | return ret; | |
1130 | ||
1131 | ret = i915_gem_check_olr(ring, seqno); | |
1132 | if (ret) | |
1133 | return ret; | |
1134 | ||
f69061be DV |
1135 | return __wait_seqno(ring, seqno, |
1136 | atomic_read(&dev_priv->gpu_error.reset_counter), | |
b29c19b6 | 1137 | interruptible, NULL, NULL); |
b361237b CW |
1138 | } |
1139 | ||
d26e3af8 CW |
1140 | static int |
1141 | i915_gem_object_wait_rendering__tail(struct drm_i915_gem_object *obj, | |
1142 | struct intel_ring_buffer *ring) | |
1143 | { | |
1144 | i915_gem_retire_requests_ring(ring); | |
1145 | ||
1146 | /* Manually manage the write flush as we may have not yet | |
1147 | * retired the buffer. | |
1148 | * | |
1149 | * Note that the last_write_seqno is always the earlier of | |
1150 | * the two (read/write) seqno, so if we haved successfully waited, | |
1151 | * we know we have passed the last write. | |
1152 | */ | |
1153 | obj->last_write_seqno = 0; | |
1154 | obj->base.write_domain &= ~I915_GEM_GPU_DOMAINS; | |
1155 | ||
1156 | return 0; | |
1157 | } | |
1158 | ||
b361237b CW |
1159 | /** |
1160 | * Ensures that all rendering to the object has completed and the object is | |
1161 | * safe to unbind from the GTT or access from the CPU. | |
1162 | */ | |
1163 | static __must_check int | |
1164 | i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj, | |
1165 | bool readonly) | |
1166 | { | |
1167 | struct intel_ring_buffer *ring = obj->ring; | |
1168 | u32 seqno; | |
1169 | int ret; | |
1170 | ||
1171 | seqno = readonly ? obj->last_write_seqno : obj->last_read_seqno; | |
1172 | if (seqno == 0) | |
1173 | return 0; | |
1174 | ||
1175 | ret = i915_wait_seqno(ring, seqno); | |
1176 | if (ret) | |
1177 | return ret; | |
1178 | ||
d26e3af8 | 1179 | return i915_gem_object_wait_rendering__tail(obj, ring); |
b361237b CW |
1180 | } |
1181 | ||
3236f57a CW |
1182 | /* A nonblocking variant of the above wait. This is a highly dangerous routine |
1183 | * as the object state may change during this call. | |
1184 | */ | |
1185 | static __must_check int | |
1186 | i915_gem_object_wait_rendering__nonblocking(struct drm_i915_gem_object *obj, | |
b29c19b6 | 1187 | struct drm_file *file, |
3236f57a CW |
1188 | bool readonly) |
1189 | { | |
1190 | struct drm_device *dev = obj->base.dev; | |
1191 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1192 | struct intel_ring_buffer *ring = obj->ring; | |
f69061be | 1193 | unsigned reset_counter; |
3236f57a CW |
1194 | u32 seqno; |
1195 | int ret; | |
1196 | ||
1197 | BUG_ON(!mutex_is_locked(&dev->struct_mutex)); | |
1198 | BUG_ON(!dev_priv->mm.interruptible); | |
1199 | ||
1200 | seqno = readonly ? obj->last_write_seqno : obj->last_read_seqno; | |
1201 | if (seqno == 0) | |
1202 | return 0; | |
1203 | ||
33196ded | 1204 | ret = i915_gem_check_wedge(&dev_priv->gpu_error, true); |
3236f57a CW |
1205 | if (ret) |
1206 | return ret; | |
1207 | ||
1208 | ret = i915_gem_check_olr(ring, seqno); | |
1209 | if (ret) | |
1210 | return ret; | |
1211 | ||
f69061be | 1212 | reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter); |
3236f57a | 1213 | mutex_unlock(&dev->struct_mutex); |
b29c19b6 | 1214 | ret = __wait_seqno(ring, seqno, reset_counter, true, NULL, file->driver_priv); |
3236f57a | 1215 | mutex_lock(&dev->struct_mutex); |
d26e3af8 CW |
1216 | if (ret) |
1217 | return ret; | |
3236f57a | 1218 | |
d26e3af8 | 1219 | return i915_gem_object_wait_rendering__tail(obj, ring); |
3236f57a CW |
1220 | } |
1221 | ||
673a394b | 1222 | /** |
2ef7eeaa EA |
1223 | * Called when user space prepares to use an object with the CPU, either |
1224 | * through the mmap ioctl's mapping or a GTT mapping. | |
673a394b EA |
1225 | */ |
1226 | int | |
1227 | i915_gem_set_domain_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 1228 | struct drm_file *file) |
673a394b EA |
1229 | { |
1230 | struct drm_i915_gem_set_domain *args = data; | |
05394f39 | 1231 | struct drm_i915_gem_object *obj; |
2ef7eeaa EA |
1232 | uint32_t read_domains = args->read_domains; |
1233 | uint32_t write_domain = args->write_domain; | |
673a394b EA |
1234 | int ret; |
1235 | ||
2ef7eeaa | 1236 | /* Only handle setting domains to types used by the CPU. */ |
21d509e3 | 1237 | if (write_domain & I915_GEM_GPU_DOMAINS) |
2ef7eeaa EA |
1238 | return -EINVAL; |
1239 | ||
21d509e3 | 1240 | if (read_domains & I915_GEM_GPU_DOMAINS) |
2ef7eeaa EA |
1241 | return -EINVAL; |
1242 | ||
1243 | /* Having something in the write domain implies it's in the read | |
1244 | * domain, and only that read domain. Enforce that in the request. | |
1245 | */ | |
1246 | if (write_domain != 0 && read_domains != write_domain) | |
1247 | return -EINVAL; | |
1248 | ||
76c1dec1 | 1249 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 1250 | if (ret) |
76c1dec1 | 1251 | return ret; |
1d7cfea1 | 1252 | |
05394f39 | 1253 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 1254 | if (&obj->base == NULL) { |
1d7cfea1 CW |
1255 | ret = -ENOENT; |
1256 | goto unlock; | |
76c1dec1 | 1257 | } |
673a394b | 1258 | |
3236f57a CW |
1259 | /* Try to flush the object off the GPU without holding the lock. |
1260 | * We will repeat the flush holding the lock in the normal manner | |
1261 | * to catch cases where we are gazumped. | |
1262 | */ | |
b29c19b6 | 1263 | ret = i915_gem_object_wait_rendering__nonblocking(obj, file, !write_domain); |
3236f57a CW |
1264 | if (ret) |
1265 | goto unref; | |
1266 | ||
2ef7eeaa EA |
1267 | if (read_domains & I915_GEM_DOMAIN_GTT) { |
1268 | ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0); | |
02354392 EA |
1269 | |
1270 | /* Silently promote "you're not bound, there was nothing to do" | |
1271 | * to success, since the client was just asking us to | |
1272 | * make sure everything was done. | |
1273 | */ | |
1274 | if (ret == -EINVAL) | |
1275 | ret = 0; | |
2ef7eeaa | 1276 | } else { |
e47c68e9 | 1277 | ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0); |
2ef7eeaa EA |
1278 | } |
1279 | ||
3236f57a | 1280 | unref: |
05394f39 | 1281 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 1282 | unlock: |
673a394b EA |
1283 | mutex_unlock(&dev->struct_mutex); |
1284 | return ret; | |
1285 | } | |
1286 | ||
1287 | /** | |
1288 | * Called when user space has done writes to this buffer | |
1289 | */ | |
1290 | int | |
1291 | i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 1292 | struct drm_file *file) |
673a394b EA |
1293 | { |
1294 | struct drm_i915_gem_sw_finish *args = data; | |
05394f39 | 1295 | struct drm_i915_gem_object *obj; |
673a394b EA |
1296 | int ret = 0; |
1297 | ||
76c1dec1 | 1298 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 1299 | if (ret) |
76c1dec1 | 1300 | return ret; |
1d7cfea1 | 1301 | |
05394f39 | 1302 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 1303 | if (&obj->base == NULL) { |
1d7cfea1 CW |
1304 | ret = -ENOENT; |
1305 | goto unlock; | |
673a394b EA |
1306 | } |
1307 | ||
673a394b | 1308 | /* Pinned buffers may be scanout, so flush the cache */ |
2c22569b CW |
1309 | if (obj->pin_display) |
1310 | i915_gem_object_flush_cpu_write_domain(obj, true); | |
e47c68e9 | 1311 | |
05394f39 | 1312 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 1313 | unlock: |
673a394b EA |
1314 | mutex_unlock(&dev->struct_mutex); |
1315 | return ret; | |
1316 | } | |
1317 | ||
1318 | /** | |
1319 | * Maps the contents of an object, returning the address it is mapped | |
1320 | * into. | |
1321 | * | |
1322 | * While the mapping holds a reference on the contents of the object, it doesn't | |
1323 | * imply a ref on the object itself. | |
1324 | */ | |
1325 | int | |
1326 | i915_gem_mmap_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 1327 | struct drm_file *file) |
673a394b EA |
1328 | { |
1329 | struct drm_i915_gem_mmap *args = data; | |
1330 | struct drm_gem_object *obj; | |
673a394b EA |
1331 | unsigned long addr; |
1332 | ||
05394f39 | 1333 | obj = drm_gem_object_lookup(dev, file, args->handle); |
673a394b | 1334 | if (obj == NULL) |
bf79cb91 | 1335 | return -ENOENT; |
673a394b | 1336 | |
1286ff73 DV |
1337 | /* prime objects have no backing filp to GEM mmap |
1338 | * pages from. | |
1339 | */ | |
1340 | if (!obj->filp) { | |
1341 | drm_gem_object_unreference_unlocked(obj); | |
1342 | return -EINVAL; | |
1343 | } | |
1344 | ||
6be5ceb0 | 1345 | addr = vm_mmap(obj->filp, 0, args->size, |
673a394b EA |
1346 | PROT_READ | PROT_WRITE, MAP_SHARED, |
1347 | args->offset); | |
bc9025bd | 1348 | drm_gem_object_unreference_unlocked(obj); |
673a394b EA |
1349 | if (IS_ERR((void *)addr)) |
1350 | return addr; | |
1351 | ||
1352 | args->addr_ptr = (uint64_t) addr; | |
1353 | ||
1354 | return 0; | |
1355 | } | |
1356 | ||
de151cf6 JB |
1357 | /** |
1358 | * i915_gem_fault - fault a page into the GTT | |
1359 | * vma: VMA in question | |
1360 | * vmf: fault info | |
1361 | * | |
1362 | * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped | |
1363 | * from userspace. The fault handler takes care of binding the object to | |
1364 | * the GTT (if needed), allocating and programming a fence register (again, | |
1365 | * only if needed based on whether the old reg is still valid or the object | |
1366 | * is tiled) and inserting a new PTE into the faulting process. | |
1367 | * | |
1368 | * Note that the faulting process may involve evicting existing objects | |
1369 | * from the GTT and/or fence registers to make room. So performance may | |
1370 | * suffer if the GTT working set is large or there are few fence registers | |
1371 | * left. | |
1372 | */ | |
1373 | int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf) | |
1374 | { | |
05394f39 CW |
1375 | struct drm_i915_gem_object *obj = to_intel_bo(vma->vm_private_data); |
1376 | struct drm_device *dev = obj->base.dev; | |
7d1c4804 | 1377 | drm_i915_private_t *dev_priv = dev->dev_private; |
de151cf6 JB |
1378 | pgoff_t page_offset; |
1379 | unsigned long pfn; | |
1380 | int ret = 0; | |
0f973f27 | 1381 | bool write = !!(vmf->flags & FAULT_FLAG_WRITE); |
de151cf6 JB |
1382 | |
1383 | /* We don't use vmf->pgoff since that has the fake offset */ | |
1384 | page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >> | |
1385 | PAGE_SHIFT; | |
1386 | ||
d9bc7e9f CW |
1387 | ret = i915_mutex_lock_interruptible(dev); |
1388 | if (ret) | |
1389 | goto out; | |
a00b10c3 | 1390 | |
db53a302 CW |
1391 | trace_i915_gem_object_fault(obj, page_offset, true, write); |
1392 | ||
eb119bd6 CW |
1393 | /* Access to snoopable pages through the GTT is incoherent. */ |
1394 | if (obj->cache_level != I915_CACHE_NONE && !HAS_LLC(dev)) { | |
1395 | ret = -EINVAL; | |
1396 | goto unlock; | |
1397 | } | |
1398 | ||
d9bc7e9f | 1399 | /* Now bind it into the GTT if needed */ |
c37e2204 | 1400 | ret = i915_gem_obj_ggtt_pin(obj, 0, true, false); |
c9839303 CW |
1401 | if (ret) |
1402 | goto unlock; | |
4a684a41 | 1403 | |
c9839303 CW |
1404 | ret = i915_gem_object_set_to_gtt_domain(obj, write); |
1405 | if (ret) | |
1406 | goto unpin; | |
74898d7e | 1407 | |
06d98131 | 1408 | ret = i915_gem_object_get_fence(obj); |
d9e86c0e | 1409 | if (ret) |
c9839303 | 1410 | goto unpin; |
7d1c4804 | 1411 | |
6299f992 CW |
1412 | obj->fault_mappable = true; |
1413 | ||
f343c5f6 BW |
1414 | pfn = dev_priv->gtt.mappable_base + i915_gem_obj_ggtt_offset(obj); |
1415 | pfn >>= PAGE_SHIFT; | |
1416 | pfn += page_offset; | |
de151cf6 JB |
1417 | |
1418 | /* Finally, remap it using the new GTT offset */ | |
1419 | ret = vm_insert_pfn(vma, (unsigned long)vmf->virtual_address, pfn); | |
c9839303 | 1420 | unpin: |
d7f46fc4 | 1421 | i915_gem_object_ggtt_unpin(obj); |
c715089f | 1422 | unlock: |
de151cf6 | 1423 | mutex_unlock(&dev->struct_mutex); |
d9bc7e9f | 1424 | out: |
de151cf6 | 1425 | switch (ret) { |
d9bc7e9f | 1426 | case -EIO: |
a9340cca DV |
1427 | /* If this -EIO is due to a gpu hang, give the reset code a |
1428 | * chance to clean up the mess. Otherwise return the proper | |
1429 | * SIGBUS. */ | |
1f83fee0 | 1430 | if (i915_terminally_wedged(&dev_priv->gpu_error)) |
a9340cca | 1431 | return VM_FAULT_SIGBUS; |
045e769a | 1432 | case -EAGAIN: |
571c608d DV |
1433 | /* |
1434 | * EAGAIN means the gpu is hung and we'll wait for the error | |
1435 | * handler to reset everything when re-faulting in | |
1436 | * i915_mutex_lock_interruptible. | |
d9bc7e9f | 1437 | */ |
c715089f CW |
1438 | case 0: |
1439 | case -ERESTARTSYS: | |
bed636ab | 1440 | case -EINTR: |
e79e0fe3 DR |
1441 | case -EBUSY: |
1442 | /* | |
1443 | * EBUSY is ok: this just means that another thread | |
1444 | * already did the job. | |
1445 | */ | |
c715089f | 1446 | return VM_FAULT_NOPAGE; |
de151cf6 | 1447 | case -ENOMEM: |
de151cf6 | 1448 | return VM_FAULT_OOM; |
a7c2e1aa DV |
1449 | case -ENOSPC: |
1450 | return VM_FAULT_SIGBUS; | |
de151cf6 | 1451 | default: |
a7c2e1aa | 1452 | WARN_ONCE(ret, "unhandled error in i915_gem_fault: %i\n", ret); |
c715089f | 1453 | return VM_FAULT_SIGBUS; |
de151cf6 JB |
1454 | } |
1455 | } | |
1456 | ||
901782b2 CW |
1457 | /** |
1458 | * i915_gem_release_mmap - remove physical page mappings | |
1459 | * @obj: obj in question | |
1460 | * | |
af901ca1 | 1461 | * Preserve the reservation of the mmapping with the DRM core code, but |
901782b2 CW |
1462 | * relinquish ownership of the pages back to the system. |
1463 | * | |
1464 | * It is vital that we remove the page mapping if we have mapped a tiled | |
1465 | * object through the GTT and then lose the fence register due to | |
1466 | * resource pressure. Similarly if the object has been moved out of the | |
1467 | * aperture, than pages mapped into userspace must be revoked. Removing the | |
1468 | * mapping will then trigger a page fault on the next user access, allowing | |
1469 | * fixup by i915_gem_fault(). | |
1470 | */ | |
d05ca301 | 1471 | void |
05394f39 | 1472 | i915_gem_release_mmap(struct drm_i915_gem_object *obj) |
901782b2 | 1473 | { |
6299f992 CW |
1474 | if (!obj->fault_mappable) |
1475 | return; | |
901782b2 | 1476 | |
51335df9 | 1477 | drm_vma_node_unmap(&obj->base.vma_node, obj->base.dev->dev_mapping); |
6299f992 | 1478 | obj->fault_mappable = false; |
901782b2 CW |
1479 | } |
1480 | ||
0fa87796 | 1481 | uint32_t |
e28f8711 | 1482 | i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode) |
92b88aeb | 1483 | { |
e28f8711 | 1484 | uint32_t gtt_size; |
92b88aeb CW |
1485 | |
1486 | if (INTEL_INFO(dev)->gen >= 4 || | |
e28f8711 CW |
1487 | tiling_mode == I915_TILING_NONE) |
1488 | return size; | |
92b88aeb CW |
1489 | |
1490 | /* Previous chips need a power-of-two fence region when tiling */ | |
1491 | if (INTEL_INFO(dev)->gen == 3) | |
e28f8711 | 1492 | gtt_size = 1024*1024; |
92b88aeb | 1493 | else |
e28f8711 | 1494 | gtt_size = 512*1024; |
92b88aeb | 1495 | |
e28f8711 CW |
1496 | while (gtt_size < size) |
1497 | gtt_size <<= 1; | |
92b88aeb | 1498 | |
e28f8711 | 1499 | return gtt_size; |
92b88aeb CW |
1500 | } |
1501 | ||
de151cf6 JB |
1502 | /** |
1503 | * i915_gem_get_gtt_alignment - return required GTT alignment for an object | |
1504 | * @obj: object to check | |
1505 | * | |
1506 | * Return the required GTT alignment for an object, taking into account | |
5e783301 | 1507 | * potential fence register mapping. |
de151cf6 | 1508 | */ |
d865110c ID |
1509 | uint32_t |
1510 | i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size, | |
1511 | int tiling_mode, bool fenced) | |
de151cf6 | 1512 | { |
de151cf6 JB |
1513 | /* |
1514 | * Minimum alignment is 4k (GTT page size), but might be greater | |
1515 | * if a fence register is needed for the object. | |
1516 | */ | |
d865110c | 1517 | if (INTEL_INFO(dev)->gen >= 4 || (!fenced && IS_G33(dev)) || |
e28f8711 | 1518 | tiling_mode == I915_TILING_NONE) |
de151cf6 JB |
1519 | return 4096; |
1520 | ||
a00b10c3 CW |
1521 | /* |
1522 | * Previous chips need to be aligned to the size of the smallest | |
1523 | * fence register that can contain the object. | |
1524 | */ | |
e28f8711 | 1525 | return i915_gem_get_gtt_size(dev, size, tiling_mode); |
a00b10c3 CW |
1526 | } |
1527 | ||
d8cb5086 CW |
1528 | static int i915_gem_object_create_mmap_offset(struct drm_i915_gem_object *obj) |
1529 | { | |
1530 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; | |
1531 | int ret; | |
1532 | ||
0de23977 | 1533 | if (drm_vma_node_has_offset(&obj->base.vma_node)) |
d8cb5086 CW |
1534 | return 0; |
1535 | ||
da494d7c DV |
1536 | dev_priv->mm.shrinker_no_lock_stealing = true; |
1537 | ||
d8cb5086 CW |
1538 | ret = drm_gem_create_mmap_offset(&obj->base); |
1539 | if (ret != -ENOSPC) | |
da494d7c | 1540 | goto out; |
d8cb5086 CW |
1541 | |
1542 | /* Badly fragmented mmap space? The only way we can recover | |
1543 | * space is by destroying unwanted objects. We can't randomly release | |
1544 | * mmap_offsets as userspace expects them to be persistent for the | |
1545 | * lifetime of the objects. The closest we can is to release the | |
1546 | * offsets on purgeable objects by truncating it and marking it purged, | |
1547 | * which prevents userspace from ever using that object again. | |
1548 | */ | |
1549 | i915_gem_purge(dev_priv, obj->base.size >> PAGE_SHIFT); | |
1550 | ret = drm_gem_create_mmap_offset(&obj->base); | |
1551 | if (ret != -ENOSPC) | |
da494d7c | 1552 | goto out; |
d8cb5086 CW |
1553 | |
1554 | i915_gem_shrink_all(dev_priv); | |
da494d7c DV |
1555 | ret = drm_gem_create_mmap_offset(&obj->base); |
1556 | out: | |
1557 | dev_priv->mm.shrinker_no_lock_stealing = false; | |
1558 | ||
1559 | return ret; | |
d8cb5086 CW |
1560 | } |
1561 | ||
1562 | static void i915_gem_object_free_mmap_offset(struct drm_i915_gem_object *obj) | |
1563 | { | |
d8cb5086 CW |
1564 | drm_gem_free_mmap_offset(&obj->base); |
1565 | } | |
1566 | ||
de151cf6 | 1567 | int |
ff72145b DA |
1568 | i915_gem_mmap_gtt(struct drm_file *file, |
1569 | struct drm_device *dev, | |
1570 | uint32_t handle, | |
1571 | uint64_t *offset) | |
de151cf6 | 1572 | { |
da761a6e | 1573 | struct drm_i915_private *dev_priv = dev->dev_private; |
05394f39 | 1574 | struct drm_i915_gem_object *obj; |
de151cf6 JB |
1575 | int ret; |
1576 | ||
76c1dec1 | 1577 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 1578 | if (ret) |
76c1dec1 | 1579 | return ret; |
de151cf6 | 1580 | |
ff72145b | 1581 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle)); |
c8725226 | 1582 | if (&obj->base == NULL) { |
1d7cfea1 CW |
1583 | ret = -ENOENT; |
1584 | goto unlock; | |
1585 | } | |
de151cf6 | 1586 | |
5d4545ae | 1587 | if (obj->base.size > dev_priv->gtt.mappable_end) { |
da761a6e | 1588 | ret = -E2BIG; |
ff56b0bc | 1589 | goto out; |
da761a6e CW |
1590 | } |
1591 | ||
05394f39 | 1592 | if (obj->madv != I915_MADV_WILLNEED) { |
ab18282d | 1593 | DRM_ERROR("Attempting to mmap a purgeable buffer\n"); |
1d7cfea1 CW |
1594 | ret = -EINVAL; |
1595 | goto out; | |
ab18282d CW |
1596 | } |
1597 | ||
d8cb5086 CW |
1598 | ret = i915_gem_object_create_mmap_offset(obj); |
1599 | if (ret) | |
1600 | goto out; | |
de151cf6 | 1601 | |
0de23977 | 1602 | *offset = drm_vma_node_offset_addr(&obj->base.vma_node); |
de151cf6 | 1603 | |
1d7cfea1 | 1604 | out: |
05394f39 | 1605 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 1606 | unlock: |
de151cf6 | 1607 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 1608 | return ret; |
de151cf6 JB |
1609 | } |
1610 | ||
ff72145b DA |
1611 | /** |
1612 | * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing | |
1613 | * @dev: DRM device | |
1614 | * @data: GTT mapping ioctl data | |
1615 | * @file: GEM object info | |
1616 | * | |
1617 | * Simply returns the fake offset to userspace so it can mmap it. | |
1618 | * The mmap call will end up in drm_gem_mmap(), which will set things | |
1619 | * up so we can get faults in the handler above. | |
1620 | * | |
1621 | * The fault handler will take care of binding the object into the GTT | |
1622 | * (since it may have been evicted to make room for something), allocating | |
1623 | * a fence register, and mapping the appropriate aperture address into | |
1624 | * userspace. | |
1625 | */ | |
1626 | int | |
1627 | i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data, | |
1628 | struct drm_file *file) | |
1629 | { | |
1630 | struct drm_i915_gem_mmap_gtt *args = data; | |
1631 | ||
ff72145b DA |
1632 | return i915_gem_mmap_gtt(file, dev, args->handle, &args->offset); |
1633 | } | |
1634 | ||
225067ee DV |
1635 | /* Immediately discard the backing storage */ |
1636 | static void | |
1637 | i915_gem_object_truncate(struct drm_i915_gem_object *obj) | |
e5281ccd | 1638 | { |
e5281ccd | 1639 | struct inode *inode; |
e5281ccd | 1640 | |
4d6294bf | 1641 | i915_gem_object_free_mmap_offset(obj); |
1286ff73 | 1642 | |
4d6294bf CW |
1643 | if (obj->base.filp == NULL) |
1644 | return; | |
e5281ccd | 1645 | |
225067ee DV |
1646 | /* Our goal here is to return as much of the memory as |
1647 | * is possible back to the system as we are called from OOM. | |
1648 | * To do this we must instruct the shmfs to drop all of its | |
1649 | * backing pages, *now*. | |
1650 | */ | |
496ad9aa | 1651 | inode = file_inode(obj->base.filp); |
225067ee | 1652 | shmem_truncate_range(inode, 0, (loff_t)-1); |
e5281ccd | 1653 | |
225067ee DV |
1654 | obj->madv = __I915_MADV_PURGED; |
1655 | } | |
e5281ccd | 1656 | |
225067ee DV |
1657 | static inline int |
1658 | i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj) | |
1659 | { | |
1660 | return obj->madv == I915_MADV_DONTNEED; | |
e5281ccd CW |
1661 | } |
1662 | ||
5cdf5881 | 1663 | static void |
05394f39 | 1664 | i915_gem_object_put_pages_gtt(struct drm_i915_gem_object *obj) |
673a394b | 1665 | { |
90797e6d ID |
1666 | struct sg_page_iter sg_iter; |
1667 | int ret; | |
1286ff73 | 1668 | |
05394f39 | 1669 | BUG_ON(obj->madv == __I915_MADV_PURGED); |
673a394b | 1670 | |
6c085a72 CW |
1671 | ret = i915_gem_object_set_to_cpu_domain(obj, true); |
1672 | if (ret) { | |
1673 | /* In the event of a disaster, abandon all caches and | |
1674 | * hope for the best. | |
1675 | */ | |
1676 | WARN_ON(ret != -EIO); | |
2c22569b | 1677 | i915_gem_clflush_object(obj, true); |
6c085a72 CW |
1678 | obj->base.read_domains = obj->base.write_domain = I915_GEM_DOMAIN_CPU; |
1679 | } | |
1680 | ||
6dacfd2f | 1681 | if (i915_gem_object_needs_bit17_swizzle(obj)) |
280b713b EA |
1682 | i915_gem_object_save_bit_17_swizzle(obj); |
1683 | ||
05394f39 CW |
1684 | if (obj->madv == I915_MADV_DONTNEED) |
1685 | obj->dirty = 0; | |
3ef94daa | 1686 | |
90797e6d | 1687 | for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, 0) { |
2db76d7c | 1688 | struct page *page = sg_page_iter_page(&sg_iter); |
9da3da66 | 1689 | |
05394f39 | 1690 | if (obj->dirty) |
9da3da66 | 1691 | set_page_dirty(page); |
3ef94daa | 1692 | |
05394f39 | 1693 | if (obj->madv == I915_MADV_WILLNEED) |
9da3da66 | 1694 | mark_page_accessed(page); |
3ef94daa | 1695 | |
9da3da66 | 1696 | page_cache_release(page); |
3ef94daa | 1697 | } |
05394f39 | 1698 | obj->dirty = 0; |
673a394b | 1699 | |
9da3da66 CW |
1700 | sg_free_table(obj->pages); |
1701 | kfree(obj->pages); | |
37e680a1 | 1702 | } |
6c085a72 | 1703 | |
dd624afd | 1704 | int |
37e680a1 CW |
1705 | i915_gem_object_put_pages(struct drm_i915_gem_object *obj) |
1706 | { | |
1707 | const struct drm_i915_gem_object_ops *ops = obj->ops; | |
1708 | ||
2f745ad3 | 1709 | if (obj->pages == NULL) |
37e680a1 CW |
1710 | return 0; |
1711 | ||
a5570178 CW |
1712 | if (obj->pages_pin_count) |
1713 | return -EBUSY; | |
1714 | ||
9843877d | 1715 | BUG_ON(i915_gem_obj_bound_any(obj)); |
3e123027 | 1716 | |
a2165e31 CW |
1717 | /* ->put_pages might need to allocate memory for the bit17 swizzle |
1718 | * array, hence protect them from being reaped by removing them from gtt | |
1719 | * lists early. */ | |
35c20a60 | 1720 | list_del(&obj->global_list); |
a2165e31 | 1721 | |
37e680a1 | 1722 | ops->put_pages(obj); |
05394f39 | 1723 | obj->pages = NULL; |
37e680a1 | 1724 | |
6c085a72 CW |
1725 | if (i915_gem_object_is_purgeable(obj)) |
1726 | i915_gem_object_truncate(obj); | |
1727 | ||
1728 | return 0; | |
1729 | } | |
1730 | ||
d9973b43 | 1731 | static unsigned long |
93927ca5 DV |
1732 | __i915_gem_shrink(struct drm_i915_private *dev_priv, long target, |
1733 | bool purgeable_only) | |
6c085a72 | 1734 | { |
57094f82 | 1735 | struct list_head still_bound_list; |
6c085a72 | 1736 | struct drm_i915_gem_object *obj, *next; |
d9973b43 | 1737 | unsigned long count = 0; |
6c085a72 CW |
1738 | |
1739 | list_for_each_entry_safe(obj, next, | |
1740 | &dev_priv->mm.unbound_list, | |
35c20a60 | 1741 | global_list) { |
93927ca5 | 1742 | if ((i915_gem_object_is_purgeable(obj) || !purgeable_only) && |
37e680a1 | 1743 | i915_gem_object_put_pages(obj) == 0) { |
6c085a72 CW |
1744 | count += obj->base.size >> PAGE_SHIFT; |
1745 | if (count >= target) | |
1746 | return count; | |
1747 | } | |
1748 | } | |
1749 | ||
57094f82 CW |
1750 | /* |
1751 | * As we may completely rewrite the bound list whilst unbinding | |
1752 | * (due to retiring requests) we have to strictly process only | |
1753 | * one element of the list at the time, and recheck the list | |
1754 | * on every iteration. | |
1755 | */ | |
1756 | INIT_LIST_HEAD(&still_bound_list); | |
1757 | while (count < target && !list_empty(&dev_priv->mm.bound_list)) { | |
07fe0b12 | 1758 | struct i915_vma *vma, *v; |
80dcfdbd | 1759 | |
57094f82 CW |
1760 | obj = list_first_entry(&dev_priv->mm.bound_list, |
1761 | typeof(*obj), global_list); | |
1762 | list_move_tail(&obj->global_list, &still_bound_list); | |
1763 | ||
80dcfdbd BW |
1764 | if (!i915_gem_object_is_purgeable(obj) && purgeable_only) |
1765 | continue; | |
1766 | ||
57094f82 CW |
1767 | /* |
1768 | * Hold a reference whilst we unbind this object, as we may | |
1769 | * end up waiting for and retiring requests. This might | |
1770 | * release the final reference (held by the active list) | |
1771 | * and result in the object being freed from under us. | |
1772 | * in this object being freed. | |
1773 | * | |
1774 | * Note 1: Shrinking the bound list is special since only active | |
1775 | * (and hence bound objects) can contain such limbo objects, so | |
1776 | * we don't need special tricks for shrinking the unbound list. | |
1777 | * The only other place where we have to be careful with active | |
1778 | * objects suddenly disappearing due to retiring requests is the | |
1779 | * eviction code. | |
1780 | * | |
1781 | * Note 2: Even though the bound list doesn't hold a reference | |
1782 | * to the object we can safely grab one here: The final object | |
1783 | * unreferencing and the bound_list are both protected by the | |
1784 | * dev->struct_mutex and so we won't ever be able to observe an | |
1785 | * object on the bound_list with a reference count equals 0. | |
1786 | */ | |
1787 | drm_gem_object_reference(&obj->base); | |
1788 | ||
07fe0b12 BW |
1789 | list_for_each_entry_safe(vma, v, &obj->vma_list, vma_link) |
1790 | if (i915_vma_unbind(vma)) | |
1791 | break; | |
80dcfdbd | 1792 | |
57094f82 | 1793 | if (i915_gem_object_put_pages(obj) == 0) |
6c085a72 | 1794 | count += obj->base.size >> PAGE_SHIFT; |
57094f82 CW |
1795 | |
1796 | drm_gem_object_unreference(&obj->base); | |
6c085a72 | 1797 | } |
57094f82 | 1798 | list_splice(&still_bound_list, &dev_priv->mm.bound_list); |
6c085a72 CW |
1799 | |
1800 | return count; | |
1801 | } | |
1802 | ||
d9973b43 | 1803 | static unsigned long |
93927ca5 DV |
1804 | i915_gem_purge(struct drm_i915_private *dev_priv, long target) |
1805 | { | |
1806 | return __i915_gem_shrink(dev_priv, target, true); | |
1807 | } | |
1808 | ||
d9973b43 | 1809 | static unsigned long |
6c085a72 CW |
1810 | i915_gem_shrink_all(struct drm_i915_private *dev_priv) |
1811 | { | |
1812 | struct drm_i915_gem_object *obj, *next; | |
7dc19d5a | 1813 | long freed = 0; |
6c085a72 CW |
1814 | |
1815 | i915_gem_evict_everything(dev_priv->dev); | |
1816 | ||
35c20a60 | 1817 | list_for_each_entry_safe(obj, next, &dev_priv->mm.unbound_list, |
7dc19d5a | 1818 | global_list) { |
d9973b43 | 1819 | if (i915_gem_object_put_pages(obj) == 0) |
7dc19d5a | 1820 | freed += obj->base.size >> PAGE_SHIFT; |
7dc19d5a DC |
1821 | } |
1822 | return freed; | |
225067ee DV |
1823 | } |
1824 | ||
37e680a1 | 1825 | static int |
6c085a72 | 1826 | i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj) |
e5281ccd | 1827 | { |
6c085a72 | 1828 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
e5281ccd CW |
1829 | int page_count, i; |
1830 | struct address_space *mapping; | |
9da3da66 CW |
1831 | struct sg_table *st; |
1832 | struct scatterlist *sg; | |
90797e6d | 1833 | struct sg_page_iter sg_iter; |
e5281ccd | 1834 | struct page *page; |
90797e6d | 1835 | unsigned long last_pfn = 0; /* suppress gcc warning */ |
6c085a72 | 1836 | gfp_t gfp; |
e5281ccd | 1837 | |
6c085a72 CW |
1838 | /* Assert that the object is not currently in any GPU domain. As it |
1839 | * wasn't in the GTT, there shouldn't be any way it could have been in | |
1840 | * a GPU cache | |
1841 | */ | |
1842 | BUG_ON(obj->base.read_domains & I915_GEM_GPU_DOMAINS); | |
1843 | BUG_ON(obj->base.write_domain & I915_GEM_GPU_DOMAINS); | |
1844 | ||
9da3da66 CW |
1845 | st = kmalloc(sizeof(*st), GFP_KERNEL); |
1846 | if (st == NULL) | |
1847 | return -ENOMEM; | |
1848 | ||
05394f39 | 1849 | page_count = obj->base.size / PAGE_SIZE; |
9da3da66 | 1850 | if (sg_alloc_table(st, page_count, GFP_KERNEL)) { |
9da3da66 | 1851 | kfree(st); |
e5281ccd | 1852 | return -ENOMEM; |
9da3da66 | 1853 | } |
e5281ccd | 1854 | |
9da3da66 CW |
1855 | /* Get the list of pages out of our struct file. They'll be pinned |
1856 | * at this point until we release them. | |
1857 | * | |
1858 | * Fail silently without starting the shrinker | |
1859 | */ | |
496ad9aa | 1860 | mapping = file_inode(obj->base.filp)->i_mapping; |
6c085a72 | 1861 | gfp = mapping_gfp_mask(mapping); |
caf49191 | 1862 | gfp |= __GFP_NORETRY | __GFP_NOWARN | __GFP_NO_KSWAPD; |
6c085a72 | 1863 | gfp &= ~(__GFP_IO | __GFP_WAIT); |
90797e6d ID |
1864 | sg = st->sgl; |
1865 | st->nents = 0; | |
1866 | for (i = 0; i < page_count; i++) { | |
6c085a72 CW |
1867 | page = shmem_read_mapping_page_gfp(mapping, i, gfp); |
1868 | if (IS_ERR(page)) { | |
1869 | i915_gem_purge(dev_priv, page_count); | |
1870 | page = shmem_read_mapping_page_gfp(mapping, i, gfp); | |
1871 | } | |
1872 | if (IS_ERR(page)) { | |
1873 | /* We've tried hard to allocate the memory by reaping | |
1874 | * our own buffer, now let the real VM do its job and | |
1875 | * go down in flames if truly OOM. | |
1876 | */ | |
caf49191 | 1877 | gfp &= ~(__GFP_NORETRY | __GFP_NOWARN | __GFP_NO_KSWAPD); |
6c085a72 CW |
1878 | gfp |= __GFP_IO | __GFP_WAIT; |
1879 | ||
1880 | i915_gem_shrink_all(dev_priv); | |
1881 | page = shmem_read_mapping_page_gfp(mapping, i, gfp); | |
1882 | if (IS_ERR(page)) | |
1883 | goto err_pages; | |
1884 | ||
caf49191 | 1885 | gfp |= __GFP_NORETRY | __GFP_NOWARN | __GFP_NO_KSWAPD; |
6c085a72 CW |
1886 | gfp &= ~(__GFP_IO | __GFP_WAIT); |
1887 | } | |
426729dc KRW |
1888 | #ifdef CONFIG_SWIOTLB |
1889 | if (swiotlb_nr_tbl()) { | |
1890 | st->nents++; | |
1891 | sg_set_page(sg, page, PAGE_SIZE, 0); | |
1892 | sg = sg_next(sg); | |
1893 | continue; | |
1894 | } | |
1895 | #endif | |
90797e6d ID |
1896 | if (!i || page_to_pfn(page) != last_pfn + 1) { |
1897 | if (i) | |
1898 | sg = sg_next(sg); | |
1899 | st->nents++; | |
1900 | sg_set_page(sg, page, PAGE_SIZE, 0); | |
1901 | } else { | |
1902 | sg->length += PAGE_SIZE; | |
1903 | } | |
1904 | last_pfn = page_to_pfn(page); | |
3bbbe706 DV |
1905 | |
1906 | /* Check that the i965g/gm workaround works. */ | |
1907 | WARN_ON((gfp & __GFP_DMA32) && (last_pfn >= 0x00100000UL)); | |
e5281ccd | 1908 | } |
426729dc KRW |
1909 | #ifdef CONFIG_SWIOTLB |
1910 | if (!swiotlb_nr_tbl()) | |
1911 | #endif | |
1912 | sg_mark_end(sg); | |
74ce6b6c CW |
1913 | obj->pages = st; |
1914 | ||
6dacfd2f | 1915 | if (i915_gem_object_needs_bit17_swizzle(obj)) |
e5281ccd CW |
1916 | i915_gem_object_do_bit_17_swizzle(obj); |
1917 | ||
1918 | return 0; | |
1919 | ||
1920 | err_pages: | |
90797e6d ID |
1921 | sg_mark_end(sg); |
1922 | for_each_sg_page(st->sgl, &sg_iter, st->nents, 0) | |
2db76d7c | 1923 | page_cache_release(sg_page_iter_page(&sg_iter)); |
9da3da66 CW |
1924 | sg_free_table(st); |
1925 | kfree(st); | |
e5281ccd | 1926 | return PTR_ERR(page); |
673a394b EA |
1927 | } |
1928 | ||
37e680a1 CW |
1929 | /* Ensure that the associated pages are gathered from the backing storage |
1930 | * and pinned into our object. i915_gem_object_get_pages() may be called | |
1931 | * multiple times before they are released by a single call to | |
1932 | * i915_gem_object_put_pages() - once the pages are no longer referenced | |
1933 | * either as a result of memory pressure (reaping pages under the shrinker) | |
1934 | * or as the object is itself released. | |
1935 | */ | |
1936 | int | |
1937 | i915_gem_object_get_pages(struct drm_i915_gem_object *obj) | |
1938 | { | |
1939 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; | |
1940 | const struct drm_i915_gem_object_ops *ops = obj->ops; | |
1941 | int ret; | |
1942 | ||
2f745ad3 | 1943 | if (obj->pages) |
37e680a1 CW |
1944 | return 0; |
1945 | ||
43e28f09 CW |
1946 | if (obj->madv != I915_MADV_WILLNEED) { |
1947 | DRM_ERROR("Attempting to obtain a purgeable object\n"); | |
1948 | return -EINVAL; | |
1949 | } | |
1950 | ||
a5570178 CW |
1951 | BUG_ON(obj->pages_pin_count); |
1952 | ||
37e680a1 CW |
1953 | ret = ops->get_pages(obj); |
1954 | if (ret) | |
1955 | return ret; | |
1956 | ||
35c20a60 | 1957 | list_add_tail(&obj->global_list, &dev_priv->mm.unbound_list); |
37e680a1 | 1958 | return 0; |
673a394b EA |
1959 | } |
1960 | ||
e2d05a8b | 1961 | static void |
05394f39 | 1962 | i915_gem_object_move_to_active(struct drm_i915_gem_object *obj, |
9d773091 | 1963 | struct intel_ring_buffer *ring) |
673a394b | 1964 | { |
05394f39 | 1965 | struct drm_device *dev = obj->base.dev; |
69dc4987 | 1966 | struct drm_i915_private *dev_priv = dev->dev_private; |
9d773091 | 1967 | u32 seqno = intel_ring_get_seqno(ring); |
617dbe27 | 1968 | |
852835f3 | 1969 | BUG_ON(ring == NULL); |
02978ff5 CW |
1970 | if (obj->ring != ring && obj->last_write_seqno) { |
1971 | /* Keep the seqno relative to the current ring */ | |
1972 | obj->last_write_seqno = seqno; | |
1973 | } | |
05394f39 | 1974 | obj->ring = ring; |
673a394b EA |
1975 | |
1976 | /* Add a reference if we're newly entering the active list. */ | |
05394f39 CW |
1977 | if (!obj->active) { |
1978 | drm_gem_object_reference(&obj->base); | |
1979 | obj->active = 1; | |
673a394b | 1980 | } |
e35a41de | 1981 | |
05394f39 | 1982 | list_move_tail(&obj->ring_list, &ring->active_list); |
caea7476 | 1983 | |
0201f1ec | 1984 | obj->last_read_seqno = seqno; |
caea7476 | 1985 | |
7dd49065 | 1986 | if (obj->fenced_gpu_access) { |
caea7476 | 1987 | obj->last_fenced_seqno = seqno; |
caea7476 | 1988 | |
7dd49065 CW |
1989 | /* Bump MRU to take account of the delayed flush */ |
1990 | if (obj->fence_reg != I915_FENCE_REG_NONE) { | |
1991 | struct drm_i915_fence_reg *reg; | |
1992 | ||
1993 | reg = &dev_priv->fence_regs[obj->fence_reg]; | |
1994 | list_move_tail(®->lru_list, | |
1995 | &dev_priv->mm.fence_list); | |
1996 | } | |
caea7476 CW |
1997 | } |
1998 | } | |
1999 | ||
e2d05a8b BW |
2000 | void i915_vma_move_to_active(struct i915_vma *vma, |
2001 | struct intel_ring_buffer *ring) | |
2002 | { | |
2003 | list_move_tail(&vma->mm_list, &vma->vm->active_list); | |
2004 | return i915_gem_object_move_to_active(vma->obj, ring); | |
2005 | } | |
2006 | ||
caea7476 | 2007 | static void |
caea7476 | 2008 | i915_gem_object_move_to_inactive(struct drm_i915_gem_object *obj) |
ce44b0ea | 2009 | { |
ca191b13 | 2010 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
feb822cf BW |
2011 | struct i915_address_space *vm; |
2012 | struct i915_vma *vma; | |
ce44b0ea | 2013 | |
65ce3027 | 2014 | BUG_ON(obj->base.write_domain & ~I915_GEM_GPU_DOMAINS); |
05394f39 | 2015 | BUG_ON(!obj->active); |
caea7476 | 2016 | |
feb822cf BW |
2017 | list_for_each_entry(vm, &dev_priv->vm_list, global_link) { |
2018 | vma = i915_gem_obj_to_vma(obj, vm); | |
2019 | if (vma && !list_empty(&vma->mm_list)) | |
2020 | list_move_tail(&vma->mm_list, &vm->inactive_list); | |
2021 | } | |
caea7476 | 2022 | |
65ce3027 | 2023 | list_del_init(&obj->ring_list); |
caea7476 CW |
2024 | obj->ring = NULL; |
2025 | ||
65ce3027 CW |
2026 | obj->last_read_seqno = 0; |
2027 | obj->last_write_seqno = 0; | |
2028 | obj->base.write_domain = 0; | |
2029 | ||
2030 | obj->last_fenced_seqno = 0; | |
caea7476 | 2031 | obj->fenced_gpu_access = false; |
caea7476 CW |
2032 | |
2033 | obj->active = 0; | |
2034 | drm_gem_object_unreference(&obj->base); | |
2035 | ||
2036 | WARN_ON(i915_verify_lists(dev)); | |
ce44b0ea | 2037 | } |
673a394b | 2038 | |
9d773091 | 2039 | static int |
fca26bb4 | 2040 | i915_gem_init_seqno(struct drm_device *dev, u32 seqno) |
53d227f2 | 2041 | { |
9d773091 CW |
2042 | struct drm_i915_private *dev_priv = dev->dev_private; |
2043 | struct intel_ring_buffer *ring; | |
2044 | int ret, i, j; | |
53d227f2 | 2045 | |
107f27a5 | 2046 | /* Carefully retire all requests without writing to the rings */ |
9d773091 | 2047 | for_each_ring(ring, dev_priv, i) { |
107f27a5 CW |
2048 | ret = intel_ring_idle(ring); |
2049 | if (ret) | |
2050 | return ret; | |
9d773091 | 2051 | } |
9d773091 | 2052 | i915_gem_retire_requests(dev); |
107f27a5 CW |
2053 | |
2054 | /* Finally reset hw state */ | |
9d773091 | 2055 | for_each_ring(ring, dev_priv, i) { |
fca26bb4 | 2056 | intel_ring_init_seqno(ring, seqno); |
498d2ac1 | 2057 | |
9d773091 CW |
2058 | for (j = 0; j < ARRAY_SIZE(ring->sync_seqno); j++) |
2059 | ring->sync_seqno[j] = 0; | |
2060 | } | |
53d227f2 | 2061 | |
9d773091 | 2062 | return 0; |
53d227f2 DV |
2063 | } |
2064 | ||
fca26bb4 MK |
2065 | int i915_gem_set_seqno(struct drm_device *dev, u32 seqno) |
2066 | { | |
2067 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2068 | int ret; | |
2069 | ||
2070 | if (seqno == 0) | |
2071 | return -EINVAL; | |
2072 | ||
2073 | /* HWS page needs to be set less than what we | |
2074 | * will inject to ring | |
2075 | */ | |
2076 | ret = i915_gem_init_seqno(dev, seqno - 1); | |
2077 | if (ret) | |
2078 | return ret; | |
2079 | ||
2080 | /* Carefully set the last_seqno value so that wrap | |
2081 | * detection still works | |
2082 | */ | |
2083 | dev_priv->next_seqno = seqno; | |
2084 | dev_priv->last_seqno = seqno - 1; | |
2085 | if (dev_priv->last_seqno == 0) | |
2086 | dev_priv->last_seqno--; | |
2087 | ||
2088 | return 0; | |
2089 | } | |
2090 | ||
9d773091 CW |
2091 | int |
2092 | i915_gem_get_seqno(struct drm_device *dev, u32 *seqno) | |
53d227f2 | 2093 | { |
9d773091 CW |
2094 | struct drm_i915_private *dev_priv = dev->dev_private; |
2095 | ||
2096 | /* reserve 0 for non-seqno */ | |
2097 | if (dev_priv->next_seqno == 0) { | |
fca26bb4 | 2098 | int ret = i915_gem_init_seqno(dev, 0); |
9d773091 CW |
2099 | if (ret) |
2100 | return ret; | |
53d227f2 | 2101 | |
9d773091 CW |
2102 | dev_priv->next_seqno = 1; |
2103 | } | |
53d227f2 | 2104 | |
f72b3435 | 2105 | *seqno = dev_priv->last_seqno = dev_priv->next_seqno++; |
9d773091 | 2106 | return 0; |
53d227f2 DV |
2107 | } |
2108 | ||
0025c077 MK |
2109 | int __i915_add_request(struct intel_ring_buffer *ring, |
2110 | struct drm_file *file, | |
7d736f4f | 2111 | struct drm_i915_gem_object *obj, |
0025c077 | 2112 | u32 *out_seqno) |
673a394b | 2113 | { |
db53a302 | 2114 | drm_i915_private_t *dev_priv = ring->dev->dev_private; |
acb868d3 | 2115 | struct drm_i915_gem_request *request; |
7d736f4f | 2116 | u32 request_ring_position, request_start; |
673a394b | 2117 | int was_empty; |
3cce469c CW |
2118 | int ret; |
2119 | ||
7d736f4f | 2120 | request_start = intel_ring_get_tail(ring); |
cc889e0f DV |
2121 | /* |
2122 | * Emit any outstanding flushes - execbuf can fail to emit the flush | |
2123 | * after having emitted the batchbuffer command. Hence we need to fix | |
2124 | * things up similar to emitting the lazy request. The difference here | |
2125 | * is that the flush _must_ happen before the next request, no matter | |
2126 | * what. | |
2127 | */ | |
a7b9761d CW |
2128 | ret = intel_ring_flush_all_caches(ring); |
2129 | if (ret) | |
2130 | return ret; | |
cc889e0f | 2131 | |
3c0e234c CW |
2132 | request = ring->preallocated_lazy_request; |
2133 | if (WARN_ON(request == NULL)) | |
acb868d3 | 2134 | return -ENOMEM; |
cc889e0f | 2135 | |
a71d8d94 CW |
2136 | /* Record the position of the start of the request so that |
2137 | * should we detect the updated seqno part-way through the | |
2138 | * GPU processing the request, we never over-estimate the | |
2139 | * position of the head. | |
2140 | */ | |
2141 | request_ring_position = intel_ring_get_tail(ring); | |
2142 | ||
9d773091 | 2143 | ret = ring->add_request(ring); |
3c0e234c | 2144 | if (ret) |
3bb73aba | 2145 | return ret; |
673a394b | 2146 | |
9d773091 | 2147 | request->seqno = intel_ring_get_seqno(ring); |
852835f3 | 2148 | request->ring = ring; |
7d736f4f | 2149 | request->head = request_start; |
a71d8d94 | 2150 | request->tail = request_ring_position; |
7d736f4f MK |
2151 | |
2152 | /* Whilst this request exists, batch_obj will be on the | |
2153 | * active_list, and so will hold the active reference. Only when this | |
2154 | * request is retired will the the batch_obj be moved onto the | |
2155 | * inactive_list and lose its active reference. Hence we do not need | |
2156 | * to explicitly hold another reference here. | |
2157 | */ | |
9a7e0c2a | 2158 | request->batch_obj = obj; |
0e50e96b | 2159 | |
9a7e0c2a CW |
2160 | /* Hold a reference to the current context so that we can inspect |
2161 | * it later in case a hangcheck error event fires. | |
2162 | */ | |
2163 | request->ctx = ring->last_context; | |
0e50e96b MK |
2164 | if (request->ctx) |
2165 | i915_gem_context_reference(request->ctx); | |
2166 | ||
673a394b | 2167 | request->emitted_jiffies = jiffies; |
852835f3 ZN |
2168 | was_empty = list_empty(&ring->request_list); |
2169 | list_add_tail(&request->list, &ring->request_list); | |
3bb73aba | 2170 | request->file_priv = NULL; |
852835f3 | 2171 | |
db53a302 CW |
2172 | if (file) { |
2173 | struct drm_i915_file_private *file_priv = file->driver_priv; | |
2174 | ||
1c25595f | 2175 | spin_lock(&file_priv->mm.lock); |
f787a5f5 | 2176 | request->file_priv = file_priv; |
b962442e | 2177 | list_add_tail(&request->client_list, |
f787a5f5 | 2178 | &file_priv->mm.request_list); |
1c25595f | 2179 | spin_unlock(&file_priv->mm.lock); |
b962442e | 2180 | } |
673a394b | 2181 | |
9d773091 | 2182 | trace_i915_gem_request_add(ring, request->seqno); |
1823521d | 2183 | ring->outstanding_lazy_seqno = 0; |
3c0e234c | 2184 | ring->preallocated_lazy_request = NULL; |
db53a302 | 2185 | |
db1b76ca | 2186 | if (!dev_priv->ums.mm_suspended) { |
10cd45b6 MK |
2187 | i915_queue_hangcheck(ring->dev); |
2188 | ||
f047e395 | 2189 | if (was_empty) { |
b29c19b6 | 2190 | cancel_delayed_work_sync(&dev_priv->mm.idle_work); |
b3b079db | 2191 | queue_delayed_work(dev_priv->wq, |
bcb45086 CW |
2192 | &dev_priv->mm.retire_work, |
2193 | round_jiffies_up_relative(HZ)); | |
f047e395 CW |
2194 | intel_mark_busy(dev_priv->dev); |
2195 | } | |
f65d9421 | 2196 | } |
cc889e0f | 2197 | |
acb868d3 | 2198 | if (out_seqno) |
9d773091 | 2199 | *out_seqno = request->seqno; |
3cce469c | 2200 | return 0; |
673a394b EA |
2201 | } |
2202 | ||
f787a5f5 CW |
2203 | static inline void |
2204 | i915_gem_request_remove_from_client(struct drm_i915_gem_request *request) | |
673a394b | 2205 | { |
1c25595f | 2206 | struct drm_i915_file_private *file_priv = request->file_priv; |
673a394b | 2207 | |
1c25595f CW |
2208 | if (!file_priv) |
2209 | return; | |
1c5d22f7 | 2210 | |
1c25595f | 2211 | spin_lock(&file_priv->mm.lock); |
b29c19b6 CW |
2212 | list_del(&request->client_list); |
2213 | request->file_priv = NULL; | |
1c25595f | 2214 | spin_unlock(&file_priv->mm.lock); |
673a394b | 2215 | } |
673a394b | 2216 | |
d1ccbb5d BW |
2217 | static bool i915_head_inside_object(u32 acthd, struct drm_i915_gem_object *obj, |
2218 | struct i915_address_space *vm) | |
aa60c664 | 2219 | { |
d1ccbb5d BW |
2220 | if (acthd >= i915_gem_obj_offset(obj, vm) && |
2221 | acthd < i915_gem_obj_offset(obj, vm) + obj->base.size) | |
aa60c664 MK |
2222 | return true; |
2223 | ||
2224 | return false; | |
2225 | } | |
2226 | ||
2227 | static bool i915_head_inside_request(const u32 acthd_unmasked, | |
2228 | const u32 request_start, | |
2229 | const u32 request_end) | |
2230 | { | |
2231 | const u32 acthd = acthd_unmasked & HEAD_ADDR; | |
2232 | ||
2233 | if (request_start < request_end) { | |
2234 | if (acthd >= request_start && acthd < request_end) | |
2235 | return true; | |
2236 | } else if (request_start > request_end) { | |
2237 | if (acthd >= request_start || acthd < request_end) | |
2238 | return true; | |
2239 | } | |
2240 | ||
2241 | return false; | |
2242 | } | |
2243 | ||
d1ccbb5d BW |
2244 | static struct i915_address_space * |
2245 | request_to_vm(struct drm_i915_gem_request *request) | |
2246 | { | |
2247 | struct drm_i915_private *dev_priv = request->ring->dev->dev_private; | |
2248 | struct i915_address_space *vm; | |
2249 | ||
2250 | vm = &dev_priv->gtt.base; | |
2251 | ||
2252 | return vm; | |
2253 | } | |
2254 | ||
aa60c664 MK |
2255 | static bool i915_request_guilty(struct drm_i915_gem_request *request, |
2256 | const u32 acthd, bool *inside) | |
2257 | { | |
2258 | /* There is a possibility that unmasked head address | |
2259 | * pointing inside the ring, matches the batch_obj address range. | |
2260 | * However this is extremely unlikely. | |
2261 | */ | |
aa60c664 | 2262 | if (request->batch_obj) { |
d1ccbb5d BW |
2263 | if (i915_head_inside_object(acthd, request->batch_obj, |
2264 | request_to_vm(request))) { | |
aa60c664 MK |
2265 | *inside = true; |
2266 | return true; | |
2267 | } | |
2268 | } | |
2269 | ||
2270 | if (i915_head_inside_request(acthd, request->head, request->tail)) { | |
2271 | *inside = false; | |
2272 | return true; | |
2273 | } | |
2274 | ||
2275 | return false; | |
2276 | } | |
2277 | ||
be62acb4 MK |
2278 | static bool i915_context_is_banned(const struct i915_ctx_hang_stats *hs) |
2279 | { | |
2280 | const unsigned long elapsed = get_seconds() - hs->guilty_ts; | |
2281 | ||
2282 | if (hs->banned) | |
2283 | return true; | |
2284 | ||
2285 | if (elapsed <= DRM_I915_CTX_BAN_PERIOD) { | |
2286 | DRM_ERROR("context hanging too fast, declaring banned!\n"); | |
2287 | return true; | |
2288 | } | |
2289 | ||
2290 | return false; | |
2291 | } | |
2292 | ||
aa60c664 MK |
2293 | static void i915_set_reset_status(struct intel_ring_buffer *ring, |
2294 | struct drm_i915_gem_request *request, | |
2295 | u32 acthd) | |
2296 | { | |
2297 | struct i915_ctx_hang_stats *hs = NULL; | |
2298 | bool inside, guilty; | |
d1ccbb5d | 2299 | unsigned long offset = 0; |
aa60c664 MK |
2300 | |
2301 | /* Innocent until proven guilty */ | |
2302 | guilty = false; | |
2303 | ||
d1ccbb5d BW |
2304 | if (request->batch_obj) |
2305 | offset = i915_gem_obj_offset(request->batch_obj, | |
2306 | request_to_vm(request)); | |
2307 | ||
f2f4d82f | 2308 | if (ring->hangcheck.action != HANGCHECK_WAIT && |
aa60c664 | 2309 | i915_request_guilty(request, acthd, &inside)) { |
f343c5f6 | 2310 | DRM_ERROR("%s hung %s bo (0x%lx ctx %d) at 0x%x\n", |
aa60c664 MK |
2311 | ring->name, |
2312 | inside ? "inside" : "flushing", | |
d1ccbb5d | 2313 | offset, |
aa60c664 MK |
2314 | request->ctx ? request->ctx->id : 0, |
2315 | acthd); | |
2316 | ||
2317 | guilty = true; | |
2318 | } | |
2319 | ||
2320 | /* If contexts are disabled or this is the default context, use | |
2321 | * file_priv->reset_state | |
2322 | */ | |
2323 | if (request->ctx && request->ctx->id != DEFAULT_CONTEXT_ID) | |
2324 | hs = &request->ctx->hang_stats; | |
2325 | else if (request->file_priv) | |
2326 | hs = &request->file_priv->hang_stats; | |
2327 | ||
2328 | if (hs) { | |
be62acb4 MK |
2329 | if (guilty) { |
2330 | hs->banned = i915_context_is_banned(hs); | |
aa60c664 | 2331 | hs->batch_active++; |
be62acb4 MK |
2332 | hs->guilty_ts = get_seconds(); |
2333 | } else { | |
aa60c664 | 2334 | hs->batch_pending++; |
be62acb4 | 2335 | } |
aa60c664 MK |
2336 | } |
2337 | } | |
2338 | ||
0e50e96b MK |
2339 | static void i915_gem_free_request(struct drm_i915_gem_request *request) |
2340 | { | |
2341 | list_del(&request->list); | |
2342 | i915_gem_request_remove_from_client(request); | |
2343 | ||
2344 | if (request->ctx) | |
2345 | i915_gem_context_unreference(request->ctx); | |
2346 | ||
2347 | kfree(request); | |
2348 | } | |
2349 | ||
dfaae392 CW |
2350 | static void i915_gem_reset_ring_lists(struct drm_i915_private *dev_priv, |
2351 | struct intel_ring_buffer *ring) | |
9375e446 | 2352 | { |
aa60c664 MK |
2353 | u32 completed_seqno; |
2354 | u32 acthd; | |
2355 | ||
2356 | acthd = intel_ring_get_active_head(ring); | |
2357 | completed_seqno = ring->get_seqno(ring, false); | |
2358 | ||
dfaae392 CW |
2359 | while (!list_empty(&ring->request_list)) { |
2360 | struct drm_i915_gem_request *request; | |
673a394b | 2361 | |
dfaae392 CW |
2362 | request = list_first_entry(&ring->request_list, |
2363 | struct drm_i915_gem_request, | |
2364 | list); | |
de151cf6 | 2365 | |
aa60c664 MK |
2366 | if (request->seqno > completed_seqno) |
2367 | i915_set_reset_status(ring, request, acthd); | |
2368 | ||
0e50e96b | 2369 | i915_gem_free_request(request); |
dfaae392 | 2370 | } |
673a394b | 2371 | |
dfaae392 | 2372 | while (!list_empty(&ring->active_list)) { |
05394f39 | 2373 | struct drm_i915_gem_object *obj; |
9375e446 | 2374 | |
05394f39 CW |
2375 | obj = list_first_entry(&ring->active_list, |
2376 | struct drm_i915_gem_object, | |
2377 | ring_list); | |
9375e446 | 2378 | |
05394f39 | 2379 | i915_gem_object_move_to_inactive(obj); |
673a394b EA |
2380 | } |
2381 | } | |
2382 | ||
19b2dbde | 2383 | void i915_gem_restore_fences(struct drm_device *dev) |
312817a3 CW |
2384 | { |
2385 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2386 | int i; | |
2387 | ||
4b9de737 | 2388 | for (i = 0; i < dev_priv->num_fence_regs; i++) { |
312817a3 | 2389 | struct drm_i915_fence_reg *reg = &dev_priv->fence_regs[i]; |
7d2cb39c | 2390 | |
94a335db DV |
2391 | /* |
2392 | * Commit delayed tiling changes if we have an object still | |
2393 | * attached to the fence, otherwise just clear the fence. | |
2394 | */ | |
2395 | if (reg->obj) { | |
2396 | i915_gem_object_update_fence(reg->obj, reg, | |
2397 | reg->obj->tiling_mode); | |
2398 | } else { | |
2399 | i915_gem_write_fence(dev, i, NULL); | |
2400 | } | |
312817a3 CW |
2401 | } |
2402 | } | |
2403 | ||
069efc1d | 2404 | void i915_gem_reset(struct drm_device *dev) |
673a394b | 2405 | { |
77f01230 | 2406 | struct drm_i915_private *dev_priv = dev->dev_private; |
b4519513 | 2407 | struct intel_ring_buffer *ring; |
1ec14ad3 | 2408 | int i; |
673a394b | 2409 | |
b4519513 CW |
2410 | for_each_ring(ring, dev_priv, i) |
2411 | i915_gem_reset_ring_lists(dev_priv, ring); | |
dfaae392 | 2412 | |
3d57e5bd BW |
2413 | i915_gem_cleanup_ringbuffer(dev); |
2414 | ||
19b2dbde | 2415 | i915_gem_restore_fences(dev); |
673a394b EA |
2416 | } |
2417 | ||
2418 | /** | |
2419 | * This function clears the request list as sequence numbers are passed. | |
2420 | */ | |
a71d8d94 | 2421 | void |
db53a302 | 2422 | i915_gem_retire_requests_ring(struct intel_ring_buffer *ring) |
673a394b | 2423 | { |
673a394b EA |
2424 | uint32_t seqno; |
2425 | ||
db53a302 | 2426 | if (list_empty(&ring->request_list)) |
6c0594a3 KW |
2427 | return; |
2428 | ||
db53a302 | 2429 | WARN_ON(i915_verify_lists(ring->dev)); |
673a394b | 2430 | |
b2eadbc8 | 2431 | seqno = ring->get_seqno(ring, true); |
1ec14ad3 | 2432 | |
852835f3 | 2433 | while (!list_empty(&ring->request_list)) { |
673a394b | 2434 | struct drm_i915_gem_request *request; |
673a394b | 2435 | |
852835f3 | 2436 | request = list_first_entry(&ring->request_list, |
673a394b EA |
2437 | struct drm_i915_gem_request, |
2438 | list); | |
673a394b | 2439 | |
dfaae392 | 2440 | if (!i915_seqno_passed(seqno, request->seqno)) |
b84d5f0c CW |
2441 | break; |
2442 | ||
db53a302 | 2443 | trace_i915_gem_request_retire(ring, request->seqno); |
a71d8d94 CW |
2444 | /* We know the GPU must have read the request to have |
2445 | * sent us the seqno + interrupt, so use the position | |
2446 | * of tail of the request to update the last known position | |
2447 | * of the GPU head. | |
2448 | */ | |
2449 | ring->last_retired_head = request->tail; | |
b84d5f0c | 2450 | |
0e50e96b | 2451 | i915_gem_free_request(request); |
b84d5f0c | 2452 | } |
673a394b | 2453 | |
b84d5f0c CW |
2454 | /* Move any buffers on the active list that are no longer referenced |
2455 | * by the ringbuffer to the flushing/inactive lists as appropriate. | |
2456 | */ | |
2457 | while (!list_empty(&ring->active_list)) { | |
05394f39 | 2458 | struct drm_i915_gem_object *obj; |
b84d5f0c | 2459 | |
0206e353 | 2460 | obj = list_first_entry(&ring->active_list, |
05394f39 CW |
2461 | struct drm_i915_gem_object, |
2462 | ring_list); | |
673a394b | 2463 | |
0201f1ec | 2464 | if (!i915_seqno_passed(seqno, obj->last_read_seqno)) |
673a394b | 2465 | break; |
b84d5f0c | 2466 | |
65ce3027 | 2467 | i915_gem_object_move_to_inactive(obj); |
673a394b | 2468 | } |
9d34e5db | 2469 | |
db53a302 CW |
2470 | if (unlikely(ring->trace_irq_seqno && |
2471 | i915_seqno_passed(seqno, ring->trace_irq_seqno))) { | |
1ec14ad3 | 2472 | ring->irq_put(ring); |
db53a302 | 2473 | ring->trace_irq_seqno = 0; |
9d34e5db | 2474 | } |
23bc5982 | 2475 | |
db53a302 | 2476 | WARN_ON(i915_verify_lists(ring->dev)); |
673a394b EA |
2477 | } |
2478 | ||
b29c19b6 | 2479 | bool |
b09a1fec CW |
2480 | i915_gem_retire_requests(struct drm_device *dev) |
2481 | { | |
2482 | drm_i915_private_t *dev_priv = dev->dev_private; | |
b4519513 | 2483 | struct intel_ring_buffer *ring; |
b29c19b6 | 2484 | bool idle = true; |
1ec14ad3 | 2485 | int i; |
b09a1fec | 2486 | |
b29c19b6 | 2487 | for_each_ring(ring, dev_priv, i) { |
b4519513 | 2488 | i915_gem_retire_requests_ring(ring); |
b29c19b6 CW |
2489 | idle &= list_empty(&ring->request_list); |
2490 | } | |
2491 | ||
2492 | if (idle) | |
2493 | mod_delayed_work(dev_priv->wq, | |
2494 | &dev_priv->mm.idle_work, | |
2495 | msecs_to_jiffies(100)); | |
2496 | ||
2497 | return idle; | |
b09a1fec CW |
2498 | } |
2499 | ||
75ef9da2 | 2500 | static void |
673a394b EA |
2501 | i915_gem_retire_work_handler(struct work_struct *work) |
2502 | { | |
b29c19b6 CW |
2503 | struct drm_i915_private *dev_priv = |
2504 | container_of(work, typeof(*dev_priv), mm.retire_work.work); | |
2505 | struct drm_device *dev = dev_priv->dev; | |
0a58705b | 2506 | bool idle; |
673a394b | 2507 | |
891b48cf | 2508 | /* Come back later if the device is busy... */ |
b29c19b6 CW |
2509 | idle = false; |
2510 | if (mutex_trylock(&dev->struct_mutex)) { | |
2511 | idle = i915_gem_retire_requests(dev); | |
2512 | mutex_unlock(&dev->struct_mutex); | |
673a394b | 2513 | } |
b29c19b6 | 2514 | if (!idle) |
bcb45086 CW |
2515 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, |
2516 | round_jiffies_up_relative(HZ)); | |
b29c19b6 | 2517 | } |
0a58705b | 2518 | |
b29c19b6 CW |
2519 | static void |
2520 | i915_gem_idle_work_handler(struct work_struct *work) | |
2521 | { | |
2522 | struct drm_i915_private *dev_priv = | |
2523 | container_of(work, typeof(*dev_priv), mm.idle_work.work); | |
2524 | ||
2525 | intel_mark_idle(dev_priv->dev); | |
673a394b EA |
2526 | } |
2527 | ||
30dfebf3 DV |
2528 | /** |
2529 | * Ensures that an object will eventually get non-busy by flushing any required | |
2530 | * write domains, emitting any outstanding lazy request and retiring and | |
2531 | * completed requests. | |
2532 | */ | |
2533 | static int | |
2534 | i915_gem_object_flush_active(struct drm_i915_gem_object *obj) | |
2535 | { | |
2536 | int ret; | |
2537 | ||
2538 | if (obj->active) { | |
0201f1ec | 2539 | ret = i915_gem_check_olr(obj->ring, obj->last_read_seqno); |
30dfebf3 DV |
2540 | if (ret) |
2541 | return ret; | |
2542 | ||
30dfebf3 DV |
2543 | i915_gem_retire_requests_ring(obj->ring); |
2544 | } | |
2545 | ||
2546 | return 0; | |
2547 | } | |
2548 | ||
23ba4fd0 BW |
2549 | /** |
2550 | * i915_gem_wait_ioctl - implements DRM_IOCTL_I915_GEM_WAIT | |
2551 | * @DRM_IOCTL_ARGS: standard ioctl arguments | |
2552 | * | |
2553 | * Returns 0 if successful, else an error is returned with the remaining time in | |
2554 | * the timeout parameter. | |
2555 | * -ETIME: object is still busy after timeout | |
2556 | * -ERESTARTSYS: signal interrupted the wait | |
2557 | * -ENONENT: object doesn't exist | |
2558 | * Also possible, but rare: | |
2559 | * -EAGAIN: GPU wedged | |
2560 | * -ENOMEM: damn | |
2561 | * -ENODEV: Internal IRQ fail | |
2562 | * -E?: The add request failed | |
2563 | * | |
2564 | * The wait ioctl with a timeout of 0 reimplements the busy ioctl. With any | |
2565 | * non-zero timeout parameter the wait ioctl will wait for the given number of | |
2566 | * nanoseconds on an object becoming unbusy. Since the wait itself does so | |
2567 | * without holding struct_mutex the object may become re-busied before this | |
2568 | * function completes. A similar but shorter * race condition exists in the busy | |
2569 | * ioctl | |
2570 | */ | |
2571 | int | |
2572 | i915_gem_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *file) | |
2573 | { | |
f69061be | 2574 | drm_i915_private_t *dev_priv = dev->dev_private; |
23ba4fd0 BW |
2575 | struct drm_i915_gem_wait *args = data; |
2576 | struct drm_i915_gem_object *obj; | |
2577 | struct intel_ring_buffer *ring = NULL; | |
eac1f14f | 2578 | struct timespec timeout_stack, *timeout = NULL; |
f69061be | 2579 | unsigned reset_counter; |
23ba4fd0 BW |
2580 | u32 seqno = 0; |
2581 | int ret = 0; | |
2582 | ||
eac1f14f BW |
2583 | if (args->timeout_ns >= 0) { |
2584 | timeout_stack = ns_to_timespec(args->timeout_ns); | |
2585 | timeout = &timeout_stack; | |
2586 | } | |
23ba4fd0 BW |
2587 | |
2588 | ret = i915_mutex_lock_interruptible(dev); | |
2589 | if (ret) | |
2590 | return ret; | |
2591 | ||
2592 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->bo_handle)); | |
2593 | if (&obj->base == NULL) { | |
2594 | mutex_unlock(&dev->struct_mutex); | |
2595 | return -ENOENT; | |
2596 | } | |
2597 | ||
30dfebf3 DV |
2598 | /* Need to make sure the object gets inactive eventually. */ |
2599 | ret = i915_gem_object_flush_active(obj); | |
23ba4fd0 BW |
2600 | if (ret) |
2601 | goto out; | |
2602 | ||
2603 | if (obj->active) { | |
0201f1ec | 2604 | seqno = obj->last_read_seqno; |
23ba4fd0 BW |
2605 | ring = obj->ring; |
2606 | } | |
2607 | ||
2608 | if (seqno == 0) | |
2609 | goto out; | |
2610 | ||
23ba4fd0 BW |
2611 | /* Do this after OLR check to make sure we make forward progress polling |
2612 | * on this IOCTL with a 0 timeout (like busy ioctl) | |
2613 | */ | |
2614 | if (!args->timeout_ns) { | |
2615 | ret = -ETIME; | |
2616 | goto out; | |
2617 | } | |
2618 | ||
2619 | drm_gem_object_unreference(&obj->base); | |
f69061be | 2620 | reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter); |
23ba4fd0 BW |
2621 | mutex_unlock(&dev->struct_mutex); |
2622 | ||
b29c19b6 | 2623 | ret = __wait_seqno(ring, seqno, reset_counter, true, timeout, file->driver_priv); |
4f42f4ef | 2624 | if (timeout) |
eac1f14f | 2625 | args->timeout_ns = timespec_to_ns(timeout); |
23ba4fd0 BW |
2626 | return ret; |
2627 | ||
2628 | out: | |
2629 | drm_gem_object_unreference(&obj->base); | |
2630 | mutex_unlock(&dev->struct_mutex); | |
2631 | return ret; | |
2632 | } | |
2633 | ||
5816d648 BW |
2634 | /** |
2635 | * i915_gem_object_sync - sync an object to a ring. | |
2636 | * | |
2637 | * @obj: object which may be in use on another ring. | |
2638 | * @to: ring we wish to use the object on. May be NULL. | |
2639 | * | |
2640 | * This code is meant to abstract object synchronization with the GPU. | |
2641 | * Calling with NULL implies synchronizing the object with the CPU | |
2642 | * rather than a particular GPU ring. | |
2643 | * | |
2644 | * Returns 0 if successful, else propagates up the lower layer error. | |
2645 | */ | |
2911a35b BW |
2646 | int |
2647 | i915_gem_object_sync(struct drm_i915_gem_object *obj, | |
2648 | struct intel_ring_buffer *to) | |
2649 | { | |
2650 | struct intel_ring_buffer *from = obj->ring; | |
2651 | u32 seqno; | |
2652 | int ret, idx; | |
2653 | ||
2654 | if (from == NULL || to == from) | |
2655 | return 0; | |
2656 | ||
5816d648 | 2657 | if (to == NULL || !i915_semaphore_is_enabled(obj->base.dev)) |
0201f1ec | 2658 | return i915_gem_object_wait_rendering(obj, false); |
2911a35b BW |
2659 | |
2660 | idx = intel_ring_sync_index(from, to); | |
2661 | ||
0201f1ec | 2662 | seqno = obj->last_read_seqno; |
2911a35b BW |
2663 | if (seqno <= from->sync_seqno[idx]) |
2664 | return 0; | |
2665 | ||
b4aca010 BW |
2666 | ret = i915_gem_check_olr(obj->ring, seqno); |
2667 | if (ret) | |
2668 | return ret; | |
2911a35b | 2669 | |
b52b89da | 2670 | trace_i915_gem_ring_sync_to(from, to, seqno); |
1500f7ea | 2671 | ret = to->sync_to(to, from, seqno); |
e3a5a225 | 2672 | if (!ret) |
7b01e260 MK |
2673 | /* We use last_read_seqno because sync_to() |
2674 | * might have just caused seqno wrap under | |
2675 | * the radar. | |
2676 | */ | |
2677 | from->sync_seqno[idx] = obj->last_read_seqno; | |
2911a35b | 2678 | |
e3a5a225 | 2679 | return ret; |
2911a35b BW |
2680 | } |
2681 | ||
b5ffc9bc CW |
2682 | static void i915_gem_object_finish_gtt(struct drm_i915_gem_object *obj) |
2683 | { | |
2684 | u32 old_write_domain, old_read_domains; | |
2685 | ||
b5ffc9bc CW |
2686 | /* Force a pagefault for domain tracking on next user access */ |
2687 | i915_gem_release_mmap(obj); | |
2688 | ||
b97c3d9c KP |
2689 | if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0) |
2690 | return; | |
2691 | ||
97c809fd CW |
2692 | /* Wait for any direct GTT access to complete */ |
2693 | mb(); | |
2694 | ||
b5ffc9bc CW |
2695 | old_read_domains = obj->base.read_domains; |
2696 | old_write_domain = obj->base.write_domain; | |
2697 | ||
2698 | obj->base.read_domains &= ~I915_GEM_DOMAIN_GTT; | |
2699 | obj->base.write_domain &= ~I915_GEM_DOMAIN_GTT; | |
2700 | ||
2701 | trace_i915_gem_object_change_domain(obj, | |
2702 | old_read_domains, | |
2703 | old_write_domain); | |
2704 | } | |
2705 | ||
07fe0b12 | 2706 | int i915_vma_unbind(struct i915_vma *vma) |
673a394b | 2707 | { |
07fe0b12 | 2708 | struct drm_i915_gem_object *obj = vma->obj; |
7bddb01f | 2709 | drm_i915_private_t *dev_priv = obj->base.dev->dev_private; |
43e28f09 | 2710 | int ret; |
673a394b | 2711 | |
b93dab6e DV |
2712 | /* For now we only ever use 1 vma per object */ |
2713 | WARN_ON(!list_is_singular(&obj->vma_list)); | |
2714 | ||
07fe0b12 | 2715 | if (list_empty(&vma->vma_link)) |
673a394b EA |
2716 | return 0; |
2717 | ||
0ff501cb DV |
2718 | if (!drm_mm_node_allocated(&vma->node)) { |
2719 | i915_gem_vma_destroy(vma); | |
2720 | ||
2721 | return 0; | |
2722 | } | |
433544bd | 2723 | |
d7f46fc4 | 2724 | if (vma->pin_count) |
31d8d651 | 2725 | return -EBUSY; |
673a394b | 2726 | |
c4670ad0 CW |
2727 | BUG_ON(obj->pages == NULL); |
2728 | ||
a8198eea | 2729 | ret = i915_gem_object_finish_gpu(obj); |
1488fc08 | 2730 | if (ret) |
a8198eea CW |
2731 | return ret; |
2732 | /* Continue on if we fail due to EIO, the GPU is hung so we | |
2733 | * should be safe and we need to cleanup or else we might | |
2734 | * cause memory corruption through use-after-free. | |
2735 | */ | |
2736 | ||
b5ffc9bc | 2737 | i915_gem_object_finish_gtt(obj); |
5323fd04 | 2738 | |
96b47b65 | 2739 | /* release the fence reg _after_ flushing */ |
d9e86c0e | 2740 | ret = i915_gem_object_put_fence(obj); |
1488fc08 | 2741 | if (ret) |
d9e86c0e | 2742 | return ret; |
96b47b65 | 2743 | |
07fe0b12 | 2744 | trace_i915_vma_unbind(vma); |
db53a302 | 2745 | |
74898d7e DV |
2746 | if (obj->has_global_gtt_mapping) |
2747 | i915_gem_gtt_unbind_object(obj); | |
7bddb01f DV |
2748 | if (obj->has_aliasing_ppgtt_mapping) { |
2749 | i915_ppgtt_unbind_object(dev_priv->mm.aliasing_ppgtt, obj); | |
2750 | obj->has_aliasing_ppgtt_mapping = 0; | |
2751 | } | |
74163907 | 2752 | i915_gem_gtt_finish_object(obj); |
7bddb01f | 2753 | |
ca191b13 | 2754 | list_del(&vma->mm_list); |
75e9e915 | 2755 | /* Avoid an unnecessary call to unbind on rebind. */ |
5cacaac7 BW |
2756 | if (i915_is_ggtt(vma->vm)) |
2757 | obj->map_and_fenceable = true; | |
673a394b | 2758 | |
2f633156 BW |
2759 | drm_mm_remove_node(&vma->node); |
2760 | i915_gem_vma_destroy(vma); | |
2761 | ||
2762 | /* Since the unbound list is global, only move to that list if | |
b93dab6e | 2763 | * no more VMAs exist. */ |
2f633156 BW |
2764 | if (list_empty(&obj->vma_list)) |
2765 | list_move_tail(&obj->global_list, &dev_priv->mm.unbound_list); | |
673a394b | 2766 | |
70903c3b CW |
2767 | /* And finally now the object is completely decoupled from this vma, |
2768 | * we can drop its hold on the backing storage and allow it to be | |
2769 | * reaped by the shrinker. | |
2770 | */ | |
2771 | i915_gem_object_unpin_pages(obj); | |
2772 | ||
88241785 | 2773 | return 0; |
54cf91dc CW |
2774 | } |
2775 | ||
07fe0b12 BW |
2776 | /** |
2777 | * Unbinds an object from the global GTT aperture. | |
2778 | */ | |
2779 | int | |
2780 | i915_gem_object_ggtt_unbind(struct drm_i915_gem_object *obj) | |
2781 | { | |
2782 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; | |
2783 | struct i915_address_space *ggtt = &dev_priv->gtt.base; | |
2784 | ||
58e73e15 | 2785 | if (!i915_gem_obj_ggtt_bound(obj)) |
07fe0b12 BW |
2786 | return 0; |
2787 | ||
d7f46fc4 | 2788 | if (i915_gem_obj_to_ggtt(obj)->pin_count) |
07fe0b12 BW |
2789 | return -EBUSY; |
2790 | ||
2791 | BUG_ON(obj->pages == NULL); | |
2792 | ||
2793 | return i915_vma_unbind(i915_gem_obj_to_vma(obj, ggtt)); | |
2794 | } | |
2795 | ||
b2da9fe5 | 2796 | int i915_gpu_idle(struct drm_device *dev) |
4df2faf4 DV |
2797 | { |
2798 | drm_i915_private_t *dev_priv = dev->dev_private; | |
b4519513 | 2799 | struct intel_ring_buffer *ring; |
1ec14ad3 | 2800 | int ret, i; |
4df2faf4 | 2801 | |
4df2faf4 | 2802 | /* Flush everything onto the inactive list. */ |
b4519513 | 2803 | for_each_ring(ring, dev_priv, i) { |
b6c7488d BW |
2804 | ret = i915_switch_context(ring, NULL, DEFAULT_CONTEXT_ID); |
2805 | if (ret) | |
2806 | return ret; | |
2807 | ||
3e960501 | 2808 | ret = intel_ring_idle(ring); |
1ec14ad3 CW |
2809 | if (ret) |
2810 | return ret; | |
2811 | } | |
4df2faf4 | 2812 | |
8a1a49f9 | 2813 | return 0; |
4df2faf4 DV |
2814 | } |
2815 | ||
9ce079e4 CW |
2816 | static void i965_write_fence_reg(struct drm_device *dev, int reg, |
2817 | struct drm_i915_gem_object *obj) | |
de151cf6 | 2818 | { |
de151cf6 | 2819 | drm_i915_private_t *dev_priv = dev->dev_private; |
56c844e5 ID |
2820 | int fence_reg; |
2821 | int fence_pitch_shift; | |
de151cf6 | 2822 | |
56c844e5 ID |
2823 | if (INTEL_INFO(dev)->gen >= 6) { |
2824 | fence_reg = FENCE_REG_SANDYBRIDGE_0; | |
2825 | fence_pitch_shift = SANDYBRIDGE_FENCE_PITCH_SHIFT; | |
2826 | } else { | |
2827 | fence_reg = FENCE_REG_965_0; | |
2828 | fence_pitch_shift = I965_FENCE_PITCH_SHIFT; | |
2829 | } | |
2830 | ||
d18b9619 CW |
2831 | fence_reg += reg * 8; |
2832 | ||
2833 | /* To w/a incoherency with non-atomic 64-bit register updates, | |
2834 | * we split the 64-bit update into two 32-bit writes. In order | |
2835 | * for a partial fence not to be evaluated between writes, we | |
2836 | * precede the update with write to turn off the fence register, | |
2837 | * and only enable the fence as the last step. | |
2838 | * | |
2839 | * For extra levels of paranoia, we make sure each step lands | |
2840 | * before applying the next step. | |
2841 | */ | |
2842 | I915_WRITE(fence_reg, 0); | |
2843 | POSTING_READ(fence_reg); | |
2844 | ||
9ce079e4 | 2845 | if (obj) { |
f343c5f6 | 2846 | u32 size = i915_gem_obj_ggtt_size(obj); |
d18b9619 | 2847 | uint64_t val; |
de151cf6 | 2848 | |
f343c5f6 | 2849 | val = (uint64_t)((i915_gem_obj_ggtt_offset(obj) + size - 4096) & |
9ce079e4 | 2850 | 0xfffff000) << 32; |
f343c5f6 | 2851 | val |= i915_gem_obj_ggtt_offset(obj) & 0xfffff000; |
56c844e5 | 2852 | val |= (uint64_t)((obj->stride / 128) - 1) << fence_pitch_shift; |
9ce079e4 CW |
2853 | if (obj->tiling_mode == I915_TILING_Y) |
2854 | val |= 1 << I965_FENCE_TILING_Y_SHIFT; | |
2855 | val |= I965_FENCE_REG_VALID; | |
c6642782 | 2856 | |
d18b9619 CW |
2857 | I915_WRITE(fence_reg + 4, val >> 32); |
2858 | POSTING_READ(fence_reg + 4); | |
2859 | ||
2860 | I915_WRITE(fence_reg + 0, val); | |
2861 | POSTING_READ(fence_reg); | |
2862 | } else { | |
2863 | I915_WRITE(fence_reg + 4, 0); | |
2864 | POSTING_READ(fence_reg + 4); | |
2865 | } | |
de151cf6 JB |
2866 | } |
2867 | ||
9ce079e4 CW |
2868 | static void i915_write_fence_reg(struct drm_device *dev, int reg, |
2869 | struct drm_i915_gem_object *obj) | |
de151cf6 | 2870 | { |
de151cf6 | 2871 | drm_i915_private_t *dev_priv = dev->dev_private; |
9ce079e4 | 2872 | u32 val; |
de151cf6 | 2873 | |
9ce079e4 | 2874 | if (obj) { |
f343c5f6 | 2875 | u32 size = i915_gem_obj_ggtt_size(obj); |
9ce079e4 CW |
2876 | int pitch_val; |
2877 | int tile_width; | |
c6642782 | 2878 | |
f343c5f6 | 2879 | WARN((i915_gem_obj_ggtt_offset(obj) & ~I915_FENCE_START_MASK) || |
9ce079e4 | 2880 | (size & -size) != size || |
f343c5f6 BW |
2881 | (i915_gem_obj_ggtt_offset(obj) & (size - 1)), |
2882 | "object 0x%08lx [fenceable? %d] not 1M or pot-size (0x%08x) aligned\n", | |
2883 | i915_gem_obj_ggtt_offset(obj), obj->map_and_fenceable, size); | |
c6642782 | 2884 | |
9ce079e4 CW |
2885 | if (obj->tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev)) |
2886 | tile_width = 128; | |
2887 | else | |
2888 | tile_width = 512; | |
2889 | ||
2890 | /* Note: pitch better be a power of two tile widths */ | |
2891 | pitch_val = obj->stride / tile_width; | |
2892 | pitch_val = ffs(pitch_val) - 1; | |
2893 | ||
f343c5f6 | 2894 | val = i915_gem_obj_ggtt_offset(obj); |
9ce079e4 CW |
2895 | if (obj->tiling_mode == I915_TILING_Y) |
2896 | val |= 1 << I830_FENCE_TILING_Y_SHIFT; | |
2897 | val |= I915_FENCE_SIZE_BITS(size); | |
2898 | val |= pitch_val << I830_FENCE_PITCH_SHIFT; | |
2899 | val |= I830_FENCE_REG_VALID; | |
2900 | } else | |
2901 | val = 0; | |
2902 | ||
2903 | if (reg < 8) | |
2904 | reg = FENCE_REG_830_0 + reg * 4; | |
2905 | else | |
2906 | reg = FENCE_REG_945_8 + (reg - 8) * 4; | |
2907 | ||
2908 | I915_WRITE(reg, val); | |
2909 | POSTING_READ(reg); | |
de151cf6 JB |
2910 | } |
2911 | ||
9ce079e4 CW |
2912 | static void i830_write_fence_reg(struct drm_device *dev, int reg, |
2913 | struct drm_i915_gem_object *obj) | |
de151cf6 | 2914 | { |
de151cf6 | 2915 | drm_i915_private_t *dev_priv = dev->dev_private; |
de151cf6 | 2916 | uint32_t val; |
de151cf6 | 2917 | |
9ce079e4 | 2918 | if (obj) { |
f343c5f6 | 2919 | u32 size = i915_gem_obj_ggtt_size(obj); |
9ce079e4 | 2920 | uint32_t pitch_val; |
de151cf6 | 2921 | |
f343c5f6 | 2922 | WARN((i915_gem_obj_ggtt_offset(obj) & ~I830_FENCE_START_MASK) || |
9ce079e4 | 2923 | (size & -size) != size || |
f343c5f6 BW |
2924 | (i915_gem_obj_ggtt_offset(obj) & (size - 1)), |
2925 | "object 0x%08lx not 512K or pot-size 0x%08x aligned\n", | |
2926 | i915_gem_obj_ggtt_offset(obj), size); | |
e76a16de | 2927 | |
9ce079e4 CW |
2928 | pitch_val = obj->stride / 128; |
2929 | pitch_val = ffs(pitch_val) - 1; | |
de151cf6 | 2930 | |
f343c5f6 | 2931 | val = i915_gem_obj_ggtt_offset(obj); |
9ce079e4 CW |
2932 | if (obj->tiling_mode == I915_TILING_Y) |
2933 | val |= 1 << I830_FENCE_TILING_Y_SHIFT; | |
2934 | val |= I830_FENCE_SIZE_BITS(size); | |
2935 | val |= pitch_val << I830_FENCE_PITCH_SHIFT; | |
2936 | val |= I830_FENCE_REG_VALID; | |
2937 | } else | |
2938 | val = 0; | |
c6642782 | 2939 | |
9ce079e4 CW |
2940 | I915_WRITE(FENCE_REG_830_0 + reg * 4, val); |
2941 | POSTING_READ(FENCE_REG_830_0 + reg * 4); | |
2942 | } | |
2943 | ||
d0a57789 CW |
2944 | inline static bool i915_gem_object_needs_mb(struct drm_i915_gem_object *obj) |
2945 | { | |
2946 | return obj && obj->base.read_domains & I915_GEM_DOMAIN_GTT; | |
2947 | } | |
2948 | ||
9ce079e4 CW |
2949 | static void i915_gem_write_fence(struct drm_device *dev, int reg, |
2950 | struct drm_i915_gem_object *obj) | |
2951 | { | |
d0a57789 CW |
2952 | struct drm_i915_private *dev_priv = dev->dev_private; |
2953 | ||
2954 | /* Ensure that all CPU reads are completed before installing a fence | |
2955 | * and all writes before removing the fence. | |
2956 | */ | |
2957 | if (i915_gem_object_needs_mb(dev_priv->fence_regs[reg].obj)) | |
2958 | mb(); | |
2959 | ||
94a335db DV |
2960 | WARN(obj && (!obj->stride || !obj->tiling_mode), |
2961 | "bogus fence setup with stride: 0x%x, tiling mode: %i\n", | |
2962 | obj->stride, obj->tiling_mode); | |
2963 | ||
9ce079e4 | 2964 | switch (INTEL_INFO(dev)->gen) { |
5ab31333 | 2965 | case 8: |
9ce079e4 | 2966 | case 7: |
56c844e5 | 2967 | case 6: |
9ce079e4 CW |
2968 | case 5: |
2969 | case 4: i965_write_fence_reg(dev, reg, obj); break; | |
2970 | case 3: i915_write_fence_reg(dev, reg, obj); break; | |
2971 | case 2: i830_write_fence_reg(dev, reg, obj); break; | |
7dbf9d6e | 2972 | default: BUG(); |
9ce079e4 | 2973 | } |
d0a57789 CW |
2974 | |
2975 | /* And similarly be paranoid that no direct access to this region | |
2976 | * is reordered to before the fence is installed. | |
2977 | */ | |
2978 | if (i915_gem_object_needs_mb(obj)) | |
2979 | mb(); | |
de151cf6 JB |
2980 | } |
2981 | ||
61050808 CW |
2982 | static inline int fence_number(struct drm_i915_private *dev_priv, |
2983 | struct drm_i915_fence_reg *fence) | |
2984 | { | |
2985 | return fence - dev_priv->fence_regs; | |
2986 | } | |
2987 | ||
2988 | static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj, | |
2989 | struct drm_i915_fence_reg *fence, | |
2990 | bool enable) | |
2991 | { | |
2dc8aae0 | 2992 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
46a0b638 CW |
2993 | int reg = fence_number(dev_priv, fence); |
2994 | ||
2995 | i915_gem_write_fence(obj->base.dev, reg, enable ? obj : NULL); | |
61050808 CW |
2996 | |
2997 | if (enable) { | |
46a0b638 | 2998 | obj->fence_reg = reg; |
61050808 CW |
2999 | fence->obj = obj; |
3000 | list_move_tail(&fence->lru_list, &dev_priv->mm.fence_list); | |
3001 | } else { | |
3002 | obj->fence_reg = I915_FENCE_REG_NONE; | |
3003 | fence->obj = NULL; | |
3004 | list_del_init(&fence->lru_list); | |
3005 | } | |
94a335db | 3006 | obj->fence_dirty = false; |
61050808 CW |
3007 | } |
3008 | ||
d9e86c0e | 3009 | static int |
d0a57789 | 3010 | i915_gem_object_wait_fence(struct drm_i915_gem_object *obj) |
d9e86c0e | 3011 | { |
1c293ea3 | 3012 | if (obj->last_fenced_seqno) { |
86d5bc37 | 3013 | int ret = i915_wait_seqno(obj->ring, obj->last_fenced_seqno); |
18991845 CW |
3014 | if (ret) |
3015 | return ret; | |
d9e86c0e CW |
3016 | |
3017 | obj->last_fenced_seqno = 0; | |
d9e86c0e CW |
3018 | } |
3019 | ||
86d5bc37 | 3020 | obj->fenced_gpu_access = false; |
d9e86c0e CW |
3021 | return 0; |
3022 | } | |
3023 | ||
3024 | int | |
3025 | i915_gem_object_put_fence(struct drm_i915_gem_object *obj) | |
3026 | { | |
61050808 | 3027 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
f9c513e9 | 3028 | struct drm_i915_fence_reg *fence; |
d9e86c0e CW |
3029 | int ret; |
3030 | ||
d0a57789 | 3031 | ret = i915_gem_object_wait_fence(obj); |
d9e86c0e CW |
3032 | if (ret) |
3033 | return ret; | |
3034 | ||
61050808 CW |
3035 | if (obj->fence_reg == I915_FENCE_REG_NONE) |
3036 | return 0; | |
d9e86c0e | 3037 | |
f9c513e9 CW |
3038 | fence = &dev_priv->fence_regs[obj->fence_reg]; |
3039 | ||
61050808 | 3040 | i915_gem_object_fence_lost(obj); |
f9c513e9 | 3041 | i915_gem_object_update_fence(obj, fence, false); |
d9e86c0e CW |
3042 | |
3043 | return 0; | |
3044 | } | |
3045 | ||
3046 | static struct drm_i915_fence_reg * | |
a360bb1a | 3047 | i915_find_fence_reg(struct drm_device *dev) |
ae3db24a | 3048 | { |
ae3db24a | 3049 | struct drm_i915_private *dev_priv = dev->dev_private; |
8fe301ad | 3050 | struct drm_i915_fence_reg *reg, *avail; |
d9e86c0e | 3051 | int i; |
ae3db24a DV |
3052 | |
3053 | /* First try to find a free reg */ | |
d9e86c0e | 3054 | avail = NULL; |
ae3db24a DV |
3055 | for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) { |
3056 | reg = &dev_priv->fence_regs[i]; | |
3057 | if (!reg->obj) | |
d9e86c0e | 3058 | return reg; |
ae3db24a | 3059 | |
1690e1eb | 3060 | if (!reg->pin_count) |
d9e86c0e | 3061 | avail = reg; |
ae3db24a DV |
3062 | } |
3063 | ||
d9e86c0e CW |
3064 | if (avail == NULL) |
3065 | return NULL; | |
ae3db24a DV |
3066 | |
3067 | /* None available, try to steal one or wait for a user to finish */ | |
d9e86c0e | 3068 | list_for_each_entry(reg, &dev_priv->mm.fence_list, lru_list) { |
1690e1eb | 3069 | if (reg->pin_count) |
ae3db24a DV |
3070 | continue; |
3071 | ||
8fe301ad | 3072 | return reg; |
ae3db24a DV |
3073 | } |
3074 | ||
8fe301ad | 3075 | return NULL; |
ae3db24a DV |
3076 | } |
3077 | ||
de151cf6 | 3078 | /** |
9a5a53b3 | 3079 | * i915_gem_object_get_fence - set up fencing for an object |
de151cf6 JB |
3080 | * @obj: object to map through a fence reg |
3081 | * | |
3082 | * When mapping objects through the GTT, userspace wants to be able to write | |
3083 | * to them without having to worry about swizzling if the object is tiled. | |
de151cf6 JB |
3084 | * This function walks the fence regs looking for a free one for @obj, |
3085 | * stealing one if it can't find any. | |
3086 | * | |
3087 | * It then sets up the reg based on the object's properties: address, pitch | |
3088 | * and tiling format. | |
9a5a53b3 CW |
3089 | * |
3090 | * For an untiled surface, this removes any existing fence. | |
de151cf6 | 3091 | */ |
8c4b8c3f | 3092 | int |
06d98131 | 3093 | i915_gem_object_get_fence(struct drm_i915_gem_object *obj) |
de151cf6 | 3094 | { |
05394f39 | 3095 | struct drm_device *dev = obj->base.dev; |
79e53945 | 3096 | struct drm_i915_private *dev_priv = dev->dev_private; |
14415745 | 3097 | bool enable = obj->tiling_mode != I915_TILING_NONE; |
d9e86c0e | 3098 | struct drm_i915_fence_reg *reg; |
ae3db24a | 3099 | int ret; |
de151cf6 | 3100 | |
14415745 CW |
3101 | /* Have we updated the tiling parameters upon the object and so |
3102 | * will need to serialise the write to the associated fence register? | |
3103 | */ | |
5d82e3e6 | 3104 | if (obj->fence_dirty) { |
d0a57789 | 3105 | ret = i915_gem_object_wait_fence(obj); |
14415745 CW |
3106 | if (ret) |
3107 | return ret; | |
3108 | } | |
9a5a53b3 | 3109 | |
d9e86c0e | 3110 | /* Just update our place in the LRU if our fence is getting reused. */ |
05394f39 CW |
3111 | if (obj->fence_reg != I915_FENCE_REG_NONE) { |
3112 | reg = &dev_priv->fence_regs[obj->fence_reg]; | |
5d82e3e6 | 3113 | if (!obj->fence_dirty) { |
14415745 CW |
3114 | list_move_tail(®->lru_list, |
3115 | &dev_priv->mm.fence_list); | |
3116 | return 0; | |
3117 | } | |
3118 | } else if (enable) { | |
3119 | reg = i915_find_fence_reg(dev); | |
3120 | if (reg == NULL) | |
3121 | return -EDEADLK; | |
d9e86c0e | 3122 | |
14415745 CW |
3123 | if (reg->obj) { |
3124 | struct drm_i915_gem_object *old = reg->obj; | |
3125 | ||
d0a57789 | 3126 | ret = i915_gem_object_wait_fence(old); |
29c5a587 CW |
3127 | if (ret) |
3128 | return ret; | |
3129 | ||
14415745 | 3130 | i915_gem_object_fence_lost(old); |
29c5a587 | 3131 | } |
14415745 | 3132 | } else |
a09ba7fa | 3133 | return 0; |
a09ba7fa | 3134 | |
14415745 | 3135 | i915_gem_object_update_fence(obj, reg, enable); |
14415745 | 3136 | |
9ce079e4 | 3137 | return 0; |
de151cf6 JB |
3138 | } |
3139 | ||
42d6ab48 CW |
3140 | static bool i915_gem_valid_gtt_space(struct drm_device *dev, |
3141 | struct drm_mm_node *gtt_space, | |
3142 | unsigned long cache_level) | |
3143 | { | |
3144 | struct drm_mm_node *other; | |
3145 | ||
3146 | /* On non-LLC machines we have to be careful when putting differing | |
3147 | * types of snoopable memory together to avoid the prefetcher | |
4239ca77 | 3148 | * crossing memory domains and dying. |
42d6ab48 CW |
3149 | */ |
3150 | if (HAS_LLC(dev)) | |
3151 | return true; | |
3152 | ||
c6cfb325 | 3153 | if (!drm_mm_node_allocated(gtt_space)) |
42d6ab48 CW |
3154 | return true; |
3155 | ||
3156 | if (list_empty(>t_space->node_list)) | |
3157 | return true; | |
3158 | ||
3159 | other = list_entry(gtt_space->node_list.prev, struct drm_mm_node, node_list); | |
3160 | if (other->allocated && !other->hole_follows && other->color != cache_level) | |
3161 | return false; | |
3162 | ||
3163 | other = list_entry(gtt_space->node_list.next, struct drm_mm_node, node_list); | |
3164 | if (other->allocated && !gtt_space->hole_follows && other->color != cache_level) | |
3165 | return false; | |
3166 | ||
3167 | return true; | |
3168 | } | |
3169 | ||
3170 | static void i915_gem_verify_gtt(struct drm_device *dev) | |
3171 | { | |
3172 | #if WATCH_GTT | |
3173 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3174 | struct drm_i915_gem_object *obj; | |
3175 | int err = 0; | |
3176 | ||
35c20a60 | 3177 | list_for_each_entry(obj, &dev_priv->mm.gtt_list, global_list) { |
42d6ab48 CW |
3178 | if (obj->gtt_space == NULL) { |
3179 | printk(KERN_ERR "object found on GTT list with no space reserved\n"); | |
3180 | err++; | |
3181 | continue; | |
3182 | } | |
3183 | ||
3184 | if (obj->cache_level != obj->gtt_space->color) { | |
3185 | printk(KERN_ERR "object reserved space [%08lx, %08lx] with wrong color, cache_level=%x, color=%lx\n", | |
f343c5f6 BW |
3186 | i915_gem_obj_ggtt_offset(obj), |
3187 | i915_gem_obj_ggtt_offset(obj) + i915_gem_obj_ggtt_size(obj), | |
42d6ab48 CW |
3188 | obj->cache_level, |
3189 | obj->gtt_space->color); | |
3190 | err++; | |
3191 | continue; | |
3192 | } | |
3193 | ||
3194 | if (!i915_gem_valid_gtt_space(dev, | |
3195 | obj->gtt_space, | |
3196 | obj->cache_level)) { | |
3197 | printk(KERN_ERR "invalid GTT space found at [%08lx, %08lx] - color=%x\n", | |
f343c5f6 BW |
3198 | i915_gem_obj_ggtt_offset(obj), |
3199 | i915_gem_obj_ggtt_offset(obj) + i915_gem_obj_ggtt_size(obj), | |
42d6ab48 CW |
3200 | obj->cache_level); |
3201 | err++; | |
3202 | continue; | |
3203 | } | |
3204 | } | |
3205 | ||
3206 | WARN_ON(err); | |
3207 | #endif | |
3208 | } | |
3209 | ||
673a394b EA |
3210 | /** |
3211 | * Finds free space in the GTT aperture and binds the object there. | |
3212 | */ | |
3213 | static int | |
07fe0b12 BW |
3214 | i915_gem_object_bind_to_vm(struct drm_i915_gem_object *obj, |
3215 | struct i915_address_space *vm, | |
3216 | unsigned alignment, | |
3217 | bool map_and_fenceable, | |
3218 | bool nonblocking) | |
673a394b | 3219 | { |
05394f39 | 3220 | struct drm_device *dev = obj->base.dev; |
673a394b | 3221 | drm_i915_private_t *dev_priv = dev->dev_private; |
5e783301 | 3222 | u32 size, fence_size, fence_alignment, unfenced_alignment; |
07fe0b12 BW |
3223 | size_t gtt_max = |
3224 | map_and_fenceable ? dev_priv->gtt.mappable_end : vm->total; | |
2f633156 | 3225 | struct i915_vma *vma; |
07f73f69 | 3226 | int ret; |
673a394b | 3227 | |
e28f8711 CW |
3228 | fence_size = i915_gem_get_gtt_size(dev, |
3229 | obj->base.size, | |
3230 | obj->tiling_mode); | |
3231 | fence_alignment = i915_gem_get_gtt_alignment(dev, | |
3232 | obj->base.size, | |
d865110c | 3233 | obj->tiling_mode, true); |
e28f8711 | 3234 | unfenced_alignment = |
d865110c | 3235 | i915_gem_get_gtt_alignment(dev, |
e28f8711 | 3236 | obj->base.size, |
d865110c | 3237 | obj->tiling_mode, false); |
a00b10c3 | 3238 | |
673a394b | 3239 | if (alignment == 0) |
5e783301 DV |
3240 | alignment = map_and_fenceable ? fence_alignment : |
3241 | unfenced_alignment; | |
75e9e915 | 3242 | if (map_and_fenceable && alignment & (fence_alignment - 1)) { |
673a394b EA |
3243 | DRM_ERROR("Invalid object alignment requested %u\n", alignment); |
3244 | return -EINVAL; | |
3245 | } | |
3246 | ||
05394f39 | 3247 | size = map_and_fenceable ? fence_size : obj->base.size; |
a00b10c3 | 3248 | |
654fc607 CW |
3249 | /* If the object is bigger than the entire aperture, reject it early |
3250 | * before evicting everything in a vain attempt to find space. | |
3251 | */ | |
0a9ae0d7 | 3252 | if (obj->base.size > gtt_max) { |
3765f304 | 3253 | DRM_ERROR("Attempting to bind an object larger than the aperture: object=%zd > %s aperture=%zu\n", |
a36689cb CW |
3254 | obj->base.size, |
3255 | map_and_fenceable ? "mappable" : "total", | |
0a9ae0d7 | 3256 | gtt_max); |
654fc607 CW |
3257 | return -E2BIG; |
3258 | } | |
3259 | ||
37e680a1 | 3260 | ret = i915_gem_object_get_pages(obj); |
6c085a72 CW |
3261 | if (ret) |
3262 | return ret; | |
3263 | ||
fbdda6fb CW |
3264 | i915_gem_object_pin_pages(obj); |
3265 | ||
07fe0b12 | 3266 | BUG_ON(!i915_is_ggtt(vm)); |
07fe0b12 | 3267 | |
accfef2e | 3268 | vma = i915_gem_obj_lookup_or_create_vma(obj, vm); |
db473b36 | 3269 | if (IS_ERR(vma)) { |
bc6bc15b DV |
3270 | ret = PTR_ERR(vma); |
3271 | goto err_unpin; | |
2f633156 BW |
3272 | } |
3273 | ||
accfef2e BW |
3274 | /* For now we only ever use 1 vma per object */ |
3275 | WARN_ON(!list_is_singular(&obj->vma_list)); | |
3276 | ||
0a9ae0d7 | 3277 | search_free: |
07fe0b12 | 3278 | ret = drm_mm_insert_node_in_range_generic(&vm->mm, &vma->node, |
0a9ae0d7 | 3279 | size, alignment, |
31e5d7c6 DH |
3280 | obj->cache_level, 0, gtt_max, |
3281 | DRM_MM_SEARCH_DEFAULT); | |
dc9dd7a2 | 3282 | if (ret) { |
f6cd1f15 | 3283 | ret = i915_gem_evict_something(dev, vm, size, alignment, |
42d6ab48 | 3284 | obj->cache_level, |
86a1ee26 CW |
3285 | map_and_fenceable, |
3286 | nonblocking); | |
dc9dd7a2 CW |
3287 | if (ret == 0) |
3288 | goto search_free; | |
9731129c | 3289 | |
bc6bc15b | 3290 | goto err_free_vma; |
673a394b | 3291 | } |
2f633156 | 3292 | if (WARN_ON(!i915_gem_valid_gtt_space(dev, &vma->node, |
c6cfb325 | 3293 | obj->cache_level))) { |
2f633156 | 3294 | ret = -EINVAL; |
bc6bc15b | 3295 | goto err_remove_node; |
673a394b EA |
3296 | } |
3297 | ||
74163907 | 3298 | ret = i915_gem_gtt_prepare_object(obj); |
2f633156 | 3299 | if (ret) |
bc6bc15b | 3300 | goto err_remove_node; |
673a394b | 3301 | |
35c20a60 | 3302 | list_move_tail(&obj->global_list, &dev_priv->mm.bound_list); |
ca191b13 | 3303 | list_add_tail(&vma->mm_list, &vm->inactive_list); |
bf1a1092 | 3304 | |
4bd561b3 BW |
3305 | if (i915_is_ggtt(vm)) { |
3306 | bool mappable, fenceable; | |
a00b10c3 | 3307 | |
49987099 DV |
3308 | fenceable = (vma->node.size == fence_size && |
3309 | (vma->node.start & (fence_alignment - 1)) == 0); | |
4bd561b3 | 3310 | |
49987099 DV |
3311 | mappable = (vma->node.start + obj->base.size <= |
3312 | dev_priv->gtt.mappable_end); | |
a00b10c3 | 3313 | |
5cacaac7 | 3314 | obj->map_and_fenceable = mappable && fenceable; |
4bd561b3 | 3315 | } |
75e9e915 | 3316 | |
7ace7ef2 | 3317 | WARN_ON(map_and_fenceable && !obj->map_and_fenceable); |
75e9e915 | 3318 | |
07fe0b12 | 3319 | trace_i915_vma_bind(vma, map_and_fenceable); |
42d6ab48 | 3320 | i915_gem_verify_gtt(dev); |
673a394b | 3321 | return 0; |
2f633156 | 3322 | |
bc6bc15b | 3323 | err_remove_node: |
6286ef9b | 3324 | drm_mm_remove_node(&vma->node); |
bc6bc15b | 3325 | err_free_vma: |
2f633156 | 3326 | i915_gem_vma_destroy(vma); |
bc6bc15b | 3327 | err_unpin: |
2f633156 | 3328 | i915_gem_object_unpin_pages(obj); |
2f633156 | 3329 | return ret; |
673a394b EA |
3330 | } |
3331 | ||
000433b6 | 3332 | bool |
2c22569b CW |
3333 | i915_gem_clflush_object(struct drm_i915_gem_object *obj, |
3334 | bool force) | |
673a394b | 3335 | { |
673a394b EA |
3336 | /* If we don't have a page list set up, then we're not pinned |
3337 | * to GPU, and we can ignore the cache flush because it'll happen | |
3338 | * again at bind time. | |
3339 | */ | |
05394f39 | 3340 | if (obj->pages == NULL) |
000433b6 | 3341 | return false; |
673a394b | 3342 | |
769ce464 ID |
3343 | /* |
3344 | * Stolen memory is always coherent with the GPU as it is explicitly | |
3345 | * marked as wc by the system, or the system is cache-coherent. | |
3346 | */ | |
3347 | if (obj->stolen) | |
000433b6 | 3348 | return false; |
769ce464 | 3349 | |
9c23f7fc CW |
3350 | /* If the GPU is snooping the contents of the CPU cache, |
3351 | * we do not need to manually clear the CPU cache lines. However, | |
3352 | * the caches are only snooped when the render cache is | |
3353 | * flushed/invalidated. As we always have to emit invalidations | |
3354 | * and flushes when moving into and out of the RENDER domain, correct | |
3355 | * snooping behaviour occurs naturally as the result of our domain | |
3356 | * tracking. | |
3357 | */ | |
2c22569b | 3358 | if (!force && cpu_cache_is_coherent(obj->base.dev, obj->cache_level)) |
000433b6 | 3359 | return false; |
9c23f7fc | 3360 | |
1c5d22f7 | 3361 | trace_i915_gem_object_clflush(obj); |
9da3da66 | 3362 | drm_clflush_sg(obj->pages); |
000433b6 CW |
3363 | |
3364 | return true; | |
e47c68e9 EA |
3365 | } |
3366 | ||
3367 | /** Flushes the GTT write domain for the object if it's dirty. */ | |
3368 | static void | |
05394f39 | 3369 | i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj) |
e47c68e9 | 3370 | { |
1c5d22f7 CW |
3371 | uint32_t old_write_domain; |
3372 | ||
05394f39 | 3373 | if (obj->base.write_domain != I915_GEM_DOMAIN_GTT) |
e47c68e9 EA |
3374 | return; |
3375 | ||
63256ec5 | 3376 | /* No actual flushing is required for the GTT write domain. Writes |
e47c68e9 EA |
3377 | * to it immediately go to main memory as far as we know, so there's |
3378 | * no chipset flush. It also doesn't land in render cache. | |
63256ec5 CW |
3379 | * |
3380 | * However, we do have to enforce the order so that all writes through | |
3381 | * the GTT land before any writes to the device, such as updates to | |
3382 | * the GATT itself. | |
e47c68e9 | 3383 | */ |
63256ec5 CW |
3384 | wmb(); |
3385 | ||
05394f39 CW |
3386 | old_write_domain = obj->base.write_domain; |
3387 | obj->base.write_domain = 0; | |
1c5d22f7 CW |
3388 | |
3389 | trace_i915_gem_object_change_domain(obj, | |
05394f39 | 3390 | obj->base.read_domains, |
1c5d22f7 | 3391 | old_write_domain); |
e47c68e9 EA |
3392 | } |
3393 | ||
3394 | /** Flushes the CPU write domain for the object if it's dirty. */ | |
3395 | static void | |
2c22569b CW |
3396 | i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj, |
3397 | bool force) | |
e47c68e9 | 3398 | { |
1c5d22f7 | 3399 | uint32_t old_write_domain; |
e47c68e9 | 3400 | |
05394f39 | 3401 | if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) |
e47c68e9 EA |
3402 | return; |
3403 | ||
000433b6 CW |
3404 | if (i915_gem_clflush_object(obj, force)) |
3405 | i915_gem_chipset_flush(obj->base.dev); | |
3406 | ||
05394f39 CW |
3407 | old_write_domain = obj->base.write_domain; |
3408 | obj->base.write_domain = 0; | |
1c5d22f7 CW |
3409 | |
3410 | trace_i915_gem_object_change_domain(obj, | |
05394f39 | 3411 | obj->base.read_domains, |
1c5d22f7 | 3412 | old_write_domain); |
e47c68e9 EA |
3413 | } |
3414 | ||
2ef7eeaa EA |
3415 | /** |
3416 | * Moves a single object to the GTT read, and possibly write domain. | |
3417 | * | |
3418 | * This function returns when the move is complete, including waiting on | |
3419 | * flushes to occur. | |
3420 | */ | |
79e53945 | 3421 | int |
2021746e | 3422 | i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write) |
2ef7eeaa | 3423 | { |
8325a09d | 3424 | drm_i915_private_t *dev_priv = obj->base.dev->dev_private; |
1c5d22f7 | 3425 | uint32_t old_write_domain, old_read_domains; |
e47c68e9 | 3426 | int ret; |
2ef7eeaa | 3427 | |
02354392 | 3428 | /* Not valid to be called on unbound objects. */ |
9843877d | 3429 | if (!i915_gem_obj_bound_any(obj)) |
02354392 EA |
3430 | return -EINVAL; |
3431 | ||
8d7e3de1 CW |
3432 | if (obj->base.write_domain == I915_GEM_DOMAIN_GTT) |
3433 | return 0; | |
3434 | ||
0201f1ec | 3435 | ret = i915_gem_object_wait_rendering(obj, !write); |
88241785 CW |
3436 | if (ret) |
3437 | return ret; | |
3438 | ||
2c22569b | 3439 | i915_gem_object_flush_cpu_write_domain(obj, false); |
1c5d22f7 | 3440 | |
d0a57789 CW |
3441 | /* Serialise direct access to this object with the barriers for |
3442 | * coherent writes from the GPU, by effectively invalidating the | |
3443 | * GTT domain upon first access. | |
3444 | */ | |
3445 | if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0) | |
3446 | mb(); | |
3447 | ||
05394f39 CW |
3448 | old_write_domain = obj->base.write_domain; |
3449 | old_read_domains = obj->base.read_domains; | |
1c5d22f7 | 3450 | |
e47c68e9 EA |
3451 | /* It should now be out of any other write domains, and we can update |
3452 | * the domain values for our changes. | |
3453 | */ | |
05394f39 CW |
3454 | BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) != 0); |
3455 | obj->base.read_domains |= I915_GEM_DOMAIN_GTT; | |
e47c68e9 | 3456 | if (write) { |
05394f39 CW |
3457 | obj->base.read_domains = I915_GEM_DOMAIN_GTT; |
3458 | obj->base.write_domain = I915_GEM_DOMAIN_GTT; | |
3459 | obj->dirty = 1; | |
2ef7eeaa EA |
3460 | } |
3461 | ||
1c5d22f7 CW |
3462 | trace_i915_gem_object_change_domain(obj, |
3463 | old_read_domains, | |
3464 | old_write_domain); | |
3465 | ||
8325a09d | 3466 | /* And bump the LRU for this access */ |
ca191b13 | 3467 | if (i915_gem_object_is_inactive(obj)) { |
5c2abbea | 3468 | struct i915_vma *vma = i915_gem_obj_to_ggtt(obj); |
ca191b13 BW |
3469 | if (vma) |
3470 | list_move_tail(&vma->mm_list, | |
3471 | &dev_priv->gtt.base.inactive_list); | |
3472 | ||
3473 | } | |
8325a09d | 3474 | |
e47c68e9 EA |
3475 | return 0; |
3476 | } | |
3477 | ||
e4ffd173 CW |
3478 | int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj, |
3479 | enum i915_cache_level cache_level) | |
3480 | { | |
7bddb01f DV |
3481 | struct drm_device *dev = obj->base.dev; |
3482 | drm_i915_private_t *dev_priv = dev->dev_private; | |
3089c6f2 | 3483 | struct i915_vma *vma; |
e4ffd173 CW |
3484 | int ret; |
3485 | ||
3486 | if (obj->cache_level == cache_level) | |
3487 | return 0; | |
3488 | ||
d7f46fc4 | 3489 | if (i915_gem_obj_is_pinned(obj)) { |
e4ffd173 CW |
3490 | DRM_DEBUG("can not change the cache level of pinned objects\n"); |
3491 | return -EBUSY; | |
3492 | } | |
3493 | ||
3089c6f2 BW |
3494 | list_for_each_entry(vma, &obj->vma_list, vma_link) { |
3495 | if (!i915_gem_valid_gtt_space(dev, &vma->node, cache_level)) { | |
07fe0b12 | 3496 | ret = i915_vma_unbind(vma); |
3089c6f2 BW |
3497 | if (ret) |
3498 | return ret; | |
3499 | ||
3500 | break; | |
3501 | } | |
42d6ab48 CW |
3502 | } |
3503 | ||
3089c6f2 | 3504 | if (i915_gem_obj_bound_any(obj)) { |
e4ffd173 CW |
3505 | ret = i915_gem_object_finish_gpu(obj); |
3506 | if (ret) | |
3507 | return ret; | |
3508 | ||
3509 | i915_gem_object_finish_gtt(obj); | |
3510 | ||
3511 | /* Before SandyBridge, you could not use tiling or fence | |
3512 | * registers with snooped memory, so relinquish any fences | |
3513 | * currently pointing to our region in the aperture. | |
3514 | */ | |
42d6ab48 | 3515 | if (INTEL_INFO(dev)->gen < 6) { |
e4ffd173 CW |
3516 | ret = i915_gem_object_put_fence(obj); |
3517 | if (ret) | |
3518 | return ret; | |
3519 | } | |
3520 | ||
74898d7e DV |
3521 | if (obj->has_global_gtt_mapping) |
3522 | i915_gem_gtt_bind_object(obj, cache_level); | |
7bddb01f DV |
3523 | if (obj->has_aliasing_ppgtt_mapping) |
3524 | i915_ppgtt_bind_object(dev_priv->mm.aliasing_ppgtt, | |
3525 | obj, cache_level); | |
e4ffd173 CW |
3526 | } |
3527 | ||
2c22569b CW |
3528 | list_for_each_entry(vma, &obj->vma_list, vma_link) |
3529 | vma->node.color = cache_level; | |
3530 | obj->cache_level = cache_level; | |
3531 | ||
3532 | if (cpu_write_needs_clflush(obj)) { | |
e4ffd173 CW |
3533 | u32 old_read_domains, old_write_domain; |
3534 | ||
3535 | /* If we're coming from LLC cached, then we haven't | |
3536 | * actually been tracking whether the data is in the | |
3537 | * CPU cache or not, since we only allow one bit set | |
3538 | * in obj->write_domain and have been skipping the clflushes. | |
3539 | * Just set it to the CPU cache for now. | |
3540 | */ | |
3541 | WARN_ON(obj->base.write_domain & ~I915_GEM_DOMAIN_CPU); | |
e4ffd173 CW |
3542 | |
3543 | old_read_domains = obj->base.read_domains; | |
3544 | old_write_domain = obj->base.write_domain; | |
3545 | ||
3546 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; | |
3547 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; | |
3548 | ||
3549 | trace_i915_gem_object_change_domain(obj, | |
3550 | old_read_domains, | |
3551 | old_write_domain); | |
3552 | } | |
3553 | ||
42d6ab48 | 3554 | i915_gem_verify_gtt(dev); |
e4ffd173 CW |
3555 | return 0; |
3556 | } | |
3557 | ||
199adf40 BW |
3558 | int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data, |
3559 | struct drm_file *file) | |
e6994aee | 3560 | { |
199adf40 | 3561 | struct drm_i915_gem_caching *args = data; |
e6994aee CW |
3562 | struct drm_i915_gem_object *obj; |
3563 | int ret; | |
3564 | ||
3565 | ret = i915_mutex_lock_interruptible(dev); | |
3566 | if (ret) | |
3567 | return ret; | |
3568 | ||
3569 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); | |
3570 | if (&obj->base == NULL) { | |
3571 | ret = -ENOENT; | |
3572 | goto unlock; | |
3573 | } | |
3574 | ||
651d794f CW |
3575 | switch (obj->cache_level) { |
3576 | case I915_CACHE_LLC: | |
3577 | case I915_CACHE_L3_LLC: | |
3578 | args->caching = I915_CACHING_CACHED; | |
3579 | break; | |
3580 | ||
4257d3ba CW |
3581 | case I915_CACHE_WT: |
3582 | args->caching = I915_CACHING_DISPLAY; | |
3583 | break; | |
3584 | ||
651d794f CW |
3585 | default: |
3586 | args->caching = I915_CACHING_NONE; | |
3587 | break; | |
3588 | } | |
e6994aee CW |
3589 | |
3590 | drm_gem_object_unreference(&obj->base); | |
3591 | unlock: | |
3592 | mutex_unlock(&dev->struct_mutex); | |
3593 | return ret; | |
3594 | } | |
3595 | ||
199adf40 BW |
3596 | int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data, |
3597 | struct drm_file *file) | |
e6994aee | 3598 | { |
199adf40 | 3599 | struct drm_i915_gem_caching *args = data; |
e6994aee CW |
3600 | struct drm_i915_gem_object *obj; |
3601 | enum i915_cache_level level; | |
3602 | int ret; | |
3603 | ||
199adf40 BW |
3604 | switch (args->caching) { |
3605 | case I915_CACHING_NONE: | |
e6994aee CW |
3606 | level = I915_CACHE_NONE; |
3607 | break; | |
199adf40 | 3608 | case I915_CACHING_CACHED: |
e6994aee CW |
3609 | level = I915_CACHE_LLC; |
3610 | break; | |
4257d3ba CW |
3611 | case I915_CACHING_DISPLAY: |
3612 | level = HAS_WT(dev) ? I915_CACHE_WT : I915_CACHE_NONE; | |
3613 | break; | |
e6994aee CW |
3614 | default: |
3615 | return -EINVAL; | |
3616 | } | |
3617 | ||
3bc2913e BW |
3618 | ret = i915_mutex_lock_interruptible(dev); |
3619 | if (ret) | |
3620 | return ret; | |
3621 | ||
e6994aee CW |
3622 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
3623 | if (&obj->base == NULL) { | |
3624 | ret = -ENOENT; | |
3625 | goto unlock; | |
3626 | } | |
3627 | ||
3628 | ret = i915_gem_object_set_cache_level(obj, level); | |
3629 | ||
3630 | drm_gem_object_unreference(&obj->base); | |
3631 | unlock: | |
3632 | mutex_unlock(&dev->struct_mutex); | |
3633 | return ret; | |
3634 | } | |
3635 | ||
cc98b413 CW |
3636 | static bool is_pin_display(struct drm_i915_gem_object *obj) |
3637 | { | |
3638 | /* There are 3 sources that pin objects: | |
3639 | * 1. The display engine (scanouts, sprites, cursors); | |
3640 | * 2. Reservations for execbuffer; | |
3641 | * 3. The user. | |
3642 | * | |
3643 | * We can ignore reservations as we hold the struct_mutex and | |
3644 | * are only called outside of the reservation path. The user | |
3645 | * can only increment pin_count once, and so if after | |
3646 | * subtracting the potential reference by the user, any pin_count | |
3647 | * remains, it must be due to another use by the display engine. | |
3648 | */ | |
d7f46fc4 | 3649 | return i915_gem_obj_to_ggtt(obj)->pin_count - !!obj->user_pin_count; |
cc98b413 CW |
3650 | } |
3651 | ||
b9241ea3 | 3652 | /* |
2da3b9b9 CW |
3653 | * Prepare buffer for display plane (scanout, cursors, etc). |
3654 | * Can be called from an uninterruptible phase (modesetting) and allows | |
3655 | * any flushes to be pipelined (for pageflips). | |
b9241ea3 ZW |
3656 | */ |
3657 | int | |
2da3b9b9 CW |
3658 | i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj, |
3659 | u32 alignment, | |
919926ae | 3660 | struct intel_ring_buffer *pipelined) |
b9241ea3 | 3661 | { |
2da3b9b9 | 3662 | u32 old_read_domains, old_write_domain; |
b9241ea3 ZW |
3663 | int ret; |
3664 | ||
0be73284 | 3665 | if (pipelined != obj->ring) { |
2911a35b BW |
3666 | ret = i915_gem_object_sync(obj, pipelined); |
3667 | if (ret) | |
b9241ea3 ZW |
3668 | return ret; |
3669 | } | |
3670 | ||
cc98b413 CW |
3671 | /* Mark the pin_display early so that we account for the |
3672 | * display coherency whilst setting up the cache domains. | |
3673 | */ | |
3674 | obj->pin_display = true; | |
3675 | ||
a7ef0640 EA |
3676 | /* The display engine is not coherent with the LLC cache on gen6. As |
3677 | * a result, we make sure that the pinning that is about to occur is | |
3678 | * done with uncached PTEs. This is lowest common denominator for all | |
3679 | * chipsets. | |
3680 | * | |
3681 | * However for gen6+, we could do better by using the GFDT bit instead | |
3682 | * of uncaching, which would allow us to flush all the LLC-cached data | |
3683 | * with that bit in the PTE to main memory with just one PIPE_CONTROL. | |
3684 | */ | |
651d794f CW |
3685 | ret = i915_gem_object_set_cache_level(obj, |
3686 | HAS_WT(obj->base.dev) ? I915_CACHE_WT : I915_CACHE_NONE); | |
a7ef0640 | 3687 | if (ret) |
cc98b413 | 3688 | goto err_unpin_display; |
a7ef0640 | 3689 | |
2da3b9b9 CW |
3690 | /* As the user may map the buffer once pinned in the display plane |
3691 | * (e.g. libkms for the bootup splash), we have to ensure that we | |
3692 | * always use map_and_fenceable for all scanout buffers. | |
3693 | */ | |
c37e2204 | 3694 | ret = i915_gem_obj_ggtt_pin(obj, alignment, true, false); |
2da3b9b9 | 3695 | if (ret) |
cc98b413 | 3696 | goto err_unpin_display; |
2da3b9b9 | 3697 | |
2c22569b | 3698 | i915_gem_object_flush_cpu_write_domain(obj, true); |
b118c1e3 | 3699 | |
2da3b9b9 | 3700 | old_write_domain = obj->base.write_domain; |
05394f39 | 3701 | old_read_domains = obj->base.read_domains; |
2da3b9b9 CW |
3702 | |
3703 | /* It should now be out of any other write domains, and we can update | |
3704 | * the domain values for our changes. | |
3705 | */ | |
e5f1d962 | 3706 | obj->base.write_domain = 0; |
05394f39 | 3707 | obj->base.read_domains |= I915_GEM_DOMAIN_GTT; |
b9241ea3 ZW |
3708 | |
3709 | trace_i915_gem_object_change_domain(obj, | |
3710 | old_read_domains, | |
2da3b9b9 | 3711 | old_write_domain); |
b9241ea3 ZW |
3712 | |
3713 | return 0; | |
cc98b413 CW |
3714 | |
3715 | err_unpin_display: | |
3716 | obj->pin_display = is_pin_display(obj); | |
3717 | return ret; | |
3718 | } | |
3719 | ||
3720 | void | |
3721 | i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object *obj) | |
3722 | { | |
d7f46fc4 | 3723 | i915_gem_object_ggtt_unpin(obj); |
cc98b413 | 3724 | obj->pin_display = is_pin_display(obj); |
b9241ea3 ZW |
3725 | } |
3726 | ||
85345517 | 3727 | int |
a8198eea | 3728 | i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj) |
85345517 | 3729 | { |
88241785 CW |
3730 | int ret; |
3731 | ||
a8198eea | 3732 | if ((obj->base.read_domains & I915_GEM_GPU_DOMAINS) == 0) |
85345517 CW |
3733 | return 0; |
3734 | ||
0201f1ec | 3735 | ret = i915_gem_object_wait_rendering(obj, false); |
c501ae7f CW |
3736 | if (ret) |
3737 | return ret; | |
3738 | ||
a8198eea CW |
3739 | /* Ensure that we invalidate the GPU's caches and TLBs. */ |
3740 | obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS; | |
c501ae7f | 3741 | return 0; |
85345517 CW |
3742 | } |
3743 | ||
e47c68e9 EA |
3744 | /** |
3745 | * Moves a single object to the CPU read, and possibly write domain. | |
3746 | * | |
3747 | * This function returns when the move is complete, including waiting on | |
3748 | * flushes to occur. | |
3749 | */ | |
dabdfe02 | 3750 | int |
919926ae | 3751 | i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write) |
e47c68e9 | 3752 | { |
1c5d22f7 | 3753 | uint32_t old_write_domain, old_read_domains; |
e47c68e9 EA |
3754 | int ret; |
3755 | ||
8d7e3de1 CW |
3756 | if (obj->base.write_domain == I915_GEM_DOMAIN_CPU) |
3757 | return 0; | |
3758 | ||
0201f1ec | 3759 | ret = i915_gem_object_wait_rendering(obj, !write); |
88241785 CW |
3760 | if (ret) |
3761 | return ret; | |
3762 | ||
e47c68e9 | 3763 | i915_gem_object_flush_gtt_write_domain(obj); |
2ef7eeaa | 3764 | |
05394f39 CW |
3765 | old_write_domain = obj->base.write_domain; |
3766 | old_read_domains = obj->base.read_domains; | |
1c5d22f7 | 3767 | |
e47c68e9 | 3768 | /* Flush the CPU cache if it's still invalid. */ |
05394f39 | 3769 | if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) { |
2c22569b | 3770 | i915_gem_clflush_object(obj, false); |
2ef7eeaa | 3771 | |
05394f39 | 3772 | obj->base.read_domains |= I915_GEM_DOMAIN_CPU; |
2ef7eeaa EA |
3773 | } |
3774 | ||
3775 | /* It should now be out of any other write domains, and we can update | |
3776 | * the domain values for our changes. | |
3777 | */ | |
05394f39 | 3778 | BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) != 0); |
e47c68e9 EA |
3779 | |
3780 | /* If we're writing through the CPU, then the GPU read domains will | |
3781 | * need to be invalidated at next use. | |
3782 | */ | |
3783 | if (write) { | |
05394f39 CW |
3784 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; |
3785 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; | |
e47c68e9 | 3786 | } |
2ef7eeaa | 3787 | |
1c5d22f7 CW |
3788 | trace_i915_gem_object_change_domain(obj, |
3789 | old_read_domains, | |
3790 | old_write_domain); | |
3791 | ||
2ef7eeaa EA |
3792 | return 0; |
3793 | } | |
3794 | ||
673a394b EA |
3795 | /* Throttle our rendering by waiting until the ring has completed our requests |
3796 | * emitted over 20 msec ago. | |
3797 | * | |
b962442e EA |
3798 | * Note that if we were to use the current jiffies each time around the loop, |
3799 | * we wouldn't escape the function with any frames outstanding if the time to | |
3800 | * render a frame was over 20ms. | |
3801 | * | |
673a394b EA |
3802 | * This should get us reasonable parallelism between CPU and GPU but also |
3803 | * relatively low latency when blocking on a particular request to finish. | |
3804 | */ | |
40a5f0de | 3805 | static int |
f787a5f5 | 3806 | i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file) |
40a5f0de | 3807 | { |
f787a5f5 CW |
3808 | struct drm_i915_private *dev_priv = dev->dev_private; |
3809 | struct drm_i915_file_private *file_priv = file->driver_priv; | |
b962442e | 3810 | unsigned long recent_enough = jiffies - msecs_to_jiffies(20); |
f787a5f5 CW |
3811 | struct drm_i915_gem_request *request; |
3812 | struct intel_ring_buffer *ring = NULL; | |
f69061be | 3813 | unsigned reset_counter; |
f787a5f5 CW |
3814 | u32 seqno = 0; |
3815 | int ret; | |
93533c29 | 3816 | |
308887aa DV |
3817 | ret = i915_gem_wait_for_error(&dev_priv->gpu_error); |
3818 | if (ret) | |
3819 | return ret; | |
3820 | ||
3821 | ret = i915_gem_check_wedge(&dev_priv->gpu_error, false); | |
3822 | if (ret) | |
3823 | return ret; | |
e110e8d6 | 3824 | |
1c25595f | 3825 | spin_lock(&file_priv->mm.lock); |
f787a5f5 | 3826 | list_for_each_entry(request, &file_priv->mm.request_list, client_list) { |
b962442e EA |
3827 | if (time_after_eq(request->emitted_jiffies, recent_enough)) |
3828 | break; | |
40a5f0de | 3829 | |
f787a5f5 CW |
3830 | ring = request->ring; |
3831 | seqno = request->seqno; | |
b962442e | 3832 | } |
f69061be | 3833 | reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter); |
1c25595f | 3834 | spin_unlock(&file_priv->mm.lock); |
40a5f0de | 3835 | |
f787a5f5 CW |
3836 | if (seqno == 0) |
3837 | return 0; | |
2bc43b5c | 3838 | |
b29c19b6 | 3839 | ret = __wait_seqno(ring, seqno, reset_counter, true, NULL, NULL); |
f787a5f5 CW |
3840 | if (ret == 0) |
3841 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, 0); | |
40a5f0de EA |
3842 | |
3843 | return ret; | |
3844 | } | |
3845 | ||
673a394b | 3846 | int |
05394f39 | 3847 | i915_gem_object_pin(struct drm_i915_gem_object *obj, |
c37e2204 | 3848 | struct i915_address_space *vm, |
05394f39 | 3849 | uint32_t alignment, |
86a1ee26 CW |
3850 | bool map_and_fenceable, |
3851 | bool nonblocking) | |
673a394b | 3852 | { |
07fe0b12 | 3853 | struct i915_vma *vma; |
673a394b EA |
3854 | int ret; |
3855 | ||
07fe0b12 BW |
3856 | WARN_ON(map_and_fenceable && !i915_is_ggtt(vm)); |
3857 | ||
3858 | vma = i915_gem_obj_to_vma(obj, vm); | |
3859 | ||
3860 | if (vma) { | |
d7f46fc4 BW |
3861 | if (WARN_ON(vma->pin_count == DRM_I915_GEM_OBJECT_MAX_PIN_COUNT)) |
3862 | return -EBUSY; | |
3863 | ||
07fe0b12 BW |
3864 | if ((alignment && |
3865 | vma->node.start & (alignment - 1)) || | |
05394f39 | 3866 | (map_and_fenceable && !obj->map_and_fenceable)) { |
d7f46fc4 | 3867 | WARN(vma->pin_count, |
ae7d49d8 | 3868 | "bo is already pinned with incorrect alignment:" |
f343c5f6 | 3869 | " offset=%lx, req.alignment=%x, req.map_and_fenceable=%d," |
75e9e915 | 3870 | " obj->map_and_fenceable=%d\n", |
07fe0b12 | 3871 | i915_gem_obj_offset(obj, vm), alignment, |
75e9e915 | 3872 | map_and_fenceable, |
05394f39 | 3873 | obj->map_and_fenceable); |
07fe0b12 | 3874 | ret = i915_vma_unbind(vma); |
ac0c6b5a CW |
3875 | if (ret) |
3876 | return ret; | |
3877 | } | |
3878 | } | |
3879 | ||
07fe0b12 | 3880 | if (!i915_gem_obj_bound(obj, vm)) { |
8742267a CW |
3881 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
3882 | ||
07fe0b12 BW |
3883 | ret = i915_gem_object_bind_to_vm(obj, vm, alignment, |
3884 | map_and_fenceable, | |
3885 | nonblocking); | |
9731129c | 3886 | if (ret) |
673a394b | 3887 | return ret; |
8742267a CW |
3888 | |
3889 | if (!dev_priv->mm.aliasing_ppgtt) | |
3890 | i915_gem_gtt_bind_object(obj, obj->cache_level); | |
22c344e9 | 3891 | } |
76446cac | 3892 | |
74898d7e DV |
3893 | if (!obj->has_global_gtt_mapping && map_and_fenceable) |
3894 | i915_gem_gtt_bind_object(obj, obj->cache_level); | |
3895 | ||
d7f46fc4 | 3896 | i915_gem_obj_to_vma(obj, vm)->pin_count++; |
6299f992 | 3897 | obj->pin_mappable |= map_and_fenceable; |
673a394b EA |
3898 | |
3899 | return 0; | |
3900 | } | |
3901 | ||
3902 | void | |
d7f46fc4 | 3903 | i915_gem_object_ggtt_unpin(struct drm_i915_gem_object *obj) |
673a394b | 3904 | { |
d7f46fc4 | 3905 | struct i915_vma *vma = i915_gem_obj_to_ggtt(obj); |
673a394b | 3906 | |
d7f46fc4 BW |
3907 | BUG_ON(!vma); |
3908 | BUG_ON(vma->pin_count == 0); | |
3909 | BUG_ON(!i915_gem_obj_ggtt_bound(obj)); | |
3910 | ||
3911 | if (--vma->pin_count == 0) | |
6299f992 | 3912 | obj->pin_mappable = false; |
673a394b EA |
3913 | } |
3914 | ||
3915 | int | |
3916 | i915_gem_pin_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 3917 | struct drm_file *file) |
673a394b EA |
3918 | { |
3919 | struct drm_i915_gem_pin *args = data; | |
05394f39 | 3920 | struct drm_i915_gem_object *obj; |
673a394b EA |
3921 | int ret; |
3922 | ||
1d7cfea1 CW |
3923 | ret = i915_mutex_lock_interruptible(dev); |
3924 | if (ret) | |
3925 | return ret; | |
673a394b | 3926 | |
05394f39 | 3927 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 3928 | if (&obj->base == NULL) { |
1d7cfea1 CW |
3929 | ret = -ENOENT; |
3930 | goto unlock; | |
673a394b | 3931 | } |
673a394b | 3932 | |
05394f39 | 3933 | if (obj->madv != I915_MADV_WILLNEED) { |
bb6baf76 | 3934 | DRM_ERROR("Attempting to pin a purgeable buffer\n"); |
1d7cfea1 CW |
3935 | ret = -EINVAL; |
3936 | goto out; | |
3ef94daa CW |
3937 | } |
3938 | ||
05394f39 | 3939 | if (obj->pin_filp != NULL && obj->pin_filp != file) { |
79e53945 JB |
3940 | DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n", |
3941 | args->handle); | |
1d7cfea1 CW |
3942 | ret = -EINVAL; |
3943 | goto out; | |
79e53945 JB |
3944 | } |
3945 | ||
aa5f8021 DV |
3946 | if (obj->user_pin_count == ULONG_MAX) { |
3947 | ret = -EBUSY; | |
3948 | goto out; | |
3949 | } | |
3950 | ||
93be8788 | 3951 | if (obj->user_pin_count == 0) { |
c37e2204 | 3952 | ret = i915_gem_obj_ggtt_pin(obj, args->alignment, true, false); |
1d7cfea1 CW |
3953 | if (ret) |
3954 | goto out; | |
673a394b EA |
3955 | } |
3956 | ||
93be8788 CW |
3957 | obj->user_pin_count++; |
3958 | obj->pin_filp = file; | |
3959 | ||
f343c5f6 | 3960 | args->offset = i915_gem_obj_ggtt_offset(obj); |
1d7cfea1 | 3961 | out: |
05394f39 | 3962 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 3963 | unlock: |
673a394b | 3964 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 3965 | return ret; |
673a394b EA |
3966 | } |
3967 | ||
3968 | int | |
3969 | i915_gem_unpin_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 3970 | struct drm_file *file) |
673a394b EA |
3971 | { |
3972 | struct drm_i915_gem_pin *args = data; | |
05394f39 | 3973 | struct drm_i915_gem_object *obj; |
76c1dec1 | 3974 | int ret; |
673a394b | 3975 | |
1d7cfea1 CW |
3976 | ret = i915_mutex_lock_interruptible(dev); |
3977 | if (ret) | |
3978 | return ret; | |
673a394b | 3979 | |
05394f39 | 3980 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 3981 | if (&obj->base == NULL) { |
1d7cfea1 CW |
3982 | ret = -ENOENT; |
3983 | goto unlock; | |
673a394b | 3984 | } |
76c1dec1 | 3985 | |
05394f39 | 3986 | if (obj->pin_filp != file) { |
79e53945 JB |
3987 | DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n", |
3988 | args->handle); | |
1d7cfea1 CW |
3989 | ret = -EINVAL; |
3990 | goto out; | |
79e53945 | 3991 | } |
05394f39 CW |
3992 | obj->user_pin_count--; |
3993 | if (obj->user_pin_count == 0) { | |
3994 | obj->pin_filp = NULL; | |
d7f46fc4 | 3995 | i915_gem_object_ggtt_unpin(obj); |
79e53945 | 3996 | } |
673a394b | 3997 | |
1d7cfea1 | 3998 | out: |
05394f39 | 3999 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 4000 | unlock: |
673a394b | 4001 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 4002 | return ret; |
673a394b EA |
4003 | } |
4004 | ||
4005 | int | |
4006 | i915_gem_busy_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 4007 | struct drm_file *file) |
673a394b EA |
4008 | { |
4009 | struct drm_i915_gem_busy *args = data; | |
05394f39 | 4010 | struct drm_i915_gem_object *obj; |
30dbf0c0 CW |
4011 | int ret; |
4012 | ||
76c1dec1 | 4013 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 4014 | if (ret) |
76c1dec1 | 4015 | return ret; |
673a394b | 4016 | |
05394f39 | 4017 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 4018 | if (&obj->base == NULL) { |
1d7cfea1 CW |
4019 | ret = -ENOENT; |
4020 | goto unlock; | |
673a394b | 4021 | } |
d1b851fc | 4022 | |
0be555b6 CW |
4023 | /* Count all active objects as busy, even if they are currently not used |
4024 | * by the gpu. Users of this interface expect objects to eventually | |
4025 | * become non-busy without any further actions, therefore emit any | |
4026 | * necessary flushes here. | |
c4de0a5d | 4027 | */ |
30dfebf3 | 4028 | ret = i915_gem_object_flush_active(obj); |
0be555b6 | 4029 | |
30dfebf3 | 4030 | args->busy = obj->active; |
e9808edd CW |
4031 | if (obj->ring) { |
4032 | BUILD_BUG_ON(I915_NUM_RINGS > 16); | |
4033 | args->busy |= intel_ring_flag(obj->ring) << 16; | |
4034 | } | |
673a394b | 4035 | |
05394f39 | 4036 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 4037 | unlock: |
673a394b | 4038 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 4039 | return ret; |
673a394b EA |
4040 | } |
4041 | ||
4042 | int | |
4043 | i915_gem_throttle_ioctl(struct drm_device *dev, void *data, | |
4044 | struct drm_file *file_priv) | |
4045 | { | |
0206e353 | 4046 | return i915_gem_ring_throttle(dev, file_priv); |
673a394b EA |
4047 | } |
4048 | ||
3ef94daa CW |
4049 | int |
4050 | i915_gem_madvise_ioctl(struct drm_device *dev, void *data, | |
4051 | struct drm_file *file_priv) | |
4052 | { | |
4053 | struct drm_i915_gem_madvise *args = data; | |
05394f39 | 4054 | struct drm_i915_gem_object *obj; |
76c1dec1 | 4055 | int ret; |
3ef94daa CW |
4056 | |
4057 | switch (args->madv) { | |
4058 | case I915_MADV_DONTNEED: | |
4059 | case I915_MADV_WILLNEED: | |
4060 | break; | |
4061 | default: | |
4062 | return -EINVAL; | |
4063 | } | |
4064 | ||
1d7cfea1 CW |
4065 | ret = i915_mutex_lock_interruptible(dev); |
4066 | if (ret) | |
4067 | return ret; | |
4068 | ||
05394f39 | 4069 | obj = to_intel_bo(drm_gem_object_lookup(dev, file_priv, args->handle)); |
c8725226 | 4070 | if (&obj->base == NULL) { |
1d7cfea1 CW |
4071 | ret = -ENOENT; |
4072 | goto unlock; | |
3ef94daa | 4073 | } |
3ef94daa | 4074 | |
d7f46fc4 | 4075 | if (i915_gem_obj_is_pinned(obj)) { |
1d7cfea1 CW |
4076 | ret = -EINVAL; |
4077 | goto out; | |
3ef94daa CW |
4078 | } |
4079 | ||
05394f39 CW |
4080 | if (obj->madv != __I915_MADV_PURGED) |
4081 | obj->madv = args->madv; | |
3ef94daa | 4082 | |
6c085a72 CW |
4083 | /* if the object is no longer attached, discard its backing storage */ |
4084 | if (i915_gem_object_is_purgeable(obj) && obj->pages == NULL) | |
2d7ef395 CW |
4085 | i915_gem_object_truncate(obj); |
4086 | ||
05394f39 | 4087 | args->retained = obj->madv != __I915_MADV_PURGED; |
bb6baf76 | 4088 | |
1d7cfea1 | 4089 | out: |
05394f39 | 4090 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 4091 | unlock: |
3ef94daa | 4092 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 4093 | return ret; |
3ef94daa CW |
4094 | } |
4095 | ||
37e680a1 CW |
4096 | void i915_gem_object_init(struct drm_i915_gem_object *obj, |
4097 | const struct drm_i915_gem_object_ops *ops) | |
0327d6ba | 4098 | { |
35c20a60 | 4099 | INIT_LIST_HEAD(&obj->global_list); |
0327d6ba | 4100 | INIT_LIST_HEAD(&obj->ring_list); |
b25cb2f8 | 4101 | INIT_LIST_HEAD(&obj->obj_exec_link); |
2f633156 | 4102 | INIT_LIST_HEAD(&obj->vma_list); |
0327d6ba | 4103 | |
37e680a1 CW |
4104 | obj->ops = ops; |
4105 | ||
0327d6ba CW |
4106 | obj->fence_reg = I915_FENCE_REG_NONE; |
4107 | obj->madv = I915_MADV_WILLNEED; | |
4108 | /* Avoid an unnecessary call to unbind on the first bind. */ | |
4109 | obj->map_and_fenceable = true; | |
4110 | ||
4111 | i915_gem_info_add_obj(obj->base.dev->dev_private, obj->base.size); | |
4112 | } | |
4113 | ||
37e680a1 CW |
4114 | static const struct drm_i915_gem_object_ops i915_gem_object_ops = { |
4115 | .get_pages = i915_gem_object_get_pages_gtt, | |
4116 | .put_pages = i915_gem_object_put_pages_gtt, | |
4117 | }; | |
4118 | ||
05394f39 CW |
4119 | struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev, |
4120 | size_t size) | |
ac52bc56 | 4121 | { |
c397b908 | 4122 | struct drm_i915_gem_object *obj; |
5949eac4 | 4123 | struct address_space *mapping; |
1a240d4d | 4124 | gfp_t mask; |
ac52bc56 | 4125 | |
42dcedd4 | 4126 | obj = i915_gem_object_alloc(dev); |
c397b908 DV |
4127 | if (obj == NULL) |
4128 | return NULL; | |
673a394b | 4129 | |
c397b908 | 4130 | if (drm_gem_object_init(dev, &obj->base, size) != 0) { |
42dcedd4 | 4131 | i915_gem_object_free(obj); |
c397b908 DV |
4132 | return NULL; |
4133 | } | |
673a394b | 4134 | |
bed1ea95 CW |
4135 | mask = GFP_HIGHUSER | __GFP_RECLAIMABLE; |
4136 | if (IS_CRESTLINE(dev) || IS_BROADWATER(dev)) { | |
4137 | /* 965gm cannot relocate objects above 4GiB. */ | |
4138 | mask &= ~__GFP_HIGHMEM; | |
4139 | mask |= __GFP_DMA32; | |
4140 | } | |
4141 | ||
496ad9aa | 4142 | mapping = file_inode(obj->base.filp)->i_mapping; |
bed1ea95 | 4143 | mapping_set_gfp_mask(mapping, mask); |
5949eac4 | 4144 | |
37e680a1 | 4145 | i915_gem_object_init(obj, &i915_gem_object_ops); |
73aa808f | 4146 | |
c397b908 DV |
4147 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; |
4148 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; | |
673a394b | 4149 | |
3d29b842 ED |
4150 | if (HAS_LLC(dev)) { |
4151 | /* On some devices, we can have the GPU use the LLC (the CPU | |
a1871112 EA |
4152 | * cache) for about a 10% performance improvement |
4153 | * compared to uncached. Graphics requests other than | |
4154 | * display scanout are coherent with the CPU in | |
4155 | * accessing this cache. This means in this mode we | |
4156 | * don't need to clflush on the CPU side, and on the | |
4157 | * GPU side we only need to flush internal caches to | |
4158 | * get data visible to the CPU. | |
4159 | * | |
4160 | * However, we maintain the display planes as UC, and so | |
4161 | * need to rebind when first used as such. | |
4162 | */ | |
4163 | obj->cache_level = I915_CACHE_LLC; | |
4164 | } else | |
4165 | obj->cache_level = I915_CACHE_NONE; | |
4166 | ||
d861e338 DV |
4167 | trace_i915_gem_object_create(obj); |
4168 | ||
05394f39 | 4169 | return obj; |
c397b908 DV |
4170 | } |
4171 | ||
1488fc08 | 4172 | void i915_gem_free_object(struct drm_gem_object *gem_obj) |
673a394b | 4173 | { |
1488fc08 | 4174 | struct drm_i915_gem_object *obj = to_intel_bo(gem_obj); |
05394f39 | 4175 | struct drm_device *dev = obj->base.dev; |
be72615b | 4176 | drm_i915_private_t *dev_priv = dev->dev_private; |
07fe0b12 | 4177 | struct i915_vma *vma, *next; |
673a394b | 4178 | |
26e12f89 CW |
4179 | trace_i915_gem_object_destroy(obj); |
4180 | ||
1488fc08 CW |
4181 | if (obj->phys_obj) |
4182 | i915_gem_detach_phys_object(dev, obj); | |
4183 | ||
07fe0b12 BW |
4184 | /* NB: 0 or 1 elements */ |
4185 | WARN_ON(!list_empty(&obj->vma_list) && | |
4186 | !list_is_singular(&obj->vma_list)); | |
4187 | list_for_each_entry_safe(vma, next, &obj->vma_list, vma_link) { | |
d7f46fc4 BW |
4188 | int ret; |
4189 | ||
4190 | vma->pin_count = 0; | |
4191 | ret = i915_vma_unbind(vma); | |
07fe0b12 BW |
4192 | if (WARN_ON(ret == -ERESTARTSYS)) { |
4193 | bool was_interruptible; | |
1488fc08 | 4194 | |
07fe0b12 BW |
4195 | was_interruptible = dev_priv->mm.interruptible; |
4196 | dev_priv->mm.interruptible = false; | |
1488fc08 | 4197 | |
07fe0b12 | 4198 | WARN_ON(i915_vma_unbind(vma)); |
1488fc08 | 4199 | |
07fe0b12 BW |
4200 | dev_priv->mm.interruptible = was_interruptible; |
4201 | } | |
1488fc08 CW |
4202 | } |
4203 | ||
1d64ae71 BW |
4204 | /* Stolen objects don't hold a ref, but do hold pin count. Fix that up |
4205 | * before progressing. */ | |
4206 | if (obj->stolen) | |
4207 | i915_gem_object_unpin_pages(obj); | |
4208 | ||
401c29f6 BW |
4209 | if (WARN_ON(obj->pages_pin_count)) |
4210 | obj->pages_pin_count = 0; | |
37e680a1 | 4211 | i915_gem_object_put_pages(obj); |
d8cb5086 | 4212 | i915_gem_object_free_mmap_offset(obj); |
0104fdbb | 4213 | i915_gem_object_release_stolen(obj); |
de151cf6 | 4214 | |
9da3da66 CW |
4215 | BUG_ON(obj->pages); |
4216 | ||
2f745ad3 CW |
4217 | if (obj->base.import_attach) |
4218 | drm_prime_gem_destroy(&obj->base, NULL); | |
de151cf6 | 4219 | |
05394f39 CW |
4220 | drm_gem_object_release(&obj->base); |
4221 | i915_gem_info_remove_obj(dev_priv, obj->base.size); | |
c397b908 | 4222 | |
05394f39 | 4223 | kfree(obj->bit_17); |
42dcedd4 | 4224 | i915_gem_object_free(obj); |
673a394b EA |
4225 | } |
4226 | ||
e656a6cb | 4227 | struct i915_vma *i915_gem_obj_to_vma(struct drm_i915_gem_object *obj, |
2f633156 | 4228 | struct i915_address_space *vm) |
e656a6cb DV |
4229 | { |
4230 | struct i915_vma *vma; | |
4231 | list_for_each_entry(vma, &obj->vma_list, vma_link) | |
4232 | if (vma->vm == vm) | |
4233 | return vma; | |
4234 | ||
4235 | return NULL; | |
4236 | } | |
4237 | ||
4238 | static struct i915_vma *__i915_gem_vma_create(struct drm_i915_gem_object *obj, | |
4239 | struct i915_address_space *vm) | |
2f633156 BW |
4240 | { |
4241 | struct i915_vma *vma = kzalloc(sizeof(*vma), GFP_KERNEL); | |
4242 | if (vma == NULL) | |
4243 | return ERR_PTR(-ENOMEM); | |
4244 | ||
4245 | INIT_LIST_HEAD(&vma->vma_link); | |
ca191b13 | 4246 | INIT_LIST_HEAD(&vma->mm_list); |
82a55ad1 | 4247 | INIT_LIST_HEAD(&vma->exec_list); |
2f633156 BW |
4248 | vma->vm = vm; |
4249 | vma->obj = obj; | |
4250 | ||
8b9c2b94 BW |
4251 | /* Keep GGTT vmas first to make debug easier */ |
4252 | if (i915_is_ggtt(vm)) | |
4253 | list_add(&vma->vma_link, &obj->vma_list); | |
4254 | else | |
4255 | list_add_tail(&vma->vma_link, &obj->vma_list); | |
4256 | ||
2f633156 BW |
4257 | return vma; |
4258 | } | |
4259 | ||
e656a6cb DV |
4260 | struct i915_vma * |
4261 | i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object *obj, | |
4262 | struct i915_address_space *vm) | |
4263 | { | |
4264 | struct i915_vma *vma; | |
4265 | ||
4266 | vma = i915_gem_obj_to_vma(obj, vm); | |
4267 | if (!vma) | |
4268 | vma = __i915_gem_vma_create(obj, vm); | |
4269 | ||
4270 | return vma; | |
4271 | } | |
4272 | ||
2f633156 BW |
4273 | void i915_gem_vma_destroy(struct i915_vma *vma) |
4274 | { | |
4275 | WARN_ON(vma->node.allocated); | |
aaa05667 CW |
4276 | |
4277 | /* Keep the vma as a placeholder in the execbuffer reservation lists */ | |
4278 | if (!list_empty(&vma->exec_list)) | |
4279 | return; | |
4280 | ||
8b9c2b94 | 4281 | list_del(&vma->vma_link); |
b93dab6e | 4282 | |
2f633156 BW |
4283 | kfree(vma); |
4284 | } | |
4285 | ||
29105ccc | 4286 | int |
45c5f202 | 4287 | i915_gem_suspend(struct drm_device *dev) |
29105ccc CW |
4288 | { |
4289 | drm_i915_private_t *dev_priv = dev->dev_private; | |
45c5f202 | 4290 | int ret = 0; |
28dfe52a | 4291 | |
45c5f202 | 4292 | mutex_lock(&dev->struct_mutex); |
f7403347 | 4293 | if (dev_priv->ums.mm_suspended) |
45c5f202 | 4294 | goto err; |
28dfe52a | 4295 | |
b2da9fe5 | 4296 | ret = i915_gpu_idle(dev); |
f7403347 | 4297 | if (ret) |
45c5f202 | 4298 | goto err; |
f7403347 | 4299 | |
b2da9fe5 | 4300 | i915_gem_retire_requests(dev); |
673a394b | 4301 | |
29105ccc | 4302 | /* Under UMS, be paranoid and evict. */ |
a39d7efc | 4303 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) |
6c085a72 | 4304 | i915_gem_evict_everything(dev); |
29105ccc | 4305 | |
29105ccc | 4306 | i915_kernel_lost_context(dev); |
6dbe2772 | 4307 | i915_gem_cleanup_ringbuffer(dev); |
29105ccc | 4308 | |
45c5f202 CW |
4309 | /* Hack! Don't let anybody do execbuf while we don't control the chip. |
4310 | * We need to replace this with a semaphore, or something. | |
4311 | * And not confound ums.mm_suspended! | |
4312 | */ | |
4313 | dev_priv->ums.mm_suspended = !drm_core_check_feature(dev, | |
4314 | DRIVER_MODESET); | |
4315 | mutex_unlock(&dev->struct_mutex); | |
4316 | ||
4317 | del_timer_sync(&dev_priv->gpu_error.hangcheck_timer); | |
29105ccc | 4318 | cancel_delayed_work_sync(&dev_priv->mm.retire_work); |
b29c19b6 | 4319 | cancel_delayed_work_sync(&dev_priv->mm.idle_work); |
29105ccc | 4320 | |
673a394b | 4321 | return 0; |
45c5f202 CW |
4322 | |
4323 | err: | |
4324 | mutex_unlock(&dev->struct_mutex); | |
4325 | return ret; | |
673a394b EA |
4326 | } |
4327 | ||
c3787e2e | 4328 | int i915_gem_l3_remap(struct intel_ring_buffer *ring, int slice) |
b9524a1e | 4329 | { |
c3787e2e | 4330 | struct drm_device *dev = ring->dev; |
b9524a1e | 4331 | drm_i915_private_t *dev_priv = dev->dev_private; |
35a85ac6 BW |
4332 | u32 reg_base = GEN7_L3LOG_BASE + (slice * 0x200); |
4333 | u32 *remap_info = dev_priv->l3_parity.remap_info[slice]; | |
c3787e2e | 4334 | int i, ret; |
b9524a1e | 4335 | |
040d2baa | 4336 | if (!HAS_L3_DPF(dev) || !remap_info) |
c3787e2e | 4337 | return 0; |
b9524a1e | 4338 | |
c3787e2e BW |
4339 | ret = intel_ring_begin(ring, GEN7_L3LOG_SIZE / 4 * 3); |
4340 | if (ret) | |
4341 | return ret; | |
b9524a1e | 4342 | |
c3787e2e BW |
4343 | /* |
4344 | * Note: We do not worry about the concurrent register cacheline hang | |
4345 | * here because no other code should access these registers other than | |
4346 | * at initialization time. | |
4347 | */ | |
b9524a1e | 4348 | for (i = 0; i < GEN7_L3LOG_SIZE; i += 4) { |
c3787e2e BW |
4349 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); |
4350 | intel_ring_emit(ring, reg_base + i); | |
4351 | intel_ring_emit(ring, remap_info[i/4]); | |
b9524a1e BW |
4352 | } |
4353 | ||
c3787e2e | 4354 | intel_ring_advance(ring); |
b9524a1e | 4355 | |
c3787e2e | 4356 | return ret; |
b9524a1e BW |
4357 | } |
4358 | ||
f691e2f4 DV |
4359 | void i915_gem_init_swizzling(struct drm_device *dev) |
4360 | { | |
4361 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4362 | ||
11782b02 | 4363 | if (INTEL_INFO(dev)->gen < 5 || |
f691e2f4 DV |
4364 | dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE) |
4365 | return; | |
4366 | ||
4367 | I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) | | |
4368 | DISP_TILE_SURFACE_SWIZZLING); | |
4369 | ||
11782b02 DV |
4370 | if (IS_GEN5(dev)) |
4371 | return; | |
4372 | ||
f691e2f4 DV |
4373 | I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_SWZCTL); |
4374 | if (IS_GEN6(dev)) | |
6b26c86d | 4375 | I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB)); |
8782e26c | 4376 | else if (IS_GEN7(dev)) |
6b26c86d | 4377 | I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB)); |
31a5336e BW |
4378 | else if (IS_GEN8(dev)) |
4379 | I915_WRITE(GAMTARBMODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_BDW)); | |
8782e26c BW |
4380 | else |
4381 | BUG(); | |
f691e2f4 | 4382 | } |
e21af88d | 4383 | |
67b1b571 CW |
4384 | static bool |
4385 | intel_enable_blt(struct drm_device *dev) | |
4386 | { | |
4387 | if (!HAS_BLT(dev)) | |
4388 | return false; | |
4389 | ||
4390 | /* The blitter was dysfunctional on early prototypes */ | |
4391 | if (IS_GEN6(dev) && dev->pdev->revision < 8) { | |
4392 | DRM_INFO("BLT not supported on this pre-production hardware;" | |
4393 | " graphics performance will be degraded.\n"); | |
4394 | return false; | |
4395 | } | |
4396 | ||
4397 | return true; | |
4398 | } | |
4399 | ||
4fc7c971 | 4400 | static int i915_gem_init_rings(struct drm_device *dev) |
8187a2b7 | 4401 | { |
4fc7c971 | 4402 | struct drm_i915_private *dev_priv = dev->dev_private; |
8187a2b7 | 4403 | int ret; |
68f95ba9 | 4404 | |
5c1143bb | 4405 | ret = intel_init_render_ring_buffer(dev); |
68f95ba9 | 4406 | if (ret) |
b6913e4b | 4407 | return ret; |
68f95ba9 CW |
4408 | |
4409 | if (HAS_BSD(dev)) { | |
5c1143bb | 4410 | ret = intel_init_bsd_ring_buffer(dev); |
68f95ba9 CW |
4411 | if (ret) |
4412 | goto cleanup_render_ring; | |
d1b851fc | 4413 | } |
68f95ba9 | 4414 | |
67b1b571 | 4415 | if (intel_enable_blt(dev)) { |
549f7365 CW |
4416 | ret = intel_init_blt_ring_buffer(dev); |
4417 | if (ret) | |
4418 | goto cleanup_bsd_ring; | |
4419 | } | |
4420 | ||
9a8a2213 BW |
4421 | if (HAS_VEBOX(dev)) { |
4422 | ret = intel_init_vebox_ring_buffer(dev); | |
4423 | if (ret) | |
4424 | goto cleanup_blt_ring; | |
4425 | } | |
4426 | ||
4427 | ||
99433931 | 4428 | ret = i915_gem_set_seqno(dev, ((u32)~0 - 0x1000)); |
4fc7c971 | 4429 | if (ret) |
9a8a2213 | 4430 | goto cleanup_vebox_ring; |
4fc7c971 BW |
4431 | |
4432 | return 0; | |
4433 | ||
9a8a2213 BW |
4434 | cleanup_vebox_ring: |
4435 | intel_cleanup_ring_buffer(&dev_priv->ring[VECS]); | |
4fc7c971 BW |
4436 | cleanup_blt_ring: |
4437 | intel_cleanup_ring_buffer(&dev_priv->ring[BCS]); | |
4438 | cleanup_bsd_ring: | |
4439 | intel_cleanup_ring_buffer(&dev_priv->ring[VCS]); | |
4440 | cleanup_render_ring: | |
4441 | intel_cleanup_ring_buffer(&dev_priv->ring[RCS]); | |
4442 | ||
4443 | return ret; | |
4444 | } | |
4445 | ||
4446 | int | |
4447 | i915_gem_init_hw(struct drm_device *dev) | |
4448 | { | |
4449 | drm_i915_private_t *dev_priv = dev->dev_private; | |
35a85ac6 | 4450 | int ret, i; |
4fc7c971 BW |
4451 | |
4452 | if (INTEL_INFO(dev)->gen < 6 && !intel_enable_gtt()) | |
4453 | return -EIO; | |
4454 | ||
59124506 | 4455 | if (dev_priv->ellc_size) |
05e21cc4 | 4456 | I915_WRITE(HSW_IDICR, I915_READ(HSW_IDICR) | IDIHASHMSK(0xf)); |
4fc7c971 | 4457 | |
9435373e RV |
4458 | if (IS_HSW_GT3(dev)) |
4459 | I915_WRITE(MI_PREDICATE_RESULT_2, LOWER_SLICE_ENABLED); | |
4460 | else | |
4461 | I915_WRITE(MI_PREDICATE_RESULT_2, LOWER_SLICE_DISABLED); | |
4462 | ||
88a2b2a3 BW |
4463 | if (HAS_PCH_NOP(dev)) { |
4464 | u32 temp = I915_READ(GEN7_MSG_CTL); | |
4465 | temp &= ~(WAIT_FOR_PCH_FLR_ACK | WAIT_FOR_PCH_RESET_ACK); | |
4466 | I915_WRITE(GEN7_MSG_CTL, temp); | |
4467 | } | |
4468 | ||
4fc7c971 BW |
4469 | i915_gem_init_swizzling(dev); |
4470 | ||
4471 | ret = i915_gem_init_rings(dev); | |
99433931 MK |
4472 | if (ret) |
4473 | return ret; | |
4474 | ||
c3787e2e BW |
4475 | for (i = 0; i < NUM_L3_SLICES(dev); i++) |
4476 | i915_gem_l3_remap(&dev_priv->ring[RCS], i); | |
4477 | ||
254f965c BW |
4478 | /* |
4479 | * XXX: There was some w/a described somewhere suggesting loading | |
4480 | * contexts before PPGTT. | |
4481 | */ | |
8245be31 BW |
4482 | ret = i915_gem_context_init(dev); |
4483 | if (ret) { | |
4484 | i915_gem_cleanup_ringbuffer(dev); | |
4485 | DRM_ERROR("Context initialization failed %d\n", ret); | |
4486 | return ret; | |
4487 | } | |
4488 | ||
b7c36d25 BW |
4489 | if (dev_priv->mm.aliasing_ppgtt) { |
4490 | ret = dev_priv->mm.aliasing_ppgtt->enable(dev); | |
4491 | if (ret) { | |
4492 | i915_gem_cleanup_aliasing_ppgtt(dev); | |
4493 | DRM_INFO("PPGTT enable failed. This is not fatal, but unexpected\n"); | |
4494 | } | |
4495 | } | |
e21af88d | 4496 | |
68f95ba9 | 4497 | return 0; |
8187a2b7 ZN |
4498 | } |
4499 | ||
1070a42b CW |
4500 | int i915_gem_init(struct drm_device *dev) |
4501 | { | |
4502 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1070a42b CW |
4503 | int ret; |
4504 | ||
1070a42b | 4505 | mutex_lock(&dev->struct_mutex); |
d62b4892 JB |
4506 | |
4507 | if (IS_VALLEYVIEW(dev)) { | |
4508 | /* VLVA0 (potential hack), BIOS isn't actually waking us */ | |
4509 | I915_WRITE(VLV_GTLC_WAKE_CTRL, 1); | |
4510 | if (wait_for((I915_READ(VLV_GTLC_PW_STATUS) & 1) == 1, 10)) | |
4511 | DRM_DEBUG_DRIVER("allow wake ack timed out\n"); | |
4512 | } | |
4513 | ||
d7e5008f | 4514 | i915_gem_init_global_gtt(dev); |
d62b4892 | 4515 | |
1070a42b CW |
4516 | ret = i915_gem_init_hw(dev); |
4517 | mutex_unlock(&dev->struct_mutex); | |
4518 | if (ret) { | |
4519 | i915_gem_cleanup_aliasing_ppgtt(dev); | |
c39538a8 | 4520 | drm_mm_takedown(&dev_priv->gtt.base.mm); |
1070a42b CW |
4521 | return ret; |
4522 | } | |
4523 | ||
53ca26ca DV |
4524 | /* Allow hardware batchbuffers unless told otherwise, but not for KMS. */ |
4525 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) | |
4526 | dev_priv->dri1.allow_batchbuffer = 1; | |
1070a42b CW |
4527 | return 0; |
4528 | } | |
4529 | ||
8187a2b7 ZN |
4530 | void |
4531 | i915_gem_cleanup_ringbuffer(struct drm_device *dev) | |
4532 | { | |
4533 | drm_i915_private_t *dev_priv = dev->dev_private; | |
b4519513 | 4534 | struct intel_ring_buffer *ring; |
1ec14ad3 | 4535 | int i; |
8187a2b7 | 4536 | |
b4519513 CW |
4537 | for_each_ring(ring, dev_priv, i) |
4538 | intel_cleanup_ring_buffer(ring); | |
8187a2b7 ZN |
4539 | } |
4540 | ||
673a394b EA |
4541 | int |
4542 | i915_gem_entervt_ioctl(struct drm_device *dev, void *data, | |
4543 | struct drm_file *file_priv) | |
4544 | { | |
db1b76ca | 4545 | struct drm_i915_private *dev_priv = dev->dev_private; |
b4519513 | 4546 | int ret; |
673a394b | 4547 | |
79e53945 JB |
4548 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
4549 | return 0; | |
4550 | ||
1f83fee0 | 4551 | if (i915_reset_in_progress(&dev_priv->gpu_error)) { |
673a394b | 4552 | DRM_ERROR("Reenabling wedged hardware, good luck\n"); |
1f83fee0 | 4553 | atomic_set(&dev_priv->gpu_error.reset_counter, 0); |
673a394b EA |
4554 | } |
4555 | ||
673a394b | 4556 | mutex_lock(&dev->struct_mutex); |
db1b76ca | 4557 | dev_priv->ums.mm_suspended = 0; |
9bb2d6f9 | 4558 | |
f691e2f4 | 4559 | ret = i915_gem_init_hw(dev); |
d816f6ac WF |
4560 | if (ret != 0) { |
4561 | mutex_unlock(&dev->struct_mutex); | |
9bb2d6f9 | 4562 | return ret; |
d816f6ac | 4563 | } |
9bb2d6f9 | 4564 | |
5cef07e1 | 4565 | BUG_ON(!list_empty(&dev_priv->gtt.base.active_list)); |
673a394b | 4566 | mutex_unlock(&dev->struct_mutex); |
dbb19d30 | 4567 | |
5f35308b CW |
4568 | ret = drm_irq_install(dev); |
4569 | if (ret) | |
4570 | goto cleanup_ringbuffer; | |
dbb19d30 | 4571 | |
673a394b | 4572 | return 0; |
5f35308b CW |
4573 | |
4574 | cleanup_ringbuffer: | |
4575 | mutex_lock(&dev->struct_mutex); | |
4576 | i915_gem_cleanup_ringbuffer(dev); | |
db1b76ca | 4577 | dev_priv->ums.mm_suspended = 1; |
5f35308b CW |
4578 | mutex_unlock(&dev->struct_mutex); |
4579 | ||
4580 | return ret; | |
673a394b EA |
4581 | } |
4582 | ||
4583 | int | |
4584 | i915_gem_leavevt_ioctl(struct drm_device *dev, void *data, | |
4585 | struct drm_file *file_priv) | |
4586 | { | |
79e53945 JB |
4587 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
4588 | return 0; | |
4589 | ||
dbb19d30 | 4590 | drm_irq_uninstall(dev); |
db1b76ca | 4591 | |
45c5f202 | 4592 | return i915_gem_suspend(dev); |
673a394b EA |
4593 | } |
4594 | ||
4595 | void | |
4596 | i915_gem_lastclose(struct drm_device *dev) | |
4597 | { | |
4598 | int ret; | |
673a394b | 4599 | |
e806b495 EA |
4600 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
4601 | return; | |
4602 | ||
45c5f202 | 4603 | ret = i915_gem_suspend(dev); |
6dbe2772 KP |
4604 | if (ret) |
4605 | DRM_ERROR("failed to idle hardware: %d\n", ret); | |
673a394b EA |
4606 | } |
4607 | ||
64193406 CW |
4608 | static void |
4609 | init_ring_lists(struct intel_ring_buffer *ring) | |
4610 | { | |
4611 | INIT_LIST_HEAD(&ring->active_list); | |
4612 | INIT_LIST_HEAD(&ring->request_list); | |
64193406 CW |
4613 | } |
4614 | ||
fc8c067e BW |
4615 | static void i915_init_vm(struct drm_i915_private *dev_priv, |
4616 | struct i915_address_space *vm) | |
4617 | { | |
4618 | vm->dev = dev_priv->dev; | |
4619 | INIT_LIST_HEAD(&vm->active_list); | |
4620 | INIT_LIST_HEAD(&vm->inactive_list); | |
4621 | INIT_LIST_HEAD(&vm->global_link); | |
4622 | list_add(&vm->global_link, &dev_priv->vm_list); | |
4623 | } | |
4624 | ||
673a394b EA |
4625 | void |
4626 | i915_gem_load(struct drm_device *dev) | |
4627 | { | |
4628 | drm_i915_private_t *dev_priv = dev->dev_private; | |
42dcedd4 CW |
4629 | int i; |
4630 | ||
4631 | dev_priv->slab = | |
4632 | kmem_cache_create("i915_gem_object", | |
4633 | sizeof(struct drm_i915_gem_object), 0, | |
4634 | SLAB_HWCACHE_ALIGN, | |
4635 | NULL); | |
673a394b | 4636 | |
fc8c067e BW |
4637 | INIT_LIST_HEAD(&dev_priv->vm_list); |
4638 | i915_init_vm(dev_priv, &dev_priv->gtt.base); | |
4639 | ||
a33afea5 | 4640 | INIT_LIST_HEAD(&dev_priv->context_list); |
6c085a72 CW |
4641 | INIT_LIST_HEAD(&dev_priv->mm.unbound_list); |
4642 | INIT_LIST_HEAD(&dev_priv->mm.bound_list); | |
a09ba7fa | 4643 | INIT_LIST_HEAD(&dev_priv->mm.fence_list); |
1ec14ad3 CW |
4644 | for (i = 0; i < I915_NUM_RINGS; i++) |
4645 | init_ring_lists(&dev_priv->ring[i]); | |
4b9de737 | 4646 | for (i = 0; i < I915_MAX_NUM_FENCES; i++) |
007cc8ac | 4647 | INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list); |
673a394b EA |
4648 | INIT_DELAYED_WORK(&dev_priv->mm.retire_work, |
4649 | i915_gem_retire_work_handler); | |
b29c19b6 CW |
4650 | INIT_DELAYED_WORK(&dev_priv->mm.idle_work, |
4651 | i915_gem_idle_work_handler); | |
1f83fee0 | 4652 | init_waitqueue_head(&dev_priv->gpu_error.reset_queue); |
31169714 | 4653 | |
94400120 DA |
4654 | /* On GEN3 we really need to make sure the ARB C3 LP bit is set */ |
4655 | if (IS_GEN3(dev)) { | |
50743298 DV |
4656 | I915_WRITE(MI_ARB_STATE, |
4657 | _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE)); | |
94400120 DA |
4658 | } |
4659 | ||
72bfa19c CW |
4660 | dev_priv->relative_constants_mode = I915_EXEC_CONSTANTS_REL_GENERAL; |
4661 | ||
de151cf6 | 4662 | /* Old X drivers will take 0-2 for front, back, depth buffers */ |
b397c836 EA |
4663 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) |
4664 | dev_priv->fence_reg_start = 3; | |
de151cf6 | 4665 | |
42b5aeab VS |
4666 | if (INTEL_INFO(dev)->gen >= 7 && !IS_VALLEYVIEW(dev)) |
4667 | dev_priv->num_fence_regs = 32; | |
4668 | else if (INTEL_INFO(dev)->gen >= 4 || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) | |
de151cf6 JB |
4669 | dev_priv->num_fence_regs = 16; |
4670 | else | |
4671 | dev_priv->num_fence_regs = 8; | |
4672 | ||
b5aa8a0f | 4673 | /* Initialize fence registers to zero */ |
19b2dbde CW |
4674 | INIT_LIST_HEAD(&dev_priv->mm.fence_list); |
4675 | i915_gem_restore_fences(dev); | |
10ed13e4 | 4676 | |
673a394b | 4677 | i915_gem_detect_bit_6_swizzle(dev); |
6b95a207 | 4678 | init_waitqueue_head(&dev_priv->pending_flip_queue); |
17250b71 | 4679 | |
ce453d81 CW |
4680 | dev_priv->mm.interruptible = true; |
4681 | ||
7dc19d5a DC |
4682 | dev_priv->mm.inactive_shrinker.scan_objects = i915_gem_inactive_scan; |
4683 | dev_priv->mm.inactive_shrinker.count_objects = i915_gem_inactive_count; | |
17250b71 CW |
4684 | dev_priv->mm.inactive_shrinker.seeks = DEFAULT_SEEKS; |
4685 | register_shrinker(&dev_priv->mm.inactive_shrinker); | |
673a394b | 4686 | } |
71acb5eb DA |
4687 | |
4688 | /* | |
4689 | * Create a physically contiguous memory object for this object | |
4690 | * e.g. for cursor + overlay regs | |
4691 | */ | |
995b6762 CW |
4692 | static int i915_gem_init_phys_object(struct drm_device *dev, |
4693 | int id, int size, int align) | |
71acb5eb DA |
4694 | { |
4695 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4696 | struct drm_i915_gem_phys_object *phys_obj; | |
4697 | int ret; | |
4698 | ||
4699 | if (dev_priv->mm.phys_objs[id - 1] || !size) | |
4700 | return 0; | |
4701 | ||
b14c5679 | 4702 | phys_obj = kzalloc(sizeof(*phys_obj), GFP_KERNEL); |
71acb5eb DA |
4703 | if (!phys_obj) |
4704 | return -ENOMEM; | |
4705 | ||
4706 | phys_obj->id = id; | |
4707 | ||
6eeefaf3 | 4708 | phys_obj->handle = drm_pci_alloc(dev, size, align); |
71acb5eb DA |
4709 | if (!phys_obj->handle) { |
4710 | ret = -ENOMEM; | |
4711 | goto kfree_obj; | |
4712 | } | |
4713 | #ifdef CONFIG_X86 | |
4714 | set_memory_wc((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE); | |
4715 | #endif | |
4716 | ||
4717 | dev_priv->mm.phys_objs[id - 1] = phys_obj; | |
4718 | ||
4719 | return 0; | |
4720 | kfree_obj: | |
9a298b2a | 4721 | kfree(phys_obj); |
71acb5eb DA |
4722 | return ret; |
4723 | } | |
4724 | ||
995b6762 | 4725 | static void i915_gem_free_phys_object(struct drm_device *dev, int id) |
71acb5eb DA |
4726 | { |
4727 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4728 | struct drm_i915_gem_phys_object *phys_obj; | |
4729 | ||
4730 | if (!dev_priv->mm.phys_objs[id - 1]) | |
4731 | return; | |
4732 | ||
4733 | phys_obj = dev_priv->mm.phys_objs[id - 1]; | |
4734 | if (phys_obj->cur_obj) { | |
4735 | i915_gem_detach_phys_object(dev, phys_obj->cur_obj); | |
4736 | } | |
4737 | ||
4738 | #ifdef CONFIG_X86 | |
4739 | set_memory_wb((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE); | |
4740 | #endif | |
4741 | drm_pci_free(dev, phys_obj->handle); | |
4742 | kfree(phys_obj); | |
4743 | dev_priv->mm.phys_objs[id - 1] = NULL; | |
4744 | } | |
4745 | ||
4746 | void i915_gem_free_all_phys_object(struct drm_device *dev) | |
4747 | { | |
4748 | int i; | |
4749 | ||
260883c8 | 4750 | for (i = I915_GEM_PHYS_CURSOR_0; i <= I915_MAX_PHYS_OBJECT; i++) |
71acb5eb DA |
4751 | i915_gem_free_phys_object(dev, i); |
4752 | } | |
4753 | ||
4754 | void i915_gem_detach_phys_object(struct drm_device *dev, | |
05394f39 | 4755 | struct drm_i915_gem_object *obj) |
71acb5eb | 4756 | { |
496ad9aa | 4757 | struct address_space *mapping = file_inode(obj->base.filp)->i_mapping; |
e5281ccd | 4758 | char *vaddr; |
71acb5eb | 4759 | int i; |
71acb5eb DA |
4760 | int page_count; |
4761 | ||
05394f39 | 4762 | if (!obj->phys_obj) |
71acb5eb | 4763 | return; |
05394f39 | 4764 | vaddr = obj->phys_obj->handle->vaddr; |
71acb5eb | 4765 | |
05394f39 | 4766 | page_count = obj->base.size / PAGE_SIZE; |
71acb5eb | 4767 | for (i = 0; i < page_count; i++) { |
5949eac4 | 4768 | struct page *page = shmem_read_mapping_page(mapping, i); |
e5281ccd CW |
4769 | if (!IS_ERR(page)) { |
4770 | char *dst = kmap_atomic(page); | |
4771 | memcpy(dst, vaddr + i*PAGE_SIZE, PAGE_SIZE); | |
4772 | kunmap_atomic(dst); | |
4773 | ||
4774 | drm_clflush_pages(&page, 1); | |
4775 | ||
4776 | set_page_dirty(page); | |
4777 | mark_page_accessed(page); | |
4778 | page_cache_release(page); | |
4779 | } | |
71acb5eb | 4780 | } |
e76e9aeb | 4781 | i915_gem_chipset_flush(dev); |
d78b47b9 | 4782 | |
05394f39 CW |
4783 | obj->phys_obj->cur_obj = NULL; |
4784 | obj->phys_obj = NULL; | |
71acb5eb DA |
4785 | } |
4786 | ||
4787 | int | |
4788 | i915_gem_attach_phys_object(struct drm_device *dev, | |
05394f39 | 4789 | struct drm_i915_gem_object *obj, |
6eeefaf3 CW |
4790 | int id, |
4791 | int align) | |
71acb5eb | 4792 | { |
496ad9aa | 4793 | struct address_space *mapping = file_inode(obj->base.filp)->i_mapping; |
71acb5eb | 4794 | drm_i915_private_t *dev_priv = dev->dev_private; |
71acb5eb DA |
4795 | int ret = 0; |
4796 | int page_count; | |
4797 | int i; | |
4798 | ||
4799 | if (id > I915_MAX_PHYS_OBJECT) | |
4800 | return -EINVAL; | |
4801 | ||
05394f39 CW |
4802 | if (obj->phys_obj) { |
4803 | if (obj->phys_obj->id == id) | |
71acb5eb DA |
4804 | return 0; |
4805 | i915_gem_detach_phys_object(dev, obj); | |
4806 | } | |
4807 | ||
71acb5eb DA |
4808 | /* create a new object */ |
4809 | if (!dev_priv->mm.phys_objs[id - 1]) { | |
4810 | ret = i915_gem_init_phys_object(dev, id, | |
05394f39 | 4811 | obj->base.size, align); |
71acb5eb | 4812 | if (ret) { |
05394f39 CW |
4813 | DRM_ERROR("failed to init phys object %d size: %zu\n", |
4814 | id, obj->base.size); | |
e5281ccd | 4815 | return ret; |
71acb5eb DA |
4816 | } |
4817 | } | |
4818 | ||
4819 | /* bind to the object */ | |
05394f39 CW |
4820 | obj->phys_obj = dev_priv->mm.phys_objs[id - 1]; |
4821 | obj->phys_obj->cur_obj = obj; | |
71acb5eb | 4822 | |
05394f39 | 4823 | page_count = obj->base.size / PAGE_SIZE; |
71acb5eb DA |
4824 | |
4825 | for (i = 0; i < page_count; i++) { | |
e5281ccd CW |
4826 | struct page *page; |
4827 | char *dst, *src; | |
4828 | ||
5949eac4 | 4829 | page = shmem_read_mapping_page(mapping, i); |
e5281ccd CW |
4830 | if (IS_ERR(page)) |
4831 | return PTR_ERR(page); | |
71acb5eb | 4832 | |
ff75b9bc | 4833 | src = kmap_atomic(page); |
05394f39 | 4834 | dst = obj->phys_obj->handle->vaddr + (i * PAGE_SIZE); |
71acb5eb | 4835 | memcpy(dst, src, PAGE_SIZE); |
3e4d3af5 | 4836 | kunmap_atomic(src); |
71acb5eb | 4837 | |
e5281ccd CW |
4838 | mark_page_accessed(page); |
4839 | page_cache_release(page); | |
4840 | } | |
d78b47b9 | 4841 | |
71acb5eb | 4842 | return 0; |
71acb5eb DA |
4843 | } |
4844 | ||
4845 | static int | |
05394f39 CW |
4846 | i915_gem_phys_pwrite(struct drm_device *dev, |
4847 | struct drm_i915_gem_object *obj, | |
71acb5eb DA |
4848 | struct drm_i915_gem_pwrite *args, |
4849 | struct drm_file *file_priv) | |
4850 | { | |
05394f39 | 4851 | void *vaddr = obj->phys_obj->handle->vaddr + args->offset; |
2bb4629a | 4852 | char __user *user_data = to_user_ptr(args->data_ptr); |
71acb5eb | 4853 | |
b47b30cc CW |
4854 | if (__copy_from_user_inatomic_nocache(vaddr, user_data, args->size)) { |
4855 | unsigned long unwritten; | |
4856 | ||
4857 | /* The physical object once assigned is fixed for the lifetime | |
4858 | * of the obj, so we can safely drop the lock and continue | |
4859 | * to access vaddr. | |
4860 | */ | |
4861 | mutex_unlock(&dev->struct_mutex); | |
4862 | unwritten = copy_from_user(vaddr, user_data, args->size); | |
4863 | mutex_lock(&dev->struct_mutex); | |
4864 | if (unwritten) | |
4865 | return -EFAULT; | |
4866 | } | |
71acb5eb | 4867 | |
e76e9aeb | 4868 | i915_gem_chipset_flush(dev); |
71acb5eb DA |
4869 | return 0; |
4870 | } | |
b962442e | 4871 | |
f787a5f5 | 4872 | void i915_gem_release(struct drm_device *dev, struct drm_file *file) |
b962442e | 4873 | { |
f787a5f5 | 4874 | struct drm_i915_file_private *file_priv = file->driver_priv; |
b962442e | 4875 | |
b29c19b6 CW |
4876 | cancel_delayed_work_sync(&file_priv->mm.idle_work); |
4877 | ||
b962442e EA |
4878 | /* Clean up our request list when the client is going away, so that |
4879 | * later retire_requests won't dereference our soon-to-be-gone | |
4880 | * file_priv. | |
4881 | */ | |
1c25595f | 4882 | spin_lock(&file_priv->mm.lock); |
f787a5f5 CW |
4883 | while (!list_empty(&file_priv->mm.request_list)) { |
4884 | struct drm_i915_gem_request *request; | |
4885 | ||
4886 | request = list_first_entry(&file_priv->mm.request_list, | |
4887 | struct drm_i915_gem_request, | |
4888 | client_list); | |
4889 | list_del(&request->client_list); | |
4890 | request->file_priv = NULL; | |
4891 | } | |
1c25595f | 4892 | spin_unlock(&file_priv->mm.lock); |
b962442e | 4893 | } |
31169714 | 4894 | |
b29c19b6 CW |
4895 | static void |
4896 | i915_gem_file_idle_work_handler(struct work_struct *work) | |
4897 | { | |
4898 | struct drm_i915_file_private *file_priv = | |
4899 | container_of(work, typeof(*file_priv), mm.idle_work.work); | |
4900 | ||
4901 | atomic_set(&file_priv->rps_wait_boost, false); | |
4902 | } | |
4903 | ||
4904 | int i915_gem_open(struct drm_device *dev, struct drm_file *file) | |
4905 | { | |
4906 | struct drm_i915_file_private *file_priv; | |
4907 | ||
4908 | DRM_DEBUG_DRIVER("\n"); | |
4909 | ||
4910 | file_priv = kzalloc(sizeof(*file_priv), GFP_KERNEL); | |
4911 | if (!file_priv) | |
4912 | return -ENOMEM; | |
4913 | ||
4914 | file->driver_priv = file_priv; | |
4915 | file_priv->dev_priv = dev->dev_private; | |
4916 | ||
4917 | spin_lock_init(&file_priv->mm.lock); | |
4918 | INIT_LIST_HEAD(&file_priv->mm.request_list); | |
4919 | INIT_DELAYED_WORK(&file_priv->mm.idle_work, | |
4920 | i915_gem_file_idle_work_handler); | |
4921 | ||
4922 | idr_init(&file_priv->context_idr); | |
4923 | ||
4924 | return 0; | |
4925 | } | |
4926 | ||
5774506f CW |
4927 | static bool mutex_is_locked_by(struct mutex *mutex, struct task_struct *task) |
4928 | { | |
4929 | if (!mutex_is_locked(mutex)) | |
4930 | return false; | |
4931 | ||
4932 | #if defined(CONFIG_SMP) || defined(CONFIG_DEBUG_MUTEXES) | |
4933 | return mutex->owner == task; | |
4934 | #else | |
4935 | /* Since UP may be pre-empted, we cannot assume that we own the lock */ | |
4936 | return false; | |
4937 | #endif | |
4938 | } | |
4939 | ||
7dc19d5a DC |
4940 | static unsigned long |
4941 | i915_gem_inactive_count(struct shrinker *shrinker, struct shrink_control *sc) | |
31169714 | 4942 | { |
17250b71 CW |
4943 | struct drm_i915_private *dev_priv = |
4944 | container_of(shrinker, | |
4945 | struct drm_i915_private, | |
4946 | mm.inactive_shrinker); | |
4947 | struct drm_device *dev = dev_priv->dev; | |
6c085a72 | 4948 | struct drm_i915_gem_object *obj; |
5774506f | 4949 | bool unlock = true; |
7dc19d5a | 4950 | unsigned long count; |
17250b71 | 4951 | |
5774506f CW |
4952 | if (!mutex_trylock(&dev->struct_mutex)) { |
4953 | if (!mutex_is_locked_by(&dev->struct_mutex, current)) | |
d3227046 | 4954 | return 0; |
5774506f | 4955 | |
677feac2 | 4956 | if (dev_priv->mm.shrinker_no_lock_stealing) |
d3227046 | 4957 | return 0; |
677feac2 | 4958 | |
5774506f CW |
4959 | unlock = false; |
4960 | } | |
31169714 | 4961 | |
7dc19d5a | 4962 | count = 0; |
35c20a60 | 4963 | list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) |
a5570178 | 4964 | if (obj->pages_pin_count == 0) |
7dc19d5a | 4965 | count += obj->base.size >> PAGE_SHIFT; |
fcb4a578 BW |
4966 | |
4967 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) { | |
4968 | if (obj->active) | |
4969 | continue; | |
4970 | ||
d7f46fc4 | 4971 | if (!i915_gem_obj_is_pinned(obj) && obj->pages_pin_count == 0) |
7dc19d5a | 4972 | count += obj->base.size >> PAGE_SHIFT; |
fcb4a578 | 4973 | } |
17250b71 | 4974 | |
5774506f CW |
4975 | if (unlock) |
4976 | mutex_unlock(&dev->struct_mutex); | |
d9973b43 | 4977 | |
7dc19d5a | 4978 | return count; |
31169714 | 4979 | } |
a70a3148 BW |
4980 | |
4981 | /* All the new VM stuff */ | |
4982 | unsigned long i915_gem_obj_offset(struct drm_i915_gem_object *o, | |
4983 | struct i915_address_space *vm) | |
4984 | { | |
4985 | struct drm_i915_private *dev_priv = o->base.dev->dev_private; | |
4986 | struct i915_vma *vma; | |
4987 | ||
6f425321 BW |
4988 | if (!dev_priv->mm.aliasing_ppgtt || |
4989 | vm == &dev_priv->mm.aliasing_ppgtt->base) | |
a70a3148 BW |
4990 | vm = &dev_priv->gtt.base; |
4991 | ||
4992 | BUG_ON(list_empty(&o->vma_list)); | |
4993 | list_for_each_entry(vma, &o->vma_list, vma_link) { | |
4994 | if (vma->vm == vm) | |
4995 | return vma->node.start; | |
4996 | ||
4997 | } | |
4998 | return -1; | |
4999 | } | |
5000 | ||
5001 | bool i915_gem_obj_bound(struct drm_i915_gem_object *o, | |
5002 | struct i915_address_space *vm) | |
5003 | { | |
5004 | struct i915_vma *vma; | |
5005 | ||
5006 | list_for_each_entry(vma, &o->vma_list, vma_link) | |
8b9c2b94 | 5007 | if (vma->vm == vm && drm_mm_node_allocated(&vma->node)) |
a70a3148 BW |
5008 | return true; |
5009 | ||
5010 | return false; | |
5011 | } | |
5012 | ||
5013 | bool i915_gem_obj_bound_any(struct drm_i915_gem_object *o) | |
5014 | { | |
5a1d5eb0 | 5015 | struct i915_vma *vma; |
a70a3148 | 5016 | |
5a1d5eb0 CW |
5017 | list_for_each_entry(vma, &o->vma_list, vma_link) |
5018 | if (drm_mm_node_allocated(&vma->node)) | |
a70a3148 BW |
5019 | return true; |
5020 | ||
5021 | return false; | |
5022 | } | |
5023 | ||
5024 | unsigned long i915_gem_obj_size(struct drm_i915_gem_object *o, | |
5025 | struct i915_address_space *vm) | |
5026 | { | |
5027 | struct drm_i915_private *dev_priv = o->base.dev->dev_private; | |
5028 | struct i915_vma *vma; | |
5029 | ||
6f425321 BW |
5030 | if (!dev_priv->mm.aliasing_ppgtt || |
5031 | vm == &dev_priv->mm.aliasing_ppgtt->base) | |
a70a3148 BW |
5032 | vm = &dev_priv->gtt.base; |
5033 | ||
5034 | BUG_ON(list_empty(&o->vma_list)); | |
5035 | ||
5036 | list_for_each_entry(vma, &o->vma_list, vma_link) | |
5037 | if (vma->vm == vm) | |
5038 | return vma->node.size; | |
5039 | ||
5040 | return 0; | |
5041 | } | |
5042 | ||
7dc19d5a DC |
5043 | static unsigned long |
5044 | i915_gem_inactive_scan(struct shrinker *shrinker, struct shrink_control *sc) | |
5045 | { | |
5046 | struct drm_i915_private *dev_priv = | |
5047 | container_of(shrinker, | |
5048 | struct drm_i915_private, | |
5049 | mm.inactive_shrinker); | |
5050 | struct drm_device *dev = dev_priv->dev; | |
7dc19d5a DC |
5051 | unsigned long freed; |
5052 | bool unlock = true; | |
5053 | ||
5054 | if (!mutex_trylock(&dev->struct_mutex)) { | |
5055 | if (!mutex_is_locked_by(&dev->struct_mutex, current)) | |
d3227046 | 5056 | return SHRINK_STOP; |
7dc19d5a DC |
5057 | |
5058 | if (dev_priv->mm.shrinker_no_lock_stealing) | |
d3227046 | 5059 | return SHRINK_STOP; |
7dc19d5a DC |
5060 | |
5061 | unlock = false; | |
5062 | } | |
5063 | ||
d9973b43 CW |
5064 | freed = i915_gem_purge(dev_priv, sc->nr_to_scan); |
5065 | if (freed < sc->nr_to_scan) | |
5066 | freed += __i915_gem_shrink(dev_priv, | |
5067 | sc->nr_to_scan - freed, | |
5068 | false); | |
5069 | if (freed < sc->nr_to_scan) | |
7dc19d5a DC |
5070 | freed += i915_gem_shrink_all(dev_priv); |
5071 | ||
5072 | if (unlock) | |
5073 | mutex_unlock(&dev->struct_mutex); | |
d9973b43 | 5074 | |
7dc19d5a DC |
5075 | return freed; |
5076 | } | |
5c2abbea BW |
5077 | |
5078 | struct i915_vma *i915_gem_obj_to_ggtt(struct drm_i915_gem_object *obj) | |
5079 | { | |
5080 | struct i915_vma *vma; | |
5081 | ||
5082 | if (WARN_ON(list_empty(&obj->vma_list))) | |
5083 | return NULL; | |
5084 | ||
5085 | vma = list_first_entry(&obj->vma_list, typeof(*vma), vma_link); | |
6e164c33 | 5086 | if (vma->vm != obj_to_ggtt(obj)) |
5c2abbea BW |
5087 | return NULL; |
5088 | ||
5089 | return vma; | |
5090 | } |