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Commit | Line | Data |
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673a394b EA |
1 | /* |
2 | * Copyright © 2008 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | * | |
26 | */ | |
27 | ||
760285e7 DH |
28 | #include <drm/drmP.h> |
29 | #include <drm/i915_drm.h> | |
673a394b | 30 | #include "i915_drv.h" |
1c5d22f7 | 31 | #include "i915_trace.h" |
652c393a | 32 | #include "intel_drv.h" |
5949eac4 | 33 | #include <linux/shmem_fs.h> |
5a0e3ad6 | 34 | #include <linux/slab.h> |
673a394b | 35 | #include <linux/swap.h> |
79e53945 | 36 | #include <linux/pci.h> |
1286ff73 | 37 | #include <linux/dma-buf.h> |
673a394b | 38 | |
05394f39 CW |
39 | static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj); |
40 | static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj); | |
88241785 CW |
41 | static __must_check int i915_gem_object_bind_to_gtt(struct drm_i915_gem_object *obj, |
42 | unsigned alignment, | |
86a1ee26 CW |
43 | bool map_and_fenceable, |
44 | bool nonblocking); | |
05394f39 CW |
45 | static int i915_gem_phys_pwrite(struct drm_device *dev, |
46 | struct drm_i915_gem_object *obj, | |
71acb5eb | 47 | struct drm_i915_gem_pwrite *args, |
05394f39 | 48 | struct drm_file *file); |
673a394b | 49 | |
61050808 CW |
50 | static void i915_gem_write_fence(struct drm_device *dev, int reg, |
51 | struct drm_i915_gem_object *obj); | |
52 | static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj, | |
53 | struct drm_i915_fence_reg *fence, | |
54 | bool enable); | |
55 | ||
17250b71 | 56 | static int i915_gem_inactive_shrink(struct shrinker *shrinker, |
1495f230 | 57 | struct shrink_control *sc); |
6c085a72 CW |
58 | static long i915_gem_purge(struct drm_i915_private *dev_priv, long target); |
59 | static void i915_gem_shrink_all(struct drm_i915_private *dev_priv); | |
8c59967c | 60 | static void i915_gem_object_truncate(struct drm_i915_gem_object *obj); |
31169714 | 61 | |
61050808 CW |
62 | static inline void i915_gem_object_fence_lost(struct drm_i915_gem_object *obj) |
63 | { | |
64 | if (obj->tiling_mode) | |
65 | i915_gem_release_mmap(obj); | |
66 | ||
67 | /* As we do not have an associated fence register, we will force | |
68 | * a tiling change if we ever need to acquire one. | |
69 | */ | |
5d82e3e6 | 70 | obj->fence_dirty = false; |
61050808 CW |
71 | obj->fence_reg = I915_FENCE_REG_NONE; |
72 | } | |
73 | ||
73aa808f CW |
74 | /* some bookkeeping */ |
75 | static void i915_gem_info_add_obj(struct drm_i915_private *dev_priv, | |
76 | size_t size) | |
77 | { | |
78 | dev_priv->mm.object_count++; | |
79 | dev_priv->mm.object_memory += size; | |
80 | } | |
81 | ||
82 | static void i915_gem_info_remove_obj(struct drm_i915_private *dev_priv, | |
83 | size_t size) | |
84 | { | |
85 | dev_priv->mm.object_count--; | |
86 | dev_priv->mm.object_memory -= size; | |
87 | } | |
88 | ||
21dd3734 CW |
89 | static int |
90 | i915_gem_wait_for_error(struct drm_device *dev) | |
30dbf0c0 CW |
91 | { |
92 | struct drm_i915_private *dev_priv = dev->dev_private; | |
93 | struct completion *x = &dev_priv->error_completion; | |
94 | unsigned long flags; | |
95 | int ret; | |
96 | ||
97 | if (!atomic_read(&dev_priv->mm.wedged)) | |
98 | return 0; | |
99 | ||
0a6759c6 DV |
100 | /* |
101 | * Only wait 10 seconds for the gpu reset to complete to avoid hanging | |
102 | * userspace. If it takes that long something really bad is going on and | |
103 | * we should simply try to bail out and fail as gracefully as possible. | |
104 | */ | |
105 | ret = wait_for_completion_interruptible_timeout(x, 10*HZ); | |
106 | if (ret == 0) { | |
107 | DRM_ERROR("Timed out waiting for the gpu reset to complete\n"); | |
108 | return -EIO; | |
109 | } else if (ret < 0) { | |
30dbf0c0 | 110 | return ret; |
0a6759c6 | 111 | } |
30dbf0c0 | 112 | |
21dd3734 CW |
113 | if (atomic_read(&dev_priv->mm.wedged)) { |
114 | /* GPU is hung, bump the completion count to account for | |
115 | * the token we just consumed so that we never hit zero and | |
116 | * end up waiting upon a subsequent completion event that | |
117 | * will never happen. | |
118 | */ | |
119 | spin_lock_irqsave(&x->wait.lock, flags); | |
120 | x->done++; | |
121 | spin_unlock_irqrestore(&x->wait.lock, flags); | |
122 | } | |
123 | return 0; | |
30dbf0c0 CW |
124 | } |
125 | ||
54cf91dc | 126 | int i915_mutex_lock_interruptible(struct drm_device *dev) |
76c1dec1 | 127 | { |
76c1dec1 CW |
128 | int ret; |
129 | ||
21dd3734 | 130 | ret = i915_gem_wait_for_error(dev); |
76c1dec1 CW |
131 | if (ret) |
132 | return ret; | |
133 | ||
134 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
135 | if (ret) | |
136 | return ret; | |
137 | ||
23bc5982 | 138 | WARN_ON(i915_verify_lists(dev)); |
76c1dec1 CW |
139 | return 0; |
140 | } | |
30dbf0c0 | 141 | |
7d1c4804 | 142 | static inline bool |
05394f39 | 143 | i915_gem_object_is_inactive(struct drm_i915_gem_object *obj) |
7d1c4804 | 144 | { |
6c085a72 | 145 | return obj->gtt_space && !obj->active; |
7d1c4804 CW |
146 | } |
147 | ||
79e53945 JB |
148 | int |
149 | i915_gem_init_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 150 | struct drm_file *file) |
79e53945 JB |
151 | { |
152 | struct drm_i915_gem_init *args = data; | |
2021746e | 153 | |
7bb6fb8d DV |
154 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
155 | return -ENODEV; | |
156 | ||
2021746e CW |
157 | if (args->gtt_start >= args->gtt_end || |
158 | (args->gtt_end | args->gtt_start) & (PAGE_SIZE - 1)) | |
159 | return -EINVAL; | |
79e53945 | 160 | |
f534bc0b DV |
161 | /* GEM with user mode setting was never supported on ilk and later. */ |
162 | if (INTEL_INFO(dev)->gen >= 5) | |
163 | return -ENODEV; | |
164 | ||
79e53945 | 165 | mutex_lock(&dev->struct_mutex); |
d7e5008f BW |
166 | i915_gem_setup_global_gtt(dev, args->gtt_start, args->gtt_end, |
167 | args->gtt_end); | |
673a394b EA |
168 | mutex_unlock(&dev->struct_mutex); |
169 | ||
2021746e | 170 | return 0; |
673a394b EA |
171 | } |
172 | ||
5a125c3c EA |
173 | int |
174 | i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 175 | struct drm_file *file) |
5a125c3c | 176 | { |
73aa808f | 177 | struct drm_i915_private *dev_priv = dev->dev_private; |
5a125c3c | 178 | struct drm_i915_gem_get_aperture *args = data; |
6299f992 CW |
179 | struct drm_i915_gem_object *obj; |
180 | size_t pinned; | |
5a125c3c | 181 | |
6299f992 | 182 | pinned = 0; |
73aa808f | 183 | mutex_lock(&dev->struct_mutex); |
6c085a72 | 184 | list_for_each_entry(obj, &dev_priv->mm.bound_list, gtt_list) |
1b50247a CW |
185 | if (obj->pin_count) |
186 | pinned += obj->gtt_space->size; | |
73aa808f | 187 | mutex_unlock(&dev->struct_mutex); |
5a125c3c | 188 | |
5d4545ae | 189 | args->aper_size = dev_priv->gtt.total; |
0206e353 | 190 | args->aper_available_size = args->aper_size - pinned; |
6299f992 | 191 | |
5a125c3c EA |
192 | return 0; |
193 | } | |
194 | ||
42dcedd4 CW |
195 | void *i915_gem_object_alloc(struct drm_device *dev) |
196 | { | |
197 | struct drm_i915_private *dev_priv = dev->dev_private; | |
198 | return kmem_cache_alloc(dev_priv->slab, GFP_KERNEL | __GFP_ZERO); | |
199 | } | |
200 | ||
201 | void i915_gem_object_free(struct drm_i915_gem_object *obj) | |
202 | { | |
203 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; | |
204 | kmem_cache_free(dev_priv->slab, obj); | |
205 | } | |
206 | ||
ff72145b DA |
207 | static int |
208 | i915_gem_create(struct drm_file *file, | |
209 | struct drm_device *dev, | |
210 | uint64_t size, | |
211 | uint32_t *handle_p) | |
673a394b | 212 | { |
05394f39 | 213 | struct drm_i915_gem_object *obj; |
a1a2d1d3 PP |
214 | int ret; |
215 | u32 handle; | |
673a394b | 216 | |
ff72145b | 217 | size = roundup(size, PAGE_SIZE); |
8ffc0246 CW |
218 | if (size == 0) |
219 | return -EINVAL; | |
673a394b EA |
220 | |
221 | /* Allocate the new object */ | |
ff72145b | 222 | obj = i915_gem_alloc_object(dev, size); |
673a394b EA |
223 | if (obj == NULL) |
224 | return -ENOMEM; | |
225 | ||
05394f39 | 226 | ret = drm_gem_handle_create(file, &obj->base, &handle); |
1dfd9754 | 227 | if (ret) { |
05394f39 CW |
228 | drm_gem_object_release(&obj->base); |
229 | i915_gem_info_remove_obj(dev->dev_private, obj->base.size); | |
42dcedd4 | 230 | i915_gem_object_free(obj); |
673a394b | 231 | return ret; |
1dfd9754 | 232 | } |
673a394b | 233 | |
202f2fef | 234 | /* drop reference from allocate - handle holds it now */ |
05394f39 | 235 | drm_gem_object_unreference(&obj->base); |
202f2fef CW |
236 | trace_i915_gem_object_create(obj); |
237 | ||
ff72145b | 238 | *handle_p = handle; |
673a394b EA |
239 | return 0; |
240 | } | |
241 | ||
ff72145b DA |
242 | int |
243 | i915_gem_dumb_create(struct drm_file *file, | |
244 | struct drm_device *dev, | |
245 | struct drm_mode_create_dumb *args) | |
246 | { | |
247 | /* have to work out size/pitch and return them */ | |
ed0291fd | 248 | args->pitch = ALIGN(args->width * ((args->bpp + 7) / 8), 64); |
ff72145b DA |
249 | args->size = args->pitch * args->height; |
250 | return i915_gem_create(file, dev, | |
251 | args->size, &args->handle); | |
252 | } | |
253 | ||
254 | int i915_gem_dumb_destroy(struct drm_file *file, | |
255 | struct drm_device *dev, | |
256 | uint32_t handle) | |
257 | { | |
258 | return drm_gem_handle_delete(file, handle); | |
259 | } | |
260 | ||
261 | /** | |
262 | * Creates a new mm object and returns a handle to it. | |
263 | */ | |
264 | int | |
265 | i915_gem_create_ioctl(struct drm_device *dev, void *data, | |
266 | struct drm_file *file) | |
267 | { | |
268 | struct drm_i915_gem_create *args = data; | |
63ed2cb2 | 269 | |
ff72145b DA |
270 | return i915_gem_create(file, dev, |
271 | args->size, &args->handle); | |
272 | } | |
273 | ||
8461d226 DV |
274 | static inline int |
275 | __copy_to_user_swizzled(char __user *cpu_vaddr, | |
276 | const char *gpu_vaddr, int gpu_offset, | |
277 | int length) | |
278 | { | |
279 | int ret, cpu_offset = 0; | |
280 | ||
281 | while (length > 0) { | |
282 | int cacheline_end = ALIGN(gpu_offset + 1, 64); | |
283 | int this_length = min(cacheline_end - gpu_offset, length); | |
284 | int swizzled_gpu_offset = gpu_offset ^ 64; | |
285 | ||
286 | ret = __copy_to_user(cpu_vaddr + cpu_offset, | |
287 | gpu_vaddr + swizzled_gpu_offset, | |
288 | this_length); | |
289 | if (ret) | |
290 | return ret + length; | |
291 | ||
292 | cpu_offset += this_length; | |
293 | gpu_offset += this_length; | |
294 | length -= this_length; | |
295 | } | |
296 | ||
297 | return 0; | |
298 | } | |
299 | ||
8c59967c | 300 | static inline int |
4f0c7cfb BW |
301 | __copy_from_user_swizzled(char *gpu_vaddr, int gpu_offset, |
302 | const char __user *cpu_vaddr, | |
8c59967c DV |
303 | int length) |
304 | { | |
305 | int ret, cpu_offset = 0; | |
306 | ||
307 | while (length > 0) { | |
308 | int cacheline_end = ALIGN(gpu_offset + 1, 64); | |
309 | int this_length = min(cacheline_end - gpu_offset, length); | |
310 | int swizzled_gpu_offset = gpu_offset ^ 64; | |
311 | ||
312 | ret = __copy_from_user(gpu_vaddr + swizzled_gpu_offset, | |
313 | cpu_vaddr + cpu_offset, | |
314 | this_length); | |
315 | if (ret) | |
316 | return ret + length; | |
317 | ||
318 | cpu_offset += this_length; | |
319 | gpu_offset += this_length; | |
320 | length -= this_length; | |
321 | } | |
322 | ||
323 | return 0; | |
324 | } | |
325 | ||
d174bd64 DV |
326 | /* Per-page copy function for the shmem pread fastpath. |
327 | * Flushes invalid cachelines before reading the target if | |
328 | * needs_clflush is set. */ | |
eb01459f | 329 | static int |
d174bd64 DV |
330 | shmem_pread_fast(struct page *page, int shmem_page_offset, int page_length, |
331 | char __user *user_data, | |
332 | bool page_do_bit17_swizzling, bool needs_clflush) | |
333 | { | |
334 | char *vaddr; | |
335 | int ret; | |
336 | ||
e7e58eb5 | 337 | if (unlikely(page_do_bit17_swizzling)) |
d174bd64 DV |
338 | return -EINVAL; |
339 | ||
340 | vaddr = kmap_atomic(page); | |
341 | if (needs_clflush) | |
342 | drm_clflush_virt_range(vaddr + shmem_page_offset, | |
343 | page_length); | |
344 | ret = __copy_to_user_inatomic(user_data, | |
345 | vaddr + shmem_page_offset, | |
346 | page_length); | |
347 | kunmap_atomic(vaddr); | |
348 | ||
f60d7f0c | 349 | return ret ? -EFAULT : 0; |
d174bd64 DV |
350 | } |
351 | ||
23c18c71 DV |
352 | static void |
353 | shmem_clflush_swizzled_range(char *addr, unsigned long length, | |
354 | bool swizzled) | |
355 | { | |
e7e58eb5 | 356 | if (unlikely(swizzled)) { |
23c18c71 DV |
357 | unsigned long start = (unsigned long) addr; |
358 | unsigned long end = (unsigned long) addr + length; | |
359 | ||
360 | /* For swizzling simply ensure that we always flush both | |
361 | * channels. Lame, but simple and it works. Swizzled | |
362 | * pwrite/pread is far from a hotpath - current userspace | |
363 | * doesn't use it at all. */ | |
364 | start = round_down(start, 128); | |
365 | end = round_up(end, 128); | |
366 | ||
367 | drm_clflush_virt_range((void *)start, end - start); | |
368 | } else { | |
369 | drm_clflush_virt_range(addr, length); | |
370 | } | |
371 | ||
372 | } | |
373 | ||
d174bd64 DV |
374 | /* Only difference to the fast-path function is that this can handle bit17 |
375 | * and uses non-atomic copy and kmap functions. */ | |
376 | static int | |
377 | shmem_pread_slow(struct page *page, int shmem_page_offset, int page_length, | |
378 | char __user *user_data, | |
379 | bool page_do_bit17_swizzling, bool needs_clflush) | |
380 | { | |
381 | char *vaddr; | |
382 | int ret; | |
383 | ||
384 | vaddr = kmap(page); | |
385 | if (needs_clflush) | |
23c18c71 DV |
386 | shmem_clflush_swizzled_range(vaddr + shmem_page_offset, |
387 | page_length, | |
388 | page_do_bit17_swizzling); | |
d174bd64 DV |
389 | |
390 | if (page_do_bit17_swizzling) | |
391 | ret = __copy_to_user_swizzled(user_data, | |
392 | vaddr, shmem_page_offset, | |
393 | page_length); | |
394 | else | |
395 | ret = __copy_to_user(user_data, | |
396 | vaddr + shmem_page_offset, | |
397 | page_length); | |
398 | kunmap(page); | |
399 | ||
f60d7f0c | 400 | return ret ? - EFAULT : 0; |
d174bd64 DV |
401 | } |
402 | ||
eb01459f | 403 | static int |
dbf7bff0 DV |
404 | i915_gem_shmem_pread(struct drm_device *dev, |
405 | struct drm_i915_gem_object *obj, | |
406 | struct drm_i915_gem_pread *args, | |
407 | struct drm_file *file) | |
eb01459f | 408 | { |
8461d226 | 409 | char __user *user_data; |
eb01459f | 410 | ssize_t remain; |
8461d226 | 411 | loff_t offset; |
eb2c0c81 | 412 | int shmem_page_offset, page_length, ret = 0; |
8461d226 | 413 | int obj_do_bit17_swizzling, page_do_bit17_swizzling; |
96d79b52 | 414 | int prefaulted = 0; |
8489731c | 415 | int needs_clflush = 0; |
9da3da66 CW |
416 | struct scatterlist *sg; |
417 | int i; | |
eb01459f | 418 | |
8461d226 | 419 | user_data = (char __user *) (uintptr_t) args->data_ptr; |
eb01459f EA |
420 | remain = args->size; |
421 | ||
8461d226 | 422 | obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj); |
eb01459f | 423 | |
8489731c DV |
424 | if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU)) { |
425 | /* If we're not in the cpu read domain, set ourself into the gtt | |
426 | * read domain and manually flush cachelines (if required). This | |
427 | * optimizes for the case when the gpu will dirty the data | |
428 | * anyway again before the next pread happens. */ | |
429 | if (obj->cache_level == I915_CACHE_NONE) | |
430 | needs_clflush = 1; | |
6c085a72 CW |
431 | if (obj->gtt_space) { |
432 | ret = i915_gem_object_set_to_gtt_domain(obj, false); | |
433 | if (ret) | |
434 | return ret; | |
435 | } | |
8489731c | 436 | } |
eb01459f | 437 | |
f60d7f0c CW |
438 | ret = i915_gem_object_get_pages(obj); |
439 | if (ret) | |
440 | return ret; | |
441 | ||
442 | i915_gem_object_pin_pages(obj); | |
443 | ||
8461d226 | 444 | offset = args->offset; |
eb01459f | 445 | |
9da3da66 | 446 | for_each_sg(obj->pages->sgl, sg, obj->pages->nents, i) { |
e5281ccd CW |
447 | struct page *page; |
448 | ||
9da3da66 CW |
449 | if (i < offset >> PAGE_SHIFT) |
450 | continue; | |
451 | ||
452 | if (remain <= 0) | |
453 | break; | |
454 | ||
eb01459f EA |
455 | /* Operation in this page |
456 | * | |
eb01459f | 457 | * shmem_page_offset = offset within page in shmem file |
eb01459f EA |
458 | * page_length = bytes to copy for this page |
459 | */ | |
c8cbbb8b | 460 | shmem_page_offset = offset_in_page(offset); |
eb01459f EA |
461 | page_length = remain; |
462 | if ((shmem_page_offset + page_length) > PAGE_SIZE) | |
463 | page_length = PAGE_SIZE - shmem_page_offset; | |
eb01459f | 464 | |
9da3da66 | 465 | page = sg_page(sg); |
8461d226 DV |
466 | page_do_bit17_swizzling = obj_do_bit17_swizzling && |
467 | (page_to_phys(page) & (1 << 17)) != 0; | |
468 | ||
d174bd64 DV |
469 | ret = shmem_pread_fast(page, shmem_page_offset, page_length, |
470 | user_data, page_do_bit17_swizzling, | |
471 | needs_clflush); | |
472 | if (ret == 0) | |
473 | goto next_page; | |
dbf7bff0 | 474 | |
dbf7bff0 DV |
475 | mutex_unlock(&dev->struct_mutex); |
476 | ||
96d79b52 | 477 | if (!prefaulted) { |
f56f821f | 478 | ret = fault_in_multipages_writeable(user_data, remain); |
96d79b52 DV |
479 | /* Userspace is tricking us, but we've already clobbered |
480 | * its pages with the prefault and promised to write the | |
481 | * data up to the first fault. Hence ignore any errors | |
482 | * and just continue. */ | |
483 | (void)ret; | |
484 | prefaulted = 1; | |
485 | } | |
eb01459f | 486 | |
d174bd64 DV |
487 | ret = shmem_pread_slow(page, shmem_page_offset, page_length, |
488 | user_data, page_do_bit17_swizzling, | |
489 | needs_clflush); | |
eb01459f | 490 | |
dbf7bff0 | 491 | mutex_lock(&dev->struct_mutex); |
f60d7f0c | 492 | |
dbf7bff0 | 493 | next_page: |
e5281ccd | 494 | mark_page_accessed(page); |
e5281ccd | 495 | |
f60d7f0c | 496 | if (ret) |
8461d226 | 497 | goto out; |
8461d226 | 498 | |
eb01459f | 499 | remain -= page_length; |
8461d226 | 500 | user_data += page_length; |
eb01459f EA |
501 | offset += page_length; |
502 | } | |
503 | ||
4f27b75d | 504 | out: |
f60d7f0c CW |
505 | i915_gem_object_unpin_pages(obj); |
506 | ||
eb01459f EA |
507 | return ret; |
508 | } | |
509 | ||
673a394b EA |
510 | /** |
511 | * Reads data from the object referenced by handle. | |
512 | * | |
513 | * On error, the contents of *data are undefined. | |
514 | */ | |
515 | int | |
516 | i915_gem_pread_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 517 | struct drm_file *file) |
673a394b EA |
518 | { |
519 | struct drm_i915_gem_pread *args = data; | |
05394f39 | 520 | struct drm_i915_gem_object *obj; |
35b62a89 | 521 | int ret = 0; |
673a394b | 522 | |
51311d0a CW |
523 | if (args->size == 0) |
524 | return 0; | |
525 | ||
526 | if (!access_ok(VERIFY_WRITE, | |
527 | (char __user *)(uintptr_t)args->data_ptr, | |
528 | args->size)) | |
529 | return -EFAULT; | |
530 | ||
4f27b75d | 531 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 532 | if (ret) |
4f27b75d | 533 | return ret; |
673a394b | 534 | |
05394f39 | 535 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 536 | if (&obj->base == NULL) { |
1d7cfea1 CW |
537 | ret = -ENOENT; |
538 | goto unlock; | |
4f27b75d | 539 | } |
673a394b | 540 | |
7dcd2499 | 541 | /* Bounds check source. */ |
05394f39 CW |
542 | if (args->offset > obj->base.size || |
543 | args->size > obj->base.size - args->offset) { | |
ce9d419d | 544 | ret = -EINVAL; |
35b62a89 | 545 | goto out; |
ce9d419d CW |
546 | } |
547 | ||
1286ff73 DV |
548 | /* prime objects have no backing filp to GEM pread/pwrite |
549 | * pages from. | |
550 | */ | |
551 | if (!obj->base.filp) { | |
552 | ret = -EINVAL; | |
553 | goto out; | |
554 | } | |
555 | ||
db53a302 CW |
556 | trace_i915_gem_object_pread(obj, args->offset, args->size); |
557 | ||
dbf7bff0 | 558 | ret = i915_gem_shmem_pread(dev, obj, args, file); |
673a394b | 559 | |
35b62a89 | 560 | out: |
05394f39 | 561 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 562 | unlock: |
4f27b75d | 563 | mutex_unlock(&dev->struct_mutex); |
eb01459f | 564 | return ret; |
673a394b EA |
565 | } |
566 | ||
0839ccb8 KP |
567 | /* This is the fast write path which cannot handle |
568 | * page faults in the source data | |
9b7530cc | 569 | */ |
0839ccb8 KP |
570 | |
571 | static inline int | |
572 | fast_user_write(struct io_mapping *mapping, | |
573 | loff_t page_base, int page_offset, | |
574 | char __user *user_data, | |
575 | int length) | |
9b7530cc | 576 | { |
4f0c7cfb BW |
577 | void __iomem *vaddr_atomic; |
578 | void *vaddr; | |
0839ccb8 | 579 | unsigned long unwritten; |
9b7530cc | 580 | |
3e4d3af5 | 581 | vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base); |
4f0c7cfb BW |
582 | /* We can use the cpu mem copy function because this is X86. */ |
583 | vaddr = (void __force*)vaddr_atomic + page_offset; | |
584 | unwritten = __copy_from_user_inatomic_nocache(vaddr, | |
0839ccb8 | 585 | user_data, length); |
3e4d3af5 | 586 | io_mapping_unmap_atomic(vaddr_atomic); |
fbd5a26d | 587 | return unwritten; |
0839ccb8 KP |
588 | } |
589 | ||
3de09aa3 EA |
590 | /** |
591 | * This is the fast pwrite path, where we copy the data directly from the | |
592 | * user into the GTT, uncached. | |
593 | */ | |
673a394b | 594 | static int |
05394f39 CW |
595 | i915_gem_gtt_pwrite_fast(struct drm_device *dev, |
596 | struct drm_i915_gem_object *obj, | |
3de09aa3 | 597 | struct drm_i915_gem_pwrite *args, |
05394f39 | 598 | struct drm_file *file) |
673a394b | 599 | { |
0839ccb8 | 600 | drm_i915_private_t *dev_priv = dev->dev_private; |
673a394b | 601 | ssize_t remain; |
0839ccb8 | 602 | loff_t offset, page_base; |
673a394b | 603 | char __user *user_data; |
935aaa69 DV |
604 | int page_offset, page_length, ret; |
605 | ||
86a1ee26 | 606 | ret = i915_gem_object_pin(obj, 0, true, true); |
935aaa69 DV |
607 | if (ret) |
608 | goto out; | |
609 | ||
610 | ret = i915_gem_object_set_to_gtt_domain(obj, true); | |
611 | if (ret) | |
612 | goto out_unpin; | |
613 | ||
614 | ret = i915_gem_object_put_fence(obj); | |
615 | if (ret) | |
616 | goto out_unpin; | |
673a394b EA |
617 | |
618 | user_data = (char __user *) (uintptr_t) args->data_ptr; | |
619 | remain = args->size; | |
673a394b | 620 | |
05394f39 | 621 | offset = obj->gtt_offset + args->offset; |
673a394b EA |
622 | |
623 | while (remain > 0) { | |
624 | /* Operation in this page | |
625 | * | |
0839ccb8 KP |
626 | * page_base = page offset within aperture |
627 | * page_offset = offset within page | |
628 | * page_length = bytes to copy for this page | |
673a394b | 629 | */ |
c8cbbb8b CW |
630 | page_base = offset & PAGE_MASK; |
631 | page_offset = offset_in_page(offset); | |
0839ccb8 KP |
632 | page_length = remain; |
633 | if ((page_offset + remain) > PAGE_SIZE) | |
634 | page_length = PAGE_SIZE - page_offset; | |
635 | ||
0839ccb8 | 636 | /* If we get a fault while copying data, then (presumably) our |
3de09aa3 EA |
637 | * source page isn't available. Return the error and we'll |
638 | * retry in the slow path. | |
0839ccb8 | 639 | */ |
5d4545ae | 640 | if (fast_user_write(dev_priv->gtt.mappable, page_base, |
935aaa69 DV |
641 | page_offset, user_data, page_length)) { |
642 | ret = -EFAULT; | |
643 | goto out_unpin; | |
644 | } | |
673a394b | 645 | |
0839ccb8 KP |
646 | remain -= page_length; |
647 | user_data += page_length; | |
648 | offset += page_length; | |
673a394b | 649 | } |
673a394b | 650 | |
935aaa69 DV |
651 | out_unpin: |
652 | i915_gem_object_unpin(obj); | |
653 | out: | |
3de09aa3 | 654 | return ret; |
673a394b EA |
655 | } |
656 | ||
d174bd64 DV |
657 | /* Per-page copy function for the shmem pwrite fastpath. |
658 | * Flushes invalid cachelines before writing to the target if | |
659 | * needs_clflush_before is set and flushes out any written cachelines after | |
660 | * writing if needs_clflush is set. */ | |
3043c60c | 661 | static int |
d174bd64 DV |
662 | shmem_pwrite_fast(struct page *page, int shmem_page_offset, int page_length, |
663 | char __user *user_data, | |
664 | bool page_do_bit17_swizzling, | |
665 | bool needs_clflush_before, | |
666 | bool needs_clflush_after) | |
673a394b | 667 | { |
d174bd64 | 668 | char *vaddr; |
673a394b | 669 | int ret; |
3de09aa3 | 670 | |
e7e58eb5 | 671 | if (unlikely(page_do_bit17_swizzling)) |
d174bd64 | 672 | return -EINVAL; |
3de09aa3 | 673 | |
d174bd64 DV |
674 | vaddr = kmap_atomic(page); |
675 | if (needs_clflush_before) | |
676 | drm_clflush_virt_range(vaddr + shmem_page_offset, | |
677 | page_length); | |
678 | ret = __copy_from_user_inatomic_nocache(vaddr + shmem_page_offset, | |
679 | user_data, | |
680 | page_length); | |
681 | if (needs_clflush_after) | |
682 | drm_clflush_virt_range(vaddr + shmem_page_offset, | |
683 | page_length); | |
684 | kunmap_atomic(vaddr); | |
3de09aa3 | 685 | |
755d2218 | 686 | return ret ? -EFAULT : 0; |
3de09aa3 EA |
687 | } |
688 | ||
d174bd64 DV |
689 | /* Only difference to the fast-path function is that this can handle bit17 |
690 | * and uses non-atomic copy and kmap functions. */ | |
3043c60c | 691 | static int |
d174bd64 DV |
692 | shmem_pwrite_slow(struct page *page, int shmem_page_offset, int page_length, |
693 | char __user *user_data, | |
694 | bool page_do_bit17_swizzling, | |
695 | bool needs_clflush_before, | |
696 | bool needs_clflush_after) | |
673a394b | 697 | { |
d174bd64 DV |
698 | char *vaddr; |
699 | int ret; | |
e5281ccd | 700 | |
d174bd64 | 701 | vaddr = kmap(page); |
e7e58eb5 | 702 | if (unlikely(needs_clflush_before || page_do_bit17_swizzling)) |
23c18c71 DV |
703 | shmem_clflush_swizzled_range(vaddr + shmem_page_offset, |
704 | page_length, | |
705 | page_do_bit17_swizzling); | |
d174bd64 DV |
706 | if (page_do_bit17_swizzling) |
707 | ret = __copy_from_user_swizzled(vaddr, shmem_page_offset, | |
e5281ccd CW |
708 | user_data, |
709 | page_length); | |
d174bd64 DV |
710 | else |
711 | ret = __copy_from_user(vaddr + shmem_page_offset, | |
712 | user_data, | |
713 | page_length); | |
714 | if (needs_clflush_after) | |
23c18c71 DV |
715 | shmem_clflush_swizzled_range(vaddr + shmem_page_offset, |
716 | page_length, | |
717 | page_do_bit17_swizzling); | |
d174bd64 | 718 | kunmap(page); |
40123c1f | 719 | |
755d2218 | 720 | return ret ? -EFAULT : 0; |
40123c1f EA |
721 | } |
722 | ||
40123c1f | 723 | static int |
e244a443 DV |
724 | i915_gem_shmem_pwrite(struct drm_device *dev, |
725 | struct drm_i915_gem_object *obj, | |
726 | struct drm_i915_gem_pwrite *args, | |
727 | struct drm_file *file) | |
40123c1f | 728 | { |
40123c1f | 729 | ssize_t remain; |
8c59967c DV |
730 | loff_t offset; |
731 | char __user *user_data; | |
eb2c0c81 | 732 | int shmem_page_offset, page_length, ret = 0; |
8c59967c | 733 | int obj_do_bit17_swizzling, page_do_bit17_swizzling; |
e244a443 | 734 | int hit_slowpath = 0; |
58642885 DV |
735 | int needs_clflush_after = 0; |
736 | int needs_clflush_before = 0; | |
9da3da66 CW |
737 | int i; |
738 | struct scatterlist *sg; | |
40123c1f | 739 | |
8c59967c | 740 | user_data = (char __user *) (uintptr_t) args->data_ptr; |
40123c1f EA |
741 | remain = args->size; |
742 | ||
8c59967c | 743 | obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj); |
40123c1f | 744 | |
58642885 DV |
745 | if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) { |
746 | /* If we're not in the cpu write domain, set ourself into the gtt | |
747 | * write domain and manually flush cachelines (if required). This | |
748 | * optimizes for the case when the gpu will use the data | |
749 | * right away and we therefore have to clflush anyway. */ | |
750 | if (obj->cache_level == I915_CACHE_NONE) | |
751 | needs_clflush_after = 1; | |
6c085a72 CW |
752 | if (obj->gtt_space) { |
753 | ret = i915_gem_object_set_to_gtt_domain(obj, true); | |
754 | if (ret) | |
755 | return ret; | |
756 | } | |
58642885 DV |
757 | } |
758 | /* Same trick applies for invalidate partially written cachelines before | |
759 | * writing. */ | |
760 | if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU) | |
761 | && obj->cache_level == I915_CACHE_NONE) | |
762 | needs_clflush_before = 1; | |
763 | ||
755d2218 CW |
764 | ret = i915_gem_object_get_pages(obj); |
765 | if (ret) | |
766 | return ret; | |
767 | ||
768 | i915_gem_object_pin_pages(obj); | |
769 | ||
673a394b | 770 | offset = args->offset; |
05394f39 | 771 | obj->dirty = 1; |
673a394b | 772 | |
9da3da66 | 773 | for_each_sg(obj->pages->sgl, sg, obj->pages->nents, i) { |
e5281ccd | 774 | struct page *page; |
58642885 | 775 | int partial_cacheline_write; |
e5281ccd | 776 | |
9da3da66 CW |
777 | if (i < offset >> PAGE_SHIFT) |
778 | continue; | |
779 | ||
780 | if (remain <= 0) | |
781 | break; | |
782 | ||
40123c1f EA |
783 | /* Operation in this page |
784 | * | |
40123c1f | 785 | * shmem_page_offset = offset within page in shmem file |
40123c1f EA |
786 | * page_length = bytes to copy for this page |
787 | */ | |
c8cbbb8b | 788 | shmem_page_offset = offset_in_page(offset); |
40123c1f EA |
789 | |
790 | page_length = remain; | |
791 | if ((shmem_page_offset + page_length) > PAGE_SIZE) | |
792 | page_length = PAGE_SIZE - shmem_page_offset; | |
40123c1f | 793 | |
58642885 DV |
794 | /* If we don't overwrite a cacheline completely we need to be |
795 | * careful to have up-to-date data by first clflushing. Don't | |
796 | * overcomplicate things and flush the entire patch. */ | |
797 | partial_cacheline_write = needs_clflush_before && | |
798 | ((shmem_page_offset | page_length) | |
799 | & (boot_cpu_data.x86_clflush_size - 1)); | |
800 | ||
9da3da66 | 801 | page = sg_page(sg); |
8c59967c DV |
802 | page_do_bit17_swizzling = obj_do_bit17_swizzling && |
803 | (page_to_phys(page) & (1 << 17)) != 0; | |
804 | ||
d174bd64 DV |
805 | ret = shmem_pwrite_fast(page, shmem_page_offset, page_length, |
806 | user_data, page_do_bit17_swizzling, | |
807 | partial_cacheline_write, | |
808 | needs_clflush_after); | |
809 | if (ret == 0) | |
810 | goto next_page; | |
e244a443 DV |
811 | |
812 | hit_slowpath = 1; | |
e244a443 | 813 | mutex_unlock(&dev->struct_mutex); |
d174bd64 DV |
814 | ret = shmem_pwrite_slow(page, shmem_page_offset, page_length, |
815 | user_data, page_do_bit17_swizzling, | |
816 | partial_cacheline_write, | |
817 | needs_clflush_after); | |
40123c1f | 818 | |
e244a443 | 819 | mutex_lock(&dev->struct_mutex); |
755d2218 | 820 | |
e244a443 | 821 | next_page: |
e5281ccd CW |
822 | set_page_dirty(page); |
823 | mark_page_accessed(page); | |
e5281ccd | 824 | |
755d2218 | 825 | if (ret) |
8c59967c | 826 | goto out; |
8c59967c | 827 | |
40123c1f | 828 | remain -= page_length; |
8c59967c | 829 | user_data += page_length; |
40123c1f | 830 | offset += page_length; |
673a394b EA |
831 | } |
832 | ||
fbd5a26d | 833 | out: |
755d2218 CW |
834 | i915_gem_object_unpin_pages(obj); |
835 | ||
e244a443 | 836 | if (hit_slowpath) { |
8dcf015e DV |
837 | /* |
838 | * Fixup: Flush cpu caches in case we didn't flush the dirty | |
839 | * cachelines in-line while writing and the object moved | |
840 | * out of the cpu write domain while we've dropped the lock. | |
841 | */ | |
842 | if (!needs_clflush_after && | |
843 | obj->base.write_domain != I915_GEM_DOMAIN_CPU) { | |
e244a443 | 844 | i915_gem_clflush_object(obj); |
e76e9aeb | 845 | i915_gem_chipset_flush(dev); |
e244a443 | 846 | } |
8c59967c | 847 | } |
673a394b | 848 | |
58642885 | 849 | if (needs_clflush_after) |
e76e9aeb | 850 | i915_gem_chipset_flush(dev); |
58642885 | 851 | |
40123c1f | 852 | return ret; |
673a394b EA |
853 | } |
854 | ||
855 | /** | |
856 | * Writes data to the object referenced by handle. | |
857 | * | |
858 | * On error, the contents of the buffer that were to be modified are undefined. | |
859 | */ | |
860 | int | |
861 | i915_gem_pwrite_ioctl(struct drm_device *dev, void *data, | |
fbd5a26d | 862 | struct drm_file *file) |
673a394b EA |
863 | { |
864 | struct drm_i915_gem_pwrite *args = data; | |
05394f39 | 865 | struct drm_i915_gem_object *obj; |
51311d0a CW |
866 | int ret; |
867 | ||
868 | if (args->size == 0) | |
869 | return 0; | |
870 | ||
871 | if (!access_ok(VERIFY_READ, | |
872 | (char __user *)(uintptr_t)args->data_ptr, | |
873 | args->size)) | |
874 | return -EFAULT; | |
875 | ||
f56f821f DV |
876 | ret = fault_in_multipages_readable((char __user *)(uintptr_t)args->data_ptr, |
877 | args->size); | |
51311d0a CW |
878 | if (ret) |
879 | return -EFAULT; | |
673a394b | 880 | |
fbd5a26d | 881 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 882 | if (ret) |
fbd5a26d | 883 | return ret; |
1d7cfea1 | 884 | |
05394f39 | 885 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 886 | if (&obj->base == NULL) { |
1d7cfea1 CW |
887 | ret = -ENOENT; |
888 | goto unlock; | |
fbd5a26d | 889 | } |
673a394b | 890 | |
7dcd2499 | 891 | /* Bounds check destination. */ |
05394f39 CW |
892 | if (args->offset > obj->base.size || |
893 | args->size > obj->base.size - args->offset) { | |
ce9d419d | 894 | ret = -EINVAL; |
35b62a89 | 895 | goto out; |
ce9d419d CW |
896 | } |
897 | ||
1286ff73 DV |
898 | /* prime objects have no backing filp to GEM pread/pwrite |
899 | * pages from. | |
900 | */ | |
901 | if (!obj->base.filp) { | |
902 | ret = -EINVAL; | |
903 | goto out; | |
904 | } | |
905 | ||
db53a302 CW |
906 | trace_i915_gem_object_pwrite(obj, args->offset, args->size); |
907 | ||
935aaa69 | 908 | ret = -EFAULT; |
673a394b EA |
909 | /* We can only do the GTT pwrite on untiled buffers, as otherwise |
910 | * it would end up going through the fenced access, and we'll get | |
911 | * different detiling behavior between reading and writing. | |
912 | * pread/pwrite currently are reading and writing from the CPU | |
913 | * perspective, requiring manual detiling by the client. | |
914 | */ | |
5c0480f2 | 915 | if (obj->phys_obj) { |
fbd5a26d | 916 | ret = i915_gem_phys_pwrite(dev, obj, args, file); |
5c0480f2 DV |
917 | goto out; |
918 | } | |
919 | ||
86a1ee26 | 920 | if (obj->cache_level == I915_CACHE_NONE && |
c07496fa | 921 | obj->tiling_mode == I915_TILING_NONE && |
5c0480f2 | 922 | obj->base.write_domain != I915_GEM_DOMAIN_CPU) { |
fbd5a26d | 923 | ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file); |
935aaa69 DV |
924 | /* Note that the gtt paths might fail with non-page-backed user |
925 | * pointers (e.g. gtt mappings when moving data between | |
926 | * textures). Fallback to the shmem path in that case. */ | |
fbd5a26d | 927 | } |
673a394b | 928 | |
86a1ee26 | 929 | if (ret == -EFAULT || ret == -ENOSPC) |
935aaa69 | 930 | ret = i915_gem_shmem_pwrite(dev, obj, args, file); |
5c0480f2 | 931 | |
35b62a89 | 932 | out: |
05394f39 | 933 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 934 | unlock: |
fbd5a26d | 935 | mutex_unlock(&dev->struct_mutex); |
673a394b EA |
936 | return ret; |
937 | } | |
938 | ||
b361237b CW |
939 | int |
940 | i915_gem_check_wedge(struct drm_i915_private *dev_priv, | |
941 | bool interruptible) | |
942 | { | |
943 | if (atomic_read(&dev_priv->mm.wedged)) { | |
944 | struct completion *x = &dev_priv->error_completion; | |
945 | bool recovery_complete; | |
946 | unsigned long flags; | |
947 | ||
948 | /* Give the error handler a chance to run. */ | |
949 | spin_lock_irqsave(&x->wait.lock, flags); | |
950 | recovery_complete = x->done > 0; | |
951 | spin_unlock_irqrestore(&x->wait.lock, flags); | |
952 | ||
953 | /* Non-interruptible callers can't handle -EAGAIN, hence return | |
954 | * -EIO unconditionally for these. */ | |
955 | if (!interruptible) | |
956 | return -EIO; | |
957 | ||
958 | /* Recovery complete, but still wedged means reset failure. */ | |
959 | if (recovery_complete) | |
960 | return -EIO; | |
961 | ||
962 | return -EAGAIN; | |
963 | } | |
964 | ||
965 | return 0; | |
966 | } | |
967 | ||
968 | /* | |
969 | * Compare seqno against outstanding lazy request. Emit a request if they are | |
970 | * equal. | |
971 | */ | |
972 | static int | |
973 | i915_gem_check_olr(struct intel_ring_buffer *ring, u32 seqno) | |
974 | { | |
975 | int ret; | |
976 | ||
977 | BUG_ON(!mutex_is_locked(&ring->dev->struct_mutex)); | |
978 | ||
979 | ret = 0; | |
980 | if (seqno == ring->outstanding_lazy_request) | |
981 | ret = i915_add_request(ring, NULL, NULL); | |
982 | ||
983 | return ret; | |
984 | } | |
985 | ||
986 | /** | |
987 | * __wait_seqno - wait until execution of seqno has finished | |
988 | * @ring: the ring expected to report seqno | |
989 | * @seqno: duh! | |
990 | * @interruptible: do an interruptible wait (normally yes) | |
991 | * @timeout: in - how long to wait (NULL forever); out - how much time remaining | |
992 | * | |
993 | * Returns 0 if the seqno was found within the alloted time. Else returns the | |
994 | * errno with remaining time filled in timeout argument. | |
995 | */ | |
996 | static int __wait_seqno(struct intel_ring_buffer *ring, u32 seqno, | |
997 | bool interruptible, struct timespec *timeout) | |
998 | { | |
999 | drm_i915_private_t *dev_priv = ring->dev->dev_private; | |
1000 | struct timespec before, now, wait_time={1,0}; | |
1001 | unsigned long timeout_jiffies; | |
1002 | long end; | |
1003 | bool wait_forever = true; | |
1004 | int ret; | |
1005 | ||
1006 | if (i915_seqno_passed(ring->get_seqno(ring, true), seqno)) | |
1007 | return 0; | |
1008 | ||
1009 | trace_i915_gem_request_wait_begin(ring, seqno); | |
1010 | ||
1011 | if (timeout != NULL) { | |
1012 | wait_time = *timeout; | |
1013 | wait_forever = false; | |
1014 | } | |
1015 | ||
1016 | timeout_jiffies = timespec_to_jiffies(&wait_time); | |
1017 | ||
1018 | if (WARN_ON(!ring->irq_get(ring))) | |
1019 | return -ENODEV; | |
1020 | ||
1021 | /* Record current time in case interrupted by signal, or wedged * */ | |
1022 | getrawmonotonic(&before); | |
1023 | ||
1024 | #define EXIT_COND \ | |
1025 | (i915_seqno_passed(ring->get_seqno(ring, false), seqno) || \ | |
1026 | atomic_read(&dev_priv->mm.wedged)) | |
1027 | do { | |
1028 | if (interruptible) | |
1029 | end = wait_event_interruptible_timeout(ring->irq_queue, | |
1030 | EXIT_COND, | |
1031 | timeout_jiffies); | |
1032 | else | |
1033 | end = wait_event_timeout(ring->irq_queue, EXIT_COND, | |
1034 | timeout_jiffies); | |
1035 | ||
1036 | ret = i915_gem_check_wedge(dev_priv, interruptible); | |
1037 | if (ret) | |
1038 | end = ret; | |
1039 | } while (end == 0 && wait_forever); | |
1040 | ||
1041 | getrawmonotonic(&now); | |
1042 | ||
1043 | ring->irq_put(ring); | |
1044 | trace_i915_gem_request_wait_end(ring, seqno); | |
1045 | #undef EXIT_COND | |
1046 | ||
1047 | if (timeout) { | |
1048 | struct timespec sleep_time = timespec_sub(now, before); | |
1049 | *timeout = timespec_sub(*timeout, sleep_time); | |
1050 | } | |
1051 | ||
1052 | switch (end) { | |
1053 | case -EIO: | |
1054 | case -EAGAIN: /* Wedged */ | |
1055 | case -ERESTARTSYS: /* Signal */ | |
1056 | return (int)end; | |
1057 | case 0: /* Timeout */ | |
1058 | if (timeout) | |
1059 | set_normalized_timespec(timeout, 0, 0); | |
1060 | return -ETIME; | |
1061 | default: /* Completed */ | |
1062 | WARN_ON(end < 0); /* We're not aware of other errors */ | |
1063 | return 0; | |
1064 | } | |
1065 | } | |
1066 | ||
1067 | /** | |
1068 | * Waits for a sequence number to be signaled, and cleans up the | |
1069 | * request and object lists appropriately for that event. | |
1070 | */ | |
1071 | int | |
1072 | i915_wait_seqno(struct intel_ring_buffer *ring, uint32_t seqno) | |
1073 | { | |
1074 | struct drm_device *dev = ring->dev; | |
1075 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1076 | bool interruptible = dev_priv->mm.interruptible; | |
1077 | int ret; | |
1078 | ||
1079 | BUG_ON(!mutex_is_locked(&dev->struct_mutex)); | |
1080 | BUG_ON(seqno == 0); | |
1081 | ||
1082 | ret = i915_gem_check_wedge(dev_priv, interruptible); | |
1083 | if (ret) | |
1084 | return ret; | |
1085 | ||
1086 | ret = i915_gem_check_olr(ring, seqno); | |
1087 | if (ret) | |
1088 | return ret; | |
1089 | ||
1090 | return __wait_seqno(ring, seqno, interruptible, NULL); | |
1091 | } | |
1092 | ||
1093 | /** | |
1094 | * Ensures that all rendering to the object has completed and the object is | |
1095 | * safe to unbind from the GTT or access from the CPU. | |
1096 | */ | |
1097 | static __must_check int | |
1098 | i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj, | |
1099 | bool readonly) | |
1100 | { | |
1101 | struct intel_ring_buffer *ring = obj->ring; | |
1102 | u32 seqno; | |
1103 | int ret; | |
1104 | ||
1105 | seqno = readonly ? obj->last_write_seqno : obj->last_read_seqno; | |
1106 | if (seqno == 0) | |
1107 | return 0; | |
1108 | ||
1109 | ret = i915_wait_seqno(ring, seqno); | |
1110 | if (ret) | |
1111 | return ret; | |
1112 | ||
1113 | i915_gem_retire_requests_ring(ring); | |
1114 | ||
1115 | /* Manually manage the write flush as we may have not yet | |
1116 | * retired the buffer. | |
1117 | */ | |
1118 | if (obj->last_write_seqno && | |
1119 | i915_seqno_passed(seqno, obj->last_write_seqno)) { | |
1120 | obj->last_write_seqno = 0; | |
1121 | obj->base.write_domain &= ~I915_GEM_GPU_DOMAINS; | |
1122 | } | |
1123 | ||
1124 | return 0; | |
1125 | } | |
1126 | ||
3236f57a CW |
1127 | /* A nonblocking variant of the above wait. This is a highly dangerous routine |
1128 | * as the object state may change during this call. | |
1129 | */ | |
1130 | static __must_check int | |
1131 | i915_gem_object_wait_rendering__nonblocking(struct drm_i915_gem_object *obj, | |
1132 | bool readonly) | |
1133 | { | |
1134 | struct drm_device *dev = obj->base.dev; | |
1135 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1136 | struct intel_ring_buffer *ring = obj->ring; | |
1137 | u32 seqno; | |
1138 | int ret; | |
1139 | ||
1140 | BUG_ON(!mutex_is_locked(&dev->struct_mutex)); | |
1141 | BUG_ON(!dev_priv->mm.interruptible); | |
1142 | ||
1143 | seqno = readonly ? obj->last_write_seqno : obj->last_read_seqno; | |
1144 | if (seqno == 0) | |
1145 | return 0; | |
1146 | ||
1147 | ret = i915_gem_check_wedge(dev_priv, true); | |
1148 | if (ret) | |
1149 | return ret; | |
1150 | ||
1151 | ret = i915_gem_check_olr(ring, seqno); | |
1152 | if (ret) | |
1153 | return ret; | |
1154 | ||
1155 | mutex_unlock(&dev->struct_mutex); | |
1156 | ret = __wait_seqno(ring, seqno, true, NULL); | |
1157 | mutex_lock(&dev->struct_mutex); | |
1158 | ||
1159 | i915_gem_retire_requests_ring(ring); | |
1160 | ||
1161 | /* Manually manage the write flush as we may have not yet | |
1162 | * retired the buffer. | |
1163 | */ | |
1164 | if (obj->last_write_seqno && | |
1165 | i915_seqno_passed(seqno, obj->last_write_seqno)) { | |
1166 | obj->last_write_seqno = 0; | |
1167 | obj->base.write_domain &= ~I915_GEM_GPU_DOMAINS; | |
1168 | } | |
1169 | ||
1170 | return ret; | |
1171 | } | |
1172 | ||
673a394b | 1173 | /** |
2ef7eeaa EA |
1174 | * Called when user space prepares to use an object with the CPU, either |
1175 | * through the mmap ioctl's mapping or a GTT mapping. | |
673a394b EA |
1176 | */ |
1177 | int | |
1178 | i915_gem_set_domain_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 1179 | struct drm_file *file) |
673a394b EA |
1180 | { |
1181 | struct drm_i915_gem_set_domain *args = data; | |
05394f39 | 1182 | struct drm_i915_gem_object *obj; |
2ef7eeaa EA |
1183 | uint32_t read_domains = args->read_domains; |
1184 | uint32_t write_domain = args->write_domain; | |
673a394b EA |
1185 | int ret; |
1186 | ||
2ef7eeaa | 1187 | /* Only handle setting domains to types used by the CPU. */ |
21d509e3 | 1188 | if (write_domain & I915_GEM_GPU_DOMAINS) |
2ef7eeaa EA |
1189 | return -EINVAL; |
1190 | ||
21d509e3 | 1191 | if (read_domains & I915_GEM_GPU_DOMAINS) |
2ef7eeaa EA |
1192 | return -EINVAL; |
1193 | ||
1194 | /* Having something in the write domain implies it's in the read | |
1195 | * domain, and only that read domain. Enforce that in the request. | |
1196 | */ | |
1197 | if (write_domain != 0 && read_domains != write_domain) | |
1198 | return -EINVAL; | |
1199 | ||
76c1dec1 | 1200 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 1201 | if (ret) |
76c1dec1 | 1202 | return ret; |
1d7cfea1 | 1203 | |
05394f39 | 1204 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 1205 | if (&obj->base == NULL) { |
1d7cfea1 CW |
1206 | ret = -ENOENT; |
1207 | goto unlock; | |
76c1dec1 | 1208 | } |
673a394b | 1209 | |
3236f57a CW |
1210 | /* Try to flush the object off the GPU without holding the lock. |
1211 | * We will repeat the flush holding the lock in the normal manner | |
1212 | * to catch cases where we are gazumped. | |
1213 | */ | |
1214 | ret = i915_gem_object_wait_rendering__nonblocking(obj, !write_domain); | |
1215 | if (ret) | |
1216 | goto unref; | |
1217 | ||
2ef7eeaa EA |
1218 | if (read_domains & I915_GEM_DOMAIN_GTT) { |
1219 | ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0); | |
02354392 EA |
1220 | |
1221 | /* Silently promote "you're not bound, there was nothing to do" | |
1222 | * to success, since the client was just asking us to | |
1223 | * make sure everything was done. | |
1224 | */ | |
1225 | if (ret == -EINVAL) | |
1226 | ret = 0; | |
2ef7eeaa | 1227 | } else { |
e47c68e9 | 1228 | ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0); |
2ef7eeaa EA |
1229 | } |
1230 | ||
3236f57a | 1231 | unref: |
05394f39 | 1232 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 1233 | unlock: |
673a394b EA |
1234 | mutex_unlock(&dev->struct_mutex); |
1235 | return ret; | |
1236 | } | |
1237 | ||
1238 | /** | |
1239 | * Called when user space has done writes to this buffer | |
1240 | */ | |
1241 | int | |
1242 | i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 1243 | struct drm_file *file) |
673a394b EA |
1244 | { |
1245 | struct drm_i915_gem_sw_finish *args = data; | |
05394f39 | 1246 | struct drm_i915_gem_object *obj; |
673a394b EA |
1247 | int ret = 0; |
1248 | ||
76c1dec1 | 1249 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 1250 | if (ret) |
76c1dec1 | 1251 | return ret; |
1d7cfea1 | 1252 | |
05394f39 | 1253 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 1254 | if (&obj->base == NULL) { |
1d7cfea1 CW |
1255 | ret = -ENOENT; |
1256 | goto unlock; | |
673a394b EA |
1257 | } |
1258 | ||
673a394b | 1259 | /* Pinned buffers may be scanout, so flush the cache */ |
05394f39 | 1260 | if (obj->pin_count) |
e47c68e9 EA |
1261 | i915_gem_object_flush_cpu_write_domain(obj); |
1262 | ||
05394f39 | 1263 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 1264 | unlock: |
673a394b EA |
1265 | mutex_unlock(&dev->struct_mutex); |
1266 | return ret; | |
1267 | } | |
1268 | ||
1269 | /** | |
1270 | * Maps the contents of an object, returning the address it is mapped | |
1271 | * into. | |
1272 | * | |
1273 | * While the mapping holds a reference on the contents of the object, it doesn't | |
1274 | * imply a ref on the object itself. | |
1275 | */ | |
1276 | int | |
1277 | i915_gem_mmap_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 1278 | struct drm_file *file) |
673a394b EA |
1279 | { |
1280 | struct drm_i915_gem_mmap *args = data; | |
1281 | struct drm_gem_object *obj; | |
673a394b EA |
1282 | unsigned long addr; |
1283 | ||
05394f39 | 1284 | obj = drm_gem_object_lookup(dev, file, args->handle); |
673a394b | 1285 | if (obj == NULL) |
bf79cb91 | 1286 | return -ENOENT; |
673a394b | 1287 | |
1286ff73 DV |
1288 | /* prime objects have no backing filp to GEM mmap |
1289 | * pages from. | |
1290 | */ | |
1291 | if (!obj->filp) { | |
1292 | drm_gem_object_unreference_unlocked(obj); | |
1293 | return -EINVAL; | |
1294 | } | |
1295 | ||
6be5ceb0 | 1296 | addr = vm_mmap(obj->filp, 0, args->size, |
673a394b EA |
1297 | PROT_READ | PROT_WRITE, MAP_SHARED, |
1298 | args->offset); | |
bc9025bd | 1299 | drm_gem_object_unreference_unlocked(obj); |
673a394b EA |
1300 | if (IS_ERR((void *)addr)) |
1301 | return addr; | |
1302 | ||
1303 | args->addr_ptr = (uint64_t) addr; | |
1304 | ||
1305 | return 0; | |
1306 | } | |
1307 | ||
de151cf6 JB |
1308 | /** |
1309 | * i915_gem_fault - fault a page into the GTT | |
1310 | * vma: VMA in question | |
1311 | * vmf: fault info | |
1312 | * | |
1313 | * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped | |
1314 | * from userspace. The fault handler takes care of binding the object to | |
1315 | * the GTT (if needed), allocating and programming a fence register (again, | |
1316 | * only if needed based on whether the old reg is still valid or the object | |
1317 | * is tiled) and inserting a new PTE into the faulting process. | |
1318 | * | |
1319 | * Note that the faulting process may involve evicting existing objects | |
1320 | * from the GTT and/or fence registers to make room. So performance may | |
1321 | * suffer if the GTT working set is large or there are few fence registers | |
1322 | * left. | |
1323 | */ | |
1324 | int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf) | |
1325 | { | |
05394f39 CW |
1326 | struct drm_i915_gem_object *obj = to_intel_bo(vma->vm_private_data); |
1327 | struct drm_device *dev = obj->base.dev; | |
7d1c4804 | 1328 | drm_i915_private_t *dev_priv = dev->dev_private; |
de151cf6 JB |
1329 | pgoff_t page_offset; |
1330 | unsigned long pfn; | |
1331 | int ret = 0; | |
0f973f27 | 1332 | bool write = !!(vmf->flags & FAULT_FLAG_WRITE); |
de151cf6 JB |
1333 | |
1334 | /* We don't use vmf->pgoff since that has the fake offset */ | |
1335 | page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >> | |
1336 | PAGE_SHIFT; | |
1337 | ||
d9bc7e9f CW |
1338 | ret = i915_mutex_lock_interruptible(dev); |
1339 | if (ret) | |
1340 | goto out; | |
a00b10c3 | 1341 | |
db53a302 CW |
1342 | trace_i915_gem_object_fault(obj, page_offset, true, write); |
1343 | ||
eb119bd6 CW |
1344 | /* Access to snoopable pages through the GTT is incoherent. */ |
1345 | if (obj->cache_level != I915_CACHE_NONE && !HAS_LLC(dev)) { | |
1346 | ret = -EINVAL; | |
1347 | goto unlock; | |
1348 | } | |
1349 | ||
d9bc7e9f | 1350 | /* Now bind it into the GTT if needed */ |
c9839303 CW |
1351 | ret = i915_gem_object_pin(obj, 0, true, false); |
1352 | if (ret) | |
1353 | goto unlock; | |
4a684a41 | 1354 | |
c9839303 CW |
1355 | ret = i915_gem_object_set_to_gtt_domain(obj, write); |
1356 | if (ret) | |
1357 | goto unpin; | |
74898d7e | 1358 | |
06d98131 | 1359 | ret = i915_gem_object_get_fence(obj); |
d9e86c0e | 1360 | if (ret) |
c9839303 | 1361 | goto unpin; |
7d1c4804 | 1362 | |
6299f992 CW |
1363 | obj->fault_mappable = true; |
1364 | ||
5d4545ae | 1365 | pfn = ((dev_priv->gtt.mappable_base + obj->gtt_offset) >> PAGE_SHIFT) + |
de151cf6 JB |
1366 | page_offset; |
1367 | ||
1368 | /* Finally, remap it using the new GTT offset */ | |
1369 | ret = vm_insert_pfn(vma, (unsigned long)vmf->virtual_address, pfn); | |
c9839303 CW |
1370 | unpin: |
1371 | i915_gem_object_unpin(obj); | |
c715089f | 1372 | unlock: |
de151cf6 | 1373 | mutex_unlock(&dev->struct_mutex); |
d9bc7e9f | 1374 | out: |
de151cf6 | 1375 | switch (ret) { |
d9bc7e9f | 1376 | case -EIO: |
a9340cca DV |
1377 | /* If this -EIO is due to a gpu hang, give the reset code a |
1378 | * chance to clean up the mess. Otherwise return the proper | |
1379 | * SIGBUS. */ | |
1380 | if (!atomic_read(&dev_priv->mm.wedged)) | |
1381 | return VM_FAULT_SIGBUS; | |
045e769a | 1382 | case -EAGAIN: |
d9bc7e9f CW |
1383 | /* Give the error handler a chance to run and move the |
1384 | * objects off the GPU active list. Next time we service the | |
1385 | * fault, we should be able to transition the page into the | |
1386 | * GTT without touching the GPU (and so avoid further | |
1387 | * EIO/EGAIN). If the GPU is wedged, then there is no issue | |
1388 | * with coherency, just lost writes. | |
1389 | */ | |
045e769a | 1390 | set_need_resched(); |
c715089f CW |
1391 | case 0: |
1392 | case -ERESTARTSYS: | |
bed636ab | 1393 | case -EINTR: |
e79e0fe3 DR |
1394 | case -EBUSY: |
1395 | /* | |
1396 | * EBUSY is ok: this just means that another thread | |
1397 | * already did the job. | |
1398 | */ | |
c715089f | 1399 | return VM_FAULT_NOPAGE; |
de151cf6 | 1400 | case -ENOMEM: |
de151cf6 | 1401 | return VM_FAULT_OOM; |
a7c2e1aa DV |
1402 | case -ENOSPC: |
1403 | return VM_FAULT_SIGBUS; | |
de151cf6 | 1404 | default: |
a7c2e1aa | 1405 | WARN_ONCE(ret, "unhandled error in i915_gem_fault: %i\n", ret); |
c715089f | 1406 | return VM_FAULT_SIGBUS; |
de151cf6 JB |
1407 | } |
1408 | } | |
1409 | ||
901782b2 CW |
1410 | /** |
1411 | * i915_gem_release_mmap - remove physical page mappings | |
1412 | * @obj: obj in question | |
1413 | * | |
af901ca1 | 1414 | * Preserve the reservation of the mmapping with the DRM core code, but |
901782b2 CW |
1415 | * relinquish ownership of the pages back to the system. |
1416 | * | |
1417 | * It is vital that we remove the page mapping if we have mapped a tiled | |
1418 | * object through the GTT and then lose the fence register due to | |
1419 | * resource pressure. Similarly if the object has been moved out of the | |
1420 | * aperture, than pages mapped into userspace must be revoked. Removing the | |
1421 | * mapping will then trigger a page fault on the next user access, allowing | |
1422 | * fixup by i915_gem_fault(). | |
1423 | */ | |
d05ca301 | 1424 | void |
05394f39 | 1425 | i915_gem_release_mmap(struct drm_i915_gem_object *obj) |
901782b2 | 1426 | { |
6299f992 CW |
1427 | if (!obj->fault_mappable) |
1428 | return; | |
901782b2 | 1429 | |
f6e47884 CW |
1430 | if (obj->base.dev->dev_mapping) |
1431 | unmap_mapping_range(obj->base.dev->dev_mapping, | |
1432 | (loff_t)obj->base.map_list.hash.key<<PAGE_SHIFT, | |
1433 | obj->base.size, 1); | |
fb7d516a | 1434 | |
6299f992 | 1435 | obj->fault_mappable = false; |
901782b2 CW |
1436 | } |
1437 | ||
0fa87796 | 1438 | uint32_t |
e28f8711 | 1439 | i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode) |
92b88aeb | 1440 | { |
e28f8711 | 1441 | uint32_t gtt_size; |
92b88aeb CW |
1442 | |
1443 | if (INTEL_INFO(dev)->gen >= 4 || | |
e28f8711 CW |
1444 | tiling_mode == I915_TILING_NONE) |
1445 | return size; | |
92b88aeb CW |
1446 | |
1447 | /* Previous chips need a power-of-two fence region when tiling */ | |
1448 | if (INTEL_INFO(dev)->gen == 3) | |
e28f8711 | 1449 | gtt_size = 1024*1024; |
92b88aeb | 1450 | else |
e28f8711 | 1451 | gtt_size = 512*1024; |
92b88aeb | 1452 | |
e28f8711 CW |
1453 | while (gtt_size < size) |
1454 | gtt_size <<= 1; | |
92b88aeb | 1455 | |
e28f8711 | 1456 | return gtt_size; |
92b88aeb CW |
1457 | } |
1458 | ||
de151cf6 JB |
1459 | /** |
1460 | * i915_gem_get_gtt_alignment - return required GTT alignment for an object | |
1461 | * @obj: object to check | |
1462 | * | |
1463 | * Return the required GTT alignment for an object, taking into account | |
5e783301 | 1464 | * potential fence register mapping. |
de151cf6 | 1465 | */ |
d865110c ID |
1466 | uint32_t |
1467 | i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size, | |
1468 | int tiling_mode, bool fenced) | |
de151cf6 | 1469 | { |
de151cf6 JB |
1470 | /* |
1471 | * Minimum alignment is 4k (GTT page size), but might be greater | |
1472 | * if a fence register is needed for the object. | |
1473 | */ | |
d865110c | 1474 | if (INTEL_INFO(dev)->gen >= 4 || (!fenced && IS_G33(dev)) || |
e28f8711 | 1475 | tiling_mode == I915_TILING_NONE) |
de151cf6 JB |
1476 | return 4096; |
1477 | ||
a00b10c3 CW |
1478 | /* |
1479 | * Previous chips need to be aligned to the size of the smallest | |
1480 | * fence register that can contain the object. | |
1481 | */ | |
e28f8711 | 1482 | return i915_gem_get_gtt_size(dev, size, tiling_mode); |
a00b10c3 CW |
1483 | } |
1484 | ||
d8cb5086 CW |
1485 | static int i915_gem_object_create_mmap_offset(struct drm_i915_gem_object *obj) |
1486 | { | |
1487 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; | |
1488 | int ret; | |
1489 | ||
1490 | if (obj->base.map_list.map) | |
1491 | return 0; | |
1492 | ||
da494d7c DV |
1493 | dev_priv->mm.shrinker_no_lock_stealing = true; |
1494 | ||
d8cb5086 CW |
1495 | ret = drm_gem_create_mmap_offset(&obj->base); |
1496 | if (ret != -ENOSPC) | |
da494d7c | 1497 | goto out; |
d8cb5086 CW |
1498 | |
1499 | /* Badly fragmented mmap space? The only way we can recover | |
1500 | * space is by destroying unwanted objects. We can't randomly release | |
1501 | * mmap_offsets as userspace expects them to be persistent for the | |
1502 | * lifetime of the objects. The closest we can is to release the | |
1503 | * offsets on purgeable objects by truncating it and marking it purged, | |
1504 | * which prevents userspace from ever using that object again. | |
1505 | */ | |
1506 | i915_gem_purge(dev_priv, obj->base.size >> PAGE_SHIFT); | |
1507 | ret = drm_gem_create_mmap_offset(&obj->base); | |
1508 | if (ret != -ENOSPC) | |
da494d7c | 1509 | goto out; |
d8cb5086 CW |
1510 | |
1511 | i915_gem_shrink_all(dev_priv); | |
da494d7c DV |
1512 | ret = drm_gem_create_mmap_offset(&obj->base); |
1513 | out: | |
1514 | dev_priv->mm.shrinker_no_lock_stealing = false; | |
1515 | ||
1516 | return ret; | |
d8cb5086 CW |
1517 | } |
1518 | ||
1519 | static void i915_gem_object_free_mmap_offset(struct drm_i915_gem_object *obj) | |
1520 | { | |
1521 | if (!obj->base.map_list.map) | |
1522 | return; | |
1523 | ||
1524 | drm_gem_free_mmap_offset(&obj->base); | |
1525 | } | |
1526 | ||
de151cf6 | 1527 | int |
ff72145b DA |
1528 | i915_gem_mmap_gtt(struct drm_file *file, |
1529 | struct drm_device *dev, | |
1530 | uint32_t handle, | |
1531 | uint64_t *offset) | |
de151cf6 | 1532 | { |
da761a6e | 1533 | struct drm_i915_private *dev_priv = dev->dev_private; |
05394f39 | 1534 | struct drm_i915_gem_object *obj; |
de151cf6 JB |
1535 | int ret; |
1536 | ||
76c1dec1 | 1537 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 1538 | if (ret) |
76c1dec1 | 1539 | return ret; |
de151cf6 | 1540 | |
ff72145b | 1541 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle)); |
c8725226 | 1542 | if (&obj->base == NULL) { |
1d7cfea1 CW |
1543 | ret = -ENOENT; |
1544 | goto unlock; | |
1545 | } | |
de151cf6 | 1546 | |
5d4545ae | 1547 | if (obj->base.size > dev_priv->gtt.mappable_end) { |
da761a6e | 1548 | ret = -E2BIG; |
ff56b0bc | 1549 | goto out; |
da761a6e CW |
1550 | } |
1551 | ||
05394f39 | 1552 | if (obj->madv != I915_MADV_WILLNEED) { |
ab18282d | 1553 | DRM_ERROR("Attempting to mmap a purgeable buffer\n"); |
1d7cfea1 CW |
1554 | ret = -EINVAL; |
1555 | goto out; | |
ab18282d CW |
1556 | } |
1557 | ||
d8cb5086 CW |
1558 | ret = i915_gem_object_create_mmap_offset(obj); |
1559 | if (ret) | |
1560 | goto out; | |
de151cf6 | 1561 | |
ff72145b | 1562 | *offset = (u64)obj->base.map_list.hash.key << PAGE_SHIFT; |
de151cf6 | 1563 | |
1d7cfea1 | 1564 | out: |
05394f39 | 1565 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 1566 | unlock: |
de151cf6 | 1567 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 1568 | return ret; |
de151cf6 JB |
1569 | } |
1570 | ||
ff72145b DA |
1571 | /** |
1572 | * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing | |
1573 | * @dev: DRM device | |
1574 | * @data: GTT mapping ioctl data | |
1575 | * @file: GEM object info | |
1576 | * | |
1577 | * Simply returns the fake offset to userspace so it can mmap it. | |
1578 | * The mmap call will end up in drm_gem_mmap(), which will set things | |
1579 | * up so we can get faults in the handler above. | |
1580 | * | |
1581 | * The fault handler will take care of binding the object into the GTT | |
1582 | * (since it may have been evicted to make room for something), allocating | |
1583 | * a fence register, and mapping the appropriate aperture address into | |
1584 | * userspace. | |
1585 | */ | |
1586 | int | |
1587 | i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data, | |
1588 | struct drm_file *file) | |
1589 | { | |
1590 | struct drm_i915_gem_mmap_gtt *args = data; | |
1591 | ||
ff72145b DA |
1592 | return i915_gem_mmap_gtt(file, dev, args->handle, &args->offset); |
1593 | } | |
1594 | ||
225067ee DV |
1595 | /* Immediately discard the backing storage */ |
1596 | static void | |
1597 | i915_gem_object_truncate(struct drm_i915_gem_object *obj) | |
e5281ccd | 1598 | { |
e5281ccd | 1599 | struct inode *inode; |
e5281ccd | 1600 | |
4d6294bf | 1601 | i915_gem_object_free_mmap_offset(obj); |
1286ff73 | 1602 | |
4d6294bf CW |
1603 | if (obj->base.filp == NULL) |
1604 | return; | |
e5281ccd | 1605 | |
225067ee DV |
1606 | /* Our goal here is to return as much of the memory as |
1607 | * is possible back to the system as we are called from OOM. | |
1608 | * To do this we must instruct the shmfs to drop all of its | |
1609 | * backing pages, *now*. | |
1610 | */ | |
05394f39 | 1611 | inode = obj->base.filp->f_path.dentry->d_inode; |
225067ee | 1612 | shmem_truncate_range(inode, 0, (loff_t)-1); |
e5281ccd | 1613 | |
225067ee DV |
1614 | obj->madv = __I915_MADV_PURGED; |
1615 | } | |
e5281ccd | 1616 | |
225067ee DV |
1617 | static inline int |
1618 | i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj) | |
1619 | { | |
1620 | return obj->madv == I915_MADV_DONTNEED; | |
e5281ccd CW |
1621 | } |
1622 | ||
5cdf5881 | 1623 | static void |
05394f39 | 1624 | i915_gem_object_put_pages_gtt(struct drm_i915_gem_object *obj) |
673a394b | 1625 | { |
05394f39 | 1626 | int page_count = obj->base.size / PAGE_SIZE; |
9da3da66 | 1627 | struct scatterlist *sg; |
6c085a72 | 1628 | int ret, i; |
1286ff73 | 1629 | |
05394f39 | 1630 | BUG_ON(obj->madv == __I915_MADV_PURGED); |
673a394b | 1631 | |
6c085a72 CW |
1632 | ret = i915_gem_object_set_to_cpu_domain(obj, true); |
1633 | if (ret) { | |
1634 | /* In the event of a disaster, abandon all caches and | |
1635 | * hope for the best. | |
1636 | */ | |
1637 | WARN_ON(ret != -EIO); | |
1638 | i915_gem_clflush_object(obj); | |
1639 | obj->base.read_domains = obj->base.write_domain = I915_GEM_DOMAIN_CPU; | |
1640 | } | |
1641 | ||
6dacfd2f | 1642 | if (i915_gem_object_needs_bit17_swizzle(obj)) |
280b713b EA |
1643 | i915_gem_object_save_bit_17_swizzle(obj); |
1644 | ||
05394f39 CW |
1645 | if (obj->madv == I915_MADV_DONTNEED) |
1646 | obj->dirty = 0; | |
3ef94daa | 1647 | |
9da3da66 CW |
1648 | for_each_sg(obj->pages->sgl, sg, page_count, i) { |
1649 | struct page *page = sg_page(sg); | |
1650 | ||
05394f39 | 1651 | if (obj->dirty) |
9da3da66 | 1652 | set_page_dirty(page); |
3ef94daa | 1653 | |
05394f39 | 1654 | if (obj->madv == I915_MADV_WILLNEED) |
9da3da66 | 1655 | mark_page_accessed(page); |
3ef94daa | 1656 | |
9da3da66 | 1657 | page_cache_release(page); |
3ef94daa | 1658 | } |
05394f39 | 1659 | obj->dirty = 0; |
673a394b | 1660 | |
9da3da66 CW |
1661 | sg_free_table(obj->pages); |
1662 | kfree(obj->pages); | |
37e680a1 | 1663 | } |
6c085a72 | 1664 | |
dd624afd | 1665 | int |
37e680a1 CW |
1666 | i915_gem_object_put_pages(struct drm_i915_gem_object *obj) |
1667 | { | |
1668 | const struct drm_i915_gem_object_ops *ops = obj->ops; | |
1669 | ||
2f745ad3 | 1670 | if (obj->pages == NULL) |
37e680a1 CW |
1671 | return 0; |
1672 | ||
1673 | BUG_ON(obj->gtt_space); | |
6c085a72 | 1674 | |
a5570178 CW |
1675 | if (obj->pages_pin_count) |
1676 | return -EBUSY; | |
1677 | ||
a2165e31 CW |
1678 | /* ->put_pages might need to allocate memory for the bit17 swizzle |
1679 | * array, hence protect them from being reaped by removing them from gtt | |
1680 | * lists early. */ | |
1681 | list_del(&obj->gtt_list); | |
1682 | ||
37e680a1 | 1683 | ops->put_pages(obj); |
05394f39 | 1684 | obj->pages = NULL; |
37e680a1 | 1685 | |
6c085a72 CW |
1686 | if (i915_gem_object_is_purgeable(obj)) |
1687 | i915_gem_object_truncate(obj); | |
1688 | ||
1689 | return 0; | |
1690 | } | |
1691 | ||
1692 | static long | |
1693 | i915_gem_purge(struct drm_i915_private *dev_priv, long target) | |
1694 | { | |
1695 | struct drm_i915_gem_object *obj, *next; | |
1696 | long count = 0; | |
1697 | ||
1698 | list_for_each_entry_safe(obj, next, | |
1699 | &dev_priv->mm.unbound_list, | |
1700 | gtt_list) { | |
1701 | if (i915_gem_object_is_purgeable(obj) && | |
37e680a1 | 1702 | i915_gem_object_put_pages(obj) == 0) { |
6c085a72 CW |
1703 | count += obj->base.size >> PAGE_SHIFT; |
1704 | if (count >= target) | |
1705 | return count; | |
1706 | } | |
1707 | } | |
1708 | ||
1709 | list_for_each_entry_safe(obj, next, | |
1710 | &dev_priv->mm.inactive_list, | |
1711 | mm_list) { | |
1712 | if (i915_gem_object_is_purgeable(obj) && | |
1713 | i915_gem_object_unbind(obj) == 0 && | |
37e680a1 | 1714 | i915_gem_object_put_pages(obj) == 0) { |
6c085a72 CW |
1715 | count += obj->base.size >> PAGE_SHIFT; |
1716 | if (count >= target) | |
1717 | return count; | |
1718 | } | |
1719 | } | |
1720 | ||
1721 | return count; | |
1722 | } | |
1723 | ||
1724 | static void | |
1725 | i915_gem_shrink_all(struct drm_i915_private *dev_priv) | |
1726 | { | |
1727 | struct drm_i915_gem_object *obj, *next; | |
1728 | ||
1729 | i915_gem_evict_everything(dev_priv->dev); | |
1730 | ||
1731 | list_for_each_entry_safe(obj, next, &dev_priv->mm.unbound_list, gtt_list) | |
37e680a1 | 1732 | i915_gem_object_put_pages(obj); |
225067ee DV |
1733 | } |
1734 | ||
37e680a1 | 1735 | static int |
6c085a72 | 1736 | i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj) |
e5281ccd | 1737 | { |
6c085a72 | 1738 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
e5281ccd CW |
1739 | int page_count, i; |
1740 | struct address_space *mapping; | |
9da3da66 CW |
1741 | struct sg_table *st; |
1742 | struct scatterlist *sg; | |
e5281ccd | 1743 | struct page *page; |
6c085a72 | 1744 | gfp_t gfp; |
e5281ccd | 1745 | |
6c085a72 CW |
1746 | /* Assert that the object is not currently in any GPU domain. As it |
1747 | * wasn't in the GTT, there shouldn't be any way it could have been in | |
1748 | * a GPU cache | |
1749 | */ | |
1750 | BUG_ON(obj->base.read_domains & I915_GEM_GPU_DOMAINS); | |
1751 | BUG_ON(obj->base.write_domain & I915_GEM_GPU_DOMAINS); | |
1752 | ||
9da3da66 CW |
1753 | st = kmalloc(sizeof(*st), GFP_KERNEL); |
1754 | if (st == NULL) | |
1755 | return -ENOMEM; | |
1756 | ||
05394f39 | 1757 | page_count = obj->base.size / PAGE_SIZE; |
9da3da66 CW |
1758 | if (sg_alloc_table(st, page_count, GFP_KERNEL)) { |
1759 | sg_free_table(st); | |
1760 | kfree(st); | |
e5281ccd | 1761 | return -ENOMEM; |
9da3da66 | 1762 | } |
e5281ccd | 1763 | |
9da3da66 CW |
1764 | /* Get the list of pages out of our struct file. They'll be pinned |
1765 | * at this point until we release them. | |
1766 | * | |
1767 | * Fail silently without starting the shrinker | |
1768 | */ | |
6c085a72 CW |
1769 | mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping; |
1770 | gfp = mapping_gfp_mask(mapping); | |
caf49191 | 1771 | gfp |= __GFP_NORETRY | __GFP_NOWARN | __GFP_NO_KSWAPD; |
6c085a72 | 1772 | gfp &= ~(__GFP_IO | __GFP_WAIT); |
9da3da66 | 1773 | for_each_sg(st->sgl, sg, page_count, i) { |
6c085a72 CW |
1774 | page = shmem_read_mapping_page_gfp(mapping, i, gfp); |
1775 | if (IS_ERR(page)) { | |
1776 | i915_gem_purge(dev_priv, page_count); | |
1777 | page = shmem_read_mapping_page_gfp(mapping, i, gfp); | |
1778 | } | |
1779 | if (IS_ERR(page)) { | |
1780 | /* We've tried hard to allocate the memory by reaping | |
1781 | * our own buffer, now let the real VM do its job and | |
1782 | * go down in flames if truly OOM. | |
1783 | */ | |
caf49191 | 1784 | gfp &= ~(__GFP_NORETRY | __GFP_NOWARN | __GFP_NO_KSWAPD); |
6c085a72 CW |
1785 | gfp |= __GFP_IO | __GFP_WAIT; |
1786 | ||
1787 | i915_gem_shrink_all(dev_priv); | |
1788 | page = shmem_read_mapping_page_gfp(mapping, i, gfp); | |
1789 | if (IS_ERR(page)) | |
1790 | goto err_pages; | |
1791 | ||
caf49191 | 1792 | gfp |= __GFP_NORETRY | __GFP_NOWARN | __GFP_NO_KSWAPD; |
6c085a72 CW |
1793 | gfp &= ~(__GFP_IO | __GFP_WAIT); |
1794 | } | |
e5281ccd | 1795 | |
9da3da66 | 1796 | sg_set_page(sg, page, PAGE_SIZE, 0); |
e5281ccd CW |
1797 | } |
1798 | ||
74ce6b6c CW |
1799 | obj->pages = st; |
1800 | ||
6dacfd2f | 1801 | if (i915_gem_object_needs_bit17_swizzle(obj)) |
e5281ccd CW |
1802 | i915_gem_object_do_bit_17_swizzle(obj); |
1803 | ||
1804 | return 0; | |
1805 | ||
1806 | err_pages: | |
9da3da66 CW |
1807 | for_each_sg(st->sgl, sg, i, page_count) |
1808 | page_cache_release(sg_page(sg)); | |
1809 | sg_free_table(st); | |
1810 | kfree(st); | |
e5281ccd | 1811 | return PTR_ERR(page); |
673a394b EA |
1812 | } |
1813 | ||
37e680a1 CW |
1814 | /* Ensure that the associated pages are gathered from the backing storage |
1815 | * and pinned into our object. i915_gem_object_get_pages() may be called | |
1816 | * multiple times before they are released by a single call to | |
1817 | * i915_gem_object_put_pages() - once the pages are no longer referenced | |
1818 | * either as a result of memory pressure (reaping pages under the shrinker) | |
1819 | * or as the object is itself released. | |
1820 | */ | |
1821 | int | |
1822 | i915_gem_object_get_pages(struct drm_i915_gem_object *obj) | |
1823 | { | |
1824 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; | |
1825 | const struct drm_i915_gem_object_ops *ops = obj->ops; | |
1826 | int ret; | |
1827 | ||
2f745ad3 | 1828 | if (obj->pages) |
37e680a1 CW |
1829 | return 0; |
1830 | ||
43e28f09 CW |
1831 | if (obj->madv != I915_MADV_WILLNEED) { |
1832 | DRM_ERROR("Attempting to obtain a purgeable object\n"); | |
1833 | return -EINVAL; | |
1834 | } | |
1835 | ||
a5570178 CW |
1836 | BUG_ON(obj->pages_pin_count); |
1837 | ||
37e680a1 CW |
1838 | ret = ops->get_pages(obj); |
1839 | if (ret) | |
1840 | return ret; | |
1841 | ||
1842 | list_add_tail(&obj->gtt_list, &dev_priv->mm.unbound_list); | |
1843 | return 0; | |
673a394b EA |
1844 | } |
1845 | ||
54cf91dc | 1846 | void |
05394f39 | 1847 | i915_gem_object_move_to_active(struct drm_i915_gem_object *obj, |
9d773091 | 1848 | struct intel_ring_buffer *ring) |
673a394b | 1849 | { |
05394f39 | 1850 | struct drm_device *dev = obj->base.dev; |
69dc4987 | 1851 | struct drm_i915_private *dev_priv = dev->dev_private; |
9d773091 | 1852 | u32 seqno = intel_ring_get_seqno(ring); |
617dbe27 | 1853 | |
852835f3 | 1854 | BUG_ON(ring == NULL); |
05394f39 | 1855 | obj->ring = ring; |
673a394b EA |
1856 | |
1857 | /* Add a reference if we're newly entering the active list. */ | |
05394f39 CW |
1858 | if (!obj->active) { |
1859 | drm_gem_object_reference(&obj->base); | |
1860 | obj->active = 1; | |
673a394b | 1861 | } |
e35a41de | 1862 | |
673a394b | 1863 | /* Move from whatever list we were on to the tail of execution. */ |
05394f39 CW |
1864 | list_move_tail(&obj->mm_list, &dev_priv->mm.active_list); |
1865 | list_move_tail(&obj->ring_list, &ring->active_list); | |
caea7476 | 1866 | |
0201f1ec | 1867 | obj->last_read_seqno = seqno; |
caea7476 | 1868 | |
7dd49065 | 1869 | if (obj->fenced_gpu_access) { |
caea7476 | 1870 | obj->last_fenced_seqno = seqno; |
caea7476 | 1871 | |
7dd49065 CW |
1872 | /* Bump MRU to take account of the delayed flush */ |
1873 | if (obj->fence_reg != I915_FENCE_REG_NONE) { | |
1874 | struct drm_i915_fence_reg *reg; | |
1875 | ||
1876 | reg = &dev_priv->fence_regs[obj->fence_reg]; | |
1877 | list_move_tail(®->lru_list, | |
1878 | &dev_priv->mm.fence_list); | |
1879 | } | |
caea7476 CW |
1880 | } |
1881 | } | |
1882 | ||
1883 | static void | |
caea7476 | 1884 | i915_gem_object_move_to_inactive(struct drm_i915_gem_object *obj) |
ce44b0ea | 1885 | { |
05394f39 | 1886 | struct drm_device *dev = obj->base.dev; |
caea7476 | 1887 | struct drm_i915_private *dev_priv = dev->dev_private; |
ce44b0ea | 1888 | |
65ce3027 | 1889 | BUG_ON(obj->base.write_domain & ~I915_GEM_GPU_DOMAINS); |
05394f39 | 1890 | BUG_ON(!obj->active); |
caea7476 | 1891 | |
f047e395 CW |
1892 | if (obj->pin_count) /* are we a framebuffer? */ |
1893 | intel_mark_fb_idle(obj); | |
caea7476 | 1894 | |
1b50247a | 1895 | list_move_tail(&obj->mm_list, &dev_priv->mm.inactive_list); |
caea7476 | 1896 | |
65ce3027 | 1897 | list_del_init(&obj->ring_list); |
caea7476 CW |
1898 | obj->ring = NULL; |
1899 | ||
65ce3027 CW |
1900 | obj->last_read_seqno = 0; |
1901 | obj->last_write_seqno = 0; | |
1902 | obj->base.write_domain = 0; | |
1903 | ||
1904 | obj->last_fenced_seqno = 0; | |
caea7476 | 1905 | obj->fenced_gpu_access = false; |
caea7476 CW |
1906 | |
1907 | obj->active = 0; | |
1908 | drm_gem_object_unreference(&obj->base); | |
1909 | ||
1910 | WARN_ON(i915_verify_lists(dev)); | |
ce44b0ea | 1911 | } |
673a394b | 1912 | |
9d773091 | 1913 | static int |
fca26bb4 | 1914 | i915_gem_init_seqno(struct drm_device *dev, u32 seqno) |
53d227f2 | 1915 | { |
9d773091 CW |
1916 | struct drm_i915_private *dev_priv = dev->dev_private; |
1917 | struct intel_ring_buffer *ring; | |
1918 | int ret, i, j; | |
53d227f2 | 1919 | |
107f27a5 | 1920 | /* Carefully retire all requests without writing to the rings */ |
9d773091 | 1921 | for_each_ring(ring, dev_priv, i) { |
107f27a5 CW |
1922 | ret = intel_ring_idle(ring); |
1923 | if (ret) | |
1924 | return ret; | |
9d773091 | 1925 | } |
9d773091 | 1926 | i915_gem_retire_requests(dev); |
107f27a5 CW |
1927 | |
1928 | /* Finally reset hw state */ | |
9d773091 | 1929 | for_each_ring(ring, dev_priv, i) { |
fca26bb4 | 1930 | intel_ring_init_seqno(ring, seqno); |
498d2ac1 | 1931 | |
9d773091 CW |
1932 | for (j = 0; j < ARRAY_SIZE(ring->sync_seqno); j++) |
1933 | ring->sync_seqno[j] = 0; | |
1934 | } | |
53d227f2 | 1935 | |
9d773091 | 1936 | return 0; |
53d227f2 DV |
1937 | } |
1938 | ||
fca26bb4 MK |
1939 | int i915_gem_set_seqno(struct drm_device *dev, u32 seqno) |
1940 | { | |
1941 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1942 | int ret; | |
1943 | ||
1944 | if (seqno == 0) | |
1945 | return -EINVAL; | |
1946 | ||
1947 | /* HWS page needs to be set less than what we | |
1948 | * will inject to ring | |
1949 | */ | |
1950 | ret = i915_gem_init_seqno(dev, seqno - 1); | |
1951 | if (ret) | |
1952 | return ret; | |
1953 | ||
1954 | /* Carefully set the last_seqno value so that wrap | |
1955 | * detection still works | |
1956 | */ | |
1957 | dev_priv->next_seqno = seqno; | |
1958 | dev_priv->last_seqno = seqno - 1; | |
1959 | if (dev_priv->last_seqno == 0) | |
1960 | dev_priv->last_seqno--; | |
1961 | ||
1962 | return 0; | |
1963 | } | |
1964 | ||
9d773091 CW |
1965 | int |
1966 | i915_gem_get_seqno(struct drm_device *dev, u32 *seqno) | |
53d227f2 | 1967 | { |
9d773091 CW |
1968 | struct drm_i915_private *dev_priv = dev->dev_private; |
1969 | ||
1970 | /* reserve 0 for non-seqno */ | |
1971 | if (dev_priv->next_seqno == 0) { | |
fca26bb4 | 1972 | int ret = i915_gem_init_seqno(dev, 0); |
9d773091 CW |
1973 | if (ret) |
1974 | return ret; | |
53d227f2 | 1975 | |
9d773091 CW |
1976 | dev_priv->next_seqno = 1; |
1977 | } | |
53d227f2 | 1978 | |
f72b3435 | 1979 | *seqno = dev_priv->last_seqno = dev_priv->next_seqno++; |
9d773091 | 1980 | return 0; |
53d227f2 DV |
1981 | } |
1982 | ||
3cce469c | 1983 | int |
db53a302 | 1984 | i915_add_request(struct intel_ring_buffer *ring, |
f787a5f5 | 1985 | struct drm_file *file, |
acb868d3 | 1986 | u32 *out_seqno) |
673a394b | 1987 | { |
db53a302 | 1988 | drm_i915_private_t *dev_priv = ring->dev->dev_private; |
acb868d3 | 1989 | struct drm_i915_gem_request *request; |
a71d8d94 | 1990 | u32 request_ring_position; |
673a394b | 1991 | int was_empty; |
3cce469c CW |
1992 | int ret; |
1993 | ||
cc889e0f DV |
1994 | /* |
1995 | * Emit any outstanding flushes - execbuf can fail to emit the flush | |
1996 | * after having emitted the batchbuffer command. Hence we need to fix | |
1997 | * things up similar to emitting the lazy request. The difference here | |
1998 | * is that the flush _must_ happen before the next request, no matter | |
1999 | * what. | |
2000 | */ | |
a7b9761d CW |
2001 | ret = intel_ring_flush_all_caches(ring); |
2002 | if (ret) | |
2003 | return ret; | |
cc889e0f | 2004 | |
acb868d3 CW |
2005 | request = kmalloc(sizeof(*request), GFP_KERNEL); |
2006 | if (request == NULL) | |
2007 | return -ENOMEM; | |
cc889e0f | 2008 | |
673a394b | 2009 | |
a71d8d94 CW |
2010 | /* Record the position of the start of the request so that |
2011 | * should we detect the updated seqno part-way through the | |
2012 | * GPU processing the request, we never over-estimate the | |
2013 | * position of the head. | |
2014 | */ | |
2015 | request_ring_position = intel_ring_get_tail(ring); | |
2016 | ||
9d773091 | 2017 | ret = ring->add_request(ring); |
3bb73aba CW |
2018 | if (ret) { |
2019 | kfree(request); | |
2020 | return ret; | |
2021 | } | |
673a394b | 2022 | |
9d773091 | 2023 | request->seqno = intel_ring_get_seqno(ring); |
852835f3 | 2024 | request->ring = ring; |
a71d8d94 | 2025 | request->tail = request_ring_position; |
673a394b | 2026 | request->emitted_jiffies = jiffies; |
852835f3 ZN |
2027 | was_empty = list_empty(&ring->request_list); |
2028 | list_add_tail(&request->list, &ring->request_list); | |
3bb73aba | 2029 | request->file_priv = NULL; |
852835f3 | 2030 | |
db53a302 CW |
2031 | if (file) { |
2032 | struct drm_i915_file_private *file_priv = file->driver_priv; | |
2033 | ||
1c25595f | 2034 | spin_lock(&file_priv->mm.lock); |
f787a5f5 | 2035 | request->file_priv = file_priv; |
b962442e | 2036 | list_add_tail(&request->client_list, |
f787a5f5 | 2037 | &file_priv->mm.request_list); |
1c25595f | 2038 | spin_unlock(&file_priv->mm.lock); |
b962442e | 2039 | } |
673a394b | 2040 | |
9d773091 | 2041 | trace_i915_gem_request_add(ring, request->seqno); |
5391d0cf | 2042 | ring->outstanding_lazy_request = 0; |
db53a302 | 2043 | |
f65d9421 | 2044 | if (!dev_priv->mm.suspended) { |
3e0dc6b0 BW |
2045 | if (i915_enable_hangcheck) { |
2046 | mod_timer(&dev_priv->hangcheck_timer, | |
cecc21fe | 2047 | round_jiffies_up(jiffies + DRM_I915_HANGCHECK_JIFFIES)); |
3e0dc6b0 | 2048 | } |
f047e395 | 2049 | if (was_empty) { |
b3b079db | 2050 | queue_delayed_work(dev_priv->wq, |
bcb45086 CW |
2051 | &dev_priv->mm.retire_work, |
2052 | round_jiffies_up_relative(HZ)); | |
f047e395 CW |
2053 | intel_mark_busy(dev_priv->dev); |
2054 | } | |
f65d9421 | 2055 | } |
cc889e0f | 2056 | |
acb868d3 | 2057 | if (out_seqno) |
9d773091 | 2058 | *out_seqno = request->seqno; |
3cce469c | 2059 | return 0; |
673a394b EA |
2060 | } |
2061 | ||
f787a5f5 CW |
2062 | static inline void |
2063 | i915_gem_request_remove_from_client(struct drm_i915_gem_request *request) | |
673a394b | 2064 | { |
1c25595f | 2065 | struct drm_i915_file_private *file_priv = request->file_priv; |
673a394b | 2066 | |
1c25595f CW |
2067 | if (!file_priv) |
2068 | return; | |
1c5d22f7 | 2069 | |
1c25595f | 2070 | spin_lock(&file_priv->mm.lock); |
09bfa517 HRK |
2071 | if (request->file_priv) { |
2072 | list_del(&request->client_list); | |
2073 | request->file_priv = NULL; | |
2074 | } | |
1c25595f | 2075 | spin_unlock(&file_priv->mm.lock); |
673a394b | 2076 | } |
673a394b | 2077 | |
dfaae392 CW |
2078 | static void i915_gem_reset_ring_lists(struct drm_i915_private *dev_priv, |
2079 | struct intel_ring_buffer *ring) | |
9375e446 | 2080 | { |
dfaae392 CW |
2081 | while (!list_empty(&ring->request_list)) { |
2082 | struct drm_i915_gem_request *request; | |
673a394b | 2083 | |
dfaae392 CW |
2084 | request = list_first_entry(&ring->request_list, |
2085 | struct drm_i915_gem_request, | |
2086 | list); | |
de151cf6 | 2087 | |
dfaae392 | 2088 | list_del(&request->list); |
f787a5f5 | 2089 | i915_gem_request_remove_from_client(request); |
dfaae392 CW |
2090 | kfree(request); |
2091 | } | |
673a394b | 2092 | |
dfaae392 | 2093 | while (!list_empty(&ring->active_list)) { |
05394f39 | 2094 | struct drm_i915_gem_object *obj; |
9375e446 | 2095 | |
05394f39 CW |
2096 | obj = list_first_entry(&ring->active_list, |
2097 | struct drm_i915_gem_object, | |
2098 | ring_list); | |
9375e446 | 2099 | |
05394f39 | 2100 | i915_gem_object_move_to_inactive(obj); |
673a394b EA |
2101 | } |
2102 | } | |
2103 | ||
312817a3 CW |
2104 | static void i915_gem_reset_fences(struct drm_device *dev) |
2105 | { | |
2106 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2107 | int i; | |
2108 | ||
4b9de737 | 2109 | for (i = 0; i < dev_priv->num_fence_regs; i++) { |
312817a3 | 2110 | struct drm_i915_fence_reg *reg = &dev_priv->fence_regs[i]; |
7d2cb39c | 2111 | |
ada726c7 | 2112 | i915_gem_write_fence(dev, i, NULL); |
7d2cb39c | 2113 | |
ada726c7 CW |
2114 | if (reg->obj) |
2115 | i915_gem_object_fence_lost(reg->obj); | |
7d2cb39c | 2116 | |
ada726c7 CW |
2117 | reg->pin_count = 0; |
2118 | reg->obj = NULL; | |
2119 | INIT_LIST_HEAD(®->lru_list); | |
312817a3 | 2120 | } |
ada726c7 CW |
2121 | |
2122 | INIT_LIST_HEAD(&dev_priv->mm.fence_list); | |
312817a3 CW |
2123 | } |
2124 | ||
069efc1d | 2125 | void i915_gem_reset(struct drm_device *dev) |
673a394b | 2126 | { |
77f01230 | 2127 | struct drm_i915_private *dev_priv = dev->dev_private; |
05394f39 | 2128 | struct drm_i915_gem_object *obj; |
b4519513 | 2129 | struct intel_ring_buffer *ring; |
1ec14ad3 | 2130 | int i; |
673a394b | 2131 | |
b4519513 CW |
2132 | for_each_ring(ring, dev_priv, i) |
2133 | i915_gem_reset_ring_lists(dev_priv, ring); | |
dfaae392 | 2134 | |
dfaae392 CW |
2135 | /* Move everything out of the GPU domains to ensure we do any |
2136 | * necessary invalidation upon reuse. | |
2137 | */ | |
05394f39 | 2138 | list_for_each_entry(obj, |
77f01230 | 2139 | &dev_priv->mm.inactive_list, |
69dc4987 | 2140 | mm_list) |
77f01230 | 2141 | { |
05394f39 | 2142 | obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS; |
77f01230 | 2143 | } |
069efc1d CW |
2144 | |
2145 | /* The fence registers are invalidated so clear them out */ | |
312817a3 | 2146 | i915_gem_reset_fences(dev); |
673a394b EA |
2147 | } |
2148 | ||
2149 | /** | |
2150 | * This function clears the request list as sequence numbers are passed. | |
2151 | */ | |
a71d8d94 | 2152 | void |
db53a302 | 2153 | i915_gem_retire_requests_ring(struct intel_ring_buffer *ring) |
673a394b | 2154 | { |
673a394b EA |
2155 | uint32_t seqno; |
2156 | ||
db53a302 | 2157 | if (list_empty(&ring->request_list)) |
6c0594a3 KW |
2158 | return; |
2159 | ||
db53a302 | 2160 | WARN_ON(i915_verify_lists(ring->dev)); |
673a394b | 2161 | |
b2eadbc8 | 2162 | seqno = ring->get_seqno(ring, true); |
1ec14ad3 | 2163 | |
852835f3 | 2164 | while (!list_empty(&ring->request_list)) { |
673a394b | 2165 | struct drm_i915_gem_request *request; |
673a394b | 2166 | |
852835f3 | 2167 | request = list_first_entry(&ring->request_list, |
673a394b EA |
2168 | struct drm_i915_gem_request, |
2169 | list); | |
673a394b | 2170 | |
dfaae392 | 2171 | if (!i915_seqno_passed(seqno, request->seqno)) |
b84d5f0c CW |
2172 | break; |
2173 | ||
db53a302 | 2174 | trace_i915_gem_request_retire(ring, request->seqno); |
a71d8d94 CW |
2175 | /* We know the GPU must have read the request to have |
2176 | * sent us the seqno + interrupt, so use the position | |
2177 | * of tail of the request to update the last known position | |
2178 | * of the GPU head. | |
2179 | */ | |
2180 | ring->last_retired_head = request->tail; | |
b84d5f0c CW |
2181 | |
2182 | list_del(&request->list); | |
f787a5f5 | 2183 | i915_gem_request_remove_from_client(request); |
b84d5f0c CW |
2184 | kfree(request); |
2185 | } | |
673a394b | 2186 | |
b84d5f0c CW |
2187 | /* Move any buffers on the active list that are no longer referenced |
2188 | * by the ringbuffer to the flushing/inactive lists as appropriate. | |
2189 | */ | |
2190 | while (!list_empty(&ring->active_list)) { | |
05394f39 | 2191 | struct drm_i915_gem_object *obj; |
b84d5f0c | 2192 | |
0206e353 | 2193 | obj = list_first_entry(&ring->active_list, |
05394f39 CW |
2194 | struct drm_i915_gem_object, |
2195 | ring_list); | |
673a394b | 2196 | |
0201f1ec | 2197 | if (!i915_seqno_passed(seqno, obj->last_read_seqno)) |
673a394b | 2198 | break; |
b84d5f0c | 2199 | |
65ce3027 | 2200 | i915_gem_object_move_to_inactive(obj); |
673a394b | 2201 | } |
9d34e5db | 2202 | |
db53a302 CW |
2203 | if (unlikely(ring->trace_irq_seqno && |
2204 | i915_seqno_passed(seqno, ring->trace_irq_seqno))) { | |
1ec14ad3 | 2205 | ring->irq_put(ring); |
db53a302 | 2206 | ring->trace_irq_seqno = 0; |
9d34e5db | 2207 | } |
23bc5982 | 2208 | |
db53a302 | 2209 | WARN_ON(i915_verify_lists(ring->dev)); |
673a394b EA |
2210 | } |
2211 | ||
b09a1fec CW |
2212 | void |
2213 | i915_gem_retire_requests(struct drm_device *dev) | |
2214 | { | |
2215 | drm_i915_private_t *dev_priv = dev->dev_private; | |
b4519513 | 2216 | struct intel_ring_buffer *ring; |
1ec14ad3 | 2217 | int i; |
b09a1fec | 2218 | |
b4519513 CW |
2219 | for_each_ring(ring, dev_priv, i) |
2220 | i915_gem_retire_requests_ring(ring); | |
b09a1fec CW |
2221 | } |
2222 | ||
75ef9da2 | 2223 | static void |
673a394b EA |
2224 | i915_gem_retire_work_handler(struct work_struct *work) |
2225 | { | |
2226 | drm_i915_private_t *dev_priv; | |
2227 | struct drm_device *dev; | |
b4519513 | 2228 | struct intel_ring_buffer *ring; |
0a58705b CW |
2229 | bool idle; |
2230 | int i; | |
673a394b EA |
2231 | |
2232 | dev_priv = container_of(work, drm_i915_private_t, | |
2233 | mm.retire_work.work); | |
2234 | dev = dev_priv->dev; | |
2235 | ||
891b48cf CW |
2236 | /* Come back later if the device is busy... */ |
2237 | if (!mutex_trylock(&dev->struct_mutex)) { | |
bcb45086 CW |
2238 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, |
2239 | round_jiffies_up_relative(HZ)); | |
891b48cf CW |
2240 | return; |
2241 | } | |
673a394b | 2242 | |
b09a1fec | 2243 | i915_gem_retire_requests(dev); |
673a394b | 2244 | |
0a58705b CW |
2245 | /* Send a periodic flush down the ring so we don't hold onto GEM |
2246 | * objects indefinitely. | |
673a394b | 2247 | */ |
0a58705b | 2248 | idle = true; |
b4519513 | 2249 | for_each_ring(ring, dev_priv, i) { |
3bb73aba CW |
2250 | if (ring->gpu_caches_dirty) |
2251 | i915_add_request(ring, NULL, NULL); | |
0a58705b CW |
2252 | |
2253 | idle &= list_empty(&ring->request_list); | |
673a394b EA |
2254 | } |
2255 | ||
0a58705b | 2256 | if (!dev_priv->mm.suspended && !idle) |
bcb45086 CW |
2257 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, |
2258 | round_jiffies_up_relative(HZ)); | |
f047e395 CW |
2259 | if (idle) |
2260 | intel_mark_idle(dev); | |
0a58705b | 2261 | |
673a394b | 2262 | mutex_unlock(&dev->struct_mutex); |
673a394b EA |
2263 | } |
2264 | ||
30dfebf3 DV |
2265 | /** |
2266 | * Ensures that an object will eventually get non-busy by flushing any required | |
2267 | * write domains, emitting any outstanding lazy request and retiring and | |
2268 | * completed requests. | |
2269 | */ | |
2270 | static int | |
2271 | i915_gem_object_flush_active(struct drm_i915_gem_object *obj) | |
2272 | { | |
2273 | int ret; | |
2274 | ||
2275 | if (obj->active) { | |
0201f1ec | 2276 | ret = i915_gem_check_olr(obj->ring, obj->last_read_seqno); |
30dfebf3 DV |
2277 | if (ret) |
2278 | return ret; | |
2279 | ||
30dfebf3 DV |
2280 | i915_gem_retire_requests_ring(obj->ring); |
2281 | } | |
2282 | ||
2283 | return 0; | |
2284 | } | |
2285 | ||
23ba4fd0 BW |
2286 | /** |
2287 | * i915_gem_wait_ioctl - implements DRM_IOCTL_I915_GEM_WAIT | |
2288 | * @DRM_IOCTL_ARGS: standard ioctl arguments | |
2289 | * | |
2290 | * Returns 0 if successful, else an error is returned with the remaining time in | |
2291 | * the timeout parameter. | |
2292 | * -ETIME: object is still busy after timeout | |
2293 | * -ERESTARTSYS: signal interrupted the wait | |
2294 | * -ENONENT: object doesn't exist | |
2295 | * Also possible, but rare: | |
2296 | * -EAGAIN: GPU wedged | |
2297 | * -ENOMEM: damn | |
2298 | * -ENODEV: Internal IRQ fail | |
2299 | * -E?: The add request failed | |
2300 | * | |
2301 | * The wait ioctl with a timeout of 0 reimplements the busy ioctl. With any | |
2302 | * non-zero timeout parameter the wait ioctl will wait for the given number of | |
2303 | * nanoseconds on an object becoming unbusy. Since the wait itself does so | |
2304 | * without holding struct_mutex the object may become re-busied before this | |
2305 | * function completes. A similar but shorter * race condition exists in the busy | |
2306 | * ioctl | |
2307 | */ | |
2308 | int | |
2309 | i915_gem_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *file) | |
2310 | { | |
2311 | struct drm_i915_gem_wait *args = data; | |
2312 | struct drm_i915_gem_object *obj; | |
2313 | struct intel_ring_buffer *ring = NULL; | |
eac1f14f | 2314 | struct timespec timeout_stack, *timeout = NULL; |
23ba4fd0 BW |
2315 | u32 seqno = 0; |
2316 | int ret = 0; | |
2317 | ||
eac1f14f BW |
2318 | if (args->timeout_ns >= 0) { |
2319 | timeout_stack = ns_to_timespec(args->timeout_ns); | |
2320 | timeout = &timeout_stack; | |
2321 | } | |
23ba4fd0 BW |
2322 | |
2323 | ret = i915_mutex_lock_interruptible(dev); | |
2324 | if (ret) | |
2325 | return ret; | |
2326 | ||
2327 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->bo_handle)); | |
2328 | if (&obj->base == NULL) { | |
2329 | mutex_unlock(&dev->struct_mutex); | |
2330 | return -ENOENT; | |
2331 | } | |
2332 | ||
30dfebf3 DV |
2333 | /* Need to make sure the object gets inactive eventually. */ |
2334 | ret = i915_gem_object_flush_active(obj); | |
23ba4fd0 BW |
2335 | if (ret) |
2336 | goto out; | |
2337 | ||
2338 | if (obj->active) { | |
0201f1ec | 2339 | seqno = obj->last_read_seqno; |
23ba4fd0 BW |
2340 | ring = obj->ring; |
2341 | } | |
2342 | ||
2343 | if (seqno == 0) | |
2344 | goto out; | |
2345 | ||
23ba4fd0 BW |
2346 | /* Do this after OLR check to make sure we make forward progress polling |
2347 | * on this IOCTL with a 0 timeout (like busy ioctl) | |
2348 | */ | |
2349 | if (!args->timeout_ns) { | |
2350 | ret = -ETIME; | |
2351 | goto out; | |
2352 | } | |
2353 | ||
2354 | drm_gem_object_unreference(&obj->base); | |
2355 | mutex_unlock(&dev->struct_mutex); | |
2356 | ||
eac1f14f BW |
2357 | ret = __wait_seqno(ring, seqno, true, timeout); |
2358 | if (timeout) { | |
2359 | WARN_ON(!timespec_valid(timeout)); | |
2360 | args->timeout_ns = timespec_to_ns(timeout); | |
2361 | } | |
23ba4fd0 BW |
2362 | return ret; |
2363 | ||
2364 | out: | |
2365 | drm_gem_object_unreference(&obj->base); | |
2366 | mutex_unlock(&dev->struct_mutex); | |
2367 | return ret; | |
2368 | } | |
2369 | ||
5816d648 BW |
2370 | /** |
2371 | * i915_gem_object_sync - sync an object to a ring. | |
2372 | * | |
2373 | * @obj: object which may be in use on another ring. | |
2374 | * @to: ring we wish to use the object on. May be NULL. | |
2375 | * | |
2376 | * This code is meant to abstract object synchronization with the GPU. | |
2377 | * Calling with NULL implies synchronizing the object with the CPU | |
2378 | * rather than a particular GPU ring. | |
2379 | * | |
2380 | * Returns 0 if successful, else propagates up the lower layer error. | |
2381 | */ | |
2911a35b BW |
2382 | int |
2383 | i915_gem_object_sync(struct drm_i915_gem_object *obj, | |
2384 | struct intel_ring_buffer *to) | |
2385 | { | |
2386 | struct intel_ring_buffer *from = obj->ring; | |
2387 | u32 seqno; | |
2388 | int ret, idx; | |
2389 | ||
2390 | if (from == NULL || to == from) | |
2391 | return 0; | |
2392 | ||
5816d648 | 2393 | if (to == NULL || !i915_semaphore_is_enabled(obj->base.dev)) |
0201f1ec | 2394 | return i915_gem_object_wait_rendering(obj, false); |
2911a35b BW |
2395 | |
2396 | idx = intel_ring_sync_index(from, to); | |
2397 | ||
0201f1ec | 2398 | seqno = obj->last_read_seqno; |
2911a35b BW |
2399 | if (seqno <= from->sync_seqno[idx]) |
2400 | return 0; | |
2401 | ||
b4aca010 BW |
2402 | ret = i915_gem_check_olr(obj->ring, seqno); |
2403 | if (ret) | |
2404 | return ret; | |
2911a35b | 2405 | |
1500f7ea | 2406 | ret = to->sync_to(to, from, seqno); |
e3a5a225 | 2407 | if (!ret) |
7b01e260 MK |
2408 | /* We use last_read_seqno because sync_to() |
2409 | * might have just caused seqno wrap under | |
2410 | * the radar. | |
2411 | */ | |
2412 | from->sync_seqno[idx] = obj->last_read_seqno; | |
2911a35b | 2413 | |
e3a5a225 | 2414 | return ret; |
2911a35b BW |
2415 | } |
2416 | ||
b5ffc9bc CW |
2417 | static void i915_gem_object_finish_gtt(struct drm_i915_gem_object *obj) |
2418 | { | |
2419 | u32 old_write_domain, old_read_domains; | |
2420 | ||
b5ffc9bc CW |
2421 | /* Act a barrier for all accesses through the GTT */ |
2422 | mb(); | |
2423 | ||
2424 | /* Force a pagefault for domain tracking on next user access */ | |
2425 | i915_gem_release_mmap(obj); | |
2426 | ||
b97c3d9c KP |
2427 | if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0) |
2428 | return; | |
2429 | ||
b5ffc9bc CW |
2430 | old_read_domains = obj->base.read_domains; |
2431 | old_write_domain = obj->base.write_domain; | |
2432 | ||
2433 | obj->base.read_domains &= ~I915_GEM_DOMAIN_GTT; | |
2434 | obj->base.write_domain &= ~I915_GEM_DOMAIN_GTT; | |
2435 | ||
2436 | trace_i915_gem_object_change_domain(obj, | |
2437 | old_read_domains, | |
2438 | old_write_domain); | |
2439 | } | |
2440 | ||
673a394b EA |
2441 | /** |
2442 | * Unbinds an object from the GTT aperture. | |
2443 | */ | |
0f973f27 | 2444 | int |
05394f39 | 2445 | i915_gem_object_unbind(struct drm_i915_gem_object *obj) |
673a394b | 2446 | { |
7bddb01f | 2447 | drm_i915_private_t *dev_priv = obj->base.dev->dev_private; |
43e28f09 | 2448 | int ret; |
673a394b | 2449 | |
05394f39 | 2450 | if (obj->gtt_space == NULL) |
673a394b EA |
2451 | return 0; |
2452 | ||
31d8d651 CW |
2453 | if (obj->pin_count) |
2454 | return -EBUSY; | |
673a394b | 2455 | |
c4670ad0 CW |
2456 | BUG_ON(obj->pages == NULL); |
2457 | ||
a8198eea | 2458 | ret = i915_gem_object_finish_gpu(obj); |
1488fc08 | 2459 | if (ret) |
a8198eea CW |
2460 | return ret; |
2461 | /* Continue on if we fail due to EIO, the GPU is hung so we | |
2462 | * should be safe and we need to cleanup or else we might | |
2463 | * cause memory corruption through use-after-free. | |
2464 | */ | |
2465 | ||
b5ffc9bc | 2466 | i915_gem_object_finish_gtt(obj); |
5323fd04 | 2467 | |
96b47b65 | 2468 | /* release the fence reg _after_ flushing */ |
d9e86c0e | 2469 | ret = i915_gem_object_put_fence(obj); |
1488fc08 | 2470 | if (ret) |
d9e86c0e | 2471 | return ret; |
96b47b65 | 2472 | |
db53a302 CW |
2473 | trace_i915_gem_object_unbind(obj); |
2474 | ||
74898d7e DV |
2475 | if (obj->has_global_gtt_mapping) |
2476 | i915_gem_gtt_unbind_object(obj); | |
7bddb01f DV |
2477 | if (obj->has_aliasing_ppgtt_mapping) { |
2478 | i915_ppgtt_unbind_object(dev_priv->mm.aliasing_ppgtt, obj); | |
2479 | obj->has_aliasing_ppgtt_mapping = 0; | |
2480 | } | |
74163907 | 2481 | i915_gem_gtt_finish_object(obj); |
7bddb01f | 2482 | |
6c085a72 CW |
2483 | list_del(&obj->mm_list); |
2484 | list_move_tail(&obj->gtt_list, &dev_priv->mm.unbound_list); | |
75e9e915 | 2485 | /* Avoid an unnecessary call to unbind on rebind. */ |
05394f39 | 2486 | obj->map_and_fenceable = true; |
673a394b | 2487 | |
05394f39 CW |
2488 | drm_mm_put_block(obj->gtt_space); |
2489 | obj->gtt_space = NULL; | |
2490 | obj->gtt_offset = 0; | |
673a394b | 2491 | |
88241785 | 2492 | return 0; |
54cf91dc CW |
2493 | } |
2494 | ||
b2da9fe5 | 2495 | int i915_gpu_idle(struct drm_device *dev) |
4df2faf4 DV |
2496 | { |
2497 | drm_i915_private_t *dev_priv = dev->dev_private; | |
b4519513 | 2498 | struct intel_ring_buffer *ring; |
1ec14ad3 | 2499 | int ret, i; |
4df2faf4 | 2500 | |
4df2faf4 | 2501 | /* Flush everything onto the inactive list. */ |
b4519513 | 2502 | for_each_ring(ring, dev_priv, i) { |
b6c7488d BW |
2503 | ret = i915_switch_context(ring, NULL, DEFAULT_CONTEXT_ID); |
2504 | if (ret) | |
2505 | return ret; | |
2506 | ||
3e960501 | 2507 | ret = intel_ring_idle(ring); |
1ec14ad3 CW |
2508 | if (ret) |
2509 | return ret; | |
2510 | } | |
4df2faf4 | 2511 | |
8a1a49f9 | 2512 | return 0; |
4df2faf4 DV |
2513 | } |
2514 | ||
9ce079e4 CW |
2515 | static void i965_write_fence_reg(struct drm_device *dev, int reg, |
2516 | struct drm_i915_gem_object *obj) | |
de151cf6 | 2517 | { |
de151cf6 | 2518 | drm_i915_private_t *dev_priv = dev->dev_private; |
56c844e5 ID |
2519 | int fence_reg; |
2520 | int fence_pitch_shift; | |
de151cf6 JB |
2521 | uint64_t val; |
2522 | ||
56c844e5 ID |
2523 | if (INTEL_INFO(dev)->gen >= 6) { |
2524 | fence_reg = FENCE_REG_SANDYBRIDGE_0; | |
2525 | fence_pitch_shift = SANDYBRIDGE_FENCE_PITCH_SHIFT; | |
2526 | } else { | |
2527 | fence_reg = FENCE_REG_965_0; | |
2528 | fence_pitch_shift = I965_FENCE_PITCH_SHIFT; | |
2529 | } | |
2530 | ||
9ce079e4 CW |
2531 | if (obj) { |
2532 | u32 size = obj->gtt_space->size; | |
de151cf6 | 2533 | |
9ce079e4 CW |
2534 | val = (uint64_t)((obj->gtt_offset + size - 4096) & |
2535 | 0xfffff000) << 32; | |
2536 | val |= obj->gtt_offset & 0xfffff000; | |
56c844e5 | 2537 | val |= (uint64_t)((obj->stride / 128) - 1) << fence_pitch_shift; |
9ce079e4 CW |
2538 | if (obj->tiling_mode == I915_TILING_Y) |
2539 | val |= 1 << I965_FENCE_TILING_Y_SHIFT; | |
2540 | val |= I965_FENCE_REG_VALID; | |
2541 | } else | |
2542 | val = 0; | |
c6642782 | 2543 | |
56c844e5 ID |
2544 | fence_reg += reg * 8; |
2545 | I915_WRITE64(fence_reg, val); | |
2546 | POSTING_READ(fence_reg); | |
de151cf6 JB |
2547 | } |
2548 | ||
9ce079e4 CW |
2549 | static void i915_write_fence_reg(struct drm_device *dev, int reg, |
2550 | struct drm_i915_gem_object *obj) | |
de151cf6 | 2551 | { |
de151cf6 | 2552 | drm_i915_private_t *dev_priv = dev->dev_private; |
9ce079e4 | 2553 | u32 val; |
de151cf6 | 2554 | |
9ce079e4 CW |
2555 | if (obj) { |
2556 | u32 size = obj->gtt_space->size; | |
2557 | int pitch_val; | |
2558 | int tile_width; | |
c6642782 | 2559 | |
9ce079e4 CW |
2560 | WARN((obj->gtt_offset & ~I915_FENCE_START_MASK) || |
2561 | (size & -size) != size || | |
2562 | (obj->gtt_offset & (size - 1)), | |
2563 | "object 0x%08x [fenceable? %d] not 1M or pot-size (0x%08x) aligned\n", | |
2564 | obj->gtt_offset, obj->map_and_fenceable, size); | |
c6642782 | 2565 | |
9ce079e4 CW |
2566 | if (obj->tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev)) |
2567 | tile_width = 128; | |
2568 | else | |
2569 | tile_width = 512; | |
2570 | ||
2571 | /* Note: pitch better be a power of two tile widths */ | |
2572 | pitch_val = obj->stride / tile_width; | |
2573 | pitch_val = ffs(pitch_val) - 1; | |
2574 | ||
2575 | val = obj->gtt_offset; | |
2576 | if (obj->tiling_mode == I915_TILING_Y) | |
2577 | val |= 1 << I830_FENCE_TILING_Y_SHIFT; | |
2578 | val |= I915_FENCE_SIZE_BITS(size); | |
2579 | val |= pitch_val << I830_FENCE_PITCH_SHIFT; | |
2580 | val |= I830_FENCE_REG_VALID; | |
2581 | } else | |
2582 | val = 0; | |
2583 | ||
2584 | if (reg < 8) | |
2585 | reg = FENCE_REG_830_0 + reg * 4; | |
2586 | else | |
2587 | reg = FENCE_REG_945_8 + (reg - 8) * 4; | |
2588 | ||
2589 | I915_WRITE(reg, val); | |
2590 | POSTING_READ(reg); | |
de151cf6 JB |
2591 | } |
2592 | ||
9ce079e4 CW |
2593 | static void i830_write_fence_reg(struct drm_device *dev, int reg, |
2594 | struct drm_i915_gem_object *obj) | |
de151cf6 | 2595 | { |
de151cf6 | 2596 | drm_i915_private_t *dev_priv = dev->dev_private; |
de151cf6 | 2597 | uint32_t val; |
de151cf6 | 2598 | |
9ce079e4 CW |
2599 | if (obj) { |
2600 | u32 size = obj->gtt_space->size; | |
2601 | uint32_t pitch_val; | |
de151cf6 | 2602 | |
9ce079e4 CW |
2603 | WARN((obj->gtt_offset & ~I830_FENCE_START_MASK) || |
2604 | (size & -size) != size || | |
2605 | (obj->gtt_offset & (size - 1)), | |
2606 | "object 0x%08x not 512K or pot-size 0x%08x aligned\n", | |
2607 | obj->gtt_offset, size); | |
e76a16de | 2608 | |
9ce079e4 CW |
2609 | pitch_val = obj->stride / 128; |
2610 | pitch_val = ffs(pitch_val) - 1; | |
de151cf6 | 2611 | |
9ce079e4 CW |
2612 | val = obj->gtt_offset; |
2613 | if (obj->tiling_mode == I915_TILING_Y) | |
2614 | val |= 1 << I830_FENCE_TILING_Y_SHIFT; | |
2615 | val |= I830_FENCE_SIZE_BITS(size); | |
2616 | val |= pitch_val << I830_FENCE_PITCH_SHIFT; | |
2617 | val |= I830_FENCE_REG_VALID; | |
2618 | } else | |
2619 | val = 0; | |
c6642782 | 2620 | |
9ce079e4 CW |
2621 | I915_WRITE(FENCE_REG_830_0 + reg * 4, val); |
2622 | POSTING_READ(FENCE_REG_830_0 + reg * 4); | |
2623 | } | |
2624 | ||
2625 | static void i915_gem_write_fence(struct drm_device *dev, int reg, | |
2626 | struct drm_i915_gem_object *obj) | |
2627 | { | |
2628 | switch (INTEL_INFO(dev)->gen) { | |
2629 | case 7: | |
56c844e5 | 2630 | case 6: |
9ce079e4 CW |
2631 | case 5: |
2632 | case 4: i965_write_fence_reg(dev, reg, obj); break; | |
2633 | case 3: i915_write_fence_reg(dev, reg, obj); break; | |
2634 | case 2: i830_write_fence_reg(dev, reg, obj); break; | |
7dbf9d6e | 2635 | default: BUG(); |
9ce079e4 | 2636 | } |
de151cf6 JB |
2637 | } |
2638 | ||
61050808 CW |
2639 | static inline int fence_number(struct drm_i915_private *dev_priv, |
2640 | struct drm_i915_fence_reg *fence) | |
2641 | { | |
2642 | return fence - dev_priv->fence_regs; | |
2643 | } | |
2644 | ||
2645 | static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj, | |
2646 | struct drm_i915_fence_reg *fence, | |
2647 | bool enable) | |
2648 | { | |
2649 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; | |
2650 | int reg = fence_number(dev_priv, fence); | |
2651 | ||
2652 | i915_gem_write_fence(obj->base.dev, reg, enable ? obj : NULL); | |
2653 | ||
2654 | if (enable) { | |
2655 | obj->fence_reg = reg; | |
2656 | fence->obj = obj; | |
2657 | list_move_tail(&fence->lru_list, &dev_priv->mm.fence_list); | |
2658 | } else { | |
2659 | obj->fence_reg = I915_FENCE_REG_NONE; | |
2660 | fence->obj = NULL; | |
2661 | list_del_init(&fence->lru_list); | |
2662 | } | |
2663 | } | |
2664 | ||
d9e86c0e | 2665 | static int |
a360bb1a | 2666 | i915_gem_object_flush_fence(struct drm_i915_gem_object *obj) |
d9e86c0e | 2667 | { |
1c293ea3 | 2668 | if (obj->last_fenced_seqno) { |
86d5bc37 | 2669 | int ret = i915_wait_seqno(obj->ring, obj->last_fenced_seqno); |
18991845 CW |
2670 | if (ret) |
2671 | return ret; | |
d9e86c0e CW |
2672 | |
2673 | obj->last_fenced_seqno = 0; | |
d9e86c0e CW |
2674 | } |
2675 | ||
63256ec5 CW |
2676 | /* Ensure that all CPU reads are completed before installing a fence |
2677 | * and all writes before removing the fence. | |
2678 | */ | |
2679 | if (obj->base.read_domains & I915_GEM_DOMAIN_GTT) | |
2680 | mb(); | |
2681 | ||
86d5bc37 | 2682 | obj->fenced_gpu_access = false; |
d9e86c0e CW |
2683 | return 0; |
2684 | } | |
2685 | ||
2686 | int | |
2687 | i915_gem_object_put_fence(struct drm_i915_gem_object *obj) | |
2688 | { | |
61050808 | 2689 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
d9e86c0e CW |
2690 | int ret; |
2691 | ||
a360bb1a | 2692 | ret = i915_gem_object_flush_fence(obj); |
d9e86c0e CW |
2693 | if (ret) |
2694 | return ret; | |
2695 | ||
61050808 CW |
2696 | if (obj->fence_reg == I915_FENCE_REG_NONE) |
2697 | return 0; | |
d9e86c0e | 2698 | |
61050808 CW |
2699 | i915_gem_object_update_fence(obj, |
2700 | &dev_priv->fence_regs[obj->fence_reg], | |
2701 | false); | |
2702 | i915_gem_object_fence_lost(obj); | |
d9e86c0e CW |
2703 | |
2704 | return 0; | |
2705 | } | |
2706 | ||
2707 | static struct drm_i915_fence_reg * | |
a360bb1a | 2708 | i915_find_fence_reg(struct drm_device *dev) |
ae3db24a | 2709 | { |
ae3db24a | 2710 | struct drm_i915_private *dev_priv = dev->dev_private; |
8fe301ad | 2711 | struct drm_i915_fence_reg *reg, *avail; |
d9e86c0e | 2712 | int i; |
ae3db24a DV |
2713 | |
2714 | /* First try to find a free reg */ | |
d9e86c0e | 2715 | avail = NULL; |
ae3db24a DV |
2716 | for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) { |
2717 | reg = &dev_priv->fence_regs[i]; | |
2718 | if (!reg->obj) | |
d9e86c0e | 2719 | return reg; |
ae3db24a | 2720 | |
1690e1eb | 2721 | if (!reg->pin_count) |
d9e86c0e | 2722 | avail = reg; |
ae3db24a DV |
2723 | } |
2724 | ||
d9e86c0e CW |
2725 | if (avail == NULL) |
2726 | return NULL; | |
ae3db24a DV |
2727 | |
2728 | /* None available, try to steal one or wait for a user to finish */ | |
d9e86c0e | 2729 | list_for_each_entry(reg, &dev_priv->mm.fence_list, lru_list) { |
1690e1eb | 2730 | if (reg->pin_count) |
ae3db24a DV |
2731 | continue; |
2732 | ||
8fe301ad | 2733 | return reg; |
ae3db24a DV |
2734 | } |
2735 | ||
8fe301ad | 2736 | return NULL; |
ae3db24a DV |
2737 | } |
2738 | ||
de151cf6 | 2739 | /** |
9a5a53b3 | 2740 | * i915_gem_object_get_fence - set up fencing for an object |
de151cf6 JB |
2741 | * @obj: object to map through a fence reg |
2742 | * | |
2743 | * When mapping objects through the GTT, userspace wants to be able to write | |
2744 | * to them without having to worry about swizzling if the object is tiled. | |
de151cf6 JB |
2745 | * This function walks the fence regs looking for a free one for @obj, |
2746 | * stealing one if it can't find any. | |
2747 | * | |
2748 | * It then sets up the reg based on the object's properties: address, pitch | |
2749 | * and tiling format. | |
9a5a53b3 CW |
2750 | * |
2751 | * For an untiled surface, this removes any existing fence. | |
de151cf6 | 2752 | */ |
8c4b8c3f | 2753 | int |
06d98131 | 2754 | i915_gem_object_get_fence(struct drm_i915_gem_object *obj) |
de151cf6 | 2755 | { |
05394f39 | 2756 | struct drm_device *dev = obj->base.dev; |
79e53945 | 2757 | struct drm_i915_private *dev_priv = dev->dev_private; |
14415745 | 2758 | bool enable = obj->tiling_mode != I915_TILING_NONE; |
d9e86c0e | 2759 | struct drm_i915_fence_reg *reg; |
ae3db24a | 2760 | int ret; |
de151cf6 | 2761 | |
14415745 CW |
2762 | /* Have we updated the tiling parameters upon the object and so |
2763 | * will need to serialise the write to the associated fence register? | |
2764 | */ | |
5d82e3e6 | 2765 | if (obj->fence_dirty) { |
14415745 CW |
2766 | ret = i915_gem_object_flush_fence(obj); |
2767 | if (ret) | |
2768 | return ret; | |
2769 | } | |
9a5a53b3 | 2770 | |
d9e86c0e | 2771 | /* Just update our place in the LRU if our fence is getting reused. */ |
05394f39 CW |
2772 | if (obj->fence_reg != I915_FENCE_REG_NONE) { |
2773 | reg = &dev_priv->fence_regs[obj->fence_reg]; | |
5d82e3e6 | 2774 | if (!obj->fence_dirty) { |
14415745 CW |
2775 | list_move_tail(®->lru_list, |
2776 | &dev_priv->mm.fence_list); | |
2777 | return 0; | |
2778 | } | |
2779 | } else if (enable) { | |
2780 | reg = i915_find_fence_reg(dev); | |
2781 | if (reg == NULL) | |
2782 | return -EDEADLK; | |
d9e86c0e | 2783 | |
14415745 CW |
2784 | if (reg->obj) { |
2785 | struct drm_i915_gem_object *old = reg->obj; | |
2786 | ||
2787 | ret = i915_gem_object_flush_fence(old); | |
29c5a587 CW |
2788 | if (ret) |
2789 | return ret; | |
2790 | ||
14415745 | 2791 | i915_gem_object_fence_lost(old); |
29c5a587 | 2792 | } |
14415745 | 2793 | } else |
a09ba7fa | 2794 | return 0; |
a09ba7fa | 2795 | |
14415745 | 2796 | i915_gem_object_update_fence(obj, reg, enable); |
5d82e3e6 | 2797 | obj->fence_dirty = false; |
14415745 | 2798 | |
9ce079e4 | 2799 | return 0; |
de151cf6 JB |
2800 | } |
2801 | ||
42d6ab48 CW |
2802 | static bool i915_gem_valid_gtt_space(struct drm_device *dev, |
2803 | struct drm_mm_node *gtt_space, | |
2804 | unsigned long cache_level) | |
2805 | { | |
2806 | struct drm_mm_node *other; | |
2807 | ||
2808 | /* On non-LLC machines we have to be careful when putting differing | |
2809 | * types of snoopable memory together to avoid the prefetcher | |
4239ca77 | 2810 | * crossing memory domains and dying. |
42d6ab48 CW |
2811 | */ |
2812 | if (HAS_LLC(dev)) | |
2813 | return true; | |
2814 | ||
2815 | if (gtt_space == NULL) | |
2816 | return true; | |
2817 | ||
2818 | if (list_empty(>t_space->node_list)) | |
2819 | return true; | |
2820 | ||
2821 | other = list_entry(gtt_space->node_list.prev, struct drm_mm_node, node_list); | |
2822 | if (other->allocated && !other->hole_follows && other->color != cache_level) | |
2823 | return false; | |
2824 | ||
2825 | other = list_entry(gtt_space->node_list.next, struct drm_mm_node, node_list); | |
2826 | if (other->allocated && !gtt_space->hole_follows && other->color != cache_level) | |
2827 | return false; | |
2828 | ||
2829 | return true; | |
2830 | } | |
2831 | ||
2832 | static void i915_gem_verify_gtt(struct drm_device *dev) | |
2833 | { | |
2834 | #if WATCH_GTT | |
2835 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2836 | struct drm_i915_gem_object *obj; | |
2837 | int err = 0; | |
2838 | ||
2839 | list_for_each_entry(obj, &dev_priv->mm.gtt_list, gtt_list) { | |
2840 | if (obj->gtt_space == NULL) { | |
2841 | printk(KERN_ERR "object found on GTT list with no space reserved\n"); | |
2842 | err++; | |
2843 | continue; | |
2844 | } | |
2845 | ||
2846 | if (obj->cache_level != obj->gtt_space->color) { | |
2847 | printk(KERN_ERR "object reserved space [%08lx, %08lx] with wrong color, cache_level=%x, color=%lx\n", | |
2848 | obj->gtt_space->start, | |
2849 | obj->gtt_space->start + obj->gtt_space->size, | |
2850 | obj->cache_level, | |
2851 | obj->gtt_space->color); | |
2852 | err++; | |
2853 | continue; | |
2854 | } | |
2855 | ||
2856 | if (!i915_gem_valid_gtt_space(dev, | |
2857 | obj->gtt_space, | |
2858 | obj->cache_level)) { | |
2859 | printk(KERN_ERR "invalid GTT space found at [%08lx, %08lx] - color=%x\n", | |
2860 | obj->gtt_space->start, | |
2861 | obj->gtt_space->start + obj->gtt_space->size, | |
2862 | obj->cache_level); | |
2863 | err++; | |
2864 | continue; | |
2865 | } | |
2866 | } | |
2867 | ||
2868 | WARN_ON(err); | |
2869 | #endif | |
2870 | } | |
2871 | ||
673a394b EA |
2872 | /** |
2873 | * Finds free space in the GTT aperture and binds the object there. | |
2874 | */ | |
2875 | static int | |
05394f39 | 2876 | i915_gem_object_bind_to_gtt(struct drm_i915_gem_object *obj, |
920afa77 | 2877 | unsigned alignment, |
86a1ee26 CW |
2878 | bool map_and_fenceable, |
2879 | bool nonblocking) | |
673a394b | 2880 | { |
05394f39 | 2881 | struct drm_device *dev = obj->base.dev; |
673a394b | 2882 | drm_i915_private_t *dev_priv = dev->dev_private; |
dc9dd7a2 | 2883 | struct drm_mm_node *node; |
5e783301 | 2884 | u32 size, fence_size, fence_alignment, unfenced_alignment; |
75e9e915 | 2885 | bool mappable, fenceable; |
07f73f69 | 2886 | int ret; |
673a394b | 2887 | |
e28f8711 CW |
2888 | fence_size = i915_gem_get_gtt_size(dev, |
2889 | obj->base.size, | |
2890 | obj->tiling_mode); | |
2891 | fence_alignment = i915_gem_get_gtt_alignment(dev, | |
2892 | obj->base.size, | |
d865110c | 2893 | obj->tiling_mode, true); |
e28f8711 | 2894 | unfenced_alignment = |
d865110c | 2895 | i915_gem_get_gtt_alignment(dev, |
e28f8711 | 2896 | obj->base.size, |
d865110c | 2897 | obj->tiling_mode, false); |
a00b10c3 | 2898 | |
673a394b | 2899 | if (alignment == 0) |
5e783301 DV |
2900 | alignment = map_and_fenceable ? fence_alignment : |
2901 | unfenced_alignment; | |
75e9e915 | 2902 | if (map_and_fenceable && alignment & (fence_alignment - 1)) { |
673a394b EA |
2903 | DRM_ERROR("Invalid object alignment requested %u\n", alignment); |
2904 | return -EINVAL; | |
2905 | } | |
2906 | ||
05394f39 | 2907 | size = map_and_fenceable ? fence_size : obj->base.size; |
a00b10c3 | 2908 | |
654fc607 CW |
2909 | /* If the object is bigger than the entire aperture, reject it early |
2910 | * before evicting everything in a vain attempt to find space. | |
2911 | */ | |
05394f39 | 2912 | if (obj->base.size > |
5d4545ae | 2913 | (map_and_fenceable ? dev_priv->gtt.mappable_end : dev_priv->gtt.total)) { |
654fc607 CW |
2914 | DRM_ERROR("Attempting to bind an object larger than the aperture\n"); |
2915 | return -E2BIG; | |
2916 | } | |
2917 | ||
37e680a1 | 2918 | ret = i915_gem_object_get_pages(obj); |
6c085a72 CW |
2919 | if (ret) |
2920 | return ret; | |
2921 | ||
fbdda6fb CW |
2922 | i915_gem_object_pin_pages(obj); |
2923 | ||
dc9dd7a2 CW |
2924 | node = kzalloc(sizeof(*node), GFP_KERNEL); |
2925 | if (node == NULL) { | |
2926 | i915_gem_object_unpin_pages(obj); | |
2927 | return -ENOMEM; | |
2928 | } | |
2929 | ||
673a394b | 2930 | search_free: |
75e9e915 | 2931 | if (map_and_fenceable) |
dc9dd7a2 CW |
2932 | ret = drm_mm_insert_node_in_range_generic(&dev_priv->mm.gtt_space, node, |
2933 | size, alignment, obj->cache_level, | |
5d4545ae | 2934 | 0, dev_priv->gtt.mappable_end); |
920afa77 | 2935 | else |
dc9dd7a2 CW |
2936 | ret = drm_mm_insert_node_generic(&dev_priv->mm.gtt_space, node, |
2937 | size, alignment, obj->cache_level); | |
2938 | if (ret) { | |
75e9e915 | 2939 | ret = i915_gem_evict_something(dev, size, alignment, |
42d6ab48 | 2940 | obj->cache_level, |
86a1ee26 CW |
2941 | map_and_fenceable, |
2942 | nonblocking); | |
dc9dd7a2 CW |
2943 | if (ret == 0) |
2944 | goto search_free; | |
9731129c | 2945 | |
dc9dd7a2 CW |
2946 | i915_gem_object_unpin_pages(obj); |
2947 | kfree(node); | |
2948 | return ret; | |
673a394b | 2949 | } |
dc9dd7a2 | 2950 | if (WARN_ON(!i915_gem_valid_gtt_space(dev, node, obj->cache_level))) { |
fbdda6fb | 2951 | i915_gem_object_unpin_pages(obj); |
dc9dd7a2 | 2952 | drm_mm_put_block(node); |
42d6ab48 | 2953 | return -EINVAL; |
673a394b EA |
2954 | } |
2955 | ||
74163907 | 2956 | ret = i915_gem_gtt_prepare_object(obj); |
7c2e6fdf | 2957 | if (ret) { |
fbdda6fb | 2958 | i915_gem_object_unpin_pages(obj); |
dc9dd7a2 | 2959 | drm_mm_put_block(node); |
6c085a72 | 2960 | return ret; |
673a394b | 2961 | } |
673a394b | 2962 | |
6c085a72 | 2963 | list_move_tail(&obj->gtt_list, &dev_priv->mm.bound_list); |
05394f39 | 2964 | list_add_tail(&obj->mm_list, &dev_priv->mm.inactive_list); |
bf1a1092 | 2965 | |
dc9dd7a2 CW |
2966 | obj->gtt_space = node; |
2967 | obj->gtt_offset = node->start; | |
1c5d22f7 | 2968 | |
75e9e915 | 2969 | fenceable = |
dc9dd7a2 CW |
2970 | node->size == fence_size && |
2971 | (node->start & (fence_alignment - 1)) == 0; | |
a00b10c3 | 2972 | |
75e9e915 | 2973 | mappable = |
5d4545ae | 2974 | obj->gtt_offset + obj->base.size <= dev_priv->gtt.mappable_end; |
a00b10c3 | 2975 | |
05394f39 | 2976 | obj->map_and_fenceable = mappable && fenceable; |
75e9e915 | 2977 | |
fbdda6fb | 2978 | i915_gem_object_unpin_pages(obj); |
db53a302 | 2979 | trace_i915_gem_object_bind(obj, map_and_fenceable); |
42d6ab48 | 2980 | i915_gem_verify_gtt(dev); |
673a394b EA |
2981 | return 0; |
2982 | } | |
2983 | ||
2984 | void | |
05394f39 | 2985 | i915_gem_clflush_object(struct drm_i915_gem_object *obj) |
673a394b | 2986 | { |
673a394b EA |
2987 | /* If we don't have a page list set up, then we're not pinned |
2988 | * to GPU, and we can ignore the cache flush because it'll happen | |
2989 | * again at bind time. | |
2990 | */ | |
05394f39 | 2991 | if (obj->pages == NULL) |
673a394b EA |
2992 | return; |
2993 | ||
9c23f7fc CW |
2994 | /* If the GPU is snooping the contents of the CPU cache, |
2995 | * we do not need to manually clear the CPU cache lines. However, | |
2996 | * the caches are only snooped when the render cache is | |
2997 | * flushed/invalidated. As we always have to emit invalidations | |
2998 | * and flushes when moving into and out of the RENDER domain, correct | |
2999 | * snooping behaviour occurs naturally as the result of our domain | |
3000 | * tracking. | |
3001 | */ | |
3002 | if (obj->cache_level != I915_CACHE_NONE) | |
3003 | return; | |
3004 | ||
1c5d22f7 | 3005 | trace_i915_gem_object_clflush(obj); |
cfa16a0d | 3006 | |
9da3da66 | 3007 | drm_clflush_sg(obj->pages); |
e47c68e9 EA |
3008 | } |
3009 | ||
3010 | /** Flushes the GTT write domain for the object if it's dirty. */ | |
3011 | static void | |
05394f39 | 3012 | i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj) |
e47c68e9 | 3013 | { |
1c5d22f7 CW |
3014 | uint32_t old_write_domain; |
3015 | ||
05394f39 | 3016 | if (obj->base.write_domain != I915_GEM_DOMAIN_GTT) |
e47c68e9 EA |
3017 | return; |
3018 | ||
63256ec5 | 3019 | /* No actual flushing is required for the GTT write domain. Writes |
e47c68e9 EA |
3020 | * to it immediately go to main memory as far as we know, so there's |
3021 | * no chipset flush. It also doesn't land in render cache. | |
63256ec5 CW |
3022 | * |
3023 | * However, we do have to enforce the order so that all writes through | |
3024 | * the GTT land before any writes to the device, such as updates to | |
3025 | * the GATT itself. | |
e47c68e9 | 3026 | */ |
63256ec5 CW |
3027 | wmb(); |
3028 | ||
05394f39 CW |
3029 | old_write_domain = obj->base.write_domain; |
3030 | obj->base.write_domain = 0; | |
1c5d22f7 CW |
3031 | |
3032 | trace_i915_gem_object_change_domain(obj, | |
05394f39 | 3033 | obj->base.read_domains, |
1c5d22f7 | 3034 | old_write_domain); |
e47c68e9 EA |
3035 | } |
3036 | ||
3037 | /** Flushes the CPU write domain for the object if it's dirty. */ | |
3038 | static void | |
05394f39 | 3039 | i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj) |
e47c68e9 | 3040 | { |
1c5d22f7 | 3041 | uint32_t old_write_domain; |
e47c68e9 | 3042 | |
05394f39 | 3043 | if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) |
e47c68e9 EA |
3044 | return; |
3045 | ||
3046 | i915_gem_clflush_object(obj); | |
e76e9aeb | 3047 | i915_gem_chipset_flush(obj->base.dev); |
05394f39 CW |
3048 | old_write_domain = obj->base.write_domain; |
3049 | obj->base.write_domain = 0; | |
1c5d22f7 CW |
3050 | |
3051 | trace_i915_gem_object_change_domain(obj, | |
05394f39 | 3052 | obj->base.read_domains, |
1c5d22f7 | 3053 | old_write_domain); |
e47c68e9 EA |
3054 | } |
3055 | ||
2ef7eeaa EA |
3056 | /** |
3057 | * Moves a single object to the GTT read, and possibly write domain. | |
3058 | * | |
3059 | * This function returns when the move is complete, including waiting on | |
3060 | * flushes to occur. | |
3061 | */ | |
79e53945 | 3062 | int |
2021746e | 3063 | i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write) |
2ef7eeaa | 3064 | { |
8325a09d | 3065 | drm_i915_private_t *dev_priv = obj->base.dev->dev_private; |
1c5d22f7 | 3066 | uint32_t old_write_domain, old_read_domains; |
e47c68e9 | 3067 | int ret; |
2ef7eeaa | 3068 | |
02354392 | 3069 | /* Not valid to be called on unbound objects. */ |
05394f39 | 3070 | if (obj->gtt_space == NULL) |
02354392 EA |
3071 | return -EINVAL; |
3072 | ||
8d7e3de1 CW |
3073 | if (obj->base.write_domain == I915_GEM_DOMAIN_GTT) |
3074 | return 0; | |
3075 | ||
0201f1ec | 3076 | ret = i915_gem_object_wait_rendering(obj, !write); |
88241785 CW |
3077 | if (ret) |
3078 | return ret; | |
3079 | ||
7213342d | 3080 | i915_gem_object_flush_cpu_write_domain(obj); |
1c5d22f7 | 3081 | |
05394f39 CW |
3082 | old_write_domain = obj->base.write_domain; |
3083 | old_read_domains = obj->base.read_domains; | |
1c5d22f7 | 3084 | |
e47c68e9 EA |
3085 | /* It should now be out of any other write domains, and we can update |
3086 | * the domain values for our changes. | |
3087 | */ | |
05394f39 CW |
3088 | BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) != 0); |
3089 | obj->base.read_domains |= I915_GEM_DOMAIN_GTT; | |
e47c68e9 | 3090 | if (write) { |
05394f39 CW |
3091 | obj->base.read_domains = I915_GEM_DOMAIN_GTT; |
3092 | obj->base.write_domain = I915_GEM_DOMAIN_GTT; | |
3093 | obj->dirty = 1; | |
2ef7eeaa EA |
3094 | } |
3095 | ||
1c5d22f7 CW |
3096 | trace_i915_gem_object_change_domain(obj, |
3097 | old_read_domains, | |
3098 | old_write_domain); | |
3099 | ||
8325a09d CW |
3100 | /* And bump the LRU for this access */ |
3101 | if (i915_gem_object_is_inactive(obj)) | |
3102 | list_move_tail(&obj->mm_list, &dev_priv->mm.inactive_list); | |
3103 | ||
e47c68e9 EA |
3104 | return 0; |
3105 | } | |
3106 | ||
e4ffd173 CW |
3107 | int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj, |
3108 | enum i915_cache_level cache_level) | |
3109 | { | |
7bddb01f DV |
3110 | struct drm_device *dev = obj->base.dev; |
3111 | drm_i915_private_t *dev_priv = dev->dev_private; | |
e4ffd173 CW |
3112 | int ret; |
3113 | ||
3114 | if (obj->cache_level == cache_level) | |
3115 | return 0; | |
3116 | ||
3117 | if (obj->pin_count) { | |
3118 | DRM_DEBUG("can not change the cache level of pinned objects\n"); | |
3119 | return -EBUSY; | |
3120 | } | |
3121 | ||
42d6ab48 CW |
3122 | if (!i915_gem_valid_gtt_space(dev, obj->gtt_space, cache_level)) { |
3123 | ret = i915_gem_object_unbind(obj); | |
3124 | if (ret) | |
3125 | return ret; | |
3126 | } | |
3127 | ||
e4ffd173 CW |
3128 | if (obj->gtt_space) { |
3129 | ret = i915_gem_object_finish_gpu(obj); | |
3130 | if (ret) | |
3131 | return ret; | |
3132 | ||
3133 | i915_gem_object_finish_gtt(obj); | |
3134 | ||
3135 | /* Before SandyBridge, you could not use tiling or fence | |
3136 | * registers with snooped memory, so relinquish any fences | |
3137 | * currently pointing to our region in the aperture. | |
3138 | */ | |
42d6ab48 | 3139 | if (INTEL_INFO(dev)->gen < 6) { |
e4ffd173 CW |
3140 | ret = i915_gem_object_put_fence(obj); |
3141 | if (ret) | |
3142 | return ret; | |
3143 | } | |
3144 | ||
74898d7e DV |
3145 | if (obj->has_global_gtt_mapping) |
3146 | i915_gem_gtt_bind_object(obj, cache_level); | |
7bddb01f DV |
3147 | if (obj->has_aliasing_ppgtt_mapping) |
3148 | i915_ppgtt_bind_object(dev_priv->mm.aliasing_ppgtt, | |
3149 | obj, cache_level); | |
42d6ab48 CW |
3150 | |
3151 | obj->gtt_space->color = cache_level; | |
e4ffd173 CW |
3152 | } |
3153 | ||
3154 | if (cache_level == I915_CACHE_NONE) { | |
3155 | u32 old_read_domains, old_write_domain; | |
3156 | ||
3157 | /* If we're coming from LLC cached, then we haven't | |
3158 | * actually been tracking whether the data is in the | |
3159 | * CPU cache or not, since we only allow one bit set | |
3160 | * in obj->write_domain and have been skipping the clflushes. | |
3161 | * Just set it to the CPU cache for now. | |
3162 | */ | |
3163 | WARN_ON(obj->base.write_domain & ~I915_GEM_DOMAIN_CPU); | |
3164 | WARN_ON(obj->base.read_domains & ~I915_GEM_DOMAIN_CPU); | |
3165 | ||
3166 | old_read_domains = obj->base.read_domains; | |
3167 | old_write_domain = obj->base.write_domain; | |
3168 | ||
3169 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; | |
3170 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; | |
3171 | ||
3172 | trace_i915_gem_object_change_domain(obj, | |
3173 | old_read_domains, | |
3174 | old_write_domain); | |
3175 | } | |
3176 | ||
3177 | obj->cache_level = cache_level; | |
42d6ab48 | 3178 | i915_gem_verify_gtt(dev); |
e4ffd173 CW |
3179 | return 0; |
3180 | } | |
3181 | ||
199adf40 BW |
3182 | int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data, |
3183 | struct drm_file *file) | |
e6994aee | 3184 | { |
199adf40 | 3185 | struct drm_i915_gem_caching *args = data; |
e6994aee CW |
3186 | struct drm_i915_gem_object *obj; |
3187 | int ret; | |
3188 | ||
3189 | ret = i915_mutex_lock_interruptible(dev); | |
3190 | if (ret) | |
3191 | return ret; | |
3192 | ||
3193 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); | |
3194 | if (&obj->base == NULL) { | |
3195 | ret = -ENOENT; | |
3196 | goto unlock; | |
3197 | } | |
3198 | ||
199adf40 | 3199 | args->caching = obj->cache_level != I915_CACHE_NONE; |
e6994aee CW |
3200 | |
3201 | drm_gem_object_unreference(&obj->base); | |
3202 | unlock: | |
3203 | mutex_unlock(&dev->struct_mutex); | |
3204 | return ret; | |
3205 | } | |
3206 | ||
199adf40 BW |
3207 | int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data, |
3208 | struct drm_file *file) | |
e6994aee | 3209 | { |
199adf40 | 3210 | struct drm_i915_gem_caching *args = data; |
e6994aee CW |
3211 | struct drm_i915_gem_object *obj; |
3212 | enum i915_cache_level level; | |
3213 | int ret; | |
3214 | ||
199adf40 BW |
3215 | switch (args->caching) { |
3216 | case I915_CACHING_NONE: | |
e6994aee CW |
3217 | level = I915_CACHE_NONE; |
3218 | break; | |
199adf40 | 3219 | case I915_CACHING_CACHED: |
e6994aee CW |
3220 | level = I915_CACHE_LLC; |
3221 | break; | |
3222 | default: | |
3223 | return -EINVAL; | |
3224 | } | |
3225 | ||
3bc2913e BW |
3226 | ret = i915_mutex_lock_interruptible(dev); |
3227 | if (ret) | |
3228 | return ret; | |
3229 | ||
e6994aee CW |
3230 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
3231 | if (&obj->base == NULL) { | |
3232 | ret = -ENOENT; | |
3233 | goto unlock; | |
3234 | } | |
3235 | ||
3236 | ret = i915_gem_object_set_cache_level(obj, level); | |
3237 | ||
3238 | drm_gem_object_unreference(&obj->base); | |
3239 | unlock: | |
3240 | mutex_unlock(&dev->struct_mutex); | |
3241 | return ret; | |
3242 | } | |
3243 | ||
b9241ea3 | 3244 | /* |
2da3b9b9 CW |
3245 | * Prepare buffer for display plane (scanout, cursors, etc). |
3246 | * Can be called from an uninterruptible phase (modesetting) and allows | |
3247 | * any flushes to be pipelined (for pageflips). | |
b9241ea3 ZW |
3248 | */ |
3249 | int | |
2da3b9b9 CW |
3250 | i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj, |
3251 | u32 alignment, | |
919926ae | 3252 | struct intel_ring_buffer *pipelined) |
b9241ea3 | 3253 | { |
2da3b9b9 | 3254 | u32 old_read_domains, old_write_domain; |
b9241ea3 ZW |
3255 | int ret; |
3256 | ||
0be73284 | 3257 | if (pipelined != obj->ring) { |
2911a35b BW |
3258 | ret = i915_gem_object_sync(obj, pipelined); |
3259 | if (ret) | |
b9241ea3 ZW |
3260 | return ret; |
3261 | } | |
3262 | ||
a7ef0640 EA |
3263 | /* The display engine is not coherent with the LLC cache on gen6. As |
3264 | * a result, we make sure that the pinning that is about to occur is | |
3265 | * done with uncached PTEs. This is lowest common denominator for all | |
3266 | * chipsets. | |
3267 | * | |
3268 | * However for gen6+, we could do better by using the GFDT bit instead | |
3269 | * of uncaching, which would allow us to flush all the LLC-cached data | |
3270 | * with that bit in the PTE to main memory with just one PIPE_CONTROL. | |
3271 | */ | |
3272 | ret = i915_gem_object_set_cache_level(obj, I915_CACHE_NONE); | |
3273 | if (ret) | |
3274 | return ret; | |
3275 | ||
2da3b9b9 CW |
3276 | /* As the user may map the buffer once pinned in the display plane |
3277 | * (e.g. libkms for the bootup splash), we have to ensure that we | |
3278 | * always use map_and_fenceable for all scanout buffers. | |
3279 | */ | |
86a1ee26 | 3280 | ret = i915_gem_object_pin(obj, alignment, true, false); |
2da3b9b9 CW |
3281 | if (ret) |
3282 | return ret; | |
3283 | ||
b118c1e3 CW |
3284 | i915_gem_object_flush_cpu_write_domain(obj); |
3285 | ||
2da3b9b9 | 3286 | old_write_domain = obj->base.write_domain; |
05394f39 | 3287 | old_read_domains = obj->base.read_domains; |
2da3b9b9 CW |
3288 | |
3289 | /* It should now be out of any other write domains, and we can update | |
3290 | * the domain values for our changes. | |
3291 | */ | |
e5f1d962 | 3292 | obj->base.write_domain = 0; |
05394f39 | 3293 | obj->base.read_domains |= I915_GEM_DOMAIN_GTT; |
b9241ea3 ZW |
3294 | |
3295 | trace_i915_gem_object_change_domain(obj, | |
3296 | old_read_domains, | |
2da3b9b9 | 3297 | old_write_domain); |
b9241ea3 ZW |
3298 | |
3299 | return 0; | |
3300 | } | |
3301 | ||
85345517 | 3302 | int |
a8198eea | 3303 | i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj) |
85345517 | 3304 | { |
88241785 CW |
3305 | int ret; |
3306 | ||
a8198eea | 3307 | if ((obj->base.read_domains & I915_GEM_GPU_DOMAINS) == 0) |
85345517 CW |
3308 | return 0; |
3309 | ||
0201f1ec | 3310 | ret = i915_gem_object_wait_rendering(obj, false); |
c501ae7f CW |
3311 | if (ret) |
3312 | return ret; | |
3313 | ||
a8198eea CW |
3314 | /* Ensure that we invalidate the GPU's caches and TLBs. */ |
3315 | obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS; | |
c501ae7f | 3316 | return 0; |
85345517 CW |
3317 | } |
3318 | ||
e47c68e9 EA |
3319 | /** |
3320 | * Moves a single object to the CPU read, and possibly write domain. | |
3321 | * | |
3322 | * This function returns when the move is complete, including waiting on | |
3323 | * flushes to occur. | |
3324 | */ | |
dabdfe02 | 3325 | int |
919926ae | 3326 | i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write) |
e47c68e9 | 3327 | { |
1c5d22f7 | 3328 | uint32_t old_write_domain, old_read_domains; |
e47c68e9 EA |
3329 | int ret; |
3330 | ||
8d7e3de1 CW |
3331 | if (obj->base.write_domain == I915_GEM_DOMAIN_CPU) |
3332 | return 0; | |
3333 | ||
0201f1ec | 3334 | ret = i915_gem_object_wait_rendering(obj, !write); |
88241785 CW |
3335 | if (ret) |
3336 | return ret; | |
3337 | ||
e47c68e9 | 3338 | i915_gem_object_flush_gtt_write_domain(obj); |
2ef7eeaa | 3339 | |
05394f39 CW |
3340 | old_write_domain = obj->base.write_domain; |
3341 | old_read_domains = obj->base.read_domains; | |
1c5d22f7 | 3342 | |
e47c68e9 | 3343 | /* Flush the CPU cache if it's still invalid. */ |
05394f39 | 3344 | if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) { |
2ef7eeaa | 3345 | i915_gem_clflush_object(obj); |
2ef7eeaa | 3346 | |
05394f39 | 3347 | obj->base.read_domains |= I915_GEM_DOMAIN_CPU; |
2ef7eeaa EA |
3348 | } |
3349 | ||
3350 | /* It should now be out of any other write domains, and we can update | |
3351 | * the domain values for our changes. | |
3352 | */ | |
05394f39 | 3353 | BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) != 0); |
e47c68e9 EA |
3354 | |
3355 | /* If we're writing through the CPU, then the GPU read domains will | |
3356 | * need to be invalidated at next use. | |
3357 | */ | |
3358 | if (write) { | |
05394f39 CW |
3359 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; |
3360 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; | |
e47c68e9 | 3361 | } |
2ef7eeaa | 3362 | |
1c5d22f7 CW |
3363 | trace_i915_gem_object_change_domain(obj, |
3364 | old_read_domains, | |
3365 | old_write_domain); | |
3366 | ||
2ef7eeaa EA |
3367 | return 0; |
3368 | } | |
3369 | ||
673a394b EA |
3370 | /* Throttle our rendering by waiting until the ring has completed our requests |
3371 | * emitted over 20 msec ago. | |
3372 | * | |
b962442e EA |
3373 | * Note that if we were to use the current jiffies each time around the loop, |
3374 | * we wouldn't escape the function with any frames outstanding if the time to | |
3375 | * render a frame was over 20ms. | |
3376 | * | |
673a394b EA |
3377 | * This should get us reasonable parallelism between CPU and GPU but also |
3378 | * relatively low latency when blocking on a particular request to finish. | |
3379 | */ | |
40a5f0de | 3380 | static int |
f787a5f5 | 3381 | i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file) |
40a5f0de | 3382 | { |
f787a5f5 CW |
3383 | struct drm_i915_private *dev_priv = dev->dev_private; |
3384 | struct drm_i915_file_private *file_priv = file->driver_priv; | |
b962442e | 3385 | unsigned long recent_enough = jiffies - msecs_to_jiffies(20); |
f787a5f5 CW |
3386 | struct drm_i915_gem_request *request; |
3387 | struct intel_ring_buffer *ring = NULL; | |
3388 | u32 seqno = 0; | |
3389 | int ret; | |
93533c29 | 3390 | |
e110e8d6 CW |
3391 | if (atomic_read(&dev_priv->mm.wedged)) |
3392 | return -EIO; | |
3393 | ||
1c25595f | 3394 | spin_lock(&file_priv->mm.lock); |
f787a5f5 | 3395 | list_for_each_entry(request, &file_priv->mm.request_list, client_list) { |
b962442e EA |
3396 | if (time_after_eq(request->emitted_jiffies, recent_enough)) |
3397 | break; | |
40a5f0de | 3398 | |
f787a5f5 CW |
3399 | ring = request->ring; |
3400 | seqno = request->seqno; | |
b962442e | 3401 | } |
1c25595f | 3402 | spin_unlock(&file_priv->mm.lock); |
40a5f0de | 3403 | |
f787a5f5 CW |
3404 | if (seqno == 0) |
3405 | return 0; | |
2bc43b5c | 3406 | |
5c81fe85 | 3407 | ret = __wait_seqno(ring, seqno, true, NULL); |
f787a5f5 CW |
3408 | if (ret == 0) |
3409 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, 0); | |
40a5f0de EA |
3410 | |
3411 | return ret; | |
3412 | } | |
3413 | ||
673a394b | 3414 | int |
05394f39 CW |
3415 | i915_gem_object_pin(struct drm_i915_gem_object *obj, |
3416 | uint32_t alignment, | |
86a1ee26 CW |
3417 | bool map_and_fenceable, |
3418 | bool nonblocking) | |
673a394b | 3419 | { |
673a394b EA |
3420 | int ret; |
3421 | ||
7e81a42e CW |
3422 | if (WARN_ON(obj->pin_count == DRM_I915_GEM_OBJECT_MAX_PIN_COUNT)) |
3423 | return -EBUSY; | |
ac0c6b5a | 3424 | |
05394f39 CW |
3425 | if (obj->gtt_space != NULL) { |
3426 | if ((alignment && obj->gtt_offset & (alignment - 1)) || | |
3427 | (map_and_fenceable && !obj->map_and_fenceable)) { | |
3428 | WARN(obj->pin_count, | |
ae7d49d8 | 3429 | "bo is already pinned with incorrect alignment:" |
75e9e915 DV |
3430 | " offset=%x, req.alignment=%x, req.map_and_fenceable=%d," |
3431 | " obj->map_and_fenceable=%d\n", | |
05394f39 | 3432 | obj->gtt_offset, alignment, |
75e9e915 | 3433 | map_and_fenceable, |
05394f39 | 3434 | obj->map_and_fenceable); |
ac0c6b5a CW |
3435 | ret = i915_gem_object_unbind(obj); |
3436 | if (ret) | |
3437 | return ret; | |
3438 | } | |
3439 | } | |
3440 | ||
05394f39 | 3441 | if (obj->gtt_space == NULL) { |
8742267a CW |
3442 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
3443 | ||
a00b10c3 | 3444 | ret = i915_gem_object_bind_to_gtt(obj, alignment, |
86a1ee26 CW |
3445 | map_and_fenceable, |
3446 | nonblocking); | |
9731129c | 3447 | if (ret) |
673a394b | 3448 | return ret; |
8742267a CW |
3449 | |
3450 | if (!dev_priv->mm.aliasing_ppgtt) | |
3451 | i915_gem_gtt_bind_object(obj, obj->cache_level); | |
22c344e9 | 3452 | } |
76446cac | 3453 | |
74898d7e DV |
3454 | if (!obj->has_global_gtt_mapping && map_and_fenceable) |
3455 | i915_gem_gtt_bind_object(obj, obj->cache_level); | |
3456 | ||
1b50247a | 3457 | obj->pin_count++; |
6299f992 | 3458 | obj->pin_mappable |= map_and_fenceable; |
673a394b EA |
3459 | |
3460 | return 0; | |
3461 | } | |
3462 | ||
3463 | void | |
05394f39 | 3464 | i915_gem_object_unpin(struct drm_i915_gem_object *obj) |
673a394b | 3465 | { |
05394f39 CW |
3466 | BUG_ON(obj->pin_count == 0); |
3467 | BUG_ON(obj->gtt_space == NULL); | |
673a394b | 3468 | |
1b50247a | 3469 | if (--obj->pin_count == 0) |
6299f992 | 3470 | obj->pin_mappable = false; |
673a394b EA |
3471 | } |
3472 | ||
3473 | int | |
3474 | i915_gem_pin_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 3475 | struct drm_file *file) |
673a394b EA |
3476 | { |
3477 | struct drm_i915_gem_pin *args = data; | |
05394f39 | 3478 | struct drm_i915_gem_object *obj; |
673a394b EA |
3479 | int ret; |
3480 | ||
1d7cfea1 CW |
3481 | ret = i915_mutex_lock_interruptible(dev); |
3482 | if (ret) | |
3483 | return ret; | |
673a394b | 3484 | |
05394f39 | 3485 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 3486 | if (&obj->base == NULL) { |
1d7cfea1 CW |
3487 | ret = -ENOENT; |
3488 | goto unlock; | |
673a394b | 3489 | } |
673a394b | 3490 | |
05394f39 | 3491 | if (obj->madv != I915_MADV_WILLNEED) { |
bb6baf76 | 3492 | DRM_ERROR("Attempting to pin a purgeable buffer\n"); |
1d7cfea1 CW |
3493 | ret = -EINVAL; |
3494 | goto out; | |
3ef94daa CW |
3495 | } |
3496 | ||
05394f39 | 3497 | if (obj->pin_filp != NULL && obj->pin_filp != file) { |
79e53945 JB |
3498 | DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n", |
3499 | args->handle); | |
1d7cfea1 CW |
3500 | ret = -EINVAL; |
3501 | goto out; | |
79e53945 JB |
3502 | } |
3503 | ||
05394f39 CW |
3504 | obj->user_pin_count++; |
3505 | obj->pin_filp = file; | |
3506 | if (obj->user_pin_count == 1) { | |
86a1ee26 | 3507 | ret = i915_gem_object_pin(obj, args->alignment, true, false); |
1d7cfea1 CW |
3508 | if (ret) |
3509 | goto out; | |
673a394b EA |
3510 | } |
3511 | ||
3512 | /* XXX - flush the CPU caches for pinned objects | |
3513 | * as the X server doesn't manage domains yet | |
3514 | */ | |
e47c68e9 | 3515 | i915_gem_object_flush_cpu_write_domain(obj); |
05394f39 | 3516 | args->offset = obj->gtt_offset; |
1d7cfea1 | 3517 | out: |
05394f39 | 3518 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 3519 | unlock: |
673a394b | 3520 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 3521 | return ret; |
673a394b EA |
3522 | } |
3523 | ||
3524 | int | |
3525 | i915_gem_unpin_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 3526 | struct drm_file *file) |
673a394b EA |
3527 | { |
3528 | struct drm_i915_gem_pin *args = data; | |
05394f39 | 3529 | struct drm_i915_gem_object *obj; |
76c1dec1 | 3530 | int ret; |
673a394b | 3531 | |
1d7cfea1 CW |
3532 | ret = i915_mutex_lock_interruptible(dev); |
3533 | if (ret) | |
3534 | return ret; | |
673a394b | 3535 | |
05394f39 | 3536 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 3537 | if (&obj->base == NULL) { |
1d7cfea1 CW |
3538 | ret = -ENOENT; |
3539 | goto unlock; | |
673a394b | 3540 | } |
76c1dec1 | 3541 | |
05394f39 | 3542 | if (obj->pin_filp != file) { |
79e53945 JB |
3543 | DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n", |
3544 | args->handle); | |
1d7cfea1 CW |
3545 | ret = -EINVAL; |
3546 | goto out; | |
79e53945 | 3547 | } |
05394f39 CW |
3548 | obj->user_pin_count--; |
3549 | if (obj->user_pin_count == 0) { | |
3550 | obj->pin_filp = NULL; | |
79e53945 JB |
3551 | i915_gem_object_unpin(obj); |
3552 | } | |
673a394b | 3553 | |
1d7cfea1 | 3554 | out: |
05394f39 | 3555 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 3556 | unlock: |
673a394b | 3557 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 3558 | return ret; |
673a394b EA |
3559 | } |
3560 | ||
3561 | int | |
3562 | i915_gem_busy_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 3563 | struct drm_file *file) |
673a394b EA |
3564 | { |
3565 | struct drm_i915_gem_busy *args = data; | |
05394f39 | 3566 | struct drm_i915_gem_object *obj; |
30dbf0c0 CW |
3567 | int ret; |
3568 | ||
76c1dec1 | 3569 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 3570 | if (ret) |
76c1dec1 | 3571 | return ret; |
673a394b | 3572 | |
05394f39 | 3573 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 3574 | if (&obj->base == NULL) { |
1d7cfea1 CW |
3575 | ret = -ENOENT; |
3576 | goto unlock; | |
673a394b | 3577 | } |
d1b851fc | 3578 | |
0be555b6 CW |
3579 | /* Count all active objects as busy, even if they are currently not used |
3580 | * by the gpu. Users of this interface expect objects to eventually | |
3581 | * become non-busy without any further actions, therefore emit any | |
3582 | * necessary flushes here. | |
c4de0a5d | 3583 | */ |
30dfebf3 | 3584 | ret = i915_gem_object_flush_active(obj); |
0be555b6 | 3585 | |
30dfebf3 | 3586 | args->busy = obj->active; |
e9808edd CW |
3587 | if (obj->ring) { |
3588 | BUILD_BUG_ON(I915_NUM_RINGS > 16); | |
3589 | args->busy |= intel_ring_flag(obj->ring) << 16; | |
3590 | } | |
673a394b | 3591 | |
05394f39 | 3592 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 3593 | unlock: |
673a394b | 3594 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 3595 | return ret; |
673a394b EA |
3596 | } |
3597 | ||
3598 | int | |
3599 | i915_gem_throttle_ioctl(struct drm_device *dev, void *data, | |
3600 | struct drm_file *file_priv) | |
3601 | { | |
0206e353 | 3602 | return i915_gem_ring_throttle(dev, file_priv); |
673a394b EA |
3603 | } |
3604 | ||
3ef94daa CW |
3605 | int |
3606 | i915_gem_madvise_ioctl(struct drm_device *dev, void *data, | |
3607 | struct drm_file *file_priv) | |
3608 | { | |
3609 | struct drm_i915_gem_madvise *args = data; | |
05394f39 | 3610 | struct drm_i915_gem_object *obj; |
76c1dec1 | 3611 | int ret; |
3ef94daa CW |
3612 | |
3613 | switch (args->madv) { | |
3614 | case I915_MADV_DONTNEED: | |
3615 | case I915_MADV_WILLNEED: | |
3616 | break; | |
3617 | default: | |
3618 | return -EINVAL; | |
3619 | } | |
3620 | ||
1d7cfea1 CW |
3621 | ret = i915_mutex_lock_interruptible(dev); |
3622 | if (ret) | |
3623 | return ret; | |
3624 | ||
05394f39 | 3625 | obj = to_intel_bo(drm_gem_object_lookup(dev, file_priv, args->handle)); |
c8725226 | 3626 | if (&obj->base == NULL) { |
1d7cfea1 CW |
3627 | ret = -ENOENT; |
3628 | goto unlock; | |
3ef94daa | 3629 | } |
3ef94daa | 3630 | |
05394f39 | 3631 | if (obj->pin_count) { |
1d7cfea1 CW |
3632 | ret = -EINVAL; |
3633 | goto out; | |
3ef94daa CW |
3634 | } |
3635 | ||
05394f39 CW |
3636 | if (obj->madv != __I915_MADV_PURGED) |
3637 | obj->madv = args->madv; | |
3ef94daa | 3638 | |
6c085a72 CW |
3639 | /* if the object is no longer attached, discard its backing storage */ |
3640 | if (i915_gem_object_is_purgeable(obj) && obj->pages == NULL) | |
2d7ef395 CW |
3641 | i915_gem_object_truncate(obj); |
3642 | ||
05394f39 | 3643 | args->retained = obj->madv != __I915_MADV_PURGED; |
bb6baf76 | 3644 | |
1d7cfea1 | 3645 | out: |
05394f39 | 3646 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 3647 | unlock: |
3ef94daa | 3648 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 3649 | return ret; |
3ef94daa CW |
3650 | } |
3651 | ||
37e680a1 CW |
3652 | void i915_gem_object_init(struct drm_i915_gem_object *obj, |
3653 | const struct drm_i915_gem_object_ops *ops) | |
0327d6ba | 3654 | { |
0327d6ba CW |
3655 | INIT_LIST_HEAD(&obj->mm_list); |
3656 | INIT_LIST_HEAD(&obj->gtt_list); | |
3657 | INIT_LIST_HEAD(&obj->ring_list); | |
3658 | INIT_LIST_HEAD(&obj->exec_list); | |
3659 | ||
37e680a1 CW |
3660 | obj->ops = ops; |
3661 | ||
0327d6ba CW |
3662 | obj->fence_reg = I915_FENCE_REG_NONE; |
3663 | obj->madv = I915_MADV_WILLNEED; | |
3664 | /* Avoid an unnecessary call to unbind on the first bind. */ | |
3665 | obj->map_and_fenceable = true; | |
3666 | ||
3667 | i915_gem_info_add_obj(obj->base.dev->dev_private, obj->base.size); | |
3668 | } | |
3669 | ||
37e680a1 CW |
3670 | static const struct drm_i915_gem_object_ops i915_gem_object_ops = { |
3671 | .get_pages = i915_gem_object_get_pages_gtt, | |
3672 | .put_pages = i915_gem_object_put_pages_gtt, | |
3673 | }; | |
3674 | ||
05394f39 CW |
3675 | struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev, |
3676 | size_t size) | |
ac52bc56 | 3677 | { |
c397b908 | 3678 | struct drm_i915_gem_object *obj; |
5949eac4 | 3679 | struct address_space *mapping; |
1a240d4d | 3680 | gfp_t mask; |
ac52bc56 | 3681 | |
42dcedd4 | 3682 | obj = i915_gem_object_alloc(dev); |
c397b908 DV |
3683 | if (obj == NULL) |
3684 | return NULL; | |
673a394b | 3685 | |
c397b908 | 3686 | if (drm_gem_object_init(dev, &obj->base, size) != 0) { |
42dcedd4 | 3687 | i915_gem_object_free(obj); |
c397b908 DV |
3688 | return NULL; |
3689 | } | |
673a394b | 3690 | |
bed1ea95 CW |
3691 | mask = GFP_HIGHUSER | __GFP_RECLAIMABLE; |
3692 | if (IS_CRESTLINE(dev) || IS_BROADWATER(dev)) { | |
3693 | /* 965gm cannot relocate objects above 4GiB. */ | |
3694 | mask &= ~__GFP_HIGHMEM; | |
3695 | mask |= __GFP_DMA32; | |
3696 | } | |
3697 | ||
5949eac4 | 3698 | mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping; |
bed1ea95 | 3699 | mapping_set_gfp_mask(mapping, mask); |
5949eac4 | 3700 | |
37e680a1 | 3701 | i915_gem_object_init(obj, &i915_gem_object_ops); |
73aa808f | 3702 | |
c397b908 DV |
3703 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; |
3704 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; | |
673a394b | 3705 | |
3d29b842 ED |
3706 | if (HAS_LLC(dev)) { |
3707 | /* On some devices, we can have the GPU use the LLC (the CPU | |
a1871112 EA |
3708 | * cache) for about a 10% performance improvement |
3709 | * compared to uncached. Graphics requests other than | |
3710 | * display scanout are coherent with the CPU in | |
3711 | * accessing this cache. This means in this mode we | |
3712 | * don't need to clflush on the CPU side, and on the | |
3713 | * GPU side we only need to flush internal caches to | |
3714 | * get data visible to the CPU. | |
3715 | * | |
3716 | * However, we maintain the display planes as UC, and so | |
3717 | * need to rebind when first used as such. | |
3718 | */ | |
3719 | obj->cache_level = I915_CACHE_LLC; | |
3720 | } else | |
3721 | obj->cache_level = I915_CACHE_NONE; | |
3722 | ||
05394f39 | 3723 | return obj; |
c397b908 DV |
3724 | } |
3725 | ||
3726 | int i915_gem_init_object(struct drm_gem_object *obj) | |
3727 | { | |
3728 | BUG(); | |
de151cf6 | 3729 | |
673a394b EA |
3730 | return 0; |
3731 | } | |
3732 | ||
1488fc08 | 3733 | void i915_gem_free_object(struct drm_gem_object *gem_obj) |
673a394b | 3734 | { |
1488fc08 | 3735 | struct drm_i915_gem_object *obj = to_intel_bo(gem_obj); |
05394f39 | 3736 | struct drm_device *dev = obj->base.dev; |
be72615b | 3737 | drm_i915_private_t *dev_priv = dev->dev_private; |
673a394b | 3738 | |
26e12f89 CW |
3739 | trace_i915_gem_object_destroy(obj); |
3740 | ||
1488fc08 CW |
3741 | if (obj->phys_obj) |
3742 | i915_gem_detach_phys_object(dev, obj); | |
3743 | ||
3744 | obj->pin_count = 0; | |
3745 | if (WARN_ON(i915_gem_object_unbind(obj) == -ERESTARTSYS)) { | |
3746 | bool was_interruptible; | |
3747 | ||
3748 | was_interruptible = dev_priv->mm.interruptible; | |
3749 | dev_priv->mm.interruptible = false; | |
3750 | ||
3751 | WARN_ON(i915_gem_object_unbind(obj)); | |
3752 | ||
3753 | dev_priv->mm.interruptible = was_interruptible; | |
3754 | } | |
3755 | ||
a5570178 | 3756 | obj->pages_pin_count = 0; |
37e680a1 | 3757 | i915_gem_object_put_pages(obj); |
d8cb5086 | 3758 | i915_gem_object_free_mmap_offset(obj); |
0104fdbb | 3759 | i915_gem_object_release_stolen(obj); |
de151cf6 | 3760 | |
9da3da66 CW |
3761 | BUG_ON(obj->pages); |
3762 | ||
2f745ad3 CW |
3763 | if (obj->base.import_attach) |
3764 | drm_prime_gem_destroy(&obj->base, NULL); | |
de151cf6 | 3765 | |
05394f39 CW |
3766 | drm_gem_object_release(&obj->base); |
3767 | i915_gem_info_remove_obj(dev_priv, obj->base.size); | |
c397b908 | 3768 | |
05394f39 | 3769 | kfree(obj->bit_17); |
42dcedd4 | 3770 | i915_gem_object_free(obj); |
673a394b EA |
3771 | } |
3772 | ||
29105ccc CW |
3773 | int |
3774 | i915_gem_idle(struct drm_device *dev) | |
3775 | { | |
3776 | drm_i915_private_t *dev_priv = dev->dev_private; | |
3777 | int ret; | |
28dfe52a | 3778 | |
29105ccc | 3779 | mutex_lock(&dev->struct_mutex); |
1c5d22f7 | 3780 | |
87acb0a5 | 3781 | if (dev_priv->mm.suspended) { |
29105ccc CW |
3782 | mutex_unlock(&dev->struct_mutex); |
3783 | return 0; | |
28dfe52a EA |
3784 | } |
3785 | ||
b2da9fe5 | 3786 | ret = i915_gpu_idle(dev); |
6dbe2772 KP |
3787 | if (ret) { |
3788 | mutex_unlock(&dev->struct_mutex); | |
673a394b | 3789 | return ret; |
6dbe2772 | 3790 | } |
b2da9fe5 | 3791 | i915_gem_retire_requests(dev); |
673a394b | 3792 | |
29105ccc | 3793 | /* Under UMS, be paranoid and evict. */ |
a39d7efc | 3794 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) |
6c085a72 | 3795 | i915_gem_evict_everything(dev); |
29105ccc | 3796 | |
312817a3 CW |
3797 | i915_gem_reset_fences(dev); |
3798 | ||
29105ccc CW |
3799 | /* Hack! Don't let anybody do execbuf while we don't control the chip. |
3800 | * We need to replace this with a semaphore, or something. | |
3801 | * And not confound mm.suspended! | |
3802 | */ | |
3803 | dev_priv->mm.suspended = 1; | |
bc0c7f14 | 3804 | del_timer_sync(&dev_priv->hangcheck_timer); |
29105ccc CW |
3805 | |
3806 | i915_kernel_lost_context(dev); | |
6dbe2772 | 3807 | i915_gem_cleanup_ringbuffer(dev); |
29105ccc | 3808 | |
6dbe2772 KP |
3809 | mutex_unlock(&dev->struct_mutex); |
3810 | ||
29105ccc CW |
3811 | /* Cancel the retire work handler, which should be idle now. */ |
3812 | cancel_delayed_work_sync(&dev_priv->mm.retire_work); | |
3813 | ||
673a394b EA |
3814 | return 0; |
3815 | } | |
3816 | ||
b9524a1e BW |
3817 | void i915_gem_l3_remap(struct drm_device *dev) |
3818 | { | |
3819 | drm_i915_private_t *dev_priv = dev->dev_private; | |
3820 | u32 misccpctl; | |
3821 | int i; | |
3822 | ||
3823 | if (!IS_IVYBRIDGE(dev)) | |
3824 | return; | |
3825 | ||
a4da4fa4 | 3826 | if (!dev_priv->l3_parity.remap_info) |
b9524a1e BW |
3827 | return; |
3828 | ||
3829 | misccpctl = I915_READ(GEN7_MISCCPCTL); | |
3830 | I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE); | |
3831 | POSTING_READ(GEN7_MISCCPCTL); | |
3832 | ||
3833 | for (i = 0; i < GEN7_L3LOG_SIZE; i += 4) { | |
3834 | u32 remap = I915_READ(GEN7_L3LOG_BASE + i); | |
a4da4fa4 | 3835 | if (remap && remap != dev_priv->l3_parity.remap_info[i/4]) |
b9524a1e BW |
3836 | DRM_DEBUG("0x%x was already programmed to %x\n", |
3837 | GEN7_L3LOG_BASE + i, remap); | |
a4da4fa4 | 3838 | if (remap && !dev_priv->l3_parity.remap_info[i/4]) |
b9524a1e | 3839 | DRM_DEBUG_DRIVER("Clearing remapped register\n"); |
a4da4fa4 | 3840 | I915_WRITE(GEN7_L3LOG_BASE + i, dev_priv->l3_parity.remap_info[i/4]); |
b9524a1e BW |
3841 | } |
3842 | ||
3843 | /* Make sure all the writes land before disabling dop clock gating */ | |
3844 | POSTING_READ(GEN7_L3LOG_BASE); | |
3845 | ||
3846 | I915_WRITE(GEN7_MISCCPCTL, misccpctl); | |
3847 | } | |
3848 | ||
f691e2f4 DV |
3849 | void i915_gem_init_swizzling(struct drm_device *dev) |
3850 | { | |
3851 | drm_i915_private_t *dev_priv = dev->dev_private; | |
3852 | ||
11782b02 | 3853 | if (INTEL_INFO(dev)->gen < 5 || |
f691e2f4 DV |
3854 | dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE) |
3855 | return; | |
3856 | ||
3857 | I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) | | |
3858 | DISP_TILE_SURFACE_SWIZZLING); | |
3859 | ||
11782b02 DV |
3860 | if (IS_GEN5(dev)) |
3861 | return; | |
3862 | ||
f691e2f4 DV |
3863 | I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_SWZCTL); |
3864 | if (IS_GEN6(dev)) | |
6b26c86d | 3865 | I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB)); |
8782e26c | 3866 | else if (IS_GEN7(dev)) |
6b26c86d | 3867 | I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB)); |
8782e26c BW |
3868 | else |
3869 | BUG(); | |
f691e2f4 | 3870 | } |
e21af88d | 3871 | |
67b1b571 CW |
3872 | static bool |
3873 | intel_enable_blt(struct drm_device *dev) | |
3874 | { | |
3875 | if (!HAS_BLT(dev)) | |
3876 | return false; | |
3877 | ||
3878 | /* The blitter was dysfunctional on early prototypes */ | |
3879 | if (IS_GEN6(dev) && dev->pdev->revision < 8) { | |
3880 | DRM_INFO("BLT not supported on this pre-production hardware;" | |
3881 | " graphics performance will be degraded.\n"); | |
3882 | return false; | |
3883 | } | |
3884 | ||
3885 | return true; | |
3886 | } | |
3887 | ||
8187a2b7 | 3888 | int |
f691e2f4 | 3889 | i915_gem_init_hw(struct drm_device *dev) |
8187a2b7 ZN |
3890 | { |
3891 | drm_i915_private_t *dev_priv = dev->dev_private; | |
3892 | int ret; | |
68f95ba9 | 3893 | |
e76e9aeb | 3894 | if (INTEL_INFO(dev)->gen < 6 && !intel_enable_gtt()) |
8ecd1a66 DV |
3895 | return -EIO; |
3896 | ||
eda2d7f5 RV |
3897 | if (IS_HASWELL(dev) && (I915_READ(0x120010) == 1)) |
3898 | I915_WRITE(0x9008, I915_READ(0x9008) | 0xf0000); | |
3899 | ||
b9524a1e BW |
3900 | i915_gem_l3_remap(dev); |
3901 | ||
f691e2f4 DV |
3902 | i915_gem_init_swizzling(dev); |
3903 | ||
f7e98ad4 MK |
3904 | dev_priv->next_seqno = dev_priv->last_seqno = (u32)~0 - 0x1000; |
3905 | ||
5c1143bb | 3906 | ret = intel_init_render_ring_buffer(dev); |
68f95ba9 | 3907 | if (ret) |
b6913e4b | 3908 | return ret; |
68f95ba9 CW |
3909 | |
3910 | if (HAS_BSD(dev)) { | |
5c1143bb | 3911 | ret = intel_init_bsd_ring_buffer(dev); |
68f95ba9 CW |
3912 | if (ret) |
3913 | goto cleanup_render_ring; | |
d1b851fc | 3914 | } |
68f95ba9 | 3915 | |
67b1b571 | 3916 | if (intel_enable_blt(dev)) { |
549f7365 CW |
3917 | ret = intel_init_blt_ring_buffer(dev); |
3918 | if (ret) | |
3919 | goto cleanup_bsd_ring; | |
3920 | } | |
3921 | ||
254f965c BW |
3922 | /* |
3923 | * XXX: There was some w/a described somewhere suggesting loading | |
3924 | * contexts before PPGTT. | |
3925 | */ | |
3926 | i915_gem_context_init(dev); | |
e21af88d DV |
3927 | i915_gem_init_ppgtt(dev); |
3928 | ||
68f95ba9 CW |
3929 | return 0; |
3930 | ||
549f7365 | 3931 | cleanup_bsd_ring: |
1ec14ad3 | 3932 | intel_cleanup_ring_buffer(&dev_priv->ring[VCS]); |
68f95ba9 | 3933 | cleanup_render_ring: |
1ec14ad3 | 3934 | intel_cleanup_ring_buffer(&dev_priv->ring[RCS]); |
8187a2b7 ZN |
3935 | return ret; |
3936 | } | |
3937 | ||
1070a42b CW |
3938 | int i915_gem_init(struct drm_device *dev) |
3939 | { | |
3940 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1070a42b CW |
3941 | int ret; |
3942 | ||
1070a42b | 3943 | mutex_lock(&dev->struct_mutex); |
d7e5008f | 3944 | i915_gem_init_global_gtt(dev); |
1070a42b CW |
3945 | ret = i915_gem_init_hw(dev); |
3946 | mutex_unlock(&dev->struct_mutex); | |
3947 | if (ret) { | |
3948 | i915_gem_cleanup_aliasing_ppgtt(dev); | |
3949 | return ret; | |
3950 | } | |
3951 | ||
53ca26ca DV |
3952 | /* Allow hardware batchbuffers unless told otherwise, but not for KMS. */ |
3953 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) | |
3954 | dev_priv->dri1.allow_batchbuffer = 1; | |
1070a42b CW |
3955 | return 0; |
3956 | } | |
3957 | ||
8187a2b7 ZN |
3958 | void |
3959 | i915_gem_cleanup_ringbuffer(struct drm_device *dev) | |
3960 | { | |
3961 | drm_i915_private_t *dev_priv = dev->dev_private; | |
b4519513 | 3962 | struct intel_ring_buffer *ring; |
1ec14ad3 | 3963 | int i; |
8187a2b7 | 3964 | |
b4519513 CW |
3965 | for_each_ring(ring, dev_priv, i) |
3966 | intel_cleanup_ring_buffer(ring); | |
8187a2b7 ZN |
3967 | } |
3968 | ||
673a394b EA |
3969 | int |
3970 | i915_gem_entervt_ioctl(struct drm_device *dev, void *data, | |
3971 | struct drm_file *file_priv) | |
3972 | { | |
3973 | drm_i915_private_t *dev_priv = dev->dev_private; | |
b4519513 | 3974 | int ret; |
673a394b | 3975 | |
79e53945 JB |
3976 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
3977 | return 0; | |
3978 | ||
ba1234d1 | 3979 | if (atomic_read(&dev_priv->mm.wedged)) { |
673a394b | 3980 | DRM_ERROR("Reenabling wedged hardware, good luck\n"); |
ba1234d1 | 3981 | atomic_set(&dev_priv->mm.wedged, 0); |
673a394b EA |
3982 | } |
3983 | ||
673a394b | 3984 | mutex_lock(&dev->struct_mutex); |
9bb2d6f9 EA |
3985 | dev_priv->mm.suspended = 0; |
3986 | ||
f691e2f4 | 3987 | ret = i915_gem_init_hw(dev); |
d816f6ac WF |
3988 | if (ret != 0) { |
3989 | mutex_unlock(&dev->struct_mutex); | |
9bb2d6f9 | 3990 | return ret; |
d816f6ac | 3991 | } |
9bb2d6f9 | 3992 | |
69dc4987 | 3993 | BUG_ON(!list_empty(&dev_priv->mm.active_list)); |
673a394b | 3994 | mutex_unlock(&dev->struct_mutex); |
dbb19d30 | 3995 | |
5f35308b CW |
3996 | ret = drm_irq_install(dev); |
3997 | if (ret) | |
3998 | goto cleanup_ringbuffer; | |
dbb19d30 | 3999 | |
673a394b | 4000 | return 0; |
5f35308b CW |
4001 | |
4002 | cleanup_ringbuffer: | |
4003 | mutex_lock(&dev->struct_mutex); | |
4004 | i915_gem_cleanup_ringbuffer(dev); | |
4005 | dev_priv->mm.suspended = 1; | |
4006 | mutex_unlock(&dev->struct_mutex); | |
4007 | ||
4008 | return ret; | |
673a394b EA |
4009 | } |
4010 | ||
4011 | int | |
4012 | i915_gem_leavevt_ioctl(struct drm_device *dev, void *data, | |
4013 | struct drm_file *file_priv) | |
4014 | { | |
79e53945 JB |
4015 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
4016 | return 0; | |
4017 | ||
dbb19d30 | 4018 | drm_irq_uninstall(dev); |
e6890f6f | 4019 | return i915_gem_idle(dev); |
673a394b EA |
4020 | } |
4021 | ||
4022 | void | |
4023 | i915_gem_lastclose(struct drm_device *dev) | |
4024 | { | |
4025 | int ret; | |
673a394b | 4026 | |
e806b495 EA |
4027 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
4028 | return; | |
4029 | ||
6dbe2772 KP |
4030 | ret = i915_gem_idle(dev); |
4031 | if (ret) | |
4032 | DRM_ERROR("failed to idle hardware: %d\n", ret); | |
673a394b EA |
4033 | } |
4034 | ||
64193406 CW |
4035 | static void |
4036 | init_ring_lists(struct intel_ring_buffer *ring) | |
4037 | { | |
4038 | INIT_LIST_HEAD(&ring->active_list); | |
4039 | INIT_LIST_HEAD(&ring->request_list); | |
64193406 CW |
4040 | } |
4041 | ||
673a394b EA |
4042 | void |
4043 | i915_gem_load(struct drm_device *dev) | |
4044 | { | |
4045 | drm_i915_private_t *dev_priv = dev->dev_private; | |
42dcedd4 CW |
4046 | int i; |
4047 | ||
4048 | dev_priv->slab = | |
4049 | kmem_cache_create("i915_gem_object", | |
4050 | sizeof(struct drm_i915_gem_object), 0, | |
4051 | SLAB_HWCACHE_ALIGN, | |
4052 | NULL); | |
673a394b | 4053 | |
69dc4987 | 4054 | INIT_LIST_HEAD(&dev_priv->mm.active_list); |
673a394b | 4055 | INIT_LIST_HEAD(&dev_priv->mm.inactive_list); |
6c085a72 CW |
4056 | INIT_LIST_HEAD(&dev_priv->mm.unbound_list); |
4057 | INIT_LIST_HEAD(&dev_priv->mm.bound_list); | |
a09ba7fa | 4058 | INIT_LIST_HEAD(&dev_priv->mm.fence_list); |
1ec14ad3 CW |
4059 | for (i = 0; i < I915_NUM_RINGS; i++) |
4060 | init_ring_lists(&dev_priv->ring[i]); | |
4b9de737 | 4061 | for (i = 0; i < I915_MAX_NUM_FENCES; i++) |
007cc8ac | 4062 | INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list); |
673a394b EA |
4063 | INIT_DELAYED_WORK(&dev_priv->mm.retire_work, |
4064 | i915_gem_retire_work_handler); | |
30dbf0c0 | 4065 | init_completion(&dev_priv->error_completion); |
31169714 | 4066 | |
94400120 DA |
4067 | /* On GEN3 we really need to make sure the ARB C3 LP bit is set */ |
4068 | if (IS_GEN3(dev)) { | |
50743298 DV |
4069 | I915_WRITE(MI_ARB_STATE, |
4070 | _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE)); | |
94400120 DA |
4071 | } |
4072 | ||
72bfa19c CW |
4073 | dev_priv->relative_constants_mode = I915_EXEC_CONSTANTS_REL_GENERAL; |
4074 | ||
de151cf6 | 4075 | /* Old X drivers will take 0-2 for front, back, depth buffers */ |
b397c836 EA |
4076 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) |
4077 | dev_priv->fence_reg_start = 3; | |
de151cf6 | 4078 | |
a6c45cf0 | 4079 | if (INTEL_INFO(dev)->gen >= 4 || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) |
de151cf6 JB |
4080 | dev_priv->num_fence_regs = 16; |
4081 | else | |
4082 | dev_priv->num_fence_regs = 8; | |
4083 | ||
b5aa8a0f | 4084 | /* Initialize fence registers to zero */ |
ada726c7 | 4085 | i915_gem_reset_fences(dev); |
10ed13e4 | 4086 | |
673a394b | 4087 | i915_gem_detect_bit_6_swizzle(dev); |
6b95a207 | 4088 | init_waitqueue_head(&dev_priv->pending_flip_queue); |
17250b71 | 4089 | |
ce453d81 CW |
4090 | dev_priv->mm.interruptible = true; |
4091 | ||
17250b71 CW |
4092 | dev_priv->mm.inactive_shrinker.shrink = i915_gem_inactive_shrink; |
4093 | dev_priv->mm.inactive_shrinker.seeks = DEFAULT_SEEKS; | |
4094 | register_shrinker(&dev_priv->mm.inactive_shrinker); | |
673a394b | 4095 | } |
71acb5eb DA |
4096 | |
4097 | /* | |
4098 | * Create a physically contiguous memory object for this object | |
4099 | * e.g. for cursor + overlay regs | |
4100 | */ | |
995b6762 CW |
4101 | static int i915_gem_init_phys_object(struct drm_device *dev, |
4102 | int id, int size, int align) | |
71acb5eb DA |
4103 | { |
4104 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4105 | struct drm_i915_gem_phys_object *phys_obj; | |
4106 | int ret; | |
4107 | ||
4108 | if (dev_priv->mm.phys_objs[id - 1] || !size) | |
4109 | return 0; | |
4110 | ||
9a298b2a | 4111 | phys_obj = kzalloc(sizeof(struct drm_i915_gem_phys_object), GFP_KERNEL); |
71acb5eb DA |
4112 | if (!phys_obj) |
4113 | return -ENOMEM; | |
4114 | ||
4115 | phys_obj->id = id; | |
4116 | ||
6eeefaf3 | 4117 | phys_obj->handle = drm_pci_alloc(dev, size, align); |
71acb5eb DA |
4118 | if (!phys_obj->handle) { |
4119 | ret = -ENOMEM; | |
4120 | goto kfree_obj; | |
4121 | } | |
4122 | #ifdef CONFIG_X86 | |
4123 | set_memory_wc((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE); | |
4124 | #endif | |
4125 | ||
4126 | dev_priv->mm.phys_objs[id - 1] = phys_obj; | |
4127 | ||
4128 | return 0; | |
4129 | kfree_obj: | |
9a298b2a | 4130 | kfree(phys_obj); |
71acb5eb DA |
4131 | return ret; |
4132 | } | |
4133 | ||
995b6762 | 4134 | static void i915_gem_free_phys_object(struct drm_device *dev, int id) |
71acb5eb DA |
4135 | { |
4136 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4137 | struct drm_i915_gem_phys_object *phys_obj; | |
4138 | ||
4139 | if (!dev_priv->mm.phys_objs[id - 1]) | |
4140 | return; | |
4141 | ||
4142 | phys_obj = dev_priv->mm.phys_objs[id - 1]; | |
4143 | if (phys_obj->cur_obj) { | |
4144 | i915_gem_detach_phys_object(dev, phys_obj->cur_obj); | |
4145 | } | |
4146 | ||
4147 | #ifdef CONFIG_X86 | |
4148 | set_memory_wb((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE); | |
4149 | #endif | |
4150 | drm_pci_free(dev, phys_obj->handle); | |
4151 | kfree(phys_obj); | |
4152 | dev_priv->mm.phys_objs[id - 1] = NULL; | |
4153 | } | |
4154 | ||
4155 | void i915_gem_free_all_phys_object(struct drm_device *dev) | |
4156 | { | |
4157 | int i; | |
4158 | ||
260883c8 | 4159 | for (i = I915_GEM_PHYS_CURSOR_0; i <= I915_MAX_PHYS_OBJECT; i++) |
71acb5eb DA |
4160 | i915_gem_free_phys_object(dev, i); |
4161 | } | |
4162 | ||
4163 | void i915_gem_detach_phys_object(struct drm_device *dev, | |
05394f39 | 4164 | struct drm_i915_gem_object *obj) |
71acb5eb | 4165 | { |
05394f39 | 4166 | struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping; |
e5281ccd | 4167 | char *vaddr; |
71acb5eb | 4168 | int i; |
71acb5eb DA |
4169 | int page_count; |
4170 | ||
05394f39 | 4171 | if (!obj->phys_obj) |
71acb5eb | 4172 | return; |
05394f39 | 4173 | vaddr = obj->phys_obj->handle->vaddr; |
71acb5eb | 4174 | |
05394f39 | 4175 | page_count = obj->base.size / PAGE_SIZE; |
71acb5eb | 4176 | for (i = 0; i < page_count; i++) { |
5949eac4 | 4177 | struct page *page = shmem_read_mapping_page(mapping, i); |
e5281ccd CW |
4178 | if (!IS_ERR(page)) { |
4179 | char *dst = kmap_atomic(page); | |
4180 | memcpy(dst, vaddr + i*PAGE_SIZE, PAGE_SIZE); | |
4181 | kunmap_atomic(dst); | |
4182 | ||
4183 | drm_clflush_pages(&page, 1); | |
4184 | ||
4185 | set_page_dirty(page); | |
4186 | mark_page_accessed(page); | |
4187 | page_cache_release(page); | |
4188 | } | |
71acb5eb | 4189 | } |
e76e9aeb | 4190 | i915_gem_chipset_flush(dev); |
d78b47b9 | 4191 | |
05394f39 CW |
4192 | obj->phys_obj->cur_obj = NULL; |
4193 | obj->phys_obj = NULL; | |
71acb5eb DA |
4194 | } |
4195 | ||
4196 | int | |
4197 | i915_gem_attach_phys_object(struct drm_device *dev, | |
05394f39 | 4198 | struct drm_i915_gem_object *obj, |
6eeefaf3 CW |
4199 | int id, |
4200 | int align) | |
71acb5eb | 4201 | { |
05394f39 | 4202 | struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping; |
71acb5eb | 4203 | drm_i915_private_t *dev_priv = dev->dev_private; |
71acb5eb DA |
4204 | int ret = 0; |
4205 | int page_count; | |
4206 | int i; | |
4207 | ||
4208 | if (id > I915_MAX_PHYS_OBJECT) | |
4209 | return -EINVAL; | |
4210 | ||
05394f39 CW |
4211 | if (obj->phys_obj) { |
4212 | if (obj->phys_obj->id == id) | |
71acb5eb DA |
4213 | return 0; |
4214 | i915_gem_detach_phys_object(dev, obj); | |
4215 | } | |
4216 | ||
71acb5eb DA |
4217 | /* create a new object */ |
4218 | if (!dev_priv->mm.phys_objs[id - 1]) { | |
4219 | ret = i915_gem_init_phys_object(dev, id, | |
05394f39 | 4220 | obj->base.size, align); |
71acb5eb | 4221 | if (ret) { |
05394f39 CW |
4222 | DRM_ERROR("failed to init phys object %d size: %zu\n", |
4223 | id, obj->base.size); | |
e5281ccd | 4224 | return ret; |
71acb5eb DA |
4225 | } |
4226 | } | |
4227 | ||
4228 | /* bind to the object */ | |
05394f39 CW |
4229 | obj->phys_obj = dev_priv->mm.phys_objs[id - 1]; |
4230 | obj->phys_obj->cur_obj = obj; | |
71acb5eb | 4231 | |
05394f39 | 4232 | page_count = obj->base.size / PAGE_SIZE; |
71acb5eb DA |
4233 | |
4234 | for (i = 0; i < page_count; i++) { | |
e5281ccd CW |
4235 | struct page *page; |
4236 | char *dst, *src; | |
4237 | ||
5949eac4 | 4238 | page = shmem_read_mapping_page(mapping, i); |
e5281ccd CW |
4239 | if (IS_ERR(page)) |
4240 | return PTR_ERR(page); | |
71acb5eb | 4241 | |
ff75b9bc | 4242 | src = kmap_atomic(page); |
05394f39 | 4243 | dst = obj->phys_obj->handle->vaddr + (i * PAGE_SIZE); |
71acb5eb | 4244 | memcpy(dst, src, PAGE_SIZE); |
3e4d3af5 | 4245 | kunmap_atomic(src); |
71acb5eb | 4246 | |
e5281ccd CW |
4247 | mark_page_accessed(page); |
4248 | page_cache_release(page); | |
4249 | } | |
d78b47b9 | 4250 | |
71acb5eb | 4251 | return 0; |
71acb5eb DA |
4252 | } |
4253 | ||
4254 | static int | |
05394f39 CW |
4255 | i915_gem_phys_pwrite(struct drm_device *dev, |
4256 | struct drm_i915_gem_object *obj, | |
71acb5eb DA |
4257 | struct drm_i915_gem_pwrite *args, |
4258 | struct drm_file *file_priv) | |
4259 | { | |
05394f39 | 4260 | void *vaddr = obj->phys_obj->handle->vaddr + args->offset; |
b47b30cc | 4261 | char __user *user_data = (char __user *) (uintptr_t) args->data_ptr; |
71acb5eb | 4262 | |
b47b30cc CW |
4263 | if (__copy_from_user_inatomic_nocache(vaddr, user_data, args->size)) { |
4264 | unsigned long unwritten; | |
4265 | ||
4266 | /* The physical object once assigned is fixed for the lifetime | |
4267 | * of the obj, so we can safely drop the lock and continue | |
4268 | * to access vaddr. | |
4269 | */ | |
4270 | mutex_unlock(&dev->struct_mutex); | |
4271 | unwritten = copy_from_user(vaddr, user_data, args->size); | |
4272 | mutex_lock(&dev->struct_mutex); | |
4273 | if (unwritten) | |
4274 | return -EFAULT; | |
4275 | } | |
71acb5eb | 4276 | |
e76e9aeb | 4277 | i915_gem_chipset_flush(dev); |
71acb5eb DA |
4278 | return 0; |
4279 | } | |
b962442e | 4280 | |
f787a5f5 | 4281 | void i915_gem_release(struct drm_device *dev, struct drm_file *file) |
b962442e | 4282 | { |
f787a5f5 | 4283 | struct drm_i915_file_private *file_priv = file->driver_priv; |
b962442e EA |
4284 | |
4285 | /* Clean up our request list when the client is going away, so that | |
4286 | * later retire_requests won't dereference our soon-to-be-gone | |
4287 | * file_priv. | |
4288 | */ | |
1c25595f | 4289 | spin_lock(&file_priv->mm.lock); |
f787a5f5 CW |
4290 | while (!list_empty(&file_priv->mm.request_list)) { |
4291 | struct drm_i915_gem_request *request; | |
4292 | ||
4293 | request = list_first_entry(&file_priv->mm.request_list, | |
4294 | struct drm_i915_gem_request, | |
4295 | client_list); | |
4296 | list_del(&request->client_list); | |
4297 | request->file_priv = NULL; | |
4298 | } | |
1c25595f | 4299 | spin_unlock(&file_priv->mm.lock); |
b962442e | 4300 | } |
31169714 | 4301 | |
5774506f CW |
4302 | static bool mutex_is_locked_by(struct mutex *mutex, struct task_struct *task) |
4303 | { | |
4304 | if (!mutex_is_locked(mutex)) | |
4305 | return false; | |
4306 | ||
4307 | #if defined(CONFIG_SMP) || defined(CONFIG_DEBUG_MUTEXES) | |
4308 | return mutex->owner == task; | |
4309 | #else | |
4310 | /* Since UP may be pre-empted, we cannot assume that we own the lock */ | |
4311 | return false; | |
4312 | #endif | |
4313 | } | |
4314 | ||
31169714 | 4315 | static int |
1495f230 | 4316 | i915_gem_inactive_shrink(struct shrinker *shrinker, struct shrink_control *sc) |
31169714 | 4317 | { |
17250b71 CW |
4318 | struct drm_i915_private *dev_priv = |
4319 | container_of(shrinker, | |
4320 | struct drm_i915_private, | |
4321 | mm.inactive_shrinker); | |
4322 | struct drm_device *dev = dev_priv->dev; | |
6c085a72 | 4323 | struct drm_i915_gem_object *obj; |
1495f230 | 4324 | int nr_to_scan = sc->nr_to_scan; |
5774506f | 4325 | bool unlock = true; |
17250b71 CW |
4326 | int cnt; |
4327 | ||
5774506f CW |
4328 | if (!mutex_trylock(&dev->struct_mutex)) { |
4329 | if (!mutex_is_locked_by(&dev->struct_mutex, current)) | |
4330 | return 0; | |
4331 | ||
677feac2 DV |
4332 | if (dev_priv->mm.shrinker_no_lock_stealing) |
4333 | return 0; | |
4334 | ||
5774506f CW |
4335 | unlock = false; |
4336 | } | |
31169714 | 4337 | |
6c085a72 CW |
4338 | if (nr_to_scan) { |
4339 | nr_to_scan -= i915_gem_purge(dev_priv, nr_to_scan); | |
4340 | if (nr_to_scan > 0) | |
4341 | i915_gem_shrink_all(dev_priv); | |
31169714 CW |
4342 | } |
4343 | ||
17250b71 | 4344 | cnt = 0; |
6c085a72 | 4345 | list_for_each_entry(obj, &dev_priv->mm.unbound_list, gtt_list) |
a5570178 CW |
4346 | if (obj->pages_pin_count == 0) |
4347 | cnt += obj->base.size >> PAGE_SHIFT; | |
6c085a72 | 4348 | list_for_each_entry(obj, &dev_priv->mm.bound_list, gtt_list) |
a5570178 | 4349 | if (obj->pin_count == 0 && obj->pages_pin_count == 0) |
6c085a72 | 4350 | cnt += obj->base.size >> PAGE_SHIFT; |
17250b71 | 4351 | |
5774506f CW |
4352 | if (unlock) |
4353 | mutex_unlock(&dev->struct_mutex); | |
6c085a72 | 4354 | return cnt; |
31169714 | 4355 | } |