]>
Commit | Line | Data |
---|---|---|
673a394b EA |
1 | /* |
2 | * Copyright © 2008 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | * | |
26 | */ | |
27 | ||
28 | #include "drmP.h" | |
29 | #include "drm.h" | |
30 | #include "i915_drm.h" | |
31 | #include "i915_drv.h" | |
1c5d22f7 | 32 | #include "i915_trace.h" |
652c393a | 33 | #include "intel_drv.h" |
5a0e3ad6 | 34 | #include <linux/slab.h> |
673a394b | 35 | #include <linux/swap.h> |
79e53945 | 36 | #include <linux/pci.h> |
673a394b | 37 | |
88241785 | 38 | static __must_check int i915_gem_object_flush_gpu_write_domain(struct drm_i915_gem_object *obj); |
05394f39 CW |
39 | static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj); |
40 | static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj); | |
88241785 CW |
41 | static __must_check int i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, |
42 | bool write); | |
43 | static __must_check int i915_gem_object_set_cpu_read_domain_range(struct drm_i915_gem_object *obj, | |
44 | uint64_t offset, | |
45 | uint64_t size); | |
05394f39 | 46 | static void i915_gem_object_set_to_full_cpu_read_domain(struct drm_i915_gem_object *obj); |
88241785 CW |
47 | static __must_check int i915_gem_object_bind_to_gtt(struct drm_i915_gem_object *obj, |
48 | unsigned alignment, | |
49 | bool map_and_fenceable); | |
d9e86c0e CW |
50 | static void i915_gem_clear_fence_reg(struct drm_device *dev, |
51 | struct drm_i915_fence_reg *reg); | |
05394f39 CW |
52 | static int i915_gem_phys_pwrite(struct drm_device *dev, |
53 | struct drm_i915_gem_object *obj, | |
71acb5eb | 54 | struct drm_i915_gem_pwrite *args, |
05394f39 CW |
55 | struct drm_file *file); |
56 | static void i915_gem_free_object_tail(struct drm_i915_gem_object *obj); | |
673a394b | 57 | |
17250b71 CW |
58 | static int i915_gem_inactive_shrink(struct shrinker *shrinker, |
59 | int nr_to_scan, | |
60 | gfp_t gfp_mask); | |
61 | ||
31169714 | 62 | |
73aa808f CW |
63 | /* some bookkeeping */ |
64 | static void i915_gem_info_add_obj(struct drm_i915_private *dev_priv, | |
65 | size_t size) | |
66 | { | |
67 | dev_priv->mm.object_count++; | |
68 | dev_priv->mm.object_memory += size; | |
69 | } | |
70 | ||
71 | static void i915_gem_info_remove_obj(struct drm_i915_private *dev_priv, | |
72 | size_t size) | |
73 | { | |
74 | dev_priv->mm.object_count--; | |
75 | dev_priv->mm.object_memory -= size; | |
76 | } | |
77 | ||
21dd3734 CW |
78 | static int |
79 | i915_gem_wait_for_error(struct drm_device *dev) | |
30dbf0c0 CW |
80 | { |
81 | struct drm_i915_private *dev_priv = dev->dev_private; | |
82 | struct completion *x = &dev_priv->error_completion; | |
83 | unsigned long flags; | |
84 | int ret; | |
85 | ||
86 | if (!atomic_read(&dev_priv->mm.wedged)) | |
87 | return 0; | |
88 | ||
89 | ret = wait_for_completion_interruptible(x); | |
90 | if (ret) | |
91 | return ret; | |
92 | ||
21dd3734 CW |
93 | if (atomic_read(&dev_priv->mm.wedged)) { |
94 | /* GPU is hung, bump the completion count to account for | |
95 | * the token we just consumed so that we never hit zero and | |
96 | * end up waiting upon a subsequent completion event that | |
97 | * will never happen. | |
98 | */ | |
99 | spin_lock_irqsave(&x->wait.lock, flags); | |
100 | x->done++; | |
101 | spin_unlock_irqrestore(&x->wait.lock, flags); | |
102 | } | |
103 | return 0; | |
30dbf0c0 CW |
104 | } |
105 | ||
54cf91dc | 106 | int i915_mutex_lock_interruptible(struct drm_device *dev) |
76c1dec1 | 107 | { |
76c1dec1 CW |
108 | int ret; |
109 | ||
21dd3734 | 110 | ret = i915_gem_wait_for_error(dev); |
76c1dec1 CW |
111 | if (ret) |
112 | return ret; | |
113 | ||
114 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
115 | if (ret) | |
116 | return ret; | |
117 | ||
23bc5982 | 118 | WARN_ON(i915_verify_lists(dev)); |
76c1dec1 CW |
119 | return 0; |
120 | } | |
30dbf0c0 | 121 | |
7d1c4804 | 122 | static inline bool |
05394f39 | 123 | i915_gem_object_is_inactive(struct drm_i915_gem_object *obj) |
7d1c4804 | 124 | { |
05394f39 | 125 | return obj->gtt_space && !obj->active && obj->pin_count == 0; |
7d1c4804 CW |
126 | } |
127 | ||
2021746e CW |
128 | void i915_gem_do_init(struct drm_device *dev, |
129 | unsigned long start, | |
130 | unsigned long mappable_end, | |
131 | unsigned long end) | |
673a394b EA |
132 | { |
133 | drm_i915_private_t *dev_priv = dev->dev_private; | |
673a394b | 134 | |
bee4a186 | 135 | drm_mm_init(&dev_priv->mm.gtt_space, start, end - start); |
673a394b | 136 | |
bee4a186 CW |
137 | dev_priv->mm.gtt_start = start; |
138 | dev_priv->mm.gtt_mappable_end = mappable_end; | |
139 | dev_priv->mm.gtt_end = end; | |
73aa808f | 140 | dev_priv->mm.gtt_total = end - start; |
fb7d516a | 141 | dev_priv->mm.mappable_gtt_total = min(end, mappable_end) - start; |
bee4a186 CW |
142 | |
143 | /* Take over this portion of the GTT */ | |
144 | intel_gtt_clear_range(start / PAGE_SIZE, (end-start) / PAGE_SIZE); | |
79e53945 | 145 | } |
673a394b | 146 | |
79e53945 JB |
147 | int |
148 | i915_gem_init_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 149 | struct drm_file *file) |
79e53945 JB |
150 | { |
151 | struct drm_i915_gem_init *args = data; | |
2021746e CW |
152 | |
153 | if (args->gtt_start >= args->gtt_end || | |
154 | (args->gtt_end | args->gtt_start) & (PAGE_SIZE - 1)) | |
155 | return -EINVAL; | |
79e53945 JB |
156 | |
157 | mutex_lock(&dev->struct_mutex); | |
2021746e | 158 | i915_gem_do_init(dev, args->gtt_start, args->gtt_end, args->gtt_end); |
673a394b EA |
159 | mutex_unlock(&dev->struct_mutex); |
160 | ||
2021746e | 161 | return 0; |
673a394b EA |
162 | } |
163 | ||
5a125c3c EA |
164 | int |
165 | i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 166 | struct drm_file *file) |
5a125c3c | 167 | { |
73aa808f | 168 | struct drm_i915_private *dev_priv = dev->dev_private; |
5a125c3c | 169 | struct drm_i915_gem_get_aperture *args = data; |
6299f992 CW |
170 | struct drm_i915_gem_object *obj; |
171 | size_t pinned; | |
5a125c3c EA |
172 | |
173 | if (!(dev->driver->driver_features & DRIVER_GEM)) | |
174 | return -ENODEV; | |
175 | ||
6299f992 | 176 | pinned = 0; |
73aa808f | 177 | mutex_lock(&dev->struct_mutex); |
6299f992 CW |
178 | list_for_each_entry(obj, &dev_priv->mm.pinned_list, mm_list) |
179 | pinned += obj->gtt_space->size; | |
73aa808f | 180 | mutex_unlock(&dev->struct_mutex); |
5a125c3c | 181 | |
6299f992 CW |
182 | args->aper_size = dev_priv->mm.gtt_total; |
183 | args->aper_available_size = args->aper_size -pinned; | |
184 | ||
5a125c3c EA |
185 | return 0; |
186 | } | |
187 | ||
673a394b EA |
188 | /** |
189 | * Creates a new mm object and returns a handle to it. | |
190 | */ | |
191 | int | |
192 | i915_gem_create_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 193 | struct drm_file *file) |
673a394b EA |
194 | { |
195 | struct drm_i915_gem_create *args = data; | |
05394f39 | 196 | struct drm_i915_gem_object *obj; |
a1a2d1d3 PP |
197 | int ret; |
198 | u32 handle; | |
673a394b EA |
199 | |
200 | args->size = roundup(args->size, PAGE_SIZE); | |
201 | ||
202 | /* Allocate the new object */ | |
ac52bc56 | 203 | obj = i915_gem_alloc_object(dev, args->size); |
673a394b EA |
204 | if (obj == NULL) |
205 | return -ENOMEM; | |
206 | ||
05394f39 | 207 | ret = drm_gem_handle_create(file, &obj->base, &handle); |
1dfd9754 | 208 | if (ret) { |
05394f39 CW |
209 | drm_gem_object_release(&obj->base); |
210 | i915_gem_info_remove_obj(dev->dev_private, obj->base.size); | |
202f2fef | 211 | kfree(obj); |
673a394b | 212 | return ret; |
1dfd9754 | 213 | } |
673a394b | 214 | |
202f2fef | 215 | /* drop reference from allocate - handle holds it now */ |
05394f39 | 216 | drm_gem_object_unreference(&obj->base); |
202f2fef CW |
217 | trace_i915_gem_object_create(obj); |
218 | ||
1dfd9754 | 219 | args->handle = handle; |
673a394b EA |
220 | return 0; |
221 | } | |
222 | ||
05394f39 | 223 | static int i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj) |
280b713b | 224 | { |
05394f39 | 225 | drm_i915_private_t *dev_priv = obj->base.dev->dev_private; |
280b713b EA |
226 | |
227 | return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 && | |
05394f39 | 228 | obj->tiling_mode != I915_TILING_NONE; |
280b713b EA |
229 | } |
230 | ||
99a03df5 | 231 | static inline void |
40123c1f EA |
232 | slow_shmem_copy(struct page *dst_page, |
233 | int dst_offset, | |
234 | struct page *src_page, | |
235 | int src_offset, | |
236 | int length) | |
237 | { | |
238 | char *dst_vaddr, *src_vaddr; | |
239 | ||
99a03df5 CW |
240 | dst_vaddr = kmap(dst_page); |
241 | src_vaddr = kmap(src_page); | |
40123c1f EA |
242 | |
243 | memcpy(dst_vaddr + dst_offset, src_vaddr + src_offset, length); | |
244 | ||
99a03df5 CW |
245 | kunmap(src_page); |
246 | kunmap(dst_page); | |
40123c1f EA |
247 | } |
248 | ||
99a03df5 | 249 | static inline void |
280b713b EA |
250 | slow_shmem_bit17_copy(struct page *gpu_page, |
251 | int gpu_offset, | |
252 | struct page *cpu_page, | |
253 | int cpu_offset, | |
254 | int length, | |
255 | int is_read) | |
256 | { | |
257 | char *gpu_vaddr, *cpu_vaddr; | |
258 | ||
259 | /* Use the unswizzled path if this page isn't affected. */ | |
260 | if ((page_to_phys(gpu_page) & (1 << 17)) == 0) { | |
261 | if (is_read) | |
262 | return slow_shmem_copy(cpu_page, cpu_offset, | |
263 | gpu_page, gpu_offset, length); | |
264 | else | |
265 | return slow_shmem_copy(gpu_page, gpu_offset, | |
266 | cpu_page, cpu_offset, length); | |
267 | } | |
268 | ||
99a03df5 CW |
269 | gpu_vaddr = kmap(gpu_page); |
270 | cpu_vaddr = kmap(cpu_page); | |
280b713b EA |
271 | |
272 | /* Copy the data, XORing A6 with A17 (1). The user already knows he's | |
273 | * XORing with the other bits (A9 for Y, A9 and A10 for X) | |
274 | */ | |
275 | while (length > 0) { | |
276 | int cacheline_end = ALIGN(gpu_offset + 1, 64); | |
277 | int this_length = min(cacheline_end - gpu_offset, length); | |
278 | int swizzled_gpu_offset = gpu_offset ^ 64; | |
279 | ||
280 | if (is_read) { | |
281 | memcpy(cpu_vaddr + cpu_offset, | |
282 | gpu_vaddr + swizzled_gpu_offset, | |
283 | this_length); | |
284 | } else { | |
285 | memcpy(gpu_vaddr + swizzled_gpu_offset, | |
286 | cpu_vaddr + cpu_offset, | |
287 | this_length); | |
288 | } | |
289 | cpu_offset += this_length; | |
290 | gpu_offset += this_length; | |
291 | length -= this_length; | |
292 | } | |
293 | ||
99a03df5 CW |
294 | kunmap(cpu_page); |
295 | kunmap(gpu_page); | |
280b713b EA |
296 | } |
297 | ||
eb01459f EA |
298 | /** |
299 | * This is the fast shmem pread path, which attempts to copy_from_user directly | |
300 | * from the backing pages of the object to the user's address space. On a | |
301 | * fault, it fails so we can fall back to i915_gem_shmem_pwrite_slow(). | |
302 | */ | |
303 | static int | |
05394f39 CW |
304 | i915_gem_shmem_pread_fast(struct drm_device *dev, |
305 | struct drm_i915_gem_object *obj, | |
eb01459f | 306 | struct drm_i915_gem_pread *args, |
05394f39 | 307 | struct drm_file *file) |
eb01459f | 308 | { |
05394f39 | 309 | struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping; |
eb01459f | 310 | ssize_t remain; |
e5281ccd | 311 | loff_t offset; |
eb01459f EA |
312 | char __user *user_data; |
313 | int page_offset, page_length; | |
eb01459f EA |
314 | |
315 | user_data = (char __user *) (uintptr_t) args->data_ptr; | |
316 | remain = args->size; | |
317 | ||
eb01459f EA |
318 | offset = args->offset; |
319 | ||
320 | while (remain > 0) { | |
e5281ccd CW |
321 | struct page *page; |
322 | char *vaddr; | |
323 | int ret; | |
324 | ||
eb01459f EA |
325 | /* Operation in this page |
326 | * | |
eb01459f EA |
327 | * page_offset = offset within page |
328 | * page_length = bytes to copy for this page | |
329 | */ | |
eb01459f EA |
330 | page_offset = offset & (PAGE_SIZE-1); |
331 | page_length = remain; | |
332 | if ((page_offset + remain) > PAGE_SIZE) | |
333 | page_length = PAGE_SIZE - page_offset; | |
334 | ||
e5281ccd CW |
335 | page = read_cache_page_gfp(mapping, offset >> PAGE_SHIFT, |
336 | GFP_HIGHUSER | __GFP_RECLAIMABLE); | |
337 | if (IS_ERR(page)) | |
338 | return PTR_ERR(page); | |
339 | ||
340 | vaddr = kmap_atomic(page); | |
341 | ret = __copy_to_user_inatomic(user_data, | |
342 | vaddr + page_offset, | |
343 | page_length); | |
344 | kunmap_atomic(vaddr); | |
345 | ||
346 | mark_page_accessed(page); | |
347 | page_cache_release(page); | |
348 | if (ret) | |
4f27b75d | 349 | return -EFAULT; |
eb01459f EA |
350 | |
351 | remain -= page_length; | |
352 | user_data += page_length; | |
353 | offset += page_length; | |
354 | } | |
355 | ||
4f27b75d | 356 | return 0; |
eb01459f EA |
357 | } |
358 | ||
359 | /** | |
360 | * This is the fallback shmem pread path, which allocates temporary storage | |
361 | * in kernel space to copy_to_user into outside of the struct_mutex, so we | |
362 | * can copy out of the object's backing pages while holding the struct mutex | |
363 | * and not take page faults. | |
364 | */ | |
365 | static int | |
05394f39 CW |
366 | i915_gem_shmem_pread_slow(struct drm_device *dev, |
367 | struct drm_i915_gem_object *obj, | |
eb01459f | 368 | struct drm_i915_gem_pread *args, |
05394f39 | 369 | struct drm_file *file) |
eb01459f | 370 | { |
05394f39 | 371 | struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping; |
eb01459f EA |
372 | struct mm_struct *mm = current->mm; |
373 | struct page **user_pages; | |
374 | ssize_t remain; | |
375 | loff_t offset, pinned_pages, i; | |
376 | loff_t first_data_page, last_data_page, num_pages; | |
e5281ccd CW |
377 | int shmem_page_offset; |
378 | int data_page_index, data_page_offset; | |
eb01459f EA |
379 | int page_length; |
380 | int ret; | |
381 | uint64_t data_ptr = args->data_ptr; | |
280b713b | 382 | int do_bit17_swizzling; |
eb01459f EA |
383 | |
384 | remain = args->size; | |
385 | ||
386 | /* Pin the user pages containing the data. We can't fault while | |
387 | * holding the struct mutex, yet we want to hold it while | |
388 | * dereferencing the user data. | |
389 | */ | |
390 | first_data_page = data_ptr / PAGE_SIZE; | |
391 | last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE; | |
392 | num_pages = last_data_page - first_data_page + 1; | |
393 | ||
4f27b75d | 394 | user_pages = drm_malloc_ab(num_pages, sizeof(struct page *)); |
eb01459f EA |
395 | if (user_pages == NULL) |
396 | return -ENOMEM; | |
397 | ||
4f27b75d | 398 | mutex_unlock(&dev->struct_mutex); |
eb01459f EA |
399 | down_read(&mm->mmap_sem); |
400 | pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr, | |
e5e9ecde | 401 | num_pages, 1, 0, user_pages, NULL); |
eb01459f | 402 | up_read(&mm->mmap_sem); |
4f27b75d | 403 | mutex_lock(&dev->struct_mutex); |
eb01459f EA |
404 | if (pinned_pages < num_pages) { |
405 | ret = -EFAULT; | |
4f27b75d | 406 | goto out; |
eb01459f EA |
407 | } |
408 | ||
4f27b75d CW |
409 | ret = i915_gem_object_set_cpu_read_domain_range(obj, |
410 | args->offset, | |
411 | args->size); | |
07f73f69 | 412 | if (ret) |
4f27b75d | 413 | goto out; |
eb01459f | 414 | |
4f27b75d | 415 | do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj); |
eb01459f | 416 | |
eb01459f EA |
417 | offset = args->offset; |
418 | ||
419 | while (remain > 0) { | |
e5281ccd CW |
420 | struct page *page; |
421 | ||
eb01459f EA |
422 | /* Operation in this page |
423 | * | |
eb01459f EA |
424 | * shmem_page_offset = offset within page in shmem file |
425 | * data_page_index = page number in get_user_pages return | |
426 | * data_page_offset = offset with data_page_index page. | |
427 | * page_length = bytes to copy for this page | |
428 | */ | |
eb01459f EA |
429 | shmem_page_offset = offset & ~PAGE_MASK; |
430 | data_page_index = data_ptr / PAGE_SIZE - first_data_page; | |
431 | data_page_offset = data_ptr & ~PAGE_MASK; | |
432 | ||
433 | page_length = remain; | |
434 | if ((shmem_page_offset + page_length) > PAGE_SIZE) | |
435 | page_length = PAGE_SIZE - shmem_page_offset; | |
436 | if ((data_page_offset + page_length) > PAGE_SIZE) | |
437 | page_length = PAGE_SIZE - data_page_offset; | |
438 | ||
e5281ccd CW |
439 | page = read_cache_page_gfp(mapping, offset >> PAGE_SHIFT, |
440 | GFP_HIGHUSER | __GFP_RECLAIMABLE); | |
441 | if (IS_ERR(page)) | |
442 | return PTR_ERR(page); | |
443 | ||
280b713b | 444 | if (do_bit17_swizzling) { |
e5281ccd | 445 | slow_shmem_bit17_copy(page, |
280b713b | 446 | shmem_page_offset, |
99a03df5 CW |
447 | user_pages[data_page_index], |
448 | data_page_offset, | |
449 | page_length, | |
450 | 1); | |
451 | } else { | |
452 | slow_shmem_copy(user_pages[data_page_index], | |
453 | data_page_offset, | |
e5281ccd | 454 | page, |
99a03df5 CW |
455 | shmem_page_offset, |
456 | page_length); | |
280b713b | 457 | } |
eb01459f | 458 | |
e5281ccd CW |
459 | mark_page_accessed(page); |
460 | page_cache_release(page); | |
461 | ||
eb01459f EA |
462 | remain -= page_length; |
463 | data_ptr += page_length; | |
464 | offset += page_length; | |
465 | } | |
466 | ||
4f27b75d | 467 | out: |
eb01459f EA |
468 | for (i = 0; i < pinned_pages; i++) { |
469 | SetPageDirty(user_pages[i]); | |
e5281ccd | 470 | mark_page_accessed(user_pages[i]); |
eb01459f EA |
471 | page_cache_release(user_pages[i]); |
472 | } | |
8e7d2b2c | 473 | drm_free_large(user_pages); |
eb01459f EA |
474 | |
475 | return ret; | |
476 | } | |
477 | ||
673a394b EA |
478 | /** |
479 | * Reads data from the object referenced by handle. | |
480 | * | |
481 | * On error, the contents of *data are undefined. | |
482 | */ | |
483 | int | |
484 | i915_gem_pread_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 485 | struct drm_file *file) |
673a394b EA |
486 | { |
487 | struct drm_i915_gem_pread *args = data; | |
05394f39 | 488 | struct drm_i915_gem_object *obj; |
35b62a89 | 489 | int ret = 0; |
673a394b | 490 | |
51311d0a CW |
491 | if (args->size == 0) |
492 | return 0; | |
493 | ||
494 | if (!access_ok(VERIFY_WRITE, | |
495 | (char __user *)(uintptr_t)args->data_ptr, | |
496 | args->size)) | |
497 | return -EFAULT; | |
498 | ||
499 | ret = fault_in_pages_writeable((char __user *)(uintptr_t)args->data_ptr, | |
500 | args->size); | |
501 | if (ret) | |
502 | return -EFAULT; | |
503 | ||
4f27b75d | 504 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 505 | if (ret) |
4f27b75d | 506 | return ret; |
673a394b | 507 | |
05394f39 | 508 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
1d7cfea1 CW |
509 | if (obj == NULL) { |
510 | ret = -ENOENT; | |
511 | goto unlock; | |
4f27b75d | 512 | } |
673a394b | 513 | |
7dcd2499 | 514 | /* Bounds check source. */ |
05394f39 CW |
515 | if (args->offset > obj->base.size || |
516 | args->size > obj->base.size - args->offset) { | |
ce9d419d | 517 | ret = -EINVAL; |
35b62a89 | 518 | goto out; |
ce9d419d CW |
519 | } |
520 | ||
4f27b75d CW |
521 | ret = i915_gem_object_set_cpu_read_domain_range(obj, |
522 | args->offset, | |
523 | args->size); | |
524 | if (ret) | |
e5281ccd | 525 | goto out; |
4f27b75d CW |
526 | |
527 | ret = -EFAULT; | |
528 | if (!i915_gem_object_needs_bit17_swizzle(obj)) | |
05394f39 | 529 | ret = i915_gem_shmem_pread_fast(dev, obj, args, file); |
4f27b75d | 530 | if (ret == -EFAULT) |
05394f39 | 531 | ret = i915_gem_shmem_pread_slow(dev, obj, args, file); |
673a394b | 532 | |
35b62a89 | 533 | out: |
05394f39 | 534 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 535 | unlock: |
4f27b75d | 536 | mutex_unlock(&dev->struct_mutex); |
eb01459f | 537 | return ret; |
673a394b EA |
538 | } |
539 | ||
0839ccb8 KP |
540 | /* This is the fast write path which cannot handle |
541 | * page faults in the source data | |
9b7530cc | 542 | */ |
0839ccb8 KP |
543 | |
544 | static inline int | |
545 | fast_user_write(struct io_mapping *mapping, | |
546 | loff_t page_base, int page_offset, | |
547 | char __user *user_data, | |
548 | int length) | |
9b7530cc | 549 | { |
9b7530cc | 550 | char *vaddr_atomic; |
0839ccb8 | 551 | unsigned long unwritten; |
9b7530cc | 552 | |
3e4d3af5 | 553 | vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base); |
0839ccb8 KP |
554 | unwritten = __copy_from_user_inatomic_nocache(vaddr_atomic + page_offset, |
555 | user_data, length); | |
3e4d3af5 | 556 | io_mapping_unmap_atomic(vaddr_atomic); |
fbd5a26d | 557 | return unwritten; |
0839ccb8 KP |
558 | } |
559 | ||
560 | /* Here's the write path which can sleep for | |
561 | * page faults | |
562 | */ | |
563 | ||
ab34c226 | 564 | static inline void |
3de09aa3 EA |
565 | slow_kernel_write(struct io_mapping *mapping, |
566 | loff_t gtt_base, int gtt_offset, | |
567 | struct page *user_page, int user_offset, | |
568 | int length) | |
0839ccb8 | 569 | { |
ab34c226 CW |
570 | char __iomem *dst_vaddr; |
571 | char *src_vaddr; | |
0839ccb8 | 572 | |
ab34c226 CW |
573 | dst_vaddr = io_mapping_map_wc(mapping, gtt_base); |
574 | src_vaddr = kmap(user_page); | |
575 | ||
576 | memcpy_toio(dst_vaddr + gtt_offset, | |
577 | src_vaddr + user_offset, | |
578 | length); | |
579 | ||
580 | kunmap(user_page); | |
581 | io_mapping_unmap(dst_vaddr); | |
9b7530cc LT |
582 | } |
583 | ||
3de09aa3 EA |
584 | /** |
585 | * This is the fast pwrite path, where we copy the data directly from the | |
586 | * user into the GTT, uncached. | |
587 | */ | |
673a394b | 588 | static int |
05394f39 CW |
589 | i915_gem_gtt_pwrite_fast(struct drm_device *dev, |
590 | struct drm_i915_gem_object *obj, | |
3de09aa3 | 591 | struct drm_i915_gem_pwrite *args, |
05394f39 | 592 | struct drm_file *file) |
673a394b | 593 | { |
0839ccb8 | 594 | drm_i915_private_t *dev_priv = dev->dev_private; |
673a394b | 595 | ssize_t remain; |
0839ccb8 | 596 | loff_t offset, page_base; |
673a394b | 597 | char __user *user_data; |
0839ccb8 | 598 | int page_offset, page_length; |
673a394b EA |
599 | |
600 | user_data = (char __user *) (uintptr_t) args->data_ptr; | |
601 | remain = args->size; | |
673a394b | 602 | |
05394f39 | 603 | offset = obj->gtt_offset + args->offset; |
673a394b EA |
604 | |
605 | while (remain > 0) { | |
606 | /* Operation in this page | |
607 | * | |
0839ccb8 KP |
608 | * page_base = page offset within aperture |
609 | * page_offset = offset within page | |
610 | * page_length = bytes to copy for this page | |
673a394b | 611 | */ |
0839ccb8 KP |
612 | page_base = (offset & ~(PAGE_SIZE-1)); |
613 | page_offset = offset & (PAGE_SIZE-1); | |
614 | page_length = remain; | |
615 | if ((page_offset + remain) > PAGE_SIZE) | |
616 | page_length = PAGE_SIZE - page_offset; | |
617 | ||
0839ccb8 | 618 | /* If we get a fault while copying data, then (presumably) our |
3de09aa3 EA |
619 | * source page isn't available. Return the error and we'll |
620 | * retry in the slow path. | |
0839ccb8 | 621 | */ |
fbd5a26d CW |
622 | if (fast_user_write(dev_priv->mm.gtt_mapping, page_base, |
623 | page_offset, user_data, page_length)) | |
624 | ||
625 | return -EFAULT; | |
673a394b | 626 | |
0839ccb8 KP |
627 | remain -= page_length; |
628 | user_data += page_length; | |
629 | offset += page_length; | |
673a394b | 630 | } |
673a394b | 631 | |
fbd5a26d | 632 | return 0; |
673a394b EA |
633 | } |
634 | ||
3de09aa3 EA |
635 | /** |
636 | * This is the fallback GTT pwrite path, which uses get_user_pages to pin | |
637 | * the memory and maps it using kmap_atomic for copying. | |
638 | * | |
639 | * This code resulted in x11perf -rgb10text consuming about 10% more CPU | |
640 | * than using i915_gem_gtt_pwrite_fast on a G45 (32-bit). | |
641 | */ | |
3043c60c | 642 | static int |
05394f39 CW |
643 | i915_gem_gtt_pwrite_slow(struct drm_device *dev, |
644 | struct drm_i915_gem_object *obj, | |
3de09aa3 | 645 | struct drm_i915_gem_pwrite *args, |
05394f39 | 646 | struct drm_file *file) |
673a394b | 647 | { |
3de09aa3 EA |
648 | drm_i915_private_t *dev_priv = dev->dev_private; |
649 | ssize_t remain; | |
650 | loff_t gtt_page_base, offset; | |
651 | loff_t first_data_page, last_data_page, num_pages; | |
652 | loff_t pinned_pages, i; | |
653 | struct page **user_pages; | |
654 | struct mm_struct *mm = current->mm; | |
655 | int gtt_page_offset, data_page_offset, data_page_index, page_length; | |
673a394b | 656 | int ret; |
3de09aa3 EA |
657 | uint64_t data_ptr = args->data_ptr; |
658 | ||
659 | remain = args->size; | |
660 | ||
661 | /* Pin the user pages containing the data. We can't fault while | |
662 | * holding the struct mutex, and all of the pwrite implementations | |
663 | * want to hold it while dereferencing the user data. | |
664 | */ | |
665 | first_data_page = data_ptr / PAGE_SIZE; | |
666 | last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE; | |
667 | num_pages = last_data_page - first_data_page + 1; | |
668 | ||
fbd5a26d | 669 | user_pages = drm_malloc_ab(num_pages, sizeof(struct page *)); |
3de09aa3 EA |
670 | if (user_pages == NULL) |
671 | return -ENOMEM; | |
672 | ||
fbd5a26d | 673 | mutex_unlock(&dev->struct_mutex); |
3de09aa3 EA |
674 | down_read(&mm->mmap_sem); |
675 | pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr, | |
676 | num_pages, 0, 0, user_pages, NULL); | |
677 | up_read(&mm->mmap_sem); | |
fbd5a26d | 678 | mutex_lock(&dev->struct_mutex); |
3de09aa3 EA |
679 | if (pinned_pages < num_pages) { |
680 | ret = -EFAULT; | |
681 | goto out_unpin_pages; | |
682 | } | |
673a394b | 683 | |
d9e86c0e CW |
684 | ret = i915_gem_object_set_to_gtt_domain(obj, true); |
685 | if (ret) | |
686 | goto out_unpin_pages; | |
687 | ||
688 | ret = i915_gem_object_put_fence(obj); | |
3de09aa3 | 689 | if (ret) |
fbd5a26d | 690 | goto out_unpin_pages; |
3de09aa3 | 691 | |
05394f39 | 692 | offset = obj->gtt_offset + args->offset; |
3de09aa3 EA |
693 | |
694 | while (remain > 0) { | |
695 | /* Operation in this page | |
696 | * | |
697 | * gtt_page_base = page offset within aperture | |
698 | * gtt_page_offset = offset within page in aperture | |
699 | * data_page_index = page number in get_user_pages return | |
700 | * data_page_offset = offset with data_page_index page. | |
701 | * page_length = bytes to copy for this page | |
702 | */ | |
703 | gtt_page_base = offset & PAGE_MASK; | |
704 | gtt_page_offset = offset & ~PAGE_MASK; | |
705 | data_page_index = data_ptr / PAGE_SIZE - first_data_page; | |
706 | data_page_offset = data_ptr & ~PAGE_MASK; | |
707 | ||
708 | page_length = remain; | |
709 | if ((gtt_page_offset + page_length) > PAGE_SIZE) | |
710 | page_length = PAGE_SIZE - gtt_page_offset; | |
711 | if ((data_page_offset + page_length) > PAGE_SIZE) | |
712 | page_length = PAGE_SIZE - data_page_offset; | |
713 | ||
ab34c226 CW |
714 | slow_kernel_write(dev_priv->mm.gtt_mapping, |
715 | gtt_page_base, gtt_page_offset, | |
716 | user_pages[data_page_index], | |
717 | data_page_offset, | |
718 | page_length); | |
3de09aa3 EA |
719 | |
720 | remain -= page_length; | |
721 | offset += page_length; | |
722 | data_ptr += page_length; | |
723 | } | |
724 | ||
3de09aa3 EA |
725 | out_unpin_pages: |
726 | for (i = 0; i < pinned_pages; i++) | |
727 | page_cache_release(user_pages[i]); | |
8e7d2b2c | 728 | drm_free_large(user_pages); |
3de09aa3 EA |
729 | |
730 | return ret; | |
731 | } | |
732 | ||
40123c1f EA |
733 | /** |
734 | * This is the fast shmem pwrite path, which attempts to directly | |
735 | * copy_from_user into the kmapped pages backing the object. | |
736 | */ | |
3043c60c | 737 | static int |
05394f39 CW |
738 | i915_gem_shmem_pwrite_fast(struct drm_device *dev, |
739 | struct drm_i915_gem_object *obj, | |
40123c1f | 740 | struct drm_i915_gem_pwrite *args, |
05394f39 | 741 | struct drm_file *file) |
673a394b | 742 | { |
05394f39 | 743 | struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping; |
40123c1f | 744 | ssize_t remain; |
e5281ccd | 745 | loff_t offset; |
40123c1f EA |
746 | char __user *user_data; |
747 | int page_offset, page_length; | |
40123c1f EA |
748 | |
749 | user_data = (char __user *) (uintptr_t) args->data_ptr; | |
750 | remain = args->size; | |
673a394b | 751 | |
40123c1f | 752 | offset = args->offset; |
05394f39 | 753 | obj->dirty = 1; |
40123c1f EA |
754 | |
755 | while (remain > 0) { | |
e5281ccd CW |
756 | struct page *page; |
757 | char *vaddr; | |
758 | int ret; | |
759 | ||
40123c1f EA |
760 | /* Operation in this page |
761 | * | |
40123c1f EA |
762 | * page_offset = offset within page |
763 | * page_length = bytes to copy for this page | |
764 | */ | |
40123c1f EA |
765 | page_offset = offset & (PAGE_SIZE-1); |
766 | page_length = remain; | |
767 | if ((page_offset + remain) > PAGE_SIZE) | |
768 | page_length = PAGE_SIZE - page_offset; | |
769 | ||
e5281ccd CW |
770 | page = read_cache_page_gfp(mapping, offset >> PAGE_SHIFT, |
771 | GFP_HIGHUSER | __GFP_RECLAIMABLE); | |
772 | if (IS_ERR(page)) | |
773 | return PTR_ERR(page); | |
774 | ||
775 | vaddr = kmap_atomic(page, KM_USER0); | |
776 | ret = __copy_from_user_inatomic(vaddr + page_offset, | |
777 | user_data, | |
778 | page_length); | |
779 | kunmap_atomic(vaddr, KM_USER0); | |
780 | ||
781 | set_page_dirty(page); | |
782 | mark_page_accessed(page); | |
783 | page_cache_release(page); | |
784 | ||
785 | /* If we get a fault while copying data, then (presumably) our | |
786 | * source page isn't available. Return the error and we'll | |
787 | * retry in the slow path. | |
788 | */ | |
789 | if (ret) | |
fbd5a26d | 790 | return -EFAULT; |
40123c1f EA |
791 | |
792 | remain -= page_length; | |
793 | user_data += page_length; | |
794 | offset += page_length; | |
795 | } | |
796 | ||
fbd5a26d | 797 | return 0; |
40123c1f EA |
798 | } |
799 | ||
800 | /** | |
801 | * This is the fallback shmem pwrite path, which uses get_user_pages to pin | |
802 | * the memory and maps it using kmap_atomic for copying. | |
803 | * | |
804 | * This avoids taking mmap_sem for faulting on the user's address while the | |
805 | * struct_mutex is held. | |
806 | */ | |
807 | static int | |
05394f39 CW |
808 | i915_gem_shmem_pwrite_slow(struct drm_device *dev, |
809 | struct drm_i915_gem_object *obj, | |
40123c1f | 810 | struct drm_i915_gem_pwrite *args, |
05394f39 | 811 | struct drm_file *file) |
40123c1f | 812 | { |
05394f39 | 813 | struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping; |
40123c1f EA |
814 | struct mm_struct *mm = current->mm; |
815 | struct page **user_pages; | |
816 | ssize_t remain; | |
817 | loff_t offset, pinned_pages, i; | |
818 | loff_t first_data_page, last_data_page, num_pages; | |
e5281ccd | 819 | int shmem_page_offset; |
40123c1f EA |
820 | int data_page_index, data_page_offset; |
821 | int page_length; | |
822 | int ret; | |
823 | uint64_t data_ptr = args->data_ptr; | |
280b713b | 824 | int do_bit17_swizzling; |
40123c1f EA |
825 | |
826 | remain = args->size; | |
827 | ||
828 | /* Pin the user pages containing the data. We can't fault while | |
829 | * holding the struct mutex, and all of the pwrite implementations | |
830 | * want to hold it while dereferencing the user data. | |
831 | */ | |
832 | first_data_page = data_ptr / PAGE_SIZE; | |
833 | last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE; | |
834 | num_pages = last_data_page - first_data_page + 1; | |
835 | ||
4f27b75d | 836 | user_pages = drm_malloc_ab(num_pages, sizeof(struct page *)); |
40123c1f EA |
837 | if (user_pages == NULL) |
838 | return -ENOMEM; | |
839 | ||
fbd5a26d | 840 | mutex_unlock(&dev->struct_mutex); |
40123c1f EA |
841 | down_read(&mm->mmap_sem); |
842 | pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr, | |
843 | num_pages, 0, 0, user_pages, NULL); | |
844 | up_read(&mm->mmap_sem); | |
fbd5a26d | 845 | mutex_lock(&dev->struct_mutex); |
40123c1f EA |
846 | if (pinned_pages < num_pages) { |
847 | ret = -EFAULT; | |
fbd5a26d | 848 | goto out; |
673a394b EA |
849 | } |
850 | ||
fbd5a26d | 851 | ret = i915_gem_object_set_to_cpu_domain(obj, 1); |
07f73f69 | 852 | if (ret) |
fbd5a26d | 853 | goto out; |
40123c1f | 854 | |
fbd5a26d | 855 | do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj); |
40123c1f | 856 | |
673a394b | 857 | offset = args->offset; |
05394f39 | 858 | obj->dirty = 1; |
673a394b | 859 | |
40123c1f | 860 | while (remain > 0) { |
e5281ccd CW |
861 | struct page *page; |
862 | ||
40123c1f EA |
863 | /* Operation in this page |
864 | * | |
40123c1f EA |
865 | * shmem_page_offset = offset within page in shmem file |
866 | * data_page_index = page number in get_user_pages return | |
867 | * data_page_offset = offset with data_page_index page. | |
868 | * page_length = bytes to copy for this page | |
869 | */ | |
40123c1f EA |
870 | shmem_page_offset = offset & ~PAGE_MASK; |
871 | data_page_index = data_ptr / PAGE_SIZE - first_data_page; | |
872 | data_page_offset = data_ptr & ~PAGE_MASK; | |
873 | ||
874 | page_length = remain; | |
875 | if ((shmem_page_offset + page_length) > PAGE_SIZE) | |
876 | page_length = PAGE_SIZE - shmem_page_offset; | |
877 | if ((data_page_offset + page_length) > PAGE_SIZE) | |
878 | page_length = PAGE_SIZE - data_page_offset; | |
879 | ||
e5281ccd CW |
880 | page = read_cache_page_gfp(mapping, offset >> PAGE_SHIFT, |
881 | GFP_HIGHUSER | __GFP_RECLAIMABLE); | |
882 | if (IS_ERR(page)) { | |
883 | ret = PTR_ERR(page); | |
884 | goto out; | |
885 | } | |
886 | ||
280b713b | 887 | if (do_bit17_swizzling) { |
e5281ccd | 888 | slow_shmem_bit17_copy(page, |
280b713b EA |
889 | shmem_page_offset, |
890 | user_pages[data_page_index], | |
891 | data_page_offset, | |
99a03df5 CW |
892 | page_length, |
893 | 0); | |
894 | } else { | |
e5281ccd | 895 | slow_shmem_copy(page, |
99a03df5 CW |
896 | shmem_page_offset, |
897 | user_pages[data_page_index], | |
898 | data_page_offset, | |
899 | page_length); | |
280b713b | 900 | } |
40123c1f | 901 | |
e5281ccd CW |
902 | set_page_dirty(page); |
903 | mark_page_accessed(page); | |
904 | page_cache_release(page); | |
905 | ||
40123c1f EA |
906 | remain -= page_length; |
907 | data_ptr += page_length; | |
908 | offset += page_length; | |
673a394b EA |
909 | } |
910 | ||
fbd5a26d | 911 | out: |
40123c1f EA |
912 | for (i = 0; i < pinned_pages; i++) |
913 | page_cache_release(user_pages[i]); | |
8e7d2b2c | 914 | drm_free_large(user_pages); |
673a394b | 915 | |
40123c1f | 916 | return ret; |
673a394b EA |
917 | } |
918 | ||
919 | /** | |
920 | * Writes data to the object referenced by handle. | |
921 | * | |
922 | * On error, the contents of the buffer that were to be modified are undefined. | |
923 | */ | |
924 | int | |
925 | i915_gem_pwrite_ioctl(struct drm_device *dev, void *data, | |
fbd5a26d | 926 | struct drm_file *file) |
673a394b EA |
927 | { |
928 | struct drm_i915_gem_pwrite *args = data; | |
05394f39 | 929 | struct drm_i915_gem_object *obj; |
51311d0a CW |
930 | int ret; |
931 | ||
932 | if (args->size == 0) | |
933 | return 0; | |
934 | ||
935 | if (!access_ok(VERIFY_READ, | |
936 | (char __user *)(uintptr_t)args->data_ptr, | |
937 | args->size)) | |
938 | return -EFAULT; | |
939 | ||
940 | ret = fault_in_pages_readable((char __user *)(uintptr_t)args->data_ptr, | |
941 | args->size); | |
942 | if (ret) | |
943 | return -EFAULT; | |
673a394b | 944 | |
fbd5a26d | 945 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 946 | if (ret) |
fbd5a26d | 947 | return ret; |
1d7cfea1 | 948 | |
05394f39 | 949 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
1d7cfea1 CW |
950 | if (obj == NULL) { |
951 | ret = -ENOENT; | |
952 | goto unlock; | |
fbd5a26d | 953 | } |
673a394b | 954 | |
7dcd2499 | 955 | /* Bounds check destination. */ |
05394f39 CW |
956 | if (args->offset > obj->base.size || |
957 | args->size > obj->base.size - args->offset) { | |
ce9d419d | 958 | ret = -EINVAL; |
35b62a89 | 959 | goto out; |
ce9d419d CW |
960 | } |
961 | ||
673a394b EA |
962 | /* We can only do the GTT pwrite on untiled buffers, as otherwise |
963 | * it would end up going through the fenced access, and we'll get | |
964 | * different detiling behavior between reading and writing. | |
965 | * pread/pwrite currently are reading and writing from the CPU | |
966 | * perspective, requiring manual detiling by the client. | |
967 | */ | |
05394f39 | 968 | if (obj->phys_obj) |
fbd5a26d | 969 | ret = i915_gem_phys_pwrite(dev, obj, args, file); |
d9e86c0e | 970 | else if (obj->gtt_space && |
05394f39 | 971 | obj->base.write_domain != I915_GEM_DOMAIN_CPU) { |
75e9e915 | 972 | ret = i915_gem_object_pin(obj, 0, true); |
fbd5a26d CW |
973 | if (ret) |
974 | goto out; | |
975 | ||
d9e86c0e CW |
976 | ret = i915_gem_object_set_to_gtt_domain(obj, true); |
977 | if (ret) | |
978 | goto out_unpin; | |
979 | ||
980 | ret = i915_gem_object_put_fence(obj); | |
fbd5a26d CW |
981 | if (ret) |
982 | goto out_unpin; | |
983 | ||
984 | ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file); | |
985 | if (ret == -EFAULT) | |
986 | ret = i915_gem_gtt_pwrite_slow(dev, obj, args, file); | |
987 | ||
988 | out_unpin: | |
989 | i915_gem_object_unpin(obj); | |
40123c1f | 990 | } else { |
fbd5a26d CW |
991 | ret = i915_gem_object_set_to_cpu_domain(obj, 1); |
992 | if (ret) | |
e5281ccd | 993 | goto out; |
673a394b | 994 | |
fbd5a26d CW |
995 | ret = -EFAULT; |
996 | if (!i915_gem_object_needs_bit17_swizzle(obj)) | |
997 | ret = i915_gem_shmem_pwrite_fast(dev, obj, args, file); | |
998 | if (ret == -EFAULT) | |
999 | ret = i915_gem_shmem_pwrite_slow(dev, obj, args, file); | |
fbd5a26d | 1000 | } |
673a394b | 1001 | |
35b62a89 | 1002 | out: |
05394f39 | 1003 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 1004 | unlock: |
fbd5a26d | 1005 | mutex_unlock(&dev->struct_mutex); |
673a394b EA |
1006 | return ret; |
1007 | } | |
1008 | ||
1009 | /** | |
2ef7eeaa EA |
1010 | * Called when user space prepares to use an object with the CPU, either |
1011 | * through the mmap ioctl's mapping or a GTT mapping. | |
673a394b EA |
1012 | */ |
1013 | int | |
1014 | i915_gem_set_domain_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 1015 | struct drm_file *file) |
673a394b EA |
1016 | { |
1017 | struct drm_i915_gem_set_domain *args = data; | |
05394f39 | 1018 | struct drm_i915_gem_object *obj; |
2ef7eeaa EA |
1019 | uint32_t read_domains = args->read_domains; |
1020 | uint32_t write_domain = args->write_domain; | |
673a394b EA |
1021 | int ret; |
1022 | ||
1023 | if (!(dev->driver->driver_features & DRIVER_GEM)) | |
1024 | return -ENODEV; | |
1025 | ||
2ef7eeaa | 1026 | /* Only handle setting domains to types used by the CPU. */ |
21d509e3 | 1027 | if (write_domain & I915_GEM_GPU_DOMAINS) |
2ef7eeaa EA |
1028 | return -EINVAL; |
1029 | ||
21d509e3 | 1030 | if (read_domains & I915_GEM_GPU_DOMAINS) |
2ef7eeaa EA |
1031 | return -EINVAL; |
1032 | ||
1033 | /* Having something in the write domain implies it's in the read | |
1034 | * domain, and only that read domain. Enforce that in the request. | |
1035 | */ | |
1036 | if (write_domain != 0 && read_domains != write_domain) | |
1037 | return -EINVAL; | |
1038 | ||
76c1dec1 | 1039 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 1040 | if (ret) |
76c1dec1 | 1041 | return ret; |
1d7cfea1 | 1042 | |
05394f39 | 1043 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
1d7cfea1 CW |
1044 | if (obj == NULL) { |
1045 | ret = -ENOENT; | |
1046 | goto unlock; | |
76c1dec1 | 1047 | } |
673a394b | 1048 | |
2ef7eeaa EA |
1049 | if (read_domains & I915_GEM_DOMAIN_GTT) { |
1050 | ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0); | |
02354392 EA |
1051 | |
1052 | /* Silently promote "you're not bound, there was nothing to do" | |
1053 | * to success, since the client was just asking us to | |
1054 | * make sure everything was done. | |
1055 | */ | |
1056 | if (ret == -EINVAL) | |
1057 | ret = 0; | |
2ef7eeaa | 1058 | } else { |
e47c68e9 | 1059 | ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0); |
2ef7eeaa EA |
1060 | } |
1061 | ||
05394f39 | 1062 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 1063 | unlock: |
673a394b EA |
1064 | mutex_unlock(&dev->struct_mutex); |
1065 | return ret; | |
1066 | } | |
1067 | ||
1068 | /** | |
1069 | * Called when user space has done writes to this buffer | |
1070 | */ | |
1071 | int | |
1072 | i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 1073 | struct drm_file *file) |
673a394b EA |
1074 | { |
1075 | struct drm_i915_gem_sw_finish *args = data; | |
05394f39 | 1076 | struct drm_i915_gem_object *obj; |
673a394b EA |
1077 | int ret = 0; |
1078 | ||
1079 | if (!(dev->driver->driver_features & DRIVER_GEM)) | |
1080 | return -ENODEV; | |
1081 | ||
76c1dec1 | 1082 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 1083 | if (ret) |
76c1dec1 | 1084 | return ret; |
1d7cfea1 | 1085 | |
05394f39 | 1086 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
673a394b | 1087 | if (obj == NULL) { |
1d7cfea1 CW |
1088 | ret = -ENOENT; |
1089 | goto unlock; | |
673a394b EA |
1090 | } |
1091 | ||
673a394b | 1092 | /* Pinned buffers may be scanout, so flush the cache */ |
05394f39 | 1093 | if (obj->pin_count) |
e47c68e9 EA |
1094 | i915_gem_object_flush_cpu_write_domain(obj); |
1095 | ||
05394f39 | 1096 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 1097 | unlock: |
673a394b EA |
1098 | mutex_unlock(&dev->struct_mutex); |
1099 | return ret; | |
1100 | } | |
1101 | ||
1102 | /** | |
1103 | * Maps the contents of an object, returning the address it is mapped | |
1104 | * into. | |
1105 | * | |
1106 | * While the mapping holds a reference on the contents of the object, it doesn't | |
1107 | * imply a ref on the object itself. | |
1108 | */ | |
1109 | int | |
1110 | i915_gem_mmap_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 1111 | struct drm_file *file) |
673a394b | 1112 | { |
da761a6e | 1113 | struct drm_i915_private *dev_priv = dev->dev_private; |
673a394b EA |
1114 | struct drm_i915_gem_mmap *args = data; |
1115 | struct drm_gem_object *obj; | |
673a394b EA |
1116 | unsigned long addr; |
1117 | ||
1118 | if (!(dev->driver->driver_features & DRIVER_GEM)) | |
1119 | return -ENODEV; | |
1120 | ||
05394f39 | 1121 | obj = drm_gem_object_lookup(dev, file, args->handle); |
673a394b | 1122 | if (obj == NULL) |
bf79cb91 | 1123 | return -ENOENT; |
673a394b | 1124 | |
da761a6e CW |
1125 | if (obj->size > dev_priv->mm.gtt_mappable_end) { |
1126 | drm_gem_object_unreference_unlocked(obj); | |
1127 | return -E2BIG; | |
1128 | } | |
1129 | ||
673a394b EA |
1130 | down_write(¤t->mm->mmap_sem); |
1131 | addr = do_mmap(obj->filp, 0, args->size, | |
1132 | PROT_READ | PROT_WRITE, MAP_SHARED, | |
1133 | args->offset); | |
1134 | up_write(¤t->mm->mmap_sem); | |
bc9025bd | 1135 | drm_gem_object_unreference_unlocked(obj); |
673a394b EA |
1136 | if (IS_ERR((void *)addr)) |
1137 | return addr; | |
1138 | ||
1139 | args->addr_ptr = (uint64_t) addr; | |
1140 | ||
1141 | return 0; | |
1142 | } | |
1143 | ||
de151cf6 JB |
1144 | /** |
1145 | * i915_gem_fault - fault a page into the GTT | |
1146 | * vma: VMA in question | |
1147 | * vmf: fault info | |
1148 | * | |
1149 | * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped | |
1150 | * from userspace. The fault handler takes care of binding the object to | |
1151 | * the GTT (if needed), allocating and programming a fence register (again, | |
1152 | * only if needed based on whether the old reg is still valid or the object | |
1153 | * is tiled) and inserting a new PTE into the faulting process. | |
1154 | * | |
1155 | * Note that the faulting process may involve evicting existing objects | |
1156 | * from the GTT and/or fence registers to make room. So performance may | |
1157 | * suffer if the GTT working set is large or there are few fence registers | |
1158 | * left. | |
1159 | */ | |
1160 | int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf) | |
1161 | { | |
05394f39 CW |
1162 | struct drm_i915_gem_object *obj = to_intel_bo(vma->vm_private_data); |
1163 | struct drm_device *dev = obj->base.dev; | |
7d1c4804 | 1164 | drm_i915_private_t *dev_priv = dev->dev_private; |
de151cf6 JB |
1165 | pgoff_t page_offset; |
1166 | unsigned long pfn; | |
1167 | int ret = 0; | |
0f973f27 | 1168 | bool write = !!(vmf->flags & FAULT_FLAG_WRITE); |
de151cf6 JB |
1169 | |
1170 | /* We don't use vmf->pgoff since that has the fake offset */ | |
1171 | page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >> | |
1172 | PAGE_SHIFT; | |
1173 | ||
1174 | /* Now bind it into the GTT if needed */ | |
1175 | mutex_lock(&dev->struct_mutex); | |
a00b10c3 | 1176 | |
919926ae CW |
1177 | if (!obj->map_and_fenceable) { |
1178 | ret = i915_gem_object_unbind(obj); | |
1179 | if (ret) | |
1180 | goto unlock; | |
a00b10c3 | 1181 | } |
05394f39 | 1182 | if (!obj->gtt_space) { |
75e9e915 | 1183 | ret = i915_gem_object_bind_to_gtt(obj, 0, true); |
c715089f CW |
1184 | if (ret) |
1185 | goto unlock; | |
de151cf6 JB |
1186 | } |
1187 | ||
4a684a41 CW |
1188 | ret = i915_gem_object_set_to_gtt_domain(obj, write); |
1189 | if (ret) | |
1190 | goto unlock; | |
1191 | ||
d9e86c0e CW |
1192 | if (obj->tiling_mode == I915_TILING_NONE) |
1193 | ret = i915_gem_object_put_fence(obj); | |
1194 | else | |
1195 | ret = i915_gem_object_get_fence(obj, NULL, true); | |
1196 | if (ret) | |
1197 | goto unlock; | |
de151cf6 | 1198 | |
05394f39 CW |
1199 | if (i915_gem_object_is_inactive(obj)) |
1200 | list_move_tail(&obj->mm_list, &dev_priv->mm.inactive_list); | |
7d1c4804 | 1201 | |
6299f992 CW |
1202 | obj->fault_mappable = true; |
1203 | ||
05394f39 | 1204 | pfn = ((dev->agp->base + obj->gtt_offset) >> PAGE_SHIFT) + |
de151cf6 JB |
1205 | page_offset; |
1206 | ||
1207 | /* Finally, remap it using the new GTT offset */ | |
1208 | ret = vm_insert_pfn(vma, (unsigned long)vmf->virtual_address, pfn); | |
c715089f | 1209 | unlock: |
de151cf6 JB |
1210 | mutex_unlock(&dev->struct_mutex); |
1211 | ||
1212 | switch (ret) { | |
045e769a CW |
1213 | case -EAGAIN: |
1214 | set_need_resched(); | |
c715089f CW |
1215 | case 0: |
1216 | case -ERESTARTSYS: | |
1217 | return VM_FAULT_NOPAGE; | |
de151cf6 | 1218 | case -ENOMEM: |
de151cf6 | 1219 | return VM_FAULT_OOM; |
de151cf6 | 1220 | default: |
c715089f | 1221 | return VM_FAULT_SIGBUS; |
de151cf6 JB |
1222 | } |
1223 | } | |
1224 | ||
1225 | /** | |
1226 | * i915_gem_create_mmap_offset - create a fake mmap offset for an object | |
1227 | * @obj: obj in question | |
1228 | * | |
1229 | * GEM memory mapping works by handing back to userspace a fake mmap offset | |
1230 | * it can use in a subsequent mmap(2) call. The DRM core code then looks | |
1231 | * up the object based on the offset and sets up the various memory mapping | |
1232 | * structures. | |
1233 | * | |
1234 | * This routine allocates and attaches a fake offset for @obj. | |
1235 | */ | |
1236 | static int | |
05394f39 | 1237 | i915_gem_create_mmap_offset(struct drm_i915_gem_object *obj) |
de151cf6 | 1238 | { |
05394f39 | 1239 | struct drm_device *dev = obj->base.dev; |
de151cf6 | 1240 | struct drm_gem_mm *mm = dev->mm_private; |
de151cf6 | 1241 | struct drm_map_list *list; |
f77d390c | 1242 | struct drm_local_map *map; |
de151cf6 JB |
1243 | int ret = 0; |
1244 | ||
1245 | /* Set the object up for mmap'ing */ | |
05394f39 | 1246 | list = &obj->base.map_list; |
9a298b2a | 1247 | list->map = kzalloc(sizeof(struct drm_map_list), GFP_KERNEL); |
de151cf6 JB |
1248 | if (!list->map) |
1249 | return -ENOMEM; | |
1250 | ||
1251 | map = list->map; | |
1252 | map->type = _DRM_GEM; | |
05394f39 | 1253 | map->size = obj->base.size; |
de151cf6 JB |
1254 | map->handle = obj; |
1255 | ||
1256 | /* Get a DRM GEM mmap offset allocated... */ | |
1257 | list->file_offset_node = drm_mm_search_free(&mm->offset_manager, | |
05394f39 CW |
1258 | obj->base.size / PAGE_SIZE, |
1259 | 0, 0); | |
de151cf6 | 1260 | if (!list->file_offset_node) { |
05394f39 CW |
1261 | DRM_ERROR("failed to allocate offset for bo %d\n", |
1262 | obj->base.name); | |
9e0ae534 | 1263 | ret = -ENOSPC; |
de151cf6 JB |
1264 | goto out_free_list; |
1265 | } | |
1266 | ||
1267 | list->file_offset_node = drm_mm_get_block(list->file_offset_node, | |
05394f39 CW |
1268 | obj->base.size / PAGE_SIZE, |
1269 | 0); | |
de151cf6 JB |
1270 | if (!list->file_offset_node) { |
1271 | ret = -ENOMEM; | |
1272 | goto out_free_list; | |
1273 | } | |
1274 | ||
1275 | list->hash.key = list->file_offset_node->start; | |
9e0ae534 CW |
1276 | ret = drm_ht_insert_item(&mm->offset_hash, &list->hash); |
1277 | if (ret) { | |
de151cf6 JB |
1278 | DRM_ERROR("failed to add to map hash\n"); |
1279 | goto out_free_mm; | |
1280 | } | |
1281 | ||
de151cf6 JB |
1282 | return 0; |
1283 | ||
1284 | out_free_mm: | |
1285 | drm_mm_put_block(list->file_offset_node); | |
1286 | out_free_list: | |
9a298b2a | 1287 | kfree(list->map); |
39a01d1f | 1288 | list->map = NULL; |
de151cf6 JB |
1289 | |
1290 | return ret; | |
1291 | } | |
1292 | ||
901782b2 CW |
1293 | /** |
1294 | * i915_gem_release_mmap - remove physical page mappings | |
1295 | * @obj: obj in question | |
1296 | * | |
af901ca1 | 1297 | * Preserve the reservation of the mmapping with the DRM core code, but |
901782b2 CW |
1298 | * relinquish ownership of the pages back to the system. |
1299 | * | |
1300 | * It is vital that we remove the page mapping if we have mapped a tiled | |
1301 | * object through the GTT and then lose the fence register due to | |
1302 | * resource pressure. Similarly if the object has been moved out of the | |
1303 | * aperture, than pages mapped into userspace must be revoked. Removing the | |
1304 | * mapping will then trigger a page fault on the next user access, allowing | |
1305 | * fixup by i915_gem_fault(). | |
1306 | */ | |
d05ca301 | 1307 | void |
05394f39 | 1308 | i915_gem_release_mmap(struct drm_i915_gem_object *obj) |
901782b2 | 1309 | { |
6299f992 CW |
1310 | if (!obj->fault_mappable) |
1311 | return; | |
901782b2 | 1312 | |
6299f992 CW |
1313 | unmap_mapping_range(obj->base.dev->dev_mapping, |
1314 | (loff_t)obj->base.map_list.hash.key<<PAGE_SHIFT, | |
1315 | obj->base.size, 1); | |
fb7d516a | 1316 | |
6299f992 | 1317 | obj->fault_mappable = false; |
901782b2 CW |
1318 | } |
1319 | ||
ab00b3e5 | 1320 | static void |
05394f39 | 1321 | i915_gem_free_mmap_offset(struct drm_i915_gem_object *obj) |
ab00b3e5 | 1322 | { |
05394f39 | 1323 | struct drm_device *dev = obj->base.dev; |
ab00b3e5 | 1324 | struct drm_gem_mm *mm = dev->mm_private; |
05394f39 | 1325 | struct drm_map_list *list = &obj->base.map_list; |
ab00b3e5 | 1326 | |
ab00b3e5 | 1327 | drm_ht_remove_item(&mm->offset_hash, &list->hash); |
39a01d1f CW |
1328 | drm_mm_put_block(list->file_offset_node); |
1329 | kfree(list->map); | |
1330 | list->map = NULL; | |
ab00b3e5 JB |
1331 | } |
1332 | ||
92b88aeb CW |
1333 | static uint32_t |
1334 | i915_gem_get_gtt_size(struct drm_i915_gem_object *obj) | |
1335 | { | |
1336 | struct drm_device *dev = obj->base.dev; | |
1337 | uint32_t size; | |
1338 | ||
1339 | if (INTEL_INFO(dev)->gen >= 4 || | |
1340 | obj->tiling_mode == I915_TILING_NONE) | |
1341 | return obj->base.size; | |
1342 | ||
1343 | /* Previous chips need a power-of-two fence region when tiling */ | |
1344 | if (INTEL_INFO(dev)->gen == 3) | |
1345 | size = 1024*1024; | |
1346 | else | |
1347 | size = 512*1024; | |
1348 | ||
1349 | while (size < obj->base.size) | |
1350 | size <<= 1; | |
1351 | ||
1352 | return size; | |
1353 | } | |
1354 | ||
de151cf6 JB |
1355 | /** |
1356 | * i915_gem_get_gtt_alignment - return required GTT alignment for an object | |
1357 | * @obj: object to check | |
1358 | * | |
1359 | * Return the required GTT alignment for an object, taking into account | |
5e783301 | 1360 | * potential fence register mapping. |
de151cf6 JB |
1361 | */ |
1362 | static uint32_t | |
05394f39 | 1363 | i915_gem_get_gtt_alignment(struct drm_i915_gem_object *obj) |
de151cf6 | 1364 | { |
05394f39 | 1365 | struct drm_device *dev = obj->base.dev; |
de151cf6 JB |
1366 | |
1367 | /* | |
1368 | * Minimum alignment is 4k (GTT page size), but might be greater | |
1369 | * if a fence register is needed for the object. | |
1370 | */ | |
a00b10c3 | 1371 | if (INTEL_INFO(dev)->gen >= 4 || |
05394f39 | 1372 | obj->tiling_mode == I915_TILING_NONE) |
de151cf6 JB |
1373 | return 4096; |
1374 | ||
a00b10c3 CW |
1375 | /* |
1376 | * Previous chips need to be aligned to the size of the smallest | |
1377 | * fence register that can contain the object. | |
1378 | */ | |
05394f39 | 1379 | return i915_gem_get_gtt_size(obj); |
a00b10c3 CW |
1380 | } |
1381 | ||
5e783301 DV |
1382 | /** |
1383 | * i915_gem_get_unfenced_gtt_alignment - return required GTT alignment for an | |
1384 | * unfenced object | |
1385 | * @obj: object to check | |
1386 | * | |
1387 | * Return the required GTT alignment for an object, only taking into account | |
1388 | * unfenced tiled surface requirements. | |
1389 | */ | |
1390 | static uint32_t | |
05394f39 | 1391 | i915_gem_get_unfenced_gtt_alignment(struct drm_i915_gem_object *obj) |
5e783301 | 1392 | { |
05394f39 | 1393 | struct drm_device *dev = obj->base.dev; |
5e783301 DV |
1394 | int tile_height; |
1395 | ||
1396 | /* | |
1397 | * Minimum alignment is 4k (GTT page size) for sane hw. | |
1398 | */ | |
1399 | if (INTEL_INFO(dev)->gen >= 4 || IS_G33(dev) || | |
05394f39 | 1400 | obj->tiling_mode == I915_TILING_NONE) |
5e783301 DV |
1401 | return 4096; |
1402 | ||
1403 | /* | |
1404 | * Older chips need unfenced tiled buffers to be aligned to the left | |
1405 | * edge of an even tile row (where tile rows are counted as if the bo is | |
1406 | * placed in a fenced gtt region). | |
1407 | */ | |
1408 | if (IS_GEN2(dev) || | |
05394f39 | 1409 | (obj->tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev))) |
5e783301 DV |
1410 | tile_height = 32; |
1411 | else | |
1412 | tile_height = 8; | |
1413 | ||
05394f39 | 1414 | return tile_height * obj->stride * 2; |
5e783301 DV |
1415 | } |
1416 | ||
de151cf6 JB |
1417 | /** |
1418 | * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing | |
1419 | * @dev: DRM device | |
1420 | * @data: GTT mapping ioctl data | |
05394f39 | 1421 | * @file: GEM object info |
de151cf6 JB |
1422 | * |
1423 | * Simply returns the fake offset to userspace so it can mmap it. | |
1424 | * The mmap call will end up in drm_gem_mmap(), which will set things | |
1425 | * up so we can get faults in the handler above. | |
1426 | * | |
1427 | * The fault handler will take care of binding the object into the GTT | |
1428 | * (since it may have been evicted to make room for something), allocating | |
1429 | * a fence register, and mapping the appropriate aperture address into | |
1430 | * userspace. | |
1431 | */ | |
1432 | int | |
1433 | i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 1434 | struct drm_file *file) |
de151cf6 | 1435 | { |
da761a6e | 1436 | struct drm_i915_private *dev_priv = dev->dev_private; |
de151cf6 | 1437 | struct drm_i915_gem_mmap_gtt *args = data; |
05394f39 | 1438 | struct drm_i915_gem_object *obj; |
de151cf6 JB |
1439 | int ret; |
1440 | ||
1441 | if (!(dev->driver->driver_features & DRIVER_GEM)) | |
1442 | return -ENODEV; | |
1443 | ||
76c1dec1 | 1444 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 1445 | if (ret) |
76c1dec1 | 1446 | return ret; |
de151cf6 | 1447 | |
05394f39 | 1448 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
1d7cfea1 CW |
1449 | if (obj == NULL) { |
1450 | ret = -ENOENT; | |
1451 | goto unlock; | |
1452 | } | |
de151cf6 | 1453 | |
05394f39 | 1454 | if (obj->base.size > dev_priv->mm.gtt_mappable_end) { |
da761a6e CW |
1455 | ret = -E2BIG; |
1456 | goto unlock; | |
1457 | } | |
1458 | ||
05394f39 | 1459 | if (obj->madv != I915_MADV_WILLNEED) { |
ab18282d | 1460 | DRM_ERROR("Attempting to mmap a purgeable buffer\n"); |
1d7cfea1 CW |
1461 | ret = -EINVAL; |
1462 | goto out; | |
ab18282d CW |
1463 | } |
1464 | ||
05394f39 | 1465 | if (!obj->base.map_list.map) { |
de151cf6 | 1466 | ret = i915_gem_create_mmap_offset(obj); |
1d7cfea1 CW |
1467 | if (ret) |
1468 | goto out; | |
de151cf6 JB |
1469 | } |
1470 | ||
05394f39 | 1471 | args->offset = (u64)obj->base.map_list.hash.key << PAGE_SHIFT; |
de151cf6 | 1472 | |
1d7cfea1 | 1473 | out: |
05394f39 | 1474 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 1475 | unlock: |
de151cf6 | 1476 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 1477 | return ret; |
de151cf6 JB |
1478 | } |
1479 | ||
e5281ccd | 1480 | static int |
05394f39 | 1481 | i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj, |
e5281ccd CW |
1482 | gfp_t gfpmask) |
1483 | { | |
e5281ccd CW |
1484 | int page_count, i; |
1485 | struct address_space *mapping; | |
1486 | struct inode *inode; | |
1487 | struct page *page; | |
1488 | ||
1489 | /* Get the list of pages out of our struct file. They'll be pinned | |
1490 | * at this point until we release them. | |
1491 | */ | |
05394f39 CW |
1492 | page_count = obj->base.size / PAGE_SIZE; |
1493 | BUG_ON(obj->pages != NULL); | |
1494 | obj->pages = drm_malloc_ab(page_count, sizeof(struct page *)); | |
1495 | if (obj->pages == NULL) | |
e5281ccd CW |
1496 | return -ENOMEM; |
1497 | ||
05394f39 | 1498 | inode = obj->base.filp->f_path.dentry->d_inode; |
e5281ccd CW |
1499 | mapping = inode->i_mapping; |
1500 | for (i = 0; i < page_count; i++) { | |
1501 | page = read_cache_page_gfp(mapping, i, | |
1502 | GFP_HIGHUSER | | |
1503 | __GFP_COLD | | |
1504 | __GFP_RECLAIMABLE | | |
1505 | gfpmask); | |
1506 | if (IS_ERR(page)) | |
1507 | goto err_pages; | |
1508 | ||
05394f39 | 1509 | obj->pages[i] = page; |
e5281ccd CW |
1510 | } |
1511 | ||
05394f39 | 1512 | if (obj->tiling_mode != I915_TILING_NONE) |
e5281ccd CW |
1513 | i915_gem_object_do_bit_17_swizzle(obj); |
1514 | ||
1515 | return 0; | |
1516 | ||
1517 | err_pages: | |
1518 | while (i--) | |
05394f39 | 1519 | page_cache_release(obj->pages[i]); |
e5281ccd | 1520 | |
05394f39 CW |
1521 | drm_free_large(obj->pages); |
1522 | obj->pages = NULL; | |
e5281ccd CW |
1523 | return PTR_ERR(page); |
1524 | } | |
1525 | ||
5cdf5881 | 1526 | static void |
05394f39 | 1527 | i915_gem_object_put_pages_gtt(struct drm_i915_gem_object *obj) |
673a394b | 1528 | { |
05394f39 | 1529 | int page_count = obj->base.size / PAGE_SIZE; |
673a394b EA |
1530 | int i; |
1531 | ||
05394f39 | 1532 | BUG_ON(obj->madv == __I915_MADV_PURGED); |
673a394b | 1533 | |
05394f39 | 1534 | if (obj->tiling_mode != I915_TILING_NONE) |
280b713b EA |
1535 | i915_gem_object_save_bit_17_swizzle(obj); |
1536 | ||
05394f39 CW |
1537 | if (obj->madv == I915_MADV_DONTNEED) |
1538 | obj->dirty = 0; | |
3ef94daa CW |
1539 | |
1540 | for (i = 0; i < page_count; i++) { | |
05394f39 CW |
1541 | if (obj->dirty) |
1542 | set_page_dirty(obj->pages[i]); | |
3ef94daa | 1543 | |
05394f39 CW |
1544 | if (obj->madv == I915_MADV_WILLNEED) |
1545 | mark_page_accessed(obj->pages[i]); | |
3ef94daa | 1546 | |
05394f39 | 1547 | page_cache_release(obj->pages[i]); |
3ef94daa | 1548 | } |
05394f39 | 1549 | obj->dirty = 0; |
673a394b | 1550 | |
05394f39 CW |
1551 | drm_free_large(obj->pages); |
1552 | obj->pages = NULL; | |
673a394b EA |
1553 | } |
1554 | ||
54cf91dc | 1555 | void |
05394f39 | 1556 | i915_gem_object_move_to_active(struct drm_i915_gem_object *obj, |
1ec14ad3 CW |
1557 | struct intel_ring_buffer *ring, |
1558 | u32 seqno) | |
673a394b | 1559 | { |
05394f39 | 1560 | struct drm_device *dev = obj->base.dev; |
69dc4987 | 1561 | struct drm_i915_private *dev_priv = dev->dev_private; |
617dbe27 | 1562 | |
852835f3 | 1563 | BUG_ON(ring == NULL); |
05394f39 | 1564 | obj->ring = ring; |
673a394b EA |
1565 | |
1566 | /* Add a reference if we're newly entering the active list. */ | |
05394f39 CW |
1567 | if (!obj->active) { |
1568 | drm_gem_object_reference(&obj->base); | |
1569 | obj->active = 1; | |
673a394b | 1570 | } |
e35a41de | 1571 | |
673a394b | 1572 | /* Move from whatever list we were on to the tail of execution. */ |
05394f39 CW |
1573 | list_move_tail(&obj->mm_list, &dev_priv->mm.active_list); |
1574 | list_move_tail(&obj->ring_list, &ring->active_list); | |
caea7476 | 1575 | |
05394f39 | 1576 | obj->last_rendering_seqno = seqno; |
caea7476 CW |
1577 | if (obj->fenced_gpu_access) { |
1578 | struct drm_i915_fence_reg *reg; | |
1579 | ||
1580 | BUG_ON(obj->fence_reg == I915_FENCE_REG_NONE); | |
1581 | ||
1582 | obj->last_fenced_seqno = seqno; | |
1583 | obj->last_fenced_ring = ring; | |
1584 | ||
1585 | reg = &dev_priv->fence_regs[obj->fence_reg]; | |
1586 | list_move_tail(®->lru_list, &dev_priv->mm.fence_list); | |
1587 | } | |
1588 | } | |
1589 | ||
1590 | static void | |
1591 | i915_gem_object_move_off_active(struct drm_i915_gem_object *obj) | |
1592 | { | |
1593 | list_del_init(&obj->ring_list); | |
1594 | obj->last_rendering_seqno = 0; | |
673a394b EA |
1595 | } |
1596 | ||
ce44b0ea | 1597 | static void |
05394f39 | 1598 | i915_gem_object_move_to_flushing(struct drm_i915_gem_object *obj) |
ce44b0ea | 1599 | { |
05394f39 | 1600 | struct drm_device *dev = obj->base.dev; |
ce44b0ea | 1601 | drm_i915_private_t *dev_priv = dev->dev_private; |
ce44b0ea | 1602 | |
05394f39 CW |
1603 | BUG_ON(!obj->active); |
1604 | list_move_tail(&obj->mm_list, &dev_priv->mm.flushing_list); | |
caea7476 CW |
1605 | |
1606 | i915_gem_object_move_off_active(obj); | |
1607 | } | |
1608 | ||
1609 | static void | |
1610 | i915_gem_object_move_to_inactive(struct drm_i915_gem_object *obj) | |
1611 | { | |
1612 | struct drm_device *dev = obj->base.dev; | |
1613 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1614 | ||
1615 | if (obj->pin_count != 0) | |
1616 | list_move_tail(&obj->mm_list, &dev_priv->mm.pinned_list); | |
1617 | else | |
1618 | list_move_tail(&obj->mm_list, &dev_priv->mm.inactive_list); | |
1619 | ||
1620 | BUG_ON(!list_empty(&obj->gpu_write_list)); | |
1621 | BUG_ON(!obj->active); | |
1622 | obj->ring = NULL; | |
1623 | ||
1624 | i915_gem_object_move_off_active(obj); | |
1625 | obj->fenced_gpu_access = false; | |
caea7476 CW |
1626 | |
1627 | obj->active = 0; | |
87ca9c8a | 1628 | obj->pending_gpu_write = false; |
caea7476 CW |
1629 | drm_gem_object_unreference(&obj->base); |
1630 | ||
1631 | WARN_ON(i915_verify_lists(dev)); | |
ce44b0ea | 1632 | } |
673a394b | 1633 | |
963b4836 CW |
1634 | /* Immediately discard the backing storage */ |
1635 | static void | |
05394f39 | 1636 | i915_gem_object_truncate(struct drm_i915_gem_object *obj) |
963b4836 | 1637 | { |
bb6baf76 | 1638 | struct inode *inode; |
963b4836 | 1639 | |
ae9fed6b CW |
1640 | /* Our goal here is to return as much of the memory as |
1641 | * is possible back to the system as we are called from OOM. | |
1642 | * To do this we must instruct the shmfs to drop all of its | |
1643 | * backing pages, *now*. Here we mirror the actions taken | |
1644 | * when by shmem_delete_inode() to release the backing store. | |
1645 | */ | |
05394f39 | 1646 | inode = obj->base.filp->f_path.dentry->d_inode; |
ae9fed6b CW |
1647 | truncate_inode_pages(inode->i_mapping, 0); |
1648 | if (inode->i_op->truncate_range) | |
1649 | inode->i_op->truncate_range(inode, 0, (loff_t)-1); | |
bb6baf76 | 1650 | |
05394f39 | 1651 | obj->madv = __I915_MADV_PURGED; |
963b4836 CW |
1652 | } |
1653 | ||
1654 | static inline int | |
05394f39 | 1655 | i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj) |
963b4836 | 1656 | { |
05394f39 | 1657 | return obj->madv == I915_MADV_DONTNEED; |
963b4836 CW |
1658 | } |
1659 | ||
63560396 DV |
1660 | static void |
1661 | i915_gem_process_flushing_list(struct drm_device *dev, | |
8a1a49f9 | 1662 | uint32_t flush_domains, |
852835f3 | 1663 | struct intel_ring_buffer *ring) |
63560396 | 1664 | { |
05394f39 | 1665 | struct drm_i915_gem_object *obj, *next; |
63560396 | 1666 | |
05394f39 | 1667 | list_for_each_entry_safe(obj, next, |
64193406 | 1668 | &ring->gpu_write_list, |
63560396 | 1669 | gpu_write_list) { |
05394f39 CW |
1670 | if (obj->base.write_domain & flush_domains) { |
1671 | uint32_t old_write_domain = obj->base.write_domain; | |
63560396 | 1672 | |
05394f39 CW |
1673 | obj->base.write_domain = 0; |
1674 | list_del_init(&obj->gpu_write_list); | |
1ec14ad3 CW |
1675 | i915_gem_object_move_to_active(obj, ring, |
1676 | i915_gem_next_request_seqno(dev, ring)); | |
63560396 | 1677 | |
63560396 | 1678 | trace_i915_gem_object_change_domain(obj, |
05394f39 | 1679 | obj->base.read_domains, |
63560396 DV |
1680 | old_write_domain); |
1681 | } | |
1682 | } | |
1683 | } | |
8187a2b7 | 1684 | |
3cce469c | 1685 | int |
8a1a49f9 | 1686 | i915_add_request(struct drm_device *dev, |
f787a5f5 | 1687 | struct drm_file *file, |
8dc5d147 | 1688 | struct drm_i915_gem_request *request, |
8a1a49f9 | 1689 | struct intel_ring_buffer *ring) |
673a394b EA |
1690 | { |
1691 | drm_i915_private_t *dev_priv = dev->dev_private; | |
f787a5f5 | 1692 | struct drm_i915_file_private *file_priv = NULL; |
673a394b EA |
1693 | uint32_t seqno; |
1694 | int was_empty; | |
3cce469c CW |
1695 | int ret; |
1696 | ||
1697 | BUG_ON(request == NULL); | |
673a394b | 1698 | |
f787a5f5 CW |
1699 | if (file != NULL) |
1700 | file_priv = file->driver_priv; | |
b962442e | 1701 | |
3cce469c CW |
1702 | ret = ring->add_request(ring, &seqno); |
1703 | if (ret) | |
1704 | return ret; | |
673a394b | 1705 | |
a56ba56c | 1706 | ring->outstanding_lazy_request = false; |
673a394b EA |
1707 | |
1708 | request->seqno = seqno; | |
852835f3 | 1709 | request->ring = ring; |
673a394b | 1710 | request->emitted_jiffies = jiffies; |
852835f3 ZN |
1711 | was_empty = list_empty(&ring->request_list); |
1712 | list_add_tail(&request->list, &ring->request_list); | |
1713 | ||
f787a5f5 | 1714 | if (file_priv) { |
1c25595f | 1715 | spin_lock(&file_priv->mm.lock); |
f787a5f5 | 1716 | request->file_priv = file_priv; |
b962442e | 1717 | list_add_tail(&request->client_list, |
f787a5f5 | 1718 | &file_priv->mm.request_list); |
1c25595f | 1719 | spin_unlock(&file_priv->mm.lock); |
b962442e | 1720 | } |
673a394b | 1721 | |
f65d9421 | 1722 | if (!dev_priv->mm.suspended) { |
b3b079db CW |
1723 | mod_timer(&dev_priv->hangcheck_timer, |
1724 | jiffies + msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)); | |
f65d9421 | 1725 | if (was_empty) |
b3b079db CW |
1726 | queue_delayed_work(dev_priv->wq, |
1727 | &dev_priv->mm.retire_work, HZ); | |
f65d9421 | 1728 | } |
3cce469c | 1729 | return 0; |
673a394b EA |
1730 | } |
1731 | ||
f787a5f5 CW |
1732 | static inline void |
1733 | i915_gem_request_remove_from_client(struct drm_i915_gem_request *request) | |
673a394b | 1734 | { |
1c25595f | 1735 | struct drm_i915_file_private *file_priv = request->file_priv; |
673a394b | 1736 | |
1c25595f CW |
1737 | if (!file_priv) |
1738 | return; | |
1c5d22f7 | 1739 | |
1c25595f CW |
1740 | spin_lock(&file_priv->mm.lock); |
1741 | list_del(&request->client_list); | |
1742 | request->file_priv = NULL; | |
1743 | spin_unlock(&file_priv->mm.lock); | |
673a394b | 1744 | } |
673a394b | 1745 | |
dfaae392 CW |
1746 | static void i915_gem_reset_ring_lists(struct drm_i915_private *dev_priv, |
1747 | struct intel_ring_buffer *ring) | |
9375e446 | 1748 | { |
dfaae392 CW |
1749 | while (!list_empty(&ring->request_list)) { |
1750 | struct drm_i915_gem_request *request; | |
673a394b | 1751 | |
dfaae392 CW |
1752 | request = list_first_entry(&ring->request_list, |
1753 | struct drm_i915_gem_request, | |
1754 | list); | |
de151cf6 | 1755 | |
dfaae392 | 1756 | list_del(&request->list); |
f787a5f5 | 1757 | i915_gem_request_remove_from_client(request); |
dfaae392 CW |
1758 | kfree(request); |
1759 | } | |
673a394b | 1760 | |
dfaae392 | 1761 | while (!list_empty(&ring->active_list)) { |
05394f39 | 1762 | struct drm_i915_gem_object *obj; |
9375e446 | 1763 | |
05394f39 CW |
1764 | obj = list_first_entry(&ring->active_list, |
1765 | struct drm_i915_gem_object, | |
1766 | ring_list); | |
9375e446 | 1767 | |
05394f39 CW |
1768 | obj->base.write_domain = 0; |
1769 | list_del_init(&obj->gpu_write_list); | |
1770 | i915_gem_object_move_to_inactive(obj); | |
673a394b EA |
1771 | } |
1772 | } | |
1773 | ||
312817a3 CW |
1774 | static void i915_gem_reset_fences(struct drm_device *dev) |
1775 | { | |
1776 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1777 | int i; | |
1778 | ||
1779 | for (i = 0; i < 16; i++) { | |
1780 | struct drm_i915_fence_reg *reg = &dev_priv->fence_regs[i]; | |
7d2cb39c CW |
1781 | struct drm_i915_gem_object *obj = reg->obj; |
1782 | ||
1783 | if (!obj) | |
1784 | continue; | |
1785 | ||
1786 | if (obj->tiling_mode) | |
1787 | i915_gem_release_mmap(obj); | |
1788 | ||
d9e86c0e CW |
1789 | reg->obj->fence_reg = I915_FENCE_REG_NONE; |
1790 | reg->obj->fenced_gpu_access = false; | |
1791 | reg->obj->last_fenced_seqno = 0; | |
1792 | reg->obj->last_fenced_ring = NULL; | |
1793 | i915_gem_clear_fence_reg(dev, reg); | |
312817a3 CW |
1794 | } |
1795 | } | |
1796 | ||
069efc1d | 1797 | void i915_gem_reset(struct drm_device *dev) |
673a394b | 1798 | { |
77f01230 | 1799 | struct drm_i915_private *dev_priv = dev->dev_private; |
05394f39 | 1800 | struct drm_i915_gem_object *obj; |
1ec14ad3 | 1801 | int i; |
673a394b | 1802 | |
1ec14ad3 CW |
1803 | for (i = 0; i < I915_NUM_RINGS; i++) |
1804 | i915_gem_reset_ring_lists(dev_priv, &dev_priv->ring[i]); | |
dfaae392 CW |
1805 | |
1806 | /* Remove anything from the flushing lists. The GPU cache is likely | |
1807 | * to be lost on reset along with the data, so simply move the | |
1808 | * lost bo to the inactive list. | |
1809 | */ | |
1810 | while (!list_empty(&dev_priv->mm.flushing_list)) { | |
05394f39 CW |
1811 | obj= list_first_entry(&dev_priv->mm.flushing_list, |
1812 | struct drm_i915_gem_object, | |
1813 | mm_list); | |
dfaae392 | 1814 | |
05394f39 CW |
1815 | obj->base.write_domain = 0; |
1816 | list_del_init(&obj->gpu_write_list); | |
1817 | i915_gem_object_move_to_inactive(obj); | |
dfaae392 CW |
1818 | } |
1819 | ||
1820 | /* Move everything out of the GPU domains to ensure we do any | |
1821 | * necessary invalidation upon reuse. | |
1822 | */ | |
05394f39 | 1823 | list_for_each_entry(obj, |
77f01230 | 1824 | &dev_priv->mm.inactive_list, |
69dc4987 | 1825 | mm_list) |
77f01230 | 1826 | { |
05394f39 | 1827 | obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS; |
77f01230 | 1828 | } |
069efc1d CW |
1829 | |
1830 | /* The fence registers are invalidated so clear them out */ | |
312817a3 | 1831 | i915_gem_reset_fences(dev); |
673a394b EA |
1832 | } |
1833 | ||
1834 | /** | |
1835 | * This function clears the request list as sequence numbers are passed. | |
1836 | */ | |
b09a1fec CW |
1837 | static void |
1838 | i915_gem_retire_requests_ring(struct drm_device *dev, | |
1839 | struct intel_ring_buffer *ring) | |
673a394b EA |
1840 | { |
1841 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1842 | uint32_t seqno; | |
1ec14ad3 | 1843 | int i; |
673a394b | 1844 | |
b84d5f0c CW |
1845 | if (!ring->status_page.page_addr || |
1846 | list_empty(&ring->request_list)) | |
6c0594a3 KW |
1847 | return; |
1848 | ||
23bc5982 | 1849 | WARN_ON(i915_verify_lists(dev)); |
673a394b | 1850 | |
78501eac | 1851 | seqno = ring->get_seqno(ring); |
1ec14ad3 | 1852 | |
076e2c0e | 1853 | for (i = 0; i < ARRAY_SIZE(ring->sync_seqno); i++) |
1ec14ad3 CW |
1854 | if (seqno >= ring->sync_seqno[i]) |
1855 | ring->sync_seqno[i] = 0; | |
1856 | ||
852835f3 | 1857 | while (!list_empty(&ring->request_list)) { |
673a394b | 1858 | struct drm_i915_gem_request *request; |
673a394b | 1859 | |
852835f3 | 1860 | request = list_first_entry(&ring->request_list, |
673a394b EA |
1861 | struct drm_i915_gem_request, |
1862 | list); | |
673a394b | 1863 | |
dfaae392 | 1864 | if (!i915_seqno_passed(seqno, request->seqno)) |
b84d5f0c CW |
1865 | break; |
1866 | ||
1867 | trace_i915_gem_request_retire(dev, request->seqno); | |
1868 | ||
1869 | list_del(&request->list); | |
f787a5f5 | 1870 | i915_gem_request_remove_from_client(request); |
b84d5f0c CW |
1871 | kfree(request); |
1872 | } | |
673a394b | 1873 | |
b84d5f0c CW |
1874 | /* Move any buffers on the active list that are no longer referenced |
1875 | * by the ringbuffer to the flushing/inactive lists as appropriate. | |
1876 | */ | |
1877 | while (!list_empty(&ring->active_list)) { | |
05394f39 | 1878 | struct drm_i915_gem_object *obj; |
b84d5f0c | 1879 | |
05394f39 CW |
1880 | obj= list_first_entry(&ring->active_list, |
1881 | struct drm_i915_gem_object, | |
1882 | ring_list); | |
673a394b | 1883 | |
05394f39 | 1884 | if (!i915_seqno_passed(seqno, obj->last_rendering_seqno)) |
673a394b | 1885 | break; |
b84d5f0c | 1886 | |
05394f39 | 1887 | if (obj->base.write_domain != 0) |
b84d5f0c CW |
1888 | i915_gem_object_move_to_flushing(obj); |
1889 | else | |
1890 | i915_gem_object_move_to_inactive(obj); | |
673a394b | 1891 | } |
9d34e5db CW |
1892 | |
1893 | if (unlikely (dev_priv->trace_irq_seqno && | |
1894 | i915_seqno_passed(dev_priv->trace_irq_seqno, seqno))) { | |
1ec14ad3 | 1895 | ring->irq_put(ring); |
9d34e5db CW |
1896 | dev_priv->trace_irq_seqno = 0; |
1897 | } | |
23bc5982 CW |
1898 | |
1899 | WARN_ON(i915_verify_lists(dev)); | |
673a394b EA |
1900 | } |
1901 | ||
b09a1fec CW |
1902 | void |
1903 | i915_gem_retire_requests(struct drm_device *dev) | |
1904 | { | |
1905 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1ec14ad3 | 1906 | int i; |
b09a1fec | 1907 | |
be72615b | 1908 | if (!list_empty(&dev_priv->mm.deferred_free_list)) { |
05394f39 | 1909 | struct drm_i915_gem_object *obj, *next; |
be72615b CW |
1910 | |
1911 | /* We must be careful that during unbind() we do not | |
1912 | * accidentally infinitely recurse into retire requests. | |
1913 | * Currently: | |
1914 | * retire -> free -> unbind -> wait -> retire_ring | |
1915 | */ | |
05394f39 | 1916 | list_for_each_entry_safe(obj, next, |
be72615b | 1917 | &dev_priv->mm.deferred_free_list, |
69dc4987 | 1918 | mm_list) |
05394f39 | 1919 | i915_gem_free_object_tail(obj); |
be72615b CW |
1920 | } |
1921 | ||
1ec14ad3 CW |
1922 | for (i = 0; i < I915_NUM_RINGS; i++) |
1923 | i915_gem_retire_requests_ring(dev, &dev_priv->ring[i]); | |
b09a1fec CW |
1924 | } |
1925 | ||
75ef9da2 | 1926 | static void |
673a394b EA |
1927 | i915_gem_retire_work_handler(struct work_struct *work) |
1928 | { | |
1929 | drm_i915_private_t *dev_priv; | |
1930 | struct drm_device *dev; | |
0a58705b CW |
1931 | bool idle; |
1932 | int i; | |
673a394b EA |
1933 | |
1934 | dev_priv = container_of(work, drm_i915_private_t, | |
1935 | mm.retire_work.work); | |
1936 | dev = dev_priv->dev; | |
1937 | ||
891b48cf CW |
1938 | /* Come back later if the device is busy... */ |
1939 | if (!mutex_trylock(&dev->struct_mutex)) { | |
1940 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ); | |
1941 | return; | |
1942 | } | |
1943 | ||
b09a1fec | 1944 | i915_gem_retire_requests(dev); |
d1b851fc | 1945 | |
0a58705b CW |
1946 | /* Send a periodic flush down the ring so we don't hold onto GEM |
1947 | * objects indefinitely. | |
1948 | */ | |
1949 | idle = true; | |
1950 | for (i = 0; i < I915_NUM_RINGS; i++) { | |
1951 | struct intel_ring_buffer *ring = &dev_priv->ring[i]; | |
1952 | ||
1953 | if (!list_empty(&ring->gpu_write_list)) { | |
1954 | struct drm_i915_gem_request *request; | |
1955 | int ret; | |
1956 | ||
1957 | ret = i915_gem_flush_ring(dev, ring, 0, | |
1958 | I915_GEM_GPU_DOMAINS); | |
1959 | request = kzalloc(sizeof(*request), GFP_KERNEL); | |
1960 | if (ret || request == NULL || | |
1961 | i915_add_request(dev, NULL, request, ring)) | |
1962 | kfree(request); | |
1963 | } | |
1964 | ||
1965 | idle &= list_empty(&ring->request_list); | |
1966 | } | |
1967 | ||
1968 | if (!dev_priv->mm.suspended && !idle) | |
9c9fe1f8 | 1969 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ); |
0a58705b | 1970 | |
673a394b EA |
1971 | mutex_unlock(&dev->struct_mutex); |
1972 | } | |
1973 | ||
5a5a0c64 | 1974 | int |
852835f3 | 1975 | i915_do_wait_request(struct drm_device *dev, uint32_t seqno, |
8a1a49f9 | 1976 | bool interruptible, struct intel_ring_buffer *ring) |
673a394b EA |
1977 | { |
1978 | drm_i915_private_t *dev_priv = dev->dev_private; | |
802c7eb6 | 1979 | u32 ier; |
673a394b EA |
1980 | int ret = 0; |
1981 | ||
1982 | BUG_ON(seqno == 0); | |
1983 | ||
ba1234d1 | 1984 | if (atomic_read(&dev_priv->mm.wedged)) |
30dbf0c0 CW |
1985 | return -EAGAIN; |
1986 | ||
5d97eb69 | 1987 | if (seqno == ring->outstanding_lazy_request) { |
3cce469c CW |
1988 | struct drm_i915_gem_request *request; |
1989 | ||
1990 | request = kzalloc(sizeof(*request), GFP_KERNEL); | |
1991 | if (request == NULL) | |
e35a41de | 1992 | return -ENOMEM; |
3cce469c CW |
1993 | |
1994 | ret = i915_add_request(dev, NULL, request, ring); | |
1995 | if (ret) { | |
1996 | kfree(request); | |
1997 | return ret; | |
1998 | } | |
1999 | ||
2000 | seqno = request->seqno; | |
e35a41de | 2001 | } |
ffed1d09 | 2002 | |
78501eac | 2003 | if (!i915_seqno_passed(ring->get_seqno(ring), seqno)) { |
bad720ff | 2004 | if (HAS_PCH_SPLIT(dev)) |
036a4a7d ZW |
2005 | ier = I915_READ(DEIER) | I915_READ(GTIER); |
2006 | else | |
2007 | ier = I915_READ(IER); | |
802c7eb6 JB |
2008 | if (!ier) { |
2009 | DRM_ERROR("something (likely vbetool) disabled " | |
2010 | "interrupts, re-enabling\n"); | |
2011 | i915_driver_irq_preinstall(dev); | |
2012 | i915_driver_irq_postinstall(dev); | |
2013 | } | |
2014 | ||
1c5d22f7 CW |
2015 | trace_i915_gem_request_wait_begin(dev, seqno); |
2016 | ||
b2223497 | 2017 | ring->waiting_seqno = seqno; |
b13c2b96 CW |
2018 | if (ring->irq_get(ring)) { |
2019 | if (interruptible) | |
2020 | ret = wait_event_interruptible(ring->irq_queue, | |
2021 | i915_seqno_passed(ring->get_seqno(ring), seqno) | |
2022 | || atomic_read(&dev_priv->mm.wedged)); | |
2023 | else | |
2024 | wait_event(ring->irq_queue, | |
2025 | i915_seqno_passed(ring->get_seqno(ring), seqno) | |
2026 | || atomic_read(&dev_priv->mm.wedged)); | |
2027 | ||
2028 | ring->irq_put(ring); | |
b5ba177d CW |
2029 | } else if (wait_for(i915_seqno_passed(ring->get_seqno(ring), |
2030 | seqno) || | |
2031 | atomic_read(&dev_priv->mm.wedged), 3000)) | |
2032 | ret = -EBUSY; | |
b2223497 | 2033 | ring->waiting_seqno = 0; |
1c5d22f7 CW |
2034 | |
2035 | trace_i915_gem_request_wait_end(dev, seqno); | |
673a394b | 2036 | } |
ba1234d1 | 2037 | if (atomic_read(&dev_priv->mm.wedged)) |
30dbf0c0 | 2038 | ret = -EAGAIN; |
673a394b EA |
2039 | |
2040 | if (ret && ret != -ERESTARTSYS) | |
8bff917c | 2041 | DRM_ERROR("%s returns %d (awaiting %d at %d, next %d)\n", |
78501eac | 2042 | __func__, ret, seqno, ring->get_seqno(ring), |
8bff917c | 2043 | dev_priv->next_seqno); |
673a394b EA |
2044 | |
2045 | /* Directly dispatch request retiring. While we have the work queue | |
2046 | * to handle this, the waiter on a request often wants an associated | |
2047 | * buffer to have made it to the inactive list, and we would need | |
2048 | * a separate wait queue to handle that. | |
2049 | */ | |
2050 | if (ret == 0) | |
b09a1fec | 2051 | i915_gem_retire_requests_ring(dev, ring); |
673a394b EA |
2052 | |
2053 | return ret; | |
2054 | } | |
2055 | ||
48764bf4 DV |
2056 | /** |
2057 | * Waits for a sequence number to be signaled, and cleans up the | |
2058 | * request and object lists appropriately for that event. | |
2059 | */ | |
2060 | static int | |
852835f3 | 2061 | i915_wait_request(struct drm_device *dev, uint32_t seqno, |
a56ba56c | 2062 | struct intel_ring_buffer *ring) |
48764bf4 | 2063 | { |
852835f3 | 2064 | return i915_do_wait_request(dev, seqno, 1, ring); |
48764bf4 DV |
2065 | } |
2066 | ||
673a394b EA |
2067 | /** |
2068 | * Ensures that all rendering to the object has completed and the object is | |
2069 | * safe to unbind from the GTT or access from the CPU. | |
2070 | */ | |
54cf91dc | 2071 | int |
05394f39 | 2072 | i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj, |
2cf34d7b | 2073 | bool interruptible) |
673a394b | 2074 | { |
05394f39 | 2075 | struct drm_device *dev = obj->base.dev; |
673a394b EA |
2076 | int ret; |
2077 | ||
e47c68e9 EA |
2078 | /* This function only exists to support waiting for existing rendering, |
2079 | * not for emitting required flushes. | |
673a394b | 2080 | */ |
05394f39 | 2081 | BUG_ON((obj->base.write_domain & I915_GEM_GPU_DOMAINS) != 0); |
673a394b EA |
2082 | |
2083 | /* If there is rendering queued on the buffer being evicted, wait for | |
2084 | * it. | |
2085 | */ | |
05394f39 | 2086 | if (obj->active) { |
2cf34d7b | 2087 | ret = i915_do_wait_request(dev, |
05394f39 | 2088 | obj->last_rendering_seqno, |
2cf34d7b | 2089 | interruptible, |
05394f39 | 2090 | obj->ring); |
2cf34d7b | 2091 | if (ret) |
673a394b EA |
2092 | return ret; |
2093 | } | |
2094 | ||
2095 | return 0; | |
2096 | } | |
2097 | ||
2098 | /** | |
2099 | * Unbinds an object from the GTT aperture. | |
2100 | */ | |
0f973f27 | 2101 | int |
05394f39 | 2102 | i915_gem_object_unbind(struct drm_i915_gem_object *obj) |
673a394b | 2103 | { |
673a394b EA |
2104 | int ret = 0; |
2105 | ||
05394f39 | 2106 | if (obj->gtt_space == NULL) |
673a394b EA |
2107 | return 0; |
2108 | ||
05394f39 | 2109 | if (obj->pin_count != 0) { |
673a394b EA |
2110 | DRM_ERROR("Attempting to unbind pinned buffer\n"); |
2111 | return -EINVAL; | |
2112 | } | |
2113 | ||
5323fd04 EA |
2114 | /* blow away mappings if mapped through GTT */ |
2115 | i915_gem_release_mmap(obj); | |
2116 | ||
673a394b EA |
2117 | /* Move the object to the CPU domain to ensure that |
2118 | * any possible CPU writes while it's not in the GTT | |
2119 | * are flushed when we go to remap it. This will | |
2120 | * also ensure that all pending GPU writes are finished | |
2121 | * before we unbind. | |
2122 | */ | |
e47c68e9 | 2123 | ret = i915_gem_object_set_to_cpu_domain(obj, 1); |
8dc1775d | 2124 | if (ret == -ERESTARTSYS) |
673a394b | 2125 | return ret; |
8dc1775d CW |
2126 | /* Continue on if we fail due to EIO, the GPU is hung so we |
2127 | * should be safe and we need to cleanup or else we might | |
2128 | * cause memory corruption through use-after-free. | |
2129 | */ | |
812ed492 CW |
2130 | if (ret) { |
2131 | i915_gem_clflush_object(obj); | |
05394f39 | 2132 | obj->base.read_domains = obj->base.write_domain = I915_GEM_DOMAIN_CPU; |
812ed492 | 2133 | } |
673a394b | 2134 | |
96b47b65 | 2135 | /* release the fence reg _after_ flushing */ |
d9e86c0e CW |
2136 | ret = i915_gem_object_put_fence(obj); |
2137 | if (ret == -ERESTARTSYS) | |
2138 | return ret; | |
96b47b65 | 2139 | |
7c2e6fdf | 2140 | i915_gem_gtt_unbind_object(obj); |
e5281ccd | 2141 | i915_gem_object_put_pages_gtt(obj); |
673a394b | 2142 | |
6299f992 | 2143 | list_del_init(&obj->gtt_list); |
05394f39 | 2144 | list_del_init(&obj->mm_list); |
75e9e915 | 2145 | /* Avoid an unnecessary call to unbind on rebind. */ |
05394f39 | 2146 | obj->map_and_fenceable = true; |
673a394b | 2147 | |
05394f39 CW |
2148 | drm_mm_put_block(obj->gtt_space); |
2149 | obj->gtt_space = NULL; | |
2150 | obj->gtt_offset = 0; | |
673a394b | 2151 | |
05394f39 | 2152 | if (i915_gem_object_is_purgeable(obj)) |
963b4836 CW |
2153 | i915_gem_object_truncate(obj); |
2154 | ||
1c5d22f7 CW |
2155 | trace_i915_gem_object_unbind(obj); |
2156 | ||
8dc1775d | 2157 | return ret; |
673a394b EA |
2158 | } |
2159 | ||
88241785 | 2160 | int |
54cf91dc CW |
2161 | i915_gem_flush_ring(struct drm_device *dev, |
2162 | struct intel_ring_buffer *ring, | |
2163 | uint32_t invalidate_domains, | |
2164 | uint32_t flush_domains) | |
2165 | { | |
88241785 CW |
2166 | int ret; |
2167 | ||
2168 | ret = ring->flush(ring, invalidate_domains, flush_domains); | |
2169 | if (ret) | |
2170 | return ret; | |
2171 | ||
2172 | i915_gem_process_flushing_list(dev, flush_domains, ring); | |
2173 | return 0; | |
54cf91dc CW |
2174 | } |
2175 | ||
a56ba56c CW |
2176 | static int i915_ring_idle(struct drm_device *dev, |
2177 | struct intel_ring_buffer *ring) | |
2178 | { | |
88241785 CW |
2179 | int ret; |
2180 | ||
395b70be | 2181 | if (list_empty(&ring->gpu_write_list) && list_empty(&ring->active_list)) |
64193406 CW |
2182 | return 0; |
2183 | ||
88241785 CW |
2184 | if (!list_empty(&ring->gpu_write_list)) { |
2185 | ret = i915_gem_flush_ring(dev, ring, | |
0ac74c6b | 2186 | I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS); |
88241785 CW |
2187 | if (ret) |
2188 | return ret; | |
2189 | } | |
2190 | ||
a56ba56c CW |
2191 | return i915_wait_request(dev, |
2192 | i915_gem_next_request_seqno(dev, ring), | |
2193 | ring); | |
2194 | } | |
2195 | ||
b47eb4a2 | 2196 | int |
4df2faf4 DV |
2197 | i915_gpu_idle(struct drm_device *dev) |
2198 | { | |
2199 | drm_i915_private_t *dev_priv = dev->dev_private; | |
2200 | bool lists_empty; | |
1ec14ad3 | 2201 | int ret, i; |
4df2faf4 | 2202 | |
d1b851fc | 2203 | lists_empty = (list_empty(&dev_priv->mm.flushing_list) && |
395b70be | 2204 | list_empty(&dev_priv->mm.active_list)); |
4df2faf4 DV |
2205 | if (lists_empty) |
2206 | return 0; | |
2207 | ||
2208 | /* Flush everything onto the inactive list. */ | |
1ec14ad3 CW |
2209 | for (i = 0; i < I915_NUM_RINGS; i++) { |
2210 | ret = i915_ring_idle(dev, &dev_priv->ring[i]); | |
2211 | if (ret) | |
2212 | return ret; | |
2213 | } | |
4df2faf4 | 2214 | |
8a1a49f9 | 2215 | return 0; |
4df2faf4 DV |
2216 | } |
2217 | ||
c6642782 DV |
2218 | static int sandybridge_write_fence_reg(struct drm_i915_gem_object *obj, |
2219 | struct intel_ring_buffer *pipelined) | |
4e901fdc | 2220 | { |
05394f39 | 2221 | struct drm_device *dev = obj->base.dev; |
4e901fdc | 2222 | drm_i915_private_t *dev_priv = dev->dev_private; |
05394f39 CW |
2223 | u32 size = obj->gtt_space->size; |
2224 | int regnum = obj->fence_reg; | |
4e901fdc EA |
2225 | uint64_t val; |
2226 | ||
05394f39 | 2227 | val = (uint64_t)((obj->gtt_offset + size - 4096) & |
c6642782 | 2228 | 0xfffff000) << 32; |
05394f39 CW |
2229 | val |= obj->gtt_offset & 0xfffff000; |
2230 | val |= (uint64_t)((obj->stride / 128) - 1) << | |
4e901fdc EA |
2231 | SANDYBRIDGE_FENCE_PITCH_SHIFT; |
2232 | ||
05394f39 | 2233 | if (obj->tiling_mode == I915_TILING_Y) |
4e901fdc EA |
2234 | val |= 1 << I965_FENCE_TILING_Y_SHIFT; |
2235 | val |= I965_FENCE_REG_VALID; | |
2236 | ||
c6642782 DV |
2237 | if (pipelined) { |
2238 | int ret = intel_ring_begin(pipelined, 6); | |
2239 | if (ret) | |
2240 | return ret; | |
2241 | ||
2242 | intel_ring_emit(pipelined, MI_NOOP); | |
2243 | intel_ring_emit(pipelined, MI_LOAD_REGISTER_IMM(2)); | |
2244 | intel_ring_emit(pipelined, FENCE_REG_SANDYBRIDGE_0 + regnum*8); | |
2245 | intel_ring_emit(pipelined, (u32)val); | |
2246 | intel_ring_emit(pipelined, FENCE_REG_SANDYBRIDGE_0 + regnum*8 + 4); | |
2247 | intel_ring_emit(pipelined, (u32)(val >> 32)); | |
2248 | intel_ring_advance(pipelined); | |
2249 | } else | |
2250 | I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + regnum * 8, val); | |
2251 | ||
2252 | return 0; | |
4e901fdc EA |
2253 | } |
2254 | ||
c6642782 DV |
2255 | static int i965_write_fence_reg(struct drm_i915_gem_object *obj, |
2256 | struct intel_ring_buffer *pipelined) | |
de151cf6 | 2257 | { |
05394f39 | 2258 | struct drm_device *dev = obj->base.dev; |
de151cf6 | 2259 | drm_i915_private_t *dev_priv = dev->dev_private; |
05394f39 CW |
2260 | u32 size = obj->gtt_space->size; |
2261 | int regnum = obj->fence_reg; | |
de151cf6 JB |
2262 | uint64_t val; |
2263 | ||
05394f39 | 2264 | val = (uint64_t)((obj->gtt_offset + size - 4096) & |
de151cf6 | 2265 | 0xfffff000) << 32; |
05394f39 CW |
2266 | val |= obj->gtt_offset & 0xfffff000; |
2267 | val |= ((obj->stride / 128) - 1) << I965_FENCE_PITCH_SHIFT; | |
2268 | if (obj->tiling_mode == I915_TILING_Y) | |
de151cf6 JB |
2269 | val |= 1 << I965_FENCE_TILING_Y_SHIFT; |
2270 | val |= I965_FENCE_REG_VALID; | |
2271 | ||
c6642782 DV |
2272 | if (pipelined) { |
2273 | int ret = intel_ring_begin(pipelined, 6); | |
2274 | if (ret) | |
2275 | return ret; | |
2276 | ||
2277 | intel_ring_emit(pipelined, MI_NOOP); | |
2278 | intel_ring_emit(pipelined, MI_LOAD_REGISTER_IMM(2)); | |
2279 | intel_ring_emit(pipelined, FENCE_REG_965_0 + regnum*8); | |
2280 | intel_ring_emit(pipelined, (u32)val); | |
2281 | intel_ring_emit(pipelined, FENCE_REG_965_0 + regnum*8 + 4); | |
2282 | intel_ring_emit(pipelined, (u32)(val >> 32)); | |
2283 | intel_ring_advance(pipelined); | |
2284 | } else | |
2285 | I915_WRITE64(FENCE_REG_965_0 + regnum * 8, val); | |
2286 | ||
2287 | return 0; | |
de151cf6 JB |
2288 | } |
2289 | ||
c6642782 DV |
2290 | static int i915_write_fence_reg(struct drm_i915_gem_object *obj, |
2291 | struct intel_ring_buffer *pipelined) | |
de151cf6 | 2292 | { |
05394f39 | 2293 | struct drm_device *dev = obj->base.dev; |
de151cf6 | 2294 | drm_i915_private_t *dev_priv = dev->dev_private; |
05394f39 | 2295 | u32 size = obj->gtt_space->size; |
c6642782 | 2296 | u32 fence_reg, val, pitch_val; |
0f973f27 | 2297 | int tile_width; |
de151cf6 | 2298 | |
c6642782 DV |
2299 | if (WARN((obj->gtt_offset & ~I915_FENCE_START_MASK) || |
2300 | (size & -size) != size || | |
2301 | (obj->gtt_offset & (size - 1)), | |
2302 | "object 0x%08x [fenceable? %d] not 1M or pot-size (0x%08x) aligned\n", | |
2303 | obj->gtt_offset, obj->map_and_fenceable, size)) | |
2304 | return -EINVAL; | |
de151cf6 | 2305 | |
c6642782 | 2306 | if (obj->tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev)) |
0f973f27 | 2307 | tile_width = 128; |
de151cf6 | 2308 | else |
0f973f27 JB |
2309 | tile_width = 512; |
2310 | ||
2311 | /* Note: pitch better be a power of two tile widths */ | |
05394f39 | 2312 | pitch_val = obj->stride / tile_width; |
0f973f27 | 2313 | pitch_val = ffs(pitch_val) - 1; |
de151cf6 | 2314 | |
05394f39 CW |
2315 | val = obj->gtt_offset; |
2316 | if (obj->tiling_mode == I915_TILING_Y) | |
de151cf6 | 2317 | val |= 1 << I830_FENCE_TILING_Y_SHIFT; |
a00b10c3 | 2318 | val |= I915_FENCE_SIZE_BITS(size); |
de151cf6 JB |
2319 | val |= pitch_val << I830_FENCE_PITCH_SHIFT; |
2320 | val |= I830_FENCE_REG_VALID; | |
2321 | ||
05394f39 | 2322 | fence_reg = obj->fence_reg; |
a00b10c3 CW |
2323 | if (fence_reg < 8) |
2324 | fence_reg = FENCE_REG_830_0 + fence_reg * 4; | |
dc529a4f | 2325 | else |
a00b10c3 | 2326 | fence_reg = FENCE_REG_945_8 + (fence_reg - 8) * 4; |
c6642782 DV |
2327 | |
2328 | if (pipelined) { | |
2329 | int ret = intel_ring_begin(pipelined, 4); | |
2330 | if (ret) | |
2331 | return ret; | |
2332 | ||
2333 | intel_ring_emit(pipelined, MI_NOOP); | |
2334 | intel_ring_emit(pipelined, MI_LOAD_REGISTER_IMM(1)); | |
2335 | intel_ring_emit(pipelined, fence_reg); | |
2336 | intel_ring_emit(pipelined, val); | |
2337 | intel_ring_advance(pipelined); | |
2338 | } else | |
2339 | I915_WRITE(fence_reg, val); | |
2340 | ||
2341 | return 0; | |
de151cf6 JB |
2342 | } |
2343 | ||
c6642782 DV |
2344 | static int i830_write_fence_reg(struct drm_i915_gem_object *obj, |
2345 | struct intel_ring_buffer *pipelined) | |
de151cf6 | 2346 | { |
05394f39 | 2347 | struct drm_device *dev = obj->base.dev; |
de151cf6 | 2348 | drm_i915_private_t *dev_priv = dev->dev_private; |
05394f39 CW |
2349 | u32 size = obj->gtt_space->size; |
2350 | int regnum = obj->fence_reg; | |
de151cf6 JB |
2351 | uint32_t val; |
2352 | uint32_t pitch_val; | |
2353 | ||
c6642782 DV |
2354 | if (WARN((obj->gtt_offset & ~I830_FENCE_START_MASK) || |
2355 | (size & -size) != size || | |
2356 | (obj->gtt_offset & (size - 1)), | |
2357 | "object 0x%08x not 512K or pot-size 0x%08x aligned\n", | |
2358 | obj->gtt_offset, size)) | |
2359 | return -EINVAL; | |
de151cf6 | 2360 | |
05394f39 | 2361 | pitch_val = obj->stride / 128; |
e76a16de | 2362 | pitch_val = ffs(pitch_val) - 1; |
e76a16de | 2363 | |
05394f39 CW |
2364 | val = obj->gtt_offset; |
2365 | if (obj->tiling_mode == I915_TILING_Y) | |
de151cf6 | 2366 | val |= 1 << I830_FENCE_TILING_Y_SHIFT; |
c6642782 | 2367 | val |= I830_FENCE_SIZE_BITS(size); |
de151cf6 JB |
2368 | val |= pitch_val << I830_FENCE_PITCH_SHIFT; |
2369 | val |= I830_FENCE_REG_VALID; | |
2370 | ||
c6642782 DV |
2371 | if (pipelined) { |
2372 | int ret = intel_ring_begin(pipelined, 4); | |
2373 | if (ret) | |
2374 | return ret; | |
2375 | ||
2376 | intel_ring_emit(pipelined, MI_NOOP); | |
2377 | intel_ring_emit(pipelined, MI_LOAD_REGISTER_IMM(1)); | |
2378 | intel_ring_emit(pipelined, FENCE_REG_830_0 + regnum*4); | |
2379 | intel_ring_emit(pipelined, val); | |
2380 | intel_ring_advance(pipelined); | |
2381 | } else | |
2382 | I915_WRITE(FENCE_REG_830_0 + regnum * 4, val); | |
2383 | ||
2384 | return 0; | |
de151cf6 JB |
2385 | } |
2386 | ||
d9e86c0e CW |
2387 | static bool ring_passed_seqno(struct intel_ring_buffer *ring, u32 seqno) |
2388 | { | |
2389 | return i915_seqno_passed(ring->get_seqno(ring), seqno); | |
2390 | } | |
2391 | ||
2392 | static int | |
2393 | i915_gem_object_flush_fence(struct drm_i915_gem_object *obj, | |
2394 | struct intel_ring_buffer *pipelined, | |
2395 | bool interruptible) | |
2396 | { | |
2397 | int ret; | |
2398 | ||
2399 | if (obj->fenced_gpu_access) { | |
88241785 CW |
2400 | if (obj->base.write_domain & I915_GEM_GPU_DOMAINS) { |
2401 | ret = i915_gem_flush_ring(obj->base.dev, | |
2402 | obj->last_fenced_ring, | |
2403 | 0, obj->base.write_domain); | |
2404 | if (ret) | |
2405 | return ret; | |
2406 | } | |
d9e86c0e CW |
2407 | |
2408 | obj->fenced_gpu_access = false; | |
2409 | } | |
2410 | ||
2411 | if (obj->last_fenced_seqno && pipelined != obj->last_fenced_ring) { | |
2412 | if (!ring_passed_seqno(obj->last_fenced_ring, | |
2413 | obj->last_fenced_seqno)) { | |
2414 | ret = i915_do_wait_request(obj->base.dev, | |
2415 | obj->last_fenced_seqno, | |
2416 | interruptible, | |
2417 | obj->last_fenced_ring); | |
2418 | if (ret) | |
2419 | return ret; | |
2420 | } | |
2421 | ||
2422 | obj->last_fenced_seqno = 0; | |
2423 | obj->last_fenced_ring = NULL; | |
2424 | } | |
2425 | ||
63256ec5 CW |
2426 | /* Ensure that all CPU reads are completed before installing a fence |
2427 | * and all writes before removing the fence. | |
2428 | */ | |
2429 | if (obj->base.read_domains & I915_GEM_DOMAIN_GTT) | |
2430 | mb(); | |
2431 | ||
d9e86c0e CW |
2432 | return 0; |
2433 | } | |
2434 | ||
2435 | int | |
2436 | i915_gem_object_put_fence(struct drm_i915_gem_object *obj) | |
2437 | { | |
2438 | int ret; | |
2439 | ||
2440 | if (obj->tiling_mode) | |
2441 | i915_gem_release_mmap(obj); | |
2442 | ||
2443 | ret = i915_gem_object_flush_fence(obj, NULL, true); | |
2444 | if (ret) | |
2445 | return ret; | |
2446 | ||
2447 | if (obj->fence_reg != I915_FENCE_REG_NONE) { | |
2448 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; | |
2449 | i915_gem_clear_fence_reg(obj->base.dev, | |
2450 | &dev_priv->fence_regs[obj->fence_reg]); | |
2451 | ||
2452 | obj->fence_reg = I915_FENCE_REG_NONE; | |
2453 | } | |
2454 | ||
2455 | return 0; | |
2456 | } | |
2457 | ||
2458 | static struct drm_i915_fence_reg * | |
2459 | i915_find_fence_reg(struct drm_device *dev, | |
2460 | struct intel_ring_buffer *pipelined) | |
ae3db24a | 2461 | { |
ae3db24a | 2462 | struct drm_i915_private *dev_priv = dev->dev_private; |
d9e86c0e CW |
2463 | struct drm_i915_fence_reg *reg, *first, *avail; |
2464 | int i; | |
ae3db24a DV |
2465 | |
2466 | /* First try to find a free reg */ | |
d9e86c0e | 2467 | avail = NULL; |
ae3db24a DV |
2468 | for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) { |
2469 | reg = &dev_priv->fence_regs[i]; | |
2470 | if (!reg->obj) | |
d9e86c0e | 2471 | return reg; |
ae3db24a | 2472 | |
05394f39 | 2473 | if (!reg->obj->pin_count) |
d9e86c0e | 2474 | avail = reg; |
ae3db24a DV |
2475 | } |
2476 | ||
d9e86c0e CW |
2477 | if (avail == NULL) |
2478 | return NULL; | |
ae3db24a DV |
2479 | |
2480 | /* None available, try to steal one or wait for a user to finish */ | |
d9e86c0e CW |
2481 | avail = first = NULL; |
2482 | list_for_each_entry(reg, &dev_priv->mm.fence_list, lru_list) { | |
2483 | if (reg->obj->pin_count) | |
ae3db24a DV |
2484 | continue; |
2485 | ||
d9e86c0e CW |
2486 | if (first == NULL) |
2487 | first = reg; | |
2488 | ||
2489 | if (!pipelined || | |
2490 | !reg->obj->last_fenced_ring || | |
2491 | reg->obj->last_fenced_ring == pipelined) { | |
2492 | avail = reg; | |
2493 | break; | |
2494 | } | |
ae3db24a DV |
2495 | } |
2496 | ||
d9e86c0e CW |
2497 | if (avail == NULL) |
2498 | avail = first; | |
ae3db24a | 2499 | |
a00b10c3 | 2500 | return avail; |
ae3db24a DV |
2501 | } |
2502 | ||
de151cf6 | 2503 | /** |
d9e86c0e | 2504 | * i915_gem_object_get_fence - set up a fence reg for an object |
de151cf6 | 2505 | * @obj: object to map through a fence reg |
d9e86c0e CW |
2506 | * @pipelined: ring on which to queue the change, or NULL for CPU access |
2507 | * @interruptible: must we wait uninterruptibly for the register to retire? | |
de151cf6 JB |
2508 | * |
2509 | * When mapping objects through the GTT, userspace wants to be able to write | |
2510 | * to them without having to worry about swizzling if the object is tiled. | |
2511 | * | |
2512 | * This function walks the fence regs looking for a free one for @obj, | |
2513 | * stealing one if it can't find any. | |
2514 | * | |
2515 | * It then sets up the reg based on the object's properties: address, pitch | |
2516 | * and tiling format. | |
2517 | */ | |
8c4b8c3f | 2518 | int |
d9e86c0e CW |
2519 | i915_gem_object_get_fence(struct drm_i915_gem_object *obj, |
2520 | struct intel_ring_buffer *pipelined, | |
2521 | bool interruptible) | |
de151cf6 | 2522 | { |
05394f39 | 2523 | struct drm_device *dev = obj->base.dev; |
79e53945 | 2524 | struct drm_i915_private *dev_priv = dev->dev_private; |
d9e86c0e | 2525 | struct drm_i915_fence_reg *reg; |
ae3db24a | 2526 | int ret; |
de151cf6 | 2527 | |
6bda10d1 CW |
2528 | /* XXX disable pipelining. There are bugs. Shocking. */ |
2529 | pipelined = NULL; | |
2530 | ||
d9e86c0e | 2531 | /* Just update our place in the LRU if our fence is getting reused. */ |
05394f39 CW |
2532 | if (obj->fence_reg != I915_FENCE_REG_NONE) { |
2533 | reg = &dev_priv->fence_regs[obj->fence_reg]; | |
007cc8ac | 2534 | list_move_tail(®->lru_list, &dev_priv->mm.fence_list); |
d9e86c0e CW |
2535 | |
2536 | if (!obj->fenced_gpu_access && !obj->last_fenced_seqno) | |
2537 | pipelined = NULL; | |
2538 | ||
2539 | if (!pipelined) { | |
2540 | if (reg->setup_seqno) { | |
2541 | if (!ring_passed_seqno(obj->last_fenced_ring, | |
2542 | reg->setup_seqno)) { | |
2543 | ret = i915_do_wait_request(obj->base.dev, | |
2544 | reg->setup_seqno, | |
2545 | interruptible, | |
2546 | obj->last_fenced_ring); | |
2547 | if (ret) | |
2548 | return ret; | |
2549 | } | |
2550 | ||
2551 | reg->setup_seqno = 0; | |
2552 | } | |
2553 | } else if (obj->last_fenced_ring && | |
2554 | obj->last_fenced_ring != pipelined) { | |
2555 | ret = i915_gem_object_flush_fence(obj, | |
2556 | pipelined, | |
2557 | interruptible); | |
2558 | if (ret) | |
2559 | return ret; | |
2560 | } else if (obj->tiling_changed) { | |
2561 | if (obj->fenced_gpu_access) { | |
88241785 CW |
2562 | if (obj->base.write_domain & I915_GEM_GPU_DOMAINS) { |
2563 | ret = i915_gem_flush_ring(obj->base.dev, obj->ring, | |
2564 | 0, obj->base.write_domain); | |
2565 | if (ret) | |
2566 | return ret; | |
2567 | } | |
d9e86c0e CW |
2568 | |
2569 | obj->fenced_gpu_access = false; | |
2570 | } | |
2571 | } | |
2572 | ||
2573 | if (!obj->fenced_gpu_access && !obj->last_fenced_seqno) | |
2574 | pipelined = NULL; | |
2575 | BUG_ON(!pipelined && reg->setup_seqno); | |
2576 | ||
2577 | if (obj->tiling_changed) { | |
2578 | if (pipelined) { | |
2579 | reg->setup_seqno = | |
2580 | i915_gem_next_request_seqno(dev, pipelined); | |
2581 | obj->last_fenced_seqno = reg->setup_seqno; | |
2582 | obj->last_fenced_ring = pipelined; | |
2583 | } | |
2584 | goto update; | |
2585 | } | |
2586 | ||
a09ba7fa EA |
2587 | return 0; |
2588 | } | |
2589 | ||
d9e86c0e CW |
2590 | reg = i915_find_fence_reg(dev, pipelined); |
2591 | if (reg == NULL) | |
2592 | return -ENOSPC; | |
de151cf6 | 2593 | |
d9e86c0e CW |
2594 | ret = i915_gem_object_flush_fence(obj, pipelined, interruptible); |
2595 | if (ret) | |
ae3db24a | 2596 | return ret; |
de151cf6 | 2597 | |
d9e86c0e CW |
2598 | if (reg->obj) { |
2599 | struct drm_i915_gem_object *old = reg->obj; | |
2600 | ||
2601 | drm_gem_object_reference(&old->base); | |
2602 | ||
2603 | if (old->tiling_mode) | |
2604 | i915_gem_release_mmap(old); | |
2605 | ||
d9e86c0e | 2606 | ret = i915_gem_object_flush_fence(old, |
6bda10d1 | 2607 | pipelined, |
d9e86c0e CW |
2608 | interruptible); |
2609 | if (ret) { | |
2610 | drm_gem_object_unreference(&old->base); | |
2611 | return ret; | |
2612 | } | |
2613 | ||
2614 | if (old->last_fenced_seqno == 0 && obj->last_fenced_seqno == 0) | |
2615 | pipelined = NULL; | |
2616 | ||
2617 | old->fence_reg = I915_FENCE_REG_NONE; | |
2618 | old->last_fenced_ring = pipelined; | |
2619 | old->last_fenced_seqno = | |
2620 | pipelined ? i915_gem_next_request_seqno(dev, pipelined) : 0; | |
2621 | ||
2622 | drm_gem_object_unreference(&old->base); | |
2623 | } else if (obj->last_fenced_seqno == 0) | |
2624 | pipelined = NULL; | |
a09ba7fa | 2625 | |
de151cf6 | 2626 | reg->obj = obj; |
d9e86c0e CW |
2627 | list_move_tail(®->lru_list, &dev_priv->mm.fence_list); |
2628 | obj->fence_reg = reg - dev_priv->fence_regs; | |
2629 | obj->last_fenced_ring = pipelined; | |
de151cf6 | 2630 | |
d9e86c0e CW |
2631 | reg->setup_seqno = |
2632 | pipelined ? i915_gem_next_request_seqno(dev, pipelined) : 0; | |
2633 | obj->last_fenced_seqno = reg->setup_seqno; | |
2634 | ||
2635 | update: | |
2636 | obj->tiling_changed = false; | |
e259befd CW |
2637 | switch (INTEL_INFO(dev)->gen) { |
2638 | case 6: | |
c6642782 | 2639 | ret = sandybridge_write_fence_reg(obj, pipelined); |
e259befd CW |
2640 | break; |
2641 | case 5: | |
2642 | case 4: | |
c6642782 | 2643 | ret = i965_write_fence_reg(obj, pipelined); |
e259befd CW |
2644 | break; |
2645 | case 3: | |
c6642782 | 2646 | ret = i915_write_fence_reg(obj, pipelined); |
e259befd CW |
2647 | break; |
2648 | case 2: | |
c6642782 | 2649 | ret = i830_write_fence_reg(obj, pipelined); |
e259befd CW |
2650 | break; |
2651 | } | |
d9ddcb96 | 2652 | |
c6642782 | 2653 | return ret; |
de151cf6 JB |
2654 | } |
2655 | ||
2656 | /** | |
2657 | * i915_gem_clear_fence_reg - clear out fence register info | |
2658 | * @obj: object to clear | |
2659 | * | |
2660 | * Zeroes out the fence register itself and clears out the associated | |
05394f39 | 2661 | * data structures in dev_priv and obj. |
de151cf6 JB |
2662 | */ |
2663 | static void | |
d9e86c0e CW |
2664 | i915_gem_clear_fence_reg(struct drm_device *dev, |
2665 | struct drm_i915_fence_reg *reg) | |
de151cf6 | 2666 | { |
79e53945 | 2667 | drm_i915_private_t *dev_priv = dev->dev_private; |
d9e86c0e | 2668 | uint32_t fence_reg = reg - dev_priv->fence_regs; |
de151cf6 | 2669 | |
e259befd CW |
2670 | switch (INTEL_INFO(dev)->gen) { |
2671 | case 6: | |
d9e86c0e | 2672 | I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + fence_reg*8, 0); |
e259befd CW |
2673 | break; |
2674 | case 5: | |
2675 | case 4: | |
d9e86c0e | 2676 | I915_WRITE64(FENCE_REG_965_0 + fence_reg*8, 0); |
e259befd CW |
2677 | break; |
2678 | case 3: | |
d9e86c0e CW |
2679 | if (fence_reg >= 8) |
2680 | fence_reg = FENCE_REG_945_8 + (fence_reg - 8) * 4; | |
dc529a4f | 2681 | else |
e259befd | 2682 | case 2: |
d9e86c0e | 2683 | fence_reg = FENCE_REG_830_0 + fence_reg * 4; |
dc529a4f EA |
2684 | |
2685 | I915_WRITE(fence_reg, 0); | |
e259befd | 2686 | break; |
dc529a4f | 2687 | } |
de151cf6 | 2688 | |
007cc8ac | 2689 | list_del_init(®->lru_list); |
d9e86c0e CW |
2690 | reg->obj = NULL; |
2691 | reg->setup_seqno = 0; | |
52dc7d32 CW |
2692 | } |
2693 | ||
673a394b EA |
2694 | /** |
2695 | * Finds free space in the GTT aperture and binds the object there. | |
2696 | */ | |
2697 | static int | |
05394f39 | 2698 | i915_gem_object_bind_to_gtt(struct drm_i915_gem_object *obj, |
920afa77 | 2699 | unsigned alignment, |
75e9e915 | 2700 | bool map_and_fenceable) |
673a394b | 2701 | { |
05394f39 | 2702 | struct drm_device *dev = obj->base.dev; |
673a394b | 2703 | drm_i915_private_t *dev_priv = dev->dev_private; |
673a394b | 2704 | struct drm_mm_node *free_space; |
a00b10c3 | 2705 | gfp_t gfpmask = __GFP_NORETRY | __GFP_NOWARN; |
5e783301 | 2706 | u32 size, fence_size, fence_alignment, unfenced_alignment; |
75e9e915 | 2707 | bool mappable, fenceable; |
07f73f69 | 2708 | int ret; |
673a394b | 2709 | |
05394f39 | 2710 | if (obj->madv != I915_MADV_WILLNEED) { |
3ef94daa CW |
2711 | DRM_ERROR("Attempting to bind a purgeable object\n"); |
2712 | return -EINVAL; | |
2713 | } | |
2714 | ||
05394f39 CW |
2715 | fence_size = i915_gem_get_gtt_size(obj); |
2716 | fence_alignment = i915_gem_get_gtt_alignment(obj); | |
2717 | unfenced_alignment = i915_gem_get_unfenced_gtt_alignment(obj); | |
a00b10c3 | 2718 | |
673a394b | 2719 | if (alignment == 0) |
5e783301 DV |
2720 | alignment = map_and_fenceable ? fence_alignment : |
2721 | unfenced_alignment; | |
75e9e915 | 2722 | if (map_and_fenceable && alignment & (fence_alignment - 1)) { |
673a394b EA |
2723 | DRM_ERROR("Invalid object alignment requested %u\n", alignment); |
2724 | return -EINVAL; | |
2725 | } | |
2726 | ||
05394f39 | 2727 | size = map_and_fenceable ? fence_size : obj->base.size; |
a00b10c3 | 2728 | |
654fc607 CW |
2729 | /* If the object is bigger than the entire aperture, reject it early |
2730 | * before evicting everything in a vain attempt to find space. | |
2731 | */ | |
05394f39 | 2732 | if (obj->base.size > |
75e9e915 | 2733 | (map_and_fenceable ? dev_priv->mm.gtt_mappable_end : dev_priv->mm.gtt_total)) { |
654fc607 CW |
2734 | DRM_ERROR("Attempting to bind an object larger than the aperture\n"); |
2735 | return -E2BIG; | |
2736 | } | |
2737 | ||
673a394b | 2738 | search_free: |
75e9e915 | 2739 | if (map_and_fenceable) |
920afa77 DV |
2740 | free_space = |
2741 | drm_mm_search_free_in_range(&dev_priv->mm.gtt_space, | |
a00b10c3 | 2742 | size, alignment, 0, |
920afa77 DV |
2743 | dev_priv->mm.gtt_mappable_end, |
2744 | 0); | |
2745 | else | |
2746 | free_space = drm_mm_search_free(&dev_priv->mm.gtt_space, | |
a00b10c3 | 2747 | size, alignment, 0); |
920afa77 DV |
2748 | |
2749 | if (free_space != NULL) { | |
75e9e915 | 2750 | if (map_and_fenceable) |
05394f39 | 2751 | obj->gtt_space = |
920afa77 | 2752 | drm_mm_get_block_range_generic(free_space, |
a00b10c3 | 2753 | size, alignment, 0, |
920afa77 DV |
2754 | dev_priv->mm.gtt_mappable_end, |
2755 | 0); | |
2756 | else | |
05394f39 | 2757 | obj->gtt_space = |
a00b10c3 | 2758 | drm_mm_get_block(free_space, size, alignment); |
920afa77 | 2759 | } |
05394f39 | 2760 | if (obj->gtt_space == NULL) { |
673a394b EA |
2761 | /* If the gtt is empty and we're still having trouble |
2762 | * fitting our object in, we're out of memory. | |
2763 | */ | |
75e9e915 DV |
2764 | ret = i915_gem_evict_something(dev, size, alignment, |
2765 | map_and_fenceable); | |
9731129c | 2766 | if (ret) |
673a394b | 2767 | return ret; |
9731129c | 2768 | |
673a394b EA |
2769 | goto search_free; |
2770 | } | |
2771 | ||
e5281ccd | 2772 | ret = i915_gem_object_get_pages_gtt(obj, gfpmask); |
673a394b | 2773 | if (ret) { |
05394f39 CW |
2774 | drm_mm_put_block(obj->gtt_space); |
2775 | obj->gtt_space = NULL; | |
07f73f69 CW |
2776 | |
2777 | if (ret == -ENOMEM) { | |
809b6334 CW |
2778 | /* first try to reclaim some memory by clearing the GTT */ |
2779 | ret = i915_gem_evict_everything(dev, false); | |
07f73f69 | 2780 | if (ret) { |
07f73f69 | 2781 | /* now try to shrink everyone else */ |
4bdadb97 CW |
2782 | if (gfpmask) { |
2783 | gfpmask = 0; | |
2784 | goto search_free; | |
07f73f69 CW |
2785 | } |
2786 | ||
809b6334 | 2787 | return -ENOMEM; |
07f73f69 CW |
2788 | } |
2789 | ||
2790 | goto search_free; | |
2791 | } | |
2792 | ||
673a394b EA |
2793 | return ret; |
2794 | } | |
2795 | ||
7c2e6fdf DV |
2796 | ret = i915_gem_gtt_bind_object(obj); |
2797 | if (ret) { | |
e5281ccd | 2798 | i915_gem_object_put_pages_gtt(obj); |
05394f39 CW |
2799 | drm_mm_put_block(obj->gtt_space); |
2800 | obj->gtt_space = NULL; | |
07f73f69 | 2801 | |
809b6334 | 2802 | if (i915_gem_evict_everything(dev, false)) |
07f73f69 | 2803 | return ret; |
07f73f69 CW |
2804 | |
2805 | goto search_free; | |
673a394b | 2806 | } |
673a394b | 2807 | |
6299f992 | 2808 | list_add_tail(&obj->gtt_list, &dev_priv->mm.gtt_list); |
05394f39 | 2809 | list_add_tail(&obj->mm_list, &dev_priv->mm.inactive_list); |
bf1a1092 | 2810 | |
673a394b EA |
2811 | /* Assert that the object is not currently in any GPU domain. As it |
2812 | * wasn't in the GTT, there shouldn't be any way it could have been in | |
2813 | * a GPU cache | |
2814 | */ | |
05394f39 CW |
2815 | BUG_ON(obj->base.read_domains & I915_GEM_GPU_DOMAINS); |
2816 | BUG_ON(obj->base.write_domain & I915_GEM_GPU_DOMAINS); | |
673a394b | 2817 | |
6299f992 | 2818 | obj->gtt_offset = obj->gtt_space->start; |
1c5d22f7 | 2819 | |
75e9e915 | 2820 | fenceable = |
05394f39 CW |
2821 | obj->gtt_space->size == fence_size && |
2822 | (obj->gtt_space->start & (fence_alignment -1)) == 0; | |
a00b10c3 | 2823 | |
75e9e915 | 2824 | mappable = |
05394f39 | 2825 | obj->gtt_offset + obj->base.size <= dev_priv->mm.gtt_mappable_end; |
a00b10c3 | 2826 | |
05394f39 | 2827 | obj->map_and_fenceable = mappable && fenceable; |
75e9e915 | 2828 | |
6299f992 | 2829 | trace_i915_gem_object_bind(obj, obj->gtt_offset, map_and_fenceable); |
673a394b EA |
2830 | return 0; |
2831 | } | |
2832 | ||
2833 | void | |
05394f39 | 2834 | i915_gem_clflush_object(struct drm_i915_gem_object *obj) |
673a394b | 2835 | { |
673a394b EA |
2836 | /* If we don't have a page list set up, then we're not pinned |
2837 | * to GPU, and we can ignore the cache flush because it'll happen | |
2838 | * again at bind time. | |
2839 | */ | |
05394f39 | 2840 | if (obj->pages == NULL) |
673a394b EA |
2841 | return; |
2842 | ||
1c5d22f7 | 2843 | trace_i915_gem_object_clflush(obj); |
cfa16a0d | 2844 | |
05394f39 | 2845 | drm_clflush_pages(obj->pages, obj->base.size / PAGE_SIZE); |
673a394b EA |
2846 | } |
2847 | ||
e47c68e9 | 2848 | /** Flushes any GPU write domain for the object if it's dirty. */ |
88241785 | 2849 | static int |
3619df03 | 2850 | i915_gem_object_flush_gpu_write_domain(struct drm_i915_gem_object *obj) |
e47c68e9 | 2851 | { |
05394f39 | 2852 | struct drm_device *dev = obj->base.dev; |
e47c68e9 | 2853 | |
05394f39 | 2854 | if ((obj->base.write_domain & I915_GEM_GPU_DOMAINS) == 0) |
88241785 | 2855 | return 0; |
e47c68e9 EA |
2856 | |
2857 | /* Queue the GPU write cache flushing we need. */ | |
88241785 | 2858 | return i915_gem_flush_ring(dev, obj->ring, 0, obj->base.write_domain); |
e47c68e9 EA |
2859 | } |
2860 | ||
2861 | /** Flushes the GTT write domain for the object if it's dirty. */ | |
2862 | static void | |
05394f39 | 2863 | i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj) |
e47c68e9 | 2864 | { |
1c5d22f7 CW |
2865 | uint32_t old_write_domain; |
2866 | ||
05394f39 | 2867 | if (obj->base.write_domain != I915_GEM_DOMAIN_GTT) |
e47c68e9 EA |
2868 | return; |
2869 | ||
63256ec5 | 2870 | /* No actual flushing is required for the GTT write domain. Writes |
e47c68e9 EA |
2871 | * to it immediately go to main memory as far as we know, so there's |
2872 | * no chipset flush. It also doesn't land in render cache. | |
63256ec5 CW |
2873 | * |
2874 | * However, we do have to enforce the order so that all writes through | |
2875 | * the GTT land before any writes to the device, such as updates to | |
2876 | * the GATT itself. | |
e47c68e9 | 2877 | */ |
63256ec5 CW |
2878 | wmb(); |
2879 | ||
4a684a41 CW |
2880 | i915_gem_release_mmap(obj); |
2881 | ||
05394f39 CW |
2882 | old_write_domain = obj->base.write_domain; |
2883 | obj->base.write_domain = 0; | |
1c5d22f7 CW |
2884 | |
2885 | trace_i915_gem_object_change_domain(obj, | |
05394f39 | 2886 | obj->base.read_domains, |
1c5d22f7 | 2887 | old_write_domain); |
e47c68e9 EA |
2888 | } |
2889 | ||
2890 | /** Flushes the CPU write domain for the object if it's dirty. */ | |
2891 | static void | |
05394f39 | 2892 | i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj) |
e47c68e9 | 2893 | { |
1c5d22f7 | 2894 | uint32_t old_write_domain; |
e47c68e9 | 2895 | |
05394f39 | 2896 | if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) |
e47c68e9 EA |
2897 | return; |
2898 | ||
2899 | i915_gem_clflush_object(obj); | |
40ce6575 | 2900 | intel_gtt_chipset_flush(); |
05394f39 CW |
2901 | old_write_domain = obj->base.write_domain; |
2902 | obj->base.write_domain = 0; | |
1c5d22f7 CW |
2903 | |
2904 | trace_i915_gem_object_change_domain(obj, | |
05394f39 | 2905 | obj->base.read_domains, |
1c5d22f7 | 2906 | old_write_domain); |
e47c68e9 EA |
2907 | } |
2908 | ||
2ef7eeaa EA |
2909 | /** |
2910 | * Moves a single object to the GTT read, and possibly write domain. | |
2911 | * | |
2912 | * This function returns when the move is complete, including waiting on | |
2913 | * flushes to occur. | |
2914 | */ | |
79e53945 | 2915 | int |
2021746e | 2916 | i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write) |
2ef7eeaa | 2917 | { |
1c5d22f7 | 2918 | uint32_t old_write_domain, old_read_domains; |
e47c68e9 | 2919 | int ret; |
2ef7eeaa | 2920 | |
02354392 | 2921 | /* Not valid to be called on unbound objects. */ |
05394f39 | 2922 | if (obj->gtt_space == NULL) |
02354392 EA |
2923 | return -EINVAL; |
2924 | ||
88241785 CW |
2925 | ret = i915_gem_object_flush_gpu_write_domain(obj); |
2926 | if (ret) | |
2927 | return ret; | |
2928 | ||
87ca9c8a CW |
2929 | if (obj->pending_gpu_write || write) { |
2930 | ret = i915_gem_object_wait_rendering(obj, true); | |
2931 | if (ret) | |
2932 | return ret; | |
2933 | } | |
2dafb1e0 | 2934 | |
7213342d | 2935 | i915_gem_object_flush_cpu_write_domain(obj); |
1c5d22f7 | 2936 | |
05394f39 CW |
2937 | old_write_domain = obj->base.write_domain; |
2938 | old_read_domains = obj->base.read_domains; | |
1c5d22f7 | 2939 | |
e47c68e9 EA |
2940 | /* It should now be out of any other write domains, and we can update |
2941 | * the domain values for our changes. | |
2942 | */ | |
05394f39 CW |
2943 | BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) != 0); |
2944 | obj->base.read_domains |= I915_GEM_DOMAIN_GTT; | |
e47c68e9 | 2945 | if (write) { |
05394f39 CW |
2946 | obj->base.read_domains = I915_GEM_DOMAIN_GTT; |
2947 | obj->base.write_domain = I915_GEM_DOMAIN_GTT; | |
2948 | obj->dirty = 1; | |
2ef7eeaa EA |
2949 | } |
2950 | ||
1c5d22f7 CW |
2951 | trace_i915_gem_object_change_domain(obj, |
2952 | old_read_domains, | |
2953 | old_write_domain); | |
2954 | ||
e47c68e9 EA |
2955 | return 0; |
2956 | } | |
2957 | ||
b9241ea3 ZW |
2958 | /* |
2959 | * Prepare buffer for display plane. Use uninterruptible for possible flush | |
2960 | * wait, as in modesetting process we're not supposed to be interrupted. | |
2961 | */ | |
2962 | int | |
05394f39 | 2963 | i915_gem_object_set_to_display_plane(struct drm_i915_gem_object *obj, |
919926ae | 2964 | struct intel_ring_buffer *pipelined) |
b9241ea3 | 2965 | { |
ba3d8d74 | 2966 | uint32_t old_read_domains; |
b9241ea3 ZW |
2967 | int ret; |
2968 | ||
2969 | /* Not valid to be called on unbound objects. */ | |
05394f39 | 2970 | if (obj->gtt_space == NULL) |
b9241ea3 ZW |
2971 | return -EINVAL; |
2972 | ||
88241785 CW |
2973 | ret = i915_gem_object_flush_gpu_write_domain(obj); |
2974 | if (ret) | |
2975 | return ret; | |
2976 | ||
b9241ea3 | 2977 | |
ced270fa | 2978 | /* Currently, we are always called from an non-interruptible context. */ |
0be73284 | 2979 | if (pipelined != obj->ring) { |
ced270fa CW |
2980 | ret = i915_gem_object_wait_rendering(obj, false); |
2981 | if (ret) | |
b9241ea3 ZW |
2982 | return ret; |
2983 | } | |
2984 | ||
b118c1e3 CW |
2985 | i915_gem_object_flush_cpu_write_domain(obj); |
2986 | ||
05394f39 CW |
2987 | old_read_domains = obj->base.read_domains; |
2988 | obj->base.read_domains |= I915_GEM_DOMAIN_GTT; | |
b9241ea3 ZW |
2989 | |
2990 | trace_i915_gem_object_change_domain(obj, | |
2991 | old_read_domains, | |
05394f39 | 2992 | obj->base.write_domain); |
b9241ea3 ZW |
2993 | |
2994 | return 0; | |
2995 | } | |
2996 | ||
85345517 CW |
2997 | int |
2998 | i915_gem_object_flush_gpu(struct drm_i915_gem_object *obj, | |
2999 | bool interruptible) | |
3000 | { | |
88241785 CW |
3001 | int ret; |
3002 | ||
85345517 CW |
3003 | if (!obj->active) |
3004 | return 0; | |
3005 | ||
88241785 CW |
3006 | if (obj->base.write_domain & I915_GEM_GPU_DOMAINS) { |
3007 | ret = i915_gem_flush_ring(obj->base.dev, obj->ring, | |
3008 | 0, obj->base.write_domain); | |
3009 | if (ret) | |
3010 | return ret; | |
3011 | } | |
85345517 | 3012 | |
05394f39 | 3013 | return i915_gem_object_wait_rendering(obj, interruptible); |
85345517 CW |
3014 | } |
3015 | ||
e47c68e9 EA |
3016 | /** |
3017 | * Moves a single object to the CPU read, and possibly write domain. | |
3018 | * | |
3019 | * This function returns when the move is complete, including waiting on | |
3020 | * flushes to occur. | |
3021 | */ | |
3022 | static int | |
919926ae | 3023 | i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write) |
e47c68e9 | 3024 | { |
1c5d22f7 | 3025 | uint32_t old_write_domain, old_read_domains; |
e47c68e9 EA |
3026 | int ret; |
3027 | ||
88241785 CW |
3028 | ret = i915_gem_object_flush_gpu_write_domain(obj); |
3029 | if (ret) | |
3030 | return ret; | |
3031 | ||
de18a29e DV |
3032 | ret = i915_gem_object_wait_rendering(obj, true); |
3033 | if (ret) | |
e47c68e9 | 3034 | return ret; |
2ef7eeaa | 3035 | |
e47c68e9 | 3036 | i915_gem_object_flush_gtt_write_domain(obj); |
2ef7eeaa | 3037 | |
e47c68e9 EA |
3038 | /* If we have a partially-valid cache of the object in the CPU, |
3039 | * finish invalidating it and free the per-page flags. | |
2ef7eeaa | 3040 | */ |
e47c68e9 | 3041 | i915_gem_object_set_to_full_cpu_read_domain(obj); |
2ef7eeaa | 3042 | |
05394f39 CW |
3043 | old_write_domain = obj->base.write_domain; |
3044 | old_read_domains = obj->base.read_domains; | |
1c5d22f7 | 3045 | |
e47c68e9 | 3046 | /* Flush the CPU cache if it's still invalid. */ |
05394f39 | 3047 | if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) { |
2ef7eeaa | 3048 | i915_gem_clflush_object(obj); |
2ef7eeaa | 3049 | |
05394f39 | 3050 | obj->base.read_domains |= I915_GEM_DOMAIN_CPU; |
2ef7eeaa EA |
3051 | } |
3052 | ||
3053 | /* It should now be out of any other write domains, and we can update | |
3054 | * the domain values for our changes. | |
3055 | */ | |
05394f39 | 3056 | BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) != 0); |
e47c68e9 EA |
3057 | |
3058 | /* If we're writing through the CPU, then the GPU read domains will | |
3059 | * need to be invalidated at next use. | |
3060 | */ | |
3061 | if (write) { | |
05394f39 CW |
3062 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; |
3063 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; | |
e47c68e9 | 3064 | } |
2ef7eeaa | 3065 | |
1c5d22f7 CW |
3066 | trace_i915_gem_object_change_domain(obj, |
3067 | old_read_domains, | |
3068 | old_write_domain); | |
3069 | ||
2ef7eeaa EA |
3070 | return 0; |
3071 | } | |
3072 | ||
673a394b | 3073 | /** |
e47c68e9 | 3074 | * Moves the object from a partially CPU read to a full one. |
673a394b | 3075 | * |
e47c68e9 EA |
3076 | * Note that this only resolves i915_gem_object_set_cpu_read_domain_range(), |
3077 | * and doesn't handle transitioning from !(read_domains & I915_GEM_DOMAIN_CPU). | |
673a394b | 3078 | */ |
e47c68e9 | 3079 | static void |
05394f39 | 3080 | i915_gem_object_set_to_full_cpu_read_domain(struct drm_i915_gem_object *obj) |
673a394b | 3081 | { |
05394f39 | 3082 | if (!obj->page_cpu_valid) |
e47c68e9 EA |
3083 | return; |
3084 | ||
3085 | /* If we're partially in the CPU read domain, finish moving it in. | |
3086 | */ | |
05394f39 | 3087 | if (obj->base.read_domains & I915_GEM_DOMAIN_CPU) { |
e47c68e9 EA |
3088 | int i; |
3089 | ||
05394f39 CW |
3090 | for (i = 0; i <= (obj->base.size - 1) / PAGE_SIZE; i++) { |
3091 | if (obj->page_cpu_valid[i]) | |
e47c68e9 | 3092 | continue; |
05394f39 | 3093 | drm_clflush_pages(obj->pages + i, 1); |
e47c68e9 | 3094 | } |
e47c68e9 EA |
3095 | } |
3096 | ||
3097 | /* Free the page_cpu_valid mappings which are now stale, whether | |
3098 | * or not we've got I915_GEM_DOMAIN_CPU. | |
3099 | */ | |
05394f39 CW |
3100 | kfree(obj->page_cpu_valid); |
3101 | obj->page_cpu_valid = NULL; | |
e47c68e9 EA |
3102 | } |
3103 | ||
3104 | /** | |
3105 | * Set the CPU read domain on a range of the object. | |
3106 | * | |
3107 | * The object ends up with I915_GEM_DOMAIN_CPU in its read flags although it's | |
3108 | * not entirely valid. The page_cpu_valid member of the object flags which | |
3109 | * pages have been flushed, and will be respected by | |
3110 | * i915_gem_object_set_to_cpu_domain() if it's called on to get a valid mapping | |
3111 | * of the whole object. | |
3112 | * | |
3113 | * This function returns when the move is complete, including waiting on | |
3114 | * flushes to occur. | |
3115 | */ | |
3116 | static int | |
05394f39 | 3117 | i915_gem_object_set_cpu_read_domain_range(struct drm_i915_gem_object *obj, |
e47c68e9 EA |
3118 | uint64_t offset, uint64_t size) |
3119 | { | |
1c5d22f7 | 3120 | uint32_t old_read_domains; |
e47c68e9 | 3121 | int i, ret; |
673a394b | 3122 | |
05394f39 | 3123 | if (offset == 0 && size == obj->base.size) |
e47c68e9 | 3124 | return i915_gem_object_set_to_cpu_domain(obj, 0); |
673a394b | 3125 | |
88241785 CW |
3126 | ret = i915_gem_object_flush_gpu_write_domain(obj); |
3127 | if (ret) | |
3128 | return ret; | |
3129 | ||
de18a29e DV |
3130 | ret = i915_gem_object_wait_rendering(obj, true); |
3131 | if (ret) | |
6a47baa6 | 3132 | return ret; |
de18a29e | 3133 | |
e47c68e9 EA |
3134 | i915_gem_object_flush_gtt_write_domain(obj); |
3135 | ||
3136 | /* If we're already fully in the CPU read domain, we're done. */ | |
05394f39 CW |
3137 | if (obj->page_cpu_valid == NULL && |
3138 | (obj->base.read_domains & I915_GEM_DOMAIN_CPU) != 0) | |
e47c68e9 | 3139 | return 0; |
673a394b | 3140 | |
e47c68e9 EA |
3141 | /* Otherwise, create/clear the per-page CPU read domain flag if we're |
3142 | * newly adding I915_GEM_DOMAIN_CPU | |
3143 | */ | |
05394f39 CW |
3144 | if (obj->page_cpu_valid == NULL) { |
3145 | obj->page_cpu_valid = kzalloc(obj->base.size / PAGE_SIZE, | |
3146 | GFP_KERNEL); | |
3147 | if (obj->page_cpu_valid == NULL) | |
e47c68e9 | 3148 | return -ENOMEM; |
05394f39 CW |
3149 | } else if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) |
3150 | memset(obj->page_cpu_valid, 0, obj->base.size / PAGE_SIZE); | |
673a394b EA |
3151 | |
3152 | /* Flush the cache on any pages that are still invalid from the CPU's | |
3153 | * perspective. | |
3154 | */ | |
e47c68e9 EA |
3155 | for (i = offset / PAGE_SIZE; i <= (offset + size - 1) / PAGE_SIZE; |
3156 | i++) { | |
05394f39 | 3157 | if (obj->page_cpu_valid[i]) |
673a394b EA |
3158 | continue; |
3159 | ||
05394f39 | 3160 | drm_clflush_pages(obj->pages + i, 1); |
673a394b | 3161 | |
05394f39 | 3162 | obj->page_cpu_valid[i] = 1; |
673a394b EA |
3163 | } |
3164 | ||
e47c68e9 EA |
3165 | /* It should now be out of any other write domains, and we can update |
3166 | * the domain values for our changes. | |
3167 | */ | |
05394f39 | 3168 | BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) != 0); |
e47c68e9 | 3169 | |
05394f39 CW |
3170 | old_read_domains = obj->base.read_domains; |
3171 | obj->base.read_domains |= I915_GEM_DOMAIN_CPU; | |
e47c68e9 | 3172 | |
1c5d22f7 CW |
3173 | trace_i915_gem_object_change_domain(obj, |
3174 | old_read_domains, | |
05394f39 | 3175 | obj->base.write_domain); |
1c5d22f7 | 3176 | |
673a394b EA |
3177 | return 0; |
3178 | } | |
3179 | ||
673a394b EA |
3180 | /* Throttle our rendering by waiting until the ring has completed our requests |
3181 | * emitted over 20 msec ago. | |
3182 | * | |
b962442e EA |
3183 | * Note that if we were to use the current jiffies each time around the loop, |
3184 | * we wouldn't escape the function with any frames outstanding if the time to | |
3185 | * render a frame was over 20ms. | |
3186 | * | |
673a394b EA |
3187 | * This should get us reasonable parallelism between CPU and GPU but also |
3188 | * relatively low latency when blocking on a particular request to finish. | |
3189 | */ | |
40a5f0de | 3190 | static int |
f787a5f5 | 3191 | i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file) |
40a5f0de | 3192 | { |
f787a5f5 CW |
3193 | struct drm_i915_private *dev_priv = dev->dev_private; |
3194 | struct drm_i915_file_private *file_priv = file->driver_priv; | |
b962442e | 3195 | unsigned long recent_enough = jiffies - msecs_to_jiffies(20); |
f787a5f5 CW |
3196 | struct drm_i915_gem_request *request; |
3197 | struct intel_ring_buffer *ring = NULL; | |
3198 | u32 seqno = 0; | |
3199 | int ret; | |
93533c29 | 3200 | |
e110e8d6 CW |
3201 | if (atomic_read(&dev_priv->mm.wedged)) |
3202 | return -EIO; | |
3203 | ||
1c25595f | 3204 | spin_lock(&file_priv->mm.lock); |
f787a5f5 | 3205 | list_for_each_entry(request, &file_priv->mm.request_list, client_list) { |
b962442e EA |
3206 | if (time_after_eq(request->emitted_jiffies, recent_enough)) |
3207 | break; | |
40a5f0de | 3208 | |
f787a5f5 CW |
3209 | ring = request->ring; |
3210 | seqno = request->seqno; | |
b962442e | 3211 | } |
1c25595f | 3212 | spin_unlock(&file_priv->mm.lock); |
40a5f0de | 3213 | |
f787a5f5 CW |
3214 | if (seqno == 0) |
3215 | return 0; | |
2bc43b5c | 3216 | |
f787a5f5 | 3217 | ret = 0; |
78501eac | 3218 | if (!i915_seqno_passed(ring->get_seqno(ring), seqno)) { |
f787a5f5 CW |
3219 | /* And wait for the seqno passing without holding any locks and |
3220 | * causing extra latency for others. This is safe as the irq | |
3221 | * generation is designed to be run atomically and so is | |
3222 | * lockless. | |
3223 | */ | |
b13c2b96 CW |
3224 | if (ring->irq_get(ring)) { |
3225 | ret = wait_event_interruptible(ring->irq_queue, | |
3226 | i915_seqno_passed(ring->get_seqno(ring), seqno) | |
3227 | || atomic_read(&dev_priv->mm.wedged)); | |
3228 | ring->irq_put(ring); | |
40a5f0de | 3229 | |
b13c2b96 CW |
3230 | if (ret == 0 && atomic_read(&dev_priv->mm.wedged)) |
3231 | ret = -EIO; | |
3232 | } | |
40a5f0de EA |
3233 | } |
3234 | ||
f787a5f5 CW |
3235 | if (ret == 0) |
3236 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, 0); | |
40a5f0de EA |
3237 | |
3238 | return ret; | |
3239 | } | |
3240 | ||
673a394b | 3241 | int |
05394f39 CW |
3242 | i915_gem_object_pin(struct drm_i915_gem_object *obj, |
3243 | uint32_t alignment, | |
75e9e915 | 3244 | bool map_and_fenceable) |
673a394b | 3245 | { |
05394f39 | 3246 | struct drm_device *dev = obj->base.dev; |
f13d3f73 | 3247 | struct drm_i915_private *dev_priv = dev->dev_private; |
673a394b EA |
3248 | int ret; |
3249 | ||
05394f39 | 3250 | BUG_ON(obj->pin_count == DRM_I915_GEM_OBJECT_MAX_PIN_COUNT); |
23bc5982 | 3251 | WARN_ON(i915_verify_lists(dev)); |
ac0c6b5a | 3252 | |
05394f39 CW |
3253 | if (obj->gtt_space != NULL) { |
3254 | if ((alignment && obj->gtt_offset & (alignment - 1)) || | |
3255 | (map_and_fenceable && !obj->map_and_fenceable)) { | |
3256 | WARN(obj->pin_count, | |
ae7d49d8 | 3257 | "bo is already pinned with incorrect alignment:" |
75e9e915 DV |
3258 | " offset=%x, req.alignment=%x, req.map_and_fenceable=%d," |
3259 | " obj->map_and_fenceable=%d\n", | |
05394f39 | 3260 | obj->gtt_offset, alignment, |
75e9e915 | 3261 | map_and_fenceable, |
05394f39 | 3262 | obj->map_and_fenceable); |
ac0c6b5a CW |
3263 | ret = i915_gem_object_unbind(obj); |
3264 | if (ret) | |
3265 | return ret; | |
3266 | } | |
3267 | } | |
3268 | ||
05394f39 | 3269 | if (obj->gtt_space == NULL) { |
a00b10c3 | 3270 | ret = i915_gem_object_bind_to_gtt(obj, alignment, |
75e9e915 | 3271 | map_and_fenceable); |
9731129c | 3272 | if (ret) |
673a394b | 3273 | return ret; |
22c344e9 | 3274 | } |
76446cac | 3275 | |
05394f39 | 3276 | if (obj->pin_count++ == 0) { |
05394f39 CW |
3277 | if (!obj->active) |
3278 | list_move_tail(&obj->mm_list, | |
f13d3f73 | 3279 | &dev_priv->mm.pinned_list); |
673a394b | 3280 | } |
6299f992 | 3281 | obj->pin_mappable |= map_and_fenceable; |
673a394b | 3282 | |
23bc5982 | 3283 | WARN_ON(i915_verify_lists(dev)); |
673a394b EA |
3284 | return 0; |
3285 | } | |
3286 | ||
3287 | void | |
05394f39 | 3288 | i915_gem_object_unpin(struct drm_i915_gem_object *obj) |
673a394b | 3289 | { |
05394f39 | 3290 | struct drm_device *dev = obj->base.dev; |
673a394b | 3291 | drm_i915_private_t *dev_priv = dev->dev_private; |
673a394b | 3292 | |
23bc5982 | 3293 | WARN_ON(i915_verify_lists(dev)); |
05394f39 CW |
3294 | BUG_ON(obj->pin_count == 0); |
3295 | BUG_ON(obj->gtt_space == NULL); | |
673a394b | 3296 | |
05394f39 CW |
3297 | if (--obj->pin_count == 0) { |
3298 | if (!obj->active) | |
3299 | list_move_tail(&obj->mm_list, | |
673a394b | 3300 | &dev_priv->mm.inactive_list); |
6299f992 | 3301 | obj->pin_mappable = false; |
673a394b | 3302 | } |
23bc5982 | 3303 | WARN_ON(i915_verify_lists(dev)); |
673a394b EA |
3304 | } |
3305 | ||
3306 | int | |
3307 | i915_gem_pin_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 3308 | struct drm_file *file) |
673a394b EA |
3309 | { |
3310 | struct drm_i915_gem_pin *args = data; | |
05394f39 | 3311 | struct drm_i915_gem_object *obj; |
673a394b EA |
3312 | int ret; |
3313 | ||
1d7cfea1 CW |
3314 | ret = i915_mutex_lock_interruptible(dev); |
3315 | if (ret) | |
3316 | return ret; | |
673a394b | 3317 | |
05394f39 | 3318 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
673a394b | 3319 | if (obj == NULL) { |
1d7cfea1 CW |
3320 | ret = -ENOENT; |
3321 | goto unlock; | |
673a394b | 3322 | } |
673a394b | 3323 | |
05394f39 | 3324 | if (obj->madv != I915_MADV_WILLNEED) { |
bb6baf76 | 3325 | DRM_ERROR("Attempting to pin a purgeable buffer\n"); |
1d7cfea1 CW |
3326 | ret = -EINVAL; |
3327 | goto out; | |
3ef94daa CW |
3328 | } |
3329 | ||
05394f39 | 3330 | if (obj->pin_filp != NULL && obj->pin_filp != file) { |
79e53945 JB |
3331 | DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n", |
3332 | args->handle); | |
1d7cfea1 CW |
3333 | ret = -EINVAL; |
3334 | goto out; | |
79e53945 JB |
3335 | } |
3336 | ||
05394f39 CW |
3337 | obj->user_pin_count++; |
3338 | obj->pin_filp = file; | |
3339 | if (obj->user_pin_count == 1) { | |
75e9e915 | 3340 | ret = i915_gem_object_pin(obj, args->alignment, true); |
1d7cfea1 CW |
3341 | if (ret) |
3342 | goto out; | |
673a394b EA |
3343 | } |
3344 | ||
3345 | /* XXX - flush the CPU caches for pinned objects | |
3346 | * as the X server doesn't manage domains yet | |
3347 | */ | |
e47c68e9 | 3348 | i915_gem_object_flush_cpu_write_domain(obj); |
05394f39 | 3349 | args->offset = obj->gtt_offset; |
1d7cfea1 | 3350 | out: |
05394f39 | 3351 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 3352 | unlock: |
673a394b | 3353 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 3354 | return ret; |
673a394b EA |
3355 | } |
3356 | ||
3357 | int | |
3358 | i915_gem_unpin_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 3359 | struct drm_file *file) |
673a394b EA |
3360 | { |
3361 | struct drm_i915_gem_pin *args = data; | |
05394f39 | 3362 | struct drm_i915_gem_object *obj; |
76c1dec1 | 3363 | int ret; |
673a394b | 3364 | |
1d7cfea1 CW |
3365 | ret = i915_mutex_lock_interruptible(dev); |
3366 | if (ret) | |
3367 | return ret; | |
673a394b | 3368 | |
05394f39 | 3369 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
673a394b | 3370 | if (obj == NULL) { |
1d7cfea1 CW |
3371 | ret = -ENOENT; |
3372 | goto unlock; | |
673a394b | 3373 | } |
76c1dec1 | 3374 | |
05394f39 | 3375 | if (obj->pin_filp != file) { |
79e53945 JB |
3376 | DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n", |
3377 | args->handle); | |
1d7cfea1 CW |
3378 | ret = -EINVAL; |
3379 | goto out; | |
79e53945 | 3380 | } |
05394f39 CW |
3381 | obj->user_pin_count--; |
3382 | if (obj->user_pin_count == 0) { | |
3383 | obj->pin_filp = NULL; | |
79e53945 JB |
3384 | i915_gem_object_unpin(obj); |
3385 | } | |
673a394b | 3386 | |
1d7cfea1 | 3387 | out: |
05394f39 | 3388 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 3389 | unlock: |
673a394b | 3390 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 3391 | return ret; |
673a394b EA |
3392 | } |
3393 | ||
3394 | int | |
3395 | i915_gem_busy_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 3396 | struct drm_file *file) |
673a394b EA |
3397 | { |
3398 | struct drm_i915_gem_busy *args = data; | |
05394f39 | 3399 | struct drm_i915_gem_object *obj; |
30dbf0c0 CW |
3400 | int ret; |
3401 | ||
76c1dec1 | 3402 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 3403 | if (ret) |
76c1dec1 | 3404 | return ret; |
673a394b | 3405 | |
05394f39 | 3406 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
673a394b | 3407 | if (obj == NULL) { |
1d7cfea1 CW |
3408 | ret = -ENOENT; |
3409 | goto unlock; | |
673a394b | 3410 | } |
d1b851fc | 3411 | |
0be555b6 CW |
3412 | /* Count all active objects as busy, even if they are currently not used |
3413 | * by the gpu. Users of this interface expect objects to eventually | |
3414 | * become non-busy without any further actions, therefore emit any | |
3415 | * necessary flushes here. | |
c4de0a5d | 3416 | */ |
05394f39 | 3417 | args->busy = obj->active; |
0be555b6 CW |
3418 | if (args->busy) { |
3419 | /* Unconditionally flush objects, even when the gpu still uses this | |
3420 | * object. Userspace calling this function indicates that it wants to | |
3421 | * use this buffer rather sooner than later, so issuing the required | |
3422 | * flush earlier is beneficial. | |
3423 | */ | |
1a1c6976 | 3424 | if (obj->base.write_domain & I915_GEM_GPU_DOMAINS) { |
88241785 CW |
3425 | ret = i915_gem_flush_ring(dev, obj->ring, |
3426 | 0, obj->base.write_domain); | |
1a1c6976 CW |
3427 | } else if (obj->ring->outstanding_lazy_request == |
3428 | obj->last_rendering_seqno) { | |
3429 | struct drm_i915_gem_request *request; | |
3430 | ||
7a194876 CW |
3431 | /* This ring is not being cleared by active usage, |
3432 | * so emit a request to do so. | |
3433 | */ | |
1a1c6976 CW |
3434 | request = kzalloc(sizeof(*request), GFP_KERNEL); |
3435 | if (request) | |
3436 | ret = i915_add_request(dev, | |
3437 | NULL, request, | |
3438 | obj->ring); | |
3439 | else | |
7a194876 CW |
3440 | ret = -ENOMEM; |
3441 | } | |
0be555b6 CW |
3442 | |
3443 | /* Update the active list for the hardware's current position. | |
3444 | * Otherwise this only updates on a delayed timer or when irqs | |
3445 | * are actually unmasked, and our working set ends up being | |
3446 | * larger than required. | |
3447 | */ | |
05394f39 | 3448 | i915_gem_retire_requests_ring(dev, obj->ring); |
0be555b6 | 3449 | |
05394f39 | 3450 | args->busy = obj->active; |
0be555b6 | 3451 | } |
673a394b | 3452 | |
05394f39 | 3453 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 3454 | unlock: |
673a394b | 3455 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 3456 | return ret; |
673a394b EA |
3457 | } |
3458 | ||
3459 | int | |
3460 | i915_gem_throttle_ioctl(struct drm_device *dev, void *data, | |
3461 | struct drm_file *file_priv) | |
3462 | { | |
3463 | return i915_gem_ring_throttle(dev, file_priv); | |
3464 | } | |
3465 | ||
3ef94daa CW |
3466 | int |
3467 | i915_gem_madvise_ioctl(struct drm_device *dev, void *data, | |
3468 | struct drm_file *file_priv) | |
3469 | { | |
3470 | struct drm_i915_gem_madvise *args = data; | |
05394f39 | 3471 | struct drm_i915_gem_object *obj; |
76c1dec1 | 3472 | int ret; |
3ef94daa CW |
3473 | |
3474 | switch (args->madv) { | |
3475 | case I915_MADV_DONTNEED: | |
3476 | case I915_MADV_WILLNEED: | |
3477 | break; | |
3478 | default: | |
3479 | return -EINVAL; | |
3480 | } | |
3481 | ||
1d7cfea1 CW |
3482 | ret = i915_mutex_lock_interruptible(dev); |
3483 | if (ret) | |
3484 | return ret; | |
3485 | ||
05394f39 | 3486 | obj = to_intel_bo(drm_gem_object_lookup(dev, file_priv, args->handle)); |
3ef94daa | 3487 | if (obj == NULL) { |
1d7cfea1 CW |
3488 | ret = -ENOENT; |
3489 | goto unlock; | |
3ef94daa | 3490 | } |
3ef94daa | 3491 | |
05394f39 | 3492 | if (obj->pin_count) { |
1d7cfea1 CW |
3493 | ret = -EINVAL; |
3494 | goto out; | |
3ef94daa CW |
3495 | } |
3496 | ||
05394f39 CW |
3497 | if (obj->madv != __I915_MADV_PURGED) |
3498 | obj->madv = args->madv; | |
3ef94daa | 3499 | |
2d7ef395 | 3500 | /* if the object is no longer bound, discard its backing storage */ |
05394f39 CW |
3501 | if (i915_gem_object_is_purgeable(obj) && |
3502 | obj->gtt_space == NULL) | |
2d7ef395 CW |
3503 | i915_gem_object_truncate(obj); |
3504 | ||
05394f39 | 3505 | args->retained = obj->madv != __I915_MADV_PURGED; |
bb6baf76 | 3506 | |
1d7cfea1 | 3507 | out: |
05394f39 | 3508 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 3509 | unlock: |
3ef94daa | 3510 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 3511 | return ret; |
3ef94daa CW |
3512 | } |
3513 | ||
05394f39 CW |
3514 | struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev, |
3515 | size_t size) | |
ac52bc56 | 3516 | { |
73aa808f | 3517 | struct drm_i915_private *dev_priv = dev->dev_private; |
c397b908 | 3518 | struct drm_i915_gem_object *obj; |
ac52bc56 | 3519 | |
c397b908 DV |
3520 | obj = kzalloc(sizeof(*obj), GFP_KERNEL); |
3521 | if (obj == NULL) | |
3522 | return NULL; | |
673a394b | 3523 | |
c397b908 DV |
3524 | if (drm_gem_object_init(dev, &obj->base, size) != 0) { |
3525 | kfree(obj); | |
3526 | return NULL; | |
3527 | } | |
673a394b | 3528 | |
73aa808f CW |
3529 | i915_gem_info_add_obj(dev_priv, size); |
3530 | ||
c397b908 DV |
3531 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; |
3532 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; | |
673a394b | 3533 | |
c397b908 | 3534 | obj->agp_type = AGP_USER_MEMORY; |
62b8b215 | 3535 | obj->base.driver_private = NULL; |
c397b908 | 3536 | obj->fence_reg = I915_FENCE_REG_NONE; |
69dc4987 | 3537 | INIT_LIST_HEAD(&obj->mm_list); |
93a37f20 | 3538 | INIT_LIST_HEAD(&obj->gtt_list); |
69dc4987 | 3539 | INIT_LIST_HEAD(&obj->ring_list); |
432e58ed | 3540 | INIT_LIST_HEAD(&obj->exec_list); |
c397b908 | 3541 | INIT_LIST_HEAD(&obj->gpu_write_list); |
c397b908 | 3542 | obj->madv = I915_MADV_WILLNEED; |
75e9e915 DV |
3543 | /* Avoid an unnecessary call to unbind on the first bind. */ |
3544 | obj->map_and_fenceable = true; | |
de151cf6 | 3545 | |
05394f39 | 3546 | return obj; |
c397b908 DV |
3547 | } |
3548 | ||
3549 | int i915_gem_init_object(struct drm_gem_object *obj) | |
3550 | { | |
3551 | BUG(); | |
de151cf6 | 3552 | |
673a394b EA |
3553 | return 0; |
3554 | } | |
3555 | ||
05394f39 | 3556 | static void i915_gem_free_object_tail(struct drm_i915_gem_object *obj) |
673a394b | 3557 | { |
05394f39 | 3558 | struct drm_device *dev = obj->base.dev; |
be72615b | 3559 | drm_i915_private_t *dev_priv = dev->dev_private; |
be72615b | 3560 | int ret; |
673a394b | 3561 | |
be72615b CW |
3562 | ret = i915_gem_object_unbind(obj); |
3563 | if (ret == -ERESTARTSYS) { | |
05394f39 | 3564 | list_move(&obj->mm_list, |
be72615b CW |
3565 | &dev_priv->mm.deferred_free_list); |
3566 | return; | |
3567 | } | |
673a394b | 3568 | |
05394f39 | 3569 | if (obj->base.map_list.map) |
7e616158 | 3570 | i915_gem_free_mmap_offset(obj); |
de151cf6 | 3571 | |
05394f39 CW |
3572 | drm_gem_object_release(&obj->base); |
3573 | i915_gem_info_remove_obj(dev_priv, obj->base.size); | |
c397b908 | 3574 | |
05394f39 CW |
3575 | kfree(obj->page_cpu_valid); |
3576 | kfree(obj->bit_17); | |
3577 | kfree(obj); | |
673a394b EA |
3578 | } |
3579 | ||
05394f39 | 3580 | void i915_gem_free_object(struct drm_gem_object *gem_obj) |
be72615b | 3581 | { |
05394f39 CW |
3582 | struct drm_i915_gem_object *obj = to_intel_bo(gem_obj); |
3583 | struct drm_device *dev = obj->base.dev; | |
be72615b CW |
3584 | |
3585 | trace_i915_gem_object_destroy(obj); | |
3586 | ||
05394f39 | 3587 | while (obj->pin_count > 0) |
be72615b CW |
3588 | i915_gem_object_unpin(obj); |
3589 | ||
05394f39 | 3590 | if (obj->phys_obj) |
be72615b CW |
3591 | i915_gem_detach_phys_object(dev, obj); |
3592 | ||
3593 | i915_gem_free_object_tail(obj); | |
3594 | } | |
3595 | ||
29105ccc CW |
3596 | int |
3597 | i915_gem_idle(struct drm_device *dev) | |
3598 | { | |
3599 | drm_i915_private_t *dev_priv = dev->dev_private; | |
3600 | int ret; | |
28dfe52a | 3601 | |
29105ccc | 3602 | mutex_lock(&dev->struct_mutex); |
1c5d22f7 | 3603 | |
87acb0a5 | 3604 | if (dev_priv->mm.suspended) { |
29105ccc CW |
3605 | mutex_unlock(&dev->struct_mutex); |
3606 | return 0; | |
28dfe52a EA |
3607 | } |
3608 | ||
29105ccc | 3609 | ret = i915_gpu_idle(dev); |
6dbe2772 KP |
3610 | if (ret) { |
3611 | mutex_unlock(&dev->struct_mutex); | |
673a394b | 3612 | return ret; |
6dbe2772 | 3613 | } |
673a394b | 3614 | |
29105ccc CW |
3615 | /* Under UMS, be paranoid and evict. */ |
3616 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) { | |
5eac3ab4 | 3617 | ret = i915_gem_evict_inactive(dev, false); |
29105ccc CW |
3618 | if (ret) { |
3619 | mutex_unlock(&dev->struct_mutex); | |
3620 | return ret; | |
3621 | } | |
3622 | } | |
3623 | ||
312817a3 CW |
3624 | i915_gem_reset_fences(dev); |
3625 | ||
29105ccc CW |
3626 | /* Hack! Don't let anybody do execbuf while we don't control the chip. |
3627 | * We need to replace this with a semaphore, or something. | |
3628 | * And not confound mm.suspended! | |
3629 | */ | |
3630 | dev_priv->mm.suspended = 1; | |
bc0c7f14 | 3631 | del_timer_sync(&dev_priv->hangcheck_timer); |
29105ccc CW |
3632 | |
3633 | i915_kernel_lost_context(dev); | |
6dbe2772 | 3634 | i915_gem_cleanup_ringbuffer(dev); |
29105ccc | 3635 | |
6dbe2772 KP |
3636 | mutex_unlock(&dev->struct_mutex); |
3637 | ||
29105ccc CW |
3638 | /* Cancel the retire work handler, which should be idle now. */ |
3639 | cancel_delayed_work_sync(&dev_priv->mm.retire_work); | |
3640 | ||
673a394b EA |
3641 | return 0; |
3642 | } | |
3643 | ||
8187a2b7 ZN |
3644 | int |
3645 | i915_gem_init_ringbuffer(struct drm_device *dev) | |
3646 | { | |
3647 | drm_i915_private_t *dev_priv = dev->dev_private; | |
3648 | int ret; | |
68f95ba9 | 3649 | |
5c1143bb | 3650 | ret = intel_init_render_ring_buffer(dev); |
68f95ba9 | 3651 | if (ret) |
b6913e4b | 3652 | return ret; |
68f95ba9 CW |
3653 | |
3654 | if (HAS_BSD(dev)) { | |
5c1143bb | 3655 | ret = intel_init_bsd_ring_buffer(dev); |
68f95ba9 CW |
3656 | if (ret) |
3657 | goto cleanup_render_ring; | |
d1b851fc | 3658 | } |
68f95ba9 | 3659 | |
549f7365 CW |
3660 | if (HAS_BLT(dev)) { |
3661 | ret = intel_init_blt_ring_buffer(dev); | |
3662 | if (ret) | |
3663 | goto cleanup_bsd_ring; | |
3664 | } | |
3665 | ||
6f392d54 CW |
3666 | dev_priv->next_seqno = 1; |
3667 | ||
68f95ba9 CW |
3668 | return 0; |
3669 | ||
549f7365 | 3670 | cleanup_bsd_ring: |
1ec14ad3 | 3671 | intel_cleanup_ring_buffer(&dev_priv->ring[VCS]); |
68f95ba9 | 3672 | cleanup_render_ring: |
1ec14ad3 | 3673 | intel_cleanup_ring_buffer(&dev_priv->ring[RCS]); |
8187a2b7 ZN |
3674 | return ret; |
3675 | } | |
3676 | ||
3677 | void | |
3678 | i915_gem_cleanup_ringbuffer(struct drm_device *dev) | |
3679 | { | |
3680 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1ec14ad3 | 3681 | int i; |
8187a2b7 | 3682 | |
1ec14ad3 CW |
3683 | for (i = 0; i < I915_NUM_RINGS; i++) |
3684 | intel_cleanup_ring_buffer(&dev_priv->ring[i]); | |
8187a2b7 ZN |
3685 | } |
3686 | ||
673a394b EA |
3687 | int |
3688 | i915_gem_entervt_ioctl(struct drm_device *dev, void *data, | |
3689 | struct drm_file *file_priv) | |
3690 | { | |
3691 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1ec14ad3 | 3692 | int ret, i; |
673a394b | 3693 | |
79e53945 JB |
3694 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
3695 | return 0; | |
3696 | ||
ba1234d1 | 3697 | if (atomic_read(&dev_priv->mm.wedged)) { |
673a394b | 3698 | DRM_ERROR("Reenabling wedged hardware, good luck\n"); |
ba1234d1 | 3699 | atomic_set(&dev_priv->mm.wedged, 0); |
673a394b EA |
3700 | } |
3701 | ||
673a394b | 3702 | mutex_lock(&dev->struct_mutex); |
9bb2d6f9 EA |
3703 | dev_priv->mm.suspended = 0; |
3704 | ||
3705 | ret = i915_gem_init_ringbuffer(dev); | |
d816f6ac WF |
3706 | if (ret != 0) { |
3707 | mutex_unlock(&dev->struct_mutex); | |
9bb2d6f9 | 3708 | return ret; |
d816f6ac | 3709 | } |
9bb2d6f9 | 3710 | |
69dc4987 | 3711 | BUG_ON(!list_empty(&dev_priv->mm.active_list)); |
673a394b EA |
3712 | BUG_ON(!list_empty(&dev_priv->mm.flushing_list)); |
3713 | BUG_ON(!list_empty(&dev_priv->mm.inactive_list)); | |
1ec14ad3 CW |
3714 | for (i = 0; i < I915_NUM_RINGS; i++) { |
3715 | BUG_ON(!list_empty(&dev_priv->ring[i].active_list)); | |
3716 | BUG_ON(!list_empty(&dev_priv->ring[i].request_list)); | |
3717 | } | |
673a394b | 3718 | mutex_unlock(&dev->struct_mutex); |
dbb19d30 | 3719 | |
5f35308b CW |
3720 | ret = drm_irq_install(dev); |
3721 | if (ret) | |
3722 | goto cleanup_ringbuffer; | |
dbb19d30 | 3723 | |
673a394b | 3724 | return 0; |
5f35308b CW |
3725 | |
3726 | cleanup_ringbuffer: | |
3727 | mutex_lock(&dev->struct_mutex); | |
3728 | i915_gem_cleanup_ringbuffer(dev); | |
3729 | dev_priv->mm.suspended = 1; | |
3730 | mutex_unlock(&dev->struct_mutex); | |
3731 | ||
3732 | return ret; | |
673a394b EA |
3733 | } |
3734 | ||
3735 | int | |
3736 | i915_gem_leavevt_ioctl(struct drm_device *dev, void *data, | |
3737 | struct drm_file *file_priv) | |
3738 | { | |
79e53945 JB |
3739 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
3740 | return 0; | |
3741 | ||
dbb19d30 | 3742 | drm_irq_uninstall(dev); |
e6890f6f | 3743 | return i915_gem_idle(dev); |
673a394b EA |
3744 | } |
3745 | ||
3746 | void | |
3747 | i915_gem_lastclose(struct drm_device *dev) | |
3748 | { | |
3749 | int ret; | |
673a394b | 3750 | |
e806b495 EA |
3751 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
3752 | return; | |
3753 | ||
6dbe2772 KP |
3754 | ret = i915_gem_idle(dev); |
3755 | if (ret) | |
3756 | DRM_ERROR("failed to idle hardware: %d\n", ret); | |
673a394b EA |
3757 | } |
3758 | ||
64193406 CW |
3759 | static void |
3760 | init_ring_lists(struct intel_ring_buffer *ring) | |
3761 | { | |
3762 | INIT_LIST_HEAD(&ring->active_list); | |
3763 | INIT_LIST_HEAD(&ring->request_list); | |
3764 | INIT_LIST_HEAD(&ring->gpu_write_list); | |
3765 | } | |
3766 | ||
673a394b EA |
3767 | void |
3768 | i915_gem_load(struct drm_device *dev) | |
3769 | { | |
b5aa8a0f | 3770 | int i; |
673a394b EA |
3771 | drm_i915_private_t *dev_priv = dev->dev_private; |
3772 | ||
69dc4987 | 3773 | INIT_LIST_HEAD(&dev_priv->mm.active_list); |
673a394b EA |
3774 | INIT_LIST_HEAD(&dev_priv->mm.flushing_list); |
3775 | INIT_LIST_HEAD(&dev_priv->mm.inactive_list); | |
f13d3f73 | 3776 | INIT_LIST_HEAD(&dev_priv->mm.pinned_list); |
a09ba7fa | 3777 | INIT_LIST_HEAD(&dev_priv->mm.fence_list); |
be72615b | 3778 | INIT_LIST_HEAD(&dev_priv->mm.deferred_free_list); |
93a37f20 | 3779 | INIT_LIST_HEAD(&dev_priv->mm.gtt_list); |
1ec14ad3 CW |
3780 | for (i = 0; i < I915_NUM_RINGS; i++) |
3781 | init_ring_lists(&dev_priv->ring[i]); | |
007cc8ac DV |
3782 | for (i = 0; i < 16; i++) |
3783 | INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list); | |
673a394b EA |
3784 | INIT_DELAYED_WORK(&dev_priv->mm.retire_work, |
3785 | i915_gem_retire_work_handler); | |
30dbf0c0 | 3786 | init_completion(&dev_priv->error_completion); |
31169714 | 3787 | |
94400120 DA |
3788 | /* On GEN3 we really need to make sure the ARB C3 LP bit is set */ |
3789 | if (IS_GEN3(dev)) { | |
3790 | u32 tmp = I915_READ(MI_ARB_STATE); | |
3791 | if (!(tmp & MI_ARB_C3_LP_WRITE_ENABLE)) { | |
3792 | /* arb state is a masked write, so set bit + bit in mask */ | |
3793 | tmp = MI_ARB_C3_LP_WRITE_ENABLE | (MI_ARB_C3_LP_WRITE_ENABLE << MI_ARB_MASK_SHIFT); | |
3794 | I915_WRITE(MI_ARB_STATE, tmp); | |
3795 | } | |
3796 | } | |
3797 | ||
72bfa19c CW |
3798 | dev_priv->relative_constants_mode = I915_EXEC_CONSTANTS_REL_GENERAL; |
3799 | ||
de151cf6 | 3800 | /* Old X drivers will take 0-2 for front, back, depth buffers */ |
b397c836 EA |
3801 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) |
3802 | dev_priv->fence_reg_start = 3; | |
de151cf6 | 3803 | |
a6c45cf0 | 3804 | if (INTEL_INFO(dev)->gen >= 4 || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) |
de151cf6 JB |
3805 | dev_priv->num_fence_regs = 16; |
3806 | else | |
3807 | dev_priv->num_fence_regs = 8; | |
3808 | ||
b5aa8a0f | 3809 | /* Initialize fence registers to zero */ |
a6c45cf0 CW |
3810 | switch (INTEL_INFO(dev)->gen) { |
3811 | case 6: | |
3812 | for (i = 0; i < 16; i++) | |
3813 | I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + (i * 8), 0); | |
3814 | break; | |
3815 | case 5: | |
3816 | case 4: | |
b5aa8a0f GH |
3817 | for (i = 0; i < 16; i++) |
3818 | I915_WRITE64(FENCE_REG_965_0 + (i * 8), 0); | |
a6c45cf0 CW |
3819 | break; |
3820 | case 3: | |
b5aa8a0f GH |
3821 | if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) |
3822 | for (i = 0; i < 8; i++) | |
3823 | I915_WRITE(FENCE_REG_945_8 + (i * 4), 0); | |
a6c45cf0 CW |
3824 | case 2: |
3825 | for (i = 0; i < 8; i++) | |
3826 | I915_WRITE(FENCE_REG_830_0 + (i * 4), 0); | |
3827 | break; | |
b5aa8a0f | 3828 | } |
673a394b | 3829 | i915_gem_detect_bit_6_swizzle(dev); |
6b95a207 | 3830 | init_waitqueue_head(&dev_priv->pending_flip_queue); |
17250b71 CW |
3831 | |
3832 | dev_priv->mm.inactive_shrinker.shrink = i915_gem_inactive_shrink; | |
3833 | dev_priv->mm.inactive_shrinker.seeks = DEFAULT_SEEKS; | |
3834 | register_shrinker(&dev_priv->mm.inactive_shrinker); | |
673a394b | 3835 | } |
71acb5eb DA |
3836 | |
3837 | /* | |
3838 | * Create a physically contiguous memory object for this object | |
3839 | * e.g. for cursor + overlay regs | |
3840 | */ | |
995b6762 CW |
3841 | static int i915_gem_init_phys_object(struct drm_device *dev, |
3842 | int id, int size, int align) | |
71acb5eb DA |
3843 | { |
3844 | drm_i915_private_t *dev_priv = dev->dev_private; | |
3845 | struct drm_i915_gem_phys_object *phys_obj; | |
3846 | int ret; | |
3847 | ||
3848 | if (dev_priv->mm.phys_objs[id - 1] || !size) | |
3849 | return 0; | |
3850 | ||
9a298b2a | 3851 | phys_obj = kzalloc(sizeof(struct drm_i915_gem_phys_object), GFP_KERNEL); |
71acb5eb DA |
3852 | if (!phys_obj) |
3853 | return -ENOMEM; | |
3854 | ||
3855 | phys_obj->id = id; | |
3856 | ||
6eeefaf3 | 3857 | phys_obj->handle = drm_pci_alloc(dev, size, align); |
71acb5eb DA |
3858 | if (!phys_obj->handle) { |
3859 | ret = -ENOMEM; | |
3860 | goto kfree_obj; | |
3861 | } | |
3862 | #ifdef CONFIG_X86 | |
3863 | set_memory_wc((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE); | |
3864 | #endif | |
3865 | ||
3866 | dev_priv->mm.phys_objs[id - 1] = phys_obj; | |
3867 | ||
3868 | return 0; | |
3869 | kfree_obj: | |
9a298b2a | 3870 | kfree(phys_obj); |
71acb5eb DA |
3871 | return ret; |
3872 | } | |
3873 | ||
995b6762 | 3874 | static void i915_gem_free_phys_object(struct drm_device *dev, int id) |
71acb5eb DA |
3875 | { |
3876 | drm_i915_private_t *dev_priv = dev->dev_private; | |
3877 | struct drm_i915_gem_phys_object *phys_obj; | |
3878 | ||
3879 | if (!dev_priv->mm.phys_objs[id - 1]) | |
3880 | return; | |
3881 | ||
3882 | phys_obj = dev_priv->mm.phys_objs[id - 1]; | |
3883 | if (phys_obj->cur_obj) { | |
3884 | i915_gem_detach_phys_object(dev, phys_obj->cur_obj); | |
3885 | } | |
3886 | ||
3887 | #ifdef CONFIG_X86 | |
3888 | set_memory_wb((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE); | |
3889 | #endif | |
3890 | drm_pci_free(dev, phys_obj->handle); | |
3891 | kfree(phys_obj); | |
3892 | dev_priv->mm.phys_objs[id - 1] = NULL; | |
3893 | } | |
3894 | ||
3895 | void i915_gem_free_all_phys_object(struct drm_device *dev) | |
3896 | { | |
3897 | int i; | |
3898 | ||
260883c8 | 3899 | for (i = I915_GEM_PHYS_CURSOR_0; i <= I915_MAX_PHYS_OBJECT; i++) |
71acb5eb DA |
3900 | i915_gem_free_phys_object(dev, i); |
3901 | } | |
3902 | ||
3903 | void i915_gem_detach_phys_object(struct drm_device *dev, | |
05394f39 | 3904 | struct drm_i915_gem_object *obj) |
71acb5eb | 3905 | { |
05394f39 | 3906 | struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping; |
e5281ccd | 3907 | char *vaddr; |
71acb5eb | 3908 | int i; |
71acb5eb DA |
3909 | int page_count; |
3910 | ||
05394f39 | 3911 | if (!obj->phys_obj) |
71acb5eb | 3912 | return; |
05394f39 | 3913 | vaddr = obj->phys_obj->handle->vaddr; |
71acb5eb | 3914 | |
05394f39 | 3915 | page_count = obj->base.size / PAGE_SIZE; |
71acb5eb | 3916 | for (i = 0; i < page_count; i++) { |
e5281ccd CW |
3917 | struct page *page = read_cache_page_gfp(mapping, i, |
3918 | GFP_HIGHUSER | __GFP_RECLAIMABLE); | |
3919 | if (!IS_ERR(page)) { | |
3920 | char *dst = kmap_atomic(page); | |
3921 | memcpy(dst, vaddr + i*PAGE_SIZE, PAGE_SIZE); | |
3922 | kunmap_atomic(dst); | |
3923 | ||
3924 | drm_clflush_pages(&page, 1); | |
3925 | ||
3926 | set_page_dirty(page); | |
3927 | mark_page_accessed(page); | |
3928 | page_cache_release(page); | |
3929 | } | |
71acb5eb | 3930 | } |
40ce6575 | 3931 | intel_gtt_chipset_flush(); |
d78b47b9 | 3932 | |
05394f39 CW |
3933 | obj->phys_obj->cur_obj = NULL; |
3934 | obj->phys_obj = NULL; | |
71acb5eb DA |
3935 | } |
3936 | ||
3937 | int | |
3938 | i915_gem_attach_phys_object(struct drm_device *dev, | |
05394f39 | 3939 | struct drm_i915_gem_object *obj, |
6eeefaf3 CW |
3940 | int id, |
3941 | int align) | |
71acb5eb | 3942 | { |
05394f39 | 3943 | struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping; |
71acb5eb | 3944 | drm_i915_private_t *dev_priv = dev->dev_private; |
71acb5eb DA |
3945 | int ret = 0; |
3946 | int page_count; | |
3947 | int i; | |
3948 | ||
3949 | if (id > I915_MAX_PHYS_OBJECT) | |
3950 | return -EINVAL; | |
3951 | ||
05394f39 CW |
3952 | if (obj->phys_obj) { |
3953 | if (obj->phys_obj->id == id) | |
71acb5eb DA |
3954 | return 0; |
3955 | i915_gem_detach_phys_object(dev, obj); | |
3956 | } | |
3957 | ||
71acb5eb DA |
3958 | /* create a new object */ |
3959 | if (!dev_priv->mm.phys_objs[id - 1]) { | |
3960 | ret = i915_gem_init_phys_object(dev, id, | |
05394f39 | 3961 | obj->base.size, align); |
71acb5eb | 3962 | if (ret) { |
05394f39 CW |
3963 | DRM_ERROR("failed to init phys object %d size: %zu\n", |
3964 | id, obj->base.size); | |
e5281ccd | 3965 | return ret; |
71acb5eb DA |
3966 | } |
3967 | } | |
3968 | ||
3969 | /* bind to the object */ | |
05394f39 CW |
3970 | obj->phys_obj = dev_priv->mm.phys_objs[id - 1]; |
3971 | obj->phys_obj->cur_obj = obj; | |
71acb5eb | 3972 | |
05394f39 | 3973 | page_count = obj->base.size / PAGE_SIZE; |
71acb5eb DA |
3974 | |
3975 | for (i = 0; i < page_count; i++) { | |
e5281ccd CW |
3976 | struct page *page; |
3977 | char *dst, *src; | |
3978 | ||
3979 | page = read_cache_page_gfp(mapping, i, | |
3980 | GFP_HIGHUSER | __GFP_RECLAIMABLE); | |
3981 | if (IS_ERR(page)) | |
3982 | return PTR_ERR(page); | |
71acb5eb | 3983 | |
ff75b9bc | 3984 | src = kmap_atomic(page); |
05394f39 | 3985 | dst = obj->phys_obj->handle->vaddr + (i * PAGE_SIZE); |
71acb5eb | 3986 | memcpy(dst, src, PAGE_SIZE); |
3e4d3af5 | 3987 | kunmap_atomic(src); |
71acb5eb | 3988 | |
e5281ccd CW |
3989 | mark_page_accessed(page); |
3990 | page_cache_release(page); | |
3991 | } | |
d78b47b9 | 3992 | |
71acb5eb | 3993 | return 0; |
71acb5eb DA |
3994 | } |
3995 | ||
3996 | static int | |
05394f39 CW |
3997 | i915_gem_phys_pwrite(struct drm_device *dev, |
3998 | struct drm_i915_gem_object *obj, | |
71acb5eb DA |
3999 | struct drm_i915_gem_pwrite *args, |
4000 | struct drm_file *file_priv) | |
4001 | { | |
05394f39 | 4002 | void *vaddr = obj->phys_obj->handle->vaddr + args->offset; |
b47b30cc | 4003 | char __user *user_data = (char __user *) (uintptr_t) args->data_ptr; |
71acb5eb | 4004 | |
b47b30cc CW |
4005 | if (__copy_from_user_inatomic_nocache(vaddr, user_data, args->size)) { |
4006 | unsigned long unwritten; | |
4007 | ||
4008 | /* The physical object once assigned is fixed for the lifetime | |
4009 | * of the obj, so we can safely drop the lock and continue | |
4010 | * to access vaddr. | |
4011 | */ | |
4012 | mutex_unlock(&dev->struct_mutex); | |
4013 | unwritten = copy_from_user(vaddr, user_data, args->size); | |
4014 | mutex_lock(&dev->struct_mutex); | |
4015 | if (unwritten) | |
4016 | return -EFAULT; | |
4017 | } | |
71acb5eb | 4018 | |
40ce6575 | 4019 | intel_gtt_chipset_flush(); |
71acb5eb DA |
4020 | return 0; |
4021 | } | |
b962442e | 4022 | |
f787a5f5 | 4023 | void i915_gem_release(struct drm_device *dev, struct drm_file *file) |
b962442e | 4024 | { |
f787a5f5 | 4025 | struct drm_i915_file_private *file_priv = file->driver_priv; |
b962442e EA |
4026 | |
4027 | /* Clean up our request list when the client is going away, so that | |
4028 | * later retire_requests won't dereference our soon-to-be-gone | |
4029 | * file_priv. | |
4030 | */ | |
1c25595f | 4031 | spin_lock(&file_priv->mm.lock); |
f787a5f5 CW |
4032 | while (!list_empty(&file_priv->mm.request_list)) { |
4033 | struct drm_i915_gem_request *request; | |
4034 | ||
4035 | request = list_first_entry(&file_priv->mm.request_list, | |
4036 | struct drm_i915_gem_request, | |
4037 | client_list); | |
4038 | list_del(&request->client_list); | |
4039 | request->file_priv = NULL; | |
4040 | } | |
1c25595f | 4041 | spin_unlock(&file_priv->mm.lock); |
b962442e | 4042 | } |
31169714 | 4043 | |
1637ef41 CW |
4044 | static int |
4045 | i915_gpu_is_active(struct drm_device *dev) | |
4046 | { | |
4047 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4048 | int lists_empty; | |
4049 | ||
1637ef41 | 4050 | lists_empty = list_empty(&dev_priv->mm.flushing_list) && |
17250b71 | 4051 | list_empty(&dev_priv->mm.active_list); |
1637ef41 CW |
4052 | |
4053 | return !lists_empty; | |
4054 | } | |
4055 | ||
31169714 | 4056 | static int |
17250b71 CW |
4057 | i915_gem_inactive_shrink(struct shrinker *shrinker, |
4058 | int nr_to_scan, | |
4059 | gfp_t gfp_mask) | |
31169714 | 4060 | { |
17250b71 CW |
4061 | struct drm_i915_private *dev_priv = |
4062 | container_of(shrinker, | |
4063 | struct drm_i915_private, | |
4064 | mm.inactive_shrinker); | |
4065 | struct drm_device *dev = dev_priv->dev; | |
4066 | struct drm_i915_gem_object *obj, *next; | |
4067 | int cnt; | |
4068 | ||
4069 | if (!mutex_trylock(&dev->struct_mutex)) | |
bbe2e11a | 4070 | return 0; |
31169714 CW |
4071 | |
4072 | /* "fast-path" to count number of available objects */ | |
4073 | if (nr_to_scan == 0) { | |
17250b71 CW |
4074 | cnt = 0; |
4075 | list_for_each_entry(obj, | |
4076 | &dev_priv->mm.inactive_list, | |
4077 | mm_list) | |
4078 | cnt++; | |
4079 | mutex_unlock(&dev->struct_mutex); | |
4080 | return cnt / 100 * sysctl_vfs_cache_pressure; | |
31169714 CW |
4081 | } |
4082 | ||
1637ef41 | 4083 | rescan: |
31169714 | 4084 | /* first scan for clean buffers */ |
17250b71 | 4085 | i915_gem_retire_requests(dev); |
31169714 | 4086 | |
17250b71 CW |
4087 | list_for_each_entry_safe(obj, next, |
4088 | &dev_priv->mm.inactive_list, | |
4089 | mm_list) { | |
4090 | if (i915_gem_object_is_purgeable(obj)) { | |
2021746e CW |
4091 | if (i915_gem_object_unbind(obj) == 0 && |
4092 | --nr_to_scan == 0) | |
17250b71 | 4093 | break; |
31169714 | 4094 | } |
31169714 CW |
4095 | } |
4096 | ||
4097 | /* second pass, evict/count anything still on the inactive list */ | |
17250b71 CW |
4098 | cnt = 0; |
4099 | list_for_each_entry_safe(obj, next, | |
4100 | &dev_priv->mm.inactive_list, | |
4101 | mm_list) { | |
2021746e CW |
4102 | if (nr_to_scan && |
4103 | i915_gem_object_unbind(obj) == 0) | |
17250b71 | 4104 | nr_to_scan--; |
2021746e | 4105 | else |
17250b71 CW |
4106 | cnt++; |
4107 | } | |
4108 | ||
4109 | if (nr_to_scan && i915_gpu_is_active(dev)) { | |
1637ef41 CW |
4110 | /* |
4111 | * We are desperate for pages, so as a last resort, wait | |
4112 | * for the GPU to finish and discard whatever we can. | |
4113 | * This has a dramatic impact to reduce the number of | |
4114 | * OOM-killer events whilst running the GPU aggressively. | |
4115 | */ | |
17250b71 | 4116 | if (i915_gpu_idle(dev) == 0) |
1637ef41 CW |
4117 | goto rescan; |
4118 | } | |
17250b71 CW |
4119 | mutex_unlock(&dev->struct_mutex); |
4120 | return cnt / 100 * sysctl_vfs_cache_pressure; | |
31169714 | 4121 | } |