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673a394b | 1 | /* |
be6a0376 | 2 | * Copyright © 2008-2015 Intel Corporation |
673a394b EA |
3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | * | |
26 | */ | |
27 | ||
760285e7 | 28 | #include <drm/drmP.h> |
0de23977 | 29 | #include <drm/drm_vma_manager.h> |
760285e7 | 30 | #include <drm/i915_drm.h> |
673a394b | 31 | #include "i915_drv.h" |
c13d87ea | 32 | #include "i915_gem_dmabuf.h" |
eb82289a | 33 | #include "i915_vgpu.h" |
1c5d22f7 | 34 | #include "i915_trace.h" |
652c393a | 35 | #include "intel_drv.h" |
5d723d7a | 36 | #include "intel_frontbuffer.h" |
0ccdacf6 | 37 | #include "intel_mocs.h" |
c13d87ea | 38 | #include <linux/reservation.h> |
5949eac4 | 39 | #include <linux/shmem_fs.h> |
5a0e3ad6 | 40 | #include <linux/slab.h> |
673a394b | 41 | #include <linux/swap.h> |
79e53945 | 42 | #include <linux/pci.h> |
1286ff73 | 43 | #include <linux/dma-buf.h> |
673a394b | 44 | |
05394f39 | 45 | static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj); |
e62b59e4 | 46 | static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj); |
61050808 | 47 | |
c76ce038 CW |
48 | static bool cpu_cache_is_coherent(struct drm_device *dev, |
49 | enum i915_cache_level level) | |
50 | { | |
51 | return HAS_LLC(dev) || level != I915_CACHE_NONE; | |
52 | } | |
53 | ||
2c22569b CW |
54 | static bool cpu_write_needs_clflush(struct drm_i915_gem_object *obj) |
55 | { | |
b50a5371 AS |
56 | if (obj->base.write_domain == I915_GEM_DOMAIN_CPU) |
57 | return false; | |
58 | ||
2c22569b CW |
59 | if (!cpu_cache_is_coherent(obj->base.dev, obj->cache_level)) |
60 | return true; | |
61 | ||
62 | return obj->pin_display; | |
63 | } | |
64 | ||
4f1959ee AS |
65 | static int |
66 | insert_mappable_node(struct drm_i915_private *i915, | |
67 | struct drm_mm_node *node, u32 size) | |
68 | { | |
69 | memset(node, 0, sizeof(*node)); | |
70 | return drm_mm_insert_node_in_range_generic(&i915->ggtt.base.mm, node, | |
71 | size, 0, 0, 0, | |
72 | i915->ggtt.mappable_end, | |
73 | DRM_MM_SEARCH_DEFAULT, | |
74 | DRM_MM_CREATE_DEFAULT); | |
75 | } | |
76 | ||
77 | static void | |
78 | remove_mappable_node(struct drm_mm_node *node) | |
79 | { | |
80 | drm_mm_remove_node(node); | |
81 | } | |
82 | ||
73aa808f CW |
83 | /* some bookkeeping */ |
84 | static void i915_gem_info_add_obj(struct drm_i915_private *dev_priv, | |
85 | size_t size) | |
86 | { | |
c20e8355 | 87 | spin_lock(&dev_priv->mm.object_stat_lock); |
73aa808f CW |
88 | dev_priv->mm.object_count++; |
89 | dev_priv->mm.object_memory += size; | |
c20e8355 | 90 | spin_unlock(&dev_priv->mm.object_stat_lock); |
73aa808f CW |
91 | } |
92 | ||
93 | static void i915_gem_info_remove_obj(struct drm_i915_private *dev_priv, | |
94 | size_t size) | |
95 | { | |
c20e8355 | 96 | spin_lock(&dev_priv->mm.object_stat_lock); |
73aa808f CW |
97 | dev_priv->mm.object_count--; |
98 | dev_priv->mm.object_memory -= size; | |
c20e8355 | 99 | spin_unlock(&dev_priv->mm.object_stat_lock); |
73aa808f CW |
100 | } |
101 | ||
21dd3734 | 102 | static int |
33196ded | 103 | i915_gem_wait_for_error(struct i915_gpu_error *error) |
30dbf0c0 | 104 | { |
30dbf0c0 CW |
105 | int ret; |
106 | ||
d98c52cf | 107 | if (!i915_reset_in_progress(error)) |
30dbf0c0 CW |
108 | return 0; |
109 | ||
0a6759c6 DV |
110 | /* |
111 | * Only wait 10 seconds for the gpu reset to complete to avoid hanging | |
112 | * userspace. If it takes that long something really bad is going on and | |
113 | * we should simply try to bail out and fail as gracefully as possible. | |
114 | */ | |
1f83fee0 | 115 | ret = wait_event_interruptible_timeout(error->reset_queue, |
d98c52cf | 116 | !i915_reset_in_progress(error), |
1f83fee0 | 117 | 10*HZ); |
0a6759c6 DV |
118 | if (ret == 0) { |
119 | DRM_ERROR("Timed out waiting for the gpu reset to complete\n"); | |
120 | return -EIO; | |
121 | } else if (ret < 0) { | |
30dbf0c0 | 122 | return ret; |
d98c52cf CW |
123 | } else { |
124 | return 0; | |
0a6759c6 | 125 | } |
30dbf0c0 CW |
126 | } |
127 | ||
54cf91dc | 128 | int i915_mutex_lock_interruptible(struct drm_device *dev) |
76c1dec1 | 129 | { |
fac5e23e | 130 | struct drm_i915_private *dev_priv = to_i915(dev); |
76c1dec1 CW |
131 | int ret; |
132 | ||
33196ded | 133 | ret = i915_gem_wait_for_error(&dev_priv->gpu_error); |
76c1dec1 CW |
134 | if (ret) |
135 | return ret; | |
136 | ||
137 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
138 | if (ret) | |
139 | return ret; | |
140 | ||
76c1dec1 CW |
141 | return 0; |
142 | } | |
30dbf0c0 | 143 | |
5a125c3c EA |
144 | int |
145 | i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 146 | struct drm_file *file) |
5a125c3c | 147 | { |
72e96d64 | 148 | struct drm_i915_private *dev_priv = to_i915(dev); |
62106b4f | 149 | struct i915_ggtt *ggtt = &dev_priv->ggtt; |
72e96d64 | 150 | struct drm_i915_gem_get_aperture *args = data; |
ca1543be | 151 | struct i915_vma *vma; |
6299f992 | 152 | size_t pinned; |
5a125c3c | 153 | |
6299f992 | 154 | pinned = 0; |
73aa808f | 155 | mutex_lock(&dev->struct_mutex); |
1c7f4bca | 156 | list_for_each_entry(vma, &ggtt->base.active_list, vm_link) |
20dfbde4 | 157 | if (i915_vma_is_pinned(vma)) |
ca1543be | 158 | pinned += vma->node.size; |
1c7f4bca | 159 | list_for_each_entry(vma, &ggtt->base.inactive_list, vm_link) |
20dfbde4 | 160 | if (i915_vma_is_pinned(vma)) |
ca1543be | 161 | pinned += vma->node.size; |
73aa808f | 162 | mutex_unlock(&dev->struct_mutex); |
5a125c3c | 163 | |
72e96d64 | 164 | args->aper_size = ggtt->base.total; |
0206e353 | 165 | args->aper_available_size = args->aper_size - pinned; |
6299f992 | 166 | |
5a125c3c EA |
167 | return 0; |
168 | } | |
169 | ||
6a2c4232 CW |
170 | static int |
171 | i915_gem_object_get_pages_phys(struct drm_i915_gem_object *obj) | |
00731155 | 172 | { |
6a2c4232 CW |
173 | struct address_space *mapping = file_inode(obj->base.filp)->i_mapping; |
174 | char *vaddr = obj->phys_handle->vaddr; | |
175 | struct sg_table *st; | |
176 | struct scatterlist *sg; | |
177 | int i; | |
00731155 | 178 | |
6a2c4232 CW |
179 | if (WARN_ON(i915_gem_object_needs_bit17_swizzle(obj))) |
180 | return -EINVAL; | |
181 | ||
182 | for (i = 0; i < obj->base.size / PAGE_SIZE; i++) { | |
183 | struct page *page; | |
184 | char *src; | |
185 | ||
186 | page = shmem_read_mapping_page(mapping, i); | |
187 | if (IS_ERR(page)) | |
188 | return PTR_ERR(page); | |
189 | ||
190 | src = kmap_atomic(page); | |
191 | memcpy(vaddr, src, PAGE_SIZE); | |
192 | drm_clflush_virt_range(vaddr, PAGE_SIZE); | |
193 | kunmap_atomic(src); | |
194 | ||
09cbfeaf | 195 | put_page(page); |
6a2c4232 CW |
196 | vaddr += PAGE_SIZE; |
197 | } | |
198 | ||
c033666a | 199 | i915_gem_chipset_flush(to_i915(obj->base.dev)); |
6a2c4232 CW |
200 | |
201 | st = kmalloc(sizeof(*st), GFP_KERNEL); | |
202 | if (st == NULL) | |
203 | return -ENOMEM; | |
204 | ||
205 | if (sg_alloc_table(st, 1, GFP_KERNEL)) { | |
206 | kfree(st); | |
207 | return -ENOMEM; | |
208 | } | |
209 | ||
210 | sg = st->sgl; | |
211 | sg->offset = 0; | |
212 | sg->length = obj->base.size; | |
00731155 | 213 | |
6a2c4232 CW |
214 | sg_dma_address(sg) = obj->phys_handle->busaddr; |
215 | sg_dma_len(sg) = obj->base.size; | |
216 | ||
217 | obj->pages = st; | |
6a2c4232 CW |
218 | return 0; |
219 | } | |
220 | ||
221 | static void | |
222 | i915_gem_object_put_pages_phys(struct drm_i915_gem_object *obj) | |
223 | { | |
224 | int ret; | |
225 | ||
226 | BUG_ON(obj->madv == __I915_MADV_PURGED); | |
00731155 | 227 | |
6a2c4232 | 228 | ret = i915_gem_object_set_to_cpu_domain(obj, true); |
f4457ae7 | 229 | if (WARN_ON(ret)) { |
6a2c4232 CW |
230 | /* In the event of a disaster, abandon all caches and |
231 | * hope for the best. | |
232 | */ | |
6a2c4232 CW |
233 | obj->base.read_domains = obj->base.write_domain = I915_GEM_DOMAIN_CPU; |
234 | } | |
235 | ||
236 | if (obj->madv == I915_MADV_DONTNEED) | |
237 | obj->dirty = 0; | |
238 | ||
239 | if (obj->dirty) { | |
00731155 | 240 | struct address_space *mapping = file_inode(obj->base.filp)->i_mapping; |
6a2c4232 | 241 | char *vaddr = obj->phys_handle->vaddr; |
00731155 CW |
242 | int i; |
243 | ||
244 | for (i = 0; i < obj->base.size / PAGE_SIZE; i++) { | |
6a2c4232 CW |
245 | struct page *page; |
246 | char *dst; | |
247 | ||
248 | page = shmem_read_mapping_page(mapping, i); | |
249 | if (IS_ERR(page)) | |
250 | continue; | |
251 | ||
252 | dst = kmap_atomic(page); | |
253 | drm_clflush_virt_range(vaddr, PAGE_SIZE); | |
254 | memcpy(dst, vaddr, PAGE_SIZE); | |
255 | kunmap_atomic(dst); | |
256 | ||
257 | set_page_dirty(page); | |
258 | if (obj->madv == I915_MADV_WILLNEED) | |
00731155 | 259 | mark_page_accessed(page); |
09cbfeaf | 260 | put_page(page); |
00731155 CW |
261 | vaddr += PAGE_SIZE; |
262 | } | |
6a2c4232 | 263 | obj->dirty = 0; |
00731155 CW |
264 | } |
265 | ||
6a2c4232 CW |
266 | sg_free_table(obj->pages); |
267 | kfree(obj->pages); | |
6a2c4232 CW |
268 | } |
269 | ||
270 | static void | |
271 | i915_gem_object_release_phys(struct drm_i915_gem_object *obj) | |
272 | { | |
273 | drm_pci_free(obj->base.dev, obj->phys_handle); | |
274 | } | |
275 | ||
276 | static const struct drm_i915_gem_object_ops i915_gem_phys_ops = { | |
277 | .get_pages = i915_gem_object_get_pages_phys, | |
278 | .put_pages = i915_gem_object_put_pages_phys, | |
279 | .release = i915_gem_object_release_phys, | |
280 | }; | |
281 | ||
aa653a68 CW |
282 | int |
283 | i915_gem_object_unbind(struct drm_i915_gem_object *obj) | |
284 | { | |
285 | struct i915_vma *vma; | |
286 | LIST_HEAD(still_in_list); | |
287 | int ret; | |
288 | ||
289 | /* The vma will only be freed if it is marked as closed, and if we wait | |
290 | * upon rendering to the vma, we may unbind anything in the list. | |
291 | */ | |
292 | while ((vma = list_first_entry_or_null(&obj->vma_list, | |
293 | struct i915_vma, | |
294 | obj_link))) { | |
295 | list_move_tail(&vma->obj_link, &still_in_list); | |
296 | ret = i915_vma_unbind(vma); | |
297 | if (ret) | |
298 | break; | |
299 | } | |
300 | list_splice(&still_in_list, &obj->vma_list); | |
301 | ||
302 | return ret; | |
303 | } | |
304 | ||
00e60f26 CW |
305 | /** |
306 | * Ensures that all rendering to the object has completed and the object is | |
307 | * safe to unbind from the GTT or access from the CPU. | |
308 | * @obj: i915 gem object | |
309 | * @readonly: waiting for just read access or read-write access | |
310 | */ | |
311 | int | |
312 | i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj, | |
313 | bool readonly) | |
314 | { | |
315 | struct reservation_object *resv; | |
316 | struct i915_gem_active *active; | |
317 | unsigned long active_mask; | |
318 | int idx; | |
319 | ||
320 | lockdep_assert_held(&obj->base.dev->struct_mutex); | |
321 | ||
322 | if (!readonly) { | |
323 | active = obj->last_read; | |
324 | active_mask = i915_gem_object_get_active(obj); | |
325 | } else { | |
326 | active_mask = 1; | |
327 | active = &obj->last_write; | |
328 | } | |
329 | ||
330 | for_each_active(active_mask, idx) { | |
331 | int ret; | |
332 | ||
333 | ret = i915_gem_active_wait(&active[idx], | |
334 | &obj->base.dev->struct_mutex); | |
335 | if (ret) | |
336 | return ret; | |
337 | } | |
338 | ||
339 | resv = i915_gem_object_get_dmabuf_resv(obj); | |
340 | if (resv) { | |
341 | long err; | |
342 | ||
343 | err = reservation_object_wait_timeout_rcu(resv, !readonly, true, | |
344 | MAX_SCHEDULE_TIMEOUT); | |
345 | if (err < 0) | |
346 | return err; | |
347 | } | |
348 | ||
349 | return 0; | |
350 | } | |
351 | ||
b8f9096d CW |
352 | /* A nonblocking variant of the above wait. Must be called prior to |
353 | * acquiring the mutex for the object, as the object state may change | |
354 | * during this call. A reference must be held by the caller for the object. | |
00e60f26 CW |
355 | */ |
356 | static __must_check int | |
b8f9096d CW |
357 | __unsafe_wait_rendering(struct drm_i915_gem_object *obj, |
358 | struct intel_rps_client *rps, | |
359 | bool readonly) | |
00e60f26 | 360 | { |
00e60f26 CW |
361 | struct i915_gem_active *active; |
362 | unsigned long active_mask; | |
b8f9096d | 363 | int idx; |
00e60f26 | 364 | |
b8f9096d | 365 | active_mask = __I915_BO_ACTIVE(obj); |
00e60f26 CW |
366 | if (!active_mask) |
367 | return 0; | |
368 | ||
369 | if (!readonly) { | |
370 | active = obj->last_read; | |
371 | } else { | |
372 | active_mask = 1; | |
373 | active = &obj->last_write; | |
374 | } | |
375 | ||
b8f9096d CW |
376 | for_each_active(active_mask, idx) { |
377 | int ret; | |
00e60f26 | 378 | |
b8f9096d CW |
379 | ret = i915_gem_active_wait_unlocked(&active[idx], |
380 | true, NULL, rps); | |
381 | if (ret) | |
382 | return ret; | |
00e60f26 CW |
383 | } |
384 | ||
b8f9096d | 385 | return 0; |
00e60f26 CW |
386 | } |
387 | ||
388 | static struct intel_rps_client *to_rps_client(struct drm_file *file) | |
389 | { | |
390 | struct drm_i915_file_private *fpriv = file->driver_priv; | |
391 | ||
392 | return &fpriv->rps; | |
393 | } | |
394 | ||
00731155 CW |
395 | int |
396 | i915_gem_object_attach_phys(struct drm_i915_gem_object *obj, | |
397 | int align) | |
398 | { | |
399 | drm_dma_handle_t *phys; | |
6a2c4232 | 400 | int ret; |
00731155 CW |
401 | |
402 | if (obj->phys_handle) { | |
403 | if ((unsigned long)obj->phys_handle->vaddr & (align -1)) | |
404 | return -EBUSY; | |
405 | ||
406 | return 0; | |
407 | } | |
408 | ||
409 | if (obj->madv != I915_MADV_WILLNEED) | |
410 | return -EFAULT; | |
411 | ||
412 | if (obj->base.filp == NULL) | |
413 | return -EINVAL; | |
414 | ||
4717ca9e CW |
415 | ret = i915_gem_object_unbind(obj); |
416 | if (ret) | |
417 | return ret; | |
418 | ||
419 | ret = i915_gem_object_put_pages(obj); | |
6a2c4232 CW |
420 | if (ret) |
421 | return ret; | |
422 | ||
00731155 CW |
423 | /* create a new object */ |
424 | phys = drm_pci_alloc(obj->base.dev, obj->base.size, align); | |
425 | if (!phys) | |
426 | return -ENOMEM; | |
427 | ||
00731155 | 428 | obj->phys_handle = phys; |
6a2c4232 CW |
429 | obj->ops = &i915_gem_phys_ops; |
430 | ||
431 | return i915_gem_object_get_pages(obj); | |
00731155 CW |
432 | } |
433 | ||
434 | static int | |
435 | i915_gem_phys_pwrite(struct drm_i915_gem_object *obj, | |
436 | struct drm_i915_gem_pwrite *args, | |
437 | struct drm_file *file_priv) | |
438 | { | |
439 | struct drm_device *dev = obj->base.dev; | |
440 | void *vaddr = obj->phys_handle->vaddr + args->offset; | |
3ed605bc | 441 | char __user *user_data = u64_to_user_ptr(args->data_ptr); |
063e4e6b | 442 | int ret = 0; |
6a2c4232 CW |
443 | |
444 | /* We manually control the domain here and pretend that it | |
445 | * remains coherent i.e. in the GTT domain, like shmem_pwrite. | |
446 | */ | |
447 | ret = i915_gem_object_wait_rendering(obj, false); | |
448 | if (ret) | |
449 | return ret; | |
00731155 | 450 | |
77a0d1ca | 451 | intel_fb_obj_invalidate(obj, ORIGIN_CPU); |
00731155 CW |
452 | if (__copy_from_user_inatomic_nocache(vaddr, user_data, args->size)) { |
453 | unsigned long unwritten; | |
454 | ||
455 | /* The physical object once assigned is fixed for the lifetime | |
456 | * of the obj, so we can safely drop the lock and continue | |
457 | * to access vaddr. | |
458 | */ | |
459 | mutex_unlock(&dev->struct_mutex); | |
460 | unwritten = copy_from_user(vaddr, user_data, args->size); | |
461 | mutex_lock(&dev->struct_mutex); | |
063e4e6b PZ |
462 | if (unwritten) { |
463 | ret = -EFAULT; | |
464 | goto out; | |
465 | } | |
00731155 CW |
466 | } |
467 | ||
6a2c4232 | 468 | drm_clflush_virt_range(vaddr, args->size); |
c033666a | 469 | i915_gem_chipset_flush(to_i915(dev)); |
063e4e6b PZ |
470 | |
471 | out: | |
de152b62 | 472 | intel_fb_obj_flush(obj, false, ORIGIN_CPU); |
063e4e6b | 473 | return ret; |
00731155 CW |
474 | } |
475 | ||
42dcedd4 CW |
476 | void *i915_gem_object_alloc(struct drm_device *dev) |
477 | { | |
fac5e23e | 478 | struct drm_i915_private *dev_priv = to_i915(dev); |
efab6d8d | 479 | return kmem_cache_zalloc(dev_priv->objects, GFP_KERNEL); |
42dcedd4 CW |
480 | } |
481 | ||
482 | void i915_gem_object_free(struct drm_i915_gem_object *obj) | |
483 | { | |
fac5e23e | 484 | struct drm_i915_private *dev_priv = to_i915(obj->base.dev); |
efab6d8d | 485 | kmem_cache_free(dev_priv->objects, obj); |
42dcedd4 CW |
486 | } |
487 | ||
ff72145b DA |
488 | static int |
489 | i915_gem_create(struct drm_file *file, | |
490 | struct drm_device *dev, | |
491 | uint64_t size, | |
492 | uint32_t *handle_p) | |
673a394b | 493 | { |
05394f39 | 494 | struct drm_i915_gem_object *obj; |
a1a2d1d3 PP |
495 | int ret; |
496 | u32 handle; | |
673a394b | 497 | |
ff72145b | 498 | size = roundup(size, PAGE_SIZE); |
8ffc0246 CW |
499 | if (size == 0) |
500 | return -EINVAL; | |
673a394b EA |
501 | |
502 | /* Allocate the new object */ | |
d37cd8a8 | 503 | obj = i915_gem_object_create(dev, size); |
fe3db79b CW |
504 | if (IS_ERR(obj)) |
505 | return PTR_ERR(obj); | |
673a394b | 506 | |
05394f39 | 507 | ret = drm_gem_handle_create(file, &obj->base, &handle); |
202f2fef | 508 | /* drop reference from allocate - handle holds it now */ |
34911fd3 | 509 | i915_gem_object_put_unlocked(obj); |
d861e338 DV |
510 | if (ret) |
511 | return ret; | |
202f2fef | 512 | |
ff72145b | 513 | *handle_p = handle; |
673a394b EA |
514 | return 0; |
515 | } | |
516 | ||
ff72145b DA |
517 | int |
518 | i915_gem_dumb_create(struct drm_file *file, | |
519 | struct drm_device *dev, | |
520 | struct drm_mode_create_dumb *args) | |
521 | { | |
522 | /* have to work out size/pitch and return them */ | |
de45eaf7 | 523 | args->pitch = ALIGN(args->width * DIV_ROUND_UP(args->bpp, 8), 64); |
ff72145b DA |
524 | args->size = args->pitch * args->height; |
525 | return i915_gem_create(file, dev, | |
da6b51d0 | 526 | args->size, &args->handle); |
ff72145b DA |
527 | } |
528 | ||
ff72145b DA |
529 | /** |
530 | * Creates a new mm object and returns a handle to it. | |
14bb2c11 TU |
531 | * @dev: drm device pointer |
532 | * @data: ioctl data blob | |
533 | * @file: drm file pointer | |
ff72145b DA |
534 | */ |
535 | int | |
536 | i915_gem_create_ioctl(struct drm_device *dev, void *data, | |
537 | struct drm_file *file) | |
538 | { | |
539 | struct drm_i915_gem_create *args = data; | |
63ed2cb2 | 540 | |
ff72145b | 541 | return i915_gem_create(file, dev, |
da6b51d0 | 542 | args->size, &args->handle); |
ff72145b DA |
543 | } |
544 | ||
8461d226 DV |
545 | static inline int |
546 | __copy_to_user_swizzled(char __user *cpu_vaddr, | |
547 | const char *gpu_vaddr, int gpu_offset, | |
548 | int length) | |
549 | { | |
550 | int ret, cpu_offset = 0; | |
551 | ||
552 | while (length > 0) { | |
553 | int cacheline_end = ALIGN(gpu_offset + 1, 64); | |
554 | int this_length = min(cacheline_end - gpu_offset, length); | |
555 | int swizzled_gpu_offset = gpu_offset ^ 64; | |
556 | ||
557 | ret = __copy_to_user(cpu_vaddr + cpu_offset, | |
558 | gpu_vaddr + swizzled_gpu_offset, | |
559 | this_length); | |
560 | if (ret) | |
561 | return ret + length; | |
562 | ||
563 | cpu_offset += this_length; | |
564 | gpu_offset += this_length; | |
565 | length -= this_length; | |
566 | } | |
567 | ||
568 | return 0; | |
569 | } | |
570 | ||
8c59967c | 571 | static inline int |
4f0c7cfb BW |
572 | __copy_from_user_swizzled(char *gpu_vaddr, int gpu_offset, |
573 | const char __user *cpu_vaddr, | |
8c59967c DV |
574 | int length) |
575 | { | |
576 | int ret, cpu_offset = 0; | |
577 | ||
578 | while (length > 0) { | |
579 | int cacheline_end = ALIGN(gpu_offset + 1, 64); | |
580 | int this_length = min(cacheline_end - gpu_offset, length); | |
581 | int swizzled_gpu_offset = gpu_offset ^ 64; | |
582 | ||
583 | ret = __copy_from_user(gpu_vaddr + swizzled_gpu_offset, | |
584 | cpu_vaddr + cpu_offset, | |
585 | this_length); | |
586 | if (ret) | |
587 | return ret + length; | |
588 | ||
589 | cpu_offset += this_length; | |
590 | gpu_offset += this_length; | |
591 | length -= this_length; | |
592 | } | |
593 | ||
594 | return 0; | |
595 | } | |
596 | ||
4c914c0c BV |
597 | /* |
598 | * Pins the specified object's pages and synchronizes the object with | |
599 | * GPU accesses. Sets needs_clflush to non-zero if the caller should | |
600 | * flush the object from the CPU cache. | |
601 | */ | |
602 | int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj, | |
603 | int *needs_clflush) | |
604 | { | |
605 | int ret; | |
606 | ||
607 | *needs_clflush = 0; | |
608 | ||
b9bcd14a | 609 | if (WARN_ON(!i915_gem_object_has_struct_page(obj))) |
4c914c0c BV |
610 | return -EINVAL; |
611 | ||
c13d87ea CW |
612 | ret = i915_gem_object_wait_rendering(obj, true); |
613 | if (ret) | |
614 | return ret; | |
615 | ||
4c914c0c BV |
616 | if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU)) { |
617 | /* If we're not in the cpu read domain, set ourself into the gtt | |
618 | * read domain and manually flush cachelines (if required). This | |
619 | * optimizes for the case when the gpu will dirty the data | |
620 | * anyway again before the next pread happens. */ | |
621 | *needs_clflush = !cpu_cache_is_coherent(obj->base.dev, | |
622 | obj->cache_level); | |
4c914c0c BV |
623 | } |
624 | ||
625 | ret = i915_gem_object_get_pages(obj); | |
626 | if (ret) | |
627 | return ret; | |
628 | ||
629 | i915_gem_object_pin_pages(obj); | |
630 | ||
631 | return ret; | |
632 | } | |
633 | ||
d174bd64 DV |
634 | /* Per-page copy function for the shmem pread fastpath. |
635 | * Flushes invalid cachelines before reading the target if | |
636 | * needs_clflush is set. */ | |
eb01459f | 637 | static int |
d174bd64 DV |
638 | shmem_pread_fast(struct page *page, int shmem_page_offset, int page_length, |
639 | char __user *user_data, | |
640 | bool page_do_bit17_swizzling, bool needs_clflush) | |
641 | { | |
642 | char *vaddr; | |
643 | int ret; | |
644 | ||
e7e58eb5 | 645 | if (unlikely(page_do_bit17_swizzling)) |
d174bd64 DV |
646 | return -EINVAL; |
647 | ||
648 | vaddr = kmap_atomic(page); | |
649 | if (needs_clflush) | |
650 | drm_clflush_virt_range(vaddr + shmem_page_offset, | |
651 | page_length); | |
652 | ret = __copy_to_user_inatomic(user_data, | |
653 | vaddr + shmem_page_offset, | |
654 | page_length); | |
655 | kunmap_atomic(vaddr); | |
656 | ||
f60d7f0c | 657 | return ret ? -EFAULT : 0; |
d174bd64 DV |
658 | } |
659 | ||
23c18c71 DV |
660 | static void |
661 | shmem_clflush_swizzled_range(char *addr, unsigned long length, | |
662 | bool swizzled) | |
663 | { | |
e7e58eb5 | 664 | if (unlikely(swizzled)) { |
23c18c71 DV |
665 | unsigned long start = (unsigned long) addr; |
666 | unsigned long end = (unsigned long) addr + length; | |
667 | ||
668 | /* For swizzling simply ensure that we always flush both | |
669 | * channels. Lame, but simple and it works. Swizzled | |
670 | * pwrite/pread is far from a hotpath - current userspace | |
671 | * doesn't use it at all. */ | |
672 | start = round_down(start, 128); | |
673 | end = round_up(end, 128); | |
674 | ||
675 | drm_clflush_virt_range((void *)start, end - start); | |
676 | } else { | |
677 | drm_clflush_virt_range(addr, length); | |
678 | } | |
679 | ||
680 | } | |
681 | ||
d174bd64 DV |
682 | /* Only difference to the fast-path function is that this can handle bit17 |
683 | * and uses non-atomic copy and kmap functions. */ | |
684 | static int | |
685 | shmem_pread_slow(struct page *page, int shmem_page_offset, int page_length, | |
686 | char __user *user_data, | |
687 | bool page_do_bit17_swizzling, bool needs_clflush) | |
688 | { | |
689 | char *vaddr; | |
690 | int ret; | |
691 | ||
692 | vaddr = kmap(page); | |
693 | if (needs_clflush) | |
23c18c71 DV |
694 | shmem_clflush_swizzled_range(vaddr + shmem_page_offset, |
695 | page_length, | |
696 | page_do_bit17_swizzling); | |
d174bd64 DV |
697 | |
698 | if (page_do_bit17_swizzling) | |
699 | ret = __copy_to_user_swizzled(user_data, | |
700 | vaddr, shmem_page_offset, | |
701 | page_length); | |
702 | else | |
703 | ret = __copy_to_user(user_data, | |
704 | vaddr + shmem_page_offset, | |
705 | page_length); | |
706 | kunmap(page); | |
707 | ||
f60d7f0c | 708 | return ret ? - EFAULT : 0; |
d174bd64 DV |
709 | } |
710 | ||
b50a5371 AS |
711 | static inline unsigned long |
712 | slow_user_access(struct io_mapping *mapping, | |
713 | uint64_t page_base, int page_offset, | |
714 | char __user *user_data, | |
715 | unsigned long length, bool pwrite) | |
716 | { | |
717 | void __iomem *ioaddr; | |
718 | void *vaddr; | |
719 | uint64_t unwritten; | |
720 | ||
721 | ioaddr = io_mapping_map_wc(mapping, page_base, PAGE_SIZE); | |
722 | /* We can use the cpu mem copy function because this is X86. */ | |
723 | vaddr = (void __force *)ioaddr + page_offset; | |
724 | if (pwrite) | |
725 | unwritten = __copy_from_user(vaddr, user_data, length); | |
726 | else | |
727 | unwritten = __copy_to_user(user_data, vaddr, length); | |
728 | ||
729 | io_mapping_unmap(ioaddr); | |
730 | return unwritten; | |
731 | } | |
732 | ||
733 | static int | |
734 | i915_gem_gtt_pread(struct drm_device *dev, | |
735 | struct drm_i915_gem_object *obj, uint64_t size, | |
736 | uint64_t data_offset, uint64_t data_ptr) | |
737 | { | |
fac5e23e | 738 | struct drm_i915_private *dev_priv = to_i915(dev); |
b50a5371 AS |
739 | struct i915_ggtt *ggtt = &dev_priv->ggtt; |
740 | struct drm_mm_node node; | |
741 | char __user *user_data; | |
742 | uint64_t remain; | |
743 | uint64_t offset; | |
744 | int ret; | |
745 | ||
de895082 | 746 | ret = i915_gem_object_ggtt_pin(obj, NULL, 0, 0, PIN_MAPPABLE); |
b50a5371 AS |
747 | if (ret) { |
748 | ret = insert_mappable_node(dev_priv, &node, PAGE_SIZE); | |
749 | if (ret) | |
750 | goto out; | |
751 | ||
752 | ret = i915_gem_object_get_pages(obj); | |
753 | if (ret) { | |
754 | remove_mappable_node(&node); | |
755 | goto out; | |
756 | } | |
757 | ||
758 | i915_gem_object_pin_pages(obj); | |
759 | } else { | |
760 | node.start = i915_gem_obj_ggtt_offset(obj); | |
761 | node.allocated = false; | |
762 | ret = i915_gem_object_put_fence(obj); | |
763 | if (ret) | |
764 | goto out_unpin; | |
765 | } | |
766 | ||
767 | ret = i915_gem_object_set_to_gtt_domain(obj, false); | |
768 | if (ret) | |
769 | goto out_unpin; | |
770 | ||
771 | user_data = u64_to_user_ptr(data_ptr); | |
772 | remain = size; | |
773 | offset = data_offset; | |
774 | ||
775 | mutex_unlock(&dev->struct_mutex); | |
776 | if (likely(!i915.prefault_disable)) { | |
777 | ret = fault_in_multipages_writeable(user_data, remain); | |
778 | if (ret) { | |
779 | mutex_lock(&dev->struct_mutex); | |
780 | goto out_unpin; | |
781 | } | |
782 | } | |
783 | ||
784 | while (remain > 0) { | |
785 | /* Operation in this page | |
786 | * | |
787 | * page_base = page offset within aperture | |
788 | * page_offset = offset within page | |
789 | * page_length = bytes to copy for this page | |
790 | */ | |
791 | u32 page_base = node.start; | |
792 | unsigned page_offset = offset_in_page(offset); | |
793 | unsigned page_length = PAGE_SIZE - page_offset; | |
794 | page_length = remain < page_length ? remain : page_length; | |
795 | if (node.allocated) { | |
796 | wmb(); | |
797 | ggtt->base.insert_page(&ggtt->base, | |
798 | i915_gem_object_get_dma_address(obj, offset >> PAGE_SHIFT), | |
799 | node.start, | |
800 | I915_CACHE_NONE, 0); | |
801 | wmb(); | |
802 | } else { | |
803 | page_base += offset & PAGE_MASK; | |
804 | } | |
805 | /* This is a slow read/write as it tries to read from | |
806 | * and write to user memory which may result into page | |
807 | * faults, and so we cannot perform this under struct_mutex. | |
808 | */ | |
809 | if (slow_user_access(ggtt->mappable, page_base, | |
810 | page_offset, user_data, | |
811 | page_length, false)) { | |
812 | ret = -EFAULT; | |
813 | break; | |
814 | } | |
815 | ||
816 | remain -= page_length; | |
817 | user_data += page_length; | |
818 | offset += page_length; | |
819 | } | |
820 | ||
821 | mutex_lock(&dev->struct_mutex); | |
822 | if (ret == 0 && (obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0) { | |
823 | /* The user has modified the object whilst we tried | |
824 | * reading from it, and we now have no idea what domain | |
825 | * the pages should be in. As we have just been touching | |
826 | * them directly, flush everything back to the GTT | |
827 | * domain. | |
828 | */ | |
829 | ret = i915_gem_object_set_to_gtt_domain(obj, false); | |
830 | } | |
831 | ||
832 | out_unpin: | |
833 | if (node.allocated) { | |
834 | wmb(); | |
835 | ggtt->base.clear_range(&ggtt->base, | |
836 | node.start, node.size, | |
837 | true); | |
838 | i915_gem_object_unpin_pages(obj); | |
839 | remove_mappable_node(&node); | |
840 | } else { | |
841 | i915_gem_object_ggtt_unpin(obj); | |
842 | } | |
843 | out: | |
844 | return ret; | |
845 | } | |
846 | ||
eb01459f | 847 | static int |
dbf7bff0 DV |
848 | i915_gem_shmem_pread(struct drm_device *dev, |
849 | struct drm_i915_gem_object *obj, | |
850 | struct drm_i915_gem_pread *args, | |
851 | struct drm_file *file) | |
eb01459f | 852 | { |
8461d226 | 853 | char __user *user_data; |
eb01459f | 854 | ssize_t remain; |
8461d226 | 855 | loff_t offset; |
eb2c0c81 | 856 | int shmem_page_offset, page_length, ret = 0; |
8461d226 | 857 | int obj_do_bit17_swizzling, page_do_bit17_swizzling; |
96d79b52 | 858 | int prefaulted = 0; |
8489731c | 859 | int needs_clflush = 0; |
67d5a50c | 860 | struct sg_page_iter sg_iter; |
eb01459f | 861 | |
6eae0059 | 862 | if (!i915_gem_object_has_struct_page(obj)) |
b50a5371 AS |
863 | return -ENODEV; |
864 | ||
3ed605bc | 865 | user_data = u64_to_user_ptr(args->data_ptr); |
eb01459f EA |
866 | remain = args->size; |
867 | ||
8461d226 | 868 | obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj); |
eb01459f | 869 | |
4c914c0c | 870 | ret = i915_gem_obj_prepare_shmem_read(obj, &needs_clflush); |
f60d7f0c CW |
871 | if (ret) |
872 | return ret; | |
873 | ||
8461d226 | 874 | offset = args->offset; |
eb01459f | 875 | |
67d5a50c ID |
876 | for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, |
877 | offset >> PAGE_SHIFT) { | |
2db76d7c | 878 | struct page *page = sg_page_iter_page(&sg_iter); |
9da3da66 CW |
879 | |
880 | if (remain <= 0) | |
881 | break; | |
882 | ||
eb01459f EA |
883 | /* Operation in this page |
884 | * | |
eb01459f | 885 | * shmem_page_offset = offset within page in shmem file |
eb01459f EA |
886 | * page_length = bytes to copy for this page |
887 | */ | |
c8cbbb8b | 888 | shmem_page_offset = offset_in_page(offset); |
eb01459f EA |
889 | page_length = remain; |
890 | if ((shmem_page_offset + page_length) > PAGE_SIZE) | |
891 | page_length = PAGE_SIZE - shmem_page_offset; | |
eb01459f | 892 | |
8461d226 DV |
893 | page_do_bit17_swizzling = obj_do_bit17_swizzling && |
894 | (page_to_phys(page) & (1 << 17)) != 0; | |
895 | ||
d174bd64 DV |
896 | ret = shmem_pread_fast(page, shmem_page_offset, page_length, |
897 | user_data, page_do_bit17_swizzling, | |
898 | needs_clflush); | |
899 | if (ret == 0) | |
900 | goto next_page; | |
dbf7bff0 | 901 | |
dbf7bff0 DV |
902 | mutex_unlock(&dev->struct_mutex); |
903 | ||
d330a953 | 904 | if (likely(!i915.prefault_disable) && !prefaulted) { |
f56f821f | 905 | ret = fault_in_multipages_writeable(user_data, remain); |
96d79b52 DV |
906 | /* Userspace is tricking us, but we've already clobbered |
907 | * its pages with the prefault and promised to write the | |
908 | * data up to the first fault. Hence ignore any errors | |
909 | * and just continue. */ | |
910 | (void)ret; | |
911 | prefaulted = 1; | |
912 | } | |
eb01459f | 913 | |
d174bd64 DV |
914 | ret = shmem_pread_slow(page, shmem_page_offset, page_length, |
915 | user_data, page_do_bit17_swizzling, | |
916 | needs_clflush); | |
eb01459f | 917 | |
dbf7bff0 | 918 | mutex_lock(&dev->struct_mutex); |
f60d7f0c | 919 | |
f60d7f0c | 920 | if (ret) |
8461d226 | 921 | goto out; |
8461d226 | 922 | |
17793c9a | 923 | next_page: |
eb01459f | 924 | remain -= page_length; |
8461d226 | 925 | user_data += page_length; |
eb01459f EA |
926 | offset += page_length; |
927 | } | |
928 | ||
4f27b75d | 929 | out: |
f60d7f0c CW |
930 | i915_gem_object_unpin_pages(obj); |
931 | ||
eb01459f EA |
932 | return ret; |
933 | } | |
934 | ||
673a394b EA |
935 | /** |
936 | * Reads data from the object referenced by handle. | |
14bb2c11 TU |
937 | * @dev: drm device pointer |
938 | * @data: ioctl data blob | |
939 | * @file: drm file pointer | |
673a394b EA |
940 | * |
941 | * On error, the contents of *data are undefined. | |
942 | */ | |
943 | int | |
944 | i915_gem_pread_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 945 | struct drm_file *file) |
673a394b EA |
946 | { |
947 | struct drm_i915_gem_pread *args = data; | |
05394f39 | 948 | struct drm_i915_gem_object *obj; |
35b62a89 | 949 | int ret = 0; |
673a394b | 950 | |
51311d0a CW |
951 | if (args->size == 0) |
952 | return 0; | |
953 | ||
954 | if (!access_ok(VERIFY_WRITE, | |
3ed605bc | 955 | u64_to_user_ptr(args->data_ptr), |
51311d0a CW |
956 | args->size)) |
957 | return -EFAULT; | |
958 | ||
03ac0642 | 959 | obj = i915_gem_object_lookup(file, args->handle); |
258a5ede CW |
960 | if (!obj) |
961 | return -ENOENT; | |
673a394b | 962 | |
7dcd2499 | 963 | /* Bounds check source. */ |
05394f39 CW |
964 | if (args->offset > obj->base.size || |
965 | args->size > obj->base.size - args->offset) { | |
ce9d419d | 966 | ret = -EINVAL; |
258a5ede | 967 | goto err; |
ce9d419d CW |
968 | } |
969 | ||
db53a302 CW |
970 | trace_i915_gem_object_pread(obj, args->offset, args->size); |
971 | ||
258a5ede CW |
972 | ret = __unsafe_wait_rendering(obj, to_rps_client(file), true); |
973 | if (ret) | |
974 | goto err; | |
975 | ||
976 | ret = i915_mutex_lock_interruptible(dev); | |
977 | if (ret) | |
978 | goto err; | |
979 | ||
dbf7bff0 | 980 | ret = i915_gem_shmem_pread(dev, obj, args, file); |
673a394b | 981 | |
b50a5371 | 982 | /* pread for non shmem backed objects */ |
1dd5b6f2 CW |
983 | if (ret == -EFAULT || ret == -ENODEV) { |
984 | intel_runtime_pm_get(to_i915(dev)); | |
b50a5371 AS |
985 | ret = i915_gem_gtt_pread(dev, obj, args->size, |
986 | args->offset, args->data_ptr); | |
1dd5b6f2 CW |
987 | intel_runtime_pm_put(to_i915(dev)); |
988 | } | |
b50a5371 | 989 | |
f8c417cd | 990 | i915_gem_object_put(obj); |
4f27b75d | 991 | mutex_unlock(&dev->struct_mutex); |
258a5ede CW |
992 | |
993 | return ret; | |
994 | ||
995 | err: | |
996 | i915_gem_object_put_unlocked(obj); | |
eb01459f | 997 | return ret; |
673a394b EA |
998 | } |
999 | ||
0839ccb8 KP |
1000 | /* This is the fast write path which cannot handle |
1001 | * page faults in the source data | |
9b7530cc | 1002 | */ |
0839ccb8 KP |
1003 | |
1004 | static inline int | |
1005 | fast_user_write(struct io_mapping *mapping, | |
1006 | loff_t page_base, int page_offset, | |
1007 | char __user *user_data, | |
1008 | int length) | |
9b7530cc | 1009 | { |
4f0c7cfb BW |
1010 | void __iomem *vaddr_atomic; |
1011 | void *vaddr; | |
0839ccb8 | 1012 | unsigned long unwritten; |
9b7530cc | 1013 | |
3e4d3af5 | 1014 | vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base); |
4f0c7cfb BW |
1015 | /* We can use the cpu mem copy function because this is X86. */ |
1016 | vaddr = (void __force*)vaddr_atomic + page_offset; | |
1017 | unwritten = __copy_from_user_inatomic_nocache(vaddr, | |
0839ccb8 | 1018 | user_data, length); |
3e4d3af5 | 1019 | io_mapping_unmap_atomic(vaddr_atomic); |
fbd5a26d | 1020 | return unwritten; |
0839ccb8 KP |
1021 | } |
1022 | ||
3de09aa3 EA |
1023 | /** |
1024 | * This is the fast pwrite path, where we copy the data directly from the | |
1025 | * user into the GTT, uncached. | |
62f90b38 | 1026 | * @i915: i915 device private data |
14bb2c11 TU |
1027 | * @obj: i915 gem object |
1028 | * @args: pwrite arguments structure | |
1029 | * @file: drm file pointer | |
3de09aa3 | 1030 | */ |
673a394b | 1031 | static int |
4f1959ee | 1032 | i915_gem_gtt_pwrite_fast(struct drm_i915_private *i915, |
05394f39 | 1033 | struct drm_i915_gem_object *obj, |
3de09aa3 | 1034 | struct drm_i915_gem_pwrite *args, |
05394f39 | 1035 | struct drm_file *file) |
673a394b | 1036 | { |
4f1959ee | 1037 | struct i915_ggtt *ggtt = &i915->ggtt; |
b50a5371 | 1038 | struct drm_device *dev = obj->base.dev; |
4f1959ee AS |
1039 | struct drm_mm_node node; |
1040 | uint64_t remain, offset; | |
673a394b | 1041 | char __user *user_data; |
4f1959ee | 1042 | int ret; |
b50a5371 AS |
1043 | bool hit_slow_path = false; |
1044 | ||
1045 | if (obj->tiling_mode != I915_TILING_NONE) | |
1046 | return -EFAULT; | |
935aaa69 | 1047 | |
de895082 CW |
1048 | ret = i915_gem_object_ggtt_pin(obj, NULL, 0, 0, |
1049 | PIN_MAPPABLE | PIN_NONBLOCK); | |
4f1959ee AS |
1050 | if (ret) { |
1051 | ret = insert_mappable_node(i915, &node, PAGE_SIZE); | |
1052 | if (ret) | |
1053 | goto out; | |
1054 | ||
1055 | ret = i915_gem_object_get_pages(obj); | |
1056 | if (ret) { | |
1057 | remove_mappable_node(&node); | |
1058 | goto out; | |
1059 | } | |
1060 | ||
1061 | i915_gem_object_pin_pages(obj); | |
1062 | } else { | |
1063 | node.start = i915_gem_obj_ggtt_offset(obj); | |
1064 | node.allocated = false; | |
b50a5371 AS |
1065 | ret = i915_gem_object_put_fence(obj); |
1066 | if (ret) | |
1067 | goto out_unpin; | |
4f1959ee | 1068 | } |
935aaa69 DV |
1069 | |
1070 | ret = i915_gem_object_set_to_gtt_domain(obj, true); | |
1071 | if (ret) | |
1072 | goto out_unpin; | |
1073 | ||
77a0d1ca | 1074 | intel_fb_obj_invalidate(obj, ORIGIN_GTT); |
4f1959ee | 1075 | obj->dirty = true; |
063e4e6b | 1076 | |
4f1959ee AS |
1077 | user_data = u64_to_user_ptr(args->data_ptr); |
1078 | offset = args->offset; | |
1079 | remain = args->size; | |
1080 | while (remain) { | |
673a394b EA |
1081 | /* Operation in this page |
1082 | * | |
0839ccb8 KP |
1083 | * page_base = page offset within aperture |
1084 | * page_offset = offset within page | |
1085 | * page_length = bytes to copy for this page | |
673a394b | 1086 | */ |
4f1959ee AS |
1087 | u32 page_base = node.start; |
1088 | unsigned page_offset = offset_in_page(offset); | |
1089 | unsigned page_length = PAGE_SIZE - page_offset; | |
1090 | page_length = remain < page_length ? remain : page_length; | |
1091 | if (node.allocated) { | |
1092 | wmb(); /* flush the write before we modify the GGTT */ | |
1093 | ggtt->base.insert_page(&ggtt->base, | |
1094 | i915_gem_object_get_dma_address(obj, offset >> PAGE_SHIFT), | |
1095 | node.start, I915_CACHE_NONE, 0); | |
1096 | wmb(); /* flush modifications to the GGTT (insert_page) */ | |
1097 | } else { | |
1098 | page_base += offset & PAGE_MASK; | |
1099 | } | |
0839ccb8 | 1100 | /* If we get a fault while copying data, then (presumably) our |
3de09aa3 EA |
1101 | * source page isn't available. Return the error and we'll |
1102 | * retry in the slow path. | |
b50a5371 AS |
1103 | * If the object is non-shmem backed, we retry again with the |
1104 | * path that handles page fault. | |
0839ccb8 | 1105 | */ |
72e96d64 | 1106 | if (fast_user_write(ggtt->mappable, page_base, |
935aaa69 | 1107 | page_offset, user_data, page_length)) { |
b50a5371 AS |
1108 | hit_slow_path = true; |
1109 | mutex_unlock(&dev->struct_mutex); | |
1110 | if (slow_user_access(ggtt->mappable, | |
1111 | page_base, | |
1112 | page_offset, user_data, | |
1113 | page_length, true)) { | |
1114 | ret = -EFAULT; | |
1115 | mutex_lock(&dev->struct_mutex); | |
1116 | goto out_flush; | |
1117 | } | |
1118 | ||
1119 | mutex_lock(&dev->struct_mutex); | |
935aaa69 | 1120 | } |
673a394b | 1121 | |
0839ccb8 KP |
1122 | remain -= page_length; |
1123 | user_data += page_length; | |
1124 | offset += page_length; | |
673a394b | 1125 | } |
673a394b | 1126 | |
063e4e6b | 1127 | out_flush: |
b50a5371 AS |
1128 | if (hit_slow_path) { |
1129 | if (ret == 0 && | |
1130 | (obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0) { | |
1131 | /* The user has modified the object whilst we tried | |
1132 | * reading from it, and we now have no idea what domain | |
1133 | * the pages should be in. As we have just been touching | |
1134 | * them directly, flush everything back to the GTT | |
1135 | * domain. | |
1136 | */ | |
1137 | ret = i915_gem_object_set_to_gtt_domain(obj, false); | |
1138 | } | |
1139 | } | |
1140 | ||
de152b62 | 1141 | intel_fb_obj_flush(obj, false, ORIGIN_GTT); |
935aaa69 | 1142 | out_unpin: |
4f1959ee AS |
1143 | if (node.allocated) { |
1144 | wmb(); | |
1145 | ggtt->base.clear_range(&ggtt->base, | |
1146 | node.start, node.size, | |
1147 | true); | |
1148 | i915_gem_object_unpin_pages(obj); | |
1149 | remove_mappable_node(&node); | |
1150 | } else { | |
1151 | i915_gem_object_ggtt_unpin(obj); | |
1152 | } | |
935aaa69 | 1153 | out: |
3de09aa3 | 1154 | return ret; |
673a394b EA |
1155 | } |
1156 | ||
d174bd64 DV |
1157 | /* Per-page copy function for the shmem pwrite fastpath. |
1158 | * Flushes invalid cachelines before writing to the target if | |
1159 | * needs_clflush_before is set and flushes out any written cachelines after | |
1160 | * writing if needs_clflush is set. */ | |
3043c60c | 1161 | static int |
d174bd64 DV |
1162 | shmem_pwrite_fast(struct page *page, int shmem_page_offset, int page_length, |
1163 | char __user *user_data, | |
1164 | bool page_do_bit17_swizzling, | |
1165 | bool needs_clflush_before, | |
1166 | bool needs_clflush_after) | |
673a394b | 1167 | { |
d174bd64 | 1168 | char *vaddr; |
673a394b | 1169 | int ret; |
3de09aa3 | 1170 | |
e7e58eb5 | 1171 | if (unlikely(page_do_bit17_swizzling)) |
d174bd64 | 1172 | return -EINVAL; |
3de09aa3 | 1173 | |
d174bd64 DV |
1174 | vaddr = kmap_atomic(page); |
1175 | if (needs_clflush_before) | |
1176 | drm_clflush_virt_range(vaddr + shmem_page_offset, | |
1177 | page_length); | |
c2831a94 CW |
1178 | ret = __copy_from_user_inatomic(vaddr + shmem_page_offset, |
1179 | user_data, page_length); | |
d174bd64 DV |
1180 | if (needs_clflush_after) |
1181 | drm_clflush_virt_range(vaddr + shmem_page_offset, | |
1182 | page_length); | |
1183 | kunmap_atomic(vaddr); | |
3de09aa3 | 1184 | |
755d2218 | 1185 | return ret ? -EFAULT : 0; |
3de09aa3 EA |
1186 | } |
1187 | ||
d174bd64 DV |
1188 | /* Only difference to the fast-path function is that this can handle bit17 |
1189 | * and uses non-atomic copy and kmap functions. */ | |
3043c60c | 1190 | static int |
d174bd64 DV |
1191 | shmem_pwrite_slow(struct page *page, int shmem_page_offset, int page_length, |
1192 | char __user *user_data, | |
1193 | bool page_do_bit17_swizzling, | |
1194 | bool needs_clflush_before, | |
1195 | bool needs_clflush_after) | |
673a394b | 1196 | { |
d174bd64 DV |
1197 | char *vaddr; |
1198 | int ret; | |
e5281ccd | 1199 | |
d174bd64 | 1200 | vaddr = kmap(page); |
e7e58eb5 | 1201 | if (unlikely(needs_clflush_before || page_do_bit17_swizzling)) |
23c18c71 DV |
1202 | shmem_clflush_swizzled_range(vaddr + shmem_page_offset, |
1203 | page_length, | |
1204 | page_do_bit17_swizzling); | |
d174bd64 DV |
1205 | if (page_do_bit17_swizzling) |
1206 | ret = __copy_from_user_swizzled(vaddr, shmem_page_offset, | |
e5281ccd CW |
1207 | user_data, |
1208 | page_length); | |
d174bd64 DV |
1209 | else |
1210 | ret = __copy_from_user(vaddr + shmem_page_offset, | |
1211 | user_data, | |
1212 | page_length); | |
1213 | if (needs_clflush_after) | |
23c18c71 DV |
1214 | shmem_clflush_swizzled_range(vaddr + shmem_page_offset, |
1215 | page_length, | |
1216 | page_do_bit17_swizzling); | |
d174bd64 | 1217 | kunmap(page); |
40123c1f | 1218 | |
755d2218 | 1219 | return ret ? -EFAULT : 0; |
40123c1f EA |
1220 | } |
1221 | ||
40123c1f | 1222 | static int |
e244a443 DV |
1223 | i915_gem_shmem_pwrite(struct drm_device *dev, |
1224 | struct drm_i915_gem_object *obj, | |
1225 | struct drm_i915_gem_pwrite *args, | |
1226 | struct drm_file *file) | |
40123c1f | 1227 | { |
40123c1f | 1228 | ssize_t remain; |
8c59967c DV |
1229 | loff_t offset; |
1230 | char __user *user_data; | |
eb2c0c81 | 1231 | int shmem_page_offset, page_length, ret = 0; |
8c59967c | 1232 | int obj_do_bit17_swizzling, page_do_bit17_swizzling; |
e244a443 | 1233 | int hit_slowpath = 0; |
58642885 DV |
1234 | int needs_clflush_after = 0; |
1235 | int needs_clflush_before = 0; | |
67d5a50c | 1236 | struct sg_page_iter sg_iter; |
40123c1f | 1237 | |
3ed605bc | 1238 | user_data = u64_to_user_ptr(args->data_ptr); |
40123c1f EA |
1239 | remain = args->size; |
1240 | ||
8c59967c | 1241 | obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj); |
40123c1f | 1242 | |
c13d87ea CW |
1243 | ret = i915_gem_object_wait_rendering(obj, false); |
1244 | if (ret) | |
1245 | return ret; | |
1246 | ||
58642885 DV |
1247 | if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) { |
1248 | /* If we're not in the cpu write domain, set ourself into the gtt | |
1249 | * write domain and manually flush cachelines (if required). This | |
1250 | * optimizes for the case when the gpu will use the data | |
1251 | * right away and we therefore have to clflush anyway. */ | |
2c22569b | 1252 | needs_clflush_after = cpu_write_needs_clflush(obj); |
58642885 | 1253 | } |
c76ce038 CW |
1254 | /* Same trick applies to invalidate partially written cachelines read |
1255 | * before writing. */ | |
1256 | if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) | |
1257 | needs_clflush_before = | |
1258 | !cpu_cache_is_coherent(dev, obj->cache_level); | |
58642885 | 1259 | |
755d2218 CW |
1260 | ret = i915_gem_object_get_pages(obj); |
1261 | if (ret) | |
1262 | return ret; | |
1263 | ||
77a0d1ca | 1264 | intel_fb_obj_invalidate(obj, ORIGIN_CPU); |
063e4e6b | 1265 | |
755d2218 CW |
1266 | i915_gem_object_pin_pages(obj); |
1267 | ||
673a394b | 1268 | offset = args->offset; |
05394f39 | 1269 | obj->dirty = 1; |
673a394b | 1270 | |
67d5a50c ID |
1271 | for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, |
1272 | offset >> PAGE_SHIFT) { | |
2db76d7c | 1273 | struct page *page = sg_page_iter_page(&sg_iter); |
58642885 | 1274 | int partial_cacheline_write; |
e5281ccd | 1275 | |
9da3da66 CW |
1276 | if (remain <= 0) |
1277 | break; | |
1278 | ||
40123c1f EA |
1279 | /* Operation in this page |
1280 | * | |
40123c1f | 1281 | * shmem_page_offset = offset within page in shmem file |
40123c1f EA |
1282 | * page_length = bytes to copy for this page |
1283 | */ | |
c8cbbb8b | 1284 | shmem_page_offset = offset_in_page(offset); |
40123c1f EA |
1285 | |
1286 | page_length = remain; | |
1287 | if ((shmem_page_offset + page_length) > PAGE_SIZE) | |
1288 | page_length = PAGE_SIZE - shmem_page_offset; | |
40123c1f | 1289 | |
58642885 DV |
1290 | /* If we don't overwrite a cacheline completely we need to be |
1291 | * careful to have up-to-date data by first clflushing. Don't | |
1292 | * overcomplicate things and flush the entire patch. */ | |
1293 | partial_cacheline_write = needs_clflush_before && | |
1294 | ((shmem_page_offset | page_length) | |
1295 | & (boot_cpu_data.x86_clflush_size - 1)); | |
1296 | ||
8c59967c DV |
1297 | page_do_bit17_swizzling = obj_do_bit17_swizzling && |
1298 | (page_to_phys(page) & (1 << 17)) != 0; | |
1299 | ||
d174bd64 DV |
1300 | ret = shmem_pwrite_fast(page, shmem_page_offset, page_length, |
1301 | user_data, page_do_bit17_swizzling, | |
1302 | partial_cacheline_write, | |
1303 | needs_clflush_after); | |
1304 | if (ret == 0) | |
1305 | goto next_page; | |
e244a443 DV |
1306 | |
1307 | hit_slowpath = 1; | |
e244a443 | 1308 | mutex_unlock(&dev->struct_mutex); |
d174bd64 DV |
1309 | ret = shmem_pwrite_slow(page, shmem_page_offset, page_length, |
1310 | user_data, page_do_bit17_swizzling, | |
1311 | partial_cacheline_write, | |
1312 | needs_clflush_after); | |
40123c1f | 1313 | |
e244a443 | 1314 | mutex_lock(&dev->struct_mutex); |
755d2218 | 1315 | |
755d2218 | 1316 | if (ret) |
8c59967c | 1317 | goto out; |
8c59967c | 1318 | |
17793c9a | 1319 | next_page: |
40123c1f | 1320 | remain -= page_length; |
8c59967c | 1321 | user_data += page_length; |
40123c1f | 1322 | offset += page_length; |
673a394b EA |
1323 | } |
1324 | ||
fbd5a26d | 1325 | out: |
755d2218 CW |
1326 | i915_gem_object_unpin_pages(obj); |
1327 | ||
e244a443 | 1328 | if (hit_slowpath) { |
8dcf015e DV |
1329 | /* |
1330 | * Fixup: Flush cpu caches in case we didn't flush the dirty | |
1331 | * cachelines in-line while writing and the object moved | |
1332 | * out of the cpu write domain while we've dropped the lock. | |
1333 | */ | |
1334 | if (!needs_clflush_after && | |
1335 | obj->base.write_domain != I915_GEM_DOMAIN_CPU) { | |
000433b6 | 1336 | if (i915_gem_clflush_object(obj, obj->pin_display)) |
ed75a55b | 1337 | needs_clflush_after = true; |
e244a443 | 1338 | } |
8c59967c | 1339 | } |
673a394b | 1340 | |
58642885 | 1341 | if (needs_clflush_after) |
c033666a | 1342 | i915_gem_chipset_flush(to_i915(dev)); |
ed75a55b VS |
1343 | else |
1344 | obj->cache_dirty = true; | |
58642885 | 1345 | |
de152b62 | 1346 | intel_fb_obj_flush(obj, false, ORIGIN_CPU); |
40123c1f | 1347 | return ret; |
673a394b EA |
1348 | } |
1349 | ||
1350 | /** | |
1351 | * Writes data to the object referenced by handle. | |
14bb2c11 TU |
1352 | * @dev: drm device |
1353 | * @data: ioctl data blob | |
1354 | * @file: drm file | |
673a394b EA |
1355 | * |
1356 | * On error, the contents of the buffer that were to be modified are undefined. | |
1357 | */ | |
1358 | int | |
1359 | i915_gem_pwrite_ioctl(struct drm_device *dev, void *data, | |
fbd5a26d | 1360 | struct drm_file *file) |
673a394b | 1361 | { |
fac5e23e | 1362 | struct drm_i915_private *dev_priv = to_i915(dev); |
673a394b | 1363 | struct drm_i915_gem_pwrite *args = data; |
05394f39 | 1364 | struct drm_i915_gem_object *obj; |
51311d0a CW |
1365 | int ret; |
1366 | ||
1367 | if (args->size == 0) | |
1368 | return 0; | |
1369 | ||
1370 | if (!access_ok(VERIFY_READ, | |
3ed605bc | 1371 | u64_to_user_ptr(args->data_ptr), |
51311d0a CW |
1372 | args->size)) |
1373 | return -EFAULT; | |
1374 | ||
d330a953 | 1375 | if (likely(!i915.prefault_disable)) { |
3ed605bc | 1376 | ret = fault_in_multipages_readable(u64_to_user_ptr(args->data_ptr), |
0b74b508 XZ |
1377 | args->size); |
1378 | if (ret) | |
1379 | return -EFAULT; | |
1380 | } | |
673a394b | 1381 | |
03ac0642 | 1382 | obj = i915_gem_object_lookup(file, args->handle); |
258a5ede CW |
1383 | if (!obj) |
1384 | return -ENOENT; | |
673a394b | 1385 | |
7dcd2499 | 1386 | /* Bounds check destination. */ |
05394f39 CW |
1387 | if (args->offset > obj->base.size || |
1388 | args->size > obj->base.size - args->offset) { | |
ce9d419d | 1389 | ret = -EINVAL; |
258a5ede | 1390 | goto err; |
ce9d419d CW |
1391 | } |
1392 | ||
db53a302 CW |
1393 | trace_i915_gem_object_pwrite(obj, args->offset, args->size); |
1394 | ||
258a5ede CW |
1395 | ret = __unsafe_wait_rendering(obj, to_rps_client(file), false); |
1396 | if (ret) | |
1397 | goto err; | |
1398 | ||
1399 | intel_runtime_pm_get(dev_priv); | |
1400 | ||
1401 | ret = i915_mutex_lock_interruptible(dev); | |
1402 | if (ret) | |
1403 | goto err_rpm; | |
1404 | ||
935aaa69 | 1405 | ret = -EFAULT; |
673a394b EA |
1406 | /* We can only do the GTT pwrite on untiled buffers, as otherwise |
1407 | * it would end up going through the fenced access, and we'll get | |
1408 | * different detiling behavior between reading and writing. | |
1409 | * pread/pwrite currently are reading and writing from the CPU | |
1410 | * perspective, requiring manual detiling by the client. | |
1411 | */ | |
6eae0059 CW |
1412 | if (!i915_gem_object_has_struct_page(obj) || |
1413 | cpu_write_needs_clflush(obj)) { | |
4f1959ee | 1414 | ret = i915_gem_gtt_pwrite_fast(dev_priv, obj, args, file); |
935aaa69 DV |
1415 | /* Note that the gtt paths might fail with non-page-backed user |
1416 | * pointers (e.g. gtt mappings when moving data between | |
1417 | * textures). Fallback to the shmem path in that case. */ | |
fbd5a26d | 1418 | } |
673a394b | 1419 | |
d1054ee4 | 1420 | if (ret == -EFAULT || ret == -ENOSPC) { |
6a2c4232 CW |
1421 | if (obj->phys_handle) |
1422 | ret = i915_gem_phys_pwrite(obj, args, file); | |
6eae0059 | 1423 | else if (i915_gem_object_has_struct_page(obj)) |
6a2c4232 | 1424 | ret = i915_gem_shmem_pwrite(dev, obj, args, file); |
b50a5371 AS |
1425 | else |
1426 | ret = -ENODEV; | |
6a2c4232 | 1427 | } |
5c0480f2 | 1428 | |
f8c417cd | 1429 | i915_gem_object_put(obj); |
fbd5a26d | 1430 | mutex_unlock(&dev->struct_mutex); |
5d77d9c5 ID |
1431 | intel_runtime_pm_put(dev_priv); |
1432 | ||
673a394b | 1433 | return ret; |
258a5ede CW |
1434 | |
1435 | err_rpm: | |
1436 | intel_runtime_pm_put(dev_priv); | |
1437 | err: | |
1438 | i915_gem_object_put_unlocked(obj); | |
1439 | return ret; | |
673a394b EA |
1440 | } |
1441 | ||
aeecc969 CW |
1442 | static enum fb_op_origin |
1443 | write_origin(struct drm_i915_gem_object *obj, unsigned domain) | |
1444 | { | |
1445 | return domain == I915_GEM_DOMAIN_GTT && !obj->has_wc_mmap ? | |
1446 | ORIGIN_GTT : ORIGIN_CPU; | |
1447 | } | |
1448 | ||
673a394b | 1449 | /** |
2ef7eeaa EA |
1450 | * Called when user space prepares to use an object with the CPU, either |
1451 | * through the mmap ioctl's mapping or a GTT mapping. | |
14bb2c11 TU |
1452 | * @dev: drm device |
1453 | * @data: ioctl data blob | |
1454 | * @file: drm file | |
673a394b EA |
1455 | */ |
1456 | int | |
1457 | i915_gem_set_domain_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 1458 | struct drm_file *file) |
673a394b EA |
1459 | { |
1460 | struct drm_i915_gem_set_domain *args = data; | |
05394f39 | 1461 | struct drm_i915_gem_object *obj; |
2ef7eeaa EA |
1462 | uint32_t read_domains = args->read_domains; |
1463 | uint32_t write_domain = args->write_domain; | |
673a394b EA |
1464 | int ret; |
1465 | ||
2ef7eeaa | 1466 | /* Only handle setting domains to types used by the CPU. */ |
b8f9096d | 1467 | if ((write_domain | read_domains) & I915_GEM_GPU_DOMAINS) |
2ef7eeaa EA |
1468 | return -EINVAL; |
1469 | ||
1470 | /* Having something in the write domain implies it's in the read | |
1471 | * domain, and only that read domain. Enforce that in the request. | |
1472 | */ | |
1473 | if (write_domain != 0 && read_domains != write_domain) | |
1474 | return -EINVAL; | |
1475 | ||
03ac0642 | 1476 | obj = i915_gem_object_lookup(file, args->handle); |
b8f9096d CW |
1477 | if (!obj) |
1478 | return -ENOENT; | |
673a394b | 1479 | |
3236f57a CW |
1480 | /* Try to flush the object off the GPU without holding the lock. |
1481 | * We will repeat the flush holding the lock in the normal manner | |
1482 | * to catch cases where we are gazumped. | |
1483 | */ | |
b8f9096d CW |
1484 | ret = __unsafe_wait_rendering(obj, to_rps_client(file), !write_domain); |
1485 | if (ret) | |
1486 | goto err; | |
1487 | ||
1488 | ret = i915_mutex_lock_interruptible(dev); | |
3236f57a | 1489 | if (ret) |
b8f9096d | 1490 | goto err; |
3236f57a | 1491 | |
43566ded | 1492 | if (read_domains & I915_GEM_DOMAIN_GTT) |
2ef7eeaa | 1493 | ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0); |
43566ded | 1494 | else |
e47c68e9 | 1495 | ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0); |
2ef7eeaa | 1496 | |
031b698a | 1497 | if (write_domain != 0) |
aeecc969 | 1498 | intel_fb_obj_invalidate(obj, write_origin(obj, write_domain)); |
031b698a | 1499 | |
f8c417cd | 1500 | i915_gem_object_put(obj); |
673a394b EA |
1501 | mutex_unlock(&dev->struct_mutex); |
1502 | return ret; | |
b8f9096d CW |
1503 | |
1504 | err: | |
1505 | i915_gem_object_put_unlocked(obj); | |
1506 | return ret; | |
673a394b EA |
1507 | } |
1508 | ||
1509 | /** | |
1510 | * Called when user space has done writes to this buffer | |
14bb2c11 TU |
1511 | * @dev: drm device |
1512 | * @data: ioctl data blob | |
1513 | * @file: drm file | |
673a394b EA |
1514 | */ |
1515 | int | |
1516 | i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 1517 | struct drm_file *file) |
673a394b EA |
1518 | { |
1519 | struct drm_i915_gem_sw_finish *args = data; | |
05394f39 | 1520 | struct drm_i915_gem_object *obj; |
c21724cc | 1521 | int err = 0; |
1d7cfea1 | 1522 | |
03ac0642 | 1523 | obj = i915_gem_object_lookup(file, args->handle); |
c21724cc CW |
1524 | if (!obj) |
1525 | return -ENOENT; | |
673a394b | 1526 | |
673a394b | 1527 | /* Pinned buffers may be scanout, so flush the cache */ |
c21724cc CW |
1528 | if (READ_ONCE(obj->pin_display)) { |
1529 | err = i915_mutex_lock_interruptible(dev); | |
1530 | if (!err) { | |
1531 | i915_gem_object_flush_cpu_write_domain(obj); | |
1532 | mutex_unlock(&dev->struct_mutex); | |
1533 | } | |
1534 | } | |
e47c68e9 | 1535 | |
c21724cc CW |
1536 | i915_gem_object_put_unlocked(obj); |
1537 | return err; | |
673a394b EA |
1538 | } |
1539 | ||
1540 | /** | |
14bb2c11 TU |
1541 | * i915_gem_mmap_ioctl - Maps the contents of an object, returning the address |
1542 | * it is mapped to. | |
1543 | * @dev: drm device | |
1544 | * @data: ioctl data blob | |
1545 | * @file: drm file | |
673a394b EA |
1546 | * |
1547 | * While the mapping holds a reference on the contents of the object, it doesn't | |
1548 | * imply a ref on the object itself. | |
34367381 DV |
1549 | * |
1550 | * IMPORTANT: | |
1551 | * | |
1552 | * DRM driver writers who look a this function as an example for how to do GEM | |
1553 | * mmap support, please don't implement mmap support like here. The modern way | |
1554 | * to implement DRM mmap support is with an mmap offset ioctl (like | |
1555 | * i915_gem_mmap_gtt) and then using the mmap syscall on the DRM fd directly. | |
1556 | * That way debug tooling like valgrind will understand what's going on, hiding | |
1557 | * the mmap call in a driver private ioctl will break that. The i915 driver only | |
1558 | * does cpu mmaps this way because we didn't know better. | |
673a394b EA |
1559 | */ |
1560 | int | |
1561 | i915_gem_mmap_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 1562 | struct drm_file *file) |
673a394b EA |
1563 | { |
1564 | struct drm_i915_gem_mmap *args = data; | |
03ac0642 | 1565 | struct drm_i915_gem_object *obj; |
673a394b EA |
1566 | unsigned long addr; |
1567 | ||
1816f923 AG |
1568 | if (args->flags & ~(I915_MMAP_WC)) |
1569 | return -EINVAL; | |
1570 | ||
568a58e5 | 1571 | if (args->flags & I915_MMAP_WC && !boot_cpu_has(X86_FEATURE_PAT)) |
1816f923 AG |
1572 | return -ENODEV; |
1573 | ||
03ac0642 CW |
1574 | obj = i915_gem_object_lookup(file, args->handle); |
1575 | if (!obj) | |
bf79cb91 | 1576 | return -ENOENT; |
673a394b | 1577 | |
1286ff73 DV |
1578 | /* prime objects have no backing filp to GEM mmap |
1579 | * pages from. | |
1580 | */ | |
03ac0642 | 1581 | if (!obj->base.filp) { |
34911fd3 | 1582 | i915_gem_object_put_unlocked(obj); |
1286ff73 DV |
1583 | return -EINVAL; |
1584 | } | |
1585 | ||
03ac0642 | 1586 | addr = vm_mmap(obj->base.filp, 0, args->size, |
673a394b EA |
1587 | PROT_READ | PROT_WRITE, MAP_SHARED, |
1588 | args->offset); | |
1816f923 AG |
1589 | if (args->flags & I915_MMAP_WC) { |
1590 | struct mm_struct *mm = current->mm; | |
1591 | struct vm_area_struct *vma; | |
1592 | ||
80a89a5e | 1593 | if (down_write_killable(&mm->mmap_sem)) { |
34911fd3 | 1594 | i915_gem_object_put_unlocked(obj); |
80a89a5e MH |
1595 | return -EINTR; |
1596 | } | |
1816f923 AG |
1597 | vma = find_vma(mm, addr); |
1598 | if (vma) | |
1599 | vma->vm_page_prot = | |
1600 | pgprot_writecombine(vm_get_page_prot(vma->vm_flags)); | |
1601 | else | |
1602 | addr = -ENOMEM; | |
1603 | up_write(&mm->mmap_sem); | |
aeecc969 CW |
1604 | |
1605 | /* This may race, but that's ok, it only gets set */ | |
03ac0642 | 1606 | WRITE_ONCE(obj->has_wc_mmap, true); |
1816f923 | 1607 | } |
34911fd3 | 1608 | i915_gem_object_put_unlocked(obj); |
673a394b EA |
1609 | if (IS_ERR((void *)addr)) |
1610 | return addr; | |
1611 | ||
1612 | args->addr_ptr = (uint64_t) addr; | |
1613 | ||
1614 | return 0; | |
1615 | } | |
1616 | ||
de151cf6 JB |
1617 | /** |
1618 | * i915_gem_fault - fault a page into the GTT | |
d9072a3e GT |
1619 | * @vma: VMA in question |
1620 | * @vmf: fault info | |
de151cf6 JB |
1621 | * |
1622 | * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped | |
1623 | * from userspace. The fault handler takes care of binding the object to | |
1624 | * the GTT (if needed), allocating and programming a fence register (again, | |
1625 | * only if needed based on whether the old reg is still valid or the object | |
1626 | * is tiled) and inserting a new PTE into the faulting process. | |
1627 | * | |
1628 | * Note that the faulting process may involve evicting existing objects | |
1629 | * from the GTT and/or fence registers to make room. So performance may | |
1630 | * suffer if the GTT working set is large or there are few fence registers | |
1631 | * left. | |
1632 | */ | |
1633 | int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf) | |
1634 | { | |
05394f39 CW |
1635 | struct drm_i915_gem_object *obj = to_intel_bo(vma->vm_private_data); |
1636 | struct drm_device *dev = obj->base.dev; | |
72e96d64 JL |
1637 | struct drm_i915_private *dev_priv = to_i915(dev); |
1638 | struct i915_ggtt *ggtt = &dev_priv->ggtt; | |
c5ad54cf | 1639 | struct i915_ggtt_view view = i915_ggtt_view_normal; |
b8f9096d | 1640 | bool write = !!(vmf->flags & FAULT_FLAG_WRITE); |
de151cf6 JB |
1641 | pgoff_t page_offset; |
1642 | unsigned long pfn; | |
b8f9096d | 1643 | int ret; |
f65c9168 | 1644 | |
de151cf6 JB |
1645 | /* We don't use vmf->pgoff since that has the fake offset */ |
1646 | page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >> | |
1647 | PAGE_SHIFT; | |
1648 | ||
db53a302 CW |
1649 | trace_i915_gem_object_fault(obj, page_offset, true, write); |
1650 | ||
6e4930f6 | 1651 | /* Try to flush the object off the GPU first without holding the lock. |
b8f9096d | 1652 | * Upon acquiring the lock, we will perform our sanity checks and then |
6e4930f6 CW |
1653 | * repeat the flush holding the lock in the normal manner to catch cases |
1654 | * where we are gazumped. | |
1655 | */ | |
b8f9096d | 1656 | ret = __unsafe_wait_rendering(obj, NULL, !write); |
6e4930f6 | 1657 | if (ret) |
b8f9096d CW |
1658 | goto err; |
1659 | ||
1660 | intel_runtime_pm_get(dev_priv); | |
1661 | ||
1662 | ret = i915_mutex_lock_interruptible(dev); | |
1663 | if (ret) | |
1664 | goto err_rpm; | |
6e4930f6 | 1665 | |
eb119bd6 CW |
1666 | /* Access to snoopable pages through the GTT is incoherent. */ |
1667 | if (obj->cache_level != I915_CACHE_NONE && !HAS_LLC(dev)) { | |
ddeff6ee | 1668 | ret = -EFAULT; |
b8f9096d | 1669 | goto err_unlock; |
eb119bd6 CW |
1670 | } |
1671 | ||
c5ad54cf | 1672 | /* Use a partial view if the object is bigger than the aperture. */ |
72e96d64 | 1673 | if (obj->base.size >= ggtt->mappable_end && |
e7ded2d7 | 1674 | obj->tiling_mode == I915_TILING_NONE) { |
c5ad54cf | 1675 | static const unsigned int chunk_size = 256; // 1 MiB |
e7ded2d7 | 1676 | |
c5ad54cf JL |
1677 | memset(&view, 0, sizeof(view)); |
1678 | view.type = I915_GGTT_VIEW_PARTIAL; | |
1679 | view.params.partial.offset = rounddown(page_offset, chunk_size); | |
1680 | view.params.partial.size = | |
1681 | min_t(unsigned int, | |
1682 | chunk_size, | |
1683 | (vma->vm_end - vma->vm_start)/PAGE_SIZE - | |
1684 | view.params.partial.offset); | |
1685 | } | |
1686 | ||
1687 | /* Now pin it into the GTT if needed */ | |
91b2db6f | 1688 | ret = i915_gem_object_ggtt_pin(obj, &view, 0, 0, PIN_MAPPABLE); |
c9839303 | 1689 | if (ret) |
b8f9096d | 1690 | goto err_unlock; |
4a684a41 | 1691 | |
c9839303 CW |
1692 | ret = i915_gem_object_set_to_gtt_domain(obj, write); |
1693 | if (ret) | |
b8f9096d | 1694 | goto err_unpin; |
74898d7e | 1695 | |
06d98131 | 1696 | ret = i915_gem_object_get_fence(obj); |
d9e86c0e | 1697 | if (ret) |
b8f9096d | 1698 | goto err_unpin; |
7d1c4804 | 1699 | |
b90b91d8 | 1700 | /* Finally, remap it using the new GTT offset */ |
72e96d64 | 1701 | pfn = ggtt->mappable_base + |
c5ad54cf | 1702 | i915_gem_obj_ggtt_offset_view(obj, &view); |
f343c5f6 | 1703 | pfn >>= PAGE_SHIFT; |
de151cf6 | 1704 | |
c5ad54cf JL |
1705 | if (unlikely(view.type == I915_GGTT_VIEW_PARTIAL)) { |
1706 | /* Overriding existing pages in partial view does not cause | |
1707 | * us any trouble as TLBs are still valid because the fault | |
1708 | * is due to userspace losing part of the mapping or never | |
1709 | * having accessed it before (at this partials' range). | |
1710 | */ | |
1711 | unsigned long base = vma->vm_start + | |
1712 | (view.params.partial.offset << PAGE_SHIFT); | |
1713 | unsigned int i; | |
b90b91d8 | 1714 | |
c5ad54cf JL |
1715 | for (i = 0; i < view.params.partial.size; i++) { |
1716 | ret = vm_insert_pfn(vma, base + i * PAGE_SIZE, pfn + i); | |
b90b91d8 CW |
1717 | if (ret) |
1718 | break; | |
1719 | } | |
1720 | ||
1721 | obj->fault_mappable = true; | |
c5ad54cf JL |
1722 | } else { |
1723 | if (!obj->fault_mappable) { | |
1724 | unsigned long size = min_t(unsigned long, | |
1725 | vma->vm_end - vma->vm_start, | |
1726 | obj->base.size); | |
1727 | int i; | |
1728 | ||
1729 | for (i = 0; i < size >> PAGE_SHIFT; i++) { | |
1730 | ret = vm_insert_pfn(vma, | |
1731 | (unsigned long)vma->vm_start + i * PAGE_SIZE, | |
1732 | pfn + i); | |
1733 | if (ret) | |
1734 | break; | |
1735 | } | |
1736 | ||
1737 | obj->fault_mappable = true; | |
1738 | } else | |
1739 | ret = vm_insert_pfn(vma, | |
1740 | (unsigned long)vmf->virtual_address, | |
1741 | pfn + page_offset); | |
1742 | } | |
b8f9096d | 1743 | err_unpin: |
c5ad54cf | 1744 | i915_gem_object_ggtt_unpin_view(obj, &view); |
b8f9096d | 1745 | err_unlock: |
de151cf6 | 1746 | mutex_unlock(&dev->struct_mutex); |
b8f9096d CW |
1747 | err_rpm: |
1748 | intel_runtime_pm_put(dev_priv); | |
1749 | err: | |
de151cf6 | 1750 | switch (ret) { |
d9bc7e9f | 1751 | case -EIO: |
2232f031 DV |
1752 | /* |
1753 | * We eat errors when the gpu is terminally wedged to avoid | |
1754 | * userspace unduly crashing (gl has no provisions for mmaps to | |
1755 | * fail). But any other -EIO isn't ours (e.g. swap in failure) | |
1756 | * and so needs to be reported. | |
1757 | */ | |
1758 | if (!i915_terminally_wedged(&dev_priv->gpu_error)) { | |
f65c9168 PZ |
1759 | ret = VM_FAULT_SIGBUS; |
1760 | break; | |
1761 | } | |
045e769a | 1762 | case -EAGAIN: |
571c608d DV |
1763 | /* |
1764 | * EAGAIN means the gpu is hung and we'll wait for the error | |
1765 | * handler to reset everything when re-faulting in | |
1766 | * i915_mutex_lock_interruptible. | |
d9bc7e9f | 1767 | */ |
c715089f CW |
1768 | case 0: |
1769 | case -ERESTARTSYS: | |
bed636ab | 1770 | case -EINTR: |
e79e0fe3 DR |
1771 | case -EBUSY: |
1772 | /* | |
1773 | * EBUSY is ok: this just means that another thread | |
1774 | * already did the job. | |
1775 | */ | |
f65c9168 PZ |
1776 | ret = VM_FAULT_NOPAGE; |
1777 | break; | |
de151cf6 | 1778 | case -ENOMEM: |
f65c9168 PZ |
1779 | ret = VM_FAULT_OOM; |
1780 | break; | |
a7c2e1aa | 1781 | case -ENOSPC: |
45d67817 | 1782 | case -EFAULT: |
f65c9168 PZ |
1783 | ret = VM_FAULT_SIGBUS; |
1784 | break; | |
de151cf6 | 1785 | default: |
a7c2e1aa | 1786 | WARN_ONCE(ret, "unhandled error in i915_gem_fault: %i\n", ret); |
f65c9168 PZ |
1787 | ret = VM_FAULT_SIGBUS; |
1788 | break; | |
de151cf6 | 1789 | } |
f65c9168 | 1790 | return ret; |
de151cf6 JB |
1791 | } |
1792 | ||
901782b2 CW |
1793 | /** |
1794 | * i915_gem_release_mmap - remove physical page mappings | |
1795 | * @obj: obj in question | |
1796 | * | |
af901ca1 | 1797 | * Preserve the reservation of the mmapping with the DRM core code, but |
901782b2 CW |
1798 | * relinquish ownership of the pages back to the system. |
1799 | * | |
1800 | * It is vital that we remove the page mapping if we have mapped a tiled | |
1801 | * object through the GTT and then lose the fence register due to | |
1802 | * resource pressure. Similarly if the object has been moved out of the | |
1803 | * aperture, than pages mapped into userspace must be revoked. Removing the | |
1804 | * mapping will then trigger a page fault on the next user access, allowing | |
1805 | * fixup by i915_gem_fault(). | |
1806 | */ | |
d05ca301 | 1807 | void |
05394f39 | 1808 | i915_gem_release_mmap(struct drm_i915_gem_object *obj) |
901782b2 | 1809 | { |
349f2ccf CW |
1810 | /* Serialisation between user GTT access and our code depends upon |
1811 | * revoking the CPU's PTE whilst the mutex is held. The next user | |
1812 | * pagefault then has to wait until we release the mutex. | |
1813 | */ | |
1814 | lockdep_assert_held(&obj->base.dev->struct_mutex); | |
1815 | ||
6299f992 CW |
1816 | if (!obj->fault_mappable) |
1817 | return; | |
901782b2 | 1818 | |
6796cb16 DH |
1819 | drm_vma_node_unmap(&obj->base.vma_node, |
1820 | obj->base.dev->anon_inode->i_mapping); | |
349f2ccf CW |
1821 | |
1822 | /* Ensure that the CPU's PTE are revoked and there are not outstanding | |
1823 | * memory transactions from userspace before we return. The TLB | |
1824 | * flushing implied above by changing the PTE above *should* be | |
1825 | * sufficient, an extra barrier here just provides us with a bit | |
1826 | * of paranoid documentation about our requirement to serialise | |
1827 | * memory writes before touching registers / GSM. | |
1828 | */ | |
1829 | wmb(); | |
1830 | ||
6299f992 | 1831 | obj->fault_mappable = false; |
901782b2 CW |
1832 | } |
1833 | ||
eedd10f4 CW |
1834 | void |
1835 | i915_gem_release_all_mmaps(struct drm_i915_private *dev_priv) | |
1836 | { | |
1837 | struct drm_i915_gem_object *obj; | |
1838 | ||
1839 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) | |
1840 | i915_gem_release_mmap(obj); | |
1841 | } | |
1842 | ||
ad1a7d20 CW |
1843 | /** |
1844 | * i915_gem_get_ggtt_size - return required global GTT size for an object | |
a9f1481f | 1845 | * @dev_priv: i915 device |
ad1a7d20 CW |
1846 | * @size: object size |
1847 | * @tiling_mode: tiling mode | |
1848 | * | |
1849 | * Return the required global GTT size for an object, taking into account | |
1850 | * potential fence register mapping. | |
1851 | */ | |
a9f1481f CW |
1852 | u64 i915_gem_get_ggtt_size(struct drm_i915_private *dev_priv, |
1853 | u64 size, int tiling_mode) | |
92b88aeb | 1854 | { |
ad1a7d20 | 1855 | u64 ggtt_size; |
92b88aeb | 1856 | |
ad1a7d20 CW |
1857 | GEM_BUG_ON(size == 0); |
1858 | ||
a9f1481f | 1859 | if (INTEL_GEN(dev_priv) >= 4 || |
e28f8711 CW |
1860 | tiling_mode == I915_TILING_NONE) |
1861 | return size; | |
92b88aeb CW |
1862 | |
1863 | /* Previous chips need a power-of-two fence region when tiling */ | |
a9f1481f | 1864 | if (IS_GEN3(dev_priv)) |
ad1a7d20 | 1865 | ggtt_size = 1024*1024; |
92b88aeb | 1866 | else |
ad1a7d20 | 1867 | ggtt_size = 512*1024; |
92b88aeb | 1868 | |
ad1a7d20 CW |
1869 | while (ggtt_size < size) |
1870 | ggtt_size <<= 1; | |
92b88aeb | 1871 | |
ad1a7d20 | 1872 | return ggtt_size; |
92b88aeb CW |
1873 | } |
1874 | ||
de151cf6 | 1875 | /** |
ad1a7d20 | 1876 | * i915_gem_get_ggtt_alignment - return required global GTT alignment |
a9f1481f | 1877 | * @dev_priv: i915 device |
14bb2c11 TU |
1878 | * @size: object size |
1879 | * @tiling_mode: tiling mode | |
ad1a7d20 | 1880 | * @fenced: is fenced alignment required or not |
de151cf6 | 1881 | * |
ad1a7d20 | 1882 | * Return the required global GTT alignment for an object, taking into account |
5e783301 | 1883 | * potential fence register mapping. |
de151cf6 | 1884 | */ |
a9f1481f | 1885 | u64 i915_gem_get_ggtt_alignment(struct drm_i915_private *dev_priv, u64 size, |
ad1a7d20 | 1886 | int tiling_mode, bool fenced) |
de151cf6 | 1887 | { |
ad1a7d20 CW |
1888 | GEM_BUG_ON(size == 0); |
1889 | ||
de151cf6 JB |
1890 | /* |
1891 | * Minimum alignment is 4k (GTT page size), but might be greater | |
1892 | * if a fence register is needed for the object. | |
1893 | */ | |
a9f1481f | 1894 | if (INTEL_GEN(dev_priv) >= 4 || (!fenced && IS_G33(dev_priv)) || |
e28f8711 | 1895 | tiling_mode == I915_TILING_NONE) |
de151cf6 JB |
1896 | return 4096; |
1897 | ||
a00b10c3 CW |
1898 | /* |
1899 | * Previous chips need to be aligned to the size of the smallest | |
1900 | * fence register that can contain the object. | |
1901 | */ | |
a9f1481f | 1902 | return i915_gem_get_ggtt_size(dev_priv, size, tiling_mode); |
a00b10c3 CW |
1903 | } |
1904 | ||
d8cb5086 CW |
1905 | static int i915_gem_object_create_mmap_offset(struct drm_i915_gem_object *obj) |
1906 | { | |
fac5e23e | 1907 | struct drm_i915_private *dev_priv = to_i915(obj->base.dev); |
f3f6184c | 1908 | int err; |
da494d7c | 1909 | |
f3f6184c CW |
1910 | err = drm_gem_create_mmap_offset(&obj->base); |
1911 | if (!err) | |
1912 | return 0; | |
d8cb5086 | 1913 | |
f3f6184c CW |
1914 | /* We can idle the GPU locklessly to flush stale objects, but in order |
1915 | * to claim that space for ourselves, we need to take the big | |
1916 | * struct_mutex to free the requests+objects and allocate our slot. | |
d8cb5086 | 1917 | */ |
f3f6184c CW |
1918 | err = i915_gem_wait_for_idle(dev_priv, true); |
1919 | if (err) | |
1920 | return err; | |
1921 | ||
1922 | err = i915_mutex_lock_interruptible(&dev_priv->drm); | |
1923 | if (!err) { | |
1924 | i915_gem_retire_requests(dev_priv); | |
1925 | err = drm_gem_create_mmap_offset(&obj->base); | |
1926 | mutex_unlock(&dev_priv->drm.struct_mutex); | |
1927 | } | |
da494d7c | 1928 | |
f3f6184c | 1929 | return err; |
d8cb5086 CW |
1930 | } |
1931 | ||
1932 | static void i915_gem_object_free_mmap_offset(struct drm_i915_gem_object *obj) | |
1933 | { | |
d8cb5086 CW |
1934 | drm_gem_free_mmap_offset(&obj->base); |
1935 | } | |
1936 | ||
da6b51d0 | 1937 | int |
ff72145b DA |
1938 | i915_gem_mmap_gtt(struct drm_file *file, |
1939 | struct drm_device *dev, | |
da6b51d0 | 1940 | uint32_t handle, |
ff72145b | 1941 | uint64_t *offset) |
de151cf6 | 1942 | { |
05394f39 | 1943 | struct drm_i915_gem_object *obj; |
de151cf6 JB |
1944 | int ret; |
1945 | ||
03ac0642 | 1946 | obj = i915_gem_object_lookup(file, handle); |
f3f6184c CW |
1947 | if (!obj) |
1948 | return -ENOENT; | |
ab18282d | 1949 | |
d8cb5086 | 1950 | ret = i915_gem_object_create_mmap_offset(obj); |
f3f6184c CW |
1951 | if (ret == 0) |
1952 | *offset = drm_vma_node_offset_addr(&obj->base.vma_node); | |
de151cf6 | 1953 | |
f3f6184c | 1954 | i915_gem_object_put_unlocked(obj); |
1d7cfea1 | 1955 | return ret; |
de151cf6 JB |
1956 | } |
1957 | ||
ff72145b DA |
1958 | /** |
1959 | * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing | |
1960 | * @dev: DRM device | |
1961 | * @data: GTT mapping ioctl data | |
1962 | * @file: GEM object info | |
1963 | * | |
1964 | * Simply returns the fake offset to userspace so it can mmap it. | |
1965 | * The mmap call will end up in drm_gem_mmap(), which will set things | |
1966 | * up so we can get faults in the handler above. | |
1967 | * | |
1968 | * The fault handler will take care of binding the object into the GTT | |
1969 | * (since it may have been evicted to make room for something), allocating | |
1970 | * a fence register, and mapping the appropriate aperture address into | |
1971 | * userspace. | |
1972 | */ | |
1973 | int | |
1974 | i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data, | |
1975 | struct drm_file *file) | |
1976 | { | |
1977 | struct drm_i915_gem_mmap_gtt *args = data; | |
1978 | ||
da6b51d0 | 1979 | return i915_gem_mmap_gtt(file, dev, args->handle, &args->offset); |
ff72145b DA |
1980 | } |
1981 | ||
225067ee DV |
1982 | /* Immediately discard the backing storage */ |
1983 | static void | |
1984 | i915_gem_object_truncate(struct drm_i915_gem_object *obj) | |
e5281ccd | 1985 | { |
4d6294bf | 1986 | i915_gem_object_free_mmap_offset(obj); |
1286ff73 | 1987 | |
4d6294bf CW |
1988 | if (obj->base.filp == NULL) |
1989 | return; | |
e5281ccd | 1990 | |
225067ee DV |
1991 | /* Our goal here is to return as much of the memory as |
1992 | * is possible back to the system as we are called from OOM. | |
1993 | * To do this we must instruct the shmfs to drop all of its | |
1994 | * backing pages, *now*. | |
1995 | */ | |
5537252b | 1996 | shmem_truncate_range(file_inode(obj->base.filp), 0, (loff_t)-1); |
225067ee DV |
1997 | obj->madv = __I915_MADV_PURGED; |
1998 | } | |
e5281ccd | 1999 | |
5537252b CW |
2000 | /* Try to discard unwanted pages */ |
2001 | static void | |
2002 | i915_gem_object_invalidate(struct drm_i915_gem_object *obj) | |
225067ee | 2003 | { |
5537252b CW |
2004 | struct address_space *mapping; |
2005 | ||
2006 | switch (obj->madv) { | |
2007 | case I915_MADV_DONTNEED: | |
2008 | i915_gem_object_truncate(obj); | |
2009 | case __I915_MADV_PURGED: | |
2010 | return; | |
2011 | } | |
2012 | ||
2013 | if (obj->base.filp == NULL) | |
2014 | return; | |
2015 | ||
2016 | mapping = file_inode(obj->base.filp)->i_mapping, | |
2017 | invalidate_mapping_pages(mapping, 0, (loff_t)-1); | |
e5281ccd CW |
2018 | } |
2019 | ||
5cdf5881 | 2020 | static void |
05394f39 | 2021 | i915_gem_object_put_pages_gtt(struct drm_i915_gem_object *obj) |
673a394b | 2022 | { |
85d1225e DG |
2023 | struct sgt_iter sgt_iter; |
2024 | struct page *page; | |
90797e6d | 2025 | int ret; |
1286ff73 | 2026 | |
05394f39 | 2027 | BUG_ON(obj->madv == __I915_MADV_PURGED); |
673a394b | 2028 | |
6c085a72 | 2029 | ret = i915_gem_object_set_to_cpu_domain(obj, true); |
f4457ae7 | 2030 | if (WARN_ON(ret)) { |
6c085a72 CW |
2031 | /* In the event of a disaster, abandon all caches and |
2032 | * hope for the best. | |
2033 | */ | |
2c22569b | 2034 | i915_gem_clflush_object(obj, true); |
6c085a72 CW |
2035 | obj->base.read_domains = obj->base.write_domain = I915_GEM_DOMAIN_CPU; |
2036 | } | |
2037 | ||
e2273302 ID |
2038 | i915_gem_gtt_finish_object(obj); |
2039 | ||
6dacfd2f | 2040 | if (i915_gem_object_needs_bit17_swizzle(obj)) |
280b713b EA |
2041 | i915_gem_object_save_bit_17_swizzle(obj); |
2042 | ||
05394f39 CW |
2043 | if (obj->madv == I915_MADV_DONTNEED) |
2044 | obj->dirty = 0; | |
3ef94daa | 2045 | |
85d1225e | 2046 | for_each_sgt_page(page, sgt_iter, obj->pages) { |
05394f39 | 2047 | if (obj->dirty) |
9da3da66 | 2048 | set_page_dirty(page); |
3ef94daa | 2049 | |
05394f39 | 2050 | if (obj->madv == I915_MADV_WILLNEED) |
9da3da66 | 2051 | mark_page_accessed(page); |
3ef94daa | 2052 | |
09cbfeaf | 2053 | put_page(page); |
3ef94daa | 2054 | } |
05394f39 | 2055 | obj->dirty = 0; |
673a394b | 2056 | |
9da3da66 CW |
2057 | sg_free_table(obj->pages); |
2058 | kfree(obj->pages); | |
37e680a1 | 2059 | } |
6c085a72 | 2060 | |
dd624afd | 2061 | int |
37e680a1 CW |
2062 | i915_gem_object_put_pages(struct drm_i915_gem_object *obj) |
2063 | { | |
2064 | const struct drm_i915_gem_object_ops *ops = obj->ops; | |
2065 | ||
2f745ad3 | 2066 | if (obj->pages == NULL) |
37e680a1 CW |
2067 | return 0; |
2068 | ||
a5570178 CW |
2069 | if (obj->pages_pin_count) |
2070 | return -EBUSY; | |
2071 | ||
15717de2 | 2072 | GEM_BUG_ON(obj->bind_count); |
3e123027 | 2073 | |
a2165e31 CW |
2074 | /* ->put_pages might need to allocate memory for the bit17 swizzle |
2075 | * array, hence protect them from being reaped by removing them from gtt | |
2076 | * lists early. */ | |
35c20a60 | 2077 | list_del(&obj->global_list); |
a2165e31 | 2078 | |
0a798eb9 | 2079 | if (obj->mapping) { |
fb8621d3 CW |
2080 | if (is_vmalloc_addr(obj->mapping)) |
2081 | vunmap(obj->mapping); | |
2082 | else | |
2083 | kunmap(kmap_to_page(obj->mapping)); | |
0a798eb9 CW |
2084 | obj->mapping = NULL; |
2085 | } | |
2086 | ||
37e680a1 | 2087 | ops->put_pages(obj); |
05394f39 | 2088 | obj->pages = NULL; |
37e680a1 | 2089 | |
5537252b | 2090 | i915_gem_object_invalidate(obj); |
6c085a72 CW |
2091 | |
2092 | return 0; | |
2093 | } | |
2094 | ||
37e680a1 | 2095 | static int |
6c085a72 | 2096 | i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj) |
e5281ccd | 2097 | { |
fac5e23e | 2098 | struct drm_i915_private *dev_priv = to_i915(obj->base.dev); |
e5281ccd CW |
2099 | int page_count, i; |
2100 | struct address_space *mapping; | |
9da3da66 CW |
2101 | struct sg_table *st; |
2102 | struct scatterlist *sg; | |
85d1225e | 2103 | struct sgt_iter sgt_iter; |
e5281ccd | 2104 | struct page *page; |
90797e6d | 2105 | unsigned long last_pfn = 0; /* suppress gcc warning */ |
e2273302 | 2106 | int ret; |
6c085a72 | 2107 | gfp_t gfp; |
e5281ccd | 2108 | |
6c085a72 CW |
2109 | /* Assert that the object is not currently in any GPU domain. As it |
2110 | * wasn't in the GTT, there shouldn't be any way it could have been in | |
2111 | * a GPU cache | |
2112 | */ | |
2113 | BUG_ON(obj->base.read_domains & I915_GEM_GPU_DOMAINS); | |
2114 | BUG_ON(obj->base.write_domain & I915_GEM_GPU_DOMAINS); | |
2115 | ||
9da3da66 CW |
2116 | st = kmalloc(sizeof(*st), GFP_KERNEL); |
2117 | if (st == NULL) | |
2118 | return -ENOMEM; | |
2119 | ||
05394f39 | 2120 | page_count = obj->base.size / PAGE_SIZE; |
9da3da66 | 2121 | if (sg_alloc_table(st, page_count, GFP_KERNEL)) { |
9da3da66 | 2122 | kfree(st); |
e5281ccd | 2123 | return -ENOMEM; |
9da3da66 | 2124 | } |
e5281ccd | 2125 | |
9da3da66 CW |
2126 | /* Get the list of pages out of our struct file. They'll be pinned |
2127 | * at this point until we release them. | |
2128 | * | |
2129 | * Fail silently without starting the shrinker | |
2130 | */ | |
496ad9aa | 2131 | mapping = file_inode(obj->base.filp)->i_mapping; |
c62d2555 | 2132 | gfp = mapping_gfp_constraint(mapping, ~(__GFP_IO | __GFP_RECLAIM)); |
d0164adc | 2133 | gfp |= __GFP_NORETRY | __GFP_NOWARN; |
90797e6d ID |
2134 | sg = st->sgl; |
2135 | st->nents = 0; | |
2136 | for (i = 0; i < page_count; i++) { | |
6c085a72 CW |
2137 | page = shmem_read_mapping_page_gfp(mapping, i, gfp); |
2138 | if (IS_ERR(page)) { | |
21ab4e74 CW |
2139 | i915_gem_shrink(dev_priv, |
2140 | page_count, | |
2141 | I915_SHRINK_BOUND | | |
2142 | I915_SHRINK_UNBOUND | | |
2143 | I915_SHRINK_PURGEABLE); | |
6c085a72 CW |
2144 | page = shmem_read_mapping_page_gfp(mapping, i, gfp); |
2145 | } | |
2146 | if (IS_ERR(page)) { | |
2147 | /* We've tried hard to allocate the memory by reaping | |
2148 | * our own buffer, now let the real VM do its job and | |
2149 | * go down in flames if truly OOM. | |
2150 | */ | |
6c085a72 | 2151 | i915_gem_shrink_all(dev_priv); |
f461d1be | 2152 | page = shmem_read_mapping_page(mapping, i); |
e2273302 ID |
2153 | if (IS_ERR(page)) { |
2154 | ret = PTR_ERR(page); | |
6c085a72 | 2155 | goto err_pages; |
e2273302 | 2156 | } |
6c085a72 | 2157 | } |
426729dc KRW |
2158 | #ifdef CONFIG_SWIOTLB |
2159 | if (swiotlb_nr_tbl()) { | |
2160 | st->nents++; | |
2161 | sg_set_page(sg, page, PAGE_SIZE, 0); | |
2162 | sg = sg_next(sg); | |
2163 | continue; | |
2164 | } | |
2165 | #endif | |
90797e6d ID |
2166 | if (!i || page_to_pfn(page) != last_pfn + 1) { |
2167 | if (i) | |
2168 | sg = sg_next(sg); | |
2169 | st->nents++; | |
2170 | sg_set_page(sg, page, PAGE_SIZE, 0); | |
2171 | } else { | |
2172 | sg->length += PAGE_SIZE; | |
2173 | } | |
2174 | last_pfn = page_to_pfn(page); | |
3bbbe706 DV |
2175 | |
2176 | /* Check that the i965g/gm workaround works. */ | |
2177 | WARN_ON((gfp & __GFP_DMA32) && (last_pfn >= 0x00100000UL)); | |
e5281ccd | 2178 | } |
426729dc KRW |
2179 | #ifdef CONFIG_SWIOTLB |
2180 | if (!swiotlb_nr_tbl()) | |
2181 | #endif | |
2182 | sg_mark_end(sg); | |
74ce6b6c CW |
2183 | obj->pages = st; |
2184 | ||
e2273302 ID |
2185 | ret = i915_gem_gtt_prepare_object(obj); |
2186 | if (ret) | |
2187 | goto err_pages; | |
2188 | ||
6dacfd2f | 2189 | if (i915_gem_object_needs_bit17_swizzle(obj)) |
e5281ccd CW |
2190 | i915_gem_object_do_bit_17_swizzle(obj); |
2191 | ||
656bfa3a DV |
2192 | if (obj->tiling_mode != I915_TILING_NONE && |
2193 | dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES) | |
2194 | i915_gem_object_pin_pages(obj); | |
2195 | ||
e5281ccd CW |
2196 | return 0; |
2197 | ||
2198 | err_pages: | |
90797e6d | 2199 | sg_mark_end(sg); |
85d1225e DG |
2200 | for_each_sgt_page(page, sgt_iter, st) |
2201 | put_page(page); | |
9da3da66 CW |
2202 | sg_free_table(st); |
2203 | kfree(st); | |
0820baf3 CW |
2204 | |
2205 | /* shmemfs first checks if there is enough memory to allocate the page | |
2206 | * and reports ENOSPC should there be insufficient, along with the usual | |
2207 | * ENOMEM for a genuine allocation failure. | |
2208 | * | |
2209 | * We use ENOSPC in our driver to mean that we have run out of aperture | |
2210 | * space and so want to translate the error from shmemfs back to our | |
2211 | * usual understanding of ENOMEM. | |
2212 | */ | |
e2273302 ID |
2213 | if (ret == -ENOSPC) |
2214 | ret = -ENOMEM; | |
2215 | ||
2216 | return ret; | |
673a394b EA |
2217 | } |
2218 | ||
37e680a1 CW |
2219 | /* Ensure that the associated pages are gathered from the backing storage |
2220 | * and pinned into our object. i915_gem_object_get_pages() may be called | |
2221 | * multiple times before they are released by a single call to | |
2222 | * i915_gem_object_put_pages() - once the pages are no longer referenced | |
2223 | * either as a result of memory pressure (reaping pages under the shrinker) | |
2224 | * or as the object is itself released. | |
2225 | */ | |
2226 | int | |
2227 | i915_gem_object_get_pages(struct drm_i915_gem_object *obj) | |
2228 | { | |
fac5e23e | 2229 | struct drm_i915_private *dev_priv = to_i915(obj->base.dev); |
37e680a1 CW |
2230 | const struct drm_i915_gem_object_ops *ops = obj->ops; |
2231 | int ret; | |
2232 | ||
2f745ad3 | 2233 | if (obj->pages) |
37e680a1 CW |
2234 | return 0; |
2235 | ||
43e28f09 | 2236 | if (obj->madv != I915_MADV_WILLNEED) { |
bd9b6a4e | 2237 | DRM_DEBUG("Attempting to obtain a purgeable object\n"); |
8c99e57d | 2238 | return -EFAULT; |
43e28f09 CW |
2239 | } |
2240 | ||
a5570178 CW |
2241 | BUG_ON(obj->pages_pin_count); |
2242 | ||
37e680a1 CW |
2243 | ret = ops->get_pages(obj); |
2244 | if (ret) | |
2245 | return ret; | |
2246 | ||
35c20a60 | 2247 | list_add_tail(&obj->global_list, &dev_priv->mm.unbound_list); |
ee286370 CW |
2248 | |
2249 | obj->get_page.sg = obj->pages->sgl; | |
2250 | obj->get_page.last = 0; | |
2251 | ||
37e680a1 | 2252 | return 0; |
673a394b EA |
2253 | } |
2254 | ||
dd6034c6 DG |
2255 | /* The 'mapping' part of i915_gem_object_pin_map() below */ |
2256 | static void *i915_gem_object_map(const struct drm_i915_gem_object *obj) | |
2257 | { | |
2258 | unsigned long n_pages = obj->base.size >> PAGE_SHIFT; | |
2259 | struct sg_table *sgt = obj->pages; | |
85d1225e DG |
2260 | struct sgt_iter sgt_iter; |
2261 | struct page *page; | |
b338fa47 DG |
2262 | struct page *stack_pages[32]; |
2263 | struct page **pages = stack_pages; | |
dd6034c6 DG |
2264 | unsigned long i = 0; |
2265 | void *addr; | |
2266 | ||
2267 | /* A single page can always be kmapped */ | |
2268 | if (n_pages == 1) | |
2269 | return kmap(sg_page(sgt->sgl)); | |
2270 | ||
b338fa47 DG |
2271 | if (n_pages > ARRAY_SIZE(stack_pages)) { |
2272 | /* Too big for stack -- allocate temporary array instead */ | |
2273 | pages = drm_malloc_gfp(n_pages, sizeof(*pages), GFP_TEMPORARY); | |
2274 | if (!pages) | |
2275 | return NULL; | |
2276 | } | |
dd6034c6 | 2277 | |
85d1225e DG |
2278 | for_each_sgt_page(page, sgt_iter, sgt) |
2279 | pages[i++] = page; | |
dd6034c6 DG |
2280 | |
2281 | /* Check that we have the expected number of pages */ | |
2282 | GEM_BUG_ON(i != n_pages); | |
2283 | ||
2284 | addr = vmap(pages, n_pages, 0, PAGE_KERNEL); | |
2285 | ||
b338fa47 DG |
2286 | if (pages != stack_pages) |
2287 | drm_free_large(pages); | |
dd6034c6 DG |
2288 | |
2289 | return addr; | |
2290 | } | |
2291 | ||
2292 | /* get, pin, and map the pages of the object into kernel space */ | |
0a798eb9 CW |
2293 | void *i915_gem_object_pin_map(struct drm_i915_gem_object *obj) |
2294 | { | |
2295 | int ret; | |
2296 | ||
2297 | lockdep_assert_held(&obj->base.dev->struct_mutex); | |
2298 | ||
2299 | ret = i915_gem_object_get_pages(obj); | |
2300 | if (ret) | |
2301 | return ERR_PTR(ret); | |
2302 | ||
2303 | i915_gem_object_pin_pages(obj); | |
2304 | ||
dd6034c6 DG |
2305 | if (!obj->mapping) { |
2306 | obj->mapping = i915_gem_object_map(obj); | |
2307 | if (!obj->mapping) { | |
0a798eb9 CW |
2308 | i915_gem_object_unpin_pages(obj); |
2309 | return ERR_PTR(-ENOMEM); | |
2310 | } | |
2311 | } | |
2312 | ||
2313 | return obj->mapping; | |
2314 | } | |
2315 | ||
b4716185 | 2316 | static void |
fa545cbf CW |
2317 | i915_gem_object_retire__write(struct i915_gem_active *active, |
2318 | struct drm_i915_gem_request *request) | |
e2d05a8b | 2319 | { |
fa545cbf CW |
2320 | struct drm_i915_gem_object *obj = |
2321 | container_of(active, struct drm_i915_gem_object, last_write); | |
b4716185 | 2322 | |
de152b62 | 2323 | intel_fb_obj_flush(obj, true, ORIGIN_CS); |
e2d05a8b BW |
2324 | } |
2325 | ||
caea7476 | 2326 | static void |
fa545cbf CW |
2327 | i915_gem_object_retire__read(struct i915_gem_active *active, |
2328 | struct drm_i915_gem_request *request) | |
ce44b0ea | 2329 | { |
fa545cbf CW |
2330 | int idx = request->engine->id; |
2331 | struct drm_i915_gem_object *obj = | |
2332 | container_of(active, struct drm_i915_gem_object, last_read[idx]); | |
ce44b0ea | 2333 | |
573adb39 | 2334 | GEM_BUG_ON(!i915_gem_object_has_active_engine(obj, idx)); |
b4716185 | 2335 | |
573adb39 CW |
2336 | i915_gem_object_clear_active(obj, idx); |
2337 | if (i915_gem_object_is_active(obj)) | |
b4716185 | 2338 | return; |
caea7476 | 2339 | |
6c246959 CW |
2340 | /* Bump our place on the bound list to keep it roughly in LRU order |
2341 | * so that we don't steal from recently used but inactive objects | |
2342 | * (unless we are forced to ofc!) | |
2343 | */ | |
b0decaf7 CW |
2344 | if (obj->bind_count) |
2345 | list_move_tail(&obj->global_list, | |
2346 | &request->i915->mm.bound_list); | |
caea7476 | 2347 | |
f8c417cd | 2348 | i915_gem_object_put(obj); |
c8725f3d CW |
2349 | } |
2350 | ||
7b4d3a16 | 2351 | static bool i915_context_is_banned(const struct i915_gem_context *ctx) |
be62acb4 | 2352 | { |
44e2c070 | 2353 | unsigned long elapsed; |
be62acb4 | 2354 | |
44e2c070 | 2355 | if (ctx->hang_stats.banned) |
be62acb4 MK |
2356 | return true; |
2357 | ||
7b4d3a16 | 2358 | elapsed = get_seconds() - ctx->hang_stats.guilty_ts; |
676fa572 CW |
2359 | if (ctx->hang_stats.ban_period_seconds && |
2360 | elapsed <= ctx->hang_stats.ban_period_seconds) { | |
7b4d3a16 CW |
2361 | DRM_DEBUG("context hanging too fast, banning!\n"); |
2362 | return true; | |
be62acb4 MK |
2363 | } |
2364 | ||
2365 | return false; | |
2366 | } | |
2367 | ||
7b4d3a16 | 2368 | static void i915_set_reset_status(struct i915_gem_context *ctx, |
b6b0fac0 | 2369 | const bool guilty) |
aa60c664 | 2370 | { |
7b4d3a16 | 2371 | struct i915_ctx_hang_stats *hs = &ctx->hang_stats; |
44e2c070 MK |
2372 | |
2373 | if (guilty) { | |
7b4d3a16 | 2374 | hs->banned = i915_context_is_banned(ctx); |
44e2c070 MK |
2375 | hs->batch_active++; |
2376 | hs->guilty_ts = get_seconds(); | |
2377 | } else { | |
2378 | hs->batch_pending++; | |
aa60c664 MK |
2379 | } |
2380 | } | |
2381 | ||
8d9fc7fd | 2382 | struct drm_i915_gem_request * |
0bc40be8 | 2383 | i915_gem_find_active_request(struct intel_engine_cs *engine) |
9375e446 | 2384 | { |
4db080f9 CW |
2385 | struct drm_i915_gem_request *request; |
2386 | ||
f69a02c9 CW |
2387 | /* We are called by the error capture and reset at a random |
2388 | * point in time. In particular, note that neither is crucially | |
2389 | * ordered with an interrupt. After a hang, the GPU is dead and we | |
2390 | * assume that no more writes can happen (we waited long enough for | |
2391 | * all writes that were in transaction to be flushed) - adding an | |
2392 | * extra delay for a recent interrupt is pointless. Hence, we do | |
2393 | * not need an engine->irq_seqno_barrier() before the seqno reads. | |
2394 | */ | |
efdf7c06 | 2395 | list_for_each_entry(request, &engine->request_list, link) { |
f69a02c9 | 2396 | if (i915_gem_request_completed(request)) |
4db080f9 | 2397 | continue; |
aa60c664 | 2398 | |
b6b0fac0 | 2399 | return request; |
4db080f9 | 2400 | } |
b6b0fac0 MK |
2401 | |
2402 | return NULL; | |
2403 | } | |
2404 | ||
7b4d3a16 | 2405 | static void i915_gem_reset_engine_status(struct intel_engine_cs *engine) |
b6b0fac0 MK |
2406 | { |
2407 | struct drm_i915_gem_request *request; | |
2408 | bool ring_hung; | |
2409 | ||
0bc40be8 | 2410 | request = i915_gem_find_active_request(engine); |
b6b0fac0 MK |
2411 | if (request == NULL) |
2412 | return; | |
2413 | ||
0bc40be8 | 2414 | ring_hung = engine->hangcheck.score >= HANGCHECK_SCORE_RING_HUNG; |
b6b0fac0 | 2415 | |
7b4d3a16 | 2416 | i915_set_reset_status(request->ctx, ring_hung); |
efdf7c06 | 2417 | list_for_each_entry_continue(request, &engine->request_list, link) |
7b4d3a16 | 2418 | i915_set_reset_status(request->ctx, false); |
4db080f9 | 2419 | } |
aa60c664 | 2420 | |
7b4d3a16 | 2421 | static void i915_gem_reset_engine_cleanup(struct intel_engine_cs *engine) |
4db080f9 | 2422 | { |
dcff85c8 | 2423 | struct drm_i915_gem_request *request; |
7e37f889 | 2424 | struct intel_ring *ring; |
608c1a52 | 2425 | |
dcff85c8 CW |
2426 | request = i915_gem_active_peek(&engine->last_request, |
2427 | &engine->i915->drm.struct_mutex); | |
2428 | ||
c4b0930b CW |
2429 | /* Mark all pending requests as complete so that any concurrent |
2430 | * (lockless) lookup doesn't try and wait upon the request as we | |
2431 | * reset it. | |
2432 | */ | |
dcff85c8 CW |
2433 | if (request) |
2434 | intel_engine_init_seqno(engine, request->fence.seqno); | |
c4b0930b | 2435 | |
dcb4c12a OM |
2436 | /* |
2437 | * Clear the execlists queue up before freeing the requests, as those | |
2438 | * are the ones that keep the context and ringbuffer backing objects | |
2439 | * pinned in place. | |
2440 | */ | |
dcb4c12a | 2441 | |
7de1691a | 2442 | if (i915.enable_execlists) { |
27af5eea TU |
2443 | /* Ensure irq handler finishes or is cancelled. */ |
2444 | tasklet_kill(&engine->irq_tasklet); | |
1197b4f2 | 2445 | |
e39d42fa | 2446 | intel_execlists_cancel_requests(engine); |
dcb4c12a OM |
2447 | } |
2448 | ||
1d62beea BW |
2449 | /* |
2450 | * We must free the requests after all the corresponding objects have | |
2451 | * been moved off active lists. Which is the same order as the normal | |
2452 | * retire_requests function does. This is important if object hold | |
2453 | * implicit references on things like e.g. ppgtt address spaces through | |
2454 | * the request. | |
2455 | */ | |
dcff85c8 | 2456 | if (request) |
05235c53 | 2457 | i915_gem_request_retire_upto(request); |
dcff85c8 | 2458 | GEM_BUG_ON(intel_engine_is_active(engine)); |
608c1a52 CW |
2459 | |
2460 | /* Having flushed all requests from all queues, we know that all | |
2461 | * ringbuffers must now be empty. However, since we do not reclaim | |
2462 | * all space when retiring the request (to prevent HEADs colliding | |
2463 | * with rapid ringbuffer wraparound) the amount of available space | |
2464 | * upon reset is less than when we start. Do one more pass over | |
2465 | * all the ringbuffers to reset last_retired_head. | |
2466 | */ | |
7e37f889 CW |
2467 | list_for_each_entry(ring, &engine->buffers, link) { |
2468 | ring->last_retired_head = ring->tail; | |
2469 | intel_ring_update_space(ring); | |
608c1a52 | 2470 | } |
2ed53a94 | 2471 | |
b913b33c | 2472 | engine->i915->gt.active_engines &= ~intel_engine_flag(engine); |
673a394b EA |
2473 | } |
2474 | ||
069efc1d | 2475 | void i915_gem_reset(struct drm_device *dev) |
673a394b | 2476 | { |
fac5e23e | 2477 | struct drm_i915_private *dev_priv = to_i915(dev); |
e2f80391 | 2478 | struct intel_engine_cs *engine; |
673a394b | 2479 | |
4db080f9 CW |
2480 | /* |
2481 | * Before we free the objects from the requests, we need to inspect | |
2482 | * them for finding the guilty party. As the requests only borrow | |
2483 | * their reference to the objects, the inspection must be done first. | |
2484 | */ | |
b4ac5afc | 2485 | for_each_engine(engine, dev_priv) |
7b4d3a16 | 2486 | i915_gem_reset_engine_status(engine); |
4db080f9 | 2487 | |
b4ac5afc | 2488 | for_each_engine(engine, dev_priv) |
7b4d3a16 | 2489 | i915_gem_reset_engine_cleanup(engine); |
b913b33c | 2490 | mod_delayed_work(dev_priv->wq, &dev_priv->gt.idle_work, 0); |
dfaae392 | 2491 | |
acce9ffa BW |
2492 | i915_gem_context_reset(dev); |
2493 | ||
19b2dbde | 2494 | i915_gem_restore_fences(dev); |
673a394b EA |
2495 | } |
2496 | ||
75ef9da2 | 2497 | static void |
673a394b EA |
2498 | i915_gem_retire_work_handler(struct work_struct *work) |
2499 | { | |
b29c19b6 | 2500 | struct drm_i915_private *dev_priv = |
67d97da3 | 2501 | container_of(work, typeof(*dev_priv), gt.retire_work.work); |
91c8a326 | 2502 | struct drm_device *dev = &dev_priv->drm; |
673a394b | 2503 | |
891b48cf | 2504 | /* Come back later if the device is busy... */ |
b29c19b6 | 2505 | if (mutex_trylock(&dev->struct_mutex)) { |
67d97da3 | 2506 | i915_gem_retire_requests(dev_priv); |
b29c19b6 | 2507 | mutex_unlock(&dev->struct_mutex); |
673a394b | 2508 | } |
67d97da3 CW |
2509 | |
2510 | /* Keep the retire handler running until we are finally idle. | |
2511 | * We do not need to do this test under locking as in the worst-case | |
2512 | * we queue the retire worker once too often. | |
2513 | */ | |
c9615613 CW |
2514 | if (READ_ONCE(dev_priv->gt.awake)) { |
2515 | i915_queue_hangcheck(dev_priv); | |
67d97da3 CW |
2516 | queue_delayed_work(dev_priv->wq, |
2517 | &dev_priv->gt.retire_work, | |
bcb45086 | 2518 | round_jiffies_up_relative(HZ)); |
c9615613 | 2519 | } |
b29c19b6 | 2520 | } |
0a58705b | 2521 | |
b29c19b6 CW |
2522 | static void |
2523 | i915_gem_idle_work_handler(struct work_struct *work) | |
2524 | { | |
2525 | struct drm_i915_private *dev_priv = | |
67d97da3 | 2526 | container_of(work, typeof(*dev_priv), gt.idle_work.work); |
91c8a326 | 2527 | struct drm_device *dev = &dev_priv->drm; |
b4ac5afc | 2528 | struct intel_engine_cs *engine; |
67d97da3 CW |
2529 | unsigned int stuck_engines; |
2530 | bool rearm_hangcheck; | |
2531 | ||
2532 | if (!READ_ONCE(dev_priv->gt.awake)) | |
2533 | return; | |
2534 | ||
2535 | if (READ_ONCE(dev_priv->gt.active_engines)) | |
2536 | return; | |
2537 | ||
2538 | rearm_hangcheck = | |
2539 | cancel_delayed_work_sync(&dev_priv->gpu_error.hangcheck_work); | |
2540 | ||
2541 | if (!mutex_trylock(&dev->struct_mutex)) { | |
2542 | /* Currently busy, come back later */ | |
2543 | mod_delayed_work(dev_priv->wq, | |
2544 | &dev_priv->gt.idle_work, | |
2545 | msecs_to_jiffies(50)); | |
2546 | goto out_rearm; | |
2547 | } | |
2548 | ||
2549 | if (dev_priv->gt.active_engines) | |
2550 | goto out_unlock; | |
b29c19b6 | 2551 | |
b4ac5afc | 2552 | for_each_engine(engine, dev_priv) |
67d97da3 | 2553 | i915_gem_batch_pool_fini(&engine->batch_pool); |
35c94185 | 2554 | |
67d97da3 CW |
2555 | GEM_BUG_ON(!dev_priv->gt.awake); |
2556 | dev_priv->gt.awake = false; | |
2557 | rearm_hangcheck = false; | |
30ecad77 | 2558 | |
2529d570 CW |
2559 | /* As we have disabled hangcheck, we need to unstick any waiters still |
2560 | * hanging around. However, as we may be racing against the interrupt | |
2561 | * handler or the waiters themselves, we skip enabling the fake-irq. | |
2562 | */ | |
67d97da3 | 2563 | stuck_engines = intel_kick_waiters(dev_priv); |
2529d570 CW |
2564 | if (unlikely(stuck_engines)) |
2565 | DRM_DEBUG_DRIVER("kicked stuck waiters (%x)...missed irq?\n", | |
2566 | stuck_engines); | |
35c94185 | 2567 | |
67d97da3 CW |
2568 | if (INTEL_GEN(dev_priv) >= 6) |
2569 | gen6_rps_idle(dev_priv); | |
2570 | intel_runtime_pm_put(dev_priv); | |
2571 | out_unlock: | |
2572 | mutex_unlock(&dev->struct_mutex); | |
b29c19b6 | 2573 | |
67d97da3 CW |
2574 | out_rearm: |
2575 | if (rearm_hangcheck) { | |
2576 | GEM_BUG_ON(!dev_priv->gt.awake); | |
2577 | i915_queue_hangcheck(dev_priv); | |
35c94185 | 2578 | } |
673a394b EA |
2579 | } |
2580 | ||
b1f788c6 CW |
2581 | void i915_gem_close_object(struct drm_gem_object *gem, struct drm_file *file) |
2582 | { | |
2583 | struct drm_i915_gem_object *obj = to_intel_bo(gem); | |
2584 | struct drm_i915_file_private *fpriv = file->driver_priv; | |
2585 | struct i915_vma *vma, *vn; | |
2586 | ||
2587 | mutex_lock(&obj->base.dev->struct_mutex); | |
2588 | list_for_each_entry_safe(vma, vn, &obj->vma_list, obj_link) | |
2589 | if (vma->vm->file == fpriv) | |
2590 | i915_vma_close(vma); | |
2591 | mutex_unlock(&obj->base.dev->struct_mutex); | |
2592 | } | |
2593 | ||
23ba4fd0 BW |
2594 | /** |
2595 | * i915_gem_wait_ioctl - implements DRM_IOCTL_I915_GEM_WAIT | |
14bb2c11 TU |
2596 | * @dev: drm device pointer |
2597 | * @data: ioctl data blob | |
2598 | * @file: drm file pointer | |
23ba4fd0 BW |
2599 | * |
2600 | * Returns 0 if successful, else an error is returned with the remaining time in | |
2601 | * the timeout parameter. | |
2602 | * -ETIME: object is still busy after timeout | |
2603 | * -ERESTARTSYS: signal interrupted the wait | |
2604 | * -ENONENT: object doesn't exist | |
2605 | * Also possible, but rare: | |
2606 | * -EAGAIN: GPU wedged | |
2607 | * -ENOMEM: damn | |
2608 | * -ENODEV: Internal IRQ fail | |
2609 | * -E?: The add request failed | |
2610 | * | |
2611 | * The wait ioctl with a timeout of 0 reimplements the busy ioctl. With any | |
2612 | * non-zero timeout parameter the wait ioctl will wait for the given number of | |
2613 | * nanoseconds on an object becoming unbusy. Since the wait itself does so | |
2614 | * without holding struct_mutex the object may become re-busied before this | |
2615 | * function completes. A similar but shorter * race condition exists in the busy | |
2616 | * ioctl | |
2617 | */ | |
2618 | int | |
2619 | i915_gem_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *file) | |
2620 | { | |
2621 | struct drm_i915_gem_wait *args = data; | |
033d549b | 2622 | struct intel_rps_client *rps = to_rps_client(file); |
23ba4fd0 | 2623 | struct drm_i915_gem_object *obj; |
033d549b CW |
2624 | unsigned long active; |
2625 | int idx, ret = 0; | |
23ba4fd0 | 2626 | |
11b5d511 DV |
2627 | if (args->flags != 0) |
2628 | return -EINVAL; | |
2629 | ||
03ac0642 | 2630 | obj = i915_gem_object_lookup(file, args->bo_handle); |
033d549b | 2631 | if (!obj) |
23ba4fd0 | 2632 | return -ENOENT; |
23ba4fd0 | 2633 | |
033d549b CW |
2634 | active = __I915_BO_ACTIVE(obj); |
2635 | for_each_active(active, idx) { | |
2636 | s64 *timeout = args->timeout_ns >= 0 ? &args->timeout_ns : NULL; | |
2637 | ret = i915_gem_active_wait_unlocked(&obj->last_read[idx], true, | |
2638 | timeout, rps); | |
2639 | if (ret) | |
2640 | break; | |
b4716185 CW |
2641 | } |
2642 | ||
033d549b | 2643 | i915_gem_object_put_unlocked(obj); |
ff865885 | 2644 | return ret; |
23ba4fd0 BW |
2645 | } |
2646 | ||
b4716185 | 2647 | static int |
fa545cbf | 2648 | __i915_gem_object_sync(struct drm_i915_gem_request *to, |
8e637178 | 2649 | struct drm_i915_gem_request *from) |
b4716185 | 2650 | { |
b4716185 CW |
2651 | int ret; |
2652 | ||
8e637178 | 2653 | if (to->engine == from->engine) |
b4716185 CW |
2654 | return 0; |
2655 | ||
39df9190 | 2656 | if (!i915.semaphores) { |
776f3236 CW |
2657 | ret = i915_wait_request(from, |
2658 | from->i915->mm.interruptible, | |
2659 | NULL, | |
2660 | NO_WAITBOOST); | |
b4716185 CW |
2661 | if (ret) |
2662 | return ret; | |
b4716185 | 2663 | } else { |
8e637178 | 2664 | int idx = intel_engine_sync_index(from->engine, to->engine); |
ddf07be7 | 2665 | if (from->fence.seqno <= from->engine->semaphore.sync_seqno[idx]) |
b4716185 CW |
2666 | return 0; |
2667 | ||
8e637178 | 2668 | trace_i915_gem_ring_sync_to(to, from); |
ddf07be7 | 2669 | ret = to->engine->semaphore.sync_to(to, from); |
b4716185 CW |
2670 | if (ret) |
2671 | return ret; | |
2672 | ||
ddf07be7 | 2673 | from->engine->semaphore.sync_seqno[idx] = from->fence.seqno; |
b4716185 CW |
2674 | } |
2675 | ||
2676 | return 0; | |
2677 | } | |
2678 | ||
5816d648 BW |
2679 | /** |
2680 | * i915_gem_object_sync - sync an object to a ring. | |
2681 | * | |
2682 | * @obj: object which may be in use on another ring. | |
8e637178 | 2683 | * @to: request we are wishing to use |
5816d648 BW |
2684 | * |
2685 | * This code is meant to abstract object synchronization with the GPU. | |
8e637178 CW |
2686 | * Conceptually we serialise writes between engines inside the GPU. |
2687 | * We only allow one engine to write into a buffer at any time, but | |
2688 | * multiple readers. To ensure each has a coherent view of memory, we must: | |
b4716185 CW |
2689 | * |
2690 | * - If there is an outstanding write request to the object, the new | |
2691 | * request must wait for it to complete (either CPU or in hw, requests | |
2692 | * on the same ring will be naturally ordered). | |
2693 | * | |
2694 | * - If we are a write request (pending_write_domain is set), the new | |
2695 | * request must wait for outstanding read requests to complete. | |
5816d648 BW |
2696 | * |
2697 | * Returns 0 if successful, else propagates up the lower layer error. | |
2698 | */ | |
2911a35b BW |
2699 | int |
2700 | i915_gem_object_sync(struct drm_i915_gem_object *obj, | |
8e637178 | 2701 | struct drm_i915_gem_request *to) |
2911a35b | 2702 | { |
8cac6f6c CW |
2703 | struct i915_gem_active *active; |
2704 | unsigned long active_mask; | |
2705 | int idx; | |
41c52415 | 2706 | |
8cac6f6c | 2707 | lockdep_assert_held(&obj->base.dev->struct_mutex); |
2911a35b | 2708 | |
573adb39 | 2709 | active_mask = i915_gem_object_get_active(obj); |
8cac6f6c CW |
2710 | if (!active_mask) |
2711 | return 0; | |
27c01aae | 2712 | |
8cac6f6c CW |
2713 | if (obj->base.pending_write_domain) { |
2714 | active = obj->last_read; | |
b4716185 | 2715 | } else { |
8cac6f6c CW |
2716 | active_mask = 1; |
2717 | active = &obj->last_write; | |
b4716185 | 2718 | } |
8cac6f6c CW |
2719 | |
2720 | for_each_active(active_mask, idx) { | |
2721 | struct drm_i915_gem_request *request; | |
2722 | int ret; | |
2723 | ||
2724 | request = i915_gem_active_peek(&active[idx], | |
2725 | &obj->base.dev->struct_mutex); | |
2726 | if (!request) | |
2727 | continue; | |
2728 | ||
fa545cbf | 2729 | ret = __i915_gem_object_sync(to, request); |
b4716185 CW |
2730 | if (ret) |
2731 | return ret; | |
2732 | } | |
2911a35b | 2733 | |
b4716185 | 2734 | return 0; |
2911a35b BW |
2735 | } |
2736 | ||
b5ffc9bc CW |
2737 | static void i915_gem_object_finish_gtt(struct drm_i915_gem_object *obj) |
2738 | { | |
2739 | u32 old_write_domain, old_read_domains; | |
2740 | ||
b5ffc9bc CW |
2741 | /* Force a pagefault for domain tracking on next user access */ |
2742 | i915_gem_release_mmap(obj); | |
2743 | ||
b97c3d9c KP |
2744 | if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0) |
2745 | return; | |
2746 | ||
b5ffc9bc CW |
2747 | old_read_domains = obj->base.read_domains; |
2748 | old_write_domain = obj->base.write_domain; | |
2749 | ||
2750 | obj->base.read_domains &= ~I915_GEM_DOMAIN_GTT; | |
2751 | obj->base.write_domain &= ~I915_GEM_DOMAIN_GTT; | |
2752 | ||
2753 | trace_i915_gem_object_change_domain(obj, | |
2754 | old_read_domains, | |
2755 | old_write_domain); | |
2756 | } | |
2757 | ||
8ef8561f CW |
2758 | static void __i915_vma_iounmap(struct i915_vma *vma) |
2759 | { | |
20dfbde4 | 2760 | GEM_BUG_ON(i915_vma_is_pinned(vma)); |
8ef8561f CW |
2761 | |
2762 | if (vma->iomap == NULL) | |
2763 | return; | |
2764 | ||
2765 | io_mapping_unmap(vma->iomap); | |
2766 | vma->iomap = NULL; | |
2767 | } | |
2768 | ||
df0e9a28 | 2769 | int i915_vma_unbind(struct i915_vma *vma) |
673a394b | 2770 | { |
07fe0b12 | 2771 | struct drm_i915_gem_object *obj = vma->obj; |
b0decaf7 | 2772 | unsigned long active; |
43e28f09 | 2773 | int ret; |
673a394b | 2774 | |
b0decaf7 CW |
2775 | /* First wait upon any activity as retiring the request may |
2776 | * have side-effects such as unpinning or even unbinding this vma. | |
2777 | */ | |
2778 | active = i915_vma_get_active(vma); | |
df0e9a28 | 2779 | if (active) { |
b0decaf7 CW |
2780 | int idx; |
2781 | ||
b1f788c6 CW |
2782 | /* When a closed VMA is retired, it is unbound - eek. |
2783 | * In order to prevent it from being recursively closed, | |
2784 | * take a pin on the vma so that the second unbind is | |
2785 | * aborted. | |
2786 | */ | |
20dfbde4 | 2787 | __i915_vma_pin(vma); |
b1f788c6 | 2788 | |
b0decaf7 CW |
2789 | for_each_active(active, idx) { |
2790 | ret = i915_gem_active_retire(&vma->last_read[idx], | |
2791 | &vma->vm->dev->struct_mutex); | |
2792 | if (ret) | |
b1f788c6 | 2793 | break; |
b0decaf7 CW |
2794 | } |
2795 | ||
20dfbde4 | 2796 | __i915_vma_unpin(vma); |
b1f788c6 CW |
2797 | if (ret) |
2798 | return ret; | |
2799 | ||
b0decaf7 CW |
2800 | GEM_BUG_ON(i915_vma_is_active(vma)); |
2801 | } | |
2802 | ||
20dfbde4 | 2803 | if (i915_vma_is_pinned(vma)) |
b0decaf7 CW |
2804 | return -EBUSY; |
2805 | ||
b1f788c6 CW |
2806 | if (!drm_mm_node_allocated(&vma->node)) |
2807 | goto destroy; | |
433544bd | 2808 | |
15717de2 CW |
2809 | GEM_BUG_ON(obj->bind_count == 0); |
2810 | GEM_BUG_ON(!obj->pages); | |
c4670ad0 | 2811 | |
3272db53 CW |
2812 | if (i915_vma_is_ggtt(vma) && |
2813 | vma->ggtt_view.type == I915_GGTT_VIEW_NORMAL) { | |
8b1bc9b4 | 2814 | i915_gem_object_finish_gtt(obj); |
5323fd04 | 2815 | |
8b1bc9b4 DV |
2816 | /* release the fence reg _after_ flushing */ |
2817 | ret = i915_gem_object_put_fence(obj); | |
2818 | if (ret) | |
2819 | return ret; | |
8ef8561f CW |
2820 | |
2821 | __i915_vma_iounmap(vma); | |
8b1bc9b4 | 2822 | } |
96b47b65 | 2823 | |
50e046b6 CW |
2824 | if (likely(!vma->vm->closed)) { |
2825 | trace_i915_vma_unbind(vma); | |
2826 | vma->vm->unbind_vma(vma); | |
2827 | } | |
3272db53 | 2828 | vma->flags &= ~(I915_VMA_GLOBAL_BIND | I915_VMA_LOCAL_BIND); |
6f65e29a | 2829 | |
50e046b6 CW |
2830 | drm_mm_remove_node(&vma->node); |
2831 | list_move_tail(&vma->vm_link, &vma->vm->unbound_list); | |
2832 | ||
3272db53 | 2833 | if (i915_vma_is_ggtt(vma)) { |
fe14d5f4 TU |
2834 | if (vma->ggtt_view.type == I915_GGTT_VIEW_NORMAL) { |
2835 | obj->map_and_fenceable = false; | |
2836 | } else if (vma->ggtt_view.pages) { | |
2837 | sg_free_table(vma->ggtt_view.pages); | |
2838 | kfree(vma->ggtt_view.pages); | |
fe14d5f4 | 2839 | } |
016a65a3 | 2840 | vma->ggtt_view.pages = NULL; |
fe14d5f4 | 2841 | } |
673a394b | 2842 | |
2f633156 | 2843 | /* Since the unbound list is global, only move to that list if |
b93dab6e | 2844 | * no more VMAs exist. */ |
15717de2 CW |
2845 | if (--obj->bind_count == 0) |
2846 | list_move_tail(&obj->global_list, | |
2847 | &to_i915(obj->base.dev)->mm.unbound_list); | |
673a394b | 2848 | |
70903c3b CW |
2849 | /* And finally now the object is completely decoupled from this vma, |
2850 | * we can drop its hold on the backing storage and allow it to be | |
2851 | * reaped by the shrinker. | |
2852 | */ | |
2853 | i915_gem_object_unpin_pages(obj); | |
2854 | ||
b1f788c6 | 2855 | destroy: |
3272db53 | 2856 | if (unlikely(i915_vma_is_closed(vma))) |
b1f788c6 CW |
2857 | i915_vma_destroy(vma); |
2858 | ||
88241785 | 2859 | return 0; |
54cf91dc CW |
2860 | } |
2861 | ||
dcff85c8 CW |
2862 | int i915_gem_wait_for_idle(struct drm_i915_private *dev_priv, |
2863 | bool interruptible) | |
4df2faf4 | 2864 | { |
e2f80391 | 2865 | struct intel_engine_cs *engine; |
b4ac5afc | 2866 | int ret; |
4df2faf4 | 2867 | |
b4ac5afc | 2868 | for_each_engine(engine, dev_priv) { |
62e63007 CW |
2869 | if (engine->last_context == NULL) |
2870 | continue; | |
2871 | ||
dcff85c8 | 2872 | ret = intel_engine_idle(engine, interruptible); |
1ec14ad3 CW |
2873 | if (ret) |
2874 | return ret; | |
2875 | } | |
4df2faf4 | 2876 | |
8a1a49f9 | 2877 | return 0; |
4df2faf4 DV |
2878 | } |
2879 | ||
4144f9b5 | 2880 | static bool i915_gem_valid_gtt_space(struct i915_vma *vma, |
42d6ab48 CW |
2881 | unsigned long cache_level) |
2882 | { | |
4144f9b5 | 2883 | struct drm_mm_node *gtt_space = &vma->node; |
42d6ab48 CW |
2884 | struct drm_mm_node *other; |
2885 | ||
4144f9b5 CW |
2886 | /* |
2887 | * On some machines we have to be careful when putting differing types | |
2888 | * of snoopable memory together to avoid the prefetcher crossing memory | |
2889 | * domains and dying. During vm initialisation, we decide whether or not | |
2890 | * these constraints apply and set the drm_mm.color_adjust | |
2891 | * appropriately. | |
42d6ab48 | 2892 | */ |
4144f9b5 | 2893 | if (vma->vm->mm.color_adjust == NULL) |
42d6ab48 CW |
2894 | return true; |
2895 | ||
c6cfb325 | 2896 | if (!drm_mm_node_allocated(gtt_space)) |
42d6ab48 CW |
2897 | return true; |
2898 | ||
2899 | if (list_empty(>t_space->node_list)) | |
2900 | return true; | |
2901 | ||
2902 | other = list_entry(gtt_space->node_list.prev, struct drm_mm_node, node_list); | |
2903 | if (other->allocated && !other->hole_follows && other->color != cache_level) | |
2904 | return false; | |
2905 | ||
2906 | other = list_entry(gtt_space->node_list.next, struct drm_mm_node, node_list); | |
2907 | if (other->allocated && !gtt_space->hole_follows && other->color != cache_level) | |
2908 | return false; | |
2909 | ||
2910 | return true; | |
2911 | } | |
2912 | ||
673a394b | 2913 | /** |
59bfa124 CW |
2914 | * i915_vma_insert - finds a slot for the vma in its address space |
2915 | * @vma: the vma | |
91b2db6f | 2916 | * @size: requested size in bytes (can be larger than the VMA) |
59bfa124 | 2917 | * @alignment: required alignment |
14bb2c11 | 2918 | * @flags: mask of PIN_* flags to use |
59bfa124 CW |
2919 | * |
2920 | * First we try to allocate some free space that meets the requirements for | |
2921 | * the VMA. Failiing that, if the flags permit, it will evict an old VMA, | |
2922 | * preferrably the oldest idle entry to make room for the new VMA. | |
2923 | * | |
2924 | * Returns: | |
2925 | * 0 on success, negative error code otherwise. | |
673a394b | 2926 | */ |
59bfa124 CW |
2927 | static int |
2928 | i915_vma_insert(struct i915_vma *vma, u64 size, u64 alignment, u64 flags) | |
673a394b | 2929 | { |
59bfa124 CW |
2930 | struct drm_i915_private *dev_priv = to_i915(vma->vm->dev); |
2931 | struct drm_i915_gem_object *obj = vma->obj; | |
de180033 CW |
2932 | u64 start, end; |
2933 | u64 min_alignment; | |
07f73f69 | 2934 | int ret; |
673a394b | 2935 | |
3272db53 | 2936 | GEM_BUG_ON(vma->flags & (I915_VMA_GLOBAL_BIND | I915_VMA_LOCAL_BIND)); |
59bfa124 | 2937 | GEM_BUG_ON(drm_mm_node_allocated(&vma->node)); |
de180033 CW |
2938 | |
2939 | size = max(size, vma->size); | |
2940 | if (flags & PIN_MAPPABLE) | |
2941 | size = i915_gem_get_ggtt_size(dev_priv, size, obj->tiling_mode); | |
2942 | ||
2943 | min_alignment = | |
2944 | i915_gem_get_ggtt_alignment(dev_priv, size, obj->tiling_mode, | |
2945 | flags & PIN_MAPPABLE); | |
2946 | if (alignment == 0) | |
2947 | alignment = min_alignment; | |
2948 | if (alignment & (min_alignment - 1)) { | |
2949 | DRM_DEBUG("Invalid object alignment requested %llu, minimum %llu\n", | |
2950 | alignment, min_alignment); | |
59bfa124 | 2951 | return -EINVAL; |
91e6711e | 2952 | } |
a00b10c3 | 2953 | |
101b506a | 2954 | start = flags & PIN_OFFSET_BIAS ? flags & PIN_OFFSET_MASK : 0; |
de180033 CW |
2955 | |
2956 | end = vma->vm->total; | |
101b506a | 2957 | if (flags & PIN_MAPPABLE) |
91b2db6f | 2958 | end = min_t(u64, end, dev_priv->ggtt.mappable_end); |
101b506a | 2959 | if (flags & PIN_ZONE_4G) |
48ea1e32 | 2960 | end = min_t(u64, end, (1ULL << 32) - PAGE_SIZE); |
101b506a | 2961 | |
91e6711e JL |
2962 | /* If binding the object/GGTT view requires more space than the entire |
2963 | * aperture has, reject it early before evicting everything in a vain | |
2964 | * attempt to find space. | |
654fc607 | 2965 | */ |
91e6711e | 2966 | if (size > end) { |
de180033 | 2967 | DRM_DEBUG("Attempting to bind an object larger than the aperture: request=%llu [object=%zd] > %s aperture=%llu\n", |
91b2db6f | 2968 | size, obj->base.size, |
1ec9e26d | 2969 | flags & PIN_MAPPABLE ? "mappable" : "total", |
d23db88c | 2970 | end); |
59bfa124 | 2971 | return -E2BIG; |
654fc607 CW |
2972 | } |
2973 | ||
37e680a1 | 2974 | ret = i915_gem_object_get_pages(obj); |
6c085a72 | 2975 | if (ret) |
59bfa124 | 2976 | return ret; |
6c085a72 | 2977 | |
fbdda6fb CW |
2978 | i915_gem_object_pin_pages(obj); |
2979 | ||
506a8e87 | 2980 | if (flags & PIN_OFFSET_FIXED) { |
59bfa124 | 2981 | u64 offset = flags & PIN_OFFSET_MASK; |
de180033 | 2982 | if (offset & (alignment - 1) || offset > end - size) { |
506a8e87 | 2983 | ret = -EINVAL; |
de180033 | 2984 | goto err_unpin; |
506a8e87 | 2985 | } |
de180033 | 2986 | |
506a8e87 CW |
2987 | vma->node.start = offset; |
2988 | vma->node.size = size; | |
2989 | vma->node.color = obj->cache_level; | |
de180033 | 2990 | ret = drm_mm_reserve_node(&vma->vm->mm, &vma->node); |
506a8e87 CW |
2991 | if (ret) { |
2992 | ret = i915_gem_evict_for_vma(vma); | |
2993 | if (ret == 0) | |
de180033 CW |
2994 | ret = drm_mm_reserve_node(&vma->vm->mm, &vma->node); |
2995 | if (ret) | |
2996 | goto err_unpin; | |
506a8e87 | 2997 | } |
101b506a | 2998 | } else { |
de180033 CW |
2999 | u32 search_flag, alloc_flag; |
3000 | ||
506a8e87 CW |
3001 | if (flags & PIN_HIGH) { |
3002 | search_flag = DRM_MM_SEARCH_BELOW; | |
3003 | alloc_flag = DRM_MM_CREATE_TOP; | |
3004 | } else { | |
3005 | search_flag = DRM_MM_SEARCH_DEFAULT; | |
3006 | alloc_flag = DRM_MM_CREATE_DEFAULT; | |
3007 | } | |
101b506a | 3008 | |
954c4691 CW |
3009 | /* We only allocate in PAGE_SIZE/GTT_PAGE_SIZE (4096) chunks, |
3010 | * so we know that we always have a minimum alignment of 4096. | |
3011 | * The drm_mm range manager is optimised to return results | |
3012 | * with zero alignment, so where possible use the optimal | |
3013 | * path. | |
3014 | */ | |
3015 | if (alignment <= 4096) | |
3016 | alignment = 0; | |
3017 | ||
0a9ae0d7 | 3018 | search_free: |
de180033 CW |
3019 | ret = drm_mm_insert_node_in_range_generic(&vma->vm->mm, |
3020 | &vma->node, | |
506a8e87 CW |
3021 | size, alignment, |
3022 | obj->cache_level, | |
3023 | start, end, | |
3024 | search_flag, | |
3025 | alloc_flag); | |
3026 | if (ret) { | |
de180033 | 3027 | ret = i915_gem_evict_something(vma->vm, size, alignment, |
506a8e87 CW |
3028 | obj->cache_level, |
3029 | start, end, | |
3030 | flags); | |
3031 | if (ret == 0) | |
3032 | goto search_free; | |
9731129c | 3033 | |
de180033 | 3034 | goto err_unpin; |
506a8e87 | 3035 | } |
673a394b | 3036 | } |
37508589 | 3037 | GEM_BUG_ON(!i915_gem_valid_gtt_space(vma, obj->cache_level)); |
673a394b | 3038 | |
35c20a60 | 3039 | list_move_tail(&obj->global_list, &dev_priv->mm.bound_list); |
de180033 | 3040 | list_move_tail(&vma->vm_link, &vma->vm->inactive_list); |
15717de2 | 3041 | obj->bind_count++; |
bf1a1092 | 3042 | |
59bfa124 | 3043 | return 0; |
2f633156 | 3044 | |
bc6bc15b | 3045 | err_unpin: |
2f633156 | 3046 | i915_gem_object_unpin_pages(obj); |
59bfa124 | 3047 | return ret; |
673a394b EA |
3048 | } |
3049 | ||
000433b6 | 3050 | bool |
2c22569b CW |
3051 | i915_gem_clflush_object(struct drm_i915_gem_object *obj, |
3052 | bool force) | |
673a394b | 3053 | { |
673a394b EA |
3054 | /* If we don't have a page list set up, then we're not pinned |
3055 | * to GPU, and we can ignore the cache flush because it'll happen | |
3056 | * again at bind time. | |
3057 | */ | |
05394f39 | 3058 | if (obj->pages == NULL) |
000433b6 | 3059 | return false; |
673a394b | 3060 | |
769ce464 ID |
3061 | /* |
3062 | * Stolen memory is always coherent with the GPU as it is explicitly | |
3063 | * marked as wc by the system, or the system is cache-coherent. | |
3064 | */ | |
6a2c4232 | 3065 | if (obj->stolen || obj->phys_handle) |
000433b6 | 3066 | return false; |
769ce464 | 3067 | |
9c23f7fc CW |
3068 | /* If the GPU is snooping the contents of the CPU cache, |
3069 | * we do not need to manually clear the CPU cache lines. However, | |
3070 | * the caches are only snooped when the render cache is | |
3071 | * flushed/invalidated. As we always have to emit invalidations | |
3072 | * and flushes when moving into and out of the RENDER domain, correct | |
3073 | * snooping behaviour occurs naturally as the result of our domain | |
3074 | * tracking. | |
3075 | */ | |
0f71979a CW |
3076 | if (!force && cpu_cache_is_coherent(obj->base.dev, obj->cache_level)) { |
3077 | obj->cache_dirty = true; | |
000433b6 | 3078 | return false; |
0f71979a | 3079 | } |
9c23f7fc | 3080 | |
1c5d22f7 | 3081 | trace_i915_gem_object_clflush(obj); |
9da3da66 | 3082 | drm_clflush_sg(obj->pages); |
0f71979a | 3083 | obj->cache_dirty = false; |
000433b6 CW |
3084 | |
3085 | return true; | |
e47c68e9 EA |
3086 | } |
3087 | ||
3088 | /** Flushes the GTT write domain for the object if it's dirty. */ | |
3089 | static void | |
05394f39 | 3090 | i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj) |
e47c68e9 | 3091 | { |
1c5d22f7 CW |
3092 | uint32_t old_write_domain; |
3093 | ||
05394f39 | 3094 | if (obj->base.write_domain != I915_GEM_DOMAIN_GTT) |
e47c68e9 EA |
3095 | return; |
3096 | ||
63256ec5 | 3097 | /* No actual flushing is required for the GTT write domain. Writes |
e47c68e9 EA |
3098 | * to it immediately go to main memory as far as we know, so there's |
3099 | * no chipset flush. It also doesn't land in render cache. | |
63256ec5 CW |
3100 | * |
3101 | * However, we do have to enforce the order so that all writes through | |
3102 | * the GTT land before any writes to the device, such as updates to | |
3103 | * the GATT itself. | |
e47c68e9 | 3104 | */ |
63256ec5 CW |
3105 | wmb(); |
3106 | ||
05394f39 CW |
3107 | old_write_domain = obj->base.write_domain; |
3108 | obj->base.write_domain = 0; | |
1c5d22f7 | 3109 | |
de152b62 | 3110 | intel_fb_obj_flush(obj, false, ORIGIN_GTT); |
f99d7069 | 3111 | |
1c5d22f7 | 3112 | trace_i915_gem_object_change_domain(obj, |
05394f39 | 3113 | obj->base.read_domains, |
1c5d22f7 | 3114 | old_write_domain); |
e47c68e9 EA |
3115 | } |
3116 | ||
3117 | /** Flushes the CPU write domain for the object if it's dirty. */ | |
3118 | static void | |
e62b59e4 | 3119 | i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj) |
e47c68e9 | 3120 | { |
1c5d22f7 | 3121 | uint32_t old_write_domain; |
e47c68e9 | 3122 | |
05394f39 | 3123 | if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) |
e47c68e9 EA |
3124 | return; |
3125 | ||
e62b59e4 | 3126 | if (i915_gem_clflush_object(obj, obj->pin_display)) |
c033666a | 3127 | i915_gem_chipset_flush(to_i915(obj->base.dev)); |
000433b6 | 3128 | |
05394f39 CW |
3129 | old_write_domain = obj->base.write_domain; |
3130 | obj->base.write_domain = 0; | |
1c5d22f7 | 3131 | |
de152b62 | 3132 | intel_fb_obj_flush(obj, false, ORIGIN_CPU); |
f99d7069 | 3133 | |
1c5d22f7 | 3134 | trace_i915_gem_object_change_domain(obj, |
05394f39 | 3135 | obj->base.read_domains, |
1c5d22f7 | 3136 | old_write_domain); |
e47c68e9 EA |
3137 | } |
3138 | ||
2ef7eeaa EA |
3139 | /** |
3140 | * Moves a single object to the GTT read, and possibly write domain. | |
14bb2c11 TU |
3141 | * @obj: object to act on |
3142 | * @write: ask for write access or read only | |
2ef7eeaa EA |
3143 | * |
3144 | * This function returns when the move is complete, including waiting on | |
3145 | * flushes to occur. | |
3146 | */ | |
79e53945 | 3147 | int |
2021746e | 3148 | i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write) |
2ef7eeaa | 3149 | { |
1c5d22f7 | 3150 | uint32_t old_write_domain, old_read_domains; |
43566ded | 3151 | struct i915_vma *vma; |
e47c68e9 | 3152 | int ret; |
2ef7eeaa | 3153 | |
0201f1ec | 3154 | ret = i915_gem_object_wait_rendering(obj, !write); |
88241785 CW |
3155 | if (ret) |
3156 | return ret; | |
3157 | ||
c13d87ea CW |
3158 | if (obj->base.write_domain == I915_GEM_DOMAIN_GTT) |
3159 | return 0; | |
3160 | ||
43566ded CW |
3161 | /* Flush and acquire obj->pages so that we are coherent through |
3162 | * direct access in memory with previous cached writes through | |
3163 | * shmemfs and that our cache domain tracking remains valid. | |
3164 | * For example, if the obj->filp was moved to swap without us | |
3165 | * being notified and releasing the pages, we would mistakenly | |
3166 | * continue to assume that the obj remained out of the CPU cached | |
3167 | * domain. | |
3168 | */ | |
3169 | ret = i915_gem_object_get_pages(obj); | |
3170 | if (ret) | |
3171 | return ret; | |
3172 | ||
e62b59e4 | 3173 | i915_gem_object_flush_cpu_write_domain(obj); |
1c5d22f7 | 3174 | |
d0a57789 CW |
3175 | /* Serialise direct access to this object with the barriers for |
3176 | * coherent writes from the GPU, by effectively invalidating the | |
3177 | * GTT domain upon first access. | |
3178 | */ | |
3179 | if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0) | |
3180 | mb(); | |
3181 | ||
05394f39 CW |
3182 | old_write_domain = obj->base.write_domain; |
3183 | old_read_domains = obj->base.read_domains; | |
1c5d22f7 | 3184 | |
e47c68e9 EA |
3185 | /* It should now be out of any other write domains, and we can update |
3186 | * the domain values for our changes. | |
3187 | */ | |
05394f39 CW |
3188 | BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) != 0); |
3189 | obj->base.read_domains |= I915_GEM_DOMAIN_GTT; | |
e47c68e9 | 3190 | if (write) { |
05394f39 CW |
3191 | obj->base.read_domains = I915_GEM_DOMAIN_GTT; |
3192 | obj->base.write_domain = I915_GEM_DOMAIN_GTT; | |
3193 | obj->dirty = 1; | |
2ef7eeaa EA |
3194 | } |
3195 | ||
1c5d22f7 CW |
3196 | trace_i915_gem_object_change_domain(obj, |
3197 | old_read_domains, | |
3198 | old_write_domain); | |
3199 | ||
8325a09d | 3200 | /* And bump the LRU for this access */ |
43566ded | 3201 | vma = i915_gem_obj_to_ggtt(obj); |
b0decaf7 CW |
3202 | if (vma && |
3203 | drm_mm_node_allocated(&vma->node) && | |
3204 | !i915_vma_is_active(vma)) | |
3205 | list_move_tail(&vma->vm_link, &vma->vm->inactive_list); | |
8325a09d | 3206 | |
e47c68e9 EA |
3207 | return 0; |
3208 | } | |
3209 | ||
ef55f92a CW |
3210 | /** |
3211 | * Changes the cache-level of an object across all VMA. | |
14bb2c11 TU |
3212 | * @obj: object to act on |
3213 | * @cache_level: new cache level to set for the object | |
ef55f92a CW |
3214 | * |
3215 | * After this function returns, the object will be in the new cache-level | |
3216 | * across all GTT and the contents of the backing storage will be coherent, | |
3217 | * with respect to the new cache-level. In order to keep the backing storage | |
3218 | * coherent for all users, we only allow a single cache level to be set | |
3219 | * globally on the object and prevent it from being changed whilst the | |
3220 | * hardware is reading from the object. That is if the object is currently | |
3221 | * on the scanout it will be set to uncached (or equivalent display | |
3222 | * cache coherency) and all non-MOCS GPU access will also be uncached so | |
3223 | * that all direct access to the scanout remains coherent. | |
3224 | */ | |
e4ffd173 CW |
3225 | int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj, |
3226 | enum i915_cache_level cache_level) | |
3227 | { | |
aa653a68 | 3228 | struct i915_vma *vma; |
ed75a55b | 3229 | int ret = 0; |
e4ffd173 CW |
3230 | |
3231 | if (obj->cache_level == cache_level) | |
ed75a55b | 3232 | goto out; |
e4ffd173 | 3233 | |
ef55f92a CW |
3234 | /* Inspect the list of currently bound VMA and unbind any that would |
3235 | * be invalid given the new cache-level. This is principally to | |
3236 | * catch the issue of the CS prefetch crossing page boundaries and | |
3237 | * reading an invalid PTE on older architectures. | |
3238 | */ | |
aa653a68 CW |
3239 | restart: |
3240 | list_for_each_entry(vma, &obj->vma_list, obj_link) { | |
ef55f92a CW |
3241 | if (!drm_mm_node_allocated(&vma->node)) |
3242 | continue; | |
3243 | ||
20dfbde4 | 3244 | if (i915_vma_is_pinned(vma)) { |
ef55f92a CW |
3245 | DRM_DEBUG("can not change the cache level of pinned objects\n"); |
3246 | return -EBUSY; | |
3247 | } | |
3248 | ||
aa653a68 CW |
3249 | if (i915_gem_valid_gtt_space(vma, cache_level)) |
3250 | continue; | |
3251 | ||
3252 | ret = i915_vma_unbind(vma); | |
3253 | if (ret) | |
3254 | return ret; | |
3255 | ||
3256 | /* As unbinding may affect other elements in the | |
3257 | * obj->vma_list (due to side-effects from retiring | |
3258 | * an active vma), play safe and restart the iterator. | |
3259 | */ | |
3260 | goto restart; | |
42d6ab48 CW |
3261 | } |
3262 | ||
ef55f92a CW |
3263 | /* We can reuse the existing drm_mm nodes but need to change the |
3264 | * cache-level on the PTE. We could simply unbind them all and | |
3265 | * rebind with the correct cache-level on next use. However since | |
3266 | * we already have a valid slot, dma mapping, pages etc, we may as | |
3267 | * rewrite the PTE in the belief that doing so tramples upon less | |
3268 | * state and so involves less work. | |
3269 | */ | |
15717de2 | 3270 | if (obj->bind_count) { |
ef55f92a CW |
3271 | /* Before we change the PTE, the GPU must not be accessing it. |
3272 | * If we wait upon the object, we know that all the bound | |
3273 | * VMA are no longer active. | |
3274 | */ | |
2e2f351d | 3275 | ret = i915_gem_object_wait_rendering(obj, false); |
e4ffd173 CW |
3276 | if (ret) |
3277 | return ret; | |
3278 | ||
aa653a68 | 3279 | if (!HAS_LLC(obj->base.dev) && cache_level != I915_CACHE_NONE) { |
ef55f92a CW |
3280 | /* Access to snoopable pages through the GTT is |
3281 | * incoherent and on some machines causes a hard | |
3282 | * lockup. Relinquish the CPU mmaping to force | |
3283 | * userspace to refault in the pages and we can | |
3284 | * then double check if the GTT mapping is still | |
3285 | * valid for that pointer access. | |
3286 | */ | |
3287 | i915_gem_release_mmap(obj); | |
3288 | ||
3289 | /* As we no longer need a fence for GTT access, | |
3290 | * we can relinquish it now (and so prevent having | |
3291 | * to steal a fence from someone else on the next | |
3292 | * fence request). Note GPU activity would have | |
3293 | * dropped the fence as all snoopable access is | |
3294 | * supposed to be linear. | |
3295 | */ | |
e4ffd173 CW |
3296 | ret = i915_gem_object_put_fence(obj); |
3297 | if (ret) | |
3298 | return ret; | |
ef55f92a CW |
3299 | } else { |
3300 | /* We either have incoherent backing store and | |
3301 | * so no GTT access or the architecture is fully | |
3302 | * coherent. In such cases, existing GTT mmaps | |
3303 | * ignore the cache bit in the PTE and we can | |
3304 | * rewrite it without confusing the GPU or having | |
3305 | * to force userspace to fault back in its mmaps. | |
3306 | */ | |
e4ffd173 CW |
3307 | } |
3308 | ||
1c7f4bca | 3309 | list_for_each_entry(vma, &obj->vma_list, obj_link) { |
ef55f92a CW |
3310 | if (!drm_mm_node_allocated(&vma->node)) |
3311 | continue; | |
3312 | ||
3313 | ret = i915_vma_bind(vma, cache_level, PIN_UPDATE); | |
3314 | if (ret) | |
3315 | return ret; | |
3316 | } | |
e4ffd173 CW |
3317 | } |
3318 | ||
1c7f4bca | 3319 | list_for_each_entry(vma, &obj->vma_list, obj_link) |
2c22569b CW |
3320 | vma->node.color = cache_level; |
3321 | obj->cache_level = cache_level; | |
3322 | ||
ed75a55b | 3323 | out: |
ef55f92a CW |
3324 | /* Flush the dirty CPU caches to the backing storage so that the |
3325 | * object is now coherent at its new cache level (with respect | |
3326 | * to the access domain). | |
3327 | */ | |
b50a5371 | 3328 | if (obj->cache_dirty && cpu_write_needs_clflush(obj)) { |
0f71979a | 3329 | if (i915_gem_clflush_object(obj, true)) |
c033666a | 3330 | i915_gem_chipset_flush(to_i915(obj->base.dev)); |
e4ffd173 CW |
3331 | } |
3332 | ||
e4ffd173 CW |
3333 | return 0; |
3334 | } | |
3335 | ||
199adf40 BW |
3336 | int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data, |
3337 | struct drm_file *file) | |
e6994aee | 3338 | { |
199adf40 | 3339 | struct drm_i915_gem_caching *args = data; |
e6994aee | 3340 | struct drm_i915_gem_object *obj; |
e6994aee | 3341 | |
03ac0642 CW |
3342 | obj = i915_gem_object_lookup(file, args->handle); |
3343 | if (!obj) | |
432be69d | 3344 | return -ENOENT; |
e6994aee | 3345 | |
651d794f CW |
3346 | switch (obj->cache_level) { |
3347 | case I915_CACHE_LLC: | |
3348 | case I915_CACHE_L3_LLC: | |
3349 | args->caching = I915_CACHING_CACHED; | |
3350 | break; | |
3351 | ||
4257d3ba CW |
3352 | case I915_CACHE_WT: |
3353 | args->caching = I915_CACHING_DISPLAY; | |
3354 | break; | |
3355 | ||
651d794f CW |
3356 | default: |
3357 | args->caching = I915_CACHING_NONE; | |
3358 | break; | |
3359 | } | |
e6994aee | 3360 | |
34911fd3 | 3361 | i915_gem_object_put_unlocked(obj); |
432be69d | 3362 | return 0; |
e6994aee CW |
3363 | } |
3364 | ||
199adf40 BW |
3365 | int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data, |
3366 | struct drm_file *file) | |
e6994aee | 3367 | { |
fac5e23e | 3368 | struct drm_i915_private *dev_priv = to_i915(dev); |
199adf40 | 3369 | struct drm_i915_gem_caching *args = data; |
e6994aee CW |
3370 | struct drm_i915_gem_object *obj; |
3371 | enum i915_cache_level level; | |
3372 | int ret; | |
3373 | ||
199adf40 BW |
3374 | switch (args->caching) { |
3375 | case I915_CACHING_NONE: | |
e6994aee CW |
3376 | level = I915_CACHE_NONE; |
3377 | break; | |
199adf40 | 3378 | case I915_CACHING_CACHED: |
e5756c10 ID |
3379 | /* |
3380 | * Due to a HW issue on BXT A stepping, GPU stores via a | |
3381 | * snooped mapping may leave stale data in a corresponding CPU | |
3382 | * cacheline, whereas normally such cachelines would get | |
3383 | * invalidated. | |
3384 | */ | |
ca377809 | 3385 | if (!HAS_LLC(dev) && !HAS_SNOOP(dev)) |
e5756c10 ID |
3386 | return -ENODEV; |
3387 | ||
e6994aee CW |
3388 | level = I915_CACHE_LLC; |
3389 | break; | |
4257d3ba CW |
3390 | case I915_CACHING_DISPLAY: |
3391 | level = HAS_WT(dev) ? I915_CACHE_WT : I915_CACHE_NONE; | |
3392 | break; | |
e6994aee CW |
3393 | default: |
3394 | return -EINVAL; | |
3395 | } | |
3396 | ||
fd0fe6ac ID |
3397 | intel_runtime_pm_get(dev_priv); |
3398 | ||
3bc2913e BW |
3399 | ret = i915_mutex_lock_interruptible(dev); |
3400 | if (ret) | |
fd0fe6ac | 3401 | goto rpm_put; |
3bc2913e | 3402 | |
03ac0642 CW |
3403 | obj = i915_gem_object_lookup(file, args->handle); |
3404 | if (!obj) { | |
e6994aee CW |
3405 | ret = -ENOENT; |
3406 | goto unlock; | |
3407 | } | |
3408 | ||
3409 | ret = i915_gem_object_set_cache_level(obj, level); | |
3410 | ||
f8c417cd | 3411 | i915_gem_object_put(obj); |
e6994aee CW |
3412 | unlock: |
3413 | mutex_unlock(&dev->struct_mutex); | |
fd0fe6ac ID |
3414 | rpm_put: |
3415 | intel_runtime_pm_put(dev_priv); | |
3416 | ||
e6994aee CW |
3417 | return ret; |
3418 | } | |
3419 | ||
b9241ea3 | 3420 | /* |
2da3b9b9 CW |
3421 | * Prepare buffer for display plane (scanout, cursors, etc). |
3422 | * Can be called from an uninterruptible phase (modesetting) and allows | |
3423 | * any flushes to be pipelined (for pageflips). | |
b9241ea3 ZW |
3424 | */ |
3425 | int | |
2da3b9b9 CW |
3426 | i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj, |
3427 | u32 alignment, | |
e6617330 | 3428 | const struct i915_ggtt_view *view) |
b9241ea3 | 3429 | { |
2da3b9b9 | 3430 | u32 old_read_domains, old_write_domain; |
b9241ea3 ZW |
3431 | int ret; |
3432 | ||
cc98b413 CW |
3433 | /* Mark the pin_display early so that we account for the |
3434 | * display coherency whilst setting up the cache domains. | |
3435 | */ | |
8a0c39b1 | 3436 | obj->pin_display++; |
cc98b413 | 3437 | |
a7ef0640 EA |
3438 | /* The display engine is not coherent with the LLC cache on gen6. As |
3439 | * a result, we make sure that the pinning that is about to occur is | |
3440 | * done with uncached PTEs. This is lowest common denominator for all | |
3441 | * chipsets. | |
3442 | * | |
3443 | * However for gen6+, we could do better by using the GFDT bit instead | |
3444 | * of uncaching, which would allow us to flush all the LLC-cached data | |
3445 | * with that bit in the PTE to main memory with just one PIPE_CONTROL. | |
3446 | */ | |
651d794f CW |
3447 | ret = i915_gem_object_set_cache_level(obj, |
3448 | HAS_WT(obj->base.dev) ? I915_CACHE_WT : I915_CACHE_NONE); | |
a7ef0640 | 3449 | if (ret) |
cc98b413 | 3450 | goto err_unpin_display; |
a7ef0640 | 3451 | |
2da3b9b9 CW |
3452 | /* As the user may map the buffer once pinned in the display plane |
3453 | * (e.g. libkms for the bootup splash), we have to ensure that we | |
3454 | * always use map_and_fenceable for all scanout buffers. | |
3455 | */ | |
91b2db6f | 3456 | ret = i915_gem_object_ggtt_pin(obj, view, 0, alignment, |
50470bb0 TU |
3457 | view->type == I915_GGTT_VIEW_NORMAL ? |
3458 | PIN_MAPPABLE : 0); | |
2da3b9b9 | 3459 | if (ret) |
cc98b413 | 3460 | goto err_unpin_display; |
2da3b9b9 | 3461 | |
e62b59e4 | 3462 | i915_gem_object_flush_cpu_write_domain(obj); |
b118c1e3 | 3463 | |
2da3b9b9 | 3464 | old_write_domain = obj->base.write_domain; |
05394f39 | 3465 | old_read_domains = obj->base.read_domains; |
2da3b9b9 CW |
3466 | |
3467 | /* It should now be out of any other write domains, and we can update | |
3468 | * the domain values for our changes. | |
3469 | */ | |
e5f1d962 | 3470 | obj->base.write_domain = 0; |
05394f39 | 3471 | obj->base.read_domains |= I915_GEM_DOMAIN_GTT; |
b9241ea3 ZW |
3472 | |
3473 | trace_i915_gem_object_change_domain(obj, | |
3474 | old_read_domains, | |
2da3b9b9 | 3475 | old_write_domain); |
b9241ea3 ZW |
3476 | |
3477 | return 0; | |
cc98b413 CW |
3478 | |
3479 | err_unpin_display: | |
8a0c39b1 | 3480 | obj->pin_display--; |
cc98b413 CW |
3481 | return ret; |
3482 | } | |
3483 | ||
3484 | void | |
e6617330 TU |
3485 | i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object *obj, |
3486 | const struct i915_ggtt_view *view) | |
cc98b413 | 3487 | { |
8a0c39b1 TU |
3488 | if (WARN_ON(obj->pin_display == 0)) |
3489 | return; | |
3490 | ||
e6617330 TU |
3491 | i915_gem_object_ggtt_unpin_view(obj, view); |
3492 | ||
8a0c39b1 | 3493 | obj->pin_display--; |
b9241ea3 ZW |
3494 | } |
3495 | ||
e47c68e9 EA |
3496 | /** |
3497 | * Moves a single object to the CPU read, and possibly write domain. | |
14bb2c11 TU |
3498 | * @obj: object to act on |
3499 | * @write: requesting write or read-only access | |
e47c68e9 EA |
3500 | * |
3501 | * This function returns when the move is complete, including waiting on | |
3502 | * flushes to occur. | |
3503 | */ | |
dabdfe02 | 3504 | int |
919926ae | 3505 | i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write) |
e47c68e9 | 3506 | { |
1c5d22f7 | 3507 | uint32_t old_write_domain, old_read_domains; |
e47c68e9 EA |
3508 | int ret; |
3509 | ||
0201f1ec | 3510 | ret = i915_gem_object_wait_rendering(obj, !write); |
88241785 CW |
3511 | if (ret) |
3512 | return ret; | |
3513 | ||
c13d87ea CW |
3514 | if (obj->base.write_domain == I915_GEM_DOMAIN_CPU) |
3515 | return 0; | |
3516 | ||
e47c68e9 | 3517 | i915_gem_object_flush_gtt_write_domain(obj); |
2ef7eeaa | 3518 | |
05394f39 CW |
3519 | old_write_domain = obj->base.write_domain; |
3520 | old_read_domains = obj->base.read_domains; | |
1c5d22f7 | 3521 | |
e47c68e9 | 3522 | /* Flush the CPU cache if it's still invalid. */ |
05394f39 | 3523 | if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) { |
2c22569b | 3524 | i915_gem_clflush_object(obj, false); |
2ef7eeaa | 3525 | |
05394f39 | 3526 | obj->base.read_domains |= I915_GEM_DOMAIN_CPU; |
2ef7eeaa EA |
3527 | } |
3528 | ||
3529 | /* It should now be out of any other write domains, and we can update | |
3530 | * the domain values for our changes. | |
3531 | */ | |
05394f39 | 3532 | BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) != 0); |
e47c68e9 EA |
3533 | |
3534 | /* If we're writing through the CPU, then the GPU read domains will | |
3535 | * need to be invalidated at next use. | |
3536 | */ | |
3537 | if (write) { | |
05394f39 CW |
3538 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; |
3539 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; | |
e47c68e9 | 3540 | } |
2ef7eeaa | 3541 | |
1c5d22f7 CW |
3542 | trace_i915_gem_object_change_domain(obj, |
3543 | old_read_domains, | |
3544 | old_write_domain); | |
3545 | ||
2ef7eeaa EA |
3546 | return 0; |
3547 | } | |
3548 | ||
673a394b EA |
3549 | /* Throttle our rendering by waiting until the ring has completed our requests |
3550 | * emitted over 20 msec ago. | |
3551 | * | |
b962442e EA |
3552 | * Note that if we were to use the current jiffies each time around the loop, |
3553 | * we wouldn't escape the function with any frames outstanding if the time to | |
3554 | * render a frame was over 20ms. | |
3555 | * | |
673a394b EA |
3556 | * This should get us reasonable parallelism between CPU and GPU but also |
3557 | * relatively low latency when blocking on a particular request to finish. | |
3558 | */ | |
40a5f0de | 3559 | static int |
f787a5f5 | 3560 | i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file) |
40a5f0de | 3561 | { |
fac5e23e | 3562 | struct drm_i915_private *dev_priv = to_i915(dev); |
f787a5f5 | 3563 | struct drm_i915_file_private *file_priv = file->driver_priv; |
d0bc54f2 | 3564 | unsigned long recent_enough = jiffies - DRM_I915_THROTTLE_JIFFIES; |
54fb2411 | 3565 | struct drm_i915_gem_request *request, *target = NULL; |
f787a5f5 | 3566 | int ret; |
93533c29 | 3567 | |
308887aa DV |
3568 | ret = i915_gem_wait_for_error(&dev_priv->gpu_error); |
3569 | if (ret) | |
3570 | return ret; | |
3571 | ||
f4457ae7 CW |
3572 | /* ABI: return -EIO if already wedged */ |
3573 | if (i915_terminally_wedged(&dev_priv->gpu_error)) | |
3574 | return -EIO; | |
e110e8d6 | 3575 | |
1c25595f | 3576 | spin_lock(&file_priv->mm.lock); |
f787a5f5 | 3577 | list_for_each_entry(request, &file_priv->mm.request_list, client_list) { |
b962442e EA |
3578 | if (time_after_eq(request->emitted_jiffies, recent_enough)) |
3579 | break; | |
40a5f0de | 3580 | |
fcfa423c JH |
3581 | /* |
3582 | * Note that the request might not have been submitted yet. | |
3583 | * In which case emitted_jiffies will be zero. | |
3584 | */ | |
3585 | if (!request->emitted_jiffies) | |
3586 | continue; | |
3587 | ||
54fb2411 | 3588 | target = request; |
b962442e | 3589 | } |
ff865885 | 3590 | if (target) |
e8a261ea | 3591 | i915_gem_request_get(target); |
1c25595f | 3592 | spin_unlock(&file_priv->mm.lock); |
40a5f0de | 3593 | |
54fb2411 | 3594 | if (target == NULL) |
f787a5f5 | 3595 | return 0; |
2bc43b5c | 3596 | |
776f3236 | 3597 | ret = i915_wait_request(target, true, NULL, NULL); |
e8a261ea | 3598 | i915_gem_request_put(target); |
ff865885 | 3599 | |
40a5f0de EA |
3600 | return ret; |
3601 | } | |
3602 | ||
d23db88c | 3603 | static bool |
91b2db6f | 3604 | i915_vma_misplaced(struct i915_vma *vma, u64 size, u64 alignment, u64 flags) |
d23db88c CW |
3605 | { |
3606 | struct drm_i915_gem_object *obj = vma->obj; | |
3607 | ||
59bfa124 CW |
3608 | if (!drm_mm_node_allocated(&vma->node)) |
3609 | return false; | |
3610 | ||
91b2db6f CW |
3611 | if (vma->node.size < size) |
3612 | return true; | |
3613 | ||
3614 | if (alignment && vma->node.start & (alignment - 1)) | |
d23db88c CW |
3615 | return true; |
3616 | ||
3617 | if (flags & PIN_MAPPABLE && !obj->map_and_fenceable) | |
3618 | return true; | |
3619 | ||
3620 | if (flags & PIN_OFFSET_BIAS && | |
3621 | vma->node.start < (flags & PIN_OFFSET_MASK)) | |
3622 | return true; | |
3623 | ||
506a8e87 CW |
3624 | if (flags & PIN_OFFSET_FIXED && |
3625 | vma->node.start != (flags & PIN_OFFSET_MASK)) | |
3626 | return true; | |
3627 | ||
d23db88c CW |
3628 | return false; |
3629 | } | |
3630 | ||
d0710abb CW |
3631 | void __i915_vma_set_map_and_fenceable(struct i915_vma *vma) |
3632 | { | |
3633 | struct drm_i915_gem_object *obj = vma->obj; | |
a9f1481f | 3634 | struct drm_i915_private *dev_priv = to_i915(obj->base.dev); |
d0710abb CW |
3635 | bool mappable, fenceable; |
3636 | u32 fence_size, fence_alignment; | |
3637 | ||
a9f1481f | 3638 | fence_size = i915_gem_get_ggtt_size(dev_priv, |
ad1a7d20 CW |
3639 | obj->base.size, |
3640 | obj->tiling_mode); | |
a9f1481f | 3641 | fence_alignment = i915_gem_get_ggtt_alignment(dev_priv, |
ad1a7d20 CW |
3642 | obj->base.size, |
3643 | obj->tiling_mode, | |
3644 | true); | |
d0710abb CW |
3645 | |
3646 | fenceable = (vma->node.size == fence_size && | |
3647 | (vma->node.start & (fence_alignment - 1)) == 0); | |
3648 | ||
3649 | mappable = (vma->node.start + fence_size <= | |
a9f1481f | 3650 | dev_priv->ggtt.mappable_end); |
d0710abb CW |
3651 | |
3652 | obj->map_and_fenceable = mappable && fenceable; | |
3653 | } | |
3654 | ||
305bc234 CW |
3655 | int __i915_vma_do_pin(struct i915_vma *vma, |
3656 | u64 size, u64 alignment, u64 flags) | |
673a394b | 3657 | { |
305bc234 | 3658 | unsigned int bound = vma->flags; |
673a394b EA |
3659 | int ret; |
3660 | ||
59bfa124 | 3661 | GEM_BUG_ON((flags & (PIN_GLOBAL | PIN_USER)) == 0); |
3272db53 | 3662 | GEM_BUG_ON((flags & PIN_GLOBAL) && !i915_vma_is_ggtt(vma)); |
d7f46fc4 | 3663 | |
305bc234 CW |
3664 | if (WARN_ON(bound & I915_VMA_PIN_OVERFLOW)) { |
3665 | ret = -EBUSY; | |
3666 | goto err; | |
3667 | } | |
ac0c6b5a | 3668 | |
de895082 | 3669 | if ((bound & I915_VMA_BIND_MASK) == 0) { |
59bfa124 CW |
3670 | ret = i915_vma_insert(vma, size, alignment, flags); |
3671 | if (ret) | |
3672 | goto err; | |
fe14d5f4 | 3673 | } |
74898d7e | 3674 | |
59bfa124 | 3675 | ret = i915_vma_bind(vma, vma->obj->cache_level, flags); |
3b16525c | 3676 | if (ret) |
59bfa124 | 3677 | goto err; |
3b16525c | 3678 | |
3272db53 | 3679 | if ((bound ^ vma->flags) & I915_VMA_GLOBAL_BIND) |
d0710abb | 3680 | __i915_vma_set_map_and_fenceable(vma); |
ef79e17c | 3681 | |
3b16525c | 3682 | GEM_BUG_ON(i915_vma_misplaced(vma, size, alignment, flags)); |
673a394b | 3683 | return 0; |
673a394b | 3684 | |
59bfa124 CW |
3685 | err: |
3686 | __i915_vma_unpin(vma); | |
3687 | return ret; | |
ec7adb6e JL |
3688 | } |
3689 | ||
3690 | int | |
3691 | i915_gem_object_ggtt_pin(struct drm_i915_gem_object *obj, | |
3692 | const struct i915_ggtt_view *view, | |
91b2db6f | 3693 | u64 size, |
2ffffd0f CW |
3694 | u64 alignment, |
3695 | u64 flags) | |
ec7adb6e | 3696 | { |
59bfa124 CW |
3697 | struct i915_vma *vma; |
3698 | int ret; | |
72e96d64 | 3699 | |
de895082 CW |
3700 | if (!view) |
3701 | view = &i915_ggtt_view_normal; | |
ec7adb6e | 3702 | |
59bfa124 CW |
3703 | vma = i915_gem_obj_lookup_or_create_ggtt_vma(obj, view); |
3704 | if (IS_ERR(vma)) | |
3705 | return PTR_ERR(vma); | |
3706 | ||
3707 | if (i915_vma_misplaced(vma, size, alignment, flags)) { | |
3708 | if (flags & PIN_NONBLOCK && | |
3709 | (i915_vma_is_pinned(vma) || i915_vma_is_active(vma))) | |
3710 | return -ENOSPC; | |
3711 | ||
3712 | WARN(i915_vma_is_pinned(vma), | |
3713 | "bo is already pinned in ggtt with incorrect alignment:" | |
3714 | " offset=%08x %08x, req.alignment=%llx, req.map_and_fenceable=%d," | |
3715 | " obj->map_and_fenceable=%d\n", | |
3716 | upper_32_bits(vma->node.start), | |
3717 | lower_32_bits(vma->node.start), | |
3718 | alignment, | |
3719 | !!(flags & PIN_MAPPABLE), | |
3720 | obj->map_and_fenceable); | |
3721 | ret = i915_vma_unbind(vma); | |
3722 | if (ret) | |
3723 | return ret; | |
3724 | } | |
3725 | ||
3726 | return i915_vma_pin(vma, size, alignment, flags | PIN_GLOBAL); | |
ec7adb6e JL |
3727 | } |
3728 | ||
673a394b | 3729 | void |
e6617330 TU |
3730 | i915_gem_object_ggtt_unpin_view(struct drm_i915_gem_object *obj, |
3731 | const struct i915_ggtt_view *view) | |
673a394b | 3732 | { |
de895082 | 3733 | i915_vma_unpin(i915_gem_obj_to_ggtt_view(obj, view)); |
673a394b EA |
3734 | } |
3735 | ||
3fdc13c7 CW |
3736 | static __always_inline unsigned __busy_read_flag(unsigned int id) |
3737 | { | |
3738 | /* Note that we could alias engines in the execbuf API, but | |
3739 | * that would be very unwise as it prevents userspace from | |
3740 | * fine control over engine selection. Ahem. | |
3741 | * | |
3742 | * This should be something like EXEC_MAX_ENGINE instead of | |
3743 | * I915_NUM_ENGINES. | |
3744 | */ | |
3745 | BUILD_BUG_ON(I915_NUM_ENGINES > 16); | |
3746 | return 0x10000 << id; | |
3747 | } | |
3748 | ||
3749 | static __always_inline unsigned int __busy_write_id(unsigned int id) | |
3750 | { | |
3751 | return id; | |
3752 | } | |
3753 | ||
3754 | static __always_inline unsigned | |
3755 | __busy_set_if_active(const struct i915_gem_active *active, | |
3756 | unsigned int (*flag)(unsigned int id)) | |
3757 | { | |
3758 | /* For more discussion about the barriers and locking concerns, | |
3759 | * see __i915_gem_active_get_rcu(). | |
3760 | */ | |
3761 | do { | |
3762 | struct drm_i915_gem_request *request; | |
3763 | unsigned int id; | |
3764 | ||
3765 | request = rcu_dereference(active->request); | |
3766 | if (!request || i915_gem_request_completed(request)) | |
3767 | return 0; | |
3768 | ||
3769 | id = request->engine->exec_id; | |
3770 | ||
3771 | /* Check that the pointer wasn't reassigned and overwritten. */ | |
3772 | if (request == rcu_access_pointer(active->request)) | |
3773 | return flag(id); | |
3774 | } while (1); | |
3775 | } | |
3776 | ||
3777 | static inline unsigned | |
3778 | busy_check_reader(const struct i915_gem_active *active) | |
3779 | { | |
3780 | return __busy_set_if_active(active, __busy_read_flag); | |
3781 | } | |
3782 | ||
3783 | static inline unsigned | |
3784 | busy_check_writer(const struct i915_gem_active *active) | |
3785 | { | |
3786 | return __busy_set_if_active(active, __busy_write_id); | |
3787 | } | |
3788 | ||
673a394b EA |
3789 | int |
3790 | i915_gem_busy_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 3791 | struct drm_file *file) |
673a394b EA |
3792 | { |
3793 | struct drm_i915_gem_busy *args = data; | |
05394f39 | 3794 | struct drm_i915_gem_object *obj; |
3fdc13c7 | 3795 | unsigned long active; |
673a394b | 3796 | |
03ac0642 | 3797 | obj = i915_gem_object_lookup(file, args->handle); |
3fdc13c7 CW |
3798 | if (!obj) |
3799 | return -ENOENT; | |
d1b851fc | 3800 | |
426960be | 3801 | args->busy = 0; |
3fdc13c7 CW |
3802 | active = __I915_BO_ACTIVE(obj); |
3803 | if (active) { | |
3804 | int idx; | |
426960be | 3805 | |
3fdc13c7 CW |
3806 | /* Yes, the lookups are intentionally racy. |
3807 | * | |
3808 | * First, we cannot simply rely on __I915_BO_ACTIVE. We have | |
3809 | * to regard the value as stale and as our ABI guarantees | |
3810 | * forward progress, we confirm the status of each active | |
3811 | * request with the hardware. | |
3812 | * | |
3813 | * Even though we guard the pointer lookup by RCU, that only | |
3814 | * guarantees that the pointer and its contents remain | |
3815 | * dereferencable and does *not* mean that the request we | |
3816 | * have is the same as the one being tracked by the object. | |
3817 | * | |
3818 | * Consider that we lookup the request just as it is being | |
3819 | * retired and freed. We take a local copy of the pointer, | |
3820 | * but before we add its engine into the busy set, the other | |
3821 | * thread reallocates it and assigns it to a task on another | |
3822 | * engine with a fresh and incomplete seqno. | |
3823 | * | |
3824 | * So after we lookup the engine's id, we double check that | |
3825 | * the active request is the same and only then do we add it | |
3826 | * into the busy set. | |
3827 | */ | |
3828 | rcu_read_lock(); | |
3829 | ||
3830 | for_each_active(active, idx) | |
3831 | args->busy |= busy_check_reader(&obj->last_read[idx]); | |
3832 | ||
3833 | /* For ABI sanity, we only care that the write engine is in | |
3834 | * the set of read engines. This is ensured by the ordering | |
3835 | * of setting last_read/last_write in i915_vma_move_to_active, | |
3836 | * and then in reverse in retire. | |
3837 | * | |
3838 | * We don't care that the set of active read/write engines | |
3839 | * may change during construction of the result, as it is | |
3840 | * equally liable to change before userspace can inspect | |
3841 | * the result. | |
3842 | */ | |
3843 | args->busy |= busy_check_writer(&obj->last_write); | |
3844 | ||
3845 | rcu_read_unlock(); | |
426960be | 3846 | } |
673a394b | 3847 | |
3fdc13c7 CW |
3848 | i915_gem_object_put_unlocked(obj); |
3849 | return 0; | |
673a394b EA |
3850 | } |
3851 | ||
3852 | int | |
3853 | i915_gem_throttle_ioctl(struct drm_device *dev, void *data, | |
3854 | struct drm_file *file_priv) | |
3855 | { | |
0206e353 | 3856 | return i915_gem_ring_throttle(dev, file_priv); |
673a394b EA |
3857 | } |
3858 | ||
3ef94daa CW |
3859 | int |
3860 | i915_gem_madvise_ioctl(struct drm_device *dev, void *data, | |
3861 | struct drm_file *file_priv) | |
3862 | { | |
fac5e23e | 3863 | struct drm_i915_private *dev_priv = to_i915(dev); |
3ef94daa | 3864 | struct drm_i915_gem_madvise *args = data; |
05394f39 | 3865 | struct drm_i915_gem_object *obj; |
76c1dec1 | 3866 | int ret; |
3ef94daa CW |
3867 | |
3868 | switch (args->madv) { | |
3869 | case I915_MADV_DONTNEED: | |
3870 | case I915_MADV_WILLNEED: | |
3871 | break; | |
3872 | default: | |
3873 | return -EINVAL; | |
3874 | } | |
3875 | ||
1d7cfea1 CW |
3876 | ret = i915_mutex_lock_interruptible(dev); |
3877 | if (ret) | |
3878 | return ret; | |
3879 | ||
03ac0642 CW |
3880 | obj = i915_gem_object_lookup(file_priv, args->handle); |
3881 | if (!obj) { | |
1d7cfea1 CW |
3882 | ret = -ENOENT; |
3883 | goto unlock; | |
3ef94daa | 3884 | } |
3ef94daa | 3885 | |
656bfa3a DV |
3886 | if (obj->pages && |
3887 | obj->tiling_mode != I915_TILING_NONE && | |
3888 | dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES) { | |
3889 | if (obj->madv == I915_MADV_WILLNEED) | |
3890 | i915_gem_object_unpin_pages(obj); | |
3891 | if (args->madv == I915_MADV_WILLNEED) | |
3892 | i915_gem_object_pin_pages(obj); | |
3893 | } | |
3894 | ||
05394f39 CW |
3895 | if (obj->madv != __I915_MADV_PURGED) |
3896 | obj->madv = args->madv; | |
3ef94daa | 3897 | |
6c085a72 | 3898 | /* if the object is no longer attached, discard its backing storage */ |
be6a0376 | 3899 | if (obj->madv == I915_MADV_DONTNEED && obj->pages == NULL) |
2d7ef395 CW |
3900 | i915_gem_object_truncate(obj); |
3901 | ||
05394f39 | 3902 | args->retained = obj->madv != __I915_MADV_PURGED; |
bb6baf76 | 3903 | |
f8c417cd | 3904 | i915_gem_object_put(obj); |
1d7cfea1 | 3905 | unlock: |
3ef94daa | 3906 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 3907 | return ret; |
3ef94daa CW |
3908 | } |
3909 | ||
37e680a1 CW |
3910 | void i915_gem_object_init(struct drm_i915_gem_object *obj, |
3911 | const struct drm_i915_gem_object_ops *ops) | |
0327d6ba | 3912 | { |
b4716185 CW |
3913 | int i; |
3914 | ||
35c20a60 | 3915 | INIT_LIST_HEAD(&obj->global_list); |
666796da | 3916 | for (i = 0; i < I915_NUM_ENGINES; i++) |
fa545cbf CW |
3917 | init_request_active(&obj->last_read[i], |
3918 | i915_gem_object_retire__read); | |
3919 | init_request_active(&obj->last_write, | |
3920 | i915_gem_object_retire__write); | |
3921 | init_request_active(&obj->last_fence, NULL); | |
b25cb2f8 | 3922 | INIT_LIST_HEAD(&obj->obj_exec_link); |
2f633156 | 3923 | INIT_LIST_HEAD(&obj->vma_list); |
8d9d5744 | 3924 | INIT_LIST_HEAD(&obj->batch_pool_link); |
0327d6ba | 3925 | |
37e680a1 CW |
3926 | obj->ops = ops; |
3927 | ||
0327d6ba CW |
3928 | obj->fence_reg = I915_FENCE_REG_NONE; |
3929 | obj->madv = I915_MADV_WILLNEED; | |
0327d6ba | 3930 | |
f19ec8cb | 3931 | i915_gem_info_add_obj(to_i915(obj->base.dev), obj->base.size); |
0327d6ba CW |
3932 | } |
3933 | ||
37e680a1 | 3934 | static const struct drm_i915_gem_object_ops i915_gem_object_ops = { |
de472664 | 3935 | .flags = I915_GEM_OBJECT_HAS_STRUCT_PAGE, |
37e680a1 CW |
3936 | .get_pages = i915_gem_object_get_pages_gtt, |
3937 | .put_pages = i915_gem_object_put_pages_gtt, | |
3938 | }; | |
3939 | ||
d37cd8a8 | 3940 | struct drm_i915_gem_object *i915_gem_object_create(struct drm_device *dev, |
05394f39 | 3941 | size_t size) |
ac52bc56 | 3942 | { |
c397b908 | 3943 | struct drm_i915_gem_object *obj; |
5949eac4 | 3944 | struct address_space *mapping; |
1a240d4d | 3945 | gfp_t mask; |
fe3db79b | 3946 | int ret; |
ac52bc56 | 3947 | |
42dcedd4 | 3948 | obj = i915_gem_object_alloc(dev); |
c397b908 | 3949 | if (obj == NULL) |
fe3db79b | 3950 | return ERR_PTR(-ENOMEM); |
673a394b | 3951 | |
fe3db79b CW |
3952 | ret = drm_gem_object_init(dev, &obj->base, size); |
3953 | if (ret) | |
3954 | goto fail; | |
673a394b | 3955 | |
bed1ea95 CW |
3956 | mask = GFP_HIGHUSER | __GFP_RECLAIMABLE; |
3957 | if (IS_CRESTLINE(dev) || IS_BROADWATER(dev)) { | |
3958 | /* 965gm cannot relocate objects above 4GiB. */ | |
3959 | mask &= ~__GFP_HIGHMEM; | |
3960 | mask |= __GFP_DMA32; | |
3961 | } | |
3962 | ||
496ad9aa | 3963 | mapping = file_inode(obj->base.filp)->i_mapping; |
bed1ea95 | 3964 | mapping_set_gfp_mask(mapping, mask); |
5949eac4 | 3965 | |
37e680a1 | 3966 | i915_gem_object_init(obj, &i915_gem_object_ops); |
73aa808f | 3967 | |
c397b908 DV |
3968 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; |
3969 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; | |
673a394b | 3970 | |
3d29b842 ED |
3971 | if (HAS_LLC(dev)) { |
3972 | /* On some devices, we can have the GPU use the LLC (the CPU | |
a1871112 EA |
3973 | * cache) for about a 10% performance improvement |
3974 | * compared to uncached. Graphics requests other than | |
3975 | * display scanout are coherent with the CPU in | |
3976 | * accessing this cache. This means in this mode we | |
3977 | * don't need to clflush on the CPU side, and on the | |
3978 | * GPU side we only need to flush internal caches to | |
3979 | * get data visible to the CPU. | |
3980 | * | |
3981 | * However, we maintain the display planes as UC, and so | |
3982 | * need to rebind when first used as such. | |
3983 | */ | |
3984 | obj->cache_level = I915_CACHE_LLC; | |
3985 | } else | |
3986 | obj->cache_level = I915_CACHE_NONE; | |
3987 | ||
d861e338 DV |
3988 | trace_i915_gem_object_create(obj); |
3989 | ||
05394f39 | 3990 | return obj; |
fe3db79b CW |
3991 | |
3992 | fail: | |
3993 | i915_gem_object_free(obj); | |
3994 | ||
3995 | return ERR_PTR(ret); | |
c397b908 DV |
3996 | } |
3997 | ||
340fbd8c CW |
3998 | static bool discard_backing_storage(struct drm_i915_gem_object *obj) |
3999 | { | |
4000 | /* If we are the last user of the backing storage (be it shmemfs | |
4001 | * pages or stolen etc), we know that the pages are going to be | |
4002 | * immediately released. In this case, we can then skip copying | |
4003 | * back the contents from the GPU. | |
4004 | */ | |
4005 | ||
4006 | if (obj->madv != I915_MADV_WILLNEED) | |
4007 | return false; | |
4008 | ||
4009 | if (obj->base.filp == NULL) | |
4010 | return true; | |
4011 | ||
4012 | /* At first glance, this looks racy, but then again so would be | |
4013 | * userspace racing mmap against close. However, the first external | |
4014 | * reference to the filp can only be obtained through the | |
4015 | * i915_gem_mmap_ioctl() which safeguards us against the user | |
4016 | * acquiring such a reference whilst we are in the middle of | |
4017 | * freeing the object. | |
4018 | */ | |
4019 | return atomic_long_read(&obj->base.filp->f_count) == 1; | |
4020 | } | |
4021 | ||
1488fc08 | 4022 | void i915_gem_free_object(struct drm_gem_object *gem_obj) |
673a394b | 4023 | { |
1488fc08 | 4024 | struct drm_i915_gem_object *obj = to_intel_bo(gem_obj); |
05394f39 | 4025 | struct drm_device *dev = obj->base.dev; |
fac5e23e | 4026 | struct drm_i915_private *dev_priv = to_i915(dev); |
07fe0b12 | 4027 | struct i915_vma *vma, *next; |
673a394b | 4028 | |
f65c9168 PZ |
4029 | intel_runtime_pm_get(dev_priv); |
4030 | ||
26e12f89 CW |
4031 | trace_i915_gem_object_destroy(obj); |
4032 | ||
b1f788c6 CW |
4033 | /* All file-owned VMA should have been released by this point through |
4034 | * i915_gem_close_object(), or earlier by i915_gem_context_close(). | |
4035 | * However, the object may also be bound into the global GTT (e.g. | |
4036 | * older GPUs without per-process support, or for direct access through | |
4037 | * the GTT either for the user or for scanout). Those VMA still need to | |
4038 | * unbound now. | |
4039 | */ | |
1c7f4bca | 4040 | list_for_each_entry_safe(vma, next, &obj->vma_list, obj_link) { |
3272db53 | 4041 | GEM_BUG_ON(!i915_vma_is_ggtt(vma)); |
b1f788c6 | 4042 | GEM_BUG_ON(i915_vma_is_active(vma)); |
3272db53 | 4043 | vma->flags &= ~I915_VMA_PIN_MASK; |
b1f788c6 | 4044 | i915_vma_close(vma); |
1488fc08 | 4045 | } |
15717de2 | 4046 | GEM_BUG_ON(obj->bind_count); |
1488fc08 | 4047 | |
1d64ae71 BW |
4048 | /* Stolen objects don't hold a ref, but do hold pin count. Fix that up |
4049 | * before progressing. */ | |
4050 | if (obj->stolen) | |
4051 | i915_gem_object_unpin_pages(obj); | |
4052 | ||
faf5bf0a | 4053 | WARN_ON(atomic_read(&obj->frontbuffer_bits)); |
a071fa00 | 4054 | |
656bfa3a DV |
4055 | if (obj->pages && obj->madv == I915_MADV_WILLNEED && |
4056 | dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES && | |
4057 | obj->tiling_mode != I915_TILING_NONE) | |
4058 | i915_gem_object_unpin_pages(obj); | |
4059 | ||
401c29f6 BW |
4060 | if (WARN_ON(obj->pages_pin_count)) |
4061 | obj->pages_pin_count = 0; | |
340fbd8c | 4062 | if (discard_backing_storage(obj)) |
5537252b | 4063 | obj->madv = I915_MADV_DONTNEED; |
37e680a1 | 4064 | i915_gem_object_put_pages(obj); |
de151cf6 | 4065 | |
9da3da66 CW |
4066 | BUG_ON(obj->pages); |
4067 | ||
2f745ad3 CW |
4068 | if (obj->base.import_attach) |
4069 | drm_prime_gem_destroy(&obj->base, NULL); | |
de151cf6 | 4070 | |
5cc9ed4b CW |
4071 | if (obj->ops->release) |
4072 | obj->ops->release(obj); | |
4073 | ||
05394f39 CW |
4074 | drm_gem_object_release(&obj->base); |
4075 | i915_gem_info_remove_obj(dev_priv, obj->base.size); | |
c397b908 | 4076 | |
05394f39 | 4077 | kfree(obj->bit_17); |
42dcedd4 | 4078 | i915_gem_object_free(obj); |
f65c9168 PZ |
4079 | |
4080 | intel_runtime_pm_put(dev_priv); | |
673a394b EA |
4081 | } |
4082 | ||
ec7adb6e JL |
4083 | struct i915_vma *i915_gem_obj_to_vma(struct drm_i915_gem_object *obj, |
4084 | struct i915_address_space *vm) | |
e656a6cb DV |
4085 | { |
4086 | struct i915_vma *vma; | |
1c7f4bca | 4087 | list_for_each_entry(vma, &obj->vma_list, obj_link) { |
1b683729 TU |
4088 | if (vma->ggtt_view.type == I915_GGTT_VIEW_NORMAL && |
4089 | vma->vm == vm) | |
e656a6cb | 4090 | return vma; |
ec7adb6e JL |
4091 | } |
4092 | return NULL; | |
4093 | } | |
4094 | ||
4095 | struct i915_vma *i915_gem_obj_to_ggtt_view(struct drm_i915_gem_object *obj, | |
4096 | const struct i915_ggtt_view *view) | |
4097 | { | |
ec7adb6e | 4098 | struct i915_vma *vma; |
e656a6cb | 4099 | |
598b9ec8 | 4100 | GEM_BUG_ON(!view); |
ec7adb6e | 4101 | |
1c7f4bca | 4102 | list_for_each_entry(vma, &obj->vma_list, obj_link) |
3272db53 CW |
4103 | if (i915_vma_is_ggtt(vma) && |
4104 | i915_ggtt_view_equal(&vma->ggtt_view, view)) | |
ec7adb6e | 4105 | return vma; |
e656a6cb DV |
4106 | return NULL; |
4107 | } | |
4108 | ||
dcff85c8 | 4109 | int i915_gem_suspend(struct drm_device *dev) |
29105ccc | 4110 | { |
fac5e23e | 4111 | struct drm_i915_private *dev_priv = to_i915(dev); |
dcff85c8 | 4112 | int ret; |
28dfe52a | 4113 | |
54b4f68f CW |
4114 | intel_suspend_gt_powersave(dev_priv); |
4115 | ||
45c5f202 | 4116 | mutex_lock(&dev->struct_mutex); |
5ab57c70 CW |
4117 | |
4118 | /* We have to flush all the executing contexts to main memory so | |
4119 | * that they can saved in the hibernation image. To ensure the last | |
4120 | * context image is coherent, we have to switch away from it. That | |
4121 | * leaves the dev_priv->kernel_context still active when | |
4122 | * we actually suspend, and its image in memory may not match the GPU | |
4123 | * state. Fortunately, the kernel_context is disposable and we do | |
4124 | * not rely on its state. | |
4125 | */ | |
4126 | ret = i915_gem_switch_to_kernel_context(dev_priv); | |
4127 | if (ret) | |
4128 | goto err; | |
4129 | ||
dcff85c8 | 4130 | ret = i915_gem_wait_for_idle(dev_priv, true); |
f7403347 | 4131 | if (ret) |
45c5f202 | 4132 | goto err; |
f7403347 | 4133 | |
c033666a | 4134 | i915_gem_retire_requests(dev_priv); |
673a394b | 4135 | |
b2e862d0 | 4136 | i915_gem_context_lost(dev_priv); |
45c5f202 CW |
4137 | mutex_unlock(&dev->struct_mutex); |
4138 | ||
737b1506 | 4139 | cancel_delayed_work_sync(&dev_priv->gpu_error.hangcheck_work); |
67d97da3 CW |
4140 | cancel_delayed_work_sync(&dev_priv->gt.retire_work); |
4141 | flush_delayed_work(&dev_priv->gt.idle_work); | |
29105ccc | 4142 | |
bdcf120b CW |
4143 | /* Assert that we sucessfully flushed all the work and |
4144 | * reset the GPU back to its idle, low power state. | |
4145 | */ | |
67d97da3 | 4146 | WARN_ON(dev_priv->gt.awake); |
bdcf120b | 4147 | |
673a394b | 4148 | return 0; |
45c5f202 CW |
4149 | |
4150 | err: | |
4151 | mutex_unlock(&dev->struct_mutex); | |
4152 | return ret; | |
673a394b EA |
4153 | } |
4154 | ||
5ab57c70 CW |
4155 | void i915_gem_resume(struct drm_device *dev) |
4156 | { | |
4157 | struct drm_i915_private *dev_priv = to_i915(dev); | |
4158 | ||
4159 | mutex_lock(&dev->struct_mutex); | |
4160 | i915_gem_restore_gtt_mappings(dev); | |
4161 | ||
4162 | /* As we didn't flush the kernel context before suspend, we cannot | |
4163 | * guarantee that the context image is complete. So let's just reset | |
4164 | * it and start again. | |
4165 | */ | |
4166 | if (i915.enable_execlists) | |
4167 | intel_lr_context_reset(dev_priv, dev_priv->kernel_context); | |
4168 | ||
4169 | mutex_unlock(&dev->struct_mutex); | |
4170 | } | |
4171 | ||
f691e2f4 DV |
4172 | void i915_gem_init_swizzling(struct drm_device *dev) |
4173 | { | |
fac5e23e | 4174 | struct drm_i915_private *dev_priv = to_i915(dev); |
f691e2f4 | 4175 | |
11782b02 | 4176 | if (INTEL_INFO(dev)->gen < 5 || |
f691e2f4 DV |
4177 | dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE) |
4178 | return; | |
4179 | ||
4180 | I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) | | |
4181 | DISP_TILE_SURFACE_SWIZZLING); | |
4182 | ||
11782b02 DV |
4183 | if (IS_GEN5(dev)) |
4184 | return; | |
4185 | ||
f691e2f4 DV |
4186 | I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_SWZCTL); |
4187 | if (IS_GEN6(dev)) | |
6b26c86d | 4188 | I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB)); |
8782e26c | 4189 | else if (IS_GEN7(dev)) |
6b26c86d | 4190 | I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB)); |
31a5336e BW |
4191 | else if (IS_GEN8(dev)) |
4192 | I915_WRITE(GAMTARBMODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_BDW)); | |
8782e26c BW |
4193 | else |
4194 | BUG(); | |
f691e2f4 | 4195 | } |
e21af88d | 4196 | |
81e7f200 VS |
4197 | static void init_unused_ring(struct drm_device *dev, u32 base) |
4198 | { | |
fac5e23e | 4199 | struct drm_i915_private *dev_priv = to_i915(dev); |
81e7f200 VS |
4200 | |
4201 | I915_WRITE(RING_CTL(base), 0); | |
4202 | I915_WRITE(RING_HEAD(base), 0); | |
4203 | I915_WRITE(RING_TAIL(base), 0); | |
4204 | I915_WRITE(RING_START(base), 0); | |
4205 | } | |
4206 | ||
4207 | static void init_unused_rings(struct drm_device *dev) | |
4208 | { | |
4209 | if (IS_I830(dev)) { | |
4210 | init_unused_ring(dev, PRB1_BASE); | |
4211 | init_unused_ring(dev, SRB0_BASE); | |
4212 | init_unused_ring(dev, SRB1_BASE); | |
4213 | init_unused_ring(dev, SRB2_BASE); | |
4214 | init_unused_ring(dev, SRB3_BASE); | |
4215 | } else if (IS_GEN2(dev)) { | |
4216 | init_unused_ring(dev, SRB0_BASE); | |
4217 | init_unused_ring(dev, SRB1_BASE); | |
4218 | } else if (IS_GEN3(dev)) { | |
4219 | init_unused_ring(dev, PRB1_BASE); | |
4220 | init_unused_ring(dev, PRB2_BASE); | |
4221 | } | |
4222 | } | |
4223 | ||
4fc7c971 BW |
4224 | int |
4225 | i915_gem_init_hw(struct drm_device *dev) | |
4226 | { | |
fac5e23e | 4227 | struct drm_i915_private *dev_priv = to_i915(dev); |
e2f80391 | 4228 | struct intel_engine_cs *engine; |
d200cda6 | 4229 | int ret; |
4fc7c971 | 4230 | |
5e4f5189 CW |
4231 | /* Double layer security blanket, see i915_gem_init() */ |
4232 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); | |
4233 | ||
3accaf7e | 4234 | if (HAS_EDRAM(dev) && INTEL_GEN(dev_priv) < 9) |
05e21cc4 | 4235 | I915_WRITE(HSW_IDICR, I915_READ(HSW_IDICR) | IDIHASHMSK(0xf)); |
4fc7c971 | 4236 | |
0bf21347 VS |
4237 | if (IS_HASWELL(dev)) |
4238 | I915_WRITE(MI_PREDICATE_RESULT_2, IS_HSW_GT3(dev) ? | |
4239 | LOWER_SLICE_ENABLED : LOWER_SLICE_DISABLED); | |
9435373e | 4240 | |
88a2b2a3 | 4241 | if (HAS_PCH_NOP(dev)) { |
6ba844b0 DV |
4242 | if (IS_IVYBRIDGE(dev)) { |
4243 | u32 temp = I915_READ(GEN7_MSG_CTL); | |
4244 | temp &= ~(WAIT_FOR_PCH_FLR_ACK | WAIT_FOR_PCH_RESET_ACK); | |
4245 | I915_WRITE(GEN7_MSG_CTL, temp); | |
4246 | } else if (INTEL_INFO(dev)->gen >= 7) { | |
4247 | u32 temp = I915_READ(HSW_NDE_RSTWRN_OPT); | |
4248 | temp &= ~RESET_PCH_HANDSHAKE_ENABLE; | |
4249 | I915_WRITE(HSW_NDE_RSTWRN_OPT, temp); | |
4250 | } | |
88a2b2a3 BW |
4251 | } |
4252 | ||
4fc7c971 BW |
4253 | i915_gem_init_swizzling(dev); |
4254 | ||
d5abdfda DV |
4255 | /* |
4256 | * At least 830 can leave some of the unused rings | |
4257 | * "active" (ie. head != tail) after resume which | |
4258 | * will prevent c3 entry. Makes sure all unused rings | |
4259 | * are totally idle. | |
4260 | */ | |
4261 | init_unused_rings(dev); | |
4262 | ||
ed54c1a1 | 4263 | BUG_ON(!dev_priv->kernel_context); |
90638cc1 | 4264 | |
4ad2fd88 JH |
4265 | ret = i915_ppgtt_init_hw(dev); |
4266 | if (ret) { | |
4267 | DRM_ERROR("PPGTT enable HW failed %d\n", ret); | |
4268 | goto out; | |
4269 | } | |
4270 | ||
4271 | /* Need to do basic initialisation of all rings first: */ | |
b4ac5afc | 4272 | for_each_engine(engine, dev_priv) { |
e2f80391 | 4273 | ret = engine->init_hw(engine); |
35a57ffb | 4274 | if (ret) |
5e4f5189 | 4275 | goto out; |
35a57ffb | 4276 | } |
99433931 | 4277 | |
0ccdacf6 PA |
4278 | intel_mocs_init_l3cc_table(dev); |
4279 | ||
33a732f4 | 4280 | /* We can't enable contexts until all firmware is loaded */ |
e556f7c1 DG |
4281 | ret = intel_guc_setup(dev); |
4282 | if (ret) | |
4283 | goto out; | |
33a732f4 | 4284 | |
5e4f5189 CW |
4285 | out: |
4286 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); | |
2fa48d8d | 4287 | return ret; |
8187a2b7 ZN |
4288 | } |
4289 | ||
39df9190 CW |
4290 | bool intel_sanitize_semaphores(struct drm_i915_private *dev_priv, int value) |
4291 | { | |
4292 | if (INTEL_INFO(dev_priv)->gen < 6) | |
4293 | return false; | |
4294 | ||
4295 | /* TODO: make semaphores and Execlists play nicely together */ | |
4296 | if (i915.enable_execlists) | |
4297 | return false; | |
4298 | ||
4299 | if (value >= 0) | |
4300 | return value; | |
4301 | ||
4302 | #ifdef CONFIG_INTEL_IOMMU | |
4303 | /* Enable semaphores on SNB when IO remapping is off */ | |
4304 | if (INTEL_INFO(dev_priv)->gen == 6 && intel_iommu_gfx_mapped) | |
4305 | return false; | |
4306 | #endif | |
4307 | ||
4308 | return true; | |
4309 | } | |
4310 | ||
1070a42b CW |
4311 | int i915_gem_init(struct drm_device *dev) |
4312 | { | |
fac5e23e | 4313 | struct drm_i915_private *dev_priv = to_i915(dev); |
1070a42b CW |
4314 | int ret; |
4315 | ||
1070a42b | 4316 | mutex_lock(&dev->struct_mutex); |
d62b4892 | 4317 | |
a83014d3 | 4318 | if (!i915.enable_execlists) { |
7e37f889 | 4319 | dev_priv->gt.cleanup_engine = intel_engine_cleanup; |
454afebd | 4320 | } else { |
117897f4 | 4321 | dev_priv->gt.cleanup_engine = intel_logical_ring_cleanup; |
a83014d3 OM |
4322 | } |
4323 | ||
5e4f5189 CW |
4324 | /* This is just a security blanket to placate dragons. |
4325 | * On some systems, we very sporadically observe that the first TLBs | |
4326 | * used by the CS may be stale, despite us poking the TLB reset. If | |
4327 | * we hold the forcewake during initialisation these problems | |
4328 | * just magically go away. | |
4329 | */ | |
4330 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); | |
4331 | ||
72778cb2 | 4332 | i915_gem_init_userptr(dev_priv); |
f6b9d5ca CW |
4333 | |
4334 | ret = i915_gem_init_ggtt(dev_priv); | |
4335 | if (ret) | |
4336 | goto out_unlock; | |
d62b4892 | 4337 | |
2fa48d8d | 4338 | ret = i915_gem_context_init(dev); |
7bcc3777 JN |
4339 | if (ret) |
4340 | goto out_unlock; | |
2fa48d8d | 4341 | |
8b3e2d36 | 4342 | ret = intel_engines_init(dev); |
35a57ffb | 4343 | if (ret) |
7bcc3777 | 4344 | goto out_unlock; |
2fa48d8d | 4345 | |
1070a42b | 4346 | ret = i915_gem_init_hw(dev); |
60990320 | 4347 | if (ret == -EIO) { |
7e21d648 | 4348 | /* Allow engine initialisation to fail by marking the GPU as |
60990320 CW |
4349 | * wedged. But we only want to do this where the GPU is angry, |
4350 | * for all other failure, such as an allocation failure, bail. | |
4351 | */ | |
4352 | DRM_ERROR("Failed to initialize GPU, declaring it wedged\n"); | |
805de8f4 | 4353 | atomic_or(I915_WEDGED, &dev_priv->gpu_error.reset_counter); |
60990320 | 4354 | ret = 0; |
1070a42b | 4355 | } |
7bcc3777 JN |
4356 | |
4357 | out_unlock: | |
5e4f5189 | 4358 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); |
60990320 | 4359 | mutex_unlock(&dev->struct_mutex); |
1070a42b | 4360 | |
60990320 | 4361 | return ret; |
1070a42b CW |
4362 | } |
4363 | ||
8187a2b7 | 4364 | void |
117897f4 | 4365 | i915_gem_cleanup_engines(struct drm_device *dev) |
8187a2b7 | 4366 | { |
fac5e23e | 4367 | struct drm_i915_private *dev_priv = to_i915(dev); |
e2f80391 | 4368 | struct intel_engine_cs *engine; |
8187a2b7 | 4369 | |
b4ac5afc | 4370 | for_each_engine(engine, dev_priv) |
117897f4 | 4371 | dev_priv->gt.cleanup_engine(engine); |
8187a2b7 ZN |
4372 | } |
4373 | ||
64193406 | 4374 | static void |
666796da | 4375 | init_engine_lists(struct intel_engine_cs *engine) |
64193406 | 4376 | { |
0bc40be8 | 4377 | INIT_LIST_HEAD(&engine->request_list); |
64193406 CW |
4378 | } |
4379 | ||
40ae4e16 ID |
4380 | void |
4381 | i915_gem_load_init_fences(struct drm_i915_private *dev_priv) | |
4382 | { | |
91c8a326 | 4383 | struct drm_device *dev = &dev_priv->drm; |
40ae4e16 ID |
4384 | |
4385 | if (INTEL_INFO(dev_priv)->gen >= 7 && !IS_VALLEYVIEW(dev_priv) && | |
4386 | !IS_CHERRYVIEW(dev_priv)) | |
4387 | dev_priv->num_fence_regs = 32; | |
4388 | else if (INTEL_INFO(dev_priv)->gen >= 4 || IS_I945G(dev_priv) || | |
4389 | IS_I945GM(dev_priv) || IS_G33(dev_priv)) | |
4390 | dev_priv->num_fence_regs = 16; | |
4391 | else | |
4392 | dev_priv->num_fence_regs = 8; | |
4393 | ||
c033666a | 4394 | if (intel_vgpu_active(dev_priv)) |
40ae4e16 ID |
4395 | dev_priv->num_fence_regs = |
4396 | I915_READ(vgtif_reg(avail_rs.fence_num)); | |
4397 | ||
4398 | /* Initialize fence registers to zero */ | |
4399 | i915_gem_restore_fences(dev); | |
4400 | ||
4401 | i915_gem_detect_bit_6_swizzle(dev); | |
4402 | } | |
4403 | ||
673a394b | 4404 | void |
d64aa096 | 4405 | i915_gem_load_init(struct drm_device *dev) |
673a394b | 4406 | { |
fac5e23e | 4407 | struct drm_i915_private *dev_priv = to_i915(dev); |
42dcedd4 CW |
4408 | int i; |
4409 | ||
efab6d8d | 4410 | dev_priv->objects = |
42dcedd4 CW |
4411 | kmem_cache_create("i915_gem_object", |
4412 | sizeof(struct drm_i915_gem_object), 0, | |
4413 | SLAB_HWCACHE_ALIGN, | |
4414 | NULL); | |
e20d2ab7 CW |
4415 | dev_priv->vmas = |
4416 | kmem_cache_create("i915_gem_vma", | |
4417 | sizeof(struct i915_vma), 0, | |
4418 | SLAB_HWCACHE_ALIGN, | |
4419 | NULL); | |
efab6d8d CW |
4420 | dev_priv->requests = |
4421 | kmem_cache_create("i915_gem_request", | |
4422 | sizeof(struct drm_i915_gem_request), 0, | |
0eafec6d CW |
4423 | SLAB_HWCACHE_ALIGN | |
4424 | SLAB_RECLAIM_ACCOUNT | | |
4425 | SLAB_DESTROY_BY_RCU, | |
efab6d8d | 4426 | NULL); |
673a394b | 4427 | |
a33afea5 | 4428 | INIT_LIST_HEAD(&dev_priv->context_list); |
6c085a72 CW |
4429 | INIT_LIST_HEAD(&dev_priv->mm.unbound_list); |
4430 | INIT_LIST_HEAD(&dev_priv->mm.bound_list); | |
a09ba7fa | 4431 | INIT_LIST_HEAD(&dev_priv->mm.fence_list); |
666796da TU |
4432 | for (i = 0; i < I915_NUM_ENGINES; i++) |
4433 | init_engine_lists(&dev_priv->engine[i]); | |
4b9de737 | 4434 | for (i = 0; i < I915_MAX_NUM_FENCES; i++) |
007cc8ac | 4435 | INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list); |
67d97da3 | 4436 | INIT_DELAYED_WORK(&dev_priv->gt.retire_work, |
673a394b | 4437 | i915_gem_retire_work_handler); |
67d97da3 | 4438 | INIT_DELAYED_WORK(&dev_priv->gt.idle_work, |
b29c19b6 | 4439 | i915_gem_idle_work_handler); |
1f15b76f | 4440 | init_waitqueue_head(&dev_priv->gpu_error.wait_queue); |
1f83fee0 | 4441 | init_waitqueue_head(&dev_priv->gpu_error.reset_queue); |
31169714 | 4442 | |
72bfa19c CW |
4443 | dev_priv->relative_constants_mode = I915_EXEC_CONSTANTS_REL_GENERAL; |
4444 | ||
19b2dbde | 4445 | INIT_LIST_HEAD(&dev_priv->mm.fence_list); |
10ed13e4 | 4446 | |
6b95a207 | 4447 | init_waitqueue_head(&dev_priv->pending_flip_queue); |
17250b71 | 4448 | |
ce453d81 CW |
4449 | dev_priv->mm.interruptible = true; |
4450 | ||
b5add959 | 4451 | spin_lock_init(&dev_priv->fb_tracking.lock); |
673a394b | 4452 | } |
71acb5eb | 4453 | |
d64aa096 ID |
4454 | void i915_gem_load_cleanup(struct drm_device *dev) |
4455 | { | |
4456 | struct drm_i915_private *dev_priv = to_i915(dev); | |
4457 | ||
4458 | kmem_cache_destroy(dev_priv->requests); | |
4459 | kmem_cache_destroy(dev_priv->vmas); | |
4460 | kmem_cache_destroy(dev_priv->objects); | |
0eafec6d CW |
4461 | |
4462 | /* And ensure that our DESTROY_BY_RCU slabs are truly destroyed */ | |
4463 | rcu_barrier(); | |
d64aa096 ID |
4464 | } |
4465 | ||
461fb99c CW |
4466 | int i915_gem_freeze_late(struct drm_i915_private *dev_priv) |
4467 | { | |
4468 | struct drm_i915_gem_object *obj; | |
4469 | ||
4470 | /* Called just before we write the hibernation image. | |
4471 | * | |
4472 | * We need to update the domain tracking to reflect that the CPU | |
4473 | * will be accessing all the pages to create and restore from the | |
4474 | * hibernation, and so upon restoration those pages will be in the | |
4475 | * CPU domain. | |
4476 | * | |
4477 | * To make sure the hibernation image contains the latest state, | |
4478 | * we update that state just before writing out the image. | |
4479 | */ | |
4480 | ||
4481 | list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) { | |
4482 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; | |
4483 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; | |
4484 | } | |
4485 | ||
4486 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) { | |
4487 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; | |
4488 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; | |
4489 | } | |
4490 | ||
4491 | return 0; | |
4492 | } | |
4493 | ||
f787a5f5 | 4494 | void i915_gem_release(struct drm_device *dev, struct drm_file *file) |
b962442e | 4495 | { |
f787a5f5 | 4496 | struct drm_i915_file_private *file_priv = file->driver_priv; |
15f7bbc7 | 4497 | struct drm_i915_gem_request *request; |
b962442e EA |
4498 | |
4499 | /* Clean up our request list when the client is going away, so that | |
4500 | * later retire_requests won't dereference our soon-to-be-gone | |
4501 | * file_priv. | |
4502 | */ | |
1c25595f | 4503 | spin_lock(&file_priv->mm.lock); |
15f7bbc7 | 4504 | list_for_each_entry(request, &file_priv->mm.request_list, client_list) |
f787a5f5 | 4505 | request->file_priv = NULL; |
1c25595f | 4506 | spin_unlock(&file_priv->mm.lock); |
b29c19b6 | 4507 | |
2e1b8730 | 4508 | if (!list_empty(&file_priv->rps.link)) { |
8d3afd7d | 4509 | spin_lock(&to_i915(dev)->rps.client_lock); |
2e1b8730 | 4510 | list_del(&file_priv->rps.link); |
8d3afd7d | 4511 | spin_unlock(&to_i915(dev)->rps.client_lock); |
1854d5ca | 4512 | } |
b29c19b6 CW |
4513 | } |
4514 | ||
4515 | int i915_gem_open(struct drm_device *dev, struct drm_file *file) | |
4516 | { | |
4517 | struct drm_i915_file_private *file_priv; | |
e422b888 | 4518 | int ret; |
b29c19b6 CW |
4519 | |
4520 | DRM_DEBUG_DRIVER("\n"); | |
4521 | ||
4522 | file_priv = kzalloc(sizeof(*file_priv), GFP_KERNEL); | |
4523 | if (!file_priv) | |
4524 | return -ENOMEM; | |
4525 | ||
4526 | file->driver_priv = file_priv; | |
f19ec8cb | 4527 | file_priv->dev_priv = to_i915(dev); |
ab0e7ff9 | 4528 | file_priv->file = file; |
2e1b8730 | 4529 | INIT_LIST_HEAD(&file_priv->rps.link); |
b29c19b6 CW |
4530 | |
4531 | spin_lock_init(&file_priv->mm.lock); | |
4532 | INIT_LIST_HEAD(&file_priv->mm.request_list); | |
b29c19b6 | 4533 | |
c80ff16e | 4534 | file_priv->bsd_engine = -1; |
de1add36 | 4535 | |
e422b888 BW |
4536 | ret = i915_gem_context_open(dev, file); |
4537 | if (ret) | |
4538 | kfree(file_priv); | |
b29c19b6 | 4539 | |
e422b888 | 4540 | return ret; |
b29c19b6 CW |
4541 | } |
4542 | ||
b680c37a DV |
4543 | /** |
4544 | * i915_gem_track_fb - update frontbuffer tracking | |
d9072a3e GT |
4545 | * @old: current GEM buffer for the frontbuffer slots |
4546 | * @new: new GEM buffer for the frontbuffer slots | |
4547 | * @frontbuffer_bits: bitmask of frontbuffer slots | |
b680c37a DV |
4548 | * |
4549 | * This updates the frontbuffer tracking bits @frontbuffer_bits by clearing them | |
4550 | * from @old and setting them in @new. Both @old and @new can be NULL. | |
4551 | */ | |
a071fa00 DV |
4552 | void i915_gem_track_fb(struct drm_i915_gem_object *old, |
4553 | struct drm_i915_gem_object *new, | |
4554 | unsigned frontbuffer_bits) | |
4555 | { | |
faf5bf0a CW |
4556 | /* Control of individual bits within the mask are guarded by |
4557 | * the owning plane->mutex, i.e. we can never see concurrent | |
4558 | * manipulation of individual bits. But since the bitfield as a whole | |
4559 | * is updated using RMW, we need to use atomics in order to update | |
4560 | * the bits. | |
4561 | */ | |
4562 | BUILD_BUG_ON(INTEL_FRONTBUFFER_BITS_PER_PIPE * I915_MAX_PIPES > | |
4563 | sizeof(atomic_t) * BITS_PER_BYTE); | |
4564 | ||
a071fa00 | 4565 | if (old) { |
faf5bf0a CW |
4566 | WARN_ON(!(atomic_read(&old->frontbuffer_bits) & frontbuffer_bits)); |
4567 | atomic_andnot(frontbuffer_bits, &old->frontbuffer_bits); | |
a071fa00 DV |
4568 | } |
4569 | ||
4570 | if (new) { | |
faf5bf0a CW |
4571 | WARN_ON(atomic_read(&new->frontbuffer_bits) & frontbuffer_bits); |
4572 | atomic_or(frontbuffer_bits, &new->frontbuffer_bits); | |
a071fa00 DV |
4573 | } |
4574 | } | |
4575 | ||
a70a3148 | 4576 | /* All the new VM stuff */ |
088e0df4 MT |
4577 | u64 i915_gem_obj_offset(struct drm_i915_gem_object *o, |
4578 | struct i915_address_space *vm) | |
a70a3148 | 4579 | { |
fac5e23e | 4580 | struct drm_i915_private *dev_priv = to_i915(o->base.dev); |
a70a3148 BW |
4581 | struct i915_vma *vma; |
4582 | ||
896ab1a5 | 4583 | WARN_ON(vm == &dev_priv->mm.aliasing_ppgtt->base); |
a70a3148 | 4584 | |
1c7f4bca | 4585 | list_for_each_entry(vma, &o->vma_list, obj_link) { |
3272db53 | 4586 | if (i915_vma_is_ggtt(vma) && |
ec7adb6e JL |
4587 | vma->ggtt_view.type != I915_GGTT_VIEW_NORMAL) |
4588 | continue; | |
4589 | if (vma->vm == vm) | |
a70a3148 | 4590 | return vma->node.start; |
a70a3148 | 4591 | } |
ec7adb6e | 4592 | |
f25748ea DV |
4593 | WARN(1, "%s vma for this object not found.\n", |
4594 | i915_is_ggtt(vm) ? "global" : "ppgtt"); | |
a70a3148 BW |
4595 | return -1; |
4596 | } | |
4597 | ||
088e0df4 MT |
4598 | u64 i915_gem_obj_ggtt_offset_view(struct drm_i915_gem_object *o, |
4599 | const struct i915_ggtt_view *view) | |
a70a3148 BW |
4600 | { |
4601 | struct i915_vma *vma; | |
4602 | ||
1c7f4bca | 4603 | list_for_each_entry(vma, &o->vma_list, obj_link) |
3272db53 CW |
4604 | if (i915_vma_is_ggtt(vma) && |
4605 | i915_ggtt_view_equal(&vma->ggtt_view, view)) | |
ec7adb6e JL |
4606 | return vma->node.start; |
4607 | ||
5678ad73 | 4608 | WARN(1, "global vma for this object not found. (view=%u)\n", view->type); |
ec7adb6e JL |
4609 | return -1; |
4610 | } | |
4611 | ||
4612 | bool i915_gem_obj_bound(struct drm_i915_gem_object *o, | |
4613 | struct i915_address_space *vm) | |
4614 | { | |
4615 | struct i915_vma *vma; | |
4616 | ||
1c7f4bca | 4617 | list_for_each_entry(vma, &o->vma_list, obj_link) { |
3272db53 | 4618 | if (i915_vma_is_ggtt(vma) && |
ec7adb6e JL |
4619 | vma->ggtt_view.type != I915_GGTT_VIEW_NORMAL) |
4620 | continue; | |
4621 | if (vma->vm == vm && drm_mm_node_allocated(&vma->node)) | |
4622 | return true; | |
4623 | } | |
4624 | ||
4625 | return false; | |
4626 | } | |
4627 | ||
4628 | bool i915_gem_obj_ggtt_bound_view(struct drm_i915_gem_object *o, | |
9abc4648 | 4629 | const struct i915_ggtt_view *view) |
ec7adb6e | 4630 | { |
ec7adb6e JL |
4631 | struct i915_vma *vma; |
4632 | ||
1c7f4bca | 4633 | list_for_each_entry(vma, &o->vma_list, obj_link) |
3272db53 | 4634 | if (i915_vma_is_ggtt(vma) && |
9abc4648 | 4635 | i915_ggtt_view_equal(&vma->ggtt_view, view) && |
fe14d5f4 | 4636 | drm_mm_node_allocated(&vma->node)) |
a70a3148 BW |
4637 | return true; |
4638 | ||
4639 | return false; | |
4640 | } | |
4641 | ||
8da32727 | 4642 | unsigned long i915_gem_obj_ggtt_size(struct drm_i915_gem_object *o) |
a70a3148 | 4643 | { |
a70a3148 BW |
4644 | struct i915_vma *vma; |
4645 | ||
8da32727 | 4646 | GEM_BUG_ON(list_empty(&o->vma_list)); |
a70a3148 | 4647 | |
1c7f4bca | 4648 | list_for_each_entry(vma, &o->vma_list, obj_link) { |
3272db53 | 4649 | if (i915_vma_is_ggtt(vma) && |
8da32727 | 4650 | vma->ggtt_view.type == I915_GGTT_VIEW_NORMAL) |
a70a3148 | 4651 | return vma->node.size; |
ec7adb6e | 4652 | } |
8da32727 | 4653 | |
a70a3148 BW |
4654 | return 0; |
4655 | } | |
4656 | ||
ec7adb6e | 4657 | bool i915_gem_obj_is_pinned(struct drm_i915_gem_object *obj) |
5c2abbea BW |
4658 | { |
4659 | struct i915_vma *vma; | |
1c7f4bca | 4660 | list_for_each_entry(vma, &obj->vma_list, obj_link) |
20dfbde4 | 4661 | if (i915_vma_is_pinned(vma)) |
ec7adb6e | 4662 | return true; |
a6631ae1 | 4663 | |
ec7adb6e | 4664 | return false; |
5c2abbea | 4665 | } |
ea70299d | 4666 | |
033908ae DG |
4667 | /* Like i915_gem_object_get_page(), but mark the returned page dirty */ |
4668 | struct page * | |
4669 | i915_gem_object_get_dirty_page(struct drm_i915_gem_object *obj, int n) | |
4670 | { | |
4671 | struct page *page; | |
4672 | ||
4673 | /* Only default objects have per-page dirty tracking */ | |
b9bcd14a | 4674 | if (WARN_ON(!i915_gem_object_has_struct_page(obj))) |
033908ae DG |
4675 | return NULL; |
4676 | ||
4677 | page = i915_gem_object_get_page(obj, n); | |
4678 | set_page_dirty(page); | |
4679 | return page; | |
4680 | } | |
4681 | ||
ea70299d DG |
4682 | /* Allocate a new GEM object and fill it with the supplied data */ |
4683 | struct drm_i915_gem_object * | |
4684 | i915_gem_object_create_from_data(struct drm_device *dev, | |
4685 | const void *data, size_t size) | |
4686 | { | |
4687 | struct drm_i915_gem_object *obj; | |
4688 | struct sg_table *sg; | |
4689 | size_t bytes; | |
4690 | int ret; | |
4691 | ||
d37cd8a8 | 4692 | obj = i915_gem_object_create(dev, round_up(size, PAGE_SIZE)); |
fe3db79b | 4693 | if (IS_ERR(obj)) |
ea70299d DG |
4694 | return obj; |
4695 | ||
4696 | ret = i915_gem_object_set_to_cpu_domain(obj, true); | |
4697 | if (ret) | |
4698 | goto fail; | |
4699 | ||
4700 | ret = i915_gem_object_get_pages(obj); | |
4701 | if (ret) | |
4702 | goto fail; | |
4703 | ||
4704 | i915_gem_object_pin_pages(obj); | |
4705 | sg = obj->pages; | |
4706 | bytes = sg_copy_from_buffer(sg->sgl, sg->nents, (void *)data, size); | |
9e7d18c0 | 4707 | obj->dirty = 1; /* Backing store is now out of date */ |
ea70299d DG |
4708 | i915_gem_object_unpin_pages(obj); |
4709 | ||
4710 | if (WARN_ON(bytes != size)) { | |
4711 | DRM_ERROR("Incomplete copy, wrote %zu of %zu", bytes, size); | |
4712 | ret = -EFAULT; | |
4713 | goto fail; | |
4714 | } | |
4715 | ||
4716 | return obj; | |
4717 | ||
4718 | fail: | |
f8c417cd | 4719 | i915_gem_object_put(obj); |
ea70299d DG |
4720 | return ERR_PTR(ret); |
4721 | } |