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Commit | Line | Data |
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673a394b EA |
1 | /* |
2 | * Copyright © 2008 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | * | |
26 | */ | |
27 | ||
760285e7 DH |
28 | #include <drm/drmP.h> |
29 | #include <drm/i915_drm.h> | |
673a394b | 30 | #include "i915_drv.h" |
1c5d22f7 | 31 | #include "i915_trace.h" |
652c393a | 32 | #include "intel_drv.h" |
5949eac4 | 33 | #include <linux/shmem_fs.h> |
5a0e3ad6 | 34 | #include <linux/slab.h> |
673a394b | 35 | #include <linux/swap.h> |
79e53945 | 36 | #include <linux/pci.h> |
1286ff73 | 37 | #include <linux/dma-buf.h> |
673a394b | 38 | |
05394f39 CW |
39 | static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj); |
40 | static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj); | |
88241785 CW |
41 | static __must_check int i915_gem_object_bind_to_gtt(struct drm_i915_gem_object *obj, |
42 | unsigned alignment, | |
86a1ee26 CW |
43 | bool map_and_fenceable, |
44 | bool nonblocking); | |
05394f39 CW |
45 | static int i915_gem_phys_pwrite(struct drm_device *dev, |
46 | struct drm_i915_gem_object *obj, | |
71acb5eb | 47 | struct drm_i915_gem_pwrite *args, |
05394f39 | 48 | struct drm_file *file); |
673a394b | 49 | |
61050808 CW |
50 | static void i915_gem_write_fence(struct drm_device *dev, int reg, |
51 | struct drm_i915_gem_object *obj); | |
52 | static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj, | |
53 | struct drm_i915_fence_reg *fence, | |
54 | bool enable); | |
55 | ||
17250b71 | 56 | static int i915_gem_inactive_shrink(struct shrinker *shrinker, |
1495f230 | 57 | struct shrink_control *sc); |
6c085a72 CW |
58 | static long i915_gem_purge(struct drm_i915_private *dev_priv, long target); |
59 | static void i915_gem_shrink_all(struct drm_i915_private *dev_priv); | |
8c59967c | 60 | static void i915_gem_object_truncate(struct drm_i915_gem_object *obj); |
31169714 | 61 | |
61050808 CW |
62 | static inline void i915_gem_object_fence_lost(struct drm_i915_gem_object *obj) |
63 | { | |
64 | if (obj->tiling_mode) | |
65 | i915_gem_release_mmap(obj); | |
66 | ||
67 | /* As we do not have an associated fence register, we will force | |
68 | * a tiling change if we ever need to acquire one. | |
69 | */ | |
5d82e3e6 | 70 | obj->fence_dirty = false; |
61050808 CW |
71 | obj->fence_reg = I915_FENCE_REG_NONE; |
72 | } | |
73 | ||
73aa808f CW |
74 | /* some bookkeeping */ |
75 | static void i915_gem_info_add_obj(struct drm_i915_private *dev_priv, | |
76 | size_t size) | |
77 | { | |
78 | dev_priv->mm.object_count++; | |
79 | dev_priv->mm.object_memory += size; | |
80 | } | |
81 | ||
82 | static void i915_gem_info_remove_obj(struct drm_i915_private *dev_priv, | |
83 | size_t size) | |
84 | { | |
85 | dev_priv->mm.object_count--; | |
86 | dev_priv->mm.object_memory -= size; | |
87 | } | |
88 | ||
21dd3734 | 89 | static int |
33196ded | 90 | i915_gem_wait_for_error(struct i915_gpu_error *error) |
30dbf0c0 | 91 | { |
30dbf0c0 CW |
92 | int ret; |
93 | ||
1f83fee0 DV |
94 | #define EXIT_COND (!i915_reset_in_progress(error)) |
95 | if (EXIT_COND) | |
30dbf0c0 CW |
96 | return 0; |
97 | ||
1f83fee0 DV |
98 | /* GPU is already declared terminally dead, give up. */ |
99 | if (i915_terminally_wedged(error)) | |
100 | return -EIO; | |
101 | ||
0a6759c6 DV |
102 | /* |
103 | * Only wait 10 seconds for the gpu reset to complete to avoid hanging | |
104 | * userspace. If it takes that long something really bad is going on and | |
105 | * we should simply try to bail out and fail as gracefully as possible. | |
106 | */ | |
1f83fee0 DV |
107 | ret = wait_event_interruptible_timeout(error->reset_queue, |
108 | EXIT_COND, | |
109 | 10*HZ); | |
0a6759c6 DV |
110 | if (ret == 0) { |
111 | DRM_ERROR("Timed out waiting for the gpu reset to complete\n"); | |
112 | return -EIO; | |
113 | } else if (ret < 0) { | |
30dbf0c0 | 114 | return ret; |
0a6759c6 | 115 | } |
1f83fee0 | 116 | #undef EXIT_COND |
30dbf0c0 | 117 | |
21dd3734 | 118 | return 0; |
30dbf0c0 CW |
119 | } |
120 | ||
54cf91dc | 121 | int i915_mutex_lock_interruptible(struct drm_device *dev) |
76c1dec1 | 122 | { |
33196ded | 123 | struct drm_i915_private *dev_priv = dev->dev_private; |
76c1dec1 CW |
124 | int ret; |
125 | ||
33196ded | 126 | ret = i915_gem_wait_for_error(&dev_priv->gpu_error); |
76c1dec1 CW |
127 | if (ret) |
128 | return ret; | |
129 | ||
130 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
131 | if (ret) | |
132 | return ret; | |
133 | ||
23bc5982 | 134 | WARN_ON(i915_verify_lists(dev)); |
76c1dec1 CW |
135 | return 0; |
136 | } | |
30dbf0c0 | 137 | |
7d1c4804 | 138 | static inline bool |
05394f39 | 139 | i915_gem_object_is_inactive(struct drm_i915_gem_object *obj) |
7d1c4804 | 140 | { |
6c085a72 | 141 | return obj->gtt_space && !obj->active; |
7d1c4804 CW |
142 | } |
143 | ||
79e53945 JB |
144 | int |
145 | i915_gem_init_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 146 | struct drm_file *file) |
79e53945 | 147 | { |
93d18799 | 148 | struct drm_i915_private *dev_priv = dev->dev_private; |
79e53945 | 149 | struct drm_i915_gem_init *args = data; |
2021746e | 150 | |
7bb6fb8d DV |
151 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
152 | return -ENODEV; | |
153 | ||
2021746e CW |
154 | if (args->gtt_start >= args->gtt_end || |
155 | (args->gtt_end | args->gtt_start) & (PAGE_SIZE - 1)) | |
156 | return -EINVAL; | |
79e53945 | 157 | |
f534bc0b DV |
158 | /* GEM with user mode setting was never supported on ilk and later. */ |
159 | if (INTEL_INFO(dev)->gen >= 5) | |
160 | return -ENODEV; | |
161 | ||
79e53945 | 162 | mutex_lock(&dev->struct_mutex); |
d7e5008f BW |
163 | i915_gem_setup_global_gtt(dev, args->gtt_start, args->gtt_end, |
164 | args->gtt_end); | |
93d18799 | 165 | dev_priv->gtt.mappable_end = args->gtt_end; |
673a394b EA |
166 | mutex_unlock(&dev->struct_mutex); |
167 | ||
2021746e | 168 | return 0; |
673a394b EA |
169 | } |
170 | ||
5a125c3c EA |
171 | int |
172 | i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 173 | struct drm_file *file) |
5a125c3c | 174 | { |
73aa808f | 175 | struct drm_i915_private *dev_priv = dev->dev_private; |
5a125c3c | 176 | struct drm_i915_gem_get_aperture *args = data; |
6299f992 CW |
177 | struct drm_i915_gem_object *obj; |
178 | size_t pinned; | |
5a125c3c | 179 | |
6299f992 | 180 | pinned = 0; |
73aa808f | 181 | mutex_lock(&dev->struct_mutex); |
6c085a72 | 182 | list_for_each_entry(obj, &dev_priv->mm.bound_list, gtt_list) |
1b50247a CW |
183 | if (obj->pin_count) |
184 | pinned += obj->gtt_space->size; | |
73aa808f | 185 | mutex_unlock(&dev->struct_mutex); |
5a125c3c | 186 | |
5d4545ae | 187 | args->aper_size = dev_priv->gtt.total; |
0206e353 | 188 | args->aper_available_size = args->aper_size - pinned; |
6299f992 | 189 | |
5a125c3c EA |
190 | return 0; |
191 | } | |
192 | ||
42dcedd4 CW |
193 | void *i915_gem_object_alloc(struct drm_device *dev) |
194 | { | |
195 | struct drm_i915_private *dev_priv = dev->dev_private; | |
196 | return kmem_cache_alloc(dev_priv->slab, GFP_KERNEL | __GFP_ZERO); | |
197 | } | |
198 | ||
199 | void i915_gem_object_free(struct drm_i915_gem_object *obj) | |
200 | { | |
201 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; | |
202 | kmem_cache_free(dev_priv->slab, obj); | |
203 | } | |
204 | ||
ff72145b DA |
205 | static int |
206 | i915_gem_create(struct drm_file *file, | |
207 | struct drm_device *dev, | |
208 | uint64_t size, | |
209 | uint32_t *handle_p) | |
673a394b | 210 | { |
05394f39 | 211 | struct drm_i915_gem_object *obj; |
a1a2d1d3 PP |
212 | int ret; |
213 | u32 handle; | |
673a394b | 214 | |
ff72145b | 215 | size = roundup(size, PAGE_SIZE); |
8ffc0246 CW |
216 | if (size == 0) |
217 | return -EINVAL; | |
673a394b EA |
218 | |
219 | /* Allocate the new object */ | |
ff72145b | 220 | obj = i915_gem_alloc_object(dev, size); |
673a394b EA |
221 | if (obj == NULL) |
222 | return -ENOMEM; | |
223 | ||
05394f39 | 224 | ret = drm_gem_handle_create(file, &obj->base, &handle); |
1dfd9754 | 225 | if (ret) { |
05394f39 CW |
226 | drm_gem_object_release(&obj->base); |
227 | i915_gem_info_remove_obj(dev->dev_private, obj->base.size); | |
42dcedd4 | 228 | i915_gem_object_free(obj); |
673a394b | 229 | return ret; |
1dfd9754 | 230 | } |
673a394b | 231 | |
202f2fef | 232 | /* drop reference from allocate - handle holds it now */ |
05394f39 | 233 | drm_gem_object_unreference(&obj->base); |
202f2fef CW |
234 | trace_i915_gem_object_create(obj); |
235 | ||
ff72145b | 236 | *handle_p = handle; |
673a394b EA |
237 | return 0; |
238 | } | |
239 | ||
ff72145b DA |
240 | int |
241 | i915_gem_dumb_create(struct drm_file *file, | |
242 | struct drm_device *dev, | |
243 | struct drm_mode_create_dumb *args) | |
244 | { | |
245 | /* have to work out size/pitch and return them */ | |
ed0291fd | 246 | args->pitch = ALIGN(args->width * ((args->bpp + 7) / 8), 64); |
ff72145b DA |
247 | args->size = args->pitch * args->height; |
248 | return i915_gem_create(file, dev, | |
249 | args->size, &args->handle); | |
250 | } | |
251 | ||
252 | int i915_gem_dumb_destroy(struct drm_file *file, | |
253 | struct drm_device *dev, | |
254 | uint32_t handle) | |
255 | { | |
256 | return drm_gem_handle_delete(file, handle); | |
257 | } | |
258 | ||
259 | /** | |
260 | * Creates a new mm object and returns a handle to it. | |
261 | */ | |
262 | int | |
263 | i915_gem_create_ioctl(struct drm_device *dev, void *data, | |
264 | struct drm_file *file) | |
265 | { | |
266 | struct drm_i915_gem_create *args = data; | |
63ed2cb2 | 267 | |
ff72145b DA |
268 | return i915_gem_create(file, dev, |
269 | args->size, &args->handle); | |
270 | } | |
271 | ||
8461d226 DV |
272 | static inline int |
273 | __copy_to_user_swizzled(char __user *cpu_vaddr, | |
274 | const char *gpu_vaddr, int gpu_offset, | |
275 | int length) | |
276 | { | |
277 | int ret, cpu_offset = 0; | |
278 | ||
279 | while (length > 0) { | |
280 | int cacheline_end = ALIGN(gpu_offset + 1, 64); | |
281 | int this_length = min(cacheline_end - gpu_offset, length); | |
282 | int swizzled_gpu_offset = gpu_offset ^ 64; | |
283 | ||
284 | ret = __copy_to_user(cpu_vaddr + cpu_offset, | |
285 | gpu_vaddr + swizzled_gpu_offset, | |
286 | this_length); | |
287 | if (ret) | |
288 | return ret + length; | |
289 | ||
290 | cpu_offset += this_length; | |
291 | gpu_offset += this_length; | |
292 | length -= this_length; | |
293 | } | |
294 | ||
295 | return 0; | |
296 | } | |
297 | ||
8c59967c | 298 | static inline int |
4f0c7cfb BW |
299 | __copy_from_user_swizzled(char *gpu_vaddr, int gpu_offset, |
300 | const char __user *cpu_vaddr, | |
8c59967c DV |
301 | int length) |
302 | { | |
303 | int ret, cpu_offset = 0; | |
304 | ||
305 | while (length > 0) { | |
306 | int cacheline_end = ALIGN(gpu_offset + 1, 64); | |
307 | int this_length = min(cacheline_end - gpu_offset, length); | |
308 | int swizzled_gpu_offset = gpu_offset ^ 64; | |
309 | ||
310 | ret = __copy_from_user(gpu_vaddr + swizzled_gpu_offset, | |
311 | cpu_vaddr + cpu_offset, | |
312 | this_length); | |
313 | if (ret) | |
314 | return ret + length; | |
315 | ||
316 | cpu_offset += this_length; | |
317 | gpu_offset += this_length; | |
318 | length -= this_length; | |
319 | } | |
320 | ||
321 | return 0; | |
322 | } | |
323 | ||
d174bd64 DV |
324 | /* Per-page copy function for the shmem pread fastpath. |
325 | * Flushes invalid cachelines before reading the target if | |
326 | * needs_clflush is set. */ | |
eb01459f | 327 | static int |
d174bd64 DV |
328 | shmem_pread_fast(struct page *page, int shmem_page_offset, int page_length, |
329 | char __user *user_data, | |
330 | bool page_do_bit17_swizzling, bool needs_clflush) | |
331 | { | |
332 | char *vaddr; | |
333 | int ret; | |
334 | ||
e7e58eb5 | 335 | if (unlikely(page_do_bit17_swizzling)) |
d174bd64 DV |
336 | return -EINVAL; |
337 | ||
338 | vaddr = kmap_atomic(page); | |
339 | if (needs_clflush) | |
340 | drm_clflush_virt_range(vaddr + shmem_page_offset, | |
341 | page_length); | |
342 | ret = __copy_to_user_inatomic(user_data, | |
343 | vaddr + shmem_page_offset, | |
344 | page_length); | |
345 | kunmap_atomic(vaddr); | |
346 | ||
f60d7f0c | 347 | return ret ? -EFAULT : 0; |
d174bd64 DV |
348 | } |
349 | ||
23c18c71 DV |
350 | static void |
351 | shmem_clflush_swizzled_range(char *addr, unsigned long length, | |
352 | bool swizzled) | |
353 | { | |
e7e58eb5 | 354 | if (unlikely(swizzled)) { |
23c18c71 DV |
355 | unsigned long start = (unsigned long) addr; |
356 | unsigned long end = (unsigned long) addr + length; | |
357 | ||
358 | /* For swizzling simply ensure that we always flush both | |
359 | * channels. Lame, but simple and it works. Swizzled | |
360 | * pwrite/pread is far from a hotpath - current userspace | |
361 | * doesn't use it at all. */ | |
362 | start = round_down(start, 128); | |
363 | end = round_up(end, 128); | |
364 | ||
365 | drm_clflush_virt_range((void *)start, end - start); | |
366 | } else { | |
367 | drm_clflush_virt_range(addr, length); | |
368 | } | |
369 | ||
370 | } | |
371 | ||
d174bd64 DV |
372 | /* Only difference to the fast-path function is that this can handle bit17 |
373 | * and uses non-atomic copy and kmap functions. */ | |
374 | static int | |
375 | shmem_pread_slow(struct page *page, int shmem_page_offset, int page_length, | |
376 | char __user *user_data, | |
377 | bool page_do_bit17_swizzling, bool needs_clflush) | |
378 | { | |
379 | char *vaddr; | |
380 | int ret; | |
381 | ||
382 | vaddr = kmap(page); | |
383 | if (needs_clflush) | |
23c18c71 DV |
384 | shmem_clflush_swizzled_range(vaddr + shmem_page_offset, |
385 | page_length, | |
386 | page_do_bit17_swizzling); | |
d174bd64 DV |
387 | |
388 | if (page_do_bit17_swizzling) | |
389 | ret = __copy_to_user_swizzled(user_data, | |
390 | vaddr, shmem_page_offset, | |
391 | page_length); | |
392 | else | |
393 | ret = __copy_to_user(user_data, | |
394 | vaddr + shmem_page_offset, | |
395 | page_length); | |
396 | kunmap(page); | |
397 | ||
f60d7f0c | 398 | return ret ? - EFAULT : 0; |
d174bd64 DV |
399 | } |
400 | ||
eb01459f | 401 | static int |
dbf7bff0 DV |
402 | i915_gem_shmem_pread(struct drm_device *dev, |
403 | struct drm_i915_gem_object *obj, | |
404 | struct drm_i915_gem_pread *args, | |
405 | struct drm_file *file) | |
eb01459f | 406 | { |
8461d226 | 407 | char __user *user_data; |
eb01459f | 408 | ssize_t remain; |
8461d226 | 409 | loff_t offset; |
eb2c0c81 | 410 | int shmem_page_offset, page_length, ret = 0; |
8461d226 | 411 | int obj_do_bit17_swizzling, page_do_bit17_swizzling; |
96d79b52 | 412 | int prefaulted = 0; |
8489731c | 413 | int needs_clflush = 0; |
67d5a50c | 414 | struct sg_page_iter sg_iter; |
eb01459f | 415 | |
2bb4629a | 416 | user_data = to_user_ptr(args->data_ptr); |
eb01459f EA |
417 | remain = args->size; |
418 | ||
8461d226 | 419 | obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj); |
eb01459f | 420 | |
8489731c DV |
421 | if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU)) { |
422 | /* If we're not in the cpu read domain, set ourself into the gtt | |
423 | * read domain and manually flush cachelines (if required). This | |
424 | * optimizes for the case when the gpu will dirty the data | |
425 | * anyway again before the next pread happens. */ | |
426 | if (obj->cache_level == I915_CACHE_NONE) | |
427 | needs_clflush = 1; | |
6c085a72 CW |
428 | if (obj->gtt_space) { |
429 | ret = i915_gem_object_set_to_gtt_domain(obj, false); | |
430 | if (ret) | |
431 | return ret; | |
432 | } | |
8489731c | 433 | } |
eb01459f | 434 | |
f60d7f0c CW |
435 | ret = i915_gem_object_get_pages(obj); |
436 | if (ret) | |
437 | return ret; | |
438 | ||
439 | i915_gem_object_pin_pages(obj); | |
440 | ||
8461d226 | 441 | offset = args->offset; |
eb01459f | 442 | |
67d5a50c ID |
443 | for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, |
444 | offset >> PAGE_SHIFT) { | |
2db76d7c | 445 | struct page *page = sg_page_iter_page(&sg_iter); |
9da3da66 CW |
446 | |
447 | if (remain <= 0) | |
448 | break; | |
449 | ||
eb01459f EA |
450 | /* Operation in this page |
451 | * | |
eb01459f | 452 | * shmem_page_offset = offset within page in shmem file |
eb01459f EA |
453 | * page_length = bytes to copy for this page |
454 | */ | |
c8cbbb8b | 455 | shmem_page_offset = offset_in_page(offset); |
eb01459f EA |
456 | page_length = remain; |
457 | if ((shmem_page_offset + page_length) > PAGE_SIZE) | |
458 | page_length = PAGE_SIZE - shmem_page_offset; | |
eb01459f | 459 | |
8461d226 DV |
460 | page_do_bit17_swizzling = obj_do_bit17_swizzling && |
461 | (page_to_phys(page) & (1 << 17)) != 0; | |
462 | ||
d174bd64 DV |
463 | ret = shmem_pread_fast(page, shmem_page_offset, page_length, |
464 | user_data, page_do_bit17_swizzling, | |
465 | needs_clflush); | |
466 | if (ret == 0) | |
467 | goto next_page; | |
dbf7bff0 | 468 | |
dbf7bff0 DV |
469 | mutex_unlock(&dev->struct_mutex); |
470 | ||
96d79b52 | 471 | if (!prefaulted) { |
f56f821f | 472 | ret = fault_in_multipages_writeable(user_data, remain); |
96d79b52 DV |
473 | /* Userspace is tricking us, but we've already clobbered |
474 | * its pages with the prefault and promised to write the | |
475 | * data up to the first fault. Hence ignore any errors | |
476 | * and just continue. */ | |
477 | (void)ret; | |
478 | prefaulted = 1; | |
479 | } | |
eb01459f | 480 | |
d174bd64 DV |
481 | ret = shmem_pread_slow(page, shmem_page_offset, page_length, |
482 | user_data, page_do_bit17_swizzling, | |
483 | needs_clflush); | |
eb01459f | 484 | |
dbf7bff0 | 485 | mutex_lock(&dev->struct_mutex); |
f60d7f0c | 486 | |
dbf7bff0 | 487 | next_page: |
e5281ccd | 488 | mark_page_accessed(page); |
e5281ccd | 489 | |
f60d7f0c | 490 | if (ret) |
8461d226 | 491 | goto out; |
8461d226 | 492 | |
eb01459f | 493 | remain -= page_length; |
8461d226 | 494 | user_data += page_length; |
eb01459f EA |
495 | offset += page_length; |
496 | } | |
497 | ||
4f27b75d | 498 | out: |
f60d7f0c CW |
499 | i915_gem_object_unpin_pages(obj); |
500 | ||
eb01459f EA |
501 | return ret; |
502 | } | |
503 | ||
673a394b EA |
504 | /** |
505 | * Reads data from the object referenced by handle. | |
506 | * | |
507 | * On error, the contents of *data are undefined. | |
508 | */ | |
509 | int | |
510 | i915_gem_pread_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 511 | struct drm_file *file) |
673a394b EA |
512 | { |
513 | struct drm_i915_gem_pread *args = data; | |
05394f39 | 514 | struct drm_i915_gem_object *obj; |
35b62a89 | 515 | int ret = 0; |
673a394b | 516 | |
51311d0a CW |
517 | if (args->size == 0) |
518 | return 0; | |
519 | ||
520 | if (!access_ok(VERIFY_WRITE, | |
2bb4629a | 521 | to_user_ptr(args->data_ptr), |
51311d0a CW |
522 | args->size)) |
523 | return -EFAULT; | |
524 | ||
4f27b75d | 525 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 526 | if (ret) |
4f27b75d | 527 | return ret; |
673a394b | 528 | |
05394f39 | 529 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 530 | if (&obj->base == NULL) { |
1d7cfea1 CW |
531 | ret = -ENOENT; |
532 | goto unlock; | |
4f27b75d | 533 | } |
673a394b | 534 | |
7dcd2499 | 535 | /* Bounds check source. */ |
05394f39 CW |
536 | if (args->offset > obj->base.size || |
537 | args->size > obj->base.size - args->offset) { | |
ce9d419d | 538 | ret = -EINVAL; |
35b62a89 | 539 | goto out; |
ce9d419d CW |
540 | } |
541 | ||
1286ff73 DV |
542 | /* prime objects have no backing filp to GEM pread/pwrite |
543 | * pages from. | |
544 | */ | |
545 | if (!obj->base.filp) { | |
546 | ret = -EINVAL; | |
547 | goto out; | |
548 | } | |
549 | ||
db53a302 CW |
550 | trace_i915_gem_object_pread(obj, args->offset, args->size); |
551 | ||
dbf7bff0 | 552 | ret = i915_gem_shmem_pread(dev, obj, args, file); |
673a394b | 553 | |
35b62a89 | 554 | out: |
05394f39 | 555 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 556 | unlock: |
4f27b75d | 557 | mutex_unlock(&dev->struct_mutex); |
eb01459f | 558 | return ret; |
673a394b EA |
559 | } |
560 | ||
0839ccb8 KP |
561 | /* This is the fast write path which cannot handle |
562 | * page faults in the source data | |
9b7530cc | 563 | */ |
0839ccb8 KP |
564 | |
565 | static inline int | |
566 | fast_user_write(struct io_mapping *mapping, | |
567 | loff_t page_base, int page_offset, | |
568 | char __user *user_data, | |
569 | int length) | |
9b7530cc | 570 | { |
4f0c7cfb BW |
571 | void __iomem *vaddr_atomic; |
572 | void *vaddr; | |
0839ccb8 | 573 | unsigned long unwritten; |
9b7530cc | 574 | |
3e4d3af5 | 575 | vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base); |
4f0c7cfb BW |
576 | /* We can use the cpu mem copy function because this is X86. */ |
577 | vaddr = (void __force*)vaddr_atomic + page_offset; | |
578 | unwritten = __copy_from_user_inatomic_nocache(vaddr, | |
0839ccb8 | 579 | user_data, length); |
3e4d3af5 | 580 | io_mapping_unmap_atomic(vaddr_atomic); |
fbd5a26d | 581 | return unwritten; |
0839ccb8 KP |
582 | } |
583 | ||
3de09aa3 EA |
584 | /** |
585 | * This is the fast pwrite path, where we copy the data directly from the | |
586 | * user into the GTT, uncached. | |
587 | */ | |
673a394b | 588 | static int |
05394f39 CW |
589 | i915_gem_gtt_pwrite_fast(struct drm_device *dev, |
590 | struct drm_i915_gem_object *obj, | |
3de09aa3 | 591 | struct drm_i915_gem_pwrite *args, |
05394f39 | 592 | struct drm_file *file) |
673a394b | 593 | { |
0839ccb8 | 594 | drm_i915_private_t *dev_priv = dev->dev_private; |
673a394b | 595 | ssize_t remain; |
0839ccb8 | 596 | loff_t offset, page_base; |
673a394b | 597 | char __user *user_data; |
935aaa69 DV |
598 | int page_offset, page_length, ret; |
599 | ||
86a1ee26 | 600 | ret = i915_gem_object_pin(obj, 0, true, true); |
935aaa69 DV |
601 | if (ret) |
602 | goto out; | |
603 | ||
604 | ret = i915_gem_object_set_to_gtt_domain(obj, true); | |
605 | if (ret) | |
606 | goto out_unpin; | |
607 | ||
608 | ret = i915_gem_object_put_fence(obj); | |
609 | if (ret) | |
610 | goto out_unpin; | |
673a394b | 611 | |
2bb4629a | 612 | user_data = to_user_ptr(args->data_ptr); |
673a394b | 613 | remain = args->size; |
673a394b | 614 | |
05394f39 | 615 | offset = obj->gtt_offset + args->offset; |
673a394b EA |
616 | |
617 | while (remain > 0) { | |
618 | /* Operation in this page | |
619 | * | |
0839ccb8 KP |
620 | * page_base = page offset within aperture |
621 | * page_offset = offset within page | |
622 | * page_length = bytes to copy for this page | |
673a394b | 623 | */ |
c8cbbb8b CW |
624 | page_base = offset & PAGE_MASK; |
625 | page_offset = offset_in_page(offset); | |
0839ccb8 KP |
626 | page_length = remain; |
627 | if ((page_offset + remain) > PAGE_SIZE) | |
628 | page_length = PAGE_SIZE - page_offset; | |
629 | ||
0839ccb8 | 630 | /* If we get a fault while copying data, then (presumably) our |
3de09aa3 EA |
631 | * source page isn't available. Return the error and we'll |
632 | * retry in the slow path. | |
0839ccb8 | 633 | */ |
5d4545ae | 634 | if (fast_user_write(dev_priv->gtt.mappable, page_base, |
935aaa69 DV |
635 | page_offset, user_data, page_length)) { |
636 | ret = -EFAULT; | |
637 | goto out_unpin; | |
638 | } | |
673a394b | 639 | |
0839ccb8 KP |
640 | remain -= page_length; |
641 | user_data += page_length; | |
642 | offset += page_length; | |
673a394b | 643 | } |
673a394b | 644 | |
935aaa69 DV |
645 | out_unpin: |
646 | i915_gem_object_unpin(obj); | |
647 | out: | |
3de09aa3 | 648 | return ret; |
673a394b EA |
649 | } |
650 | ||
d174bd64 DV |
651 | /* Per-page copy function for the shmem pwrite fastpath. |
652 | * Flushes invalid cachelines before writing to the target if | |
653 | * needs_clflush_before is set and flushes out any written cachelines after | |
654 | * writing if needs_clflush is set. */ | |
3043c60c | 655 | static int |
d174bd64 DV |
656 | shmem_pwrite_fast(struct page *page, int shmem_page_offset, int page_length, |
657 | char __user *user_data, | |
658 | bool page_do_bit17_swizzling, | |
659 | bool needs_clflush_before, | |
660 | bool needs_clflush_after) | |
673a394b | 661 | { |
d174bd64 | 662 | char *vaddr; |
673a394b | 663 | int ret; |
3de09aa3 | 664 | |
e7e58eb5 | 665 | if (unlikely(page_do_bit17_swizzling)) |
d174bd64 | 666 | return -EINVAL; |
3de09aa3 | 667 | |
d174bd64 DV |
668 | vaddr = kmap_atomic(page); |
669 | if (needs_clflush_before) | |
670 | drm_clflush_virt_range(vaddr + shmem_page_offset, | |
671 | page_length); | |
672 | ret = __copy_from_user_inatomic_nocache(vaddr + shmem_page_offset, | |
673 | user_data, | |
674 | page_length); | |
675 | if (needs_clflush_after) | |
676 | drm_clflush_virt_range(vaddr + shmem_page_offset, | |
677 | page_length); | |
678 | kunmap_atomic(vaddr); | |
3de09aa3 | 679 | |
755d2218 | 680 | return ret ? -EFAULT : 0; |
3de09aa3 EA |
681 | } |
682 | ||
d174bd64 DV |
683 | /* Only difference to the fast-path function is that this can handle bit17 |
684 | * and uses non-atomic copy and kmap functions. */ | |
3043c60c | 685 | static int |
d174bd64 DV |
686 | shmem_pwrite_slow(struct page *page, int shmem_page_offset, int page_length, |
687 | char __user *user_data, | |
688 | bool page_do_bit17_swizzling, | |
689 | bool needs_clflush_before, | |
690 | bool needs_clflush_after) | |
673a394b | 691 | { |
d174bd64 DV |
692 | char *vaddr; |
693 | int ret; | |
e5281ccd | 694 | |
d174bd64 | 695 | vaddr = kmap(page); |
e7e58eb5 | 696 | if (unlikely(needs_clflush_before || page_do_bit17_swizzling)) |
23c18c71 DV |
697 | shmem_clflush_swizzled_range(vaddr + shmem_page_offset, |
698 | page_length, | |
699 | page_do_bit17_swizzling); | |
d174bd64 DV |
700 | if (page_do_bit17_swizzling) |
701 | ret = __copy_from_user_swizzled(vaddr, shmem_page_offset, | |
e5281ccd CW |
702 | user_data, |
703 | page_length); | |
d174bd64 DV |
704 | else |
705 | ret = __copy_from_user(vaddr + shmem_page_offset, | |
706 | user_data, | |
707 | page_length); | |
708 | if (needs_clflush_after) | |
23c18c71 DV |
709 | shmem_clflush_swizzled_range(vaddr + shmem_page_offset, |
710 | page_length, | |
711 | page_do_bit17_swizzling); | |
d174bd64 | 712 | kunmap(page); |
40123c1f | 713 | |
755d2218 | 714 | return ret ? -EFAULT : 0; |
40123c1f EA |
715 | } |
716 | ||
40123c1f | 717 | static int |
e244a443 DV |
718 | i915_gem_shmem_pwrite(struct drm_device *dev, |
719 | struct drm_i915_gem_object *obj, | |
720 | struct drm_i915_gem_pwrite *args, | |
721 | struct drm_file *file) | |
40123c1f | 722 | { |
40123c1f | 723 | ssize_t remain; |
8c59967c DV |
724 | loff_t offset; |
725 | char __user *user_data; | |
eb2c0c81 | 726 | int shmem_page_offset, page_length, ret = 0; |
8c59967c | 727 | int obj_do_bit17_swizzling, page_do_bit17_swizzling; |
e244a443 | 728 | int hit_slowpath = 0; |
58642885 DV |
729 | int needs_clflush_after = 0; |
730 | int needs_clflush_before = 0; | |
67d5a50c | 731 | struct sg_page_iter sg_iter; |
40123c1f | 732 | |
2bb4629a | 733 | user_data = to_user_ptr(args->data_ptr); |
40123c1f EA |
734 | remain = args->size; |
735 | ||
8c59967c | 736 | obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj); |
40123c1f | 737 | |
58642885 DV |
738 | if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) { |
739 | /* If we're not in the cpu write domain, set ourself into the gtt | |
740 | * write domain and manually flush cachelines (if required). This | |
741 | * optimizes for the case when the gpu will use the data | |
742 | * right away and we therefore have to clflush anyway. */ | |
743 | if (obj->cache_level == I915_CACHE_NONE) | |
744 | needs_clflush_after = 1; | |
6c085a72 CW |
745 | if (obj->gtt_space) { |
746 | ret = i915_gem_object_set_to_gtt_domain(obj, true); | |
747 | if (ret) | |
748 | return ret; | |
749 | } | |
58642885 DV |
750 | } |
751 | /* Same trick applies for invalidate partially written cachelines before | |
752 | * writing. */ | |
753 | if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU) | |
754 | && obj->cache_level == I915_CACHE_NONE) | |
755 | needs_clflush_before = 1; | |
756 | ||
755d2218 CW |
757 | ret = i915_gem_object_get_pages(obj); |
758 | if (ret) | |
759 | return ret; | |
760 | ||
761 | i915_gem_object_pin_pages(obj); | |
762 | ||
673a394b | 763 | offset = args->offset; |
05394f39 | 764 | obj->dirty = 1; |
673a394b | 765 | |
67d5a50c ID |
766 | for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, |
767 | offset >> PAGE_SHIFT) { | |
2db76d7c | 768 | struct page *page = sg_page_iter_page(&sg_iter); |
58642885 | 769 | int partial_cacheline_write; |
e5281ccd | 770 | |
9da3da66 CW |
771 | if (remain <= 0) |
772 | break; | |
773 | ||
40123c1f EA |
774 | /* Operation in this page |
775 | * | |
40123c1f | 776 | * shmem_page_offset = offset within page in shmem file |
40123c1f EA |
777 | * page_length = bytes to copy for this page |
778 | */ | |
c8cbbb8b | 779 | shmem_page_offset = offset_in_page(offset); |
40123c1f EA |
780 | |
781 | page_length = remain; | |
782 | if ((shmem_page_offset + page_length) > PAGE_SIZE) | |
783 | page_length = PAGE_SIZE - shmem_page_offset; | |
40123c1f | 784 | |
58642885 DV |
785 | /* If we don't overwrite a cacheline completely we need to be |
786 | * careful to have up-to-date data by first clflushing. Don't | |
787 | * overcomplicate things and flush the entire patch. */ | |
788 | partial_cacheline_write = needs_clflush_before && | |
789 | ((shmem_page_offset | page_length) | |
790 | & (boot_cpu_data.x86_clflush_size - 1)); | |
791 | ||
8c59967c DV |
792 | page_do_bit17_swizzling = obj_do_bit17_swizzling && |
793 | (page_to_phys(page) & (1 << 17)) != 0; | |
794 | ||
d174bd64 DV |
795 | ret = shmem_pwrite_fast(page, shmem_page_offset, page_length, |
796 | user_data, page_do_bit17_swizzling, | |
797 | partial_cacheline_write, | |
798 | needs_clflush_after); | |
799 | if (ret == 0) | |
800 | goto next_page; | |
e244a443 DV |
801 | |
802 | hit_slowpath = 1; | |
e244a443 | 803 | mutex_unlock(&dev->struct_mutex); |
d174bd64 DV |
804 | ret = shmem_pwrite_slow(page, shmem_page_offset, page_length, |
805 | user_data, page_do_bit17_swizzling, | |
806 | partial_cacheline_write, | |
807 | needs_clflush_after); | |
40123c1f | 808 | |
e244a443 | 809 | mutex_lock(&dev->struct_mutex); |
755d2218 | 810 | |
e244a443 | 811 | next_page: |
e5281ccd CW |
812 | set_page_dirty(page); |
813 | mark_page_accessed(page); | |
e5281ccd | 814 | |
755d2218 | 815 | if (ret) |
8c59967c | 816 | goto out; |
8c59967c | 817 | |
40123c1f | 818 | remain -= page_length; |
8c59967c | 819 | user_data += page_length; |
40123c1f | 820 | offset += page_length; |
673a394b EA |
821 | } |
822 | ||
fbd5a26d | 823 | out: |
755d2218 CW |
824 | i915_gem_object_unpin_pages(obj); |
825 | ||
e244a443 | 826 | if (hit_slowpath) { |
8dcf015e DV |
827 | /* |
828 | * Fixup: Flush cpu caches in case we didn't flush the dirty | |
829 | * cachelines in-line while writing and the object moved | |
830 | * out of the cpu write domain while we've dropped the lock. | |
831 | */ | |
832 | if (!needs_clflush_after && | |
833 | obj->base.write_domain != I915_GEM_DOMAIN_CPU) { | |
e244a443 | 834 | i915_gem_clflush_object(obj); |
e76e9aeb | 835 | i915_gem_chipset_flush(dev); |
e244a443 | 836 | } |
8c59967c | 837 | } |
673a394b | 838 | |
58642885 | 839 | if (needs_clflush_after) |
e76e9aeb | 840 | i915_gem_chipset_flush(dev); |
58642885 | 841 | |
40123c1f | 842 | return ret; |
673a394b EA |
843 | } |
844 | ||
845 | /** | |
846 | * Writes data to the object referenced by handle. | |
847 | * | |
848 | * On error, the contents of the buffer that were to be modified are undefined. | |
849 | */ | |
850 | int | |
851 | i915_gem_pwrite_ioctl(struct drm_device *dev, void *data, | |
fbd5a26d | 852 | struct drm_file *file) |
673a394b EA |
853 | { |
854 | struct drm_i915_gem_pwrite *args = data; | |
05394f39 | 855 | struct drm_i915_gem_object *obj; |
51311d0a CW |
856 | int ret; |
857 | ||
858 | if (args->size == 0) | |
859 | return 0; | |
860 | ||
861 | if (!access_ok(VERIFY_READ, | |
2bb4629a | 862 | to_user_ptr(args->data_ptr), |
51311d0a CW |
863 | args->size)) |
864 | return -EFAULT; | |
865 | ||
2bb4629a | 866 | ret = fault_in_multipages_readable(to_user_ptr(args->data_ptr), |
f56f821f | 867 | args->size); |
51311d0a CW |
868 | if (ret) |
869 | return -EFAULT; | |
673a394b | 870 | |
fbd5a26d | 871 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 872 | if (ret) |
fbd5a26d | 873 | return ret; |
1d7cfea1 | 874 | |
05394f39 | 875 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 876 | if (&obj->base == NULL) { |
1d7cfea1 CW |
877 | ret = -ENOENT; |
878 | goto unlock; | |
fbd5a26d | 879 | } |
673a394b | 880 | |
7dcd2499 | 881 | /* Bounds check destination. */ |
05394f39 CW |
882 | if (args->offset > obj->base.size || |
883 | args->size > obj->base.size - args->offset) { | |
ce9d419d | 884 | ret = -EINVAL; |
35b62a89 | 885 | goto out; |
ce9d419d CW |
886 | } |
887 | ||
1286ff73 DV |
888 | /* prime objects have no backing filp to GEM pread/pwrite |
889 | * pages from. | |
890 | */ | |
891 | if (!obj->base.filp) { | |
892 | ret = -EINVAL; | |
893 | goto out; | |
894 | } | |
895 | ||
db53a302 CW |
896 | trace_i915_gem_object_pwrite(obj, args->offset, args->size); |
897 | ||
935aaa69 | 898 | ret = -EFAULT; |
673a394b EA |
899 | /* We can only do the GTT pwrite on untiled buffers, as otherwise |
900 | * it would end up going through the fenced access, and we'll get | |
901 | * different detiling behavior between reading and writing. | |
902 | * pread/pwrite currently are reading and writing from the CPU | |
903 | * perspective, requiring manual detiling by the client. | |
904 | */ | |
5c0480f2 | 905 | if (obj->phys_obj) { |
fbd5a26d | 906 | ret = i915_gem_phys_pwrite(dev, obj, args, file); |
5c0480f2 DV |
907 | goto out; |
908 | } | |
909 | ||
86a1ee26 | 910 | if (obj->cache_level == I915_CACHE_NONE && |
c07496fa | 911 | obj->tiling_mode == I915_TILING_NONE && |
5c0480f2 | 912 | obj->base.write_domain != I915_GEM_DOMAIN_CPU) { |
fbd5a26d | 913 | ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file); |
935aaa69 DV |
914 | /* Note that the gtt paths might fail with non-page-backed user |
915 | * pointers (e.g. gtt mappings when moving data between | |
916 | * textures). Fallback to the shmem path in that case. */ | |
fbd5a26d | 917 | } |
673a394b | 918 | |
86a1ee26 | 919 | if (ret == -EFAULT || ret == -ENOSPC) |
935aaa69 | 920 | ret = i915_gem_shmem_pwrite(dev, obj, args, file); |
5c0480f2 | 921 | |
35b62a89 | 922 | out: |
05394f39 | 923 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 924 | unlock: |
fbd5a26d | 925 | mutex_unlock(&dev->struct_mutex); |
673a394b EA |
926 | return ret; |
927 | } | |
928 | ||
b361237b | 929 | int |
33196ded | 930 | i915_gem_check_wedge(struct i915_gpu_error *error, |
b361237b CW |
931 | bool interruptible) |
932 | { | |
1f83fee0 | 933 | if (i915_reset_in_progress(error)) { |
b361237b CW |
934 | /* Non-interruptible callers can't handle -EAGAIN, hence return |
935 | * -EIO unconditionally for these. */ | |
936 | if (!interruptible) | |
937 | return -EIO; | |
938 | ||
1f83fee0 DV |
939 | /* Recovery complete, but the reset failed ... */ |
940 | if (i915_terminally_wedged(error)) | |
b361237b CW |
941 | return -EIO; |
942 | ||
943 | return -EAGAIN; | |
944 | } | |
945 | ||
946 | return 0; | |
947 | } | |
948 | ||
949 | /* | |
950 | * Compare seqno against outstanding lazy request. Emit a request if they are | |
951 | * equal. | |
952 | */ | |
953 | static int | |
954 | i915_gem_check_olr(struct intel_ring_buffer *ring, u32 seqno) | |
955 | { | |
956 | int ret; | |
957 | ||
958 | BUG_ON(!mutex_is_locked(&ring->dev->struct_mutex)); | |
959 | ||
960 | ret = 0; | |
961 | if (seqno == ring->outstanding_lazy_request) | |
962 | ret = i915_add_request(ring, NULL, NULL); | |
963 | ||
964 | return ret; | |
965 | } | |
966 | ||
967 | /** | |
968 | * __wait_seqno - wait until execution of seqno has finished | |
969 | * @ring: the ring expected to report seqno | |
970 | * @seqno: duh! | |
f69061be | 971 | * @reset_counter: reset sequence associated with the given seqno |
b361237b CW |
972 | * @interruptible: do an interruptible wait (normally yes) |
973 | * @timeout: in - how long to wait (NULL forever); out - how much time remaining | |
974 | * | |
f69061be DV |
975 | * Note: It is of utmost importance that the passed in seqno and reset_counter |
976 | * values have been read by the caller in an smp safe manner. Where read-side | |
977 | * locks are involved, it is sufficient to read the reset_counter before | |
978 | * unlocking the lock that protects the seqno. For lockless tricks, the | |
979 | * reset_counter _must_ be read before, and an appropriate smp_rmb must be | |
980 | * inserted. | |
981 | * | |
b361237b CW |
982 | * Returns 0 if the seqno was found within the alloted time. Else returns the |
983 | * errno with remaining time filled in timeout argument. | |
984 | */ | |
985 | static int __wait_seqno(struct intel_ring_buffer *ring, u32 seqno, | |
f69061be | 986 | unsigned reset_counter, |
b361237b CW |
987 | bool interruptible, struct timespec *timeout) |
988 | { | |
989 | drm_i915_private_t *dev_priv = ring->dev->dev_private; | |
990 | struct timespec before, now, wait_time={1,0}; | |
991 | unsigned long timeout_jiffies; | |
992 | long end; | |
993 | bool wait_forever = true; | |
994 | int ret; | |
995 | ||
996 | if (i915_seqno_passed(ring->get_seqno(ring, true), seqno)) | |
997 | return 0; | |
998 | ||
999 | trace_i915_gem_request_wait_begin(ring, seqno); | |
1000 | ||
1001 | if (timeout != NULL) { | |
1002 | wait_time = *timeout; | |
1003 | wait_forever = false; | |
1004 | } | |
1005 | ||
1006 | timeout_jiffies = timespec_to_jiffies(&wait_time); | |
1007 | ||
1008 | if (WARN_ON(!ring->irq_get(ring))) | |
1009 | return -ENODEV; | |
1010 | ||
1011 | /* Record current time in case interrupted by signal, or wedged * */ | |
1012 | getrawmonotonic(&before); | |
1013 | ||
1014 | #define EXIT_COND \ | |
1015 | (i915_seqno_passed(ring->get_seqno(ring, false), seqno) || \ | |
f69061be DV |
1016 | i915_reset_in_progress(&dev_priv->gpu_error) || \ |
1017 | reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter)) | |
b361237b CW |
1018 | do { |
1019 | if (interruptible) | |
1020 | end = wait_event_interruptible_timeout(ring->irq_queue, | |
1021 | EXIT_COND, | |
1022 | timeout_jiffies); | |
1023 | else | |
1024 | end = wait_event_timeout(ring->irq_queue, EXIT_COND, | |
1025 | timeout_jiffies); | |
1026 | ||
f69061be DV |
1027 | /* We need to check whether any gpu reset happened in between |
1028 | * the caller grabbing the seqno and now ... */ | |
1029 | if (reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter)) | |
1030 | end = -EAGAIN; | |
1031 | ||
1032 | /* ... but upgrade the -EGAIN to an -EIO if the gpu is truely | |
1033 | * gone. */ | |
33196ded | 1034 | ret = i915_gem_check_wedge(&dev_priv->gpu_error, interruptible); |
b361237b CW |
1035 | if (ret) |
1036 | end = ret; | |
1037 | } while (end == 0 && wait_forever); | |
1038 | ||
1039 | getrawmonotonic(&now); | |
1040 | ||
1041 | ring->irq_put(ring); | |
1042 | trace_i915_gem_request_wait_end(ring, seqno); | |
1043 | #undef EXIT_COND | |
1044 | ||
1045 | if (timeout) { | |
1046 | struct timespec sleep_time = timespec_sub(now, before); | |
1047 | *timeout = timespec_sub(*timeout, sleep_time); | |
4f42f4ef CW |
1048 | if (!timespec_valid(timeout)) /* i.e. negative time remains */ |
1049 | set_normalized_timespec(timeout, 0, 0); | |
b361237b CW |
1050 | } |
1051 | ||
1052 | switch (end) { | |
1053 | case -EIO: | |
1054 | case -EAGAIN: /* Wedged */ | |
1055 | case -ERESTARTSYS: /* Signal */ | |
1056 | return (int)end; | |
1057 | case 0: /* Timeout */ | |
b361237b CW |
1058 | return -ETIME; |
1059 | default: /* Completed */ | |
1060 | WARN_ON(end < 0); /* We're not aware of other errors */ | |
1061 | return 0; | |
1062 | } | |
1063 | } | |
1064 | ||
1065 | /** | |
1066 | * Waits for a sequence number to be signaled, and cleans up the | |
1067 | * request and object lists appropriately for that event. | |
1068 | */ | |
1069 | int | |
1070 | i915_wait_seqno(struct intel_ring_buffer *ring, uint32_t seqno) | |
1071 | { | |
1072 | struct drm_device *dev = ring->dev; | |
1073 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1074 | bool interruptible = dev_priv->mm.interruptible; | |
1075 | int ret; | |
1076 | ||
1077 | BUG_ON(!mutex_is_locked(&dev->struct_mutex)); | |
1078 | BUG_ON(seqno == 0); | |
1079 | ||
33196ded | 1080 | ret = i915_gem_check_wedge(&dev_priv->gpu_error, interruptible); |
b361237b CW |
1081 | if (ret) |
1082 | return ret; | |
1083 | ||
1084 | ret = i915_gem_check_olr(ring, seqno); | |
1085 | if (ret) | |
1086 | return ret; | |
1087 | ||
f69061be DV |
1088 | return __wait_seqno(ring, seqno, |
1089 | atomic_read(&dev_priv->gpu_error.reset_counter), | |
1090 | interruptible, NULL); | |
b361237b CW |
1091 | } |
1092 | ||
1093 | /** | |
1094 | * Ensures that all rendering to the object has completed and the object is | |
1095 | * safe to unbind from the GTT or access from the CPU. | |
1096 | */ | |
1097 | static __must_check int | |
1098 | i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj, | |
1099 | bool readonly) | |
1100 | { | |
1101 | struct intel_ring_buffer *ring = obj->ring; | |
1102 | u32 seqno; | |
1103 | int ret; | |
1104 | ||
1105 | seqno = readonly ? obj->last_write_seqno : obj->last_read_seqno; | |
1106 | if (seqno == 0) | |
1107 | return 0; | |
1108 | ||
1109 | ret = i915_wait_seqno(ring, seqno); | |
1110 | if (ret) | |
1111 | return ret; | |
1112 | ||
1113 | i915_gem_retire_requests_ring(ring); | |
1114 | ||
1115 | /* Manually manage the write flush as we may have not yet | |
1116 | * retired the buffer. | |
1117 | */ | |
1118 | if (obj->last_write_seqno && | |
1119 | i915_seqno_passed(seqno, obj->last_write_seqno)) { | |
1120 | obj->last_write_seqno = 0; | |
1121 | obj->base.write_domain &= ~I915_GEM_GPU_DOMAINS; | |
1122 | } | |
1123 | ||
1124 | return 0; | |
1125 | } | |
1126 | ||
3236f57a CW |
1127 | /* A nonblocking variant of the above wait. This is a highly dangerous routine |
1128 | * as the object state may change during this call. | |
1129 | */ | |
1130 | static __must_check int | |
1131 | i915_gem_object_wait_rendering__nonblocking(struct drm_i915_gem_object *obj, | |
1132 | bool readonly) | |
1133 | { | |
1134 | struct drm_device *dev = obj->base.dev; | |
1135 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1136 | struct intel_ring_buffer *ring = obj->ring; | |
f69061be | 1137 | unsigned reset_counter; |
3236f57a CW |
1138 | u32 seqno; |
1139 | int ret; | |
1140 | ||
1141 | BUG_ON(!mutex_is_locked(&dev->struct_mutex)); | |
1142 | BUG_ON(!dev_priv->mm.interruptible); | |
1143 | ||
1144 | seqno = readonly ? obj->last_write_seqno : obj->last_read_seqno; | |
1145 | if (seqno == 0) | |
1146 | return 0; | |
1147 | ||
33196ded | 1148 | ret = i915_gem_check_wedge(&dev_priv->gpu_error, true); |
3236f57a CW |
1149 | if (ret) |
1150 | return ret; | |
1151 | ||
1152 | ret = i915_gem_check_olr(ring, seqno); | |
1153 | if (ret) | |
1154 | return ret; | |
1155 | ||
f69061be | 1156 | reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter); |
3236f57a | 1157 | mutex_unlock(&dev->struct_mutex); |
f69061be | 1158 | ret = __wait_seqno(ring, seqno, reset_counter, true, NULL); |
3236f57a CW |
1159 | mutex_lock(&dev->struct_mutex); |
1160 | ||
1161 | i915_gem_retire_requests_ring(ring); | |
1162 | ||
1163 | /* Manually manage the write flush as we may have not yet | |
1164 | * retired the buffer. | |
1165 | */ | |
1166 | if (obj->last_write_seqno && | |
1167 | i915_seqno_passed(seqno, obj->last_write_seqno)) { | |
1168 | obj->last_write_seqno = 0; | |
1169 | obj->base.write_domain &= ~I915_GEM_GPU_DOMAINS; | |
1170 | } | |
1171 | ||
1172 | return ret; | |
1173 | } | |
1174 | ||
673a394b | 1175 | /** |
2ef7eeaa EA |
1176 | * Called when user space prepares to use an object with the CPU, either |
1177 | * through the mmap ioctl's mapping or a GTT mapping. | |
673a394b EA |
1178 | */ |
1179 | int | |
1180 | i915_gem_set_domain_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 1181 | struct drm_file *file) |
673a394b EA |
1182 | { |
1183 | struct drm_i915_gem_set_domain *args = data; | |
05394f39 | 1184 | struct drm_i915_gem_object *obj; |
2ef7eeaa EA |
1185 | uint32_t read_domains = args->read_domains; |
1186 | uint32_t write_domain = args->write_domain; | |
673a394b EA |
1187 | int ret; |
1188 | ||
2ef7eeaa | 1189 | /* Only handle setting domains to types used by the CPU. */ |
21d509e3 | 1190 | if (write_domain & I915_GEM_GPU_DOMAINS) |
2ef7eeaa EA |
1191 | return -EINVAL; |
1192 | ||
21d509e3 | 1193 | if (read_domains & I915_GEM_GPU_DOMAINS) |
2ef7eeaa EA |
1194 | return -EINVAL; |
1195 | ||
1196 | /* Having something in the write domain implies it's in the read | |
1197 | * domain, and only that read domain. Enforce that in the request. | |
1198 | */ | |
1199 | if (write_domain != 0 && read_domains != write_domain) | |
1200 | return -EINVAL; | |
1201 | ||
76c1dec1 | 1202 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 1203 | if (ret) |
76c1dec1 | 1204 | return ret; |
1d7cfea1 | 1205 | |
05394f39 | 1206 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 1207 | if (&obj->base == NULL) { |
1d7cfea1 CW |
1208 | ret = -ENOENT; |
1209 | goto unlock; | |
76c1dec1 | 1210 | } |
673a394b | 1211 | |
3236f57a CW |
1212 | /* Try to flush the object off the GPU without holding the lock. |
1213 | * We will repeat the flush holding the lock in the normal manner | |
1214 | * to catch cases where we are gazumped. | |
1215 | */ | |
1216 | ret = i915_gem_object_wait_rendering__nonblocking(obj, !write_domain); | |
1217 | if (ret) | |
1218 | goto unref; | |
1219 | ||
2ef7eeaa EA |
1220 | if (read_domains & I915_GEM_DOMAIN_GTT) { |
1221 | ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0); | |
02354392 EA |
1222 | |
1223 | /* Silently promote "you're not bound, there was nothing to do" | |
1224 | * to success, since the client was just asking us to | |
1225 | * make sure everything was done. | |
1226 | */ | |
1227 | if (ret == -EINVAL) | |
1228 | ret = 0; | |
2ef7eeaa | 1229 | } else { |
e47c68e9 | 1230 | ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0); |
2ef7eeaa EA |
1231 | } |
1232 | ||
3236f57a | 1233 | unref: |
05394f39 | 1234 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 1235 | unlock: |
673a394b EA |
1236 | mutex_unlock(&dev->struct_mutex); |
1237 | return ret; | |
1238 | } | |
1239 | ||
1240 | /** | |
1241 | * Called when user space has done writes to this buffer | |
1242 | */ | |
1243 | int | |
1244 | i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 1245 | struct drm_file *file) |
673a394b EA |
1246 | { |
1247 | struct drm_i915_gem_sw_finish *args = data; | |
05394f39 | 1248 | struct drm_i915_gem_object *obj; |
673a394b EA |
1249 | int ret = 0; |
1250 | ||
76c1dec1 | 1251 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 1252 | if (ret) |
76c1dec1 | 1253 | return ret; |
1d7cfea1 | 1254 | |
05394f39 | 1255 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 1256 | if (&obj->base == NULL) { |
1d7cfea1 CW |
1257 | ret = -ENOENT; |
1258 | goto unlock; | |
673a394b EA |
1259 | } |
1260 | ||
673a394b | 1261 | /* Pinned buffers may be scanout, so flush the cache */ |
05394f39 | 1262 | if (obj->pin_count) |
e47c68e9 EA |
1263 | i915_gem_object_flush_cpu_write_domain(obj); |
1264 | ||
05394f39 | 1265 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 1266 | unlock: |
673a394b EA |
1267 | mutex_unlock(&dev->struct_mutex); |
1268 | return ret; | |
1269 | } | |
1270 | ||
1271 | /** | |
1272 | * Maps the contents of an object, returning the address it is mapped | |
1273 | * into. | |
1274 | * | |
1275 | * While the mapping holds a reference on the contents of the object, it doesn't | |
1276 | * imply a ref on the object itself. | |
1277 | */ | |
1278 | int | |
1279 | i915_gem_mmap_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 1280 | struct drm_file *file) |
673a394b EA |
1281 | { |
1282 | struct drm_i915_gem_mmap *args = data; | |
1283 | struct drm_gem_object *obj; | |
673a394b EA |
1284 | unsigned long addr; |
1285 | ||
05394f39 | 1286 | obj = drm_gem_object_lookup(dev, file, args->handle); |
673a394b | 1287 | if (obj == NULL) |
bf79cb91 | 1288 | return -ENOENT; |
673a394b | 1289 | |
1286ff73 DV |
1290 | /* prime objects have no backing filp to GEM mmap |
1291 | * pages from. | |
1292 | */ | |
1293 | if (!obj->filp) { | |
1294 | drm_gem_object_unreference_unlocked(obj); | |
1295 | return -EINVAL; | |
1296 | } | |
1297 | ||
6be5ceb0 | 1298 | addr = vm_mmap(obj->filp, 0, args->size, |
673a394b EA |
1299 | PROT_READ | PROT_WRITE, MAP_SHARED, |
1300 | args->offset); | |
bc9025bd | 1301 | drm_gem_object_unreference_unlocked(obj); |
673a394b EA |
1302 | if (IS_ERR((void *)addr)) |
1303 | return addr; | |
1304 | ||
1305 | args->addr_ptr = (uint64_t) addr; | |
1306 | ||
1307 | return 0; | |
1308 | } | |
1309 | ||
de151cf6 JB |
1310 | /** |
1311 | * i915_gem_fault - fault a page into the GTT | |
1312 | * vma: VMA in question | |
1313 | * vmf: fault info | |
1314 | * | |
1315 | * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped | |
1316 | * from userspace. The fault handler takes care of binding the object to | |
1317 | * the GTT (if needed), allocating and programming a fence register (again, | |
1318 | * only if needed based on whether the old reg is still valid or the object | |
1319 | * is tiled) and inserting a new PTE into the faulting process. | |
1320 | * | |
1321 | * Note that the faulting process may involve evicting existing objects | |
1322 | * from the GTT and/or fence registers to make room. So performance may | |
1323 | * suffer if the GTT working set is large or there are few fence registers | |
1324 | * left. | |
1325 | */ | |
1326 | int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf) | |
1327 | { | |
05394f39 CW |
1328 | struct drm_i915_gem_object *obj = to_intel_bo(vma->vm_private_data); |
1329 | struct drm_device *dev = obj->base.dev; | |
7d1c4804 | 1330 | drm_i915_private_t *dev_priv = dev->dev_private; |
de151cf6 JB |
1331 | pgoff_t page_offset; |
1332 | unsigned long pfn; | |
1333 | int ret = 0; | |
0f973f27 | 1334 | bool write = !!(vmf->flags & FAULT_FLAG_WRITE); |
de151cf6 JB |
1335 | |
1336 | /* We don't use vmf->pgoff since that has the fake offset */ | |
1337 | page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >> | |
1338 | PAGE_SHIFT; | |
1339 | ||
d9bc7e9f CW |
1340 | ret = i915_mutex_lock_interruptible(dev); |
1341 | if (ret) | |
1342 | goto out; | |
a00b10c3 | 1343 | |
db53a302 CW |
1344 | trace_i915_gem_object_fault(obj, page_offset, true, write); |
1345 | ||
eb119bd6 CW |
1346 | /* Access to snoopable pages through the GTT is incoherent. */ |
1347 | if (obj->cache_level != I915_CACHE_NONE && !HAS_LLC(dev)) { | |
1348 | ret = -EINVAL; | |
1349 | goto unlock; | |
1350 | } | |
1351 | ||
d9bc7e9f | 1352 | /* Now bind it into the GTT if needed */ |
c9839303 CW |
1353 | ret = i915_gem_object_pin(obj, 0, true, false); |
1354 | if (ret) | |
1355 | goto unlock; | |
4a684a41 | 1356 | |
c9839303 CW |
1357 | ret = i915_gem_object_set_to_gtt_domain(obj, write); |
1358 | if (ret) | |
1359 | goto unpin; | |
74898d7e | 1360 | |
06d98131 | 1361 | ret = i915_gem_object_get_fence(obj); |
d9e86c0e | 1362 | if (ret) |
c9839303 | 1363 | goto unpin; |
7d1c4804 | 1364 | |
6299f992 CW |
1365 | obj->fault_mappable = true; |
1366 | ||
5d4545ae | 1367 | pfn = ((dev_priv->gtt.mappable_base + obj->gtt_offset) >> PAGE_SHIFT) + |
de151cf6 JB |
1368 | page_offset; |
1369 | ||
1370 | /* Finally, remap it using the new GTT offset */ | |
1371 | ret = vm_insert_pfn(vma, (unsigned long)vmf->virtual_address, pfn); | |
c9839303 CW |
1372 | unpin: |
1373 | i915_gem_object_unpin(obj); | |
c715089f | 1374 | unlock: |
de151cf6 | 1375 | mutex_unlock(&dev->struct_mutex); |
d9bc7e9f | 1376 | out: |
de151cf6 | 1377 | switch (ret) { |
d9bc7e9f | 1378 | case -EIO: |
a9340cca DV |
1379 | /* If this -EIO is due to a gpu hang, give the reset code a |
1380 | * chance to clean up the mess. Otherwise return the proper | |
1381 | * SIGBUS. */ | |
1f83fee0 | 1382 | if (i915_terminally_wedged(&dev_priv->gpu_error)) |
a9340cca | 1383 | return VM_FAULT_SIGBUS; |
045e769a | 1384 | case -EAGAIN: |
d9bc7e9f CW |
1385 | /* Give the error handler a chance to run and move the |
1386 | * objects off the GPU active list. Next time we service the | |
1387 | * fault, we should be able to transition the page into the | |
1388 | * GTT without touching the GPU (and so avoid further | |
1389 | * EIO/EGAIN). If the GPU is wedged, then there is no issue | |
1390 | * with coherency, just lost writes. | |
1391 | */ | |
045e769a | 1392 | set_need_resched(); |
c715089f CW |
1393 | case 0: |
1394 | case -ERESTARTSYS: | |
bed636ab | 1395 | case -EINTR: |
e79e0fe3 DR |
1396 | case -EBUSY: |
1397 | /* | |
1398 | * EBUSY is ok: this just means that another thread | |
1399 | * already did the job. | |
1400 | */ | |
c715089f | 1401 | return VM_FAULT_NOPAGE; |
de151cf6 | 1402 | case -ENOMEM: |
de151cf6 | 1403 | return VM_FAULT_OOM; |
a7c2e1aa DV |
1404 | case -ENOSPC: |
1405 | return VM_FAULT_SIGBUS; | |
de151cf6 | 1406 | default: |
a7c2e1aa | 1407 | WARN_ONCE(ret, "unhandled error in i915_gem_fault: %i\n", ret); |
c715089f | 1408 | return VM_FAULT_SIGBUS; |
de151cf6 JB |
1409 | } |
1410 | } | |
1411 | ||
901782b2 CW |
1412 | /** |
1413 | * i915_gem_release_mmap - remove physical page mappings | |
1414 | * @obj: obj in question | |
1415 | * | |
af901ca1 | 1416 | * Preserve the reservation of the mmapping with the DRM core code, but |
901782b2 CW |
1417 | * relinquish ownership of the pages back to the system. |
1418 | * | |
1419 | * It is vital that we remove the page mapping if we have mapped a tiled | |
1420 | * object through the GTT and then lose the fence register due to | |
1421 | * resource pressure. Similarly if the object has been moved out of the | |
1422 | * aperture, than pages mapped into userspace must be revoked. Removing the | |
1423 | * mapping will then trigger a page fault on the next user access, allowing | |
1424 | * fixup by i915_gem_fault(). | |
1425 | */ | |
d05ca301 | 1426 | void |
05394f39 | 1427 | i915_gem_release_mmap(struct drm_i915_gem_object *obj) |
901782b2 | 1428 | { |
6299f992 CW |
1429 | if (!obj->fault_mappable) |
1430 | return; | |
901782b2 | 1431 | |
f6e47884 CW |
1432 | if (obj->base.dev->dev_mapping) |
1433 | unmap_mapping_range(obj->base.dev->dev_mapping, | |
1434 | (loff_t)obj->base.map_list.hash.key<<PAGE_SHIFT, | |
1435 | obj->base.size, 1); | |
fb7d516a | 1436 | |
6299f992 | 1437 | obj->fault_mappable = false; |
901782b2 CW |
1438 | } |
1439 | ||
0fa87796 | 1440 | uint32_t |
e28f8711 | 1441 | i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode) |
92b88aeb | 1442 | { |
e28f8711 | 1443 | uint32_t gtt_size; |
92b88aeb CW |
1444 | |
1445 | if (INTEL_INFO(dev)->gen >= 4 || | |
e28f8711 CW |
1446 | tiling_mode == I915_TILING_NONE) |
1447 | return size; | |
92b88aeb CW |
1448 | |
1449 | /* Previous chips need a power-of-two fence region when tiling */ | |
1450 | if (INTEL_INFO(dev)->gen == 3) | |
e28f8711 | 1451 | gtt_size = 1024*1024; |
92b88aeb | 1452 | else |
e28f8711 | 1453 | gtt_size = 512*1024; |
92b88aeb | 1454 | |
e28f8711 CW |
1455 | while (gtt_size < size) |
1456 | gtt_size <<= 1; | |
92b88aeb | 1457 | |
e28f8711 | 1458 | return gtt_size; |
92b88aeb CW |
1459 | } |
1460 | ||
de151cf6 JB |
1461 | /** |
1462 | * i915_gem_get_gtt_alignment - return required GTT alignment for an object | |
1463 | * @obj: object to check | |
1464 | * | |
1465 | * Return the required GTT alignment for an object, taking into account | |
5e783301 | 1466 | * potential fence register mapping. |
de151cf6 | 1467 | */ |
d865110c ID |
1468 | uint32_t |
1469 | i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size, | |
1470 | int tiling_mode, bool fenced) | |
de151cf6 | 1471 | { |
de151cf6 JB |
1472 | /* |
1473 | * Minimum alignment is 4k (GTT page size), but might be greater | |
1474 | * if a fence register is needed for the object. | |
1475 | */ | |
d865110c | 1476 | if (INTEL_INFO(dev)->gen >= 4 || (!fenced && IS_G33(dev)) || |
e28f8711 | 1477 | tiling_mode == I915_TILING_NONE) |
de151cf6 JB |
1478 | return 4096; |
1479 | ||
a00b10c3 CW |
1480 | /* |
1481 | * Previous chips need to be aligned to the size of the smallest | |
1482 | * fence register that can contain the object. | |
1483 | */ | |
e28f8711 | 1484 | return i915_gem_get_gtt_size(dev, size, tiling_mode); |
a00b10c3 CW |
1485 | } |
1486 | ||
d8cb5086 CW |
1487 | static int i915_gem_object_create_mmap_offset(struct drm_i915_gem_object *obj) |
1488 | { | |
1489 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; | |
1490 | int ret; | |
1491 | ||
1492 | if (obj->base.map_list.map) | |
1493 | return 0; | |
1494 | ||
da494d7c DV |
1495 | dev_priv->mm.shrinker_no_lock_stealing = true; |
1496 | ||
d8cb5086 CW |
1497 | ret = drm_gem_create_mmap_offset(&obj->base); |
1498 | if (ret != -ENOSPC) | |
da494d7c | 1499 | goto out; |
d8cb5086 CW |
1500 | |
1501 | /* Badly fragmented mmap space? The only way we can recover | |
1502 | * space is by destroying unwanted objects. We can't randomly release | |
1503 | * mmap_offsets as userspace expects them to be persistent for the | |
1504 | * lifetime of the objects. The closest we can is to release the | |
1505 | * offsets on purgeable objects by truncating it and marking it purged, | |
1506 | * which prevents userspace from ever using that object again. | |
1507 | */ | |
1508 | i915_gem_purge(dev_priv, obj->base.size >> PAGE_SHIFT); | |
1509 | ret = drm_gem_create_mmap_offset(&obj->base); | |
1510 | if (ret != -ENOSPC) | |
da494d7c | 1511 | goto out; |
d8cb5086 CW |
1512 | |
1513 | i915_gem_shrink_all(dev_priv); | |
da494d7c DV |
1514 | ret = drm_gem_create_mmap_offset(&obj->base); |
1515 | out: | |
1516 | dev_priv->mm.shrinker_no_lock_stealing = false; | |
1517 | ||
1518 | return ret; | |
d8cb5086 CW |
1519 | } |
1520 | ||
1521 | static void i915_gem_object_free_mmap_offset(struct drm_i915_gem_object *obj) | |
1522 | { | |
1523 | if (!obj->base.map_list.map) | |
1524 | return; | |
1525 | ||
1526 | drm_gem_free_mmap_offset(&obj->base); | |
1527 | } | |
1528 | ||
de151cf6 | 1529 | int |
ff72145b DA |
1530 | i915_gem_mmap_gtt(struct drm_file *file, |
1531 | struct drm_device *dev, | |
1532 | uint32_t handle, | |
1533 | uint64_t *offset) | |
de151cf6 | 1534 | { |
da761a6e | 1535 | struct drm_i915_private *dev_priv = dev->dev_private; |
05394f39 | 1536 | struct drm_i915_gem_object *obj; |
de151cf6 JB |
1537 | int ret; |
1538 | ||
76c1dec1 | 1539 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 1540 | if (ret) |
76c1dec1 | 1541 | return ret; |
de151cf6 | 1542 | |
ff72145b | 1543 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle)); |
c8725226 | 1544 | if (&obj->base == NULL) { |
1d7cfea1 CW |
1545 | ret = -ENOENT; |
1546 | goto unlock; | |
1547 | } | |
de151cf6 | 1548 | |
5d4545ae | 1549 | if (obj->base.size > dev_priv->gtt.mappable_end) { |
da761a6e | 1550 | ret = -E2BIG; |
ff56b0bc | 1551 | goto out; |
da761a6e CW |
1552 | } |
1553 | ||
05394f39 | 1554 | if (obj->madv != I915_MADV_WILLNEED) { |
ab18282d | 1555 | DRM_ERROR("Attempting to mmap a purgeable buffer\n"); |
1d7cfea1 CW |
1556 | ret = -EINVAL; |
1557 | goto out; | |
ab18282d CW |
1558 | } |
1559 | ||
d8cb5086 CW |
1560 | ret = i915_gem_object_create_mmap_offset(obj); |
1561 | if (ret) | |
1562 | goto out; | |
de151cf6 | 1563 | |
ff72145b | 1564 | *offset = (u64)obj->base.map_list.hash.key << PAGE_SHIFT; |
de151cf6 | 1565 | |
1d7cfea1 | 1566 | out: |
05394f39 | 1567 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 1568 | unlock: |
de151cf6 | 1569 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 1570 | return ret; |
de151cf6 JB |
1571 | } |
1572 | ||
ff72145b DA |
1573 | /** |
1574 | * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing | |
1575 | * @dev: DRM device | |
1576 | * @data: GTT mapping ioctl data | |
1577 | * @file: GEM object info | |
1578 | * | |
1579 | * Simply returns the fake offset to userspace so it can mmap it. | |
1580 | * The mmap call will end up in drm_gem_mmap(), which will set things | |
1581 | * up so we can get faults in the handler above. | |
1582 | * | |
1583 | * The fault handler will take care of binding the object into the GTT | |
1584 | * (since it may have been evicted to make room for something), allocating | |
1585 | * a fence register, and mapping the appropriate aperture address into | |
1586 | * userspace. | |
1587 | */ | |
1588 | int | |
1589 | i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data, | |
1590 | struct drm_file *file) | |
1591 | { | |
1592 | struct drm_i915_gem_mmap_gtt *args = data; | |
1593 | ||
ff72145b DA |
1594 | return i915_gem_mmap_gtt(file, dev, args->handle, &args->offset); |
1595 | } | |
1596 | ||
225067ee DV |
1597 | /* Immediately discard the backing storage */ |
1598 | static void | |
1599 | i915_gem_object_truncate(struct drm_i915_gem_object *obj) | |
e5281ccd | 1600 | { |
e5281ccd | 1601 | struct inode *inode; |
e5281ccd | 1602 | |
4d6294bf | 1603 | i915_gem_object_free_mmap_offset(obj); |
1286ff73 | 1604 | |
4d6294bf CW |
1605 | if (obj->base.filp == NULL) |
1606 | return; | |
e5281ccd | 1607 | |
225067ee DV |
1608 | /* Our goal here is to return as much of the memory as |
1609 | * is possible back to the system as we are called from OOM. | |
1610 | * To do this we must instruct the shmfs to drop all of its | |
1611 | * backing pages, *now*. | |
1612 | */ | |
496ad9aa | 1613 | inode = file_inode(obj->base.filp); |
225067ee | 1614 | shmem_truncate_range(inode, 0, (loff_t)-1); |
e5281ccd | 1615 | |
225067ee DV |
1616 | obj->madv = __I915_MADV_PURGED; |
1617 | } | |
e5281ccd | 1618 | |
225067ee DV |
1619 | static inline int |
1620 | i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj) | |
1621 | { | |
1622 | return obj->madv == I915_MADV_DONTNEED; | |
e5281ccd CW |
1623 | } |
1624 | ||
5cdf5881 | 1625 | static void |
05394f39 | 1626 | i915_gem_object_put_pages_gtt(struct drm_i915_gem_object *obj) |
673a394b | 1627 | { |
90797e6d ID |
1628 | struct sg_page_iter sg_iter; |
1629 | int ret; | |
1286ff73 | 1630 | |
05394f39 | 1631 | BUG_ON(obj->madv == __I915_MADV_PURGED); |
673a394b | 1632 | |
6c085a72 CW |
1633 | ret = i915_gem_object_set_to_cpu_domain(obj, true); |
1634 | if (ret) { | |
1635 | /* In the event of a disaster, abandon all caches and | |
1636 | * hope for the best. | |
1637 | */ | |
1638 | WARN_ON(ret != -EIO); | |
1639 | i915_gem_clflush_object(obj); | |
1640 | obj->base.read_domains = obj->base.write_domain = I915_GEM_DOMAIN_CPU; | |
1641 | } | |
1642 | ||
6dacfd2f | 1643 | if (i915_gem_object_needs_bit17_swizzle(obj)) |
280b713b EA |
1644 | i915_gem_object_save_bit_17_swizzle(obj); |
1645 | ||
05394f39 CW |
1646 | if (obj->madv == I915_MADV_DONTNEED) |
1647 | obj->dirty = 0; | |
3ef94daa | 1648 | |
90797e6d | 1649 | for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, 0) { |
2db76d7c | 1650 | struct page *page = sg_page_iter_page(&sg_iter); |
9da3da66 | 1651 | |
05394f39 | 1652 | if (obj->dirty) |
9da3da66 | 1653 | set_page_dirty(page); |
3ef94daa | 1654 | |
05394f39 | 1655 | if (obj->madv == I915_MADV_WILLNEED) |
9da3da66 | 1656 | mark_page_accessed(page); |
3ef94daa | 1657 | |
9da3da66 | 1658 | page_cache_release(page); |
3ef94daa | 1659 | } |
05394f39 | 1660 | obj->dirty = 0; |
673a394b | 1661 | |
9da3da66 CW |
1662 | sg_free_table(obj->pages); |
1663 | kfree(obj->pages); | |
37e680a1 | 1664 | } |
6c085a72 | 1665 | |
dd624afd | 1666 | int |
37e680a1 CW |
1667 | i915_gem_object_put_pages(struct drm_i915_gem_object *obj) |
1668 | { | |
1669 | const struct drm_i915_gem_object_ops *ops = obj->ops; | |
1670 | ||
2f745ad3 | 1671 | if (obj->pages == NULL) |
37e680a1 CW |
1672 | return 0; |
1673 | ||
1674 | BUG_ON(obj->gtt_space); | |
6c085a72 | 1675 | |
a5570178 CW |
1676 | if (obj->pages_pin_count) |
1677 | return -EBUSY; | |
1678 | ||
a2165e31 CW |
1679 | /* ->put_pages might need to allocate memory for the bit17 swizzle |
1680 | * array, hence protect them from being reaped by removing them from gtt | |
1681 | * lists early. */ | |
1682 | list_del(&obj->gtt_list); | |
1683 | ||
37e680a1 | 1684 | ops->put_pages(obj); |
05394f39 | 1685 | obj->pages = NULL; |
37e680a1 | 1686 | |
6c085a72 CW |
1687 | if (i915_gem_object_is_purgeable(obj)) |
1688 | i915_gem_object_truncate(obj); | |
1689 | ||
1690 | return 0; | |
1691 | } | |
1692 | ||
1693 | static long | |
93927ca5 DV |
1694 | __i915_gem_shrink(struct drm_i915_private *dev_priv, long target, |
1695 | bool purgeable_only) | |
6c085a72 CW |
1696 | { |
1697 | struct drm_i915_gem_object *obj, *next; | |
1698 | long count = 0; | |
1699 | ||
1700 | list_for_each_entry_safe(obj, next, | |
1701 | &dev_priv->mm.unbound_list, | |
1702 | gtt_list) { | |
93927ca5 | 1703 | if ((i915_gem_object_is_purgeable(obj) || !purgeable_only) && |
37e680a1 | 1704 | i915_gem_object_put_pages(obj) == 0) { |
6c085a72 CW |
1705 | count += obj->base.size >> PAGE_SHIFT; |
1706 | if (count >= target) | |
1707 | return count; | |
1708 | } | |
1709 | } | |
1710 | ||
1711 | list_for_each_entry_safe(obj, next, | |
1712 | &dev_priv->mm.inactive_list, | |
1713 | mm_list) { | |
93927ca5 | 1714 | if ((i915_gem_object_is_purgeable(obj) || !purgeable_only) && |
6c085a72 | 1715 | i915_gem_object_unbind(obj) == 0 && |
37e680a1 | 1716 | i915_gem_object_put_pages(obj) == 0) { |
6c085a72 CW |
1717 | count += obj->base.size >> PAGE_SHIFT; |
1718 | if (count >= target) | |
1719 | return count; | |
1720 | } | |
1721 | } | |
1722 | ||
1723 | return count; | |
1724 | } | |
1725 | ||
93927ca5 DV |
1726 | static long |
1727 | i915_gem_purge(struct drm_i915_private *dev_priv, long target) | |
1728 | { | |
1729 | return __i915_gem_shrink(dev_priv, target, true); | |
1730 | } | |
1731 | ||
6c085a72 CW |
1732 | static void |
1733 | i915_gem_shrink_all(struct drm_i915_private *dev_priv) | |
1734 | { | |
1735 | struct drm_i915_gem_object *obj, *next; | |
1736 | ||
1737 | i915_gem_evict_everything(dev_priv->dev); | |
1738 | ||
1739 | list_for_each_entry_safe(obj, next, &dev_priv->mm.unbound_list, gtt_list) | |
37e680a1 | 1740 | i915_gem_object_put_pages(obj); |
225067ee DV |
1741 | } |
1742 | ||
37e680a1 | 1743 | static int |
6c085a72 | 1744 | i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj) |
e5281ccd | 1745 | { |
6c085a72 | 1746 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
e5281ccd CW |
1747 | int page_count, i; |
1748 | struct address_space *mapping; | |
9da3da66 CW |
1749 | struct sg_table *st; |
1750 | struct scatterlist *sg; | |
90797e6d | 1751 | struct sg_page_iter sg_iter; |
e5281ccd | 1752 | struct page *page; |
90797e6d | 1753 | unsigned long last_pfn = 0; /* suppress gcc warning */ |
6c085a72 | 1754 | gfp_t gfp; |
e5281ccd | 1755 | |
6c085a72 CW |
1756 | /* Assert that the object is not currently in any GPU domain. As it |
1757 | * wasn't in the GTT, there shouldn't be any way it could have been in | |
1758 | * a GPU cache | |
1759 | */ | |
1760 | BUG_ON(obj->base.read_domains & I915_GEM_GPU_DOMAINS); | |
1761 | BUG_ON(obj->base.write_domain & I915_GEM_GPU_DOMAINS); | |
1762 | ||
9da3da66 CW |
1763 | st = kmalloc(sizeof(*st), GFP_KERNEL); |
1764 | if (st == NULL) | |
1765 | return -ENOMEM; | |
1766 | ||
05394f39 | 1767 | page_count = obj->base.size / PAGE_SIZE; |
9da3da66 CW |
1768 | if (sg_alloc_table(st, page_count, GFP_KERNEL)) { |
1769 | sg_free_table(st); | |
1770 | kfree(st); | |
e5281ccd | 1771 | return -ENOMEM; |
9da3da66 | 1772 | } |
e5281ccd | 1773 | |
9da3da66 CW |
1774 | /* Get the list of pages out of our struct file. They'll be pinned |
1775 | * at this point until we release them. | |
1776 | * | |
1777 | * Fail silently without starting the shrinker | |
1778 | */ | |
496ad9aa | 1779 | mapping = file_inode(obj->base.filp)->i_mapping; |
6c085a72 | 1780 | gfp = mapping_gfp_mask(mapping); |
caf49191 | 1781 | gfp |= __GFP_NORETRY | __GFP_NOWARN | __GFP_NO_KSWAPD; |
6c085a72 | 1782 | gfp &= ~(__GFP_IO | __GFP_WAIT); |
90797e6d ID |
1783 | sg = st->sgl; |
1784 | st->nents = 0; | |
1785 | for (i = 0; i < page_count; i++) { | |
6c085a72 CW |
1786 | page = shmem_read_mapping_page_gfp(mapping, i, gfp); |
1787 | if (IS_ERR(page)) { | |
1788 | i915_gem_purge(dev_priv, page_count); | |
1789 | page = shmem_read_mapping_page_gfp(mapping, i, gfp); | |
1790 | } | |
1791 | if (IS_ERR(page)) { | |
1792 | /* We've tried hard to allocate the memory by reaping | |
1793 | * our own buffer, now let the real VM do its job and | |
1794 | * go down in flames if truly OOM. | |
1795 | */ | |
caf49191 | 1796 | gfp &= ~(__GFP_NORETRY | __GFP_NOWARN | __GFP_NO_KSWAPD); |
6c085a72 CW |
1797 | gfp |= __GFP_IO | __GFP_WAIT; |
1798 | ||
1799 | i915_gem_shrink_all(dev_priv); | |
1800 | page = shmem_read_mapping_page_gfp(mapping, i, gfp); | |
1801 | if (IS_ERR(page)) | |
1802 | goto err_pages; | |
1803 | ||
caf49191 | 1804 | gfp |= __GFP_NORETRY | __GFP_NOWARN | __GFP_NO_KSWAPD; |
6c085a72 CW |
1805 | gfp &= ~(__GFP_IO | __GFP_WAIT); |
1806 | } | |
e5281ccd | 1807 | |
90797e6d ID |
1808 | if (!i || page_to_pfn(page) != last_pfn + 1) { |
1809 | if (i) | |
1810 | sg = sg_next(sg); | |
1811 | st->nents++; | |
1812 | sg_set_page(sg, page, PAGE_SIZE, 0); | |
1813 | } else { | |
1814 | sg->length += PAGE_SIZE; | |
1815 | } | |
1816 | last_pfn = page_to_pfn(page); | |
e5281ccd CW |
1817 | } |
1818 | ||
90797e6d | 1819 | sg_mark_end(sg); |
74ce6b6c CW |
1820 | obj->pages = st; |
1821 | ||
6dacfd2f | 1822 | if (i915_gem_object_needs_bit17_swizzle(obj)) |
e5281ccd CW |
1823 | i915_gem_object_do_bit_17_swizzle(obj); |
1824 | ||
1825 | return 0; | |
1826 | ||
1827 | err_pages: | |
90797e6d ID |
1828 | sg_mark_end(sg); |
1829 | for_each_sg_page(st->sgl, &sg_iter, st->nents, 0) | |
2db76d7c | 1830 | page_cache_release(sg_page_iter_page(&sg_iter)); |
9da3da66 CW |
1831 | sg_free_table(st); |
1832 | kfree(st); | |
e5281ccd | 1833 | return PTR_ERR(page); |
673a394b EA |
1834 | } |
1835 | ||
37e680a1 CW |
1836 | /* Ensure that the associated pages are gathered from the backing storage |
1837 | * and pinned into our object. i915_gem_object_get_pages() may be called | |
1838 | * multiple times before they are released by a single call to | |
1839 | * i915_gem_object_put_pages() - once the pages are no longer referenced | |
1840 | * either as a result of memory pressure (reaping pages under the shrinker) | |
1841 | * or as the object is itself released. | |
1842 | */ | |
1843 | int | |
1844 | i915_gem_object_get_pages(struct drm_i915_gem_object *obj) | |
1845 | { | |
1846 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; | |
1847 | const struct drm_i915_gem_object_ops *ops = obj->ops; | |
1848 | int ret; | |
1849 | ||
2f745ad3 | 1850 | if (obj->pages) |
37e680a1 CW |
1851 | return 0; |
1852 | ||
43e28f09 CW |
1853 | if (obj->madv != I915_MADV_WILLNEED) { |
1854 | DRM_ERROR("Attempting to obtain a purgeable object\n"); | |
1855 | return -EINVAL; | |
1856 | } | |
1857 | ||
a5570178 CW |
1858 | BUG_ON(obj->pages_pin_count); |
1859 | ||
37e680a1 CW |
1860 | ret = ops->get_pages(obj); |
1861 | if (ret) | |
1862 | return ret; | |
1863 | ||
1864 | list_add_tail(&obj->gtt_list, &dev_priv->mm.unbound_list); | |
1865 | return 0; | |
673a394b EA |
1866 | } |
1867 | ||
54cf91dc | 1868 | void |
05394f39 | 1869 | i915_gem_object_move_to_active(struct drm_i915_gem_object *obj, |
9d773091 | 1870 | struct intel_ring_buffer *ring) |
673a394b | 1871 | { |
05394f39 | 1872 | struct drm_device *dev = obj->base.dev; |
69dc4987 | 1873 | struct drm_i915_private *dev_priv = dev->dev_private; |
9d773091 | 1874 | u32 seqno = intel_ring_get_seqno(ring); |
617dbe27 | 1875 | |
852835f3 | 1876 | BUG_ON(ring == NULL); |
05394f39 | 1877 | obj->ring = ring; |
673a394b EA |
1878 | |
1879 | /* Add a reference if we're newly entering the active list. */ | |
05394f39 CW |
1880 | if (!obj->active) { |
1881 | drm_gem_object_reference(&obj->base); | |
1882 | obj->active = 1; | |
673a394b | 1883 | } |
e35a41de | 1884 | |
673a394b | 1885 | /* Move from whatever list we were on to the tail of execution. */ |
05394f39 CW |
1886 | list_move_tail(&obj->mm_list, &dev_priv->mm.active_list); |
1887 | list_move_tail(&obj->ring_list, &ring->active_list); | |
caea7476 | 1888 | |
0201f1ec | 1889 | obj->last_read_seqno = seqno; |
caea7476 | 1890 | |
7dd49065 | 1891 | if (obj->fenced_gpu_access) { |
caea7476 | 1892 | obj->last_fenced_seqno = seqno; |
caea7476 | 1893 | |
7dd49065 CW |
1894 | /* Bump MRU to take account of the delayed flush */ |
1895 | if (obj->fence_reg != I915_FENCE_REG_NONE) { | |
1896 | struct drm_i915_fence_reg *reg; | |
1897 | ||
1898 | reg = &dev_priv->fence_regs[obj->fence_reg]; | |
1899 | list_move_tail(®->lru_list, | |
1900 | &dev_priv->mm.fence_list); | |
1901 | } | |
caea7476 CW |
1902 | } |
1903 | } | |
1904 | ||
1905 | static void | |
caea7476 | 1906 | i915_gem_object_move_to_inactive(struct drm_i915_gem_object *obj) |
ce44b0ea | 1907 | { |
05394f39 | 1908 | struct drm_device *dev = obj->base.dev; |
caea7476 | 1909 | struct drm_i915_private *dev_priv = dev->dev_private; |
ce44b0ea | 1910 | |
65ce3027 | 1911 | BUG_ON(obj->base.write_domain & ~I915_GEM_GPU_DOMAINS); |
05394f39 | 1912 | BUG_ON(!obj->active); |
caea7476 | 1913 | |
1b50247a | 1914 | list_move_tail(&obj->mm_list, &dev_priv->mm.inactive_list); |
caea7476 | 1915 | |
65ce3027 | 1916 | list_del_init(&obj->ring_list); |
caea7476 CW |
1917 | obj->ring = NULL; |
1918 | ||
65ce3027 CW |
1919 | obj->last_read_seqno = 0; |
1920 | obj->last_write_seqno = 0; | |
1921 | obj->base.write_domain = 0; | |
1922 | ||
1923 | obj->last_fenced_seqno = 0; | |
caea7476 | 1924 | obj->fenced_gpu_access = false; |
caea7476 CW |
1925 | |
1926 | obj->active = 0; | |
1927 | drm_gem_object_unreference(&obj->base); | |
1928 | ||
1929 | WARN_ON(i915_verify_lists(dev)); | |
ce44b0ea | 1930 | } |
673a394b | 1931 | |
9d773091 | 1932 | static int |
fca26bb4 | 1933 | i915_gem_init_seqno(struct drm_device *dev, u32 seqno) |
53d227f2 | 1934 | { |
9d773091 CW |
1935 | struct drm_i915_private *dev_priv = dev->dev_private; |
1936 | struct intel_ring_buffer *ring; | |
1937 | int ret, i, j; | |
53d227f2 | 1938 | |
107f27a5 | 1939 | /* Carefully retire all requests without writing to the rings */ |
9d773091 | 1940 | for_each_ring(ring, dev_priv, i) { |
107f27a5 CW |
1941 | ret = intel_ring_idle(ring); |
1942 | if (ret) | |
1943 | return ret; | |
9d773091 | 1944 | } |
9d773091 | 1945 | i915_gem_retire_requests(dev); |
107f27a5 CW |
1946 | |
1947 | /* Finally reset hw state */ | |
9d773091 | 1948 | for_each_ring(ring, dev_priv, i) { |
fca26bb4 | 1949 | intel_ring_init_seqno(ring, seqno); |
498d2ac1 | 1950 | |
9d773091 CW |
1951 | for (j = 0; j < ARRAY_SIZE(ring->sync_seqno); j++) |
1952 | ring->sync_seqno[j] = 0; | |
1953 | } | |
53d227f2 | 1954 | |
9d773091 | 1955 | return 0; |
53d227f2 DV |
1956 | } |
1957 | ||
fca26bb4 MK |
1958 | int i915_gem_set_seqno(struct drm_device *dev, u32 seqno) |
1959 | { | |
1960 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1961 | int ret; | |
1962 | ||
1963 | if (seqno == 0) | |
1964 | return -EINVAL; | |
1965 | ||
1966 | /* HWS page needs to be set less than what we | |
1967 | * will inject to ring | |
1968 | */ | |
1969 | ret = i915_gem_init_seqno(dev, seqno - 1); | |
1970 | if (ret) | |
1971 | return ret; | |
1972 | ||
1973 | /* Carefully set the last_seqno value so that wrap | |
1974 | * detection still works | |
1975 | */ | |
1976 | dev_priv->next_seqno = seqno; | |
1977 | dev_priv->last_seqno = seqno - 1; | |
1978 | if (dev_priv->last_seqno == 0) | |
1979 | dev_priv->last_seqno--; | |
1980 | ||
1981 | return 0; | |
1982 | } | |
1983 | ||
9d773091 CW |
1984 | int |
1985 | i915_gem_get_seqno(struct drm_device *dev, u32 *seqno) | |
53d227f2 | 1986 | { |
9d773091 CW |
1987 | struct drm_i915_private *dev_priv = dev->dev_private; |
1988 | ||
1989 | /* reserve 0 for non-seqno */ | |
1990 | if (dev_priv->next_seqno == 0) { | |
fca26bb4 | 1991 | int ret = i915_gem_init_seqno(dev, 0); |
9d773091 CW |
1992 | if (ret) |
1993 | return ret; | |
53d227f2 | 1994 | |
9d773091 CW |
1995 | dev_priv->next_seqno = 1; |
1996 | } | |
53d227f2 | 1997 | |
f72b3435 | 1998 | *seqno = dev_priv->last_seqno = dev_priv->next_seqno++; |
9d773091 | 1999 | return 0; |
53d227f2 DV |
2000 | } |
2001 | ||
3cce469c | 2002 | int |
db53a302 | 2003 | i915_add_request(struct intel_ring_buffer *ring, |
f787a5f5 | 2004 | struct drm_file *file, |
acb868d3 | 2005 | u32 *out_seqno) |
673a394b | 2006 | { |
db53a302 | 2007 | drm_i915_private_t *dev_priv = ring->dev->dev_private; |
acb868d3 | 2008 | struct drm_i915_gem_request *request; |
a71d8d94 | 2009 | u32 request_ring_position; |
673a394b | 2010 | int was_empty; |
3cce469c CW |
2011 | int ret; |
2012 | ||
cc889e0f DV |
2013 | /* |
2014 | * Emit any outstanding flushes - execbuf can fail to emit the flush | |
2015 | * after having emitted the batchbuffer command. Hence we need to fix | |
2016 | * things up similar to emitting the lazy request. The difference here | |
2017 | * is that the flush _must_ happen before the next request, no matter | |
2018 | * what. | |
2019 | */ | |
a7b9761d CW |
2020 | ret = intel_ring_flush_all_caches(ring); |
2021 | if (ret) | |
2022 | return ret; | |
cc889e0f | 2023 | |
acb868d3 CW |
2024 | request = kmalloc(sizeof(*request), GFP_KERNEL); |
2025 | if (request == NULL) | |
2026 | return -ENOMEM; | |
cc889e0f | 2027 | |
673a394b | 2028 | |
a71d8d94 CW |
2029 | /* Record the position of the start of the request so that |
2030 | * should we detect the updated seqno part-way through the | |
2031 | * GPU processing the request, we never over-estimate the | |
2032 | * position of the head. | |
2033 | */ | |
2034 | request_ring_position = intel_ring_get_tail(ring); | |
2035 | ||
9d773091 | 2036 | ret = ring->add_request(ring); |
3bb73aba CW |
2037 | if (ret) { |
2038 | kfree(request); | |
2039 | return ret; | |
2040 | } | |
673a394b | 2041 | |
9d773091 | 2042 | request->seqno = intel_ring_get_seqno(ring); |
852835f3 | 2043 | request->ring = ring; |
a71d8d94 | 2044 | request->tail = request_ring_position; |
0e50e96b MK |
2045 | request->ctx = ring->last_context; |
2046 | ||
2047 | if (request->ctx) | |
2048 | i915_gem_context_reference(request->ctx); | |
2049 | ||
673a394b | 2050 | request->emitted_jiffies = jiffies; |
852835f3 ZN |
2051 | was_empty = list_empty(&ring->request_list); |
2052 | list_add_tail(&request->list, &ring->request_list); | |
3bb73aba | 2053 | request->file_priv = NULL; |
852835f3 | 2054 | |
db53a302 CW |
2055 | if (file) { |
2056 | struct drm_i915_file_private *file_priv = file->driver_priv; | |
2057 | ||
1c25595f | 2058 | spin_lock(&file_priv->mm.lock); |
f787a5f5 | 2059 | request->file_priv = file_priv; |
b962442e | 2060 | list_add_tail(&request->client_list, |
f787a5f5 | 2061 | &file_priv->mm.request_list); |
1c25595f | 2062 | spin_unlock(&file_priv->mm.lock); |
b962442e | 2063 | } |
673a394b | 2064 | |
9d773091 | 2065 | trace_i915_gem_request_add(ring, request->seqno); |
5391d0cf | 2066 | ring->outstanding_lazy_request = 0; |
db53a302 | 2067 | |
f65d9421 | 2068 | if (!dev_priv->mm.suspended) { |
3e0dc6b0 | 2069 | if (i915_enable_hangcheck) { |
99584db3 | 2070 | mod_timer(&dev_priv->gpu_error.hangcheck_timer, |
cecc21fe | 2071 | round_jiffies_up(jiffies + DRM_I915_HANGCHECK_JIFFIES)); |
3e0dc6b0 | 2072 | } |
f047e395 | 2073 | if (was_empty) { |
b3b079db | 2074 | queue_delayed_work(dev_priv->wq, |
bcb45086 CW |
2075 | &dev_priv->mm.retire_work, |
2076 | round_jiffies_up_relative(HZ)); | |
f047e395 CW |
2077 | intel_mark_busy(dev_priv->dev); |
2078 | } | |
f65d9421 | 2079 | } |
cc889e0f | 2080 | |
acb868d3 | 2081 | if (out_seqno) |
9d773091 | 2082 | *out_seqno = request->seqno; |
3cce469c | 2083 | return 0; |
673a394b EA |
2084 | } |
2085 | ||
f787a5f5 CW |
2086 | static inline void |
2087 | i915_gem_request_remove_from_client(struct drm_i915_gem_request *request) | |
673a394b | 2088 | { |
1c25595f | 2089 | struct drm_i915_file_private *file_priv = request->file_priv; |
673a394b | 2090 | |
1c25595f CW |
2091 | if (!file_priv) |
2092 | return; | |
1c5d22f7 | 2093 | |
1c25595f | 2094 | spin_lock(&file_priv->mm.lock); |
09bfa517 HRK |
2095 | if (request->file_priv) { |
2096 | list_del(&request->client_list); | |
2097 | request->file_priv = NULL; | |
2098 | } | |
1c25595f | 2099 | spin_unlock(&file_priv->mm.lock); |
673a394b | 2100 | } |
673a394b | 2101 | |
0e50e96b MK |
2102 | static void i915_gem_free_request(struct drm_i915_gem_request *request) |
2103 | { | |
2104 | list_del(&request->list); | |
2105 | i915_gem_request_remove_from_client(request); | |
2106 | ||
2107 | if (request->ctx) | |
2108 | i915_gem_context_unreference(request->ctx); | |
2109 | ||
2110 | kfree(request); | |
2111 | } | |
2112 | ||
dfaae392 CW |
2113 | static void i915_gem_reset_ring_lists(struct drm_i915_private *dev_priv, |
2114 | struct intel_ring_buffer *ring) | |
9375e446 | 2115 | { |
dfaae392 CW |
2116 | while (!list_empty(&ring->request_list)) { |
2117 | struct drm_i915_gem_request *request; | |
673a394b | 2118 | |
dfaae392 CW |
2119 | request = list_first_entry(&ring->request_list, |
2120 | struct drm_i915_gem_request, | |
2121 | list); | |
de151cf6 | 2122 | |
0e50e96b | 2123 | i915_gem_free_request(request); |
dfaae392 | 2124 | } |
673a394b | 2125 | |
dfaae392 | 2126 | while (!list_empty(&ring->active_list)) { |
05394f39 | 2127 | struct drm_i915_gem_object *obj; |
9375e446 | 2128 | |
05394f39 CW |
2129 | obj = list_first_entry(&ring->active_list, |
2130 | struct drm_i915_gem_object, | |
2131 | ring_list); | |
9375e446 | 2132 | |
05394f39 | 2133 | i915_gem_object_move_to_inactive(obj); |
673a394b EA |
2134 | } |
2135 | } | |
2136 | ||
312817a3 CW |
2137 | static void i915_gem_reset_fences(struct drm_device *dev) |
2138 | { | |
2139 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2140 | int i; | |
2141 | ||
4b9de737 | 2142 | for (i = 0; i < dev_priv->num_fence_regs; i++) { |
312817a3 | 2143 | struct drm_i915_fence_reg *reg = &dev_priv->fence_regs[i]; |
7d2cb39c | 2144 | |
ada726c7 CW |
2145 | if (reg->obj) |
2146 | i915_gem_object_fence_lost(reg->obj); | |
7d2cb39c | 2147 | |
f9c513e9 CW |
2148 | i915_gem_write_fence(dev, i, NULL); |
2149 | ||
ada726c7 CW |
2150 | reg->pin_count = 0; |
2151 | reg->obj = NULL; | |
2152 | INIT_LIST_HEAD(®->lru_list); | |
312817a3 | 2153 | } |
ada726c7 CW |
2154 | |
2155 | INIT_LIST_HEAD(&dev_priv->mm.fence_list); | |
312817a3 CW |
2156 | } |
2157 | ||
069efc1d | 2158 | void i915_gem_reset(struct drm_device *dev) |
673a394b | 2159 | { |
77f01230 | 2160 | struct drm_i915_private *dev_priv = dev->dev_private; |
05394f39 | 2161 | struct drm_i915_gem_object *obj; |
b4519513 | 2162 | struct intel_ring_buffer *ring; |
1ec14ad3 | 2163 | int i; |
673a394b | 2164 | |
b4519513 CW |
2165 | for_each_ring(ring, dev_priv, i) |
2166 | i915_gem_reset_ring_lists(dev_priv, ring); | |
dfaae392 | 2167 | |
dfaae392 CW |
2168 | /* Move everything out of the GPU domains to ensure we do any |
2169 | * necessary invalidation upon reuse. | |
2170 | */ | |
05394f39 | 2171 | list_for_each_entry(obj, |
77f01230 | 2172 | &dev_priv->mm.inactive_list, |
69dc4987 | 2173 | mm_list) |
77f01230 | 2174 | { |
05394f39 | 2175 | obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS; |
77f01230 | 2176 | } |
069efc1d CW |
2177 | |
2178 | /* The fence registers are invalidated so clear them out */ | |
312817a3 | 2179 | i915_gem_reset_fences(dev); |
673a394b EA |
2180 | } |
2181 | ||
2182 | /** | |
2183 | * This function clears the request list as sequence numbers are passed. | |
2184 | */ | |
a71d8d94 | 2185 | void |
db53a302 | 2186 | i915_gem_retire_requests_ring(struct intel_ring_buffer *ring) |
673a394b | 2187 | { |
673a394b EA |
2188 | uint32_t seqno; |
2189 | ||
db53a302 | 2190 | if (list_empty(&ring->request_list)) |
6c0594a3 KW |
2191 | return; |
2192 | ||
db53a302 | 2193 | WARN_ON(i915_verify_lists(ring->dev)); |
673a394b | 2194 | |
b2eadbc8 | 2195 | seqno = ring->get_seqno(ring, true); |
1ec14ad3 | 2196 | |
852835f3 | 2197 | while (!list_empty(&ring->request_list)) { |
673a394b | 2198 | struct drm_i915_gem_request *request; |
673a394b | 2199 | |
852835f3 | 2200 | request = list_first_entry(&ring->request_list, |
673a394b EA |
2201 | struct drm_i915_gem_request, |
2202 | list); | |
673a394b | 2203 | |
dfaae392 | 2204 | if (!i915_seqno_passed(seqno, request->seqno)) |
b84d5f0c CW |
2205 | break; |
2206 | ||
db53a302 | 2207 | trace_i915_gem_request_retire(ring, request->seqno); |
a71d8d94 CW |
2208 | /* We know the GPU must have read the request to have |
2209 | * sent us the seqno + interrupt, so use the position | |
2210 | * of tail of the request to update the last known position | |
2211 | * of the GPU head. | |
2212 | */ | |
2213 | ring->last_retired_head = request->tail; | |
b84d5f0c | 2214 | |
0e50e96b | 2215 | i915_gem_free_request(request); |
b84d5f0c | 2216 | } |
673a394b | 2217 | |
b84d5f0c CW |
2218 | /* Move any buffers on the active list that are no longer referenced |
2219 | * by the ringbuffer to the flushing/inactive lists as appropriate. | |
2220 | */ | |
2221 | while (!list_empty(&ring->active_list)) { | |
05394f39 | 2222 | struct drm_i915_gem_object *obj; |
b84d5f0c | 2223 | |
0206e353 | 2224 | obj = list_first_entry(&ring->active_list, |
05394f39 CW |
2225 | struct drm_i915_gem_object, |
2226 | ring_list); | |
673a394b | 2227 | |
0201f1ec | 2228 | if (!i915_seqno_passed(seqno, obj->last_read_seqno)) |
673a394b | 2229 | break; |
b84d5f0c | 2230 | |
65ce3027 | 2231 | i915_gem_object_move_to_inactive(obj); |
673a394b | 2232 | } |
9d34e5db | 2233 | |
db53a302 CW |
2234 | if (unlikely(ring->trace_irq_seqno && |
2235 | i915_seqno_passed(seqno, ring->trace_irq_seqno))) { | |
1ec14ad3 | 2236 | ring->irq_put(ring); |
db53a302 | 2237 | ring->trace_irq_seqno = 0; |
9d34e5db | 2238 | } |
23bc5982 | 2239 | |
db53a302 | 2240 | WARN_ON(i915_verify_lists(ring->dev)); |
673a394b EA |
2241 | } |
2242 | ||
b09a1fec CW |
2243 | void |
2244 | i915_gem_retire_requests(struct drm_device *dev) | |
2245 | { | |
2246 | drm_i915_private_t *dev_priv = dev->dev_private; | |
b4519513 | 2247 | struct intel_ring_buffer *ring; |
1ec14ad3 | 2248 | int i; |
b09a1fec | 2249 | |
b4519513 CW |
2250 | for_each_ring(ring, dev_priv, i) |
2251 | i915_gem_retire_requests_ring(ring); | |
b09a1fec CW |
2252 | } |
2253 | ||
75ef9da2 | 2254 | static void |
673a394b EA |
2255 | i915_gem_retire_work_handler(struct work_struct *work) |
2256 | { | |
2257 | drm_i915_private_t *dev_priv; | |
2258 | struct drm_device *dev; | |
b4519513 | 2259 | struct intel_ring_buffer *ring; |
0a58705b CW |
2260 | bool idle; |
2261 | int i; | |
673a394b EA |
2262 | |
2263 | dev_priv = container_of(work, drm_i915_private_t, | |
2264 | mm.retire_work.work); | |
2265 | dev = dev_priv->dev; | |
2266 | ||
891b48cf CW |
2267 | /* Come back later if the device is busy... */ |
2268 | if (!mutex_trylock(&dev->struct_mutex)) { | |
bcb45086 CW |
2269 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, |
2270 | round_jiffies_up_relative(HZ)); | |
891b48cf CW |
2271 | return; |
2272 | } | |
673a394b | 2273 | |
b09a1fec | 2274 | i915_gem_retire_requests(dev); |
673a394b | 2275 | |
0a58705b CW |
2276 | /* Send a periodic flush down the ring so we don't hold onto GEM |
2277 | * objects indefinitely. | |
673a394b | 2278 | */ |
0a58705b | 2279 | idle = true; |
b4519513 | 2280 | for_each_ring(ring, dev_priv, i) { |
3bb73aba CW |
2281 | if (ring->gpu_caches_dirty) |
2282 | i915_add_request(ring, NULL, NULL); | |
0a58705b CW |
2283 | |
2284 | idle &= list_empty(&ring->request_list); | |
673a394b EA |
2285 | } |
2286 | ||
0a58705b | 2287 | if (!dev_priv->mm.suspended && !idle) |
bcb45086 CW |
2288 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, |
2289 | round_jiffies_up_relative(HZ)); | |
f047e395 CW |
2290 | if (idle) |
2291 | intel_mark_idle(dev); | |
0a58705b | 2292 | |
673a394b | 2293 | mutex_unlock(&dev->struct_mutex); |
673a394b EA |
2294 | } |
2295 | ||
30dfebf3 DV |
2296 | /** |
2297 | * Ensures that an object will eventually get non-busy by flushing any required | |
2298 | * write domains, emitting any outstanding lazy request and retiring and | |
2299 | * completed requests. | |
2300 | */ | |
2301 | static int | |
2302 | i915_gem_object_flush_active(struct drm_i915_gem_object *obj) | |
2303 | { | |
2304 | int ret; | |
2305 | ||
2306 | if (obj->active) { | |
0201f1ec | 2307 | ret = i915_gem_check_olr(obj->ring, obj->last_read_seqno); |
30dfebf3 DV |
2308 | if (ret) |
2309 | return ret; | |
2310 | ||
30dfebf3 DV |
2311 | i915_gem_retire_requests_ring(obj->ring); |
2312 | } | |
2313 | ||
2314 | return 0; | |
2315 | } | |
2316 | ||
23ba4fd0 BW |
2317 | /** |
2318 | * i915_gem_wait_ioctl - implements DRM_IOCTL_I915_GEM_WAIT | |
2319 | * @DRM_IOCTL_ARGS: standard ioctl arguments | |
2320 | * | |
2321 | * Returns 0 if successful, else an error is returned with the remaining time in | |
2322 | * the timeout parameter. | |
2323 | * -ETIME: object is still busy after timeout | |
2324 | * -ERESTARTSYS: signal interrupted the wait | |
2325 | * -ENONENT: object doesn't exist | |
2326 | * Also possible, but rare: | |
2327 | * -EAGAIN: GPU wedged | |
2328 | * -ENOMEM: damn | |
2329 | * -ENODEV: Internal IRQ fail | |
2330 | * -E?: The add request failed | |
2331 | * | |
2332 | * The wait ioctl with a timeout of 0 reimplements the busy ioctl. With any | |
2333 | * non-zero timeout parameter the wait ioctl will wait for the given number of | |
2334 | * nanoseconds on an object becoming unbusy. Since the wait itself does so | |
2335 | * without holding struct_mutex the object may become re-busied before this | |
2336 | * function completes. A similar but shorter * race condition exists in the busy | |
2337 | * ioctl | |
2338 | */ | |
2339 | int | |
2340 | i915_gem_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *file) | |
2341 | { | |
f69061be | 2342 | drm_i915_private_t *dev_priv = dev->dev_private; |
23ba4fd0 BW |
2343 | struct drm_i915_gem_wait *args = data; |
2344 | struct drm_i915_gem_object *obj; | |
2345 | struct intel_ring_buffer *ring = NULL; | |
eac1f14f | 2346 | struct timespec timeout_stack, *timeout = NULL; |
f69061be | 2347 | unsigned reset_counter; |
23ba4fd0 BW |
2348 | u32 seqno = 0; |
2349 | int ret = 0; | |
2350 | ||
eac1f14f BW |
2351 | if (args->timeout_ns >= 0) { |
2352 | timeout_stack = ns_to_timespec(args->timeout_ns); | |
2353 | timeout = &timeout_stack; | |
2354 | } | |
23ba4fd0 BW |
2355 | |
2356 | ret = i915_mutex_lock_interruptible(dev); | |
2357 | if (ret) | |
2358 | return ret; | |
2359 | ||
2360 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->bo_handle)); | |
2361 | if (&obj->base == NULL) { | |
2362 | mutex_unlock(&dev->struct_mutex); | |
2363 | return -ENOENT; | |
2364 | } | |
2365 | ||
30dfebf3 DV |
2366 | /* Need to make sure the object gets inactive eventually. */ |
2367 | ret = i915_gem_object_flush_active(obj); | |
23ba4fd0 BW |
2368 | if (ret) |
2369 | goto out; | |
2370 | ||
2371 | if (obj->active) { | |
0201f1ec | 2372 | seqno = obj->last_read_seqno; |
23ba4fd0 BW |
2373 | ring = obj->ring; |
2374 | } | |
2375 | ||
2376 | if (seqno == 0) | |
2377 | goto out; | |
2378 | ||
23ba4fd0 BW |
2379 | /* Do this after OLR check to make sure we make forward progress polling |
2380 | * on this IOCTL with a 0 timeout (like busy ioctl) | |
2381 | */ | |
2382 | if (!args->timeout_ns) { | |
2383 | ret = -ETIME; | |
2384 | goto out; | |
2385 | } | |
2386 | ||
2387 | drm_gem_object_unreference(&obj->base); | |
f69061be | 2388 | reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter); |
23ba4fd0 BW |
2389 | mutex_unlock(&dev->struct_mutex); |
2390 | ||
f69061be | 2391 | ret = __wait_seqno(ring, seqno, reset_counter, true, timeout); |
4f42f4ef | 2392 | if (timeout) |
eac1f14f | 2393 | args->timeout_ns = timespec_to_ns(timeout); |
23ba4fd0 BW |
2394 | return ret; |
2395 | ||
2396 | out: | |
2397 | drm_gem_object_unreference(&obj->base); | |
2398 | mutex_unlock(&dev->struct_mutex); | |
2399 | return ret; | |
2400 | } | |
2401 | ||
5816d648 BW |
2402 | /** |
2403 | * i915_gem_object_sync - sync an object to a ring. | |
2404 | * | |
2405 | * @obj: object which may be in use on another ring. | |
2406 | * @to: ring we wish to use the object on. May be NULL. | |
2407 | * | |
2408 | * This code is meant to abstract object synchronization with the GPU. | |
2409 | * Calling with NULL implies synchronizing the object with the CPU | |
2410 | * rather than a particular GPU ring. | |
2411 | * | |
2412 | * Returns 0 if successful, else propagates up the lower layer error. | |
2413 | */ | |
2911a35b BW |
2414 | int |
2415 | i915_gem_object_sync(struct drm_i915_gem_object *obj, | |
2416 | struct intel_ring_buffer *to) | |
2417 | { | |
2418 | struct intel_ring_buffer *from = obj->ring; | |
2419 | u32 seqno; | |
2420 | int ret, idx; | |
2421 | ||
2422 | if (from == NULL || to == from) | |
2423 | return 0; | |
2424 | ||
5816d648 | 2425 | if (to == NULL || !i915_semaphore_is_enabled(obj->base.dev)) |
0201f1ec | 2426 | return i915_gem_object_wait_rendering(obj, false); |
2911a35b BW |
2427 | |
2428 | idx = intel_ring_sync_index(from, to); | |
2429 | ||
0201f1ec | 2430 | seqno = obj->last_read_seqno; |
2911a35b BW |
2431 | if (seqno <= from->sync_seqno[idx]) |
2432 | return 0; | |
2433 | ||
b4aca010 BW |
2434 | ret = i915_gem_check_olr(obj->ring, seqno); |
2435 | if (ret) | |
2436 | return ret; | |
2911a35b | 2437 | |
1500f7ea | 2438 | ret = to->sync_to(to, from, seqno); |
e3a5a225 | 2439 | if (!ret) |
7b01e260 MK |
2440 | /* We use last_read_seqno because sync_to() |
2441 | * might have just caused seqno wrap under | |
2442 | * the radar. | |
2443 | */ | |
2444 | from->sync_seqno[idx] = obj->last_read_seqno; | |
2911a35b | 2445 | |
e3a5a225 | 2446 | return ret; |
2911a35b BW |
2447 | } |
2448 | ||
b5ffc9bc CW |
2449 | static void i915_gem_object_finish_gtt(struct drm_i915_gem_object *obj) |
2450 | { | |
2451 | u32 old_write_domain, old_read_domains; | |
2452 | ||
b5ffc9bc CW |
2453 | /* Force a pagefault for domain tracking on next user access */ |
2454 | i915_gem_release_mmap(obj); | |
2455 | ||
b97c3d9c KP |
2456 | if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0) |
2457 | return; | |
2458 | ||
97c809fd CW |
2459 | /* Wait for any direct GTT access to complete */ |
2460 | mb(); | |
2461 | ||
b5ffc9bc CW |
2462 | old_read_domains = obj->base.read_domains; |
2463 | old_write_domain = obj->base.write_domain; | |
2464 | ||
2465 | obj->base.read_domains &= ~I915_GEM_DOMAIN_GTT; | |
2466 | obj->base.write_domain &= ~I915_GEM_DOMAIN_GTT; | |
2467 | ||
2468 | trace_i915_gem_object_change_domain(obj, | |
2469 | old_read_domains, | |
2470 | old_write_domain); | |
2471 | } | |
2472 | ||
673a394b EA |
2473 | /** |
2474 | * Unbinds an object from the GTT aperture. | |
2475 | */ | |
0f973f27 | 2476 | int |
05394f39 | 2477 | i915_gem_object_unbind(struct drm_i915_gem_object *obj) |
673a394b | 2478 | { |
7bddb01f | 2479 | drm_i915_private_t *dev_priv = obj->base.dev->dev_private; |
43e28f09 | 2480 | int ret; |
673a394b | 2481 | |
05394f39 | 2482 | if (obj->gtt_space == NULL) |
673a394b EA |
2483 | return 0; |
2484 | ||
31d8d651 CW |
2485 | if (obj->pin_count) |
2486 | return -EBUSY; | |
673a394b | 2487 | |
c4670ad0 CW |
2488 | BUG_ON(obj->pages == NULL); |
2489 | ||
a8198eea | 2490 | ret = i915_gem_object_finish_gpu(obj); |
1488fc08 | 2491 | if (ret) |
a8198eea CW |
2492 | return ret; |
2493 | /* Continue on if we fail due to EIO, the GPU is hung so we | |
2494 | * should be safe and we need to cleanup or else we might | |
2495 | * cause memory corruption through use-after-free. | |
2496 | */ | |
2497 | ||
b5ffc9bc | 2498 | i915_gem_object_finish_gtt(obj); |
5323fd04 | 2499 | |
96b47b65 | 2500 | /* release the fence reg _after_ flushing */ |
d9e86c0e | 2501 | ret = i915_gem_object_put_fence(obj); |
1488fc08 | 2502 | if (ret) |
d9e86c0e | 2503 | return ret; |
96b47b65 | 2504 | |
db53a302 CW |
2505 | trace_i915_gem_object_unbind(obj); |
2506 | ||
74898d7e DV |
2507 | if (obj->has_global_gtt_mapping) |
2508 | i915_gem_gtt_unbind_object(obj); | |
7bddb01f DV |
2509 | if (obj->has_aliasing_ppgtt_mapping) { |
2510 | i915_ppgtt_unbind_object(dev_priv->mm.aliasing_ppgtt, obj); | |
2511 | obj->has_aliasing_ppgtt_mapping = 0; | |
2512 | } | |
74163907 | 2513 | i915_gem_gtt_finish_object(obj); |
7bddb01f | 2514 | |
6c085a72 CW |
2515 | list_del(&obj->mm_list); |
2516 | list_move_tail(&obj->gtt_list, &dev_priv->mm.unbound_list); | |
75e9e915 | 2517 | /* Avoid an unnecessary call to unbind on rebind. */ |
05394f39 | 2518 | obj->map_and_fenceable = true; |
673a394b | 2519 | |
05394f39 CW |
2520 | drm_mm_put_block(obj->gtt_space); |
2521 | obj->gtt_space = NULL; | |
2522 | obj->gtt_offset = 0; | |
673a394b | 2523 | |
88241785 | 2524 | return 0; |
54cf91dc CW |
2525 | } |
2526 | ||
b2da9fe5 | 2527 | int i915_gpu_idle(struct drm_device *dev) |
4df2faf4 DV |
2528 | { |
2529 | drm_i915_private_t *dev_priv = dev->dev_private; | |
b4519513 | 2530 | struct intel_ring_buffer *ring; |
1ec14ad3 | 2531 | int ret, i; |
4df2faf4 | 2532 | |
4df2faf4 | 2533 | /* Flush everything onto the inactive list. */ |
b4519513 | 2534 | for_each_ring(ring, dev_priv, i) { |
b6c7488d BW |
2535 | ret = i915_switch_context(ring, NULL, DEFAULT_CONTEXT_ID); |
2536 | if (ret) | |
2537 | return ret; | |
2538 | ||
3e960501 | 2539 | ret = intel_ring_idle(ring); |
1ec14ad3 CW |
2540 | if (ret) |
2541 | return ret; | |
2542 | } | |
4df2faf4 | 2543 | |
8a1a49f9 | 2544 | return 0; |
4df2faf4 DV |
2545 | } |
2546 | ||
9ce079e4 CW |
2547 | static void i965_write_fence_reg(struct drm_device *dev, int reg, |
2548 | struct drm_i915_gem_object *obj) | |
de151cf6 | 2549 | { |
de151cf6 | 2550 | drm_i915_private_t *dev_priv = dev->dev_private; |
56c844e5 ID |
2551 | int fence_reg; |
2552 | int fence_pitch_shift; | |
de151cf6 JB |
2553 | uint64_t val; |
2554 | ||
56c844e5 ID |
2555 | if (INTEL_INFO(dev)->gen >= 6) { |
2556 | fence_reg = FENCE_REG_SANDYBRIDGE_0; | |
2557 | fence_pitch_shift = SANDYBRIDGE_FENCE_PITCH_SHIFT; | |
2558 | } else { | |
2559 | fence_reg = FENCE_REG_965_0; | |
2560 | fence_pitch_shift = I965_FENCE_PITCH_SHIFT; | |
2561 | } | |
2562 | ||
9ce079e4 CW |
2563 | if (obj) { |
2564 | u32 size = obj->gtt_space->size; | |
de151cf6 | 2565 | |
9ce079e4 CW |
2566 | val = (uint64_t)((obj->gtt_offset + size - 4096) & |
2567 | 0xfffff000) << 32; | |
2568 | val |= obj->gtt_offset & 0xfffff000; | |
56c844e5 | 2569 | val |= (uint64_t)((obj->stride / 128) - 1) << fence_pitch_shift; |
9ce079e4 CW |
2570 | if (obj->tiling_mode == I915_TILING_Y) |
2571 | val |= 1 << I965_FENCE_TILING_Y_SHIFT; | |
2572 | val |= I965_FENCE_REG_VALID; | |
2573 | } else | |
2574 | val = 0; | |
c6642782 | 2575 | |
56c844e5 ID |
2576 | fence_reg += reg * 8; |
2577 | I915_WRITE64(fence_reg, val); | |
2578 | POSTING_READ(fence_reg); | |
de151cf6 JB |
2579 | } |
2580 | ||
9ce079e4 CW |
2581 | static void i915_write_fence_reg(struct drm_device *dev, int reg, |
2582 | struct drm_i915_gem_object *obj) | |
de151cf6 | 2583 | { |
de151cf6 | 2584 | drm_i915_private_t *dev_priv = dev->dev_private; |
9ce079e4 | 2585 | u32 val; |
de151cf6 | 2586 | |
9ce079e4 CW |
2587 | if (obj) { |
2588 | u32 size = obj->gtt_space->size; | |
2589 | int pitch_val; | |
2590 | int tile_width; | |
c6642782 | 2591 | |
9ce079e4 CW |
2592 | WARN((obj->gtt_offset & ~I915_FENCE_START_MASK) || |
2593 | (size & -size) != size || | |
2594 | (obj->gtt_offset & (size - 1)), | |
2595 | "object 0x%08x [fenceable? %d] not 1M or pot-size (0x%08x) aligned\n", | |
2596 | obj->gtt_offset, obj->map_and_fenceable, size); | |
c6642782 | 2597 | |
9ce079e4 CW |
2598 | if (obj->tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev)) |
2599 | tile_width = 128; | |
2600 | else | |
2601 | tile_width = 512; | |
2602 | ||
2603 | /* Note: pitch better be a power of two tile widths */ | |
2604 | pitch_val = obj->stride / tile_width; | |
2605 | pitch_val = ffs(pitch_val) - 1; | |
2606 | ||
2607 | val = obj->gtt_offset; | |
2608 | if (obj->tiling_mode == I915_TILING_Y) | |
2609 | val |= 1 << I830_FENCE_TILING_Y_SHIFT; | |
2610 | val |= I915_FENCE_SIZE_BITS(size); | |
2611 | val |= pitch_val << I830_FENCE_PITCH_SHIFT; | |
2612 | val |= I830_FENCE_REG_VALID; | |
2613 | } else | |
2614 | val = 0; | |
2615 | ||
2616 | if (reg < 8) | |
2617 | reg = FENCE_REG_830_0 + reg * 4; | |
2618 | else | |
2619 | reg = FENCE_REG_945_8 + (reg - 8) * 4; | |
2620 | ||
2621 | I915_WRITE(reg, val); | |
2622 | POSTING_READ(reg); | |
de151cf6 JB |
2623 | } |
2624 | ||
9ce079e4 CW |
2625 | static void i830_write_fence_reg(struct drm_device *dev, int reg, |
2626 | struct drm_i915_gem_object *obj) | |
de151cf6 | 2627 | { |
de151cf6 | 2628 | drm_i915_private_t *dev_priv = dev->dev_private; |
de151cf6 | 2629 | uint32_t val; |
de151cf6 | 2630 | |
9ce079e4 CW |
2631 | if (obj) { |
2632 | u32 size = obj->gtt_space->size; | |
2633 | uint32_t pitch_val; | |
de151cf6 | 2634 | |
9ce079e4 CW |
2635 | WARN((obj->gtt_offset & ~I830_FENCE_START_MASK) || |
2636 | (size & -size) != size || | |
2637 | (obj->gtt_offset & (size - 1)), | |
2638 | "object 0x%08x not 512K or pot-size 0x%08x aligned\n", | |
2639 | obj->gtt_offset, size); | |
e76a16de | 2640 | |
9ce079e4 CW |
2641 | pitch_val = obj->stride / 128; |
2642 | pitch_val = ffs(pitch_val) - 1; | |
de151cf6 | 2643 | |
9ce079e4 CW |
2644 | val = obj->gtt_offset; |
2645 | if (obj->tiling_mode == I915_TILING_Y) | |
2646 | val |= 1 << I830_FENCE_TILING_Y_SHIFT; | |
2647 | val |= I830_FENCE_SIZE_BITS(size); | |
2648 | val |= pitch_val << I830_FENCE_PITCH_SHIFT; | |
2649 | val |= I830_FENCE_REG_VALID; | |
2650 | } else | |
2651 | val = 0; | |
c6642782 | 2652 | |
9ce079e4 CW |
2653 | I915_WRITE(FENCE_REG_830_0 + reg * 4, val); |
2654 | POSTING_READ(FENCE_REG_830_0 + reg * 4); | |
2655 | } | |
2656 | ||
d0a57789 CW |
2657 | inline static bool i915_gem_object_needs_mb(struct drm_i915_gem_object *obj) |
2658 | { | |
2659 | return obj && obj->base.read_domains & I915_GEM_DOMAIN_GTT; | |
2660 | } | |
2661 | ||
9ce079e4 CW |
2662 | static void i915_gem_write_fence(struct drm_device *dev, int reg, |
2663 | struct drm_i915_gem_object *obj) | |
2664 | { | |
d0a57789 CW |
2665 | struct drm_i915_private *dev_priv = dev->dev_private; |
2666 | ||
2667 | /* Ensure that all CPU reads are completed before installing a fence | |
2668 | * and all writes before removing the fence. | |
2669 | */ | |
2670 | if (i915_gem_object_needs_mb(dev_priv->fence_regs[reg].obj)) | |
2671 | mb(); | |
2672 | ||
9ce079e4 CW |
2673 | switch (INTEL_INFO(dev)->gen) { |
2674 | case 7: | |
56c844e5 | 2675 | case 6: |
9ce079e4 CW |
2676 | case 5: |
2677 | case 4: i965_write_fence_reg(dev, reg, obj); break; | |
2678 | case 3: i915_write_fence_reg(dev, reg, obj); break; | |
2679 | case 2: i830_write_fence_reg(dev, reg, obj); break; | |
7dbf9d6e | 2680 | default: BUG(); |
9ce079e4 | 2681 | } |
d0a57789 CW |
2682 | |
2683 | /* And similarly be paranoid that no direct access to this region | |
2684 | * is reordered to before the fence is installed. | |
2685 | */ | |
2686 | if (i915_gem_object_needs_mb(obj)) | |
2687 | mb(); | |
de151cf6 JB |
2688 | } |
2689 | ||
61050808 CW |
2690 | static inline int fence_number(struct drm_i915_private *dev_priv, |
2691 | struct drm_i915_fence_reg *fence) | |
2692 | { | |
2693 | return fence - dev_priv->fence_regs; | |
2694 | } | |
2695 | ||
25ff1195 CW |
2696 | static void i915_gem_write_fence__ipi(void *data) |
2697 | { | |
2698 | wbinvd(); | |
2699 | } | |
2700 | ||
61050808 CW |
2701 | static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj, |
2702 | struct drm_i915_fence_reg *fence, | |
2703 | bool enable) | |
2704 | { | |
25ff1195 CW |
2705 | struct drm_device *dev = obj->base.dev; |
2706 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2707 | int fence_reg = fence_number(dev_priv, fence); | |
2708 | ||
2709 | /* In order to fully serialize access to the fenced region and | |
2710 | * the update to the fence register we need to take extreme | |
2711 | * measures on SNB+. In theory, the write to the fence register | |
2712 | * flushes all memory transactions before, and coupled with the | |
2713 | * mb() placed around the register write we serialise all memory | |
2714 | * operations with respect to the changes in the tiler. Yet, on | |
2715 | * SNB+ we need to take a step further and emit an explicit wbinvd() | |
2716 | * on each processor in order to manually flush all memory | |
2717 | * transactions before updating the fence register. | |
2718 | */ | |
2719 | if (HAS_LLC(obj->base.dev)) | |
2720 | on_each_cpu(i915_gem_write_fence__ipi, NULL, 1); | |
2721 | i915_gem_write_fence(dev, fence_reg, enable ? obj : NULL); | |
61050808 CW |
2722 | |
2723 | if (enable) { | |
25ff1195 | 2724 | obj->fence_reg = fence_reg; |
61050808 CW |
2725 | fence->obj = obj; |
2726 | list_move_tail(&fence->lru_list, &dev_priv->mm.fence_list); | |
2727 | } else { | |
2728 | obj->fence_reg = I915_FENCE_REG_NONE; | |
2729 | fence->obj = NULL; | |
2730 | list_del_init(&fence->lru_list); | |
2731 | } | |
2732 | } | |
2733 | ||
d9e86c0e | 2734 | static int |
d0a57789 | 2735 | i915_gem_object_wait_fence(struct drm_i915_gem_object *obj) |
d9e86c0e | 2736 | { |
1c293ea3 | 2737 | if (obj->last_fenced_seqno) { |
86d5bc37 | 2738 | int ret = i915_wait_seqno(obj->ring, obj->last_fenced_seqno); |
18991845 CW |
2739 | if (ret) |
2740 | return ret; | |
d9e86c0e CW |
2741 | |
2742 | obj->last_fenced_seqno = 0; | |
d9e86c0e CW |
2743 | } |
2744 | ||
86d5bc37 | 2745 | obj->fenced_gpu_access = false; |
d9e86c0e CW |
2746 | return 0; |
2747 | } | |
2748 | ||
2749 | int | |
2750 | i915_gem_object_put_fence(struct drm_i915_gem_object *obj) | |
2751 | { | |
61050808 | 2752 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
f9c513e9 | 2753 | struct drm_i915_fence_reg *fence; |
d9e86c0e CW |
2754 | int ret; |
2755 | ||
d0a57789 | 2756 | ret = i915_gem_object_wait_fence(obj); |
d9e86c0e CW |
2757 | if (ret) |
2758 | return ret; | |
2759 | ||
61050808 CW |
2760 | if (obj->fence_reg == I915_FENCE_REG_NONE) |
2761 | return 0; | |
d9e86c0e | 2762 | |
f9c513e9 CW |
2763 | fence = &dev_priv->fence_regs[obj->fence_reg]; |
2764 | ||
61050808 | 2765 | i915_gem_object_fence_lost(obj); |
f9c513e9 | 2766 | i915_gem_object_update_fence(obj, fence, false); |
d9e86c0e CW |
2767 | |
2768 | return 0; | |
2769 | } | |
2770 | ||
2771 | static struct drm_i915_fence_reg * | |
a360bb1a | 2772 | i915_find_fence_reg(struct drm_device *dev) |
ae3db24a | 2773 | { |
ae3db24a | 2774 | struct drm_i915_private *dev_priv = dev->dev_private; |
8fe301ad | 2775 | struct drm_i915_fence_reg *reg, *avail; |
d9e86c0e | 2776 | int i; |
ae3db24a DV |
2777 | |
2778 | /* First try to find a free reg */ | |
d9e86c0e | 2779 | avail = NULL; |
ae3db24a DV |
2780 | for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) { |
2781 | reg = &dev_priv->fence_regs[i]; | |
2782 | if (!reg->obj) | |
d9e86c0e | 2783 | return reg; |
ae3db24a | 2784 | |
1690e1eb | 2785 | if (!reg->pin_count) |
d9e86c0e | 2786 | avail = reg; |
ae3db24a DV |
2787 | } |
2788 | ||
d9e86c0e CW |
2789 | if (avail == NULL) |
2790 | return NULL; | |
ae3db24a DV |
2791 | |
2792 | /* None available, try to steal one or wait for a user to finish */ | |
d9e86c0e | 2793 | list_for_each_entry(reg, &dev_priv->mm.fence_list, lru_list) { |
1690e1eb | 2794 | if (reg->pin_count) |
ae3db24a DV |
2795 | continue; |
2796 | ||
8fe301ad | 2797 | return reg; |
ae3db24a DV |
2798 | } |
2799 | ||
8fe301ad | 2800 | return NULL; |
ae3db24a DV |
2801 | } |
2802 | ||
de151cf6 | 2803 | /** |
9a5a53b3 | 2804 | * i915_gem_object_get_fence - set up fencing for an object |
de151cf6 JB |
2805 | * @obj: object to map through a fence reg |
2806 | * | |
2807 | * When mapping objects through the GTT, userspace wants to be able to write | |
2808 | * to them without having to worry about swizzling if the object is tiled. | |
de151cf6 JB |
2809 | * This function walks the fence regs looking for a free one for @obj, |
2810 | * stealing one if it can't find any. | |
2811 | * | |
2812 | * It then sets up the reg based on the object's properties: address, pitch | |
2813 | * and tiling format. | |
9a5a53b3 CW |
2814 | * |
2815 | * For an untiled surface, this removes any existing fence. | |
de151cf6 | 2816 | */ |
8c4b8c3f | 2817 | int |
06d98131 | 2818 | i915_gem_object_get_fence(struct drm_i915_gem_object *obj) |
de151cf6 | 2819 | { |
05394f39 | 2820 | struct drm_device *dev = obj->base.dev; |
79e53945 | 2821 | struct drm_i915_private *dev_priv = dev->dev_private; |
14415745 | 2822 | bool enable = obj->tiling_mode != I915_TILING_NONE; |
d9e86c0e | 2823 | struct drm_i915_fence_reg *reg; |
ae3db24a | 2824 | int ret; |
de151cf6 | 2825 | |
14415745 CW |
2826 | /* Have we updated the tiling parameters upon the object and so |
2827 | * will need to serialise the write to the associated fence register? | |
2828 | */ | |
5d82e3e6 | 2829 | if (obj->fence_dirty) { |
d0a57789 | 2830 | ret = i915_gem_object_wait_fence(obj); |
14415745 CW |
2831 | if (ret) |
2832 | return ret; | |
2833 | } | |
9a5a53b3 | 2834 | |
d9e86c0e | 2835 | /* Just update our place in the LRU if our fence is getting reused. */ |
05394f39 CW |
2836 | if (obj->fence_reg != I915_FENCE_REG_NONE) { |
2837 | reg = &dev_priv->fence_regs[obj->fence_reg]; | |
5d82e3e6 | 2838 | if (!obj->fence_dirty) { |
14415745 CW |
2839 | list_move_tail(®->lru_list, |
2840 | &dev_priv->mm.fence_list); | |
2841 | return 0; | |
2842 | } | |
2843 | } else if (enable) { | |
2844 | reg = i915_find_fence_reg(dev); | |
2845 | if (reg == NULL) | |
2846 | return -EDEADLK; | |
d9e86c0e | 2847 | |
14415745 CW |
2848 | if (reg->obj) { |
2849 | struct drm_i915_gem_object *old = reg->obj; | |
2850 | ||
d0a57789 | 2851 | ret = i915_gem_object_wait_fence(old); |
29c5a587 CW |
2852 | if (ret) |
2853 | return ret; | |
2854 | ||
14415745 | 2855 | i915_gem_object_fence_lost(old); |
29c5a587 | 2856 | } |
14415745 | 2857 | } else |
a09ba7fa | 2858 | return 0; |
a09ba7fa | 2859 | |
14415745 | 2860 | i915_gem_object_update_fence(obj, reg, enable); |
5d82e3e6 | 2861 | obj->fence_dirty = false; |
14415745 | 2862 | |
9ce079e4 | 2863 | return 0; |
de151cf6 JB |
2864 | } |
2865 | ||
42d6ab48 CW |
2866 | static bool i915_gem_valid_gtt_space(struct drm_device *dev, |
2867 | struct drm_mm_node *gtt_space, | |
2868 | unsigned long cache_level) | |
2869 | { | |
2870 | struct drm_mm_node *other; | |
2871 | ||
2872 | /* On non-LLC machines we have to be careful when putting differing | |
2873 | * types of snoopable memory together to avoid the prefetcher | |
4239ca77 | 2874 | * crossing memory domains and dying. |
42d6ab48 CW |
2875 | */ |
2876 | if (HAS_LLC(dev)) | |
2877 | return true; | |
2878 | ||
2879 | if (gtt_space == NULL) | |
2880 | return true; | |
2881 | ||
2882 | if (list_empty(>t_space->node_list)) | |
2883 | return true; | |
2884 | ||
2885 | other = list_entry(gtt_space->node_list.prev, struct drm_mm_node, node_list); | |
2886 | if (other->allocated && !other->hole_follows && other->color != cache_level) | |
2887 | return false; | |
2888 | ||
2889 | other = list_entry(gtt_space->node_list.next, struct drm_mm_node, node_list); | |
2890 | if (other->allocated && !gtt_space->hole_follows && other->color != cache_level) | |
2891 | return false; | |
2892 | ||
2893 | return true; | |
2894 | } | |
2895 | ||
2896 | static void i915_gem_verify_gtt(struct drm_device *dev) | |
2897 | { | |
2898 | #if WATCH_GTT | |
2899 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2900 | struct drm_i915_gem_object *obj; | |
2901 | int err = 0; | |
2902 | ||
2903 | list_for_each_entry(obj, &dev_priv->mm.gtt_list, gtt_list) { | |
2904 | if (obj->gtt_space == NULL) { | |
2905 | printk(KERN_ERR "object found on GTT list with no space reserved\n"); | |
2906 | err++; | |
2907 | continue; | |
2908 | } | |
2909 | ||
2910 | if (obj->cache_level != obj->gtt_space->color) { | |
2911 | printk(KERN_ERR "object reserved space [%08lx, %08lx] with wrong color, cache_level=%x, color=%lx\n", | |
2912 | obj->gtt_space->start, | |
2913 | obj->gtt_space->start + obj->gtt_space->size, | |
2914 | obj->cache_level, | |
2915 | obj->gtt_space->color); | |
2916 | err++; | |
2917 | continue; | |
2918 | } | |
2919 | ||
2920 | if (!i915_gem_valid_gtt_space(dev, | |
2921 | obj->gtt_space, | |
2922 | obj->cache_level)) { | |
2923 | printk(KERN_ERR "invalid GTT space found at [%08lx, %08lx] - color=%x\n", | |
2924 | obj->gtt_space->start, | |
2925 | obj->gtt_space->start + obj->gtt_space->size, | |
2926 | obj->cache_level); | |
2927 | err++; | |
2928 | continue; | |
2929 | } | |
2930 | } | |
2931 | ||
2932 | WARN_ON(err); | |
2933 | #endif | |
2934 | } | |
2935 | ||
673a394b EA |
2936 | /** |
2937 | * Finds free space in the GTT aperture and binds the object there. | |
2938 | */ | |
2939 | static int | |
05394f39 | 2940 | i915_gem_object_bind_to_gtt(struct drm_i915_gem_object *obj, |
920afa77 | 2941 | unsigned alignment, |
86a1ee26 CW |
2942 | bool map_and_fenceable, |
2943 | bool nonblocking) | |
673a394b | 2944 | { |
05394f39 | 2945 | struct drm_device *dev = obj->base.dev; |
673a394b | 2946 | drm_i915_private_t *dev_priv = dev->dev_private; |
dc9dd7a2 | 2947 | struct drm_mm_node *node; |
5e783301 | 2948 | u32 size, fence_size, fence_alignment, unfenced_alignment; |
75e9e915 | 2949 | bool mappable, fenceable; |
07f73f69 | 2950 | int ret; |
673a394b | 2951 | |
e28f8711 CW |
2952 | fence_size = i915_gem_get_gtt_size(dev, |
2953 | obj->base.size, | |
2954 | obj->tiling_mode); | |
2955 | fence_alignment = i915_gem_get_gtt_alignment(dev, | |
2956 | obj->base.size, | |
d865110c | 2957 | obj->tiling_mode, true); |
e28f8711 | 2958 | unfenced_alignment = |
d865110c | 2959 | i915_gem_get_gtt_alignment(dev, |
e28f8711 | 2960 | obj->base.size, |
d865110c | 2961 | obj->tiling_mode, false); |
a00b10c3 | 2962 | |
673a394b | 2963 | if (alignment == 0) |
5e783301 DV |
2964 | alignment = map_and_fenceable ? fence_alignment : |
2965 | unfenced_alignment; | |
75e9e915 | 2966 | if (map_and_fenceable && alignment & (fence_alignment - 1)) { |
673a394b EA |
2967 | DRM_ERROR("Invalid object alignment requested %u\n", alignment); |
2968 | return -EINVAL; | |
2969 | } | |
2970 | ||
05394f39 | 2971 | size = map_and_fenceable ? fence_size : obj->base.size; |
a00b10c3 | 2972 | |
654fc607 CW |
2973 | /* If the object is bigger than the entire aperture, reject it early |
2974 | * before evicting everything in a vain attempt to find space. | |
2975 | */ | |
05394f39 | 2976 | if (obj->base.size > |
5d4545ae | 2977 | (map_and_fenceable ? dev_priv->gtt.mappable_end : dev_priv->gtt.total)) { |
a36689cb CW |
2978 | DRM_ERROR("Attempting to bind an object larger than the aperture: object=%zd > %s aperture=%ld\n", |
2979 | obj->base.size, | |
2980 | map_and_fenceable ? "mappable" : "total", | |
2981 | map_and_fenceable ? dev_priv->gtt.mappable_end : dev_priv->gtt.total); | |
654fc607 CW |
2982 | return -E2BIG; |
2983 | } | |
2984 | ||
37e680a1 | 2985 | ret = i915_gem_object_get_pages(obj); |
6c085a72 CW |
2986 | if (ret) |
2987 | return ret; | |
2988 | ||
fbdda6fb CW |
2989 | i915_gem_object_pin_pages(obj); |
2990 | ||
dc9dd7a2 CW |
2991 | node = kzalloc(sizeof(*node), GFP_KERNEL); |
2992 | if (node == NULL) { | |
2993 | i915_gem_object_unpin_pages(obj); | |
2994 | return -ENOMEM; | |
2995 | } | |
2996 | ||
673a394b | 2997 | search_free: |
75e9e915 | 2998 | if (map_and_fenceable) |
dc9dd7a2 CW |
2999 | ret = drm_mm_insert_node_in_range_generic(&dev_priv->mm.gtt_space, node, |
3000 | size, alignment, obj->cache_level, | |
5d4545ae | 3001 | 0, dev_priv->gtt.mappable_end); |
920afa77 | 3002 | else |
dc9dd7a2 CW |
3003 | ret = drm_mm_insert_node_generic(&dev_priv->mm.gtt_space, node, |
3004 | size, alignment, obj->cache_level); | |
3005 | if (ret) { | |
75e9e915 | 3006 | ret = i915_gem_evict_something(dev, size, alignment, |
42d6ab48 | 3007 | obj->cache_level, |
86a1ee26 CW |
3008 | map_and_fenceable, |
3009 | nonblocking); | |
dc9dd7a2 CW |
3010 | if (ret == 0) |
3011 | goto search_free; | |
9731129c | 3012 | |
dc9dd7a2 CW |
3013 | i915_gem_object_unpin_pages(obj); |
3014 | kfree(node); | |
3015 | return ret; | |
673a394b | 3016 | } |
dc9dd7a2 | 3017 | if (WARN_ON(!i915_gem_valid_gtt_space(dev, node, obj->cache_level))) { |
fbdda6fb | 3018 | i915_gem_object_unpin_pages(obj); |
dc9dd7a2 | 3019 | drm_mm_put_block(node); |
42d6ab48 | 3020 | return -EINVAL; |
673a394b EA |
3021 | } |
3022 | ||
74163907 | 3023 | ret = i915_gem_gtt_prepare_object(obj); |
7c2e6fdf | 3024 | if (ret) { |
fbdda6fb | 3025 | i915_gem_object_unpin_pages(obj); |
dc9dd7a2 | 3026 | drm_mm_put_block(node); |
6c085a72 | 3027 | return ret; |
673a394b | 3028 | } |
673a394b | 3029 | |
6c085a72 | 3030 | list_move_tail(&obj->gtt_list, &dev_priv->mm.bound_list); |
05394f39 | 3031 | list_add_tail(&obj->mm_list, &dev_priv->mm.inactive_list); |
bf1a1092 | 3032 | |
dc9dd7a2 CW |
3033 | obj->gtt_space = node; |
3034 | obj->gtt_offset = node->start; | |
1c5d22f7 | 3035 | |
75e9e915 | 3036 | fenceable = |
dc9dd7a2 CW |
3037 | node->size == fence_size && |
3038 | (node->start & (fence_alignment - 1)) == 0; | |
a00b10c3 | 3039 | |
75e9e915 | 3040 | mappable = |
5d4545ae | 3041 | obj->gtt_offset + obj->base.size <= dev_priv->gtt.mappable_end; |
a00b10c3 | 3042 | |
05394f39 | 3043 | obj->map_and_fenceable = mappable && fenceable; |
75e9e915 | 3044 | |
fbdda6fb | 3045 | i915_gem_object_unpin_pages(obj); |
db53a302 | 3046 | trace_i915_gem_object_bind(obj, map_and_fenceable); |
42d6ab48 | 3047 | i915_gem_verify_gtt(dev); |
673a394b EA |
3048 | return 0; |
3049 | } | |
3050 | ||
3051 | void | |
05394f39 | 3052 | i915_gem_clflush_object(struct drm_i915_gem_object *obj) |
673a394b | 3053 | { |
673a394b EA |
3054 | /* If we don't have a page list set up, then we're not pinned |
3055 | * to GPU, and we can ignore the cache flush because it'll happen | |
3056 | * again at bind time. | |
3057 | */ | |
05394f39 | 3058 | if (obj->pages == NULL) |
673a394b EA |
3059 | return; |
3060 | ||
769ce464 ID |
3061 | /* |
3062 | * Stolen memory is always coherent with the GPU as it is explicitly | |
3063 | * marked as wc by the system, or the system is cache-coherent. | |
3064 | */ | |
3065 | if (obj->stolen) | |
3066 | return; | |
3067 | ||
9c23f7fc CW |
3068 | /* If the GPU is snooping the contents of the CPU cache, |
3069 | * we do not need to manually clear the CPU cache lines. However, | |
3070 | * the caches are only snooped when the render cache is | |
3071 | * flushed/invalidated. As we always have to emit invalidations | |
3072 | * and flushes when moving into and out of the RENDER domain, correct | |
3073 | * snooping behaviour occurs naturally as the result of our domain | |
3074 | * tracking. | |
3075 | */ | |
3076 | if (obj->cache_level != I915_CACHE_NONE) | |
3077 | return; | |
3078 | ||
1c5d22f7 | 3079 | trace_i915_gem_object_clflush(obj); |
cfa16a0d | 3080 | |
9da3da66 | 3081 | drm_clflush_sg(obj->pages); |
e47c68e9 EA |
3082 | } |
3083 | ||
3084 | /** Flushes the GTT write domain for the object if it's dirty. */ | |
3085 | static void | |
05394f39 | 3086 | i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj) |
e47c68e9 | 3087 | { |
1c5d22f7 CW |
3088 | uint32_t old_write_domain; |
3089 | ||
05394f39 | 3090 | if (obj->base.write_domain != I915_GEM_DOMAIN_GTT) |
e47c68e9 EA |
3091 | return; |
3092 | ||
63256ec5 | 3093 | /* No actual flushing is required for the GTT write domain. Writes |
e47c68e9 EA |
3094 | * to it immediately go to main memory as far as we know, so there's |
3095 | * no chipset flush. It also doesn't land in render cache. | |
63256ec5 CW |
3096 | * |
3097 | * However, we do have to enforce the order so that all writes through | |
3098 | * the GTT land before any writes to the device, such as updates to | |
3099 | * the GATT itself. | |
e47c68e9 | 3100 | */ |
63256ec5 CW |
3101 | wmb(); |
3102 | ||
05394f39 CW |
3103 | old_write_domain = obj->base.write_domain; |
3104 | obj->base.write_domain = 0; | |
1c5d22f7 CW |
3105 | |
3106 | trace_i915_gem_object_change_domain(obj, | |
05394f39 | 3107 | obj->base.read_domains, |
1c5d22f7 | 3108 | old_write_domain); |
e47c68e9 EA |
3109 | } |
3110 | ||
3111 | /** Flushes the CPU write domain for the object if it's dirty. */ | |
3112 | static void | |
05394f39 | 3113 | i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj) |
e47c68e9 | 3114 | { |
1c5d22f7 | 3115 | uint32_t old_write_domain; |
e47c68e9 | 3116 | |
05394f39 | 3117 | if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) |
e47c68e9 EA |
3118 | return; |
3119 | ||
3120 | i915_gem_clflush_object(obj); | |
e76e9aeb | 3121 | i915_gem_chipset_flush(obj->base.dev); |
05394f39 CW |
3122 | old_write_domain = obj->base.write_domain; |
3123 | obj->base.write_domain = 0; | |
1c5d22f7 CW |
3124 | |
3125 | trace_i915_gem_object_change_domain(obj, | |
05394f39 | 3126 | obj->base.read_domains, |
1c5d22f7 | 3127 | old_write_domain); |
e47c68e9 EA |
3128 | } |
3129 | ||
2ef7eeaa EA |
3130 | /** |
3131 | * Moves a single object to the GTT read, and possibly write domain. | |
3132 | * | |
3133 | * This function returns when the move is complete, including waiting on | |
3134 | * flushes to occur. | |
3135 | */ | |
79e53945 | 3136 | int |
2021746e | 3137 | i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write) |
2ef7eeaa | 3138 | { |
8325a09d | 3139 | drm_i915_private_t *dev_priv = obj->base.dev->dev_private; |
1c5d22f7 | 3140 | uint32_t old_write_domain, old_read_domains; |
e47c68e9 | 3141 | int ret; |
2ef7eeaa | 3142 | |
02354392 | 3143 | /* Not valid to be called on unbound objects. */ |
05394f39 | 3144 | if (obj->gtt_space == NULL) |
02354392 EA |
3145 | return -EINVAL; |
3146 | ||
8d7e3de1 CW |
3147 | if (obj->base.write_domain == I915_GEM_DOMAIN_GTT) |
3148 | return 0; | |
3149 | ||
0201f1ec | 3150 | ret = i915_gem_object_wait_rendering(obj, !write); |
88241785 CW |
3151 | if (ret) |
3152 | return ret; | |
3153 | ||
7213342d | 3154 | i915_gem_object_flush_cpu_write_domain(obj); |
1c5d22f7 | 3155 | |
d0a57789 CW |
3156 | /* Serialise direct access to this object with the barriers for |
3157 | * coherent writes from the GPU, by effectively invalidating the | |
3158 | * GTT domain upon first access. | |
3159 | */ | |
3160 | if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0) | |
3161 | mb(); | |
3162 | ||
05394f39 CW |
3163 | old_write_domain = obj->base.write_domain; |
3164 | old_read_domains = obj->base.read_domains; | |
1c5d22f7 | 3165 | |
e47c68e9 EA |
3166 | /* It should now be out of any other write domains, and we can update |
3167 | * the domain values for our changes. | |
3168 | */ | |
05394f39 CW |
3169 | BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) != 0); |
3170 | obj->base.read_domains |= I915_GEM_DOMAIN_GTT; | |
e47c68e9 | 3171 | if (write) { |
05394f39 CW |
3172 | obj->base.read_domains = I915_GEM_DOMAIN_GTT; |
3173 | obj->base.write_domain = I915_GEM_DOMAIN_GTT; | |
3174 | obj->dirty = 1; | |
2ef7eeaa EA |
3175 | } |
3176 | ||
1c5d22f7 CW |
3177 | trace_i915_gem_object_change_domain(obj, |
3178 | old_read_domains, | |
3179 | old_write_domain); | |
3180 | ||
8325a09d CW |
3181 | /* And bump the LRU for this access */ |
3182 | if (i915_gem_object_is_inactive(obj)) | |
3183 | list_move_tail(&obj->mm_list, &dev_priv->mm.inactive_list); | |
3184 | ||
e47c68e9 EA |
3185 | return 0; |
3186 | } | |
3187 | ||
e4ffd173 CW |
3188 | int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj, |
3189 | enum i915_cache_level cache_level) | |
3190 | { | |
7bddb01f DV |
3191 | struct drm_device *dev = obj->base.dev; |
3192 | drm_i915_private_t *dev_priv = dev->dev_private; | |
e4ffd173 CW |
3193 | int ret; |
3194 | ||
3195 | if (obj->cache_level == cache_level) | |
3196 | return 0; | |
3197 | ||
3198 | if (obj->pin_count) { | |
3199 | DRM_DEBUG("can not change the cache level of pinned objects\n"); | |
3200 | return -EBUSY; | |
3201 | } | |
3202 | ||
42d6ab48 CW |
3203 | if (!i915_gem_valid_gtt_space(dev, obj->gtt_space, cache_level)) { |
3204 | ret = i915_gem_object_unbind(obj); | |
3205 | if (ret) | |
3206 | return ret; | |
3207 | } | |
3208 | ||
e4ffd173 CW |
3209 | if (obj->gtt_space) { |
3210 | ret = i915_gem_object_finish_gpu(obj); | |
3211 | if (ret) | |
3212 | return ret; | |
3213 | ||
3214 | i915_gem_object_finish_gtt(obj); | |
3215 | ||
3216 | /* Before SandyBridge, you could not use tiling or fence | |
3217 | * registers with snooped memory, so relinquish any fences | |
3218 | * currently pointing to our region in the aperture. | |
3219 | */ | |
42d6ab48 | 3220 | if (INTEL_INFO(dev)->gen < 6) { |
e4ffd173 CW |
3221 | ret = i915_gem_object_put_fence(obj); |
3222 | if (ret) | |
3223 | return ret; | |
3224 | } | |
3225 | ||
74898d7e DV |
3226 | if (obj->has_global_gtt_mapping) |
3227 | i915_gem_gtt_bind_object(obj, cache_level); | |
7bddb01f DV |
3228 | if (obj->has_aliasing_ppgtt_mapping) |
3229 | i915_ppgtt_bind_object(dev_priv->mm.aliasing_ppgtt, | |
3230 | obj, cache_level); | |
42d6ab48 CW |
3231 | |
3232 | obj->gtt_space->color = cache_level; | |
e4ffd173 CW |
3233 | } |
3234 | ||
3235 | if (cache_level == I915_CACHE_NONE) { | |
3236 | u32 old_read_domains, old_write_domain; | |
3237 | ||
3238 | /* If we're coming from LLC cached, then we haven't | |
3239 | * actually been tracking whether the data is in the | |
3240 | * CPU cache or not, since we only allow one bit set | |
3241 | * in obj->write_domain and have been skipping the clflushes. | |
3242 | * Just set it to the CPU cache for now. | |
3243 | */ | |
3244 | WARN_ON(obj->base.write_domain & ~I915_GEM_DOMAIN_CPU); | |
3245 | WARN_ON(obj->base.read_domains & ~I915_GEM_DOMAIN_CPU); | |
3246 | ||
3247 | old_read_domains = obj->base.read_domains; | |
3248 | old_write_domain = obj->base.write_domain; | |
3249 | ||
3250 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; | |
3251 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; | |
3252 | ||
3253 | trace_i915_gem_object_change_domain(obj, | |
3254 | old_read_domains, | |
3255 | old_write_domain); | |
3256 | } | |
3257 | ||
3258 | obj->cache_level = cache_level; | |
42d6ab48 | 3259 | i915_gem_verify_gtt(dev); |
e4ffd173 CW |
3260 | return 0; |
3261 | } | |
3262 | ||
199adf40 BW |
3263 | int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data, |
3264 | struct drm_file *file) | |
e6994aee | 3265 | { |
199adf40 | 3266 | struct drm_i915_gem_caching *args = data; |
e6994aee CW |
3267 | struct drm_i915_gem_object *obj; |
3268 | int ret; | |
3269 | ||
3270 | ret = i915_mutex_lock_interruptible(dev); | |
3271 | if (ret) | |
3272 | return ret; | |
3273 | ||
3274 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); | |
3275 | if (&obj->base == NULL) { | |
3276 | ret = -ENOENT; | |
3277 | goto unlock; | |
3278 | } | |
3279 | ||
199adf40 | 3280 | args->caching = obj->cache_level != I915_CACHE_NONE; |
e6994aee CW |
3281 | |
3282 | drm_gem_object_unreference(&obj->base); | |
3283 | unlock: | |
3284 | mutex_unlock(&dev->struct_mutex); | |
3285 | return ret; | |
3286 | } | |
3287 | ||
199adf40 BW |
3288 | int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data, |
3289 | struct drm_file *file) | |
e6994aee | 3290 | { |
199adf40 | 3291 | struct drm_i915_gem_caching *args = data; |
e6994aee CW |
3292 | struct drm_i915_gem_object *obj; |
3293 | enum i915_cache_level level; | |
3294 | int ret; | |
3295 | ||
199adf40 BW |
3296 | switch (args->caching) { |
3297 | case I915_CACHING_NONE: | |
e6994aee CW |
3298 | level = I915_CACHE_NONE; |
3299 | break; | |
199adf40 | 3300 | case I915_CACHING_CACHED: |
e6994aee CW |
3301 | level = I915_CACHE_LLC; |
3302 | break; | |
3303 | default: | |
3304 | return -EINVAL; | |
3305 | } | |
3306 | ||
3bc2913e BW |
3307 | ret = i915_mutex_lock_interruptible(dev); |
3308 | if (ret) | |
3309 | return ret; | |
3310 | ||
e6994aee CW |
3311 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
3312 | if (&obj->base == NULL) { | |
3313 | ret = -ENOENT; | |
3314 | goto unlock; | |
3315 | } | |
3316 | ||
3317 | ret = i915_gem_object_set_cache_level(obj, level); | |
3318 | ||
3319 | drm_gem_object_unreference(&obj->base); | |
3320 | unlock: | |
3321 | mutex_unlock(&dev->struct_mutex); | |
3322 | return ret; | |
3323 | } | |
3324 | ||
b9241ea3 | 3325 | /* |
2da3b9b9 CW |
3326 | * Prepare buffer for display plane (scanout, cursors, etc). |
3327 | * Can be called from an uninterruptible phase (modesetting) and allows | |
3328 | * any flushes to be pipelined (for pageflips). | |
b9241ea3 ZW |
3329 | */ |
3330 | int | |
2da3b9b9 CW |
3331 | i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj, |
3332 | u32 alignment, | |
919926ae | 3333 | struct intel_ring_buffer *pipelined) |
b9241ea3 | 3334 | { |
2da3b9b9 | 3335 | u32 old_read_domains, old_write_domain; |
b9241ea3 ZW |
3336 | int ret; |
3337 | ||
0be73284 | 3338 | if (pipelined != obj->ring) { |
2911a35b BW |
3339 | ret = i915_gem_object_sync(obj, pipelined); |
3340 | if (ret) | |
b9241ea3 ZW |
3341 | return ret; |
3342 | } | |
3343 | ||
a7ef0640 EA |
3344 | /* The display engine is not coherent with the LLC cache on gen6. As |
3345 | * a result, we make sure that the pinning that is about to occur is | |
3346 | * done with uncached PTEs. This is lowest common denominator for all | |
3347 | * chipsets. | |
3348 | * | |
3349 | * However for gen6+, we could do better by using the GFDT bit instead | |
3350 | * of uncaching, which would allow us to flush all the LLC-cached data | |
3351 | * with that bit in the PTE to main memory with just one PIPE_CONTROL. | |
3352 | */ | |
3353 | ret = i915_gem_object_set_cache_level(obj, I915_CACHE_NONE); | |
3354 | if (ret) | |
3355 | return ret; | |
3356 | ||
2da3b9b9 CW |
3357 | /* As the user may map the buffer once pinned in the display plane |
3358 | * (e.g. libkms for the bootup splash), we have to ensure that we | |
3359 | * always use map_and_fenceable for all scanout buffers. | |
3360 | */ | |
86a1ee26 | 3361 | ret = i915_gem_object_pin(obj, alignment, true, false); |
2da3b9b9 CW |
3362 | if (ret) |
3363 | return ret; | |
3364 | ||
b118c1e3 CW |
3365 | i915_gem_object_flush_cpu_write_domain(obj); |
3366 | ||
2da3b9b9 | 3367 | old_write_domain = obj->base.write_domain; |
05394f39 | 3368 | old_read_domains = obj->base.read_domains; |
2da3b9b9 CW |
3369 | |
3370 | /* It should now be out of any other write domains, and we can update | |
3371 | * the domain values for our changes. | |
3372 | */ | |
e5f1d962 | 3373 | obj->base.write_domain = 0; |
05394f39 | 3374 | obj->base.read_domains |= I915_GEM_DOMAIN_GTT; |
b9241ea3 ZW |
3375 | |
3376 | trace_i915_gem_object_change_domain(obj, | |
3377 | old_read_domains, | |
2da3b9b9 | 3378 | old_write_domain); |
b9241ea3 ZW |
3379 | |
3380 | return 0; | |
3381 | } | |
3382 | ||
85345517 | 3383 | int |
a8198eea | 3384 | i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj) |
85345517 | 3385 | { |
88241785 CW |
3386 | int ret; |
3387 | ||
a8198eea | 3388 | if ((obj->base.read_domains & I915_GEM_GPU_DOMAINS) == 0) |
85345517 CW |
3389 | return 0; |
3390 | ||
0201f1ec | 3391 | ret = i915_gem_object_wait_rendering(obj, false); |
c501ae7f CW |
3392 | if (ret) |
3393 | return ret; | |
3394 | ||
a8198eea CW |
3395 | /* Ensure that we invalidate the GPU's caches and TLBs. */ |
3396 | obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS; | |
c501ae7f | 3397 | return 0; |
85345517 CW |
3398 | } |
3399 | ||
e47c68e9 EA |
3400 | /** |
3401 | * Moves a single object to the CPU read, and possibly write domain. | |
3402 | * | |
3403 | * This function returns when the move is complete, including waiting on | |
3404 | * flushes to occur. | |
3405 | */ | |
dabdfe02 | 3406 | int |
919926ae | 3407 | i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write) |
e47c68e9 | 3408 | { |
1c5d22f7 | 3409 | uint32_t old_write_domain, old_read_domains; |
e47c68e9 EA |
3410 | int ret; |
3411 | ||
8d7e3de1 CW |
3412 | if (obj->base.write_domain == I915_GEM_DOMAIN_CPU) |
3413 | return 0; | |
3414 | ||
0201f1ec | 3415 | ret = i915_gem_object_wait_rendering(obj, !write); |
88241785 CW |
3416 | if (ret) |
3417 | return ret; | |
3418 | ||
e47c68e9 | 3419 | i915_gem_object_flush_gtt_write_domain(obj); |
2ef7eeaa | 3420 | |
05394f39 CW |
3421 | old_write_domain = obj->base.write_domain; |
3422 | old_read_domains = obj->base.read_domains; | |
1c5d22f7 | 3423 | |
e47c68e9 | 3424 | /* Flush the CPU cache if it's still invalid. */ |
05394f39 | 3425 | if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) { |
2ef7eeaa | 3426 | i915_gem_clflush_object(obj); |
2ef7eeaa | 3427 | |
05394f39 | 3428 | obj->base.read_domains |= I915_GEM_DOMAIN_CPU; |
2ef7eeaa EA |
3429 | } |
3430 | ||
3431 | /* It should now be out of any other write domains, and we can update | |
3432 | * the domain values for our changes. | |
3433 | */ | |
05394f39 | 3434 | BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) != 0); |
e47c68e9 EA |
3435 | |
3436 | /* If we're writing through the CPU, then the GPU read domains will | |
3437 | * need to be invalidated at next use. | |
3438 | */ | |
3439 | if (write) { | |
05394f39 CW |
3440 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; |
3441 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; | |
e47c68e9 | 3442 | } |
2ef7eeaa | 3443 | |
1c5d22f7 CW |
3444 | trace_i915_gem_object_change_domain(obj, |
3445 | old_read_domains, | |
3446 | old_write_domain); | |
3447 | ||
2ef7eeaa EA |
3448 | return 0; |
3449 | } | |
3450 | ||
673a394b EA |
3451 | /* Throttle our rendering by waiting until the ring has completed our requests |
3452 | * emitted over 20 msec ago. | |
3453 | * | |
b962442e EA |
3454 | * Note that if we were to use the current jiffies each time around the loop, |
3455 | * we wouldn't escape the function with any frames outstanding if the time to | |
3456 | * render a frame was over 20ms. | |
3457 | * | |
673a394b EA |
3458 | * This should get us reasonable parallelism between CPU and GPU but also |
3459 | * relatively low latency when blocking on a particular request to finish. | |
3460 | */ | |
40a5f0de | 3461 | static int |
f787a5f5 | 3462 | i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file) |
40a5f0de | 3463 | { |
f787a5f5 CW |
3464 | struct drm_i915_private *dev_priv = dev->dev_private; |
3465 | struct drm_i915_file_private *file_priv = file->driver_priv; | |
b962442e | 3466 | unsigned long recent_enough = jiffies - msecs_to_jiffies(20); |
f787a5f5 CW |
3467 | struct drm_i915_gem_request *request; |
3468 | struct intel_ring_buffer *ring = NULL; | |
f69061be | 3469 | unsigned reset_counter; |
f787a5f5 CW |
3470 | u32 seqno = 0; |
3471 | int ret; | |
93533c29 | 3472 | |
308887aa DV |
3473 | ret = i915_gem_wait_for_error(&dev_priv->gpu_error); |
3474 | if (ret) | |
3475 | return ret; | |
3476 | ||
3477 | ret = i915_gem_check_wedge(&dev_priv->gpu_error, false); | |
3478 | if (ret) | |
3479 | return ret; | |
e110e8d6 | 3480 | |
1c25595f | 3481 | spin_lock(&file_priv->mm.lock); |
f787a5f5 | 3482 | list_for_each_entry(request, &file_priv->mm.request_list, client_list) { |
b962442e EA |
3483 | if (time_after_eq(request->emitted_jiffies, recent_enough)) |
3484 | break; | |
40a5f0de | 3485 | |
f787a5f5 CW |
3486 | ring = request->ring; |
3487 | seqno = request->seqno; | |
b962442e | 3488 | } |
f69061be | 3489 | reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter); |
1c25595f | 3490 | spin_unlock(&file_priv->mm.lock); |
40a5f0de | 3491 | |
f787a5f5 CW |
3492 | if (seqno == 0) |
3493 | return 0; | |
2bc43b5c | 3494 | |
f69061be | 3495 | ret = __wait_seqno(ring, seqno, reset_counter, true, NULL); |
f787a5f5 CW |
3496 | if (ret == 0) |
3497 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, 0); | |
40a5f0de EA |
3498 | |
3499 | return ret; | |
3500 | } | |
3501 | ||
673a394b | 3502 | int |
05394f39 CW |
3503 | i915_gem_object_pin(struct drm_i915_gem_object *obj, |
3504 | uint32_t alignment, | |
86a1ee26 CW |
3505 | bool map_and_fenceable, |
3506 | bool nonblocking) | |
673a394b | 3507 | { |
673a394b EA |
3508 | int ret; |
3509 | ||
7e81a42e CW |
3510 | if (WARN_ON(obj->pin_count == DRM_I915_GEM_OBJECT_MAX_PIN_COUNT)) |
3511 | return -EBUSY; | |
ac0c6b5a | 3512 | |
05394f39 CW |
3513 | if (obj->gtt_space != NULL) { |
3514 | if ((alignment && obj->gtt_offset & (alignment - 1)) || | |
3515 | (map_and_fenceable && !obj->map_and_fenceable)) { | |
3516 | WARN(obj->pin_count, | |
ae7d49d8 | 3517 | "bo is already pinned with incorrect alignment:" |
75e9e915 DV |
3518 | " offset=%x, req.alignment=%x, req.map_and_fenceable=%d," |
3519 | " obj->map_and_fenceable=%d\n", | |
05394f39 | 3520 | obj->gtt_offset, alignment, |
75e9e915 | 3521 | map_and_fenceable, |
05394f39 | 3522 | obj->map_and_fenceable); |
ac0c6b5a CW |
3523 | ret = i915_gem_object_unbind(obj); |
3524 | if (ret) | |
3525 | return ret; | |
3526 | } | |
3527 | } | |
3528 | ||
05394f39 | 3529 | if (obj->gtt_space == NULL) { |
8742267a CW |
3530 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
3531 | ||
a00b10c3 | 3532 | ret = i915_gem_object_bind_to_gtt(obj, alignment, |
86a1ee26 CW |
3533 | map_and_fenceable, |
3534 | nonblocking); | |
9731129c | 3535 | if (ret) |
673a394b | 3536 | return ret; |
8742267a CW |
3537 | |
3538 | if (!dev_priv->mm.aliasing_ppgtt) | |
3539 | i915_gem_gtt_bind_object(obj, obj->cache_level); | |
22c344e9 | 3540 | } |
76446cac | 3541 | |
74898d7e DV |
3542 | if (!obj->has_global_gtt_mapping && map_and_fenceable) |
3543 | i915_gem_gtt_bind_object(obj, obj->cache_level); | |
3544 | ||
1b50247a | 3545 | obj->pin_count++; |
6299f992 | 3546 | obj->pin_mappable |= map_and_fenceable; |
673a394b EA |
3547 | |
3548 | return 0; | |
3549 | } | |
3550 | ||
3551 | void | |
05394f39 | 3552 | i915_gem_object_unpin(struct drm_i915_gem_object *obj) |
673a394b | 3553 | { |
05394f39 CW |
3554 | BUG_ON(obj->pin_count == 0); |
3555 | BUG_ON(obj->gtt_space == NULL); | |
673a394b | 3556 | |
1b50247a | 3557 | if (--obj->pin_count == 0) |
6299f992 | 3558 | obj->pin_mappable = false; |
673a394b EA |
3559 | } |
3560 | ||
3561 | int | |
3562 | i915_gem_pin_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 3563 | struct drm_file *file) |
673a394b EA |
3564 | { |
3565 | struct drm_i915_gem_pin *args = data; | |
05394f39 | 3566 | struct drm_i915_gem_object *obj; |
673a394b EA |
3567 | int ret; |
3568 | ||
1d7cfea1 CW |
3569 | ret = i915_mutex_lock_interruptible(dev); |
3570 | if (ret) | |
3571 | return ret; | |
673a394b | 3572 | |
05394f39 | 3573 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 3574 | if (&obj->base == NULL) { |
1d7cfea1 CW |
3575 | ret = -ENOENT; |
3576 | goto unlock; | |
673a394b | 3577 | } |
673a394b | 3578 | |
05394f39 | 3579 | if (obj->madv != I915_MADV_WILLNEED) { |
bb6baf76 | 3580 | DRM_ERROR("Attempting to pin a purgeable buffer\n"); |
1d7cfea1 CW |
3581 | ret = -EINVAL; |
3582 | goto out; | |
3ef94daa CW |
3583 | } |
3584 | ||
05394f39 | 3585 | if (obj->pin_filp != NULL && obj->pin_filp != file) { |
79e53945 JB |
3586 | DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n", |
3587 | args->handle); | |
1d7cfea1 CW |
3588 | ret = -EINVAL; |
3589 | goto out; | |
79e53945 JB |
3590 | } |
3591 | ||
93be8788 | 3592 | if (obj->user_pin_count == 0) { |
86a1ee26 | 3593 | ret = i915_gem_object_pin(obj, args->alignment, true, false); |
1d7cfea1 CW |
3594 | if (ret) |
3595 | goto out; | |
673a394b EA |
3596 | } |
3597 | ||
93be8788 CW |
3598 | obj->user_pin_count++; |
3599 | obj->pin_filp = file; | |
3600 | ||
673a394b EA |
3601 | /* XXX - flush the CPU caches for pinned objects |
3602 | * as the X server doesn't manage domains yet | |
3603 | */ | |
e47c68e9 | 3604 | i915_gem_object_flush_cpu_write_domain(obj); |
05394f39 | 3605 | args->offset = obj->gtt_offset; |
1d7cfea1 | 3606 | out: |
05394f39 | 3607 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 3608 | unlock: |
673a394b | 3609 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 3610 | return ret; |
673a394b EA |
3611 | } |
3612 | ||
3613 | int | |
3614 | i915_gem_unpin_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 3615 | struct drm_file *file) |
673a394b EA |
3616 | { |
3617 | struct drm_i915_gem_pin *args = data; | |
05394f39 | 3618 | struct drm_i915_gem_object *obj; |
76c1dec1 | 3619 | int ret; |
673a394b | 3620 | |
1d7cfea1 CW |
3621 | ret = i915_mutex_lock_interruptible(dev); |
3622 | if (ret) | |
3623 | return ret; | |
673a394b | 3624 | |
05394f39 | 3625 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 3626 | if (&obj->base == NULL) { |
1d7cfea1 CW |
3627 | ret = -ENOENT; |
3628 | goto unlock; | |
673a394b | 3629 | } |
76c1dec1 | 3630 | |
05394f39 | 3631 | if (obj->pin_filp != file) { |
79e53945 JB |
3632 | DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n", |
3633 | args->handle); | |
1d7cfea1 CW |
3634 | ret = -EINVAL; |
3635 | goto out; | |
79e53945 | 3636 | } |
05394f39 CW |
3637 | obj->user_pin_count--; |
3638 | if (obj->user_pin_count == 0) { | |
3639 | obj->pin_filp = NULL; | |
79e53945 JB |
3640 | i915_gem_object_unpin(obj); |
3641 | } | |
673a394b | 3642 | |
1d7cfea1 | 3643 | out: |
05394f39 | 3644 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 3645 | unlock: |
673a394b | 3646 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 3647 | return ret; |
673a394b EA |
3648 | } |
3649 | ||
3650 | int | |
3651 | i915_gem_busy_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 3652 | struct drm_file *file) |
673a394b EA |
3653 | { |
3654 | struct drm_i915_gem_busy *args = data; | |
05394f39 | 3655 | struct drm_i915_gem_object *obj; |
30dbf0c0 CW |
3656 | int ret; |
3657 | ||
76c1dec1 | 3658 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 3659 | if (ret) |
76c1dec1 | 3660 | return ret; |
673a394b | 3661 | |
05394f39 | 3662 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 3663 | if (&obj->base == NULL) { |
1d7cfea1 CW |
3664 | ret = -ENOENT; |
3665 | goto unlock; | |
673a394b | 3666 | } |
d1b851fc | 3667 | |
0be555b6 CW |
3668 | /* Count all active objects as busy, even if they are currently not used |
3669 | * by the gpu. Users of this interface expect objects to eventually | |
3670 | * become non-busy without any further actions, therefore emit any | |
3671 | * necessary flushes here. | |
c4de0a5d | 3672 | */ |
30dfebf3 | 3673 | ret = i915_gem_object_flush_active(obj); |
0be555b6 | 3674 | |
30dfebf3 | 3675 | args->busy = obj->active; |
e9808edd CW |
3676 | if (obj->ring) { |
3677 | BUILD_BUG_ON(I915_NUM_RINGS > 16); | |
3678 | args->busy |= intel_ring_flag(obj->ring) << 16; | |
3679 | } | |
673a394b | 3680 | |
05394f39 | 3681 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 3682 | unlock: |
673a394b | 3683 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 3684 | return ret; |
673a394b EA |
3685 | } |
3686 | ||
3687 | int | |
3688 | i915_gem_throttle_ioctl(struct drm_device *dev, void *data, | |
3689 | struct drm_file *file_priv) | |
3690 | { | |
0206e353 | 3691 | return i915_gem_ring_throttle(dev, file_priv); |
673a394b EA |
3692 | } |
3693 | ||
3ef94daa CW |
3694 | int |
3695 | i915_gem_madvise_ioctl(struct drm_device *dev, void *data, | |
3696 | struct drm_file *file_priv) | |
3697 | { | |
3698 | struct drm_i915_gem_madvise *args = data; | |
05394f39 | 3699 | struct drm_i915_gem_object *obj; |
76c1dec1 | 3700 | int ret; |
3ef94daa CW |
3701 | |
3702 | switch (args->madv) { | |
3703 | case I915_MADV_DONTNEED: | |
3704 | case I915_MADV_WILLNEED: | |
3705 | break; | |
3706 | default: | |
3707 | return -EINVAL; | |
3708 | } | |
3709 | ||
1d7cfea1 CW |
3710 | ret = i915_mutex_lock_interruptible(dev); |
3711 | if (ret) | |
3712 | return ret; | |
3713 | ||
05394f39 | 3714 | obj = to_intel_bo(drm_gem_object_lookup(dev, file_priv, args->handle)); |
c8725226 | 3715 | if (&obj->base == NULL) { |
1d7cfea1 CW |
3716 | ret = -ENOENT; |
3717 | goto unlock; | |
3ef94daa | 3718 | } |
3ef94daa | 3719 | |
05394f39 | 3720 | if (obj->pin_count) { |
1d7cfea1 CW |
3721 | ret = -EINVAL; |
3722 | goto out; | |
3ef94daa CW |
3723 | } |
3724 | ||
05394f39 CW |
3725 | if (obj->madv != __I915_MADV_PURGED) |
3726 | obj->madv = args->madv; | |
3ef94daa | 3727 | |
6c085a72 CW |
3728 | /* if the object is no longer attached, discard its backing storage */ |
3729 | if (i915_gem_object_is_purgeable(obj) && obj->pages == NULL) | |
2d7ef395 CW |
3730 | i915_gem_object_truncate(obj); |
3731 | ||
05394f39 | 3732 | args->retained = obj->madv != __I915_MADV_PURGED; |
bb6baf76 | 3733 | |
1d7cfea1 | 3734 | out: |
05394f39 | 3735 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 3736 | unlock: |
3ef94daa | 3737 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 3738 | return ret; |
3ef94daa CW |
3739 | } |
3740 | ||
37e680a1 CW |
3741 | void i915_gem_object_init(struct drm_i915_gem_object *obj, |
3742 | const struct drm_i915_gem_object_ops *ops) | |
0327d6ba | 3743 | { |
0327d6ba CW |
3744 | INIT_LIST_HEAD(&obj->mm_list); |
3745 | INIT_LIST_HEAD(&obj->gtt_list); | |
3746 | INIT_LIST_HEAD(&obj->ring_list); | |
3747 | INIT_LIST_HEAD(&obj->exec_list); | |
3748 | ||
37e680a1 CW |
3749 | obj->ops = ops; |
3750 | ||
0327d6ba CW |
3751 | obj->fence_reg = I915_FENCE_REG_NONE; |
3752 | obj->madv = I915_MADV_WILLNEED; | |
3753 | /* Avoid an unnecessary call to unbind on the first bind. */ | |
3754 | obj->map_and_fenceable = true; | |
3755 | ||
3756 | i915_gem_info_add_obj(obj->base.dev->dev_private, obj->base.size); | |
3757 | } | |
3758 | ||
37e680a1 CW |
3759 | static const struct drm_i915_gem_object_ops i915_gem_object_ops = { |
3760 | .get_pages = i915_gem_object_get_pages_gtt, | |
3761 | .put_pages = i915_gem_object_put_pages_gtt, | |
3762 | }; | |
3763 | ||
05394f39 CW |
3764 | struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev, |
3765 | size_t size) | |
ac52bc56 | 3766 | { |
c397b908 | 3767 | struct drm_i915_gem_object *obj; |
5949eac4 | 3768 | struct address_space *mapping; |
1a240d4d | 3769 | gfp_t mask; |
ac52bc56 | 3770 | |
42dcedd4 | 3771 | obj = i915_gem_object_alloc(dev); |
c397b908 DV |
3772 | if (obj == NULL) |
3773 | return NULL; | |
673a394b | 3774 | |
c397b908 | 3775 | if (drm_gem_object_init(dev, &obj->base, size) != 0) { |
42dcedd4 | 3776 | i915_gem_object_free(obj); |
c397b908 DV |
3777 | return NULL; |
3778 | } | |
673a394b | 3779 | |
bed1ea95 CW |
3780 | mask = GFP_HIGHUSER | __GFP_RECLAIMABLE; |
3781 | if (IS_CRESTLINE(dev) || IS_BROADWATER(dev)) { | |
3782 | /* 965gm cannot relocate objects above 4GiB. */ | |
3783 | mask &= ~__GFP_HIGHMEM; | |
3784 | mask |= __GFP_DMA32; | |
3785 | } | |
3786 | ||
496ad9aa | 3787 | mapping = file_inode(obj->base.filp)->i_mapping; |
bed1ea95 | 3788 | mapping_set_gfp_mask(mapping, mask); |
5949eac4 | 3789 | |
37e680a1 | 3790 | i915_gem_object_init(obj, &i915_gem_object_ops); |
73aa808f | 3791 | |
c397b908 DV |
3792 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; |
3793 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; | |
673a394b | 3794 | |
3d29b842 ED |
3795 | if (HAS_LLC(dev)) { |
3796 | /* On some devices, we can have the GPU use the LLC (the CPU | |
a1871112 EA |
3797 | * cache) for about a 10% performance improvement |
3798 | * compared to uncached. Graphics requests other than | |
3799 | * display scanout are coherent with the CPU in | |
3800 | * accessing this cache. This means in this mode we | |
3801 | * don't need to clflush on the CPU side, and on the | |
3802 | * GPU side we only need to flush internal caches to | |
3803 | * get data visible to the CPU. | |
3804 | * | |
3805 | * However, we maintain the display planes as UC, and so | |
3806 | * need to rebind when first used as such. | |
3807 | */ | |
3808 | obj->cache_level = I915_CACHE_LLC; | |
3809 | } else | |
3810 | obj->cache_level = I915_CACHE_NONE; | |
3811 | ||
05394f39 | 3812 | return obj; |
c397b908 DV |
3813 | } |
3814 | ||
3815 | int i915_gem_init_object(struct drm_gem_object *obj) | |
3816 | { | |
3817 | BUG(); | |
de151cf6 | 3818 | |
673a394b EA |
3819 | return 0; |
3820 | } | |
3821 | ||
1488fc08 | 3822 | void i915_gem_free_object(struct drm_gem_object *gem_obj) |
673a394b | 3823 | { |
1488fc08 | 3824 | struct drm_i915_gem_object *obj = to_intel_bo(gem_obj); |
05394f39 | 3825 | struct drm_device *dev = obj->base.dev; |
be72615b | 3826 | drm_i915_private_t *dev_priv = dev->dev_private; |
673a394b | 3827 | |
26e12f89 CW |
3828 | trace_i915_gem_object_destroy(obj); |
3829 | ||
1488fc08 CW |
3830 | if (obj->phys_obj) |
3831 | i915_gem_detach_phys_object(dev, obj); | |
3832 | ||
3833 | obj->pin_count = 0; | |
3834 | if (WARN_ON(i915_gem_object_unbind(obj) == -ERESTARTSYS)) { | |
3835 | bool was_interruptible; | |
3836 | ||
3837 | was_interruptible = dev_priv->mm.interruptible; | |
3838 | dev_priv->mm.interruptible = false; | |
3839 | ||
3840 | WARN_ON(i915_gem_object_unbind(obj)); | |
3841 | ||
3842 | dev_priv->mm.interruptible = was_interruptible; | |
3843 | } | |
3844 | ||
a5570178 | 3845 | obj->pages_pin_count = 0; |
37e680a1 | 3846 | i915_gem_object_put_pages(obj); |
d8cb5086 | 3847 | i915_gem_object_free_mmap_offset(obj); |
0104fdbb | 3848 | i915_gem_object_release_stolen(obj); |
de151cf6 | 3849 | |
9da3da66 CW |
3850 | BUG_ON(obj->pages); |
3851 | ||
2f745ad3 CW |
3852 | if (obj->base.import_attach) |
3853 | drm_prime_gem_destroy(&obj->base, NULL); | |
de151cf6 | 3854 | |
05394f39 CW |
3855 | drm_gem_object_release(&obj->base); |
3856 | i915_gem_info_remove_obj(dev_priv, obj->base.size); | |
c397b908 | 3857 | |
05394f39 | 3858 | kfree(obj->bit_17); |
42dcedd4 | 3859 | i915_gem_object_free(obj); |
673a394b EA |
3860 | } |
3861 | ||
29105ccc CW |
3862 | int |
3863 | i915_gem_idle(struct drm_device *dev) | |
3864 | { | |
3865 | drm_i915_private_t *dev_priv = dev->dev_private; | |
3866 | int ret; | |
28dfe52a | 3867 | |
29105ccc | 3868 | mutex_lock(&dev->struct_mutex); |
1c5d22f7 | 3869 | |
87acb0a5 | 3870 | if (dev_priv->mm.suspended) { |
29105ccc CW |
3871 | mutex_unlock(&dev->struct_mutex); |
3872 | return 0; | |
28dfe52a EA |
3873 | } |
3874 | ||
b2da9fe5 | 3875 | ret = i915_gpu_idle(dev); |
6dbe2772 KP |
3876 | if (ret) { |
3877 | mutex_unlock(&dev->struct_mutex); | |
673a394b | 3878 | return ret; |
6dbe2772 | 3879 | } |
b2da9fe5 | 3880 | i915_gem_retire_requests(dev); |
673a394b | 3881 | |
29105ccc | 3882 | /* Under UMS, be paranoid and evict. */ |
a39d7efc | 3883 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) |
6c085a72 | 3884 | i915_gem_evict_everything(dev); |
29105ccc | 3885 | |
312817a3 CW |
3886 | i915_gem_reset_fences(dev); |
3887 | ||
29105ccc CW |
3888 | /* Hack! Don't let anybody do execbuf while we don't control the chip. |
3889 | * We need to replace this with a semaphore, or something. | |
3890 | * And not confound mm.suspended! | |
3891 | */ | |
3892 | dev_priv->mm.suspended = 1; | |
99584db3 | 3893 | del_timer_sync(&dev_priv->gpu_error.hangcheck_timer); |
29105ccc CW |
3894 | |
3895 | i915_kernel_lost_context(dev); | |
6dbe2772 | 3896 | i915_gem_cleanup_ringbuffer(dev); |
29105ccc | 3897 | |
6dbe2772 KP |
3898 | mutex_unlock(&dev->struct_mutex); |
3899 | ||
29105ccc CW |
3900 | /* Cancel the retire work handler, which should be idle now. */ |
3901 | cancel_delayed_work_sync(&dev_priv->mm.retire_work); | |
3902 | ||
673a394b EA |
3903 | return 0; |
3904 | } | |
3905 | ||
b9524a1e BW |
3906 | void i915_gem_l3_remap(struct drm_device *dev) |
3907 | { | |
3908 | drm_i915_private_t *dev_priv = dev->dev_private; | |
3909 | u32 misccpctl; | |
3910 | int i; | |
3911 | ||
eb32e458 | 3912 | if (!HAS_L3_GPU_CACHE(dev)) |
b9524a1e BW |
3913 | return; |
3914 | ||
a4da4fa4 | 3915 | if (!dev_priv->l3_parity.remap_info) |
b9524a1e BW |
3916 | return; |
3917 | ||
3918 | misccpctl = I915_READ(GEN7_MISCCPCTL); | |
3919 | I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE); | |
3920 | POSTING_READ(GEN7_MISCCPCTL); | |
3921 | ||
3922 | for (i = 0; i < GEN7_L3LOG_SIZE; i += 4) { | |
3923 | u32 remap = I915_READ(GEN7_L3LOG_BASE + i); | |
a4da4fa4 | 3924 | if (remap && remap != dev_priv->l3_parity.remap_info[i/4]) |
b9524a1e BW |
3925 | DRM_DEBUG("0x%x was already programmed to %x\n", |
3926 | GEN7_L3LOG_BASE + i, remap); | |
a4da4fa4 | 3927 | if (remap && !dev_priv->l3_parity.remap_info[i/4]) |
b9524a1e | 3928 | DRM_DEBUG_DRIVER("Clearing remapped register\n"); |
a4da4fa4 | 3929 | I915_WRITE(GEN7_L3LOG_BASE + i, dev_priv->l3_parity.remap_info[i/4]); |
b9524a1e BW |
3930 | } |
3931 | ||
3932 | /* Make sure all the writes land before disabling dop clock gating */ | |
3933 | POSTING_READ(GEN7_L3LOG_BASE); | |
3934 | ||
3935 | I915_WRITE(GEN7_MISCCPCTL, misccpctl); | |
3936 | } | |
3937 | ||
f691e2f4 DV |
3938 | void i915_gem_init_swizzling(struct drm_device *dev) |
3939 | { | |
3940 | drm_i915_private_t *dev_priv = dev->dev_private; | |
3941 | ||
11782b02 | 3942 | if (INTEL_INFO(dev)->gen < 5 || |
f691e2f4 DV |
3943 | dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE) |
3944 | return; | |
3945 | ||
3946 | I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) | | |
3947 | DISP_TILE_SURFACE_SWIZZLING); | |
3948 | ||
11782b02 DV |
3949 | if (IS_GEN5(dev)) |
3950 | return; | |
3951 | ||
f691e2f4 DV |
3952 | I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_SWZCTL); |
3953 | if (IS_GEN6(dev)) | |
6b26c86d | 3954 | I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB)); |
8782e26c | 3955 | else if (IS_GEN7(dev)) |
6b26c86d | 3956 | I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB)); |
8782e26c BW |
3957 | else |
3958 | BUG(); | |
f691e2f4 | 3959 | } |
e21af88d | 3960 | |
67b1b571 CW |
3961 | static bool |
3962 | intel_enable_blt(struct drm_device *dev) | |
3963 | { | |
3964 | if (!HAS_BLT(dev)) | |
3965 | return false; | |
3966 | ||
3967 | /* The blitter was dysfunctional on early prototypes */ | |
3968 | if (IS_GEN6(dev) && dev->pdev->revision < 8) { | |
3969 | DRM_INFO("BLT not supported on this pre-production hardware;" | |
3970 | " graphics performance will be degraded.\n"); | |
3971 | return false; | |
3972 | } | |
3973 | ||
3974 | return true; | |
3975 | } | |
3976 | ||
4fc7c971 | 3977 | static int i915_gem_init_rings(struct drm_device *dev) |
8187a2b7 | 3978 | { |
4fc7c971 | 3979 | struct drm_i915_private *dev_priv = dev->dev_private; |
8187a2b7 | 3980 | int ret; |
68f95ba9 | 3981 | |
5c1143bb | 3982 | ret = intel_init_render_ring_buffer(dev); |
68f95ba9 | 3983 | if (ret) |
b6913e4b | 3984 | return ret; |
68f95ba9 CW |
3985 | |
3986 | if (HAS_BSD(dev)) { | |
5c1143bb | 3987 | ret = intel_init_bsd_ring_buffer(dev); |
68f95ba9 CW |
3988 | if (ret) |
3989 | goto cleanup_render_ring; | |
d1b851fc | 3990 | } |
68f95ba9 | 3991 | |
67b1b571 | 3992 | if (intel_enable_blt(dev)) { |
549f7365 CW |
3993 | ret = intel_init_blt_ring_buffer(dev); |
3994 | if (ret) | |
3995 | goto cleanup_bsd_ring; | |
3996 | } | |
3997 | ||
99433931 | 3998 | ret = i915_gem_set_seqno(dev, ((u32)~0 - 0x1000)); |
4fc7c971 BW |
3999 | if (ret) |
4000 | goto cleanup_blt_ring; | |
4001 | ||
4002 | return 0; | |
4003 | ||
4004 | cleanup_blt_ring: | |
4005 | intel_cleanup_ring_buffer(&dev_priv->ring[BCS]); | |
4006 | cleanup_bsd_ring: | |
4007 | intel_cleanup_ring_buffer(&dev_priv->ring[VCS]); | |
4008 | cleanup_render_ring: | |
4009 | intel_cleanup_ring_buffer(&dev_priv->ring[RCS]); | |
4010 | ||
4011 | return ret; | |
4012 | } | |
4013 | ||
4014 | int | |
4015 | i915_gem_init_hw(struct drm_device *dev) | |
4016 | { | |
4017 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4018 | int ret; | |
4019 | ||
4020 | if (INTEL_INFO(dev)->gen < 6 && !intel_enable_gtt()) | |
4021 | return -EIO; | |
4022 | ||
4023 | if (IS_HASWELL(dev) && (I915_READ(0x120010) == 1)) | |
4024 | I915_WRITE(0x9008, I915_READ(0x9008) | 0xf0000); | |
4025 | ||
88a2b2a3 BW |
4026 | if (HAS_PCH_NOP(dev)) { |
4027 | u32 temp = I915_READ(GEN7_MSG_CTL); | |
4028 | temp &= ~(WAIT_FOR_PCH_FLR_ACK | WAIT_FOR_PCH_RESET_ACK); | |
4029 | I915_WRITE(GEN7_MSG_CTL, temp); | |
4030 | } | |
4031 | ||
4fc7c971 BW |
4032 | i915_gem_l3_remap(dev); |
4033 | ||
4034 | i915_gem_init_swizzling(dev); | |
4035 | ||
4036 | ret = i915_gem_init_rings(dev); | |
99433931 MK |
4037 | if (ret) |
4038 | return ret; | |
4039 | ||
254f965c BW |
4040 | /* |
4041 | * XXX: There was some w/a described somewhere suggesting loading | |
4042 | * contexts before PPGTT. | |
4043 | */ | |
4044 | i915_gem_context_init(dev); | |
b7c36d25 BW |
4045 | if (dev_priv->mm.aliasing_ppgtt) { |
4046 | ret = dev_priv->mm.aliasing_ppgtt->enable(dev); | |
4047 | if (ret) { | |
4048 | i915_gem_cleanup_aliasing_ppgtt(dev); | |
4049 | DRM_INFO("PPGTT enable failed. This is not fatal, but unexpected\n"); | |
4050 | } | |
4051 | } | |
e21af88d | 4052 | |
68f95ba9 | 4053 | return 0; |
8187a2b7 ZN |
4054 | } |
4055 | ||
1070a42b CW |
4056 | int i915_gem_init(struct drm_device *dev) |
4057 | { | |
4058 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1070a42b CW |
4059 | int ret; |
4060 | ||
1070a42b | 4061 | mutex_lock(&dev->struct_mutex); |
d62b4892 JB |
4062 | |
4063 | if (IS_VALLEYVIEW(dev)) { | |
4064 | /* VLVA0 (potential hack), BIOS isn't actually waking us */ | |
4065 | I915_WRITE(VLV_GTLC_WAKE_CTRL, 1); | |
4066 | if (wait_for((I915_READ(VLV_GTLC_PW_STATUS) & 1) == 1, 10)) | |
4067 | DRM_DEBUG_DRIVER("allow wake ack timed out\n"); | |
4068 | } | |
4069 | ||
d7e5008f | 4070 | i915_gem_init_global_gtt(dev); |
d62b4892 | 4071 | |
1070a42b CW |
4072 | ret = i915_gem_init_hw(dev); |
4073 | mutex_unlock(&dev->struct_mutex); | |
4074 | if (ret) { | |
4075 | i915_gem_cleanup_aliasing_ppgtt(dev); | |
4076 | return ret; | |
4077 | } | |
4078 | ||
53ca26ca DV |
4079 | /* Allow hardware batchbuffers unless told otherwise, but not for KMS. */ |
4080 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) | |
4081 | dev_priv->dri1.allow_batchbuffer = 1; | |
1070a42b CW |
4082 | return 0; |
4083 | } | |
4084 | ||
8187a2b7 ZN |
4085 | void |
4086 | i915_gem_cleanup_ringbuffer(struct drm_device *dev) | |
4087 | { | |
4088 | drm_i915_private_t *dev_priv = dev->dev_private; | |
b4519513 | 4089 | struct intel_ring_buffer *ring; |
1ec14ad3 | 4090 | int i; |
8187a2b7 | 4091 | |
b4519513 CW |
4092 | for_each_ring(ring, dev_priv, i) |
4093 | intel_cleanup_ring_buffer(ring); | |
8187a2b7 ZN |
4094 | } |
4095 | ||
673a394b EA |
4096 | int |
4097 | i915_gem_entervt_ioctl(struct drm_device *dev, void *data, | |
4098 | struct drm_file *file_priv) | |
4099 | { | |
4100 | drm_i915_private_t *dev_priv = dev->dev_private; | |
b4519513 | 4101 | int ret; |
673a394b | 4102 | |
79e53945 JB |
4103 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
4104 | return 0; | |
4105 | ||
1f83fee0 | 4106 | if (i915_reset_in_progress(&dev_priv->gpu_error)) { |
673a394b | 4107 | DRM_ERROR("Reenabling wedged hardware, good luck\n"); |
1f83fee0 | 4108 | atomic_set(&dev_priv->gpu_error.reset_counter, 0); |
673a394b EA |
4109 | } |
4110 | ||
673a394b | 4111 | mutex_lock(&dev->struct_mutex); |
9bb2d6f9 EA |
4112 | dev_priv->mm.suspended = 0; |
4113 | ||
f691e2f4 | 4114 | ret = i915_gem_init_hw(dev); |
d816f6ac WF |
4115 | if (ret != 0) { |
4116 | mutex_unlock(&dev->struct_mutex); | |
9bb2d6f9 | 4117 | return ret; |
d816f6ac | 4118 | } |
9bb2d6f9 | 4119 | |
69dc4987 | 4120 | BUG_ON(!list_empty(&dev_priv->mm.active_list)); |
673a394b | 4121 | mutex_unlock(&dev->struct_mutex); |
dbb19d30 | 4122 | |
5f35308b CW |
4123 | ret = drm_irq_install(dev); |
4124 | if (ret) | |
4125 | goto cleanup_ringbuffer; | |
dbb19d30 | 4126 | |
673a394b | 4127 | return 0; |
5f35308b CW |
4128 | |
4129 | cleanup_ringbuffer: | |
4130 | mutex_lock(&dev->struct_mutex); | |
4131 | i915_gem_cleanup_ringbuffer(dev); | |
4132 | dev_priv->mm.suspended = 1; | |
4133 | mutex_unlock(&dev->struct_mutex); | |
4134 | ||
4135 | return ret; | |
673a394b EA |
4136 | } |
4137 | ||
4138 | int | |
4139 | i915_gem_leavevt_ioctl(struct drm_device *dev, void *data, | |
4140 | struct drm_file *file_priv) | |
4141 | { | |
79e53945 JB |
4142 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
4143 | return 0; | |
4144 | ||
dbb19d30 | 4145 | drm_irq_uninstall(dev); |
e6890f6f | 4146 | return i915_gem_idle(dev); |
673a394b EA |
4147 | } |
4148 | ||
4149 | void | |
4150 | i915_gem_lastclose(struct drm_device *dev) | |
4151 | { | |
4152 | int ret; | |
673a394b | 4153 | |
e806b495 EA |
4154 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
4155 | return; | |
4156 | ||
6dbe2772 KP |
4157 | ret = i915_gem_idle(dev); |
4158 | if (ret) | |
4159 | DRM_ERROR("failed to idle hardware: %d\n", ret); | |
673a394b EA |
4160 | } |
4161 | ||
64193406 CW |
4162 | static void |
4163 | init_ring_lists(struct intel_ring_buffer *ring) | |
4164 | { | |
4165 | INIT_LIST_HEAD(&ring->active_list); | |
4166 | INIT_LIST_HEAD(&ring->request_list); | |
64193406 CW |
4167 | } |
4168 | ||
673a394b EA |
4169 | void |
4170 | i915_gem_load(struct drm_device *dev) | |
4171 | { | |
4172 | drm_i915_private_t *dev_priv = dev->dev_private; | |
42dcedd4 CW |
4173 | int i; |
4174 | ||
4175 | dev_priv->slab = | |
4176 | kmem_cache_create("i915_gem_object", | |
4177 | sizeof(struct drm_i915_gem_object), 0, | |
4178 | SLAB_HWCACHE_ALIGN, | |
4179 | NULL); | |
673a394b | 4180 | |
69dc4987 | 4181 | INIT_LIST_HEAD(&dev_priv->mm.active_list); |
673a394b | 4182 | INIT_LIST_HEAD(&dev_priv->mm.inactive_list); |
6c085a72 CW |
4183 | INIT_LIST_HEAD(&dev_priv->mm.unbound_list); |
4184 | INIT_LIST_HEAD(&dev_priv->mm.bound_list); | |
a09ba7fa | 4185 | INIT_LIST_HEAD(&dev_priv->mm.fence_list); |
1ec14ad3 CW |
4186 | for (i = 0; i < I915_NUM_RINGS; i++) |
4187 | init_ring_lists(&dev_priv->ring[i]); | |
4b9de737 | 4188 | for (i = 0; i < I915_MAX_NUM_FENCES; i++) |
007cc8ac | 4189 | INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list); |
673a394b EA |
4190 | INIT_DELAYED_WORK(&dev_priv->mm.retire_work, |
4191 | i915_gem_retire_work_handler); | |
1f83fee0 | 4192 | init_waitqueue_head(&dev_priv->gpu_error.reset_queue); |
31169714 | 4193 | |
94400120 DA |
4194 | /* On GEN3 we really need to make sure the ARB C3 LP bit is set */ |
4195 | if (IS_GEN3(dev)) { | |
50743298 DV |
4196 | I915_WRITE(MI_ARB_STATE, |
4197 | _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE)); | |
94400120 DA |
4198 | } |
4199 | ||
72bfa19c CW |
4200 | dev_priv->relative_constants_mode = I915_EXEC_CONSTANTS_REL_GENERAL; |
4201 | ||
de151cf6 | 4202 | /* Old X drivers will take 0-2 for front, back, depth buffers */ |
b397c836 EA |
4203 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) |
4204 | dev_priv->fence_reg_start = 3; | |
de151cf6 | 4205 | |
42b5aeab VS |
4206 | if (INTEL_INFO(dev)->gen >= 7 && !IS_VALLEYVIEW(dev)) |
4207 | dev_priv->num_fence_regs = 32; | |
4208 | else if (INTEL_INFO(dev)->gen >= 4 || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) | |
de151cf6 JB |
4209 | dev_priv->num_fence_regs = 16; |
4210 | else | |
4211 | dev_priv->num_fence_regs = 8; | |
4212 | ||
b5aa8a0f | 4213 | /* Initialize fence registers to zero */ |
ada726c7 | 4214 | i915_gem_reset_fences(dev); |
10ed13e4 | 4215 | |
673a394b | 4216 | i915_gem_detect_bit_6_swizzle(dev); |
6b95a207 | 4217 | init_waitqueue_head(&dev_priv->pending_flip_queue); |
17250b71 | 4218 | |
ce453d81 CW |
4219 | dev_priv->mm.interruptible = true; |
4220 | ||
17250b71 CW |
4221 | dev_priv->mm.inactive_shrinker.shrink = i915_gem_inactive_shrink; |
4222 | dev_priv->mm.inactive_shrinker.seeks = DEFAULT_SEEKS; | |
4223 | register_shrinker(&dev_priv->mm.inactive_shrinker); | |
673a394b | 4224 | } |
71acb5eb DA |
4225 | |
4226 | /* | |
4227 | * Create a physically contiguous memory object for this object | |
4228 | * e.g. for cursor + overlay regs | |
4229 | */ | |
995b6762 CW |
4230 | static int i915_gem_init_phys_object(struct drm_device *dev, |
4231 | int id, int size, int align) | |
71acb5eb DA |
4232 | { |
4233 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4234 | struct drm_i915_gem_phys_object *phys_obj; | |
4235 | int ret; | |
4236 | ||
4237 | if (dev_priv->mm.phys_objs[id - 1] || !size) | |
4238 | return 0; | |
4239 | ||
9a298b2a | 4240 | phys_obj = kzalloc(sizeof(struct drm_i915_gem_phys_object), GFP_KERNEL); |
71acb5eb DA |
4241 | if (!phys_obj) |
4242 | return -ENOMEM; | |
4243 | ||
4244 | phys_obj->id = id; | |
4245 | ||
6eeefaf3 | 4246 | phys_obj->handle = drm_pci_alloc(dev, size, align); |
71acb5eb DA |
4247 | if (!phys_obj->handle) { |
4248 | ret = -ENOMEM; | |
4249 | goto kfree_obj; | |
4250 | } | |
4251 | #ifdef CONFIG_X86 | |
4252 | set_memory_wc((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE); | |
4253 | #endif | |
4254 | ||
4255 | dev_priv->mm.phys_objs[id - 1] = phys_obj; | |
4256 | ||
4257 | return 0; | |
4258 | kfree_obj: | |
9a298b2a | 4259 | kfree(phys_obj); |
71acb5eb DA |
4260 | return ret; |
4261 | } | |
4262 | ||
995b6762 | 4263 | static void i915_gem_free_phys_object(struct drm_device *dev, int id) |
71acb5eb DA |
4264 | { |
4265 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4266 | struct drm_i915_gem_phys_object *phys_obj; | |
4267 | ||
4268 | if (!dev_priv->mm.phys_objs[id - 1]) | |
4269 | return; | |
4270 | ||
4271 | phys_obj = dev_priv->mm.phys_objs[id - 1]; | |
4272 | if (phys_obj->cur_obj) { | |
4273 | i915_gem_detach_phys_object(dev, phys_obj->cur_obj); | |
4274 | } | |
4275 | ||
4276 | #ifdef CONFIG_X86 | |
4277 | set_memory_wb((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE); | |
4278 | #endif | |
4279 | drm_pci_free(dev, phys_obj->handle); | |
4280 | kfree(phys_obj); | |
4281 | dev_priv->mm.phys_objs[id - 1] = NULL; | |
4282 | } | |
4283 | ||
4284 | void i915_gem_free_all_phys_object(struct drm_device *dev) | |
4285 | { | |
4286 | int i; | |
4287 | ||
260883c8 | 4288 | for (i = I915_GEM_PHYS_CURSOR_0; i <= I915_MAX_PHYS_OBJECT; i++) |
71acb5eb DA |
4289 | i915_gem_free_phys_object(dev, i); |
4290 | } | |
4291 | ||
4292 | void i915_gem_detach_phys_object(struct drm_device *dev, | |
05394f39 | 4293 | struct drm_i915_gem_object *obj) |
71acb5eb | 4294 | { |
496ad9aa | 4295 | struct address_space *mapping = file_inode(obj->base.filp)->i_mapping; |
e5281ccd | 4296 | char *vaddr; |
71acb5eb | 4297 | int i; |
71acb5eb DA |
4298 | int page_count; |
4299 | ||
05394f39 | 4300 | if (!obj->phys_obj) |
71acb5eb | 4301 | return; |
05394f39 | 4302 | vaddr = obj->phys_obj->handle->vaddr; |
71acb5eb | 4303 | |
05394f39 | 4304 | page_count = obj->base.size / PAGE_SIZE; |
71acb5eb | 4305 | for (i = 0; i < page_count; i++) { |
5949eac4 | 4306 | struct page *page = shmem_read_mapping_page(mapping, i); |
e5281ccd CW |
4307 | if (!IS_ERR(page)) { |
4308 | char *dst = kmap_atomic(page); | |
4309 | memcpy(dst, vaddr + i*PAGE_SIZE, PAGE_SIZE); | |
4310 | kunmap_atomic(dst); | |
4311 | ||
4312 | drm_clflush_pages(&page, 1); | |
4313 | ||
4314 | set_page_dirty(page); | |
4315 | mark_page_accessed(page); | |
4316 | page_cache_release(page); | |
4317 | } | |
71acb5eb | 4318 | } |
e76e9aeb | 4319 | i915_gem_chipset_flush(dev); |
d78b47b9 | 4320 | |
05394f39 CW |
4321 | obj->phys_obj->cur_obj = NULL; |
4322 | obj->phys_obj = NULL; | |
71acb5eb DA |
4323 | } |
4324 | ||
4325 | int | |
4326 | i915_gem_attach_phys_object(struct drm_device *dev, | |
05394f39 | 4327 | struct drm_i915_gem_object *obj, |
6eeefaf3 CW |
4328 | int id, |
4329 | int align) | |
71acb5eb | 4330 | { |
496ad9aa | 4331 | struct address_space *mapping = file_inode(obj->base.filp)->i_mapping; |
71acb5eb | 4332 | drm_i915_private_t *dev_priv = dev->dev_private; |
71acb5eb DA |
4333 | int ret = 0; |
4334 | int page_count; | |
4335 | int i; | |
4336 | ||
4337 | if (id > I915_MAX_PHYS_OBJECT) | |
4338 | return -EINVAL; | |
4339 | ||
05394f39 CW |
4340 | if (obj->phys_obj) { |
4341 | if (obj->phys_obj->id == id) | |
71acb5eb DA |
4342 | return 0; |
4343 | i915_gem_detach_phys_object(dev, obj); | |
4344 | } | |
4345 | ||
71acb5eb DA |
4346 | /* create a new object */ |
4347 | if (!dev_priv->mm.phys_objs[id - 1]) { | |
4348 | ret = i915_gem_init_phys_object(dev, id, | |
05394f39 | 4349 | obj->base.size, align); |
71acb5eb | 4350 | if (ret) { |
05394f39 CW |
4351 | DRM_ERROR("failed to init phys object %d size: %zu\n", |
4352 | id, obj->base.size); | |
e5281ccd | 4353 | return ret; |
71acb5eb DA |
4354 | } |
4355 | } | |
4356 | ||
4357 | /* bind to the object */ | |
05394f39 CW |
4358 | obj->phys_obj = dev_priv->mm.phys_objs[id - 1]; |
4359 | obj->phys_obj->cur_obj = obj; | |
71acb5eb | 4360 | |
05394f39 | 4361 | page_count = obj->base.size / PAGE_SIZE; |
71acb5eb DA |
4362 | |
4363 | for (i = 0; i < page_count; i++) { | |
e5281ccd CW |
4364 | struct page *page; |
4365 | char *dst, *src; | |
4366 | ||
5949eac4 | 4367 | page = shmem_read_mapping_page(mapping, i); |
e5281ccd CW |
4368 | if (IS_ERR(page)) |
4369 | return PTR_ERR(page); | |
71acb5eb | 4370 | |
ff75b9bc | 4371 | src = kmap_atomic(page); |
05394f39 | 4372 | dst = obj->phys_obj->handle->vaddr + (i * PAGE_SIZE); |
71acb5eb | 4373 | memcpy(dst, src, PAGE_SIZE); |
3e4d3af5 | 4374 | kunmap_atomic(src); |
71acb5eb | 4375 | |
e5281ccd CW |
4376 | mark_page_accessed(page); |
4377 | page_cache_release(page); | |
4378 | } | |
d78b47b9 | 4379 | |
71acb5eb | 4380 | return 0; |
71acb5eb DA |
4381 | } |
4382 | ||
4383 | static int | |
05394f39 CW |
4384 | i915_gem_phys_pwrite(struct drm_device *dev, |
4385 | struct drm_i915_gem_object *obj, | |
71acb5eb DA |
4386 | struct drm_i915_gem_pwrite *args, |
4387 | struct drm_file *file_priv) | |
4388 | { | |
05394f39 | 4389 | void *vaddr = obj->phys_obj->handle->vaddr + args->offset; |
2bb4629a | 4390 | char __user *user_data = to_user_ptr(args->data_ptr); |
71acb5eb | 4391 | |
b47b30cc CW |
4392 | if (__copy_from_user_inatomic_nocache(vaddr, user_data, args->size)) { |
4393 | unsigned long unwritten; | |
4394 | ||
4395 | /* The physical object once assigned is fixed for the lifetime | |
4396 | * of the obj, so we can safely drop the lock and continue | |
4397 | * to access vaddr. | |
4398 | */ | |
4399 | mutex_unlock(&dev->struct_mutex); | |
4400 | unwritten = copy_from_user(vaddr, user_data, args->size); | |
4401 | mutex_lock(&dev->struct_mutex); | |
4402 | if (unwritten) | |
4403 | return -EFAULT; | |
4404 | } | |
71acb5eb | 4405 | |
e76e9aeb | 4406 | i915_gem_chipset_flush(dev); |
71acb5eb DA |
4407 | return 0; |
4408 | } | |
b962442e | 4409 | |
f787a5f5 | 4410 | void i915_gem_release(struct drm_device *dev, struct drm_file *file) |
b962442e | 4411 | { |
f787a5f5 | 4412 | struct drm_i915_file_private *file_priv = file->driver_priv; |
b962442e EA |
4413 | |
4414 | /* Clean up our request list when the client is going away, so that | |
4415 | * later retire_requests won't dereference our soon-to-be-gone | |
4416 | * file_priv. | |
4417 | */ | |
1c25595f | 4418 | spin_lock(&file_priv->mm.lock); |
f787a5f5 CW |
4419 | while (!list_empty(&file_priv->mm.request_list)) { |
4420 | struct drm_i915_gem_request *request; | |
4421 | ||
4422 | request = list_first_entry(&file_priv->mm.request_list, | |
4423 | struct drm_i915_gem_request, | |
4424 | client_list); | |
4425 | list_del(&request->client_list); | |
4426 | request->file_priv = NULL; | |
4427 | } | |
1c25595f | 4428 | spin_unlock(&file_priv->mm.lock); |
b962442e | 4429 | } |
31169714 | 4430 | |
5774506f CW |
4431 | static bool mutex_is_locked_by(struct mutex *mutex, struct task_struct *task) |
4432 | { | |
4433 | if (!mutex_is_locked(mutex)) | |
4434 | return false; | |
4435 | ||
4436 | #if defined(CONFIG_SMP) || defined(CONFIG_DEBUG_MUTEXES) | |
4437 | return mutex->owner == task; | |
4438 | #else | |
4439 | /* Since UP may be pre-empted, we cannot assume that we own the lock */ | |
4440 | return false; | |
4441 | #endif | |
4442 | } | |
4443 | ||
31169714 | 4444 | static int |
1495f230 | 4445 | i915_gem_inactive_shrink(struct shrinker *shrinker, struct shrink_control *sc) |
31169714 | 4446 | { |
17250b71 CW |
4447 | struct drm_i915_private *dev_priv = |
4448 | container_of(shrinker, | |
4449 | struct drm_i915_private, | |
4450 | mm.inactive_shrinker); | |
4451 | struct drm_device *dev = dev_priv->dev; | |
6c085a72 | 4452 | struct drm_i915_gem_object *obj; |
1495f230 | 4453 | int nr_to_scan = sc->nr_to_scan; |
5774506f | 4454 | bool unlock = true; |
17250b71 CW |
4455 | int cnt; |
4456 | ||
5774506f CW |
4457 | if (!mutex_trylock(&dev->struct_mutex)) { |
4458 | if (!mutex_is_locked_by(&dev->struct_mutex, current)) | |
4459 | return 0; | |
4460 | ||
677feac2 DV |
4461 | if (dev_priv->mm.shrinker_no_lock_stealing) |
4462 | return 0; | |
4463 | ||
5774506f CW |
4464 | unlock = false; |
4465 | } | |
31169714 | 4466 | |
6c085a72 CW |
4467 | if (nr_to_scan) { |
4468 | nr_to_scan -= i915_gem_purge(dev_priv, nr_to_scan); | |
93927ca5 DV |
4469 | if (nr_to_scan > 0) |
4470 | nr_to_scan -= __i915_gem_shrink(dev_priv, nr_to_scan, | |
4471 | false); | |
6c085a72 CW |
4472 | if (nr_to_scan > 0) |
4473 | i915_gem_shrink_all(dev_priv); | |
31169714 CW |
4474 | } |
4475 | ||
17250b71 | 4476 | cnt = 0; |
6c085a72 | 4477 | list_for_each_entry(obj, &dev_priv->mm.unbound_list, gtt_list) |
a5570178 CW |
4478 | if (obj->pages_pin_count == 0) |
4479 | cnt += obj->base.size >> PAGE_SHIFT; | |
93927ca5 | 4480 | list_for_each_entry(obj, &dev_priv->mm.inactive_list, gtt_list) |
a5570178 | 4481 | if (obj->pin_count == 0 && obj->pages_pin_count == 0) |
6c085a72 | 4482 | cnt += obj->base.size >> PAGE_SHIFT; |
17250b71 | 4483 | |
5774506f CW |
4484 | if (unlock) |
4485 | mutex_unlock(&dev->struct_mutex); | |
6c085a72 | 4486 | return cnt; |
31169714 | 4487 | } |