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Commit | Line | Data |
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673a394b EA |
1 | /* |
2 | * Copyright © 2008 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | * | |
26 | */ | |
27 | ||
28 | #include "drmP.h" | |
29 | #include "drm.h" | |
30 | #include "i915_drm.h" | |
31 | #include "i915_drv.h" | |
1c5d22f7 | 32 | #include "i915_trace.h" |
652c393a | 33 | #include "intel_drv.h" |
5949eac4 | 34 | #include <linux/shmem_fs.h> |
5a0e3ad6 | 35 | #include <linux/slab.h> |
673a394b | 36 | #include <linux/swap.h> |
79e53945 | 37 | #include <linux/pci.h> |
673a394b | 38 | |
88241785 | 39 | static __must_check int i915_gem_object_flush_gpu_write_domain(struct drm_i915_gem_object *obj); |
05394f39 CW |
40 | static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj); |
41 | static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj); | |
88241785 CW |
42 | static __must_check int i915_gem_object_set_cpu_read_domain_range(struct drm_i915_gem_object *obj, |
43 | uint64_t offset, | |
44 | uint64_t size); | |
05394f39 | 45 | static void i915_gem_object_set_to_full_cpu_read_domain(struct drm_i915_gem_object *obj); |
88241785 CW |
46 | static __must_check int i915_gem_object_bind_to_gtt(struct drm_i915_gem_object *obj, |
47 | unsigned alignment, | |
48 | bool map_and_fenceable); | |
d9e86c0e CW |
49 | static void i915_gem_clear_fence_reg(struct drm_device *dev, |
50 | struct drm_i915_fence_reg *reg); | |
05394f39 CW |
51 | static int i915_gem_phys_pwrite(struct drm_device *dev, |
52 | struct drm_i915_gem_object *obj, | |
71acb5eb | 53 | struct drm_i915_gem_pwrite *args, |
05394f39 CW |
54 | struct drm_file *file); |
55 | static void i915_gem_free_object_tail(struct drm_i915_gem_object *obj); | |
673a394b | 56 | |
17250b71 | 57 | static int i915_gem_inactive_shrink(struct shrinker *shrinker, |
1495f230 | 58 | struct shrink_control *sc); |
8c59967c | 59 | static void i915_gem_object_truncate(struct drm_i915_gem_object *obj); |
31169714 | 60 | |
73aa808f CW |
61 | /* some bookkeeping */ |
62 | static void i915_gem_info_add_obj(struct drm_i915_private *dev_priv, | |
63 | size_t size) | |
64 | { | |
65 | dev_priv->mm.object_count++; | |
66 | dev_priv->mm.object_memory += size; | |
67 | } | |
68 | ||
69 | static void i915_gem_info_remove_obj(struct drm_i915_private *dev_priv, | |
70 | size_t size) | |
71 | { | |
72 | dev_priv->mm.object_count--; | |
73 | dev_priv->mm.object_memory -= size; | |
74 | } | |
75 | ||
21dd3734 CW |
76 | static int |
77 | i915_gem_wait_for_error(struct drm_device *dev) | |
30dbf0c0 CW |
78 | { |
79 | struct drm_i915_private *dev_priv = dev->dev_private; | |
80 | struct completion *x = &dev_priv->error_completion; | |
81 | unsigned long flags; | |
82 | int ret; | |
83 | ||
84 | if (!atomic_read(&dev_priv->mm.wedged)) | |
85 | return 0; | |
86 | ||
87 | ret = wait_for_completion_interruptible(x); | |
88 | if (ret) | |
89 | return ret; | |
90 | ||
21dd3734 CW |
91 | if (atomic_read(&dev_priv->mm.wedged)) { |
92 | /* GPU is hung, bump the completion count to account for | |
93 | * the token we just consumed so that we never hit zero and | |
94 | * end up waiting upon a subsequent completion event that | |
95 | * will never happen. | |
96 | */ | |
97 | spin_lock_irqsave(&x->wait.lock, flags); | |
98 | x->done++; | |
99 | spin_unlock_irqrestore(&x->wait.lock, flags); | |
100 | } | |
101 | return 0; | |
30dbf0c0 CW |
102 | } |
103 | ||
54cf91dc | 104 | int i915_mutex_lock_interruptible(struct drm_device *dev) |
76c1dec1 | 105 | { |
76c1dec1 CW |
106 | int ret; |
107 | ||
21dd3734 | 108 | ret = i915_gem_wait_for_error(dev); |
76c1dec1 CW |
109 | if (ret) |
110 | return ret; | |
111 | ||
112 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
113 | if (ret) | |
114 | return ret; | |
115 | ||
23bc5982 | 116 | WARN_ON(i915_verify_lists(dev)); |
76c1dec1 CW |
117 | return 0; |
118 | } | |
30dbf0c0 | 119 | |
7d1c4804 | 120 | static inline bool |
05394f39 | 121 | i915_gem_object_is_inactive(struct drm_i915_gem_object *obj) |
7d1c4804 | 122 | { |
05394f39 | 123 | return obj->gtt_space && !obj->active && obj->pin_count == 0; |
7d1c4804 CW |
124 | } |
125 | ||
79e53945 JB |
126 | int |
127 | i915_gem_init_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 128 | struct drm_file *file) |
79e53945 JB |
129 | { |
130 | struct drm_i915_gem_init *args = data; | |
2021746e CW |
131 | |
132 | if (args->gtt_start >= args->gtt_end || | |
133 | (args->gtt_end | args->gtt_start) & (PAGE_SIZE - 1)) | |
134 | return -EINVAL; | |
79e53945 JB |
135 | |
136 | mutex_lock(&dev->struct_mutex); | |
644ec02b DV |
137 | i915_gem_init_global_gtt(dev, args->gtt_start, |
138 | args->gtt_end, args->gtt_end); | |
673a394b EA |
139 | mutex_unlock(&dev->struct_mutex); |
140 | ||
2021746e | 141 | return 0; |
673a394b EA |
142 | } |
143 | ||
5a125c3c EA |
144 | int |
145 | i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 146 | struct drm_file *file) |
5a125c3c | 147 | { |
73aa808f | 148 | struct drm_i915_private *dev_priv = dev->dev_private; |
5a125c3c | 149 | struct drm_i915_gem_get_aperture *args = data; |
6299f992 CW |
150 | struct drm_i915_gem_object *obj; |
151 | size_t pinned; | |
5a125c3c EA |
152 | |
153 | if (!(dev->driver->driver_features & DRIVER_GEM)) | |
154 | return -ENODEV; | |
155 | ||
6299f992 | 156 | pinned = 0; |
73aa808f | 157 | mutex_lock(&dev->struct_mutex); |
6299f992 CW |
158 | list_for_each_entry(obj, &dev_priv->mm.pinned_list, mm_list) |
159 | pinned += obj->gtt_space->size; | |
73aa808f | 160 | mutex_unlock(&dev->struct_mutex); |
5a125c3c | 161 | |
6299f992 | 162 | args->aper_size = dev_priv->mm.gtt_total; |
0206e353 | 163 | args->aper_available_size = args->aper_size - pinned; |
6299f992 | 164 | |
5a125c3c EA |
165 | return 0; |
166 | } | |
167 | ||
ff72145b DA |
168 | static int |
169 | i915_gem_create(struct drm_file *file, | |
170 | struct drm_device *dev, | |
171 | uint64_t size, | |
172 | uint32_t *handle_p) | |
673a394b | 173 | { |
05394f39 | 174 | struct drm_i915_gem_object *obj; |
a1a2d1d3 PP |
175 | int ret; |
176 | u32 handle; | |
673a394b | 177 | |
ff72145b | 178 | size = roundup(size, PAGE_SIZE); |
8ffc0246 CW |
179 | if (size == 0) |
180 | return -EINVAL; | |
673a394b EA |
181 | |
182 | /* Allocate the new object */ | |
ff72145b | 183 | obj = i915_gem_alloc_object(dev, size); |
673a394b EA |
184 | if (obj == NULL) |
185 | return -ENOMEM; | |
186 | ||
05394f39 | 187 | ret = drm_gem_handle_create(file, &obj->base, &handle); |
1dfd9754 | 188 | if (ret) { |
05394f39 CW |
189 | drm_gem_object_release(&obj->base); |
190 | i915_gem_info_remove_obj(dev->dev_private, obj->base.size); | |
202f2fef | 191 | kfree(obj); |
673a394b | 192 | return ret; |
1dfd9754 | 193 | } |
673a394b | 194 | |
202f2fef | 195 | /* drop reference from allocate - handle holds it now */ |
05394f39 | 196 | drm_gem_object_unreference(&obj->base); |
202f2fef CW |
197 | trace_i915_gem_object_create(obj); |
198 | ||
ff72145b | 199 | *handle_p = handle; |
673a394b EA |
200 | return 0; |
201 | } | |
202 | ||
ff72145b DA |
203 | int |
204 | i915_gem_dumb_create(struct drm_file *file, | |
205 | struct drm_device *dev, | |
206 | struct drm_mode_create_dumb *args) | |
207 | { | |
208 | /* have to work out size/pitch and return them */ | |
ed0291fd | 209 | args->pitch = ALIGN(args->width * ((args->bpp + 7) / 8), 64); |
ff72145b DA |
210 | args->size = args->pitch * args->height; |
211 | return i915_gem_create(file, dev, | |
212 | args->size, &args->handle); | |
213 | } | |
214 | ||
215 | int i915_gem_dumb_destroy(struct drm_file *file, | |
216 | struct drm_device *dev, | |
217 | uint32_t handle) | |
218 | { | |
219 | return drm_gem_handle_delete(file, handle); | |
220 | } | |
221 | ||
222 | /** | |
223 | * Creates a new mm object and returns a handle to it. | |
224 | */ | |
225 | int | |
226 | i915_gem_create_ioctl(struct drm_device *dev, void *data, | |
227 | struct drm_file *file) | |
228 | { | |
229 | struct drm_i915_gem_create *args = data; | |
230 | return i915_gem_create(file, dev, | |
231 | args->size, &args->handle); | |
232 | } | |
233 | ||
05394f39 | 234 | static int i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj) |
280b713b | 235 | { |
05394f39 | 236 | drm_i915_private_t *dev_priv = obj->base.dev->dev_private; |
280b713b EA |
237 | |
238 | return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 && | |
05394f39 | 239 | obj->tiling_mode != I915_TILING_NONE; |
280b713b EA |
240 | } |
241 | ||
eb01459f EA |
242 | /** |
243 | * This is the fast shmem pread path, which attempts to copy_from_user directly | |
244 | * from the backing pages of the object to the user's address space. On a | |
245 | * fault, it fails so we can fall back to i915_gem_shmem_pwrite_slow(). | |
246 | */ | |
247 | static int | |
05394f39 CW |
248 | i915_gem_shmem_pread_fast(struct drm_device *dev, |
249 | struct drm_i915_gem_object *obj, | |
eb01459f | 250 | struct drm_i915_gem_pread *args, |
05394f39 | 251 | struct drm_file *file) |
eb01459f | 252 | { |
05394f39 | 253 | struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping; |
eb01459f | 254 | ssize_t remain; |
e5281ccd | 255 | loff_t offset; |
eb01459f EA |
256 | char __user *user_data; |
257 | int page_offset, page_length; | |
eb01459f EA |
258 | |
259 | user_data = (char __user *) (uintptr_t) args->data_ptr; | |
260 | remain = args->size; | |
261 | ||
eb01459f EA |
262 | offset = args->offset; |
263 | ||
264 | while (remain > 0) { | |
e5281ccd CW |
265 | struct page *page; |
266 | char *vaddr; | |
267 | int ret; | |
268 | ||
eb01459f EA |
269 | /* Operation in this page |
270 | * | |
eb01459f EA |
271 | * page_offset = offset within page |
272 | * page_length = bytes to copy for this page | |
273 | */ | |
c8cbbb8b | 274 | page_offset = offset_in_page(offset); |
eb01459f EA |
275 | page_length = remain; |
276 | if ((page_offset + remain) > PAGE_SIZE) | |
277 | page_length = PAGE_SIZE - page_offset; | |
278 | ||
5949eac4 | 279 | page = shmem_read_mapping_page(mapping, offset >> PAGE_SHIFT); |
e5281ccd CW |
280 | if (IS_ERR(page)) |
281 | return PTR_ERR(page); | |
282 | ||
283 | vaddr = kmap_atomic(page); | |
284 | ret = __copy_to_user_inatomic(user_data, | |
285 | vaddr + page_offset, | |
286 | page_length); | |
287 | kunmap_atomic(vaddr); | |
288 | ||
289 | mark_page_accessed(page); | |
290 | page_cache_release(page); | |
291 | if (ret) | |
4f27b75d | 292 | return -EFAULT; |
eb01459f EA |
293 | |
294 | remain -= page_length; | |
295 | user_data += page_length; | |
296 | offset += page_length; | |
297 | } | |
298 | ||
4f27b75d | 299 | return 0; |
eb01459f EA |
300 | } |
301 | ||
8461d226 DV |
302 | static inline int |
303 | __copy_to_user_swizzled(char __user *cpu_vaddr, | |
304 | const char *gpu_vaddr, int gpu_offset, | |
305 | int length) | |
306 | { | |
307 | int ret, cpu_offset = 0; | |
308 | ||
309 | while (length > 0) { | |
310 | int cacheline_end = ALIGN(gpu_offset + 1, 64); | |
311 | int this_length = min(cacheline_end - gpu_offset, length); | |
312 | int swizzled_gpu_offset = gpu_offset ^ 64; | |
313 | ||
314 | ret = __copy_to_user(cpu_vaddr + cpu_offset, | |
315 | gpu_vaddr + swizzled_gpu_offset, | |
316 | this_length); | |
317 | if (ret) | |
318 | return ret + length; | |
319 | ||
320 | cpu_offset += this_length; | |
321 | gpu_offset += this_length; | |
322 | length -= this_length; | |
323 | } | |
324 | ||
325 | return 0; | |
326 | } | |
327 | ||
8c59967c DV |
328 | static inline int |
329 | __copy_from_user_swizzled(char __user *gpu_vaddr, int gpu_offset, | |
330 | const char *cpu_vaddr, | |
331 | int length) | |
332 | { | |
333 | int ret, cpu_offset = 0; | |
334 | ||
335 | while (length > 0) { | |
336 | int cacheline_end = ALIGN(gpu_offset + 1, 64); | |
337 | int this_length = min(cacheline_end - gpu_offset, length); | |
338 | int swizzled_gpu_offset = gpu_offset ^ 64; | |
339 | ||
340 | ret = __copy_from_user(gpu_vaddr + swizzled_gpu_offset, | |
341 | cpu_vaddr + cpu_offset, | |
342 | this_length); | |
343 | if (ret) | |
344 | return ret + length; | |
345 | ||
346 | cpu_offset += this_length; | |
347 | gpu_offset += this_length; | |
348 | length -= this_length; | |
349 | } | |
350 | ||
351 | return 0; | |
352 | } | |
353 | ||
eb01459f EA |
354 | /** |
355 | * This is the fallback shmem pread path, which allocates temporary storage | |
356 | * in kernel space to copy_to_user into outside of the struct_mutex, so we | |
357 | * can copy out of the object's backing pages while holding the struct mutex | |
358 | * and not take page faults. | |
359 | */ | |
360 | static int | |
05394f39 CW |
361 | i915_gem_shmem_pread_slow(struct drm_device *dev, |
362 | struct drm_i915_gem_object *obj, | |
eb01459f | 363 | struct drm_i915_gem_pread *args, |
05394f39 | 364 | struct drm_file *file) |
eb01459f | 365 | { |
05394f39 | 366 | struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping; |
8461d226 | 367 | char __user *user_data; |
eb01459f | 368 | ssize_t remain; |
8461d226 | 369 | loff_t offset; |
eb2c0c81 | 370 | int shmem_page_offset, page_length, ret = 0; |
8461d226 | 371 | int obj_do_bit17_swizzling, page_do_bit17_swizzling; |
eb01459f | 372 | |
8461d226 | 373 | user_data = (char __user *) (uintptr_t) args->data_ptr; |
eb01459f EA |
374 | remain = args->size; |
375 | ||
8461d226 | 376 | obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj); |
eb01459f | 377 | |
8461d226 | 378 | offset = args->offset; |
eb01459f | 379 | |
4f27b75d | 380 | mutex_unlock(&dev->struct_mutex); |
eb01459f EA |
381 | |
382 | while (remain > 0) { | |
e5281ccd | 383 | struct page *page; |
8461d226 | 384 | char *vaddr; |
e5281ccd | 385 | |
eb01459f EA |
386 | /* Operation in this page |
387 | * | |
eb01459f | 388 | * shmem_page_offset = offset within page in shmem file |
eb01459f EA |
389 | * page_length = bytes to copy for this page |
390 | */ | |
c8cbbb8b | 391 | shmem_page_offset = offset_in_page(offset); |
eb01459f EA |
392 | page_length = remain; |
393 | if ((shmem_page_offset + page_length) > PAGE_SIZE) | |
394 | page_length = PAGE_SIZE - shmem_page_offset; | |
eb01459f | 395 | |
5949eac4 | 396 | page = shmem_read_mapping_page(mapping, offset >> PAGE_SHIFT); |
b65552f0 JJ |
397 | if (IS_ERR(page)) { |
398 | ret = PTR_ERR(page); | |
399 | goto out; | |
400 | } | |
e5281ccd | 401 | |
8461d226 DV |
402 | page_do_bit17_swizzling = obj_do_bit17_swizzling && |
403 | (page_to_phys(page) & (1 << 17)) != 0; | |
404 | ||
405 | vaddr = kmap(page); | |
406 | if (page_do_bit17_swizzling) | |
407 | ret = __copy_to_user_swizzled(user_data, | |
408 | vaddr, shmem_page_offset, | |
409 | page_length); | |
410 | else | |
411 | ret = __copy_to_user(user_data, | |
412 | vaddr + shmem_page_offset, | |
413 | page_length); | |
414 | kunmap(page); | |
eb01459f | 415 | |
e5281ccd CW |
416 | mark_page_accessed(page); |
417 | page_cache_release(page); | |
418 | ||
8461d226 DV |
419 | if (ret) { |
420 | ret = -EFAULT; | |
421 | goto out; | |
422 | } | |
423 | ||
eb01459f | 424 | remain -= page_length; |
8461d226 | 425 | user_data += page_length; |
eb01459f EA |
426 | offset += page_length; |
427 | } | |
428 | ||
4f27b75d | 429 | out: |
8461d226 DV |
430 | mutex_lock(&dev->struct_mutex); |
431 | /* Fixup: Kill any reinstated backing storage pages */ | |
432 | if (obj->madv == __I915_MADV_PURGED) | |
433 | i915_gem_object_truncate(obj); | |
eb01459f EA |
434 | |
435 | return ret; | |
436 | } | |
437 | ||
673a394b EA |
438 | /** |
439 | * Reads data from the object referenced by handle. | |
440 | * | |
441 | * On error, the contents of *data are undefined. | |
442 | */ | |
443 | int | |
444 | i915_gem_pread_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 445 | struct drm_file *file) |
673a394b EA |
446 | { |
447 | struct drm_i915_gem_pread *args = data; | |
05394f39 | 448 | struct drm_i915_gem_object *obj; |
35b62a89 | 449 | int ret = 0; |
673a394b | 450 | |
51311d0a CW |
451 | if (args->size == 0) |
452 | return 0; | |
453 | ||
454 | if (!access_ok(VERIFY_WRITE, | |
455 | (char __user *)(uintptr_t)args->data_ptr, | |
456 | args->size)) | |
457 | return -EFAULT; | |
458 | ||
459 | ret = fault_in_pages_writeable((char __user *)(uintptr_t)args->data_ptr, | |
460 | args->size); | |
461 | if (ret) | |
462 | return -EFAULT; | |
463 | ||
4f27b75d | 464 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 465 | if (ret) |
4f27b75d | 466 | return ret; |
673a394b | 467 | |
05394f39 | 468 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 469 | if (&obj->base == NULL) { |
1d7cfea1 CW |
470 | ret = -ENOENT; |
471 | goto unlock; | |
4f27b75d | 472 | } |
673a394b | 473 | |
7dcd2499 | 474 | /* Bounds check source. */ |
05394f39 CW |
475 | if (args->offset > obj->base.size || |
476 | args->size > obj->base.size - args->offset) { | |
ce9d419d | 477 | ret = -EINVAL; |
35b62a89 | 478 | goto out; |
ce9d419d CW |
479 | } |
480 | ||
db53a302 CW |
481 | trace_i915_gem_object_pread(obj, args->offset, args->size); |
482 | ||
4f27b75d CW |
483 | ret = i915_gem_object_set_cpu_read_domain_range(obj, |
484 | args->offset, | |
485 | args->size); | |
486 | if (ret) | |
e5281ccd | 487 | goto out; |
4f27b75d CW |
488 | |
489 | ret = -EFAULT; | |
490 | if (!i915_gem_object_needs_bit17_swizzle(obj)) | |
05394f39 | 491 | ret = i915_gem_shmem_pread_fast(dev, obj, args, file); |
4f27b75d | 492 | if (ret == -EFAULT) |
05394f39 | 493 | ret = i915_gem_shmem_pread_slow(dev, obj, args, file); |
673a394b | 494 | |
35b62a89 | 495 | out: |
05394f39 | 496 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 497 | unlock: |
4f27b75d | 498 | mutex_unlock(&dev->struct_mutex); |
eb01459f | 499 | return ret; |
673a394b EA |
500 | } |
501 | ||
0839ccb8 KP |
502 | /* This is the fast write path which cannot handle |
503 | * page faults in the source data | |
9b7530cc | 504 | */ |
0839ccb8 KP |
505 | |
506 | static inline int | |
507 | fast_user_write(struct io_mapping *mapping, | |
508 | loff_t page_base, int page_offset, | |
509 | char __user *user_data, | |
510 | int length) | |
9b7530cc | 511 | { |
9b7530cc | 512 | char *vaddr_atomic; |
0839ccb8 | 513 | unsigned long unwritten; |
9b7530cc | 514 | |
3e4d3af5 | 515 | vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base); |
0839ccb8 KP |
516 | unwritten = __copy_from_user_inatomic_nocache(vaddr_atomic + page_offset, |
517 | user_data, length); | |
3e4d3af5 | 518 | io_mapping_unmap_atomic(vaddr_atomic); |
fbd5a26d | 519 | return unwritten; |
0839ccb8 KP |
520 | } |
521 | ||
522 | /* Here's the write path which can sleep for | |
523 | * page faults | |
524 | */ | |
525 | ||
ab34c226 | 526 | static inline void |
3de09aa3 EA |
527 | slow_kernel_write(struct io_mapping *mapping, |
528 | loff_t gtt_base, int gtt_offset, | |
529 | struct page *user_page, int user_offset, | |
530 | int length) | |
0839ccb8 | 531 | { |
ab34c226 CW |
532 | char __iomem *dst_vaddr; |
533 | char *src_vaddr; | |
0839ccb8 | 534 | |
ab34c226 CW |
535 | dst_vaddr = io_mapping_map_wc(mapping, gtt_base); |
536 | src_vaddr = kmap(user_page); | |
537 | ||
538 | memcpy_toio(dst_vaddr + gtt_offset, | |
539 | src_vaddr + user_offset, | |
540 | length); | |
541 | ||
542 | kunmap(user_page); | |
543 | io_mapping_unmap(dst_vaddr); | |
9b7530cc LT |
544 | } |
545 | ||
3de09aa3 EA |
546 | /** |
547 | * This is the fast pwrite path, where we copy the data directly from the | |
548 | * user into the GTT, uncached. | |
549 | */ | |
673a394b | 550 | static int |
05394f39 CW |
551 | i915_gem_gtt_pwrite_fast(struct drm_device *dev, |
552 | struct drm_i915_gem_object *obj, | |
3de09aa3 | 553 | struct drm_i915_gem_pwrite *args, |
05394f39 | 554 | struct drm_file *file) |
673a394b | 555 | { |
0839ccb8 | 556 | drm_i915_private_t *dev_priv = dev->dev_private; |
673a394b | 557 | ssize_t remain; |
0839ccb8 | 558 | loff_t offset, page_base; |
673a394b | 559 | char __user *user_data; |
0839ccb8 | 560 | int page_offset, page_length; |
673a394b EA |
561 | |
562 | user_data = (char __user *) (uintptr_t) args->data_ptr; | |
563 | remain = args->size; | |
673a394b | 564 | |
05394f39 | 565 | offset = obj->gtt_offset + args->offset; |
673a394b EA |
566 | |
567 | while (remain > 0) { | |
568 | /* Operation in this page | |
569 | * | |
0839ccb8 KP |
570 | * page_base = page offset within aperture |
571 | * page_offset = offset within page | |
572 | * page_length = bytes to copy for this page | |
673a394b | 573 | */ |
c8cbbb8b CW |
574 | page_base = offset & PAGE_MASK; |
575 | page_offset = offset_in_page(offset); | |
0839ccb8 KP |
576 | page_length = remain; |
577 | if ((page_offset + remain) > PAGE_SIZE) | |
578 | page_length = PAGE_SIZE - page_offset; | |
579 | ||
0839ccb8 | 580 | /* If we get a fault while copying data, then (presumably) our |
3de09aa3 EA |
581 | * source page isn't available. Return the error and we'll |
582 | * retry in the slow path. | |
0839ccb8 | 583 | */ |
fbd5a26d CW |
584 | if (fast_user_write(dev_priv->mm.gtt_mapping, page_base, |
585 | page_offset, user_data, page_length)) | |
fbd5a26d | 586 | return -EFAULT; |
673a394b | 587 | |
0839ccb8 KP |
588 | remain -= page_length; |
589 | user_data += page_length; | |
590 | offset += page_length; | |
673a394b | 591 | } |
673a394b | 592 | |
fbd5a26d | 593 | return 0; |
673a394b EA |
594 | } |
595 | ||
3de09aa3 EA |
596 | /** |
597 | * This is the fallback GTT pwrite path, which uses get_user_pages to pin | |
598 | * the memory and maps it using kmap_atomic for copying. | |
599 | * | |
600 | * This code resulted in x11perf -rgb10text consuming about 10% more CPU | |
601 | * than using i915_gem_gtt_pwrite_fast on a G45 (32-bit). | |
602 | */ | |
3043c60c | 603 | static int |
05394f39 CW |
604 | i915_gem_gtt_pwrite_slow(struct drm_device *dev, |
605 | struct drm_i915_gem_object *obj, | |
3de09aa3 | 606 | struct drm_i915_gem_pwrite *args, |
05394f39 | 607 | struct drm_file *file) |
673a394b | 608 | { |
3de09aa3 EA |
609 | drm_i915_private_t *dev_priv = dev->dev_private; |
610 | ssize_t remain; | |
611 | loff_t gtt_page_base, offset; | |
612 | loff_t first_data_page, last_data_page, num_pages; | |
613 | loff_t pinned_pages, i; | |
614 | struct page **user_pages; | |
615 | struct mm_struct *mm = current->mm; | |
616 | int gtt_page_offset, data_page_offset, data_page_index, page_length; | |
673a394b | 617 | int ret; |
3de09aa3 EA |
618 | uint64_t data_ptr = args->data_ptr; |
619 | ||
620 | remain = args->size; | |
621 | ||
622 | /* Pin the user pages containing the data. We can't fault while | |
623 | * holding the struct mutex, and all of the pwrite implementations | |
624 | * want to hold it while dereferencing the user data. | |
625 | */ | |
626 | first_data_page = data_ptr / PAGE_SIZE; | |
627 | last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE; | |
628 | num_pages = last_data_page - first_data_page + 1; | |
629 | ||
fbd5a26d | 630 | user_pages = drm_malloc_ab(num_pages, sizeof(struct page *)); |
3de09aa3 EA |
631 | if (user_pages == NULL) |
632 | return -ENOMEM; | |
633 | ||
fbd5a26d | 634 | mutex_unlock(&dev->struct_mutex); |
3de09aa3 EA |
635 | down_read(&mm->mmap_sem); |
636 | pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr, | |
637 | num_pages, 0, 0, user_pages, NULL); | |
638 | up_read(&mm->mmap_sem); | |
fbd5a26d | 639 | mutex_lock(&dev->struct_mutex); |
3de09aa3 EA |
640 | if (pinned_pages < num_pages) { |
641 | ret = -EFAULT; | |
642 | goto out_unpin_pages; | |
643 | } | |
673a394b | 644 | |
d9e86c0e CW |
645 | ret = i915_gem_object_set_to_gtt_domain(obj, true); |
646 | if (ret) | |
647 | goto out_unpin_pages; | |
648 | ||
649 | ret = i915_gem_object_put_fence(obj); | |
3de09aa3 | 650 | if (ret) |
fbd5a26d | 651 | goto out_unpin_pages; |
3de09aa3 | 652 | |
05394f39 | 653 | offset = obj->gtt_offset + args->offset; |
3de09aa3 EA |
654 | |
655 | while (remain > 0) { | |
656 | /* Operation in this page | |
657 | * | |
658 | * gtt_page_base = page offset within aperture | |
659 | * gtt_page_offset = offset within page in aperture | |
660 | * data_page_index = page number in get_user_pages return | |
661 | * data_page_offset = offset with data_page_index page. | |
662 | * page_length = bytes to copy for this page | |
663 | */ | |
664 | gtt_page_base = offset & PAGE_MASK; | |
c8cbbb8b | 665 | gtt_page_offset = offset_in_page(offset); |
3de09aa3 | 666 | data_page_index = data_ptr / PAGE_SIZE - first_data_page; |
c8cbbb8b | 667 | data_page_offset = offset_in_page(data_ptr); |
3de09aa3 EA |
668 | |
669 | page_length = remain; | |
670 | if ((gtt_page_offset + page_length) > PAGE_SIZE) | |
671 | page_length = PAGE_SIZE - gtt_page_offset; | |
672 | if ((data_page_offset + page_length) > PAGE_SIZE) | |
673 | page_length = PAGE_SIZE - data_page_offset; | |
674 | ||
ab34c226 CW |
675 | slow_kernel_write(dev_priv->mm.gtt_mapping, |
676 | gtt_page_base, gtt_page_offset, | |
677 | user_pages[data_page_index], | |
678 | data_page_offset, | |
679 | page_length); | |
3de09aa3 EA |
680 | |
681 | remain -= page_length; | |
682 | offset += page_length; | |
683 | data_ptr += page_length; | |
684 | } | |
685 | ||
3de09aa3 EA |
686 | out_unpin_pages: |
687 | for (i = 0; i < pinned_pages; i++) | |
688 | page_cache_release(user_pages[i]); | |
8e7d2b2c | 689 | drm_free_large(user_pages); |
3de09aa3 EA |
690 | |
691 | return ret; | |
692 | } | |
693 | ||
3043c60c | 694 | static int |
e244a443 DV |
695 | i915_gem_shmem_pwrite(struct drm_device *dev, |
696 | struct drm_i915_gem_object *obj, | |
697 | struct drm_i915_gem_pwrite *args, | |
698 | struct drm_file *file) | |
40123c1f | 699 | { |
05394f39 | 700 | struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping; |
40123c1f | 701 | ssize_t remain; |
8c59967c DV |
702 | loff_t offset; |
703 | char __user *user_data; | |
eb2c0c81 | 704 | int shmem_page_offset, page_length, ret = 0; |
8c59967c | 705 | int obj_do_bit17_swizzling, page_do_bit17_swizzling; |
e244a443 | 706 | int hit_slowpath = 0; |
40123c1f | 707 | |
8c59967c | 708 | user_data = (char __user *) (uintptr_t) args->data_ptr; |
40123c1f EA |
709 | remain = args->size; |
710 | ||
8c59967c | 711 | obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj); |
40123c1f | 712 | |
673a394b | 713 | offset = args->offset; |
05394f39 | 714 | obj->dirty = 1; |
673a394b | 715 | |
40123c1f | 716 | while (remain > 0) { |
e5281ccd | 717 | struct page *page; |
8c59967c | 718 | char *vaddr; |
e5281ccd | 719 | |
40123c1f EA |
720 | /* Operation in this page |
721 | * | |
40123c1f | 722 | * shmem_page_offset = offset within page in shmem file |
40123c1f EA |
723 | * page_length = bytes to copy for this page |
724 | */ | |
c8cbbb8b | 725 | shmem_page_offset = offset_in_page(offset); |
40123c1f EA |
726 | |
727 | page_length = remain; | |
728 | if ((shmem_page_offset + page_length) > PAGE_SIZE) | |
729 | page_length = PAGE_SIZE - shmem_page_offset; | |
40123c1f | 730 | |
5949eac4 | 731 | page = shmem_read_mapping_page(mapping, offset >> PAGE_SHIFT); |
e5281ccd CW |
732 | if (IS_ERR(page)) { |
733 | ret = PTR_ERR(page); | |
734 | goto out; | |
735 | } | |
736 | ||
8c59967c DV |
737 | page_do_bit17_swizzling = obj_do_bit17_swizzling && |
738 | (page_to_phys(page) & (1 << 17)) != 0; | |
739 | ||
e244a443 DV |
740 | if (!page_do_bit17_swizzling) { |
741 | vaddr = kmap_atomic(page); | |
742 | ret = __copy_from_user_inatomic(vaddr + shmem_page_offset, | |
743 | user_data, | |
744 | page_length); | |
745 | kunmap_atomic(vaddr); | |
746 | ||
747 | if (ret == 0) | |
748 | goto next_page; | |
749 | } | |
750 | ||
751 | hit_slowpath = 1; | |
752 | ||
753 | mutex_unlock(&dev->struct_mutex); | |
754 | ||
8c59967c DV |
755 | vaddr = kmap(page); |
756 | if (page_do_bit17_swizzling) | |
757 | ret = __copy_from_user_swizzled(vaddr, shmem_page_offset, | |
758 | user_data, | |
759 | page_length); | |
760 | else | |
761 | ret = __copy_from_user(vaddr + shmem_page_offset, | |
762 | user_data, | |
763 | page_length); | |
764 | kunmap(page); | |
40123c1f | 765 | |
e244a443 DV |
766 | mutex_lock(&dev->struct_mutex); |
767 | next_page: | |
e5281ccd CW |
768 | set_page_dirty(page); |
769 | mark_page_accessed(page); | |
770 | page_cache_release(page); | |
771 | ||
8c59967c DV |
772 | if (ret) { |
773 | ret = -EFAULT; | |
774 | goto out; | |
775 | } | |
776 | ||
40123c1f | 777 | remain -= page_length; |
8c59967c | 778 | user_data += page_length; |
40123c1f | 779 | offset += page_length; |
673a394b EA |
780 | } |
781 | ||
fbd5a26d | 782 | out: |
e244a443 DV |
783 | if (hit_slowpath) { |
784 | /* Fixup: Kill any reinstated backing storage pages */ | |
785 | if (obj->madv == __I915_MADV_PURGED) | |
786 | i915_gem_object_truncate(obj); | |
787 | /* and flush dirty cachelines in case the object isn't in the cpu write | |
788 | * domain anymore. */ | |
789 | if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) { | |
790 | i915_gem_clflush_object(obj); | |
791 | intel_gtt_chipset_flush(); | |
792 | } | |
8c59967c | 793 | } |
673a394b | 794 | |
40123c1f | 795 | return ret; |
673a394b EA |
796 | } |
797 | ||
798 | /** | |
799 | * Writes data to the object referenced by handle. | |
800 | * | |
801 | * On error, the contents of the buffer that were to be modified are undefined. | |
802 | */ | |
803 | int | |
804 | i915_gem_pwrite_ioctl(struct drm_device *dev, void *data, | |
fbd5a26d | 805 | struct drm_file *file) |
673a394b EA |
806 | { |
807 | struct drm_i915_gem_pwrite *args = data; | |
05394f39 | 808 | struct drm_i915_gem_object *obj; |
51311d0a CW |
809 | int ret; |
810 | ||
811 | if (args->size == 0) | |
812 | return 0; | |
813 | ||
814 | if (!access_ok(VERIFY_READ, | |
815 | (char __user *)(uintptr_t)args->data_ptr, | |
816 | args->size)) | |
817 | return -EFAULT; | |
818 | ||
819 | ret = fault_in_pages_readable((char __user *)(uintptr_t)args->data_ptr, | |
820 | args->size); | |
821 | if (ret) | |
822 | return -EFAULT; | |
673a394b | 823 | |
fbd5a26d | 824 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 825 | if (ret) |
fbd5a26d | 826 | return ret; |
1d7cfea1 | 827 | |
05394f39 | 828 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 829 | if (&obj->base == NULL) { |
1d7cfea1 CW |
830 | ret = -ENOENT; |
831 | goto unlock; | |
fbd5a26d | 832 | } |
673a394b | 833 | |
7dcd2499 | 834 | /* Bounds check destination. */ |
05394f39 CW |
835 | if (args->offset > obj->base.size || |
836 | args->size > obj->base.size - args->offset) { | |
ce9d419d | 837 | ret = -EINVAL; |
35b62a89 | 838 | goto out; |
ce9d419d CW |
839 | } |
840 | ||
db53a302 CW |
841 | trace_i915_gem_object_pwrite(obj, args->offset, args->size); |
842 | ||
673a394b EA |
843 | /* We can only do the GTT pwrite on untiled buffers, as otherwise |
844 | * it would end up going through the fenced access, and we'll get | |
845 | * different detiling behavior between reading and writing. | |
846 | * pread/pwrite currently are reading and writing from the CPU | |
847 | * perspective, requiring manual detiling by the client. | |
848 | */ | |
5c0480f2 | 849 | if (obj->phys_obj) { |
fbd5a26d | 850 | ret = i915_gem_phys_pwrite(dev, obj, args, file); |
5c0480f2 DV |
851 | goto out; |
852 | } | |
853 | ||
854 | if (obj->gtt_space && | |
855 | obj->base.write_domain != I915_GEM_DOMAIN_CPU) { | |
75e9e915 | 856 | ret = i915_gem_object_pin(obj, 0, true); |
fbd5a26d CW |
857 | if (ret) |
858 | goto out; | |
859 | ||
d9e86c0e CW |
860 | ret = i915_gem_object_set_to_gtt_domain(obj, true); |
861 | if (ret) | |
862 | goto out_unpin; | |
863 | ||
864 | ret = i915_gem_object_put_fence(obj); | |
fbd5a26d CW |
865 | if (ret) |
866 | goto out_unpin; | |
867 | ||
868 | ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file); | |
869 | if (ret == -EFAULT) | |
870 | ret = i915_gem_gtt_pwrite_slow(dev, obj, args, file); | |
871 | ||
872 | out_unpin: | |
873 | i915_gem_object_unpin(obj); | |
673a394b | 874 | |
5c0480f2 DV |
875 | if (ret != -EFAULT) |
876 | goto out; | |
877 | /* Fall through to the shmfs paths because the gtt paths might | |
878 | * fail with non-page-backed user pointers (e.g. gtt mappings | |
879 | * when moving data between textures). */ | |
fbd5a26d | 880 | } |
673a394b | 881 | |
5c0480f2 DV |
882 | ret = i915_gem_object_set_to_cpu_domain(obj, 1); |
883 | if (ret) | |
884 | goto out; | |
885 | ||
e244a443 | 886 | ret = i915_gem_shmem_pwrite(dev, obj, args, file); |
5c0480f2 | 887 | |
35b62a89 | 888 | out: |
05394f39 | 889 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 890 | unlock: |
fbd5a26d | 891 | mutex_unlock(&dev->struct_mutex); |
673a394b EA |
892 | return ret; |
893 | } | |
894 | ||
895 | /** | |
2ef7eeaa EA |
896 | * Called when user space prepares to use an object with the CPU, either |
897 | * through the mmap ioctl's mapping or a GTT mapping. | |
673a394b EA |
898 | */ |
899 | int | |
900 | i915_gem_set_domain_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 901 | struct drm_file *file) |
673a394b EA |
902 | { |
903 | struct drm_i915_gem_set_domain *args = data; | |
05394f39 | 904 | struct drm_i915_gem_object *obj; |
2ef7eeaa EA |
905 | uint32_t read_domains = args->read_domains; |
906 | uint32_t write_domain = args->write_domain; | |
673a394b EA |
907 | int ret; |
908 | ||
909 | if (!(dev->driver->driver_features & DRIVER_GEM)) | |
910 | return -ENODEV; | |
911 | ||
2ef7eeaa | 912 | /* Only handle setting domains to types used by the CPU. */ |
21d509e3 | 913 | if (write_domain & I915_GEM_GPU_DOMAINS) |
2ef7eeaa EA |
914 | return -EINVAL; |
915 | ||
21d509e3 | 916 | if (read_domains & I915_GEM_GPU_DOMAINS) |
2ef7eeaa EA |
917 | return -EINVAL; |
918 | ||
919 | /* Having something in the write domain implies it's in the read | |
920 | * domain, and only that read domain. Enforce that in the request. | |
921 | */ | |
922 | if (write_domain != 0 && read_domains != write_domain) | |
923 | return -EINVAL; | |
924 | ||
76c1dec1 | 925 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 926 | if (ret) |
76c1dec1 | 927 | return ret; |
1d7cfea1 | 928 | |
05394f39 | 929 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 930 | if (&obj->base == NULL) { |
1d7cfea1 CW |
931 | ret = -ENOENT; |
932 | goto unlock; | |
76c1dec1 | 933 | } |
673a394b | 934 | |
2ef7eeaa EA |
935 | if (read_domains & I915_GEM_DOMAIN_GTT) { |
936 | ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0); | |
02354392 EA |
937 | |
938 | /* Silently promote "you're not bound, there was nothing to do" | |
939 | * to success, since the client was just asking us to | |
940 | * make sure everything was done. | |
941 | */ | |
942 | if (ret == -EINVAL) | |
943 | ret = 0; | |
2ef7eeaa | 944 | } else { |
e47c68e9 | 945 | ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0); |
2ef7eeaa EA |
946 | } |
947 | ||
05394f39 | 948 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 949 | unlock: |
673a394b EA |
950 | mutex_unlock(&dev->struct_mutex); |
951 | return ret; | |
952 | } | |
953 | ||
954 | /** | |
955 | * Called when user space has done writes to this buffer | |
956 | */ | |
957 | int | |
958 | i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 959 | struct drm_file *file) |
673a394b EA |
960 | { |
961 | struct drm_i915_gem_sw_finish *args = data; | |
05394f39 | 962 | struct drm_i915_gem_object *obj; |
673a394b EA |
963 | int ret = 0; |
964 | ||
965 | if (!(dev->driver->driver_features & DRIVER_GEM)) | |
966 | return -ENODEV; | |
967 | ||
76c1dec1 | 968 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 969 | if (ret) |
76c1dec1 | 970 | return ret; |
1d7cfea1 | 971 | |
05394f39 | 972 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 973 | if (&obj->base == NULL) { |
1d7cfea1 CW |
974 | ret = -ENOENT; |
975 | goto unlock; | |
673a394b EA |
976 | } |
977 | ||
673a394b | 978 | /* Pinned buffers may be scanout, so flush the cache */ |
05394f39 | 979 | if (obj->pin_count) |
e47c68e9 EA |
980 | i915_gem_object_flush_cpu_write_domain(obj); |
981 | ||
05394f39 | 982 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 983 | unlock: |
673a394b EA |
984 | mutex_unlock(&dev->struct_mutex); |
985 | return ret; | |
986 | } | |
987 | ||
988 | /** | |
989 | * Maps the contents of an object, returning the address it is mapped | |
990 | * into. | |
991 | * | |
992 | * While the mapping holds a reference on the contents of the object, it doesn't | |
993 | * imply a ref on the object itself. | |
994 | */ | |
995 | int | |
996 | i915_gem_mmap_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 997 | struct drm_file *file) |
673a394b EA |
998 | { |
999 | struct drm_i915_gem_mmap *args = data; | |
1000 | struct drm_gem_object *obj; | |
673a394b EA |
1001 | unsigned long addr; |
1002 | ||
1003 | if (!(dev->driver->driver_features & DRIVER_GEM)) | |
1004 | return -ENODEV; | |
1005 | ||
05394f39 | 1006 | obj = drm_gem_object_lookup(dev, file, args->handle); |
673a394b | 1007 | if (obj == NULL) |
bf79cb91 | 1008 | return -ENOENT; |
673a394b | 1009 | |
673a394b EA |
1010 | down_write(¤t->mm->mmap_sem); |
1011 | addr = do_mmap(obj->filp, 0, args->size, | |
1012 | PROT_READ | PROT_WRITE, MAP_SHARED, | |
1013 | args->offset); | |
1014 | up_write(¤t->mm->mmap_sem); | |
bc9025bd | 1015 | drm_gem_object_unreference_unlocked(obj); |
673a394b EA |
1016 | if (IS_ERR((void *)addr)) |
1017 | return addr; | |
1018 | ||
1019 | args->addr_ptr = (uint64_t) addr; | |
1020 | ||
1021 | return 0; | |
1022 | } | |
1023 | ||
de151cf6 JB |
1024 | /** |
1025 | * i915_gem_fault - fault a page into the GTT | |
1026 | * vma: VMA in question | |
1027 | * vmf: fault info | |
1028 | * | |
1029 | * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped | |
1030 | * from userspace. The fault handler takes care of binding the object to | |
1031 | * the GTT (if needed), allocating and programming a fence register (again, | |
1032 | * only if needed based on whether the old reg is still valid or the object | |
1033 | * is tiled) and inserting a new PTE into the faulting process. | |
1034 | * | |
1035 | * Note that the faulting process may involve evicting existing objects | |
1036 | * from the GTT and/or fence registers to make room. So performance may | |
1037 | * suffer if the GTT working set is large or there are few fence registers | |
1038 | * left. | |
1039 | */ | |
1040 | int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf) | |
1041 | { | |
05394f39 CW |
1042 | struct drm_i915_gem_object *obj = to_intel_bo(vma->vm_private_data); |
1043 | struct drm_device *dev = obj->base.dev; | |
7d1c4804 | 1044 | drm_i915_private_t *dev_priv = dev->dev_private; |
de151cf6 JB |
1045 | pgoff_t page_offset; |
1046 | unsigned long pfn; | |
1047 | int ret = 0; | |
0f973f27 | 1048 | bool write = !!(vmf->flags & FAULT_FLAG_WRITE); |
de151cf6 JB |
1049 | |
1050 | /* We don't use vmf->pgoff since that has the fake offset */ | |
1051 | page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >> | |
1052 | PAGE_SHIFT; | |
1053 | ||
d9bc7e9f CW |
1054 | ret = i915_mutex_lock_interruptible(dev); |
1055 | if (ret) | |
1056 | goto out; | |
a00b10c3 | 1057 | |
db53a302 CW |
1058 | trace_i915_gem_object_fault(obj, page_offset, true, write); |
1059 | ||
d9bc7e9f | 1060 | /* Now bind it into the GTT if needed */ |
919926ae CW |
1061 | if (!obj->map_and_fenceable) { |
1062 | ret = i915_gem_object_unbind(obj); | |
1063 | if (ret) | |
1064 | goto unlock; | |
a00b10c3 | 1065 | } |
05394f39 | 1066 | if (!obj->gtt_space) { |
75e9e915 | 1067 | ret = i915_gem_object_bind_to_gtt(obj, 0, true); |
c715089f CW |
1068 | if (ret) |
1069 | goto unlock; | |
de151cf6 | 1070 | |
e92d03bf EA |
1071 | ret = i915_gem_object_set_to_gtt_domain(obj, write); |
1072 | if (ret) | |
1073 | goto unlock; | |
1074 | } | |
4a684a41 | 1075 | |
74898d7e DV |
1076 | if (!obj->has_global_gtt_mapping) |
1077 | i915_gem_gtt_bind_object(obj, obj->cache_level); | |
1078 | ||
d9e86c0e CW |
1079 | if (obj->tiling_mode == I915_TILING_NONE) |
1080 | ret = i915_gem_object_put_fence(obj); | |
1081 | else | |
ce453d81 | 1082 | ret = i915_gem_object_get_fence(obj, NULL); |
d9e86c0e CW |
1083 | if (ret) |
1084 | goto unlock; | |
de151cf6 | 1085 | |
05394f39 CW |
1086 | if (i915_gem_object_is_inactive(obj)) |
1087 | list_move_tail(&obj->mm_list, &dev_priv->mm.inactive_list); | |
7d1c4804 | 1088 | |
6299f992 CW |
1089 | obj->fault_mappable = true; |
1090 | ||
05394f39 | 1091 | pfn = ((dev->agp->base + obj->gtt_offset) >> PAGE_SHIFT) + |
de151cf6 JB |
1092 | page_offset; |
1093 | ||
1094 | /* Finally, remap it using the new GTT offset */ | |
1095 | ret = vm_insert_pfn(vma, (unsigned long)vmf->virtual_address, pfn); | |
c715089f | 1096 | unlock: |
de151cf6 | 1097 | mutex_unlock(&dev->struct_mutex); |
d9bc7e9f | 1098 | out: |
de151cf6 | 1099 | switch (ret) { |
d9bc7e9f | 1100 | case -EIO: |
045e769a | 1101 | case -EAGAIN: |
d9bc7e9f CW |
1102 | /* Give the error handler a chance to run and move the |
1103 | * objects off the GPU active list. Next time we service the | |
1104 | * fault, we should be able to transition the page into the | |
1105 | * GTT without touching the GPU (and so avoid further | |
1106 | * EIO/EGAIN). If the GPU is wedged, then there is no issue | |
1107 | * with coherency, just lost writes. | |
1108 | */ | |
045e769a | 1109 | set_need_resched(); |
c715089f CW |
1110 | case 0: |
1111 | case -ERESTARTSYS: | |
bed636ab | 1112 | case -EINTR: |
c715089f | 1113 | return VM_FAULT_NOPAGE; |
de151cf6 | 1114 | case -ENOMEM: |
de151cf6 | 1115 | return VM_FAULT_OOM; |
de151cf6 | 1116 | default: |
c715089f | 1117 | return VM_FAULT_SIGBUS; |
de151cf6 JB |
1118 | } |
1119 | } | |
1120 | ||
901782b2 CW |
1121 | /** |
1122 | * i915_gem_release_mmap - remove physical page mappings | |
1123 | * @obj: obj in question | |
1124 | * | |
af901ca1 | 1125 | * Preserve the reservation of the mmapping with the DRM core code, but |
901782b2 CW |
1126 | * relinquish ownership of the pages back to the system. |
1127 | * | |
1128 | * It is vital that we remove the page mapping if we have mapped a tiled | |
1129 | * object through the GTT and then lose the fence register due to | |
1130 | * resource pressure. Similarly if the object has been moved out of the | |
1131 | * aperture, than pages mapped into userspace must be revoked. Removing the | |
1132 | * mapping will then trigger a page fault on the next user access, allowing | |
1133 | * fixup by i915_gem_fault(). | |
1134 | */ | |
d05ca301 | 1135 | void |
05394f39 | 1136 | i915_gem_release_mmap(struct drm_i915_gem_object *obj) |
901782b2 | 1137 | { |
6299f992 CW |
1138 | if (!obj->fault_mappable) |
1139 | return; | |
901782b2 | 1140 | |
f6e47884 CW |
1141 | if (obj->base.dev->dev_mapping) |
1142 | unmap_mapping_range(obj->base.dev->dev_mapping, | |
1143 | (loff_t)obj->base.map_list.hash.key<<PAGE_SHIFT, | |
1144 | obj->base.size, 1); | |
fb7d516a | 1145 | |
6299f992 | 1146 | obj->fault_mappable = false; |
901782b2 CW |
1147 | } |
1148 | ||
92b88aeb | 1149 | static uint32_t |
e28f8711 | 1150 | i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode) |
92b88aeb | 1151 | { |
e28f8711 | 1152 | uint32_t gtt_size; |
92b88aeb CW |
1153 | |
1154 | if (INTEL_INFO(dev)->gen >= 4 || | |
e28f8711 CW |
1155 | tiling_mode == I915_TILING_NONE) |
1156 | return size; | |
92b88aeb CW |
1157 | |
1158 | /* Previous chips need a power-of-two fence region when tiling */ | |
1159 | if (INTEL_INFO(dev)->gen == 3) | |
e28f8711 | 1160 | gtt_size = 1024*1024; |
92b88aeb | 1161 | else |
e28f8711 | 1162 | gtt_size = 512*1024; |
92b88aeb | 1163 | |
e28f8711 CW |
1164 | while (gtt_size < size) |
1165 | gtt_size <<= 1; | |
92b88aeb | 1166 | |
e28f8711 | 1167 | return gtt_size; |
92b88aeb CW |
1168 | } |
1169 | ||
de151cf6 JB |
1170 | /** |
1171 | * i915_gem_get_gtt_alignment - return required GTT alignment for an object | |
1172 | * @obj: object to check | |
1173 | * | |
1174 | * Return the required GTT alignment for an object, taking into account | |
5e783301 | 1175 | * potential fence register mapping. |
de151cf6 JB |
1176 | */ |
1177 | static uint32_t | |
e28f8711 CW |
1178 | i915_gem_get_gtt_alignment(struct drm_device *dev, |
1179 | uint32_t size, | |
1180 | int tiling_mode) | |
de151cf6 | 1181 | { |
de151cf6 JB |
1182 | /* |
1183 | * Minimum alignment is 4k (GTT page size), but might be greater | |
1184 | * if a fence register is needed for the object. | |
1185 | */ | |
a00b10c3 | 1186 | if (INTEL_INFO(dev)->gen >= 4 || |
e28f8711 | 1187 | tiling_mode == I915_TILING_NONE) |
de151cf6 JB |
1188 | return 4096; |
1189 | ||
a00b10c3 CW |
1190 | /* |
1191 | * Previous chips need to be aligned to the size of the smallest | |
1192 | * fence register that can contain the object. | |
1193 | */ | |
e28f8711 | 1194 | return i915_gem_get_gtt_size(dev, size, tiling_mode); |
a00b10c3 CW |
1195 | } |
1196 | ||
5e783301 DV |
1197 | /** |
1198 | * i915_gem_get_unfenced_gtt_alignment - return required GTT alignment for an | |
1199 | * unfenced object | |
e28f8711 CW |
1200 | * @dev: the device |
1201 | * @size: size of the object | |
1202 | * @tiling_mode: tiling mode of the object | |
5e783301 DV |
1203 | * |
1204 | * Return the required GTT alignment for an object, only taking into account | |
1205 | * unfenced tiled surface requirements. | |
1206 | */ | |
467cffba | 1207 | uint32_t |
e28f8711 CW |
1208 | i915_gem_get_unfenced_gtt_alignment(struct drm_device *dev, |
1209 | uint32_t size, | |
1210 | int tiling_mode) | |
5e783301 | 1211 | { |
5e783301 DV |
1212 | /* |
1213 | * Minimum alignment is 4k (GTT page size) for sane hw. | |
1214 | */ | |
1215 | if (INTEL_INFO(dev)->gen >= 4 || IS_G33(dev) || | |
e28f8711 | 1216 | tiling_mode == I915_TILING_NONE) |
5e783301 DV |
1217 | return 4096; |
1218 | ||
e28f8711 CW |
1219 | /* Previous hardware however needs to be aligned to a power-of-two |
1220 | * tile height. The simplest method for determining this is to reuse | |
1221 | * the power-of-tile object size. | |
5e783301 | 1222 | */ |
e28f8711 | 1223 | return i915_gem_get_gtt_size(dev, size, tiling_mode); |
5e783301 DV |
1224 | } |
1225 | ||
de151cf6 | 1226 | int |
ff72145b DA |
1227 | i915_gem_mmap_gtt(struct drm_file *file, |
1228 | struct drm_device *dev, | |
1229 | uint32_t handle, | |
1230 | uint64_t *offset) | |
de151cf6 | 1231 | { |
da761a6e | 1232 | struct drm_i915_private *dev_priv = dev->dev_private; |
05394f39 | 1233 | struct drm_i915_gem_object *obj; |
de151cf6 JB |
1234 | int ret; |
1235 | ||
1236 | if (!(dev->driver->driver_features & DRIVER_GEM)) | |
1237 | return -ENODEV; | |
1238 | ||
76c1dec1 | 1239 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 1240 | if (ret) |
76c1dec1 | 1241 | return ret; |
de151cf6 | 1242 | |
ff72145b | 1243 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle)); |
c8725226 | 1244 | if (&obj->base == NULL) { |
1d7cfea1 CW |
1245 | ret = -ENOENT; |
1246 | goto unlock; | |
1247 | } | |
de151cf6 | 1248 | |
05394f39 | 1249 | if (obj->base.size > dev_priv->mm.gtt_mappable_end) { |
da761a6e | 1250 | ret = -E2BIG; |
ff56b0bc | 1251 | goto out; |
da761a6e CW |
1252 | } |
1253 | ||
05394f39 | 1254 | if (obj->madv != I915_MADV_WILLNEED) { |
ab18282d | 1255 | DRM_ERROR("Attempting to mmap a purgeable buffer\n"); |
1d7cfea1 CW |
1256 | ret = -EINVAL; |
1257 | goto out; | |
ab18282d CW |
1258 | } |
1259 | ||
05394f39 | 1260 | if (!obj->base.map_list.map) { |
b464e9a2 | 1261 | ret = drm_gem_create_mmap_offset(&obj->base); |
1d7cfea1 CW |
1262 | if (ret) |
1263 | goto out; | |
de151cf6 JB |
1264 | } |
1265 | ||
ff72145b | 1266 | *offset = (u64)obj->base.map_list.hash.key << PAGE_SHIFT; |
de151cf6 | 1267 | |
1d7cfea1 | 1268 | out: |
05394f39 | 1269 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 1270 | unlock: |
de151cf6 | 1271 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 1272 | return ret; |
de151cf6 JB |
1273 | } |
1274 | ||
ff72145b DA |
1275 | /** |
1276 | * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing | |
1277 | * @dev: DRM device | |
1278 | * @data: GTT mapping ioctl data | |
1279 | * @file: GEM object info | |
1280 | * | |
1281 | * Simply returns the fake offset to userspace so it can mmap it. | |
1282 | * The mmap call will end up in drm_gem_mmap(), which will set things | |
1283 | * up so we can get faults in the handler above. | |
1284 | * | |
1285 | * The fault handler will take care of binding the object into the GTT | |
1286 | * (since it may have been evicted to make room for something), allocating | |
1287 | * a fence register, and mapping the appropriate aperture address into | |
1288 | * userspace. | |
1289 | */ | |
1290 | int | |
1291 | i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data, | |
1292 | struct drm_file *file) | |
1293 | { | |
1294 | struct drm_i915_gem_mmap_gtt *args = data; | |
1295 | ||
1296 | if (!(dev->driver->driver_features & DRIVER_GEM)) | |
1297 | return -ENODEV; | |
1298 | ||
1299 | return i915_gem_mmap_gtt(file, dev, args->handle, &args->offset); | |
1300 | } | |
1301 | ||
1302 | ||
e5281ccd | 1303 | static int |
05394f39 | 1304 | i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj, |
e5281ccd CW |
1305 | gfp_t gfpmask) |
1306 | { | |
e5281ccd CW |
1307 | int page_count, i; |
1308 | struct address_space *mapping; | |
1309 | struct inode *inode; | |
1310 | struct page *page; | |
1311 | ||
1312 | /* Get the list of pages out of our struct file. They'll be pinned | |
1313 | * at this point until we release them. | |
1314 | */ | |
05394f39 CW |
1315 | page_count = obj->base.size / PAGE_SIZE; |
1316 | BUG_ON(obj->pages != NULL); | |
1317 | obj->pages = drm_malloc_ab(page_count, sizeof(struct page *)); | |
1318 | if (obj->pages == NULL) | |
e5281ccd CW |
1319 | return -ENOMEM; |
1320 | ||
05394f39 | 1321 | inode = obj->base.filp->f_path.dentry->d_inode; |
e5281ccd | 1322 | mapping = inode->i_mapping; |
5949eac4 HD |
1323 | gfpmask |= mapping_gfp_mask(mapping); |
1324 | ||
e5281ccd | 1325 | for (i = 0; i < page_count; i++) { |
5949eac4 | 1326 | page = shmem_read_mapping_page_gfp(mapping, i, gfpmask); |
e5281ccd CW |
1327 | if (IS_ERR(page)) |
1328 | goto err_pages; | |
1329 | ||
05394f39 | 1330 | obj->pages[i] = page; |
e5281ccd CW |
1331 | } |
1332 | ||
6dacfd2f | 1333 | if (i915_gem_object_needs_bit17_swizzle(obj)) |
e5281ccd CW |
1334 | i915_gem_object_do_bit_17_swizzle(obj); |
1335 | ||
1336 | return 0; | |
1337 | ||
1338 | err_pages: | |
1339 | while (i--) | |
05394f39 | 1340 | page_cache_release(obj->pages[i]); |
e5281ccd | 1341 | |
05394f39 CW |
1342 | drm_free_large(obj->pages); |
1343 | obj->pages = NULL; | |
e5281ccd CW |
1344 | return PTR_ERR(page); |
1345 | } | |
1346 | ||
5cdf5881 | 1347 | static void |
05394f39 | 1348 | i915_gem_object_put_pages_gtt(struct drm_i915_gem_object *obj) |
673a394b | 1349 | { |
05394f39 | 1350 | int page_count = obj->base.size / PAGE_SIZE; |
673a394b EA |
1351 | int i; |
1352 | ||
05394f39 | 1353 | BUG_ON(obj->madv == __I915_MADV_PURGED); |
673a394b | 1354 | |
6dacfd2f | 1355 | if (i915_gem_object_needs_bit17_swizzle(obj)) |
280b713b EA |
1356 | i915_gem_object_save_bit_17_swizzle(obj); |
1357 | ||
05394f39 CW |
1358 | if (obj->madv == I915_MADV_DONTNEED) |
1359 | obj->dirty = 0; | |
3ef94daa CW |
1360 | |
1361 | for (i = 0; i < page_count; i++) { | |
05394f39 CW |
1362 | if (obj->dirty) |
1363 | set_page_dirty(obj->pages[i]); | |
3ef94daa | 1364 | |
05394f39 CW |
1365 | if (obj->madv == I915_MADV_WILLNEED) |
1366 | mark_page_accessed(obj->pages[i]); | |
3ef94daa | 1367 | |
05394f39 | 1368 | page_cache_release(obj->pages[i]); |
3ef94daa | 1369 | } |
05394f39 | 1370 | obj->dirty = 0; |
673a394b | 1371 | |
05394f39 CW |
1372 | drm_free_large(obj->pages); |
1373 | obj->pages = NULL; | |
673a394b EA |
1374 | } |
1375 | ||
54cf91dc | 1376 | void |
05394f39 | 1377 | i915_gem_object_move_to_active(struct drm_i915_gem_object *obj, |
1ec14ad3 CW |
1378 | struct intel_ring_buffer *ring, |
1379 | u32 seqno) | |
673a394b | 1380 | { |
05394f39 | 1381 | struct drm_device *dev = obj->base.dev; |
69dc4987 | 1382 | struct drm_i915_private *dev_priv = dev->dev_private; |
617dbe27 | 1383 | |
852835f3 | 1384 | BUG_ON(ring == NULL); |
05394f39 | 1385 | obj->ring = ring; |
673a394b EA |
1386 | |
1387 | /* Add a reference if we're newly entering the active list. */ | |
05394f39 CW |
1388 | if (!obj->active) { |
1389 | drm_gem_object_reference(&obj->base); | |
1390 | obj->active = 1; | |
673a394b | 1391 | } |
e35a41de | 1392 | |
673a394b | 1393 | /* Move from whatever list we were on to the tail of execution. */ |
05394f39 CW |
1394 | list_move_tail(&obj->mm_list, &dev_priv->mm.active_list); |
1395 | list_move_tail(&obj->ring_list, &ring->active_list); | |
caea7476 | 1396 | |
05394f39 | 1397 | obj->last_rendering_seqno = seqno; |
caea7476 CW |
1398 | if (obj->fenced_gpu_access) { |
1399 | struct drm_i915_fence_reg *reg; | |
1400 | ||
1401 | BUG_ON(obj->fence_reg == I915_FENCE_REG_NONE); | |
1402 | ||
1403 | obj->last_fenced_seqno = seqno; | |
1404 | obj->last_fenced_ring = ring; | |
1405 | ||
1406 | reg = &dev_priv->fence_regs[obj->fence_reg]; | |
1407 | list_move_tail(®->lru_list, &dev_priv->mm.fence_list); | |
1408 | } | |
1409 | } | |
1410 | ||
1411 | static void | |
1412 | i915_gem_object_move_off_active(struct drm_i915_gem_object *obj) | |
1413 | { | |
1414 | list_del_init(&obj->ring_list); | |
1415 | obj->last_rendering_seqno = 0; | |
673a394b EA |
1416 | } |
1417 | ||
ce44b0ea | 1418 | static void |
05394f39 | 1419 | i915_gem_object_move_to_flushing(struct drm_i915_gem_object *obj) |
ce44b0ea | 1420 | { |
05394f39 | 1421 | struct drm_device *dev = obj->base.dev; |
ce44b0ea | 1422 | drm_i915_private_t *dev_priv = dev->dev_private; |
ce44b0ea | 1423 | |
05394f39 CW |
1424 | BUG_ON(!obj->active); |
1425 | list_move_tail(&obj->mm_list, &dev_priv->mm.flushing_list); | |
caea7476 CW |
1426 | |
1427 | i915_gem_object_move_off_active(obj); | |
1428 | } | |
1429 | ||
1430 | static void | |
1431 | i915_gem_object_move_to_inactive(struct drm_i915_gem_object *obj) | |
1432 | { | |
1433 | struct drm_device *dev = obj->base.dev; | |
1434 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1435 | ||
1436 | if (obj->pin_count != 0) | |
1437 | list_move_tail(&obj->mm_list, &dev_priv->mm.pinned_list); | |
1438 | else | |
1439 | list_move_tail(&obj->mm_list, &dev_priv->mm.inactive_list); | |
1440 | ||
1441 | BUG_ON(!list_empty(&obj->gpu_write_list)); | |
1442 | BUG_ON(!obj->active); | |
1443 | obj->ring = NULL; | |
1444 | ||
1445 | i915_gem_object_move_off_active(obj); | |
1446 | obj->fenced_gpu_access = false; | |
caea7476 CW |
1447 | |
1448 | obj->active = 0; | |
87ca9c8a | 1449 | obj->pending_gpu_write = false; |
caea7476 CW |
1450 | drm_gem_object_unreference(&obj->base); |
1451 | ||
1452 | WARN_ON(i915_verify_lists(dev)); | |
ce44b0ea | 1453 | } |
673a394b | 1454 | |
963b4836 CW |
1455 | /* Immediately discard the backing storage */ |
1456 | static void | |
05394f39 | 1457 | i915_gem_object_truncate(struct drm_i915_gem_object *obj) |
963b4836 | 1458 | { |
bb6baf76 | 1459 | struct inode *inode; |
963b4836 | 1460 | |
ae9fed6b CW |
1461 | /* Our goal here is to return as much of the memory as |
1462 | * is possible back to the system as we are called from OOM. | |
1463 | * To do this we must instruct the shmfs to drop all of its | |
e2377fe0 | 1464 | * backing pages, *now*. |
ae9fed6b | 1465 | */ |
05394f39 | 1466 | inode = obj->base.filp->f_path.dentry->d_inode; |
e2377fe0 | 1467 | shmem_truncate_range(inode, 0, (loff_t)-1); |
bb6baf76 | 1468 | |
a14917ee CW |
1469 | if (obj->base.map_list.map) |
1470 | drm_gem_free_mmap_offset(&obj->base); | |
1471 | ||
05394f39 | 1472 | obj->madv = __I915_MADV_PURGED; |
963b4836 CW |
1473 | } |
1474 | ||
1475 | static inline int | |
05394f39 | 1476 | i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj) |
963b4836 | 1477 | { |
05394f39 | 1478 | return obj->madv == I915_MADV_DONTNEED; |
963b4836 CW |
1479 | } |
1480 | ||
63560396 | 1481 | static void |
db53a302 CW |
1482 | i915_gem_process_flushing_list(struct intel_ring_buffer *ring, |
1483 | uint32_t flush_domains) | |
63560396 | 1484 | { |
05394f39 | 1485 | struct drm_i915_gem_object *obj, *next; |
63560396 | 1486 | |
05394f39 | 1487 | list_for_each_entry_safe(obj, next, |
64193406 | 1488 | &ring->gpu_write_list, |
63560396 | 1489 | gpu_write_list) { |
05394f39 CW |
1490 | if (obj->base.write_domain & flush_domains) { |
1491 | uint32_t old_write_domain = obj->base.write_domain; | |
63560396 | 1492 | |
05394f39 CW |
1493 | obj->base.write_domain = 0; |
1494 | list_del_init(&obj->gpu_write_list); | |
1ec14ad3 | 1495 | i915_gem_object_move_to_active(obj, ring, |
db53a302 | 1496 | i915_gem_next_request_seqno(ring)); |
63560396 | 1497 | |
63560396 | 1498 | trace_i915_gem_object_change_domain(obj, |
05394f39 | 1499 | obj->base.read_domains, |
63560396 DV |
1500 | old_write_domain); |
1501 | } | |
1502 | } | |
1503 | } | |
8187a2b7 | 1504 | |
53d227f2 DV |
1505 | static u32 |
1506 | i915_gem_get_seqno(struct drm_device *dev) | |
1507 | { | |
1508 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1509 | u32 seqno = dev_priv->next_seqno; | |
1510 | ||
1511 | /* reserve 0 for non-seqno */ | |
1512 | if (++dev_priv->next_seqno == 0) | |
1513 | dev_priv->next_seqno = 1; | |
1514 | ||
1515 | return seqno; | |
1516 | } | |
1517 | ||
1518 | u32 | |
1519 | i915_gem_next_request_seqno(struct intel_ring_buffer *ring) | |
1520 | { | |
1521 | if (ring->outstanding_lazy_request == 0) | |
1522 | ring->outstanding_lazy_request = i915_gem_get_seqno(ring->dev); | |
1523 | ||
1524 | return ring->outstanding_lazy_request; | |
1525 | } | |
1526 | ||
3cce469c | 1527 | int |
db53a302 | 1528 | i915_add_request(struct intel_ring_buffer *ring, |
f787a5f5 | 1529 | struct drm_file *file, |
db53a302 | 1530 | struct drm_i915_gem_request *request) |
673a394b | 1531 | { |
db53a302 | 1532 | drm_i915_private_t *dev_priv = ring->dev->dev_private; |
673a394b | 1533 | uint32_t seqno; |
a71d8d94 | 1534 | u32 request_ring_position; |
673a394b | 1535 | int was_empty; |
3cce469c CW |
1536 | int ret; |
1537 | ||
1538 | BUG_ON(request == NULL); | |
53d227f2 | 1539 | seqno = i915_gem_next_request_seqno(ring); |
673a394b | 1540 | |
a71d8d94 CW |
1541 | /* Record the position of the start of the request so that |
1542 | * should we detect the updated seqno part-way through the | |
1543 | * GPU processing the request, we never over-estimate the | |
1544 | * position of the head. | |
1545 | */ | |
1546 | request_ring_position = intel_ring_get_tail(ring); | |
1547 | ||
3cce469c CW |
1548 | ret = ring->add_request(ring, &seqno); |
1549 | if (ret) | |
1550 | return ret; | |
673a394b | 1551 | |
db53a302 | 1552 | trace_i915_gem_request_add(ring, seqno); |
673a394b EA |
1553 | |
1554 | request->seqno = seqno; | |
852835f3 | 1555 | request->ring = ring; |
a71d8d94 | 1556 | request->tail = request_ring_position; |
673a394b | 1557 | request->emitted_jiffies = jiffies; |
852835f3 ZN |
1558 | was_empty = list_empty(&ring->request_list); |
1559 | list_add_tail(&request->list, &ring->request_list); | |
1560 | ||
db53a302 CW |
1561 | if (file) { |
1562 | struct drm_i915_file_private *file_priv = file->driver_priv; | |
1563 | ||
1c25595f | 1564 | spin_lock(&file_priv->mm.lock); |
f787a5f5 | 1565 | request->file_priv = file_priv; |
b962442e | 1566 | list_add_tail(&request->client_list, |
f787a5f5 | 1567 | &file_priv->mm.request_list); |
1c25595f | 1568 | spin_unlock(&file_priv->mm.lock); |
b962442e | 1569 | } |
673a394b | 1570 | |
5391d0cf | 1571 | ring->outstanding_lazy_request = 0; |
db53a302 | 1572 | |
f65d9421 | 1573 | if (!dev_priv->mm.suspended) { |
3e0dc6b0 BW |
1574 | if (i915_enable_hangcheck) { |
1575 | mod_timer(&dev_priv->hangcheck_timer, | |
1576 | jiffies + | |
1577 | msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)); | |
1578 | } | |
f65d9421 | 1579 | if (was_empty) |
b3b079db CW |
1580 | queue_delayed_work(dev_priv->wq, |
1581 | &dev_priv->mm.retire_work, HZ); | |
f65d9421 | 1582 | } |
3cce469c | 1583 | return 0; |
673a394b EA |
1584 | } |
1585 | ||
f787a5f5 CW |
1586 | static inline void |
1587 | i915_gem_request_remove_from_client(struct drm_i915_gem_request *request) | |
673a394b | 1588 | { |
1c25595f | 1589 | struct drm_i915_file_private *file_priv = request->file_priv; |
673a394b | 1590 | |
1c25595f CW |
1591 | if (!file_priv) |
1592 | return; | |
1c5d22f7 | 1593 | |
1c25595f | 1594 | spin_lock(&file_priv->mm.lock); |
09bfa517 HRK |
1595 | if (request->file_priv) { |
1596 | list_del(&request->client_list); | |
1597 | request->file_priv = NULL; | |
1598 | } | |
1c25595f | 1599 | spin_unlock(&file_priv->mm.lock); |
673a394b | 1600 | } |
673a394b | 1601 | |
dfaae392 CW |
1602 | static void i915_gem_reset_ring_lists(struct drm_i915_private *dev_priv, |
1603 | struct intel_ring_buffer *ring) | |
9375e446 | 1604 | { |
dfaae392 CW |
1605 | while (!list_empty(&ring->request_list)) { |
1606 | struct drm_i915_gem_request *request; | |
673a394b | 1607 | |
dfaae392 CW |
1608 | request = list_first_entry(&ring->request_list, |
1609 | struct drm_i915_gem_request, | |
1610 | list); | |
de151cf6 | 1611 | |
dfaae392 | 1612 | list_del(&request->list); |
f787a5f5 | 1613 | i915_gem_request_remove_from_client(request); |
dfaae392 CW |
1614 | kfree(request); |
1615 | } | |
673a394b | 1616 | |
dfaae392 | 1617 | while (!list_empty(&ring->active_list)) { |
05394f39 | 1618 | struct drm_i915_gem_object *obj; |
9375e446 | 1619 | |
05394f39 CW |
1620 | obj = list_first_entry(&ring->active_list, |
1621 | struct drm_i915_gem_object, | |
1622 | ring_list); | |
9375e446 | 1623 | |
05394f39 CW |
1624 | obj->base.write_domain = 0; |
1625 | list_del_init(&obj->gpu_write_list); | |
1626 | i915_gem_object_move_to_inactive(obj); | |
673a394b EA |
1627 | } |
1628 | } | |
1629 | ||
312817a3 CW |
1630 | static void i915_gem_reset_fences(struct drm_device *dev) |
1631 | { | |
1632 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1633 | int i; | |
1634 | ||
4b9de737 | 1635 | for (i = 0; i < dev_priv->num_fence_regs; i++) { |
312817a3 | 1636 | struct drm_i915_fence_reg *reg = &dev_priv->fence_regs[i]; |
7d2cb39c CW |
1637 | struct drm_i915_gem_object *obj = reg->obj; |
1638 | ||
1639 | if (!obj) | |
1640 | continue; | |
1641 | ||
1642 | if (obj->tiling_mode) | |
1643 | i915_gem_release_mmap(obj); | |
1644 | ||
d9e86c0e CW |
1645 | reg->obj->fence_reg = I915_FENCE_REG_NONE; |
1646 | reg->obj->fenced_gpu_access = false; | |
1647 | reg->obj->last_fenced_seqno = 0; | |
1648 | reg->obj->last_fenced_ring = NULL; | |
1649 | i915_gem_clear_fence_reg(dev, reg); | |
312817a3 CW |
1650 | } |
1651 | } | |
1652 | ||
069efc1d | 1653 | void i915_gem_reset(struct drm_device *dev) |
673a394b | 1654 | { |
77f01230 | 1655 | struct drm_i915_private *dev_priv = dev->dev_private; |
05394f39 | 1656 | struct drm_i915_gem_object *obj; |
1ec14ad3 | 1657 | int i; |
673a394b | 1658 | |
1ec14ad3 CW |
1659 | for (i = 0; i < I915_NUM_RINGS; i++) |
1660 | i915_gem_reset_ring_lists(dev_priv, &dev_priv->ring[i]); | |
dfaae392 CW |
1661 | |
1662 | /* Remove anything from the flushing lists. The GPU cache is likely | |
1663 | * to be lost on reset along with the data, so simply move the | |
1664 | * lost bo to the inactive list. | |
1665 | */ | |
1666 | while (!list_empty(&dev_priv->mm.flushing_list)) { | |
0206e353 | 1667 | obj = list_first_entry(&dev_priv->mm.flushing_list, |
05394f39 CW |
1668 | struct drm_i915_gem_object, |
1669 | mm_list); | |
dfaae392 | 1670 | |
05394f39 CW |
1671 | obj->base.write_domain = 0; |
1672 | list_del_init(&obj->gpu_write_list); | |
1673 | i915_gem_object_move_to_inactive(obj); | |
dfaae392 CW |
1674 | } |
1675 | ||
1676 | /* Move everything out of the GPU domains to ensure we do any | |
1677 | * necessary invalidation upon reuse. | |
1678 | */ | |
05394f39 | 1679 | list_for_each_entry(obj, |
77f01230 | 1680 | &dev_priv->mm.inactive_list, |
69dc4987 | 1681 | mm_list) |
77f01230 | 1682 | { |
05394f39 | 1683 | obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS; |
77f01230 | 1684 | } |
069efc1d CW |
1685 | |
1686 | /* The fence registers are invalidated so clear them out */ | |
312817a3 | 1687 | i915_gem_reset_fences(dev); |
673a394b EA |
1688 | } |
1689 | ||
1690 | /** | |
1691 | * This function clears the request list as sequence numbers are passed. | |
1692 | */ | |
a71d8d94 | 1693 | void |
db53a302 | 1694 | i915_gem_retire_requests_ring(struct intel_ring_buffer *ring) |
673a394b | 1695 | { |
673a394b | 1696 | uint32_t seqno; |
1ec14ad3 | 1697 | int i; |
673a394b | 1698 | |
db53a302 | 1699 | if (list_empty(&ring->request_list)) |
6c0594a3 KW |
1700 | return; |
1701 | ||
db53a302 | 1702 | WARN_ON(i915_verify_lists(ring->dev)); |
673a394b | 1703 | |
78501eac | 1704 | seqno = ring->get_seqno(ring); |
1ec14ad3 | 1705 | |
076e2c0e | 1706 | for (i = 0; i < ARRAY_SIZE(ring->sync_seqno); i++) |
1ec14ad3 CW |
1707 | if (seqno >= ring->sync_seqno[i]) |
1708 | ring->sync_seqno[i] = 0; | |
1709 | ||
852835f3 | 1710 | while (!list_empty(&ring->request_list)) { |
673a394b | 1711 | struct drm_i915_gem_request *request; |
673a394b | 1712 | |
852835f3 | 1713 | request = list_first_entry(&ring->request_list, |
673a394b EA |
1714 | struct drm_i915_gem_request, |
1715 | list); | |
673a394b | 1716 | |
dfaae392 | 1717 | if (!i915_seqno_passed(seqno, request->seqno)) |
b84d5f0c CW |
1718 | break; |
1719 | ||
db53a302 | 1720 | trace_i915_gem_request_retire(ring, request->seqno); |
a71d8d94 CW |
1721 | /* We know the GPU must have read the request to have |
1722 | * sent us the seqno + interrupt, so use the position | |
1723 | * of tail of the request to update the last known position | |
1724 | * of the GPU head. | |
1725 | */ | |
1726 | ring->last_retired_head = request->tail; | |
b84d5f0c CW |
1727 | |
1728 | list_del(&request->list); | |
f787a5f5 | 1729 | i915_gem_request_remove_from_client(request); |
b84d5f0c CW |
1730 | kfree(request); |
1731 | } | |
673a394b | 1732 | |
b84d5f0c CW |
1733 | /* Move any buffers on the active list that are no longer referenced |
1734 | * by the ringbuffer to the flushing/inactive lists as appropriate. | |
1735 | */ | |
1736 | while (!list_empty(&ring->active_list)) { | |
05394f39 | 1737 | struct drm_i915_gem_object *obj; |
b84d5f0c | 1738 | |
0206e353 | 1739 | obj = list_first_entry(&ring->active_list, |
05394f39 CW |
1740 | struct drm_i915_gem_object, |
1741 | ring_list); | |
673a394b | 1742 | |
05394f39 | 1743 | if (!i915_seqno_passed(seqno, obj->last_rendering_seqno)) |
673a394b | 1744 | break; |
b84d5f0c | 1745 | |
05394f39 | 1746 | if (obj->base.write_domain != 0) |
b84d5f0c CW |
1747 | i915_gem_object_move_to_flushing(obj); |
1748 | else | |
1749 | i915_gem_object_move_to_inactive(obj); | |
673a394b | 1750 | } |
9d34e5db | 1751 | |
db53a302 CW |
1752 | if (unlikely(ring->trace_irq_seqno && |
1753 | i915_seqno_passed(seqno, ring->trace_irq_seqno))) { | |
1ec14ad3 | 1754 | ring->irq_put(ring); |
db53a302 | 1755 | ring->trace_irq_seqno = 0; |
9d34e5db | 1756 | } |
23bc5982 | 1757 | |
db53a302 | 1758 | WARN_ON(i915_verify_lists(ring->dev)); |
673a394b EA |
1759 | } |
1760 | ||
b09a1fec CW |
1761 | void |
1762 | i915_gem_retire_requests(struct drm_device *dev) | |
1763 | { | |
1764 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1ec14ad3 | 1765 | int i; |
b09a1fec | 1766 | |
be72615b | 1767 | if (!list_empty(&dev_priv->mm.deferred_free_list)) { |
05394f39 | 1768 | struct drm_i915_gem_object *obj, *next; |
be72615b CW |
1769 | |
1770 | /* We must be careful that during unbind() we do not | |
1771 | * accidentally infinitely recurse into retire requests. | |
1772 | * Currently: | |
1773 | * retire -> free -> unbind -> wait -> retire_ring | |
1774 | */ | |
05394f39 | 1775 | list_for_each_entry_safe(obj, next, |
be72615b | 1776 | &dev_priv->mm.deferred_free_list, |
69dc4987 | 1777 | mm_list) |
05394f39 | 1778 | i915_gem_free_object_tail(obj); |
be72615b CW |
1779 | } |
1780 | ||
1ec14ad3 | 1781 | for (i = 0; i < I915_NUM_RINGS; i++) |
db53a302 | 1782 | i915_gem_retire_requests_ring(&dev_priv->ring[i]); |
b09a1fec CW |
1783 | } |
1784 | ||
75ef9da2 | 1785 | static void |
673a394b EA |
1786 | i915_gem_retire_work_handler(struct work_struct *work) |
1787 | { | |
1788 | drm_i915_private_t *dev_priv; | |
1789 | struct drm_device *dev; | |
0a58705b CW |
1790 | bool idle; |
1791 | int i; | |
673a394b EA |
1792 | |
1793 | dev_priv = container_of(work, drm_i915_private_t, | |
1794 | mm.retire_work.work); | |
1795 | dev = dev_priv->dev; | |
1796 | ||
891b48cf CW |
1797 | /* Come back later if the device is busy... */ |
1798 | if (!mutex_trylock(&dev->struct_mutex)) { | |
1799 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ); | |
1800 | return; | |
1801 | } | |
1802 | ||
b09a1fec | 1803 | i915_gem_retire_requests(dev); |
d1b851fc | 1804 | |
0a58705b CW |
1805 | /* Send a periodic flush down the ring so we don't hold onto GEM |
1806 | * objects indefinitely. | |
1807 | */ | |
1808 | idle = true; | |
1809 | for (i = 0; i < I915_NUM_RINGS; i++) { | |
1810 | struct intel_ring_buffer *ring = &dev_priv->ring[i]; | |
1811 | ||
1812 | if (!list_empty(&ring->gpu_write_list)) { | |
1813 | struct drm_i915_gem_request *request; | |
1814 | int ret; | |
1815 | ||
db53a302 CW |
1816 | ret = i915_gem_flush_ring(ring, |
1817 | 0, I915_GEM_GPU_DOMAINS); | |
0a58705b CW |
1818 | request = kzalloc(sizeof(*request), GFP_KERNEL); |
1819 | if (ret || request == NULL || | |
db53a302 | 1820 | i915_add_request(ring, NULL, request)) |
0a58705b CW |
1821 | kfree(request); |
1822 | } | |
1823 | ||
1824 | idle &= list_empty(&ring->request_list); | |
1825 | } | |
1826 | ||
1827 | if (!dev_priv->mm.suspended && !idle) | |
9c9fe1f8 | 1828 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ); |
0a58705b | 1829 | |
673a394b EA |
1830 | mutex_unlock(&dev->struct_mutex); |
1831 | } | |
1832 | ||
db53a302 CW |
1833 | /** |
1834 | * Waits for a sequence number to be signaled, and cleans up the | |
1835 | * request and object lists appropriately for that event. | |
1836 | */ | |
5a5a0c64 | 1837 | int |
db53a302 | 1838 | i915_wait_request(struct intel_ring_buffer *ring, |
b93f9cf1 BW |
1839 | uint32_t seqno, |
1840 | bool do_retire) | |
673a394b | 1841 | { |
db53a302 | 1842 | drm_i915_private_t *dev_priv = ring->dev->dev_private; |
802c7eb6 | 1843 | u32 ier; |
673a394b EA |
1844 | int ret = 0; |
1845 | ||
1846 | BUG_ON(seqno == 0); | |
1847 | ||
d9bc7e9f CW |
1848 | if (atomic_read(&dev_priv->mm.wedged)) { |
1849 | struct completion *x = &dev_priv->error_completion; | |
1850 | bool recovery_complete; | |
1851 | unsigned long flags; | |
1852 | ||
1853 | /* Give the error handler a chance to run. */ | |
1854 | spin_lock_irqsave(&x->wait.lock, flags); | |
1855 | recovery_complete = x->done > 0; | |
1856 | spin_unlock_irqrestore(&x->wait.lock, flags); | |
1857 | ||
1858 | return recovery_complete ? -EIO : -EAGAIN; | |
1859 | } | |
30dbf0c0 | 1860 | |
5d97eb69 | 1861 | if (seqno == ring->outstanding_lazy_request) { |
3cce469c CW |
1862 | struct drm_i915_gem_request *request; |
1863 | ||
1864 | request = kzalloc(sizeof(*request), GFP_KERNEL); | |
1865 | if (request == NULL) | |
e35a41de | 1866 | return -ENOMEM; |
3cce469c | 1867 | |
db53a302 | 1868 | ret = i915_add_request(ring, NULL, request); |
3cce469c CW |
1869 | if (ret) { |
1870 | kfree(request); | |
1871 | return ret; | |
1872 | } | |
1873 | ||
1874 | seqno = request->seqno; | |
e35a41de | 1875 | } |
ffed1d09 | 1876 | |
78501eac | 1877 | if (!i915_seqno_passed(ring->get_seqno(ring), seqno)) { |
db53a302 | 1878 | if (HAS_PCH_SPLIT(ring->dev)) |
036a4a7d ZW |
1879 | ier = I915_READ(DEIER) | I915_READ(GTIER); |
1880 | else | |
1881 | ier = I915_READ(IER); | |
802c7eb6 JB |
1882 | if (!ier) { |
1883 | DRM_ERROR("something (likely vbetool) disabled " | |
1884 | "interrupts, re-enabling\n"); | |
f01c22fd CW |
1885 | ring->dev->driver->irq_preinstall(ring->dev); |
1886 | ring->dev->driver->irq_postinstall(ring->dev); | |
802c7eb6 JB |
1887 | } |
1888 | ||
db53a302 | 1889 | trace_i915_gem_request_wait_begin(ring, seqno); |
1c5d22f7 | 1890 | |
b2223497 | 1891 | ring->waiting_seqno = seqno; |
b13c2b96 | 1892 | if (ring->irq_get(ring)) { |
ce453d81 | 1893 | if (dev_priv->mm.interruptible) |
b13c2b96 CW |
1894 | ret = wait_event_interruptible(ring->irq_queue, |
1895 | i915_seqno_passed(ring->get_seqno(ring), seqno) | |
1896 | || atomic_read(&dev_priv->mm.wedged)); | |
1897 | else | |
1898 | wait_event(ring->irq_queue, | |
1899 | i915_seqno_passed(ring->get_seqno(ring), seqno) | |
1900 | || atomic_read(&dev_priv->mm.wedged)); | |
1901 | ||
1902 | ring->irq_put(ring); | |
e959b5db EA |
1903 | } else if (wait_for_atomic(i915_seqno_passed(ring->get_seqno(ring), |
1904 | seqno) || | |
1905 | atomic_read(&dev_priv->mm.wedged), 3000)) | |
b5ba177d | 1906 | ret = -EBUSY; |
b2223497 | 1907 | ring->waiting_seqno = 0; |
1c5d22f7 | 1908 | |
db53a302 | 1909 | trace_i915_gem_request_wait_end(ring, seqno); |
673a394b | 1910 | } |
ba1234d1 | 1911 | if (atomic_read(&dev_priv->mm.wedged)) |
30dbf0c0 | 1912 | ret = -EAGAIN; |
673a394b | 1913 | |
673a394b EA |
1914 | /* Directly dispatch request retiring. While we have the work queue |
1915 | * to handle this, the waiter on a request often wants an associated | |
1916 | * buffer to have made it to the inactive list, and we would need | |
1917 | * a separate wait queue to handle that. | |
1918 | */ | |
b93f9cf1 | 1919 | if (ret == 0 && do_retire) |
db53a302 | 1920 | i915_gem_retire_requests_ring(ring); |
673a394b EA |
1921 | |
1922 | return ret; | |
1923 | } | |
1924 | ||
673a394b EA |
1925 | /** |
1926 | * Ensures that all rendering to the object has completed and the object is | |
1927 | * safe to unbind from the GTT or access from the CPU. | |
1928 | */ | |
54cf91dc | 1929 | int |
ce453d81 | 1930 | i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj) |
673a394b | 1931 | { |
673a394b EA |
1932 | int ret; |
1933 | ||
e47c68e9 EA |
1934 | /* This function only exists to support waiting for existing rendering, |
1935 | * not for emitting required flushes. | |
673a394b | 1936 | */ |
05394f39 | 1937 | BUG_ON((obj->base.write_domain & I915_GEM_GPU_DOMAINS) != 0); |
673a394b EA |
1938 | |
1939 | /* If there is rendering queued on the buffer being evicted, wait for | |
1940 | * it. | |
1941 | */ | |
05394f39 | 1942 | if (obj->active) { |
b93f9cf1 BW |
1943 | ret = i915_wait_request(obj->ring, obj->last_rendering_seqno, |
1944 | true); | |
2cf34d7b | 1945 | if (ret) |
673a394b EA |
1946 | return ret; |
1947 | } | |
1948 | ||
1949 | return 0; | |
1950 | } | |
1951 | ||
b5ffc9bc CW |
1952 | static void i915_gem_object_finish_gtt(struct drm_i915_gem_object *obj) |
1953 | { | |
1954 | u32 old_write_domain, old_read_domains; | |
1955 | ||
b5ffc9bc CW |
1956 | /* Act a barrier for all accesses through the GTT */ |
1957 | mb(); | |
1958 | ||
1959 | /* Force a pagefault for domain tracking on next user access */ | |
1960 | i915_gem_release_mmap(obj); | |
1961 | ||
b97c3d9c KP |
1962 | if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0) |
1963 | return; | |
1964 | ||
b5ffc9bc CW |
1965 | old_read_domains = obj->base.read_domains; |
1966 | old_write_domain = obj->base.write_domain; | |
1967 | ||
1968 | obj->base.read_domains &= ~I915_GEM_DOMAIN_GTT; | |
1969 | obj->base.write_domain &= ~I915_GEM_DOMAIN_GTT; | |
1970 | ||
1971 | trace_i915_gem_object_change_domain(obj, | |
1972 | old_read_domains, | |
1973 | old_write_domain); | |
1974 | } | |
1975 | ||
673a394b EA |
1976 | /** |
1977 | * Unbinds an object from the GTT aperture. | |
1978 | */ | |
0f973f27 | 1979 | int |
05394f39 | 1980 | i915_gem_object_unbind(struct drm_i915_gem_object *obj) |
673a394b | 1981 | { |
7bddb01f | 1982 | drm_i915_private_t *dev_priv = obj->base.dev->dev_private; |
673a394b EA |
1983 | int ret = 0; |
1984 | ||
05394f39 | 1985 | if (obj->gtt_space == NULL) |
673a394b EA |
1986 | return 0; |
1987 | ||
05394f39 | 1988 | if (obj->pin_count != 0) { |
673a394b EA |
1989 | DRM_ERROR("Attempting to unbind pinned buffer\n"); |
1990 | return -EINVAL; | |
1991 | } | |
1992 | ||
a8198eea CW |
1993 | ret = i915_gem_object_finish_gpu(obj); |
1994 | if (ret == -ERESTARTSYS) | |
1995 | return ret; | |
1996 | /* Continue on if we fail due to EIO, the GPU is hung so we | |
1997 | * should be safe and we need to cleanup or else we might | |
1998 | * cause memory corruption through use-after-free. | |
1999 | */ | |
2000 | ||
b5ffc9bc | 2001 | i915_gem_object_finish_gtt(obj); |
5323fd04 | 2002 | |
673a394b EA |
2003 | /* Move the object to the CPU domain to ensure that |
2004 | * any possible CPU writes while it's not in the GTT | |
a8198eea | 2005 | * are flushed when we go to remap it. |
673a394b | 2006 | */ |
a8198eea CW |
2007 | if (ret == 0) |
2008 | ret = i915_gem_object_set_to_cpu_domain(obj, 1); | |
8dc1775d | 2009 | if (ret == -ERESTARTSYS) |
673a394b | 2010 | return ret; |
812ed492 | 2011 | if (ret) { |
a8198eea CW |
2012 | /* In the event of a disaster, abandon all caches and |
2013 | * hope for the best. | |
2014 | */ | |
812ed492 | 2015 | i915_gem_clflush_object(obj); |
05394f39 | 2016 | obj->base.read_domains = obj->base.write_domain = I915_GEM_DOMAIN_CPU; |
812ed492 | 2017 | } |
673a394b | 2018 | |
96b47b65 | 2019 | /* release the fence reg _after_ flushing */ |
d9e86c0e CW |
2020 | ret = i915_gem_object_put_fence(obj); |
2021 | if (ret == -ERESTARTSYS) | |
2022 | return ret; | |
96b47b65 | 2023 | |
db53a302 CW |
2024 | trace_i915_gem_object_unbind(obj); |
2025 | ||
74898d7e DV |
2026 | if (obj->has_global_gtt_mapping) |
2027 | i915_gem_gtt_unbind_object(obj); | |
7bddb01f DV |
2028 | if (obj->has_aliasing_ppgtt_mapping) { |
2029 | i915_ppgtt_unbind_object(dev_priv->mm.aliasing_ppgtt, obj); | |
2030 | obj->has_aliasing_ppgtt_mapping = 0; | |
2031 | } | |
74163907 | 2032 | i915_gem_gtt_finish_object(obj); |
7bddb01f | 2033 | |
e5281ccd | 2034 | i915_gem_object_put_pages_gtt(obj); |
673a394b | 2035 | |
6299f992 | 2036 | list_del_init(&obj->gtt_list); |
05394f39 | 2037 | list_del_init(&obj->mm_list); |
75e9e915 | 2038 | /* Avoid an unnecessary call to unbind on rebind. */ |
05394f39 | 2039 | obj->map_and_fenceable = true; |
673a394b | 2040 | |
05394f39 CW |
2041 | drm_mm_put_block(obj->gtt_space); |
2042 | obj->gtt_space = NULL; | |
2043 | obj->gtt_offset = 0; | |
673a394b | 2044 | |
05394f39 | 2045 | if (i915_gem_object_is_purgeable(obj)) |
963b4836 CW |
2046 | i915_gem_object_truncate(obj); |
2047 | ||
8dc1775d | 2048 | return ret; |
673a394b EA |
2049 | } |
2050 | ||
88241785 | 2051 | int |
db53a302 | 2052 | i915_gem_flush_ring(struct intel_ring_buffer *ring, |
54cf91dc CW |
2053 | uint32_t invalidate_domains, |
2054 | uint32_t flush_domains) | |
2055 | { | |
88241785 CW |
2056 | int ret; |
2057 | ||
36d527de CW |
2058 | if (((invalidate_domains | flush_domains) & I915_GEM_GPU_DOMAINS) == 0) |
2059 | return 0; | |
2060 | ||
db53a302 CW |
2061 | trace_i915_gem_ring_flush(ring, invalidate_domains, flush_domains); |
2062 | ||
88241785 CW |
2063 | ret = ring->flush(ring, invalidate_domains, flush_domains); |
2064 | if (ret) | |
2065 | return ret; | |
2066 | ||
36d527de CW |
2067 | if (flush_domains & I915_GEM_GPU_DOMAINS) |
2068 | i915_gem_process_flushing_list(ring, flush_domains); | |
2069 | ||
88241785 | 2070 | return 0; |
54cf91dc CW |
2071 | } |
2072 | ||
b93f9cf1 | 2073 | static int i915_ring_idle(struct intel_ring_buffer *ring, bool do_retire) |
a56ba56c | 2074 | { |
88241785 CW |
2075 | int ret; |
2076 | ||
395b70be | 2077 | if (list_empty(&ring->gpu_write_list) && list_empty(&ring->active_list)) |
64193406 CW |
2078 | return 0; |
2079 | ||
88241785 | 2080 | if (!list_empty(&ring->gpu_write_list)) { |
db53a302 | 2081 | ret = i915_gem_flush_ring(ring, |
0ac74c6b | 2082 | I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS); |
88241785 CW |
2083 | if (ret) |
2084 | return ret; | |
2085 | } | |
2086 | ||
b93f9cf1 BW |
2087 | return i915_wait_request(ring, i915_gem_next_request_seqno(ring), |
2088 | do_retire); | |
a56ba56c CW |
2089 | } |
2090 | ||
b93f9cf1 | 2091 | int i915_gpu_idle(struct drm_device *dev, bool do_retire) |
4df2faf4 DV |
2092 | { |
2093 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1ec14ad3 | 2094 | int ret, i; |
4df2faf4 | 2095 | |
4df2faf4 | 2096 | /* Flush everything onto the inactive list. */ |
1ec14ad3 | 2097 | for (i = 0; i < I915_NUM_RINGS; i++) { |
b93f9cf1 | 2098 | ret = i915_ring_idle(&dev_priv->ring[i], do_retire); |
1ec14ad3 CW |
2099 | if (ret) |
2100 | return ret; | |
2101 | } | |
4df2faf4 | 2102 | |
8a1a49f9 | 2103 | return 0; |
4df2faf4 DV |
2104 | } |
2105 | ||
c6642782 DV |
2106 | static int sandybridge_write_fence_reg(struct drm_i915_gem_object *obj, |
2107 | struct intel_ring_buffer *pipelined) | |
4e901fdc | 2108 | { |
05394f39 | 2109 | struct drm_device *dev = obj->base.dev; |
4e901fdc | 2110 | drm_i915_private_t *dev_priv = dev->dev_private; |
05394f39 CW |
2111 | u32 size = obj->gtt_space->size; |
2112 | int regnum = obj->fence_reg; | |
4e901fdc EA |
2113 | uint64_t val; |
2114 | ||
05394f39 | 2115 | val = (uint64_t)((obj->gtt_offset + size - 4096) & |
c6642782 | 2116 | 0xfffff000) << 32; |
05394f39 CW |
2117 | val |= obj->gtt_offset & 0xfffff000; |
2118 | val |= (uint64_t)((obj->stride / 128) - 1) << | |
4e901fdc EA |
2119 | SANDYBRIDGE_FENCE_PITCH_SHIFT; |
2120 | ||
05394f39 | 2121 | if (obj->tiling_mode == I915_TILING_Y) |
4e901fdc EA |
2122 | val |= 1 << I965_FENCE_TILING_Y_SHIFT; |
2123 | val |= I965_FENCE_REG_VALID; | |
2124 | ||
c6642782 DV |
2125 | if (pipelined) { |
2126 | int ret = intel_ring_begin(pipelined, 6); | |
2127 | if (ret) | |
2128 | return ret; | |
2129 | ||
2130 | intel_ring_emit(pipelined, MI_NOOP); | |
2131 | intel_ring_emit(pipelined, MI_LOAD_REGISTER_IMM(2)); | |
2132 | intel_ring_emit(pipelined, FENCE_REG_SANDYBRIDGE_0 + regnum*8); | |
2133 | intel_ring_emit(pipelined, (u32)val); | |
2134 | intel_ring_emit(pipelined, FENCE_REG_SANDYBRIDGE_0 + regnum*8 + 4); | |
2135 | intel_ring_emit(pipelined, (u32)(val >> 32)); | |
2136 | intel_ring_advance(pipelined); | |
2137 | } else | |
2138 | I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + regnum * 8, val); | |
2139 | ||
2140 | return 0; | |
4e901fdc EA |
2141 | } |
2142 | ||
c6642782 DV |
2143 | static int i965_write_fence_reg(struct drm_i915_gem_object *obj, |
2144 | struct intel_ring_buffer *pipelined) | |
de151cf6 | 2145 | { |
05394f39 | 2146 | struct drm_device *dev = obj->base.dev; |
de151cf6 | 2147 | drm_i915_private_t *dev_priv = dev->dev_private; |
05394f39 CW |
2148 | u32 size = obj->gtt_space->size; |
2149 | int regnum = obj->fence_reg; | |
de151cf6 JB |
2150 | uint64_t val; |
2151 | ||
05394f39 | 2152 | val = (uint64_t)((obj->gtt_offset + size - 4096) & |
de151cf6 | 2153 | 0xfffff000) << 32; |
05394f39 CW |
2154 | val |= obj->gtt_offset & 0xfffff000; |
2155 | val |= ((obj->stride / 128) - 1) << I965_FENCE_PITCH_SHIFT; | |
2156 | if (obj->tiling_mode == I915_TILING_Y) | |
de151cf6 JB |
2157 | val |= 1 << I965_FENCE_TILING_Y_SHIFT; |
2158 | val |= I965_FENCE_REG_VALID; | |
2159 | ||
c6642782 DV |
2160 | if (pipelined) { |
2161 | int ret = intel_ring_begin(pipelined, 6); | |
2162 | if (ret) | |
2163 | return ret; | |
2164 | ||
2165 | intel_ring_emit(pipelined, MI_NOOP); | |
2166 | intel_ring_emit(pipelined, MI_LOAD_REGISTER_IMM(2)); | |
2167 | intel_ring_emit(pipelined, FENCE_REG_965_0 + regnum*8); | |
2168 | intel_ring_emit(pipelined, (u32)val); | |
2169 | intel_ring_emit(pipelined, FENCE_REG_965_0 + regnum*8 + 4); | |
2170 | intel_ring_emit(pipelined, (u32)(val >> 32)); | |
2171 | intel_ring_advance(pipelined); | |
2172 | } else | |
2173 | I915_WRITE64(FENCE_REG_965_0 + regnum * 8, val); | |
2174 | ||
2175 | return 0; | |
de151cf6 JB |
2176 | } |
2177 | ||
c6642782 DV |
2178 | static int i915_write_fence_reg(struct drm_i915_gem_object *obj, |
2179 | struct intel_ring_buffer *pipelined) | |
de151cf6 | 2180 | { |
05394f39 | 2181 | struct drm_device *dev = obj->base.dev; |
de151cf6 | 2182 | drm_i915_private_t *dev_priv = dev->dev_private; |
05394f39 | 2183 | u32 size = obj->gtt_space->size; |
c6642782 | 2184 | u32 fence_reg, val, pitch_val; |
0f973f27 | 2185 | int tile_width; |
de151cf6 | 2186 | |
c6642782 DV |
2187 | if (WARN((obj->gtt_offset & ~I915_FENCE_START_MASK) || |
2188 | (size & -size) != size || | |
2189 | (obj->gtt_offset & (size - 1)), | |
2190 | "object 0x%08x [fenceable? %d] not 1M or pot-size (0x%08x) aligned\n", | |
2191 | obj->gtt_offset, obj->map_and_fenceable, size)) | |
2192 | return -EINVAL; | |
de151cf6 | 2193 | |
c6642782 | 2194 | if (obj->tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev)) |
0f973f27 | 2195 | tile_width = 128; |
de151cf6 | 2196 | else |
0f973f27 JB |
2197 | tile_width = 512; |
2198 | ||
2199 | /* Note: pitch better be a power of two tile widths */ | |
05394f39 | 2200 | pitch_val = obj->stride / tile_width; |
0f973f27 | 2201 | pitch_val = ffs(pitch_val) - 1; |
de151cf6 | 2202 | |
05394f39 CW |
2203 | val = obj->gtt_offset; |
2204 | if (obj->tiling_mode == I915_TILING_Y) | |
de151cf6 | 2205 | val |= 1 << I830_FENCE_TILING_Y_SHIFT; |
a00b10c3 | 2206 | val |= I915_FENCE_SIZE_BITS(size); |
de151cf6 JB |
2207 | val |= pitch_val << I830_FENCE_PITCH_SHIFT; |
2208 | val |= I830_FENCE_REG_VALID; | |
2209 | ||
05394f39 | 2210 | fence_reg = obj->fence_reg; |
a00b10c3 CW |
2211 | if (fence_reg < 8) |
2212 | fence_reg = FENCE_REG_830_0 + fence_reg * 4; | |
dc529a4f | 2213 | else |
a00b10c3 | 2214 | fence_reg = FENCE_REG_945_8 + (fence_reg - 8) * 4; |
c6642782 DV |
2215 | |
2216 | if (pipelined) { | |
2217 | int ret = intel_ring_begin(pipelined, 4); | |
2218 | if (ret) | |
2219 | return ret; | |
2220 | ||
2221 | intel_ring_emit(pipelined, MI_NOOP); | |
2222 | intel_ring_emit(pipelined, MI_LOAD_REGISTER_IMM(1)); | |
2223 | intel_ring_emit(pipelined, fence_reg); | |
2224 | intel_ring_emit(pipelined, val); | |
2225 | intel_ring_advance(pipelined); | |
2226 | } else | |
2227 | I915_WRITE(fence_reg, val); | |
2228 | ||
2229 | return 0; | |
de151cf6 JB |
2230 | } |
2231 | ||
c6642782 DV |
2232 | static int i830_write_fence_reg(struct drm_i915_gem_object *obj, |
2233 | struct intel_ring_buffer *pipelined) | |
de151cf6 | 2234 | { |
05394f39 | 2235 | struct drm_device *dev = obj->base.dev; |
de151cf6 | 2236 | drm_i915_private_t *dev_priv = dev->dev_private; |
05394f39 CW |
2237 | u32 size = obj->gtt_space->size; |
2238 | int regnum = obj->fence_reg; | |
de151cf6 JB |
2239 | uint32_t val; |
2240 | uint32_t pitch_val; | |
2241 | ||
c6642782 DV |
2242 | if (WARN((obj->gtt_offset & ~I830_FENCE_START_MASK) || |
2243 | (size & -size) != size || | |
2244 | (obj->gtt_offset & (size - 1)), | |
2245 | "object 0x%08x not 512K or pot-size 0x%08x aligned\n", | |
2246 | obj->gtt_offset, size)) | |
2247 | return -EINVAL; | |
de151cf6 | 2248 | |
05394f39 | 2249 | pitch_val = obj->stride / 128; |
e76a16de | 2250 | pitch_val = ffs(pitch_val) - 1; |
e76a16de | 2251 | |
05394f39 CW |
2252 | val = obj->gtt_offset; |
2253 | if (obj->tiling_mode == I915_TILING_Y) | |
de151cf6 | 2254 | val |= 1 << I830_FENCE_TILING_Y_SHIFT; |
c6642782 | 2255 | val |= I830_FENCE_SIZE_BITS(size); |
de151cf6 JB |
2256 | val |= pitch_val << I830_FENCE_PITCH_SHIFT; |
2257 | val |= I830_FENCE_REG_VALID; | |
2258 | ||
c6642782 DV |
2259 | if (pipelined) { |
2260 | int ret = intel_ring_begin(pipelined, 4); | |
2261 | if (ret) | |
2262 | return ret; | |
2263 | ||
2264 | intel_ring_emit(pipelined, MI_NOOP); | |
2265 | intel_ring_emit(pipelined, MI_LOAD_REGISTER_IMM(1)); | |
2266 | intel_ring_emit(pipelined, FENCE_REG_830_0 + regnum*4); | |
2267 | intel_ring_emit(pipelined, val); | |
2268 | intel_ring_advance(pipelined); | |
2269 | } else | |
2270 | I915_WRITE(FENCE_REG_830_0 + regnum * 4, val); | |
2271 | ||
2272 | return 0; | |
de151cf6 JB |
2273 | } |
2274 | ||
d9e86c0e CW |
2275 | static bool ring_passed_seqno(struct intel_ring_buffer *ring, u32 seqno) |
2276 | { | |
2277 | return i915_seqno_passed(ring->get_seqno(ring), seqno); | |
2278 | } | |
2279 | ||
2280 | static int | |
2281 | i915_gem_object_flush_fence(struct drm_i915_gem_object *obj, | |
ce453d81 | 2282 | struct intel_ring_buffer *pipelined) |
d9e86c0e CW |
2283 | { |
2284 | int ret; | |
2285 | ||
2286 | if (obj->fenced_gpu_access) { | |
88241785 | 2287 | if (obj->base.write_domain & I915_GEM_GPU_DOMAINS) { |
db53a302 | 2288 | ret = i915_gem_flush_ring(obj->last_fenced_ring, |
88241785 CW |
2289 | 0, obj->base.write_domain); |
2290 | if (ret) | |
2291 | return ret; | |
2292 | } | |
d9e86c0e CW |
2293 | |
2294 | obj->fenced_gpu_access = false; | |
2295 | } | |
2296 | ||
2297 | if (obj->last_fenced_seqno && pipelined != obj->last_fenced_ring) { | |
2298 | if (!ring_passed_seqno(obj->last_fenced_ring, | |
2299 | obj->last_fenced_seqno)) { | |
db53a302 | 2300 | ret = i915_wait_request(obj->last_fenced_ring, |
b93f9cf1 BW |
2301 | obj->last_fenced_seqno, |
2302 | true); | |
d9e86c0e CW |
2303 | if (ret) |
2304 | return ret; | |
2305 | } | |
2306 | ||
2307 | obj->last_fenced_seqno = 0; | |
2308 | obj->last_fenced_ring = NULL; | |
2309 | } | |
2310 | ||
63256ec5 CW |
2311 | /* Ensure that all CPU reads are completed before installing a fence |
2312 | * and all writes before removing the fence. | |
2313 | */ | |
2314 | if (obj->base.read_domains & I915_GEM_DOMAIN_GTT) | |
2315 | mb(); | |
2316 | ||
d9e86c0e CW |
2317 | return 0; |
2318 | } | |
2319 | ||
2320 | int | |
2321 | i915_gem_object_put_fence(struct drm_i915_gem_object *obj) | |
2322 | { | |
2323 | int ret; | |
2324 | ||
2325 | if (obj->tiling_mode) | |
2326 | i915_gem_release_mmap(obj); | |
2327 | ||
ce453d81 | 2328 | ret = i915_gem_object_flush_fence(obj, NULL); |
d9e86c0e CW |
2329 | if (ret) |
2330 | return ret; | |
2331 | ||
2332 | if (obj->fence_reg != I915_FENCE_REG_NONE) { | |
2333 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; | |
1690e1eb CW |
2334 | |
2335 | WARN_ON(dev_priv->fence_regs[obj->fence_reg].pin_count); | |
d9e86c0e CW |
2336 | i915_gem_clear_fence_reg(obj->base.dev, |
2337 | &dev_priv->fence_regs[obj->fence_reg]); | |
2338 | ||
2339 | obj->fence_reg = I915_FENCE_REG_NONE; | |
2340 | } | |
2341 | ||
2342 | return 0; | |
2343 | } | |
2344 | ||
2345 | static struct drm_i915_fence_reg * | |
2346 | i915_find_fence_reg(struct drm_device *dev, | |
2347 | struct intel_ring_buffer *pipelined) | |
ae3db24a | 2348 | { |
ae3db24a | 2349 | struct drm_i915_private *dev_priv = dev->dev_private; |
d9e86c0e CW |
2350 | struct drm_i915_fence_reg *reg, *first, *avail; |
2351 | int i; | |
ae3db24a DV |
2352 | |
2353 | /* First try to find a free reg */ | |
d9e86c0e | 2354 | avail = NULL; |
ae3db24a DV |
2355 | for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) { |
2356 | reg = &dev_priv->fence_regs[i]; | |
2357 | if (!reg->obj) | |
d9e86c0e | 2358 | return reg; |
ae3db24a | 2359 | |
1690e1eb | 2360 | if (!reg->pin_count) |
d9e86c0e | 2361 | avail = reg; |
ae3db24a DV |
2362 | } |
2363 | ||
d9e86c0e CW |
2364 | if (avail == NULL) |
2365 | return NULL; | |
ae3db24a DV |
2366 | |
2367 | /* None available, try to steal one or wait for a user to finish */ | |
d9e86c0e CW |
2368 | avail = first = NULL; |
2369 | list_for_each_entry(reg, &dev_priv->mm.fence_list, lru_list) { | |
1690e1eb | 2370 | if (reg->pin_count) |
ae3db24a DV |
2371 | continue; |
2372 | ||
d9e86c0e CW |
2373 | if (first == NULL) |
2374 | first = reg; | |
2375 | ||
2376 | if (!pipelined || | |
2377 | !reg->obj->last_fenced_ring || | |
2378 | reg->obj->last_fenced_ring == pipelined) { | |
2379 | avail = reg; | |
2380 | break; | |
2381 | } | |
ae3db24a DV |
2382 | } |
2383 | ||
d9e86c0e CW |
2384 | if (avail == NULL) |
2385 | avail = first; | |
ae3db24a | 2386 | |
a00b10c3 | 2387 | return avail; |
ae3db24a DV |
2388 | } |
2389 | ||
de151cf6 | 2390 | /** |
d9e86c0e | 2391 | * i915_gem_object_get_fence - set up a fence reg for an object |
de151cf6 | 2392 | * @obj: object to map through a fence reg |
d9e86c0e CW |
2393 | * @pipelined: ring on which to queue the change, or NULL for CPU access |
2394 | * @interruptible: must we wait uninterruptibly for the register to retire? | |
de151cf6 JB |
2395 | * |
2396 | * When mapping objects through the GTT, userspace wants to be able to write | |
2397 | * to them without having to worry about swizzling if the object is tiled. | |
2398 | * | |
2399 | * This function walks the fence regs looking for a free one for @obj, | |
2400 | * stealing one if it can't find any. | |
2401 | * | |
2402 | * It then sets up the reg based on the object's properties: address, pitch | |
2403 | * and tiling format. | |
2404 | */ | |
8c4b8c3f | 2405 | int |
d9e86c0e | 2406 | i915_gem_object_get_fence(struct drm_i915_gem_object *obj, |
ce453d81 | 2407 | struct intel_ring_buffer *pipelined) |
de151cf6 | 2408 | { |
05394f39 | 2409 | struct drm_device *dev = obj->base.dev; |
79e53945 | 2410 | struct drm_i915_private *dev_priv = dev->dev_private; |
d9e86c0e | 2411 | struct drm_i915_fence_reg *reg; |
ae3db24a | 2412 | int ret; |
de151cf6 | 2413 | |
6bda10d1 CW |
2414 | /* XXX disable pipelining. There are bugs. Shocking. */ |
2415 | pipelined = NULL; | |
2416 | ||
d9e86c0e | 2417 | /* Just update our place in the LRU if our fence is getting reused. */ |
05394f39 CW |
2418 | if (obj->fence_reg != I915_FENCE_REG_NONE) { |
2419 | reg = &dev_priv->fence_regs[obj->fence_reg]; | |
007cc8ac | 2420 | list_move_tail(®->lru_list, &dev_priv->mm.fence_list); |
d9e86c0e | 2421 | |
29c5a587 CW |
2422 | if (obj->tiling_changed) { |
2423 | ret = i915_gem_object_flush_fence(obj, pipelined); | |
2424 | if (ret) | |
2425 | return ret; | |
2426 | ||
2427 | if (!obj->fenced_gpu_access && !obj->last_fenced_seqno) | |
2428 | pipelined = NULL; | |
2429 | ||
2430 | if (pipelined) { | |
2431 | reg->setup_seqno = | |
2432 | i915_gem_next_request_seqno(pipelined); | |
2433 | obj->last_fenced_seqno = reg->setup_seqno; | |
2434 | obj->last_fenced_ring = pipelined; | |
2435 | } | |
2436 | ||
2437 | goto update; | |
2438 | } | |
d9e86c0e CW |
2439 | |
2440 | if (!pipelined) { | |
2441 | if (reg->setup_seqno) { | |
2442 | if (!ring_passed_seqno(obj->last_fenced_ring, | |
2443 | reg->setup_seqno)) { | |
db53a302 | 2444 | ret = i915_wait_request(obj->last_fenced_ring, |
b93f9cf1 BW |
2445 | reg->setup_seqno, |
2446 | true); | |
d9e86c0e CW |
2447 | if (ret) |
2448 | return ret; | |
2449 | } | |
2450 | ||
2451 | reg->setup_seqno = 0; | |
2452 | } | |
2453 | } else if (obj->last_fenced_ring && | |
2454 | obj->last_fenced_ring != pipelined) { | |
ce453d81 | 2455 | ret = i915_gem_object_flush_fence(obj, pipelined); |
d9e86c0e CW |
2456 | if (ret) |
2457 | return ret; | |
d9e86c0e CW |
2458 | } |
2459 | ||
a09ba7fa EA |
2460 | return 0; |
2461 | } | |
2462 | ||
d9e86c0e CW |
2463 | reg = i915_find_fence_reg(dev, pipelined); |
2464 | if (reg == NULL) | |
39965b37 | 2465 | return -EDEADLK; |
de151cf6 | 2466 | |
ce453d81 | 2467 | ret = i915_gem_object_flush_fence(obj, pipelined); |
d9e86c0e | 2468 | if (ret) |
ae3db24a | 2469 | return ret; |
de151cf6 | 2470 | |
d9e86c0e CW |
2471 | if (reg->obj) { |
2472 | struct drm_i915_gem_object *old = reg->obj; | |
2473 | ||
2474 | drm_gem_object_reference(&old->base); | |
2475 | ||
2476 | if (old->tiling_mode) | |
2477 | i915_gem_release_mmap(old); | |
2478 | ||
ce453d81 | 2479 | ret = i915_gem_object_flush_fence(old, pipelined); |
d9e86c0e CW |
2480 | if (ret) { |
2481 | drm_gem_object_unreference(&old->base); | |
2482 | return ret; | |
2483 | } | |
2484 | ||
2485 | if (old->last_fenced_seqno == 0 && obj->last_fenced_seqno == 0) | |
2486 | pipelined = NULL; | |
2487 | ||
2488 | old->fence_reg = I915_FENCE_REG_NONE; | |
2489 | old->last_fenced_ring = pipelined; | |
2490 | old->last_fenced_seqno = | |
db53a302 | 2491 | pipelined ? i915_gem_next_request_seqno(pipelined) : 0; |
d9e86c0e CW |
2492 | |
2493 | drm_gem_object_unreference(&old->base); | |
2494 | } else if (obj->last_fenced_seqno == 0) | |
2495 | pipelined = NULL; | |
a09ba7fa | 2496 | |
de151cf6 | 2497 | reg->obj = obj; |
d9e86c0e CW |
2498 | list_move_tail(®->lru_list, &dev_priv->mm.fence_list); |
2499 | obj->fence_reg = reg - dev_priv->fence_regs; | |
2500 | obj->last_fenced_ring = pipelined; | |
de151cf6 | 2501 | |
d9e86c0e | 2502 | reg->setup_seqno = |
db53a302 | 2503 | pipelined ? i915_gem_next_request_seqno(pipelined) : 0; |
d9e86c0e CW |
2504 | obj->last_fenced_seqno = reg->setup_seqno; |
2505 | ||
2506 | update: | |
2507 | obj->tiling_changed = false; | |
e259befd | 2508 | switch (INTEL_INFO(dev)->gen) { |
25aebfc3 | 2509 | case 7: |
e259befd | 2510 | case 6: |
c6642782 | 2511 | ret = sandybridge_write_fence_reg(obj, pipelined); |
e259befd CW |
2512 | break; |
2513 | case 5: | |
2514 | case 4: | |
c6642782 | 2515 | ret = i965_write_fence_reg(obj, pipelined); |
e259befd CW |
2516 | break; |
2517 | case 3: | |
c6642782 | 2518 | ret = i915_write_fence_reg(obj, pipelined); |
e259befd CW |
2519 | break; |
2520 | case 2: | |
c6642782 | 2521 | ret = i830_write_fence_reg(obj, pipelined); |
e259befd CW |
2522 | break; |
2523 | } | |
d9ddcb96 | 2524 | |
c6642782 | 2525 | return ret; |
de151cf6 JB |
2526 | } |
2527 | ||
2528 | /** | |
2529 | * i915_gem_clear_fence_reg - clear out fence register info | |
2530 | * @obj: object to clear | |
2531 | * | |
2532 | * Zeroes out the fence register itself and clears out the associated | |
05394f39 | 2533 | * data structures in dev_priv and obj. |
de151cf6 JB |
2534 | */ |
2535 | static void | |
d9e86c0e CW |
2536 | i915_gem_clear_fence_reg(struct drm_device *dev, |
2537 | struct drm_i915_fence_reg *reg) | |
de151cf6 | 2538 | { |
79e53945 | 2539 | drm_i915_private_t *dev_priv = dev->dev_private; |
d9e86c0e | 2540 | uint32_t fence_reg = reg - dev_priv->fence_regs; |
de151cf6 | 2541 | |
e259befd | 2542 | switch (INTEL_INFO(dev)->gen) { |
25aebfc3 | 2543 | case 7: |
e259befd | 2544 | case 6: |
d9e86c0e | 2545 | I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + fence_reg*8, 0); |
e259befd CW |
2546 | break; |
2547 | case 5: | |
2548 | case 4: | |
d9e86c0e | 2549 | I915_WRITE64(FENCE_REG_965_0 + fence_reg*8, 0); |
e259befd CW |
2550 | break; |
2551 | case 3: | |
d9e86c0e CW |
2552 | if (fence_reg >= 8) |
2553 | fence_reg = FENCE_REG_945_8 + (fence_reg - 8) * 4; | |
dc529a4f | 2554 | else |
e259befd | 2555 | case 2: |
d9e86c0e | 2556 | fence_reg = FENCE_REG_830_0 + fence_reg * 4; |
dc529a4f EA |
2557 | |
2558 | I915_WRITE(fence_reg, 0); | |
e259befd | 2559 | break; |
dc529a4f | 2560 | } |
de151cf6 | 2561 | |
007cc8ac | 2562 | list_del_init(®->lru_list); |
d9e86c0e CW |
2563 | reg->obj = NULL; |
2564 | reg->setup_seqno = 0; | |
1690e1eb | 2565 | reg->pin_count = 0; |
52dc7d32 CW |
2566 | } |
2567 | ||
673a394b EA |
2568 | /** |
2569 | * Finds free space in the GTT aperture and binds the object there. | |
2570 | */ | |
2571 | static int | |
05394f39 | 2572 | i915_gem_object_bind_to_gtt(struct drm_i915_gem_object *obj, |
920afa77 | 2573 | unsigned alignment, |
75e9e915 | 2574 | bool map_and_fenceable) |
673a394b | 2575 | { |
05394f39 | 2576 | struct drm_device *dev = obj->base.dev; |
673a394b | 2577 | drm_i915_private_t *dev_priv = dev->dev_private; |
673a394b | 2578 | struct drm_mm_node *free_space; |
a00b10c3 | 2579 | gfp_t gfpmask = __GFP_NORETRY | __GFP_NOWARN; |
5e783301 | 2580 | u32 size, fence_size, fence_alignment, unfenced_alignment; |
75e9e915 | 2581 | bool mappable, fenceable; |
07f73f69 | 2582 | int ret; |
673a394b | 2583 | |
05394f39 | 2584 | if (obj->madv != I915_MADV_WILLNEED) { |
3ef94daa CW |
2585 | DRM_ERROR("Attempting to bind a purgeable object\n"); |
2586 | return -EINVAL; | |
2587 | } | |
2588 | ||
e28f8711 CW |
2589 | fence_size = i915_gem_get_gtt_size(dev, |
2590 | obj->base.size, | |
2591 | obj->tiling_mode); | |
2592 | fence_alignment = i915_gem_get_gtt_alignment(dev, | |
2593 | obj->base.size, | |
2594 | obj->tiling_mode); | |
2595 | unfenced_alignment = | |
2596 | i915_gem_get_unfenced_gtt_alignment(dev, | |
2597 | obj->base.size, | |
2598 | obj->tiling_mode); | |
a00b10c3 | 2599 | |
673a394b | 2600 | if (alignment == 0) |
5e783301 DV |
2601 | alignment = map_and_fenceable ? fence_alignment : |
2602 | unfenced_alignment; | |
75e9e915 | 2603 | if (map_and_fenceable && alignment & (fence_alignment - 1)) { |
673a394b EA |
2604 | DRM_ERROR("Invalid object alignment requested %u\n", alignment); |
2605 | return -EINVAL; | |
2606 | } | |
2607 | ||
05394f39 | 2608 | size = map_and_fenceable ? fence_size : obj->base.size; |
a00b10c3 | 2609 | |
654fc607 CW |
2610 | /* If the object is bigger than the entire aperture, reject it early |
2611 | * before evicting everything in a vain attempt to find space. | |
2612 | */ | |
05394f39 | 2613 | if (obj->base.size > |
75e9e915 | 2614 | (map_and_fenceable ? dev_priv->mm.gtt_mappable_end : dev_priv->mm.gtt_total)) { |
654fc607 CW |
2615 | DRM_ERROR("Attempting to bind an object larger than the aperture\n"); |
2616 | return -E2BIG; | |
2617 | } | |
2618 | ||
673a394b | 2619 | search_free: |
75e9e915 | 2620 | if (map_and_fenceable) |
920afa77 DV |
2621 | free_space = |
2622 | drm_mm_search_free_in_range(&dev_priv->mm.gtt_space, | |
a00b10c3 | 2623 | size, alignment, 0, |
920afa77 DV |
2624 | dev_priv->mm.gtt_mappable_end, |
2625 | 0); | |
2626 | else | |
2627 | free_space = drm_mm_search_free(&dev_priv->mm.gtt_space, | |
a00b10c3 | 2628 | size, alignment, 0); |
920afa77 DV |
2629 | |
2630 | if (free_space != NULL) { | |
75e9e915 | 2631 | if (map_and_fenceable) |
05394f39 | 2632 | obj->gtt_space = |
920afa77 | 2633 | drm_mm_get_block_range_generic(free_space, |
a00b10c3 | 2634 | size, alignment, 0, |
920afa77 DV |
2635 | dev_priv->mm.gtt_mappable_end, |
2636 | 0); | |
2637 | else | |
05394f39 | 2638 | obj->gtt_space = |
a00b10c3 | 2639 | drm_mm_get_block(free_space, size, alignment); |
920afa77 | 2640 | } |
05394f39 | 2641 | if (obj->gtt_space == NULL) { |
673a394b EA |
2642 | /* If the gtt is empty and we're still having trouble |
2643 | * fitting our object in, we're out of memory. | |
2644 | */ | |
75e9e915 DV |
2645 | ret = i915_gem_evict_something(dev, size, alignment, |
2646 | map_and_fenceable); | |
9731129c | 2647 | if (ret) |
673a394b | 2648 | return ret; |
9731129c | 2649 | |
673a394b EA |
2650 | goto search_free; |
2651 | } | |
2652 | ||
e5281ccd | 2653 | ret = i915_gem_object_get_pages_gtt(obj, gfpmask); |
673a394b | 2654 | if (ret) { |
05394f39 CW |
2655 | drm_mm_put_block(obj->gtt_space); |
2656 | obj->gtt_space = NULL; | |
07f73f69 CW |
2657 | |
2658 | if (ret == -ENOMEM) { | |
809b6334 CW |
2659 | /* first try to reclaim some memory by clearing the GTT */ |
2660 | ret = i915_gem_evict_everything(dev, false); | |
07f73f69 | 2661 | if (ret) { |
07f73f69 | 2662 | /* now try to shrink everyone else */ |
4bdadb97 CW |
2663 | if (gfpmask) { |
2664 | gfpmask = 0; | |
2665 | goto search_free; | |
07f73f69 CW |
2666 | } |
2667 | ||
809b6334 | 2668 | return -ENOMEM; |
07f73f69 CW |
2669 | } |
2670 | ||
2671 | goto search_free; | |
2672 | } | |
2673 | ||
673a394b EA |
2674 | return ret; |
2675 | } | |
2676 | ||
74163907 | 2677 | ret = i915_gem_gtt_prepare_object(obj); |
7c2e6fdf | 2678 | if (ret) { |
e5281ccd | 2679 | i915_gem_object_put_pages_gtt(obj); |
05394f39 CW |
2680 | drm_mm_put_block(obj->gtt_space); |
2681 | obj->gtt_space = NULL; | |
07f73f69 | 2682 | |
809b6334 | 2683 | if (i915_gem_evict_everything(dev, false)) |
07f73f69 | 2684 | return ret; |
07f73f69 CW |
2685 | |
2686 | goto search_free; | |
673a394b | 2687 | } |
0ebb9829 DV |
2688 | |
2689 | if (!dev_priv->mm.aliasing_ppgtt) | |
2690 | i915_gem_gtt_bind_object(obj, obj->cache_level); | |
673a394b | 2691 | |
6299f992 | 2692 | list_add_tail(&obj->gtt_list, &dev_priv->mm.gtt_list); |
05394f39 | 2693 | list_add_tail(&obj->mm_list, &dev_priv->mm.inactive_list); |
bf1a1092 | 2694 | |
673a394b EA |
2695 | /* Assert that the object is not currently in any GPU domain. As it |
2696 | * wasn't in the GTT, there shouldn't be any way it could have been in | |
2697 | * a GPU cache | |
2698 | */ | |
05394f39 CW |
2699 | BUG_ON(obj->base.read_domains & I915_GEM_GPU_DOMAINS); |
2700 | BUG_ON(obj->base.write_domain & I915_GEM_GPU_DOMAINS); | |
673a394b | 2701 | |
6299f992 | 2702 | obj->gtt_offset = obj->gtt_space->start; |
1c5d22f7 | 2703 | |
75e9e915 | 2704 | fenceable = |
05394f39 | 2705 | obj->gtt_space->size == fence_size && |
0206e353 | 2706 | (obj->gtt_space->start & (fence_alignment - 1)) == 0; |
a00b10c3 | 2707 | |
75e9e915 | 2708 | mappable = |
05394f39 | 2709 | obj->gtt_offset + obj->base.size <= dev_priv->mm.gtt_mappable_end; |
a00b10c3 | 2710 | |
05394f39 | 2711 | obj->map_and_fenceable = mappable && fenceable; |
75e9e915 | 2712 | |
db53a302 | 2713 | trace_i915_gem_object_bind(obj, map_and_fenceable); |
673a394b EA |
2714 | return 0; |
2715 | } | |
2716 | ||
2717 | void | |
05394f39 | 2718 | i915_gem_clflush_object(struct drm_i915_gem_object *obj) |
673a394b | 2719 | { |
673a394b EA |
2720 | /* If we don't have a page list set up, then we're not pinned |
2721 | * to GPU, and we can ignore the cache flush because it'll happen | |
2722 | * again at bind time. | |
2723 | */ | |
05394f39 | 2724 | if (obj->pages == NULL) |
673a394b EA |
2725 | return; |
2726 | ||
9c23f7fc CW |
2727 | /* If the GPU is snooping the contents of the CPU cache, |
2728 | * we do not need to manually clear the CPU cache lines. However, | |
2729 | * the caches are only snooped when the render cache is | |
2730 | * flushed/invalidated. As we always have to emit invalidations | |
2731 | * and flushes when moving into and out of the RENDER domain, correct | |
2732 | * snooping behaviour occurs naturally as the result of our domain | |
2733 | * tracking. | |
2734 | */ | |
2735 | if (obj->cache_level != I915_CACHE_NONE) | |
2736 | return; | |
2737 | ||
1c5d22f7 | 2738 | trace_i915_gem_object_clflush(obj); |
cfa16a0d | 2739 | |
05394f39 | 2740 | drm_clflush_pages(obj->pages, obj->base.size / PAGE_SIZE); |
673a394b EA |
2741 | } |
2742 | ||
e47c68e9 | 2743 | /** Flushes any GPU write domain for the object if it's dirty. */ |
88241785 | 2744 | static int |
3619df03 | 2745 | i915_gem_object_flush_gpu_write_domain(struct drm_i915_gem_object *obj) |
e47c68e9 | 2746 | { |
05394f39 | 2747 | if ((obj->base.write_domain & I915_GEM_GPU_DOMAINS) == 0) |
88241785 | 2748 | return 0; |
e47c68e9 EA |
2749 | |
2750 | /* Queue the GPU write cache flushing we need. */ | |
db53a302 | 2751 | return i915_gem_flush_ring(obj->ring, 0, obj->base.write_domain); |
e47c68e9 EA |
2752 | } |
2753 | ||
2754 | /** Flushes the GTT write domain for the object if it's dirty. */ | |
2755 | static void | |
05394f39 | 2756 | i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj) |
e47c68e9 | 2757 | { |
1c5d22f7 CW |
2758 | uint32_t old_write_domain; |
2759 | ||
05394f39 | 2760 | if (obj->base.write_domain != I915_GEM_DOMAIN_GTT) |
e47c68e9 EA |
2761 | return; |
2762 | ||
63256ec5 | 2763 | /* No actual flushing is required for the GTT write domain. Writes |
e47c68e9 EA |
2764 | * to it immediately go to main memory as far as we know, so there's |
2765 | * no chipset flush. It also doesn't land in render cache. | |
63256ec5 CW |
2766 | * |
2767 | * However, we do have to enforce the order so that all writes through | |
2768 | * the GTT land before any writes to the device, such as updates to | |
2769 | * the GATT itself. | |
e47c68e9 | 2770 | */ |
63256ec5 CW |
2771 | wmb(); |
2772 | ||
05394f39 CW |
2773 | old_write_domain = obj->base.write_domain; |
2774 | obj->base.write_domain = 0; | |
1c5d22f7 CW |
2775 | |
2776 | trace_i915_gem_object_change_domain(obj, | |
05394f39 | 2777 | obj->base.read_domains, |
1c5d22f7 | 2778 | old_write_domain); |
e47c68e9 EA |
2779 | } |
2780 | ||
2781 | /** Flushes the CPU write domain for the object if it's dirty. */ | |
2782 | static void | |
05394f39 | 2783 | i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj) |
e47c68e9 | 2784 | { |
1c5d22f7 | 2785 | uint32_t old_write_domain; |
e47c68e9 | 2786 | |
05394f39 | 2787 | if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) |
e47c68e9 EA |
2788 | return; |
2789 | ||
2790 | i915_gem_clflush_object(obj); | |
40ce6575 | 2791 | intel_gtt_chipset_flush(); |
05394f39 CW |
2792 | old_write_domain = obj->base.write_domain; |
2793 | obj->base.write_domain = 0; | |
1c5d22f7 CW |
2794 | |
2795 | trace_i915_gem_object_change_domain(obj, | |
05394f39 | 2796 | obj->base.read_domains, |
1c5d22f7 | 2797 | old_write_domain); |
e47c68e9 EA |
2798 | } |
2799 | ||
2ef7eeaa EA |
2800 | /** |
2801 | * Moves a single object to the GTT read, and possibly write domain. | |
2802 | * | |
2803 | * This function returns when the move is complete, including waiting on | |
2804 | * flushes to occur. | |
2805 | */ | |
79e53945 | 2806 | int |
2021746e | 2807 | i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write) |
2ef7eeaa | 2808 | { |
1c5d22f7 | 2809 | uint32_t old_write_domain, old_read_domains; |
e47c68e9 | 2810 | int ret; |
2ef7eeaa | 2811 | |
02354392 | 2812 | /* Not valid to be called on unbound objects. */ |
05394f39 | 2813 | if (obj->gtt_space == NULL) |
02354392 EA |
2814 | return -EINVAL; |
2815 | ||
8d7e3de1 CW |
2816 | if (obj->base.write_domain == I915_GEM_DOMAIN_GTT) |
2817 | return 0; | |
2818 | ||
88241785 CW |
2819 | ret = i915_gem_object_flush_gpu_write_domain(obj); |
2820 | if (ret) | |
2821 | return ret; | |
2822 | ||
87ca9c8a | 2823 | if (obj->pending_gpu_write || write) { |
ce453d81 | 2824 | ret = i915_gem_object_wait_rendering(obj); |
87ca9c8a CW |
2825 | if (ret) |
2826 | return ret; | |
2827 | } | |
2dafb1e0 | 2828 | |
7213342d | 2829 | i915_gem_object_flush_cpu_write_domain(obj); |
1c5d22f7 | 2830 | |
05394f39 CW |
2831 | old_write_domain = obj->base.write_domain; |
2832 | old_read_domains = obj->base.read_domains; | |
1c5d22f7 | 2833 | |
e47c68e9 EA |
2834 | /* It should now be out of any other write domains, and we can update |
2835 | * the domain values for our changes. | |
2836 | */ | |
05394f39 CW |
2837 | BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) != 0); |
2838 | obj->base.read_domains |= I915_GEM_DOMAIN_GTT; | |
e47c68e9 | 2839 | if (write) { |
05394f39 CW |
2840 | obj->base.read_domains = I915_GEM_DOMAIN_GTT; |
2841 | obj->base.write_domain = I915_GEM_DOMAIN_GTT; | |
2842 | obj->dirty = 1; | |
2ef7eeaa EA |
2843 | } |
2844 | ||
1c5d22f7 CW |
2845 | trace_i915_gem_object_change_domain(obj, |
2846 | old_read_domains, | |
2847 | old_write_domain); | |
2848 | ||
e47c68e9 EA |
2849 | return 0; |
2850 | } | |
2851 | ||
e4ffd173 CW |
2852 | int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj, |
2853 | enum i915_cache_level cache_level) | |
2854 | { | |
7bddb01f DV |
2855 | struct drm_device *dev = obj->base.dev; |
2856 | drm_i915_private_t *dev_priv = dev->dev_private; | |
e4ffd173 CW |
2857 | int ret; |
2858 | ||
2859 | if (obj->cache_level == cache_level) | |
2860 | return 0; | |
2861 | ||
2862 | if (obj->pin_count) { | |
2863 | DRM_DEBUG("can not change the cache level of pinned objects\n"); | |
2864 | return -EBUSY; | |
2865 | } | |
2866 | ||
2867 | if (obj->gtt_space) { | |
2868 | ret = i915_gem_object_finish_gpu(obj); | |
2869 | if (ret) | |
2870 | return ret; | |
2871 | ||
2872 | i915_gem_object_finish_gtt(obj); | |
2873 | ||
2874 | /* Before SandyBridge, you could not use tiling or fence | |
2875 | * registers with snooped memory, so relinquish any fences | |
2876 | * currently pointing to our region in the aperture. | |
2877 | */ | |
2878 | if (INTEL_INFO(obj->base.dev)->gen < 6) { | |
2879 | ret = i915_gem_object_put_fence(obj); | |
2880 | if (ret) | |
2881 | return ret; | |
2882 | } | |
2883 | ||
74898d7e DV |
2884 | if (obj->has_global_gtt_mapping) |
2885 | i915_gem_gtt_bind_object(obj, cache_level); | |
7bddb01f DV |
2886 | if (obj->has_aliasing_ppgtt_mapping) |
2887 | i915_ppgtt_bind_object(dev_priv->mm.aliasing_ppgtt, | |
2888 | obj, cache_level); | |
e4ffd173 CW |
2889 | } |
2890 | ||
2891 | if (cache_level == I915_CACHE_NONE) { | |
2892 | u32 old_read_domains, old_write_domain; | |
2893 | ||
2894 | /* If we're coming from LLC cached, then we haven't | |
2895 | * actually been tracking whether the data is in the | |
2896 | * CPU cache or not, since we only allow one bit set | |
2897 | * in obj->write_domain and have been skipping the clflushes. | |
2898 | * Just set it to the CPU cache for now. | |
2899 | */ | |
2900 | WARN_ON(obj->base.write_domain & ~I915_GEM_DOMAIN_CPU); | |
2901 | WARN_ON(obj->base.read_domains & ~I915_GEM_DOMAIN_CPU); | |
2902 | ||
2903 | old_read_domains = obj->base.read_domains; | |
2904 | old_write_domain = obj->base.write_domain; | |
2905 | ||
2906 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; | |
2907 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; | |
2908 | ||
2909 | trace_i915_gem_object_change_domain(obj, | |
2910 | old_read_domains, | |
2911 | old_write_domain); | |
2912 | } | |
2913 | ||
2914 | obj->cache_level = cache_level; | |
2915 | return 0; | |
2916 | } | |
2917 | ||
b9241ea3 | 2918 | /* |
2da3b9b9 CW |
2919 | * Prepare buffer for display plane (scanout, cursors, etc). |
2920 | * Can be called from an uninterruptible phase (modesetting) and allows | |
2921 | * any flushes to be pipelined (for pageflips). | |
2922 | * | |
2923 | * For the display plane, we want to be in the GTT but out of any write | |
2924 | * domains. So in many ways this looks like set_to_gtt_domain() apart from the | |
2925 | * ability to pipeline the waits, pinning and any additional subtleties | |
2926 | * that may differentiate the display plane from ordinary buffers. | |
b9241ea3 ZW |
2927 | */ |
2928 | int | |
2da3b9b9 CW |
2929 | i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj, |
2930 | u32 alignment, | |
919926ae | 2931 | struct intel_ring_buffer *pipelined) |
b9241ea3 | 2932 | { |
2da3b9b9 | 2933 | u32 old_read_domains, old_write_domain; |
b9241ea3 ZW |
2934 | int ret; |
2935 | ||
88241785 CW |
2936 | ret = i915_gem_object_flush_gpu_write_domain(obj); |
2937 | if (ret) | |
2938 | return ret; | |
2939 | ||
0be73284 | 2940 | if (pipelined != obj->ring) { |
ce453d81 | 2941 | ret = i915_gem_object_wait_rendering(obj); |
f0b69efc | 2942 | if (ret == -ERESTARTSYS) |
b9241ea3 ZW |
2943 | return ret; |
2944 | } | |
2945 | ||
a7ef0640 EA |
2946 | /* The display engine is not coherent with the LLC cache on gen6. As |
2947 | * a result, we make sure that the pinning that is about to occur is | |
2948 | * done with uncached PTEs. This is lowest common denominator for all | |
2949 | * chipsets. | |
2950 | * | |
2951 | * However for gen6+, we could do better by using the GFDT bit instead | |
2952 | * of uncaching, which would allow us to flush all the LLC-cached data | |
2953 | * with that bit in the PTE to main memory with just one PIPE_CONTROL. | |
2954 | */ | |
2955 | ret = i915_gem_object_set_cache_level(obj, I915_CACHE_NONE); | |
2956 | if (ret) | |
2957 | return ret; | |
2958 | ||
2da3b9b9 CW |
2959 | /* As the user may map the buffer once pinned in the display plane |
2960 | * (e.g. libkms for the bootup splash), we have to ensure that we | |
2961 | * always use map_and_fenceable for all scanout buffers. | |
2962 | */ | |
2963 | ret = i915_gem_object_pin(obj, alignment, true); | |
2964 | if (ret) | |
2965 | return ret; | |
2966 | ||
b118c1e3 CW |
2967 | i915_gem_object_flush_cpu_write_domain(obj); |
2968 | ||
2da3b9b9 | 2969 | old_write_domain = obj->base.write_domain; |
05394f39 | 2970 | old_read_domains = obj->base.read_domains; |
2da3b9b9 CW |
2971 | |
2972 | /* It should now be out of any other write domains, and we can update | |
2973 | * the domain values for our changes. | |
2974 | */ | |
2975 | BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) != 0); | |
05394f39 | 2976 | obj->base.read_domains |= I915_GEM_DOMAIN_GTT; |
b9241ea3 ZW |
2977 | |
2978 | trace_i915_gem_object_change_domain(obj, | |
2979 | old_read_domains, | |
2da3b9b9 | 2980 | old_write_domain); |
b9241ea3 ZW |
2981 | |
2982 | return 0; | |
2983 | } | |
2984 | ||
85345517 | 2985 | int |
a8198eea | 2986 | i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj) |
85345517 | 2987 | { |
88241785 CW |
2988 | int ret; |
2989 | ||
a8198eea | 2990 | if ((obj->base.read_domains & I915_GEM_GPU_DOMAINS) == 0) |
85345517 CW |
2991 | return 0; |
2992 | ||
88241785 | 2993 | if (obj->base.write_domain & I915_GEM_GPU_DOMAINS) { |
db53a302 | 2994 | ret = i915_gem_flush_ring(obj->ring, 0, obj->base.write_domain); |
88241785 CW |
2995 | if (ret) |
2996 | return ret; | |
2997 | } | |
85345517 | 2998 | |
c501ae7f CW |
2999 | ret = i915_gem_object_wait_rendering(obj); |
3000 | if (ret) | |
3001 | return ret; | |
3002 | ||
a8198eea CW |
3003 | /* Ensure that we invalidate the GPU's caches and TLBs. */ |
3004 | obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS; | |
c501ae7f | 3005 | return 0; |
85345517 CW |
3006 | } |
3007 | ||
e47c68e9 EA |
3008 | /** |
3009 | * Moves a single object to the CPU read, and possibly write domain. | |
3010 | * | |
3011 | * This function returns when the move is complete, including waiting on | |
3012 | * flushes to occur. | |
3013 | */ | |
dabdfe02 | 3014 | int |
919926ae | 3015 | i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write) |
e47c68e9 | 3016 | { |
1c5d22f7 | 3017 | uint32_t old_write_domain, old_read_domains; |
e47c68e9 EA |
3018 | int ret; |
3019 | ||
8d7e3de1 CW |
3020 | if (obj->base.write_domain == I915_GEM_DOMAIN_CPU) |
3021 | return 0; | |
3022 | ||
88241785 CW |
3023 | ret = i915_gem_object_flush_gpu_write_domain(obj); |
3024 | if (ret) | |
3025 | return ret; | |
3026 | ||
ce453d81 | 3027 | ret = i915_gem_object_wait_rendering(obj); |
de18a29e | 3028 | if (ret) |
e47c68e9 | 3029 | return ret; |
2ef7eeaa | 3030 | |
e47c68e9 | 3031 | i915_gem_object_flush_gtt_write_domain(obj); |
2ef7eeaa | 3032 | |
e47c68e9 EA |
3033 | /* If we have a partially-valid cache of the object in the CPU, |
3034 | * finish invalidating it and free the per-page flags. | |
2ef7eeaa | 3035 | */ |
e47c68e9 | 3036 | i915_gem_object_set_to_full_cpu_read_domain(obj); |
2ef7eeaa | 3037 | |
05394f39 CW |
3038 | old_write_domain = obj->base.write_domain; |
3039 | old_read_domains = obj->base.read_domains; | |
1c5d22f7 | 3040 | |
e47c68e9 | 3041 | /* Flush the CPU cache if it's still invalid. */ |
05394f39 | 3042 | if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) { |
2ef7eeaa | 3043 | i915_gem_clflush_object(obj); |
2ef7eeaa | 3044 | |
05394f39 | 3045 | obj->base.read_domains |= I915_GEM_DOMAIN_CPU; |
2ef7eeaa EA |
3046 | } |
3047 | ||
3048 | /* It should now be out of any other write domains, and we can update | |
3049 | * the domain values for our changes. | |
3050 | */ | |
05394f39 | 3051 | BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) != 0); |
e47c68e9 EA |
3052 | |
3053 | /* If we're writing through the CPU, then the GPU read domains will | |
3054 | * need to be invalidated at next use. | |
3055 | */ | |
3056 | if (write) { | |
05394f39 CW |
3057 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; |
3058 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; | |
e47c68e9 | 3059 | } |
2ef7eeaa | 3060 | |
1c5d22f7 CW |
3061 | trace_i915_gem_object_change_domain(obj, |
3062 | old_read_domains, | |
3063 | old_write_domain); | |
3064 | ||
2ef7eeaa EA |
3065 | return 0; |
3066 | } | |
3067 | ||
673a394b | 3068 | /** |
e47c68e9 | 3069 | * Moves the object from a partially CPU read to a full one. |
673a394b | 3070 | * |
e47c68e9 EA |
3071 | * Note that this only resolves i915_gem_object_set_cpu_read_domain_range(), |
3072 | * and doesn't handle transitioning from !(read_domains & I915_GEM_DOMAIN_CPU). | |
673a394b | 3073 | */ |
e47c68e9 | 3074 | static void |
05394f39 | 3075 | i915_gem_object_set_to_full_cpu_read_domain(struct drm_i915_gem_object *obj) |
673a394b | 3076 | { |
05394f39 | 3077 | if (!obj->page_cpu_valid) |
e47c68e9 EA |
3078 | return; |
3079 | ||
3080 | /* If we're partially in the CPU read domain, finish moving it in. | |
3081 | */ | |
05394f39 | 3082 | if (obj->base.read_domains & I915_GEM_DOMAIN_CPU) { |
e47c68e9 EA |
3083 | int i; |
3084 | ||
05394f39 CW |
3085 | for (i = 0; i <= (obj->base.size - 1) / PAGE_SIZE; i++) { |
3086 | if (obj->page_cpu_valid[i]) | |
e47c68e9 | 3087 | continue; |
05394f39 | 3088 | drm_clflush_pages(obj->pages + i, 1); |
e47c68e9 | 3089 | } |
e47c68e9 EA |
3090 | } |
3091 | ||
3092 | /* Free the page_cpu_valid mappings which are now stale, whether | |
3093 | * or not we've got I915_GEM_DOMAIN_CPU. | |
3094 | */ | |
05394f39 CW |
3095 | kfree(obj->page_cpu_valid); |
3096 | obj->page_cpu_valid = NULL; | |
e47c68e9 EA |
3097 | } |
3098 | ||
3099 | /** | |
3100 | * Set the CPU read domain on a range of the object. | |
3101 | * | |
3102 | * The object ends up with I915_GEM_DOMAIN_CPU in its read flags although it's | |
3103 | * not entirely valid. The page_cpu_valid member of the object flags which | |
3104 | * pages have been flushed, and will be respected by | |
3105 | * i915_gem_object_set_to_cpu_domain() if it's called on to get a valid mapping | |
3106 | * of the whole object. | |
3107 | * | |
3108 | * This function returns when the move is complete, including waiting on | |
3109 | * flushes to occur. | |
3110 | */ | |
3111 | static int | |
05394f39 | 3112 | i915_gem_object_set_cpu_read_domain_range(struct drm_i915_gem_object *obj, |
e47c68e9 EA |
3113 | uint64_t offset, uint64_t size) |
3114 | { | |
1c5d22f7 | 3115 | uint32_t old_read_domains; |
e47c68e9 | 3116 | int i, ret; |
673a394b | 3117 | |
05394f39 | 3118 | if (offset == 0 && size == obj->base.size) |
e47c68e9 | 3119 | return i915_gem_object_set_to_cpu_domain(obj, 0); |
673a394b | 3120 | |
88241785 CW |
3121 | ret = i915_gem_object_flush_gpu_write_domain(obj); |
3122 | if (ret) | |
3123 | return ret; | |
3124 | ||
ce453d81 | 3125 | ret = i915_gem_object_wait_rendering(obj); |
de18a29e | 3126 | if (ret) |
6a47baa6 | 3127 | return ret; |
de18a29e | 3128 | |
e47c68e9 EA |
3129 | i915_gem_object_flush_gtt_write_domain(obj); |
3130 | ||
3131 | /* If we're already fully in the CPU read domain, we're done. */ | |
05394f39 CW |
3132 | if (obj->page_cpu_valid == NULL && |
3133 | (obj->base.read_domains & I915_GEM_DOMAIN_CPU) != 0) | |
e47c68e9 | 3134 | return 0; |
673a394b | 3135 | |
e47c68e9 EA |
3136 | /* Otherwise, create/clear the per-page CPU read domain flag if we're |
3137 | * newly adding I915_GEM_DOMAIN_CPU | |
3138 | */ | |
05394f39 CW |
3139 | if (obj->page_cpu_valid == NULL) { |
3140 | obj->page_cpu_valid = kzalloc(obj->base.size / PAGE_SIZE, | |
3141 | GFP_KERNEL); | |
3142 | if (obj->page_cpu_valid == NULL) | |
e47c68e9 | 3143 | return -ENOMEM; |
05394f39 CW |
3144 | } else if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) |
3145 | memset(obj->page_cpu_valid, 0, obj->base.size / PAGE_SIZE); | |
673a394b EA |
3146 | |
3147 | /* Flush the cache on any pages that are still invalid from the CPU's | |
3148 | * perspective. | |
3149 | */ | |
e47c68e9 EA |
3150 | for (i = offset / PAGE_SIZE; i <= (offset + size - 1) / PAGE_SIZE; |
3151 | i++) { | |
05394f39 | 3152 | if (obj->page_cpu_valid[i]) |
673a394b EA |
3153 | continue; |
3154 | ||
05394f39 | 3155 | drm_clflush_pages(obj->pages + i, 1); |
673a394b | 3156 | |
05394f39 | 3157 | obj->page_cpu_valid[i] = 1; |
673a394b EA |
3158 | } |
3159 | ||
e47c68e9 EA |
3160 | /* It should now be out of any other write domains, and we can update |
3161 | * the domain values for our changes. | |
3162 | */ | |
05394f39 | 3163 | BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) != 0); |
e47c68e9 | 3164 | |
05394f39 CW |
3165 | old_read_domains = obj->base.read_domains; |
3166 | obj->base.read_domains |= I915_GEM_DOMAIN_CPU; | |
e47c68e9 | 3167 | |
1c5d22f7 CW |
3168 | trace_i915_gem_object_change_domain(obj, |
3169 | old_read_domains, | |
05394f39 | 3170 | obj->base.write_domain); |
1c5d22f7 | 3171 | |
673a394b EA |
3172 | return 0; |
3173 | } | |
3174 | ||
673a394b EA |
3175 | /* Throttle our rendering by waiting until the ring has completed our requests |
3176 | * emitted over 20 msec ago. | |
3177 | * | |
b962442e EA |
3178 | * Note that if we were to use the current jiffies each time around the loop, |
3179 | * we wouldn't escape the function with any frames outstanding if the time to | |
3180 | * render a frame was over 20ms. | |
3181 | * | |
673a394b EA |
3182 | * This should get us reasonable parallelism between CPU and GPU but also |
3183 | * relatively low latency when blocking on a particular request to finish. | |
3184 | */ | |
40a5f0de | 3185 | static int |
f787a5f5 | 3186 | i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file) |
40a5f0de | 3187 | { |
f787a5f5 CW |
3188 | struct drm_i915_private *dev_priv = dev->dev_private; |
3189 | struct drm_i915_file_private *file_priv = file->driver_priv; | |
b962442e | 3190 | unsigned long recent_enough = jiffies - msecs_to_jiffies(20); |
f787a5f5 CW |
3191 | struct drm_i915_gem_request *request; |
3192 | struct intel_ring_buffer *ring = NULL; | |
3193 | u32 seqno = 0; | |
3194 | int ret; | |
93533c29 | 3195 | |
e110e8d6 CW |
3196 | if (atomic_read(&dev_priv->mm.wedged)) |
3197 | return -EIO; | |
3198 | ||
1c25595f | 3199 | spin_lock(&file_priv->mm.lock); |
f787a5f5 | 3200 | list_for_each_entry(request, &file_priv->mm.request_list, client_list) { |
b962442e EA |
3201 | if (time_after_eq(request->emitted_jiffies, recent_enough)) |
3202 | break; | |
40a5f0de | 3203 | |
f787a5f5 CW |
3204 | ring = request->ring; |
3205 | seqno = request->seqno; | |
b962442e | 3206 | } |
1c25595f | 3207 | spin_unlock(&file_priv->mm.lock); |
40a5f0de | 3208 | |
f787a5f5 CW |
3209 | if (seqno == 0) |
3210 | return 0; | |
2bc43b5c | 3211 | |
f787a5f5 | 3212 | ret = 0; |
78501eac | 3213 | if (!i915_seqno_passed(ring->get_seqno(ring), seqno)) { |
f787a5f5 CW |
3214 | /* And wait for the seqno passing without holding any locks and |
3215 | * causing extra latency for others. This is safe as the irq | |
3216 | * generation is designed to be run atomically and so is | |
3217 | * lockless. | |
3218 | */ | |
b13c2b96 CW |
3219 | if (ring->irq_get(ring)) { |
3220 | ret = wait_event_interruptible(ring->irq_queue, | |
3221 | i915_seqno_passed(ring->get_seqno(ring), seqno) | |
3222 | || atomic_read(&dev_priv->mm.wedged)); | |
3223 | ring->irq_put(ring); | |
40a5f0de | 3224 | |
b13c2b96 CW |
3225 | if (ret == 0 && atomic_read(&dev_priv->mm.wedged)) |
3226 | ret = -EIO; | |
e959b5db EA |
3227 | } else if (wait_for_atomic(i915_seqno_passed(ring->get_seqno(ring), |
3228 | seqno) || | |
7ea29b13 EA |
3229 | atomic_read(&dev_priv->mm.wedged), 3000)) { |
3230 | ret = -EBUSY; | |
b13c2b96 | 3231 | } |
40a5f0de EA |
3232 | } |
3233 | ||
f787a5f5 CW |
3234 | if (ret == 0) |
3235 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, 0); | |
40a5f0de EA |
3236 | |
3237 | return ret; | |
3238 | } | |
3239 | ||
673a394b | 3240 | int |
05394f39 CW |
3241 | i915_gem_object_pin(struct drm_i915_gem_object *obj, |
3242 | uint32_t alignment, | |
75e9e915 | 3243 | bool map_and_fenceable) |
673a394b | 3244 | { |
05394f39 | 3245 | struct drm_device *dev = obj->base.dev; |
f13d3f73 | 3246 | struct drm_i915_private *dev_priv = dev->dev_private; |
673a394b EA |
3247 | int ret; |
3248 | ||
05394f39 | 3249 | BUG_ON(obj->pin_count == DRM_I915_GEM_OBJECT_MAX_PIN_COUNT); |
23bc5982 | 3250 | WARN_ON(i915_verify_lists(dev)); |
ac0c6b5a | 3251 | |
05394f39 CW |
3252 | if (obj->gtt_space != NULL) { |
3253 | if ((alignment && obj->gtt_offset & (alignment - 1)) || | |
3254 | (map_and_fenceable && !obj->map_and_fenceable)) { | |
3255 | WARN(obj->pin_count, | |
ae7d49d8 | 3256 | "bo is already pinned with incorrect alignment:" |
75e9e915 DV |
3257 | " offset=%x, req.alignment=%x, req.map_and_fenceable=%d," |
3258 | " obj->map_and_fenceable=%d\n", | |
05394f39 | 3259 | obj->gtt_offset, alignment, |
75e9e915 | 3260 | map_and_fenceable, |
05394f39 | 3261 | obj->map_and_fenceable); |
ac0c6b5a CW |
3262 | ret = i915_gem_object_unbind(obj); |
3263 | if (ret) | |
3264 | return ret; | |
3265 | } | |
3266 | } | |
3267 | ||
05394f39 | 3268 | if (obj->gtt_space == NULL) { |
a00b10c3 | 3269 | ret = i915_gem_object_bind_to_gtt(obj, alignment, |
75e9e915 | 3270 | map_and_fenceable); |
9731129c | 3271 | if (ret) |
673a394b | 3272 | return ret; |
22c344e9 | 3273 | } |
76446cac | 3274 | |
74898d7e DV |
3275 | if (!obj->has_global_gtt_mapping && map_and_fenceable) |
3276 | i915_gem_gtt_bind_object(obj, obj->cache_level); | |
3277 | ||
05394f39 | 3278 | if (obj->pin_count++ == 0) { |
05394f39 CW |
3279 | if (!obj->active) |
3280 | list_move_tail(&obj->mm_list, | |
f13d3f73 | 3281 | &dev_priv->mm.pinned_list); |
673a394b | 3282 | } |
6299f992 | 3283 | obj->pin_mappable |= map_and_fenceable; |
673a394b | 3284 | |
23bc5982 | 3285 | WARN_ON(i915_verify_lists(dev)); |
673a394b EA |
3286 | return 0; |
3287 | } | |
3288 | ||
3289 | void | |
05394f39 | 3290 | i915_gem_object_unpin(struct drm_i915_gem_object *obj) |
673a394b | 3291 | { |
05394f39 | 3292 | struct drm_device *dev = obj->base.dev; |
673a394b | 3293 | drm_i915_private_t *dev_priv = dev->dev_private; |
673a394b | 3294 | |
23bc5982 | 3295 | WARN_ON(i915_verify_lists(dev)); |
05394f39 CW |
3296 | BUG_ON(obj->pin_count == 0); |
3297 | BUG_ON(obj->gtt_space == NULL); | |
673a394b | 3298 | |
05394f39 CW |
3299 | if (--obj->pin_count == 0) { |
3300 | if (!obj->active) | |
3301 | list_move_tail(&obj->mm_list, | |
673a394b | 3302 | &dev_priv->mm.inactive_list); |
6299f992 | 3303 | obj->pin_mappable = false; |
673a394b | 3304 | } |
23bc5982 | 3305 | WARN_ON(i915_verify_lists(dev)); |
673a394b EA |
3306 | } |
3307 | ||
3308 | int | |
3309 | i915_gem_pin_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 3310 | struct drm_file *file) |
673a394b EA |
3311 | { |
3312 | struct drm_i915_gem_pin *args = data; | |
05394f39 | 3313 | struct drm_i915_gem_object *obj; |
673a394b EA |
3314 | int ret; |
3315 | ||
1d7cfea1 CW |
3316 | ret = i915_mutex_lock_interruptible(dev); |
3317 | if (ret) | |
3318 | return ret; | |
673a394b | 3319 | |
05394f39 | 3320 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 3321 | if (&obj->base == NULL) { |
1d7cfea1 CW |
3322 | ret = -ENOENT; |
3323 | goto unlock; | |
673a394b | 3324 | } |
673a394b | 3325 | |
05394f39 | 3326 | if (obj->madv != I915_MADV_WILLNEED) { |
bb6baf76 | 3327 | DRM_ERROR("Attempting to pin a purgeable buffer\n"); |
1d7cfea1 CW |
3328 | ret = -EINVAL; |
3329 | goto out; | |
3ef94daa CW |
3330 | } |
3331 | ||
05394f39 | 3332 | if (obj->pin_filp != NULL && obj->pin_filp != file) { |
79e53945 JB |
3333 | DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n", |
3334 | args->handle); | |
1d7cfea1 CW |
3335 | ret = -EINVAL; |
3336 | goto out; | |
79e53945 JB |
3337 | } |
3338 | ||
05394f39 CW |
3339 | obj->user_pin_count++; |
3340 | obj->pin_filp = file; | |
3341 | if (obj->user_pin_count == 1) { | |
75e9e915 | 3342 | ret = i915_gem_object_pin(obj, args->alignment, true); |
1d7cfea1 CW |
3343 | if (ret) |
3344 | goto out; | |
673a394b EA |
3345 | } |
3346 | ||
3347 | /* XXX - flush the CPU caches for pinned objects | |
3348 | * as the X server doesn't manage domains yet | |
3349 | */ | |
e47c68e9 | 3350 | i915_gem_object_flush_cpu_write_domain(obj); |
05394f39 | 3351 | args->offset = obj->gtt_offset; |
1d7cfea1 | 3352 | out: |
05394f39 | 3353 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 3354 | unlock: |
673a394b | 3355 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 3356 | return ret; |
673a394b EA |
3357 | } |
3358 | ||
3359 | int | |
3360 | i915_gem_unpin_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 3361 | struct drm_file *file) |
673a394b EA |
3362 | { |
3363 | struct drm_i915_gem_pin *args = data; | |
05394f39 | 3364 | struct drm_i915_gem_object *obj; |
76c1dec1 | 3365 | int ret; |
673a394b | 3366 | |
1d7cfea1 CW |
3367 | ret = i915_mutex_lock_interruptible(dev); |
3368 | if (ret) | |
3369 | return ret; | |
673a394b | 3370 | |
05394f39 | 3371 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 3372 | if (&obj->base == NULL) { |
1d7cfea1 CW |
3373 | ret = -ENOENT; |
3374 | goto unlock; | |
673a394b | 3375 | } |
76c1dec1 | 3376 | |
05394f39 | 3377 | if (obj->pin_filp != file) { |
79e53945 JB |
3378 | DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n", |
3379 | args->handle); | |
1d7cfea1 CW |
3380 | ret = -EINVAL; |
3381 | goto out; | |
79e53945 | 3382 | } |
05394f39 CW |
3383 | obj->user_pin_count--; |
3384 | if (obj->user_pin_count == 0) { | |
3385 | obj->pin_filp = NULL; | |
79e53945 JB |
3386 | i915_gem_object_unpin(obj); |
3387 | } | |
673a394b | 3388 | |
1d7cfea1 | 3389 | out: |
05394f39 | 3390 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 3391 | unlock: |
673a394b | 3392 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 3393 | return ret; |
673a394b EA |
3394 | } |
3395 | ||
3396 | int | |
3397 | i915_gem_busy_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 3398 | struct drm_file *file) |
673a394b EA |
3399 | { |
3400 | struct drm_i915_gem_busy *args = data; | |
05394f39 | 3401 | struct drm_i915_gem_object *obj; |
30dbf0c0 CW |
3402 | int ret; |
3403 | ||
76c1dec1 | 3404 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 3405 | if (ret) |
76c1dec1 | 3406 | return ret; |
673a394b | 3407 | |
05394f39 | 3408 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 3409 | if (&obj->base == NULL) { |
1d7cfea1 CW |
3410 | ret = -ENOENT; |
3411 | goto unlock; | |
673a394b | 3412 | } |
d1b851fc | 3413 | |
0be555b6 CW |
3414 | /* Count all active objects as busy, even if they are currently not used |
3415 | * by the gpu. Users of this interface expect objects to eventually | |
3416 | * become non-busy without any further actions, therefore emit any | |
3417 | * necessary flushes here. | |
c4de0a5d | 3418 | */ |
05394f39 | 3419 | args->busy = obj->active; |
0be555b6 CW |
3420 | if (args->busy) { |
3421 | /* Unconditionally flush objects, even when the gpu still uses this | |
3422 | * object. Userspace calling this function indicates that it wants to | |
3423 | * use this buffer rather sooner than later, so issuing the required | |
3424 | * flush earlier is beneficial. | |
3425 | */ | |
1a1c6976 | 3426 | if (obj->base.write_domain & I915_GEM_GPU_DOMAINS) { |
db53a302 | 3427 | ret = i915_gem_flush_ring(obj->ring, |
88241785 | 3428 | 0, obj->base.write_domain); |
1a1c6976 CW |
3429 | } else if (obj->ring->outstanding_lazy_request == |
3430 | obj->last_rendering_seqno) { | |
3431 | struct drm_i915_gem_request *request; | |
3432 | ||
7a194876 CW |
3433 | /* This ring is not being cleared by active usage, |
3434 | * so emit a request to do so. | |
3435 | */ | |
1a1c6976 | 3436 | request = kzalloc(sizeof(*request), GFP_KERNEL); |
457eafce | 3437 | if (request) { |
0206e353 | 3438 | ret = i915_add_request(obj->ring, NULL, request); |
457eafce RM |
3439 | if (ret) |
3440 | kfree(request); | |
3441 | } else | |
7a194876 CW |
3442 | ret = -ENOMEM; |
3443 | } | |
0be555b6 CW |
3444 | |
3445 | /* Update the active list for the hardware's current position. | |
3446 | * Otherwise this only updates on a delayed timer or when irqs | |
3447 | * are actually unmasked, and our working set ends up being | |
3448 | * larger than required. | |
3449 | */ | |
db53a302 | 3450 | i915_gem_retire_requests_ring(obj->ring); |
0be555b6 | 3451 | |
05394f39 | 3452 | args->busy = obj->active; |
0be555b6 | 3453 | } |
673a394b | 3454 | |
05394f39 | 3455 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 3456 | unlock: |
673a394b | 3457 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 3458 | return ret; |
673a394b EA |
3459 | } |
3460 | ||
3461 | int | |
3462 | i915_gem_throttle_ioctl(struct drm_device *dev, void *data, | |
3463 | struct drm_file *file_priv) | |
3464 | { | |
0206e353 | 3465 | return i915_gem_ring_throttle(dev, file_priv); |
673a394b EA |
3466 | } |
3467 | ||
3ef94daa CW |
3468 | int |
3469 | i915_gem_madvise_ioctl(struct drm_device *dev, void *data, | |
3470 | struct drm_file *file_priv) | |
3471 | { | |
3472 | struct drm_i915_gem_madvise *args = data; | |
05394f39 | 3473 | struct drm_i915_gem_object *obj; |
76c1dec1 | 3474 | int ret; |
3ef94daa CW |
3475 | |
3476 | switch (args->madv) { | |
3477 | case I915_MADV_DONTNEED: | |
3478 | case I915_MADV_WILLNEED: | |
3479 | break; | |
3480 | default: | |
3481 | return -EINVAL; | |
3482 | } | |
3483 | ||
1d7cfea1 CW |
3484 | ret = i915_mutex_lock_interruptible(dev); |
3485 | if (ret) | |
3486 | return ret; | |
3487 | ||
05394f39 | 3488 | obj = to_intel_bo(drm_gem_object_lookup(dev, file_priv, args->handle)); |
c8725226 | 3489 | if (&obj->base == NULL) { |
1d7cfea1 CW |
3490 | ret = -ENOENT; |
3491 | goto unlock; | |
3ef94daa | 3492 | } |
3ef94daa | 3493 | |
05394f39 | 3494 | if (obj->pin_count) { |
1d7cfea1 CW |
3495 | ret = -EINVAL; |
3496 | goto out; | |
3ef94daa CW |
3497 | } |
3498 | ||
05394f39 CW |
3499 | if (obj->madv != __I915_MADV_PURGED) |
3500 | obj->madv = args->madv; | |
3ef94daa | 3501 | |
2d7ef395 | 3502 | /* if the object is no longer bound, discard its backing storage */ |
05394f39 CW |
3503 | if (i915_gem_object_is_purgeable(obj) && |
3504 | obj->gtt_space == NULL) | |
2d7ef395 CW |
3505 | i915_gem_object_truncate(obj); |
3506 | ||
05394f39 | 3507 | args->retained = obj->madv != __I915_MADV_PURGED; |
bb6baf76 | 3508 | |
1d7cfea1 | 3509 | out: |
05394f39 | 3510 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 3511 | unlock: |
3ef94daa | 3512 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 3513 | return ret; |
3ef94daa CW |
3514 | } |
3515 | ||
05394f39 CW |
3516 | struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev, |
3517 | size_t size) | |
ac52bc56 | 3518 | { |
73aa808f | 3519 | struct drm_i915_private *dev_priv = dev->dev_private; |
c397b908 | 3520 | struct drm_i915_gem_object *obj; |
5949eac4 | 3521 | struct address_space *mapping; |
ac52bc56 | 3522 | |
c397b908 DV |
3523 | obj = kzalloc(sizeof(*obj), GFP_KERNEL); |
3524 | if (obj == NULL) | |
3525 | return NULL; | |
673a394b | 3526 | |
c397b908 DV |
3527 | if (drm_gem_object_init(dev, &obj->base, size) != 0) { |
3528 | kfree(obj); | |
3529 | return NULL; | |
3530 | } | |
673a394b | 3531 | |
5949eac4 HD |
3532 | mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping; |
3533 | mapping_set_gfp_mask(mapping, GFP_HIGHUSER | __GFP_RECLAIMABLE); | |
3534 | ||
73aa808f CW |
3535 | i915_gem_info_add_obj(dev_priv, size); |
3536 | ||
c397b908 DV |
3537 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; |
3538 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; | |
673a394b | 3539 | |
3d29b842 ED |
3540 | if (HAS_LLC(dev)) { |
3541 | /* On some devices, we can have the GPU use the LLC (the CPU | |
a1871112 EA |
3542 | * cache) for about a 10% performance improvement |
3543 | * compared to uncached. Graphics requests other than | |
3544 | * display scanout are coherent with the CPU in | |
3545 | * accessing this cache. This means in this mode we | |
3546 | * don't need to clflush on the CPU side, and on the | |
3547 | * GPU side we only need to flush internal caches to | |
3548 | * get data visible to the CPU. | |
3549 | * | |
3550 | * However, we maintain the display planes as UC, and so | |
3551 | * need to rebind when first used as such. | |
3552 | */ | |
3553 | obj->cache_level = I915_CACHE_LLC; | |
3554 | } else | |
3555 | obj->cache_level = I915_CACHE_NONE; | |
3556 | ||
62b8b215 | 3557 | obj->base.driver_private = NULL; |
c397b908 | 3558 | obj->fence_reg = I915_FENCE_REG_NONE; |
69dc4987 | 3559 | INIT_LIST_HEAD(&obj->mm_list); |
93a37f20 | 3560 | INIT_LIST_HEAD(&obj->gtt_list); |
69dc4987 | 3561 | INIT_LIST_HEAD(&obj->ring_list); |
432e58ed | 3562 | INIT_LIST_HEAD(&obj->exec_list); |
c397b908 | 3563 | INIT_LIST_HEAD(&obj->gpu_write_list); |
c397b908 | 3564 | obj->madv = I915_MADV_WILLNEED; |
75e9e915 DV |
3565 | /* Avoid an unnecessary call to unbind on the first bind. */ |
3566 | obj->map_and_fenceable = true; | |
de151cf6 | 3567 | |
05394f39 | 3568 | return obj; |
c397b908 DV |
3569 | } |
3570 | ||
3571 | int i915_gem_init_object(struct drm_gem_object *obj) | |
3572 | { | |
3573 | BUG(); | |
de151cf6 | 3574 | |
673a394b EA |
3575 | return 0; |
3576 | } | |
3577 | ||
05394f39 | 3578 | static void i915_gem_free_object_tail(struct drm_i915_gem_object *obj) |
673a394b | 3579 | { |
05394f39 | 3580 | struct drm_device *dev = obj->base.dev; |
be72615b | 3581 | drm_i915_private_t *dev_priv = dev->dev_private; |
be72615b | 3582 | int ret; |
673a394b | 3583 | |
be72615b CW |
3584 | ret = i915_gem_object_unbind(obj); |
3585 | if (ret == -ERESTARTSYS) { | |
05394f39 | 3586 | list_move(&obj->mm_list, |
be72615b CW |
3587 | &dev_priv->mm.deferred_free_list); |
3588 | return; | |
3589 | } | |
673a394b | 3590 | |
26e12f89 CW |
3591 | trace_i915_gem_object_destroy(obj); |
3592 | ||
05394f39 | 3593 | if (obj->base.map_list.map) |
b464e9a2 | 3594 | drm_gem_free_mmap_offset(&obj->base); |
de151cf6 | 3595 | |
05394f39 CW |
3596 | drm_gem_object_release(&obj->base); |
3597 | i915_gem_info_remove_obj(dev_priv, obj->base.size); | |
c397b908 | 3598 | |
05394f39 CW |
3599 | kfree(obj->page_cpu_valid); |
3600 | kfree(obj->bit_17); | |
3601 | kfree(obj); | |
673a394b EA |
3602 | } |
3603 | ||
05394f39 | 3604 | void i915_gem_free_object(struct drm_gem_object *gem_obj) |
be72615b | 3605 | { |
05394f39 CW |
3606 | struct drm_i915_gem_object *obj = to_intel_bo(gem_obj); |
3607 | struct drm_device *dev = obj->base.dev; | |
be72615b | 3608 | |
05394f39 | 3609 | while (obj->pin_count > 0) |
be72615b CW |
3610 | i915_gem_object_unpin(obj); |
3611 | ||
05394f39 | 3612 | if (obj->phys_obj) |
be72615b CW |
3613 | i915_gem_detach_phys_object(dev, obj); |
3614 | ||
3615 | i915_gem_free_object_tail(obj); | |
3616 | } | |
3617 | ||
29105ccc CW |
3618 | int |
3619 | i915_gem_idle(struct drm_device *dev) | |
3620 | { | |
3621 | drm_i915_private_t *dev_priv = dev->dev_private; | |
3622 | int ret; | |
28dfe52a | 3623 | |
29105ccc | 3624 | mutex_lock(&dev->struct_mutex); |
1c5d22f7 | 3625 | |
87acb0a5 | 3626 | if (dev_priv->mm.suspended) { |
29105ccc CW |
3627 | mutex_unlock(&dev->struct_mutex); |
3628 | return 0; | |
28dfe52a EA |
3629 | } |
3630 | ||
b93f9cf1 | 3631 | ret = i915_gpu_idle(dev, true); |
6dbe2772 KP |
3632 | if (ret) { |
3633 | mutex_unlock(&dev->struct_mutex); | |
673a394b | 3634 | return ret; |
6dbe2772 | 3635 | } |
673a394b | 3636 | |
29105ccc CW |
3637 | /* Under UMS, be paranoid and evict. */ |
3638 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) { | |
5eac3ab4 | 3639 | ret = i915_gem_evict_inactive(dev, false); |
29105ccc CW |
3640 | if (ret) { |
3641 | mutex_unlock(&dev->struct_mutex); | |
3642 | return ret; | |
3643 | } | |
3644 | } | |
3645 | ||
312817a3 CW |
3646 | i915_gem_reset_fences(dev); |
3647 | ||
29105ccc CW |
3648 | /* Hack! Don't let anybody do execbuf while we don't control the chip. |
3649 | * We need to replace this with a semaphore, or something. | |
3650 | * And not confound mm.suspended! | |
3651 | */ | |
3652 | dev_priv->mm.suspended = 1; | |
bc0c7f14 | 3653 | del_timer_sync(&dev_priv->hangcheck_timer); |
29105ccc CW |
3654 | |
3655 | i915_kernel_lost_context(dev); | |
6dbe2772 | 3656 | i915_gem_cleanup_ringbuffer(dev); |
29105ccc | 3657 | |
6dbe2772 KP |
3658 | mutex_unlock(&dev->struct_mutex); |
3659 | ||
29105ccc CW |
3660 | /* Cancel the retire work handler, which should be idle now. */ |
3661 | cancel_delayed_work_sync(&dev_priv->mm.retire_work); | |
3662 | ||
673a394b EA |
3663 | return 0; |
3664 | } | |
3665 | ||
f691e2f4 DV |
3666 | void i915_gem_init_swizzling(struct drm_device *dev) |
3667 | { | |
3668 | drm_i915_private_t *dev_priv = dev->dev_private; | |
3669 | ||
11782b02 | 3670 | if (INTEL_INFO(dev)->gen < 5 || |
f691e2f4 DV |
3671 | dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE) |
3672 | return; | |
3673 | ||
3674 | I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) | | |
3675 | DISP_TILE_SURFACE_SWIZZLING); | |
3676 | ||
11782b02 DV |
3677 | if (IS_GEN5(dev)) |
3678 | return; | |
3679 | ||
f691e2f4 DV |
3680 | I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_SWZCTL); |
3681 | if (IS_GEN6(dev)) | |
3682 | I915_WRITE(ARB_MODE, ARB_MODE_ENABLE(ARB_MODE_SWIZZLE_SNB)); | |
3683 | else | |
3684 | I915_WRITE(ARB_MODE, ARB_MODE_ENABLE(ARB_MODE_SWIZZLE_IVB)); | |
3685 | } | |
e21af88d DV |
3686 | |
3687 | void i915_gem_init_ppgtt(struct drm_device *dev) | |
3688 | { | |
3689 | drm_i915_private_t *dev_priv = dev->dev_private; | |
3690 | uint32_t pd_offset; | |
3691 | struct intel_ring_buffer *ring; | |
3692 | int i; | |
3693 | ||
3694 | if (!dev_priv->mm.aliasing_ppgtt) | |
3695 | return; | |
3696 | ||
3697 | pd_offset = dev_priv->mm.aliasing_ppgtt->pd_offset; | |
3698 | pd_offset /= 64; /* in cachelines, */ | |
3699 | pd_offset <<= 16; | |
3700 | ||
3701 | if (INTEL_INFO(dev)->gen == 6) { | |
3702 | uint32_t ecochk = I915_READ(GAM_ECOCHK); | |
3703 | I915_WRITE(GAM_ECOCHK, ecochk | ECOCHK_SNB_BIT | | |
3704 | ECOCHK_PPGTT_CACHE64B); | |
3705 | I915_WRITE(GFX_MODE, GFX_MODE_ENABLE(GFX_PPGTT_ENABLE)); | |
3706 | } else if (INTEL_INFO(dev)->gen >= 7) { | |
3707 | I915_WRITE(GAM_ECOCHK, ECOCHK_PPGTT_CACHE64B); | |
3708 | /* GFX_MODE is per-ring on gen7+ */ | |
3709 | } | |
3710 | ||
3711 | for (i = 0; i < I915_NUM_RINGS; i++) { | |
3712 | ring = &dev_priv->ring[i]; | |
3713 | ||
3714 | if (INTEL_INFO(dev)->gen >= 7) | |
3715 | I915_WRITE(RING_MODE_GEN7(ring), | |
3716 | GFX_MODE_ENABLE(GFX_PPGTT_ENABLE)); | |
3717 | ||
3718 | I915_WRITE(RING_PP_DIR_DCLV(ring), PP_DIR_DCLV_2G); | |
3719 | I915_WRITE(RING_PP_DIR_BASE(ring), pd_offset); | |
3720 | } | |
3721 | } | |
3722 | ||
8187a2b7 | 3723 | int |
f691e2f4 | 3724 | i915_gem_init_hw(struct drm_device *dev) |
8187a2b7 ZN |
3725 | { |
3726 | drm_i915_private_t *dev_priv = dev->dev_private; | |
3727 | int ret; | |
68f95ba9 | 3728 | |
f691e2f4 DV |
3729 | i915_gem_init_swizzling(dev); |
3730 | ||
5c1143bb | 3731 | ret = intel_init_render_ring_buffer(dev); |
68f95ba9 | 3732 | if (ret) |
b6913e4b | 3733 | return ret; |
68f95ba9 CW |
3734 | |
3735 | if (HAS_BSD(dev)) { | |
5c1143bb | 3736 | ret = intel_init_bsd_ring_buffer(dev); |
68f95ba9 CW |
3737 | if (ret) |
3738 | goto cleanup_render_ring; | |
d1b851fc | 3739 | } |
68f95ba9 | 3740 | |
549f7365 CW |
3741 | if (HAS_BLT(dev)) { |
3742 | ret = intel_init_blt_ring_buffer(dev); | |
3743 | if (ret) | |
3744 | goto cleanup_bsd_ring; | |
3745 | } | |
3746 | ||
6f392d54 CW |
3747 | dev_priv->next_seqno = 1; |
3748 | ||
e21af88d DV |
3749 | i915_gem_init_ppgtt(dev); |
3750 | ||
68f95ba9 CW |
3751 | return 0; |
3752 | ||
549f7365 | 3753 | cleanup_bsd_ring: |
1ec14ad3 | 3754 | intel_cleanup_ring_buffer(&dev_priv->ring[VCS]); |
68f95ba9 | 3755 | cleanup_render_ring: |
1ec14ad3 | 3756 | intel_cleanup_ring_buffer(&dev_priv->ring[RCS]); |
8187a2b7 ZN |
3757 | return ret; |
3758 | } | |
3759 | ||
3760 | void | |
3761 | i915_gem_cleanup_ringbuffer(struct drm_device *dev) | |
3762 | { | |
3763 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1ec14ad3 | 3764 | int i; |
8187a2b7 | 3765 | |
1ec14ad3 CW |
3766 | for (i = 0; i < I915_NUM_RINGS; i++) |
3767 | intel_cleanup_ring_buffer(&dev_priv->ring[i]); | |
8187a2b7 ZN |
3768 | } |
3769 | ||
673a394b EA |
3770 | int |
3771 | i915_gem_entervt_ioctl(struct drm_device *dev, void *data, | |
3772 | struct drm_file *file_priv) | |
3773 | { | |
3774 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1ec14ad3 | 3775 | int ret, i; |
673a394b | 3776 | |
79e53945 JB |
3777 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
3778 | return 0; | |
3779 | ||
ba1234d1 | 3780 | if (atomic_read(&dev_priv->mm.wedged)) { |
673a394b | 3781 | DRM_ERROR("Reenabling wedged hardware, good luck\n"); |
ba1234d1 | 3782 | atomic_set(&dev_priv->mm.wedged, 0); |
673a394b EA |
3783 | } |
3784 | ||
673a394b | 3785 | mutex_lock(&dev->struct_mutex); |
9bb2d6f9 EA |
3786 | dev_priv->mm.suspended = 0; |
3787 | ||
f691e2f4 | 3788 | ret = i915_gem_init_hw(dev); |
d816f6ac WF |
3789 | if (ret != 0) { |
3790 | mutex_unlock(&dev->struct_mutex); | |
9bb2d6f9 | 3791 | return ret; |
d816f6ac | 3792 | } |
9bb2d6f9 | 3793 | |
69dc4987 | 3794 | BUG_ON(!list_empty(&dev_priv->mm.active_list)); |
673a394b EA |
3795 | BUG_ON(!list_empty(&dev_priv->mm.flushing_list)); |
3796 | BUG_ON(!list_empty(&dev_priv->mm.inactive_list)); | |
1ec14ad3 CW |
3797 | for (i = 0; i < I915_NUM_RINGS; i++) { |
3798 | BUG_ON(!list_empty(&dev_priv->ring[i].active_list)); | |
3799 | BUG_ON(!list_empty(&dev_priv->ring[i].request_list)); | |
3800 | } | |
673a394b | 3801 | mutex_unlock(&dev->struct_mutex); |
dbb19d30 | 3802 | |
5f35308b CW |
3803 | ret = drm_irq_install(dev); |
3804 | if (ret) | |
3805 | goto cleanup_ringbuffer; | |
dbb19d30 | 3806 | |
673a394b | 3807 | return 0; |
5f35308b CW |
3808 | |
3809 | cleanup_ringbuffer: | |
3810 | mutex_lock(&dev->struct_mutex); | |
3811 | i915_gem_cleanup_ringbuffer(dev); | |
3812 | dev_priv->mm.suspended = 1; | |
3813 | mutex_unlock(&dev->struct_mutex); | |
3814 | ||
3815 | return ret; | |
673a394b EA |
3816 | } |
3817 | ||
3818 | int | |
3819 | i915_gem_leavevt_ioctl(struct drm_device *dev, void *data, | |
3820 | struct drm_file *file_priv) | |
3821 | { | |
79e53945 JB |
3822 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
3823 | return 0; | |
3824 | ||
dbb19d30 | 3825 | drm_irq_uninstall(dev); |
e6890f6f | 3826 | return i915_gem_idle(dev); |
673a394b EA |
3827 | } |
3828 | ||
3829 | void | |
3830 | i915_gem_lastclose(struct drm_device *dev) | |
3831 | { | |
3832 | int ret; | |
673a394b | 3833 | |
e806b495 EA |
3834 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
3835 | return; | |
3836 | ||
6dbe2772 KP |
3837 | ret = i915_gem_idle(dev); |
3838 | if (ret) | |
3839 | DRM_ERROR("failed to idle hardware: %d\n", ret); | |
673a394b EA |
3840 | } |
3841 | ||
64193406 CW |
3842 | static void |
3843 | init_ring_lists(struct intel_ring_buffer *ring) | |
3844 | { | |
3845 | INIT_LIST_HEAD(&ring->active_list); | |
3846 | INIT_LIST_HEAD(&ring->request_list); | |
3847 | INIT_LIST_HEAD(&ring->gpu_write_list); | |
3848 | } | |
3849 | ||
673a394b EA |
3850 | void |
3851 | i915_gem_load(struct drm_device *dev) | |
3852 | { | |
b5aa8a0f | 3853 | int i; |
673a394b EA |
3854 | drm_i915_private_t *dev_priv = dev->dev_private; |
3855 | ||
69dc4987 | 3856 | INIT_LIST_HEAD(&dev_priv->mm.active_list); |
673a394b EA |
3857 | INIT_LIST_HEAD(&dev_priv->mm.flushing_list); |
3858 | INIT_LIST_HEAD(&dev_priv->mm.inactive_list); | |
f13d3f73 | 3859 | INIT_LIST_HEAD(&dev_priv->mm.pinned_list); |
a09ba7fa | 3860 | INIT_LIST_HEAD(&dev_priv->mm.fence_list); |
be72615b | 3861 | INIT_LIST_HEAD(&dev_priv->mm.deferred_free_list); |
93a37f20 | 3862 | INIT_LIST_HEAD(&dev_priv->mm.gtt_list); |
1ec14ad3 CW |
3863 | for (i = 0; i < I915_NUM_RINGS; i++) |
3864 | init_ring_lists(&dev_priv->ring[i]); | |
4b9de737 | 3865 | for (i = 0; i < I915_MAX_NUM_FENCES; i++) |
007cc8ac | 3866 | INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list); |
673a394b EA |
3867 | INIT_DELAYED_WORK(&dev_priv->mm.retire_work, |
3868 | i915_gem_retire_work_handler); | |
30dbf0c0 | 3869 | init_completion(&dev_priv->error_completion); |
31169714 | 3870 | |
94400120 DA |
3871 | /* On GEN3 we really need to make sure the ARB C3 LP bit is set */ |
3872 | if (IS_GEN3(dev)) { | |
3873 | u32 tmp = I915_READ(MI_ARB_STATE); | |
3874 | if (!(tmp & MI_ARB_C3_LP_WRITE_ENABLE)) { | |
3875 | /* arb state is a masked write, so set bit + bit in mask */ | |
3876 | tmp = MI_ARB_C3_LP_WRITE_ENABLE | (MI_ARB_C3_LP_WRITE_ENABLE << MI_ARB_MASK_SHIFT); | |
3877 | I915_WRITE(MI_ARB_STATE, tmp); | |
3878 | } | |
3879 | } | |
3880 | ||
72bfa19c CW |
3881 | dev_priv->relative_constants_mode = I915_EXEC_CONSTANTS_REL_GENERAL; |
3882 | ||
de151cf6 | 3883 | /* Old X drivers will take 0-2 for front, back, depth buffers */ |
b397c836 EA |
3884 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) |
3885 | dev_priv->fence_reg_start = 3; | |
de151cf6 | 3886 | |
a6c45cf0 | 3887 | if (INTEL_INFO(dev)->gen >= 4 || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) |
de151cf6 JB |
3888 | dev_priv->num_fence_regs = 16; |
3889 | else | |
3890 | dev_priv->num_fence_regs = 8; | |
3891 | ||
b5aa8a0f | 3892 | /* Initialize fence registers to zero */ |
10ed13e4 EA |
3893 | for (i = 0; i < dev_priv->num_fence_regs; i++) { |
3894 | i915_gem_clear_fence_reg(dev, &dev_priv->fence_regs[i]); | |
b5aa8a0f | 3895 | } |
10ed13e4 | 3896 | |
673a394b | 3897 | i915_gem_detect_bit_6_swizzle(dev); |
6b95a207 | 3898 | init_waitqueue_head(&dev_priv->pending_flip_queue); |
17250b71 | 3899 | |
ce453d81 CW |
3900 | dev_priv->mm.interruptible = true; |
3901 | ||
17250b71 CW |
3902 | dev_priv->mm.inactive_shrinker.shrink = i915_gem_inactive_shrink; |
3903 | dev_priv->mm.inactive_shrinker.seeks = DEFAULT_SEEKS; | |
3904 | register_shrinker(&dev_priv->mm.inactive_shrinker); | |
673a394b | 3905 | } |
71acb5eb DA |
3906 | |
3907 | /* | |
3908 | * Create a physically contiguous memory object for this object | |
3909 | * e.g. for cursor + overlay regs | |
3910 | */ | |
995b6762 CW |
3911 | static int i915_gem_init_phys_object(struct drm_device *dev, |
3912 | int id, int size, int align) | |
71acb5eb DA |
3913 | { |
3914 | drm_i915_private_t *dev_priv = dev->dev_private; | |
3915 | struct drm_i915_gem_phys_object *phys_obj; | |
3916 | int ret; | |
3917 | ||
3918 | if (dev_priv->mm.phys_objs[id - 1] || !size) | |
3919 | return 0; | |
3920 | ||
9a298b2a | 3921 | phys_obj = kzalloc(sizeof(struct drm_i915_gem_phys_object), GFP_KERNEL); |
71acb5eb DA |
3922 | if (!phys_obj) |
3923 | return -ENOMEM; | |
3924 | ||
3925 | phys_obj->id = id; | |
3926 | ||
6eeefaf3 | 3927 | phys_obj->handle = drm_pci_alloc(dev, size, align); |
71acb5eb DA |
3928 | if (!phys_obj->handle) { |
3929 | ret = -ENOMEM; | |
3930 | goto kfree_obj; | |
3931 | } | |
3932 | #ifdef CONFIG_X86 | |
3933 | set_memory_wc((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE); | |
3934 | #endif | |
3935 | ||
3936 | dev_priv->mm.phys_objs[id - 1] = phys_obj; | |
3937 | ||
3938 | return 0; | |
3939 | kfree_obj: | |
9a298b2a | 3940 | kfree(phys_obj); |
71acb5eb DA |
3941 | return ret; |
3942 | } | |
3943 | ||
995b6762 | 3944 | static void i915_gem_free_phys_object(struct drm_device *dev, int id) |
71acb5eb DA |
3945 | { |
3946 | drm_i915_private_t *dev_priv = dev->dev_private; | |
3947 | struct drm_i915_gem_phys_object *phys_obj; | |
3948 | ||
3949 | if (!dev_priv->mm.phys_objs[id - 1]) | |
3950 | return; | |
3951 | ||
3952 | phys_obj = dev_priv->mm.phys_objs[id - 1]; | |
3953 | if (phys_obj->cur_obj) { | |
3954 | i915_gem_detach_phys_object(dev, phys_obj->cur_obj); | |
3955 | } | |
3956 | ||
3957 | #ifdef CONFIG_X86 | |
3958 | set_memory_wb((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE); | |
3959 | #endif | |
3960 | drm_pci_free(dev, phys_obj->handle); | |
3961 | kfree(phys_obj); | |
3962 | dev_priv->mm.phys_objs[id - 1] = NULL; | |
3963 | } | |
3964 | ||
3965 | void i915_gem_free_all_phys_object(struct drm_device *dev) | |
3966 | { | |
3967 | int i; | |
3968 | ||
260883c8 | 3969 | for (i = I915_GEM_PHYS_CURSOR_0; i <= I915_MAX_PHYS_OBJECT; i++) |
71acb5eb DA |
3970 | i915_gem_free_phys_object(dev, i); |
3971 | } | |
3972 | ||
3973 | void i915_gem_detach_phys_object(struct drm_device *dev, | |
05394f39 | 3974 | struct drm_i915_gem_object *obj) |
71acb5eb | 3975 | { |
05394f39 | 3976 | struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping; |
e5281ccd | 3977 | char *vaddr; |
71acb5eb | 3978 | int i; |
71acb5eb DA |
3979 | int page_count; |
3980 | ||
05394f39 | 3981 | if (!obj->phys_obj) |
71acb5eb | 3982 | return; |
05394f39 | 3983 | vaddr = obj->phys_obj->handle->vaddr; |
71acb5eb | 3984 | |
05394f39 | 3985 | page_count = obj->base.size / PAGE_SIZE; |
71acb5eb | 3986 | for (i = 0; i < page_count; i++) { |
5949eac4 | 3987 | struct page *page = shmem_read_mapping_page(mapping, i); |
e5281ccd CW |
3988 | if (!IS_ERR(page)) { |
3989 | char *dst = kmap_atomic(page); | |
3990 | memcpy(dst, vaddr + i*PAGE_SIZE, PAGE_SIZE); | |
3991 | kunmap_atomic(dst); | |
3992 | ||
3993 | drm_clflush_pages(&page, 1); | |
3994 | ||
3995 | set_page_dirty(page); | |
3996 | mark_page_accessed(page); | |
3997 | page_cache_release(page); | |
3998 | } | |
71acb5eb | 3999 | } |
40ce6575 | 4000 | intel_gtt_chipset_flush(); |
d78b47b9 | 4001 | |
05394f39 CW |
4002 | obj->phys_obj->cur_obj = NULL; |
4003 | obj->phys_obj = NULL; | |
71acb5eb DA |
4004 | } |
4005 | ||
4006 | int | |
4007 | i915_gem_attach_phys_object(struct drm_device *dev, | |
05394f39 | 4008 | struct drm_i915_gem_object *obj, |
6eeefaf3 CW |
4009 | int id, |
4010 | int align) | |
71acb5eb | 4011 | { |
05394f39 | 4012 | struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping; |
71acb5eb | 4013 | drm_i915_private_t *dev_priv = dev->dev_private; |
71acb5eb DA |
4014 | int ret = 0; |
4015 | int page_count; | |
4016 | int i; | |
4017 | ||
4018 | if (id > I915_MAX_PHYS_OBJECT) | |
4019 | return -EINVAL; | |
4020 | ||
05394f39 CW |
4021 | if (obj->phys_obj) { |
4022 | if (obj->phys_obj->id == id) | |
71acb5eb DA |
4023 | return 0; |
4024 | i915_gem_detach_phys_object(dev, obj); | |
4025 | } | |
4026 | ||
71acb5eb DA |
4027 | /* create a new object */ |
4028 | if (!dev_priv->mm.phys_objs[id - 1]) { | |
4029 | ret = i915_gem_init_phys_object(dev, id, | |
05394f39 | 4030 | obj->base.size, align); |
71acb5eb | 4031 | if (ret) { |
05394f39 CW |
4032 | DRM_ERROR("failed to init phys object %d size: %zu\n", |
4033 | id, obj->base.size); | |
e5281ccd | 4034 | return ret; |
71acb5eb DA |
4035 | } |
4036 | } | |
4037 | ||
4038 | /* bind to the object */ | |
05394f39 CW |
4039 | obj->phys_obj = dev_priv->mm.phys_objs[id - 1]; |
4040 | obj->phys_obj->cur_obj = obj; | |
71acb5eb | 4041 | |
05394f39 | 4042 | page_count = obj->base.size / PAGE_SIZE; |
71acb5eb DA |
4043 | |
4044 | for (i = 0; i < page_count; i++) { | |
e5281ccd CW |
4045 | struct page *page; |
4046 | char *dst, *src; | |
4047 | ||
5949eac4 | 4048 | page = shmem_read_mapping_page(mapping, i); |
e5281ccd CW |
4049 | if (IS_ERR(page)) |
4050 | return PTR_ERR(page); | |
71acb5eb | 4051 | |
ff75b9bc | 4052 | src = kmap_atomic(page); |
05394f39 | 4053 | dst = obj->phys_obj->handle->vaddr + (i * PAGE_SIZE); |
71acb5eb | 4054 | memcpy(dst, src, PAGE_SIZE); |
3e4d3af5 | 4055 | kunmap_atomic(src); |
71acb5eb | 4056 | |
e5281ccd CW |
4057 | mark_page_accessed(page); |
4058 | page_cache_release(page); | |
4059 | } | |
d78b47b9 | 4060 | |
71acb5eb | 4061 | return 0; |
71acb5eb DA |
4062 | } |
4063 | ||
4064 | static int | |
05394f39 CW |
4065 | i915_gem_phys_pwrite(struct drm_device *dev, |
4066 | struct drm_i915_gem_object *obj, | |
71acb5eb DA |
4067 | struct drm_i915_gem_pwrite *args, |
4068 | struct drm_file *file_priv) | |
4069 | { | |
05394f39 | 4070 | void *vaddr = obj->phys_obj->handle->vaddr + args->offset; |
b47b30cc | 4071 | char __user *user_data = (char __user *) (uintptr_t) args->data_ptr; |
71acb5eb | 4072 | |
b47b30cc CW |
4073 | if (__copy_from_user_inatomic_nocache(vaddr, user_data, args->size)) { |
4074 | unsigned long unwritten; | |
4075 | ||
4076 | /* The physical object once assigned is fixed for the lifetime | |
4077 | * of the obj, so we can safely drop the lock and continue | |
4078 | * to access vaddr. | |
4079 | */ | |
4080 | mutex_unlock(&dev->struct_mutex); | |
4081 | unwritten = copy_from_user(vaddr, user_data, args->size); | |
4082 | mutex_lock(&dev->struct_mutex); | |
4083 | if (unwritten) | |
4084 | return -EFAULT; | |
4085 | } | |
71acb5eb | 4086 | |
40ce6575 | 4087 | intel_gtt_chipset_flush(); |
71acb5eb DA |
4088 | return 0; |
4089 | } | |
b962442e | 4090 | |
f787a5f5 | 4091 | void i915_gem_release(struct drm_device *dev, struct drm_file *file) |
b962442e | 4092 | { |
f787a5f5 | 4093 | struct drm_i915_file_private *file_priv = file->driver_priv; |
b962442e EA |
4094 | |
4095 | /* Clean up our request list when the client is going away, so that | |
4096 | * later retire_requests won't dereference our soon-to-be-gone | |
4097 | * file_priv. | |
4098 | */ | |
1c25595f | 4099 | spin_lock(&file_priv->mm.lock); |
f787a5f5 CW |
4100 | while (!list_empty(&file_priv->mm.request_list)) { |
4101 | struct drm_i915_gem_request *request; | |
4102 | ||
4103 | request = list_first_entry(&file_priv->mm.request_list, | |
4104 | struct drm_i915_gem_request, | |
4105 | client_list); | |
4106 | list_del(&request->client_list); | |
4107 | request->file_priv = NULL; | |
4108 | } | |
1c25595f | 4109 | spin_unlock(&file_priv->mm.lock); |
b962442e | 4110 | } |
31169714 | 4111 | |
1637ef41 CW |
4112 | static int |
4113 | i915_gpu_is_active(struct drm_device *dev) | |
4114 | { | |
4115 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4116 | int lists_empty; | |
4117 | ||
1637ef41 | 4118 | lists_empty = list_empty(&dev_priv->mm.flushing_list) && |
17250b71 | 4119 | list_empty(&dev_priv->mm.active_list); |
1637ef41 CW |
4120 | |
4121 | return !lists_empty; | |
4122 | } | |
4123 | ||
31169714 | 4124 | static int |
1495f230 | 4125 | i915_gem_inactive_shrink(struct shrinker *shrinker, struct shrink_control *sc) |
31169714 | 4126 | { |
17250b71 CW |
4127 | struct drm_i915_private *dev_priv = |
4128 | container_of(shrinker, | |
4129 | struct drm_i915_private, | |
4130 | mm.inactive_shrinker); | |
4131 | struct drm_device *dev = dev_priv->dev; | |
4132 | struct drm_i915_gem_object *obj, *next; | |
1495f230 | 4133 | int nr_to_scan = sc->nr_to_scan; |
17250b71 CW |
4134 | int cnt; |
4135 | ||
4136 | if (!mutex_trylock(&dev->struct_mutex)) | |
bbe2e11a | 4137 | return 0; |
31169714 CW |
4138 | |
4139 | /* "fast-path" to count number of available objects */ | |
4140 | if (nr_to_scan == 0) { | |
17250b71 CW |
4141 | cnt = 0; |
4142 | list_for_each_entry(obj, | |
4143 | &dev_priv->mm.inactive_list, | |
4144 | mm_list) | |
4145 | cnt++; | |
4146 | mutex_unlock(&dev->struct_mutex); | |
4147 | return cnt / 100 * sysctl_vfs_cache_pressure; | |
31169714 CW |
4148 | } |
4149 | ||
1637ef41 | 4150 | rescan: |
31169714 | 4151 | /* first scan for clean buffers */ |
17250b71 | 4152 | i915_gem_retire_requests(dev); |
31169714 | 4153 | |
17250b71 CW |
4154 | list_for_each_entry_safe(obj, next, |
4155 | &dev_priv->mm.inactive_list, | |
4156 | mm_list) { | |
4157 | if (i915_gem_object_is_purgeable(obj)) { | |
2021746e CW |
4158 | if (i915_gem_object_unbind(obj) == 0 && |
4159 | --nr_to_scan == 0) | |
17250b71 | 4160 | break; |
31169714 | 4161 | } |
31169714 CW |
4162 | } |
4163 | ||
4164 | /* second pass, evict/count anything still on the inactive list */ | |
17250b71 CW |
4165 | cnt = 0; |
4166 | list_for_each_entry_safe(obj, next, | |
4167 | &dev_priv->mm.inactive_list, | |
4168 | mm_list) { | |
2021746e CW |
4169 | if (nr_to_scan && |
4170 | i915_gem_object_unbind(obj) == 0) | |
17250b71 | 4171 | nr_to_scan--; |
2021746e | 4172 | else |
17250b71 CW |
4173 | cnt++; |
4174 | } | |
4175 | ||
4176 | if (nr_to_scan && i915_gpu_is_active(dev)) { | |
1637ef41 CW |
4177 | /* |
4178 | * We are desperate for pages, so as a last resort, wait | |
4179 | * for the GPU to finish and discard whatever we can. | |
4180 | * This has a dramatic impact to reduce the number of | |
4181 | * OOM-killer events whilst running the GPU aggressively. | |
4182 | */ | |
b93f9cf1 | 4183 | if (i915_gpu_idle(dev, true) == 0) |
1637ef41 CW |
4184 | goto rescan; |
4185 | } | |
17250b71 CW |
4186 | mutex_unlock(&dev->struct_mutex); |
4187 | return cnt / 100 * sysctl_vfs_cache_pressure; | |
31169714 | 4188 | } |