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673a394b EA |
1 | /* |
2 | * Copyright © 2008 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | * | |
26 | */ | |
27 | ||
28 | #include "drmP.h" | |
29 | #include "drm.h" | |
30 | #include "i915_drm.h" | |
31 | #include "i915_drv.h" | |
652c393a | 32 | #include "intel_drv.h" |
673a394b | 33 | #include <linux/swap.h> |
79e53945 | 34 | #include <linux/pci.h> |
673a394b | 35 | |
28dfe52a EA |
36 | #define I915_GEM_GPU_DOMAINS (~(I915_GEM_DOMAIN_CPU | I915_GEM_DOMAIN_GTT)) |
37 | ||
e47c68e9 EA |
38 | static void i915_gem_object_flush_gpu_write_domain(struct drm_gem_object *obj); |
39 | static void i915_gem_object_flush_gtt_write_domain(struct drm_gem_object *obj); | |
40 | static void i915_gem_object_flush_cpu_write_domain(struct drm_gem_object *obj); | |
e47c68e9 EA |
41 | static int i915_gem_object_set_to_cpu_domain(struct drm_gem_object *obj, |
42 | int write); | |
43 | static int i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object *obj, | |
44 | uint64_t offset, | |
45 | uint64_t size); | |
46 | static void i915_gem_object_set_to_full_cpu_read_domain(struct drm_gem_object *obj); | |
673a394b | 47 | static int i915_gem_object_wait_rendering(struct drm_gem_object *obj); |
de151cf6 JB |
48 | static int i915_gem_object_bind_to_gtt(struct drm_gem_object *obj, |
49 | unsigned alignment); | |
de151cf6 JB |
50 | static void i915_gem_clear_fence_reg(struct drm_gem_object *obj); |
51 | static int i915_gem_evict_something(struct drm_device *dev); | |
71acb5eb DA |
52 | static int i915_gem_phys_pwrite(struct drm_device *dev, struct drm_gem_object *obj, |
53 | struct drm_i915_gem_pwrite *args, | |
54 | struct drm_file *file_priv); | |
673a394b | 55 | |
79e53945 JB |
56 | int i915_gem_do_init(struct drm_device *dev, unsigned long start, |
57 | unsigned long end) | |
673a394b EA |
58 | { |
59 | drm_i915_private_t *dev_priv = dev->dev_private; | |
673a394b | 60 | |
79e53945 JB |
61 | if (start >= end || |
62 | (start & (PAGE_SIZE - 1)) != 0 || | |
63 | (end & (PAGE_SIZE - 1)) != 0) { | |
673a394b EA |
64 | return -EINVAL; |
65 | } | |
66 | ||
79e53945 JB |
67 | drm_mm_init(&dev_priv->mm.gtt_space, start, |
68 | end - start); | |
673a394b | 69 | |
79e53945 JB |
70 | dev->gtt_total = (uint32_t) (end - start); |
71 | ||
72 | return 0; | |
73 | } | |
673a394b | 74 | |
79e53945 JB |
75 | int |
76 | i915_gem_init_ioctl(struct drm_device *dev, void *data, | |
77 | struct drm_file *file_priv) | |
78 | { | |
79 | struct drm_i915_gem_init *args = data; | |
80 | int ret; | |
81 | ||
82 | mutex_lock(&dev->struct_mutex); | |
83 | ret = i915_gem_do_init(dev, args->gtt_start, args->gtt_end); | |
673a394b EA |
84 | mutex_unlock(&dev->struct_mutex); |
85 | ||
79e53945 | 86 | return ret; |
673a394b EA |
87 | } |
88 | ||
5a125c3c EA |
89 | int |
90 | i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data, | |
91 | struct drm_file *file_priv) | |
92 | { | |
5a125c3c | 93 | struct drm_i915_gem_get_aperture *args = data; |
5a125c3c EA |
94 | |
95 | if (!(dev->driver->driver_features & DRIVER_GEM)) | |
96 | return -ENODEV; | |
97 | ||
98 | args->aper_size = dev->gtt_total; | |
2678d9d6 KP |
99 | args->aper_available_size = (args->aper_size - |
100 | atomic_read(&dev->pin_memory)); | |
5a125c3c EA |
101 | |
102 | return 0; | |
103 | } | |
104 | ||
673a394b EA |
105 | |
106 | /** | |
107 | * Creates a new mm object and returns a handle to it. | |
108 | */ | |
109 | int | |
110 | i915_gem_create_ioctl(struct drm_device *dev, void *data, | |
111 | struct drm_file *file_priv) | |
112 | { | |
113 | struct drm_i915_gem_create *args = data; | |
114 | struct drm_gem_object *obj; | |
a1a2d1d3 PP |
115 | int ret; |
116 | u32 handle; | |
673a394b EA |
117 | |
118 | args->size = roundup(args->size, PAGE_SIZE); | |
119 | ||
120 | /* Allocate the new object */ | |
121 | obj = drm_gem_object_alloc(dev, args->size); | |
122 | if (obj == NULL) | |
123 | return -ENOMEM; | |
124 | ||
125 | ret = drm_gem_handle_create(file_priv, obj, &handle); | |
126 | mutex_lock(&dev->struct_mutex); | |
127 | drm_gem_object_handle_unreference(obj); | |
128 | mutex_unlock(&dev->struct_mutex); | |
129 | ||
130 | if (ret) | |
131 | return ret; | |
132 | ||
133 | args->handle = handle; | |
134 | ||
135 | return 0; | |
136 | } | |
137 | ||
eb01459f EA |
138 | static inline int |
139 | fast_shmem_read(struct page **pages, | |
140 | loff_t page_base, int page_offset, | |
141 | char __user *data, | |
142 | int length) | |
143 | { | |
144 | char __iomem *vaddr; | |
2bc43b5c | 145 | int unwritten; |
eb01459f EA |
146 | |
147 | vaddr = kmap_atomic(pages[page_base >> PAGE_SHIFT], KM_USER0); | |
148 | if (vaddr == NULL) | |
149 | return -ENOMEM; | |
2bc43b5c | 150 | unwritten = __copy_to_user_inatomic(data, vaddr + page_offset, length); |
eb01459f EA |
151 | kunmap_atomic(vaddr, KM_USER0); |
152 | ||
2bc43b5c FM |
153 | if (unwritten) |
154 | return -EFAULT; | |
155 | ||
156 | return 0; | |
eb01459f EA |
157 | } |
158 | ||
280b713b EA |
159 | static int i915_gem_object_needs_bit17_swizzle(struct drm_gem_object *obj) |
160 | { | |
161 | drm_i915_private_t *dev_priv = obj->dev->dev_private; | |
162 | struct drm_i915_gem_object *obj_priv = obj->driver_private; | |
163 | ||
164 | return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 && | |
165 | obj_priv->tiling_mode != I915_TILING_NONE; | |
166 | } | |
167 | ||
40123c1f EA |
168 | static inline int |
169 | slow_shmem_copy(struct page *dst_page, | |
170 | int dst_offset, | |
171 | struct page *src_page, | |
172 | int src_offset, | |
173 | int length) | |
174 | { | |
175 | char *dst_vaddr, *src_vaddr; | |
176 | ||
177 | dst_vaddr = kmap_atomic(dst_page, KM_USER0); | |
178 | if (dst_vaddr == NULL) | |
179 | return -ENOMEM; | |
180 | ||
181 | src_vaddr = kmap_atomic(src_page, KM_USER1); | |
182 | if (src_vaddr == NULL) { | |
183 | kunmap_atomic(dst_vaddr, KM_USER0); | |
184 | return -ENOMEM; | |
185 | } | |
186 | ||
187 | memcpy(dst_vaddr + dst_offset, src_vaddr + src_offset, length); | |
188 | ||
189 | kunmap_atomic(src_vaddr, KM_USER1); | |
190 | kunmap_atomic(dst_vaddr, KM_USER0); | |
191 | ||
192 | return 0; | |
193 | } | |
194 | ||
280b713b EA |
195 | static inline int |
196 | slow_shmem_bit17_copy(struct page *gpu_page, | |
197 | int gpu_offset, | |
198 | struct page *cpu_page, | |
199 | int cpu_offset, | |
200 | int length, | |
201 | int is_read) | |
202 | { | |
203 | char *gpu_vaddr, *cpu_vaddr; | |
204 | ||
205 | /* Use the unswizzled path if this page isn't affected. */ | |
206 | if ((page_to_phys(gpu_page) & (1 << 17)) == 0) { | |
207 | if (is_read) | |
208 | return slow_shmem_copy(cpu_page, cpu_offset, | |
209 | gpu_page, gpu_offset, length); | |
210 | else | |
211 | return slow_shmem_copy(gpu_page, gpu_offset, | |
212 | cpu_page, cpu_offset, length); | |
213 | } | |
214 | ||
215 | gpu_vaddr = kmap_atomic(gpu_page, KM_USER0); | |
216 | if (gpu_vaddr == NULL) | |
217 | return -ENOMEM; | |
218 | ||
219 | cpu_vaddr = kmap_atomic(cpu_page, KM_USER1); | |
220 | if (cpu_vaddr == NULL) { | |
221 | kunmap_atomic(gpu_vaddr, KM_USER0); | |
222 | return -ENOMEM; | |
223 | } | |
224 | ||
225 | /* Copy the data, XORing A6 with A17 (1). The user already knows he's | |
226 | * XORing with the other bits (A9 for Y, A9 and A10 for X) | |
227 | */ | |
228 | while (length > 0) { | |
229 | int cacheline_end = ALIGN(gpu_offset + 1, 64); | |
230 | int this_length = min(cacheline_end - gpu_offset, length); | |
231 | int swizzled_gpu_offset = gpu_offset ^ 64; | |
232 | ||
233 | if (is_read) { | |
234 | memcpy(cpu_vaddr + cpu_offset, | |
235 | gpu_vaddr + swizzled_gpu_offset, | |
236 | this_length); | |
237 | } else { | |
238 | memcpy(gpu_vaddr + swizzled_gpu_offset, | |
239 | cpu_vaddr + cpu_offset, | |
240 | this_length); | |
241 | } | |
242 | cpu_offset += this_length; | |
243 | gpu_offset += this_length; | |
244 | length -= this_length; | |
245 | } | |
246 | ||
247 | kunmap_atomic(cpu_vaddr, KM_USER1); | |
248 | kunmap_atomic(gpu_vaddr, KM_USER0); | |
249 | ||
250 | return 0; | |
251 | } | |
252 | ||
eb01459f EA |
253 | /** |
254 | * This is the fast shmem pread path, which attempts to copy_from_user directly | |
255 | * from the backing pages of the object to the user's address space. On a | |
256 | * fault, it fails so we can fall back to i915_gem_shmem_pwrite_slow(). | |
257 | */ | |
258 | static int | |
259 | i915_gem_shmem_pread_fast(struct drm_device *dev, struct drm_gem_object *obj, | |
260 | struct drm_i915_gem_pread *args, | |
261 | struct drm_file *file_priv) | |
262 | { | |
263 | struct drm_i915_gem_object *obj_priv = obj->driver_private; | |
264 | ssize_t remain; | |
265 | loff_t offset, page_base; | |
266 | char __user *user_data; | |
267 | int page_offset, page_length; | |
268 | int ret; | |
269 | ||
270 | user_data = (char __user *) (uintptr_t) args->data_ptr; | |
271 | remain = args->size; | |
272 | ||
273 | mutex_lock(&dev->struct_mutex); | |
274 | ||
275 | ret = i915_gem_object_get_pages(obj); | |
276 | if (ret != 0) | |
277 | goto fail_unlock; | |
278 | ||
279 | ret = i915_gem_object_set_cpu_read_domain_range(obj, args->offset, | |
280 | args->size); | |
281 | if (ret != 0) | |
282 | goto fail_put_pages; | |
283 | ||
284 | obj_priv = obj->driver_private; | |
285 | offset = args->offset; | |
286 | ||
287 | while (remain > 0) { | |
288 | /* Operation in this page | |
289 | * | |
290 | * page_base = page offset within aperture | |
291 | * page_offset = offset within page | |
292 | * page_length = bytes to copy for this page | |
293 | */ | |
294 | page_base = (offset & ~(PAGE_SIZE-1)); | |
295 | page_offset = offset & (PAGE_SIZE-1); | |
296 | page_length = remain; | |
297 | if ((page_offset + remain) > PAGE_SIZE) | |
298 | page_length = PAGE_SIZE - page_offset; | |
299 | ||
300 | ret = fast_shmem_read(obj_priv->pages, | |
301 | page_base, page_offset, | |
302 | user_data, page_length); | |
303 | if (ret) | |
304 | goto fail_put_pages; | |
305 | ||
306 | remain -= page_length; | |
307 | user_data += page_length; | |
308 | offset += page_length; | |
309 | } | |
310 | ||
311 | fail_put_pages: | |
312 | i915_gem_object_put_pages(obj); | |
313 | fail_unlock: | |
314 | mutex_unlock(&dev->struct_mutex); | |
315 | ||
316 | return ret; | |
317 | } | |
318 | ||
319 | /** | |
320 | * This is the fallback shmem pread path, which allocates temporary storage | |
321 | * in kernel space to copy_to_user into outside of the struct_mutex, so we | |
322 | * can copy out of the object's backing pages while holding the struct mutex | |
323 | * and not take page faults. | |
324 | */ | |
325 | static int | |
326 | i915_gem_shmem_pread_slow(struct drm_device *dev, struct drm_gem_object *obj, | |
327 | struct drm_i915_gem_pread *args, | |
328 | struct drm_file *file_priv) | |
329 | { | |
330 | struct drm_i915_gem_object *obj_priv = obj->driver_private; | |
331 | struct mm_struct *mm = current->mm; | |
332 | struct page **user_pages; | |
333 | ssize_t remain; | |
334 | loff_t offset, pinned_pages, i; | |
335 | loff_t first_data_page, last_data_page, num_pages; | |
336 | int shmem_page_index, shmem_page_offset; | |
337 | int data_page_index, data_page_offset; | |
338 | int page_length; | |
339 | int ret; | |
340 | uint64_t data_ptr = args->data_ptr; | |
280b713b | 341 | int do_bit17_swizzling; |
eb01459f EA |
342 | |
343 | remain = args->size; | |
344 | ||
345 | /* Pin the user pages containing the data. We can't fault while | |
346 | * holding the struct mutex, yet we want to hold it while | |
347 | * dereferencing the user data. | |
348 | */ | |
349 | first_data_page = data_ptr / PAGE_SIZE; | |
350 | last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE; | |
351 | num_pages = last_data_page - first_data_page + 1; | |
352 | ||
8e7d2b2c | 353 | user_pages = drm_calloc_large(num_pages, sizeof(struct page *)); |
eb01459f EA |
354 | if (user_pages == NULL) |
355 | return -ENOMEM; | |
356 | ||
357 | down_read(&mm->mmap_sem); | |
358 | pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr, | |
e5e9ecde | 359 | num_pages, 1, 0, user_pages, NULL); |
eb01459f EA |
360 | up_read(&mm->mmap_sem); |
361 | if (pinned_pages < num_pages) { | |
362 | ret = -EFAULT; | |
363 | goto fail_put_user_pages; | |
364 | } | |
365 | ||
280b713b EA |
366 | do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj); |
367 | ||
eb01459f EA |
368 | mutex_lock(&dev->struct_mutex); |
369 | ||
370 | ret = i915_gem_object_get_pages(obj); | |
371 | if (ret != 0) | |
372 | goto fail_unlock; | |
373 | ||
374 | ret = i915_gem_object_set_cpu_read_domain_range(obj, args->offset, | |
375 | args->size); | |
376 | if (ret != 0) | |
377 | goto fail_put_pages; | |
378 | ||
379 | obj_priv = obj->driver_private; | |
380 | offset = args->offset; | |
381 | ||
382 | while (remain > 0) { | |
383 | /* Operation in this page | |
384 | * | |
385 | * shmem_page_index = page number within shmem file | |
386 | * shmem_page_offset = offset within page in shmem file | |
387 | * data_page_index = page number in get_user_pages return | |
388 | * data_page_offset = offset with data_page_index page. | |
389 | * page_length = bytes to copy for this page | |
390 | */ | |
391 | shmem_page_index = offset / PAGE_SIZE; | |
392 | shmem_page_offset = offset & ~PAGE_MASK; | |
393 | data_page_index = data_ptr / PAGE_SIZE - first_data_page; | |
394 | data_page_offset = data_ptr & ~PAGE_MASK; | |
395 | ||
396 | page_length = remain; | |
397 | if ((shmem_page_offset + page_length) > PAGE_SIZE) | |
398 | page_length = PAGE_SIZE - shmem_page_offset; | |
399 | if ((data_page_offset + page_length) > PAGE_SIZE) | |
400 | page_length = PAGE_SIZE - data_page_offset; | |
401 | ||
280b713b EA |
402 | if (do_bit17_swizzling) { |
403 | ret = slow_shmem_bit17_copy(obj_priv->pages[shmem_page_index], | |
404 | shmem_page_offset, | |
405 | user_pages[data_page_index], | |
406 | data_page_offset, | |
407 | page_length, | |
408 | 1); | |
409 | } else { | |
410 | ret = slow_shmem_copy(user_pages[data_page_index], | |
411 | data_page_offset, | |
412 | obj_priv->pages[shmem_page_index], | |
413 | shmem_page_offset, | |
414 | page_length); | |
415 | } | |
eb01459f EA |
416 | if (ret) |
417 | goto fail_put_pages; | |
418 | ||
419 | remain -= page_length; | |
420 | data_ptr += page_length; | |
421 | offset += page_length; | |
422 | } | |
423 | ||
424 | fail_put_pages: | |
425 | i915_gem_object_put_pages(obj); | |
426 | fail_unlock: | |
427 | mutex_unlock(&dev->struct_mutex); | |
428 | fail_put_user_pages: | |
429 | for (i = 0; i < pinned_pages; i++) { | |
430 | SetPageDirty(user_pages[i]); | |
431 | page_cache_release(user_pages[i]); | |
432 | } | |
8e7d2b2c | 433 | drm_free_large(user_pages); |
eb01459f EA |
434 | |
435 | return ret; | |
436 | } | |
437 | ||
673a394b EA |
438 | /** |
439 | * Reads data from the object referenced by handle. | |
440 | * | |
441 | * On error, the contents of *data are undefined. | |
442 | */ | |
443 | int | |
444 | i915_gem_pread_ioctl(struct drm_device *dev, void *data, | |
445 | struct drm_file *file_priv) | |
446 | { | |
447 | struct drm_i915_gem_pread *args = data; | |
448 | struct drm_gem_object *obj; | |
449 | struct drm_i915_gem_object *obj_priv; | |
673a394b EA |
450 | int ret; |
451 | ||
452 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); | |
453 | if (obj == NULL) | |
454 | return -EBADF; | |
455 | obj_priv = obj->driver_private; | |
456 | ||
457 | /* Bounds check source. | |
458 | * | |
459 | * XXX: This could use review for overflow issues... | |
460 | */ | |
461 | if (args->offset > obj->size || args->size > obj->size || | |
462 | args->offset + args->size > obj->size) { | |
463 | drm_gem_object_unreference(obj); | |
464 | return -EINVAL; | |
465 | } | |
466 | ||
280b713b | 467 | if (i915_gem_object_needs_bit17_swizzle(obj)) { |
eb01459f | 468 | ret = i915_gem_shmem_pread_slow(dev, obj, args, file_priv); |
280b713b EA |
469 | } else { |
470 | ret = i915_gem_shmem_pread_fast(dev, obj, args, file_priv); | |
471 | if (ret != 0) | |
472 | ret = i915_gem_shmem_pread_slow(dev, obj, args, | |
473 | file_priv); | |
474 | } | |
673a394b EA |
475 | |
476 | drm_gem_object_unreference(obj); | |
673a394b | 477 | |
eb01459f | 478 | return ret; |
673a394b EA |
479 | } |
480 | ||
0839ccb8 KP |
481 | /* This is the fast write path which cannot handle |
482 | * page faults in the source data | |
9b7530cc | 483 | */ |
0839ccb8 KP |
484 | |
485 | static inline int | |
486 | fast_user_write(struct io_mapping *mapping, | |
487 | loff_t page_base, int page_offset, | |
488 | char __user *user_data, | |
489 | int length) | |
9b7530cc | 490 | { |
9b7530cc | 491 | char *vaddr_atomic; |
0839ccb8 | 492 | unsigned long unwritten; |
9b7530cc | 493 | |
0839ccb8 KP |
494 | vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base); |
495 | unwritten = __copy_from_user_inatomic_nocache(vaddr_atomic + page_offset, | |
496 | user_data, length); | |
497 | io_mapping_unmap_atomic(vaddr_atomic); | |
498 | if (unwritten) | |
499 | return -EFAULT; | |
500 | return 0; | |
501 | } | |
502 | ||
503 | /* Here's the write path which can sleep for | |
504 | * page faults | |
505 | */ | |
506 | ||
507 | static inline int | |
3de09aa3 EA |
508 | slow_kernel_write(struct io_mapping *mapping, |
509 | loff_t gtt_base, int gtt_offset, | |
510 | struct page *user_page, int user_offset, | |
511 | int length) | |
0839ccb8 | 512 | { |
3de09aa3 | 513 | char *src_vaddr, *dst_vaddr; |
0839ccb8 KP |
514 | unsigned long unwritten; |
515 | ||
3de09aa3 EA |
516 | dst_vaddr = io_mapping_map_atomic_wc(mapping, gtt_base); |
517 | src_vaddr = kmap_atomic(user_page, KM_USER1); | |
518 | unwritten = __copy_from_user_inatomic_nocache(dst_vaddr + gtt_offset, | |
519 | src_vaddr + user_offset, | |
520 | length); | |
521 | kunmap_atomic(src_vaddr, KM_USER1); | |
522 | io_mapping_unmap_atomic(dst_vaddr); | |
0839ccb8 KP |
523 | if (unwritten) |
524 | return -EFAULT; | |
9b7530cc | 525 | return 0; |
9b7530cc LT |
526 | } |
527 | ||
40123c1f EA |
528 | static inline int |
529 | fast_shmem_write(struct page **pages, | |
530 | loff_t page_base, int page_offset, | |
531 | char __user *data, | |
532 | int length) | |
533 | { | |
534 | char __iomem *vaddr; | |
d0088775 | 535 | unsigned long unwritten; |
40123c1f EA |
536 | |
537 | vaddr = kmap_atomic(pages[page_base >> PAGE_SHIFT], KM_USER0); | |
538 | if (vaddr == NULL) | |
539 | return -ENOMEM; | |
d0088775 | 540 | unwritten = __copy_from_user_inatomic(vaddr + page_offset, data, length); |
40123c1f EA |
541 | kunmap_atomic(vaddr, KM_USER0); |
542 | ||
d0088775 DA |
543 | if (unwritten) |
544 | return -EFAULT; | |
40123c1f EA |
545 | return 0; |
546 | } | |
547 | ||
3de09aa3 EA |
548 | /** |
549 | * This is the fast pwrite path, where we copy the data directly from the | |
550 | * user into the GTT, uncached. | |
551 | */ | |
673a394b | 552 | static int |
3de09aa3 EA |
553 | i915_gem_gtt_pwrite_fast(struct drm_device *dev, struct drm_gem_object *obj, |
554 | struct drm_i915_gem_pwrite *args, | |
555 | struct drm_file *file_priv) | |
673a394b EA |
556 | { |
557 | struct drm_i915_gem_object *obj_priv = obj->driver_private; | |
0839ccb8 | 558 | drm_i915_private_t *dev_priv = dev->dev_private; |
673a394b | 559 | ssize_t remain; |
0839ccb8 | 560 | loff_t offset, page_base; |
673a394b | 561 | char __user *user_data; |
0839ccb8 KP |
562 | int page_offset, page_length; |
563 | int ret; | |
673a394b EA |
564 | |
565 | user_data = (char __user *) (uintptr_t) args->data_ptr; | |
566 | remain = args->size; | |
567 | if (!access_ok(VERIFY_READ, user_data, remain)) | |
568 | return -EFAULT; | |
569 | ||
570 | ||
571 | mutex_lock(&dev->struct_mutex); | |
572 | ret = i915_gem_object_pin(obj, 0); | |
573 | if (ret) { | |
574 | mutex_unlock(&dev->struct_mutex); | |
575 | return ret; | |
576 | } | |
2ef7eeaa | 577 | ret = i915_gem_object_set_to_gtt_domain(obj, 1); |
673a394b EA |
578 | if (ret) |
579 | goto fail; | |
580 | ||
581 | obj_priv = obj->driver_private; | |
582 | offset = obj_priv->gtt_offset + args->offset; | |
673a394b EA |
583 | |
584 | while (remain > 0) { | |
585 | /* Operation in this page | |
586 | * | |
0839ccb8 KP |
587 | * page_base = page offset within aperture |
588 | * page_offset = offset within page | |
589 | * page_length = bytes to copy for this page | |
673a394b | 590 | */ |
0839ccb8 KP |
591 | page_base = (offset & ~(PAGE_SIZE-1)); |
592 | page_offset = offset & (PAGE_SIZE-1); | |
593 | page_length = remain; | |
594 | if ((page_offset + remain) > PAGE_SIZE) | |
595 | page_length = PAGE_SIZE - page_offset; | |
596 | ||
597 | ret = fast_user_write (dev_priv->mm.gtt_mapping, page_base, | |
598 | page_offset, user_data, page_length); | |
599 | ||
600 | /* If we get a fault while copying data, then (presumably) our | |
3de09aa3 EA |
601 | * source page isn't available. Return the error and we'll |
602 | * retry in the slow path. | |
0839ccb8 | 603 | */ |
3de09aa3 EA |
604 | if (ret) |
605 | goto fail; | |
673a394b | 606 | |
0839ccb8 KP |
607 | remain -= page_length; |
608 | user_data += page_length; | |
609 | offset += page_length; | |
673a394b | 610 | } |
673a394b EA |
611 | |
612 | fail: | |
613 | i915_gem_object_unpin(obj); | |
614 | mutex_unlock(&dev->struct_mutex); | |
615 | ||
616 | return ret; | |
617 | } | |
618 | ||
3de09aa3 EA |
619 | /** |
620 | * This is the fallback GTT pwrite path, which uses get_user_pages to pin | |
621 | * the memory and maps it using kmap_atomic for copying. | |
622 | * | |
623 | * This code resulted in x11perf -rgb10text consuming about 10% more CPU | |
624 | * than using i915_gem_gtt_pwrite_fast on a G45 (32-bit). | |
625 | */ | |
3043c60c | 626 | static int |
3de09aa3 EA |
627 | i915_gem_gtt_pwrite_slow(struct drm_device *dev, struct drm_gem_object *obj, |
628 | struct drm_i915_gem_pwrite *args, | |
629 | struct drm_file *file_priv) | |
673a394b | 630 | { |
3de09aa3 EA |
631 | struct drm_i915_gem_object *obj_priv = obj->driver_private; |
632 | drm_i915_private_t *dev_priv = dev->dev_private; | |
633 | ssize_t remain; | |
634 | loff_t gtt_page_base, offset; | |
635 | loff_t first_data_page, last_data_page, num_pages; | |
636 | loff_t pinned_pages, i; | |
637 | struct page **user_pages; | |
638 | struct mm_struct *mm = current->mm; | |
639 | int gtt_page_offset, data_page_offset, data_page_index, page_length; | |
673a394b | 640 | int ret; |
3de09aa3 EA |
641 | uint64_t data_ptr = args->data_ptr; |
642 | ||
643 | remain = args->size; | |
644 | ||
645 | /* Pin the user pages containing the data. We can't fault while | |
646 | * holding the struct mutex, and all of the pwrite implementations | |
647 | * want to hold it while dereferencing the user data. | |
648 | */ | |
649 | first_data_page = data_ptr / PAGE_SIZE; | |
650 | last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE; | |
651 | num_pages = last_data_page - first_data_page + 1; | |
652 | ||
8e7d2b2c | 653 | user_pages = drm_calloc_large(num_pages, sizeof(struct page *)); |
3de09aa3 EA |
654 | if (user_pages == NULL) |
655 | return -ENOMEM; | |
656 | ||
657 | down_read(&mm->mmap_sem); | |
658 | pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr, | |
659 | num_pages, 0, 0, user_pages, NULL); | |
660 | up_read(&mm->mmap_sem); | |
661 | if (pinned_pages < num_pages) { | |
662 | ret = -EFAULT; | |
663 | goto out_unpin_pages; | |
664 | } | |
673a394b EA |
665 | |
666 | mutex_lock(&dev->struct_mutex); | |
3de09aa3 EA |
667 | ret = i915_gem_object_pin(obj, 0); |
668 | if (ret) | |
669 | goto out_unlock; | |
670 | ||
671 | ret = i915_gem_object_set_to_gtt_domain(obj, 1); | |
672 | if (ret) | |
673 | goto out_unpin_object; | |
674 | ||
675 | obj_priv = obj->driver_private; | |
676 | offset = obj_priv->gtt_offset + args->offset; | |
677 | ||
678 | while (remain > 0) { | |
679 | /* Operation in this page | |
680 | * | |
681 | * gtt_page_base = page offset within aperture | |
682 | * gtt_page_offset = offset within page in aperture | |
683 | * data_page_index = page number in get_user_pages return | |
684 | * data_page_offset = offset with data_page_index page. | |
685 | * page_length = bytes to copy for this page | |
686 | */ | |
687 | gtt_page_base = offset & PAGE_MASK; | |
688 | gtt_page_offset = offset & ~PAGE_MASK; | |
689 | data_page_index = data_ptr / PAGE_SIZE - first_data_page; | |
690 | data_page_offset = data_ptr & ~PAGE_MASK; | |
691 | ||
692 | page_length = remain; | |
693 | if ((gtt_page_offset + page_length) > PAGE_SIZE) | |
694 | page_length = PAGE_SIZE - gtt_page_offset; | |
695 | if ((data_page_offset + page_length) > PAGE_SIZE) | |
696 | page_length = PAGE_SIZE - data_page_offset; | |
697 | ||
698 | ret = slow_kernel_write(dev_priv->mm.gtt_mapping, | |
699 | gtt_page_base, gtt_page_offset, | |
700 | user_pages[data_page_index], | |
701 | data_page_offset, | |
702 | page_length); | |
703 | ||
704 | /* If we get a fault while copying data, then (presumably) our | |
705 | * source page isn't available. Return the error and we'll | |
706 | * retry in the slow path. | |
707 | */ | |
708 | if (ret) | |
709 | goto out_unpin_object; | |
710 | ||
711 | remain -= page_length; | |
712 | offset += page_length; | |
713 | data_ptr += page_length; | |
714 | } | |
715 | ||
716 | out_unpin_object: | |
717 | i915_gem_object_unpin(obj); | |
718 | out_unlock: | |
719 | mutex_unlock(&dev->struct_mutex); | |
720 | out_unpin_pages: | |
721 | for (i = 0; i < pinned_pages; i++) | |
722 | page_cache_release(user_pages[i]); | |
8e7d2b2c | 723 | drm_free_large(user_pages); |
3de09aa3 EA |
724 | |
725 | return ret; | |
726 | } | |
727 | ||
40123c1f EA |
728 | /** |
729 | * This is the fast shmem pwrite path, which attempts to directly | |
730 | * copy_from_user into the kmapped pages backing the object. | |
731 | */ | |
3043c60c | 732 | static int |
40123c1f EA |
733 | i915_gem_shmem_pwrite_fast(struct drm_device *dev, struct drm_gem_object *obj, |
734 | struct drm_i915_gem_pwrite *args, | |
735 | struct drm_file *file_priv) | |
673a394b | 736 | { |
40123c1f EA |
737 | struct drm_i915_gem_object *obj_priv = obj->driver_private; |
738 | ssize_t remain; | |
739 | loff_t offset, page_base; | |
740 | char __user *user_data; | |
741 | int page_offset, page_length; | |
673a394b | 742 | int ret; |
40123c1f EA |
743 | |
744 | user_data = (char __user *) (uintptr_t) args->data_ptr; | |
745 | remain = args->size; | |
673a394b EA |
746 | |
747 | mutex_lock(&dev->struct_mutex); | |
748 | ||
40123c1f EA |
749 | ret = i915_gem_object_get_pages(obj); |
750 | if (ret != 0) | |
751 | goto fail_unlock; | |
673a394b | 752 | |
e47c68e9 | 753 | ret = i915_gem_object_set_to_cpu_domain(obj, 1); |
40123c1f EA |
754 | if (ret != 0) |
755 | goto fail_put_pages; | |
756 | ||
757 | obj_priv = obj->driver_private; | |
758 | offset = args->offset; | |
759 | obj_priv->dirty = 1; | |
760 | ||
761 | while (remain > 0) { | |
762 | /* Operation in this page | |
763 | * | |
764 | * page_base = page offset within aperture | |
765 | * page_offset = offset within page | |
766 | * page_length = bytes to copy for this page | |
767 | */ | |
768 | page_base = (offset & ~(PAGE_SIZE-1)); | |
769 | page_offset = offset & (PAGE_SIZE-1); | |
770 | page_length = remain; | |
771 | if ((page_offset + remain) > PAGE_SIZE) | |
772 | page_length = PAGE_SIZE - page_offset; | |
773 | ||
774 | ret = fast_shmem_write(obj_priv->pages, | |
775 | page_base, page_offset, | |
776 | user_data, page_length); | |
777 | if (ret) | |
778 | goto fail_put_pages; | |
779 | ||
780 | remain -= page_length; | |
781 | user_data += page_length; | |
782 | offset += page_length; | |
783 | } | |
784 | ||
785 | fail_put_pages: | |
786 | i915_gem_object_put_pages(obj); | |
787 | fail_unlock: | |
788 | mutex_unlock(&dev->struct_mutex); | |
789 | ||
790 | return ret; | |
791 | } | |
792 | ||
793 | /** | |
794 | * This is the fallback shmem pwrite path, which uses get_user_pages to pin | |
795 | * the memory and maps it using kmap_atomic for copying. | |
796 | * | |
797 | * This avoids taking mmap_sem for faulting on the user's address while the | |
798 | * struct_mutex is held. | |
799 | */ | |
800 | static int | |
801 | i915_gem_shmem_pwrite_slow(struct drm_device *dev, struct drm_gem_object *obj, | |
802 | struct drm_i915_gem_pwrite *args, | |
803 | struct drm_file *file_priv) | |
804 | { | |
805 | struct drm_i915_gem_object *obj_priv = obj->driver_private; | |
806 | struct mm_struct *mm = current->mm; | |
807 | struct page **user_pages; | |
808 | ssize_t remain; | |
809 | loff_t offset, pinned_pages, i; | |
810 | loff_t first_data_page, last_data_page, num_pages; | |
811 | int shmem_page_index, shmem_page_offset; | |
812 | int data_page_index, data_page_offset; | |
813 | int page_length; | |
814 | int ret; | |
815 | uint64_t data_ptr = args->data_ptr; | |
280b713b | 816 | int do_bit17_swizzling; |
40123c1f EA |
817 | |
818 | remain = args->size; | |
819 | ||
820 | /* Pin the user pages containing the data. We can't fault while | |
821 | * holding the struct mutex, and all of the pwrite implementations | |
822 | * want to hold it while dereferencing the user data. | |
823 | */ | |
824 | first_data_page = data_ptr / PAGE_SIZE; | |
825 | last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE; | |
826 | num_pages = last_data_page - first_data_page + 1; | |
827 | ||
8e7d2b2c | 828 | user_pages = drm_calloc_large(num_pages, sizeof(struct page *)); |
40123c1f EA |
829 | if (user_pages == NULL) |
830 | return -ENOMEM; | |
831 | ||
832 | down_read(&mm->mmap_sem); | |
833 | pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr, | |
834 | num_pages, 0, 0, user_pages, NULL); | |
835 | up_read(&mm->mmap_sem); | |
836 | if (pinned_pages < num_pages) { | |
837 | ret = -EFAULT; | |
838 | goto fail_put_user_pages; | |
673a394b EA |
839 | } |
840 | ||
280b713b EA |
841 | do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj); |
842 | ||
40123c1f EA |
843 | mutex_lock(&dev->struct_mutex); |
844 | ||
845 | ret = i915_gem_object_get_pages(obj); | |
846 | if (ret != 0) | |
847 | goto fail_unlock; | |
848 | ||
849 | ret = i915_gem_object_set_to_cpu_domain(obj, 1); | |
850 | if (ret != 0) | |
851 | goto fail_put_pages; | |
852 | ||
853 | obj_priv = obj->driver_private; | |
673a394b | 854 | offset = args->offset; |
40123c1f | 855 | obj_priv->dirty = 1; |
673a394b | 856 | |
40123c1f EA |
857 | while (remain > 0) { |
858 | /* Operation in this page | |
859 | * | |
860 | * shmem_page_index = page number within shmem file | |
861 | * shmem_page_offset = offset within page in shmem file | |
862 | * data_page_index = page number in get_user_pages return | |
863 | * data_page_offset = offset with data_page_index page. | |
864 | * page_length = bytes to copy for this page | |
865 | */ | |
866 | shmem_page_index = offset / PAGE_SIZE; | |
867 | shmem_page_offset = offset & ~PAGE_MASK; | |
868 | data_page_index = data_ptr / PAGE_SIZE - first_data_page; | |
869 | data_page_offset = data_ptr & ~PAGE_MASK; | |
870 | ||
871 | page_length = remain; | |
872 | if ((shmem_page_offset + page_length) > PAGE_SIZE) | |
873 | page_length = PAGE_SIZE - shmem_page_offset; | |
874 | if ((data_page_offset + page_length) > PAGE_SIZE) | |
875 | page_length = PAGE_SIZE - data_page_offset; | |
876 | ||
280b713b EA |
877 | if (do_bit17_swizzling) { |
878 | ret = slow_shmem_bit17_copy(obj_priv->pages[shmem_page_index], | |
879 | shmem_page_offset, | |
880 | user_pages[data_page_index], | |
881 | data_page_offset, | |
882 | page_length, | |
883 | 0); | |
884 | } else { | |
885 | ret = slow_shmem_copy(obj_priv->pages[shmem_page_index], | |
886 | shmem_page_offset, | |
887 | user_pages[data_page_index], | |
888 | data_page_offset, | |
889 | page_length); | |
890 | } | |
40123c1f EA |
891 | if (ret) |
892 | goto fail_put_pages; | |
893 | ||
894 | remain -= page_length; | |
895 | data_ptr += page_length; | |
896 | offset += page_length; | |
673a394b EA |
897 | } |
898 | ||
40123c1f EA |
899 | fail_put_pages: |
900 | i915_gem_object_put_pages(obj); | |
901 | fail_unlock: | |
673a394b | 902 | mutex_unlock(&dev->struct_mutex); |
40123c1f EA |
903 | fail_put_user_pages: |
904 | for (i = 0; i < pinned_pages; i++) | |
905 | page_cache_release(user_pages[i]); | |
8e7d2b2c | 906 | drm_free_large(user_pages); |
673a394b | 907 | |
40123c1f | 908 | return ret; |
673a394b EA |
909 | } |
910 | ||
911 | /** | |
912 | * Writes data to the object referenced by handle. | |
913 | * | |
914 | * On error, the contents of the buffer that were to be modified are undefined. | |
915 | */ | |
916 | int | |
917 | i915_gem_pwrite_ioctl(struct drm_device *dev, void *data, | |
918 | struct drm_file *file_priv) | |
919 | { | |
920 | struct drm_i915_gem_pwrite *args = data; | |
921 | struct drm_gem_object *obj; | |
922 | struct drm_i915_gem_object *obj_priv; | |
923 | int ret = 0; | |
924 | ||
925 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); | |
926 | if (obj == NULL) | |
927 | return -EBADF; | |
928 | obj_priv = obj->driver_private; | |
929 | ||
930 | /* Bounds check destination. | |
931 | * | |
932 | * XXX: This could use review for overflow issues... | |
933 | */ | |
934 | if (args->offset > obj->size || args->size > obj->size || | |
935 | args->offset + args->size > obj->size) { | |
936 | drm_gem_object_unreference(obj); | |
937 | return -EINVAL; | |
938 | } | |
939 | ||
940 | /* We can only do the GTT pwrite on untiled buffers, as otherwise | |
941 | * it would end up going through the fenced access, and we'll get | |
942 | * different detiling behavior between reading and writing. | |
943 | * pread/pwrite currently are reading and writing from the CPU | |
944 | * perspective, requiring manual detiling by the client. | |
945 | */ | |
71acb5eb DA |
946 | if (obj_priv->phys_obj) |
947 | ret = i915_gem_phys_pwrite(dev, obj, args, file_priv); | |
948 | else if (obj_priv->tiling_mode == I915_TILING_NONE && | |
3de09aa3 EA |
949 | dev->gtt_total != 0) { |
950 | ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file_priv); | |
951 | if (ret == -EFAULT) { | |
952 | ret = i915_gem_gtt_pwrite_slow(dev, obj, args, | |
953 | file_priv); | |
954 | } | |
280b713b EA |
955 | } else if (i915_gem_object_needs_bit17_swizzle(obj)) { |
956 | ret = i915_gem_shmem_pwrite_slow(dev, obj, args, file_priv); | |
40123c1f EA |
957 | } else { |
958 | ret = i915_gem_shmem_pwrite_fast(dev, obj, args, file_priv); | |
959 | if (ret == -EFAULT) { | |
960 | ret = i915_gem_shmem_pwrite_slow(dev, obj, args, | |
961 | file_priv); | |
962 | } | |
963 | } | |
673a394b EA |
964 | |
965 | #if WATCH_PWRITE | |
966 | if (ret) | |
967 | DRM_INFO("pwrite failed %d\n", ret); | |
968 | #endif | |
969 | ||
970 | drm_gem_object_unreference(obj); | |
971 | ||
972 | return ret; | |
973 | } | |
974 | ||
975 | /** | |
2ef7eeaa EA |
976 | * Called when user space prepares to use an object with the CPU, either |
977 | * through the mmap ioctl's mapping or a GTT mapping. | |
673a394b EA |
978 | */ |
979 | int | |
980 | i915_gem_set_domain_ioctl(struct drm_device *dev, void *data, | |
981 | struct drm_file *file_priv) | |
982 | { | |
a09ba7fa | 983 | struct drm_i915_private *dev_priv = dev->dev_private; |
673a394b EA |
984 | struct drm_i915_gem_set_domain *args = data; |
985 | struct drm_gem_object *obj; | |
652c393a | 986 | struct drm_i915_gem_object *obj_priv; |
2ef7eeaa EA |
987 | uint32_t read_domains = args->read_domains; |
988 | uint32_t write_domain = args->write_domain; | |
673a394b EA |
989 | int ret; |
990 | ||
991 | if (!(dev->driver->driver_features & DRIVER_GEM)) | |
992 | return -ENODEV; | |
993 | ||
2ef7eeaa | 994 | /* Only handle setting domains to types used by the CPU. */ |
21d509e3 | 995 | if (write_domain & I915_GEM_GPU_DOMAINS) |
2ef7eeaa EA |
996 | return -EINVAL; |
997 | ||
21d509e3 | 998 | if (read_domains & I915_GEM_GPU_DOMAINS) |
2ef7eeaa EA |
999 | return -EINVAL; |
1000 | ||
1001 | /* Having something in the write domain implies it's in the read | |
1002 | * domain, and only that read domain. Enforce that in the request. | |
1003 | */ | |
1004 | if (write_domain != 0 && read_domains != write_domain) | |
1005 | return -EINVAL; | |
1006 | ||
673a394b EA |
1007 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); |
1008 | if (obj == NULL) | |
1009 | return -EBADF; | |
652c393a | 1010 | obj_priv = obj->driver_private; |
673a394b EA |
1011 | |
1012 | mutex_lock(&dev->struct_mutex); | |
652c393a JB |
1013 | |
1014 | intel_mark_busy(dev, obj); | |
1015 | ||
673a394b | 1016 | #if WATCH_BUF |
cfd43c02 | 1017 | DRM_INFO("set_domain_ioctl %p(%zd), %08x %08x\n", |
2ef7eeaa | 1018 | obj, obj->size, read_domains, write_domain); |
673a394b | 1019 | #endif |
2ef7eeaa EA |
1020 | if (read_domains & I915_GEM_DOMAIN_GTT) { |
1021 | ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0); | |
02354392 | 1022 | |
a09ba7fa EA |
1023 | /* Update the LRU on the fence for the CPU access that's |
1024 | * about to occur. | |
1025 | */ | |
1026 | if (obj_priv->fence_reg != I915_FENCE_REG_NONE) { | |
1027 | list_move_tail(&obj_priv->fence_list, | |
1028 | &dev_priv->mm.fence_list); | |
1029 | } | |
1030 | ||
02354392 EA |
1031 | /* Silently promote "you're not bound, there was nothing to do" |
1032 | * to success, since the client was just asking us to | |
1033 | * make sure everything was done. | |
1034 | */ | |
1035 | if (ret == -EINVAL) | |
1036 | ret = 0; | |
2ef7eeaa | 1037 | } else { |
e47c68e9 | 1038 | ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0); |
2ef7eeaa EA |
1039 | } |
1040 | ||
673a394b EA |
1041 | drm_gem_object_unreference(obj); |
1042 | mutex_unlock(&dev->struct_mutex); | |
1043 | return ret; | |
1044 | } | |
1045 | ||
1046 | /** | |
1047 | * Called when user space has done writes to this buffer | |
1048 | */ | |
1049 | int | |
1050 | i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data, | |
1051 | struct drm_file *file_priv) | |
1052 | { | |
1053 | struct drm_i915_gem_sw_finish *args = data; | |
1054 | struct drm_gem_object *obj; | |
1055 | struct drm_i915_gem_object *obj_priv; | |
1056 | int ret = 0; | |
1057 | ||
1058 | if (!(dev->driver->driver_features & DRIVER_GEM)) | |
1059 | return -ENODEV; | |
1060 | ||
1061 | mutex_lock(&dev->struct_mutex); | |
1062 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); | |
1063 | if (obj == NULL) { | |
1064 | mutex_unlock(&dev->struct_mutex); | |
1065 | return -EBADF; | |
1066 | } | |
1067 | ||
1068 | #if WATCH_BUF | |
cfd43c02 | 1069 | DRM_INFO("%s: sw_finish %d (%p %zd)\n", |
673a394b EA |
1070 | __func__, args->handle, obj, obj->size); |
1071 | #endif | |
1072 | obj_priv = obj->driver_private; | |
1073 | ||
1074 | /* Pinned buffers may be scanout, so flush the cache */ | |
e47c68e9 EA |
1075 | if (obj_priv->pin_count) |
1076 | i915_gem_object_flush_cpu_write_domain(obj); | |
1077 | ||
673a394b EA |
1078 | drm_gem_object_unreference(obj); |
1079 | mutex_unlock(&dev->struct_mutex); | |
1080 | return ret; | |
1081 | } | |
1082 | ||
1083 | /** | |
1084 | * Maps the contents of an object, returning the address it is mapped | |
1085 | * into. | |
1086 | * | |
1087 | * While the mapping holds a reference on the contents of the object, it doesn't | |
1088 | * imply a ref on the object itself. | |
1089 | */ | |
1090 | int | |
1091 | i915_gem_mmap_ioctl(struct drm_device *dev, void *data, | |
1092 | struct drm_file *file_priv) | |
1093 | { | |
1094 | struct drm_i915_gem_mmap *args = data; | |
1095 | struct drm_gem_object *obj; | |
1096 | loff_t offset; | |
1097 | unsigned long addr; | |
1098 | ||
1099 | if (!(dev->driver->driver_features & DRIVER_GEM)) | |
1100 | return -ENODEV; | |
1101 | ||
1102 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); | |
1103 | if (obj == NULL) | |
1104 | return -EBADF; | |
1105 | ||
1106 | offset = args->offset; | |
1107 | ||
1108 | down_write(¤t->mm->mmap_sem); | |
1109 | addr = do_mmap(obj->filp, 0, args->size, | |
1110 | PROT_READ | PROT_WRITE, MAP_SHARED, | |
1111 | args->offset); | |
1112 | up_write(¤t->mm->mmap_sem); | |
1113 | mutex_lock(&dev->struct_mutex); | |
1114 | drm_gem_object_unreference(obj); | |
1115 | mutex_unlock(&dev->struct_mutex); | |
1116 | if (IS_ERR((void *)addr)) | |
1117 | return addr; | |
1118 | ||
1119 | args->addr_ptr = (uint64_t) addr; | |
1120 | ||
1121 | return 0; | |
1122 | } | |
1123 | ||
de151cf6 JB |
1124 | /** |
1125 | * i915_gem_fault - fault a page into the GTT | |
1126 | * vma: VMA in question | |
1127 | * vmf: fault info | |
1128 | * | |
1129 | * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped | |
1130 | * from userspace. The fault handler takes care of binding the object to | |
1131 | * the GTT (if needed), allocating and programming a fence register (again, | |
1132 | * only if needed based on whether the old reg is still valid or the object | |
1133 | * is tiled) and inserting a new PTE into the faulting process. | |
1134 | * | |
1135 | * Note that the faulting process may involve evicting existing objects | |
1136 | * from the GTT and/or fence registers to make room. So performance may | |
1137 | * suffer if the GTT working set is large or there are few fence registers | |
1138 | * left. | |
1139 | */ | |
1140 | int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf) | |
1141 | { | |
1142 | struct drm_gem_object *obj = vma->vm_private_data; | |
1143 | struct drm_device *dev = obj->dev; | |
1144 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1145 | struct drm_i915_gem_object *obj_priv = obj->driver_private; | |
1146 | pgoff_t page_offset; | |
1147 | unsigned long pfn; | |
1148 | int ret = 0; | |
0f973f27 | 1149 | bool write = !!(vmf->flags & FAULT_FLAG_WRITE); |
de151cf6 JB |
1150 | |
1151 | /* We don't use vmf->pgoff since that has the fake offset */ | |
1152 | page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >> | |
1153 | PAGE_SHIFT; | |
1154 | ||
1155 | /* Now bind it into the GTT if needed */ | |
1156 | mutex_lock(&dev->struct_mutex); | |
1157 | if (!obj_priv->gtt_space) { | |
1158 | ret = i915_gem_object_bind_to_gtt(obj, obj_priv->gtt_alignment); | |
1159 | if (ret) { | |
1160 | mutex_unlock(&dev->struct_mutex); | |
1161 | return VM_FAULT_SIGBUS; | |
1162 | } | |
07f4f3e8 KH |
1163 | |
1164 | ret = i915_gem_object_set_to_gtt_domain(obj, write); | |
1165 | if (ret) { | |
1166 | mutex_unlock(&dev->struct_mutex); | |
1167 | return VM_FAULT_SIGBUS; | |
1168 | } | |
1169 | ||
14b60391 | 1170 | list_add_tail(&obj_priv->list, &dev_priv->mm.inactive_list); |
de151cf6 JB |
1171 | } |
1172 | ||
1173 | /* Need a new fence register? */ | |
a09ba7fa | 1174 | if (obj_priv->tiling_mode != I915_TILING_NONE) { |
8c4b8c3f | 1175 | ret = i915_gem_object_get_fence_reg(obj); |
7d8d58b2 CW |
1176 | if (ret) { |
1177 | mutex_unlock(&dev->struct_mutex); | |
d9ddcb96 | 1178 | return VM_FAULT_SIGBUS; |
7d8d58b2 | 1179 | } |
d9ddcb96 | 1180 | } |
de151cf6 JB |
1181 | |
1182 | pfn = ((dev->agp->base + obj_priv->gtt_offset) >> PAGE_SHIFT) + | |
1183 | page_offset; | |
1184 | ||
1185 | /* Finally, remap it using the new GTT offset */ | |
1186 | ret = vm_insert_pfn(vma, (unsigned long)vmf->virtual_address, pfn); | |
1187 | ||
1188 | mutex_unlock(&dev->struct_mutex); | |
1189 | ||
1190 | switch (ret) { | |
1191 | case -ENOMEM: | |
1192 | case -EAGAIN: | |
1193 | return VM_FAULT_OOM; | |
1194 | case -EFAULT: | |
959b887c | 1195 | case -EINVAL: |
de151cf6 JB |
1196 | return VM_FAULT_SIGBUS; |
1197 | default: | |
1198 | return VM_FAULT_NOPAGE; | |
1199 | } | |
1200 | } | |
1201 | ||
1202 | /** | |
1203 | * i915_gem_create_mmap_offset - create a fake mmap offset for an object | |
1204 | * @obj: obj in question | |
1205 | * | |
1206 | * GEM memory mapping works by handing back to userspace a fake mmap offset | |
1207 | * it can use in a subsequent mmap(2) call. The DRM core code then looks | |
1208 | * up the object based on the offset and sets up the various memory mapping | |
1209 | * structures. | |
1210 | * | |
1211 | * This routine allocates and attaches a fake offset for @obj. | |
1212 | */ | |
1213 | static int | |
1214 | i915_gem_create_mmap_offset(struct drm_gem_object *obj) | |
1215 | { | |
1216 | struct drm_device *dev = obj->dev; | |
1217 | struct drm_gem_mm *mm = dev->mm_private; | |
1218 | struct drm_i915_gem_object *obj_priv = obj->driver_private; | |
1219 | struct drm_map_list *list; | |
f77d390c | 1220 | struct drm_local_map *map; |
de151cf6 JB |
1221 | int ret = 0; |
1222 | ||
1223 | /* Set the object up for mmap'ing */ | |
1224 | list = &obj->map_list; | |
9a298b2a | 1225 | list->map = kzalloc(sizeof(struct drm_map_list), GFP_KERNEL); |
de151cf6 JB |
1226 | if (!list->map) |
1227 | return -ENOMEM; | |
1228 | ||
1229 | map = list->map; | |
1230 | map->type = _DRM_GEM; | |
1231 | map->size = obj->size; | |
1232 | map->handle = obj; | |
1233 | ||
1234 | /* Get a DRM GEM mmap offset allocated... */ | |
1235 | list->file_offset_node = drm_mm_search_free(&mm->offset_manager, | |
1236 | obj->size / PAGE_SIZE, 0, 0); | |
1237 | if (!list->file_offset_node) { | |
1238 | DRM_ERROR("failed to allocate offset for bo %d\n", obj->name); | |
1239 | ret = -ENOMEM; | |
1240 | goto out_free_list; | |
1241 | } | |
1242 | ||
1243 | list->file_offset_node = drm_mm_get_block(list->file_offset_node, | |
1244 | obj->size / PAGE_SIZE, 0); | |
1245 | if (!list->file_offset_node) { | |
1246 | ret = -ENOMEM; | |
1247 | goto out_free_list; | |
1248 | } | |
1249 | ||
1250 | list->hash.key = list->file_offset_node->start; | |
1251 | if (drm_ht_insert_item(&mm->offset_hash, &list->hash)) { | |
1252 | DRM_ERROR("failed to add to map hash\n"); | |
1253 | goto out_free_mm; | |
1254 | } | |
1255 | ||
1256 | /* By now we should be all set, any drm_mmap request on the offset | |
1257 | * below will get to our mmap & fault handler */ | |
1258 | obj_priv->mmap_offset = ((uint64_t) list->hash.key) << PAGE_SHIFT; | |
1259 | ||
1260 | return 0; | |
1261 | ||
1262 | out_free_mm: | |
1263 | drm_mm_put_block(list->file_offset_node); | |
1264 | out_free_list: | |
9a298b2a | 1265 | kfree(list->map); |
de151cf6 JB |
1266 | |
1267 | return ret; | |
1268 | } | |
1269 | ||
901782b2 CW |
1270 | /** |
1271 | * i915_gem_release_mmap - remove physical page mappings | |
1272 | * @obj: obj in question | |
1273 | * | |
1274 | * Preserve the reservation of the mmaping with the DRM core code, but | |
1275 | * relinquish ownership of the pages back to the system. | |
1276 | * | |
1277 | * It is vital that we remove the page mapping if we have mapped a tiled | |
1278 | * object through the GTT and then lose the fence register due to | |
1279 | * resource pressure. Similarly if the object has been moved out of the | |
1280 | * aperture, than pages mapped into userspace must be revoked. Removing the | |
1281 | * mapping will then trigger a page fault on the next user access, allowing | |
1282 | * fixup by i915_gem_fault(). | |
1283 | */ | |
d05ca301 | 1284 | void |
901782b2 CW |
1285 | i915_gem_release_mmap(struct drm_gem_object *obj) |
1286 | { | |
1287 | struct drm_device *dev = obj->dev; | |
1288 | struct drm_i915_gem_object *obj_priv = obj->driver_private; | |
1289 | ||
1290 | if (dev->dev_mapping) | |
1291 | unmap_mapping_range(dev->dev_mapping, | |
1292 | obj_priv->mmap_offset, obj->size, 1); | |
1293 | } | |
1294 | ||
ab00b3e5 JB |
1295 | static void |
1296 | i915_gem_free_mmap_offset(struct drm_gem_object *obj) | |
1297 | { | |
1298 | struct drm_device *dev = obj->dev; | |
1299 | struct drm_i915_gem_object *obj_priv = obj->driver_private; | |
1300 | struct drm_gem_mm *mm = dev->mm_private; | |
1301 | struct drm_map_list *list; | |
1302 | ||
1303 | list = &obj->map_list; | |
1304 | drm_ht_remove_item(&mm->offset_hash, &list->hash); | |
1305 | ||
1306 | if (list->file_offset_node) { | |
1307 | drm_mm_put_block(list->file_offset_node); | |
1308 | list->file_offset_node = NULL; | |
1309 | } | |
1310 | ||
1311 | if (list->map) { | |
9a298b2a | 1312 | kfree(list->map); |
ab00b3e5 JB |
1313 | list->map = NULL; |
1314 | } | |
1315 | ||
1316 | obj_priv->mmap_offset = 0; | |
1317 | } | |
1318 | ||
de151cf6 JB |
1319 | /** |
1320 | * i915_gem_get_gtt_alignment - return required GTT alignment for an object | |
1321 | * @obj: object to check | |
1322 | * | |
1323 | * Return the required GTT alignment for an object, taking into account | |
1324 | * potential fence register mapping if needed. | |
1325 | */ | |
1326 | static uint32_t | |
1327 | i915_gem_get_gtt_alignment(struct drm_gem_object *obj) | |
1328 | { | |
1329 | struct drm_device *dev = obj->dev; | |
1330 | struct drm_i915_gem_object *obj_priv = obj->driver_private; | |
1331 | int start, i; | |
1332 | ||
1333 | /* | |
1334 | * Minimum alignment is 4k (GTT page size), but might be greater | |
1335 | * if a fence register is needed for the object. | |
1336 | */ | |
1337 | if (IS_I965G(dev) || obj_priv->tiling_mode == I915_TILING_NONE) | |
1338 | return 4096; | |
1339 | ||
1340 | /* | |
1341 | * Previous chips need to be aligned to the size of the smallest | |
1342 | * fence register that can contain the object. | |
1343 | */ | |
1344 | if (IS_I9XX(dev)) | |
1345 | start = 1024*1024; | |
1346 | else | |
1347 | start = 512*1024; | |
1348 | ||
1349 | for (i = start; i < obj->size; i <<= 1) | |
1350 | ; | |
1351 | ||
1352 | return i; | |
1353 | } | |
1354 | ||
1355 | /** | |
1356 | * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing | |
1357 | * @dev: DRM device | |
1358 | * @data: GTT mapping ioctl data | |
1359 | * @file_priv: GEM object info | |
1360 | * | |
1361 | * Simply returns the fake offset to userspace so it can mmap it. | |
1362 | * The mmap call will end up in drm_gem_mmap(), which will set things | |
1363 | * up so we can get faults in the handler above. | |
1364 | * | |
1365 | * The fault handler will take care of binding the object into the GTT | |
1366 | * (since it may have been evicted to make room for something), allocating | |
1367 | * a fence register, and mapping the appropriate aperture address into | |
1368 | * userspace. | |
1369 | */ | |
1370 | int | |
1371 | i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data, | |
1372 | struct drm_file *file_priv) | |
1373 | { | |
1374 | struct drm_i915_gem_mmap_gtt *args = data; | |
1375 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1376 | struct drm_gem_object *obj; | |
1377 | struct drm_i915_gem_object *obj_priv; | |
1378 | int ret; | |
1379 | ||
1380 | if (!(dev->driver->driver_features & DRIVER_GEM)) | |
1381 | return -ENODEV; | |
1382 | ||
1383 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); | |
1384 | if (obj == NULL) | |
1385 | return -EBADF; | |
1386 | ||
1387 | mutex_lock(&dev->struct_mutex); | |
1388 | ||
1389 | obj_priv = obj->driver_private; | |
1390 | ||
1391 | if (!obj_priv->mmap_offset) { | |
1392 | ret = i915_gem_create_mmap_offset(obj); | |
13af1062 CW |
1393 | if (ret) { |
1394 | drm_gem_object_unreference(obj); | |
1395 | mutex_unlock(&dev->struct_mutex); | |
de151cf6 | 1396 | return ret; |
13af1062 | 1397 | } |
de151cf6 JB |
1398 | } |
1399 | ||
1400 | args->offset = obj_priv->mmap_offset; | |
1401 | ||
1402 | obj_priv->gtt_alignment = i915_gem_get_gtt_alignment(obj); | |
1403 | ||
1404 | /* Make sure the alignment is correct for fence regs etc */ | |
1405 | if (obj_priv->agp_mem && | |
1406 | (obj_priv->gtt_offset & (obj_priv->gtt_alignment - 1))) { | |
1407 | drm_gem_object_unreference(obj); | |
1408 | mutex_unlock(&dev->struct_mutex); | |
1409 | return -EINVAL; | |
1410 | } | |
1411 | ||
1412 | /* | |
1413 | * Pull it into the GTT so that we have a page list (makes the | |
1414 | * initial fault faster and any subsequent flushing possible). | |
1415 | */ | |
1416 | if (!obj_priv->agp_mem) { | |
1417 | ret = i915_gem_object_bind_to_gtt(obj, obj_priv->gtt_alignment); | |
1418 | if (ret) { | |
1419 | drm_gem_object_unreference(obj); | |
1420 | mutex_unlock(&dev->struct_mutex); | |
1421 | return ret; | |
1422 | } | |
14b60391 | 1423 | list_add_tail(&obj_priv->list, &dev_priv->mm.inactive_list); |
de151cf6 JB |
1424 | } |
1425 | ||
1426 | drm_gem_object_unreference(obj); | |
1427 | mutex_unlock(&dev->struct_mutex); | |
1428 | ||
1429 | return 0; | |
1430 | } | |
1431 | ||
6911a9b8 | 1432 | void |
856fa198 | 1433 | i915_gem_object_put_pages(struct drm_gem_object *obj) |
673a394b EA |
1434 | { |
1435 | struct drm_i915_gem_object *obj_priv = obj->driver_private; | |
1436 | int page_count = obj->size / PAGE_SIZE; | |
1437 | int i; | |
1438 | ||
856fa198 | 1439 | BUG_ON(obj_priv->pages_refcount == 0); |
673a394b | 1440 | |
856fa198 EA |
1441 | if (--obj_priv->pages_refcount != 0) |
1442 | return; | |
673a394b | 1443 | |
280b713b EA |
1444 | if (obj_priv->tiling_mode != I915_TILING_NONE) |
1445 | i915_gem_object_save_bit_17_swizzle(obj); | |
1446 | ||
673a394b | 1447 | for (i = 0; i < page_count; i++) |
856fa198 | 1448 | if (obj_priv->pages[i] != NULL) { |
673a394b | 1449 | if (obj_priv->dirty) |
856fa198 EA |
1450 | set_page_dirty(obj_priv->pages[i]); |
1451 | mark_page_accessed(obj_priv->pages[i]); | |
1452 | page_cache_release(obj_priv->pages[i]); | |
673a394b EA |
1453 | } |
1454 | obj_priv->dirty = 0; | |
1455 | ||
8e7d2b2c | 1456 | drm_free_large(obj_priv->pages); |
856fa198 | 1457 | obj_priv->pages = NULL; |
673a394b EA |
1458 | } |
1459 | ||
1460 | static void | |
ce44b0ea | 1461 | i915_gem_object_move_to_active(struct drm_gem_object *obj, uint32_t seqno) |
673a394b EA |
1462 | { |
1463 | struct drm_device *dev = obj->dev; | |
1464 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1465 | struct drm_i915_gem_object *obj_priv = obj->driver_private; | |
1466 | ||
1467 | /* Add a reference if we're newly entering the active list. */ | |
1468 | if (!obj_priv->active) { | |
1469 | drm_gem_object_reference(obj); | |
1470 | obj_priv->active = 1; | |
1471 | } | |
1472 | /* Move from whatever list we were on to the tail of execution. */ | |
5e118f41 | 1473 | spin_lock(&dev_priv->mm.active_list_lock); |
673a394b EA |
1474 | list_move_tail(&obj_priv->list, |
1475 | &dev_priv->mm.active_list); | |
5e118f41 | 1476 | spin_unlock(&dev_priv->mm.active_list_lock); |
ce44b0ea | 1477 | obj_priv->last_rendering_seqno = seqno; |
673a394b EA |
1478 | } |
1479 | ||
ce44b0ea EA |
1480 | static void |
1481 | i915_gem_object_move_to_flushing(struct drm_gem_object *obj) | |
1482 | { | |
1483 | struct drm_device *dev = obj->dev; | |
1484 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1485 | struct drm_i915_gem_object *obj_priv = obj->driver_private; | |
1486 | ||
1487 | BUG_ON(!obj_priv->active); | |
1488 | list_move_tail(&obj_priv->list, &dev_priv->mm.flushing_list); | |
1489 | obj_priv->last_rendering_seqno = 0; | |
1490 | } | |
673a394b EA |
1491 | |
1492 | static void | |
1493 | i915_gem_object_move_to_inactive(struct drm_gem_object *obj) | |
1494 | { | |
1495 | struct drm_device *dev = obj->dev; | |
1496 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1497 | struct drm_i915_gem_object *obj_priv = obj->driver_private; | |
1498 | ||
1499 | i915_verify_inactive(dev, __FILE__, __LINE__); | |
1500 | if (obj_priv->pin_count != 0) | |
1501 | list_del_init(&obj_priv->list); | |
1502 | else | |
1503 | list_move_tail(&obj_priv->list, &dev_priv->mm.inactive_list); | |
1504 | ||
ce44b0ea | 1505 | obj_priv->last_rendering_seqno = 0; |
673a394b EA |
1506 | if (obj_priv->active) { |
1507 | obj_priv->active = 0; | |
1508 | drm_gem_object_unreference(obj); | |
1509 | } | |
1510 | i915_verify_inactive(dev, __FILE__, __LINE__); | |
1511 | } | |
1512 | ||
1513 | /** | |
1514 | * Creates a new sequence number, emitting a write of it to the status page | |
1515 | * plus an interrupt, which will trigger i915_user_interrupt_handler. | |
1516 | * | |
1517 | * Must be called with struct_lock held. | |
1518 | * | |
1519 | * Returned sequence numbers are nonzero on success. | |
1520 | */ | |
1521 | static uint32_t | |
b962442e EA |
1522 | i915_add_request(struct drm_device *dev, struct drm_file *file_priv, |
1523 | uint32_t flush_domains) | |
673a394b EA |
1524 | { |
1525 | drm_i915_private_t *dev_priv = dev->dev_private; | |
b962442e | 1526 | struct drm_i915_file_private *i915_file_priv = NULL; |
673a394b EA |
1527 | struct drm_i915_gem_request *request; |
1528 | uint32_t seqno; | |
1529 | int was_empty; | |
1530 | RING_LOCALS; | |
1531 | ||
b962442e EA |
1532 | if (file_priv != NULL) |
1533 | i915_file_priv = file_priv->driver_priv; | |
1534 | ||
9a298b2a | 1535 | request = kzalloc(sizeof(*request), GFP_KERNEL); |
673a394b EA |
1536 | if (request == NULL) |
1537 | return 0; | |
1538 | ||
1539 | /* Grab the seqno we're going to make this request be, and bump the | |
1540 | * next (skipping 0 so it can be the reserved no-seqno value). | |
1541 | */ | |
1542 | seqno = dev_priv->mm.next_gem_seqno; | |
1543 | dev_priv->mm.next_gem_seqno++; | |
1544 | if (dev_priv->mm.next_gem_seqno == 0) | |
1545 | dev_priv->mm.next_gem_seqno++; | |
1546 | ||
1547 | BEGIN_LP_RING(4); | |
1548 | OUT_RING(MI_STORE_DWORD_INDEX); | |
1549 | OUT_RING(I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT); | |
1550 | OUT_RING(seqno); | |
1551 | ||
1552 | OUT_RING(MI_USER_INTERRUPT); | |
1553 | ADVANCE_LP_RING(); | |
1554 | ||
1555 | DRM_DEBUG("%d\n", seqno); | |
1556 | ||
1557 | request->seqno = seqno; | |
1558 | request->emitted_jiffies = jiffies; | |
673a394b EA |
1559 | was_empty = list_empty(&dev_priv->mm.request_list); |
1560 | list_add_tail(&request->list, &dev_priv->mm.request_list); | |
b962442e EA |
1561 | if (i915_file_priv) { |
1562 | list_add_tail(&request->client_list, | |
1563 | &i915_file_priv->mm.request_list); | |
1564 | } else { | |
1565 | INIT_LIST_HEAD(&request->client_list); | |
1566 | } | |
673a394b | 1567 | |
ce44b0ea EA |
1568 | /* Associate any objects on the flushing list matching the write |
1569 | * domain we're flushing with our flush. | |
1570 | */ | |
1571 | if (flush_domains != 0) { | |
1572 | struct drm_i915_gem_object *obj_priv, *next; | |
1573 | ||
1574 | list_for_each_entry_safe(obj_priv, next, | |
1575 | &dev_priv->mm.flushing_list, list) { | |
1576 | struct drm_gem_object *obj = obj_priv->obj; | |
1577 | ||
1578 | if ((obj->write_domain & flush_domains) == | |
1579 | obj->write_domain) { | |
1580 | obj->write_domain = 0; | |
1581 | i915_gem_object_move_to_active(obj, seqno); | |
1582 | } | |
1583 | } | |
1584 | ||
1585 | } | |
1586 | ||
6dbe2772 | 1587 | if (was_empty && !dev_priv->mm.suspended) |
9c9fe1f8 | 1588 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ); |
673a394b EA |
1589 | return seqno; |
1590 | } | |
1591 | ||
1592 | /** | |
1593 | * Command execution barrier | |
1594 | * | |
1595 | * Ensures that all commands in the ring are finished | |
1596 | * before signalling the CPU | |
1597 | */ | |
3043c60c | 1598 | static uint32_t |
673a394b EA |
1599 | i915_retire_commands(struct drm_device *dev) |
1600 | { | |
1601 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1602 | uint32_t cmd = MI_FLUSH | MI_NO_WRITE_FLUSH; | |
1603 | uint32_t flush_domains = 0; | |
1604 | RING_LOCALS; | |
1605 | ||
1606 | /* The sampler always gets flushed on i965 (sigh) */ | |
1607 | if (IS_I965G(dev)) | |
1608 | flush_domains |= I915_GEM_DOMAIN_SAMPLER; | |
1609 | BEGIN_LP_RING(2); | |
1610 | OUT_RING(cmd); | |
1611 | OUT_RING(0); /* noop */ | |
1612 | ADVANCE_LP_RING(); | |
1613 | return flush_domains; | |
1614 | } | |
1615 | ||
1616 | /** | |
1617 | * Moves buffers associated only with the given active seqno from the active | |
1618 | * to inactive list, potentially freeing them. | |
1619 | */ | |
1620 | static void | |
1621 | i915_gem_retire_request(struct drm_device *dev, | |
1622 | struct drm_i915_gem_request *request) | |
1623 | { | |
1624 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1625 | ||
1626 | /* Move any buffers on the active list that are no longer referenced | |
1627 | * by the ringbuffer to the flushing/inactive lists as appropriate. | |
1628 | */ | |
5e118f41 | 1629 | spin_lock(&dev_priv->mm.active_list_lock); |
673a394b EA |
1630 | while (!list_empty(&dev_priv->mm.active_list)) { |
1631 | struct drm_gem_object *obj; | |
1632 | struct drm_i915_gem_object *obj_priv; | |
1633 | ||
1634 | obj_priv = list_first_entry(&dev_priv->mm.active_list, | |
1635 | struct drm_i915_gem_object, | |
1636 | list); | |
1637 | obj = obj_priv->obj; | |
1638 | ||
1639 | /* If the seqno being retired doesn't match the oldest in the | |
1640 | * list, then the oldest in the list must still be newer than | |
1641 | * this seqno. | |
1642 | */ | |
1643 | if (obj_priv->last_rendering_seqno != request->seqno) | |
5e118f41 | 1644 | goto out; |
de151cf6 | 1645 | |
673a394b EA |
1646 | #if WATCH_LRU |
1647 | DRM_INFO("%s: retire %d moves to inactive list %p\n", | |
1648 | __func__, request->seqno, obj); | |
1649 | #endif | |
1650 | ||
ce44b0ea EA |
1651 | if (obj->write_domain != 0) |
1652 | i915_gem_object_move_to_flushing(obj); | |
68c84342 SL |
1653 | else { |
1654 | /* Take a reference on the object so it won't be | |
1655 | * freed while the spinlock is held. The list | |
1656 | * protection for this spinlock is safe when breaking | |
1657 | * the lock like this since the next thing we do | |
1658 | * is just get the head of the list again. | |
1659 | */ | |
1660 | drm_gem_object_reference(obj); | |
673a394b | 1661 | i915_gem_object_move_to_inactive(obj); |
68c84342 SL |
1662 | spin_unlock(&dev_priv->mm.active_list_lock); |
1663 | drm_gem_object_unreference(obj); | |
1664 | spin_lock(&dev_priv->mm.active_list_lock); | |
1665 | } | |
673a394b | 1666 | } |
5e118f41 CW |
1667 | out: |
1668 | spin_unlock(&dev_priv->mm.active_list_lock); | |
673a394b EA |
1669 | } |
1670 | ||
1671 | /** | |
1672 | * Returns true if seq1 is later than seq2. | |
1673 | */ | |
1674 | static int | |
1675 | i915_seqno_passed(uint32_t seq1, uint32_t seq2) | |
1676 | { | |
1677 | return (int32_t)(seq1 - seq2) >= 0; | |
1678 | } | |
1679 | ||
1680 | uint32_t | |
1681 | i915_get_gem_seqno(struct drm_device *dev) | |
1682 | { | |
1683 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1684 | ||
1685 | return READ_HWSP(dev_priv, I915_GEM_HWS_INDEX); | |
1686 | } | |
1687 | ||
1688 | /** | |
1689 | * This function clears the request list as sequence numbers are passed. | |
1690 | */ | |
1691 | void | |
1692 | i915_gem_retire_requests(struct drm_device *dev) | |
1693 | { | |
1694 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1695 | uint32_t seqno; | |
1696 | ||
6c0594a3 KW |
1697 | if (!dev_priv->hw_status_page) |
1698 | return; | |
1699 | ||
673a394b EA |
1700 | seqno = i915_get_gem_seqno(dev); |
1701 | ||
1702 | while (!list_empty(&dev_priv->mm.request_list)) { | |
1703 | struct drm_i915_gem_request *request; | |
1704 | uint32_t retiring_seqno; | |
1705 | ||
1706 | request = list_first_entry(&dev_priv->mm.request_list, | |
1707 | struct drm_i915_gem_request, | |
1708 | list); | |
1709 | retiring_seqno = request->seqno; | |
1710 | ||
1711 | if (i915_seqno_passed(seqno, retiring_seqno) || | |
1712 | dev_priv->mm.wedged) { | |
1713 | i915_gem_retire_request(dev, request); | |
1714 | ||
1715 | list_del(&request->list); | |
b962442e | 1716 | list_del(&request->client_list); |
9a298b2a | 1717 | kfree(request); |
673a394b EA |
1718 | } else |
1719 | break; | |
1720 | } | |
1721 | } | |
1722 | ||
1723 | void | |
1724 | i915_gem_retire_work_handler(struct work_struct *work) | |
1725 | { | |
1726 | drm_i915_private_t *dev_priv; | |
1727 | struct drm_device *dev; | |
1728 | ||
1729 | dev_priv = container_of(work, drm_i915_private_t, | |
1730 | mm.retire_work.work); | |
1731 | dev = dev_priv->dev; | |
1732 | ||
1733 | mutex_lock(&dev->struct_mutex); | |
1734 | i915_gem_retire_requests(dev); | |
6dbe2772 KP |
1735 | if (!dev_priv->mm.suspended && |
1736 | !list_empty(&dev_priv->mm.request_list)) | |
9c9fe1f8 | 1737 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ); |
673a394b EA |
1738 | mutex_unlock(&dev->struct_mutex); |
1739 | } | |
1740 | ||
1741 | /** | |
1742 | * Waits for a sequence number to be signaled, and cleans up the | |
1743 | * request and object lists appropriately for that event. | |
1744 | */ | |
3043c60c | 1745 | static int |
673a394b EA |
1746 | i915_wait_request(struct drm_device *dev, uint32_t seqno) |
1747 | { | |
1748 | drm_i915_private_t *dev_priv = dev->dev_private; | |
802c7eb6 | 1749 | u32 ier; |
673a394b EA |
1750 | int ret = 0; |
1751 | ||
1752 | BUG_ON(seqno == 0); | |
1753 | ||
1754 | if (!i915_seqno_passed(i915_get_gem_seqno(dev), seqno)) { | |
036a4a7d ZW |
1755 | if (IS_IGDNG(dev)) |
1756 | ier = I915_READ(DEIER) | I915_READ(GTIER); | |
1757 | else | |
1758 | ier = I915_READ(IER); | |
802c7eb6 JB |
1759 | if (!ier) { |
1760 | DRM_ERROR("something (likely vbetool) disabled " | |
1761 | "interrupts, re-enabling\n"); | |
1762 | i915_driver_irq_preinstall(dev); | |
1763 | i915_driver_irq_postinstall(dev); | |
1764 | } | |
1765 | ||
673a394b EA |
1766 | dev_priv->mm.waiting_gem_seqno = seqno; |
1767 | i915_user_irq_get(dev); | |
1768 | ret = wait_event_interruptible(dev_priv->irq_queue, | |
1769 | i915_seqno_passed(i915_get_gem_seqno(dev), | |
1770 | seqno) || | |
1771 | dev_priv->mm.wedged); | |
1772 | i915_user_irq_put(dev); | |
1773 | dev_priv->mm.waiting_gem_seqno = 0; | |
1774 | } | |
1775 | if (dev_priv->mm.wedged) | |
1776 | ret = -EIO; | |
1777 | ||
1778 | if (ret && ret != -ERESTARTSYS) | |
1779 | DRM_ERROR("%s returns %d (awaiting %d at %d)\n", | |
1780 | __func__, ret, seqno, i915_get_gem_seqno(dev)); | |
1781 | ||
1782 | /* Directly dispatch request retiring. While we have the work queue | |
1783 | * to handle this, the waiter on a request often wants an associated | |
1784 | * buffer to have made it to the inactive list, and we would need | |
1785 | * a separate wait queue to handle that. | |
1786 | */ | |
1787 | if (ret == 0) | |
1788 | i915_gem_retire_requests(dev); | |
1789 | ||
1790 | return ret; | |
1791 | } | |
1792 | ||
1793 | static void | |
1794 | i915_gem_flush(struct drm_device *dev, | |
1795 | uint32_t invalidate_domains, | |
1796 | uint32_t flush_domains) | |
1797 | { | |
1798 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1799 | uint32_t cmd; | |
1800 | RING_LOCALS; | |
1801 | ||
1802 | #if WATCH_EXEC | |
1803 | DRM_INFO("%s: invalidate %08x flush %08x\n", __func__, | |
1804 | invalidate_domains, flush_domains); | |
1805 | #endif | |
1806 | ||
1807 | if (flush_domains & I915_GEM_DOMAIN_CPU) | |
1808 | drm_agp_chipset_flush(dev); | |
1809 | ||
21d509e3 | 1810 | if ((invalidate_domains | flush_domains) & I915_GEM_GPU_DOMAINS) { |
673a394b EA |
1811 | /* |
1812 | * read/write caches: | |
1813 | * | |
1814 | * I915_GEM_DOMAIN_RENDER is always invalidated, but is | |
1815 | * only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is | |
1816 | * also flushed at 2d versus 3d pipeline switches. | |
1817 | * | |
1818 | * read-only caches: | |
1819 | * | |
1820 | * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if | |
1821 | * MI_READ_FLUSH is set, and is always flushed on 965. | |
1822 | * | |
1823 | * I915_GEM_DOMAIN_COMMAND may not exist? | |
1824 | * | |
1825 | * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is | |
1826 | * invalidated when MI_EXE_FLUSH is set. | |
1827 | * | |
1828 | * I915_GEM_DOMAIN_VERTEX, which exists on 965, is | |
1829 | * invalidated with every MI_FLUSH. | |
1830 | * | |
1831 | * TLBs: | |
1832 | * | |
1833 | * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND | |
1834 | * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and | |
1835 | * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER | |
1836 | * are flushed at any MI_FLUSH. | |
1837 | */ | |
1838 | ||
1839 | cmd = MI_FLUSH | MI_NO_WRITE_FLUSH; | |
1840 | if ((invalidate_domains|flush_domains) & | |
1841 | I915_GEM_DOMAIN_RENDER) | |
1842 | cmd &= ~MI_NO_WRITE_FLUSH; | |
1843 | if (!IS_I965G(dev)) { | |
1844 | /* | |
1845 | * On the 965, the sampler cache always gets flushed | |
1846 | * and this bit is reserved. | |
1847 | */ | |
1848 | if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER) | |
1849 | cmd |= MI_READ_FLUSH; | |
1850 | } | |
1851 | if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION) | |
1852 | cmd |= MI_EXE_FLUSH; | |
1853 | ||
1854 | #if WATCH_EXEC | |
1855 | DRM_INFO("%s: queue flush %08x to ring\n", __func__, cmd); | |
1856 | #endif | |
1857 | BEGIN_LP_RING(2); | |
1858 | OUT_RING(cmd); | |
1859 | OUT_RING(0); /* noop */ | |
1860 | ADVANCE_LP_RING(); | |
1861 | } | |
1862 | } | |
1863 | ||
1864 | /** | |
1865 | * Ensures that all rendering to the object has completed and the object is | |
1866 | * safe to unbind from the GTT or access from the CPU. | |
1867 | */ | |
1868 | static int | |
1869 | i915_gem_object_wait_rendering(struct drm_gem_object *obj) | |
1870 | { | |
1871 | struct drm_device *dev = obj->dev; | |
1872 | struct drm_i915_gem_object *obj_priv = obj->driver_private; | |
1873 | int ret; | |
1874 | ||
e47c68e9 EA |
1875 | /* This function only exists to support waiting for existing rendering, |
1876 | * not for emitting required flushes. | |
673a394b | 1877 | */ |
e47c68e9 | 1878 | BUG_ON((obj->write_domain & I915_GEM_GPU_DOMAINS) != 0); |
673a394b EA |
1879 | |
1880 | /* If there is rendering queued on the buffer being evicted, wait for | |
1881 | * it. | |
1882 | */ | |
1883 | if (obj_priv->active) { | |
1884 | #if WATCH_BUF | |
1885 | DRM_INFO("%s: object %p wait for seqno %08x\n", | |
1886 | __func__, obj, obj_priv->last_rendering_seqno); | |
1887 | #endif | |
1888 | ret = i915_wait_request(dev, obj_priv->last_rendering_seqno); | |
1889 | if (ret != 0) | |
1890 | return ret; | |
1891 | } | |
1892 | ||
1893 | return 0; | |
1894 | } | |
1895 | ||
1896 | /** | |
1897 | * Unbinds an object from the GTT aperture. | |
1898 | */ | |
0f973f27 | 1899 | int |
673a394b EA |
1900 | i915_gem_object_unbind(struct drm_gem_object *obj) |
1901 | { | |
1902 | struct drm_device *dev = obj->dev; | |
1903 | struct drm_i915_gem_object *obj_priv = obj->driver_private; | |
1904 | int ret = 0; | |
1905 | ||
1906 | #if WATCH_BUF | |
1907 | DRM_INFO("%s:%d %p\n", __func__, __LINE__, obj); | |
1908 | DRM_INFO("gtt_space %p\n", obj_priv->gtt_space); | |
1909 | #endif | |
1910 | if (obj_priv->gtt_space == NULL) | |
1911 | return 0; | |
1912 | ||
1913 | if (obj_priv->pin_count != 0) { | |
1914 | DRM_ERROR("Attempting to unbind pinned buffer\n"); | |
1915 | return -EINVAL; | |
1916 | } | |
1917 | ||
5323fd04 EA |
1918 | /* blow away mappings if mapped through GTT */ |
1919 | i915_gem_release_mmap(obj); | |
1920 | ||
1921 | if (obj_priv->fence_reg != I915_FENCE_REG_NONE) | |
1922 | i915_gem_clear_fence_reg(obj); | |
1923 | ||
673a394b EA |
1924 | /* Move the object to the CPU domain to ensure that |
1925 | * any possible CPU writes while it's not in the GTT | |
1926 | * are flushed when we go to remap it. This will | |
1927 | * also ensure that all pending GPU writes are finished | |
1928 | * before we unbind. | |
1929 | */ | |
e47c68e9 | 1930 | ret = i915_gem_object_set_to_cpu_domain(obj, 1); |
673a394b | 1931 | if (ret) { |
e47c68e9 EA |
1932 | if (ret != -ERESTARTSYS) |
1933 | DRM_ERROR("set_domain failed: %d\n", ret); | |
673a394b EA |
1934 | return ret; |
1935 | } | |
1936 | ||
5323fd04 EA |
1937 | BUG_ON(obj_priv->active); |
1938 | ||
673a394b EA |
1939 | if (obj_priv->agp_mem != NULL) { |
1940 | drm_unbind_agp(obj_priv->agp_mem); | |
1941 | drm_free_agp(obj_priv->agp_mem, obj->size / PAGE_SIZE); | |
1942 | obj_priv->agp_mem = NULL; | |
1943 | } | |
1944 | ||
856fa198 | 1945 | i915_gem_object_put_pages(obj); |
673a394b EA |
1946 | |
1947 | if (obj_priv->gtt_space) { | |
1948 | atomic_dec(&dev->gtt_count); | |
1949 | atomic_sub(obj->size, &dev->gtt_memory); | |
1950 | ||
1951 | drm_mm_put_block(obj_priv->gtt_space); | |
1952 | obj_priv->gtt_space = NULL; | |
1953 | } | |
1954 | ||
1955 | /* Remove ourselves from the LRU list if present. */ | |
1956 | if (!list_empty(&obj_priv->list)) | |
1957 | list_del_init(&obj_priv->list); | |
1958 | ||
1959 | return 0; | |
1960 | } | |
1961 | ||
1962 | static int | |
1963 | i915_gem_evict_something(struct drm_device *dev) | |
1964 | { | |
1965 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1966 | struct drm_gem_object *obj; | |
1967 | struct drm_i915_gem_object *obj_priv; | |
1968 | int ret = 0; | |
1969 | ||
1970 | for (;;) { | |
1971 | /* If there's an inactive buffer available now, grab it | |
1972 | * and be done. | |
1973 | */ | |
1974 | if (!list_empty(&dev_priv->mm.inactive_list)) { | |
1975 | obj_priv = list_first_entry(&dev_priv->mm.inactive_list, | |
1976 | struct drm_i915_gem_object, | |
1977 | list); | |
1978 | obj = obj_priv->obj; | |
1979 | BUG_ON(obj_priv->pin_count != 0); | |
1980 | #if WATCH_LRU | |
1981 | DRM_INFO("%s: evicting %p\n", __func__, obj); | |
1982 | #endif | |
1983 | BUG_ON(obj_priv->active); | |
1984 | ||
1985 | /* Wait on the rendering and unbind the buffer. */ | |
1986 | ret = i915_gem_object_unbind(obj); | |
1987 | break; | |
1988 | } | |
1989 | ||
1990 | /* If we didn't get anything, but the ring is still processing | |
1991 | * things, wait for one of those things to finish and hopefully | |
1992 | * leave us a buffer to evict. | |
1993 | */ | |
1994 | if (!list_empty(&dev_priv->mm.request_list)) { | |
1995 | struct drm_i915_gem_request *request; | |
1996 | ||
1997 | request = list_first_entry(&dev_priv->mm.request_list, | |
1998 | struct drm_i915_gem_request, | |
1999 | list); | |
2000 | ||
2001 | ret = i915_wait_request(dev, request->seqno); | |
2002 | if (ret) | |
2003 | break; | |
2004 | ||
2005 | /* if waiting caused an object to become inactive, | |
2006 | * then loop around and wait for it. Otherwise, we | |
2007 | * assume that waiting freed and unbound something, | |
2008 | * so there should now be some space in the GTT | |
2009 | */ | |
2010 | if (!list_empty(&dev_priv->mm.inactive_list)) | |
2011 | continue; | |
2012 | break; | |
2013 | } | |
2014 | ||
2015 | /* If we didn't have anything on the request list but there | |
2016 | * are buffers awaiting a flush, emit one and try again. | |
2017 | * When we wait on it, those buffers waiting for that flush | |
2018 | * will get moved to inactive. | |
2019 | */ | |
2020 | if (!list_empty(&dev_priv->mm.flushing_list)) { | |
2021 | obj_priv = list_first_entry(&dev_priv->mm.flushing_list, | |
2022 | struct drm_i915_gem_object, | |
2023 | list); | |
2024 | obj = obj_priv->obj; | |
2025 | ||
2026 | i915_gem_flush(dev, | |
2027 | obj->write_domain, | |
2028 | obj->write_domain); | |
b962442e | 2029 | i915_add_request(dev, NULL, obj->write_domain); |
673a394b EA |
2030 | |
2031 | obj = NULL; | |
2032 | continue; | |
2033 | } | |
2034 | ||
2035 | DRM_ERROR("inactive empty %d request empty %d " | |
2036 | "flushing empty %d\n", | |
2037 | list_empty(&dev_priv->mm.inactive_list), | |
2038 | list_empty(&dev_priv->mm.request_list), | |
2039 | list_empty(&dev_priv->mm.flushing_list)); | |
2040 | /* If we didn't do any of the above, there's nothing to be done | |
2041 | * and we just can't fit it in. | |
2042 | */ | |
2939e1f5 | 2043 | return -ENOSPC; |
673a394b EA |
2044 | } |
2045 | return ret; | |
2046 | } | |
2047 | ||
ac94a962 KP |
2048 | static int |
2049 | i915_gem_evict_everything(struct drm_device *dev) | |
2050 | { | |
2051 | int ret; | |
2052 | ||
2053 | for (;;) { | |
2054 | ret = i915_gem_evict_something(dev); | |
2055 | if (ret != 0) | |
2056 | break; | |
2057 | } | |
2939e1f5 | 2058 | if (ret == -ENOSPC) |
15c35334 | 2059 | return 0; |
ac94a962 KP |
2060 | return ret; |
2061 | } | |
2062 | ||
6911a9b8 | 2063 | int |
856fa198 | 2064 | i915_gem_object_get_pages(struct drm_gem_object *obj) |
673a394b EA |
2065 | { |
2066 | struct drm_i915_gem_object *obj_priv = obj->driver_private; | |
2067 | int page_count, i; | |
2068 | struct address_space *mapping; | |
2069 | struct inode *inode; | |
2070 | struct page *page; | |
2071 | int ret; | |
2072 | ||
856fa198 | 2073 | if (obj_priv->pages_refcount++ != 0) |
673a394b EA |
2074 | return 0; |
2075 | ||
2076 | /* Get the list of pages out of our struct file. They'll be pinned | |
2077 | * at this point until we release them. | |
2078 | */ | |
2079 | page_count = obj->size / PAGE_SIZE; | |
856fa198 | 2080 | BUG_ON(obj_priv->pages != NULL); |
8e7d2b2c | 2081 | obj_priv->pages = drm_calloc_large(page_count, sizeof(struct page *)); |
856fa198 | 2082 | if (obj_priv->pages == NULL) { |
673a394b | 2083 | DRM_ERROR("Faled to allocate page list\n"); |
856fa198 | 2084 | obj_priv->pages_refcount--; |
673a394b EA |
2085 | return -ENOMEM; |
2086 | } | |
2087 | ||
2088 | inode = obj->filp->f_path.dentry->d_inode; | |
2089 | mapping = inode->i_mapping; | |
2090 | for (i = 0; i < page_count; i++) { | |
2091 | page = read_mapping_page(mapping, i, NULL); | |
2092 | if (IS_ERR(page)) { | |
2093 | ret = PTR_ERR(page); | |
2094 | DRM_ERROR("read_mapping_page failed: %d\n", ret); | |
856fa198 | 2095 | i915_gem_object_put_pages(obj); |
673a394b EA |
2096 | return ret; |
2097 | } | |
856fa198 | 2098 | obj_priv->pages[i] = page; |
673a394b | 2099 | } |
280b713b EA |
2100 | |
2101 | if (obj_priv->tiling_mode != I915_TILING_NONE) | |
2102 | i915_gem_object_do_bit_17_swizzle(obj); | |
2103 | ||
673a394b EA |
2104 | return 0; |
2105 | } | |
2106 | ||
de151cf6 JB |
2107 | static void i965_write_fence_reg(struct drm_i915_fence_reg *reg) |
2108 | { | |
2109 | struct drm_gem_object *obj = reg->obj; | |
2110 | struct drm_device *dev = obj->dev; | |
2111 | drm_i915_private_t *dev_priv = dev->dev_private; | |
2112 | struct drm_i915_gem_object *obj_priv = obj->driver_private; | |
2113 | int regnum = obj_priv->fence_reg; | |
2114 | uint64_t val; | |
2115 | ||
2116 | val = (uint64_t)((obj_priv->gtt_offset + obj->size - 4096) & | |
2117 | 0xfffff000) << 32; | |
2118 | val |= obj_priv->gtt_offset & 0xfffff000; | |
2119 | val |= ((obj_priv->stride / 128) - 1) << I965_FENCE_PITCH_SHIFT; | |
2120 | if (obj_priv->tiling_mode == I915_TILING_Y) | |
2121 | val |= 1 << I965_FENCE_TILING_Y_SHIFT; | |
2122 | val |= I965_FENCE_REG_VALID; | |
2123 | ||
2124 | I915_WRITE64(FENCE_REG_965_0 + (regnum * 8), val); | |
2125 | } | |
2126 | ||
2127 | static void i915_write_fence_reg(struct drm_i915_fence_reg *reg) | |
2128 | { | |
2129 | struct drm_gem_object *obj = reg->obj; | |
2130 | struct drm_device *dev = obj->dev; | |
2131 | drm_i915_private_t *dev_priv = dev->dev_private; | |
2132 | struct drm_i915_gem_object *obj_priv = obj->driver_private; | |
2133 | int regnum = obj_priv->fence_reg; | |
0f973f27 | 2134 | int tile_width; |
dc529a4f | 2135 | uint32_t fence_reg, val; |
de151cf6 JB |
2136 | uint32_t pitch_val; |
2137 | ||
2138 | if ((obj_priv->gtt_offset & ~I915_FENCE_START_MASK) || | |
2139 | (obj_priv->gtt_offset & (obj->size - 1))) { | |
f06da264 | 2140 | WARN(1, "%s: object 0x%08x not 1M or size (0x%zx) aligned\n", |
0f973f27 | 2141 | __func__, obj_priv->gtt_offset, obj->size); |
de151cf6 JB |
2142 | return; |
2143 | } | |
2144 | ||
0f973f27 JB |
2145 | if (obj_priv->tiling_mode == I915_TILING_Y && |
2146 | HAS_128_BYTE_Y_TILING(dev)) | |
2147 | tile_width = 128; | |
de151cf6 | 2148 | else |
0f973f27 JB |
2149 | tile_width = 512; |
2150 | ||
2151 | /* Note: pitch better be a power of two tile widths */ | |
2152 | pitch_val = obj_priv->stride / tile_width; | |
2153 | pitch_val = ffs(pitch_val) - 1; | |
de151cf6 JB |
2154 | |
2155 | val = obj_priv->gtt_offset; | |
2156 | if (obj_priv->tiling_mode == I915_TILING_Y) | |
2157 | val |= 1 << I830_FENCE_TILING_Y_SHIFT; | |
2158 | val |= I915_FENCE_SIZE_BITS(obj->size); | |
2159 | val |= pitch_val << I830_FENCE_PITCH_SHIFT; | |
2160 | val |= I830_FENCE_REG_VALID; | |
2161 | ||
dc529a4f EA |
2162 | if (regnum < 8) |
2163 | fence_reg = FENCE_REG_830_0 + (regnum * 4); | |
2164 | else | |
2165 | fence_reg = FENCE_REG_945_8 + ((regnum - 8) * 4); | |
2166 | I915_WRITE(fence_reg, val); | |
de151cf6 JB |
2167 | } |
2168 | ||
2169 | static void i830_write_fence_reg(struct drm_i915_fence_reg *reg) | |
2170 | { | |
2171 | struct drm_gem_object *obj = reg->obj; | |
2172 | struct drm_device *dev = obj->dev; | |
2173 | drm_i915_private_t *dev_priv = dev->dev_private; | |
2174 | struct drm_i915_gem_object *obj_priv = obj->driver_private; | |
2175 | int regnum = obj_priv->fence_reg; | |
2176 | uint32_t val; | |
2177 | uint32_t pitch_val; | |
8d7773a3 | 2178 | uint32_t fence_size_bits; |
de151cf6 | 2179 | |
8d7773a3 | 2180 | if ((obj_priv->gtt_offset & ~I830_FENCE_START_MASK) || |
de151cf6 | 2181 | (obj_priv->gtt_offset & (obj->size - 1))) { |
8d7773a3 | 2182 | WARN(1, "%s: object 0x%08x not 512K or size aligned\n", |
0f973f27 | 2183 | __func__, obj_priv->gtt_offset); |
de151cf6 JB |
2184 | return; |
2185 | } | |
2186 | ||
e76a16de EA |
2187 | pitch_val = obj_priv->stride / 128; |
2188 | pitch_val = ffs(pitch_val) - 1; | |
2189 | WARN_ON(pitch_val > I830_FENCE_MAX_PITCH_VAL); | |
2190 | ||
de151cf6 JB |
2191 | val = obj_priv->gtt_offset; |
2192 | if (obj_priv->tiling_mode == I915_TILING_Y) | |
2193 | val |= 1 << I830_FENCE_TILING_Y_SHIFT; | |
8d7773a3 DV |
2194 | fence_size_bits = I830_FENCE_SIZE_BITS(obj->size); |
2195 | WARN_ON(fence_size_bits & ~0x00000f00); | |
2196 | val |= fence_size_bits; | |
de151cf6 JB |
2197 | val |= pitch_val << I830_FENCE_PITCH_SHIFT; |
2198 | val |= I830_FENCE_REG_VALID; | |
2199 | ||
2200 | I915_WRITE(FENCE_REG_830_0 + (regnum * 4), val); | |
de151cf6 JB |
2201 | } |
2202 | ||
2203 | /** | |
2204 | * i915_gem_object_get_fence_reg - set up a fence reg for an object | |
2205 | * @obj: object to map through a fence reg | |
2206 | * | |
2207 | * When mapping objects through the GTT, userspace wants to be able to write | |
2208 | * to them without having to worry about swizzling if the object is tiled. | |
2209 | * | |
2210 | * This function walks the fence regs looking for a free one for @obj, | |
2211 | * stealing one if it can't find any. | |
2212 | * | |
2213 | * It then sets up the reg based on the object's properties: address, pitch | |
2214 | * and tiling format. | |
2215 | */ | |
8c4b8c3f CW |
2216 | int |
2217 | i915_gem_object_get_fence_reg(struct drm_gem_object *obj) | |
de151cf6 JB |
2218 | { |
2219 | struct drm_device *dev = obj->dev; | |
79e53945 | 2220 | struct drm_i915_private *dev_priv = dev->dev_private; |
de151cf6 JB |
2221 | struct drm_i915_gem_object *obj_priv = obj->driver_private; |
2222 | struct drm_i915_fence_reg *reg = NULL; | |
fc7170ba CW |
2223 | struct drm_i915_gem_object *old_obj_priv = NULL; |
2224 | int i, ret, avail; | |
de151cf6 | 2225 | |
a09ba7fa EA |
2226 | /* Just update our place in the LRU if our fence is getting used. */ |
2227 | if (obj_priv->fence_reg != I915_FENCE_REG_NONE) { | |
2228 | list_move_tail(&obj_priv->fence_list, &dev_priv->mm.fence_list); | |
2229 | return 0; | |
2230 | } | |
2231 | ||
de151cf6 JB |
2232 | switch (obj_priv->tiling_mode) { |
2233 | case I915_TILING_NONE: | |
2234 | WARN(1, "allocating a fence for non-tiled object?\n"); | |
2235 | break; | |
2236 | case I915_TILING_X: | |
0f973f27 JB |
2237 | if (!obj_priv->stride) |
2238 | return -EINVAL; | |
2239 | WARN((obj_priv->stride & (512 - 1)), | |
2240 | "object 0x%08x is X tiled but has non-512B pitch\n", | |
2241 | obj_priv->gtt_offset); | |
de151cf6 JB |
2242 | break; |
2243 | case I915_TILING_Y: | |
0f973f27 JB |
2244 | if (!obj_priv->stride) |
2245 | return -EINVAL; | |
2246 | WARN((obj_priv->stride & (128 - 1)), | |
2247 | "object 0x%08x is Y tiled but has non-128B pitch\n", | |
2248 | obj_priv->gtt_offset); | |
de151cf6 JB |
2249 | break; |
2250 | } | |
2251 | ||
2252 | /* First try to find a free reg */ | |
fc7170ba | 2253 | avail = 0; |
de151cf6 JB |
2254 | for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) { |
2255 | reg = &dev_priv->fence_regs[i]; | |
2256 | if (!reg->obj) | |
2257 | break; | |
fc7170ba CW |
2258 | |
2259 | old_obj_priv = reg->obj->driver_private; | |
2260 | if (!old_obj_priv->pin_count) | |
2261 | avail++; | |
de151cf6 JB |
2262 | } |
2263 | ||
2264 | /* None available, try to steal one or wait for a user to finish */ | |
2265 | if (i == dev_priv->num_fence_regs) { | |
a09ba7fa | 2266 | struct drm_gem_object *old_obj = NULL; |
de151cf6 | 2267 | |
fc7170ba | 2268 | if (avail == 0) |
2939e1f5 | 2269 | return -ENOSPC; |
fc7170ba | 2270 | |
a09ba7fa EA |
2271 | list_for_each_entry(old_obj_priv, &dev_priv->mm.fence_list, |
2272 | fence_list) { | |
2273 | old_obj = old_obj_priv->obj; | |
d7619c4b CW |
2274 | |
2275 | if (old_obj_priv->pin_count) | |
2276 | continue; | |
2277 | ||
a09ba7fa EA |
2278 | /* Take a reference, as otherwise the wait_rendering |
2279 | * below may cause the object to get freed out from | |
2280 | * under us. | |
2281 | */ | |
2282 | drm_gem_object_reference(old_obj); | |
2283 | ||
d7619c4b CW |
2284 | /* i915 uses fences for GPU access to tiled buffers */ |
2285 | if (IS_I965G(dev) || !old_obj_priv->active) | |
de151cf6 | 2286 | break; |
d7619c4b | 2287 | |
a09ba7fa EA |
2288 | /* This brings the object to the head of the LRU if it |
2289 | * had been written to. The only way this should | |
2290 | * result in us waiting longer than the expected | |
2291 | * optimal amount of time is if there was a | |
2292 | * fence-using buffer later that was read-only. | |
2293 | */ | |
2294 | i915_gem_object_flush_gpu_write_domain(old_obj); | |
2295 | ret = i915_gem_object_wait_rendering(old_obj); | |
58c2fb64 CW |
2296 | if (ret != 0) { |
2297 | drm_gem_object_unreference(old_obj); | |
d7619c4b | 2298 | return ret; |
de151cf6 | 2299 | } |
d7619c4b | 2300 | |
a09ba7fa | 2301 | break; |
de151cf6 JB |
2302 | } |
2303 | ||
2304 | /* | |
2305 | * Zap this virtual mapping so we can set up a fence again | |
2306 | * for this object next time we need it. | |
2307 | */ | |
58c2fb64 CW |
2308 | i915_gem_release_mmap(old_obj); |
2309 | ||
a09ba7fa | 2310 | i = old_obj_priv->fence_reg; |
58c2fb64 CW |
2311 | reg = &dev_priv->fence_regs[i]; |
2312 | ||
de151cf6 | 2313 | old_obj_priv->fence_reg = I915_FENCE_REG_NONE; |
a09ba7fa | 2314 | list_del_init(&old_obj_priv->fence_list); |
58c2fb64 | 2315 | |
a09ba7fa | 2316 | drm_gem_object_unreference(old_obj); |
de151cf6 JB |
2317 | } |
2318 | ||
2319 | obj_priv->fence_reg = i; | |
a09ba7fa EA |
2320 | list_add_tail(&obj_priv->fence_list, &dev_priv->mm.fence_list); |
2321 | ||
de151cf6 JB |
2322 | reg->obj = obj; |
2323 | ||
2324 | if (IS_I965G(dev)) | |
2325 | i965_write_fence_reg(reg); | |
2326 | else if (IS_I9XX(dev)) | |
2327 | i915_write_fence_reg(reg); | |
2328 | else | |
2329 | i830_write_fence_reg(reg); | |
d9ddcb96 EA |
2330 | |
2331 | return 0; | |
de151cf6 JB |
2332 | } |
2333 | ||
2334 | /** | |
2335 | * i915_gem_clear_fence_reg - clear out fence register info | |
2336 | * @obj: object to clear | |
2337 | * | |
2338 | * Zeroes out the fence register itself and clears out the associated | |
2339 | * data structures in dev_priv and obj_priv. | |
2340 | */ | |
2341 | static void | |
2342 | i915_gem_clear_fence_reg(struct drm_gem_object *obj) | |
2343 | { | |
2344 | struct drm_device *dev = obj->dev; | |
79e53945 | 2345 | drm_i915_private_t *dev_priv = dev->dev_private; |
de151cf6 JB |
2346 | struct drm_i915_gem_object *obj_priv = obj->driver_private; |
2347 | ||
2348 | if (IS_I965G(dev)) | |
2349 | I915_WRITE64(FENCE_REG_965_0 + (obj_priv->fence_reg * 8), 0); | |
dc529a4f EA |
2350 | else { |
2351 | uint32_t fence_reg; | |
2352 | ||
2353 | if (obj_priv->fence_reg < 8) | |
2354 | fence_reg = FENCE_REG_830_0 + obj_priv->fence_reg * 4; | |
2355 | else | |
2356 | fence_reg = FENCE_REG_945_8 + (obj_priv->fence_reg - | |
2357 | 8) * 4; | |
2358 | ||
2359 | I915_WRITE(fence_reg, 0); | |
2360 | } | |
de151cf6 JB |
2361 | |
2362 | dev_priv->fence_regs[obj_priv->fence_reg].obj = NULL; | |
2363 | obj_priv->fence_reg = I915_FENCE_REG_NONE; | |
a09ba7fa | 2364 | list_del_init(&obj_priv->fence_list); |
de151cf6 JB |
2365 | } |
2366 | ||
52dc7d32 CW |
2367 | /** |
2368 | * i915_gem_object_put_fence_reg - waits on outstanding fenced access | |
2369 | * to the buffer to finish, and then resets the fence register. | |
2370 | * @obj: tiled object holding a fence register. | |
2371 | * | |
2372 | * Zeroes out the fence register itself and clears out the associated | |
2373 | * data structures in dev_priv and obj_priv. | |
2374 | */ | |
2375 | int | |
2376 | i915_gem_object_put_fence_reg(struct drm_gem_object *obj) | |
2377 | { | |
2378 | struct drm_device *dev = obj->dev; | |
2379 | struct drm_i915_gem_object *obj_priv = obj->driver_private; | |
2380 | ||
2381 | if (obj_priv->fence_reg == I915_FENCE_REG_NONE) | |
2382 | return 0; | |
2383 | ||
2384 | /* On the i915, GPU access to tiled buffers is via a fence, | |
2385 | * therefore we must wait for any outstanding access to complete | |
2386 | * before clearing the fence. | |
2387 | */ | |
2388 | if (!IS_I965G(dev)) { | |
2389 | int ret; | |
2390 | ||
2391 | i915_gem_object_flush_gpu_write_domain(obj); | |
2392 | i915_gem_object_flush_gtt_write_domain(obj); | |
2393 | ret = i915_gem_object_wait_rendering(obj); | |
2394 | if (ret != 0) | |
2395 | return ret; | |
2396 | } | |
2397 | ||
2398 | i915_gem_clear_fence_reg (obj); | |
2399 | ||
2400 | return 0; | |
2401 | } | |
2402 | ||
673a394b EA |
2403 | /** |
2404 | * Finds free space in the GTT aperture and binds the object there. | |
2405 | */ | |
2406 | static int | |
2407 | i915_gem_object_bind_to_gtt(struct drm_gem_object *obj, unsigned alignment) | |
2408 | { | |
2409 | struct drm_device *dev = obj->dev; | |
2410 | drm_i915_private_t *dev_priv = dev->dev_private; | |
2411 | struct drm_i915_gem_object *obj_priv = obj->driver_private; | |
2412 | struct drm_mm_node *free_space; | |
2413 | int page_count, ret; | |
2414 | ||
9bb2d6f9 EA |
2415 | if (dev_priv->mm.suspended) |
2416 | return -EBUSY; | |
673a394b | 2417 | if (alignment == 0) |
0f973f27 | 2418 | alignment = i915_gem_get_gtt_alignment(obj); |
8d7773a3 | 2419 | if (alignment & (i915_gem_get_gtt_alignment(obj) - 1)) { |
673a394b EA |
2420 | DRM_ERROR("Invalid object alignment requested %u\n", alignment); |
2421 | return -EINVAL; | |
2422 | } | |
2423 | ||
2424 | search_free: | |
2425 | free_space = drm_mm_search_free(&dev_priv->mm.gtt_space, | |
2426 | obj->size, alignment, 0); | |
2427 | if (free_space != NULL) { | |
2428 | obj_priv->gtt_space = drm_mm_get_block(free_space, obj->size, | |
2429 | alignment); | |
2430 | if (obj_priv->gtt_space != NULL) { | |
2431 | obj_priv->gtt_space->private = obj; | |
2432 | obj_priv->gtt_offset = obj_priv->gtt_space->start; | |
2433 | } | |
2434 | } | |
2435 | if (obj_priv->gtt_space == NULL) { | |
5e118f41 CW |
2436 | bool lists_empty; |
2437 | ||
673a394b EA |
2438 | /* If the gtt is empty and we're still having trouble |
2439 | * fitting our object in, we're out of memory. | |
2440 | */ | |
2441 | #if WATCH_LRU | |
2442 | DRM_INFO("%s: GTT full, evicting something\n", __func__); | |
2443 | #endif | |
5e118f41 CW |
2444 | spin_lock(&dev_priv->mm.active_list_lock); |
2445 | lists_empty = (list_empty(&dev_priv->mm.inactive_list) && | |
2446 | list_empty(&dev_priv->mm.flushing_list) && | |
2447 | list_empty(&dev_priv->mm.active_list)); | |
2448 | spin_unlock(&dev_priv->mm.active_list_lock); | |
2449 | if (lists_empty) { | |
673a394b | 2450 | DRM_ERROR("GTT full, but LRU list empty\n"); |
2939e1f5 | 2451 | return -ENOSPC; |
673a394b EA |
2452 | } |
2453 | ||
2454 | ret = i915_gem_evict_something(dev); | |
2455 | if (ret != 0) { | |
ac94a962 KP |
2456 | if (ret != -ERESTARTSYS) |
2457 | DRM_ERROR("Failed to evict a buffer %d\n", ret); | |
673a394b EA |
2458 | return ret; |
2459 | } | |
2460 | goto search_free; | |
2461 | } | |
2462 | ||
2463 | #if WATCH_BUF | |
cfd43c02 | 2464 | DRM_INFO("Binding object of size %zd at 0x%08x\n", |
673a394b EA |
2465 | obj->size, obj_priv->gtt_offset); |
2466 | #endif | |
856fa198 | 2467 | ret = i915_gem_object_get_pages(obj); |
673a394b EA |
2468 | if (ret) { |
2469 | drm_mm_put_block(obj_priv->gtt_space); | |
2470 | obj_priv->gtt_space = NULL; | |
2471 | return ret; | |
2472 | } | |
2473 | ||
2474 | page_count = obj->size / PAGE_SIZE; | |
2475 | /* Create an AGP memory structure pointing at our pages, and bind it | |
2476 | * into the GTT. | |
2477 | */ | |
2478 | obj_priv->agp_mem = drm_agp_bind_pages(dev, | |
856fa198 | 2479 | obj_priv->pages, |
673a394b | 2480 | page_count, |
ba1eb1d8 KP |
2481 | obj_priv->gtt_offset, |
2482 | obj_priv->agp_type); | |
673a394b | 2483 | if (obj_priv->agp_mem == NULL) { |
856fa198 | 2484 | i915_gem_object_put_pages(obj); |
673a394b EA |
2485 | drm_mm_put_block(obj_priv->gtt_space); |
2486 | obj_priv->gtt_space = NULL; | |
2487 | return -ENOMEM; | |
2488 | } | |
2489 | atomic_inc(&dev->gtt_count); | |
2490 | atomic_add(obj->size, &dev->gtt_memory); | |
2491 | ||
2492 | /* Assert that the object is not currently in any GPU domain. As it | |
2493 | * wasn't in the GTT, there shouldn't be any way it could have been in | |
2494 | * a GPU cache | |
2495 | */ | |
21d509e3 CW |
2496 | BUG_ON(obj->read_domains & I915_GEM_GPU_DOMAINS); |
2497 | BUG_ON(obj->write_domain & I915_GEM_GPU_DOMAINS); | |
673a394b EA |
2498 | |
2499 | return 0; | |
2500 | } | |
2501 | ||
2502 | void | |
2503 | i915_gem_clflush_object(struct drm_gem_object *obj) | |
2504 | { | |
2505 | struct drm_i915_gem_object *obj_priv = obj->driver_private; | |
2506 | ||
2507 | /* If we don't have a page list set up, then we're not pinned | |
2508 | * to GPU, and we can ignore the cache flush because it'll happen | |
2509 | * again at bind time. | |
2510 | */ | |
856fa198 | 2511 | if (obj_priv->pages == NULL) |
673a394b EA |
2512 | return; |
2513 | ||
856fa198 | 2514 | drm_clflush_pages(obj_priv->pages, obj->size / PAGE_SIZE); |
673a394b EA |
2515 | } |
2516 | ||
e47c68e9 EA |
2517 | /** Flushes any GPU write domain for the object if it's dirty. */ |
2518 | static void | |
2519 | i915_gem_object_flush_gpu_write_domain(struct drm_gem_object *obj) | |
2520 | { | |
2521 | struct drm_device *dev = obj->dev; | |
2522 | uint32_t seqno; | |
2523 | ||
2524 | if ((obj->write_domain & I915_GEM_GPU_DOMAINS) == 0) | |
2525 | return; | |
2526 | ||
2527 | /* Queue the GPU write cache flushing we need. */ | |
2528 | i915_gem_flush(dev, 0, obj->write_domain); | |
b962442e | 2529 | seqno = i915_add_request(dev, NULL, obj->write_domain); |
e47c68e9 EA |
2530 | obj->write_domain = 0; |
2531 | i915_gem_object_move_to_active(obj, seqno); | |
2532 | } | |
2533 | ||
2534 | /** Flushes the GTT write domain for the object if it's dirty. */ | |
2535 | static void | |
2536 | i915_gem_object_flush_gtt_write_domain(struct drm_gem_object *obj) | |
2537 | { | |
2538 | if (obj->write_domain != I915_GEM_DOMAIN_GTT) | |
2539 | return; | |
2540 | ||
2541 | /* No actual flushing is required for the GTT write domain. Writes | |
2542 | * to it immediately go to main memory as far as we know, so there's | |
2543 | * no chipset flush. It also doesn't land in render cache. | |
2544 | */ | |
2545 | obj->write_domain = 0; | |
2546 | } | |
2547 | ||
2548 | /** Flushes the CPU write domain for the object if it's dirty. */ | |
2549 | static void | |
2550 | i915_gem_object_flush_cpu_write_domain(struct drm_gem_object *obj) | |
2551 | { | |
2552 | struct drm_device *dev = obj->dev; | |
2553 | ||
2554 | if (obj->write_domain != I915_GEM_DOMAIN_CPU) | |
2555 | return; | |
2556 | ||
2557 | i915_gem_clflush_object(obj); | |
2558 | drm_agp_chipset_flush(dev); | |
2559 | obj->write_domain = 0; | |
2560 | } | |
2561 | ||
2ef7eeaa EA |
2562 | /** |
2563 | * Moves a single object to the GTT read, and possibly write domain. | |
2564 | * | |
2565 | * This function returns when the move is complete, including waiting on | |
2566 | * flushes to occur. | |
2567 | */ | |
79e53945 | 2568 | int |
2ef7eeaa EA |
2569 | i915_gem_object_set_to_gtt_domain(struct drm_gem_object *obj, int write) |
2570 | { | |
2ef7eeaa | 2571 | struct drm_i915_gem_object *obj_priv = obj->driver_private; |
e47c68e9 | 2572 | int ret; |
2ef7eeaa | 2573 | |
02354392 EA |
2574 | /* Not valid to be called on unbound objects. */ |
2575 | if (obj_priv->gtt_space == NULL) | |
2576 | return -EINVAL; | |
2577 | ||
e47c68e9 EA |
2578 | i915_gem_object_flush_gpu_write_domain(obj); |
2579 | /* Wait on any GPU rendering and flushing to occur. */ | |
2580 | ret = i915_gem_object_wait_rendering(obj); | |
2581 | if (ret != 0) | |
2582 | return ret; | |
2583 | ||
2584 | /* If we're writing through the GTT domain, then CPU and GPU caches | |
2585 | * will need to be invalidated at next use. | |
2ef7eeaa | 2586 | */ |
e47c68e9 EA |
2587 | if (write) |
2588 | obj->read_domains &= I915_GEM_DOMAIN_GTT; | |
2ef7eeaa | 2589 | |
e47c68e9 | 2590 | i915_gem_object_flush_cpu_write_domain(obj); |
2ef7eeaa | 2591 | |
e47c68e9 EA |
2592 | /* It should now be out of any other write domains, and we can update |
2593 | * the domain values for our changes. | |
2594 | */ | |
2595 | BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_GTT) != 0); | |
2596 | obj->read_domains |= I915_GEM_DOMAIN_GTT; | |
2597 | if (write) { | |
2598 | obj->write_domain = I915_GEM_DOMAIN_GTT; | |
2599 | obj_priv->dirty = 1; | |
2ef7eeaa EA |
2600 | } |
2601 | ||
e47c68e9 EA |
2602 | return 0; |
2603 | } | |
2604 | ||
2605 | /** | |
2606 | * Moves a single object to the CPU read, and possibly write domain. | |
2607 | * | |
2608 | * This function returns when the move is complete, including waiting on | |
2609 | * flushes to occur. | |
2610 | */ | |
2611 | static int | |
2612 | i915_gem_object_set_to_cpu_domain(struct drm_gem_object *obj, int write) | |
2613 | { | |
e47c68e9 EA |
2614 | int ret; |
2615 | ||
2616 | i915_gem_object_flush_gpu_write_domain(obj); | |
2ef7eeaa | 2617 | /* Wait on any GPU rendering and flushing to occur. */ |
e47c68e9 EA |
2618 | ret = i915_gem_object_wait_rendering(obj); |
2619 | if (ret != 0) | |
2620 | return ret; | |
2ef7eeaa | 2621 | |
e47c68e9 | 2622 | i915_gem_object_flush_gtt_write_domain(obj); |
2ef7eeaa | 2623 | |
e47c68e9 EA |
2624 | /* If we have a partially-valid cache of the object in the CPU, |
2625 | * finish invalidating it and free the per-page flags. | |
2ef7eeaa | 2626 | */ |
e47c68e9 | 2627 | i915_gem_object_set_to_full_cpu_read_domain(obj); |
2ef7eeaa | 2628 | |
e47c68e9 EA |
2629 | /* Flush the CPU cache if it's still invalid. */ |
2630 | if ((obj->read_domains & I915_GEM_DOMAIN_CPU) == 0) { | |
2ef7eeaa | 2631 | i915_gem_clflush_object(obj); |
2ef7eeaa | 2632 | |
e47c68e9 | 2633 | obj->read_domains |= I915_GEM_DOMAIN_CPU; |
2ef7eeaa EA |
2634 | } |
2635 | ||
2636 | /* It should now be out of any other write domains, and we can update | |
2637 | * the domain values for our changes. | |
2638 | */ | |
e47c68e9 EA |
2639 | BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_CPU) != 0); |
2640 | ||
2641 | /* If we're writing through the CPU, then the GPU read domains will | |
2642 | * need to be invalidated at next use. | |
2643 | */ | |
2644 | if (write) { | |
2645 | obj->read_domains &= I915_GEM_DOMAIN_CPU; | |
2646 | obj->write_domain = I915_GEM_DOMAIN_CPU; | |
2647 | } | |
2ef7eeaa EA |
2648 | |
2649 | return 0; | |
2650 | } | |
2651 | ||
673a394b EA |
2652 | /* |
2653 | * Set the next domain for the specified object. This | |
2654 | * may not actually perform the necessary flushing/invaliding though, | |
2655 | * as that may want to be batched with other set_domain operations | |
2656 | * | |
2657 | * This is (we hope) the only really tricky part of gem. The goal | |
2658 | * is fairly simple -- track which caches hold bits of the object | |
2659 | * and make sure they remain coherent. A few concrete examples may | |
2660 | * help to explain how it works. For shorthand, we use the notation | |
2661 | * (read_domains, write_domain), e.g. (CPU, CPU) to indicate the | |
2662 | * a pair of read and write domain masks. | |
2663 | * | |
2664 | * Case 1: the batch buffer | |
2665 | * | |
2666 | * 1. Allocated | |
2667 | * 2. Written by CPU | |
2668 | * 3. Mapped to GTT | |
2669 | * 4. Read by GPU | |
2670 | * 5. Unmapped from GTT | |
2671 | * 6. Freed | |
2672 | * | |
2673 | * Let's take these a step at a time | |
2674 | * | |
2675 | * 1. Allocated | |
2676 | * Pages allocated from the kernel may still have | |
2677 | * cache contents, so we set them to (CPU, CPU) always. | |
2678 | * 2. Written by CPU (using pwrite) | |
2679 | * The pwrite function calls set_domain (CPU, CPU) and | |
2680 | * this function does nothing (as nothing changes) | |
2681 | * 3. Mapped by GTT | |
2682 | * This function asserts that the object is not | |
2683 | * currently in any GPU-based read or write domains | |
2684 | * 4. Read by GPU | |
2685 | * i915_gem_execbuffer calls set_domain (COMMAND, 0). | |
2686 | * As write_domain is zero, this function adds in the | |
2687 | * current read domains (CPU+COMMAND, 0). | |
2688 | * flush_domains is set to CPU. | |
2689 | * invalidate_domains is set to COMMAND | |
2690 | * clflush is run to get data out of the CPU caches | |
2691 | * then i915_dev_set_domain calls i915_gem_flush to | |
2692 | * emit an MI_FLUSH and drm_agp_chipset_flush | |
2693 | * 5. Unmapped from GTT | |
2694 | * i915_gem_object_unbind calls set_domain (CPU, CPU) | |
2695 | * flush_domains and invalidate_domains end up both zero | |
2696 | * so no flushing/invalidating happens | |
2697 | * 6. Freed | |
2698 | * yay, done | |
2699 | * | |
2700 | * Case 2: The shared render buffer | |
2701 | * | |
2702 | * 1. Allocated | |
2703 | * 2. Mapped to GTT | |
2704 | * 3. Read/written by GPU | |
2705 | * 4. set_domain to (CPU,CPU) | |
2706 | * 5. Read/written by CPU | |
2707 | * 6. Read/written by GPU | |
2708 | * | |
2709 | * 1. Allocated | |
2710 | * Same as last example, (CPU, CPU) | |
2711 | * 2. Mapped to GTT | |
2712 | * Nothing changes (assertions find that it is not in the GPU) | |
2713 | * 3. Read/written by GPU | |
2714 | * execbuffer calls set_domain (RENDER, RENDER) | |
2715 | * flush_domains gets CPU | |
2716 | * invalidate_domains gets GPU | |
2717 | * clflush (obj) | |
2718 | * MI_FLUSH and drm_agp_chipset_flush | |
2719 | * 4. set_domain (CPU, CPU) | |
2720 | * flush_domains gets GPU | |
2721 | * invalidate_domains gets CPU | |
2722 | * wait_rendering (obj) to make sure all drawing is complete. | |
2723 | * This will include an MI_FLUSH to get the data from GPU | |
2724 | * to memory | |
2725 | * clflush (obj) to invalidate the CPU cache | |
2726 | * Another MI_FLUSH in i915_gem_flush (eliminate this somehow?) | |
2727 | * 5. Read/written by CPU | |
2728 | * cache lines are loaded and dirtied | |
2729 | * 6. Read written by GPU | |
2730 | * Same as last GPU access | |
2731 | * | |
2732 | * Case 3: The constant buffer | |
2733 | * | |
2734 | * 1. Allocated | |
2735 | * 2. Written by CPU | |
2736 | * 3. Read by GPU | |
2737 | * 4. Updated (written) by CPU again | |
2738 | * 5. Read by GPU | |
2739 | * | |
2740 | * 1. Allocated | |
2741 | * (CPU, CPU) | |
2742 | * 2. Written by CPU | |
2743 | * (CPU, CPU) | |
2744 | * 3. Read by GPU | |
2745 | * (CPU+RENDER, 0) | |
2746 | * flush_domains = CPU | |
2747 | * invalidate_domains = RENDER | |
2748 | * clflush (obj) | |
2749 | * MI_FLUSH | |
2750 | * drm_agp_chipset_flush | |
2751 | * 4. Updated (written) by CPU again | |
2752 | * (CPU, CPU) | |
2753 | * flush_domains = 0 (no previous write domain) | |
2754 | * invalidate_domains = 0 (no new read domains) | |
2755 | * 5. Read by GPU | |
2756 | * (CPU+RENDER, 0) | |
2757 | * flush_domains = CPU | |
2758 | * invalidate_domains = RENDER | |
2759 | * clflush (obj) | |
2760 | * MI_FLUSH | |
2761 | * drm_agp_chipset_flush | |
2762 | */ | |
c0d90829 | 2763 | static void |
8b0e378a | 2764 | i915_gem_object_set_to_gpu_domain(struct drm_gem_object *obj) |
673a394b EA |
2765 | { |
2766 | struct drm_device *dev = obj->dev; | |
2767 | struct drm_i915_gem_object *obj_priv = obj->driver_private; | |
2768 | uint32_t invalidate_domains = 0; | |
2769 | uint32_t flush_domains = 0; | |
e47c68e9 | 2770 | |
8b0e378a EA |
2771 | BUG_ON(obj->pending_read_domains & I915_GEM_DOMAIN_CPU); |
2772 | BUG_ON(obj->pending_write_domain == I915_GEM_DOMAIN_CPU); | |
673a394b | 2773 | |
652c393a JB |
2774 | intel_mark_busy(dev, obj); |
2775 | ||
673a394b EA |
2776 | #if WATCH_BUF |
2777 | DRM_INFO("%s: object %p read %08x -> %08x write %08x -> %08x\n", | |
2778 | __func__, obj, | |
8b0e378a EA |
2779 | obj->read_domains, obj->pending_read_domains, |
2780 | obj->write_domain, obj->pending_write_domain); | |
673a394b EA |
2781 | #endif |
2782 | /* | |
2783 | * If the object isn't moving to a new write domain, | |
2784 | * let the object stay in multiple read domains | |
2785 | */ | |
8b0e378a EA |
2786 | if (obj->pending_write_domain == 0) |
2787 | obj->pending_read_domains |= obj->read_domains; | |
673a394b EA |
2788 | else |
2789 | obj_priv->dirty = 1; | |
2790 | ||
2791 | /* | |
2792 | * Flush the current write domain if | |
2793 | * the new read domains don't match. Invalidate | |
2794 | * any read domains which differ from the old | |
2795 | * write domain | |
2796 | */ | |
8b0e378a EA |
2797 | if (obj->write_domain && |
2798 | obj->write_domain != obj->pending_read_domains) { | |
673a394b | 2799 | flush_domains |= obj->write_domain; |
8b0e378a EA |
2800 | invalidate_domains |= |
2801 | obj->pending_read_domains & ~obj->write_domain; | |
673a394b EA |
2802 | } |
2803 | /* | |
2804 | * Invalidate any read caches which may have | |
2805 | * stale data. That is, any new read domains. | |
2806 | */ | |
8b0e378a | 2807 | invalidate_domains |= obj->pending_read_domains & ~obj->read_domains; |
673a394b EA |
2808 | if ((flush_domains | invalidate_domains) & I915_GEM_DOMAIN_CPU) { |
2809 | #if WATCH_BUF | |
2810 | DRM_INFO("%s: CPU domain flush %08x invalidate %08x\n", | |
2811 | __func__, flush_domains, invalidate_domains); | |
2812 | #endif | |
673a394b EA |
2813 | i915_gem_clflush_object(obj); |
2814 | } | |
2815 | ||
efbeed96 EA |
2816 | /* The actual obj->write_domain will be updated with |
2817 | * pending_write_domain after we emit the accumulated flush for all | |
2818 | * of our domain changes in execbuffers (which clears objects' | |
2819 | * write_domains). So if we have a current write domain that we | |
2820 | * aren't changing, set pending_write_domain to that. | |
2821 | */ | |
2822 | if (flush_domains == 0 && obj->pending_write_domain == 0) | |
2823 | obj->pending_write_domain = obj->write_domain; | |
8b0e378a | 2824 | obj->read_domains = obj->pending_read_domains; |
673a394b EA |
2825 | |
2826 | dev->invalidate_domains |= invalidate_domains; | |
2827 | dev->flush_domains |= flush_domains; | |
2828 | #if WATCH_BUF | |
2829 | DRM_INFO("%s: read %08x write %08x invalidate %08x flush %08x\n", | |
2830 | __func__, | |
2831 | obj->read_domains, obj->write_domain, | |
2832 | dev->invalidate_domains, dev->flush_domains); | |
2833 | #endif | |
673a394b EA |
2834 | } |
2835 | ||
2836 | /** | |
e47c68e9 | 2837 | * Moves the object from a partially CPU read to a full one. |
673a394b | 2838 | * |
e47c68e9 EA |
2839 | * Note that this only resolves i915_gem_object_set_cpu_read_domain_range(), |
2840 | * and doesn't handle transitioning from !(read_domains & I915_GEM_DOMAIN_CPU). | |
673a394b | 2841 | */ |
e47c68e9 EA |
2842 | static void |
2843 | i915_gem_object_set_to_full_cpu_read_domain(struct drm_gem_object *obj) | |
673a394b EA |
2844 | { |
2845 | struct drm_i915_gem_object *obj_priv = obj->driver_private; | |
673a394b | 2846 | |
e47c68e9 EA |
2847 | if (!obj_priv->page_cpu_valid) |
2848 | return; | |
2849 | ||
2850 | /* If we're partially in the CPU read domain, finish moving it in. | |
2851 | */ | |
2852 | if (obj->read_domains & I915_GEM_DOMAIN_CPU) { | |
2853 | int i; | |
2854 | ||
2855 | for (i = 0; i <= (obj->size - 1) / PAGE_SIZE; i++) { | |
2856 | if (obj_priv->page_cpu_valid[i]) | |
2857 | continue; | |
856fa198 | 2858 | drm_clflush_pages(obj_priv->pages + i, 1); |
e47c68e9 | 2859 | } |
e47c68e9 EA |
2860 | } |
2861 | ||
2862 | /* Free the page_cpu_valid mappings which are now stale, whether | |
2863 | * or not we've got I915_GEM_DOMAIN_CPU. | |
2864 | */ | |
9a298b2a | 2865 | kfree(obj_priv->page_cpu_valid); |
e47c68e9 EA |
2866 | obj_priv->page_cpu_valid = NULL; |
2867 | } | |
2868 | ||
2869 | /** | |
2870 | * Set the CPU read domain on a range of the object. | |
2871 | * | |
2872 | * The object ends up with I915_GEM_DOMAIN_CPU in its read flags although it's | |
2873 | * not entirely valid. The page_cpu_valid member of the object flags which | |
2874 | * pages have been flushed, and will be respected by | |
2875 | * i915_gem_object_set_to_cpu_domain() if it's called on to get a valid mapping | |
2876 | * of the whole object. | |
2877 | * | |
2878 | * This function returns when the move is complete, including waiting on | |
2879 | * flushes to occur. | |
2880 | */ | |
2881 | static int | |
2882 | i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object *obj, | |
2883 | uint64_t offset, uint64_t size) | |
2884 | { | |
2885 | struct drm_i915_gem_object *obj_priv = obj->driver_private; | |
2886 | int i, ret; | |
673a394b | 2887 | |
e47c68e9 EA |
2888 | if (offset == 0 && size == obj->size) |
2889 | return i915_gem_object_set_to_cpu_domain(obj, 0); | |
673a394b | 2890 | |
e47c68e9 EA |
2891 | i915_gem_object_flush_gpu_write_domain(obj); |
2892 | /* Wait on any GPU rendering and flushing to occur. */ | |
6a47baa6 | 2893 | ret = i915_gem_object_wait_rendering(obj); |
e47c68e9 | 2894 | if (ret != 0) |
6a47baa6 | 2895 | return ret; |
e47c68e9 EA |
2896 | i915_gem_object_flush_gtt_write_domain(obj); |
2897 | ||
2898 | /* If we're already fully in the CPU read domain, we're done. */ | |
2899 | if (obj_priv->page_cpu_valid == NULL && | |
2900 | (obj->read_domains & I915_GEM_DOMAIN_CPU) != 0) | |
2901 | return 0; | |
673a394b | 2902 | |
e47c68e9 EA |
2903 | /* Otherwise, create/clear the per-page CPU read domain flag if we're |
2904 | * newly adding I915_GEM_DOMAIN_CPU | |
2905 | */ | |
673a394b | 2906 | if (obj_priv->page_cpu_valid == NULL) { |
9a298b2a EA |
2907 | obj_priv->page_cpu_valid = kzalloc(obj->size / PAGE_SIZE, |
2908 | GFP_KERNEL); | |
e47c68e9 EA |
2909 | if (obj_priv->page_cpu_valid == NULL) |
2910 | return -ENOMEM; | |
2911 | } else if ((obj->read_domains & I915_GEM_DOMAIN_CPU) == 0) | |
2912 | memset(obj_priv->page_cpu_valid, 0, obj->size / PAGE_SIZE); | |
673a394b EA |
2913 | |
2914 | /* Flush the cache on any pages that are still invalid from the CPU's | |
2915 | * perspective. | |
2916 | */ | |
e47c68e9 EA |
2917 | for (i = offset / PAGE_SIZE; i <= (offset + size - 1) / PAGE_SIZE; |
2918 | i++) { | |
673a394b EA |
2919 | if (obj_priv->page_cpu_valid[i]) |
2920 | continue; | |
2921 | ||
856fa198 | 2922 | drm_clflush_pages(obj_priv->pages + i, 1); |
673a394b EA |
2923 | |
2924 | obj_priv->page_cpu_valid[i] = 1; | |
2925 | } | |
2926 | ||
e47c68e9 EA |
2927 | /* It should now be out of any other write domains, and we can update |
2928 | * the domain values for our changes. | |
2929 | */ | |
2930 | BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_CPU) != 0); | |
2931 | ||
2932 | obj->read_domains |= I915_GEM_DOMAIN_CPU; | |
2933 | ||
673a394b EA |
2934 | return 0; |
2935 | } | |
2936 | ||
673a394b EA |
2937 | /** |
2938 | * Pin an object to the GTT and evaluate the relocations landing in it. | |
2939 | */ | |
2940 | static int | |
2941 | i915_gem_object_pin_and_relocate(struct drm_gem_object *obj, | |
2942 | struct drm_file *file_priv, | |
40a5f0de EA |
2943 | struct drm_i915_gem_exec_object *entry, |
2944 | struct drm_i915_gem_relocation_entry *relocs) | |
673a394b EA |
2945 | { |
2946 | struct drm_device *dev = obj->dev; | |
0839ccb8 | 2947 | drm_i915_private_t *dev_priv = dev->dev_private; |
673a394b EA |
2948 | struct drm_i915_gem_object *obj_priv = obj->driver_private; |
2949 | int i, ret; | |
0839ccb8 | 2950 | void __iomem *reloc_page; |
673a394b EA |
2951 | |
2952 | /* Choose the GTT offset for our buffer and put it there. */ | |
2953 | ret = i915_gem_object_pin(obj, (uint32_t) entry->alignment); | |
2954 | if (ret) | |
2955 | return ret; | |
2956 | ||
2957 | entry->offset = obj_priv->gtt_offset; | |
2958 | ||
673a394b EA |
2959 | /* Apply the relocations, using the GTT aperture to avoid cache |
2960 | * flushing requirements. | |
2961 | */ | |
2962 | for (i = 0; i < entry->relocation_count; i++) { | |
40a5f0de | 2963 | struct drm_i915_gem_relocation_entry *reloc= &relocs[i]; |
673a394b EA |
2964 | struct drm_gem_object *target_obj; |
2965 | struct drm_i915_gem_object *target_obj_priv; | |
3043c60c EA |
2966 | uint32_t reloc_val, reloc_offset; |
2967 | uint32_t __iomem *reloc_entry; | |
673a394b | 2968 | |
673a394b | 2969 | target_obj = drm_gem_object_lookup(obj->dev, file_priv, |
40a5f0de | 2970 | reloc->target_handle); |
673a394b EA |
2971 | if (target_obj == NULL) { |
2972 | i915_gem_object_unpin(obj); | |
2973 | return -EBADF; | |
2974 | } | |
2975 | target_obj_priv = target_obj->driver_private; | |
2976 | ||
2977 | /* The target buffer should have appeared before us in the | |
2978 | * exec_object list, so it should have a GTT space bound by now. | |
2979 | */ | |
2980 | if (target_obj_priv->gtt_space == NULL) { | |
2981 | DRM_ERROR("No GTT space found for object %d\n", | |
40a5f0de | 2982 | reloc->target_handle); |
673a394b EA |
2983 | drm_gem_object_unreference(target_obj); |
2984 | i915_gem_object_unpin(obj); | |
2985 | return -EINVAL; | |
2986 | } | |
2987 | ||
40a5f0de | 2988 | if (reloc->offset > obj->size - 4) { |
673a394b EA |
2989 | DRM_ERROR("Relocation beyond object bounds: " |
2990 | "obj %p target %d offset %d size %d.\n", | |
40a5f0de EA |
2991 | obj, reloc->target_handle, |
2992 | (int) reloc->offset, (int) obj->size); | |
673a394b EA |
2993 | drm_gem_object_unreference(target_obj); |
2994 | i915_gem_object_unpin(obj); | |
2995 | return -EINVAL; | |
2996 | } | |
40a5f0de | 2997 | if (reloc->offset & 3) { |
673a394b EA |
2998 | DRM_ERROR("Relocation not 4-byte aligned: " |
2999 | "obj %p target %d offset %d.\n", | |
40a5f0de EA |
3000 | obj, reloc->target_handle, |
3001 | (int) reloc->offset); | |
673a394b EA |
3002 | drm_gem_object_unreference(target_obj); |
3003 | i915_gem_object_unpin(obj); | |
3004 | return -EINVAL; | |
3005 | } | |
3006 | ||
40a5f0de EA |
3007 | if (reloc->write_domain & I915_GEM_DOMAIN_CPU || |
3008 | reloc->read_domains & I915_GEM_DOMAIN_CPU) { | |
e47c68e9 EA |
3009 | DRM_ERROR("reloc with read/write CPU domains: " |
3010 | "obj %p target %d offset %d " | |
3011 | "read %08x write %08x", | |
40a5f0de EA |
3012 | obj, reloc->target_handle, |
3013 | (int) reloc->offset, | |
3014 | reloc->read_domains, | |
3015 | reloc->write_domain); | |
491152b8 CW |
3016 | drm_gem_object_unreference(target_obj); |
3017 | i915_gem_object_unpin(obj); | |
e47c68e9 EA |
3018 | return -EINVAL; |
3019 | } | |
3020 | ||
40a5f0de EA |
3021 | if (reloc->write_domain && target_obj->pending_write_domain && |
3022 | reloc->write_domain != target_obj->pending_write_domain) { | |
673a394b EA |
3023 | DRM_ERROR("Write domain conflict: " |
3024 | "obj %p target %d offset %d " | |
3025 | "new %08x old %08x\n", | |
40a5f0de EA |
3026 | obj, reloc->target_handle, |
3027 | (int) reloc->offset, | |
3028 | reloc->write_domain, | |
673a394b EA |
3029 | target_obj->pending_write_domain); |
3030 | drm_gem_object_unreference(target_obj); | |
3031 | i915_gem_object_unpin(obj); | |
3032 | return -EINVAL; | |
3033 | } | |
3034 | ||
3035 | #if WATCH_RELOC | |
3036 | DRM_INFO("%s: obj %p offset %08x target %d " | |
3037 | "read %08x write %08x gtt %08x " | |
3038 | "presumed %08x delta %08x\n", | |
3039 | __func__, | |
3040 | obj, | |
40a5f0de EA |
3041 | (int) reloc->offset, |
3042 | (int) reloc->target_handle, | |
3043 | (int) reloc->read_domains, | |
3044 | (int) reloc->write_domain, | |
673a394b | 3045 | (int) target_obj_priv->gtt_offset, |
40a5f0de EA |
3046 | (int) reloc->presumed_offset, |
3047 | reloc->delta); | |
673a394b EA |
3048 | #endif |
3049 | ||
40a5f0de EA |
3050 | target_obj->pending_read_domains |= reloc->read_domains; |
3051 | target_obj->pending_write_domain |= reloc->write_domain; | |
673a394b EA |
3052 | |
3053 | /* If the relocation already has the right value in it, no | |
3054 | * more work needs to be done. | |
3055 | */ | |
40a5f0de | 3056 | if (target_obj_priv->gtt_offset == reloc->presumed_offset) { |
673a394b EA |
3057 | drm_gem_object_unreference(target_obj); |
3058 | continue; | |
3059 | } | |
3060 | ||
2ef7eeaa EA |
3061 | ret = i915_gem_object_set_to_gtt_domain(obj, 1); |
3062 | if (ret != 0) { | |
3063 | drm_gem_object_unreference(target_obj); | |
3064 | i915_gem_object_unpin(obj); | |
3065 | return -EINVAL; | |
673a394b EA |
3066 | } |
3067 | ||
3068 | /* Map the page containing the relocation we're going to | |
3069 | * perform. | |
3070 | */ | |
40a5f0de | 3071 | reloc_offset = obj_priv->gtt_offset + reloc->offset; |
0839ccb8 KP |
3072 | reloc_page = io_mapping_map_atomic_wc(dev_priv->mm.gtt_mapping, |
3073 | (reloc_offset & | |
3074 | ~(PAGE_SIZE - 1))); | |
3043c60c | 3075 | reloc_entry = (uint32_t __iomem *)(reloc_page + |
0839ccb8 | 3076 | (reloc_offset & (PAGE_SIZE - 1))); |
40a5f0de | 3077 | reloc_val = target_obj_priv->gtt_offset + reloc->delta; |
673a394b EA |
3078 | |
3079 | #if WATCH_BUF | |
3080 | DRM_INFO("Applied relocation: %p@0x%08x %08x -> %08x\n", | |
40a5f0de | 3081 | obj, (unsigned int) reloc->offset, |
673a394b EA |
3082 | readl(reloc_entry), reloc_val); |
3083 | #endif | |
3084 | writel(reloc_val, reloc_entry); | |
0839ccb8 | 3085 | io_mapping_unmap_atomic(reloc_page); |
673a394b | 3086 | |
40a5f0de EA |
3087 | /* The updated presumed offset for this entry will be |
3088 | * copied back out to the user. | |
673a394b | 3089 | */ |
40a5f0de | 3090 | reloc->presumed_offset = target_obj_priv->gtt_offset; |
673a394b EA |
3091 | |
3092 | drm_gem_object_unreference(target_obj); | |
3093 | } | |
3094 | ||
673a394b EA |
3095 | #if WATCH_BUF |
3096 | if (0) | |
3097 | i915_gem_dump_object(obj, 128, __func__, ~0); | |
3098 | #endif | |
3099 | return 0; | |
3100 | } | |
3101 | ||
3102 | /** Dispatch a batchbuffer to the ring | |
3103 | */ | |
3104 | static int | |
3105 | i915_dispatch_gem_execbuffer(struct drm_device *dev, | |
3106 | struct drm_i915_gem_execbuffer *exec, | |
201361a5 | 3107 | struct drm_clip_rect *cliprects, |
673a394b EA |
3108 | uint64_t exec_offset) |
3109 | { | |
3110 | drm_i915_private_t *dev_priv = dev->dev_private; | |
673a394b EA |
3111 | int nbox = exec->num_cliprects; |
3112 | int i = 0, count; | |
83d60795 | 3113 | uint32_t exec_start, exec_len; |
673a394b EA |
3114 | RING_LOCALS; |
3115 | ||
3116 | exec_start = (uint32_t) exec_offset + exec->batch_start_offset; | |
3117 | exec_len = (uint32_t) exec->batch_len; | |
3118 | ||
673a394b EA |
3119 | count = nbox ? nbox : 1; |
3120 | ||
3121 | for (i = 0; i < count; i++) { | |
3122 | if (i < nbox) { | |
201361a5 | 3123 | int ret = i915_emit_box(dev, cliprects, i, |
673a394b EA |
3124 | exec->DR1, exec->DR4); |
3125 | if (ret) | |
3126 | return ret; | |
3127 | } | |
3128 | ||
3129 | if (IS_I830(dev) || IS_845G(dev)) { | |
3130 | BEGIN_LP_RING(4); | |
3131 | OUT_RING(MI_BATCH_BUFFER); | |
3132 | OUT_RING(exec_start | MI_BATCH_NON_SECURE); | |
3133 | OUT_RING(exec_start + exec_len - 4); | |
3134 | OUT_RING(0); | |
3135 | ADVANCE_LP_RING(); | |
3136 | } else { | |
3137 | BEGIN_LP_RING(2); | |
3138 | if (IS_I965G(dev)) { | |
3139 | OUT_RING(MI_BATCH_BUFFER_START | | |
3140 | (2 << 6) | | |
3141 | MI_BATCH_NON_SECURE_I965); | |
3142 | OUT_RING(exec_start); | |
3143 | } else { | |
3144 | OUT_RING(MI_BATCH_BUFFER_START | | |
3145 | (2 << 6)); | |
3146 | OUT_RING(exec_start | MI_BATCH_NON_SECURE); | |
3147 | } | |
3148 | ADVANCE_LP_RING(); | |
3149 | } | |
3150 | } | |
3151 | ||
3152 | /* XXX breadcrumb */ | |
3153 | return 0; | |
3154 | } | |
3155 | ||
3156 | /* Throttle our rendering by waiting until the ring has completed our requests | |
3157 | * emitted over 20 msec ago. | |
3158 | * | |
b962442e EA |
3159 | * Note that if we were to use the current jiffies each time around the loop, |
3160 | * we wouldn't escape the function with any frames outstanding if the time to | |
3161 | * render a frame was over 20ms. | |
3162 | * | |
673a394b EA |
3163 | * This should get us reasonable parallelism between CPU and GPU but also |
3164 | * relatively low latency when blocking on a particular request to finish. | |
3165 | */ | |
3166 | static int | |
3167 | i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file_priv) | |
3168 | { | |
3169 | struct drm_i915_file_private *i915_file_priv = file_priv->driver_priv; | |
3170 | int ret = 0; | |
b962442e | 3171 | unsigned long recent_enough = jiffies - msecs_to_jiffies(20); |
673a394b EA |
3172 | |
3173 | mutex_lock(&dev->struct_mutex); | |
b962442e EA |
3174 | while (!list_empty(&i915_file_priv->mm.request_list)) { |
3175 | struct drm_i915_gem_request *request; | |
3176 | ||
3177 | request = list_first_entry(&i915_file_priv->mm.request_list, | |
3178 | struct drm_i915_gem_request, | |
3179 | client_list); | |
3180 | ||
3181 | if (time_after_eq(request->emitted_jiffies, recent_enough)) | |
3182 | break; | |
3183 | ||
3184 | ret = i915_wait_request(dev, request->seqno); | |
3185 | if (ret != 0) | |
3186 | break; | |
3187 | } | |
673a394b | 3188 | mutex_unlock(&dev->struct_mutex); |
b962442e | 3189 | |
673a394b EA |
3190 | return ret; |
3191 | } | |
3192 | ||
40a5f0de EA |
3193 | static int |
3194 | i915_gem_get_relocs_from_user(struct drm_i915_gem_exec_object *exec_list, | |
3195 | uint32_t buffer_count, | |
3196 | struct drm_i915_gem_relocation_entry **relocs) | |
3197 | { | |
3198 | uint32_t reloc_count = 0, reloc_index = 0, i; | |
3199 | int ret; | |
3200 | ||
3201 | *relocs = NULL; | |
3202 | for (i = 0; i < buffer_count; i++) { | |
3203 | if (reloc_count + exec_list[i].relocation_count < reloc_count) | |
3204 | return -EINVAL; | |
3205 | reloc_count += exec_list[i].relocation_count; | |
3206 | } | |
3207 | ||
8e7d2b2c | 3208 | *relocs = drm_calloc_large(reloc_count, sizeof(**relocs)); |
40a5f0de EA |
3209 | if (*relocs == NULL) |
3210 | return -ENOMEM; | |
3211 | ||
3212 | for (i = 0; i < buffer_count; i++) { | |
3213 | struct drm_i915_gem_relocation_entry __user *user_relocs; | |
3214 | ||
3215 | user_relocs = (void __user *)(uintptr_t)exec_list[i].relocs_ptr; | |
3216 | ||
3217 | ret = copy_from_user(&(*relocs)[reloc_index], | |
3218 | user_relocs, | |
3219 | exec_list[i].relocation_count * | |
3220 | sizeof(**relocs)); | |
3221 | if (ret != 0) { | |
8e7d2b2c | 3222 | drm_free_large(*relocs); |
40a5f0de | 3223 | *relocs = NULL; |
2bc43b5c | 3224 | return -EFAULT; |
40a5f0de EA |
3225 | } |
3226 | ||
3227 | reloc_index += exec_list[i].relocation_count; | |
3228 | } | |
3229 | ||
2bc43b5c | 3230 | return 0; |
40a5f0de EA |
3231 | } |
3232 | ||
3233 | static int | |
3234 | i915_gem_put_relocs_to_user(struct drm_i915_gem_exec_object *exec_list, | |
3235 | uint32_t buffer_count, | |
3236 | struct drm_i915_gem_relocation_entry *relocs) | |
3237 | { | |
3238 | uint32_t reloc_count = 0, i; | |
2bc43b5c | 3239 | int ret = 0; |
40a5f0de EA |
3240 | |
3241 | for (i = 0; i < buffer_count; i++) { | |
3242 | struct drm_i915_gem_relocation_entry __user *user_relocs; | |
2bc43b5c | 3243 | int unwritten; |
40a5f0de EA |
3244 | |
3245 | user_relocs = (void __user *)(uintptr_t)exec_list[i].relocs_ptr; | |
3246 | ||
2bc43b5c FM |
3247 | unwritten = copy_to_user(user_relocs, |
3248 | &relocs[reloc_count], | |
3249 | exec_list[i].relocation_count * | |
3250 | sizeof(*relocs)); | |
3251 | ||
3252 | if (unwritten) { | |
3253 | ret = -EFAULT; | |
3254 | goto err; | |
40a5f0de EA |
3255 | } |
3256 | ||
3257 | reloc_count += exec_list[i].relocation_count; | |
3258 | } | |
3259 | ||
2bc43b5c | 3260 | err: |
8e7d2b2c | 3261 | drm_free_large(relocs); |
40a5f0de EA |
3262 | |
3263 | return ret; | |
3264 | } | |
3265 | ||
83d60795 CW |
3266 | static int |
3267 | i915_gem_check_execbuffer (struct drm_i915_gem_execbuffer *exec, | |
3268 | uint64_t exec_offset) | |
3269 | { | |
3270 | uint32_t exec_start, exec_len; | |
3271 | ||
3272 | exec_start = (uint32_t) exec_offset + exec->batch_start_offset; | |
3273 | exec_len = (uint32_t) exec->batch_len; | |
3274 | ||
3275 | if ((exec_start | exec_len) & 0x7) | |
3276 | return -EINVAL; | |
3277 | ||
3278 | if (!exec_start) | |
3279 | return -EINVAL; | |
3280 | ||
3281 | return 0; | |
3282 | } | |
3283 | ||
673a394b EA |
3284 | int |
3285 | i915_gem_execbuffer(struct drm_device *dev, void *data, | |
3286 | struct drm_file *file_priv) | |
3287 | { | |
3288 | drm_i915_private_t *dev_priv = dev->dev_private; | |
673a394b EA |
3289 | struct drm_i915_gem_execbuffer *args = data; |
3290 | struct drm_i915_gem_exec_object *exec_list = NULL; | |
3291 | struct drm_gem_object **object_list = NULL; | |
3292 | struct drm_gem_object *batch_obj; | |
b70d11da | 3293 | struct drm_i915_gem_object *obj_priv; |
201361a5 | 3294 | struct drm_clip_rect *cliprects = NULL; |
40a5f0de EA |
3295 | struct drm_i915_gem_relocation_entry *relocs; |
3296 | int ret, ret2, i, pinned = 0; | |
673a394b | 3297 | uint64_t exec_offset; |
40a5f0de | 3298 | uint32_t seqno, flush_domains, reloc_index; |
ac94a962 | 3299 | int pin_tries; |
673a394b EA |
3300 | |
3301 | #if WATCH_EXEC | |
3302 | DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n", | |
3303 | (int) args->buffers_ptr, args->buffer_count, args->batch_len); | |
3304 | #endif | |
3305 | ||
4f481ed2 EA |
3306 | if (args->buffer_count < 1) { |
3307 | DRM_ERROR("execbuf with %d buffers\n", args->buffer_count); | |
3308 | return -EINVAL; | |
3309 | } | |
673a394b | 3310 | /* Copy in the exec list from userland */ |
8e7d2b2c JB |
3311 | exec_list = drm_calloc_large(sizeof(*exec_list), args->buffer_count); |
3312 | object_list = drm_calloc_large(sizeof(*object_list), args->buffer_count); | |
673a394b EA |
3313 | if (exec_list == NULL || object_list == NULL) { |
3314 | DRM_ERROR("Failed to allocate exec or object list " | |
3315 | "for %d buffers\n", | |
3316 | args->buffer_count); | |
3317 | ret = -ENOMEM; | |
3318 | goto pre_mutex_err; | |
3319 | } | |
3320 | ret = copy_from_user(exec_list, | |
3321 | (struct drm_i915_relocation_entry __user *) | |
3322 | (uintptr_t) args->buffers_ptr, | |
3323 | sizeof(*exec_list) * args->buffer_count); | |
3324 | if (ret != 0) { | |
3325 | DRM_ERROR("copy %d exec entries failed %d\n", | |
3326 | args->buffer_count, ret); | |
3327 | goto pre_mutex_err; | |
3328 | } | |
3329 | ||
201361a5 | 3330 | if (args->num_cliprects != 0) { |
9a298b2a EA |
3331 | cliprects = kcalloc(args->num_cliprects, sizeof(*cliprects), |
3332 | GFP_KERNEL); | |
201361a5 EA |
3333 | if (cliprects == NULL) |
3334 | goto pre_mutex_err; | |
3335 | ||
3336 | ret = copy_from_user(cliprects, | |
3337 | (struct drm_clip_rect __user *) | |
3338 | (uintptr_t) args->cliprects_ptr, | |
3339 | sizeof(*cliprects) * args->num_cliprects); | |
3340 | if (ret != 0) { | |
3341 | DRM_ERROR("copy %d cliprects failed: %d\n", | |
3342 | args->num_cliprects, ret); | |
3343 | goto pre_mutex_err; | |
3344 | } | |
3345 | } | |
3346 | ||
40a5f0de EA |
3347 | ret = i915_gem_get_relocs_from_user(exec_list, args->buffer_count, |
3348 | &relocs); | |
3349 | if (ret != 0) | |
3350 | goto pre_mutex_err; | |
3351 | ||
673a394b EA |
3352 | mutex_lock(&dev->struct_mutex); |
3353 | ||
3354 | i915_verify_inactive(dev, __FILE__, __LINE__); | |
3355 | ||
3356 | if (dev_priv->mm.wedged) { | |
3357 | DRM_ERROR("Execbuf while wedged\n"); | |
3358 | mutex_unlock(&dev->struct_mutex); | |
a198bc80 CW |
3359 | ret = -EIO; |
3360 | goto pre_mutex_err; | |
673a394b EA |
3361 | } |
3362 | ||
3363 | if (dev_priv->mm.suspended) { | |
3364 | DRM_ERROR("Execbuf while VT-switched.\n"); | |
3365 | mutex_unlock(&dev->struct_mutex); | |
a198bc80 CW |
3366 | ret = -EBUSY; |
3367 | goto pre_mutex_err; | |
673a394b EA |
3368 | } |
3369 | ||
ac94a962 | 3370 | /* Look up object handles */ |
673a394b EA |
3371 | for (i = 0; i < args->buffer_count; i++) { |
3372 | object_list[i] = drm_gem_object_lookup(dev, file_priv, | |
3373 | exec_list[i].handle); | |
3374 | if (object_list[i] == NULL) { | |
3375 | DRM_ERROR("Invalid object handle %d at index %d\n", | |
3376 | exec_list[i].handle, i); | |
3377 | ret = -EBADF; | |
3378 | goto err; | |
3379 | } | |
b70d11da KH |
3380 | |
3381 | obj_priv = object_list[i]->driver_private; | |
3382 | if (obj_priv->in_execbuffer) { | |
3383 | DRM_ERROR("Object %p appears more than once in object list\n", | |
3384 | object_list[i]); | |
3385 | ret = -EBADF; | |
3386 | goto err; | |
3387 | } | |
3388 | obj_priv->in_execbuffer = true; | |
ac94a962 | 3389 | } |
673a394b | 3390 | |
ac94a962 KP |
3391 | /* Pin and relocate */ |
3392 | for (pin_tries = 0; ; pin_tries++) { | |
3393 | ret = 0; | |
40a5f0de EA |
3394 | reloc_index = 0; |
3395 | ||
ac94a962 KP |
3396 | for (i = 0; i < args->buffer_count; i++) { |
3397 | object_list[i]->pending_read_domains = 0; | |
3398 | object_list[i]->pending_write_domain = 0; | |
3399 | ret = i915_gem_object_pin_and_relocate(object_list[i], | |
3400 | file_priv, | |
40a5f0de EA |
3401 | &exec_list[i], |
3402 | &relocs[reloc_index]); | |
ac94a962 KP |
3403 | if (ret) |
3404 | break; | |
3405 | pinned = i + 1; | |
40a5f0de | 3406 | reloc_index += exec_list[i].relocation_count; |
ac94a962 KP |
3407 | } |
3408 | /* success */ | |
3409 | if (ret == 0) | |
3410 | break; | |
3411 | ||
3412 | /* error other than GTT full, or we've already tried again */ | |
2939e1f5 | 3413 | if (ret != -ENOSPC || pin_tries >= 1) { |
f1acec93 EA |
3414 | if (ret != -ERESTARTSYS) |
3415 | DRM_ERROR("Failed to pin buffers %d\n", ret); | |
673a394b EA |
3416 | goto err; |
3417 | } | |
ac94a962 KP |
3418 | |
3419 | /* unpin all of our buffers */ | |
3420 | for (i = 0; i < pinned; i++) | |
3421 | i915_gem_object_unpin(object_list[i]); | |
b1177636 | 3422 | pinned = 0; |
ac94a962 KP |
3423 | |
3424 | /* evict everyone we can from the aperture */ | |
3425 | ret = i915_gem_evict_everything(dev); | |
3426 | if (ret) | |
3427 | goto err; | |
673a394b EA |
3428 | } |
3429 | ||
3430 | /* Set the pending read domains for the batch buffer to COMMAND */ | |
3431 | batch_obj = object_list[args->buffer_count-1]; | |
5f26a2c7 CW |
3432 | if (batch_obj->pending_write_domain) { |
3433 | DRM_ERROR("Attempting to use self-modifying batch buffer\n"); | |
3434 | ret = -EINVAL; | |
3435 | goto err; | |
3436 | } | |
3437 | batch_obj->pending_read_domains |= I915_GEM_DOMAIN_COMMAND; | |
673a394b | 3438 | |
83d60795 CW |
3439 | /* Sanity check the batch buffer, prior to moving objects */ |
3440 | exec_offset = exec_list[args->buffer_count - 1].offset; | |
3441 | ret = i915_gem_check_execbuffer (args, exec_offset); | |
3442 | if (ret != 0) { | |
3443 | DRM_ERROR("execbuf with invalid offset/length\n"); | |
3444 | goto err; | |
3445 | } | |
3446 | ||
673a394b EA |
3447 | i915_verify_inactive(dev, __FILE__, __LINE__); |
3448 | ||
646f0f6e KP |
3449 | /* Zero the global flush/invalidate flags. These |
3450 | * will be modified as new domains are computed | |
3451 | * for each object | |
3452 | */ | |
3453 | dev->invalidate_domains = 0; | |
3454 | dev->flush_domains = 0; | |
3455 | ||
673a394b EA |
3456 | for (i = 0; i < args->buffer_count; i++) { |
3457 | struct drm_gem_object *obj = object_list[i]; | |
673a394b | 3458 | |
646f0f6e | 3459 | /* Compute new gpu domains and update invalidate/flush */ |
8b0e378a | 3460 | i915_gem_object_set_to_gpu_domain(obj); |
673a394b EA |
3461 | } |
3462 | ||
3463 | i915_verify_inactive(dev, __FILE__, __LINE__); | |
3464 | ||
646f0f6e KP |
3465 | if (dev->invalidate_domains | dev->flush_domains) { |
3466 | #if WATCH_EXEC | |
3467 | DRM_INFO("%s: invalidate_domains %08x flush_domains %08x\n", | |
3468 | __func__, | |
3469 | dev->invalidate_domains, | |
3470 | dev->flush_domains); | |
3471 | #endif | |
3472 | i915_gem_flush(dev, | |
3473 | dev->invalidate_domains, | |
3474 | dev->flush_domains); | |
3475 | if (dev->flush_domains) | |
b962442e EA |
3476 | (void)i915_add_request(dev, file_priv, |
3477 | dev->flush_domains); | |
646f0f6e | 3478 | } |
673a394b | 3479 | |
efbeed96 EA |
3480 | for (i = 0; i < args->buffer_count; i++) { |
3481 | struct drm_gem_object *obj = object_list[i]; | |
3482 | ||
3483 | obj->write_domain = obj->pending_write_domain; | |
3484 | } | |
3485 | ||
673a394b EA |
3486 | i915_verify_inactive(dev, __FILE__, __LINE__); |
3487 | ||
3488 | #if WATCH_COHERENCY | |
3489 | for (i = 0; i < args->buffer_count; i++) { | |
3490 | i915_gem_object_check_coherency(object_list[i], | |
3491 | exec_list[i].handle); | |
3492 | } | |
3493 | #endif | |
3494 | ||
673a394b | 3495 | #if WATCH_EXEC |
6911a9b8 | 3496 | i915_gem_dump_object(batch_obj, |
673a394b EA |
3497 | args->batch_len, |
3498 | __func__, | |
3499 | ~0); | |
3500 | #endif | |
3501 | ||
673a394b | 3502 | /* Exec the batchbuffer */ |
201361a5 | 3503 | ret = i915_dispatch_gem_execbuffer(dev, args, cliprects, exec_offset); |
673a394b EA |
3504 | if (ret) { |
3505 | DRM_ERROR("dispatch failed %d\n", ret); | |
3506 | goto err; | |
3507 | } | |
3508 | ||
3509 | /* | |
3510 | * Ensure that the commands in the batch buffer are | |
3511 | * finished before the interrupt fires | |
3512 | */ | |
3513 | flush_domains = i915_retire_commands(dev); | |
3514 | ||
3515 | i915_verify_inactive(dev, __FILE__, __LINE__); | |
3516 | ||
3517 | /* | |
3518 | * Get a seqno representing the execution of the current buffer, | |
3519 | * which we can wait on. We would like to mitigate these interrupts, | |
3520 | * likely by only creating seqnos occasionally (so that we have | |
3521 | * *some* interrupts representing completion of buffers that we can | |
3522 | * wait on when trying to clear up gtt space). | |
3523 | */ | |
b962442e | 3524 | seqno = i915_add_request(dev, file_priv, flush_domains); |
673a394b | 3525 | BUG_ON(seqno == 0); |
673a394b EA |
3526 | for (i = 0; i < args->buffer_count; i++) { |
3527 | struct drm_gem_object *obj = object_list[i]; | |
673a394b | 3528 | |
ce44b0ea | 3529 | i915_gem_object_move_to_active(obj, seqno); |
673a394b EA |
3530 | #if WATCH_LRU |
3531 | DRM_INFO("%s: move to exec list %p\n", __func__, obj); | |
3532 | #endif | |
3533 | } | |
3534 | #if WATCH_LRU | |
3535 | i915_dump_lru(dev, __func__); | |
3536 | #endif | |
3537 | ||
3538 | i915_verify_inactive(dev, __FILE__, __LINE__); | |
3539 | ||
673a394b | 3540 | err: |
aad87dff JL |
3541 | for (i = 0; i < pinned; i++) |
3542 | i915_gem_object_unpin(object_list[i]); | |
3543 | ||
b70d11da KH |
3544 | for (i = 0; i < args->buffer_count; i++) { |
3545 | if (object_list[i]) { | |
3546 | obj_priv = object_list[i]->driver_private; | |
3547 | obj_priv->in_execbuffer = false; | |
3548 | } | |
aad87dff | 3549 | drm_gem_object_unreference(object_list[i]); |
b70d11da | 3550 | } |
673a394b | 3551 | |
673a394b EA |
3552 | mutex_unlock(&dev->struct_mutex); |
3553 | ||
a35f2e2b RD |
3554 | if (!ret) { |
3555 | /* Copy the new buffer offsets back to the user's exec list. */ | |
3556 | ret = copy_to_user((struct drm_i915_relocation_entry __user *) | |
3557 | (uintptr_t) args->buffers_ptr, | |
3558 | exec_list, | |
3559 | sizeof(*exec_list) * args->buffer_count); | |
2bc43b5c FM |
3560 | if (ret) { |
3561 | ret = -EFAULT; | |
a35f2e2b RD |
3562 | DRM_ERROR("failed to copy %d exec entries " |
3563 | "back to user (%d)\n", | |
3564 | args->buffer_count, ret); | |
2bc43b5c | 3565 | } |
a35f2e2b RD |
3566 | } |
3567 | ||
40a5f0de EA |
3568 | /* Copy the updated relocations out regardless of current error |
3569 | * state. Failure to update the relocs would mean that the next | |
3570 | * time userland calls execbuf, it would do so with presumed offset | |
3571 | * state that didn't match the actual object state. | |
3572 | */ | |
3573 | ret2 = i915_gem_put_relocs_to_user(exec_list, args->buffer_count, | |
3574 | relocs); | |
3575 | if (ret2 != 0) { | |
3576 | DRM_ERROR("Failed to copy relocations back out: %d\n", ret2); | |
3577 | ||
3578 | if (ret == 0) | |
3579 | ret = ret2; | |
3580 | } | |
3581 | ||
673a394b | 3582 | pre_mutex_err: |
8e7d2b2c JB |
3583 | drm_free_large(object_list); |
3584 | drm_free_large(exec_list); | |
9a298b2a | 3585 | kfree(cliprects); |
673a394b EA |
3586 | |
3587 | return ret; | |
3588 | } | |
3589 | ||
3590 | int | |
3591 | i915_gem_object_pin(struct drm_gem_object *obj, uint32_t alignment) | |
3592 | { | |
3593 | struct drm_device *dev = obj->dev; | |
3594 | struct drm_i915_gem_object *obj_priv = obj->driver_private; | |
3595 | int ret; | |
3596 | ||
3597 | i915_verify_inactive(dev, __FILE__, __LINE__); | |
3598 | if (obj_priv->gtt_space == NULL) { | |
3599 | ret = i915_gem_object_bind_to_gtt(obj, alignment); | |
3600 | if (ret != 0) { | |
9bb2d6f9 | 3601 | if (ret != -EBUSY && ret != -ERESTARTSYS) |
0fce81e3 | 3602 | DRM_ERROR("Failure to bind: %d\n", ret); |
673a394b EA |
3603 | return ret; |
3604 | } | |
22c344e9 CW |
3605 | } |
3606 | /* | |
3607 | * Pre-965 chips need a fence register set up in order to | |
3608 | * properly handle tiled surfaces. | |
3609 | */ | |
a09ba7fa | 3610 | if (!IS_I965G(dev) && obj_priv->tiling_mode != I915_TILING_NONE) { |
8c4b8c3f | 3611 | ret = i915_gem_object_get_fence_reg(obj); |
22c344e9 CW |
3612 | if (ret != 0) { |
3613 | if (ret != -EBUSY && ret != -ERESTARTSYS) | |
3614 | DRM_ERROR("Failure to install fence: %d\n", | |
3615 | ret); | |
3616 | return ret; | |
3617 | } | |
673a394b EA |
3618 | } |
3619 | obj_priv->pin_count++; | |
3620 | ||
3621 | /* If the object is not active and not pending a flush, | |
3622 | * remove it from the inactive list | |
3623 | */ | |
3624 | if (obj_priv->pin_count == 1) { | |
3625 | atomic_inc(&dev->pin_count); | |
3626 | atomic_add(obj->size, &dev->pin_memory); | |
3627 | if (!obj_priv->active && | |
21d509e3 | 3628 | (obj->write_domain & I915_GEM_GPU_DOMAINS) == 0 && |
673a394b EA |
3629 | !list_empty(&obj_priv->list)) |
3630 | list_del_init(&obj_priv->list); | |
3631 | } | |
3632 | i915_verify_inactive(dev, __FILE__, __LINE__); | |
3633 | ||
3634 | return 0; | |
3635 | } | |
3636 | ||
3637 | void | |
3638 | i915_gem_object_unpin(struct drm_gem_object *obj) | |
3639 | { | |
3640 | struct drm_device *dev = obj->dev; | |
3641 | drm_i915_private_t *dev_priv = dev->dev_private; | |
3642 | struct drm_i915_gem_object *obj_priv = obj->driver_private; | |
3643 | ||
3644 | i915_verify_inactive(dev, __FILE__, __LINE__); | |
3645 | obj_priv->pin_count--; | |
3646 | BUG_ON(obj_priv->pin_count < 0); | |
3647 | BUG_ON(obj_priv->gtt_space == NULL); | |
3648 | ||
3649 | /* If the object is no longer pinned, and is | |
3650 | * neither active nor being flushed, then stick it on | |
3651 | * the inactive list | |
3652 | */ | |
3653 | if (obj_priv->pin_count == 0) { | |
3654 | if (!obj_priv->active && | |
21d509e3 | 3655 | (obj->write_domain & I915_GEM_GPU_DOMAINS) == 0) |
673a394b EA |
3656 | list_move_tail(&obj_priv->list, |
3657 | &dev_priv->mm.inactive_list); | |
3658 | atomic_dec(&dev->pin_count); | |
3659 | atomic_sub(obj->size, &dev->pin_memory); | |
3660 | } | |
3661 | i915_verify_inactive(dev, __FILE__, __LINE__); | |
3662 | } | |
3663 | ||
3664 | int | |
3665 | i915_gem_pin_ioctl(struct drm_device *dev, void *data, | |
3666 | struct drm_file *file_priv) | |
3667 | { | |
3668 | struct drm_i915_gem_pin *args = data; | |
3669 | struct drm_gem_object *obj; | |
3670 | struct drm_i915_gem_object *obj_priv; | |
3671 | int ret; | |
3672 | ||
3673 | mutex_lock(&dev->struct_mutex); | |
3674 | ||
3675 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); | |
3676 | if (obj == NULL) { | |
3677 | DRM_ERROR("Bad handle in i915_gem_pin_ioctl(): %d\n", | |
3678 | args->handle); | |
3679 | mutex_unlock(&dev->struct_mutex); | |
3680 | return -EBADF; | |
3681 | } | |
3682 | obj_priv = obj->driver_private; | |
3683 | ||
79e53945 JB |
3684 | if (obj_priv->pin_filp != NULL && obj_priv->pin_filp != file_priv) { |
3685 | DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n", | |
3686 | args->handle); | |
96dec61d | 3687 | drm_gem_object_unreference(obj); |
673a394b | 3688 | mutex_unlock(&dev->struct_mutex); |
79e53945 JB |
3689 | return -EINVAL; |
3690 | } | |
3691 | ||
3692 | obj_priv->user_pin_count++; | |
3693 | obj_priv->pin_filp = file_priv; | |
3694 | if (obj_priv->user_pin_count == 1) { | |
3695 | ret = i915_gem_object_pin(obj, args->alignment); | |
3696 | if (ret != 0) { | |
3697 | drm_gem_object_unreference(obj); | |
3698 | mutex_unlock(&dev->struct_mutex); | |
3699 | return ret; | |
3700 | } | |
673a394b EA |
3701 | } |
3702 | ||
3703 | /* XXX - flush the CPU caches for pinned objects | |
3704 | * as the X server doesn't manage domains yet | |
3705 | */ | |
e47c68e9 | 3706 | i915_gem_object_flush_cpu_write_domain(obj); |
673a394b EA |
3707 | args->offset = obj_priv->gtt_offset; |
3708 | drm_gem_object_unreference(obj); | |
3709 | mutex_unlock(&dev->struct_mutex); | |
3710 | ||
3711 | return 0; | |
3712 | } | |
3713 | ||
3714 | int | |
3715 | i915_gem_unpin_ioctl(struct drm_device *dev, void *data, | |
3716 | struct drm_file *file_priv) | |
3717 | { | |
3718 | struct drm_i915_gem_pin *args = data; | |
3719 | struct drm_gem_object *obj; | |
79e53945 | 3720 | struct drm_i915_gem_object *obj_priv; |
673a394b EA |
3721 | |
3722 | mutex_lock(&dev->struct_mutex); | |
3723 | ||
3724 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); | |
3725 | if (obj == NULL) { | |
3726 | DRM_ERROR("Bad handle in i915_gem_unpin_ioctl(): %d\n", | |
3727 | args->handle); | |
3728 | mutex_unlock(&dev->struct_mutex); | |
3729 | return -EBADF; | |
3730 | } | |
3731 | ||
79e53945 JB |
3732 | obj_priv = obj->driver_private; |
3733 | if (obj_priv->pin_filp != file_priv) { | |
3734 | DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n", | |
3735 | args->handle); | |
3736 | drm_gem_object_unreference(obj); | |
3737 | mutex_unlock(&dev->struct_mutex); | |
3738 | return -EINVAL; | |
3739 | } | |
3740 | obj_priv->user_pin_count--; | |
3741 | if (obj_priv->user_pin_count == 0) { | |
3742 | obj_priv->pin_filp = NULL; | |
3743 | i915_gem_object_unpin(obj); | |
3744 | } | |
673a394b EA |
3745 | |
3746 | drm_gem_object_unreference(obj); | |
3747 | mutex_unlock(&dev->struct_mutex); | |
3748 | return 0; | |
3749 | } | |
3750 | ||
3751 | int | |
3752 | i915_gem_busy_ioctl(struct drm_device *dev, void *data, | |
3753 | struct drm_file *file_priv) | |
3754 | { | |
3755 | struct drm_i915_gem_busy *args = data; | |
3756 | struct drm_gem_object *obj; | |
3757 | struct drm_i915_gem_object *obj_priv; | |
3758 | ||
673a394b EA |
3759 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); |
3760 | if (obj == NULL) { | |
3761 | DRM_ERROR("Bad handle in i915_gem_busy_ioctl(): %d\n", | |
3762 | args->handle); | |
673a394b EA |
3763 | return -EBADF; |
3764 | } | |
3765 | ||
b1ce786c | 3766 | mutex_lock(&dev->struct_mutex); |
f21289b3 EA |
3767 | /* Update the active list for the hardware's current position. |
3768 | * Otherwise this only updates on a delayed timer or when irqs are | |
3769 | * actually unmasked, and our working set ends up being larger than | |
3770 | * required. | |
3771 | */ | |
3772 | i915_gem_retire_requests(dev); | |
3773 | ||
673a394b | 3774 | obj_priv = obj->driver_private; |
c4de0a5d EA |
3775 | /* Don't count being on the flushing list against the object being |
3776 | * done. Otherwise, a buffer left on the flushing list but not getting | |
3777 | * flushed (because nobody's flushing that domain) won't ever return | |
3778 | * unbusy and get reused by libdrm's bo cache. The other expected | |
3779 | * consumer of this interface, OpenGL's occlusion queries, also specs | |
3780 | * that the objects get unbusy "eventually" without any interference. | |
3781 | */ | |
3782 | args->busy = obj_priv->active && obj_priv->last_rendering_seqno != 0; | |
673a394b EA |
3783 | |
3784 | drm_gem_object_unreference(obj); | |
3785 | mutex_unlock(&dev->struct_mutex); | |
3786 | return 0; | |
3787 | } | |
3788 | ||
3789 | int | |
3790 | i915_gem_throttle_ioctl(struct drm_device *dev, void *data, | |
3791 | struct drm_file *file_priv) | |
3792 | { | |
3793 | return i915_gem_ring_throttle(dev, file_priv); | |
3794 | } | |
3795 | ||
3796 | int i915_gem_init_object(struct drm_gem_object *obj) | |
3797 | { | |
3798 | struct drm_i915_gem_object *obj_priv; | |
3799 | ||
9a298b2a | 3800 | obj_priv = kzalloc(sizeof(*obj_priv), GFP_KERNEL); |
673a394b EA |
3801 | if (obj_priv == NULL) |
3802 | return -ENOMEM; | |
3803 | ||
3804 | /* | |
3805 | * We've just allocated pages from the kernel, | |
3806 | * so they've just been written by the CPU with | |
3807 | * zeros. They'll need to be clflushed before we | |
3808 | * use them with the GPU. | |
3809 | */ | |
3810 | obj->write_domain = I915_GEM_DOMAIN_CPU; | |
3811 | obj->read_domains = I915_GEM_DOMAIN_CPU; | |
3812 | ||
ba1eb1d8 KP |
3813 | obj_priv->agp_type = AGP_USER_MEMORY; |
3814 | ||
673a394b EA |
3815 | obj->driver_private = obj_priv; |
3816 | obj_priv->obj = obj; | |
de151cf6 | 3817 | obj_priv->fence_reg = I915_FENCE_REG_NONE; |
673a394b | 3818 | INIT_LIST_HEAD(&obj_priv->list); |
a09ba7fa | 3819 | INIT_LIST_HEAD(&obj_priv->fence_list); |
de151cf6 | 3820 | |
673a394b EA |
3821 | return 0; |
3822 | } | |
3823 | ||
3824 | void i915_gem_free_object(struct drm_gem_object *obj) | |
3825 | { | |
de151cf6 | 3826 | struct drm_device *dev = obj->dev; |
673a394b EA |
3827 | struct drm_i915_gem_object *obj_priv = obj->driver_private; |
3828 | ||
3829 | while (obj_priv->pin_count > 0) | |
3830 | i915_gem_object_unpin(obj); | |
3831 | ||
71acb5eb DA |
3832 | if (obj_priv->phys_obj) |
3833 | i915_gem_detach_phys_object(dev, obj); | |
3834 | ||
673a394b EA |
3835 | i915_gem_object_unbind(obj); |
3836 | ||
ab00b3e5 | 3837 | i915_gem_free_mmap_offset(obj); |
de151cf6 | 3838 | |
9a298b2a | 3839 | kfree(obj_priv->page_cpu_valid); |
280b713b | 3840 | kfree(obj_priv->bit_17); |
9a298b2a | 3841 | kfree(obj->driver_private); |
673a394b EA |
3842 | } |
3843 | ||
673a394b EA |
3844 | /** Unbinds all objects that are on the given buffer list. */ |
3845 | static int | |
3846 | i915_gem_evict_from_list(struct drm_device *dev, struct list_head *head) | |
3847 | { | |
3848 | struct drm_gem_object *obj; | |
3849 | struct drm_i915_gem_object *obj_priv; | |
3850 | int ret; | |
3851 | ||
3852 | while (!list_empty(head)) { | |
3853 | obj_priv = list_first_entry(head, | |
3854 | struct drm_i915_gem_object, | |
3855 | list); | |
3856 | obj = obj_priv->obj; | |
3857 | ||
3858 | if (obj_priv->pin_count != 0) { | |
3859 | DRM_ERROR("Pinned object in unbind list\n"); | |
3860 | mutex_unlock(&dev->struct_mutex); | |
3861 | return -EINVAL; | |
3862 | } | |
3863 | ||
3864 | ret = i915_gem_object_unbind(obj); | |
3865 | if (ret != 0) { | |
3866 | DRM_ERROR("Error unbinding object in LeaveVT: %d\n", | |
3867 | ret); | |
3868 | mutex_unlock(&dev->struct_mutex); | |
3869 | return ret; | |
3870 | } | |
3871 | } | |
3872 | ||
3873 | ||
3874 | return 0; | |
3875 | } | |
3876 | ||
5669fcac | 3877 | int |
673a394b EA |
3878 | i915_gem_idle(struct drm_device *dev) |
3879 | { | |
3880 | drm_i915_private_t *dev_priv = dev->dev_private; | |
3881 | uint32_t seqno, cur_seqno, last_seqno; | |
3882 | int stuck, ret; | |
3883 | ||
6dbe2772 KP |
3884 | mutex_lock(&dev->struct_mutex); |
3885 | ||
3886 | if (dev_priv->mm.suspended || dev_priv->ring.ring_obj == NULL) { | |
3887 | mutex_unlock(&dev->struct_mutex); | |
673a394b | 3888 | return 0; |
6dbe2772 | 3889 | } |
673a394b EA |
3890 | |
3891 | /* Hack! Don't let anybody do execbuf while we don't control the chip. | |
3892 | * We need to replace this with a semaphore, or something. | |
3893 | */ | |
3894 | dev_priv->mm.suspended = 1; | |
3895 | ||
6dbe2772 KP |
3896 | /* Cancel the retire work handler, wait for it to finish if running |
3897 | */ | |
3898 | mutex_unlock(&dev->struct_mutex); | |
3899 | cancel_delayed_work_sync(&dev_priv->mm.retire_work); | |
3900 | mutex_lock(&dev->struct_mutex); | |
3901 | ||
673a394b EA |
3902 | i915_kernel_lost_context(dev); |
3903 | ||
3904 | /* Flush the GPU along with all non-CPU write domains | |
3905 | */ | |
21d509e3 CW |
3906 | i915_gem_flush(dev, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS); |
3907 | seqno = i915_add_request(dev, NULL, I915_GEM_GPU_DOMAINS); | |
673a394b EA |
3908 | |
3909 | if (seqno == 0) { | |
3910 | mutex_unlock(&dev->struct_mutex); | |
3911 | return -ENOMEM; | |
3912 | } | |
3913 | ||
3914 | dev_priv->mm.waiting_gem_seqno = seqno; | |
3915 | last_seqno = 0; | |
3916 | stuck = 0; | |
3917 | for (;;) { | |
3918 | cur_seqno = i915_get_gem_seqno(dev); | |
3919 | if (i915_seqno_passed(cur_seqno, seqno)) | |
3920 | break; | |
3921 | if (last_seqno == cur_seqno) { | |
3922 | if (stuck++ > 100) { | |
3923 | DRM_ERROR("hardware wedged\n"); | |
3924 | dev_priv->mm.wedged = 1; | |
3925 | DRM_WAKEUP(&dev_priv->irq_queue); | |
3926 | break; | |
3927 | } | |
3928 | } | |
3929 | msleep(10); | |
3930 | last_seqno = cur_seqno; | |
3931 | } | |
3932 | dev_priv->mm.waiting_gem_seqno = 0; | |
3933 | ||
3934 | i915_gem_retire_requests(dev); | |
3935 | ||
5e118f41 | 3936 | spin_lock(&dev_priv->mm.active_list_lock); |
28dfe52a EA |
3937 | if (!dev_priv->mm.wedged) { |
3938 | /* Active and flushing should now be empty as we've | |
3939 | * waited for a sequence higher than any pending execbuffer | |
3940 | */ | |
3941 | WARN_ON(!list_empty(&dev_priv->mm.active_list)); | |
3942 | WARN_ON(!list_empty(&dev_priv->mm.flushing_list)); | |
3943 | /* Request should now be empty as we've also waited | |
3944 | * for the last request in the list | |
3945 | */ | |
3946 | WARN_ON(!list_empty(&dev_priv->mm.request_list)); | |
3947 | } | |
673a394b | 3948 | |
28dfe52a EA |
3949 | /* Empty the active and flushing lists to inactive. If there's |
3950 | * anything left at this point, it means that we're wedged and | |
3951 | * nothing good's going to happen by leaving them there. So strip | |
3952 | * the GPU domains and just stuff them onto inactive. | |
673a394b | 3953 | */ |
28dfe52a EA |
3954 | while (!list_empty(&dev_priv->mm.active_list)) { |
3955 | struct drm_i915_gem_object *obj_priv; | |
673a394b | 3956 | |
28dfe52a EA |
3957 | obj_priv = list_first_entry(&dev_priv->mm.active_list, |
3958 | struct drm_i915_gem_object, | |
3959 | list); | |
3960 | obj_priv->obj->write_domain &= ~I915_GEM_GPU_DOMAINS; | |
3961 | i915_gem_object_move_to_inactive(obj_priv->obj); | |
3962 | } | |
5e118f41 | 3963 | spin_unlock(&dev_priv->mm.active_list_lock); |
28dfe52a EA |
3964 | |
3965 | while (!list_empty(&dev_priv->mm.flushing_list)) { | |
3966 | struct drm_i915_gem_object *obj_priv; | |
3967 | ||
151903d5 | 3968 | obj_priv = list_first_entry(&dev_priv->mm.flushing_list, |
28dfe52a EA |
3969 | struct drm_i915_gem_object, |
3970 | list); | |
3971 | obj_priv->obj->write_domain &= ~I915_GEM_GPU_DOMAINS; | |
3972 | i915_gem_object_move_to_inactive(obj_priv->obj); | |
3973 | } | |
3974 | ||
3975 | ||
3976 | /* Move all inactive buffers out of the GTT. */ | |
673a394b | 3977 | ret = i915_gem_evict_from_list(dev, &dev_priv->mm.inactive_list); |
28dfe52a | 3978 | WARN_ON(!list_empty(&dev_priv->mm.inactive_list)); |
6dbe2772 KP |
3979 | if (ret) { |
3980 | mutex_unlock(&dev->struct_mutex); | |
673a394b | 3981 | return ret; |
6dbe2772 | 3982 | } |
673a394b | 3983 | |
6dbe2772 KP |
3984 | i915_gem_cleanup_ringbuffer(dev); |
3985 | mutex_unlock(&dev->struct_mutex); | |
3986 | ||
673a394b EA |
3987 | return 0; |
3988 | } | |
3989 | ||
3990 | static int | |
3991 | i915_gem_init_hws(struct drm_device *dev) | |
3992 | { | |
3993 | drm_i915_private_t *dev_priv = dev->dev_private; | |
3994 | struct drm_gem_object *obj; | |
3995 | struct drm_i915_gem_object *obj_priv; | |
3996 | int ret; | |
3997 | ||
3998 | /* If we need a physical address for the status page, it's already | |
3999 | * initialized at driver load time. | |
4000 | */ | |
4001 | if (!I915_NEED_GFX_HWS(dev)) | |
4002 | return 0; | |
4003 | ||
4004 | obj = drm_gem_object_alloc(dev, 4096); | |
4005 | if (obj == NULL) { | |
4006 | DRM_ERROR("Failed to allocate status page\n"); | |
4007 | return -ENOMEM; | |
4008 | } | |
4009 | obj_priv = obj->driver_private; | |
ba1eb1d8 | 4010 | obj_priv->agp_type = AGP_USER_CACHED_MEMORY; |
673a394b EA |
4011 | |
4012 | ret = i915_gem_object_pin(obj, 4096); | |
4013 | if (ret != 0) { | |
4014 | drm_gem_object_unreference(obj); | |
4015 | return ret; | |
4016 | } | |
4017 | ||
4018 | dev_priv->status_gfx_addr = obj_priv->gtt_offset; | |
673a394b | 4019 | |
856fa198 | 4020 | dev_priv->hw_status_page = kmap(obj_priv->pages[0]); |
ba1eb1d8 | 4021 | if (dev_priv->hw_status_page == NULL) { |
673a394b EA |
4022 | DRM_ERROR("Failed to map status page.\n"); |
4023 | memset(&dev_priv->hws_map, 0, sizeof(dev_priv->hws_map)); | |
3eb2ee77 | 4024 | i915_gem_object_unpin(obj); |
673a394b EA |
4025 | drm_gem_object_unreference(obj); |
4026 | return -EINVAL; | |
4027 | } | |
4028 | dev_priv->hws_obj = obj; | |
673a394b EA |
4029 | memset(dev_priv->hw_status_page, 0, PAGE_SIZE); |
4030 | I915_WRITE(HWS_PGA, dev_priv->status_gfx_addr); | |
ba1eb1d8 | 4031 | I915_READ(HWS_PGA); /* posting read */ |
673a394b EA |
4032 | DRM_DEBUG("hws offset: 0x%08x\n", dev_priv->status_gfx_addr); |
4033 | ||
4034 | return 0; | |
4035 | } | |
4036 | ||
85a7bb98 CW |
4037 | static void |
4038 | i915_gem_cleanup_hws(struct drm_device *dev) | |
4039 | { | |
4040 | drm_i915_private_t *dev_priv = dev->dev_private; | |
bab2d1f6 CW |
4041 | struct drm_gem_object *obj; |
4042 | struct drm_i915_gem_object *obj_priv; | |
85a7bb98 CW |
4043 | |
4044 | if (dev_priv->hws_obj == NULL) | |
4045 | return; | |
4046 | ||
bab2d1f6 CW |
4047 | obj = dev_priv->hws_obj; |
4048 | obj_priv = obj->driver_private; | |
4049 | ||
856fa198 | 4050 | kunmap(obj_priv->pages[0]); |
85a7bb98 CW |
4051 | i915_gem_object_unpin(obj); |
4052 | drm_gem_object_unreference(obj); | |
4053 | dev_priv->hws_obj = NULL; | |
bab2d1f6 | 4054 | |
85a7bb98 CW |
4055 | memset(&dev_priv->hws_map, 0, sizeof(dev_priv->hws_map)); |
4056 | dev_priv->hw_status_page = NULL; | |
4057 | ||
4058 | /* Write high address into HWS_PGA when disabling. */ | |
4059 | I915_WRITE(HWS_PGA, 0x1ffff000); | |
4060 | } | |
4061 | ||
79e53945 | 4062 | int |
673a394b EA |
4063 | i915_gem_init_ringbuffer(struct drm_device *dev) |
4064 | { | |
4065 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4066 | struct drm_gem_object *obj; | |
4067 | struct drm_i915_gem_object *obj_priv; | |
79e53945 | 4068 | drm_i915_ring_buffer_t *ring = &dev_priv->ring; |
673a394b | 4069 | int ret; |
50aa253d | 4070 | u32 head; |
673a394b EA |
4071 | |
4072 | ret = i915_gem_init_hws(dev); | |
4073 | if (ret != 0) | |
4074 | return ret; | |
4075 | ||
4076 | obj = drm_gem_object_alloc(dev, 128 * 1024); | |
4077 | if (obj == NULL) { | |
4078 | DRM_ERROR("Failed to allocate ringbuffer\n"); | |
85a7bb98 | 4079 | i915_gem_cleanup_hws(dev); |
673a394b EA |
4080 | return -ENOMEM; |
4081 | } | |
4082 | obj_priv = obj->driver_private; | |
4083 | ||
4084 | ret = i915_gem_object_pin(obj, 4096); | |
4085 | if (ret != 0) { | |
4086 | drm_gem_object_unreference(obj); | |
85a7bb98 | 4087 | i915_gem_cleanup_hws(dev); |
673a394b EA |
4088 | return ret; |
4089 | } | |
4090 | ||
4091 | /* Set up the kernel mapping for the ring. */ | |
79e53945 | 4092 | ring->Size = obj->size; |
673a394b | 4093 | |
79e53945 JB |
4094 | ring->map.offset = dev->agp->base + obj_priv->gtt_offset; |
4095 | ring->map.size = obj->size; | |
4096 | ring->map.type = 0; | |
4097 | ring->map.flags = 0; | |
4098 | ring->map.mtrr = 0; | |
673a394b | 4099 | |
79e53945 JB |
4100 | drm_core_ioremap_wc(&ring->map, dev); |
4101 | if (ring->map.handle == NULL) { | |
673a394b EA |
4102 | DRM_ERROR("Failed to map ringbuffer.\n"); |
4103 | memset(&dev_priv->ring, 0, sizeof(dev_priv->ring)); | |
47ed185a | 4104 | i915_gem_object_unpin(obj); |
673a394b | 4105 | drm_gem_object_unreference(obj); |
85a7bb98 | 4106 | i915_gem_cleanup_hws(dev); |
673a394b EA |
4107 | return -EINVAL; |
4108 | } | |
79e53945 JB |
4109 | ring->ring_obj = obj; |
4110 | ring->virtual_start = ring->map.handle; | |
673a394b EA |
4111 | |
4112 | /* Stop the ring if it's running. */ | |
4113 | I915_WRITE(PRB0_CTL, 0); | |
673a394b | 4114 | I915_WRITE(PRB0_TAIL, 0); |
50aa253d | 4115 | I915_WRITE(PRB0_HEAD, 0); |
673a394b EA |
4116 | |
4117 | /* Initialize the ring. */ | |
4118 | I915_WRITE(PRB0_START, obj_priv->gtt_offset); | |
50aa253d KP |
4119 | head = I915_READ(PRB0_HEAD) & HEAD_ADDR; |
4120 | ||
4121 | /* G45 ring initialization fails to reset head to zero */ | |
4122 | if (head != 0) { | |
4123 | DRM_ERROR("Ring head not reset to zero " | |
4124 | "ctl %08x head %08x tail %08x start %08x\n", | |
4125 | I915_READ(PRB0_CTL), | |
4126 | I915_READ(PRB0_HEAD), | |
4127 | I915_READ(PRB0_TAIL), | |
4128 | I915_READ(PRB0_START)); | |
4129 | I915_WRITE(PRB0_HEAD, 0); | |
4130 | ||
4131 | DRM_ERROR("Ring head forced to zero " | |
4132 | "ctl %08x head %08x tail %08x start %08x\n", | |
4133 | I915_READ(PRB0_CTL), | |
4134 | I915_READ(PRB0_HEAD), | |
4135 | I915_READ(PRB0_TAIL), | |
4136 | I915_READ(PRB0_START)); | |
4137 | } | |
4138 | ||
673a394b EA |
4139 | I915_WRITE(PRB0_CTL, |
4140 | ((obj->size - 4096) & RING_NR_PAGES) | | |
4141 | RING_NO_REPORT | | |
4142 | RING_VALID); | |
4143 | ||
50aa253d KP |
4144 | head = I915_READ(PRB0_HEAD) & HEAD_ADDR; |
4145 | ||
4146 | /* If the head is still not zero, the ring is dead */ | |
4147 | if (head != 0) { | |
4148 | DRM_ERROR("Ring initialization failed " | |
4149 | "ctl %08x head %08x tail %08x start %08x\n", | |
4150 | I915_READ(PRB0_CTL), | |
4151 | I915_READ(PRB0_HEAD), | |
4152 | I915_READ(PRB0_TAIL), | |
4153 | I915_READ(PRB0_START)); | |
4154 | return -EIO; | |
4155 | } | |
4156 | ||
673a394b | 4157 | /* Update our cache of the ring state */ |
79e53945 JB |
4158 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) |
4159 | i915_kernel_lost_context(dev); | |
4160 | else { | |
4161 | ring->head = I915_READ(PRB0_HEAD) & HEAD_ADDR; | |
4162 | ring->tail = I915_READ(PRB0_TAIL) & TAIL_ADDR; | |
4163 | ring->space = ring->head - (ring->tail + 8); | |
4164 | if (ring->space < 0) | |
4165 | ring->space += ring->Size; | |
4166 | } | |
673a394b EA |
4167 | |
4168 | return 0; | |
4169 | } | |
4170 | ||
79e53945 | 4171 | void |
673a394b EA |
4172 | i915_gem_cleanup_ringbuffer(struct drm_device *dev) |
4173 | { | |
4174 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4175 | ||
4176 | if (dev_priv->ring.ring_obj == NULL) | |
4177 | return; | |
4178 | ||
4179 | drm_core_ioremapfree(&dev_priv->ring.map, dev); | |
4180 | ||
4181 | i915_gem_object_unpin(dev_priv->ring.ring_obj); | |
4182 | drm_gem_object_unreference(dev_priv->ring.ring_obj); | |
4183 | dev_priv->ring.ring_obj = NULL; | |
4184 | memset(&dev_priv->ring, 0, sizeof(dev_priv->ring)); | |
4185 | ||
85a7bb98 | 4186 | i915_gem_cleanup_hws(dev); |
673a394b EA |
4187 | } |
4188 | ||
4189 | int | |
4190 | i915_gem_entervt_ioctl(struct drm_device *dev, void *data, | |
4191 | struct drm_file *file_priv) | |
4192 | { | |
4193 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4194 | int ret; | |
4195 | ||
79e53945 JB |
4196 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
4197 | return 0; | |
4198 | ||
673a394b EA |
4199 | if (dev_priv->mm.wedged) { |
4200 | DRM_ERROR("Reenabling wedged hardware, good luck\n"); | |
4201 | dev_priv->mm.wedged = 0; | |
4202 | } | |
4203 | ||
673a394b | 4204 | mutex_lock(&dev->struct_mutex); |
9bb2d6f9 EA |
4205 | dev_priv->mm.suspended = 0; |
4206 | ||
4207 | ret = i915_gem_init_ringbuffer(dev); | |
d816f6ac WF |
4208 | if (ret != 0) { |
4209 | mutex_unlock(&dev->struct_mutex); | |
9bb2d6f9 | 4210 | return ret; |
d816f6ac | 4211 | } |
9bb2d6f9 | 4212 | |
5e118f41 | 4213 | spin_lock(&dev_priv->mm.active_list_lock); |
673a394b | 4214 | BUG_ON(!list_empty(&dev_priv->mm.active_list)); |
5e118f41 CW |
4215 | spin_unlock(&dev_priv->mm.active_list_lock); |
4216 | ||
673a394b EA |
4217 | BUG_ON(!list_empty(&dev_priv->mm.flushing_list)); |
4218 | BUG_ON(!list_empty(&dev_priv->mm.inactive_list)); | |
4219 | BUG_ON(!list_empty(&dev_priv->mm.request_list)); | |
673a394b | 4220 | mutex_unlock(&dev->struct_mutex); |
dbb19d30 KH |
4221 | |
4222 | drm_irq_install(dev); | |
4223 | ||
673a394b EA |
4224 | return 0; |
4225 | } | |
4226 | ||
4227 | int | |
4228 | i915_gem_leavevt_ioctl(struct drm_device *dev, void *data, | |
4229 | struct drm_file *file_priv) | |
4230 | { | |
4231 | int ret; | |
4232 | ||
79e53945 JB |
4233 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
4234 | return 0; | |
4235 | ||
673a394b | 4236 | ret = i915_gem_idle(dev); |
dbb19d30 KH |
4237 | drm_irq_uninstall(dev); |
4238 | ||
6dbe2772 | 4239 | return ret; |
673a394b EA |
4240 | } |
4241 | ||
4242 | void | |
4243 | i915_gem_lastclose(struct drm_device *dev) | |
4244 | { | |
4245 | int ret; | |
673a394b | 4246 | |
e806b495 EA |
4247 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
4248 | return; | |
4249 | ||
6dbe2772 KP |
4250 | ret = i915_gem_idle(dev); |
4251 | if (ret) | |
4252 | DRM_ERROR("failed to idle hardware: %d\n", ret); | |
673a394b EA |
4253 | } |
4254 | ||
4255 | void | |
4256 | i915_gem_load(struct drm_device *dev) | |
4257 | { | |
b5aa8a0f | 4258 | int i; |
673a394b EA |
4259 | drm_i915_private_t *dev_priv = dev->dev_private; |
4260 | ||
5e118f41 | 4261 | spin_lock_init(&dev_priv->mm.active_list_lock); |
673a394b EA |
4262 | INIT_LIST_HEAD(&dev_priv->mm.active_list); |
4263 | INIT_LIST_HEAD(&dev_priv->mm.flushing_list); | |
4264 | INIT_LIST_HEAD(&dev_priv->mm.inactive_list); | |
4265 | INIT_LIST_HEAD(&dev_priv->mm.request_list); | |
a09ba7fa | 4266 | INIT_LIST_HEAD(&dev_priv->mm.fence_list); |
673a394b EA |
4267 | INIT_DELAYED_WORK(&dev_priv->mm.retire_work, |
4268 | i915_gem_retire_work_handler); | |
4269 | dev_priv->mm.next_gem_seqno = 1; | |
4270 | ||
de151cf6 JB |
4271 | /* Old X drivers will take 0-2 for front, back, depth buffers */ |
4272 | dev_priv->fence_reg_start = 3; | |
4273 | ||
0f973f27 | 4274 | if (IS_I965G(dev) || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) |
de151cf6 JB |
4275 | dev_priv->num_fence_regs = 16; |
4276 | else | |
4277 | dev_priv->num_fence_regs = 8; | |
4278 | ||
b5aa8a0f GH |
4279 | /* Initialize fence registers to zero */ |
4280 | if (IS_I965G(dev)) { | |
4281 | for (i = 0; i < 16; i++) | |
4282 | I915_WRITE64(FENCE_REG_965_0 + (i * 8), 0); | |
4283 | } else { | |
4284 | for (i = 0; i < 8; i++) | |
4285 | I915_WRITE(FENCE_REG_830_0 + (i * 4), 0); | |
4286 | if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) | |
4287 | for (i = 0; i < 8; i++) | |
4288 | I915_WRITE(FENCE_REG_945_8 + (i * 4), 0); | |
4289 | } | |
4290 | ||
673a394b EA |
4291 | i915_gem_detect_bit_6_swizzle(dev); |
4292 | } | |
71acb5eb DA |
4293 | |
4294 | /* | |
4295 | * Create a physically contiguous memory object for this object | |
4296 | * e.g. for cursor + overlay regs | |
4297 | */ | |
4298 | int i915_gem_init_phys_object(struct drm_device *dev, | |
4299 | int id, int size) | |
4300 | { | |
4301 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4302 | struct drm_i915_gem_phys_object *phys_obj; | |
4303 | int ret; | |
4304 | ||
4305 | if (dev_priv->mm.phys_objs[id - 1] || !size) | |
4306 | return 0; | |
4307 | ||
9a298b2a | 4308 | phys_obj = kzalloc(sizeof(struct drm_i915_gem_phys_object), GFP_KERNEL); |
71acb5eb DA |
4309 | if (!phys_obj) |
4310 | return -ENOMEM; | |
4311 | ||
4312 | phys_obj->id = id; | |
4313 | ||
4314 | phys_obj->handle = drm_pci_alloc(dev, size, 0, 0xffffffff); | |
4315 | if (!phys_obj->handle) { | |
4316 | ret = -ENOMEM; | |
4317 | goto kfree_obj; | |
4318 | } | |
4319 | #ifdef CONFIG_X86 | |
4320 | set_memory_wc((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE); | |
4321 | #endif | |
4322 | ||
4323 | dev_priv->mm.phys_objs[id - 1] = phys_obj; | |
4324 | ||
4325 | return 0; | |
4326 | kfree_obj: | |
9a298b2a | 4327 | kfree(phys_obj); |
71acb5eb DA |
4328 | return ret; |
4329 | } | |
4330 | ||
4331 | void i915_gem_free_phys_object(struct drm_device *dev, int id) | |
4332 | { | |
4333 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4334 | struct drm_i915_gem_phys_object *phys_obj; | |
4335 | ||
4336 | if (!dev_priv->mm.phys_objs[id - 1]) | |
4337 | return; | |
4338 | ||
4339 | phys_obj = dev_priv->mm.phys_objs[id - 1]; | |
4340 | if (phys_obj->cur_obj) { | |
4341 | i915_gem_detach_phys_object(dev, phys_obj->cur_obj); | |
4342 | } | |
4343 | ||
4344 | #ifdef CONFIG_X86 | |
4345 | set_memory_wb((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE); | |
4346 | #endif | |
4347 | drm_pci_free(dev, phys_obj->handle); | |
4348 | kfree(phys_obj); | |
4349 | dev_priv->mm.phys_objs[id - 1] = NULL; | |
4350 | } | |
4351 | ||
4352 | void i915_gem_free_all_phys_object(struct drm_device *dev) | |
4353 | { | |
4354 | int i; | |
4355 | ||
260883c8 | 4356 | for (i = I915_GEM_PHYS_CURSOR_0; i <= I915_MAX_PHYS_OBJECT; i++) |
71acb5eb DA |
4357 | i915_gem_free_phys_object(dev, i); |
4358 | } | |
4359 | ||
4360 | void i915_gem_detach_phys_object(struct drm_device *dev, | |
4361 | struct drm_gem_object *obj) | |
4362 | { | |
4363 | struct drm_i915_gem_object *obj_priv; | |
4364 | int i; | |
4365 | int ret; | |
4366 | int page_count; | |
4367 | ||
4368 | obj_priv = obj->driver_private; | |
4369 | if (!obj_priv->phys_obj) | |
4370 | return; | |
4371 | ||
856fa198 | 4372 | ret = i915_gem_object_get_pages(obj); |
71acb5eb DA |
4373 | if (ret) |
4374 | goto out; | |
4375 | ||
4376 | page_count = obj->size / PAGE_SIZE; | |
4377 | ||
4378 | for (i = 0; i < page_count; i++) { | |
856fa198 | 4379 | char *dst = kmap_atomic(obj_priv->pages[i], KM_USER0); |
71acb5eb DA |
4380 | char *src = obj_priv->phys_obj->handle->vaddr + (i * PAGE_SIZE); |
4381 | ||
4382 | memcpy(dst, src, PAGE_SIZE); | |
4383 | kunmap_atomic(dst, KM_USER0); | |
4384 | } | |
856fa198 | 4385 | drm_clflush_pages(obj_priv->pages, page_count); |
71acb5eb | 4386 | drm_agp_chipset_flush(dev); |
d78b47b9 CW |
4387 | |
4388 | i915_gem_object_put_pages(obj); | |
71acb5eb DA |
4389 | out: |
4390 | obj_priv->phys_obj->cur_obj = NULL; | |
4391 | obj_priv->phys_obj = NULL; | |
4392 | } | |
4393 | ||
4394 | int | |
4395 | i915_gem_attach_phys_object(struct drm_device *dev, | |
4396 | struct drm_gem_object *obj, int id) | |
4397 | { | |
4398 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4399 | struct drm_i915_gem_object *obj_priv; | |
4400 | int ret = 0; | |
4401 | int page_count; | |
4402 | int i; | |
4403 | ||
4404 | if (id > I915_MAX_PHYS_OBJECT) | |
4405 | return -EINVAL; | |
4406 | ||
4407 | obj_priv = obj->driver_private; | |
4408 | ||
4409 | if (obj_priv->phys_obj) { | |
4410 | if (obj_priv->phys_obj->id == id) | |
4411 | return 0; | |
4412 | i915_gem_detach_phys_object(dev, obj); | |
4413 | } | |
4414 | ||
4415 | ||
4416 | /* create a new object */ | |
4417 | if (!dev_priv->mm.phys_objs[id - 1]) { | |
4418 | ret = i915_gem_init_phys_object(dev, id, | |
4419 | obj->size); | |
4420 | if (ret) { | |
aeb565df | 4421 | DRM_ERROR("failed to init phys object %d size: %zu\n", id, obj->size); |
71acb5eb DA |
4422 | goto out; |
4423 | } | |
4424 | } | |
4425 | ||
4426 | /* bind to the object */ | |
4427 | obj_priv->phys_obj = dev_priv->mm.phys_objs[id - 1]; | |
4428 | obj_priv->phys_obj->cur_obj = obj; | |
4429 | ||
856fa198 | 4430 | ret = i915_gem_object_get_pages(obj); |
71acb5eb DA |
4431 | if (ret) { |
4432 | DRM_ERROR("failed to get page list\n"); | |
4433 | goto out; | |
4434 | } | |
4435 | ||
4436 | page_count = obj->size / PAGE_SIZE; | |
4437 | ||
4438 | for (i = 0; i < page_count; i++) { | |
856fa198 | 4439 | char *src = kmap_atomic(obj_priv->pages[i], KM_USER0); |
71acb5eb DA |
4440 | char *dst = obj_priv->phys_obj->handle->vaddr + (i * PAGE_SIZE); |
4441 | ||
4442 | memcpy(dst, src, PAGE_SIZE); | |
4443 | kunmap_atomic(src, KM_USER0); | |
4444 | } | |
4445 | ||
d78b47b9 CW |
4446 | i915_gem_object_put_pages(obj); |
4447 | ||
71acb5eb DA |
4448 | return 0; |
4449 | out: | |
4450 | return ret; | |
4451 | } | |
4452 | ||
4453 | static int | |
4454 | i915_gem_phys_pwrite(struct drm_device *dev, struct drm_gem_object *obj, | |
4455 | struct drm_i915_gem_pwrite *args, | |
4456 | struct drm_file *file_priv) | |
4457 | { | |
4458 | struct drm_i915_gem_object *obj_priv = obj->driver_private; | |
4459 | void *obj_addr; | |
4460 | int ret; | |
4461 | char __user *user_data; | |
4462 | ||
4463 | user_data = (char __user *) (uintptr_t) args->data_ptr; | |
4464 | obj_addr = obj_priv->phys_obj->handle->vaddr + args->offset; | |
4465 | ||
e08fb4f6 | 4466 | DRM_DEBUG("obj_addr %p, %lld\n", obj_addr, args->size); |
71acb5eb DA |
4467 | ret = copy_from_user(obj_addr, user_data, args->size); |
4468 | if (ret) | |
4469 | return -EFAULT; | |
4470 | ||
4471 | drm_agp_chipset_flush(dev); | |
4472 | return 0; | |
4473 | } | |
b962442e EA |
4474 | |
4475 | void i915_gem_release(struct drm_device * dev, struct drm_file *file_priv) | |
4476 | { | |
4477 | struct drm_i915_file_private *i915_file_priv = file_priv->driver_priv; | |
4478 | ||
4479 | /* Clean up our request list when the client is going away, so that | |
4480 | * later retire_requests won't dereference our soon-to-be-gone | |
4481 | * file_priv. | |
4482 | */ | |
4483 | mutex_lock(&dev->struct_mutex); | |
4484 | while (!list_empty(&i915_file_priv->mm.request_list)) | |
4485 | list_del_init(i915_file_priv->mm.request_list.next); | |
4486 | mutex_unlock(&dev->struct_mutex); | |
4487 | } |