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Commit | Line | Data |
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673a394b EA |
1 | /* |
2 | * Copyright © 2008 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | * | |
26 | */ | |
27 | ||
760285e7 DH |
28 | #include <drm/drmP.h> |
29 | #include <drm/i915_drm.h> | |
673a394b | 30 | #include "i915_drv.h" |
1c5d22f7 | 31 | #include "i915_trace.h" |
652c393a | 32 | #include "intel_drv.h" |
5949eac4 | 33 | #include <linux/shmem_fs.h> |
5a0e3ad6 | 34 | #include <linux/slab.h> |
673a394b | 35 | #include <linux/swap.h> |
79e53945 | 36 | #include <linux/pci.h> |
1286ff73 | 37 | #include <linux/dma-buf.h> |
673a394b | 38 | |
05394f39 | 39 | static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj); |
2c22569b CW |
40 | static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj, |
41 | bool force); | |
07fe0b12 BW |
42 | static __must_check int |
43 | i915_gem_object_bind_to_vm(struct drm_i915_gem_object *obj, | |
44 | struct i915_address_space *vm, | |
45 | unsigned alignment, | |
46 | bool map_and_fenceable, | |
47 | bool nonblocking); | |
05394f39 CW |
48 | static int i915_gem_phys_pwrite(struct drm_device *dev, |
49 | struct drm_i915_gem_object *obj, | |
71acb5eb | 50 | struct drm_i915_gem_pwrite *args, |
05394f39 | 51 | struct drm_file *file); |
673a394b | 52 | |
61050808 CW |
53 | static void i915_gem_write_fence(struct drm_device *dev, int reg, |
54 | struct drm_i915_gem_object *obj); | |
55 | static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj, | |
56 | struct drm_i915_fence_reg *fence, | |
57 | bool enable); | |
58 | ||
17250b71 | 59 | static int i915_gem_inactive_shrink(struct shrinker *shrinker, |
1495f230 | 60 | struct shrink_control *sc); |
6c085a72 CW |
61 | static long i915_gem_purge(struct drm_i915_private *dev_priv, long target); |
62 | static void i915_gem_shrink_all(struct drm_i915_private *dev_priv); | |
8c59967c | 63 | static void i915_gem_object_truncate(struct drm_i915_gem_object *obj); |
31169714 | 64 | |
c76ce038 CW |
65 | static bool cpu_cache_is_coherent(struct drm_device *dev, |
66 | enum i915_cache_level level) | |
67 | { | |
68 | return HAS_LLC(dev) || level != I915_CACHE_NONE; | |
69 | } | |
70 | ||
2c22569b CW |
71 | static bool cpu_write_needs_clflush(struct drm_i915_gem_object *obj) |
72 | { | |
73 | if (!cpu_cache_is_coherent(obj->base.dev, obj->cache_level)) | |
74 | return true; | |
75 | ||
76 | return obj->pin_display; | |
77 | } | |
78 | ||
61050808 CW |
79 | static inline void i915_gem_object_fence_lost(struct drm_i915_gem_object *obj) |
80 | { | |
81 | if (obj->tiling_mode) | |
82 | i915_gem_release_mmap(obj); | |
83 | ||
84 | /* As we do not have an associated fence register, we will force | |
85 | * a tiling change if we ever need to acquire one. | |
86 | */ | |
5d82e3e6 | 87 | obj->fence_dirty = false; |
61050808 CW |
88 | obj->fence_reg = I915_FENCE_REG_NONE; |
89 | } | |
90 | ||
73aa808f CW |
91 | /* some bookkeeping */ |
92 | static void i915_gem_info_add_obj(struct drm_i915_private *dev_priv, | |
93 | size_t size) | |
94 | { | |
c20e8355 | 95 | spin_lock(&dev_priv->mm.object_stat_lock); |
73aa808f CW |
96 | dev_priv->mm.object_count++; |
97 | dev_priv->mm.object_memory += size; | |
c20e8355 | 98 | spin_unlock(&dev_priv->mm.object_stat_lock); |
73aa808f CW |
99 | } |
100 | ||
101 | static void i915_gem_info_remove_obj(struct drm_i915_private *dev_priv, | |
102 | size_t size) | |
103 | { | |
c20e8355 | 104 | spin_lock(&dev_priv->mm.object_stat_lock); |
73aa808f CW |
105 | dev_priv->mm.object_count--; |
106 | dev_priv->mm.object_memory -= size; | |
c20e8355 | 107 | spin_unlock(&dev_priv->mm.object_stat_lock); |
73aa808f CW |
108 | } |
109 | ||
21dd3734 | 110 | static int |
33196ded | 111 | i915_gem_wait_for_error(struct i915_gpu_error *error) |
30dbf0c0 | 112 | { |
30dbf0c0 CW |
113 | int ret; |
114 | ||
7abb690a DV |
115 | #define EXIT_COND (!i915_reset_in_progress(error) || \ |
116 | i915_terminally_wedged(error)) | |
1f83fee0 | 117 | if (EXIT_COND) |
30dbf0c0 CW |
118 | return 0; |
119 | ||
0a6759c6 DV |
120 | /* |
121 | * Only wait 10 seconds for the gpu reset to complete to avoid hanging | |
122 | * userspace. If it takes that long something really bad is going on and | |
123 | * we should simply try to bail out and fail as gracefully as possible. | |
124 | */ | |
1f83fee0 DV |
125 | ret = wait_event_interruptible_timeout(error->reset_queue, |
126 | EXIT_COND, | |
127 | 10*HZ); | |
0a6759c6 DV |
128 | if (ret == 0) { |
129 | DRM_ERROR("Timed out waiting for the gpu reset to complete\n"); | |
130 | return -EIO; | |
131 | } else if (ret < 0) { | |
30dbf0c0 | 132 | return ret; |
0a6759c6 | 133 | } |
1f83fee0 | 134 | #undef EXIT_COND |
30dbf0c0 | 135 | |
21dd3734 | 136 | return 0; |
30dbf0c0 CW |
137 | } |
138 | ||
54cf91dc | 139 | int i915_mutex_lock_interruptible(struct drm_device *dev) |
76c1dec1 | 140 | { |
33196ded | 141 | struct drm_i915_private *dev_priv = dev->dev_private; |
76c1dec1 CW |
142 | int ret; |
143 | ||
33196ded | 144 | ret = i915_gem_wait_for_error(&dev_priv->gpu_error); |
76c1dec1 CW |
145 | if (ret) |
146 | return ret; | |
147 | ||
148 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
149 | if (ret) | |
150 | return ret; | |
151 | ||
23bc5982 | 152 | WARN_ON(i915_verify_lists(dev)); |
76c1dec1 CW |
153 | return 0; |
154 | } | |
30dbf0c0 | 155 | |
7d1c4804 | 156 | static inline bool |
05394f39 | 157 | i915_gem_object_is_inactive(struct drm_i915_gem_object *obj) |
7d1c4804 | 158 | { |
9843877d | 159 | return i915_gem_obj_bound_any(obj) && !obj->active; |
7d1c4804 CW |
160 | } |
161 | ||
79e53945 JB |
162 | int |
163 | i915_gem_init_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 164 | struct drm_file *file) |
79e53945 | 165 | { |
93d18799 | 166 | struct drm_i915_private *dev_priv = dev->dev_private; |
79e53945 | 167 | struct drm_i915_gem_init *args = data; |
2021746e | 168 | |
7bb6fb8d DV |
169 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
170 | return -ENODEV; | |
171 | ||
2021746e CW |
172 | if (args->gtt_start >= args->gtt_end || |
173 | (args->gtt_end | args->gtt_start) & (PAGE_SIZE - 1)) | |
174 | return -EINVAL; | |
79e53945 | 175 | |
f534bc0b DV |
176 | /* GEM with user mode setting was never supported on ilk and later. */ |
177 | if (INTEL_INFO(dev)->gen >= 5) | |
178 | return -ENODEV; | |
179 | ||
79e53945 | 180 | mutex_lock(&dev->struct_mutex); |
d7e5008f BW |
181 | i915_gem_setup_global_gtt(dev, args->gtt_start, args->gtt_end, |
182 | args->gtt_end); | |
93d18799 | 183 | dev_priv->gtt.mappable_end = args->gtt_end; |
673a394b EA |
184 | mutex_unlock(&dev->struct_mutex); |
185 | ||
2021746e | 186 | return 0; |
673a394b EA |
187 | } |
188 | ||
5a125c3c EA |
189 | int |
190 | i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 191 | struct drm_file *file) |
5a125c3c | 192 | { |
73aa808f | 193 | struct drm_i915_private *dev_priv = dev->dev_private; |
5a125c3c | 194 | struct drm_i915_gem_get_aperture *args = data; |
6299f992 CW |
195 | struct drm_i915_gem_object *obj; |
196 | size_t pinned; | |
5a125c3c | 197 | |
6299f992 | 198 | pinned = 0; |
73aa808f | 199 | mutex_lock(&dev->struct_mutex); |
35c20a60 | 200 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) |
1b50247a | 201 | if (obj->pin_count) |
f343c5f6 | 202 | pinned += i915_gem_obj_ggtt_size(obj); |
73aa808f | 203 | mutex_unlock(&dev->struct_mutex); |
5a125c3c | 204 | |
853ba5d2 | 205 | args->aper_size = dev_priv->gtt.base.total; |
0206e353 | 206 | args->aper_available_size = args->aper_size - pinned; |
6299f992 | 207 | |
5a125c3c EA |
208 | return 0; |
209 | } | |
210 | ||
42dcedd4 CW |
211 | void *i915_gem_object_alloc(struct drm_device *dev) |
212 | { | |
213 | struct drm_i915_private *dev_priv = dev->dev_private; | |
214 | return kmem_cache_alloc(dev_priv->slab, GFP_KERNEL | __GFP_ZERO); | |
215 | } | |
216 | ||
217 | void i915_gem_object_free(struct drm_i915_gem_object *obj) | |
218 | { | |
219 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; | |
220 | kmem_cache_free(dev_priv->slab, obj); | |
221 | } | |
222 | ||
ff72145b DA |
223 | static int |
224 | i915_gem_create(struct drm_file *file, | |
225 | struct drm_device *dev, | |
226 | uint64_t size, | |
227 | uint32_t *handle_p) | |
673a394b | 228 | { |
05394f39 | 229 | struct drm_i915_gem_object *obj; |
a1a2d1d3 PP |
230 | int ret; |
231 | u32 handle; | |
673a394b | 232 | |
ff72145b | 233 | size = roundup(size, PAGE_SIZE); |
8ffc0246 CW |
234 | if (size == 0) |
235 | return -EINVAL; | |
673a394b EA |
236 | |
237 | /* Allocate the new object */ | |
ff72145b | 238 | obj = i915_gem_alloc_object(dev, size); |
673a394b EA |
239 | if (obj == NULL) |
240 | return -ENOMEM; | |
241 | ||
05394f39 | 242 | ret = drm_gem_handle_create(file, &obj->base, &handle); |
202f2fef | 243 | /* drop reference from allocate - handle holds it now */ |
d861e338 DV |
244 | drm_gem_object_unreference_unlocked(&obj->base); |
245 | if (ret) | |
246 | return ret; | |
202f2fef | 247 | |
ff72145b | 248 | *handle_p = handle; |
673a394b EA |
249 | return 0; |
250 | } | |
251 | ||
ff72145b DA |
252 | int |
253 | i915_gem_dumb_create(struct drm_file *file, | |
254 | struct drm_device *dev, | |
255 | struct drm_mode_create_dumb *args) | |
256 | { | |
257 | /* have to work out size/pitch and return them */ | |
ed0291fd | 258 | args->pitch = ALIGN(args->width * ((args->bpp + 7) / 8), 64); |
ff72145b DA |
259 | args->size = args->pitch * args->height; |
260 | return i915_gem_create(file, dev, | |
261 | args->size, &args->handle); | |
262 | } | |
263 | ||
264 | int i915_gem_dumb_destroy(struct drm_file *file, | |
265 | struct drm_device *dev, | |
266 | uint32_t handle) | |
267 | { | |
268 | return drm_gem_handle_delete(file, handle); | |
269 | } | |
270 | ||
271 | /** | |
272 | * Creates a new mm object and returns a handle to it. | |
273 | */ | |
274 | int | |
275 | i915_gem_create_ioctl(struct drm_device *dev, void *data, | |
276 | struct drm_file *file) | |
277 | { | |
278 | struct drm_i915_gem_create *args = data; | |
63ed2cb2 | 279 | |
ff72145b DA |
280 | return i915_gem_create(file, dev, |
281 | args->size, &args->handle); | |
282 | } | |
283 | ||
8461d226 DV |
284 | static inline int |
285 | __copy_to_user_swizzled(char __user *cpu_vaddr, | |
286 | const char *gpu_vaddr, int gpu_offset, | |
287 | int length) | |
288 | { | |
289 | int ret, cpu_offset = 0; | |
290 | ||
291 | while (length > 0) { | |
292 | int cacheline_end = ALIGN(gpu_offset + 1, 64); | |
293 | int this_length = min(cacheline_end - gpu_offset, length); | |
294 | int swizzled_gpu_offset = gpu_offset ^ 64; | |
295 | ||
296 | ret = __copy_to_user(cpu_vaddr + cpu_offset, | |
297 | gpu_vaddr + swizzled_gpu_offset, | |
298 | this_length); | |
299 | if (ret) | |
300 | return ret + length; | |
301 | ||
302 | cpu_offset += this_length; | |
303 | gpu_offset += this_length; | |
304 | length -= this_length; | |
305 | } | |
306 | ||
307 | return 0; | |
308 | } | |
309 | ||
8c59967c | 310 | static inline int |
4f0c7cfb BW |
311 | __copy_from_user_swizzled(char *gpu_vaddr, int gpu_offset, |
312 | const char __user *cpu_vaddr, | |
8c59967c DV |
313 | int length) |
314 | { | |
315 | int ret, cpu_offset = 0; | |
316 | ||
317 | while (length > 0) { | |
318 | int cacheline_end = ALIGN(gpu_offset + 1, 64); | |
319 | int this_length = min(cacheline_end - gpu_offset, length); | |
320 | int swizzled_gpu_offset = gpu_offset ^ 64; | |
321 | ||
322 | ret = __copy_from_user(gpu_vaddr + swizzled_gpu_offset, | |
323 | cpu_vaddr + cpu_offset, | |
324 | this_length); | |
325 | if (ret) | |
326 | return ret + length; | |
327 | ||
328 | cpu_offset += this_length; | |
329 | gpu_offset += this_length; | |
330 | length -= this_length; | |
331 | } | |
332 | ||
333 | return 0; | |
334 | } | |
335 | ||
d174bd64 DV |
336 | /* Per-page copy function for the shmem pread fastpath. |
337 | * Flushes invalid cachelines before reading the target if | |
338 | * needs_clflush is set. */ | |
eb01459f | 339 | static int |
d174bd64 DV |
340 | shmem_pread_fast(struct page *page, int shmem_page_offset, int page_length, |
341 | char __user *user_data, | |
342 | bool page_do_bit17_swizzling, bool needs_clflush) | |
343 | { | |
344 | char *vaddr; | |
345 | int ret; | |
346 | ||
e7e58eb5 | 347 | if (unlikely(page_do_bit17_swizzling)) |
d174bd64 DV |
348 | return -EINVAL; |
349 | ||
350 | vaddr = kmap_atomic(page); | |
351 | if (needs_clflush) | |
352 | drm_clflush_virt_range(vaddr + shmem_page_offset, | |
353 | page_length); | |
354 | ret = __copy_to_user_inatomic(user_data, | |
355 | vaddr + shmem_page_offset, | |
356 | page_length); | |
357 | kunmap_atomic(vaddr); | |
358 | ||
f60d7f0c | 359 | return ret ? -EFAULT : 0; |
d174bd64 DV |
360 | } |
361 | ||
23c18c71 DV |
362 | static void |
363 | shmem_clflush_swizzled_range(char *addr, unsigned long length, | |
364 | bool swizzled) | |
365 | { | |
e7e58eb5 | 366 | if (unlikely(swizzled)) { |
23c18c71 DV |
367 | unsigned long start = (unsigned long) addr; |
368 | unsigned long end = (unsigned long) addr + length; | |
369 | ||
370 | /* For swizzling simply ensure that we always flush both | |
371 | * channels. Lame, but simple and it works. Swizzled | |
372 | * pwrite/pread is far from a hotpath - current userspace | |
373 | * doesn't use it at all. */ | |
374 | start = round_down(start, 128); | |
375 | end = round_up(end, 128); | |
376 | ||
377 | drm_clflush_virt_range((void *)start, end - start); | |
378 | } else { | |
379 | drm_clflush_virt_range(addr, length); | |
380 | } | |
381 | ||
382 | } | |
383 | ||
d174bd64 DV |
384 | /* Only difference to the fast-path function is that this can handle bit17 |
385 | * and uses non-atomic copy and kmap functions. */ | |
386 | static int | |
387 | shmem_pread_slow(struct page *page, int shmem_page_offset, int page_length, | |
388 | char __user *user_data, | |
389 | bool page_do_bit17_swizzling, bool needs_clflush) | |
390 | { | |
391 | char *vaddr; | |
392 | int ret; | |
393 | ||
394 | vaddr = kmap(page); | |
395 | if (needs_clflush) | |
23c18c71 DV |
396 | shmem_clflush_swizzled_range(vaddr + shmem_page_offset, |
397 | page_length, | |
398 | page_do_bit17_swizzling); | |
d174bd64 DV |
399 | |
400 | if (page_do_bit17_swizzling) | |
401 | ret = __copy_to_user_swizzled(user_data, | |
402 | vaddr, shmem_page_offset, | |
403 | page_length); | |
404 | else | |
405 | ret = __copy_to_user(user_data, | |
406 | vaddr + shmem_page_offset, | |
407 | page_length); | |
408 | kunmap(page); | |
409 | ||
f60d7f0c | 410 | return ret ? - EFAULT : 0; |
d174bd64 DV |
411 | } |
412 | ||
eb01459f | 413 | static int |
dbf7bff0 DV |
414 | i915_gem_shmem_pread(struct drm_device *dev, |
415 | struct drm_i915_gem_object *obj, | |
416 | struct drm_i915_gem_pread *args, | |
417 | struct drm_file *file) | |
eb01459f | 418 | { |
8461d226 | 419 | char __user *user_data; |
eb01459f | 420 | ssize_t remain; |
8461d226 | 421 | loff_t offset; |
eb2c0c81 | 422 | int shmem_page_offset, page_length, ret = 0; |
8461d226 | 423 | int obj_do_bit17_swizzling, page_do_bit17_swizzling; |
96d79b52 | 424 | int prefaulted = 0; |
8489731c | 425 | int needs_clflush = 0; |
67d5a50c | 426 | struct sg_page_iter sg_iter; |
eb01459f | 427 | |
2bb4629a | 428 | user_data = to_user_ptr(args->data_ptr); |
eb01459f EA |
429 | remain = args->size; |
430 | ||
8461d226 | 431 | obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj); |
eb01459f | 432 | |
8489731c DV |
433 | if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU)) { |
434 | /* If we're not in the cpu read domain, set ourself into the gtt | |
435 | * read domain and manually flush cachelines (if required). This | |
436 | * optimizes for the case when the gpu will dirty the data | |
437 | * anyway again before the next pread happens. */ | |
c76ce038 | 438 | needs_clflush = !cpu_cache_is_coherent(dev, obj->cache_level); |
9843877d | 439 | if (i915_gem_obj_bound_any(obj)) { |
6c085a72 CW |
440 | ret = i915_gem_object_set_to_gtt_domain(obj, false); |
441 | if (ret) | |
442 | return ret; | |
443 | } | |
8489731c | 444 | } |
eb01459f | 445 | |
f60d7f0c CW |
446 | ret = i915_gem_object_get_pages(obj); |
447 | if (ret) | |
448 | return ret; | |
449 | ||
450 | i915_gem_object_pin_pages(obj); | |
451 | ||
8461d226 | 452 | offset = args->offset; |
eb01459f | 453 | |
67d5a50c ID |
454 | for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, |
455 | offset >> PAGE_SHIFT) { | |
2db76d7c | 456 | struct page *page = sg_page_iter_page(&sg_iter); |
9da3da66 CW |
457 | |
458 | if (remain <= 0) | |
459 | break; | |
460 | ||
eb01459f EA |
461 | /* Operation in this page |
462 | * | |
eb01459f | 463 | * shmem_page_offset = offset within page in shmem file |
eb01459f EA |
464 | * page_length = bytes to copy for this page |
465 | */ | |
c8cbbb8b | 466 | shmem_page_offset = offset_in_page(offset); |
eb01459f EA |
467 | page_length = remain; |
468 | if ((shmem_page_offset + page_length) > PAGE_SIZE) | |
469 | page_length = PAGE_SIZE - shmem_page_offset; | |
eb01459f | 470 | |
8461d226 DV |
471 | page_do_bit17_swizzling = obj_do_bit17_swizzling && |
472 | (page_to_phys(page) & (1 << 17)) != 0; | |
473 | ||
d174bd64 DV |
474 | ret = shmem_pread_fast(page, shmem_page_offset, page_length, |
475 | user_data, page_do_bit17_swizzling, | |
476 | needs_clflush); | |
477 | if (ret == 0) | |
478 | goto next_page; | |
dbf7bff0 | 479 | |
dbf7bff0 DV |
480 | mutex_unlock(&dev->struct_mutex); |
481 | ||
0b74b508 | 482 | if (likely(!i915_prefault_disable) && !prefaulted) { |
f56f821f | 483 | ret = fault_in_multipages_writeable(user_data, remain); |
96d79b52 DV |
484 | /* Userspace is tricking us, but we've already clobbered |
485 | * its pages with the prefault and promised to write the | |
486 | * data up to the first fault. Hence ignore any errors | |
487 | * and just continue. */ | |
488 | (void)ret; | |
489 | prefaulted = 1; | |
490 | } | |
eb01459f | 491 | |
d174bd64 DV |
492 | ret = shmem_pread_slow(page, shmem_page_offset, page_length, |
493 | user_data, page_do_bit17_swizzling, | |
494 | needs_clflush); | |
eb01459f | 495 | |
dbf7bff0 | 496 | mutex_lock(&dev->struct_mutex); |
f60d7f0c | 497 | |
dbf7bff0 | 498 | next_page: |
e5281ccd | 499 | mark_page_accessed(page); |
e5281ccd | 500 | |
f60d7f0c | 501 | if (ret) |
8461d226 | 502 | goto out; |
8461d226 | 503 | |
eb01459f | 504 | remain -= page_length; |
8461d226 | 505 | user_data += page_length; |
eb01459f EA |
506 | offset += page_length; |
507 | } | |
508 | ||
4f27b75d | 509 | out: |
f60d7f0c CW |
510 | i915_gem_object_unpin_pages(obj); |
511 | ||
eb01459f EA |
512 | return ret; |
513 | } | |
514 | ||
673a394b EA |
515 | /** |
516 | * Reads data from the object referenced by handle. | |
517 | * | |
518 | * On error, the contents of *data are undefined. | |
519 | */ | |
520 | int | |
521 | i915_gem_pread_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 522 | struct drm_file *file) |
673a394b EA |
523 | { |
524 | struct drm_i915_gem_pread *args = data; | |
05394f39 | 525 | struct drm_i915_gem_object *obj; |
35b62a89 | 526 | int ret = 0; |
673a394b | 527 | |
51311d0a CW |
528 | if (args->size == 0) |
529 | return 0; | |
530 | ||
531 | if (!access_ok(VERIFY_WRITE, | |
2bb4629a | 532 | to_user_ptr(args->data_ptr), |
51311d0a CW |
533 | args->size)) |
534 | return -EFAULT; | |
535 | ||
4f27b75d | 536 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 537 | if (ret) |
4f27b75d | 538 | return ret; |
673a394b | 539 | |
05394f39 | 540 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 541 | if (&obj->base == NULL) { |
1d7cfea1 CW |
542 | ret = -ENOENT; |
543 | goto unlock; | |
4f27b75d | 544 | } |
673a394b | 545 | |
7dcd2499 | 546 | /* Bounds check source. */ |
05394f39 CW |
547 | if (args->offset > obj->base.size || |
548 | args->size > obj->base.size - args->offset) { | |
ce9d419d | 549 | ret = -EINVAL; |
35b62a89 | 550 | goto out; |
ce9d419d CW |
551 | } |
552 | ||
1286ff73 DV |
553 | /* prime objects have no backing filp to GEM pread/pwrite |
554 | * pages from. | |
555 | */ | |
556 | if (!obj->base.filp) { | |
557 | ret = -EINVAL; | |
558 | goto out; | |
559 | } | |
560 | ||
db53a302 CW |
561 | trace_i915_gem_object_pread(obj, args->offset, args->size); |
562 | ||
dbf7bff0 | 563 | ret = i915_gem_shmem_pread(dev, obj, args, file); |
673a394b | 564 | |
35b62a89 | 565 | out: |
05394f39 | 566 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 567 | unlock: |
4f27b75d | 568 | mutex_unlock(&dev->struct_mutex); |
eb01459f | 569 | return ret; |
673a394b EA |
570 | } |
571 | ||
0839ccb8 KP |
572 | /* This is the fast write path which cannot handle |
573 | * page faults in the source data | |
9b7530cc | 574 | */ |
0839ccb8 KP |
575 | |
576 | static inline int | |
577 | fast_user_write(struct io_mapping *mapping, | |
578 | loff_t page_base, int page_offset, | |
579 | char __user *user_data, | |
580 | int length) | |
9b7530cc | 581 | { |
4f0c7cfb BW |
582 | void __iomem *vaddr_atomic; |
583 | void *vaddr; | |
0839ccb8 | 584 | unsigned long unwritten; |
9b7530cc | 585 | |
3e4d3af5 | 586 | vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base); |
4f0c7cfb BW |
587 | /* We can use the cpu mem copy function because this is X86. */ |
588 | vaddr = (void __force*)vaddr_atomic + page_offset; | |
589 | unwritten = __copy_from_user_inatomic_nocache(vaddr, | |
0839ccb8 | 590 | user_data, length); |
3e4d3af5 | 591 | io_mapping_unmap_atomic(vaddr_atomic); |
fbd5a26d | 592 | return unwritten; |
0839ccb8 KP |
593 | } |
594 | ||
3de09aa3 EA |
595 | /** |
596 | * This is the fast pwrite path, where we copy the data directly from the | |
597 | * user into the GTT, uncached. | |
598 | */ | |
673a394b | 599 | static int |
05394f39 CW |
600 | i915_gem_gtt_pwrite_fast(struct drm_device *dev, |
601 | struct drm_i915_gem_object *obj, | |
3de09aa3 | 602 | struct drm_i915_gem_pwrite *args, |
05394f39 | 603 | struct drm_file *file) |
673a394b | 604 | { |
0839ccb8 | 605 | drm_i915_private_t *dev_priv = dev->dev_private; |
673a394b | 606 | ssize_t remain; |
0839ccb8 | 607 | loff_t offset, page_base; |
673a394b | 608 | char __user *user_data; |
935aaa69 DV |
609 | int page_offset, page_length, ret; |
610 | ||
c37e2204 | 611 | ret = i915_gem_obj_ggtt_pin(obj, 0, true, true); |
935aaa69 DV |
612 | if (ret) |
613 | goto out; | |
614 | ||
615 | ret = i915_gem_object_set_to_gtt_domain(obj, true); | |
616 | if (ret) | |
617 | goto out_unpin; | |
618 | ||
619 | ret = i915_gem_object_put_fence(obj); | |
620 | if (ret) | |
621 | goto out_unpin; | |
673a394b | 622 | |
2bb4629a | 623 | user_data = to_user_ptr(args->data_ptr); |
673a394b | 624 | remain = args->size; |
673a394b | 625 | |
f343c5f6 | 626 | offset = i915_gem_obj_ggtt_offset(obj) + args->offset; |
673a394b EA |
627 | |
628 | while (remain > 0) { | |
629 | /* Operation in this page | |
630 | * | |
0839ccb8 KP |
631 | * page_base = page offset within aperture |
632 | * page_offset = offset within page | |
633 | * page_length = bytes to copy for this page | |
673a394b | 634 | */ |
c8cbbb8b CW |
635 | page_base = offset & PAGE_MASK; |
636 | page_offset = offset_in_page(offset); | |
0839ccb8 KP |
637 | page_length = remain; |
638 | if ((page_offset + remain) > PAGE_SIZE) | |
639 | page_length = PAGE_SIZE - page_offset; | |
640 | ||
0839ccb8 | 641 | /* If we get a fault while copying data, then (presumably) our |
3de09aa3 EA |
642 | * source page isn't available. Return the error and we'll |
643 | * retry in the slow path. | |
0839ccb8 | 644 | */ |
5d4545ae | 645 | if (fast_user_write(dev_priv->gtt.mappable, page_base, |
935aaa69 DV |
646 | page_offset, user_data, page_length)) { |
647 | ret = -EFAULT; | |
648 | goto out_unpin; | |
649 | } | |
673a394b | 650 | |
0839ccb8 KP |
651 | remain -= page_length; |
652 | user_data += page_length; | |
653 | offset += page_length; | |
673a394b | 654 | } |
673a394b | 655 | |
935aaa69 DV |
656 | out_unpin: |
657 | i915_gem_object_unpin(obj); | |
658 | out: | |
3de09aa3 | 659 | return ret; |
673a394b EA |
660 | } |
661 | ||
d174bd64 DV |
662 | /* Per-page copy function for the shmem pwrite fastpath. |
663 | * Flushes invalid cachelines before writing to the target if | |
664 | * needs_clflush_before is set and flushes out any written cachelines after | |
665 | * writing if needs_clflush is set. */ | |
3043c60c | 666 | static int |
d174bd64 DV |
667 | shmem_pwrite_fast(struct page *page, int shmem_page_offset, int page_length, |
668 | char __user *user_data, | |
669 | bool page_do_bit17_swizzling, | |
670 | bool needs_clflush_before, | |
671 | bool needs_clflush_after) | |
673a394b | 672 | { |
d174bd64 | 673 | char *vaddr; |
673a394b | 674 | int ret; |
3de09aa3 | 675 | |
e7e58eb5 | 676 | if (unlikely(page_do_bit17_swizzling)) |
d174bd64 | 677 | return -EINVAL; |
3de09aa3 | 678 | |
d174bd64 DV |
679 | vaddr = kmap_atomic(page); |
680 | if (needs_clflush_before) | |
681 | drm_clflush_virt_range(vaddr + shmem_page_offset, | |
682 | page_length); | |
683 | ret = __copy_from_user_inatomic_nocache(vaddr + shmem_page_offset, | |
684 | user_data, | |
685 | page_length); | |
686 | if (needs_clflush_after) | |
687 | drm_clflush_virt_range(vaddr + shmem_page_offset, | |
688 | page_length); | |
689 | kunmap_atomic(vaddr); | |
3de09aa3 | 690 | |
755d2218 | 691 | return ret ? -EFAULT : 0; |
3de09aa3 EA |
692 | } |
693 | ||
d174bd64 DV |
694 | /* Only difference to the fast-path function is that this can handle bit17 |
695 | * and uses non-atomic copy and kmap functions. */ | |
3043c60c | 696 | static int |
d174bd64 DV |
697 | shmem_pwrite_slow(struct page *page, int shmem_page_offset, int page_length, |
698 | char __user *user_data, | |
699 | bool page_do_bit17_swizzling, | |
700 | bool needs_clflush_before, | |
701 | bool needs_clflush_after) | |
673a394b | 702 | { |
d174bd64 DV |
703 | char *vaddr; |
704 | int ret; | |
e5281ccd | 705 | |
d174bd64 | 706 | vaddr = kmap(page); |
e7e58eb5 | 707 | if (unlikely(needs_clflush_before || page_do_bit17_swizzling)) |
23c18c71 DV |
708 | shmem_clflush_swizzled_range(vaddr + shmem_page_offset, |
709 | page_length, | |
710 | page_do_bit17_swizzling); | |
d174bd64 DV |
711 | if (page_do_bit17_swizzling) |
712 | ret = __copy_from_user_swizzled(vaddr, shmem_page_offset, | |
e5281ccd CW |
713 | user_data, |
714 | page_length); | |
d174bd64 DV |
715 | else |
716 | ret = __copy_from_user(vaddr + shmem_page_offset, | |
717 | user_data, | |
718 | page_length); | |
719 | if (needs_clflush_after) | |
23c18c71 DV |
720 | shmem_clflush_swizzled_range(vaddr + shmem_page_offset, |
721 | page_length, | |
722 | page_do_bit17_swizzling); | |
d174bd64 | 723 | kunmap(page); |
40123c1f | 724 | |
755d2218 | 725 | return ret ? -EFAULT : 0; |
40123c1f EA |
726 | } |
727 | ||
40123c1f | 728 | static int |
e244a443 DV |
729 | i915_gem_shmem_pwrite(struct drm_device *dev, |
730 | struct drm_i915_gem_object *obj, | |
731 | struct drm_i915_gem_pwrite *args, | |
732 | struct drm_file *file) | |
40123c1f | 733 | { |
40123c1f | 734 | ssize_t remain; |
8c59967c DV |
735 | loff_t offset; |
736 | char __user *user_data; | |
eb2c0c81 | 737 | int shmem_page_offset, page_length, ret = 0; |
8c59967c | 738 | int obj_do_bit17_swizzling, page_do_bit17_swizzling; |
e244a443 | 739 | int hit_slowpath = 0; |
58642885 DV |
740 | int needs_clflush_after = 0; |
741 | int needs_clflush_before = 0; | |
67d5a50c | 742 | struct sg_page_iter sg_iter; |
40123c1f | 743 | |
2bb4629a | 744 | user_data = to_user_ptr(args->data_ptr); |
40123c1f EA |
745 | remain = args->size; |
746 | ||
8c59967c | 747 | obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj); |
40123c1f | 748 | |
58642885 DV |
749 | if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) { |
750 | /* If we're not in the cpu write domain, set ourself into the gtt | |
751 | * write domain and manually flush cachelines (if required). This | |
752 | * optimizes for the case when the gpu will use the data | |
753 | * right away and we therefore have to clflush anyway. */ | |
2c22569b | 754 | needs_clflush_after = cpu_write_needs_clflush(obj); |
9843877d | 755 | if (i915_gem_obj_bound_any(obj)) { |
6c085a72 CW |
756 | ret = i915_gem_object_set_to_gtt_domain(obj, true); |
757 | if (ret) | |
758 | return ret; | |
759 | } | |
58642885 | 760 | } |
c76ce038 CW |
761 | /* Same trick applies to invalidate partially written cachelines read |
762 | * before writing. */ | |
763 | if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) | |
764 | needs_clflush_before = | |
765 | !cpu_cache_is_coherent(dev, obj->cache_level); | |
58642885 | 766 | |
755d2218 CW |
767 | ret = i915_gem_object_get_pages(obj); |
768 | if (ret) | |
769 | return ret; | |
770 | ||
771 | i915_gem_object_pin_pages(obj); | |
772 | ||
673a394b | 773 | offset = args->offset; |
05394f39 | 774 | obj->dirty = 1; |
673a394b | 775 | |
67d5a50c ID |
776 | for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, |
777 | offset >> PAGE_SHIFT) { | |
2db76d7c | 778 | struct page *page = sg_page_iter_page(&sg_iter); |
58642885 | 779 | int partial_cacheline_write; |
e5281ccd | 780 | |
9da3da66 CW |
781 | if (remain <= 0) |
782 | break; | |
783 | ||
40123c1f EA |
784 | /* Operation in this page |
785 | * | |
40123c1f | 786 | * shmem_page_offset = offset within page in shmem file |
40123c1f EA |
787 | * page_length = bytes to copy for this page |
788 | */ | |
c8cbbb8b | 789 | shmem_page_offset = offset_in_page(offset); |
40123c1f EA |
790 | |
791 | page_length = remain; | |
792 | if ((shmem_page_offset + page_length) > PAGE_SIZE) | |
793 | page_length = PAGE_SIZE - shmem_page_offset; | |
40123c1f | 794 | |
58642885 DV |
795 | /* If we don't overwrite a cacheline completely we need to be |
796 | * careful to have up-to-date data by first clflushing. Don't | |
797 | * overcomplicate things and flush the entire patch. */ | |
798 | partial_cacheline_write = needs_clflush_before && | |
799 | ((shmem_page_offset | page_length) | |
800 | & (boot_cpu_data.x86_clflush_size - 1)); | |
801 | ||
8c59967c DV |
802 | page_do_bit17_swizzling = obj_do_bit17_swizzling && |
803 | (page_to_phys(page) & (1 << 17)) != 0; | |
804 | ||
d174bd64 DV |
805 | ret = shmem_pwrite_fast(page, shmem_page_offset, page_length, |
806 | user_data, page_do_bit17_swizzling, | |
807 | partial_cacheline_write, | |
808 | needs_clflush_after); | |
809 | if (ret == 0) | |
810 | goto next_page; | |
e244a443 DV |
811 | |
812 | hit_slowpath = 1; | |
e244a443 | 813 | mutex_unlock(&dev->struct_mutex); |
d174bd64 DV |
814 | ret = shmem_pwrite_slow(page, shmem_page_offset, page_length, |
815 | user_data, page_do_bit17_swizzling, | |
816 | partial_cacheline_write, | |
817 | needs_clflush_after); | |
40123c1f | 818 | |
e244a443 | 819 | mutex_lock(&dev->struct_mutex); |
755d2218 | 820 | |
e244a443 | 821 | next_page: |
e5281ccd CW |
822 | set_page_dirty(page); |
823 | mark_page_accessed(page); | |
e5281ccd | 824 | |
755d2218 | 825 | if (ret) |
8c59967c | 826 | goto out; |
8c59967c | 827 | |
40123c1f | 828 | remain -= page_length; |
8c59967c | 829 | user_data += page_length; |
40123c1f | 830 | offset += page_length; |
673a394b EA |
831 | } |
832 | ||
fbd5a26d | 833 | out: |
755d2218 CW |
834 | i915_gem_object_unpin_pages(obj); |
835 | ||
e244a443 | 836 | if (hit_slowpath) { |
8dcf015e DV |
837 | /* |
838 | * Fixup: Flush cpu caches in case we didn't flush the dirty | |
839 | * cachelines in-line while writing and the object moved | |
840 | * out of the cpu write domain while we've dropped the lock. | |
841 | */ | |
842 | if (!needs_clflush_after && | |
843 | obj->base.write_domain != I915_GEM_DOMAIN_CPU) { | |
000433b6 CW |
844 | if (i915_gem_clflush_object(obj, obj->pin_display)) |
845 | i915_gem_chipset_flush(dev); | |
e244a443 | 846 | } |
8c59967c | 847 | } |
673a394b | 848 | |
58642885 | 849 | if (needs_clflush_after) |
e76e9aeb | 850 | i915_gem_chipset_flush(dev); |
58642885 | 851 | |
40123c1f | 852 | return ret; |
673a394b EA |
853 | } |
854 | ||
855 | /** | |
856 | * Writes data to the object referenced by handle. | |
857 | * | |
858 | * On error, the contents of the buffer that were to be modified are undefined. | |
859 | */ | |
860 | int | |
861 | i915_gem_pwrite_ioctl(struct drm_device *dev, void *data, | |
fbd5a26d | 862 | struct drm_file *file) |
673a394b EA |
863 | { |
864 | struct drm_i915_gem_pwrite *args = data; | |
05394f39 | 865 | struct drm_i915_gem_object *obj; |
51311d0a CW |
866 | int ret; |
867 | ||
868 | if (args->size == 0) | |
869 | return 0; | |
870 | ||
871 | if (!access_ok(VERIFY_READ, | |
2bb4629a | 872 | to_user_ptr(args->data_ptr), |
51311d0a CW |
873 | args->size)) |
874 | return -EFAULT; | |
875 | ||
0b74b508 XZ |
876 | if (likely(!i915_prefault_disable)) { |
877 | ret = fault_in_multipages_readable(to_user_ptr(args->data_ptr), | |
878 | args->size); | |
879 | if (ret) | |
880 | return -EFAULT; | |
881 | } | |
673a394b | 882 | |
fbd5a26d | 883 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 884 | if (ret) |
fbd5a26d | 885 | return ret; |
1d7cfea1 | 886 | |
05394f39 | 887 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 888 | if (&obj->base == NULL) { |
1d7cfea1 CW |
889 | ret = -ENOENT; |
890 | goto unlock; | |
fbd5a26d | 891 | } |
673a394b | 892 | |
7dcd2499 | 893 | /* Bounds check destination. */ |
05394f39 CW |
894 | if (args->offset > obj->base.size || |
895 | args->size > obj->base.size - args->offset) { | |
ce9d419d | 896 | ret = -EINVAL; |
35b62a89 | 897 | goto out; |
ce9d419d CW |
898 | } |
899 | ||
1286ff73 DV |
900 | /* prime objects have no backing filp to GEM pread/pwrite |
901 | * pages from. | |
902 | */ | |
903 | if (!obj->base.filp) { | |
904 | ret = -EINVAL; | |
905 | goto out; | |
906 | } | |
907 | ||
db53a302 CW |
908 | trace_i915_gem_object_pwrite(obj, args->offset, args->size); |
909 | ||
935aaa69 | 910 | ret = -EFAULT; |
673a394b EA |
911 | /* We can only do the GTT pwrite on untiled buffers, as otherwise |
912 | * it would end up going through the fenced access, and we'll get | |
913 | * different detiling behavior between reading and writing. | |
914 | * pread/pwrite currently are reading and writing from the CPU | |
915 | * perspective, requiring manual detiling by the client. | |
916 | */ | |
5c0480f2 | 917 | if (obj->phys_obj) { |
fbd5a26d | 918 | ret = i915_gem_phys_pwrite(dev, obj, args, file); |
5c0480f2 DV |
919 | goto out; |
920 | } | |
921 | ||
2c22569b CW |
922 | if (obj->tiling_mode == I915_TILING_NONE && |
923 | obj->base.write_domain != I915_GEM_DOMAIN_CPU && | |
924 | cpu_write_needs_clflush(obj)) { | |
fbd5a26d | 925 | ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file); |
935aaa69 DV |
926 | /* Note that the gtt paths might fail with non-page-backed user |
927 | * pointers (e.g. gtt mappings when moving data between | |
928 | * textures). Fallback to the shmem path in that case. */ | |
fbd5a26d | 929 | } |
673a394b | 930 | |
86a1ee26 | 931 | if (ret == -EFAULT || ret == -ENOSPC) |
935aaa69 | 932 | ret = i915_gem_shmem_pwrite(dev, obj, args, file); |
5c0480f2 | 933 | |
35b62a89 | 934 | out: |
05394f39 | 935 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 936 | unlock: |
fbd5a26d | 937 | mutex_unlock(&dev->struct_mutex); |
673a394b EA |
938 | return ret; |
939 | } | |
940 | ||
b361237b | 941 | int |
33196ded | 942 | i915_gem_check_wedge(struct i915_gpu_error *error, |
b361237b CW |
943 | bool interruptible) |
944 | { | |
1f83fee0 | 945 | if (i915_reset_in_progress(error)) { |
b361237b CW |
946 | /* Non-interruptible callers can't handle -EAGAIN, hence return |
947 | * -EIO unconditionally for these. */ | |
948 | if (!interruptible) | |
949 | return -EIO; | |
950 | ||
1f83fee0 DV |
951 | /* Recovery complete, but the reset failed ... */ |
952 | if (i915_terminally_wedged(error)) | |
b361237b CW |
953 | return -EIO; |
954 | ||
955 | return -EAGAIN; | |
956 | } | |
957 | ||
958 | return 0; | |
959 | } | |
960 | ||
961 | /* | |
962 | * Compare seqno against outstanding lazy request. Emit a request if they are | |
963 | * equal. | |
964 | */ | |
965 | static int | |
966 | i915_gem_check_olr(struct intel_ring_buffer *ring, u32 seqno) | |
967 | { | |
968 | int ret; | |
969 | ||
970 | BUG_ON(!mutex_is_locked(&ring->dev->struct_mutex)); | |
971 | ||
972 | ret = 0; | |
973 | if (seqno == ring->outstanding_lazy_request) | |
0025c077 | 974 | ret = i915_add_request(ring, NULL); |
b361237b CW |
975 | |
976 | return ret; | |
977 | } | |
978 | ||
979 | /** | |
980 | * __wait_seqno - wait until execution of seqno has finished | |
981 | * @ring: the ring expected to report seqno | |
982 | * @seqno: duh! | |
f69061be | 983 | * @reset_counter: reset sequence associated with the given seqno |
b361237b CW |
984 | * @interruptible: do an interruptible wait (normally yes) |
985 | * @timeout: in - how long to wait (NULL forever); out - how much time remaining | |
986 | * | |
f69061be DV |
987 | * Note: It is of utmost importance that the passed in seqno and reset_counter |
988 | * values have been read by the caller in an smp safe manner. Where read-side | |
989 | * locks are involved, it is sufficient to read the reset_counter before | |
990 | * unlocking the lock that protects the seqno. For lockless tricks, the | |
991 | * reset_counter _must_ be read before, and an appropriate smp_rmb must be | |
992 | * inserted. | |
993 | * | |
b361237b CW |
994 | * Returns 0 if the seqno was found within the alloted time. Else returns the |
995 | * errno with remaining time filled in timeout argument. | |
996 | */ | |
997 | static int __wait_seqno(struct intel_ring_buffer *ring, u32 seqno, | |
f69061be | 998 | unsigned reset_counter, |
b361237b CW |
999 | bool interruptible, struct timespec *timeout) |
1000 | { | |
1001 | drm_i915_private_t *dev_priv = ring->dev->dev_private; | |
1002 | struct timespec before, now, wait_time={1,0}; | |
1003 | unsigned long timeout_jiffies; | |
1004 | long end; | |
1005 | bool wait_forever = true; | |
1006 | int ret; | |
1007 | ||
1008 | if (i915_seqno_passed(ring->get_seqno(ring, true), seqno)) | |
1009 | return 0; | |
1010 | ||
1011 | trace_i915_gem_request_wait_begin(ring, seqno); | |
1012 | ||
1013 | if (timeout != NULL) { | |
1014 | wait_time = *timeout; | |
1015 | wait_forever = false; | |
1016 | } | |
1017 | ||
e054cc39 | 1018 | timeout_jiffies = timespec_to_jiffies_timeout(&wait_time); |
b361237b CW |
1019 | |
1020 | if (WARN_ON(!ring->irq_get(ring))) | |
1021 | return -ENODEV; | |
1022 | ||
1023 | /* Record current time in case interrupted by signal, or wedged * */ | |
1024 | getrawmonotonic(&before); | |
1025 | ||
1026 | #define EXIT_COND \ | |
1027 | (i915_seqno_passed(ring->get_seqno(ring, false), seqno) || \ | |
f69061be DV |
1028 | i915_reset_in_progress(&dev_priv->gpu_error) || \ |
1029 | reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter)) | |
b361237b CW |
1030 | do { |
1031 | if (interruptible) | |
1032 | end = wait_event_interruptible_timeout(ring->irq_queue, | |
1033 | EXIT_COND, | |
1034 | timeout_jiffies); | |
1035 | else | |
1036 | end = wait_event_timeout(ring->irq_queue, EXIT_COND, | |
1037 | timeout_jiffies); | |
1038 | ||
f69061be DV |
1039 | /* We need to check whether any gpu reset happened in between |
1040 | * the caller grabbing the seqno and now ... */ | |
1041 | if (reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter)) | |
1042 | end = -EAGAIN; | |
1043 | ||
1044 | /* ... but upgrade the -EGAIN to an -EIO if the gpu is truely | |
1045 | * gone. */ | |
33196ded | 1046 | ret = i915_gem_check_wedge(&dev_priv->gpu_error, interruptible); |
b361237b CW |
1047 | if (ret) |
1048 | end = ret; | |
1049 | } while (end == 0 && wait_forever); | |
1050 | ||
1051 | getrawmonotonic(&now); | |
1052 | ||
1053 | ring->irq_put(ring); | |
1054 | trace_i915_gem_request_wait_end(ring, seqno); | |
1055 | #undef EXIT_COND | |
1056 | ||
1057 | if (timeout) { | |
1058 | struct timespec sleep_time = timespec_sub(now, before); | |
1059 | *timeout = timespec_sub(*timeout, sleep_time); | |
4f42f4ef CW |
1060 | if (!timespec_valid(timeout)) /* i.e. negative time remains */ |
1061 | set_normalized_timespec(timeout, 0, 0); | |
b361237b CW |
1062 | } |
1063 | ||
1064 | switch (end) { | |
1065 | case -EIO: | |
1066 | case -EAGAIN: /* Wedged */ | |
1067 | case -ERESTARTSYS: /* Signal */ | |
1068 | return (int)end; | |
1069 | case 0: /* Timeout */ | |
b361237b CW |
1070 | return -ETIME; |
1071 | default: /* Completed */ | |
1072 | WARN_ON(end < 0); /* We're not aware of other errors */ | |
1073 | return 0; | |
1074 | } | |
1075 | } | |
1076 | ||
1077 | /** | |
1078 | * Waits for a sequence number to be signaled, and cleans up the | |
1079 | * request and object lists appropriately for that event. | |
1080 | */ | |
1081 | int | |
1082 | i915_wait_seqno(struct intel_ring_buffer *ring, uint32_t seqno) | |
1083 | { | |
1084 | struct drm_device *dev = ring->dev; | |
1085 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1086 | bool interruptible = dev_priv->mm.interruptible; | |
1087 | int ret; | |
1088 | ||
1089 | BUG_ON(!mutex_is_locked(&dev->struct_mutex)); | |
1090 | BUG_ON(seqno == 0); | |
1091 | ||
33196ded | 1092 | ret = i915_gem_check_wedge(&dev_priv->gpu_error, interruptible); |
b361237b CW |
1093 | if (ret) |
1094 | return ret; | |
1095 | ||
1096 | ret = i915_gem_check_olr(ring, seqno); | |
1097 | if (ret) | |
1098 | return ret; | |
1099 | ||
f69061be DV |
1100 | return __wait_seqno(ring, seqno, |
1101 | atomic_read(&dev_priv->gpu_error.reset_counter), | |
1102 | interruptible, NULL); | |
b361237b CW |
1103 | } |
1104 | ||
d26e3af8 CW |
1105 | static int |
1106 | i915_gem_object_wait_rendering__tail(struct drm_i915_gem_object *obj, | |
1107 | struct intel_ring_buffer *ring) | |
1108 | { | |
1109 | i915_gem_retire_requests_ring(ring); | |
1110 | ||
1111 | /* Manually manage the write flush as we may have not yet | |
1112 | * retired the buffer. | |
1113 | * | |
1114 | * Note that the last_write_seqno is always the earlier of | |
1115 | * the two (read/write) seqno, so if we haved successfully waited, | |
1116 | * we know we have passed the last write. | |
1117 | */ | |
1118 | obj->last_write_seqno = 0; | |
1119 | obj->base.write_domain &= ~I915_GEM_GPU_DOMAINS; | |
1120 | ||
1121 | return 0; | |
1122 | } | |
1123 | ||
b361237b CW |
1124 | /** |
1125 | * Ensures that all rendering to the object has completed and the object is | |
1126 | * safe to unbind from the GTT or access from the CPU. | |
1127 | */ | |
1128 | static __must_check int | |
1129 | i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj, | |
1130 | bool readonly) | |
1131 | { | |
1132 | struct intel_ring_buffer *ring = obj->ring; | |
1133 | u32 seqno; | |
1134 | int ret; | |
1135 | ||
1136 | seqno = readonly ? obj->last_write_seqno : obj->last_read_seqno; | |
1137 | if (seqno == 0) | |
1138 | return 0; | |
1139 | ||
1140 | ret = i915_wait_seqno(ring, seqno); | |
1141 | if (ret) | |
1142 | return ret; | |
1143 | ||
d26e3af8 | 1144 | return i915_gem_object_wait_rendering__tail(obj, ring); |
b361237b CW |
1145 | } |
1146 | ||
3236f57a CW |
1147 | /* A nonblocking variant of the above wait. This is a highly dangerous routine |
1148 | * as the object state may change during this call. | |
1149 | */ | |
1150 | static __must_check int | |
1151 | i915_gem_object_wait_rendering__nonblocking(struct drm_i915_gem_object *obj, | |
1152 | bool readonly) | |
1153 | { | |
1154 | struct drm_device *dev = obj->base.dev; | |
1155 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1156 | struct intel_ring_buffer *ring = obj->ring; | |
f69061be | 1157 | unsigned reset_counter; |
3236f57a CW |
1158 | u32 seqno; |
1159 | int ret; | |
1160 | ||
1161 | BUG_ON(!mutex_is_locked(&dev->struct_mutex)); | |
1162 | BUG_ON(!dev_priv->mm.interruptible); | |
1163 | ||
1164 | seqno = readonly ? obj->last_write_seqno : obj->last_read_seqno; | |
1165 | if (seqno == 0) | |
1166 | return 0; | |
1167 | ||
33196ded | 1168 | ret = i915_gem_check_wedge(&dev_priv->gpu_error, true); |
3236f57a CW |
1169 | if (ret) |
1170 | return ret; | |
1171 | ||
1172 | ret = i915_gem_check_olr(ring, seqno); | |
1173 | if (ret) | |
1174 | return ret; | |
1175 | ||
f69061be | 1176 | reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter); |
3236f57a | 1177 | mutex_unlock(&dev->struct_mutex); |
f69061be | 1178 | ret = __wait_seqno(ring, seqno, reset_counter, true, NULL); |
3236f57a | 1179 | mutex_lock(&dev->struct_mutex); |
d26e3af8 CW |
1180 | if (ret) |
1181 | return ret; | |
3236f57a | 1182 | |
d26e3af8 | 1183 | return i915_gem_object_wait_rendering__tail(obj, ring); |
3236f57a CW |
1184 | } |
1185 | ||
673a394b | 1186 | /** |
2ef7eeaa EA |
1187 | * Called when user space prepares to use an object with the CPU, either |
1188 | * through the mmap ioctl's mapping or a GTT mapping. | |
673a394b EA |
1189 | */ |
1190 | int | |
1191 | i915_gem_set_domain_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 1192 | struct drm_file *file) |
673a394b EA |
1193 | { |
1194 | struct drm_i915_gem_set_domain *args = data; | |
05394f39 | 1195 | struct drm_i915_gem_object *obj; |
2ef7eeaa EA |
1196 | uint32_t read_domains = args->read_domains; |
1197 | uint32_t write_domain = args->write_domain; | |
673a394b EA |
1198 | int ret; |
1199 | ||
2ef7eeaa | 1200 | /* Only handle setting domains to types used by the CPU. */ |
21d509e3 | 1201 | if (write_domain & I915_GEM_GPU_DOMAINS) |
2ef7eeaa EA |
1202 | return -EINVAL; |
1203 | ||
21d509e3 | 1204 | if (read_domains & I915_GEM_GPU_DOMAINS) |
2ef7eeaa EA |
1205 | return -EINVAL; |
1206 | ||
1207 | /* Having something in the write domain implies it's in the read | |
1208 | * domain, and only that read domain. Enforce that in the request. | |
1209 | */ | |
1210 | if (write_domain != 0 && read_domains != write_domain) | |
1211 | return -EINVAL; | |
1212 | ||
76c1dec1 | 1213 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 1214 | if (ret) |
76c1dec1 | 1215 | return ret; |
1d7cfea1 | 1216 | |
05394f39 | 1217 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 1218 | if (&obj->base == NULL) { |
1d7cfea1 CW |
1219 | ret = -ENOENT; |
1220 | goto unlock; | |
76c1dec1 | 1221 | } |
673a394b | 1222 | |
3236f57a CW |
1223 | /* Try to flush the object off the GPU without holding the lock. |
1224 | * We will repeat the flush holding the lock in the normal manner | |
1225 | * to catch cases where we are gazumped. | |
1226 | */ | |
1227 | ret = i915_gem_object_wait_rendering__nonblocking(obj, !write_domain); | |
1228 | if (ret) | |
1229 | goto unref; | |
1230 | ||
2ef7eeaa EA |
1231 | if (read_domains & I915_GEM_DOMAIN_GTT) { |
1232 | ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0); | |
02354392 EA |
1233 | |
1234 | /* Silently promote "you're not bound, there was nothing to do" | |
1235 | * to success, since the client was just asking us to | |
1236 | * make sure everything was done. | |
1237 | */ | |
1238 | if (ret == -EINVAL) | |
1239 | ret = 0; | |
2ef7eeaa | 1240 | } else { |
e47c68e9 | 1241 | ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0); |
2ef7eeaa EA |
1242 | } |
1243 | ||
3236f57a | 1244 | unref: |
05394f39 | 1245 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 1246 | unlock: |
673a394b EA |
1247 | mutex_unlock(&dev->struct_mutex); |
1248 | return ret; | |
1249 | } | |
1250 | ||
1251 | /** | |
1252 | * Called when user space has done writes to this buffer | |
1253 | */ | |
1254 | int | |
1255 | i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 1256 | struct drm_file *file) |
673a394b EA |
1257 | { |
1258 | struct drm_i915_gem_sw_finish *args = data; | |
05394f39 | 1259 | struct drm_i915_gem_object *obj; |
673a394b EA |
1260 | int ret = 0; |
1261 | ||
76c1dec1 | 1262 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 1263 | if (ret) |
76c1dec1 | 1264 | return ret; |
1d7cfea1 | 1265 | |
05394f39 | 1266 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 1267 | if (&obj->base == NULL) { |
1d7cfea1 CW |
1268 | ret = -ENOENT; |
1269 | goto unlock; | |
673a394b EA |
1270 | } |
1271 | ||
673a394b | 1272 | /* Pinned buffers may be scanout, so flush the cache */ |
2c22569b CW |
1273 | if (obj->pin_display) |
1274 | i915_gem_object_flush_cpu_write_domain(obj, true); | |
e47c68e9 | 1275 | |
05394f39 | 1276 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 1277 | unlock: |
673a394b EA |
1278 | mutex_unlock(&dev->struct_mutex); |
1279 | return ret; | |
1280 | } | |
1281 | ||
1282 | /** | |
1283 | * Maps the contents of an object, returning the address it is mapped | |
1284 | * into. | |
1285 | * | |
1286 | * While the mapping holds a reference on the contents of the object, it doesn't | |
1287 | * imply a ref on the object itself. | |
1288 | */ | |
1289 | int | |
1290 | i915_gem_mmap_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 1291 | struct drm_file *file) |
673a394b EA |
1292 | { |
1293 | struct drm_i915_gem_mmap *args = data; | |
1294 | struct drm_gem_object *obj; | |
673a394b EA |
1295 | unsigned long addr; |
1296 | ||
05394f39 | 1297 | obj = drm_gem_object_lookup(dev, file, args->handle); |
673a394b | 1298 | if (obj == NULL) |
bf79cb91 | 1299 | return -ENOENT; |
673a394b | 1300 | |
1286ff73 DV |
1301 | /* prime objects have no backing filp to GEM mmap |
1302 | * pages from. | |
1303 | */ | |
1304 | if (!obj->filp) { | |
1305 | drm_gem_object_unreference_unlocked(obj); | |
1306 | return -EINVAL; | |
1307 | } | |
1308 | ||
6be5ceb0 | 1309 | addr = vm_mmap(obj->filp, 0, args->size, |
673a394b EA |
1310 | PROT_READ | PROT_WRITE, MAP_SHARED, |
1311 | args->offset); | |
bc9025bd | 1312 | drm_gem_object_unreference_unlocked(obj); |
673a394b EA |
1313 | if (IS_ERR((void *)addr)) |
1314 | return addr; | |
1315 | ||
1316 | args->addr_ptr = (uint64_t) addr; | |
1317 | ||
1318 | return 0; | |
1319 | } | |
1320 | ||
de151cf6 JB |
1321 | /** |
1322 | * i915_gem_fault - fault a page into the GTT | |
1323 | * vma: VMA in question | |
1324 | * vmf: fault info | |
1325 | * | |
1326 | * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped | |
1327 | * from userspace. The fault handler takes care of binding the object to | |
1328 | * the GTT (if needed), allocating and programming a fence register (again, | |
1329 | * only if needed based on whether the old reg is still valid or the object | |
1330 | * is tiled) and inserting a new PTE into the faulting process. | |
1331 | * | |
1332 | * Note that the faulting process may involve evicting existing objects | |
1333 | * from the GTT and/or fence registers to make room. So performance may | |
1334 | * suffer if the GTT working set is large or there are few fence registers | |
1335 | * left. | |
1336 | */ | |
1337 | int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf) | |
1338 | { | |
05394f39 CW |
1339 | struct drm_i915_gem_object *obj = to_intel_bo(vma->vm_private_data); |
1340 | struct drm_device *dev = obj->base.dev; | |
7d1c4804 | 1341 | drm_i915_private_t *dev_priv = dev->dev_private; |
de151cf6 JB |
1342 | pgoff_t page_offset; |
1343 | unsigned long pfn; | |
1344 | int ret = 0; | |
0f973f27 | 1345 | bool write = !!(vmf->flags & FAULT_FLAG_WRITE); |
de151cf6 JB |
1346 | |
1347 | /* We don't use vmf->pgoff since that has the fake offset */ | |
1348 | page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >> | |
1349 | PAGE_SHIFT; | |
1350 | ||
d9bc7e9f CW |
1351 | ret = i915_mutex_lock_interruptible(dev); |
1352 | if (ret) | |
1353 | goto out; | |
a00b10c3 | 1354 | |
db53a302 CW |
1355 | trace_i915_gem_object_fault(obj, page_offset, true, write); |
1356 | ||
eb119bd6 CW |
1357 | /* Access to snoopable pages through the GTT is incoherent. */ |
1358 | if (obj->cache_level != I915_CACHE_NONE && !HAS_LLC(dev)) { | |
1359 | ret = -EINVAL; | |
1360 | goto unlock; | |
1361 | } | |
1362 | ||
d9bc7e9f | 1363 | /* Now bind it into the GTT if needed */ |
c37e2204 | 1364 | ret = i915_gem_obj_ggtt_pin(obj, 0, true, false); |
c9839303 CW |
1365 | if (ret) |
1366 | goto unlock; | |
4a684a41 | 1367 | |
c9839303 CW |
1368 | ret = i915_gem_object_set_to_gtt_domain(obj, write); |
1369 | if (ret) | |
1370 | goto unpin; | |
74898d7e | 1371 | |
06d98131 | 1372 | ret = i915_gem_object_get_fence(obj); |
d9e86c0e | 1373 | if (ret) |
c9839303 | 1374 | goto unpin; |
7d1c4804 | 1375 | |
6299f992 CW |
1376 | obj->fault_mappable = true; |
1377 | ||
f343c5f6 BW |
1378 | pfn = dev_priv->gtt.mappable_base + i915_gem_obj_ggtt_offset(obj); |
1379 | pfn >>= PAGE_SHIFT; | |
1380 | pfn += page_offset; | |
de151cf6 JB |
1381 | |
1382 | /* Finally, remap it using the new GTT offset */ | |
1383 | ret = vm_insert_pfn(vma, (unsigned long)vmf->virtual_address, pfn); | |
c9839303 CW |
1384 | unpin: |
1385 | i915_gem_object_unpin(obj); | |
c715089f | 1386 | unlock: |
de151cf6 | 1387 | mutex_unlock(&dev->struct_mutex); |
d9bc7e9f | 1388 | out: |
de151cf6 | 1389 | switch (ret) { |
d9bc7e9f | 1390 | case -EIO: |
a9340cca DV |
1391 | /* If this -EIO is due to a gpu hang, give the reset code a |
1392 | * chance to clean up the mess. Otherwise return the proper | |
1393 | * SIGBUS. */ | |
1f83fee0 | 1394 | if (i915_terminally_wedged(&dev_priv->gpu_error)) |
a9340cca | 1395 | return VM_FAULT_SIGBUS; |
045e769a | 1396 | case -EAGAIN: |
d9bc7e9f CW |
1397 | /* Give the error handler a chance to run and move the |
1398 | * objects off the GPU active list. Next time we service the | |
1399 | * fault, we should be able to transition the page into the | |
1400 | * GTT without touching the GPU (and so avoid further | |
1401 | * EIO/EGAIN). If the GPU is wedged, then there is no issue | |
1402 | * with coherency, just lost writes. | |
1403 | */ | |
045e769a | 1404 | set_need_resched(); |
c715089f CW |
1405 | case 0: |
1406 | case -ERESTARTSYS: | |
bed636ab | 1407 | case -EINTR: |
e79e0fe3 DR |
1408 | case -EBUSY: |
1409 | /* | |
1410 | * EBUSY is ok: this just means that another thread | |
1411 | * already did the job. | |
1412 | */ | |
c715089f | 1413 | return VM_FAULT_NOPAGE; |
de151cf6 | 1414 | case -ENOMEM: |
de151cf6 | 1415 | return VM_FAULT_OOM; |
a7c2e1aa DV |
1416 | case -ENOSPC: |
1417 | return VM_FAULT_SIGBUS; | |
de151cf6 | 1418 | default: |
a7c2e1aa | 1419 | WARN_ONCE(ret, "unhandled error in i915_gem_fault: %i\n", ret); |
c715089f | 1420 | return VM_FAULT_SIGBUS; |
de151cf6 JB |
1421 | } |
1422 | } | |
1423 | ||
901782b2 CW |
1424 | /** |
1425 | * i915_gem_release_mmap - remove physical page mappings | |
1426 | * @obj: obj in question | |
1427 | * | |
af901ca1 | 1428 | * Preserve the reservation of the mmapping with the DRM core code, but |
901782b2 CW |
1429 | * relinquish ownership of the pages back to the system. |
1430 | * | |
1431 | * It is vital that we remove the page mapping if we have mapped a tiled | |
1432 | * object through the GTT and then lose the fence register due to | |
1433 | * resource pressure. Similarly if the object has been moved out of the | |
1434 | * aperture, than pages mapped into userspace must be revoked. Removing the | |
1435 | * mapping will then trigger a page fault on the next user access, allowing | |
1436 | * fixup by i915_gem_fault(). | |
1437 | */ | |
d05ca301 | 1438 | void |
05394f39 | 1439 | i915_gem_release_mmap(struct drm_i915_gem_object *obj) |
901782b2 | 1440 | { |
6299f992 CW |
1441 | if (!obj->fault_mappable) |
1442 | return; | |
901782b2 | 1443 | |
f6e47884 CW |
1444 | if (obj->base.dev->dev_mapping) |
1445 | unmap_mapping_range(obj->base.dev->dev_mapping, | |
1446 | (loff_t)obj->base.map_list.hash.key<<PAGE_SHIFT, | |
1447 | obj->base.size, 1); | |
fb7d516a | 1448 | |
6299f992 | 1449 | obj->fault_mappable = false; |
901782b2 CW |
1450 | } |
1451 | ||
0fa87796 | 1452 | uint32_t |
e28f8711 | 1453 | i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode) |
92b88aeb | 1454 | { |
e28f8711 | 1455 | uint32_t gtt_size; |
92b88aeb CW |
1456 | |
1457 | if (INTEL_INFO(dev)->gen >= 4 || | |
e28f8711 CW |
1458 | tiling_mode == I915_TILING_NONE) |
1459 | return size; | |
92b88aeb CW |
1460 | |
1461 | /* Previous chips need a power-of-two fence region when tiling */ | |
1462 | if (INTEL_INFO(dev)->gen == 3) | |
e28f8711 | 1463 | gtt_size = 1024*1024; |
92b88aeb | 1464 | else |
e28f8711 | 1465 | gtt_size = 512*1024; |
92b88aeb | 1466 | |
e28f8711 CW |
1467 | while (gtt_size < size) |
1468 | gtt_size <<= 1; | |
92b88aeb | 1469 | |
e28f8711 | 1470 | return gtt_size; |
92b88aeb CW |
1471 | } |
1472 | ||
de151cf6 JB |
1473 | /** |
1474 | * i915_gem_get_gtt_alignment - return required GTT alignment for an object | |
1475 | * @obj: object to check | |
1476 | * | |
1477 | * Return the required GTT alignment for an object, taking into account | |
5e783301 | 1478 | * potential fence register mapping. |
de151cf6 | 1479 | */ |
d865110c ID |
1480 | uint32_t |
1481 | i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size, | |
1482 | int tiling_mode, bool fenced) | |
de151cf6 | 1483 | { |
de151cf6 JB |
1484 | /* |
1485 | * Minimum alignment is 4k (GTT page size), but might be greater | |
1486 | * if a fence register is needed for the object. | |
1487 | */ | |
d865110c | 1488 | if (INTEL_INFO(dev)->gen >= 4 || (!fenced && IS_G33(dev)) || |
e28f8711 | 1489 | tiling_mode == I915_TILING_NONE) |
de151cf6 JB |
1490 | return 4096; |
1491 | ||
a00b10c3 CW |
1492 | /* |
1493 | * Previous chips need to be aligned to the size of the smallest | |
1494 | * fence register that can contain the object. | |
1495 | */ | |
e28f8711 | 1496 | return i915_gem_get_gtt_size(dev, size, tiling_mode); |
a00b10c3 CW |
1497 | } |
1498 | ||
d8cb5086 CW |
1499 | static int i915_gem_object_create_mmap_offset(struct drm_i915_gem_object *obj) |
1500 | { | |
1501 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; | |
1502 | int ret; | |
1503 | ||
1504 | if (obj->base.map_list.map) | |
1505 | return 0; | |
1506 | ||
da494d7c DV |
1507 | dev_priv->mm.shrinker_no_lock_stealing = true; |
1508 | ||
d8cb5086 CW |
1509 | ret = drm_gem_create_mmap_offset(&obj->base); |
1510 | if (ret != -ENOSPC) | |
da494d7c | 1511 | goto out; |
d8cb5086 CW |
1512 | |
1513 | /* Badly fragmented mmap space? The only way we can recover | |
1514 | * space is by destroying unwanted objects. We can't randomly release | |
1515 | * mmap_offsets as userspace expects them to be persistent for the | |
1516 | * lifetime of the objects. The closest we can is to release the | |
1517 | * offsets on purgeable objects by truncating it and marking it purged, | |
1518 | * which prevents userspace from ever using that object again. | |
1519 | */ | |
1520 | i915_gem_purge(dev_priv, obj->base.size >> PAGE_SHIFT); | |
1521 | ret = drm_gem_create_mmap_offset(&obj->base); | |
1522 | if (ret != -ENOSPC) | |
da494d7c | 1523 | goto out; |
d8cb5086 CW |
1524 | |
1525 | i915_gem_shrink_all(dev_priv); | |
da494d7c DV |
1526 | ret = drm_gem_create_mmap_offset(&obj->base); |
1527 | out: | |
1528 | dev_priv->mm.shrinker_no_lock_stealing = false; | |
1529 | ||
1530 | return ret; | |
d8cb5086 CW |
1531 | } |
1532 | ||
1533 | static void i915_gem_object_free_mmap_offset(struct drm_i915_gem_object *obj) | |
1534 | { | |
1535 | if (!obj->base.map_list.map) | |
1536 | return; | |
1537 | ||
1538 | drm_gem_free_mmap_offset(&obj->base); | |
1539 | } | |
1540 | ||
de151cf6 | 1541 | int |
ff72145b DA |
1542 | i915_gem_mmap_gtt(struct drm_file *file, |
1543 | struct drm_device *dev, | |
1544 | uint32_t handle, | |
1545 | uint64_t *offset) | |
de151cf6 | 1546 | { |
da761a6e | 1547 | struct drm_i915_private *dev_priv = dev->dev_private; |
05394f39 | 1548 | struct drm_i915_gem_object *obj; |
de151cf6 JB |
1549 | int ret; |
1550 | ||
76c1dec1 | 1551 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 1552 | if (ret) |
76c1dec1 | 1553 | return ret; |
de151cf6 | 1554 | |
ff72145b | 1555 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle)); |
c8725226 | 1556 | if (&obj->base == NULL) { |
1d7cfea1 CW |
1557 | ret = -ENOENT; |
1558 | goto unlock; | |
1559 | } | |
de151cf6 | 1560 | |
5d4545ae | 1561 | if (obj->base.size > dev_priv->gtt.mappable_end) { |
da761a6e | 1562 | ret = -E2BIG; |
ff56b0bc | 1563 | goto out; |
da761a6e CW |
1564 | } |
1565 | ||
05394f39 | 1566 | if (obj->madv != I915_MADV_WILLNEED) { |
ab18282d | 1567 | DRM_ERROR("Attempting to mmap a purgeable buffer\n"); |
1d7cfea1 CW |
1568 | ret = -EINVAL; |
1569 | goto out; | |
ab18282d CW |
1570 | } |
1571 | ||
d8cb5086 CW |
1572 | ret = i915_gem_object_create_mmap_offset(obj); |
1573 | if (ret) | |
1574 | goto out; | |
de151cf6 | 1575 | |
ff72145b | 1576 | *offset = (u64)obj->base.map_list.hash.key << PAGE_SHIFT; |
de151cf6 | 1577 | |
1d7cfea1 | 1578 | out: |
05394f39 | 1579 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 1580 | unlock: |
de151cf6 | 1581 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 1582 | return ret; |
de151cf6 JB |
1583 | } |
1584 | ||
ff72145b DA |
1585 | /** |
1586 | * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing | |
1587 | * @dev: DRM device | |
1588 | * @data: GTT mapping ioctl data | |
1589 | * @file: GEM object info | |
1590 | * | |
1591 | * Simply returns the fake offset to userspace so it can mmap it. | |
1592 | * The mmap call will end up in drm_gem_mmap(), which will set things | |
1593 | * up so we can get faults in the handler above. | |
1594 | * | |
1595 | * The fault handler will take care of binding the object into the GTT | |
1596 | * (since it may have been evicted to make room for something), allocating | |
1597 | * a fence register, and mapping the appropriate aperture address into | |
1598 | * userspace. | |
1599 | */ | |
1600 | int | |
1601 | i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data, | |
1602 | struct drm_file *file) | |
1603 | { | |
1604 | struct drm_i915_gem_mmap_gtt *args = data; | |
1605 | ||
ff72145b DA |
1606 | return i915_gem_mmap_gtt(file, dev, args->handle, &args->offset); |
1607 | } | |
1608 | ||
225067ee DV |
1609 | /* Immediately discard the backing storage */ |
1610 | static void | |
1611 | i915_gem_object_truncate(struct drm_i915_gem_object *obj) | |
e5281ccd | 1612 | { |
e5281ccd | 1613 | struct inode *inode; |
e5281ccd | 1614 | |
4d6294bf | 1615 | i915_gem_object_free_mmap_offset(obj); |
1286ff73 | 1616 | |
4d6294bf CW |
1617 | if (obj->base.filp == NULL) |
1618 | return; | |
e5281ccd | 1619 | |
225067ee DV |
1620 | /* Our goal here is to return as much of the memory as |
1621 | * is possible back to the system as we are called from OOM. | |
1622 | * To do this we must instruct the shmfs to drop all of its | |
1623 | * backing pages, *now*. | |
1624 | */ | |
496ad9aa | 1625 | inode = file_inode(obj->base.filp); |
225067ee | 1626 | shmem_truncate_range(inode, 0, (loff_t)-1); |
e5281ccd | 1627 | |
225067ee DV |
1628 | obj->madv = __I915_MADV_PURGED; |
1629 | } | |
e5281ccd | 1630 | |
225067ee DV |
1631 | static inline int |
1632 | i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj) | |
1633 | { | |
1634 | return obj->madv == I915_MADV_DONTNEED; | |
e5281ccd CW |
1635 | } |
1636 | ||
5cdf5881 | 1637 | static void |
05394f39 | 1638 | i915_gem_object_put_pages_gtt(struct drm_i915_gem_object *obj) |
673a394b | 1639 | { |
90797e6d ID |
1640 | struct sg_page_iter sg_iter; |
1641 | int ret; | |
1286ff73 | 1642 | |
05394f39 | 1643 | BUG_ON(obj->madv == __I915_MADV_PURGED); |
673a394b | 1644 | |
6c085a72 CW |
1645 | ret = i915_gem_object_set_to_cpu_domain(obj, true); |
1646 | if (ret) { | |
1647 | /* In the event of a disaster, abandon all caches and | |
1648 | * hope for the best. | |
1649 | */ | |
1650 | WARN_ON(ret != -EIO); | |
2c22569b | 1651 | i915_gem_clflush_object(obj, true); |
6c085a72 CW |
1652 | obj->base.read_domains = obj->base.write_domain = I915_GEM_DOMAIN_CPU; |
1653 | } | |
1654 | ||
6dacfd2f | 1655 | if (i915_gem_object_needs_bit17_swizzle(obj)) |
280b713b EA |
1656 | i915_gem_object_save_bit_17_swizzle(obj); |
1657 | ||
05394f39 CW |
1658 | if (obj->madv == I915_MADV_DONTNEED) |
1659 | obj->dirty = 0; | |
3ef94daa | 1660 | |
90797e6d | 1661 | for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, 0) { |
2db76d7c | 1662 | struct page *page = sg_page_iter_page(&sg_iter); |
9da3da66 | 1663 | |
05394f39 | 1664 | if (obj->dirty) |
9da3da66 | 1665 | set_page_dirty(page); |
3ef94daa | 1666 | |
05394f39 | 1667 | if (obj->madv == I915_MADV_WILLNEED) |
9da3da66 | 1668 | mark_page_accessed(page); |
3ef94daa | 1669 | |
9da3da66 | 1670 | page_cache_release(page); |
3ef94daa | 1671 | } |
05394f39 | 1672 | obj->dirty = 0; |
673a394b | 1673 | |
9da3da66 CW |
1674 | sg_free_table(obj->pages); |
1675 | kfree(obj->pages); | |
37e680a1 | 1676 | } |
6c085a72 | 1677 | |
dd624afd | 1678 | int |
37e680a1 CW |
1679 | i915_gem_object_put_pages(struct drm_i915_gem_object *obj) |
1680 | { | |
1681 | const struct drm_i915_gem_object_ops *ops = obj->ops; | |
1682 | ||
2f745ad3 | 1683 | if (obj->pages == NULL) |
37e680a1 CW |
1684 | return 0; |
1685 | ||
a5570178 CW |
1686 | if (obj->pages_pin_count) |
1687 | return -EBUSY; | |
1688 | ||
9843877d | 1689 | BUG_ON(i915_gem_obj_bound_any(obj)); |
3e123027 | 1690 | |
a2165e31 CW |
1691 | /* ->put_pages might need to allocate memory for the bit17 swizzle |
1692 | * array, hence protect them from being reaped by removing them from gtt | |
1693 | * lists early. */ | |
35c20a60 | 1694 | list_del(&obj->global_list); |
a2165e31 | 1695 | |
37e680a1 | 1696 | ops->put_pages(obj); |
05394f39 | 1697 | obj->pages = NULL; |
37e680a1 | 1698 | |
6c085a72 CW |
1699 | if (i915_gem_object_is_purgeable(obj)) |
1700 | i915_gem_object_truncate(obj); | |
1701 | ||
1702 | return 0; | |
1703 | } | |
1704 | ||
1705 | static long | |
93927ca5 DV |
1706 | __i915_gem_shrink(struct drm_i915_private *dev_priv, long target, |
1707 | bool purgeable_only) | |
6c085a72 CW |
1708 | { |
1709 | struct drm_i915_gem_object *obj, *next; | |
1710 | long count = 0; | |
1711 | ||
1712 | list_for_each_entry_safe(obj, next, | |
1713 | &dev_priv->mm.unbound_list, | |
35c20a60 | 1714 | global_list) { |
93927ca5 | 1715 | if ((i915_gem_object_is_purgeable(obj) || !purgeable_only) && |
37e680a1 | 1716 | i915_gem_object_put_pages(obj) == 0) { |
6c085a72 CW |
1717 | count += obj->base.size >> PAGE_SHIFT; |
1718 | if (count >= target) | |
1719 | return count; | |
1720 | } | |
1721 | } | |
1722 | ||
07fe0b12 BW |
1723 | list_for_each_entry_safe(obj, next, &dev_priv->mm.bound_list, |
1724 | global_list) { | |
1725 | struct i915_vma *vma, *v; | |
80dcfdbd BW |
1726 | |
1727 | if (!i915_gem_object_is_purgeable(obj) && purgeable_only) | |
1728 | continue; | |
1729 | ||
07fe0b12 BW |
1730 | list_for_each_entry_safe(vma, v, &obj->vma_list, vma_link) |
1731 | if (i915_vma_unbind(vma)) | |
1732 | break; | |
80dcfdbd BW |
1733 | |
1734 | if (!i915_gem_object_put_pages(obj)) { | |
6c085a72 CW |
1735 | count += obj->base.size >> PAGE_SHIFT; |
1736 | if (count >= target) | |
1737 | return count; | |
1738 | } | |
1739 | } | |
1740 | ||
1741 | return count; | |
1742 | } | |
1743 | ||
93927ca5 DV |
1744 | static long |
1745 | i915_gem_purge(struct drm_i915_private *dev_priv, long target) | |
1746 | { | |
1747 | return __i915_gem_shrink(dev_priv, target, true); | |
1748 | } | |
1749 | ||
6c085a72 CW |
1750 | static void |
1751 | i915_gem_shrink_all(struct drm_i915_private *dev_priv) | |
1752 | { | |
1753 | struct drm_i915_gem_object *obj, *next; | |
1754 | ||
1755 | i915_gem_evict_everything(dev_priv->dev); | |
1756 | ||
35c20a60 BW |
1757 | list_for_each_entry_safe(obj, next, &dev_priv->mm.unbound_list, |
1758 | global_list) | |
37e680a1 | 1759 | i915_gem_object_put_pages(obj); |
225067ee DV |
1760 | } |
1761 | ||
37e680a1 | 1762 | static int |
6c085a72 | 1763 | i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj) |
e5281ccd | 1764 | { |
6c085a72 | 1765 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
e5281ccd CW |
1766 | int page_count, i; |
1767 | struct address_space *mapping; | |
9da3da66 CW |
1768 | struct sg_table *st; |
1769 | struct scatterlist *sg; | |
90797e6d | 1770 | struct sg_page_iter sg_iter; |
e5281ccd | 1771 | struct page *page; |
90797e6d | 1772 | unsigned long last_pfn = 0; /* suppress gcc warning */ |
6c085a72 | 1773 | gfp_t gfp; |
e5281ccd | 1774 | |
6c085a72 CW |
1775 | /* Assert that the object is not currently in any GPU domain. As it |
1776 | * wasn't in the GTT, there shouldn't be any way it could have been in | |
1777 | * a GPU cache | |
1778 | */ | |
1779 | BUG_ON(obj->base.read_domains & I915_GEM_GPU_DOMAINS); | |
1780 | BUG_ON(obj->base.write_domain & I915_GEM_GPU_DOMAINS); | |
1781 | ||
9da3da66 CW |
1782 | st = kmalloc(sizeof(*st), GFP_KERNEL); |
1783 | if (st == NULL) | |
1784 | return -ENOMEM; | |
1785 | ||
05394f39 | 1786 | page_count = obj->base.size / PAGE_SIZE; |
9da3da66 CW |
1787 | if (sg_alloc_table(st, page_count, GFP_KERNEL)) { |
1788 | sg_free_table(st); | |
1789 | kfree(st); | |
e5281ccd | 1790 | return -ENOMEM; |
9da3da66 | 1791 | } |
e5281ccd | 1792 | |
9da3da66 CW |
1793 | /* Get the list of pages out of our struct file. They'll be pinned |
1794 | * at this point until we release them. | |
1795 | * | |
1796 | * Fail silently without starting the shrinker | |
1797 | */ | |
496ad9aa | 1798 | mapping = file_inode(obj->base.filp)->i_mapping; |
6c085a72 | 1799 | gfp = mapping_gfp_mask(mapping); |
caf49191 | 1800 | gfp |= __GFP_NORETRY | __GFP_NOWARN | __GFP_NO_KSWAPD; |
6c085a72 | 1801 | gfp &= ~(__GFP_IO | __GFP_WAIT); |
90797e6d ID |
1802 | sg = st->sgl; |
1803 | st->nents = 0; | |
1804 | for (i = 0; i < page_count; i++) { | |
6c085a72 CW |
1805 | page = shmem_read_mapping_page_gfp(mapping, i, gfp); |
1806 | if (IS_ERR(page)) { | |
1807 | i915_gem_purge(dev_priv, page_count); | |
1808 | page = shmem_read_mapping_page_gfp(mapping, i, gfp); | |
1809 | } | |
1810 | if (IS_ERR(page)) { | |
1811 | /* We've tried hard to allocate the memory by reaping | |
1812 | * our own buffer, now let the real VM do its job and | |
1813 | * go down in flames if truly OOM. | |
1814 | */ | |
caf49191 | 1815 | gfp &= ~(__GFP_NORETRY | __GFP_NOWARN | __GFP_NO_KSWAPD); |
6c085a72 CW |
1816 | gfp |= __GFP_IO | __GFP_WAIT; |
1817 | ||
1818 | i915_gem_shrink_all(dev_priv); | |
1819 | page = shmem_read_mapping_page_gfp(mapping, i, gfp); | |
1820 | if (IS_ERR(page)) | |
1821 | goto err_pages; | |
1822 | ||
caf49191 | 1823 | gfp |= __GFP_NORETRY | __GFP_NOWARN | __GFP_NO_KSWAPD; |
6c085a72 CW |
1824 | gfp &= ~(__GFP_IO | __GFP_WAIT); |
1825 | } | |
1625e7e5 KRW |
1826 | #ifdef CONFIG_SWIOTLB |
1827 | if (swiotlb_nr_tbl()) { | |
1828 | st->nents++; | |
1829 | sg_set_page(sg, page, PAGE_SIZE, 0); | |
1830 | sg = sg_next(sg); | |
1831 | continue; | |
1832 | } | |
1833 | #endif | |
90797e6d ID |
1834 | if (!i || page_to_pfn(page) != last_pfn + 1) { |
1835 | if (i) | |
1836 | sg = sg_next(sg); | |
1837 | st->nents++; | |
1838 | sg_set_page(sg, page, PAGE_SIZE, 0); | |
1839 | } else { | |
1840 | sg->length += PAGE_SIZE; | |
1841 | } | |
1842 | last_pfn = page_to_pfn(page); | |
e5281ccd | 1843 | } |
1625e7e5 KRW |
1844 | #ifdef CONFIG_SWIOTLB |
1845 | if (!swiotlb_nr_tbl()) | |
1846 | #endif | |
1847 | sg_mark_end(sg); | |
74ce6b6c CW |
1848 | obj->pages = st; |
1849 | ||
6dacfd2f | 1850 | if (i915_gem_object_needs_bit17_swizzle(obj)) |
e5281ccd CW |
1851 | i915_gem_object_do_bit_17_swizzle(obj); |
1852 | ||
1853 | return 0; | |
1854 | ||
1855 | err_pages: | |
90797e6d ID |
1856 | sg_mark_end(sg); |
1857 | for_each_sg_page(st->sgl, &sg_iter, st->nents, 0) | |
2db76d7c | 1858 | page_cache_release(sg_page_iter_page(&sg_iter)); |
9da3da66 CW |
1859 | sg_free_table(st); |
1860 | kfree(st); | |
e5281ccd | 1861 | return PTR_ERR(page); |
673a394b EA |
1862 | } |
1863 | ||
37e680a1 CW |
1864 | /* Ensure that the associated pages are gathered from the backing storage |
1865 | * and pinned into our object. i915_gem_object_get_pages() may be called | |
1866 | * multiple times before they are released by a single call to | |
1867 | * i915_gem_object_put_pages() - once the pages are no longer referenced | |
1868 | * either as a result of memory pressure (reaping pages under the shrinker) | |
1869 | * or as the object is itself released. | |
1870 | */ | |
1871 | int | |
1872 | i915_gem_object_get_pages(struct drm_i915_gem_object *obj) | |
1873 | { | |
1874 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; | |
1875 | const struct drm_i915_gem_object_ops *ops = obj->ops; | |
1876 | int ret; | |
1877 | ||
2f745ad3 | 1878 | if (obj->pages) |
37e680a1 CW |
1879 | return 0; |
1880 | ||
43e28f09 CW |
1881 | if (obj->madv != I915_MADV_WILLNEED) { |
1882 | DRM_ERROR("Attempting to obtain a purgeable object\n"); | |
1883 | return -EINVAL; | |
1884 | } | |
1885 | ||
a5570178 CW |
1886 | BUG_ON(obj->pages_pin_count); |
1887 | ||
37e680a1 CW |
1888 | ret = ops->get_pages(obj); |
1889 | if (ret) | |
1890 | return ret; | |
1891 | ||
35c20a60 | 1892 | list_add_tail(&obj->global_list, &dev_priv->mm.unbound_list); |
37e680a1 | 1893 | return 0; |
673a394b EA |
1894 | } |
1895 | ||
54cf91dc | 1896 | void |
05394f39 | 1897 | i915_gem_object_move_to_active(struct drm_i915_gem_object *obj, |
9d773091 | 1898 | struct intel_ring_buffer *ring) |
673a394b | 1899 | { |
05394f39 | 1900 | struct drm_device *dev = obj->base.dev; |
69dc4987 | 1901 | struct drm_i915_private *dev_priv = dev->dev_private; |
9d773091 | 1902 | u32 seqno = intel_ring_get_seqno(ring); |
617dbe27 | 1903 | |
852835f3 | 1904 | BUG_ON(ring == NULL); |
02978ff5 CW |
1905 | if (obj->ring != ring && obj->last_write_seqno) { |
1906 | /* Keep the seqno relative to the current ring */ | |
1907 | obj->last_write_seqno = seqno; | |
1908 | } | |
05394f39 | 1909 | obj->ring = ring; |
673a394b EA |
1910 | |
1911 | /* Add a reference if we're newly entering the active list. */ | |
05394f39 CW |
1912 | if (!obj->active) { |
1913 | drm_gem_object_reference(&obj->base); | |
1914 | obj->active = 1; | |
673a394b | 1915 | } |
e35a41de | 1916 | |
05394f39 | 1917 | list_move_tail(&obj->ring_list, &ring->active_list); |
caea7476 | 1918 | |
0201f1ec | 1919 | obj->last_read_seqno = seqno; |
caea7476 | 1920 | |
7dd49065 | 1921 | if (obj->fenced_gpu_access) { |
caea7476 | 1922 | obj->last_fenced_seqno = seqno; |
caea7476 | 1923 | |
7dd49065 CW |
1924 | /* Bump MRU to take account of the delayed flush */ |
1925 | if (obj->fence_reg != I915_FENCE_REG_NONE) { | |
1926 | struct drm_i915_fence_reg *reg; | |
1927 | ||
1928 | reg = &dev_priv->fence_regs[obj->fence_reg]; | |
1929 | list_move_tail(®->lru_list, | |
1930 | &dev_priv->mm.fence_list); | |
1931 | } | |
caea7476 CW |
1932 | } |
1933 | } | |
1934 | ||
1935 | static void | |
caea7476 | 1936 | i915_gem_object_move_to_inactive(struct drm_i915_gem_object *obj) |
ce44b0ea | 1937 | { |
ca191b13 BW |
1938 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
1939 | struct i915_address_space *ggtt_vm = &dev_priv->gtt.base; | |
1940 | struct i915_vma *vma = i915_gem_obj_to_vma(obj, ggtt_vm); | |
ce44b0ea | 1941 | |
65ce3027 | 1942 | BUG_ON(obj->base.write_domain & ~I915_GEM_GPU_DOMAINS); |
05394f39 | 1943 | BUG_ON(!obj->active); |
caea7476 | 1944 | |
ca191b13 | 1945 | list_move_tail(&vma->mm_list, &ggtt_vm->inactive_list); |
caea7476 | 1946 | |
65ce3027 | 1947 | list_del_init(&obj->ring_list); |
caea7476 CW |
1948 | obj->ring = NULL; |
1949 | ||
65ce3027 CW |
1950 | obj->last_read_seqno = 0; |
1951 | obj->last_write_seqno = 0; | |
1952 | obj->base.write_domain = 0; | |
1953 | ||
1954 | obj->last_fenced_seqno = 0; | |
caea7476 | 1955 | obj->fenced_gpu_access = false; |
caea7476 CW |
1956 | |
1957 | obj->active = 0; | |
1958 | drm_gem_object_unreference(&obj->base); | |
1959 | ||
1960 | WARN_ON(i915_verify_lists(dev)); | |
ce44b0ea | 1961 | } |
673a394b | 1962 | |
9d773091 | 1963 | static int |
fca26bb4 | 1964 | i915_gem_init_seqno(struct drm_device *dev, u32 seqno) |
53d227f2 | 1965 | { |
9d773091 CW |
1966 | struct drm_i915_private *dev_priv = dev->dev_private; |
1967 | struct intel_ring_buffer *ring; | |
1968 | int ret, i, j; | |
53d227f2 | 1969 | |
107f27a5 | 1970 | /* Carefully retire all requests without writing to the rings */ |
9d773091 | 1971 | for_each_ring(ring, dev_priv, i) { |
107f27a5 CW |
1972 | ret = intel_ring_idle(ring); |
1973 | if (ret) | |
1974 | return ret; | |
9d773091 | 1975 | } |
9d773091 | 1976 | i915_gem_retire_requests(dev); |
107f27a5 CW |
1977 | |
1978 | /* Finally reset hw state */ | |
9d773091 | 1979 | for_each_ring(ring, dev_priv, i) { |
fca26bb4 | 1980 | intel_ring_init_seqno(ring, seqno); |
498d2ac1 | 1981 | |
9d773091 CW |
1982 | for (j = 0; j < ARRAY_SIZE(ring->sync_seqno); j++) |
1983 | ring->sync_seqno[j] = 0; | |
1984 | } | |
53d227f2 | 1985 | |
9d773091 | 1986 | return 0; |
53d227f2 DV |
1987 | } |
1988 | ||
fca26bb4 MK |
1989 | int i915_gem_set_seqno(struct drm_device *dev, u32 seqno) |
1990 | { | |
1991 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1992 | int ret; | |
1993 | ||
1994 | if (seqno == 0) | |
1995 | return -EINVAL; | |
1996 | ||
1997 | /* HWS page needs to be set less than what we | |
1998 | * will inject to ring | |
1999 | */ | |
2000 | ret = i915_gem_init_seqno(dev, seqno - 1); | |
2001 | if (ret) | |
2002 | return ret; | |
2003 | ||
2004 | /* Carefully set the last_seqno value so that wrap | |
2005 | * detection still works | |
2006 | */ | |
2007 | dev_priv->next_seqno = seqno; | |
2008 | dev_priv->last_seqno = seqno - 1; | |
2009 | if (dev_priv->last_seqno == 0) | |
2010 | dev_priv->last_seqno--; | |
2011 | ||
2012 | return 0; | |
2013 | } | |
2014 | ||
9d773091 CW |
2015 | int |
2016 | i915_gem_get_seqno(struct drm_device *dev, u32 *seqno) | |
53d227f2 | 2017 | { |
9d773091 CW |
2018 | struct drm_i915_private *dev_priv = dev->dev_private; |
2019 | ||
2020 | /* reserve 0 for non-seqno */ | |
2021 | if (dev_priv->next_seqno == 0) { | |
fca26bb4 | 2022 | int ret = i915_gem_init_seqno(dev, 0); |
9d773091 CW |
2023 | if (ret) |
2024 | return ret; | |
53d227f2 | 2025 | |
9d773091 CW |
2026 | dev_priv->next_seqno = 1; |
2027 | } | |
53d227f2 | 2028 | |
f72b3435 | 2029 | *seqno = dev_priv->last_seqno = dev_priv->next_seqno++; |
9d773091 | 2030 | return 0; |
53d227f2 DV |
2031 | } |
2032 | ||
0025c077 MK |
2033 | int __i915_add_request(struct intel_ring_buffer *ring, |
2034 | struct drm_file *file, | |
7d736f4f | 2035 | struct drm_i915_gem_object *obj, |
0025c077 | 2036 | u32 *out_seqno) |
673a394b | 2037 | { |
db53a302 | 2038 | drm_i915_private_t *dev_priv = ring->dev->dev_private; |
acb868d3 | 2039 | struct drm_i915_gem_request *request; |
7d736f4f | 2040 | u32 request_ring_position, request_start; |
673a394b | 2041 | int was_empty; |
3cce469c CW |
2042 | int ret; |
2043 | ||
7d736f4f | 2044 | request_start = intel_ring_get_tail(ring); |
cc889e0f DV |
2045 | /* |
2046 | * Emit any outstanding flushes - execbuf can fail to emit the flush | |
2047 | * after having emitted the batchbuffer command. Hence we need to fix | |
2048 | * things up similar to emitting the lazy request. The difference here | |
2049 | * is that the flush _must_ happen before the next request, no matter | |
2050 | * what. | |
2051 | */ | |
a7b9761d CW |
2052 | ret = intel_ring_flush_all_caches(ring); |
2053 | if (ret) | |
2054 | return ret; | |
cc889e0f | 2055 | |
acb868d3 CW |
2056 | request = kmalloc(sizeof(*request), GFP_KERNEL); |
2057 | if (request == NULL) | |
2058 | return -ENOMEM; | |
cc889e0f | 2059 | |
673a394b | 2060 | |
a71d8d94 CW |
2061 | /* Record the position of the start of the request so that |
2062 | * should we detect the updated seqno part-way through the | |
2063 | * GPU processing the request, we never over-estimate the | |
2064 | * position of the head. | |
2065 | */ | |
2066 | request_ring_position = intel_ring_get_tail(ring); | |
2067 | ||
9d773091 | 2068 | ret = ring->add_request(ring); |
3bb73aba CW |
2069 | if (ret) { |
2070 | kfree(request); | |
2071 | return ret; | |
2072 | } | |
673a394b | 2073 | |
9d773091 | 2074 | request->seqno = intel_ring_get_seqno(ring); |
852835f3 | 2075 | request->ring = ring; |
7d736f4f | 2076 | request->head = request_start; |
a71d8d94 | 2077 | request->tail = request_ring_position; |
0e50e96b | 2078 | request->ctx = ring->last_context; |
7d736f4f MK |
2079 | request->batch_obj = obj; |
2080 | ||
2081 | /* Whilst this request exists, batch_obj will be on the | |
2082 | * active_list, and so will hold the active reference. Only when this | |
2083 | * request is retired will the the batch_obj be moved onto the | |
2084 | * inactive_list and lose its active reference. Hence we do not need | |
2085 | * to explicitly hold another reference here. | |
2086 | */ | |
0e50e96b MK |
2087 | |
2088 | if (request->ctx) | |
2089 | i915_gem_context_reference(request->ctx); | |
2090 | ||
673a394b | 2091 | request->emitted_jiffies = jiffies; |
852835f3 ZN |
2092 | was_empty = list_empty(&ring->request_list); |
2093 | list_add_tail(&request->list, &ring->request_list); | |
3bb73aba | 2094 | request->file_priv = NULL; |
852835f3 | 2095 | |
db53a302 CW |
2096 | if (file) { |
2097 | struct drm_i915_file_private *file_priv = file->driver_priv; | |
2098 | ||
1c25595f | 2099 | spin_lock(&file_priv->mm.lock); |
f787a5f5 | 2100 | request->file_priv = file_priv; |
b962442e | 2101 | list_add_tail(&request->client_list, |
f787a5f5 | 2102 | &file_priv->mm.request_list); |
1c25595f | 2103 | spin_unlock(&file_priv->mm.lock); |
b962442e | 2104 | } |
673a394b | 2105 | |
9d773091 | 2106 | trace_i915_gem_request_add(ring, request->seqno); |
5391d0cf | 2107 | ring->outstanding_lazy_request = 0; |
db53a302 | 2108 | |
db1b76ca | 2109 | if (!dev_priv->ums.mm_suspended) { |
10cd45b6 MK |
2110 | i915_queue_hangcheck(ring->dev); |
2111 | ||
f047e395 | 2112 | if (was_empty) { |
b3b079db | 2113 | queue_delayed_work(dev_priv->wq, |
bcb45086 CW |
2114 | &dev_priv->mm.retire_work, |
2115 | round_jiffies_up_relative(HZ)); | |
f047e395 CW |
2116 | intel_mark_busy(dev_priv->dev); |
2117 | } | |
f65d9421 | 2118 | } |
cc889e0f | 2119 | |
acb868d3 | 2120 | if (out_seqno) |
9d773091 | 2121 | *out_seqno = request->seqno; |
3cce469c | 2122 | return 0; |
673a394b EA |
2123 | } |
2124 | ||
f787a5f5 CW |
2125 | static inline void |
2126 | i915_gem_request_remove_from_client(struct drm_i915_gem_request *request) | |
673a394b | 2127 | { |
1c25595f | 2128 | struct drm_i915_file_private *file_priv = request->file_priv; |
673a394b | 2129 | |
1c25595f CW |
2130 | if (!file_priv) |
2131 | return; | |
1c5d22f7 | 2132 | |
1c25595f | 2133 | spin_lock(&file_priv->mm.lock); |
09bfa517 HRK |
2134 | if (request->file_priv) { |
2135 | list_del(&request->client_list); | |
2136 | request->file_priv = NULL; | |
2137 | } | |
1c25595f | 2138 | spin_unlock(&file_priv->mm.lock); |
673a394b | 2139 | } |
673a394b | 2140 | |
d1ccbb5d BW |
2141 | static bool i915_head_inside_object(u32 acthd, struct drm_i915_gem_object *obj, |
2142 | struct i915_address_space *vm) | |
aa60c664 | 2143 | { |
d1ccbb5d BW |
2144 | if (acthd >= i915_gem_obj_offset(obj, vm) && |
2145 | acthd < i915_gem_obj_offset(obj, vm) + obj->base.size) | |
aa60c664 MK |
2146 | return true; |
2147 | ||
2148 | return false; | |
2149 | } | |
2150 | ||
2151 | static bool i915_head_inside_request(const u32 acthd_unmasked, | |
2152 | const u32 request_start, | |
2153 | const u32 request_end) | |
2154 | { | |
2155 | const u32 acthd = acthd_unmasked & HEAD_ADDR; | |
2156 | ||
2157 | if (request_start < request_end) { | |
2158 | if (acthd >= request_start && acthd < request_end) | |
2159 | return true; | |
2160 | } else if (request_start > request_end) { | |
2161 | if (acthd >= request_start || acthd < request_end) | |
2162 | return true; | |
2163 | } | |
2164 | ||
2165 | return false; | |
2166 | } | |
2167 | ||
d1ccbb5d BW |
2168 | static struct i915_address_space * |
2169 | request_to_vm(struct drm_i915_gem_request *request) | |
2170 | { | |
2171 | struct drm_i915_private *dev_priv = request->ring->dev->dev_private; | |
2172 | struct i915_address_space *vm; | |
2173 | ||
2174 | vm = &dev_priv->gtt.base; | |
2175 | ||
2176 | return vm; | |
2177 | } | |
2178 | ||
aa60c664 MK |
2179 | static bool i915_request_guilty(struct drm_i915_gem_request *request, |
2180 | const u32 acthd, bool *inside) | |
2181 | { | |
2182 | /* There is a possibility that unmasked head address | |
2183 | * pointing inside the ring, matches the batch_obj address range. | |
2184 | * However this is extremely unlikely. | |
2185 | */ | |
aa60c664 | 2186 | if (request->batch_obj) { |
d1ccbb5d BW |
2187 | if (i915_head_inside_object(acthd, request->batch_obj, |
2188 | request_to_vm(request))) { | |
aa60c664 MK |
2189 | *inside = true; |
2190 | return true; | |
2191 | } | |
2192 | } | |
2193 | ||
2194 | if (i915_head_inside_request(acthd, request->head, request->tail)) { | |
2195 | *inside = false; | |
2196 | return true; | |
2197 | } | |
2198 | ||
2199 | return false; | |
2200 | } | |
2201 | ||
2202 | static void i915_set_reset_status(struct intel_ring_buffer *ring, | |
2203 | struct drm_i915_gem_request *request, | |
2204 | u32 acthd) | |
2205 | { | |
2206 | struct i915_ctx_hang_stats *hs = NULL; | |
2207 | bool inside, guilty; | |
d1ccbb5d | 2208 | unsigned long offset = 0; |
aa60c664 MK |
2209 | |
2210 | /* Innocent until proven guilty */ | |
2211 | guilty = false; | |
2212 | ||
d1ccbb5d BW |
2213 | if (request->batch_obj) |
2214 | offset = i915_gem_obj_offset(request->batch_obj, | |
2215 | request_to_vm(request)); | |
2216 | ||
f2f4d82f | 2217 | if (ring->hangcheck.action != HANGCHECK_WAIT && |
aa60c664 | 2218 | i915_request_guilty(request, acthd, &inside)) { |
f343c5f6 | 2219 | DRM_ERROR("%s hung %s bo (0x%lx ctx %d) at 0x%x\n", |
aa60c664 MK |
2220 | ring->name, |
2221 | inside ? "inside" : "flushing", | |
d1ccbb5d | 2222 | offset, |
aa60c664 MK |
2223 | request->ctx ? request->ctx->id : 0, |
2224 | acthd); | |
2225 | ||
2226 | guilty = true; | |
2227 | } | |
2228 | ||
2229 | /* If contexts are disabled or this is the default context, use | |
2230 | * file_priv->reset_state | |
2231 | */ | |
2232 | if (request->ctx && request->ctx->id != DEFAULT_CONTEXT_ID) | |
2233 | hs = &request->ctx->hang_stats; | |
2234 | else if (request->file_priv) | |
2235 | hs = &request->file_priv->hang_stats; | |
2236 | ||
2237 | if (hs) { | |
2238 | if (guilty) | |
2239 | hs->batch_active++; | |
2240 | else | |
2241 | hs->batch_pending++; | |
2242 | } | |
2243 | } | |
2244 | ||
0e50e96b MK |
2245 | static void i915_gem_free_request(struct drm_i915_gem_request *request) |
2246 | { | |
2247 | list_del(&request->list); | |
2248 | i915_gem_request_remove_from_client(request); | |
2249 | ||
2250 | if (request->ctx) | |
2251 | i915_gem_context_unreference(request->ctx); | |
2252 | ||
2253 | kfree(request); | |
2254 | } | |
2255 | ||
dfaae392 CW |
2256 | static void i915_gem_reset_ring_lists(struct drm_i915_private *dev_priv, |
2257 | struct intel_ring_buffer *ring) | |
9375e446 | 2258 | { |
aa60c664 MK |
2259 | u32 completed_seqno; |
2260 | u32 acthd; | |
2261 | ||
2262 | acthd = intel_ring_get_active_head(ring); | |
2263 | completed_seqno = ring->get_seqno(ring, false); | |
2264 | ||
dfaae392 CW |
2265 | while (!list_empty(&ring->request_list)) { |
2266 | struct drm_i915_gem_request *request; | |
673a394b | 2267 | |
dfaae392 CW |
2268 | request = list_first_entry(&ring->request_list, |
2269 | struct drm_i915_gem_request, | |
2270 | list); | |
de151cf6 | 2271 | |
aa60c664 MK |
2272 | if (request->seqno > completed_seqno) |
2273 | i915_set_reset_status(ring, request, acthd); | |
2274 | ||
0e50e96b | 2275 | i915_gem_free_request(request); |
dfaae392 | 2276 | } |
673a394b | 2277 | |
dfaae392 | 2278 | while (!list_empty(&ring->active_list)) { |
05394f39 | 2279 | struct drm_i915_gem_object *obj; |
9375e446 | 2280 | |
05394f39 CW |
2281 | obj = list_first_entry(&ring->active_list, |
2282 | struct drm_i915_gem_object, | |
2283 | ring_list); | |
9375e446 | 2284 | |
05394f39 | 2285 | i915_gem_object_move_to_inactive(obj); |
673a394b EA |
2286 | } |
2287 | } | |
2288 | ||
19b2dbde | 2289 | void i915_gem_restore_fences(struct drm_device *dev) |
312817a3 CW |
2290 | { |
2291 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2292 | int i; | |
2293 | ||
4b9de737 | 2294 | for (i = 0; i < dev_priv->num_fence_regs; i++) { |
312817a3 | 2295 | struct drm_i915_fence_reg *reg = &dev_priv->fence_regs[i]; |
7d2cb39c | 2296 | |
94a335db DV |
2297 | /* |
2298 | * Commit delayed tiling changes if we have an object still | |
2299 | * attached to the fence, otherwise just clear the fence. | |
2300 | */ | |
2301 | if (reg->obj) { | |
2302 | i915_gem_object_update_fence(reg->obj, reg, | |
2303 | reg->obj->tiling_mode); | |
2304 | } else { | |
2305 | i915_gem_write_fence(dev, i, NULL); | |
2306 | } | |
312817a3 CW |
2307 | } |
2308 | } | |
2309 | ||
069efc1d | 2310 | void i915_gem_reset(struct drm_device *dev) |
673a394b | 2311 | { |
77f01230 | 2312 | struct drm_i915_private *dev_priv = dev->dev_private; |
b4519513 | 2313 | struct intel_ring_buffer *ring; |
1ec14ad3 | 2314 | int i; |
673a394b | 2315 | |
b4519513 CW |
2316 | for_each_ring(ring, dev_priv, i) |
2317 | i915_gem_reset_ring_lists(dev_priv, ring); | |
dfaae392 | 2318 | |
19b2dbde | 2319 | i915_gem_restore_fences(dev); |
673a394b EA |
2320 | } |
2321 | ||
2322 | /** | |
2323 | * This function clears the request list as sequence numbers are passed. | |
2324 | */ | |
a71d8d94 | 2325 | void |
db53a302 | 2326 | i915_gem_retire_requests_ring(struct intel_ring_buffer *ring) |
673a394b | 2327 | { |
673a394b EA |
2328 | uint32_t seqno; |
2329 | ||
db53a302 | 2330 | if (list_empty(&ring->request_list)) |
6c0594a3 KW |
2331 | return; |
2332 | ||
db53a302 | 2333 | WARN_ON(i915_verify_lists(ring->dev)); |
673a394b | 2334 | |
b2eadbc8 | 2335 | seqno = ring->get_seqno(ring, true); |
1ec14ad3 | 2336 | |
852835f3 | 2337 | while (!list_empty(&ring->request_list)) { |
673a394b | 2338 | struct drm_i915_gem_request *request; |
673a394b | 2339 | |
852835f3 | 2340 | request = list_first_entry(&ring->request_list, |
673a394b EA |
2341 | struct drm_i915_gem_request, |
2342 | list); | |
673a394b | 2343 | |
dfaae392 | 2344 | if (!i915_seqno_passed(seqno, request->seqno)) |
b84d5f0c CW |
2345 | break; |
2346 | ||
db53a302 | 2347 | trace_i915_gem_request_retire(ring, request->seqno); |
a71d8d94 CW |
2348 | /* We know the GPU must have read the request to have |
2349 | * sent us the seqno + interrupt, so use the position | |
2350 | * of tail of the request to update the last known position | |
2351 | * of the GPU head. | |
2352 | */ | |
2353 | ring->last_retired_head = request->tail; | |
b84d5f0c | 2354 | |
0e50e96b | 2355 | i915_gem_free_request(request); |
b84d5f0c | 2356 | } |
673a394b | 2357 | |
b84d5f0c CW |
2358 | /* Move any buffers on the active list that are no longer referenced |
2359 | * by the ringbuffer to the flushing/inactive lists as appropriate. | |
2360 | */ | |
2361 | while (!list_empty(&ring->active_list)) { | |
05394f39 | 2362 | struct drm_i915_gem_object *obj; |
b84d5f0c | 2363 | |
0206e353 | 2364 | obj = list_first_entry(&ring->active_list, |
05394f39 CW |
2365 | struct drm_i915_gem_object, |
2366 | ring_list); | |
673a394b | 2367 | |
0201f1ec | 2368 | if (!i915_seqno_passed(seqno, obj->last_read_seqno)) |
673a394b | 2369 | break; |
b84d5f0c | 2370 | |
65ce3027 | 2371 | i915_gem_object_move_to_inactive(obj); |
673a394b | 2372 | } |
9d34e5db | 2373 | |
db53a302 CW |
2374 | if (unlikely(ring->trace_irq_seqno && |
2375 | i915_seqno_passed(seqno, ring->trace_irq_seqno))) { | |
1ec14ad3 | 2376 | ring->irq_put(ring); |
db53a302 | 2377 | ring->trace_irq_seqno = 0; |
9d34e5db | 2378 | } |
23bc5982 | 2379 | |
db53a302 | 2380 | WARN_ON(i915_verify_lists(ring->dev)); |
673a394b EA |
2381 | } |
2382 | ||
b09a1fec CW |
2383 | void |
2384 | i915_gem_retire_requests(struct drm_device *dev) | |
2385 | { | |
2386 | drm_i915_private_t *dev_priv = dev->dev_private; | |
b4519513 | 2387 | struct intel_ring_buffer *ring; |
1ec14ad3 | 2388 | int i; |
b09a1fec | 2389 | |
b4519513 CW |
2390 | for_each_ring(ring, dev_priv, i) |
2391 | i915_gem_retire_requests_ring(ring); | |
b09a1fec CW |
2392 | } |
2393 | ||
75ef9da2 | 2394 | static void |
673a394b EA |
2395 | i915_gem_retire_work_handler(struct work_struct *work) |
2396 | { | |
2397 | drm_i915_private_t *dev_priv; | |
2398 | struct drm_device *dev; | |
b4519513 | 2399 | struct intel_ring_buffer *ring; |
0a58705b CW |
2400 | bool idle; |
2401 | int i; | |
673a394b EA |
2402 | |
2403 | dev_priv = container_of(work, drm_i915_private_t, | |
2404 | mm.retire_work.work); | |
2405 | dev = dev_priv->dev; | |
2406 | ||
891b48cf CW |
2407 | /* Come back later if the device is busy... */ |
2408 | if (!mutex_trylock(&dev->struct_mutex)) { | |
bcb45086 CW |
2409 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, |
2410 | round_jiffies_up_relative(HZ)); | |
891b48cf CW |
2411 | return; |
2412 | } | |
673a394b | 2413 | |
b09a1fec | 2414 | i915_gem_retire_requests(dev); |
673a394b | 2415 | |
0a58705b CW |
2416 | /* Send a periodic flush down the ring so we don't hold onto GEM |
2417 | * objects indefinitely. | |
673a394b | 2418 | */ |
0a58705b | 2419 | idle = true; |
b4519513 | 2420 | for_each_ring(ring, dev_priv, i) { |
3bb73aba | 2421 | if (ring->gpu_caches_dirty) |
0025c077 | 2422 | i915_add_request(ring, NULL); |
0a58705b CW |
2423 | |
2424 | idle &= list_empty(&ring->request_list); | |
673a394b EA |
2425 | } |
2426 | ||
db1b76ca | 2427 | if (!dev_priv->ums.mm_suspended && !idle) |
bcb45086 CW |
2428 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, |
2429 | round_jiffies_up_relative(HZ)); | |
f047e395 CW |
2430 | if (idle) |
2431 | intel_mark_idle(dev); | |
0a58705b | 2432 | |
673a394b | 2433 | mutex_unlock(&dev->struct_mutex); |
673a394b EA |
2434 | } |
2435 | ||
30dfebf3 DV |
2436 | /** |
2437 | * Ensures that an object will eventually get non-busy by flushing any required | |
2438 | * write domains, emitting any outstanding lazy request and retiring and | |
2439 | * completed requests. | |
2440 | */ | |
2441 | static int | |
2442 | i915_gem_object_flush_active(struct drm_i915_gem_object *obj) | |
2443 | { | |
2444 | int ret; | |
2445 | ||
2446 | if (obj->active) { | |
0201f1ec | 2447 | ret = i915_gem_check_olr(obj->ring, obj->last_read_seqno); |
30dfebf3 DV |
2448 | if (ret) |
2449 | return ret; | |
2450 | ||
30dfebf3 DV |
2451 | i915_gem_retire_requests_ring(obj->ring); |
2452 | } | |
2453 | ||
2454 | return 0; | |
2455 | } | |
2456 | ||
23ba4fd0 BW |
2457 | /** |
2458 | * i915_gem_wait_ioctl - implements DRM_IOCTL_I915_GEM_WAIT | |
2459 | * @DRM_IOCTL_ARGS: standard ioctl arguments | |
2460 | * | |
2461 | * Returns 0 if successful, else an error is returned with the remaining time in | |
2462 | * the timeout parameter. | |
2463 | * -ETIME: object is still busy after timeout | |
2464 | * -ERESTARTSYS: signal interrupted the wait | |
2465 | * -ENONENT: object doesn't exist | |
2466 | * Also possible, but rare: | |
2467 | * -EAGAIN: GPU wedged | |
2468 | * -ENOMEM: damn | |
2469 | * -ENODEV: Internal IRQ fail | |
2470 | * -E?: The add request failed | |
2471 | * | |
2472 | * The wait ioctl with a timeout of 0 reimplements the busy ioctl. With any | |
2473 | * non-zero timeout parameter the wait ioctl will wait for the given number of | |
2474 | * nanoseconds on an object becoming unbusy. Since the wait itself does so | |
2475 | * without holding struct_mutex the object may become re-busied before this | |
2476 | * function completes. A similar but shorter * race condition exists in the busy | |
2477 | * ioctl | |
2478 | */ | |
2479 | int | |
2480 | i915_gem_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *file) | |
2481 | { | |
f69061be | 2482 | drm_i915_private_t *dev_priv = dev->dev_private; |
23ba4fd0 BW |
2483 | struct drm_i915_gem_wait *args = data; |
2484 | struct drm_i915_gem_object *obj; | |
2485 | struct intel_ring_buffer *ring = NULL; | |
eac1f14f | 2486 | struct timespec timeout_stack, *timeout = NULL; |
f69061be | 2487 | unsigned reset_counter; |
23ba4fd0 BW |
2488 | u32 seqno = 0; |
2489 | int ret = 0; | |
2490 | ||
eac1f14f BW |
2491 | if (args->timeout_ns >= 0) { |
2492 | timeout_stack = ns_to_timespec(args->timeout_ns); | |
2493 | timeout = &timeout_stack; | |
2494 | } | |
23ba4fd0 BW |
2495 | |
2496 | ret = i915_mutex_lock_interruptible(dev); | |
2497 | if (ret) | |
2498 | return ret; | |
2499 | ||
2500 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->bo_handle)); | |
2501 | if (&obj->base == NULL) { | |
2502 | mutex_unlock(&dev->struct_mutex); | |
2503 | return -ENOENT; | |
2504 | } | |
2505 | ||
30dfebf3 DV |
2506 | /* Need to make sure the object gets inactive eventually. */ |
2507 | ret = i915_gem_object_flush_active(obj); | |
23ba4fd0 BW |
2508 | if (ret) |
2509 | goto out; | |
2510 | ||
2511 | if (obj->active) { | |
0201f1ec | 2512 | seqno = obj->last_read_seqno; |
23ba4fd0 BW |
2513 | ring = obj->ring; |
2514 | } | |
2515 | ||
2516 | if (seqno == 0) | |
2517 | goto out; | |
2518 | ||
23ba4fd0 BW |
2519 | /* Do this after OLR check to make sure we make forward progress polling |
2520 | * on this IOCTL with a 0 timeout (like busy ioctl) | |
2521 | */ | |
2522 | if (!args->timeout_ns) { | |
2523 | ret = -ETIME; | |
2524 | goto out; | |
2525 | } | |
2526 | ||
2527 | drm_gem_object_unreference(&obj->base); | |
f69061be | 2528 | reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter); |
23ba4fd0 BW |
2529 | mutex_unlock(&dev->struct_mutex); |
2530 | ||
f69061be | 2531 | ret = __wait_seqno(ring, seqno, reset_counter, true, timeout); |
4f42f4ef | 2532 | if (timeout) |
eac1f14f | 2533 | args->timeout_ns = timespec_to_ns(timeout); |
23ba4fd0 BW |
2534 | return ret; |
2535 | ||
2536 | out: | |
2537 | drm_gem_object_unreference(&obj->base); | |
2538 | mutex_unlock(&dev->struct_mutex); | |
2539 | return ret; | |
2540 | } | |
2541 | ||
5816d648 BW |
2542 | /** |
2543 | * i915_gem_object_sync - sync an object to a ring. | |
2544 | * | |
2545 | * @obj: object which may be in use on another ring. | |
2546 | * @to: ring we wish to use the object on. May be NULL. | |
2547 | * | |
2548 | * This code is meant to abstract object synchronization with the GPU. | |
2549 | * Calling with NULL implies synchronizing the object with the CPU | |
2550 | * rather than a particular GPU ring. | |
2551 | * | |
2552 | * Returns 0 if successful, else propagates up the lower layer error. | |
2553 | */ | |
2911a35b BW |
2554 | int |
2555 | i915_gem_object_sync(struct drm_i915_gem_object *obj, | |
2556 | struct intel_ring_buffer *to) | |
2557 | { | |
2558 | struct intel_ring_buffer *from = obj->ring; | |
2559 | u32 seqno; | |
2560 | int ret, idx; | |
2561 | ||
2562 | if (from == NULL || to == from) | |
2563 | return 0; | |
2564 | ||
5816d648 | 2565 | if (to == NULL || !i915_semaphore_is_enabled(obj->base.dev)) |
0201f1ec | 2566 | return i915_gem_object_wait_rendering(obj, false); |
2911a35b BW |
2567 | |
2568 | idx = intel_ring_sync_index(from, to); | |
2569 | ||
0201f1ec | 2570 | seqno = obj->last_read_seqno; |
2911a35b BW |
2571 | if (seqno <= from->sync_seqno[idx]) |
2572 | return 0; | |
2573 | ||
b4aca010 BW |
2574 | ret = i915_gem_check_olr(obj->ring, seqno); |
2575 | if (ret) | |
2576 | return ret; | |
2911a35b | 2577 | |
1500f7ea | 2578 | ret = to->sync_to(to, from, seqno); |
e3a5a225 | 2579 | if (!ret) |
7b01e260 MK |
2580 | /* We use last_read_seqno because sync_to() |
2581 | * might have just caused seqno wrap under | |
2582 | * the radar. | |
2583 | */ | |
2584 | from->sync_seqno[idx] = obj->last_read_seqno; | |
2911a35b | 2585 | |
e3a5a225 | 2586 | return ret; |
2911a35b BW |
2587 | } |
2588 | ||
b5ffc9bc CW |
2589 | static void i915_gem_object_finish_gtt(struct drm_i915_gem_object *obj) |
2590 | { | |
2591 | u32 old_write_domain, old_read_domains; | |
2592 | ||
b5ffc9bc CW |
2593 | /* Force a pagefault for domain tracking on next user access */ |
2594 | i915_gem_release_mmap(obj); | |
2595 | ||
b97c3d9c KP |
2596 | if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0) |
2597 | return; | |
2598 | ||
97c809fd CW |
2599 | /* Wait for any direct GTT access to complete */ |
2600 | mb(); | |
2601 | ||
b5ffc9bc CW |
2602 | old_read_domains = obj->base.read_domains; |
2603 | old_write_domain = obj->base.write_domain; | |
2604 | ||
2605 | obj->base.read_domains &= ~I915_GEM_DOMAIN_GTT; | |
2606 | obj->base.write_domain &= ~I915_GEM_DOMAIN_GTT; | |
2607 | ||
2608 | trace_i915_gem_object_change_domain(obj, | |
2609 | old_read_domains, | |
2610 | old_write_domain); | |
2611 | } | |
2612 | ||
07fe0b12 | 2613 | int i915_vma_unbind(struct i915_vma *vma) |
673a394b | 2614 | { |
07fe0b12 | 2615 | struct drm_i915_gem_object *obj = vma->obj; |
7bddb01f | 2616 | drm_i915_private_t *dev_priv = obj->base.dev->dev_private; |
43e28f09 | 2617 | int ret; |
673a394b | 2618 | |
07fe0b12 | 2619 | if (list_empty(&vma->vma_link)) |
673a394b EA |
2620 | return 0; |
2621 | ||
31d8d651 CW |
2622 | if (obj->pin_count) |
2623 | return -EBUSY; | |
673a394b | 2624 | |
c4670ad0 CW |
2625 | BUG_ON(obj->pages == NULL); |
2626 | ||
a8198eea | 2627 | ret = i915_gem_object_finish_gpu(obj); |
1488fc08 | 2628 | if (ret) |
a8198eea CW |
2629 | return ret; |
2630 | /* Continue on if we fail due to EIO, the GPU is hung so we | |
2631 | * should be safe and we need to cleanup or else we might | |
2632 | * cause memory corruption through use-after-free. | |
2633 | */ | |
2634 | ||
b5ffc9bc | 2635 | i915_gem_object_finish_gtt(obj); |
5323fd04 | 2636 | |
96b47b65 | 2637 | /* release the fence reg _after_ flushing */ |
d9e86c0e | 2638 | ret = i915_gem_object_put_fence(obj); |
1488fc08 | 2639 | if (ret) |
d9e86c0e | 2640 | return ret; |
96b47b65 | 2641 | |
07fe0b12 | 2642 | trace_i915_vma_unbind(vma); |
db53a302 | 2643 | |
74898d7e DV |
2644 | if (obj->has_global_gtt_mapping) |
2645 | i915_gem_gtt_unbind_object(obj); | |
7bddb01f DV |
2646 | if (obj->has_aliasing_ppgtt_mapping) { |
2647 | i915_ppgtt_unbind_object(dev_priv->mm.aliasing_ppgtt, obj); | |
2648 | obj->has_aliasing_ppgtt_mapping = 0; | |
2649 | } | |
74163907 | 2650 | i915_gem_gtt_finish_object(obj); |
401c29f6 | 2651 | i915_gem_object_unpin_pages(obj); |
7bddb01f | 2652 | |
ca191b13 | 2653 | list_del(&vma->mm_list); |
75e9e915 | 2654 | /* Avoid an unnecessary call to unbind on rebind. */ |
5cacaac7 BW |
2655 | if (i915_is_ggtt(vma->vm)) |
2656 | obj->map_and_fenceable = true; | |
673a394b | 2657 | |
2f633156 BW |
2658 | drm_mm_remove_node(&vma->node); |
2659 | i915_gem_vma_destroy(vma); | |
2660 | ||
2661 | /* Since the unbound list is global, only move to that list if | |
2662 | * no more VMAs exist. | |
2663 | * NB: Until we have real VMAs there will only ever be one */ | |
2664 | WARN_ON(!list_empty(&obj->vma_list)); | |
2665 | if (list_empty(&obj->vma_list)) | |
2666 | list_move_tail(&obj->global_list, &dev_priv->mm.unbound_list); | |
673a394b | 2667 | |
88241785 | 2668 | return 0; |
54cf91dc CW |
2669 | } |
2670 | ||
07fe0b12 BW |
2671 | /** |
2672 | * Unbinds an object from the global GTT aperture. | |
2673 | */ | |
2674 | int | |
2675 | i915_gem_object_ggtt_unbind(struct drm_i915_gem_object *obj) | |
2676 | { | |
2677 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; | |
2678 | struct i915_address_space *ggtt = &dev_priv->gtt.base; | |
2679 | ||
58e73e15 | 2680 | if (!i915_gem_obj_ggtt_bound(obj)) |
07fe0b12 BW |
2681 | return 0; |
2682 | ||
2683 | if (obj->pin_count) | |
2684 | return -EBUSY; | |
2685 | ||
2686 | BUG_ON(obj->pages == NULL); | |
2687 | ||
2688 | return i915_vma_unbind(i915_gem_obj_to_vma(obj, ggtt)); | |
2689 | } | |
2690 | ||
b2da9fe5 | 2691 | int i915_gpu_idle(struct drm_device *dev) |
4df2faf4 DV |
2692 | { |
2693 | drm_i915_private_t *dev_priv = dev->dev_private; | |
b4519513 | 2694 | struct intel_ring_buffer *ring; |
1ec14ad3 | 2695 | int ret, i; |
4df2faf4 | 2696 | |
4df2faf4 | 2697 | /* Flush everything onto the inactive list. */ |
b4519513 | 2698 | for_each_ring(ring, dev_priv, i) { |
b6c7488d BW |
2699 | ret = i915_switch_context(ring, NULL, DEFAULT_CONTEXT_ID); |
2700 | if (ret) | |
2701 | return ret; | |
2702 | ||
3e960501 | 2703 | ret = intel_ring_idle(ring); |
1ec14ad3 CW |
2704 | if (ret) |
2705 | return ret; | |
2706 | } | |
4df2faf4 | 2707 | |
8a1a49f9 | 2708 | return 0; |
4df2faf4 DV |
2709 | } |
2710 | ||
9ce079e4 CW |
2711 | static void i965_write_fence_reg(struct drm_device *dev, int reg, |
2712 | struct drm_i915_gem_object *obj) | |
de151cf6 | 2713 | { |
de151cf6 | 2714 | drm_i915_private_t *dev_priv = dev->dev_private; |
56c844e5 ID |
2715 | int fence_reg; |
2716 | int fence_pitch_shift; | |
de151cf6 | 2717 | |
56c844e5 ID |
2718 | if (INTEL_INFO(dev)->gen >= 6) { |
2719 | fence_reg = FENCE_REG_SANDYBRIDGE_0; | |
2720 | fence_pitch_shift = SANDYBRIDGE_FENCE_PITCH_SHIFT; | |
2721 | } else { | |
2722 | fence_reg = FENCE_REG_965_0; | |
2723 | fence_pitch_shift = I965_FENCE_PITCH_SHIFT; | |
2724 | } | |
2725 | ||
d18b9619 CW |
2726 | fence_reg += reg * 8; |
2727 | ||
2728 | /* To w/a incoherency with non-atomic 64-bit register updates, | |
2729 | * we split the 64-bit update into two 32-bit writes. In order | |
2730 | * for a partial fence not to be evaluated between writes, we | |
2731 | * precede the update with write to turn off the fence register, | |
2732 | * and only enable the fence as the last step. | |
2733 | * | |
2734 | * For extra levels of paranoia, we make sure each step lands | |
2735 | * before applying the next step. | |
2736 | */ | |
2737 | I915_WRITE(fence_reg, 0); | |
2738 | POSTING_READ(fence_reg); | |
2739 | ||
9ce079e4 | 2740 | if (obj) { |
f343c5f6 | 2741 | u32 size = i915_gem_obj_ggtt_size(obj); |
d18b9619 | 2742 | uint64_t val; |
de151cf6 | 2743 | |
f343c5f6 | 2744 | val = (uint64_t)((i915_gem_obj_ggtt_offset(obj) + size - 4096) & |
9ce079e4 | 2745 | 0xfffff000) << 32; |
f343c5f6 | 2746 | val |= i915_gem_obj_ggtt_offset(obj) & 0xfffff000; |
56c844e5 | 2747 | val |= (uint64_t)((obj->stride / 128) - 1) << fence_pitch_shift; |
9ce079e4 CW |
2748 | if (obj->tiling_mode == I915_TILING_Y) |
2749 | val |= 1 << I965_FENCE_TILING_Y_SHIFT; | |
2750 | val |= I965_FENCE_REG_VALID; | |
c6642782 | 2751 | |
d18b9619 CW |
2752 | I915_WRITE(fence_reg + 4, val >> 32); |
2753 | POSTING_READ(fence_reg + 4); | |
2754 | ||
2755 | I915_WRITE(fence_reg + 0, val); | |
2756 | POSTING_READ(fence_reg); | |
2757 | } else { | |
2758 | I915_WRITE(fence_reg + 4, 0); | |
2759 | POSTING_READ(fence_reg + 4); | |
2760 | } | |
de151cf6 JB |
2761 | } |
2762 | ||
9ce079e4 CW |
2763 | static void i915_write_fence_reg(struct drm_device *dev, int reg, |
2764 | struct drm_i915_gem_object *obj) | |
de151cf6 | 2765 | { |
de151cf6 | 2766 | drm_i915_private_t *dev_priv = dev->dev_private; |
9ce079e4 | 2767 | u32 val; |
de151cf6 | 2768 | |
9ce079e4 | 2769 | if (obj) { |
f343c5f6 | 2770 | u32 size = i915_gem_obj_ggtt_size(obj); |
9ce079e4 CW |
2771 | int pitch_val; |
2772 | int tile_width; | |
c6642782 | 2773 | |
f343c5f6 | 2774 | WARN((i915_gem_obj_ggtt_offset(obj) & ~I915_FENCE_START_MASK) || |
9ce079e4 | 2775 | (size & -size) != size || |
f343c5f6 BW |
2776 | (i915_gem_obj_ggtt_offset(obj) & (size - 1)), |
2777 | "object 0x%08lx [fenceable? %d] not 1M or pot-size (0x%08x) aligned\n", | |
2778 | i915_gem_obj_ggtt_offset(obj), obj->map_and_fenceable, size); | |
c6642782 | 2779 | |
9ce079e4 CW |
2780 | if (obj->tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev)) |
2781 | tile_width = 128; | |
2782 | else | |
2783 | tile_width = 512; | |
2784 | ||
2785 | /* Note: pitch better be a power of two tile widths */ | |
2786 | pitch_val = obj->stride / tile_width; | |
2787 | pitch_val = ffs(pitch_val) - 1; | |
2788 | ||
f343c5f6 | 2789 | val = i915_gem_obj_ggtt_offset(obj); |
9ce079e4 CW |
2790 | if (obj->tiling_mode == I915_TILING_Y) |
2791 | val |= 1 << I830_FENCE_TILING_Y_SHIFT; | |
2792 | val |= I915_FENCE_SIZE_BITS(size); | |
2793 | val |= pitch_val << I830_FENCE_PITCH_SHIFT; | |
2794 | val |= I830_FENCE_REG_VALID; | |
2795 | } else | |
2796 | val = 0; | |
2797 | ||
2798 | if (reg < 8) | |
2799 | reg = FENCE_REG_830_0 + reg * 4; | |
2800 | else | |
2801 | reg = FENCE_REG_945_8 + (reg - 8) * 4; | |
2802 | ||
2803 | I915_WRITE(reg, val); | |
2804 | POSTING_READ(reg); | |
de151cf6 JB |
2805 | } |
2806 | ||
9ce079e4 CW |
2807 | static void i830_write_fence_reg(struct drm_device *dev, int reg, |
2808 | struct drm_i915_gem_object *obj) | |
de151cf6 | 2809 | { |
de151cf6 | 2810 | drm_i915_private_t *dev_priv = dev->dev_private; |
de151cf6 | 2811 | uint32_t val; |
de151cf6 | 2812 | |
9ce079e4 | 2813 | if (obj) { |
f343c5f6 | 2814 | u32 size = i915_gem_obj_ggtt_size(obj); |
9ce079e4 | 2815 | uint32_t pitch_val; |
de151cf6 | 2816 | |
f343c5f6 | 2817 | WARN((i915_gem_obj_ggtt_offset(obj) & ~I830_FENCE_START_MASK) || |
9ce079e4 | 2818 | (size & -size) != size || |
f343c5f6 BW |
2819 | (i915_gem_obj_ggtt_offset(obj) & (size - 1)), |
2820 | "object 0x%08lx not 512K or pot-size 0x%08x aligned\n", | |
2821 | i915_gem_obj_ggtt_offset(obj), size); | |
e76a16de | 2822 | |
9ce079e4 CW |
2823 | pitch_val = obj->stride / 128; |
2824 | pitch_val = ffs(pitch_val) - 1; | |
de151cf6 | 2825 | |
f343c5f6 | 2826 | val = i915_gem_obj_ggtt_offset(obj); |
9ce079e4 CW |
2827 | if (obj->tiling_mode == I915_TILING_Y) |
2828 | val |= 1 << I830_FENCE_TILING_Y_SHIFT; | |
2829 | val |= I830_FENCE_SIZE_BITS(size); | |
2830 | val |= pitch_val << I830_FENCE_PITCH_SHIFT; | |
2831 | val |= I830_FENCE_REG_VALID; | |
2832 | } else | |
2833 | val = 0; | |
c6642782 | 2834 | |
9ce079e4 CW |
2835 | I915_WRITE(FENCE_REG_830_0 + reg * 4, val); |
2836 | POSTING_READ(FENCE_REG_830_0 + reg * 4); | |
2837 | } | |
2838 | ||
d0a57789 CW |
2839 | inline static bool i915_gem_object_needs_mb(struct drm_i915_gem_object *obj) |
2840 | { | |
2841 | return obj && obj->base.read_domains & I915_GEM_DOMAIN_GTT; | |
2842 | } | |
2843 | ||
9ce079e4 CW |
2844 | static void i915_gem_write_fence(struct drm_device *dev, int reg, |
2845 | struct drm_i915_gem_object *obj) | |
2846 | { | |
d0a57789 CW |
2847 | struct drm_i915_private *dev_priv = dev->dev_private; |
2848 | ||
2849 | /* Ensure that all CPU reads are completed before installing a fence | |
2850 | * and all writes before removing the fence. | |
2851 | */ | |
2852 | if (i915_gem_object_needs_mb(dev_priv->fence_regs[reg].obj)) | |
2853 | mb(); | |
2854 | ||
94a335db DV |
2855 | WARN(obj && (!obj->stride || !obj->tiling_mode), |
2856 | "bogus fence setup with stride: 0x%x, tiling mode: %i\n", | |
2857 | obj->stride, obj->tiling_mode); | |
2858 | ||
9ce079e4 CW |
2859 | switch (INTEL_INFO(dev)->gen) { |
2860 | case 7: | |
56c844e5 | 2861 | case 6: |
9ce079e4 CW |
2862 | case 5: |
2863 | case 4: i965_write_fence_reg(dev, reg, obj); break; | |
2864 | case 3: i915_write_fence_reg(dev, reg, obj); break; | |
2865 | case 2: i830_write_fence_reg(dev, reg, obj); break; | |
7dbf9d6e | 2866 | default: BUG(); |
9ce079e4 | 2867 | } |
d0a57789 CW |
2868 | |
2869 | /* And similarly be paranoid that no direct access to this region | |
2870 | * is reordered to before the fence is installed. | |
2871 | */ | |
2872 | if (i915_gem_object_needs_mb(obj)) | |
2873 | mb(); | |
de151cf6 JB |
2874 | } |
2875 | ||
61050808 CW |
2876 | static inline int fence_number(struct drm_i915_private *dev_priv, |
2877 | struct drm_i915_fence_reg *fence) | |
2878 | { | |
2879 | return fence - dev_priv->fence_regs; | |
2880 | } | |
2881 | ||
2882 | static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj, | |
2883 | struct drm_i915_fence_reg *fence, | |
2884 | bool enable) | |
2885 | { | |
2dc8aae0 | 2886 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
46a0b638 CW |
2887 | int reg = fence_number(dev_priv, fence); |
2888 | ||
2889 | i915_gem_write_fence(obj->base.dev, reg, enable ? obj : NULL); | |
61050808 CW |
2890 | |
2891 | if (enable) { | |
46a0b638 | 2892 | obj->fence_reg = reg; |
61050808 CW |
2893 | fence->obj = obj; |
2894 | list_move_tail(&fence->lru_list, &dev_priv->mm.fence_list); | |
2895 | } else { | |
2896 | obj->fence_reg = I915_FENCE_REG_NONE; | |
2897 | fence->obj = NULL; | |
2898 | list_del_init(&fence->lru_list); | |
2899 | } | |
94a335db | 2900 | obj->fence_dirty = false; |
61050808 CW |
2901 | } |
2902 | ||
d9e86c0e | 2903 | static int |
d0a57789 | 2904 | i915_gem_object_wait_fence(struct drm_i915_gem_object *obj) |
d9e86c0e | 2905 | { |
1c293ea3 | 2906 | if (obj->last_fenced_seqno) { |
86d5bc37 | 2907 | int ret = i915_wait_seqno(obj->ring, obj->last_fenced_seqno); |
18991845 CW |
2908 | if (ret) |
2909 | return ret; | |
d9e86c0e CW |
2910 | |
2911 | obj->last_fenced_seqno = 0; | |
d9e86c0e CW |
2912 | } |
2913 | ||
86d5bc37 | 2914 | obj->fenced_gpu_access = false; |
d9e86c0e CW |
2915 | return 0; |
2916 | } | |
2917 | ||
2918 | int | |
2919 | i915_gem_object_put_fence(struct drm_i915_gem_object *obj) | |
2920 | { | |
61050808 | 2921 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
f9c513e9 | 2922 | struct drm_i915_fence_reg *fence; |
d9e86c0e CW |
2923 | int ret; |
2924 | ||
d0a57789 | 2925 | ret = i915_gem_object_wait_fence(obj); |
d9e86c0e CW |
2926 | if (ret) |
2927 | return ret; | |
2928 | ||
61050808 CW |
2929 | if (obj->fence_reg == I915_FENCE_REG_NONE) |
2930 | return 0; | |
d9e86c0e | 2931 | |
f9c513e9 CW |
2932 | fence = &dev_priv->fence_regs[obj->fence_reg]; |
2933 | ||
61050808 | 2934 | i915_gem_object_fence_lost(obj); |
f9c513e9 | 2935 | i915_gem_object_update_fence(obj, fence, false); |
d9e86c0e CW |
2936 | |
2937 | return 0; | |
2938 | } | |
2939 | ||
2940 | static struct drm_i915_fence_reg * | |
a360bb1a | 2941 | i915_find_fence_reg(struct drm_device *dev) |
ae3db24a | 2942 | { |
ae3db24a | 2943 | struct drm_i915_private *dev_priv = dev->dev_private; |
8fe301ad | 2944 | struct drm_i915_fence_reg *reg, *avail; |
d9e86c0e | 2945 | int i; |
ae3db24a DV |
2946 | |
2947 | /* First try to find a free reg */ | |
d9e86c0e | 2948 | avail = NULL; |
ae3db24a DV |
2949 | for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) { |
2950 | reg = &dev_priv->fence_regs[i]; | |
2951 | if (!reg->obj) | |
d9e86c0e | 2952 | return reg; |
ae3db24a | 2953 | |
1690e1eb | 2954 | if (!reg->pin_count) |
d9e86c0e | 2955 | avail = reg; |
ae3db24a DV |
2956 | } |
2957 | ||
d9e86c0e CW |
2958 | if (avail == NULL) |
2959 | return NULL; | |
ae3db24a DV |
2960 | |
2961 | /* None available, try to steal one or wait for a user to finish */ | |
d9e86c0e | 2962 | list_for_each_entry(reg, &dev_priv->mm.fence_list, lru_list) { |
1690e1eb | 2963 | if (reg->pin_count) |
ae3db24a DV |
2964 | continue; |
2965 | ||
8fe301ad | 2966 | return reg; |
ae3db24a DV |
2967 | } |
2968 | ||
8fe301ad | 2969 | return NULL; |
ae3db24a DV |
2970 | } |
2971 | ||
de151cf6 | 2972 | /** |
9a5a53b3 | 2973 | * i915_gem_object_get_fence - set up fencing for an object |
de151cf6 JB |
2974 | * @obj: object to map through a fence reg |
2975 | * | |
2976 | * When mapping objects through the GTT, userspace wants to be able to write | |
2977 | * to them without having to worry about swizzling if the object is tiled. | |
de151cf6 JB |
2978 | * This function walks the fence regs looking for a free one for @obj, |
2979 | * stealing one if it can't find any. | |
2980 | * | |
2981 | * It then sets up the reg based on the object's properties: address, pitch | |
2982 | * and tiling format. | |
9a5a53b3 CW |
2983 | * |
2984 | * For an untiled surface, this removes any existing fence. | |
de151cf6 | 2985 | */ |
8c4b8c3f | 2986 | int |
06d98131 | 2987 | i915_gem_object_get_fence(struct drm_i915_gem_object *obj) |
de151cf6 | 2988 | { |
05394f39 | 2989 | struct drm_device *dev = obj->base.dev; |
79e53945 | 2990 | struct drm_i915_private *dev_priv = dev->dev_private; |
14415745 | 2991 | bool enable = obj->tiling_mode != I915_TILING_NONE; |
d9e86c0e | 2992 | struct drm_i915_fence_reg *reg; |
ae3db24a | 2993 | int ret; |
de151cf6 | 2994 | |
14415745 CW |
2995 | /* Have we updated the tiling parameters upon the object and so |
2996 | * will need to serialise the write to the associated fence register? | |
2997 | */ | |
5d82e3e6 | 2998 | if (obj->fence_dirty) { |
d0a57789 | 2999 | ret = i915_gem_object_wait_fence(obj); |
14415745 CW |
3000 | if (ret) |
3001 | return ret; | |
3002 | } | |
9a5a53b3 | 3003 | |
d9e86c0e | 3004 | /* Just update our place in the LRU if our fence is getting reused. */ |
05394f39 CW |
3005 | if (obj->fence_reg != I915_FENCE_REG_NONE) { |
3006 | reg = &dev_priv->fence_regs[obj->fence_reg]; | |
5d82e3e6 | 3007 | if (!obj->fence_dirty) { |
14415745 CW |
3008 | list_move_tail(®->lru_list, |
3009 | &dev_priv->mm.fence_list); | |
3010 | return 0; | |
3011 | } | |
3012 | } else if (enable) { | |
3013 | reg = i915_find_fence_reg(dev); | |
3014 | if (reg == NULL) | |
3015 | return -EDEADLK; | |
d9e86c0e | 3016 | |
14415745 CW |
3017 | if (reg->obj) { |
3018 | struct drm_i915_gem_object *old = reg->obj; | |
3019 | ||
d0a57789 | 3020 | ret = i915_gem_object_wait_fence(old); |
29c5a587 CW |
3021 | if (ret) |
3022 | return ret; | |
3023 | ||
14415745 | 3024 | i915_gem_object_fence_lost(old); |
29c5a587 | 3025 | } |
14415745 | 3026 | } else |
a09ba7fa | 3027 | return 0; |
a09ba7fa | 3028 | |
14415745 | 3029 | i915_gem_object_update_fence(obj, reg, enable); |
14415745 | 3030 | |
9ce079e4 | 3031 | return 0; |
de151cf6 JB |
3032 | } |
3033 | ||
42d6ab48 CW |
3034 | static bool i915_gem_valid_gtt_space(struct drm_device *dev, |
3035 | struct drm_mm_node *gtt_space, | |
3036 | unsigned long cache_level) | |
3037 | { | |
3038 | struct drm_mm_node *other; | |
3039 | ||
3040 | /* On non-LLC machines we have to be careful when putting differing | |
3041 | * types of snoopable memory together to avoid the prefetcher | |
4239ca77 | 3042 | * crossing memory domains and dying. |
42d6ab48 CW |
3043 | */ |
3044 | if (HAS_LLC(dev)) | |
3045 | return true; | |
3046 | ||
c6cfb325 | 3047 | if (!drm_mm_node_allocated(gtt_space)) |
42d6ab48 CW |
3048 | return true; |
3049 | ||
3050 | if (list_empty(>t_space->node_list)) | |
3051 | return true; | |
3052 | ||
3053 | other = list_entry(gtt_space->node_list.prev, struct drm_mm_node, node_list); | |
3054 | if (other->allocated && !other->hole_follows && other->color != cache_level) | |
3055 | return false; | |
3056 | ||
3057 | other = list_entry(gtt_space->node_list.next, struct drm_mm_node, node_list); | |
3058 | if (other->allocated && !gtt_space->hole_follows && other->color != cache_level) | |
3059 | return false; | |
3060 | ||
3061 | return true; | |
3062 | } | |
3063 | ||
3064 | static void i915_gem_verify_gtt(struct drm_device *dev) | |
3065 | { | |
3066 | #if WATCH_GTT | |
3067 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3068 | struct drm_i915_gem_object *obj; | |
3069 | int err = 0; | |
3070 | ||
35c20a60 | 3071 | list_for_each_entry(obj, &dev_priv->mm.gtt_list, global_list) { |
42d6ab48 CW |
3072 | if (obj->gtt_space == NULL) { |
3073 | printk(KERN_ERR "object found on GTT list with no space reserved\n"); | |
3074 | err++; | |
3075 | continue; | |
3076 | } | |
3077 | ||
3078 | if (obj->cache_level != obj->gtt_space->color) { | |
3079 | printk(KERN_ERR "object reserved space [%08lx, %08lx] with wrong color, cache_level=%x, color=%lx\n", | |
f343c5f6 BW |
3080 | i915_gem_obj_ggtt_offset(obj), |
3081 | i915_gem_obj_ggtt_offset(obj) + i915_gem_obj_ggtt_size(obj), | |
42d6ab48 CW |
3082 | obj->cache_level, |
3083 | obj->gtt_space->color); | |
3084 | err++; | |
3085 | continue; | |
3086 | } | |
3087 | ||
3088 | if (!i915_gem_valid_gtt_space(dev, | |
3089 | obj->gtt_space, | |
3090 | obj->cache_level)) { | |
3091 | printk(KERN_ERR "invalid GTT space found at [%08lx, %08lx] - color=%x\n", | |
f343c5f6 BW |
3092 | i915_gem_obj_ggtt_offset(obj), |
3093 | i915_gem_obj_ggtt_offset(obj) + i915_gem_obj_ggtt_size(obj), | |
42d6ab48 CW |
3094 | obj->cache_level); |
3095 | err++; | |
3096 | continue; | |
3097 | } | |
3098 | } | |
3099 | ||
3100 | WARN_ON(err); | |
3101 | #endif | |
3102 | } | |
3103 | ||
673a394b EA |
3104 | /** |
3105 | * Finds free space in the GTT aperture and binds the object there. | |
3106 | */ | |
3107 | static int | |
07fe0b12 BW |
3108 | i915_gem_object_bind_to_vm(struct drm_i915_gem_object *obj, |
3109 | struct i915_address_space *vm, | |
3110 | unsigned alignment, | |
3111 | bool map_and_fenceable, | |
3112 | bool nonblocking) | |
673a394b | 3113 | { |
05394f39 | 3114 | struct drm_device *dev = obj->base.dev; |
673a394b | 3115 | drm_i915_private_t *dev_priv = dev->dev_private; |
5e783301 | 3116 | u32 size, fence_size, fence_alignment, unfenced_alignment; |
75e9e915 | 3117 | bool mappable, fenceable; |
07fe0b12 BW |
3118 | size_t gtt_max = |
3119 | map_and_fenceable ? dev_priv->gtt.mappable_end : vm->total; | |
2f633156 | 3120 | struct i915_vma *vma; |
07f73f69 | 3121 | int ret; |
673a394b | 3122 | |
2f633156 BW |
3123 | if (WARN_ON(!list_empty(&obj->vma_list))) |
3124 | return -EBUSY; | |
3125 | ||
e28f8711 CW |
3126 | fence_size = i915_gem_get_gtt_size(dev, |
3127 | obj->base.size, | |
3128 | obj->tiling_mode); | |
3129 | fence_alignment = i915_gem_get_gtt_alignment(dev, | |
3130 | obj->base.size, | |
d865110c | 3131 | obj->tiling_mode, true); |
e28f8711 | 3132 | unfenced_alignment = |
d865110c | 3133 | i915_gem_get_gtt_alignment(dev, |
e28f8711 | 3134 | obj->base.size, |
d865110c | 3135 | obj->tiling_mode, false); |
a00b10c3 | 3136 | |
673a394b | 3137 | if (alignment == 0) |
5e783301 DV |
3138 | alignment = map_and_fenceable ? fence_alignment : |
3139 | unfenced_alignment; | |
75e9e915 | 3140 | if (map_and_fenceable && alignment & (fence_alignment - 1)) { |
673a394b EA |
3141 | DRM_ERROR("Invalid object alignment requested %u\n", alignment); |
3142 | return -EINVAL; | |
3143 | } | |
3144 | ||
05394f39 | 3145 | size = map_and_fenceable ? fence_size : obj->base.size; |
a00b10c3 | 3146 | |
654fc607 CW |
3147 | /* If the object is bigger than the entire aperture, reject it early |
3148 | * before evicting everything in a vain attempt to find space. | |
3149 | */ | |
0a9ae0d7 | 3150 | if (obj->base.size > gtt_max) { |
3765f304 | 3151 | DRM_ERROR("Attempting to bind an object larger than the aperture: object=%zd > %s aperture=%zu\n", |
a36689cb CW |
3152 | obj->base.size, |
3153 | map_and_fenceable ? "mappable" : "total", | |
0a9ae0d7 | 3154 | gtt_max); |
654fc607 CW |
3155 | return -E2BIG; |
3156 | } | |
3157 | ||
37e680a1 | 3158 | ret = i915_gem_object_get_pages(obj); |
6c085a72 CW |
3159 | if (ret) |
3160 | return ret; | |
3161 | ||
fbdda6fb CW |
3162 | i915_gem_object_pin_pages(obj); |
3163 | ||
07fe0b12 BW |
3164 | /* FIXME: For now we only ever use 1 VMA per object */ |
3165 | BUG_ON(!i915_is_ggtt(vm)); | |
3166 | WARN_ON(!list_empty(&obj->vma_list)); | |
3167 | ||
3168 | vma = i915_gem_vma_create(obj, vm); | |
db473b36 | 3169 | if (IS_ERR(vma)) { |
bc6bc15b DV |
3170 | ret = PTR_ERR(vma); |
3171 | goto err_unpin; | |
2f633156 BW |
3172 | } |
3173 | ||
0a9ae0d7 | 3174 | search_free: |
07fe0b12 | 3175 | ret = drm_mm_insert_node_in_range_generic(&vm->mm, &vma->node, |
0a9ae0d7 BW |
3176 | size, alignment, |
3177 | obj->cache_level, 0, gtt_max); | |
dc9dd7a2 | 3178 | if (ret) { |
f6cd1f15 | 3179 | ret = i915_gem_evict_something(dev, vm, size, alignment, |
42d6ab48 | 3180 | obj->cache_level, |
86a1ee26 CW |
3181 | map_and_fenceable, |
3182 | nonblocking); | |
dc9dd7a2 CW |
3183 | if (ret == 0) |
3184 | goto search_free; | |
9731129c | 3185 | |
bc6bc15b | 3186 | goto err_free_vma; |
673a394b | 3187 | } |
2f633156 | 3188 | if (WARN_ON(!i915_gem_valid_gtt_space(dev, &vma->node, |
c6cfb325 | 3189 | obj->cache_level))) { |
2f633156 | 3190 | ret = -EINVAL; |
bc6bc15b | 3191 | goto err_remove_node; |
673a394b EA |
3192 | } |
3193 | ||
74163907 | 3194 | ret = i915_gem_gtt_prepare_object(obj); |
2f633156 | 3195 | if (ret) |
bc6bc15b | 3196 | goto err_remove_node; |
673a394b | 3197 | |
35c20a60 | 3198 | list_move_tail(&obj->global_list, &dev_priv->mm.bound_list); |
ca191b13 | 3199 | list_add_tail(&vma->mm_list, &vm->inactive_list); |
07fe0b12 | 3200 | |
75e9e915 | 3201 | fenceable = |
07fe0b12 | 3202 | i915_is_ggtt(vm) && |
c6cfb325 BW |
3203 | i915_gem_obj_ggtt_size(obj) == fence_size && |
3204 | (i915_gem_obj_ggtt_offset(obj) & (fence_alignment - 1)) == 0; | |
a00b10c3 | 3205 | |
07fe0b12 BW |
3206 | mappable = |
3207 | i915_is_ggtt(vm) && | |
3208 | vma->node.start + obj->base.size <= dev_priv->gtt.mappable_end; | |
a00b10c3 | 3209 | |
5cacaac7 BW |
3210 | /* Map and fenceable only changes if the VM is the global GGTT */ |
3211 | if (i915_is_ggtt(vm)) | |
3212 | obj->map_and_fenceable = mappable && fenceable; | |
75e9e915 | 3213 | |
7ace7ef2 BW |
3214 | WARN_ON(map_and_fenceable && !obj->map_and_fenceable); |
3215 | ||
07fe0b12 | 3216 | trace_i915_vma_bind(vma, map_and_fenceable); |
42d6ab48 | 3217 | i915_gem_verify_gtt(dev); |
673a394b | 3218 | return 0; |
2f633156 | 3219 | |
bc6bc15b | 3220 | err_remove_node: |
6286ef9b | 3221 | drm_mm_remove_node(&vma->node); |
bc6bc15b | 3222 | err_free_vma: |
2f633156 | 3223 | i915_gem_vma_destroy(vma); |
bc6bc15b | 3224 | err_unpin: |
2f633156 | 3225 | i915_gem_object_unpin_pages(obj); |
2f633156 | 3226 | return ret; |
673a394b EA |
3227 | } |
3228 | ||
000433b6 | 3229 | bool |
2c22569b CW |
3230 | i915_gem_clflush_object(struct drm_i915_gem_object *obj, |
3231 | bool force) | |
673a394b | 3232 | { |
673a394b EA |
3233 | /* If we don't have a page list set up, then we're not pinned |
3234 | * to GPU, and we can ignore the cache flush because it'll happen | |
3235 | * again at bind time. | |
3236 | */ | |
05394f39 | 3237 | if (obj->pages == NULL) |
000433b6 | 3238 | return false; |
673a394b | 3239 | |
769ce464 ID |
3240 | /* |
3241 | * Stolen memory is always coherent with the GPU as it is explicitly | |
3242 | * marked as wc by the system, or the system is cache-coherent. | |
3243 | */ | |
3244 | if (obj->stolen) | |
000433b6 | 3245 | return false; |
769ce464 | 3246 | |
9c23f7fc CW |
3247 | /* If the GPU is snooping the contents of the CPU cache, |
3248 | * we do not need to manually clear the CPU cache lines. However, | |
3249 | * the caches are only snooped when the render cache is | |
3250 | * flushed/invalidated. As we always have to emit invalidations | |
3251 | * and flushes when moving into and out of the RENDER domain, correct | |
3252 | * snooping behaviour occurs naturally as the result of our domain | |
3253 | * tracking. | |
3254 | */ | |
2c22569b | 3255 | if (!force && cpu_cache_is_coherent(obj->base.dev, obj->cache_level)) |
000433b6 | 3256 | return false; |
9c23f7fc | 3257 | |
1c5d22f7 | 3258 | trace_i915_gem_object_clflush(obj); |
9da3da66 | 3259 | drm_clflush_sg(obj->pages); |
000433b6 CW |
3260 | |
3261 | return true; | |
e47c68e9 EA |
3262 | } |
3263 | ||
3264 | /** Flushes the GTT write domain for the object if it's dirty. */ | |
3265 | static void | |
05394f39 | 3266 | i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj) |
e47c68e9 | 3267 | { |
1c5d22f7 CW |
3268 | uint32_t old_write_domain; |
3269 | ||
05394f39 | 3270 | if (obj->base.write_domain != I915_GEM_DOMAIN_GTT) |
e47c68e9 EA |
3271 | return; |
3272 | ||
63256ec5 | 3273 | /* No actual flushing is required for the GTT write domain. Writes |
e47c68e9 EA |
3274 | * to it immediately go to main memory as far as we know, so there's |
3275 | * no chipset flush. It also doesn't land in render cache. | |
63256ec5 CW |
3276 | * |
3277 | * However, we do have to enforce the order so that all writes through | |
3278 | * the GTT land before any writes to the device, such as updates to | |
3279 | * the GATT itself. | |
e47c68e9 | 3280 | */ |
63256ec5 CW |
3281 | wmb(); |
3282 | ||
05394f39 CW |
3283 | old_write_domain = obj->base.write_domain; |
3284 | obj->base.write_domain = 0; | |
1c5d22f7 CW |
3285 | |
3286 | trace_i915_gem_object_change_domain(obj, | |
05394f39 | 3287 | obj->base.read_domains, |
1c5d22f7 | 3288 | old_write_domain); |
e47c68e9 EA |
3289 | } |
3290 | ||
3291 | /** Flushes the CPU write domain for the object if it's dirty. */ | |
3292 | static void | |
2c22569b CW |
3293 | i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj, |
3294 | bool force) | |
e47c68e9 | 3295 | { |
1c5d22f7 | 3296 | uint32_t old_write_domain; |
e47c68e9 | 3297 | |
05394f39 | 3298 | if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) |
e47c68e9 EA |
3299 | return; |
3300 | ||
000433b6 CW |
3301 | if (i915_gem_clflush_object(obj, force)) |
3302 | i915_gem_chipset_flush(obj->base.dev); | |
3303 | ||
05394f39 CW |
3304 | old_write_domain = obj->base.write_domain; |
3305 | obj->base.write_domain = 0; | |
1c5d22f7 CW |
3306 | |
3307 | trace_i915_gem_object_change_domain(obj, | |
05394f39 | 3308 | obj->base.read_domains, |
1c5d22f7 | 3309 | old_write_domain); |
e47c68e9 EA |
3310 | } |
3311 | ||
2ef7eeaa EA |
3312 | /** |
3313 | * Moves a single object to the GTT read, and possibly write domain. | |
3314 | * | |
3315 | * This function returns when the move is complete, including waiting on | |
3316 | * flushes to occur. | |
3317 | */ | |
79e53945 | 3318 | int |
2021746e | 3319 | i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write) |
2ef7eeaa | 3320 | { |
8325a09d | 3321 | drm_i915_private_t *dev_priv = obj->base.dev->dev_private; |
1c5d22f7 | 3322 | uint32_t old_write_domain, old_read_domains; |
e47c68e9 | 3323 | int ret; |
2ef7eeaa | 3324 | |
02354392 | 3325 | /* Not valid to be called on unbound objects. */ |
9843877d | 3326 | if (!i915_gem_obj_bound_any(obj)) |
02354392 EA |
3327 | return -EINVAL; |
3328 | ||
8d7e3de1 CW |
3329 | if (obj->base.write_domain == I915_GEM_DOMAIN_GTT) |
3330 | return 0; | |
3331 | ||
0201f1ec | 3332 | ret = i915_gem_object_wait_rendering(obj, !write); |
88241785 CW |
3333 | if (ret) |
3334 | return ret; | |
3335 | ||
2c22569b | 3336 | i915_gem_object_flush_cpu_write_domain(obj, false); |
1c5d22f7 | 3337 | |
d0a57789 CW |
3338 | /* Serialise direct access to this object with the barriers for |
3339 | * coherent writes from the GPU, by effectively invalidating the | |
3340 | * GTT domain upon first access. | |
3341 | */ | |
3342 | if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0) | |
3343 | mb(); | |
3344 | ||
05394f39 CW |
3345 | old_write_domain = obj->base.write_domain; |
3346 | old_read_domains = obj->base.read_domains; | |
1c5d22f7 | 3347 | |
e47c68e9 EA |
3348 | /* It should now be out of any other write domains, and we can update |
3349 | * the domain values for our changes. | |
3350 | */ | |
05394f39 CW |
3351 | BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) != 0); |
3352 | obj->base.read_domains |= I915_GEM_DOMAIN_GTT; | |
e47c68e9 | 3353 | if (write) { |
05394f39 CW |
3354 | obj->base.read_domains = I915_GEM_DOMAIN_GTT; |
3355 | obj->base.write_domain = I915_GEM_DOMAIN_GTT; | |
3356 | obj->dirty = 1; | |
2ef7eeaa EA |
3357 | } |
3358 | ||
1c5d22f7 CW |
3359 | trace_i915_gem_object_change_domain(obj, |
3360 | old_read_domains, | |
3361 | old_write_domain); | |
3362 | ||
8325a09d | 3363 | /* And bump the LRU for this access */ |
ca191b13 BW |
3364 | if (i915_gem_object_is_inactive(obj)) { |
3365 | struct i915_vma *vma = i915_gem_obj_to_vma(obj, | |
3366 | &dev_priv->gtt.base); | |
3367 | if (vma) | |
3368 | list_move_tail(&vma->mm_list, | |
3369 | &dev_priv->gtt.base.inactive_list); | |
3370 | ||
3371 | } | |
8325a09d | 3372 | |
e47c68e9 EA |
3373 | return 0; |
3374 | } | |
3375 | ||
e4ffd173 CW |
3376 | int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj, |
3377 | enum i915_cache_level cache_level) | |
3378 | { | |
7bddb01f DV |
3379 | struct drm_device *dev = obj->base.dev; |
3380 | drm_i915_private_t *dev_priv = dev->dev_private; | |
3089c6f2 | 3381 | struct i915_vma *vma; |
e4ffd173 CW |
3382 | int ret; |
3383 | ||
3384 | if (obj->cache_level == cache_level) | |
3385 | return 0; | |
3386 | ||
3387 | if (obj->pin_count) { | |
3388 | DRM_DEBUG("can not change the cache level of pinned objects\n"); | |
3389 | return -EBUSY; | |
3390 | } | |
3391 | ||
3089c6f2 BW |
3392 | list_for_each_entry(vma, &obj->vma_list, vma_link) { |
3393 | if (!i915_gem_valid_gtt_space(dev, &vma->node, cache_level)) { | |
07fe0b12 | 3394 | ret = i915_vma_unbind(vma); |
3089c6f2 BW |
3395 | if (ret) |
3396 | return ret; | |
3397 | ||
3398 | break; | |
3399 | } | |
42d6ab48 CW |
3400 | } |
3401 | ||
3089c6f2 | 3402 | if (i915_gem_obj_bound_any(obj)) { |
e4ffd173 CW |
3403 | ret = i915_gem_object_finish_gpu(obj); |
3404 | if (ret) | |
3405 | return ret; | |
3406 | ||
3407 | i915_gem_object_finish_gtt(obj); | |
3408 | ||
3409 | /* Before SandyBridge, you could not use tiling or fence | |
3410 | * registers with snooped memory, so relinquish any fences | |
3411 | * currently pointing to our region in the aperture. | |
3412 | */ | |
42d6ab48 | 3413 | if (INTEL_INFO(dev)->gen < 6) { |
e4ffd173 CW |
3414 | ret = i915_gem_object_put_fence(obj); |
3415 | if (ret) | |
3416 | return ret; | |
3417 | } | |
3418 | ||
74898d7e DV |
3419 | if (obj->has_global_gtt_mapping) |
3420 | i915_gem_gtt_bind_object(obj, cache_level); | |
7bddb01f DV |
3421 | if (obj->has_aliasing_ppgtt_mapping) |
3422 | i915_ppgtt_bind_object(dev_priv->mm.aliasing_ppgtt, | |
3423 | obj, cache_level); | |
e4ffd173 CW |
3424 | } |
3425 | ||
2c22569b CW |
3426 | list_for_each_entry(vma, &obj->vma_list, vma_link) |
3427 | vma->node.color = cache_level; | |
3428 | obj->cache_level = cache_level; | |
3429 | ||
3430 | if (cpu_write_needs_clflush(obj)) { | |
e4ffd173 CW |
3431 | u32 old_read_domains, old_write_domain; |
3432 | ||
3433 | /* If we're coming from LLC cached, then we haven't | |
3434 | * actually been tracking whether the data is in the | |
3435 | * CPU cache or not, since we only allow one bit set | |
3436 | * in obj->write_domain and have been skipping the clflushes. | |
3437 | * Just set it to the CPU cache for now. | |
3438 | */ | |
3439 | WARN_ON(obj->base.write_domain & ~I915_GEM_DOMAIN_CPU); | |
3440 | WARN_ON(obj->base.read_domains & ~I915_GEM_DOMAIN_CPU); | |
3441 | ||
3442 | old_read_domains = obj->base.read_domains; | |
3443 | old_write_domain = obj->base.write_domain; | |
3444 | ||
3445 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; | |
3446 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; | |
3447 | ||
3448 | trace_i915_gem_object_change_domain(obj, | |
3449 | old_read_domains, | |
3450 | old_write_domain); | |
3451 | } | |
3452 | ||
42d6ab48 | 3453 | i915_gem_verify_gtt(dev); |
e4ffd173 CW |
3454 | return 0; |
3455 | } | |
3456 | ||
199adf40 BW |
3457 | int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data, |
3458 | struct drm_file *file) | |
e6994aee | 3459 | { |
199adf40 | 3460 | struct drm_i915_gem_caching *args = data; |
e6994aee CW |
3461 | struct drm_i915_gem_object *obj; |
3462 | int ret; | |
3463 | ||
3464 | ret = i915_mutex_lock_interruptible(dev); | |
3465 | if (ret) | |
3466 | return ret; | |
3467 | ||
3468 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); | |
3469 | if (&obj->base == NULL) { | |
3470 | ret = -ENOENT; | |
3471 | goto unlock; | |
3472 | } | |
3473 | ||
199adf40 | 3474 | args->caching = obj->cache_level != I915_CACHE_NONE; |
e6994aee CW |
3475 | |
3476 | drm_gem_object_unreference(&obj->base); | |
3477 | unlock: | |
3478 | mutex_unlock(&dev->struct_mutex); | |
3479 | return ret; | |
3480 | } | |
3481 | ||
199adf40 BW |
3482 | int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data, |
3483 | struct drm_file *file) | |
e6994aee | 3484 | { |
199adf40 | 3485 | struct drm_i915_gem_caching *args = data; |
e6994aee CW |
3486 | struct drm_i915_gem_object *obj; |
3487 | enum i915_cache_level level; | |
3488 | int ret; | |
3489 | ||
199adf40 BW |
3490 | switch (args->caching) { |
3491 | case I915_CACHING_NONE: | |
e6994aee CW |
3492 | level = I915_CACHE_NONE; |
3493 | break; | |
199adf40 | 3494 | case I915_CACHING_CACHED: |
e6994aee CW |
3495 | level = I915_CACHE_LLC; |
3496 | break; | |
3497 | default: | |
3498 | return -EINVAL; | |
3499 | } | |
3500 | ||
3bc2913e BW |
3501 | ret = i915_mutex_lock_interruptible(dev); |
3502 | if (ret) | |
3503 | return ret; | |
3504 | ||
e6994aee CW |
3505 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
3506 | if (&obj->base == NULL) { | |
3507 | ret = -ENOENT; | |
3508 | goto unlock; | |
3509 | } | |
3510 | ||
3511 | ret = i915_gem_object_set_cache_level(obj, level); | |
3512 | ||
3513 | drm_gem_object_unreference(&obj->base); | |
3514 | unlock: | |
3515 | mutex_unlock(&dev->struct_mutex); | |
3516 | return ret; | |
3517 | } | |
3518 | ||
cc98b413 CW |
3519 | static bool is_pin_display(struct drm_i915_gem_object *obj) |
3520 | { | |
3521 | /* There are 3 sources that pin objects: | |
3522 | * 1. The display engine (scanouts, sprites, cursors); | |
3523 | * 2. Reservations for execbuffer; | |
3524 | * 3. The user. | |
3525 | * | |
3526 | * We can ignore reservations as we hold the struct_mutex and | |
3527 | * are only called outside of the reservation path. The user | |
3528 | * can only increment pin_count once, and so if after | |
3529 | * subtracting the potential reference by the user, any pin_count | |
3530 | * remains, it must be due to another use by the display engine. | |
3531 | */ | |
3532 | return obj->pin_count - !!obj->user_pin_count; | |
3533 | } | |
3534 | ||
b9241ea3 | 3535 | /* |
2da3b9b9 CW |
3536 | * Prepare buffer for display plane (scanout, cursors, etc). |
3537 | * Can be called from an uninterruptible phase (modesetting) and allows | |
3538 | * any flushes to be pipelined (for pageflips). | |
b9241ea3 ZW |
3539 | */ |
3540 | int | |
2da3b9b9 CW |
3541 | i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj, |
3542 | u32 alignment, | |
919926ae | 3543 | struct intel_ring_buffer *pipelined) |
b9241ea3 | 3544 | { |
2da3b9b9 | 3545 | u32 old_read_domains, old_write_domain; |
b9241ea3 ZW |
3546 | int ret; |
3547 | ||
0be73284 | 3548 | if (pipelined != obj->ring) { |
2911a35b BW |
3549 | ret = i915_gem_object_sync(obj, pipelined); |
3550 | if (ret) | |
b9241ea3 ZW |
3551 | return ret; |
3552 | } | |
3553 | ||
cc98b413 CW |
3554 | /* Mark the pin_display early so that we account for the |
3555 | * display coherency whilst setting up the cache domains. | |
3556 | */ | |
3557 | obj->pin_display = true; | |
3558 | ||
a7ef0640 EA |
3559 | /* The display engine is not coherent with the LLC cache on gen6. As |
3560 | * a result, we make sure that the pinning that is about to occur is | |
3561 | * done with uncached PTEs. This is lowest common denominator for all | |
3562 | * chipsets. | |
3563 | * | |
3564 | * However for gen6+, we could do better by using the GFDT bit instead | |
3565 | * of uncaching, which would allow us to flush all the LLC-cached data | |
3566 | * with that bit in the PTE to main memory with just one PIPE_CONTROL. | |
3567 | */ | |
3568 | ret = i915_gem_object_set_cache_level(obj, I915_CACHE_NONE); | |
3569 | if (ret) | |
cc98b413 | 3570 | goto err_unpin_display; |
a7ef0640 | 3571 | |
2da3b9b9 CW |
3572 | /* As the user may map the buffer once pinned in the display plane |
3573 | * (e.g. libkms for the bootup splash), we have to ensure that we | |
3574 | * always use map_and_fenceable for all scanout buffers. | |
3575 | */ | |
c37e2204 | 3576 | ret = i915_gem_obj_ggtt_pin(obj, alignment, true, false); |
2da3b9b9 | 3577 | if (ret) |
cc98b413 | 3578 | goto err_unpin_display; |
2da3b9b9 | 3579 | |
2c22569b | 3580 | i915_gem_object_flush_cpu_write_domain(obj, true); |
b118c1e3 | 3581 | |
2da3b9b9 | 3582 | old_write_domain = obj->base.write_domain; |
05394f39 | 3583 | old_read_domains = obj->base.read_domains; |
2da3b9b9 CW |
3584 | |
3585 | /* It should now be out of any other write domains, and we can update | |
3586 | * the domain values for our changes. | |
3587 | */ | |
e5f1d962 | 3588 | obj->base.write_domain = 0; |
05394f39 | 3589 | obj->base.read_domains |= I915_GEM_DOMAIN_GTT; |
b9241ea3 ZW |
3590 | |
3591 | trace_i915_gem_object_change_domain(obj, | |
3592 | old_read_domains, | |
2da3b9b9 | 3593 | old_write_domain); |
b9241ea3 ZW |
3594 | |
3595 | return 0; | |
cc98b413 CW |
3596 | |
3597 | err_unpin_display: | |
3598 | obj->pin_display = is_pin_display(obj); | |
3599 | return ret; | |
3600 | } | |
3601 | ||
3602 | void | |
3603 | i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object *obj) | |
3604 | { | |
3605 | i915_gem_object_unpin(obj); | |
3606 | obj->pin_display = is_pin_display(obj); | |
b9241ea3 ZW |
3607 | } |
3608 | ||
85345517 | 3609 | int |
a8198eea | 3610 | i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj) |
85345517 | 3611 | { |
88241785 CW |
3612 | int ret; |
3613 | ||
a8198eea | 3614 | if ((obj->base.read_domains & I915_GEM_GPU_DOMAINS) == 0) |
85345517 CW |
3615 | return 0; |
3616 | ||
0201f1ec | 3617 | ret = i915_gem_object_wait_rendering(obj, false); |
c501ae7f CW |
3618 | if (ret) |
3619 | return ret; | |
3620 | ||
a8198eea CW |
3621 | /* Ensure that we invalidate the GPU's caches and TLBs. */ |
3622 | obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS; | |
c501ae7f | 3623 | return 0; |
85345517 CW |
3624 | } |
3625 | ||
e47c68e9 EA |
3626 | /** |
3627 | * Moves a single object to the CPU read, and possibly write domain. | |
3628 | * | |
3629 | * This function returns when the move is complete, including waiting on | |
3630 | * flushes to occur. | |
3631 | */ | |
dabdfe02 | 3632 | int |
919926ae | 3633 | i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write) |
e47c68e9 | 3634 | { |
1c5d22f7 | 3635 | uint32_t old_write_domain, old_read_domains; |
e47c68e9 EA |
3636 | int ret; |
3637 | ||
8d7e3de1 CW |
3638 | if (obj->base.write_domain == I915_GEM_DOMAIN_CPU) |
3639 | return 0; | |
3640 | ||
0201f1ec | 3641 | ret = i915_gem_object_wait_rendering(obj, !write); |
88241785 CW |
3642 | if (ret) |
3643 | return ret; | |
3644 | ||
e47c68e9 | 3645 | i915_gem_object_flush_gtt_write_domain(obj); |
2ef7eeaa | 3646 | |
05394f39 CW |
3647 | old_write_domain = obj->base.write_domain; |
3648 | old_read_domains = obj->base.read_domains; | |
1c5d22f7 | 3649 | |
e47c68e9 | 3650 | /* Flush the CPU cache if it's still invalid. */ |
05394f39 | 3651 | if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) { |
2c22569b | 3652 | i915_gem_clflush_object(obj, false); |
2ef7eeaa | 3653 | |
05394f39 | 3654 | obj->base.read_domains |= I915_GEM_DOMAIN_CPU; |
2ef7eeaa EA |
3655 | } |
3656 | ||
3657 | /* It should now be out of any other write domains, and we can update | |
3658 | * the domain values for our changes. | |
3659 | */ | |
05394f39 | 3660 | BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) != 0); |
e47c68e9 EA |
3661 | |
3662 | /* If we're writing through the CPU, then the GPU read domains will | |
3663 | * need to be invalidated at next use. | |
3664 | */ | |
3665 | if (write) { | |
05394f39 CW |
3666 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; |
3667 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; | |
e47c68e9 | 3668 | } |
2ef7eeaa | 3669 | |
1c5d22f7 CW |
3670 | trace_i915_gem_object_change_domain(obj, |
3671 | old_read_domains, | |
3672 | old_write_domain); | |
3673 | ||
2ef7eeaa EA |
3674 | return 0; |
3675 | } | |
3676 | ||
673a394b EA |
3677 | /* Throttle our rendering by waiting until the ring has completed our requests |
3678 | * emitted over 20 msec ago. | |
3679 | * | |
b962442e EA |
3680 | * Note that if we were to use the current jiffies each time around the loop, |
3681 | * we wouldn't escape the function with any frames outstanding if the time to | |
3682 | * render a frame was over 20ms. | |
3683 | * | |
673a394b EA |
3684 | * This should get us reasonable parallelism between CPU and GPU but also |
3685 | * relatively low latency when blocking on a particular request to finish. | |
3686 | */ | |
40a5f0de | 3687 | static int |
f787a5f5 | 3688 | i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file) |
40a5f0de | 3689 | { |
f787a5f5 CW |
3690 | struct drm_i915_private *dev_priv = dev->dev_private; |
3691 | struct drm_i915_file_private *file_priv = file->driver_priv; | |
b962442e | 3692 | unsigned long recent_enough = jiffies - msecs_to_jiffies(20); |
f787a5f5 CW |
3693 | struct drm_i915_gem_request *request; |
3694 | struct intel_ring_buffer *ring = NULL; | |
f69061be | 3695 | unsigned reset_counter; |
f787a5f5 CW |
3696 | u32 seqno = 0; |
3697 | int ret; | |
93533c29 | 3698 | |
308887aa DV |
3699 | ret = i915_gem_wait_for_error(&dev_priv->gpu_error); |
3700 | if (ret) | |
3701 | return ret; | |
3702 | ||
3703 | ret = i915_gem_check_wedge(&dev_priv->gpu_error, false); | |
3704 | if (ret) | |
3705 | return ret; | |
e110e8d6 | 3706 | |
1c25595f | 3707 | spin_lock(&file_priv->mm.lock); |
f787a5f5 | 3708 | list_for_each_entry(request, &file_priv->mm.request_list, client_list) { |
b962442e EA |
3709 | if (time_after_eq(request->emitted_jiffies, recent_enough)) |
3710 | break; | |
40a5f0de | 3711 | |
f787a5f5 CW |
3712 | ring = request->ring; |
3713 | seqno = request->seqno; | |
b962442e | 3714 | } |
f69061be | 3715 | reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter); |
1c25595f | 3716 | spin_unlock(&file_priv->mm.lock); |
40a5f0de | 3717 | |
f787a5f5 CW |
3718 | if (seqno == 0) |
3719 | return 0; | |
2bc43b5c | 3720 | |
f69061be | 3721 | ret = __wait_seqno(ring, seqno, reset_counter, true, NULL); |
f787a5f5 CW |
3722 | if (ret == 0) |
3723 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, 0); | |
40a5f0de EA |
3724 | |
3725 | return ret; | |
3726 | } | |
3727 | ||
673a394b | 3728 | int |
05394f39 | 3729 | i915_gem_object_pin(struct drm_i915_gem_object *obj, |
c37e2204 | 3730 | struct i915_address_space *vm, |
05394f39 | 3731 | uint32_t alignment, |
86a1ee26 CW |
3732 | bool map_and_fenceable, |
3733 | bool nonblocking) | |
673a394b | 3734 | { |
07fe0b12 | 3735 | struct i915_vma *vma; |
673a394b EA |
3736 | int ret; |
3737 | ||
7e81a42e CW |
3738 | if (WARN_ON(obj->pin_count == DRM_I915_GEM_OBJECT_MAX_PIN_COUNT)) |
3739 | return -EBUSY; | |
ac0c6b5a | 3740 | |
07fe0b12 BW |
3741 | WARN_ON(map_and_fenceable && !i915_is_ggtt(vm)); |
3742 | ||
3743 | vma = i915_gem_obj_to_vma(obj, vm); | |
3744 | ||
3745 | if (vma) { | |
3746 | if ((alignment && | |
3747 | vma->node.start & (alignment - 1)) || | |
05394f39 CW |
3748 | (map_and_fenceable && !obj->map_and_fenceable)) { |
3749 | WARN(obj->pin_count, | |
ae7d49d8 | 3750 | "bo is already pinned with incorrect alignment:" |
f343c5f6 | 3751 | " offset=%lx, req.alignment=%x, req.map_and_fenceable=%d," |
75e9e915 | 3752 | " obj->map_and_fenceable=%d\n", |
07fe0b12 | 3753 | i915_gem_obj_offset(obj, vm), alignment, |
75e9e915 | 3754 | map_and_fenceable, |
05394f39 | 3755 | obj->map_and_fenceable); |
07fe0b12 | 3756 | ret = i915_vma_unbind(vma); |
ac0c6b5a CW |
3757 | if (ret) |
3758 | return ret; | |
3759 | } | |
3760 | } | |
3761 | ||
07fe0b12 | 3762 | if (!i915_gem_obj_bound(obj, vm)) { |
8742267a CW |
3763 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
3764 | ||
07fe0b12 BW |
3765 | ret = i915_gem_object_bind_to_vm(obj, vm, alignment, |
3766 | map_and_fenceable, | |
3767 | nonblocking); | |
9731129c | 3768 | if (ret) |
673a394b | 3769 | return ret; |
8742267a CW |
3770 | |
3771 | if (!dev_priv->mm.aliasing_ppgtt) | |
3772 | i915_gem_gtt_bind_object(obj, obj->cache_level); | |
22c344e9 | 3773 | } |
76446cac | 3774 | |
74898d7e DV |
3775 | if (!obj->has_global_gtt_mapping && map_and_fenceable) |
3776 | i915_gem_gtt_bind_object(obj, obj->cache_level); | |
3777 | ||
1b50247a | 3778 | obj->pin_count++; |
6299f992 | 3779 | obj->pin_mappable |= map_and_fenceable; |
673a394b EA |
3780 | |
3781 | return 0; | |
3782 | } | |
3783 | ||
3784 | void | |
05394f39 | 3785 | i915_gem_object_unpin(struct drm_i915_gem_object *obj) |
673a394b | 3786 | { |
05394f39 | 3787 | BUG_ON(obj->pin_count == 0); |
9843877d | 3788 | BUG_ON(!i915_gem_obj_bound_any(obj)); |
673a394b | 3789 | |
1b50247a | 3790 | if (--obj->pin_count == 0) |
6299f992 | 3791 | obj->pin_mappable = false; |
673a394b EA |
3792 | } |
3793 | ||
3794 | int | |
3795 | i915_gem_pin_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 3796 | struct drm_file *file) |
673a394b EA |
3797 | { |
3798 | struct drm_i915_gem_pin *args = data; | |
05394f39 | 3799 | struct drm_i915_gem_object *obj; |
673a394b EA |
3800 | int ret; |
3801 | ||
1d7cfea1 CW |
3802 | ret = i915_mutex_lock_interruptible(dev); |
3803 | if (ret) | |
3804 | return ret; | |
673a394b | 3805 | |
05394f39 | 3806 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 3807 | if (&obj->base == NULL) { |
1d7cfea1 CW |
3808 | ret = -ENOENT; |
3809 | goto unlock; | |
673a394b | 3810 | } |
673a394b | 3811 | |
05394f39 | 3812 | if (obj->madv != I915_MADV_WILLNEED) { |
bb6baf76 | 3813 | DRM_ERROR("Attempting to pin a purgeable buffer\n"); |
1d7cfea1 CW |
3814 | ret = -EINVAL; |
3815 | goto out; | |
3ef94daa CW |
3816 | } |
3817 | ||
05394f39 | 3818 | if (obj->pin_filp != NULL && obj->pin_filp != file) { |
79e53945 JB |
3819 | DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n", |
3820 | args->handle); | |
1d7cfea1 CW |
3821 | ret = -EINVAL; |
3822 | goto out; | |
79e53945 JB |
3823 | } |
3824 | ||
93be8788 | 3825 | if (obj->user_pin_count == 0) { |
c37e2204 | 3826 | ret = i915_gem_obj_ggtt_pin(obj, args->alignment, true, false); |
1d7cfea1 CW |
3827 | if (ret) |
3828 | goto out; | |
673a394b EA |
3829 | } |
3830 | ||
93be8788 CW |
3831 | obj->user_pin_count++; |
3832 | obj->pin_filp = file; | |
3833 | ||
f343c5f6 | 3834 | args->offset = i915_gem_obj_ggtt_offset(obj); |
1d7cfea1 | 3835 | out: |
05394f39 | 3836 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 3837 | unlock: |
673a394b | 3838 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 3839 | return ret; |
673a394b EA |
3840 | } |
3841 | ||
3842 | int | |
3843 | i915_gem_unpin_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 3844 | struct drm_file *file) |
673a394b EA |
3845 | { |
3846 | struct drm_i915_gem_pin *args = data; | |
05394f39 | 3847 | struct drm_i915_gem_object *obj; |
76c1dec1 | 3848 | int ret; |
673a394b | 3849 | |
1d7cfea1 CW |
3850 | ret = i915_mutex_lock_interruptible(dev); |
3851 | if (ret) | |
3852 | return ret; | |
673a394b | 3853 | |
05394f39 | 3854 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 3855 | if (&obj->base == NULL) { |
1d7cfea1 CW |
3856 | ret = -ENOENT; |
3857 | goto unlock; | |
673a394b | 3858 | } |
76c1dec1 | 3859 | |
05394f39 | 3860 | if (obj->pin_filp != file) { |
79e53945 JB |
3861 | DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n", |
3862 | args->handle); | |
1d7cfea1 CW |
3863 | ret = -EINVAL; |
3864 | goto out; | |
79e53945 | 3865 | } |
05394f39 CW |
3866 | obj->user_pin_count--; |
3867 | if (obj->user_pin_count == 0) { | |
3868 | obj->pin_filp = NULL; | |
79e53945 JB |
3869 | i915_gem_object_unpin(obj); |
3870 | } | |
673a394b | 3871 | |
1d7cfea1 | 3872 | out: |
05394f39 | 3873 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 3874 | unlock: |
673a394b | 3875 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 3876 | return ret; |
673a394b EA |
3877 | } |
3878 | ||
3879 | int | |
3880 | i915_gem_busy_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 3881 | struct drm_file *file) |
673a394b EA |
3882 | { |
3883 | struct drm_i915_gem_busy *args = data; | |
05394f39 | 3884 | struct drm_i915_gem_object *obj; |
30dbf0c0 CW |
3885 | int ret; |
3886 | ||
76c1dec1 | 3887 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 3888 | if (ret) |
76c1dec1 | 3889 | return ret; |
673a394b | 3890 | |
05394f39 | 3891 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 3892 | if (&obj->base == NULL) { |
1d7cfea1 CW |
3893 | ret = -ENOENT; |
3894 | goto unlock; | |
673a394b | 3895 | } |
d1b851fc | 3896 | |
0be555b6 CW |
3897 | /* Count all active objects as busy, even if they are currently not used |
3898 | * by the gpu. Users of this interface expect objects to eventually | |
3899 | * become non-busy without any further actions, therefore emit any | |
3900 | * necessary flushes here. | |
c4de0a5d | 3901 | */ |
30dfebf3 | 3902 | ret = i915_gem_object_flush_active(obj); |
0be555b6 | 3903 | |
30dfebf3 | 3904 | args->busy = obj->active; |
e9808edd CW |
3905 | if (obj->ring) { |
3906 | BUILD_BUG_ON(I915_NUM_RINGS > 16); | |
3907 | args->busy |= intel_ring_flag(obj->ring) << 16; | |
3908 | } | |
673a394b | 3909 | |
05394f39 | 3910 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 3911 | unlock: |
673a394b | 3912 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 3913 | return ret; |
673a394b EA |
3914 | } |
3915 | ||
3916 | int | |
3917 | i915_gem_throttle_ioctl(struct drm_device *dev, void *data, | |
3918 | struct drm_file *file_priv) | |
3919 | { | |
0206e353 | 3920 | return i915_gem_ring_throttle(dev, file_priv); |
673a394b EA |
3921 | } |
3922 | ||
3ef94daa CW |
3923 | int |
3924 | i915_gem_madvise_ioctl(struct drm_device *dev, void *data, | |
3925 | struct drm_file *file_priv) | |
3926 | { | |
3927 | struct drm_i915_gem_madvise *args = data; | |
05394f39 | 3928 | struct drm_i915_gem_object *obj; |
76c1dec1 | 3929 | int ret; |
3ef94daa CW |
3930 | |
3931 | switch (args->madv) { | |
3932 | case I915_MADV_DONTNEED: | |
3933 | case I915_MADV_WILLNEED: | |
3934 | break; | |
3935 | default: | |
3936 | return -EINVAL; | |
3937 | } | |
3938 | ||
1d7cfea1 CW |
3939 | ret = i915_mutex_lock_interruptible(dev); |
3940 | if (ret) | |
3941 | return ret; | |
3942 | ||
05394f39 | 3943 | obj = to_intel_bo(drm_gem_object_lookup(dev, file_priv, args->handle)); |
c8725226 | 3944 | if (&obj->base == NULL) { |
1d7cfea1 CW |
3945 | ret = -ENOENT; |
3946 | goto unlock; | |
3ef94daa | 3947 | } |
3ef94daa | 3948 | |
05394f39 | 3949 | if (obj->pin_count) { |
1d7cfea1 CW |
3950 | ret = -EINVAL; |
3951 | goto out; | |
3ef94daa CW |
3952 | } |
3953 | ||
05394f39 CW |
3954 | if (obj->madv != __I915_MADV_PURGED) |
3955 | obj->madv = args->madv; | |
3ef94daa | 3956 | |
6c085a72 CW |
3957 | /* if the object is no longer attached, discard its backing storage */ |
3958 | if (i915_gem_object_is_purgeable(obj) && obj->pages == NULL) | |
2d7ef395 CW |
3959 | i915_gem_object_truncate(obj); |
3960 | ||
05394f39 | 3961 | args->retained = obj->madv != __I915_MADV_PURGED; |
bb6baf76 | 3962 | |
1d7cfea1 | 3963 | out: |
05394f39 | 3964 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 3965 | unlock: |
3ef94daa | 3966 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 3967 | return ret; |
3ef94daa CW |
3968 | } |
3969 | ||
37e680a1 CW |
3970 | void i915_gem_object_init(struct drm_i915_gem_object *obj, |
3971 | const struct drm_i915_gem_object_ops *ops) | |
0327d6ba | 3972 | { |
35c20a60 | 3973 | INIT_LIST_HEAD(&obj->global_list); |
0327d6ba CW |
3974 | INIT_LIST_HEAD(&obj->ring_list); |
3975 | INIT_LIST_HEAD(&obj->exec_list); | |
2f633156 | 3976 | INIT_LIST_HEAD(&obj->vma_list); |
0327d6ba | 3977 | |
37e680a1 CW |
3978 | obj->ops = ops; |
3979 | ||
0327d6ba CW |
3980 | obj->fence_reg = I915_FENCE_REG_NONE; |
3981 | obj->madv = I915_MADV_WILLNEED; | |
3982 | /* Avoid an unnecessary call to unbind on the first bind. */ | |
3983 | obj->map_and_fenceable = true; | |
3984 | ||
3985 | i915_gem_info_add_obj(obj->base.dev->dev_private, obj->base.size); | |
3986 | } | |
3987 | ||
37e680a1 CW |
3988 | static const struct drm_i915_gem_object_ops i915_gem_object_ops = { |
3989 | .get_pages = i915_gem_object_get_pages_gtt, | |
3990 | .put_pages = i915_gem_object_put_pages_gtt, | |
3991 | }; | |
3992 | ||
05394f39 CW |
3993 | struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev, |
3994 | size_t size) | |
ac52bc56 | 3995 | { |
c397b908 | 3996 | struct drm_i915_gem_object *obj; |
5949eac4 | 3997 | struct address_space *mapping; |
1a240d4d | 3998 | gfp_t mask; |
ac52bc56 | 3999 | |
42dcedd4 | 4000 | obj = i915_gem_object_alloc(dev); |
c397b908 DV |
4001 | if (obj == NULL) |
4002 | return NULL; | |
673a394b | 4003 | |
c397b908 | 4004 | if (drm_gem_object_init(dev, &obj->base, size) != 0) { |
42dcedd4 | 4005 | i915_gem_object_free(obj); |
c397b908 DV |
4006 | return NULL; |
4007 | } | |
673a394b | 4008 | |
bed1ea95 CW |
4009 | mask = GFP_HIGHUSER | __GFP_RECLAIMABLE; |
4010 | if (IS_CRESTLINE(dev) || IS_BROADWATER(dev)) { | |
4011 | /* 965gm cannot relocate objects above 4GiB. */ | |
4012 | mask &= ~__GFP_HIGHMEM; | |
4013 | mask |= __GFP_DMA32; | |
4014 | } | |
4015 | ||
496ad9aa | 4016 | mapping = file_inode(obj->base.filp)->i_mapping; |
bed1ea95 | 4017 | mapping_set_gfp_mask(mapping, mask); |
5949eac4 | 4018 | |
37e680a1 | 4019 | i915_gem_object_init(obj, &i915_gem_object_ops); |
73aa808f | 4020 | |
c397b908 DV |
4021 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; |
4022 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; | |
673a394b | 4023 | |
3d29b842 ED |
4024 | if (HAS_LLC(dev)) { |
4025 | /* On some devices, we can have the GPU use the LLC (the CPU | |
a1871112 EA |
4026 | * cache) for about a 10% performance improvement |
4027 | * compared to uncached. Graphics requests other than | |
4028 | * display scanout are coherent with the CPU in | |
4029 | * accessing this cache. This means in this mode we | |
4030 | * don't need to clflush on the CPU side, and on the | |
4031 | * GPU side we only need to flush internal caches to | |
4032 | * get data visible to the CPU. | |
4033 | * | |
4034 | * However, we maintain the display planes as UC, and so | |
4035 | * need to rebind when first used as such. | |
4036 | */ | |
4037 | obj->cache_level = I915_CACHE_LLC; | |
4038 | } else | |
4039 | obj->cache_level = I915_CACHE_NONE; | |
4040 | ||
d861e338 DV |
4041 | trace_i915_gem_object_create(obj); |
4042 | ||
05394f39 | 4043 | return obj; |
c397b908 DV |
4044 | } |
4045 | ||
4046 | int i915_gem_init_object(struct drm_gem_object *obj) | |
4047 | { | |
4048 | BUG(); | |
de151cf6 | 4049 | |
673a394b EA |
4050 | return 0; |
4051 | } | |
4052 | ||
1488fc08 | 4053 | void i915_gem_free_object(struct drm_gem_object *gem_obj) |
673a394b | 4054 | { |
1488fc08 | 4055 | struct drm_i915_gem_object *obj = to_intel_bo(gem_obj); |
05394f39 | 4056 | struct drm_device *dev = obj->base.dev; |
be72615b | 4057 | drm_i915_private_t *dev_priv = dev->dev_private; |
07fe0b12 | 4058 | struct i915_vma *vma, *next; |
673a394b | 4059 | |
26e12f89 CW |
4060 | trace_i915_gem_object_destroy(obj); |
4061 | ||
1488fc08 CW |
4062 | if (obj->phys_obj) |
4063 | i915_gem_detach_phys_object(dev, obj); | |
4064 | ||
4065 | obj->pin_count = 0; | |
07fe0b12 BW |
4066 | /* NB: 0 or 1 elements */ |
4067 | WARN_ON(!list_empty(&obj->vma_list) && | |
4068 | !list_is_singular(&obj->vma_list)); | |
4069 | list_for_each_entry_safe(vma, next, &obj->vma_list, vma_link) { | |
4070 | int ret = i915_vma_unbind(vma); | |
4071 | if (WARN_ON(ret == -ERESTARTSYS)) { | |
4072 | bool was_interruptible; | |
1488fc08 | 4073 | |
07fe0b12 BW |
4074 | was_interruptible = dev_priv->mm.interruptible; |
4075 | dev_priv->mm.interruptible = false; | |
1488fc08 | 4076 | |
07fe0b12 | 4077 | WARN_ON(i915_vma_unbind(vma)); |
1488fc08 | 4078 | |
07fe0b12 BW |
4079 | dev_priv->mm.interruptible = was_interruptible; |
4080 | } | |
1488fc08 CW |
4081 | } |
4082 | ||
1d64ae71 BW |
4083 | /* Stolen objects don't hold a ref, but do hold pin count. Fix that up |
4084 | * before progressing. */ | |
4085 | if (obj->stolen) | |
4086 | i915_gem_object_unpin_pages(obj); | |
4087 | ||
401c29f6 BW |
4088 | if (WARN_ON(obj->pages_pin_count)) |
4089 | obj->pages_pin_count = 0; | |
37e680a1 | 4090 | i915_gem_object_put_pages(obj); |
d8cb5086 | 4091 | i915_gem_object_free_mmap_offset(obj); |
0104fdbb | 4092 | i915_gem_object_release_stolen(obj); |
de151cf6 | 4093 | |
9da3da66 CW |
4094 | BUG_ON(obj->pages); |
4095 | ||
2f745ad3 CW |
4096 | if (obj->base.import_attach) |
4097 | drm_prime_gem_destroy(&obj->base, NULL); | |
de151cf6 | 4098 | |
05394f39 CW |
4099 | drm_gem_object_release(&obj->base); |
4100 | i915_gem_info_remove_obj(dev_priv, obj->base.size); | |
c397b908 | 4101 | |
05394f39 | 4102 | kfree(obj->bit_17); |
42dcedd4 | 4103 | i915_gem_object_free(obj); |
673a394b EA |
4104 | } |
4105 | ||
2f633156 BW |
4106 | struct i915_vma *i915_gem_vma_create(struct drm_i915_gem_object *obj, |
4107 | struct i915_address_space *vm) | |
4108 | { | |
4109 | struct i915_vma *vma = kzalloc(sizeof(*vma), GFP_KERNEL); | |
4110 | if (vma == NULL) | |
4111 | return ERR_PTR(-ENOMEM); | |
4112 | ||
4113 | INIT_LIST_HEAD(&vma->vma_link); | |
ca191b13 | 4114 | INIT_LIST_HEAD(&vma->mm_list); |
2f633156 BW |
4115 | vma->vm = vm; |
4116 | vma->obj = obj; | |
4117 | ||
8b9c2b94 BW |
4118 | /* Keep GGTT vmas first to make debug easier */ |
4119 | if (i915_is_ggtt(vm)) | |
4120 | list_add(&vma->vma_link, &obj->vma_list); | |
4121 | else | |
4122 | list_add_tail(&vma->vma_link, &obj->vma_list); | |
4123 | ||
2f633156 BW |
4124 | return vma; |
4125 | } | |
4126 | ||
4127 | void i915_gem_vma_destroy(struct i915_vma *vma) | |
4128 | { | |
4129 | WARN_ON(vma->node.allocated); | |
8b9c2b94 | 4130 | list_del(&vma->vma_link); |
2f633156 BW |
4131 | kfree(vma); |
4132 | } | |
4133 | ||
29105ccc CW |
4134 | int |
4135 | i915_gem_idle(struct drm_device *dev) | |
4136 | { | |
4137 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4138 | int ret; | |
28dfe52a | 4139 | |
db1b76ca | 4140 | if (dev_priv->ums.mm_suspended) { |
29105ccc CW |
4141 | mutex_unlock(&dev->struct_mutex); |
4142 | return 0; | |
28dfe52a EA |
4143 | } |
4144 | ||
b2da9fe5 | 4145 | ret = i915_gpu_idle(dev); |
6dbe2772 KP |
4146 | if (ret) { |
4147 | mutex_unlock(&dev->struct_mutex); | |
673a394b | 4148 | return ret; |
6dbe2772 | 4149 | } |
b2da9fe5 | 4150 | i915_gem_retire_requests(dev); |
673a394b | 4151 | |
29105ccc | 4152 | /* Under UMS, be paranoid and evict. */ |
a39d7efc | 4153 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) |
6c085a72 | 4154 | i915_gem_evict_everything(dev); |
29105ccc | 4155 | |
99584db3 | 4156 | del_timer_sync(&dev_priv->gpu_error.hangcheck_timer); |
29105ccc CW |
4157 | |
4158 | i915_kernel_lost_context(dev); | |
6dbe2772 | 4159 | i915_gem_cleanup_ringbuffer(dev); |
29105ccc | 4160 | |
29105ccc CW |
4161 | /* Cancel the retire work handler, which should be idle now. */ |
4162 | cancel_delayed_work_sync(&dev_priv->mm.retire_work); | |
4163 | ||
673a394b EA |
4164 | return 0; |
4165 | } | |
4166 | ||
b9524a1e BW |
4167 | void i915_gem_l3_remap(struct drm_device *dev) |
4168 | { | |
4169 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4170 | u32 misccpctl; | |
4171 | int i; | |
4172 | ||
eb32e458 | 4173 | if (!HAS_L3_GPU_CACHE(dev)) |
b9524a1e BW |
4174 | return; |
4175 | ||
a4da4fa4 | 4176 | if (!dev_priv->l3_parity.remap_info) |
b9524a1e BW |
4177 | return; |
4178 | ||
4179 | misccpctl = I915_READ(GEN7_MISCCPCTL); | |
4180 | I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE); | |
4181 | POSTING_READ(GEN7_MISCCPCTL); | |
4182 | ||
4183 | for (i = 0; i < GEN7_L3LOG_SIZE; i += 4) { | |
4184 | u32 remap = I915_READ(GEN7_L3LOG_BASE + i); | |
a4da4fa4 | 4185 | if (remap && remap != dev_priv->l3_parity.remap_info[i/4]) |
b9524a1e BW |
4186 | DRM_DEBUG("0x%x was already programmed to %x\n", |
4187 | GEN7_L3LOG_BASE + i, remap); | |
a4da4fa4 | 4188 | if (remap && !dev_priv->l3_parity.remap_info[i/4]) |
b9524a1e | 4189 | DRM_DEBUG_DRIVER("Clearing remapped register\n"); |
a4da4fa4 | 4190 | I915_WRITE(GEN7_L3LOG_BASE + i, dev_priv->l3_parity.remap_info[i/4]); |
b9524a1e BW |
4191 | } |
4192 | ||
4193 | /* Make sure all the writes land before disabling dop clock gating */ | |
4194 | POSTING_READ(GEN7_L3LOG_BASE); | |
4195 | ||
4196 | I915_WRITE(GEN7_MISCCPCTL, misccpctl); | |
4197 | } | |
4198 | ||
f691e2f4 DV |
4199 | void i915_gem_init_swizzling(struct drm_device *dev) |
4200 | { | |
4201 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4202 | ||
11782b02 | 4203 | if (INTEL_INFO(dev)->gen < 5 || |
f691e2f4 DV |
4204 | dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE) |
4205 | return; | |
4206 | ||
4207 | I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) | | |
4208 | DISP_TILE_SURFACE_SWIZZLING); | |
4209 | ||
11782b02 DV |
4210 | if (IS_GEN5(dev)) |
4211 | return; | |
4212 | ||
f691e2f4 DV |
4213 | I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_SWZCTL); |
4214 | if (IS_GEN6(dev)) | |
6b26c86d | 4215 | I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB)); |
8782e26c | 4216 | else if (IS_GEN7(dev)) |
6b26c86d | 4217 | I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB)); |
8782e26c BW |
4218 | else |
4219 | BUG(); | |
f691e2f4 | 4220 | } |
e21af88d | 4221 | |
67b1b571 CW |
4222 | static bool |
4223 | intel_enable_blt(struct drm_device *dev) | |
4224 | { | |
4225 | if (!HAS_BLT(dev)) | |
4226 | return false; | |
4227 | ||
4228 | /* The blitter was dysfunctional on early prototypes */ | |
4229 | if (IS_GEN6(dev) && dev->pdev->revision < 8) { | |
4230 | DRM_INFO("BLT not supported on this pre-production hardware;" | |
4231 | " graphics performance will be degraded.\n"); | |
4232 | return false; | |
4233 | } | |
4234 | ||
4235 | return true; | |
4236 | } | |
4237 | ||
4fc7c971 | 4238 | static int i915_gem_init_rings(struct drm_device *dev) |
8187a2b7 | 4239 | { |
4fc7c971 | 4240 | struct drm_i915_private *dev_priv = dev->dev_private; |
8187a2b7 | 4241 | int ret; |
68f95ba9 | 4242 | |
5c1143bb | 4243 | ret = intel_init_render_ring_buffer(dev); |
68f95ba9 | 4244 | if (ret) |
b6913e4b | 4245 | return ret; |
68f95ba9 CW |
4246 | |
4247 | if (HAS_BSD(dev)) { | |
5c1143bb | 4248 | ret = intel_init_bsd_ring_buffer(dev); |
68f95ba9 CW |
4249 | if (ret) |
4250 | goto cleanup_render_ring; | |
d1b851fc | 4251 | } |
68f95ba9 | 4252 | |
67b1b571 | 4253 | if (intel_enable_blt(dev)) { |
549f7365 CW |
4254 | ret = intel_init_blt_ring_buffer(dev); |
4255 | if (ret) | |
4256 | goto cleanup_bsd_ring; | |
4257 | } | |
4258 | ||
9a8a2213 BW |
4259 | if (HAS_VEBOX(dev)) { |
4260 | ret = intel_init_vebox_ring_buffer(dev); | |
4261 | if (ret) | |
4262 | goto cleanup_blt_ring; | |
4263 | } | |
4264 | ||
4265 | ||
99433931 | 4266 | ret = i915_gem_set_seqno(dev, ((u32)~0 - 0x1000)); |
4fc7c971 | 4267 | if (ret) |
9a8a2213 | 4268 | goto cleanup_vebox_ring; |
4fc7c971 BW |
4269 | |
4270 | return 0; | |
4271 | ||
9a8a2213 BW |
4272 | cleanup_vebox_ring: |
4273 | intel_cleanup_ring_buffer(&dev_priv->ring[VECS]); | |
4fc7c971 BW |
4274 | cleanup_blt_ring: |
4275 | intel_cleanup_ring_buffer(&dev_priv->ring[BCS]); | |
4276 | cleanup_bsd_ring: | |
4277 | intel_cleanup_ring_buffer(&dev_priv->ring[VCS]); | |
4278 | cleanup_render_ring: | |
4279 | intel_cleanup_ring_buffer(&dev_priv->ring[RCS]); | |
4280 | ||
4281 | return ret; | |
4282 | } | |
4283 | ||
4284 | int | |
4285 | i915_gem_init_hw(struct drm_device *dev) | |
4286 | { | |
4287 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4288 | int ret; | |
4289 | ||
4290 | if (INTEL_INFO(dev)->gen < 6 && !intel_enable_gtt()) | |
4291 | return -EIO; | |
4292 | ||
59124506 | 4293 | if (dev_priv->ellc_size) |
05e21cc4 | 4294 | I915_WRITE(HSW_IDICR, I915_READ(HSW_IDICR) | IDIHASHMSK(0xf)); |
4fc7c971 | 4295 | |
88a2b2a3 BW |
4296 | if (HAS_PCH_NOP(dev)) { |
4297 | u32 temp = I915_READ(GEN7_MSG_CTL); | |
4298 | temp &= ~(WAIT_FOR_PCH_FLR_ACK | WAIT_FOR_PCH_RESET_ACK); | |
4299 | I915_WRITE(GEN7_MSG_CTL, temp); | |
4300 | } | |
4301 | ||
4fc7c971 BW |
4302 | i915_gem_l3_remap(dev); |
4303 | ||
4304 | i915_gem_init_swizzling(dev); | |
4305 | ||
4306 | ret = i915_gem_init_rings(dev); | |
99433931 MK |
4307 | if (ret) |
4308 | return ret; | |
4309 | ||
254f965c BW |
4310 | /* |
4311 | * XXX: There was some w/a described somewhere suggesting loading | |
4312 | * contexts before PPGTT. | |
4313 | */ | |
4314 | i915_gem_context_init(dev); | |
b7c36d25 BW |
4315 | if (dev_priv->mm.aliasing_ppgtt) { |
4316 | ret = dev_priv->mm.aliasing_ppgtt->enable(dev); | |
4317 | if (ret) { | |
4318 | i915_gem_cleanup_aliasing_ppgtt(dev); | |
4319 | DRM_INFO("PPGTT enable failed. This is not fatal, but unexpected\n"); | |
4320 | } | |
4321 | } | |
e21af88d | 4322 | |
68f95ba9 | 4323 | return 0; |
8187a2b7 ZN |
4324 | } |
4325 | ||
1070a42b CW |
4326 | int i915_gem_init(struct drm_device *dev) |
4327 | { | |
4328 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1070a42b CW |
4329 | int ret; |
4330 | ||
1070a42b | 4331 | mutex_lock(&dev->struct_mutex); |
d62b4892 JB |
4332 | |
4333 | if (IS_VALLEYVIEW(dev)) { | |
4334 | /* VLVA0 (potential hack), BIOS isn't actually waking us */ | |
4335 | I915_WRITE(VLV_GTLC_WAKE_CTRL, 1); | |
4336 | if (wait_for((I915_READ(VLV_GTLC_PW_STATUS) & 1) == 1, 10)) | |
4337 | DRM_DEBUG_DRIVER("allow wake ack timed out\n"); | |
4338 | } | |
4339 | ||
d7e5008f | 4340 | i915_gem_init_global_gtt(dev); |
d62b4892 | 4341 | |
1070a42b CW |
4342 | ret = i915_gem_init_hw(dev); |
4343 | mutex_unlock(&dev->struct_mutex); | |
4344 | if (ret) { | |
4345 | i915_gem_cleanup_aliasing_ppgtt(dev); | |
4346 | return ret; | |
4347 | } | |
4348 | ||
53ca26ca DV |
4349 | /* Allow hardware batchbuffers unless told otherwise, but not for KMS. */ |
4350 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) | |
4351 | dev_priv->dri1.allow_batchbuffer = 1; | |
1070a42b CW |
4352 | return 0; |
4353 | } | |
4354 | ||
8187a2b7 ZN |
4355 | void |
4356 | i915_gem_cleanup_ringbuffer(struct drm_device *dev) | |
4357 | { | |
4358 | drm_i915_private_t *dev_priv = dev->dev_private; | |
b4519513 | 4359 | struct intel_ring_buffer *ring; |
1ec14ad3 | 4360 | int i; |
8187a2b7 | 4361 | |
b4519513 CW |
4362 | for_each_ring(ring, dev_priv, i) |
4363 | intel_cleanup_ring_buffer(ring); | |
8187a2b7 ZN |
4364 | } |
4365 | ||
673a394b EA |
4366 | int |
4367 | i915_gem_entervt_ioctl(struct drm_device *dev, void *data, | |
4368 | struct drm_file *file_priv) | |
4369 | { | |
db1b76ca | 4370 | struct drm_i915_private *dev_priv = dev->dev_private; |
b4519513 | 4371 | int ret; |
673a394b | 4372 | |
79e53945 JB |
4373 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
4374 | return 0; | |
4375 | ||
1f83fee0 | 4376 | if (i915_reset_in_progress(&dev_priv->gpu_error)) { |
673a394b | 4377 | DRM_ERROR("Reenabling wedged hardware, good luck\n"); |
1f83fee0 | 4378 | atomic_set(&dev_priv->gpu_error.reset_counter, 0); |
673a394b EA |
4379 | } |
4380 | ||
673a394b | 4381 | mutex_lock(&dev->struct_mutex); |
db1b76ca | 4382 | dev_priv->ums.mm_suspended = 0; |
9bb2d6f9 | 4383 | |
f691e2f4 | 4384 | ret = i915_gem_init_hw(dev); |
d816f6ac WF |
4385 | if (ret != 0) { |
4386 | mutex_unlock(&dev->struct_mutex); | |
9bb2d6f9 | 4387 | return ret; |
d816f6ac | 4388 | } |
9bb2d6f9 | 4389 | |
5cef07e1 | 4390 | BUG_ON(!list_empty(&dev_priv->gtt.base.active_list)); |
673a394b | 4391 | mutex_unlock(&dev->struct_mutex); |
dbb19d30 | 4392 | |
5f35308b CW |
4393 | ret = drm_irq_install(dev); |
4394 | if (ret) | |
4395 | goto cleanup_ringbuffer; | |
dbb19d30 | 4396 | |
673a394b | 4397 | return 0; |
5f35308b CW |
4398 | |
4399 | cleanup_ringbuffer: | |
4400 | mutex_lock(&dev->struct_mutex); | |
4401 | i915_gem_cleanup_ringbuffer(dev); | |
db1b76ca | 4402 | dev_priv->ums.mm_suspended = 1; |
5f35308b CW |
4403 | mutex_unlock(&dev->struct_mutex); |
4404 | ||
4405 | return ret; | |
673a394b EA |
4406 | } |
4407 | ||
4408 | int | |
4409 | i915_gem_leavevt_ioctl(struct drm_device *dev, void *data, | |
4410 | struct drm_file *file_priv) | |
4411 | { | |
db1b76ca DV |
4412 | struct drm_i915_private *dev_priv = dev->dev_private; |
4413 | int ret; | |
4414 | ||
79e53945 JB |
4415 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
4416 | return 0; | |
4417 | ||
dbb19d30 | 4418 | drm_irq_uninstall(dev); |
db1b76ca DV |
4419 | |
4420 | mutex_lock(&dev->struct_mutex); | |
4421 | ret = i915_gem_idle(dev); | |
4422 | ||
4423 | /* Hack! Don't let anybody do execbuf while we don't control the chip. | |
4424 | * We need to replace this with a semaphore, or something. | |
4425 | * And not confound ums.mm_suspended! | |
4426 | */ | |
4427 | if (ret != 0) | |
4428 | dev_priv->ums.mm_suspended = 1; | |
4429 | mutex_unlock(&dev->struct_mutex); | |
4430 | ||
4431 | return ret; | |
673a394b EA |
4432 | } |
4433 | ||
4434 | void | |
4435 | i915_gem_lastclose(struct drm_device *dev) | |
4436 | { | |
4437 | int ret; | |
673a394b | 4438 | |
e806b495 EA |
4439 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
4440 | return; | |
4441 | ||
db1b76ca | 4442 | mutex_lock(&dev->struct_mutex); |
6dbe2772 KP |
4443 | ret = i915_gem_idle(dev); |
4444 | if (ret) | |
4445 | DRM_ERROR("failed to idle hardware: %d\n", ret); | |
db1b76ca | 4446 | mutex_unlock(&dev->struct_mutex); |
673a394b EA |
4447 | } |
4448 | ||
64193406 CW |
4449 | static void |
4450 | init_ring_lists(struct intel_ring_buffer *ring) | |
4451 | { | |
4452 | INIT_LIST_HEAD(&ring->active_list); | |
4453 | INIT_LIST_HEAD(&ring->request_list); | |
64193406 CW |
4454 | } |
4455 | ||
fc8c067e BW |
4456 | static void i915_init_vm(struct drm_i915_private *dev_priv, |
4457 | struct i915_address_space *vm) | |
4458 | { | |
4459 | vm->dev = dev_priv->dev; | |
4460 | INIT_LIST_HEAD(&vm->active_list); | |
4461 | INIT_LIST_HEAD(&vm->inactive_list); | |
4462 | INIT_LIST_HEAD(&vm->global_link); | |
4463 | list_add(&vm->global_link, &dev_priv->vm_list); | |
4464 | } | |
4465 | ||
673a394b EA |
4466 | void |
4467 | i915_gem_load(struct drm_device *dev) | |
4468 | { | |
4469 | drm_i915_private_t *dev_priv = dev->dev_private; | |
42dcedd4 CW |
4470 | int i; |
4471 | ||
4472 | dev_priv->slab = | |
4473 | kmem_cache_create("i915_gem_object", | |
4474 | sizeof(struct drm_i915_gem_object), 0, | |
4475 | SLAB_HWCACHE_ALIGN, | |
4476 | NULL); | |
673a394b | 4477 | |
fc8c067e BW |
4478 | INIT_LIST_HEAD(&dev_priv->vm_list); |
4479 | i915_init_vm(dev_priv, &dev_priv->gtt.base); | |
4480 | ||
6c085a72 CW |
4481 | INIT_LIST_HEAD(&dev_priv->mm.unbound_list); |
4482 | INIT_LIST_HEAD(&dev_priv->mm.bound_list); | |
a09ba7fa | 4483 | INIT_LIST_HEAD(&dev_priv->mm.fence_list); |
1ec14ad3 CW |
4484 | for (i = 0; i < I915_NUM_RINGS; i++) |
4485 | init_ring_lists(&dev_priv->ring[i]); | |
4b9de737 | 4486 | for (i = 0; i < I915_MAX_NUM_FENCES; i++) |
007cc8ac | 4487 | INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list); |
673a394b EA |
4488 | INIT_DELAYED_WORK(&dev_priv->mm.retire_work, |
4489 | i915_gem_retire_work_handler); | |
1f83fee0 | 4490 | init_waitqueue_head(&dev_priv->gpu_error.reset_queue); |
31169714 | 4491 | |
94400120 DA |
4492 | /* On GEN3 we really need to make sure the ARB C3 LP bit is set */ |
4493 | if (IS_GEN3(dev)) { | |
50743298 DV |
4494 | I915_WRITE(MI_ARB_STATE, |
4495 | _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE)); | |
94400120 DA |
4496 | } |
4497 | ||
72bfa19c CW |
4498 | dev_priv->relative_constants_mode = I915_EXEC_CONSTANTS_REL_GENERAL; |
4499 | ||
de151cf6 | 4500 | /* Old X drivers will take 0-2 for front, back, depth buffers */ |
b397c836 EA |
4501 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) |
4502 | dev_priv->fence_reg_start = 3; | |
de151cf6 | 4503 | |
42b5aeab VS |
4504 | if (INTEL_INFO(dev)->gen >= 7 && !IS_VALLEYVIEW(dev)) |
4505 | dev_priv->num_fence_regs = 32; | |
4506 | else if (INTEL_INFO(dev)->gen >= 4 || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) | |
de151cf6 JB |
4507 | dev_priv->num_fence_regs = 16; |
4508 | else | |
4509 | dev_priv->num_fence_regs = 8; | |
4510 | ||
b5aa8a0f | 4511 | /* Initialize fence registers to zero */ |
19b2dbde CW |
4512 | INIT_LIST_HEAD(&dev_priv->mm.fence_list); |
4513 | i915_gem_restore_fences(dev); | |
10ed13e4 | 4514 | |
673a394b | 4515 | i915_gem_detect_bit_6_swizzle(dev); |
6b95a207 | 4516 | init_waitqueue_head(&dev_priv->pending_flip_queue); |
17250b71 | 4517 | |
ce453d81 CW |
4518 | dev_priv->mm.interruptible = true; |
4519 | ||
17250b71 CW |
4520 | dev_priv->mm.inactive_shrinker.shrink = i915_gem_inactive_shrink; |
4521 | dev_priv->mm.inactive_shrinker.seeks = DEFAULT_SEEKS; | |
4522 | register_shrinker(&dev_priv->mm.inactive_shrinker); | |
673a394b | 4523 | } |
71acb5eb DA |
4524 | |
4525 | /* | |
4526 | * Create a physically contiguous memory object for this object | |
4527 | * e.g. for cursor + overlay regs | |
4528 | */ | |
995b6762 CW |
4529 | static int i915_gem_init_phys_object(struct drm_device *dev, |
4530 | int id, int size, int align) | |
71acb5eb DA |
4531 | { |
4532 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4533 | struct drm_i915_gem_phys_object *phys_obj; | |
4534 | int ret; | |
4535 | ||
4536 | if (dev_priv->mm.phys_objs[id - 1] || !size) | |
4537 | return 0; | |
4538 | ||
9a298b2a | 4539 | phys_obj = kzalloc(sizeof(struct drm_i915_gem_phys_object), GFP_KERNEL); |
71acb5eb DA |
4540 | if (!phys_obj) |
4541 | return -ENOMEM; | |
4542 | ||
4543 | phys_obj->id = id; | |
4544 | ||
6eeefaf3 | 4545 | phys_obj->handle = drm_pci_alloc(dev, size, align); |
71acb5eb DA |
4546 | if (!phys_obj->handle) { |
4547 | ret = -ENOMEM; | |
4548 | goto kfree_obj; | |
4549 | } | |
4550 | #ifdef CONFIG_X86 | |
4551 | set_memory_wc((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE); | |
4552 | #endif | |
4553 | ||
4554 | dev_priv->mm.phys_objs[id - 1] = phys_obj; | |
4555 | ||
4556 | return 0; | |
4557 | kfree_obj: | |
9a298b2a | 4558 | kfree(phys_obj); |
71acb5eb DA |
4559 | return ret; |
4560 | } | |
4561 | ||
995b6762 | 4562 | static void i915_gem_free_phys_object(struct drm_device *dev, int id) |
71acb5eb DA |
4563 | { |
4564 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4565 | struct drm_i915_gem_phys_object *phys_obj; | |
4566 | ||
4567 | if (!dev_priv->mm.phys_objs[id - 1]) | |
4568 | return; | |
4569 | ||
4570 | phys_obj = dev_priv->mm.phys_objs[id - 1]; | |
4571 | if (phys_obj->cur_obj) { | |
4572 | i915_gem_detach_phys_object(dev, phys_obj->cur_obj); | |
4573 | } | |
4574 | ||
4575 | #ifdef CONFIG_X86 | |
4576 | set_memory_wb((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE); | |
4577 | #endif | |
4578 | drm_pci_free(dev, phys_obj->handle); | |
4579 | kfree(phys_obj); | |
4580 | dev_priv->mm.phys_objs[id - 1] = NULL; | |
4581 | } | |
4582 | ||
4583 | void i915_gem_free_all_phys_object(struct drm_device *dev) | |
4584 | { | |
4585 | int i; | |
4586 | ||
260883c8 | 4587 | for (i = I915_GEM_PHYS_CURSOR_0; i <= I915_MAX_PHYS_OBJECT; i++) |
71acb5eb DA |
4588 | i915_gem_free_phys_object(dev, i); |
4589 | } | |
4590 | ||
4591 | void i915_gem_detach_phys_object(struct drm_device *dev, | |
05394f39 | 4592 | struct drm_i915_gem_object *obj) |
71acb5eb | 4593 | { |
496ad9aa | 4594 | struct address_space *mapping = file_inode(obj->base.filp)->i_mapping; |
e5281ccd | 4595 | char *vaddr; |
71acb5eb | 4596 | int i; |
71acb5eb DA |
4597 | int page_count; |
4598 | ||
05394f39 | 4599 | if (!obj->phys_obj) |
71acb5eb | 4600 | return; |
05394f39 | 4601 | vaddr = obj->phys_obj->handle->vaddr; |
71acb5eb | 4602 | |
05394f39 | 4603 | page_count = obj->base.size / PAGE_SIZE; |
71acb5eb | 4604 | for (i = 0; i < page_count; i++) { |
5949eac4 | 4605 | struct page *page = shmem_read_mapping_page(mapping, i); |
e5281ccd CW |
4606 | if (!IS_ERR(page)) { |
4607 | char *dst = kmap_atomic(page); | |
4608 | memcpy(dst, vaddr + i*PAGE_SIZE, PAGE_SIZE); | |
4609 | kunmap_atomic(dst); | |
4610 | ||
4611 | drm_clflush_pages(&page, 1); | |
4612 | ||
4613 | set_page_dirty(page); | |
4614 | mark_page_accessed(page); | |
4615 | page_cache_release(page); | |
4616 | } | |
71acb5eb | 4617 | } |
e76e9aeb | 4618 | i915_gem_chipset_flush(dev); |
d78b47b9 | 4619 | |
05394f39 CW |
4620 | obj->phys_obj->cur_obj = NULL; |
4621 | obj->phys_obj = NULL; | |
71acb5eb DA |
4622 | } |
4623 | ||
4624 | int | |
4625 | i915_gem_attach_phys_object(struct drm_device *dev, | |
05394f39 | 4626 | struct drm_i915_gem_object *obj, |
6eeefaf3 CW |
4627 | int id, |
4628 | int align) | |
71acb5eb | 4629 | { |
496ad9aa | 4630 | struct address_space *mapping = file_inode(obj->base.filp)->i_mapping; |
71acb5eb | 4631 | drm_i915_private_t *dev_priv = dev->dev_private; |
71acb5eb DA |
4632 | int ret = 0; |
4633 | int page_count; | |
4634 | int i; | |
4635 | ||
4636 | if (id > I915_MAX_PHYS_OBJECT) | |
4637 | return -EINVAL; | |
4638 | ||
05394f39 CW |
4639 | if (obj->phys_obj) { |
4640 | if (obj->phys_obj->id == id) | |
71acb5eb DA |
4641 | return 0; |
4642 | i915_gem_detach_phys_object(dev, obj); | |
4643 | } | |
4644 | ||
71acb5eb DA |
4645 | /* create a new object */ |
4646 | if (!dev_priv->mm.phys_objs[id - 1]) { | |
4647 | ret = i915_gem_init_phys_object(dev, id, | |
05394f39 | 4648 | obj->base.size, align); |
71acb5eb | 4649 | if (ret) { |
05394f39 CW |
4650 | DRM_ERROR("failed to init phys object %d size: %zu\n", |
4651 | id, obj->base.size); | |
e5281ccd | 4652 | return ret; |
71acb5eb DA |
4653 | } |
4654 | } | |
4655 | ||
4656 | /* bind to the object */ | |
05394f39 CW |
4657 | obj->phys_obj = dev_priv->mm.phys_objs[id - 1]; |
4658 | obj->phys_obj->cur_obj = obj; | |
71acb5eb | 4659 | |
05394f39 | 4660 | page_count = obj->base.size / PAGE_SIZE; |
71acb5eb DA |
4661 | |
4662 | for (i = 0; i < page_count; i++) { | |
e5281ccd CW |
4663 | struct page *page; |
4664 | char *dst, *src; | |
4665 | ||
5949eac4 | 4666 | page = shmem_read_mapping_page(mapping, i); |
e5281ccd CW |
4667 | if (IS_ERR(page)) |
4668 | return PTR_ERR(page); | |
71acb5eb | 4669 | |
ff75b9bc | 4670 | src = kmap_atomic(page); |
05394f39 | 4671 | dst = obj->phys_obj->handle->vaddr + (i * PAGE_SIZE); |
71acb5eb | 4672 | memcpy(dst, src, PAGE_SIZE); |
3e4d3af5 | 4673 | kunmap_atomic(src); |
71acb5eb | 4674 | |
e5281ccd CW |
4675 | mark_page_accessed(page); |
4676 | page_cache_release(page); | |
4677 | } | |
d78b47b9 | 4678 | |
71acb5eb | 4679 | return 0; |
71acb5eb DA |
4680 | } |
4681 | ||
4682 | static int | |
05394f39 CW |
4683 | i915_gem_phys_pwrite(struct drm_device *dev, |
4684 | struct drm_i915_gem_object *obj, | |
71acb5eb DA |
4685 | struct drm_i915_gem_pwrite *args, |
4686 | struct drm_file *file_priv) | |
4687 | { | |
05394f39 | 4688 | void *vaddr = obj->phys_obj->handle->vaddr + args->offset; |
2bb4629a | 4689 | char __user *user_data = to_user_ptr(args->data_ptr); |
71acb5eb | 4690 | |
b47b30cc CW |
4691 | if (__copy_from_user_inatomic_nocache(vaddr, user_data, args->size)) { |
4692 | unsigned long unwritten; | |
4693 | ||
4694 | /* The physical object once assigned is fixed for the lifetime | |
4695 | * of the obj, so we can safely drop the lock and continue | |
4696 | * to access vaddr. | |
4697 | */ | |
4698 | mutex_unlock(&dev->struct_mutex); | |
4699 | unwritten = copy_from_user(vaddr, user_data, args->size); | |
4700 | mutex_lock(&dev->struct_mutex); | |
4701 | if (unwritten) | |
4702 | return -EFAULT; | |
4703 | } | |
71acb5eb | 4704 | |
e76e9aeb | 4705 | i915_gem_chipset_flush(dev); |
71acb5eb DA |
4706 | return 0; |
4707 | } | |
b962442e | 4708 | |
f787a5f5 | 4709 | void i915_gem_release(struct drm_device *dev, struct drm_file *file) |
b962442e | 4710 | { |
f787a5f5 | 4711 | struct drm_i915_file_private *file_priv = file->driver_priv; |
b962442e EA |
4712 | |
4713 | /* Clean up our request list when the client is going away, so that | |
4714 | * later retire_requests won't dereference our soon-to-be-gone | |
4715 | * file_priv. | |
4716 | */ | |
1c25595f | 4717 | spin_lock(&file_priv->mm.lock); |
f787a5f5 CW |
4718 | while (!list_empty(&file_priv->mm.request_list)) { |
4719 | struct drm_i915_gem_request *request; | |
4720 | ||
4721 | request = list_first_entry(&file_priv->mm.request_list, | |
4722 | struct drm_i915_gem_request, | |
4723 | client_list); | |
4724 | list_del(&request->client_list); | |
4725 | request->file_priv = NULL; | |
4726 | } | |
1c25595f | 4727 | spin_unlock(&file_priv->mm.lock); |
b962442e | 4728 | } |
31169714 | 4729 | |
5774506f CW |
4730 | static bool mutex_is_locked_by(struct mutex *mutex, struct task_struct *task) |
4731 | { | |
4732 | if (!mutex_is_locked(mutex)) | |
4733 | return false; | |
4734 | ||
4735 | #if defined(CONFIG_SMP) || defined(CONFIG_DEBUG_MUTEXES) | |
4736 | return mutex->owner == task; | |
4737 | #else | |
4738 | /* Since UP may be pre-empted, we cannot assume that we own the lock */ | |
4739 | return false; | |
4740 | #endif | |
4741 | } | |
4742 | ||
31169714 | 4743 | static int |
1495f230 | 4744 | i915_gem_inactive_shrink(struct shrinker *shrinker, struct shrink_control *sc) |
31169714 | 4745 | { |
17250b71 CW |
4746 | struct drm_i915_private *dev_priv = |
4747 | container_of(shrinker, | |
4748 | struct drm_i915_private, | |
4749 | mm.inactive_shrinker); | |
4750 | struct drm_device *dev = dev_priv->dev; | |
6c085a72 | 4751 | struct drm_i915_gem_object *obj; |
1495f230 | 4752 | int nr_to_scan = sc->nr_to_scan; |
5774506f | 4753 | bool unlock = true; |
17250b71 CW |
4754 | int cnt; |
4755 | ||
5774506f CW |
4756 | if (!mutex_trylock(&dev->struct_mutex)) { |
4757 | if (!mutex_is_locked_by(&dev->struct_mutex, current)) | |
4758 | return 0; | |
4759 | ||
677feac2 DV |
4760 | if (dev_priv->mm.shrinker_no_lock_stealing) |
4761 | return 0; | |
4762 | ||
5774506f CW |
4763 | unlock = false; |
4764 | } | |
31169714 | 4765 | |
6c085a72 CW |
4766 | if (nr_to_scan) { |
4767 | nr_to_scan -= i915_gem_purge(dev_priv, nr_to_scan); | |
93927ca5 DV |
4768 | if (nr_to_scan > 0) |
4769 | nr_to_scan -= __i915_gem_shrink(dev_priv, nr_to_scan, | |
4770 | false); | |
6c085a72 CW |
4771 | if (nr_to_scan > 0) |
4772 | i915_gem_shrink_all(dev_priv); | |
31169714 CW |
4773 | } |
4774 | ||
17250b71 | 4775 | cnt = 0; |
35c20a60 | 4776 | list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) |
a5570178 CW |
4777 | if (obj->pages_pin_count == 0) |
4778 | cnt += obj->base.size >> PAGE_SHIFT; | |
fcb4a578 BW |
4779 | |
4780 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) { | |
4781 | if (obj->active) | |
4782 | continue; | |
4783 | ||
a5570178 | 4784 | if (obj->pin_count == 0 && obj->pages_pin_count == 0) |
6c085a72 | 4785 | cnt += obj->base.size >> PAGE_SHIFT; |
fcb4a578 | 4786 | } |
17250b71 | 4787 | |
5774506f CW |
4788 | if (unlock) |
4789 | mutex_unlock(&dev->struct_mutex); | |
6c085a72 | 4790 | return cnt; |
31169714 | 4791 | } |
a70a3148 BW |
4792 | |
4793 | /* All the new VM stuff */ | |
4794 | unsigned long i915_gem_obj_offset(struct drm_i915_gem_object *o, | |
4795 | struct i915_address_space *vm) | |
4796 | { | |
4797 | struct drm_i915_private *dev_priv = o->base.dev->dev_private; | |
4798 | struct i915_vma *vma; | |
4799 | ||
4800 | if (vm == &dev_priv->mm.aliasing_ppgtt->base) | |
4801 | vm = &dev_priv->gtt.base; | |
4802 | ||
4803 | BUG_ON(list_empty(&o->vma_list)); | |
4804 | list_for_each_entry(vma, &o->vma_list, vma_link) { | |
4805 | if (vma->vm == vm) | |
4806 | return vma->node.start; | |
4807 | ||
4808 | } | |
4809 | return -1; | |
4810 | } | |
4811 | ||
4812 | bool i915_gem_obj_bound(struct drm_i915_gem_object *o, | |
4813 | struct i915_address_space *vm) | |
4814 | { | |
4815 | struct i915_vma *vma; | |
4816 | ||
4817 | list_for_each_entry(vma, &o->vma_list, vma_link) | |
8b9c2b94 | 4818 | if (vma->vm == vm && drm_mm_node_allocated(&vma->node)) |
a70a3148 BW |
4819 | return true; |
4820 | ||
4821 | return false; | |
4822 | } | |
4823 | ||
4824 | bool i915_gem_obj_bound_any(struct drm_i915_gem_object *o) | |
4825 | { | |
4826 | struct drm_i915_private *dev_priv = o->base.dev->dev_private; | |
4827 | struct i915_address_space *vm; | |
4828 | ||
4829 | list_for_each_entry(vm, &dev_priv->vm_list, global_link) | |
4830 | if (i915_gem_obj_bound(o, vm)) | |
4831 | return true; | |
4832 | ||
4833 | return false; | |
4834 | } | |
4835 | ||
4836 | unsigned long i915_gem_obj_size(struct drm_i915_gem_object *o, | |
4837 | struct i915_address_space *vm) | |
4838 | { | |
4839 | struct drm_i915_private *dev_priv = o->base.dev->dev_private; | |
4840 | struct i915_vma *vma; | |
4841 | ||
4842 | if (vm == &dev_priv->mm.aliasing_ppgtt->base) | |
4843 | vm = &dev_priv->gtt.base; | |
4844 | ||
4845 | BUG_ON(list_empty(&o->vma_list)); | |
4846 | ||
4847 | list_for_each_entry(vma, &o->vma_list, vma_link) | |
4848 | if (vma->vm == vm) | |
4849 | return vma->node.size; | |
4850 | ||
4851 | return 0; | |
4852 | } | |
4853 | ||
4854 | struct i915_vma *i915_gem_obj_to_vma(struct drm_i915_gem_object *obj, | |
4855 | struct i915_address_space *vm) | |
4856 | { | |
4857 | struct i915_vma *vma; | |
4858 | list_for_each_entry(vma, &obj->vma_list, vma_link) | |
4859 | if (vma->vm == vm) | |
4860 | return vma; | |
4861 | ||
4862 | return NULL; | |
4863 | } |