]>
Commit | Line | Data |
---|---|---|
673a394b EA |
1 | /* |
2 | * Copyright © 2008 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | * | |
26 | */ | |
27 | ||
760285e7 | 28 | #include <drm/drmP.h> |
0de23977 | 29 | #include <drm/drm_vma_manager.h> |
760285e7 | 30 | #include <drm/i915_drm.h> |
673a394b | 31 | #include "i915_drv.h" |
1c5d22f7 | 32 | #include "i915_trace.h" |
652c393a | 33 | #include "intel_drv.h" |
5949eac4 | 34 | #include <linux/shmem_fs.h> |
5a0e3ad6 | 35 | #include <linux/slab.h> |
673a394b | 36 | #include <linux/swap.h> |
79e53945 | 37 | #include <linux/pci.h> |
1286ff73 | 38 | #include <linux/dma-buf.h> |
673a394b | 39 | |
05394f39 | 40 | static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj); |
2c22569b CW |
41 | static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj, |
42 | bool force); | |
07fe0b12 | 43 | static __must_check int |
23f54483 BW |
44 | i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj, |
45 | bool readonly); | |
46 | static __must_check int | |
07fe0b12 BW |
47 | i915_gem_object_bind_to_vm(struct drm_i915_gem_object *obj, |
48 | struct i915_address_space *vm, | |
49 | unsigned alignment, | |
50 | bool map_and_fenceable, | |
51 | bool nonblocking); | |
05394f39 CW |
52 | static int i915_gem_phys_pwrite(struct drm_device *dev, |
53 | struct drm_i915_gem_object *obj, | |
71acb5eb | 54 | struct drm_i915_gem_pwrite *args, |
05394f39 | 55 | struct drm_file *file); |
673a394b | 56 | |
61050808 CW |
57 | static void i915_gem_write_fence(struct drm_device *dev, int reg, |
58 | struct drm_i915_gem_object *obj); | |
59 | static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj, | |
60 | struct drm_i915_fence_reg *fence, | |
61 | bool enable); | |
62 | ||
7dc19d5a DC |
63 | static unsigned long i915_gem_inactive_count(struct shrinker *shrinker, |
64 | struct shrink_control *sc); | |
65 | static unsigned long i915_gem_inactive_scan(struct shrinker *shrinker, | |
66 | struct shrink_control *sc); | |
d9973b43 CW |
67 | static unsigned long i915_gem_purge(struct drm_i915_private *dev_priv, long target); |
68 | static unsigned long i915_gem_shrink_all(struct drm_i915_private *dev_priv); | |
8c59967c | 69 | static void i915_gem_object_truncate(struct drm_i915_gem_object *obj); |
31169714 | 70 | |
c76ce038 CW |
71 | static bool cpu_cache_is_coherent(struct drm_device *dev, |
72 | enum i915_cache_level level) | |
73 | { | |
74 | return HAS_LLC(dev) || level != I915_CACHE_NONE; | |
75 | } | |
76 | ||
2c22569b CW |
77 | static bool cpu_write_needs_clflush(struct drm_i915_gem_object *obj) |
78 | { | |
79 | if (!cpu_cache_is_coherent(obj->base.dev, obj->cache_level)) | |
80 | return true; | |
81 | ||
82 | return obj->pin_display; | |
83 | } | |
84 | ||
61050808 CW |
85 | static inline void i915_gem_object_fence_lost(struct drm_i915_gem_object *obj) |
86 | { | |
87 | if (obj->tiling_mode) | |
88 | i915_gem_release_mmap(obj); | |
89 | ||
90 | /* As we do not have an associated fence register, we will force | |
91 | * a tiling change if we ever need to acquire one. | |
92 | */ | |
5d82e3e6 | 93 | obj->fence_dirty = false; |
61050808 CW |
94 | obj->fence_reg = I915_FENCE_REG_NONE; |
95 | } | |
96 | ||
73aa808f CW |
97 | /* some bookkeeping */ |
98 | static void i915_gem_info_add_obj(struct drm_i915_private *dev_priv, | |
99 | size_t size) | |
100 | { | |
c20e8355 | 101 | spin_lock(&dev_priv->mm.object_stat_lock); |
73aa808f CW |
102 | dev_priv->mm.object_count++; |
103 | dev_priv->mm.object_memory += size; | |
c20e8355 | 104 | spin_unlock(&dev_priv->mm.object_stat_lock); |
73aa808f CW |
105 | } |
106 | ||
107 | static void i915_gem_info_remove_obj(struct drm_i915_private *dev_priv, | |
108 | size_t size) | |
109 | { | |
c20e8355 | 110 | spin_lock(&dev_priv->mm.object_stat_lock); |
73aa808f CW |
111 | dev_priv->mm.object_count--; |
112 | dev_priv->mm.object_memory -= size; | |
c20e8355 | 113 | spin_unlock(&dev_priv->mm.object_stat_lock); |
73aa808f CW |
114 | } |
115 | ||
21dd3734 | 116 | static int |
33196ded | 117 | i915_gem_wait_for_error(struct i915_gpu_error *error) |
30dbf0c0 | 118 | { |
30dbf0c0 CW |
119 | int ret; |
120 | ||
7abb690a DV |
121 | #define EXIT_COND (!i915_reset_in_progress(error) || \ |
122 | i915_terminally_wedged(error)) | |
1f83fee0 | 123 | if (EXIT_COND) |
30dbf0c0 CW |
124 | return 0; |
125 | ||
0a6759c6 DV |
126 | /* |
127 | * Only wait 10 seconds for the gpu reset to complete to avoid hanging | |
128 | * userspace. If it takes that long something really bad is going on and | |
129 | * we should simply try to bail out and fail as gracefully as possible. | |
130 | */ | |
1f83fee0 DV |
131 | ret = wait_event_interruptible_timeout(error->reset_queue, |
132 | EXIT_COND, | |
133 | 10*HZ); | |
0a6759c6 DV |
134 | if (ret == 0) { |
135 | DRM_ERROR("Timed out waiting for the gpu reset to complete\n"); | |
136 | return -EIO; | |
137 | } else if (ret < 0) { | |
30dbf0c0 | 138 | return ret; |
0a6759c6 | 139 | } |
1f83fee0 | 140 | #undef EXIT_COND |
30dbf0c0 | 141 | |
21dd3734 | 142 | return 0; |
30dbf0c0 CW |
143 | } |
144 | ||
54cf91dc | 145 | int i915_mutex_lock_interruptible(struct drm_device *dev) |
76c1dec1 | 146 | { |
33196ded | 147 | struct drm_i915_private *dev_priv = dev->dev_private; |
76c1dec1 CW |
148 | int ret; |
149 | ||
33196ded | 150 | ret = i915_gem_wait_for_error(&dev_priv->gpu_error); |
76c1dec1 CW |
151 | if (ret) |
152 | return ret; | |
153 | ||
154 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
155 | if (ret) | |
156 | return ret; | |
157 | ||
23bc5982 | 158 | WARN_ON(i915_verify_lists(dev)); |
76c1dec1 CW |
159 | return 0; |
160 | } | |
30dbf0c0 | 161 | |
7d1c4804 | 162 | static inline bool |
05394f39 | 163 | i915_gem_object_is_inactive(struct drm_i915_gem_object *obj) |
7d1c4804 | 164 | { |
9843877d | 165 | return i915_gem_obj_bound_any(obj) && !obj->active; |
7d1c4804 CW |
166 | } |
167 | ||
79e53945 JB |
168 | int |
169 | i915_gem_init_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 170 | struct drm_file *file) |
79e53945 | 171 | { |
93d18799 | 172 | struct drm_i915_private *dev_priv = dev->dev_private; |
79e53945 | 173 | struct drm_i915_gem_init *args = data; |
2021746e | 174 | |
7bb6fb8d DV |
175 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
176 | return -ENODEV; | |
177 | ||
2021746e CW |
178 | if (args->gtt_start >= args->gtt_end || |
179 | (args->gtt_end | args->gtt_start) & (PAGE_SIZE - 1)) | |
180 | return -EINVAL; | |
79e53945 | 181 | |
f534bc0b DV |
182 | /* GEM with user mode setting was never supported on ilk and later. */ |
183 | if (INTEL_INFO(dev)->gen >= 5) | |
184 | return -ENODEV; | |
185 | ||
79e53945 | 186 | mutex_lock(&dev->struct_mutex); |
d7e5008f BW |
187 | i915_gem_setup_global_gtt(dev, args->gtt_start, args->gtt_end, |
188 | args->gtt_end); | |
93d18799 | 189 | dev_priv->gtt.mappable_end = args->gtt_end; |
673a394b EA |
190 | mutex_unlock(&dev->struct_mutex); |
191 | ||
2021746e | 192 | return 0; |
673a394b EA |
193 | } |
194 | ||
5a125c3c EA |
195 | int |
196 | i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 197 | struct drm_file *file) |
5a125c3c | 198 | { |
73aa808f | 199 | struct drm_i915_private *dev_priv = dev->dev_private; |
5a125c3c | 200 | struct drm_i915_gem_get_aperture *args = data; |
6299f992 CW |
201 | struct drm_i915_gem_object *obj; |
202 | size_t pinned; | |
5a125c3c | 203 | |
6299f992 | 204 | pinned = 0; |
73aa808f | 205 | mutex_lock(&dev->struct_mutex); |
35c20a60 | 206 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) |
1b50247a | 207 | if (obj->pin_count) |
f343c5f6 | 208 | pinned += i915_gem_obj_ggtt_size(obj); |
73aa808f | 209 | mutex_unlock(&dev->struct_mutex); |
5a125c3c | 210 | |
853ba5d2 | 211 | args->aper_size = dev_priv->gtt.base.total; |
0206e353 | 212 | args->aper_available_size = args->aper_size - pinned; |
6299f992 | 213 | |
5a125c3c EA |
214 | return 0; |
215 | } | |
216 | ||
42dcedd4 CW |
217 | void *i915_gem_object_alloc(struct drm_device *dev) |
218 | { | |
219 | struct drm_i915_private *dev_priv = dev->dev_private; | |
fac15c10 | 220 | return kmem_cache_zalloc(dev_priv->slab, GFP_KERNEL); |
42dcedd4 CW |
221 | } |
222 | ||
223 | void i915_gem_object_free(struct drm_i915_gem_object *obj) | |
224 | { | |
225 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; | |
226 | kmem_cache_free(dev_priv->slab, obj); | |
227 | } | |
228 | ||
ff72145b DA |
229 | static int |
230 | i915_gem_create(struct drm_file *file, | |
231 | struct drm_device *dev, | |
232 | uint64_t size, | |
233 | uint32_t *handle_p) | |
673a394b | 234 | { |
05394f39 | 235 | struct drm_i915_gem_object *obj; |
a1a2d1d3 PP |
236 | int ret; |
237 | u32 handle; | |
673a394b | 238 | |
ff72145b | 239 | size = roundup(size, PAGE_SIZE); |
8ffc0246 CW |
240 | if (size == 0) |
241 | return -EINVAL; | |
673a394b EA |
242 | |
243 | /* Allocate the new object */ | |
ff72145b | 244 | obj = i915_gem_alloc_object(dev, size); |
673a394b EA |
245 | if (obj == NULL) |
246 | return -ENOMEM; | |
247 | ||
05394f39 | 248 | ret = drm_gem_handle_create(file, &obj->base, &handle); |
202f2fef | 249 | /* drop reference from allocate - handle holds it now */ |
d861e338 DV |
250 | drm_gem_object_unreference_unlocked(&obj->base); |
251 | if (ret) | |
252 | return ret; | |
202f2fef | 253 | |
ff72145b | 254 | *handle_p = handle; |
673a394b EA |
255 | return 0; |
256 | } | |
257 | ||
ff72145b DA |
258 | int |
259 | i915_gem_dumb_create(struct drm_file *file, | |
260 | struct drm_device *dev, | |
261 | struct drm_mode_create_dumb *args) | |
262 | { | |
263 | /* have to work out size/pitch and return them */ | |
ed0291fd | 264 | args->pitch = ALIGN(args->width * ((args->bpp + 7) / 8), 64); |
ff72145b DA |
265 | args->size = args->pitch * args->height; |
266 | return i915_gem_create(file, dev, | |
267 | args->size, &args->handle); | |
268 | } | |
269 | ||
ff72145b DA |
270 | /** |
271 | * Creates a new mm object and returns a handle to it. | |
272 | */ | |
273 | int | |
274 | i915_gem_create_ioctl(struct drm_device *dev, void *data, | |
275 | struct drm_file *file) | |
276 | { | |
277 | struct drm_i915_gem_create *args = data; | |
63ed2cb2 | 278 | |
ff72145b DA |
279 | return i915_gem_create(file, dev, |
280 | args->size, &args->handle); | |
281 | } | |
282 | ||
8461d226 DV |
283 | static inline int |
284 | __copy_to_user_swizzled(char __user *cpu_vaddr, | |
285 | const char *gpu_vaddr, int gpu_offset, | |
286 | int length) | |
287 | { | |
288 | int ret, cpu_offset = 0; | |
289 | ||
290 | while (length > 0) { | |
291 | int cacheline_end = ALIGN(gpu_offset + 1, 64); | |
292 | int this_length = min(cacheline_end - gpu_offset, length); | |
293 | int swizzled_gpu_offset = gpu_offset ^ 64; | |
294 | ||
295 | ret = __copy_to_user(cpu_vaddr + cpu_offset, | |
296 | gpu_vaddr + swizzled_gpu_offset, | |
297 | this_length); | |
298 | if (ret) | |
299 | return ret + length; | |
300 | ||
301 | cpu_offset += this_length; | |
302 | gpu_offset += this_length; | |
303 | length -= this_length; | |
304 | } | |
305 | ||
306 | return 0; | |
307 | } | |
308 | ||
8c59967c | 309 | static inline int |
4f0c7cfb BW |
310 | __copy_from_user_swizzled(char *gpu_vaddr, int gpu_offset, |
311 | const char __user *cpu_vaddr, | |
8c59967c DV |
312 | int length) |
313 | { | |
314 | int ret, cpu_offset = 0; | |
315 | ||
316 | while (length > 0) { | |
317 | int cacheline_end = ALIGN(gpu_offset + 1, 64); | |
318 | int this_length = min(cacheline_end - gpu_offset, length); | |
319 | int swizzled_gpu_offset = gpu_offset ^ 64; | |
320 | ||
321 | ret = __copy_from_user(gpu_vaddr + swizzled_gpu_offset, | |
322 | cpu_vaddr + cpu_offset, | |
323 | this_length); | |
324 | if (ret) | |
325 | return ret + length; | |
326 | ||
327 | cpu_offset += this_length; | |
328 | gpu_offset += this_length; | |
329 | length -= this_length; | |
330 | } | |
331 | ||
332 | return 0; | |
333 | } | |
334 | ||
d174bd64 DV |
335 | /* Per-page copy function for the shmem pread fastpath. |
336 | * Flushes invalid cachelines before reading the target if | |
337 | * needs_clflush is set. */ | |
eb01459f | 338 | static int |
d174bd64 DV |
339 | shmem_pread_fast(struct page *page, int shmem_page_offset, int page_length, |
340 | char __user *user_data, | |
341 | bool page_do_bit17_swizzling, bool needs_clflush) | |
342 | { | |
343 | char *vaddr; | |
344 | int ret; | |
345 | ||
e7e58eb5 | 346 | if (unlikely(page_do_bit17_swizzling)) |
d174bd64 DV |
347 | return -EINVAL; |
348 | ||
349 | vaddr = kmap_atomic(page); | |
350 | if (needs_clflush) | |
351 | drm_clflush_virt_range(vaddr + shmem_page_offset, | |
352 | page_length); | |
353 | ret = __copy_to_user_inatomic(user_data, | |
354 | vaddr + shmem_page_offset, | |
355 | page_length); | |
356 | kunmap_atomic(vaddr); | |
357 | ||
f60d7f0c | 358 | return ret ? -EFAULT : 0; |
d174bd64 DV |
359 | } |
360 | ||
23c18c71 DV |
361 | static void |
362 | shmem_clflush_swizzled_range(char *addr, unsigned long length, | |
363 | bool swizzled) | |
364 | { | |
e7e58eb5 | 365 | if (unlikely(swizzled)) { |
23c18c71 DV |
366 | unsigned long start = (unsigned long) addr; |
367 | unsigned long end = (unsigned long) addr + length; | |
368 | ||
369 | /* For swizzling simply ensure that we always flush both | |
370 | * channels. Lame, but simple and it works. Swizzled | |
371 | * pwrite/pread is far from a hotpath - current userspace | |
372 | * doesn't use it at all. */ | |
373 | start = round_down(start, 128); | |
374 | end = round_up(end, 128); | |
375 | ||
376 | drm_clflush_virt_range((void *)start, end - start); | |
377 | } else { | |
378 | drm_clflush_virt_range(addr, length); | |
379 | } | |
380 | ||
381 | } | |
382 | ||
d174bd64 DV |
383 | /* Only difference to the fast-path function is that this can handle bit17 |
384 | * and uses non-atomic copy and kmap functions. */ | |
385 | static int | |
386 | shmem_pread_slow(struct page *page, int shmem_page_offset, int page_length, | |
387 | char __user *user_data, | |
388 | bool page_do_bit17_swizzling, bool needs_clflush) | |
389 | { | |
390 | char *vaddr; | |
391 | int ret; | |
392 | ||
393 | vaddr = kmap(page); | |
394 | if (needs_clflush) | |
23c18c71 DV |
395 | shmem_clflush_swizzled_range(vaddr + shmem_page_offset, |
396 | page_length, | |
397 | page_do_bit17_swizzling); | |
d174bd64 DV |
398 | |
399 | if (page_do_bit17_swizzling) | |
400 | ret = __copy_to_user_swizzled(user_data, | |
401 | vaddr, shmem_page_offset, | |
402 | page_length); | |
403 | else | |
404 | ret = __copy_to_user(user_data, | |
405 | vaddr + shmem_page_offset, | |
406 | page_length); | |
407 | kunmap(page); | |
408 | ||
f60d7f0c | 409 | return ret ? - EFAULT : 0; |
d174bd64 DV |
410 | } |
411 | ||
eb01459f | 412 | static int |
dbf7bff0 DV |
413 | i915_gem_shmem_pread(struct drm_device *dev, |
414 | struct drm_i915_gem_object *obj, | |
415 | struct drm_i915_gem_pread *args, | |
416 | struct drm_file *file) | |
eb01459f | 417 | { |
8461d226 | 418 | char __user *user_data; |
eb01459f | 419 | ssize_t remain; |
8461d226 | 420 | loff_t offset; |
eb2c0c81 | 421 | int shmem_page_offset, page_length, ret = 0; |
8461d226 | 422 | int obj_do_bit17_swizzling, page_do_bit17_swizzling; |
96d79b52 | 423 | int prefaulted = 0; |
8489731c | 424 | int needs_clflush = 0; |
67d5a50c | 425 | struct sg_page_iter sg_iter; |
eb01459f | 426 | |
2bb4629a | 427 | user_data = to_user_ptr(args->data_ptr); |
eb01459f EA |
428 | remain = args->size; |
429 | ||
8461d226 | 430 | obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj); |
eb01459f | 431 | |
8489731c DV |
432 | if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU)) { |
433 | /* If we're not in the cpu read domain, set ourself into the gtt | |
434 | * read domain and manually flush cachelines (if required). This | |
435 | * optimizes for the case when the gpu will dirty the data | |
436 | * anyway again before the next pread happens. */ | |
c76ce038 | 437 | needs_clflush = !cpu_cache_is_coherent(dev, obj->cache_level); |
23f54483 BW |
438 | ret = i915_gem_object_wait_rendering(obj, true); |
439 | if (ret) | |
440 | return ret; | |
8489731c | 441 | } |
eb01459f | 442 | |
f60d7f0c CW |
443 | ret = i915_gem_object_get_pages(obj); |
444 | if (ret) | |
445 | return ret; | |
446 | ||
447 | i915_gem_object_pin_pages(obj); | |
448 | ||
8461d226 | 449 | offset = args->offset; |
eb01459f | 450 | |
67d5a50c ID |
451 | for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, |
452 | offset >> PAGE_SHIFT) { | |
2db76d7c | 453 | struct page *page = sg_page_iter_page(&sg_iter); |
9da3da66 CW |
454 | |
455 | if (remain <= 0) | |
456 | break; | |
457 | ||
eb01459f EA |
458 | /* Operation in this page |
459 | * | |
eb01459f | 460 | * shmem_page_offset = offset within page in shmem file |
eb01459f EA |
461 | * page_length = bytes to copy for this page |
462 | */ | |
c8cbbb8b | 463 | shmem_page_offset = offset_in_page(offset); |
eb01459f EA |
464 | page_length = remain; |
465 | if ((shmem_page_offset + page_length) > PAGE_SIZE) | |
466 | page_length = PAGE_SIZE - shmem_page_offset; | |
eb01459f | 467 | |
8461d226 DV |
468 | page_do_bit17_swizzling = obj_do_bit17_swizzling && |
469 | (page_to_phys(page) & (1 << 17)) != 0; | |
470 | ||
d174bd64 DV |
471 | ret = shmem_pread_fast(page, shmem_page_offset, page_length, |
472 | user_data, page_do_bit17_swizzling, | |
473 | needs_clflush); | |
474 | if (ret == 0) | |
475 | goto next_page; | |
dbf7bff0 | 476 | |
dbf7bff0 DV |
477 | mutex_unlock(&dev->struct_mutex); |
478 | ||
0b74b508 | 479 | if (likely(!i915_prefault_disable) && !prefaulted) { |
f56f821f | 480 | ret = fault_in_multipages_writeable(user_data, remain); |
96d79b52 DV |
481 | /* Userspace is tricking us, but we've already clobbered |
482 | * its pages with the prefault and promised to write the | |
483 | * data up to the first fault. Hence ignore any errors | |
484 | * and just continue. */ | |
485 | (void)ret; | |
486 | prefaulted = 1; | |
487 | } | |
eb01459f | 488 | |
d174bd64 DV |
489 | ret = shmem_pread_slow(page, shmem_page_offset, page_length, |
490 | user_data, page_do_bit17_swizzling, | |
491 | needs_clflush); | |
eb01459f | 492 | |
dbf7bff0 | 493 | mutex_lock(&dev->struct_mutex); |
f60d7f0c | 494 | |
dbf7bff0 | 495 | next_page: |
e5281ccd | 496 | mark_page_accessed(page); |
e5281ccd | 497 | |
f60d7f0c | 498 | if (ret) |
8461d226 | 499 | goto out; |
8461d226 | 500 | |
eb01459f | 501 | remain -= page_length; |
8461d226 | 502 | user_data += page_length; |
eb01459f EA |
503 | offset += page_length; |
504 | } | |
505 | ||
4f27b75d | 506 | out: |
f60d7f0c CW |
507 | i915_gem_object_unpin_pages(obj); |
508 | ||
eb01459f EA |
509 | return ret; |
510 | } | |
511 | ||
673a394b EA |
512 | /** |
513 | * Reads data from the object referenced by handle. | |
514 | * | |
515 | * On error, the contents of *data are undefined. | |
516 | */ | |
517 | int | |
518 | i915_gem_pread_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 519 | struct drm_file *file) |
673a394b EA |
520 | { |
521 | struct drm_i915_gem_pread *args = data; | |
05394f39 | 522 | struct drm_i915_gem_object *obj; |
35b62a89 | 523 | int ret = 0; |
673a394b | 524 | |
51311d0a CW |
525 | if (args->size == 0) |
526 | return 0; | |
527 | ||
528 | if (!access_ok(VERIFY_WRITE, | |
2bb4629a | 529 | to_user_ptr(args->data_ptr), |
51311d0a CW |
530 | args->size)) |
531 | return -EFAULT; | |
532 | ||
4f27b75d | 533 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 534 | if (ret) |
4f27b75d | 535 | return ret; |
673a394b | 536 | |
05394f39 | 537 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 538 | if (&obj->base == NULL) { |
1d7cfea1 CW |
539 | ret = -ENOENT; |
540 | goto unlock; | |
4f27b75d | 541 | } |
673a394b | 542 | |
7dcd2499 | 543 | /* Bounds check source. */ |
05394f39 CW |
544 | if (args->offset > obj->base.size || |
545 | args->size > obj->base.size - args->offset) { | |
ce9d419d | 546 | ret = -EINVAL; |
35b62a89 | 547 | goto out; |
ce9d419d CW |
548 | } |
549 | ||
1286ff73 DV |
550 | /* prime objects have no backing filp to GEM pread/pwrite |
551 | * pages from. | |
552 | */ | |
553 | if (!obj->base.filp) { | |
554 | ret = -EINVAL; | |
555 | goto out; | |
556 | } | |
557 | ||
db53a302 CW |
558 | trace_i915_gem_object_pread(obj, args->offset, args->size); |
559 | ||
dbf7bff0 | 560 | ret = i915_gem_shmem_pread(dev, obj, args, file); |
673a394b | 561 | |
35b62a89 | 562 | out: |
05394f39 | 563 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 564 | unlock: |
4f27b75d | 565 | mutex_unlock(&dev->struct_mutex); |
eb01459f | 566 | return ret; |
673a394b EA |
567 | } |
568 | ||
0839ccb8 KP |
569 | /* This is the fast write path which cannot handle |
570 | * page faults in the source data | |
9b7530cc | 571 | */ |
0839ccb8 KP |
572 | |
573 | static inline int | |
574 | fast_user_write(struct io_mapping *mapping, | |
575 | loff_t page_base, int page_offset, | |
576 | char __user *user_data, | |
577 | int length) | |
9b7530cc | 578 | { |
4f0c7cfb BW |
579 | void __iomem *vaddr_atomic; |
580 | void *vaddr; | |
0839ccb8 | 581 | unsigned long unwritten; |
9b7530cc | 582 | |
3e4d3af5 | 583 | vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base); |
4f0c7cfb BW |
584 | /* We can use the cpu mem copy function because this is X86. */ |
585 | vaddr = (void __force*)vaddr_atomic + page_offset; | |
586 | unwritten = __copy_from_user_inatomic_nocache(vaddr, | |
0839ccb8 | 587 | user_data, length); |
3e4d3af5 | 588 | io_mapping_unmap_atomic(vaddr_atomic); |
fbd5a26d | 589 | return unwritten; |
0839ccb8 KP |
590 | } |
591 | ||
3de09aa3 EA |
592 | /** |
593 | * This is the fast pwrite path, where we copy the data directly from the | |
594 | * user into the GTT, uncached. | |
595 | */ | |
673a394b | 596 | static int |
05394f39 CW |
597 | i915_gem_gtt_pwrite_fast(struct drm_device *dev, |
598 | struct drm_i915_gem_object *obj, | |
3de09aa3 | 599 | struct drm_i915_gem_pwrite *args, |
05394f39 | 600 | struct drm_file *file) |
673a394b | 601 | { |
0839ccb8 | 602 | drm_i915_private_t *dev_priv = dev->dev_private; |
673a394b | 603 | ssize_t remain; |
0839ccb8 | 604 | loff_t offset, page_base; |
673a394b | 605 | char __user *user_data; |
935aaa69 DV |
606 | int page_offset, page_length, ret; |
607 | ||
c37e2204 | 608 | ret = i915_gem_obj_ggtt_pin(obj, 0, true, true); |
935aaa69 DV |
609 | if (ret) |
610 | goto out; | |
611 | ||
612 | ret = i915_gem_object_set_to_gtt_domain(obj, true); | |
613 | if (ret) | |
614 | goto out_unpin; | |
615 | ||
616 | ret = i915_gem_object_put_fence(obj); | |
617 | if (ret) | |
618 | goto out_unpin; | |
673a394b | 619 | |
2bb4629a | 620 | user_data = to_user_ptr(args->data_ptr); |
673a394b | 621 | remain = args->size; |
673a394b | 622 | |
f343c5f6 | 623 | offset = i915_gem_obj_ggtt_offset(obj) + args->offset; |
673a394b EA |
624 | |
625 | while (remain > 0) { | |
626 | /* Operation in this page | |
627 | * | |
0839ccb8 KP |
628 | * page_base = page offset within aperture |
629 | * page_offset = offset within page | |
630 | * page_length = bytes to copy for this page | |
673a394b | 631 | */ |
c8cbbb8b CW |
632 | page_base = offset & PAGE_MASK; |
633 | page_offset = offset_in_page(offset); | |
0839ccb8 KP |
634 | page_length = remain; |
635 | if ((page_offset + remain) > PAGE_SIZE) | |
636 | page_length = PAGE_SIZE - page_offset; | |
637 | ||
0839ccb8 | 638 | /* If we get a fault while copying data, then (presumably) our |
3de09aa3 EA |
639 | * source page isn't available. Return the error and we'll |
640 | * retry in the slow path. | |
0839ccb8 | 641 | */ |
5d4545ae | 642 | if (fast_user_write(dev_priv->gtt.mappable, page_base, |
935aaa69 DV |
643 | page_offset, user_data, page_length)) { |
644 | ret = -EFAULT; | |
645 | goto out_unpin; | |
646 | } | |
673a394b | 647 | |
0839ccb8 KP |
648 | remain -= page_length; |
649 | user_data += page_length; | |
650 | offset += page_length; | |
673a394b | 651 | } |
673a394b | 652 | |
935aaa69 DV |
653 | out_unpin: |
654 | i915_gem_object_unpin(obj); | |
655 | out: | |
3de09aa3 | 656 | return ret; |
673a394b EA |
657 | } |
658 | ||
d174bd64 DV |
659 | /* Per-page copy function for the shmem pwrite fastpath. |
660 | * Flushes invalid cachelines before writing to the target if | |
661 | * needs_clflush_before is set and flushes out any written cachelines after | |
662 | * writing if needs_clflush is set. */ | |
3043c60c | 663 | static int |
d174bd64 DV |
664 | shmem_pwrite_fast(struct page *page, int shmem_page_offset, int page_length, |
665 | char __user *user_data, | |
666 | bool page_do_bit17_swizzling, | |
667 | bool needs_clflush_before, | |
668 | bool needs_clflush_after) | |
673a394b | 669 | { |
d174bd64 | 670 | char *vaddr; |
673a394b | 671 | int ret; |
3de09aa3 | 672 | |
e7e58eb5 | 673 | if (unlikely(page_do_bit17_swizzling)) |
d174bd64 | 674 | return -EINVAL; |
3de09aa3 | 675 | |
d174bd64 DV |
676 | vaddr = kmap_atomic(page); |
677 | if (needs_clflush_before) | |
678 | drm_clflush_virt_range(vaddr + shmem_page_offset, | |
679 | page_length); | |
680 | ret = __copy_from_user_inatomic_nocache(vaddr + shmem_page_offset, | |
681 | user_data, | |
682 | page_length); | |
683 | if (needs_clflush_after) | |
684 | drm_clflush_virt_range(vaddr + shmem_page_offset, | |
685 | page_length); | |
686 | kunmap_atomic(vaddr); | |
3de09aa3 | 687 | |
755d2218 | 688 | return ret ? -EFAULT : 0; |
3de09aa3 EA |
689 | } |
690 | ||
d174bd64 DV |
691 | /* Only difference to the fast-path function is that this can handle bit17 |
692 | * and uses non-atomic copy and kmap functions. */ | |
3043c60c | 693 | static int |
d174bd64 DV |
694 | shmem_pwrite_slow(struct page *page, int shmem_page_offset, int page_length, |
695 | char __user *user_data, | |
696 | bool page_do_bit17_swizzling, | |
697 | bool needs_clflush_before, | |
698 | bool needs_clflush_after) | |
673a394b | 699 | { |
d174bd64 DV |
700 | char *vaddr; |
701 | int ret; | |
e5281ccd | 702 | |
d174bd64 | 703 | vaddr = kmap(page); |
e7e58eb5 | 704 | if (unlikely(needs_clflush_before || page_do_bit17_swizzling)) |
23c18c71 DV |
705 | shmem_clflush_swizzled_range(vaddr + shmem_page_offset, |
706 | page_length, | |
707 | page_do_bit17_swizzling); | |
d174bd64 DV |
708 | if (page_do_bit17_swizzling) |
709 | ret = __copy_from_user_swizzled(vaddr, shmem_page_offset, | |
e5281ccd CW |
710 | user_data, |
711 | page_length); | |
d174bd64 DV |
712 | else |
713 | ret = __copy_from_user(vaddr + shmem_page_offset, | |
714 | user_data, | |
715 | page_length); | |
716 | if (needs_clflush_after) | |
23c18c71 DV |
717 | shmem_clflush_swizzled_range(vaddr + shmem_page_offset, |
718 | page_length, | |
719 | page_do_bit17_swizzling); | |
d174bd64 | 720 | kunmap(page); |
40123c1f | 721 | |
755d2218 | 722 | return ret ? -EFAULT : 0; |
40123c1f EA |
723 | } |
724 | ||
40123c1f | 725 | static int |
e244a443 DV |
726 | i915_gem_shmem_pwrite(struct drm_device *dev, |
727 | struct drm_i915_gem_object *obj, | |
728 | struct drm_i915_gem_pwrite *args, | |
729 | struct drm_file *file) | |
40123c1f | 730 | { |
40123c1f | 731 | ssize_t remain; |
8c59967c DV |
732 | loff_t offset; |
733 | char __user *user_data; | |
eb2c0c81 | 734 | int shmem_page_offset, page_length, ret = 0; |
8c59967c | 735 | int obj_do_bit17_swizzling, page_do_bit17_swizzling; |
e244a443 | 736 | int hit_slowpath = 0; |
58642885 DV |
737 | int needs_clflush_after = 0; |
738 | int needs_clflush_before = 0; | |
67d5a50c | 739 | struct sg_page_iter sg_iter; |
40123c1f | 740 | |
2bb4629a | 741 | user_data = to_user_ptr(args->data_ptr); |
40123c1f EA |
742 | remain = args->size; |
743 | ||
8c59967c | 744 | obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj); |
40123c1f | 745 | |
58642885 DV |
746 | if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) { |
747 | /* If we're not in the cpu write domain, set ourself into the gtt | |
748 | * write domain and manually flush cachelines (if required). This | |
749 | * optimizes for the case when the gpu will use the data | |
750 | * right away and we therefore have to clflush anyway. */ | |
2c22569b | 751 | needs_clflush_after = cpu_write_needs_clflush(obj); |
23f54483 BW |
752 | ret = i915_gem_object_wait_rendering(obj, false); |
753 | if (ret) | |
754 | return ret; | |
58642885 | 755 | } |
c76ce038 CW |
756 | /* Same trick applies to invalidate partially written cachelines read |
757 | * before writing. */ | |
758 | if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) | |
759 | needs_clflush_before = | |
760 | !cpu_cache_is_coherent(dev, obj->cache_level); | |
58642885 | 761 | |
755d2218 CW |
762 | ret = i915_gem_object_get_pages(obj); |
763 | if (ret) | |
764 | return ret; | |
765 | ||
766 | i915_gem_object_pin_pages(obj); | |
767 | ||
673a394b | 768 | offset = args->offset; |
05394f39 | 769 | obj->dirty = 1; |
673a394b | 770 | |
67d5a50c ID |
771 | for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, |
772 | offset >> PAGE_SHIFT) { | |
2db76d7c | 773 | struct page *page = sg_page_iter_page(&sg_iter); |
58642885 | 774 | int partial_cacheline_write; |
e5281ccd | 775 | |
9da3da66 CW |
776 | if (remain <= 0) |
777 | break; | |
778 | ||
40123c1f EA |
779 | /* Operation in this page |
780 | * | |
40123c1f | 781 | * shmem_page_offset = offset within page in shmem file |
40123c1f EA |
782 | * page_length = bytes to copy for this page |
783 | */ | |
c8cbbb8b | 784 | shmem_page_offset = offset_in_page(offset); |
40123c1f EA |
785 | |
786 | page_length = remain; | |
787 | if ((shmem_page_offset + page_length) > PAGE_SIZE) | |
788 | page_length = PAGE_SIZE - shmem_page_offset; | |
40123c1f | 789 | |
58642885 DV |
790 | /* If we don't overwrite a cacheline completely we need to be |
791 | * careful to have up-to-date data by first clflushing. Don't | |
792 | * overcomplicate things and flush the entire patch. */ | |
793 | partial_cacheline_write = needs_clflush_before && | |
794 | ((shmem_page_offset | page_length) | |
795 | & (boot_cpu_data.x86_clflush_size - 1)); | |
796 | ||
8c59967c DV |
797 | page_do_bit17_swizzling = obj_do_bit17_swizzling && |
798 | (page_to_phys(page) & (1 << 17)) != 0; | |
799 | ||
d174bd64 DV |
800 | ret = shmem_pwrite_fast(page, shmem_page_offset, page_length, |
801 | user_data, page_do_bit17_swizzling, | |
802 | partial_cacheline_write, | |
803 | needs_clflush_after); | |
804 | if (ret == 0) | |
805 | goto next_page; | |
e244a443 DV |
806 | |
807 | hit_slowpath = 1; | |
e244a443 | 808 | mutex_unlock(&dev->struct_mutex); |
d174bd64 DV |
809 | ret = shmem_pwrite_slow(page, shmem_page_offset, page_length, |
810 | user_data, page_do_bit17_swizzling, | |
811 | partial_cacheline_write, | |
812 | needs_clflush_after); | |
40123c1f | 813 | |
e244a443 | 814 | mutex_lock(&dev->struct_mutex); |
755d2218 | 815 | |
e244a443 | 816 | next_page: |
e5281ccd CW |
817 | set_page_dirty(page); |
818 | mark_page_accessed(page); | |
e5281ccd | 819 | |
755d2218 | 820 | if (ret) |
8c59967c | 821 | goto out; |
8c59967c | 822 | |
40123c1f | 823 | remain -= page_length; |
8c59967c | 824 | user_data += page_length; |
40123c1f | 825 | offset += page_length; |
673a394b EA |
826 | } |
827 | ||
fbd5a26d | 828 | out: |
755d2218 CW |
829 | i915_gem_object_unpin_pages(obj); |
830 | ||
e244a443 | 831 | if (hit_slowpath) { |
8dcf015e DV |
832 | /* |
833 | * Fixup: Flush cpu caches in case we didn't flush the dirty | |
834 | * cachelines in-line while writing and the object moved | |
835 | * out of the cpu write domain while we've dropped the lock. | |
836 | */ | |
837 | if (!needs_clflush_after && | |
838 | obj->base.write_domain != I915_GEM_DOMAIN_CPU) { | |
000433b6 CW |
839 | if (i915_gem_clflush_object(obj, obj->pin_display)) |
840 | i915_gem_chipset_flush(dev); | |
e244a443 | 841 | } |
8c59967c | 842 | } |
673a394b | 843 | |
58642885 | 844 | if (needs_clflush_after) |
e76e9aeb | 845 | i915_gem_chipset_flush(dev); |
58642885 | 846 | |
40123c1f | 847 | return ret; |
673a394b EA |
848 | } |
849 | ||
850 | /** | |
851 | * Writes data to the object referenced by handle. | |
852 | * | |
853 | * On error, the contents of the buffer that were to be modified are undefined. | |
854 | */ | |
855 | int | |
856 | i915_gem_pwrite_ioctl(struct drm_device *dev, void *data, | |
fbd5a26d | 857 | struct drm_file *file) |
673a394b EA |
858 | { |
859 | struct drm_i915_gem_pwrite *args = data; | |
05394f39 | 860 | struct drm_i915_gem_object *obj; |
51311d0a CW |
861 | int ret; |
862 | ||
863 | if (args->size == 0) | |
864 | return 0; | |
865 | ||
866 | if (!access_ok(VERIFY_READ, | |
2bb4629a | 867 | to_user_ptr(args->data_ptr), |
51311d0a CW |
868 | args->size)) |
869 | return -EFAULT; | |
870 | ||
0b74b508 XZ |
871 | if (likely(!i915_prefault_disable)) { |
872 | ret = fault_in_multipages_readable(to_user_ptr(args->data_ptr), | |
873 | args->size); | |
874 | if (ret) | |
875 | return -EFAULT; | |
876 | } | |
673a394b | 877 | |
fbd5a26d | 878 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 879 | if (ret) |
fbd5a26d | 880 | return ret; |
1d7cfea1 | 881 | |
05394f39 | 882 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 883 | if (&obj->base == NULL) { |
1d7cfea1 CW |
884 | ret = -ENOENT; |
885 | goto unlock; | |
fbd5a26d | 886 | } |
673a394b | 887 | |
7dcd2499 | 888 | /* Bounds check destination. */ |
05394f39 CW |
889 | if (args->offset > obj->base.size || |
890 | args->size > obj->base.size - args->offset) { | |
ce9d419d | 891 | ret = -EINVAL; |
35b62a89 | 892 | goto out; |
ce9d419d CW |
893 | } |
894 | ||
1286ff73 DV |
895 | /* prime objects have no backing filp to GEM pread/pwrite |
896 | * pages from. | |
897 | */ | |
898 | if (!obj->base.filp) { | |
899 | ret = -EINVAL; | |
900 | goto out; | |
901 | } | |
902 | ||
db53a302 CW |
903 | trace_i915_gem_object_pwrite(obj, args->offset, args->size); |
904 | ||
935aaa69 | 905 | ret = -EFAULT; |
673a394b EA |
906 | /* We can only do the GTT pwrite on untiled buffers, as otherwise |
907 | * it would end up going through the fenced access, and we'll get | |
908 | * different detiling behavior between reading and writing. | |
909 | * pread/pwrite currently are reading and writing from the CPU | |
910 | * perspective, requiring manual detiling by the client. | |
911 | */ | |
5c0480f2 | 912 | if (obj->phys_obj) { |
fbd5a26d | 913 | ret = i915_gem_phys_pwrite(dev, obj, args, file); |
5c0480f2 DV |
914 | goto out; |
915 | } | |
916 | ||
2c22569b CW |
917 | if (obj->tiling_mode == I915_TILING_NONE && |
918 | obj->base.write_domain != I915_GEM_DOMAIN_CPU && | |
919 | cpu_write_needs_clflush(obj)) { | |
fbd5a26d | 920 | ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file); |
935aaa69 DV |
921 | /* Note that the gtt paths might fail with non-page-backed user |
922 | * pointers (e.g. gtt mappings when moving data between | |
923 | * textures). Fallback to the shmem path in that case. */ | |
fbd5a26d | 924 | } |
673a394b | 925 | |
86a1ee26 | 926 | if (ret == -EFAULT || ret == -ENOSPC) |
935aaa69 | 927 | ret = i915_gem_shmem_pwrite(dev, obj, args, file); |
5c0480f2 | 928 | |
35b62a89 | 929 | out: |
05394f39 | 930 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 931 | unlock: |
fbd5a26d | 932 | mutex_unlock(&dev->struct_mutex); |
673a394b EA |
933 | return ret; |
934 | } | |
935 | ||
b361237b | 936 | int |
33196ded | 937 | i915_gem_check_wedge(struct i915_gpu_error *error, |
b361237b CW |
938 | bool interruptible) |
939 | { | |
1f83fee0 | 940 | if (i915_reset_in_progress(error)) { |
b361237b CW |
941 | /* Non-interruptible callers can't handle -EAGAIN, hence return |
942 | * -EIO unconditionally for these. */ | |
943 | if (!interruptible) | |
944 | return -EIO; | |
945 | ||
1f83fee0 DV |
946 | /* Recovery complete, but the reset failed ... */ |
947 | if (i915_terminally_wedged(error)) | |
b361237b CW |
948 | return -EIO; |
949 | ||
950 | return -EAGAIN; | |
951 | } | |
952 | ||
953 | return 0; | |
954 | } | |
955 | ||
956 | /* | |
957 | * Compare seqno against outstanding lazy request. Emit a request if they are | |
958 | * equal. | |
959 | */ | |
960 | static int | |
961 | i915_gem_check_olr(struct intel_ring_buffer *ring, u32 seqno) | |
962 | { | |
963 | int ret; | |
964 | ||
965 | BUG_ON(!mutex_is_locked(&ring->dev->struct_mutex)); | |
966 | ||
967 | ret = 0; | |
1823521d | 968 | if (seqno == ring->outstanding_lazy_seqno) |
0025c077 | 969 | ret = i915_add_request(ring, NULL); |
b361237b CW |
970 | |
971 | return ret; | |
972 | } | |
973 | ||
094f9a54 CW |
974 | static void fake_irq(unsigned long data) |
975 | { | |
976 | wake_up_process((struct task_struct *)data); | |
977 | } | |
978 | ||
979 | static bool missed_irq(struct drm_i915_private *dev_priv, | |
980 | struct intel_ring_buffer *ring) | |
981 | { | |
982 | return test_bit(ring->id, &dev_priv->gpu_error.missed_irq_rings); | |
983 | } | |
984 | ||
b29c19b6 CW |
985 | static bool can_wait_boost(struct drm_i915_file_private *file_priv) |
986 | { | |
987 | if (file_priv == NULL) | |
988 | return true; | |
989 | ||
990 | return !atomic_xchg(&file_priv->rps_wait_boost, true); | |
991 | } | |
992 | ||
b361237b CW |
993 | /** |
994 | * __wait_seqno - wait until execution of seqno has finished | |
995 | * @ring: the ring expected to report seqno | |
996 | * @seqno: duh! | |
f69061be | 997 | * @reset_counter: reset sequence associated with the given seqno |
b361237b CW |
998 | * @interruptible: do an interruptible wait (normally yes) |
999 | * @timeout: in - how long to wait (NULL forever); out - how much time remaining | |
1000 | * | |
f69061be DV |
1001 | * Note: It is of utmost importance that the passed in seqno and reset_counter |
1002 | * values have been read by the caller in an smp safe manner. Where read-side | |
1003 | * locks are involved, it is sufficient to read the reset_counter before | |
1004 | * unlocking the lock that protects the seqno. For lockless tricks, the | |
1005 | * reset_counter _must_ be read before, and an appropriate smp_rmb must be | |
1006 | * inserted. | |
1007 | * | |
b361237b CW |
1008 | * Returns 0 if the seqno was found within the alloted time. Else returns the |
1009 | * errno with remaining time filled in timeout argument. | |
1010 | */ | |
1011 | static int __wait_seqno(struct intel_ring_buffer *ring, u32 seqno, | |
f69061be | 1012 | unsigned reset_counter, |
b29c19b6 CW |
1013 | bool interruptible, |
1014 | struct timespec *timeout, | |
1015 | struct drm_i915_file_private *file_priv) | |
b361237b CW |
1016 | { |
1017 | drm_i915_private_t *dev_priv = ring->dev->dev_private; | |
094f9a54 CW |
1018 | struct timespec before, now; |
1019 | DEFINE_WAIT(wait); | |
1020 | long timeout_jiffies; | |
b361237b CW |
1021 | int ret; |
1022 | ||
c67a470b PZ |
1023 | WARN(dev_priv->pc8.irqs_disabled, "IRQs disabled\n"); |
1024 | ||
b361237b CW |
1025 | if (i915_seqno_passed(ring->get_seqno(ring, true), seqno)) |
1026 | return 0; | |
1027 | ||
094f9a54 | 1028 | timeout_jiffies = timeout ? timespec_to_jiffies_timeout(timeout) : 1; |
b361237b | 1029 | |
b29c19b6 CW |
1030 | if (dev_priv->info->gen >= 6 && can_wait_boost(file_priv)) { |
1031 | gen6_rps_boost(dev_priv); | |
1032 | if (file_priv) | |
1033 | mod_delayed_work(dev_priv->wq, | |
1034 | &file_priv->mm.idle_work, | |
1035 | msecs_to_jiffies(100)); | |
1036 | } | |
1037 | ||
094f9a54 CW |
1038 | if (!(dev_priv->gpu_error.test_irq_rings & intel_ring_flag(ring)) && |
1039 | WARN_ON(!ring->irq_get(ring))) | |
b361237b CW |
1040 | return -ENODEV; |
1041 | ||
094f9a54 CW |
1042 | /* Record current time in case interrupted by signal, or wedged */ |
1043 | trace_i915_gem_request_wait_begin(ring, seqno); | |
b361237b | 1044 | getrawmonotonic(&before); |
094f9a54 CW |
1045 | for (;;) { |
1046 | struct timer_list timer; | |
1047 | unsigned long expire; | |
b361237b | 1048 | |
094f9a54 CW |
1049 | prepare_to_wait(&ring->irq_queue, &wait, |
1050 | interruptible ? TASK_INTERRUPTIBLE : TASK_UNINTERRUPTIBLE); | |
b361237b | 1051 | |
f69061be DV |
1052 | /* We need to check whether any gpu reset happened in between |
1053 | * the caller grabbing the seqno and now ... */ | |
094f9a54 CW |
1054 | if (reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter)) { |
1055 | /* ... but upgrade the -EAGAIN to an -EIO if the gpu | |
1056 | * is truely gone. */ | |
1057 | ret = i915_gem_check_wedge(&dev_priv->gpu_error, interruptible); | |
1058 | if (ret == 0) | |
1059 | ret = -EAGAIN; | |
1060 | break; | |
1061 | } | |
f69061be | 1062 | |
094f9a54 CW |
1063 | if (i915_seqno_passed(ring->get_seqno(ring, false), seqno)) { |
1064 | ret = 0; | |
1065 | break; | |
1066 | } | |
b361237b | 1067 | |
094f9a54 CW |
1068 | if (interruptible && signal_pending(current)) { |
1069 | ret = -ERESTARTSYS; | |
1070 | break; | |
1071 | } | |
1072 | ||
1073 | if (timeout_jiffies <= 0) { | |
1074 | ret = -ETIME; | |
1075 | break; | |
1076 | } | |
1077 | ||
1078 | timer.function = NULL; | |
1079 | if (timeout || missed_irq(dev_priv, ring)) { | |
1080 | setup_timer_on_stack(&timer, fake_irq, (unsigned long)current); | |
1081 | expire = jiffies + (missed_irq(dev_priv, ring) ? 1: timeout_jiffies); | |
1082 | mod_timer(&timer, expire); | |
1083 | } | |
1084 | ||
5035c275 | 1085 | io_schedule(); |
094f9a54 CW |
1086 | |
1087 | if (timeout) | |
1088 | timeout_jiffies = expire - jiffies; | |
1089 | ||
1090 | if (timer.function) { | |
1091 | del_singleshot_timer_sync(&timer); | |
1092 | destroy_timer_on_stack(&timer); | |
1093 | } | |
1094 | } | |
b361237b | 1095 | getrawmonotonic(&now); |
094f9a54 | 1096 | trace_i915_gem_request_wait_end(ring, seqno); |
b361237b CW |
1097 | |
1098 | ring->irq_put(ring); | |
094f9a54 CW |
1099 | |
1100 | finish_wait(&ring->irq_queue, &wait); | |
b361237b CW |
1101 | |
1102 | if (timeout) { | |
1103 | struct timespec sleep_time = timespec_sub(now, before); | |
1104 | *timeout = timespec_sub(*timeout, sleep_time); | |
4f42f4ef CW |
1105 | if (!timespec_valid(timeout)) /* i.e. negative time remains */ |
1106 | set_normalized_timespec(timeout, 0, 0); | |
b361237b CW |
1107 | } |
1108 | ||
094f9a54 | 1109 | return ret; |
b361237b CW |
1110 | } |
1111 | ||
1112 | /** | |
1113 | * Waits for a sequence number to be signaled, and cleans up the | |
1114 | * request and object lists appropriately for that event. | |
1115 | */ | |
1116 | int | |
1117 | i915_wait_seqno(struct intel_ring_buffer *ring, uint32_t seqno) | |
1118 | { | |
1119 | struct drm_device *dev = ring->dev; | |
1120 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1121 | bool interruptible = dev_priv->mm.interruptible; | |
1122 | int ret; | |
1123 | ||
1124 | BUG_ON(!mutex_is_locked(&dev->struct_mutex)); | |
1125 | BUG_ON(seqno == 0); | |
1126 | ||
33196ded | 1127 | ret = i915_gem_check_wedge(&dev_priv->gpu_error, interruptible); |
b361237b CW |
1128 | if (ret) |
1129 | return ret; | |
1130 | ||
1131 | ret = i915_gem_check_olr(ring, seqno); | |
1132 | if (ret) | |
1133 | return ret; | |
1134 | ||
f69061be DV |
1135 | return __wait_seqno(ring, seqno, |
1136 | atomic_read(&dev_priv->gpu_error.reset_counter), | |
b29c19b6 | 1137 | interruptible, NULL, NULL); |
b361237b CW |
1138 | } |
1139 | ||
d26e3af8 CW |
1140 | static int |
1141 | i915_gem_object_wait_rendering__tail(struct drm_i915_gem_object *obj, | |
1142 | struct intel_ring_buffer *ring) | |
1143 | { | |
1144 | i915_gem_retire_requests_ring(ring); | |
1145 | ||
1146 | /* Manually manage the write flush as we may have not yet | |
1147 | * retired the buffer. | |
1148 | * | |
1149 | * Note that the last_write_seqno is always the earlier of | |
1150 | * the two (read/write) seqno, so if we haved successfully waited, | |
1151 | * we know we have passed the last write. | |
1152 | */ | |
1153 | obj->last_write_seqno = 0; | |
1154 | obj->base.write_domain &= ~I915_GEM_GPU_DOMAINS; | |
1155 | ||
1156 | return 0; | |
1157 | } | |
1158 | ||
b361237b CW |
1159 | /** |
1160 | * Ensures that all rendering to the object has completed and the object is | |
1161 | * safe to unbind from the GTT or access from the CPU. | |
1162 | */ | |
1163 | static __must_check int | |
1164 | i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj, | |
1165 | bool readonly) | |
1166 | { | |
1167 | struct intel_ring_buffer *ring = obj->ring; | |
1168 | u32 seqno; | |
1169 | int ret; | |
1170 | ||
1171 | seqno = readonly ? obj->last_write_seqno : obj->last_read_seqno; | |
1172 | if (seqno == 0) | |
1173 | return 0; | |
1174 | ||
1175 | ret = i915_wait_seqno(ring, seqno); | |
1176 | if (ret) | |
1177 | return ret; | |
1178 | ||
d26e3af8 | 1179 | return i915_gem_object_wait_rendering__tail(obj, ring); |
b361237b CW |
1180 | } |
1181 | ||
3236f57a CW |
1182 | /* A nonblocking variant of the above wait. This is a highly dangerous routine |
1183 | * as the object state may change during this call. | |
1184 | */ | |
1185 | static __must_check int | |
1186 | i915_gem_object_wait_rendering__nonblocking(struct drm_i915_gem_object *obj, | |
b29c19b6 | 1187 | struct drm_file *file, |
3236f57a CW |
1188 | bool readonly) |
1189 | { | |
1190 | struct drm_device *dev = obj->base.dev; | |
1191 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1192 | struct intel_ring_buffer *ring = obj->ring; | |
f69061be | 1193 | unsigned reset_counter; |
3236f57a CW |
1194 | u32 seqno; |
1195 | int ret; | |
1196 | ||
1197 | BUG_ON(!mutex_is_locked(&dev->struct_mutex)); | |
1198 | BUG_ON(!dev_priv->mm.interruptible); | |
1199 | ||
1200 | seqno = readonly ? obj->last_write_seqno : obj->last_read_seqno; | |
1201 | if (seqno == 0) | |
1202 | return 0; | |
1203 | ||
33196ded | 1204 | ret = i915_gem_check_wedge(&dev_priv->gpu_error, true); |
3236f57a CW |
1205 | if (ret) |
1206 | return ret; | |
1207 | ||
1208 | ret = i915_gem_check_olr(ring, seqno); | |
1209 | if (ret) | |
1210 | return ret; | |
1211 | ||
f69061be | 1212 | reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter); |
3236f57a | 1213 | mutex_unlock(&dev->struct_mutex); |
b29c19b6 | 1214 | ret = __wait_seqno(ring, seqno, reset_counter, true, NULL, file->driver_priv); |
3236f57a | 1215 | mutex_lock(&dev->struct_mutex); |
d26e3af8 CW |
1216 | if (ret) |
1217 | return ret; | |
3236f57a | 1218 | |
d26e3af8 | 1219 | return i915_gem_object_wait_rendering__tail(obj, ring); |
3236f57a CW |
1220 | } |
1221 | ||
673a394b | 1222 | /** |
2ef7eeaa EA |
1223 | * Called when user space prepares to use an object with the CPU, either |
1224 | * through the mmap ioctl's mapping or a GTT mapping. | |
673a394b EA |
1225 | */ |
1226 | int | |
1227 | i915_gem_set_domain_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 1228 | struct drm_file *file) |
673a394b EA |
1229 | { |
1230 | struct drm_i915_gem_set_domain *args = data; | |
05394f39 | 1231 | struct drm_i915_gem_object *obj; |
2ef7eeaa EA |
1232 | uint32_t read_domains = args->read_domains; |
1233 | uint32_t write_domain = args->write_domain; | |
673a394b EA |
1234 | int ret; |
1235 | ||
2ef7eeaa | 1236 | /* Only handle setting domains to types used by the CPU. */ |
21d509e3 | 1237 | if (write_domain & I915_GEM_GPU_DOMAINS) |
2ef7eeaa EA |
1238 | return -EINVAL; |
1239 | ||
21d509e3 | 1240 | if (read_domains & I915_GEM_GPU_DOMAINS) |
2ef7eeaa EA |
1241 | return -EINVAL; |
1242 | ||
1243 | /* Having something in the write domain implies it's in the read | |
1244 | * domain, and only that read domain. Enforce that in the request. | |
1245 | */ | |
1246 | if (write_domain != 0 && read_domains != write_domain) | |
1247 | return -EINVAL; | |
1248 | ||
76c1dec1 | 1249 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 1250 | if (ret) |
76c1dec1 | 1251 | return ret; |
1d7cfea1 | 1252 | |
05394f39 | 1253 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 1254 | if (&obj->base == NULL) { |
1d7cfea1 CW |
1255 | ret = -ENOENT; |
1256 | goto unlock; | |
76c1dec1 | 1257 | } |
673a394b | 1258 | |
3236f57a CW |
1259 | /* Try to flush the object off the GPU without holding the lock. |
1260 | * We will repeat the flush holding the lock in the normal manner | |
1261 | * to catch cases where we are gazumped. | |
1262 | */ | |
b29c19b6 | 1263 | ret = i915_gem_object_wait_rendering__nonblocking(obj, file, !write_domain); |
3236f57a CW |
1264 | if (ret) |
1265 | goto unref; | |
1266 | ||
2ef7eeaa EA |
1267 | if (read_domains & I915_GEM_DOMAIN_GTT) { |
1268 | ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0); | |
02354392 EA |
1269 | |
1270 | /* Silently promote "you're not bound, there was nothing to do" | |
1271 | * to success, since the client was just asking us to | |
1272 | * make sure everything was done. | |
1273 | */ | |
1274 | if (ret == -EINVAL) | |
1275 | ret = 0; | |
2ef7eeaa | 1276 | } else { |
e47c68e9 | 1277 | ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0); |
2ef7eeaa EA |
1278 | } |
1279 | ||
3236f57a | 1280 | unref: |
05394f39 | 1281 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 1282 | unlock: |
673a394b EA |
1283 | mutex_unlock(&dev->struct_mutex); |
1284 | return ret; | |
1285 | } | |
1286 | ||
1287 | /** | |
1288 | * Called when user space has done writes to this buffer | |
1289 | */ | |
1290 | int | |
1291 | i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 1292 | struct drm_file *file) |
673a394b EA |
1293 | { |
1294 | struct drm_i915_gem_sw_finish *args = data; | |
05394f39 | 1295 | struct drm_i915_gem_object *obj; |
673a394b EA |
1296 | int ret = 0; |
1297 | ||
76c1dec1 | 1298 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 1299 | if (ret) |
76c1dec1 | 1300 | return ret; |
1d7cfea1 | 1301 | |
05394f39 | 1302 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 1303 | if (&obj->base == NULL) { |
1d7cfea1 CW |
1304 | ret = -ENOENT; |
1305 | goto unlock; | |
673a394b EA |
1306 | } |
1307 | ||
673a394b | 1308 | /* Pinned buffers may be scanout, so flush the cache */ |
2c22569b CW |
1309 | if (obj->pin_display) |
1310 | i915_gem_object_flush_cpu_write_domain(obj, true); | |
e47c68e9 | 1311 | |
05394f39 | 1312 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 1313 | unlock: |
673a394b EA |
1314 | mutex_unlock(&dev->struct_mutex); |
1315 | return ret; | |
1316 | } | |
1317 | ||
1318 | /** | |
1319 | * Maps the contents of an object, returning the address it is mapped | |
1320 | * into. | |
1321 | * | |
1322 | * While the mapping holds a reference on the contents of the object, it doesn't | |
1323 | * imply a ref on the object itself. | |
1324 | */ | |
1325 | int | |
1326 | i915_gem_mmap_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 1327 | struct drm_file *file) |
673a394b EA |
1328 | { |
1329 | struct drm_i915_gem_mmap *args = data; | |
1330 | struct drm_gem_object *obj; | |
673a394b EA |
1331 | unsigned long addr; |
1332 | ||
05394f39 | 1333 | obj = drm_gem_object_lookup(dev, file, args->handle); |
673a394b | 1334 | if (obj == NULL) |
bf79cb91 | 1335 | return -ENOENT; |
673a394b | 1336 | |
1286ff73 DV |
1337 | /* prime objects have no backing filp to GEM mmap |
1338 | * pages from. | |
1339 | */ | |
1340 | if (!obj->filp) { | |
1341 | drm_gem_object_unreference_unlocked(obj); | |
1342 | return -EINVAL; | |
1343 | } | |
1344 | ||
6be5ceb0 | 1345 | addr = vm_mmap(obj->filp, 0, args->size, |
673a394b EA |
1346 | PROT_READ | PROT_WRITE, MAP_SHARED, |
1347 | args->offset); | |
bc9025bd | 1348 | drm_gem_object_unreference_unlocked(obj); |
673a394b EA |
1349 | if (IS_ERR((void *)addr)) |
1350 | return addr; | |
1351 | ||
1352 | args->addr_ptr = (uint64_t) addr; | |
1353 | ||
1354 | return 0; | |
1355 | } | |
1356 | ||
de151cf6 JB |
1357 | /** |
1358 | * i915_gem_fault - fault a page into the GTT | |
1359 | * vma: VMA in question | |
1360 | * vmf: fault info | |
1361 | * | |
1362 | * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped | |
1363 | * from userspace. The fault handler takes care of binding the object to | |
1364 | * the GTT (if needed), allocating and programming a fence register (again, | |
1365 | * only if needed based on whether the old reg is still valid or the object | |
1366 | * is tiled) and inserting a new PTE into the faulting process. | |
1367 | * | |
1368 | * Note that the faulting process may involve evicting existing objects | |
1369 | * from the GTT and/or fence registers to make room. So performance may | |
1370 | * suffer if the GTT working set is large or there are few fence registers | |
1371 | * left. | |
1372 | */ | |
1373 | int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf) | |
1374 | { | |
05394f39 CW |
1375 | struct drm_i915_gem_object *obj = to_intel_bo(vma->vm_private_data); |
1376 | struct drm_device *dev = obj->base.dev; | |
7d1c4804 | 1377 | drm_i915_private_t *dev_priv = dev->dev_private; |
de151cf6 JB |
1378 | pgoff_t page_offset; |
1379 | unsigned long pfn; | |
1380 | int ret = 0; | |
0f973f27 | 1381 | bool write = !!(vmf->flags & FAULT_FLAG_WRITE); |
de151cf6 JB |
1382 | |
1383 | /* We don't use vmf->pgoff since that has the fake offset */ | |
1384 | page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >> | |
1385 | PAGE_SHIFT; | |
1386 | ||
d9bc7e9f CW |
1387 | ret = i915_mutex_lock_interruptible(dev); |
1388 | if (ret) | |
1389 | goto out; | |
a00b10c3 | 1390 | |
db53a302 CW |
1391 | trace_i915_gem_object_fault(obj, page_offset, true, write); |
1392 | ||
eb119bd6 CW |
1393 | /* Access to snoopable pages through the GTT is incoherent. */ |
1394 | if (obj->cache_level != I915_CACHE_NONE && !HAS_LLC(dev)) { | |
1395 | ret = -EINVAL; | |
1396 | goto unlock; | |
1397 | } | |
1398 | ||
d9bc7e9f | 1399 | /* Now bind it into the GTT if needed */ |
c37e2204 | 1400 | ret = i915_gem_obj_ggtt_pin(obj, 0, true, false); |
c9839303 CW |
1401 | if (ret) |
1402 | goto unlock; | |
4a684a41 | 1403 | |
c9839303 CW |
1404 | ret = i915_gem_object_set_to_gtt_domain(obj, write); |
1405 | if (ret) | |
1406 | goto unpin; | |
74898d7e | 1407 | |
06d98131 | 1408 | ret = i915_gem_object_get_fence(obj); |
d9e86c0e | 1409 | if (ret) |
c9839303 | 1410 | goto unpin; |
7d1c4804 | 1411 | |
6299f992 CW |
1412 | obj->fault_mappable = true; |
1413 | ||
f343c5f6 BW |
1414 | pfn = dev_priv->gtt.mappable_base + i915_gem_obj_ggtt_offset(obj); |
1415 | pfn >>= PAGE_SHIFT; | |
1416 | pfn += page_offset; | |
de151cf6 JB |
1417 | |
1418 | /* Finally, remap it using the new GTT offset */ | |
1419 | ret = vm_insert_pfn(vma, (unsigned long)vmf->virtual_address, pfn); | |
c9839303 CW |
1420 | unpin: |
1421 | i915_gem_object_unpin(obj); | |
c715089f | 1422 | unlock: |
de151cf6 | 1423 | mutex_unlock(&dev->struct_mutex); |
d9bc7e9f | 1424 | out: |
de151cf6 | 1425 | switch (ret) { |
d9bc7e9f | 1426 | case -EIO: |
a9340cca DV |
1427 | /* If this -EIO is due to a gpu hang, give the reset code a |
1428 | * chance to clean up the mess. Otherwise return the proper | |
1429 | * SIGBUS. */ | |
1f83fee0 | 1430 | if (i915_terminally_wedged(&dev_priv->gpu_error)) |
a9340cca | 1431 | return VM_FAULT_SIGBUS; |
045e769a | 1432 | case -EAGAIN: |
571c608d DV |
1433 | /* |
1434 | * EAGAIN means the gpu is hung and we'll wait for the error | |
1435 | * handler to reset everything when re-faulting in | |
1436 | * i915_mutex_lock_interruptible. | |
d9bc7e9f | 1437 | */ |
c715089f CW |
1438 | case 0: |
1439 | case -ERESTARTSYS: | |
bed636ab | 1440 | case -EINTR: |
e79e0fe3 DR |
1441 | case -EBUSY: |
1442 | /* | |
1443 | * EBUSY is ok: this just means that another thread | |
1444 | * already did the job. | |
1445 | */ | |
c715089f | 1446 | return VM_FAULT_NOPAGE; |
de151cf6 | 1447 | case -ENOMEM: |
de151cf6 | 1448 | return VM_FAULT_OOM; |
a7c2e1aa DV |
1449 | case -ENOSPC: |
1450 | return VM_FAULT_SIGBUS; | |
de151cf6 | 1451 | default: |
a7c2e1aa | 1452 | WARN_ONCE(ret, "unhandled error in i915_gem_fault: %i\n", ret); |
c715089f | 1453 | return VM_FAULT_SIGBUS; |
de151cf6 JB |
1454 | } |
1455 | } | |
1456 | ||
901782b2 CW |
1457 | /** |
1458 | * i915_gem_release_mmap - remove physical page mappings | |
1459 | * @obj: obj in question | |
1460 | * | |
af901ca1 | 1461 | * Preserve the reservation of the mmapping with the DRM core code, but |
901782b2 CW |
1462 | * relinquish ownership of the pages back to the system. |
1463 | * | |
1464 | * It is vital that we remove the page mapping if we have mapped a tiled | |
1465 | * object through the GTT and then lose the fence register due to | |
1466 | * resource pressure. Similarly if the object has been moved out of the | |
1467 | * aperture, than pages mapped into userspace must be revoked. Removing the | |
1468 | * mapping will then trigger a page fault on the next user access, allowing | |
1469 | * fixup by i915_gem_fault(). | |
1470 | */ | |
d05ca301 | 1471 | void |
05394f39 | 1472 | i915_gem_release_mmap(struct drm_i915_gem_object *obj) |
901782b2 | 1473 | { |
6299f992 CW |
1474 | if (!obj->fault_mappable) |
1475 | return; | |
901782b2 | 1476 | |
51335df9 | 1477 | drm_vma_node_unmap(&obj->base.vma_node, obj->base.dev->dev_mapping); |
6299f992 | 1478 | obj->fault_mappable = false; |
901782b2 CW |
1479 | } |
1480 | ||
0fa87796 | 1481 | uint32_t |
e28f8711 | 1482 | i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode) |
92b88aeb | 1483 | { |
e28f8711 | 1484 | uint32_t gtt_size; |
92b88aeb CW |
1485 | |
1486 | if (INTEL_INFO(dev)->gen >= 4 || | |
e28f8711 CW |
1487 | tiling_mode == I915_TILING_NONE) |
1488 | return size; | |
92b88aeb CW |
1489 | |
1490 | /* Previous chips need a power-of-two fence region when tiling */ | |
1491 | if (INTEL_INFO(dev)->gen == 3) | |
e28f8711 | 1492 | gtt_size = 1024*1024; |
92b88aeb | 1493 | else |
e28f8711 | 1494 | gtt_size = 512*1024; |
92b88aeb | 1495 | |
e28f8711 CW |
1496 | while (gtt_size < size) |
1497 | gtt_size <<= 1; | |
92b88aeb | 1498 | |
e28f8711 | 1499 | return gtt_size; |
92b88aeb CW |
1500 | } |
1501 | ||
de151cf6 JB |
1502 | /** |
1503 | * i915_gem_get_gtt_alignment - return required GTT alignment for an object | |
1504 | * @obj: object to check | |
1505 | * | |
1506 | * Return the required GTT alignment for an object, taking into account | |
5e783301 | 1507 | * potential fence register mapping. |
de151cf6 | 1508 | */ |
d865110c ID |
1509 | uint32_t |
1510 | i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size, | |
1511 | int tiling_mode, bool fenced) | |
de151cf6 | 1512 | { |
de151cf6 JB |
1513 | /* |
1514 | * Minimum alignment is 4k (GTT page size), but might be greater | |
1515 | * if a fence register is needed for the object. | |
1516 | */ | |
d865110c | 1517 | if (INTEL_INFO(dev)->gen >= 4 || (!fenced && IS_G33(dev)) || |
e28f8711 | 1518 | tiling_mode == I915_TILING_NONE) |
de151cf6 JB |
1519 | return 4096; |
1520 | ||
a00b10c3 CW |
1521 | /* |
1522 | * Previous chips need to be aligned to the size of the smallest | |
1523 | * fence register that can contain the object. | |
1524 | */ | |
e28f8711 | 1525 | return i915_gem_get_gtt_size(dev, size, tiling_mode); |
a00b10c3 CW |
1526 | } |
1527 | ||
d8cb5086 CW |
1528 | static int i915_gem_object_create_mmap_offset(struct drm_i915_gem_object *obj) |
1529 | { | |
1530 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; | |
1531 | int ret; | |
1532 | ||
0de23977 | 1533 | if (drm_vma_node_has_offset(&obj->base.vma_node)) |
d8cb5086 CW |
1534 | return 0; |
1535 | ||
da494d7c DV |
1536 | dev_priv->mm.shrinker_no_lock_stealing = true; |
1537 | ||
d8cb5086 CW |
1538 | ret = drm_gem_create_mmap_offset(&obj->base); |
1539 | if (ret != -ENOSPC) | |
da494d7c | 1540 | goto out; |
d8cb5086 CW |
1541 | |
1542 | /* Badly fragmented mmap space? The only way we can recover | |
1543 | * space is by destroying unwanted objects. We can't randomly release | |
1544 | * mmap_offsets as userspace expects them to be persistent for the | |
1545 | * lifetime of the objects. The closest we can is to release the | |
1546 | * offsets on purgeable objects by truncating it and marking it purged, | |
1547 | * which prevents userspace from ever using that object again. | |
1548 | */ | |
1549 | i915_gem_purge(dev_priv, obj->base.size >> PAGE_SHIFT); | |
1550 | ret = drm_gem_create_mmap_offset(&obj->base); | |
1551 | if (ret != -ENOSPC) | |
da494d7c | 1552 | goto out; |
d8cb5086 CW |
1553 | |
1554 | i915_gem_shrink_all(dev_priv); | |
da494d7c DV |
1555 | ret = drm_gem_create_mmap_offset(&obj->base); |
1556 | out: | |
1557 | dev_priv->mm.shrinker_no_lock_stealing = false; | |
1558 | ||
1559 | return ret; | |
d8cb5086 CW |
1560 | } |
1561 | ||
1562 | static void i915_gem_object_free_mmap_offset(struct drm_i915_gem_object *obj) | |
1563 | { | |
d8cb5086 CW |
1564 | drm_gem_free_mmap_offset(&obj->base); |
1565 | } | |
1566 | ||
de151cf6 | 1567 | int |
ff72145b DA |
1568 | i915_gem_mmap_gtt(struct drm_file *file, |
1569 | struct drm_device *dev, | |
1570 | uint32_t handle, | |
1571 | uint64_t *offset) | |
de151cf6 | 1572 | { |
da761a6e | 1573 | struct drm_i915_private *dev_priv = dev->dev_private; |
05394f39 | 1574 | struct drm_i915_gem_object *obj; |
de151cf6 JB |
1575 | int ret; |
1576 | ||
76c1dec1 | 1577 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 1578 | if (ret) |
76c1dec1 | 1579 | return ret; |
de151cf6 | 1580 | |
ff72145b | 1581 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle)); |
c8725226 | 1582 | if (&obj->base == NULL) { |
1d7cfea1 CW |
1583 | ret = -ENOENT; |
1584 | goto unlock; | |
1585 | } | |
de151cf6 | 1586 | |
5d4545ae | 1587 | if (obj->base.size > dev_priv->gtt.mappable_end) { |
da761a6e | 1588 | ret = -E2BIG; |
ff56b0bc | 1589 | goto out; |
da761a6e CW |
1590 | } |
1591 | ||
05394f39 | 1592 | if (obj->madv != I915_MADV_WILLNEED) { |
ab18282d | 1593 | DRM_ERROR("Attempting to mmap a purgeable buffer\n"); |
1d7cfea1 CW |
1594 | ret = -EINVAL; |
1595 | goto out; | |
ab18282d CW |
1596 | } |
1597 | ||
d8cb5086 CW |
1598 | ret = i915_gem_object_create_mmap_offset(obj); |
1599 | if (ret) | |
1600 | goto out; | |
de151cf6 | 1601 | |
0de23977 | 1602 | *offset = drm_vma_node_offset_addr(&obj->base.vma_node); |
de151cf6 | 1603 | |
1d7cfea1 | 1604 | out: |
05394f39 | 1605 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 1606 | unlock: |
de151cf6 | 1607 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 1608 | return ret; |
de151cf6 JB |
1609 | } |
1610 | ||
ff72145b DA |
1611 | /** |
1612 | * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing | |
1613 | * @dev: DRM device | |
1614 | * @data: GTT mapping ioctl data | |
1615 | * @file: GEM object info | |
1616 | * | |
1617 | * Simply returns the fake offset to userspace so it can mmap it. | |
1618 | * The mmap call will end up in drm_gem_mmap(), which will set things | |
1619 | * up so we can get faults in the handler above. | |
1620 | * | |
1621 | * The fault handler will take care of binding the object into the GTT | |
1622 | * (since it may have been evicted to make room for something), allocating | |
1623 | * a fence register, and mapping the appropriate aperture address into | |
1624 | * userspace. | |
1625 | */ | |
1626 | int | |
1627 | i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data, | |
1628 | struct drm_file *file) | |
1629 | { | |
1630 | struct drm_i915_gem_mmap_gtt *args = data; | |
1631 | ||
ff72145b DA |
1632 | return i915_gem_mmap_gtt(file, dev, args->handle, &args->offset); |
1633 | } | |
1634 | ||
225067ee DV |
1635 | /* Immediately discard the backing storage */ |
1636 | static void | |
1637 | i915_gem_object_truncate(struct drm_i915_gem_object *obj) | |
e5281ccd | 1638 | { |
e5281ccd | 1639 | struct inode *inode; |
e5281ccd | 1640 | |
4d6294bf | 1641 | i915_gem_object_free_mmap_offset(obj); |
1286ff73 | 1642 | |
4d6294bf CW |
1643 | if (obj->base.filp == NULL) |
1644 | return; | |
e5281ccd | 1645 | |
225067ee DV |
1646 | /* Our goal here is to return as much of the memory as |
1647 | * is possible back to the system as we are called from OOM. | |
1648 | * To do this we must instruct the shmfs to drop all of its | |
1649 | * backing pages, *now*. | |
1650 | */ | |
496ad9aa | 1651 | inode = file_inode(obj->base.filp); |
225067ee | 1652 | shmem_truncate_range(inode, 0, (loff_t)-1); |
e5281ccd | 1653 | |
225067ee DV |
1654 | obj->madv = __I915_MADV_PURGED; |
1655 | } | |
e5281ccd | 1656 | |
225067ee DV |
1657 | static inline int |
1658 | i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj) | |
1659 | { | |
1660 | return obj->madv == I915_MADV_DONTNEED; | |
e5281ccd CW |
1661 | } |
1662 | ||
5cdf5881 | 1663 | static void |
05394f39 | 1664 | i915_gem_object_put_pages_gtt(struct drm_i915_gem_object *obj) |
673a394b | 1665 | { |
90797e6d ID |
1666 | struct sg_page_iter sg_iter; |
1667 | int ret; | |
1286ff73 | 1668 | |
05394f39 | 1669 | BUG_ON(obj->madv == __I915_MADV_PURGED); |
673a394b | 1670 | |
6c085a72 CW |
1671 | ret = i915_gem_object_set_to_cpu_domain(obj, true); |
1672 | if (ret) { | |
1673 | /* In the event of a disaster, abandon all caches and | |
1674 | * hope for the best. | |
1675 | */ | |
1676 | WARN_ON(ret != -EIO); | |
2c22569b | 1677 | i915_gem_clflush_object(obj, true); |
6c085a72 CW |
1678 | obj->base.read_domains = obj->base.write_domain = I915_GEM_DOMAIN_CPU; |
1679 | } | |
1680 | ||
6dacfd2f | 1681 | if (i915_gem_object_needs_bit17_swizzle(obj)) |
280b713b EA |
1682 | i915_gem_object_save_bit_17_swizzle(obj); |
1683 | ||
05394f39 CW |
1684 | if (obj->madv == I915_MADV_DONTNEED) |
1685 | obj->dirty = 0; | |
3ef94daa | 1686 | |
90797e6d | 1687 | for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, 0) { |
2db76d7c | 1688 | struct page *page = sg_page_iter_page(&sg_iter); |
9da3da66 | 1689 | |
05394f39 | 1690 | if (obj->dirty) |
9da3da66 | 1691 | set_page_dirty(page); |
3ef94daa | 1692 | |
05394f39 | 1693 | if (obj->madv == I915_MADV_WILLNEED) |
9da3da66 | 1694 | mark_page_accessed(page); |
3ef94daa | 1695 | |
9da3da66 | 1696 | page_cache_release(page); |
3ef94daa | 1697 | } |
05394f39 | 1698 | obj->dirty = 0; |
673a394b | 1699 | |
9da3da66 CW |
1700 | sg_free_table(obj->pages); |
1701 | kfree(obj->pages); | |
37e680a1 | 1702 | } |
6c085a72 | 1703 | |
dd624afd | 1704 | int |
37e680a1 CW |
1705 | i915_gem_object_put_pages(struct drm_i915_gem_object *obj) |
1706 | { | |
1707 | const struct drm_i915_gem_object_ops *ops = obj->ops; | |
1708 | ||
2f745ad3 | 1709 | if (obj->pages == NULL) |
37e680a1 CW |
1710 | return 0; |
1711 | ||
a5570178 CW |
1712 | if (obj->pages_pin_count) |
1713 | return -EBUSY; | |
1714 | ||
9843877d | 1715 | BUG_ON(i915_gem_obj_bound_any(obj)); |
3e123027 | 1716 | |
a2165e31 CW |
1717 | /* ->put_pages might need to allocate memory for the bit17 swizzle |
1718 | * array, hence protect them from being reaped by removing them from gtt | |
1719 | * lists early. */ | |
35c20a60 | 1720 | list_del(&obj->global_list); |
a2165e31 | 1721 | |
37e680a1 | 1722 | ops->put_pages(obj); |
05394f39 | 1723 | obj->pages = NULL; |
37e680a1 | 1724 | |
6c085a72 CW |
1725 | if (i915_gem_object_is_purgeable(obj)) |
1726 | i915_gem_object_truncate(obj); | |
1727 | ||
1728 | return 0; | |
1729 | } | |
1730 | ||
d9973b43 | 1731 | static unsigned long |
93927ca5 DV |
1732 | __i915_gem_shrink(struct drm_i915_private *dev_priv, long target, |
1733 | bool purgeable_only) | |
6c085a72 | 1734 | { |
57094f82 | 1735 | struct list_head still_bound_list; |
6c085a72 | 1736 | struct drm_i915_gem_object *obj, *next; |
d9973b43 | 1737 | unsigned long count = 0; |
6c085a72 CW |
1738 | |
1739 | list_for_each_entry_safe(obj, next, | |
1740 | &dev_priv->mm.unbound_list, | |
35c20a60 | 1741 | global_list) { |
93927ca5 | 1742 | if ((i915_gem_object_is_purgeable(obj) || !purgeable_only) && |
37e680a1 | 1743 | i915_gem_object_put_pages(obj) == 0) { |
6c085a72 CW |
1744 | count += obj->base.size >> PAGE_SHIFT; |
1745 | if (count >= target) | |
1746 | return count; | |
1747 | } | |
1748 | } | |
1749 | ||
57094f82 CW |
1750 | /* |
1751 | * As we may completely rewrite the bound list whilst unbinding | |
1752 | * (due to retiring requests) we have to strictly process only | |
1753 | * one element of the list at the time, and recheck the list | |
1754 | * on every iteration. | |
1755 | */ | |
1756 | INIT_LIST_HEAD(&still_bound_list); | |
1757 | while (count < target && !list_empty(&dev_priv->mm.bound_list)) { | |
07fe0b12 | 1758 | struct i915_vma *vma, *v; |
80dcfdbd | 1759 | |
57094f82 CW |
1760 | obj = list_first_entry(&dev_priv->mm.bound_list, |
1761 | typeof(*obj), global_list); | |
1762 | list_move_tail(&obj->global_list, &still_bound_list); | |
1763 | ||
80dcfdbd BW |
1764 | if (!i915_gem_object_is_purgeable(obj) && purgeable_only) |
1765 | continue; | |
1766 | ||
57094f82 CW |
1767 | /* |
1768 | * Hold a reference whilst we unbind this object, as we may | |
1769 | * end up waiting for and retiring requests. This might | |
1770 | * release the final reference (held by the active list) | |
1771 | * and result in the object being freed from under us. | |
1772 | * in this object being freed. | |
1773 | * | |
1774 | * Note 1: Shrinking the bound list is special since only active | |
1775 | * (and hence bound objects) can contain such limbo objects, so | |
1776 | * we don't need special tricks for shrinking the unbound list. | |
1777 | * The only other place where we have to be careful with active | |
1778 | * objects suddenly disappearing due to retiring requests is the | |
1779 | * eviction code. | |
1780 | * | |
1781 | * Note 2: Even though the bound list doesn't hold a reference | |
1782 | * to the object we can safely grab one here: The final object | |
1783 | * unreferencing and the bound_list are both protected by the | |
1784 | * dev->struct_mutex and so we won't ever be able to observe an | |
1785 | * object on the bound_list with a reference count equals 0. | |
1786 | */ | |
1787 | drm_gem_object_reference(&obj->base); | |
1788 | ||
07fe0b12 BW |
1789 | list_for_each_entry_safe(vma, v, &obj->vma_list, vma_link) |
1790 | if (i915_vma_unbind(vma)) | |
1791 | break; | |
80dcfdbd | 1792 | |
57094f82 | 1793 | if (i915_gem_object_put_pages(obj) == 0) |
6c085a72 | 1794 | count += obj->base.size >> PAGE_SHIFT; |
57094f82 CW |
1795 | |
1796 | drm_gem_object_unreference(&obj->base); | |
6c085a72 | 1797 | } |
57094f82 | 1798 | list_splice(&still_bound_list, &dev_priv->mm.bound_list); |
6c085a72 CW |
1799 | |
1800 | return count; | |
1801 | } | |
1802 | ||
d9973b43 | 1803 | static unsigned long |
93927ca5 DV |
1804 | i915_gem_purge(struct drm_i915_private *dev_priv, long target) |
1805 | { | |
1806 | return __i915_gem_shrink(dev_priv, target, true); | |
1807 | } | |
1808 | ||
d9973b43 | 1809 | static unsigned long |
6c085a72 CW |
1810 | i915_gem_shrink_all(struct drm_i915_private *dev_priv) |
1811 | { | |
1812 | struct drm_i915_gem_object *obj, *next; | |
7dc19d5a | 1813 | long freed = 0; |
6c085a72 CW |
1814 | |
1815 | i915_gem_evict_everything(dev_priv->dev); | |
1816 | ||
35c20a60 | 1817 | list_for_each_entry_safe(obj, next, &dev_priv->mm.unbound_list, |
7dc19d5a | 1818 | global_list) { |
d9973b43 | 1819 | if (i915_gem_object_put_pages(obj) == 0) |
7dc19d5a | 1820 | freed += obj->base.size >> PAGE_SHIFT; |
7dc19d5a DC |
1821 | } |
1822 | return freed; | |
225067ee DV |
1823 | } |
1824 | ||
37e680a1 | 1825 | static int |
6c085a72 | 1826 | i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj) |
e5281ccd | 1827 | { |
6c085a72 | 1828 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
e5281ccd CW |
1829 | int page_count, i; |
1830 | struct address_space *mapping; | |
9da3da66 CW |
1831 | struct sg_table *st; |
1832 | struct scatterlist *sg; | |
90797e6d | 1833 | struct sg_page_iter sg_iter; |
e5281ccd | 1834 | struct page *page; |
90797e6d | 1835 | unsigned long last_pfn = 0; /* suppress gcc warning */ |
6c085a72 | 1836 | gfp_t gfp; |
e5281ccd | 1837 | |
6c085a72 CW |
1838 | /* Assert that the object is not currently in any GPU domain. As it |
1839 | * wasn't in the GTT, there shouldn't be any way it could have been in | |
1840 | * a GPU cache | |
1841 | */ | |
1842 | BUG_ON(obj->base.read_domains & I915_GEM_GPU_DOMAINS); | |
1843 | BUG_ON(obj->base.write_domain & I915_GEM_GPU_DOMAINS); | |
1844 | ||
9da3da66 CW |
1845 | st = kmalloc(sizeof(*st), GFP_KERNEL); |
1846 | if (st == NULL) | |
1847 | return -ENOMEM; | |
1848 | ||
05394f39 | 1849 | page_count = obj->base.size / PAGE_SIZE; |
9da3da66 | 1850 | if (sg_alloc_table(st, page_count, GFP_KERNEL)) { |
9da3da66 | 1851 | kfree(st); |
e5281ccd | 1852 | return -ENOMEM; |
9da3da66 | 1853 | } |
e5281ccd | 1854 | |
9da3da66 CW |
1855 | /* Get the list of pages out of our struct file. They'll be pinned |
1856 | * at this point until we release them. | |
1857 | * | |
1858 | * Fail silently without starting the shrinker | |
1859 | */ | |
496ad9aa | 1860 | mapping = file_inode(obj->base.filp)->i_mapping; |
6c085a72 | 1861 | gfp = mapping_gfp_mask(mapping); |
caf49191 | 1862 | gfp |= __GFP_NORETRY | __GFP_NOWARN | __GFP_NO_KSWAPD; |
6c085a72 | 1863 | gfp &= ~(__GFP_IO | __GFP_WAIT); |
90797e6d ID |
1864 | sg = st->sgl; |
1865 | st->nents = 0; | |
1866 | for (i = 0; i < page_count; i++) { | |
6c085a72 CW |
1867 | page = shmem_read_mapping_page_gfp(mapping, i, gfp); |
1868 | if (IS_ERR(page)) { | |
1869 | i915_gem_purge(dev_priv, page_count); | |
1870 | page = shmem_read_mapping_page_gfp(mapping, i, gfp); | |
1871 | } | |
1872 | if (IS_ERR(page)) { | |
1873 | /* We've tried hard to allocate the memory by reaping | |
1874 | * our own buffer, now let the real VM do its job and | |
1875 | * go down in flames if truly OOM. | |
1876 | */ | |
caf49191 | 1877 | gfp &= ~(__GFP_NORETRY | __GFP_NOWARN | __GFP_NO_KSWAPD); |
6c085a72 CW |
1878 | gfp |= __GFP_IO | __GFP_WAIT; |
1879 | ||
1880 | i915_gem_shrink_all(dev_priv); | |
1881 | page = shmem_read_mapping_page_gfp(mapping, i, gfp); | |
1882 | if (IS_ERR(page)) | |
1883 | goto err_pages; | |
1884 | ||
caf49191 | 1885 | gfp |= __GFP_NORETRY | __GFP_NOWARN | __GFP_NO_KSWAPD; |
6c085a72 CW |
1886 | gfp &= ~(__GFP_IO | __GFP_WAIT); |
1887 | } | |
426729dc KRW |
1888 | #ifdef CONFIG_SWIOTLB |
1889 | if (swiotlb_nr_tbl()) { | |
1890 | st->nents++; | |
1891 | sg_set_page(sg, page, PAGE_SIZE, 0); | |
1892 | sg = sg_next(sg); | |
1893 | continue; | |
1894 | } | |
1895 | #endif | |
90797e6d ID |
1896 | if (!i || page_to_pfn(page) != last_pfn + 1) { |
1897 | if (i) | |
1898 | sg = sg_next(sg); | |
1899 | st->nents++; | |
1900 | sg_set_page(sg, page, PAGE_SIZE, 0); | |
1901 | } else { | |
1902 | sg->length += PAGE_SIZE; | |
1903 | } | |
1904 | last_pfn = page_to_pfn(page); | |
3bbbe706 DV |
1905 | |
1906 | /* Check that the i965g/gm workaround works. */ | |
1907 | WARN_ON((gfp & __GFP_DMA32) && (last_pfn >= 0x00100000UL)); | |
e5281ccd | 1908 | } |
426729dc KRW |
1909 | #ifdef CONFIG_SWIOTLB |
1910 | if (!swiotlb_nr_tbl()) | |
1911 | #endif | |
1912 | sg_mark_end(sg); | |
74ce6b6c CW |
1913 | obj->pages = st; |
1914 | ||
6dacfd2f | 1915 | if (i915_gem_object_needs_bit17_swizzle(obj)) |
e5281ccd CW |
1916 | i915_gem_object_do_bit_17_swizzle(obj); |
1917 | ||
1918 | return 0; | |
1919 | ||
1920 | err_pages: | |
90797e6d ID |
1921 | sg_mark_end(sg); |
1922 | for_each_sg_page(st->sgl, &sg_iter, st->nents, 0) | |
2db76d7c | 1923 | page_cache_release(sg_page_iter_page(&sg_iter)); |
9da3da66 CW |
1924 | sg_free_table(st); |
1925 | kfree(st); | |
e5281ccd | 1926 | return PTR_ERR(page); |
673a394b EA |
1927 | } |
1928 | ||
37e680a1 CW |
1929 | /* Ensure that the associated pages are gathered from the backing storage |
1930 | * and pinned into our object. i915_gem_object_get_pages() may be called | |
1931 | * multiple times before they are released by a single call to | |
1932 | * i915_gem_object_put_pages() - once the pages are no longer referenced | |
1933 | * either as a result of memory pressure (reaping pages under the shrinker) | |
1934 | * or as the object is itself released. | |
1935 | */ | |
1936 | int | |
1937 | i915_gem_object_get_pages(struct drm_i915_gem_object *obj) | |
1938 | { | |
1939 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; | |
1940 | const struct drm_i915_gem_object_ops *ops = obj->ops; | |
1941 | int ret; | |
1942 | ||
2f745ad3 | 1943 | if (obj->pages) |
37e680a1 CW |
1944 | return 0; |
1945 | ||
43e28f09 CW |
1946 | if (obj->madv != I915_MADV_WILLNEED) { |
1947 | DRM_ERROR("Attempting to obtain a purgeable object\n"); | |
1948 | return -EINVAL; | |
1949 | } | |
1950 | ||
a5570178 CW |
1951 | BUG_ON(obj->pages_pin_count); |
1952 | ||
37e680a1 CW |
1953 | ret = ops->get_pages(obj); |
1954 | if (ret) | |
1955 | return ret; | |
1956 | ||
35c20a60 | 1957 | list_add_tail(&obj->global_list, &dev_priv->mm.unbound_list); |
37e680a1 | 1958 | return 0; |
673a394b EA |
1959 | } |
1960 | ||
e2d05a8b | 1961 | static void |
05394f39 | 1962 | i915_gem_object_move_to_active(struct drm_i915_gem_object *obj, |
9d773091 | 1963 | struct intel_ring_buffer *ring) |
673a394b | 1964 | { |
05394f39 | 1965 | struct drm_device *dev = obj->base.dev; |
69dc4987 | 1966 | struct drm_i915_private *dev_priv = dev->dev_private; |
9d773091 | 1967 | u32 seqno = intel_ring_get_seqno(ring); |
617dbe27 | 1968 | |
852835f3 | 1969 | BUG_ON(ring == NULL); |
02978ff5 CW |
1970 | if (obj->ring != ring && obj->last_write_seqno) { |
1971 | /* Keep the seqno relative to the current ring */ | |
1972 | obj->last_write_seqno = seqno; | |
1973 | } | |
05394f39 | 1974 | obj->ring = ring; |
673a394b EA |
1975 | |
1976 | /* Add a reference if we're newly entering the active list. */ | |
05394f39 CW |
1977 | if (!obj->active) { |
1978 | drm_gem_object_reference(&obj->base); | |
1979 | obj->active = 1; | |
673a394b | 1980 | } |
e35a41de | 1981 | |
05394f39 | 1982 | list_move_tail(&obj->ring_list, &ring->active_list); |
caea7476 | 1983 | |
0201f1ec | 1984 | obj->last_read_seqno = seqno; |
caea7476 | 1985 | |
7dd49065 | 1986 | if (obj->fenced_gpu_access) { |
caea7476 | 1987 | obj->last_fenced_seqno = seqno; |
caea7476 | 1988 | |
7dd49065 CW |
1989 | /* Bump MRU to take account of the delayed flush */ |
1990 | if (obj->fence_reg != I915_FENCE_REG_NONE) { | |
1991 | struct drm_i915_fence_reg *reg; | |
1992 | ||
1993 | reg = &dev_priv->fence_regs[obj->fence_reg]; | |
1994 | list_move_tail(®->lru_list, | |
1995 | &dev_priv->mm.fence_list); | |
1996 | } | |
caea7476 CW |
1997 | } |
1998 | } | |
1999 | ||
e2d05a8b BW |
2000 | void i915_vma_move_to_active(struct i915_vma *vma, |
2001 | struct intel_ring_buffer *ring) | |
2002 | { | |
2003 | list_move_tail(&vma->mm_list, &vma->vm->active_list); | |
2004 | return i915_gem_object_move_to_active(vma->obj, ring); | |
2005 | } | |
2006 | ||
caea7476 | 2007 | static void |
caea7476 | 2008 | i915_gem_object_move_to_inactive(struct drm_i915_gem_object *obj) |
ce44b0ea | 2009 | { |
ca191b13 BW |
2010 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
2011 | struct i915_address_space *ggtt_vm = &dev_priv->gtt.base; | |
2012 | struct i915_vma *vma = i915_gem_obj_to_vma(obj, ggtt_vm); | |
ce44b0ea | 2013 | |
65ce3027 | 2014 | BUG_ON(obj->base.write_domain & ~I915_GEM_GPU_DOMAINS); |
05394f39 | 2015 | BUG_ON(!obj->active); |
caea7476 | 2016 | |
ca191b13 | 2017 | list_move_tail(&vma->mm_list, &ggtt_vm->inactive_list); |
caea7476 | 2018 | |
65ce3027 | 2019 | list_del_init(&obj->ring_list); |
caea7476 CW |
2020 | obj->ring = NULL; |
2021 | ||
65ce3027 CW |
2022 | obj->last_read_seqno = 0; |
2023 | obj->last_write_seqno = 0; | |
2024 | obj->base.write_domain = 0; | |
2025 | ||
2026 | obj->last_fenced_seqno = 0; | |
caea7476 | 2027 | obj->fenced_gpu_access = false; |
caea7476 CW |
2028 | |
2029 | obj->active = 0; | |
2030 | drm_gem_object_unreference(&obj->base); | |
2031 | ||
2032 | WARN_ON(i915_verify_lists(dev)); | |
ce44b0ea | 2033 | } |
673a394b | 2034 | |
9d773091 | 2035 | static int |
fca26bb4 | 2036 | i915_gem_init_seqno(struct drm_device *dev, u32 seqno) |
53d227f2 | 2037 | { |
9d773091 CW |
2038 | struct drm_i915_private *dev_priv = dev->dev_private; |
2039 | struct intel_ring_buffer *ring; | |
2040 | int ret, i, j; | |
53d227f2 | 2041 | |
107f27a5 | 2042 | /* Carefully retire all requests without writing to the rings */ |
9d773091 | 2043 | for_each_ring(ring, dev_priv, i) { |
107f27a5 CW |
2044 | ret = intel_ring_idle(ring); |
2045 | if (ret) | |
2046 | return ret; | |
9d773091 | 2047 | } |
9d773091 | 2048 | i915_gem_retire_requests(dev); |
107f27a5 CW |
2049 | |
2050 | /* Finally reset hw state */ | |
9d773091 | 2051 | for_each_ring(ring, dev_priv, i) { |
fca26bb4 | 2052 | intel_ring_init_seqno(ring, seqno); |
498d2ac1 | 2053 | |
9d773091 CW |
2054 | for (j = 0; j < ARRAY_SIZE(ring->sync_seqno); j++) |
2055 | ring->sync_seqno[j] = 0; | |
2056 | } | |
53d227f2 | 2057 | |
9d773091 | 2058 | return 0; |
53d227f2 DV |
2059 | } |
2060 | ||
fca26bb4 MK |
2061 | int i915_gem_set_seqno(struct drm_device *dev, u32 seqno) |
2062 | { | |
2063 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2064 | int ret; | |
2065 | ||
2066 | if (seqno == 0) | |
2067 | return -EINVAL; | |
2068 | ||
2069 | /* HWS page needs to be set less than what we | |
2070 | * will inject to ring | |
2071 | */ | |
2072 | ret = i915_gem_init_seqno(dev, seqno - 1); | |
2073 | if (ret) | |
2074 | return ret; | |
2075 | ||
2076 | /* Carefully set the last_seqno value so that wrap | |
2077 | * detection still works | |
2078 | */ | |
2079 | dev_priv->next_seqno = seqno; | |
2080 | dev_priv->last_seqno = seqno - 1; | |
2081 | if (dev_priv->last_seqno == 0) | |
2082 | dev_priv->last_seqno--; | |
2083 | ||
2084 | return 0; | |
2085 | } | |
2086 | ||
9d773091 CW |
2087 | int |
2088 | i915_gem_get_seqno(struct drm_device *dev, u32 *seqno) | |
53d227f2 | 2089 | { |
9d773091 CW |
2090 | struct drm_i915_private *dev_priv = dev->dev_private; |
2091 | ||
2092 | /* reserve 0 for non-seqno */ | |
2093 | if (dev_priv->next_seqno == 0) { | |
fca26bb4 | 2094 | int ret = i915_gem_init_seqno(dev, 0); |
9d773091 CW |
2095 | if (ret) |
2096 | return ret; | |
53d227f2 | 2097 | |
9d773091 CW |
2098 | dev_priv->next_seqno = 1; |
2099 | } | |
53d227f2 | 2100 | |
f72b3435 | 2101 | *seqno = dev_priv->last_seqno = dev_priv->next_seqno++; |
9d773091 | 2102 | return 0; |
53d227f2 DV |
2103 | } |
2104 | ||
0025c077 MK |
2105 | int __i915_add_request(struct intel_ring_buffer *ring, |
2106 | struct drm_file *file, | |
7d736f4f | 2107 | struct drm_i915_gem_object *obj, |
0025c077 | 2108 | u32 *out_seqno) |
673a394b | 2109 | { |
db53a302 | 2110 | drm_i915_private_t *dev_priv = ring->dev->dev_private; |
acb868d3 | 2111 | struct drm_i915_gem_request *request; |
7d736f4f | 2112 | u32 request_ring_position, request_start; |
673a394b | 2113 | int was_empty; |
3cce469c CW |
2114 | int ret; |
2115 | ||
7d736f4f | 2116 | request_start = intel_ring_get_tail(ring); |
cc889e0f DV |
2117 | /* |
2118 | * Emit any outstanding flushes - execbuf can fail to emit the flush | |
2119 | * after having emitted the batchbuffer command. Hence we need to fix | |
2120 | * things up similar to emitting the lazy request. The difference here | |
2121 | * is that the flush _must_ happen before the next request, no matter | |
2122 | * what. | |
2123 | */ | |
a7b9761d CW |
2124 | ret = intel_ring_flush_all_caches(ring); |
2125 | if (ret) | |
2126 | return ret; | |
cc889e0f | 2127 | |
3c0e234c CW |
2128 | request = ring->preallocated_lazy_request; |
2129 | if (WARN_ON(request == NULL)) | |
acb868d3 | 2130 | return -ENOMEM; |
cc889e0f | 2131 | |
a71d8d94 CW |
2132 | /* Record the position of the start of the request so that |
2133 | * should we detect the updated seqno part-way through the | |
2134 | * GPU processing the request, we never over-estimate the | |
2135 | * position of the head. | |
2136 | */ | |
2137 | request_ring_position = intel_ring_get_tail(ring); | |
2138 | ||
9d773091 | 2139 | ret = ring->add_request(ring); |
3c0e234c | 2140 | if (ret) |
3bb73aba | 2141 | return ret; |
673a394b | 2142 | |
9d773091 | 2143 | request->seqno = intel_ring_get_seqno(ring); |
852835f3 | 2144 | request->ring = ring; |
7d736f4f | 2145 | request->head = request_start; |
a71d8d94 | 2146 | request->tail = request_ring_position; |
7d736f4f MK |
2147 | |
2148 | /* Whilst this request exists, batch_obj will be on the | |
2149 | * active_list, and so will hold the active reference. Only when this | |
2150 | * request is retired will the the batch_obj be moved onto the | |
2151 | * inactive_list and lose its active reference. Hence we do not need | |
2152 | * to explicitly hold another reference here. | |
2153 | */ | |
9a7e0c2a | 2154 | request->batch_obj = obj; |
0e50e96b | 2155 | |
9a7e0c2a CW |
2156 | /* Hold a reference to the current context so that we can inspect |
2157 | * it later in case a hangcheck error event fires. | |
2158 | */ | |
2159 | request->ctx = ring->last_context; | |
0e50e96b MK |
2160 | if (request->ctx) |
2161 | i915_gem_context_reference(request->ctx); | |
2162 | ||
673a394b | 2163 | request->emitted_jiffies = jiffies; |
852835f3 ZN |
2164 | was_empty = list_empty(&ring->request_list); |
2165 | list_add_tail(&request->list, &ring->request_list); | |
3bb73aba | 2166 | request->file_priv = NULL; |
852835f3 | 2167 | |
db53a302 CW |
2168 | if (file) { |
2169 | struct drm_i915_file_private *file_priv = file->driver_priv; | |
2170 | ||
1c25595f | 2171 | spin_lock(&file_priv->mm.lock); |
f787a5f5 | 2172 | request->file_priv = file_priv; |
b962442e | 2173 | list_add_tail(&request->client_list, |
f787a5f5 | 2174 | &file_priv->mm.request_list); |
1c25595f | 2175 | spin_unlock(&file_priv->mm.lock); |
b962442e | 2176 | } |
673a394b | 2177 | |
9d773091 | 2178 | trace_i915_gem_request_add(ring, request->seqno); |
1823521d | 2179 | ring->outstanding_lazy_seqno = 0; |
3c0e234c | 2180 | ring->preallocated_lazy_request = NULL; |
db53a302 | 2181 | |
db1b76ca | 2182 | if (!dev_priv->ums.mm_suspended) { |
10cd45b6 MK |
2183 | i915_queue_hangcheck(ring->dev); |
2184 | ||
f047e395 | 2185 | if (was_empty) { |
b29c19b6 | 2186 | cancel_delayed_work_sync(&dev_priv->mm.idle_work); |
b3b079db | 2187 | queue_delayed_work(dev_priv->wq, |
bcb45086 CW |
2188 | &dev_priv->mm.retire_work, |
2189 | round_jiffies_up_relative(HZ)); | |
f047e395 CW |
2190 | intel_mark_busy(dev_priv->dev); |
2191 | } | |
f65d9421 | 2192 | } |
cc889e0f | 2193 | |
acb868d3 | 2194 | if (out_seqno) |
9d773091 | 2195 | *out_seqno = request->seqno; |
3cce469c | 2196 | return 0; |
673a394b EA |
2197 | } |
2198 | ||
f787a5f5 CW |
2199 | static inline void |
2200 | i915_gem_request_remove_from_client(struct drm_i915_gem_request *request) | |
673a394b | 2201 | { |
1c25595f | 2202 | struct drm_i915_file_private *file_priv = request->file_priv; |
673a394b | 2203 | |
1c25595f CW |
2204 | if (!file_priv) |
2205 | return; | |
1c5d22f7 | 2206 | |
1c25595f | 2207 | spin_lock(&file_priv->mm.lock); |
b29c19b6 CW |
2208 | list_del(&request->client_list); |
2209 | request->file_priv = NULL; | |
1c25595f | 2210 | spin_unlock(&file_priv->mm.lock); |
673a394b | 2211 | } |
673a394b | 2212 | |
d1ccbb5d BW |
2213 | static bool i915_head_inside_object(u32 acthd, struct drm_i915_gem_object *obj, |
2214 | struct i915_address_space *vm) | |
aa60c664 | 2215 | { |
d1ccbb5d BW |
2216 | if (acthd >= i915_gem_obj_offset(obj, vm) && |
2217 | acthd < i915_gem_obj_offset(obj, vm) + obj->base.size) | |
aa60c664 MK |
2218 | return true; |
2219 | ||
2220 | return false; | |
2221 | } | |
2222 | ||
2223 | static bool i915_head_inside_request(const u32 acthd_unmasked, | |
2224 | const u32 request_start, | |
2225 | const u32 request_end) | |
2226 | { | |
2227 | const u32 acthd = acthd_unmasked & HEAD_ADDR; | |
2228 | ||
2229 | if (request_start < request_end) { | |
2230 | if (acthd >= request_start && acthd < request_end) | |
2231 | return true; | |
2232 | } else if (request_start > request_end) { | |
2233 | if (acthd >= request_start || acthd < request_end) | |
2234 | return true; | |
2235 | } | |
2236 | ||
2237 | return false; | |
2238 | } | |
2239 | ||
d1ccbb5d BW |
2240 | static struct i915_address_space * |
2241 | request_to_vm(struct drm_i915_gem_request *request) | |
2242 | { | |
2243 | struct drm_i915_private *dev_priv = request->ring->dev->dev_private; | |
2244 | struct i915_address_space *vm; | |
2245 | ||
2246 | vm = &dev_priv->gtt.base; | |
2247 | ||
2248 | return vm; | |
2249 | } | |
2250 | ||
aa60c664 MK |
2251 | static bool i915_request_guilty(struct drm_i915_gem_request *request, |
2252 | const u32 acthd, bool *inside) | |
2253 | { | |
2254 | /* There is a possibility that unmasked head address | |
2255 | * pointing inside the ring, matches the batch_obj address range. | |
2256 | * However this is extremely unlikely. | |
2257 | */ | |
aa60c664 | 2258 | if (request->batch_obj) { |
d1ccbb5d BW |
2259 | if (i915_head_inside_object(acthd, request->batch_obj, |
2260 | request_to_vm(request))) { | |
aa60c664 MK |
2261 | *inside = true; |
2262 | return true; | |
2263 | } | |
2264 | } | |
2265 | ||
2266 | if (i915_head_inside_request(acthd, request->head, request->tail)) { | |
2267 | *inside = false; | |
2268 | return true; | |
2269 | } | |
2270 | ||
2271 | return false; | |
2272 | } | |
2273 | ||
be62acb4 MK |
2274 | static bool i915_context_is_banned(const struct i915_ctx_hang_stats *hs) |
2275 | { | |
2276 | const unsigned long elapsed = get_seconds() - hs->guilty_ts; | |
2277 | ||
2278 | if (hs->banned) | |
2279 | return true; | |
2280 | ||
2281 | if (elapsed <= DRM_I915_CTX_BAN_PERIOD) { | |
2282 | DRM_ERROR("context hanging too fast, declaring banned!\n"); | |
2283 | return true; | |
2284 | } | |
2285 | ||
2286 | return false; | |
2287 | } | |
2288 | ||
aa60c664 MK |
2289 | static void i915_set_reset_status(struct intel_ring_buffer *ring, |
2290 | struct drm_i915_gem_request *request, | |
2291 | u32 acthd) | |
2292 | { | |
2293 | struct i915_ctx_hang_stats *hs = NULL; | |
2294 | bool inside, guilty; | |
d1ccbb5d | 2295 | unsigned long offset = 0; |
aa60c664 MK |
2296 | |
2297 | /* Innocent until proven guilty */ | |
2298 | guilty = false; | |
2299 | ||
d1ccbb5d BW |
2300 | if (request->batch_obj) |
2301 | offset = i915_gem_obj_offset(request->batch_obj, | |
2302 | request_to_vm(request)); | |
2303 | ||
f2f4d82f | 2304 | if (ring->hangcheck.action != HANGCHECK_WAIT && |
aa60c664 | 2305 | i915_request_guilty(request, acthd, &inside)) { |
f343c5f6 | 2306 | DRM_ERROR("%s hung %s bo (0x%lx ctx %d) at 0x%x\n", |
aa60c664 MK |
2307 | ring->name, |
2308 | inside ? "inside" : "flushing", | |
d1ccbb5d | 2309 | offset, |
aa60c664 MK |
2310 | request->ctx ? request->ctx->id : 0, |
2311 | acthd); | |
2312 | ||
2313 | guilty = true; | |
2314 | } | |
2315 | ||
2316 | /* If contexts are disabled or this is the default context, use | |
2317 | * file_priv->reset_state | |
2318 | */ | |
2319 | if (request->ctx && request->ctx->id != DEFAULT_CONTEXT_ID) | |
2320 | hs = &request->ctx->hang_stats; | |
2321 | else if (request->file_priv) | |
2322 | hs = &request->file_priv->hang_stats; | |
2323 | ||
2324 | if (hs) { | |
be62acb4 MK |
2325 | if (guilty) { |
2326 | hs->banned = i915_context_is_banned(hs); | |
aa60c664 | 2327 | hs->batch_active++; |
be62acb4 MK |
2328 | hs->guilty_ts = get_seconds(); |
2329 | } else { | |
aa60c664 | 2330 | hs->batch_pending++; |
be62acb4 | 2331 | } |
aa60c664 MK |
2332 | } |
2333 | } | |
2334 | ||
0e50e96b MK |
2335 | static void i915_gem_free_request(struct drm_i915_gem_request *request) |
2336 | { | |
2337 | list_del(&request->list); | |
2338 | i915_gem_request_remove_from_client(request); | |
2339 | ||
2340 | if (request->ctx) | |
2341 | i915_gem_context_unreference(request->ctx); | |
2342 | ||
2343 | kfree(request); | |
2344 | } | |
2345 | ||
dfaae392 CW |
2346 | static void i915_gem_reset_ring_lists(struct drm_i915_private *dev_priv, |
2347 | struct intel_ring_buffer *ring) | |
9375e446 | 2348 | { |
aa60c664 MK |
2349 | u32 completed_seqno; |
2350 | u32 acthd; | |
2351 | ||
2352 | acthd = intel_ring_get_active_head(ring); | |
2353 | completed_seqno = ring->get_seqno(ring, false); | |
2354 | ||
dfaae392 CW |
2355 | while (!list_empty(&ring->request_list)) { |
2356 | struct drm_i915_gem_request *request; | |
673a394b | 2357 | |
dfaae392 CW |
2358 | request = list_first_entry(&ring->request_list, |
2359 | struct drm_i915_gem_request, | |
2360 | list); | |
de151cf6 | 2361 | |
aa60c664 MK |
2362 | if (request->seqno > completed_seqno) |
2363 | i915_set_reset_status(ring, request, acthd); | |
2364 | ||
0e50e96b | 2365 | i915_gem_free_request(request); |
dfaae392 | 2366 | } |
673a394b | 2367 | |
dfaae392 | 2368 | while (!list_empty(&ring->active_list)) { |
05394f39 | 2369 | struct drm_i915_gem_object *obj; |
9375e446 | 2370 | |
05394f39 CW |
2371 | obj = list_first_entry(&ring->active_list, |
2372 | struct drm_i915_gem_object, | |
2373 | ring_list); | |
9375e446 | 2374 | |
05394f39 | 2375 | i915_gem_object_move_to_inactive(obj); |
673a394b EA |
2376 | } |
2377 | } | |
2378 | ||
19b2dbde | 2379 | void i915_gem_restore_fences(struct drm_device *dev) |
312817a3 CW |
2380 | { |
2381 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2382 | int i; | |
2383 | ||
4b9de737 | 2384 | for (i = 0; i < dev_priv->num_fence_regs; i++) { |
312817a3 | 2385 | struct drm_i915_fence_reg *reg = &dev_priv->fence_regs[i]; |
7d2cb39c | 2386 | |
94a335db DV |
2387 | /* |
2388 | * Commit delayed tiling changes if we have an object still | |
2389 | * attached to the fence, otherwise just clear the fence. | |
2390 | */ | |
2391 | if (reg->obj) { | |
2392 | i915_gem_object_update_fence(reg->obj, reg, | |
2393 | reg->obj->tiling_mode); | |
2394 | } else { | |
2395 | i915_gem_write_fence(dev, i, NULL); | |
2396 | } | |
312817a3 CW |
2397 | } |
2398 | } | |
2399 | ||
069efc1d | 2400 | void i915_gem_reset(struct drm_device *dev) |
673a394b | 2401 | { |
77f01230 | 2402 | struct drm_i915_private *dev_priv = dev->dev_private; |
b4519513 | 2403 | struct intel_ring_buffer *ring; |
1ec14ad3 | 2404 | int i; |
673a394b | 2405 | |
b4519513 CW |
2406 | for_each_ring(ring, dev_priv, i) |
2407 | i915_gem_reset_ring_lists(dev_priv, ring); | |
dfaae392 | 2408 | |
19b2dbde | 2409 | i915_gem_restore_fences(dev); |
673a394b EA |
2410 | } |
2411 | ||
2412 | /** | |
2413 | * This function clears the request list as sequence numbers are passed. | |
2414 | */ | |
a71d8d94 | 2415 | void |
db53a302 | 2416 | i915_gem_retire_requests_ring(struct intel_ring_buffer *ring) |
673a394b | 2417 | { |
673a394b EA |
2418 | uint32_t seqno; |
2419 | ||
db53a302 | 2420 | if (list_empty(&ring->request_list)) |
6c0594a3 KW |
2421 | return; |
2422 | ||
db53a302 | 2423 | WARN_ON(i915_verify_lists(ring->dev)); |
673a394b | 2424 | |
b2eadbc8 | 2425 | seqno = ring->get_seqno(ring, true); |
1ec14ad3 | 2426 | |
852835f3 | 2427 | while (!list_empty(&ring->request_list)) { |
673a394b | 2428 | struct drm_i915_gem_request *request; |
673a394b | 2429 | |
852835f3 | 2430 | request = list_first_entry(&ring->request_list, |
673a394b EA |
2431 | struct drm_i915_gem_request, |
2432 | list); | |
673a394b | 2433 | |
dfaae392 | 2434 | if (!i915_seqno_passed(seqno, request->seqno)) |
b84d5f0c CW |
2435 | break; |
2436 | ||
db53a302 | 2437 | trace_i915_gem_request_retire(ring, request->seqno); |
a71d8d94 CW |
2438 | /* We know the GPU must have read the request to have |
2439 | * sent us the seqno + interrupt, so use the position | |
2440 | * of tail of the request to update the last known position | |
2441 | * of the GPU head. | |
2442 | */ | |
2443 | ring->last_retired_head = request->tail; | |
b84d5f0c | 2444 | |
0e50e96b | 2445 | i915_gem_free_request(request); |
b84d5f0c | 2446 | } |
673a394b | 2447 | |
b84d5f0c CW |
2448 | /* Move any buffers on the active list that are no longer referenced |
2449 | * by the ringbuffer to the flushing/inactive lists as appropriate. | |
2450 | */ | |
2451 | while (!list_empty(&ring->active_list)) { | |
05394f39 | 2452 | struct drm_i915_gem_object *obj; |
b84d5f0c | 2453 | |
0206e353 | 2454 | obj = list_first_entry(&ring->active_list, |
05394f39 CW |
2455 | struct drm_i915_gem_object, |
2456 | ring_list); | |
673a394b | 2457 | |
0201f1ec | 2458 | if (!i915_seqno_passed(seqno, obj->last_read_seqno)) |
673a394b | 2459 | break; |
b84d5f0c | 2460 | |
65ce3027 | 2461 | i915_gem_object_move_to_inactive(obj); |
673a394b | 2462 | } |
9d34e5db | 2463 | |
db53a302 CW |
2464 | if (unlikely(ring->trace_irq_seqno && |
2465 | i915_seqno_passed(seqno, ring->trace_irq_seqno))) { | |
1ec14ad3 | 2466 | ring->irq_put(ring); |
db53a302 | 2467 | ring->trace_irq_seqno = 0; |
9d34e5db | 2468 | } |
23bc5982 | 2469 | |
db53a302 | 2470 | WARN_ON(i915_verify_lists(ring->dev)); |
673a394b EA |
2471 | } |
2472 | ||
b29c19b6 | 2473 | bool |
b09a1fec CW |
2474 | i915_gem_retire_requests(struct drm_device *dev) |
2475 | { | |
2476 | drm_i915_private_t *dev_priv = dev->dev_private; | |
b4519513 | 2477 | struct intel_ring_buffer *ring; |
b29c19b6 | 2478 | bool idle = true; |
1ec14ad3 | 2479 | int i; |
b09a1fec | 2480 | |
b29c19b6 | 2481 | for_each_ring(ring, dev_priv, i) { |
b4519513 | 2482 | i915_gem_retire_requests_ring(ring); |
b29c19b6 CW |
2483 | idle &= list_empty(&ring->request_list); |
2484 | } | |
2485 | ||
2486 | if (idle) | |
2487 | mod_delayed_work(dev_priv->wq, | |
2488 | &dev_priv->mm.idle_work, | |
2489 | msecs_to_jiffies(100)); | |
2490 | ||
2491 | return idle; | |
b09a1fec CW |
2492 | } |
2493 | ||
75ef9da2 | 2494 | static void |
673a394b EA |
2495 | i915_gem_retire_work_handler(struct work_struct *work) |
2496 | { | |
b29c19b6 CW |
2497 | struct drm_i915_private *dev_priv = |
2498 | container_of(work, typeof(*dev_priv), mm.retire_work.work); | |
2499 | struct drm_device *dev = dev_priv->dev; | |
0a58705b | 2500 | bool idle; |
673a394b | 2501 | |
891b48cf | 2502 | /* Come back later if the device is busy... */ |
b29c19b6 CW |
2503 | idle = false; |
2504 | if (mutex_trylock(&dev->struct_mutex)) { | |
2505 | idle = i915_gem_retire_requests(dev); | |
2506 | mutex_unlock(&dev->struct_mutex); | |
673a394b | 2507 | } |
b29c19b6 | 2508 | if (!idle) |
bcb45086 CW |
2509 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, |
2510 | round_jiffies_up_relative(HZ)); | |
b29c19b6 | 2511 | } |
0a58705b | 2512 | |
b29c19b6 CW |
2513 | static void |
2514 | i915_gem_idle_work_handler(struct work_struct *work) | |
2515 | { | |
2516 | struct drm_i915_private *dev_priv = | |
2517 | container_of(work, typeof(*dev_priv), mm.idle_work.work); | |
2518 | ||
2519 | intel_mark_idle(dev_priv->dev); | |
673a394b EA |
2520 | } |
2521 | ||
30dfebf3 DV |
2522 | /** |
2523 | * Ensures that an object will eventually get non-busy by flushing any required | |
2524 | * write domains, emitting any outstanding lazy request and retiring and | |
2525 | * completed requests. | |
2526 | */ | |
2527 | static int | |
2528 | i915_gem_object_flush_active(struct drm_i915_gem_object *obj) | |
2529 | { | |
2530 | int ret; | |
2531 | ||
2532 | if (obj->active) { | |
0201f1ec | 2533 | ret = i915_gem_check_olr(obj->ring, obj->last_read_seqno); |
30dfebf3 DV |
2534 | if (ret) |
2535 | return ret; | |
2536 | ||
30dfebf3 DV |
2537 | i915_gem_retire_requests_ring(obj->ring); |
2538 | } | |
2539 | ||
2540 | return 0; | |
2541 | } | |
2542 | ||
23ba4fd0 BW |
2543 | /** |
2544 | * i915_gem_wait_ioctl - implements DRM_IOCTL_I915_GEM_WAIT | |
2545 | * @DRM_IOCTL_ARGS: standard ioctl arguments | |
2546 | * | |
2547 | * Returns 0 if successful, else an error is returned with the remaining time in | |
2548 | * the timeout parameter. | |
2549 | * -ETIME: object is still busy after timeout | |
2550 | * -ERESTARTSYS: signal interrupted the wait | |
2551 | * -ENONENT: object doesn't exist | |
2552 | * Also possible, but rare: | |
2553 | * -EAGAIN: GPU wedged | |
2554 | * -ENOMEM: damn | |
2555 | * -ENODEV: Internal IRQ fail | |
2556 | * -E?: The add request failed | |
2557 | * | |
2558 | * The wait ioctl with a timeout of 0 reimplements the busy ioctl. With any | |
2559 | * non-zero timeout parameter the wait ioctl will wait for the given number of | |
2560 | * nanoseconds on an object becoming unbusy. Since the wait itself does so | |
2561 | * without holding struct_mutex the object may become re-busied before this | |
2562 | * function completes. A similar but shorter * race condition exists in the busy | |
2563 | * ioctl | |
2564 | */ | |
2565 | int | |
2566 | i915_gem_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *file) | |
2567 | { | |
f69061be | 2568 | drm_i915_private_t *dev_priv = dev->dev_private; |
23ba4fd0 BW |
2569 | struct drm_i915_gem_wait *args = data; |
2570 | struct drm_i915_gem_object *obj; | |
2571 | struct intel_ring_buffer *ring = NULL; | |
eac1f14f | 2572 | struct timespec timeout_stack, *timeout = NULL; |
f69061be | 2573 | unsigned reset_counter; |
23ba4fd0 BW |
2574 | u32 seqno = 0; |
2575 | int ret = 0; | |
2576 | ||
eac1f14f BW |
2577 | if (args->timeout_ns >= 0) { |
2578 | timeout_stack = ns_to_timespec(args->timeout_ns); | |
2579 | timeout = &timeout_stack; | |
2580 | } | |
23ba4fd0 BW |
2581 | |
2582 | ret = i915_mutex_lock_interruptible(dev); | |
2583 | if (ret) | |
2584 | return ret; | |
2585 | ||
2586 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->bo_handle)); | |
2587 | if (&obj->base == NULL) { | |
2588 | mutex_unlock(&dev->struct_mutex); | |
2589 | return -ENOENT; | |
2590 | } | |
2591 | ||
30dfebf3 DV |
2592 | /* Need to make sure the object gets inactive eventually. */ |
2593 | ret = i915_gem_object_flush_active(obj); | |
23ba4fd0 BW |
2594 | if (ret) |
2595 | goto out; | |
2596 | ||
2597 | if (obj->active) { | |
0201f1ec | 2598 | seqno = obj->last_read_seqno; |
23ba4fd0 BW |
2599 | ring = obj->ring; |
2600 | } | |
2601 | ||
2602 | if (seqno == 0) | |
2603 | goto out; | |
2604 | ||
23ba4fd0 BW |
2605 | /* Do this after OLR check to make sure we make forward progress polling |
2606 | * on this IOCTL with a 0 timeout (like busy ioctl) | |
2607 | */ | |
2608 | if (!args->timeout_ns) { | |
2609 | ret = -ETIME; | |
2610 | goto out; | |
2611 | } | |
2612 | ||
2613 | drm_gem_object_unreference(&obj->base); | |
f69061be | 2614 | reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter); |
23ba4fd0 BW |
2615 | mutex_unlock(&dev->struct_mutex); |
2616 | ||
b29c19b6 | 2617 | ret = __wait_seqno(ring, seqno, reset_counter, true, timeout, file->driver_priv); |
4f42f4ef | 2618 | if (timeout) |
eac1f14f | 2619 | args->timeout_ns = timespec_to_ns(timeout); |
23ba4fd0 BW |
2620 | return ret; |
2621 | ||
2622 | out: | |
2623 | drm_gem_object_unreference(&obj->base); | |
2624 | mutex_unlock(&dev->struct_mutex); | |
2625 | return ret; | |
2626 | } | |
2627 | ||
5816d648 BW |
2628 | /** |
2629 | * i915_gem_object_sync - sync an object to a ring. | |
2630 | * | |
2631 | * @obj: object which may be in use on another ring. | |
2632 | * @to: ring we wish to use the object on. May be NULL. | |
2633 | * | |
2634 | * This code is meant to abstract object synchronization with the GPU. | |
2635 | * Calling with NULL implies synchronizing the object with the CPU | |
2636 | * rather than a particular GPU ring. | |
2637 | * | |
2638 | * Returns 0 if successful, else propagates up the lower layer error. | |
2639 | */ | |
2911a35b BW |
2640 | int |
2641 | i915_gem_object_sync(struct drm_i915_gem_object *obj, | |
2642 | struct intel_ring_buffer *to) | |
2643 | { | |
2644 | struct intel_ring_buffer *from = obj->ring; | |
2645 | u32 seqno; | |
2646 | int ret, idx; | |
2647 | ||
2648 | if (from == NULL || to == from) | |
2649 | return 0; | |
2650 | ||
5816d648 | 2651 | if (to == NULL || !i915_semaphore_is_enabled(obj->base.dev)) |
0201f1ec | 2652 | return i915_gem_object_wait_rendering(obj, false); |
2911a35b BW |
2653 | |
2654 | idx = intel_ring_sync_index(from, to); | |
2655 | ||
0201f1ec | 2656 | seqno = obj->last_read_seqno; |
2911a35b BW |
2657 | if (seqno <= from->sync_seqno[idx]) |
2658 | return 0; | |
2659 | ||
b4aca010 BW |
2660 | ret = i915_gem_check_olr(obj->ring, seqno); |
2661 | if (ret) | |
2662 | return ret; | |
2911a35b | 2663 | |
b52b89da | 2664 | trace_i915_gem_ring_sync_to(from, to, seqno); |
1500f7ea | 2665 | ret = to->sync_to(to, from, seqno); |
e3a5a225 | 2666 | if (!ret) |
7b01e260 MK |
2667 | /* We use last_read_seqno because sync_to() |
2668 | * might have just caused seqno wrap under | |
2669 | * the radar. | |
2670 | */ | |
2671 | from->sync_seqno[idx] = obj->last_read_seqno; | |
2911a35b | 2672 | |
e3a5a225 | 2673 | return ret; |
2911a35b BW |
2674 | } |
2675 | ||
b5ffc9bc CW |
2676 | static void i915_gem_object_finish_gtt(struct drm_i915_gem_object *obj) |
2677 | { | |
2678 | u32 old_write_domain, old_read_domains; | |
2679 | ||
b5ffc9bc CW |
2680 | /* Force a pagefault for domain tracking on next user access */ |
2681 | i915_gem_release_mmap(obj); | |
2682 | ||
b97c3d9c KP |
2683 | if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0) |
2684 | return; | |
2685 | ||
97c809fd CW |
2686 | /* Wait for any direct GTT access to complete */ |
2687 | mb(); | |
2688 | ||
b5ffc9bc CW |
2689 | old_read_domains = obj->base.read_domains; |
2690 | old_write_domain = obj->base.write_domain; | |
2691 | ||
2692 | obj->base.read_domains &= ~I915_GEM_DOMAIN_GTT; | |
2693 | obj->base.write_domain &= ~I915_GEM_DOMAIN_GTT; | |
2694 | ||
2695 | trace_i915_gem_object_change_domain(obj, | |
2696 | old_read_domains, | |
2697 | old_write_domain); | |
2698 | } | |
2699 | ||
07fe0b12 | 2700 | int i915_vma_unbind(struct i915_vma *vma) |
673a394b | 2701 | { |
07fe0b12 | 2702 | struct drm_i915_gem_object *obj = vma->obj; |
7bddb01f | 2703 | drm_i915_private_t *dev_priv = obj->base.dev->dev_private; |
43e28f09 | 2704 | int ret; |
673a394b | 2705 | |
b93dab6e DV |
2706 | /* For now we only ever use 1 vma per object */ |
2707 | WARN_ON(!list_is_singular(&obj->vma_list)); | |
2708 | ||
07fe0b12 | 2709 | if (list_empty(&vma->vma_link)) |
673a394b EA |
2710 | return 0; |
2711 | ||
0ff501cb DV |
2712 | if (!drm_mm_node_allocated(&vma->node)) { |
2713 | i915_gem_vma_destroy(vma); | |
2714 | ||
2715 | return 0; | |
2716 | } | |
433544bd | 2717 | |
31d8d651 CW |
2718 | if (obj->pin_count) |
2719 | return -EBUSY; | |
673a394b | 2720 | |
c4670ad0 CW |
2721 | BUG_ON(obj->pages == NULL); |
2722 | ||
a8198eea | 2723 | ret = i915_gem_object_finish_gpu(obj); |
1488fc08 | 2724 | if (ret) |
a8198eea CW |
2725 | return ret; |
2726 | /* Continue on if we fail due to EIO, the GPU is hung so we | |
2727 | * should be safe and we need to cleanup or else we might | |
2728 | * cause memory corruption through use-after-free. | |
2729 | */ | |
2730 | ||
b5ffc9bc | 2731 | i915_gem_object_finish_gtt(obj); |
5323fd04 | 2732 | |
96b47b65 | 2733 | /* release the fence reg _after_ flushing */ |
d9e86c0e | 2734 | ret = i915_gem_object_put_fence(obj); |
1488fc08 | 2735 | if (ret) |
d9e86c0e | 2736 | return ret; |
96b47b65 | 2737 | |
07fe0b12 | 2738 | trace_i915_vma_unbind(vma); |
db53a302 | 2739 | |
74898d7e DV |
2740 | if (obj->has_global_gtt_mapping) |
2741 | i915_gem_gtt_unbind_object(obj); | |
7bddb01f DV |
2742 | if (obj->has_aliasing_ppgtt_mapping) { |
2743 | i915_ppgtt_unbind_object(dev_priv->mm.aliasing_ppgtt, obj); | |
2744 | obj->has_aliasing_ppgtt_mapping = 0; | |
2745 | } | |
74163907 | 2746 | i915_gem_gtt_finish_object(obj); |
401c29f6 | 2747 | i915_gem_object_unpin_pages(obj); |
7bddb01f | 2748 | |
ca191b13 | 2749 | list_del(&vma->mm_list); |
75e9e915 | 2750 | /* Avoid an unnecessary call to unbind on rebind. */ |
5cacaac7 BW |
2751 | if (i915_is_ggtt(vma->vm)) |
2752 | obj->map_and_fenceable = true; | |
673a394b | 2753 | |
2f633156 | 2754 | drm_mm_remove_node(&vma->node); |
433544bd | 2755 | |
2f633156 BW |
2756 | i915_gem_vma_destroy(vma); |
2757 | ||
2758 | /* Since the unbound list is global, only move to that list if | |
b93dab6e | 2759 | * no more VMAs exist. */ |
2f633156 BW |
2760 | if (list_empty(&obj->vma_list)) |
2761 | list_move_tail(&obj->global_list, &dev_priv->mm.unbound_list); | |
673a394b | 2762 | |
88241785 | 2763 | return 0; |
54cf91dc CW |
2764 | } |
2765 | ||
07fe0b12 BW |
2766 | /** |
2767 | * Unbinds an object from the global GTT aperture. | |
2768 | */ | |
2769 | int | |
2770 | i915_gem_object_ggtt_unbind(struct drm_i915_gem_object *obj) | |
2771 | { | |
2772 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; | |
2773 | struct i915_address_space *ggtt = &dev_priv->gtt.base; | |
2774 | ||
58e73e15 | 2775 | if (!i915_gem_obj_ggtt_bound(obj)) |
07fe0b12 BW |
2776 | return 0; |
2777 | ||
2778 | if (obj->pin_count) | |
2779 | return -EBUSY; | |
2780 | ||
2781 | BUG_ON(obj->pages == NULL); | |
2782 | ||
2783 | return i915_vma_unbind(i915_gem_obj_to_vma(obj, ggtt)); | |
2784 | } | |
2785 | ||
b2da9fe5 | 2786 | int i915_gpu_idle(struct drm_device *dev) |
4df2faf4 DV |
2787 | { |
2788 | drm_i915_private_t *dev_priv = dev->dev_private; | |
b4519513 | 2789 | struct intel_ring_buffer *ring; |
1ec14ad3 | 2790 | int ret, i; |
4df2faf4 | 2791 | |
4df2faf4 | 2792 | /* Flush everything onto the inactive list. */ |
b4519513 | 2793 | for_each_ring(ring, dev_priv, i) { |
b6c7488d BW |
2794 | ret = i915_switch_context(ring, NULL, DEFAULT_CONTEXT_ID); |
2795 | if (ret) | |
2796 | return ret; | |
2797 | ||
3e960501 | 2798 | ret = intel_ring_idle(ring); |
1ec14ad3 CW |
2799 | if (ret) |
2800 | return ret; | |
2801 | } | |
4df2faf4 | 2802 | |
8a1a49f9 | 2803 | return 0; |
4df2faf4 DV |
2804 | } |
2805 | ||
9ce079e4 CW |
2806 | static void i965_write_fence_reg(struct drm_device *dev, int reg, |
2807 | struct drm_i915_gem_object *obj) | |
de151cf6 | 2808 | { |
de151cf6 | 2809 | drm_i915_private_t *dev_priv = dev->dev_private; |
56c844e5 ID |
2810 | int fence_reg; |
2811 | int fence_pitch_shift; | |
de151cf6 | 2812 | |
56c844e5 ID |
2813 | if (INTEL_INFO(dev)->gen >= 6) { |
2814 | fence_reg = FENCE_REG_SANDYBRIDGE_0; | |
2815 | fence_pitch_shift = SANDYBRIDGE_FENCE_PITCH_SHIFT; | |
2816 | } else { | |
2817 | fence_reg = FENCE_REG_965_0; | |
2818 | fence_pitch_shift = I965_FENCE_PITCH_SHIFT; | |
2819 | } | |
2820 | ||
d18b9619 CW |
2821 | fence_reg += reg * 8; |
2822 | ||
2823 | /* To w/a incoherency with non-atomic 64-bit register updates, | |
2824 | * we split the 64-bit update into two 32-bit writes. In order | |
2825 | * for a partial fence not to be evaluated between writes, we | |
2826 | * precede the update with write to turn off the fence register, | |
2827 | * and only enable the fence as the last step. | |
2828 | * | |
2829 | * For extra levels of paranoia, we make sure each step lands | |
2830 | * before applying the next step. | |
2831 | */ | |
2832 | I915_WRITE(fence_reg, 0); | |
2833 | POSTING_READ(fence_reg); | |
2834 | ||
9ce079e4 | 2835 | if (obj) { |
f343c5f6 | 2836 | u32 size = i915_gem_obj_ggtt_size(obj); |
d18b9619 | 2837 | uint64_t val; |
de151cf6 | 2838 | |
f343c5f6 | 2839 | val = (uint64_t)((i915_gem_obj_ggtt_offset(obj) + size - 4096) & |
9ce079e4 | 2840 | 0xfffff000) << 32; |
f343c5f6 | 2841 | val |= i915_gem_obj_ggtt_offset(obj) & 0xfffff000; |
56c844e5 | 2842 | val |= (uint64_t)((obj->stride / 128) - 1) << fence_pitch_shift; |
9ce079e4 CW |
2843 | if (obj->tiling_mode == I915_TILING_Y) |
2844 | val |= 1 << I965_FENCE_TILING_Y_SHIFT; | |
2845 | val |= I965_FENCE_REG_VALID; | |
c6642782 | 2846 | |
d18b9619 CW |
2847 | I915_WRITE(fence_reg + 4, val >> 32); |
2848 | POSTING_READ(fence_reg + 4); | |
2849 | ||
2850 | I915_WRITE(fence_reg + 0, val); | |
2851 | POSTING_READ(fence_reg); | |
2852 | } else { | |
2853 | I915_WRITE(fence_reg + 4, 0); | |
2854 | POSTING_READ(fence_reg + 4); | |
2855 | } | |
de151cf6 JB |
2856 | } |
2857 | ||
9ce079e4 CW |
2858 | static void i915_write_fence_reg(struct drm_device *dev, int reg, |
2859 | struct drm_i915_gem_object *obj) | |
de151cf6 | 2860 | { |
de151cf6 | 2861 | drm_i915_private_t *dev_priv = dev->dev_private; |
9ce079e4 | 2862 | u32 val; |
de151cf6 | 2863 | |
9ce079e4 | 2864 | if (obj) { |
f343c5f6 | 2865 | u32 size = i915_gem_obj_ggtt_size(obj); |
9ce079e4 CW |
2866 | int pitch_val; |
2867 | int tile_width; | |
c6642782 | 2868 | |
f343c5f6 | 2869 | WARN((i915_gem_obj_ggtt_offset(obj) & ~I915_FENCE_START_MASK) || |
9ce079e4 | 2870 | (size & -size) != size || |
f343c5f6 BW |
2871 | (i915_gem_obj_ggtt_offset(obj) & (size - 1)), |
2872 | "object 0x%08lx [fenceable? %d] not 1M or pot-size (0x%08x) aligned\n", | |
2873 | i915_gem_obj_ggtt_offset(obj), obj->map_and_fenceable, size); | |
c6642782 | 2874 | |
9ce079e4 CW |
2875 | if (obj->tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev)) |
2876 | tile_width = 128; | |
2877 | else | |
2878 | tile_width = 512; | |
2879 | ||
2880 | /* Note: pitch better be a power of two tile widths */ | |
2881 | pitch_val = obj->stride / tile_width; | |
2882 | pitch_val = ffs(pitch_val) - 1; | |
2883 | ||
f343c5f6 | 2884 | val = i915_gem_obj_ggtt_offset(obj); |
9ce079e4 CW |
2885 | if (obj->tiling_mode == I915_TILING_Y) |
2886 | val |= 1 << I830_FENCE_TILING_Y_SHIFT; | |
2887 | val |= I915_FENCE_SIZE_BITS(size); | |
2888 | val |= pitch_val << I830_FENCE_PITCH_SHIFT; | |
2889 | val |= I830_FENCE_REG_VALID; | |
2890 | } else | |
2891 | val = 0; | |
2892 | ||
2893 | if (reg < 8) | |
2894 | reg = FENCE_REG_830_0 + reg * 4; | |
2895 | else | |
2896 | reg = FENCE_REG_945_8 + (reg - 8) * 4; | |
2897 | ||
2898 | I915_WRITE(reg, val); | |
2899 | POSTING_READ(reg); | |
de151cf6 JB |
2900 | } |
2901 | ||
9ce079e4 CW |
2902 | static void i830_write_fence_reg(struct drm_device *dev, int reg, |
2903 | struct drm_i915_gem_object *obj) | |
de151cf6 | 2904 | { |
de151cf6 | 2905 | drm_i915_private_t *dev_priv = dev->dev_private; |
de151cf6 | 2906 | uint32_t val; |
de151cf6 | 2907 | |
9ce079e4 | 2908 | if (obj) { |
f343c5f6 | 2909 | u32 size = i915_gem_obj_ggtt_size(obj); |
9ce079e4 | 2910 | uint32_t pitch_val; |
de151cf6 | 2911 | |
f343c5f6 | 2912 | WARN((i915_gem_obj_ggtt_offset(obj) & ~I830_FENCE_START_MASK) || |
9ce079e4 | 2913 | (size & -size) != size || |
f343c5f6 BW |
2914 | (i915_gem_obj_ggtt_offset(obj) & (size - 1)), |
2915 | "object 0x%08lx not 512K or pot-size 0x%08x aligned\n", | |
2916 | i915_gem_obj_ggtt_offset(obj), size); | |
e76a16de | 2917 | |
9ce079e4 CW |
2918 | pitch_val = obj->stride / 128; |
2919 | pitch_val = ffs(pitch_val) - 1; | |
de151cf6 | 2920 | |
f343c5f6 | 2921 | val = i915_gem_obj_ggtt_offset(obj); |
9ce079e4 CW |
2922 | if (obj->tiling_mode == I915_TILING_Y) |
2923 | val |= 1 << I830_FENCE_TILING_Y_SHIFT; | |
2924 | val |= I830_FENCE_SIZE_BITS(size); | |
2925 | val |= pitch_val << I830_FENCE_PITCH_SHIFT; | |
2926 | val |= I830_FENCE_REG_VALID; | |
2927 | } else | |
2928 | val = 0; | |
c6642782 | 2929 | |
9ce079e4 CW |
2930 | I915_WRITE(FENCE_REG_830_0 + reg * 4, val); |
2931 | POSTING_READ(FENCE_REG_830_0 + reg * 4); | |
2932 | } | |
2933 | ||
d0a57789 CW |
2934 | inline static bool i915_gem_object_needs_mb(struct drm_i915_gem_object *obj) |
2935 | { | |
2936 | return obj && obj->base.read_domains & I915_GEM_DOMAIN_GTT; | |
2937 | } | |
2938 | ||
9ce079e4 CW |
2939 | static void i915_gem_write_fence(struct drm_device *dev, int reg, |
2940 | struct drm_i915_gem_object *obj) | |
2941 | { | |
d0a57789 CW |
2942 | struct drm_i915_private *dev_priv = dev->dev_private; |
2943 | ||
2944 | /* Ensure that all CPU reads are completed before installing a fence | |
2945 | * and all writes before removing the fence. | |
2946 | */ | |
2947 | if (i915_gem_object_needs_mb(dev_priv->fence_regs[reg].obj)) | |
2948 | mb(); | |
2949 | ||
94a335db DV |
2950 | WARN(obj && (!obj->stride || !obj->tiling_mode), |
2951 | "bogus fence setup with stride: 0x%x, tiling mode: %i\n", | |
2952 | obj->stride, obj->tiling_mode); | |
2953 | ||
9ce079e4 CW |
2954 | switch (INTEL_INFO(dev)->gen) { |
2955 | case 7: | |
56c844e5 | 2956 | case 6: |
9ce079e4 CW |
2957 | case 5: |
2958 | case 4: i965_write_fence_reg(dev, reg, obj); break; | |
2959 | case 3: i915_write_fence_reg(dev, reg, obj); break; | |
2960 | case 2: i830_write_fence_reg(dev, reg, obj); break; | |
7dbf9d6e | 2961 | default: BUG(); |
9ce079e4 | 2962 | } |
d0a57789 CW |
2963 | |
2964 | /* And similarly be paranoid that no direct access to this region | |
2965 | * is reordered to before the fence is installed. | |
2966 | */ | |
2967 | if (i915_gem_object_needs_mb(obj)) | |
2968 | mb(); | |
de151cf6 JB |
2969 | } |
2970 | ||
61050808 CW |
2971 | static inline int fence_number(struct drm_i915_private *dev_priv, |
2972 | struct drm_i915_fence_reg *fence) | |
2973 | { | |
2974 | return fence - dev_priv->fence_regs; | |
2975 | } | |
2976 | ||
2977 | static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj, | |
2978 | struct drm_i915_fence_reg *fence, | |
2979 | bool enable) | |
2980 | { | |
2dc8aae0 | 2981 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
46a0b638 CW |
2982 | int reg = fence_number(dev_priv, fence); |
2983 | ||
2984 | i915_gem_write_fence(obj->base.dev, reg, enable ? obj : NULL); | |
61050808 CW |
2985 | |
2986 | if (enable) { | |
46a0b638 | 2987 | obj->fence_reg = reg; |
61050808 CW |
2988 | fence->obj = obj; |
2989 | list_move_tail(&fence->lru_list, &dev_priv->mm.fence_list); | |
2990 | } else { | |
2991 | obj->fence_reg = I915_FENCE_REG_NONE; | |
2992 | fence->obj = NULL; | |
2993 | list_del_init(&fence->lru_list); | |
2994 | } | |
94a335db | 2995 | obj->fence_dirty = false; |
61050808 CW |
2996 | } |
2997 | ||
d9e86c0e | 2998 | static int |
d0a57789 | 2999 | i915_gem_object_wait_fence(struct drm_i915_gem_object *obj) |
d9e86c0e | 3000 | { |
1c293ea3 | 3001 | if (obj->last_fenced_seqno) { |
86d5bc37 | 3002 | int ret = i915_wait_seqno(obj->ring, obj->last_fenced_seqno); |
18991845 CW |
3003 | if (ret) |
3004 | return ret; | |
d9e86c0e CW |
3005 | |
3006 | obj->last_fenced_seqno = 0; | |
d9e86c0e CW |
3007 | } |
3008 | ||
86d5bc37 | 3009 | obj->fenced_gpu_access = false; |
d9e86c0e CW |
3010 | return 0; |
3011 | } | |
3012 | ||
3013 | int | |
3014 | i915_gem_object_put_fence(struct drm_i915_gem_object *obj) | |
3015 | { | |
61050808 | 3016 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
f9c513e9 | 3017 | struct drm_i915_fence_reg *fence; |
d9e86c0e CW |
3018 | int ret; |
3019 | ||
d0a57789 | 3020 | ret = i915_gem_object_wait_fence(obj); |
d9e86c0e CW |
3021 | if (ret) |
3022 | return ret; | |
3023 | ||
61050808 CW |
3024 | if (obj->fence_reg == I915_FENCE_REG_NONE) |
3025 | return 0; | |
d9e86c0e | 3026 | |
f9c513e9 CW |
3027 | fence = &dev_priv->fence_regs[obj->fence_reg]; |
3028 | ||
61050808 | 3029 | i915_gem_object_fence_lost(obj); |
f9c513e9 | 3030 | i915_gem_object_update_fence(obj, fence, false); |
d9e86c0e CW |
3031 | |
3032 | return 0; | |
3033 | } | |
3034 | ||
3035 | static struct drm_i915_fence_reg * | |
a360bb1a | 3036 | i915_find_fence_reg(struct drm_device *dev) |
ae3db24a | 3037 | { |
ae3db24a | 3038 | struct drm_i915_private *dev_priv = dev->dev_private; |
8fe301ad | 3039 | struct drm_i915_fence_reg *reg, *avail; |
d9e86c0e | 3040 | int i; |
ae3db24a DV |
3041 | |
3042 | /* First try to find a free reg */ | |
d9e86c0e | 3043 | avail = NULL; |
ae3db24a DV |
3044 | for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) { |
3045 | reg = &dev_priv->fence_regs[i]; | |
3046 | if (!reg->obj) | |
d9e86c0e | 3047 | return reg; |
ae3db24a | 3048 | |
1690e1eb | 3049 | if (!reg->pin_count) |
d9e86c0e | 3050 | avail = reg; |
ae3db24a DV |
3051 | } |
3052 | ||
d9e86c0e CW |
3053 | if (avail == NULL) |
3054 | return NULL; | |
ae3db24a DV |
3055 | |
3056 | /* None available, try to steal one or wait for a user to finish */ | |
d9e86c0e | 3057 | list_for_each_entry(reg, &dev_priv->mm.fence_list, lru_list) { |
1690e1eb | 3058 | if (reg->pin_count) |
ae3db24a DV |
3059 | continue; |
3060 | ||
8fe301ad | 3061 | return reg; |
ae3db24a DV |
3062 | } |
3063 | ||
8fe301ad | 3064 | return NULL; |
ae3db24a DV |
3065 | } |
3066 | ||
de151cf6 | 3067 | /** |
9a5a53b3 | 3068 | * i915_gem_object_get_fence - set up fencing for an object |
de151cf6 JB |
3069 | * @obj: object to map through a fence reg |
3070 | * | |
3071 | * When mapping objects through the GTT, userspace wants to be able to write | |
3072 | * to them without having to worry about swizzling if the object is tiled. | |
de151cf6 JB |
3073 | * This function walks the fence regs looking for a free one for @obj, |
3074 | * stealing one if it can't find any. | |
3075 | * | |
3076 | * It then sets up the reg based on the object's properties: address, pitch | |
3077 | * and tiling format. | |
9a5a53b3 CW |
3078 | * |
3079 | * For an untiled surface, this removes any existing fence. | |
de151cf6 | 3080 | */ |
8c4b8c3f | 3081 | int |
06d98131 | 3082 | i915_gem_object_get_fence(struct drm_i915_gem_object *obj) |
de151cf6 | 3083 | { |
05394f39 | 3084 | struct drm_device *dev = obj->base.dev; |
79e53945 | 3085 | struct drm_i915_private *dev_priv = dev->dev_private; |
14415745 | 3086 | bool enable = obj->tiling_mode != I915_TILING_NONE; |
d9e86c0e | 3087 | struct drm_i915_fence_reg *reg; |
ae3db24a | 3088 | int ret; |
de151cf6 | 3089 | |
14415745 CW |
3090 | /* Have we updated the tiling parameters upon the object and so |
3091 | * will need to serialise the write to the associated fence register? | |
3092 | */ | |
5d82e3e6 | 3093 | if (obj->fence_dirty) { |
d0a57789 | 3094 | ret = i915_gem_object_wait_fence(obj); |
14415745 CW |
3095 | if (ret) |
3096 | return ret; | |
3097 | } | |
9a5a53b3 | 3098 | |
d9e86c0e | 3099 | /* Just update our place in the LRU if our fence is getting reused. */ |
05394f39 CW |
3100 | if (obj->fence_reg != I915_FENCE_REG_NONE) { |
3101 | reg = &dev_priv->fence_regs[obj->fence_reg]; | |
5d82e3e6 | 3102 | if (!obj->fence_dirty) { |
14415745 CW |
3103 | list_move_tail(®->lru_list, |
3104 | &dev_priv->mm.fence_list); | |
3105 | return 0; | |
3106 | } | |
3107 | } else if (enable) { | |
3108 | reg = i915_find_fence_reg(dev); | |
3109 | if (reg == NULL) | |
3110 | return -EDEADLK; | |
d9e86c0e | 3111 | |
14415745 CW |
3112 | if (reg->obj) { |
3113 | struct drm_i915_gem_object *old = reg->obj; | |
3114 | ||
d0a57789 | 3115 | ret = i915_gem_object_wait_fence(old); |
29c5a587 CW |
3116 | if (ret) |
3117 | return ret; | |
3118 | ||
14415745 | 3119 | i915_gem_object_fence_lost(old); |
29c5a587 | 3120 | } |
14415745 | 3121 | } else |
a09ba7fa | 3122 | return 0; |
a09ba7fa | 3123 | |
14415745 | 3124 | i915_gem_object_update_fence(obj, reg, enable); |
14415745 | 3125 | |
9ce079e4 | 3126 | return 0; |
de151cf6 JB |
3127 | } |
3128 | ||
42d6ab48 CW |
3129 | static bool i915_gem_valid_gtt_space(struct drm_device *dev, |
3130 | struct drm_mm_node *gtt_space, | |
3131 | unsigned long cache_level) | |
3132 | { | |
3133 | struct drm_mm_node *other; | |
3134 | ||
3135 | /* On non-LLC machines we have to be careful when putting differing | |
3136 | * types of snoopable memory together to avoid the prefetcher | |
4239ca77 | 3137 | * crossing memory domains and dying. |
42d6ab48 CW |
3138 | */ |
3139 | if (HAS_LLC(dev)) | |
3140 | return true; | |
3141 | ||
c6cfb325 | 3142 | if (!drm_mm_node_allocated(gtt_space)) |
42d6ab48 CW |
3143 | return true; |
3144 | ||
3145 | if (list_empty(>t_space->node_list)) | |
3146 | return true; | |
3147 | ||
3148 | other = list_entry(gtt_space->node_list.prev, struct drm_mm_node, node_list); | |
3149 | if (other->allocated && !other->hole_follows && other->color != cache_level) | |
3150 | return false; | |
3151 | ||
3152 | other = list_entry(gtt_space->node_list.next, struct drm_mm_node, node_list); | |
3153 | if (other->allocated && !gtt_space->hole_follows && other->color != cache_level) | |
3154 | return false; | |
3155 | ||
3156 | return true; | |
3157 | } | |
3158 | ||
3159 | static void i915_gem_verify_gtt(struct drm_device *dev) | |
3160 | { | |
3161 | #if WATCH_GTT | |
3162 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3163 | struct drm_i915_gem_object *obj; | |
3164 | int err = 0; | |
3165 | ||
35c20a60 | 3166 | list_for_each_entry(obj, &dev_priv->mm.gtt_list, global_list) { |
42d6ab48 CW |
3167 | if (obj->gtt_space == NULL) { |
3168 | printk(KERN_ERR "object found on GTT list with no space reserved\n"); | |
3169 | err++; | |
3170 | continue; | |
3171 | } | |
3172 | ||
3173 | if (obj->cache_level != obj->gtt_space->color) { | |
3174 | printk(KERN_ERR "object reserved space [%08lx, %08lx] with wrong color, cache_level=%x, color=%lx\n", | |
f343c5f6 BW |
3175 | i915_gem_obj_ggtt_offset(obj), |
3176 | i915_gem_obj_ggtt_offset(obj) + i915_gem_obj_ggtt_size(obj), | |
42d6ab48 CW |
3177 | obj->cache_level, |
3178 | obj->gtt_space->color); | |
3179 | err++; | |
3180 | continue; | |
3181 | } | |
3182 | ||
3183 | if (!i915_gem_valid_gtt_space(dev, | |
3184 | obj->gtt_space, | |
3185 | obj->cache_level)) { | |
3186 | printk(KERN_ERR "invalid GTT space found at [%08lx, %08lx] - color=%x\n", | |
f343c5f6 BW |
3187 | i915_gem_obj_ggtt_offset(obj), |
3188 | i915_gem_obj_ggtt_offset(obj) + i915_gem_obj_ggtt_size(obj), | |
42d6ab48 CW |
3189 | obj->cache_level); |
3190 | err++; | |
3191 | continue; | |
3192 | } | |
3193 | } | |
3194 | ||
3195 | WARN_ON(err); | |
3196 | #endif | |
3197 | } | |
3198 | ||
673a394b EA |
3199 | /** |
3200 | * Finds free space in the GTT aperture and binds the object there. | |
3201 | */ | |
3202 | static int | |
07fe0b12 BW |
3203 | i915_gem_object_bind_to_vm(struct drm_i915_gem_object *obj, |
3204 | struct i915_address_space *vm, | |
3205 | unsigned alignment, | |
3206 | bool map_and_fenceable, | |
3207 | bool nonblocking) | |
673a394b | 3208 | { |
05394f39 | 3209 | struct drm_device *dev = obj->base.dev; |
673a394b | 3210 | drm_i915_private_t *dev_priv = dev->dev_private; |
5e783301 | 3211 | u32 size, fence_size, fence_alignment, unfenced_alignment; |
07fe0b12 BW |
3212 | size_t gtt_max = |
3213 | map_and_fenceable ? dev_priv->gtt.mappable_end : vm->total; | |
2f633156 | 3214 | struct i915_vma *vma; |
07f73f69 | 3215 | int ret; |
673a394b | 3216 | |
e28f8711 CW |
3217 | fence_size = i915_gem_get_gtt_size(dev, |
3218 | obj->base.size, | |
3219 | obj->tiling_mode); | |
3220 | fence_alignment = i915_gem_get_gtt_alignment(dev, | |
3221 | obj->base.size, | |
d865110c | 3222 | obj->tiling_mode, true); |
e28f8711 | 3223 | unfenced_alignment = |
d865110c | 3224 | i915_gem_get_gtt_alignment(dev, |
e28f8711 | 3225 | obj->base.size, |
d865110c | 3226 | obj->tiling_mode, false); |
a00b10c3 | 3227 | |
673a394b | 3228 | if (alignment == 0) |
5e783301 DV |
3229 | alignment = map_and_fenceable ? fence_alignment : |
3230 | unfenced_alignment; | |
75e9e915 | 3231 | if (map_and_fenceable && alignment & (fence_alignment - 1)) { |
673a394b EA |
3232 | DRM_ERROR("Invalid object alignment requested %u\n", alignment); |
3233 | return -EINVAL; | |
3234 | } | |
3235 | ||
05394f39 | 3236 | size = map_and_fenceable ? fence_size : obj->base.size; |
a00b10c3 | 3237 | |
654fc607 CW |
3238 | /* If the object is bigger than the entire aperture, reject it early |
3239 | * before evicting everything in a vain attempt to find space. | |
3240 | */ | |
0a9ae0d7 | 3241 | if (obj->base.size > gtt_max) { |
3765f304 | 3242 | DRM_ERROR("Attempting to bind an object larger than the aperture: object=%zd > %s aperture=%zu\n", |
a36689cb CW |
3243 | obj->base.size, |
3244 | map_and_fenceable ? "mappable" : "total", | |
0a9ae0d7 | 3245 | gtt_max); |
654fc607 CW |
3246 | return -E2BIG; |
3247 | } | |
3248 | ||
37e680a1 | 3249 | ret = i915_gem_object_get_pages(obj); |
6c085a72 CW |
3250 | if (ret) |
3251 | return ret; | |
3252 | ||
fbdda6fb CW |
3253 | i915_gem_object_pin_pages(obj); |
3254 | ||
07fe0b12 | 3255 | BUG_ON(!i915_is_ggtt(vm)); |
07fe0b12 | 3256 | |
accfef2e | 3257 | vma = i915_gem_obj_lookup_or_create_vma(obj, vm); |
db473b36 | 3258 | if (IS_ERR(vma)) { |
bc6bc15b DV |
3259 | ret = PTR_ERR(vma); |
3260 | goto err_unpin; | |
2f633156 BW |
3261 | } |
3262 | ||
accfef2e BW |
3263 | /* For now we only ever use 1 vma per object */ |
3264 | WARN_ON(!list_is_singular(&obj->vma_list)); | |
3265 | ||
0a9ae0d7 | 3266 | search_free: |
07fe0b12 | 3267 | ret = drm_mm_insert_node_in_range_generic(&vm->mm, &vma->node, |
0a9ae0d7 | 3268 | size, alignment, |
31e5d7c6 DH |
3269 | obj->cache_level, 0, gtt_max, |
3270 | DRM_MM_SEARCH_DEFAULT); | |
dc9dd7a2 | 3271 | if (ret) { |
f6cd1f15 | 3272 | ret = i915_gem_evict_something(dev, vm, size, alignment, |
42d6ab48 | 3273 | obj->cache_level, |
86a1ee26 CW |
3274 | map_and_fenceable, |
3275 | nonblocking); | |
dc9dd7a2 CW |
3276 | if (ret == 0) |
3277 | goto search_free; | |
9731129c | 3278 | |
bc6bc15b | 3279 | goto err_free_vma; |
673a394b | 3280 | } |
2f633156 | 3281 | if (WARN_ON(!i915_gem_valid_gtt_space(dev, &vma->node, |
c6cfb325 | 3282 | obj->cache_level))) { |
2f633156 | 3283 | ret = -EINVAL; |
bc6bc15b | 3284 | goto err_remove_node; |
673a394b EA |
3285 | } |
3286 | ||
74163907 | 3287 | ret = i915_gem_gtt_prepare_object(obj); |
2f633156 | 3288 | if (ret) |
bc6bc15b | 3289 | goto err_remove_node; |
673a394b | 3290 | |
35c20a60 | 3291 | list_move_tail(&obj->global_list, &dev_priv->mm.bound_list); |
ca191b13 | 3292 | list_add_tail(&vma->mm_list, &vm->inactive_list); |
bf1a1092 | 3293 | |
4bd561b3 BW |
3294 | if (i915_is_ggtt(vm)) { |
3295 | bool mappable, fenceable; | |
a00b10c3 | 3296 | |
49987099 DV |
3297 | fenceable = (vma->node.size == fence_size && |
3298 | (vma->node.start & (fence_alignment - 1)) == 0); | |
4bd561b3 | 3299 | |
49987099 DV |
3300 | mappable = (vma->node.start + obj->base.size <= |
3301 | dev_priv->gtt.mappable_end); | |
a00b10c3 | 3302 | |
5cacaac7 | 3303 | obj->map_and_fenceable = mappable && fenceable; |
4bd561b3 | 3304 | } |
75e9e915 | 3305 | |
7ace7ef2 | 3306 | WARN_ON(map_and_fenceable && !obj->map_and_fenceable); |
75e9e915 | 3307 | |
07fe0b12 | 3308 | trace_i915_vma_bind(vma, map_and_fenceable); |
42d6ab48 | 3309 | i915_gem_verify_gtt(dev); |
673a394b | 3310 | return 0; |
2f633156 | 3311 | |
bc6bc15b | 3312 | err_remove_node: |
6286ef9b | 3313 | drm_mm_remove_node(&vma->node); |
bc6bc15b | 3314 | err_free_vma: |
2f633156 | 3315 | i915_gem_vma_destroy(vma); |
bc6bc15b | 3316 | err_unpin: |
2f633156 | 3317 | i915_gem_object_unpin_pages(obj); |
2f633156 | 3318 | return ret; |
673a394b EA |
3319 | } |
3320 | ||
000433b6 | 3321 | bool |
2c22569b CW |
3322 | i915_gem_clflush_object(struct drm_i915_gem_object *obj, |
3323 | bool force) | |
673a394b | 3324 | { |
673a394b EA |
3325 | /* If we don't have a page list set up, then we're not pinned |
3326 | * to GPU, and we can ignore the cache flush because it'll happen | |
3327 | * again at bind time. | |
3328 | */ | |
05394f39 | 3329 | if (obj->pages == NULL) |
000433b6 | 3330 | return false; |
673a394b | 3331 | |
769ce464 ID |
3332 | /* |
3333 | * Stolen memory is always coherent with the GPU as it is explicitly | |
3334 | * marked as wc by the system, or the system is cache-coherent. | |
3335 | */ | |
3336 | if (obj->stolen) | |
000433b6 | 3337 | return false; |
769ce464 | 3338 | |
9c23f7fc CW |
3339 | /* If the GPU is snooping the contents of the CPU cache, |
3340 | * we do not need to manually clear the CPU cache lines. However, | |
3341 | * the caches are only snooped when the render cache is | |
3342 | * flushed/invalidated. As we always have to emit invalidations | |
3343 | * and flushes when moving into and out of the RENDER domain, correct | |
3344 | * snooping behaviour occurs naturally as the result of our domain | |
3345 | * tracking. | |
3346 | */ | |
2c22569b | 3347 | if (!force && cpu_cache_is_coherent(obj->base.dev, obj->cache_level)) |
000433b6 | 3348 | return false; |
9c23f7fc | 3349 | |
1c5d22f7 | 3350 | trace_i915_gem_object_clflush(obj); |
9da3da66 | 3351 | drm_clflush_sg(obj->pages); |
000433b6 CW |
3352 | |
3353 | return true; | |
e47c68e9 EA |
3354 | } |
3355 | ||
3356 | /** Flushes the GTT write domain for the object if it's dirty. */ | |
3357 | static void | |
05394f39 | 3358 | i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj) |
e47c68e9 | 3359 | { |
1c5d22f7 CW |
3360 | uint32_t old_write_domain; |
3361 | ||
05394f39 | 3362 | if (obj->base.write_domain != I915_GEM_DOMAIN_GTT) |
e47c68e9 EA |
3363 | return; |
3364 | ||
63256ec5 | 3365 | /* No actual flushing is required for the GTT write domain. Writes |
e47c68e9 EA |
3366 | * to it immediately go to main memory as far as we know, so there's |
3367 | * no chipset flush. It also doesn't land in render cache. | |
63256ec5 CW |
3368 | * |
3369 | * However, we do have to enforce the order so that all writes through | |
3370 | * the GTT land before any writes to the device, such as updates to | |
3371 | * the GATT itself. | |
e47c68e9 | 3372 | */ |
63256ec5 CW |
3373 | wmb(); |
3374 | ||
05394f39 CW |
3375 | old_write_domain = obj->base.write_domain; |
3376 | obj->base.write_domain = 0; | |
1c5d22f7 CW |
3377 | |
3378 | trace_i915_gem_object_change_domain(obj, | |
05394f39 | 3379 | obj->base.read_domains, |
1c5d22f7 | 3380 | old_write_domain); |
e47c68e9 EA |
3381 | } |
3382 | ||
3383 | /** Flushes the CPU write domain for the object if it's dirty. */ | |
3384 | static void | |
2c22569b CW |
3385 | i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj, |
3386 | bool force) | |
e47c68e9 | 3387 | { |
1c5d22f7 | 3388 | uint32_t old_write_domain; |
e47c68e9 | 3389 | |
05394f39 | 3390 | if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) |
e47c68e9 EA |
3391 | return; |
3392 | ||
000433b6 CW |
3393 | if (i915_gem_clflush_object(obj, force)) |
3394 | i915_gem_chipset_flush(obj->base.dev); | |
3395 | ||
05394f39 CW |
3396 | old_write_domain = obj->base.write_domain; |
3397 | obj->base.write_domain = 0; | |
1c5d22f7 CW |
3398 | |
3399 | trace_i915_gem_object_change_domain(obj, | |
05394f39 | 3400 | obj->base.read_domains, |
1c5d22f7 | 3401 | old_write_domain); |
e47c68e9 EA |
3402 | } |
3403 | ||
2ef7eeaa EA |
3404 | /** |
3405 | * Moves a single object to the GTT read, and possibly write domain. | |
3406 | * | |
3407 | * This function returns when the move is complete, including waiting on | |
3408 | * flushes to occur. | |
3409 | */ | |
79e53945 | 3410 | int |
2021746e | 3411 | i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write) |
2ef7eeaa | 3412 | { |
8325a09d | 3413 | drm_i915_private_t *dev_priv = obj->base.dev->dev_private; |
1c5d22f7 | 3414 | uint32_t old_write_domain, old_read_domains; |
e47c68e9 | 3415 | int ret; |
2ef7eeaa | 3416 | |
02354392 | 3417 | /* Not valid to be called on unbound objects. */ |
9843877d | 3418 | if (!i915_gem_obj_bound_any(obj)) |
02354392 EA |
3419 | return -EINVAL; |
3420 | ||
8d7e3de1 CW |
3421 | if (obj->base.write_domain == I915_GEM_DOMAIN_GTT) |
3422 | return 0; | |
3423 | ||
0201f1ec | 3424 | ret = i915_gem_object_wait_rendering(obj, !write); |
88241785 CW |
3425 | if (ret) |
3426 | return ret; | |
3427 | ||
2c22569b | 3428 | i915_gem_object_flush_cpu_write_domain(obj, false); |
1c5d22f7 | 3429 | |
d0a57789 CW |
3430 | /* Serialise direct access to this object with the barriers for |
3431 | * coherent writes from the GPU, by effectively invalidating the | |
3432 | * GTT domain upon first access. | |
3433 | */ | |
3434 | if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0) | |
3435 | mb(); | |
3436 | ||
05394f39 CW |
3437 | old_write_domain = obj->base.write_domain; |
3438 | old_read_domains = obj->base.read_domains; | |
1c5d22f7 | 3439 | |
e47c68e9 EA |
3440 | /* It should now be out of any other write domains, and we can update |
3441 | * the domain values for our changes. | |
3442 | */ | |
05394f39 CW |
3443 | BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) != 0); |
3444 | obj->base.read_domains |= I915_GEM_DOMAIN_GTT; | |
e47c68e9 | 3445 | if (write) { |
05394f39 CW |
3446 | obj->base.read_domains = I915_GEM_DOMAIN_GTT; |
3447 | obj->base.write_domain = I915_GEM_DOMAIN_GTT; | |
3448 | obj->dirty = 1; | |
2ef7eeaa EA |
3449 | } |
3450 | ||
1c5d22f7 CW |
3451 | trace_i915_gem_object_change_domain(obj, |
3452 | old_read_domains, | |
3453 | old_write_domain); | |
3454 | ||
8325a09d | 3455 | /* And bump the LRU for this access */ |
ca191b13 | 3456 | if (i915_gem_object_is_inactive(obj)) { |
5c2abbea | 3457 | struct i915_vma *vma = i915_gem_obj_to_ggtt(obj); |
ca191b13 BW |
3458 | if (vma) |
3459 | list_move_tail(&vma->mm_list, | |
3460 | &dev_priv->gtt.base.inactive_list); | |
3461 | ||
3462 | } | |
8325a09d | 3463 | |
e47c68e9 EA |
3464 | return 0; |
3465 | } | |
3466 | ||
e4ffd173 CW |
3467 | int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj, |
3468 | enum i915_cache_level cache_level) | |
3469 | { | |
7bddb01f DV |
3470 | struct drm_device *dev = obj->base.dev; |
3471 | drm_i915_private_t *dev_priv = dev->dev_private; | |
3089c6f2 | 3472 | struct i915_vma *vma; |
e4ffd173 CW |
3473 | int ret; |
3474 | ||
3475 | if (obj->cache_level == cache_level) | |
3476 | return 0; | |
3477 | ||
3478 | if (obj->pin_count) { | |
3479 | DRM_DEBUG("can not change the cache level of pinned objects\n"); | |
3480 | return -EBUSY; | |
3481 | } | |
3482 | ||
3089c6f2 BW |
3483 | list_for_each_entry(vma, &obj->vma_list, vma_link) { |
3484 | if (!i915_gem_valid_gtt_space(dev, &vma->node, cache_level)) { | |
07fe0b12 | 3485 | ret = i915_vma_unbind(vma); |
3089c6f2 BW |
3486 | if (ret) |
3487 | return ret; | |
3488 | ||
3489 | break; | |
3490 | } | |
42d6ab48 CW |
3491 | } |
3492 | ||
3089c6f2 | 3493 | if (i915_gem_obj_bound_any(obj)) { |
e4ffd173 CW |
3494 | ret = i915_gem_object_finish_gpu(obj); |
3495 | if (ret) | |
3496 | return ret; | |
3497 | ||
3498 | i915_gem_object_finish_gtt(obj); | |
3499 | ||
3500 | /* Before SandyBridge, you could not use tiling or fence | |
3501 | * registers with snooped memory, so relinquish any fences | |
3502 | * currently pointing to our region in the aperture. | |
3503 | */ | |
42d6ab48 | 3504 | if (INTEL_INFO(dev)->gen < 6) { |
e4ffd173 CW |
3505 | ret = i915_gem_object_put_fence(obj); |
3506 | if (ret) | |
3507 | return ret; | |
3508 | } | |
3509 | ||
74898d7e DV |
3510 | if (obj->has_global_gtt_mapping) |
3511 | i915_gem_gtt_bind_object(obj, cache_level); | |
7bddb01f DV |
3512 | if (obj->has_aliasing_ppgtt_mapping) |
3513 | i915_ppgtt_bind_object(dev_priv->mm.aliasing_ppgtt, | |
3514 | obj, cache_level); | |
e4ffd173 CW |
3515 | } |
3516 | ||
2c22569b CW |
3517 | list_for_each_entry(vma, &obj->vma_list, vma_link) |
3518 | vma->node.color = cache_level; | |
3519 | obj->cache_level = cache_level; | |
3520 | ||
3521 | if (cpu_write_needs_clflush(obj)) { | |
e4ffd173 CW |
3522 | u32 old_read_domains, old_write_domain; |
3523 | ||
3524 | /* If we're coming from LLC cached, then we haven't | |
3525 | * actually been tracking whether the data is in the | |
3526 | * CPU cache or not, since we only allow one bit set | |
3527 | * in obj->write_domain and have been skipping the clflushes. | |
3528 | * Just set it to the CPU cache for now. | |
3529 | */ | |
3530 | WARN_ON(obj->base.write_domain & ~I915_GEM_DOMAIN_CPU); | |
e4ffd173 CW |
3531 | |
3532 | old_read_domains = obj->base.read_domains; | |
3533 | old_write_domain = obj->base.write_domain; | |
3534 | ||
3535 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; | |
3536 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; | |
3537 | ||
3538 | trace_i915_gem_object_change_domain(obj, | |
3539 | old_read_domains, | |
3540 | old_write_domain); | |
3541 | } | |
3542 | ||
42d6ab48 | 3543 | i915_gem_verify_gtt(dev); |
e4ffd173 CW |
3544 | return 0; |
3545 | } | |
3546 | ||
199adf40 BW |
3547 | int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data, |
3548 | struct drm_file *file) | |
e6994aee | 3549 | { |
199adf40 | 3550 | struct drm_i915_gem_caching *args = data; |
e6994aee CW |
3551 | struct drm_i915_gem_object *obj; |
3552 | int ret; | |
3553 | ||
3554 | ret = i915_mutex_lock_interruptible(dev); | |
3555 | if (ret) | |
3556 | return ret; | |
3557 | ||
3558 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); | |
3559 | if (&obj->base == NULL) { | |
3560 | ret = -ENOENT; | |
3561 | goto unlock; | |
3562 | } | |
3563 | ||
651d794f CW |
3564 | switch (obj->cache_level) { |
3565 | case I915_CACHE_LLC: | |
3566 | case I915_CACHE_L3_LLC: | |
3567 | args->caching = I915_CACHING_CACHED; | |
3568 | break; | |
3569 | ||
4257d3ba CW |
3570 | case I915_CACHE_WT: |
3571 | args->caching = I915_CACHING_DISPLAY; | |
3572 | break; | |
3573 | ||
651d794f CW |
3574 | default: |
3575 | args->caching = I915_CACHING_NONE; | |
3576 | break; | |
3577 | } | |
e6994aee CW |
3578 | |
3579 | drm_gem_object_unreference(&obj->base); | |
3580 | unlock: | |
3581 | mutex_unlock(&dev->struct_mutex); | |
3582 | return ret; | |
3583 | } | |
3584 | ||
199adf40 BW |
3585 | int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data, |
3586 | struct drm_file *file) | |
e6994aee | 3587 | { |
199adf40 | 3588 | struct drm_i915_gem_caching *args = data; |
e6994aee CW |
3589 | struct drm_i915_gem_object *obj; |
3590 | enum i915_cache_level level; | |
3591 | int ret; | |
3592 | ||
199adf40 BW |
3593 | switch (args->caching) { |
3594 | case I915_CACHING_NONE: | |
e6994aee CW |
3595 | level = I915_CACHE_NONE; |
3596 | break; | |
199adf40 | 3597 | case I915_CACHING_CACHED: |
e6994aee CW |
3598 | level = I915_CACHE_LLC; |
3599 | break; | |
4257d3ba CW |
3600 | case I915_CACHING_DISPLAY: |
3601 | level = HAS_WT(dev) ? I915_CACHE_WT : I915_CACHE_NONE; | |
3602 | break; | |
e6994aee CW |
3603 | default: |
3604 | return -EINVAL; | |
3605 | } | |
3606 | ||
3bc2913e BW |
3607 | ret = i915_mutex_lock_interruptible(dev); |
3608 | if (ret) | |
3609 | return ret; | |
3610 | ||
e6994aee CW |
3611 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
3612 | if (&obj->base == NULL) { | |
3613 | ret = -ENOENT; | |
3614 | goto unlock; | |
3615 | } | |
3616 | ||
3617 | ret = i915_gem_object_set_cache_level(obj, level); | |
3618 | ||
3619 | drm_gem_object_unreference(&obj->base); | |
3620 | unlock: | |
3621 | mutex_unlock(&dev->struct_mutex); | |
3622 | return ret; | |
3623 | } | |
3624 | ||
cc98b413 CW |
3625 | static bool is_pin_display(struct drm_i915_gem_object *obj) |
3626 | { | |
3627 | /* There are 3 sources that pin objects: | |
3628 | * 1. The display engine (scanouts, sprites, cursors); | |
3629 | * 2. Reservations for execbuffer; | |
3630 | * 3. The user. | |
3631 | * | |
3632 | * We can ignore reservations as we hold the struct_mutex and | |
3633 | * are only called outside of the reservation path. The user | |
3634 | * can only increment pin_count once, and so if after | |
3635 | * subtracting the potential reference by the user, any pin_count | |
3636 | * remains, it must be due to another use by the display engine. | |
3637 | */ | |
3638 | return obj->pin_count - !!obj->user_pin_count; | |
3639 | } | |
3640 | ||
b9241ea3 | 3641 | /* |
2da3b9b9 CW |
3642 | * Prepare buffer for display plane (scanout, cursors, etc). |
3643 | * Can be called from an uninterruptible phase (modesetting) and allows | |
3644 | * any flushes to be pipelined (for pageflips). | |
b9241ea3 ZW |
3645 | */ |
3646 | int | |
2da3b9b9 CW |
3647 | i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj, |
3648 | u32 alignment, | |
919926ae | 3649 | struct intel_ring_buffer *pipelined) |
b9241ea3 | 3650 | { |
2da3b9b9 | 3651 | u32 old_read_domains, old_write_domain; |
b9241ea3 ZW |
3652 | int ret; |
3653 | ||
0be73284 | 3654 | if (pipelined != obj->ring) { |
2911a35b BW |
3655 | ret = i915_gem_object_sync(obj, pipelined); |
3656 | if (ret) | |
b9241ea3 ZW |
3657 | return ret; |
3658 | } | |
3659 | ||
cc98b413 CW |
3660 | /* Mark the pin_display early so that we account for the |
3661 | * display coherency whilst setting up the cache domains. | |
3662 | */ | |
3663 | obj->pin_display = true; | |
3664 | ||
a7ef0640 EA |
3665 | /* The display engine is not coherent with the LLC cache on gen6. As |
3666 | * a result, we make sure that the pinning that is about to occur is | |
3667 | * done with uncached PTEs. This is lowest common denominator for all | |
3668 | * chipsets. | |
3669 | * | |
3670 | * However for gen6+, we could do better by using the GFDT bit instead | |
3671 | * of uncaching, which would allow us to flush all the LLC-cached data | |
3672 | * with that bit in the PTE to main memory with just one PIPE_CONTROL. | |
3673 | */ | |
651d794f CW |
3674 | ret = i915_gem_object_set_cache_level(obj, |
3675 | HAS_WT(obj->base.dev) ? I915_CACHE_WT : I915_CACHE_NONE); | |
a7ef0640 | 3676 | if (ret) |
cc98b413 | 3677 | goto err_unpin_display; |
a7ef0640 | 3678 | |
2da3b9b9 CW |
3679 | /* As the user may map the buffer once pinned in the display plane |
3680 | * (e.g. libkms for the bootup splash), we have to ensure that we | |
3681 | * always use map_and_fenceable for all scanout buffers. | |
3682 | */ | |
c37e2204 | 3683 | ret = i915_gem_obj_ggtt_pin(obj, alignment, true, false); |
2da3b9b9 | 3684 | if (ret) |
cc98b413 | 3685 | goto err_unpin_display; |
2da3b9b9 | 3686 | |
2c22569b | 3687 | i915_gem_object_flush_cpu_write_domain(obj, true); |
b118c1e3 | 3688 | |
2da3b9b9 | 3689 | old_write_domain = obj->base.write_domain; |
05394f39 | 3690 | old_read_domains = obj->base.read_domains; |
2da3b9b9 CW |
3691 | |
3692 | /* It should now be out of any other write domains, and we can update | |
3693 | * the domain values for our changes. | |
3694 | */ | |
e5f1d962 | 3695 | obj->base.write_domain = 0; |
05394f39 | 3696 | obj->base.read_domains |= I915_GEM_DOMAIN_GTT; |
b9241ea3 ZW |
3697 | |
3698 | trace_i915_gem_object_change_domain(obj, | |
3699 | old_read_domains, | |
2da3b9b9 | 3700 | old_write_domain); |
b9241ea3 ZW |
3701 | |
3702 | return 0; | |
cc98b413 CW |
3703 | |
3704 | err_unpin_display: | |
3705 | obj->pin_display = is_pin_display(obj); | |
3706 | return ret; | |
3707 | } | |
3708 | ||
3709 | void | |
3710 | i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object *obj) | |
3711 | { | |
3712 | i915_gem_object_unpin(obj); | |
3713 | obj->pin_display = is_pin_display(obj); | |
b9241ea3 ZW |
3714 | } |
3715 | ||
85345517 | 3716 | int |
a8198eea | 3717 | i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj) |
85345517 | 3718 | { |
88241785 CW |
3719 | int ret; |
3720 | ||
a8198eea | 3721 | if ((obj->base.read_domains & I915_GEM_GPU_DOMAINS) == 0) |
85345517 CW |
3722 | return 0; |
3723 | ||
0201f1ec | 3724 | ret = i915_gem_object_wait_rendering(obj, false); |
c501ae7f CW |
3725 | if (ret) |
3726 | return ret; | |
3727 | ||
a8198eea CW |
3728 | /* Ensure that we invalidate the GPU's caches and TLBs. */ |
3729 | obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS; | |
c501ae7f | 3730 | return 0; |
85345517 CW |
3731 | } |
3732 | ||
e47c68e9 EA |
3733 | /** |
3734 | * Moves a single object to the CPU read, and possibly write domain. | |
3735 | * | |
3736 | * This function returns when the move is complete, including waiting on | |
3737 | * flushes to occur. | |
3738 | */ | |
dabdfe02 | 3739 | int |
919926ae | 3740 | i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write) |
e47c68e9 | 3741 | { |
1c5d22f7 | 3742 | uint32_t old_write_domain, old_read_domains; |
e47c68e9 EA |
3743 | int ret; |
3744 | ||
8d7e3de1 CW |
3745 | if (obj->base.write_domain == I915_GEM_DOMAIN_CPU) |
3746 | return 0; | |
3747 | ||
0201f1ec | 3748 | ret = i915_gem_object_wait_rendering(obj, !write); |
88241785 CW |
3749 | if (ret) |
3750 | return ret; | |
3751 | ||
e47c68e9 | 3752 | i915_gem_object_flush_gtt_write_domain(obj); |
2ef7eeaa | 3753 | |
05394f39 CW |
3754 | old_write_domain = obj->base.write_domain; |
3755 | old_read_domains = obj->base.read_domains; | |
1c5d22f7 | 3756 | |
e47c68e9 | 3757 | /* Flush the CPU cache if it's still invalid. */ |
05394f39 | 3758 | if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) { |
2c22569b | 3759 | i915_gem_clflush_object(obj, false); |
2ef7eeaa | 3760 | |
05394f39 | 3761 | obj->base.read_domains |= I915_GEM_DOMAIN_CPU; |
2ef7eeaa EA |
3762 | } |
3763 | ||
3764 | /* It should now be out of any other write domains, and we can update | |
3765 | * the domain values for our changes. | |
3766 | */ | |
05394f39 | 3767 | BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) != 0); |
e47c68e9 EA |
3768 | |
3769 | /* If we're writing through the CPU, then the GPU read domains will | |
3770 | * need to be invalidated at next use. | |
3771 | */ | |
3772 | if (write) { | |
05394f39 CW |
3773 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; |
3774 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; | |
e47c68e9 | 3775 | } |
2ef7eeaa | 3776 | |
1c5d22f7 CW |
3777 | trace_i915_gem_object_change_domain(obj, |
3778 | old_read_domains, | |
3779 | old_write_domain); | |
3780 | ||
2ef7eeaa EA |
3781 | return 0; |
3782 | } | |
3783 | ||
673a394b EA |
3784 | /* Throttle our rendering by waiting until the ring has completed our requests |
3785 | * emitted over 20 msec ago. | |
3786 | * | |
b962442e EA |
3787 | * Note that if we were to use the current jiffies each time around the loop, |
3788 | * we wouldn't escape the function with any frames outstanding if the time to | |
3789 | * render a frame was over 20ms. | |
3790 | * | |
673a394b EA |
3791 | * This should get us reasonable parallelism between CPU and GPU but also |
3792 | * relatively low latency when blocking on a particular request to finish. | |
3793 | */ | |
40a5f0de | 3794 | static int |
f787a5f5 | 3795 | i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file) |
40a5f0de | 3796 | { |
f787a5f5 CW |
3797 | struct drm_i915_private *dev_priv = dev->dev_private; |
3798 | struct drm_i915_file_private *file_priv = file->driver_priv; | |
b962442e | 3799 | unsigned long recent_enough = jiffies - msecs_to_jiffies(20); |
f787a5f5 CW |
3800 | struct drm_i915_gem_request *request; |
3801 | struct intel_ring_buffer *ring = NULL; | |
f69061be | 3802 | unsigned reset_counter; |
f787a5f5 CW |
3803 | u32 seqno = 0; |
3804 | int ret; | |
93533c29 | 3805 | |
308887aa DV |
3806 | ret = i915_gem_wait_for_error(&dev_priv->gpu_error); |
3807 | if (ret) | |
3808 | return ret; | |
3809 | ||
3810 | ret = i915_gem_check_wedge(&dev_priv->gpu_error, false); | |
3811 | if (ret) | |
3812 | return ret; | |
e110e8d6 | 3813 | |
1c25595f | 3814 | spin_lock(&file_priv->mm.lock); |
f787a5f5 | 3815 | list_for_each_entry(request, &file_priv->mm.request_list, client_list) { |
b962442e EA |
3816 | if (time_after_eq(request->emitted_jiffies, recent_enough)) |
3817 | break; | |
40a5f0de | 3818 | |
f787a5f5 CW |
3819 | ring = request->ring; |
3820 | seqno = request->seqno; | |
b962442e | 3821 | } |
f69061be | 3822 | reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter); |
1c25595f | 3823 | spin_unlock(&file_priv->mm.lock); |
40a5f0de | 3824 | |
f787a5f5 CW |
3825 | if (seqno == 0) |
3826 | return 0; | |
2bc43b5c | 3827 | |
b29c19b6 | 3828 | ret = __wait_seqno(ring, seqno, reset_counter, true, NULL, NULL); |
f787a5f5 CW |
3829 | if (ret == 0) |
3830 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, 0); | |
40a5f0de EA |
3831 | |
3832 | return ret; | |
3833 | } | |
3834 | ||
673a394b | 3835 | int |
05394f39 | 3836 | i915_gem_object_pin(struct drm_i915_gem_object *obj, |
c37e2204 | 3837 | struct i915_address_space *vm, |
05394f39 | 3838 | uint32_t alignment, |
86a1ee26 CW |
3839 | bool map_and_fenceable, |
3840 | bool nonblocking) | |
673a394b | 3841 | { |
07fe0b12 | 3842 | struct i915_vma *vma; |
673a394b EA |
3843 | int ret; |
3844 | ||
7e81a42e CW |
3845 | if (WARN_ON(obj->pin_count == DRM_I915_GEM_OBJECT_MAX_PIN_COUNT)) |
3846 | return -EBUSY; | |
ac0c6b5a | 3847 | |
07fe0b12 BW |
3848 | WARN_ON(map_and_fenceable && !i915_is_ggtt(vm)); |
3849 | ||
3850 | vma = i915_gem_obj_to_vma(obj, vm); | |
3851 | ||
3852 | if (vma) { | |
3853 | if ((alignment && | |
3854 | vma->node.start & (alignment - 1)) || | |
05394f39 CW |
3855 | (map_and_fenceable && !obj->map_and_fenceable)) { |
3856 | WARN(obj->pin_count, | |
ae7d49d8 | 3857 | "bo is already pinned with incorrect alignment:" |
f343c5f6 | 3858 | " offset=%lx, req.alignment=%x, req.map_and_fenceable=%d," |
75e9e915 | 3859 | " obj->map_and_fenceable=%d\n", |
07fe0b12 | 3860 | i915_gem_obj_offset(obj, vm), alignment, |
75e9e915 | 3861 | map_and_fenceable, |
05394f39 | 3862 | obj->map_and_fenceable); |
07fe0b12 | 3863 | ret = i915_vma_unbind(vma); |
ac0c6b5a CW |
3864 | if (ret) |
3865 | return ret; | |
3866 | } | |
3867 | } | |
3868 | ||
07fe0b12 | 3869 | if (!i915_gem_obj_bound(obj, vm)) { |
8742267a CW |
3870 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
3871 | ||
07fe0b12 BW |
3872 | ret = i915_gem_object_bind_to_vm(obj, vm, alignment, |
3873 | map_and_fenceable, | |
3874 | nonblocking); | |
9731129c | 3875 | if (ret) |
673a394b | 3876 | return ret; |
8742267a CW |
3877 | |
3878 | if (!dev_priv->mm.aliasing_ppgtt) | |
3879 | i915_gem_gtt_bind_object(obj, obj->cache_level); | |
22c344e9 | 3880 | } |
76446cac | 3881 | |
74898d7e DV |
3882 | if (!obj->has_global_gtt_mapping && map_and_fenceable) |
3883 | i915_gem_gtt_bind_object(obj, obj->cache_level); | |
3884 | ||
1b50247a | 3885 | obj->pin_count++; |
6299f992 | 3886 | obj->pin_mappable |= map_and_fenceable; |
673a394b EA |
3887 | |
3888 | return 0; | |
3889 | } | |
3890 | ||
3891 | void | |
05394f39 | 3892 | i915_gem_object_unpin(struct drm_i915_gem_object *obj) |
673a394b | 3893 | { |
05394f39 | 3894 | BUG_ON(obj->pin_count == 0); |
9843877d | 3895 | BUG_ON(!i915_gem_obj_bound_any(obj)); |
673a394b | 3896 | |
1b50247a | 3897 | if (--obj->pin_count == 0) |
6299f992 | 3898 | obj->pin_mappable = false; |
673a394b EA |
3899 | } |
3900 | ||
3901 | int | |
3902 | i915_gem_pin_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 3903 | struct drm_file *file) |
673a394b EA |
3904 | { |
3905 | struct drm_i915_gem_pin *args = data; | |
05394f39 | 3906 | struct drm_i915_gem_object *obj; |
673a394b EA |
3907 | int ret; |
3908 | ||
1d7cfea1 CW |
3909 | ret = i915_mutex_lock_interruptible(dev); |
3910 | if (ret) | |
3911 | return ret; | |
673a394b | 3912 | |
05394f39 | 3913 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 3914 | if (&obj->base == NULL) { |
1d7cfea1 CW |
3915 | ret = -ENOENT; |
3916 | goto unlock; | |
673a394b | 3917 | } |
673a394b | 3918 | |
05394f39 | 3919 | if (obj->madv != I915_MADV_WILLNEED) { |
bb6baf76 | 3920 | DRM_ERROR("Attempting to pin a purgeable buffer\n"); |
1d7cfea1 CW |
3921 | ret = -EINVAL; |
3922 | goto out; | |
3ef94daa CW |
3923 | } |
3924 | ||
05394f39 | 3925 | if (obj->pin_filp != NULL && obj->pin_filp != file) { |
79e53945 JB |
3926 | DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n", |
3927 | args->handle); | |
1d7cfea1 CW |
3928 | ret = -EINVAL; |
3929 | goto out; | |
79e53945 JB |
3930 | } |
3931 | ||
93be8788 | 3932 | if (obj->user_pin_count == 0) { |
c37e2204 | 3933 | ret = i915_gem_obj_ggtt_pin(obj, args->alignment, true, false); |
1d7cfea1 CW |
3934 | if (ret) |
3935 | goto out; | |
673a394b EA |
3936 | } |
3937 | ||
93be8788 CW |
3938 | obj->user_pin_count++; |
3939 | obj->pin_filp = file; | |
3940 | ||
f343c5f6 | 3941 | args->offset = i915_gem_obj_ggtt_offset(obj); |
1d7cfea1 | 3942 | out: |
05394f39 | 3943 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 3944 | unlock: |
673a394b | 3945 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 3946 | return ret; |
673a394b EA |
3947 | } |
3948 | ||
3949 | int | |
3950 | i915_gem_unpin_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 3951 | struct drm_file *file) |
673a394b EA |
3952 | { |
3953 | struct drm_i915_gem_pin *args = data; | |
05394f39 | 3954 | struct drm_i915_gem_object *obj; |
76c1dec1 | 3955 | int ret; |
673a394b | 3956 | |
1d7cfea1 CW |
3957 | ret = i915_mutex_lock_interruptible(dev); |
3958 | if (ret) | |
3959 | return ret; | |
673a394b | 3960 | |
05394f39 | 3961 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 3962 | if (&obj->base == NULL) { |
1d7cfea1 CW |
3963 | ret = -ENOENT; |
3964 | goto unlock; | |
673a394b | 3965 | } |
76c1dec1 | 3966 | |
05394f39 | 3967 | if (obj->pin_filp != file) { |
79e53945 JB |
3968 | DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n", |
3969 | args->handle); | |
1d7cfea1 CW |
3970 | ret = -EINVAL; |
3971 | goto out; | |
79e53945 | 3972 | } |
05394f39 CW |
3973 | obj->user_pin_count--; |
3974 | if (obj->user_pin_count == 0) { | |
3975 | obj->pin_filp = NULL; | |
79e53945 JB |
3976 | i915_gem_object_unpin(obj); |
3977 | } | |
673a394b | 3978 | |
1d7cfea1 | 3979 | out: |
05394f39 | 3980 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 3981 | unlock: |
673a394b | 3982 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 3983 | return ret; |
673a394b EA |
3984 | } |
3985 | ||
3986 | int | |
3987 | i915_gem_busy_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 3988 | struct drm_file *file) |
673a394b EA |
3989 | { |
3990 | struct drm_i915_gem_busy *args = data; | |
05394f39 | 3991 | struct drm_i915_gem_object *obj; |
30dbf0c0 CW |
3992 | int ret; |
3993 | ||
76c1dec1 | 3994 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 3995 | if (ret) |
76c1dec1 | 3996 | return ret; |
673a394b | 3997 | |
05394f39 | 3998 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 3999 | if (&obj->base == NULL) { |
1d7cfea1 CW |
4000 | ret = -ENOENT; |
4001 | goto unlock; | |
673a394b | 4002 | } |
d1b851fc | 4003 | |
0be555b6 CW |
4004 | /* Count all active objects as busy, even if they are currently not used |
4005 | * by the gpu. Users of this interface expect objects to eventually | |
4006 | * become non-busy without any further actions, therefore emit any | |
4007 | * necessary flushes here. | |
c4de0a5d | 4008 | */ |
30dfebf3 | 4009 | ret = i915_gem_object_flush_active(obj); |
0be555b6 | 4010 | |
30dfebf3 | 4011 | args->busy = obj->active; |
e9808edd CW |
4012 | if (obj->ring) { |
4013 | BUILD_BUG_ON(I915_NUM_RINGS > 16); | |
4014 | args->busy |= intel_ring_flag(obj->ring) << 16; | |
4015 | } | |
673a394b | 4016 | |
05394f39 | 4017 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 4018 | unlock: |
673a394b | 4019 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 4020 | return ret; |
673a394b EA |
4021 | } |
4022 | ||
4023 | int | |
4024 | i915_gem_throttle_ioctl(struct drm_device *dev, void *data, | |
4025 | struct drm_file *file_priv) | |
4026 | { | |
0206e353 | 4027 | return i915_gem_ring_throttle(dev, file_priv); |
673a394b EA |
4028 | } |
4029 | ||
3ef94daa CW |
4030 | int |
4031 | i915_gem_madvise_ioctl(struct drm_device *dev, void *data, | |
4032 | struct drm_file *file_priv) | |
4033 | { | |
4034 | struct drm_i915_gem_madvise *args = data; | |
05394f39 | 4035 | struct drm_i915_gem_object *obj; |
76c1dec1 | 4036 | int ret; |
3ef94daa CW |
4037 | |
4038 | switch (args->madv) { | |
4039 | case I915_MADV_DONTNEED: | |
4040 | case I915_MADV_WILLNEED: | |
4041 | break; | |
4042 | default: | |
4043 | return -EINVAL; | |
4044 | } | |
4045 | ||
1d7cfea1 CW |
4046 | ret = i915_mutex_lock_interruptible(dev); |
4047 | if (ret) | |
4048 | return ret; | |
4049 | ||
05394f39 | 4050 | obj = to_intel_bo(drm_gem_object_lookup(dev, file_priv, args->handle)); |
c8725226 | 4051 | if (&obj->base == NULL) { |
1d7cfea1 CW |
4052 | ret = -ENOENT; |
4053 | goto unlock; | |
3ef94daa | 4054 | } |
3ef94daa | 4055 | |
05394f39 | 4056 | if (obj->pin_count) { |
1d7cfea1 CW |
4057 | ret = -EINVAL; |
4058 | goto out; | |
3ef94daa CW |
4059 | } |
4060 | ||
05394f39 CW |
4061 | if (obj->madv != __I915_MADV_PURGED) |
4062 | obj->madv = args->madv; | |
3ef94daa | 4063 | |
6c085a72 CW |
4064 | /* if the object is no longer attached, discard its backing storage */ |
4065 | if (i915_gem_object_is_purgeable(obj) && obj->pages == NULL) | |
2d7ef395 CW |
4066 | i915_gem_object_truncate(obj); |
4067 | ||
05394f39 | 4068 | args->retained = obj->madv != __I915_MADV_PURGED; |
bb6baf76 | 4069 | |
1d7cfea1 | 4070 | out: |
05394f39 | 4071 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 4072 | unlock: |
3ef94daa | 4073 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 4074 | return ret; |
3ef94daa CW |
4075 | } |
4076 | ||
37e680a1 CW |
4077 | void i915_gem_object_init(struct drm_i915_gem_object *obj, |
4078 | const struct drm_i915_gem_object_ops *ops) | |
0327d6ba | 4079 | { |
35c20a60 | 4080 | INIT_LIST_HEAD(&obj->global_list); |
0327d6ba | 4081 | INIT_LIST_HEAD(&obj->ring_list); |
b25cb2f8 | 4082 | INIT_LIST_HEAD(&obj->obj_exec_link); |
2f633156 | 4083 | INIT_LIST_HEAD(&obj->vma_list); |
0327d6ba | 4084 | |
37e680a1 CW |
4085 | obj->ops = ops; |
4086 | ||
0327d6ba CW |
4087 | obj->fence_reg = I915_FENCE_REG_NONE; |
4088 | obj->madv = I915_MADV_WILLNEED; | |
4089 | /* Avoid an unnecessary call to unbind on the first bind. */ | |
4090 | obj->map_and_fenceable = true; | |
4091 | ||
4092 | i915_gem_info_add_obj(obj->base.dev->dev_private, obj->base.size); | |
4093 | } | |
4094 | ||
37e680a1 CW |
4095 | static const struct drm_i915_gem_object_ops i915_gem_object_ops = { |
4096 | .get_pages = i915_gem_object_get_pages_gtt, | |
4097 | .put_pages = i915_gem_object_put_pages_gtt, | |
4098 | }; | |
4099 | ||
05394f39 CW |
4100 | struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev, |
4101 | size_t size) | |
ac52bc56 | 4102 | { |
c397b908 | 4103 | struct drm_i915_gem_object *obj; |
5949eac4 | 4104 | struct address_space *mapping; |
1a240d4d | 4105 | gfp_t mask; |
ac52bc56 | 4106 | |
42dcedd4 | 4107 | obj = i915_gem_object_alloc(dev); |
c397b908 DV |
4108 | if (obj == NULL) |
4109 | return NULL; | |
673a394b | 4110 | |
c397b908 | 4111 | if (drm_gem_object_init(dev, &obj->base, size) != 0) { |
42dcedd4 | 4112 | i915_gem_object_free(obj); |
c397b908 DV |
4113 | return NULL; |
4114 | } | |
673a394b | 4115 | |
bed1ea95 CW |
4116 | mask = GFP_HIGHUSER | __GFP_RECLAIMABLE; |
4117 | if (IS_CRESTLINE(dev) || IS_BROADWATER(dev)) { | |
4118 | /* 965gm cannot relocate objects above 4GiB. */ | |
4119 | mask &= ~__GFP_HIGHMEM; | |
4120 | mask |= __GFP_DMA32; | |
4121 | } | |
4122 | ||
496ad9aa | 4123 | mapping = file_inode(obj->base.filp)->i_mapping; |
bed1ea95 | 4124 | mapping_set_gfp_mask(mapping, mask); |
5949eac4 | 4125 | |
37e680a1 | 4126 | i915_gem_object_init(obj, &i915_gem_object_ops); |
73aa808f | 4127 | |
c397b908 DV |
4128 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; |
4129 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; | |
673a394b | 4130 | |
3d29b842 ED |
4131 | if (HAS_LLC(dev)) { |
4132 | /* On some devices, we can have the GPU use the LLC (the CPU | |
a1871112 EA |
4133 | * cache) for about a 10% performance improvement |
4134 | * compared to uncached. Graphics requests other than | |
4135 | * display scanout are coherent with the CPU in | |
4136 | * accessing this cache. This means in this mode we | |
4137 | * don't need to clflush on the CPU side, and on the | |
4138 | * GPU side we only need to flush internal caches to | |
4139 | * get data visible to the CPU. | |
4140 | * | |
4141 | * However, we maintain the display planes as UC, and so | |
4142 | * need to rebind when first used as such. | |
4143 | */ | |
4144 | obj->cache_level = I915_CACHE_LLC; | |
4145 | } else | |
4146 | obj->cache_level = I915_CACHE_NONE; | |
4147 | ||
d861e338 DV |
4148 | trace_i915_gem_object_create(obj); |
4149 | ||
05394f39 | 4150 | return obj; |
c397b908 DV |
4151 | } |
4152 | ||
1488fc08 | 4153 | void i915_gem_free_object(struct drm_gem_object *gem_obj) |
673a394b | 4154 | { |
1488fc08 | 4155 | struct drm_i915_gem_object *obj = to_intel_bo(gem_obj); |
05394f39 | 4156 | struct drm_device *dev = obj->base.dev; |
be72615b | 4157 | drm_i915_private_t *dev_priv = dev->dev_private; |
07fe0b12 | 4158 | struct i915_vma *vma, *next; |
673a394b | 4159 | |
26e12f89 CW |
4160 | trace_i915_gem_object_destroy(obj); |
4161 | ||
1488fc08 CW |
4162 | if (obj->phys_obj) |
4163 | i915_gem_detach_phys_object(dev, obj); | |
4164 | ||
4165 | obj->pin_count = 0; | |
07fe0b12 BW |
4166 | /* NB: 0 or 1 elements */ |
4167 | WARN_ON(!list_empty(&obj->vma_list) && | |
4168 | !list_is_singular(&obj->vma_list)); | |
4169 | list_for_each_entry_safe(vma, next, &obj->vma_list, vma_link) { | |
4170 | int ret = i915_vma_unbind(vma); | |
4171 | if (WARN_ON(ret == -ERESTARTSYS)) { | |
4172 | bool was_interruptible; | |
1488fc08 | 4173 | |
07fe0b12 BW |
4174 | was_interruptible = dev_priv->mm.interruptible; |
4175 | dev_priv->mm.interruptible = false; | |
1488fc08 | 4176 | |
07fe0b12 | 4177 | WARN_ON(i915_vma_unbind(vma)); |
1488fc08 | 4178 | |
07fe0b12 BW |
4179 | dev_priv->mm.interruptible = was_interruptible; |
4180 | } | |
1488fc08 CW |
4181 | } |
4182 | ||
1d64ae71 BW |
4183 | /* Stolen objects don't hold a ref, but do hold pin count. Fix that up |
4184 | * before progressing. */ | |
4185 | if (obj->stolen) | |
4186 | i915_gem_object_unpin_pages(obj); | |
4187 | ||
401c29f6 BW |
4188 | if (WARN_ON(obj->pages_pin_count)) |
4189 | obj->pages_pin_count = 0; | |
37e680a1 | 4190 | i915_gem_object_put_pages(obj); |
d8cb5086 | 4191 | i915_gem_object_free_mmap_offset(obj); |
0104fdbb | 4192 | i915_gem_object_release_stolen(obj); |
de151cf6 | 4193 | |
9da3da66 CW |
4194 | BUG_ON(obj->pages); |
4195 | ||
2f745ad3 CW |
4196 | if (obj->base.import_attach) |
4197 | drm_prime_gem_destroy(&obj->base, NULL); | |
de151cf6 | 4198 | |
05394f39 CW |
4199 | drm_gem_object_release(&obj->base); |
4200 | i915_gem_info_remove_obj(dev_priv, obj->base.size); | |
c397b908 | 4201 | |
05394f39 | 4202 | kfree(obj->bit_17); |
42dcedd4 | 4203 | i915_gem_object_free(obj); |
673a394b EA |
4204 | } |
4205 | ||
e656a6cb | 4206 | struct i915_vma *i915_gem_obj_to_vma(struct drm_i915_gem_object *obj, |
2f633156 | 4207 | struct i915_address_space *vm) |
e656a6cb DV |
4208 | { |
4209 | struct i915_vma *vma; | |
4210 | list_for_each_entry(vma, &obj->vma_list, vma_link) | |
4211 | if (vma->vm == vm) | |
4212 | return vma; | |
4213 | ||
4214 | return NULL; | |
4215 | } | |
4216 | ||
4217 | static struct i915_vma *__i915_gem_vma_create(struct drm_i915_gem_object *obj, | |
4218 | struct i915_address_space *vm) | |
2f633156 BW |
4219 | { |
4220 | struct i915_vma *vma = kzalloc(sizeof(*vma), GFP_KERNEL); | |
4221 | if (vma == NULL) | |
4222 | return ERR_PTR(-ENOMEM); | |
4223 | ||
4224 | INIT_LIST_HEAD(&vma->vma_link); | |
ca191b13 | 4225 | INIT_LIST_HEAD(&vma->mm_list); |
82a55ad1 | 4226 | INIT_LIST_HEAD(&vma->exec_list); |
2f633156 BW |
4227 | vma->vm = vm; |
4228 | vma->obj = obj; | |
4229 | ||
8b9c2b94 BW |
4230 | /* Keep GGTT vmas first to make debug easier */ |
4231 | if (i915_is_ggtt(vm)) | |
4232 | list_add(&vma->vma_link, &obj->vma_list); | |
4233 | else | |
4234 | list_add_tail(&vma->vma_link, &obj->vma_list); | |
4235 | ||
2f633156 BW |
4236 | return vma; |
4237 | } | |
4238 | ||
e656a6cb DV |
4239 | struct i915_vma * |
4240 | i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object *obj, | |
4241 | struct i915_address_space *vm) | |
4242 | { | |
4243 | struct i915_vma *vma; | |
4244 | ||
4245 | vma = i915_gem_obj_to_vma(obj, vm); | |
4246 | if (!vma) | |
4247 | vma = __i915_gem_vma_create(obj, vm); | |
4248 | ||
4249 | return vma; | |
4250 | } | |
4251 | ||
2f633156 BW |
4252 | void i915_gem_vma_destroy(struct i915_vma *vma) |
4253 | { | |
4254 | WARN_ON(vma->node.allocated); | |
aaa05667 CW |
4255 | |
4256 | /* Keep the vma as a placeholder in the execbuffer reservation lists */ | |
4257 | if (!list_empty(&vma->exec_list)) | |
4258 | return; | |
4259 | ||
8b9c2b94 | 4260 | list_del(&vma->vma_link); |
b93dab6e | 4261 | |
2f633156 BW |
4262 | kfree(vma); |
4263 | } | |
4264 | ||
29105ccc CW |
4265 | int |
4266 | i915_gem_idle(struct drm_device *dev) | |
4267 | { | |
4268 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4269 | int ret; | |
28dfe52a | 4270 | |
f7403347 | 4271 | if (dev_priv->ums.mm_suspended) |
29105ccc | 4272 | return 0; |
28dfe52a | 4273 | |
b2da9fe5 | 4274 | ret = i915_gpu_idle(dev); |
f7403347 | 4275 | if (ret) |
673a394b | 4276 | return ret; |
f7403347 | 4277 | |
b2da9fe5 | 4278 | i915_gem_retire_requests(dev); |
673a394b | 4279 | |
29105ccc | 4280 | /* Under UMS, be paranoid and evict. */ |
a39d7efc | 4281 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) |
6c085a72 | 4282 | i915_gem_evict_everything(dev); |
29105ccc | 4283 | |
99584db3 | 4284 | del_timer_sync(&dev_priv->gpu_error.hangcheck_timer); |
29105ccc CW |
4285 | |
4286 | i915_kernel_lost_context(dev); | |
6dbe2772 | 4287 | i915_gem_cleanup_ringbuffer(dev); |
29105ccc | 4288 | |
29105ccc CW |
4289 | /* Cancel the retire work handler, which should be idle now. */ |
4290 | cancel_delayed_work_sync(&dev_priv->mm.retire_work); | |
b29c19b6 | 4291 | cancel_delayed_work_sync(&dev_priv->mm.idle_work); |
29105ccc | 4292 | |
673a394b EA |
4293 | return 0; |
4294 | } | |
4295 | ||
c3787e2e | 4296 | int i915_gem_l3_remap(struct intel_ring_buffer *ring, int slice) |
b9524a1e | 4297 | { |
c3787e2e | 4298 | struct drm_device *dev = ring->dev; |
b9524a1e | 4299 | drm_i915_private_t *dev_priv = dev->dev_private; |
35a85ac6 BW |
4300 | u32 reg_base = GEN7_L3LOG_BASE + (slice * 0x200); |
4301 | u32 *remap_info = dev_priv->l3_parity.remap_info[slice]; | |
c3787e2e | 4302 | int i, ret; |
b9524a1e | 4303 | |
040d2baa | 4304 | if (!HAS_L3_DPF(dev) || !remap_info) |
c3787e2e | 4305 | return 0; |
b9524a1e | 4306 | |
c3787e2e BW |
4307 | ret = intel_ring_begin(ring, GEN7_L3LOG_SIZE / 4 * 3); |
4308 | if (ret) | |
4309 | return ret; | |
b9524a1e | 4310 | |
c3787e2e BW |
4311 | /* |
4312 | * Note: We do not worry about the concurrent register cacheline hang | |
4313 | * here because no other code should access these registers other than | |
4314 | * at initialization time. | |
4315 | */ | |
b9524a1e | 4316 | for (i = 0; i < GEN7_L3LOG_SIZE; i += 4) { |
c3787e2e BW |
4317 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); |
4318 | intel_ring_emit(ring, reg_base + i); | |
4319 | intel_ring_emit(ring, remap_info[i/4]); | |
b9524a1e BW |
4320 | } |
4321 | ||
c3787e2e | 4322 | intel_ring_advance(ring); |
b9524a1e | 4323 | |
c3787e2e | 4324 | return ret; |
b9524a1e BW |
4325 | } |
4326 | ||
f691e2f4 DV |
4327 | void i915_gem_init_swizzling(struct drm_device *dev) |
4328 | { | |
4329 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4330 | ||
11782b02 | 4331 | if (INTEL_INFO(dev)->gen < 5 || |
f691e2f4 DV |
4332 | dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE) |
4333 | return; | |
4334 | ||
4335 | I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) | | |
4336 | DISP_TILE_SURFACE_SWIZZLING); | |
4337 | ||
11782b02 DV |
4338 | if (IS_GEN5(dev)) |
4339 | return; | |
4340 | ||
f691e2f4 DV |
4341 | I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_SWZCTL); |
4342 | if (IS_GEN6(dev)) | |
6b26c86d | 4343 | I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB)); |
8782e26c | 4344 | else if (IS_GEN7(dev)) |
6b26c86d | 4345 | I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB)); |
8782e26c BW |
4346 | else |
4347 | BUG(); | |
f691e2f4 | 4348 | } |
e21af88d | 4349 | |
67b1b571 CW |
4350 | static bool |
4351 | intel_enable_blt(struct drm_device *dev) | |
4352 | { | |
4353 | if (!HAS_BLT(dev)) | |
4354 | return false; | |
4355 | ||
4356 | /* The blitter was dysfunctional on early prototypes */ | |
4357 | if (IS_GEN6(dev) && dev->pdev->revision < 8) { | |
4358 | DRM_INFO("BLT not supported on this pre-production hardware;" | |
4359 | " graphics performance will be degraded.\n"); | |
4360 | return false; | |
4361 | } | |
4362 | ||
4363 | return true; | |
4364 | } | |
4365 | ||
4fc7c971 | 4366 | static int i915_gem_init_rings(struct drm_device *dev) |
8187a2b7 | 4367 | { |
4fc7c971 | 4368 | struct drm_i915_private *dev_priv = dev->dev_private; |
8187a2b7 | 4369 | int ret; |
68f95ba9 | 4370 | |
5c1143bb | 4371 | ret = intel_init_render_ring_buffer(dev); |
68f95ba9 | 4372 | if (ret) |
b6913e4b | 4373 | return ret; |
68f95ba9 CW |
4374 | |
4375 | if (HAS_BSD(dev)) { | |
5c1143bb | 4376 | ret = intel_init_bsd_ring_buffer(dev); |
68f95ba9 CW |
4377 | if (ret) |
4378 | goto cleanup_render_ring; | |
d1b851fc | 4379 | } |
68f95ba9 | 4380 | |
67b1b571 | 4381 | if (intel_enable_blt(dev)) { |
549f7365 CW |
4382 | ret = intel_init_blt_ring_buffer(dev); |
4383 | if (ret) | |
4384 | goto cleanup_bsd_ring; | |
4385 | } | |
4386 | ||
9a8a2213 BW |
4387 | if (HAS_VEBOX(dev)) { |
4388 | ret = intel_init_vebox_ring_buffer(dev); | |
4389 | if (ret) | |
4390 | goto cleanup_blt_ring; | |
4391 | } | |
4392 | ||
4393 | ||
99433931 | 4394 | ret = i915_gem_set_seqno(dev, ((u32)~0 - 0x1000)); |
4fc7c971 | 4395 | if (ret) |
9a8a2213 | 4396 | goto cleanup_vebox_ring; |
4fc7c971 BW |
4397 | |
4398 | return 0; | |
4399 | ||
9a8a2213 BW |
4400 | cleanup_vebox_ring: |
4401 | intel_cleanup_ring_buffer(&dev_priv->ring[VECS]); | |
4fc7c971 BW |
4402 | cleanup_blt_ring: |
4403 | intel_cleanup_ring_buffer(&dev_priv->ring[BCS]); | |
4404 | cleanup_bsd_ring: | |
4405 | intel_cleanup_ring_buffer(&dev_priv->ring[VCS]); | |
4406 | cleanup_render_ring: | |
4407 | intel_cleanup_ring_buffer(&dev_priv->ring[RCS]); | |
4408 | ||
4409 | return ret; | |
4410 | } | |
4411 | ||
4412 | int | |
4413 | i915_gem_init_hw(struct drm_device *dev) | |
4414 | { | |
4415 | drm_i915_private_t *dev_priv = dev->dev_private; | |
35a85ac6 | 4416 | int ret, i; |
4fc7c971 BW |
4417 | |
4418 | if (INTEL_INFO(dev)->gen < 6 && !intel_enable_gtt()) | |
4419 | return -EIO; | |
4420 | ||
59124506 | 4421 | if (dev_priv->ellc_size) |
05e21cc4 | 4422 | I915_WRITE(HSW_IDICR, I915_READ(HSW_IDICR) | IDIHASHMSK(0xf)); |
4fc7c971 | 4423 | |
9435373e RV |
4424 | if (IS_HSW_GT3(dev)) |
4425 | I915_WRITE(MI_PREDICATE_RESULT_2, LOWER_SLICE_ENABLED); | |
4426 | else | |
4427 | I915_WRITE(MI_PREDICATE_RESULT_2, LOWER_SLICE_DISABLED); | |
4428 | ||
88a2b2a3 BW |
4429 | if (HAS_PCH_NOP(dev)) { |
4430 | u32 temp = I915_READ(GEN7_MSG_CTL); | |
4431 | temp &= ~(WAIT_FOR_PCH_FLR_ACK | WAIT_FOR_PCH_RESET_ACK); | |
4432 | I915_WRITE(GEN7_MSG_CTL, temp); | |
4433 | } | |
4434 | ||
4fc7c971 BW |
4435 | i915_gem_init_swizzling(dev); |
4436 | ||
4437 | ret = i915_gem_init_rings(dev); | |
99433931 MK |
4438 | if (ret) |
4439 | return ret; | |
4440 | ||
c3787e2e BW |
4441 | for (i = 0; i < NUM_L3_SLICES(dev); i++) |
4442 | i915_gem_l3_remap(&dev_priv->ring[RCS], i); | |
4443 | ||
254f965c BW |
4444 | /* |
4445 | * XXX: There was some w/a described somewhere suggesting loading | |
4446 | * contexts before PPGTT. | |
4447 | */ | |
4448 | i915_gem_context_init(dev); | |
b7c36d25 BW |
4449 | if (dev_priv->mm.aliasing_ppgtt) { |
4450 | ret = dev_priv->mm.aliasing_ppgtt->enable(dev); | |
4451 | if (ret) { | |
4452 | i915_gem_cleanup_aliasing_ppgtt(dev); | |
4453 | DRM_INFO("PPGTT enable failed. This is not fatal, but unexpected\n"); | |
4454 | } | |
4455 | } | |
e21af88d | 4456 | |
68f95ba9 | 4457 | return 0; |
8187a2b7 ZN |
4458 | } |
4459 | ||
1070a42b CW |
4460 | int i915_gem_init(struct drm_device *dev) |
4461 | { | |
4462 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1070a42b CW |
4463 | int ret; |
4464 | ||
1070a42b | 4465 | mutex_lock(&dev->struct_mutex); |
d62b4892 JB |
4466 | |
4467 | if (IS_VALLEYVIEW(dev)) { | |
4468 | /* VLVA0 (potential hack), BIOS isn't actually waking us */ | |
4469 | I915_WRITE(VLV_GTLC_WAKE_CTRL, 1); | |
4470 | if (wait_for((I915_READ(VLV_GTLC_PW_STATUS) & 1) == 1, 10)) | |
4471 | DRM_DEBUG_DRIVER("allow wake ack timed out\n"); | |
4472 | } | |
4473 | ||
d7e5008f | 4474 | i915_gem_init_global_gtt(dev); |
d62b4892 | 4475 | |
1070a42b CW |
4476 | ret = i915_gem_init_hw(dev); |
4477 | mutex_unlock(&dev->struct_mutex); | |
4478 | if (ret) { | |
4479 | i915_gem_cleanup_aliasing_ppgtt(dev); | |
4480 | return ret; | |
4481 | } | |
4482 | ||
53ca26ca DV |
4483 | /* Allow hardware batchbuffers unless told otherwise, but not for KMS. */ |
4484 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) | |
4485 | dev_priv->dri1.allow_batchbuffer = 1; | |
1070a42b CW |
4486 | return 0; |
4487 | } | |
4488 | ||
8187a2b7 ZN |
4489 | void |
4490 | i915_gem_cleanup_ringbuffer(struct drm_device *dev) | |
4491 | { | |
4492 | drm_i915_private_t *dev_priv = dev->dev_private; | |
b4519513 | 4493 | struct intel_ring_buffer *ring; |
1ec14ad3 | 4494 | int i; |
8187a2b7 | 4495 | |
b4519513 CW |
4496 | for_each_ring(ring, dev_priv, i) |
4497 | intel_cleanup_ring_buffer(ring); | |
8187a2b7 ZN |
4498 | } |
4499 | ||
673a394b EA |
4500 | int |
4501 | i915_gem_entervt_ioctl(struct drm_device *dev, void *data, | |
4502 | struct drm_file *file_priv) | |
4503 | { | |
db1b76ca | 4504 | struct drm_i915_private *dev_priv = dev->dev_private; |
b4519513 | 4505 | int ret; |
673a394b | 4506 | |
79e53945 JB |
4507 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
4508 | return 0; | |
4509 | ||
1f83fee0 | 4510 | if (i915_reset_in_progress(&dev_priv->gpu_error)) { |
673a394b | 4511 | DRM_ERROR("Reenabling wedged hardware, good luck\n"); |
1f83fee0 | 4512 | atomic_set(&dev_priv->gpu_error.reset_counter, 0); |
673a394b EA |
4513 | } |
4514 | ||
673a394b | 4515 | mutex_lock(&dev->struct_mutex); |
db1b76ca | 4516 | dev_priv->ums.mm_suspended = 0; |
9bb2d6f9 | 4517 | |
f691e2f4 | 4518 | ret = i915_gem_init_hw(dev); |
d816f6ac WF |
4519 | if (ret != 0) { |
4520 | mutex_unlock(&dev->struct_mutex); | |
9bb2d6f9 | 4521 | return ret; |
d816f6ac | 4522 | } |
9bb2d6f9 | 4523 | |
5cef07e1 | 4524 | BUG_ON(!list_empty(&dev_priv->gtt.base.active_list)); |
673a394b | 4525 | mutex_unlock(&dev->struct_mutex); |
dbb19d30 | 4526 | |
5f35308b CW |
4527 | ret = drm_irq_install(dev); |
4528 | if (ret) | |
4529 | goto cleanup_ringbuffer; | |
dbb19d30 | 4530 | |
673a394b | 4531 | return 0; |
5f35308b CW |
4532 | |
4533 | cleanup_ringbuffer: | |
4534 | mutex_lock(&dev->struct_mutex); | |
4535 | i915_gem_cleanup_ringbuffer(dev); | |
db1b76ca | 4536 | dev_priv->ums.mm_suspended = 1; |
5f35308b CW |
4537 | mutex_unlock(&dev->struct_mutex); |
4538 | ||
4539 | return ret; | |
673a394b EA |
4540 | } |
4541 | ||
4542 | int | |
4543 | i915_gem_leavevt_ioctl(struct drm_device *dev, void *data, | |
4544 | struct drm_file *file_priv) | |
4545 | { | |
db1b76ca DV |
4546 | struct drm_i915_private *dev_priv = dev->dev_private; |
4547 | int ret; | |
4548 | ||
79e53945 JB |
4549 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
4550 | return 0; | |
4551 | ||
dbb19d30 | 4552 | drm_irq_uninstall(dev); |
db1b76ca DV |
4553 | |
4554 | mutex_lock(&dev->struct_mutex); | |
4555 | ret = i915_gem_idle(dev); | |
4556 | ||
4557 | /* Hack! Don't let anybody do execbuf while we don't control the chip. | |
4558 | * We need to replace this with a semaphore, or something. | |
4559 | * And not confound ums.mm_suspended! | |
4560 | */ | |
4561 | if (ret != 0) | |
4562 | dev_priv->ums.mm_suspended = 1; | |
4563 | mutex_unlock(&dev->struct_mutex); | |
4564 | ||
4565 | return ret; | |
673a394b EA |
4566 | } |
4567 | ||
4568 | void | |
4569 | i915_gem_lastclose(struct drm_device *dev) | |
4570 | { | |
4571 | int ret; | |
673a394b | 4572 | |
e806b495 EA |
4573 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
4574 | return; | |
4575 | ||
db1b76ca | 4576 | mutex_lock(&dev->struct_mutex); |
6dbe2772 KP |
4577 | ret = i915_gem_idle(dev); |
4578 | if (ret) | |
4579 | DRM_ERROR("failed to idle hardware: %d\n", ret); | |
db1b76ca | 4580 | mutex_unlock(&dev->struct_mutex); |
673a394b EA |
4581 | } |
4582 | ||
64193406 CW |
4583 | static void |
4584 | init_ring_lists(struct intel_ring_buffer *ring) | |
4585 | { | |
4586 | INIT_LIST_HEAD(&ring->active_list); | |
4587 | INIT_LIST_HEAD(&ring->request_list); | |
64193406 CW |
4588 | } |
4589 | ||
fc8c067e BW |
4590 | static void i915_init_vm(struct drm_i915_private *dev_priv, |
4591 | struct i915_address_space *vm) | |
4592 | { | |
4593 | vm->dev = dev_priv->dev; | |
4594 | INIT_LIST_HEAD(&vm->active_list); | |
4595 | INIT_LIST_HEAD(&vm->inactive_list); | |
4596 | INIT_LIST_HEAD(&vm->global_link); | |
4597 | list_add(&vm->global_link, &dev_priv->vm_list); | |
4598 | } | |
4599 | ||
673a394b EA |
4600 | void |
4601 | i915_gem_load(struct drm_device *dev) | |
4602 | { | |
4603 | drm_i915_private_t *dev_priv = dev->dev_private; | |
42dcedd4 CW |
4604 | int i; |
4605 | ||
4606 | dev_priv->slab = | |
4607 | kmem_cache_create("i915_gem_object", | |
4608 | sizeof(struct drm_i915_gem_object), 0, | |
4609 | SLAB_HWCACHE_ALIGN, | |
4610 | NULL); | |
673a394b | 4611 | |
fc8c067e BW |
4612 | INIT_LIST_HEAD(&dev_priv->vm_list); |
4613 | i915_init_vm(dev_priv, &dev_priv->gtt.base); | |
4614 | ||
a33afea5 | 4615 | INIT_LIST_HEAD(&dev_priv->context_list); |
6c085a72 CW |
4616 | INIT_LIST_HEAD(&dev_priv->mm.unbound_list); |
4617 | INIT_LIST_HEAD(&dev_priv->mm.bound_list); | |
a09ba7fa | 4618 | INIT_LIST_HEAD(&dev_priv->mm.fence_list); |
1ec14ad3 CW |
4619 | for (i = 0; i < I915_NUM_RINGS; i++) |
4620 | init_ring_lists(&dev_priv->ring[i]); | |
4b9de737 | 4621 | for (i = 0; i < I915_MAX_NUM_FENCES; i++) |
007cc8ac | 4622 | INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list); |
673a394b EA |
4623 | INIT_DELAYED_WORK(&dev_priv->mm.retire_work, |
4624 | i915_gem_retire_work_handler); | |
b29c19b6 CW |
4625 | INIT_DELAYED_WORK(&dev_priv->mm.idle_work, |
4626 | i915_gem_idle_work_handler); | |
1f83fee0 | 4627 | init_waitqueue_head(&dev_priv->gpu_error.reset_queue); |
31169714 | 4628 | |
94400120 DA |
4629 | /* On GEN3 we really need to make sure the ARB C3 LP bit is set */ |
4630 | if (IS_GEN3(dev)) { | |
50743298 DV |
4631 | I915_WRITE(MI_ARB_STATE, |
4632 | _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE)); | |
94400120 DA |
4633 | } |
4634 | ||
72bfa19c CW |
4635 | dev_priv->relative_constants_mode = I915_EXEC_CONSTANTS_REL_GENERAL; |
4636 | ||
de151cf6 | 4637 | /* Old X drivers will take 0-2 for front, back, depth buffers */ |
b397c836 EA |
4638 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) |
4639 | dev_priv->fence_reg_start = 3; | |
de151cf6 | 4640 | |
42b5aeab VS |
4641 | if (INTEL_INFO(dev)->gen >= 7 && !IS_VALLEYVIEW(dev)) |
4642 | dev_priv->num_fence_regs = 32; | |
4643 | else if (INTEL_INFO(dev)->gen >= 4 || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) | |
de151cf6 JB |
4644 | dev_priv->num_fence_regs = 16; |
4645 | else | |
4646 | dev_priv->num_fence_regs = 8; | |
4647 | ||
b5aa8a0f | 4648 | /* Initialize fence registers to zero */ |
19b2dbde CW |
4649 | INIT_LIST_HEAD(&dev_priv->mm.fence_list); |
4650 | i915_gem_restore_fences(dev); | |
10ed13e4 | 4651 | |
673a394b | 4652 | i915_gem_detect_bit_6_swizzle(dev); |
6b95a207 | 4653 | init_waitqueue_head(&dev_priv->pending_flip_queue); |
17250b71 | 4654 | |
ce453d81 CW |
4655 | dev_priv->mm.interruptible = true; |
4656 | ||
7dc19d5a DC |
4657 | dev_priv->mm.inactive_shrinker.scan_objects = i915_gem_inactive_scan; |
4658 | dev_priv->mm.inactive_shrinker.count_objects = i915_gem_inactive_count; | |
17250b71 CW |
4659 | dev_priv->mm.inactive_shrinker.seeks = DEFAULT_SEEKS; |
4660 | register_shrinker(&dev_priv->mm.inactive_shrinker); | |
673a394b | 4661 | } |
71acb5eb DA |
4662 | |
4663 | /* | |
4664 | * Create a physically contiguous memory object for this object | |
4665 | * e.g. for cursor + overlay regs | |
4666 | */ | |
995b6762 CW |
4667 | static int i915_gem_init_phys_object(struct drm_device *dev, |
4668 | int id, int size, int align) | |
71acb5eb DA |
4669 | { |
4670 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4671 | struct drm_i915_gem_phys_object *phys_obj; | |
4672 | int ret; | |
4673 | ||
4674 | if (dev_priv->mm.phys_objs[id - 1] || !size) | |
4675 | return 0; | |
4676 | ||
b14c5679 | 4677 | phys_obj = kzalloc(sizeof(*phys_obj), GFP_KERNEL); |
71acb5eb DA |
4678 | if (!phys_obj) |
4679 | return -ENOMEM; | |
4680 | ||
4681 | phys_obj->id = id; | |
4682 | ||
6eeefaf3 | 4683 | phys_obj->handle = drm_pci_alloc(dev, size, align); |
71acb5eb DA |
4684 | if (!phys_obj->handle) { |
4685 | ret = -ENOMEM; | |
4686 | goto kfree_obj; | |
4687 | } | |
4688 | #ifdef CONFIG_X86 | |
4689 | set_memory_wc((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE); | |
4690 | #endif | |
4691 | ||
4692 | dev_priv->mm.phys_objs[id - 1] = phys_obj; | |
4693 | ||
4694 | return 0; | |
4695 | kfree_obj: | |
9a298b2a | 4696 | kfree(phys_obj); |
71acb5eb DA |
4697 | return ret; |
4698 | } | |
4699 | ||
995b6762 | 4700 | static void i915_gem_free_phys_object(struct drm_device *dev, int id) |
71acb5eb DA |
4701 | { |
4702 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4703 | struct drm_i915_gem_phys_object *phys_obj; | |
4704 | ||
4705 | if (!dev_priv->mm.phys_objs[id - 1]) | |
4706 | return; | |
4707 | ||
4708 | phys_obj = dev_priv->mm.phys_objs[id - 1]; | |
4709 | if (phys_obj->cur_obj) { | |
4710 | i915_gem_detach_phys_object(dev, phys_obj->cur_obj); | |
4711 | } | |
4712 | ||
4713 | #ifdef CONFIG_X86 | |
4714 | set_memory_wb((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE); | |
4715 | #endif | |
4716 | drm_pci_free(dev, phys_obj->handle); | |
4717 | kfree(phys_obj); | |
4718 | dev_priv->mm.phys_objs[id - 1] = NULL; | |
4719 | } | |
4720 | ||
4721 | void i915_gem_free_all_phys_object(struct drm_device *dev) | |
4722 | { | |
4723 | int i; | |
4724 | ||
260883c8 | 4725 | for (i = I915_GEM_PHYS_CURSOR_0; i <= I915_MAX_PHYS_OBJECT; i++) |
71acb5eb DA |
4726 | i915_gem_free_phys_object(dev, i); |
4727 | } | |
4728 | ||
4729 | void i915_gem_detach_phys_object(struct drm_device *dev, | |
05394f39 | 4730 | struct drm_i915_gem_object *obj) |
71acb5eb | 4731 | { |
496ad9aa | 4732 | struct address_space *mapping = file_inode(obj->base.filp)->i_mapping; |
e5281ccd | 4733 | char *vaddr; |
71acb5eb | 4734 | int i; |
71acb5eb DA |
4735 | int page_count; |
4736 | ||
05394f39 | 4737 | if (!obj->phys_obj) |
71acb5eb | 4738 | return; |
05394f39 | 4739 | vaddr = obj->phys_obj->handle->vaddr; |
71acb5eb | 4740 | |
05394f39 | 4741 | page_count = obj->base.size / PAGE_SIZE; |
71acb5eb | 4742 | for (i = 0; i < page_count; i++) { |
5949eac4 | 4743 | struct page *page = shmem_read_mapping_page(mapping, i); |
e5281ccd CW |
4744 | if (!IS_ERR(page)) { |
4745 | char *dst = kmap_atomic(page); | |
4746 | memcpy(dst, vaddr + i*PAGE_SIZE, PAGE_SIZE); | |
4747 | kunmap_atomic(dst); | |
4748 | ||
4749 | drm_clflush_pages(&page, 1); | |
4750 | ||
4751 | set_page_dirty(page); | |
4752 | mark_page_accessed(page); | |
4753 | page_cache_release(page); | |
4754 | } | |
71acb5eb | 4755 | } |
e76e9aeb | 4756 | i915_gem_chipset_flush(dev); |
d78b47b9 | 4757 | |
05394f39 CW |
4758 | obj->phys_obj->cur_obj = NULL; |
4759 | obj->phys_obj = NULL; | |
71acb5eb DA |
4760 | } |
4761 | ||
4762 | int | |
4763 | i915_gem_attach_phys_object(struct drm_device *dev, | |
05394f39 | 4764 | struct drm_i915_gem_object *obj, |
6eeefaf3 CW |
4765 | int id, |
4766 | int align) | |
71acb5eb | 4767 | { |
496ad9aa | 4768 | struct address_space *mapping = file_inode(obj->base.filp)->i_mapping; |
71acb5eb | 4769 | drm_i915_private_t *dev_priv = dev->dev_private; |
71acb5eb DA |
4770 | int ret = 0; |
4771 | int page_count; | |
4772 | int i; | |
4773 | ||
4774 | if (id > I915_MAX_PHYS_OBJECT) | |
4775 | return -EINVAL; | |
4776 | ||
05394f39 CW |
4777 | if (obj->phys_obj) { |
4778 | if (obj->phys_obj->id == id) | |
71acb5eb DA |
4779 | return 0; |
4780 | i915_gem_detach_phys_object(dev, obj); | |
4781 | } | |
4782 | ||
71acb5eb DA |
4783 | /* create a new object */ |
4784 | if (!dev_priv->mm.phys_objs[id - 1]) { | |
4785 | ret = i915_gem_init_phys_object(dev, id, | |
05394f39 | 4786 | obj->base.size, align); |
71acb5eb | 4787 | if (ret) { |
05394f39 CW |
4788 | DRM_ERROR("failed to init phys object %d size: %zu\n", |
4789 | id, obj->base.size); | |
e5281ccd | 4790 | return ret; |
71acb5eb DA |
4791 | } |
4792 | } | |
4793 | ||
4794 | /* bind to the object */ | |
05394f39 CW |
4795 | obj->phys_obj = dev_priv->mm.phys_objs[id - 1]; |
4796 | obj->phys_obj->cur_obj = obj; | |
71acb5eb | 4797 | |
05394f39 | 4798 | page_count = obj->base.size / PAGE_SIZE; |
71acb5eb DA |
4799 | |
4800 | for (i = 0; i < page_count; i++) { | |
e5281ccd CW |
4801 | struct page *page; |
4802 | char *dst, *src; | |
4803 | ||
5949eac4 | 4804 | page = shmem_read_mapping_page(mapping, i); |
e5281ccd CW |
4805 | if (IS_ERR(page)) |
4806 | return PTR_ERR(page); | |
71acb5eb | 4807 | |
ff75b9bc | 4808 | src = kmap_atomic(page); |
05394f39 | 4809 | dst = obj->phys_obj->handle->vaddr + (i * PAGE_SIZE); |
71acb5eb | 4810 | memcpy(dst, src, PAGE_SIZE); |
3e4d3af5 | 4811 | kunmap_atomic(src); |
71acb5eb | 4812 | |
e5281ccd CW |
4813 | mark_page_accessed(page); |
4814 | page_cache_release(page); | |
4815 | } | |
d78b47b9 | 4816 | |
71acb5eb | 4817 | return 0; |
71acb5eb DA |
4818 | } |
4819 | ||
4820 | static int | |
05394f39 CW |
4821 | i915_gem_phys_pwrite(struct drm_device *dev, |
4822 | struct drm_i915_gem_object *obj, | |
71acb5eb DA |
4823 | struct drm_i915_gem_pwrite *args, |
4824 | struct drm_file *file_priv) | |
4825 | { | |
05394f39 | 4826 | void *vaddr = obj->phys_obj->handle->vaddr + args->offset; |
2bb4629a | 4827 | char __user *user_data = to_user_ptr(args->data_ptr); |
71acb5eb | 4828 | |
b47b30cc CW |
4829 | if (__copy_from_user_inatomic_nocache(vaddr, user_data, args->size)) { |
4830 | unsigned long unwritten; | |
4831 | ||
4832 | /* The physical object once assigned is fixed for the lifetime | |
4833 | * of the obj, so we can safely drop the lock and continue | |
4834 | * to access vaddr. | |
4835 | */ | |
4836 | mutex_unlock(&dev->struct_mutex); | |
4837 | unwritten = copy_from_user(vaddr, user_data, args->size); | |
4838 | mutex_lock(&dev->struct_mutex); | |
4839 | if (unwritten) | |
4840 | return -EFAULT; | |
4841 | } | |
71acb5eb | 4842 | |
e76e9aeb | 4843 | i915_gem_chipset_flush(dev); |
71acb5eb DA |
4844 | return 0; |
4845 | } | |
b962442e | 4846 | |
f787a5f5 | 4847 | void i915_gem_release(struct drm_device *dev, struct drm_file *file) |
b962442e | 4848 | { |
f787a5f5 | 4849 | struct drm_i915_file_private *file_priv = file->driver_priv; |
b962442e | 4850 | |
b29c19b6 CW |
4851 | cancel_delayed_work_sync(&file_priv->mm.idle_work); |
4852 | ||
b962442e EA |
4853 | /* Clean up our request list when the client is going away, so that |
4854 | * later retire_requests won't dereference our soon-to-be-gone | |
4855 | * file_priv. | |
4856 | */ | |
1c25595f | 4857 | spin_lock(&file_priv->mm.lock); |
f787a5f5 CW |
4858 | while (!list_empty(&file_priv->mm.request_list)) { |
4859 | struct drm_i915_gem_request *request; | |
4860 | ||
4861 | request = list_first_entry(&file_priv->mm.request_list, | |
4862 | struct drm_i915_gem_request, | |
4863 | client_list); | |
4864 | list_del(&request->client_list); | |
4865 | request->file_priv = NULL; | |
4866 | } | |
1c25595f | 4867 | spin_unlock(&file_priv->mm.lock); |
b962442e | 4868 | } |
31169714 | 4869 | |
b29c19b6 CW |
4870 | static void |
4871 | i915_gem_file_idle_work_handler(struct work_struct *work) | |
4872 | { | |
4873 | struct drm_i915_file_private *file_priv = | |
4874 | container_of(work, typeof(*file_priv), mm.idle_work.work); | |
4875 | ||
4876 | atomic_set(&file_priv->rps_wait_boost, false); | |
4877 | } | |
4878 | ||
4879 | int i915_gem_open(struct drm_device *dev, struct drm_file *file) | |
4880 | { | |
4881 | struct drm_i915_file_private *file_priv; | |
4882 | ||
4883 | DRM_DEBUG_DRIVER("\n"); | |
4884 | ||
4885 | file_priv = kzalloc(sizeof(*file_priv), GFP_KERNEL); | |
4886 | if (!file_priv) | |
4887 | return -ENOMEM; | |
4888 | ||
4889 | file->driver_priv = file_priv; | |
4890 | file_priv->dev_priv = dev->dev_private; | |
4891 | ||
4892 | spin_lock_init(&file_priv->mm.lock); | |
4893 | INIT_LIST_HEAD(&file_priv->mm.request_list); | |
4894 | INIT_DELAYED_WORK(&file_priv->mm.idle_work, | |
4895 | i915_gem_file_idle_work_handler); | |
4896 | ||
4897 | idr_init(&file_priv->context_idr); | |
4898 | ||
4899 | return 0; | |
4900 | } | |
4901 | ||
5774506f CW |
4902 | static bool mutex_is_locked_by(struct mutex *mutex, struct task_struct *task) |
4903 | { | |
4904 | if (!mutex_is_locked(mutex)) | |
4905 | return false; | |
4906 | ||
4907 | #if defined(CONFIG_SMP) || defined(CONFIG_DEBUG_MUTEXES) | |
4908 | return mutex->owner == task; | |
4909 | #else | |
4910 | /* Since UP may be pre-empted, we cannot assume that we own the lock */ | |
4911 | return false; | |
4912 | #endif | |
4913 | } | |
4914 | ||
7dc19d5a DC |
4915 | static unsigned long |
4916 | i915_gem_inactive_count(struct shrinker *shrinker, struct shrink_control *sc) | |
31169714 | 4917 | { |
17250b71 CW |
4918 | struct drm_i915_private *dev_priv = |
4919 | container_of(shrinker, | |
4920 | struct drm_i915_private, | |
4921 | mm.inactive_shrinker); | |
4922 | struct drm_device *dev = dev_priv->dev; | |
6c085a72 | 4923 | struct drm_i915_gem_object *obj; |
5774506f | 4924 | bool unlock = true; |
7dc19d5a | 4925 | unsigned long count; |
17250b71 | 4926 | |
5774506f CW |
4927 | if (!mutex_trylock(&dev->struct_mutex)) { |
4928 | if (!mutex_is_locked_by(&dev->struct_mutex, current)) | |
d3227046 | 4929 | return 0; |
5774506f | 4930 | |
677feac2 | 4931 | if (dev_priv->mm.shrinker_no_lock_stealing) |
d3227046 | 4932 | return 0; |
677feac2 | 4933 | |
5774506f CW |
4934 | unlock = false; |
4935 | } | |
31169714 | 4936 | |
7dc19d5a | 4937 | count = 0; |
35c20a60 | 4938 | list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) |
a5570178 | 4939 | if (obj->pages_pin_count == 0) |
7dc19d5a | 4940 | count += obj->base.size >> PAGE_SHIFT; |
fcb4a578 BW |
4941 | |
4942 | list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) { | |
4943 | if (obj->active) | |
4944 | continue; | |
4945 | ||
a5570178 | 4946 | if (obj->pin_count == 0 && obj->pages_pin_count == 0) |
7dc19d5a | 4947 | count += obj->base.size >> PAGE_SHIFT; |
fcb4a578 | 4948 | } |
17250b71 | 4949 | |
5774506f CW |
4950 | if (unlock) |
4951 | mutex_unlock(&dev->struct_mutex); | |
d9973b43 | 4952 | |
7dc19d5a | 4953 | return count; |
31169714 | 4954 | } |
a70a3148 BW |
4955 | |
4956 | /* All the new VM stuff */ | |
4957 | unsigned long i915_gem_obj_offset(struct drm_i915_gem_object *o, | |
4958 | struct i915_address_space *vm) | |
4959 | { | |
4960 | struct drm_i915_private *dev_priv = o->base.dev->dev_private; | |
4961 | struct i915_vma *vma; | |
4962 | ||
4963 | if (vm == &dev_priv->mm.aliasing_ppgtt->base) | |
4964 | vm = &dev_priv->gtt.base; | |
4965 | ||
4966 | BUG_ON(list_empty(&o->vma_list)); | |
4967 | list_for_each_entry(vma, &o->vma_list, vma_link) { | |
4968 | if (vma->vm == vm) | |
4969 | return vma->node.start; | |
4970 | ||
4971 | } | |
4972 | return -1; | |
4973 | } | |
4974 | ||
4975 | bool i915_gem_obj_bound(struct drm_i915_gem_object *o, | |
4976 | struct i915_address_space *vm) | |
4977 | { | |
4978 | struct i915_vma *vma; | |
4979 | ||
4980 | list_for_each_entry(vma, &o->vma_list, vma_link) | |
8b9c2b94 | 4981 | if (vma->vm == vm && drm_mm_node_allocated(&vma->node)) |
a70a3148 BW |
4982 | return true; |
4983 | ||
4984 | return false; | |
4985 | } | |
4986 | ||
4987 | bool i915_gem_obj_bound_any(struct drm_i915_gem_object *o) | |
4988 | { | |
5a1d5eb0 | 4989 | struct i915_vma *vma; |
a70a3148 | 4990 | |
5a1d5eb0 CW |
4991 | list_for_each_entry(vma, &o->vma_list, vma_link) |
4992 | if (drm_mm_node_allocated(&vma->node)) | |
a70a3148 BW |
4993 | return true; |
4994 | ||
4995 | return false; | |
4996 | } | |
4997 | ||
4998 | unsigned long i915_gem_obj_size(struct drm_i915_gem_object *o, | |
4999 | struct i915_address_space *vm) | |
5000 | { | |
5001 | struct drm_i915_private *dev_priv = o->base.dev->dev_private; | |
5002 | struct i915_vma *vma; | |
5003 | ||
5004 | if (vm == &dev_priv->mm.aliasing_ppgtt->base) | |
5005 | vm = &dev_priv->gtt.base; | |
5006 | ||
5007 | BUG_ON(list_empty(&o->vma_list)); | |
5008 | ||
5009 | list_for_each_entry(vma, &o->vma_list, vma_link) | |
5010 | if (vma->vm == vm) | |
5011 | return vma->node.size; | |
5012 | ||
5013 | return 0; | |
5014 | } | |
5015 | ||
7dc19d5a DC |
5016 | static unsigned long |
5017 | i915_gem_inactive_scan(struct shrinker *shrinker, struct shrink_control *sc) | |
5018 | { | |
5019 | struct drm_i915_private *dev_priv = | |
5020 | container_of(shrinker, | |
5021 | struct drm_i915_private, | |
5022 | mm.inactive_shrinker); | |
5023 | struct drm_device *dev = dev_priv->dev; | |
7dc19d5a DC |
5024 | unsigned long freed; |
5025 | bool unlock = true; | |
5026 | ||
5027 | if (!mutex_trylock(&dev->struct_mutex)) { | |
5028 | if (!mutex_is_locked_by(&dev->struct_mutex, current)) | |
d3227046 | 5029 | return SHRINK_STOP; |
7dc19d5a DC |
5030 | |
5031 | if (dev_priv->mm.shrinker_no_lock_stealing) | |
d3227046 | 5032 | return SHRINK_STOP; |
7dc19d5a DC |
5033 | |
5034 | unlock = false; | |
5035 | } | |
5036 | ||
d9973b43 CW |
5037 | freed = i915_gem_purge(dev_priv, sc->nr_to_scan); |
5038 | if (freed < sc->nr_to_scan) | |
5039 | freed += __i915_gem_shrink(dev_priv, | |
5040 | sc->nr_to_scan - freed, | |
5041 | false); | |
5042 | if (freed < sc->nr_to_scan) | |
7dc19d5a DC |
5043 | freed += i915_gem_shrink_all(dev_priv); |
5044 | ||
5045 | if (unlock) | |
5046 | mutex_unlock(&dev->struct_mutex); | |
d9973b43 | 5047 | |
7dc19d5a DC |
5048 | return freed; |
5049 | } | |
5c2abbea BW |
5050 | |
5051 | struct i915_vma *i915_gem_obj_to_ggtt(struct drm_i915_gem_object *obj) | |
5052 | { | |
5053 | struct i915_vma *vma; | |
5054 | ||
5055 | if (WARN_ON(list_empty(&obj->vma_list))) | |
5056 | return NULL; | |
5057 | ||
5058 | vma = list_first_entry(&obj->vma_list, typeof(*vma), vma_link); | |
5059 | if (WARN_ON(vma->vm != obj_to_ggtt(obj))) | |
5060 | return NULL; | |
5061 | ||
5062 | return vma; | |
5063 | } |