]>
Commit | Line | Data |
---|---|---|
673a394b EA |
1 | /* |
2 | * Copyright © 2008 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | * | |
26 | */ | |
27 | ||
28 | #include "drmP.h" | |
29 | #include "drm.h" | |
30 | #include "i915_drm.h" | |
31 | #include "i915_drv.h" | |
1c5d22f7 | 32 | #include "i915_trace.h" |
652c393a | 33 | #include "intel_drv.h" |
5a0e3ad6 | 34 | #include <linux/slab.h> |
673a394b | 35 | #include <linux/swap.h> |
79e53945 | 36 | #include <linux/pci.h> |
673a394b | 37 | |
0f8c6d7c CW |
38 | struct change_domains { |
39 | uint32_t invalidate_domains; | |
40 | uint32_t flush_domains; | |
41 | uint32_t flush_rings; | |
42 | }; | |
43 | ||
a00b10c3 CW |
44 | static uint32_t i915_gem_get_gtt_alignment(struct drm_i915_gem_object *obj_priv); |
45 | static uint32_t i915_gem_get_gtt_size(struct drm_i915_gem_object *obj_priv); | |
ba3d8d74 DV |
46 | |
47 | static int i915_gem_object_flush_gpu_write_domain(struct drm_gem_object *obj, | |
48 | bool pipelined); | |
e47c68e9 EA |
49 | static void i915_gem_object_flush_gtt_write_domain(struct drm_gem_object *obj); |
50 | static void i915_gem_object_flush_cpu_write_domain(struct drm_gem_object *obj); | |
e47c68e9 EA |
51 | static int i915_gem_object_set_to_cpu_domain(struct drm_gem_object *obj, |
52 | int write); | |
53 | static int i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object *obj, | |
54 | uint64_t offset, | |
55 | uint64_t size); | |
56 | static void i915_gem_object_set_to_full_cpu_read_domain(struct drm_gem_object *obj); | |
2cf34d7b CW |
57 | static int i915_gem_object_wait_rendering(struct drm_gem_object *obj, |
58 | bool interruptible); | |
de151cf6 | 59 | static int i915_gem_object_bind_to_gtt(struct drm_gem_object *obj, |
a00b10c3 | 60 | unsigned alignment, |
75e9e915 | 61 | bool map_and_fenceable); |
de151cf6 | 62 | static void i915_gem_clear_fence_reg(struct drm_gem_object *obj); |
71acb5eb DA |
63 | static int i915_gem_phys_pwrite(struct drm_device *dev, struct drm_gem_object *obj, |
64 | struct drm_i915_gem_pwrite *args, | |
65 | struct drm_file *file_priv); | |
be72615b | 66 | static void i915_gem_free_object_tail(struct drm_gem_object *obj); |
673a394b | 67 | |
17250b71 CW |
68 | static int i915_gem_inactive_shrink(struct shrinker *shrinker, |
69 | int nr_to_scan, | |
70 | gfp_t gfp_mask); | |
71 | ||
31169714 | 72 | |
73aa808f CW |
73 | /* some bookkeeping */ |
74 | static void i915_gem_info_add_obj(struct drm_i915_private *dev_priv, | |
75 | size_t size) | |
76 | { | |
77 | dev_priv->mm.object_count++; | |
78 | dev_priv->mm.object_memory += size; | |
79 | } | |
80 | ||
81 | static void i915_gem_info_remove_obj(struct drm_i915_private *dev_priv, | |
82 | size_t size) | |
83 | { | |
84 | dev_priv->mm.object_count--; | |
85 | dev_priv->mm.object_memory -= size; | |
86 | } | |
87 | ||
88 | static void i915_gem_info_add_gtt(struct drm_i915_private *dev_priv, | |
a00b10c3 | 89 | struct drm_i915_gem_object *obj) |
73aa808f CW |
90 | { |
91 | dev_priv->mm.gtt_count++; | |
a00b10c3 CW |
92 | dev_priv->mm.gtt_memory += obj->gtt_space->size; |
93 | if (obj->gtt_offset < dev_priv->mm.gtt_mappable_end) { | |
fb7d516a | 94 | dev_priv->mm.mappable_gtt_used += |
a00b10c3 CW |
95 | min_t(size_t, obj->gtt_space->size, |
96 | dev_priv->mm.gtt_mappable_end - obj->gtt_offset); | |
fb7d516a | 97 | } |
73aa808f CW |
98 | } |
99 | ||
100 | static void i915_gem_info_remove_gtt(struct drm_i915_private *dev_priv, | |
a00b10c3 | 101 | struct drm_i915_gem_object *obj) |
73aa808f CW |
102 | { |
103 | dev_priv->mm.gtt_count--; | |
a00b10c3 CW |
104 | dev_priv->mm.gtt_memory -= obj->gtt_space->size; |
105 | if (obj->gtt_offset < dev_priv->mm.gtt_mappable_end) { | |
fb7d516a | 106 | dev_priv->mm.mappable_gtt_used -= |
a00b10c3 CW |
107 | min_t(size_t, obj->gtt_space->size, |
108 | dev_priv->mm.gtt_mappable_end - obj->gtt_offset); | |
fb7d516a DV |
109 | } |
110 | } | |
111 | ||
112 | /** | |
113 | * Update the mappable working set counters. Call _only_ when there is a change | |
114 | * in one of (pin|fault)_mappable and update *_mappable _before_ calling. | |
115 | * @mappable: new state the changed mappable flag (either pin_ or fault_). | |
116 | */ | |
117 | static void | |
118 | i915_gem_info_update_mappable(struct drm_i915_private *dev_priv, | |
a00b10c3 | 119 | struct drm_i915_gem_object *obj, |
fb7d516a DV |
120 | bool mappable) |
121 | { | |
fb7d516a | 122 | if (mappable) { |
a00b10c3 | 123 | if (obj->pin_mappable && obj->fault_mappable) |
fb7d516a DV |
124 | /* Combined state was already mappable. */ |
125 | return; | |
126 | dev_priv->mm.gtt_mappable_count++; | |
a00b10c3 | 127 | dev_priv->mm.gtt_mappable_memory += obj->gtt_space->size; |
fb7d516a | 128 | } else { |
a00b10c3 | 129 | if (obj->pin_mappable || obj->fault_mappable) |
fb7d516a DV |
130 | /* Combined state still mappable. */ |
131 | return; | |
132 | dev_priv->mm.gtt_mappable_count--; | |
a00b10c3 | 133 | dev_priv->mm.gtt_mappable_memory -= obj->gtt_space->size; |
fb7d516a | 134 | } |
73aa808f CW |
135 | } |
136 | ||
137 | static void i915_gem_info_add_pin(struct drm_i915_private *dev_priv, | |
a00b10c3 | 138 | struct drm_i915_gem_object *obj, |
fb7d516a | 139 | bool mappable) |
73aa808f CW |
140 | { |
141 | dev_priv->mm.pin_count++; | |
a00b10c3 | 142 | dev_priv->mm.pin_memory += obj->gtt_space->size; |
fb7d516a | 143 | if (mappable) { |
a00b10c3 | 144 | obj->pin_mappable = true; |
fb7d516a DV |
145 | i915_gem_info_update_mappable(dev_priv, obj, true); |
146 | } | |
73aa808f CW |
147 | } |
148 | ||
149 | static void i915_gem_info_remove_pin(struct drm_i915_private *dev_priv, | |
a00b10c3 | 150 | struct drm_i915_gem_object *obj) |
73aa808f CW |
151 | { |
152 | dev_priv->mm.pin_count--; | |
a00b10c3 CW |
153 | dev_priv->mm.pin_memory -= obj->gtt_space->size; |
154 | if (obj->pin_mappable) { | |
155 | obj->pin_mappable = false; | |
fb7d516a DV |
156 | i915_gem_info_update_mappable(dev_priv, obj, false); |
157 | } | |
73aa808f CW |
158 | } |
159 | ||
30dbf0c0 CW |
160 | int |
161 | i915_gem_check_is_wedged(struct drm_device *dev) | |
162 | { | |
163 | struct drm_i915_private *dev_priv = dev->dev_private; | |
164 | struct completion *x = &dev_priv->error_completion; | |
165 | unsigned long flags; | |
166 | int ret; | |
167 | ||
168 | if (!atomic_read(&dev_priv->mm.wedged)) | |
169 | return 0; | |
170 | ||
171 | ret = wait_for_completion_interruptible(x); | |
172 | if (ret) | |
173 | return ret; | |
174 | ||
175 | /* Success, we reset the GPU! */ | |
176 | if (!atomic_read(&dev_priv->mm.wedged)) | |
177 | return 0; | |
178 | ||
179 | /* GPU is hung, bump the completion count to account for | |
180 | * the token we just consumed so that we never hit zero and | |
181 | * end up waiting upon a subsequent completion event that | |
182 | * will never happen. | |
183 | */ | |
184 | spin_lock_irqsave(&x->wait.lock, flags); | |
185 | x->done++; | |
186 | spin_unlock_irqrestore(&x->wait.lock, flags); | |
187 | return -EIO; | |
188 | } | |
189 | ||
76c1dec1 CW |
190 | static int i915_mutex_lock_interruptible(struct drm_device *dev) |
191 | { | |
192 | struct drm_i915_private *dev_priv = dev->dev_private; | |
193 | int ret; | |
194 | ||
195 | ret = i915_gem_check_is_wedged(dev); | |
196 | if (ret) | |
197 | return ret; | |
198 | ||
199 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
200 | if (ret) | |
201 | return ret; | |
202 | ||
203 | if (atomic_read(&dev_priv->mm.wedged)) { | |
204 | mutex_unlock(&dev->struct_mutex); | |
205 | return -EAGAIN; | |
206 | } | |
207 | ||
23bc5982 | 208 | WARN_ON(i915_verify_lists(dev)); |
76c1dec1 CW |
209 | return 0; |
210 | } | |
30dbf0c0 | 211 | |
7d1c4804 CW |
212 | static inline bool |
213 | i915_gem_object_is_inactive(struct drm_i915_gem_object *obj_priv) | |
214 | { | |
215 | return obj_priv->gtt_space && | |
216 | !obj_priv->active && | |
217 | obj_priv->pin_count == 0; | |
218 | } | |
219 | ||
73aa808f CW |
220 | int i915_gem_do_init(struct drm_device *dev, |
221 | unsigned long start, | |
53984635 | 222 | unsigned long mappable_end, |
79e53945 | 223 | unsigned long end) |
673a394b EA |
224 | { |
225 | drm_i915_private_t *dev_priv = dev->dev_private; | |
673a394b | 226 | |
79e53945 JB |
227 | if (start >= end || |
228 | (start & (PAGE_SIZE - 1)) != 0 || | |
229 | (end & (PAGE_SIZE - 1)) != 0) { | |
673a394b EA |
230 | return -EINVAL; |
231 | } | |
232 | ||
79e53945 JB |
233 | drm_mm_init(&dev_priv->mm.gtt_space, start, |
234 | end - start); | |
673a394b | 235 | |
73aa808f | 236 | dev_priv->mm.gtt_total = end - start; |
fb7d516a | 237 | dev_priv->mm.mappable_gtt_total = min(end, mappable_end) - start; |
53984635 | 238 | dev_priv->mm.gtt_mappable_end = mappable_end; |
79e53945 JB |
239 | |
240 | return 0; | |
241 | } | |
673a394b | 242 | |
79e53945 JB |
243 | int |
244 | i915_gem_init_ioctl(struct drm_device *dev, void *data, | |
245 | struct drm_file *file_priv) | |
246 | { | |
247 | struct drm_i915_gem_init *args = data; | |
248 | int ret; | |
249 | ||
250 | mutex_lock(&dev->struct_mutex); | |
53984635 | 251 | ret = i915_gem_do_init(dev, args->gtt_start, args->gtt_end, args->gtt_end); |
673a394b EA |
252 | mutex_unlock(&dev->struct_mutex); |
253 | ||
79e53945 | 254 | return ret; |
673a394b EA |
255 | } |
256 | ||
5a125c3c EA |
257 | int |
258 | i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data, | |
259 | struct drm_file *file_priv) | |
260 | { | |
73aa808f | 261 | struct drm_i915_private *dev_priv = dev->dev_private; |
5a125c3c | 262 | struct drm_i915_gem_get_aperture *args = data; |
5a125c3c EA |
263 | |
264 | if (!(dev->driver->driver_features & DRIVER_GEM)) | |
265 | return -ENODEV; | |
266 | ||
73aa808f CW |
267 | mutex_lock(&dev->struct_mutex); |
268 | args->aper_size = dev_priv->mm.gtt_total; | |
269 | args->aper_available_size = args->aper_size - dev_priv->mm.pin_memory; | |
270 | mutex_unlock(&dev->struct_mutex); | |
5a125c3c EA |
271 | |
272 | return 0; | |
273 | } | |
274 | ||
673a394b EA |
275 | |
276 | /** | |
277 | * Creates a new mm object and returns a handle to it. | |
278 | */ | |
279 | int | |
280 | i915_gem_create_ioctl(struct drm_device *dev, void *data, | |
281 | struct drm_file *file_priv) | |
282 | { | |
283 | struct drm_i915_gem_create *args = data; | |
284 | struct drm_gem_object *obj; | |
a1a2d1d3 PP |
285 | int ret; |
286 | u32 handle; | |
673a394b EA |
287 | |
288 | args->size = roundup(args->size, PAGE_SIZE); | |
289 | ||
290 | /* Allocate the new object */ | |
ac52bc56 | 291 | obj = i915_gem_alloc_object(dev, args->size); |
673a394b EA |
292 | if (obj == NULL) |
293 | return -ENOMEM; | |
294 | ||
295 | ret = drm_gem_handle_create(file_priv, obj, &handle); | |
1dfd9754 | 296 | if (ret) { |
202f2fef CW |
297 | drm_gem_object_release(obj); |
298 | i915_gem_info_remove_obj(dev->dev_private, obj->size); | |
299 | kfree(obj); | |
673a394b | 300 | return ret; |
1dfd9754 | 301 | } |
673a394b | 302 | |
202f2fef CW |
303 | /* drop reference from allocate - handle holds it now */ |
304 | drm_gem_object_unreference(obj); | |
305 | trace_i915_gem_object_create(obj); | |
306 | ||
1dfd9754 | 307 | args->handle = handle; |
673a394b EA |
308 | return 0; |
309 | } | |
310 | ||
280b713b EA |
311 | static int i915_gem_object_needs_bit17_swizzle(struct drm_gem_object *obj) |
312 | { | |
313 | drm_i915_private_t *dev_priv = obj->dev->dev_private; | |
23010e43 | 314 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
280b713b EA |
315 | |
316 | return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 && | |
317 | obj_priv->tiling_mode != I915_TILING_NONE; | |
318 | } | |
319 | ||
99a03df5 | 320 | static inline void |
40123c1f EA |
321 | slow_shmem_copy(struct page *dst_page, |
322 | int dst_offset, | |
323 | struct page *src_page, | |
324 | int src_offset, | |
325 | int length) | |
326 | { | |
327 | char *dst_vaddr, *src_vaddr; | |
328 | ||
99a03df5 CW |
329 | dst_vaddr = kmap(dst_page); |
330 | src_vaddr = kmap(src_page); | |
40123c1f EA |
331 | |
332 | memcpy(dst_vaddr + dst_offset, src_vaddr + src_offset, length); | |
333 | ||
99a03df5 CW |
334 | kunmap(src_page); |
335 | kunmap(dst_page); | |
40123c1f EA |
336 | } |
337 | ||
99a03df5 | 338 | static inline void |
280b713b EA |
339 | slow_shmem_bit17_copy(struct page *gpu_page, |
340 | int gpu_offset, | |
341 | struct page *cpu_page, | |
342 | int cpu_offset, | |
343 | int length, | |
344 | int is_read) | |
345 | { | |
346 | char *gpu_vaddr, *cpu_vaddr; | |
347 | ||
348 | /* Use the unswizzled path if this page isn't affected. */ | |
349 | if ((page_to_phys(gpu_page) & (1 << 17)) == 0) { | |
350 | if (is_read) | |
351 | return slow_shmem_copy(cpu_page, cpu_offset, | |
352 | gpu_page, gpu_offset, length); | |
353 | else | |
354 | return slow_shmem_copy(gpu_page, gpu_offset, | |
355 | cpu_page, cpu_offset, length); | |
356 | } | |
357 | ||
99a03df5 CW |
358 | gpu_vaddr = kmap(gpu_page); |
359 | cpu_vaddr = kmap(cpu_page); | |
280b713b EA |
360 | |
361 | /* Copy the data, XORing A6 with A17 (1). The user already knows he's | |
362 | * XORing with the other bits (A9 for Y, A9 and A10 for X) | |
363 | */ | |
364 | while (length > 0) { | |
365 | int cacheline_end = ALIGN(gpu_offset + 1, 64); | |
366 | int this_length = min(cacheline_end - gpu_offset, length); | |
367 | int swizzled_gpu_offset = gpu_offset ^ 64; | |
368 | ||
369 | if (is_read) { | |
370 | memcpy(cpu_vaddr + cpu_offset, | |
371 | gpu_vaddr + swizzled_gpu_offset, | |
372 | this_length); | |
373 | } else { | |
374 | memcpy(gpu_vaddr + swizzled_gpu_offset, | |
375 | cpu_vaddr + cpu_offset, | |
376 | this_length); | |
377 | } | |
378 | cpu_offset += this_length; | |
379 | gpu_offset += this_length; | |
380 | length -= this_length; | |
381 | } | |
382 | ||
99a03df5 CW |
383 | kunmap(cpu_page); |
384 | kunmap(gpu_page); | |
280b713b EA |
385 | } |
386 | ||
eb01459f EA |
387 | /** |
388 | * This is the fast shmem pread path, which attempts to copy_from_user directly | |
389 | * from the backing pages of the object to the user's address space. On a | |
390 | * fault, it fails so we can fall back to i915_gem_shmem_pwrite_slow(). | |
391 | */ | |
392 | static int | |
393 | i915_gem_shmem_pread_fast(struct drm_device *dev, struct drm_gem_object *obj, | |
394 | struct drm_i915_gem_pread *args, | |
395 | struct drm_file *file_priv) | |
396 | { | |
23010e43 | 397 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
e5281ccd | 398 | struct address_space *mapping = obj->filp->f_path.dentry->d_inode->i_mapping; |
eb01459f | 399 | ssize_t remain; |
e5281ccd | 400 | loff_t offset; |
eb01459f EA |
401 | char __user *user_data; |
402 | int page_offset, page_length; | |
eb01459f EA |
403 | |
404 | user_data = (char __user *) (uintptr_t) args->data_ptr; | |
405 | remain = args->size; | |
406 | ||
23010e43 | 407 | obj_priv = to_intel_bo(obj); |
eb01459f EA |
408 | offset = args->offset; |
409 | ||
410 | while (remain > 0) { | |
e5281ccd CW |
411 | struct page *page; |
412 | char *vaddr; | |
413 | int ret; | |
414 | ||
eb01459f EA |
415 | /* Operation in this page |
416 | * | |
eb01459f EA |
417 | * page_offset = offset within page |
418 | * page_length = bytes to copy for this page | |
419 | */ | |
eb01459f EA |
420 | page_offset = offset & (PAGE_SIZE-1); |
421 | page_length = remain; | |
422 | if ((page_offset + remain) > PAGE_SIZE) | |
423 | page_length = PAGE_SIZE - page_offset; | |
424 | ||
e5281ccd CW |
425 | page = read_cache_page_gfp(mapping, offset >> PAGE_SHIFT, |
426 | GFP_HIGHUSER | __GFP_RECLAIMABLE); | |
427 | if (IS_ERR(page)) | |
428 | return PTR_ERR(page); | |
429 | ||
430 | vaddr = kmap_atomic(page); | |
431 | ret = __copy_to_user_inatomic(user_data, | |
432 | vaddr + page_offset, | |
433 | page_length); | |
434 | kunmap_atomic(vaddr); | |
435 | ||
436 | mark_page_accessed(page); | |
437 | page_cache_release(page); | |
438 | if (ret) | |
4f27b75d | 439 | return -EFAULT; |
eb01459f EA |
440 | |
441 | remain -= page_length; | |
442 | user_data += page_length; | |
443 | offset += page_length; | |
444 | } | |
445 | ||
4f27b75d | 446 | return 0; |
eb01459f EA |
447 | } |
448 | ||
449 | /** | |
450 | * This is the fallback shmem pread path, which allocates temporary storage | |
451 | * in kernel space to copy_to_user into outside of the struct_mutex, so we | |
452 | * can copy out of the object's backing pages while holding the struct mutex | |
453 | * and not take page faults. | |
454 | */ | |
455 | static int | |
456 | i915_gem_shmem_pread_slow(struct drm_device *dev, struct drm_gem_object *obj, | |
457 | struct drm_i915_gem_pread *args, | |
458 | struct drm_file *file_priv) | |
459 | { | |
e5281ccd | 460 | struct address_space *mapping = obj->filp->f_path.dentry->d_inode->i_mapping; |
23010e43 | 461 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
eb01459f EA |
462 | struct mm_struct *mm = current->mm; |
463 | struct page **user_pages; | |
464 | ssize_t remain; | |
465 | loff_t offset, pinned_pages, i; | |
466 | loff_t first_data_page, last_data_page, num_pages; | |
e5281ccd CW |
467 | int shmem_page_offset; |
468 | int data_page_index, data_page_offset; | |
eb01459f EA |
469 | int page_length; |
470 | int ret; | |
471 | uint64_t data_ptr = args->data_ptr; | |
280b713b | 472 | int do_bit17_swizzling; |
eb01459f EA |
473 | |
474 | remain = args->size; | |
475 | ||
476 | /* Pin the user pages containing the data. We can't fault while | |
477 | * holding the struct mutex, yet we want to hold it while | |
478 | * dereferencing the user data. | |
479 | */ | |
480 | first_data_page = data_ptr / PAGE_SIZE; | |
481 | last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE; | |
482 | num_pages = last_data_page - first_data_page + 1; | |
483 | ||
4f27b75d | 484 | user_pages = drm_malloc_ab(num_pages, sizeof(struct page *)); |
eb01459f EA |
485 | if (user_pages == NULL) |
486 | return -ENOMEM; | |
487 | ||
4f27b75d | 488 | mutex_unlock(&dev->struct_mutex); |
eb01459f EA |
489 | down_read(&mm->mmap_sem); |
490 | pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr, | |
e5e9ecde | 491 | num_pages, 1, 0, user_pages, NULL); |
eb01459f | 492 | up_read(&mm->mmap_sem); |
4f27b75d | 493 | mutex_lock(&dev->struct_mutex); |
eb01459f EA |
494 | if (pinned_pages < num_pages) { |
495 | ret = -EFAULT; | |
4f27b75d | 496 | goto out; |
eb01459f EA |
497 | } |
498 | ||
4f27b75d CW |
499 | ret = i915_gem_object_set_cpu_read_domain_range(obj, |
500 | args->offset, | |
501 | args->size); | |
07f73f69 | 502 | if (ret) |
4f27b75d | 503 | goto out; |
eb01459f | 504 | |
4f27b75d | 505 | do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj); |
eb01459f | 506 | |
23010e43 | 507 | obj_priv = to_intel_bo(obj); |
eb01459f EA |
508 | offset = args->offset; |
509 | ||
510 | while (remain > 0) { | |
e5281ccd CW |
511 | struct page *page; |
512 | ||
eb01459f EA |
513 | /* Operation in this page |
514 | * | |
eb01459f EA |
515 | * shmem_page_offset = offset within page in shmem file |
516 | * data_page_index = page number in get_user_pages return | |
517 | * data_page_offset = offset with data_page_index page. | |
518 | * page_length = bytes to copy for this page | |
519 | */ | |
eb01459f EA |
520 | shmem_page_offset = offset & ~PAGE_MASK; |
521 | data_page_index = data_ptr / PAGE_SIZE - first_data_page; | |
522 | data_page_offset = data_ptr & ~PAGE_MASK; | |
523 | ||
524 | page_length = remain; | |
525 | if ((shmem_page_offset + page_length) > PAGE_SIZE) | |
526 | page_length = PAGE_SIZE - shmem_page_offset; | |
527 | if ((data_page_offset + page_length) > PAGE_SIZE) | |
528 | page_length = PAGE_SIZE - data_page_offset; | |
529 | ||
e5281ccd CW |
530 | page = read_cache_page_gfp(mapping, offset >> PAGE_SHIFT, |
531 | GFP_HIGHUSER | __GFP_RECLAIMABLE); | |
532 | if (IS_ERR(page)) | |
533 | return PTR_ERR(page); | |
534 | ||
280b713b | 535 | if (do_bit17_swizzling) { |
e5281ccd | 536 | slow_shmem_bit17_copy(page, |
280b713b | 537 | shmem_page_offset, |
99a03df5 CW |
538 | user_pages[data_page_index], |
539 | data_page_offset, | |
540 | page_length, | |
541 | 1); | |
542 | } else { | |
543 | slow_shmem_copy(user_pages[data_page_index], | |
544 | data_page_offset, | |
e5281ccd | 545 | page, |
99a03df5 CW |
546 | shmem_page_offset, |
547 | page_length); | |
280b713b | 548 | } |
eb01459f | 549 | |
e5281ccd CW |
550 | mark_page_accessed(page); |
551 | page_cache_release(page); | |
552 | ||
eb01459f EA |
553 | remain -= page_length; |
554 | data_ptr += page_length; | |
555 | offset += page_length; | |
556 | } | |
557 | ||
4f27b75d | 558 | out: |
eb01459f EA |
559 | for (i = 0; i < pinned_pages; i++) { |
560 | SetPageDirty(user_pages[i]); | |
e5281ccd | 561 | mark_page_accessed(user_pages[i]); |
eb01459f EA |
562 | page_cache_release(user_pages[i]); |
563 | } | |
8e7d2b2c | 564 | drm_free_large(user_pages); |
eb01459f EA |
565 | |
566 | return ret; | |
567 | } | |
568 | ||
673a394b EA |
569 | /** |
570 | * Reads data from the object referenced by handle. | |
571 | * | |
572 | * On error, the contents of *data are undefined. | |
573 | */ | |
574 | int | |
575 | i915_gem_pread_ioctl(struct drm_device *dev, void *data, | |
576 | struct drm_file *file_priv) | |
577 | { | |
578 | struct drm_i915_gem_pread *args = data; | |
579 | struct drm_gem_object *obj; | |
580 | struct drm_i915_gem_object *obj_priv; | |
35b62a89 | 581 | int ret = 0; |
673a394b | 582 | |
51311d0a CW |
583 | if (args->size == 0) |
584 | return 0; | |
585 | ||
586 | if (!access_ok(VERIFY_WRITE, | |
587 | (char __user *)(uintptr_t)args->data_ptr, | |
588 | args->size)) | |
589 | return -EFAULT; | |
590 | ||
591 | ret = fault_in_pages_writeable((char __user *)(uintptr_t)args->data_ptr, | |
592 | args->size); | |
593 | if (ret) | |
594 | return -EFAULT; | |
595 | ||
4f27b75d | 596 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 597 | if (ret) |
4f27b75d | 598 | return ret; |
673a394b EA |
599 | |
600 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); | |
1d7cfea1 CW |
601 | if (obj == NULL) { |
602 | ret = -ENOENT; | |
603 | goto unlock; | |
4f27b75d | 604 | } |
23010e43 | 605 | obj_priv = to_intel_bo(obj); |
673a394b | 606 | |
7dcd2499 CW |
607 | /* Bounds check source. */ |
608 | if (args->offset > obj->size || args->size > obj->size - args->offset) { | |
ce9d419d | 609 | ret = -EINVAL; |
35b62a89 | 610 | goto out; |
ce9d419d CW |
611 | } |
612 | ||
4f27b75d CW |
613 | ret = i915_gem_object_set_cpu_read_domain_range(obj, |
614 | args->offset, | |
615 | args->size); | |
616 | if (ret) | |
e5281ccd | 617 | goto out; |
4f27b75d CW |
618 | |
619 | ret = -EFAULT; | |
620 | if (!i915_gem_object_needs_bit17_swizzle(obj)) | |
280b713b | 621 | ret = i915_gem_shmem_pread_fast(dev, obj, args, file_priv); |
4f27b75d CW |
622 | if (ret == -EFAULT) |
623 | ret = i915_gem_shmem_pread_slow(dev, obj, args, file_priv); | |
673a394b | 624 | |
35b62a89 | 625 | out: |
4f27b75d | 626 | drm_gem_object_unreference(obj); |
1d7cfea1 | 627 | unlock: |
4f27b75d | 628 | mutex_unlock(&dev->struct_mutex); |
eb01459f | 629 | return ret; |
673a394b EA |
630 | } |
631 | ||
0839ccb8 KP |
632 | /* This is the fast write path which cannot handle |
633 | * page faults in the source data | |
9b7530cc | 634 | */ |
0839ccb8 KP |
635 | |
636 | static inline int | |
637 | fast_user_write(struct io_mapping *mapping, | |
638 | loff_t page_base, int page_offset, | |
639 | char __user *user_data, | |
640 | int length) | |
9b7530cc | 641 | { |
9b7530cc | 642 | char *vaddr_atomic; |
0839ccb8 | 643 | unsigned long unwritten; |
9b7530cc | 644 | |
3e4d3af5 | 645 | vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base); |
0839ccb8 KP |
646 | unwritten = __copy_from_user_inatomic_nocache(vaddr_atomic + page_offset, |
647 | user_data, length); | |
3e4d3af5 | 648 | io_mapping_unmap_atomic(vaddr_atomic); |
fbd5a26d | 649 | return unwritten; |
0839ccb8 KP |
650 | } |
651 | ||
652 | /* Here's the write path which can sleep for | |
653 | * page faults | |
654 | */ | |
655 | ||
ab34c226 | 656 | static inline void |
3de09aa3 EA |
657 | slow_kernel_write(struct io_mapping *mapping, |
658 | loff_t gtt_base, int gtt_offset, | |
659 | struct page *user_page, int user_offset, | |
660 | int length) | |
0839ccb8 | 661 | { |
ab34c226 CW |
662 | char __iomem *dst_vaddr; |
663 | char *src_vaddr; | |
0839ccb8 | 664 | |
ab34c226 CW |
665 | dst_vaddr = io_mapping_map_wc(mapping, gtt_base); |
666 | src_vaddr = kmap(user_page); | |
667 | ||
668 | memcpy_toio(dst_vaddr + gtt_offset, | |
669 | src_vaddr + user_offset, | |
670 | length); | |
671 | ||
672 | kunmap(user_page); | |
673 | io_mapping_unmap(dst_vaddr); | |
9b7530cc LT |
674 | } |
675 | ||
3de09aa3 EA |
676 | /** |
677 | * This is the fast pwrite path, where we copy the data directly from the | |
678 | * user into the GTT, uncached. | |
679 | */ | |
673a394b | 680 | static int |
3de09aa3 EA |
681 | i915_gem_gtt_pwrite_fast(struct drm_device *dev, struct drm_gem_object *obj, |
682 | struct drm_i915_gem_pwrite *args, | |
683 | struct drm_file *file_priv) | |
673a394b | 684 | { |
23010e43 | 685 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
0839ccb8 | 686 | drm_i915_private_t *dev_priv = dev->dev_private; |
673a394b | 687 | ssize_t remain; |
0839ccb8 | 688 | loff_t offset, page_base; |
673a394b | 689 | char __user *user_data; |
0839ccb8 | 690 | int page_offset, page_length; |
673a394b EA |
691 | |
692 | user_data = (char __user *) (uintptr_t) args->data_ptr; | |
693 | remain = args->size; | |
673a394b | 694 | |
23010e43 | 695 | obj_priv = to_intel_bo(obj); |
673a394b | 696 | offset = obj_priv->gtt_offset + args->offset; |
673a394b EA |
697 | |
698 | while (remain > 0) { | |
699 | /* Operation in this page | |
700 | * | |
0839ccb8 KP |
701 | * page_base = page offset within aperture |
702 | * page_offset = offset within page | |
703 | * page_length = bytes to copy for this page | |
673a394b | 704 | */ |
0839ccb8 KP |
705 | page_base = (offset & ~(PAGE_SIZE-1)); |
706 | page_offset = offset & (PAGE_SIZE-1); | |
707 | page_length = remain; | |
708 | if ((page_offset + remain) > PAGE_SIZE) | |
709 | page_length = PAGE_SIZE - page_offset; | |
710 | ||
0839ccb8 | 711 | /* If we get a fault while copying data, then (presumably) our |
3de09aa3 EA |
712 | * source page isn't available. Return the error and we'll |
713 | * retry in the slow path. | |
0839ccb8 | 714 | */ |
fbd5a26d CW |
715 | if (fast_user_write(dev_priv->mm.gtt_mapping, page_base, |
716 | page_offset, user_data, page_length)) | |
717 | ||
718 | return -EFAULT; | |
673a394b | 719 | |
0839ccb8 KP |
720 | remain -= page_length; |
721 | user_data += page_length; | |
722 | offset += page_length; | |
673a394b | 723 | } |
673a394b | 724 | |
fbd5a26d | 725 | return 0; |
673a394b EA |
726 | } |
727 | ||
3de09aa3 EA |
728 | /** |
729 | * This is the fallback GTT pwrite path, which uses get_user_pages to pin | |
730 | * the memory and maps it using kmap_atomic for copying. | |
731 | * | |
732 | * This code resulted in x11perf -rgb10text consuming about 10% more CPU | |
733 | * than using i915_gem_gtt_pwrite_fast on a G45 (32-bit). | |
734 | */ | |
3043c60c | 735 | static int |
3de09aa3 EA |
736 | i915_gem_gtt_pwrite_slow(struct drm_device *dev, struct drm_gem_object *obj, |
737 | struct drm_i915_gem_pwrite *args, | |
738 | struct drm_file *file_priv) | |
673a394b | 739 | { |
23010e43 | 740 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
3de09aa3 EA |
741 | drm_i915_private_t *dev_priv = dev->dev_private; |
742 | ssize_t remain; | |
743 | loff_t gtt_page_base, offset; | |
744 | loff_t first_data_page, last_data_page, num_pages; | |
745 | loff_t pinned_pages, i; | |
746 | struct page **user_pages; | |
747 | struct mm_struct *mm = current->mm; | |
748 | int gtt_page_offset, data_page_offset, data_page_index, page_length; | |
673a394b | 749 | int ret; |
3de09aa3 EA |
750 | uint64_t data_ptr = args->data_ptr; |
751 | ||
752 | remain = args->size; | |
753 | ||
754 | /* Pin the user pages containing the data. We can't fault while | |
755 | * holding the struct mutex, and all of the pwrite implementations | |
756 | * want to hold it while dereferencing the user data. | |
757 | */ | |
758 | first_data_page = data_ptr / PAGE_SIZE; | |
759 | last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE; | |
760 | num_pages = last_data_page - first_data_page + 1; | |
761 | ||
fbd5a26d | 762 | user_pages = drm_malloc_ab(num_pages, sizeof(struct page *)); |
3de09aa3 EA |
763 | if (user_pages == NULL) |
764 | return -ENOMEM; | |
765 | ||
fbd5a26d | 766 | mutex_unlock(&dev->struct_mutex); |
3de09aa3 EA |
767 | down_read(&mm->mmap_sem); |
768 | pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr, | |
769 | num_pages, 0, 0, user_pages, NULL); | |
770 | up_read(&mm->mmap_sem); | |
fbd5a26d | 771 | mutex_lock(&dev->struct_mutex); |
3de09aa3 EA |
772 | if (pinned_pages < num_pages) { |
773 | ret = -EFAULT; | |
774 | goto out_unpin_pages; | |
775 | } | |
673a394b | 776 | |
3de09aa3 EA |
777 | ret = i915_gem_object_set_to_gtt_domain(obj, 1); |
778 | if (ret) | |
fbd5a26d | 779 | goto out_unpin_pages; |
3de09aa3 | 780 | |
23010e43 | 781 | obj_priv = to_intel_bo(obj); |
3de09aa3 EA |
782 | offset = obj_priv->gtt_offset + args->offset; |
783 | ||
784 | while (remain > 0) { | |
785 | /* Operation in this page | |
786 | * | |
787 | * gtt_page_base = page offset within aperture | |
788 | * gtt_page_offset = offset within page in aperture | |
789 | * data_page_index = page number in get_user_pages return | |
790 | * data_page_offset = offset with data_page_index page. | |
791 | * page_length = bytes to copy for this page | |
792 | */ | |
793 | gtt_page_base = offset & PAGE_MASK; | |
794 | gtt_page_offset = offset & ~PAGE_MASK; | |
795 | data_page_index = data_ptr / PAGE_SIZE - first_data_page; | |
796 | data_page_offset = data_ptr & ~PAGE_MASK; | |
797 | ||
798 | page_length = remain; | |
799 | if ((gtt_page_offset + page_length) > PAGE_SIZE) | |
800 | page_length = PAGE_SIZE - gtt_page_offset; | |
801 | if ((data_page_offset + page_length) > PAGE_SIZE) | |
802 | page_length = PAGE_SIZE - data_page_offset; | |
803 | ||
ab34c226 CW |
804 | slow_kernel_write(dev_priv->mm.gtt_mapping, |
805 | gtt_page_base, gtt_page_offset, | |
806 | user_pages[data_page_index], | |
807 | data_page_offset, | |
808 | page_length); | |
3de09aa3 EA |
809 | |
810 | remain -= page_length; | |
811 | offset += page_length; | |
812 | data_ptr += page_length; | |
813 | } | |
814 | ||
3de09aa3 EA |
815 | out_unpin_pages: |
816 | for (i = 0; i < pinned_pages; i++) | |
817 | page_cache_release(user_pages[i]); | |
8e7d2b2c | 818 | drm_free_large(user_pages); |
3de09aa3 EA |
819 | |
820 | return ret; | |
821 | } | |
822 | ||
40123c1f EA |
823 | /** |
824 | * This is the fast shmem pwrite path, which attempts to directly | |
825 | * copy_from_user into the kmapped pages backing the object. | |
826 | */ | |
3043c60c | 827 | static int |
40123c1f EA |
828 | i915_gem_shmem_pwrite_fast(struct drm_device *dev, struct drm_gem_object *obj, |
829 | struct drm_i915_gem_pwrite *args, | |
830 | struct drm_file *file_priv) | |
673a394b | 831 | { |
e5281ccd | 832 | struct address_space *mapping = obj->filp->f_path.dentry->d_inode->i_mapping; |
23010e43 | 833 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
40123c1f | 834 | ssize_t remain; |
e5281ccd | 835 | loff_t offset; |
40123c1f EA |
836 | char __user *user_data; |
837 | int page_offset, page_length; | |
40123c1f EA |
838 | |
839 | user_data = (char __user *) (uintptr_t) args->data_ptr; | |
840 | remain = args->size; | |
673a394b | 841 | |
23010e43 | 842 | obj_priv = to_intel_bo(obj); |
40123c1f EA |
843 | offset = args->offset; |
844 | obj_priv->dirty = 1; | |
845 | ||
846 | while (remain > 0) { | |
e5281ccd CW |
847 | struct page *page; |
848 | char *vaddr; | |
849 | int ret; | |
850 | ||
40123c1f EA |
851 | /* Operation in this page |
852 | * | |
40123c1f EA |
853 | * page_offset = offset within page |
854 | * page_length = bytes to copy for this page | |
855 | */ | |
40123c1f EA |
856 | page_offset = offset & (PAGE_SIZE-1); |
857 | page_length = remain; | |
858 | if ((page_offset + remain) > PAGE_SIZE) | |
859 | page_length = PAGE_SIZE - page_offset; | |
860 | ||
e5281ccd CW |
861 | page = read_cache_page_gfp(mapping, offset >> PAGE_SHIFT, |
862 | GFP_HIGHUSER | __GFP_RECLAIMABLE); | |
863 | if (IS_ERR(page)) | |
864 | return PTR_ERR(page); | |
865 | ||
866 | vaddr = kmap_atomic(page, KM_USER0); | |
867 | ret = __copy_from_user_inatomic(vaddr + page_offset, | |
868 | user_data, | |
869 | page_length); | |
870 | kunmap_atomic(vaddr, KM_USER0); | |
871 | ||
872 | set_page_dirty(page); | |
873 | mark_page_accessed(page); | |
874 | page_cache_release(page); | |
875 | ||
876 | /* If we get a fault while copying data, then (presumably) our | |
877 | * source page isn't available. Return the error and we'll | |
878 | * retry in the slow path. | |
879 | */ | |
880 | if (ret) | |
fbd5a26d | 881 | return -EFAULT; |
40123c1f EA |
882 | |
883 | remain -= page_length; | |
884 | user_data += page_length; | |
885 | offset += page_length; | |
886 | } | |
887 | ||
fbd5a26d | 888 | return 0; |
40123c1f EA |
889 | } |
890 | ||
891 | /** | |
892 | * This is the fallback shmem pwrite path, which uses get_user_pages to pin | |
893 | * the memory and maps it using kmap_atomic for copying. | |
894 | * | |
895 | * This avoids taking mmap_sem for faulting on the user's address while the | |
896 | * struct_mutex is held. | |
897 | */ | |
898 | static int | |
899 | i915_gem_shmem_pwrite_slow(struct drm_device *dev, struct drm_gem_object *obj, | |
900 | struct drm_i915_gem_pwrite *args, | |
901 | struct drm_file *file_priv) | |
902 | { | |
e5281ccd | 903 | struct address_space *mapping = obj->filp->f_path.dentry->d_inode->i_mapping; |
23010e43 | 904 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
40123c1f EA |
905 | struct mm_struct *mm = current->mm; |
906 | struct page **user_pages; | |
907 | ssize_t remain; | |
908 | loff_t offset, pinned_pages, i; | |
909 | loff_t first_data_page, last_data_page, num_pages; | |
e5281ccd | 910 | int shmem_page_offset; |
40123c1f EA |
911 | int data_page_index, data_page_offset; |
912 | int page_length; | |
913 | int ret; | |
914 | uint64_t data_ptr = args->data_ptr; | |
280b713b | 915 | int do_bit17_swizzling; |
40123c1f EA |
916 | |
917 | remain = args->size; | |
918 | ||
919 | /* Pin the user pages containing the data. We can't fault while | |
920 | * holding the struct mutex, and all of the pwrite implementations | |
921 | * want to hold it while dereferencing the user data. | |
922 | */ | |
923 | first_data_page = data_ptr / PAGE_SIZE; | |
924 | last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE; | |
925 | num_pages = last_data_page - first_data_page + 1; | |
926 | ||
4f27b75d | 927 | user_pages = drm_malloc_ab(num_pages, sizeof(struct page *)); |
40123c1f EA |
928 | if (user_pages == NULL) |
929 | return -ENOMEM; | |
930 | ||
fbd5a26d | 931 | mutex_unlock(&dev->struct_mutex); |
40123c1f EA |
932 | down_read(&mm->mmap_sem); |
933 | pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr, | |
934 | num_pages, 0, 0, user_pages, NULL); | |
935 | up_read(&mm->mmap_sem); | |
fbd5a26d | 936 | mutex_lock(&dev->struct_mutex); |
40123c1f EA |
937 | if (pinned_pages < num_pages) { |
938 | ret = -EFAULT; | |
fbd5a26d | 939 | goto out; |
673a394b EA |
940 | } |
941 | ||
fbd5a26d | 942 | ret = i915_gem_object_set_to_cpu_domain(obj, 1); |
07f73f69 | 943 | if (ret) |
fbd5a26d | 944 | goto out; |
40123c1f | 945 | |
fbd5a26d | 946 | do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj); |
40123c1f | 947 | |
23010e43 | 948 | obj_priv = to_intel_bo(obj); |
673a394b | 949 | offset = args->offset; |
40123c1f | 950 | obj_priv->dirty = 1; |
673a394b | 951 | |
40123c1f | 952 | while (remain > 0) { |
e5281ccd CW |
953 | struct page *page; |
954 | ||
40123c1f EA |
955 | /* Operation in this page |
956 | * | |
40123c1f EA |
957 | * shmem_page_offset = offset within page in shmem file |
958 | * data_page_index = page number in get_user_pages return | |
959 | * data_page_offset = offset with data_page_index page. | |
960 | * page_length = bytes to copy for this page | |
961 | */ | |
40123c1f EA |
962 | shmem_page_offset = offset & ~PAGE_MASK; |
963 | data_page_index = data_ptr / PAGE_SIZE - first_data_page; | |
964 | data_page_offset = data_ptr & ~PAGE_MASK; | |
965 | ||
966 | page_length = remain; | |
967 | if ((shmem_page_offset + page_length) > PAGE_SIZE) | |
968 | page_length = PAGE_SIZE - shmem_page_offset; | |
969 | if ((data_page_offset + page_length) > PAGE_SIZE) | |
970 | page_length = PAGE_SIZE - data_page_offset; | |
971 | ||
e5281ccd CW |
972 | page = read_cache_page_gfp(mapping, offset >> PAGE_SHIFT, |
973 | GFP_HIGHUSER | __GFP_RECLAIMABLE); | |
974 | if (IS_ERR(page)) { | |
975 | ret = PTR_ERR(page); | |
976 | goto out; | |
977 | } | |
978 | ||
280b713b | 979 | if (do_bit17_swizzling) { |
e5281ccd | 980 | slow_shmem_bit17_copy(page, |
280b713b EA |
981 | shmem_page_offset, |
982 | user_pages[data_page_index], | |
983 | data_page_offset, | |
99a03df5 CW |
984 | page_length, |
985 | 0); | |
986 | } else { | |
e5281ccd | 987 | slow_shmem_copy(page, |
99a03df5 CW |
988 | shmem_page_offset, |
989 | user_pages[data_page_index], | |
990 | data_page_offset, | |
991 | page_length); | |
280b713b | 992 | } |
40123c1f | 993 | |
e5281ccd CW |
994 | set_page_dirty(page); |
995 | mark_page_accessed(page); | |
996 | page_cache_release(page); | |
997 | ||
40123c1f EA |
998 | remain -= page_length; |
999 | data_ptr += page_length; | |
1000 | offset += page_length; | |
673a394b EA |
1001 | } |
1002 | ||
fbd5a26d | 1003 | out: |
40123c1f EA |
1004 | for (i = 0; i < pinned_pages; i++) |
1005 | page_cache_release(user_pages[i]); | |
8e7d2b2c | 1006 | drm_free_large(user_pages); |
673a394b | 1007 | |
40123c1f | 1008 | return ret; |
673a394b EA |
1009 | } |
1010 | ||
1011 | /** | |
1012 | * Writes data to the object referenced by handle. | |
1013 | * | |
1014 | * On error, the contents of the buffer that were to be modified are undefined. | |
1015 | */ | |
1016 | int | |
1017 | i915_gem_pwrite_ioctl(struct drm_device *dev, void *data, | |
fbd5a26d | 1018 | struct drm_file *file) |
673a394b EA |
1019 | { |
1020 | struct drm_i915_gem_pwrite *args = data; | |
1021 | struct drm_gem_object *obj; | |
1022 | struct drm_i915_gem_object *obj_priv; | |
51311d0a CW |
1023 | int ret; |
1024 | ||
1025 | if (args->size == 0) | |
1026 | return 0; | |
1027 | ||
1028 | if (!access_ok(VERIFY_READ, | |
1029 | (char __user *)(uintptr_t)args->data_ptr, | |
1030 | args->size)) | |
1031 | return -EFAULT; | |
1032 | ||
1033 | ret = fault_in_pages_readable((char __user *)(uintptr_t)args->data_ptr, | |
1034 | args->size); | |
1035 | if (ret) | |
1036 | return -EFAULT; | |
673a394b | 1037 | |
fbd5a26d | 1038 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 1039 | if (ret) |
fbd5a26d | 1040 | return ret; |
1d7cfea1 CW |
1041 | |
1042 | obj = drm_gem_object_lookup(dev, file, args->handle); | |
1043 | if (obj == NULL) { | |
1044 | ret = -ENOENT; | |
1045 | goto unlock; | |
fbd5a26d | 1046 | } |
23010e43 | 1047 | obj_priv = to_intel_bo(obj); |
673a394b | 1048 | |
7dcd2499 CW |
1049 | /* Bounds check destination. */ |
1050 | if (args->offset > obj->size || args->size > obj->size - args->offset) { | |
ce9d419d | 1051 | ret = -EINVAL; |
35b62a89 | 1052 | goto out; |
ce9d419d CW |
1053 | } |
1054 | ||
673a394b EA |
1055 | /* We can only do the GTT pwrite on untiled buffers, as otherwise |
1056 | * it would end up going through the fenced access, and we'll get | |
1057 | * different detiling behavior between reading and writing. | |
1058 | * pread/pwrite currently are reading and writing from the CPU | |
1059 | * perspective, requiring manual detiling by the client. | |
1060 | */ | |
71acb5eb | 1061 | if (obj_priv->phys_obj) |
fbd5a26d | 1062 | ret = i915_gem_phys_pwrite(dev, obj, args, file); |
71acb5eb | 1063 | else if (obj_priv->tiling_mode == I915_TILING_NONE && |
5cdf5881 | 1064 | obj_priv->gtt_space && |
9b8c4a0b | 1065 | obj->write_domain != I915_GEM_DOMAIN_CPU) { |
75e9e915 | 1066 | ret = i915_gem_object_pin(obj, 0, true); |
fbd5a26d CW |
1067 | if (ret) |
1068 | goto out; | |
1069 | ||
1070 | ret = i915_gem_object_set_to_gtt_domain(obj, 1); | |
1071 | if (ret) | |
1072 | goto out_unpin; | |
1073 | ||
1074 | ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file); | |
1075 | if (ret == -EFAULT) | |
1076 | ret = i915_gem_gtt_pwrite_slow(dev, obj, args, file); | |
1077 | ||
1078 | out_unpin: | |
1079 | i915_gem_object_unpin(obj); | |
40123c1f | 1080 | } else { |
fbd5a26d CW |
1081 | ret = i915_gem_object_set_to_cpu_domain(obj, 1); |
1082 | if (ret) | |
e5281ccd | 1083 | goto out; |
673a394b | 1084 | |
fbd5a26d CW |
1085 | ret = -EFAULT; |
1086 | if (!i915_gem_object_needs_bit17_swizzle(obj)) | |
1087 | ret = i915_gem_shmem_pwrite_fast(dev, obj, args, file); | |
1088 | if (ret == -EFAULT) | |
1089 | ret = i915_gem_shmem_pwrite_slow(dev, obj, args, file); | |
fbd5a26d | 1090 | } |
673a394b | 1091 | |
35b62a89 | 1092 | out: |
fbd5a26d | 1093 | drm_gem_object_unreference(obj); |
1d7cfea1 | 1094 | unlock: |
fbd5a26d | 1095 | mutex_unlock(&dev->struct_mutex); |
673a394b EA |
1096 | return ret; |
1097 | } | |
1098 | ||
1099 | /** | |
2ef7eeaa EA |
1100 | * Called when user space prepares to use an object with the CPU, either |
1101 | * through the mmap ioctl's mapping or a GTT mapping. | |
673a394b EA |
1102 | */ |
1103 | int | |
1104 | i915_gem_set_domain_ioctl(struct drm_device *dev, void *data, | |
1105 | struct drm_file *file_priv) | |
1106 | { | |
a09ba7fa | 1107 | struct drm_i915_private *dev_priv = dev->dev_private; |
673a394b EA |
1108 | struct drm_i915_gem_set_domain *args = data; |
1109 | struct drm_gem_object *obj; | |
652c393a | 1110 | struct drm_i915_gem_object *obj_priv; |
2ef7eeaa EA |
1111 | uint32_t read_domains = args->read_domains; |
1112 | uint32_t write_domain = args->write_domain; | |
673a394b EA |
1113 | int ret; |
1114 | ||
1115 | if (!(dev->driver->driver_features & DRIVER_GEM)) | |
1116 | return -ENODEV; | |
1117 | ||
2ef7eeaa | 1118 | /* Only handle setting domains to types used by the CPU. */ |
21d509e3 | 1119 | if (write_domain & I915_GEM_GPU_DOMAINS) |
2ef7eeaa EA |
1120 | return -EINVAL; |
1121 | ||
21d509e3 | 1122 | if (read_domains & I915_GEM_GPU_DOMAINS) |
2ef7eeaa EA |
1123 | return -EINVAL; |
1124 | ||
1125 | /* Having something in the write domain implies it's in the read | |
1126 | * domain, and only that read domain. Enforce that in the request. | |
1127 | */ | |
1128 | if (write_domain != 0 && read_domains != write_domain) | |
1129 | return -EINVAL; | |
1130 | ||
76c1dec1 | 1131 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 1132 | if (ret) |
76c1dec1 | 1133 | return ret; |
1d7cfea1 | 1134 | |
673a394b | 1135 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); |
1d7cfea1 CW |
1136 | if (obj == NULL) { |
1137 | ret = -ENOENT; | |
1138 | goto unlock; | |
76c1dec1 | 1139 | } |
23010e43 | 1140 | obj_priv = to_intel_bo(obj); |
673a394b | 1141 | |
652c393a JB |
1142 | intel_mark_busy(dev, obj); |
1143 | ||
2ef7eeaa EA |
1144 | if (read_domains & I915_GEM_DOMAIN_GTT) { |
1145 | ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0); | |
02354392 | 1146 | |
a09ba7fa EA |
1147 | /* Update the LRU on the fence for the CPU access that's |
1148 | * about to occur. | |
1149 | */ | |
1150 | if (obj_priv->fence_reg != I915_FENCE_REG_NONE) { | |
007cc8ac DV |
1151 | struct drm_i915_fence_reg *reg = |
1152 | &dev_priv->fence_regs[obj_priv->fence_reg]; | |
1153 | list_move_tail(®->lru_list, | |
a09ba7fa EA |
1154 | &dev_priv->mm.fence_list); |
1155 | } | |
1156 | ||
02354392 EA |
1157 | /* Silently promote "you're not bound, there was nothing to do" |
1158 | * to success, since the client was just asking us to | |
1159 | * make sure everything was done. | |
1160 | */ | |
1161 | if (ret == -EINVAL) | |
1162 | ret = 0; | |
2ef7eeaa | 1163 | } else { |
e47c68e9 | 1164 | ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0); |
2ef7eeaa EA |
1165 | } |
1166 | ||
7d1c4804 CW |
1167 | /* Maintain LRU order of "inactive" objects */ |
1168 | if (ret == 0 && i915_gem_object_is_inactive(obj_priv)) | |
69dc4987 | 1169 | list_move_tail(&obj_priv->mm_list, &dev_priv->mm.inactive_list); |
7d1c4804 | 1170 | |
673a394b | 1171 | drm_gem_object_unreference(obj); |
1d7cfea1 | 1172 | unlock: |
673a394b EA |
1173 | mutex_unlock(&dev->struct_mutex); |
1174 | return ret; | |
1175 | } | |
1176 | ||
1177 | /** | |
1178 | * Called when user space has done writes to this buffer | |
1179 | */ | |
1180 | int | |
1181 | i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data, | |
1182 | struct drm_file *file_priv) | |
1183 | { | |
1184 | struct drm_i915_gem_sw_finish *args = data; | |
1185 | struct drm_gem_object *obj; | |
673a394b EA |
1186 | int ret = 0; |
1187 | ||
1188 | if (!(dev->driver->driver_features & DRIVER_GEM)) | |
1189 | return -ENODEV; | |
1190 | ||
76c1dec1 | 1191 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 1192 | if (ret) |
76c1dec1 | 1193 | return ret; |
1d7cfea1 | 1194 | |
673a394b EA |
1195 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); |
1196 | if (obj == NULL) { | |
1d7cfea1 CW |
1197 | ret = -ENOENT; |
1198 | goto unlock; | |
673a394b EA |
1199 | } |
1200 | ||
673a394b | 1201 | /* Pinned buffers may be scanout, so flush the cache */ |
3d2a812a | 1202 | if (to_intel_bo(obj)->pin_count) |
e47c68e9 EA |
1203 | i915_gem_object_flush_cpu_write_domain(obj); |
1204 | ||
673a394b | 1205 | drm_gem_object_unreference(obj); |
1d7cfea1 | 1206 | unlock: |
673a394b EA |
1207 | mutex_unlock(&dev->struct_mutex); |
1208 | return ret; | |
1209 | } | |
1210 | ||
1211 | /** | |
1212 | * Maps the contents of an object, returning the address it is mapped | |
1213 | * into. | |
1214 | * | |
1215 | * While the mapping holds a reference on the contents of the object, it doesn't | |
1216 | * imply a ref on the object itself. | |
1217 | */ | |
1218 | int | |
1219 | i915_gem_mmap_ioctl(struct drm_device *dev, void *data, | |
1220 | struct drm_file *file_priv) | |
1221 | { | |
da761a6e | 1222 | struct drm_i915_private *dev_priv = dev->dev_private; |
673a394b EA |
1223 | struct drm_i915_gem_mmap *args = data; |
1224 | struct drm_gem_object *obj; | |
1225 | loff_t offset; | |
1226 | unsigned long addr; | |
1227 | ||
1228 | if (!(dev->driver->driver_features & DRIVER_GEM)) | |
1229 | return -ENODEV; | |
1230 | ||
1231 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); | |
1232 | if (obj == NULL) | |
bf79cb91 | 1233 | return -ENOENT; |
673a394b | 1234 | |
da761a6e CW |
1235 | if (obj->size > dev_priv->mm.gtt_mappable_end) { |
1236 | drm_gem_object_unreference_unlocked(obj); | |
1237 | return -E2BIG; | |
1238 | } | |
1239 | ||
673a394b EA |
1240 | offset = args->offset; |
1241 | ||
1242 | down_write(¤t->mm->mmap_sem); | |
1243 | addr = do_mmap(obj->filp, 0, args->size, | |
1244 | PROT_READ | PROT_WRITE, MAP_SHARED, | |
1245 | args->offset); | |
1246 | up_write(¤t->mm->mmap_sem); | |
bc9025bd | 1247 | drm_gem_object_unreference_unlocked(obj); |
673a394b EA |
1248 | if (IS_ERR((void *)addr)) |
1249 | return addr; | |
1250 | ||
1251 | args->addr_ptr = (uint64_t) addr; | |
1252 | ||
1253 | return 0; | |
1254 | } | |
1255 | ||
de151cf6 JB |
1256 | /** |
1257 | * i915_gem_fault - fault a page into the GTT | |
1258 | * vma: VMA in question | |
1259 | * vmf: fault info | |
1260 | * | |
1261 | * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped | |
1262 | * from userspace. The fault handler takes care of binding the object to | |
1263 | * the GTT (if needed), allocating and programming a fence register (again, | |
1264 | * only if needed based on whether the old reg is still valid or the object | |
1265 | * is tiled) and inserting a new PTE into the faulting process. | |
1266 | * | |
1267 | * Note that the faulting process may involve evicting existing objects | |
1268 | * from the GTT and/or fence registers to make room. So performance may | |
1269 | * suffer if the GTT working set is large or there are few fence registers | |
1270 | * left. | |
1271 | */ | |
1272 | int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf) | |
1273 | { | |
1274 | struct drm_gem_object *obj = vma->vm_private_data; | |
1275 | struct drm_device *dev = obj->dev; | |
7d1c4804 | 1276 | drm_i915_private_t *dev_priv = dev->dev_private; |
23010e43 | 1277 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
de151cf6 JB |
1278 | pgoff_t page_offset; |
1279 | unsigned long pfn; | |
1280 | int ret = 0; | |
0f973f27 | 1281 | bool write = !!(vmf->flags & FAULT_FLAG_WRITE); |
de151cf6 JB |
1282 | |
1283 | /* We don't use vmf->pgoff since that has the fake offset */ | |
1284 | page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >> | |
1285 | PAGE_SHIFT; | |
1286 | ||
1287 | /* Now bind it into the GTT if needed */ | |
1288 | mutex_lock(&dev->struct_mutex); | |
fb7d516a | 1289 | BUG_ON(obj_priv->pin_count && !obj_priv->pin_mappable); |
a00b10c3 CW |
1290 | |
1291 | if (obj_priv->gtt_space) { | |
75e9e915 | 1292 | if (!obj_priv->map_and_fenceable) { |
a00b10c3 CW |
1293 | ret = i915_gem_object_unbind(obj); |
1294 | if (ret) | |
1295 | goto unlock; | |
1296 | } | |
1297 | } | |
16e809ac | 1298 | |
de151cf6 | 1299 | if (!obj_priv->gtt_space) { |
75e9e915 | 1300 | ret = i915_gem_object_bind_to_gtt(obj, 0, true); |
c715089f CW |
1301 | if (ret) |
1302 | goto unlock; | |
de151cf6 JB |
1303 | } |
1304 | ||
4a684a41 CW |
1305 | ret = i915_gem_object_set_to_gtt_domain(obj, write); |
1306 | if (ret) | |
1307 | goto unlock; | |
1308 | ||
fb7d516a DV |
1309 | if (!obj_priv->fault_mappable) { |
1310 | obj_priv->fault_mappable = true; | |
a00b10c3 | 1311 | i915_gem_info_update_mappable(dev_priv, obj_priv, true); |
fb7d516a DV |
1312 | } |
1313 | ||
de151cf6 | 1314 | /* Need a new fence register? */ |
a09ba7fa | 1315 | if (obj_priv->tiling_mode != I915_TILING_NONE) { |
2cf34d7b | 1316 | ret = i915_gem_object_get_fence_reg(obj, true); |
c715089f CW |
1317 | if (ret) |
1318 | goto unlock; | |
d9ddcb96 | 1319 | } |
de151cf6 | 1320 | |
7d1c4804 | 1321 | if (i915_gem_object_is_inactive(obj_priv)) |
69dc4987 | 1322 | list_move_tail(&obj_priv->mm_list, &dev_priv->mm.inactive_list); |
7d1c4804 | 1323 | |
de151cf6 JB |
1324 | pfn = ((dev->agp->base + obj_priv->gtt_offset) >> PAGE_SHIFT) + |
1325 | page_offset; | |
1326 | ||
1327 | /* Finally, remap it using the new GTT offset */ | |
1328 | ret = vm_insert_pfn(vma, (unsigned long)vmf->virtual_address, pfn); | |
c715089f | 1329 | unlock: |
de151cf6 JB |
1330 | mutex_unlock(&dev->struct_mutex); |
1331 | ||
1332 | switch (ret) { | |
045e769a CW |
1333 | case -EAGAIN: |
1334 | set_need_resched(); | |
c715089f CW |
1335 | case 0: |
1336 | case -ERESTARTSYS: | |
1337 | return VM_FAULT_NOPAGE; | |
de151cf6 | 1338 | case -ENOMEM: |
de151cf6 | 1339 | return VM_FAULT_OOM; |
de151cf6 | 1340 | default: |
c715089f | 1341 | return VM_FAULT_SIGBUS; |
de151cf6 JB |
1342 | } |
1343 | } | |
1344 | ||
1345 | /** | |
1346 | * i915_gem_create_mmap_offset - create a fake mmap offset for an object | |
1347 | * @obj: obj in question | |
1348 | * | |
1349 | * GEM memory mapping works by handing back to userspace a fake mmap offset | |
1350 | * it can use in a subsequent mmap(2) call. The DRM core code then looks | |
1351 | * up the object based on the offset and sets up the various memory mapping | |
1352 | * structures. | |
1353 | * | |
1354 | * This routine allocates and attaches a fake offset for @obj. | |
1355 | */ | |
1356 | static int | |
1357 | i915_gem_create_mmap_offset(struct drm_gem_object *obj) | |
1358 | { | |
1359 | struct drm_device *dev = obj->dev; | |
1360 | struct drm_gem_mm *mm = dev->mm_private; | |
de151cf6 | 1361 | struct drm_map_list *list; |
f77d390c | 1362 | struct drm_local_map *map; |
de151cf6 JB |
1363 | int ret = 0; |
1364 | ||
1365 | /* Set the object up for mmap'ing */ | |
1366 | list = &obj->map_list; | |
9a298b2a | 1367 | list->map = kzalloc(sizeof(struct drm_map_list), GFP_KERNEL); |
de151cf6 JB |
1368 | if (!list->map) |
1369 | return -ENOMEM; | |
1370 | ||
1371 | map = list->map; | |
1372 | map->type = _DRM_GEM; | |
1373 | map->size = obj->size; | |
1374 | map->handle = obj; | |
1375 | ||
1376 | /* Get a DRM GEM mmap offset allocated... */ | |
1377 | list->file_offset_node = drm_mm_search_free(&mm->offset_manager, | |
1378 | obj->size / PAGE_SIZE, 0, 0); | |
1379 | if (!list->file_offset_node) { | |
1380 | DRM_ERROR("failed to allocate offset for bo %d\n", obj->name); | |
9e0ae534 | 1381 | ret = -ENOSPC; |
de151cf6 JB |
1382 | goto out_free_list; |
1383 | } | |
1384 | ||
1385 | list->file_offset_node = drm_mm_get_block(list->file_offset_node, | |
1386 | obj->size / PAGE_SIZE, 0); | |
1387 | if (!list->file_offset_node) { | |
1388 | ret = -ENOMEM; | |
1389 | goto out_free_list; | |
1390 | } | |
1391 | ||
1392 | list->hash.key = list->file_offset_node->start; | |
9e0ae534 CW |
1393 | ret = drm_ht_insert_item(&mm->offset_hash, &list->hash); |
1394 | if (ret) { | |
de151cf6 JB |
1395 | DRM_ERROR("failed to add to map hash\n"); |
1396 | goto out_free_mm; | |
1397 | } | |
1398 | ||
de151cf6 JB |
1399 | return 0; |
1400 | ||
1401 | out_free_mm: | |
1402 | drm_mm_put_block(list->file_offset_node); | |
1403 | out_free_list: | |
9a298b2a | 1404 | kfree(list->map); |
39a01d1f | 1405 | list->map = NULL; |
de151cf6 JB |
1406 | |
1407 | return ret; | |
1408 | } | |
1409 | ||
901782b2 CW |
1410 | /** |
1411 | * i915_gem_release_mmap - remove physical page mappings | |
1412 | * @obj: obj in question | |
1413 | * | |
af901ca1 | 1414 | * Preserve the reservation of the mmapping with the DRM core code, but |
901782b2 CW |
1415 | * relinquish ownership of the pages back to the system. |
1416 | * | |
1417 | * It is vital that we remove the page mapping if we have mapped a tiled | |
1418 | * object through the GTT and then lose the fence register due to | |
1419 | * resource pressure. Similarly if the object has been moved out of the | |
1420 | * aperture, than pages mapped into userspace must be revoked. Removing the | |
1421 | * mapping will then trigger a page fault on the next user access, allowing | |
1422 | * fixup by i915_gem_fault(). | |
1423 | */ | |
d05ca301 | 1424 | void |
901782b2 CW |
1425 | i915_gem_release_mmap(struct drm_gem_object *obj) |
1426 | { | |
1427 | struct drm_device *dev = obj->dev; | |
fb7d516a | 1428 | struct drm_i915_private *dev_priv = dev->dev_private; |
23010e43 | 1429 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
901782b2 | 1430 | |
39a01d1f | 1431 | if (unlikely(obj->map_list.map && dev->dev_mapping)) |
901782b2 | 1432 | unmap_mapping_range(dev->dev_mapping, |
39a01d1f CW |
1433 | (loff_t)obj->map_list.hash.key<<PAGE_SHIFT, |
1434 | obj->size, 1); | |
fb7d516a DV |
1435 | |
1436 | if (obj_priv->fault_mappable) { | |
1437 | obj_priv->fault_mappable = false; | |
a00b10c3 | 1438 | i915_gem_info_update_mappable(dev_priv, obj_priv, false); |
fb7d516a | 1439 | } |
901782b2 CW |
1440 | } |
1441 | ||
ab00b3e5 JB |
1442 | static void |
1443 | i915_gem_free_mmap_offset(struct drm_gem_object *obj) | |
1444 | { | |
1445 | struct drm_device *dev = obj->dev; | |
ab00b3e5 | 1446 | struct drm_gem_mm *mm = dev->mm_private; |
39a01d1f | 1447 | struct drm_map_list *list = &obj->map_list; |
ab00b3e5 | 1448 | |
ab00b3e5 | 1449 | drm_ht_remove_item(&mm->offset_hash, &list->hash); |
39a01d1f CW |
1450 | drm_mm_put_block(list->file_offset_node); |
1451 | kfree(list->map); | |
1452 | list->map = NULL; | |
ab00b3e5 JB |
1453 | } |
1454 | ||
de151cf6 JB |
1455 | /** |
1456 | * i915_gem_get_gtt_alignment - return required GTT alignment for an object | |
1457 | * @obj: object to check | |
1458 | * | |
1459 | * Return the required GTT alignment for an object, taking into account | |
5e783301 | 1460 | * potential fence register mapping. |
de151cf6 JB |
1461 | */ |
1462 | static uint32_t | |
a00b10c3 | 1463 | i915_gem_get_gtt_alignment(struct drm_i915_gem_object *obj_priv) |
de151cf6 | 1464 | { |
a00b10c3 | 1465 | struct drm_device *dev = obj_priv->base.dev; |
de151cf6 JB |
1466 | |
1467 | /* | |
1468 | * Minimum alignment is 4k (GTT page size), but might be greater | |
1469 | * if a fence register is needed for the object. | |
1470 | */ | |
a00b10c3 CW |
1471 | if (INTEL_INFO(dev)->gen >= 4 || |
1472 | obj_priv->tiling_mode == I915_TILING_NONE) | |
de151cf6 JB |
1473 | return 4096; |
1474 | ||
a00b10c3 CW |
1475 | /* |
1476 | * Previous chips need to be aligned to the size of the smallest | |
1477 | * fence register that can contain the object. | |
1478 | */ | |
1479 | return i915_gem_get_gtt_size(obj_priv); | |
1480 | } | |
1481 | ||
5e783301 DV |
1482 | /** |
1483 | * i915_gem_get_unfenced_gtt_alignment - return required GTT alignment for an | |
1484 | * unfenced object | |
1485 | * @obj: object to check | |
1486 | * | |
1487 | * Return the required GTT alignment for an object, only taking into account | |
1488 | * unfenced tiled surface requirements. | |
1489 | */ | |
1490 | static uint32_t | |
1491 | i915_gem_get_unfenced_gtt_alignment(struct drm_i915_gem_object *obj_priv) | |
1492 | { | |
1493 | struct drm_device *dev = obj_priv->base.dev; | |
1494 | int tile_height; | |
1495 | ||
1496 | /* | |
1497 | * Minimum alignment is 4k (GTT page size) for sane hw. | |
1498 | */ | |
1499 | if (INTEL_INFO(dev)->gen >= 4 || IS_G33(dev) || | |
1500 | obj_priv->tiling_mode == I915_TILING_NONE) | |
1501 | return 4096; | |
1502 | ||
1503 | /* | |
1504 | * Older chips need unfenced tiled buffers to be aligned to the left | |
1505 | * edge of an even tile row (where tile rows are counted as if the bo is | |
1506 | * placed in a fenced gtt region). | |
1507 | */ | |
1508 | if (IS_GEN2(dev) || | |
1509 | (obj_priv->tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev))) | |
1510 | tile_height = 32; | |
1511 | else | |
1512 | tile_height = 8; | |
1513 | ||
1514 | return tile_height * obj_priv->stride * 2; | |
1515 | } | |
1516 | ||
a00b10c3 CW |
1517 | static uint32_t |
1518 | i915_gem_get_gtt_size(struct drm_i915_gem_object *obj_priv) | |
1519 | { | |
1520 | struct drm_device *dev = obj_priv->base.dev; | |
1521 | uint32_t size; | |
1522 | ||
1523 | /* | |
1524 | * Minimum alignment is 4k (GTT page size), but might be greater | |
1525 | * if a fence register is needed for the object. | |
1526 | */ | |
1527 | if (INTEL_INFO(dev)->gen >= 4) | |
1528 | return obj_priv->base.size; | |
1529 | ||
de151cf6 JB |
1530 | /* |
1531 | * Previous chips need to be aligned to the size of the smallest | |
1532 | * fence register that can contain the object. | |
1533 | */ | |
a6c45cf0 | 1534 | if (INTEL_INFO(dev)->gen == 3) |
a00b10c3 | 1535 | size = 1024*1024; |
de151cf6 | 1536 | else |
a00b10c3 | 1537 | size = 512*1024; |
de151cf6 | 1538 | |
a00b10c3 CW |
1539 | while (size < obj_priv->base.size) |
1540 | size <<= 1; | |
de151cf6 | 1541 | |
a00b10c3 | 1542 | return size; |
de151cf6 JB |
1543 | } |
1544 | ||
1545 | /** | |
1546 | * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing | |
1547 | * @dev: DRM device | |
1548 | * @data: GTT mapping ioctl data | |
1549 | * @file_priv: GEM object info | |
1550 | * | |
1551 | * Simply returns the fake offset to userspace so it can mmap it. | |
1552 | * The mmap call will end up in drm_gem_mmap(), which will set things | |
1553 | * up so we can get faults in the handler above. | |
1554 | * | |
1555 | * The fault handler will take care of binding the object into the GTT | |
1556 | * (since it may have been evicted to make room for something), allocating | |
1557 | * a fence register, and mapping the appropriate aperture address into | |
1558 | * userspace. | |
1559 | */ | |
1560 | int | |
1561 | i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data, | |
1562 | struct drm_file *file_priv) | |
1563 | { | |
da761a6e | 1564 | struct drm_i915_private *dev_priv = dev->dev_private; |
de151cf6 | 1565 | struct drm_i915_gem_mmap_gtt *args = data; |
de151cf6 JB |
1566 | struct drm_gem_object *obj; |
1567 | struct drm_i915_gem_object *obj_priv; | |
1568 | int ret; | |
1569 | ||
1570 | if (!(dev->driver->driver_features & DRIVER_GEM)) | |
1571 | return -ENODEV; | |
1572 | ||
76c1dec1 | 1573 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 1574 | if (ret) |
76c1dec1 | 1575 | return ret; |
de151cf6 | 1576 | |
1d7cfea1 CW |
1577 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); |
1578 | if (obj == NULL) { | |
1579 | ret = -ENOENT; | |
1580 | goto unlock; | |
1581 | } | |
23010e43 | 1582 | obj_priv = to_intel_bo(obj); |
de151cf6 | 1583 | |
da761a6e CW |
1584 | if (obj->size > dev_priv->mm.gtt_mappable_end) { |
1585 | ret = -E2BIG; | |
1586 | goto unlock; | |
1587 | } | |
1588 | ||
ab18282d CW |
1589 | if (obj_priv->madv != I915_MADV_WILLNEED) { |
1590 | DRM_ERROR("Attempting to mmap a purgeable buffer\n"); | |
1d7cfea1 CW |
1591 | ret = -EINVAL; |
1592 | goto out; | |
ab18282d CW |
1593 | } |
1594 | ||
39a01d1f | 1595 | if (!obj->map_list.map) { |
de151cf6 | 1596 | ret = i915_gem_create_mmap_offset(obj); |
1d7cfea1 CW |
1597 | if (ret) |
1598 | goto out; | |
de151cf6 JB |
1599 | } |
1600 | ||
39a01d1f | 1601 | args->offset = (u64)obj->map_list.hash.key << PAGE_SHIFT; |
de151cf6 | 1602 | |
1d7cfea1 | 1603 | out: |
de151cf6 | 1604 | drm_gem_object_unreference(obj); |
1d7cfea1 | 1605 | unlock: |
de151cf6 | 1606 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 1607 | return ret; |
de151cf6 JB |
1608 | } |
1609 | ||
e5281ccd CW |
1610 | static int |
1611 | i915_gem_object_get_pages_gtt(struct drm_gem_object *obj, | |
1612 | gfp_t gfpmask) | |
1613 | { | |
1614 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); | |
1615 | int page_count, i; | |
1616 | struct address_space *mapping; | |
1617 | struct inode *inode; | |
1618 | struct page *page; | |
1619 | ||
1620 | /* Get the list of pages out of our struct file. They'll be pinned | |
1621 | * at this point until we release them. | |
1622 | */ | |
1623 | page_count = obj->size / PAGE_SIZE; | |
1624 | BUG_ON(obj_priv->pages != NULL); | |
1625 | obj_priv->pages = drm_malloc_ab(page_count, sizeof(struct page *)); | |
1626 | if (obj_priv->pages == NULL) | |
1627 | return -ENOMEM; | |
1628 | ||
1629 | inode = obj->filp->f_path.dentry->d_inode; | |
1630 | mapping = inode->i_mapping; | |
1631 | for (i = 0; i < page_count; i++) { | |
1632 | page = read_cache_page_gfp(mapping, i, | |
1633 | GFP_HIGHUSER | | |
1634 | __GFP_COLD | | |
1635 | __GFP_RECLAIMABLE | | |
1636 | gfpmask); | |
1637 | if (IS_ERR(page)) | |
1638 | goto err_pages; | |
1639 | ||
1640 | obj_priv->pages[i] = page; | |
1641 | } | |
1642 | ||
1643 | if (obj_priv->tiling_mode != I915_TILING_NONE) | |
1644 | i915_gem_object_do_bit_17_swizzle(obj); | |
1645 | ||
1646 | return 0; | |
1647 | ||
1648 | err_pages: | |
1649 | while (i--) | |
1650 | page_cache_release(obj_priv->pages[i]); | |
1651 | ||
1652 | drm_free_large(obj_priv->pages); | |
1653 | obj_priv->pages = NULL; | |
1654 | return PTR_ERR(page); | |
1655 | } | |
1656 | ||
5cdf5881 | 1657 | static void |
e5281ccd | 1658 | i915_gem_object_put_pages_gtt(struct drm_gem_object *obj) |
673a394b | 1659 | { |
23010e43 | 1660 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
673a394b EA |
1661 | int page_count = obj->size / PAGE_SIZE; |
1662 | int i; | |
1663 | ||
bb6baf76 | 1664 | BUG_ON(obj_priv->madv == __I915_MADV_PURGED); |
673a394b | 1665 | |
280b713b EA |
1666 | if (obj_priv->tiling_mode != I915_TILING_NONE) |
1667 | i915_gem_object_save_bit_17_swizzle(obj); | |
1668 | ||
3ef94daa | 1669 | if (obj_priv->madv == I915_MADV_DONTNEED) |
13a05fd9 | 1670 | obj_priv->dirty = 0; |
3ef94daa CW |
1671 | |
1672 | for (i = 0; i < page_count; i++) { | |
3ef94daa CW |
1673 | if (obj_priv->dirty) |
1674 | set_page_dirty(obj_priv->pages[i]); | |
1675 | ||
1676 | if (obj_priv->madv == I915_MADV_WILLNEED) | |
856fa198 | 1677 | mark_page_accessed(obj_priv->pages[i]); |
3ef94daa CW |
1678 | |
1679 | page_cache_release(obj_priv->pages[i]); | |
1680 | } | |
673a394b EA |
1681 | obj_priv->dirty = 0; |
1682 | ||
8e7d2b2c | 1683 | drm_free_large(obj_priv->pages); |
856fa198 | 1684 | obj_priv->pages = NULL; |
673a394b EA |
1685 | } |
1686 | ||
a56ba56c CW |
1687 | static uint32_t |
1688 | i915_gem_next_request_seqno(struct drm_device *dev, | |
1689 | struct intel_ring_buffer *ring) | |
1690 | { | |
1691 | drm_i915_private_t *dev_priv = dev->dev_private; | |
5d97eb69 | 1692 | return ring->outstanding_lazy_request = dev_priv->next_seqno; |
a56ba56c CW |
1693 | } |
1694 | ||
673a394b | 1695 | static void |
617dbe27 | 1696 | i915_gem_object_move_to_active(struct drm_gem_object *obj, |
852835f3 | 1697 | struct intel_ring_buffer *ring) |
673a394b EA |
1698 | { |
1699 | struct drm_device *dev = obj->dev; | |
69dc4987 | 1700 | struct drm_i915_private *dev_priv = dev->dev_private; |
23010e43 | 1701 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
a56ba56c | 1702 | uint32_t seqno = i915_gem_next_request_seqno(dev, ring); |
617dbe27 | 1703 | |
852835f3 ZN |
1704 | BUG_ON(ring == NULL); |
1705 | obj_priv->ring = ring; | |
673a394b EA |
1706 | |
1707 | /* Add a reference if we're newly entering the active list. */ | |
1708 | if (!obj_priv->active) { | |
1709 | drm_gem_object_reference(obj); | |
1710 | obj_priv->active = 1; | |
1711 | } | |
e35a41de | 1712 | |
673a394b | 1713 | /* Move from whatever list we were on to the tail of execution. */ |
69dc4987 CW |
1714 | list_move_tail(&obj_priv->mm_list, &dev_priv->mm.active_list); |
1715 | list_move_tail(&obj_priv->ring_list, &ring->active_list); | |
ce44b0ea | 1716 | obj_priv->last_rendering_seqno = seqno; |
673a394b EA |
1717 | } |
1718 | ||
ce44b0ea EA |
1719 | static void |
1720 | i915_gem_object_move_to_flushing(struct drm_gem_object *obj) | |
1721 | { | |
1722 | struct drm_device *dev = obj->dev; | |
1723 | drm_i915_private_t *dev_priv = dev->dev_private; | |
23010e43 | 1724 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
ce44b0ea EA |
1725 | |
1726 | BUG_ON(!obj_priv->active); | |
69dc4987 CW |
1727 | list_move_tail(&obj_priv->mm_list, &dev_priv->mm.flushing_list); |
1728 | list_del_init(&obj_priv->ring_list); | |
ce44b0ea EA |
1729 | obj_priv->last_rendering_seqno = 0; |
1730 | } | |
673a394b | 1731 | |
963b4836 CW |
1732 | /* Immediately discard the backing storage */ |
1733 | static void | |
1734 | i915_gem_object_truncate(struct drm_gem_object *obj) | |
1735 | { | |
23010e43 | 1736 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
bb6baf76 | 1737 | struct inode *inode; |
963b4836 | 1738 | |
ae9fed6b CW |
1739 | /* Our goal here is to return as much of the memory as |
1740 | * is possible back to the system as we are called from OOM. | |
1741 | * To do this we must instruct the shmfs to drop all of its | |
1742 | * backing pages, *now*. Here we mirror the actions taken | |
1743 | * when by shmem_delete_inode() to release the backing store. | |
1744 | */ | |
bb6baf76 | 1745 | inode = obj->filp->f_path.dentry->d_inode; |
ae9fed6b CW |
1746 | truncate_inode_pages(inode->i_mapping, 0); |
1747 | if (inode->i_op->truncate_range) | |
1748 | inode->i_op->truncate_range(inode, 0, (loff_t)-1); | |
bb6baf76 CW |
1749 | |
1750 | obj_priv->madv = __I915_MADV_PURGED; | |
963b4836 CW |
1751 | } |
1752 | ||
1753 | static inline int | |
1754 | i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj_priv) | |
1755 | { | |
1756 | return obj_priv->madv == I915_MADV_DONTNEED; | |
1757 | } | |
1758 | ||
673a394b EA |
1759 | static void |
1760 | i915_gem_object_move_to_inactive(struct drm_gem_object *obj) | |
1761 | { | |
1762 | struct drm_device *dev = obj->dev; | |
1763 | drm_i915_private_t *dev_priv = dev->dev_private; | |
23010e43 | 1764 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
673a394b | 1765 | |
673a394b | 1766 | if (obj_priv->pin_count != 0) |
69dc4987 | 1767 | list_move_tail(&obj_priv->mm_list, &dev_priv->mm.pinned_list); |
673a394b | 1768 | else |
69dc4987 CW |
1769 | list_move_tail(&obj_priv->mm_list, &dev_priv->mm.inactive_list); |
1770 | list_del_init(&obj_priv->ring_list); | |
673a394b | 1771 | |
99fcb766 DV |
1772 | BUG_ON(!list_empty(&obj_priv->gpu_write_list)); |
1773 | ||
ce44b0ea | 1774 | obj_priv->last_rendering_seqno = 0; |
852835f3 | 1775 | obj_priv->ring = NULL; |
673a394b EA |
1776 | if (obj_priv->active) { |
1777 | obj_priv->active = 0; | |
1778 | drm_gem_object_unreference(obj); | |
1779 | } | |
23bc5982 | 1780 | WARN_ON(i915_verify_lists(dev)); |
673a394b EA |
1781 | } |
1782 | ||
63560396 DV |
1783 | static void |
1784 | i915_gem_process_flushing_list(struct drm_device *dev, | |
8a1a49f9 | 1785 | uint32_t flush_domains, |
852835f3 | 1786 | struct intel_ring_buffer *ring) |
63560396 DV |
1787 | { |
1788 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1789 | struct drm_i915_gem_object *obj_priv, *next; | |
1790 | ||
1791 | list_for_each_entry_safe(obj_priv, next, | |
64193406 | 1792 | &ring->gpu_write_list, |
63560396 | 1793 | gpu_write_list) { |
a8089e84 | 1794 | struct drm_gem_object *obj = &obj_priv->base; |
63560396 | 1795 | |
64193406 | 1796 | if (obj->write_domain & flush_domains) { |
63560396 DV |
1797 | uint32_t old_write_domain = obj->write_domain; |
1798 | ||
1799 | obj->write_domain = 0; | |
1800 | list_del_init(&obj_priv->gpu_write_list); | |
617dbe27 | 1801 | i915_gem_object_move_to_active(obj, ring); |
63560396 DV |
1802 | |
1803 | /* update the fence lru list */ | |
007cc8ac DV |
1804 | if (obj_priv->fence_reg != I915_FENCE_REG_NONE) { |
1805 | struct drm_i915_fence_reg *reg = | |
1806 | &dev_priv->fence_regs[obj_priv->fence_reg]; | |
1807 | list_move_tail(®->lru_list, | |
63560396 | 1808 | &dev_priv->mm.fence_list); |
007cc8ac | 1809 | } |
63560396 DV |
1810 | |
1811 | trace_i915_gem_object_change_domain(obj, | |
1812 | obj->read_domains, | |
1813 | old_write_domain); | |
1814 | } | |
1815 | } | |
1816 | } | |
8187a2b7 | 1817 | |
3cce469c | 1818 | int |
8a1a49f9 | 1819 | i915_add_request(struct drm_device *dev, |
f787a5f5 | 1820 | struct drm_file *file, |
8dc5d147 | 1821 | struct drm_i915_gem_request *request, |
8a1a49f9 | 1822 | struct intel_ring_buffer *ring) |
673a394b EA |
1823 | { |
1824 | drm_i915_private_t *dev_priv = dev->dev_private; | |
f787a5f5 | 1825 | struct drm_i915_file_private *file_priv = NULL; |
673a394b EA |
1826 | uint32_t seqno; |
1827 | int was_empty; | |
3cce469c CW |
1828 | int ret; |
1829 | ||
1830 | BUG_ON(request == NULL); | |
673a394b | 1831 | |
f787a5f5 CW |
1832 | if (file != NULL) |
1833 | file_priv = file->driver_priv; | |
b962442e | 1834 | |
3cce469c CW |
1835 | ret = ring->add_request(ring, &seqno); |
1836 | if (ret) | |
1837 | return ret; | |
673a394b | 1838 | |
a56ba56c | 1839 | ring->outstanding_lazy_request = false; |
673a394b EA |
1840 | |
1841 | request->seqno = seqno; | |
852835f3 | 1842 | request->ring = ring; |
673a394b | 1843 | request->emitted_jiffies = jiffies; |
852835f3 ZN |
1844 | was_empty = list_empty(&ring->request_list); |
1845 | list_add_tail(&request->list, &ring->request_list); | |
1846 | ||
f787a5f5 | 1847 | if (file_priv) { |
1c25595f | 1848 | spin_lock(&file_priv->mm.lock); |
f787a5f5 | 1849 | request->file_priv = file_priv; |
b962442e | 1850 | list_add_tail(&request->client_list, |
f787a5f5 | 1851 | &file_priv->mm.request_list); |
1c25595f | 1852 | spin_unlock(&file_priv->mm.lock); |
b962442e | 1853 | } |
673a394b | 1854 | |
f65d9421 | 1855 | if (!dev_priv->mm.suspended) { |
b3b079db CW |
1856 | mod_timer(&dev_priv->hangcheck_timer, |
1857 | jiffies + msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)); | |
f65d9421 | 1858 | if (was_empty) |
b3b079db CW |
1859 | queue_delayed_work(dev_priv->wq, |
1860 | &dev_priv->mm.retire_work, HZ); | |
f65d9421 | 1861 | } |
3cce469c | 1862 | return 0; |
673a394b EA |
1863 | } |
1864 | ||
1865 | /** | |
1866 | * Command execution barrier | |
1867 | * | |
1868 | * Ensures that all commands in the ring are finished | |
1869 | * before signalling the CPU | |
1870 | */ | |
8a1a49f9 | 1871 | static void |
852835f3 | 1872 | i915_retire_commands(struct drm_device *dev, struct intel_ring_buffer *ring) |
673a394b | 1873 | { |
673a394b | 1874 | uint32_t flush_domains = 0; |
673a394b EA |
1875 | |
1876 | /* The sampler always gets flushed on i965 (sigh) */ | |
a6c45cf0 | 1877 | if (INTEL_INFO(dev)->gen >= 4) |
673a394b | 1878 | flush_domains |= I915_GEM_DOMAIN_SAMPLER; |
852835f3 | 1879 | |
78501eac | 1880 | ring->flush(ring, I915_GEM_DOMAIN_COMMAND, flush_domains); |
673a394b EA |
1881 | } |
1882 | ||
f787a5f5 CW |
1883 | static inline void |
1884 | i915_gem_request_remove_from_client(struct drm_i915_gem_request *request) | |
673a394b | 1885 | { |
1c25595f | 1886 | struct drm_i915_file_private *file_priv = request->file_priv; |
673a394b | 1887 | |
1c25595f CW |
1888 | if (!file_priv) |
1889 | return; | |
1c5d22f7 | 1890 | |
1c25595f CW |
1891 | spin_lock(&file_priv->mm.lock); |
1892 | list_del(&request->client_list); | |
1893 | request->file_priv = NULL; | |
1894 | spin_unlock(&file_priv->mm.lock); | |
673a394b | 1895 | } |
673a394b | 1896 | |
dfaae392 CW |
1897 | static void i915_gem_reset_ring_lists(struct drm_i915_private *dev_priv, |
1898 | struct intel_ring_buffer *ring) | |
9375e446 | 1899 | { |
dfaae392 CW |
1900 | while (!list_empty(&ring->request_list)) { |
1901 | struct drm_i915_gem_request *request; | |
673a394b | 1902 | |
dfaae392 CW |
1903 | request = list_first_entry(&ring->request_list, |
1904 | struct drm_i915_gem_request, | |
1905 | list); | |
de151cf6 | 1906 | |
dfaae392 | 1907 | list_del(&request->list); |
f787a5f5 | 1908 | i915_gem_request_remove_from_client(request); |
dfaae392 CW |
1909 | kfree(request); |
1910 | } | |
673a394b | 1911 | |
dfaae392 | 1912 | while (!list_empty(&ring->active_list)) { |
9375e446 CW |
1913 | struct drm_i915_gem_object *obj_priv; |
1914 | ||
dfaae392 | 1915 | obj_priv = list_first_entry(&ring->active_list, |
9375e446 | 1916 | struct drm_i915_gem_object, |
69dc4987 | 1917 | ring_list); |
9375e446 CW |
1918 | |
1919 | obj_priv->base.write_domain = 0; | |
dfaae392 | 1920 | list_del_init(&obj_priv->gpu_write_list); |
9375e446 | 1921 | i915_gem_object_move_to_inactive(&obj_priv->base); |
673a394b EA |
1922 | } |
1923 | } | |
1924 | ||
069efc1d | 1925 | void i915_gem_reset(struct drm_device *dev) |
673a394b | 1926 | { |
77f01230 CW |
1927 | struct drm_i915_private *dev_priv = dev->dev_private; |
1928 | struct drm_i915_gem_object *obj_priv; | |
069efc1d | 1929 | int i; |
673a394b | 1930 | |
dfaae392 | 1931 | i915_gem_reset_ring_lists(dev_priv, &dev_priv->render_ring); |
87acb0a5 | 1932 | i915_gem_reset_ring_lists(dev_priv, &dev_priv->bsd_ring); |
549f7365 | 1933 | i915_gem_reset_ring_lists(dev_priv, &dev_priv->blt_ring); |
dfaae392 CW |
1934 | |
1935 | /* Remove anything from the flushing lists. The GPU cache is likely | |
1936 | * to be lost on reset along with the data, so simply move the | |
1937 | * lost bo to the inactive list. | |
1938 | */ | |
1939 | while (!list_empty(&dev_priv->mm.flushing_list)) { | |
1940 | obj_priv = list_first_entry(&dev_priv->mm.flushing_list, | |
1941 | struct drm_i915_gem_object, | |
69dc4987 | 1942 | mm_list); |
dfaae392 CW |
1943 | |
1944 | obj_priv->base.write_domain = 0; | |
1945 | list_del_init(&obj_priv->gpu_write_list); | |
1946 | i915_gem_object_move_to_inactive(&obj_priv->base); | |
1947 | } | |
1948 | ||
1949 | /* Move everything out of the GPU domains to ensure we do any | |
1950 | * necessary invalidation upon reuse. | |
1951 | */ | |
77f01230 CW |
1952 | list_for_each_entry(obj_priv, |
1953 | &dev_priv->mm.inactive_list, | |
69dc4987 | 1954 | mm_list) |
77f01230 CW |
1955 | { |
1956 | obj_priv->base.read_domains &= ~I915_GEM_GPU_DOMAINS; | |
1957 | } | |
069efc1d CW |
1958 | |
1959 | /* The fence registers are invalidated so clear them out */ | |
1960 | for (i = 0; i < 16; i++) { | |
1961 | struct drm_i915_fence_reg *reg; | |
1962 | ||
1963 | reg = &dev_priv->fence_regs[i]; | |
1964 | if (!reg->obj) | |
1965 | continue; | |
1966 | ||
1967 | i915_gem_clear_fence_reg(reg->obj); | |
1968 | } | |
673a394b EA |
1969 | } |
1970 | ||
1971 | /** | |
1972 | * This function clears the request list as sequence numbers are passed. | |
1973 | */ | |
b09a1fec CW |
1974 | static void |
1975 | i915_gem_retire_requests_ring(struct drm_device *dev, | |
1976 | struct intel_ring_buffer *ring) | |
673a394b EA |
1977 | { |
1978 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1979 | uint32_t seqno; | |
1980 | ||
b84d5f0c CW |
1981 | if (!ring->status_page.page_addr || |
1982 | list_empty(&ring->request_list)) | |
6c0594a3 KW |
1983 | return; |
1984 | ||
23bc5982 | 1985 | WARN_ON(i915_verify_lists(dev)); |
673a394b | 1986 | |
78501eac | 1987 | seqno = ring->get_seqno(ring); |
852835f3 | 1988 | while (!list_empty(&ring->request_list)) { |
673a394b | 1989 | struct drm_i915_gem_request *request; |
673a394b | 1990 | |
852835f3 | 1991 | request = list_first_entry(&ring->request_list, |
673a394b EA |
1992 | struct drm_i915_gem_request, |
1993 | list); | |
673a394b | 1994 | |
dfaae392 | 1995 | if (!i915_seqno_passed(seqno, request->seqno)) |
b84d5f0c CW |
1996 | break; |
1997 | ||
1998 | trace_i915_gem_request_retire(dev, request->seqno); | |
1999 | ||
2000 | list_del(&request->list); | |
f787a5f5 | 2001 | i915_gem_request_remove_from_client(request); |
b84d5f0c CW |
2002 | kfree(request); |
2003 | } | |
673a394b | 2004 | |
b84d5f0c CW |
2005 | /* Move any buffers on the active list that are no longer referenced |
2006 | * by the ringbuffer to the flushing/inactive lists as appropriate. | |
2007 | */ | |
2008 | while (!list_empty(&ring->active_list)) { | |
2009 | struct drm_gem_object *obj; | |
2010 | struct drm_i915_gem_object *obj_priv; | |
2011 | ||
2012 | obj_priv = list_first_entry(&ring->active_list, | |
2013 | struct drm_i915_gem_object, | |
69dc4987 | 2014 | ring_list); |
673a394b | 2015 | |
dfaae392 | 2016 | if (!i915_seqno_passed(seqno, obj_priv->last_rendering_seqno)) |
673a394b | 2017 | break; |
b84d5f0c CW |
2018 | |
2019 | obj = &obj_priv->base; | |
b84d5f0c CW |
2020 | if (obj->write_domain != 0) |
2021 | i915_gem_object_move_to_flushing(obj); | |
2022 | else | |
2023 | i915_gem_object_move_to_inactive(obj); | |
673a394b | 2024 | } |
9d34e5db CW |
2025 | |
2026 | if (unlikely (dev_priv->trace_irq_seqno && | |
2027 | i915_seqno_passed(dev_priv->trace_irq_seqno, seqno))) { | |
78501eac | 2028 | ring->user_irq_put(ring); |
9d34e5db CW |
2029 | dev_priv->trace_irq_seqno = 0; |
2030 | } | |
23bc5982 CW |
2031 | |
2032 | WARN_ON(i915_verify_lists(dev)); | |
673a394b EA |
2033 | } |
2034 | ||
b09a1fec CW |
2035 | void |
2036 | i915_gem_retire_requests(struct drm_device *dev) | |
2037 | { | |
2038 | drm_i915_private_t *dev_priv = dev->dev_private; | |
2039 | ||
be72615b CW |
2040 | if (!list_empty(&dev_priv->mm.deferred_free_list)) { |
2041 | struct drm_i915_gem_object *obj_priv, *tmp; | |
2042 | ||
2043 | /* We must be careful that during unbind() we do not | |
2044 | * accidentally infinitely recurse into retire requests. | |
2045 | * Currently: | |
2046 | * retire -> free -> unbind -> wait -> retire_ring | |
2047 | */ | |
2048 | list_for_each_entry_safe(obj_priv, tmp, | |
2049 | &dev_priv->mm.deferred_free_list, | |
69dc4987 | 2050 | mm_list) |
be72615b CW |
2051 | i915_gem_free_object_tail(&obj_priv->base); |
2052 | } | |
2053 | ||
b09a1fec | 2054 | i915_gem_retire_requests_ring(dev, &dev_priv->render_ring); |
87acb0a5 | 2055 | i915_gem_retire_requests_ring(dev, &dev_priv->bsd_ring); |
549f7365 | 2056 | i915_gem_retire_requests_ring(dev, &dev_priv->blt_ring); |
b09a1fec CW |
2057 | } |
2058 | ||
75ef9da2 | 2059 | static void |
673a394b EA |
2060 | i915_gem_retire_work_handler(struct work_struct *work) |
2061 | { | |
2062 | drm_i915_private_t *dev_priv; | |
2063 | struct drm_device *dev; | |
2064 | ||
2065 | dev_priv = container_of(work, drm_i915_private_t, | |
2066 | mm.retire_work.work); | |
2067 | dev = dev_priv->dev; | |
2068 | ||
891b48cf CW |
2069 | /* Come back later if the device is busy... */ |
2070 | if (!mutex_trylock(&dev->struct_mutex)) { | |
2071 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ); | |
2072 | return; | |
2073 | } | |
2074 | ||
b09a1fec | 2075 | i915_gem_retire_requests(dev); |
d1b851fc | 2076 | |
6dbe2772 | 2077 | if (!dev_priv->mm.suspended && |
d1b851fc | 2078 | (!list_empty(&dev_priv->render_ring.request_list) || |
549f7365 CW |
2079 | !list_empty(&dev_priv->bsd_ring.request_list) || |
2080 | !list_empty(&dev_priv->blt_ring.request_list))) | |
9c9fe1f8 | 2081 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ); |
673a394b EA |
2082 | mutex_unlock(&dev->struct_mutex); |
2083 | } | |
2084 | ||
5a5a0c64 | 2085 | int |
852835f3 | 2086 | i915_do_wait_request(struct drm_device *dev, uint32_t seqno, |
8a1a49f9 | 2087 | bool interruptible, struct intel_ring_buffer *ring) |
673a394b EA |
2088 | { |
2089 | drm_i915_private_t *dev_priv = dev->dev_private; | |
802c7eb6 | 2090 | u32 ier; |
673a394b EA |
2091 | int ret = 0; |
2092 | ||
2093 | BUG_ON(seqno == 0); | |
2094 | ||
ba1234d1 | 2095 | if (atomic_read(&dev_priv->mm.wedged)) |
30dbf0c0 CW |
2096 | return -EAGAIN; |
2097 | ||
5d97eb69 | 2098 | if (seqno == ring->outstanding_lazy_request) { |
3cce469c CW |
2099 | struct drm_i915_gem_request *request; |
2100 | ||
2101 | request = kzalloc(sizeof(*request), GFP_KERNEL); | |
2102 | if (request == NULL) | |
e35a41de | 2103 | return -ENOMEM; |
3cce469c CW |
2104 | |
2105 | ret = i915_add_request(dev, NULL, request, ring); | |
2106 | if (ret) { | |
2107 | kfree(request); | |
2108 | return ret; | |
2109 | } | |
2110 | ||
2111 | seqno = request->seqno; | |
e35a41de | 2112 | } |
ffed1d09 | 2113 | |
78501eac | 2114 | if (!i915_seqno_passed(ring->get_seqno(ring), seqno)) { |
bad720ff | 2115 | if (HAS_PCH_SPLIT(dev)) |
036a4a7d ZW |
2116 | ier = I915_READ(DEIER) | I915_READ(GTIER); |
2117 | else | |
2118 | ier = I915_READ(IER); | |
802c7eb6 JB |
2119 | if (!ier) { |
2120 | DRM_ERROR("something (likely vbetool) disabled " | |
2121 | "interrupts, re-enabling\n"); | |
2122 | i915_driver_irq_preinstall(dev); | |
2123 | i915_driver_irq_postinstall(dev); | |
2124 | } | |
2125 | ||
1c5d22f7 CW |
2126 | trace_i915_gem_request_wait_begin(dev, seqno); |
2127 | ||
b2223497 | 2128 | ring->waiting_seqno = seqno; |
78501eac | 2129 | ring->user_irq_get(ring); |
48764bf4 | 2130 | if (interruptible) |
852835f3 | 2131 | ret = wait_event_interruptible(ring->irq_queue, |
78501eac | 2132 | i915_seqno_passed(ring->get_seqno(ring), seqno) |
852835f3 | 2133 | || atomic_read(&dev_priv->mm.wedged)); |
48764bf4 | 2134 | else |
852835f3 | 2135 | wait_event(ring->irq_queue, |
78501eac | 2136 | i915_seqno_passed(ring->get_seqno(ring), seqno) |
852835f3 | 2137 | || atomic_read(&dev_priv->mm.wedged)); |
48764bf4 | 2138 | |
78501eac | 2139 | ring->user_irq_put(ring); |
b2223497 | 2140 | ring->waiting_seqno = 0; |
1c5d22f7 CW |
2141 | |
2142 | trace_i915_gem_request_wait_end(dev, seqno); | |
673a394b | 2143 | } |
ba1234d1 | 2144 | if (atomic_read(&dev_priv->mm.wedged)) |
30dbf0c0 | 2145 | ret = -EAGAIN; |
673a394b EA |
2146 | |
2147 | if (ret && ret != -ERESTARTSYS) | |
8bff917c | 2148 | DRM_ERROR("%s returns %d (awaiting %d at %d, next %d)\n", |
78501eac | 2149 | __func__, ret, seqno, ring->get_seqno(ring), |
8bff917c | 2150 | dev_priv->next_seqno); |
673a394b EA |
2151 | |
2152 | /* Directly dispatch request retiring. While we have the work queue | |
2153 | * to handle this, the waiter on a request often wants an associated | |
2154 | * buffer to have made it to the inactive list, and we would need | |
2155 | * a separate wait queue to handle that. | |
2156 | */ | |
2157 | if (ret == 0) | |
b09a1fec | 2158 | i915_gem_retire_requests_ring(dev, ring); |
673a394b EA |
2159 | |
2160 | return ret; | |
2161 | } | |
2162 | ||
48764bf4 DV |
2163 | /** |
2164 | * Waits for a sequence number to be signaled, and cleans up the | |
2165 | * request and object lists appropriately for that event. | |
2166 | */ | |
2167 | static int | |
852835f3 | 2168 | i915_wait_request(struct drm_device *dev, uint32_t seqno, |
a56ba56c | 2169 | struct intel_ring_buffer *ring) |
48764bf4 | 2170 | { |
852835f3 | 2171 | return i915_do_wait_request(dev, seqno, 1, ring); |
48764bf4 DV |
2172 | } |
2173 | ||
20f0cd55 | 2174 | static void |
9220434a | 2175 | i915_gem_flush_ring(struct drm_device *dev, |
c78ec30b | 2176 | struct drm_file *file_priv, |
9220434a CW |
2177 | struct intel_ring_buffer *ring, |
2178 | uint32_t invalidate_domains, | |
2179 | uint32_t flush_domains) | |
2180 | { | |
78501eac | 2181 | ring->flush(ring, invalidate_domains, flush_domains); |
9220434a CW |
2182 | i915_gem_process_flushing_list(dev, flush_domains, ring); |
2183 | } | |
2184 | ||
8187a2b7 ZN |
2185 | static void |
2186 | i915_gem_flush(struct drm_device *dev, | |
c78ec30b | 2187 | struct drm_file *file_priv, |
8187a2b7 | 2188 | uint32_t invalidate_domains, |
9220434a CW |
2189 | uint32_t flush_domains, |
2190 | uint32_t flush_rings) | |
8187a2b7 ZN |
2191 | { |
2192 | drm_i915_private_t *dev_priv = dev->dev_private; | |
8bff917c | 2193 | |
8187a2b7 | 2194 | if (flush_domains & I915_GEM_DOMAIN_CPU) |
40ce6575 | 2195 | intel_gtt_chipset_flush(); |
8bff917c | 2196 | |
9220434a CW |
2197 | if ((flush_domains | invalidate_domains) & I915_GEM_GPU_DOMAINS) { |
2198 | if (flush_rings & RING_RENDER) | |
c78ec30b | 2199 | i915_gem_flush_ring(dev, file_priv, |
9220434a CW |
2200 | &dev_priv->render_ring, |
2201 | invalidate_domains, flush_domains); | |
2202 | if (flush_rings & RING_BSD) | |
c78ec30b | 2203 | i915_gem_flush_ring(dev, file_priv, |
9220434a CW |
2204 | &dev_priv->bsd_ring, |
2205 | invalidate_domains, flush_domains); | |
549f7365 CW |
2206 | if (flush_rings & RING_BLT) |
2207 | i915_gem_flush_ring(dev, file_priv, | |
2208 | &dev_priv->blt_ring, | |
2209 | invalidate_domains, flush_domains); | |
9220434a | 2210 | } |
8187a2b7 ZN |
2211 | } |
2212 | ||
673a394b EA |
2213 | /** |
2214 | * Ensures that all rendering to the object has completed and the object is | |
2215 | * safe to unbind from the GTT or access from the CPU. | |
2216 | */ | |
2217 | static int | |
2cf34d7b CW |
2218 | i915_gem_object_wait_rendering(struct drm_gem_object *obj, |
2219 | bool interruptible) | |
673a394b EA |
2220 | { |
2221 | struct drm_device *dev = obj->dev; | |
23010e43 | 2222 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
673a394b EA |
2223 | int ret; |
2224 | ||
e47c68e9 EA |
2225 | /* This function only exists to support waiting for existing rendering, |
2226 | * not for emitting required flushes. | |
673a394b | 2227 | */ |
e47c68e9 | 2228 | BUG_ON((obj->write_domain & I915_GEM_GPU_DOMAINS) != 0); |
673a394b EA |
2229 | |
2230 | /* If there is rendering queued on the buffer being evicted, wait for | |
2231 | * it. | |
2232 | */ | |
2233 | if (obj_priv->active) { | |
2cf34d7b CW |
2234 | ret = i915_do_wait_request(dev, |
2235 | obj_priv->last_rendering_seqno, | |
2236 | interruptible, | |
2237 | obj_priv->ring); | |
2238 | if (ret) | |
673a394b EA |
2239 | return ret; |
2240 | } | |
2241 | ||
2242 | return 0; | |
2243 | } | |
2244 | ||
2245 | /** | |
2246 | * Unbinds an object from the GTT aperture. | |
2247 | */ | |
0f973f27 | 2248 | int |
673a394b EA |
2249 | i915_gem_object_unbind(struct drm_gem_object *obj) |
2250 | { | |
2251 | struct drm_device *dev = obj->dev; | |
73aa808f | 2252 | struct drm_i915_private *dev_priv = dev->dev_private; |
23010e43 | 2253 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
673a394b EA |
2254 | int ret = 0; |
2255 | ||
673a394b EA |
2256 | if (obj_priv->gtt_space == NULL) |
2257 | return 0; | |
2258 | ||
2259 | if (obj_priv->pin_count != 0) { | |
2260 | DRM_ERROR("Attempting to unbind pinned buffer\n"); | |
2261 | return -EINVAL; | |
2262 | } | |
2263 | ||
5323fd04 EA |
2264 | /* blow away mappings if mapped through GTT */ |
2265 | i915_gem_release_mmap(obj); | |
2266 | ||
673a394b EA |
2267 | /* Move the object to the CPU domain to ensure that |
2268 | * any possible CPU writes while it's not in the GTT | |
2269 | * are flushed when we go to remap it. This will | |
2270 | * also ensure that all pending GPU writes are finished | |
2271 | * before we unbind. | |
2272 | */ | |
e47c68e9 | 2273 | ret = i915_gem_object_set_to_cpu_domain(obj, 1); |
8dc1775d | 2274 | if (ret == -ERESTARTSYS) |
673a394b | 2275 | return ret; |
8dc1775d CW |
2276 | /* Continue on if we fail due to EIO, the GPU is hung so we |
2277 | * should be safe and we need to cleanup or else we might | |
2278 | * cause memory corruption through use-after-free. | |
2279 | */ | |
812ed492 CW |
2280 | if (ret) { |
2281 | i915_gem_clflush_object(obj); | |
2282 | obj->read_domains = obj->write_domain = I915_GEM_DOMAIN_CPU; | |
2283 | } | |
673a394b | 2284 | |
96b47b65 DV |
2285 | /* release the fence reg _after_ flushing */ |
2286 | if (obj_priv->fence_reg != I915_FENCE_REG_NONE) | |
2287 | i915_gem_clear_fence_reg(obj); | |
2288 | ||
73aa808f CW |
2289 | drm_unbind_agp(obj_priv->agp_mem); |
2290 | drm_free_agp(obj_priv->agp_mem, obj->size / PAGE_SIZE); | |
673a394b | 2291 | |
e5281ccd | 2292 | i915_gem_object_put_pages_gtt(obj); |
673a394b | 2293 | |
a00b10c3 | 2294 | i915_gem_info_remove_gtt(dev_priv, obj_priv); |
69dc4987 | 2295 | list_del_init(&obj_priv->mm_list); |
75e9e915 DV |
2296 | /* Avoid an unnecessary call to unbind on rebind. */ |
2297 | obj_priv->map_and_fenceable = true; | |
673a394b | 2298 | |
73aa808f CW |
2299 | drm_mm_put_block(obj_priv->gtt_space); |
2300 | obj_priv->gtt_space = NULL; | |
9af90d19 | 2301 | obj_priv->gtt_offset = 0; |
673a394b | 2302 | |
963b4836 CW |
2303 | if (i915_gem_object_is_purgeable(obj_priv)) |
2304 | i915_gem_object_truncate(obj); | |
2305 | ||
1c5d22f7 CW |
2306 | trace_i915_gem_object_unbind(obj); |
2307 | ||
8dc1775d | 2308 | return ret; |
673a394b EA |
2309 | } |
2310 | ||
a56ba56c CW |
2311 | static int i915_ring_idle(struct drm_device *dev, |
2312 | struct intel_ring_buffer *ring) | |
2313 | { | |
395b70be | 2314 | if (list_empty(&ring->gpu_write_list) && list_empty(&ring->active_list)) |
64193406 CW |
2315 | return 0; |
2316 | ||
a56ba56c CW |
2317 | i915_gem_flush_ring(dev, NULL, ring, |
2318 | I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS); | |
2319 | return i915_wait_request(dev, | |
2320 | i915_gem_next_request_seqno(dev, ring), | |
2321 | ring); | |
2322 | } | |
2323 | ||
b47eb4a2 | 2324 | int |
4df2faf4 DV |
2325 | i915_gpu_idle(struct drm_device *dev) |
2326 | { | |
2327 | drm_i915_private_t *dev_priv = dev->dev_private; | |
2328 | bool lists_empty; | |
852835f3 | 2329 | int ret; |
4df2faf4 | 2330 | |
d1b851fc | 2331 | lists_empty = (list_empty(&dev_priv->mm.flushing_list) && |
395b70be | 2332 | list_empty(&dev_priv->mm.active_list)); |
4df2faf4 DV |
2333 | if (lists_empty) |
2334 | return 0; | |
2335 | ||
2336 | /* Flush everything onto the inactive list. */ | |
a56ba56c | 2337 | ret = i915_ring_idle(dev, &dev_priv->render_ring); |
8a1a49f9 DV |
2338 | if (ret) |
2339 | return ret; | |
d1b851fc | 2340 | |
87acb0a5 CW |
2341 | ret = i915_ring_idle(dev, &dev_priv->bsd_ring); |
2342 | if (ret) | |
2343 | return ret; | |
d1b851fc | 2344 | |
549f7365 CW |
2345 | ret = i915_ring_idle(dev, &dev_priv->blt_ring); |
2346 | if (ret) | |
2347 | return ret; | |
4df2faf4 | 2348 | |
8a1a49f9 | 2349 | return 0; |
4df2faf4 DV |
2350 | } |
2351 | ||
a00b10c3 | 2352 | static void sandybridge_write_fence_reg(struct drm_gem_object *obj) |
4e901fdc | 2353 | { |
4e901fdc EA |
2354 | struct drm_device *dev = obj->dev; |
2355 | drm_i915_private_t *dev_priv = dev->dev_private; | |
23010e43 | 2356 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
a00b10c3 | 2357 | u32 size = i915_gem_get_gtt_size(obj_priv); |
4e901fdc EA |
2358 | int regnum = obj_priv->fence_reg; |
2359 | uint64_t val; | |
2360 | ||
a00b10c3 | 2361 | val = (uint64_t)((obj_priv->gtt_offset + size - 4096) & |
4e901fdc EA |
2362 | 0xfffff000) << 32; |
2363 | val |= obj_priv->gtt_offset & 0xfffff000; | |
2364 | val |= (uint64_t)((obj_priv->stride / 128) - 1) << | |
2365 | SANDYBRIDGE_FENCE_PITCH_SHIFT; | |
2366 | ||
2367 | if (obj_priv->tiling_mode == I915_TILING_Y) | |
2368 | val |= 1 << I965_FENCE_TILING_Y_SHIFT; | |
2369 | val |= I965_FENCE_REG_VALID; | |
2370 | ||
2371 | I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + (regnum * 8), val); | |
2372 | } | |
2373 | ||
a00b10c3 | 2374 | static void i965_write_fence_reg(struct drm_gem_object *obj) |
de151cf6 | 2375 | { |
de151cf6 JB |
2376 | struct drm_device *dev = obj->dev; |
2377 | drm_i915_private_t *dev_priv = dev->dev_private; | |
23010e43 | 2378 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
a00b10c3 | 2379 | u32 size = i915_gem_get_gtt_size(obj_priv); |
de151cf6 JB |
2380 | int regnum = obj_priv->fence_reg; |
2381 | uint64_t val; | |
2382 | ||
a00b10c3 | 2383 | val = (uint64_t)((obj_priv->gtt_offset + size - 4096) & |
de151cf6 JB |
2384 | 0xfffff000) << 32; |
2385 | val |= obj_priv->gtt_offset & 0xfffff000; | |
2386 | val |= ((obj_priv->stride / 128) - 1) << I965_FENCE_PITCH_SHIFT; | |
2387 | if (obj_priv->tiling_mode == I915_TILING_Y) | |
2388 | val |= 1 << I965_FENCE_TILING_Y_SHIFT; | |
2389 | val |= I965_FENCE_REG_VALID; | |
2390 | ||
2391 | I915_WRITE64(FENCE_REG_965_0 + (regnum * 8), val); | |
2392 | } | |
2393 | ||
a00b10c3 | 2394 | static void i915_write_fence_reg(struct drm_gem_object *obj) |
de151cf6 | 2395 | { |
de151cf6 JB |
2396 | struct drm_device *dev = obj->dev; |
2397 | drm_i915_private_t *dev_priv = dev->dev_private; | |
23010e43 | 2398 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
a00b10c3 CW |
2399 | u32 size = i915_gem_get_gtt_size(obj_priv); |
2400 | uint32_t fence_reg, val, pitch_val; | |
0f973f27 | 2401 | int tile_width; |
de151cf6 JB |
2402 | |
2403 | if ((obj_priv->gtt_offset & ~I915_FENCE_START_MASK) || | |
a00b10c3 CW |
2404 | (obj_priv->gtt_offset & (size - 1))) { |
2405 | WARN(1, "%s: object 0x%08x [fenceable? %d] not 1M or size (0x%08x) aligned [gtt_space offset=%lx, size=%lx]\n", | |
75e9e915 | 2406 | __func__, obj_priv->gtt_offset, obj_priv->map_and_fenceable, size, |
a00b10c3 | 2407 | obj_priv->gtt_space->start, obj_priv->gtt_space->size); |
de151cf6 JB |
2408 | return; |
2409 | } | |
2410 | ||
0f973f27 JB |
2411 | if (obj_priv->tiling_mode == I915_TILING_Y && |
2412 | HAS_128_BYTE_Y_TILING(dev)) | |
2413 | tile_width = 128; | |
de151cf6 | 2414 | else |
0f973f27 JB |
2415 | tile_width = 512; |
2416 | ||
2417 | /* Note: pitch better be a power of two tile widths */ | |
2418 | pitch_val = obj_priv->stride / tile_width; | |
2419 | pitch_val = ffs(pitch_val) - 1; | |
de151cf6 | 2420 | |
c36a2a6d DV |
2421 | if (obj_priv->tiling_mode == I915_TILING_Y && |
2422 | HAS_128_BYTE_Y_TILING(dev)) | |
2423 | WARN_ON(pitch_val > I830_FENCE_MAX_PITCH_VAL); | |
2424 | else | |
2425 | WARN_ON(pitch_val > I915_FENCE_MAX_PITCH_VAL); | |
2426 | ||
de151cf6 JB |
2427 | val = obj_priv->gtt_offset; |
2428 | if (obj_priv->tiling_mode == I915_TILING_Y) | |
2429 | val |= 1 << I830_FENCE_TILING_Y_SHIFT; | |
a00b10c3 | 2430 | val |= I915_FENCE_SIZE_BITS(size); |
de151cf6 JB |
2431 | val |= pitch_val << I830_FENCE_PITCH_SHIFT; |
2432 | val |= I830_FENCE_REG_VALID; | |
2433 | ||
a00b10c3 CW |
2434 | fence_reg = obj_priv->fence_reg; |
2435 | if (fence_reg < 8) | |
2436 | fence_reg = FENCE_REG_830_0 + fence_reg * 4; | |
dc529a4f | 2437 | else |
a00b10c3 | 2438 | fence_reg = FENCE_REG_945_8 + (fence_reg - 8) * 4; |
dc529a4f | 2439 | I915_WRITE(fence_reg, val); |
de151cf6 JB |
2440 | } |
2441 | ||
a00b10c3 | 2442 | static void i830_write_fence_reg(struct drm_gem_object *obj) |
de151cf6 | 2443 | { |
de151cf6 JB |
2444 | struct drm_device *dev = obj->dev; |
2445 | drm_i915_private_t *dev_priv = dev->dev_private; | |
23010e43 | 2446 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
a00b10c3 | 2447 | u32 size = i915_gem_get_gtt_size(obj_priv); |
de151cf6 JB |
2448 | int regnum = obj_priv->fence_reg; |
2449 | uint32_t val; | |
2450 | uint32_t pitch_val; | |
8d7773a3 | 2451 | uint32_t fence_size_bits; |
de151cf6 | 2452 | |
8d7773a3 | 2453 | if ((obj_priv->gtt_offset & ~I830_FENCE_START_MASK) || |
de151cf6 | 2454 | (obj_priv->gtt_offset & (obj->size - 1))) { |
8d7773a3 | 2455 | WARN(1, "%s: object 0x%08x not 512K or size aligned\n", |
0f973f27 | 2456 | __func__, obj_priv->gtt_offset); |
de151cf6 JB |
2457 | return; |
2458 | } | |
2459 | ||
e76a16de EA |
2460 | pitch_val = obj_priv->stride / 128; |
2461 | pitch_val = ffs(pitch_val) - 1; | |
2462 | WARN_ON(pitch_val > I830_FENCE_MAX_PITCH_VAL); | |
2463 | ||
de151cf6 JB |
2464 | val = obj_priv->gtt_offset; |
2465 | if (obj_priv->tiling_mode == I915_TILING_Y) | |
2466 | val |= 1 << I830_FENCE_TILING_Y_SHIFT; | |
a00b10c3 | 2467 | fence_size_bits = I830_FENCE_SIZE_BITS(size); |
8d7773a3 DV |
2468 | WARN_ON(fence_size_bits & ~0x00000f00); |
2469 | val |= fence_size_bits; | |
de151cf6 JB |
2470 | val |= pitch_val << I830_FENCE_PITCH_SHIFT; |
2471 | val |= I830_FENCE_REG_VALID; | |
2472 | ||
2473 | I915_WRITE(FENCE_REG_830_0 + (regnum * 4), val); | |
de151cf6 JB |
2474 | } |
2475 | ||
2cf34d7b CW |
2476 | static int i915_find_fence_reg(struct drm_device *dev, |
2477 | bool interruptible) | |
ae3db24a | 2478 | { |
ae3db24a | 2479 | struct drm_i915_private *dev_priv = dev->dev_private; |
a00b10c3 CW |
2480 | struct drm_i915_fence_reg *reg; |
2481 | struct drm_i915_gem_object *obj_priv = NULL; | |
ae3db24a DV |
2482 | int i, avail, ret; |
2483 | ||
2484 | /* First try to find a free reg */ | |
2485 | avail = 0; | |
2486 | for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) { | |
2487 | reg = &dev_priv->fence_regs[i]; | |
2488 | if (!reg->obj) | |
2489 | return i; | |
2490 | ||
23010e43 | 2491 | obj_priv = to_intel_bo(reg->obj); |
ae3db24a DV |
2492 | if (!obj_priv->pin_count) |
2493 | avail++; | |
2494 | } | |
2495 | ||
2496 | if (avail == 0) | |
2497 | return -ENOSPC; | |
2498 | ||
2499 | /* None available, try to steal one or wait for a user to finish */ | |
a00b10c3 | 2500 | avail = I915_FENCE_REG_NONE; |
007cc8ac DV |
2501 | list_for_each_entry(reg, &dev_priv->mm.fence_list, |
2502 | lru_list) { | |
a00b10c3 | 2503 | obj_priv = to_intel_bo(reg->obj); |
ae3db24a DV |
2504 | if (obj_priv->pin_count) |
2505 | continue; | |
2506 | ||
2507 | /* found one! */ | |
a00b10c3 | 2508 | avail = obj_priv->fence_reg; |
ae3db24a DV |
2509 | break; |
2510 | } | |
2511 | ||
a00b10c3 | 2512 | BUG_ON(avail == I915_FENCE_REG_NONE); |
ae3db24a DV |
2513 | |
2514 | /* We only have a reference on obj from the active list. put_fence_reg | |
2515 | * might drop that one, causing a use-after-free in it. So hold a | |
2516 | * private reference to obj like the other callers of put_fence_reg | |
2517 | * (set_tiling ioctl) do. */ | |
a00b10c3 CW |
2518 | drm_gem_object_reference(&obj_priv->base); |
2519 | ret = i915_gem_object_put_fence_reg(&obj_priv->base, interruptible); | |
2520 | drm_gem_object_unreference(&obj_priv->base); | |
ae3db24a DV |
2521 | if (ret != 0) |
2522 | return ret; | |
2523 | ||
a00b10c3 | 2524 | return avail; |
ae3db24a DV |
2525 | } |
2526 | ||
de151cf6 JB |
2527 | /** |
2528 | * i915_gem_object_get_fence_reg - set up a fence reg for an object | |
2529 | * @obj: object to map through a fence reg | |
2530 | * | |
2531 | * When mapping objects through the GTT, userspace wants to be able to write | |
2532 | * to them without having to worry about swizzling if the object is tiled. | |
2533 | * | |
2534 | * This function walks the fence regs looking for a free one for @obj, | |
2535 | * stealing one if it can't find any. | |
2536 | * | |
2537 | * It then sets up the reg based on the object's properties: address, pitch | |
2538 | * and tiling format. | |
2539 | */ | |
8c4b8c3f | 2540 | int |
2cf34d7b CW |
2541 | i915_gem_object_get_fence_reg(struct drm_gem_object *obj, |
2542 | bool interruptible) | |
de151cf6 JB |
2543 | { |
2544 | struct drm_device *dev = obj->dev; | |
79e53945 | 2545 | struct drm_i915_private *dev_priv = dev->dev_private; |
23010e43 | 2546 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
de151cf6 | 2547 | struct drm_i915_fence_reg *reg = NULL; |
ae3db24a | 2548 | int ret; |
de151cf6 | 2549 | |
a09ba7fa EA |
2550 | /* Just update our place in the LRU if our fence is getting used. */ |
2551 | if (obj_priv->fence_reg != I915_FENCE_REG_NONE) { | |
007cc8ac DV |
2552 | reg = &dev_priv->fence_regs[obj_priv->fence_reg]; |
2553 | list_move_tail(®->lru_list, &dev_priv->mm.fence_list); | |
a09ba7fa EA |
2554 | return 0; |
2555 | } | |
2556 | ||
de151cf6 JB |
2557 | switch (obj_priv->tiling_mode) { |
2558 | case I915_TILING_NONE: | |
2559 | WARN(1, "allocating a fence for non-tiled object?\n"); | |
2560 | break; | |
2561 | case I915_TILING_X: | |
0f973f27 JB |
2562 | if (!obj_priv->stride) |
2563 | return -EINVAL; | |
2564 | WARN((obj_priv->stride & (512 - 1)), | |
2565 | "object 0x%08x is X tiled but has non-512B pitch\n", | |
2566 | obj_priv->gtt_offset); | |
de151cf6 JB |
2567 | break; |
2568 | case I915_TILING_Y: | |
0f973f27 JB |
2569 | if (!obj_priv->stride) |
2570 | return -EINVAL; | |
2571 | WARN((obj_priv->stride & (128 - 1)), | |
2572 | "object 0x%08x is Y tiled but has non-128B pitch\n", | |
2573 | obj_priv->gtt_offset); | |
de151cf6 JB |
2574 | break; |
2575 | } | |
2576 | ||
2cf34d7b | 2577 | ret = i915_find_fence_reg(dev, interruptible); |
ae3db24a DV |
2578 | if (ret < 0) |
2579 | return ret; | |
de151cf6 | 2580 | |
ae3db24a DV |
2581 | obj_priv->fence_reg = ret; |
2582 | reg = &dev_priv->fence_regs[obj_priv->fence_reg]; | |
007cc8ac | 2583 | list_add_tail(®->lru_list, &dev_priv->mm.fence_list); |
a09ba7fa | 2584 | |
de151cf6 JB |
2585 | reg->obj = obj; |
2586 | ||
e259befd CW |
2587 | switch (INTEL_INFO(dev)->gen) { |
2588 | case 6: | |
a00b10c3 | 2589 | sandybridge_write_fence_reg(obj); |
e259befd CW |
2590 | break; |
2591 | case 5: | |
2592 | case 4: | |
a00b10c3 | 2593 | i965_write_fence_reg(obj); |
e259befd CW |
2594 | break; |
2595 | case 3: | |
a00b10c3 | 2596 | i915_write_fence_reg(obj); |
e259befd CW |
2597 | break; |
2598 | case 2: | |
a00b10c3 | 2599 | i830_write_fence_reg(obj); |
e259befd CW |
2600 | break; |
2601 | } | |
d9ddcb96 | 2602 | |
a00b10c3 CW |
2603 | trace_i915_gem_object_get_fence(obj, |
2604 | obj_priv->fence_reg, | |
2605 | obj_priv->tiling_mode); | |
1c5d22f7 | 2606 | |
d9ddcb96 | 2607 | return 0; |
de151cf6 JB |
2608 | } |
2609 | ||
2610 | /** | |
2611 | * i915_gem_clear_fence_reg - clear out fence register info | |
2612 | * @obj: object to clear | |
2613 | * | |
2614 | * Zeroes out the fence register itself and clears out the associated | |
2615 | * data structures in dev_priv and obj_priv. | |
2616 | */ | |
2617 | static void | |
2618 | i915_gem_clear_fence_reg(struct drm_gem_object *obj) | |
2619 | { | |
2620 | struct drm_device *dev = obj->dev; | |
79e53945 | 2621 | drm_i915_private_t *dev_priv = dev->dev_private; |
23010e43 | 2622 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
007cc8ac DV |
2623 | struct drm_i915_fence_reg *reg = |
2624 | &dev_priv->fence_regs[obj_priv->fence_reg]; | |
e259befd | 2625 | uint32_t fence_reg; |
de151cf6 | 2626 | |
e259befd CW |
2627 | switch (INTEL_INFO(dev)->gen) { |
2628 | case 6: | |
4e901fdc EA |
2629 | I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + |
2630 | (obj_priv->fence_reg * 8), 0); | |
e259befd CW |
2631 | break; |
2632 | case 5: | |
2633 | case 4: | |
de151cf6 | 2634 | I915_WRITE64(FENCE_REG_965_0 + (obj_priv->fence_reg * 8), 0); |
e259befd CW |
2635 | break; |
2636 | case 3: | |
9b74f734 | 2637 | if (obj_priv->fence_reg >= 8) |
e259befd | 2638 | fence_reg = FENCE_REG_945_8 + (obj_priv->fence_reg - 8) * 4; |
dc529a4f | 2639 | else |
e259befd CW |
2640 | case 2: |
2641 | fence_reg = FENCE_REG_830_0 + obj_priv->fence_reg * 4; | |
dc529a4f EA |
2642 | |
2643 | I915_WRITE(fence_reg, 0); | |
e259befd | 2644 | break; |
dc529a4f | 2645 | } |
de151cf6 | 2646 | |
007cc8ac | 2647 | reg->obj = NULL; |
de151cf6 | 2648 | obj_priv->fence_reg = I915_FENCE_REG_NONE; |
007cc8ac | 2649 | list_del_init(®->lru_list); |
de151cf6 JB |
2650 | } |
2651 | ||
52dc7d32 CW |
2652 | /** |
2653 | * i915_gem_object_put_fence_reg - waits on outstanding fenced access | |
2654 | * to the buffer to finish, and then resets the fence register. | |
2655 | * @obj: tiled object holding a fence register. | |
2cf34d7b | 2656 | * @bool: whether the wait upon the fence is interruptible |
52dc7d32 CW |
2657 | * |
2658 | * Zeroes out the fence register itself and clears out the associated | |
2659 | * data structures in dev_priv and obj_priv. | |
2660 | */ | |
2661 | int | |
2cf34d7b CW |
2662 | i915_gem_object_put_fence_reg(struct drm_gem_object *obj, |
2663 | bool interruptible) | |
52dc7d32 CW |
2664 | { |
2665 | struct drm_device *dev = obj->dev; | |
53640e1d | 2666 | struct drm_i915_private *dev_priv = dev->dev_private; |
23010e43 | 2667 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
53640e1d | 2668 | struct drm_i915_fence_reg *reg; |
52dc7d32 CW |
2669 | |
2670 | if (obj_priv->fence_reg == I915_FENCE_REG_NONE) | |
2671 | return 0; | |
2672 | ||
10ae9bd2 DV |
2673 | /* If we've changed tiling, GTT-mappings of the object |
2674 | * need to re-fault to ensure that the correct fence register | |
2675 | * setup is in place. | |
2676 | */ | |
2677 | i915_gem_release_mmap(obj); | |
2678 | ||
52dc7d32 CW |
2679 | /* On the i915, GPU access to tiled buffers is via a fence, |
2680 | * therefore we must wait for any outstanding access to complete | |
2681 | * before clearing the fence. | |
2682 | */ | |
53640e1d CW |
2683 | reg = &dev_priv->fence_regs[obj_priv->fence_reg]; |
2684 | if (reg->gpu) { | |
52dc7d32 CW |
2685 | int ret; |
2686 | ||
2cf34d7b | 2687 | ret = i915_gem_object_flush_gpu_write_domain(obj, true); |
0bc23aad | 2688 | if (ret) |
2dafb1e0 CW |
2689 | return ret; |
2690 | ||
2cf34d7b | 2691 | ret = i915_gem_object_wait_rendering(obj, interruptible); |
0bc23aad | 2692 | if (ret) |
52dc7d32 | 2693 | return ret; |
53640e1d CW |
2694 | |
2695 | reg->gpu = false; | |
52dc7d32 CW |
2696 | } |
2697 | ||
4a726612 | 2698 | i915_gem_object_flush_gtt_write_domain(obj); |
0bc23aad | 2699 | i915_gem_clear_fence_reg(obj); |
52dc7d32 CW |
2700 | |
2701 | return 0; | |
2702 | } | |
2703 | ||
673a394b EA |
2704 | /** |
2705 | * Finds free space in the GTT aperture and binds the object there. | |
2706 | */ | |
2707 | static int | |
920afa77 DV |
2708 | i915_gem_object_bind_to_gtt(struct drm_gem_object *obj, |
2709 | unsigned alignment, | |
75e9e915 | 2710 | bool map_and_fenceable) |
673a394b EA |
2711 | { |
2712 | struct drm_device *dev = obj->dev; | |
2713 | drm_i915_private_t *dev_priv = dev->dev_private; | |
23010e43 | 2714 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
673a394b | 2715 | struct drm_mm_node *free_space; |
a00b10c3 | 2716 | gfp_t gfpmask = __GFP_NORETRY | __GFP_NOWARN; |
5e783301 | 2717 | u32 size, fence_size, fence_alignment, unfenced_alignment; |
75e9e915 | 2718 | bool mappable, fenceable; |
07f73f69 | 2719 | int ret; |
673a394b | 2720 | |
bb6baf76 | 2721 | if (obj_priv->madv != I915_MADV_WILLNEED) { |
3ef94daa CW |
2722 | DRM_ERROR("Attempting to bind a purgeable object\n"); |
2723 | return -EINVAL; | |
2724 | } | |
2725 | ||
a00b10c3 CW |
2726 | fence_size = i915_gem_get_gtt_size(obj_priv); |
2727 | fence_alignment = i915_gem_get_gtt_alignment(obj_priv); | |
5e783301 | 2728 | unfenced_alignment = i915_gem_get_unfenced_gtt_alignment(obj_priv); |
a00b10c3 | 2729 | |
673a394b | 2730 | if (alignment == 0) |
5e783301 DV |
2731 | alignment = map_and_fenceable ? fence_alignment : |
2732 | unfenced_alignment; | |
75e9e915 | 2733 | if (map_and_fenceable && alignment & (fence_alignment - 1)) { |
673a394b EA |
2734 | DRM_ERROR("Invalid object alignment requested %u\n", alignment); |
2735 | return -EINVAL; | |
2736 | } | |
2737 | ||
75e9e915 | 2738 | size = map_and_fenceable ? fence_size : obj->size; |
a00b10c3 | 2739 | |
654fc607 CW |
2740 | /* If the object is bigger than the entire aperture, reject it early |
2741 | * before evicting everything in a vain attempt to find space. | |
2742 | */ | |
920afa77 | 2743 | if (obj->size > |
75e9e915 | 2744 | (map_and_fenceable ? dev_priv->mm.gtt_mappable_end : dev_priv->mm.gtt_total)) { |
654fc607 CW |
2745 | DRM_ERROR("Attempting to bind an object larger than the aperture\n"); |
2746 | return -E2BIG; | |
2747 | } | |
2748 | ||
673a394b | 2749 | search_free: |
75e9e915 | 2750 | if (map_and_fenceable) |
920afa77 DV |
2751 | free_space = |
2752 | drm_mm_search_free_in_range(&dev_priv->mm.gtt_space, | |
a00b10c3 | 2753 | size, alignment, 0, |
920afa77 DV |
2754 | dev_priv->mm.gtt_mappable_end, |
2755 | 0); | |
2756 | else | |
2757 | free_space = drm_mm_search_free(&dev_priv->mm.gtt_space, | |
a00b10c3 | 2758 | size, alignment, 0); |
920afa77 DV |
2759 | |
2760 | if (free_space != NULL) { | |
75e9e915 | 2761 | if (map_and_fenceable) |
920afa77 DV |
2762 | obj_priv->gtt_space = |
2763 | drm_mm_get_block_range_generic(free_space, | |
a00b10c3 | 2764 | size, alignment, 0, |
920afa77 DV |
2765 | dev_priv->mm.gtt_mappable_end, |
2766 | 0); | |
2767 | else | |
2768 | obj_priv->gtt_space = | |
a00b10c3 | 2769 | drm_mm_get_block(free_space, size, alignment); |
920afa77 | 2770 | } |
673a394b EA |
2771 | if (obj_priv->gtt_space == NULL) { |
2772 | /* If the gtt is empty and we're still having trouble | |
2773 | * fitting our object in, we're out of memory. | |
2774 | */ | |
75e9e915 DV |
2775 | ret = i915_gem_evict_something(dev, size, alignment, |
2776 | map_and_fenceable); | |
9731129c | 2777 | if (ret) |
673a394b | 2778 | return ret; |
9731129c | 2779 | |
673a394b EA |
2780 | goto search_free; |
2781 | } | |
2782 | ||
e5281ccd | 2783 | ret = i915_gem_object_get_pages_gtt(obj, gfpmask); |
673a394b EA |
2784 | if (ret) { |
2785 | drm_mm_put_block(obj_priv->gtt_space); | |
2786 | obj_priv->gtt_space = NULL; | |
07f73f69 CW |
2787 | |
2788 | if (ret == -ENOMEM) { | |
2789 | /* first try to clear up some space from the GTT */ | |
a00b10c3 | 2790 | ret = i915_gem_evict_something(dev, size, |
75e9e915 DV |
2791 | alignment, |
2792 | map_and_fenceable); | |
07f73f69 | 2793 | if (ret) { |
07f73f69 | 2794 | /* now try to shrink everyone else */ |
4bdadb97 CW |
2795 | if (gfpmask) { |
2796 | gfpmask = 0; | |
2797 | goto search_free; | |
07f73f69 CW |
2798 | } |
2799 | ||
2800 | return ret; | |
2801 | } | |
2802 | ||
2803 | goto search_free; | |
2804 | } | |
2805 | ||
673a394b EA |
2806 | return ret; |
2807 | } | |
2808 | ||
673a394b EA |
2809 | /* Create an AGP memory structure pointing at our pages, and bind it |
2810 | * into the GTT. | |
2811 | */ | |
2812 | obj_priv->agp_mem = drm_agp_bind_pages(dev, | |
856fa198 | 2813 | obj_priv->pages, |
07f73f69 | 2814 | obj->size >> PAGE_SHIFT, |
9af90d19 | 2815 | obj_priv->gtt_space->start, |
ba1eb1d8 | 2816 | obj_priv->agp_type); |
673a394b | 2817 | if (obj_priv->agp_mem == NULL) { |
e5281ccd | 2818 | i915_gem_object_put_pages_gtt(obj); |
673a394b EA |
2819 | drm_mm_put_block(obj_priv->gtt_space); |
2820 | obj_priv->gtt_space = NULL; | |
07f73f69 | 2821 | |
a00b10c3 | 2822 | ret = i915_gem_evict_something(dev, size, |
75e9e915 | 2823 | alignment, map_and_fenceable); |
9731129c | 2824 | if (ret) |
07f73f69 | 2825 | return ret; |
07f73f69 CW |
2826 | |
2827 | goto search_free; | |
673a394b | 2828 | } |
673a394b | 2829 | |
fb7d516a DV |
2830 | obj_priv->gtt_offset = obj_priv->gtt_space->start; |
2831 | ||
bf1a1092 | 2832 | /* keep track of bounds object by adding it to the inactive list */ |
69dc4987 | 2833 | list_add_tail(&obj_priv->mm_list, &dev_priv->mm.inactive_list); |
a00b10c3 | 2834 | i915_gem_info_add_gtt(dev_priv, obj_priv); |
bf1a1092 | 2835 | |
673a394b EA |
2836 | /* Assert that the object is not currently in any GPU domain. As it |
2837 | * wasn't in the GTT, there shouldn't be any way it could have been in | |
2838 | * a GPU cache | |
2839 | */ | |
21d509e3 CW |
2840 | BUG_ON(obj->read_domains & I915_GEM_GPU_DOMAINS); |
2841 | BUG_ON(obj->write_domain & I915_GEM_GPU_DOMAINS); | |
673a394b | 2842 | |
75e9e915 | 2843 | trace_i915_gem_object_bind(obj, obj_priv->gtt_offset, map_and_fenceable); |
1c5d22f7 | 2844 | |
75e9e915 | 2845 | fenceable = |
a00b10c3 CW |
2846 | obj_priv->gtt_space->size == fence_size && |
2847 | (obj_priv->gtt_space->start & (fence_alignment -1)) == 0; | |
2848 | ||
75e9e915 | 2849 | mappable = |
a00b10c3 CW |
2850 | obj_priv->gtt_offset + obj->size <= dev_priv->mm.gtt_mappable_end; |
2851 | ||
75e9e915 DV |
2852 | obj_priv->map_and_fenceable = mappable && fenceable; |
2853 | ||
673a394b EA |
2854 | return 0; |
2855 | } | |
2856 | ||
2857 | void | |
2858 | i915_gem_clflush_object(struct drm_gem_object *obj) | |
2859 | { | |
23010e43 | 2860 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
673a394b EA |
2861 | |
2862 | /* If we don't have a page list set up, then we're not pinned | |
2863 | * to GPU, and we can ignore the cache flush because it'll happen | |
2864 | * again at bind time. | |
2865 | */ | |
856fa198 | 2866 | if (obj_priv->pages == NULL) |
673a394b EA |
2867 | return; |
2868 | ||
1c5d22f7 | 2869 | trace_i915_gem_object_clflush(obj); |
cfa16a0d | 2870 | |
856fa198 | 2871 | drm_clflush_pages(obj_priv->pages, obj->size / PAGE_SIZE); |
673a394b EA |
2872 | } |
2873 | ||
e47c68e9 | 2874 | /** Flushes any GPU write domain for the object if it's dirty. */ |
2dafb1e0 | 2875 | static int |
ba3d8d74 DV |
2876 | i915_gem_object_flush_gpu_write_domain(struct drm_gem_object *obj, |
2877 | bool pipelined) | |
e47c68e9 EA |
2878 | { |
2879 | struct drm_device *dev = obj->dev; | |
e47c68e9 EA |
2880 | |
2881 | if ((obj->write_domain & I915_GEM_GPU_DOMAINS) == 0) | |
2dafb1e0 | 2882 | return 0; |
e47c68e9 EA |
2883 | |
2884 | /* Queue the GPU write cache flushing we need. */ | |
c78ec30b | 2885 | i915_gem_flush_ring(dev, NULL, |
9220434a CW |
2886 | to_intel_bo(obj)->ring, |
2887 | 0, obj->write_domain); | |
48b956c5 | 2888 | BUG_ON(obj->write_domain); |
1c5d22f7 | 2889 | |
ba3d8d74 DV |
2890 | if (pipelined) |
2891 | return 0; | |
2892 | ||
2cf34d7b | 2893 | return i915_gem_object_wait_rendering(obj, true); |
e47c68e9 EA |
2894 | } |
2895 | ||
2896 | /** Flushes the GTT write domain for the object if it's dirty. */ | |
2897 | static void | |
2898 | i915_gem_object_flush_gtt_write_domain(struct drm_gem_object *obj) | |
2899 | { | |
1c5d22f7 CW |
2900 | uint32_t old_write_domain; |
2901 | ||
e47c68e9 EA |
2902 | if (obj->write_domain != I915_GEM_DOMAIN_GTT) |
2903 | return; | |
2904 | ||
2905 | /* No actual flushing is required for the GTT write domain. Writes | |
2906 | * to it immediately go to main memory as far as we know, so there's | |
2907 | * no chipset flush. It also doesn't land in render cache. | |
2908 | */ | |
4a684a41 CW |
2909 | i915_gem_release_mmap(obj); |
2910 | ||
1c5d22f7 | 2911 | old_write_domain = obj->write_domain; |
e47c68e9 | 2912 | obj->write_domain = 0; |
1c5d22f7 CW |
2913 | |
2914 | trace_i915_gem_object_change_domain(obj, | |
2915 | obj->read_domains, | |
2916 | old_write_domain); | |
e47c68e9 EA |
2917 | } |
2918 | ||
2919 | /** Flushes the CPU write domain for the object if it's dirty. */ | |
2920 | static void | |
2921 | i915_gem_object_flush_cpu_write_domain(struct drm_gem_object *obj) | |
2922 | { | |
1c5d22f7 | 2923 | uint32_t old_write_domain; |
e47c68e9 EA |
2924 | |
2925 | if (obj->write_domain != I915_GEM_DOMAIN_CPU) | |
2926 | return; | |
2927 | ||
2928 | i915_gem_clflush_object(obj); | |
40ce6575 | 2929 | intel_gtt_chipset_flush(); |
1c5d22f7 | 2930 | old_write_domain = obj->write_domain; |
e47c68e9 | 2931 | obj->write_domain = 0; |
1c5d22f7 CW |
2932 | |
2933 | trace_i915_gem_object_change_domain(obj, | |
2934 | obj->read_domains, | |
2935 | old_write_domain); | |
e47c68e9 EA |
2936 | } |
2937 | ||
2ef7eeaa EA |
2938 | /** |
2939 | * Moves a single object to the GTT read, and possibly write domain. | |
2940 | * | |
2941 | * This function returns when the move is complete, including waiting on | |
2942 | * flushes to occur. | |
2943 | */ | |
79e53945 | 2944 | int |
2ef7eeaa EA |
2945 | i915_gem_object_set_to_gtt_domain(struct drm_gem_object *obj, int write) |
2946 | { | |
23010e43 | 2947 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
1c5d22f7 | 2948 | uint32_t old_write_domain, old_read_domains; |
e47c68e9 | 2949 | int ret; |
2ef7eeaa | 2950 | |
02354392 EA |
2951 | /* Not valid to be called on unbound objects. */ |
2952 | if (obj_priv->gtt_space == NULL) | |
2953 | return -EINVAL; | |
2954 | ||
ba3d8d74 | 2955 | ret = i915_gem_object_flush_gpu_write_domain(obj, false); |
2dafb1e0 CW |
2956 | if (ret != 0) |
2957 | return ret; | |
2958 | ||
7213342d | 2959 | i915_gem_object_flush_cpu_write_domain(obj); |
1c5d22f7 | 2960 | |
ba3d8d74 | 2961 | if (write) { |
2cf34d7b | 2962 | ret = i915_gem_object_wait_rendering(obj, true); |
ba3d8d74 DV |
2963 | if (ret) |
2964 | return ret; | |
ba3d8d74 | 2965 | } |
e47c68e9 | 2966 | |
1c5d22f7 CW |
2967 | old_write_domain = obj->write_domain; |
2968 | old_read_domains = obj->read_domains; | |
2969 | ||
e47c68e9 EA |
2970 | /* It should now be out of any other write domains, and we can update |
2971 | * the domain values for our changes. | |
2972 | */ | |
2973 | BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_GTT) != 0); | |
2974 | obj->read_domains |= I915_GEM_DOMAIN_GTT; | |
2975 | if (write) { | |
7213342d | 2976 | obj->read_domains = I915_GEM_DOMAIN_GTT; |
e47c68e9 EA |
2977 | obj->write_domain = I915_GEM_DOMAIN_GTT; |
2978 | obj_priv->dirty = 1; | |
2ef7eeaa EA |
2979 | } |
2980 | ||
1c5d22f7 CW |
2981 | trace_i915_gem_object_change_domain(obj, |
2982 | old_read_domains, | |
2983 | old_write_domain); | |
2984 | ||
e47c68e9 EA |
2985 | return 0; |
2986 | } | |
2987 | ||
b9241ea3 ZW |
2988 | /* |
2989 | * Prepare buffer for display plane. Use uninterruptible for possible flush | |
2990 | * wait, as in modesetting process we're not supposed to be interrupted. | |
2991 | */ | |
2992 | int | |
48b956c5 CW |
2993 | i915_gem_object_set_to_display_plane(struct drm_gem_object *obj, |
2994 | bool pipelined) | |
b9241ea3 | 2995 | { |
23010e43 | 2996 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
ba3d8d74 | 2997 | uint32_t old_read_domains; |
b9241ea3 ZW |
2998 | int ret; |
2999 | ||
3000 | /* Not valid to be called on unbound objects. */ | |
3001 | if (obj_priv->gtt_space == NULL) | |
3002 | return -EINVAL; | |
3003 | ||
ced270fa | 3004 | ret = i915_gem_object_flush_gpu_write_domain(obj, true); |
2dafb1e0 CW |
3005 | if (ret) |
3006 | return ret; | |
b9241ea3 | 3007 | |
ced270fa CW |
3008 | /* Currently, we are always called from an non-interruptible context. */ |
3009 | if (!pipelined) { | |
3010 | ret = i915_gem_object_wait_rendering(obj, false); | |
3011 | if (ret) | |
b9241ea3 ZW |
3012 | return ret; |
3013 | } | |
3014 | ||
b118c1e3 CW |
3015 | i915_gem_object_flush_cpu_write_domain(obj); |
3016 | ||
b9241ea3 | 3017 | old_read_domains = obj->read_domains; |
c78ec30b | 3018 | obj->read_domains |= I915_GEM_DOMAIN_GTT; |
b9241ea3 ZW |
3019 | |
3020 | trace_i915_gem_object_change_domain(obj, | |
3021 | old_read_domains, | |
ba3d8d74 | 3022 | obj->write_domain); |
b9241ea3 ZW |
3023 | |
3024 | return 0; | |
3025 | } | |
3026 | ||
85345517 CW |
3027 | int |
3028 | i915_gem_object_flush_gpu(struct drm_i915_gem_object *obj, | |
3029 | bool interruptible) | |
3030 | { | |
3031 | if (!obj->active) | |
3032 | return 0; | |
3033 | ||
3034 | if (obj->base.write_domain & I915_GEM_GPU_DOMAINS) | |
3035 | i915_gem_flush_ring(obj->base.dev, NULL, obj->ring, | |
3036 | 0, obj->base.write_domain); | |
3037 | ||
3038 | return i915_gem_object_wait_rendering(&obj->base, interruptible); | |
3039 | } | |
3040 | ||
e47c68e9 EA |
3041 | /** |
3042 | * Moves a single object to the CPU read, and possibly write domain. | |
3043 | * | |
3044 | * This function returns when the move is complete, including waiting on | |
3045 | * flushes to occur. | |
3046 | */ | |
3047 | static int | |
3048 | i915_gem_object_set_to_cpu_domain(struct drm_gem_object *obj, int write) | |
3049 | { | |
1c5d22f7 | 3050 | uint32_t old_write_domain, old_read_domains; |
e47c68e9 EA |
3051 | int ret; |
3052 | ||
ba3d8d74 | 3053 | ret = i915_gem_object_flush_gpu_write_domain(obj, false); |
e47c68e9 EA |
3054 | if (ret != 0) |
3055 | return ret; | |
2ef7eeaa | 3056 | |
e47c68e9 | 3057 | i915_gem_object_flush_gtt_write_domain(obj); |
2ef7eeaa | 3058 | |
e47c68e9 EA |
3059 | /* If we have a partially-valid cache of the object in the CPU, |
3060 | * finish invalidating it and free the per-page flags. | |
2ef7eeaa | 3061 | */ |
e47c68e9 | 3062 | i915_gem_object_set_to_full_cpu_read_domain(obj); |
2ef7eeaa | 3063 | |
7213342d | 3064 | if (write) { |
2cf34d7b | 3065 | ret = i915_gem_object_wait_rendering(obj, true); |
7213342d CW |
3066 | if (ret) |
3067 | return ret; | |
3068 | } | |
3069 | ||
1c5d22f7 CW |
3070 | old_write_domain = obj->write_domain; |
3071 | old_read_domains = obj->read_domains; | |
3072 | ||
e47c68e9 EA |
3073 | /* Flush the CPU cache if it's still invalid. */ |
3074 | if ((obj->read_domains & I915_GEM_DOMAIN_CPU) == 0) { | |
2ef7eeaa | 3075 | i915_gem_clflush_object(obj); |
2ef7eeaa | 3076 | |
e47c68e9 | 3077 | obj->read_domains |= I915_GEM_DOMAIN_CPU; |
2ef7eeaa EA |
3078 | } |
3079 | ||
3080 | /* It should now be out of any other write domains, and we can update | |
3081 | * the domain values for our changes. | |
3082 | */ | |
e47c68e9 EA |
3083 | BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_CPU) != 0); |
3084 | ||
3085 | /* If we're writing through the CPU, then the GPU read domains will | |
3086 | * need to be invalidated at next use. | |
3087 | */ | |
3088 | if (write) { | |
c78ec30b | 3089 | obj->read_domains = I915_GEM_DOMAIN_CPU; |
e47c68e9 EA |
3090 | obj->write_domain = I915_GEM_DOMAIN_CPU; |
3091 | } | |
2ef7eeaa | 3092 | |
1c5d22f7 CW |
3093 | trace_i915_gem_object_change_domain(obj, |
3094 | old_read_domains, | |
3095 | old_write_domain); | |
3096 | ||
2ef7eeaa EA |
3097 | return 0; |
3098 | } | |
3099 | ||
673a394b EA |
3100 | /* |
3101 | * Set the next domain for the specified object. This | |
3102 | * may not actually perform the necessary flushing/invaliding though, | |
3103 | * as that may want to be batched with other set_domain operations | |
3104 | * | |
3105 | * This is (we hope) the only really tricky part of gem. The goal | |
3106 | * is fairly simple -- track which caches hold bits of the object | |
3107 | * and make sure they remain coherent. A few concrete examples may | |
3108 | * help to explain how it works. For shorthand, we use the notation | |
3109 | * (read_domains, write_domain), e.g. (CPU, CPU) to indicate the | |
3110 | * a pair of read and write domain masks. | |
3111 | * | |
3112 | * Case 1: the batch buffer | |
3113 | * | |
3114 | * 1. Allocated | |
3115 | * 2. Written by CPU | |
3116 | * 3. Mapped to GTT | |
3117 | * 4. Read by GPU | |
3118 | * 5. Unmapped from GTT | |
3119 | * 6. Freed | |
3120 | * | |
3121 | * Let's take these a step at a time | |
3122 | * | |
3123 | * 1. Allocated | |
3124 | * Pages allocated from the kernel may still have | |
3125 | * cache contents, so we set them to (CPU, CPU) always. | |
3126 | * 2. Written by CPU (using pwrite) | |
3127 | * The pwrite function calls set_domain (CPU, CPU) and | |
3128 | * this function does nothing (as nothing changes) | |
3129 | * 3. Mapped by GTT | |
3130 | * This function asserts that the object is not | |
3131 | * currently in any GPU-based read or write domains | |
3132 | * 4. Read by GPU | |
3133 | * i915_gem_execbuffer calls set_domain (COMMAND, 0). | |
3134 | * As write_domain is zero, this function adds in the | |
3135 | * current read domains (CPU+COMMAND, 0). | |
3136 | * flush_domains is set to CPU. | |
3137 | * invalidate_domains is set to COMMAND | |
3138 | * clflush is run to get data out of the CPU caches | |
3139 | * then i915_dev_set_domain calls i915_gem_flush to | |
3140 | * emit an MI_FLUSH and drm_agp_chipset_flush | |
3141 | * 5. Unmapped from GTT | |
3142 | * i915_gem_object_unbind calls set_domain (CPU, CPU) | |
3143 | * flush_domains and invalidate_domains end up both zero | |
3144 | * so no flushing/invalidating happens | |
3145 | * 6. Freed | |
3146 | * yay, done | |
3147 | * | |
3148 | * Case 2: The shared render buffer | |
3149 | * | |
3150 | * 1. Allocated | |
3151 | * 2. Mapped to GTT | |
3152 | * 3. Read/written by GPU | |
3153 | * 4. set_domain to (CPU,CPU) | |
3154 | * 5. Read/written by CPU | |
3155 | * 6. Read/written by GPU | |
3156 | * | |
3157 | * 1. Allocated | |
3158 | * Same as last example, (CPU, CPU) | |
3159 | * 2. Mapped to GTT | |
3160 | * Nothing changes (assertions find that it is not in the GPU) | |
3161 | * 3. Read/written by GPU | |
3162 | * execbuffer calls set_domain (RENDER, RENDER) | |
3163 | * flush_domains gets CPU | |
3164 | * invalidate_domains gets GPU | |
3165 | * clflush (obj) | |
3166 | * MI_FLUSH and drm_agp_chipset_flush | |
3167 | * 4. set_domain (CPU, CPU) | |
3168 | * flush_domains gets GPU | |
3169 | * invalidate_domains gets CPU | |
3170 | * wait_rendering (obj) to make sure all drawing is complete. | |
3171 | * This will include an MI_FLUSH to get the data from GPU | |
3172 | * to memory | |
3173 | * clflush (obj) to invalidate the CPU cache | |
3174 | * Another MI_FLUSH in i915_gem_flush (eliminate this somehow?) | |
3175 | * 5. Read/written by CPU | |
3176 | * cache lines are loaded and dirtied | |
3177 | * 6. Read written by GPU | |
3178 | * Same as last GPU access | |
3179 | * | |
3180 | * Case 3: The constant buffer | |
3181 | * | |
3182 | * 1. Allocated | |
3183 | * 2. Written by CPU | |
3184 | * 3. Read by GPU | |
3185 | * 4. Updated (written) by CPU again | |
3186 | * 5. Read by GPU | |
3187 | * | |
3188 | * 1. Allocated | |
3189 | * (CPU, CPU) | |
3190 | * 2. Written by CPU | |
3191 | * (CPU, CPU) | |
3192 | * 3. Read by GPU | |
3193 | * (CPU+RENDER, 0) | |
3194 | * flush_domains = CPU | |
3195 | * invalidate_domains = RENDER | |
3196 | * clflush (obj) | |
3197 | * MI_FLUSH | |
3198 | * drm_agp_chipset_flush | |
3199 | * 4. Updated (written) by CPU again | |
3200 | * (CPU, CPU) | |
3201 | * flush_domains = 0 (no previous write domain) | |
3202 | * invalidate_domains = 0 (no new read domains) | |
3203 | * 5. Read by GPU | |
3204 | * (CPU+RENDER, 0) | |
3205 | * flush_domains = CPU | |
3206 | * invalidate_domains = RENDER | |
3207 | * clflush (obj) | |
3208 | * MI_FLUSH | |
3209 | * drm_agp_chipset_flush | |
3210 | */ | |
c0d90829 | 3211 | static void |
b6651458 | 3212 | i915_gem_object_set_to_gpu_domain(struct drm_gem_object *obj, |
0f8c6d7c CW |
3213 | struct intel_ring_buffer *ring, |
3214 | struct change_domains *cd) | |
673a394b | 3215 | { |
23010e43 | 3216 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
673a394b EA |
3217 | uint32_t invalidate_domains = 0; |
3218 | uint32_t flush_domains = 0; | |
652c393a | 3219 | |
673a394b EA |
3220 | /* |
3221 | * If the object isn't moving to a new write domain, | |
3222 | * let the object stay in multiple read domains | |
3223 | */ | |
8b0e378a EA |
3224 | if (obj->pending_write_domain == 0) |
3225 | obj->pending_read_domains |= obj->read_domains; | |
673a394b EA |
3226 | |
3227 | /* | |
3228 | * Flush the current write domain if | |
3229 | * the new read domains don't match. Invalidate | |
3230 | * any read domains which differ from the old | |
3231 | * write domain | |
3232 | */ | |
8b0e378a | 3233 | if (obj->write_domain && |
13b29289 CW |
3234 | (obj->write_domain != obj->pending_read_domains || |
3235 | obj_priv->ring != ring)) { | |
673a394b | 3236 | flush_domains |= obj->write_domain; |
8b0e378a EA |
3237 | invalidate_domains |= |
3238 | obj->pending_read_domains & ~obj->write_domain; | |
673a394b EA |
3239 | } |
3240 | /* | |
3241 | * Invalidate any read caches which may have | |
3242 | * stale data. That is, any new read domains. | |
3243 | */ | |
8b0e378a | 3244 | invalidate_domains |= obj->pending_read_domains & ~obj->read_domains; |
3d2a812a | 3245 | if ((flush_domains | invalidate_domains) & I915_GEM_DOMAIN_CPU) |
673a394b | 3246 | i915_gem_clflush_object(obj); |
673a394b | 3247 | |
4a684a41 CW |
3248 | /* blow away mappings if mapped through GTT */ |
3249 | if ((flush_domains | invalidate_domains) & I915_GEM_DOMAIN_GTT) | |
3250 | i915_gem_release_mmap(obj); | |
3251 | ||
efbeed96 EA |
3252 | /* The actual obj->write_domain will be updated with |
3253 | * pending_write_domain after we emit the accumulated flush for all | |
3254 | * of our domain changes in execbuffers (which clears objects' | |
3255 | * write_domains). So if we have a current write domain that we | |
3256 | * aren't changing, set pending_write_domain to that. | |
3257 | */ | |
3258 | if (flush_domains == 0 && obj->pending_write_domain == 0) | |
3259 | obj->pending_write_domain = obj->write_domain; | |
673a394b | 3260 | |
0f8c6d7c CW |
3261 | cd->invalidate_domains |= invalidate_domains; |
3262 | cd->flush_domains |= flush_domains; | |
b6651458 | 3263 | if (flush_domains & I915_GEM_GPU_DOMAINS) |
0f8c6d7c | 3264 | cd->flush_rings |= obj_priv->ring->id; |
b6651458 | 3265 | if (invalidate_domains & I915_GEM_GPU_DOMAINS) |
0f8c6d7c | 3266 | cd->flush_rings |= ring->id; |
673a394b EA |
3267 | } |
3268 | ||
3269 | /** | |
e47c68e9 | 3270 | * Moves the object from a partially CPU read to a full one. |
673a394b | 3271 | * |
e47c68e9 EA |
3272 | * Note that this only resolves i915_gem_object_set_cpu_read_domain_range(), |
3273 | * and doesn't handle transitioning from !(read_domains & I915_GEM_DOMAIN_CPU). | |
673a394b | 3274 | */ |
e47c68e9 EA |
3275 | static void |
3276 | i915_gem_object_set_to_full_cpu_read_domain(struct drm_gem_object *obj) | |
673a394b | 3277 | { |
23010e43 | 3278 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
673a394b | 3279 | |
e47c68e9 EA |
3280 | if (!obj_priv->page_cpu_valid) |
3281 | return; | |
3282 | ||
3283 | /* If we're partially in the CPU read domain, finish moving it in. | |
3284 | */ | |
3285 | if (obj->read_domains & I915_GEM_DOMAIN_CPU) { | |
3286 | int i; | |
3287 | ||
3288 | for (i = 0; i <= (obj->size - 1) / PAGE_SIZE; i++) { | |
3289 | if (obj_priv->page_cpu_valid[i]) | |
3290 | continue; | |
856fa198 | 3291 | drm_clflush_pages(obj_priv->pages + i, 1); |
e47c68e9 | 3292 | } |
e47c68e9 EA |
3293 | } |
3294 | ||
3295 | /* Free the page_cpu_valid mappings which are now stale, whether | |
3296 | * or not we've got I915_GEM_DOMAIN_CPU. | |
3297 | */ | |
9a298b2a | 3298 | kfree(obj_priv->page_cpu_valid); |
e47c68e9 EA |
3299 | obj_priv->page_cpu_valid = NULL; |
3300 | } | |
3301 | ||
3302 | /** | |
3303 | * Set the CPU read domain on a range of the object. | |
3304 | * | |
3305 | * The object ends up with I915_GEM_DOMAIN_CPU in its read flags although it's | |
3306 | * not entirely valid. The page_cpu_valid member of the object flags which | |
3307 | * pages have been flushed, and will be respected by | |
3308 | * i915_gem_object_set_to_cpu_domain() if it's called on to get a valid mapping | |
3309 | * of the whole object. | |
3310 | * | |
3311 | * This function returns when the move is complete, including waiting on | |
3312 | * flushes to occur. | |
3313 | */ | |
3314 | static int | |
3315 | i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object *obj, | |
3316 | uint64_t offset, uint64_t size) | |
3317 | { | |
23010e43 | 3318 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
1c5d22f7 | 3319 | uint32_t old_read_domains; |
e47c68e9 | 3320 | int i, ret; |
673a394b | 3321 | |
e47c68e9 EA |
3322 | if (offset == 0 && size == obj->size) |
3323 | return i915_gem_object_set_to_cpu_domain(obj, 0); | |
673a394b | 3324 | |
ba3d8d74 | 3325 | ret = i915_gem_object_flush_gpu_write_domain(obj, false); |
e47c68e9 | 3326 | if (ret != 0) |
6a47baa6 | 3327 | return ret; |
e47c68e9 EA |
3328 | i915_gem_object_flush_gtt_write_domain(obj); |
3329 | ||
3330 | /* If we're already fully in the CPU read domain, we're done. */ | |
3331 | if (obj_priv->page_cpu_valid == NULL && | |
3332 | (obj->read_domains & I915_GEM_DOMAIN_CPU) != 0) | |
3333 | return 0; | |
673a394b | 3334 | |
e47c68e9 EA |
3335 | /* Otherwise, create/clear the per-page CPU read domain flag if we're |
3336 | * newly adding I915_GEM_DOMAIN_CPU | |
3337 | */ | |
673a394b | 3338 | if (obj_priv->page_cpu_valid == NULL) { |
9a298b2a EA |
3339 | obj_priv->page_cpu_valid = kzalloc(obj->size / PAGE_SIZE, |
3340 | GFP_KERNEL); | |
e47c68e9 EA |
3341 | if (obj_priv->page_cpu_valid == NULL) |
3342 | return -ENOMEM; | |
3343 | } else if ((obj->read_domains & I915_GEM_DOMAIN_CPU) == 0) | |
3344 | memset(obj_priv->page_cpu_valid, 0, obj->size / PAGE_SIZE); | |
673a394b EA |
3345 | |
3346 | /* Flush the cache on any pages that are still invalid from the CPU's | |
3347 | * perspective. | |
3348 | */ | |
e47c68e9 EA |
3349 | for (i = offset / PAGE_SIZE; i <= (offset + size - 1) / PAGE_SIZE; |
3350 | i++) { | |
673a394b EA |
3351 | if (obj_priv->page_cpu_valid[i]) |
3352 | continue; | |
3353 | ||
856fa198 | 3354 | drm_clflush_pages(obj_priv->pages + i, 1); |
673a394b EA |
3355 | |
3356 | obj_priv->page_cpu_valid[i] = 1; | |
3357 | } | |
3358 | ||
e47c68e9 EA |
3359 | /* It should now be out of any other write domains, and we can update |
3360 | * the domain values for our changes. | |
3361 | */ | |
3362 | BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_CPU) != 0); | |
3363 | ||
1c5d22f7 | 3364 | old_read_domains = obj->read_domains; |
e47c68e9 EA |
3365 | obj->read_domains |= I915_GEM_DOMAIN_CPU; |
3366 | ||
1c5d22f7 CW |
3367 | trace_i915_gem_object_change_domain(obj, |
3368 | old_read_domains, | |
3369 | obj->write_domain); | |
3370 | ||
673a394b EA |
3371 | return 0; |
3372 | } | |
3373 | ||
673a394b | 3374 | static int |
bcf50e27 CW |
3375 | i915_gem_execbuffer_relocate_entry(struct drm_i915_gem_object *obj, |
3376 | struct drm_file *file_priv, | |
3377 | struct drm_i915_gem_exec_object2 *entry, | |
3378 | struct drm_i915_gem_relocation_entry *reloc) | |
673a394b | 3379 | { |
9af90d19 | 3380 | struct drm_device *dev = obj->base.dev; |
bcf50e27 CW |
3381 | struct drm_gem_object *target_obj; |
3382 | uint32_t target_offset; | |
3383 | int ret = -EINVAL; | |
673a394b | 3384 | |
bcf50e27 CW |
3385 | target_obj = drm_gem_object_lookup(dev, file_priv, |
3386 | reloc->target_handle); | |
3387 | if (target_obj == NULL) | |
3388 | return -ENOENT; | |
673a394b | 3389 | |
bcf50e27 | 3390 | target_offset = to_intel_bo(target_obj)->gtt_offset; |
76446cac | 3391 | |
bcf50e27 CW |
3392 | #if WATCH_RELOC |
3393 | DRM_INFO("%s: obj %p offset %08x target %d " | |
3394 | "read %08x write %08x gtt %08x " | |
3395 | "presumed %08x delta %08x\n", | |
3396 | __func__, | |
3397 | obj, | |
3398 | (int) reloc->offset, | |
3399 | (int) reloc->target_handle, | |
3400 | (int) reloc->read_domains, | |
3401 | (int) reloc->write_domain, | |
3402 | (int) target_offset, | |
3403 | (int) reloc->presumed_offset, | |
3404 | reloc->delta); | |
3405 | #endif | |
673a394b | 3406 | |
bcf50e27 CW |
3407 | /* The target buffer should have appeared before us in the |
3408 | * exec_object list, so it should have a GTT space bound by now. | |
3409 | */ | |
3410 | if (target_offset == 0) { | |
3411 | DRM_ERROR("No GTT space found for object %d\n", | |
3412 | reloc->target_handle); | |
3413 | goto err; | |
3414 | } | |
9af90d19 | 3415 | |
bcf50e27 CW |
3416 | /* Validate that the target is in a valid r/w GPU domain */ |
3417 | if (reloc->write_domain & (reloc->write_domain - 1)) { | |
3418 | DRM_ERROR("reloc with multiple write domains: " | |
3419 | "obj %p target %d offset %d " | |
3420 | "read %08x write %08x", | |
3421 | obj, reloc->target_handle, | |
3422 | (int) reloc->offset, | |
3423 | reloc->read_domains, | |
3424 | reloc->write_domain); | |
3425 | goto err; | |
3426 | } | |
3427 | if (reloc->write_domain & I915_GEM_DOMAIN_CPU || | |
3428 | reloc->read_domains & I915_GEM_DOMAIN_CPU) { | |
3429 | DRM_ERROR("reloc with read/write CPU domains: " | |
3430 | "obj %p target %d offset %d " | |
3431 | "read %08x write %08x", | |
3432 | obj, reloc->target_handle, | |
3433 | (int) reloc->offset, | |
3434 | reloc->read_domains, | |
3435 | reloc->write_domain); | |
3436 | goto err; | |
3437 | } | |
3438 | if (reloc->write_domain && target_obj->pending_write_domain && | |
3439 | reloc->write_domain != target_obj->pending_write_domain) { | |
3440 | DRM_ERROR("Write domain conflict: " | |
3441 | "obj %p target %d offset %d " | |
3442 | "new %08x old %08x\n", | |
3443 | obj, reloc->target_handle, | |
3444 | (int) reloc->offset, | |
3445 | reloc->write_domain, | |
3446 | target_obj->pending_write_domain); | |
3447 | goto err; | |
3448 | } | |
673a394b | 3449 | |
bcf50e27 CW |
3450 | target_obj->pending_read_domains |= reloc->read_domains; |
3451 | target_obj->pending_write_domain |= reloc->write_domain; | |
8542a0bb | 3452 | |
bcf50e27 CW |
3453 | /* If the relocation already has the right value in it, no |
3454 | * more work needs to be done. | |
3455 | */ | |
3456 | if (target_offset == reloc->presumed_offset) | |
3457 | goto out; | |
673a394b | 3458 | |
bcf50e27 CW |
3459 | /* Check that the relocation address is valid... */ |
3460 | if (reloc->offset > obj->base.size - 4) { | |
3461 | DRM_ERROR("Relocation beyond object bounds: " | |
3462 | "obj %p target %d offset %d size %d.\n", | |
3463 | obj, reloc->target_handle, | |
3464 | (int) reloc->offset, | |
3465 | (int) obj->base.size); | |
3466 | goto err; | |
3467 | } | |
3468 | if (reloc->offset & 3) { | |
3469 | DRM_ERROR("Relocation not 4-byte aligned: " | |
3470 | "obj %p target %d offset %d.\n", | |
3471 | obj, reloc->target_handle, | |
3472 | (int) reloc->offset); | |
3473 | goto err; | |
3474 | } | |
673a394b | 3475 | |
bcf50e27 CW |
3476 | /* and points to somewhere within the target object. */ |
3477 | if (reloc->delta >= target_obj->size) { | |
3478 | DRM_ERROR("Relocation beyond target object bounds: " | |
3479 | "obj %p target %d delta %d size %d.\n", | |
3480 | obj, reloc->target_handle, | |
3481 | (int) reloc->delta, | |
3482 | (int) target_obj->size); | |
3483 | goto err; | |
3484 | } | |
673a394b | 3485 | |
bcf50e27 CW |
3486 | reloc->delta += target_offset; |
3487 | if (obj->base.write_domain == I915_GEM_DOMAIN_CPU) { | |
3488 | uint32_t page_offset = reloc->offset & ~PAGE_MASK; | |
3489 | char *vaddr; | |
673a394b | 3490 | |
bcf50e27 CW |
3491 | vaddr = kmap_atomic(obj->pages[reloc->offset >> PAGE_SHIFT]); |
3492 | *(uint32_t *)(vaddr + page_offset) = reloc->delta; | |
3493 | kunmap_atomic(vaddr); | |
3494 | } else { | |
3495 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3496 | uint32_t __iomem *reloc_entry; | |
3497 | void __iomem *reloc_page; | |
8542a0bb | 3498 | |
bcf50e27 CW |
3499 | ret = i915_gem_object_set_to_gtt_domain(&obj->base, 1); |
3500 | if (ret) | |
3501 | goto err; | |
673a394b | 3502 | |
bcf50e27 CW |
3503 | /* Map the page containing the relocation we're going to perform. */ |
3504 | reloc->offset += obj->gtt_offset; | |
3505 | reloc_page = io_mapping_map_atomic_wc(dev_priv->mm.gtt_mapping, | |
3506 | reloc->offset & PAGE_MASK); | |
3507 | reloc_entry = (uint32_t __iomem *) | |
3508 | (reloc_page + (reloc->offset & ~PAGE_MASK)); | |
3509 | iowrite32(reloc->delta, reloc_entry); | |
3510 | io_mapping_unmap_atomic(reloc_page); | |
3511 | } | |
673a394b | 3512 | |
bcf50e27 CW |
3513 | /* and update the user's relocation entry */ |
3514 | reloc->presumed_offset = target_offset; | |
b962442e | 3515 | |
bcf50e27 CW |
3516 | out: |
3517 | ret = 0; | |
3518 | err: | |
3519 | drm_gem_object_unreference(target_obj); | |
3520 | return ret; | |
3521 | } | |
b962442e | 3522 | |
bcf50e27 CW |
3523 | static int |
3524 | i915_gem_execbuffer_relocate_object(struct drm_i915_gem_object *obj, | |
3525 | struct drm_file *file_priv, | |
3526 | struct drm_i915_gem_exec_object2 *entry) | |
3527 | { | |
3528 | struct drm_i915_gem_relocation_entry __user *user_relocs; | |
3529 | int i, ret; | |
3530 | ||
3531 | user_relocs = (void __user *)(uintptr_t)entry->relocs_ptr; | |
3532 | for (i = 0; i < entry->relocation_count; i++) { | |
3533 | struct drm_i915_gem_relocation_entry reloc; | |
3534 | ||
3535 | if (__copy_from_user_inatomic(&reloc, | |
3536 | user_relocs+i, | |
3537 | sizeof(reloc))) | |
3538 | return -EFAULT; | |
3539 | ||
3540 | ret = i915_gem_execbuffer_relocate_entry(obj, file_priv, entry, &reloc); | |
3541 | if (ret) | |
3542 | return ret; | |
b962442e | 3543 | |
b5dc608c | 3544 | if (__copy_to_user_inatomic(&user_relocs[i].presumed_offset, |
bcf50e27 CW |
3545 | &reloc.presumed_offset, |
3546 | sizeof(reloc.presumed_offset))) | |
3547 | return -EFAULT; | |
b962442e | 3548 | } |
b962442e | 3549 | |
bcf50e27 CW |
3550 | return 0; |
3551 | } | |
3552 | ||
3553 | static int | |
3554 | i915_gem_execbuffer_relocate_object_slow(struct drm_i915_gem_object *obj, | |
3555 | struct drm_file *file_priv, | |
3556 | struct drm_i915_gem_exec_object2 *entry, | |
3557 | struct drm_i915_gem_relocation_entry *relocs) | |
3558 | { | |
3559 | int i, ret; | |
3560 | ||
3561 | for (i = 0; i < entry->relocation_count; i++) { | |
3562 | ret = i915_gem_execbuffer_relocate_entry(obj, file_priv, entry, &relocs[i]); | |
3563 | if (ret) | |
3564 | return ret; | |
3565 | } | |
3566 | ||
3567 | return 0; | |
673a394b EA |
3568 | } |
3569 | ||
40a5f0de | 3570 | static int |
bcf50e27 CW |
3571 | i915_gem_execbuffer_relocate(struct drm_device *dev, |
3572 | struct drm_file *file, | |
3573 | struct drm_gem_object **object_list, | |
3574 | struct drm_i915_gem_exec_object2 *exec_list, | |
3575 | int count) | |
3576 | { | |
3577 | int i, ret; | |
3578 | ||
3579 | for (i = 0; i < count; i++) { | |
3580 | struct drm_i915_gem_object *obj = to_intel_bo(object_list[i]); | |
3581 | obj->base.pending_read_domains = 0; | |
3582 | obj->base.pending_write_domain = 0; | |
3583 | ret = i915_gem_execbuffer_relocate_object(obj, file, | |
3584 | &exec_list[i]); | |
3585 | if (ret) | |
3586 | return ret; | |
3587 | } | |
3588 | ||
3589 | return 0; | |
673a394b EA |
3590 | } |
3591 | ||
40a5f0de | 3592 | static int |
bcf50e27 CW |
3593 | i915_gem_execbuffer_reserve(struct drm_device *dev, |
3594 | struct drm_file *file, | |
3595 | struct drm_gem_object **object_list, | |
3596 | struct drm_i915_gem_exec_object2 *exec_list, | |
3597 | int count) | |
40a5f0de | 3598 | { |
9af90d19 CW |
3599 | struct drm_i915_private *dev_priv = dev->dev_private; |
3600 | int ret, i, retry; | |
40a5f0de | 3601 | |
9af90d19 | 3602 | /* attempt to pin all of the buffers into the GTT */ |
5eac3ab4 CW |
3603 | retry = 0; |
3604 | do { | |
9af90d19 CW |
3605 | ret = 0; |
3606 | for (i = 0; i < count; i++) { | |
3607 | struct drm_i915_gem_exec_object2 *entry = &exec_list[i]; | |
16e809ac | 3608 | struct drm_i915_gem_object *obj = to_intel_bo(object_list[i]); |
9af90d19 CW |
3609 | bool need_fence = |
3610 | entry->flags & EXEC_OBJECT_NEEDS_FENCE && | |
3611 | obj->tiling_mode != I915_TILING_NONE; | |
3612 | ||
16e809ac DV |
3613 | /* g33/pnv can't fence buffers in the unmappable part */ |
3614 | bool need_mappable = | |
3615 | entry->relocation_count ? true : need_fence; | |
3616 | ||
9af90d19 | 3617 | /* Check fence reg constraints and rebind if necessary */ |
75e9e915 | 3618 | if (need_mappable && !obj->map_and_fenceable) { |
9af90d19 CW |
3619 | ret = i915_gem_object_unbind(&obj->base); |
3620 | if (ret) | |
3621 | break; | |
3622 | } | |
40a5f0de | 3623 | |
920afa77 | 3624 | ret = i915_gem_object_pin(&obj->base, |
16e809ac | 3625 | entry->alignment, |
75e9e915 | 3626 | need_mappable); |
9af90d19 CW |
3627 | if (ret) |
3628 | break; | |
40a5f0de | 3629 | |
9af90d19 CW |
3630 | /* |
3631 | * Pre-965 chips need a fence register set up in order | |
3632 | * to properly handle blits to/from tiled surfaces. | |
3633 | */ | |
3634 | if (need_fence) { | |
3635 | ret = i915_gem_object_get_fence_reg(&obj->base, true); | |
3636 | if (ret) { | |
3637 | i915_gem_object_unpin(&obj->base); | |
3638 | break; | |
3639 | } | |
40a5f0de | 3640 | |
9af90d19 CW |
3641 | dev_priv->fence_regs[obj->fence_reg].gpu = true; |
3642 | } | |
40a5f0de | 3643 | |
9af90d19 | 3644 | entry->offset = obj->gtt_offset; |
40a5f0de EA |
3645 | } |
3646 | ||
9af90d19 CW |
3647 | while (i--) |
3648 | i915_gem_object_unpin(object_list[i]); | |
3649 | ||
5eac3ab4 | 3650 | if (ret != -ENOSPC || retry > 1) |
9af90d19 CW |
3651 | return ret; |
3652 | ||
5eac3ab4 CW |
3653 | /* First attempt, just clear anything that is purgeable. |
3654 | * Second attempt, clear the entire GTT. | |
3655 | */ | |
3656 | ret = i915_gem_evict_everything(dev, retry == 0); | |
9af90d19 CW |
3657 | if (ret) |
3658 | return ret; | |
40a5f0de | 3659 | |
5eac3ab4 CW |
3660 | retry++; |
3661 | } while (1); | |
40a5f0de EA |
3662 | } |
3663 | ||
bcf50e27 CW |
3664 | static int |
3665 | i915_gem_execbuffer_relocate_slow(struct drm_device *dev, | |
3666 | struct drm_file *file, | |
3667 | struct drm_gem_object **object_list, | |
3668 | struct drm_i915_gem_exec_object2 *exec_list, | |
3669 | int count) | |
3670 | { | |
3671 | struct drm_i915_gem_relocation_entry *reloc; | |
3672 | int i, total, ret; | |
3673 | ||
3674 | for (i = 0; i < count; i++) { | |
3675 | struct drm_i915_gem_object *obj = to_intel_bo(object_list[i]); | |
3676 | obj->in_execbuffer = false; | |
3677 | } | |
3678 | ||
3679 | mutex_unlock(&dev->struct_mutex); | |
3680 | ||
3681 | total = 0; | |
3682 | for (i = 0; i < count; i++) | |
3683 | total += exec_list[i].relocation_count; | |
3684 | ||
3685 | reloc = drm_malloc_ab(total, sizeof(*reloc)); | |
3686 | if (reloc == NULL) { | |
3687 | mutex_lock(&dev->struct_mutex); | |
3688 | return -ENOMEM; | |
3689 | } | |
3690 | ||
3691 | total = 0; | |
3692 | for (i = 0; i < count; i++) { | |
3693 | struct drm_i915_gem_relocation_entry __user *user_relocs; | |
3694 | ||
3695 | user_relocs = (void __user *)(uintptr_t)exec_list[i].relocs_ptr; | |
3696 | ||
3697 | if (copy_from_user(reloc+total, user_relocs, | |
3698 | exec_list[i].relocation_count * | |
3699 | sizeof(*reloc))) { | |
3700 | ret = -EFAULT; | |
3701 | mutex_lock(&dev->struct_mutex); | |
3702 | goto err; | |
3703 | } | |
3704 | ||
3705 | total += exec_list[i].relocation_count; | |
3706 | } | |
3707 | ||
3708 | ret = i915_mutex_lock_interruptible(dev); | |
3709 | if (ret) { | |
3710 | mutex_lock(&dev->struct_mutex); | |
3711 | goto err; | |
3712 | } | |
3713 | ||
3714 | ret = i915_gem_execbuffer_reserve(dev, file, | |
3715 | object_list, exec_list, | |
3716 | count); | |
3717 | if (ret) | |
3718 | goto err; | |
3719 | ||
3720 | total = 0; | |
3721 | for (i = 0; i < count; i++) { | |
3722 | struct drm_i915_gem_object *obj = to_intel_bo(object_list[i]); | |
3723 | obj->base.pending_read_domains = 0; | |
3724 | obj->base.pending_write_domain = 0; | |
3725 | ret = i915_gem_execbuffer_relocate_object_slow(obj, file, | |
3726 | &exec_list[i], | |
3727 | reloc + total); | |
3728 | if (ret) | |
3729 | goto err; | |
3730 | ||
3731 | total += exec_list[i].relocation_count; | |
3732 | } | |
3733 | ||
3734 | /* Leave the user relocations as are, this is the painfully slow path, | |
3735 | * and we want to avoid the complication of dropping the lock whilst | |
3736 | * having buffers reserved in the aperture and so causing spurious | |
3737 | * ENOSPC for random operations. | |
3738 | */ | |
3739 | ||
3740 | err: | |
3741 | drm_free_large(reloc); | |
3742 | return ret; | |
3743 | } | |
3744 | ||
13b29289 CW |
3745 | static int |
3746 | i915_gem_execbuffer_move_to_gpu(struct drm_device *dev, | |
3747 | struct drm_file *file, | |
3748 | struct intel_ring_buffer *ring, | |
3749 | struct drm_gem_object **objects, | |
3750 | int count) | |
3751 | { | |
0f8c6d7c | 3752 | struct change_domains cd; |
13b29289 CW |
3753 | int ret, i; |
3754 | ||
0f8c6d7c CW |
3755 | cd.invalidate_domains = 0; |
3756 | cd.flush_domains = 0; | |
3757 | cd.flush_rings = 0; | |
13b29289 | 3758 | for (i = 0; i < count; i++) |
0f8c6d7c | 3759 | i915_gem_object_set_to_gpu_domain(objects[i], ring, &cd); |
13b29289 | 3760 | |
0f8c6d7c | 3761 | if (cd.invalidate_domains | cd.flush_domains) { |
13b29289 CW |
3762 | #if WATCH_EXEC |
3763 | DRM_INFO("%s: invalidate_domains %08x flush_domains %08x\n", | |
3764 | __func__, | |
0f8c6d7c CW |
3765 | cd.invalidate_domains, |
3766 | cd.flush_domains); | |
13b29289 CW |
3767 | #endif |
3768 | i915_gem_flush(dev, file, | |
0f8c6d7c CW |
3769 | cd.invalidate_domains, |
3770 | cd.flush_domains, | |
3771 | cd.flush_rings); | |
13b29289 CW |
3772 | } |
3773 | ||
3774 | for (i = 0; i < count; i++) { | |
3775 | struct drm_i915_gem_object *obj = to_intel_bo(objects[i]); | |
3776 | /* XXX replace with semaphores */ | |
3777 | if (obj->ring && ring != obj->ring) { | |
3778 | ret = i915_gem_object_wait_rendering(&obj->base, true); | |
3779 | if (ret) | |
3780 | return ret; | |
3781 | } | |
3782 | } | |
3783 | ||
3784 | return 0; | |
3785 | } | |
3786 | ||
673a394b EA |
3787 | /* Throttle our rendering by waiting until the ring has completed our requests |
3788 | * emitted over 20 msec ago. | |
3789 | * | |
b962442e EA |
3790 | * Note that if we were to use the current jiffies each time around the loop, |
3791 | * we wouldn't escape the function with any frames outstanding if the time to | |
3792 | * render a frame was over 20ms. | |
3793 | * | |
673a394b EA |
3794 | * This should get us reasonable parallelism between CPU and GPU but also |
3795 | * relatively low latency when blocking on a particular request to finish. | |
3796 | */ | |
40a5f0de | 3797 | static int |
f787a5f5 | 3798 | i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file) |
40a5f0de | 3799 | { |
f787a5f5 CW |
3800 | struct drm_i915_private *dev_priv = dev->dev_private; |
3801 | struct drm_i915_file_private *file_priv = file->driver_priv; | |
b962442e | 3802 | unsigned long recent_enough = jiffies - msecs_to_jiffies(20); |
f787a5f5 CW |
3803 | struct drm_i915_gem_request *request; |
3804 | struct intel_ring_buffer *ring = NULL; | |
3805 | u32 seqno = 0; | |
3806 | int ret; | |
93533c29 | 3807 | |
1c25595f | 3808 | spin_lock(&file_priv->mm.lock); |
f787a5f5 | 3809 | list_for_each_entry(request, &file_priv->mm.request_list, client_list) { |
b962442e EA |
3810 | if (time_after_eq(request->emitted_jiffies, recent_enough)) |
3811 | break; | |
40a5f0de | 3812 | |
f787a5f5 CW |
3813 | ring = request->ring; |
3814 | seqno = request->seqno; | |
b962442e | 3815 | } |
1c25595f | 3816 | spin_unlock(&file_priv->mm.lock); |
40a5f0de | 3817 | |
f787a5f5 CW |
3818 | if (seqno == 0) |
3819 | return 0; | |
2bc43b5c | 3820 | |
f787a5f5 | 3821 | ret = 0; |
78501eac | 3822 | if (!i915_seqno_passed(ring->get_seqno(ring), seqno)) { |
f787a5f5 CW |
3823 | /* And wait for the seqno passing without holding any locks and |
3824 | * causing extra latency for others. This is safe as the irq | |
3825 | * generation is designed to be run atomically and so is | |
3826 | * lockless. | |
3827 | */ | |
78501eac | 3828 | ring->user_irq_get(ring); |
f787a5f5 | 3829 | ret = wait_event_interruptible(ring->irq_queue, |
78501eac | 3830 | i915_seqno_passed(ring->get_seqno(ring), seqno) |
f787a5f5 | 3831 | || atomic_read(&dev_priv->mm.wedged)); |
78501eac | 3832 | ring->user_irq_put(ring); |
40a5f0de | 3833 | |
f787a5f5 CW |
3834 | if (ret == 0 && atomic_read(&dev_priv->mm.wedged)) |
3835 | ret = -EIO; | |
40a5f0de EA |
3836 | } |
3837 | ||
f787a5f5 CW |
3838 | if (ret == 0) |
3839 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, 0); | |
40a5f0de EA |
3840 | |
3841 | return ret; | |
3842 | } | |
3843 | ||
83d60795 | 3844 | static int |
2549d6c2 CW |
3845 | i915_gem_check_execbuffer(struct drm_i915_gem_execbuffer2 *exec, |
3846 | uint64_t exec_offset) | |
83d60795 CW |
3847 | { |
3848 | uint32_t exec_start, exec_len; | |
3849 | ||
3850 | exec_start = (uint32_t) exec_offset + exec->batch_start_offset; | |
3851 | exec_len = (uint32_t) exec->batch_len; | |
3852 | ||
3853 | if ((exec_start | exec_len) & 0x7) | |
3854 | return -EINVAL; | |
3855 | ||
3856 | if (!exec_start) | |
3857 | return -EINVAL; | |
3858 | ||
3859 | return 0; | |
3860 | } | |
3861 | ||
6b95a207 | 3862 | static int |
2549d6c2 CW |
3863 | validate_exec_list(struct drm_i915_gem_exec_object2 *exec, |
3864 | int count) | |
6b95a207 | 3865 | { |
2549d6c2 | 3866 | int i; |
6b95a207 | 3867 | |
2549d6c2 CW |
3868 | for (i = 0; i < count; i++) { |
3869 | char __user *ptr = (char __user *)(uintptr_t)exec[i].relocs_ptr; | |
d1d78830 | 3870 | int length; /* limited by fault_in_pages_readable() */ |
6b95a207 | 3871 | |
d1d78830 CW |
3872 | /* First check for malicious input causing overflow */ |
3873 | if (exec[i].relocation_count > | |
3874 | INT_MAX / sizeof(struct drm_i915_gem_relocation_entry)) | |
3875 | return -EINVAL; | |
6b95a207 | 3876 | |
d1d78830 CW |
3877 | length = exec[i].relocation_count * |
3878 | sizeof(struct drm_i915_gem_relocation_entry); | |
2549d6c2 CW |
3879 | if (!access_ok(VERIFY_READ, ptr, length)) |
3880 | return -EFAULT; | |
40a5f0de | 3881 | |
b5dc608c CW |
3882 | /* we may also need to update the presumed offsets */ |
3883 | if (!access_ok(VERIFY_WRITE, ptr, length)) | |
3884 | return -EFAULT; | |
3885 | ||
2549d6c2 CW |
3886 | if (fault_in_pages_readable(ptr, length)) |
3887 | return -EFAULT; | |
6b95a207 | 3888 | } |
6b95a207 | 3889 | |
83d60795 | 3890 | return 0; |
6b95a207 KH |
3891 | } |
3892 | ||
8dc5d147 | 3893 | static int |
76446cac | 3894 | i915_gem_do_execbuffer(struct drm_device *dev, void *data, |
9af90d19 | 3895 | struct drm_file *file, |
76446cac JB |
3896 | struct drm_i915_gem_execbuffer2 *args, |
3897 | struct drm_i915_gem_exec_object2 *exec_list) | |
673a394b EA |
3898 | { |
3899 | drm_i915_private_t *dev_priv = dev->dev_private; | |
673a394b EA |
3900 | struct drm_gem_object **object_list = NULL; |
3901 | struct drm_gem_object *batch_obj; | |
201361a5 | 3902 | struct drm_clip_rect *cliprects = NULL; |
8dc5d147 | 3903 | struct drm_i915_gem_request *request = NULL; |
9af90d19 | 3904 | int ret, i, flips; |
673a394b | 3905 | uint64_t exec_offset; |
673a394b | 3906 | |
852835f3 ZN |
3907 | struct intel_ring_buffer *ring = NULL; |
3908 | ||
30dbf0c0 CW |
3909 | ret = i915_gem_check_is_wedged(dev); |
3910 | if (ret) | |
3911 | return ret; | |
3912 | ||
2549d6c2 CW |
3913 | ret = validate_exec_list(exec_list, args->buffer_count); |
3914 | if (ret) | |
3915 | return ret; | |
3916 | ||
673a394b EA |
3917 | #if WATCH_EXEC |
3918 | DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n", | |
3919 | (int) args->buffers_ptr, args->buffer_count, args->batch_len); | |
3920 | #endif | |
549f7365 CW |
3921 | switch (args->flags & I915_EXEC_RING_MASK) { |
3922 | case I915_EXEC_DEFAULT: | |
3923 | case I915_EXEC_RENDER: | |
3924 | ring = &dev_priv->render_ring; | |
3925 | break; | |
3926 | case I915_EXEC_BSD: | |
d1b851fc | 3927 | if (!HAS_BSD(dev)) { |
549f7365 | 3928 | DRM_ERROR("execbuf with invalid ring (BSD)\n"); |
d1b851fc ZN |
3929 | return -EINVAL; |
3930 | } | |
3931 | ring = &dev_priv->bsd_ring; | |
549f7365 CW |
3932 | break; |
3933 | case I915_EXEC_BLT: | |
3934 | if (!HAS_BLT(dev)) { | |
3935 | DRM_ERROR("execbuf with invalid ring (BLT)\n"); | |
3936 | return -EINVAL; | |
3937 | } | |
3938 | ring = &dev_priv->blt_ring; | |
3939 | break; | |
3940 | default: | |
3941 | DRM_ERROR("execbuf with unknown ring: %d\n", | |
3942 | (int)(args->flags & I915_EXEC_RING_MASK)); | |
3943 | return -EINVAL; | |
d1b851fc ZN |
3944 | } |
3945 | ||
4f481ed2 EA |
3946 | if (args->buffer_count < 1) { |
3947 | DRM_ERROR("execbuf with %d buffers\n", args->buffer_count); | |
3948 | return -EINVAL; | |
3949 | } | |
c8e0f93a | 3950 | object_list = drm_malloc_ab(sizeof(*object_list), args->buffer_count); |
76446cac JB |
3951 | if (object_list == NULL) { |
3952 | DRM_ERROR("Failed to allocate object list for %d buffers\n", | |
673a394b EA |
3953 | args->buffer_count); |
3954 | ret = -ENOMEM; | |
3955 | goto pre_mutex_err; | |
3956 | } | |
673a394b | 3957 | |
201361a5 | 3958 | if (args->num_cliprects != 0) { |
9a298b2a EA |
3959 | cliprects = kcalloc(args->num_cliprects, sizeof(*cliprects), |
3960 | GFP_KERNEL); | |
a40e8d31 OA |
3961 | if (cliprects == NULL) { |
3962 | ret = -ENOMEM; | |
201361a5 | 3963 | goto pre_mutex_err; |
a40e8d31 | 3964 | } |
201361a5 EA |
3965 | |
3966 | ret = copy_from_user(cliprects, | |
3967 | (struct drm_clip_rect __user *) | |
3968 | (uintptr_t) args->cliprects_ptr, | |
3969 | sizeof(*cliprects) * args->num_cliprects); | |
3970 | if (ret != 0) { | |
3971 | DRM_ERROR("copy %d cliprects failed: %d\n", | |
3972 | args->num_cliprects, ret); | |
c877cdce | 3973 | ret = -EFAULT; |
201361a5 EA |
3974 | goto pre_mutex_err; |
3975 | } | |
3976 | } | |
3977 | ||
8dc5d147 CW |
3978 | request = kzalloc(sizeof(*request), GFP_KERNEL); |
3979 | if (request == NULL) { | |
3980 | ret = -ENOMEM; | |
40a5f0de | 3981 | goto pre_mutex_err; |
8dc5d147 | 3982 | } |
40a5f0de | 3983 | |
76c1dec1 CW |
3984 | ret = i915_mutex_lock_interruptible(dev); |
3985 | if (ret) | |
a198bc80 | 3986 | goto pre_mutex_err; |
673a394b EA |
3987 | |
3988 | if (dev_priv->mm.suspended) { | |
673a394b | 3989 | mutex_unlock(&dev->struct_mutex); |
a198bc80 CW |
3990 | ret = -EBUSY; |
3991 | goto pre_mutex_err; | |
673a394b EA |
3992 | } |
3993 | ||
ac94a962 | 3994 | /* Look up object handles */ |
673a394b | 3995 | for (i = 0; i < args->buffer_count; i++) { |
7e318e18 CW |
3996 | struct drm_i915_gem_object *obj_priv; |
3997 | ||
9af90d19 | 3998 | object_list[i] = drm_gem_object_lookup(dev, file, |
673a394b EA |
3999 | exec_list[i].handle); |
4000 | if (object_list[i] == NULL) { | |
4001 | DRM_ERROR("Invalid object handle %d at index %d\n", | |
4002 | exec_list[i].handle, i); | |
0ce907f8 CW |
4003 | /* prevent error path from reading uninitialized data */ |
4004 | args->buffer_count = i + 1; | |
bf79cb91 | 4005 | ret = -ENOENT; |
673a394b EA |
4006 | goto err; |
4007 | } | |
b70d11da | 4008 | |
23010e43 | 4009 | obj_priv = to_intel_bo(object_list[i]); |
b70d11da KH |
4010 | if (obj_priv->in_execbuffer) { |
4011 | DRM_ERROR("Object %p appears more than once in object list\n", | |
4012 | object_list[i]); | |
0ce907f8 CW |
4013 | /* prevent error path from reading uninitialized data */ |
4014 | args->buffer_count = i + 1; | |
bf79cb91 | 4015 | ret = -EINVAL; |
b70d11da KH |
4016 | goto err; |
4017 | } | |
4018 | obj_priv->in_execbuffer = true; | |
ac94a962 | 4019 | } |
673a394b | 4020 | |
9af90d19 | 4021 | /* Move the objects en-masse into the GTT, evicting if necessary. */ |
bcf50e27 CW |
4022 | ret = i915_gem_execbuffer_reserve(dev, file, |
4023 | object_list, exec_list, | |
4024 | args->buffer_count); | |
9af90d19 CW |
4025 | if (ret) |
4026 | goto err; | |
ac94a962 | 4027 | |
9af90d19 | 4028 | /* The objects are in their final locations, apply the relocations. */ |
bcf50e27 CW |
4029 | ret = i915_gem_execbuffer_relocate(dev, file, |
4030 | object_list, exec_list, | |
4031 | args->buffer_count); | |
4032 | if (ret) { | |
4033 | if (ret == -EFAULT) { | |
4034 | ret = i915_gem_execbuffer_relocate_slow(dev, file, | |
4035 | object_list, | |
4036 | exec_list, | |
4037 | args->buffer_count); | |
4038 | BUG_ON(!mutex_is_locked(&dev->struct_mutex)); | |
4039 | } | |
9af90d19 | 4040 | if (ret) |
ac94a962 | 4041 | goto err; |
673a394b EA |
4042 | } |
4043 | ||
4044 | /* Set the pending read domains for the batch buffer to COMMAND */ | |
4045 | batch_obj = object_list[args->buffer_count-1]; | |
5f26a2c7 CW |
4046 | if (batch_obj->pending_write_domain) { |
4047 | DRM_ERROR("Attempting to use self-modifying batch buffer\n"); | |
4048 | ret = -EINVAL; | |
4049 | goto err; | |
4050 | } | |
4051 | batch_obj->pending_read_domains |= I915_GEM_DOMAIN_COMMAND; | |
673a394b | 4052 | |
9af90d19 CW |
4053 | /* Sanity check the batch buffer */ |
4054 | exec_offset = to_intel_bo(batch_obj)->gtt_offset; | |
4055 | ret = i915_gem_check_execbuffer(args, exec_offset); | |
83d60795 CW |
4056 | if (ret != 0) { |
4057 | DRM_ERROR("execbuf with invalid offset/length\n"); | |
4058 | goto err; | |
4059 | } | |
4060 | ||
13b29289 CW |
4061 | ret = i915_gem_execbuffer_move_to_gpu(dev, file, ring, |
4062 | object_list, args->buffer_count); | |
4063 | if (ret) | |
4064 | goto err; | |
673a394b | 4065 | |
673a394b EA |
4066 | #if WATCH_COHERENCY |
4067 | for (i = 0; i < args->buffer_count; i++) { | |
4068 | i915_gem_object_check_coherency(object_list[i], | |
4069 | exec_list[i].handle); | |
4070 | } | |
4071 | #endif | |
4072 | ||
673a394b | 4073 | #if WATCH_EXEC |
6911a9b8 | 4074 | i915_gem_dump_object(batch_obj, |
673a394b EA |
4075 | args->batch_len, |
4076 | __func__, | |
4077 | ~0); | |
4078 | #endif | |
4079 | ||
e59f2bac CW |
4080 | /* Check for any pending flips. As we only maintain a flip queue depth |
4081 | * of 1, we can simply insert a WAIT for the next display flip prior | |
4082 | * to executing the batch and avoid stalling the CPU. | |
4083 | */ | |
4084 | flips = 0; | |
4085 | for (i = 0; i < args->buffer_count; i++) { | |
4086 | if (object_list[i]->write_domain) | |
4087 | flips |= atomic_read(&to_intel_bo(object_list[i])->pending_flip); | |
4088 | } | |
4089 | if (flips) { | |
4090 | int plane, flip_mask; | |
4091 | ||
4092 | for (plane = 0; flips >> plane; plane++) { | |
4093 | if (((flips >> plane) & 1) == 0) | |
4094 | continue; | |
4095 | ||
4096 | if (plane) | |
4097 | flip_mask = MI_WAIT_FOR_PLANE_B_FLIP; | |
4098 | else | |
4099 | flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; | |
4100 | ||
e1f99ce6 CW |
4101 | ret = intel_ring_begin(ring, 2); |
4102 | if (ret) | |
4103 | goto err; | |
4104 | ||
78501eac CW |
4105 | intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask); |
4106 | intel_ring_emit(ring, MI_NOOP); | |
4107 | intel_ring_advance(ring); | |
e59f2bac CW |
4108 | } |
4109 | } | |
4110 | ||
673a394b | 4111 | /* Exec the batchbuffer */ |
78501eac | 4112 | ret = ring->dispatch_execbuffer(ring, args, cliprects, exec_offset); |
673a394b EA |
4113 | if (ret) { |
4114 | DRM_ERROR("dispatch failed %d\n", ret); | |
4115 | goto err; | |
4116 | } | |
4117 | ||
673a394b EA |
4118 | for (i = 0; i < args->buffer_count; i++) { |
4119 | struct drm_gem_object *obj = object_list[i]; | |
673a394b | 4120 | |
7e318e18 CW |
4121 | obj->read_domains = obj->pending_read_domains; |
4122 | obj->write_domain = obj->pending_write_domain; | |
4123 | ||
617dbe27 | 4124 | i915_gem_object_move_to_active(obj, ring); |
7e318e18 CW |
4125 | if (obj->write_domain) { |
4126 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); | |
4127 | obj_priv->dirty = 1; | |
4128 | list_move_tail(&obj_priv->gpu_write_list, | |
64193406 | 4129 | &ring->gpu_write_list); |
7e318e18 CW |
4130 | intel_mark_busy(dev, obj); |
4131 | } | |
4132 | ||
4133 | trace_i915_gem_object_change_domain(obj, | |
4134 | obj->read_domains, | |
4135 | obj->write_domain); | |
673a394b | 4136 | } |
673a394b | 4137 | |
7e318e18 CW |
4138 | /* |
4139 | * Ensure that the commands in the batch buffer are | |
4140 | * finished before the interrupt fires | |
4141 | */ | |
4142 | i915_retire_commands(dev, ring); | |
4143 | ||
3cce469c | 4144 | if (i915_add_request(dev, file, request, ring)) |
5d97eb69 | 4145 | i915_gem_next_request_seqno(dev, ring); |
3cce469c CW |
4146 | else |
4147 | request = NULL; | |
673a394b | 4148 | |
673a394b | 4149 | err: |
b70d11da | 4150 | for (i = 0; i < args->buffer_count; i++) { |
7e318e18 CW |
4151 | if (object_list[i] == NULL) |
4152 | break; | |
4153 | ||
4154 | to_intel_bo(object_list[i])->in_execbuffer = false; | |
aad87dff | 4155 | drm_gem_object_unreference(object_list[i]); |
b70d11da | 4156 | } |
673a394b | 4157 | |
673a394b EA |
4158 | mutex_unlock(&dev->struct_mutex); |
4159 | ||
93533c29 | 4160 | pre_mutex_err: |
8e7d2b2c | 4161 | drm_free_large(object_list); |
9a298b2a | 4162 | kfree(cliprects); |
8dc5d147 | 4163 | kfree(request); |
673a394b EA |
4164 | |
4165 | return ret; | |
4166 | } | |
4167 | ||
76446cac JB |
4168 | /* |
4169 | * Legacy execbuffer just creates an exec2 list from the original exec object | |
4170 | * list array and passes it to the real function. | |
4171 | */ | |
4172 | int | |
4173 | i915_gem_execbuffer(struct drm_device *dev, void *data, | |
4174 | struct drm_file *file_priv) | |
4175 | { | |
4176 | struct drm_i915_gem_execbuffer *args = data; | |
4177 | struct drm_i915_gem_execbuffer2 exec2; | |
4178 | struct drm_i915_gem_exec_object *exec_list = NULL; | |
4179 | struct drm_i915_gem_exec_object2 *exec2_list = NULL; | |
4180 | int ret, i; | |
4181 | ||
4182 | #if WATCH_EXEC | |
4183 | DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n", | |
4184 | (int) args->buffers_ptr, args->buffer_count, args->batch_len); | |
4185 | #endif | |
4186 | ||
4187 | if (args->buffer_count < 1) { | |
4188 | DRM_ERROR("execbuf with %d buffers\n", args->buffer_count); | |
4189 | return -EINVAL; | |
4190 | } | |
4191 | ||
4192 | /* Copy in the exec list from userland */ | |
4193 | exec_list = drm_malloc_ab(sizeof(*exec_list), args->buffer_count); | |
4194 | exec2_list = drm_malloc_ab(sizeof(*exec2_list), args->buffer_count); | |
4195 | if (exec_list == NULL || exec2_list == NULL) { | |
4196 | DRM_ERROR("Failed to allocate exec list for %d buffers\n", | |
4197 | args->buffer_count); | |
4198 | drm_free_large(exec_list); | |
4199 | drm_free_large(exec2_list); | |
4200 | return -ENOMEM; | |
4201 | } | |
4202 | ret = copy_from_user(exec_list, | |
4203 | (struct drm_i915_relocation_entry __user *) | |
4204 | (uintptr_t) args->buffers_ptr, | |
4205 | sizeof(*exec_list) * args->buffer_count); | |
4206 | if (ret != 0) { | |
4207 | DRM_ERROR("copy %d exec entries failed %d\n", | |
4208 | args->buffer_count, ret); | |
4209 | drm_free_large(exec_list); | |
4210 | drm_free_large(exec2_list); | |
4211 | return -EFAULT; | |
4212 | } | |
4213 | ||
4214 | for (i = 0; i < args->buffer_count; i++) { | |
4215 | exec2_list[i].handle = exec_list[i].handle; | |
4216 | exec2_list[i].relocation_count = exec_list[i].relocation_count; | |
4217 | exec2_list[i].relocs_ptr = exec_list[i].relocs_ptr; | |
4218 | exec2_list[i].alignment = exec_list[i].alignment; | |
4219 | exec2_list[i].offset = exec_list[i].offset; | |
a6c45cf0 | 4220 | if (INTEL_INFO(dev)->gen < 4) |
76446cac JB |
4221 | exec2_list[i].flags = EXEC_OBJECT_NEEDS_FENCE; |
4222 | else | |
4223 | exec2_list[i].flags = 0; | |
4224 | } | |
4225 | ||
4226 | exec2.buffers_ptr = args->buffers_ptr; | |
4227 | exec2.buffer_count = args->buffer_count; | |
4228 | exec2.batch_start_offset = args->batch_start_offset; | |
4229 | exec2.batch_len = args->batch_len; | |
4230 | exec2.DR1 = args->DR1; | |
4231 | exec2.DR4 = args->DR4; | |
4232 | exec2.num_cliprects = args->num_cliprects; | |
4233 | exec2.cliprects_ptr = args->cliprects_ptr; | |
852835f3 | 4234 | exec2.flags = I915_EXEC_RENDER; |
76446cac JB |
4235 | |
4236 | ret = i915_gem_do_execbuffer(dev, data, file_priv, &exec2, exec2_list); | |
4237 | if (!ret) { | |
4238 | /* Copy the new buffer offsets back to the user's exec list. */ | |
4239 | for (i = 0; i < args->buffer_count; i++) | |
4240 | exec_list[i].offset = exec2_list[i].offset; | |
4241 | /* ... and back out to userspace */ | |
4242 | ret = copy_to_user((struct drm_i915_relocation_entry __user *) | |
4243 | (uintptr_t) args->buffers_ptr, | |
4244 | exec_list, | |
4245 | sizeof(*exec_list) * args->buffer_count); | |
4246 | if (ret) { | |
4247 | ret = -EFAULT; | |
4248 | DRM_ERROR("failed to copy %d exec entries " | |
4249 | "back to user (%d)\n", | |
4250 | args->buffer_count, ret); | |
4251 | } | |
76446cac JB |
4252 | } |
4253 | ||
4254 | drm_free_large(exec_list); | |
4255 | drm_free_large(exec2_list); | |
4256 | return ret; | |
4257 | } | |
4258 | ||
4259 | int | |
4260 | i915_gem_execbuffer2(struct drm_device *dev, void *data, | |
4261 | struct drm_file *file_priv) | |
4262 | { | |
4263 | struct drm_i915_gem_execbuffer2 *args = data; | |
4264 | struct drm_i915_gem_exec_object2 *exec2_list = NULL; | |
4265 | int ret; | |
4266 | ||
4267 | #if WATCH_EXEC | |
4268 | DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n", | |
4269 | (int) args->buffers_ptr, args->buffer_count, args->batch_len); | |
4270 | #endif | |
4271 | ||
4272 | if (args->buffer_count < 1) { | |
4273 | DRM_ERROR("execbuf2 with %d buffers\n", args->buffer_count); | |
4274 | return -EINVAL; | |
4275 | } | |
4276 | ||
4277 | exec2_list = drm_malloc_ab(sizeof(*exec2_list), args->buffer_count); | |
4278 | if (exec2_list == NULL) { | |
4279 | DRM_ERROR("Failed to allocate exec list for %d buffers\n", | |
4280 | args->buffer_count); | |
4281 | return -ENOMEM; | |
4282 | } | |
4283 | ret = copy_from_user(exec2_list, | |
4284 | (struct drm_i915_relocation_entry __user *) | |
4285 | (uintptr_t) args->buffers_ptr, | |
4286 | sizeof(*exec2_list) * args->buffer_count); | |
4287 | if (ret != 0) { | |
4288 | DRM_ERROR("copy %d exec entries failed %d\n", | |
4289 | args->buffer_count, ret); | |
4290 | drm_free_large(exec2_list); | |
4291 | return -EFAULT; | |
4292 | } | |
4293 | ||
4294 | ret = i915_gem_do_execbuffer(dev, data, file_priv, args, exec2_list); | |
4295 | if (!ret) { | |
4296 | /* Copy the new buffer offsets back to the user's exec list. */ | |
4297 | ret = copy_to_user((struct drm_i915_relocation_entry __user *) | |
4298 | (uintptr_t) args->buffers_ptr, | |
4299 | exec2_list, | |
4300 | sizeof(*exec2_list) * args->buffer_count); | |
4301 | if (ret) { | |
4302 | ret = -EFAULT; | |
4303 | DRM_ERROR("failed to copy %d exec entries " | |
4304 | "back to user (%d)\n", | |
4305 | args->buffer_count, ret); | |
4306 | } | |
4307 | } | |
4308 | ||
4309 | drm_free_large(exec2_list); | |
4310 | return ret; | |
4311 | } | |
4312 | ||
673a394b | 4313 | int |
920afa77 | 4314 | i915_gem_object_pin(struct drm_gem_object *obj, uint32_t alignment, |
75e9e915 | 4315 | bool map_and_fenceable) |
673a394b EA |
4316 | { |
4317 | struct drm_device *dev = obj->dev; | |
f13d3f73 | 4318 | struct drm_i915_private *dev_priv = dev->dev_private; |
23010e43 | 4319 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
673a394b EA |
4320 | int ret; |
4321 | ||
778c3544 | 4322 | BUG_ON(obj_priv->pin_count == DRM_I915_GEM_OBJECT_MAX_PIN_COUNT); |
75e9e915 | 4323 | BUG_ON(map_and_fenceable && !map_and_fenceable); |
23bc5982 | 4324 | WARN_ON(i915_verify_lists(dev)); |
ac0c6b5a CW |
4325 | |
4326 | if (obj_priv->gtt_space != NULL) { | |
a00b10c3 | 4327 | if ((alignment && obj_priv->gtt_offset & (alignment - 1)) || |
75e9e915 | 4328 | (map_and_fenceable && !obj_priv->map_and_fenceable)) { |
ae7d49d8 CW |
4329 | WARN(obj_priv->pin_count, |
4330 | "bo is already pinned with incorrect alignment:" | |
75e9e915 DV |
4331 | " offset=%x, req.alignment=%x, req.map_and_fenceable=%d," |
4332 | " obj->map_and_fenceable=%d\n", | |
a00b10c3 | 4333 | obj_priv->gtt_offset, alignment, |
75e9e915 DV |
4334 | map_and_fenceable, |
4335 | obj_priv->map_and_fenceable); | |
ac0c6b5a CW |
4336 | ret = i915_gem_object_unbind(obj); |
4337 | if (ret) | |
4338 | return ret; | |
4339 | } | |
4340 | } | |
4341 | ||
673a394b | 4342 | if (obj_priv->gtt_space == NULL) { |
a00b10c3 | 4343 | ret = i915_gem_object_bind_to_gtt(obj, alignment, |
75e9e915 | 4344 | map_and_fenceable); |
9731129c | 4345 | if (ret) |
673a394b | 4346 | return ret; |
22c344e9 | 4347 | } |
76446cac | 4348 | |
7465378f | 4349 | if (obj_priv->pin_count++ == 0) { |
75e9e915 | 4350 | i915_gem_info_add_pin(dev_priv, obj_priv, map_and_fenceable); |
f13d3f73 | 4351 | if (!obj_priv->active) |
69dc4987 | 4352 | list_move_tail(&obj_priv->mm_list, |
f13d3f73 | 4353 | &dev_priv->mm.pinned_list); |
673a394b | 4354 | } |
75e9e915 | 4355 | BUG_ON(!obj_priv->pin_mappable && map_and_fenceable); |
673a394b | 4356 | |
23bc5982 | 4357 | WARN_ON(i915_verify_lists(dev)); |
673a394b EA |
4358 | return 0; |
4359 | } | |
4360 | ||
4361 | void | |
4362 | i915_gem_object_unpin(struct drm_gem_object *obj) | |
4363 | { | |
4364 | struct drm_device *dev = obj->dev; | |
4365 | drm_i915_private_t *dev_priv = dev->dev_private; | |
23010e43 | 4366 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
673a394b | 4367 | |
23bc5982 | 4368 | WARN_ON(i915_verify_lists(dev)); |
7465378f | 4369 | BUG_ON(obj_priv->pin_count == 0); |
673a394b EA |
4370 | BUG_ON(obj_priv->gtt_space == NULL); |
4371 | ||
7465378f | 4372 | if (--obj_priv->pin_count == 0) { |
f13d3f73 | 4373 | if (!obj_priv->active) |
69dc4987 | 4374 | list_move_tail(&obj_priv->mm_list, |
673a394b | 4375 | &dev_priv->mm.inactive_list); |
a00b10c3 | 4376 | i915_gem_info_remove_pin(dev_priv, obj_priv); |
673a394b | 4377 | } |
23bc5982 | 4378 | WARN_ON(i915_verify_lists(dev)); |
673a394b EA |
4379 | } |
4380 | ||
4381 | int | |
4382 | i915_gem_pin_ioctl(struct drm_device *dev, void *data, | |
4383 | struct drm_file *file_priv) | |
4384 | { | |
4385 | struct drm_i915_gem_pin *args = data; | |
4386 | struct drm_gem_object *obj; | |
4387 | struct drm_i915_gem_object *obj_priv; | |
4388 | int ret; | |
4389 | ||
1d7cfea1 CW |
4390 | ret = i915_mutex_lock_interruptible(dev); |
4391 | if (ret) | |
4392 | return ret; | |
673a394b EA |
4393 | |
4394 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); | |
4395 | if (obj == NULL) { | |
1d7cfea1 CW |
4396 | ret = -ENOENT; |
4397 | goto unlock; | |
673a394b | 4398 | } |
23010e43 | 4399 | obj_priv = to_intel_bo(obj); |
673a394b | 4400 | |
bb6baf76 CW |
4401 | if (obj_priv->madv != I915_MADV_WILLNEED) { |
4402 | DRM_ERROR("Attempting to pin a purgeable buffer\n"); | |
1d7cfea1 CW |
4403 | ret = -EINVAL; |
4404 | goto out; | |
3ef94daa CW |
4405 | } |
4406 | ||
79e53945 JB |
4407 | if (obj_priv->pin_filp != NULL && obj_priv->pin_filp != file_priv) { |
4408 | DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n", | |
4409 | args->handle); | |
1d7cfea1 CW |
4410 | ret = -EINVAL; |
4411 | goto out; | |
79e53945 JB |
4412 | } |
4413 | ||
4414 | obj_priv->user_pin_count++; | |
4415 | obj_priv->pin_filp = file_priv; | |
4416 | if (obj_priv->user_pin_count == 1) { | |
75e9e915 | 4417 | ret = i915_gem_object_pin(obj, args->alignment, true); |
1d7cfea1 CW |
4418 | if (ret) |
4419 | goto out; | |
673a394b EA |
4420 | } |
4421 | ||
4422 | /* XXX - flush the CPU caches for pinned objects | |
4423 | * as the X server doesn't manage domains yet | |
4424 | */ | |
e47c68e9 | 4425 | i915_gem_object_flush_cpu_write_domain(obj); |
673a394b | 4426 | args->offset = obj_priv->gtt_offset; |
1d7cfea1 | 4427 | out: |
673a394b | 4428 | drm_gem_object_unreference(obj); |
1d7cfea1 | 4429 | unlock: |
673a394b | 4430 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 4431 | return ret; |
673a394b EA |
4432 | } |
4433 | ||
4434 | int | |
4435 | i915_gem_unpin_ioctl(struct drm_device *dev, void *data, | |
4436 | struct drm_file *file_priv) | |
4437 | { | |
4438 | struct drm_i915_gem_pin *args = data; | |
4439 | struct drm_gem_object *obj; | |
79e53945 | 4440 | struct drm_i915_gem_object *obj_priv; |
76c1dec1 | 4441 | int ret; |
673a394b | 4442 | |
1d7cfea1 CW |
4443 | ret = i915_mutex_lock_interruptible(dev); |
4444 | if (ret) | |
4445 | return ret; | |
673a394b EA |
4446 | |
4447 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); | |
4448 | if (obj == NULL) { | |
1d7cfea1 CW |
4449 | ret = -ENOENT; |
4450 | goto unlock; | |
673a394b | 4451 | } |
23010e43 | 4452 | obj_priv = to_intel_bo(obj); |
76c1dec1 | 4453 | |
79e53945 JB |
4454 | if (obj_priv->pin_filp != file_priv) { |
4455 | DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n", | |
4456 | args->handle); | |
1d7cfea1 CW |
4457 | ret = -EINVAL; |
4458 | goto out; | |
79e53945 JB |
4459 | } |
4460 | obj_priv->user_pin_count--; | |
4461 | if (obj_priv->user_pin_count == 0) { | |
4462 | obj_priv->pin_filp = NULL; | |
4463 | i915_gem_object_unpin(obj); | |
4464 | } | |
673a394b | 4465 | |
1d7cfea1 | 4466 | out: |
673a394b | 4467 | drm_gem_object_unreference(obj); |
1d7cfea1 | 4468 | unlock: |
673a394b | 4469 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 4470 | return ret; |
673a394b EA |
4471 | } |
4472 | ||
4473 | int | |
4474 | i915_gem_busy_ioctl(struct drm_device *dev, void *data, | |
4475 | struct drm_file *file_priv) | |
4476 | { | |
4477 | struct drm_i915_gem_busy *args = data; | |
4478 | struct drm_gem_object *obj; | |
4479 | struct drm_i915_gem_object *obj_priv; | |
30dbf0c0 CW |
4480 | int ret; |
4481 | ||
76c1dec1 | 4482 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 4483 | if (ret) |
76c1dec1 | 4484 | return ret; |
673a394b | 4485 | |
673a394b EA |
4486 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); |
4487 | if (obj == NULL) { | |
1d7cfea1 CW |
4488 | ret = -ENOENT; |
4489 | goto unlock; | |
673a394b | 4490 | } |
1d7cfea1 | 4491 | obj_priv = to_intel_bo(obj); |
d1b851fc | 4492 | |
0be555b6 CW |
4493 | /* Count all active objects as busy, even if they are currently not used |
4494 | * by the gpu. Users of this interface expect objects to eventually | |
4495 | * become non-busy without any further actions, therefore emit any | |
4496 | * necessary flushes here. | |
c4de0a5d | 4497 | */ |
0be555b6 CW |
4498 | args->busy = obj_priv->active; |
4499 | if (args->busy) { | |
4500 | /* Unconditionally flush objects, even when the gpu still uses this | |
4501 | * object. Userspace calling this function indicates that it wants to | |
4502 | * use this buffer rather sooner than later, so issuing the required | |
4503 | * flush earlier is beneficial. | |
4504 | */ | |
c78ec30b CW |
4505 | if (obj->write_domain & I915_GEM_GPU_DOMAINS) |
4506 | i915_gem_flush_ring(dev, file_priv, | |
9220434a CW |
4507 | obj_priv->ring, |
4508 | 0, obj->write_domain); | |
0be555b6 CW |
4509 | |
4510 | /* Update the active list for the hardware's current position. | |
4511 | * Otherwise this only updates on a delayed timer or when irqs | |
4512 | * are actually unmasked, and our working set ends up being | |
4513 | * larger than required. | |
4514 | */ | |
4515 | i915_gem_retire_requests_ring(dev, obj_priv->ring); | |
4516 | ||
4517 | args->busy = obj_priv->active; | |
4518 | } | |
673a394b EA |
4519 | |
4520 | drm_gem_object_unreference(obj); | |
1d7cfea1 | 4521 | unlock: |
673a394b | 4522 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 4523 | return ret; |
673a394b EA |
4524 | } |
4525 | ||
4526 | int | |
4527 | i915_gem_throttle_ioctl(struct drm_device *dev, void *data, | |
4528 | struct drm_file *file_priv) | |
4529 | { | |
4530 | return i915_gem_ring_throttle(dev, file_priv); | |
4531 | } | |
4532 | ||
3ef94daa CW |
4533 | int |
4534 | i915_gem_madvise_ioctl(struct drm_device *dev, void *data, | |
4535 | struct drm_file *file_priv) | |
4536 | { | |
4537 | struct drm_i915_gem_madvise *args = data; | |
4538 | struct drm_gem_object *obj; | |
4539 | struct drm_i915_gem_object *obj_priv; | |
76c1dec1 | 4540 | int ret; |
3ef94daa CW |
4541 | |
4542 | switch (args->madv) { | |
4543 | case I915_MADV_DONTNEED: | |
4544 | case I915_MADV_WILLNEED: | |
4545 | break; | |
4546 | default: | |
4547 | return -EINVAL; | |
4548 | } | |
4549 | ||
1d7cfea1 CW |
4550 | ret = i915_mutex_lock_interruptible(dev); |
4551 | if (ret) | |
4552 | return ret; | |
4553 | ||
3ef94daa CW |
4554 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); |
4555 | if (obj == NULL) { | |
1d7cfea1 CW |
4556 | ret = -ENOENT; |
4557 | goto unlock; | |
3ef94daa | 4558 | } |
23010e43 | 4559 | obj_priv = to_intel_bo(obj); |
3ef94daa CW |
4560 | |
4561 | if (obj_priv->pin_count) { | |
1d7cfea1 CW |
4562 | ret = -EINVAL; |
4563 | goto out; | |
3ef94daa CW |
4564 | } |
4565 | ||
bb6baf76 CW |
4566 | if (obj_priv->madv != __I915_MADV_PURGED) |
4567 | obj_priv->madv = args->madv; | |
3ef94daa | 4568 | |
2d7ef395 CW |
4569 | /* if the object is no longer bound, discard its backing storage */ |
4570 | if (i915_gem_object_is_purgeable(obj_priv) && | |
4571 | obj_priv->gtt_space == NULL) | |
4572 | i915_gem_object_truncate(obj); | |
4573 | ||
bb6baf76 CW |
4574 | args->retained = obj_priv->madv != __I915_MADV_PURGED; |
4575 | ||
1d7cfea1 | 4576 | out: |
3ef94daa | 4577 | drm_gem_object_unreference(obj); |
1d7cfea1 | 4578 | unlock: |
3ef94daa | 4579 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 4580 | return ret; |
3ef94daa CW |
4581 | } |
4582 | ||
ac52bc56 DV |
4583 | struct drm_gem_object * i915_gem_alloc_object(struct drm_device *dev, |
4584 | size_t size) | |
4585 | { | |
73aa808f | 4586 | struct drm_i915_private *dev_priv = dev->dev_private; |
c397b908 | 4587 | struct drm_i915_gem_object *obj; |
ac52bc56 | 4588 | |
c397b908 DV |
4589 | obj = kzalloc(sizeof(*obj), GFP_KERNEL); |
4590 | if (obj == NULL) | |
4591 | return NULL; | |
673a394b | 4592 | |
c397b908 DV |
4593 | if (drm_gem_object_init(dev, &obj->base, size) != 0) { |
4594 | kfree(obj); | |
4595 | return NULL; | |
4596 | } | |
673a394b | 4597 | |
73aa808f CW |
4598 | i915_gem_info_add_obj(dev_priv, size); |
4599 | ||
c397b908 DV |
4600 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; |
4601 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; | |
673a394b | 4602 | |
c397b908 | 4603 | obj->agp_type = AGP_USER_MEMORY; |
62b8b215 | 4604 | obj->base.driver_private = NULL; |
c397b908 | 4605 | obj->fence_reg = I915_FENCE_REG_NONE; |
69dc4987 CW |
4606 | INIT_LIST_HEAD(&obj->mm_list); |
4607 | INIT_LIST_HEAD(&obj->ring_list); | |
c397b908 | 4608 | INIT_LIST_HEAD(&obj->gpu_write_list); |
c397b908 | 4609 | obj->madv = I915_MADV_WILLNEED; |
75e9e915 DV |
4610 | /* Avoid an unnecessary call to unbind on the first bind. */ |
4611 | obj->map_and_fenceable = true; | |
de151cf6 | 4612 | |
c397b908 DV |
4613 | return &obj->base; |
4614 | } | |
4615 | ||
4616 | int i915_gem_init_object(struct drm_gem_object *obj) | |
4617 | { | |
4618 | BUG(); | |
de151cf6 | 4619 | |
673a394b EA |
4620 | return 0; |
4621 | } | |
4622 | ||
be72615b | 4623 | static void i915_gem_free_object_tail(struct drm_gem_object *obj) |
673a394b | 4624 | { |
de151cf6 | 4625 | struct drm_device *dev = obj->dev; |
be72615b | 4626 | drm_i915_private_t *dev_priv = dev->dev_private; |
23010e43 | 4627 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
be72615b | 4628 | int ret; |
673a394b | 4629 | |
be72615b CW |
4630 | ret = i915_gem_object_unbind(obj); |
4631 | if (ret == -ERESTARTSYS) { | |
69dc4987 | 4632 | list_move(&obj_priv->mm_list, |
be72615b CW |
4633 | &dev_priv->mm.deferred_free_list); |
4634 | return; | |
4635 | } | |
673a394b | 4636 | |
39a01d1f | 4637 | if (obj->map_list.map) |
7e616158 | 4638 | i915_gem_free_mmap_offset(obj); |
de151cf6 | 4639 | |
c397b908 | 4640 | drm_gem_object_release(obj); |
73aa808f | 4641 | i915_gem_info_remove_obj(dev_priv, obj->size); |
c397b908 | 4642 | |
9a298b2a | 4643 | kfree(obj_priv->page_cpu_valid); |
280b713b | 4644 | kfree(obj_priv->bit_17); |
c397b908 | 4645 | kfree(obj_priv); |
673a394b EA |
4646 | } |
4647 | ||
be72615b CW |
4648 | void i915_gem_free_object(struct drm_gem_object *obj) |
4649 | { | |
4650 | struct drm_device *dev = obj->dev; | |
4651 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); | |
4652 | ||
4653 | trace_i915_gem_object_destroy(obj); | |
4654 | ||
4655 | while (obj_priv->pin_count > 0) | |
4656 | i915_gem_object_unpin(obj); | |
4657 | ||
4658 | if (obj_priv->phys_obj) | |
4659 | i915_gem_detach_phys_object(dev, obj); | |
4660 | ||
4661 | i915_gem_free_object_tail(obj); | |
4662 | } | |
4663 | ||
29105ccc CW |
4664 | int |
4665 | i915_gem_idle(struct drm_device *dev) | |
4666 | { | |
4667 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4668 | int ret; | |
28dfe52a | 4669 | |
29105ccc | 4670 | mutex_lock(&dev->struct_mutex); |
1c5d22f7 | 4671 | |
87acb0a5 | 4672 | if (dev_priv->mm.suspended) { |
29105ccc CW |
4673 | mutex_unlock(&dev->struct_mutex); |
4674 | return 0; | |
28dfe52a EA |
4675 | } |
4676 | ||
29105ccc | 4677 | ret = i915_gpu_idle(dev); |
6dbe2772 KP |
4678 | if (ret) { |
4679 | mutex_unlock(&dev->struct_mutex); | |
673a394b | 4680 | return ret; |
6dbe2772 | 4681 | } |
673a394b | 4682 | |
29105ccc CW |
4683 | /* Under UMS, be paranoid and evict. */ |
4684 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) { | |
5eac3ab4 | 4685 | ret = i915_gem_evict_inactive(dev, false); |
29105ccc CW |
4686 | if (ret) { |
4687 | mutex_unlock(&dev->struct_mutex); | |
4688 | return ret; | |
4689 | } | |
4690 | } | |
4691 | ||
4692 | /* Hack! Don't let anybody do execbuf while we don't control the chip. | |
4693 | * We need to replace this with a semaphore, or something. | |
4694 | * And not confound mm.suspended! | |
4695 | */ | |
4696 | dev_priv->mm.suspended = 1; | |
bc0c7f14 | 4697 | del_timer_sync(&dev_priv->hangcheck_timer); |
29105ccc CW |
4698 | |
4699 | i915_kernel_lost_context(dev); | |
6dbe2772 | 4700 | i915_gem_cleanup_ringbuffer(dev); |
29105ccc | 4701 | |
6dbe2772 KP |
4702 | mutex_unlock(&dev->struct_mutex); |
4703 | ||
29105ccc CW |
4704 | /* Cancel the retire work handler, which should be idle now. */ |
4705 | cancel_delayed_work_sync(&dev_priv->mm.retire_work); | |
4706 | ||
673a394b EA |
4707 | return 0; |
4708 | } | |
4709 | ||
e552eb70 JB |
4710 | /* |
4711 | * 965+ support PIPE_CONTROL commands, which provide finer grained control | |
4712 | * over cache flushing. | |
4713 | */ | |
8187a2b7 | 4714 | static int |
e552eb70 JB |
4715 | i915_gem_init_pipe_control(struct drm_device *dev) |
4716 | { | |
4717 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4718 | struct drm_gem_object *obj; | |
4719 | struct drm_i915_gem_object *obj_priv; | |
4720 | int ret; | |
4721 | ||
34dc4d44 | 4722 | obj = i915_gem_alloc_object(dev, 4096); |
e552eb70 JB |
4723 | if (obj == NULL) { |
4724 | DRM_ERROR("Failed to allocate seqno page\n"); | |
4725 | ret = -ENOMEM; | |
4726 | goto err; | |
4727 | } | |
4728 | obj_priv = to_intel_bo(obj); | |
4729 | obj_priv->agp_type = AGP_USER_CACHED_MEMORY; | |
4730 | ||
75e9e915 | 4731 | ret = i915_gem_object_pin(obj, 4096, true); |
e552eb70 JB |
4732 | if (ret) |
4733 | goto err_unref; | |
4734 | ||
4735 | dev_priv->seqno_gfx_addr = obj_priv->gtt_offset; | |
4736 | dev_priv->seqno_page = kmap(obj_priv->pages[0]); | |
4737 | if (dev_priv->seqno_page == NULL) | |
4738 | goto err_unpin; | |
4739 | ||
4740 | dev_priv->seqno_obj = obj; | |
4741 | memset(dev_priv->seqno_page, 0, PAGE_SIZE); | |
4742 | ||
4743 | return 0; | |
4744 | ||
4745 | err_unpin: | |
4746 | i915_gem_object_unpin(obj); | |
4747 | err_unref: | |
4748 | drm_gem_object_unreference(obj); | |
4749 | err: | |
4750 | return ret; | |
4751 | } | |
4752 | ||
8187a2b7 ZN |
4753 | |
4754 | static void | |
e552eb70 JB |
4755 | i915_gem_cleanup_pipe_control(struct drm_device *dev) |
4756 | { | |
4757 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4758 | struct drm_gem_object *obj; | |
4759 | struct drm_i915_gem_object *obj_priv; | |
4760 | ||
4761 | obj = dev_priv->seqno_obj; | |
4762 | obj_priv = to_intel_bo(obj); | |
4763 | kunmap(obj_priv->pages[0]); | |
4764 | i915_gem_object_unpin(obj); | |
4765 | drm_gem_object_unreference(obj); | |
4766 | dev_priv->seqno_obj = NULL; | |
4767 | ||
4768 | dev_priv->seqno_page = NULL; | |
673a394b EA |
4769 | } |
4770 | ||
8187a2b7 ZN |
4771 | int |
4772 | i915_gem_init_ringbuffer(struct drm_device *dev) | |
4773 | { | |
4774 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4775 | int ret; | |
68f95ba9 | 4776 | |
8187a2b7 ZN |
4777 | if (HAS_PIPE_CONTROL(dev)) { |
4778 | ret = i915_gem_init_pipe_control(dev); | |
4779 | if (ret) | |
4780 | return ret; | |
4781 | } | |
68f95ba9 | 4782 | |
5c1143bb | 4783 | ret = intel_init_render_ring_buffer(dev); |
68f95ba9 CW |
4784 | if (ret) |
4785 | goto cleanup_pipe_control; | |
4786 | ||
4787 | if (HAS_BSD(dev)) { | |
5c1143bb | 4788 | ret = intel_init_bsd_ring_buffer(dev); |
68f95ba9 CW |
4789 | if (ret) |
4790 | goto cleanup_render_ring; | |
d1b851fc | 4791 | } |
68f95ba9 | 4792 | |
549f7365 CW |
4793 | if (HAS_BLT(dev)) { |
4794 | ret = intel_init_blt_ring_buffer(dev); | |
4795 | if (ret) | |
4796 | goto cleanup_bsd_ring; | |
4797 | } | |
4798 | ||
6f392d54 CW |
4799 | dev_priv->next_seqno = 1; |
4800 | ||
68f95ba9 CW |
4801 | return 0; |
4802 | ||
549f7365 | 4803 | cleanup_bsd_ring: |
78501eac | 4804 | intel_cleanup_ring_buffer(&dev_priv->bsd_ring); |
68f95ba9 | 4805 | cleanup_render_ring: |
78501eac | 4806 | intel_cleanup_ring_buffer(&dev_priv->render_ring); |
68f95ba9 CW |
4807 | cleanup_pipe_control: |
4808 | if (HAS_PIPE_CONTROL(dev)) | |
4809 | i915_gem_cleanup_pipe_control(dev); | |
8187a2b7 ZN |
4810 | return ret; |
4811 | } | |
4812 | ||
4813 | void | |
4814 | i915_gem_cleanup_ringbuffer(struct drm_device *dev) | |
4815 | { | |
4816 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4817 | ||
78501eac CW |
4818 | intel_cleanup_ring_buffer(&dev_priv->render_ring); |
4819 | intel_cleanup_ring_buffer(&dev_priv->bsd_ring); | |
4820 | intel_cleanup_ring_buffer(&dev_priv->blt_ring); | |
8187a2b7 ZN |
4821 | if (HAS_PIPE_CONTROL(dev)) |
4822 | i915_gem_cleanup_pipe_control(dev); | |
4823 | } | |
4824 | ||
673a394b EA |
4825 | int |
4826 | i915_gem_entervt_ioctl(struct drm_device *dev, void *data, | |
4827 | struct drm_file *file_priv) | |
4828 | { | |
4829 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4830 | int ret; | |
4831 | ||
79e53945 JB |
4832 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
4833 | return 0; | |
4834 | ||
ba1234d1 | 4835 | if (atomic_read(&dev_priv->mm.wedged)) { |
673a394b | 4836 | DRM_ERROR("Reenabling wedged hardware, good luck\n"); |
ba1234d1 | 4837 | atomic_set(&dev_priv->mm.wedged, 0); |
673a394b EA |
4838 | } |
4839 | ||
673a394b | 4840 | mutex_lock(&dev->struct_mutex); |
9bb2d6f9 EA |
4841 | dev_priv->mm.suspended = 0; |
4842 | ||
4843 | ret = i915_gem_init_ringbuffer(dev); | |
d816f6ac WF |
4844 | if (ret != 0) { |
4845 | mutex_unlock(&dev->struct_mutex); | |
9bb2d6f9 | 4846 | return ret; |
d816f6ac | 4847 | } |
9bb2d6f9 | 4848 | |
69dc4987 | 4849 | BUG_ON(!list_empty(&dev_priv->mm.active_list)); |
852835f3 | 4850 | BUG_ON(!list_empty(&dev_priv->render_ring.active_list)); |
87acb0a5 | 4851 | BUG_ON(!list_empty(&dev_priv->bsd_ring.active_list)); |
549f7365 | 4852 | BUG_ON(!list_empty(&dev_priv->blt_ring.active_list)); |
673a394b EA |
4853 | BUG_ON(!list_empty(&dev_priv->mm.flushing_list)); |
4854 | BUG_ON(!list_empty(&dev_priv->mm.inactive_list)); | |
852835f3 | 4855 | BUG_ON(!list_empty(&dev_priv->render_ring.request_list)); |
87acb0a5 | 4856 | BUG_ON(!list_empty(&dev_priv->bsd_ring.request_list)); |
549f7365 | 4857 | BUG_ON(!list_empty(&dev_priv->blt_ring.request_list)); |
673a394b | 4858 | mutex_unlock(&dev->struct_mutex); |
dbb19d30 | 4859 | |
5f35308b CW |
4860 | ret = drm_irq_install(dev); |
4861 | if (ret) | |
4862 | goto cleanup_ringbuffer; | |
dbb19d30 | 4863 | |
673a394b | 4864 | return 0; |
5f35308b CW |
4865 | |
4866 | cleanup_ringbuffer: | |
4867 | mutex_lock(&dev->struct_mutex); | |
4868 | i915_gem_cleanup_ringbuffer(dev); | |
4869 | dev_priv->mm.suspended = 1; | |
4870 | mutex_unlock(&dev->struct_mutex); | |
4871 | ||
4872 | return ret; | |
673a394b EA |
4873 | } |
4874 | ||
4875 | int | |
4876 | i915_gem_leavevt_ioctl(struct drm_device *dev, void *data, | |
4877 | struct drm_file *file_priv) | |
4878 | { | |
79e53945 JB |
4879 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
4880 | return 0; | |
4881 | ||
dbb19d30 | 4882 | drm_irq_uninstall(dev); |
e6890f6f | 4883 | return i915_gem_idle(dev); |
673a394b EA |
4884 | } |
4885 | ||
4886 | void | |
4887 | i915_gem_lastclose(struct drm_device *dev) | |
4888 | { | |
4889 | int ret; | |
673a394b | 4890 | |
e806b495 EA |
4891 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
4892 | return; | |
4893 | ||
6dbe2772 KP |
4894 | ret = i915_gem_idle(dev); |
4895 | if (ret) | |
4896 | DRM_ERROR("failed to idle hardware: %d\n", ret); | |
673a394b EA |
4897 | } |
4898 | ||
64193406 CW |
4899 | static void |
4900 | init_ring_lists(struct intel_ring_buffer *ring) | |
4901 | { | |
4902 | INIT_LIST_HEAD(&ring->active_list); | |
4903 | INIT_LIST_HEAD(&ring->request_list); | |
4904 | INIT_LIST_HEAD(&ring->gpu_write_list); | |
4905 | } | |
4906 | ||
673a394b EA |
4907 | void |
4908 | i915_gem_load(struct drm_device *dev) | |
4909 | { | |
b5aa8a0f | 4910 | int i; |
673a394b EA |
4911 | drm_i915_private_t *dev_priv = dev->dev_private; |
4912 | ||
69dc4987 | 4913 | INIT_LIST_HEAD(&dev_priv->mm.active_list); |
673a394b EA |
4914 | INIT_LIST_HEAD(&dev_priv->mm.flushing_list); |
4915 | INIT_LIST_HEAD(&dev_priv->mm.inactive_list); | |
f13d3f73 | 4916 | INIT_LIST_HEAD(&dev_priv->mm.pinned_list); |
a09ba7fa | 4917 | INIT_LIST_HEAD(&dev_priv->mm.fence_list); |
be72615b | 4918 | INIT_LIST_HEAD(&dev_priv->mm.deferred_free_list); |
64193406 CW |
4919 | init_ring_lists(&dev_priv->render_ring); |
4920 | init_ring_lists(&dev_priv->bsd_ring); | |
4921 | init_ring_lists(&dev_priv->blt_ring); | |
007cc8ac DV |
4922 | for (i = 0; i < 16; i++) |
4923 | INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list); | |
673a394b EA |
4924 | INIT_DELAYED_WORK(&dev_priv->mm.retire_work, |
4925 | i915_gem_retire_work_handler); | |
30dbf0c0 | 4926 | init_completion(&dev_priv->error_completion); |
31169714 | 4927 | |
94400120 DA |
4928 | /* On GEN3 we really need to make sure the ARB C3 LP bit is set */ |
4929 | if (IS_GEN3(dev)) { | |
4930 | u32 tmp = I915_READ(MI_ARB_STATE); | |
4931 | if (!(tmp & MI_ARB_C3_LP_WRITE_ENABLE)) { | |
4932 | /* arb state is a masked write, so set bit + bit in mask */ | |
4933 | tmp = MI_ARB_C3_LP_WRITE_ENABLE | (MI_ARB_C3_LP_WRITE_ENABLE << MI_ARB_MASK_SHIFT); | |
4934 | I915_WRITE(MI_ARB_STATE, tmp); | |
4935 | } | |
4936 | } | |
4937 | ||
de151cf6 | 4938 | /* Old X drivers will take 0-2 for front, back, depth buffers */ |
b397c836 EA |
4939 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) |
4940 | dev_priv->fence_reg_start = 3; | |
de151cf6 | 4941 | |
a6c45cf0 | 4942 | if (INTEL_INFO(dev)->gen >= 4 || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) |
de151cf6 JB |
4943 | dev_priv->num_fence_regs = 16; |
4944 | else | |
4945 | dev_priv->num_fence_regs = 8; | |
4946 | ||
b5aa8a0f | 4947 | /* Initialize fence registers to zero */ |
a6c45cf0 CW |
4948 | switch (INTEL_INFO(dev)->gen) { |
4949 | case 6: | |
4950 | for (i = 0; i < 16; i++) | |
4951 | I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + (i * 8), 0); | |
4952 | break; | |
4953 | case 5: | |
4954 | case 4: | |
b5aa8a0f GH |
4955 | for (i = 0; i < 16; i++) |
4956 | I915_WRITE64(FENCE_REG_965_0 + (i * 8), 0); | |
a6c45cf0 CW |
4957 | break; |
4958 | case 3: | |
b5aa8a0f GH |
4959 | if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) |
4960 | for (i = 0; i < 8; i++) | |
4961 | I915_WRITE(FENCE_REG_945_8 + (i * 4), 0); | |
a6c45cf0 CW |
4962 | case 2: |
4963 | for (i = 0; i < 8; i++) | |
4964 | I915_WRITE(FENCE_REG_830_0 + (i * 4), 0); | |
4965 | break; | |
b5aa8a0f | 4966 | } |
673a394b | 4967 | i915_gem_detect_bit_6_swizzle(dev); |
6b95a207 | 4968 | init_waitqueue_head(&dev_priv->pending_flip_queue); |
17250b71 CW |
4969 | |
4970 | dev_priv->mm.inactive_shrinker.shrink = i915_gem_inactive_shrink; | |
4971 | dev_priv->mm.inactive_shrinker.seeks = DEFAULT_SEEKS; | |
4972 | register_shrinker(&dev_priv->mm.inactive_shrinker); | |
673a394b | 4973 | } |
71acb5eb DA |
4974 | |
4975 | /* | |
4976 | * Create a physically contiguous memory object for this object | |
4977 | * e.g. for cursor + overlay regs | |
4978 | */ | |
995b6762 CW |
4979 | static int i915_gem_init_phys_object(struct drm_device *dev, |
4980 | int id, int size, int align) | |
71acb5eb DA |
4981 | { |
4982 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4983 | struct drm_i915_gem_phys_object *phys_obj; | |
4984 | int ret; | |
4985 | ||
4986 | if (dev_priv->mm.phys_objs[id - 1] || !size) | |
4987 | return 0; | |
4988 | ||
9a298b2a | 4989 | phys_obj = kzalloc(sizeof(struct drm_i915_gem_phys_object), GFP_KERNEL); |
71acb5eb DA |
4990 | if (!phys_obj) |
4991 | return -ENOMEM; | |
4992 | ||
4993 | phys_obj->id = id; | |
4994 | ||
6eeefaf3 | 4995 | phys_obj->handle = drm_pci_alloc(dev, size, align); |
71acb5eb DA |
4996 | if (!phys_obj->handle) { |
4997 | ret = -ENOMEM; | |
4998 | goto kfree_obj; | |
4999 | } | |
5000 | #ifdef CONFIG_X86 | |
5001 | set_memory_wc((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE); | |
5002 | #endif | |
5003 | ||
5004 | dev_priv->mm.phys_objs[id - 1] = phys_obj; | |
5005 | ||
5006 | return 0; | |
5007 | kfree_obj: | |
9a298b2a | 5008 | kfree(phys_obj); |
71acb5eb DA |
5009 | return ret; |
5010 | } | |
5011 | ||
995b6762 | 5012 | static void i915_gem_free_phys_object(struct drm_device *dev, int id) |
71acb5eb DA |
5013 | { |
5014 | drm_i915_private_t *dev_priv = dev->dev_private; | |
5015 | struct drm_i915_gem_phys_object *phys_obj; | |
5016 | ||
5017 | if (!dev_priv->mm.phys_objs[id - 1]) | |
5018 | return; | |
5019 | ||
5020 | phys_obj = dev_priv->mm.phys_objs[id - 1]; | |
5021 | if (phys_obj->cur_obj) { | |
5022 | i915_gem_detach_phys_object(dev, phys_obj->cur_obj); | |
5023 | } | |
5024 | ||
5025 | #ifdef CONFIG_X86 | |
5026 | set_memory_wb((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE); | |
5027 | #endif | |
5028 | drm_pci_free(dev, phys_obj->handle); | |
5029 | kfree(phys_obj); | |
5030 | dev_priv->mm.phys_objs[id - 1] = NULL; | |
5031 | } | |
5032 | ||
5033 | void i915_gem_free_all_phys_object(struct drm_device *dev) | |
5034 | { | |
5035 | int i; | |
5036 | ||
260883c8 | 5037 | for (i = I915_GEM_PHYS_CURSOR_0; i <= I915_MAX_PHYS_OBJECT; i++) |
71acb5eb DA |
5038 | i915_gem_free_phys_object(dev, i); |
5039 | } | |
5040 | ||
5041 | void i915_gem_detach_phys_object(struct drm_device *dev, | |
5042 | struct drm_gem_object *obj) | |
5043 | { | |
e5281ccd CW |
5044 | struct address_space *mapping = obj->filp->f_path.dentry->d_inode->i_mapping; |
5045 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); | |
5046 | char *vaddr; | |
71acb5eb | 5047 | int i; |
71acb5eb DA |
5048 | int page_count; |
5049 | ||
71acb5eb DA |
5050 | if (!obj_priv->phys_obj) |
5051 | return; | |
e5281ccd | 5052 | vaddr = obj_priv->phys_obj->handle->vaddr; |
71acb5eb DA |
5053 | |
5054 | page_count = obj->size / PAGE_SIZE; | |
5055 | ||
5056 | for (i = 0; i < page_count; i++) { | |
e5281ccd CW |
5057 | struct page *page = read_cache_page_gfp(mapping, i, |
5058 | GFP_HIGHUSER | __GFP_RECLAIMABLE); | |
5059 | if (!IS_ERR(page)) { | |
5060 | char *dst = kmap_atomic(page); | |
5061 | memcpy(dst, vaddr + i*PAGE_SIZE, PAGE_SIZE); | |
5062 | kunmap_atomic(dst); | |
5063 | ||
5064 | drm_clflush_pages(&page, 1); | |
5065 | ||
5066 | set_page_dirty(page); | |
5067 | mark_page_accessed(page); | |
5068 | page_cache_release(page); | |
5069 | } | |
71acb5eb | 5070 | } |
40ce6575 | 5071 | intel_gtt_chipset_flush(); |
d78b47b9 | 5072 | |
71acb5eb DA |
5073 | obj_priv->phys_obj->cur_obj = NULL; |
5074 | obj_priv->phys_obj = NULL; | |
5075 | } | |
5076 | ||
5077 | int | |
5078 | i915_gem_attach_phys_object(struct drm_device *dev, | |
6eeefaf3 CW |
5079 | struct drm_gem_object *obj, |
5080 | int id, | |
5081 | int align) | |
71acb5eb | 5082 | { |
e5281ccd | 5083 | struct address_space *mapping = obj->filp->f_path.dentry->d_inode->i_mapping; |
71acb5eb DA |
5084 | drm_i915_private_t *dev_priv = dev->dev_private; |
5085 | struct drm_i915_gem_object *obj_priv; | |
5086 | int ret = 0; | |
5087 | int page_count; | |
5088 | int i; | |
5089 | ||
5090 | if (id > I915_MAX_PHYS_OBJECT) | |
5091 | return -EINVAL; | |
5092 | ||
23010e43 | 5093 | obj_priv = to_intel_bo(obj); |
71acb5eb DA |
5094 | |
5095 | if (obj_priv->phys_obj) { | |
5096 | if (obj_priv->phys_obj->id == id) | |
5097 | return 0; | |
5098 | i915_gem_detach_phys_object(dev, obj); | |
5099 | } | |
5100 | ||
71acb5eb DA |
5101 | /* create a new object */ |
5102 | if (!dev_priv->mm.phys_objs[id - 1]) { | |
5103 | ret = i915_gem_init_phys_object(dev, id, | |
6eeefaf3 | 5104 | obj->size, align); |
71acb5eb | 5105 | if (ret) { |
aeb565df | 5106 | DRM_ERROR("failed to init phys object %d size: %zu\n", id, obj->size); |
e5281ccd | 5107 | return ret; |
71acb5eb DA |
5108 | } |
5109 | } | |
5110 | ||
5111 | /* bind to the object */ | |
5112 | obj_priv->phys_obj = dev_priv->mm.phys_objs[id - 1]; | |
5113 | obj_priv->phys_obj->cur_obj = obj; | |
5114 | ||
71acb5eb DA |
5115 | page_count = obj->size / PAGE_SIZE; |
5116 | ||
5117 | for (i = 0; i < page_count; i++) { | |
e5281ccd CW |
5118 | struct page *page; |
5119 | char *dst, *src; | |
5120 | ||
5121 | page = read_cache_page_gfp(mapping, i, | |
5122 | GFP_HIGHUSER | __GFP_RECLAIMABLE); | |
5123 | if (IS_ERR(page)) | |
5124 | return PTR_ERR(page); | |
71acb5eb | 5125 | |
ff75b9bc | 5126 | src = kmap_atomic(page); |
e5281ccd | 5127 | dst = obj_priv->phys_obj->handle->vaddr + (i * PAGE_SIZE); |
71acb5eb | 5128 | memcpy(dst, src, PAGE_SIZE); |
3e4d3af5 | 5129 | kunmap_atomic(src); |
71acb5eb | 5130 | |
e5281ccd CW |
5131 | mark_page_accessed(page); |
5132 | page_cache_release(page); | |
5133 | } | |
d78b47b9 | 5134 | |
71acb5eb | 5135 | return 0; |
71acb5eb DA |
5136 | } |
5137 | ||
5138 | static int | |
5139 | i915_gem_phys_pwrite(struct drm_device *dev, struct drm_gem_object *obj, | |
5140 | struct drm_i915_gem_pwrite *args, | |
5141 | struct drm_file *file_priv) | |
5142 | { | |
23010e43 | 5143 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
b47b30cc CW |
5144 | void *vaddr = obj_priv->phys_obj->handle->vaddr + args->offset; |
5145 | char __user *user_data = (char __user *) (uintptr_t) args->data_ptr; | |
71acb5eb | 5146 | |
b47b30cc | 5147 | DRM_DEBUG_DRIVER("vaddr %p, %lld\n", vaddr, args->size); |
71acb5eb | 5148 | |
b47b30cc CW |
5149 | if (__copy_from_user_inatomic_nocache(vaddr, user_data, args->size)) { |
5150 | unsigned long unwritten; | |
5151 | ||
5152 | /* The physical object once assigned is fixed for the lifetime | |
5153 | * of the obj, so we can safely drop the lock and continue | |
5154 | * to access vaddr. | |
5155 | */ | |
5156 | mutex_unlock(&dev->struct_mutex); | |
5157 | unwritten = copy_from_user(vaddr, user_data, args->size); | |
5158 | mutex_lock(&dev->struct_mutex); | |
5159 | if (unwritten) | |
5160 | return -EFAULT; | |
5161 | } | |
71acb5eb | 5162 | |
40ce6575 | 5163 | intel_gtt_chipset_flush(); |
71acb5eb DA |
5164 | return 0; |
5165 | } | |
b962442e | 5166 | |
f787a5f5 | 5167 | void i915_gem_release(struct drm_device *dev, struct drm_file *file) |
b962442e | 5168 | { |
f787a5f5 | 5169 | struct drm_i915_file_private *file_priv = file->driver_priv; |
b962442e EA |
5170 | |
5171 | /* Clean up our request list when the client is going away, so that | |
5172 | * later retire_requests won't dereference our soon-to-be-gone | |
5173 | * file_priv. | |
5174 | */ | |
1c25595f | 5175 | spin_lock(&file_priv->mm.lock); |
f787a5f5 CW |
5176 | while (!list_empty(&file_priv->mm.request_list)) { |
5177 | struct drm_i915_gem_request *request; | |
5178 | ||
5179 | request = list_first_entry(&file_priv->mm.request_list, | |
5180 | struct drm_i915_gem_request, | |
5181 | client_list); | |
5182 | list_del(&request->client_list); | |
5183 | request->file_priv = NULL; | |
5184 | } | |
1c25595f | 5185 | spin_unlock(&file_priv->mm.lock); |
b962442e | 5186 | } |
31169714 | 5187 | |
1637ef41 CW |
5188 | static int |
5189 | i915_gpu_is_active(struct drm_device *dev) | |
5190 | { | |
5191 | drm_i915_private_t *dev_priv = dev->dev_private; | |
5192 | int lists_empty; | |
5193 | ||
1637ef41 | 5194 | lists_empty = list_empty(&dev_priv->mm.flushing_list) && |
17250b71 | 5195 | list_empty(&dev_priv->mm.active_list); |
1637ef41 CW |
5196 | |
5197 | return !lists_empty; | |
5198 | } | |
5199 | ||
31169714 | 5200 | static int |
17250b71 CW |
5201 | i915_gem_inactive_shrink(struct shrinker *shrinker, |
5202 | int nr_to_scan, | |
5203 | gfp_t gfp_mask) | |
31169714 | 5204 | { |
17250b71 CW |
5205 | struct drm_i915_private *dev_priv = |
5206 | container_of(shrinker, | |
5207 | struct drm_i915_private, | |
5208 | mm.inactive_shrinker); | |
5209 | struct drm_device *dev = dev_priv->dev; | |
5210 | struct drm_i915_gem_object *obj, *next; | |
5211 | int cnt; | |
5212 | ||
5213 | if (!mutex_trylock(&dev->struct_mutex)) | |
bbe2e11a | 5214 | return 0; |
31169714 CW |
5215 | |
5216 | /* "fast-path" to count number of available objects */ | |
5217 | if (nr_to_scan == 0) { | |
17250b71 CW |
5218 | cnt = 0; |
5219 | list_for_each_entry(obj, | |
5220 | &dev_priv->mm.inactive_list, | |
5221 | mm_list) | |
5222 | cnt++; | |
5223 | mutex_unlock(&dev->struct_mutex); | |
5224 | return cnt / 100 * sysctl_vfs_cache_pressure; | |
31169714 CW |
5225 | } |
5226 | ||
1637ef41 | 5227 | rescan: |
31169714 | 5228 | /* first scan for clean buffers */ |
17250b71 | 5229 | i915_gem_retire_requests(dev); |
31169714 | 5230 | |
17250b71 CW |
5231 | list_for_each_entry_safe(obj, next, |
5232 | &dev_priv->mm.inactive_list, | |
5233 | mm_list) { | |
5234 | if (i915_gem_object_is_purgeable(obj)) { | |
5235 | i915_gem_object_unbind(&obj->base); | |
5236 | if (--nr_to_scan == 0) | |
5237 | break; | |
31169714 | 5238 | } |
31169714 CW |
5239 | } |
5240 | ||
5241 | /* second pass, evict/count anything still on the inactive list */ | |
17250b71 CW |
5242 | cnt = 0; |
5243 | list_for_each_entry_safe(obj, next, | |
5244 | &dev_priv->mm.inactive_list, | |
5245 | mm_list) { | |
5246 | if (nr_to_scan) { | |
5247 | i915_gem_object_unbind(&obj->base); | |
5248 | nr_to_scan--; | |
5249 | } else | |
5250 | cnt++; | |
5251 | } | |
5252 | ||
5253 | if (nr_to_scan && i915_gpu_is_active(dev)) { | |
1637ef41 CW |
5254 | /* |
5255 | * We are desperate for pages, so as a last resort, wait | |
5256 | * for the GPU to finish and discard whatever we can. | |
5257 | * This has a dramatic impact to reduce the number of | |
5258 | * OOM-killer events whilst running the GPU aggressively. | |
5259 | */ | |
17250b71 | 5260 | if (i915_gpu_idle(dev) == 0) |
1637ef41 CW |
5261 | goto rescan; |
5262 | } | |
17250b71 CW |
5263 | mutex_unlock(&dev->struct_mutex); |
5264 | return cnt / 100 * sysctl_vfs_cache_pressure; | |
31169714 | 5265 | } |