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Commit | Line | Data |
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673a394b | 1 | /* |
be6a0376 | 2 | * Copyright © 2008-2015 Intel Corporation |
673a394b EA |
3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | * | |
26 | */ | |
27 | ||
760285e7 | 28 | #include <drm/drmP.h> |
0de23977 | 29 | #include <drm/drm_vma_manager.h> |
760285e7 | 30 | #include <drm/i915_drm.h> |
673a394b | 31 | #include "i915_drv.h" |
57822dc6 | 32 | #include "i915_gem_clflush.h" |
eb82289a | 33 | #include "i915_vgpu.h" |
1c5d22f7 | 34 | #include "i915_trace.h" |
652c393a | 35 | #include "intel_drv.h" |
5d723d7a | 36 | #include "intel_frontbuffer.h" |
0ccdacf6 | 37 | #include "intel_mocs.h" |
465c403c | 38 | #include "i915_gemfs.h" |
6b5e90f5 | 39 | #include <linux/dma-fence-array.h> |
fe3288b5 | 40 | #include <linux/kthread.h> |
c13d87ea | 41 | #include <linux/reservation.h> |
5949eac4 | 42 | #include <linux/shmem_fs.h> |
5a0e3ad6 | 43 | #include <linux/slab.h> |
20e4933c | 44 | #include <linux/stop_machine.h> |
673a394b | 45 | #include <linux/swap.h> |
79e53945 | 46 | #include <linux/pci.h> |
1286ff73 | 47 | #include <linux/dma-buf.h> |
673a394b | 48 | |
fbbd37b3 | 49 | static void i915_gem_flush_free_objects(struct drm_i915_private *i915); |
61050808 | 50 | |
2c22569b CW |
51 | static bool cpu_write_needs_clflush(struct drm_i915_gem_object *obj) |
52 | { | |
e27ab73d | 53 | if (obj->cache_dirty) |
b50a5371 AS |
54 | return false; |
55 | ||
b8f55be6 | 56 | if (!(obj->cache_coherent & I915_BO_CACHE_COHERENT_FOR_WRITE)) |
2c22569b CW |
57 | return true; |
58 | ||
59 | return obj->pin_display; | |
60 | } | |
61 | ||
4f1959ee | 62 | static int |
bb6dc8d9 | 63 | insert_mappable_node(struct i915_ggtt *ggtt, |
4f1959ee AS |
64 | struct drm_mm_node *node, u32 size) |
65 | { | |
66 | memset(node, 0, sizeof(*node)); | |
4e64e553 CW |
67 | return drm_mm_insert_node_in_range(&ggtt->base.mm, node, |
68 | size, 0, I915_COLOR_UNEVICTABLE, | |
69 | 0, ggtt->mappable_end, | |
70 | DRM_MM_INSERT_LOW); | |
4f1959ee AS |
71 | } |
72 | ||
73 | static void | |
74 | remove_mappable_node(struct drm_mm_node *node) | |
75 | { | |
76 | drm_mm_remove_node(node); | |
77 | } | |
78 | ||
73aa808f CW |
79 | /* some bookkeeping */ |
80 | static void i915_gem_info_add_obj(struct drm_i915_private *dev_priv, | |
3ef7f228 | 81 | u64 size) |
73aa808f | 82 | { |
c20e8355 | 83 | spin_lock(&dev_priv->mm.object_stat_lock); |
73aa808f CW |
84 | dev_priv->mm.object_count++; |
85 | dev_priv->mm.object_memory += size; | |
c20e8355 | 86 | spin_unlock(&dev_priv->mm.object_stat_lock); |
73aa808f CW |
87 | } |
88 | ||
89 | static void i915_gem_info_remove_obj(struct drm_i915_private *dev_priv, | |
3ef7f228 | 90 | u64 size) |
73aa808f | 91 | { |
c20e8355 | 92 | spin_lock(&dev_priv->mm.object_stat_lock); |
73aa808f CW |
93 | dev_priv->mm.object_count--; |
94 | dev_priv->mm.object_memory -= size; | |
c20e8355 | 95 | spin_unlock(&dev_priv->mm.object_stat_lock); |
73aa808f CW |
96 | } |
97 | ||
21dd3734 | 98 | static int |
33196ded | 99 | i915_gem_wait_for_error(struct i915_gpu_error *error) |
30dbf0c0 | 100 | { |
30dbf0c0 CW |
101 | int ret; |
102 | ||
4c7d62c6 CW |
103 | might_sleep(); |
104 | ||
0a6759c6 DV |
105 | /* |
106 | * Only wait 10 seconds for the gpu reset to complete to avoid hanging | |
107 | * userspace. If it takes that long something really bad is going on and | |
108 | * we should simply try to bail out and fail as gracefully as possible. | |
109 | */ | |
1f83fee0 | 110 | ret = wait_event_interruptible_timeout(error->reset_queue, |
8c185eca | 111 | !i915_reset_backoff(error), |
b52992c0 | 112 | I915_RESET_TIMEOUT); |
0a6759c6 DV |
113 | if (ret == 0) { |
114 | DRM_ERROR("Timed out waiting for the gpu reset to complete\n"); | |
115 | return -EIO; | |
116 | } else if (ret < 0) { | |
30dbf0c0 | 117 | return ret; |
d98c52cf CW |
118 | } else { |
119 | return 0; | |
0a6759c6 | 120 | } |
30dbf0c0 CW |
121 | } |
122 | ||
54cf91dc | 123 | int i915_mutex_lock_interruptible(struct drm_device *dev) |
76c1dec1 | 124 | { |
fac5e23e | 125 | struct drm_i915_private *dev_priv = to_i915(dev); |
76c1dec1 CW |
126 | int ret; |
127 | ||
33196ded | 128 | ret = i915_gem_wait_for_error(&dev_priv->gpu_error); |
76c1dec1 CW |
129 | if (ret) |
130 | return ret; | |
131 | ||
132 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
133 | if (ret) | |
134 | return ret; | |
135 | ||
76c1dec1 CW |
136 | return 0; |
137 | } | |
30dbf0c0 | 138 | |
5a125c3c EA |
139 | int |
140 | i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 141 | struct drm_file *file) |
5a125c3c | 142 | { |
72e96d64 | 143 | struct drm_i915_private *dev_priv = to_i915(dev); |
62106b4f | 144 | struct i915_ggtt *ggtt = &dev_priv->ggtt; |
72e96d64 | 145 | struct drm_i915_gem_get_aperture *args = data; |
ca1543be | 146 | struct i915_vma *vma; |
ff8f7975 | 147 | u64 pinned; |
5a125c3c | 148 | |
ff8f7975 | 149 | pinned = ggtt->base.reserved; |
73aa808f | 150 | mutex_lock(&dev->struct_mutex); |
1c7f4bca | 151 | list_for_each_entry(vma, &ggtt->base.active_list, vm_link) |
20dfbde4 | 152 | if (i915_vma_is_pinned(vma)) |
ca1543be | 153 | pinned += vma->node.size; |
1c7f4bca | 154 | list_for_each_entry(vma, &ggtt->base.inactive_list, vm_link) |
20dfbde4 | 155 | if (i915_vma_is_pinned(vma)) |
ca1543be | 156 | pinned += vma->node.size; |
73aa808f | 157 | mutex_unlock(&dev->struct_mutex); |
5a125c3c | 158 | |
72e96d64 | 159 | args->aper_size = ggtt->base.total; |
0206e353 | 160 | args->aper_available_size = args->aper_size - pinned; |
6299f992 | 161 | |
5a125c3c EA |
162 | return 0; |
163 | } | |
164 | ||
b91b09ee | 165 | static int i915_gem_object_get_pages_phys(struct drm_i915_gem_object *obj) |
00731155 | 166 | { |
93c76a3d | 167 | struct address_space *mapping = obj->base.filp->f_mapping; |
dbb4351b | 168 | drm_dma_handle_t *phys; |
6a2c4232 CW |
169 | struct sg_table *st; |
170 | struct scatterlist *sg; | |
dbb4351b | 171 | char *vaddr; |
6a2c4232 | 172 | int i; |
b91b09ee | 173 | int err; |
00731155 | 174 | |
6a2c4232 | 175 | if (WARN_ON(i915_gem_object_needs_bit17_swizzle(obj))) |
b91b09ee | 176 | return -EINVAL; |
6a2c4232 | 177 | |
dbb4351b CW |
178 | /* Always aligning to the object size, allows a single allocation |
179 | * to handle all possible callers, and given typical object sizes, | |
180 | * the alignment of the buddy allocation will naturally match. | |
181 | */ | |
182 | phys = drm_pci_alloc(obj->base.dev, | |
750fae23 | 183 | roundup_pow_of_two(obj->base.size), |
dbb4351b CW |
184 | roundup_pow_of_two(obj->base.size)); |
185 | if (!phys) | |
b91b09ee | 186 | return -ENOMEM; |
dbb4351b CW |
187 | |
188 | vaddr = phys->vaddr; | |
6a2c4232 CW |
189 | for (i = 0; i < obj->base.size / PAGE_SIZE; i++) { |
190 | struct page *page; | |
191 | char *src; | |
192 | ||
193 | page = shmem_read_mapping_page(mapping, i); | |
dbb4351b | 194 | if (IS_ERR(page)) { |
b91b09ee | 195 | err = PTR_ERR(page); |
dbb4351b CW |
196 | goto err_phys; |
197 | } | |
6a2c4232 CW |
198 | |
199 | src = kmap_atomic(page); | |
200 | memcpy(vaddr, src, PAGE_SIZE); | |
201 | drm_clflush_virt_range(vaddr, PAGE_SIZE); | |
202 | kunmap_atomic(src); | |
203 | ||
09cbfeaf | 204 | put_page(page); |
6a2c4232 CW |
205 | vaddr += PAGE_SIZE; |
206 | } | |
207 | ||
c033666a | 208 | i915_gem_chipset_flush(to_i915(obj->base.dev)); |
6a2c4232 CW |
209 | |
210 | st = kmalloc(sizeof(*st), GFP_KERNEL); | |
dbb4351b | 211 | if (!st) { |
b91b09ee | 212 | err = -ENOMEM; |
dbb4351b CW |
213 | goto err_phys; |
214 | } | |
6a2c4232 CW |
215 | |
216 | if (sg_alloc_table(st, 1, GFP_KERNEL)) { | |
217 | kfree(st); | |
b91b09ee | 218 | err = -ENOMEM; |
dbb4351b | 219 | goto err_phys; |
6a2c4232 CW |
220 | } |
221 | ||
222 | sg = st->sgl; | |
223 | sg->offset = 0; | |
224 | sg->length = obj->base.size; | |
00731155 | 225 | |
dbb4351b | 226 | sg_dma_address(sg) = phys->busaddr; |
6a2c4232 CW |
227 | sg_dma_len(sg) = obj->base.size; |
228 | ||
dbb4351b | 229 | obj->phys_handle = phys; |
b91b09ee | 230 | |
a5c08166 | 231 | __i915_gem_object_set_pages(obj, st, sg->length); |
b91b09ee MA |
232 | |
233 | return 0; | |
dbb4351b CW |
234 | |
235 | err_phys: | |
236 | drm_pci_free(obj->base.dev, phys); | |
b91b09ee MA |
237 | |
238 | return err; | |
6a2c4232 CW |
239 | } |
240 | ||
e27ab73d CW |
241 | static void __start_cpu_write(struct drm_i915_gem_object *obj) |
242 | { | |
243 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; | |
244 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; | |
245 | if (cpu_write_needs_clflush(obj)) | |
246 | obj->cache_dirty = true; | |
247 | } | |
248 | ||
6a2c4232 | 249 | static void |
2b3c8317 | 250 | __i915_gem_object_release_shmem(struct drm_i915_gem_object *obj, |
e5facdf9 CW |
251 | struct sg_table *pages, |
252 | bool needs_clflush) | |
6a2c4232 | 253 | { |
a4f5ea64 | 254 | GEM_BUG_ON(obj->mm.madv == __I915_MADV_PURGED); |
00731155 | 255 | |
a4f5ea64 CW |
256 | if (obj->mm.madv == I915_MADV_DONTNEED) |
257 | obj->mm.dirty = false; | |
6a2c4232 | 258 | |
e5facdf9 CW |
259 | if (needs_clflush && |
260 | (obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0 && | |
b8f55be6 | 261 | !(obj->cache_coherent & I915_BO_CACHE_COHERENT_FOR_READ)) |
2b3c8317 | 262 | drm_clflush_sg(pages); |
03ac84f1 | 263 | |
e27ab73d | 264 | __start_cpu_write(obj); |
03ac84f1 CW |
265 | } |
266 | ||
267 | static void | |
268 | i915_gem_object_put_pages_phys(struct drm_i915_gem_object *obj, | |
269 | struct sg_table *pages) | |
270 | { | |
e5facdf9 | 271 | __i915_gem_object_release_shmem(obj, pages, false); |
03ac84f1 | 272 | |
a4f5ea64 | 273 | if (obj->mm.dirty) { |
93c76a3d | 274 | struct address_space *mapping = obj->base.filp->f_mapping; |
6a2c4232 | 275 | char *vaddr = obj->phys_handle->vaddr; |
00731155 CW |
276 | int i; |
277 | ||
278 | for (i = 0; i < obj->base.size / PAGE_SIZE; i++) { | |
6a2c4232 CW |
279 | struct page *page; |
280 | char *dst; | |
281 | ||
282 | page = shmem_read_mapping_page(mapping, i); | |
283 | if (IS_ERR(page)) | |
284 | continue; | |
285 | ||
286 | dst = kmap_atomic(page); | |
287 | drm_clflush_virt_range(vaddr, PAGE_SIZE); | |
288 | memcpy(dst, vaddr, PAGE_SIZE); | |
289 | kunmap_atomic(dst); | |
290 | ||
291 | set_page_dirty(page); | |
a4f5ea64 | 292 | if (obj->mm.madv == I915_MADV_WILLNEED) |
00731155 | 293 | mark_page_accessed(page); |
09cbfeaf | 294 | put_page(page); |
00731155 CW |
295 | vaddr += PAGE_SIZE; |
296 | } | |
a4f5ea64 | 297 | obj->mm.dirty = false; |
00731155 CW |
298 | } |
299 | ||
03ac84f1 CW |
300 | sg_free_table(pages); |
301 | kfree(pages); | |
dbb4351b CW |
302 | |
303 | drm_pci_free(obj->base.dev, obj->phys_handle); | |
6a2c4232 CW |
304 | } |
305 | ||
306 | static void | |
307 | i915_gem_object_release_phys(struct drm_i915_gem_object *obj) | |
308 | { | |
a4f5ea64 | 309 | i915_gem_object_unpin_pages(obj); |
6a2c4232 CW |
310 | } |
311 | ||
312 | static const struct drm_i915_gem_object_ops i915_gem_phys_ops = { | |
313 | .get_pages = i915_gem_object_get_pages_phys, | |
314 | .put_pages = i915_gem_object_put_pages_phys, | |
315 | .release = i915_gem_object_release_phys, | |
316 | }; | |
317 | ||
581ab1fe CW |
318 | static const struct drm_i915_gem_object_ops i915_gem_object_ops; |
319 | ||
35a9611c | 320 | int i915_gem_object_unbind(struct drm_i915_gem_object *obj) |
aa653a68 CW |
321 | { |
322 | struct i915_vma *vma; | |
323 | LIST_HEAD(still_in_list); | |
02bef8f9 CW |
324 | int ret; |
325 | ||
326 | lockdep_assert_held(&obj->base.dev->struct_mutex); | |
aa653a68 | 327 | |
02bef8f9 CW |
328 | /* Closed vma are removed from the obj->vma_list - but they may |
329 | * still have an active binding on the object. To remove those we | |
330 | * must wait for all rendering to complete to the object (as unbinding | |
331 | * must anyway), and retire the requests. | |
aa653a68 | 332 | */ |
e95433c7 CW |
333 | ret = i915_gem_object_wait(obj, |
334 | I915_WAIT_INTERRUPTIBLE | | |
335 | I915_WAIT_LOCKED | | |
336 | I915_WAIT_ALL, | |
337 | MAX_SCHEDULE_TIMEOUT, | |
338 | NULL); | |
02bef8f9 CW |
339 | if (ret) |
340 | return ret; | |
341 | ||
342 | i915_gem_retire_requests(to_i915(obj->base.dev)); | |
343 | ||
aa653a68 CW |
344 | while ((vma = list_first_entry_or_null(&obj->vma_list, |
345 | struct i915_vma, | |
346 | obj_link))) { | |
347 | list_move_tail(&vma->obj_link, &still_in_list); | |
348 | ret = i915_vma_unbind(vma); | |
349 | if (ret) | |
350 | break; | |
351 | } | |
352 | list_splice(&still_in_list, &obj->vma_list); | |
353 | ||
354 | return ret; | |
355 | } | |
356 | ||
e95433c7 CW |
357 | static long |
358 | i915_gem_object_wait_fence(struct dma_fence *fence, | |
359 | unsigned int flags, | |
360 | long timeout, | |
562d9bae | 361 | struct intel_rps_client *rps_client) |
00e60f26 | 362 | { |
e95433c7 | 363 | struct drm_i915_gem_request *rq; |
00e60f26 | 364 | |
e95433c7 | 365 | BUILD_BUG_ON(I915_WAIT_INTERRUPTIBLE != 0x1); |
00e60f26 | 366 | |
e95433c7 CW |
367 | if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &fence->flags)) |
368 | return timeout; | |
369 | ||
370 | if (!dma_fence_is_i915(fence)) | |
371 | return dma_fence_wait_timeout(fence, | |
372 | flags & I915_WAIT_INTERRUPTIBLE, | |
373 | timeout); | |
374 | ||
375 | rq = to_request(fence); | |
376 | if (i915_gem_request_completed(rq)) | |
377 | goto out; | |
378 | ||
379 | /* This client is about to stall waiting for the GPU. In many cases | |
380 | * this is undesirable and limits the throughput of the system, as | |
381 | * many clients cannot continue processing user input/output whilst | |
382 | * blocked. RPS autotuning may take tens of milliseconds to respond | |
383 | * to the GPU load and thus incurs additional latency for the client. | |
384 | * We can circumvent that by promoting the GPU frequency to maximum | |
385 | * before we wait. This makes the GPU throttle up much more quickly | |
386 | * (good for benchmarks and user experience, e.g. window animations), | |
387 | * but at a cost of spending more power processing the workload | |
388 | * (bad for battery). Not all clients even want their results | |
389 | * immediately and for them we should just let the GPU select its own | |
390 | * frequency to maximise efficiency. To prevent a single client from | |
391 | * forcing the clocks too high for the whole system, we only allow | |
392 | * each client to waitboost once in a busy period. | |
393 | */ | |
562d9bae | 394 | if (rps_client) { |
e95433c7 | 395 | if (INTEL_GEN(rq->i915) >= 6) |
562d9bae | 396 | gen6_rps_boost(rq, rps_client); |
e95433c7 | 397 | else |
562d9bae | 398 | rps_client = NULL; |
00e60f26 CW |
399 | } |
400 | ||
e95433c7 CW |
401 | timeout = i915_wait_request(rq, flags, timeout); |
402 | ||
403 | out: | |
404 | if (flags & I915_WAIT_LOCKED && i915_gem_request_completed(rq)) | |
405 | i915_gem_request_retire_upto(rq); | |
406 | ||
e95433c7 CW |
407 | return timeout; |
408 | } | |
409 | ||
410 | static long | |
411 | i915_gem_object_wait_reservation(struct reservation_object *resv, | |
412 | unsigned int flags, | |
413 | long timeout, | |
562d9bae | 414 | struct intel_rps_client *rps_client) |
e95433c7 | 415 | { |
e54ca977 | 416 | unsigned int seq = __read_seqcount_begin(&resv->seq); |
e95433c7 | 417 | struct dma_fence *excl; |
e54ca977 | 418 | bool prune_fences = false; |
e95433c7 CW |
419 | |
420 | if (flags & I915_WAIT_ALL) { | |
421 | struct dma_fence **shared; | |
422 | unsigned int count, i; | |
00e60f26 CW |
423 | int ret; |
424 | ||
e95433c7 CW |
425 | ret = reservation_object_get_fences_rcu(resv, |
426 | &excl, &count, &shared); | |
00e60f26 CW |
427 | if (ret) |
428 | return ret; | |
00e60f26 | 429 | |
e95433c7 CW |
430 | for (i = 0; i < count; i++) { |
431 | timeout = i915_gem_object_wait_fence(shared[i], | |
432 | flags, timeout, | |
562d9bae | 433 | rps_client); |
d892e939 | 434 | if (timeout < 0) |
e95433c7 | 435 | break; |
00e60f26 | 436 | |
e95433c7 CW |
437 | dma_fence_put(shared[i]); |
438 | } | |
439 | ||
440 | for (; i < count; i++) | |
441 | dma_fence_put(shared[i]); | |
442 | kfree(shared); | |
e54ca977 CW |
443 | |
444 | prune_fences = count && timeout >= 0; | |
e95433c7 CW |
445 | } else { |
446 | excl = reservation_object_get_excl_rcu(resv); | |
00e60f26 CW |
447 | } |
448 | ||
e54ca977 | 449 | if (excl && timeout >= 0) { |
562d9bae SAK |
450 | timeout = i915_gem_object_wait_fence(excl, flags, timeout, |
451 | rps_client); | |
e54ca977 CW |
452 | prune_fences = timeout >= 0; |
453 | } | |
e95433c7 CW |
454 | |
455 | dma_fence_put(excl); | |
456 | ||
03d1cac6 CW |
457 | /* Oportunistically prune the fences iff we know they have *all* been |
458 | * signaled and that the reservation object has not been changed (i.e. | |
459 | * no new fences have been added). | |
460 | */ | |
e54ca977 | 461 | if (prune_fences && !__read_seqcount_retry(&resv->seq, seq)) { |
03d1cac6 CW |
462 | if (reservation_object_trylock(resv)) { |
463 | if (!__read_seqcount_retry(&resv->seq, seq)) | |
464 | reservation_object_add_excl_fence(resv, NULL); | |
465 | reservation_object_unlock(resv); | |
466 | } | |
e54ca977 CW |
467 | } |
468 | ||
e95433c7 | 469 | return timeout; |
00e60f26 CW |
470 | } |
471 | ||
6b5e90f5 CW |
472 | static void __fence_set_priority(struct dma_fence *fence, int prio) |
473 | { | |
474 | struct drm_i915_gem_request *rq; | |
475 | struct intel_engine_cs *engine; | |
476 | ||
477 | if (!dma_fence_is_i915(fence)) | |
478 | return; | |
479 | ||
480 | rq = to_request(fence); | |
481 | engine = rq->engine; | |
482 | if (!engine->schedule) | |
483 | return; | |
484 | ||
485 | engine->schedule(rq, prio); | |
486 | } | |
487 | ||
488 | static void fence_set_priority(struct dma_fence *fence, int prio) | |
489 | { | |
490 | /* Recurse once into a fence-array */ | |
491 | if (dma_fence_is_array(fence)) { | |
492 | struct dma_fence_array *array = to_dma_fence_array(fence); | |
493 | int i; | |
494 | ||
495 | for (i = 0; i < array->num_fences; i++) | |
496 | __fence_set_priority(array->fences[i], prio); | |
497 | } else { | |
498 | __fence_set_priority(fence, prio); | |
499 | } | |
500 | } | |
501 | ||
502 | int | |
503 | i915_gem_object_wait_priority(struct drm_i915_gem_object *obj, | |
504 | unsigned int flags, | |
505 | int prio) | |
506 | { | |
507 | struct dma_fence *excl; | |
508 | ||
509 | if (flags & I915_WAIT_ALL) { | |
510 | struct dma_fence **shared; | |
511 | unsigned int count, i; | |
512 | int ret; | |
513 | ||
514 | ret = reservation_object_get_fences_rcu(obj->resv, | |
515 | &excl, &count, &shared); | |
516 | if (ret) | |
517 | return ret; | |
518 | ||
519 | for (i = 0; i < count; i++) { | |
520 | fence_set_priority(shared[i], prio); | |
521 | dma_fence_put(shared[i]); | |
522 | } | |
523 | ||
524 | kfree(shared); | |
525 | } else { | |
526 | excl = reservation_object_get_excl_rcu(obj->resv); | |
527 | } | |
528 | ||
529 | if (excl) { | |
530 | fence_set_priority(excl, prio); | |
531 | dma_fence_put(excl); | |
532 | } | |
533 | return 0; | |
534 | } | |
535 | ||
e95433c7 CW |
536 | /** |
537 | * Waits for rendering to the object to be completed | |
538 | * @obj: i915 gem object | |
539 | * @flags: how to wait (under a lock, for all rendering or just for writes etc) | |
540 | * @timeout: how long to wait | |
541 | * @rps: client (user process) to charge for any waitboosting | |
00e60f26 | 542 | */ |
e95433c7 CW |
543 | int |
544 | i915_gem_object_wait(struct drm_i915_gem_object *obj, | |
545 | unsigned int flags, | |
546 | long timeout, | |
562d9bae | 547 | struct intel_rps_client *rps_client) |
00e60f26 | 548 | { |
e95433c7 CW |
549 | might_sleep(); |
550 | #if IS_ENABLED(CONFIG_LOCKDEP) | |
551 | GEM_BUG_ON(debug_locks && | |
552 | !!lockdep_is_held(&obj->base.dev->struct_mutex) != | |
553 | !!(flags & I915_WAIT_LOCKED)); | |
554 | #endif | |
555 | GEM_BUG_ON(timeout < 0); | |
00e60f26 | 556 | |
d07f0e59 CW |
557 | timeout = i915_gem_object_wait_reservation(obj->resv, |
558 | flags, timeout, | |
562d9bae | 559 | rps_client); |
e95433c7 | 560 | return timeout < 0 ? timeout : 0; |
00e60f26 CW |
561 | } |
562 | ||
563 | static struct intel_rps_client *to_rps_client(struct drm_file *file) | |
564 | { | |
565 | struct drm_i915_file_private *fpriv = file->driver_priv; | |
566 | ||
562d9bae | 567 | return &fpriv->rps_client; |
00e60f26 CW |
568 | } |
569 | ||
00731155 CW |
570 | static int |
571 | i915_gem_phys_pwrite(struct drm_i915_gem_object *obj, | |
572 | struct drm_i915_gem_pwrite *args, | |
03ac84f1 | 573 | struct drm_file *file) |
00731155 | 574 | { |
00731155 | 575 | void *vaddr = obj->phys_handle->vaddr + args->offset; |
3ed605bc | 576 | char __user *user_data = u64_to_user_ptr(args->data_ptr); |
6a2c4232 CW |
577 | |
578 | /* We manually control the domain here and pretend that it | |
579 | * remains coherent i.e. in the GTT domain, like shmem_pwrite. | |
580 | */ | |
77a0d1ca | 581 | intel_fb_obj_invalidate(obj, ORIGIN_CPU); |
10466d2a CW |
582 | if (copy_from_user(vaddr, user_data, args->size)) |
583 | return -EFAULT; | |
00731155 | 584 | |
6a2c4232 | 585 | drm_clflush_virt_range(vaddr, args->size); |
10466d2a | 586 | i915_gem_chipset_flush(to_i915(obj->base.dev)); |
063e4e6b | 587 | |
d59b21ec | 588 | intel_fb_obj_flush(obj, ORIGIN_CPU); |
10466d2a | 589 | return 0; |
00731155 CW |
590 | } |
591 | ||
187685cb | 592 | void *i915_gem_object_alloc(struct drm_i915_private *dev_priv) |
42dcedd4 | 593 | { |
efab6d8d | 594 | return kmem_cache_zalloc(dev_priv->objects, GFP_KERNEL); |
42dcedd4 CW |
595 | } |
596 | ||
597 | void i915_gem_object_free(struct drm_i915_gem_object *obj) | |
598 | { | |
fac5e23e | 599 | struct drm_i915_private *dev_priv = to_i915(obj->base.dev); |
efab6d8d | 600 | kmem_cache_free(dev_priv->objects, obj); |
42dcedd4 CW |
601 | } |
602 | ||
ff72145b DA |
603 | static int |
604 | i915_gem_create(struct drm_file *file, | |
12d79d78 | 605 | struct drm_i915_private *dev_priv, |
ff72145b DA |
606 | uint64_t size, |
607 | uint32_t *handle_p) | |
673a394b | 608 | { |
05394f39 | 609 | struct drm_i915_gem_object *obj; |
a1a2d1d3 PP |
610 | int ret; |
611 | u32 handle; | |
673a394b | 612 | |
ff72145b | 613 | size = roundup(size, PAGE_SIZE); |
8ffc0246 CW |
614 | if (size == 0) |
615 | return -EINVAL; | |
673a394b EA |
616 | |
617 | /* Allocate the new object */ | |
12d79d78 | 618 | obj = i915_gem_object_create(dev_priv, size); |
fe3db79b CW |
619 | if (IS_ERR(obj)) |
620 | return PTR_ERR(obj); | |
673a394b | 621 | |
05394f39 | 622 | ret = drm_gem_handle_create(file, &obj->base, &handle); |
202f2fef | 623 | /* drop reference from allocate - handle holds it now */ |
f0cd5182 | 624 | i915_gem_object_put(obj); |
d861e338 DV |
625 | if (ret) |
626 | return ret; | |
202f2fef | 627 | |
ff72145b | 628 | *handle_p = handle; |
673a394b EA |
629 | return 0; |
630 | } | |
631 | ||
ff72145b DA |
632 | int |
633 | i915_gem_dumb_create(struct drm_file *file, | |
634 | struct drm_device *dev, | |
635 | struct drm_mode_create_dumb *args) | |
636 | { | |
637 | /* have to work out size/pitch and return them */ | |
de45eaf7 | 638 | args->pitch = ALIGN(args->width * DIV_ROUND_UP(args->bpp, 8), 64); |
ff72145b | 639 | args->size = args->pitch * args->height; |
12d79d78 | 640 | return i915_gem_create(file, to_i915(dev), |
da6b51d0 | 641 | args->size, &args->handle); |
ff72145b DA |
642 | } |
643 | ||
e27ab73d CW |
644 | static bool gpu_write_needs_clflush(struct drm_i915_gem_object *obj) |
645 | { | |
646 | return !(obj->cache_level == I915_CACHE_NONE || | |
647 | obj->cache_level == I915_CACHE_WT); | |
648 | } | |
649 | ||
ff72145b DA |
650 | /** |
651 | * Creates a new mm object and returns a handle to it. | |
14bb2c11 TU |
652 | * @dev: drm device pointer |
653 | * @data: ioctl data blob | |
654 | * @file: drm file pointer | |
ff72145b DA |
655 | */ |
656 | int | |
657 | i915_gem_create_ioctl(struct drm_device *dev, void *data, | |
658 | struct drm_file *file) | |
659 | { | |
12d79d78 | 660 | struct drm_i915_private *dev_priv = to_i915(dev); |
ff72145b | 661 | struct drm_i915_gem_create *args = data; |
63ed2cb2 | 662 | |
12d79d78 | 663 | i915_gem_flush_free_objects(dev_priv); |
fbbd37b3 | 664 | |
12d79d78 | 665 | return i915_gem_create(file, dev_priv, |
da6b51d0 | 666 | args->size, &args->handle); |
ff72145b DA |
667 | } |
668 | ||
ef74921b CW |
669 | static inline enum fb_op_origin |
670 | fb_write_origin(struct drm_i915_gem_object *obj, unsigned int domain) | |
671 | { | |
672 | return (domain == I915_GEM_DOMAIN_GTT ? | |
673 | obj->frontbuffer_ggtt_origin : ORIGIN_CPU); | |
674 | } | |
675 | ||
676 | static void | |
677 | flush_write_domain(struct drm_i915_gem_object *obj, unsigned int flush_domains) | |
678 | { | |
679 | struct drm_i915_private *dev_priv = to_i915(obj->base.dev); | |
680 | ||
681 | if (!(obj->base.write_domain & flush_domains)) | |
682 | return; | |
683 | ||
684 | /* No actual flushing is required for the GTT write domain. Writes | |
685 | * to it "immediately" go to main memory as far as we know, so there's | |
686 | * no chipset flush. It also doesn't land in render cache. | |
687 | * | |
688 | * However, we do have to enforce the order so that all writes through | |
689 | * the GTT land before any writes to the device, such as updates to | |
690 | * the GATT itself. | |
691 | * | |
692 | * We also have to wait a bit for the writes to land from the GTT. | |
693 | * An uncached read (i.e. mmio) seems to be ideal for the round-trip | |
694 | * timing. This issue has only been observed when switching quickly | |
695 | * between GTT writes and CPU reads from inside the kernel on recent hw, | |
696 | * and it appears to only affect discrete GTT blocks (i.e. on LLC | |
697 | * system agents we cannot reproduce this behaviour). | |
698 | */ | |
699 | wmb(); | |
700 | ||
701 | switch (obj->base.write_domain) { | |
702 | case I915_GEM_DOMAIN_GTT: | |
c5ba5b24 | 703 | if (!HAS_LLC(dev_priv)) { |
b69a784f CW |
704 | intel_runtime_pm_get(dev_priv); |
705 | spin_lock_irq(&dev_priv->uncore.lock); | |
c5ba5b24 | 706 | POSTING_READ_FW(RING_HEAD(dev_priv->engine[RCS]->mmio_base)); |
b69a784f CW |
707 | spin_unlock_irq(&dev_priv->uncore.lock); |
708 | intel_runtime_pm_put(dev_priv); | |
ef74921b CW |
709 | } |
710 | ||
711 | intel_fb_obj_flush(obj, | |
712 | fb_write_origin(obj, I915_GEM_DOMAIN_GTT)); | |
713 | break; | |
714 | ||
715 | case I915_GEM_DOMAIN_CPU: | |
716 | i915_gem_clflush_object(obj, I915_CLFLUSH_SYNC); | |
717 | break; | |
e27ab73d CW |
718 | |
719 | case I915_GEM_DOMAIN_RENDER: | |
720 | if (gpu_write_needs_clflush(obj)) | |
721 | obj->cache_dirty = true; | |
722 | break; | |
ef74921b CW |
723 | } |
724 | ||
725 | obj->base.write_domain = 0; | |
726 | } | |
727 | ||
8461d226 DV |
728 | static inline int |
729 | __copy_to_user_swizzled(char __user *cpu_vaddr, | |
730 | const char *gpu_vaddr, int gpu_offset, | |
731 | int length) | |
732 | { | |
733 | int ret, cpu_offset = 0; | |
734 | ||
735 | while (length > 0) { | |
736 | int cacheline_end = ALIGN(gpu_offset + 1, 64); | |
737 | int this_length = min(cacheline_end - gpu_offset, length); | |
738 | int swizzled_gpu_offset = gpu_offset ^ 64; | |
739 | ||
740 | ret = __copy_to_user(cpu_vaddr + cpu_offset, | |
741 | gpu_vaddr + swizzled_gpu_offset, | |
742 | this_length); | |
743 | if (ret) | |
744 | return ret + length; | |
745 | ||
746 | cpu_offset += this_length; | |
747 | gpu_offset += this_length; | |
748 | length -= this_length; | |
749 | } | |
750 | ||
751 | return 0; | |
752 | } | |
753 | ||
8c59967c | 754 | static inline int |
4f0c7cfb BW |
755 | __copy_from_user_swizzled(char *gpu_vaddr, int gpu_offset, |
756 | const char __user *cpu_vaddr, | |
8c59967c DV |
757 | int length) |
758 | { | |
759 | int ret, cpu_offset = 0; | |
760 | ||
761 | while (length > 0) { | |
762 | int cacheline_end = ALIGN(gpu_offset + 1, 64); | |
763 | int this_length = min(cacheline_end - gpu_offset, length); | |
764 | int swizzled_gpu_offset = gpu_offset ^ 64; | |
765 | ||
766 | ret = __copy_from_user(gpu_vaddr + swizzled_gpu_offset, | |
767 | cpu_vaddr + cpu_offset, | |
768 | this_length); | |
769 | if (ret) | |
770 | return ret + length; | |
771 | ||
772 | cpu_offset += this_length; | |
773 | gpu_offset += this_length; | |
774 | length -= this_length; | |
775 | } | |
776 | ||
777 | return 0; | |
778 | } | |
779 | ||
4c914c0c BV |
780 | /* |
781 | * Pins the specified object's pages and synchronizes the object with | |
782 | * GPU accesses. Sets needs_clflush to non-zero if the caller should | |
783 | * flush the object from the CPU cache. | |
784 | */ | |
785 | int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj, | |
43394c7d | 786 | unsigned int *needs_clflush) |
4c914c0c BV |
787 | { |
788 | int ret; | |
789 | ||
e95433c7 | 790 | lockdep_assert_held(&obj->base.dev->struct_mutex); |
4c914c0c | 791 | |
e95433c7 | 792 | *needs_clflush = 0; |
43394c7d CW |
793 | if (!i915_gem_object_has_struct_page(obj)) |
794 | return -ENODEV; | |
4c914c0c | 795 | |
e95433c7 CW |
796 | ret = i915_gem_object_wait(obj, |
797 | I915_WAIT_INTERRUPTIBLE | | |
798 | I915_WAIT_LOCKED, | |
799 | MAX_SCHEDULE_TIMEOUT, | |
800 | NULL); | |
c13d87ea CW |
801 | if (ret) |
802 | return ret; | |
803 | ||
a4f5ea64 | 804 | ret = i915_gem_object_pin_pages(obj); |
9764951e CW |
805 | if (ret) |
806 | return ret; | |
807 | ||
b8f55be6 CW |
808 | if (obj->cache_coherent & I915_BO_CACHE_COHERENT_FOR_READ || |
809 | !static_cpu_has(X86_FEATURE_CLFLUSH)) { | |
7f5f95d8 CW |
810 | ret = i915_gem_object_set_to_cpu_domain(obj, false); |
811 | if (ret) | |
812 | goto err_unpin; | |
813 | else | |
814 | goto out; | |
815 | } | |
816 | ||
ef74921b | 817 | flush_write_domain(obj, ~I915_GEM_DOMAIN_CPU); |
a314d5cb | 818 | |
43394c7d CW |
819 | /* If we're not in the cpu read domain, set ourself into the gtt |
820 | * read domain and manually flush cachelines (if required). This | |
821 | * optimizes for the case when the gpu will dirty the data | |
822 | * anyway again before the next pread happens. | |
823 | */ | |
e27ab73d CW |
824 | if (!obj->cache_dirty && |
825 | !(obj->base.read_domains & I915_GEM_DOMAIN_CPU)) | |
7f5f95d8 | 826 | *needs_clflush = CLFLUSH_BEFORE; |
4c914c0c | 827 | |
7f5f95d8 | 828 | out: |
9764951e | 829 | /* return with the pages pinned */ |
43394c7d | 830 | return 0; |
9764951e CW |
831 | |
832 | err_unpin: | |
833 | i915_gem_object_unpin_pages(obj); | |
834 | return ret; | |
43394c7d CW |
835 | } |
836 | ||
837 | int i915_gem_obj_prepare_shmem_write(struct drm_i915_gem_object *obj, | |
838 | unsigned int *needs_clflush) | |
839 | { | |
840 | int ret; | |
841 | ||
e95433c7 CW |
842 | lockdep_assert_held(&obj->base.dev->struct_mutex); |
843 | ||
43394c7d CW |
844 | *needs_clflush = 0; |
845 | if (!i915_gem_object_has_struct_page(obj)) | |
846 | return -ENODEV; | |
847 | ||
e95433c7 CW |
848 | ret = i915_gem_object_wait(obj, |
849 | I915_WAIT_INTERRUPTIBLE | | |
850 | I915_WAIT_LOCKED | | |
851 | I915_WAIT_ALL, | |
852 | MAX_SCHEDULE_TIMEOUT, | |
853 | NULL); | |
43394c7d CW |
854 | if (ret) |
855 | return ret; | |
856 | ||
a4f5ea64 | 857 | ret = i915_gem_object_pin_pages(obj); |
9764951e CW |
858 | if (ret) |
859 | return ret; | |
860 | ||
b8f55be6 CW |
861 | if (obj->cache_coherent & I915_BO_CACHE_COHERENT_FOR_WRITE || |
862 | !static_cpu_has(X86_FEATURE_CLFLUSH)) { | |
7f5f95d8 CW |
863 | ret = i915_gem_object_set_to_cpu_domain(obj, true); |
864 | if (ret) | |
865 | goto err_unpin; | |
866 | else | |
867 | goto out; | |
868 | } | |
869 | ||
ef74921b | 870 | flush_write_domain(obj, ~I915_GEM_DOMAIN_CPU); |
a314d5cb | 871 | |
43394c7d CW |
872 | /* If we're not in the cpu write domain, set ourself into the |
873 | * gtt write domain and manually flush cachelines (as required). | |
874 | * This optimizes for the case when the gpu will use the data | |
875 | * right away and we therefore have to clflush anyway. | |
876 | */ | |
e27ab73d | 877 | if (!obj->cache_dirty) { |
7f5f95d8 | 878 | *needs_clflush |= CLFLUSH_AFTER; |
43394c7d | 879 | |
e27ab73d CW |
880 | /* |
881 | * Same trick applies to invalidate partially written | |
882 | * cachelines read before writing. | |
883 | */ | |
884 | if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU)) | |
885 | *needs_clflush |= CLFLUSH_BEFORE; | |
886 | } | |
43394c7d | 887 | |
7f5f95d8 | 888 | out: |
43394c7d | 889 | intel_fb_obj_invalidate(obj, ORIGIN_CPU); |
a4f5ea64 | 890 | obj->mm.dirty = true; |
9764951e | 891 | /* return with the pages pinned */ |
43394c7d | 892 | return 0; |
9764951e CW |
893 | |
894 | err_unpin: | |
895 | i915_gem_object_unpin_pages(obj); | |
896 | return ret; | |
4c914c0c BV |
897 | } |
898 | ||
23c18c71 DV |
899 | static void |
900 | shmem_clflush_swizzled_range(char *addr, unsigned long length, | |
901 | bool swizzled) | |
902 | { | |
e7e58eb5 | 903 | if (unlikely(swizzled)) { |
23c18c71 DV |
904 | unsigned long start = (unsigned long) addr; |
905 | unsigned long end = (unsigned long) addr + length; | |
906 | ||
907 | /* For swizzling simply ensure that we always flush both | |
908 | * channels. Lame, but simple and it works. Swizzled | |
909 | * pwrite/pread is far from a hotpath - current userspace | |
910 | * doesn't use it at all. */ | |
911 | start = round_down(start, 128); | |
912 | end = round_up(end, 128); | |
913 | ||
914 | drm_clflush_virt_range((void *)start, end - start); | |
915 | } else { | |
916 | drm_clflush_virt_range(addr, length); | |
917 | } | |
918 | ||
919 | } | |
920 | ||
d174bd64 DV |
921 | /* Only difference to the fast-path function is that this can handle bit17 |
922 | * and uses non-atomic copy and kmap functions. */ | |
923 | static int | |
bb6dc8d9 | 924 | shmem_pread_slow(struct page *page, int offset, int length, |
d174bd64 DV |
925 | char __user *user_data, |
926 | bool page_do_bit17_swizzling, bool needs_clflush) | |
927 | { | |
928 | char *vaddr; | |
929 | int ret; | |
930 | ||
931 | vaddr = kmap(page); | |
932 | if (needs_clflush) | |
bb6dc8d9 | 933 | shmem_clflush_swizzled_range(vaddr + offset, length, |
23c18c71 | 934 | page_do_bit17_swizzling); |
d174bd64 DV |
935 | |
936 | if (page_do_bit17_swizzling) | |
bb6dc8d9 | 937 | ret = __copy_to_user_swizzled(user_data, vaddr, offset, length); |
d174bd64 | 938 | else |
bb6dc8d9 | 939 | ret = __copy_to_user(user_data, vaddr + offset, length); |
d174bd64 DV |
940 | kunmap(page); |
941 | ||
f60d7f0c | 942 | return ret ? - EFAULT : 0; |
d174bd64 DV |
943 | } |
944 | ||
bb6dc8d9 CW |
945 | static int |
946 | shmem_pread(struct page *page, int offset, int length, char __user *user_data, | |
947 | bool page_do_bit17_swizzling, bool needs_clflush) | |
948 | { | |
949 | int ret; | |
950 | ||
951 | ret = -ENODEV; | |
952 | if (!page_do_bit17_swizzling) { | |
953 | char *vaddr = kmap_atomic(page); | |
954 | ||
955 | if (needs_clflush) | |
956 | drm_clflush_virt_range(vaddr + offset, length); | |
957 | ret = __copy_to_user_inatomic(user_data, vaddr + offset, length); | |
958 | kunmap_atomic(vaddr); | |
959 | } | |
960 | if (ret == 0) | |
961 | return 0; | |
962 | ||
963 | return shmem_pread_slow(page, offset, length, user_data, | |
964 | page_do_bit17_swizzling, needs_clflush); | |
965 | } | |
966 | ||
967 | static int | |
968 | i915_gem_shmem_pread(struct drm_i915_gem_object *obj, | |
969 | struct drm_i915_gem_pread *args) | |
970 | { | |
971 | char __user *user_data; | |
972 | u64 remain; | |
973 | unsigned int obj_do_bit17_swizzling; | |
974 | unsigned int needs_clflush; | |
975 | unsigned int idx, offset; | |
976 | int ret; | |
977 | ||
978 | obj_do_bit17_swizzling = 0; | |
979 | if (i915_gem_object_needs_bit17_swizzle(obj)) | |
980 | obj_do_bit17_swizzling = BIT(17); | |
981 | ||
982 | ret = mutex_lock_interruptible(&obj->base.dev->struct_mutex); | |
983 | if (ret) | |
984 | return ret; | |
985 | ||
986 | ret = i915_gem_obj_prepare_shmem_read(obj, &needs_clflush); | |
987 | mutex_unlock(&obj->base.dev->struct_mutex); | |
988 | if (ret) | |
989 | return ret; | |
990 | ||
991 | remain = args->size; | |
992 | user_data = u64_to_user_ptr(args->data_ptr); | |
993 | offset = offset_in_page(args->offset); | |
994 | for (idx = args->offset >> PAGE_SHIFT; remain; idx++) { | |
995 | struct page *page = i915_gem_object_get_page(obj, idx); | |
996 | int length; | |
997 | ||
998 | length = remain; | |
999 | if (offset + length > PAGE_SIZE) | |
1000 | length = PAGE_SIZE - offset; | |
1001 | ||
1002 | ret = shmem_pread(page, offset, length, user_data, | |
1003 | page_to_phys(page) & obj_do_bit17_swizzling, | |
1004 | needs_clflush); | |
1005 | if (ret) | |
1006 | break; | |
1007 | ||
1008 | remain -= length; | |
1009 | user_data += length; | |
1010 | offset = 0; | |
1011 | } | |
1012 | ||
1013 | i915_gem_obj_finish_shmem_access(obj); | |
1014 | return ret; | |
1015 | } | |
1016 | ||
1017 | static inline bool | |
1018 | gtt_user_read(struct io_mapping *mapping, | |
1019 | loff_t base, int offset, | |
1020 | char __user *user_data, int length) | |
b50a5371 | 1021 | { |
afe722be | 1022 | void __iomem *vaddr; |
bb6dc8d9 | 1023 | unsigned long unwritten; |
b50a5371 | 1024 | |
b50a5371 | 1025 | /* We can use the cpu mem copy function because this is X86. */ |
afe722be VS |
1026 | vaddr = io_mapping_map_atomic_wc(mapping, base); |
1027 | unwritten = __copy_to_user_inatomic(user_data, | |
1028 | (void __force *)vaddr + offset, | |
1029 | length); | |
bb6dc8d9 CW |
1030 | io_mapping_unmap_atomic(vaddr); |
1031 | if (unwritten) { | |
afe722be VS |
1032 | vaddr = io_mapping_map_wc(mapping, base, PAGE_SIZE); |
1033 | unwritten = copy_to_user(user_data, | |
1034 | (void __force *)vaddr + offset, | |
1035 | length); | |
bb6dc8d9 CW |
1036 | io_mapping_unmap(vaddr); |
1037 | } | |
b50a5371 AS |
1038 | return unwritten; |
1039 | } | |
1040 | ||
1041 | static int | |
bb6dc8d9 CW |
1042 | i915_gem_gtt_pread(struct drm_i915_gem_object *obj, |
1043 | const struct drm_i915_gem_pread *args) | |
b50a5371 | 1044 | { |
bb6dc8d9 CW |
1045 | struct drm_i915_private *i915 = to_i915(obj->base.dev); |
1046 | struct i915_ggtt *ggtt = &i915->ggtt; | |
b50a5371 | 1047 | struct drm_mm_node node; |
bb6dc8d9 CW |
1048 | struct i915_vma *vma; |
1049 | void __user *user_data; | |
1050 | u64 remain, offset; | |
b50a5371 AS |
1051 | int ret; |
1052 | ||
bb6dc8d9 CW |
1053 | ret = mutex_lock_interruptible(&i915->drm.struct_mutex); |
1054 | if (ret) | |
1055 | return ret; | |
1056 | ||
1057 | intel_runtime_pm_get(i915); | |
1058 | vma = i915_gem_object_ggtt_pin(obj, NULL, 0, 0, | |
a3259ca9 CW |
1059 | PIN_MAPPABLE | |
1060 | PIN_NONFAULT | | |
1061 | PIN_NONBLOCK); | |
18034584 CW |
1062 | if (!IS_ERR(vma)) { |
1063 | node.start = i915_ggtt_offset(vma); | |
1064 | node.allocated = false; | |
49ef5294 | 1065 | ret = i915_vma_put_fence(vma); |
18034584 CW |
1066 | if (ret) { |
1067 | i915_vma_unpin(vma); | |
1068 | vma = ERR_PTR(ret); | |
1069 | } | |
1070 | } | |
058d88c4 | 1071 | if (IS_ERR(vma)) { |
bb6dc8d9 | 1072 | ret = insert_mappable_node(ggtt, &node, PAGE_SIZE); |
b50a5371 | 1073 | if (ret) |
bb6dc8d9 CW |
1074 | goto out_unlock; |
1075 | GEM_BUG_ON(!node.allocated); | |
b50a5371 AS |
1076 | } |
1077 | ||
1078 | ret = i915_gem_object_set_to_gtt_domain(obj, false); | |
1079 | if (ret) | |
1080 | goto out_unpin; | |
1081 | ||
bb6dc8d9 | 1082 | mutex_unlock(&i915->drm.struct_mutex); |
b50a5371 | 1083 | |
bb6dc8d9 CW |
1084 | user_data = u64_to_user_ptr(args->data_ptr); |
1085 | remain = args->size; | |
1086 | offset = args->offset; | |
b50a5371 AS |
1087 | |
1088 | while (remain > 0) { | |
1089 | /* Operation in this page | |
1090 | * | |
1091 | * page_base = page offset within aperture | |
1092 | * page_offset = offset within page | |
1093 | * page_length = bytes to copy for this page | |
1094 | */ | |
1095 | u32 page_base = node.start; | |
1096 | unsigned page_offset = offset_in_page(offset); | |
1097 | unsigned page_length = PAGE_SIZE - page_offset; | |
1098 | page_length = remain < page_length ? remain : page_length; | |
1099 | if (node.allocated) { | |
1100 | wmb(); | |
1101 | ggtt->base.insert_page(&ggtt->base, | |
1102 | i915_gem_object_get_dma_address(obj, offset >> PAGE_SHIFT), | |
bb6dc8d9 | 1103 | node.start, I915_CACHE_NONE, 0); |
b50a5371 AS |
1104 | wmb(); |
1105 | } else { | |
1106 | page_base += offset & PAGE_MASK; | |
1107 | } | |
bb6dc8d9 CW |
1108 | |
1109 | if (gtt_user_read(&ggtt->mappable, page_base, page_offset, | |
1110 | user_data, page_length)) { | |
b50a5371 AS |
1111 | ret = -EFAULT; |
1112 | break; | |
1113 | } | |
1114 | ||
1115 | remain -= page_length; | |
1116 | user_data += page_length; | |
1117 | offset += page_length; | |
1118 | } | |
1119 | ||
bb6dc8d9 | 1120 | mutex_lock(&i915->drm.struct_mutex); |
b50a5371 AS |
1121 | out_unpin: |
1122 | if (node.allocated) { | |
1123 | wmb(); | |
1124 | ggtt->base.clear_range(&ggtt->base, | |
4fb84d99 | 1125 | node.start, node.size); |
b50a5371 AS |
1126 | remove_mappable_node(&node); |
1127 | } else { | |
058d88c4 | 1128 | i915_vma_unpin(vma); |
b50a5371 | 1129 | } |
bb6dc8d9 CW |
1130 | out_unlock: |
1131 | intel_runtime_pm_put(i915); | |
1132 | mutex_unlock(&i915->drm.struct_mutex); | |
f60d7f0c | 1133 | |
eb01459f EA |
1134 | return ret; |
1135 | } | |
1136 | ||
673a394b EA |
1137 | /** |
1138 | * Reads data from the object referenced by handle. | |
14bb2c11 TU |
1139 | * @dev: drm device pointer |
1140 | * @data: ioctl data blob | |
1141 | * @file: drm file pointer | |
673a394b EA |
1142 | * |
1143 | * On error, the contents of *data are undefined. | |
1144 | */ | |
1145 | int | |
1146 | i915_gem_pread_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 1147 | struct drm_file *file) |
673a394b EA |
1148 | { |
1149 | struct drm_i915_gem_pread *args = data; | |
05394f39 | 1150 | struct drm_i915_gem_object *obj; |
bb6dc8d9 | 1151 | int ret; |
673a394b | 1152 | |
51311d0a CW |
1153 | if (args->size == 0) |
1154 | return 0; | |
1155 | ||
1156 | if (!access_ok(VERIFY_WRITE, | |
3ed605bc | 1157 | u64_to_user_ptr(args->data_ptr), |
51311d0a CW |
1158 | args->size)) |
1159 | return -EFAULT; | |
1160 | ||
03ac0642 | 1161 | obj = i915_gem_object_lookup(file, args->handle); |
258a5ede CW |
1162 | if (!obj) |
1163 | return -ENOENT; | |
673a394b | 1164 | |
7dcd2499 | 1165 | /* Bounds check source. */ |
966d5bf5 | 1166 | if (range_overflows_t(u64, args->offset, args->size, obj->base.size)) { |
ce9d419d | 1167 | ret = -EINVAL; |
bb6dc8d9 | 1168 | goto out; |
ce9d419d CW |
1169 | } |
1170 | ||
db53a302 CW |
1171 | trace_i915_gem_object_pread(obj, args->offset, args->size); |
1172 | ||
e95433c7 CW |
1173 | ret = i915_gem_object_wait(obj, |
1174 | I915_WAIT_INTERRUPTIBLE, | |
1175 | MAX_SCHEDULE_TIMEOUT, | |
1176 | to_rps_client(file)); | |
258a5ede | 1177 | if (ret) |
bb6dc8d9 | 1178 | goto out; |
258a5ede | 1179 | |
bb6dc8d9 | 1180 | ret = i915_gem_object_pin_pages(obj); |
258a5ede | 1181 | if (ret) |
bb6dc8d9 | 1182 | goto out; |
673a394b | 1183 | |
bb6dc8d9 | 1184 | ret = i915_gem_shmem_pread(obj, args); |
9c870d03 | 1185 | if (ret == -EFAULT || ret == -ENODEV) |
bb6dc8d9 | 1186 | ret = i915_gem_gtt_pread(obj, args); |
b50a5371 | 1187 | |
bb6dc8d9 CW |
1188 | i915_gem_object_unpin_pages(obj); |
1189 | out: | |
f0cd5182 | 1190 | i915_gem_object_put(obj); |
eb01459f | 1191 | return ret; |
673a394b EA |
1192 | } |
1193 | ||
0839ccb8 KP |
1194 | /* This is the fast write path which cannot handle |
1195 | * page faults in the source data | |
9b7530cc | 1196 | */ |
0839ccb8 | 1197 | |
fe115628 CW |
1198 | static inline bool |
1199 | ggtt_write(struct io_mapping *mapping, | |
1200 | loff_t base, int offset, | |
1201 | char __user *user_data, int length) | |
9b7530cc | 1202 | { |
afe722be | 1203 | void __iomem *vaddr; |
0839ccb8 | 1204 | unsigned long unwritten; |
9b7530cc | 1205 | |
4f0c7cfb | 1206 | /* We can use the cpu mem copy function because this is X86. */ |
afe722be VS |
1207 | vaddr = io_mapping_map_atomic_wc(mapping, base); |
1208 | unwritten = __copy_from_user_inatomic_nocache((void __force *)vaddr + offset, | |
0839ccb8 | 1209 | user_data, length); |
fe115628 CW |
1210 | io_mapping_unmap_atomic(vaddr); |
1211 | if (unwritten) { | |
afe722be VS |
1212 | vaddr = io_mapping_map_wc(mapping, base, PAGE_SIZE); |
1213 | unwritten = copy_from_user((void __force *)vaddr + offset, | |
1214 | user_data, length); | |
fe115628 CW |
1215 | io_mapping_unmap(vaddr); |
1216 | } | |
bb6dc8d9 | 1217 | |
bb6dc8d9 CW |
1218 | return unwritten; |
1219 | } | |
1220 | ||
3de09aa3 EA |
1221 | /** |
1222 | * This is the fast pwrite path, where we copy the data directly from the | |
1223 | * user into the GTT, uncached. | |
fe115628 | 1224 | * @obj: i915 GEM object |
14bb2c11 | 1225 | * @args: pwrite arguments structure |
3de09aa3 | 1226 | */ |
673a394b | 1227 | static int |
fe115628 CW |
1228 | i915_gem_gtt_pwrite_fast(struct drm_i915_gem_object *obj, |
1229 | const struct drm_i915_gem_pwrite *args) | |
673a394b | 1230 | { |
fe115628 | 1231 | struct drm_i915_private *i915 = to_i915(obj->base.dev); |
4f1959ee AS |
1232 | struct i915_ggtt *ggtt = &i915->ggtt; |
1233 | struct drm_mm_node node; | |
fe115628 CW |
1234 | struct i915_vma *vma; |
1235 | u64 remain, offset; | |
1236 | void __user *user_data; | |
4f1959ee | 1237 | int ret; |
b50a5371 | 1238 | |
fe115628 CW |
1239 | ret = mutex_lock_interruptible(&i915->drm.struct_mutex); |
1240 | if (ret) | |
1241 | return ret; | |
935aaa69 | 1242 | |
9c870d03 | 1243 | intel_runtime_pm_get(i915); |
058d88c4 | 1244 | vma = i915_gem_object_ggtt_pin(obj, NULL, 0, 0, |
a3259ca9 CW |
1245 | PIN_MAPPABLE | |
1246 | PIN_NONFAULT | | |
1247 | PIN_NONBLOCK); | |
18034584 CW |
1248 | if (!IS_ERR(vma)) { |
1249 | node.start = i915_ggtt_offset(vma); | |
1250 | node.allocated = false; | |
49ef5294 | 1251 | ret = i915_vma_put_fence(vma); |
18034584 CW |
1252 | if (ret) { |
1253 | i915_vma_unpin(vma); | |
1254 | vma = ERR_PTR(ret); | |
1255 | } | |
1256 | } | |
058d88c4 | 1257 | if (IS_ERR(vma)) { |
bb6dc8d9 | 1258 | ret = insert_mappable_node(ggtt, &node, PAGE_SIZE); |
4f1959ee | 1259 | if (ret) |
fe115628 CW |
1260 | goto out_unlock; |
1261 | GEM_BUG_ON(!node.allocated); | |
4f1959ee | 1262 | } |
935aaa69 DV |
1263 | |
1264 | ret = i915_gem_object_set_to_gtt_domain(obj, true); | |
1265 | if (ret) | |
1266 | goto out_unpin; | |
1267 | ||
fe115628 CW |
1268 | mutex_unlock(&i915->drm.struct_mutex); |
1269 | ||
b19482d7 | 1270 | intel_fb_obj_invalidate(obj, ORIGIN_CPU); |
063e4e6b | 1271 | |
4f1959ee AS |
1272 | user_data = u64_to_user_ptr(args->data_ptr); |
1273 | offset = args->offset; | |
1274 | remain = args->size; | |
1275 | while (remain) { | |
673a394b EA |
1276 | /* Operation in this page |
1277 | * | |
0839ccb8 KP |
1278 | * page_base = page offset within aperture |
1279 | * page_offset = offset within page | |
1280 | * page_length = bytes to copy for this page | |
673a394b | 1281 | */ |
4f1959ee | 1282 | u32 page_base = node.start; |
bb6dc8d9 CW |
1283 | unsigned int page_offset = offset_in_page(offset); |
1284 | unsigned int page_length = PAGE_SIZE - page_offset; | |
4f1959ee AS |
1285 | page_length = remain < page_length ? remain : page_length; |
1286 | if (node.allocated) { | |
1287 | wmb(); /* flush the write before we modify the GGTT */ | |
1288 | ggtt->base.insert_page(&ggtt->base, | |
1289 | i915_gem_object_get_dma_address(obj, offset >> PAGE_SHIFT), | |
1290 | node.start, I915_CACHE_NONE, 0); | |
1291 | wmb(); /* flush modifications to the GGTT (insert_page) */ | |
1292 | } else { | |
1293 | page_base += offset & PAGE_MASK; | |
1294 | } | |
0839ccb8 | 1295 | /* If we get a fault while copying data, then (presumably) our |
3de09aa3 EA |
1296 | * source page isn't available. Return the error and we'll |
1297 | * retry in the slow path. | |
b50a5371 AS |
1298 | * If the object is non-shmem backed, we retry again with the |
1299 | * path that handles page fault. | |
0839ccb8 | 1300 | */ |
fe115628 CW |
1301 | if (ggtt_write(&ggtt->mappable, page_base, page_offset, |
1302 | user_data, page_length)) { | |
1303 | ret = -EFAULT; | |
1304 | break; | |
935aaa69 | 1305 | } |
673a394b | 1306 | |
0839ccb8 KP |
1307 | remain -= page_length; |
1308 | user_data += page_length; | |
1309 | offset += page_length; | |
673a394b | 1310 | } |
d59b21ec | 1311 | intel_fb_obj_flush(obj, ORIGIN_CPU); |
fe115628 CW |
1312 | |
1313 | mutex_lock(&i915->drm.struct_mutex); | |
935aaa69 | 1314 | out_unpin: |
4f1959ee AS |
1315 | if (node.allocated) { |
1316 | wmb(); | |
1317 | ggtt->base.clear_range(&ggtt->base, | |
4fb84d99 | 1318 | node.start, node.size); |
4f1959ee AS |
1319 | remove_mappable_node(&node); |
1320 | } else { | |
058d88c4 | 1321 | i915_vma_unpin(vma); |
4f1959ee | 1322 | } |
fe115628 | 1323 | out_unlock: |
9c870d03 | 1324 | intel_runtime_pm_put(i915); |
fe115628 | 1325 | mutex_unlock(&i915->drm.struct_mutex); |
3de09aa3 | 1326 | return ret; |
673a394b EA |
1327 | } |
1328 | ||
3043c60c | 1329 | static int |
fe115628 | 1330 | shmem_pwrite_slow(struct page *page, int offset, int length, |
d174bd64 DV |
1331 | char __user *user_data, |
1332 | bool page_do_bit17_swizzling, | |
1333 | bool needs_clflush_before, | |
1334 | bool needs_clflush_after) | |
673a394b | 1335 | { |
d174bd64 DV |
1336 | char *vaddr; |
1337 | int ret; | |
e5281ccd | 1338 | |
d174bd64 | 1339 | vaddr = kmap(page); |
e7e58eb5 | 1340 | if (unlikely(needs_clflush_before || page_do_bit17_swizzling)) |
fe115628 | 1341 | shmem_clflush_swizzled_range(vaddr + offset, length, |
23c18c71 | 1342 | page_do_bit17_swizzling); |
d174bd64 | 1343 | if (page_do_bit17_swizzling) |
fe115628 CW |
1344 | ret = __copy_from_user_swizzled(vaddr, offset, user_data, |
1345 | length); | |
d174bd64 | 1346 | else |
fe115628 | 1347 | ret = __copy_from_user(vaddr + offset, user_data, length); |
d174bd64 | 1348 | if (needs_clflush_after) |
fe115628 | 1349 | shmem_clflush_swizzled_range(vaddr + offset, length, |
23c18c71 | 1350 | page_do_bit17_swizzling); |
d174bd64 | 1351 | kunmap(page); |
40123c1f | 1352 | |
755d2218 | 1353 | return ret ? -EFAULT : 0; |
40123c1f EA |
1354 | } |
1355 | ||
fe115628 CW |
1356 | /* Per-page copy function for the shmem pwrite fastpath. |
1357 | * Flushes invalid cachelines before writing to the target if | |
1358 | * needs_clflush_before is set and flushes out any written cachelines after | |
1359 | * writing if needs_clflush is set. | |
1360 | */ | |
40123c1f | 1361 | static int |
fe115628 CW |
1362 | shmem_pwrite(struct page *page, int offset, int len, char __user *user_data, |
1363 | bool page_do_bit17_swizzling, | |
1364 | bool needs_clflush_before, | |
1365 | bool needs_clflush_after) | |
40123c1f | 1366 | { |
fe115628 CW |
1367 | int ret; |
1368 | ||
1369 | ret = -ENODEV; | |
1370 | if (!page_do_bit17_swizzling) { | |
1371 | char *vaddr = kmap_atomic(page); | |
1372 | ||
1373 | if (needs_clflush_before) | |
1374 | drm_clflush_virt_range(vaddr + offset, len); | |
1375 | ret = __copy_from_user_inatomic(vaddr + offset, user_data, len); | |
1376 | if (needs_clflush_after) | |
1377 | drm_clflush_virt_range(vaddr + offset, len); | |
1378 | ||
1379 | kunmap_atomic(vaddr); | |
1380 | } | |
1381 | if (ret == 0) | |
1382 | return ret; | |
1383 | ||
1384 | return shmem_pwrite_slow(page, offset, len, user_data, | |
1385 | page_do_bit17_swizzling, | |
1386 | needs_clflush_before, | |
1387 | needs_clflush_after); | |
1388 | } | |
1389 | ||
1390 | static int | |
1391 | i915_gem_shmem_pwrite(struct drm_i915_gem_object *obj, | |
1392 | const struct drm_i915_gem_pwrite *args) | |
1393 | { | |
1394 | struct drm_i915_private *i915 = to_i915(obj->base.dev); | |
1395 | void __user *user_data; | |
1396 | u64 remain; | |
1397 | unsigned int obj_do_bit17_swizzling; | |
1398 | unsigned int partial_cacheline_write; | |
43394c7d | 1399 | unsigned int needs_clflush; |
fe115628 CW |
1400 | unsigned int offset, idx; |
1401 | int ret; | |
40123c1f | 1402 | |
fe115628 | 1403 | ret = mutex_lock_interruptible(&i915->drm.struct_mutex); |
755d2218 CW |
1404 | if (ret) |
1405 | return ret; | |
1406 | ||
fe115628 CW |
1407 | ret = i915_gem_obj_prepare_shmem_write(obj, &needs_clflush); |
1408 | mutex_unlock(&i915->drm.struct_mutex); | |
1409 | if (ret) | |
1410 | return ret; | |
673a394b | 1411 | |
fe115628 CW |
1412 | obj_do_bit17_swizzling = 0; |
1413 | if (i915_gem_object_needs_bit17_swizzle(obj)) | |
1414 | obj_do_bit17_swizzling = BIT(17); | |
e5281ccd | 1415 | |
fe115628 CW |
1416 | /* If we don't overwrite a cacheline completely we need to be |
1417 | * careful to have up-to-date data by first clflushing. Don't | |
1418 | * overcomplicate things and flush the entire patch. | |
1419 | */ | |
1420 | partial_cacheline_write = 0; | |
1421 | if (needs_clflush & CLFLUSH_BEFORE) | |
1422 | partial_cacheline_write = boot_cpu_data.x86_clflush_size - 1; | |
9da3da66 | 1423 | |
fe115628 CW |
1424 | user_data = u64_to_user_ptr(args->data_ptr); |
1425 | remain = args->size; | |
1426 | offset = offset_in_page(args->offset); | |
1427 | for (idx = args->offset >> PAGE_SHIFT; remain; idx++) { | |
1428 | struct page *page = i915_gem_object_get_page(obj, idx); | |
1429 | int length; | |
40123c1f | 1430 | |
fe115628 CW |
1431 | length = remain; |
1432 | if (offset + length > PAGE_SIZE) | |
1433 | length = PAGE_SIZE - offset; | |
755d2218 | 1434 | |
fe115628 CW |
1435 | ret = shmem_pwrite(page, offset, length, user_data, |
1436 | page_to_phys(page) & obj_do_bit17_swizzling, | |
1437 | (offset | length) & partial_cacheline_write, | |
1438 | needs_clflush & CLFLUSH_AFTER); | |
755d2218 | 1439 | if (ret) |
fe115628 | 1440 | break; |
755d2218 | 1441 | |
fe115628 CW |
1442 | remain -= length; |
1443 | user_data += length; | |
1444 | offset = 0; | |
8c59967c | 1445 | } |
673a394b | 1446 | |
d59b21ec | 1447 | intel_fb_obj_flush(obj, ORIGIN_CPU); |
fe115628 | 1448 | i915_gem_obj_finish_shmem_access(obj); |
40123c1f | 1449 | return ret; |
673a394b EA |
1450 | } |
1451 | ||
1452 | /** | |
1453 | * Writes data to the object referenced by handle. | |
14bb2c11 TU |
1454 | * @dev: drm device |
1455 | * @data: ioctl data blob | |
1456 | * @file: drm file | |
673a394b EA |
1457 | * |
1458 | * On error, the contents of the buffer that were to be modified are undefined. | |
1459 | */ | |
1460 | int | |
1461 | i915_gem_pwrite_ioctl(struct drm_device *dev, void *data, | |
fbd5a26d | 1462 | struct drm_file *file) |
673a394b EA |
1463 | { |
1464 | struct drm_i915_gem_pwrite *args = data; | |
05394f39 | 1465 | struct drm_i915_gem_object *obj; |
51311d0a CW |
1466 | int ret; |
1467 | ||
1468 | if (args->size == 0) | |
1469 | return 0; | |
1470 | ||
1471 | if (!access_ok(VERIFY_READ, | |
3ed605bc | 1472 | u64_to_user_ptr(args->data_ptr), |
51311d0a CW |
1473 | args->size)) |
1474 | return -EFAULT; | |
1475 | ||
03ac0642 | 1476 | obj = i915_gem_object_lookup(file, args->handle); |
258a5ede CW |
1477 | if (!obj) |
1478 | return -ENOENT; | |
673a394b | 1479 | |
7dcd2499 | 1480 | /* Bounds check destination. */ |
966d5bf5 | 1481 | if (range_overflows_t(u64, args->offset, args->size, obj->base.size)) { |
ce9d419d | 1482 | ret = -EINVAL; |
258a5ede | 1483 | goto err; |
ce9d419d CW |
1484 | } |
1485 | ||
db53a302 CW |
1486 | trace_i915_gem_object_pwrite(obj, args->offset, args->size); |
1487 | ||
7c55e2c5 CW |
1488 | ret = -ENODEV; |
1489 | if (obj->ops->pwrite) | |
1490 | ret = obj->ops->pwrite(obj, args); | |
1491 | if (ret != -ENODEV) | |
1492 | goto err; | |
1493 | ||
e95433c7 CW |
1494 | ret = i915_gem_object_wait(obj, |
1495 | I915_WAIT_INTERRUPTIBLE | | |
1496 | I915_WAIT_ALL, | |
1497 | MAX_SCHEDULE_TIMEOUT, | |
1498 | to_rps_client(file)); | |
258a5ede CW |
1499 | if (ret) |
1500 | goto err; | |
1501 | ||
fe115628 | 1502 | ret = i915_gem_object_pin_pages(obj); |
258a5ede | 1503 | if (ret) |
fe115628 | 1504 | goto err; |
258a5ede | 1505 | |
935aaa69 | 1506 | ret = -EFAULT; |
673a394b EA |
1507 | /* We can only do the GTT pwrite on untiled buffers, as otherwise |
1508 | * it would end up going through the fenced access, and we'll get | |
1509 | * different detiling behavior between reading and writing. | |
1510 | * pread/pwrite currently are reading and writing from the CPU | |
1511 | * perspective, requiring manual detiling by the client. | |
1512 | */ | |
6eae0059 | 1513 | if (!i915_gem_object_has_struct_page(obj) || |
9c870d03 | 1514 | cpu_write_needs_clflush(obj)) |
935aaa69 DV |
1515 | /* Note that the gtt paths might fail with non-page-backed user |
1516 | * pointers (e.g. gtt mappings when moving data between | |
9c870d03 CW |
1517 | * textures). Fallback to the shmem path in that case. |
1518 | */ | |
fe115628 | 1519 | ret = i915_gem_gtt_pwrite_fast(obj, args); |
673a394b | 1520 | |
d1054ee4 | 1521 | if (ret == -EFAULT || ret == -ENOSPC) { |
6a2c4232 CW |
1522 | if (obj->phys_handle) |
1523 | ret = i915_gem_phys_pwrite(obj, args, file); | |
b50a5371 | 1524 | else |
fe115628 | 1525 | ret = i915_gem_shmem_pwrite(obj, args); |
6a2c4232 | 1526 | } |
5c0480f2 | 1527 | |
fe115628 | 1528 | i915_gem_object_unpin_pages(obj); |
258a5ede | 1529 | err: |
f0cd5182 | 1530 | i915_gem_object_put(obj); |
258a5ede | 1531 | return ret; |
673a394b EA |
1532 | } |
1533 | ||
40e62d5d CW |
1534 | static void i915_gem_object_bump_inactive_ggtt(struct drm_i915_gem_object *obj) |
1535 | { | |
1536 | struct drm_i915_private *i915; | |
1537 | struct list_head *list; | |
1538 | struct i915_vma *vma; | |
1539 | ||
1540 | list_for_each_entry(vma, &obj->vma_list, obj_link) { | |
1541 | if (!i915_vma_is_ggtt(vma)) | |
28f412e0 | 1542 | break; |
40e62d5d CW |
1543 | |
1544 | if (i915_vma_is_active(vma)) | |
1545 | continue; | |
1546 | ||
1547 | if (!drm_mm_node_allocated(&vma->node)) | |
1548 | continue; | |
1549 | ||
1550 | list_move_tail(&vma->vm_link, &vma->vm->inactive_list); | |
1551 | } | |
1552 | ||
1553 | i915 = to_i915(obj->base.dev); | |
1554 | list = obj->bind_count ? &i915->mm.bound_list : &i915->mm.unbound_list; | |
56cea323 | 1555 | list_move_tail(&obj->global_link, list); |
40e62d5d CW |
1556 | } |
1557 | ||
673a394b | 1558 | /** |
2ef7eeaa EA |
1559 | * Called when user space prepares to use an object with the CPU, either |
1560 | * through the mmap ioctl's mapping or a GTT mapping. | |
14bb2c11 TU |
1561 | * @dev: drm device |
1562 | * @data: ioctl data blob | |
1563 | * @file: drm file | |
673a394b EA |
1564 | */ |
1565 | int | |
1566 | i915_gem_set_domain_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 1567 | struct drm_file *file) |
673a394b EA |
1568 | { |
1569 | struct drm_i915_gem_set_domain *args = data; | |
05394f39 | 1570 | struct drm_i915_gem_object *obj; |
2ef7eeaa EA |
1571 | uint32_t read_domains = args->read_domains; |
1572 | uint32_t write_domain = args->write_domain; | |
40e62d5d | 1573 | int err; |
673a394b | 1574 | |
2ef7eeaa | 1575 | /* Only handle setting domains to types used by the CPU. */ |
b8f9096d | 1576 | if ((write_domain | read_domains) & I915_GEM_GPU_DOMAINS) |
2ef7eeaa EA |
1577 | return -EINVAL; |
1578 | ||
1579 | /* Having something in the write domain implies it's in the read | |
1580 | * domain, and only that read domain. Enforce that in the request. | |
1581 | */ | |
1582 | if (write_domain != 0 && read_domains != write_domain) | |
1583 | return -EINVAL; | |
1584 | ||
03ac0642 | 1585 | obj = i915_gem_object_lookup(file, args->handle); |
b8f9096d CW |
1586 | if (!obj) |
1587 | return -ENOENT; | |
673a394b | 1588 | |
3236f57a CW |
1589 | /* Try to flush the object off the GPU without holding the lock. |
1590 | * We will repeat the flush holding the lock in the normal manner | |
1591 | * to catch cases where we are gazumped. | |
1592 | */ | |
40e62d5d | 1593 | err = i915_gem_object_wait(obj, |
e95433c7 CW |
1594 | I915_WAIT_INTERRUPTIBLE | |
1595 | (write_domain ? I915_WAIT_ALL : 0), | |
1596 | MAX_SCHEDULE_TIMEOUT, | |
1597 | to_rps_client(file)); | |
40e62d5d | 1598 | if (err) |
f0cd5182 | 1599 | goto out; |
b8f9096d | 1600 | |
40e62d5d CW |
1601 | /* Flush and acquire obj->pages so that we are coherent through |
1602 | * direct access in memory with previous cached writes through | |
1603 | * shmemfs and that our cache domain tracking remains valid. | |
1604 | * For example, if the obj->filp was moved to swap without us | |
1605 | * being notified and releasing the pages, we would mistakenly | |
1606 | * continue to assume that the obj remained out of the CPU cached | |
1607 | * domain. | |
1608 | */ | |
1609 | err = i915_gem_object_pin_pages(obj); | |
1610 | if (err) | |
f0cd5182 | 1611 | goto out; |
40e62d5d CW |
1612 | |
1613 | err = i915_mutex_lock_interruptible(dev); | |
1614 | if (err) | |
f0cd5182 | 1615 | goto out_unpin; |
3236f57a | 1616 | |
e22d8e3c CW |
1617 | if (read_domains & I915_GEM_DOMAIN_WC) |
1618 | err = i915_gem_object_set_to_wc_domain(obj, write_domain); | |
1619 | else if (read_domains & I915_GEM_DOMAIN_GTT) | |
1620 | err = i915_gem_object_set_to_gtt_domain(obj, write_domain); | |
43566ded | 1621 | else |
e22d8e3c | 1622 | err = i915_gem_object_set_to_cpu_domain(obj, write_domain); |
2ef7eeaa | 1623 | |
40e62d5d CW |
1624 | /* And bump the LRU for this access */ |
1625 | i915_gem_object_bump_inactive_ggtt(obj); | |
031b698a | 1626 | |
673a394b | 1627 | mutex_unlock(&dev->struct_mutex); |
b8f9096d | 1628 | |
40e62d5d | 1629 | if (write_domain != 0) |
ef74921b CW |
1630 | intel_fb_obj_invalidate(obj, |
1631 | fb_write_origin(obj, write_domain)); | |
40e62d5d | 1632 | |
f0cd5182 | 1633 | out_unpin: |
40e62d5d | 1634 | i915_gem_object_unpin_pages(obj); |
f0cd5182 CW |
1635 | out: |
1636 | i915_gem_object_put(obj); | |
40e62d5d | 1637 | return err; |
673a394b EA |
1638 | } |
1639 | ||
1640 | /** | |
1641 | * Called when user space has done writes to this buffer | |
14bb2c11 TU |
1642 | * @dev: drm device |
1643 | * @data: ioctl data blob | |
1644 | * @file: drm file | |
673a394b EA |
1645 | */ |
1646 | int | |
1647 | i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 1648 | struct drm_file *file) |
673a394b EA |
1649 | { |
1650 | struct drm_i915_gem_sw_finish *args = data; | |
05394f39 | 1651 | struct drm_i915_gem_object *obj; |
1d7cfea1 | 1652 | |
03ac0642 | 1653 | obj = i915_gem_object_lookup(file, args->handle); |
c21724cc CW |
1654 | if (!obj) |
1655 | return -ENOENT; | |
673a394b | 1656 | |
673a394b | 1657 | /* Pinned buffers may be scanout, so flush the cache */ |
5a97bcc6 | 1658 | i915_gem_object_flush_if_display(obj); |
f0cd5182 | 1659 | i915_gem_object_put(obj); |
5a97bcc6 CW |
1660 | |
1661 | return 0; | |
673a394b EA |
1662 | } |
1663 | ||
1664 | /** | |
14bb2c11 TU |
1665 | * i915_gem_mmap_ioctl - Maps the contents of an object, returning the address |
1666 | * it is mapped to. | |
1667 | * @dev: drm device | |
1668 | * @data: ioctl data blob | |
1669 | * @file: drm file | |
673a394b EA |
1670 | * |
1671 | * While the mapping holds a reference on the contents of the object, it doesn't | |
1672 | * imply a ref on the object itself. | |
34367381 DV |
1673 | * |
1674 | * IMPORTANT: | |
1675 | * | |
1676 | * DRM driver writers who look a this function as an example for how to do GEM | |
1677 | * mmap support, please don't implement mmap support like here. The modern way | |
1678 | * to implement DRM mmap support is with an mmap offset ioctl (like | |
1679 | * i915_gem_mmap_gtt) and then using the mmap syscall on the DRM fd directly. | |
1680 | * That way debug tooling like valgrind will understand what's going on, hiding | |
1681 | * the mmap call in a driver private ioctl will break that. The i915 driver only | |
1682 | * does cpu mmaps this way because we didn't know better. | |
673a394b EA |
1683 | */ |
1684 | int | |
1685 | i915_gem_mmap_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 1686 | struct drm_file *file) |
673a394b EA |
1687 | { |
1688 | struct drm_i915_gem_mmap *args = data; | |
03ac0642 | 1689 | struct drm_i915_gem_object *obj; |
673a394b EA |
1690 | unsigned long addr; |
1691 | ||
1816f923 AG |
1692 | if (args->flags & ~(I915_MMAP_WC)) |
1693 | return -EINVAL; | |
1694 | ||
568a58e5 | 1695 | if (args->flags & I915_MMAP_WC && !boot_cpu_has(X86_FEATURE_PAT)) |
1816f923 AG |
1696 | return -ENODEV; |
1697 | ||
03ac0642 CW |
1698 | obj = i915_gem_object_lookup(file, args->handle); |
1699 | if (!obj) | |
bf79cb91 | 1700 | return -ENOENT; |
673a394b | 1701 | |
1286ff73 DV |
1702 | /* prime objects have no backing filp to GEM mmap |
1703 | * pages from. | |
1704 | */ | |
03ac0642 | 1705 | if (!obj->base.filp) { |
f0cd5182 | 1706 | i915_gem_object_put(obj); |
1286ff73 DV |
1707 | return -EINVAL; |
1708 | } | |
1709 | ||
03ac0642 | 1710 | addr = vm_mmap(obj->base.filp, 0, args->size, |
673a394b EA |
1711 | PROT_READ | PROT_WRITE, MAP_SHARED, |
1712 | args->offset); | |
1816f923 AG |
1713 | if (args->flags & I915_MMAP_WC) { |
1714 | struct mm_struct *mm = current->mm; | |
1715 | struct vm_area_struct *vma; | |
1716 | ||
80a89a5e | 1717 | if (down_write_killable(&mm->mmap_sem)) { |
f0cd5182 | 1718 | i915_gem_object_put(obj); |
80a89a5e MH |
1719 | return -EINTR; |
1720 | } | |
1816f923 AG |
1721 | vma = find_vma(mm, addr); |
1722 | if (vma) | |
1723 | vma->vm_page_prot = | |
1724 | pgprot_writecombine(vm_get_page_prot(vma->vm_flags)); | |
1725 | else | |
1726 | addr = -ENOMEM; | |
1727 | up_write(&mm->mmap_sem); | |
aeecc969 CW |
1728 | |
1729 | /* This may race, but that's ok, it only gets set */ | |
50349247 | 1730 | WRITE_ONCE(obj->frontbuffer_ggtt_origin, ORIGIN_CPU); |
1816f923 | 1731 | } |
f0cd5182 | 1732 | i915_gem_object_put(obj); |
673a394b EA |
1733 | if (IS_ERR((void *)addr)) |
1734 | return addr; | |
1735 | ||
1736 | args->addr_ptr = (uint64_t) addr; | |
1737 | ||
1738 | return 0; | |
1739 | } | |
1740 | ||
03af84fe CW |
1741 | static unsigned int tile_row_pages(struct drm_i915_gem_object *obj) |
1742 | { | |
6649a0b6 | 1743 | return i915_gem_object_get_tile_row_size(obj) >> PAGE_SHIFT; |
03af84fe CW |
1744 | } |
1745 | ||
4cc69075 CW |
1746 | /** |
1747 | * i915_gem_mmap_gtt_version - report the current feature set for GTT mmaps | |
1748 | * | |
1749 | * A history of the GTT mmap interface: | |
1750 | * | |
1751 | * 0 - Everything had to fit into the GTT. Both parties of a memcpy had to | |
1752 | * aligned and suitable for fencing, and still fit into the available | |
1753 | * mappable space left by the pinned display objects. A classic problem | |
1754 | * we called the page-fault-of-doom where we would ping-pong between | |
1755 | * two objects that could not fit inside the GTT and so the memcpy | |
1756 | * would page one object in at the expense of the other between every | |
1757 | * single byte. | |
1758 | * | |
1759 | * 1 - Objects can be any size, and have any compatible fencing (X Y, or none | |
1760 | * as set via i915_gem_set_tiling() [DRM_I915_GEM_SET_TILING]). If the | |
1761 | * object is too large for the available space (or simply too large | |
1762 | * for the mappable aperture!), a view is created instead and faulted | |
1763 | * into userspace. (This view is aligned and sized appropriately for | |
1764 | * fenced access.) | |
1765 | * | |
e22d8e3c CW |
1766 | * 2 - Recognise WC as a separate cache domain so that we can flush the |
1767 | * delayed writes via GTT before performing direct access via WC. | |
1768 | * | |
4cc69075 CW |
1769 | * Restrictions: |
1770 | * | |
1771 | * * snoopable objects cannot be accessed via the GTT. It can cause machine | |
1772 | * hangs on some architectures, corruption on others. An attempt to service | |
1773 | * a GTT page fault from a snoopable object will generate a SIGBUS. | |
1774 | * | |
1775 | * * the object must be able to fit into RAM (physical memory, though no | |
1776 | * limited to the mappable aperture). | |
1777 | * | |
1778 | * | |
1779 | * Caveats: | |
1780 | * | |
1781 | * * a new GTT page fault will synchronize rendering from the GPU and flush | |
1782 | * all data to system memory. Subsequent access will not be synchronized. | |
1783 | * | |
1784 | * * all mappings are revoked on runtime device suspend. | |
1785 | * | |
1786 | * * there are only 8, 16 or 32 fence registers to share between all users | |
1787 | * (older machines require fence register for display and blitter access | |
1788 | * as well). Contention of the fence registers will cause the previous users | |
1789 | * to be unmapped and any new access will generate new page faults. | |
1790 | * | |
1791 | * * running out of memory while servicing a fault may generate a SIGBUS, | |
1792 | * rather than the expected SIGSEGV. | |
1793 | */ | |
1794 | int i915_gem_mmap_gtt_version(void) | |
1795 | { | |
e22d8e3c | 1796 | return 2; |
4cc69075 CW |
1797 | } |
1798 | ||
2d4281bb CW |
1799 | static inline struct i915_ggtt_view |
1800 | compute_partial_view(struct drm_i915_gem_object *obj, | |
2d4281bb CW |
1801 | pgoff_t page_offset, |
1802 | unsigned int chunk) | |
1803 | { | |
1804 | struct i915_ggtt_view view; | |
1805 | ||
1806 | if (i915_gem_object_is_tiled(obj)) | |
1807 | chunk = roundup(chunk, tile_row_pages(obj)); | |
1808 | ||
2d4281bb | 1809 | view.type = I915_GGTT_VIEW_PARTIAL; |
8bab1193 CW |
1810 | view.partial.offset = rounddown(page_offset, chunk); |
1811 | view.partial.size = | |
2d4281bb | 1812 | min_t(unsigned int, chunk, |
8bab1193 | 1813 | (obj->base.size >> PAGE_SHIFT) - view.partial.offset); |
2d4281bb CW |
1814 | |
1815 | /* If the partial covers the entire object, just create a normal VMA. */ | |
1816 | if (chunk >= obj->base.size >> PAGE_SHIFT) | |
1817 | view.type = I915_GGTT_VIEW_NORMAL; | |
1818 | ||
1819 | return view; | |
1820 | } | |
1821 | ||
de151cf6 JB |
1822 | /** |
1823 | * i915_gem_fault - fault a page into the GTT | |
d9072a3e | 1824 | * @vmf: fault info |
de151cf6 JB |
1825 | * |
1826 | * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped | |
1827 | * from userspace. The fault handler takes care of binding the object to | |
1828 | * the GTT (if needed), allocating and programming a fence register (again, | |
1829 | * only if needed based on whether the old reg is still valid or the object | |
1830 | * is tiled) and inserting a new PTE into the faulting process. | |
1831 | * | |
1832 | * Note that the faulting process may involve evicting existing objects | |
1833 | * from the GTT and/or fence registers to make room. So performance may | |
1834 | * suffer if the GTT working set is large or there are few fence registers | |
1835 | * left. | |
4cc69075 CW |
1836 | * |
1837 | * The current feature set supported by i915_gem_fault() and thus GTT mmaps | |
1838 | * is exposed via I915_PARAM_MMAP_GTT_VERSION (see i915_gem_mmap_gtt_version). | |
de151cf6 | 1839 | */ |
11bac800 | 1840 | int i915_gem_fault(struct vm_fault *vmf) |
de151cf6 | 1841 | { |
03af84fe | 1842 | #define MIN_CHUNK_PAGES ((1 << 20) >> PAGE_SHIFT) /* 1 MiB */ |
11bac800 | 1843 | struct vm_area_struct *area = vmf->vma; |
058d88c4 | 1844 | struct drm_i915_gem_object *obj = to_intel_bo(area->vm_private_data); |
05394f39 | 1845 | struct drm_device *dev = obj->base.dev; |
72e96d64 JL |
1846 | struct drm_i915_private *dev_priv = to_i915(dev); |
1847 | struct i915_ggtt *ggtt = &dev_priv->ggtt; | |
b8f9096d | 1848 | bool write = !!(vmf->flags & FAULT_FLAG_WRITE); |
058d88c4 | 1849 | struct i915_vma *vma; |
de151cf6 | 1850 | pgoff_t page_offset; |
82118877 | 1851 | unsigned int flags; |
b8f9096d | 1852 | int ret; |
f65c9168 | 1853 | |
de151cf6 | 1854 | /* We don't use vmf->pgoff since that has the fake offset */ |
1a29d85e | 1855 | page_offset = (vmf->address - area->vm_start) >> PAGE_SHIFT; |
de151cf6 | 1856 | |
db53a302 CW |
1857 | trace_i915_gem_object_fault(obj, page_offset, true, write); |
1858 | ||
6e4930f6 | 1859 | /* Try to flush the object off the GPU first without holding the lock. |
b8f9096d | 1860 | * Upon acquiring the lock, we will perform our sanity checks and then |
6e4930f6 CW |
1861 | * repeat the flush holding the lock in the normal manner to catch cases |
1862 | * where we are gazumped. | |
1863 | */ | |
e95433c7 CW |
1864 | ret = i915_gem_object_wait(obj, |
1865 | I915_WAIT_INTERRUPTIBLE, | |
1866 | MAX_SCHEDULE_TIMEOUT, | |
1867 | NULL); | |
6e4930f6 | 1868 | if (ret) |
b8f9096d CW |
1869 | goto err; |
1870 | ||
40e62d5d CW |
1871 | ret = i915_gem_object_pin_pages(obj); |
1872 | if (ret) | |
1873 | goto err; | |
1874 | ||
b8f9096d CW |
1875 | intel_runtime_pm_get(dev_priv); |
1876 | ||
1877 | ret = i915_mutex_lock_interruptible(dev); | |
1878 | if (ret) | |
1879 | goto err_rpm; | |
6e4930f6 | 1880 | |
eb119bd6 | 1881 | /* Access to snoopable pages through the GTT is incoherent. */ |
0031fb96 | 1882 | if (obj->cache_level != I915_CACHE_NONE && !HAS_LLC(dev_priv)) { |
ddeff6ee | 1883 | ret = -EFAULT; |
b8f9096d | 1884 | goto err_unlock; |
eb119bd6 CW |
1885 | } |
1886 | ||
82118877 CW |
1887 | /* If the object is smaller than a couple of partial vma, it is |
1888 | * not worth only creating a single partial vma - we may as well | |
1889 | * clear enough space for the full object. | |
1890 | */ | |
1891 | flags = PIN_MAPPABLE; | |
1892 | if (obj->base.size > 2 * MIN_CHUNK_PAGES << PAGE_SHIFT) | |
1893 | flags |= PIN_NONBLOCK | PIN_NONFAULT; | |
1894 | ||
a61007a8 | 1895 | /* Now pin it into the GTT as needed */ |
82118877 | 1896 | vma = i915_gem_object_ggtt_pin(obj, NULL, 0, 0, flags); |
a61007a8 | 1897 | if (IS_ERR(vma)) { |
a61007a8 | 1898 | /* Use a partial view if it is bigger than available space */ |
2d4281bb | 1899 | struct i915_ggtt_view view = |
8201c1fa | 1900 | compute_partial_view(obj, page_offset, MIN_CHUNK_PAGES); |
aa136d9d | 1901 | |
50349247 CW |
1902 | /* Userspace is now writing through an untracked VMA, abandon |
1903 | * all hope that the hardware is able to track future writes. | |
1904 | */ | |
1905 | obj->frontbuffer_ggtt_origin = ORIGIN_CPU; | |
1906 | ||
a61007a8 CW |
1907 | vma = i915_gem_object_ggtt_pin(obj, &view, 0, 0, PIN_MAPPABLE); |
1908 | } | |
058d88c4 CW |
1909 | if (IS_ERR(vma)) { |
1910 | ret = PTR_ERR(vma); | |
b8f9096d | 1911 | goto err_unlock; |
058d88c4 | 1912 | } |
4a684a41 | 1913 | |
c9839303 CW |
1914 | ret = i915_gem_object_set_to_gtt_domain(obj, write); |
1915 | if (ret) | |
b8f9096d | 1916 | goto err_unpin; |
74898d7e | 1917 | |
3bd40735 | 1918 | ret = i915_vma_pin_fence(vma); |
d9e86c0e | 1919 | if (ret) |
b8f9096d | 1920 | goto err_unpin; |
7d1c4804 | 1921 | |
b90b91d8 | 1922 | /* Finally, remap it using the new GTT offset */ |
c58305af | 1923 | ret = remap_io_mapping(area, |
8bab1193 | 1924 | area->vm_start + (vma->ggtt_view.partial.offset << PAGE_SHIFT), |
c58305af CW |
1925 | (ggtt->mappable_base + vma->node.start) >> PAGE_SHIFT, |
1926 | min_t(u64, vma->size, area->vm_end - area->vm_start), | |
1927 | &ggtt->mappable); | |
a65adaf8 CW |
1928 | if (ret) |
1929 | goto err_fence; | |
a61007a8 | 1930 | |
a65adaf8 CW |
1931 | /* Mark as being mmapped into userspace for later revocation */ |
1932 | assert_rpm_wakelock_held(dev_priv); | |
1933 | if (!i915_vma_set_userfault(vma) && !obj->userfault_count++) | |
1934 | list_add(&obj->userfault_link, &dev_priv->mm.userfault_list); | |
1935 | GEM_BUG_ON(!obj->userfault_count); | |
1936 | ||
1937 | err_fence: | |
3bd40735 | 1938 | i915_vma_unpin_fence(vma); |
b8f9096d | 1939 | err_unpin: |
058d88c4 | 1940 | __i915_vma_unpin(vma); |
b8f9096d | 1941 | err_unlock: |
de151cf6 | 1942 | mutex_unlock(&dev->struct_mutex); |
b8f9096d CW |
1943 | err_rpm: |
1944 | intel_runtime_pm_put(dev_priv); | |
40e62d5d | 1945 | i915_gem_object_unpin_pages(obj); |
b8f9096d | 1946 | err: |
de151cf6 | 1947 | switch (ret) { |
d9bc7e9f | 1948 | case -EIO: |
2232f031 DV |
1949 | /* |
1950 | * We eat errors when the gpu is terminally wedged to avoid | |
1951 | * userspace unduly crashing (gl has no provisions for mmaps to | |
1952 | * fail). But any other -EIO isn't ours (e.g. swap in failure) | |
1953 | * and so needs to be reported. | |
1954 | */ | |
1955 | if (!i915_terminally_wedged(&dev_priv->gpu_error)) { | |
f65c9168 PZ |
1956 | ret = VM_FAULT_SIGBUS; |
1957 | break; | |
1958 | } | |
045e769a | 1959 | case -EAGAIN: |
571c608d DV |
1960 | /* |
1961 | * EAGAIN means the gpu is hung and we'll wait for the error | |
1962 | * handler to reset everything when re-faulting in | |
1963 | * i915_mutex_lock_interruptible. | |
d9bc7e9f | 1964 | */ |
c715089f CW |
1965 | case 0: |
1966 | case -ERESTARTSYS: | |
bed636ab | 1967 | case -EINTR: |
e79e0fe3 DR |
1968 | case -EBUSY: |
1969 | /* | |
1970 | * EBUSY is ok: this just means that another thread | |
1971 | * already did the job. | |
1972 | */ | |
f65c9168 PZ |
1973 | ret = VM_FAULT_NOPAGE; |
1974 | break; | |
de151cf6 | 1975 | case -ENOMEM: |
f65c9168 PZ |
1976 | ret = VM_FAULT_OOM; |
1977 | break; | |
a7c2e1aa | 1978 | case -ENOSPC: |
45d67817 | 1979 | case -EFAULT: |
f65c9168 PZ |
1980 | ret = VM_FAULT_SIGBUS; |
1981 | break; | |
de151cf6 | 1982 | default: |
a7c2e1aa | 1983 | WARN_ONCE(ret, "unhandled error in i915_gem_fault: %i\n", ret); |
f65c9168 PZ |
1984 | ret = VM_FAULT_SIGBUS; |
1985 | break; | |
de151cf6 | 1986 | } |
f65c9168 | 1987 | return ret; |
de151cf6 JB |
1988 | } |
1989 | ||
a65adaf8 CW |
1990 | static void __i915_gem_object_release_mmap(struct drm_i915_gem_object *obj) |
1991 | { | |
1992 | struct i915_vma *vma; | |
1993 | ||
1994 | GEM_BUG_ON(!obj->userfault_count); | |
1995 | ||
1996 | obj->userfault_count = 0; | |
1997 | list_del(&obj->userfault_link); | |
1998 | drm_vma_node_unmap(&obj->base.vma_node, | |
1999 | obj->base.dev->anon_inode->i_mapping); | |
2000 | ||
2001 | list_for_each_entry(vma, &obj->vma_list, obj_link) { | |
2002 | if (!i915_vma_is_ggtt(vma)) | |
2003 | break; | |
2004 | ||
2005 | i915_vma_unset_userfault(vma); | |
2006 | } | |
2007 | } | |
2008 | ||
901782b2 CW |
2009 | /** |
2010 | * i915_gem_release_mmap - remove physical page mappings | |
2011 | * @obj: obj in question | |
2012 | * | |
af901ca1 | 2013 | * Preserve the reservation of the mmapping with the DRM core code, but |
901782b2 CW |
2014 | * relinquish ownership of the pages back to the system. |
2015 | * | |
2016 | * It is vital that we remove the page mapping if we have mapped a tiled | |
2017 | * object through the GTT and then lose the fence register due to | |
2018 | * resource pressure. Similarly if the object has been moved out of the | |
2019 | * aperture, than pages mapped into userspace must be revoked. Removing the | |
2020 | * mapping will then trigger a page fault on the next user access, allowing | |
2021 | * fixup by i915_gem_fault(). | |
2022 | */ | |
d05ca301 | 2023 | void |
05394f39 | 2024 | i915_gem_release_mmap(struct drm_i915_gem_object *obj) |
901782b2 | 2025 | { |
275f039d | 2026 | struct drm_i915_private *i915 = to_i915(obj->base.dev); |
275f039d | 2027 | |
349f2ccf CW |
2028 | /* Serialisation between user GTT access and our code depends upon |
2029 | * revoking the CPU's PTE whilst the mutex is held. The next user | |
2030 | * pagefault then has to wait until we release the mutex. | |
9c870d03 CW |
2031 | * |
2032 | * Note that RPM complicates somewhat by adding an additional | |
2033 | * requirement that operations to the GGTT be made holding the RPM | |
2034 | * wakeref. | |
349f2ccf | 2035 | */ |
275f039d | 2036 | lockdep_assert_held(&i915->drm.struct_mutex); |
9c870d03 | 2037 | intel_runtime_pm_get(i915); |
349f2ccf | 2038 | |
a65adaf8 | 2039 | if (!obj->userfault_count) |
9c870d03 | 2040 | goto out; |
901782b2 | 2041 | |
a65adaf8 | 2042 | __i915_gem_object_release_mmap(obj); |
349f2ccf CW |
2043 | |
2044 | /* Ensure that the CPU's PTE are revoked and there are not outstanding | |
2045 | * memory transactions from userspace before we return. The TLB | |
2046 | * flushing implied above by changing the PTE above *should* be | |
2047 | * sufficient, an extra barrier here just provides us with a bit | |
2048 | * of paranoid documentation about our requirement to serialise | |
2049 | * memory writes before touching registers / GSM. | |
2050 | */ | |
2051 | wmb(); | |
9c870d03 CW |
2052 | |
2053 | out: | |
2054 | intel_runtime_pm_put(i915); | |
901782b2 CW |
2055 | } |
2056 | ||
7c108fd8 | 2057 | void i915_gem_runtime_suspend(struct drm_i915_private *dev_priv) |
eedd10f4 | 2058 | { |
3594a3e2 | 2059 | struct drm_i915_gem_object *obj, *on; |
7c108fd8 | 2060 | int i; |
eedd10f4 | 2061 | |
3594a3e2 CW |
2062 | /* |
2063 | * Only called during RPM suspend. All users of the userfault_list | |
2064 | * must be holding an RPM wakeref to ensure that this can not | |
2065 | * run concurrently with themselves (and use the struct_mutex for | |
2066 | * protection between themselves). | |
2067 | */ | |
275f039d | 2068 | |
3594a3e2 | 2069 | list_for_each_entry_safe(obj, on, |
a65adaf8 CW |
2070 | &dev_priv->mm.userfault_list, userfault_link) |
2071 | __i915_gem_object_release_mmap(obj); | |
7c108fd8 CW |
2072 | |
2073 | /* The fence will be lost when the device powers down. If any were | |
2074 | * in use by hardware (i.e. they are pinned), we should not be powering | |
2075 | * down! All other fences will be reacquired by the user upon waking. | |
2076 | */ | |
2077 | for (i = 0; i < dev_priv->num_fence_regs; i++) { | |
2078 | struct drm_i915_fence_reg *reg = &dev_priv->fence_regs[i]; | |
2079 | ||
e0ec3ec6 CW |
2080 | /* Ideally we want to assert that the fence register is not |
2081 | * live at this point (i.e. that no piece of code will be | |
2082 | * trying to write through fence + GTT, as that both violates | |
2083 | * our tracking of activity and associated locking/barriers, | |
2084 | * but also is illegal given that the hw is powered down). | |
2085 | * | |
2086 | * Previously we used reg->pin_count as a "liveness" indicator. | |
2087 | * That is not sufficient, and we need a more fine-grained | |
2088 | * tool if we want to have a sanity check here. | |
2089 | */ | |
7c108fd8 CW |
2090 | |
2091 | if (!reg->vma) | |
2092 | continue; | |
2093 | ||
a65adaf8 | 2094 | GEM_BUG_ON(i915_vma_has_userfault(reg->vma)); |
7c108fd8 CW |
2095 | reg->dirty = true; |
2096 | } | |
eedd10f4 CW |
2097 | } |
2098 | ||
d8cb5086 CW |
2099 | static int i915_gem_object_create_mmap_offset(struct drm_i915_gem_object *obj) |
2100 | { | |
fac5e23e | 2101 | struct drm_i915_private *dev_priv = to_i915(obj->base.dev); |
f3f6184c | 2102 | int err; |
da494d7c | 2103 | |
f3f6184c | 2104 | err = drm_gem_create_mmap_offset(&obj->base); |
b42a13d9 | 2105 | if (likely(!err)) |
f3f6184c | 2106 | return 0; |
d8cb5086 | 2107 | |
b42a13d9 CW |
2108 | /* Attempt to reap some mmap space from dead objects */ |
2109 | do { | |
2110 | err = i915_gem_wait_for_idle(dev_priv, I915_WAIT_INTERRUPTIBLE); | |
2111 | if (err) | |
2112 | break; | |
f3f6184c | 2113 | |
b42a13d9 | 2114 | i915_gem_drain_freed_objects(dev_priv); |
f3f6184c | 2115 | err = drm_gem_create_mmap_offset(&obj->base); |
b42a13d9 CW |
2116 | if (!err) |
2117 | break; | |
2118 | ||
2119 | } while (flush_delayed_work(&dev_priv->gt.retire_work)); | |
da494d7c | 2120 | |
f3f6184c | 2121 | return err; |
d8cb5086 CW |
2122 | } |
2123 | ||
2124 | static void i915_gem_object_free_mmap_offset(struct drm_i915_gem_object *obj) | |
2125 | { | |
d8cb5086 CW |
2126 | drm_gem_free_mmap_offset(&obj->base); |
2127 | } | |
2128 | ||
da6b51d0 | 2129 | int |
ff72145b DA |
2130 | i915_gem_mmap_gtt(struct drm_file *file, |
2131 | struct drm_device *dev, | |
da6b51d0 | 2132 | uint32_t handle, |
ff72145b | 2133 | uint64_t *offset) |
de151cf6 | 2134 | { |
05394f39 | 2135 | struct drm_i915_gem_object *obj; |
de151cf6 JB |
2136 | int ret; |
2137 | ||
03ac0642 | 2138 | obj = i915_gem_object_lookup(file, handle); |
f3f6184c CW |
2139 | if (!obj) |
2140 | return -ENOENT; | |
ab18282d | 2141 | |
d8cb5086 | 2142 | ret = i915_gem_object_create_mmap_offset(obj); |
f3f6184c CW |
2143 | if (ret == 0) |
2144 | *offset = drm_vma_node_offset_addr(&obj->base.vma_node); | |
de151cf6 | 2145 | |
f0cd5182 | 2146 | i915_gem_object_put(obj); |
1d7cfea1 | 2147 | return ret; |
de151cf6 JB |
2148 | } |
2149 | ||
ff72145b DA |
2150 | /** |
2151 | * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing | |
2152 | * @dev: DRM device | |
2153 | * @data: GTT mapping ioctl data | |
2154 | * @file: GEM object info | |
2155 | * | |
2156 | * Simply returns the fake offset to userspace so it can mmap it. | |
2157 | * The mmap call will end up in drm_gem_mmap(), which will set things | |
2158 | * up so we can get faults in the handler above. | |
2159 | * | |
2160 | * The fault handler will take care of binding the object into the GTT | |
2161 | * (since it may have been evicted to make room for something), allocating | |
2162 | * a fence register, and mapping the appropriate aperture address into | |
2163 | * userspace. | |
2164 | */ | |
2165 | int | |
2166 | i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data, | |
2167 | struct drm_file *file) | |
2168 | { | |
2169 | struct drm_i915_gem_mmap_gtt *args = data; | |
2170 | ||
da6b51d0 | 2171 | return i915_gem_mmap_gtt(file, dev, args->handle, &args->offset); |
ff72145b DA |
2172 | } |
2173 | ||
225067ee DV |
2174 | /* Immediately discard the backing storage */ |
2175 | static void | |
2176 | i915_gem_object_truncate(struct drm_i915_gem_object *obj) | |
e5281ccd | 2177 | { |
4d6294bf | 2178 | i915_gem_object_free_mmap_offset(obj); |
1286ff73 | 2179 | |
4d6294bf CW |
2180 | if (obj->base.filp == NULL) |
2181 | return; | |
e5281ccd | 2182 | |
225067ee DV |
2183 | /* Our goal here is to return as much of the memory as |
2184 | * is possible back to the system as we are called from OOM. | |
2185 | * To do this we must instruct the shmfs to drop all of its | |
2186 | * backing pages, *now*. | |
2187 | */ | |
5537252b | 2188 | shmem_truncate_range(file_inode(obj->base.filp), 0, (loff_t)-1); |
a4f5ea64 | 2189 | obj->mm.madv = __I915_MADV_PURGED; |
4e5462ee | 2190 | obj->mm.pages = ERR_PTR(-EFAULT); |
225067ee | 2191 | } |
e5281ccd | 2192 | |
5537252b | 2193 | /* Try to discard unwanted pages */ |
03ac84f1 | 2194 | void __i915_gem_object_invalidate(struct drm_i915_gem_object *obj) |
225067ee | 2195 | { |
5537252b CW |
2196 | struct address_space *mapping; |
2197 | ||
1233e2db | 2198 | lockdep_assert_held(&obj->mm.lock); |
f1fa4f44 | 2199 | GEM_BUG_ON(i915_gem_object_has_pages(obj)); |
1233e2db | 2200 | |
a4f5ea64 | 2201 | switch (obj->mm.madv) { |
5537252b CW |
2202 | case I915_MADV_DONTNEED: |
2203 | i915_gem_object_truncate(obj); | |
2204 | case __I915_MADV_PURGED: | |
2205 | return; | |
2206 | } | |
2207 | ||
2208 | if (obj->base.filp == NULL) | |
2209 | return; | |
2210 | ||
93c76a3d | 2211 | mapping = obj->base.filp->f_mapping, |
5537252b | 2212 | invalidate_mapping_pages(mapping, 0, (loff_t)-1); |
e5281ccd CW |
2213 | } |
2214 | ||
5cdf5881 | 2215 | static void |
03ac84f1 CW |
2216 | i915_gem_object_put_pages_gtt(struct drm_i915_gem_object *obj, |
2217 | struct sg_table *pages) | |
673a394b | 2218 | { |
85d1225e DG |
2219 | struct sgt_iter sgt_iter; |
2220 | struct page *page; | |
1286ff73 | 2221 | |
e5facdf9 | 2222 | __i915_gem_object_release_shmem(obj, pages, true); |
673a394b | 2223 | |
03ac84f1 | 2224 | i915_gem_gtt_finish_pages(obj, pages); |
e2273302 | 2225 | |
6dacfd2f | 2226 | if (i915_gem_object_needs_bit17_swizzle(obj)) |
03ac84f1 | 2227 | i915_gem_object_save_bit_17_swizzle(obj, pages); |
280b713b | 2228 | |
03ac84f1 | 2229 | for_each_sgt_page(page, sgt_iter, pages) { |
a4f5ea64 | 2230 | if (obj->mm.dirty) |
9da3da66 | 2231 | set_page_dirty(page); |
3ef94daa | 2232 | |
a4f5ea64 | 2233 | if (obj->mm.madv == I915_MADV_WILLNEED) |
9da3da66 | 2234 | mark_page_accessed(page); |
3ef94daa | 2235 | |
09cbfeaf | 2236 | put_page(page); |
3ef94daa | 2237 | } |
a4f5ea64 | 2238 | obj->mm.dirty = false; |
673a394b | 2239 | |
03ac84f1 CW |
2240 | sg_free_table(pages); |
2241 | kfree(pages); | |
37e680a1 | 2242 | } |
6c085a72 | 2243 | |
96d77634 CW |
2244 | static void __i915_gem_object_reset_page_iter(struct drm_i915_gem_object *obj) |
2245 | { | |
2246 | struct radix_tree_iter iter; | |
c23aa71b | 2247 | void __rcu **slot; |
96d77634 | 2248 | |
a4f5ea64 CW |
2249 | radix_tree_for_each_slot(slot, &obj->mm.get_page.radix, &iter, 0) |
2250 | radix_tree_delete(&obj->mm.get_page.radix, iter.index); | |
96d77634 CW |
2251 | } |
2252 | ||
548625ee CW |
2253 | void __i915_gem_object_put_pages(struct drm_i915_gem_object *obj, |
2254 | enum i915_mm_subclass subclass) | |
37e680a1 | 2255 | { |
03ac84f1 | 2256 | struct sg_table *pages; |
37e680a1 | 2257 | |
a4f5ea64 | 2258 | if (i915_gem_object_has_pinned_pages(obj)) |
03ac84f1 | 2259 | return; |
a5570178 | 2260 | |
15717de2 | 2261 | GEM_BUG_ON(obj->bind_count); |
f1fa4f44 | 2262 | if (!i915_gem_object_has_pages(obj)) |
1233e2db CW |
2263 | return; |
2264 | ||
2265 | /* May be called by shrinker from within get_pages() (on another bo) */ | |
548625ee | 2266 | mutex_lock_nested(&obj->mm.lock, subclass); |
1233e2db CW |
2267 | if (unlikely(atomic_read(&obj->mm.pages_pin_count))) |
2268 | goto unlock; | |
3e123027 | 2269 | |
a2165e31 CW |
2270 | /* ->put_pages might need to allocate memory for the bit17 swizzle |
2271 | * array, hence protect them from being reaped by removing them from gtt | |
2272 | * lists early. */ | |
03ac84f1 CW |
2273 | pages = fetch_and_zero(&obj->mm.pages); |
2274 | GEM_BUG_ON(!pages); | |
a2165e31 | 2275 | |
a4f5ea64 | 2276 | if (obj->mm.mapping) { |
4b30cb23 CW |
2277 | void *ptr; |
2278 | ||
0ce81788 | 2279 | ptr = page_mask_bits(obj->mm.mapping); |
4b30cb23 CW |
2280 | if (is_vmalloc_addr(ptr)) |
2281 | vunmap(ptr); | |
fb8621d3 | 2282 | else |
4b30cb23 CW |
2283 | kunmap(kmap_to_page(ptr)); |
2284 | ||
a4f5ea64 | 2285 | obj->mm.mapping = NULL; |
0a798eb9 CW |
2286 | } |
2287 | ||
96d77634 CW |
2288 | __i915_gem_object_reset_page_iter(obj); |
2289 | ||
4e5462ee CW |
2290 | if (!IS_ERR(pages)) |
2291 | obj->ops->put_pages(obj, pages); | |
2292 | ||
a5c08166 MA |
2293 | obj->mm.page_sizes.phys = obj->mm.page_sizes.sg = 0; |
2294 | ||
1233e2db CW |
2295 | unlock: |
2296 | mutex_unlock(&obj->mm.lock); | |
6c085a72 CW |
2297 | } |
2298 | ||
935a2f77 | 2299 | static bool i915_sg_trim(struct sg_table *orig_st) |
0c40ce13 TU |
2300 | { |
2301 | struct sg_table new_st; | |
2302 | struct scatterlist *sg, *new_sg; | |
2303 | unsigned int i; | |
2304 | ||
2305 | if (orig_st->nents == orig_st->orig_nents) | |
935a2f77 | 2306 | return false; |
0c40ce13 | 2307 | |
8bfc478f | 2308 | if (sg_alloc_table(&new_st, orig_st->nents, GFP_KERNEL | __GFP_NOWARN)) |
935a2f77 | 2309 | return false; |
0c40ce13 TU |
2310 | |
2311 | new_sg = new_st.sgl; | |
2312 | for_each_sg(orig_st->sgl, sg, orig_st->nents, i) { | |
2313 | sg_set_page(new_sg, sg_page(sg), sg->length, 0); | |
2314 | /* called before being DMA mapped, no need to copy sg->dma_* */ | |
2315 | new_sg = sg_next(new_sg); | |
2316 | } | |
c2dc6cc9 | 2317 | GEM_BUG_ON(new_sg); /* Should walk exactly nents and hit the end */ |
0c40ce13 TU |
2318 | |
2319 | sg_free_table(orig_st); | |
2320 | ||
2321 | *orig_st = new_st; | |
935a2f77 | 2322 | return true; |
0c40ce13 TU |
2323 | } |
2324 | ||
b91b09ee | 2325 | static int i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj) |
e5281ccd | 2326 | { |
fac5e23e | 2327 | struct drm_i915_private *dev_priv = to_i915(obj->base.dev); |
d766ef53 CW |
2328 | const unsigned long page_count = obj->base.size / PAGE_SIZE; |
2329 | unsigned long i; | |
e5281ccd | 2330 | struct address_space *mapping; |
9da3da66 CW |
2331 | struct sg_table *st; |
2332 | struct scatterlist *sg; | |
85d1225e | 2333 | struct sgt_iter sgt_iter; |
e5281ccd | 2334 | struct page *page; |
90797e6d | 2335 | unsigned long last_pfn = 0; /* suppress gcc warning */ |
5602452e | 2336 | unsigned int max_segment = i915_sg_segment_size(); |
84e8978e | 2337 | unsigned int sg_page_sizes; |
4846bf0c | 2338 | gfp_t noreclaim; |
e2273302 | 2339 | int ret; |
e5281ccd | 2340 | |
6c085a72 CW |
2341 | /* Assert that the object is not currently in any GPU domain. As it |
2342 | * wasn't in the GTT, there shouldn't be any way it could have been in | |
2343 | * a GPU cache | |
2344 | */ | |
03ac84f1 CW |
2345 | GEM_BUG_ON(obj->base.read_domains & I915_GEM_GPU_DOMAINS); |
2346 | GEM_BUG_ON(obj->base.write_domain & I915_GEM_GPU_DOMAINS); | |
6c085a72 | 2347 | |
9da3da66 CW |
2348 | st = kmalloc(sizeof(*st), GFP_KERNEL); |
2349 | if (st == NULL) | |
b91b09ee | 2350 | return -ENOMEM; |
9da3da66 | 2351 | |
d766ef53 | 2352 | rebuild_st: |
9da3da66 | 2353 | if (sg_alloc_table(st, page_count, GFP_KERNEL)) { |
9da3da66 | 2354 | kfree(st); |
b91b09ee | 2355 | return -ENOMEM; |
9da3da66 | 2356 | } |
e5281ccd | 2357 | |
9da3da66 CW |
2358 | /* Get the list of pages out of our struct file. They'll be pinned |
2359 | * at this point until we release them. | |
2360 | * | |
2361 | * Fail silently without starting the shrinker | |
2362 | */ | |
93c76a3d | 2363 | mapping = obj->base.filp->f_mapping; |
0f6ab55d | 2364 | noreclaim = mapping_gfp_constraint(mapping, ~__GFP_RECLAIM); |
4846bf0c CW |
2365 | noreclaim |= __GFP_NORETRY | __GFP_NOWARN; |
2366 | ||
90797e6d ID |
2367 | sg = st->sgl; |
2368 | st->nents = 0; | |
84e8978e | 2369 | sg_page_sizes = 0; |
90797e6d | 2370 | for (i = 0; i < page_count; i++) { |
4846bf0c CW |
2371 | const unsigned int shrink[] = { |
2372 | I915_SHRINK_BOUND | I915_SHRINK_UNBOUND | I915_SHRINK_PURGEABLE, | |
2373 | 0, | |
2374 | }, *s = shrink; | |
2375 | gfp_t gfp = noreclaim; | |
2376 | ||
2377 | do { | |
6c085a72 | 2378 | page = shmem_read_mapping_page_gfp(mapping, i, gfp); |
4846bf0c CW |
2379 | if (likely(!IS_ERR(page))) |
2380 | break; | |
2381 | ||
2382 | if (!*s) { | |
2383 | ret = PTR_ERR(page); | |
2384 | goto err_sg; | |
2385 | } | |
2386 | ||
912d572d | 2387 | i915_gem_shrink(dev_priv, 2 * page_count, NULL, *s++); |
4846bf0c | 2388 | cond_resched(); |
24f8e00a | 2389 | |
6c085a72 CW |
2390 | /* We've tried hard to allocate the memory by reaping |
2391 | * our own buffer, now let the real VM do its job and | |
2392 | * go down in flames if truly OOM. | |
24f8e00a CW |
2393 | * |
2394 | * However, since graphics tend to be disposable, | |
2395 | * defer the oom here by reporting the ENOMEM back | |
2396 | * to userspace. | |
6c085a72 | 2397 | */ |
4846bf0c CW |
2398 | if (!*s) { |
2399 | /* reclaim and warn, but no oom */ | |
2400 | gfp = mapping_gfp_mask(mapping); | |
eaf41801 CW |
2401 | |
2402 | /* Our bo are always dirty and so we require | |
2403 | * kswapd to reclaim our pages (direct reclaim | |
2404 | * does not effectively begin pageout of our | |
2405 | * buffers on its own). However, direct reclaim | |
2406 | * only waits for kswapd when under allocation | |
2407 | * congestion. So as a result __GFP_RECLAIM is | |
2408 | * unreliable and fails to actually reclaim our | |
2409 | * dirty pages -- unless you try over and over | |
2410 | * again with !__GFP_NORETRY. However, we still | |
2411 | * want to fail this allocation rather than | |
2412 | * trigger the out-of-memory killer and for | |
dbb32956 | 2413 | * this we want __GFP_RETRY_MAYFAIL. |
eaf41801 | 2414 | */ |
dbb32956 | 2415 | gfp |= __GFP_RETRY_MAYFAIL; |
e2273302 | 2416 | } |
4846bf0c CW |
2417 | } while (1); |
2418 | ||
871dfbd6 CW |
2419 | if (!i || |
2420 | sg->length >= max_segment || | |
2421 | page_to_pfn(page) != last_pfn + 1) { | |
a5c08166 | 2422 | if (i) { |
84e8978e | 2423 | sg_page_sizes |= sg->length; |
90797e6d | 2424 | sg = sg_next(sg); |
a5c08166 | 2425 | } |
90797e6d ID |
2426 | st->nents++; |
2427 | sg_set_page(sg, page, PAGE_SIZE, 0); | |
2428 | } else { | |
2429 | sg->length += PAGE_SIZE; | |
2430 | } | |
2431 | last_pfn = page_to_pfn(page); | |
3bbbe706 DV |
2432 | |
2433 | /* Check that the i965g/gm workaround works. */ | |
2434 | WARN_ON((gfp & __GFP_DMA32) && (last_pfn >= 0x00100000UL)); | |
e5281ccd | 2435 | } |
a5c08166 | 2436 | if (sg) { /* loop terminated early; short sg table */ |
84e8978e | 2437 | sg_page_sizes |= sg->length; |
426729dc | 2438 | sg_mark_end(sg); |
a5c08166 | 2439 | } |
74ce6b6c | 2440 | |
0c40ce13 TU |
2441 | /* Trim unused sg entries to avoid wasting memory. */ |
2442 | i915_sg_trim(st); | |
2443 | ||
03ac84f1 | 2444 | ret = i915_gem_gtt_prepare_pages(obj, st); |
d766ef53 CW |
2445 | if (ret) { |
2446 | /* DMA remapping failed? One possible cause is that | |
2447 | * it could not reserve enough large entries, asking | |
2448 | * for PAGE_SIZE chunks instead may be helpful. | |
2449 | */ | |
2450 | if (max_segment > PAGE_SIZE) { | |
2451 | for_each_sgt_page(page, sgt_iter, st) | |
2452 | put_page(page); | |
2453 | sg_free_table(st); | |
2454 | ||
2455 | max_segment = PAGE_SIZE; | |
2456 | goto rebuild_st; | |
2457 | } else { | |
2458 | dev_warn(&dev_priv->drm.pdev->dev, | |
2459 | "Failed to DMA remap %lu pages\n", | |
2460 | page_count); | |
2461 | goto err_pages; | |
2462 | } | |
2463 | } | |
e2273302 | 2464 | |
6dacfd2f | 2465 | if (i915_gem_object_needs_bit17_swizzle(obj)) |
03ac84f1 | 2466 | i915_gem_object_do_bit_17_swizzle(obj, st); |
e5281ccd | 2467 | |
84e8978e | 2468 | __i915_gem_object_set_pages(obj, st, sg_page_sizes); |
b91b09ee MA |
2469 | |
2470 | return 0; | |
e5281ccd | 2471 | |
b17993b7 | 2472 | err_sg: |
90797e6d | 2473 | sg_mark_end(sg); |
b17993b7 | 2474 | err_pages: |
85d1225e DG |
2475 | for_each_sgt_page(page, sgt_iter, st) |
2476 | put_page(page); | |
9da3da66 CW |
2477 | sg_free_table(st); |
2478 | kfree(st); | |
0820baf3 CW |
2479 | |
2480 | /* shmemfs first checks if there is enough memory to allocate the page | |
2481 | * and reports ENOSPC should there be insufficient, along with the usual | |
2482 | * ENOMEM for a genuine allocation failure. | |
2483 | * | |
2484 | * We use ENOSPC in our driver to mean that we have run out of aperture | |
2485 | * space and so want to translate the error from shmemfs back to our | |
2486 | * usual understanding of ENOMEM. | |
2487 | */ | |
e2273302 ID |
2488 | if (ret == -ENOSPC) |
2489 | ret = -ENOMEM; | |
2490 | ||
b91b09ee | 2491 | return ret; |
03ac84f1 CW |
2492 | } |
2493 | ||
2494 | void __i915_gem_object_set_pages(struct drm_i915_gem_object *obj, | |
a5c08166 | 2495 | struct sg_table *pages, |
84e8978e | 2496 | unsigned int sg_page_sizes) |
03ac84f1 | 2497 | { |
a5c08166 MA |
2498 | struct drm_i915_private *i915 = to_i915(obj->base.dev); |
2499 | unsigned long supported = INTEL_INFO(i915)->page_sizes; | |
2500 | int i; | |
2501 | ||
1233e2db | 2502 | lockdep_assert_held(&obj->mm.lock); |
03ac84f1 CW |
2503 | |
2504 | obj->mm.get_page.sg_pos = pages->sgl; | |
2505 | obj->mm.get_page.sg_idx = 0; | |
2506 | ||
2507 | obj->mm.pages = pages; | |
2c3a3f44 CW |
2508 | |
2509 | if (i915_gem_object_is_tiled(obj) && | |
2510 | to_i915(obj->base.dev)->quirks & QUIRK_PIN_SWIZZLED_PAGES) { | |
2511 | GEM_BUG_ON(obj->mm.quirked); | |
2512 | __i915_gem_object_pin_pages(obj); | |
2513 | obj->mm.quirked = true; | |
2514 | } | |
a5c08166 | 2515 | |
84e8978e MA |
2516 | GEM_BUG_ON(!sg_page_sizes); |
2517 | obj->mm.page_sizes.phys = sg_page_sizes; | |
a5c08166 MA |
2518 | |
2519 | /* | |
84e8978e MA |
2520 | * Calculate the supported page-sizes which fit into the given |
2521 | * sg_page_sizes. This will give us the page-sizes which we may be able | |
2522 | * to use opportunistically when later inserting into the GTT. For | |
2523 | * example if phys=2G, then in theory we should be able to use 1G, 2M, | |
2524 | * 64K or 4K pages, although in practice this will depend on a number of | |
2525 | * other factors. | |
a5c08166 MA |
2526 | */ |
2527 | obj->mm.page_sizes.sg = 0; | |
2528 | for_each_set_bit(i, &supported, ilog2(I915_GTT_MAX_PAGE_SIZE) + 1) { | |
2529 | if (obj->mm.page_sizes.phys & ~0u << i) | |
2530 | obj->mm.page_sizes.sg |= BIT(i); | |
2531 | } | |
2532 | ||
2533 | GEM_BUG_ON(!HAS_PAGE_SIZES(i915, obj->mm.page_sizes.sg)); | |
03ac84f1 CW |
2534 | } |
2535 | ||
2536 | static int ____i915_gem_object_get_pages(struct drm_i915_gem_object *obj) | |
2537 | { | |
b91b09ee | 2538 | int err; |
03ac84f1 CW |
2539 | |
2540 | if (unlikely(obj->mm.madv != I915_MADV_WILLNEED)) { | |
2541 | DRM_DEBUG("Attempting to obtain a purgeable object\n"); | |
2542 | return -EFAULT; | |
2543 | } | |
2544 | ||
b91b09ee MA |
2545 | err = obj->ops->get_pages(obj); |
2546 | GEM_BUG_ON(!err && IS_ERR_OR_NULL(obj->mm.pages)); | |
03ac84f1 | 2547 | |
b91b09ee | 2548 | return err; |
673a394b EA |
2549 | } |
2550 | ||
37e680a1 | 2551 | /* Ensure that the associated pages are gathered from the backing storage |
1233e2db | 2552 | * and pinned into our object. i915_gem_object_pin_pages() may be called |
37e680a1 | 2553 | * multiple times before they are released by a single call to |
1233e2db | 2554 | * i915_gem_object_unpin_pages() - once the pages are no longer referenced |
37e680a1 CW |
2555 | * either as a result of memory pressure (reaping pages under the shrinker) |
2556 | * or as the object is itself released. | |
2557 | */ | |
a4f5ea64 | 2558 | int __i915_gem_object_get_pages(struct drm_i915_gem_object *obj) |
37e680a1 | 2559 | { |
03ac84f1 | 2560 | int err; |
37e680a1 | 2561 | |
1233e2db CW |
2562 | err = mutex_lock_interruptible(&obj->mm.lock); |
2563 | if (err) | |
2564 | return err; | |
4c7d62c6 | 2565 | |
f1fa4f44 | 2566 | if (unlikely(!i915_gem_object_has_pages(obj))) { |
88c880bb CW |
2567 | GEM_BUG_ON(i915_gem_object_has_pinned_pages(obj)); |
2568 | ||
2c3a3f44 CW |
2569 | err = ____i915_gem_object_get_pages(obj); |
2570 | if (err) | |
2571 | goto unlock; | |
37e680a1 | 2572 | |
2c3a3f44 CW |
2573 | smp_mb__before_atomic(); |
2574 | } | |
2575 | atomic_inc(&obj->mm.pages_pin_count); | |
ee286370 | 2576 | |
1233e2db CW |
2577 | unlock: |
2578 | mutex_unlock(&obj->mm.lock); | |
03ac84f1 | 2579 | return err; |
673a394b EA |
2580 | } |
2581 | ||
dd6034c6 | 2582 | /* The 'mapping' part of i915_gem_object_pin_map() below */ |
d31d7cb1 CW |
2583 | static void *i915_gem_object_map(const struct drm_i915_gem_object *obj, |
2584 | enum i915_map_type type) | |
dd6034c6 DG |
2585 | { |
2586 | unsigned long n_pages = obj->base.size >> PAGE_SHIFT; | |
a4f5ea64 | 2587 | struct sg_table *sgt = obj->mm.pages; |
85d1225e DG |
2588 | struct sgt_iter sgt_iter; |
2589 | struct page *page; | |
b338fa47 DG |
2590 | struct page *stack_pages[32]; |
2591 | struct page **pages = stack_pages; | |
dd6034c6 | 2592 | unsigned long i = 0; |
d31d7cb1 | 2593 | pgprot_t pgprot; |
dd6034c6 DG |
2594 | void *addr; |
2595 | ||
2596 | /* A single page can always be kmapped */ | |
d31d7cb1 | 2597 | if (n_pages == 1 && type == I915_MAP_WB) |
dd6034c6 DG |
2598 | return kmap(sg_page(sgt->sgl)); |
2599 | ||
b338fa47 DG |
2600 | if (n_pages > ARRAY_SIZE(stack_pages)) { |
2601 | /* Too big for stack -- allocate temporary array instead */ | |
0ee931c4 | 2602 | pages = kvmalloc_array(n_pages, sizeof(*pages), GFP_KERNEL); |
b338fa47 DG |
2603 | if (!pages) |
2604 | return NULL; | |
2605 | } | |
dd6034c6 | 2606 | |
85d1225e DG |
2607 | for_each_sgt_page(page, sgt_iter, sgt) |
2608 | pages[i++] = page; | |
dd6034c6 DG |
2609 | |
2610 | /* Check that we have the expected number of pages */ | |
2611 | GEM_BUG_ON(i != n_pages); | |
2612 | ||
d31d7cb1 | 2613 | switch (type) { |
a575c676 CW |
2614 | default: |
2615 | MISSING_CASE(type); | |
2616 | /* fallthrough to use PAGE_KERNEL anyway */ | |
d31d7cb1 CW |
2617 | case I915_MAP_WB: |
2618 | pgprot = PAGE_KERNEL; | |
2619 | break; | |
2620 | case I915_MAP_WC: | |
2621 | pgprot = pgprot_writecombine(PAGE_KERNEL_IO); | |
2622 | break; | |
2623 | } | |
2624 | addr = vmap(pages, n_pages, 0, pgprot); | |
dd6034c6 | 2625 | |
b338fa47 | 2626 | if (pages != stack_pages) |
2098105e | 2627 | kvfree(pages); |
dd6034c6 DG |
2628 | |
2629 | return addr; | |
2630 | } | |
2631 | ||
2632 | /* get, pin, and map the pages of the object into kernel space */ | |
d31d7cb1 CW |
2633 | void *i915_gem_object_pin_map(struct drm_i915_gem_object *obj, |
2634 | enum i915_map_type type) | |
0a798eb9 | 2635 | { |
d31d7cb1 CW |
2636 | enum i915_map_type has_type; |
2637 | bool pinned; | |
2638 | void *ptr; | |
0a798eb9 CW |
2639 | int ret; |
2640 | ||
d31d7cb1 | 2641 | GEM_BUG_ON(!i915_gem_object_has_struct_page(obj)); |
0a798eb9 | 2642 | |
1233e2db | 2643 | ret = mutex_lock_interruptible(&obj->mm.lock); |
0a798eb9 CW |
2644 | if (ret) |
2645 | return ERR_PTR(ret); | |
2646 | ||
a575c676 CW |
2647 | pinned = !(type & I915_MAP_OVERRIDE); |
2648 | type &= ~I915_MAP_OVERRIDE; | |
2649 | ||
1233e2db | 2650 | if (!atomic_inc_not_zero(&obj->mm.pages_pin_count)) { |
f1fa4f44 | 2651 | if (unlikely(!i915_gem_object_has_pages(obj))) { |
88c880bb CW |
2652 | GEM_BUG_ON(i915_gem_object_has_pinned_pages(obj)); |
2653 | ||
2c3a3f44 CW |
2654 | ret = ____i915_gem_object_get_pages(obj); |
2655 | if (ret) | |
2656 | goto err_unlock; | |
1233e2db | 2657 | |
2c3a3f44 CW |
2658 | smp_mb__before_atomic(); |
2659 | } | |
2660 | atomic_inc(&obj->mm.pages_pin_count); | |
1233e2db CW |
2661 | pinned = false; |
2662 | } | |
f1fa4f44 | 2663 | GEM_BUG_ON(!i915_gem_object_has_pages(obj)); |
0a798eb9 | 2664 | |
0ce81788 | 2665 | ptr = page_unpack_bits(obj->mm.mapping, &has_type); |
d31d7cb1 CW |
2666 | if (ptr && has_type != type) { |
2667 | if (pinned) { | |
2668 | ret = -EBUSY; | |
1233e2db | 2669 | goto err_unpin; |
0a798eb9 | 2670 | } |
d31d7cb1 CW |
2671 | |
2672 | if (is_vmalloc_addr(ptr)) | |
2673 | vunmap(ptr); | |
2674 | else | |
2675 | kunmap(kmap_to_page(ptr)); | |
2676 | ||
a4f5ea64 | 2677 | ptr = obj->mm.mapping = NULL; |
0a798eb9 CW |
2678 | } |
2679 | ||
d31d7cb1 CW |
2680 | if (!ptr) { |
2681 | ptr = i915_gem_object_map(obj, type); | |
2682 | if (!ptr) { | |
2683 | ret = -ENOMEM; | |
1233e2db | 2684 | goto err_unpin; |
d31d7cb1 CW |
2685 | } |
2686 | ||
0ce81788 | 2687 | obj->mm.mapping = page_pack_bits(ptr, type); |
d31d7cb1 CW |
2688 | } |
2689 | ||
1233e2db CW |
2690 | out_unlock: |
2691 | mutex_unlock(&obj->mm.lock); | |
d31d7cb1 CW |
2692 | return ptr; |
2693 | ||
1233e2db CW |
2694 | err_unpin: |
2695 | atomic_dec(&obj->mm.pages_pin_count); | |
2696 | err_unlock: | |
2697 | ptr = ERR_PTR(ret); | |
2698 | goto out_unlock; | |
0a798eb9 CW |
2699 | } |
2700 | ||
7c55e2c5 CW |
2701 | static int |
2702 | i915_gem_object_pwrite_gtt(struct drm_i915_gem_object *obj, | |
2703 | const struct drm_i915_gem_pwrite *arg) | |
2704 | { | |
2705 | struct address_space *mapping = obj->base.filp->f_mapping; | |
2706 | char __user *user_data = u64_to_user_ptr(arg->data_ptr); | |
2707 | u64 remain, offset; | |
2708 | unsigned int pg; | |
2709 | ||
2710 | /* Before we instantiate/pin the backing store for our use, we | |
2711 | * can prepopulate the shmemfs filp efficiently using a write into | |
2712 | * the pagecache. We avoid the penalty of instantiating all the | |
2713 | * pages, important if the user is just writing to a few and never | |
2714 | * uses the object on the GPU, and using a direct write into shmemfs | |
2715 | * allows it to avoid the cost of retrieving a page (either swapin | |
2716 | * or clearing-before-use) before it is overwritten. | |
2717 | */ | |
f1fa4f44 | 2718 | if (i915_gem_object_has_pages(obj)) |
7c55e2c5 CW |
2719 | return -ENODEV; |
2720 | ||
2721 | /* Before the pages are instantiated the object is treated as being | |
2722 | * in the CPU domain. The pages will be clflushed as required before | |
2723 | * use, and we can freely write into the pages directly. If userspace | |
2724 | * races pwrite with any other operation; corruption will ensue - | |
2725 | * that is userspace's prerogative! | |
2726 | */ | |
2727 | ||
2728 | remain = arg->size; | |
2729 | offset = arg->offset; | |
2730 | pg = offset_in_page(offset); | |
2731 | ||
2732 | do { | |
2733 | unsigned int len, unwritten; | |
2734 | struct page *page; | |
2735 | void *data, *vaddr; | |
2736 | int err; | |
2737 | ||
2738 | len = PAGE_SIZE - pg; | |
2739 | if (len > remain) | |
2740 | len = remain; | |
2741 | ||
2742 | err = pagecache_write_begin(obj->base.filp, mapping, | |
2743 | offset, len, 0, | |
2744 | &page, &data); | |
2745 | if (err < 0) | |
2746 | return err; | |
2747 | ||
2748 | vaddr = kmap(page); | |
2749 | unwritten = copy_from_user(vaddr + pg, user_data, len); | |
2750 | kunmap(page); | |
2751 | ||
2752 | err = pagecache_write_end(obj->base.filp, mapping, | |
2753 | offset, len, len - unwritten, | |
2754 | page, data); | |
2755 | if (err < 0) | |
2756 | return err; | |
2757 | ||
2758 | if (unwritten) | |
2759 | return -EFAULT; | |
2760 | ||
2761 | remain -= len; | |
2762 | user_data += len; | |
2763 | offset += len; | |
2764 | pg = 0; | |
2765 | } while (remain); | |
2766 | ||
2767 | return 0; | |
2768 | } | |
2769 | ||
77b25a97 CW |
2770 | static bool ban_context(const struct i915_gem_context *ctx, |
2771 | unsigned int score) | |
be62acb4 | 2772 | { |
6095868a | 2773 | return (i915_gem_context_is_bannable(ctx) && |
77b25a97 | 2774 | score >= CONTEXT_SCORE_BAN_THRESHOLD); |
be62acb4 MK |
2775 | } |
2776 | ||
e5e1fc47 | 2777 | static void i915_gem_context_mark_guilty(struct i915_gem_context *ctx) |
aa60c664 | 2778 | { |
77b25a97 CW |
2779 | unsigned int score; |
2780 | bool banned; | |
b083a087 | 2781 | |
77b25a97 | 2782 | atomic_inc(&ctx->guilty_count); |
b083a087 | 2783 | |
77b25a97 CW |
2784 | score = atomic_add_return(CONTEXT_SCORE_GUILTY, &ctx->ban_score); |
2785 | banned = ban_context(ctx, score); | |
2786 | DRM_DEBUG_DRIVER("context %s marked guilty (score %d) banned? %s\n", | |
2787 | ctx->name, score, yesno(banned)); | |
2788 | if (!banned) | |
b083a087 MK |
2789 | return; |
2790 | ||
77b25a97 CW |
2791 | i915_gem_context_set_banned(ctx); |
2792 | if (!IS_ERR_OR_NULL(ctx->file_priv)) { | |
2793 | atomic_inc(&ctx->file_priv->context_bans); | |
2794 | DRM_DEBUG_DRIVER("client %s has had %d context banned\n", | |
2795 | ctx->name, atomic_read(&ctx->file_priv->context_bans)); | |
2796 | } | |
e5e1fc47 MK |
2797 | } |
2798 | ||
2799 | static void i915_gem_context_mark_innocent(struct i915_gem_context *ctx) | |
2800 | { | |
77b25a97 | 2801 | atomic_inc(&ctx->active_count); |
aa60c664 MK |
2802 | } |
2803 | ||
8d9fc7fd | 2804 | struct drm_i915_gem_request * |
0bc40be8 | 2805 | i915_gem_find_active_request(struct intel_engine_cs *engine) |
9375e446 | 2806 | { |
754c9fd5 CW |
2807 | struct drm_i915_gem_request *request, *active = NULL; |
2808 | unsigned long flags; | |
4db080f9 | 2809 | |
f69a02c9 CW |
2810 | /* We are called by the error capture and reset at a random |
2811 | * point in time. In particular, note that neither is crucially | |
2812 | * ordered with an interrupt. After a hang, the GPU is dead and we | |
2813 | * assume that no more writes can happen (we waited long enough for | |
2814 | * all writes that were in transaction to be flushed) - adding an | |
2815 | * extra delay for a recent interrupt is pointless. Hence, we do | |
2816 | * not need an engine->irq_seqno_barrier() before the seqno reads. | |
2817 | */ | |
754c9fd5 | 2818 | spin_lock_irqsave(&engine->timeline->lock, flags); |
73cb9701 | 2819 | list_for_each_entry(request, &engine->timeline->requests, link) { |
754c9fd5 CW |
2820 | if (__i915_gem_request_completed(request, |
2821 | request->global_seqno)) | |
4db080f9 | 2822 | continue; |
aa60c664 | 2823 | |
36193acd | 2824 | GEM_BUG_ON(request->engine != engine); |
c00122f3 CW |
2825 | GEM_BUG_ON(test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, |
2826 | &request->fence.flags)); | |
754c9fd5 CW |
2827 | |
2828 | active = request; | |
2829 | break; | |
4db080f9 | 2830 | } |
754c9fd5 | 2831 | spin_unlock_irqrestore(&engine->timeline->lock, flags); |
b6b0fac0 | 2832 | |
754c9fd5 | 2833 | return active; |
b6b0fac0 MK |
2834 | } |
2835 | ||
bf2f0436 MK |
2836 | static bool engine_stalled(struct intel_engine_cs *engine) |
2837 | { | |
2838 | if (!engine->hangcheck.stalled) | |
2839 | return false; | |
2840 | ||
2841 | /* Check for possible seqno movement after hang declaration */ | |
2842 | if (engine->hangcheck.seqno != intel_engine_get_seqno(engine)) { | |
2843 | DRM_DEBUG_DRIVER("%s pardoned\n", engine->name); | |
2844 | return false; | |
2845 | } | |
2846 | ||
2847 | return true; | |
2848 | } | |
2849 | ||
a1ef70e1 MT |
2850 | /* |
2851 | * Ensure irq handler finishes, and not run again. | |
2852 | * Also return the active request so that we only search for it once. | |
2853 | */ | |
2854 | struct drm_i915_gem_request * | |
2855 | i915_gem_reset_prepare_engine(struct intel_engine_cs *engine) | |
2856 | { | |
2857 | struct drm_i915_gem_request *request = NULL; | |
2858 | ||
1749d90f CW |
2859 | /* |
2860 | * During the reset sequence, we must prevent the engine from | |
2861 | * entering RC6. As the context state is undefined until we restart | |
2862 | * the engine, if it does enter RC6 during the reset, the state | |
2863 | * written to the powercontext is undefined and so we may lose | |
2864 | * GPU state upon resume, i.e. fail to restart after a reset. | |
2865 | */ | |
2866 | intel_uncore_forcewake_get(engine->i915, FORCEWAKE_ALL); | |
2867 | ||
2868 | /* | |
2869 | * Prevent the signaler thread from updating the request | |
a1ef70e1 MT |
2870 | * state (by calling dma_fence_signal) as we are processing |
2871 | * the reset. The write from the GPU of the seqno is | |
2872 | * asynchronous and the signaler thread may see a different | |
2873 | * value to us and declare the request complete, even though | |
2874 | * the reset routine have picked that request as the active | |
2875 | * (incomplete) request. This conflict is not handled | |
2876 | * gracefully! | |
2877 | */ | |
2878 | kthread_park(engine->breadcrumbs.signaler); | |
2879 | ||
1749d90f CW |
2880 | /* |
2881 | * Prevent request submission to the hardware until we have | |
a1ef70e1 MT |
2882 | * completed the reset in i915_gem_reset_finish(). If a request |
2883 | * is completed by one engine, it may then queue a request | |
2884 | * to a second via its engine->irq_tasklet *just* as we are | |
2885 | * calling engine->init_hw() and also writing the ELSP. | |
2886 | * Turning off the engine->irq_tasklet until the reset is over | |
2887 | * prevents the race. | |
2888 | */ | |
b620e870 MK |
2889 | tasklet_kill(&engine->execlists.irq_tasklet); |
2890 | tasklet_disable(&engine->execlists.irq_tasklet); | |
a1ef70e1 MT |
2891 | |
2892 | if (engine->irq_seqno_barrier) | |
2893 | engine->irq_seqno_barrier(engine); | |
2894 | ||
d1d1ebf4 CW |
2895 | request = i915_gem_find_active_request(engine); |
2896 | if (request && request->fence.error == -EIO) | |
2897 | request = ERR_PTR(-EIO); /* Previous reset failed! */ | |
a1ef70e1 MT |
2898 | |
2899 | return request; | |
2900 | } | |
2901 | ||
0e178aef | 2902 | int i915_gem_reset_prepare(struct drm_i915_private *dev_priv) |
4c965543 CW |
2903 | { |
2904 | struct intel_engine_cs *engine; | |
a1ef70e1 | 2905 | struct drm_i915_gem_request *request; |
4c965543 | 2906 | enum intel_engine_id id; |
0e178aef | 2907 | int err = 0; |
4c965543 | 2908 | |
0e178aef | 2909 | for_each_engine(engine, dev_priv, id) { |
a1ef70e1 MT |
2910 | request = i915_gem_reset_prepare_engine(engine); |
2911 | if (IS_ERR(request)) { | |
2912 | err = PTR_ERR(request); | |
2913 | continue; | |
0e178aef | 2914 | } |
c64992e0 MT |
2915 | |
2916 | engine->hangcheck.active_request = request; | |
0e178aef CW |
2917 | } |
2918 | ||
4c965543 | 2919 | i915_gem_revoke_fences(dev_priv); |
0e178aef CW |
2920 | |
2921 | return err; | |
4c965543 CW |
2922 | } |
2923 | ||
36193acd | 2924 | static void skip_request(struct drm_i915_gem_request *request) |
821ed7df CW |
2925 | { |
2926 | void *vaddr = request->ring->vaddr; | |
2927 | u32 head; | |
2928 | ||
2929 | /* As this request likely depends on state from the lost | |
2930 | * context, clear out all the user operations leaving the | |
2931 | * breadcrumb at the end (so we get the fence notifications). | |
2932 | */ | |
2933 | head = request->head; | |
2934 | if (request->postfix < head) { | |
2935 | memset(vaddr + head, 0, request->ring->size - head); | |
2936 | head = 0; | |
2937 | } | |
2938 | memset(vaddr + head, 0, request->postfix - head); | |
c0d5f32c CW |
2939 | |
2940 | dma_fence_set_error(&request->fence, -EIO); | |
821ed7df CW |
2941 | } |
2942 | ||
36193acd MK |
2943 | static void engine_skip_context(struct drm_i915_gem_request *request) |
2944 | { | |
2945 | struct intel_engine_cs *engine = request->engine; | |
2946 | struct i915_gem_context *hung_ctx = request->ctx; | |
2947 | struct intel_timeline *timeline; | |
2948 | unsigned long flags; | |
2949 | ||
2950 | timeline = i915_gem_context_lookup_timeline(hung_ctx, engine); | |
2951 | ||
2952 | spin_lock_irqsave(&engine->timeline->lock, flags); | |
2953 | spin_lock(&timeline->lock); | |
2954 | ||
2955 | list_for_each_entry_continue(request, &engine->timeline->requests, link) | |
2956 | if (request->ctx == hung_ctx) | |
2957 | skip_request(request); | |
2958 | ||
2959 | list_for_each_entry(request, &timeline->requests, link) | |
2960 | skip_request(request); | |
2961 | ||
2962 | spin_unlock(&timeline->lock); | |
2963 | spin_unlock_irqrestore(&engine->timeline->lock, flags); | |
2964 | } | |
2965 | ||
d1d1ebf4 CW |
2966 | /* Returns the request if it was guilty of the hang */ |
2967 | static struct drm_i915_gem_request * | |
2968 | i915_gem_reset_request(struct intel_engine_cs *engine, | |
2969 | struct drm_i915_gem_request *request) | |
61da5362 | 2970 | { |
71895a08 MK |
2971 | /* The guilty request will get skipped on a hung engine. |
2972 | * | |
2973 | * Users of client default contexts do not rely on logical | |
2974 | * state preserved between batches so it is safe to execute | |
2975 | * queued requests following the hang. Non default contexts | |
2976 | * rely on preserved state, so skipping a batch loses the | |
2977 | * evolution of the state and it needs to be considered corrupted. | |
2978 | * Executing more queued batches on top of corrupted state is | |
2979 | * risky. But we take the risk by trying to advance through | |
2980 | * the queued requests in order to make the client behaviour | |
2981 | * more predictable around resets, by not throwing away random | |
2982 | * amount of batches it has prepared for execution. Sophisticated | |
2983 | * clients can use gem_reset_stats_ioctl and dma fence status | |
2984 | * (exported via sync_file info ioctl on explicit fences) to observe | |
2985 | * when it loses the context state and should rebuild accordingly. | |
2986 | * | |
2987 | * The context ban, and ultimately the client ban, mechanism are safety | |
2988 | * valves if client submission ends up resulting in nothing more than | |
2989 | * subsequent hangs. | |
2990 | */ | |
2991 | ||
d1d1ebf4 | 2992 | if (engine_stalled(engine)) { |
61da5362 MK |
2993 | i915_gem_context_mark_guilty(request->ctx); |
2994 | skip_request(request); | |
d1d1ebf4 CW |
2995 | |
2996 | /* If this context is now banned, skip all pending requests. */ | |
2997 | if (i915_gem_context_is_banned(request->ctx)) | |
2998 | engine_skip_context(request); | |
61da5362 | 2999 | } else { |
d1d1ebf4 CW |
3000 | /* |
3001 | * Since this is not the hung engine, it may have advanced | |
3002 | * since the hang declaration. Double check by refinding | |
3003 | * the active request at the time of the reset. | |
3004 | */ | |
3005 | request = i915_gem_find_active_request(engine); | |
3006 | if (request) { | |
3007 | i915_gem_context_mark_innocent(request->ctx); | |
3008 | dma_fence_set_error(&request->fence, -EAGAIN); | |
3009 | ||
3010 | /* Rewind the engine to replay the incomplete rq */ | |
3011 | spin_lock_irq(&engine->timeline->lock); | |
3012 | request = list_prev_entry(request, link); | |
3013 | if (&request->link == &engine->timeline->requests) | |
3014 | request = NULL; | |
3015 | spin_unlock_irq(&engine->timeline->lock); | |
3016 | } | |
61da5362 MK |
3017 | } |
3018 | ||
d1d1ebf4 | 3019 | return request; |
61da5362 MK |
3020 | } |
3021 | ||
a1ef70e1 MT |
3022 | void i915_gem_reset_engine(struct intel_engine_cs *engine, |
3023 | struct drm_i915_gem_request *request) | |
b6b0fac0 | 3024 | { |
ed454f2c CW |
3025 | engine->irq_posted = 0; |
3026 | ||
d1d1ebf4 CW |
3027 | if (request) |
3028 | request = i915_gem_reset_request(engine, request); | |
3029 | ||
3030 | if (request) { | |
c0dcb203 CW |
3031 | DRM_DEBUG_DRIVER("resetting %s to restart from tail of request 0x%x\n", |
3032 | engine->name, request->global_seqno); | |
c0dcb203 | 3033 | } |
821ed7df CW |
3034 | |
3035 | /* Setup the CS to resume from the breadcrumb of the hung request */ | |
3036 | engine->reset_hw(engine, request); | |
4db080f9 | 3037 | } |
aa60c664 | 3038 | |
d8027093 | 3039 | void i915_gem_reset(struct drm_i915_private *dev_priv) |
4db080f9 | 3040 | { |
821ed7df | 3041 | struct intel_engine_cs *engine; |
3b3f1650 | 3042 | enum intel_engine_id id; |
608c1a52 | 3043 | |
4c7d62c6 CW |
3044 | lockdep_assert_held(&dev_priv->drm.struct_mutex); |
3045 | ||
821ed7df CW |
3046 | i915_gem_retire_requests(dev_priv); |
3047 | ||
2ae55738 CW |
3048 | for_each_engine(engine, dev_priv, id) { |
3049 | struct i915_gem_context *ctx; | |
3050 | ||
c64992e0 | 3051 | i915_gem_reset_engine(engine, engine->hangcheck.active_request); |
2ae55738 CW |
3052 | ctx = fetch_and_zero(&engine->last_retired_context); |
3053 | if (ctx) | |
3054 | engine->context_unpin(engine, ctx); | |
3055 | } | |
821ed7df | 3056 | |
4362f4f6 | 3057 | i915_gem_restore_fences(dev_priv); |
f2a91d1a CW |
3058 | |
3059 | if (dev_priv->gt.awake) { | |
3060 | intel_sanitize_gt_powersave(dev_priv); | |
3061 | intel_enable_gt_powersave(dev_priv); | |
3062 | if (INTEL_GEN(dev_priv) >= 6) | |
3063 | gen6_rps_busy(dev_priv); | |
3064 | } | |
821ed7df CW |
3065 | } |
3066 | ||
a1ef70e1 MT |
3067 | void i915_gem_reset_finish_engine(struct intel_engine_cs *engine) |
3068 | { | |
b620e870 | 3069 | tasklet_enable(&engine->execlists.irq_tasklet); |
a1ef70e1 | 3070 | kthread_unpark(engine->breadcrumbs.signaler); |
1749d90f CW |
3071 | |
3072 | intel_uncore_forcewake_put(engine->i915, FORCEWAKE_ALL); | |
a1ef70e1 MT |
3073 | } |
3074 | ||
d8027093 CW |
3075 | void i915_gem_reset_finish(struct drm_i915_private *dev_priv) |
3076 | { | |
1f7b847d CW |
3077 | struct intel_engine_cs *engine; |
3078 | enum intel_engine_id id; | |
3079 | ||
d8027093 | 3080 | lockdep_assert_held(&dev_priv->drm.struct_mutex); |
1f7b847d | 3081 | |
fe3288b5 | 3082 | for_each_engine(engine, dev_priv, id) { |
c64992e0 | 3083 | engine->hangcheck.active_request = NULL; |
a1ef70e1 | 3084 | i915_gem_reset_finish_engine(engine); |
fe3288b5 | 3085 | } |
d8027093 CW |
3086 | } |
3087 | ||
821ed7df | 3088 | static void nop_submit_request(struct drm_i915_gem_request *request) |
af7a8ffa | 3089 | { |
af7a8ffa DV |
3090 | dma_fence_set_error(&request->fence, -EIO); |
3091 | ||
3092 | i915_gem_request_submit(request); | |
3093 | } | |
3094 | ||
3095 | static void nop_complete_submit_request(struct drm_i915_gem_request *request) | |
821ed7df | 3096 | { |
8d550824 CW |
3097 | unsigned long flags; |
3098 | ||
3cd9442f | 3099 | dma_fence_set_error(&request->fence, -EIO); |
8d550824 CW |
3100 | |
3101 | spin_lock_irqsave(&request->engine->timeline->lock, flags); | |
3102 | __i915_gem_request_submit(request); | |
3dcf93f7 | 3103 | intel_engine_init_global_seqno(request->engine, request->global_seqno); |
8d550824 | 3104 | spin_unlock_irqrestore(&request->engine->timeline->lock, flags); |
821ed7df CW |
3105 | } |
3106 | ||
af7a8ffa | 3107 | void i915_gem_set_wedged(struct drm_i915_private *i915) |
821ed7df | 3108 | { |
af7a8ffa DV |
3109 | struct intel_engine_cs *engine; |
3110 | enum intel_engine_id id; | |
3111 | ||
3112 | /* | |
3113 | * First, stop submission to hw, but do not yet complete requests by | |
3114 | * rolling the global seqno forward (since this would complete requests | |
3115 | * for which we haven't set the fence error to EIO yet). | |
3116 | */ | |
3117 | for_each_engine(engine, i915, id) | |
3118 | engine->submit_request = nop_submit_request; | |
3119 | ||
3120 | /* | |
3121 | * Make sure no one is running the old callback before we proceed with | |
3122 | * cancelling requests and resetting the completion tracking. Otherwise | |
3123 | * we might submit a request to the hardware which never completes. | |
20e4933c | 3124 | */ |
af7a8ffa | 3125 | synchronize_rcu(); |
70c2a24d | 3126 | |
af7a8ffa DV |
3127 | for_each_engine(engine, i915, id) { |
3128 | /* Mark all executing requests as skipped */ | |
3129 | engine->cancel_requests(engine); | |
5e32d748 | 3130 | |
af7a8ffa DV |
3131 | /* |
3132 | * Only once we've force-cancelled all in-flight requests can we | |
3133 | * start to complete all requests. | |
3134 | */ | |
3135 | engine->submit_request = nop_complete_submit_request; | |
3136 | } | |
3137 | ||
3138 | /* | |
3139 | * Make sure no request can slip through without getting completed by | |
3140 | * either this call here to intel_engine_init_global_seqno, or the one | |
3141 | * in nop_complete_submit_request. | |
5e32d748 | 3142 | */ |
af7a8ffa | 3143 | synchronize_rcu(); |
673a394b | 3144 | |
af7a8ffa DV |
3145 | for_each_engine(engine, i915, id) { |
3146 | unsigned long flags; | |
673a394b | 3147 | |
af7a8ffa DV |
3148 | /* Mark all pending requests as complete so that any concurrent |
3149 | * (lockless) lookup doesn't try and wait upon the request as we | |
3150 | * reset it. | |
3151 | */ | |
3152 | spin_lock_irqsave(&engine->timeline->lock, flags); | |
3153 | intel_engine_init_global_seqno(engine, | |
3154 | intel_engine_last_submit(engine)); | |
3155 | spin_unlock_irqrestore(&engine->timeline->lock, flags); | |
3156 | } | |
20e4933c | 3157 | |
3d7adbbf CW |
3158 | set_bit(I915_WEDGED, &i915->gpu_error.flags); |
3159 | wake_up_all(&i915->gpu_error.reset_queue); | |
673a394b EA |
3160 | } |
3161 | ||
2e8f9d32 CW |
3162 | bool i915_gem_unset_wedged(struct drm_i915_private *i915) |
3163 | { | |
3164 | struct i915_gem_timeline *tl; | |
3165 | int i; | |
3166 | ||
3167 | lockdep_assert_held(&i915->drm.struct_mutex); | |
3168 | if (!test_bit(I915_WEDGED, &i915->gpu_error.flags)) | |
3169 | return true; | |
3170 | ||
3171 | /* Before unwedging, make sure that all pending operations | |
3172 | * are flushed and errored out - we may have requests waiting upon | |
3173 | * third party fences. We marked all inflight requests as EIO, and | |
3174 | * every execbuf since returned EIO, for consistency we want all | |
3175 | * the currently pending requests to also be marked as EIO, which | |
3176 | * is done inside our nop_submit_request - and so we must wait. | |
3177 | * | |
3178 | * No more can be submitted until we reset the wedged bit. | |
3179 | */ | |
3180 | list_for_each_entry(tl, &i915->gt.timelines, link) { | |
3181 | for (i = 0; i < ARRAY_SIZE(tl->engine); i++) { | |
3182 | struct drm_i915_gem_request *rq; | |
3183 | ||
3184 | rq = i915_gem_active_peek(&tl->engine[i].last_request, | |
3185 | &i915->drm.struct_mutex); | |
3186 | if (!rq) | |
3187 | continue; | |
3188 | ||
3189 | /* We can't use our normal waiter as we want to | |
3190 | * avoid recursively trying to handle the current | |
3191 | * reset. The basic dma_fence_default_wait() installs | |
3192 | * a callback for dma_fence_signal(), which is | |
3193 | * triggered by our nop handler (indirectly, the | |
3194 | * callback enables the signaler thread which is | |
3195 | * woken by the nop_submit_request() advancing the seqno | |
3196 | * and when the seqno passes the fence, the signaler | |
3197 | * then signals the fence waking us up). | |
3198 | */ | |
3199 | if (dma_fence_default_wait(&rq->fence, true, | |
3200 | MAX_SCHEDULE_TIMEOUT) < 0) | |
3201 | return false; | |
3202 | } | |
3203 | } | |
3204 | ||
3205 | /* Undo nop_submit_request. We prevent all new i915 requests from | |
3206 | * being queued (by disallowing execbuf whilst wedged) so having | |
3207 | * waited for all active requests above, we know the system is idle | |
3208 | * and do not have to worry about a thread being inside | |
3209 | * engine->submit_request() as we swap over. So unlike installing | |
3210 | * the nop_submit_request on reset, we can do this from normal | |
3211 | * context and do not require stop_machine(). | |
3212 | */ | |
3213 | intel_engines_reset_default_submission(i915); | |
36703e79 | 3214 | i915_gem_contexts_lost(i915); |
2e8f9d32 CW |
3215 | |
3216 | smp_mb__before_atomic(); /* complete takeover before enabling execbuf */ | |
3217 | clear_bit(I915_WEDGED, &i915->gpu_error.flags); | |
3218 | ||
3219 | return true; | |
3220 | } | |
3221 | ||
75ef9da2 | 3222 | static void |
673a394b EA |
3223 | i915_gem_retire_work_handler(struct work_struct *work) |
3224 | { | |
b29c19b6 | 3225 | struct drm_i915_private *dev_priv = |
67d97da3 | 3226 | container_of(work, typeof(*dev_priv), gt.retire_work.work); |
91c8a326 | 3227 | struct drm_device *dev = &dev_priv->drm; |
673a394b | 3228 | |
891b48cf | 3229 | /* Come back later if the device is busy... */ |
b29c19b6 | 3230 | if (mutex_trylock(&dev->struct_mutex)) { |
67d97da3 | 3231 | i915_gem_retire_requests(dev_priv); |
b29c19b6 | 3232 | mutex_unlock(&dev->struct_mutex); |
673a394b | 3233 | } |
67d97da3 CW |
3234 | |
3235 | /* Keep the retire handler running until we are finally idle. | |
3236 | * We do not need to do this test under locking as in the worst-case | |
3237 | * we queue the retire worker once too often. | |
3238 | */ | |
c9615613 CW |
3239 | if (READ_ONCE(dev_priv->gt.awake)) { |
3240 | i915_queue_hangcheck(dev_priv); | |
67d97da3 CW |
3241 | queue_delayed_work(dev_priv->wq, |
3242 | &dev_priv->gt.retire_work, | |
bcb45086 | 3243 | round_jiffies_up_relative(HZ)); |
c9615613 | 3244 | } |
b29c19b6 | 3245 | } |
0a58705b | 3246 | |
b29c19b6 CW |
3247 | static void |
3248 | i915_gem_idle_work_handler(struct work_struct *work) | |
3249 | { | |
3250 | struct drm_i915_private *dev_priv = | |
67d97da3 | 3251 | container_of(work, typeof(*dev_priv), gt.idle_work.work); |
91c8a326 | 3252 | struct drm_device *dev = &dev_priv->drm; |
67d97da3 CW |
3253 | bool rearm_hangcheck; |
3254 | ||
3255 | if (!READ_ONCE(dev_priv->gt.awake)) | |
3256 | return; | |
3257 | ||
0cb5670b ID |
3258 | /* |
3259 | * Wait for last execlists context complete, but bail out in case a | |
3260 | * new request is submitted. | |
3261 | */ | |
8490ae20 | 3262 | wait_for(intel_engines_are_idle(dev_priv), 10); |
28176ef4 | 3263 | if (READ_ONCE(dev_priv->gt.active_requests)) |
67d97da3 CW |
3264 | return; |
3265 | ||
3266 | rearm_hangcheck = | |
3267 | cancel_delayed_work_sync(&dev_priv->gpu_error.hangcheck_work); | |
3268 | ||
3269 | if (!mutex_trylock(&dev->struct_mutex)) { | |
3270 | /* Currently busy, come back later */ | |
3271 | mod_delayed_work(dev_priv->wq, | |
3272 | &dev_priv->gt.idle_work, | |
3273 | msecs_to_jiffies(50)); | |
3274 | goto out_rearm; | |
3275 | } | |
3276 | ||
93c97dc1 ID |
3277 | /* |
3278 | * New request retired after this work handler started, extend active | |
3279 | * period until next instance of the work. | |
3280 | */ | |
3281 | if (work_pending(work)) | |
3282 | goto out_unlock; | |
3283 | ||
28176ef4 | 3284 | if (dev_priv->gt.active_requests) |
67d97da3 | 3285 | goto out_unlock; |
b29c19b6 | 3286 | |
05425249 | 3287 | if (wait_for(intel_engines_are_idle(dev_priv), 10)) |
0cb5670b ID |
3288 | DRM_ERROR("Timeout waiting for engines to idle\n"); |
3289 | ||
6c067579 | 3290 | intel_engines_mark_idle(dev_priv); |
47979480 | 3291 | i915_gem_timelines_mark_idle(dev_priv); |
35c94185 | 3292 | |
67d97da3 CW |
3293 | GEM_BUG_ON(!dev_priv->gt.awake); |
3294 | dev_priv->gt.awake = false; | |
3295 | rearm_hangcheck = false; | |
30ecad77 | 3296 | |
67d97da3 CW |
3297 | if (INTEL_GEN(dev_priv) >= 6) |
3298 | gen6_rps_idle(dev_priv); | |
3299 | intel_runtime_pm_put(dev_priv); | |
3300 | out_unlock: | |
3301 | mutex_unlock(&dev->struct_mutex); | |
b29c19b6 | 3302 | |
67d97da3 CW |
3303 | out_rearm: |
3304 | if (rearm_hangcheck) { | |
3305 | GEM_BUG_ON(!dev_priv->gt.awake); | |
3306 | i915_queue_hangcheck(dev_priv); | |
35c94185 | 3307 | } |
673a394b EA |
3308 | } |
3309 | ||
b1f788c6 CW |
3310 | void i915_gem_close_object(struct drm_gem_object *gem, struct drm_file *file) |
3311 | { | |
d1b48c1e | 3312 | struct drm_i915_private *i915 = to_i915(gem->dev); |
b1f788c6 CW |
3313 | struct drm_i915_gem_object *obj = to_intel_bo(gem); |
3314 | struct drm_i915_file_private *fpriv = file->driver_priv; | |
d1b48c1e | 3315 | struct i915_lut_handle *lut, *ln; |
b1f788c6 | 3316 | |
d1b48c1e CW |
3317 | mutex_lock(&i915->drm.struct_mutex); |
3318 | ||
3319 | list_for_each_entry_safe(lut, ln, &obj->lut_list, obj_link) { | |
3320 | struct i915_gem_context *ctx = lut->ctx; | |
3321 | struct i915_vma *vma; | |
3322 | ||
432295d7 | 3323 | GEM_BUG_ON(ctx->file_priv == ERR_PTR(-EBADF)); |
d1b48c1e CW |
3324 | if (ctx->file_priv != fpriv) |
3325 | continue; | |
3326 | ||
3327 | vma = radix_tree_delete(&ctx->handles_vma, lut->handle); | |
3ffff017 CW |
3328 | GEM_BUG_ON(vma->obj != obj); |
3329 | ||
3330 | /* We allow the process to have multiple handles to the same | |
3331 | * vma, in the same fd namespace, by virtue of flink/open. | |
3332 | */ | |
3333 | GEM_BUG_ON(!vma->open_count); | |
3334 | if (!--vma->open_count && !i915_vma_is_ggtt(vma)) | |
b1f788c6 | 3335 | i915_vma_close(vma); |
f8a7fde4 | 3336 | |
d1b48c1e CW |
3337 | list_del(&lut->obj_link); |
3338 | list_del(&lut->ctx_link); | |
4ff4b44c | 3339 | |
d1b48c1e CW |
3340 | kmem_cache_free(i915->luts, lut); |
3341 | __i915_gem_object_release_unless_active(obj); | |
f8a7fde4 | 3342 | } |
d1b48c1e CW |
3343 | |
3344 | mutex_unlock(&i915->drm.struct_mutex); | |
b1f788c6 CW |
3345 | } |
3346 | ||
e95433c7 CW |
3347 | static unsigned long to_wait_timeout(s64 timeout_ns) |
3348 | { | |
3349 | if (timeout_ns < 0) | |
3350 | return MAX_SCHEDULE_TIMEOUT; | |
3351 | ||
3352 | if (timeout_ns == 0) | |
3353 | return 0; | |
3354 | ||
3355 | return nsecs_to_jiffies_timeout(timeout_ns); | |
3356 | } | |
3357 | ||
23ba4fd0 BW |
3358 | /** |
3359 | * i915_gem_wait_ioctl - implements DRM_IOCTL_I915_GEM_WAIT | |
14bb2c11 TU |
3360 | * @dev: drm device pointer |
3361 | * @data: ioctl data blob | |
3362 | * @file: drm file pointer | |
23ba4fd0 BW |
3363 | * |
3364 | * Returns 0 if successful, else an error is returned with the remaining time in | |
3365 | * the timeout parameter. | |
3366 | * -ETIME: object is still busy after timeout | |
3367 | * -ERESTARTSYS: signal interrupted the wait | |
3368 | * -ENONENT: object doesn't exist | |
3369 | * Also possible, but rare: | |
b8050148 | 3370 | * -EAGAIN: incomplete, restart syscall |
23ba4fd0 BW |
3371 | * -ENOMEM: damn |
3372 | * -ENODEV: Internal IRQ fail | |
3373 | * -E?: The add request failed | |
3374 | * | |
3375 | * The wait ioctl with a timeout of 0 reimplements the busy ioctl. With any | |
3376 | * non-zero timeout parameter the wait ioctl will wait for the given number of | |
3377 | * nanoseconds on an object becoming unbusy. Since the wait itself does so | |
3378 | * without holding struct_mutex the object may become re-busied before this | |
3379 | * function completes. A similar but shorter * race condition exists in the busy | |
3380 | * ioctl | |
3381 | */ | |
3382 | int | |
3383 | i915_gem_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *file) | |
3384 | { | |
3385 | struct drm_i915_gem_wait *args = data; | |
3386 | struct drm_i915_gem_object *obj; | |
e95433c7 CW |
3387 | ktime_t start; |
3388 | long ret; | |
23ba4fd0 | 3389 | |
11b5d511 DV |
3390 | if (args->flags != 0) |
3391 | return -EINVAL; | |
3392 | ||
03ac0642 | 3393 | obj = i915_gem_object_lookup(file, args->bo_handle); |
033d549b | 3394 | if (!obj) |
23ba4fd0 | 3395 | return -ENOENT; |
23ba4fd0 | 3396 | |
e95433c7 CW |
3397 | start = ktime_get(); |
3398 | ||
3399 | ret = i915_gem_object_wait(obj, | |
3400 | I915_WAIT_INTERRUPTIBLE | I915_WAIT_ALL, | |
3401 | to_wait_timeout(args->timeout_ns), | |
3402 | to_rps_client(file)); | |
3403 | ||
3404 | if (args->timeout_ns > 0) { | |
3405 | args->timeout_ns -= ktime_to_ns(ktime_sub(ktime_get(), start)); | |
3406 | if (args->timeout_ns < 0) | |
3407 | args->timeout_ns = 0; | |
c1d2061b CW |
3408 | |
3409 | /* | |
3410 | * Apparently ktime isn't accurate enough and occasionally has a | |
3411 | * bit of mismatch in the jiffies<->nsecs<->ktime loop. So patch | |
3412 | * things up to make the test happy. We allow up to 1 jiffy. | |
3413 | * | |
3414 | * This is a regression from the timespec->ktime conversion. | |
3415 | */ | |
3416 | if (ret == -ETIME && !nsecs_to_jiffies(args->timeout_ns)) | |
3417 | args->timeout_ns = 0; | |
b8050148 CW |
3418 | |
3419 | /* Asked to wait beyond the jiffie/scheduler precision? */ | |
3420 | if (ret == -ETIME && args->timeout_ns) | |
3421 | ret = -EAGAIN; | |
b4716185 CW |
3422 | } |
3423 | ||
f0cd5182 | 3424 | i915_gem_object_put(obj); |
ff865885 | 3425 | return ret; |
23ba4fd0 BW |
3426 | } |
3427 | ||
73cb9701 | 3428 | static int wait_for_timeline(struct i915_gem_timeline *tl, unsigned int flags) |
4df2faf4 | 3429 | { |
73cb9701 | 3430 | int ret, i; |
4df2faf4 | 3431 | |
73cb9701 CW |
3432 | for (i = 0; i < ARRAY_SIZE(tl->engine); i++) { |
3433 | ret = i915_gem_active_wait(&tl->engine[i].last_request, flags); | |
3434 | if (ret) | |
3435 | return ret; | |
3436 | } | |
62e63007 | 3437 | |
73cb9701 CW |
3438 | return 0; |
3439 | } | |
3440 | ||
25112b64 CW |
3441 | static int wait_for_engines(struct drm_i915_private *i915) |
3442 | { | |
cad9946c CW |
3443 | if (wait_for(intel_engines_are_idle(i915), 50)) { |
3444 | DRM_ERROR("Failed to idle engines, declaring wedged!\n"); | |
3445 | i915_gem_set_wedged(i915); | |
3446 | return -EIO; | |
25112b64 CW |
3447 | } |
3448 | ||
3449 | return 0; | |
3450 | } | |
3451 | ||
73cb9701 CW |
3452 | int i915_gem_wait_for_idle(struct drm_i915_private *i915, unsigned int flags) |
3453 | { | |
73cb9701 CW |
3454 | int ret; |
3455 | ||
863e9fde CW |
3456 | /* If the device is asleep, we have no requests outstanding */ |
3457 | if (!READ_ONCE(i915->gt.awake)) | |
3458 | return 0; | |
3459 | ||
9caa34aa CW |
3460 | if (flags & I915_WAIT_LOCKED) { |
3461 | struct i915_gem_timeline *tl; | |
3462 | ||
3463 | lockdep_assert_held(&i915->drm.struct_mutex); | |
3464 | ||
3465 | list_for_each_entry(tl, &i915->gt.timelines, link) { | |
3466 | ret = wait_for_timeline(tl, flags); | |
3467 | if (ret) | |
3468 | return ret; | |
3469 | } | |
72022a70 CW |
3470 | |
3471 | i915_gem_retire_requests(i915); | |
3472 | GEM_BUG_ON(i915->gt.active_requests); | |
25112b64 CW |
3473 | |
3474 | ret = wait_for_engines(i915); | |
9caa34aa CW |
3475 | } else { |
3476 | ret = wait_for_timeline(&i915->gt.global_timeline, flags); | |
1ec14ad3 | 3477 | } |
4df2faf4 | 3478 | |
25112b64 | 3479 | return ret; |
4df2faf4 DV |
3480 | } |
3481 | ||
5a97bcc6 CW |
3482 | static void __i915_gem_object_flush_for_display(struct drm_i915_gem_object *obj) |
3483 | { | |
e27ab73d CW |
3484 | /* |
3485 | * We manually flush the CPU domain so that we can override and | |
3486 | * force the flush for the display, and perform it asyncrhonously. | |
3487 | */ | |
3488 | flush_write_domain(obj, ~I915_GEM_DOMAIN_CPU); | |
3489 | if (obj->cache_dirty) | |
3490 | i915_gem_clflush_object(obj, I915_CLFLUSH_FORCE); | |
5a97bcc6 CW |
3491 | obj->base.write_domain = 0; |
3492 | } | |
3493 | ||
3494 | void i915_gem_object_flush_if_display(struct drm_i915_gem_object *obj) | |
3495 | { | |
3496 | if (!READ_ONCE(obj->pin_display)) | |
3497 | return; | |
3498 | ||
3499 | mutex_lock(&obj->base.dev->struct_mutex); | |
3500 | __i915_gem_object_flush_for_display(obj); | |
3501 | mutex_unlock(&obj->base.dev->struct_mutex); | |
3502 | } | |
3503 | ||
e22d8e3c CW |
3504 | /** |
3505 | * Moves a single object to the WC read, and possibly write domain. | |
3506 | * @obj: object to act on | |
3507 | * @write: ask for write access or read only | |
3508 | * | |
3509 | * This function returns when the move is complete, including waiting on | |
3510 | * flushes to occur. | |
3511 | */ | |
3512 | int | |
3513 | i915_gem_object_set_to_wc_domain(struct drm_i915_gem_object *obj, bool write) | |
3514 | { | |
3515 | int ret; | |
3516 | ||
3517 | lockdep_assert_held(&obj->base.dev->struct_mutex); | |
3518 | ||
3519 | ret = i915_gem_object_wait(obj, | |
3520 | I915_WAIT_INTERRUPTIBLE | | |
3521 | I915_WAIT_LOCKED | | |
3522 | (write ? I915_WAIT_ALL : 0), | |
3523 | MAX_SCHEDULE_TIMEOUT, | |
3524 | NULL); | |
3525 | if (ret) | |
3526 | return ret; | |
3527 | ||
3528 | if (obj->base.write_domain == I915_GEM_DOMAIN_WC) | |
3529 | return 0; | |
3530 | ||
3531 | /* Flush and acquire obj->pages so that we are coherent through | |
3532 | * direct access in memory with previous cached writes through | |
3533 | * shmemfs and that our cache domain tracking remains valid. | |
3534 | * For example, if the obj->filp was moved to swap without us | |
3535 | * being notified and releasing the pages, we would mistakenly | |
3536 | * continue to assume that the obj remained out of the CPU cached | |
3537 | * domain. | |
3538 | */ | |
3539 | ret = i915_gem_object_pin_pages(obj); | |
3540 | if (ret) | |
3541 | return ret; | |
3542 | ||
3543 | flush_write_domain(obj, ~I915_GEM_DOMAIN_WC); | |
3544 | ||
3545 | /* Serialise direct access to this object with the barriers for | |
3546 | * coherent writes from the GPU, by effectively invalidating the | |
3547 | * WC domain upon first access. | |
3548 | */ | |
3549 | if ((obj->base.read_domains & I915_GEM_DOMAIN_WC) == 0) | |
3550 | mb(); | |
3551 | ||
3552 | /* It should now be out of any other write domains, and we can update | |
3553 | * the domain values for our changes. | |
3554 | */ | |
3555 | GEM_BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_WC) != 0); | |
3556 | obj->base.read_domains |= I915_GEM_DOMAIN_WC; | |
3557 | if (write) { | |
3558 | obj->base.read_domains = I915_GEM_DOMAIN_WC; | |
3559 | obj->base.write_domain = I915_GEM_DOMAIN_WC; | |
3560 | obj->mm.dirty = true; | |
3561 | } | |
3562 | ||
3563 | i915_gem_object_unpin_pages(obj); | |
3564 | return 0; | |
3565 | } | |
3566 | ||
2ef7eeaa EA |
3567 | /** |
3568 | * Moves a single object to the GTT read, and possibly write domain. | |
14bb2c11 TU |
3569 | * @obj: object to act on |
3570 | * @write: ask for write access or read only | |
2ef7eeaa EA |
3571 | * |
3572 | * This function returns when the move is complete, including waiting on | |
3573 | * flushes to occur. | |
3574 | */ | |
79e53945 | 3575 | int |
2021746e | 3576 | i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write) |
2ef7eeaa | 3577 | { |
e47c68e9 | 3578 | int ret; |
2ef7eeaa | 3579 | |
e95433c7 | 3580 | lockdep_assert_held(&obj->base.dev->struct_mutex); |
4c7d62c6 | 3581 | |
e95433c7 CW |
3582 | ret = i915_gem_object_wait(obj, |
3583 | I915_WAIT_INTERRUPTIBLE | | |
3584 | I915_WAIT_LOCKED | | |
3585 | (write ? I915_WAIT_ALL : 0), | |
3586 | MAX_SCHEDULE_TIMEOUT, | |
3587 | NULL); | |
88241785 CW |
3588 | if (ret) |
3589 | return ret; | |
3590 | ||
c13d87ea CW |
3591 | if (obj->base.write_domain == I915_GEM_DOMAIN_GTT) |
3592 | return 0; | |
3593 | ||
43566ded CW |
3594 | /* Flush and acquire obj->pages so that we are coherent through |
3595 | * direct access in memory with previous cached writes through | |
3596 | * shmemfs and that our cache domain tracking remains valid. | |
3597 | * For example, if the obj->filp was moved to swap without us | |
3598 | * being notified and releasing the pages, we would mistakenly | |
3599 | * continue to assume that the obj remained out of the CPU cached | |
3600 | * domain. | |
3601 | */ | |
a4f5ea64 | 3602 | ret = i915_gem_object_pin_pages(obj); |
43566ded CW |
3603 | if (ret) |
3604 | return ret; | |
3605 | ||
ef74921b | 3606 | flush_write_domain(obj, ~I915_GEM_DOMAIN_GTT); |
1c5d22f7 | 3607 | |
d0a57789 CW |
3608 | /* Serialise direct access to this object with the barriers for |
3609 | * coherent writes from the GPU, by effectively invalidating the | |
3610 | * GTT domain upon first access. | |
3611 | */ | |
3612 | if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0) | |
3613 | mb(); | |
3614 | ||
e47c68e9 EA |
3615 | /* It should now be out of any other write domains, and we can update |
3616 | * the domain values for our changes. | |
3617 | */ | |
40e62d5d | 3618 | GEM_BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) != 0); |
05394f39 | 3619 | obj->base.read_domains |= I915_GEM_DOMAIN_GTT; |
e47c68e9 | 3620 | if (write) { |
05394f39 CW |
3621 | obj->base.read_domains = I915_GEM_DOMAIN_GTT; |
3622 | obj->base.write_domain = I915_GEM_DOMAIN_GTT; | |
a4f5ea64 | 3623 | obj->mm.dirty = true; |
2ef7eeaa EA |
3624 | } |
3625 | ||
a4f5ea64 | 3626 | i915_gem_object_unpin_pages(obj); |
e47c68e9 EA |
3627 | return 0; |
3628 | } | |
3629 | ||
ef55f92a CW |
3630 | /** |
3631 | * Changes the cache-level of an object across all VMA. | |
14bb2c11 TU |
3632 | * @obj: object to act on |
3633 | * @cache_level: new cache level to set for the object | |
ef55f92a CW |
3634 | * |
3635 | * After this function returns, the object will be in the new cache-level | |
3636 | * across all GTT and the contents of the backing storage will be coherent, | |
3637 | * with respect to the new cache-level. In order to keep the backing storage | |
3638 | * coherent for all users, we only allow a single cache level to be set | |
3639 | * globally on the object and prevent it from being changed whilst the | |
3640 | * hardware is reading from the object. That is if the object is currently | |
3641 | * on the scanout it will be set to uncached (or equivalent display | |
3642 | * cache coherency) and all non-MOCS GPU access will also be uncached so | |
3643 | * that all direct access to the scanout remains coherent. | |
3644 | */ | |
e4ffd173 CW |
3645 | int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj, |
3646 | enum i915_cache_level cache_level) | |
3647 | { | |
aa653a68 | 3648 | struct i915_vma *vma; |
a6a7cc4b | 3649 | int ret; |
e4ffd173 | 3650 | |
4c7d62c6 CW |
3651 | lockdep_assert_held(&obj->base.dev->struct_mutex); |
3652 | ||
e4ffd173 | 3653 | if (obj->cache_level == cache_level) |
a6a7cc4b | 3654 | return 0; |
e4ffd173 | 3655 | |
ef55f92a CW |
3656 | /* Inspect the list of currently bound VMA and unbind any that would |
3657 | * be invalid given the new cache-level. This is principally to | |
3658 | * catch the issue of the CS prefetch crossing page boundaries and | |
3659 | * reading an invalid PTE on older architectures. | |
3660 | */ | |
aa653a68 CW |
3661 | restart: |
3662 | list_for_each_entry(vma, &obj->vma_list, obj_link) { | |
ef55f92a CW |
3663 | if (!drm_mm_node_allocated(&vma->node)) |
3664 | continue; | |
3665 | ||
20dfbde4 | 3666 | if (i915_vma_is_pinned(vma)) { |
ef55f92a CW |
3667 | DRM_DEBUG("can not change the cache level of pinned objects\n"); |
3668 | return -EBUSY; | |
3669 | } | |
3670 | ||
aa653a68 CW |
3671 | if (i915_gem_valid_gtt_space(vma, cache_level)) |
3672 | continue; | |
3673 | ||
3674 | ret = i915_vma_unbind(vma); | |
3675 | if (ret) | |
3676 | return ret; | |
3677 | ||
3678 | /* As unbinding may affect other elements in the | |
3679 | * obj->vma_list (due to side-effects from retiring | |
3680 | * an active vma), play safe and restart the iterator. | |
3681 | */ | |
3682 | goto restart; | |
42d6ab48 CW |
3683 | } |
3684 | ||
ef55f92a CW |
3685 | /* We can reuse the existing drm_mm nodes but need to change the |
3686 | * cache-level on the PTE. We could simply unbind them all and | |
3687 | * rebind with the correct cache-level on next use. However since | |
3688 | * we already have a valid slot, dma mapping, pages etc, we may as | |
3689 | * rewrite the PTE in the belief that doing so tramples upon less | |
3690 | * state and so involves less work. | |
3691 | */ | |
15717de2 | 3692 | if (obj->bind_count) { |
ef55f92a CW |
3693 | /* Before we change the PTE, the GPU must not be accessing it. |
3694 | * If we wait upon the object, we know that all the bound | |
3695 | * VMA are no longer active. | |
3696 | */ | |
e95433c7 CW |
3697 | ret = i915_gem_object_wait(obj, |
3698 | I915_WAIT_INTERRUPTIBLE | | |
3699 | I915_WAIT_LOCKED | | |
3700 | I915_WAIT_ALL, | |
3701 | MAX_SCHEDULE_TIMEOUT, | |
3702 | NULL); | |
e4ffd173 CW |
3703 | if (ret) |
3704 | return ret; | |
3705 | ||
0031fb96 TU |
3706 | if (!HAS_LLC(to_i915(obj->base.dev)) && |
3707 | cache_level != I915_CACHE_NONE) { | |
ef55f92a CW |
3708 | /* Access to snoopable pages through the GTT is |
3709 | * incoherent and on some machines causes a hard | |
3710 | * lockup. Relinquish the CPU mmaping to force | |
3711 | * userspace to refault in the pages and we can | |
3712 | * then double check if the GTT mapping is still | |
3713 | * valid for that pointer access. | |
3714 | */ | |
3715 | i915_gem_release_mmap(obj); | |
3716 | ||
3717 | /* As we no longer need a fence for GTT access, | |
3718 | * we can relinquish it now (and so prevent having | |
3719 | * to steal a fence from someone else on the next | |
3720 | * fence request). Note GPU activity would have | |
3721 | * dropped the fence as all snoopable access is | |
3722 | * supposed to be linear. | |
3723 | */ | |
49ef5294 CW |
3724 | list_for_each_entry(vma, &obj->vma_list, obj_link) { |
3725 | ret = i915_vma_put_fence(vma); | |
3726 | if (ret) | |
3727 | return ret; | |
3728 | } | |
ef55f92a CW |
3729 | } else { |
3730 | /* We either have incoherent backing store and | |
3731 | * so no GTT access or the architecture is fully | |
3732 | * coherent. In such cases, existing GTT mmaps | |
3733 | * ignore the cache bit in the PTE and we can | |
3734 | * rewrite it without confusing the GPU or having | |
3735 | * to force userspace to fault back in its mmaps. | |
3736 | */ | |
e4ffd173 CW |
3737 | } |
3738 | ||
1c7f4bca | 3739 | list_for_each_entry(vma, &obj->vma_list, obj_link) { |
ef55f92a CW |
3740 | if (!drm_mm_node_allocated(&vma->node)) |
3741 | continue; | |
3742 | ||
3743 | ret = i915_vma_bind(vma, cache_level, PIN_UPDATE); | |
3744 | if (ret) | |
3745 | return ret; | |
3746 | } | |
e4ffd173 CW |
3747 | } |
3748 | ||
1c7f4bca | 3749 | list_for_each_entry(vma, &obj->vma_list, obj_link) |
2c22569b | 3750 | vma->node.color = cache_level; |
b8f55be6 | 3751 | i915_gem_object_set_cache_coherency(obj, cache_level); |
e27ab73d | 3752 | obj->cache_dirty = true; /* Always invalidate stale cachelines */ |
2c22569b | 3753 | |
e4ffd173 CW |
3754 | return 0; |
3755 | } | |
3756 | ||
199adf40 BW |
3757 | int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data, |
3758 | struct drm_file *file) | |
e6994aee | 3759 | { |
199adf40 | 3760 | struct drm_i915_gem_caching *args = data; |
e6994aee | 3761 | struct drm_i915_gem_object *obj; |
fbbd37b3 | 3762 | int err = 0; |
e6994aee | 3763 | |
fbbd37b3 CW |
3764 | rcu_read_lock(); |
3765 | obj = i915_gem_object_lookup_rcu(file, args->handle); | |
3766 | if (!obj) { | |
3767 | err = -ENOENT; | |
3768 | goto out; | |
3769 | } | |
e6994aee | 3770 | |
651d794f CW |
3771 | switch (obj->cache_level) { |
3772 | case I915_CACHE_LLC: | |
3773 | case I915_CACHE_L3_LLC: | |
3774 | args->caching = I915_CACHING_CACHED; | |
3775 | break; | |
3776 | ||
4257d3ba CW |
3777 | case I915_CACHE_WT: |
3778 | args->caching = I915_CACHING_DISPLAY; | |
3779 | break; | |
3780 | ||
651d794f CW |
3781 | default: |
3782 | args->caching = I915_CACHING_NONE; | |
3783 | break; | |
3784 | } | |
fbbd37b3 CW |
3785 | out: |
3786 | rcu_read_unlock(); | |
3787 | return err; | |
e6994aee CW |
3788 | } |
3789 | ||
199adf40 BW |
3790 | int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data, |
3791 | struct drm_file *file) | |
e6994aee | 3792 | { |
9c870d03 | 3793 | struct drm_i915_private *i915 = to_i915(dev); |
199adf40 | 3794 | struct drm_i915_gem_caching *args = data; |
e6994aee CW |
3795 | struct drm_i915_gem_object *obj; |
3796 | enum i915_cache_level level; | |
d65415df | 3797 | int ret = 0; |
e6994aee | 3798 | |
199adf40 BW |
3799 | switch (args->caching) { |
3800 | case I915_CACHING_NONE: | |
e6994aee CW |
3801 | level = I915_CACHE_NONE; |
3802 | break; | |
199adf40 | 3803 | case I915_CACHING_CACHED: |
e5756c10 ID |
3804 | /* |
3805 | * Due to a HW issue on BXT A stepping, GPU stores via a | |
3806 | * snooped mapping may leave stale data in a corresponding CPU | |
3807 | * cacheline, whereas normally such cachelines would get | |
3808 | * invalidated. | |
3809 | */ | |
9c870d03 | 3810 | if (!HAS_LLC(i915) && !HAS_SNOOP(i915)) |
e5756c10 ID |
3811 | return -ENODEV; |
3812 | ||
e6994aee CW |
3813 | level = I915_CACHE_LLC; |
3814 | break; | |
4257d3ba | 3815 | case I915_CACHING_DISPLAY: |
9c870d03 | 3816 | level = HAS_WT(i915) ? I915_CACHE_WT : I915_CACHE_NONE; |
4257d3ba | 3817 | break; |
e6994aee CW |
3818 | default: |
3819 | return -EINVAL; | |
3820 | } | |
3821 | ||
d65415df CW |
3822 | obj = i915_gem_object_lookup(file, args->handle); |
3823 | if (!obj) | |
3824 | return -ENOENT; | |
3825 | ||
3826 | if (obj->cache_level == level) | |
3827 | goto out; | |
3828 | ||
3829 | ret = i915_gem_object_wait(obj, | |
3830 | I915_WAIT_INTERRUPTIBLE, | |
3831 | MAX_SCHEDULE_TIMEOUT, | |
3832 | to_rps_client(file)); | |
3bc2913e | 3833 | if (ret) |
d65415df | 3834 | goto out; |
3bc2913e | 3835 | |
d65415df CW |
3836 | ret = i915_mutex_lock_interruptible(dev); |
3837 | if (ret) | |
3838 | goto out; | |
e6994aee CW |
3839 | |
3840 | ret = i915_gem_object_set_cache_level(obj, level); | |
e6994aee | 3841 | mutex_unlock(&dev->struct_mutex); |
d65415df CW |
3842 | |
3843 | out: | |
3844 | i915_gem_object_put(obj); | |
e6994aee CW |
3845 | return ret; |
3846 | } | |
3847 | ||
b9241ea3 | 3848 | /* |
2da3b9b9 CW |
3849 | * Prepare buffer for display plane (scanout, cursors, etc). |
3850 | * Can be called from an uninterruptible phase (modesetting) and allows | |
3851 | * any flushes to be pipelined (for pageflips). | |
b9241ea3 | 3852 | */ |
058d88c4 | 3853 | struct i915_vma * |
2da3b9b9 CW |
3854 | i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj, |
3855 | u32 alignment, | |
e6617330 | 3856 | const struct i915_ggtt_view *view) |
b9241ea3 | 3857 | { |
058d88c4 | 3858 | struct i915_vma *vma; |
b9241ea3 ZW |
3859 | int ret; |
3860 | ||
4c7d62c6 CW |
3861 | lockdep_assert_held(&obj->base.dev->struct_mutex); |
3862 | ||
cc98b413 CW |
3863 | /* Mark the pin_display early so that we account for the |
3864 | * display coherency whilst setting up the cache domains. | |
3865 | */ | |
8a0c39b1 | 3866 | obj->pin_display++; |
cc98b413 | 3867 | |
a7ef0640 EA |
3868 | /* The display engine is not coherent with the LLC cache on gen6. As |
3869 | * a result, we make sure that the pinning that is about to occur is | |
3870 | * done with uncached PTEs. This is lowest common denominator for all | |
3871 | * chipsets. | |
3872 | * | |
3873 | * However for gen6+, we could do better by using the GFDT bit instead | |
3874 | * of uncaching, which would allow us to flush all the LLC-cached data | |
3875 | * with that bit in the PTE to main memory with just one PIPE_CONTROL. | |
3876 | */ | |
651d794f | 3877 | ret = i915_gem_object_set_cache_level(obj, |
8652744b TU |
3878 | HAS_WT(to_i915(obj->base.dev)) ? |
3879 | I915_CACHE_WT : I915_CACHE_NONE); | |
058d88c4 CW |
3880 | if (ret) { |
3881 | vma = ERR_PTR(ret); | |
cc98b413 | 3882 | goto err_unpin_display; |
058d88c4 | 3883 | } |
a7ef0640 | 3884 | |
2da3b9b9 CW |
3885 | /* As the user may map the buffer once pinned in the display plane |
3886 | * (e.g. libkms for the bootup splash), we have to ensure that we | |
2efb813d CW |
3887 | * always use map_and_fenceable for all scanout buffers. However, |
3888 | * it may simply be too big to fit into mappable, in which case | |
3889 | * put it anyway and hope that userspace can cope (but always first | |
3890 | * try to preserve the existing ABI). | |
2da3b9b9 | 3891 | */ |
2efb813d | 3892 | vma = ERR_PTR(-ENOSPC); |
47a8e3f6 | 3893 | if (!view || view->type == I915_GGTT_VIEW_NORMAL) |
2efb813d CW |
3894 | vma = i915_gem_object_ggtt_pin(obj, view, 0, alignment, |
3895 | PIN_MAPPABLE | PIN_NONBLOCK); | |
767a222e CW |
3896 | if (IS_ERR(vma)) { |
3897 | struct drm_i915_private *i915 = to_i915(obj->base.dev); | |
3898 | unsigned int flags; | |
3899 | ||
3900 | /* Valleyview is definitely limited to scanning out the first | |
3901 | * 512MiB. Lets presume this behaviour was inherited from the | |
3902 | * g4x display engine and that all earlier gen are similarly | |
3903 | * limited. Testing suggests that it is a little more | |
3904 | * complicated than this. For example, Cherryview appears quite | |
3905 | * happy to scanout from anywhere within its global aperture. | |
3906 | */ | |
3907 | flags = 0; | |
3908 | if (HAS_GMCH_DISPLAY(i915)) | |
3909 | flags = PIN_MAPPABLE; | |
3910 | vma = i915_gem_object_ggtt_pin(obj, view, 0, alignment, flags); | |
3911 | } | |
058d88c4 | 3912 | if (IS_ERR(vma)) |
cc98b413 | 3913 | goto err_unpin_display; |
2da3b9b9 | 3914 | |
d8923dcf CW |
3915 | vma->display_alignment = max_t(u64, vma->display_alignment, alignment); |
3916 | ||
a6a7cc4b | 3917 | /* Treat this as an end-of-frame, like intel_user_framebuffer_dirty() */ |
5a97bcc6 | 3918 | __i915_gem_object_flush_for_display(obj); |
d59b21ec | 3919 | intel_fb_obj_flush(obj, ORIGIN_DIRTYFB); |
b118c1e3 | 3920 | |
2da3b9b9 CW |
3921 | /* It should now be out of any other write domains, and we can update |
3922 | * the domain values for our changes. | |
3923 | */ | |
05394f39 | 3924 | obj->base.read_domains |= I915_GEM_DOMAIN_GTT; |
b9241ea3 | 3925 | |
058d88c4 | 3926 | return vma; |
cc98b413 CW |
3927 | |
3928 | err_unpin_display: | |
8a0c39b1 | 3929 | obj->pin_display--; |
058d88c4 | 3930 | return vma; |
cc98b413 CW |
3931 | } |
3932 | ||
3933 | void | |
058d88c4 | 3934 | i915_gem_object_unpin_from_display_plane(struct i915_vma *vma) |
cc98b413 | 3935 | { |
49d73912 | 3936 | lockdep_assert_held(&vma->vm->i915->drm.struct_mutex); |
4c7d62c6 | 3937 | |
058d88c4 | 3938 | if (WARN_ON(vma->obj->pin_display == 0)) |
8a0c39b1 TU |
3939 | return; |
3940 | ||
d8923dcf | 3941 | if (--vma->obj->pin_display == 0) |
f51455d4 | 3942 | vma->display_alignment = I915_GTT_MIN_ALIGNMENT; |
e6617330 | 3943 | |
383d5823 | 3944 | /* Bump the LRU to try and avoid premature eviction whilst flipping */ |
befedbb7 | 3945 | i915_gem_object_bump_inactive_ggtt(vma->obj); |
383d5823 | 3946 | |
058d88c4 | 3947 | i915_vma_unpin(vma); |
b9241ea3 ZW |
3948 | } |
3949 | ||
e47c68e9 EA |
3950 | /** |
3951 | * Moves a single object to the CPU read, and possibly write domain. | |
14bb2c11 TU |
3952 | * @obj: object to act on |
3953 | * @write: requesting write or read-only access | |
e47c68e9 EA |
3954 | * |
3955 | * This function returns when the move is complete, including waiting on | |
3956 | * flushes to occur. | |
3957 | */ | |
dabdfe02 | 3958 | int |
919926ae | 3959 | i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write) |
e47c68e9 | 3960 | { |
e47c68e9 EA |
3961 | int ret; |
3962 | ||
e95433c7 | 3963 | lockdep_assert_held(&obj->base.dev->struct_mutex); |
4c7d62c6 | 3964 | |
e95433c7 CW |
3965 | ret = i915_gem_object_wait(obj, |
3966 | I915_WAIT_INTERRUPTIBLE | | |
3967 | I915_WAIT_LOCKED | | |
3968 | (write ? I915_WAIT_ALL : 0), | |
3969 | MAX_SCHEDULE_TIMEOUT, | |
3970 | NULL); | |
88241785 CW |
3971 | if (ret) |
3972 | return ret; | |
3973 | ||
ef74921b | 3974 | flush_write_domain(obj, ~I915_GEM_DOMAIN_CPU); |
2ef7eeaa | 3975 | |
e47c68e9 | 3976 | /* Flush the CPU cache if it's still invalid. */ |
05394f39 | 3977 | if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) { |
57822dc6 | 3978 | i915_gem_clflush_object(obj, I915_CLFLUSH_SYNC); |
05394f39 | 3979 | obj->base.read_domains |= I915_GEM_DOMAIN_CPU; |
2ef7eeaa EA |
3980 | } |
3981 | ||
3982 | /* It should now be out of any other write domains, and we can update | |
3983 | * the domain values for our changes. | |
3984 | */ | |
e27ab73d | 3985 | GEM_BUG_ON(obj->base.write_domain & ~I915_GEM_DOMAIN_CPU); |
e47c68e9 EA |
3986 | |
3987 | /* If we're writing through the CPU, then the GPU read domains will | |
3988 | * need to be invalidated at next use. | |
3989 | */ | |
e27ab73d CW |
3990 | if (write) |
3991 | __start_cpu_write(obj); | |
2ef7eeaa EA |
3992 | |
3993 | return 0; | |
3994 | } | |
3995 | ||
673a394b EA |
3996 | /* Throttle our rendering by waiting until the ring has completed our requests |
3997 | * emitted over 20 msec ago. | |
3998 | * | |
b962442e EA |
3999 | * Note that if we were to use the current jiffies each time around the loop, |
4000 | * we wouldn't escape the function with any frames outstanding if the time to | |
4001 | * render a frame was over 20ms. | |
4002 | * | |
673a394b EA |
4003 | * This should get us reasonable parallelism between CPU and GPU but also |
4004 | * relatively low latency when blocking on a particular request to finish. | |
4005 | */ | |
40a5f0de | 4006 | static int |
f787a5f5 | 4007 | i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file) |
40a5f0de | 4008 | { |
fac5e23e | 4009 | struct drm_i915_private *dev_priv = to_i915(dev); |
f787a5f5 | 4010 | struct drm_i915_file_private *file_priv = file->driver_priv; |
d0bc54f2 | 4011 | unsigned long recent_enough = jiffies - DRM_I915_THROTTLE_JIFFIES; |
54fb2411 | 4012 | struct drm_i915_gem_request *request, *target = NULL; |
e95433c7 | 4013 | long ret; |
93533c29 | 4014 | |
f4457ae7 CW |
4015 | /* ABI: return -EIO if already wedged */ |
4016 | if (i915_terminally_wedged(&dev_priv->gpu_error)) | |
4017 | return -EIO; | |
e110e8d6 | 4018 | |
1c25595f | 4019 | spin_lock(&file_priv->mm.lock); |
c8659efa | 4020 | list_for_each_entry(request, &file_priv->mm.request_list, client_link) { |
b962442e EA |
4021 | if (time_after_eq(request->emitted_jiffies, recent_enough)) |
4022 | break; | |
40a5f0de | 4023 | |
c8659efa CW |
4024 | if (target) { |
4025 | list_del(&target->client_link); | |
4026 | target->file_priv = NULL; | |
4027 | } | |
fcfa423c | 4028 | |
54fb2411 | 4029 | target = request; |
b962442e | 4030 | } |
ff865885 | 4031 | if (target) |
e8a261ea | 4032 | i915_gem_request_get(target); |
1c25595f | 4033 | spin_unlock(&file_priv->mm.lock); |
40a5f0de | 4034 | |
54fb2411 | 4035 | if (target == NULL) |
f787a5f5 | 4036 | return 0; |
2bc43b5c | 4037 | |
e95433c7 CW |
4038 | ret = i915_wait_request(target, |
4039 | I915_WAIT_INTERRUPTIBLE, | |
4040 | MAX_SCHEDULE_TIMEOUT); | |
e8a261ea | 4041 | i915_gem_request_put(target); |
ff865885 | 4042 | |
e95433c7 | 4043 | return ret < 0 ? ret : 0; |
40a5f0de EA |
4044 | } |
4045 | ||
058d88c4 | 4046 | struct i915_vma * |
ec7adb6e JL |
4047 | i915_gem_object_ggtt_pin(struct drm_i915_gem_object *obj, |
4048 | const struct i915_ggtt_view *view, | |
91b2db6f | 4049 | u64 size, |
2ffffd0f CW |
4050 | u64 alignment, |
4051 | u64 flags) | |
ec7adb6e | 4052 | { |
ad16d2ed CW |
4053 | struct drm_i915_private *dev_priv = to_i915(obj->base.dev); |
4054 | struct i915_address_space *vm = &dev_priv->ggtt.base; | |
59bfa124 CW |
4055 | struct i915_vma *vma; |
4056 | int ret; | |
72e96d64 | 4057 | |
4c7d62c6 CW |
4058 | lockdep_assert_held(&obj->base.dev->struct_mutex); |
4059 | ||
43ae70d9 CW |
4060 | if (!view && flags & PIN_MAPPABLE) { |
4061 | /* If the required space is larger than the available | |
4062 | * aperture, we will not able to find a slot for the | |
4063 | * object and unbinding the object now will be in | |
4064 | * vain. Worse, doing so may cause us to ping-pong | |
4065 | * the object in and out of the Global GTT and | |
4066 | * waste a lot of cycles under the mutex. | |
4067 | */ | |
4068 | if (obj->base.size > dev_priv->ggtt.mappable_end) | |
4069 | return ERR_PTR(-E2BIG); | |
4070 | ||
4071 | /* If NONBLOCK is set the caller is optimistically | |
4072 | * trying to cache the full object within the mappable | |
4073 | * aperture, and *must* have a fallback in place for | |
4074 | * situations where we cannot bind the object. We | |
4075 | * can be a little more lax here and use the fallback | |
4076 | * more often to avoid costly migrations of ourselves | |
4077 | * and other objects within the aperture. | |
4078 | * | |
4079 | * Half-the-aperture is used as a simple heuristic. | |
4080 | * More interesting would to do search for a free | |
4081 | * block prior to making the commitment to unbind. | |
4082 | * That caters for the self-harm case, and with a | |
4083 | * little more heuristics (e.g. NOFAULT, NOEVICT) | |
4084 | * we could try to minimise harm to others. | |
4085 | */ | |
4086 | if (flags & PIN_NONBLOCK && | |
4087 | obj->base.size > dev_priv->ggtt.mappable_end / 2) | |
4088 | return ERR_PTR(-ENOSPC); | |
4089 | } | |
4090 | ||
718659a6 | 4091 | vma = i915_vma_instance(obj, vm, view); |
e0216b76 | 4092 | if (unlikely(IS_ERR(vma))) |
058d88c4 | 4093 | return vma; |
59bfa124 CW |
4094 | |
4095 | if (i915_vma_misplaced(vma, size, alignment, flags)) { | |
43ae70d9 CW |
4096 | if (flags & PIN_NONBLOCK) { |
4097 | if (i915_vma_is_pinned(vma) || i915_vma_is_active(vma)) | |
4098 | return ERR_PTR(-ENOSPC); | |
59bfa124 | 4099 | |
43ae70d9 | 4100 | if (flags & PIN_MAPPABLE && |
944397f0 | 4101 | vma->fence_size > dev_priv->ggtt.mappable_end / 2) |
ad16d2ed CW |
4102 | return ERR_PTR(-ENOSPC); |
4103 | } | |
4104 | ||
59bfa124 CW |
4105 | WARN(i915_vma_is_pinned(vma), |
4106 | "bo is already pinned in ggtt with incorrect alignment:" | |
05a20d09 CW |
4107 | " offset=%08x, req.alignment=%llx," |
4108 | " req.map_and_fenceable=%d, vma->map_and_fenceable=%d\n", | |
4109 | i915_ggtt_offset(vma), alignment, | |
59bfa124 | 4110 | !!(flags & PIN_MAPPABLE), |
05a20d09 | 4111 | i915_vma_is_map_and_fenceable(vma)); |
59bfa124 CW |
4112 | ret = i915_vma_unbind(vma); |
4113 | if (ret) | |
058d88c4 | 4114 | return ERR_PTR(ret); |
59bfa124 CW |
4115 | } |
4116 | ||
058d88c4 CW |
4117 | ret = i915_vma_pin(vma, size, alignment, flags | PIN_GLOBAL); |
4118 | if (ret) | |
4119 | return ERR_PTR(ret); | |
ec7adb6e | 4120 | |
058d88c4 | 4121 | return vma; |
673a394b EA |
4122 | } |
4123 | ||
edf6b76f | 4124 | static __always_inline unsigned int __busy_read_flag(unsigned int id) |
3fdc13c7 CW |
4125 | { |
4126 | /* Note that we could alias engines in the execbuf API, but | |
4127 | * that would be very unwise as it prevents userspace from | |
4128 | * fine control over engine selection. Ahem. | |
4129 | * | |
4130 | * This should be something like EXEC_MAX_ENGINE instead of | |
4131 | * I915_NUM_ENGINES. | |
4132 | */ | |
4133 | BUILD_BUG_ON(I915_NUM_ENGINES > 16); | |
4134 | return 0x10000 << id; | |
4135 | } | |
4136 | ||
4137 | static __always_inline unsigned int __busy_write_id(unsigned int id) | |
4138 | { | |
70cb472c CW |
4139 | /* The uABI guarantees an active writer is also amongst the read |
4140 | * engines. This would be true if we accessed the activity tracking | |
4141 | * under the lock, but as we perform the lookup of the object and | |
4142 | * its activity locklessly we can not guarantee that the last_write | |
4143 | * being active implies that we have set the same engine flag from | |
4144 | * last_read - hence we always set both read and write busy for | |
4145 | * last_write. | |
4146 | */ | |
4147 | return id | __busy_read_flag(id); | |
3fdc13c7 CW |
4148 | } |
4149 | ||
edf6b76f | 4150 | static __always_inline unsigned int |
d07f0e59 | 4151 | __busy_set_if_active(const struct dma_fence *fence, |
3fdc13c7 CW |
4152 | unsigned int (*flag)(unsigned int id)) |
4153 | { | |
d07f0e59 | 4154 | struct drm_i915_gem_request *rq; |
3fdc13c7 | 4155 | |
d07f0e59 CW |
4156 | /* We have to check the current hw status of the fence as the uABI |
4157 | * guarantees forward progress. We could rely on the idle worker | |
4158 | * to eventually flush us, but to minimise latency just ask the | |
4159 | * hardware. | |
1255501d | 4160 | * |
d07f0e59 | 4161 | * Note we only report on the status of native fences. |
1255501d | 4162 | */ |
d07f0e59 CW |
4163 | if (!dma_fence_is_i915(fence)) |
4164 | return 0; | |
4165 | ||
4166 | /* opencode to_request() in order to avoid const warnings */ | |
4167 | rq = container_of(fence, struct drm_i915_gem_request, fence); | |
4168 | if (i915_gem_request_completed(rq)) | |
4169 | return 0; | |
4170 | ||
1d39f281 | 4171 | return flag(rq->engine->uabi_id); |
3fdc13c7 CW |
4172 | } |
4173 | ||
edf6b76f | 4174 | static __always_inline unsigned int |
d07f0e59 | 4175 | busy_check_reader(const struct dma_fence *fence) |
3fdc13c7 | 4176 | { |
d07f0e59 | 4177 | return __busy_set_if_active(fence, __busy_read_flag); |
3fdc13c7 CW |
4178 | } |
4179 | ||
edf6b76f | 4180 | static __always_inline unsigned int |
d07f0e59 | 4181 | busy_check_writer(const struct dma_fence *fence) |
3fdc13c7 | 4182 | { |
d07f0e59 CW |
4183 | if (!fence) |
4184 | return 0; | |
4185 | ||
4186 | return __busy_set_if_active(fence, __busy_write_id); | |
3fdc13c7 CW |
4187 | } |
4188 | ||
673a394b EA |
4189 | int |
4190 | i915_gem_busy_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 4191 | struct drm_file *file) |
673a394b EA |
4192 | { |
4193 | struct drm_i915_gem_busy *args = data; | |
05394f39 | 4194 | struct drm_i915_gem_object *obj; |
d07f0e59 CW |
4195 | struct reservation_object_list *list; |
4196 | unsigned int seq; | |
fbbd37b3 | 4197 | int err; |
673a394b | 4198 | |
d07f0e59 | 4199 | err = -ENOENT; |
fbbd37b3 CW |
4200 | rcu_read_lock(); |
4201 | obj = i915_gem_object_lookup_rcu(file, args->handle); | |
d07f0e59 | 4202 | if (!obj) |
fbbd37b3 | 4203 | goto out; |
d1b851fc | 4204 | |
d07f0e59 CW |
4205 | /* A discrepancy here is that we do not report the status of |
4206 | * non-i915 fences, i.e. even though we may report the object as idle, | |
4207 | * a call to set-domain may still stall waiting for foreign rendering. | |
4208 | * This also means that wait-ioctl may report an object as busy, | |
4209 | * where busy-ioctl considers it idle. | |
4210 | * | |
4211 | * We trade the ability to warn of foreign fences to report on which | |
4212 | * i915 engines are active for the object. | |
4213 | * | |
4214 | * Alternatively, we can trade that extra information on read/write | |
4215 | * activity with | |
4216 | * args->busy = | |
4217 | * !reservation_object_test_signaled_rcu(obj->resv, true); | |
4218 | * to report the overall busyness. This is what the wait-ioctl does. | |
4219 | * | |
4220 | */ | |
4221 | retry: | |
4222 | seq = raw_read_seqcount(&obj->resv->seq); | |
426960be | 4223 | |
d07f0e59 CW |
4224 | /* Translate the exclusive fence to the READ *and* WRITE engine */ |
4225 | args->busy = busy_check_writer(rcu_dereference(obj->resv->fence_excl)); | |
3fdc13c7 | 4226 | |
d07f0e59 CW |
4227 | /* Translate shared fences to READ set of engines */ |
4228 | list = rcu_dereference(obj->resv->fence); | |
4229 | if (list) { | |
4230 | unsigned int shared_count = list->shared_count, i; | |
3fdc13c7 | 4231 | |
d07f0e59 CW |
4232 | for (i = 0; i < shared_count; ++i) { |
4233 | struct dma_fence *fence = | |
4234 | rcu_dereference(list->shared[i]); | |
4235 | ||
4236 | args->busy |= busy_check_reader(fence); | |
4237 | } | |
426960be | 4238 | } |
673a394b | 4239 | |
d07f0e59 CW |
4240 | if (args->busy && read_seqcount_retry(&obj->resv->seq, seq)) |
4241 | goto retry; | |
4242 | ||
4243 | err = 0; | |
fbbd37b3 CW |
4244 | out: |
4245 | rcu_read_unlock(); | |
4246 | return err; | |
673a394b EA |
4247 | } |
4248 | ||
4249 | int | |
4250 | i915_gem_throttle_ioctl(struct drm_device *dev, void *data, | |
4251 | struct drm_file *file_priv) | |
4252 | { | |
0206e353 | 4253 | return i915_gem_ring_throttle(dev, file_priv); |
673a394b EA |
4254 | } |
4255 | ||
3ef94daa CW |
4256 | int |
4257 | i915_gem_madvise_ioctl(struct drm_device *dev, void *data, | |
4258 | struct drm_file *file_priv) | |
4259 | { | |
fac5e23e | 4260 | struct drm_i915_private *dev_priv = to_i915(dev); |
3ef94daa | 4261 | struct drm_i915_gem_madvise *args = data; |
05394f39 | 4262 | struct drm_i915_gem_object *obj; |
1233e2db | 4263 | int err; |
3ef94daa CW |
4264 | |
4265 | switch (args->madv) { | |
4266 | case I915_MADV_DONTNEED: | |
4267 | case I915_MADV_WILLNEED: | |
4268 | break; | |
4269 | default: | |
4270 | return -EINVAL; | |
4271 | } | |
4272 | ||
03ac0642 | 4273 | obj = i915_gem_object_lookup(file_priv, args->handle); |
1233e2db CW |
4274 | if (!obj) |
4275 | return -ENOENT; | |
4276 | ||
4277 | err = mutex_lock_interruptible(&obj->mm.lock); | |
4278 | if (err) | |
4279 | goto out; | |
3ef94daa | 4280 | |
f1fa4f44 | 4281 | if (i915_gem_object_has_pages(obj) && |
3e510a8e | 4282 | i915_gem_object_is_tiled(obj) && |
656bfa3a | 4283 | dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES) { |
bc0629a7 CW |
4284 | if (obj->mm.madv == I915_MADV_WILLNEED) { |
4285 | GEM_BUG_ON(!obj->mm.quirked); | |
a4f5ea64 | 4286 | __i915_gem_object_unpin_pages(obj); |
bc0629a7 CW |
4287 | obj->mm.quirked = false; |
4288 | } | |
4289 | if (args->madv == I915_MADV_WILLNEED) { | |
2c3a3f44 | 4290 | GEM_BUG_ON(obj->mm.quirked); |
a4f5ea64 | 4291 | __i915_gem_object_pin_pages(obj); |
bc0629a7 CW |
4292 | obj->mm.quirked = true; |
4293 | } | |
656bfa3a DV |
4294 | } |
4295 | ||
a4f5ea64 CW |
4296 | if (obj->mm.madv != __I915_MADV_PURGED) |
4297 | obj->mm.madv = args->madv; | |
3ef94daa | 4298 | |
6c085a72 | 4299 | /* if the object is no longer attached, discard its backing storage */ |
f1fa4f44 CW |
4300 | if (obj->mm.madv == I915_MADV_DONTNEED && |
4301 | !i915_gem_object_has_pages(obj)) | |
2d7ef395 CW |
4302 | i915_gem_object_truncate(obj); |
4303 | ||
a4f5ea64 | 4304 | args->retained = obj->mm.madv != __I915_MADV_PURGED; |
1233e2db | 4305 | mutex_unlock(&obj->mm.lock); |
bb6baf76 | 4306 | |
1233e2db | 4307 | out: |
f8c417cd | 4308 | i915_gem_object_put(obj); |
1233e2db | 4309 | return err; |
3ef94daa CW |
4310 | } |
4311 | ||
5b8c8aec CW |
4312 | static void |
4313 | frontbuffer_retire(struct i915_gem_active *active, | |
4314 | struct drm_i915_gem_request *request) | |
4315 | { | |
4316 | struct drm_i915_gem_object *obj = | |
4317 | container_of(active, typeof(*obj), frontbuffer_write); | |
4318 | ||
d59b21ec | 4319 | intel_fb_obj_flush(obj, ORIGIN_CS); |
5b8c8aec CW |
4320 | } |
4321 | ||
37e680a1 CW |
4322 | void i915_gem_object_init(struct drm_i915_gem_object *obj, |
4323 | const struct drm_i915_gem_object_ops *ops) | |
0327d6ba | 4324 | { |
1233e2db CW |
4325 | mutex_init(&obj->mm.lock); |
4326 | ||
56cea323 | 4327 | INIT_LIST_HEAD(&obj->global_link); |
2f633156 | 4328 | INIT_LIST_HEAD(&obj->vma_list); |
d1b48c1e | 4329 | INIT_LIST_HEAD(&obj->lut_list); |
8d9d5744 | 4330 | INIT_LIST_HEAD(&obj->batch_pool_link); |
0327d6ba | 4331 | |
37e680a1 CW |
4332 | obj->ops = ops; |
4333 | ||
d07f0e59 CW |
4334 | reservation_object_init(&obj->__builtin_resv); |
4335 | obj->resv = &obj->__builtin_resv; | |
4336 | ||
50349247 | 4337 | obj->frontbuffer_ggtt_origin = ORIGIN_GTT; |
5b8c8aec | 4338 | init_request_active(&obj->frontbuffer_write, frontbuffer_retire); |
a4f5ea64 CW |
4339 | |
4340 | obj->mm.madv = I915_MADV_WILLNEED; | |
4341 | INIT_RADIX_TREE(&obj->mm.get_page.radix, GFP_KERNEL | __GFP_NOWARN); | |
4342 | mutex_init(&obj->mm.get_page.lock); | |
0327d6ba | 4343 | |
f19ec8cb | 4344 | i915_gem_info_add_obj(to_i915(obj->base.dev), obj->base.size); |
0327d6ba CW |
4345 | } |
4346 | ||
37e680a1 | 4347 | static const struct drm_i915_gem_object_ops i915_gem_object_ops = { |
3599a91c TU |
4348 | .flags = I915_GEM_OBJECT_HAS_STRUCT_PAGE | |
4349 | I915_GEM_OBJECT_IS_SHRINKABLE, | |
7c55e2c5 | 4350 | |
37e680a1 CW |
4351 | .get_pages = i915_gem_object_get_pages_gtt, |
4352 | .put_pages = i915_gem_object_put_pages_gtt, | |
7c55e2c5 CW |
4353 | |
4354 | .pwrite = i915_gem_object_pwrite_gtt, | |
37e680a1 CW |
4355 | }; |
4356 | ||
465c403c MA |
4357 | static int i915_gem_object_create_shmem(struct drm_device *dev, |
4358 | struct drm_gem_object *obj, | |
4359 | size_t size) | |
4360 | { | |
4361 | struct drm_i915_private *i915 = to_i915(dev); | |
4362 | unsigned long flags = VM_NORESERVE; | |
4363 | struct file *filp; | |
4364 | ||
4365 | drm_gem_private_object_init(dev, obj, size); | |
4366 | ||
4367 | if (i915->mm.gemfs) | |
4368 | filp = shmem_file_setup_with_mnt(i915->mm.gemfs, "i915", size, | |
4369 | flags); | |
4370 | else | |
4371 | filp = shmem_file_setup("i915", size, flags); | |
4372 | ||
4373 | if (IS_ERR(filp)) | |
4374 | return PTR_ERR(filp); | |
4375 | ||
4376 | obj->filp = filp; | |
4377 | ||
4378 | return 0; | |
4379 | } | |
4380 | ||
b4bcbe2a | 4381 | struct drm_i915_gem_object * |
12d79d78 | 4382 | i915_gem_object_create(struct drm_i915_private *dev_priv, u64 size) |
ac52bc56 | 4383 | { |
c397b908 | 4384 | struct drm_i915_gem_object *obj; |
5949eac4 | 4385 | struct address_space *mapping; |
b8f55be6 | 4386 | unsigned int cache_level; |
1a240d4d | 4387 | gfp_t mask; |
fe3db79b | 4388 | int ret; |
ac52bc56 | 4389 | |
b4bcbe2a CW |
4390 | /* There is a prevalence of the assumption that we fit the object's |
4391 | * page count inside a 32bit _signed_ variable. Let's document this and | |
4392 | * catch if we ever need to fix it. In the meantime, if you do spot | |
4393 | * such a local variable, please consider fixing! | |
4394 | */ | |
7a3ee5de | 4395 | if (size >> PAGE_SHIFT > INT_MAX) |
b4bcbe2a CW |
4396 | return ERR_PTR(-E2BIG); |
4397 | ||
4398 | if (overflows_type(size, obj->base.size)) | |
4399 | return ERR_PTR(-E2BIG); | |
4400 | ||
187685cb | 4401 | obj = i915_gem_object_alloc(dev_priv); |
c397b908 | 4402 | if (obj == NULL) |
fe3db79b | 4403 | return ERR_PTR(-ENOMEM); |
673a394b | 4404 | |
465c403c | 4405 | ret = i915_gem_object_create_shmem(&dev_priv->drm, &obj->base, size); |
fe3db79b CW |
4406 | if (ret) |
4407 | goto fail; | |
673a394b | 4408 | |
bed1ea95 | 4409 | mask = GFP_HIGHUSER | __GFP_RECLAIMABLE; |
c0f86832 | 4410 | if (IS_I965GM(dev_priv) || IS_I965G(dev_priv)) { |
bed1ea95 CW |
4411 | /* 965gm cannot relocate objects above 4GiB. */ |
4412 | mask &= ~__GFP_HIGHMEM; | |
4413 | mask |= __GFP_DMA32; | |
4414 | } | |
4415 | ||
93c76a3d | 4416 | mapping = obj->base.filp->f_mapping; |
bed1ea95 | 4417 | mapping_set_gfp_mask(mapping, mask); |
4846bf0c | 4418 | GEM_BUG_ON(!(mapping_gfp_mask(mapping) & __GFP_RECLAIM)); |
5949eac4 | 4419 | |
37e680a1 | 4420 | i915_gem_object_init(obj, &i915_gem_object_ops); |
73aa808f | 4421 | |
c397b908 DV |
4422 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; |
4423 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; | |
673a394b | 4424 | |
b8f55be6 | 4425 | if (HAS_LLC(dev_priv)) |
3d29b842 | 4426 | /* On some devices, we can have the GPU use the LLC (the CPU |
a1871112 EA |
4427 | * cache) for about a 10% performance improvement |
4428 | * compared to uncached. Graphics requests other than | |
4429 | * display scanout are coherent with the CPU in | |
4430 | * accessing this cache. This means in this mode we | |
4431 | * don't need to clflush on the CPU side, and on the | |
4432 | * GPU side we only need to flush internal caches to | |
4433 | * get data visible to the CPU. | |
4434 | * | |
4435 | * However, we maintain the display planes as UC, and so | |
4436 | * need to rebind when first used as such. | |
4437 | */ | |
b8f55be6 CW |
4438 | cache_level = I915_CACHE_LLC; |
4439 | else | |
4440 | cache_level = I915_CACHE_NONE; | |
a1871112 | 4441 | |
b8f55be6 | 4442 | i915_gem_object_set_cache_coherency(obj, cache_level); |
e27ab73d | 4443 | |
d861e338 DV |
4444 | trace_i915_gem_object_create(obj); |
4445 | ||
05394f39 | 4446 | return obj; |
fe3db79b CW |
4447 | |
4448 | fail: | |
4449 | i915_gem_object_free(obj); | |
fe3db79b | 4450 | return ERR_PTR(ret); |
c397b908 DV |
4451 | } |
4452 | ||
340fbd8c CW |
4453 | static bool discard_backing_storage(struct drm_i915_gem_object *obj) |
4454 | { | |
4455 | /* If we are the last user of the backing storage (be it shmemfs | |
4456 | * pages or stolen etc), we know that the pages are going to be | |
4457 | * immediately released. In this case, we can then skip copying | |
4458 | * back the contents from the GPU. | |
4459 | */ | |
4460 | ||
a4f5ea64 | 4461 | if (obj->mm.madv != I915_MADV_WILLNEED) |
340fbd8c CW |
4462 | return false; |
4463 | ||
4464 | if (obj->base.filp == NULL) | |
4465 | return true; | |
4466 | ||
4467 | /* At first glance, this looks racy, but then again so would be | |
4468 | * userspace racing mmap against close. However, the first external | |
4469 | * reference to the filp can only be obtained through the | |
4470 | * i915_gem_mmap_ioctl() which safeguards us against the user | |
4471 | * acquiring such a reference whilst we are in the middle of | |
4472 | * freeing the object. | |
4473 | */ | |
4474 | return atomic_long_read(&obj->base.filp->f_count) == 1; | |
4475 | } | |
4476 | ||
fbbd37b3 CW |
4477 | static void __i915_gem_free_objects(struct drm_i915_private *i915, |
4478 | struct llist_node *freed) | |
673a394b | 4479 | { |
fbbd37b3 | 4480 | struct drm_i915_gem_object *obj, *on; |
673a394b | 4481 | |
fbbd37b3 CW |
4482 | mutex_lock(&i915->drm.struct_mutex); |
4483 | intel_runtime_pm_get(i915); | |
4484 | llist_for_each_entry(obj, freed, freed) { | |
4485 | struct i915_vma *vma, *vn; | |
4486 | ||
4487 | trace_i915_gem_object_destroy(obj); | |
4488 | ||
4489 | GEM_BUG_ON(i915_gem_object_is_active(obj)); | |
4490 | list_for_each_entry_safe(vma, vn, | |
4491 | &obj->vma_list, obj_link) { | |
fbbd37b3 CW |
4492 | GEM_BUG_ON(i915_vma_is_active(vma)); |
4493 | vma->flags &= ~I915_VMA_PIN_MASK; | |
4494 | i915_vma_close(vma); | |
4495 | } | |
db6c2b41 CW |
4496 | GEM_BUG_ON(!list_empty(&obj->vma_list)); |
4497 | GEM_BUG_ON(!RB_EMPTY_ROOT(&obj->vma_tree)); | |
fbbd37b3 | 4498 | |
56cea323 | 4499 | list_del(&obj->global_link); |
fbbd37b3 CW |
4500 | } |
4501 | intel_runtime_pm_put(i915); | |
4502 | mutex_unlock(&i915->drm.struct_mutex); | |
4503 | ||
f2be9d68 CW |
4504 | cond_resched(); |
4505 | ||
fbbd37b3 CW |
4506 | llist_for_each_entry_safe(obj, on, freed, freed) { |
4507 | GEM_BUG_ON(obj->bind_count); | |
a65adaf8 | 4508 | GEM_BUG_ON(obj->userfault_count); |
fbbd37b3 | 4509 | GEM_BUG_ON(atomic_read(&obj->frontbuffer_bits)); |
67b48040 | 4510 | GEM_BUG_ON(!list_empty(&obj->lut_list)); |
fbbd37b3 CW |
4511 | |
4512 | if (obj->ops->release) | |
4513 | obj->ops->release(obj); | |
f65c9168 | 4514 | |
fbbd37b3 CW |
4515 | if (WARN_ON(i915_gem_object_has_pinned_pages(obj))) |
4516 | atomic_set(&obj->mm.pages_pin_count, 0); | |
548625ee | 4517 | __i915_gem_object_put_pages(obj, I915_MM_NORMAL); |
f1fa4f44 | 4518 | GEM_BUG_ON(i915_gem_object_has_pages(obj)); |
fbbd37b3 CW |
4519 | |
4520 | if (obj->base.import_attach) | |
4521 | drm_prime_gem_destroy(&obj->base, NULL); | |
4522 | ||
d07f0e59 | 4523 | reservation_object_fini(&obj->__builtin_resv); |
fbbd37b3 CW |
4524 | drm_gem_object_release(&obj->base); |
4525 | i915_gem_info_remove_obj(i915, obj->base.size); | |
4526 | ||
4527 | kfree(obj->bit_17); | |
4528 | i915_gem_object_free(obj); | |
4529 | } | |
4530 | } | |
4531 | ||
4532 | static void i915_gem_flush_free_objects(struct drm_i915_private *i915) | |
4533 | { | |
4534 | struct llist_node *freed; | |
4535 | ||
4536 | freed = llist_del_all(&i915->mm.free_list); | |
4537 | if (unlikely(freed)) | |
4538 | __i915_gem_free_objects(i915, freed); | |
4539 | } | |
4540 | ||
4541 | static void __i915_gem_free_work(struct work_struct *work) | |
4542 | { | |
4543 | struct drm_i915_private *i915 = | |
4544 | container_of(work, struct drm_i915_private, mm.free_work); | |
4545 | struct llist_node *freed; | |
26e12f89 | 4546 | |
b1f788c6 CW |
4547 | /* All file-owned VMA should have been released by this point through |
4548 | * i915_gem_close_object(), or earlier by i915_gem_context_close(). | |
4549 | * However, the object may also be bound into the global GTT (e.g. | |
4550 | * older GPUs without per-process support, or for direct access through | |
4551 | * the GTT either for the user or for scanout). Those VMA still need to | |
4552 | * unbound now. | |
4553 | */ | |
1488fc08 | 4554 | |
5ad08be7 | 4555 | while ((freed = llist_del_all(&i915->mm.free_list))) { |
fbbd37b3 | 4556 | __i915_gem_free_objects(i915, freed); |
5ad08be7 CW |
4557 | if (need_resched()) |
4558 | break; | |
4559 | } | |
fbbd37b3 | 4560 | } |
a071fa00 | 4561 | |
fbbd37b3 CW |
4562 | static void __i915_gem_free_object_rcu(struct rcu_head *head) |
4563 | { | |
4564 | struct drm_i915_gem_object *obj = | |
4565 | container_of(head, typeof(*obj), rcu); | |
4566 | struct drm_i915_private *i915 = to_i915(obj->base.dev); | |
4567 | ||
4568 | /* We can't simply use call_rcu() from i915_gem_free_object() | |
4569 | * as we need to block whilst unbinding, and the call_rcu | |
4570 | * task may be called from softirq context. So we take a | |
4571 | * detour through a worker. | |
4572 | */ | |
4573 | if (llist_add(&obj->freed, &i915->mm.free_list)) | |
4574 | schedule_work(&i915->mm.free_work); | |
4575 | } | |
656bfa3a | 4576 | |
fbbd37b3 CW |
4577 | void i915_gem_free_object(struct drm_gem_object *gem_obj) |
4578 | { | |
4579 | struct drm_i915_gem_object *obj = to_intel_bo(gem_obj); | |
a4f5ea64 | 4580 | |
bc0629a7 CW |
4581 | if (obj->mm.quirked) |
4582 | __i915_gem_object_unpin_pages(obj); | |
4583 | ||
340fbd8c | 4584 | if (discard_backing_storage(obj)) |
a4f5ea64 | 4585 | obj->mm.madv = I915_MADV_DONTNEED; |
de151cf6 | 4586 | |
fbbd37b3 CW |
4587 | /* Before we free the object, make sure any pure RCU-only |
4588 | * read-side critical sections are complete, e.g. | |
4589 | * i915_gem_busy_ioctl(). For the corresponding synchronized | |
4590 | * lookup see i915_gem_object_lookup_rcu(). | |
4591 | */ | |
4592 | call_rcu(&obj->rcu, __i915_gem_free_object_rcu); | |
673a394b EA |
4593 | } |
4594 | ||
f8a7fde4 CW |
4595 | void __i915_gem_object_release_unless_active(struct drm_i915_gem_object *obj) |
4596 | { | |
4597 | lockdep_assert_held(&obj->base.dev->struct_mutex); | |
4598 | ||
d1b48c1e CW |
4599 | if (!i915_gem_object_has_active_reference(obj) && |
4600 | i915_gem_object_is_active(obj)) | |
f8a7fde4 CW |
4601 | i915_gem_object_set_active_reference(obj); |
4602 | else | |
4603 | i915_gem_object_put(obj); | |
4604 | } | |
4605 | ||
3033acab CW |
4606 | static void assert_kernel_context_is_current(struct drm_i915_private *dev_priv) |
4607 | { | |
4608 | struct intel_engine_cs *engine; | |
4609 | enum intel_engine_id id; | |
4610 | ||
4611 | for_each_engine(engine, dev_priv, id) | |
f131e356 CW |
4612 | GEM_BUG_ON(engine->last_retired_context && |
4613 | !i915_gem_context_is_kernel(engine->last_retired_context)); | |
3033acab CW |
4614 | } |
4615 | ||
24145517 CW |
4616 | void i915_gem_sanitize(struct drm_i915_private *i915) |
4617 | { | |
f36325f3 CW |
4618 | if (i915_terminally_wedged(&i915->gpu_error)) { |
4619 | mutex_lock(&i915->drm.struct_mutex); | |
4620 | i915_gem_unset_wedged(i915); | |
4621 | mutex_unlock(&i915->drm.struct_mutex); | |
4622 | } | |
4623 | ||
24145517 CW |
4624 | /* |
4625 | * If we inherit context state from the BIOS or earlier occupants | |
4626 | * of the GPU, the GPU may be in an inconsistent state when we | |
4627 | * try to take over. The only way to remove the earlier state | |
4628 | * is by resetting. However, resetting on earlier gen is tricky as | |
4629 | * it may impact the display and we are uncertain about the stability | |
ea117b8d | 4630 | * of the reset, so this could be applied to even earlier gen. |
24145517 | 4631 | */ |
ea117b8d | 4632 | if (INTEL_GEN(i915) >= 5) { |
24145517 CW |
4633 | int reset = intel_gpu_reset(i915, ALL_ENGINES); |
4634 | WARN_ON(reset && reset != -ENODEV); | |
4635 | } | |
4636 | } | |
4637 | ||
bf9e8429 | 4638 | int i915_gem_suspend(struct drm_i915_private *dev_priv) |
29105ccc | 4639 | { |
bf9e8429 | 4640 | struct drm_device *dev = &dev_priv->drm; |
dcff85c8 | 4641 | int ret; |
28dfe52a | 4642 | |
c998e8a0 | 4643 | intel_runtime_pm_get(dev_priv); |
54b4f68f CW |
4644 | intel_suspend_gt_powersave(dev_priv); |
4645 | ||
45c5f202 | 4646 | mutex_lock(&dev->struct_mutex); |
5ab57c70 CW |
4647 | |
4648 | /* We have to flush all the executing contexts to main memory so | |
4649 | * that they can saved in the hibernation image. To ensure the last | |
4650 | * context image is coherent, we have to switch away from it. That | |
4651 | * leaves the dev_priv->kernel_context still active when | |
4652 | * we actually suspend, and its image in memory may not match the GPU | |
4653 | * state. Fortunately, the kernel_context is disposable and we do | |
4654 | * not rely on its state. | |
4655 | */ | |
4656 | ret = i915_gem_switch_to_kernel_context(dev_priv); | |
4657 | if (ret) | |
c998e8a0 | 4658 | goto err_unlock; |
5ab57c70 | 4659 | |
22dd3bb9 CW |
4660 | ret = i915_gem_wait_for_idle(dev_priv, |
4661 | I915_WAIT_INTERRUPTIBLE | | |
4662 | I915_WAIT_LOCKED); | |
cad9946c | 4663 | if (ret && ret != -EIO) |
c998e8a0 | 4664 | goto err_unlock; |
f7403347 | 4665 | |
3033acab | 4666 | assert_kernel_context_is_current(dev_priv); |
829a0af2 | 4667 | i915_gem_contexts_lost(dev_priv); |
45c5f202 CW |
4668 | mutex_unlock(&dev->struct_mutex); |
4669 | ||
63987bfe SAK |
4670 | intel_guc_suspend(dev_priv); |
4671 | ||
737b1506 | 4672 | cancel_delayed_work_sync(&dev_priv->gpu_error.hangcheck_work); |
67d97da3 | 4673 | cancel_delayed_work_sync(&dev_priv->gt.retire_work); |
bdeb9785 CW |
4674 | |
4675 | /* As the idle_work is rearming if it detects a race, play safe and | |
4676 | * repeat the flush until it is definitely idle. | |
4677 | */ | |
7c26240e | 4678 | drain_delayed_work(&dev_priv->gt.idle_work); |
bdeb9785 | 4679 | |
bdcf120b CW |
4680 | /* Assert that we sucessfully flushed all the work and |
4681 | * reset the GPU back to its idle, low power state. | |
4682 | */ | |
67d97da3 | 4683 | WARN_ON(dev_priv->gt.awake); |
fc692bd3 CW |
4684 | if (WARN_ON(!intel_engines_are_idle(dev_priv))) |
4685 | i915_gem_set_wedged(dev_priv); /* no hope, discard everything */ | |
bdcf120b | 4686 | |
1c777c5d ID |
4687 | /* |
4688 | * Neither the BIOS, ourselves or any other kernel | |
4689 | * expects the system to be in execlists mode on startup, | |
4690 | * so we need to reset the GPU back to legacy mode. And the only | |
4691 | * known way to disable logical contexts is through a GPU reset. | |
4692 | * | |
4693 | * So in order to leave the system in a known default configuration, | |
4694 | * always reset the GPU upon unload and suspend. Afterwards we then | |
4695 | * clean up the GEM state tracking, flushing off the requests and | |
4696 | * leaving the system in a known idle state. | |
4697 | * | |
4698 | * Note that is of the upmost importance that the GPU is idle and | |
4699 | * all stray writes are flushed *before* we dismantle the backing | |
4700 | * storage for the pinned objects. | |
4701 | * | |
4702 | * However, since we are uncertain that resetting the GPU on older | |
4703 | * machines is a good idea, we don't - just in case it leaves the | |
4704 | * machine in an unusable condition. | |
4705 | */ | |
24145517 | 4706 | i915_gem_sanitize(dev_priv); |
cad9946c CW |
4707 | |
4708 | intel_runtime_pm_put(dev_priv); | |
4709 | return 0; | |
1c777c5d | 4710 | |
c998e8a0 | 4711 | err_unlock: |
45c5f202 | 4712 | mutex_unlock(&dev->struct_mutex); |
c998e8a0 | 4713 | intel_runtime_pm_put(dev_priv); |
45c5f202 | 4714 | return ret; |
673a394b EA |
4715 | } |
4716 | ||
bf9e8429 | 4717 | void i915_gem_resume(struct drm_i915_private *dev_priv) |
5ab57c70 | 4718 | { |
bf9e8429 | 4719 | struct drm_device *dev = &dev_priv->drm; |
5ab57c70 | 4720 | |
31ab49ab ID |
4721 | WARN_ON(dev_priv->gt.awake); |
4722 | ||
5ab57c70 | 4723 | mutex_lock(&dev->struct_mutex); |
275a991c | 4724 | i915_gem_restore_gtt_mappings(dev_priv); |
269e6ea9 | 4725 | i915_gem_restore_fences(dev_priv); |
5ab57c70 CW |
4726 | |
4727 | /* As we didn't flush the kernel context before suspend, we cannot | |
4728 | * guarantee that the context image is complete. So let's just reset | |
4729 | * it and start again. | |
4730 | */ | |
821ed7df | 4731 | dev_priv->gt.resume(dev_priv); |
5ab57c70 CW |
4732 | |
4733 | mutex_unlock(&dev->struct_mutex); | |
4734 | } | |
4735 | ||
c6be607a | 4736 | void i915_gem_init_swizzling(struct drm_i915_private *dev_priv) |
f691e2f4 | 4737 | { |
c6be607a | 4738 | if (INTEL_GEN(dev_priv) < 5 || |
f691e2f4 DV |
4739 | dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE) |
4740 | return; | |
4741 | ||
4742 | I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) | | |
4743 | DISP_TILE_SURFACE_SWIZZLING); | |
4744 | ||
5db94019 | 4745 | if (IS_GEN5(dev_priv)) |
11782b02 DV |
4746 | return; |
4747 | ||
f691e2f4 | 4748 | I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_SWZCTL); |
5db94019 | 4749 | if (IS_GEN6(dev_priv)) |
6b26c86d | 4750 | I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB)); |
5db94019 | 4751 | else if (IS_GEN7(dev_priv)) |
6b26c86d | 4752 | I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB)); |
5db94019 | 4753 | else if (IS_GEN8(dev_priv)) |
31a5336e | 4754 | I915_WRITE(GAMTARBMODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_BDW)); |
8782e26c BW |
4755 | else |
4756 | BUG(); | |
f691e2f4 | 4757 | } |
e21af88d | 4758 | |
50a0bc90 | 4759 | static void init_unused_ring(struct drm_i915_private *dev_priv, u32 base) |
81e7f200 | 4760 | { |
81e7f200 VS |
4761 | I915_WRITE(RING_CTL(base), 0); |
4762 | I915_WRITE(RING_HEAD(base), 0); | |
4763 | I915_WRITE(RING_TAIL(base), 0); | |
4764 | I915_WRITE(RING_START(base), 0); | |
4765 | } | |
4766 | ||
50a0bc90 | 4767 | static void init_unused_rings(struct drm_i915_private *dev_priv) |
81e7f200 | 4768 | { |
50a0bc90 TU |
4769 | if (IS_I830(dev_priv)) { |
4770 | init_unused_ring(dev_priv, PRB1_BASE); | |
4771 | init_unused_ring(dev_priv, SRB0_BASE); | |
4772 | init_unused_ring(dev_priv, SRB1_BASE); | |
4773 | init_unused_ring(dev_priv, SRB2_BASE); | |
4774 | init_unused_ring(dev_priv, SRB3_BASE); | |
4775 | } else if (IS_GEN2(dev_priv)) { | |
4776 | init_unused_ring(dev_priv, SRB0_BASE); | |
4777 | init_unused_ring(dev_priv, SRB1_BASE); | |
4778 | } else if (IS_GEN3(dev_priv)) { | |
4779 | init_unused_ring(dev_priv, PRB1_BASE); | |
4780 | init_unused_ring(dev_priv, PRB2_BASE); | |
81e7f200 VS |
4781 | } |
4782 | } | |
4783 | ||
20a8a74a | 4784 | static int __i915_gem_restart_engines(void *data) |
4fc7c971 | 4785 | { |
20a8a74a | 4786 | struct drm_i915_private *i915 = data; |
e2f80391 | 4787 | struct intel_engine_cs *engine; |
3b3f1650 | 4788 | enum intel_engine_id id; |
20a8a74a CW |
4789 | int err; |
4790 | ||
4791 | for_each_engine(engine, i915, id) { | |
4792 | err = engine->init_hw(engine); | |
4793 | if (err) | |
4794 | return err; | |
4795 | } | |
4796 | ||
4797 | return 0; | |
4798 | } | |
4799 | ||
4800 | int i915_gem_init_hw(struct drm_i915_private *dev_priv) | |
4801 | { | |
d200cda6 | 4802 | int ret; |
4fc7c971 | 4803 | |
de867c20 CW |
4804 | dev_priv->gt.last_init_time = ktime_get(); |
4805 | ||
5e4f5189 CW |
4806 | /* Double layer security blanket, see i915_gem_init() */ |
4807 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); | |
4808 | ||
0031fb96 | 4809 | if (HAS_EDRAM(dev_priv) && INTEL_GEN(dev_priv) < 9) |
05e21cc4 | 4810 | I915_WRITE(HSW_IDICR, I915_READ(HSW_IDICR) | IDIHASHMSK(0xf)); |
4fc7c971 | 4811 | |
772c2a51 | 4812 | if (IS_HASWELL(dev_priv)) |
50a0bc90 | 4813 | I915_WRITE(MI_PREDICATE_RESULT_2, IS_HSW_GT3(dev_priv) ? |
0bf21347 | 4814 | LOWER_SLICE_ENABLED : LOWER_SLICE_DISABLED); |
9435373e | 4815 | |
6e266956 | 4816 | if (HAS_PCH_NOP(dev_priv)) { |
fd6b8f43 | 4817 | if (IS_IVYBRIDGE(dev_priv)) { |
6ba844b0 DV |
4818 | u32 temp = I915_READ(GEN7_MSG_CTL); |
4819 | temp &= ~(WAIT_FOR_PCH_FLR_ACK | WAIT_FOR_PCH_RESET_ACK); | |
4820 | I915_WRITE(GEN7_MSG_CTL, temp); | |
c6be607a | 4821 | } else if (INTEL_GEN(dev_priv) >= 7) { |
6ba844b0 DV |
4822 | u32 temp = I915_READ(HSW_NDE_RSTWRN_OPT); |
4823 | temp &= ~RESET_PCH_HANDSHAKE_ENABLE; | |
4824 | I915_WRITE(HSW_NDE_RSTWRN_OPT, temp); | |
4825 | } | |
88a2b2a3 BW |
4826 | } |
4827 | ||
c6be607a | 4828 | i915_gem_init_swizzling(dev_priv); |
4fc7c971 | 4829 | |
d5abdfda DV |
4830 | /* |
4831 | * At least 830 can leave some of the unused rings | |
4832 | * "active" (ie. head != tail) after resume which | |
4833 | * will prevent c3 entry. Makes sure all unused rings | |
4834 | * are totally idle. | |
4835 | */ | |
50a0bc90 | 4836 | init_unused_rings(dev_priv); |
d5abdfda | 4837 | |
ed54c1a1 | 4838 | BUG_ON(!dev_priv->kernel_context); |
90638cc1 | 4839 | |
c6be607a | 4840 | ret = i915_ppgtt_init_hw(dev_priv); |
4ad2fd88 JH |
4841 | if (ret) { |
4842 | DRM_ERROR("PPGTT enable HW failed %d\n", ret); | |
4843 | goto out; | |
4844 | } | |
4845 | ||
4846 | /* Need to do basic initialisation of all rings first: */ | |
20a8a74a CW |
4847 | ret = __i915_gem_restart_engines(dev_priv); |
4848 | if (ret) | |
4849 | goto out; | |
99433931 | 4850 | |
bf9e8429 | 4851 | intel_mocs_init_l3cc_table(dev_priv); |
0ccdacf6 | 4852 | |
b8991403 OM |
4853 | /* We can't enable contexts until all firmware is loaded */ |
4854 | ret = intel_uc_init_hw(dev_priv); | |
4855 | if (ret) | |
4856 | goto out; | |
33a732f4 | 4857 | |
5e4f5189 CW |
4858 | out: |
4859 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); | |
2fa48d8d | 4860 | return ret; |
8187a2b7 ZN |
4861 | } |
4862 | ||
39df9190 CW |
4863 | bool intel_sanitize_semaphores(struct drm_i915_private *dev_priv, int value) |
4864 | { | |
4865 | if (INTEL_INFO(dev_priv)->gen < 6) | |
4866 | return false; | |
4867 | ||
4868 | /* TODO: make semaphores and Execlists play nicely together */ | |
4f044a88 | 4869 | if (i915_modparams.enable_execlists) |
39df9190 CW |
4870 | return false; |
4871 | ||
4872 | if (value >= 0) | |
4873 | return value; | |
4874 | ||
39df9190 | 4875 | /* Enable semaphores on SNB when IO remapping is off */ |
80debff8 | 4876 | if (IS_GEN6(dev_priv) && intel_vtd_active()) |
39df9190 | 4877 | return false; |
39df9190 CW |
4878 | |
4879 | return true; | |
4880 | } | |
4881 | ||
bf9e8429 | 4882 | int i915_gem_init(struct drm_i915_private *dev_priv) |
1070a42b | 4883 | { |
1070a42b CW |
4884 | int ret; |
4885 | ||
bf9e8429 | 4886 | mutex_lock(&dev_priv->drm.struct_mutex); |
d62b4892 | 4887 | |
da9fe3f3 MA |
4888 | /* |
4889 | * We need to fallback to 4K pages since gvt gtt handling doesn't | |
4890 | * support huge page entries - we will need to check either hypervisor | |
4891 | * mm can support huge guest page or just do emulation in gvt. | |
4892 | */ | |
4893 | if (intel_vgpu_active(dev_priv)) | |
4894 | mkwrite_device_info(dev_priv)->page_sizes = | |
4895 | I915_GTT_PAGE_SIZE_4K; | |
4896 | ||
94312828 | 4897 | dev_priv->mm.unordered_timeline = dma_fence_context_alloc(1); |
57822dc6 | 4898 | |
4f044a88 | 4899 | if (!i915_modparams.enable_execlists) { |
821ed7df | 4900 | dev_priv->gt.resume = intel_legacy_submission_resume; |
7e37f889 | 4901 | dev_priv->gt.cleanup_engine = intel_engine_cleanup; |
454afebd | 4902 | } else { |
821ed7df | 4903 | dev_priv->gt.resume = intel_lr_context_resume; |
117897f4 | 4904 | dev_priv->gt.cleanup_engine = intel_logical_ring_cleanup; |
a83014d3 OM |
4905 | } |
4906 | ||
5e4f5189 CW |
4907 | /* This is just a security blanket to placate dragons. |
4908 | * On some systems, we very sporadically observe that the first TLBs | |
4909 | * used by the CS may be stale, despite us poking the TLB reset. If | |
4910 | * we hold the forcewake during initialisation these problems | |
4911 | * just magically go away. | |
4912 | */ | |
4913 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); | |
4914 | ||
8a2421bd CW |
4915 | ret = i915_gem_init_userptr(dev_priv); |
4916 | if (ret) | |
4917 | goto out_unlock; | |
f6b9d5ca CW |
4918 | |
4919 | ret = i915_gem_init_ggtt(dev_priv); | |
4920 | if (ret) | |
4921 | goto out_unlock; | |
d62b4892 | 4922 | |
829a0af2 | 4923 | ret = i915_gem_contexts_init(dev_priv); |
7bcc3777 JN |
4924 | if (ret) |
4925 | goto out_unlock; | |
2fa48d8d | 4926 | |
bf9e8429 | 4927 | ret = intel_engines_init(dev_priv); |
35a57ffb | 4928 | if (ret) |
7bcc3777 | 4929 | goto out_unlock; |
2fa48d8d | 4930 | |
bf9e8429 | 4931 | ret = i915_gem_init_hw(dev_priv); |
60990320 | 4932 | if (ret == -EIO) { |
7e21d648 | 4933 | /* Allow engine initialisation to fail by marking the GPU as |
60990320 CW |
4934 | * wedged. But we only want to do this where the GPU is angry, |
4935 | * for all other failure, such as an allocation failure, bail. | |
4936 | */ | |
4937 | DRM_ERROR("Failed to initialize GPU, declaring it wedged\n"); | |
821ed7df | 4938 | i915_gem_set_wedged(dev_priv); |
60990320 | 4939 | ret = 0; |
1070a42b | 4940 | } |
7bcc3777 JN |
4941 | |
4942 | out_unlock: | |
5e4f5189 | 4943 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); |
bf9e8429 | 4944 | mutex_unlock(&dev_priv->drm.struct_mutex); |
1070a42b | 4945 | |
60990320 | 4946 | return ret; |
1070a42b CW |
4947 | } |
4948 | ||
24145517 CW |
4949 | void i915_gem_init_mmio(struct drm_i915_private *i915) |
4950 | { | |
4951 | i915_gem_sanitize(i915); | |
4952 | } | |
4953 | ||
8187a2b7 | 4954 | void |
cb15d9f8 | 4955 | i915_gem_cleanup_engines(struct drm_i915_private *dev_priv) |
8187a2b7 | 4956 | { |
e2f80391 | 4957 | struct intel_engine_cs *engine; |
3b3f1650 | 4958 | enum intel_engine_id id; |
8187a2b7 | 4959 | |
3b3f1650 | 4960 | for_each_engine(engine, dev_priv, id) |
117897f4 | 4961 | dev_priv->gt.cleanup_engine(engine); |
8187a2b7 ZN |
4962 | } |
4963 | ||
40ae4e16 ID |
4964 | void |
4965 | i915_gem_load_init_fences(struct drm_i915_private *dev_priv) | |
4966 | { | |
49ef5294 | 4967 | int i; |
40ae4e16 ID |
4968 | |
4969 | if (INTEL_INFO(dev_priv)->gen >= 7 && !IS_VALLEYVIEW(dev_priv) && | |
4970 | !IS_CHERRYVIEW(dev_priv)) | |
4971 | dev_priv->num_fence_regs = 32; | |
73f67aa8 JN |
4972 | else if (INTEL_INFO(dev_priv)->gen >= 4 || |
4973 | IS_I945G(dev_priv) || IS_I945GM(dev_priv) || | |
4974 | IS_G33(dev_priv) || IS_PINEVIEW(dev_priv)) | |
40ae4e16 ID |
4975 | dev_priv->num_fence_regs = 16; |
4976 | else | |
4977 | dev_priv->num_fence_regs = 8; | |
4978 | ||
c033666a | 4979 | if (intel_vgpu_active(dev_priv)) |
40ae4e16 ID |
4980 | dev_priv->num_fence_regs = |
4981 | I915_READ(vgtif_reg(avail_rs.fence_num)); | |
4982 | ||
4983 | /* Initialize fence registers to zero */ | |
49ef5294 CW |
4984 | for (i = 0; i < dev_priv->num_fence_regs; i++) { |
4985 | struct drm_i915_fence_reg *fence = &dev_priv->fence_regs[i]; | |
4986 | ||
4987 | fence->i915 = dev_priv; | |
4988 | fence->id = i; | |
4989 | list_add_tail(&fence->link, &dev_priv->mm.fence_list); | |
4990 | } | |
4362f4f6 | 4991 | i915_gem_restore_fences(dev_priv); |
40ae4e16 | 4992 | |
4362f4f6 | 4993 | i915_gem_detect_bit_6_swizzle(dev_priv); |
40ae4e16 ID |
4994 | } |
4995 | ||
73cb9701 | 4996 | int |
cb15d9f8 | 4997 | i915_gem_load_init(struct drm_i915_private *dev_priv) |
673a394b | 4998 | { |
a933568e | 4999 | int err = -ENOMEM; |
42dcedd4 | 5000 | |
a933568e TU |
5001 | dev_priv->objects = KMEM_CACHE(drm_i915_gem_object, SLAB_HWCACHE_ALIGN); |
5002 | if (!dev_priv->objects) | |
73cb9701 | 5003 | goto err_out; |
73cb9701 | 5004 | |
a933568e TU |
5005 | dev_priv->vmas = KMEM_CACHE(i915_vma, SLAB_HWCACHE_ALIGN); |
5006 | if (!dev_priv->vmas) | |
73cb9701 | 5007 | goto err_objects; |
73cb9701 | 5008 | |
d1b48c1e CW |
5009 | dev_priv->luts = KMEM_CACHE(i915_lut_handle, 0); |
5010 | if (!dev_priv->luts) | |
5011 | goto err_vmas; | |
5012 | ||
a933568e TU |
5013 | dev_priv->requests = KMEM_CACHE(drm_i915_gem_request, |
5014 | SLAB_HWCACHE_ALIGN | | |
5015 | SLAB_RECLAIM_ACCOUNT | | |
5f0d5a3a | 5016 | SLAB_TYPESAFE_BY_RCU); |
a933568e | 5017 | if (!dev_priv->requests) |
d1b48c1e | 5018 | goto err_luts; |
73cb9701 | 5019 | |
52e54209 CW |
5020 | dev_priv->dependencies = KMEM_CACHE(i915_dependency, |
5021 | SLAB_HWCACHE_ALIGN | | |
5022 | SLAB_RECLAIM_ACCOUNT); | |
5023 | if (!dev_priv->dependencies) | |
5024 | goto err_requests; | |
5025 | ||
c5cf9a91 CW |
5026 | dev_priv->priorities = KMEM_CACHE(i915_priolist, SLAB_HWCACHE_ALIGN); |
5027 | if (!dev_priv->priorities) | |
5028 | goto err_dependencies; | |
5029 | ||
73cb9701 CW |
5030 | mutex_lock(&dev_priv->drm.struct_mutex); |
5031 | INIT_LIST_HEAD(&dev_priv->gt.timelines); | |
bb89485e | 5032 | err = i915_gem_timeline_init__global(dev_priv); |
73cb9701 CW |
5033 | mutex_unlock(&dev_priv->drm.struct_mutex); |
5034 | if (err) | |
c5cf9a91 | 5035 | goto err_priorities; |
673a394b | 5036 | |
fbbd37b3 CW |
5037 | INIT_WORK(&dev_priv->mm.free_work, __i915_gem_free_work); |
5038 | init_llist_head(&dev_priv->mm.free_list); | |
6c085a72 CW |
5039 | INIT_LIST_HEAD(&dev_priv->mm.unbound_list); |
5040 | INIT_LIST_HEAD(&dev_priv->mm.bound_list); | |
a09ba7fa | 5041 | INIT_LIST_HEAD(&dev_priv->mm.fence_list); |
275f039d | 5042 | INIT_LIST_HEAD(&dev_priv->mm.userfault_list); |
67d97da3 | 5043 | INIT_DELAYED_WORK(&dev_priv->gt.retire_work, |
673a394b | 5044 | i915_gem_retire_work_handler); |
67d97da3 | 5045 | INIT_DELAYED_WORK(&dev_priv->gt.idle_work, |
b29c19b6 | 5046 | i915_gem_idle_work_handler); |
1f15b76f | 5047 | init_waitqueue_head(&dev_priv->gpu_error.wait_queue); |
1f83fee0 | 5048 | init_waitqueue_head(&dev_priv->gpu_error.reset_queue); |
31169714 | 5049 | |
6f633402 JL |
5050 | atomic_set(&dev_priv->mm.bsd_engine_dispatch_index, 0); |
5051 | ||
b5add959 | 5052 | spin_lock_init(&dev_priv->fb_tracking.lock); |
73cb9701 | 5053 | |
465c403c MA |
5054 | err = i915_gemfs_init(dev_priv); |
5055 | if (err) | |
5056 | DRM_NOTE("Unable to create a private tmpfs mount, hugepage support will be disabled(%d).\n", err); | |
5057 | ||
73cb9701 CW |
5058 | return 0; |
5059 | ||
c5cf9a91 CW |
5060 | err_priorities: |
5061 | kmem_cache_destroy(dev_priv->priorities); | |
52e54209 CW |
5062 | err_dependencies: |
5063 | kmem_cache_destroy(dev_priv->dependencies); | |
73cb9701 CW |
5064 | err_requests: |
5065 | kmem_cache_destroy(dev_priv->requests); | |
d1b48c1e CW |
5066 | err_luts: |
5067 | kmem_cache_destroy(dev_priv->luts); | |
73cb9701 CW |
5068 | err_vmas: |
5069 | kmem_cache_destroy(dev_priv->vmas); | |
5070 | err_objects: | |
5071 | kmem_cache_destroy(dev_priv->objects); | |
5072 | err_out: | |
5073 | return err; | |
673a394b | 5074 | } |
71acb5eb | 5075 | |
cb15d9f8 | 5076 | void i915_gem_load_cleanup(struct drm_i915_private *dev_priv) |
d64aa096 | 5077 | { |
c4d4c1c6 | 5078 | i915_gem_drain_freed_objects(dev_priv); |
7d5d59e5 | 5079 | WARN_ON(!llist_empty(&dev_priv->mm.free_list)); |
c4d4c1c6 | 5080 | WARN_ON(dev_priv->mm.object_count); |
7d5d59e5 | 5081 | |
ea84aa77 MA |
5082 | mutex_lock(&dev_priv->drm.struct_mutex); |
5083 | i915_gem_timeline_fini(&dev_priv->gt.global_timeline); | |
5084 | WARN_ON(!list_empty(&dev_priv->gt.timelines)); | |
5085 | mutex_unlock(&dev_priv->drm.struct_mutex); | |
5086 | ||
c5cf9a91 | 5087 | kmem_cache_destroy(dev_priv->priorities); |
52e54209 | 5088 | kmem_cache_destroy(dev_priv->dependencies); |
d64aa096 | 5089 | kmem_cache_destroy(dev_priv->requests); |
d1b48c1e | 5090 | kmem_cache_destroy(dev_priv->luts); |
d64aa096 ID |
5091 | kmem_cache_destroy(dev_priv->vmas); |
5092 | kmem_cache_destroy(dev_priv->objects); | |
0eafec6d CW |
5093 | |
5094 | /* And ensure that our DESTROY_BY_RCU slabs are truly destroyed */ | |
5095 | rcu_barrier(); | |
465c403c MA |
5096 | |
5097 | i915_gemfs_fini(dev_priv); | |
d64aa096 ID |
5098 | } |
5099 | ||
6a800eab CW |
5100 | int i915_gem_freeze(struct drm_i915_private *dev_priv) |
5101 | { | |
d0aa301a CW |
5102 | /* Discard all purgeable objects, let userspace recover those as |
5103 | * required after resuming. | |
5104 | */ | |
6a800eab | 5105 | i915_gem_shrink_all(dev_priv); |
6a800eab | 5106 | |
6a800eab CW |
5107 | return 0; |
5108 | } | |
5109 | ||
461fb99c CW |
5110 | int i915_gem_freeze_late(struct drm_i915_private *dev_priv) |
5111 | { | |
5112 | struct drm_i915_gem_object *obj; | |
7aab2d53 CW |
5113 | struct list_head *phases[] = { |
5114 | &dev_priv->mm.unbound_list, | |
5115 | &dev_priv->mm.bound_list, | |
5116 | NULL | |
5117 | }, **p; | |
461fb99c CW |
5118 | |
5119 | /* Called just before we write the hibernation image. | |
5120 | * | |
5121 | * We need to update the domain tracking to reflect that the CPU | |
5122 | * will be accessing all the pages to create and restore from the | |
5123 | * hibernation, and so upon restoration those pages will be in the | |
5124 | * CPU domain. | |
5125 | * | |
5126 | * To make sure the hibernation image contains the latest state, | |
5127 | * we update that state just before writing out the image. | |
7aab2d53 CW |
5128 | * |
5129 | * To try and reduce the hibernation image, we manually shrink | |
d0aa301a | 5130 | * the objects as well, see i915_gem_freeze() |
461fb99c CW |
5131 | */ |
5132 | ||
912d572d | 5133 | i915_gem_shrink(dev_priv, -1UL, NULL, I915_SHRINK_UNBOUND); |
17b93c40 | 5134 | i915_gem_drain_freed_objects(dev_priv); |
461fb99c | 5135 | |
d0aa301a | 5136 | mutex_lock(&dev_priv->drm.struct_mutex); |
7aab2d53 | 5137 | for (p = phases; *p; p++) { |
e27ab73d CW |
5138 | list_for_each_entry(obj, *p, global_link) |
5139 | __start_cpu_write(obj); | |
461fb99c | 5140 | } |
6a800eab | 5141 | mutex_unlock(&dev_priv->drm.struct_mutex); |
461fb99c CW |
5142 | |
5143 | return 0; | |
5144 | } | |
5145 | ||
f787a5f5 | 5146 | void i915_gem_release(struct drm_device *dev, struct drm_file *file) |
b962442e | 5147 | { |
f787a5f5 | 5148 | struct drm_i915_file_private *file_priv = file->driver_priv; |
15f7bbc7 | 5149 | struct drm_i915_gem_request *request; |
b962442e EA |
5150 | |
5151 | /* Clean up our request list when the client is going away, so that | |
5152 | * later retire_requests won't dereference our soon-to-be-gone | |
5153 | * file_priv. | |
5154 | */ | |
1c25595f | 5155 | spin_lock(&file_priv->mm.lock); |
c8659efa | 5156 | list_for_each_entry(request, &file_priv->mm.request_list, client_link) |
f787a5f5 | 5157 | request->file_priv = NULL; |
1c25595f | 5158 | spin_unlock(&file_priv->mm.lock); |
b29c19b6 CW |
5159 | } |
5160 | ||
829a0af2 | 5161 | int i915_gem_open(struct drm_i915_private *i915, struct drm_file *file) |
b29c19b6 CW |
5162 | { |
5163 | struct drm_i915_file_private *file_priv; | |
e422b888 | 5164 | int ret; |
b29c19b6 | 5165 | |
c4c29d7b | 5166 | DRM_DEBUG("\n"); |
b29c19b6 CW |
5167 | |
5168 | file_priv = kzalloc(sizeof(*file_priv), GFP_KERNEL); | |
5169 | if (!file_priv) | |
5170 | return -ENOMEM; | |
5171 | ||
5172 | file->driver_priv = file_priv; | |
829a0af2 | 5173 | file_priv->dev_priv = i915; |
ab0e7ff9 | 5174 | file_priv->file = file; |
b29c19b6 CW |
5175 | |
5176 | spin_lock_init(&file_priv->mm.lock); | |
5177 | INIT_LIST_HEAD(&file_priv->mm.request_list); | |
b29c19b6 | 5178 | |
c80ff16e | 5179 | file_priv->bsd_engine = -1; |
de1add36 | 5180 | |
829a0af2 | 5181 | ret = i915_gem_context_open(i915, file); |
e422b888 BW |
5182 | if (ret) |
5183 | kfree(file_priv); | |
b29c19b6 | 5184 | |
e422b888 | 5185 | return ret; |
b29c19b6 CW |
5186 | } |
5187 | ||
b680c37a DV |
5188 | /** |
5189 | * i915_gem_track_fb - update frontbuffer tracking | |
d9072a3e GT |
5190 | * @old: current GEM buffer for the frontbuffer slots |
5191 | * @new: new GEM buffer for the frontbuffer slots | |
5192 | * @frontbuffer_bits: bitmask of frontbuffer slots | |
b680c37a DV |
5193 | * |
5194 | * This updates the frontbuffer tracking bits @frontbuffer_bits by clearing them | |
5195 | * from @old and setting them in @new. Both @old and @new can be NULL. | |
5196 | */ | |
a071fa00 DV |
5197 | void i915_gem_track_fb(struct drm_i915_gem_object *old, |
5198 | struct drm_i915_gem_object *new, | |
5199 | unsigned frontbuffer_bits) | |
5200 | { | |
faf5bf0a CW |
5201 | /* Control of individual bits within the mask are guarded by |
5202 | * the owning plane->mutex, i.e. we can never see concurrent | |
5203 | * manipulation of individual bits. But since the bitfield as a whole | |
5204 | * is updated using RMW, we need to use atomics in order to update | |
5205 | * the bits. | |
5206 | */ | |
5207 | BUILD_BUG_ON(INTEL_FRONTBUFFER_BITS_PER_PIPE * I915_MAX_PIPES > | |
5208 | sizeof(atomic_t) * BITS_PER_BYTE); | |
5209 | ||
a071fa00 | 5210 | if (old) { |
faf5bf0a CW |
5211 | WARN_ON(!(atomic_read(&old->frontbuffer_bits) & frontbuffer_bits)); |
5212 | atomic_andnot(frontbuffer_bits, &old->frontbuffer_bits); | |
a071fa00 DV |
5213 | } |
5214 | ||
5215 | if (new) { | |
faf5bf0a CW |
5216 | WARN_ON(atomic_read(&new->frontbuffer_bits) & frontbuffer_bits); |
5217 | atomic_or(frontbuffer_bits, &new->frontbuffer_bits); | |
a071fa00 DV |
5218 | } |
5219 | } | |
5220 | ||
ea70299d DG |
5221 | /* Allocate a new GEM object and fill it with the supplied data */ |
5222 | struct drm_i915_gem_object * | |
12d79d78 | 5223 | i915_gem_object_create_from_data(struct drm_i915_private *dev_priv, |
ea70299d DG |
5224 | const void *data, size_t size) |
5225 | { | |
5226 | struct drm_i915_gem_object *obj; | |
be062fa4 CW |
5227 | struct file *file; |
5228 | size_t offset; | |
5229 | int err; | |
ea70299d | 5230 | |
12d79d78 | 5231 | obj = i915_gem_object_create(dev_priv, round_up(size, PAGE_SIZE)); |
fe3db79b | 5232 | if (IS_ERR(obj)) |
ea70299d DG |
5233 | return obj; |
5234 | ||
ce8ff099 | 5235 | GEM_BUG_ON(obj->base.write_domain != I915_GEM_DOMAIN_CPU); |
ea70299d | 5236 | |
be062fa4 CW |
5237 | file = obj->base.filp; |
5238 | offset = 0; | |
5239 | do { | |
5240 | unsigned int len = min_t(typeof(size), size, PAGE_SIZE); | |
5241 | struct page *page; | |
5242 | void *pgdata, *vaddr; | |
ea70299d | 5243 | |
be062fa4 CW |
5244 | err = pagecache_write_begin(file, file->f_mapping, |
5245 | offset, len, 0, | |
5246 | &page, &pgdata); | |
5247 | if (err < 0) | |
5248 | goto fail; | |
ea70299d | 5249 | |
be062fa4 CW |
5250 | vaddr = kmap(page); |
5251 | memcpy(vaddr, data, len); | |
5252 | kunmap(page); | |
5253 | ||
5254 | err = pagecache_write_end(file, file->f_mapping, | |
5255 | offset, len, len, | |
5256 | page, pgdata); | |
5257 | if (err < 0) | |
5258 | goto fail; | |
5259 | ||
5260 | size -= len; | |
5261 | data += len; | |
5262 | offset += len; | |
5263 | } while (size); | |
ea70299d DG |
5264 | |
5265 | return obj; | |
5266 | ||
5267 | fail: | |
f8c417cd | 5268 | i915_gem_object_put(obj); |
be062fa4 | 5269 | return ERR_PTR(err); |
ea70299d | 5270 | } |
96d77634 CW |
5271 | |
5272 | struct scatterlist * | |
5273 | i915_gem_object_get_sg(struct drm_i915_gem_object *obj, | |
5274 | unsigned int n, | |
5275 | unsigned int *offset) | |
5276 | { | |
a4f5ea64 | 5277 | struct i915_gem_object_page_iter *iter = &obj->mm.get_page; |
96d77634 CW |
5278 | struct scatterlist *sg; |
5279 | unsigned int idx, count; | |
5280 | ||
5281 | might_sleep(); | |
5282 | GEM_BUG_ON(n >= obj->base.size >> PAGE_SHIFT); | |
a4f5ea64 | 5283 | GEM_BUG_ON(!i915_gem_object_has_pinned_pages(obj)); |
96d77634 CW |
5284 | |
5285 | /* As we iterate forward through the sg, we record each entry in a | |
5286 | * radixtree for quick repeated (backwards) lookups. If we have seen | |
5287 | * this index previously, we will have an entry for it. | |
5288 | * | |
5289 | * Initial lookup is O(N), but this is amortized to O(1) for | |
5290 | * sequential page access (where each new request is consecutive | |
5291 | * to the previous one). Repeated lookups are O(lg(obj->base.size)), | |
5292 | * i.e. O(1) with a large constant! | |
5293 | */ | |
5294 | if (n < READ_ONCE(iter->sg_idx)) | |
5295 | goto lookup; | |
5296 | ||
5297 | mutex_lock(&iter->lock); | |
5298 | ||
5299 | /* We prefer to reuse the last sg so that repeated lookup of this | |
5300 | * (or the subsequent) sg are fast - comparing against the last | |
5301 | * sg is faster than going through the radixtree. | |
5302 | */ | |
5303 | ||
5304 | sg = iter->sg_pos; | |
5305 | idx = iter->sg_idx; | |
5306 | count = __sg_page_count(sg); | |
5307 | ||
5308 | while (idx + count <= n) { | |
5309 | unsigned long exception, i; | |
5310 | int ret; | |
5311 | ||
5312 | /* If we cannot allocate and insert this entry, or the | |
5313 | * individual pages from this range, cancel updating the | |
5314 | * sg_idx so that on this lookup we are forced to linearly | |
5315 | * scan onwards, but on future lookups we will try the | |
5316 | * insertion again (in which case we need to be careful of | |
5317 | * the error return reporting that we have already inserted | |
5318 | * this index). | |
5319 | */ | |
5320 | ret = radix_tree_insert(&iter->radix, idx, sg); | |
5321 | if (ret && ret != -EEXIST) | |
5322 | goto scan; | |
5323 | ||
5324 | exception = | |
5325 | RADIX_TREE_EXCEPTIONAL_ENTRY | | |
5326 | idx << RADIX_TREE_EXCEPTIONAL_SHIFT; | |
5327 | for (i = 1; i < count; i++) { | |
5328 | ret = radix_tree_insert(&iter->radix, idx + i, | |
5329 | (void *)exception); | |
5330 | if (ret && ret != -EEXIST) | |
5331 | goto scan; | |
5332 | } | |
5333 | ||
5334 | idx += count; | |
5335 | sg = ____sg_next(sg); | |
5336 | count = __sg_page_count(sg); | |
5337 | } | |
5338 | ||
5339 | scan: | |
5340 | iter->sg_pos = sg; | |
5341 | iter->sg_idx = idx; | |
5342 | ||
5343 | mutex_unlock(&iter->lock); | |
5344 | ||
5345 | if (unlikely(n < idx)) /* insertion completed by another thread */ | |
5346 | goto lookup; | |
5347 | ||
5348 | /* In case we failed to insert the entry into the radixtree, we need | |
5349 | * to look beyond the current sg. | |
5350 | */ | |
5351 | while (idx + count <= n) { | |
5352 | idx += count; | |
5353 | sg = ____sg_next(sg); | |
5354 | count = __sg_page_count(sg); | |
5355 | } | |
5356 | ||
5357 | *offset = n - idx; | |
5358 | return sg; | |
5359 | ||
5360 | lookup: | |
5361 | rcu_read_lock(); | |
5362 | ||
5363 | sg = radix_tree_lookup(&iter->radix, n); | |
5364 | GEM_BUG_ON(!sg); | |
5365 | ||
5366 | /* If this index is in the middle of multi-page sg entry, | |
5367 | * the radixtree will contain an exceptional entry that points | |
5368 | * to the start of that range. We will return the pointer to | |
5369 | * the base page and the offset of this page within the | |
5370 | * sg entry's range. | |
5371 | */ | |
5372 | *offset = 0; | |
5373 | if (unlikely(radix_tree_exception(sg))) { | |
5374 | unsigned long base = | |
5375 | (unsigned long)sg >> RADIX_TREE_EXCEPTIONAL_SHIFT; | |
5376 | ||
5377 | sg = radix_tree_lookup(&iter->radix, base); | |
5378 | GEM_BUG_ON(!sg); | |
5379 | ||
5380 | *offset = n - base; | |
5381 | } | |
5382 | ||
5383 | rcu_read_unlock(); | |
5384 | ||
5385 | return sg; | |
5386 | } | |
5387 | ||
5388 | struct page * | |
5389 | i915_gem_object_get_page(struct drm_i915_gem_object *obj, unsigned int n) | |
5390 | { | |
5391 | struct scatterlist *sg; | |
5392 | unsigned int offset; | |
5393 | ||
5394 | GEM_BUG_ON(!i915_gem_object_has_struct_page(obj)); | |
5395 | ||
5396 | sg = i915_gem_object_get_sg(obj, n, &offset); | |
5397 | return nth_page(sg_page(sg), offset); | |
5398 | } | |
5399 | ||
5400 | /* Like i915_gem_object_get_page(), but mark the returned page dirty */ | |
5401 | struct page * | |
5402 | i915_gem_object_get_dirty_page(struct drm_i915_gem_object *obj, | |
5403 | unsigned int n) | |
5404 | { | |
5405 | struct page *page; | |
5406 | ||
5407 | page = i915_gem_object_get_page(obj, n); | |
a4f5ea64 | 5408 | if (!obj->mm.dirty) |
96d77634 CW |
5409 | set_page_dirty(page); |
5410 | ||
5411 | return page; | |
5412 | } | |
5413 | ||
5414 | dma_addr_t | |
5415 | i915_gem_object_get_dma_address(struct drm_i915_gem_object *obj, | |
5416 | unsigned long n) | |
5417 | { | |
5418 | struct scatterlist *sg; | |
5419 | unsigned int offset; | |
5420 | ||
5421 | sg = i915_gem_object_get_sg(obj, n, &offset); | |
5422 | return sg_dma_address(sg) + (offset << PAGE_SHIFT); | |
5423 | } | |
935a2f77 | 5424 | |
8eeb7906 CW |
5425 | int i915_gem_object_attach_phys(struct drm_i915_gem_object *obj, int align) |
5426 | { | |
5427 | struct sg_table *pages; | |
5428 | int err; | |
5429 | ||
5430 | if (align > obj->base.size) | |
5431 | return -EINVAL; | |
5432 | ||
5433 | if (obj->ops == &i915_gem_phys_ops) | |
5434 | return 0; | |
5435 | ||
5436 | if (obj->ops != &i915_gem_object_ops) | |
5437 | return -EINVAL; | |
5438 | ||
5439 | err = i915_gem_object_unbind(obj); | |
5440 | if (err) | |
5441 | return err; | |
5442 | ||
5443 | mutex_lock(&obj->mm.lock); | |
5444 | ||
5445 | if (obj->mm.madv != I915_MADV_WILLNEED) { | |
5446 | err = -EFAULT; | |
5447 | goto err_unlock; | |
5448 | } | |
5449 | ||
5450 | if (obj->mm.quirked) { | |
5451 | err = -EFAULT; | |
5452 | goto err_unlock; | |
5453 | } | |
5454 | ||
5455 | if (obj->mm.mapping) { | |
5456 | err = -EBUSY; | |
5457 | goto err_unlock; | |
5458 | } | |
5459 | ||
5460 | pages = obj->mm.pages; | |
5461 | obj->ops = &i915_gem_phys_ops; | |
5462 | ||
8fb6a5df | 5463 | err = ____i915_gem_object_get_pages(obj); |
8eeb7906 CW |
5464 | if (err) |
5465 | goto err_xfer; | |
5466 | ||
5467 | /* Perma-pin (until release) the physical set of pages */ | |
5468 | __i915_gem_object_pin_pages(obj); | |
5469 | ||
5470 | if (!IS_ERR_OR_NULL(pages)) | |
5471 | i915_gem_object_ops.put_pages(obj, pages); | |
5472 | mutex_unlock(&obj->mm.lock); | |
5473 | return 0; | |
5474 | ||
5475 | err_xfer: | |
5476 | obj->ops = &i915_gem_object_ops; | |
5477 | obj->mm.pages = pages; | |
5478 | err_unlock: | |
5479 | mutex_unlock(&obj->mm.lock); | |
5480 | return err; | |
5481 | } | |
5482 | ||
935a2f77 CW |
5483 | #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST) |
5484 | #include "selftests/scatterlist.c" | |
66d9cb5d | 5485 | #include "selftests/mock_gem_device.c" |
44653988 | 5486 | #include "selftests/huge_gem_object.c" |
4049866f | 5487 | #include "selftests/huge_pages.c" |
8335fd65 | 5488 | #include "selftests/i915_gem_object.c" |
17059450 | 5489 | #include "selftests/i915_gem_coherency.c" |
935a2f77 | 5490 | #endif |