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673a394b EA |
1 | /* |
2 | * Copyright © 2008 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | * | |
26 | */ | |
27 | ||
28 | #include "drmP.h" | |
29 | #include "drm.h" | |
30 | #include "i915_drm.h" | |
31 | #include "i915_drv.h" | |
32 | #include <linux/swap.h> | |
33 | ||
34 | static int | |
35 | i915_gem_object_set_domain(struct drm_gem_object *obj, | |
36 | uint32_t read_domains, | |
37 | uint32_t write_domain); | |
38 | static int | |
39 | i915_gem_object_set_domain_range(struct drm_gem_object *obj, | |
40 | uint64_t offset, | |
41 | uint64_t size, | |
42 | uint32_t read_domains, | |
43 | uint32_t write_domain); | |
44 | static int | |
45 | i915_gem_set_domain(struct drm_gem_object *obj, | |
46 | struct drm_file *file_priv, | |
47 | uint32_t read_domains, | |
48 | uint32_t write_domain); | |
49 | static int i915_gem_object_get_page_list(struct drm_gem_object *obj); | |
50 | static void i915_gem_object_free_page_list(struct drm_gem_object *obj); | |
51 | static int i915_gem_object_wait_rendering(struct drm_gem_object *obj); | |
52 | ||
6dbe2772 KP |
53 | static void |
54 | i915_gem_cleanup_ringbuffer(struct drm_device *dev); | |
55 | ||
673a394b EA |
56 | int |
57 | i915_gem_init_ioctl(struct drm_device *dev, void *data, | |
58 | struct drm_file *file_priv) | |
59 | { | |
60 | drm_i915_private_t *dev_priv = dev->dev_private; | |
61 | struct drm_i915_gem_init *args = data; | |
62 | ||
63 | mutex_lock(&dev->struct_mutex); | |
64 | ||
65 | if (args->gtt_start >= args->gtt_end || | |
66 | (args->gtt_start & (PAGE_SIZE - 1)) != 0 || | |
67 | (args->gtt_end & (PAGE_SIZE - 1)) != 0) { | |
68 | mutex_unlock(&dev->struct_mutex); | |
69 | return -EINVAL; | |
70 | } | |
71 | ||
72 | drm_mm_init(&dev_priv->mm.gtt_space, args->gtt_start, | |
73 | args->gtt_end - args->gtt_start); | |
74 | ||
75 | dev->gtt_total = (uint32_t) (args->gtt_end - args->gtt_start); | |
76 | ||
77 | mutex_unlock(&dev->struct_mutex); | |
78 | ||
79 | return 0; | |
80 | } | |
81 | ||
82 | ||
83 | /** | |
84 | * Creates a new mm object and returns a handle to it. | |
85 | */ | |
86 | int | |
87 | i915_gem_create_ioctl(struct drm_device *dev, void *data, | |
88 | struct drm_file *file_priv) | |
89 | { | |
90 | struct drm_i915_gem_create *args = data; | |
91 | struct drm_gem_object *obj; | |
92 | int handle, ret; | |
93 | ||
94 | args->size = roundup(args->size, PAGE_SIZE); | |
95 | ||
96 | /* Allocate the new object */ | |
97 | obj = drm_gem_object_alloc(dev, args->size); | |
98 | if (obj == NULL) | |
99 | return -ENOMEM; | |
100 | ||
101 | ret = drm_gem_handle_create(file_priv, obj, &handle); | |
102 | mutex_lock(&dev->struct_mutex); | |
103 | drm_gem_object_handle_unreference(obj); | |
104 | mutex_unlock(&dev->struct_mutex); | |
105 | ||
106 | if (ret) | |
107 | return ret; | |
108 | ||
109 | args->handle = handle; | |
110 | ||
111 | return 0; | |
112 | } | |
113 | ||
114 | /** | |
115 | * Reads data from the object referenced by handle. | |
116 | * | |
117 | * On error, the contents of *data are undefined. | |
118 | */ | |
119 | int | |
120 | i915_gem_pread_ioctl(struct drm_device *dev, void *data, | |
121 | struct drm_file *file_priv) | |
122 | { | |
123 | struct drm_i915_gem_pread *args = data; | |
124 | struct drm_gem_object *obj; | |
125 | struct drm_i915_gem_object *obj_priv; | |
126 | ssize_t read; | |
127 | loff_t offset; | |
128 | int ret; | |
129 | ||
130 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); | |
131 | if (obj == NULL) | |
132 | return -EBADF; | |
133 | obj_priv = obj->driver_private; | |
134 | ||
135 | /* Bounds check source. | |
136 | * | |
137 | * XXX: This could use review for overflow issues... | |
138 | */ | |
139 | if (args->offset > obj->size || args->size > obj->size || | |
140 | args->offset + args->size > obj->size) { | |
141 | drm_gem_object_unreference(obj); | |
142 | return -EINVAL; | |
143 | } | |
144 | ||
145 | mutex_lock(&dev->struct_mutex); | |
146 | ||
147 | ret = i915_gem_object_set_domain_range(obj, args->offset, args->size, | |
148 | I915_GEM_DOMAIN_CPU, 0); | |
149 | if (ret != 0) { | |
150 | drm_gem_object_unreference(obj); | |
151 | mutex_unlock(&dev->struct_mutex); | |
e7d22bc3 | 152 | return ret; |
673a394b EA |
153 | } |
154 | ||
155 | offset = args->offset; | |
156 | ||
157 | read = vfs_read(obj->filp, (char __user *)(uintptr_t)args->data_ptr, | |
158 | args->size, &offset); | |
159 | if (read != args->size) { | |
160 | drm_gem_object_unreference(obj); | |
161 | mutex_unlock(&dev->struct_mutex); | |
162 | if (read < 0) | |
163 | return read; | |
164 | else | |
165 | return -EINVAL; | |
166 | } | |
167 | ||
168 | drm_gem_object_unreference(obj); | |
169 | mutex_unlock(&dev->struct_mutex); | |
170 | ||
171 | return 0; | |
172 | } | |
173 | ||
9b7530cc LT |
174 | /* |
175 | * Try to write quickly with an atomic kmap. Return true on success. | |
176 | * | |
177 | * If this fails (which includes a partial write), we'll redo the whole | |
178 | * thing with the slow version. | |
179 | * | |
180 | * This is a workaround for the low performance of iounmap (approximate | |
181 | * 10% cpu cost on normal 3D workloads). kmap_atomic on HIGHMEM kernels | |
182 | * happens to let us map card memory without taking IPIs. When the vmap | |
183 | * rework lands we should be able to dump this hack. | |
184 | */ | |
185 | static inline int fast_user_write(unsigned long pfn, char __user *user_data, int l) | |
186 | { | |
187 | #ifdef CONFIG_HIGHMEM | |
188 | unsigned long unwritten; | |
189 | char *vaddr_atomic; | |
190 | ||
191 | vaddr_atomic = kmap_atomic_pfn(pfn, KM_USER0); | |
192 | #if WATCH_PWRITE | |
193 | DRM_INFO("pwrite i %d o %d l %d pfn %ld vaddr %p\n", | |
194 | i, o, l, pfn, vaddr_atomic); | |
195 | #endif | |
196 | unwritten = __copy_from_user_inatomic_nocache(vaddr_atomic + o, user_data, l); | |
197 | kunmap_atomic(vaddr_atomic, KM_USER0); | |
198 | return !unwritten; | |
199 | #else | |
200 | return 0; | |
201 | #endif | |
202 | } | |
203 | ||
673a394b EA |
204 | static int |
205 | i915_gem_gtt_pwrite(struct drm_device *dev, struct drm_gem_object *obj, | |
206 | struct drm_i915_gem_pwrite *args, | |
207 | struct drm_file *file_priv) | |
208 | { | |
209 | struct drm_i915_gem_object *obj_priv = obj->driver_private; | |
210 | ssize_t remain; | |
211 | loff_t offset; | |
212 | char __user *user_data; | |
673a394b | 213 | int ret = 0; |
673a394b EA |
214 | |
215 | user_data = (char __user *) (uintptr_t) args->data_ptr; | |
216 | remain = args->size; | |
217 | if (!access_ok(VERIFY_READ, user_data, remain)) | |
218 | return -EFAULT; | |
219 | ||
220 | ||
221 | mutex_lock(&dev->struct_mutex); | |
222 | ret = i915_gem_object_pin(obj, 0); | |
223 | if (ret) { | |
224 | mutex_unlock(&dev->struct_mutex); | |
225 | return ret; | |
226 | } | |
227 | ret = i915_gem_set_domain(obj, file_priv, | |
228 | I915_GEM_DOMAIN_GTT, I915_GEM_DOMAIN_GTT); | |
229 | if (ret) | |
230 | goto fail; | |
231 | ||
232 | obj_priv = obj->driver_private; | |
233 | offset = obj_priv->gtt_offset + args->offset; | |
234 | obj_priv->dirty = 1; | |
235 | ||
236 | while (remain > 0) { | |
9b7530cc LT |
237 | unsigned long pfn; |
238 | int i, o, l; | |
239 | ||
673a394b EA |
240 | /* Operation in this page |
241 | * | |
242 | * i = page number | |
243 | * o = offset within page | |
244 | * l = bytes to copy | |
245 | */ | |
246 | i = offset >> PAGE_SHIFT; | |
247 | o = offset & (PAGE_SIZE-1); | |
248 | l = remain; | |
249 | if ((o + l) > PAGE_SIZE) | |
250 | l = PAGE_SIZE - o; | |
251 | ||
252 | pfn = (dev->agp->base >> PAGE_SHIFT) + i; | |
253 | ||
9b7530cc LT |
254 | if (!fast_user_write(pfn, user_data, l)) { |
255 | unsigned long unwritten; | |
256 | char __iomem *vaddr; | |
673a394b | 257 | |
bd88ee4c | 258 | vaddr = ioremap_wc(pfn << PAGE_SHIFT, PAGE_SIZE); |
673a394b EA |
259 | #if WATCH_PWRITE |
260 | DRM_INFO("pwrite slow i %d o %d l %d " | |
261 | "pfn %ld vaddr %p\n", | |
262 | i, o, l, pfn, vaddr); | |
263 | #endif | |
264 | if (vaddr == NULL) { | |
265 | ret = -EFAULT; | |
266 | goto fail; | |
267 | } | |
268 | unwritten = __copy_from_user(vaddr + o, user_data, l); | |
269 | #if WATCH_PWRITE | |
270 | DRM_INFO("unwritten %ld\n", unwritten); | |
271 | #endif | |
272 | iounmap(vaddr); | |
273 | if (unwritten) { | |
274 | ret = -EFAULT; | |
275 | goto fail; | |
276 | } | |
277 | } | |
278 | ||
279 | remain -= l; | |
280 | user_data += l; | |
281 | offset += l; | |
282 | } | |
283 | #if WATCH_PWRITE && 1 | |
284 | i915_gem_clflush_object(obj); | |
285 | i915_gem_dump_object(obj, args->offset + args->size, __func__, ~0); | |
286 | i915_gem_clflush_object(obj); | |
287 | #endif | |
288 | ||
289 | fail: | |
290 | i915_gem_object_unpin(obj); | |
291 | mutex_unlock(&dev->struct_mutex); | |
292 | ||
293 | return ret; | |
294 | } | |
295 | ||
3043c60c | 296 | static int |
673a394b EA |
297 | i915_gem_shmem_pwrite(struct drm_device *dev, struct drm_gem_object *obj, |
298 | struct drm_i915_gem_pwrite *args, | |
299 | struct drm_file *file_priv) | |
300 | { | |
301 | int ret; | |
302 | loff_t offset; | |
303 | ssize_t written; | |
304 | ||
305 | mutex_lock(&dev->struct_mutex); | |
306 | ||
307 | ret = i915_gem_set_domain(obj, file_priv, | |
308 | I915_GEM_DOMAIN_CPU, I915_GEM_DOMAIN_CPU); | |
309 | if (ret) { | |
310 | mutex_unlock(&dev->struct_mutex); | |
311 | return ret; | |
312 | } | |
313 | ||
314 | offset = args->offset; | |
315 | ||
316 | written = vfs_write(obj->filp, | |
317 | (char __user *)(uintptr_t) args->data_ptr, | |
318 | args->size, &offset); | |
319 | if (written != args->size) { | |
320 | mutex_unlock(&dev->struct_mutex); | |
321 | if (written < 0) | |
322 | return written; | |
323 | else | |
324 | return -EINVAL; | |
325 | } | |
326 | ||
327 | mutex_unlock(&dev->struct_mutex); | |
328 | ||
329 | return 0; | |
330 | } | |
331 | ||
332 | /** | |
333 | * Writes data to the object referenced by handle. | |
334 | * | |
335 | * On error, the contents of the buffer that were to be modified are undefined. | |
336 | */ | |
337 | int | |
338 | i915_gem_pwrite_ioctl(struct drm_device *dev, void *data, | |
339 | struct drm_file *file_priv) | |
340 | { | |
341 | struct drm_i915_gem_pwrite *args = data; | |
342 | struct drm_gem_object *obj; | |
343 | struct drm_i915_gem_object *obj_priv; | |
344 | int ret = 0; | |
345 | ||
346 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); | |
347 | if (obj == NULL) | |
348 | return -EBADF; | |
349 | obj_priv = obj->driver_private; | |
350 | ||
351 | /* Bounds check destination. | |
352 | * | |
353 | * XXX: This could use review for overflow issues... | |
354 | */ | |
355 | if (args->offset > obj->size || args->size > obj->size || | |
356 | args->offset + args->size > obj->size) { | |
357 | drm_gem_object_unreference(obj); | |
358 | return -EINVAL; | |
359 | } | |
360 | ||
361 | /* We can only do the GTT pwrite on untiled buffers, as otherwise | |
362 | * it would end up going through the fenced access, and we'll get | |
363 | * different detiling behavior between reading and writing. | |
364 | * pread/pwrite currently are reading and writing from the CPU | |
365 | * perspective, requiring manual detiling by the client. | |
366 | */ | |
367 | if (obj_priv->tiling_mode == I915_TILING_NONE && | |
368 | dev->gtt_total != 0) | |
369 | ret = i915_gem_gtt_pwrite(dev, obj, args, file_priv); | |
370 | else | |
371 | ret = i915_gem_shmem_pwrite(dev, obj, args, file_priv); | |
372 | ||
373 | #if WATCH_PWRITE | |
374 | if (ret) | |
375 | DRM_INFO("pwrite failed %d\n", ret); | |
376 | #endif | |
377 | ||
378 | drm_gem_object_unreference(obj); | |
379 | ||
380 | return ret; | |
381 | } | |
382 | ||
383 | /** | |
384 | * Called when user space prepares to use an object | |
385 | */ | |
386 | int | |
387 | i915_gem_set_domain_ioctl(struct drm_device *dev, void *data, | |
388 | struct drm_file *file_priv) | |
389 | { | |
390 | struct drm_i915_gem_set_domain *args = data; | |
391 | struct drm_gem_object *obj; | |
392 | int ret; | |
393 | ||
394 | if (!(dev->driver->driver_features & DRIVER_GEM)) | |
395 | return -ENODEV; | |
396 | ||
397 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); | |
398 | if (obj == NULL) | |
399 | return -EBADF; | |
400 | ||
401 | mutex_lock(&dev->struct_mutex); | |
402 | #if WATCH_BUF | |
403 | DRM_INFO("set_domain_ioctl %p(%d), %08x %08x\n", | |
404 | obj, obj->size, args->read_domains, args->write_domain); | |
405 | #endif | |
406 | ret = i915_gem_set_domain(obj, file_priv, | |
407 | args->read_domains, args->write_domain); | |
408 | drm_gem_object_unreference(obj); | |
409 | mutex_unlock(&dev->struct_mutex); | |
410 | return ret; | |
411 | } | |
412 | ||
413 | /** | |
414 | * Called when user space has done writes to this buffer | |
415 | */ | |
416 | int | |
417 | i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data, | |
418 | struct drm_file *file_priv) | |
419 | { | |
420 | struct drm_i915_gem_sw_finish *args = data; | |
421 | struct drm_gem_object *obj; | |
422 | struct drm_i915_gem_object *obj_priv; | |
423 | int ret = 0; | |
424 | ||
425 | if (!(dev->driver->driver_features & DRIVER_GEM)) | |
426 | return -ENODEV; | |
427 | ||
428 | mutex_lock(&dev->struct_mutex); | |
429 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); | |
430 | if (obj == NULL) { | |
431 | mutex_unlock(&dev->struct_mutex); | |
432 | return -EBADF; | |
433 | } | |
434 | ||
435 | #if WATCH_BUF | |
436 | DRM_INFO("%s: sw_finish %d (%p %d)\n", | |
437 | __func__, args->handle, obj, obj->size); | |
438 | #endif | |
439 | obj_priv = obj->driver_private; | |
440 | ||
441 | /* Pinned buffers may be scanout, so flush the cache */ | |
442 | if ((obj->write_domain & I915_GEM_DOMAIN_CPU) && obj_priv->pin_count) { | |
443 | i915_gem_clflush_object(obj); | |
444 | drm_agp_chipset_flush(dev); | |
445 | } | |
446 | drm_gem_object_unreference(obj); | |
447 | mutex_unlock(&dev->struct_mutex); | |
448 | return ret; | |
449 | } | |
450 | ||
451 | /** | |
452 | * Maps the contents of an object, returning the address it is mapped | |
453 | * into. | |
454 | * | |
455 | * While the mapping holds a reference on the contents of the object, it doesn't | |
456 | * imply a ref on the object itself. | |
457 | */ | |
458 | int | |
459 | i915_gem_mmap_ioctl(struct drm_device *dev, void *data, | |
460 | struct drm_file *file_priv) | |
461 | { | |
462 | struct drm_i915_gem_mmap *args = data; | |
463 | struct drm_gem_object *obj; | |
464 | loff_t offset; | |
465 | unsigned long addr; | |
466 | ||
467 | if (!(dev->driver->driver_features & DRIVER_GEM)) | |
468 | return -ENODEV; | |
469 | ||
470 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); | |
471 | if (obj == NULL) | |
472 | return -EBADF; | |
473 | ||
474 | offset = args->offset; | |
475 | ||
476 | down_write(¤t->mm->mmap_sem); | |
477 | addr = do_mmap(obj->filp, 0, args->size, | |
478 | PROT_READ | PROT_WRITE, MAP_SHARED, | |
479 | args->offset); | |
480 | up_write(¤t->mm->mmap_sem); | |
481 | mutex_lock(&dev->struct_mutex); | |
482 | drm_gem_object_unreference(obj); | |
483 | mutex_unlock(&dev->struct_mutex); | |
484 | if (IS_ERR((void *)addr)) | |
485 | return addr; | |
486 | ||
487 | args->addr_ptr = (uint64_t) addr; | |
488 | ||
489 | return 0; | |
490 | } | |
491 | ||
492 | static void | |
493 | i915_gem_object_free_page_list(struct drm_gem_object *obj) | |
494 | { | |
495 | struct drm_i915_gem_object *obj_priv = obj->driver_private; | |
496 | int page_count = obj->size / PAGE_SIZE; | |
497 | int i; | |
498 | ||
499 | if (obj_priv->page_list == NULL) | |
500 | return; | |
501 | ||
502 | ||
503 | for (i = 0; i < page_count; i++) | |
504 | if (obj_priv->page_list[i] != NULL) { | |
505 | if (obj_priv->dirty) | |
506 | set_page_dirty(obj_priv->page_list[i]); | |
507 | mark_page_accessed(obj_priv->page_list[i]); | |
508 | page_cache_release(obj_priv->page_list[i]); | |
509 | } | |
510 | obj_priv->dirty = 0; | |
511 | ||
512 | drm_free(obj_priv->page_list, | |
513 | page_count * sizeof(struct page *), | |
514 | DRM_MEM_DRIVER); | |
515 | obj_priv->page_list = NULL; | |
516 | } | |
517 | ||
518 | static void | |
519 | i915_gem_object_move_to_active(struct drm_gem_object *obj) | |
520 | { | |
521 | struct drm_device *dev = obj->dev; | |
522 | drm_i915_private_t *dev_priv = dev->dev_private; | |
523 | struct drm_i915_gem_object *obj_priv = obj->driver_private; | |
524 | ||
525 | /* Add a reference if we're newly entering the active list. */ | |
526 | if (!obj_priv->active) { | |
527 | drm_gem_object_reference(obj); | |
528 | obj_priv->active = 1; | |
529 | } | |
530 | /* Move from whatever list we were on to the tail of execution. */ | |
531 | list_move_tail(&obj_priv->list, | |
532 | &dev_priv->mm.active_list); | |
533 | } | |
534 | ||
535 | ||
536 | static void | |
537 | i915_gem_object_move_to_inactive(struct drm_gem_object *obj) | |
538 | { | |
539 | struct drm_device *dev = obj->dev; | |
540 | drm_i915_private_t *dev_priv = dev->dev_private; | |
541 | struct drm_i915_gem_object *obj_priv = obj->driver_private; | |
542 | ||
543 | i915_verify_inactive(dev, __FILE__, __LINE__); | |
544 | if (obj_priv->pin_count != 0) | |
545 | list_del_init(&obj_priv->list); | |
546 | else | |
547 | list_move_tail(&obj_priv->list, &dev_priv->mm.inactive_list); | |
548 | ||
549 | if (obj_priv->active) { | |
550 | obj_priv->active = 0; | |
551 | drm_gem_object_unreference(obj); | |
552 | } | |
553 | i915_verify_inactive(dev, __FILE__, __LINE__); | |
554 | } | |
555 | ||
556 | /** | |
557 | * Creates a new sequence number, emitting a write of it to the status page | |
558 | * plus an interrupt, which will trigger i915_user_interrupt_handler. | |
559 | * | |
560 | * Must be called with struct_lock held. | |
561 | * | |
562 | * Returned sequence numbers are nonzero on success. | |
563 | */ | |
564 | static uint32_t | |
565 | i915_add_request(struct drm_device *dev, uint32_t flush_domains) | |
566 | { | |
567 | drm_i915_private_t *dev_priv = dev->dev_private; | |
568 | struct drm_i915_gem_request *request; | |
569 | uint32_t seqno; | |
570 | int was_empty; | |
571 | RING_LOCALS; | |
572 | ||
573 | request = drm_calloc(1, sizeof(*request), DRM_MEM_DRIVER); | |
574 | if (request == NULL) | |
575 | return 0; | |
576 | ||
577 | /* Grab the seqno we're going to make this request be, and bump the | |
578 | * next (skipping 0 so it can be the reserved no-seqno value). | |
579 | */ | |
580 | seqno = dev_priv->mm.next_gem_seqno; | |
581 | dev_priv->mm.next_gem_seqno++; | |
582 | if (dev_priv->mm.next_gem_seqno == 0) | |
583 | dev_priv->mm.next_gem_seqno++; | |
584 | ||
585 | BEGIN_LP_RING(4); | |
586 | OUT_RING(MI_STORE_DWORD_INDEX); | |
587 | OUT_RING(I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT); | |
588 | OUT_RING(seqno); | |
589 | ||
590 | OUT_RING(MI_USER_INTERRUPT); | |
591 | ADVANCE_LP_RING(); | |
592 | ||
593 | DRM_DEBUG("%d\n", seqno); | |
594 | ||
595 | request->seqno = seqno; | |
596 | request->emitted_jiffies = jiffies; | |
597 | request->flush_domains = flush_domains; | |
598 | was_empty = list_empty(&dev_priv->mm.request_list); | |
599 | list_add_tail(&request->list, &dev_priv->mm.request_list); | |
600 | ||
6dbe2772 | 601 | if (was_empty && !dev_priv->mm.suspended) |
673a394b EA |
602 | schedule_delayed_work(&dev_priv->mm.retire_work, HZ); |
603 | return seqno; | |
604 | } | |
605 | ||
606 | /** | |
607 | * Command execution barrier | |
608 | * | |
609 | * Ensures that all commands in the ring are finished | |
610 | * before signalling the CPU | |
611 | */ | |
3043c60c | 612 | static uint32_t |
673a394b EA |
613 | i915_retire_commands(struct drm_device *dev) |
614 | { | |
615 | drm_i915_private_t *dev_priv = dev->dev_private; | |
616 | uint32_t cmd = MI_FLUSH | MI_NO_WRITE_FLUSH; | |
617 | uint32_t flush_domains = 0; | |
618 | RING_LOCALS; | |
619 | ||
620 | /* The sampler always gets flushed on i965 (sigh) */ | |
621 | if (IS_I965G(dev)) | |
622 | flush_domains |= I915_GEM_DOMAIN_SAMPLER; | |
623 | BEGIN_LP_RING(2); | |
624 | OUT_RING(cmd); | |
625 | OUT_RING(0); /* noop */ | |
626 | ADVANCE_LP_RING(); | |
627 | return flush_domains; | |
628 | } | |
629 | ||
630 | /** | |
631 | * Moves buffers associated only with the given active seqno from the active | |
632 | * to inactive list, potentially freeing them. | |
633 | */ | |
634 | static void | |
635 | i915_gem_retire_request(struct drm_device *dev, | |
636 | struct drm_i915_gem_request *request) | |
637 | { | |
638 | drm_i915_private_t *dev_priv = dev->dev_private; | |
639 | ||
640 | /* Move any buffers on the active list that are no longer referenced | |
641 | * by the ringbuffer to the flushing/inactive lists as appropriate. | |
642 | */ | |
643 | while (!list_empty(&dev_priv->mm.active_list)) { | |
644 | struct drm_gem_object *obj; | |
645 | struct drm_i915_gem_object *obj_priv; | |
646 | ||
647 | obj_priv = list_first_entry(&dev_priv->mm.active_list, | |
648 | struct drm_i915_gem_object, | |
649 | list); | |
650 | obj = obj_priv->obj; | |
651 | ||
652 | /* If the seqno being retired doesn't match the oldest in the | |
653 | * list, then the oldest in the list must still be newer than | |
654 | * this seqno. | |
655 | */ | |
656 | if (obj_priv->last_rendering_seqno != request->seqno) | |
657 | return; | |
658 | #if WATCH_LRU | |
659 | DRM_INFO("%s: retire %d moves to inactive list %p\n", | |
660 | __func__, request->seqno, obj); | |
661 | #endif | |
662 | ||
663 | if (obj->write_domain != 0) { | |
664 | list_move_tail(&obj_priv->list, | |
665 | &dev_priv->mm.flushing_list); | |
666 | } else { | |
667 | i915_gem_object_move_to_inactive(obj); | |
668 | } | |
669 | } | |
670 | ||
671 | if (request->flush_domains != 0) { | |
672 | struct drm_i915_gem_object *obj_priv, *next; | |
673 | ||
674 | /* Clear the write domain and activity from any buffers | |
675 | * that are just waiting for a flush matching the one retired. | |
676 | */ | |
677 | list_for_each_entry_safe(obj_priv, next, | |
678 | &dev_priv->mm.flushing_list, list) { | |
679 | struct drm_gem_object *obj = obj_priv->obj; | |
680 | ||
681 | if (obj->write_domain & request->flush_domains) { | |
682 | obj->write_domain = 0; | |
683 | i915_gem_object_move_to_inactive(obj); | |
684 | } | |
685 | } | |
686 | ||
687 | } | |
688 | } | |
689 | ||
690 | /** | |
691 | * Returns true if seq1 is later than seq2. | |
692 | */ | |
693 | static int | |
694 | i915_seqno_passed(uint32_t seq1, uint32_t seq2) | |
695 | { | |
696 | return (int32_t)(seq1 - seq2) >= 0; | |
697 | } | |
698 | ||
699 | uint32_t | |
700 | i915_get_gem_seqno(struct drm_device *dev) | |
701 | { | |
702 | drm_i915_private_t *dev_priv = dev->dev_private; | |
703 | ||
704 | return READ_HWSP(dev_priv, I915_GEM_HWS_INDEX); | |
705 | } | |
706 | ||
707 | /** | |
708 | * This function clears the request list as sequence numbers are passed. | |
709 | */ | |
710 | void | |
711 | i915_gem_retire_requests(struct drm_device *dev) | |
712 | { | |
713 | drm_i915_private_t *dev_priv = dev->dev_private; | |
714 | uint32_t seqno; | |
715 | ||
716 | seqno = i915_get_gem_seqno(dev); | |
717 | ||
718 | while (!list_empty(&dev_priv->mm.request_list)) { | |
719 | struct drm_i915_gem_request *request; | |
720 | uint32_t retiring_seqno; | |
721 | ||
722 | request = list_first_entry(&dev_priv->mm.request_list, | |
723 | struct drm_i915_gem_request, | |
724 | list); | |
725 | retiring_seqno = request->seqno; | |
726 | ||
727 | if (i915_seqno_passed(seqno, retiring_seqno) || | |
728 | dev_priv->mm.wedged) { | |
729 | i915_gem_retire_request(dev, request); | |
730 | ||
731 | list_del(&request->list); | |
732 | drm_free(request, sizeof(*request), DRM_MEM_DRIVER); | |
733 | } else | |
734 | break; | |
735 | } | |
736 | } | |
737 | ||
738 | void | |
739 | i915_gem_retire_work_handler(struct work_struct *work) | |
740 | { | |
741 | drm_i915_private_t *dev_priv; | |
742 | struct drm_device *dev; | |
743 | ||
744 | dev_priv = container_of(work, drm_i915_private_t, | |
745 | mm.retire_work.work); | |
746 | dev = dev_priv->dev; | |
747 | ||
748 | mutex_lock(&dev->struct_mutex); | |
749 | i915_gem_retire_requests(dev); | |
6dbe2772 KP |
750 | if (!dev_priv->mm.suspended && |
751 | !list_empty(&dev_priv->mm.request_list)) | |
673a394b EA |
752 | schedule_delayed_work(&dev_priv->mm.retire_work, HZ); |
753 | mutex_unlock(&dev->struct_mutex); | |
754 | } | |
755 | ||
756 | /** | |
757 | * Waits for a sequence number to be signaled, and cleans up the | |
758 | * request and object lists appropriately for that event. | |
759 | */ | |
3043c60c | 760 | static int |
673a394b EA |
761 | i915_wait_request(struct drm_device *dev, uint32_t seqno) |
762 | { | |
763 | drm_i915_private_t *dev_priv = dev->dev_private; | |
764 | int ret = 0; | |
765 | ||
766 | BUG_ON(seqno == 0); | |
767 | ||
768 | if (!i915_seqno_passed(i915_get_gem_seqno(dev), seqno)) { | |
769 | dev_priv->mm.waiting_gem_seqno = seqno; | |
770 | i915_user_irq_get(dev); | |
771 | ret = wait_event_interruptible(dev_priv->irq_queue, | |
772 | i915_seqno_passed(i915_get_gem_seqno(dev), | |
773 | seqno) || | |
774 | dev_priv->mm.wedged); | |
775 | i915_user_irq_put(dev); | |
776 | dev_priv->mm.waiting_gem_seqno = 0; | |
777 | } | |
778 | if (dev_priv->mm.wedged) | |
779 | ret = -EIO; | |
780 | ||
781 | if (ret && ret != -ERESTARTSYS) | |
782 | DRM_ERROR("%s returns %d (awaiting %d at %d)\n", | |
783 | __func__, ret, seqno, i915_get_gem_seqno(dev)); | |
784 | ||
785 | /* Directly dispatch request retiring. While we have the work queue | |
786 | * to handle this, the waiter on a request often wants an associated | |
787 | * buffer to have made it to the inactive list, and we would need | |
788 | * a separate wait queue to handle that. | |
789 | */ | |
790 | if (ret == 0) | |
791 | i915_gem_retire_requests(dev); | |
792 | ||
793 | return ret; | |
794 | } | |
795 | ||
796 | static void | |
797 | i915_gem_flush(struct drm_device *dev, | |
798 | uint32_t invalidate_domains, | |
799 | uint32_t flush_domains) | |
800 | { | |
801 | drm_i915_private_t *dev_priv = dev->dev_private; | |
802 | uint32_t cmd; | |
803 | RING_LOCALS; | |
804 | ||
805 | #if WATCH_EXEC | |
806 | DRM_INFO("%s: invalidate %08x flush %08x\n", __func__, | |
807 | invalidate_domains, flush_domains); | |
808 | #endif | |
809 | ||
810 | if (flush_domains & I915_GEM_DOMAIN_CPU) | |
811 | drm_agp_chipset_flush(dev); | |
812 | ||
813 | if ((invalidate_domains | flush_domains) & ~(I915_GEM_DOMAIN_CPU | | |
814 | I915_GEM_DOMAIN_GTT)) { | |
815 | /* | |
816 | * read/write caches: | |
817 | * | |
818 | * I915_GEM_DOMAIN_RENDER is always invalidated, but is | |
819 | * only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is | |
820 | * also flushed at 2d versus 3d pipeline switches. | |
821 | * | |
822 | * read-only caches: | |
823 | * | |
824 | * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if | |
825 | * MI_READ_FLUSH is set, and is always flushed on 965. | |
826 | * | |
827 | * I915_GEM_DOMAIN_COMMAND may not exist? | |
828 | * | |
829 | * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is | |
830 | * invalidated when MI_EXE_FLUSH is set. | |
831 | * | |
832 | * I915_GEM_DOMAIN_VERTEX, which exists on 965, is | |
833 | * invalidated with every MI_FLUSH. | |
834 | * | |
835 | * TLBs: | |
836 | * | |
837 | * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND | |
838 | * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and | |
839 | * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER | |
840 | * are flushed at any MI_FLUSH. | |
841 | */ | |
842 | ||
843 | cmd = MI_FLUSH | MI_NO_WRITE_FLUSH; | |
844 | if ((invalidate_domains|flush_domains) & | |
845 | I915_GEM_DOMAIN_RENDER) | |
846 | cmd &= ~MI_NO_WRITE_FLUSH; | |
847 | if (!IS_I965G(dev)) { | |
848 | /* | |
849 | * On the 965, the sampler cache always gets flushed | |
850 | * and this bit is reserved. | |
851 | */ | |
852 | if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER) | |
853 | cmd |= MI_READ_FLUSH; | |
854 | } | |
855 | if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION) | |
856 | cmd |= MI_EXE_FLUSH; | |
857 | ||
858 | #if WATCH_EXEC | |
859 | DRM_INFO("%s: queue flush %08x to ring\n", __func__, cmd); | |
860 | #endif | |
861 | BEGIN_LP_RING(2); | |
862 | OUT_RING(cmd); | |
863 | OUT_RING(0); /* noop */ | |
864 | ADVANCE_LP_RING(); | |
865 | } | |
866 | } | |
867 | ||
868 | /** | |
869 | * Ensures that all rendering to the object has completed and the object is | |
870 | * safe to unbind from the GTT or access from the CPU. | |
871 | */ | |
872 | static int | |
873 | i915_gem_object_wait_rendering(struct drm_gem_object *obj) | |
874 | { | |
875 | struct drm_device *dev = obj->dev; | |
876 | struct drm_i915_gem_object *obj_priv = obj->driver_private; | |
877 | int ret; | |
878 | ||
879 | /* If there are writes queued to the buffer, flush and | |
880 | * create a new seqno to wait for. | |
881 | */ | |
882 | if (obj->write_domain & ~(I915_GEM_DOMAIN_CPU|I915_GEM_DOMAIN_GTT)) { | |
883 | uint32_t write_domain = obj->write_domain; | |
884 | #if WATCH_BUF | |
885 | DRM_INFO("%s: flushing object %p from write domain %08x\n", | |
886 | __func__, obj, write_domain); | |
887 | #endif | |
888 | i915_gem_flush(dev, 0, write_domain); | |
889 | ||
890 | i915_gem_object_move_to_active(obj); | |
891 | obj_priv->last_rendering_seqno = i915_add_request(dev, | |
892 | write_domain); | |
893 | BUG_ON(obj_priv->last_rendering_seqno == 0); | |
894 | #if WATCH_LRU | |
895 | DRM_INFO("%s: flush moves to exec list %p\n", __func__, obj); | |
896 | #endif | |
897 | } | |
898 | ||
899 | /* If there is rendering queued on the buffer being evicted, wait for | |
900 | * it. | |
901 | */ | |
902 | if (obj_priv->active) { | |
903 | #if WATCH_BUF | |
904 | DRM_INFO("%s: object %p wait for seqno %08x\n", | |
905 | __func__, obj, obj_priv->last_rendering_seqno); | |
906 | #endif | |
907 | ret = i915_wait_request(dev, obj_priv->last_rendering_seqno); | |
908 | if (ret != 0) | |
909 | return ret; | |
910 | } | |
911 | ||
912 | return 0; | |
913 | } | |
914 | ||
915 | /** | |
916 | * Unbinds an object from the GTT aperture. | |
917 | */ | |
918 | static int | |
919 | i915_gem_object_unbind(struct drm_gem_object *obj) | |
920 | { | |
921 | struct drm_device *dev = obj->dev; | |
922 | struct drm_i915_gem_object *obj_priv = obj->driver_private; | |
923 | int ret = 0; | |
924 | ||
925 | #if WATCH_BUF | |
926 | DRM_INFO("%s:%d %p\n", __func__, __LINE__, obj); | |
927 | DRM_INFO("gtt_space %p\n", obj_priv->gtt_space); | |
928 | #endif | |
929 | if (obj_priv->gtt_space == NULL) | |
930 | return 0; | |
931 | ||
932 | if (obj_priv->pin_count != 0) { | |
933 | DRM_ERROR("Attempting to unbind pinned buffer\n"); | |
934 | return -EINVAL; | |
935 | } | |
936 | ||
937 | /* Wait for any rendering to complete | |
938 | */ | |
939 | ret = i915_gem_object_wait_rendering(obj); | |
940 | if (ret) { | |
941 | DRM_ERROR("wait_rendering failed: %d\n", ret); | |
942 | return ret; | |
943 | } | |
944 | ||
945 | /* Move the object to the CPU domain to ensure that | |
946 | * any possible CPU writes while it's not in the GTT | |
947 | * are flushed when we go to remap it. This will | |
948 | * also ensure that all pending GPU writes are finished | |
949 | * before we unbind. | |
950 | */ | |
951 | ret = i915_gem_object_set_domain(obj, I915_GEM_DOMAIN_CPU, | |
952 | I915_GEM_DOMAIN_CPU); | |
953 | if (ret) { | |
954 | DRM_ERROR("set_domain failed: %d\n", ret); | |
955 | return ret; | |
956 | } | |
957 | ||
958 | if (obj_priv->agp_mem != NULL) { | |
959 | drm_unbind_agp(obj_priv->agp_mem); | |
960 | drm_free_agp(obj_priv->agp_mem, obj->size / PAGE_SIZE); | |
961 | obj_priv->agp_mem = NULL; | |
962 | } | |
963 | ||
964 | BUG_ON(obj_priv->active); | |
965 | ||
966 | i915_gem_object_free_page_list(obj); | |
967 | ||
968 | if (obj_priv->gtt_space) { | |
969 | atomic_dec(&dev->gtt_count); | |
970 | atomic_sub(obj->size, &dev->gtt_memory); | |
971 | ||
972 | drm_mm_put_block(obj_priv->gtt_space); | |
973 | obj_priv->gtt_space = NULL; | |
974 | } | |
975 | ||
976 | /* Remove ourselves from the LRU list if present. */ | |
977 | if (!list_empty(&obj_priv->list)) | |
978 | list_del_init(&obj_priv->list); | |
979 | ||
980 | return 0; | |
981 | } | |
982 | ||
983 | static int | |
984 | i915_gem_evict_something(struct drm_device *dev) | |
985 | { | |
986 | drm_i915_private_t *dev_priv = dev->dev_private; | |
987 | struct drm_gem_object *obj; | |
988 | struct drm_i915_gem_object *obj_priv; | |
989 | int ret = 0; | |
990 | ||
991 | for (;;) { | |
992 | /* If there's an inactive buffer available now, grab it | |
993 | * and be done. | |
994 | */ | |
995 | if (!list_empty(&dev_priv->mm.inactive_list)) { | |
996 | obj_priv = list_first_entry(&dev_priv->mm.inactive_list, | |
997 | struct drm_i915_gem_object, | |
998 | list); | |
999 | obj = obj_priv->obj; | |
1000 | BUG_ON(obj_priv->pin_count != 0); | |
1001 | #if WATCH_LRU | |
1002 | DRM_INFO("%s: evicting %p\n", __func__, obj); | |
1003 | #endif | |
1004 | BUG_ON(obj_priv->active); | |
1005 | ||
1006 | /* Wait on the rendering and unbind the buffer. */ | |
1007 | ret = i915_gem_object_unbind(obj); | |
1008 | break; | |
1009 | } | |
1010 | ||
1011 | /* If we didn't get anything, but the ring is still processing | |
1012 | * things, wait for one of those things to finish and hopefully | |
1013 | * leave us a buffer to evict. | |
1014 | */ | |
1015 | if (!list_empty(&dev_priv->mm.request_list)) { | |
1016 | struct drm_i915_gem_request *request; | |
1017 | ||
1018 | request = list_first_entry(&dev_priv->mm.request_list, | |
1019 | struct drm_i915_gem_request, | |
1020 | list); | |
1021 | ||
1022 | ret = i915_wait_request(dev, request->seqno); | |
1023 | if (ret) | |
1024 | break; | |
1025 | ||
1026 | /* if waiting caused an object to become inactive, | |
1027 | * then loop around and wait for it. Otherwise, we | |
1028 | * assume that waiting freed and unbound something, | |
1029 | * so there should now be some space in the GTT | |
1030 | */ | |
1031 | if (!list_empty(&dev_priv->mm.inactive_list)) | |
1032 | continue; | |
1033 | break; | |
1034 | } | |
1035 | ||
1036 | /* If we didn't have anything on the request list but there | |
1037 | * are buffers awaiting a flush, emit one and try again. | |
1038 | * When we wait on it, those buffers waiting for that flush | |
1039 | * will get moved to inactive. | |
1040 | */ | |
1041 | if (!list_empty(&dev_priv->mm.flushing_list)) { | |
1042 | obj_priv = list_first_entry(&dev_priv->mm.flushing_list, | |
1043 | struct drm_i915_gem_object, | |
1044 | list); | |
1045 | obj = obj_priv->obj; | |
1046 | ||
1047 | i915_gem_flush(dev, | |
1048 | obj->write_domain, | |
1049 | obj->write_domain); | |
1050 | i915_add_request(dev, obj->write_domain); | |
1051 | ||
1052 | obj = NULL; | |
1053 | continue; | |
1054 | } | |
1055 | ||
1056 | DRM_ERROR("inactive empty %d request empty %d " | |
1057 | "flushing empty %d\n", | |
1058 | list_empty(&dev_priv->mm.inactive_list), | |
1059 | list_empty(&dev_priv->mm.request_list), | |
1060 | list_empty(&dev_priv->mm.flushing_list)); | |
1061 | /* If we didn't do any of the above, there's nothing to be done | |
1062 | * and we just can't fit it in. | |
1063 | */ | |
1064 | return -ENOMEM; | |
1065 | } | |
1066 | return ret; | |
1067 | } | |
1068 | ||
1069 | static int | |
1070 | i915_gem_object_get_page_list(struct drm_gem_object *obj) | |
1071 | { | |
1072 | struct drm_i915_gem_object *obj_priv = obj->driver_private; | |
1073 | int page_count, i; | |
1074 | struct address_space *mapping; | |
1075 | struct inode *inode; | |
1076 | struct page *page; | |
1077 | int ret; | |
1078 | ||
1079 | if (obj_priv->page_list) | |
1080 | return 0; | |
1081 | ||
1082 | /* Get the list of pages out of our struct file. They'll be pinned | |
1083 | * at this point until we release them. | |
1084 | */ | |
1085 | page_count = obj->size / PAGE_SIZE; | |
1086 | BUG_ON(obj_priv->page_list != NULL); | |
1087 | obj_priv->page_list = drm_calloc(page_count, sizeof(struct page *), | |
1088 | DRM_MEM_DRIVER); | |
1089 | if (obj_priv->page_list == NULL) { | |
1090 | DRM_ERROR("Faled to allocate page list\n"); | |
1091 | return -ENOMEM; | |
1092 | } | |
1093 | ||
1094 | inode = obj->filp->f_path.dentry->d_inode; | |
1095 | mapping = inode->i_mapping; | |
1096 | for (i = 0; i < page_count; i++) { | |
1097 | page = read_mapping_page(mapping, i, NULL); | |
1098 | if (IS_ERR(page)) { | |
1099 | ret = PTR_ERR(page); | |
1100 | DRM_ERROR("read_mapping_page failed: %d\n", ret); | |
1101 | i915_gem_object_free_page_list(obj); | |
1102 | return ret; | |
1103 | } | |
1104 | obj_priv->page_list[i] = page; | |
1105 | } | |
1106 | return 0; | |
1107 | } | |
1108 | ||
1109 | /** | |
1110 | * Finds free space in the GTT aperture and binds the object there. | |
1111 | */ | |
1112 | static int | |
1113 | i915_gem_object_bind_to_gtt(struct drm_gem_object *obj, unsigned alignment) | |
1114 | { | |
1115 | struct drm_device *dev = obj->dev; | |
1116 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1117 | struct drm_i915_gem_object *obj_priv = obj->driver_private; | |
1118 | struct drm_mm_node *free_space; | |
1119 | int page_count, ret; | |
1120 | ||
1121 | if (alignment == 0) | |
1122 | alignment = PAGE_SIZE; | |
1123 | if (alignment & (PAGE_SIZE - 1)) { | |
1124 | DRM_ERROR("Invalid object alignment requested %u\n", alignment); | |
1125 | return -EINVAL; | |
1126 | } | |
1127 | ||
1128 | search_free: | |
1129 | free_space = drm_mm_search_free(&dev_priv->mm.gtt_space, | |
1130 | obj->size, alignment, 0); | |
1131 | if (free_space != NULL) { | |
1132 | obj_priv->gtt_space = drm_mm_get_block(free_space, obj->size, | |
1133 | alignment); | |
1134 | if (obj_priv->gtt_space != NULL) { | |
1135 | obj_priv->gtt_space->private = obj; | |
1136 | obj_priv->gtt_offset = obj_priv->gtt_space->start; | |
1137 | } | |
1138 | } | |
1139 | if (obj_priv->gtt_space == NULL) { | |
1140 | /* If the gtt is empty and we're still having trouble | |
1141 | * fitting our object in, we're out of memory. | |
1142 | */ | |
1143 | #if WATCH_LRU | |
1144 | DRM_INFO("%s: GTT full, evicting something\n", __func__); | |
1145 | #endif | |
1146 | if (list_empty(&dev_priv->mm.inactive_list) && | |
1147 | list_empty(&dev_priv->mm.flushing_list) && | |
1148 | list_empty(&dev_priv->mm.active_list)) { | |
1149 | DRM_ERROR("GTT full, but LRU list empty\n"); | |
1150 | return -ENOMEM; | |
1151 | } | |
1152 | ||
1153 | ret = i915_gem_evict_something(dev); | |
1154 | if (ret != 0) { | |
1155 | DRM_ERROR("Failed to evict a buffer %d\n", ret); | |
1156 | return ret; | |
1157 | } | |
1158 | goto search_free; | |
1159 | } | |
1160 | ||
1161 | #if WATCH_BUF | |
1162 | DRM_INFO("Binding object of size %d at 0x%08x\n", | |
1163 | obj->size, obj_priv->gtt_offset); | |
1164 | #endif | |
1165 | ret = i915_gem_object_get_page_list(obj); | |
1166 | if (ret) { | |
1167 | drm_mm_put_block(obj_priv->gtt_space); | |
1168 | obj_priv->gtt_space = NULL; | |
1169 | return ret; | |
1170 | } | |
1171 | ||
1172 | page_count = obj->size / PAGE_SIZE; | |
1173 | /* Create an AGP memory structure pointing at our pages, and bind it | |
1174 | * into the GTT. | |
1175 | */ | |
1176 | obj_priv->agp_mem = drm_agp_bind_pages(dev, | |
1177 | obj_priv->page_list, | |
1178 | page_count, | |
ba1eb1d8 KP |
1179 | obj_priv->gtt_offset, |
1180 | obj_priv->agp_type); | |
673a394b EA |
1181 | if (obj_priv->agp_mem == NULL) { |
1182 | i915_gem_object_free_page_list(obj); | |
1183 | drm_mm_put_block(obj_priv->gtt_space); | |
1184 | obj_priv->gtt_space = NULL; | |
1185 | return -ENOMEM; | |
1186 | } | |
1187 | atomic_inc(&dev->gtt_count); | |
1188 | atomic_add(obj->size, &dev->gtt_memory); | |
1189 | ||
1190 | /* Assert that the object is not currently in any GPU domain. As it | |
1191 | * wasn't in the GTT, there shouldn't be any way it could have been in | |
1192 | * a GPU cache | |
1193 | */ | |
1194 | BUG_ON(obj->read_domains & ~(I915_GEM_DOMAIN_CPU|I915_GEM_DOMAIN_GTT)); | |
1195 | BUG_ON(obj->write_domain & ~(I915_GEM_DOMAIN_CPU|I915_GEM_DOMAIN_GTT)); | |
1196 | ||
1197 | return 0; | |
1198 | } | |
1199 | ||
1200 | void | |
1201 | i915_gem_clflush_object(struct drm_gem_object *obj) | |
1202 | { | |
1203 | struct drm_i915_gem_object *obj_priv = obj->driver_private; | |
1204 | ||
1205 | /* If we don't have a page list set up, then we're not pinned | |
1206 | * to GPU, and we can ignore the cache flush because it'll happen | |
1207 | * again at bind time. | |
1208 | */ | |
1209 | if (obj_priv->page_list == NULL) | |
1210 | return; | |
1211 | ||
1212 | drm_clflush_pages(obj_priv->page_list, obj->size / PAGE_SIZE); | |
1213 | } | |
1214 | ||
1215 | /* | |
1216 | * Set the next domain for the specified object. This | |
1217 | * may not actually perform the necessary flushing/invaliding though, | |
1218 | * as that may want to be batched with other set_domain operations | |
1219 | * | |
1220 | * This is (we hope) the only really tricky part of gem. The goal | |
1221 | * is fairly simple -- track which caches hold bits of the object | |
1222 | * and make sure they remain coherent. A few concrete examples may | |
1223 | * help to explain how it works. For shorthand, we use the notation | |
1224 | * (read_domains, write_domain), e.g. (CPU, CPU) to indicate the | |
1225 | * a pair of read and write domain masks. | |
1226 | * | |
1227 | * Case 1: the batch buffer | |
1228 | * | |
1229 | * 1. Allocated | |
1230 | * 2. Written by CPU | |
1231 | * 3. Mapped to GTT | |
1232 | * 4. Read by GPU | |
1233 | * 5. Unmapped from GTT | |
1234 | * 6. Freed | |
1235 | * | |
1236 | * Let's take these a step at a time | |
1237 | * | |
1238 | * 1. Allocated | |
1239 | * Pages allocated from the kernel may still have | |
1240 | * cache contents, so we set them to (CPU, CPU) always. | |
1241 | * 2. Written by CPU (using pwrite) | |
1242 | * The pwrite function calls set_domain (CPU, CPU) and | |
1243 | * this function does nothing (as nothing changes) | |
1244 | * 3. Mapped by GTT | |
1245 | * This function asserts that the object is not | |
1246 | * currently in any GPU-based read or write domains | |
1247 | * 4. Read by GPU | |
1248 | * i915_gem_execbuffer calls set_domain (COMMAND, 0). | |
1249 | * As write_domain is zero, this function adds in the | |
1250 | * current read domains (CPU+COMMAND, 0). | |
1251 | * flush_domains is set to CPU. | |
1252 | * invalidate_domains is set to COMMAND | |
1253 | * clflush is run to get data out of the CPU caches | |
1254 | * then i915_dev_set_domain calls i915_gem_flush to | |
1255 | * emit an MI_FLUSH and drm_agp_chipset_flush | |
1256 | * 5. Unmapped from GTT | |
1257 | * i915_gem_object_unbind calls set_domain (CPU, CPU) | |
1258 | * flush_domains and invalidate_domains end up both zero | |
1259 | * so no flushing/invalidating happens | |
1260 | * 6. Freed | |
1261 | * yay, done | |
1262 | * | |
1263 | * Case 2: The shared render buffer | |
1264 | * | |
1265 | * 1. Allocated | |
1266 | * 2. Mapped to GTT | |
1267 | * 3. Read/written by GPU | |
1268 | * 4. set_domain to (CPU,CPU) | |
1269 | * 5. Read/written by CPU | |
1270 | * 6. Read/written by GPU | |
1271 | * | |
1272 | * 1. Allocated | |
1273 | * Same as last example, (CPU, CPU) | |
1274 | * 2. Mapped to GTT | |
1275 | * Nothing changes (assertions find that it is not in the GPU) | |
1276 | * 3. Read/written by GPU | |
1277 | * execbuffer calls set_domain (RENDER, RENDER) | |
1278 | * flush_domains gets CPU | |
1279 | * invalidate_domains gets GPU | |
1280 | * clflush (obj) | |
1281 | * MI_FLUSH and drm_agp_chipset_flush | |
1282 | * 4. set_domain (CPU, CPU) | |
1283 | * flush_domains gets GPU | |
1284 | * invalidate_domains gets CPU | |
1285 | * wait_rendering (obj) to make sure all drawing is complete. | |
1286 | * This will include an MI_FLUSH to get the data from GPU | |
1287 | * to memory | |
1288 | * clflush (obj) to invalidate the CPU cache | |
1289 | * Another MI_FLUSH in i915_gem_flush (eliminate this somehow?) | |
1290 | * 5. Read/written by CPU | |
1291 | * cache lines are loaded and dirtied | |
1292 | * 6. Read written by GPU | |
1293 | * Same as last GPU access | |
1294 | * | |
1295 | * Case 3: The constant buffer | |
1296 | * | |
1297 | * 1. Allocated | |
1298 | * 2. Written by CPU | |
1299 | * 3. Read by GPU | |
1300 | * 4. Updated (written) by CPU again | |
1301 | * 5. Read by GPU | |
1302 | * | |
1303 | * 1. Allocated | |
1304 | * (CPU, CPU) | |
1305 | * 2. Written by CPU | |
1306 | * (CPU, CPU) | |
1307 | * 3. Read by GPU | |
1308 | * (CPU+RENDER, 0) | |
1309 | * flush_domains = CPU | |
1310 | * invalidate_domains = RENDER | |
1311 | * clflush (obj) | |
1312 | * MI_FLUSH | |
1313 | * drm_agp_chipset_flush | |
1314 | * 4. Updated (written) by CPU again | |
1315 | * (CPU, CPU) | |
1316 | * flush_domains = 0 (no previous write domain) | |
1317 | * invalidate_domains = 0 (no new read domains) | |
1318 | * 5. Read by GPU | |
1319 | * (CPU+RENDER, 0) | |
1320 | * flush_domains = CPU | |
1321 | * invalidate_domains = RENDER | |
1322 | * clflush (obj) | |
1323 | * MI_FLUSH | |
1324 | * drm_agp_chipset_flush | |
1325 | */ | |
1326 | static int | |
1327 | i915_gem_object_set_domain(struct drm_gem_object *obj, | |
1328 | uint32_t read_domains, | |
1329 | uint32_t write_domain) | |
1330 | { | |
1331 | struct drm_device *dev = obj->dev; | |
1332 | struct drm_i915_gem_object *obj_priv = obj->driver_private; | |
1333 | uint32_t invalidate_domains = 0; | |
1334 | uint32_t flush_domains = 0; | |
1335 | int ret; | |
1336 | ||
1337 | #if WATCH_BUF | |
1338 | DRM_INFO("%s: object %p read %08x -> %08x write %08x -> %08x\n", | |
1339 | __func__, obj, | |
1340 | obj->read_domains, read_domains, | |
1341 | obj->write_domain, write_domain); | |
1342 | #endif | |
1343 | /* | |
1344 | * If the object isn't moving to a new write domain, | |
1345 | * let the object stay in multiple read domains | |
1346 | */ | |
1347 | if (write_domain == 0) | |
1348 | read_domains |= obj->read_domains; | |
1349 | else | |
1350 | obj_priv->dirty = 1; | |
1351 | ||
1352 | /* | |
1353 | * Flush the current write domain if | |
1354 | * the new read domains don't match. Invalidate | |
1355 | * any read domains which differ from the old | |
1356 | * write domain | |
1357 | */ | |
1358 | if (obj->write_domain && obj->write_domain != read_domains) { | |
1359 | flush_domains |= obj->write_domain; | |
1360 | invalidate_domains |= read_domains & ~obj->write_domain; | |
1361 | } | |
1362 | /* | |
1363 | * Invalidate any read caches which may have | |
1364 | * stale data. That is, any new read domains. | |
1365 | */ | |
1366 | invalidate_domains |= read_domains & ~obj->read_domains; | |
1367 | if ((flush_domains | invalidate_domains) & I915_GEM_DOMAIN_CPU) { | |
1368 | #if WATCH_BUF | |
1369 | DRM_INFO("%s: CPU domain flush %08x invalidate %08x\n", | |
1370 | __func__, flush_domains, invalidate_domains); | |
1371 | #endif | |
1372 | /* | |
1373 | * If we're invaliding the CPU cache and flushing a GPU cache, | |
1374 | * then pause for rendering so that the GPU caches will be | |
1375 | * flushed before the cpu cache is invalidated | |
1376 | */ | |
1377 | if ((invalidate_domains & I915_GEM_DOMAIN_CPU) && | |
1378 | (flush_domains & ~(I915_GEM_DOMAIN_CPU | | |
1379 | I915_GEM_DOMAIN_GTT))) { | |
1380 | ret = i915_gem_object_wait_rendering(obj); | |
1381 | if (ret) | |
1382 | return ret; | |
1383 | } | |
1384 | i915_gem_clflush_object(obj); | |
1385 | } | |
1386 | ||
1387 | if ((write_domain | flush_domains) != 0) | |
1388 | obj->write_domain = write_domain; | |
1389 | ||
1390 | /* If we're invalidating the CPU domain, clear the per-page CPU | |
1391 | * domain list as well. | |
1392 | */ | |
1393 | if (obj_priv->page_cpu_valid != NULL && | |
1394 | (write_domain != 0 || | |
1395 | read_domains & I915_GEM_DOMAIN_CPU)) { | |
1396 | drm_free(obj_priv->page_cpu_valid, obj->size / PAGE_SIZE, | |
1397 | DRM_MEM_DRIVER); | |
1398 | obj_priv->page_cpu_valid = NULL; | |
1399 | } | |
1400 | obj->read_domains = read_domains; | |
1401 | ||
1402 | dev->invalidate_domains |= invalidate_domains; | |
1403 | dev->flush_domains |= flush_domains; | |
1404 | #if WATCH_BUF | |
1405 | DRM_INFO("%s: read %08x write %08x invalidate %08x flush %08x\n", | |
1406 | __func__, | |
1407 | obj->read_domains, obj->write_domain, | |
1408 | dev->invalidate_domains, dev->flush_domains); | |
1409 | #endif | |
1410 | return 0; | |
1411 | } | |
1412 | ||
1413 | /** | |
1414 | * Set the read/write domain on a range of the object. | |
1415 | * | |
1416 | * Currently only implemented for CPU reads, otherwise drops to normal | |
1417 | * i915_gem_object_set_domain(). | |
1418 | */ | |
1419 | static int | |
1420 | i915_gem_object_set_domain_range(struct drm_gem_object *obj, | |
1421 | uint64_t offset, | |
1422 | uint64_t size, | |
1423 | uint32_t read_domains, | |
1424 | uint32_t write_domain) | |
1425 | { | |
1426 | struct drm_i915_gem_object *obj_priv = obj->driver_private; | |
1427 | int ret, i; | |
1428 | ||
1429 | if (obj->read_domains & I915_GEM_DOMAIN_CPU) | |
1430 | return 0; | |
1431 | ||
1432 | if (read_domains != I915_GEM_DOMAIN_CPU || | |
1433 | write_domain != 0) | |
1434 | return i915_gem_object_set_domain(obj, | |
1435 | read_domains, write_domain); | |
1436 | ||
1437 | /* Wait on any GPU rendering to the object to be flushed. */ | |
1438 | if (obj->write_domain & ~(I915_GEM_DOMAIN_CPU | I915_GEM_DOMAIN_GTT)) { | |
1439 | ret = i915_gem_object_wait_rendering(obj); | |
1440 | if (ret) | |
1441 | return ret; | |
1442 | } | |
1443 | ||
1444 | if (obj_priv->page_cpu_valid == NULL) { | |
1445 | obj_priv->page_cpu_valid = drm_calloc(1, obj->size / PAGE_SIZE, | |
1446 | DRM_MEM_DRIVER); | |
1447 | } | |
1448 | ||
1449 | /* Flush the cache on any pages that are still invalid from the CPU's | |
1450 | * perspective. | |
1451 | */ | |
1452 | for (i = offset / PAGE_SIZE; i <= (offset + size - 1) / PAGE_SIZE; i++) { | |
1453 | if (obj_priv->page_cpu_valid[i]) | |
1454 | continue; | |
1455 | ||
1456 | drm_clflush_pages(obj_priv->page_list + i, 1); | |
1457 | ||
1458 | obj_priv->page_cpu_valid[i] = 1; | |
1459 | } | |
1460 | ||
1461 | return 0; | |
1462 | } | |
1463 | ||
1464 | /** | |
1465 | * Once all of the objects have been set in the proper domain, | |
1466 | * perform the necessary flush and invalidate operations. | |
1467 | * | |
1468 | * Returns the write domains flushed, for use in flush tracking. | |
1469 | */ | |
1470 | static uint32_t | |
1471 | i915_gem_dev_set_domain(struct drm_device *dev) | |
1472 | { | |
1473 | uint32_t flush_domains = dev->flush_domains; | |
1474 | ||
1475 | /* | |
1476 | * Now that all the buffers are synced to the proper domains, | |
1477 | * flush and invalidate the collected domains | |
1478 | */ | |
1479 | if (dev->invalidate_domains | dev->flush_domains) { | |
1480 | #if WATCH_EXEC | |
1481 | DRM_INFO("%s: invalidate_domains %08x flush_domains %08x\n", | |
1482 | __func__, | |
1483 | dev->invalidate_domains, | |
1484 | dev->flush_domains); | |
1485 | #endif | |
1486 | i915_gem_flush(dev, | |
1487 | dev->invalidate_domains, | |
1488 | dev->flush_domains); | |
1489 | dev->invalidate_domains = 0; | |
1490 | dev->flush_domains = 0; | |
1491 | } | |
1492 | ||
1493 | return flush_domains; | |
1494 | } | |
1495 | ||
1496 | /** | |
1497 | * Pin an object to the GTT and evaluate the relocations landing in it. | |
1498 | */ | |
1499 | static int | |
1500 | i915_gem_object_pin_and_relocate(struct drm_gem_object *obj, | |
1501 | struct drm_file *file_priv, | |
1502 | struct drm_i915_gem_exec_object *entry) | |
1503 | { | |
1504 | struct drm_device *dev = obj->dev; | |
1505 | struct drm_i915_gem_relocation_entry reloc; | |
1506 | struct drm_i915_gem_relocation_entry __user *relocs; | |
1507 | struct drm_i915_gem_object *obj_priv = obj->driver_private; | |
1508 | int i, ret; | |
1509 | uint32_t last_reloc_offset = -1; | |
3043c60c | 1510 | void __iomem *reloc_page = NULL; |
673a394b EA |
1511 | |
1512 | /* Choose the GTT offset for our buffer and put it there. */ | |
1513 | ret = i915_gem_object_pin(obj, (uint32_t) entry->alignment); | |
1514 | if (ret) | |
1515 | return ret; | |
1516 | ||
1517 | entry->offset = obj_priv->gtt_offset; | |
1518 | ||
1519 | relocs = (struct drm_i915_gem_relocation_entry __user *) | |
1520 | (uintptr_t) entry->relocs_ptr; | |
1521 | /* Apply the relocations, using the GTT aperture to avoid cache | |
1522 | * flushing requirements. | |
1523 | */ | |
1524 | for (i = 0; i < entry->relocation_count; i++) { | |
1525 | struct drm_gem_object *target_obj; | |
1526 | struct drm_i915_gem_object *target_obj_priv; | |
3043c60c EA |
1527 | uint32_t reloc_val, reloc_offset; |
1528 | uint32_t __iomem *reloc_entry; | |
673a394b EA |
1529 | |
1530 | ret = copy_from_user(&reloc, relocs + i, sizeof(reloc)); | |
1531 | if (ret != 0) { | |
1532 | i915_gem_object_unpin(obj); | |
1533 | return ret; | |
1534 | } | |
1535 | ||
1536 | target_obj = drm_gem_object_lookup(obj->dev, file_priv, | |
1537 | reloc.target_handle); | |
1538 | if (target_obj == NULL) { | |
1539 | i915_gem_object_unpin(obj); | |
1540 | return -EBADF; | |
1541 | } | |
1542 | target_obj_priv = target_obj->driver_private; | |
1543 | ||
1544 | /* The target buffer should have appeared before us in the | |
1545 | * exec_object list, so it should have a GTT space bound by now. | |
1546 | */ | |
1547 | if (target_obj_priv->gtt_space == NULL) { | |
1548 | DRM_ERROR("No GTT space found for object %d\n", | |
1549 | reloc.target_handle); | |
1550 | drm_gem_object_unreference(target_obj); | |
1551 | i915_gem_object_unpin(obj); | |
1552 | return -EINVAL; | |
1553 | } | |
1554 | ||
1555 | if (reloc.offset > obj->size - 4) { | |
1556 | DRM_ERROR("Relocation beyond object bounds: " | |
1557 | "obj %p target %d offset %d size %d.\n", | |
1558 | obj, reloc.target_handle, | |
1559 | (int) reloc.offset, (int) obj->size); | |
1560 | drm_gem_object_unreference(target_obj); | |
1561 | i915_gem_object_unpin(obj); | |
1562 | return -EINVAL; | |
1563 | } | |
1564 | if (reloc.offset & 3) { | |
1565 | DRM_ERROR("Relocation not 4-byte aligned: " | |
1566 | "obj %p target %d offset %d.\n", | |
1567 | obj, reloc.target_handle, | |
1568 | (int) reloc.offset); | |
1569 | drm_gem_object_unreference(target_obj); | |
1570 | i915_gem_object_unpin(obj); | |
1571 | return -EINVAL; | |
1572 | } | |
1573 | ||
1574 | if (reloc.write_domain && target_obj->pending_write_domain && | |
1575 | reloc.write_domain != target_obj->pending_write_domain) { | |
1576 | DRM_ERROR("Write domain conflict: " | |
1577 | "obj %p target %d offset %d " | |
1578 | "new %08x old %08x\n", | |
1579 | obj, reloc.target_handle, | |
1580 | (int) reloc.offset, | |
1581 | reloc.write_domain, | |
1582 | target_obj->pending_write_domain); | |
1583 | drm_gem_object_unreference(target_obj); | |
1584 | i915_gem_object_unpin(obj); | |
1585 | return -EINVAL; | |
1586 | } | |
1587 | ||
1588 | #if WATCH_RELOC | |
1589 | DRM_INFO("%s: obj %p offset %08x target %d " | |
1590 | "read %08x write %08x gtt %08x " | |
1591 | "presumed %08x delta %08x\n", | |
1592 | __func__, | |
1593 | obj, | |
1594 | (int) reloc.offset, | |
1595 | (int) reloc.target_handle, | |
1596 | (int) reloc.read_domains, | |
1597 | (int) reloc.write_domain, | |
1598 | (int) target_obj_priv->gtt_offset, | |
1599 | (int) reloc.presumed_offset, | |
1600 | reloc.delta); | |
1601 | #endif | |
1602 | ||
1603 | target_obj->pending_read_domains |= reloc.read_domains; | |
1604 | target_obj->pending_write_domain |= reloc.write_domain; | |
1605 | ||
1606 | /* If the relocation already has the right value in it, no | |
1607 | * more work needs to be done. | |
1608 | */ | |
1609 | if (target_obj_priv->gtt_offset == reloc.presumed_offset) { | |
1610 | drm_gem_object_unreference(target_obj); | |
1611 | continue; | |
1612 | } | |
1613 | ||
1614 | /* Now that we're going to actually write some data in, | |
1615 | * make sure that any rendering using this buffer's contents | |
1616 | * is completed. | |
1617 | */ | |
1618 | i915_gem_object_wait_rendering(obj); | |
1619 | ||
1620 | /* As we're writing through the gtt, flush | |
1621 | * any CPU writes before we write the relocations | |
1622 | */ | |
1623 | if (obj->write_domain & I915_GEM_DOMAIN_CPU) { | |
1624 | i915_gem_clflush_object(obj); | |
1625 | drm_agp_chipset_flush(dev); | |
1626 | obj->write_domain = 0; | |
1627 | } | |
1628 | ||
1629 | /* Map the page containing the relocation we're going to | |
1630 | * perform. | |
1631 | */ | |
1632 | reloc_offset = obj_priv->gtt_offset + reloc.offset; | |
1633 | if (reloc_page == NULL || | |
1634 | (last_reloc_offset & ~(PAGE_SIZE - 1)) != | |
1635 | (reloc_offset & ~(PAGE_SIZE - 1))) { | |
1636 | if (reloc_page != NULL) | |
1637 | iounmap(reloc_page); | |
1638 | ||
bd88ee4c EA |
1639 | reloc_page = ioremap_wc(dev->agp->base + |
1640 | (reloc_offset & | |
1641 | ~(PAGE_SIZE - 1)), | |
1642 | PAGE_SIZE); | |
673a394b EA |
1643 | last_reloc_offset = reloc_offset; |
1644 | if (reloc_page == NULL) { | |
1645 | drm_gem_object_unreference(target_obj); | |
1646 | i915_gem_object_unpin(obj); | |
1647 | return -ENOMEM; | |
1648 | } | |
1649 | } | |
1650 | ||
3043c60c | 1651 | reloc_entry = (uint32_t __iomem *)(reloc_page + |
673a394b EA |
1652 | (reloc_offset & (PAGE_SIZE - 1))); |
1653 | reloc_val = target_obj_priv->gtt_offset + reloc.delta; | |
1654 | ||
1655 | #if WATCH_BUF | |
1656 | DRM_INFO("Applied relocation: %p@0x%08x %08x -> %08x\n", | |
1657 | obj, (unsigned int) reloc.offset, | |
1658 | readl(reloc_entry), reloc_val); | |
1659 | #endif | |
1660 | writel(reloc_val, reloc_entry); | |
1661 | ||
1662 | /* Write the updated presumed offset for this entry back out | |
1663 | * to the user. | |
1664 | */ | |
1665 | reloc.presumed_offset = target_obj_priv->gtt_offset; | |
1666 | ret = copy_to_user(relocs + i, &reloc, sizeof(reloc)); | |
1667 | if (ret != 0) { | |
1668 | drm_gem_object_unreference(target_obj); | |
1669 | i915_gem_object_unpin(obj); | |
1670 | return ret; | |
1671 | } | |
1672 | ||
1673 | drm_gem_object_unreference(target_obj); | |
1674 | } | |
1675 | ||
1676 | if (reloc_page != NULL) | |
1677 | iounmap(reloc_page); | |
1678 | ||
1679 | #if WATCH_BUF | |
1680 | if (0) | |
1681 | i915_gem_dump_object(obj, 128, __func__, ~0); | |
1682 | #endif | |
1683 | return 0; | |
1684 | } | |
1685 | ||
1686 | /** Dispatch a batchbuffer to the ring | |
1687 | */ | |
1688 | static int | |
1689 | i915_dispatch_gem_execbuffer(struct drm_device *dev, | |
1690 | struct drm_i915_gem_execbuffer *exec, | |
1691 | uint64_t exec_offset) | |
1692 | { | |
1693 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1694 | struct drm_clip_rect __user *boxes = (struct drm_clip_rect __user *) | |
1695 | (uintptr_t) exec->cliprects_ptr; | |
1696 | int nbox = exec->num_cliprects; | |
1697 | int i = 0, count; | |
1698 | uint32_t exec_start, exec_len; | |
1699 | RING_LOCALS; | |
1700 | ||
1701 | exec_start = (uint32_t) exec_offset + exec->batch_start_offset; | |
1702 | exec_len = (uint32_t) exec->batch_len; | |
1703 | ||
1704 | if ((exec_start | exec_len) & 0x7) { | |
1705 | DRM_ERROR("alignment\n"); | |
1706 | return -EINVAL; | |
1707 | } | |
1708 | ||
1709 | if (!exec_start) | |
1710 | return -EINVAL; | |
1711 | ||
1712 | count = nbox ? nbox : 1; | |
1713 | ||
1714 | for (i = 0; i < count; i++) { | |
1715 | if (i < nbox) { | |
1716 | int ret = i915_emit_box(dev, boxes, i, | |
1717 | exec->DR1, exec->DR4); | |
1718 | if (ret) | |
1719 | return ret; | |
1720 | } | |
1721 | ||
1722 | if (IS_I830(dev) || IS_845G(dev)) { | |
1723 | BEGIN_LP_RING(4); | |
1724 | OUT_RING(MI_BATCH_BUFFER); | |
1725 | OUT_RING(exec_start | MI_BATCH_NON_SECURE); | |
1726 | OUT_RING(exec_start + exec_len - 4); | |
1727 | OUT_RING(0); | |
1728 | ADVANCE_LP_RING(); | |
1729 | } else { | |
1730 | BEGIN_LP_RING(2); | |
1731 | if (IS_I965G(dev)) { | |
1732 | OUT_RING(MI_BATCH_BUFFER_START | | |
1733 | (2 << 6) | | |
1734 | MI_BATCH_NON_SECURE_I965); | |
1735 | OUT_RING(exec_start); | |
1736 | } else { | |
1737 | OUT_RING(MI_BATCH_BUFFER_START | | |
1738 | (2 << 6)); | |
1739 | OUT_RING(exec_start | MI_BATCH_NON_SECURE); | |
1740 | } | |
1741 | ADVANCE_LP_RING(); | |
1742 | } | |
1743 | } | |
1744 | ||
1745 | /* XXX breadcrumb */ | |
1746 | return 0; | |
1747 | } | |
1748 | ||
1749 | /* Throttle our rendering by waiting until the ring has completed our requests | |
1750 | * emitted over 20 msec ago. | |
1751 | * | |
1752 | * This should get us reasonable parallelism between CPU and GPU but also | |
1753 | * relatively low latency when blocking on a particular request to finish. | |
1754 | */ | |
1755 | static int | |
1756 | i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file_priv) | |
1757 | { | |
1758 | struct drm_i915_file_private *i915_file_priv = file_priv->driver_priv; | |
1759 | int ret = 0; | |
1760 | uint32_t seqno; | |
1761 | ||
1762 | mutex_lock(&dev->struct_mutex); | |
1763 | seqno = i915_file_priv->mm.last_gem_throttle_seqno; | |
1764 | i915_file_priv->mm.last_gem_throttle_seqno = | |
1765 | i915_file_priv->mm.last_gem_seqno; | |
1766 | if (seqno) | |
1767 | ret = i915_wait_request(dev, seqno); | |
1768 | mutex_unlock(&dev->struct_mutex); | |
1769 | return ret; | |
1770 | } | |
1771 | ||
1772 | int | |
1773 | i915_gem_execbuffer(struct drm_device *dev, void *data, | |
1774 | struct drm_file *file_priv) | |
1775 | { | |
1776 | drm_i915_private_t *dev_priv = dev->dev_private; | |
1777 | struct drm_i915_file_private *i915_file_priv = file_priv->driver_priv; | |
1778 | struct drm_i915_gem_execbuffer *args = data; | |
1779 | struct drm_i915_gem_exec_object *exec_list = NULL; | |
1780 | struct drm_gem_object **object_list = NULL; | |
1781 | struct drm_gem_object *batch_obj; | |
1782 | int ret, i, pinned = 0; | |
1783 | uint64_t exec_offset; | |
1784 | uint32_t seqno, flush_domains; | |
1785 | ||
1786 | #if WATCH_EXEC | |
1787 | DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n", | |
1788 | (int) args->buffers_ptr, args->buffer_count, args->batch_len); | |
1789 | #endif | |
1790 | ||
4f481ed2 EA |
1791 | if (args->buffer_count < 1) { |
1792 | DRM_ERROR("execbuf with %d buffers\n", args->buffer_count); | |
1793 | return -EINVAL; | |
1794 | } | |
673a394b EA |
1795 | /* Copy in the exec list from userland */ |
1796 | exec_list = drm_calloc(sizeof(*exec_list), args->buffer_count, | |
1797 | DRM_MEM_DRIVER); | |
1798 | object_list = drm_calloc(sizeof(*object_list), args->buffer_count, | |
1799 | DRM_MEM_DRIVER); | |
1800 | if (exec_list == NULL || object_list == NULL) { | |
1801 | DRM_ERROR("Failed to allocate exec or object list " | |
1802 | "for %d buffers\n", | |
1803 | args->buffer_count); | |
1804 | ret = -ENOMEM; | |
1805 | goto pre_mutex_err; | |
1806 | } | |
1807 | ret = copy_from_user(exec_list, | |
1808 | (struct drm_i915_relocation_entry __user *) | |
1809 | (uintptr_t) args->buffers_ptr, | |
1810 | sizeof(*exec_list) * args->buffer_count); | |
1811 | if (ret != 0) { | |
1812 | DRM_ERROR("copy %d exec entries failed %d\n", | |
1813 | args->buffer_count, ret); | |
1814 | goto pre_mutex_err; | |
1815 | } | |
1816 | ||
1817 | mutex_lock(&dev->struct_mutex); | |
1818 | ||
1819 | i915_verify_inactive(dev, __FILE__, __LINE__); | |
1820 | ||
1821 | if (dev_priv->mm.wedged) { | |
1822 | DRM_ERROR("Execbuf while wedged\n"); | |
1823 | mutex_unlock(&dev->struct_mutex); | |
1824 | return -EIO; | |
1825 | } | |
1826 | ||
1827 | if (dev_priv->mm.suspended) { | |
1828 | DRM_ERROR("Execbuf while VT-switched.\n"); | |
1829 | mutex_unlock(&dev->struct_mutex); | |
1830 | return -EBUSY; | |
1831 | } | |
1832 | ||
1833 | /* Zero the gloabl flush/invalidate flags. These | |
1834 | * will be modified as each object is bound to the | |
1835 | * gtt | |
1836 | */ | |
1837 | dev->invalidate_domains = 0; | |
1838 | dev->flush_domains = 0; | |
1839 | ||
1840 | /* Look up object handles and perform the relocations */ | |
1841 | for (i = 0; i < args->buffer_count; i++) { | |
1842 | object_list[i] = drm_gem_object_lookup(dev, file_priv, | |
1843 | exec_list[i].handle); | |
1844 | if (object_list[i] == NULL) { | |
1845 | DRM_ERROR("Invalid object handle %d at index %d\n", | |
1846 | exec_list[i].handle, i); | |
1847 | ret = -EBADF; | |
1848 | goto err; | |
1849 | } | |
1850 | ||
1851 | object_list[i]->pending_read_domains = 0; | |
1852 | object_list[i]->pending_write_domain = 0; | |
1853 | ret = i915_gem_object_pin_and_relocate(object_list[i], | |
1854 | file_priv, | |
1855 | &exec_list[i]); | |
1856 | if (ret) { | |
1857 | DRM_ERROR("object bind and relocate failed %d\n", ret); | |
1858 | goto err; | |
1859 | } | |
1860 | pinned = i + 1; | |
1861 | } | |
1862 | ||
1863 | /* Set the pending read domains for the batch buffer to COMMAND */ | |
1864 | batch_obj = object_list[args->buffer_count-1]; | |
1865 | batch_obj->pending_read_domains = I915_GEM_DOMAIN_COMMAND; | |
1866 | batch_obj->pending_write_domain = 0; | |
1867 | ||
1868 | i915_verify_inactive(dev, __FILE__, __LINE__); | |
1869 | ||
1870 | for (i = 0; i < args->buffer_count; i++) { | |
1871 | struct drm_gem_object *obj = object_list[i]; | |
1872 | struct drm_i915_gem_object *obj_priv = obj->driver_private; | |
1873 | ||
1874 | if (obj_priv->gtt_space == NULL) { | |
1875 | /* We evicted the buffer in the process of validating | |
1876 | * our set of buffers in. We could try to recover by | |
1877 | * kicking them everything out and trying again from | |
1878 | * the start. | |
1879 | */ | |
1880 | ret = -ENOMEM; | |
1881 | goto err; | |
1882 | } | |
1883 | ||
1884 | /* make sure all previous memory operations have passed */ | |
1885 | ret = i915_gem_object_set_domain(obj, | |
1886 | obj->pending_read_domains, | |
1887 | obj->pending_write_domain); | |
1888 | if (ret) | |
1889 | goto err; | |
1890 | } | |
1891 | ||
1892 | i915_verify_inactive(dev, __FILE__, __LINE__); | |
1893 | ||
1894 | /* Flush/invalidate caches and chipset buffer */ | |
1895 | flush_domains = i915_gem_dev_set_domain(dev); | |
1896 | ||
1897 | i915_verify_inactive(dev, __FILE__, __LINE__); | |
1898 | ||
1899 | #if WATCH_COHERENCY | |
1900 | for (i = 0; i < args->buffer_count; i++) { | |
1901 | i915_gem_object_check_coherency(object_list[i], | |
1902 | exec_list[i].handle); | |
1903 | } | |
1904 | #endif | |
1905 | ||
1906 | exec_offset = exec_list[args->buffer_count - 1].offset; | |
1907 | ||
1908 | #if WATCH_EXEC | |
1909 | i915_gem_dump_object(object_list[args->buffer_count - 1], | |
1910 | args->batch_len, | |
1911 | __func__, | |
1912 | ~0); | |
1913 | #endif | |
1914 | ||
1915 | (void)i915_add_request(dev, flush_domains); | |
1916 | ||
1917 | /* Exec the batchbuffer */ | |
1918 | ret = i915_dispatch_gem_execbuffer(dev, args, exec_offset); | |
1919 | if (ret) { | |
1920 | DRM_ERROR("dispatch failed %d\n", ret); | |
1921 | goto err; | |
1922 | } | |
1923 | ||
1924 | /* | |
1925 | * Ensure that the commands in the batch buffer are | |
1926 | * finished before the interrupt fires | |
1927 | */ | |
1928 | flush_domains = i915_retire_commands(dev); | |
1929 | ||
1930 | i915_verify_inactive(dev, __FILE__, __LINE__); | |
1931 | ||
1932 | /* | |
1933 | * Get a seqno representing the execution of the current buffer, | |
1934 | * which we can wait on. We would like to mitigate these interrupts, | |
1935 | * likely by only creating seqnos occasionally (so that we have | |
1936 | * *some* interrupts representing completion of buffers that we can | |
1937 | * wait on when trying to clear up gtt space). | |
1938 | */ | |
1939 | seqno = i915_add_request(dev, flush_domains); | |
1940 | BUG_ON(seqno == 0); | |
1941 | i915_file_priv->mm.last_gem_seqno = seqno; | |
1942 | for (i = 0; i < args->buffer_count; i++) { | |
1943 | struct drm_gem_object *obj = object_list[i]; | |
1944 | struct drm_i915_gem_object *obj_priv = obj->driver_private; | |
1945 | ||
1946 | i915_gem_object_move_to_active(obj); | |
1947 | obj_priv->last_rendering_seqno = seqno; | |
1948 | #if WATCH_LRU | |
1949 | DRM_INFO("%s: move to exec list %p\n", __func__, obj); | |
1950 | #endif | |
1951 | } | |
1952 | #if WATCH_LRU | |
1953 | i915_dump_lru(dev, __func__); | |
1954 | #endif | |
1955 | ||
1956 | i915_verify_inactive(dev, __FILE__, __LINE__); | |
1957 | ||
1958 | /* Copy the new buffer offsets back to the user's exec list. */ | |
1959 | ret = copy_to_user((struct drm_i915_relocation_entry __user *) | |
1960 | (uintptr_t) args->buffers_ptr, | |
1961 | exec_list, | |
1962 | sizeof(*exec_list) * args->buffer_count); | |
1963 | if (ret) | |
1964 | DRM_ERROR("failed to copy %d exec entries " | |
1965 | "back to user (%d)\n", | |
1966 | args->buffer_count, ret); | |
1967 | err: | |
1968 | if (object_list != NULL) { | |
1969 | for (i = 0; i < pinned; i++) | |
1970 | i915_gem_object_unpin(object_list[i]); | |
1971 | ||
1972 | for (i = 0; i < args->buffer_count; i++) | |
1973 | drm_gem_object_unreference(object_list[i]); | |
1974 | } | |
1975 | mutex_unlock(&dev->struct_mutex); | |
1976 | ||
1977 | pre_mutex_err: | |
1978 | drm_free(object_list, sizeof(*object_list) * args->buffer_count, | |
1979 | DRM_MEM_DRIVER); | |
1980 | drm_free(exec_list, sizeof(*exec_list) * args->buffer_count, | |
1981 | DRM_MEM_DRIVER); | |
1982 | ||
1983 | return ret; | |
1984 | } | |
1985 | ||
1986 | int | |
1987 | i915_gem_object_pin(struct drm_gem_object *obj, uint32_t alignment) | |
1988 | { | |
1989 | struct drm_device *dev = obj->dev; | |
1990 | struct drm_i915_gem_object *obj_priv = obj->driver_private; | |
1991 | int ret; | |
1992 | ||
1993 | i915_verify_inactive(dev, __FILE__, __LINE__); | |
1994 | if (obj_priv->gtt_space == NULL) { | |
1995 | ret = i915_gem_object_bind_to_gtt(obj, alignment); | |
1996 | if (ret != 0) { | |
1997 | DRM_ERROR("Failure to bind: %d", ret); | |
1998 | return ret; | |
1999 | } | |
2000 | } | |
2001 | obj_priv->pin_count++; | |
2002 | ||
2003 | /* If the object is not active and not pending a flush, | |
2004 | * remove it from the inactive list | |
2005 | */ | |
2006 | if (obj_priv->pin_count == 1) { | |
2007 | atomic_inc(&dev->pin_count); | |
2008 | atomic_add(obj->size, &dev->pin_memory); | |
2009 | if (!obj_priv->active && | |
2010 | (obj->write_domain & ~(I915_GEM_DOMAIN_CPU | | |
2011 | I915_GEM_DOMAIN_GTT)) == 0 && | |
2012 | !list_empty(&obj_priv->list)) | |
2013 | list_del_init(&obj_priv->list); | |
2014 | } | |
2015 | i915_verify_inactive(dev, __FILE__, __LINE__); | |
2016 | ||
2017 | return 0; | |
2018 | } | |
2019 | ||
2020 | void | |
2021 | i915_gem_object_unpin(struct drm_gem_object *obj) | |
2022 | { | |
2023 | struct drm_device *dev = obj->dev; | |
2024 | drm_i915_private_t *dev_priv = dev->dev_private; | |
2025 | struct drm_i915_gem_object *obj_priv = obj->driver_private; | |
2026 | ||
2027 | i915_verify_inactive(dev, __FILE__, __LINE__); | |
2028 | obj_priv->pin_count--; | |
2029 | BUG_ON(obj_priv->pin_count < 0); | |
2030 | BUG_ON(obj_priv->gtt_space == NULL); | |
2031 | ||
2032 | /* If the object is no longer pinned, and is | |
2033 | * neither active nor being flushed, then stick it on | |
2034 | * the inactive list | |
2035 | */ | |
2036 | if (obj_priv->pin_count == 0) { | |
2037 | if (!obj_priv->active && | |
2038 | (obj->write_domain & ~(I915_GEM_DOMAIN_CPU | | |
2039 | I915_GEM_DOMAIN_GTT)) == 0) | |
2040 | list_move_tail(&obj_priv->list, | |
2041 | &dev_priv->mm.inactive_list); | |
2042 | atomic_dec(&dev->pin_count); | |
2043 | atomic_sub(obj->size, &dev->pin_memory); | |
2044 | } | |
2045 | i915_verify_inactive(dev, __FILE__, __LINE__); | |
2046 | } | |
2047 | ||
2048 | int | |
2049 | i915_gem_pin_ioctl(struct drm_device *dev, void *data, | |
2050 | struct drm_file *file_priv) | |
2051 | { | |
2052 | struct drm_i915_gem_pin *args = data; | |
2053 | struct drm_gem_object *obj; | |
2054 | struct drm_i915_gem_object *obj_priv; | |
2055 | int ret; | |
2056 | ||
2057 | mutex_lock(&dev->struct_mutex); | |
2058 | ||
2059 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); | |
2060 | if (obj == NULL) { | |
2061 | DRM_ERROR("Bad handle in i915_gem_pin_ioctl(): %d\n", | |
2062 | args->handle); | |
2063 | mutex_unlock(&dev->struct_mutex); | |
2064 | return -EBADF; | |
2065 | } | |
2066 | obj_priv = obj->driver_private; | |
2067 | ||
2068 | ret = i915_gem_object_pin(obj, args->alignment); | |
2069 | if (ret != 0) { | |
2070 | drm_gem_object_unreference(obj); | |
2071 | mutex_unlock(&dev->struct_mutex); | |
2072 | return ret; | |
2073 | } | |
2074 | ||
2075 | /* XXX - flush the CPU caches for pinned objects | |
2076 | * as the X server doesn't manage domains yet | |
2077 | */ | |
2078 | if (obj->write_domain & I915_GEM_DOMAIN_CPU) { | |
2079 | i915_gem_clflush_object(obj); | |
2080 | drm_agp_chipset_flush(dev); | |
2081 | obj->write_domain = 0; | |
2082 | } | |
2083 | args->offset = obj_priv->gtt_offset; | |
2084 | drm_gem_object_unreference(obj); | |
2085 | mutex_unlock(&dev->struct_mutex); | |
2086 | ||
2087 | return 0; | |
2088 | } | |
2089 | ||
2090 | int | |
2091 | i915_gem_unpin_ioctl(struct drm_device *dev, void *data, | |
2092 | struct drm_file *file_priv) | |
2093 | { | |
2094 | struct drm_i915_gem_pin *args = data; | |
2095 | struct drm_gem_object *obj; | |
2096 | ||
2097 | mutex_lock(&dev->struct_mutex); | |
2098 | ||
2099 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); | |
2100 | if (obj == NULL) { | |
2101 | DRM_ERROR("Bad handle in i915_gem_unpin_ioctl(): %d\n", | |
2102 | args->handle); | |
2103 | mutex_unlock(&dev->struct_mutex); | |
2104 | return -EBADF; | |
2105 | } | |
2106 | ||
2107 | i915_gem_object_unpin(obj); | |
2108 | ||
2109 | drm_gem_object_unreference(obj); | |
2110 | mutex_unlock(&dev->struct_mutex); | |
2111 | return 0; | |
2112 | } | |
2113 | ||
2114 | int | |
2115 | i915_gem_busy_ioctl(struct drm_device *dev, void *data, | |
2116 | struct drm_file *file_priv) | |
2117 | { | |
2118 | struct drm_i915_gem_busy *args = data; | |
2119 | struct drm_gem_object *obj; | |
2120 | struct drm_i915_gem_object *obj_priv; | |
2121 | ||
2122 | mutex_lock(&dev->struct_mutex); | |
2123 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); | |
2124 | if (obj == NULL) { | |
2125 | DRM_ERROR("Bad handle in i915_gem_busy_ioctl(): %d\n", | |
2126 | args->handle); | |
2127 | mutex_unlock(&dev->struct_mutex); | |
2128 | return -EBADF; | |
2129 | } | |
2130 | ||
2131 | obj_priv = obj->driver_private; | |
2132 | args->busy = obj_priv->active; | |
2133 | ||
2134 | drm_gem_object_unreference(obj); | |
2135 | mutex_unlock(&dev->struct_mutex); | |
2136 | return 0; | |
2137 | } | |
2138 | ||
2139 | int | |
2140 | i915_gem_throttle_ioctl(struct drm_device *dev, void *data, | |
2141 | struct drm_file *file_priv) | |
2142 | { | |
2143 | return i915_gem_ring_throttle(dev, file_priv); | |
2144 | } | |
2145 | ||
2146 | int i915_gem_init_object(struct drm_gem_object *obj) | |
2147 | { | |
2148 | struct drm_i915_gem_object *obj_priv; | |
2149 | ||
2150 | obj_priv = drm_calloc(1, sizeof(*obj_priv), DRM_MEM_DRIVER); | |
2151 | if (obj_priv == NULL) | |
2152 | return -ENOMEM; | |
2153 | ||
2154 | /* | |
2155 | * We've just allocated pages from the kernel, | |
2156 | * so they've just been written by the CPU with | |
2157 | * zeros. They'll need to be clflushed before we | |
2158 | * use them with the GPU. | |
2159 | */ | |
2160 | obj->write_domain = I915_GEM_DOMAIN_CPU; | |
2161 | obj->read_domains = I915_GEM_DOMAIN_CPU; | |
2162 | ||
ba1eb1d8 KP |
2163 | obj_priv->agp_type = AGP_USER_MEMORY; |
2164 | ||
673a394b EA |
2165 | obj->driver_private = obj_priv; |
2166 | obj_priv->obj = obj; | |
2167 | INIT_LIST_HEAD(&obj_priv->list); | |
2168 | return 0; | |
2169 | } | |
2170 | ||
2171 | void i915_gem_free_object(struct drm_gem_object *obj) | |
2172 | { | |
2173 | struct drm_i915_gem_object *obj_priv = obj->driver_private; | |
2174 | ||
2175 | while (obj_priv->pin_count > 0) | |
2176 | i915_gem_object_unpin(obj); | |
2177 | ||
2178 | i915_gem_object_unbind(obj); | |
2179 | ||
2180 | drm_free(obj_priv->page_cpu_valid, 1, DRM_MEM_DRIVER); | |
2181 | drm_free(obj->driver_private, 1, DRM_MEM_DRIVER); | |
2182 | } | |
2183 | ||
2184 | static int | |
2185 | i915_gem_set_domain(struct drm_gem_object *obj, | |
2186 | struct drm_file *file_priv, | |
2187 | uint32_t read_domains, | |
2188 | uint32_t write_domain) | |
2189 | { | |
2190 | struct drm_device *dev = obj->dev; | |
2191 | int ret; | |
2192 | uint32_t flush_domains; | |
2193 | ||
2194 | BUG_ON(!mutex_is_locked(&dev->struct_mutex)); | |
2195 | ||
2196 | ret = i915_gem_object_set_domain(obj, read_domains, write_domain); | |
2197 | if (ret) | |
2198 | return ret; | |
2199 | flush_domains = i915_gem_dev_set_domain(obj->dev); | |
2200 | ||
2201 | if (flush_domains & ~(I915_GEM_DOMAIN_CPU|I915_GEM_DOMAIN_GTT)) | |
2202 | (void) i915_add_request(dev, flush_domains); | |
2203 | ||
2204 | return 0; | |
2205 | } | |
2206 | ||
2207 | /** Unbinds all objects that are on the given buffer list. */ | |
2208 | static int | |
2209 | i915_gem_evict_from_list(struct drm_device *dev, struct list_head *head) | |
2210 | { | |
2211 | struct drm_gem_object *obj; | |
2212 | struct drm_i915_gem_object *obj_priv; | |
2213 | int ret; | |
2214 | ||
2215 | while (!list_empty(head)) { | |
2216 | obj_priv = list_first_entry(head, | |
2217 | struct drm_i915_gem_object, | |
2218 | list); | |
2219 | obj = obj_priv->obj; | |
2220 | ||
2221 | if (obj_priv->pin_count != 0) { | |
2222 | DRM_ERROR("Pinned object in unbind list\n"); | |
2223 | mutex_unlock(&dev->struct_mutex); | |
2224 | return -EINVAL; | |
2225 | } | |
2226 | ||
2227 | ret = i915_gem_object_unbind(obj); | |
2228 | if (ret != 0) { | |
2229 | DRM_ERROR("Error unbinding object in LeaveVT: %d\n", | |
2230 | ret); | |
2231 | mutex_unlock(&dev->struct_mutex); | |
2232 | return ret; | |
2233 | } | |
2234 | } | |
2235 | ||
2236 | ||
2237 | return 0; | |
2238 | } | |
2239 | ||
2240 | static int | |
2241 | i915_gem_idle(struct drm_device *dev) | |
2242 | { | |
2243 | drm_i915_private_t *dev_priv = dev->dev_private; | |
2244 | uint32_t seqno, cur_seqno, last_seqno; | |
2245 | int stuck, ret; | |
2246 | ||
6dbe2772 KP |
2247 | mutex_lock(&dev->struct_mutex); |
2248 | ||
2249 | if (dev_priv->mm.suspended || dev_priv->ring.ring_obj == NULL) { | |
2250 | mutex_unlock(&dev->struct_mutex); | |
673a394b | 2251 | return 0; |
6dbe2772 | 2252 | } |
673a394b EA |
2253 | |
2254 | /* Hack! Don't let anybody do execbuf while we don't control the chip. | |
2255 | * We need to replace this with a semaphore, or something. | |
2256 | */ | |
2257 | dev_priv->mm.suspended = 1; | |
2258 | ||
6dbe2772 KP |
2259 | /* Cancel the retire work handler, wait for it to finish if running |
2260 | */ | |
2261 | mutex_unlock(&dev->struct_mutex); | |
2262 | cancel_delayed_work_sync(&dev_priv->mm.retire_work); | |
2263 | mutex_lock(&dev->struct_mutex); | |
2264 | ||
673a394b EA |
2265 | i915_kernel_lost_context(dev); |
2266 | ||
2267 | /* Flush the GPU along with all non-CPU write domains | |
2268 | */ | |
2269 | i915_gem_flush(dev, ~(I915_GEM_DOMAIN_CPU|I915_GEM_DOMAIN_GTT), | |
2270 | ~(I915_GEM_DOMAIN_CPU|I915_GEM_DOMAIN_GTT)); | |
2271 | seqno = i915_add_request(dev, ~(I915_GEM_DOMAIN_CPU | | |
2272 | I915_GEM_DOMAIN_GTT)); | |
2273 | ||
2274 | if (seqno == 0) { | |
2275 | mutex_unlock(&dev->struct_mutex); | |
2276 | return -ENOMEM; | |
2277 | } | |
2278 | ||
2279 | dev_priv->mm.waiting_gem_seqno = seqno; | |
2280 | last_seqno = 0; | |
2281 | stuck = 0; | |
2282 | for (;;) { | |
2283 | cur_seqno = i915_get_gem_seqno(dev); | |
2284 | if (i915_seqno_passed(cur_seqno, seqno)) | |
2285 | break; | |
2286 | if (last_seqno == cur_seqno) { | |
2287 | if (stuck++ > 100) { | |
2288 | DRM_ERROR("hardware wedged\n"); | |
2289 | dev_priv->mm.wedged = 1; | |
2290 | DRM_WAKEUP(&dev_priv->irq_queue); | |
2291 | break; | |
2292 | } | |
2293 | } | |
2294 | msleep(10); | |
2295 | last_seqno = cur_seqno; | |
2296 | } | |
2297 | dev_priv->mm.waiting_gem_seqno = 0; | |
2298 | ||
2299 | i915_gem_retire_requests(dev); | |
2300 | ||
2301 | /* Active and flushing should now be empty as we've | |
2302 | * waited for a sequence higher than any pending execbuffer | |
2303 | */ | |
2304 | BUG_ON(!list_empty(&dev_priv->mm.active_list)); | |
2305 | BUG_ON(!list_empty(&dev_priv->mm.flushing_list)); | |
2306 | ||
2307 | /* Request should now be empty as we've also waited | |
2308 | * for the last request in the list | |
2309 | */ | |
2310 | BUG_ON(!list_empty(&dev_priv->mm.request_list)); | |
2311 | ||
2312 | /* Move all buffers out of the GTT. */ | |
2313 | ret = i915_gem_evict_from_list(dev, &dev_priv->mm.inactive_list); | |
6dbe2772 KP |
2314 | if (ret) { |
2315 | mutex_unlock(&dev->struct_mutex); | |
673a394b | 2316 | return ret; |
6dbe2772 | 2317 | } |
673a394b EA |
2318 | |
2319 | BUG_ON(!list_empty(&dev_priv->mm.active_list)); | |
2320 | BUG_ON(!list_empty(&dev_priv->mm.flushing_list)); | |
2321 | BUG_ON(!list_empty(&dev_priv->mm.inactive_list)); | |
2322 | BUG_ON(!list_empty(&dev_priv->mm.request_list)); | |
6dbe2772 KP |
2323 | |
2324 | i915_gem_cleanup_ringbuffer(dev); | |
2325 | mutex_unlock(&dev->struct_mutex); | |
2326 | ||
673a394b EA |
2327 | return 0; |
2328 | } | |
2329 | ||
2330 | static int | |
2331 | i915_gem_init_hws(struct drm_device *dev) | |
2332 | { | |
2333 | drm_i915_private_t *dev_priv = dev->dev_private; | |
2334 | struct drm_gem_object *obj; | |
2335 | struct drm_i915_gem_object *obj_priv; | |
2336 | int ret; | |
2337 | ||
2338 | /* If we need a physical address for the status page, it's already | |
2339 | * initialized at driver load time. | |
2340 | */ | |
2341 | if (!I915_NEED_GFX_HWS(dev)) | |
2342 | return 0; | |
2343 | ||
2344 | obj = drm_gem_object_alloc(dev, 4096); | |
2345 | if (obj == NULL) { | |
2346 | DRM_ERROR("Failed to allocate status page\n"); | |
2347 | return -ENOMEM; | |
2348 | } | |
2349 | obj_priv = obj->driver_private; | |
ba1eb1d8 | 2350 | obj_priv->agp_type = AGP_USER_CACHED_MEMORY; |
673a394b EA |
2351 | |
2352 | ret = i915_gem_object_pin(obj, 4096); | |
2353 | if (ret != 0) { | |
2354 | drm_gem_object_unreference(obj); | |
2355 | return ret; | |
2356 | } | |
2357 | ||
2358 | dev_priv->status_gfx_addr = obj_priv->gtt_offset; | |
673a394b | 2359 | |
ba1eb1d8 KP |
2360 | dev_priv->hw_status_page = kmap(obj_priv->page_list[0]); |
2361 | if (dev_priv->hw_status_page == NULL) { | |
673a394b EA |
2362 | DRM_ERROR("Failed to map status page.\n"); |
2363 | memset(&dev_priv->hws_map, 0, sizeof(dev_priv->hws_map)); | |
2364 | drm_gem_object_unreference(obj); | |
2365 | return -EINVAL; | |
2366 | } | |
2367 | dev_priv->hws_obj = obj; | |
673a394b EA |
2368 | memset(dev_priv->hw_status_page, 0, PAGE_SIZE); |
2369 | I915_WRITE(HWS_PGA, dev_priv->status_gfx_addr); | |
ba1eb1d8 | 2370 | I915_READ(HWS_PGA); /* posting read */ |
673a394b EA |
2371 | DRM_DEBUG("hws offset: 0x%08x\n", dev_priv->status_gfx_addr); |
2372 | ||
2373 | return 0; | |
2374 | } | |
2375 | ||
2376 | static int | |
2377 | i915_gem_init_ringbuffer(struct drm_device *dev) | |
2378 | { | |
2379 | drm_i915_private_t *dev_priv = dev->dev_private; | |
2380 | struct drm_gem_object *obj; | |
2381 | struct drm_i915_gem_object *obj_priv; | |
2382 | int ret; | |
50aa253d | 2383 | u32 head; |
673a394b EA |
2384 | |
2385 | ret = i915_gem_init_hws(dev); | |
2386 | if (ret != 0) | |
2387 | return ret; | |
2388 | ||
2389 | obj = drm_gem_object_alloc(dev, 128 * 1024); | |
2390 | if (obj == NULL) { | |
2391 | DRM_ERROR("Failed to allocate ringbuffer\n"); | |
2392 | return -ENOMEM; | |
2393 | } | |
2394 | obj_priv = obj->driver_private; | |
2395 | ||
2396 | ret = i915_gem_object_pin(obj, 4096); | |
2397 | if (ret != 0) { | |
2398 | drm_gem_object_unreference(obj); | |
2399 | return ret; | |
2400 | } | |
2401 | ||
2402 | /* Set up the kernel mapping for the ring. */ | |
2403 | dev_priv->ring.Size = obj->size; | |
2404 | dev_priv->ring.tail_mask = obj->size - 1; | |
2405 | ||
2406 | dev_priv->ring.map.offset = dev->agp->base + obj_priv->gtt_offset; | |
2407 | dev_priv->ring.map.size = obj->size; | |
2408 | dev_priv->ring.map.type = 0; | |
2409 | dev_priv->ring.map.flags = 0; | |
2410 | dev_priv->ring.map.mtrr = 0; | |
2411 | ||
bd88ee4c | 2412 | drm_core_ioremap_wc(&dev_priv->ring.map, dev); |
673a394b EA |
2413 | if (dev_priv->ring.map.handle == NULL) { |
2414 | DRM_ERROR("Failed to map ringbuffer.\n"); | |
2415 | memset(&dev_priv->ring, 0, sizeof(dev_priv->ring)); | |
2416 | drm_gem_object_unreference(obj); | |
2417 | return -EINVAL; | |
2418 | } | |
2419 | dev_priv->ring.ring_obj = obj; | |
2420 | dev_priv->ring.virtual_start = dev_priv->ring.map.handle; | |
2421 | ||
2422 | /* Stop the ring if it's running. */ | |
2423 | I915_WRITE(PRB0_CTL, 0); | |
673a394b | 2424 | I915_WRITE(PRB0_TAIL, 0); |
50aa253d | 2425 | I915_WRITE(PRB0_HEAD, 0); |
673a394b EA |
2426 | |
2427 | /* Initialize the ring. */ | |
2428 | I915_WRITE(PRB0_START, obj_priv->gtt_offset); | |
50aa253d KP |
2429 | head = I915_READ(PRB0_HEAD) & HEAD_ADDR; |
2430 | ||
2431 | /* G45 ring initialization fails to reset head to zero */ | |
2432 | if (head != 0) { | |
2433 | DRM_ERROR("Ring head not reset to zero " | |
2434 | "ctl %08x head %08x tail %08x start %08x\n", | |
2435 | I915_READ(PRB0_CTL), | |
2436 | I915_READ(PRB0_HEAD), | |
2437 | I915_READ(PRB0_TAIL), | |
2438 | I915_READ(PRB0_START)); | |
2439 | I915_WRITE(PRB0_HEAD, 0); | |
2440 | ||
2441 | DRM_ERROR("Ring head forced to zero " | |
2442 | "ctl %08x head %08x tail %08x start %08x\n", | |
2443 | I915_READ(PRB0_CTL), | |
2444 | I915_READ(PRB0_HEAD), | |
2445 | I915_READ(PRB0_TAIL), | |
2446 | I915_READ(PRB0_START)); | |
2447 | } | |
2448 | ||
673a394b EA |
2449 | I915_WRITE(PRB0_CTL, |
2450 | ((obj->size - 4096) & RING_NR_PAGES) | | |
2451 | RING_NO_REPORT | | |
2452 | RING_VALID); | |
2453 | ||
50aa253d KP |
2454 | head = I915_READ(PRB0_HEAD) & HEAD_ADDR; |
2455 | ||
2456 | /* If the head is still not zero, the ring is dead */ | |
2457 | if (head != 0) { | |
2458 | DRM_ERROR("Ring initialization failed " | |
2459 | "ctl %08x head %08x tail %08x start %08x\n", | |
2460 | I915_READ(PRB0_CTL), | |
2461 | I915_READ(PRB0_HEAD), | |
2462 | I915_READ(PRB0_TAIL), | |
2463 | I915_READ(PRB0_START)); | |
2464 | return -EIO; | |
2465 | } | |
2466 | ||
673a394b EA |
2467 | /* Update our cache of the ring state */ |
2468 | i915_kernel_lost_context(dev); | |
2469 | ||
2470 | return 0; | |
2471 | } | |
2472 | ||
2473 | static void | |
2474 | i915_gem_cleanup_ringbuffer(struct drm_device *dev) | |
2475 | { | |
2476 | drm_i915_private_t *dev_priv = dev->dev_private; | |
2477 | ||
2478 | if (dev_priv->ring.ring_obj == NULL) | |
2479 | return; | |
2480 | ||
2481 | drm_core_ioremapfree(&dev_priv->ring.map, dev); | |
2482 | ||
2483 | i915_gem_object_unpin(dev_priv->ring.ring_obj); | |
2484 | drm_gem_object_unreference(dev_priv->ring.ring_obj); | |
2485 | dev_priv->ring.ring_obj = NULL; | |
2486 | memset(&dev_priv->ring, 0, sizeof(dev_priv->ring)); | |
2487 | ||
2488 | if (dev_priv->hws_obj != NULL) { | |
ba1eb1d8 KP |
2489 | struct drm_gem_object *obj = dev_priv->hws_obj; |
2490 | struct drm_i915_gem_object *obj_priv = obj->driver_private; | |
2491 | ||
2492 | kunmap(obj_priv->page_list[0]); | |
2493 | i915_gem_object_unpin(obj); | |
2494 | drm_gem_object_unreference(obj); | |
673a394b EA |
2495 | dev_priv->hws_obj = NULL; |
2496 | memset(&dev_priv->hws_map, 0, sizeof(dev_priv->hws_map)); | |
ba1eb1d8 | 2497 | dev_priv->hw_status_page = NULL; |
673a394b EA |
2498 | |
2499 | /* Write high address into HWS_PGA when disabling. */ | |
2500 | I915_WRITE(HWS_PGA, 0x1ffff000); | |
2501 | } | |
2502 | } | |
2503 | ||
2504 | int | |
2505 | i915_gem_entervt_ioctl(struct drm_device *dev, void *data, | |
2506 | struct drm_file *file_priv) | |
2507 | { | |
2508 | drm_i915_private_t *dev_priv = dev->dev_private; | |
2509 | int ret; | |
2510 | ||
2511 | if (dev_priv->mm.wedged) { | |
2512 | DRM_ERROR("Reenabling wedged hardware, good luck\n"); | |
2513 | dev_priv->mm.wedged = 0; | |
2514 | } | |
2515 | ||
2516 | ret = i915_gem_init_ringbuffer(dev); | |
2517 | if (ret != 0) | |
2518 | return ret; | |
2519 | ||
2520 | mutex_lock(&dev->struct_mutex); | |
2521 | BUG_ON(!list_empty(&dev_priv->mm.active_list)); | |
2522 | BUG_ON(!list_empty(&dev_priv->mm.flushing_list)); | |
2523 | BUG_ON(!list_empty(&dev_priv->mm.inactive_list)); | |
2524 | BUG_ON(!list_empty(&dev_priv->mm.request_list)); | |
2525 | dev_priv->mm.suspended = 0; | |
2526 | mutex_unlock(&dev->struct_mutex); | |
dbb19d30 KH |
2527 | |
2528 | drm_irq_install(dev); | |
2529 | ||
673a394b EA |
2530 | return 0; |
2531 | } | |
2532 | ||
2533 | int | |
2534 | i915_gem_leavevt_ioctl(struct drm_device *dev, void *data, | |
2535 | struct drm_file *file_priv) | |
2536 | { | |
2537 | int ret; | |
2538 | ||
673a394b | 2539 | ret = i915_gem_idle(dev); |
dbb19d30 KH |
2540 | drm_irq_uninstall(dev); |
2541 | ||
6dbe2772 | 2542 | return ret; |
673a394b EA |
2543 | } |
2544 | ||
2545 | void | |
2546 | i915_gem_lastclose(struct drm_device *dev) | |
2547 | { | |
2548 | int ret; | |
673a394b | 2549 | |
6dbe2772 KP |
2550 | ret = i915_gem_idle(dev); |
2551 | if (ret) | |
2552 | DRM_ERROR("failed to idle hardware: %d\n", ret); | |
673a394b EA |
2553 | } |
2554 | ||
2555 | void | |
2556 | i915_gem_load(struct drm_device *dev) | |
2557 | { | |
2558 | drm_i915_private_t *dev_priv = dev->dev_private; | |
2559 | ||
2560 | INIT_LIST_HEAD(&dev_priv->mm.active_list); | |
2561 | INIT_LIST_HEAD(&dev_priv->mm.flushing_list); | |
2562 | INIT_LIST_HEAD(&dev_priv->mm.inactive_list); | |
2563 | INIT_LIST_HEAD(&dev_priv->mm.request_list); | |
2564 | INIT_DELAYED_WORK(&dev_priv->mm.retire_work, | |
2565 | i915_gem_retire_work_handler); | |
546b0974 EA |
2566 | INIT_WORK(&dev_priv->mm.vblank_work, |
2567 | i915_gem_vblank_work_handler); | |
673a394b EA |
2568 | dev_priv->mm.next_gem_seqno = 1; |
2569 | ||
2570 | i915_gem_detect_bit_6_swizzle(dev); | |
2571 | } |