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Commit | Line | Data |
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673a394b EA |
1 | /* |
2 | * Copyright © 2008 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | * | |
26 | */ | |
27 | ||
760285e7 DH |
28 | #include <drm/drmP.h> |
29 | #include <drm/i915_drm.h> | |
673a394b | 30 | #include "i915_drv.h" |
1c5d22f7 | 31 | #include "i915_trace.h" |
652c393a | 32 | #include "intel_drv.h" |
5949eac4 | 33 | #include <linux/shmem_fs.h> |
5a0e3ad6 | 34 | #include <linux/slab.h> |
673a394b | 35 | #include <linux/swap.h> |
79e53945 | 36 | #include <linux/pci.h> |
1286ff73 | 37 | #include <linux/dma-buf.h> |
673a394b | 38 | |
05394f39 CW |
39 | static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj); |
40 | static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj); | |
88241785 CW |
41 | static __must_check int i915_gem_object_bind_to_gtt(struct drm_i915_gem_object *obj, |
42 | unsigned alignment, | |
86a1ee26 CW |
43 | bool map_and_fenceable, |
44 | bool nonblocking); | |
05394f39 CW |
45 | static int i915_gem_phys_pwrite(struct drm_device *dev, |
46 | struct drm_i915_gem_object *obj, | |
71acb5eb | 47 | struct drm_i915_gem_pwrite *args, |
05394f39 | 48 | struct drm_file *file); |
673a394b | 49 | |
61050808 CW |
50 | static void i915_gem_write_fence(struct drm_device *dev, int reg, |
51 | struct drm_i915_gem_object *obj); | |
52 | static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj, | |
53 | struct drm_i915_fence_reg *fence, | |
54 | bool enable); | |
55 | ||
17250b71 | 56 | static int i915_gem_inactive_shrink(struct shrinker *shrinker, |
1495f230 | 57 | struct shrink_control *sc); |
6c085a72 CW |
58 | static long i915_gem_purge(struct drm_i915_private *dev_priv, long target); |
59 | static void i915_gem_shrink_all(struct drm_i915_private *dev_priv); | |
8c59967c | 60 | static void i915_gem_object_truncate(struct drm_i915_gem_object *obj); |
31169714 | 61 | |
61050808 CW |
62 | static inline void i915_gem_object_fence_lost(struct drm_i915_gem_object *obj) |
63 | { | |
64 | if (obj->tiling_mode) | |
65 | i915_gem_release_mmap(obj); | |
66 | ||
67 | /* As we do not have an associated fence register, we will force | |
68 | * a tiling change if we ever need to acquire one. | |
69 | */ | |
5d82e3e6 | 70 | obj->fence_dirty = false; |
61050808 CW |
71 | obj->fence_reg = I915_FENCE_REG_NONE; |
72 | } | |
73 | ||
73aa808f CW |
74 | /* some bookkeeping */ |
75 | static void i915_gem_info_add_obj(struct drm_i915_private *dev_priv, | |
76 | size_t size) | |
77 | { | |
78 | dev_priv->mm.object_count++; | |
79 | dev_priv->mm.object_memory += size; | |
80 | } | |
81 | ||
82 | static void i915_gem_info_remove_obj(struct drm_i915_private *dev_priv, | |
83 | size_t size) | |
84 | { | |
85 | dev_priv->mm.object_count--; | |
86 | dev_priv->mm.object_memory -= size; | |
87 | } | |
88 | ||
21dd3734 CW |
89 | static int |
90 | i915_gem_wait_for_error(struct drm_device *dev) | |
30dbf0c0 CW |
91 | { |
92 | struct drm_i915_private *dev_priv = dev->dev_private; | |
93 | struct completion *x = &dev_priv->error_completion; | |
94 | unsigned long flags; | |
95 | int ret; | |
96 | ||
97 | if (!atomic_read(&dev_priv->mm.wedged)) | |
98 | return 0; | |
99 | ||
0a6759c6 DV |
100 | /* |
101 | * Only wait 10 seconds for the gpu reset to complete to avoid hanging | |
102 | * userspace. If it takes that long something really bad is going on and | |
103 | * we should simply try to bail out and fail as gracefully as possible. | |
104 | */ | |
105 | ret = wait_for_completion_interruptible_timeout(x, 10*HZ); | |
106 | if (ret == 0) { | |
107 | DRM_ERROR("Timed out waiting for the gpu reset to complete\n"); | |
108 | return -EIO; | |
109 | } else if (ret < 0) { | |
30dbf0c0 | 110 | return ret; |
0a6759c6 | 111 | } |
30dbf0c0 | 112 | |
21dd3734 CW |
113 | if (atomic_read(&dev_priv->mm.wedged)) { |
114 | /* GPU is hung, bump the completion count to account for | |
115 | * the token we just consumed so that we never hit zero and | |
116 | * end up waiting upon a subsequent completion event that | |
117 | * will never happen. | |
118 | */ | |
119 | spin_lock_irqsave(&x->wait.lock, flags); | |
120 | x->done++; | |
121 | spin_unlock_irqrestore(&x->wait.lock, flags); | |
122 | } | |
123 | return 0; | |
30dbf0c0 CW |
124 | } |
125 | ||
54cf91dc | 126 | int i915_mutex_lock_interruptible(struct drm_device *dev) |
76c1dec1 | 127 | { |
76c1dec1 CW |
128 | int ret; |
129 | ||
21dd3734 | 130 | ret = i915_gem_wait_for_error(dev); |
76c1dec1 CW |
131 | if (ret) |
132 | return ret; | |
133 | ||
134 | ret = mutex_lock_interruptible(&dev->struct_mutex); | |
135 | if (ret) | |
136 | return ret; | |
137 | ||
23bc5982 | 138 | WARN_ON(i915_verify_lists(dev)); |
76c1dec1 CW |
139 | return 0; |
140 | } | |
30dbf0c0 | 141 | |
7d1c4804 | 142 | static inline bool |
05394f39 | 143 | i915_gem_object_is_inactive(struct drm_i915_gem_object *obj) |
7d1c4804 | 144 | { |
6c085a72 | 145 | return obj->gtt_space && !obj->active; |
7d1c4804 CW |
146 | } |
147 | ||
79e53945 JB |
148 | int |
149 | i915_gem_init_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 150 | struct drm_file *file) |
79e53945 JB |
151 | { |
152 | struct drm_i915_gem_init *args = data; | |
2021746e | 153 | |
7bb6fb8d DV |
154 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
155 | return -ENODEV; | |
156 | ||
2021746e CW |
157 | if (args->gtt_start >= args->gtt_end || |
158 | (args->gtt_end | args->gtt_start) & (PAGE_SIZE - 1)) | |
159 | return -EINVAL; | |
79e53945 | 160 | |
f534bc0b DV |
161 | /* GEM with user mode setting was never supported on ilk and later. */ |
162 | if (INTEL_INFO(dev)->gen >= 5) | |
163 | return -ENODEV; | |
164 | ||
79e53945 | 165 | mutex_lock(&dev->struct_mutex); |
644ec02b DV |
166 | i915_gem_init_global_gtt(dev, args->gtt_start, |
167 | args->gtt_end, args->gtt_end); | |
673a394b EA |
168 | mutex_unlock(&dev->struct_mutex); |
169 | ||
2021746e | 170 | return 0; |
673a394b EA |
171 | } |
172 | ||
5a125c3c EA |
173 | int |
174 | i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 175 | struct drm_file *file) |
5a125c3c | 176 | { |
73aa808f | 177 | struct drm_i915_private *dev_priv = dev->dev_private; |
5a125c3c | 178 | struct drm_i915_gem_get_aperture *args = data; |
6299f992 CW |
179 | struct drm_i915_gem_object *obj; |
180 | size_t pinned; | |
5a125c3c | 181 | |
6299f992 | 182 | pinned = 0; |
73aa808f | 183 | mutex_lock(&dev->struct_mutex); |
6c085a72 | 184 | list_for_each_entry(obj, &dev_priv->mm.bound_list, gtt_list) |
1b50247a CW |
185 | if (obj->pin_count) |
186 | pinned += obj->gtt_space->size; | |
73aa808f | 187 | mutex_unlock(&dev->struct_mutex); |
5a125c3c | 188 | |
6299f992 | 189 | args->aper_size = dev_priv->mm.gtt_total; |
0206e353 | 190 | args->aper_available_size = args->aper_size - pinned; |
6299f992 | 191 | |
5a125c3c EA |
192 | return 0; |
193 | } | |
194 | ||
42dcedd4 CW |
195 | void *i915_gem_object_alloc(struct drm_device *dev) |
196 | { | |
197 | struct drm_i915_private *dev_priv = dev->dev_private; | |
198 | return kmem_cache_alloc(dev_priv->slab, GFP_KERNEL | __GFP_ZERO); | |
199 | } | |
200 | ||
201 | void i915_gem_object_free(struct drm_i915_gem_object *obj) | |
202 | { | |
203 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; | |
204 | kmem_cache_free(dev_priv->slab, obj); | |
205 | } | |
206 | ||
ff72145b DA |
207 | static int |
208 | i915_gem_create(struct drm_file *file, | |
209 | struct drm_device *dev, | |
210 | uint64_t size, | |
211 | uint32_t *handle_p) | |
673a394b | 212 | { |
05394f39 | 213 | struct drm_i915_gem_object *obj; |
a1a2d1d3 PP |
214 | int ret; |
215 | u32 handle; | |
673a394b | 216 | |
ff72145b | 217 | size = roundup(size, PAGE_SIZE); |
8ffc0246 CW |
218 | if (size == 0) |
219 | return -EINVAL; | |
673a394b EA |
220 | |
221 | /* Allocate the new object */ | |
ff72145b | 222 | obj = i915_gem_alloc_object(dev, size); |
673a394b EA |
223 | if (obj == NULL) |
224 | return -ENOMEM; | |
225 | ||
05394f39 | 226 | ret = drm_gem_handle_create(file, &obj->base, &handle); |
1dfd9754 | 227 | if (ret) { |
05394f39 CW |
228 | drm_gem_object_release(&obj->base); |
229 | i915_gem_info_remove_obj(dev->dev_private, obj->base.size); | |
42dcedd4 | 230 | i915_gem_object_free(obj); |
673a394b | 231 | return ret; |
1dfd9754 | 232 | } |
673a394b | 233 | |
202f2fef | 234 | /* drop reference from allocate - handle holds it now */ |
05394f39 | 235 | drm_gem_object_unreference(&obj->base); |
202f2fef CW |
236 | trace_i915_gem_object_create(obj); |
237 | ||
ff72145b | 238 | *handle_p = handle; |
673a394b EA |
239 | return 0; |
240 | } | |
241 | ||
ff72145b DA |
242 | int |
243 | i915_gem_dumb_create(struct drm_file *file, | |
244 | struct drm_device *dev, | |
245 | struct drm_mode_create_dumb *args) | |
246 | { | |
247 | /* have to work out size/pitch and return them */ | |
ed0291fd | 248 | args->pitch = ALIGN(args->width * ((args->bpp + 7) / 8), 64); |
ff72145b DA |
249 | args->size = args->pitch * args->height; |
250 | return i915_gem_create(file, dev, | |
251 | args->size, &args->handle); | |
252 | } | |
253 | ||
254 | int i915_gem_dumb_destroy(struct drm_file *file, | |
255 | struct drm_device *dev, | |
256 | uint32_t handle) | |
257 | { | |
258 | return drm_gem_handle_delete(file, handle); | |
259 | } | |
260 | ||
261 | /** | |
262 | * Creates a new mm object and returns a handle to it. | |
263 | */ | |
264 | int | |
265 | i915_gem_create_ioctl(struct drm_device *dev, void *data, | |
266 | struct drm_file *file) | |
267 | { | |
268 | struct drm_i915_gem_create *args = data; | |
63ed2cb2 | 269 | |
ff72145b DA |
270 | return i915_gem_create(file, dev, |
271 | args->size, &args->handle); | |
272 | } | |
273 | ||
8461d226 DV |
274 | static inline int |
275 | __copy_to_user_swizzled(char __user *cpu_vaddr, | |
276 | const char *gpu_vaddr, int gpu_offset, | |
277 | int length) | |
278 | { | |
279 | int ret, cpu_offset = 0; | |
280 | ||
281 | while (length > 0) { | |
282 | int cacheline_end = ALIGN(gpu_offset + 1, 64); | |
283 | int this_length = min(cacheline_end - gpu_offset, length); | |
284 | int swizzled_gpu_offset = gpu_offset ^ 64; | |
285 | ||
286 | ret = __copy_to_user(cpu_vaddr + cpu_offset, | |
287 | gpu_vaddr + swizzled_gpu_offset, | |
288 | this_length); | |
289 | if (ret) | |
290 | return ret + length; | |
291 | ||
292 | cpu_offset += this_length; | |
293 | gpu_offset += this_length; | |
294 | length -= this_length; | |
295 | } | |
296 | ||
297 | return 0; | |
298 | } | |
299 | ||
8c59967c | 300 | static inline int |
4f0c7cfb BW |
301 | __copy_from_user_swizzled(char *gpu_vaddr, int gpu_offset, |
302 | const char __user *cpu_vaddr, | |
8c59967c DV |
303 | int length) |
304 | { | |
305 | int ret, cpu_offset = 0; | |
306 | ||
307 | while (length > 0) { | |
308 | int cacheline_end = ALIGN(gpu_offset + 1, 64); | |
309 | int this_length = min(cacheline_end - gpu_offset, length); | |
310 | int swizzled_gpu_offset = gpu_offset ^ 64; | |
311 | ||
312 | ret = __copy_from_user(gpu_vaddr + swizzled_gpu_offset, | |
313 | cpu_vaddr + cpu_offset, | |
314 | this_length); | |
315 | if (ret) | |
316 | return ret + length; | |
317 | ||
318 | cpu_offset += this_length; | |
319 | gpu_offset += this_length; | |
320 | length -= this_length; | |
321 | } | |
322 | ||
323 | return 0; | |
324 | } | |
325 | ||
d174bd64 DV |
326 | /* Per-page copy function for the shmem pread fastpath. |
327 | * Flushes invalid cachelines before reading the target if | |
328 | * needs_clflush is set. */ | |
eb01459f | 329 | static int |
d174bd64 DV |
330 | shmem_pread_fast(struct page *page, int shmem_page_offset, int page_length, |
331 | char __user *user_data, | |
332 | bool page_do_bit17_swizzling, bool needs_clflush) | |
333 | { | |
334 | char *vaddr; | |
335 | int ret; | |
336 | ||
e7e58eb5 | 337 | if (unlikely(page_do_bit17_swizzling)) |
d174bd64 DV |
338 | return -EINVAL; |
339 | ||
340 | vaddr = kmap_atomic(page); | |
341 | if (needs_clflush) | |
342 | drm_clflush_virt_range(vaddr + shmem_page_offset, | |
343 | page_length); | |
344 | ret = __copy_to_user_inatomic(user_data, | |
345 | vaddr + shmem_page_offset, | |
346 | page_length); | |
347 | kunmap_atomic(vaddr); | |
348 | ||
f60d7f0c | 349 | return ret ? -EFAULT : 0; |
d174bd64 DV |
350 | } |
351 | ||
23c18c71 DV |
352 | static void |
353 | shmem_clflush_swizzled_range(char *addr, unsigned long length, | |
354 | bool swizzled) | |
355 | { | |
e7e58eb5 | 356 | if (unlikely(swizzled)) { |
23c18c71 DV |
357 | unsigned long start = (unsigned long) addr; |
358 | unsigned long end = (unsigned long) addr + length; | |
359 | ||
360 | /* For swizzling simply ensure that we always flush both | |
361 | * channels. Lame, but simple and it works. Swizzled | |
362 | * pwrite/pread is far from a hotpath - current userspace | |
363 | * doesn't use it at all. */ | |
364 | start = round_down(start, 128); | |
365 | end = round_up(end, 128); | |
366 | ||
367 | drm_clflush_virt_range((void *)start, end - start); | |
368 | } else { | |
369 | drm_clflush_virt_range(addr, length); | |
370 | } | |
371 | ||
372 | } | |
373 | ||
d174bd64 DV |
374 | /* Only difference to the fast-path function is that this can handle bit17 |
375 | * and uses non-atomic copy and kmap functions. */ | |
376 | static int | |
377 | shmem_pread_slow(struct page *page, int shmem_page_offset, int page_length, | |
378 | char __user *user_data, | |
379 | bool page_do_bit17_swizzling, bool needs_clflush) | |
380 | { | |
381 | char *vaddr; | |
382 | int ret; | |
383 | ||
384 | vaddr = kmap(page); | |
385 | if (needs_clflush) | |
23c18c71 DV |
386 | shmem_clflush_swizzled_range(vaddr + shmem_page_offset, |
387 | page_length, | |
388 | page_do_bit17_swizzling); | |
d174bd64 DV |
389 | |
390 | if (page_do_bit17_swizzling) | |
391 | ret = __copy_to_user_swizzled(user_data, | |
392 | vaddr, shmem_page_offset, | |
393 | page_length); | |
394 | else | |
395 | ret = __copy_to_user(user_data, | |
396 | vaddr + shmem_page_offset, | |
397 | page_length); | |
398 | kunmap(page); | |
399 | ||
f60d7f0c | 400 | return ret ? - EFAULT : 0; |
d174bd64 DV |
401 | } |
402 | ||
eb01459f | 403 | static int |
dbf7bff0 DV |
404 | i915_gem_shmem_pread(struct drm_device *dev, |
405 | struct drm_i915_gem_object *obj, | |
406 | struct drm_i915_gem_pread *args, | |
407 | struct drm_file *file) | |
eb01459f | 408 | { |
8461d226 | 409 | char __user *user_data; |
eb01459f | 410 | ssize_t remain; |
8461d226 | 411 | loff_t offset; |
eb2c0c81 | 412 | int shmem_page_offset, page_length, ret = 0; |
8461d226 | 413 | int obj_do_bit17_swizzling, page_do_bit17_swizzling; |
96d79b52 | 414 | int prefaulted = 0; |
8489731c | 415 | int needs_clflush = 0; |
9da3da66 CW |
416 | struct scatterlist *sg; |
417 | int i; | |
eb01459f | 418 | |
8461d226 | 419 | user_data = (char __user *) (uintptr_t) args->data_ptr; |
eb01459f EA |
420 | remain = args->size; |
421 | ||
8461d226 | 422 | obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj); |
eb01459f | 423 | |
8489731c DV |
424 | if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU)) { |
425 | /* If we're not in the cpu read domain, set ourself into the gtt | |
426 | * read domain and manually flush cachelines (if required). This | |
427 | * optimizes for the case when the gpu will dirty the data | |
428 | * anyway again before the next pread happens. */ | |
429 | if (obj->cache_level == I915_CACHE_NONE) | |
430 | needs_clflush = 1; | |
6c085a72 CW |
431 | if (obj->gtt_space) { |
432 | ret = i915_gem_object_set_to_gtt_domain(obj, false); | |
433 | if (ret) | |
434 | return ret; | |
435 | } | |
8489731c | 436 | } |
eb01459f | 437 | |
f60d7f0c CW |
438 | ret = i915_gem_object_get_pages(obj); |
439 | if (ret) | |
440 | return ret; | |
441 | ||
442 | i915_gem_object_pin_pages(obj); | |
443 | ||
8461d226 | 444 | offset = args->offset; |
eb01459f | 445 | |
9da3da66 | 446 | for_each_sg(obj->pages->sgl, sg, obj->pages->nents, i) { |
e5281ccd CW |
447 | struct page *page; |
448 | ||
9da3da66 CW |
449 | if (i < offset >> PAGE_SHIFT) |
450 | continue; | |
451 | ||
452 | if (remain <= 0) | |
453 | break; | |
454 | ||
eb01459f EA |
455 | /* Operation in this page |
456 | * | |
eb01459f | 457 | * shmem_page_offset = offset within page in shmem file |
eb01459f EA |
458 | * page_length = bytes to copy for this page |
459 | */ | |
c8cbbb8b | 460 | shmem_page_offset = offset_in_page(offset); |
eb01459f EA |
461 | page_length = remain; |
462 | if ((shmem_page_offset + page_length) > PAGE_SIZE) | |
463 | page_length = PAGE_SIZE - shmem_page_offset; | |
eb01459f | 464 | |
9da3da66 | 465 | page = sg_page(sg); |
8461d226 DV |
466 | page_do_bit17_swizzling = obj_do_bit17_swizzling && |
467 | (page_to_phys(page) & (1 << 17)) != 0; | |
468 | ||
d174bd64 DV |
469 | ret = shmem_pread_fast(page, shmem_page_offset, page_length, |
470 | user_data, page_do_bit17_swizzling, | |
471 | needs_clflush); | |
472 | if (ret == 0) | |
473 | goto next_page; | |
dbf7bff0 | 474 | |
dbf7bff0 DV |
475 | mutex_unlock(&dev->struct_mutex); |
476 | ||
96d79b52 | 477 | if (!prefaulted) { |
f56f821f | 478 | ret = fault_in_multipages_writeable(user_data, remain); |
96d79b52 DV |
479 | /* Userspace is tricking us, but we've already clobbered |
480 | * its pages with the prefault and promised to write the | |
481 | * data up to the first fault. Hence ignore any errors | |
482 | * and just continue. */ | |
483 | (void)ret; | |
484 | prefaulted = 1; | |
485 | } | |
eb01459f | 486 | |
d174bd64 DV |
487 | ret = shmem_pread_slow(page, shmem_page_offset, page_length, |
488 | user_data, page_do_bit17_swizzling, | |
489 | needs_clflush); | |
eb01459f | 490 | |
dbf7bff0 | 491 | mutex_lock(&dev->struct_mutex); |
f60d7f0c | 492 | |
dbf7bff0 | 493 | next_page: |
e5281ccd | 494 | mark_page_accessed(page); |
e5281ccd | 495 | |
f60d7f0c | 496 | if (ret) |
8461d226 | 497 | goto out; |
8461d226 | 498 | |
eb01459f | 499 | remain -= page_length; |
8461d226 | 500 | user_data += page_length; |
eb01459f EA |
501 | offset += page_length; |
502 | } | |
503 | ||
4f27b75d | 504 | out: |
f60d7f0c CW |
505 | i915_gem_object_unpin_pages(obj); |
506 | ||
eb01459f EA |
507 | return ret; |
508 | } | |
509 | ||
673a394b EA |
510 | /** |
511 | * Reads data from the object referenced by handle. | |
512 | * | |
513 | * On error, the contents of *data are undefined. | |
514 | */ | |
515 | int | |
516 | i915_gem_pread_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 517 | struct drm_file *file) |
673a394b EA |
518 | { |
519 | struct drm_i915_gem_pread *args = data; | |
05394f39 | 520 | struct drm_i915_gem_object *obj; |
35b62a89 | 521 | int ret = 0; |
673a394b | 522 | |
51311d0a CW |
523 | if (args->size == 0) |
524 | return 0; | |
525 | ||
526 | if (!access_ok(VERIFY_WRITE, | |
527 | (char __user *)(uintptr_t)args->data_ptr, | |
528 | args->size)) | |
529 | return -EFAULT; | |
530 | ||
4f27b75d | 531 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 532 | if (ret) |
4f27b75d | 533 | return ret; |
673a394b | 534 | |
05394f39 | 535 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 536 | if (&obj->base == NULL) { |
1d7cfea1 CW |
537 | ret = -ENOENT; |
538 | goto unlock; | |
4f27b75d | 539 | } |
673a394b | 540 | |
7dcd2499 | 541 | /* Bounds check source. */ |
05394f39 CW |
542 | if (args->offset > obj->base.size || |
543 | args->size > obj->base.size - args->offset) { | |
ce9d419d | 544 | ret = -EINVAL; |
35b62a89 | 545 | goto out; |
ce9d419d CW |
546 | } |
547 | ||
1286ff73 DV |
548 | /* prime objects have no backing filp to GEM pread/pwrite |
549 | * pages from. | |
550 | */ | |
551 | if (!obj->base.filp) { | |
552 | ret = -EINVAL; | |
553 | goto out; | |
554 | } | |
555 | ||
db53a302 CW |
556 | trace_i915_gem_object_pread(obj, args->offset, args->size); |
557 | ||
dbf7bff0 | 558 | ret = i915_gem_shmem_pread(dev, obj, args, file); |
673a394b | 559 | |
35b62a89 | 560 | out: |
05394f39 | 561 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 562 | unlock: |
4f27b75d | 563 | mutex_unlock(&dev->struct_mutex); |
eb01459f | 564 | return ret; |
673a394b EA |
565 | } |
566 | ||
0839ccb8 KP |
567 | /* This is the fast write path which cannot handle |
568 | * page faults in the source data | |
9b7530cc | 569 | */ |
0839ccb8 KP |
570 | |
571 | static inline int | |
572 | fast_user_write(struct io_mapping *mapping, | |
573 | loff_t page_base, int page_offset, | |
574 | char __user *user_data, | |
575 | int length) | |
9b7530cc | 576 | { |
4f0c7cfb BW |
577 | void __iomem *vaddr_atomic; |
578 | void *vaddr; | |
0839ccb8 | 579 | unsigned long unwritten; |
9b7530cc | 580 | |
3e4d3af5 | 581 | vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base); |
4f0c7cfb BW |
582 | /* We can use the cpu mem copy function because this is X86. */ |
583 | vaddr = (void __force*)vaddr_atomic + page_offset; | |
584 | unwritten = __copy_from_user_inatomic_nocache(vaddr, | |
0839ccb8 | 585 | user_data, length); |
3e4d3af5 | 586 | io_mapping_unmap_atomic(vaddr_atomic); |
fbd5a26d | 587 | return unwritten; |
0839ccb8 KP |
588 | } |
589 | ||
3de09aa3 EA |
590 | /** |
591 | * This is the fast pwrite path, where we copy the data directly from the | |
592 | * user into the GTT, uncached. | |
593 | */ | |
673a394b | 594 | static int |
05394f39 CW |
595 | i915_gem_gtt_pwrite_fast(struct drm_device *dev, |
596 | struct drm_i915_gem_object *obj, | |
3de09aa3 | 597 | struct drm_i915_gem_pwrite *args, |
05394f39 | 598 | struct drm_file *file) |
673a394b | 599 | { |
0839ccb8 | 600 | drm_i915_private_t *dev_priv = dev->dev_private; |
673a394b | 601 | ssize_t remain; |
0839ccb8 | 602 | loff_t offset, page_base; |
673a394b | 603 | char __user *user_data; |
935aaa69 DV |
604 | int page_offset, page_length, ret; |
605 | ||
86a1ee26 | 606 | ret = i915_gem_object_pin(obj, 0, true, true); |
935aaa69 DV |
607 | if (ret) |
608 | goto out; | |
609 | ||
610 | ret = i915_gem_object_set_to_gtt_domain(obj, true); | |
611 | if (ret) | |
612 | goto out_unpin; | |
613 | ||
614 | ret = i915_gem_object_put_fence(obj); | |
615 | if (ret) | |
616 | goto out_unpin; | |
673a394b EA |
617 | |
618 | user_data = (char __user *) (uintptr_t) args->data_ptr; | |
619 | remain = args->size; | |
673a394b | 620 | |
05394f39 | 621 | offset = obj->gtt_offset + args->offset; |
673a394b EA |
622 | |
623 | while (remain > 0) { | |
624 | /* Operation in this page | |
625 | * | |
0839ccb8 KP |
626 | * page_base = page offset within aperture |
627 | * page_offset = offset within page | |
628 | * page_length = bytes to copy for this page | |
673a394b | 629 | */ |
c8cbbb8b CW |
630 | page_base = offset & PAGE_MASK; |
631 | page_offset = offset_in_page(offset); | |
0839ccb8 KP |
632 | page_length = remain; |
633 | if ((page_offset + remain) > PAGE_SIZE) | |
634 | page_length = PAGE_SIZE - page_offset; | |
635 | ||
0839ccb8 | 636 | /* If we get a fault while copying data, then (presumably) our |
3de09aa3 EA |
637 | * source page isn't available. Return the error and we'll |
638 | * retry in the slow path. | |
0839ccb8 | 639 | */ |
fbd5a26d | 640 | if (fast_user_write(dev_priv->mm.gtt_mapping, page_base, |
935aaa69 DV |
641 | page_offset, user_data, page_length)) { |
642 | ret = -EFAULT; | |
643 | goto out_unpin; | |
644 | } | |
673a394b | 645 | |
0839ccb8 KP |
646 | remain -= page_length; |
647 | user_data += page_length; | |
648 | offset += page_length; | |
673a394b | 649 | } |
673a394b | 650 | |
935aaa69 DV |
651 | out_unpin: |
652 | i915_gem_object_unpin(obj); | |
653 | out: | |
3de09aa3 | 654 | return ret; |
673a394b EA |
655 | } |
656 | ||
d174bd64 DV |
657 | /* Per-page copy function for the shmem pwrite fastpath. |
658 | * Flushes invalid cachelines before writing to the target if | |
659 | * needs_clflush_before is set and flushes out any written cachelines after | |
660 | * writing if needs_clflush is set. */ | |
3043c60c | 661 | static int |
d174bd64 DV |
662 | shmem_pwrite_fast(struct page *page, int shmem_page_offset, int page_length, |
663 | char __user *user_data, | |
664 | bool page_do_bit17_swizzling, | |
665 | bool needs_clflush_before, | |
666 | bool needs_clflush_after) | |
673a394b | 667 | { |
d174bd64 | 668 | char *vaddr; |
673a394b | 669 | int ret; |
3de09aa3 | 670 | |
e7e58eb5 | 671 | if (unlikely(page_do_bit17_swizzling)) |
d174bd64 | 672 | return -EINVAL; |
3de09aa3 | 673 | |
d174bd64 DV |
674 | vaddr = kmap_atomic(page); |
675 | if (needs_clflush_before) | |
676 | drm_clflush_virt_range(vaddr + shmem_page_offset, | |
677 | page_length); | |
678 | ret = __copy_from_user_inatomic_nocache(vaddr + shmem_page_offset, | |
679 | user_data, | |
680 | page_length); | |
681 | if (needs_clflush_after) | |
682 | drm_clflush_virt_range(vaddr + shmem_page_offset, | |
683 | page_length); | |
684 | kunmap_atomic(vaddr); | |
3de09aa3 | 685 | |
755d2218 | 686 | return ret ? -EFAULT : 0; |
3de09aa3 EA |
687 | } |
688 | ||
d174bd64 DV |
689 | /* Only difference to the fast-path function is that this can handle bit17 |
690 | * and uses non-atomic copy and kmap functions. */ | |
3043c60c | 691 | static int |
d174bd64 DV |
692 | shmem_pwrite_slow(struct page *page, int shmem_page_offset, int page_length, |
693 | char __user *user_data, | |
694 | bool page_do_bit17_swizzling, | |
695 | bool needs_clflush_before, | |
696 | bool needs_clflush_after) | |
673a394b | 697 | { |
d174bd64 DV |
698 | char *vaddr; |
699 | int ret; | |
e5281ccd | 700 | |
d174bd64 | 701 | vaddr = kmap(page); |
e7e58eb5 | 702 | if (unlikely(needs_clflush_before || page_do_bit17_swizzling)) |
23c18c71 DV |
703 | shmem_clflush_swizzled_range(vaddr + shmem_page_offset, |
704 | page_length, | |
705 | page_do_bit17_swizzling); | |
d174bd64 DV |
706 | if (page_do_bit17_swizzling) |
707 | ret = __copy_from_user_swizzled(vaddr, shmem_page_offset, | |
e5281ccd CW |
708 | user_data, |
709 | page_length); | |
d174bd64 DV |
710 | else |
711 | ret = __copy_from_user(vaddr + shmem_page_offset, | |
712 | user_data, | |
713 | page_length); | |
714 | if (needs_clflush_after) | |
23c18c71 DV |
715 | shmem_clflush_swizzled_range(vaddr + shmem_page_offset, |
716 | page_length, | |
717 | page_do_bit17_swizzling); | |
d174bd64 | 718 | kunmap(page); |
40123c1f | 719 | |
755d2218 | 720 | return ret ? -EFAULT : 0; |
40123c1f EA |
721 | } |
722 | ||
40123c1f | 723 | static int |
e244a443 DV |
724 | i915_gem_shmem_pwrite(struct drm_device *dev, |
725 | struct drm_i915_gem_object *obj, | |
726 | struct drm_i915_gem_pwrite *args, | |
727 | struct drm_file *file) | |
40123c1f | 728 | { |
40123c1f | 729 | ssize_t remain; |
8c59967c DV |
730 | loff_t offset; |
731 | char __user *user_data; | |
eb2c0c81 | 732 | int shmem_page_offset, page_length, ret = 0; |
8c59967c | 733 | int obj_do_bit17_swizzling, page_do_bit17_swizzling; |
e244a443 | 734 | int hit_slowpath = 0; |
58642885 DV |
735 | int needs_clflush_after = 0; |
736 | int needs_clflush_before = 0; | |
9da3da66 CW |
737 | int i; |
738 | struct scatterlist *sg; | |
40123c1f | 739 | |
8c59967c | 740 | user_data = (char __user *) (uintptr_t) args->data_ptr; |
40123c1f EA |
741 | remain = args->size; |
742 | ||
8c59967c | 743 | obj_do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj); |
40123c1f | 744 | |
58642885 DV |
745 | if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) { |
746 | /* If we're not in the cpu write domain, set ourself into the gtt | |
747 | * write domain and manually flush cachelines (if required). This | |
748 | * optimizes for the case when the gpu will use the data | |
749 | * right away and we therefore have to clflush anyway. */ | |
750 | if (obj->cache_level == I915_CACHE_NONE) | |
751 | needs_clflush_after = 1; | |
6c085a72 CW |
752 | if (obj->gtt_space) { |
753 | ret = i915_gem_object_set_to_gtt_domain(obj, true); | |
754 | if (ret) | |
755 | return ret; | |
756 | } | |
58642885 DV |
757 | } |
758 | /* Same trick applies for invalidate partially written cachelines before | |
759 | * writing. */ | |
760 | if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU) | |
761 | && obj->cache_level == I915_CACHE_NONE) | |
762 | needs_clflush_before = 1; | |
763 | ||
755d2218 CW |
764 | ret = i915_gem_object_get_pages(obj); |
765 | if (ret) | |
766 | return ret; | |
767 | ||
768 | i915_gem_object_pin_pages(obj); | |
769 | ||
673a394b | 770 | offset = args->offset; |
05394f39 | 771 | obj->dirty = 1; |
673a394b | 772 | |
9da3da66 | 773 | for_each_sg(obj->pages->sgl, sg, obj->pages->nents, i) { |
e5281ccd | 774 | struct page *page; |
58642885 | 775 | int partial_cacheline_write; |
e5281ccd | 776 | |
9da3da66 CW |
777 | if (i < offset >> PAGE_SHIFT) |
778 | continue; | |
779 | ||
780 | if (remain <= 0) | |
781 | break; | |
782 | ||
40123c1f EA |
783 | /* Operation in this page |
784 | * | |
40123c1f | 785 | * shmem_page_offset = offset within page in shmem file |
40123c1f EA |
786 | * page_length = bytes to copy for this page |
787 | */ | |
c8cbbb8b | 788 | shmem_page_offset = offset_in_page(offset); |
40123c1f EA |
789 | |
790 | page_length = remain; | |
791 | if ((shmem_page_offset + page_length) > PAGE_SIZE) | |
792 | page_length = PAGE_SIZE - shmem_page_offset; | |
40123c1f | 793 | |
58642885 DV |
794 | /* If we don't overwrite a cacheline completely we need to be |
795 | * careful to have up-to-date data by first clflushing. Don't | |
796 | * overcomplicate things and flush the entire patch. */ | |
797 | partial_cacheline_write = needs_clflush_before && | |
798 | ((shmem_page_offset | page_length) | |
799 | & (boot_cpu_data.x86_clflush_size - 1)); | |
800 | ||
9da3da66 | 801 | page = sg_page(sg); |
8c59967c DV |
802 | page_do_bit17_swizzling = obj_do_bit17_swizzling && |
803 | (page_to_phys(page) & (1 << 17)) != 0; | |
804 | ||
d174bd64 DV |
805 | ret = shmem_pwrite_fast(page, shmem_page_offset, page_length, |
806 | user_data, page_do_bit17_swizzling, | |
807 | partial_cacheline_write, | |
808 | needs_clflush_after); | |
809 | if (ret == 0) | |
810 | goto next_page; | |
e244a443 DV |
811 | |
812 | hit_slowpath = 1; | |
e244a443 | 813 | mutex_unlock(&dev->struct_mutex); |
d174bd64 DV |
814 | ret = shmem_pwrite_slow(page, shmem_page_offset, page_length, |
815 | user_data, page_do_bit17_swizzling, | |
816 | partial_cacheline_write, | |
817 | needs_clflush_after); | |
40123c1f | 818 | |
e244a443 | 819 | mutex_lock(&dev->struct_mutex); |
755d2218 | 820 | |
e244a443 | 821 | next_page: |
e5281ccd CW |
822 | set_page_dirty(page); |
823 | mark_page_accessed(page); | |
e5281ccd | 824 | |
755d2218 | 825 | if (ret) |
8c59967c | 826 | goto out; |
8c59967c | 827 | |
40123c1f | 828 | remain -= page_length; |
8c59967c | 829 | user_data += page_length; |
40123c1f | 830 | offset += page_length; |
673a394b EA |
831 | } |
832 | ||
fbd5a26d | 833 | out: |
755d2218 CW |
834 | i915_gem_object_unpin_pages(obj); |
835 | ||
e244a443 | 836 | if (hit_slowpath) { |
8dcf015e DV |
837 | /* |
838 | * Fixup: Flush cpu caches in case we didn't flush the dirty | |
839 | * cachelines in-line while writing and the object moved | |
840 | * out of the cpu write domain while we've dropped the lock. | |
841 | */ | |
842 | if (!needs_clflush_after && | |
843 | obj->base.write_domain != I915_GEM_DOMAIN_CPU) { | |
e244a443 | 844 | i915_gem_clflush_object(obj); |
e76e9aeb | 845 | i915_gem_chipset_flush(dev); |
e244a443 | 846 | } |
8c59967c | 847 | } |
673a394b | 848 | |
58642885 | 849 | if (needs_clflush_after) |
e76e9aeb | 850 | i915_gem_chipset_flush(dev); |
58642885 | 851 | |
40123c1f | 852 | return ret; |
673a394b EA |
853 | } |
854 | ||
855 | /** | |
856 | * Writes data to the object referenced by handle. | |
857 | * | |
858 | * On error, the contents of the buffer that were to be modified are undefined. | |
859 | */ | |
860 | int | |
861 | i915_gem_pwrite_ioctl(struct drm_device *dev, void *data, | |
fbd5a26d | 862 | struct drm_file *file) |
673a394b EA |
863 | { |
864 | struct drm_i915_gem_pwrite *args = data; | |
05394f39 | 865 | struct drm_i915_gem_object *obj; |
51311d0a CW |
866 | int ret; |
867 | ||
868 | if (args->size == 0) | |
869 | return 0; | |
870 | ||
871 | if (!access_ok(VERIFY_READ, | |
872 | (char __user *)(uintptr_t)args->data_ptr, | |
873 | args->size)) | |
874 | return -EFAULT; | |
875 | ||
f56f821f DV |
876 | ret = fault_in_multipages_readable((char __user *)(uintptr_t)args->data_ptr, |
877 | args->size); | |
51311d0a CW |
878 | if (ret) |
879 | return -EFAULT; | |
673a394b | 880 | |
fbd5a26d | 881 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 882 | if (ret) |
fbd5a26d | 883 | return ret; |
1d7cfea1 | 884 | |
05394f39 | 885 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 886 | if (&obj->base == NULL) { |
1d7cfea1 CW |
887 | ret = -ENOENT; |
888 | goto unlock; | |
fbd5a26d | 889 | } |
673a394b | 890 | |
7dcd2499 | 891 | /* Bounds check destination. */ |
05394f39 CW |
892 | if (args->offset > obj->base.size || |
893 | args->size > obj->base.size - args->offset) { | |
ce9d419d | 894 | ret = -EINVAL; |
35b62a89 | 895 | goto out; |
ce9d419d CW |
896 | } |
897 | ||
1286ff73 DV |
898 | /* prime objects have no backing filp to GEM pread/pwrite |
899 | * pages from. | |
900 | */ | |
901 | if (!obj->base.filp) { | |
902 | ret = -EINVAL; | |
903 | goto out; | |
904 | } | |
905 | ||
db53a302 CW |
906 | trace_i915_gem_object_pwrite(obj, args->offset, args->size); |
907 | ||
935aaa69 | 908 | ret = -EFAULT; |
673a394b EA |
909 | /* We can only do the GTT pwrite on untiled buffers, as otherwise |
910 | * it would end up going through the fenced access, and we'll get | |
911 | * different detiling behavior between reading and writing. | |
912 | * pread/pwrite currently are reading and writing from the CPU | |
913 | * perspective, requiring manual detiling by the client. | |
914 | */ | |
5c0480f2 | 915 | if (obj->phys_obj) { |
fbd5a26d | 916 | ret = i915_gem_phys_pwrite(dev, obj, args, file); |
5c0480f2 DV |
917 | goto out; |
918 | } | |
919 | ||
86a1ee26 | 920 | if (obj->cache_level == I915_CACHE_NONE && |
c07496fa | 921 | obj->tiling_mode == I915_TILING_NONE && |
5c0480f2 | 922 | obj->base.write_domain != I915_GEM_DOMAIN_CPU) { |
fbd5a26d | 923 | ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file); |
935aaa69 DV |
924 | /* Note that the gtt paths might fail with non-page-backed user |
925 | * pointers (e.g. gtt mappings when moving data between | |
926 | * textures). Fallback to the shmem path in that case. */ | |
fbd5a26d | 927 | } |
673a394b | 928 | |
86a1ee26 | 929 | if (ret == -EFAULT || ret == -ENOSPC) |
935aaa69 | 930 | ret = i915_gem_shmem_pwrite(dev, obj, args, file); |
5c0480f2 | 931 | |
35b62a89 | 932 | out: |
05394f39 | 933 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 934 | unlock: |
fbd5a26d | 935 | mutex_unlock(&dev->struct_mutex); |
673a394b EA |
936 | return ret; |
937 | } | |
938 | ||
b361237b CW |
939 | int |
940 | i915_gem_check_wedge(struct drm_i915_private *dev_priv, | |
941 | bool interruptible) | |
942 | { | |
943 | if (atomic_read(&dev_priv->mm.wedged)) { | |
944 | struct completion *x = &dev_priv->error_completion; | |
945 | bool recovery_complete; | |
946 | unsigned long flags; | |
947 | ||
948 | /* Give the error handler a chance to run. */ | |
949 | spin_lock_irqsave(&x->wait.lock, flags); | |
950 | recovery_complete = x->done > 0; | |
951 | spin_unlock_irqrestore(&x->wait.lock, flags); | |
952 | ||
953 | /* Non-interruptible callers can't handle -EAGAIN, hence return | |
954 | * -EIO unconditionally for these. */ | |
955 | if (!interruptible) | |
956 | return -EIO; | |
957 | ||
958 | /* Recovery complete, but still wedged means reset failure. */ | |
959 | if (recovery_complete) | |
960 | return -EIO; | |
961 | ||
962 | return -EAGAIN; | |
963 | } | |
964 | ||
965 | return 0; | |
966 | } | |
967 | ||
968 | /* | |
969 | * Compare seqno against outstanding lazy request. Emit a request if they are | |
970 | * equal. | |
971 | */ | |
972 | static int | |
973 | i915_gem_check_olr(struct intel_ring_buffer *ring, u32 seqno) | |
974 | { | |
975 | int ret; | |
976 | ||
977 | BUG_ON(!mutex_is_locked(&ring->dev->struct_mutex)); | |
978 | ||
979 | ret = 0; | |
980 | if (seqno == ring->outstanding_lazy_request) | |
981 | ret = i915_add_request(ring, NULL, NULL); | |
982 | ||
983 | return ret; | |
984 | } | |
985 | ||
986 | /** | |
987 | * __wait_seqno - wait until execution of seqno has finished | |
988 | * @ring: the ring expected to report seqno | |
989 | * @seqno: duh! | |
990 | * @interruptible: do an interruptible wait (normally yes) | |
991 | * @timeout: in - how long to wait (NULL forever); out - how much time remaining | |
992 | * | |
993 | * Returns 0 if the seqno was found within the alloted time. Else returns the | |
994 | * errno with remaining time filled in timeout argument. | |
995 | */ | |
996 | static int __wait_seqno(struct intel_ring_buffer *ring, u32 seqno, | |
997 | bool interruptible, struct timespec *timeout) | |
998 | { | |
999 | drm_i915_private_t *dev_priv = ring->dev->dev_private; | |
1000 | struct timespec before, now, wait_time={1,0}; | |
1001 | unsigned long timeout_jiffies; | |
1002 | long end; | |
1003 | bool wait_forever = true; | |
1004 | int ret; | |
1005 | ||
1006 | if (i915_seqno_passed(ring->get_seqno(ring, true), seqno)) | |
1007 | return 0; | |
1008 | ||
1009 | trace_i915_gem_request_wait_begin(ring, seqno); | |
1010 | ||
1011 | if (timeout != NULL) { | |
1012 | wait_time = *timeout; | |
1013 | wait_forever = false; | |
1014 | } | |
1015 | ||
1016 | timeout_jiffies = timespec_to_jiffies(&wait_time); | |
1017 | ||
1018 | if (WARN_ON(!ring->irq_get(ring))) | |
1019 | return -ENODEV; | |
1020 | ||
1021 | /* Record current time in case interrupted by signal, or wedged * */ | |
1022 | getrawmonotonic(&before); | |
1023 | ||
1024 | #define EXIT_COND \ | |
1025 | (i915_seqno_passed(ring->get_seqno(ring, false), seqno) || \ | |
1026 | atomic_read(&dev_priv->mm.wedged)) | |
1027 | do { | |
1028 | if (interruptible) | |
1029 | end = wait_event_interruptible_timeout(ring->irq_queue, | |
1030 | EXIT_COND, | |
1031 | timeout_jiffies); | |
1032 | else | |
1033 | end = wait_event_timeout(ring->irq_queue, EXIT_COND, | |
1034 | timeout_jiffies); | |
1035 | ||
1036 | ret = i915_gem_check_wedge(dev_priv, interruptible); | |
1037 | if (ret) | |
1038 | end = ret; | |
1039 | } while (end == 0 && wait_forever); | |
1040 | ||
1041 | getrawmonotonic(&now); | |
1042 | ||
1043 | ring->irq_put(ring); | |
1044 | trace_i915_gem_request_wait_end(ring, seqno); | |
1045 | #undef EXIT_COND | |
1046 | ||
1047 | if (timeout) { | |
1048 | struct timespec sleep_time = timespec_sub(now, before); | |
1049 | *timeout = timespec_sub(*timeout, sleep_time); | |
1050 | } | |
1051 | ||
1052 | switch (end) { | |
1053 | case -EIO: | |
1054 | case -EAGAIN: /* Wedged */ | |
1055 | case -ERESTARTSYS: /* Signal */ | |
1056 | return (int)end; | |
1057 | case 0: /* Timeout */ | |
1058 | if (timeout) | |
1059 | set_normalized_timespec(timeout, 0, 0); | |
1060 | return -ETIME; | |
1061 | default: /* Completed */ | |
1062 | WARN_ON(end < 0); /* We're not aware of other errors */ | |
1063 | return 0; | |
1064 | } | |
1065 | } | |
1066 | ||
1067 | /** | |
1068 | * Waits for a sequence number to be signaled, and cleans up the | |
1069 | * request and object lists appropriately for that event. | |
1070 | */ | |
1071 | int | |
1072 | i915_wait_seqno(struct intel_ring_buffer *ring, uint32_t seqno) | |
1073 | { | |
1074 | struct drm_device *dev = ring->dev; | |
1075 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1076 | bool interruptible = dev_priv->mm.interruptible; | |
1077 | int ret; | |
1078 | ||
1079 | BUG_ON(!mutex_is_locked(&dev->struct_mutex)); | |
1080 | BUG_ON(seqno == 0); | |
1081 | ||
1082 | ret = i915_gem_check_wedge(dev_priv, interruptible); | |
1083 | if (ret) | |
1084 | return ret; | |
1085 | ||
1086 | ret = i915_gem_check_olr(ring, seqno); | |
1087 | if (ret) | |
1088 | return ret; | |
1089 | ||
1090 | return __wait_seqno(ring, seqno, interruptible, NULL); | |
1091 | } | |
1092 | ||
1093 | /** | |
1094 | * Ensures that all rendering to the object has completed and the object is | |
1095 | * safe to unbind from the GTT or access from the CPU. | |
1096 | */ | |
1097 | static __must_check int | |
1098 | i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj, | |
1099 | bool readonly) | |
1100 | { | |
1101 | struct intel_ring_buffer *ring = obj->ring; | |
1102 | u32 seqno; | |
1103 | int ret; | |
1104 | ||
1105 | seqno = readonly ? obj->last_write_seqno : obj->last_read_seqno; | |
1106 | if (seqno == 0) | |
1107 | return 0; | |
1108 | ||
1109 | ret = i915_wait_seqno(ring, seqno); | |
1110 | if (ret) | |
1111 | return ret; | |
1112 | ||
1113 | i915_gem_retire_requests_ring(ring); | |
1114 | ||
1115 | /* Manually manage the write flush as we may have not yet | |
1116 | * retired the buffer. | |
1117 | */ | |
1118 | if (obj->last_write_seqno && | |
1119 | i915_seqno_passed(seqno, obj->last_write_seqno)) { | |
1120 | obj->last_write_seqno = 0; | |
1121 | obj->base.write_domain &= ~I915_GEM_GPU_DOMAINS; | |
1122 | } | |
1123 | ||
1124 | return 0; | |
1125 | } | |
1126 | ||
3236f57a CW |
1127 | /* A nonblocking variant of the above wait. This is a highly dangerous routine |
1128 | * as the object state may change during this call. | |
1129 | */ | |
1130 | static __must_check int | |
1131 | i915_gem_object_wait_rendering__nonblocking(struct drm_i915_gem_object *obj, | |
1132 | bool readonly) | |
1133 | { | |
1134 | struct drm_device *dev = obj->base.dev; | |
1135 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1136 | struct intel_ring_buffer *ring = obj->ring; | |
1137 | u32 seqno; | |
1138 | int ret; | |
1139 | ||
1140 | BUG_ON(!mutex_is_locked(&dev->struct_mutex)); | |
1141 | BUG_ON(!dev_priv->mm.interruptible); | |
1142 | ||
1143 | seqno = readonly ? obj->last_write_seqno : obj->last_read_seqno; | |
1144 | if (seqno == 0) | |
1145 | return 0; | |
1146 | ||
1147 | ret = i915_gem_check_wedge(dev_priv, true); | |
1148 | if (ret) | |
1149 | return ret; | |
1150 | ||
1151 | ret = i915_gem_check_olr(ring, seqno); | |
1152 | if (ret) | |
1153 | return ret; | |
1154 | ||
1155 | mutex_unlock(&dev->struct_mutex); | |
1156 | ret = __wait_seqno(ring, seqno, true, NULL); | |
1157 | mutex_lock(&dev->struct_mutex); | |
1158 | ||
1159 | i915_gem_retire_requests_ring(ring); | |
1160 | ||
1161 | /* Manually manage the write flush as we may have not yet | |
1162 | * retired the buffer. | |
1163 | */ | |
1164 | if (obj->last_write_seqno && | |
1165 | i915_seqno_passed(seqno, obj->last_write_seqno)) { | |
1166 | obj->last_write_seqno = 0; | |
1167 | obj->base.write_domain &= ~I915_GEM_GPU_DOMAINS; | |
1168 | } | |
1169 | ||
1170 | return ret; | |
1171 | } | |
1172 | ||
673a394b | 1173 | /** |
2ef7eeaa EA |
1174 | * Called when user space prepares to use an object with the CPU, either |
1175 | * through the mmap ioctl's mapping or a GTT mapping. | |
673a394b EA |
1176 | */ |
1177 | int | |
1178 | i915_gem_set_domain_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 1179 | struct drm_file *file) |
673a394b EA |
1180 | { |
1181 | struct drm_i915_gem_set_domain *args = data; | |
05394f39 | 1182 | struct drm_i915_gem_object *obj; |
2ef7eeaa EA |
1183 | uint32_t read_domains = args->read_domains; |
1184 | uint32_t write_domain = args->write_domain; | |
673a394b EA |
1185 | int ret; |
1186 | ||
2ef7eeaa | 1187 | /* Only handle setting domains to types used by the CPU. */ |
21d509e3 | 1188 | if (write_domain & I915_GEM_GPU_DOMAINS) |
2ef7eeaa EA |
1189 | return -EINVAL; |
1190 | ||
21d509e3 | 1191 | if (read_domains & I915_GEM_GPU_DOMAINS) |
2ef7eeaa EA |
1192 | return -EINVAL; |
1193 | ||
1194 | /* Having something in the write domain implies it's in the read | |
1195 | * domain, and only that read domain. Enforce that in the request. | |
1196 | */ | |
1197 | if (write_domain != 0 && read_domains != write_domain) | |
1198 | return -EINVAL; | |
1199 | ||
76c1dec1 | 1200 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 1201 | if (ret) |
76c1dec1 | 1202 | return ret; |
1d7cfea1 | 1203 | |
05394f39 | 1204 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 1205 | if (&obj->base == NULL) { |
1d7cfea1 CW |
1206 | ret = -ENOENT; |
1207 | goto unlock; | |
76c1dec1 | 1208 | } |
673a394b | 1209 | |
3236f57a CW |
1210 | /* Try to flush the object off the GPU without holding the lock. |
1211 | * We will repeat the flush holding the lock in the normal manner | |
1212 | * to catch cases where we are gazumped. | |
1213 | */ | |
1214 | ret = i915_gem_object_wait_rendering__nonblocking(obj, !write_domain); | |
1215 | if (ret) | |
1216 | goto unref; | |
1217 | ||
2ef7eeaa EA |
1218 | if (read_domains & I915_GEM_DOMAIN_GTT) { |
1219 | ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0); | |
02354392 EA |
1220 | |
1221 | /* Silently promote "you're not bound, there was nothing to do" | |
1222 | * to success, since the client was just asking us to | |
1223 | * make sure everything was done. | |
1224 | */ | |
1225 | if (ret == -EINVAL) | |
1226 | ret = 0; | |
2ef7eeaa | 1227 | } else { |
e47c68e9 | 1228 | ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0); |
2ef7eeaa EA |
1229 | } |
1230 | ||
3236f57a | 1231 | unref: |
05394f39 | 1232 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 1233 | unlock: |
673a394b EA |
1234 | mutex_unlock(&dev->struct_mutex); |
1235 | return ret; | |
1236 | } | |
1237 | ||
1238 | /** | |
1239 | * Called when user space has done writes to this buffer | |
1240 | */ | |
1241 | int | |
1242 | i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 1243 | struct drm_file *file) |
673a394b EA |
1244 | { |
1245 | struct drm_i915_gem_sw_finish *args = data; | |
05394f39 | 1246 | struct drm_i915_gem_object *obj; |
673a394b EA |
1247 | int ret = 0; |
1248 | ||
76c1dec1 | 1249 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 1250 | if (ret) |
76c1dec1 | 1251 | return ret; |
1d7cfea1 | 1252 | |
05394f39 | 1253 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 1254 | if (&obj->base == NULL) { |
1d7cfea1 CW |
1255 | ret = -ENOENT; |
1256 | goto unlock; | |
673a394b EA |
1257 | } |
1258 | ||
673a394b | 1259 | /* Pinned buffers may be scanout, so flush the cache */ |
05394f39 | 1260 | if (obj->pin_count) |
e47c68e9 EA |
1261 | i915_gem_object_flush_cpu_write_domain(obj); |
1262 | ||
05394f39 | 1263 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 1264 | unlock: |
673a394b EA |
1265 | mutex_unlock(&dev->struct_mutex); |
1266 | return ret; | |
1267 | } | |
1268 | ||
1269 | /** | |
1270 | * Maps the contents of an object, returning the address it is mapped | |
1271 | * into. | |
1272 | * | |
1273 | * While the mapping holds a reference on the contents of the object, it doesn't | |
1274 | * imply a ref on the object itself. | |
1275 | */ | |
1276 | int | |
1277 | i915_gem_mmap_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 1278 | struct drm_file *file) |
673a394b EA |
1279 | { |
1280 | struct drm_i915_gem_mmap *args = data; | |
1281 | struct drm_gem_object *obj; | |
673a394b EA |
1282 | unsigned long addr; |
1283 | ||
05394f39 | 1284 | obj = drm_gem_object_lookup(dev, file, args->handle); |
673a394b | 1285 | if (obj == NULL) |
bf79cb91 | 1286 | return -ENOENT; |
673a394b | 1287 | |
1286ff73 DV |
1288 | /* prime objects have no backing filp to GEM mmap |
1289 | * pages from. | |
1290 | */ | |
1291 | if (!obj->filp) { | |
1292 | drm_gem_object_unreference_unlocked(obj); | |
1293 | return -EINVAL; | |
1294 | } | |
1295 | ||
6be5ceb0 | 1296 | addr = vm_mmap(obj->filp, 0, args->size, |
673a394b EA |
1297 | PROT_READ | PROT_WRITE, MAP_SHARED, |
1298 | args->offset); | |
bc9025bd | 1299 | drm_gem_object_unreference_unlocked(obj); |
673a394b EA |
1300 | if (IS_ERR((void *)addr)) |
1301 | return addr; | |
1302 | ||
1303 | args->addr_ptr = (uint64_t) addr; | |
1304 | ||
1305 | return 0; | |
1306 | } | |
1307 | ||
de151cf6 JB |
1308 | /** |
1309 | * i915_gem_fault - fault a page into the GTT | |
1310 | * vma: VMA in question | |
1311 | * vmf: fault info | |
1312 | * | |
1313 | * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped | |
1314 | * from userspace. The fault handler takes care of binding the object to | |
1315 | * the GTT (if needed), allocating and programming a fence register (again, | |
1316 | * only if needed based on whether the old reg is still valid or the object | |
1317 | * is tiled) and inserting a new PTE into the faulting process. | |
1318 | * | |
1319 | * Note that the faulting process may involve evicting existing objects | |
1320 | * from the GTT and/or fence registers to make room. So performance may | |
1321 | * suffer if the GTT working set is large or there are few fence registers | |
1322 | * left. | |
1323 | */ | |
1324 | int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf) | |
1325 | { | |
05394f39 CW |
1326 | struct drm_i915_gem_object *obj = to_intel_bo(vma->vm_private_data); |
1327 | struct drm_device *dev = obj->base.dev; | |
7d1c4804 | 1328 | drm_i915_private_t *dev_priv = dev->dev_private; |
de151cf6 JB |
1329 | pgoff_t page_offset; |
1330 | unsigned long pfn; | |
1331 | int ret = 0; | |
0f973f27 | 1332 | bool write = !!(vmf->flags & FAULT_FLAG_WRITE); |
de151cf6 JB |
1333 | |
1334 | /* We don't use vmf->pgoff since that has the fake offset */ | |
1335 | page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >> | |
1336 | PAGE_SHIFT; | |
1337 | ||
d9bc7e9f CW |
1338 | ret = i915_mutex_lock_interruptible(dev); |
1339 | if (ret) | |
1340 | goto out; | |
a00b10c3 | 1341 | |
db53a302 CW |
1342 | trace_i915_gem_object_fault(obj, page_offset, true, write); |
1343 | ||
d9bc7e9f | 1344 | /* Now bind it into the GTT if needed */ |
c9839303 CW |
1345 | ret = i915_gem_object_pin(obj, 0, true, false); |
1346 | if (ret) | |
1347 | goto unlock; | |
4a684a41 | 1348 | |
c9839303 CW |
1349 | ret = i915_gem_object_set_to_gtt_domain(obj, write); |
1350 | if (ret) | |
1351 | goto unpin; | |
74898d7e | 1352 | |
06d98131 | 1353 | ret = i915_gem_object_get_fence(obj); |
d9e86c0e | 1354 | if (ret) |
c9839303 | 1355 | goto unpin; |
7d1c4804 | 1356 | |
6299f992 CW |
1357 | obj->fault_mappable = true; |
1358 | ||
dd2757f8 | 1359 | pfn = ((dev_priv->mm.gtt_base_addr + obj->gtt_offset) >> PAGE_SHIFT) + |
de151cf6 JB |
1360 | page_offset; |
1361 | ||
1362 | /* Finally, remap it using the new GTT offset */ | |
1363 | ret = vm_insert_pfn(vma, (unsigned long)vmf->virtual_address, pfn); | |
c9839303 CW |
1364 | unpin: |
1365 | i915_gem_object_unpin(obj); | |
c715089f | 1366 | unlock: |
de151cf6 | 1367 | mutex_unlock(&dev->struct_mutex); |
d9bc7e9f | 1368 | out: |
de151cf6 | 1369 | switch (ret) { |
d9bc7e9f | 1370 | case -EIO: |
a9340cca DV |
1371 | /* If this -EIO is due to a gpu hang, give the reset code a |
1372 | * chance to clean up the mess. Otherwise return the proper | |
1373 | * SIGBUS. */ | |
1374 | if (!atomic_read(&dev_priv->mm.wedged)) | |
1375 | return VM_FAULT_SIGBUS; | |
045e769a | 1376 | case -EAGAIN: |
d9bc7e9f CW |
1377 | /* Give the error handler a chance to run and move the |
1378 | * objects off the GPU active list. Next time we service the | |
1379 | * fault, we should be able to transition the page into the | |
1380 | * GTT without touching the GPU (and so avoid further | |
1381 | * EIO/EGAIN). If the GPU is wedged, then there is no issue | |
1382 | * with coherency, just lost writes. | |
1383 | */ | |
045e769a | 1384 | set_need_resched(); |
c715089f CW |
1385 | case 0: |
1386 | case -ERESTARTSYS: | |
bed636ab | 1387 | case -EINTR: |
e79e0fe3 DR |
1388 | case -EBUSY: |
1389 | /* | |
1390 | * EBUSY is ok: this just means that another thread | |
1391 | * already did the job. | |
1392 | */ | |
c715089f | 1393 | return VM_FAULT_NOPAGE; |
de151cf6 | 1394 | case -ENOMEM: |
de151cf6 | 1395 | return VM_FAULT_OOM; |
a7c2e1aa DV |
1396 | case -ENOSPC: |
1397 | return VM_FAULT_SIGBUS; | |
de151cf6 | 1398 | default: |
a7c2e1aa | 1399 | WARN_ONCE(ret, "unhandled error in i915_gem_fault: %i\n", ret); |
c715089f | 1400 | return VM_FAULT_SIGBUS; |
de151cf6 JB |
1401 | } |
1402 | } | |
1403 | ||
901782b2 CW |
1404 | /** |
1405 | * i915_gem_release_mmap - remove physical page mappings | |
1406 | * @obj: obj in question | |
1407 | * | |
af901ca1 | 1408 | * Preserve the reservation of the mmapping with the DRM core code, but |
901782b2 CW |
1409 | * relinquish ownership of the pages back to the system. |
1410 | * | |
1411 | * It is vital that we remove the page mapping if we have mapped a tiled | |
1412 | * object through the GTT and then lose the fence register due to | |
1413 | * resource pressure. Similarly if the object has been moved out of the | |
1414 | * aperture, than pages mapped into userspace must be revoked. Removing the | |
1415 | * mapping will then trigger a page fault on the next user access, allowing | |
1416 | * fixup by i915_gem_fault(). | |
1417 | */ | |
d05ca301 | 1418 | void |
05394f39 | 1419 | i915_gem_release_mmap(struct drm_i915_gem_object *obj) |
901782b2 | 1420 | { |
6299f992 CW |
1421 | if (!obj->fault_mappable) |
1422 | return; | |
901782b2 | 1423 | |
f6e47884 CW |
1424 | if (obj->base.dev->dev_mapping) |
1425 | unmap_mapping_range(obj->base.dev->dev_mapping, | |
1426 | (loff_t)obj->base.map_list.hash.key<<PAGE_SHIFT, | |
1427 | obj->base.size, 1); | |
fb7d516a | 1428 | |
6299f992 | 1429 | obj->fault_mappable = false; |
901782b2 CW |
1430 | } |
1431 | ||
92b88aeb | 1432 | static uint32_t |
e28f8711 | 1433 | i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode) |
92b88aeb | 1434 | { |
e28f8711 | 1435 | uint32_t gtt_size; |
92b88aeb CW |
1436 | |
1437 | if (INTEL_INFO(dev)->gen >= 4 || | |
e28f8711 CW |
1438 | tiling_mode == I915_TILING_NONE) |
1439 | return size; | |
92b88aeb CW |
1440 | |
1441 | /* Previous chips need a power-of-two fence region when tiling */ | |
1442 | if (INTEL_INFO(dev)->gen == 3) | |
e28f8711 | 1443 | gtt_size = 1024*1024; |
92b88aeb | 1444 | else |
e28f8711 | 1445 | gtt_size = 512*1024; |
92b88aeb | 1446 | |
e28f8711 CW |
1447 | while (gtt_size < size) |
1448 | gtt_size <<= 1; | |
92b88aeb | 1449 | |
e28f8711 | 1450 | return gtt_size; |
92b88aeb CW |
1451 | } |
1452 | ||
de151cf6 JB |
1453 | /** |
1454 | * i915_gem_get_gtt_alignment - return required GTT alignment for an object | |
1455 | * @obj: object to check | |
1456 | * | |
1457 | * Return the required GTT alignment for an object, taking into account | |
5e783301 | 1458 | * potential fence register mapping. |
de151cf6 JB |
1459 | */ |
1460 | static uint32_t | |
e28f8711 CW |
1461 | i915_gem_get_gtt_alignment(struct drm_device *dev, |
1462 | uint32_t size, | |
1463 | int tiling_mode) | |
de151cf6 | 1464 | { |
de151cf6 JB |
1465 | /* |
1466 | * Minimum alignment is 4k (GTT page size), but might be greater | |
1467 | * if a fence register is needed for the object. | |
1468 | */ | |
a00b10c3 | 1469 | if (INTEL_INFO(dev)->gen >= 4 || |
e28f8711 | 1470 | tiling_mode == I915_TILING_NONE) |
de151cf6 JB |
1471 | return 4096; |
1472 | ||
a00b10c3 CW |
1473 | /* |
1474 | * Previous chips need to be aligned to the size of the smallest | |
1475 | * fence register that can contain the object. | |
1476 | */ | |
e28f8711 | 1477 | return i915_gem_get_gtt_size(dev, size, tiling_mode); |
a00b10c3 CW |
1478 | } |
1479 | ||
5e783301 DV |
1480 | /** |
1481 | * i915_gem_get_unfenced_gtt_alignment - return required GTT alignment for an | |
1482 | * unfenced object | |
e28f8711 CW |
1483 | * @dev: the device |
1484 | * @size: size of the object | |
1485 | * @tiling_mode: tiling mode of the object | |
5e783301 DV |
1486 | * |
1487 | * Return the required GTT alignment for an object, only taking into account | |
1488 | * unfenced tiled surface requirements. | |
1489 | */ | |
467cffba | 1490 | uint32_t |
e28f8711 CW |
1491 | i915_gem_get_unfenced_gtt_alignment(struct drm_device *dev, |
1492 | uint32_t size, | |
1493 | int tiling_mode) | |
5e783301 | 1494 | { |
5e783301 DV |
1495 | /* |
1496 | * Minimum alignment is 4k (GTT page size) for sane hw. | |
1497 | */ | |
1498 | if (INTEL_INFO(dev)->gen >= 4 || IS_G33(dev) || | |
e28f8711 | 1499 | tiling_mode == I915_TILING_NONE) |
5e783301 DV |
1500 | return 4096; |
1501 | ||
e28f8711 CW |
1502 | /* Previous hardware however needs to be aligned to a power-of-two |
1503 | * tile height. The simplest method for determining this is to reuse | |
1504 | * the power-of-tile object size. | |
5e783301 | 1505 | */ |
e28f8711 | 1506 | return i915_gem_get_gtt_size(dev, size, tiling_mode); |
5e783301 DV |
1507 | } |
1508 | ||
d8cb5086 CW |
1509 | static int i915_gem_object_create_mmap_offset(struct drm_i915_gem_object *obj) |
1510 | { | |
1511 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; | |
1512 | int ret; | |
1513 | ||
1514 | if (obj->base.map_list.map) | |
1515 | return 0; | |
1516 | ||
1517 | ret = drm_gem_create_mmap_offset(&obj->base); | |
1518 | if (ret != -ENOSPC) | |
1519 | return ret; | |
1520 | ||
1521 | /* Badly fragmented mmap space? The only way we can recover | |
1522 | * space is by destroying unwanted objects. We can't randomly release | |
1523 | * mmap_offsets as userspace expects them to be persistent for the | |
1524 | * lifetime of the objects. The closest we can is to release the | |
1525 | * offsets on purgeable objects by truncating it and marking it purged, | |
1526 | * which prevents userspace from ever using that object again. | |
1527 | */ | |
1528 | i915_gem_purge(dev_priv, obj->base.size >> PAGE_SHIFT); | |
1529 | ret = drm_gem_create_mmap_offset(&obj->base); | |
1530 | if (ret != -ENOSPC) | |
1531 | return ret; | |
1532 | ||
1533 | i915_gem_shrink_all(dev_priv); | |
1534 | return drm_gem_create_mmap_offset(&obj->base); | |
1535 | } | |
1536 | ||
1537 | static void i915_gem_object_free_mmap_offset(struct drm_i915_gem_object *obj) | |
1538 | { | |
1539 | if (!obj->base.map_list.map) | |
1540 | return; | |
1541 | ||
1542 | drm_gem_free_mmap_offset(&obj->base); | |
1543 | } | |
1544 | ||
de151cf6 | 1545 | int |
ff72145b DA |
1546 | i915_gem_mmap_gtt(struct drm_file *file, |
1547 | struct drm_device *dev, | |
1548 | uint32_t handle, | |
1549 | uint64_t *offset) | |
de151cf6 | 1550 | { |
da761a6e | 1551 | struct drm_i915_private *dev_priv = dev->dev_private; |
05394f39 | 1552 | struct drm_i915_gem_object *obj; |
de151cf6 JB |
1553 | int ret; |
1554 | ||
76c1dec1 | 1555 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 1556 | if (ret) |
76c1dec1 | 1557 | return ret; |
de151cf6 | 1558 | |
ff72145b | 1559 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle)); |
c8725226 | 1560 | if (&obj->base == NULL) { |
1d7cfea1 CW |
1561 | ret = -ENOENT; |
1562 | goto unlock; | |
1563 | } | |
de151cf6 | 1564 | |
05394f39 | 1565 | if (obj->base.size > dev_priv->mm.gtt_mappable_end) { |
da761a6e | 1566 | ret = -E2BIG; |
ff56b0bc | 1567 | goto out; |
da761a6e CW |
1568 | } |
1569 | ||
05394f39 | 1570 | if (obj->madv != I915_MADV_WILLNEED) { |
ab18282d | 1571 | DRM_ERROR("Attempting to mmap a purgeable buffer\n"); |
1d7cfea1 CW |
1572 | ret = -EINVAL; |
1573 | goto out; | |
ab18282d CW |
1574 | } |
1575 | ||
d8cb5086 CW |
1576 | ret = i915_gem_object_create_mmap_offset(obj); |
1577 | if (ret) | |
1578 | goto out; | |
de151cf6 | 1579 | |
ff72145b | 1580 | *offset = (u64)obj->base.map_list.hash.key << PAGE_SHIFT; |
de151cf6 | 1581 | |
1d7cfea1 | 1582 | out: |
05394f39 | 1583 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 1584 | unlock: |
de151cf6 | 1585 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 1586 | return ret; |
de151cf6 JB |
1587 | } |
1588 | ||
ff72145b DA |
1589 | /** |
1590 | * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing | |
1591 | * @dev: DRM device | |
1592 | * @data: GTT mapping ioctl data | |
1593 | * @file: GEM object info | |
1594 | * | |
1595 | * Simply returns the fake offset to userspace so it can mmap it. | |
1596 | * The mmap call will end up in drm_gem_mmap(), which will set things | |
1597 | * up so we can get faults in the handler above. | |
1598 | * | |
1599 | * The fault handler will take care of binding the object into the GTT | |
1600 | * (since it may have been evicted to make room for something), allocating | |
1601 | * a fence register, and mapping the appropriate aperture address into | |
1602 | * userspace. | |
1603 | */ | |
1604 | int | |
1605 | i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data, | |
1606 | struct drm_file *file) | |
1607 | { | |
1608 | struct drm_i915_gem_mmap_gtt *args = data; | |
1609 | ||
ff72145b DA |
1610 | return i915_gem_mmap_gtt(file, dev, args->handle, &args->offset); |
1611 | } | |
1612 | ||
225067ee DV |
1613 | /* Immediately discard the backing storage */ |
1614 | static void | |
1615 | i915_gem_object_truncate(struct drm_i915_gem_object *obj) | |
e5281ccd | 1616 | { |
e5281ccd | 1617 | struct inode *inode; |
e5281ccd | 1618 | |
4d6294bf | 1619 | i915_gem_object_free_mmap_offset(obj); |
1286ff73 | 1620 | |
4d6294bf CW |
1621 | if (obj->base.filp == NULL) |
1622 | return; | |
e5281ccd | 1623 | |
225067ee DV |
1624 | /* Our goal here is to return as much of the memory as |
1625 | * is possible back to the system as we are called from OOM. | |
1626 | * To do this we must instruct the shmfs to drop all of its | |
1627 | * backing pages, *now*. | |
1628 | */ | |
05394f39 | 1629 | inode = obj->base.filp->f_path.dentry->d_inode; |
225067ee | 1630 | shmem_truncate_range(inode, 0, (loff_t)-1); |
e5281ccd | 1631 | |
225067ee DV |
1632 | obj->madv = __I915_MADV_PURGED; |
1633 | } | |
e5281ccd | 1634 | |
225067ee DV |
1635 | static inline int |
1636 | i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj) | |
1637 | { | |
1638 | return obj->madv == I915_MADV_DONTNEED; | |
e5281ccd CW |
1639 | } |
1640 | ||
5cdf5881 | 1641 | static void |
05394f39 | 1642 | i915_gem_object_put_pages_gtt(struct drm_i915_gem_object *obj) |
673a394b | 1643 | { |
05394f39 | 1644 | int page_count = obj->base.size / PAGE_SIZE; |
9da3da66 | 1645 | struct scatterlist *sg; |
6c085a72 | 1646 | int ret, i; |
1286ff73 | 1647 | |
05394f39 | 1648 | BUG_ON(obj->madv == __I915_MADV_PURGED); |
673a394b | 1649 | |
6c085a72 CW |
1650 | ret = i915_gem_object_set_to_cpu_domain(obj, true); |
1651 | if (ret) { | |
1652 | /* In the event of a disaster, abandon all caches and | |
1653 | * hope for the best. | |
1654 | */ | |
1655 | WARN_ON(ret != -EIO); | |
1656 | i915_gem_clflush_object(obj); | |
1657 | obj->base.read_domains = obj->base.write_domain = I915_GEM_DOMAIN_CPU; | |
1658 | } | |
1659 | ||
6dacfd2f | 1660 | if (i915_gem_object_needs_bit17_swizzle(obj)) |
280b713b EA |
1661 | i915_gem_object_save_bit_17_swizzle(obj); |
1662 | ||
05394f39 CW |
1663 | if (obj->madv == I915_MADV_DONTNEED) |
1664 | obj->dirty = 0; | |
3ef94daa | 1665 | |
9da3da66 CW |
1666 | for_each_sg(obj->pages->sgl, sg, page_count, i) { |
1667 | struct page *page = sg_page(sg); | |
1668 | ||
05394f39 | 1669 | if (obj->dirty) |
9da3da66 | 1670 | set_page_dirty(page); |
3ef94daa | 1671 | |
05394f39 | 1672 | if (obj->madv == I915_MADV_WILLNEED) |
9da3da66 | 1673 | mark_page_accessed(page); |
3ef94daa | 1674 | |
9da3da66 | 1675 | page_cache_release(page); |
3ef94daa | 1676 | } |
05394f39 | 1677 | obj->dirty = 0; |
673a394b | 1678 | |
9da3da66 CW |
1679 | sg_free_table(obj->pages); |
1680 | kfree(obj->pages); | |
37e680a1 | 1681 | } |
6c085a72 | 1682 | |
37e680a1 CW |
1683 | static int |
1684 | i915_gem_object_put_pages(struct drm_i915_gem_object *obj) | |
1685 | { | |
1686 | const struct drm_i915_gem_object_ops *ops = obj->ops; | |
1687 | ||
2f745ad3 | 1688 | if (obj->pages == NULL) |
37e680a1 CW |
1689 | return 0; |
1690 | ||
1691 | BUG_ON(obj->gtt_space); | |
6c085a72 | 1692 | |
a5570178 CW |
1693 | if (obj->pages_pin_count) |
1694 | return -EBUSY; | |
1695 | ||
37e680a1 | 1696 | ops->put_pages(obj); |
05394f39 | 1697 | obj->pages = NULL; |
37e680a1 CW |
1698 | |
1699 | list_del(&obj->gtt_list); | |
6c085a72 CW |
1700 | if (i915_gem_object_is_purgeable(obj)) |
1701 | i915_gem_object_truncate(obj); | |
1702 | ||
1703 | return 0; | |
1704 | } | |
1705 | ||
1706 | static long | |
1707 | i915_gem_purge(struct drm_i915_private *dev_priv, long target) | |
1708 | { | |
1709 | struct drm_i915_gem_object *obj, *next; | |
1710 | long count = 0; | |
1711 | ||
1712 | list_for_each_entry_safe(obj, next, | |
1713 | &dev_priv->mm.unbound_list, | |
1714 | gtt_list) { | |
1715 | if (i915_gem_object_is_purgeable(obj) && | |
37e680a1 | 1716 | i915_gem_object_put_pages(obj) == 0) { |
6c085a72 CW |
1717 | count += obj->base.size >> PAGE_SHIFT; |
1718 | if (count >= target) | |
1719 | return count; | |
1720 | } | |
1721 | } | |
1722 | ||
1723 | list_for_each_entry_safe(obj, next, | |
1724 | &dev_priv->mm.inactive_list, | |
1725 | mm_list) { | |
1726 | if (i915_gem_object_is_purgeable(obj) && | |
1727 | i915_gem_object_unbind(obj) == 0 && | |
37e680a1 | 1728 | i915_gem_object_put_pages(obj) == 0) { |
6c085a72 CW |
1729 | count += obj->base.size >> PAGE_SHIFT; |
1730 | if (count >= target) | |
1731 | return count; | |
1732 | } | |
1733 | } | |
1734 | ||
1735 | return count; | |
1736 | } | |
1737 | ||
1738 | static void | |
1739 | i915_gem_shrink_all(struct drm_i915_private *dev_priv) | |
1740 | { | |
1741 | struct drm_i915_gem_object *obj, *next; | |
1742 | ||
1743 | i915_gem_evict_everything(dev_priv->dev); | |
1744 | ||
1745 | list_for_each_entry_safe(obj, next, &dev_priv->mm.unbound_list, gtt_list) | |
37e680a1 | 1746 | i915_gem_object_put_pages(obj); |
225067ee DV |
1747 | } |
1748 | ||
37e680a1 | 1749 | static int |
6c085a72 | 1750 | i915_gem_object_get_pages_gtt(struct drm_i915_gem_object *obj) |
e5281ccd | 1751 | { |
6c085a72 | 1752 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
e5281ccd CW |
1753 | int page_count, i; |
1754 | struct address_space *mapping; | |
9da3da66 CW |
1755 | struct sg_table *st; |
1756 | struct scatterlist *sg; | |
e5281ccd | 1757 | struct page *page; |
6c085a72 | 1758 | gfp_t gfp; |
e5281ccd | 1759 | |
6c085a72 CW |
1760 | /* Assert that the object is not currently in any GPU domain. As it |
1761 | * wasn't in the GTT, there shouldn't be any way it could have been in | |
1762 | * a GPU cache | |
1763 | */ | |
1764 | BUG_ON(obj->base.read_domains & I915_GEM_GPU_DOMAINS); | |
1765 | BUG_ON(obj->base.write_domain & I915_GEM_GPU_DOMAINS); | |
1766 | ||
9da3da66 CW |
1767 | st = kmalloc(sizeof(*st), GFP_KERNEL); |
1768 | if (st == NULL) | |
1769 | return -ENOMEM; | |
1770 | ||
05394f39 | 1771 | page_count = obj->base.size / PAGE_SIZE; |
9da3da66 CW |
1772 | if (sg_alloc_table(st, page_count, GFP_KERNEL)) { |
1773 | sg_free_table(st); | |
1774 | kfree(st); | |
e5281ccd | 1775 | return -ENOMEM; |
9da3da66 | 1776 | } |
e5281ccd | 1777 | |
9da3da66 CW |
1778 | /* Get the list of pages out of our struct file. They'll be pinned |
1779 | * at this point until we release them. | |
1780 | * | |
1781 | * Fail silently without starting the shrinker | |
1782 | */ | |
6c085a72 CW |
1783 | mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping; |
1784 | gfp = mapping_gfp_mask(mapping); | |
d7c3b937 | 1785 | gfp |= __GFP_NORETRY | __GFP_NOWARN; |
6c085a72 | 1786 | gfp &= ~(__GFP_IO | __GFP_WAIT); |
9da3da66 | 1787 | for_each_sg(st->sgl, sg, page_count, i) { |
6c085a72 CW |
1788 | page = shmem_read_mapping_page_gfp(mapping, i, gfp); |
1789 | if (IS_ERR(page)) { | |
1790 | i915_gem_purge(dev_priv, page_count); | |
1791 | page = shmem_read_mapping_page_gfp(mapping, i, gfp); | |
1792 | } | |
1793 | if (IS_ERR(page)) { | |
1794 | /* We've tried hard to allocate the memory by reaping | |
1795 | * our own buffer, now let the real VM do its job and | |
1796 | * go down in flames if truly OOM. | |
1797 | */ | |
d7c3b937 | 1798 | gfp &= ~(__GFP_NORETRY | __GFP_NOWARN); |
6c085a72 CW |
1799 | gfp |= __GFP_IO | __GFP_WAIT; |
1800 | ||
1801 | i915_gem_shrink_all(dev_priv); | |
1802 | page = shmem_read_mapping_page_gfp(mapping, i, gfp); | |
1803 | if (IS_ERR(page)) | |
1804 | goto err_pages; | |
1805 | ||
d7c3b937 | 1806 | gfp |= __GFP_NORETRY | __GFP_NOWARN; |
6c085a72 CW |
1807 | gfp &= ~(__GFP_IO | __GFP_WAIT); |
1808 | } | |
e5281ccd | 1809 | |
9da3da66 | 1810 | sg_set_page(sg, page, PAGE_SIZE, 0); |
e5281ccd CW |
1811 | } |
1812 | ||
74ce6b6c CW |
1813 | obj->pages = st; |
1814 | ||
6dacfd2f | 1815 | if (i915_gem_object_needs_bit17_swizzle(obj)) |
e5281ccd CW |
1816 | i915_gem_object_do_bit_17_swizzle(obj); |
1817 | ||
1818 | return 0; | |
1819 | ||
1820 | err_pages: | |
9da3da66 CW |
1821 | for_each_sg(st->sgl, sg, i, page_count) |
1822 | page_cache_release(sg_page(sg)); | |
1823 | sg_free_table(st); | |
1824 | kfree(st); | |
e5281ccd | 1825 | return PTR_ERR(page); |
673a394b EA |
1826 | } |
1827 | ||
37e680a1 CW |
1828 | /* Ensure that the associated pages are gathered from the backing storage |
1829 | * and pinned into our object. i915_gem_object_get_pages() may be called | |
1830 | * multiple times before they are released by a single call to | |
1831 | * i915_gem_object_put_pages() - once the pages are no longer referenced | |
1832 | * either as a result of memory pressure (reaping pages under the shrinker) | |
1833 | * or as the object is itself released. | |
1834 | */ | |
1835 | int | |
1836 | i915_gem_object_get_pages(struct drm_i915_gem_object *obj) | |
1837 | { | |
1838 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; | |
1839 | const struct drm_i915_gem_object_ops *ops = obj->ops; | |
1840 | int ret; | |
1841 | ||
2f745ad3 | 1842 | if (obj->pages) |
37e680a1 CW |
1843 | return 0; |
1844 | ||
a5570178 CW |
1845 | BUG_ON(obj->pages_pin_count); |
1846 | ||
37e680a1 CW |
1847 | ret = ops->get_pages(obj); |
1848 | if (ret) | |
1849 | return ret; | |
1850 | ||
1851 | list_add_tail(&obj->gtt_list, &dev_priv->mm.unbound_list); | |
1852 | return 0; | |
673a394b EA |
1853 | } |
1854 | ||
54cf91dc | 1855 | void |
05394f39 | 1856 | i915_gem_object_move_to_active(struct drm_i915_gem_object *obj, |
9d773091 | 1857 | struct intel_ring_buffer *ring) |
673a394b | 1858 | { |
05394f39 | 1859 | struct drm_device *dev = obj->base.dev; |
69dc4987 | 1860 | struct drm_i915_private *dev_priv = dev->dev_private; |
9d773091 | 1861 | u32 seqno = intel_ring_get_seqno(ring); |
617dbe27 | 1862 | |
852835f3 | 1863 | BUG_ON(ring == NULL); |
05394f39 | 1864 | obj->ring = ring; |
673a394b EA |
1865 | |
1866 | /* Add a reference if we're newly entering the active list. */ | |
05394f39 CW |
1867 | if (!obj->active) { |
1868 | drm_gem_object_reference(&obj->base); | |
1869 | obj->active = 1; | |
673a394b | 1870 | } |
e35a41de | 1871 | |
673a394b | 1872 | /* Move from whatever list we were on to the tail of execution. */ |
05394f39 CW |
1873 | list_move_tail(&obj->mm_list, &dev_priv->mm.active_list); |
1874 | list_move_tail(&obj->ring_list, &ring->active_list); | |
caea7476 | 1875 | |
0201f1ec | 1876 | obj->last_read_seqno = seqno; |
caea7476 | 1877 | |
7dd49065 | 1878 | if (obj->fenced_gpu_access) { |
caea7476 | 1879 | obj->last_fenced_seqno = seqno; |
caea7476 | 1880 | |
7dd49065 CW |
1881 | /* Bump MRU to take account of the delayed flush */ |
1882 | if (obj->fence_reg != I915_FENCE_REG_NONE) { | |
1883 | struct drm_i915_fence_reg *reg; | |
1884 | ||
1885 | reg = &dev_priv->fence_regs[obj->fence_reg]; | |
1886 | list_move_tail(®->lru_list, | |
1887 | &dev_priv->mm.fence_list); | |
1888 | } | |
caea7476 CW |
1889 | } |
1890 | } | |
1891 | ||
1892 | static void | |
caea7476 | 1893 | i915_gem_object_move_to_inactive(struct drm_i915_gem_object *obj) |
ce44b0ea | 1894 | { |
05394f39 | 1895 | struct drm_device *dev = obj->base.dev; |
caea7476 | 1896 | struct drm_i915_private *dev_priv = dev->dev_private; |
ce44b0ea | 1897 | |
65ce3027 | 1898 | BUG_ON(obj->base.write_domain & ~I915_GEM_GPU_DOMAINS); |
05394f39 | 1899 | BUG_ON(!obj->active); |
caea7476 | 1900 | |
f047e395 CW |
1901 | if (obj->pin_count) /* are we a framebuffer? */ |
1902 | intel_mark_fb_idle(obj); | |
caea7476 | 1903 | |
1b50247a | 1904 | list_move_tail(&obj->mm_list, &dev_priv->mm.inactive_list); |
caea7476 | 1905 | |
65ce3027 | 1906 | list_del_init(&obj->ring_list); |
caea7476 CW |
1907 | obj->ring = NULL; |
1908 | ||
65ce3027 CW |
1909 | obj->last_read_seqno = 0; |
1910 | obj->last_write_seqno = 0; | |
1911 | obj->base.write_domain = 0; | |
1912 | ||
1913 | obj->last_fenced_seqno = 0; | |
caea7476 | 1914 | obj->fenced_gpu_access = false; |
caea7476 CW |
1915 | |
1916 | obj->active = 0; | |
1917 | drm_gem_object_unreference(&obj->base); | |
1918 | ||
1919 | WARN_ON(i915_verify_lists(dev)); | |
ce44b0ea | 1920 | } |
673a394b | 1921 | |
9d773091 CW |
1922 | static int |
1923 | i915_gem_handle_seqno_wrap(struct drm_device *dev) | |
53d227f2 | 1924 | { |
9d773091 CW |
1925 | struct drm_i915_private *dev_priv = dev->dev_private; |
1926 | struct intel_ring_buffer *ring; | |
1927 | int ret, i, j; | |
53d227f2 | 1928 | |
9d773091 CW |
1929 | /* The hardware uses various monotonic 32-bit counters, if we |
1930 | * detect that they will wraparound we need to idle the GPU | |
1931 | * and reset those counters. | |
1932 | */ | |
1933 | ret = 0; | |
1934 | for_each_ring(ring, dev_priv, i) { | |
1935 | for (j = 0; j < ARRAY_SIZE(ring->sync_seqno); j++) | |
1936 | ret |= ring->sync_seqno[j] != 0; | |
1937 | } | |
1938 | if (ret == 0) | |
1939 | return ret; | |
1940 | ||
1941 | ret = i915_gpu_idle(dev); | |
1942 | if (ret) | |
1943 | return ret; | |
1944 | ||
1945 | i915_gem_retire_requests(dev); | |
1946 | for_each_ring(ring, dev_priv, i) { | |
498d2ac1 MK |
1947 | ret = intel_ring_handle_seqno_wrap(ring); |
1948 | if (ret) | |
1949 | return ret; | |
1950 | ||
9d773091 CW |
1951 | for (j = 0; j < ARRAY_SIZE(ring->sync_seqno); j++) |
1952 | ring->sync_seqno[j] = 0; | |
1953 | } | |
53d227f2 | 1954 | |
9d773091 | 1955 | return 0; |
53d227f2 DV |
1956 | } |
1957 | ||
9d773091 CW |
1958 | int |
1959 | i915_gem_get_seqno(struct drm_device *dev, u32 *seqno) | |
53d227f2 | 1960 | { |
9d773091 CW |
1961 | struct drm_i915_private *dev_priv = dev->dev_private; |
1962 | ||
1963 | /* reserve 0 for non-seqno */ | |
1964 | if (dev_priv->next_seqno == 0) { | |
1965 | int ret = i915_gem_handle_seqno_wrap(dev); | |
1966 | if (ret) | |
1967 | return ret; | |
1968 | ||
1969 | dev_priv->next_seqno = 1; | |
1970 | } | |
53d227f2 | 1971 | |
f72b3435 | 1972 | *seqno = dev_priv->last_seqno = dev_priv->next_seqno++; |
9d773091 | 1973 | return 0; |
53d227f2 DV |
1974 | } |
1975 | ||
3cce469c | 1976 | int |
db53a302 | 1977 | i915_add_request(struct intel_ring_buffer *ring, |
f787a5f5 | 1978 | struct drm_file *file, |
acb868d3 | 1979 | u32 *out_seqno) |
673a394b | 1980 | { |
db53a302 | 1981 | drm_i915_private_t *dev_priv = ring->dev->dev_private; |
acb868d3 | 1982 | struct drm_i915_gem_request *request; |
a71d8d94 | 1983 | u32 request_ring_position; |
673a394b | 1984 | int was_empty; |
3cce469c CW |
1985 | int ret; |
1986 | ||
cc889e0f DV |
1987 | /* |
1988 | * Emit any outstanding flushes - execbuf can fail to emit the flush | |
1989 | * after having emitted the batchbuffer command. Hence we need to fix | |
1990 | * things up similar to emitting the lazy request. The difference here | |
1991 | * is that the flush _must_ happen before the next request, no matter | |
1992 | * what. | |
1993 | */ | |
a7b9761d CW |
1994 | ret = intel_ring_flush_all_caches(ring); |
1995 | if (ret) | |
1996 | return ret; | |
cc889e0f | 1997 | |
acb868d3 CW |
1998 | request = kmalloc(sizeof(*request), GFP_KERNEL); |
1999 | if (request == NULL) | |
2000 | return -ENOMEM; | |
cc889e0f | 2001 | |
673a394b | 2002 | |
a71d8d94 CW |
2003 | /* Record the position of the start of the request so that |
2004 | * should we detect the updated seqno part-way through the | |
2005 | * GPU processing the request, we never over-estimate the | |
2006 | * position of the head. | |
2007 | */ | |
2008 | request_ring_position = intel_ring_get_tail(ring); | |
2009 | ||
9d773091 | 2010 | ret = ring->add_request(ring); |
3bb73aba CW |
2011 | if (ret) { |
2012 | kfree(request); | |
2013 | return ret; | |
2014 | } | |
673a394b | 2015 | |
9d773091 | 2016 | request->seqno = intel_ring_get_seqno(ring); |
852835f3 | 2017 | request->ring = ring; |
a71d8d94 | 2018 | request->tail = request_ring_position; |
673a394b | 2019 | request->emitted_jiffies = jiffies; |
852835f3 ZN |
2020 | was_empty = list_empty(&ring->request_list); |
2021 | list_add_tail(&request->list, &ring->request_list); | |
3bb73aba | 2022 | request->file_priv = NULL; |
852835f3 | 2023 | |
db53a302 CW |
2024 | if (file) { |
2025 | struct drm_i915_file_private *file_priv = file->driver_priv; | |
2026 | ||
1c25595f | 2027 | spin_lock(&file_priv->mm.lock); |
f787a5f5 | 2028 | request->file_priv = file_priv; |
b962442e | 2029 | list_add_tail(&request->client_list, |
f787a5f5 | 2030 | &file_priv->mm.request_list); |
1c25595f | 2031 | spin_unlock(&file_priv->mm.lock); |
b962442e | 2032 | } |
673a394b | 2033 | |
9d773091 | 2034 | trace_i915_gem_request_add(ring, request->seqno); |
5391d0cf | 2035 | ring->outstanding_lazy_request = 0; |
db53a302 | 2036 | |
f65d9421 | 2037 | if (!dev_priv->mm.suspended) { |
3e0dc6b0 BW |
2038 | if (i915_enable_hangcheck) { |
2039 | mod_timer(&dev_priv->hangcheck_timer, | |
cecc21fe | 2040 | round_jiffies_up(jiffies + DRM_I915_HANGCHECK_JIFFIES)); |
3e0dc6b0 | 2041 | } |
f047e395 | 2042 | if (was_empty) { |
b3b079db | 2043 | queue_delayed_work(dev_priv->wq, |
bcb45086 CW |
2044 | &dev_priv->mm.retire_work, |
2045 | round_jiffies_up_relative(HZ)); | |
f047e395 CW |
2046 | intel_mark_busy(dev_priv->dev); |
2047 | } | |
f65d9421 | 2048 | } |
cc889e0f | 2049 | |
acb868d3 | 2050 | if (out_seqno) |
9d773091 | 2051 | *out_seqno = request->seqno; |
3cce469c | 2052 | return 0; |
673a394b EA |
2053 | } |
2054 | ||
f787a5f5 CW |
2055 | static inline void |
2056 | i915_gem_request_remove_from_client(struct drm_i915_gem_request *request) | |
673a394b | 2057 | { |
1c25595f | 2058 | struct drm_i915_file_private *file_priv = request->file_priv; |
673a394b | 2059 | |
1c25595f CW |
2060 | if (!file_priv) |
2061 | return; | |
1c5d22f7 | 2062 | |
1c25595f | 2063 | spin_lock(&file_priv->mm.lock); |
09bfa517 HRK |
2064 | if (request->file_priv) { |
2065 | list_del(&request->client_list); | |
2066 | request->file_priv = NULL; | |
2067 | } | |
1c25595f | 2068 | spin_unlock(&file_priv->mm.lock); |
673a394b | 2069 | } |
673a394b | 2070 | |
dfaae392 CW |
2071 | static void i915_gem_reset_ring_lists(struct drm_i915_private *dev_priv, |
2072 | struct intel_ring_buffer *ring) | |
9375e446 | 2073 | { |
dfaae392 CW |
2074 | while (!list_empty(&ring->request_list)) { |
2075 | struct drm_i915_gem_request *request; | |
673a394b | 2076 | |
dfaae392 CW |
2077 | request = list_first_entry(&ring->request_list, |
2078 | struct drm_i915_gem_request, | |
2079 | list); | |
de151cf6 | 2080 | |
dfaae392 | 2081 | list_del(&request->list); |
f787a5f5 | 2082 | i915_gem_request_remove_from_client(request); |
dfaae392 CW |
2083 | kfree(request); |
2084 | } | |
673a394b | 2085 | |
dfaae392 | 2086 | while (!list_empty(&ring->active_list)) { |
05394f39 | 2087 | struct drm_i915_gem_object *obj; |
9375e446 | 2088 | |
05394f39 CW |
2089 | obj = list_first_entry(&ring->active_list, |
2090 | struct drm_i915_gem_object, | |
2091 | ring_list); | |
9375e446 | 2092 | |
05394f39 | 2093 | i915_gem_object_move_to_inactive(obj); |
673a394b EA |
2094 | } |
2095 | } | |
2096 | ||
312817a3 CW |
2097 | static void i915_gem_reset_fences(struct drm_device *dev) |
2098 | { | |
2099 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2100 | int i; | |
2101 | ||
4b9de737 | 2102 | for (i = 0; i < dev_priv->num_fence_regs; i++) { |
312817a3 | 2103 | struct drm_i915_fence_reg *reg = &dev_priv->fence_regs[i]; |
7d2cb39c | 2104 | |
ada726c7 | 2105 | i915_gem_write_fence(dev, i, NULL); |
7d2cb39c | 2106 | |
ada726c7 CW |
2107 | if (reg->obj) |
2108 | i915_gem_object_fence_lost(reg->obj); | |
7d2cb39c | 2109 | |
ada726c7 CW |
2110 | reg->pin_count = 0; |
2111 | reg->obj = NULL; | |
2112 | INIT_LIST_HEAD(®->lru_list); | |
312817a3 | 2113 | } |
ada726c7 CW |
2114 | |
2115 | INIT_LIST_HEAD(&dev_priv->mm.fence_list); | |
312817a3 CW |
2116 | } |
2117 | ||
069efc1d | 2118 | void i915_gem_reset(struct drm_device *dev) |
673a394b | 2119 | { |
77f01230 | 2120 | struct drm_i915_private *dev_priv = dev->dev_private; |
05394f39 | 2121 | struct drm_i915_gem_object *obj; |
b4519513 | 2122 | struct intel_ring_buffer *ring; |
1ec14ad3 | 2123 | int i; |
673a394b | 2124 | |
b4519513 CW |
2125 | for_each_ring(ring, dev_priv, i) |
2126 | i915_gem_reset_ring_lists(dev_priv, ring); | |
dfaae392 | 2127 | |
dfaae392 CW |
2128 | /* Move everything out of the GPU domains to ensure we do any |
2129 | * necessary invalidation upon reuse. | |
2130 | */ | |
05394f39 | 2131 | list_for_each_entry(obj, |
77f01230 | 2132 | &dev_priv->mm.inactive_list, |
69dc4987 | 2133 | mm_list) |
77f01230 | 2134 | { |
05394f39 | 2135 | obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS; |
77f01230 | 2136 | } |
069efc1d CW |
2137 | |
2138 | /* The fence registers are invalidated so clear them out */ | |
312817a3 | 2139 | i915_gem_reset_fences(dev); |
673a394b EA |
2140 | } |
2141 | ||
2142 | /** | |
2143 | * This function clears the request list as sequence numbers are passed. | |
2144 | */ | |
a71d8d94 | 2145 | void |
db53a302 | 2146 | i915_gem_retire_requests_ring(struct intel_ring_buffer *ring) |
673a394b | 2147 | { |
673a394b EA |
2148 | uint32_t seqno; |
2149 | ||
db53a302 | 2150 | if (list_empty(&ring->request_list)) |
6c0594a3 KW |
2151 | return; |
2152 | ||
db53a302 | 2153 | WARN_ON(i915_verify_lists(ring->dev)); |
673a394b | 2154 | |
b2eadbc8 | 2155 | seqno = ring->get_seqno(ring, true); |
1ec14ad3 | 2156 | |
852835f3 | 2157 | while (!list_empty(&ring->request_list)) { |
673a394b | 2158 | struct drm_i915_gem_request *request; |
673a394b | 2159 | |
852835f3 | 2160 | request = list_first_entry(&ring->request_list, |
673a394b EA |
2161 | struct drm_i915_gem_request, |
2162 | list); | |
673a394b | 2163 | |
dfaae392 | 2164 | if (!i915_seqno_passed(seqno, request->seqno)) |
b84d5f0c CW |
2165 | break; |
2166 | ||
db53a302 | 2167 | trace_i915_gem_request_retire(ring, request->seqno); |
a71d8d94 CW |
2168 | /* We know the GPU must have read the request to have |
2169 | * sent us the seqno + interrupt, so use the position | |
2170 | * of tail of the request to update the last known position | |
2171 | * of the GPU head. | |
2172 | */ | |
2173 | ring->last_retired_head = request->tail; | |
b84d5f0c CW |
2174 | |
2175 | list_del(&request->list); | |
f787a5f5 | 2176 | i915_gem_request_remove_from_client(request); |
b84d5f0c CW |
2177 | kfree(request); |
2178 | } | |
673a394b | 2179 | |
b84d5f0c CW |
2180 | /* Move any buffers on the active list that are no longer referenced |
2181 | * by the ringbuffer to the flushing/inactive lists as appropriate. | |
2182 | */ | |
2183 | while (!list_empty(&ring->active_list)) { | |
05394f39 | 2184 | struct drm_i915_gem_object *obj; |
b84d5f0c | 2185 | |
0206e353 | 2186 | obj = list_first_entry(&ring->active_list, |
05394f39 CW |
2187 | struct drm_i915_gem_object, |
2188 | ring_list); | |
673a394b | 2189 | |
0201f1ec | 2190 | if (!i915_seqno_passed(seqno, obj->last_read_seqno)) |
673a394b | 2191 | break; |
b84d5f0c | 2192 | |
65ce3027 | 2193 | i915_gem_object_move_to_inactive(obj); |
673a394b | 2194 | } |
9d34e5db | 2195 | |
db53a302 CW |
2196 | if (unlikely(ring->trace_irq_seqno && |
2197 | i915_seqno_passed(seqno, ring->trace_irq_seqno))) { | |
1ec14ad3 | 2198 | ring->irq_put(ring); |
db53a302 | 2199 | ring->trace_irq_seqno = 0; |
9d34e5db | 2200 | } |
23bc5982 | 2201 | |
db53a302 | 2202 | WARN_ON(i915_verify_lists(ring->dev)); |
673a394b EA |
2203 | } |
2204 | ||
b09a1fec CW |
2205 | void |
2206 | i915_gem_retire_requests(struct drm_device *dev) | |
2207 | { | |
2208 | drm_i915_private_t *dev_priv = dev->dev_private; | |
b4519513 | 2209 | struct intel_ring_buffer *ring; |
1ec14ad3 | 2210 | int i; |
b09a1fec | 2211 | |
b4519513 CW |
2212 | for_each_ring(ring, dev_priv, i) |
2213 | i915_gem_retire_requests_ring(ring); | |
b09a1fec CW |
2214 | } |
2215 | ||
75ef9da2 | 2216 | static void |
673a394b EA |
2217 | i915_gem_retire_work_handler(struct work_struct *work) |
2218 | { | |
2219 | drm_i915_private_t *dev_priv; | |
2220 | struct drm_device *dev; | |
b4519513 | 2221 | struct intel_ring_buffer *ring; |
0a58705b CW |
2222 | bool idle; |
2223 | int i; | |
673a394b EA |
2224 | |
2225 | dev_priv = container_of(work, drm_i915_private_t, | |
2226 | mm.retire_work.work); | |
2227 | dev = dev_priv->dev; | |
2228 | ||
891b48cf CW |
2229 | /* Come back later if the device is busy... */ |
2230 | if (!mutex_trylock(&dev->struct_mutex)) { | |
bcb45086 CW |
2231 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, |
2232 | round_jiffies_up_relative(HZ)); | |
891b48cf CW |
2233 | return; |
2234 | } | |
673a394b | 2235 | |
b09a1fec | 2236 | i915_gem_retire_requests(dev); |
673a394b | 2237 | |
0a58705b CW |
2238 | /* Send a periodic flush down the ring so we don't hold onto GEM |
2239 | * objects indefinitely. | |
673a394b | 2240 | */ |
0a58705b | 2241 | idle = true; |
b4519513 | 2242 | for_each_ring(ring, dev_priv, i) { |
3bb73aba CW |
2243 | if (ring->gpu_caches_dirty) |
2244 | i915_add_request(ring, NULL, NULL); | |
0a58705b CW |
2245 | |
2246 | idle &= list_empty(&ring->request_list); | |
673a394b EA |
2247 | } |
2248 | ||
0a58705b | 2249 | if (!dev_priv->mm.suspended && !idle) |
bcb45086 CW |
2250 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, |
2251 | round_jiffies_up_relative(HZ)); | |
f047e395 CW |
2252 | if (idle) |
2253 | intel_mark_idle(dev); | |
0a58705b | 2254 | |
673a394b | 2255 | mutex_unlock(&dev->struct_mutex); |
673a394b EA |
2256 | } |
2257 | ||
30dfebf3 DV |
2258 | /** |
2259 | * Ensures that an object will eventually get non-busy by flushing any required | |
2260 | * write domains, emitting any outstanding lazy request and retiring and | |
2261 | * completed requests. | |
2262 | */ | |
2263 | static int | |
2264 | i915_gem_object_flush_active(struct drm_i915_gem_object *obj) | |
2265 | { | |
2266 | int ret; | |
2267 | ||
2268 | if (obj->active) { | |
0201f1ec | 2269 | ret = i915_gem_check_olr(obj->ring, obj->last_read_seqno); |
30dfebf3 DV |
2270 | if (ret) |
2271 | return ret; | |
2272 | ||
30dfebf3 DV |
2273 | i915_gem_retire_requests_ring(obj->ring); |
2274 | } | |
2275 | ||
2276 | return 0; | |
2277 | } | |
2278 | ||
23ba4fd0 BW |
2279 | /** |
2280 | * i915_gem_wait_ioctl - implements DRM_IOCTL_I915_GEM_WAIT | |
2281 | * @DRM_IOCTL_ARGS: standard ioctl arguments | |
2282 | * | |
2283 | * Returns 0 if successful, else an error is returned with the remaining time in | |
2284 | * the timeout parameter. | |
2285 | * -ETIME: object is still busy after timeout | |
2286 | * -ERESTARTSYS: signal interrupted the wait | |
2287 | * -ENONENT: object doesn't exist | |
2288 | * Also possible, but rare: | |
2289 | * -EAGAIN: GPU wedged | |
2290 | * -ENOMEM: damn | |
2291 | * -ENODEV: Internal IRQ fail | |
2292 | * -E?: The add request failed | |
2293 | * | |
2294 | * The wait ioctl with a timeout of 0 reimplements the busy ioctl. With any | |
2295 | * non-zero timeout parameter the wait ioctl will wait for the given number of | |
2296 | * nanoseconds on an object becoming unbusy. Since the wait itself does so | |
2297 | * without holding struct_mutex the object may become re-busied before this | |
2298 | * function completes. A similar but shorter * race condition exists in the busy | |
2299 | * ioctl | |
2300 | */ | |
2301 | int | |
2302 | i915_gem_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *file) | |
2303 | { | |
2304 | struct drm_i915_gem_wait *args = data; | |
2305 | struct drm_i915_gem_object *obj; | |
2306 | struct intel_ring_buffer *ring = NULL; | |
eac1f14f | 2307 | struct timespec timeout_stack, *timeout = NULL; |
23ba4fd0 BW |
2308 | u32 seqno = 0; |
2309 | int ret = 0; | |
2310 | ||
eac1f14f BW |
2311 | if (args->timeout_ns >= 0) { |
2312 | timeout_stack = ns_to_timespec(args->timeout_ns); | |
2313 | timeout = &timeout_stack; | |
2314 | } | |
23ba4fd0 BW |
2315 | |
2316 | ret = i915_mutex_lock_interruptible(dev); | |
2317 | if (ret) | |
2318 | return ret; | |
2319 | ||
2320 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->bo_handle)); | |
2321 | if (&obj->base == NULL) { | |
2322 | mutex_unlock(&dev->struct_mutex); | |
2323 | return -ENOENT; | |
2324 | } | |
2325 | ||
30dfebf3 DV |
2326 | /* Need to make sure the object gets inactive eventually. */ |
2327 | ret = i915_gem_object_flush_active(obj); | |
23ba4fd0 BW |
2328 | if (ret) |
2329 | goto out; | |
2330 | ||
2331 | if (obj->active) { | |
0201f1ec | 2332 | seqno = obj->last_read_seqno; |
23ba4fd0 BW |
2333 | ring = obj->ring; |
2334 | } | |
2335 | ||
2336 | if (seqno == 0) | |
2337 | goto out; | |
2338 | ||
23ba4fd0 BW |
2339 | /* Do this after OLR check to make sure we make forward progress polling |
2340 | * on this IOCTL with a 0 timeout (like busy ioctl) | |
2341 | */ | |
2342 | if (!args->timeout_ns) { | |
2343 | ret = -ETIME; | |
2344 | goto out; | |
2345 | } | |
2346 | ||
2347 | drm_gem_object_unreference(&obj->base); | |
2348 | mutex_unlock(&dev->struct_mutex); | |
2349 | ||
eac1f14f BW |
2350 | ret = __wait_seqno(ring, seqno, true, timeout); |
2351 | if (timeout) { | |
2352 | WARN_ON(!timespec_valid(timeout)); | |
2353 | args->timeout_ns = timespec_to_ns(timeout); | |
2354 | } | |
23ba4fd0 BW |
2355 | return ret; |
2356 | ||
2357 | out: | |
2358 | drm_gem_object_unreference(&obj->base); | |
2359 | mutex_unlock(&dev->struct_mutex); | |
2360 | return ret; | |
2361 | } | |
2362 | ||
5816d648 BW |
2363 | /** |
2364 | * i915_gem_object_sync - sync an object to a ring. | |
2365 | * | |
2366 | * @obj: object which may be in use on another ring. | |
2367 | * @to: ring we wish to use the object on. May be NULL. | |
2368 | * | |
2369 | * This code is meant to abstract object synchronization with the GPU. | |
2370 | * Calling with NULL implies synchronizing the object with the CPU | |
2371 | * rather than a particular GPU ring. | |
2372 | * | |
2373 | * Returns 0 if successful, else propagates up the lower layer error. | |
2374 | */ | |
2911a35b BW |
2375 | int |
2376 | i915_gem_object_sync(struct drm_i915_gem_object *obj, | |
2377 | struct intel_ring_buffer *to) | |
2378 | { | |
2379 | struct intel_ring_buffer *from = obj->ring; | |
2380 | u32 seqno; | |
2381 | int ret, idx; | |
2382 | ||
2383 | if (from == NULL || to == from) | |
2384 | return 0; | |
2385 | ||
5816d648 | 2386 | if (to == NULL || !i915_semaphore_is_enabled(obj->base.dev)) |
0201f1ec | 2387 | return i915_gem_object_wait_rendering(obj, false); |
2911a35b BW |
2388 | |
2389 | idx = intel_ring_sync_index(from, to); | |
2390 | ||
0201f1ec | 2391 | seqno = obj->last_read_seqno; |
2911a35b BW |
2392 | if (seqno <= from->sync_seqno[idx]) |
2393 | return 0; | |
2394 | ||
b4aca010 BW |
2395 | ret = i915_gem_check_olr(obj->ring, seqno); |
2396 | if (ret) | |
2397 | return ret; | |
2911a35b | 2398 | |
1500f7ea | 2399 | ret = to->sync_to(to, from, seqno); |
e3a5a225 | 2400 | if (!ret) |
7b01e260 MK |
2401 | /* We use last_read_seqno because sync_to() |
2402 | * might have just caused seqno wrap under | |
2403 | * the radar. | |
2404 | */ | |
2405 | from->sync_seqno[idx] = obj->last_read_seqno; | |
2911a35b | 2406 | |
e3a5a225 | 2407 | return ret; |
2911a35b BW |
2408 | } |
2409 | ||
b5ffc9bc CW |
2410 | static void i915_gem_object_finish_gtt(struct drm_i915_gem_object *obj) |
2411 | { | |
2412 | u32 old_write_domain, old_read_domains; | |
2413 | ||
b5ffc9bc CW |
2414 | /* Act a barrier for all accesses through the GTT */ |
2415 | mb(); | |
2416 | ||
2417 | /* Force a pagefault for domain tracking on next user access */ | |
2418 | i915_gem_release_mmap(obj); | |
2419 | ||
b97c3d9c KP |
2420 | if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0) |
2421 | return; | |
2422 | ||
b5ffc9bc CW |
2423 | old_read_domains = obj->base.read_domains; |
2424 | old_write_domain = obj->base.write_domain; | |
2425 | ||
2426 | obj->base.read_domains &= ~I915_GEM_DOMAIN_GTT; | |
2427 | obj->base.write_domain &= ~I915_GEM_DOMAIN_GTT; | |
2428 | ||
2429 | trace_i915_gem_object_change_domain(obj, | |
2430 | old_read_domains, | |
2431 | old_write_domain); | |
2432 | } | |
2433 | ||
673a394b EA |
2434 | /** |
2435 | * Unbinds an object from the GTT aperture. | |
2436 | */ | |
0f973f27 | 2437 | int |
05394f39 | 2438 | i915_gem_object_unbind(struct drm_i915_gem_object *obj) |
673a394b | 2439 | { |
7bddb01f | 2440 | drm_i915_private_t *dev_priv = obj->base.dev->dev_private; |
673a394b EA |
2441 | int ret = 0; |
2442 | ||
05394f39 | 2443 | if (obj->gtt_space == NULL) |
673a394b EA |
2444 | return 0; |
2445 | ||
31d8d651 CW |
2446 | if (obj->pin_count) |
2447 | return -EBUSY; | |
673a394b | 2448 | |
c4670ad0 CW |
2449 | BUG_ON(obj->pages == NULL); |
2450 | ||
a8198eea | 2451 | ret = i915_gem_object_finish_gpu(obj); |
1488fc08 | 2452 | if (ret) |
a8198eea CW |
2453 | return ret; |
2454 | /* Continue on if we fail due to EIO, the GPU is hung so we | |
2455 | * should be safe and we need to cleanup or else we might | |
2456 | * cause memory corruption through use-after-free. | |
2457 | */ | |
2458 | ||
b5ffc9bc | 2459 | i915_gem_object_finish_gtt(obj); |
5323fd04 | 2460 | |
96b47b65 | 2461 | /* release the fence reg _after_ flushing */ |
d9e86c0e | 2462 | ret = i915_gem_object_put_fence(obj); |
1488fc08 | 2463 | if (ret) |
d9e86c0e | 2464 | return ret; |
96b47b65 | 2465 | |
db53a302 CW |
2466 | trace_i915_gem_object_unbind(obj); |
2467 | ||
74898d7e DV |
2468 | if (obj->has_global_gtt_mapping) |
2469 | i915_gem_gtt_unbind_object(obj); | |
7bddb01f DV |
2470 | if (obj->has_aliasing_ppgtt_mapping) { |
2471 | i915_ppgtt_unbind_object(dev_priv->mm.aliasing_ppgtt, obj); | |
2472 | obj->has_aliasing_ppgtt_mapping = 0; | |
2473 | } | |
74163907 | 2474 | i915_gem_gtt_finish_object(obj); |
7bddb01f | 2475 | |
6c085a72 CW |
2476 | list_del(&obj->mm_list); |
2477 | list_move_tail(&obj->gtt_list, &dev_priv->mm.unbound_list); | |
75e9e915 | 2478 | /* Avoid an unnecessary call to unbind on rebind. */ |
05394f39 | 2479 | obj->map_and_fenceable = true; |
673a394b | 2480 | |
05394f39 CW |
2481 | drm_mm_put_block(obj->gtt_space); |
2482 | obj->gtt_space = NULL; | |
2483 | obj->gtt_offset = 0; | |
673a394b | 2484 | |
88241785 | 2485 | return 0; |
54cf91dc CW |
2486 | } |
2487 | ||
b2da9fe5 | 2488 | int i915_gpu_idle(struct drm_device *dev) |
4df2faf4 DV |
2489 | { |
2490 | drm_i915_private_t *dev_priv = dev->dev_private; | |
b4519513 | 2491 | struct intel_ring_buffer *ring; |
1ec14ad3 | 2492 | int ret, i; |
4df2faf4 | 2493 | |
4df2faf4 | 2494 | /* Flush everything onto the inactive list. */ |
b4519513 | 2495 | for_each_ring(ring, dev_priv, i) { |
b6c7488d BW |
2496 | ret = i915_switch_context(ring, NULL, DEFAULT_CONTEXT_ID); |
2497 | if (ret) | |
2498 | return ret; | |
2499 | ||
3e960501 | 2500 | ret = intel_ring_idle(ring); |
1ec14ad3 CW |
2501 | if (ret) |
2502 | return ret; | |
2503 | } | |
4df2faf4 | 2504 | |
8a1a49f9 | 2505 | return 0; |
4df2faf4 DV |
2506 | } |
2507 | ||
9ce079e4 CW |
2508 | static void sandybridge_write_fence_reg(struct drm_device *dev, int reg, |
2509 | struct drm_i915_gem_object *obj) | |
4e901fdc | 2510 | { |
4e901fdc | 2511 | drm_i915_private_t *dev_priv = dev->dev_private; |
4e901fdc EA |
2512 | uint64_t val; |
2513 | ||
9ce079e4 CW |
2514 | if (obj) { |
2515 | u32 size = obj->gtt_space->size; | |
4e901fdc | 2516 | |
9ce079e4 CW |
2517 | val = (uint64_t)((obj->gtt_offset + size - 4096) & |
2518 | 0xfffff000) << 32; | |
2519 | val |= obj->gtt_offset & 0xfffff000; | |
2520 | val |= (uint64_t)((obj->stride / 128) - 1) << | |
2521 | SANDYBRIDGE_FENCE_PITCH_SHIFT; | |
4e901fdc | 2522 | |
9ce079e4 CW |
2523 | if (obj->tiling_mode == I915_TILING_Y) |
2524 | val |= 1 << I965_FENCE_TILING_Y_SHIFT; | |
2525 | val |= I965_FENCE_REG_VALID; | |
2526 | } else | |
2527 | val = 0; | |
c6642782 | 2528 | |
9ce079e4 CW |
2529 | I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + reg * 8, val); |
2530 | POSTING_READ(FENCE_REG_SANDYBRIDGE_0 + reg * 8); | |
4e901fdc EA |
2531 | } |
2532 | ||
9ce079e4 CW |
2533 | static void i965_write_fence_reg(struct drm_device *dev, int reg, |
2534 | struct drm_i915_gem_object *obj) | |
de151cf6 | 2535 | { |
de151cf6 | 2536 | drm_i915_private_t *dev_priv = dev->dev_private; |
de151cf6 JB |
2537 | uint64_t val; |
2538 | ||
9ce079e4 CW |
2539 | if (obj) { |
2540 | u32 size = obj->gtt_space->size; | |
de151cf6 | 2541 | |
9ce079e4 CW |
2542 | val = (uint64_t)((obj->gtt_offset + size - 4096) & |
2543 | 0xfffff000) << 32; | |
2544 | val |= obj->gtt_offset & 0xfffff000; | |
2545 | val |= ((obj->stride / 128) - 1) << I965_FENCE_PITCH_SHIFT; | |
2546 | if (obj->tiling_mode == I915_TILING_Y) | |
2547 | val |= 1 << I965_FENCE_TILING_Y_SHIFT; | |
2548 | val |= I965_FENCE_REG_VALID; | |
2549 | } else | |
2550 | val = 0; | |
c6642782 | 2551 | |
9ce079e4 CW |
2552 | I915_WRITE64(FENCE_REG_965_0 + reg * 8, val); |
2553 | POSTING_READ(FENCE_REG_965_0 + reg * 8); | |
de151cf6 JB |
2554 | } |
2555 | ||
9ce079e4 CW |
2556 | static void i915_write_fence_reg(struct drm_device *dev, int reg, |
2557 | struct drm_i915_gem_object *obj) | |
de151cf6 | 2558 | { |
de151cf6 | 2559 | drm_i915_private_t *dev_priv = dev->dev_private; |
9ce079e4 | 2560 | u32 val; |
de151cf6 | 2561 | |
9ce079e4 CW |
2562 | if (obj) { |
2563 | u32 size = obj->gtt_space->size; | |
2564 | int pitch_val; | |
2565 | int tile_width; | |
c6642782 | 2566 | |
9ce079e4 CW |
2567 | WARN((obj->gtt_offset & ~I915_FENCE_START_MASK) || |
2568 | (size & -size) != size || | |
2569 | (obj->gtt_offset & (size - 1)), | |
2570 | "object 0x%08x [fenceable? %d] not 1M or pot-size (0x%08x) aligned\n", | |
2571 | obj->gtt_offset, obj->map_and_fenceable, size); | |
c6642782 | 2572 | |
9ce079e4 CW |
2573 | if (obj->tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev)) |
2574 | tile_width = 128; | |
2575 | else | |
2576 | tile_width = 512; | |
2577 | ||
2578 | /* Note: pitch better be a power of two tile widths */ | |
2579 | pitch_val = obj->stride / tile_width; | |
2580 | pitch_val = ffs(pitch_val) - 1; | |
2581 | ||
2582 | val = obj->gtt_offset; | |
2583 | if (obj->tiling_mode == I915_TILING_Y) | |
2584 | val |= 1 << I830_FENCE_TILING_Y_SHIFT; | |
2585 | val |= I915_FENCE_SIZE_BITS(size); | |
2586 | val |= pitch_val << I830_FENCE_PITCH_SHIFT; | |
2587 | val |= I830_FENCE_REG_VALID; | |
2588 | } else | |
2589 | val = 0; | |
2590 | ||
2591 | if (reg < 8) | |
2592 | reg = FENCE_REG_830_0 + reg * 4; | |
2593 | else | |
2594 | reg = FENCE_REG_945_8 + (reg - 8) * 4; | |
2595 | ||
2596 | I915_WRITE(reg, val); | |
2597 | POSTING_READ(reg); | |
de151cf6 JB |
2598 | } |
2599 | ||
9ce079e4 CW |
2600 | static void i830_write_fence_reg(struct drm_device *dev, int reg, |
2601 | struct drm_i915_gem_object *obj) | |
de151cf6 | 2602 | { |
de151cf6 | 2603 | drm_i915_private_t *dev_priv = dev->dev_private; |
de151cf6 | 2604 | uint32_t val; |
de151cf6 | 2605 | |
9ce079e4 CW |
2606 | if (obj) { |
2607 | u32 size = obj->gtt_space->size; | |
2608 | uint32_t pitch_val; | |
de151cf6 | 2609 | |
9ce079e4 CW |
2610 | WARN((obj->gtt_offset & ~I830_FENCE_START_MASK) || |
2611 | (size & -size) != size || | |
2612 | (obj->gtt_offset & (size - 1)), | |
2613 | "object 0x%08x not 512K or pot-size 0x%08x aligned\n", | |
2614 | obj->gtt_offset, size); | |
e76a16de | 2615 | |
9ce079e4 CW |
2616 | pitch_val = obj->stride / 128; |
2617 | pitch_val = ffs(pitch_val) - 1; | |
de151cf6 | 2618 | |
9ce079e4 CW |
2619 | val = obj->gtt_offset; |
2620 | if (obj->tiling_mode == I915_TILING_Y) | |
2621 | val |= 1 << I830_FENCE_TILING_Y_SHIFT; | |
2622 | val |= I830_FENCE_SIZE_BITS(size); | |
2623 | val |= pitch_val << I830_FENCE_PITCH_SHIFT; | |
2624 | val |= I830_FENCE_REG_VALID; | |
2625 | } else | |
2626 | val = 0; | |
c6642782 | 2627 | |
9ce079e4 CW |
2628 | I915_WRITE(FENCE_REG_830_0 + reg * 4, val); |
2629 | POSTING_READ(FENCE_REG_830_0 + reg * 4); | |
2630 | } | |
2631 | ||
2632 | static void i915_gem_write_fence(struct drm_device *dev, int reg, | |
2633 | struct drm_i915_gem_object *obj) | |
2634 | { | |
2635 | switch (INTEL_INFO(dev)->gen) { | |
2636 | case 7: | |
2637 | case 6: sandybridge_write_fence_reg(dev, reg, obj); break; | |
2638 | case 5: | |
2639 | case 4: i965_write_fence_reg(dev, reg, obj); break; | |
2640 | case 3: i915_write_fence_reg(dev, reg, obj); break; | |
2641 | case 2: i830_write_fence_reg(dev, reg, obj); break; | |
2642 | default: break; | |
2643 | } | |
de151cf6 JB |
2644 | } |
2645 | ||
61050808 CW |
2646 | static inline int fence_number(struct drm_i915_private *dev_priv, |
2647 | struct drm_i915_fence_reg *fence) | |
2648 | { | |
2649 | return fence - dev_priv->fence_regs; | |
2650 | } | |
2651 | ||
2652 | static void i915_gem_object_update_fence(struct drm_i915_gem_object *obj, | |
2653 | struct drm_i915_fence_reg *fence, | |
2654 | bool enable) | |
2655 | { | |
2656 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; | |
2657 | int reg = fence_number(dev_priv, fence); | |
2658 | ||
2659 | i915_gem_write_fence(obj->base.dev, reg, enable ? obj : NULL); | |
2660 | ||
2661 | if (enable) { | |
2662 | obj->fence_reg = reg; | |
2663 | fence->obj = obj; | |
2664 | list_move_tail(&fence->lru_list, &dev_priv->mm.fence_list); | |
2665 | } else { | |
2666 | obj->fence_reg = I915_FENCE_REG_NONE; | |
2667 | fence->obj = NULL; | |
2668 | list_del_init(&fence->lru_list); | |
2669 | } | |
2670 | } | |
2671 | ||
d9e86c0e | 2672 | static int |
a360bb1a | 2673 | i915_gem_object_flush_fence(struct drm_i915_gem_object *obj) |
d9e86c0e | 2674 | { |
1c293ea3 | 2675 | if (obj->last_fenced_seqno) { |
86d5bc37 | 2676 | int ret = i915_wait_seqno(obj->ring, obj->last_fenced_seqno); |
18991845 CW |
2677 | if (ret) |
2678 | return ret; | |
d9e86c0e CW |
2679 | |
2680 | obj->last_fenced_seqno = 0; | |
d9e86c0e CW |
2681 | } |
2682 | ||
63256ec5 CW |
2683 | /* Ensure that all CPU reads are completed before installing a fence |
2684 | * and all writes before removing the fence. | |
2685 | */ | |
2686 | if (obj->base.read_domains & I915_GEM_DOMAIN_GTT) | |
2687 | mb(); | |
2688 | ||
86d5bc37 | 2689 | obj->fenced_gpu_access = false; |
d9e86c0e CW |
2690 | return 0; |
2691 | } | |
2692 | ||
2693 | int | |
2694 | i915_gem_object_put_fence(struct drm_i915_gem_object *obj) | |
2695 | { | |
61050808 | 2696 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
d9e86c0e CW |
2697 | int ret; |
2698 | ||
a360bb1a | 2699 | ret = i915_gem_object_flush_fence(obj); |
d9e86c0e CW |
2700 | if (ret) |
2701 | return ret; | |
2702 | ||
61050808 CW |
2703 | if (obj->fence_reg == I915_FENCE_REG_NONE) |
2704 | return 0; | |
d9e86c0e | 2705 | |
61050808 CW |
2706 | i915_gem_object_update_fence(obj, |
2707 | &dev_priv->fence_regs[obj->fence_reg], | |
2708 | false); | |
2709 | i915_gem_object_fence_lost(obj); | |
d9e86c0e CW |
2710 | |
2711 | return 0; | |
2712 | } | |
2713 | ||
2714 | static struct drm_i915_fence_reg * | |
a360bb1a | 2715 | i915_find_fence_reg(struct drm_device *dev) |
ae3db24a | 2716 | { |
ae3db24a | 2717 | struct drm_i915_private *dev_priv = dev->dev_private; |
8fe301ad | 2718 | struct drm_i915_fence_reg *reg, *avail; |
d9e86c0e | 2719 | int i; |
ae3db24a DV |
2720 | |
2721 | /* First try to find a free reg */ | |
d9e86c0e | 2722 | avail = NULL; |
ae3db24a DV |
2723 | for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) { |
2724 | reg = &dev_priv->fence_regs[i]; | |
2725 | if (!reg->obj) | |
d9e86c0e | 2726 | return reg; |
ae3db24a | 2727 | |
1690e1eb | 2728 | if (!reg->pin_count) |
d9e86c0e | 2729 | avail = reg; |
ae3db24a DV |
2730 | } |
2731 | ||
d9e86c0e CW |
2732 | if (avail == NULL) |
2733 | return NULL; | |
ae3db24a DV |
2734 | |
2735 | /* None available, try to steal one or wait for a user to finish */ | |
d9e86c0e | 2736 | list_for_each_entry(reg, &dev_priv->mm.fence_list, lru_list) { |
1690e1eb | 2737 | if (reg->pin_count) |
ae3db24a DV |
2738 | continue; |
2739 | ||
8fe301ad | 2740 | return reg; |
ae3db24a DV |
2741 | } |
2742 | ||
8fe301ad | 2743 | return NULL; |
ae3db24a DV |
2744 | } |
2745 | ||
de151cf6 | 2746 | /** |
9a5a53b3 | 2747 | * i915_gem_object_get_fence - set up fencing for an object |
de151cf6 JB |
2748 | * @obj: object to map through a fence reg |
2749 | * | |
2750 | * When mapping objects through the GTT, userspace wants to be able to write | |
2751 | * to them without having to worry about swizzling if the object is tiled. | |
de151cf6 JB |
2752 | * This function walks the fence regs looking for a free one for @obj, |
2753 | * stealing one if it can't find any. | |
2754 | * | |
2755 | * It then sets up the reg based on the object's properties: address, pitch | |
2756 | * and tiling format. | |
9a5a53b3 CW |
2757 | * |
2758 | * For an untiled surface, this removes any existing fence. | |
de151cf6 | 2759 | */ |
8c4b8c3f | 2760 | int |
06d98131 | 2761 | i915_gem_object_get_fence(struct drm_i915_gem_object *obj) |
de151cf6 | 2762 | { |
05394f39 | 2763 | struct drm_device *dev = obj->base.dev; |
79e53945 | 2764 | struct drm_i915_private *dev_priv = dev->dev_private; |
14415745 | 2765 | bool enable = obj->tiling_mode != I915_TILING_NONE; |
d9e86c0e | 2766 | struct drm_i915_fence_reg *reg; |
ae3db24a | 2767 | int ret; |
de151cf6 | 2768 | |
14415745 CW |
2769 | /* Have we updated the tiling parameters upon the object and so |
2770 | * will need to serialise the write to the associated fence register? | |
2771 | */ | |
5d82e3e6 | 2772 | if (obj->fence_dirty) { |
14415745 CW |
2773 | ret = i915_gem_object_flush_fence(obj); |
2774 | if (ret) | |
2775 | return ret; | |
2776 | } | |
9a5a53b3 | 2777 | |
d9e86c0e | 2778 | /* Just update our place in the LRU if our fence is getting reused. */ |
05394f39 CW |
2779 | if (obj->fence_reg != I915_FENCE_REG_NONE) { |
2780 | reg = &dev_priv->fence_regs[obj->fence_reg]; | |
5d82e3e6 | 2781 | if (!obj->fence_dirty) { |
14415745 CW |
2782 | list_move_tail(®->lru_list, |
2783 | &dev_priv->mm.fence_list); | |
2784 | return 0; | |
2785 | } | |
2786 | } else if (enable) { | |
2787 | reg = i915_find_fence_reg(dev); | |
2788 | if (reg == NULL) | |
2789 | return -EDEADLK; | |
d9e86c0e | 2790 | |
14415745 CW |
2791 | if (reg->obj) { |
2792 | struct drm_i915_gem_object *old = reg->obj; | |
2793 | ||
2794 | ret = i915_gem_object_flush_fence(old); | |
29c5a587 CW |
2795 | if (ret) |
2796 | return ret; | |
2797 | ||
14415745 | 2798 | i915_gem_object_fence_lost(old); |
29c5a587 | 2799 | } |
14415745 | 2800 | } else |
a09ba7fa | 2801 | return 0; |
a09ba7fa | 2802 | |
14415745 | 2803 | i915_gem_object_update_fence(obj, reg, enable); |
5d82e3e6 | 2804 | obj->fence_dirty = false; |
14415745 | 2805 | |
9ce079e4 | 2806 | return 0; |
de151cf6 JB |
2807 | } |
2808 | ||
42d6ab48 CW |
2809 | static bool i915_gem_valid_gtt_space(struct drm_device *dev, |
2810 | struct drm_mm_node *gtt_space, | |
2811 | unsigned long cache_level) | |
2812 | { | |
2813 | struct drm_mm_node *other; | |
2814 | ||
2815 | /* On non-LLC machines we have to be careful when putting differing | |
2816 | * types of snoopable memory together to avoid the prefetcher | |
4239ca77 | 2817 | * crossing memory domains and dying. |
42d6ab48 CW |
2818 | */ |
2819 | if (HAS_LLC(dev)) | |
2820 | return true; | |
2821 | ||
2822 | if (gtt_space == NULL) | |
2823 | return true; | |
2824 | ||
2825 | if (list_empty(>t_space->node_list)) | |
2826 | return true; | |
2827 | ||
2828 | other = list_entry(gtt_space->node_list.prev, struct drm_mm_node, node_list); | |
2829 | if (other->allocated && !other->hole_follows && other->color != cache_level) | |
2830 | return false; | |
2831 | ||
2832 | other = list_entry(gtt_space->node_list.next, struct drm_mm_node, node_list); | |
2833 | if (other->allocated && !gtt_space->hole_follows && other->color != cache_level) | |
2834 | return false; | |
2835 | ||
2836 | return true; | |
2837 | } | |
2838 | ||
2839 | static void i915_gem_verify_gtt(struct drm_device *dev) | |
2840 | { | |
2841 | #if WATCH_GTT | |
2842 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2843 | struct drm_i915_gem_object *obj; | |
2844 | int err = 0; | |
2845 | ||
2846 | list_for_each_entry(obj, &dev_priv->mm.gtt_list, gtt_list) { | |
2847 | if (obj->gtt_space == NULL) { | |
2848 | printk(KERN_ERR "object found on GTT list with no space reserved\n"); | |
2849 | err++; | |
2850 | continue; | |
2851 | } | |
2852 | ||
2853 | if (obj->cache_level != obj->gtt_space->color) { | |
2854 | printk(KERN_ERR "object reserved space [%08lx, %08lx] with wrong color, cache_level=%x, color=%lx\n", | |
2855 | obj->gtt_space->start, | |
2856 | obj->gtt_space->start + obj->gtt_space->size, | |
2857 | obj->cache_level, | |
2858 | obj->gtt_space->color); | |
2859 | err++; | |
2860 | continue; | |
2861 | } | |
2862 | ||
2863 | if (!i915_gem_valid_gtt_space(dev, | |
2864 | obj->gtt_space, | |
2865 | obj->cache_level)) { | |
2866 | printk(KERN_ERR "invalid GTT space found at [%08lx, %08lx] - color=%x\n", | |
2867 | obj->gtt_space->start, | |
2868 | obj->gtt_space->start + obj->gtt_space->size, | |
2869 | obj->cache_level); | |
2870 | err++; | |
2871 | continue; | |
2872 | } | |
2873 | } | |
2874 | ||
2875 | WARN_ON(err); | |
2876 | #endif | |
2877 | } | |
2878 | ||
673a394b EA |
2879 | /** |
2880 | * Finds free space in the GTT aperture and binds the object there. | |
2881 | */ | |
2882 | static int | |
05394f39 | 2883 | i915_gem_object_bind_to_gtt(struct drm_i915_gem_object *obj, |
920afa77 | 2884 | unsigned alignment, |
86a1ee26 CW |
2885 | bool map_and_fenceable, |
2886 | bool nonblocking) | |
673a394b | 2887 | { |
05394f39 | 2888 | struct drm_device *dev = obj->base.dev; |
673a394b | 2889 | drm_i915_private_t *dev_priv = dev->dev_private; |
673a394b | 2890 | struct drm_mm_node *free_space; |
5e783301 | 2891 | u32 size, fence_size, fence_alignment, unfenced_alignment; |
75e9e915 | 2892 | bool mappable, fenceable; |
07f73f69 | 2893 | int ret; |
673a394b | 2894 | |
05394f39 | 2895 | if (obj->madv != I915_MADV_WILLNEED) { |
3ef94daa CW |
2896 | DRM_ERROR("Attempting to bind a purgeable object\n"); |
2897 | return -EINVAL; | |
2898 | } | |
2899 | ||
e28f8711 CW |
2900 | fence_size = i915_gem_get_gtt_size(dev, |
2901 | obj->base.size, | |
2902 | obj->tiling_mode); | |
2903 | fence_alignment = i915_gem_get_gtt_alignment(dev, | |
2904 | obj->base.size, | |
2905 | obj->tiling_mode); | |
2906 | unfenced_alignment = | |
2907 | i915_gem_get_unfenced_gtt_alignment(dev, | |
2908 | obj->base.size, | |
2909 | obj->tiling_mode); | |
a00b10c3 | 2910 | |
673a394b | 2911 | if (alignment == 0) |
5e783301 DV |
2912 | alignment = map_and_fenceable ? fence_alignment : |
2913 | unfenced_alignment; | |
75e9e915 | 2914 | if (map_and_fenceable && alignment & (fence_alignment - 1)) { |
673a394b EA |
2915 | DRM_ERROR("Invalid object alignment requested %u\n", alignment); |
2916 | return -EINVAL; | |
2917 | } | |
2918 | ||
05394f39 | 2919 | size = map_and_fenceable ? fence_size : obj->base.size; |
a00b10c3 | 2920 | |
654fc607 CW |
2921 | /* If the object is bigger than the entire aperture, reject it early |
2922 | * before evicting everything in a vain attempt to find space. | |
2923 | */ | |
05394f39 | 2924 | if (obj->base.size > |
75e9e915 | 2925 | (map_and_fenceable ? dev_priv->mm.gtt_mappable_end : dev_priv->mm.gtt_total)) { |
654fc607 CW |
2926 | DRM_ERROR("Attempting to bind an object larger than the aperture\n"); |
2927 | return -E2BIG; | |
2928 | } | |
2929 | ||
37e680a1 | 2930 | ret = i915_gem_object_get_pages(obj); |
6c085a72 CW |
2931 | if (ret) |
2932 | return ret; | |
2933 | ||
fbdda6fb CW |
2934 | i915_gem_object_pin_pages(obj); |
2935 | ||
673a394b | 2936 | search_free: |
75e9e915 | 2937 | if (map_and_fenceable) |
8742267a CW |
2938 | free_space = drm_mm_search_free_in_range_color(&dev_priv->mm.gtt_space, |
2939 | size, alignment, obj->cache_level, | |
2940 | 0, dev_priv->mm.gtt_mappable_end, | |
2941 | false); | |
920afa77 | 2942 | else |
42d6ab48 CW |
2943 | free_space = drm_mm_search_free_color(&dev_priv->mm.gtt_space, |
2944 | size, alignment, obj->cache_level, | |
2945 | false); | |
920afa77 DV |
2946 | |
2947 | if (free_space != NULL) { | |
75e9e915 | 2948 | if (map_and_fenceable) |
8742267a | 2949 | free_space = |
920afa77 | 2950 | drm_mm_get_block_range_generic(free_space, |
42d6ab48 | 2951 | size, alignment, obj->cache_level, |
6b9d89b4 | 2952 | 0, dev_priv->mm.gtt_mappable_end, |
42d6ab48 | 2953 | false); |
920afa77 | 2954 | else |
8742267a | 2955 | free_space = |
42d6ab48 CW |
2956 | drm_mm_get_block_generic(free_space, |
2957 | size, alignment, obj->cache_level, | |
2958 | false); | |
920afa77 | 2959 | } |
8742267a | 2960 | if (free_space == NULL) { |
75e9e915 | 2961 | ret = i915_gem_evict_something(dev, size, alignment, |
42d6ab48 | 2962 | obj->cache_level, |
86a1ee26 CW |
2963 | map_and_fenceable, |
2964 | nonblocking); | |
fbdda6fb CW |
2965 | if (ret) { |
2966 | i915_gem_object_unpin_pages(obj); | |
673a394b | 2967 | return ret; |
fbdda6fb | 2968 | } |
9731129c | 2969 | |
673a394b EA |
2970 | goto search_free; |
2971 | } | |
42d6ab48 | 2972 | if (WARN_ON(!i915_gem_valid_gtt_space(dev, |
8742267a | 2973 | free_space, |
42d6ab48 | 2974 | obj->cache_level))) { |
fbdda6fb | 2975 | i915_gem_object_unpin_pages(obj); |
8742267a | 2976 | drm_mm_put_block(free_space); |
42d6ab48 | 2977 | return -EINVAL; |
673a394b EA |
2978 | } |
2979 | ||
74163907 | 2980 | ret = i915_gem_gtt_prepare_object(obj); |
7c2e6fdf | 2981 | if (ret) { |
fbdda6fb | 2982 | i915_gem_object_unpin_pages(obj); |
8742267a | 2983 | drm_mm_put_block(free_space); |
6c085a72 | 2984 | return ret; |
673a394b | 2985 | } |
673a394b | 2986 | |
6c085a72 | 2987 | list_move_tail(&obj->gtt_list, &dev_priv->mm.bound_list); |
05394f39 | 2988 | list_add_tail(&obj->mm_list, &dev_priv->mm.inactive_list); |
bf1a1092 | 2989 | |
8742267a CW |
2990 | obj->gtt_space = free_space; |
2991 | obj->gtt_offset = free_space->start; | |
1c5d22f7 | 2992 | |
75e9e915 | 2993 | fenceable = |
8742267a CW |
2994 | free_space->size == fence_size && |
2995 | (free_space->start & (fence_alignment - 1)) == 0; | |
a00b10c3 | 2996 | |
75e9e915 | 2997 | mappable = |
05394f39 | 2998 | obj->gtt_offset + obj->base.size <= dev_priv->mm.gtt_mappable_end; |
a00b10c3 | 2999 | |
05394f39 | 3000 | obj->map_and_fenceable = mappable && fenceable; |
75e9e915 | 3001 | |
fbdda6fb | 3002 | i915_gem_object_unpin_pages(obj); |
db53a302 | 3003 | trace_i915_gem_object_bind(obj, map_and_fenceable); |
42d6ab48 | 3004 | i915_gem_verify_gtt(dev); |
673a394b EA |
3005 | return 0; |
3006 | } | |
3007 | ||
3008 | void | |
05394f39 | 3009 | i915_gem_clflush_object(struct drm_i915_gem_object *obj) |
673a394b | 3010 | { |
673a394b EA |
3011 | /* If we don't have a page list set up, then we're not pinned |
3012 | * to GPU, and we can ignore the cache flush because it'll happen | |
3013 | * again at bind time. | |
3014 | */ | |
05394f39 | 3015 | if (obj->pages == NULL) |
673a394b EA |
3016 | return; |
3017 | ||
9c23f7fc CW |
3018 | /* If the GPU is snooping the contents of the CPU cache, |
3019 | * we do not need to manually clear the CPU cache lines. However, | |
3020 | * the caches are only snooped when the render cache is | |
3021 | * flushed/invalidated. As we always have to emit invalidations | |
3022 | * and flushes when moving into and out of the RENDER domain, correct | |
3023 | * snooping behaviour occurs naturally as the result of our domain | |
3024 | * tracking. | |
3025 | */ | |
3026 | if (obj->cache_level != I915_CACHE_NONE) | |
3027 | return; | |
3028 | ||
1c5d22f7 | 3029 | trace_i915_gem_object_clflush(obj); |
cfa16a0d | 3030 | |
9da3da66 | 3031 | drm_clflush_sg(obj->pages); |
e47c68e9 EA |
3032 | } |
3033 | ||
3034 | /** Flushes the GTT write domain for the object if it's dirty. */ | |
3035 | static void | |
05394f39 | 3036 | i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object *obj) |
e47c68e9 | 3037 | { |
1c5d22f7 CW |
3038 | uint32_t old_write_domain; |
3039 | ||
05394f39 | 3040 | if (obj->base.write_domain != I915_GEM_DOMAIN_GTT) |
e47c68e9 EA |
3041 | return; |
3042 | ||
63256ec5 | 3043 | /* No actual flushing is required for the GTT write domain. Writes |
e47c68e9 EA |
3044 | * to it immediately go to main memory as far as we know, so there's |
3045 | * no chipset flush. It also doesn't land in render cache. | |
63256ec5 CW |
3046 | * |
3047 | * However, we do have to enforce the order so that all writes through | |
3048 | * the GTT land before any writes to the device, such as updates to | |
3049 | * the GATT itself. | |
e47c68e9 | 3050 | */ |
63256ec5 CW |
3051 | wmb(); |
3052 | ||
05394f39 CW |
3053 | old_write_domain = obj->base.write_domain; |
3054 | obj->base.write_domain = 0; | |
1c5d22f7 CW |
3055 | |
3056 | trace_i915_gem_object_change_domain(obj, | |
05394f39 | 3057 | obj->base.read_domains, |
1c5d22f7 | 3058 | old_write_domain); |
e47c68e9 EA |
3059 | } |
3060 | ||
3061 | /** Flushes the CPU write domain for the object if it's dirty. */ | |
3062 | static void | |
05394f39 | 3063 | i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object *obj) |
e47c68e9 | 3064 | { |
1c5d22f7 | 3065 | uint32_t old_write_domain; |
e47c68e9 | 3066 | |
05394f39 | 3067 | if (obj->base.write_domain != I915_GEM_DOMAIN_CPU) |
e47c68e9 EA |
3068 | return; |
3069 | ||
3070 | i915_gem_clflush_object(obj); | |
e76e9aeb | 3071 | i915_gem_chipset_flush(obj->base.dev); |
05394f39 CW |
3072 | old_write_domain = obj->base.write_domain; |
3073 | obj->base.write_domain = 0; | |
1c5d22f7 CW |
3074 | |
3075 | trace_i915_gem_object_change_domain(obj, | |
05394f39 | 3076 | obj->base.read_domains, |
1c5d22f7 | 3077 | old_write_domain); |
e47c68e9 EA |
3078 | } |
3079 | ||
2ef7eeaa EA |
3080 | /** |
3081 | * Moves a single object to the GTT read, and possibly write domain. | |
3082 | * | |
3083 | * This function returns when the move is complete, including waiting on | |
3084 | * flushes to occur. | |
3085 | */ | |
79e53945 | 3086 | int |
2021746e | 3087 | i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write) |
2ef7eeaa | 3088 | { |
8325a09d | 3089 | drm_i915_private_t *dev_priv = obj->base.dev->dev_private; |
1c5d22f7 | 3090 | uint32_t old_write_domain, old_read_domains; |
e47c68e9 | 3091 | int ret; |
2ef7eeaa | 3092 | |
02354392 | 3093 | /* Not valid to be called on unbound objects. */ |
05394f39 | 3094 | if (obj->gtt_space == NULL) |
02354392 EA |
3095 | return -EINVAL; |
3096 | ||
8d7e3de1 CW |
3097 | if (obj->base.write_domain == I915_GEM_DOMAIN_GTT) |
3098 | return 0; | |
3099 | ||
0201f1ec | 3100 | ret = i915_gem_object_wait_rendering(obj, !write); |
88241785 CW |
3101 | if (ret) |
3102 | return ret; | |
3103 | ||
7213342d | 3104 | i915_gem_object_flush_cpu_write_domain(obj); |
1c5d22f7 | 3105 | |
05394f39 CW |
3106 | old_write_domain = obj->base.write_domain; |
3107 | old_read_domains = obj->base.read_domains; | |
1c5d22f7 | 3108 | |
e47c68e9 EA |
3109 | /* It should now be out of any other write domains, and we can update |
3110 | * the domain values for our changes. | |
3111 | */ | |
05394f39 CW |
3112 | BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) != 0); |
3113 | obj->base.read_domains |= I915_GEM_DOMAIN_GTT; | |
e47c68e9 | 3114 | if (write) { |
05394f39 CW |
3115 | obj->base.read_domains = I915_GEM_DOMAIN_GTT; |
3116 | obj->base.write_domain = I915_GEM_DOMAIN_GTT; | |
3117 | obj->dirty = 1; | |
2ef7eeaa EA |
3118 | } |
3119 | ||
1c5d22f7 CW |
3120 | trace_i915_gem_object_change_domain(obj, |
3121 | old_read_domains, | |
3122 | old_write_domain); | |
3123 | ||
8325a09d CW |
3124 | /* And bump the LRU for this access */ |
3125 | if (i915_gem_object_is_inactive(obj)) | |
3126 | list_move_tail(&obj->mm_list, &dev_priv->mm.inactive_list); | |
3127 | ||
e47c68e9 EA |
3128 | return 0; |
3129 | } | |
3130 | ||
e4ffd173 CW |
3131 | int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj, |
3132 | enum i915_cache_level cache_level) | |
3133 | { | |
7bddb01f DV |
3134 | struct drm_device *dev = obj->base.dev; |
3135 | drm_i915_private_t *dev_priv = dev->dev_private; | |
e4ffd173 CW |
3136 | int ret; |
3137 | ||
3138 | if (obj->cache_level == cache_level) | |
3139 | return 0; | |
3140 | ||
3141 | if (obj->pin_count) { | |
3142 | DRM_DEBUG("can not change the cache level of pinned objects\n"); | |
3143 | return -EBUSY; | |
3144 | } | |
3145 | ||
42d6ab48 CW |
3146 | if (!i915_gem_valid_gtt_space(dev, obj->gtt_space, cache_level)) { |
3147 | ret = i915_gem_object_unbind(obj); | |
3148 | if (ret) | |
3149 | return ret; | |
3150 | } | |
3151 | ||
e4ffd173 CW |
3152 | if (obj->gtt_space) { |
3153 | ret = i915_gem_object_finish_gpu(obj); | |
3154 | if (ret) | |
3155 | return ret; | |
3156 | ||
3157 | i915_gem_object_finish_gtt(obj); | |
3158 | ||
3159 | /* Before SandyBridge, you could not use tiling or fence | |
3160 | * registers with snooped memory, so relinquish any fences | |
3161 | * currently pointing to our region in the aperture. | |
3162 | */ | |
42d6ab48 | 3163 | if (INTEL_INFO(dev)->gen < 6) { |
e4ffd173 CW |
3164 | ret = i915_gem_object_put_fence(obj); |
3165 | if (ret) | |
3166 | return ret; | |
3167 | } | |
3168 | ||
74898d7e DV |
3169 | if (obj->has_global_gtt_mapping) |
3170 | i915_gem_gtt_bind_object(obj, cache_level); | |
7bddb01f DV |
3171 | if (obj->has_aliasing_ppgtt_mapping) |
3172 | i915_ppgtt_bind_object(dev_priv->mm.aliasing_ppgtt, | |
3173 | obj, cache_level); | |
42d6ab48 CW |
3174 | |
3175 | obj->gtt_space->color = cache_level; | |
e4ffd173 CW |
3176 | } |
3177 | ||
3178 | if (cache_level == I915_CACHE_NONE) { | |
3179 | u32 old_read_domains, old_write_domain; | |
3180 | ||
3181 | /* If we're coming from LLC cached, then we haven't | |
3182 | * actually been tracking whether the data is in the | |
3183 | * CPU cache or not, since we only allow one bit set | |
3184 | * in obj->write_domain and have been skipping the clflushes. | |
3185 | * Just set it to the CPU cache for now. | |
3186 | */ | |
3187 | WARN_ON(obj->base.write_domain & ~I915_GEM_DOMAIN_CPU); | |
3188 | WARN_ON(obj->base.read_domains & ~I915_GEM_DOMAIN_CPU); | |
3189 | ||
3190 | old_read_domains = obj->base.read_domains; | |
3191 | old_write_domain = obj->base.write_domain; | |
3192 | ||
3193 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; | |
3194 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; | |
3195 | ||
3196 | trace_i915_gem_object_change_domain(obj, | |
3197 | old_read_domains, | |
3198 | old_write_domain); | |
3199 | } | |
3200 | ||
3201 | obj->cache_level = cache_level; | |
42d6ab48 | 3202 | i915_gem_verify_gtt(dev); |
e4ffd173 CW |
3203 | return 0; |
3204 | } | |
3205 | ||
199adf40 BW |
3206 | int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data, |
3207 | struct drm_file *file) | |
e6994aee | 3208 | { |
199adf40 | 3209 | struct drm_i915_gem_caching *args = data; |
e6994aee CW |
3210 | struct drm_i915_gem_object *obj; |
3211 | int ret; | |
3212 | ||
3213 | ret = i915_mutex_lock_interruptible(dev); | |
3214 | if (ret) | |
3215 | return ret; | |
3216 | ||
3217 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); | |
3218 | if (&obj->base == NULL) { | |
3219 | ret = -ENOENT; | |
3220 | goto unlock; | |
3221 | } | |
3222 | ||
199adf40 | 3223 | args->caching = obj->cache_level != I915_CACHE_NONE; |
e6994aee CW |
3224 | |
3225 | drm_gem_object_unreference(&obj->base); | |
3226 | unlock: | |
3227 | mutex_unlock(&dev->struct_mutex); | |
3228 | return ret; | |
3229 | } | |
3230 | ||
199adf40 BW |
3231 | int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data, |
3232 | struct drm_file *file) | |
e6994aee | 3233 | { |
199adf40 | 3234 | struct drm_i915_gem_caching *args = data; |
e6994aee CW |
3235 | struct drm_i915_gem_object *obj; |
3236 | enum i915_cache_level level; | |
3237 | int ret; | |
3238 | ||
199adf40 BW |
3239 | switch (args->caching) { |
3240 | case I915_CACHING_NONE: | |
e6994aee CW |
3241 | level = I915_CACHE_NONE; |
3242 | break; | |
199adf40 | 3243 | case I915_CACHING_CACHED: |
e6994aee CW |
3244 | level = I915_CACHE_LLC; |
3245 | break; | |
3246 | default: | |
3247 | return -EINVAL; | |
3248 | } | |
3249 | ||
3bc2913e BW |
3250 | ret = i915_mutex_lock_interruptible(dev); |
3251 | if (ret) | |
3252 | return ret; | |
3253 | ||
e6994aee CW |
3254 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
3255 | if (&obj->base == NULL) { | |
3256 | ret = -ENOENT; | |
3257 | goto unlock; | |
3258 | } | |
3259 | ||
3260 | ret = i915_gem_object_set_cache_level(obj, level); | |
3261 | ||
3262 | drm_gem_object_unreference(&obj->base); | |
3263 | unlock: | |
3264 | mutex_unlock(&dev->struct_mutex); | |
3265 | return ret; | |
3266 | } | |
3267 | ||
b9241ea3 | 3268 | /* |
2da3b9b9 CW |
3269 | * Prepare buffer for display plane (scanout, cursors, etc). |
3270 | * Can be called from an uninterruptible phase (modesetting) and allows | |
3271 | * any flushes to be pipelined (for pageflips). | |
b9241ea3 ZW |
3272 | */ |
3273 | int | |
2da3b9b9 CW |
3274 | i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj, |
3275 | u32 alignment, | |
919926ae | 3276 | struct intel_ring_buffer *pipelined) |
b9241ea3 | 3277 | { |
2da3b9b9 | 3278 | u32 old_read_domains, old_write_domain; |
b9241ea3 ZW |
3279 | int ret; |
3280 | ||
0be73284 | 3281 | if (pipelined != obj->ring) { |
2911a35b BW |
3282 | ret = i915_gem_object_sync(obj, pipelined); |
3283 | if (ret) | |
b9241ea3 ZW |
3284 | return ret; |
3285 | } | |
3286 | ||
a7ef0640 EA |
3287 | /* The display engine is not coherent with the LLC cache on gen6. As |
3288 | * a result, we make sure that the pinning that is about to occur is | |
3289 | * done with uncached PTEs. This is lowest common denominator for all | |
3290 | * chipsets. | |
3291 | * | |
3292 | * However for gen6+, we could do better by using the GFDT bit instead | |
3293 | * of uncaching, which would allow us to flush all the LLC-cached data | |
3294 | * with that bit in the PTE to main memory with just one PIPE_CONTROL. | |
3295 | */ | |
3296 | ret = i915_gem_object_set_cache_level(obj, I915_CACHE_NONE); | |
3297 | if (ret) | |
3298 | return ret; | |
3299 | ||
2da3b9b9 CW |
3300 | /* As the user may map the buffer once pinned in the display plane |
3301 | * (e.g. libkms for the bootup splash), we have to ensure that we | |
3302 | * always use map_and_fenceable for all scanout buffers. | |
3303 | */ | |
86a1ee26 | 3304 | ret = i915_gem_object_pin(obj, alignment, true, false); |
2da3b9b9 CW |
3305 | if (ret) |
3306 | return ret; | |
3307 | ||
b118c1e3 CW |
3308 | i915_gem_object_flush_cpu_write_domain(obj); |
3309 | ||
2da3b9b9 | 3310 | old_write_domain = obj->base.write_domain; |
05394f39 | 3311 | old_read_domains = obj->base.read_domains; |
2da3b9b9 CW |
3312 | |
3313 | /* It should now be out of any other write domains, and we can update | |
3314 | * the domain values for our changes. | |
3315 | */ | |
e5f1d962 | 3316 | obj->base.write_domain = 0; |
05394f39 | 3317 | obj->base.read_domains |= I915_GEM_DOMAIN_GTT; |
b9241ea3 ZW |
3318 | |
3319 | trace_i915_gem_object_change_domain(obj, | |
3320 | old_read_domains, | |
2da3b9b9 | 3321 | old_write_domain); |
b9241ea3 ZW |
3322 | |
3323 | return 0; | |
3324 | } | |
3325 | ||
85345517 | 3326 | int |
a8198eea | 3327 | i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj) |
85345517 | 3328 | { |
88241785 CW |
3329 | int ret; |
3330 | ||
a8198eea | 3331 | if ((obj->base.read_domains & I915_GEM_GPU_DOMAINS) == 0) |
85345517 CW |
3332 | return 0; |
3333 | ||
0201f1ec | 3334 | ret = i915_gem_object_wait_rendering(obj, false); |
c501ae7f CW |
3335 | if (ret) |
3336 | return ret; | |
3337 | ||
a8198eea CW |
3338 | /* Ensure that we invalidate the GPU's caches and TLBs. */ |
3339 | obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS; | |
c501ae7f | 3340 | return 0; |
85345517 CW |
3341 | } |
3342 | ||
e47c68e9 EA |
3343 | /** |
3344 | * Moves a single object to the CPU read, and possibly write domain. | |
3345 | * | |
3346 | * This function returns when the move is complete, including waiting on | |
3347 | * flushes to occur. | |
3348 | */ | |
dabdfe02 | 3349 | int |
919926ae | 3350 | i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write) |
e47c68e9 | 3351 | { |
1c5d22f7 | 3352 | uint32_t old_write_domain, old_read_domains; |
e47c68e9 EA |
3353 | int ret; |
3354 | ||
8d7e3de1 CW |
3355 | if (obj->base.write_domain == I915_GEM_DOMAIN_CPU) |
3356 | return 0; | |
3357 | ||
0201f1ec | 3358 | ret = i915_gem_object_wait_rendering(obj, !write); |
88241785 CW |
3359 | if (ret) |
3360 | return ret; | |
3361 | ||
e47c68e9 | 3362 | i915_gem_object_flush_gtt_write_domain(obj); |
2ef7eeaa | 3363 | |
05394f39 CW |
3364 | old_write_domain = obj->base.write_domain; |
3365 | old_read_domains = obj->base.read_domains; | |
1c5d22f7 | 3366 | |
e47c68e9 | 3367 | /* Flush the CPU cache if it's still invalid. */ |
05394f39 | 3368 | if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) { |
2ef7eeaa | 3369 | i915_gem_clflush_object(obj); |
2ef7eeaa | 3370 | |
05394f39 | 3371 | obj->base.read_domains |= I915_GEM_DOMAIN_CPU; |
2ef7eeaa EA |
3372 | } |
3373 | ||
3374 | /* It should now be out of any other write domains, and we can update | |
3375 | * the domain values for our changes. | |
3376 | */ | |
05394f39 | 3377 | BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_CPU) != 0); |
e47c68e9 EA |
3378 | |
3379 | /* If we're writing through the CPU, then the GPU read domains will | |
3380 | * need to be invalidated at next use. | |
3381 | */ | |
3382 | if (write) { | |
05394f39 CW |
3383 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; |
3384 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; | |
e47c68e9 | 3385 | } |
2ef7eeaa | 3386 | |
1c5d22f7 CW |
3387 | trace_i915_gem_object_change_domain(obj, |
3388 | old_read_domains, | |
3389 | old_write_domain); | |
3390 | ||
2ef7eeaa EA |
3391 | return 0; |
3392 | } | |
3393 | ||
673a394b EA |
3394 | /* Throttle our rendering by waiting until the ring has completed our requests |
3395 | * emitted over 20 msec ago. | |
3396 | * | |
b962442e EA |
3397 | * Note that if we were to use the current jiffies each time around the loop, |
3398 | * we wouldn't escape the function with any frames outstanding if the time to | |
3399 | * render a frame was over 20ms. | |
3400 | * | |
673a394b EA |
3401 | * This should get us reasonable parallelism between CPU and GPU but also |
3402 | * relatively low latency when blocking on a particular request to finish. | |
3403 | */ | |
40a5f0de | 3404 | static int |
f787a5f5 | 3405 | i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file) |
40a5f0de | 3406 | { |
f787a5f5 CW |
3407 | struct drm_i915_private *dev_priv = dev->dev_private; |
3408 | struct drm_i915_file_private *file_priv = file->driver_priv; | |
b962442e | 3409 | unsigned long recent_enough = jiffies - msecs_to_jiffies(20); |
f787a5f5 CW |
3410 | struct drm_i915_gem_request *request; |
3411 | struct intel_ring_buffer *ring = NULL; | |
3412 | u32 seqno = 0; | |
3413 | int ret; | |
93533c29 | 3414 | |
e110e8d6 CW |
3415 | if (atomic_read(&dev_priv->mm.wedged)) |
3416 | return -EIO; | |
3417 | ||
1c25595f | 3418 | spin_lock(&file_priv->mm.lock); |
f787a5f5 | 3419 | list_for_each_entry(request, &file_priv->mm.request_list, client_list) { |
b962442e EA |
3420 | if (time_after_eq(request->emitted_jiffies, recent_enough)) |
3421 | break; | |
40a5f0de | 3422 | |
f787a5f5 CW |
3423 | ring = request->ring; |
3424 | seqno = request->seqno; | |
b962442e | 3425 | } |
1c25595f | 3426 | spin_unlock(&file_priv->mm.lock); |
40a5f0de | 3427 | |
f787a5f5 CW |
3428 | if (seqno == 0) |
3429 | return 0; | |
2bc43b5c | 3430 | |
5c81fe85 | 3431 | ret = __wait_seqno(ring, seqno, true, NULL); |
f787a5f5 CW |
3432 | if (ret == 0) |
3433 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, 0); | |
40a5f0de EA |
3434 | |
3435 | return ret; | |
3436 | } | |
3437 | ||
673a394b | 3438 | int |
05394f39 CW |
3439 | i915_gem_object_pin(struct drm_i915_gem_object *obj, |
3440 | uint32_t alignment, | |
86a1ee26 CW |
3441 | bool map_and_fenceable, |
3442 | bool nonblocking) | |
673a394b | 3443 | { |
673a394b EA |
3444 | int ret; |
3445 | ||
7e81a42e CW |
3446 | if (WARN_ON(obj->pin_count == DRM_I915_GEM_OBJECT_MAX_PIN_COUNT)) |
3447 | return -EBUSY; | |
ac0c6b5a | 3448 | |
05394f39 CW |
3449 | if (obj->gtt_space != NULL) { |
3450 | if ((alignment && obj->gtt_offset & (alignment - 1)) || | |
3451 | (map_and_fenceable && !obj->map_and_fenceable)) { | |
3452 | WARN(obj->pin_count, | |
ae7d49d8 | 3453 | "bo is already pinned with incorrect alignment:" |
75e9e915 DV |
3454 | " offset=%x, req.alignment=%x, req.map_and_fenceable=%d," |
3455 | " obj->map_and_fenceable=%d\n", | |
05394f39 | 3456 | obj->gtt_offset, alignment, |
75e9e915 | 3457 | map_and_fenceable, |
05394f39 | 3458 | obj->map_and_fenceable); |
ac0c6b5a CW |
3459 | ret = i915_gem_object_unbind(obj); |
3460 | if (ret) | |
3461 | return ret; | |
3462 | } | |
3463 | } | |
3464 | ||
05394f39 | 3465 | if (obj->gtt_space == NULL) { |
8742267a CW |
3466 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
3467 | ||
a00b10c3 | 3468 | ret = i915_gem_object_bind_to_gtt(obj, alignment, |
86a1ee26 CW |
3469 | map_and_fenceable, |
3470 | nonblocking); | |
9731129c | 3471 | if (ret) |
673a394b | 3472 | return ret; |
8742267a CW |
3473 | |
3474 | if (!dev_priv->mm.aliasing_ppgtt) | |
3475 | i915_gem_gtt_bind_object(obj, obj->cache_level); | |
22c344e9 | 3476 | } |
76446cac | 3477 | |
74898d7e DV |
3478 | if (!obj->has_global_gtt_mapping && map_and_fenceable) |
3479 | i915_gem_gtt_bind_object(obj, obj->cache_level); | |
3480 | ||
1b50247a | 3481 | obj->pin_count++; |
6299f992 | 3482 | obj->pin_mappable |= map_and_fenceable; |
673a394b EA |
3483 | |
3484 | return 0; | |
3485 | } | |
3486 | ||
3487 | void | |
05394f39 | 3488 | i915_gem_object_unpin(struct drm_i915_gem_object *obj) |
673a394b | 3489 | { |
05394f39 CW |
3490 | BUG_ON(obj->pin_count == 0); |
3491 | BUG_ON(obj->gtt_space == NULL); | |
673a394b | 3492 | |
1b50247a | 3493 | if (--obj->pin_count == 0) |
6299f992 | 3494 | obj->pin_mappable = false; |
673a394b EA |
3495 | } |
3496 | ||
3497 | int | |
3498 | i915_gem_pin_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 3499 | struct drm_file *file) |
673a394b EA |
3500 | { |
3501 | struct drm_i915_gem_pin *args = data; | |
05394f39 | 3502 | struct drm_i915_gem_object *obj; |
673a394b EA |
3503 | int ret; |
3504 | ||
1d7cfea1 CW |
3505 | ret = i915_mutex_lock_interruptible(dev); |
3506 | if (ret) | |
3507 | return ret; | |
673a394b | 3508 | |
05394f39 | 3509 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 3510 | if (&obj->base == NULL) { |
1d7cfea1 CW |
3511 | ret = -ENOENT; |
3512 | goto unlock; | |
673a394b | 3513 | } |
673a394b | 3514 | |
05394f39 | 3515 | if (obj->madv != I915_MADV_WILLNEED) { |
bb6baf76 | 3516 | DRM_ERROR("Attempting to pin a purgeable buffer\n"); |
1d7cfea1 CW |
3517 | ret = -EINVAL; |
3518 | goto out; | |
3ef94daa CW |
3519 | } |
3520 | ||
05394f39 | 3521 | if (obj->pin_filp != NULL && obj->pin_filp != file) { |
79e53945 JB |
3522 | DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n", |
3523 | args->handle); | |
1d7cfea1 CW |
3524 | ret = -EINVAL; |
3525 | goto out; | |
79e53945 JB |
3526 | } |
3527 | ||
05394f39 CW |
3528 | obj->user_pin_count++; |
3529 | obj->pin_filp = file; | |
3530 | if (obj->user_pin_count == 1) { | |
86a1ee26 | 3531 | ret = i915_gem_object_pin(obj, args->alignment, true, false); |
1d7cfea1 CW |
3532 | if (ret) |
3533 | goto out; | |
673a394b EA |
3534 | } |
3535 | ||
3536 | /* XXX - flush the CPU caches for pinned objects | |
3537 | * as the X server doesn't manage domains yet | |
3538 | */ | |
e47c68e9 | 3539 | i915_gem_object_flush_cpu_write_domain(obj); |
05394f39 | 3540 | args->offset = obj->gtt_offset; |
1d7cfea1 | 3541 | out: |
05394f39 | 3542 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 3543 | unlock: |
673a394b | 3544 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 3545 | return ret; |
673a394b EA |
3546 | } |
3547 | ||
3548 | int | |
3549 | i915_gem_unpin_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 3550 | struct drm_file *file) |
673a394b EA |
3551 | { |
3552 | struct drm_i915_gem_pin *args = data; | |
05394f39 | 3553 | struct drm_i915_gem_object *obj; |
76c1dec1 | 3554 | int ret; |
673a394b | 3555 | |
1d7cfea1 CW |
3556 | ret = i915_mutex_lock_interruptible(dev); |
3557 | if (ret) | |
3558 | return ret; | |
673a394b | 3559 | |
05394f39 | 3560 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 3561 | if (&obj->base == NULL) { |
1d7cfea1 CW |
3562 | ret = -ENOENT; |
3563 | goto unlock; | |
673a394b | 3564 | } |
76c1dec1 | 3565 | |
05394f39 | 3566 | if (obj->pin_filp != file) { |
79e53945 JB |
3567 | DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n", |
3568 | args->handle); | |
1d7cfea1 CW |
3569 | ret = -EINVAL; |
3570 | goto out; | |
79e53945 | 3571 | } |
05394f39 CW |
3572 | obj->user_pin_count--; |
3573 | if (obj->user_pin_count == 0) { | |
3574 | obj->pin_filp = NULL; | |
79e53945 JB |
3575 | i915_gem_object_unpin(obj); |
3576 | } | |
673a394b | 3577 | |
1d7cfea1 | 3578 | out: |
05394f39 | 3579 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 3580 | unlock: |
673a394b | 3581 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 3582 | return ret; |
673a394b EA |
3583 | } |
3584 | ||
3585 | int | |
3586 | i915_gem_busy_ioctl(struct drm_device *dev, void *data, | |
05394f39 | 3587 | struct drm_file *file) |
673a394b EA |
3588 | { |
3589 | struct drm_i915_gem_busy *args = data; | |
05394f39 | 3590 | struct drm_i915_gem_object *obj; |
30dbf0c0 CW |
3591 | int ret; |
3592 | ||
76c1dec1 | 3593 | ret = i915_mutex_lock_interruptible(dev); |
1d7cfea1 | 3594 | if (ret) |
76c1dec1 | 3595 | return ret; |
673a394b | 3596 | |
05394f39 | 3597 | obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle)); |
c8725226 | 3598 | if (&obj->base == NULL) { |
1d7cfea1 CW |
3599 | ret = -ENOENT; |
3600 | goto unlock; | |
673a394b | 3601 | } |
d1b851fc | 3602 | |
0be555b6 CW |
3603 | /* Count all active objects as busy, even if they are currently not used |
3604 | * by the gpu. Users of this interface expect objects to eventually | |
3605 | * become non-busy without any further actions, therefore emit any | |
3606 | * necessary flushes here. | |
c4de0a5d | 3607 | */ |
30dfebf3 | 3608 | ret = i915_gem_object_flush_active(obj); |
0be555b6 | 3609 | |
30dfebf3 | 3610 | args->busy = obj->active; |
e9808edd CW |
3611 | if (obj->ring) { |
3612 | BUILD_BUG_ON(I915_NUM_RINGS > 16); | |
3613 | args->busy |= intel_ring_flag(obj->ring) << 16; | |
3614 | } | |
673a394b | 3615 | |
05394f39 | 3616 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 3617 | unlock: |
673a394b | 3618 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 3619 | return ret; |
673a394b EA |
3620 | } |
3621 | ||
3622 | int | |
3623 | i915_gem_throttle_ioctl(struct drm_device *dev, void *data, | |
3624 | struct drm_file *file_priv) | |
3625 | { | |
0206e353 | 3626 | return i915_gem_ring_throttle(dev, file_priv); |
673a394b EA |
3627 | } |
3628 | ||
3ef94daa CW |
3629 | int |
3630 | i915_gem_madvise_ioctl(struct drm_device *dev, void *data, | |
3631 | struct drm_file *file_priv) | |
3632 | { | |
3633 | struct drm_i915_gem_madvise *args = data; | |
05394f39 | 3634 | struct drm_i915_gem_object *obj; |
76c1dec1 | 3635 | int ret; |
3ef94daa CW |
3636 | |
3637 | switch (args->madv) { | |
3638 | case I915_MADV_DONTNEED: | |
3639 | case I915_MADV_WILLNEED: | |
3640 | break; | |
3641 | default: | |
3642 | return -EINVAL; | |
3643 | } | |
3644 | ||
1d7cfea1 CW |
3645 | ret = i915_mutex_lock_interruptible(dev); |
3646 | if (ret) | |
3647 | return ret; | |
3648 | ||
05394f39 | 3649 | obj = to_intel_bo(drm_gem_object_lookup(dev, file_priv, args->handle)); |
c8725226 | 3650 | if (&obj->base == NULL) { |
1d7cfea1 CW |
3651 | ret = -ENOENT; |
3652 | goto unlock; | |
3ef94daa | 3653 | } |
3ef94daa | 3654 | |
05394f39 | 3655 | if (obj->pin_count) { |
1d7cfea1 CW |
3656 | ret = -EINVAL; |
3657 | goto out; | |
3ef94daa CW |
3658 | } |
3659 | ||
05394f39 CW |
3660 | if (obj->madv != __I915_MADV_PURGED) |
3661 | obj->madv = args->madv; | |
3ef94daa | 3662 | |
6c085a72 CW |
3663 | /* if the object is no longer attached, discard its backing storage */ |
3664 | if (i915_gem_object_is_purgeable(obj) && obj->pages == NULL) | |
2d7ef395 CW |
3665 | i915_gem_object_truncate(obj); |
3666 | ||
05394f39 | 3667 | args->retained = obj->madv != __I915_MADV_PURGED; |
bb6baf76 | 3668 | |
1d7cfea1 | 3669 | out: |
05394f39 | 3670 | drm_gem_object_unreference(&obj->base); |
1d7cfea1 | 3671 | unlock: |
3ef94daa | 3672 | mutex_unlock(&dev->struct_mutex); |
1d7cfea1 | 3673 | return ret; |
3ef94daa CW |
3674 | } |
3675 | ||
37e680a1 CW |
3676 | void i915_gem_object_init(struct drm_i915_gem_object *obj, |
3677 | const struct drm_i915_gem_object_ops *ops) | |
0327d6ba | 3678 | { |
0327d6ba CW |
3679 | INIT_LIST_HEAD(&obj->mm_list); |
3680 | INIT_LIST_HEAD(&obj->gtt_list); | |
3681 | INIT_LIST_HEAD(&obj->ring_list); | |
3682 | INIT_LIST_HEAD(&obj->exec_list); | |
3683 | ||
37e680a1 CW |
3684 | obj->ops = ops; |
3685 | ||
0327d6ba CW |
3686 | obj->fence_reg = I915_FENCE_REG_NONE; |
3687 | obj->madv = I915_MADV_WILLNEED; | |
3688 | /* Avoid an unnecessary call to unbind on the first bind. */ | |
3689 | obj->map_and_fenceable = true; | |
3690 | ||
3691 | i915_gem_info_add_obj(obj->base.dev->dev_private, obj->base.size); | |
3692 | } | |
3693 | ||
37e680a1 CW |
3694 | static const struct drm_i915_gem_object_ops i915_gem_object_ops = { |
3695 | .get_pages = i915_gem_object_get_pages_gtt, | |
3696 | .put_pages = i915_gem_object_put_pages_gtt, | |
3697 | }; | |
3698 | ||
05394f39 CW |
3699 | struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev, |
3700 | size_t size) | |
ac52bc56 | 3701 | { |
c397b908 | 3702 | struct drm_i915_gem_object *obj; |
5949eac4 | 3703 | struct address_space *mapping; |
1a240d4d | 3704 | gfp_t mask; |
ac52bc56 | 3705 | |
42dcedd4 | 3706 | obj = i915_gem_object_alloc(dev); |
c397b908 DV |
3707 | if (obj == NULL) |
3708 | return NULL; | |
673a394b | 3709 | |
c397b908 | 3710 | if (drm_gem_object_init(dev, &obj->base, size) != 0) { |
42dcedd4 | 3711 | i915_gem_object_free(obj); |
c397b908 DV |
3712 | return NULL; |
3713 | } | |
673a394b | 3714 | |
bed1ea95 CW |
3715 | mask = GFP_HIGHUSER | __GFP_RECLAIMABLE; |
3716 | if (IS_CRESTLINE(dev) || IS_BROADWATER(dev)) { | |
3717 | /* 965gm cannot relocate objects above 4GiB. */ | |
3718 | mask &= ~__GFP_HIGHMEM; | |
3719 | mask |= __GFP_DMA32; | |
3720 | } | |
3721 | ||
5949eac4 | 3722 | mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping; |
bed1ea95 | 3723 | mapping_set_gfp_mask(mapping, mask); |
5949eac4 | 3724 | |
37e680a1 | 3725 | i915_gem_object_init(obj, &i915_gem_object_ops); |
73aa808f | 3726 | |
c397b908 DV |
3727 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; |
3728 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; | |
673a394b | 3729 | |
3d29b842 ED |
3730 | if (HAS_LLC(dev)) { |
3731 | /* On some devices, we can have the GPU use the LLC (the CPU | |
a1871112 EA |
3732 | * cache) for about a 10% performance improvement |
3733 | * compared to uncached. Graphics requests other than | |
3734 | * display scanout are coherent with the CPU in | |
3735 | * accessing this cache. This means in this mode we | |
3736 | * don't need to clflush on the CPU side, and on the | |
3737 | * GPU side we only need to flush internal caches to | |
3738 | * get data visible to the CPU. | |
3739 | * | |
3740 | * However, we maintain the display planes as UC, and so | |
3741 | * need to rebind when first used as such. | |
3742 | */ | |
3743 | obj->cache_level = I915_CACHE_LLC; | |
3744 | } else | |
3745 | obj->cache_level = I915_CACHE_NONE; | |
3746 | ||
05394f39 | 3747 | return obj; |
c397b908 DV |
3748 | } |
3749 | ||
3750 | int i915_gem_init_object(struct drm_gem_object *obj) | |
3751 | { | |
3752 | BUG(); | |
de151cf6 | 3753 | |
673a394b EA |
3754 | return 0; |
3755 | } | |
3756 | ||
1488fc08 | 3757 | void i915_gem_free_object(struct drm_gem_object *gem_obj) |
673a394b | 3758 | { |
1488fc08 | 3759 | struct drm_i915_gem_object *obj = to_intel_bo(gem_obj); |
05394f39 | 3760 | struct drm_device *dev = obj->base.dev; |
be72615b | 3761 | drm_i915_private_t *dev_priv = dev->dev_private; |
673a394b | 3762 | |
26e12f89 CW |
3763 | trace_i915_gem_object_destroy(obj); |
3764 | ||
1488fc08 CW |
3765 | if (obj->phys_obj) |
3766 | i915_gem_detach_phys_object(dev, obj); | |
3767 | ||
3768 | obj->pin_count = 0; | |
3769 | if (WARN_ON(i915_gem_object_unbind(obj) == -ERESTARTSYS)) { | |
3770 | bool was_interruptible; | |
3771 | ||
3772 | was_interruptible = dev_priv->mm.interruptible; | |
3773 | dev_priv->mm.interruptible = false; | |
3774 | ||
3775 | WARN_ON(i915_gem_object_unbind(obj)); | |
3776 | ||
3777 | dev_priv->mm.interruptible = was_interruptible; | |
3778 | } | |
3779 | ||
a5570178 | 3780 | obj->pages_pin_count = 0; |
37e680a1 | 3781 | i915_gem_object_put_pages(obj); |
d8cb5086 | 3782 | i915_gem_object_free_mmap_offset(obj); |
0104fdbb | 3783 | i915_gem_object_release_stolen(obj); |
de151cf6 | 3784 | |
9da3da66 CW |
3785 | BUG_ON(obj->pages); |
3786 | ||
2f745ad3 CW |
3787 | if (obj->base.import_attach) |
3788 | drm_prime_gem_destroy(&obj->base, NULL); | |
de151cf6 | 3789 | |
05394f39 CW |
3790 | drm_gem_object_release(&obj->base); |
3791 | i915_gem_info_remove_obj(dev_priv, obj->base.size); | |
c397b908 | 3792 | |
05394f39 | 3793 | kfree(obj->bit_17); |
42dcedd4 | 3794 | i915_gem_object_free(obj); |
673a394b EA |
3795 | } |
3796 | ||
29105ccc CW |
3797 | int |
3798 | i915_gem_idle(struct drm_device *dev) | |
3799 | { | |
3800 | drm_i915_private_t *dev_priv = dev->dev_private; | |
3801 | int ret; | |
28dfe52a | 3802 | |
29105ccc | 3803 | mutex_lock(&dev->struct_mutex); |
1c5d22f7 | 3804 | |
87acb0a5 | 3805 | if (dev_priv->mm.suspended) { |
29105ccc CW |
3806 | mutex_unlock(&dev->struct_mutex); |
3807 | return 0; | |
28dfe52a EA |
3808 | } |
3809 | ||
b2da9fe5 | 3810 | ret = i915_gpu_idle(dev); |
6dbe2772 KP |
3811 | if (ret) { |
3812 | mutex_unlock(&dev->struct_mutex); | |
673a394b | 3813 | return ret; |
6dbe2772 | 3814 | } |
b2da9fe5 | 3815 | i915_gem_retire_requests(dev); |
673a394b | 3816 | |
29105ccc | 3817 | /* Under UMS, be paranoid and evict. */ |
a39d7efc | 3818 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) |
6c085a72 | 3819 | i915_gem_evict_everything(dev); |
29105ccc | 3820 | |
312817a3 CW |
3821 | i915_gem_reset_fences(dev); |
3822 | ||
29105ccc CW |
3823 | /* Hack! Don't let anybody do execbuf while we don't control the chip. |
3824 | * We need to replace this with a semaphore, or something. | |
3825 | * And not confound mm.suspended! | |
3826 | */ | |
3827 | dev_priv->mm.suspended = 1; | |
bc0c7f14 | 3828 | del_timer_sync(&dev_priv->hangcheck_timer); |
29105ccc CW |
3829 | |
3830 | i915_kernel_lost_context(dev); | |
6dbe2772 | 3831 | i915_gem_cleanup_ringbuffer(dev); |
29105ccc | 3832 | |
6dbe2772 KP |
3833 | mutex_unlock(&dev->struct_mutex); |
3834 | ||
29105ccc CW |
3835 | /* Cancel the retire work handler, which should be idle now. */ |
3836 | cancel_delayed_work_sync(&dev_priv->mm.retire_work); | |
3837 | ||
673a394b EA |
3838 | return 0; |
3839 | } | |
3840 | ||
b9524a1e BW |
3841 | void i915_gem_l3_remap(struct drm_device *dev) |
3842 | { | |
3843 | drm_i915_private_t *dev_priv = dev->dev_private; | |
3844 | u32 misccpctl; | |
3845 | int i; | |
3846 | ||
3847 | if (!IS_IVYBRIDGE(dev)) | |
3848 | return; | |
3849 | ||
a4da4fa4 | 3850 | if (!dev_priv->l3_parity.remap_info) |
b9524a1e BW |
3851 | return; |
3852 | ||
3853 | misccpctl = I915_READ(GEN7_MISCCPCTL); | |
3854 | I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE); | |
3855 | POSTING_READ(GEN7_MISCCPCTL); | |
3856 | ||
3857 | for (i = 0; i < GEN7_L3LOG_SIZE; i += 4) { | |
3858 | u32 remap = I915_READ(GEN7_L3LOG_BASE + i); | |
a4da4fa4 | 3859 | if (remap && remap != dev_priv->l3_parity.remap_info[i/4]) |
b9524a1e BW |
3860 | DRM_DEBUG("0x%x was already programmed to %x\n", |
3861 | GEN7_L3LOG_BASE + i, remap); | |
a4da4fa4 | 3862 | if (remap && !dev_priv->l3_parity.remap_info[i/4]) |
b9524a1e | 3863 | DRM_DEBUG_DRIVER("Clearing remapped register\n"); |
a4da4fa4 | 3864 | I915_WRITE(GEN7_L3LOG_BASE + i, dev_priv->l3_parity.remap_info[i/4]); |
b9524a1e BW |
3865 | } |
3866 | ||
3867 | /* Make sure all the writes land before disabling dop clock gating */ | |
3868 | POSTING_READ(GEN7_L3LOG_BASE); | |
3869 | ||
3870 | I915_WRITE(GEN7_MISCCPCTL, misccpctl); | |
3871 | } | |
3872 | ||
f691e2f4 DV |
3873 | void i915_gem_init_swizzling(struct drm_device *dev) |
3874 | { | |
3875 | drm_i915_private_t *dev_priv = dev->dev_private; | |
3876 | ||
11782b02 | 3877 | if (INTEL_INFO(dev)->gen < 5 || |
f691e2f4 DV |
3878 | dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_NONE) |
3879 | return; | |
3880 | ||
3881 | I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) | | |
3882 | DISP_TILE_SURFACE_SWIZZLING); | |
3883 | ||
11782b02 DV |
3884 | if (IS_GEN5(dev)) |
3885 | return; | |
3886 | ||
f691e2f4 DV |
3887 | I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_SWZCTL); |
3888 | if (IS_GEN6(dev)) | |
6b26c86d | 3889 | I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB)); |
f691e2f4 | 3890 | else |
6b26c86d | 3891 | I915_WRITE(ARB_MODE, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB)); |
f691e2f4 | 3892 | } |
e21af88d | 3893 | |
67b1b571 CW |
3894 | static bool |
3895 | intel_enable_blt(struct drm_device *dev) | |
3896 | { | |
3897 | if (!HAS_BLT(dev)) | |
3898 | return false; | |
3899 | ||
3900 | /* The blitter was dysfunctional on early prototypes */ | |
3901 | if (IS_GEN6(dev) && dev->pdev->revision < 8) { | |
3902 | DRM_INFO("BLT not supported on this pre-production hardware;" | |
3903 | " graphics performance will be degraded.\n"); | |
3904 | return false; | |
3905 | } | |
3906 | ||
3907 | return true; | |
3908 | } | |
3909 | ||
8187a2b7 | 3910 | int |
f691e2f4 | 3911 | i915_gem_init_hw(struct drm_device *dev) |
8187a2b7 ZN |
3912 | { |
3913 | drm_i915_private_t *dev_priv = dev->dev_private; | |
3914 | int ret; | |
68f95ba9 | 3915 | |
e76e9aeb | 3916 | if (INTEL_INFO(dev)->gen < 6 && !intel_enable_gtt()) |
8ecd1a66 DV |
3917 | return -EIO; |
3918 | ||
eda2d7f5 RV |
3919 | if (IS_HASWELL(dev) && (I915_READ(0x120010) == 1)) |
3920 | I915_WRITE(0x9008, I915_READ(0x9008) | 0xf0000); | |
3921 | ||
b9524a1e BW |
3922 | i915_gem_l3_remap(dev); |
3923 | ||
f691e2f4 DV |
3924 | i915_gem_init_swizzling(dev); |
3925 | ||
5c1143bb | 3926 | ret = intel_init_render_ring_buffer(dev); |
68f95ba9 | 3927 | if (ret) |
b6913e4b | 3928 | return ret; |
68f95ba9 CW |
3929 | |
3930 | if (HAS_BSD(dev)) { | |
5c1143bb | 3931 | ret = intel_init_bsd_ring_buffer(dev); |
68f95ba9 CW |
3932 | if (ret) |
3933 | goto cleanup_render_ring; | |
d1b851fc | 3934 | } |
68f95ba9 | 3935 | |
67b1b571 | 3936 | if (intel_enable_blt(dev)) { |
549f7365 CW |
3937 | ret = intel_init_blt_ring_buffer(dev); |
3938 | if (ret) | |
3939 | goto cleanup_bsd_ring; | |
3940 | } | |
3941 | ||
6f392d54 CW |
3942 | dev_priv->next_seqno = 1; |
3943 | ||
254f965c BW |
3944 | /* |
3945 | * XXX: There was some w/a described somewhere suggesting loading | |
3946 | * contexts before PPGTT. | |
3947 | */ | |
3948 | i915_gem_context_init(dev); | |
e21af88d DV |
3949 | i915_gem_init_ppgtt(dev); |
3950 | ||
68f95ba9 CW |
3951 | return 0; |
3952 | ||
549f7365 | 3953 | cleanup_bsd_ring: |
1ec14ad3 | 3954 | intel_cleanup_ring_buffer(&dev_priv->ring[VCS]); |
68f95ba9 | 3955 | cleanup_render_ring: |
1ec14ad3 | 3956 | intel_cleanup_ring_buffer(&dev_priv->ring[RCS]); |
8187a2b7 ZN |
3957 | return ret; |
3958 | } | |
3959 | ||
1070a42b CW |
3960 | static bool |
3961 | intel_enable_ppgtt(struct drm_device *dev) | |
3962 | { | |
3963 | if (i915_enable_ppgtt >= 0) | |
3964 | return i915_enable_ppgtt; | |
3965 | ||
3966 | #ifdef CONFIG_INTEL_IOMMU | |
3967 | /* Disable ppgtt on SNB if VT-d is on. */ | |
3968 | if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped) | |
3969 | return false; | |
3970 | #endif | |
3971 | ||
3972 | return true; | |
3973 | } | |
3974 | ||
3975 | int i915_gem_init(struct drm_device *dev) | |
3976 | { | |
3977 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3978 | unsigned long gtt_size, mappable_size; | |
3979 | int ret; | |
3980 | ||
3981 | gtt_size = dev_priv->mm.gtt->gtt_total_entries << PAGE_SHIFT; | |
3982 | mappable_size = dev_priv->mm.gtt->gtt_mappable_entries << PAGE_SHIFT; | |
3983 | ||
3984 | mutex_lock(&dev->struct_mutex); | |
3985 | if (intel_enable_ppgtt(dev) && HAS_ALIASING_PPGTT(dev)) { | |
3986 | /* PPGTT pdes are stolen from global gtt ptes, so shrink the | |
3987 | * aperture accordingly when using aliasing ppgtt. */ | |
3988 | gtt_size -= I915_PPGTT_PD_ENTRIES*PAGE_SIZE; | |
3989 | ||
3990 | i915_gem_init_global_gtt(dev, 0, mappable_size, gtt_size); | |
3991 | ||
3992 | ret = i915_gem_init_aliasing_ppgtt(dev); | |
3993 | if (ret) { | |
3994 | mutex_unlock(&dev->struct_mutex); | |
3995 | return ret; | |
3996 | } | |
3997 | } else { | |
3998 | /* Let GEM Manage all of the aperture. | |
3999 | * | |
4000 | * However, leave one page at the end still bound to the scratch | |
4001 | * page. There are a number of places where the hardware | |
4002 | * apparently prefetches past the end of the object, and we've | |
4003 | * seen multiple hangs with the GPU head pointer stuck in a | |
4004 | * batchbuffer bound at the last page of the aperture. One page | |
4005 | * should be enough to keep any prefetching inside of the | |
4006 | * aperture. | |
4007 | */ | |
4008 | i915_gem_init_global_gtt(dev, 0, mappable_size, | |
4009 | gtt_size); | |
4010 | } | |
4011 | ||
4012 | ret = i915_gem_init_hw(dev); | |
4013 | mutex_unlock(&dev->struct_mutex); | |
4014 | if (ret) { | |
4015 | i915_gem_cleanup_aliasing_ppgtt(dev); | |
4016 | return ret; | |
4017 | } | |
4018 | ||
53ca26ca DV |
4019 | /* Allow hardware batchbuffers unless told otherwise, but not for KMS. */ |
4020 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) | |
4021 | dev_priv->dri1.allow_batchbuffer = 1; | |
1070a42b CW |
4022 | return 0; |
4023 | } | |
4024 | ||
8187a2b7 ZN |
4025 | void |
4026 | i915_gem_cleanup_ringbuffer(struct drm_device *dev) | |
4027 | { | |
4028 | drm_i915_private_t *dev_priv = dev->dev_private; | |
b4519513 | 4029 | struct intel_ring_buffer *ring; |
1ec14ad3 | 4030 | int i; |
8187a2b7 | 4031 | |
b4519513 CW |
4032 | for_each_ring(ring, dev_priv, i) |
4033 | intel_cleanup_ring_buffer(ring); | |
8187a2b7 ZN |
4034 | } |
4035 | ||
673a394b EA |
4036 | int |
4037 | i915_gem_entervt_ioctl(struct drm_device *dev, void *data, | |
4038 | struct drm_file *file_priv) | |
4039 | { | |
4040 | drm_i915_private_t *dev_priv = dev->dev_private; | |
b4519513 | 4041 | int ret; |
673a394b | 4042 | |
79e53945 JB |
4043 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
4044 | return 0; | |
4045 | ||
ba1234d1 | 4046 | if (atomic_read(&dev_priv->mm.wedged)) { |
673a394b | 4047 | DRM_ERROR("Reenabling wedged hardware, good luck\n"); |
ba1234d1 | 4048 | atomic_set(&dev_priv->mm.wedged, 0); |
673a394b EA |
4049 | } |
4050 | ||
673a394b | 4051 | mutex_lock(&dev->struct_mutex); |
9bb2d6f9 EA |
4052 | dev_priv->mm.suspended = 0; |
4053 | ||
f691e2f4 | 4054 | ret = i915_gem_init_hw(dev); |
d816f6ac WF |
4055 | if (ret != 0) { |
4056 | mutex_unlock(&dev->struct_mutex); | |
9bb2d6f9 | 4057 | return ret; |
d816f6ac | 4058 | } |
9bb2d6f9 | 4059 | |
69dc4987 | 4060 | BUG_ON(!list_empty(&dev_priv->mm.active_list)); |
673a394b | 4061 | mutex_unlock(&dev->struct_mutex); |
dbb19d30 | 4062 | |
5f35308b CW |
4063 | ret = drm_irq_install(dev); |
4064 | if (ret) | |
4065 | goto cleanup_ringbuffer; | |
dbb19d30 | 4066 | |
673a394b | 4067 | return 0; |
5f35308b CW |
4068 | |
4069 | cleanup_ringbuffer: | |
4070 | mutex_lock(&dev->struct_mutex); | |
4071 | i915_gem_cleanup_ringbuffer(dev); | |
4072 | dev_priv->mm.suspended = 1; | |
4073 | mutex_unlock(&dev->struct_mutex); | |
4074 | ||
4075 | return ret; | |
673a394b EA |
4076 | } |
4077 | ||
4078 | int | |
4079 | i915_gem_leavevt_ioctl(struct drm_device *dev, void *data, | |
4080 | struct drm_file *file_priv) | |
4081 | { | |
79e53945 JB |
4082 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
4083 | return 0; | |
4084 | ||
dbb19d30 | 4085 | drm_irq_uninstall(dev); |
e6890f6f | 4086 | return i915_gem_idle(dev); |
673a394b EA |
4087 | } |
4088 | ||
4089 | void | |
4090 | i915_gem_lastclose(struct drm_device *dev) | |
4091 | { | |
4092 | int ret; | |
673a394b | 4093 | |
e806b495 EA |
4094 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
4095 | return; | |
4096 | ||
6dbe2772 KP |
4097 | ret = i915_gem_idle(dev); |
4098 | if (ret) | |
4099 | DRM_ERROR("failed to idle hardware: %d\n", ret); | |
673a394b EA |
4100 | } |
4101 | ||
64193406 CW |
4102 | static void |
4103 | init_ring_lists(struct intel_ring_buffer *ring) | |
4104 | { | |
4105 | INIT_LIST_HEAD(&ring->active_list); | |
4106 | INIT_LIST_HEAD(&ring->request_list); | |
64193406 CW |
4107 | } |
4108 | ||
673a394b EA |
4109 | void |
4110 | i915_gem_load(struct drm_device *dev) | |
4111 | { | |
4112 | drm_i915_private_t *dev_priv = dev->dev_private; | |
42dcedd4 CW |
4113 | int i; |
4114 | ||
4115 | dev_priv->slab = | |
4116 | kmem_cache_create("i915_gem_object", | |
4117 | sizeof(struct drm_i915_gem_object), 0, | |
4118 | SLAB_HWCACHE_ALIGN, | |
4119 | NULL); | |
673a394b | 4120 | |
69dc4987 | 4121 | INIT_LIST_HEAD(&dev_priv->mm.active_list); |
673a394b | 4122 | INIT_LIST_HEAD(&dev_priv->mm.inactive_list); |
6c085a72 CW |
4123 | INIT_LIST_HEAD(&dev_priv->mm.unbound_list); |
4124 | INIT_LIST_HEAD(&dev_priv->mm.bound_list); | |
a09ba7fa | 4125 | INIT_LIST_HEAD(&dev_priv->mm.fence_list); |
1ec14ad3 CW |
4126 | for (i = 0; i < I915_NUM_RINGS; i++) |
4127 | init_ring_lists(&dev_priv->ring[i]); | |
4b9de737 | 4128 | for (i = 0; i < I915_MAX_NUM_FENCES; i++) |
007cc8ac | 4129 | INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list); |
673a394b EA |
4130 | INIT_DELAYED_WORK(&dev_priv->mm.retire_work, |
4131 | i915_gem_retire_work_handler); | |
30dbf0c0 | 4132 | init_completion(&dev_priv->error_completion); |
31169714 | 4133 | |
94400120 DA |
4134 | /* On GEN3 we really need to make sure the ARB C3 LP bit is set */ |
4135 | if (IS_GEN3(dev)) { | |
50743298 DV |
4136 | I915_WRITE(MI_ARB_STATE, |
4137 | _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE)); | |
94400120 DA |
4138 | } |
4139 | ||
72bfa19c CW |
4140 | dev_priv->relative_constants_mode = I915_EXEC_CONSTANTS_REL_GENERAL; |
4141 | ||
de151cf6 | 4142 | /* Old X drivers will take 0-2 for front, back, depth buffers */ |
b397c836 EA |
4143 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) |
4144 | dev_priv->fence_reg_start = 3; | |
de151cf6 | 4145 | |
a6c45cf0 | 4146 | if (INTEL_INFO(dev)->gen >= 4 || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) |
de151cf6 JB |
4147 | dev_priv->num_fence_regs = 16; |
4148 | else | |
4149 | dev_priv->num_fence_regs = 8; | |
4150 | ||
b5aa8a0f | 4151 | /* Initialize fence registers to zero */ |
ada726c7 | 4152 | i915_gem_reset_fences(dev); |
10ed13e4 | 4153 | |
673a394b | 4154 | i915_gem_detect_bit_6_swizzle(dev); |
6b95a207 | 4155 | init_waitqueue_head(&dev_priv->pending_flip_queue); |
17250b71 | 4156 | |
ce453d81 CW |
4157 | dev_priv->mm.interruptible = true; |
4158 | ||
17250b71 CW |
4159 | dev_priv->mm.inactive_shrinker.shrink = i915_gem_inactive_shrink; |
4160 | dev_priv->mm.inactive_shrinker.seeks = DEFAULT_SEEKS; | |
4161 | register_shrinker(&dev_priv->mm.inactive_shrinker); | |
673a394b | 4162 | } |
71acb5eb DA |
4163 | |
4164 | /* | |
4165 | * Create a physically contiguous memory object for this object | |
4166 | * e.g. for cursor + overlay regs | |
4167 | */ | |
995b6762 CW |
4168 | static int i915_gem_init_phys_object(struct drm_device *dev, |
4169 | int id, int size, int align) | |
71acb5eb DA |
4170 | { |
4171 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4172 | struct drm_i915_gem_phys_object *phys_obj; | |
4173 | int ret; | |
4174 | ||
4175 | if (dev_priv->mm.phys_objs[id - 1] || !size) | |
4176 | return 0; | |
4177 | ||
9a298b2a | 4178 | phys_obj = kzalloc(sizeof(struct drm_i915_gem_phys_object), GFP_KERNEL); |
71acb5eb DA |
4179 | if (!phys_obj) |
4180 | return -ENOMEM; | |
4181 | ||
4182 | phys_obj->id = id; | |
4183 | ||
6eeefaf3 | 4184 | phys_obj->handle = drm_pci_alloc(dev, size, align); |
71acb5eb DA |
4185 | if (!phys_obj->handle) { |
4186 | ret = -ENOMEM; | |
4187 | goto kfree_obj; | |
4188 | } | |
4189 | #ifdef CONFIG_X86 | |
4190 | set_memory_wc((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE); | |
4191 | #endif | |
4192 | ||
4193 | dev_priv->mm.phys_objs[id - 1] = phys_obj; | |
4194 | ||
4195 | return 0; | |
4196 | kfree_obj: | |
9a298b2a | 4197 | kfree(phys_obj); |
71acb5eb DA |
4198 | return ret; |
4199 | } | |
4200 | ||
995b6762 | 4201 | static void i915_gem_free_phys_object(struct drm_device *dev, int id) |
71acb5eb DA |
4202 | { |
4203 | drm_i915_private_t *dev_priv = dev->dev_private; | |
4204 | struct drm_i915_gem_phys_object *phys_obj; | |
4205 | ||
4206 | if (!dev_priv->mm.phys_objs[id - 1]) | |
4207 | return; | |
4208 | ||
4209 | phys_obj = dev_priv->mm.phys_objs[id - 1]; | |
4210 | if (phys_obj->cur_obj) { | |
4211 | i915_gem_detach_phys_object(dev, phys_obj->cur_obj); | |
4212 | } | |
4213 | ||
4214 | #ifdef CONFIG_X86 | |
4215 | set_memory_wb((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE); | |
4216 | #endif | |
4217 | drm_pci_free(dev, phys_obj->handle); | |
4218 | kfree(phys_obj); | |
4219 | dev_priv->mm.phys_objs[id - 1] = NULL; | |
4220 | } | |
4221 | ||
4222 | void i915_gem_free_all_phys_object(struct drm_device *dev) | |
4223 | { | |
4224 | int i; | |
4225 | ||
260883c8 | 4226 | for (i = I915_GEM_PHYS_CURSOR_0; i <= I915_MAX_PHYS_OBJECT; i++) |
71acb5eb DA |
4227 | i915_gem_free_phys_object(dev, i); |
4228 | } | |
4229 | ||
4230 | void i915_gem_detach_phys_object(struct drm_device *dev, | |
05394f39 | 4231 | struct drm_i915_gem_object *obj) |
71acb5eb | 4232 | { |
05394f39 | 4233 | struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping; |
e5281ccd | 4234 | char *vaddr; |
71acb5eb | 4235 | int i; |
71acb5eb DA |
4236 | int page_count; |
4237 | ||
05394f39 | 4238 | if (!obj->phys_obj) |
71acb5eb | 4239 | return; |
05394f39 | 4240 | vaddr = obj->phys_obj->handle->vaddr; |
71acb5eb | 4241 | |
05394f39 | 4242 | page_count = obj->base.size / PAGE_SIZE; |
71acb5eb | 4243 | for (i = 0; i < page_count; i++) { |
5949eac4 | 4244 | struct page *page = shmem_read_mapping_page(mapping, i); |
e5281ccd CW |
4245 | if (!IS_ERR(page)) { |
4246 | char *dst = kmap_atomic(page); | |
4247 | memcpy(dst, vaddr + i*PAGE_SIZE, PAGE_SIZE); | |
4248 | kunmap_atomic(dst); | |
4249 | ||
4250 | drm_clflush_pages(&page, 1); | |
4251 | ||
4252 | set_page_dirty(page); | |
4253 | mark_page_accessed(page); | |
4254 | page_cache_release(page); | |
4255 | } | |
71acb5eb | 4256 | } |
e76e9aeb | 4257 | i915_gem_chipset_flush(dev); |
d78b47b9 | 4258 | |
05394f39 CW |
4259 | obj->phys_obj->cur_obj = NULL; |
4260 | obj->phys_obj = NULL; | |
71acb5eb DA |
4261 | } |
4262 | ||
4263 | int | |
4264 | i915_gem_attach_phys_object(struct drm_device *dev, | |
05394f39 | 4265 | struct drm_i915_gem_object *obj, |
6eeefaf3 CW |
4266 | int id, |
4267 | int align) | |
71acb5eb | 4268 | { |
05394f39 | 4269 | struct address_space *mapping = obj->base.filp->f_path.dentry->d_inode->i_mapping; |
71acb5eb | 4270 | drm_i915_private_t *dev_priv = dev->dev_private; |
71acb5eb DA |
4271 | int ret = 0; |
4272 | int page_count; | |
4273 | int i; | |
4274 | ||
4275 | if (id > I915_MAX_PHYS_OBJECT) | |
4276 | return -EINVAL; | |
4277 | ||
05394f39 CW |
4278 | if (obj->phys_obj) { |
4279 | if (obj->phys_obj->id == id) | |
71acb5eb DA |
4280 | return 0; |
4281 | i915_gem_detach_phys_object(dev, obj); | |
4282 | } | |
4283 | ||
71acb5eb DA |
4284 | /* create a new object */ |
4285 | if (!dev_priv->mm.phys_objs[id - 1]) { | |
4286 | ret = i915_gem_init_phys_object(dev, id, | |
05394f39 | 4287 | obj->base.size, align); |
71acb5eb | 4288 | if (ret) { |
05394f39 CW |
4289 | DRM_ERROR("failed to init phys object %d size: %zu\n", |
4290 | id, obj->base.size); | |
e5281ccd | 4291 | return ret; |
71acb5eb DA |
4292 | } |
4293 | } | |
4294 | ||
4295 | /* bind to the object */ | |
05394f39 CW |
4296 | obj->phys_obj = dev_priv->mm.phys_objs[id - 1]; |
4297 | obj->phys_obj->cur_obj = obj; | |
71acb5eb | 4298 | |
05394f39 | 4299 | page_count = obj->base.size / PAGE_SIZE; |
71acb5eb DA |
4300 | |
4301 | for (i = 0; i < page_count; i++) { | |
e5281ccd CW |
4302 | struct page *page; |
4303 | char *dst, *src; | |
4304 | ||
5949eac4 | 4305 | page = shmem_read_mapping_page(mapping, i); |
e5281ccd CW |
4306 | if (IS_ERR(page)) |
4307 | return PTR_ERR(page); | |
71acb5eb | 4308 | |
ff75b9bc | 4309 | src = kmap_atomic(page); |
05394f39 | 4310 | dst = obj->phys_obj->handle->vaddr + (i * PAGE_SIZE); |
71acb5eb | 4311 | memcpy(dst, src, PAGE_SIZE); |
3e4d3af5 | 4312 | kunmap_atomic(src); |
71acb5eb | 4313 | |
e5281ccd CW |
4314 | mark_page_accessed(page); |
4315 | page_cache_release(page); | |
4316 | } | |
d78b47b9 | 4317 | |
71acb5eb | 4318 | return 0; |
71acb5eb DA |
4319 | } |
4320 | ||
4321 | static int | |
05394f39 CW |
4322 | i915_gem_phys_pwrite(struct drm_device *dev, |
4323 | struct drm_i915_gem_object *obj, | |
71acb5eb DA |
4324 | struct drm_i915_gem_pwrite *args, |
4325 | struct drm_file *file_priv) | |
4326 | { | |
05394f39 | 4327 | void *vaddr = obj->phys_obj->handle->vaddr + args->offset; |
b47b30cc | 4328 | char __user *user_data = (char __user *) (uintptr_t) args->data_ptr; |
71acb5eb | 4329 | |
b47b30cc CW |
4330 | if (__copy_from_user_inatomic_nocache(vaddr, user_data, args->size)) { |
4331 | unsigned long unwritten; | |
4332 | ||
4333 | /* The physical object once assigned is fixed for the lifetime | |
4334 | * of the obj, so we can safely drop the lock and continue | |
4335 | * to access vaddr. | |
4336 | */ | |
4337 | mutex_unlock(&dev->struct_mutex); | |
4338 | unwritten = copy_from_user(vaddr, user_data, args->size); | |
4339 | mutex_lock(&dev->struct_mutex); | |
4340 | if (unwritten) | |
4341 | return -EFAULT; | |
4342 | } | |
71acb5eb | 4343 | |
e76e9aeb | 4344 | i915_gem_chipset_flush(dev); |
71acb5eb DA |
4345 | return 0; |
4346 | } | |
b962442e | 4347 | |
f787a5f5 | 4348 | void i915_gem_release(struct drm_device *dev, struct drm_file *file) |
b962442e | 4349 | { |
f787a5f5 | 4350 | struct drm_i915_file_private *file_priv = file->driver_priv; |
b962442e EA |
4351 | |
4352 | /* Clean up our request list when the client is going away, so that | |
4353 | * later retire_requests won't dereference our soon-to-be-gone | |
4354 | * file_priv. | |
4355 | */ | |
1c25595f | 4356 | spin_lock(&file_priv->mm.lock); |
f787a5f5 CW |
4357 | while (!list_empty(&file_priv->mm.request_list)) { |
4358 | struct drm_i915_gem_request *request; | |
4359 | ||
4360 | request = list_first_entry(&file_priv->mm.request_list, | |
4361 | struct drm_i915_gem_request, | |
4362 | client_list); | |
4363 | list_del(&request->client_list); | |
4364 | request->file_priv = NULL; | |
4365 | } | |
1c25595f | 4366 | spin_unlock(&file_priv->mm.lock); |
b962442e | 4367 | } |
31169714 | 4368 | |
5774506f CW |
4369 | static bool mutex_is_locked_by(struct mutex *mutex, struct task_struct *task) |
4370 | { | |
4371 | if (!mutex_is_locked(mutex)) | |
4372 | return false; | |
4373 | ||
4374 | #if defined(CONFIG_SMP) || defined(CONFIG_DEBUG_MUTEXES) | |
4375 | return mutex->owner == task; | |
4376 | #else | |
4377 | /* Since UP may be pre-empted, we cannot assume that we own the lock */ | |
4378 | return false; | |
4379 | #endif | |
4380 | } | |
4381 | ||
31169714 | 4382 | static int |
1495f230 | 4383 | i915_gem_inactive_shrink(struct shrinker *shrinker, struct shrink_control *sc) |
31169714 | 4384 | { |
17250b71 CW |
4385 | struct drm_i915_private *dev_priv = |
4386 | container_of(shrinker, | |
4387 | struct drm_i915_private, | |
4388 | mm.inactive_shrinker); | |
4389 | struct drm_device *dev = dev_priv->dev; | |
6c085a72 | 4390 | struct drm_i915_gem_object *obj; |
1495f230 | 4391 | int nr_to_scan = sc->nr_to_scan; |
5774506f | 4392 | bool unlock = true; |
17250b71 CW |
4393 | int cnt; |
4394 | ||
5774506f CW |
4395 | if (!mutex_trylock(&dev->struct_mutex)) { |
4396 | if (!mutex_is_locked_by(&dev->struct_mutex, current)) | |
4397 | return 0; | |
4398 | ||
4399 | unlock = false; | |
4400 | } | |
31169714 | 4401 | |
6c085a72 CW |
4402 | if (nr_to_scan) { |
4403 | nr_to_scan -= i915_gem_purge(dev_priv, nr_to_scan); | |
4404 | if (nr_to_scan > 0) | |
4405 | i915_gem_shrink_all(dev_priv); | |
31169714 CW |
4406 | } |
4407 | ||
17250b71 | 4408 | cnt = 0; |
6c085a72 | 4409 | list_for_each_entry(obj, &dev_priv->mm.unbound_list, gtt_list) |
a5570178 CW |
4410 | if (obj->pages_pin_count == 0) |
4411 | cnt += obj->base.size >> PAGE_SHIFT; | |
6c085a72 | 4412 | list_for_each_entry(obj, &dev_priv->mm.bound_list, gtt_list) |
a5570178 | 4413 | if (obj->pin_count == 0 && obj->pages_pin_count == 0) |
6c085a72 | 4414 | cnt += obj->base.size >> PAGE_SHIFT; |
17250b71 | 4415 | |
5774506f CW |
4416 | if (unlock) |
4417 | mutex_unlock(&dev->struct_mutex); | |
6c085a72 | 4418 | return cnt; |
31169714 | 4419 | } |